delete irrelevant configs

880 files changed, 0 insertions, 404976 deletions

diff --git a/gcc/config/1750a/1750a.c b/gcc/config/1750a/1750a.c
deleted file mode 100755
index 134f69d..0000000
--- a/gcc/config/1750a/1750a.c
+++ /dev/null
@@ -1,734 +0,0 @@
-/* Subroutines for insn-output.c for MIL-STD-1750.
-   Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
-   Contributed by O.M.Kellogg, DASA (kellogg@space.otn.dasa.de)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define __datalbl
-#include "config.h"
-#include <stdio.h>
-#include <string.h>
-#include "rtl.h"
-#include "tree.h"
-#include "expr.h"
-#define HAVE_cc0
-#include "conditions.h"
-#include "real.h"
-#include "regs.h"
-
-struct datalabel_array datalbl[DATALBL_ARRSIZ];
-int datalbl_ndx = -1;
-struct jumplabel_array jmplbl[JMPLBL_ARRSIZ];
-int jmplbl_ndx = -1;
-int label_pending = 0, program_counter = 0;
-enum section current_section = Normal;
-char *sectname[4] =
-{"Init", "Normal", "Konst", "Static"};
-
-int
-notice_update_cc (exp)
-     rtx exp;
-{
-  if (GET_CODE (exp) == SET)
-    {
-      enum rtx_code src_code = GET_CODE (SET_SRC (exp));
-      /* Jumps do not alter the cc's.  */
-      if (SET_DEST (exp) == pc_rtx)
-	return;
-      /* Moving a register or constant into memory doesn't alter the cc's. */
-      if (GET_CODE (SET_DEST (exp)) == MEM
-	  && (src_code == REG || src_code == CONST_INT))
-	return;
-      /* Function calls clobber the cc's.  */
-      if (src_code == CALL)
-	{
-	  CC_STATUS_INIT;
-	  return;
-	}
-      /* Emulated longword bit-ops leave cc's incorrect */
-      if (GET_MODE (SET_DEST (exp)) == HImode ?
-	       src_code == AND || src_code == IOR ||
-	       src_code == XOR || src_code == NOT : 0)
-	{
-	  CC_STATUS_INIT;
-	  return;
-	}
-      /* Tests and compares set the cc's in predictable ways.  */
-      if (SET_DEST (exp) == cc0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  cc_status.value1 = SET_SRC (exp);
-	  return;
-	}
-      /* Anything else will set cc_status. */
-      cc_status.flags = CC_NO_OVERFLOW;
-      cc_status.value1 = SET_SRC (exp);
-      cc_status.value2 = SET_DEST (exp);
-      return;
-    }
-  else if (GET_CODE (exp) == PARALLEL
-	   && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
-    {
-      if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
-	return;
-      if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
-	  return;
-	}
-      CC_STATUS_INIT;
-    }
-  else
-    {
-      CC_STATUS_INIT;
-    }
-}
-
-
-rtx
-function_arg (cum, mode, type, named)
-     int cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int size;
-
-  if (MUST_PASS_IN_STACK (mode, type))
-    return (rtx) 0;
-  if (mode == BLKmode)
-    size = int_size_in_bytes (type);
-  else
-    size = GET_MODE_SIZE (mode);
-  if (cum + size < 12)
-    return gen_rtx (REG, mode, cum);
-  else
-    return (rtx) 0;
-}
-
-
-double
-get_double (x)
-     rtx x;
-{
-  union
-    {
-      double d;
-      long i[2];
-    }
-  du;
-
-  du.i[0] = CONST_DOUBLE_LOW (x);
-  du.i[1] = CONST_DOUBLE_HIGH (x);
-  return du.d;
-}
-
-char *
-float_label (code, value)
-     char code;
-     double value;
-{
-  int i = 1;
-  static char label[32];
-  char *p;
-
-  label[0] = code;
-  p = label + 1;
-  sprintf (p, "%lf", value);
-  while (*p)
-    {
-      *p = (*p == '+') ? 'p' :
-	(*p == '-') ? 'm' : *p;
-      p++;
-    }
-  return xstrdup (label);
-}
-
-
-char *
-movcnt_regno_adjust (op)
-     rtx *op;
-{
-  static char outstr[80];
-  int op0r = REGNO (op[0]), op1r = REGNO (op[1]), op2r = REGNO (op[2]);
-#define dstreg op0r
-#define srcreg op1r
-#define cntreg op2r
-#define cntreg_1750 (op0r + 1)
-
-  if (cntreg == cntreg_1750)
-    sprintf (outstr, "mov r%d,r%d", op0r, op1r);
-  else if (dstreg + 1 == srcreg && cntreg > srcreg)
-    sprintf (outstr, "xwr r%d,r%d\n\tmov r%d,r%d", op2r, op1r, op0r, op2r);
-  else if (dstreg == cntreg + 1)
-    sprintf (outstr, "xwr r%d,r%d\n\tmov r%d,r%d", op0r, op2r, op2r, op1r);
-  else if (dstreg == srcreg + 1)
-    sprintf (outstr, "xwr r%d,r%d\n\txwr r%d,r%d\n\tmov r%d,r%d",
-	     op0r, op1r, op0r, op2r, op1r, op2r);
-  else if (cntreg + 1 == srcreg)
-    sprintf (outstr, "xwr r%d,r%d\n\txwr r%d,r%d\n\tmov r%d,r%d",
-	     op2r, op1r, op0r, op2r, op2r, op0r);
-  else if (cntreg == srcreg + 1)
-    sprintf (outstr, "xwr r%d,r%d\n\tmov r%d,r%d", op0r, op1r, op1r, op0r);
-  else
-    sprintf (outstr, "xwr r%d,r%d\n\tmov r%d,r%d\n\txwr r%d,r%d",
-	     op2r, cntreg_1750, op0r, op1r, op2r, cntreg_1750);
-  return outstr;
-}
-
-char *
-mod_regno_adjust (instr, op)
-     char *instr;
-     rtx *op;
-{
-  static char outstr[40];
-  char *r = (!strncmp (instr, "dvr", 3) ? "r" : "");
-  int modregno_gcc = REGNO (op[3]), modregno_1750 = REGNO (op[0]) + 1;
-
-  if (modregno_gcc == modregno_1750
-      || (reg_renumber != NULL
-	  && reg_renumber[modregno_gcc] >= 0
-	  && reg_renumber[modregno_gcc] == reg_renumber[modregno_1750]))
-    sprintf (outstr, "%s r%%0,%s%%2", instr, r);
-  else
-    sprintf (outstr, "lr r%d,r%d\n\t%s r%%0,%s%%2\n\txwr r%d,r%d",
-	     modregno_gcc, modregno_1750, instr, r, modregno_1750,
-	     modregno_gcc);
-  return outstr;
-}
-
-
-/* Check if op is a valid memory operand for 1750A Load/Store instructions
-   (memory indirection permitted.)  */
-
-int
-memop_valid (op)
-     rtx op;
-{
-  static int recurred = 0;
-  int valid;
-
-  if (GET_MODE (op) != Pmode && GET_MODE (op) != VOIDmode
-      && GET_MODE (op) != QImode)
-    return 0;
-  switch (GET_CODE (op))
-    {
-    case MEM:
-      if (!recurred && GET_CODE (XEXP (op, 0)) == REG)
-	return 1;
-    case MINUS:
-    case MULT:
-    case DIV:
-      return 0;
-    case PLUS:
-      recurred = 1;
-      valid = memop_valid (XEXP (op, 0));
-      if (valid)
-	valid = memop_valid (XEXP (op, 1));
-       recurred = 0;
-       return valid;
-    case REG:
-      if (REGNO (op) > 0)
-	return 1;
-      return 0;
-    case CONST:
-    case CONST_INT:
-    case SYMBOL_REF:
-    case SUBREG:
-      return 1;
-    default:
-      printf ("memop_valid: code=%d\n", (int) GET_CODE (op));
-      return 1;
-    }
-}
-
-
-/* predicate for the MOV instruction: */
-int
-mov_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG);
-}
-
-/* predicate for the STC instruction: */
-int
-small_nonneg_const (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) <= 15)
-    return 1;
-  return 0;
-}
-
-/* predicate for constant zero: */
-int
-zero_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return op == CONST0_RTX (mode);
-}
-
-
-/* predicate for 1750 `B' addressing mode (Base Register with Offset)
-   memory operand */
-int
-b_mode_operand (op)
-     rtx op;
-{
-  if (GET_CODE (op) == MEM)
-    {
-      rtx inner = XEXP (op, 0);
-      if (GET_CODE (inner) == REG && REG_OK_FOR_INDEX_P (inner))
-	return 1;
-      if (GET_CODE (inner) == PLUS)
-	{
-	  rtx plus_op0 = XEXP (inner, 0);
-	  if (GET_CODE (plus_op0) == REG && REG_OK_FOR_INDEX_P (plus_op0))
-	    {
-	      rtx plus_op1 = XEXP (inner, 1);
-	      if (GET_CODE (plus_op1) == CONST_INT
-		  && INTVAL (plus_op1) >= 0
-		  && INTVAL (plus_op1) <= 255)
-		return 1;
-	    }
-	}
-    }
-  return 0;
-}
-
-
-/* Decide whether to output a conditional jump as a "Jump Conditional"
-   or as a "Branch Conditional": */
-
-int
-find_jmplbl (labelnum)
-     int labelnum;
-{
-  int i, found = 0;
-
-  for (i = 0; i <= jmplbl_ndx; i++)
-    if (labelnum == jmplbl[i].num)
-      {
-	found = 1;
-	break;
-      }
-  if (found)
-    return i;
-  return -1;
-}
-
-char *
-branch_or_jump (condition, targetlabel_number)
-     char *condition;
-     int targetlabel_number;
-{
-  static char buf[30];
-  int index;
-
-  if ((index = find_jmplbl (targetlabel_number)) >= 0)
-    if (program_counter - jmplbl[index].pc < 128)
-      {
-	sprintf (buf, "b%s %%l0", condition);
-	return buf;
-      }
-  sprintf (buf, "jc %s,%%l0", condition);
-  return buf;
-}
-
-
-int
-unsigned_comparison_operator (insn)
-     rtx insn;
-{
-  switch (GET_CODE (insn))
-    {
-    case GEU:
-    case GTU:
-    case LEU:
-    case LTU:
-      return 1;
-    default:
-      return 0;
-    }
-}
-
-int
-next_cc_user_is_unsigned (insn)
-     rtx insn;
-{
-  if ( !(insn = next_cc0_user (insn)))
-    abort ();
-  else if (GET_CODE (insn) == JUMP_INSN
-	   && GET_CODE (PATTERN (insn)) == SET
-	   && GET_CODE (SET_SRC (PATTERN (insn))) == IF_THEN_ELSE)
-    return unsigned_comparison_operator (XEXP (SET_SRC (PATTERN (insn)), 0));
-  else if (GET_CODE (insn) == INSN
-	   && GET_CODE (PATTERN (insn)) == SET)
-    return unsigned_comparison_operator (SET_SRC (PATTERN (insn)));
-  else
-    abort ();
-}
-
-
-static int addr_inc;
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand X.  X is an RTL
-   expression.
-
-   CODE is a value that can be used to specify one of several ways
-   of printing the operand.  It is used when identical operands
-   must be printed differently depending on the context.  CODE
-   comes from the `%' specification that was used to request
-   printing of the operand.  If the specification was just `%DIGIT'
-   then CODE is 0; if the specification was `%LTR DIGIT' then CODE
-   is the ASCII code for LTR.
-
-   If X is a register, this macro should print the register's name.
-   The names can be found in an array `reg_names' whose type is
-   `char *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
-
-   When the machine description has a specification `%PUNCT' (a `%'
-   followed by a punctuation character), this macro is called with
-   a null pointer for X and the punctuation character for CODE.
-
-   The 1750 specific codes are:
-   'J' for the negative of a constant
-   'Q' for printing addresses in B mode syntax
-   'd' for the second register in a pair
-   't' for the third register in a triple 
-   'b' for the bit number (using 1750 test bit convention)
-   'B' for the bit number of the 1's complement (for bit clear)
-   'w' for int - 16
-*/
-
-print_operand (file, x, letter)
-     FILE *file;
-     rtx x;
-     int letter;
-{
-  switch (GET_CODE (x))
-    {
-    case REG:
-      if (letter == 'd')
-	fprintf (file, "%d", REGNO (x) + 1);
-      else if (letter == 't')
-	fprintf (file, "%d", REGNO (x) + 2);
-      else
-	fprintf (file, "%d", REGNO (x));
-      break;
-
-    case SYMBOL_REF:
-      fprintf (file, "%s", XSTR (x, 0));
-      if (letter == 'A')
-	fprintf (file, "+1");
-      break;
-
-    case LABEL_REF:
-    case CONST:
-    case MEM:
-      if (letter == 'Q')
-	{
-	  rtx inner = XEXP (x, 0);
-	  switch (GET_CODE (inner))
-	    {
-	    case REG:
-	      fprintf (file, "r%d,0", REGNO (inner));
-	      break;
-	    case PLUS:
-	      fprintf (file, "r%d,%d", REGNO (XEXP (inner, 0)),
-		       INTVAL (XEXP (inner, 1)));
-	      break;
-	    default:
-	      fprintf (file, "[ill Q code=%d]", GET_CODE (inner));
-	    }
-	}
-      else
-	{
-	  addr_inc = (letter == 'A' ? 1 : 0);
-	  output_address (XEXP (x, 0));
-	}
-      break;
-
-    case CONST_DOUBLE:
-/*    {
-	double value = get_double (x);
-	char fltstr[32];
-	sprintf (fltstr, "%lf", value);
-
-	if (letter == 'D' || letter == 'E')
-	  {
-	    int i, found = 0;
-	    for (i = 0; i <= datalbl_ndx; i++)
-	      if (strcmp (fltstr, datalbl[i].value) == 0)
-		{
-		  found = 1;
-		  break;
-		}
-	    if (!found)
-	      {
-		strcpy (datalbl[i = ++datalbl_ndx].value, fltstr);
-		datalbl[i].name = float_label (letter, value);
-		datalbl[i].size = (letter == 'E') ? 3 : 2;
-		check_section (Konst);
-		fprintf (file, "K%s \tdata%s %s ;p_o\n", datalbl[i].name,
-			(letter == 'E' ? "ef" : "f"), fltstr);
-		check_section (Normal);
-	      }
-	  }
-	else if (letter == 'F' || letter == 'G')
-	  {
-	    int i, found = 0;
-	    for (i = 0; i <= datalbl_ndx; i++)
-	      if (strcmp (fltstr, datalbl[i].value) == 0)
-		{
-		  found = 1;
-		  break;
-		}
-	    if (!found)
-	      {
-		fprintf (stderr,
-		   "float value %lfnot found upon label reference\n", value);
-		strcpy (datalbl[i = ++datalbl_ndx].value, fltstr);
-		datalbl[i].name = float_label (letter, value);
-		datalbl[i].size = (letter == 'G') ? 3 : 2;
-		check_section (Konst);
-		fprintf (file, "K%s \tdata%s %s ;p_o\n", datalbl[i].name,
-			(letter == 'G' ? "ef" : "f"), fltstr);
-		check_section (Normal);
-	      }
-	    fprintf (file, "%s ;P_O 'F'", datalbl[i].name);
-	  }
-	else
-	  fprintf (file, " %s  ;P_O cst_dbl ", fltstr);
-      }
- */
-      fprintf (file, "%lf", get_double (x));
-      break;
-
-    case CONST_INT:
-      if (letter == 'J')
-	fprintf (file, "%d", -INTVAL (x));
-      else if (letter == 'b')
-        fprintf (file, "%d", which_bit (INTVAL (x)));
-      else if (letter == 'B')
-        fprintf (file, "%d", which_bit (~INTVAL (x)));
-      else if (letter == 'w')
-	fprintf (file, "%d", INTVAL (x) - 16);
-      else
-	fprintf (file, "%d", INTVAL (x));
-      break;
-
-    case CODE_LABEL:
-      fprintf (file, "L%d", XINT (x, 3));
-      break;
-
-    case CALL:
-      fprintf (file, "CALL nargs=%d, func is either '%s' or '%s'",
-       XEXP (x, 1), XSTR (XEXP (XEXP (x, 0), 1), 0), XSTR (XEXP (x, 0), 1));
-      break;
-
-    case PLUS:
-      {
-	rtx op0 = XEXP (x, 0), op1 = XEXP (x, 1);
-	int op0code = GET_CODE (op0), op1code = GET_CODE (op1);
-	if (op1code == CONST_INT)
-	  switch (op0code)
-	    {
-	    case REG:
-	      fprintf (file, "%d,r%d  ; p_o_PLUS for REG and CONST_INT",
-		       INTVAL (op1), REGNO (op0));
-	      break;
-	    case SYMBOL_REF:
-	      fprintf (file, "%d+%s", INTVAL (op1), XSTR (op0, 0));
-	      break;
-	    case MEM:
-	      fprintf (file, "%d,[mem:", INTVAL (op1));
-	      output_address (XEXP (op0, 0));
-	      fprintf (file, "] ;P_O plus");
-	      break;
-	    default:
-	      fprintf (file, "p_o_PLUS UFO, code=%d, with CONST=%d",
-		       (int) op0code, INTVAL (op1));
-	    }
-	else if (op1code == SYMBOL_REF && op0code == REG)
-	  fprintf (file, "%s,r%d  ; P_O: (plus reg sym)",
-		   XSTR (op1, 0), REGNO (op0));
-	else
-	  fprintf (file, "p_o_+: op0code=%d, op1code=%d", op0code, op1code);
-      }
-      break;
-
-    default:
-      fprintf (file, "p_o_UFO code=%d", GET_CODE (x));
-    }
-
-  addr_inc = 0;
-}
-
-print_operand_address (file, addr)
-     FILE *file;
-     rtx addr;
-{
-  switch (GET_CODE (addr))
-    {
-    case REG:
-      fprintf (file, "%d,r%d ; P_O_A", addr_inc, REGNO (addr));
-      break;
-    case PLUS:
-      {
-	register rtx x = XEXP (addr, 0), y = XEXP (addr, 1);
-	switch (GET_CODE (x))
-	  {
-	  case REG:
-	    switch (GET_CODE (y))
-	      {
-	      case CONST:
-		output_address (XEXP (y, 0));
-		fprintf (file, ",r%d ;P_O_A reg + const expr", REGNO (x));
-		break;
-	      case CONST_INT:
-		fprintf (file, "%d,r%d", INTVAL (y) + addr_inc, REGNO (x));
-		break;
-	      case SYMBOL_REF:
-		fprintf (file, "%s", XSTR (y, 0));
-		if (addr_inc)
-		  fprintf (file, "+%d", addr_inc);
-		fprintf (file, ",r%d  ; P_O_A reg + sym", REGNO (x));
-		break;
-	      case LABEL_REF:
-		output_address (XEXP (y, 0));
-		fprintf (file, ",r%d  ; P_O_A reg + label", REGNO (x));
-		break;
-	      default:
-		fprintf (file, "[P_O_A reg%d+UFO code=%d]",
-			 REGNO (x), GET_CODE (y));
-	      }
-	    break;
-	  case LABEL_REF:
-	    output_address (XEXP (x, 0));
-	    break;
-	  case SYMBOL_REF:
-	    switch (GET_CODE (y))
-	      {
-	      case CONST_INT:
-		fprintf (file, "%d+%s", INTVAL (y) + addr_inc, XSTR (x, 0));
-		break;
-	      case REG:
-		fprintf (file, "%s,r%d ;P_O_A sym + reg",
-			 XSTR (x, 0), REGNO (y));
-		break;
-	      default:
-		fprintf (file, "P_O_A sym/lab+UFO[sym=%s,code(y)=%d]",
-			 XSTR (x, 0), GET_CODE (y));
-	      }
-	    break;
-	  case CONST:
-	    output_address (XEXP (x, 0));
-	    if (GET_CODE (y) == REG)
-	      fprintf (file, ",r%d ;P_O_A const + reg", REGNO (x));
-	    else
-	      fprintf (file, "P_O_A const+UFO code(y)=%d]", GET_CODE (y));
-	    break;
-	  case MEM:
-	    output_address (y);
-	    fprintf (file, ",[mem:");
-	    output_address (XEXP (x, 0));
-	    fprintf (file, "] ;P_O_A plus");
-	    break;
-	  default:
-	    fprintf (file, "P_O_A plus op1_UFO[code1=%d,code2=%d]",
-		     GET_CODE (x), GET_CODE (y));
-	  }
-      }
-      break;
-    case CONST_INT:
-      if (INTVAL (addr) < 0x10000 && INTVAL (addr) >= -0x10000)
-	fprintf (file, "%d ; p_o_a const addr?!", INTVAL (addr));
-      else
-	{
-	  fprintf (file, "[p_o_a=ILLEGAL_CONST]");
-	  output_addr_const (file, addr);
-	}
-      break;
-    case LABEL_REF:
-    case SYMBOL_REF:
-      fprintf (file, "%s", XSTR (addr, 0));
-      if (addr_inc)
-	fprintf (file, "+%d", addr_inc);
-      break;
-    case MEM:
-      fprintf (file, "[memUFO:");
-      output_address (XEXP (addr, 0));
-      fprintf (file, "]");
-      break;
-    case CONST:
-      output_address (XEXP (addr, 0));
-      fprintf (file, " ;P_O_A const");
-      break;
-    case CODE_LABEL:
-      fprintf (file, "L%d", XINT (addr, 3));
-      break;
-    default:
-      fprintf (file, " p_o_a UFO, code=%d val=0x%x",
-	       (int) GET_CODE (addr), INTVAL (addr));
-      break;
-    }
-  addr_inc = 0;
-}
-
-
-/*
- *  Return non zero if the LS 16 bits of the given value has just one bit set,
- *  otherwise return zero. Note this function may be used to detect one
- *  bit clear by inverting the param.
- */
-int
-one_bit_set_p (x)
-     int x;
-{
-  x &= 0xffff; 
-  return x && (x & (x - 1)) == 0;
-}
-
-
-/*
- * Return the number of the least significant bit set, using the  same
- * convention for bit numbering as in the MIL-STD-1750 sb instruction.
- */
-int
-which_bit (x)
-     int x;
-{
-  int b = 15;
-
-  while (b > 0 && (x & 1) == 0)
-    {
-      b--;
-      x >>= 1;
-    }
-
-  return b;
-}
-
-
diff --git a/gcc/config/1750a/1750a.h b/gcc/config/1750a/1750a.h
deleted file mode 100755
index 5d3b2a0..0000000
--- a/gcc/config/1750a/1750a.h
+++ /dev/null
@@ -1,1348 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by O.M.Kellogg, DASA (oliver.kellogg@space.otn.dasa.de)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-/* See tm-sun3.h, tm-sun2.h, tm-isi68.h for different CPP_PREDEFINES.  */
-#define CPP_PREDEFINES ""
-
-/* Print subsidiary information on the compiler version in use.  */
-#ifdef IEEE
-#define TARGET_VERSION fprintf (stderr, " (1750A, IEEE syntax)");
-#else
-#define TARGET_VERSION fprintf (stderr, " (MIL-STD-1750A)");
-#endif
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-#define TARGET_SWITCHES  \
-  { {"vaxc-alignment", 2}, \
-    { "", TARGET_DEFAULT}}
-
-/* Default target_flags if no switches specified.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 1
-#endif
-
-/*****************************************************************************/
-
-/* SPECIAL ADDITION FOR MIL-STD-1750A     by O.M.Kellogg, 15-Apr-1993 */
-/* See file aux-output.c for the actual data instances. */
-struct datalabel_array {
-    char *name;
-    char value[14];
-    int size;
-};
-struct jumplabel_array {
-    int pc;
-    int num;
-};
-enum section { Init, Normal, Konst, Static };
-#define DATALBL_ARRSIZ 256
-#define JMPLBL_ARRSIZ  256
-#ifndef __datalbl
-extern struct datalabel_array datalbl[];
-extern struct jumplabel_array jmplbl[];
-extern int datalbl_ndx, jmplbl_ndx, label_pending, program_counter;
-extern enum section current_section;
-extern char *sectname[4];
-extern char *float_label();
-extern struct rtx_def *function_arg ();
-extern char *movcnt_regno_adjust ();
-extern char *mod_regno_adjust ();
-extern char *branch_or_jump ();
-#endif
-/*--------------------------------------------------------------------*/
-
-/* target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   Though 1750 actually counts bits in big-endian fashion, the sign bit
-   is still the most significant bit, which is leftmost. Therefore leaving
-   this little-endian. Adjust short before assembler output when needed:
-   e.g. in QImode, a GCC bit n is a 1750 bit (15-n). */
-#define BITS_BIG_ENDIAN 0 
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* For 1750 we can decide arbitrarily
-   since there are no machine instructions for them.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword value is lowest
-   numbered.
-   True for 1750. */
-#define WORDS_BIG_ENDIAN 1
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT        16
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD        16
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD       1
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE         16
-
-#define PTRDIFF_TYPE        "int"
-
-/* Type to use for `size_t'. If undefined, uses `long unsigned int'. */
-#define SIZE_TYPE           "int"
-
-/* 1750a preliminary
-   #define TARGET_FLOAT_FORMAT UNKNOWN_FLOAT_FORMAT
-*/
-
-/* Allocation boundary (in *bits*) for storing pointers in memory.  */
-#define POINTER_BOUNDARY     16
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-/* 1750: should have had to make this 32 when BITS_PER_WORD is 32. */
-#define PARM_BOUNDARY        16
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY       16
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY    16
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT    16
-
-/* Define this to 1 if move instructions will actually fail to work
-   when given unaligned data. */
-#define STRICT_ALIGNMENT 0
-
-/* Define number of bits in most basic integer type.
-   (If undefined, default is BITS_PER_WORD).
-   #define INT_TYPE_SIZE  16  */
-
-/* Define number of bits in short integer type.
-   (If undefined, default is half of BITS_PER_WORD). */
-#define SHORT_TYPE_SIZE 16
-
-/* Define number of bits in long integer type.
-   (If undefined, default is BITS_PER_WORD). */
-#define LONG_TYPE_SIZE  32
-
-/* Define number of bits in long long integer type.
-   (If undefined, default is twice BITS_PER_WORD). */
-/* 1750 PRELIMINARY : no processor support for `long long', therefore
-        need to check out the long-long opencodings ! */
-#define LONG_LONG_TYPE_SIZE  64
-
-/* Define number of bits in char type.
-   (If undefined, default is one fourth of BITS_PER_WORD). */
-#define CHAR_TYPE_SIZE  16
-
-/* Define number of bits in float type.
-   (If undefined, default is BITS_PER_WORD). */
-#define FLOAT_TYPE_SIZE  32
-
-/* Define number of bits in double type.
-   (If undefined, default is twice BITS_PER_WORD). */
-#define DOUBLE_TYPE_SIZE  48
-
-/*****************************************************************************/
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers. */
-#define FIRST_PSEUDO_REGISTER 16
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   R15 is the 1750A stack pointer. R14 is the frame pointer. */
-
-#define FIXED_REGISTERS  \
- { 0, 0, 0, 0, 0, 0, 0, 0, \
-   0, 0, 0, 0, 0, 0, 1, 1 }
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.
-   1750: return value in R0 foll. (depending on size of retval).
-   Should be possible to refine this (how many regs are actually used) */
-
-#define CALL_USED_REGISTERS \
- { 1, 1, 1, 1, 1, 1, 1, 1, \
-   1, 1, 1, 1, 1, 1, 1, 1 }
-
-/* Order in which to allocate registers.  Each register must be
-   listed once, even those in FIXED_REGISTERS.  List frame pointer
-   late and fixed registers last.  Note that, in general, we prefer
-   registers listed in CALL_USED_REGISTERS, keeping the others
-   available for storage of persistent values.  */
-
-/* #define REG_ALLOC_ORDER \
-   { 2, 0, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }
- */
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-   All 1750 registers are one word long. */
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output. */
-#define MODES_TIEABLE_P(MODE1, MODE2)	1
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* 1750A pc isn't overloaded on a register.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 15
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 14
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c. */
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 14
-
-/* Define this if successive args to a function occupy decreasing addresses
-   on the stack. 
-   #define ARGS_GROW_DOWNWARD
-*/
-
-/* Register in which static-chain is passed to a function. */
-#define STATIC_CHAIN_REGNUM 13
-
-/* Place in which caller passes the structure value address.
-   0 means push the value on the stack like an argument. 
-   #define STRUCT_VALUE 0
-*/
-
-/* Register in which address to store a structure value
-   arrives in the function.  
-   #define STRUCT_VALUE_INCOMING 0
-*/
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 12
-
-/* Define this to be 1 if all structure return values must be in memory. */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/*****************************************************************************/
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-/* 1750 note: The names (BASE_REGS/INDEX_REGS) are used in their *gcc sense*
-   (i.e. *opposite* to the MIL-STD-1750A defined meanings). This means that
-   R1..R15 are called "base" regs and R12..R15 are "index" regs.
-   Index reg mode (in the gcc sense) is not yet implemented (these are the
-   1750 "Base with Index Reg" instructions, LBX etc. See 1750.md)
-
-   Here's an example to drive this point home: in "LBX B12,R5"
-   B12 shall be called the "index" reg and R5 shall be the "base" reg.
-   This naming inversion is due to the GCC defined capabilities of
-   "Base" vs. "Index" regs. */
-
-enum reg_class { NO_REGS, R2, R0_1, INDEX_REGS, BASE_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Since GENERAL_REGS is the same class as ALL_REGS,
-   don't give it a different class number; just make it an alias. */
-#define GENERAL_REGS ALL_REGS
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- { "NO_REGS", "R2", "R0_1", "INDEX_REGS", "BASE_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.
-   1750 "index" (remember, in the *GCC* sense!) regs are R12 through R15. 
-   The only 1750 register not usable as BASE_REG is R0. */
-
-#define REG_CLASS_CONTENTS  {0, 0x0004, 0x0003, 0xf000, 0xfffe, 0xffff}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-#define REGNO_REG_CLASS(REGNO) ((REGNO) == 2 ? R2 : (REGNO) == 0 ? R0_1 : \
-  (REGNO) >= 12 ? INDEX_REGS : (REGNO) >  0 ? BASE_REGS : ALL_REGS)
-
-/* The class value for index registers, and the one for base regs. */
-
-#define BASE_REG_CLASS  BASE_REGS
-#define INDEX_REG_CLASS INDEX_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.
-   For the 1750, we have 'z' for R0_1, 't' for R2, 'b' for gcc Base regs 
-   and 'x' for gcc Index regs. */
-
-#define REG_CLASS_FROM_LETTER(C) ((C) == 't' ? R2 : \
-				  (C) == 'z' ? R0_1 : \
-				  (C) == 'b' ? BASE_REGS : \
-				  (C) == 'x' ? INDEX_REGS : NO_REGS)
-
-/* The letters I,J,K,.. to P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   For the 1750A, 
-   `I' is used for ISP mode instructions,
-   `J' is used for ISN mode instructions,
-   `K' is used for the STC instruction's constant range,
-   `L' is used for unsigned 8-bit address displacements in instructions
-       of addressing mode "Base Relative",
-   `M' is for IM mode instructions et al.,
-   `O' is a synonym for (const_int 0). */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)				\
-  ((C) == 'I' ? (VALUE) > 0 && (VALUE) <=  16 :			\
-   (C) == 'J' ? (VALUE) < 0 && (VALUE) >= -16 :			\
-   (C) == 'K' ? (VALUE) >= 0 && (VALUE) <= 15 :			\
-   (C) == 'L' ? (VALUE) >= 0 && (VALUE) <= 0xFF :		\
-   (C) == 'M' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : 	\
-   (C) == 'O' ? (VALUE) == 0 :				0)
-
-/* Similar, but for floating constants, and defining letter 'G'.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'G' ? ((VALUE) == CONST0_RTX (HFmode)         \
-                 || (VALUE) == CONST0_RTX (TQFmode)) : 0)
-
-/* Optional extra constraints for this machine.
-
-   For the 1750, `Q' means that this is a memory operand consisting
-   of the sum of an Index Register (in the GCC sense, i.e. R12..R15)
-   and a constant in the range 0..255. This constraint is used for
-   the Base Register with Offset address mode instructions (LB,STB,AB,..)  */
-
-#define EXTRA_CONSTRAINT(OP, C)				\
-  ((C) == 'Q' && b_mode_operand (OP))
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)  CLASS
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.
-   On the 1750A, this is the size of MODE in words,
-   since class doesn't make any difference. */
-#define CLASS_MAX_NREGS(CLASS,MODE)  GET_MODE_SIZE(MODE)
-
-/*****************************************************************************/
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD 1
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   goes at a more negative offset in the frame. 
-   #define FRAME_GROWS_DOWNWARD
-*/
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.
-*/
-#define STARTING_FRAME_OFFSET 1
-
-/* This is the default anyway:
-   #define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) FRAMEADDR
-*/
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   1750 note: what GCC calls a "byte" is really a 16-bit word,
-   because BITS_PER_UNIT is 16. */
-
-#define PUSH_ROUNDING(BYTES) (BYTES)
-
-/* Define this macro if functions should assume that stack space has
-   been allocated for arguments even when their values are passed in
-   registers.
-   Size, in bytes, of the area reserved for arguments passed in
-   registers for the function represented by FNDECL. 
-   #define REG_PARM_STACK_SPACE(FNDECL) 14 */
-
-/* Define this if it is the responsibility of the caller to allocate
-   the area reserved for arguments passed in registers. 
-   #define OUTGOING_REG_PARM_STACK_SPACE */
-
-/* Offset of first parameter from the argument pointer register value.
-   1750 note:
-   Parameters appear in reversed order on the frame (so when they are
-   popped, they come off in the normal left-to-right order.)
-   Computed as follows:
-   one word for the caller's (PC+1) (i.e. the return address)
-   plus total size of called function's "auto" variables
-   plus one word for the caller's frame pointer (i.e. the old FP) */
-
-#define FIRST_PARM_OFFSET(FNDECL) \
-   (1 + get_frame_size() + 1)
-
-/* Value is 1 if returning from a function call automatically
-   pops the arguments described by the number-of-args field in the call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-*/
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0. */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx(REG,TYPE_MODE(VALTYPE),0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE. */
-/* 1750 note: no libcalls yet */
-
-#define LIBCALL_VALUE(MODE)  printf("LIBCALL_VALUE called!\n"), \
-  gen_rtx(REG,MODE,0)
-
-/* 1 if N is a possible register number for a function value. */
-
-#define FUNCTION_VALUE_REGNO_P(N)  ((N) == 0)
-
-/* 1 if the tree TYPE should be returned in memory instead of in regs. 
-   #define RETURN_IN_MEMORY(TYPE) \
-   (int_size_in_bytes(TYPE) > 12)
-*/
-
-/* Define this if PCC uses the nonreentrant convention for returning
-   structure and union values. 
-   #define PCC_STATIC_STRUCT_RETURN  */
-
-/* 1 if N is a possible register number for function argument passing. */
-
-#define FUNCTION_ARG_REGNO_P(N)  ((N) < 12)
-
-/*****************************************************************************/
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   For 1750A, this is a single integer, which is a number of words
-   of arguments scanned so far.  */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   For 1750A, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)   ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)
-
-   1750 note: "int_size_in_bytes()" returns a unit relative to
-   BITS_PER_UNIT, so in our case not bytes, but 16-bit words.  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM) += (MODE) == BLKmode ? int_size_in_bytes(TYPE) : GET_MODE_SIZE(MODE))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) function_arg (CUM,MODE,TYPE,NAMED)
-
-/* Define the following macro if function calls on the target machine
-   do not preserve any registers; in other words, if `CALL_USED_REGISTERS'
-   has 1 for all registers. This macro enables `-fcaller-saves' by
-   default. Eventually that option will be enabled by default on all
-   machines and both the option and this macro will be eliminated. */
-
-#define DEFAULT_CALLER_SAVES
-
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) {   \
-  if (flag_verbose_asm)						\
-    {								\
-      int regno, regs_used = 0;					\
-      fprintf (FILE, "\t; registers used: ");			\
-      for (regno = 0; regno < 14; regno++)			\
-	if (regs_ever_live[regno])				\
-	  {							\
-	    fprintf (FILE, " %s", reg_names[regno]);		\
-	    regs_used++;					\
-	  }							\
-      if (regs_used == 0)					\
-	fprintf (FILE, "(none)");			 	\
-    }								\
-  if (SIZE > 0)							\
-    {								\
-      fprintf (FILE, "\n\t%s\tr15,%d",				\
-	       (SIZE <= 16 ? "sisp" : "sim"), SIZE);		\
-      if (flag_verbose_asm)					\
-	fprintf (FILE, "  ; reserve local-variable space");	\
-    }								\
-  if (frame_pointer_needed)					\
-    {								\
-      fprintf(FILE, "\n\tpshm\tr14,r14");			\
-      if (flag_verbose_asm)					\
-	fprintf (FILE, "  ; push old frame");			\
-      fprintf (FILE, "\n\tlr\tr14,r15");			\
-      if (flag_verbose_asm)					\
-	fprintf (FILE, "  ; set new frame");			\
-    }								\
-  fprintf (FILE, "\n");					 	\
-  program_counter = 0;						\
-  jmplbl_ndx = -1;						\
-}
-
-/************* 1750: PROFILER HANDLING NOT YET DONE !!!!!!! *************/
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "; got into FUNCTION_PROFILER with label # %d\n", (LABELNO))
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.  */
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "; got into FUNCTION_BLOCK_PROFILER with label # %d\n",LABELNO)
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  */
-#define BLOCK_PROFILER(FILE, BLOCKNO)	\
-  fprintf (FILE, "; got into BLOCK_PROFILER with block # %d\n",BLOCKNO)
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 0
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning. */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) {			\
-  if (frame_pointer_needed)					\
-    {								\
-      fprintf (FILE, "\tlr\tr15,r14");				\
-      if (flag_verbose_asm)					\
-        fprintf (FILE, "  ; set stack ptr to frame ptr");	\
-      fprintf (FILE, "\n\tpopm\tr14,r14");			\
-      if (flag_verbose_asm)					\
-        fprintf (FILE, "  ; restore previous frame ptr");	\
-      fprintf (FILE, "\n");					\
-    }								\
-  if (SIZE > 0)							\
-    {								\
-      fprintf (FILE, "\t%s\tr15,%d",				\
-	       (SIZE <= 16 ? "aisp" : "aim"), SIZE);		\
-      if (flag_verbose_asm)					\
-	fprintf (FILE, "  ; free up local-var space");		\
-      fprintf (FILE, "\n");					\
-    }								\
-  fprintf (FILE, "\turs\tr15\n\n");				\
-}
-
-/* If the memory address ADDR is relative to the frame pointer,
-   correct it to be relative to the stack pointer instead.
-   This is for when we don't use a frame pointer.
-   ADDR should be a variable name.
-
-   #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH)  
-*/
-
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved.
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) DEPTH = 0
-*/
-
-#define ELIMINABLE_REGS { \
-	{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },  \
-	{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },  \
-	{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM } }
-
-#define CAN_ELIMINATE(FROM, TO)   1
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)   \
-	OFFSET = (TO == STACK_POINTER_REGNUM) ? -1 : 0
-
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  */
-
-#define TRAMPOLINE_TEMPLATE(FILE)  fprintf(FILE,"TRAMPOLINE_TEMPLATE called\n")
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 2
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)  printf("INITIALIZE_TRAMPO called\n")
-/* {									\
-  emit_move_insn (gen_rtx (MEM, QImode, plus_constant (TRAMP, 1)), CXT); \
-  emit_move_insn (gen_rtx (MEM, QImode, plus_constant (TRAMP, 6)), FNADDR); \
-} */
-
-
-/*****************************************************************************/
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* 1750 doesn't have a lot of auto-incr./decr. - just for the stack ptr. */
-
-/* #define HAVE_POST_INCREMENT 0 just for R15 (stack pointer) */
-/* #define HAVE_POST_DECREMENT 0 */
-/* #define HAVE_PRE_DECREMENT 0  just for R15 (stack pointer) */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c. 
-   1750 note: The words BASE and INDEX are used in their GCC senses:
-   The "Index Registers", R12 through R15, are used in the 1750
-   instructions LB,STB,AB,SBB,MB,DB,LBX,STBX,...
-   */
-
-#define REGNO_OK_FOR_BASE_P(REGNO)  \
- ((REGNO) > 0 && (REGNO) <= 15 ||   \
-  reg_renumber[REGNO] > 0 && reg_renumber[REGNO] <= 15)
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
- ((REGNO) >= 12 && (REGNO) <= 15 || \
-  reg_renumber[REGNO] >= 12 && reg_renumber[REGNO] <= 15)
-
-/* Now macros that check whether X is a register and also,
-   strictly, whether it is in a specified class.
-
-/* 1 if X is an address register  */
-
-#define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-#define MAX_REGS_PER_ADDRESS 1
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)  CONSTANT_P(X)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifdef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P(REGNO(X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X)  REGNO_OK_FOR_BASE_P(REGNO(X))
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) (REGNO (X) >= 12)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) (REGNO (X) > 0)
-
-#endif
-
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS.
-
-   1750 note: Currently we don't implement address expressions that use
-   GCC "Index"-class regs. To be expanded to handle the 1750 "Base with Index"
-   instructions (see also MAX_REGS_PER_ADDRESS and others). */
-
-#define GO_IF_BASED_ADDRESS(X, ADDR) {					\
-   if ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P(X)))			\
-     goto ADDR;								\
-   if (GET_CODE (X) == PLUS)						\
-    { register rtx x0 = XEXP(X,0), x1 = XEXP(X,1);			\
-      if ((REG_P(x0) && REG_OK_FOR_BASE_P(x0) && CONSTANT_ADDRESS_P(x1)) \
-       || (REG_P(x1) && REG_OK_FOR_BASE_P(x1) && CONSTANT_ADDRESS_P(x0))) \
-     goto ADDR; } }
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) {			\
-	if (CONSTANT_ADDRESS_P(X)) goto ADDR;				\
-	GO_IF_BASED_ADDRESS(X,ADDR) }
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output. */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the 68000, only predecrement and postincrement address depend thus
-   (the amount of decrement or increment being the length of the operand).  */
-/* 1750: not used. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-/*****************************************************************************/
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE QImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 65536
-
-/* If a memory-to-memory move would take MOVE_RATIO or more simple
-   move-instruction pairs, we will do a movstr or libcall instead.  */
-#define MOVE_RATIO 4
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count. */
-/* #define SHIFT_COUNT_TRUNCATED 1 */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
-/* When a prototype says `char' or `short', really pass an `int'. 
-   1750: for now, `char' is 16 bits wide anyway.
-   #define PROMOTE_PROTOTYPES */
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode QImode
-
-/* A function address in a call instruction
-   is a 16-bit address (for indexing purposes) */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE)  \
-  case CONST_INT:						\
-    return (INTVAL(RTX) >= -16 && INTVAL(RTX) <= 16) ? 1 : 3;	\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 3;							\
-  case CONST_DOUBLE:						\
-    return 4;
-
-#define ADDRESS_COST(ADDRESS)  (memop_valid (ADDRESS) ?  3 : 10)
-
-#define REGISTER_MOVE_COST(FROM,TO)	2
-
-#define MEMORY_MOVE_COST(M,C,I)		4
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  */
-/* MIL-STD-1750: none -- just has the garden variety C,P,Z,N flags. */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.
-   1750: See file out-1750a.c for notice_update_cc().  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP)
-
-/**********************************************/
-/* Produce debugging info in the DWARF format 
-   #define DWARF_DEBUGGING_INFO
-*/
-
-/*****************************************************************************/
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(FILE)   {					\
-   char *p, name[40];							\
-   if ((p = (char *)strrchr(main_input_filename,'/')) != NULL ? 1 :	\
-       (p = (char *)strrchr(main_input_filename,']')) != NULL)		\
-	p++;								\
-   else									\
-	p = main_input_filename;					\
-   strcpy(name,p);							\
-   if (p = (char *)strchr(name,'.'))					\
-	*p = '\0';							\
-   fprintf(FILE,"\tname %s\n",name); 					\
-   fprintf(FILE,"\tnolist\n\tinclude \"ms1750.inc\"\n\tlist\n\n");	\
-   fprintf(FILE,"\tglobal\t__main\n\n");  }
-
-/* Output at end of assembler file.  
-   For 1750, we copy the data labels accrued in datalbl[] from the Constants 
-   section (Konst) to the Writable-Data section (Static).     */
-
-#define ASM_FILE_END(FILE)	\
-   do {									\
-      if (datalbl_ndx >= 0) {						\
-         int i, cum_size=0;						\
-         fprintf(FILE,"\n\tstatic\ninit_srel\n");			\
-         for (i = 0; i <= datalbl_ndx; i++) {				\
-	    if (datalbl[i].name == NULL)				\
-	    {								\
-	       fprintf(stderr, "asm_file_end internal datalbl err\n");	\
-	       exit (0);						\
-	    }								\
-            fprintf(FILE,"%s \tblock %d\n",				\
-                 datalbl[i].name,datalbl[i].size);			\
-            cum_size += datalbl[i].size;				\
-	 }								\
-         fprintf(FILE,"\n\tinit\n");					\
-         fprintf(FILE,"\tlim\tr0,init_srel\n");           /* destin. */	\
-         fprintf(FILE,"\tlim\tr1,%d\n",cum_size);         /* count */	\
-         fprintf(FILE,"\tlim\tr2,K%s\n",datalbl[0].name); /* source */	\
-         fprintf(FILE,"\tmov\tr0,r2\n");				\
-         fprintf(FILE,"\n\tnormal\n");					\
-         datalbl_ndx = -1;			/* reset stuff */	\
-         for (i = 0; i < DATALBL_ARRSIZ; i++)				\
-            datalbl[i].size = 0;					\
-      }									\
-      fprintf(FILE,"\n\tend\n");					\
-   } while (0)
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "; ASM_APP_ON\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "; ASM_APP_OFF\n"
-
-
-#define EXTRA_SECTIONS  in_readonly_data
-
-#define EXTRA_SECTION_FUNCTIONS		\
-    void const_section()					\
-    {								\
-	fprintf(asm_out_file,"\tkonst\n");			\
-	current_section = Konst;				\
-    }								\
-    check_section(sect)						\
-	 enum section sect;					\
-    {								\
-        if (current_section != sect) {				\
-	    fprintf(asm_out_file,"\t%s\n",sectname[(int)sect]); \
-	    current_section = sect;				\
-	}							\
-	switch (sect) {						\
-	  case Init:						\
-	  case Normal:						\
-	    in_section = in_text;				\
-	    break;						\
-	  case Static:						\
-	    in_section = in_data;				\
-	    break;						\
-	  case Konst:						\
-	    in_section = in_readonly_data;			\
-	    break;						\
-	}							\
-    }
-
-		
-/* Function that switches to the read-only data section (optional) */
-#define READONLY_DATA_SECTION	const_section
-
-/* Output before program init section */
-#define INIT_SECTION_ASM_OP "\n\tinit     ; init_section\n"
-
-/* Output before program text section */
-#define TEXT_SECTION_ASM_OP "\n\tnormal   ; text_section\n"
-
-/* Output before writable data.
-   1750 Note: This is actually read-only data. The copying from read-only
-   to writable memory is done elsewhere (in ASM_FILE_END.)
- */
-#define DATA_SECTION_ASM_OP "\n\tkonst    ; data_section\n"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
- { "0", "1", "2", "3", "4", "5", "6", "7", \
-   "8", "9","10","11","12","13","14","15" }
-
-/* How to renumber registers for dbx and gdb. */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/******************  Assembler output formatting  **********************/
-
-#define ASM_IDENTIFY_GCC(FILE)  fputs ("; gcc2_compiled:\n", FILE)
-
-#define ASM_COMMENT_START  ";"
-
-#define ASM_OUTPUT_FUNNAM(FILE,NAME)	\
-	fprintf(FILE,"%s\n",NAME)
-
-#define ASM_OUTPUT_OPCODE(FILE,PTR)  do {		\
-	while (*(PTR) != '\0' && *(PTR) != ' ') {	\
-	    putc (*(PTR), FILE);			\
-	    (PTR)++;					\
-	  }						\
-	while (*(PTR) == ' ')				\
-	    (PTR)++;					\
-	putc ('\t', FILE);				\
-	program_counter += 2;				\
-     } while (0)
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL)	\
-	fprintf(FILE,"%s\n",NAME)
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-/* 1750 note: Labels are prefixed with a 'K'. This is because handling
-   has been changed for labels to be output in the "Constants" section
-   (named "Konst"), and special initialization code takes care of copying
-   the Const-section data into the writable data section (named "Static").
-   In the Static section we therefore have the true label names (i.e.
-   not prefixed with 'K').  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do {  if (NAME[0] == '.') {					\
-	   fprintf(stderr,"Oops! label %s can't begin with '.'\n",NAME); \
-	   abort();						\
-	}							\
-	else {							\
-	   check_section(Konst);				\
-	   fprintf(FILE,"K%s\n",NAME);				\
-	   fflush(FILE);					\
-	   datalbl[++datalbl_ndx].name = (char *)xstrdup (NAME);\
-	   datalbl[datalbl_ndx].size = 0;			\
-	   label_pending = 1;					\
-	}							\
-  } while (0)
-
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME) do {		\
-	   fprintf (FILE, "\tglobal  %s\t; export\n", NAME);	\
-  } while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX ""
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)		\
-	do {							\
-	  if (strcmp(PREFIX,"LC") == 0) {			\
-	     label_pending = 1;					\
-	     datalbl[++datalbl_ndx].name = (char *) malloc (9); \
-	     sprintf(datalbl[datalbl_ndx].name,"LC%d",NUM);	\
-	     datalbl[datalbl_ndx].size = 0;			\
-	     check_section(Konst);				\
-	     fprintf(FILE,"K%s%d\n",PREFIX,NUM);		\
-	  }							\
-	  else if (find_jmplbl(NUM) < 0) {			\
-	     jmplbl[++jmplbl_ndx].num = NUM;			\
-	     jmplbl[jmplbl_ndx].pc = program_counter;		\
-	     fprintf(FILE, "%s%d\n", PREFIX, NUM);		\
-	  }							\
-	  fflush(FILE);						\
-	} while (0)
-
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-	  sprintf (LABEL, "%s%d", PREFIX, NUM)
-
-/* Output at the end of a jump table.
-   1750: To be uncommented when we can put jump tables in Konst.  
-   #define ASM_OUTPUT_CASE_END(FILE,NUM,INSN)      \
-	fprintf (FILE, "\tnormal\t; case_end\n")
- */
-
-/* Currently, it is not possible to put jump tables in section Konst.
-   This is because there is a one-to-one relation between sections Konst
-   and Static (i.e., all Konst data are copied to Static, and the order
-   of data is the same between the two sections.) However, jump tables are
-   not copied to Static, which destroys the equivalence between Konst and
-   Static. When a more intelligent Konst-to-Static copying mechanism is
-   implemented (i.e. one that excludes the copying of jumptables), then
-   ASM_OUTPUT_CASE_END shall be defined, and JUMP_LABELS_IN_TEXT_SECTION
-   shall be undefined.   */
-
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* This is how to output an assembler line defining a 1750A `float'
-   constant.  */
-
-#define ASM_OUTPUT_SHORT_FLOAT(FILE,VALUE) 			\
-  do {								\
-      if (label_pending) {					\
-	 label_pending = 0;					\
-         sprintf (datalbl[datalbl_ndx].value, "%lf", (double) VALUE); \
-      }								\
-      datalbl[datalbl_ndx].size += 2;				\
-      fprintf (FILE, "\tdataf\t%lf\n",VALUE);			\
-  } while(0)
-
-/* This is how to output an assembler line defining a 1750A `double'
-    constant. */
-
-#define ASM_OUTPUT_THREE_QUARTER_FLOAT(FILE,VALUE)		\
-  do {								\
-      if (label_pending) {					\
-	 label_pending = 0;					\
-         sprintf (datalbl[datalbl_ndx].value, "%lf", VALUE);	\
-      }								\
-      datalbl[datalbl_ndx].size += 3;				\
-      fprintf(FILE,"\tdataef\t%lf\n",VALUE);			\
-  } while (0)
-
-/* This is how to output an assembler line defining a string constant.  */
-
-#define ASM_OUTPUT_ASCII(FILE, PTR, LEN)  do {		\
-	int i;								\
-	if (label_pending)						\
-	   label_pending = 0;						\
-	datalbl[datalbl_ndx].size += LEN;				\
-	for (i = 0; i < LEN; i++) {					\
-	  if ((i % 15) == 0) {						\
-	    if (i != 0)							\
-	      fprintf(FILE,"\n");					\
-	    fprintf(FILE,"\tdata\t");					\
-	  }								\
-	  else								\
-	    fprintf(FILE,",");						\
-	  if (PTR[i] >= 32 && PTR[i] < 127)				\
-	    fprintf(FILE,"'%c'",PTR[i]);				\
-	  else								\
-	    fprintf(FILE,"%d",PTR[i]);					\
-	}								\
-	fprintf(FILE,"\n");						\
-  } while (0)
-
-/* This is how to output an assembler line defining a `char', `short', or
-  `int' constant.
-   1750 NOTE: The reason why this macro also outputs `short' and `int'
-   constants is that for the 1750, BITS_PER_UNIT is 16 (as opposed to the
-   usual 8.) This behavior is different from the usual, where
-   ASM_OUTPUT_CHAR only outputs character constants. The name
-   of this macro should perhaps be `ASM_OUTPUT_QUARTER_INT' or so.
- */
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  do {	  \
-	if (label_pending) 						\
-	   label_pending = 0;						\
-	datalbl[datalbl_ndx].size++;					\
-	fprintf(FILE, "\tdata\t");					\
-	output_addr_const(FILE, VALUE); 				\
-	fprintf(FILE, "\n");						\
-  } while (0)
-
-/* This is how to output an assembler line defining a `long int' constant.
-   1750 NOTE: The reason why this macro outputs `long' instead of `short'
-   constants is that for the 1750, BITS_PER_UNIT is 16 (as opposed to the
-   usual 8.) The name of this macro should perhaps be `ASM_OUTPUT_HALF_INT'.
- */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE) do {	  \
-	if (label_pending)						\
-	   label_pending = 0;						\
-	datalbl[datalbl_ndx].size += 2;					\
-	fprintf(FILE, "\tdatal\t%d\n",INTVAL(VALUE));			\
-  } while (0)
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE) do {	  \
-	if (label_pending)						\
-	   label_pending = 0;						\
-	datalbl[datalbl_ndx].size++;					\
-	fprintf(FILE, "\tdata\t#%x\n", VALUE);				\
-  } while (0)
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tPSHM R%s,R%s\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-	fprintf (FILE, "\tPOPM R%s,R%s\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute. */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)   \
-	fprintf (FILE, "\tdata\tL%d ;addr_vec_elt\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-	fprintf (FILE, "\tdata\tL%d-L%d ;addr_diff_elt\n", VALUE,REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
- fprintf(FILE,"; in ASM_OUTPUT_ALIGN: pwr_of_2_bytcnt=%d\n",LOG)
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)	\
-   fprintf(FILE,"; in ASM_OUTPUT_SKIP: size=%d\n",SIZE)
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  do {	\
-	check_section(Static);					  \
-	fprintf (FILE, "\tcommon  %s,%d\n", NAME, SIZE);	  \
-     } while (0)
-
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)  do {		\
-	fprintf (FILE, "\tglobal  %s\t; import\n", NAME);	\
-     }  while (0)
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  do {  \
-	check_section (Static);					\
-	fprintf(FILE,"%s \tblock   %d\t; local common\n",NAME,SIZE);	\
-     } while (0)
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE, NAME)  do {	\
-	fprintf(FILE, "\tinit\n\t"); assemble_name(FILE, NAME); \
-        fprintf(FILE,"  ;constructor\n"); } while (0)
-
-#define ASM_OUTPUT_DESTRUCTOR(FILE, NAME)  do {	\
-	fprintf(FILE, "\tinit\n\t"); assemble_name(FILE, NAME); \
-        fprintf(FILE,"  ;destructor\n"); } while (0)
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL	007
-#define TARGET_BS	010
-#define TARGET_TAB	011
-#define TARGET_NEWLINE	012
-#define TARGET_VT	013
-#define TARGET_FF	014
-#define TARGET_CR	015
-
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.
-   1750 note:  there are three special CODE characters:
-        'D', 'E': print a reference to a floating point constant (D=double,
-		  E=single precision) label name
-	'F': print a label defining a floating-point constant value
-	'J': print the absolute value of a negative INT_CONST
-	     (this is used in LISN/CISN/MISN/SISP and others)
-	'Q': print a 1750 Base-Register-with-offset instruction's operands
- */
-
-/* 1750A: see file aux-output.c */
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand(FILE,X,CODE)
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  print_operand_address(FILE,ADDR)
-
diff --git a/gcc/config/1750a/1750a.md b/gcc/config/1750a/1750a.md
deleted file mode 100755
index cff2d92..0000000
--- a/gcc/config/1750a/1750a.md
+++ /dev/null
@@ -1,1436 +0,0 @@
-;;- Machine description for GNU compiler
-;;- MIL-STD-1750A version.
-;; Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
-;; Contributed by O.M.Kellogg, DASA (oliver.kellogg@space.otn.dasa.de).
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 1, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- instruction definitions
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;;- When naming insn's (operand 0 of define_insn) be careful about using
-;;- names from other targets machine descriptions.
-
-;; MIL-STD-1750 specific remarks:
-;;
-;; 1) BITS_PER_UNIT = 16
-;;
-;; 2) GCC   to    MIL-STD-1750       data type mappings:
-;;    QImode => single integer (16 bits or 1 reg).
-;;    HImode => double integer (32 bits or 2 regs).
-;;    HFmode => single precision float (32 bits or 2 regs).
-;;    TQFmode => extended precision float (48 bits or 3 regs).
-;; 
-;; 3) Immediate integer operands Constraints:
-;;    'I'  1 .. 16
-;;    'J' -1 ..-16
-;;    'K'  0 .. 15
-;;    'L'  0 .. 255
-;;    'M' -32768 .. 32767
-;;    'O' => 0  (for optimizations and GCC quirks)
-;;
-;; Further notes:
-;;-  Assembly output ending in ".M" are macros in file M1750.INC
-
-
-;; stackpush
-(define_insn ""
-  [(set (match_operand:QI 0 "push_operand" "=<")
-        (match_operand:QI 1 "general_operand" "r"))]
-  ""
-  "pshm r%1,r%1")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "push_operand" "=<")
-        (match_operand:HI 1 "general_operand" "r"))]
-  ""
-  "pshm r%1,r%d1")
-
-(define_insn ""
-  [(set (match_operand:HF 0 "push_operand" "=<")
-        (match_operand:HF 1 "general_operand" "r"))]
-  ""
-  "pshm r%1,r%d1")
-
-(define_insn ""
-  [(set (match_operand:TQF 0 "push_operand" "=<")
-        (match_operand:TQF 1 "general_operand" "r"))]
-  ""
-  "pshm r%1,r%t1")
-
-;; stackpop
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=r")
-        (match_operand:QI 1 "push_operand" ">"))]
-  ""
-  "popm r%1,r%1")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=r")
-        (match_operand:HI 1 "push_operand" ">"))]
-  ""
-  "popm r%1,r%d1")
-
-(define_insn ""
-  [(set (match_operand:HF 0 "general_operand" "=r")
-        (match_operand:HF 1 "push_operand" ">"))]
-  ""
-  "popm r%1,r%d1")
-   
-(define_insn ""
-  [(set (match_operand:TQF 0 "general_operand" "=r")
-        (match_operand:TQF 1 "push_operand" ">"))]
-  ""
-  "popm r%1,r%t1")
-
-
-;; Test operations.
-
-(define_insn "tstqi"
-  [(set (cc0)
-        (match_operand:QI 0 "register_operand" "r"))]
-  ""
-  "lr r%0,r%0   ; from tstqi")
-
-(define_insn "tsthi"
-  [(set (cc0)
-        (match_operand:HI 0 "register_operand" "r"))]
-  ""
-  "dlr r%0,r%0   ; from tsthi")
-
-; With 1750A floats, testing the most significant word suffices.
-
-(define_insn "tsthf"
-  [(set (cc0)
-        (match_operand:HF 0 "register_operand" "r"))]
-  ""
-  "lr r%0,r%0   ; tsthf")
-
-(define_insn "tsttqf"
-  [(set (cc0)
-        (match_operand:TQF 0 "register_operand" "r"))]
-  ""
-  "lr r%0,r%0   ; tsttqf")
-
-
-;; block move.
-
-(define_insn "movstrqi"
-  [(set (match_operand:BLK 0 "mov_memory_operand" "m")
-	(match_operand:BLK 1 "mov_memory_operand" "m"))
-   (use (match_operand:QI 2 "general_operand" "r"))
-   (match_operand 3 "" "")
-   (clobber (match_dup 0))
-   (clobber (match_dup 1))
-   (clobber (match_dup 2))]
-  ""
-  "*
-   {
-     rtx regops[3];
-
-     regops[0] = XEXP (operands[0], 0);
-     regops[1] = XEXP (operands[1], 0);
-     regops[2] = operands[2];
-
-     return movcnt_regno_adjust (regops);
-   } ")
-
-
-;; compare instructions.
-
-(define_insn "cmpqi"
-  [(set (cc0)
-        (compare (match_operand:QI 0 "register_operand" "r,r,r,r,r")
-                 (match_operand:QI 1 "general_operand"  "I,J,i,r,m")))]
-  ""
-  "*
-   {
-     if (next_cc_user_is_unsigned (insn))
-       switch (which_alternative)
-	 {
-	 case 0:
-	 case 1:
-	 case 2:
-	   return \"ucim.m %0,%1\";
-	 case 3:
-	   return \"ucr.m %0,%1\";
-	 case 4:
-	   return \"uc.m %0,%1\";
-	 }
-     else
-       switch (which_alternative)
-	 {
-	 case 0:
-	   return \"cisp r%0,%1\";
-	 case 1:
-	   return \"cisn r%0,%J1\";
-	 case 2:
-	   return \"cim  r%0,%1\";
-	 case 3:
-	   return \"cr   r%0,r%1\";
-	 case 4:
-	   return \"c    r%0,%1\";
-	 }
-   } ")
-
-(define_insn "cmphi"
-  [(set (cc0)
-        (compare (match_operand:HI 0 "general_operand" "r,r")
-                 (match_operand:HI 1 "general_operand" "r,m")))]
-  ""
-  "*
-   {
-     if (next_cc_user_is_unsigned (insn))
-       {
-         if (which_alternative == 0)
-	   return \"ducr.m %0,%1\";
-	 return \"duc.m %0,%1\";
-       }
-     else
-       {
-         if (which_alternative == 0)
-           return \"dcr r%0,r%1\";
-         return \"dc  r%0,%1\";
-       }
-   } ")
-
-(define_insn "cmphf"
- [(set (cc0)
-       (compare (match_operand:HF 0 "general_operand" "r,r")
-                (match_operand:HF 1 "general_operand" "r,m")))]
- ""
- "@
-   fcr r%0,r%1
-   fc  r%0,%1 ")
-
-(define_insn "cmptqf"
-  [(set (cc0)
-        (compare (match_operand:TQF 0 "general_operand" "r,r")
-                 (match_operand:TQF 1 "general_operand" "r,m")))]
-  ""
-  "@
-    efcr r%0,r%1
-    efc  r%0,%1 ")
-
-
-;; truncation instructions
-;;- 1750: any needed?
-
-(define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-        (truncate:QI (match_operand:HI 1 "register_operand" "r")))]
-  ""
-  "lr  r%0,r%d1")
-
-
-;; zero extension instructions: not defined, GCC can synthesize
-
-;; sign extension instructions
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-        (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m")) )]
-  ""
-  "*
-    if (which_alternative == 0)
-      {
-        if (REGNO (operands [0]) != REGNO (operands [1]))
-          output_asm_insn (\"lr r%0,r%1\", operands);
-      }
-    else
-      output_asm_insn (\"l  r%0,%1\", operands);
-    return \"dsra r%0,16  ;extendqihi2\";
-  ")
-
-
-;; Conversions between float and double.
-
-; 1750 HF-to-TQF extend: just append 16 bits (least signif.) with all bits zero
-(define_insn "extendhftqf2"
-  [(set (match_operand:TQF 0 "register_operand" "=r,r")
-        (float_extend:TQF (match_operand:HF 1 "general_operand" "r,m")))]
-  ""
-  "*
-    output_asm_insn(\"xorr r%t0,r%t0   ;extendhftqf2\", operands);
-    if (which_alternative == 0)
-      {
-        if (REGNO (operands[1]) != REGNO (operands[0]))
-          return \"dlr r%0,r%1\";
-        else
-          return \";\";
-      }
-    else
-      return \"dl  r%0,%1\";
-   ")
-
-; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits
-(define_insn "trunctqfhf2"
-  [(set (match_operand:HF 0 "register_operand" "=r,r")
-        (float_truncate:HF
-          (match_operand:TQF 1 "general_operand" "r,m")))]
-  ""
-  "@
-     dlr r%0,r%1  ;trunctqfhf2
-     dl  r%0,%1   ;trunctqfhf2 ")
-
-
-;; Conversion between fixed point and floating point.
-
-(define_insn "floatqihf2"
-  [(set           (match_operand:HF 0 "register_operand" "=r")
-        (float:HF (match_operand:QI 1 "register_operand" "r")))]
-  ""
-  "flt r%0,r%1")
-
-(define_insn "floathitqf2"
-  [(set           (match_operand:TQF 0 "register_operand" "=r")
-        (float:TQF (match_operand:HI 1 "register_operand" "r")))]
-  ""
-  "eflt r%0,r%1")
-
-
-;; Convert floats to ints
-
-(define_insn "fix_trunchfqi2"
-  [(set                 (match_operand:QI 0 "register_operand" "=r")
-        (fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))]
-  ""
-  "fix r%0,r%1")
-
-(define_insn "fix_trunctqfhi2"
-  [(set                 (match_operand:HI 0 "register_operand" "=r")
-        (fix:HI (fix:TQF (match_operand:TQF 1 "register_operand" "r"))))]
-  ""
-  "efix r%0,r%1")
-
-
-;; Move instructions
-
-;; We can't deal with normal byte-size characters, only with WIDE characters!
-;; This may appear as a serious restriction, but it also opens the doors
-;; for ISO 10646  :-)
-
-;; 16-bit moves
-
-; memory indirect to reg
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-        (mem:QI (match_operand 1 "memory_operand"  "m")))]
-  ""
-  "li   r%0,%1")
-
-; reg/const to memory indirect
-(define_insn ""
-  [(set (mem:QI (match_operand 0 "memory_operand" "=m,m"))
-        (match_operand:QI 1 "nonmemory_operand"  "r,K"))]
-  ""
-  "@
-     sti  r%1,%0
-     stci %1,%0")
-
-; general case
-(define_insn "movqi"
-  [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,m,m")
-        (match_operand:QI 1 "general_operand"  "O,I,J,i,r,m,r,K"))]
-  ""
-  "@
-     xorr r%0,r%0
-     lisp r%0,%1
-     lisn r%0,%J1
-     lim  r%0,%1
-     lr   r%0,r%1
-     l    r%0,%1
-     st   r%1,%0
-     stc  %1,%0   ")
-
-;; 32-bit moves
-
-; memory indirect to reg
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-        (mem:HI (match_operand 1 "memory_operand"  "m")))]
-  ""
-  "dli  r%0,%1")
-
-; reg to memory indirect
-(define_insn ""
-  [(set (mem:HI (match_operand 0 "memory_operand" "=m"))
-        (match_operand:HI 1 "register_operand"  "r"))]
-  ""
-  "dsti r%1,%0")
-
-; general case
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=r,r,r,r,r,m,m")
-        (match_operand:HI 1 "general_operand"  "O,I,J,r,m,r,K"))]
-  ""
-  "@
-    xorr r%0,r%0\;xorr r%d0,r%d0
-    xorr r%0,r%0\;lisp r%d0,%1
-    lisn r%0,1  \;lisn r%d0,%J1
-    dlr  r%0,r%1
-    dl   r%0,%1
-    dst  r%1,%0
-    stc  0,%0   \;stc  %1,%A0 ")
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-        (match_operand:HI 1 "general_operand"  "g"))]
-  ""
-  "
-   {
-     rtx op1 = operands[1];
-     if (GET_CODE (operands[0]) == MEM)
-       {
-         if (GET_CODE (op1) == MEM
-	     || (GET_CODE (op1) == CONST_INT
-		 && (INTVAL (op1) < 0 || INTVAL (op1) > 15)))
-	   operands[1] = force_reg (HImode, operands[1]);
-       }
-     else if (GET_CODE (op1) == CONST_INT
-	      && (INTVAL (op1) < -16 || INTVAL (op1) > 16))
-       operands[1] = force_const_mem (HImode, operands[1]);
-   }")
-
-
-;; Single-Float moves
-
-(define_insn ""
-  [(set (match_operand:HF 0 "general_operand" "=r,r,m,m")
-        (match_operand:HF 1 "general_operand"  "r,m,r,G"))]
-  ""
-  "@
-    dlr  r%0,r%1
-    dl   r%0,%1
-    dst  r%1,%0
-    stc  0,%0   \;stc 0,%A0 ")
-
-(define_expand "movhf"
-  [(set (match_operand:HF 0 "general_operand" "")
-        (match_operand:HF 1 "general_operand" ""))]
-  ""
-  "
-   {
-     enum rtx_code op1code = GET_CODE (operands[1]);
-     if (GET_CODE (operands[0]) == MEM)
-       {
-         if (op1code == MEM || (op1code == CONST_DOUBLE
-             && !rtx_equal_p (operands[1], CONST0_RTX (HFmode))))
-	   operands[1] = force_reg (HFmode, operands[1]);
-       }
-     else if (op1code == CONST_DOUBLE)
-       operands[1] = force_const_mem (HFmode, operands[1]);
-   }")
-
-
-;; Longfloat moves
-
-(define_insn ""
-  [(set (match_operand:TQF 0 "general_operand" "=r,r,m")
-        (match_operand:TQF 1 "general_operand"  "r,m,r"))]
-  ""
-  "@
-    eflr.m %0,%1
-    efl  r%0,%1
-    efst r%1,%0 ")
-
-(define_expand "movtqf"
-  [(set (match_operand:TQF 0 "general_operand" "")
-        (match_operand:TQF 1 "general_operand" ""))]
-  ""
-  "
-   {
-     enum rtx_code op1code = GET_CODE (operands[1]);
-     if (GET_CODE (operands[0]) == MEM)
-       {
-         if (op1code == MEM || op1code == CONST_DOUBLE)
-	   operands[1] = force_reg (TQFmode, operands[1]);
-       }
-     else if (op1code == CONST_DOUBLE)
-       operands[1] = force_const_mem (TQFmode, operands[1]);
-   }")
-
-
-;; add instructions 
-
-;; single integer
-
-(define_insn "addqi3"
-  [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m")
-        (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0")
-                 (match_operand:QI 2 "general_operand"  "I,J,i,r,m,I,J")))]
-  ""
-  "*
-    switch (which_alternative)
-      {
-        case 0:
-          return \"aisp r%0,%2\";
-        case 1:
-          return \"sisp r%0,%J2\";
-        case 2:
-          if (INTVAL(operands[2]) < 0)
-            return \"sim r%0,%J2\";
-          else
-            return \"aim r%0,%2\";
-        case 3:
-          return \"ar r%0,r%2\";
-        case 4:
-          return \"a r%0,%2\";
-        case 5:
-          return \"incm %2,%0\";
-        case 6:
-          return \"decm %J2,%0\";
-      } ")
-
-;; double integer
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-        (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
-                 (match_operand:HI 2 "general_operand" "r,m")))]
-  ""
-  "@
-    dar r%0,r%2
-    da  r%0,%2 ")
-
-(define_insn "addhf3"
-  [(set (match_operand:HF 0 "register_operand" "=r,r")
-        (plus:HF (match_operand:HF 1 "register_operand" "%0,0")
-                 (match_operand:HF 2 "general_operand" "r,m")))]
-  ""
-  "@
-    far r%0,r%2
-    fa  r%0,%2 ")
-
-(define_insn "addtqf3"
-  [(set (match_operand:TQF 0 "register_operand" "=r,r")
-        (plus:TQF (match_operand:TQF 1 "register_operand" "%0,0")
-                 (match_operand:TQF 2 "general_operand" "r,m")))]
-  ""
-  "@
-    efar r%0,r%2
-    efa  r%0,%2 ")
-
-
-;; subtract instructions
-
-;; single integer
-(define_insn "subqi3"
-  [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,m")
-        (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0")
-                  (match_operand:QI 2 "general_operand"  "I,i,r,m,I")))]
-  ""
-  "@
-    sisp r%0,%2
-    sim  r%0,%2
-    sr   r%0,r%2
-    s    r%0,%2
-    decm %2,%0 ")
-
-;; double integer
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-        (minus:HI (match_operand:HI 1 "register_operand" "0,0")
-                  (match_operand:HI 2 "general_operand" "r,m")))]
-  ""
-  "@
-    dsr r%0,r%2
-    ds  r%0,%2 ")
-
-(define_insn "subhf3"
-  [(set (match_operand:HF 0 "register_operand" "=r,r")
-        (minus:HF (match_operand:HF 1 "register_operand" "0,0")
-                  (match_operand:HF 2 "general_operand" "r,m")))]
-  ""
-  "@
-    fsr r%0,r%2
-    fs  r%0,%2 ")
-
-(define_insn "subtqf3"
-  [(set (match_operand:TQF 0 "register_operand" "=r,r")
-        (minus:TQF (match_operand:TQF 1 "register_operand" "0,0")
-                  (match_operand:TQF 2 "general_operand" "r,m")))]
-  ""
-  "@
-    efsr r%0,r%2
-    efs  r%0,%2 ")
-
-
-;; multiply instructions
-
-(define_insn "mulqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
-        (mult:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
-                 (match_operand:QI 2 "general_operand"  "I,J,M,r,m")))]
-  ""
-  "@
-     misp r%0,%2
-     misn r%0,%J2
-     msim r%0,%2
-     msr  r%0,r%2
-     ms   r%0,%2  ")
-
-
-; 32-bit product
-(define_insn "mulqihi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
-    (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%r,r,r"))
-             (sign_extend:HI (match_operand:QI 2 "general_operand" "r,m,i"))))]
-  ""
-  "*
-    if (REGNO (operands[1]) != REGNO (operands[0]))
-      output_asm_insn (\"lr r%0,r%1\", operands);
-
-    switch (which_alternative)
-      {
-      case 0:
-        return \"mr  r%0,r%2\";
-      case 1:
-        return \"m   r%0,%2\";
-      case 2:
-        return \"mim r%0,%2\";
-      }
-  ")
-
-
-(define_insn "mulhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-        (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
-                 (match_operand:HI 2 "general_operand" "r,m")))]
-  ""
-  "@
-    dmr r%0,r%2
-    dm  r%0,%2 ")
-
-; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's)
-
-(define_insn "mulhf3"
-  [(set (match_operand:HF 0 "register_operand" "=r,r")
-        (mult:HF (match_operand:HF 1 "register_operand" "%0,0")
-                 (match_operand:HF 2 "general_operand" "r,m")))]
-  ""
-  "@
-    fmr r%0,r%2
-    fm  r%0,%2 ")
-
-(define_insn "multqf3"
-  [(set (match_operand:TQF 0 "register_operand" "=r,r")
-        (mult:TQF (match_operand:TQF 1 "register_operand" "%0,0")
-                 (match_operand:TQF 2 "general_operand" "r,m")))]
-  ""
-  "@
-    efmr r%0,r%2
-    efm  r%0,%2 ")
-
-
-;; divide instructions
-;; The 1750 16bit integer division instructions deliver a 16-bit
-;; quotient and a 16-bit remainder, where the remainder is in the next higher
-;; register number above the quotient. For now, we haven't found a way
-;; to give the reload pass knowledge of this property. So we make do with
-;; whatever registers the allocator wants, and willy-nilly output a pair of
-;; register-copy ops when needed. (See mod_regno_adjust() in file aux-output.c)
-;; A comment in the description of `divmodM4' suggests that one leave the divM3
-;; undefined when there is a divmodM4 available.
-
-(define_insn "divmodqi4"
-  [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
-        (div:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
-                (match_operand:QI 2 "general_operand"  "I,J,M,r,m")))
-   (set (match_operand:QI 3 "register_operand" "=r,r,r,r,r")
-        (mod:QI (match_dup 1) (match_dup 2)))]
-  ""
-  "*
-   {
-     char *istr;
-     switch(which_alternative)
-       {
-       case 0:
-         istr = \"disp\";
-         break;
-       case 1:
-	 {
-	   rtx new_opnds[4];
-	   new_opnds[0] = operands[0];
-	   new_opnds[1] = operands[1];
-	   new_opnds[2] = GEN_INT (-INTVAL(operands[2]));
-	   new_opnds[3] = operands[3];
-           istr = \"disn\";
-	   return mod_regno_adjust (istr, new_opnds);
-	 }
-         break;
-       case 2:
-         istr = \"dvim\";
-         break;
-       case 3:
-         istr = \"dvr \";
-         break;
-       case 4:
-         istr = \"dv  \";
-         break;
-      }
-      return mod_regno_adjust (istr, operands);
-     }")
-
-;; Division for other types is straightforward.
-
-(define_insn "divhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-        (div:HI (match_operand:HI 1 "register_operand" "0,0")
-                (match_operand:HI 2 "general_operand" "r,m")))]
-  ""
-  "@
-    ddr r%0,r%2
-    dd  r%0,%2 ")
-
-(define_insn "divhf3"
-  [(set (match_operand:HF 0 "register_operand" "=r,r")
-        (div:HF (match_operand:HF 1 "register_operand" "0,0")
-                (match_operand:HF 2 "general_operand" "r,m")))]
-  ""
-  "@
-    fdr r%0,r%2
-    fd  r%0,%2 ")
-
-(define_insn "divtqf3"
-  [(set (match_operand:TQF 0 "register_operand" "=r,r")
-        (div:TQF (match_operand:TQF 1 "register_operand" "0,0")
-                (match_operand:TQF 2 "general_operand" "r,m")))]
-  ""
-  "@
-    efdr r%0,r%2
-    efd  r%0,%2 ")
-
-
-;; Other arithmetic instructions:
-
-;; Absolute value
-
-(define_insn "absqi2"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-        (abs:QI (match_operand:QI 1 "register_operand" "r")))]
-  ""
-  "abs r%0,r%1")
-
-(define_insn "abshi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-        (abs:HI (match_operand:HI 1 "register_operand" "r")))]
-  ""
-  "dabs r%0,r%1")
-
-(define_insn "abshf2"
-  [(set (match_operand:HF 0 "register_operand" "=r")
-        (abs:HF (match_operand:HF 1 "register_operand" "r")))]
-  ""
-  "fabs r%0,r%1")
-
-
-;; Negation
-
-(define_insn "negqi2"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-        (neg:QI (match_operand:QI 1 "register_operand" "r")))]
-  ""
-  "neg r%0,r%1")
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-        (neg:HI (match_operand:HI 1 "register_operand" "r")))]
-  ""
-  "dneg r%0,r%1")
-
-(define_insn "neghf2"
-  [(set (match_operand:HF 0 "register_operand" "=r")
-        (neg:HF (match_operand:HF 1 "register_operand" "r")))]
-  ""
-  "fneg r%0,r%1")
-
-; The 1750A does not have an extended float negate instruction, so simulate.
-(define_expand "negtqf2"
-  [(set (match_operand:TQF 0 "register_operand" "=&r")
-        (neg:TQF (match_operand:TQF 1 "register_operand" "r")))]
-  ""
-  "
-   emit_insn(gen_rtx(SET,VOIDmode,operands[0],CONST0_RTX(TQFmode)));
-   emit_insn(gen_rtx(SET,VOIDmode,operands[0],
-             gen_rtx(MINUS,TQFmode,operands[0],operands[1])));
-   DONE;
-  ")
-
-
-;; bit-logical instructions
-
-;; Set Bit
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=r,m")
-        (ior:QI  (match_operand:QI 1 "general_operand" "0,0")
-                 (match_operand:QI 2 "const_int_operand" "i,i")))]
-  "one_bit_set_p (INTVAL (operands [2]))"
-  "@
-    sbr    %b2,r%0
-    sb     %b2,%0")
-
-;; Reset Bit
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=r,m")
-        (and:QI  (match_operand:QI 1 "general_operand" "0,0")
-                 (match_operand:QI 2 "const_int_operand" "i,i")))]
-  "one_bit_set_p ((~INTVAL (operands [2])) & 0xffff)"
-  "@
-    rbr    %B2,r%0
-    rb     %B2,%0")
-
-;; Set Variable Bit
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-        (ior:QI  (match_operand:QI 1 "register_operand" "0")
-                 (lshiftrt:QI (const_int 0x8000)
-                      (match_operand:QI 2 "register_operand" "r"))))]
-  ""
-  "svbr   r%2,%r0")
-
-;; Reset Variable Bit
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=r")
-        (and:QI  (match_operand:QI 1 "general_operand" "0")
-            (not:QI (lshiftrt:QI (const_int 0x8000)
-                        (match_operand:QI 2 "register_operand" "r")))))]
-  ""
-  "rvbr   r%2,%r0")
-
-
-;; AND
-
-(define_insn "andqi3"
-  [(set (match_operand:QI 0 "general_operand" "=r,r,r")
-        (and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
-                (match_operand:QI 2 "general_operand" "M,r,m")))]
-  ""
-  "@
-    andm r%0,%2
-    andr r%0,r%2
-    and  r%0,%2 ")
-
-; This sets incorrect condition codes. See notice_update_cc()
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-        (and:HI (match_operand:HI 1 "register_operand" "%0")
-                (match_operand:HI 2 "register_operand" "r")))]
-  ""
-  "danr.m %0,%2")
-
-;; OR
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=r,r,r")
-        (ior:QI  (match_operand:QI 1 "general_operand" "%0,0,0")
-                 (match_operand:QI 2 "general_operand" "M,r,m")))]
-  ""
-  "@
-    orim r%0,%2
-    orr  r%0,r%2
-    or   r%0,%2 ")
-
-; This sets incorrect condition codes. See notice_update_cc()
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-        (ior:HI (match_operand:HI 1 "register_operand" "%0")
-                (match_operand:HI 2 "register_operand" "r")))]
-  ""
-  "dorr.m %0,%2")
-
-;; XOR
-
-(define_insn "xorqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r,r,r")
-        (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0")
-                (match_operand:QI 2 "general_operand"  "M,r,m")))]
-  ""
-  "@
-    xorm r%0,%2
-    xorr r%0,r%2
-    xor  r%0,%2 ")
-
-; This sets incorrect condition codes. See notice_update_cc()
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-        (xor:HI (match_operand:HI 1 "register_operand" "%0")
-                (match_operand:HI 2 "register_operand" "r")))]
-  ""
-  "dxrr.m %0,%2")
-
-;; NAND
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r,r,r")
-	(ior:QI (not:QI (match_operand:QI 1 "register_operand" "%0,0,0"))
-		(not:QI (match_operand:QI 2 "general_operand" "M,r,m"))))]
-  ""
-  "@
-    nim r%0,%2
-    nr  r%0,r%2
-    n   r%0,%2 ")
-
-; This sets incorrect condition codes. See notice_update_cc()
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(ior:HI (not:HI (match_operand:HI 1 "register_operand" "%0"))
-		(not:HI (match_operand:HI 2 "register_operand" "r"))))]
-  ""
-  "dnr.m %0,%2")
-
-;; NOT
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-        (not:QI (match_operand:QI 1 "register_operand" "0")))]
-  ""
-  "nr r%0,r%0")
-
-; This sets incorrect condition codes. See notice_update_cc()
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-        (not:HI (match_operand:HI 1 "register_operand" "0")))]
-  ""
-  "dnr.m %0,%0")
-
-
-;; Shift instructions
-
-; (What to the 1750 is logical-shift-left, GCC likes to call "arithmetic")
-(define_insn "ashlqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r,r")
-        (ashift:QI (match_operand:QI 1 "register_operand" "0,0")
-                   (match_operand:QI 2 "nonmemory_operand" "I,r")))]
-  ""
-  "@
-    sll r%0,%2
-    slr r%0,r%2 ")
-
-(define_insn "ashlhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-        (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
-                   (match_operand:QI 2 "nonmemory_operand" "L,r")))]
-  ""                        ; the 'L' constraint is a slight imprecise...
-  "*
-    if (which_alternative == 1)
-      return \"dslr r%0,r%2\";
-    else if (INTVAL(operands[2]) <= 16)
-      return \"dsll r%0,%2\";
-    else
-      {
-        output_asm_insn (\"dsll r%0,16  ; ashlhi3 shiftcnt > 16\", operands);
-        return \"sll r%0,%w2\";
-      }
-  ")
-
-
-;; Right shift by a variable shiftcount works by negating the shift count,
-;; then emitting a right shift with the shift count negated.  This means
-;; that all actual shift counts in the RTL will be positive.  This 
-;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
-;; which isn't valid.
-(define_expand "lshrqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
-		     (match_operand:QI 2 "nonmemory_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
-		     (match_operand:QI 2 "immediate_operand" "I")))]
-  ""
-  "srl r%0,%2")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
-		     (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
-  ""
-  "slr r%0,r%2 ")
-
-;; Same thing for HImode.
-
-(define_expand "lshrhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
-		     (match_operand:QI 2 "nonmemory_operand" "g")))]
-  ""
-  "
-  {
-    if (GET_CODE (operands[2]) != CONST_INT)
-      operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
-  }")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
-		     (match_operand:QI 2 "immediate_operand" "L")))]
-  ""
-  "*
-    if (INTVAL (operands[2]) <= 16)
-      return \"dsrl r%0,%2\";
-    output_asm_insn (\"dsrl r%0,16  ; lshrhi3 shiftcount > 16\", operands);
-    return \"srl  r%d0,%w2\";
-  ")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
-		     (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
-  ""
-  "dslr r%0,r%2 ")
-
-;; Same applies for arithmetic shift right.
-(define_expand "ashrqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
-		     (match_operand:QI 2 "nonmemory_operand" "g")))]
-  ""
-  "
-  {
-    if (GET_CODE (operands[2]) != CONST_INT)
-      operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
-  }")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
-		     (match_operand:QI 2 "immediate_operand" "I")))]
-  ""
-  "sra r%0,%2")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
-		     (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
-  ""
-  "sar r%0,r%2 ")
-
-;; HImode arithmetic shift right.
-(define_expand "ashrhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
-		     (match_operand:QI 2 "nonmemory_operand" "g")))]
-  ""
-  "
-  {
-    if (GET_CODE (operands[2]) != CONST_INT)
-      operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
-  }")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
-		     (match_operand:QI 2 "immediate_operand" "L")))]
-  ""
-  "*
-    if (INTVAL (operands[2]) <= 16)
-      return \"dsra r%0,%2\";
-    output_asm_insn (\"dsra r%0,16  ; ashrhi3 shiftcount > 16\", operands);
-    return \"sra  r%d0,%w2\";
-  ")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
-		     (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
-  ""
-  "dsar r%0,r%2 ")
-
-
-;; rotate instructions
-
-(define_insn "rotlqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r,r")
-        (rotate:QI (match_operand:QI 1 "register_operand" "0,0")
-                   (match_operand:QI 2 "nonmemory_operand" "I,r")))]
-  ""
-  "@
-    slc r%0,%2
-    scr r%0,r%2 ")
-
-(define_insn "rotlhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-        (rotate:HI (match_operand:HI 1 "register_operand" "0,0")
-                   (match_operand:QI 2 "nonmemory_operand" "I,r")))]
-  ""
-  "@
-    dslc r%0,%2
-    dscr r%0,r%2 ")
-
-(define_insn "rotrqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-        (rotatert:QI (match_operand:QI 1 "register_operand" "0")
-                     (match_operand:QI 2 "register_operand" "r")))]
-  ""
-  "neg r%2,r%2\;scr r%0,r%2 ")
-
-(define_insn "rotrhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-        (rotatert:HI (match_operand:HI 1 "register_operand" "0")
-                     (match_operand:QI 2 "nonmemory_operand" "r")))]
-  ""
-  "neg  r%2,r%2\;dscr r%0,r%2 ")
-
-
-
-;; Special cases of bit-field insns which we should
-;; recognize in preference to the general case.
-;; These handle aligned 8-bit and 16-bit fields,
-;; which can usually be done with move instructions.
-;    1750: t.b.d.
-;********************
-
-;; Bit field instructions, general cases.
-;; "o,d" constraint causes a nonoffsettable memref to match the "o"
-;; so that its address is reloaded.
-
-;; (define_insn "extv" ...
-
-;; (define_insn "extzv" ...
-
-;; (define_insn "insv" ...
-
-;; Now recognize bit field insns that operate on registers
-;; (or at least were intended to do so).
-;[unnamed only]
-
-;; Special patterns for optimizing bit-field instructions.
-;**************************************
-
-; cc status test ops n.a. on 1750 ......... e.g. "sleu" on 68k:
-;  [(set (match_operand:QI 0 "general_operand" "=d")
-;        (leu (cc0) (const_int 0)))]
-;  ""
-;  "* cc_status = cc_prev_status;
-;     return \"sls %0\"; ")
-
-
-;; Basic conditional jump instructions.
-
-(define_insn "beq"
-  [(set (pc)
-        (if_then_else (eq (cc0)
-                          (const_int 0))
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))]
-  ""
-  "* return branch_or_jump (\"ez\", CODE_LABEL_NUMBER (operands[0]));
-  ")
-
-(define_insn "bne"
-  [(set (pc)
-        (if_then_else (ne (cc0)
-                          (const_int 0))
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))]
-  ""
-  "* return branch_or_jump (\"nz\", CODE_LABEL_NUMBER (operands[0]));
-  ")
-
-(define_insn "bgt"
-  [(set (pc)
-        (if_then_else (gt (cc0)
-                          (const_int 0))
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))]
-  ""
-  "* return branch_or_jump (\"gt\", CODE_LABEL_NUMBER (operands[0]));
-  ")
-
-(define_insn "blt"
-  [(set (pc)
-        (if_then_else (lt (cc0)
-                          (const_int 0))
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))]
-  ""
-  "* return branch_or_jump (\"lt\", CODE_LABEL_NUMBER (operands[0]));
-  ")
-
-(define_insn "bge"
-  [(set (pc)
-        (if_then_else (ge (cc0)
-                          (const_int 0))
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))]
-  ""
-  "* return branch_or_jump (\"ge\", CODE_LABEL_NUMBER (operands[0]));
-  ")
-
-(define_insn "ble"
-  [(set (pc)
-        (if_then_else (le (cc0)
-                          (const_int 0))
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))]
-  ""
-  "* return branch_or_jump (\"le\", CODE_LABEL_NUMBER (operands[0]));
-  ")
-
-
-; no unsigned branches available on 1750. But GCC still needs them, so faking:
-
-(define_insn "bgtu"
-  [(set (pc)
-        (if_then_else (gtu (cc0)
-                          (const_int 0))
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))]
-  ""
-  "jc gt,%l0 ; Warning: this should be an *unsigned* test!")
-
-(define_insn "bltu"
-  [(set (pc)
-        (if_then_else (ltu (cc0)
-                          (const_int 0))
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))]
-  ""
-  "jc lt,%l0 ; Warning: this should be an *unsigned* test!")
-
-(define_insn "bgeu"
-  [(set (pc)
-        (if_then_else (geu (cc0)
-                          (const_int 0))
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))]
-  ""
-  "jc ge,%l0 ; Warning: this should be an *unsigned* test!")
-
-(define_insn "bleu"
-  [(set (pc)
-        (if_then_else (leu (cc0)
-                          (const_int 0))
-                      (label_ref (match_operand 0 "" ""))
-                      (pc)))]
-  ""
-  "jc le,%l0 ; Warning: this should be an *unsigned* test!")
-
-
-;; Negated conditional jump instructions.
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (eq (cc0)
-                          (const_int 0))
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return branch_or_jump (\"nz\", CODE_LABEL_NUMBER (operands[0]));
-  ")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ne (cc0)
-                          (const_int 0))
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return branch_or_jump (\"ez\", CODE_LABEL_NUMBER (operands[0]));
-  ")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (gt (cc0)
-                          (const_int 0))
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return branch_or_jump (\"le\", CODE_LABEL_NUMBER (operands[0]));
-  ")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (lt (cc0)
-                          (const_int 0))
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return branch_or_jump (\"ge\", CODE_LABEL_NUMBER (operands[0]));
-  ")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ge (cc0)
-                          (const_int 0))
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return branch_or_jump (\"lt\", CODE_LABEL_NUMBER (operands[0]));
-  ")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (le (cc0)
-                          (const_int 0))
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return branch_or_jump (\"gt\", CODE_LABEL_NUMBER (operands[0]));
-  ")
-
-
-;; Negated unsigned conditional jump instructions (faked for 1750).
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (gtu (cc0)
-                          (const_int 0))
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jc le,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ltu (cc0)
-                          (const_int 0))
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jc ge,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (geu (cc0)
-                          (const_int 0))
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jc lt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (leu (cc0)
-                          (const_int 0))
-                      (pc)
-                      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jc gt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
-
-;; Tablejump 
-;; 1750 note: CASE_VECTOR_PC_RELATIVE is not defined
-(define_insn "tablejump"
-  [(set (pc)
-        (match_operand:QI 0 "register_operand" "b"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jc 15,0,r%0   ; tablejump label_ref=%1")
-
-
-;; Unconditional jump
-(define_insn "jump"
-  [(set (pc)
-        (label_ref (match_operand 0 "" "")))]
-  ""
-  "jc 15,%0")
-
-;; Call subroutine, returning value in operand 0
-;; (which must be a hard register).
-(define_insn "call_value"
-  [(set (match_operand 0 "register_operand" "r")
-        (call (match_operand:QI 1 "memory_operand" "m")
-              (match_operand:QI 2 "general_operand" "g")))]
-  ;; Operand 2 not really used for 1750.
-  ""
-  "sjs r15,%1   ; return value in R0")
-
-;; Call subroutine with no return value.
-
-;;  Operand 1 not really used in MIL-STD-1750.
-(define_insn ""
-  [(call (match_operand:QI 0 "memory_operand" "mp")
-         (match_operand:QI 1 "general_operand" ""))]
-  ""
-  "sjs r15,%0   ; no return value")
-
-;;;;;;;;;;;; 1750: NOT READY YET.
-(define_insn "call"
-  [(call (match_operand:QI 0 "" "")
-         (match_operand:QI 1 "" ""))]
-  ""
-  "ANYCALL %0")
-
-
-; (define_insn "return"
-;   [(return)]
-;   ""
-;   "*
-;    { 
-;         rtx oprnd = GEN_INT (get_frame_size());
-;         output_asm_insn(\"ret.m  %0\",&oprnd);
-;         return \"\;\";
-;    } ")
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:QI 0 "address_operand" "p"))]
-  ""
-  "jci 15,%0")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
-
-
-;; Subtract One and Jump (if non-zero)
-(define_peephole 
-  [(set (match_operand:QI 0 "register_operand" "=r")
-        (plus:QI (match_operand:QI 1 "register_operand" "%0")
-                 (match_operand:QI 2 "immediate_operand" "J")))
-   (set (cc0) (match_dup 0))
-   (set (pc)
-        (if_then_else (ne (cc0) (const_int 0))
-         (label_ref (match_operand 3 "" ""))
-         (pc)))
-   ]
-  "INTVAL(operands[2]) == -1"
-  "soj r%0,%3")
-
-;; Combine a Load Register with subsequent increment/decrement into a LIM
-(define_peephole 
-  [(set (match_operand:QI 0 "register_operand" "=r")
-        (match_operand:QI 1 "register_operand" "b"))
-   (set (match_dup 0)
-        (plus:QI (match_dup 0)
-                 (match_operand:QI 2 "immediate_operand" "i")))]
-  "REGNO(operands[1]) > 0"
-  "lim r%0,%2,r%1  ; LR,inc/dec peephole")
-
-;; Eliminate the redundant load in a store/load sequence
-(define_peephole 
-  [(set (mem:QI (plus:QI (match_operand:QI 0 "register_operand" "r")
-			  (match_operand:QI 1 "immediate_operand" "i")))
-	(match_operand:QI 2 "register_operand" "r"))
-   (set (match_operand:QI 3 "register_operand" "=r")
-	(mem:QI (plus:QI (match_dup 0)
-			 (match_dup 1))))
-   ]
-  "REGNO(operands[2]) == REGNO(operands[3])"
-  "st r%2,%1,r%0  ; eliminated previous redundant load")
-
-;;;End.
diff --git a/gcc/config/1750a/ms1750.inc b/gcc/config/1750a/ms1750.inc
deleted file mode 100755
index cb41e95..0000000
--- a/gcc/config/1750a/ms1750.inc
+++ /dev/null
@@ -1,158 +0,0 @@
-;; GCC assembler includefile for AS1750
-;;
-;; Macros defined:
-;;   EFLR.M  #d,#s	Load the three regs starting at R#s to R#d following.
-;;   RET.M   #fs	Return from function (uses the framesize #fs)
-
-
-UC	SET	15
-
-; Return from function ; parameter: framesize
-     MACRO RET.M
-	IF `1` > 0
-	    IF `1` <= 16
-		AISP R14,`1`
-	    ELSE
-		AIM  R14,`1`
-	    ENDIF
-	ENDIF
-	LR   R15,R14
-	URS  R15
-     ENDMACRO
-
-; Useful instructions missing from the 1750A standard:
-
-; Extended Float Load from Registers
-     MACRO EFLR.M	; args : #1=dest-regno, #2=source-regno
-ONE 	SET  `1` + 2
-TWO 	SET  `2` + 2
-	IF `1` >= `2` || `1`+2 < `2`
-	    LR    R`ONE`,R`TWO`
-	    DLR   R`1`,R`2`
-	ELSE
-	    DLR   R`1`,R`2`
-	    LR    R`ONE`,R`TWO`
-	    DLR   R`1`,R`1`	; Just to update condition codes
-	ENDIF
-     ENDMACRO
-
-; The following leave the condition codes haywire. But that is
-; accounted for (see notice_update_cc in config/1750a.c.)
-
-; Double ANd Register with Register
-     MACRO DANR.M
-ONE 	SET  `1` + 1
-TWO 	SET  `2` + 1
-	ANDR  R`1`,R`2`
-	ANDR  R`ONE`,R`TWO`
-     ENDMACRO
-
-; Double OR Register with Register
-     MACRO DORR.M
-ONE 	SET  `1` + 1
-TWO 	SET  `2` + 1
-	ORR   R`1`,R`2`
-	ORR   R`ONE`,R`TWO`
-     ENDMACRO
-
-; Double eXoR Register with Register
-     MACRO DXRR.M
-ONE 	SET  `1` + 1
-TWO 	SET  `2` + 1
-	XORR  R`1`,R`2`
-	XORR  R`ONE`,R`TWO`
-     ENDMACRO
-
-; Double Nand Register with register
-     MACRO DNR.M
-ONE 	SET  `1` + 1
-TWO 	SET  `2` + 1
-	NR    R`1`,R`2`
-	NR    R`ONE`,R`TWO`
-     ENDMACRO
-
-; Unsigned Compare Immediate
-
-     MACRO UCIM.M
-LAST	SET   `1` + 3
-	PSHM  R`1`,R`LAST`
-LO	SET   `1` + 1
-	LR    R`LO`,R`1`
-	XORR  R`1`,R`1`
-HI	SET   `1` + 2
-	XORR  R`HI`,R`HI`
-	LIM   R`LAST`,`2`
-	DCR   R`1`,R`HI`
-	POPM  R`1`,R`LAST`
-     ENDMACRO
-
-
-; Unsigned Compare Register with register
-
-     MACRO UCR.M
-	PSHM  R10,R13    ; R12 and R13 are assumed not to be input parameters
-	LR    R13,R`2`
-	LR    R11,R`1`
-	XORR  R12,R12
-	XORR  R10,R10
-	DCR   R10,R12
-	POPM  R10,R13
-     ENDMACRO
-
-
-; Unsigned Compare register with memory
-
-     MACRO UC.M
-	PSHM  R10,R13
-	L     R13,`2`
-	LR    R11,R`1`
-	XORR  R12,R12
-	XORR  R10,R10
-	DCR   R10,R12
-	POPM  R10,R13
-     ENDMACRO
-
-
-; Double Unsigned Compare Register with register
-
-     MACRO DUCR.M
-	PSHM	R13,R14    ; R13 and R14 are assumed not to be input parameters
-LOW1	SET	`1` + 1
-LOW2	SET	`2` + 1
-	PSHM	R`1`,R`LOW1`
-	PSHM	R`2`,R`LOW2`
-	LR	R13,R`LOW1`
-	LR	R14,R`LOW2`
-	DSRL	R`1`,1
-	DSRL	R`2`,1
-	DCR	R`1`,R`2`
-	BNE	+6
-	ANDM	R13,1
-	ANDM	R14,1
-	CR	R13,R14
-	POPM	R`2`,R`LOW2`
-	POPM	R`1`,R`LOW1`
-	POPM	R13,R14
-     ENDMACRO
-
-
-; Double Unsigned Compare register with memory
-
-     MACRO DUC.M
-	PSHM	R13,R14    ; R13 and R14 are assumed not to be input parameters
-LOW1	SET	`1` + 1
-	PSHM	R`1`,R`LOW1`
-	DL	R13,`2`
-	DSRL	R`1`,1
-	DSRL	R13,1
-	DCR	R`1`,R13
-	BNE	+10        ; done, go pop the saved regs
-	DL	R13,`2`    ; interested in the *low* word (R14)
-	L	R13,1,R15
-	ANDM	R13,1
-	ANDM	R14,1
-	CR	R13,R14
-	POPM	R`1`,R`LOW1`
-	POPM	R13,R14
-     ENDMACRO
-
diff --git a/gcc/config/1750a/xm-1750a.h b/gcc/config/1750a/xm-1750a.h
deleted file mode 100755
index 81f5e69..0000000
--- a/gcc/config/1750a/xm-1750a.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Configuration for GNU C-compiler for MIL-STD-1750a.
-   Copyright (C) 1995 Free Software Foundation, Inc.
-
- This file is part of GNU CC.
-
- GNU CC is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 1, or (at your option)
- any later version.
-
- GNU CC is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GNU CC; see the file COPYING.  If not, write to
- the Free Software Foundation, 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA.
-
-*/
-
-#error Gcc cannot run on a 1750a due to size problems!
diff --git a/gcc/config/README b/gcc/config/README
deleted file mode 100755
index 60328ec..0000000
--- a/gcc/config/README
+++ /dev/null
@@ -1,5 +0,0 @@
-This directory contains machine-specific files for the GNU C compiler.
-It has a subdirectory for each basic CPU type.
-The only files in this directory itself
-are some .h files that pertain to particular operating systems
-and are used for more than one CPU type.
diff --git a/gcc/config/a29k/a29k.c b/gcc/config/a29k/a29k.c
deleted file mode 100755
index 395a6ff..0000000
--- a/gcc/config/a29k/a29k.c
+++ /dev/null
@@ -1,1538 +0,0 @@
-/* Subroutines used for code generation on AMD Am29000.
-   Copyright (C) 1987, 88, 90-94, 1995, 1997 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#include "expr.h"
-#include "obstack.h"
-#include "tree.h"
-#include "reload.h"
-
-#define min(A,B)	((A) < (B) ? (A) : (B))
-
-/* This gives the size in words of the register stack for the current
-   procedure.  */
-
-static int a29k_regstack_size;
-
-/* True if the current procedure has a call instruction.  */
-
-static int a29k_makes_calls;
-
-/* This points to the last insn of the insn prologue.  It is set when
-   an insn without a filled delay slot is found near the start of the
-   function.  */
-
-static char *a29k_last_prologue_insn;
-
-/* This points to the first insn that will be in the epilogue.  It is null if
-   no epilogue is required.  */
-
-static char *a29k_first_epilogue_insn;
-
-/* This is nonzero if a a29k_first_epilogue_insn was put in a delay slot.  It
-   indicates that an intermediate label needs to be written.  */
-
-static int a29k_first_epilogue_insn_used;
-
-/* Location to hold the name of the current function.  We need this prolog to
-   contain the tag words prior to the declaration.  So the name must be stored
-   away.  */
-
-char *a29k_function_name;
-
-/* Mapping of registers to debug register numbers.  The only change is
-   for the frame pointer and the register numbers used for the incoming
-   arguments.  */
-
-int a29k_debug_reg_map[FIRST_PSEUDO_REGISTER];
-
-/* Save information from a "cmpxx" operation until the branch or scc is
-   emitted.  */
-
-rtx a29k_compare_op0, a29k_compare_op1;
-int a29k_compare_fp_p;
-
-/* Gives names for registers.  */
-extern char *reg_names[];
-
-/* Returns 1 if OP is a 8-bit constant. */
-
-int
-cint_8_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffffff00) == 0;
-}
-
-/* Returns 1 if OP is a 16-bit constant.  */
-
-int
-cint_16_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0;
-}
-
-/* Returns 1 if OP is a constant that cannot be moved in a single insn.  */
-
-int
-long_const_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (! CONSTANT_P (op))
-    return 0;
-
-  if (TARGET_29050 && GET_CODE (op) == CONST_INT
-      && (INTVAL (op) & 0xffff) == 0)
-    return 0;
-
-  return (GET_CODE (op) != CONST_INT
-	  || ((INTVAL (op) & 0xffff0000) != 0
-	      && (INTVAL (op) & 0xffff0000) != 0xffff0000
-	      && INTVAL (op) != 0x80000000));
-}
-
-/* The following four functions detect constants of 0, 8, 16, and 24 used as
-   a position in ZERO_EXTRACT operations.  They can either be the appropriate
-   constant integer or a shift (which will be produced by combine).  */
-
-static int
-shift_constant_operand (op, mode, val)
-     rtx op;
-     enum machine_mode mode;
-     int val;
-{
-  return ((GET_CODE (op) == CONST_INT && INTVAL (op) == val)
-	  || (GET_CODE (op) == ASHIFT
-	      && GET_CODE (XEXP (op, 0)) == CONST_INT
-	      && INTVAL (XEXP (op, 0)) == val / 8
-	      && GET_CODE (XEXP (op, 1)) == CONST_INT
-	      && INTVAL (XEXP (op, 1)) == 3));
-}
-
-int
-const_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return shift_constant_operand (op, mode, 0);
-}
-
-int
-const_8_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return shift_constant_operand (op, mode, 8);
-}
-
-int
-const_16_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return shift_constant_operand (op, mode, 16);
-}
-
-int
-const_24_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return shift_constant_operand (op, mode, 24);
-}
-
-/* Returns 1 if OP is a floating-point constant of the proper mode.  */
-
-int
-float_const_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == mode;
-}
-
-/* Returns 1 if OP is a floating-point constant of the proper mode or a
-   general-purpose register.  */
-
-int
-gpc_reg_or_float_constant_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return float_const_operand (op, mode) || gpc_reg_operand (op, mode);
-}
-
-/* Returns 1 if OP is an integer constant of the proper mode or a
-   general-purpose register.  */
-
-int
-gpc_reg_or_integer_constant_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return ((GET_MODE (op) == VOIDmode
-	   && (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE))
-	  || gpc_reg_operand (op, mode));
-}
-     
-/* Returns 1 if OP is a special machine register.  */
-
-int
-spec_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != REG || GET_MODE (op) != mode)
-    return 0;
-
-  switch (GET_MODE_CLASS (mode))
-    {
-    case MODE_PARTIAL_INT:
-      return REGNO (op) >= R_BP && REGNO (op) <= R_CR;
-    case MODE_INT:
-      return REGNO (op) >= R_Q && REGNO (op) <= R_EXO;
-    default:
-      return 0;
-    }
-}
-
-/* Returns 1 if OP is an accumulator register.  */
-
-int
-accum_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == REG
-	  && REGNO (op) >= R_ACU (0) && REGNO (op) <= R_ACU (3));
-}
-
-/* Returns 1 if OP is a normal data register.  */
-
-int
-gpc_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int regno;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return 0;
-
-  if (GET_CODE (op) == REG)
-    regno = REGNO (op);
-  else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
-    {
-      regno = REGNO (SUBREG_REG (op));
-      if (regno < FIRST_PSEUDO_REGISTER)
-	regno += SUBREG_WORD (op);
-    }
-  else
-    return 0;
-
-  return (regno >= FIRST_PSEUDO_REGISTER || regno < R_BP
-	  || (regno >= R_KR (0) && regno <= R_KR (31)));
-}
-
-/* Returns 1 if OP is either an 8-bit constant integer or a general register.
-   If a register, it must be in the proper mode unless MODE is VOIDmode.  */
-
-int
-srcb_operand (op, mode)
-      register rtx op;
-      enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT
-      && (mode == QImode
-	  || (INTVAL (op) & 0xffffff00) == 0))
-    return 1;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return 0;
-
-  return gpc_reg_operand (op, mode);
-}
-
-int
-cmplsrcb_operand (op, mode)
-      register rtx op;
-      enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT
-      && (mode == QImode
-	  || (INTVAL (op) & 0xffffff00) == 0xffffff00))
-    return 1;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return 0;
-
-  return gpc_reg_operand (op, mode);
-}
-
-/* Return 1 if OP is either an immediate or a general register.  This is used
-   for the input operand of mtsr/mtrsim.  */
-
-int
-gpc_reg_or_immediate_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return gpc_reg_operand (op, mode) || immediate_operand (op, mode);
-}
-
-/* Return 1 if OP can be used as the second operand of and AND insn.  This
-   includes srcb_operand and a constant whose complement fits in 8 bits.  */
-
-int
-and_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (srcb_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT
-	      && ((unsigned) ((~ INTVAL (op)) & GET_MODE_MASK (mode)) < 256)));
-}
-
-/* Return 1 if OP can be used as the second operand of an ADD insn.
-   This is the same as above, except we use negative, rather than
-   complement.   */
-
-int
-add_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (srcb_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT
-	      && ((unsigned) ((- INTVAL (op)) & GET_MODE_MASK (mode)) < 256)));
-}
-
-/* Return 1 if OP is a valid address in a CALL_INSN.  These are a SYMBOL_REF
-   to the current function, all SYMBOL_REFs if TARGET_SMALL_MEMORY, or
-   a sufficiently-small constant.  */
-
-int
-call_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-      return (TARGET_SMALL_MEMORY
-	      || (! TARGET_LARGE_MEMORY
-		  && ((GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_FLAG (op))
-		      || ! strcmp (XSTR (op, 0), current_function_name))));
-
-    case CONST_INT:
-      return (unsigned HOST_WIDE_INT) INTVAL (op) < 0x40000;
-
-    default:
-      return 0;
-    }
-}
-
-/* Return 1 if OP can be used as the input operand for a move insn.  */
-
-int
-in_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  rtx orig_op = op;
-
-  if (! general_operand (op, mode))
-    return 0;
-
-  while (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  switch (GET_CODE (op))
-    {
-    case REG:
-      return 1;
-
-    case MEM:
-      return (GET_MODE_SIZE (mode) >= UNITS_PER_WORD || TARGET_DW_ENABLE);
-
-    case CONST_INT:
-      if (GET_MODE_CLASS (mode) != MODE_INT
-	  && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
-	return 0;
-
-      return 1;
-
-    case CONST:
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return (GET_MODE (op) == mode
-	      || mode == SImode || mode == HImode || mode == QImode);
-
-    case CONST_DOUBLE:
-      return ((GET_MODE_CLASS (mode) == MODE_FLOAT
-	       && mode == GET_MODE (op))
-	      || (GET_MODE (op) == VOIDmode
-		  && GET_MODE_CLASS (mode) == MODE_INT));
-
-    default:
-      return 0;
-    }
-}
-
-/* Return 1 if OP can be used as the output operand for a move insn.  */
-
-int
-out_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  rtx orig_op = op;
-
-  if (! general_operand (op, mode))
-    return 0;
-
-  while (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) == REG)
-    return (gpc_reg_operand (orig_op, mode)
-	    || spec_reg_operand (orig_op, mode)
-	    || (GET_MODE_CLASS (mode) == MODE_FLOAT
-		&& accum_reg_operand (orig_op, mode)));
-
-  else if (GET_CODE (op) == MEM)
-    return (GET_MODE_SIZE (mode) >= UNITS_PER_WORD || TARGET_DW_ENABLE);
-  else
-    return 0;
-}
-
-/* Return 1 if OP is an item in memory, given that we are in reload.  */
-
-int
-reload_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int regno = true_regnum (op);
-
-  return (! CONSTANT_P (op)
-	  && (regno == -1
-	      || (GET_CODE (op) == REG
-		  && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
-}
-
-/* Given an object for which reload_memory_operand is true, return the address
-   of the operand, taking into account anything that reload may do.  */
-
-rtx
-a29k_get_reloaded_address (op)
-     rtx op;
-{
-  if (GET_CODE (op) == SUBREG)
-    {
-      if (SUBREG_WORD (op) != 0)
-	abort ();
-
-      op = SUBREG_REG (op);
-    }
-
-  if (GET_CODE (op) == REG)
-    op = reg_equiv_mem[REGNO (op)];
-
-  return find_replacement (&XEXP (op, 0));
-}
-
-/* Subfunction of the following function.  Update the flags of any MEM
-   found in part of X.  */
-
-static void
-a29k_set_memflags_1 (x, in_struct_p, scalar_p, volatile_p, unchanging_p)
-     rtx x;
-     int in_struct_p, scalar_p, volatile_p, unchanging_p;
-{
-  int i;
-
-  switch (GET_CODE (x))
-    {
-    case SEQUENCE:
-    case PARALLEL:
-      for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
-	a29k_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
-			     unchanging_p);
-      break;
-
-    case INSN:
-      a29k_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
-			   unchanging_p);
-      break;
-
-    case SET:
-      a29k_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
-			   unchanging_p);
-      a29k_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p, unchanging_p);
-      break;
-
-    case MEM:
-      MEM_IN_STRUCT_P (x) = in_struct_p;
-      MEM_SCALAR_P (x) = scalar_p;
-      MEM_VOLATILE_P (x) = volatile_p;
-      RTX_UNCHANGING_P (x) = unchanging_p;
-      break;
-    }
-}
-
-/* Given INSN, which is either an INSN or a SEQUENCE generated to
-   perform a memory operation, look for any MEMs in either a SET_DEST or
-   a SET_SRC and copy the in-struct, unchanging, and volatile flags from
-   REF into each of the MEMs found.  If REF is not a MEM, don't do
-   anything.  */
-
-void
-a29k_set_memflags (insn, ref)
-     rtx insn;
-     rtx ref;
-{
-  /* Note that it is always safe to get these flags, though they won't
-     be what we think if REF is not a MEM.  */
-  int in_struct_p = MEM_IN_STRUCT_P (ref);
-  int scalar_p = MEM_IN_SCALAR_P (ref);
-  int volatile_p = MEM_VOLATILE_P (ref);
-  int unchanging_p = RTX_UNCHANGING_P (ref);
-
-  if (GET_CODE (ref) != MEM
-      || (! in_struct_p && ! volatile_p && ! unchanging_p))
-    return;
-
-  a29k_set_memflags_1 (insn, in_struct_p, scalar_p, volatile_p, unchanging_p);
-}
-
-/* Return 1 if OP is a comparison operator that we have in floating-point.  */
-
-int
-fp_comparison_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return ((mode == VOIDmode || mode == GET_MODE (op))
-	  && (GET_CODE (op) == EQ || GET_CODE (op) == GT ||
-	      GET_CODE (op) == GE));
-}
-
-/* Return 1 if OP is a valid branch comparison.  */
-
-int
-branch_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return ((mode == VOIDmode || mode == GET_MODE (op))
-	  && (GET_CODE (op) == GE || GET_CODE (op) == LT));
-}
-
-/* Return 1 if OP is a load multiple operation.  It is known to be a
-   PARALLEL and the first three sections will be tested.  */
-
-int
-load_multiple_operation (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int count = XVECLEN (op, 0) - 2;
-  int dest_regno;
-  rtx src_addr;
-  int i;
-
-  /* Perform a quick check so we don't blow up below.  */
-  if (count <= 1
-      || GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
-      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
-    return 0;
-
-  dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
-  src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
-
-  for (i = 1; i < count; i++)
-    {
-      rtx elt = XVECEXP (op, 0, i + 2);
-
-      if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_DEST (elt)) != REG
-	  || GET_MODE (SET_DEST (elt)) != SImode
-	  || REGNO (SET_DEST (elt)) != dest_regno + i
-	  || GET_CODE (SET_SRC (elt)) != MEM
-	  || GET_MODE (SET_SRC (elt)) != SImode
-	  || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
-	  || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
-	  || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
-	  || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
-	return 0;
-    }
-
-  return 1;
-}
-
-/* Similar, but tests for store multiple.  */
-
-int
-store_multiple_operation (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int num_special = TARGET_NO_STOREM_BUG ? 2 : 1;
-  int count = XVECLEN (op, 0) - num_special;
-  int src_regno;
-  rtx dest_addr;
-  int i;
-
-  /* Perform a quick check so we don't blow up below.  */
-  if (count <= 1
-      || GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
-      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
-    return 0;
-
-  src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
-  dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
-
-  for (i = 1; i < count; i++)
-    {
-      rtx elt = XVECEXP (op, 0, i + num_special);
-
-      if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_SRC (elt)) != REG
-	  || GET_MODE (SET_SRC (elt)) != SImode
-	  || REGNO (SET_SRC (elt)) != src_regno + i
-	  || GET_CODE (SET_DEST (elt)) != MEM
-	  || GET_MODE (SET_DEST (elt)) != SImode
-	  || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
-	  || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
-	  || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
-	  || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
-	return 0;
-    }
-
-  return 1;
-}
-
-/* Given a special register REG and MASK, a value being masked against a
-   quantity to which the special register is set, return 1 if the masking
-   operation is built-in to the setting of that special register.  */
-
-int
-masks_bits_for_special (reg, mask)
-     rtx reg;
-     rtx mask;
-{
-   int needed_mask_value;
-
-  if (GET_CODE (reg) != REG || GET_CODE (mask) != CONST_INT)
-    abort ();
-
-  switch (REGNO (reg))
-    {
-    case R_BP:
-    case R_INT:
-      needed_mask_value = 3;
-      break;
-
-    case R_FC:
-      needed_mask_value = 31;
-      break;
-
-    case R_CR:
-    case R_LRU:
-      needed_mask_value = 255;
-      break;
-
-    case R_FPE:
-      needed_mask_value = 511;
-      break;
-
-    case R_MMU:
-      needed_mask_value = 0x3ff;
-      break;
-
-    case R_OPS:
-    case R_CPS:
-    case R_RBP:
-    case R_FPS:
-      needed_mask_value = 0xffff;
-      break;
-
-    case R_VAB:
-      needed_mask_value = 0xffff0000;
-      break;
-
-    case R_Q:
-    case R_CFG:
-    case R_CHA:
-    case R_CHD:
-    case R_CHC:
-    case R_TMC:
-    case R_TMR:
-    case R_PC0:
-    case R_PC1:
-    case R_PC2:
-      return 0;
-
-    default:
-      abort ();
-    }
-
-   return (INTVAL (mask) & ~ needed_mask_value) == 0;
-}
-
-/* Return nonzero if this label is that of the return point, but there is
-   a non-null epilogue.  */
-
-int
-epilogue_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return next_active_insn (op) == 0 && a29k_first_epilogue_insn != 0;
-}
-
-/* Return the register class of a scratch register needed to copy IN into
-   or out of a register in CLASS in MODE.  If it can be done directly,
-   NO_REGS is returned.  */
-
-enum reg_class
-secondary_reload_class (class, mode, in)
-     enum reg_class class;
-     enum machine_mode mode;
-     rtx in;
-{
-  int regno = -1;
-  enum rtx_code code = GET_CODE (in);
-
-  if (! CONSTANT_P (in))
-    {
-      regno = true_regnum (in);
-
-      /* A pseudo is the same as memory.  */
-      if (regno == -1 || regno >= FIRST_PSEUDO_REGISTER)
-	code = MEM;
-    }
-
-  /* If we are transferring between memory and a multi-word mode, we need
-     CR.  */
-
-  if (code == MEM && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
-    return CR_REGS;
-
-  /* If between memory and a mode smaller than a word without DW being
-     enabled, we need BP.  */
-
-  if (code == MEM && ! TARGET_DW_ENABLE
-      && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
-    return BP_REGS;
-
-  /* Otherwise, we can place anything into GENERAL_REGS and can put
-     GENERAL_REGS into anything.  */
-  if (class == GENERAL_REGS
-      || (regno != -1
-	  && (regno < R_BP
-	      || (regno >= R_KR (0) && regno <= R_KR (31)))))
-    return NO_REGS;
-
-  /* We can place 16-bit constants into a special register.  */
-  if (code == CONST_INT
-      && (GET_MODE_BITSIZE (mode) <= 16 || (unsigned) INTVAL (in) <= 65535)
-      && (class == BP_REGS || class == Q_REGS || class == SPECIAL_REGS))
-    return NO_REGS;
-
-  /* Otherwise, we need GENERAL_REGS.  */
-  return GENERAL_REGS;
-}
-
-/* START is the zero-based incoming argument register index used (0 is 160,
-   i.e., the first incoming argument register) and COUNT is the number used.
-
-   Mark the corresponding incoming registers as neither fixed nor call used.
-   For each register used for incoming arguments, we have one less local
-   register that can be used.  So also mark some high-numbered registers as
-   fixed.
-
-   Return the first register number to use for the argument.  */
-
-int
-incoming_reg (start, count)
-     int start;
-     int count;
-{
-  int i;
-
-  /* We only use 16 argument registers, so truncate at the end of the
-     area.  */
-  if (start + count > 16)
-    count = 16 - start;
-
-  if (! TARGET_NO_REUSE_ARGS)
-    /* Mark all the used registers as not fixed and saved over calls.  */
-    for (i = R_AR (start); i < R_AR (start + count); i++)
-      {
-	fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 0;
-	CLEAR_HARD_REG_BIT (fixed_reg_set, i);
-	CLEAR_HARD_REG_BIT (call_used_reg_set, i);
-	CLEAR_HARD_REG_BIT (call_fixed_reg_set, i);
-      }
-
-  /* Shorten the maximum size of the frame.
-     Remember that R_AR(-1,-2) are place holders for the caller's lr0,lr1.
-     Make sure to keep the frame rounded to an even boundary.  Rounding up
-     to an 8 byte boundary will use a slot.  Otherwise a frame with 121 local
-     regs and 5 arguments will overrun the stack (121+1 + 5 + 2 > 128).  */
-  /* ??? An alternative would be to never allocate one reg.  */
-  for (i = (R_AR (0) - 2 - start - count) & ~1; i < R_AR (0) - 2 - start; i++)
-    {
-      fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
-      SET_HARD_REG_BIT (fixed_reg_set, i);
-      SET_HARD_REG_BIT (call_used_reg_set, i);
-      SET_HARD_REG_BIT (call_fixed_reg_set, i);
-    }
-
-  return R_AR (start);
-}
-
-/* Add CLOBBERs to CALL_INSN_FUNCTION_USAGE chain of INSN indicating
-   that LR2 up to, but not including, OP are clobbered.  If OP is
-   zero, indicate all parameter registers are clobbered.  */
-
-void
-a29k_clobbers_to (insn, op)
-     rtx insn;
-     rtx op;
-{
-  int i;
-  int high_regno;
-
-  if (op == 0)
-    high_regno = R_LR (18);
-  else if (GET_CODE (op) != REG || REGNO (op) < R_LR (0)
-	   || REGNO (op) > R_LR (18))
-    abort ();
-  else
-    high_regno = REGNO (op);
-
-  for (i = R_LR (2); i < high_regno; i++)
-    CALL_INSN_FUNCTION_USAGE (insn)
-      = gen_rtx (EXPR_LIST, VOIDmode,
-		 gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, i)),
-		 CALL_INSN_FUNCTION_USAGE (insn));
-}
-
-/* These routines are used in finding insns to fill delay slots in the
-   epilogue.  */
-
-/* Return 1 if the current function will adjust the register stack.  */
-
-int
-needs_regstack_p ()
-{
-  int i;
-  rtx insn;
-
-  if (frame_pointer_needed)
-    return 1;
-
-  /* If any local register is used, we need to adjust the regstack.  */
-  for (i = R_LR (127); i >= R_LR (0); i --)
-    if (regs_ever_live[i])
-      return 1;
-
-  /* We need a register stack if we make any calls.  */
-  for (insn = get_insns (); insn; insn = next_insn (insn))
-    if (GET_CODE (insn) == CALL_INSN
-	|| (GET_CODE (insn) == INSN
-	    && GET_CODE (PATTERN (insn)) == SEQUENCE
-	    && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN))
-      return 1;
-
-  /* Otherwise, we don't.  */
-  return 0;
-}
-
-/* Return 1 if X uses a local register.  */
-
-int
-uses_local_reg_p (x)
-     rtx x;
-{
-  char *fmt;
-  int i, j;
-
-  switch (GET_CODE (x))
-    {
-    case REG:
-      return REGNO (x) >= R_LR (0) && REGNO (x) <= R_FP;
-
-    case CONST_INT:
-    case CONST:
-    case PC:
-    case CC0:
-    case LABEL_REF:
-    case SYMBOL_REF:
-      return 0;
-    }
-
-  fmt = GET_RTX_FORMAT (GET_CODE (x));
-  for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
-    {
-      if (fmt[i] == 'e')
-	{
-	  if (uses_local_reg_p (XEXP (x, i)))
-	    return 1;
-	}
-      else if (fmt[i] == 'E')
-	{
-	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
-	    if (uses_local_reg_p (XVECEXP (x, i, j)))
-	      return 1;
-	}
-    }
-
-  return 0;
-}
-
-/* Returns 1 if this function is known to have a null epilogue.  */
-
-int
-null_epilogue ()
-{
-  return (reload_completed && ! needs_regstack_p ()
-	  && get_frame_size () == 0
-	  && current_function_pretend_args_size == 0);
-}
-
-/* Write out the assembler form of an operand.  Recognize the following
-   special options:
-
-	%N means write the low-order 8 bits of the negative of the constant
-	%Q means write a QImode operand (truncate constants to 8 bits)
-	%M means write the low-order 16 bits of the constant
-	%m means write the low-order 16 bits shifted left 16 bits
-	%C means write the low-order 8 bits of the complement of the constant
-	%b means write `f' is this is a reversed condition, `t' otherwise
-	%B means write `t' is this is a reversed condition, `f' otherwise
-	%J means write the 29k opcode part for a comparison operation
-	%e means write the label with an extra `X' is this is the epilogue
-	               otherwise the normal label name
-	%E means write nothing if this insn has a delay slot,
-		       a nop unless this is the epilogue label, in which case
-		       write the first epilogue insn
-	%F means write just the normal operand if the insn has a delay slot;
-		       otherwise, this is a recursive call so output the
-		       symbol + 4 and write the first prologue insn in the
-		       delay slot.
-	%L means write the register number plus one ("low order" register)
-		       or the low-order part of a multi-word constant
-	%O means write the register number plus two
-	%P means write the register number plus three ("low order" of TImode)
-	%S means write the number of words in the mode of the operand,
-		       minus one (for CR)
-        %V means write the number of elements in a PARALLEL minus 1
-	%# means write nothing if we have a delay slot, "\n\tnop" otherwise
-	%* means write the register name for TPC.  */
-
-void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     char code;
-{
-  char buf[100];
-
-  /* These macros test for integers and extract the low-order bits.  */
-#define INT_P(X)  \
-((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE)	\
- && GET_MODE (X) == VOIDmode)
-
-#define INT_LOWPART(X) \
-  (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
-
-  switch (code)
-    {
-    case 'Q':
-      if (GET_CODE (x) == REG)
-	break;
-      else if (! INT_P (x))
-	output_operand_lossage ("invalid %%Q value");
-      fprintf (file, "%d", INT_LOWPART (x) & 0xff);
-      return;
-
-    case 'C':
-      if (! INT_P (x))
-	output_operand_lossage ("invalid %%C value");
-      fprintf (file, "%d", (~ INT_LOWPART (x)) & 0xff);
-      return;
-
-    case 'N':
-      if (! INT_P (x))
-	output_operand_lossage ("invalid %%N value");
-      fprintf (file, "%d", (- INT_LOWPART (x)) & 0xff);
-      return;
-
-    case 'M':
-      if (! INT_P (x))
-	output_operand_lossage ("invalid %%M value");
-      fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
-      return;
-
-    case 'm':
-      if (! INT_P (x))
-	output_operand_lossage ("invalid %%m value");
-      fprintf (file, "%d", (INT_LOWPART (x) & 0xffff) << 16);
-      return;
-
-    case 'b':
-      if (GET_CODE (x) == GE)
-	fprintf (file, "f");
-      else
-	fprintf (file, "t");
-      return;
-
-    case 'B':
-      if (GET_CODE (x) == GE)
-	fprintf (file, "t");
-      else
-	fprintf (file, "f");
-      return;
-
-    case 'J':
-      /* It so happens that the RTX names for the conditions are the same as
-	 the 29k's insns except for "ne", which requires "neq".  */
-      fprintf (file, GET_RTX_NAME (GET_CODE (x)));
-      if (GET_CODE (x) == NE)
-	fprintf (file, "q");
-      return;
-
-    case 'e':
-      if (optimize && flag_delayed_branch
-	  && a29k_last_prologue_insn == 0 && epilogue_operand (x, VOIDmode)
-	  && dbr_sequence_length () == 0)
-	{
-	  /* We need to output the label number of the last label in the
-	     function, which is not necessarily X since there might be
-	     a USE insn in between.  First go forward to the last insn, then
-	     back up to a label.  */
-	  while (NEXT_INSN (x) != 0)
-	    x = NEXT_INSN (x);
-
-	  while (GET_CODE (x) != CODE_LABEL)
-	    x = PREV_INSN (x);
-
-	  ASM_GENERATE_INTERNAL_LABEL (buf, "LX", CODE_LABEL_NUMBER (x));
-	  assemble_name (file, buf);
-	}
-      else
-	output_asm_label (x);
-      return;
-
-    case 'E':
-      if (dbr_sequence_length ())
-	;
-      else if (a29k_last_prologue_insn)
-	{
-	  fprintf (file, "\n\t%s", a29k_last_prologue_insn);
-	  a29k_last_prologue_insn = 0;
-	}
-      else if (optimize && flag_delayed_branch
-	       && epilogue_operand (x, VOIDmode))
-	{
-	  fprintf (file, "\n\t%s", a29k_first_epilogue_insn);
-	  a29k_first_epilogue_insn_used = 1;
-	}
-      else
-	fprintf (file, "\n\tnop");
-      return;
-      
-    case 'F':
-      output_addr_const (file, x);
-      if (dbr_sequence_length () == 0)
-	{
-	  /* If this doesn't have its delay slot filled, see if we need to
-	     put the last insn of the prolog in it.  If not, see if this is
-	     a recursive call.  If so, we can put the first insn of its
-	     prolog in the delay slot.  Otherwise, write a nop.  */
-	  if (a29k_last_prologue_insn)
-	    {
-	      fprintf (file, "\n\t%s", a29k_last_prologue_insn);
-	      a29k_last_prologue_insn = 0;
-	    }
-	  else if (GET_CODE (x) == SYMBOL_REF
-	      && ! strcmp (XSTR (x, 0), current_function_name))
-	    fprintf (file, "+4\n\t%s,%d",
-		     a29k_regstack_size >= 64 ? "const gr121" : "sub gr1,gr1",
-		     a29k_regstack_size * 4);
-	  else
-	    fprintf (file, "\n\tnop");
-	}
-      return;
-
-    case 'L':
-      if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
-	{
-	  union real_extract u;
-
-	  bcopy ((char *) &CONST_DOUBLE_LOW (x), (char *) &u, sizeof u);
-	  fprintf (file, "$double1(%.20e)", u.d);
-	}
-      else if (GET_CODE (x) == REG)
-	fprintf (file, "%s", reg_names[REGNO (x) + 1]);
-      else
-	output_operand_lossage ("invalid %%L value");
-      return;
-
-    case 'O':
-      if (GET_CODE (x) != REG)
-	output_operand_lossage ("invalid %%O value");
-      fprintf (file, "%s", reg_names[REGNO (x) + 2]);
-      return;
-
-    case 'P':
-      if (GET_CODE (x) != REG)
-	output_operand_lossage ("invalid %%P value");
-      fprintf (file, "%s", reg_names[REGNO (x) + 3]);
-      return;
-
-    case 'S':
-      fprintf (file, "%d", (GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD)-1);
-      return;
-
-    case 'V':
-      if (GET_CODE (x) != PARALLEL)
-	output_operand_lossage ("invalid %%V value");
-      fprintf (file, "%d", XVECLEN (x, 0) - 2);
-      return;
-
-    case '#':
-      if (dbr_sequence_length () == 0)
-	{
-	  if (a29k_last_prologue_insn)
-	    {
-	      fprintf (file, "\n\t%s", a29k_last_prologue_insn);
-	      a29k_last_prologue_insn = 0;
-	    }
-	  else
-	    fprintf (file, "\n\tnop");
-	}
-      return;
-
-    case '*':
-      fprintf (file, "%s", reg_names [R_TPC]);
-      return;
-    }
-
-  if (GET_CODE (x) == REG)
-    fprintf (file, "%s", reg_names [REGNO (x)]);
-
-  else if (GET_CODE (x) == MEM)
-    output_address (XEXP (x, 0));
-
-  else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == SUBREG
-	   && GET_CODE (SUBREG_REG (XEXP (x, 0))) == CONST_DOUBLE)
-    {
-      union real_extract u;
-
-      if (GET_MODE (SUBREG_REG (XEXP (x, 0))) == SFmode)
-	fprintf (file, "$float");
-      else
-	fprintf (file, "$double%d", SUBREG_WORD (XEXP (x, 0)));
-      bcopy ((char *) &CONST_DOUBLE_LOW (SUBREG_REG (XEXP (x, 0))),
-	     (char *) &u, sizeof u);
-      fprintf (file, "(%.20e)", u.d);
-    }
-
-  else if (GET_CODE (x) == CONST_DOUBLE
-	   && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
-    {
-      union real_extract u;
-
-      bcopy ((char *) &CONST_DOUBLE_LOW (x), (char *) &u, sizeof u);
-      fprintf (file, "$%s(%.20e)",
-	       GET_MODE (x) == SFmode ? "float" : "double0", u.d);
-    }
-
-  else
-    output_addr_const (file, x);
-}
-
-/* This page contains routines to output function prolog and epilog code. */
-
-/* Compute the size of the register stack, and determine if there are any
-   call instructions.  */
-
-static void
-compute_regstack_size ()
-{
-  int i;
-  rtx insn;
-
-  /* See if we make any calls.  We need to set lr1 if so.  */
-  a29k_makes_calls = 0;
-  for (insn = get_insns (); insn; insn = next_insn (insn))
-    if (GET_CODE (insn) == CALL_INSN
-	|| (GET_CODE (insn) == INSN
-	    && GET_CODE (PATTERN (insn)) == SEQUENCE
-	    && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN))
-      {
-	a29k_makes_calls = 1;
-	break;
-      }
-
-  /* Find the highest local register used.  */
-  for (i = R_LR (127); i >= R_LR (0); i--)
-    if (regs_ever_live[i])
-      break;
-
-  a29k_regstack_size = i - (R_LR (0) - 1);
-
-  /* If calling routines, ensure we count lr0 & lr1.  */
-  if (a29k_makes_calls && a29k_regstack_size < 2)
-    a29k_regstack_size = 2;
-
-  /* Count frame pointer and align to 8 byte boundary (even number of
-     registers).  */
-  a29k_regstack_size += frame_pointer_needed;
-  if (a29k_regstack_size & 1) a29k_regstack_size++;
-}
-
-/*  Sets register names for incoming arguments and frame pointer.
-    This can't be computed until after register allocation.  */
-
-void
-a29k_compute_reg_names ()
-{
-  int i;
-
-  compute_regstack_size ();
-
-  /* Set the names and numbers of the frame pointer and incoming argument
-     registers.  */
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    a29k_debug_reg_map[i] = i;
-
-  reg_names[FRAME_POINTER_REGNUM] = reg_names[R_LR (a29k_regstack_size - 1)];
-  a29k_debug_reg_map[FRAME_POINTER_REGNUM] = R_LR (a29k_regstack_size - 1);
-
-  for (i = 0; i < 16; i++)
-    {
-      reg_names[R_AR (i)] = reg_names[R_LR (a29k_regstack_size + i + 2)];
-      a29k_debug_reg_map[R_AR (i)] = R_LR (a29k_regstack_size + i + 2);
-    }
-
-  /* If using kernel register map, swap numbers for kernel and user
-     registers.  */
-  if (TARGET_KERNEL_REGISTERS)
-    for (i = 0; i < 32; i++)
-      {
-	int tem = a29k_debug_reg_map[i];
-	a29k_debug_reg_map[i] = a29k_debug_reg_map[R_KR (i)];
-	a29k_debug_reg_map[R_KR (i)] = tem;
-      }
-}
-
-/* Output function prolog code to file FILE.  Memory stack size is SIZE.  */
-
-void
-output_prolog (file, size)
-     FILE *file;
-     int size;
-{
-  int i;
-  int arg_count = 0;
-  rtx insn;
-  unsigned int tag_word;
-
-  /* See how many incoming arguments we have in registers.  */
-  for (i = R_AR (0); i < R_AR (16); i++)
-    if (! fixed_regs[i])
-      arg_count++;
-
-  /* The argument count includes the caller's lr0 and lr1.  */
-  arg_count += 2;
-
-  /* Compute memory stack size.  Add in number of bytes that the we should
-     push and pretend the caller did and the size of outgoing arguments.
-     Then round to a doubleword boundary.  */
-  size += (current_function_pretend_args_size
-	   + current_function_outgoing_args_size);
-  size = (size + 7) & ~7;
-
-  /* Write header words.  See if one or two word form.  */
-  tag_word = (frame_pointer_needed ? 0x400000 : 0) + (arg_count << 16);
-
-  if (size / 8 > 0xff)
-    fprintf (file, "\t.word %d, 0x%0x\n", (size / 8) << 2,
-	     0x800000 + tag_word);
-  else
-    fprintf (file, "\t.word 0x%0x\n", tag_word + ((size / 8) << 3));
-
-  /* Define the function name.  */
-  assemble_name (file, a29k_function_name);
-  fprintf (file, ":\n");
-
-  /* Push the register stack by the proper amount.  There are two possible
-     ways to do this.  */
-  if (a29k_regstack_size >= 256/4)
-    fprintf (file, "\tconst %s,%d\n\tsub gr1,gr1,%s\n",
-	     reg_names[R_TAV], a29k_regstack_size * 4, reg_names[R_TAV]);
-  else if (a29k_regstack_size)
-    fprintf (file, "\tsub gr1,gr1,%d\n", a29k_regstack_size * 4);
-
-  /* Test that the registers are available.  */
-  if (a29k_regstack_size)
-    fprintf (file, "\tasgeu V_%sSPILL,gr1,%s\n",
-	     TARGET_KERNEL_REGISTERS ? "K" : "", reg_names[R_RAB]);
-
-  /* Set up frame pointer, if one is needed.  */
-  if (frame_pointer_needed)
-    fprintf (file, "\tsll %s,%s,0\n", reg_names[FRAME_POINTER_REGNUM],
-	     reg_names[R_MSP]);
-
-  /* Make room for any frame space.  There are three ways to do this.  */
-  if (size >= 256)
-    {
-      fprintf (file, "\tconst %s,%d\n", reg_names[R_TAV], size);
-      if (size >= 65536)
-	fprintf (file, "\tconsth %s,%d\n", reg_names[R_TAV], size);
-      if (TARGET_STACK_CHECK)
-	fprintf (file, "\tcall %s,__msp_check\n", reg_names[R_TPC]);
-      fprintf (file, "\tsub %s,%s,%s\n",
-	       reg_names[R_MSP], reg_names[R_MSP], reg_names[R_TAV]);
-    }
-  else if (size)
-    {
-      if (TARGET_STACK_CHECK)
-	fprintf (file, "\tcall %s,__msp_check\n", reg_names[R_TPC]);
-      fprintf (file, "\tsub %s,%s,%d\n",
-	       reg_names[R_MSP], reg_names[R_MSP], size);
-    }
-
-  /* If this routine will make calls, set lr1.  If we see an insn that
-     can use a delay slot before a call or jump, save this insn for that
-     slot (this condition is equivalent to seeing if we have an insn that
-     needs delay slots before an insn that has a filled delay slot).  */
-  a29k_last_prologue_insn = 0;
-  if (a29k_makes_calls)
-    {
-      i = (a29k_regstack_size + arg_count) * 4;
-      if (i >= 256)
-	fprintf (file, "\tconst %s,%d\n\tadd lr1,gr1,%s\n",
-		 reg_names[R_TAV], i, reg_names[R_TAV]);
-      else
-	{
-	  if (optimize && flag_delayed_branch)
-	    for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-	      {
-		if (GET_CODE (insn) == CODE_LABEL
-		    || (GET_CODE (insn) == INSN
-			&& GET_CODE (PATTERN (insn)) == SEQUENCE))
-		  break;
-
-		if (GET_CODE (insn) == NOTE
-		    || (GET_CODE (insn) == INSN
-			&& (GET_CODE (PATTERN (insn)) == USE
-			    || GET_CODE (PATTERN (insn)) == CLOBBER)))
-		  continue;
-
-		if (num_delay_slots (insn) > 0)
-		  {
-		    a29k_last_prologue_insn = (char *) oballoc (100);
-		    sprintf (a29k_last_prologue_insn, "add lr1,gr1,%d", i);
-		    break;
-		  }
-	      }
-
-	  if (a29k_last_prologue_insn == 0)
-	    fprintf (file, "\tadd lr1,gr1,%d\n", i);
-	}
-    }
-
-  /* Compute the first insn of the epilogue.  */
-  a29k_first_epilogue_insn_used = 0;
-
-  if (size == 0 && a29k_regstack_size == 0 && ! frame_pointer_needed)
-    a29k_first_epilogue_insn = 0;
-  else
-    a29k_first_epilogue_insn = (char *) oballoc (100);
-
-  if (frame_pointer_needed)
-    sprintf (a29k_first_epilogue_insn, "sll %s,%s,0",
-	     reg_names[R_MSP], reg_names[FRAME_POINTER_REGNUM]);
-  else if (a29k_regstack_size)
-    {
-      if (a29k_regstack_size >= 256 / 4)
-	sprintf (a29k_first_epilogue_insn, "const %s,%d",
-		 reg_names[R_TAV], a29k_regstack_size * 4);
-      else
-	sprintf (a29k_first_epilogue_insn, "add gr1,gr1,%d",
-		 a29k_regstack_size * 4);
-    }
-  else if (size)
-    {
-      if (size >= 256)
-	sprintf (a29k_first_epilogue_insn, "const %s,%d",
-		 reg_names[R_TAV], size);
-      else
-	sprintf (a29k_first_epilogue_insn, "add %s,%s,%d",
-		 reg_names[R_MSP], reg_names[R_MSP], size);
-    }
-}
-
-/* Call this after writing what might be the first instruction of the
-   epilogue.  If that first insn was used in a delay slot, an intermediate
-   label is written.  */
-
-static void
-check_epilogue_internal_label (file)
-     FILE *file;
-{
-  rtx insn;
-
-  if (! a29k_first_epilogue_insn_used)
-    return;
-
-  for (insn = get_last_insn ();
-       GET_CODE (insn) != CODE_LABEL;
-       insn = PREV_INSN (insn))
-    ;
-
-  ASM_OUTPUT_INTERNAL_LABEL (file, "LX", CODE_LABEL_NUMBER (insn));
-  a29k_first_epilogue_insn_used = 0;
-}
-
-/* Output the epilog of the last procedure to file FILE.  SIZE is the memory
-   stack size.  The register stack size is in the variable
-   A29K_REGSTACK_SIZE.  */
-
-void
-output_epilog (file, size)
-     FILE *file;
-     int size;
-{
-  rtx insn;
-  int locals_unavailable = 0;	/* True until after first insn
-				   after gr1 update. */
-
-  /* If we hit a BARRIER before a real insn or CODE_LABEL, we don't
-     need to do anything because we are never jumped to.  */
-  insn = get_last_insn ();
-  if (GET_CODE (insn) == NOTE)
-    insn = prev_nonnote_insn (insn);
-
-  if (insn && GET_CODE (insn) == BARRIER)
-    return;
-
-  /* If a frame pointer was needed we must restore the memory stack pointer
-     before adjusting the register stack.  */
-  if (frame_pointer_needed)
-    {
-      fprintf (file, "\tsll %s,%s,0\n",
-	       reg_names[R_MSP], reg_names[FRAME_POINTER_REGNUM]);
-      check_epilogue_internal_label (file);
-    }
-
-  /* Restore the register stack.  There are two ways to do this.  */
-  if (a29k_regstack_size)
-    {
-      if (a29k_regstack_size >= 256/4)
-	{
-	  fprintf (file, "\tconst %s,%d\n",
-		   reg_names[R_TAV], a29k_regstack_size * 4);
-	  check_epilogue_internal_label (file);
-	  fprintf (file, "\tadd gr1,gr1,%s\n", reg_names[R_TAV]);
-	}
-      else
-	{
-	  fprintf (file, "\tadd gr1,gr1,%d\n", a29k_regstack_size * 4);
-	  check_epilogue_internal_label (file);
-	}
-      locals_unavailable = 1;
-    }
-
-  /* Restore the memory stack pointer if there is no frame pointer.
-     Adjust the size to include any pretend arguments and pushed
-     arguments and round to doubleword boundary.  */
-  size += (current_function_pretend_args_size
-	   + current_function_outgoing_args_size);
-  size = (size + 7) & ~7;
-
-  if (size && ! frame_pointer_needed)
-    {
-      if (size >= 256)
-	{
-	  fprintf (file, "\tconst %s,%d\n", reg_names[R_TAV], size);
-	  check_epilogue_internal_label (file);
-	  locals_unavailable = 0;
-	  if (size >= 65536)
-	    fprintf (file, "\tconsth %s,%d\n", reg_names[R_TAV], size);
-	  fprintf (file, "\tadd %s,%s,%s\n",
-		   reg_names[R_MSP], reg_names[R_MSP], reg_names[R_TAV]);
-	}
-      else
-	{
-	  fprintf (file, "\tadd %s,%s,%d\n",
-		   reg_names[R_MSP], reg_names[R_MSP], size);
-	  check_epilogue_internal_label (file);
-	  locals_unavailable = 0;
-	}
-    }
-
-  if (locals_unavailable)
-    {
-      /* If we have an insn for this delay slot, write it.  */
-      if (current_function_epilogue_delay_list)
-	final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
-			 file, 1, -2, 1);
-      else
-	fprintf (file, "\tnop\n");
-    }
-
-  fprintf (file, "\tjmpi lr0\n");
-  if (a29k_regstack_size)
-    fprintf (file, "\tasleu V_%sFILL,lr1,%s\n",
-	     TARGET_KERNEL_REGISTERS ? "K" : "", reg_names[R_RFB]);
-  else if (current_function_epilogue_delay_list)
-    final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
-		     file, 1, -2, 1);
-  else
-    fprintf (file, "\tnop\n");
-}
diff --git a/gcc/config/a29k/a29k.h b/gcc/config/a29k/a29k.h
deleted file mode 100755
index acff143..0000000
--- a/gcc/config/a29k/a29k.h
+++ /dev/null
@@ -1,1673 +0,0 @@
-/* Definitions of target machine for GNU compiler, for AMD Am29000 CPU.
-   Copyright (C) 1988, 90-97, 1998 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-D_AM29K -D_AM29000 -D_EPI -Acpu(a29k) -Amachine(a29k)"
-
-/* Print subsidiary information on the compiler version in use.  */
-#define TARGET_VERSION
-
-/* Pass -w to assembler.  */
-#define ASM_SPEC "-w"
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-/* This means that the DW bit will be enabled, to allow direct loads
-   of bytes.  */
-
-#define TARGET_DW_ENABLE	(target_flags & 1)
-
-/* This means that the external hardware does supports byte writes.  */
-
-#define TARGET_BYTE_WRITES	(target_flags & 2)
-
-/* This means that a "small memory model" has been selected where all
-   function addresses are known to be within 256K.  This allows CALL to be
-   used.  */
-
-#define TARGET_SMALL_MEMORY	(target_flags & 4)
-
-/* This means that we must always used on indirect call, even when
-   calling a function in the same file, since the file might be > 256KB.  */
-
-#define TARGET_LARGE_MEMORY	(target_flags & 8)
-
-/* This means that we are compiling for a 29050.  */
-
-#define TARGET_29050		(target_flags & 16)
-
-/* This means that we are compiling for the kernel which means that we use
-   gr64-gr95 instead of gr96-126.  */
-
-#define TARGET_KERNEL_REGISTERS	(target_flags & 32)
-
-/* This means that a call to "__msp_check" should be inserted after each stack
-   adjustment to check for stack overflow.  */
-
-#define TARGET_STACK_CHECK	(target_flags & 64)
-
-/* This handles 29k processors which cannot handle the separation
-   of a mtsrim insns and a storem insn (most 29000 chips to date, but
-   not the 29050.  */
-
-#define TARGET_NO_STOREM_BUG	(target_flags & 128)
-
-/* This forces the compiler not to use incoming argument registers except
-   for copying out arguments.  It helps detect problems when a function is
-   called with fewer arguments than it is declared with.  */
-
-#define TARGET_NO_REUSE_ARGS	(target_flags & 256)
-
-/* This means that neither builtin nor emulated float operations are
-   available, and that GCC should generate libcalls instead. */
-
-#define TARGET_SOFT_FLOAT	(target_flags & 512)
-
-/* This means that we should not emit the multm or mutmu instructions
-   that some embedded systems' trap handlers don't support.  */
-
-#define TARGET_MULTM		((target_flags & 1024) == 0)
-
-#define TARGET_SWITCHES			\
-  { {"dw", 1},				\
-    {"ndw", -1},			\
-    {"bw", 2},				\
-    {"nbw", - (1|2)},			\
-    {"small", 4},			\
-    {"normal", - (4|8)},		\
-    {"large", 8},			\
-    {"29050", 16+128},			\
-    {"29000", -16},			\
-    {"kernel-registers", 32},		\
-    {"user-registers", -32},		\
-    {"stack-check", 64},		\
-    {"no-stack-check", - 74},		\
-    {"storem-bug", -128},		\
-    {"no-storem-bug", 128},		\
-    {"reuse-arg-regs", -256},		\
-    {"no-reuse-arg-regs", 256},		\
-    {"soft-float", 512},		\
-    {"no-multm", 1024},			\
-    {"", TARGET_DEFAULT}}
-
-/* CYGNUS LOCAL: reuse-arg-regs bug, see PR 8144 */
-#define TARGET_DEFAULT (3 + 256)
-
-/* Show we can debug even without a frame pointer.  */
-#define CAN_DEBUG_WITHOUT_FP
-
-/* target machine storage layout */
-
-/* Define the types for size_t, ptrdiff_t, and wchar_t.  These are the
-   same as those used by EPI.  The type for wchar_t does not make much
-   sense, but is what is used.  */
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-#define WCHAR_TYPE "char"
-#define WCHAR_TYPE_SIZE BITS_PER_UNIT
-
-/* Define this macro if it is advisable to hold scalars in registers
-   in a wider mode than that declared by the program.  In such cases, 
-   the value is constrained to be within the bounds of the declared
-   type, but kept valid in the wider mode.  The signedness of the
-   extension may differ from that of the type.  */
-
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)  \
-  if (GET_MODE_CLASS (MODE) == MODE_INT	\
-      && GET_MODE_SIZE (MODE) < 4)  	\
-    (MODE) = SImode;
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is arbitrary on the 29k since it has no actual bit-field insns.
-   It is better to define this as TRUE because BYTES_BIG_ENDIAN is TRUE
-   and we want to be able to convert BP position to bit position with
-   just a shift.  */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.
-   This is true on 29k.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered. 
-
-   For 29k we can decide arbitrarily since there are no machine instructions
-   for them.  Might as well be consistent with bytes. */
-#define WORDS_BIG_ENDIAN 1
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 64
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 32
-
-/* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  (TREE_CODE (EXP) == STRING_CST	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Set this non-zero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 0
-
-/* Set this non-zero if unaligned move instructions are extremely slow.
-
-   On the 29k, they trap.  */
-#define SLOW_UNALIGNED_ACCESS 1
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   29k has 256 registers, of which 62 are not defined.  gr0 and gr1 are
-   not produced in generated RTL so we can start at gr96, and call it
-   register zero.
-
-   So 0-31 are gr96-gr127, lr0-lr127 are 32-159.  To represent the input
-   arguments, whose register numbers we won't know until we are done,
-   use register 160-175.  They cannot be modified.  Similarly, 176 is used
-   for the frame pointer.  It is assigned the last local register number
-   once the number of registers used is known.
-
-   We use 177, 178, 179, and 180 for the special registers BP, FC, CR, and Q,
-   respectively.  Registers 181 through 199 are used for the other special
-   registers that may be used by the programmer, but are never used by the
-   compiler.
-
-   Registers 200-203 are the four floating-point accumulator register in
-   the 29050.
-
-   Registers 204-235 are the 32 global registers for kernel mode when
-   -mkernel-registers is not specified, and the 32 global user registers
-   when it is.
-
-   When -mkernel-registers is specified, we still use the same register
-   map but change the names so 0-31 print as gr64-gr95.  */
-
-#define FIRST_PSEUDO_REGISTER 236
-
-/* Because of the large number of registers on the 29k, we define macros
-   to refer to each group of registers and then define the number for some
-   registers used in the calling sequence.  */
-
-#define R_GR(N)		((N) - 96)	/* gr96 is register number 0 */
-#define R_LR(N)		((N) + 32)	/* lr0 is register number 32 */
-#define R_FP		176		/* frame pointer is register 176 */
-#define R_AR(N)		((N) + 160)	/* first incoming arg reg is 160 */
-#define R_KR(N)		((N) + 204)	/* kernel registers (gr64 to gr95) */
-
-/* Define the numbers of the special registers.  */
-#define R_BP	177
-#define R_FC	178
-#define R_CR	179
-#define R_Q	180
-
-/* These special registers are not used by the compiler, but may be referenced
-   by the programmer via asm declarations.  */
-
-#define R_VAB	181
-#define R_OPS	182
-#define R_CPS	183
-#define R_CFG	184
-#define R_CHA	185
-#define R_CHD	186
-#define R_CHC	187
-#define R_RBP	188
-#define R_TMC	189
-#define R_TMR	190
-#define R_PC0	191
-#define R_PC1	192
-#define R_PC2	193
-#define R_MMU	194
-#define R_LRU	195
-#define R_FPE	196
-#define R_INT	197
-#define R_FPS	198
-#define R_EXO	199
-
-/* Define the number for floating-point accumulator N.  */
-#define R_ACU(N)	((N) + 200)
-
-/* Now define the registers used in the calling sequence.  */
-#define R_TAV	R_GR (121)
-#define R_TPC	R_GR (122)
-#define R_LRP	R_GR (123)
-#define R_SLP	R_GR (124)
-#define R_MSP	R_GR (125)
-#define R_RAB	R_GR (126)
-#define R_RFB	R_GR (127)
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.  */
-
-#define FIXED_REGISTERS  \
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
-  0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1,			  \
-  0, 0, 0, 0,					  \
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS  \
- {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1,			  \
-  1, 1, 1, 1,					  \
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
-
-/* List the order in which to allocate registers.  Each register must be
-   listed once, even those in FIXED_REGISTERS.
-
-   We allocate in the following order:
-	gr116-gr120	(not used for anything but temps)
-	gr96-gr111	(function return values, reverse order)
-	argument registers (160-175)
-	lr0-lr127	(locals, saved)
-        acc3-0		(acc0 special)
-	everything else  */
-
-#define REG_ALLOC_ORDER		\
-  {R_GR (116), R_GR (117), R_GR (118), R_GR (119), R_GR (120),		\
-   R_GR (111), R_GR (110), R_GR (109), R_GR (108), R_GR (107),		\
-   R_GR (106), R_GR (105), R_GR (104), R_GR (103), R_GR (102),		\
-   R_GR (101), R_GR (100), R_GR (99), R_GR (98), R_GR (97), R_GR (96),	\
-   R_AR (0), R_AR (1), R_AR (2), R_AR (3), R_AR (4), R_AR (5),		\
-   R_AR (6), R_AR (7), R_AR (8), R_AR (9), R_AR (10), R_AR (11),	\
-   R_AR (12), R_AR (13), R_AR (14), R_AR (15),				\
-   R_LR (0), R_LR (1), R_LR (2), R_LR (3), R_LR (4), R_LR (5),		\
-   R_LR (6), R_LR (7), R_LR (8), R_LR (9), R_LR (10), R_LR (11),	\
-   R_LR (12), R_LR (13), R_LR (14), R_LR (15), R_LR (16), R_LR (17),	\
-   R_LR (18), R_LR (19), R_LR (20), R_LR (21), R_LR (22), R_LR (23),	\
-   R_LR (24), R_LR (25), R_LR (26), R_LR (27), R_LR (28), R_LR (29),	\
-   R_LR (30), R_LR (31), R_LR (32), R_LR (33), R_LR (34), R_LR (35),	\
-   R_LR (36), R_LR (37), R_LR (38), R_LR (39), R_LR (40), R_LR (41),	\
-   R_LR (42), R_LR (43), R_LR (44), R_LR (45), R_LR (46), R_LR (47), 	\
-   R_LR (48), R_LR (49), R_LR (50), R_LR (51), R_LR (52), R_LR (53),	\
-   R_LR (54), R_LR (55), R_LR (56), R_LR (57), R_LR (58), R_LR (59),	\
-   R_LR (60), R_LR (61), R_LR (62), R_LR (63), R_LR (64), R_LR (65),	\
-   R_LR (66), R_LR (67), R_LR (68), R_LR (69), R_LR (70), R_LR (71),	\
-   R_LR (72), R_LR (73), R_LR (74), R_LR (75), R_LR (76), R_LR (77),	\
-   R_LR (78), R_LR (79), R_LR (80), R_LR (81), R_LR (82), R_LR (83),	\
-   R_LR (84), R_LR (85), R_LR (86), R_LR (87), R_LR (88), R_LR (89),	\
-   R_LR (90), R_LR (91), R_LR (92), R_LR (93), R_LR (94), R_LR (95),	\
-   R_LR (96), R_LR (97), R_LR (98), R_LR (99), R_LR (100), R_LR (101),	\
-   R_LR (102), R_LR (103), R_LR (104), R_LR (105), R_LR (106),		\
-   R_LR (107), R_LR (108), R_LR (109), R_LR (110), R_LR (111),		\
-   R_LR (112), R_LR (113), R_LR (114), R_LR (115), R_LR (116),		\
-   R_LR (117), R_LR (118), R_LR (119), R_LR (120), R_LR (121),		\
-   R_LR (122), R_LR (123), R_LR (124), R_LR (124), R_LR (126),		\
-   R_LR (127),								\
-   R_ACU (3), R_ACU (2), R_ACU (1), R_ACU (0),				\
-   R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (121),		\
-   R_GR (122), R_GR (123), R_GR (124), R_GR (125), R_GR (126),		\
-   R_GR (127),								\
-   R_FP, R_BP, R_FC, R_CR, R_Q,						\
-   R_VAB, R_OPS, R_CPS, R_CFG, R_CHA, R_CHD, R_CHC, R_RBP, R_TMC,	\
-   R_TMR, R_PC0, R_PC1, R_PC2, R_MMU, R_LRU, R_FPE, R_INT, R_FPS,	\
-   R_EXO,								\
-   R_KR (0), R_KR (1), R_KR (2), R_KR (3), R_KR (4), R_KR (5), 		\
-   R_KR (6), R_KR (7), R_KR (8), R_KR (9), R_KR (10), R_KR (11),	\
-   R_KR (12), R_KR (13), R_KR (14), R_KR (15), R_KR (16), R_KR (17),	\
-   R_KR (18), R_KR (19), R_KR (20), R_KR (21), R_KR (22), R_KR (23),	\
-   R_KR (24), R_KR (25), R_KR (26), R_KR (27), R_KR (28), R_KR (29),	\
-   R_KR (30), R_KR (31) }
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((REGNO) >= R_ACU (0) && (REGNO) <= R_ACU (3)? 1		\
-   : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On 29k, the cpu registers can hold any mode.  But a double-precision
-   floating-point value should start at an even register.  The special
-   registers cannot hold floating-point values, BP, CR, and FC cannot
-   hold integer or floating-point values,  and the accumulators cannot
-   hold integer values.
-
-   DImode and larger values should start at an even register just like
-   DFmode values, even though the instruction set doesn't require it, in order
-   to prevent reload from aborting due to a modes_equiv_for_class_p failure.
-
-   (I'd like to use the "?:" syntax to make this more readable, but Sun's
-   compiler doesn't seem to accept it.)  */
-#define HARD_REGNO_MODE_OK(REGNO, MODE)  				\
-(((REGNO) >= R_ACU (0) && (REGNO) <= R_ACU (3)				\
-    && (GET_MODE_CLASS (MODE) == MODE_FLOAT				\
-	|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT))		\
-   || ((REGNO) >= R_BP && (REGNO) <= R_CR				\
-       && GET_MODE_CLASS (MODE) == MODE_PARTIAL_INT)			\
-   || ((REGNO) >= R_Q && (REGNO) < R_ACU (0)				\
-       && GET_MODE_CLASS (MODE) != MODE_FLOAT				\
-       && GET_MODE_CLASS (MODE) != MODE_COMPLEX_FLOAT)			\
-   || (((REGNO) < R_BP || (REGNO) >= R_KR (0))				 \
-       && ((((REGNO) & 1) == 0)						\
-	   || GET_MODE_UNIT_SIZE (MODE) <= UNITS_PER_WORD)))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.
-
-   On the 29k, normally we'd just have problems with DFmode because of the
-   even alignment.  However, we also have to be a bit concerned about
-   the special register's restriction to non-floating and the floating-point
-   accumulator's restriction to only floating.  This probably won't
-   cause any great inefficiencies in practice.  */
-
-#define MODES_TIEABLE_P(MODE1, MODE2)			\
-  ((MODE1) == (MODE2)					\
-   || (GET_MODE_CLASS (MODE1) == MODE_INT		\
-       && GET_MODE_CLASS (MODE2) == MODE_INT))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* 29k pc isn't overloaded on a register that the compiler knows about.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM R_GR (125)
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM R_FP
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM R_FP
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM R_SLP
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM R_LRP
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.
-   
-   The 29k has nine registers classes: LR0_REGS, GENERAL_REGS, SPECIAL_REGS,
-   BP_REGS, FC_REGS, CR_REGS, Q_REGS, ACCUM_REGS, and ACCUM0_REGS.
-   LR0_REGS, BP_REGS, FC_REGS, CR_REGS, and Q_REGS contain just the single
-   register.  The latter two classes are used to represent the floating-point
-   accumulator registers in the 29050.  We also define the union class
-   FLOAT_REGS to represent any register that can be used to hold a
-   floating-point value.  The union of SPECIAL_REGS and ACCUM_REGS isn't
-   useful as the former cannot contain floating-point and the latter can only
-   contain floating-point.  */
-
-enum reg_class { NO_REGS, LR0_REGS, GENERAL_REGS, BP_REGS, FC_REGS, CR_REGS,
-		 Q_REGS, SPECIAL_REGS, ACCUM0_REGS, ACCUM_REGS, FLOAT_REGS,
-		 ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES				\
- {"NO_REGS", "LR0_REGS", "GENERAL_REGS", "BP_REGS", "FC_REGS", "CR_REGS", \
-  "Q_REGS", "SPECIAL_REGS", "ACCUM0_REGS", "ACCUM_REGS", "FLOAT_REGS",    \
-  "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS	\
-  { {0, 0, 0, 0, 0, 0, 0, 0}, 				   \
-    {0, 1, 0, 0, 0, 0, 0, 0},				   \
-    {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xfff, 0xfff},	   \
-    {0, 0, 0, 0, 0, 0x20000, 0, 0}, 			   \
-    {0, 0, 0, 0, 0, 0x40000, 0, 0}, 			   \
-    {0, 0, 0, 0, 0, 0x80000, 0, 0}, 			   \
-    {0, 0, 0, 0, 0, 0x100000, 0, 0}, 			   \
-    {0, 0, 0, 0, 0, 0xfffe0000, 0xff, 0},		   \
-    {0, 0, 0, 0, 0, 0, 0x100, 0},			   \
-    {0, 0, 0, 0, 0, 0, 0xf00, 0},			   \
-    {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xff, 0xfff}, 	   \
-    {~0, ~0, ~0, ~0, ~0, ~0, ~0, 0xfff} }
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO)		\
-  ((REGNO) == R_BP ? BP_REGS		\
-   : (REGNO) == R_FC ? FC_REGS		\
-   : (REGNO) == R_CR ? CR_REGS		\
-   : (REGNO) == R_Q ? Q_REGS		\
-   : (REGNO) > R_BP && (REGNO) <= R_EXO ? SPECIAL_REGS	\
-   : (REGNO) == R_ACU (0) ? ACCUM0_REGS	\
-   : (REGNO) >= R_KR (0) ? GENERAL_REGS \
-   : (REGNO) > R_ACU (0) ? ACCUM_REGS	\
-   : (REGNO) == R_LR (0) ? LR0_REGS	\
-   : GENERAL_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS NO_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C)	\
- ((C) == 'r' ? GENERAL_REGS		\
-  : (C) == 'l' ? LR0_REGS		\
-  : (C) == 'b' ? BP_REGS		\
-  : (C) == 'f' ? FC_REGS		\
-  : (C) == 'c' ? CR_REGS		\
-  : (C) == 'q' ? Q_REGS			\
-  : (C) == 'h' ? SPECIAL_REGS		\
-  : (C) == 'a' ? ACCUM_REGS		\
-  : (C) == 'A' ? ACCUM0_REGS		\
-  : (C) == 'f' ? FLOAT_REGS		\
-  : NO_REGS)
-
-/* Define this macro to change register usage conditional on target flags.
-
-   On the 29k, we use this to change the register names for kernel mapping.  */
-
-#define CONDITIONAL_REGISTER_USAGE		\
-  {						\
-    char *p;					\
-    int i;					\
-						\
-    if (TARGET_KERNEL_REGISTERS)		\
-      for (i = 0; i < 32; i++)			\
-	{					\
-	  p = reg_names[i];			\
-	  reg_names[i] = reg_names[R_KR (i)];	\
-	  reg_names[R_KR (i)] = p;		\
-	}					\
-  }
-
-/* The letters I, J, K, L, M, N, O, and P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   For 29k:
-   `I' is used for the range of constants most insns can contain.
-   `J' is for the few 16-bit insns.
-   `K' is a constant whose high-order 24 bits are all one
-   `L' is a HImode constant whose high-order 8 bits are all one
-   `M' is a 32-bit constant whose high-order 16 bits are all one (for CONSTN)
-   `N' is a 32-bit constant whose negative is 8 bits
-   `O' is the 32-bit constant 0x80000000, any constant with low-order
-          16 bits zero for 29050.
-   `P' is a HImode constant whose negative is 8 bits  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)				\
-  ((C) == 'I' ? (unsigned) (VALUE) < 0x100			\
-   : (C) == 'J' ? (unsigned) (VALUE) < 0x10000			\
-   : (C) == 'K' ? ((VALUE) & 0xffffff00) == 0xffffff00		\
-   : (C) == 'L' ? ((VALUE) & 0xff00) == 0xff00			\
-   : (C) == 'M' ? ((VALUE) & 0xffff0000) == 0xffff0000		\
-   : (C) == 'N' ? ((VALUE) < 0 && (VALUE) > -256)		\
-   : (C) == 'O' ? ((VALUE) == 0x80000000			\
-		   || (TARGET_29050 && ((VALUE) & 0xffff) == 0)) \
-   : (C) == 'P' ? (((VALUE) | 0xffff0000) < 0			\
-		   && ((VALUE) | 0xffff0000) > -256)		\
-   : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.
-   All floating-point constants are valid on 29k.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  1
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)	CLASS
-
-/* Return the register class of a scratch register needed to copy IN into
-   or out of a register in CLASS in MODE.  If it can be done directly,
-   NO_REGS is returned.  */
-
-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
-  secondary_reload_class (CLASS, MODE, IN)
-
-/* This function is used to get the address of an object.  */
-
-extern struct rtx_def *a29k_get_reloaded_address ();
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.
-
-   On 29k, this is the size of MODE in words except that the floating-point
-   accumulators only require one word for anything they can hold.  */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)				\
- (((CLASS) == ACCUM_REGS || (CLASS) == ACCUM0_REGS) ? 1		\
-  : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Define the cost of moving between registers of various classes.  Everything
-   involving a general register is cheap, but moving between the other types
-   (even within a class) is two insns.  */
-
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)	\
-  ((CLASS1) == GENERAL_REGS || (CLASS2) == GENERAL_REGS ? 2 : 4)
-
-/* A C expressions returning the cost of moving data of MODE from a register to
-   or from memory.
-
-   It takes extra insns on the 29k to form addresses, so we want to make
-   this higher.  In addition, we need to keep it more expensive than the
-   most expensive register-register copy.  */
-
-#define MEMORY_MOVE_COST(MODE,CLASS,IN) 6
-
-/* A C statement (sans semicolon) to update the integer variable COST
-   based on the relationship between INSN that is dependent on
-   DEP_INSN through the dependence LINK.  The default is to make no
-   adjustment to COST.  On the a29k, ignore the cost of anti- and
-   output-dependencies.  */
-#define ADJUST_COST(INSN,LINK,DEP_INSN,COST)				\
-  if (REG_NOTE_KIND (LINK) != 0)					\
-    (COST) = 0; /* Anti or output dependence.  */
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-
-#define STARTING_FRAME_OFFSET (- current_function_pretend_args_size)
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On 29k, don't define this because there are no push insns.  */
-/*  #define PUSH_ROUNDING(BYTES) */
-
-/* Define this if the maximum size of all the outgoing args is to be
-   accumulated and pushed during the prologue.  The amount can be
-   found in the variable current_function_outgoing_args_size.  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Offset of first parameter from the argument pointer register value.  */
-
-#define FIRST_PARM_OFFSET(FNDECL) (- current_function_pretend_args_size)
-
-/* Define this if stack space is still allocated for a parameter passed
-   in a register.  */
-/* #define REG_PARM_STACK_SPACE */
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.
-
-   On 29k the value is found in gr96.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), R_GR (96))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, R_GR (96))
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.
-   On 29k, gr96-gr111 are used.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == R_GR (96))
-
-/* 1 if N is a possible register number for function argument passing.
-   On 29k, these are lr2-lr17.  */
-
-#define FUNCTION_ARG_REGNO_P(N) ((N) <= R_LR (17) && (N) >= R_LR (2))
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On 29k, this is a single integer, which is a number of words
-   of arguments scanned so far.
-   Thus 16 or more means all following args should go on the stack.  */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)  (CUM) = 0
-
-/* Same, but called for incoming args.
-
-   On the 29k, we use this to set all argument registers to fixed and
-   set the last 16 local regs, less two, (lr110-lr125) to available.  Some
-   will later be changed to call-saved by FUNCTION_INCOMING_ARG.
-   lr126,lr127 are always fixed, they are place holders for the caller's
-   lr0,lr1.  */
-
-#define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE)	\
-{ int i;							\
-  for (i = R_AR (0) - 2; i < R_AR (16); i++)			\
-    {								\
-      fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; \
-      SET_HARD_REG_BIT (fixed_reg_set, i);			\
-      SET_HARD_REG_BIT (call_used_reg_set, i);			\
-      SET_HARD_REG_BIT (call_fixed_reg_set, i);			\
-    }								\
-  for (i = R_LR (110); i < R_LR (126); i++)					\
-    {								\
-      fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 0; \
-      CLEAR_HARD_REG_BIT (fixed_reg_set, i);			\
-      CLEAR_HARD_REG_BIT (call_used_reg_set, i);		\
-      CLEAR_HARD_REG_BIT (call_fixed_reg_set, i);		\
-    }								\
-  (CUM) = 0;							\
- }
-
-/* Define intermediate macro to compute the size (in registers) of an argument
-   for the 29k.  */
-
-#define A29K_ARG_SIZE(MODE, TYPE, NAMED)				\
-(! (NAMED) ? 0								\
- : (MODE) != BLKmode							\
- ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD 	\
- : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
-  if (MUST_PASS_IN_STACK (MODE, TYPE))					\
-    (CUM) = 16;								\
-  else									\
-    (CUM) += A29K_ARG_SIZE (MODE, TYPE, NAMED)
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-
-   On 29k the first 16 words of args are normally in registers
-   and the rest are pushed.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)			\
-((CUM) < 16 && (NAMED) && ! MUST_PASS_IN_STACK (MODE, TYPE)	\
- ? gen_rtx(REG, (MODE), R_LR (2) + (CUM)) : 0)
-
-/* Define where a function finds its arguments.
-   This is different from FUNCTION_ARG because of register windows.
-
-   On the 29k, we hack this to call a function that sets the used registers
-   as non-fixed and not used by calls.  */
-
-#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED)			\
-((CUM) < 16 && (NAMED) && ! MUST_PASS_IN_STACK (MODE, TYPE)		\
- ? gen_rtx (REG, MODE,							\
-	    incoming_reg (CUM, A29K_ARG_SIZE (MODE, TYPE, NAMED)))	\
- : 0)
-
-/* This indicates that an argument is to be passed with an invisible reference
-   (i.e., a pointer to the object is passed).
-
-   On the 29k, we do this if it must be passed on the stack.  */
-
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)	\
-  (MUST_PASS_IN_STACK (MODE, TYPE))
-
-/* Specify the padding direction of arguments.
-
-   On the 29k, we must pad upwards in order to be able to pass args in
-   registers.  */
-
-#define FUNCTION_ARG_PADDING(MODE, TYPE)	upward
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)		\
-((CUM) < 16 && 16 < (CUM) + A29K_ARG_SIZE (MODE, TYPE, NAMED) && (NAMED) \
- ? 16 - (CUM) : 0)
-
-/* Perform any needed actions needed for a function that is receiving a
-   variable number of arguments. 
-
-   CUM is as above.
-
-   MODE and TYPE are the mode and type of the current parameter.
-
-   PRETEND_SIZE is a variable that should be set to the amount of stack
-   that must be pushed by the prolog to pretend that our caller pushed
-   it.
-
-   Normally, this macro will push all remaining incoming registers on the
-   stack and set PRETEND_SIZE to the length of the registers pushed.  */
-
-#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
-{ if ((CUM) < 16)							\
-    {									\
-      int first_reg_offset = (CUM);					\
-									\
-      if (MUST_PASS_IN_STACK (MODE, TYPE))				\
-	first_reg_offset += A29K_ARG_SIZE (TYPE_MODE (TYPE), TYPE, 1);	\
-									\
-      if (first_reg_offset > 16)					\
-	first_reg_offset = 16;						\
-									\
-      if (! (NO_RTL) && first_reg_offset != 16)				\
-	move_block_from_reg						\
-	  (R_AR (0) + first_reg_offset,					\
-	   gen_rtx (MEM, BLKmode, virtual_incoming_args_rtx),		\
-	   16 - first_reg_offset, (16 - first_reg_offset) * UNITS_PER_WORD); \
-      PRETEND_SIZE = (16 - first_reg_offset) * UNITS_PER_WORD;		\
-    }									\
-}
-
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  Note that we can't use "rtx" here
-   since it hasn't been defined!  */
-
-extern struct rtx_def *a29k_compare_op0, *a29k_compare_op1;
-extern int a29k_compare_fp_p;
-
-/* This macro produces the initial definition of a function name.
-
-   For the 29k, we need the prolog to contain one or two words prior to
-   the declaration of the function name.  So just store away the name and
-   write it as part of the prolog.  This also computes the register names,
-   which can't be done until after register allocation, but must be done
-   before final_start_function is called.  */
-
-extern char *a29k_function_name;
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL)	\
-  a29k_function_name = NAME; \
-  a29k_compute_reg_names ();
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)  output_prolog (FILE, SIZE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE)	output_epilog (FILE, SIZE)
-
-/* Define the number of delay slots needed for the function epilogue.
-
-   On the 29k, we need a slot except when we have a register stack adjustment,
-   have a memory stack adjustment, and have no frame pointer.  */
-
-#define DELAY_SLOTS_FOR_EPILOGUE 					\
-  (! (needs_regstack_p ()						\
-      && (get_frame_size () + current_function_pretend_args_size	\
-	   + current_function_outgoing_args_size) != 0			\
-      && ! frame_pointer_needed))
-
-/* Define whether INSN can be placed in delay slot N for the epilogue.
-
-   On the 29k, we must be able to place it in a delay slot, it must
-   not use sp if the frame pointer cannot be eliminated, and it cannot
-   use local regs if we need to push the register stack.
-   If this is a SET with a memory as source, it might load from
-   a stack slot, unless the address is constant.  */
-
-#define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N)				\
-  (get_attr_in_delay_slot (INSN) == IN_DELAY_SLOT_YES			\
-   && ! (frame_pointer_needed						\
-	 && reg_mentioned_p (stack_pointer_rtx, PATTERN (INSN)))	\
-   && ! (needs_regstack_p () && uses_local_reg_p (PATTERN (INSN)))	\
-   && (GET_CODE (PATTERN (INSN)) != SET					\
-       || GET_CODE (SET_SRC (PATTERN (INSN))) != MEM			\
-       || ! rtx_varies_p (XEXP (SET_SRC (PATTERN (INSN)), 0))))
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.
-
-   The trampoline should set the static chain pointer to value placed
-   into the trampoline and should branch to the specified routine.  We
-   use gr121 (tav) as a temporary.  */
-
-#define TRAMPOLINE_TEMPLATE(FILE)			\
-{							\
-  fprintf (FILE, "\tconst %s,0\n", reg_names[R_TAV]);	\
-  fprintf (FILE, "\tconsth %s,0\n", reg_names[R_TAV]);	\
-  fprintf (FILE, "\tconst %s,0\n", reg_names[R_SLP]);	\
-  fprintf (FILE, "\tjmpi %s\n", reg_names[R_TAV]);	\
-  fprintf (FILE, "\tconsth %s,0\n", reg_names[R_SLP]);	\
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE    20
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.
-
-   We do this on the 29k by writing the bytes of the addresses into the
-   trampoline one byte at a time.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  INITIALIZE_TRAMPOLINE_VALUE (TRAMP, FNADDR, 0, 4);			\
-  INITIALIZE_TRAMPOLINE_VALUE (TRAMP, CXT, 8, 16);			\
-}
-
-/* Define a sub-macro to initialize one value into the trampoline.
-   We specify the offsets of the CONST and CONSTH instructions, respectively
-   and copy the value a byte at a time into these instructions.  */
-
-#define INITIALIZE_TRAMPOLINE_VALUE(TRAMP, VALUE, CONST, CONSTH)	\
-{									\
-  rtx _addr, _temp;							\
-  rtx _val = force_reg (SImode, VALUE);					\
-									\
-  _addr = memory_address (QImode, plus_constant (TRAMP, (CONST) + 3));	\
-  emit_move_insn (gen_rtx (MEM, QImode, _addr),				\
-		  gen_lowpart (QImode, _val));				\
-									\
-  _temp = expand_shift (RSHIFT_EXPR, SImode, _val,			\
-		       build_int_2 (8, 0), 0, 1);			\
-  _addr = memory_address (QImode, plus_constant (TRAMP, (CONST) + 1));	\
-  emit_move_insn (gen_rtx (MEM, QImode, _addr),				\
-		  gen_lowpart (QImode, _temp));				\
-									\
-  _temp = expand_shift (RSHIFT_EXPR, SImode, _temp,			\
-		       build_int_2 (8, 0), _temp, 1);			\
-  _addr = memory_address (QImode, plus_constant (TRAMP, (CONSTH) + 3));	\
-  emit_move_insn (gen_rtx (MEM, QImode, _addr),				\
-		  gen_lowpart (QImode, _temp));				\
-									\
-  _temp = expand_shift (RSHIFT_EXPR, SImode, _temp,			\
-		       build_int_2 (8, 0), _temp, 1);			\
-  _addr = memory_address (QImode, plus_constant (TRAMP, (CONSTH) + 1));	\
-  emit_move_insn (gen_rtx (MEM, QImode, _addr),				\
-		  gen_lowpart (QImode, _temp));				\
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) 0
-#define REGNO_OK_FOR_BASE_P(REGNO) 1
-
-/* Given the value returned from get_frame_size, compute the actual size
-   of the frame we will allocate.   We include the pretend and outgoing
-   arg sizes and round to a doubleword.  */
-
-#define ACTUAL_FRAME_SIZE(SIZE)				\
-  (((SIZE) + current_function_pretend_args_size		\
-    + current_function_outgoing_args_size + 7) & ~7)
-
-/* Define the initial offset between the frame and stack pointer.  */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)	\
-  (DEPTH) = ACTUAL_FRAME_SIZE (get_frame_size ())
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-#define MAX_REGS_PER_ADDRESS 1
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)  \
-(GET_CODE (X) == CONST_INT && (unsigned) INTVAL (X) < 0x100)
-
-/* Include all constant integers and constant doubles */
-#define LEGITIMATE_CONSTANT_P(X)	1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) 0
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X)  1
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   On the 29k, a legitimate address is a register and so is a
-   constant of less than 256.  */
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
-{ if (REG_P (X) && REG_OK_FOR_BASE_P (X))	\
-    goto ADDR;					\
-  if (GET_CODE (X) == CONST_INT			\
-      && (unsigned) INTVAL (X) < 0x100)		\
-    goto ADDR;					\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the 29k, we need not do anything.  However, if we don't,
-   `memory_address' will try lots of things to get a valid address, most of
-   which will result in dead code and extra pseudos.  So we make the address
-   valid here.
-
-   This is easy:  The only valid addresses are an offset from a register
-   and we know the address isn't valid.  So just call either `force_operand'
-   or `force_reg' unless this is a (plus (reg ...) (const_int 0)).  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)			\
-{ if (GET_CODE (X) == PLUS && XEXP (X, 1) == const0_rtx)	\
-    X = XEXP (x, 0);						\
-  if (GET_CODE (X) == MULT || GET_CODE (X) == PLUS)		\
-    X = force_operand (X, 0);					\
-  else								\
-    X = force_reg (Pmode, X);					\
-  goto WIN;							\
-}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the 29k this is never true.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-/* Compute the cost of an address.  For the 29k, all valid addresses are
-   the same cost.  */
-
-#define ADDRESS_COST(X)  0
-
-/* Define this if some processing needs to be done immediately before
-   emitting code for an insn.  */
-
-/* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.
-
-   We actually lie a bit here as overflow conditions are different.  But
-   they aren't being checked anyway.  */
-
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move to of from memory
-   in one reasonably fast instruction.
-
-   For the 29k, we will define movti, so put this at 4 words.  */
-#define MOVE_MAX 16
-
-/* Largest number of bytes of an object that can be placed in a register.
-   On the 29k we have plenty of registers, so use TImode.  */
-#define MAX_FIXED_MODE_SIZE	GET_MODE_BITSIZE (TImode)
-
-/* Nonzero if access to memory by bytes is no faster than for words.
-   Also non-zero if doing byte operations (specifically shifts) in registers
-   is undesirable. 
-
-   On the 29k, large masks are expensive, so we want to use bytes to
-   manipulate fields.  */
-#define SLOW_BYTE_ACCESS	0
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.  */
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* Define if the object format being used is COFF or a superset.  */
-#define OBJECT_FORMAT_COFF
-
-/* This uses COFF, so it wants SDB format.  */
-#define SDB_DEBUGGING_INFO
-
-/* Define this to be the delimiter between SDB sub-sections.  The default
-   is ";".  */
-#define SDB_DELIM	"\n"
-
-/* Do not break .stabs pseudos into continuations.  */
-#define DBX_CONTIN_LENGTH 0
-
-/* Don't try to use the `x' type-cross-reference character in DBX data.
-   Also has the consequence of putting each struct, union or enum
-   into a separate .stabs, containing only cross-refs to the others.  */
-#define DBX_NO_XREFS
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true, which
-   is just the sign bit.  */
-
-#define STORE_FLAG_VALUE (-2147483647 - 1)
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* Mode of a function address in a call instruction (for indexing purposes).
-
-   Doesn't matter on 29k.  */
-#define FUNCTION_MODE SImode
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.  */
-#define NO_FUNCTION_CSE
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
-   few bits. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.
-
-   We only care about the cost if it is valid in an insn.  The only
-   constants that cause an insn to generate more than one machine
-   instruction are those involving floating-point or address.  So 
-   only these need be expensive.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    return 0;							\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 6;							\
-  case CONST_DOUBLE:						\
-    return GET_MODE (RTX) == SFmode ? 6 : 8;
-    
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.
-
-   All MEMs cost the same if they are valid.  This is used to ensure
-   that (mem (symbol_ref ...)) is placed into a CALL when valid.
-
-   The multiply cost depends on whether this is a 29050 or not.  */
-
-#define RTX_COSTS(X,CODE,OUTER_CODE)			\
-  case MULT:						\
-    return TARGET_29050 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (40);  \
-  case DIV:						\
-  case UDIV:						\
-  case MOD:						\
-  case UMOD:						\
-    return COSTS_N_INSNS (50);				\
-  case MEM:						\
-    return COSTS_N_INSNS (2);
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(FILE)					\
-{ char *p, *after_dir = main_input_filename;			\
-  if (TARGET_29050)						\
-    fprintf (FILE, "\t.cputype 29050\n");			\
-  for (p = main_input_filename; *p; p++)			\
-    if (*p == '/')						\
-      after_dir = p + 1;					\
-  fprintf (FILE, "\t.file ");					\
-  output_quoted_string (FILE, after_dir);			\
-  fprintf (FILE, "\n");						\
-  fprintf (FILE, "\t.sect .lit,lit\n"); }
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-
-/* The next few macros don't have tabs on most machines, but
-   at least one 29K assembler wants them.  */
-
-/* Output before instructions.  */
-
-#define TEXT_SECTION_ASM_OP "\t.text"
-
-/* Output before read-only data.  */
-
-#define READONLY_DATA_SECTION_ASM_OP "\t.use .lit"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP "\t.data"
-
-/* Define an extra section for read-only data, a routine to enter it, and
-   indicate that it is for read-only data.  */
-
-#define EXTRA_SECTIONS	readonly_data
-
-#define EXTRA_SECTION_FUNCTIONS					\
-void								\
-literal_section ()						\
-{								\
-  if (in_section != readonly_data)				\
-    {								\
-      fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
-      in_section = readonly_data;				\
-    }								\
-}								\
-
-#define READONLY_DATA_SECTION	literal_section
-
-/* If we are referencing a function that is static or is known to be
-   in this file, make the SYMBOL_REF special.  We can use this to indicate
-   that we can branch to this function without emitting a no-op after the
-   call.  */
-
-#define ENCODE_SECTION_INFO(DECL)  \
-  if (TREE_CODE (DECL) == FUNCTION_DECL			\
-      && (TREE_ASM_WRITTEN (DECL) || ! TREE_PUBLIC (DECL))) \
-    SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"gr96", "gr97", "gr98", "gr99", "gr100", "gr101", "gr102", "gr103", "gr104", \
- "gr105", "gr106", "gr107", "gr108", "gr109", "gr110", "gr111", "gr112", \
- "gr113", "gr114", "gr115", "gr116", "gr117", "gr118", "gr119", "gr120", \
- "gr121", "gr122", "gr123", "gr124", "gr125", "gr126", "gr127",		 \
- "lr0", "lr1", "lr2", "lr3", "lr4", "lr5", "lr6", "lr7", "lr8", "lr9",   \
- "lr10", "lr11", "lr12", "lr13", "lr14", "lr15", "lr16", "lr17", "lr18", \
- "lr19", "lr20", "lr21", "lr22", "lr23", "lr24", "lr25", "lr26", "lr27", \
- "lr28", "lr29", "lr30", "lr31", "lr32", "lr33", "lr34", "lr35", "lr36", \
- "lr37", "lr38", "lr39", "lr40", "lr41", "lr42", "lr43", "lr44", "lr45", \
- "lr46", "lr47", "lr48", "lr49", "lr50", "lr51", "lr52", "lr53", "lr54", \
- "lr55", "lr56", "lr57", "lr58", "lr59", "lr60", "lr61", "lr62", "lr63", \
- "lr64", "lr65", "lr66", "lr67", "lr68", "lr69", "lr70", "lr71", "lr72", \
- "lr73", "lr74", "lr75", "lr76", "lr77", "lr78", "lr79", "lr80", "lr81", \
- "lr82", "lr83", "lr84", "lr85", "lr86", "lr87", "lr88", "lr89", "lr90", \
- "lr91", "lr92", "lr93", "lr94", "lr95", "lr96", "lr97", "lr98", "lr99", \
- "lr100", "lr101", "lr102", "lr103", "lr104", "lr105", "lr106", "lr107", \
- "lr108", "lr109", "lr110", "lr111", "lr112", "lr113", "lr114", "lr115", \
- "lr116", "lr117", "lr118", "lr119", "lr120", "lr121", "lr122", "lr123", \
- "lr124", "lr125", "lr126", "lr127",					 \
-  "AI0", "AI1", "AI2", "AI3", "AI4", "AI5", "AI6", "AI7", "AI8", "AI9",  \
-  "AI10", "AI11", "AI12", "AI13", "AI14", "AI15", "FP",			 \
-  "bp", "fc", "cr", "q",						 \
-  "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr",	 \
-  "pc0", "pc1", "pc2", "mmu", "lru", "fpe", "int", "fps", "exo",	 \
-  "0", "1", "2", "3",							 \
-  "gr64", "gr65", "gr66", "gr67", "gr68", "gr69", "gr70", "gr71",	 \
-  "gr72", "gr73", "gr74", "gr75", "gr76", "gr77", "gr78", "gr79",	 \
-  "gr80", "gr81", "gr82", "gr83", "gr84", "gr85", "gr86", "gr87",	 \
-  "gr88", "gr89", "gr90", "gr91", "gr92", "gr93", "gr94", "gr95" }
-
-/* How to renumber registers for dbx and gdb.  */
-
-extern int a29k_debug_reg_map[];
-#define DBX_REGISTER_NUMBER(REGNO) a29k_debug_reg_map[REGNO]
-
-/* This how to write an assembler directive to FILE to switch to
-   section NAME for DECL.  */
-
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
-  fprintf (FILE, "\t.sect %s, bss\n\t.use %s\n", NAME, NAME)
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to output a label for a jump table.  Arguments are the same as
-   for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
-   passed. */
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN)	\
-{ ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)		\
-  fprintf (FILE, "\t.double %.20e\n", (VALUE))
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)		\
-  fprintf (FILE, "\t.float %.20e\n", (VALUE))
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.hword "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)					\
-  fprintf (FILE, "\tsub %s,%s,4\n\tstore 0,0,%s,%s\n",			\
-           reg_names[R_MSP], reg_names[R_MSP], reg_names[REGNO],	\
-	   reg_names[R_MSP]);
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)					\
-  fprintf (FILE, "\tload 0,0,%s,%s\n\tadd %s,%s,4\n",			\
-           reg_names[REGNO], reg_names[R_MSP], reg_names[R_MSP],	\
-	   reg_names[R_MSP]);
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.word L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.
-   Don't define this if it is not supported. */
-
-/* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", 1 << (LOG))
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.block %d\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\t.comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED)	\
-( fputs ("\t.lcomm ", (FILE)),				\
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand (FILE, X, CODE)
-
-/* Determine which codes are valid without a following integer.  These must
-   not be alphabetic.
-
-   We support `#' which is null if a delay slot exists, otherwise
-   "\n\tnop" and `*' which prints the register name for TPC (gr122).  */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#' || (CODE) == '*')
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx addr = ADDR;					\
-  if (!REG_P (addr)						\
-      && ! (GET_CODE (addr) == CONST_INT			\
-	    && INTVAL (addr) >= 0 && INTVAL (addr) < 256))	\
-    abort ();							\
-  output_operand (addr, 0);					\
-}
-/* Define the codes that are matched by predicates in a29k.c.  */
-
-#define PREDICATE_CODES \
-  {"cint_8_operand", {CONST_INT}},				\
-  {"cint_16_operand", {CONST_INT}},				\
-  {"long_const_operand", {CONST_INT, CONST, CONST_DOUBLE,	\
-			  LABEL_REF, SYMBOL_REF}},		\
-  {"shift_constant_operand", {CONST_INT, ASHIFT}},		\
-  {"const_0_operand", {CONST_INT, ASHIFT}},			\
-  {"const_8_operand", {CONST_INT, ASHIFT}},			\
-  {"const_16_operand", {CONST_INT, ASHIFT}},			\
-  {"const_24_operand", {CONST_INT, ASHIFT}},			\
-  {"float_const_operand", {CONST_DOUBLE}},			\
-  {"gpc_reg_operand", {SUBREG, REG}},				\
-  {"gpc_reg_or_float_constant_operand", {SUBREG, REG, CONST_DOUBLE}}, \
-  {"gpc_reg_or_integer_constant_operand", {SUBREG, REG,		\
-					   CONST_INT, CONST_DOUBLE}}, \
-  {"gpc_reg_or_immediate_operand", {SUBREG, REG, CONST_INT,	\
-				    CONST_DOUBLE, CONST,	\
-				    SYMBOL_REF, LABEL_REF}},	\
-  {"spec_reg_operand", {REG}},					\
-  {"accum_reg_operand", {REG}},					\
-  {"srcb_operand", {SUBREG, REG, CONST_INT}},			\
-  {"cmplsrcb_operand", {SUBREG, REG, CONST_INT}},		\
-  {"reg_or_immediate_operand", {SUBREG, REG, CONST_INT, CONST,	\
-				CONST_DOUBLE, CONST, SYMBOL_REF, LABEL_REF}}, \
-  {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}},		\
-  {"and_operand", {SUBREG, REG, CONST_INT}},			\
-  {"add_operand", {SUBREG, REG, CONST_INT}},			\
-  {"call_operand", {SYMBOL_REF, CONST_INT}},			\
-  {"in_operand", {SUBREG, MEM, REG, CONST_INT, CONST, SYMBOL_REF, \
-		  LABEL_REF, CONST_DOUBLE}},			\
-  {"out_operand", {SUBREG, REG, MEM}},				\
-  {"reload_memory_operand", {SUBREG, REG, MEM}},		\
-  {"fp_comparison_operator", {EQ, GT, GE}},			\
-  {"branch_operator", {GE, LT}},				\
-  {"load_multiple_operation", {PARALLEL}},			\
-  {"store_multiple_operation", {PARALLEL}},			\
-  {"epilogue_operand", {CODE_LABEL}},
diff --git a/gcc/config/a29k/a29k.md b/gcc/config/a29k/a29k.md
deleted file mode 100755
index cc4f422..0000000
--- a/gcc/config/a29k/a29k.md
+++ /dev/null
@@ -1,2874 +0,0 @@
-;;- Machine description for AMD Am29000 for GNU C compiler
-;;   Copyright (C) 1991, 1992, 1994 Free Software Foundation, Inc.
-;;   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; The insns in this file are presented in the same order as the AMD 29000
-;; User's Manual (i.e., alphabetical by machine op-code).
-;;
-;; DEFINE_EXPAND's are located near the first occurrence of the major insn
-;; that they generate.
-
-;; The only attribute we have is the type.  We only care about calls, branches,
-;; loads, stores, floating-point operations, and multi-word insns.
-;; Everything else is miscellaneous.
-
-(define_attr "type"
-  "call,branch,load,store,fadd,fmul,fam,fdiv,fsqrt,dmul,dam,ddiv,dsqrt,multi,misc"
-  (const_string "misc"))
-
-;; ASM insns cannot go into a delay slot, so call them "multi".
-(define_asm_attributes [(set_attr "type" "multi")])
-
-(define_attr "in_delay_slot" "yes,no"
-  (if_then_else (eq_attr "type" "call,branch,multi")  (const_string "no")
-		(const_string "yes")))
-
-;; Branch and call insns require a single delay slot.  Annulling is not
-;; supported.
-(define_delay (eq_attr "type" "call,branch")
-  [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
-
-;; Define the function unit usages.  We first define memory as a unit.
-(define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 5
-  [(eq_attr "type" "load")])
-(define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 6
-  [(eq_attr "type" "store")])
-(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
-
-;; Now define the function units for the floating-point support.  Most
-;; units are pipelined and can accept an input every cycle.
-;;
-;; Note that we have an inaccuracy here.  If a fmac insn is issued, followed
-;; 2 cycles later by a fadd, there will be a conflict for the floating
-;; adder that we can't represent.  Also, all insns will conflict for the
-;; floating-point rounder.  It isn't clear how to represent this.
-
-(define_function_unit "multiplier" 1 0 (eq_attr "type" "fmul") 3 0)
-(define_function_unit "multiplier" 1 0 (eq_attr "type" "dmul") 6 4)
-(define_function_unit "multiplier" 1 0 (eq_attr "type" "fam") 6 0)
-(define_function_unit "multiplier" 1 0 (eq_attr "type" "dam") 9 4)
-
-(define_function_unit "adder" 1 0 (eq_attr "type" "fadd,fam,dam") 3 0)
-
-(define_function_unit "divider" 1 0 (eq_attr "type" "fdiv") 11 10)
-(define_function_unit "divider" 1 0 (eq_attr "type" "fsqrt") 28 27)
-(define_function_unit "divider" 1 0 (eq_attr "type" "ddiv") 18 17)
-(define_function_unit "divider" 1 0 (eq_attr "type" "dsqrt") 57 56)
-
-;; ADD
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
-		 (match_operand:SI 2 "add_operand" "rI,N")))]
-  ""
-  "@
-   add %0,%1,%2
-   sub %0,%1,%n2")
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
-		 (match_operand:DI 2 "gpc_reg_operand" "r")))]
-  ""
-  "add %L0,%L1,%L2\;addc %0,%1,%2"
-  [(set_attr "type" "multi")])
-
-;; AND/ANDN
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
-		(match_operand:SI 2 "and_operand" "rI,K")))]
-  ""
-  "@
-   and %0,%1,%2
-   andn %0,%1,%C2")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		(match_operand:SI 2 "cmplsrcb_operand" "r,K")))]
-  ""
-  "@
-   andn %0,%2,%1
-   nor %0,%1,%C2")
-
-;; CALLI
-;;
-;; Each call pattern is duplicated so that we can add CLOBBERs to the
-;; resulting insn.
-;;
-;; We indicate that LR0 is clobbered in the CALL_INSN itself.  Otherwise,
-;; reorg will think it is just clobbered by the called function.
-
-(define_expand "call"
-  [(use (match_operand:SI 0 "" ""))
-   (use (match_operand 1 "" ""))
-   (use (match_operand 2 "" ""))]
-  ""
-  "
-{ rtx insn = emit_call_insn (gen_call_internal (operands[0], operands[1]));
-  a29k_clobbers_to (insn, operands[2]);
-
-  DONE;
-}")
- 
-(define_expand "call_internal"
-  [(parallel [(call (match_operand:SI 0 "" "")
-		    (match_operand 1 "" ""))
-	      (clobber (scratch:SI))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) != MEM)
-    abort ();
-
-  /* We tell here whether this is a recursive call, since this insn may
-     later be inlined into another function.  */
-  if (! TARGET_SMALL_MEMORY
-      && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
-    operands[0] = gen_rtx (MEM, SImode,
-			   force_reg (Pmode, XEXP (operands[0], 0)));
-}")
- 
-(define_expand "call_value"
-  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
-   (use (match_operand:SI 1 "" ""))
-   (use (match_operand 2 "" ""))
-   (use (match_operand 3 "" ""))]
-  ""
-  "
-{ rtx insn = emit_call_insn (gen_call_value_internal (operands[0], operands[1],
-						      operands[2]));
-
-  a29k_clobbers_to (insn, operands[3]);
-  DONE;
-}")
- 
-(define_expand "call_value_internal"
-  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
-		   (call (match_operand:SI 1 "" "")
-			 (match_operand 2 "" "")))
-		   (clobber (scratch:SI))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) != MEM)
-    abort ();
-
-  /* We tell here whether this is a recursive call, since this insn may
-     later be inlined into another function.  */
-  if (! TARGET_SMALL_MEMORY
-      && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
-    operands[1] = gen_rtx (MEM, SImode,
-			   force_reg (Pmode, XEXP (operands[1], 0)));
-
-}")
- 
-(define_insn ""
-  [(call (match_operand:SI 0 "memory_operand" "m")
-	 (match_operand 1 "" ""))
-   (clobber (match_scratch:SI 2 "=&l"))]
-  "GET_CODE (XEXP (operands[0], 0)) != CONST_INT"
-  "calli lr0,%0%#"
-  [(set_attr "type" "call")])
-
-(define_insn ""
-  [(call (mem:SI (match_operand:SI 0 "call_operand" "i"))
-	 (match_operand:SI 1 "general_operand" "g"))
-   (clobber (match_scratch:SI 2 "=&l"))]
-  ""
-  "call lr0,%F0"
-  [(set_attr "type" "call")])
-
-(define_insn ""
-  [(set (match_operand 0 "gpc_reg_operand" "=r")
-	(call (match_operand:SI 1 "memory_operand" "m")
-	      (match_operand 2 "" "")))
-   (clobber (match_scratch:SI 3 "=&l"))]
-  "GET_CODE (XEXP (operands[1], 0)) != CONST_INT"
-  "calli lr0,%1%#"
-  [(set_attr "type" "call")])
-
-(define_insn ""
-  [(set (match_operand 0 "gpc_reg_operand" "=r")
-	(call (mem:SI (match_operand:SI 1 "call_operand" "i"))
-	      (match_operand:SI 2 "general_operand" "g")))
-   (clobber (match_scratch:SI 3 "=&l"))]
-  ""
-  "call lr0,%F1"
-  [(set_attr "type" "call")])
-
-(define_expand "probe"
-  [(call (mem:SI (symbol_ref:SI "_msp_check"))
-	 (const_int 1))]
-  "TARGET_STACK_CHECK"
-  "")
-
-;; This is used for internal routine calls via TPC.  Currently used only
-;; in probe, above.
-(define_insn ""
-  [(call (mem:SI (match_operand:SI 0 "immediate_operand" "s"))
-	 (const_int 1))]
-  ""
-  "call %*,%0"
-  [(set_attr "type" "call")])
-
-;; CONST, CONSTH, CONSTN
-;;
-;; Many of these are generated from move insns.
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(and:SI (match_operand:SI 1 "immediate_operand" "i")
-		(const_int 65535)))]
-  ""
-  "const %0,%1")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (const_int 16)
-			 (match_operand:SI 1 "const_0_operand" ""))
-	(ashiftrt:SI (match_operand:SI 2 "immediate_operand" "i")
-		     (const_int 16)))]
-  ""
-  "consth %0,%2")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (const_int 16)
-			 (match_operand:SI 1 "const_0_operand" ""))
-	(match_operand:SI 2 "cint_16_operand" "J"))]
-  ""
-  "consth %0,%m2")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0"))
-		(match_operand:SI 2 "const_int_operand" "n")))]
-  "(INTVAL (operands[2]) & 0xffff) == 0"
-  "consth %0,%2")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0"))
-		(and:SI (match_operand:SI 2 "immediate_operand" "i")
-			(const_int -65536))))]
-  ""
-  "consth %0,%2")
-
-;; CONVERT
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(fix:SI (match_operand:SF 1 "register_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "convert %0,%1,0,3,0,1")
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(fix:SI (match_operand:DF 1 "register_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "convert %0,%1,0,3,0,2")
-
-(define_insn "fixuns_truncsfsi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "convert %0,%1,1,3,0,1")
-
-(define_insn "fixuns_truncdfsi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "convert %0,%1,1,3,0,2")
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "convert %0,%1,0,4,1,2")
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "convert %0,%1,0,4,2,1")
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "convert %0,%1,0,4,1,0")
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "convert %0,%1,0,4,2,0")
-
-(define_insn "floatunssisf2"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "convert %0,%1,1,4,1,0")
-
-(define_insn "floatunssidf2"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "convert %0,%1,1,4,2,0")
-
-;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(match_operator 3 "comparison_operator"
-			[(match_operand:SI 1 "gpc_reg_operand" "r")
-			 (match_operand:SI 2 "srcb_operand" "rI")]))]
-  ""
-  "cp%J3 %0,%1,%2")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(match_operator 3 "fp_comparison_operator"
-			[(match_operand:SF 1 "register_operand" "r")
-			 (match_operand:SF 2 "register_operand" "r")]))]
-  "! TARGET_SOFT_FLOAT"
-  "f%J3 %0,%1,%2"
-  [(set_attr "type" "fadd")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(match_operator 3 "fp_comparison_operator"
-			[(match_operand:DF 1 "register_operand" "r")
-			 (match_operand:DF 2 "register_operand" "r")]))]
-  "! TARGET_SOFT_FLOAT"
-  "d%J3 %0,%1,%2"
-  [(set_attr "type" "fadd")])
-
-;; DADD
-(define_expand "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(plus:DF (match_operand:DF 1 "register_operand" "")
-		 (match_operand:DF 2 "register_operand" "")))]
-  "! TARGET_SOFT_FLOAT"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(plus:DF (match_operand:DF 1 "register_operand" "%r")
-		 (match_operand:DF 2 "register_operand" "r")))]
-  "! TARGET_29050 "
-  "dadd %0,%1,%2"
-  [(set_attr "type" "fadd")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,a")
-	(plus:DF (match_operand:DF 1 "register_operand" "%r,r")
-		 (match_operand:DF 2 "register_operand" "r,0")))]
-  "TARGET_29050"
-  "@
-   dadd %0,%1,%2
-   dmac 8,%0,%1,%1"
-  [(set_attr "type" "fadd,dam")])
-
-;; DDIV
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(div:DF (match_operand:DF 1 "register_operand" "=r")
-		(match_operand:DF 2 "register_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "ddiv %0,%1,%2"
-  [(set_attr "type" "ddiv")])
-
-;; DIVIDE
-;;
-;; We must set Q to the sign extension of the dividend first.  For MOD, we
-;; must get the remainder from Q.
-;;
-;; For divmod: operand 1 is divided by operand 2; quotient goes to operand
-;; 0 and remainder to operand 3.
-(define_expand "divmodsi4"
-  [(set (match_dup 4)
-	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		     (const_int 31)))
-   (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
-		   (div:SI (match_dup 1)
-			   (match_operand:SI 2 "gpc_reg_operand" "")))
-	      (set (match_operand:SI 3 "gpc_reg_operand" "")
-		   (mod:SI (match_dup 1)
-			   (match_dup 2)))
-	      (use (match_dup 4))])]
-  ""
-  "
-{
-  operands[4] = gen_reg_rtx (SImode);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		(match_operand:SI 2 "gpc_reg_operand" "r")))
-   (set (match_operand:SI 3 "register_operand" "=q")
-	(mod:SI (match_dup 1)
-		(match_dup 2)))
-   (use (match_operand:SI 4 "register_operand" "3"))]
-  ""
-  "divide %0,%1,%2")
-
-;; DIVIDU
-;;
-;; Similar to DIVIDE.
-(define_expand "udivmodsi4"
-  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
-		   (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "gpc_reg_operand" "")))
-	      (set (match_operand:SI 3 "gpc_reg_operand" "")
-		   (umod:SI (match_dup 1)
-			    (match_dup 2)))
-	      (use (const_int 0))])]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		 (match_operand:SI 2 "gpc_reg_operand" "r")))
-   (set (match_operand:SI 3 "register_operand" "=q")
-	(umod:SI (match_dup 1)
-		 (match_dup 2)))
-   (use (match_operand:SI 4 "const_int_operand" "3"))]
-  ""
-  "dividu %0,%1,%2")
-
-;; DMAC/DMSM
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=a,*r")
-	(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r,A")
-			  (match_operand:DF 2 "register_operand" "r,r"))
-		 (match_operand:DF 3 "register_operand" "0,*r")))]
-  "TARGET_29050"
-  "@
-   dmac 0,%0,%1,%2
-   dmsm %0,%2,%3"
-  [(set_attr "type" "dam")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=a")
-	(plus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
-			  (match_operand:DF 2 "register_operand" "r"))
-		 (match_operand:DF 3 "register_operand" "0")))]
-  "TARGET_29050"
-  "dmac 1,%0,%2,%1"
-  [(set_attr "type" "dam")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=a")
-	(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r")
-			   (match_operand:DF 2 "register_operand" "r"))
-		  (match_operand:DF 3 "register_operand" "0")))]
-  "TARGET_29050"
-  "dmac 2,%0,%1,%2"
-  [(set_attr "type" "dam")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=a")
-	(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "r")
-			   (neg:DF (match_operand:DF 2 "register_operand" "r")))
-		  (match_operand:DF 3 "register_operand" "0")))]
-  "TARGET_29050"
-  "dmac 3,%0,%1,%2"
-  [(set_attr "type" "dam")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=a")
-	(mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
-		 (match_operand:DF 2 "register_operand" "r")))]
-  "TARGET_29050"
-  "dmac 5,%0,%2,%1"
-  [(set_attr "type" "dam")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=a")
-	(minus:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
-		  (match_operand:DF 2 "register_operand" "0")))]
-  "TARGET_29050"
-  "dmac 11,%0,%1,%1"
-  [(set_attr "type" "dam")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=a")
-	(neg:DF (plus:DF (match_operand:DF 1 "register_operand" "%r")
-			 (match_operand:DF 2 "register_operand" "0"))))]
-  "TARGET_29050"
-  "dmac 11,%0,%1,%1"
-  [(set_attr "type" "dam")])
-
-(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r,r,a")
-       (neg:DF (match_operand:DF 1 "register_operand" "0,r,r")))
-  (clobber (match_scratch:SI 2 "=&r,&r,X"))]
- "TARGET_29050"
- "@
-  cpeq %2,gr1,gr1\;xor %0,%1,%2
-  cpeq %2,gr1,gr1\;xor %0,%1,%2\;sll %L0,%L1,0
-  dmac 13,%0,%1,%1"
- [(set_attr "type" "multi,multi,dam")])
-
-;; DMUL
-(define_expand "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(mult:DF (match_operand:DF 1 "register_operand" "")
-		 (match_operand:DF 2 "register_operand" "")))]
-  "! TARGET_SOFT_FLOAT"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(mult:DF (match_operand:DF 1 "register_operand" "%r")
-		 (match_operand:DF 2 "register_operand" "r")))]
-  "! TARGET_29050"
-  "dmul %0,%1,%2"
-  [(set_attr "type" "dmul")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,a")
-	(mult:DF (match_operand:DF 1 "register_operand" "%r,r")
-		 (match_operand:DF 2 "register_operand" "r,r")))]
-  "TARGET_29050"
-  "@
-   dmul %0,%1,%2
-   dmac 4,%0,%1,%2"
-  [(set_attr "type" "dmul,dam")])
-
-;; DSUB
-(define_expand "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(minus:DF (match_operand:DF 1 "register_operand" "r")
-		  (match_operand:DF 2 "register_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(minus:DF (match_operand:DF 1 "register_operand" "r")
-		  (match_operand:DF 2 "register_operand" "r")))]
-  "! TARGET_29050"
-  "dsub %0,%1,%2"
-  [(set_attr "type" "fadd")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,a,a")
-	(minus:DF (match_operand:DF 1 "register_operand" "r,0,r")
-		  (match_operand:DF 2 "register_operand" "r,r,0")))]
-  "TARGET_29050"
-  "@
-   dsub %0,%1,%2
-   dmac 9,%0,%2,%2
-   dmac 10,%0,%1,%1"
-  [(set_attr "type" "fadd,dam,dam")])
-
-;; EXBYTE
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI")
-			(const_int -256))
-		(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
-				 (const_int 8)
-				 (ashift:PSI
-				  (match_operand:PSI 3 "register_operand" "b")
-				  (const_int 3)))))]
-  ""
-  "exbyte %0,%2,%1")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			 (const_int 8)
-			 (ashift:PSI
-			  (match_operand:PSI 2 "register_operand" "b")
-			  (const_int 3))))]
-  ""
-  "exbyte %0,%1,0")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (const_int 8)
-			 (match_operand:PSI 1 "const_24_operand" ""))
-	(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
-			 (const_int 8)
-			 (ashift:PSI
-			  (match_operand:PSI 3 "register_operand" "b")
-			  (const_int 3))))]
-  ""
-  "exbyte %0,%2,%0")
-
-(define_expand "extzv"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "general_operand" "")
-			 (match_operand:SI 3 "general_operand" "")))]
-  ""
-  "
-{
-  int size, pos;
-
-  if (GET_CODE (operands[2]) != CONST_INT
-      || GET_CODE (operands[3]) != CONST_INT)
-    FAIL;
-
-  size = INTVAL (operands[2]);
-  pos = INTVAL (operands[3]);
-
-  /* Can't do this unless a byte extraction.  If extracting the high
-     or low byte, don't do this because a shift or AND is shorter.
-     Don't do 16-bit extracts, since the only two are the high and low
-     ends, and it is faster to do them with CONSTH and SRL.  */
-
-  if (size != 8 || (pos != 8 && pos != 16))
-    FAIL;
-
-  operands[3] = gen_rtx (ASHIFT, PSImode,
-			 force_reg (PSImode, GEN_INT (pos / 8)),
-			 GEN_INT (3));
-
-}")
-
-;; EXHW
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI")
-		(const_int -65536))
-		(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
-				 (const_int 16)
-				 (ashift:PSI
-				  (match_operand:PSI 3 "register_operand" "b")
-				  (const_int 3)))))]
-  ""
-  "exhw %0,%2,%1")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			 (const_int 16)
-			 (ashift:PSI
-			  (match_operand:PSI 2 "register_operand" "b")
-			  (const_int 3))))]
-  ""
-  "exhw %0,%1,0")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (const_int 16)
-			 (match_operand:PSI 1 "const_16_operand" ""))
-	(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
-			 (const_int 16)
-			 (ashift:PSI
-			  (match_operand:PSI 3 "register_operand" "b")
-			  (const_int 3))))]
-  ""
-  "exhw %0,%2,%0")
-
-;; EXHWS
-;;
-;; This is probably unused.  The high-order 16-bits are obtained with an SRA
-;; insn.  The low-order 16 bits are a sign-extend, which is a pair of
-;; shifts.  Setting BP followed by the insn is equivalent, so we don't
-;; bother going to any trouble to generate this insn.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(sign_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			 (const_int 16)
-			 (ashift:PSI
-			  (match_operand:PSI 2 "register_operand" "b")
-			  (const_int 3))))]
-  ""
-  "exhws %0,%1")
-
-;; EXTRACT
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		   (match_operand:PSI 2 "register_operand" "f")))]
-  ""
-  "extract %0,%1,%1")
-
-(define_expand "rotlsi3"
-  [(set (match_dup 3)
-	(match_operand:SI 2 "gpc_reg_or_immediate_operand" ""))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		   (match_dup 3)))]
-  ""
-  "
-{ operands[2] = gen_lowpart (PSImode, operands[2]);
-  operands[3] = gen_reg_rtx (PSImode);
-}")
-
-;; It would be nice to be able to have a define_split corresponding to the
-;; above, but there is no way to tell combine we need a PSImode temporary.
-;; If we put a (clobber (scratch:PSI)) there, combine would merge the above
-;; two insns.  This is bad because it then thinks only one insn is needed.
-
-;; FADD
-(define_expand "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(plus:SF (match_operand:SF 1 "register_operand" "")
-		 (match_operand:SF 2 "register_operand" "")))]
-  "! TARGET_SOFT_FLOAT"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(plus:SF (match_operand:SF 1 "register_operand" "%r")
-		 (match_operand:SF 2 "register_operand" "r")))]
-  "! TARGET_29050"
-  "fadd %0,%1,%2"
-  [(set_attr "type" "fadd")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r,a")
-	(plus:SF (match_operand:SF 1 "register_operand" "%r,r")
-		 (match_operand:SF 2 "register_operand" "r,0")))]
-  "TARGET_29050"
-  "@
-   fadd %0,%1,%2
-   fmac 8,%0,%1,%1"
-  [(set_attr "type" "fadd,fam")])
-
-;; FDIV
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(div:SF (match_operand:SF 1 "register_operand" "=r")
-		(match_operand:SF 2 "register_operand" "r")))]
-  "! TARGET_SOFT_FLOAT"
-  "fdiv %0,%1,%2"
-  [(set_attr "type" "fdiv")])
-
-;; FDMUL
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "%r"))
-		 (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
-  "! TARGET_SOFT_FLOAT"
-  "fdmul %0,%1,%2")
-
-;; FMAC/FMSM
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=a,*r")
-	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r,A")
-			  (match_operand:SF 2 "register_operand" "r,r"))
-		 (match_operand:SF 3 "register_operand" "0,*r")))]
-  "TARGET_29050"
-  "@
-   fmac 0,%0,%1,%2
-   fmsm %0,%2,%3"
-  [(set_attr "type" "fam")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(plus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
-			  (match_operand:SF 2 "register_operand" "r"))
-		 (match_operand:SF 3 "register_operand" "0")))]
-  "TARGET_29050"
-  "fmac 1,%0,%2,%1"
-  [(set_attr "type" "fam")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r")
-			   (match_operand:SF 2 "register_operand" "r"))
-		  (match_operand:SF 3 "register_operand" "0")))]
-  "TARGET_29050"
-  "fmac 2,%0,%1,%2"
-  [(set_attr "type" "fam")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
-			   (match_operand:SF 2 "register_operand" "r"))
-		  (match_operand:SF 3 "register_operand" "0")))]
-  "TARGET_29050"
-  "fmac 3,%0,%2,%1"
-  [(set_attr "type" "fam")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
-		 (match_operand:SF 2 "register_operand" "r")))]
-  "TARGET_29050"
-  "fmac 5,%0,%2,%1"
-  [(set_attr "type" "fam")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(minus:SF (neg:SF (match_operand:SF 1 "register_operand" "%r"))
-		  (match_operand:SF 2 "register_operand" "0")))]
-  "TARGET_29050"
-  "fmac 11,%0,%1,%1"
-  [(set_attr "type" "fam")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(neg:SF (plus:SF (match_operand:SF 1 "register_operand" "%r")
-			 (match_operand:SF 2 "register_operand" "0"))))]
-  "TARGET_29050"
-  "fmac 11,%0,%1,%1"
-  [(set_attr "type" "fam")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r,a")
-	(neg:SF (match_operand:SF 1 "register_operand" "r,r")))
-   (clobber (match_scratch:SI 2 "=&r,X"))]
-  "TARGET_29050"
-  "@
-   cpeq %2,gr1,gr1\;xor %0,%1,%2
-   fmac 13,%0,%1,%1"
-  [(set_attr "type" "multi,fam")])
-
-;; FMUL
-(define_expand "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(mult:SF (match_operand:SF 1 "register_operand" "")
-		 (match_operand:SF 2 "register_operand" "")))]
-  "! TARGET_SOFT_FLOAT"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(mult:SF (match_operand:SF 1 "register_operand" "%r")
-		 (match_operand:SF 2 "register_operand" "r")))]
-  "! TARGET_29050"
-  "fmul %0,%1,%2"
-  [(set_attr "type" "fmul")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r,a")
-	(mult:SF (match_operand:SF 1 "register_operand" "%r,r")
-		 (match_operand:SF 2 "register_operand" "r,r")))]
-  "TARGET_29050"
-  "@
-   fmul %0,%1,%2
-   fmac 4,%0,%1,%2"
-  [(set_attr "type" "fmul,fam")])
-
-;; FSUB
-(define_expand "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(minus:SF (match_operand:SF 1 "register_operand" "")
-		  (match_operand:SF 2 "register_operand" "")))]
-  "! TARGET_SOFT_FLOAT"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(minus:SF (match_operand:SF 1 "register_operand" "r")
-		  (match_operand:SF 2 "register_operand" "r")))]
-  "! TARGET_29050"
-  "fsub %0,%1,%2"
-  [(set_attr "type" "fadd")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r,a,a")
-	(minus:SF (match_operand:SF 1 "register_operand" "r,0,r")
-		  (match_operand:SF 2 "register_operand" "r,r,0")))]
-  "TARGET_29050"
-  "@
-   fsub %0,%1,%2
-   fmac 9,%0,%2,%2
-   fmac 10,%0,%1,%1"
-  [(set_attr "type" "fadd,fam,fam")])
-
-;; INBYTE
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (const_int 8)
-			 (ashift:PSI
-			  (match_operand:PSI 2 "register_operand" "b")
-			  (const_int 3)))
-	(match_operand:SI 1 "srcb_operand" "rI"))]
-  ""
-  "inbyte %0,%0,%1")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI
-		 (not:SI
-		  (ashift:SI (const_int 255)
-			     (ashift:PSI
-			      (match_operand:PSI 3 "register_operand" "b")
-			      (const_int 3))))
-		 (match_operand:SI 1 "gpc_reg_operand" "r"))
-		(ashift:SI (zero_extend:SI
-			    (match_operand:QI 2 "srcb_operand" "rI"))
-			   (ashift:PSI (match_dup 3) (const_int 3)))))]
-  ""
-  "inbyte %0,%1,%2")
-
-;; INHW
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (const_int 16)
-			 (ashift:PSI
-			  (match_operand:PSI 2 "register_operand" "b")
-			  (const_int 3)))
-	(match_operand:SI 1 "srcb_operand" "rI"))]
-  ""
-  "inhw %0,%0,%1")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI
-		 (not:SI
-		  (ashift:SI (const_int 65535)
-			     (ashift:PSI
-			      (match_operand:PSI 3 "register_operand" "b")
-			      (const_int 3))))
-		 (match_operand:SI 1 "gpc_reg_operand" "r"))
-		(ashift:SI (zero_extend:SI
-			    (match_operand:HI 2 "srcb_operand" "rI"))
-			   (ashift:PSI (match_dup 3) (const_int 3)))))]
-  ""
-  "inhw %0,%1,%2")
-
-(define_expand "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "")
-			 (match_operand:SI 1 "general_operand" "")
-			 (match_operand:SI 2 "general_operand" ""))
-	(match_operand:SI 3 "srcb_operand" ""))]
-  ""
-  "
-{
-  int size, pos;
-
-  if (GET_CODE (operands[1]) != CONST_INT
-      || GET_CODE (operands[2]) != CONST_INT)
-    FAIL;
-
-  size = INTVAL (operands[1]);
-  pos = INTVAL (operands[2]);
-  if ((size != 8 && size != 16) || pos % size != 0)
-    FAIL;
-
-  operands[2] = gen_rtx (ASHIFT, PSImode,
-			 force_reg (PSImode, GEN_INT (pos / 8)),
-			 GEN_INT (3));
-}")
-
-;; LOAD (also used by move insn).
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(const_int -4))))
-   (set (match_operand:PSI 2 "register_operand" "=b")
-	(truncate:PSI (match_dup 1)))]
-  "! TARGET_DW_ENABLE"
-  "load 0,16,%0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
-  "TARGET_DW_ENABLE"
-  "load 0,1,%0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
-	(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
-  "TARGET_DW_ENABLE"
-  "load 0,1,%0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
-  "TARGET_DW_ENABLE"
-  "load 0,2,%0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))
-   (clobber (match_scratch:PSI 2 "=&b"))]
-  "TARGET_DW_ENABLE"
-  "load 0,17,%0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
-	(sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))
-   (clobber (match_scratch:PSI 2 "=&b"))]
-  "TARGET_DW_ENABLE"
-  "load 0,17,%0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))
-   (clobber (match_scratch:PSI 2 "=&b"))]
-  "TARGET_DW_ENABLE"
-  "load 0,18,%0,%1"
-  [(set_attr "type" "load")])
-
-;; LOADM
-(define_expand "load_multiple"
-  [(set (match_dup 4)
-	(match_operand:PSI 2 "const_int_operand" ""))
-   (match_par_dup 3 [(set (match_operand:SI 0 "" "")
-			  (match_operand:SI 1 "" ""))])]
-  ""
-  "
-{
-  int regno;
-  int count;
-  rtx from;
-  int i;
-
-  /* Support only loading a constant number of hard registers from memory.  */
-  if (GET_CODE (operands[2]) != CONST_INT
-      || operands[2] == const1_rtx
-      || GET_CODE (operands[1]) != MEM
-      || GET_CODE (operands[0]) != REG
-      || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
-    FAIL;
-
-  count = INTVAL (operands[2]);
-  regno = REGNO (operands[0]);
-
-  /* CR gets set to the number of registers minus one.  */
-  operands[2] = GEN_INT(count - 1);
-
-  operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2));
-  from = memory_address (SImode, XEXP (operands[1], 0));
-  XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode,
-					 gen_rtx (REG, SImode, regno),
-					 gen_rtx (MEM, SImode, from));
-  operands[4] = gen_reg_rtx (PSImode);
-
-  XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]);
-  XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]);
-
-  for (i = 1; i < count; i++)
-    XVECEXP (operands[3], 0, i + 2)
-      = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
-		 gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
-}")
-
-;; Indicate that CR is used and is then clobbered.
-(define_insn ""
-  [(set (match_operand 0 "gpc_reg_operand" "=r")
-	(match_operand 1 "memory_operand" "m"))
-   (use (match_operand:PSI 2 "register_operand" "+c"))
-   (clobber (match_dup 2))]
-  "GET_MODE (operands[0]) == GET_MODE (operands[1])
-   && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
-  "loadm 0,0,%0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(match_parallel 0 "load_multiple_operation"
-		   [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
-			 (match_operand:SI 2 "memory_operand" "m"))
-		    (use (match_operand:PSI 3 "register_operand" "+c"))
-		    (clobber (match_dup 3))])]
-  ""
-  "loadm 0,0,%1,%2"
-  [(set_attr "type" "load")])
-
-;; MTSR (used also by move insn)
-(define_insn ""
-  [(set (match_operand:SI 0 "spec_reg_operand" "=*h,*h")
-	(and:SI (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")
-		(match_operand:SI 2 "const_int_operand" "n,n")))]
-  "masks_bits_for_special (operands[0], operands[2])"
-  "@
-   mtsr %0,%1
-   mtsrim %0,%1")
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "register_operand" "=h,h")
-	(truncate:PSI
-	 (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")))]
-  ""
-  "@
-   mtsr %0,%1
-   mtsrim %0,%1")
-
-;; MULTIPLY, MULTM, MULTMU
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
-		 (match_operand:SI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 3 "=&q"))]
-  ""
-  "multiply %0,%1,%2")
-
-(define_insn "mulsidi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
-		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
-   (clobber (match_scratch:SI 3 "=&q"))]
-  "TARGET_MULTM"
-  "multiply %L0,%1,%2\;multm %0,%1,%2"
-  [(set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))
-   (clobber (reg:SI 180))]
-  "reload_completed"
-  [(parallel [(set (match_dup 3)
-		   (mult:SI (match_dup 1) (match_dup 2)))
-	      (clobber (reg:SI 180))])
-   (parallel [(set (match_dup 4)
-		   (truncate:SI
-		    (lshiftrt:DI
-		     (mult:DI (sign_extend:DI (match_dup 1))
-			      (sign_extend:DI (match_dup 2)))
-		     (const_int 32))))
-	      (clobber (reg:SI 180))])]
-  "
-{ operands[3] = operand_subword (operands[0], 1, 1, DImode);
-  operands[4] = operand_subword (operands[0], 0, 1, DImode); } ")
-			    
-(define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
-		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
-   (clobber (match_scratch:SI 3 "=&q"))]
-  "TARGET_MULTM"
-  "multiplu %L0,%1,%2\;multmu %0,%1,%2"
-  [(set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))
-   (clobber (reg:SI 180))]
-  "reload_completed"
-  [(parallel [(set (match_dup 3)
-		   (mult:SI (match_dup 1) (match_dup 2)))
-	      (clobber (reg:SI 180))])
-   (parallel [(set (match_dup 4)
-		   (truncate:SI
-		    (lshiftrt:DI
-		     (mult:DI (zero_extend:DI (match_dup 1))
-			      (zero_extend:DI (match_dup 2)))
-		     (const_int 32))))
-	      (clobber (reg:SI 180))])]
-  "
-{ operands[3] = operand_subword (operands[0], 1, 1, DImode);
-  operands[4] = operand_subword (operands[0], 0, 1, DImode); } ")
-			    
-(define_insn "smulsi3_highpart"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI
-	  (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-		   (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
-	  (const_int 32))))
-   (clobber (match_scratch:SI 3 "=&q"))]
-  "TARGET_MULTM"
-  "multm %0,%1,%2")
-
-(define_insn "umulsi3_highpart"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI
-	  (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-		   (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
-	  (const_int 32))))
-   (clobber (match_scratch:SI 3 "=&q"))]
-  "TARGET_MULTM"
-  "multmu %0,%1,%2")
-
-;; NAND
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
-  ""
-  "nand %0,%1,%2")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-		(match_operand:SI 2 "const_int_operand" "K")))]
-  ; Match TARGET_29050 in "orn" pattern for slightly better reload.
-  "! TARGET_29050 && ((unsigned) ~ INTVAL (operands[2])) < 256"
-  "nand %0,%1,%C2")
-
-;; NOR
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
-  ""
-  "nor %0,%1,%2")
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  ""
-  "nor %0,%1,0")
-
-;; OR/ORN
-(define_expand "iorsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(match_operand:SI 2 "srcb_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
-		(match_operand:SI 2 "srcb_operand" "rI")))]
-  "! TARGET_29050"
-  "or %0,%1,%2")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
-		(match_operand:SI 2 "and_operand" "rI,K")))]
-  "TARGET_29050"
-  "@
-   or %0,%1,%2
-   orn %0,%1,%C2")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		(match_operand:SI 2 "cmplsrcb_operand" "r,K")))]
-  "TARGET_29050"
-  "@
-   orn %0,%2,%1
-   nand %0,%1,%C2")
-
-
-;; SLL (also used by move insn)
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "aseq 0x40,gr1,gr1")
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		   (match_operand:QI 2 "srcb_operand" "rn")))]
-  ""
-  "sll %0,%1,%Q2")
-
-;; SQRT
-(define_insn "sqrtsf2"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
-	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
-  "TARGET_29050"
-  "sqrt %0,%1,1"
-  [(set_attr "type" "fsqrt")])
-
-(define_insn "sqrtdf2"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
-	(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
-  "TARGET_29050"
-  "sqrt %0,%1,2"
-  [(set_attr "type" "dsqrt")])
-
-;; SRA
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		     (match_operand:QI 2 "srcb_operand" "rn")))]
-  ""
-  "sra %0,%1,%Q2")
-
-;; SRL
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		     (match_operand:QI 2 "srcb_operand" "rn")))]
-  ""
-  "srl %0,%1,%Q2")
-
-;; STORE
-;;
-;; These somewhat bogus patterns exist to set OPT = 001/010 for partial-word
-;; stores on systems with DW not set.
-(define_insn ""
-  [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r")
-			(const_int -4)))
-	(match_operand:SI 1 "gpc_reg_operand" "r"))]
-  "! TARGET_DW_ENABLE"
-  "store 0,1,%1,%0"
-  [(set_attr "type" "store")])
-
-(define_insn ""
-  [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r")
-			(const_int -3)))
-	(match_operand:SI 1 "gpc_reg_operand" "r"))]
-  "! TARGET_DW_ENABLE"
-  "store 0,2,%1,%0"
-  [(set_attr "type" "store")])
-
-;; STOREM
-(define_expand "store_multiple"
-  [(use (match_operand 0 "" ""))
-   (use (match_operand 1 "" ""))
-   (use (match_operand 2 "" ""))]
-  ""
-  "
-{ rtx pat;
-
- if (TARGET_NO_STOREM_BUG)
-    pat = gen_store_multiple_no_bug (operands[0], operands[1], operands[2]);
-  else
-    pat = gen_store_multiple_bug (operands[0], operands[1], operands[2]);
-
-  if (pat)
-    emit_insn (pat);
-  else
-    FAIL;
-
-  DONE;
-}")
-
-(define_expand "store_multiple_no_bug"
-  [(set (match_dup 4)
-	(match_operand:PSI 2 "const_int_operand" ""))
-   (match_par_dup 3 [(set (match_operand:SI 0 "" "")
-			  (match_operand:SI 1 "" ""))])]
-  ""
-  "
-{
-  int regno;
-  int count;
-  rtx from;
-  int i;
-
-  /* Support only storing a constant number of hard registers to memory.  */
-  if (GET_CODE (operands[2]) != CONST_INT
-      || operands[2] == const1_rtx
-      || GET_CODE (operands[0]) != MEM
-      || GET_CODE (operands[1]) != REG
-      || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
-    FAIL;
-
-  count = INTVAL (operands[2]);
-  regno = REGNO (operands[1]);
-
-  /* CR gets set to the number of registers minus one.  */
-  operands[2] = GEN_INT(count - 1);
-
-  operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2));
-  from = memory_address (SImode, XEXP (operands[0], 0));
-  XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode,
-					 gen_rtx (MEM, SImode, from),
-					 gen_rtx (REG, SImode, regno));
-  operands[4] = gen_reg_rtx (PSImode);
-  XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]);
-  XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]);
-
-  for (i = 1; i < count; i++)
-    XVECEXP (operands[3], 0, i + 2)
-      = gen_rtx (SET, VOIDmode,
-		 gen_rtx (MEM, SImode, plus_constant (from, i * 4)),
-		 gen_rtx (REG, SImode, regno + i));
-}")
-
-(define_expand "store_multiple_bug"
-  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
-			  (match_operand:SI 1 "" ""))
-		     (use (match_operand:SI 2 "" ""))])]
-  ""
-  "
-{
-  int regno;
-  int count;
-  rtx from;
-  int i;
-
-  /* Support only storing a constant number of hard registers to memory.  */
-  if (GET_CODE (operands[2]) != CONST_INT
-      || operands[2] == const1_rtx
-      || GET_CODE (operands[0]) != MEM
-      || GET_CODE (operands[1]) != REG
-      || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
-    FAIL;
-
-  count = INTVAL (operands[2]);
-  regno = REGNO (operands[1]);
-
-  operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
-  from = memory_address (SImode, XEXP (operands[0], 0));
-  XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode,
-					 gen_rtx (MEM, SImode, from),
-					 gen_rtx (REG, SImode, regno));
-  XVECEXP (operands[3], 0, 1)
-    = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, PSImode));
-
-  for (i = 1; i < count; i++)
-    XVECEXP (operands[3], 0, i + 1)
-      = gen_rtx (SET, VOIDmode,
-		 gen_rtx (MEM, SImode, plus_constant (from, i * 4)),
-		 gen_rtx (REG, SImode, regno + i));
-}")
-
-(define_insn ""
-  [(set (match_operand 0 "memory_operand" "=m")
-	(match_operand 1 "gpc_reg_operand" "r"))
-   (clobber (match_scratch:PSI 2 "=&c"))]
-  "!TARGET_NO_STOREM_BUG
-   && GET_MODE (operands[0]) == GET_MODE (operands[1])
-   && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
-  "mtsrim cr,%S1\;storem 0,0,%1,%0"
-  [(set_attr "type" "multi")])
-
-(define_insn ""
-  [(match_parallel 0 "store_multiple_operation"
-		   [(set (match_operand:SI 1 "memory_operand" "=m")
-			 (match_operand:SI 2 "gpc_reg_operand" "r"))
-		    (clobber (match_scratch:PSI 3 "=&c"))])]
-  "!TARGET_NO_STOREM_BUG"
-  "mtsrim cr,%V0\;storem 0,0,%2,%1"
-  [(set_attr "type" "multi")])
-
-(define_insn ""
-  [(set (match_operand 0 "memory_operand" "=m")
-	(match_operand 1 "gpc_reg_operand" "r"))
-   (use (match_operand:PSI 2 "register_operand" "+c"))
-   (clobber (match_dup 2))]
-  "TARGET_NO_STOREM_BUG
-   && GET_MODE (operands[0]) == GET_MODE (operands[1])
-   && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
-  "storem 0,0,%1,%0"
-  [(set_attr "type" "store")])
-
-(define_insn ""
-  [(match_parallel 0 "store_multiple_operation"
-		   [(set (match_operand:SI 1 "memory_operand" "=m")
-			 (match_operand:SI 2 "gpc_reg_operand" "r"))
-		    (use (match_operand:PSI 3 "register_operand" "+c"))
-		    (clobber (match_dup 3))])]
-  "TARGET_NO_STOREM_BUG"
-  "storem 0,0,%2,%1"
-  [(set_attr "type" "store")])
-
-;; SUB
-;;
-;; Either operand can be a register or an 8-bit constant, but both cannot be
-;; constants (can't usually occur anyway).
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(minus:SI (match_operand:SI 1 "srcb_operand" "")
-		  (match_operand:SI 2 "srcb_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == CONST_INT
-      && GET_CODE (operands[1]) == CONST_INT)
-    operands[1] = force_reg (SImode, operands[1]);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(minus:SI (match_operand:SI 1 "srcb_operand" "r,I")
-		  (match_operand:SI 2 "srcb_operand" "rI,r")))]
-  "register_operand (operands[1], SImode)
-   || register_operand (operands[2], SImode)"
-  "@
-   sub %0,%1,%2
-   subr %0,%2,%1")
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-		  (match_operand:DI 2 "gpc_reg_operand" "r")))]
-  ""
-  "sub %L0,%L1,%L2\;subc %0,%1,%2"
-  [(set_attr "type" "multi")])
-
-;; SUBR (also used above in SUB)
-(define_insn "negdi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
-  ""
-  "subr %L0,%L1,0\;subrc %0,%1,0"
-  [(set_attr "type" "multi")])
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  ""
-  "subr %0,%1,0")
-
-;; XNOR
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
-			(match_operand:SI 2 "gpc_reg_operand" "r"))))]
-  ""
-  "xnor %0,%1,%2")
-
-;; XOR
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
-		(match_operand:SI 2 "and_operand" "rI,K")))]
-  ""
-  "@
-   xor %0,%1,%2
-   xnor %0,%1,%C2")
-
-;; Can use XOR to negate floating-point values, but we are better off not doing
-;; it that way on the 29050 so it can combine with the fmac insns.
-(define_expand "negsf2"
-  [(parallel [(set (match_operand:SF 0 "register_operand" "")
-		   (neg:SF (match_operand:SF 1 "register_operand" "")))
-	      (clobber (match_scratch:SI 2 ""))])]
-  "! TARGET_SOFT_FLOAT"
-  "
-{
-  rtx result;
-  rtx target;
-
-  if (! TARGET_29050)
-    {
-      target = operand_subword_force (operands[0], 0, SFmode);
-      result = expand_binop (SImode, xor_optab,
-			     operand_subword_force (operands[1], 0, SFmode),
-			     GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
-      if (result == 0)
-	abort ();
-
-      if (result != target)
-	emit_move_insn (result, target);
-
-      /* Make a place for REG_EQUAL.  */
-      emit_move_insn (operands[0], operands[0]);
-      DONE;
-    }
-}")
-
-(define_expand "negdf2"
-  [(parallel [(set (match_operand:DF 0 "register_operand" "")
-		   (neg:DF (match_operand:DF 1 "register_operand" "")))
-	      (clobber (match_scratch:SI 2 ""))])]
-  "! TARGET_SOFT_FLOAT"
-  "
-{
-  rtx result;
-  rtx target;
-  rtx insns;
-
-  if (! TARGET_29050)
-    {
-      start_sequence ();
-      target = operand_subword (operands[0], 0, 1, DFmode);
-      result = expand_binop (SImode, xor_optab,
-			     operand_subword_force (operands[1], 0, DFmode),
-			     GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
-      if (result == 0)
-	abort ();
-
-      if (result != target)
-	emit_move_insn (result, target);
-  
-      emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
-		      operand_subword_force (operands[1], 1, DFmode));
-
-      insns = get_insns ();
-      end_sequence ();
-
-      emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
-      DONE;
-    }
-}")
-
-;; Sign extend and truncation operations.
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
-	(zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
-  ""
-  "and %0,%1,255")
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
-  ""
-  "and %0,%1,255")
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")))]
-  ""
-  "consth %0,0")
-
-(define_expand "extendqihi2"
-  [(set (match_dup 2)
-	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
-		   (const_int 24)))
-   (set (match_operand:HI 0 "gpc_reg_operand" "")
-	(ashiftrt:SI (match_dup 2)
-		     (const_int 24)))]
-  ""
-  "
-{ operands[0] = gen_lowpart (SImode, operands[0]);
-  operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "extendqisi2"
-  [(set (match_dup 2)
-	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
-		   (const_int 24)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashiftrt:SI (match_dup 2)
-		     (const_int 24)))]
-  ""
-  "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "extendhisi2"
-  [(set (match_dup 2)
-	(ashift:SI (match_operand:HI 1 "gpc_reg_operand" "")
-		   (const_int 16)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashiftrt:SI (match_dup 2)
-		     (const_int 16)))]
-  ""
-  "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
-;; Define the methods used to move data around.
-;;
-;; movsi:
-;;
-;; If storing into memory, force source into register.
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM && ! gpc_reg_operand (operands[1], SImode))
-    operands[1] = copy_to_mode_reg (SImode, operands[1]);
-  else if (spec_reg_operand (operands[0], SImode)
-	   && ! (register_operand (operands[1], SImode)
-		 || cint_16_operand (operands[1], SImode)))
-    operands[1] = force_reg (SImode, operands[1]);
-}")
-
-(define_expand "movpsi"
-  [(set (match_operand:PSI 0 "general_operand" "")
-	(match_operand:PSI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM
-      && ! gpc_reg_operand (operands[1], PSImode))
-    operands[1] = copy_to_mode_reg (PSImode, operands[1]);
-  else if (spec_reg_operand (operands[0], PSImode)
-	   && ! (register_operand (operands[1], PSImode)
-		 || cint_16_operand (operands[1], PSImode)))
-    operands[1] = force_reg (PSImode, operands[1]);
-}")
-
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(match_operand:SI 1 "long_const_operand" ""))]
-  ""
-  [(set (match_dup 0)
-	(and:SI (match_dup 1)
-		(const_int 65535)))
-   (set (match_dup 0)
-	(ior:SI (zero_extend:SI (match_dup 2))
-		(and:SI (match_dup 1)
-			(const_int -65536))))]
-  " operands[2] = gen_lowpart (HImode, operands[0]); ")
-
-;; Subroutines to load/store halfwords.  Operands 0 and 1 are the output and
-;; input, respectively, except that the address is passed for a MEM instead 
-;; of the MEM itself and the short item is passed in QImode.
-;;
-;; Operand 2 is a scratch general register and operand 3 is a scratch register
-;; used for BP.  When called before reload, pseudos are passed for both
-;; operands.  During reload, R_TAV is used for the general register, and
-;; a reload register of class BR_REGS (R_VP) for BP.
-;;
-;; We have two versions of the store operations, for when halfword writes are
-;; supported and when they are not.
-(define_expand "loadhi"
-  [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
-		   (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				   (const_int -4))))
-	      (set (match_operand:PSI 3 "register_operand" "")
-		   (truncate:PSI (match_dup 1)))])
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(zero_extract:SI (match_dup 2)
-			 (const_int 16)
-			 (ashift:PSI (match_dup 3) (const_int 3))))]
-  ""
-  "")
-
-(define_expand "storehinhww"
- [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
-		   (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "")
-				   (const_int -4))))
-	      (set (match_operand:PSI 3 "register_operand" "")
-		   (truncate:PSI (match_dup 0)))])
-   (set (zero_extract:SI (match_dup 2)
-			 (const_int 16)
-			 (ashift:PSI (match_dup 3) (const_int 3)))
-	(match_operand:SI 1 "gpc_reg_operand" ""))
-   (set (mem:SI (match_dup 0))
-	(match_dup 2))]
-  ""
-  "")
-
-(define_expand "storehihww"
-  [(set (match_operand:PSI 3 "register_operand" "")
-	(truncate:PSI (match_operand:SI 0 "gpc_reg_operand" "")))
-   (set (match_operand:SI 2 "gpc_reg_operand" "")
-	(ior:SI (and:SI (not:SI (ashift:SI (const_int 65535)
-					   (ashift:PSI (match_dup 3)
-						       (const_int 3))))
-			(match_operand:SI 1 "gpc_reg_operand" ""))
-		(ashift:SI (zero_extend:SI (match_dup 4))
-			   (ashift:PSI (match_dup 3) (const_int 3)))))
-   (set (mem:SI (and:SI (match_dup 0)
-			(const_int -3)))
-	(match_dup 2))]
-  ""
-  "
-{ operands[4] = gen_lowpart (HImode, operands[1]); }")
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{ if (GET_CODE (operands[0]) == MEM) 
-    {
-      if (! gpc_reg_operand (operands[1], HImode))
-	operands[1] = copy_to_mode_reg (HImode, operands[1]);
-      if (! TARGET_DW_ENABLE)
-	{
-	  rtx general = gen_reg_rtx (SImode);
-	  rtx bp = gen_reg_rtx (PSImode);
-	  rtx (*fcn) ()
-	    = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww;
-	  rtx seq = (*fcn) (XEXP (operands[0], 0),
-			    gen_lowpart (SImode, operands[1]),
-			    general, bp);
-	    
-	  a29k_set_memflags (seq, operands[0]);
-	  emit_insn (seq);
-	  DONE;
-	}
-    }
-  else if (GET_CODE (operands[1]) == MEM)
-    {
-      if (! TARGET_DW_ENABLE)
-	{
-	  rtx general = gen_reg_rtx (SImode);
-	  rtx bp = gen_reg_rtx (PSImode);
-	  rtx seq = gen_loadhi (gen_lowpart (SImode, operands[0]),
-				XEXP (operands[1], 0), general, bp);
-
-	  a29k_set_memflags (seq, operands[1]);
-	  emit_insn (seq);
-	  DONE;
-	}
-    }
-}")
-
-(define_expand "reload_inhi"
-  [(parallel [(match_operand:SI 0 "register_operand" "=r")
-	      (match_operand:SI 1 "reload_memory_operand" "m")
-	      (match_operand:PSI 2 "register_operand" "=b")])]
-  "! TARGET_DW_ENABLE"
-  "
-{ rtx seq = gen_loadhi (gen_lowpart (SImode, operands[0]),
-			a29k_get_reloaded_address (operands[1]),
-			gen_rtx (REG, SImode, R_TAV),
-			operands[2]);
-
-  a29k_set_memflags (seq, operands[1]);
-  emit_insn (seq);
-  DONE;
-}")
-
-(define_expand "reload_outhi"
-  [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m")
-	      (match_operand:SI 1 "register_operand" "m")
-	      (match_operand:PSI 2 "register_operand" "=b")])]
-  "! TARGET_DW_ENABLE"
-  "
-{ rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww;
-  rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]),
-		    gen_lowpart (SImode, operands[1]),
-		    gen_rtx (REG, SImode, R_TAV), operands[2]);
-
-  a29k_set_memflags (seq, operands[0]);
-  emit_insn (seq);
-  DONE;
-}")
-
-;; Subroutines to load/store bytes.  Operands 0 and 1 are the output and
-;; input, respectively, except that the address is passed for a MEM instead 
-;; of the MEM itself and the short item is passed in QImode.
-;;
-;; Operand 2 is a scratch general register and operand 3 is a scratch register
-;; used for BP.  When called before reload, pseudos are passed for both
-;; operands.  During reload, R_TAV is used for the general register, and
-;; a reload register of class BR_REGS (R_VP) for BP.
-;;
-;; We have two versions of the store operations, for when byte writes are
-;; supported and when they are not.
-(define_expand "loadqi"
-  [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
-		   (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				   (const_int -4))))
-	      (set (match_operand:PSI 3 "register_operand" "")
-		   (truncate:PSI (match_dup 1)))])
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(zero_extract:SI (match_dup 2)
-			 (const_int 8)
-			 (ashift:PSI (match_dup 3) (const_int 3))))]
-  ""
-  "")
-
-(define_expand "storeqinhww"
-  [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
-		   (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "")
-				   (const_int -4))))
-	      (set (match_operand:PSI 3 "register_operand" "")
-		   (truncate:PSI (match_dup 0)))])
-   (set (zero_extract:SI (match_dup 2)
-			 (const_int 8)
-			 (ashift:PSI (match_dup 3)
-				     (const_int 3)))
-	(match_operand:SI 1 "gpc_reg_operand" ""))
-   (set (mem:SI (match_dup 0))
-	(match_dup 2))]
-  ""
-  "")
-
-(define_expand "storeqihww"
-  [(set (match_operand:PSI 3 "register_operand" "")
-	(truncate:PSI (match_operand:SI 0 "gpc_reg_operand" "")))
-   (set (match_operand:SI 2 "gpc_reg_operand" "")
-	(ior:SI (and:SI (not:SI (ashift:SI (const_int 255)
-					   (ashift:PSI (match_dup 3)
-						       (const_int 3))))
-			(match_operand:SI 1 "gpc_reg_operand" ""))
-		(ashift:SI (zero_extend:SI (match_dup 4))
-			   (ashift:PSI (match_dup 3)
-				       (const_int 3)))))
-   (set (mem:SI (and:SI (match_dup 0)
-		        (const_int -4)))
-	(match_dup 2))]
-  ""
-  "
-{ operands[4] = gen_lowpart (QImode, operands[1]); }")
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{ if (GET_CODE (operands[0]) == MEM)
-    {
-      if (! gpc_reg_operand (operands[1], QImode))
-	operands[1] = copy_to_mode_reg (QImode, operands[1]);
-      if (! TARGET_DW_ENABLE)
-	{
-	  rtx general = gen_reg_rtx (SImode);
-	  rtx bp = gen_reg_rtx (PSImode);
-	  rtx (*fcn) ()
-	    = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww;
-	  rtx seq = (*fcn) (XEXP (operands[0], 0),
-			    gen_lowpart (SImode, operands[1]),
-			    general, bp);
-	    
-	  a29k_set_memflags (seq, operands[0]);
-	  emit_insn (seq);
-	  DONE;
-	}
-    }
-  else if (GET_CODE (operands[1]) == MEM)
-    {
-      if (! TARGET_DW_ENABLE)
-	{
-	  rtx general = gen_reg_rtx (SImode);
-	  rtx bp = gen_reg_rtx (PSImode);
-	  rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]),
-				XEXP (operands[1], 0), general, bp);
-
-	  a29k_set_memflags (seq, operands[1]);
-	  emit_insn (seq);
-	  DONE;
-	}
-    }
-}")
-
-(define_expand "reload_inqi"
-  [(parallel [(match_operand:SI 0 "register_operand" "=r")
-	      (match_operand:SI 1 "reload_memory_operand" "m")
-	      (match_operand:PSI 2 "register_operand" "=b")])]
-  "! TARGET_DW_ENABLE"
-  "
-{ rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]),
-			a29k_get_reloaded_address (operands[1]),
-			gen_rtx (REG, SImode, R_TAV),
-			operands[2]);
-
-  a29k_set_memflags (seq, operands[1]);
-  emit_insn (seq);
-  DONE;
-}")
-
-(define_expand "reload_outqi"
-  [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m")
-	      (match_operand:SI 1 "register_operand" "m")
-	      (match_operand:PSI 2 "register_operand" "=b")])]
-  "! TARGET_DW_ENABLE"
-  "
-{ rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww;
-  rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]),
-		    gen_lowpart (SImode, operands[1]),
-		    gen_rtx (REG, SImode, R_TAV), operands[2]);
-
-  a29k_set_memflags (seq, operands[0]);
-  emit_insn (seq);
-  DONE;
-}")
-
-;; Now the actual insns used to move data around.  We include here the
-;; DEFINE_SPLITs that may be needed.  In some cases these will be
-;; split again.  For floating-point, if we can look inside the constant,
-;; always split it.  This can eliminate unnecessary insns.
-(define_insn ""
-  [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m")
-	(match_operand:SF 1 "in_operand" "r,E,F,m,r"))]
-  "(gpc_reg_operand (operands[0], SFmode)
-    || gpc_reg_operand (operands[1], SFmode))
-   && ! TARGET_29050"
-  "@
-   sll %0,%1,0
-   #
-   const %0,%1\;consth %0,%1
-   load 0,0,%0,%1
-   store 0,0,%1,%0"
-  [(set_attr "type" "misc,multi,multi,load,store")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m,*a,r")
-	(match_operand:SF 1 "in_operand" "r,E,F,m,r,r,*a"))]
-  "(gpc_reg_operand (operands[0], SFmode)
-    || gpc_reg_operand (operands[1], SFmode))
-   && TARGET_29050"
-  "@
-   sll %0,%1,0
-   #
-   const %0,%1\;consth %0,%1
-   load 0,0,%0,%1
-   store 0,0,%1,%0
-   mtacc %1,1,%0
-   mfacc %0,1,%1"
-  [(set_attr "type" "misc,multi,multi,load,store,fadd,fadd")])
-
-;; Turn this into SImode.  It will then be split up that way.
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "")
-	(match_operand:SF 1 "float_const_operand" ""))]
-  "HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT"
-  [(set (match_dup 0)
-	(match_dup 1))]
-  "
-{ operands[0] = operand_subword (operands[0], 0, 0, SFmode);
-  operands[1] = operand_subword (operands[1], 0, 0, SFmode);
-
-  if (operands[0] == 0 || operands[1] == 0)
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m")
-	(match_operand:DF 1 "in_operand" "rE,F,m,r"))
-   (clobber (match_scratch:PSI 2 "=X,X,&c,&c"))]
-  "(gpc_reg_operand (operands[0], DFmode)
-    || gpc_reg_operand (operands[1], DFmode))
-   && ! TARGET_29050"
-  "@
-   #
-   const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1
-   mtsrim cr,1\;loadm 0,0,%0,%1
-   mtsrim cr,1\;storem 0,0,%1,%0"
-  [(set_attr "type" "multi")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m,?*a,?r")
-	(match_operand:DF 1 "in_operand" "rE,F,m,r,r,*a"))
-   (clobber (match_scratch:PSI 2 "=X,X,&c,&c,X,X"))]
-  "(gpc_reg_operand (operands[0], DFmode)
-    || gpc_reg_operand (operands[1], DFmode))
-   && TARGET_29050"
-  "@
-   #
-   const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1
-   mtsrim cr,1\;loadm 0,0,%0,%1
-   mtsrim cr,1\;storem 0,0,%1,%0
-   mtacc %1,2,%0
-   mfacc %0,2,%1"
-  [(set_attr "type" "multi,multi,multi,multi,fadd,fadd")])
-
-;; Split register-register copies and constant loads into two SImode loads,
-;; one for each word.  In the constant case, they will get further split.
-;; Don't so this until register allocation, though, since it will
-;; interfere with register allocation.  Normally copy the lowest-addressed
-;; word first; the exception is if we are copying register to register and
-;; the lowest register of the first operand is the highest register of the
-;; second operand.
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(match_operand:DF 1 "gpc_reg_or_float_constant_operand" ""))
-   (clobber (match_scratch:PSI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 5) (match_dup 6))]
-  "
-{ if (GET_CODE (operands[1]) == REG
-      && REGNO (operands[0]) == REGNO (operands[1]) + 1)
-    {
-      operands[3] = operand_subword (operands[0], 1, 1, DFmode);
-      operands[4] = operand_subword (operands[1], 1, 1, DFmode);
-      operands[5] = operand_subword (operands[0], 0, 1, DFmode);
-      operands[6] = operand_subword (operands[1], 0, 1, DFmode);
-    }
-  else
-    {
-      operands[3] = operand_subword (operands[0], 0, 1, DFmode);
-      operands[4] = operand_subword (operands[1], 0, 1, DFmode);
-      operands[5] = operand_subword (operands[0], 1, 1, DFmode);
-      operands[6] = operand_subword (operands[1], 1, 1, DFmode);
-    }
-
-  if (operands[3] == 0 || operands[4] == 0
-      || operands[5] == 0 || operands[6] == 0)
-    FAIL;
-}")
-
-;; Split memory loads and stores into the MTSR and LOADM/STOREM.
-(define_split
-  [(set (match_operand:DF 0 "out_operand" "")
-	(match_operand:DF 1 "in_operand" ""))
-   (clobber (reg:PSI 179))]
-  "TARGET_NO_STOREM_BUG
-   && (memory_operand (operands[0], DFmode)
-       || memory_operand (operands[1], DFmode))"
-  [(set (reg:PSI 179) (const_int 1))
-   (parallel [(set (match_dup 0) (match_dup 1))
-	      (use (reg:PSI 179))
-	      (clobber (reg:PSI 179))])]
-  "")
-
-;; DI move is similar to DF move.
-(define_insn ""
-  [(set (match_operand:DI 0 "out_operand" "=?r,r,m")
-	(match_operand:DI 1 "in_operand" "rn,m,r"))
-   (clobber (match_scratch:PSI 2 "=X,&c,&c"))]
-  "(gpc_reg_operand (operands[0], DImode)
-     || gpc_reg_operand (operands[1], DImode))"
-  "@
-   #
-   mtsrim cr,1\;loadm 0,0,%0,%1
-   mtsrim cr,1\;storem 0,0,%1,%0"
-  [(set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_operand:DI 1 "gpc_reg_or_integer_constant_operand" ""))
-   (clobber (match_scratch:PSI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 5) (match_dup 6))]
-  "
-{ if (GET_CODE (operands[1]) == REG
-      && REGNO (operands[0]) == REGNO (operands[1]) + 1)
-    {
-      operands[3] = operand_subword (operands[0], 1, 1, DImode);
-      operands[4] = operand_subword (operands[1], 1, 1, DImode);
-      operands[5] = operand_subword (operands[0], 0, 1, DImode);
-      operands[6] = operand_subword (operands[1], 0, 1, DImode);
-    }
-  else
-    {
-      operands[3] = operand_subword (operands[0], 0, 1, DImode);
-      operands[4] = operand_subword (operands[1], 0, 1, DImode);
-      operands[5] = operand_subword (operands[0], 1, 1, DImode);
-      operands[6] = operand_subword (operands[1], 1, 1, DImode);
-    }
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "out_operand" "")
-	(match_operand:DI 1 "in_operand" ""))
-   (clobber (reg:PSI 179))]
-  "TARGET_NO_STOREM_BUG
-   && (memory_operand (operands[0], DImode)
-       || memory_operand (operands[1], DImode))"
-  [(set (reg:PSI 179) (const_int 1))
-   (parallel [(set (match_dup 0) (match_dup 1))
-	      (use (reg:PSI 179))
-	      (clobber (reg:PSI 179))])]
-  "")
-
-;; TImode moves are very similar to DImode moves, except that we can't
-;; have constants.
-(define_insn ""
-  [(set (match_operand:TI 0 "out_operand" "=?r,r,m")
-	(match_operand:TI 1 "in_operand" "r,m,r"))
-   (clobber (match_scratch:PSI 2 "=X,&c,&c"))]
-  "(gpc_reg_operand (operands[0], TImode)
-    || gpc_reg_operand (operands[1], TImode))"
-  "@
-   #
-   mtsrim cr,3\;loadm 0,0,%0,%1
-   mtsrim cr,3\;storem 0,0,%1,%0"
-  [(set_attr "type" "multi,multi,multi")])
-
-(define_split
-  [(set (match_operand:TI 0 "gpc_reg_operand" "")
-	(match_operand:TI 1 "gpc_reg_operand" ""))
-   (clobber (match_scratch:PSI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 5) (match_dup 6))
-   (set (match_dup 7) (match_dup 8))
-   (set (match_dup 9) (match_dup 10))]
-  "
-{
-  if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
-      && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
-    {
-      operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3);
-      operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3);
-      operands[5] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
-      operands[6] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
-      operands[7] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-      operands[8] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-      operands[9] = gen_rtx (REG, SImode, REGNO (operands[0]));
-      operands[10] = gen_rtx (REG, SImode, REGNO (operands[1]));
-    }
-  else
-    {
-      operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]));
-      operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]));
-      operands[5] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-      operands[6] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-      operands[7] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
-      operands[8] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
-      operands[9] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3);
-      operands[10] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3); 
-    }
-}")
-
-(define_split
-  [(set (match_operand:TI 0 "out_operand" "")
-	(match_operand:TI 1 "in_operand" ""))
-   (clobber (reg:PSI 179))]
-  "TARGET_NO_STOREM_BUG
-   && (memory_operand (operands[0], TImode)
-       || memory_operand (operands[1], TImode))"
-  [(set (reg:PSI 179) (const_int 3))
-   (parallel [(set (match_dup 0) (match_dup 1))
-	      (use (reg:PSI 179))
-	      (clobber (reg:PSI 179))])]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h")
-        (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))]
-  "(gpc_reg_operand (operands[0], SImode)
-    || gpc_reg_operand (operands[1], SImode)
-    || (spec_reg_operand (operands[0], SImode)
-        && cint_16_operand (operands[1], SImode)))
-   && ! TARGET_29050"
-  "@
-   sll %0,%1,0
-   const %0,%1
-   constn %0,%M1
-   cpeq %0,gr1,gr1
-   #
-   load 0,0,%0,%1
-   mfsr %0,%1
-   store 0,0,%1,%0
-   mtsr %0,%1
-   mtsrim %0,%1"
-  [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h")
-        (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))]
-  "(gpc_reg_operand (operands[0], SImode)
-    || gpc_reg_operand (operands[1], SImode)
-    || (spec_reg_operand (operands[0], SImode)
-        && cint_16_operand (operands[1], SImode)))
-   && TARGET_29050"
-  "@
-   sll %0,%1,0
-   const %0,%1
-   constn %0,%M1
-   consthz %0,%1
-   #
-   load 0,0,%0,%1
-   mfsr %0,%1
-   store 0,0,%1,%0
-   mtsr %0,%1
-   mtsrim %0,%1"
-  [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")])
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "out_operand" "=*r,*r,*r,*r,m,h,h")
-        (match_operand:PSI 1 "in_operand" "r,i,m,h,r,r,J"))]
-  "(gpc_reg_operand (operands[0], PSImode)
-    || gpc_reg_operand (operands[1], PSImode)
-    || (spec_reg_operand (operands[0], PSImode)
-        && cint_16_operand (operands[1], PSImode)))"
-  "@
-   sll %0,%1,0
-   const %0,%1
-   load 0,0,%0,%1
-   mfsr %0,%1
-   store 0,0,%1,%0
-   mtsr %0,%1
-   mtsrim %0,%1"
-  [(set_attr "type" "misc,multi,load,misc,store,misc,misc")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "out_operand" "=r,r,r,m,r,*h,*h")
-        (match_operand:HI 1 "in_operand" "r,i,m,r,*h,r,i"))]
-  "gpc_reg_operand (operands[0], HImode)
-   || gpc_reg_operand (operands[1], HImode)
-   || (spec_reg_operand (operands[0], HImode)
-       && cint_16_operand (operands[1], HImode))"
-  "@
-   sll %0,%1,0
-   const %0,%1
-   load 0,2,%0,%1
-   store 0,2,%1,%0
-   mfsr %0,%1
-   mtsr %0,%1
-   mtsrim %0,%1"
-  [(set_attr "type" "misc,misc,load,store,misc,misc,misc")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "out_operand" "=r,r,r,m,r,*h,*h")
-        (match_operand:QI 1 "in_operand" "r,i,m,r,*h,r,i"))]
-  "gpc_reg_operand (operands[0], QImode)
-   || gpc_reg_operand (operands[1], QImode)
-   || (spec_reg_operand (operands[0], HImode)
-       && cint_16_operand (operands[1], HImode))"
-  "@
-   sll %0,%1,0
-   const %0,%1
-   load 0,1,%0,%1
-   store 0,1,%1,%0
-   mfsr %0,%1
-   mtsr %0,%1
-   mtsrim %0,%1"
-  [(set_attr "type" "misc,misc,load,store,misc,misc,misc")])
-
-;; Define move insns for DI, TI, SF, and DF.
-;;
-;; In no case do we support mem->mem directly.
-;;
-;; For DI move of constant to register, split apart at this time since these
-;; can require anywhere from 2 to 4 insns and determining which is complex.
-;;
-;; In other cases, handle similarly to SImode moves.
-;;
-;; However, indicate that DI, TI, and DF moves may clobber CR (reg 179).
-(define_expand "movdi"
-  [(parallel [(set (match_operand:DI 0 "general_operand" "")
-		   (match_operand:DI 1 "general_operand" ""))
-	      (clobber (scratch:PSI))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (DImode, operands[1]);
-}")
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{ if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (SFmode, operands[1]);
-}")
-
-(define_expand "movdf"
-  [(parallel [(set (match_operand:DF 0 "general_operand" "")
-		   (match_operand:DF 1 "general_operand" ""))
-	      (clobber (scratch:PSI))])]
-  ""
-  "
-{ if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (DFmode, operands[1]);
-}")
-
-(define_expand "movti"
-  [(parallel [(set (match_operand:TI 0 "general_operand" "")
-		   (match_operand:TI 1 "general_operand" ""))
-	      (clobber (scratch:PSI))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (TImode, operands[1]);
-
-  /* We can't handle constants in general because there is no rtl to represent
-     128 bit constants.  Splitting happens to work for CONST_INTs so we split
-     them for good code.  Other constants will get forced to memory.  */
-
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-     rtx part0, part1, part2, part3;
-
-     part0 = operand_subword (operands[0], 0, 1, TImode);
-     part1 = operand_subword (operands[0], 1, 1, TImode);
-     part2 = operand_subword (operands[0], 2, 1, TImode);
-     part3 = operand_subword (operands[0], 3, 1, TImode);
-
-     emit_move_insn (part0, const0_rtx);
-     emit_move_insn (part1, const0_rtx);
-     emit_move_insn (part2, const0_rtx);
-     emit_move_insn (part3, const0_rtx);
-
-     DONE;
-    }
-  else if (CONSTANT_P (operands[1]))
-    {
-      operands[1] = force_const_mem (TImode, operands[1]);
-      if (! memory_address_p (TImode, XEXP (operands[1], 0))
-	  && ! reload_in_progress)
-        operands[1] = change_address (operands[1], TImode,
-				      XEXP (operands[1], 0));
-    }
-}")
-
-;; Here are the variants of the above for use during reload.
-
-(define_expand "reload_indf"
-  [(parallel [(set (match_operand:DF 0 "register_operand" "=r")
-		   (match_operand:DF 1 "reload_memory_operand" "m"))
-	      (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
-  ""
-  "")
-
-(define_expand "reload_outdf"
-  [(parallel [(set (match_operand:DF 0 "reload_memory_operand" "=m")
-		   (match_operand:DF 1 "register_operand" "r"))
-	      (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
-  ""
-  "")
-
-(define_expand "reload_indi"
-  [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
-		   (match_operand:DI 1 "reload_memory_operand" "m"))
-	      (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
-  ""
-  "")
-
-(define_expand "reload_outdi"
-  [(parallel [(set (match_operand:DI 0 "reload_memory_operand" "=m")
-		   (match_operand:DI 1 "register_operand" "r"))
-	      (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
-  ""
-  "")
-
-(define_expand "reload_inti"
-  [(parallel [(set (match_operand:TI 0 "register_operand" "=r")
-		   (match_operand:TI 1 "reload_memory_operand" "m"))
-	      (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
-  ""
-  "")
-
-(define_expand "reload_outti"
-  [(parallel [(set (match_operand:TI 0 "reload_memory_operand" "=m")
-		   (match_operand:TI 1 "register_operand" "r"))
-	      (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
-  ""
-  "")
-
-;; For compare operations, we simply store the comparison operands and
-;; do nothing else.  The following branch or scc insn will output whatever
-;; is needed.
-(define_expand "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "gpc_reg_operand" "")
-		 (match_operand:SI 1 "srcb_operand" "")))]
-  ""
-  "
-{
-  a29k_compare_op0 = operands[0];
-  a29k_compare_op1 = operands[1];
-  a29k_compare_fp_p = 0;
-  DONE;
-}")
-
-(define_expand "cmpsf"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "gpc_reg_operand" "")
-		 (match_operand:SF 1 "gpc_reg_operand" "")))]
-  "! TARGET_SOFT_FLOAT"
-  "
-{
-  a29k_compare_op0 = operands[0];
-  a29k_compare_op1 = operands[1];
-  a29k_compare_fp_p = 1;
-  DONE;
-}")
-
-(define_expand "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "gpc_reg_operand" "")
-		 (match_operand:DF 1 "gpc_reg_operand" "")))]
-  "! TARGET_SOFT_FLOAT"
-  "
-{
-  a29k_compare_op0 = operands[0];
-  a29k_compare_op1 = operands[1];
-  a29k_compare_fp_p = 1;
-  DONE;
-}")
-
-;; We can generate bit-tests better if we use NE instead of EQ, but we
-;; don't have an NE for floating-point.  So we have to have two patterns
-;; for EQ and two for NE.
-
-(define_expand "beq"
-  [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3)))
-   (set (pc)
-	(if_then_else (ge (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT)
-    {
-      emit_insn (gen_beq_fp (operands[0]));
-      DONE;
-    }
-
-  operands[1] = gen_reg_rtx (SImode);
-  operands[2] = a29k_compare_op0;
-  operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "beq_fp"
-  [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3)))
-   (set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (SImode);
-  operands[2] = a29k_compare_op0;
-  operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bne"
-  [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3)))
-   (set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT)
-    {
-      emit_insn (gen_bne_fp (operands[0]));
-      DONE;
-    }
-
-  operands[1] = gen_reg_rtx (SImode);
-  operands[2] = a29k_compare_op0;
-  operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bne_fp"
-  [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3)))
-   (set (pc)
-	(if_then_else (ge (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (SImode);
-  operands[2] = a29k_compare_op0;
-  operands[3] = a29k_compare_op1;
-}")
-
-;; We don't have a floating-point "lt" insn, so we have to use "gt" in that
-;; case with the operands swapped.  The operands must both be registers in
-;; the floating-point case, so we know that swapping them is OK.
-(define_expand "blt"
-  [(set (match_dup 1) (match_dup 2))
-   (set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (SImode);
-  if (a29k_compare_fp_p)
-    operands[2] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0);
-  else
-    operands[2] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1);
-}")
-
-;; Similarly for "le".
-(define_expand "ble"
-  [(set (match_dup 1) (match_dup 2))
-   (set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (SImode);
-  if (a29k_compare_fp_p)
-    operands[2] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0);
-  else
-    operands[2] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1);
-}")
-
-(define_expand "bltu"
-  [(set (match_dup 1) (ltu:SI (match_dup 2) (match_dup 3)))
-   (set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (SImode);
-  operands[2] = a29k_compare_op0;
-  operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bleu"
-  [(set (match_dup 1) (leu:SI (match_dup 2) (match_dup 3)))
-   (set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (SImode);
-  operands[2] = a29k_compare_op0;
-  operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bgt"
-  [(set (match_dup 1) (gt:SI (match_dup 2) (match_dup 3)))
-   (set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (SImode);
-  operands[2] = a29k_compare_op0;
-  operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bge"
-  [(set (match_dup 1) (ge:SI (match_dup 2) (match_dup 3)))
-   (set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (SImode);
-  operands[2] = a29k_compare_op0;
-  operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bgtu"
-  [(set (match_dup 1) (gtu:SI (match_dup 2) (match_dup 3)))
-   (set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (SImode);
-  operands[2] = a29k_compare_op0;
-  operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "bgeu"
-  [(set (match_dup 1) (geu:SI (match_dup 2) (match_dup 3)))
-   (set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (SImode);
-  operands[2] = a29k_compare_op0;
-  operands[3] = a29k_compare_op1;
-}")
-
-(define_expand "seq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(eq:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "
-{
-  operands[1] = a29k_compare_op0;
-  operands[2] = a29k_compare_op1;
-}")
-		 
-;; This is the most complicated case, because we don't have a floating-point
-;; "ne" insn.  If integer, handle normally.  If floating-point, write the
-;; compare and then write an insn to reverse the test.
-(define_expand "sne_fp"
-  [(set (match_dup 3)
-	(eq:SI (match_operand 1 "gpc_reg_operand" "")
-	       (match_operand 2 "gpc_reg_operand" "")))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ge:SI (match_dup 3) (const_int 0)))]
-  "! TARGET_SOFT_FLOAT"
-  "
-{ operands[3] = gen_reg_rtx (SImode);
-}");
-
-(define_expand "sne"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ne:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "
-{
-  operands[1] = a29k_compare_op0;
-  operands[2] = a29k_compare_op1;
-
-  if (a29k_compare_fp_p)
-    {
-      emit_insn (gen_sne_fp (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-		 
-;; We don't have a floating-point "lt" insn, so use "gt" and swap the
-;; operands, the same as we do "blt".
-(define_expand "slt"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  if (a29k_compare_fp_p)
-    operands[1] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0);
-  else
-    operands[1] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1);
-}")
-
-;; Similarly for "le"
-(define_expand "sle"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  if (a29k_compare_fp_p)
-    operands[1] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0);
-  else
-    operands[1] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1);
-}")
-
-(define_expand "sltu"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ltu:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "
-{
-  operands[1] = a29k_compare_op0;
-  operands[2] = a29k_compare_op1;
-}")
-
-(define_expand "sleu"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(leu:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "
-{
-  operands[1] = a29k_compare_op0;
-  operands[2] = a29k_compare_op1;
-}")
-
-(define_expand "sgt"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(gt:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "
-{
-  operands[1] = a29k_compare_op0;
-  operands[2] = a29k_compare_op1;
-}")
-
-(define_expand "sge"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ge:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "
-{
-  operands[1] = a29k_compare_op0;
-  operands[2] = a29k_compare_op1;
-}")
-		 
-(define_expand "sgtu"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(gtu:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "
-{
-  operands[1] = a29k_compare_op0;
-  operands[2] = a29k_compare_op1;
-}")
-
-(define_expand "sgeu"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(geu:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "
-{
-  operands[1] = a29k_compare_op0;
-  operands[2] = a29k_compare_op1;
-}")
-
-;; Now define the actual jump insns.
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "branch_operator"
-				      [(match_operand:SI 1 "gpc_reg_operand" "r")
-				       (const_int 0)])
-		      (label_ref (match_operand 2 "" ""))
-		      (pc)))]
-  ""
-  "jmp%b0 %1,%l2%#"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "branch_operator"
-				      [(match_operand:SI 1 "gpc_reg_operand" "r")
-				       (const_int 0)])
-		      (return)
-		      (pc)))]
-  "null_epilogue ()"
-  "jmp%b0i %1,lr0%#"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "branch_operator"
-				      [(match_operand:SI 1 "gpc_reg_operand" "r")
-				       (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 2 "" ""))))]
-  ""
-  "jmp%B0 %1,%l2%#"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "branch_operator"
-				      [(match_operand:SI 1 "gpc_reg_operand" "r")
-				       (const_int 0)])
-		      (pc)
-		      (return)))]
-  "null_epilogue ()"
-  "jmp%B0i %1,lr0%#"
-  [(set_attr "type" "branch")])
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "jmp %e0%E0"
-  [(set_attr "type" "branch")])
-
-(define_insn "return"
-  [(return)]
-  "null_epilogue ()"
-  "jmpi lr0%#"
-  [(set_attr "type" "branch")])
-
-(define_insn "indirect_jump"
-  [(set (pc)
-	(match_operand:SI 0 "gpc_reg_operand" "r"))]
-  ""
-  "jmpi %0%#"
-  [(set_attr "type" "branch")])
-
-(define_insn "tablejump"
-  [(set (pc)
-	(match_operand:SI 0 "gpc_reg_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmpi %0%#"
-  [(set_attr "type" "branch")])
-
-;; JMPFDEC
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (match_operand:SI 0 "gpc_reg_operand" "r")
-			  (const_int 0))
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  ""
-  "jmpfdec %0,%l1%#"
-  [(set_attr "type" "branch")])
diff --git a/gcc/config/a29k/t-a29k b/gcc/config/a29k/t-a29k
deleted file mode 100755
index 7468422..0000000
--- a/gcc/config/a29k/t-a29k
+++ /dev/null
@@ -1,5 +0,0 @@
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# We need crt0.o.
-LIBGCC1_TEST =
diff --git a/gcc/config/a29k/t-a29kbare b/gcc/config/a29k/t-a29kbare
deleted file mode 100755
index 21ba24f..0000000
--- a/gcc/config/a29k/t-a29kbare
+++ /dev/null
@@ -1,19 +0,0 @@
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# We need crt0.o.
-LIBGCC1_TEST =
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... 
-
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-
diff --git a/gcc/config/a29k/t-vx29k b/gcc/config/a29k/t-vx29k
deleted file mode 100755
index 293674e..0000000
--- a/gcc/config/a29k/t-vx29k
+++ /dev/null
@@ -1,17 +0,0 @@
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# We need crt0.o.
-LIBGCC1_TEST =
-
-# We don't want to put exit in libgcc.a for VxWorks, because VxWorks
-# does not have _exit.
-TARGET_LIBGCC2_CFLAGS = -Dexit=unused_exit
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
diff --git a/gcc/config/a29k/udi.h b/gcc/config/a29k/udi.h
deleted file mode 100755
index 400ffbb..0000000
--- a/gcc/config/a29k/udi.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Definitions of target machine for GNU compiler, for AMD Am29000 CPU
-   running over UDI using COFF.
-   Copyright (C) 1994, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Support the ctors and dtors sections for g++.  */
-
-#define CTORS_SECTION_ASM_OP	"\t.use .ctors"
-#define DTORS_SECTION_ASM_OP	"\t.use .dtors"
-
-/* A list of other sections which the compiler might be "in" at any
-   given time.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS readonly_data, in_ctors, in_dtors
-
-/* A list of extra section function definitions.  */
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  READONLY_DATA_FUNCTION						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-#define READONLY_DATA_FUNCTION					\
-void								\
-literal_section ()						\
-{								\
-  if (in_section != readonly_data)				\
-    {								\
-      fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
-      in_section = readonly_data;				\
-    }								\
-}								\
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-#define INT_ASM_OP ".word"
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
diff --git a/gcc/config/a29k/unix.h b/gcc/config/a29k/unix.h
deleted file mode 100755
index f05f258..0000000
--- a/gcc/config/a29k/unix.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Definitions of target machine for GNU compiler, for AMD Am29000 CPU, Unix.
-   Copyright (C) 1991, 1993, 1994, 1996 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* We define unix instead of EPI and define unix-style machine names.  */
-
-/* Set our default target to be the 29050; that is the more interesting chip
-   for Unix systems.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (1+2+16+128)
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dam29k -Da29k -Dam29000 -Asystem(unix) -Acpu(a29k) -Amachine(a29k)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{!m29000:-Dam29050 -D__am29050__}"
-
-/* Use a default linker configuration file.  */
-#undef LINK_SPEC
-#define LINK_SPEC "-T default.gld%s"
-
-/* Define the magic numbers that we recognize as COFF.  */
-
-#define MY_ISCOFF(magic) ((magic) == SIPFBOMAGIC || (magic) == SIPRBOMAGIC)
-
-/* For some systems, it is best if double-word objects are aligned on a 
-   doubleword boundary.  We want to maintain compatibility with MetaWare in
-   a29k.h, but do not feel constrained to do so here.  */
-
-#undef BIGGEST_ALIGNMENT
-#define BIGGEST_ALIGNMENT 64
-
-/* Add shared data as a kludge for now.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)					\
-{ char *p, *after_dir = main_input_filename;			\
-  if (TARGET_29050)						\
-    fprintf (FILE, "\t.cputype 29050\n");			\
-  for (p = main_input_filename; *p; p++)			\
-    if (*p == '/')						\
-      after_dir = p + 1;					\
-  fprintf (FILE, "\t.file ");					\
-  output_quoted_string (FILE, after_dir);			\
-  fprintf (FILE, "\n");						\
-  if (flag_shared_data)						\
-    fprintf (FILE, "\t.sect .shdata,data\n");			\
-  fprintf (FILE, "\t.sect .lit,lit\n");  }
-
-/* Output before shared  data.  */
-
-#define SHARED_SECTION_ASM_OP "\t.use .shdata"
-
-/* If we want shared data, we have to turn off commons.  */
-
-#define OVERRIDE_OPTIONS if (flag_shared_data) flag_no_common = 1;
-
-/* Default to -fno-pcc-struct-return, since we don't have to worry about
-   compatibility.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-#if 0 /* This would be needed except that the 29k doesn't have strict
-	 alignment requirements.  */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE)				\
-  (((TYPE) != 0)							\
-	? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY)				\
-		? PARM_BOUNDARY						\
-		: TYPE_ALIGN(TYPE))					\
-	: ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY)			\
-		? PARM_BOUNDARY						\
-		: GET_MODE_ALIGNMENT(MODE)))
-#endif
diff --git a/gcc/config/a29k/vx29k.h b/gcc/config/a29k/vx29k.h
deleted file mode 100755
index 8739b1b..0000000
--- a/gcc/config/a29k/vx29k.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Vxworks 29k version.
-   Copyright (C) 1994, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file just exists to give specs for the 29k running on VxWorks.  */
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#undef  CPP_PREDEFINES
-#define CPP_PREDEFINES "-D_AM29K -D_AM29000 -Acpu(a29k) -Amachine(a29k) -D__vxworks -D__vxworks_5"
-
-/* Vxworks header files require that the macro CPU be set.
-   We could define it in CPP_PREDEFINES, but the value is (or will be)
-   dependent upon GCC options.  */
-
-#undef CPP_SPEC
-#define CPP_SPEC "-DCPU=AM29200"
-
-/* VxWorks does all the library stuff itself.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC ""
-
-/* VxWorks provides the functionality of crt0.o and friends itself.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "crtbegin.o%s"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s"
diff --git a/gcc/config/a29k/x-unix b/gcc/config/a29k/x-unix
deleted file mode 100755
index ed85ea3..0000000
--- a/gcc/config/a29k/x-unix
+++ /dev/null
@@ -1,2 +0,0 @@
-# Needed for missing functions in Sym1.
-CLIB=-liberty -lld
diff --git a/gcc/config/a29k/xm-a29k.h b/gcc/config/a29k/xm-a29k.h
deleted file mode 100755
index 774e34b..0000000
--- a/gcc/config/a29k/xm-a29k.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Configuration for GNU C-compiler for AMD Am29000 processor. 
-   Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_WORDS_BIG_ENDIAN
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
diff --git a/gcc/config/a29k/xm-unix.h b/gcc/config/a29k/xm-unix.h
deleted file mode 100755
index 206d8fd..0000000
--- a/gcc/config/a29k/xm-unix.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Configuration for GNU C-compiler for AMD Am29000 processor. 
-   Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_WORDS_BIG_ENDIAN
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* Ultra is V7, which is closest to USG.  */
-#define USG
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
deleted file mode 100755
index 970f1d6..0000000
--- a/gcc/config/alpha/alpha.c
+++ /dev/null
@@ -1,5101 +0,0 @@
-/* Subroutines used for code generation on the DEC Alpha.
-   Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "config.h"
-#include "system.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#include "reload.h"
-#include "tree.h"
-#include "expr.h"
-#include "obstack.h"
-#include "except.h"
-#include "function.h"
-#include "toplev.h"
-
-/* External data.  */
-extern char *version_string;
-extern int rtx_equal_function_value_matters;
-
-/* Specify which cpu to schedule for. */
-
-enum processor_type alpha_cpu;
-static char* const alpha_cpu_name[] = 
-{
-  "ev4", "ev5", "ev6"
-};
-
-/* Specify how accurate floating-point traps need to be.  */
-
-enum alpha_trap_precision alpha_tp;
-
-/* Specify the floating-point rounding mode.  */
-
-enum alpha_fp_rounding_mode alpha_fprm;
-
-/* Specify which things cause traps.  */
-
-enum alpha_fp_trap_mode alpha_fptm;
-
-/* Strings decoded into the above options.  */
-
-char *alpha_cpu_string;		/* -mcpu= */
-char *alpha_tp_string;		/* -mtrap-precision=[p|s|i] */
-char *alpha_fprm_string;	/* -mfp-rounding-mode=[n|m|c|d] */
-char *alpha_fptm_string;	/* -mfp-trap-mode=[n|u|su|sui] */
-char *alpha_mlat_string;	/* -mmemory-latency= */
-
-/* Save information from a "cmpxx" operation until the branch or scc is
-   emitted.  */
-
-rtx alpha_compare_op0, alpha_compare_op1;
-int alpha_compare_fp_p;
-
-/* Define the information needed to modify the epilogue for EH.  */
-
-rtx alpha_eh_epilogue_sp_ofs;
-
-/* Non-zero if inside of a function, because the Alpha asm can't
-   handle .files inside of functions.  */
-
-static int inside_function = FALSE;
-
-/* If non-null, this rtx holds the return address for the function.  */
-
-static rtx alpha_return_addr_rtx;
-
-/* The number of cycles of latency we should assume on memory reads.  */
-
-int alpha_memory_latency = 3;
-
-/* Whether the function needs the GP.  */
-
-static int alpha_function_needs_gp;
-
-/* The alias set for prologue/epilogue register save/restore.  */
-
-static int alpha_sr_alias_set;
-
-/* Declarations of static functions.  */
-static void alpha_set_memflags_1
-  PROTO((rtx, int, int, int));
-static rtx alpha_emit_set_const_1
-  PROTO((rtx, enum machine_mode, HOST_WIDE_INT, int));
-static void alpha_expand_unaligned_load_words
-  PROTO((rtx *out_regs, rtx smem, HOST_WIDE_INT words, HOST_WIDE_INT ofs));
-static void alpha_expand_unaligned_store_words
-  PROTO((rtx *out_regs, rtx smem, HOST_WIDE_INT words, HOST_WIDE_INT ofs));
-static void alpha_sa_mask
-  PROTO((unsigned long *imaskP, unsigned long *fmaskP));
-static int alpha_does_function_need_gp
-  PROTO((void));
-
-
-/* Get the number of args of a function in one of two ways.  */
-#ifdef OPEN_VMS
-#define NUM_ARGS current_function_args_info.num_args
-#else
-#define NUM_ARGS current_function_args_info
-#endif
-
-#define REG_PV 27
-#define REG_RA 26
-
-/* Parse target option strings. */
-
-void
-override_options ()
-{
-  alpha_cpu
-    = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
-      : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
-
-  if (alpha_cpu_string)
-    {
-      if (! strcmp (alpha_cpu_string, "ev4")
-	  || ! strcmp (alpha_cpu_string, "21064"))
-	{
-	  alpha_cpu = PROCESSOR_EV4;
-	  target_flags &= ~ (MASK_BWX | MASK_CIX | MASK_MAX);
-	}
-      else if (! strcmp (alpha_cpu_string, "ev5")
-	       || ! strcmp (alpha_cpu_string, "21164"))
-	{
-	  alpha_cpu = PROCESSOR_EV5;
-	  target_flags &= ~ (MASK_BWX | MASK_CIX | MASK_MAX);
-	}
-      else if (! strcmp (alpha_cpu_string, "ev56")
-	       || ! strcmp (alpha_cpu_string, "21164a"))
-	{
-	  alpha_cpu = PROCESSOR_EV5;
-	  target_flags |= MASK_BWX;
-	  target_flags &= ~ (MASK_CIX | MASK_MAX);
-	}
-      else if (! strcmp (alpha_cpu_string, "pca56")
-	       || ! strcmp (alpha_cpu_string, "21164PC")
-	       || ! strcmp (alpha_cpu_string, "21164pc"))
-	{
-	  alpha_cpu = PROCESSOR_EV5;
-	  target_flags |= MASK_BWX | MASK_MAX;
-	  target_flags &= ~ MASK_CIX;
-	}
-      else if (! strcmp (alpha_cpu_string, "ev6")
-	       || ! strcmp (alpha_cpu_string, "21264"))
-	{
-	  alpha_cpu = PROCESSOR_EV6;
-	  target_flags |= MASK_BWX | MASK_CIX | MASK_MAX;
-	}
-      else
-	error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
-    }
-
-  alpha_tp = ALPHA_TP_PROG;
-  alpha_fprm = ALPHA_FPRM_NORM;
-  alpha_fptm = ALPHA_FPTM_N;
-
-  if (TARGET_IEEE)
-    {
-      alpha_tp = ALPHA_TP_INSN;
-      alpha_fptm = ALPHA_FPTM_SU;
-    }
-
-  if (TARGET_IEEE_WITH_INEXACT)
-    {
-      alpha_tp = ALPHA_TP_INSN;
-      alpha_fptm = ALPHA_FPTM_SUI;
-    }
-
-  if (alpha_tp_string)
-    {
-      if (! strcmp (alpha_tp_string, "p"))
-	alpha_tp = ALPHA_TP_PROG;
-      else if (! strcmp (alpha_tp_string, "f"))
-	alpha_tp = ALPHA_TP_FUNC;
-      else if (! strcmp (alpha_tp_string, "i"))
-	alpha_tp = ALPHA_TP_INSN;
-      else
-	error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string);
-    }
-
-  if (alpha_fprm_string)
-    {
-      if (! strcmp (alpha_fprm_string, "n"))
-	alpha_fprm = ALPHA_FPRM_NORM;
-      else if (! strcmp (alpha_fprm_string, "m"))
-	alpha_fprm = ALPHA_FPRM_MINF;
-      else if (! strcmp (alpha_fprm_string, "c"))
-	alpha_fprm = ALPHA_FPRM_CHOP;
-      else if (! strcmp (alpha_fprm_string,"d"))
-	alpha_fprm = ALPHA_FPRM_DYN;
-      else
-	error ("bad value `%s' for -mfp-rounding-mode switch",
-	       alpha_fprm_string);
-    }
-
-  if (alpha_fptm_string)
-    {
-      if (strcmp (alpha_fptm_string, "n") == 0)
-	alpha_fptm = ALPHA_FPTM_N;
-      else if (strcmp (alpha_fptm_string, "u") == 0)
-	alpha_fptm = ALPHA_FPTM_U;
-      else if (strcmp (alpha_fptm_string, "su") == 0)
-	alpha_fptm = ALPHA_FPTM_SU;
-      else if (strcmp (alpha_fptm_string, "sui") == 0)
-	alpha_fptm = ALPHA_FPTM_SUI;
-      else
-	error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
-    }
-
-  /* Do some sanity checks on the above option. */
-
-  if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
-      && alpha_tp != ALPHA_TP_INSN)
-    {
-      warning ("fp software completion requires -mtrap-precision=i");
-      alpha_tp = ALPHA_TP_INSN;
-    }
-
-  if (TARGET_FLOAT_VAX)
-    {
-      if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
-	{
-	  warning ("rounding mode not supported for VAX floats");
-	  alpha_fprm = ALPHA_FPRM_NORM;
-	}
-      if (alpha_fptm == ALPHA_FPTM_SUI)
-	{
-	  warning ("trap mode not supported for VAX floats");
-	  alpha_fptm = ALPHA_FPTM_SU;
-	}
-    }
-
-  {
-    char *end;
-    int lat;
-
-    if (!alpha_mlat_string)
-      alpha_mlat_string = "L1";
-
-    if (ISDIGIT ((unsigned char)alpha_mlat_string[0])
-	&& (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
-      ;
-    else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
-	     && ISDIGIT ((unsigned char)alpha_mlat_string[1])
-	     && alpha_mlat_string[2] == '\0')
-      {
-	static int const cache_latency[][4] = 
-	{
-	  { 3, 30, -1 },	/* ev4 -- Bcache is a guess */
-	  { 2, 12, 38 },	/* ev5 -- Bcache from PC164 LMbench numbers */
-	  { 3, 13, -1 },	/* ev6 -- Ho hum, doesn't exist yet */
-	};
-
-	lat = alpha_mlat_string[1] - '0';
-	if (lat < 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
-	  {
-	    warning ("L%d cache latency unknown for %s",
-		     lat, alpha_cpu_name[alpha_cpu]);
-	    lat = 3;
-	  }
-	else
-	  lat = cache_latency[alpha_cpu][lat-1];
-      }
-    else if (! strcmp (alpha_mlat_string, "main"))
-      {
-	/* Most current memories have about 370ns latency.  This is
-	   a reasonable guess for a fast cpu.  */
-	lat = 150;
-      }
-    else
-      {
-	warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string);
-	lat = 3;
-      }
-
-    alpha_memory_latency = lat;
-  }
-
-  /* Default the definition of "small data" to 8 bytes.  */
-  if (!g_switch_set)
-    g_switch_value = 8;
-
-  /* Acquire a unique set number for our register saves and restores.  */
-  alpha_sr_alias_set = new_alias_set ();
-}
-
-/* Returns 1 if VALUE is a mask that contains full bytes of zero or ones.  */
-
-int
-zap_mask (value)
-     HOST_WIDE_INT value;
-{
-  int i;
-
-  for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
-       i++, value >>= 8)
-    if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
-      return 0;
-
-  return 1;
-}
-
-/* Returns 1 if OP is either the constant zero or a register.  If a
-   register, it must be in the proper mode unless MODE is VOIDmode.  */
-
-int
-reg_or_0_operand (op, mode)
-      register rtx op;
-      enum machine_mode mode;
-{
-  return op == const0_rtx || register_operand (op, mode);
-}
-
-/* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
-   any register.  */
-
-int
-reg_or_6bit_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return ((GET_CODE (op) == CONST_INT
-	   && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
-	  || register_operand (op, mode));
-}
-
-
-/* Return 1 if OP is an 8-bit constant or any register.  */
-
-int
-reg_or_8bit_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return ((GET_CODE (op) == CONST_INT
-	   && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
-	  || register_operand (op, mode));
-}
-
-/* Return 1 if OP is an 8-bit constant.  */
-
-int
-cint8_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return ((GET_CODE (op) == CONST_INT
-	   && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100));
-}
-
-/* Return 1 if the operand is a valid second operand to an add insn.  */
-
-int
-add_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    /* Constraints I, J, O and P are covered by K.  */
-    return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
-	    || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
-
-  return register_operand (op, mode);
-}
-
-/* Return 1 if the operand is a valid second operand to a sign-extending
-   add insn.  */
-
-int
-sext_add_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
-	    || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
-
-  return register_operand (op, mode);
-}
-
-/* Return 1 if OP is the constant 4 or 8.  */
-
-int
-const48_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT
-	  && (INTVAL (op) == 4 || INTVAL (op) == 8));
-}
-
-/* Return 1 if OP is a valid first operand to an AND insn.  */
-
-int
-and_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
-    return (zap_mask (CONST_DOUBLE_LOW (op))
-	    && zap_mask (CONST_DOUBLE_HIGH (op)));
-
-  if (GET_CODE (op) == CONST_INT)
-    return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
-	    || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
-	    || zap_mask (INTVAL (op)));
-
-  return register_operand (op, mode);
-}
-
-/* Return 1 if OP is a valid first operand to an IOR or XOR insn.  */
-
-int
-or_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
-	    || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
-
-  return register_operand (op, mode);
-}
-
-/* Return 1 if OP is a constant that is the width, in bits, of an integral
-   mode smaller than DImode.  */
-
-int
-mode_width_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT
-	  && (INTVAL (op) == 8 || INTVAL (op) == 16
-	      || INTVAL (op) == 32 || INTVAL (op) == 64));
-}
-
-/* Return 1 if OP is a constant that is the width of an integral machine mode
-   smaller than an integer.  */
-
-int
-mode_mask_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-#if HOST_BITS_PER_WIDE_INT == 32
-  if (GET_CODE (op) == CONST_DOUBLE)
-    return (CONST_DOUBLE_LOW (op) == -1
-	    && (CONST_DOUBLE_HIGH (op) == -1
-		|| CONST_DOUBLE_HIGH (op) == 0));
-#else
-  if (GET_CODE (op) == CONST_DOUBLE)
-    return (CONST_DOUBLE_LOW (op) == -1 && CONST_DOUBLE_HIGH (op) == 0);
-#endif
-
-  return (GET_CODE (op) == CONST_INT
-	  && (INTVAL (op) == 0xff
-	      || INTVAL (op) == 0xffff
-	      || INTVAL (op) == (HOST_WIDE_INT)0xffffffff
-#if HOST_BITS_PER_WIDE_INT == 64
-	      || INTVAL (op) == -1
-#endif
-	      ));
-}
-
-/* Return 1 if OP is a multiple of 8 less than 64.  */
-
-int
-mul8_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT
-	  && (unsigned HOST_WIDE_INT) INTVAL (op) < 64
-	  && (INTVAL (op) & 7) == 0);
-}
-
-/* Return 1 if OP is the constant zero in floating-point.  */
-
-int
-fp0_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return (GET_MODE (op) == mode
-	  && GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode));
-}
-
-/* Return 1 if OP is the floating-point constant zero or a register.  */
-
-int
-reg_or_fp0_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return fp0_operand (op, mode) || register_operand (op, mode);
-}
-
-/* Return 1 if OP is a hard floating-point register.  */
-
-int
-hard_fp_register_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return ((GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == FLOAT_REGS)
-	  || (GET_CODE (op) == SUBREG
-	      && hard_fp_register_operand (SUBREG_REG (op), mode)));
-}
-
-/* Return 1 if OP is a register or a constant integer.  */
-
-
-int
-reg_or_cint_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-     return (GET_CODE (op) == CONST_INT
-	     || register_operand (op, mode));
-}
-
-/* Return 1 if OP is something that can be reloaded into a register;
-   if it is a MEM, it need not be valid.  */
-
-int
-some_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
-    return 0;
-
-  switch (GET_CODE (op))
-    {
-    case REG:  case MEM:  case CONST_DOUBLE:  case CONST_INT:  case LABEL_REF:
-    case SYMBOL_REF:  case CONST:
-      return 1;
-
-    case SUBREG:
-      return some_operand (SUBREG_REG (op), VOIDmode);
-
-    default:
-      break;
-    }
-
-  return 0;
-}
-
-/* Return 1 if OP is a valid operand for the source of a move insn.  */
-
-int
-input_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
-    return 0;
-
-  if (GET_MODE_CLASS (mode) == MODE_FLOAT && GET_MODE (op) != mode)
-    return 0;
-
-  switch (GET_CODE (op))
-    {
-    case LABEL_REF:
-    case SYMBOL_REF:
-    case CONST:
-      /* This handles both the Windows/NT and OSF cases.  */
-      return mode == ptr_mode || mode == DImode;
-
-    case REG:
-      return 1;
-
-    case SUBREG:
-      if (register_operand (op, mode))
-	return 1;
-      /* ... fall through ... */
-    case MEM:
-      return ((TARGET_BWX || (mode != HImode && mode != QImode))
-	      && general_operand (op, mode));
-
-    case CONST_DOUBLE:
-      return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
-
-    case CONST_INT:
-      return mode == QImode || mode == HImode || add_operand (op, mode);
-
-    default:
-      break;
-    }
-
-  return 0;
-}
-
-/* Return 1 if OP is a SYMBOL_REF for a function known to be in this
-   file.  */
-
-int
-current_file_function_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == SYMBOL_REF
-	  && ! profile_flag && ! profile_block_flag
-	  && (SYMBOL_REF_FLAG (op)
-	      || op == XEXP (DECL_RTL (current_function_decl), 0)));
-}
-
-/* Return 1 if OP is a valid operand for the MEM of a CALL insn.  */
-
-int
-call_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (mode != Pmode)
-    return 0;
-
-  return (GET_CODE (op) == SYMBOL_REF
-	  || (GET_CODE (op) == REG
-	      && (TARGET_OPEN_VMS || TARGET_WINDOWS_NT || REGNO (op) == 27)));
-}
-
-/* Return 1 if OP is a valid Alpha comparison operator.  Here we know which
-   comparisons are valid in which insn.  */
-
-int
-alpha_comparison_operator (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  enum rtx_code code = GET_CODE (op);
-
-  if (mode != GET_MODE (op) || GET_RTX_CLASS (code) != '<')
-    return 0;
-
-  return (code == EQ || code == LE || code == LT
-	  || (mode == DImode && (code == LEU || code == LTU)));
-}
-
-/* Return 1 if OP is a valid Alpha swapped comparison operator.  */
-
-int
-alpha_swapped_comparison_operator (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  enum rtx_code code = GET_CODE (op);
-
-  if (mode != GET_MODE (op) || GET_RTX_CLASS (code) != '<')
-    return 0;
-
-  code = swap_condition (code);
-  return (code == EQ || code == LE || code == LT
-	  || (mode == DImode && (code == LEU || code == LTU)));
-}
-
-/* Return 1 if OP is a signed comparison operation.  */
-
-int
-signed_comparison_operator (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  switch (GET_CODE (op))
-    {
-    case EQ:  case NE:  case LE:  case LT:  case GE:   case GT:
-      return 1;
-
-    default:
-      break;
-    }
-
-  return 0;
-}
-
-/* Return 1 if this is a divide or modulus operator.  */
-
-int
-divmod_operator (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  switch (GET_CODE (op))
-    {
-    case DIV:  case MOD:  case UDIV:  case UMOD:
-      return 1;
-
-    default:
-      break;
-    }
-
-  return 0;
-}
-
-/* Return 1 if this memory address is a known aligned register plus
-   a constant.  It must be a valid address.  This means that we can do
-   this as an aligned reference plus some offset.
-
-   Take into account what reload will do.
-
-   We could say that out-of-range stack slots are alignable, but that would
-   complicate get_aligned_mem and it isn't worth the trouble since few
-   functions have large stack space.  */
-
-int
-aligned_memory_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == SUBREG)
-    {
-      if (GET_MODE (op) != mode)
-	return 0;
-      op = SUBREG_REG (op);
-      mode = GET_MODE (op);
-    }
-
-  if (reload_in_progress && GET_CODE (op) == REG
-      && REGNO (op) >= FIRST_PSEUDO_REGISTER)
-    op = reg_equiv_mem[REGNO (op)];
-
-  if (GET_CODE (op) != MEM || GET_MODE (op) != mode
-      || ! memory_address_p (mode, XEXP (op, 0)))
-    return 0;
-
-  op = XEXP (op, 0);
-
-  if (GET_CODE (op) == PLUS)
-    op = XEXP (op, 0);
-
-  return (GET_CODE (op) == REG
-	  && REGNO_POINTER_ALIGN (REGNO (op)) >= 4);
-}
-
-/* Similar, but return 1 if OP is a MEM which is not alignable.  */
-
-int
-unaligned_memory_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == SUBREG)
-    {
-      if (GET_MODE (op) != mode)
-	return 0;
-      op = SUBREG_REG (op);
-      mode = GET_MODE (op);
-    }
-
-  if (reload_in_progress && GET_CODE (op) == REG
-      && REGNO (op) >= FIRST_PSEUDO_REGISTER)
-    op = reg_equiv_mem[REGNO (op)];
-
-  if (GET_CODE (op) != MEM || GET_MODE (op) != mode)
-    return 0;
-
-  op = XEXP (op, 0);
-
-  if (! memory_address_p (mode, op))
-    return 1;
-
-  if (GET_CODE (op) == PLUS)
-    op = XEXP (op, 0);
-
-  return (GET_CODE (op) != REG
-	  || REGNO_POINTER_ALIGN (REGNO (op)) < 4);
-}
-
-/* Return 1 if OP is either a register or an unaligned memory location.  */
-
-int
-reg_or_unaligned_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return register_operand (op, mode) || unaligned_memory_operand (op, mode);
-}
-
-/* Return 1 if OP is any memory location.  During reload a pseudo matches.  */
-
-int
-any_memory_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == MEM
-	  || (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
-	  || (reload_in_progress && GET_CODE (op) == REG
-	      && REGNO (op) >= FIRST_PSEUDO_REGISTER)
-	  || (reload_in_progress && GET_CODE (op) == SUBREG
-	      && GET_CODE (SUBREG_REG (op)) == REG
-	      && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
-}
-
-/* Returns 1 if OP is not an eliminable register.
-
-   This exists to cure a pathological abort in the s8addq (et al) patterns,
-
-	long foo () { long t; bar(); return (long) &t * 26107; }
-
-   which run afoul of a hack in reload to cure a (presumably) similar
-   problem with lea-type instructions on other targets.  But there is
-   one of us and many of them, so work around the problem by selectively
-   preventing combine from making the optimization.  */
-
-int
-reg_not_elim_operand (op, mode)
-      register rtx op;
-      enum machine_mode mode;
-{
-  rtx inner = op;
-  if (GET_CODE (op) == SUBREG)
-    inner = SUBREG_REG (op);
-  if (inner == frame_pointer_rtx || inner == arg_pointer_rtx)
-    return 0;
-
-  return register_operand (op, mode);
-}
-
-/* Return 1 if this function can directly return via $26.  */
-
-int
-direct_return ()
-{
-  return (! TARGET_OPEN_VMS && reload_completed && alpha_sa_size () == 0
-	  && get_frame_size () == 0
-	  && current_function_outgoing_args_size == 0
-	  && current_function_pretend_args_size == 0);
-}
-
-/* REF is an alignable memory location.  Place an aligned SImode
-   reference into *PALIGNED_MEM and the number of bits to shift into
-   *PBITNUM.  */
-
-void
-get_aligned_mem (ref, paligned_mem, pbitnum)
-     rtx ref;
-     rtx *paligned_mem, *pbitnum;
-{
-  rtx base;
-  HOST_WIDE_INT offset = 0;
-
-  if (GET_CODE (ref) == SUBREG)
-    {
-      offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
-      if (BYTES_BIG_ENDIAN)
-	offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
-		   - MIN (UNITS_PER_WORD,
-			  GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
-      ref = SUBREG_REG (ref);
-    }
-
-  if (GET_CODE (ref) == REG)
-    ref = reg_equiv_mem[REGNO (ref)];
-
-  if (reload_in_progress)
-    base = find_replacement (&XEXP (ref, 0));
-  else
-    base = XEXP (ref, 0);
-
-  if (GET_CODE (base) == PLUS)
-    offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
-
-  *paligned_mem = gen_rtx_MEM (SImode, plus_constant (base, offset & ~3));
-  MEM_COPY_ATTRIBUTES (*paligned_mem, ref);
-  RTX_UNCHANGING_P (*paligned_mem) = RTX_UNCHANGING_P (ref);
-
-  /* Sadly, we cannot use alias sets here because we may overlap other
-     data in a different alias set.  */
-  /* MEM_ALIAS_SET (*paligned_mem) = MEM_ALIAS_SET (ref); */
-
-  *pbitnum = GEN_INT ((offset & 3) * 8);
-}
-
-/* Similar, but just get the address.  Handle the two reload cases.  
-   Add EXTRA_OFFSET to the address we return.  */
-
-rtx
-get_unaligned_address (ref, extra_offset)
-     rtx ref;
-     int extra_offset;
-{
-  rtx base;
-  HOST_WIDE_INT offset = 0;
-
-  if (GET_CODE (ref) == SUBREG)
-    {
-      offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
-      if (BYTES_BIG_ENDIAN)
-	offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
-		   - MIN (UNITS_PER_WORD,
-			  GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
-      ref = SUBREG_REG (ref);
-    }
-
-  if (GET_CODE (ref) == REG)
-    ref = reg_equiv_mem[REGNO (ref)];
-
-  if (reload_in_progress)
-    base = find_replacement (&XEXP (ref, 0));
-  else
-    base = XEXP (ref, 0);
-
-  if (GET_CODE (base) == PLUS)
-    offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
-
-  return plus_constant (base, offset + extra_offset);
-}
-
-/* Subfunction of the following function.  Update the flags of any MEM
-   found in part of X.  */
-
-static void
-alpha_set_memflags_1 (x, in_struct_p, volatile_p, unchanging_p)
-     rtx x;
-     int in_struct_p, volatile_p, unchanging_p;
-{
-  int i;
-
-  switch (GET_CODE (x))
-    {
-    case SEQUENCE:
-    case PARALLEL:
-      for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
-	alpha_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
-			      unchanging_p);
-      break;
-
-    case INSN:
-      alpha_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
-			    unchanging_p);
-      break;
-
-    case SET:
-      alpha_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
-			    unchanging_p);
-      alpha_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p,
-			    unchanging_p);
-      break;
-
-    case MEM:
-      MEM_IN_STRUCT_P (x) = in_struct_p;
-      MEM_VOLATILE_P (x) = volatile_p;
-      RTX_UNCHANGING_P (x) = unchanging_p;
-      /* Sadly, we cannot use alias sets because the extra aliasing
-	 produced by the AND interferes.  Given that two-byte quantities
-	 are the only thing we would be able to differentiate anyway,
-	 there does not seem to be any point in convoluting the early
-	 out of the alias check.  */
-      /* MEM_ALIAS_SET (x) = alias_set; */
-      break;
-
-    default:
-      break;
-    }
-}
-
-/* Given INSN, which is either an INSN or a SEQUENCE generated to
-   perform a memory operation, look for any MEMs in either a SET_DEST or
-   a SET_SRC and copy the in-struct, unchanging, and volatile flags from
-   REF into each of the MEMs found.  If REF is not a MEM, don't do
-   anything.  */
-
-void
-alpha_set_memflags (insn, ref)
-     rtx insn;
-     rtx ref;
-{
-  int in_struct_p, volatile_p, unchanging_p;
-
-  if (GET_CODE (ref) != MEM)
-    return;
-
-  in_struct_p = MEM_IN_STRUCT_P (ref);
-  volatile_p = MEM_VOLATILE_P (ref);
-  unchanging_p = RTX_UNCHANGING_P (ref);
-
-  /* This is only called from alpha.md, after having had something 
-     generated from one of the insn patterns.  So if everything is
-     zero, the pattern is already up-to-date.  */
-  if (! in_struct_p && ! volatile_p && ! unchanging_p)
-    return;
-
-  alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p);
-}
-
-/* Try to output insns to set TARGET equal to the constant C if it can be
-   done in less than N insns.  Do all computations in MODE.  Returns the place
-   where the output has been placed if it can be done and the insns have been
-   emitted.  If it would take more than N insns, zero is returned and no
-   insns and emitted.  */
-
-rtx
-alpha_emit_set_const (target, mode, c, n)
-     rtx target;
-     enum machine_mode mode;
-     HOST_WIDE_INT c;
-     int n;
-{
-  rtx pat;
-  int i;
-
-  /* Try 1 insn, then 2, then up to N. */
-  for (i = 1; i <= n; i++)
-    if ((pat = alpha_emit_set_const_1 (target, mode, c, i)) != 0)
-      return pat;
-
-  return 0;
-}
-
-/* Internal routine for the above to check for N or below insns.  */
-
-static rtx
-alpha_emit_set_const_1 (target, mode, c, n)
-     rtx target;
-     enum machine_mode mode;
-     HOST_WIDE_INT c;
-     int n;
-{
-  HOST_WIDE_INT new = c;
-  int i, bits;
-  /* Use a pseudo if highly optimizing and still generating RTL.  */
-  rtx subtarget
-    = (flag_expensive_optimizations && rtx_equal_function_value_matters
-       ? 0 : target);
-  rtx temp;
-
-#if HOST_BITS_PER_WIDE_INT == 64
-  /* We are only called for SImode and DImode.  If this is SImode, ensure that
-     we are sign extended to a full word.  This does not make any sense when
-     cross-compiling on a narrow machine.  */
-
-  if (mode == SImode)
-    c = (c & 0xffffffff) - 2 * (c & 0x80000000);
-#endif
-
-  /* If this is a sign-extended 32-bit constant, we can do this in at most
-     three insns, so do it if we have enough insns left.  We always have
-     a sign-extended 32-bit constant when compiling on a narrow machine.   */
-
-  if (HOST_BITS_PER_WIDE_INT != 64
-      || c >> 31 == -1 || c >> 31 == 0)
-    {
-      HOST_WIDE_INT low = (c & 0xffff) - 2 * (c & 0x8000);
-      HOST_WIDE_INT tmp1 = c - low;
-      HOST_WIDE_INT high
-	= ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
-      HOST_WIDE_INT extra = 0;
-
-      /* If HIGH will be interpreted as negative but the constant is
-	 positive, we must adjust it to do two ldha insns.  */
-
-      if ((high & 0x8000) != 0 && c >= 0)
-	{
-	  extra = 0x4000;
-	  tmp1 -= 0x40000000;
-	  high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
-	}
-
-      if (c == low || (low == 0 && extra == 0))
-	{
-	  /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
-	     but that meant that we can't handle INT_MIN on 32-bit machines
-	     (like NT/Alpha), because we recurse indefinitely through 
-	     emit_move_insn to gen_movdi.  So instead, since we know exactly
-	     what we want, create it explicitly.  */
-
-	  if (target == NULL)
-	    target = gen_reg_rtx (mode);
-	  emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
-	  return target;
-	}
-      else if (n >= 2 + (extra != 0))
-	{
-	  temp = copy_to_suggested_reg (GEN_INT (low), subtarget, mode);
-
-	  if (extra != 0)
-	    temp = expand_binop (mode, add_optab, temp, GEN_INT (extra << 16),
-				 subtarget, 0, OPTAB_WIDEN);
-
-	  return expand_binop (mode, add_optab, temp, GEN_INT (high << 16),
-			       target, 0, OPTAB_WIDEN);
-	}
-    }
-
-  /* If we couldn't do it that way, try some other methods.  But if we have
-     no instructions left, don't bother.  Likewise, if this is SImode and
-     we can't make pseudos, we can't do anything since the expand_binop
-     and expand_unop calls will widen and try to make pseudos.  */
-
-  if (n == 1
-      || (mode == SImode && ! rtx_equal_function_value_matters))
-    return 0;
-
-#if HOST_BITS_PER_WIDE_INT == 64
-  /* First, see if can load a value into the target that is the same as the
-     constant except that all bytes that are 0 are changed to be 0xff.  If we
-     can, then we can do a ZAPNOT to obtain the desired constant.  */
-
-  for (i = 0; i < 64; i += 8)
-    if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0)
-      new |= (HOST_WIDE_INT) 0xff << i;
-
-  /* We are only called for SImode and DImode.  If this is SImode, ensure that
-     we are sign extended to a full word.  */
-
-  if (mode == SImode)
-    new = (new & 0xffffffff) - 2 * (new & 0x80000000);
-
-  if (new != c
-      && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0)
-    return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new),
-			 target, 0, OPTAB_WIDEN);
-#endif
-
-  /* Next, see if we can load a related constant and then shift and possibly
-     negate it to get the constant we want.  Try this once each increasing
-     numbers of insns.  */
-
-  for (i = 1; i < n; i++)
-    {
-      /* First try complementing.  */
-      if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0)
-	return expand_unop (mode, one_cmpl_optab, temp, target, 0);
-
-      /* Next try to form a constant and do a left shift.  We can do this
-	 if some low-order bits are zero; the exact_log2 call below tells
-	 us that information.  The bits we are shifting out could be any
-	 value, but here we'll just try the 0- and sign-extended forms of
-	 the constant.  To try to increase the chance of having the same
-	 constant in more than one insn, start at the highest number of
-	 bits to shift, but try all possibilities in case a ZAPNOT will
-	 be useful.  */
-
-      if ((bits = exact_log2 (c & - c)) > 0)
-	for (; bits > 0; bits--)
-	  if ((temp = (alpha_emit_set_const
-		       (subtarget, mode,
-			(unsigned HOST_WIDE_INT) (c >> bits), i))) != 0
-	      || ((temp = (alpha_emit_set_const
-			  (subtarget, mode,
-			   ((unsigned HOST_WIDE_INT) c) >> bits, i)))
-		  != 0))
-	    return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
-				 target, 0, OPTAB_WIDEN);
-
-      /* Now try high-order zero bits.  Here we try the shifted-in bits as
-	 all zero and all ones.  Be careful to avoid shifting outside the
-	 mode and to avoid shifting outside the host wide int size.  */
-      /* On narrow hosts, don't shift a 1 into the high bit, since we'll
-	 confuse the recursive call and set all of the high 32 bits.  */
-
-      if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
-		   - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
-	for (; bits > 0; bits--)
-	  if ((temp = alpha_emit_set_const (subtarget, mode,
-					    c << bits, i)) != 0
-	      || ((temp = (alpha_emit_set_const
-			   (subtarget, mode,
-			    ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
-			    i)))
-		  != 0))
-	    return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
-				 target, 1, OPTAB_WIDEN);
-
-      /* Now try high-order 1 bits.  We get that with a sign-extension.
-	 But one bit isn't enough here.  Be careful to avoid shifting outside
-	 the mode and to avoid shifting outside the host wide int size. */
-      
-      if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
-		   - floor_log2 (~ c) - 2)) > 0)
-	for (; bits > 0; bits--)
-	  if ((temp = alpha_emit_set_const (subtarget, mode,
-					    c << bits, i)) != 0
-	      || ((temp = (alpha_emit_set_const
-			   (subtarget, mode,
-			    ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
-			    i)))
-		  != 0))
-	    return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
-				 target, 0, OPTAB_WIDEN);
-    }
-
-  return 0;
-}
-
-/* Having failed to find a 3 insn sequence in alpha_emit_set_const,
-   fall back to a straight forward decomposition.  We do this to avoid
-   exponential run times encountered when looking for longer sequences
-   with alpha_emit_set_const.  */
-
-rtx
-alpha_emit_set_long_const (target, c1, c2)
-     rtx target;
-     HOST_WIDE_INT c1, c2;
-{
-  HOST_WIDE_INT d1, d2, d3, d4;
-
-  /* Decompose the entire word */
-#if HOST_BITS_PER_WIDE_INT >= 64
-  if (c2 != -(c1 < 0))
-    abort ();
-  d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
-  c1 -= d1;
-  d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
-  c1 = (c1 - d2) >> 32;
-  d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
-  c1 -= d3;
-  d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
-  if (c1 != d4)
-    abort ();
-#else
-  d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
-  c1 -= d1;
-  d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
-  if (c1 != d2)
-    abort ();
-  c2 += (d2 < 0);
-  d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
-  c2 -= d3;
-  d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
-  if (c2 != d4)
-    abort ();
-#endif
-
-  /* Construct the high word */
-  if (d4)
-    {
-      emit_move_insn (target, GEN_INT (d4));
-      if (d3)
-	emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
-    }
-  else
-    emit_move_insn (target, GEN_INT (d3));
-
-  /* Shift it into place */
-  emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
-
-  /* Add in the low bits.  */
-  if (d2)
-    emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
-  if (d1)
-    emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
-
-  return target;
-}
-
-/* Generate the comparison for a conditional branch.  */
-
-rtx
-alpha_emit_conditional_branch (code)
-     enum rtx_code code;
-{
-  enum rtx_code cmp_code, branch_code;
-  enum machine_mode cmp_mode, branch_mode = VOIDmode;
-  rtx op0 = alpha_compare_op0, op1 = alpha_compare_op1;
-  rtx tem;
-
-  /* The general case: fold the comparison code to the types of compares
-     that we have, choosing the branch as necessary.  */
-  switch (code)
-    {
-    case EQ:  case LE:  case LT:  case LEU:  case LTU:
-      /* We have these compares: */
-      cmp_code = code, branch_code = NE;
-      break;
-
-    case NE:
-      /* This must be reversed. */
-      cmp_code = EQ, branch_code = EQ;
-      break;
-
-    case GE:  case GT: case GEU:  case GTU:
-      /* For FP, we swap them, for INT, we reverse them.  */
-      if (alpha_compare_fp_p)
-	{
-	  cmp_code = swap_condition (code);
-	  branch_code = NE;
-	  tem = op0, op0 = op1, op1 = tem;
-	}
-      else
-	{
-	  cmp_code = reverse_condition (code);
-	  branch_code = EQ;
-	}
-      break;
-
-    default:
-      abort ();
-    }
-
-  if (alpha_compare_fp_p)
-    {
-      cmp_mode = DFmode;
-      if (flag_fast_math)
-	{
-	  /* When we are not as concerned about non-finite values, and we
-	     are comparing against zero, we can branch directly.  */
-	  if (op1 == CONST0_RTX (DFmode))
-	    cmp_code = NIL, branch_code = code;
-	  else if (op0 == CONST0_RTX (DFmode))
-	    {
-	      /* Undo the swap we probably did just above.  */
-	      tem = op0, op0 = op1, op1 = tem;
-	      branch_code = swap_condition (cmp_code);
-	      cmp_code = NIL;
-	    }
-	}
-      else
-	{
-	  /* ??? We mark the the branch mode to be CCmode to prevent the
-	     compare and branch from being combined, since the compare 
-	     insn follows IEEE rules that the branch does not.  */
-	  branch_mode = CCmode;
-	}
-    }
-  else
-    {
-      cmp_mode = DImode;
-
-      /* The following optimizations are only for signed compares.  */
-      if (code != LEU && code != LTU && code != GEU && code != GTU)
-	{
-	  /* Whee.  Compare and branch against 0 directly.  */
-	  if (op1 == const0_rtx)
-	    cmp_code = NIL, branch_code = code;
-
-	  /* We want to use cmpcc/bcc when we can, since there is a zero delay
-	     bypass between logicals and br/cmov on EV5.  But we don't want to
-	     force valid immediate constants into registers needlessly.  */
-	  else if (GET_CODE (op1) == CONST_INT)
-	    {
-	      HOST_WIDE_INT v = INTVAL (op1), n = -v;
-
-	      if (! CONST_OK_FOR_LETTER_P (v, 'I')
-		  && (CONST_OK_FOR_LETTER_P (n, 'K')
-		      || CONST_OK_FOR_LETTER_P (n, 'L')))
-		{
-		  cmp_code = PLUS, branch_code = code;
-		  op1 = GEN_INT (n);
-		}
-	    }
-	}
-    }
-
-  /* Force op0 into a register.  */
-  if (GET_CODE (op0) != REG)
-    op0 = force_reg (cmp_mode, op0);
-
-  /* Emit an initial compare instruction, if necessary.  */
-  tem = op0;
-  if (cmp_code != NIL)
-    {
-      tem = gen_reg_rtx (cmp_mode);
-      emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
-    }
-
-  /* Return the branch comparison.  */
-  return gen_rtx_fmt_ee (branch_code, branch_mode, tem, CONST0_RTX (cmp_mode));
-}
-
-
-/* Rewrite a comparison against zero CMP of the form
-   (CODE (cc0) (const_int 0)) so it can be written validly in
-   a conditional move (if_then_else CMP ...).
-   If both of the operands that set cc0 are non-zero we must emit
-   an insn to perform the compare (it can't be done within
-   the conditional move). */
-rtx
-alpha_emit_conditional_move (cmp, mode)
-     rtx cmp;
-     enum machine_mode mode;
-{
-  enum rtx_code code = GET_CODE (cmp);
-  enum rtx_code cmov_code = NE;
-  rtx op0 = alpha_compare_op0;
-  rtx op1 = alpha_compare_op1;
-  enum machine_mode cmp_mode
-    = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
-  enum machine_mode cmp_op_mode = alpha_compare_fp_p ? DFmode : DImode;
-  enum machine_mode cmov_mode = VOIDmode;
-  rtx tem;
-
-  if (alpha_compare_fp_p != FLOAT_MODE_P (mode))
-    return 0;
-
-  /* We may be able to use a conditional move directly.
-     This avoids emitting spurious compares. */
-  if (signed_comparison_operator (cmp, cmp_op_mode)
-      && (!alpha_compare_fp_p || flag_fast_math)
-      && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
-    return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
-
-  /* We can't put the comparison insides a conditional move;
-     emit a compare instruction and put that inside the
-     conditional move.  Make sure we emit only comparisons we have;
-     swap or reverse as necessary.  */
-
-  switch (code)
-    {
-    case EQ:  case LE:  case LT:  case LEU:  case LTU:
-      /* We have these compares: */
-      break;
-
-    case NE:
-      /* This must be reversed. */
-      code = reverse_condition (code);
-      cmov_code = EQ;
-      break;
-
-    case GE:  case GT:  case GEU:  case GTU:
-      /* These must be swapped.  Make sure the new first operand is in
-	 a register.  */
-      code = swap_condition (code);
-      tem = op0, op0 = op1, op1 = tem;
-      op0 = force_reg (cmp_mode, op0);
-      break;
-
-    default:
-      abort ();
-    }
-
-  /* ??? We mark the branch mode to be CCmode to prevent the compare
-     and cmov from being combined, since the compare insn follows IEEE
-     rules that the cmov does not.  */
-  if (alpha_compare_fp_p && !flag_fast_math)
-    cmov_mode = CCmode;
-
-  tem = gen_reg_rtx (cmp_op_mode);
-  emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_op_mode, op0, op1));
-  return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_op_mode));
-}
-
-/* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
-   unaligned data:
-
-           unsigned:                       signed:
-   word:   ldq_u  r1,X(r11)                ldq_u  r1,X(r11)
-           ldq_u  r2,X+1(r11)              ldq_u  r2,X+1(r11)
-           lda    r3,X(r11)                lda    r3,X+2(r11)
-           extwl  r1,r3,r1                 extql  r1,r3,r1
-           extwh  r2,r3,r2                 extqh  r2,r3,r2
-           or     r1.r2.r1                 or     r1,r2,r1
-                                           sra    r1,48,r1
-
-   long:   ldq_u  r1,X(r11)                ldq_u  r1,X(r11)
-           ldq_u  r2,X+3(r11)              ldq_u  r2,X+3(r11)
-           lda    r3,X(r11)                lda    r3,X(r11)
-           extll  r1,r3,r1                 extll  r1,r3,r1
-           extlh  r2,r3,r2                 extlh  r2,r3,r2
-           or     r1.r2.r1                 addl   r1,r2,r1
-
-   quad:   ldq_u  r1,X(r11)
-           ldq_u  r2,X+7(r11)
-           lda    r3,X(r11)
-           extql  r1,r3,r1
-           extqh  r2,r3,r2
-           or     r1.r2.r1
-*/
-
-void
-alpha_expand_unaligned_load (tgt, mem, size, ofs, sign)
-     rtx tgt, mem;
-     HOST_WIDE_INT size, ofs;
-     int sign;
-{
-  rtx meml, memh, addr, extl, exth;
-  enum machine_mode mode;
-
-  meml = gen_reg_rtx (DImode);
-  memh = gen_reg_rtx (DImode);
-  addr = gen_reg_rtx (DImode);
-  extl = gen_reg_rtx (DImode);
-  exth = gen_reg_rtx (DImode);
-
-  emit_move_insn (meml,
-		  change_address (mem, DImode,
-				  gen_rtx_AND (DImode, 
-					       plus_constant (XEXP (mem, 0),
-							      ofs),
-					       GEN_INT (-8))));
-
-  emit_move_insn (memh,
-		  change_address (mem, DImode,
-				  gen_rtx_AND (DImode, 
-					       plus_constant (XEXP (mem, 0),
-							      ofs + size - 1),
-					       GEN_INT (-8))));
-
-  if (sign && size == 2)
-    {
-      emit_move_insn (addr, plus_constant (XEXP (mem, 0), ofs+2));
-
-      emit_insn (gen_extxl (extl, meml, GEN_INT (64), addr));
-      emit_insn (gen_extqh (exth, memh, addr));
-
-      /* We must use tgt here for the target.  Alpha-vms port fails if we use
-	 addr for the target, because addr is marked as a pointer and combine
-	 knows that pointers are always sign-extended 32 bit values.  */
-      addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
-      addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48), 
-			   addr, 1, OPTAB_WIDEN);
-    }
-  else
-    {
-      emit_move_insn (addr, plus_constant (XEXP (mem, 0), ofs));
-      emit_insn (gen_extxl (extl, meml, GEN_INT (size*8), addr));
-      switch (size)
-	{
-	case 2:
-	  emit_insn (gen_extwh (exth, memh, addr));
-	  mode = HImode;
-	  break;
-
-	case 4:
-	  emit_insn (gen_extlh (exth, memh, addr));
-	  mode = SImode;
-	  break;
-
-	case 8:
-	  emit_insn (gen_extqh (exth, memh, addr));
-	  mode = DImode;
-	  break;
-	}
-
-      addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
-			   gen_lowpart (mode, exth), gen_lowpart (mode, tgt),
-			   sign, OPTAB_WIDEN);
-    }
-
-  if (addr != tgt)
-    emit_move_insn (tgt, gen_lowpart(GET_MODE (tgt), addr));
-}
-
-/* Similarly, use ins and msk instructions to perform unaligned stores.  */
-
-void
-alpha_expand_unaligned_store (dst, src, size, ofs)
-     rtx dst, src;
-     HOST_WIDE_INT size, ofs;
-{
-  rtx dstl, dsth, addr, insl, insh, meml, memh;
-  
-  dstl = gen_reg_rtx (DImode);
-  dsth = gen_reg_rtx (DImode);
-  insl = gen_reg_rtx (DImode);
-  insh = gen_reg_rtx (DImode);
-
-  meml = change_address (dst, DImode,
-			 gen_rtx_AND (DImode, 
-				      plus_constant (XEXP (dst, 0), ofs),
-				      GEN_INT (-8)));
-  memh = change_address (dst, DImode,
-			 gen_rtx_AND (DImode, 
-				      plus_constant (XEXP (dst, 0),
-						     ofs+size-1),
-				      GEN_INT (-8)));
-
-  emit_move_insn (dsth, memh);
-  emit_move_insn (dstl, meml);
-  addr = copy_addr_to_reg (plus_constant (XEXP (dst, 0), ofs));
-
-  if (src != const0_rtx)
-    {
-      emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
-			    GEN_INT (size*8), addr));
-
-      switch (size)
-	{
-	case 2:
-	  emit_insn (gen_inswl (insl, gen_lowpart (HImode, src), addr));
-	  break;
-	case 4:
-	  emit_insn (gen_insll (insl, gen_lowpart (SImode, src), addr));
-	  break;
-	case 8:
-	  emit_insn (gen_insql (insl, src, addr));
-	  break;
-	}
-    }
-
-  emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
-
-  switch (size)
-    {
-    case 2:
-      emit_insn (gen_mskxl (dstl, dstl, GEN_INT (0xffff), addr));
-      break;
-    case 4:
-      emit_insn (gen_mskxl (dstl, dstl, GEN_INT (0xffffffff), addr));
-      break;
-    case 8:
-      {
-#if HOST_BITS_PER_WIDE_INT == 32
-	rtx msk = immed_double_const (0xffffffff, 0xffffffff, DImode);
-#else
-	rtx msk = immed_double_const (0xffffffffffffffff, 0, DImode);
-#endif
-	emit_insn (gen_mskxl (dstl, dstl, msk, addr));
-      }
-      break;
-    }
-
-  if (src != const0_rtx)
-    {
-      dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
-      dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
-    }
-  
-  /* Must store high before low for degenerate case of aligned.  */
-  emit_move_insn (memh, dsth);
-  emit_move_insn (meml, dstl);
-}
-
-/* The block move code tries to maximize speed by separating loads and
-   stores at the expense of register pressure: we load all of the data
-   before we store it back out.  There are two secondary effects worth
-   mentioning, that this speeds copying to/from aligned and unaligned
-   buffers, and that it makes the code significantly easier to write.  */
-
-#define MAX_MOVE_WORDS	8
-
-/* Load an integral number of consecutive unaligned quadwords.  */
-
-static void
-alpha_expand_unaligned_load_words (out_regs, smem, words, ofs)
-     rtx *out_regs;
-     rtx smem;
-     HOST_WIDE_INT words, ofs;
-{
-  rtx const im8 = GEN_INT (-8);
-  rtx const i64 = GEN_INT (64);
-  rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
-  rtx sreg, areg;
-  HOST_WIDE_INT i;
-
-  /* Generate all the tmp registers we need.  */
-  for (i = 0; i < words; ++i)
-    {
-      data_regs[i] = out_regs[i];
-      ext_tmps[i] = gen_reg_rtx (DImode);
-    }
-  data_regs[words] = gen_reg_rtx (DImode);
-
-  if (ofs != 0)
-    smem = change_address (smem, GET_MODE (smem),
-			   plus_constant (XEXP (smem, 0), ofs));
-  
-  /* Load up all of the source data.  */
-  for (i = 0; i < words; ++i)
-    {
-      emit_move_insn (data_regs[i],
-		      change_address (smem, DImode,
-				      gen_rtx_AND (DImode,
-						   plus_constant (XEXP(smem,0),
-								  8*i),
-						   im8)));
-    }
-  emit_move_insn (data_regs[words],
-		  change_address (smem, DImode,
-				  gen_rtx_AND (DImode,
-					       plus_constant (XEXP(smem,0),
-							      8*words - 1),
-					       im8)));
-
-  /* Extract the half-word fragments.  Unfortunately DEC decided to make
-     extxh with offset zero a noop instead of zeroing the register, so 
-     we must take care of that edge condition ourselves with cmov.  */
-
-  sreg = copy_addr_to_reg (XEXP (smem, 0));
-  areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL, 
-		       1, OPTAB_WIDEN);
-  for (i = 0; i < words; ++i)
-    {
-      emit_insn (gen_extxl (data_regs[i], data_regs[i], i64, sreg));
-
-      emit_insn (gen_extqh (ext_tmps[i], data_regs[i+1], sreg));
-      emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
-			      gen_rtx_IF_THEN_ELSE (DImode,
-						    gen_rtx_EQ (DImode, areg,
-								const0_rtx),
-						    const0_rtx, ext_tmps[i])));
-    }
-
-  /* Merge the half-words into whole words.  */
-  for (i = 0; i < words; ++i)
-    {
-      out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
-				  ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
-    }
-}
-
-/* Store an integral number of consecutive unaligned quadwords.  DATA_REGS
-   may be NULL to store zeros.  */
-
-static void
-alpha_expand_unaligned_store_words (data_regs, dmem, words, ofs)
-     rtx *data_regs;
-     rtx dmem;
-     HOST_WIDE_INT words, ofs;
-{
-  rtx const im8 = GEN_INT (-8);
-  rtx const i64 = GEN_INT (64);
-#if HOST_BITS_PER_WIDE_INT == 32
-  rtx const im1 = immed_double_const (0xffffffff, 0xffffffff, DImode);
-#else
-  rtx const im1 = immed_double_const (0xffffffffffffffff, 0, DImode);
-#endif
-  rtx ins_tmps[MAX_MOVE_WORDS];
-  rtx st_tmp_1, st_tmp_2, dreg;
-  rtx st_addr_1, st_addr_2;
-  HOST_WIDE_INT i;
-
-  /* Generate all the tmp registers we need.  */
-  if (data_regs != NULL)
-    for (i = 0; i < words; ++i)
-      ins_tmps[i] = gen_reg_rtx(DImode);
-  st_tmp_1 = gen_reg_rtx(DImode);
-  st_tmp_2 = gen_reg_rtx(DImode);
-  
-  if (ofs != 0)
-    dmem = change_address (dmem, GET_MODE (dmem),
-			   plus_constant (XEXP (dmem, 0), ofs));
-  
-
-  st_addr_2 = change_address (dmem, DImode,
-			      gen_rtx_AND (DImode,
-					   plus_constant (XEXP(dmem,0),
-							  words*8 - 1),
-				       im8));
-  st_addr_1 = change_address (dmem, DImode,
-			      gen_rtx_AND (DImode, 
-					   XEXP (dmem, 0),
-					   im8));
-
-  /* Load up the destination end bits.  */
-  emit_move_insn (st_tmp_2, st_addr_2);
-  emit_move_insn (st_tmp_1, st_addr_1);
-
-  /* Shift the input data into place.  */
-  dreg = copy_addr_to_reg (XEXP (dmem, 0));
-  if (data_regs != NULL)
-    {
-      for (i = words-1; i >= 0; --i)
-	{
-	  emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
-	  emit_insn (gen_insql (data_regs[i], data_regs[i], dreg));
-	}
-      for (i = words-1; i > 0; --i)
-	{
-	  ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
-					ins_tmps[i-1], ins_tmps[i-1], 1,
-					OPTAB_WIDEN);
-	}
-    }
-
-  /* Split and merge the ends with the destination data.  */
-  emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
-  emit_insn (gen_mskxl (st_tmp_1, st_tmp_1, im1, dreg));
-
-  if (data_regs != NULL)
-    {
-      st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1],
-			       st_tmp_2, 1, OPTAB_WIDEN);
-      st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
-			       st_tmp_1, 1, OPTAB_WIDEN);
-    }
-
-  /* Store it all.  */
-  emit_move_insn (st_addr_2, st_tmp_2);
-  for (i = words-1; i > 0; --i)
-    {
-      emit_move_insn (change_address (dmem, DImode,
-				      gen_rtx_AND (DImode,
-						   plus_constant(XEXP (dmem,0),
-								 i*8),
-					       im8)),
-		      data_regs ? ins_tmps[i-1] : const0_rtx);
-    }
-  emit_move_insn (st_addr_1, st_tmp_1);
-}
-
-
-/* Expand string/block move operations.
-
-   operands[0] is the pointer to the destination.
-   operands[1] is the pointer to the source.
-   operands[2] is the number of bytes to move.
-   operands[3] is the alignment.  */
-
-int
-alpha_expand_block_move (operands)
-     rtx operands[];
-{
-  rtx bytes_rtx	= operands[2];
-  rtx align_rtx = operands[3];
-  HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
-  HOST_WIDE_INT bytes = orig_bytes;
-  HOST_WIDE_INT src_align = INTVAL (align_rtx);
-  HOST_WIDE_INT dst_align = src_align;
-  rtx orig_src	= operands[1];
-  rtx orig_dst	= operands[0];
-  rtx data_regs[2*MAX_MOVE_WORDS+16];
-  rtx tmp;
-  int i, words, ofs, nregs = 0;
-  
-  if (bytes <= 0)
-    return 1;
-  if (bytes > MAX_MOVE_WORDS*8)
-    return 0;
-
-  /* Look for additional alignment information from recorded register info.  */
-
-  tmp = XEXP (orig_src, 0);
-  if (GET_CODE (tmp) == REG)
-    {
-      if (REGNO_POINTER_ALIGN (REGNO (tmp)) > src_align)
-	src_align = REGNO_POINTER_ALIGN (REGNO (tmp));
-    }
-  else if (GET_CODE (tmp) == PLUS
-	   && GET_CODE (XEXP (tmp, 0)) == REG
-	   && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
-    {
-      HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
-      int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
-
-      if (a > src_align)
-	{
-          if (a >= 8 && c % 8 == 0)
-	    src_align = 8;
-          else if (a >= 4 && c % 4 == 0)
-	    src_align = 4;
-          else if (a >= 2 && c % 2 == 0)
-	    src_align = 2;
-	}
-    }
-	
-  tmp = XEXP (orig_dst, 0);
-  if (GET_CODE (tmp) == REG)
-    {
-      if (REGNO_POINTER_ALIGN (REGNO (tmp)) > dst_align)
-	dst_align = REGNO_POINTER_ALIGN (REGNO (tmp));
-    }
-  else if (GET_CODE (tmp) == PLUS
-	   && GET_CODE (XEXP (tmp, 0)) == REG
-	   && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
-    {
-      HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
-      int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
-
-      if (a > dst_align)
-	{
-          if (a >= 8 && c % 8 == 0)
-	    dst_align = 8;
-          else if (a >= 4 && c % 4 == 0)
-	    dst_align = 4;
-          else if (a >= 2 && c % 2 == 0)
-	    dst_align = 2;
-	}
-    }
-
-  /*
-   * Load the entire block into registers.
-   */
-
-  if (GET_CODE (XEXP (orig_src, 0)) == ADDRESSOF)
-    {
-      enum machine_mode mode;
-      tmp = XEXP (XEXP (orig_src, 0), 0);
-
-      mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
-      if (mode != BLKmode
-	  && GET_MODE_SIZE (GET_MODE (tmp)) <= bytes)
-	{
-	  /* Whee!  Optimize the load to use the existing register.  */
-	  data_regs[nregs++] = gen_lowpart (mode, tmp);
-	  goto src_done;
-	}
-
-      /* ??? We could potentially be copying 3 bytes or whatnot from
-	 a wider reg.  Probably not worth worrying about.  */
-      /* No appropriate mode; fall back on memory.  */
-      orig_src = change_address (orig_src, GET_MODE (orig_src),
-				 copy_addr_to_reg (XEXP (orig_src, 0)));
-    }
-
-  ofs = 0;
-  if (src_align >= 8 && bytes >= 8)
-    {
-      words = bytes / 8;
-
-      for (i = 0; i < words; ++i)
-	data_regs[nregs+i] = gen_reg_rtx(DImode);
-
-      for (i = 0; i < words; ++i)
-	{
-	  emit_move_insn (data_regs[nregs+i],
-			  change_address(orig_src, DImode,
-					 plus_constant (XEXP (orig_src, 0),
-							ofs + i*8)));
-	}
-
-      nregs += words;
-      bytes -= words * 8;
-      ofs += words * 8;
-    }
-  if (src_align >= 4 && bytes >= 4)
-    {
-      words = bytes / 4;
-
-      for (i = 0; i < words; ++i)
-	data_regs[nregs+i] = gen_reg_rtx(SImode);
-
-      for (i = 0; i < words; ++i)
-	{
-	  emit_move_insn (data_regs[nregs+i],
-			  change_address(orig_src, SImode,
-					 plus_constant (XEXP (orig_src, 0),
-							ofs + i*4)));
-	}
-
-      nregs += words;
-      bytes -= words * 4;
-      ofs += words * 4;
-    }
-  if (bytes >= 16)
-    {
-      words = bytes / 8;
-
-      for (i = 0; i < words+1; ++i)
-	data_regs[nregs+i] = gen_reg_rtx(DImode);
-
-      alpha_expand_unaligned_load_words(data_regs+nregs, orig_src, words, ofs);
-
-      nregs += words;
-      bytes -= words * 8;
-      ofs += words * 8;
-    }
-  if (!TARGET_BWX && bytes >= 8)
-    {
-      data_regs[nregs++] = tmp = gen_reg_rtx (DImode);
-      alpha_expand_unaligned_load (tmp, orig_src, 8, ofs, 0);
-      bytes -= 8;
-      ofs += 8;
-    }
-  if (!TARGET_BWX && bytes >= 4)
-    {
-      data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
-      alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
-      bytes -= 4;
-      ofs += 4;
-    }
-  if (bytes >= 2)
-    {
-      if (src_align >= 2)
-	{
-	  do {
-	    data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
-	    emit_move_insn (tmp,
-			    change_address (orig_src, HImode,
-					    plus_constant (XEXP (orig_src, 0),
-							   ofs)));
-	    bytes -= 2;
-	    ofs += 2;
-	  } while (bytes >= 2);
-	}
-      else if (!TARGET_BWX)
-	{
-	  data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
-	  alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
-	  bytes -= 2;
-	  ofs += 2;
-	}
-    }
-  while (bytes > 0)
-    {
-      data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
-      emit_move_insn (tmp,
-		      change_address (orig_src, QImode,
-				      plus_constant (XEXP (orig_src, 0),
-						     ofs)));
-      bytes -= 1;
-      ofs += 1;
-    }
- src_done:
-
-  if (nregs > (int)(sizeof(data_regs)/sizeof(*data_regs)))
-    abort();
-
-  /*
-   * Now save it back out again.
-   */
-
-  i = 0, ofs = 0;
-
-  if (GET_CODE (XEXP (orig_dst, 0)) == ADDRESSOF)
-    {
-      enum machine_mode mode;
-      tmp = XEXP (XEXP (orig_dst, 0), 0);
-
-      mode = mode_for_size (orig_bytes * BITS_PER_UNIT, MODE_INT, 1);
-      if (GET_MODE (tmp) == mode && nregs == 1)
-	{
-	  emit_move_insn (tmp, data_regs[0]);
-	  i = 1;
-	  goto dst_done;
-	}
-
-      /* ??? If nregs > 1, consider reconstructing the word in regs.  */
-      /* ??? Optimize mode < dst_mode with strict_low_part.  */
-
-      /* No appropriate mode; fall back on memory.  We can speed things
-	 up by recognizing extra alignment information.  */
-      orig_dst = change_address (orig_dst, GET_MODE (orig_dst),
-				 copy_addr_to_reg (XEXP (orig_dst, 0)));
-      dst_align = GET_MODE_SIZE (GET_MODE (tmp));
-    }
-
-  /* Write out the data in whatever chunks reading the source allowed.  */
-  if (dst_align >= 8)
-    {
-      while (i < nregs && GET_MODE (data_regs[i]) == DImode)
-	{
-	  emit_move_insn (change_address(orig_dst, DImode,
-					 plus_constant (XEXP (orig_dst, 0),
-							ofs)),
-			  data_regs[i]);
-	  ofs += 8;
-	  i++;
-	}
-    }
-  if (dst_align >= 4)
-    {
-      /* If the source has remaining DImode regs, write them out in
-	 two pieces.  */
-      while (i < nregs && GET_MODE (data_regs[i]) == DImode)
-	{
-	  tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
-			      NULL_RTX, 1, OPTAB_WIDEN);
-
-	  emit_move_insn (change_address(orig_dst, SImode,
-					 plus_constant (XEXP (orig_dst, 0),
-							ofs)),
-			  gen_lowpart (SImode, data_regs[i]));
-	  emit_move_insn (change_address(orig_dst, SImode,
-					 plus_constant (XEXP (orig_dst, 0),
-							ofs+4)),
-			  gen_lowpart (SImode, tmp));
-	  ofs += 8;
-	  i++;
-	}
-
-      while (i < nregs && GET_MODE (data_regs[i]) == SImode)
-	{
-	  emit_move_insn (change_address(orig_dst, SImode,
-					 plus_constant (XEXP (orig_dst, 0),
-							ofs)),
-			  data_regs[i]);
-	  ofs += 4;
-	  i++;
-	}
-    }
-  if (i < nregs && GET_MODE (data_regs[i]) == DImode)
-    {
-      /* Write out a remaining block of words using unaligned methods.  */
-
-      for (words = 1; i+words < nregs ; ++words)
-	if (GET_MODE (data_regs[i+words]) != DImode)
-	  break;
-
-      if (words == 1)
-	alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
-      else
-        alpha_expand_unaligned_store_words (data_regs+i, orig_dst, words, ofs);
-     
-      i += words;
-      ofs += words * 8;
-    }
-
-  /* Due to the above, this won't be aligned.  */
-  /* ??? If we have more than one of these, consider constructing full
-     words in registers and using alpha_expand_unaligned_store_words.  */
-  while (i < nregs && GET_MODE (data_regs[i]) == SImode)
-    {
-      alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
-      ofs += 4;
-      i++;
-    }
-
-  if (dst_align >= 2)
-    while (i < nregs && GET_MODE (data_regs[i]) == HImode)
-      {
-	emit_move_insn (change_address (orig_dst, HImode,
-					plus_constant (XEXP (orig_dst, 0),
-						       ofs)),
-			data_regs[i]);
-	i++;
-	ofs += 2;
-      }
-  else
-    while (i < nregs && GET_MODE (data_regs[i]) == HImode)
-      {
-	alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
-	i++;
-	ofs += 2;
-      }
-  while (i < nregs && GET_MODE (data_regs[i]) == QImode)
-    {
-      emit_move_insn (change_address (orig_dst, QImode,
-				      plus_constant (XEXP (orig_dst, 0),
-						     ofs)),
-		      data_regs[i]);
-      i++;
-      ofs += 1;
-    }
- dst_done:
-
-  if (i != nregs)
-    abort();
-
-  return 1;
-}
-
-int
-alpha_expand_block_clear (operands)
-     rtx operands[];
-{
-  rtx bytes_rtx	= operands[1];
-  rtx align_rtx = operands[2];
-  HOST_WIDE_INT bytes = INTVAL (bytes_rtx);
-  HOST_WIDE_INT align = INTVAL (align_rtx);
-  rtx orig_dst	= operands[0];
-  rtx tmp;
-  HOST_WIDE_INT i, words, ofs = 0;
-  
-  if (bytes <= 0)
-    return 1;
-  if (bytes > MAX_MOVE_WORDS*8)
-    return 0;
-
-  /* Look for stricter alignment.  */
-
-  tmp = XEXP (orig_dst, 0);
-  if (GET_CODE (tmp) == REG)
-    {
-      if (REGNO_POINTER_ALIGN (REGNO (tmp)) > align)
-	align = REGNO_POINTER_ALIGN (REGNO (tmp));
-    }
-  else if (GET_CODE (tmp) == PLUS
-	   && GET_CODE (XEXP (tmp, 0)) == REG
-	   && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
-    {
-      HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
-      int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
-
-      if (a > align)
-	{
-          if (a >= 8 && c % 8 == 0)
-	    align = 8;
-          else if (a >= 4 && c % 4 == 0)
-	    align = 4;
-          else if (a >= 2 && c % 2 == 0)
-	    align = 2;
-	}
-    }
-
-  /* Handle a block of contiguous words first.  */
-
-  if (align >= 8 && bytes >= 8)
-    {
-      words = bytes / 8;
-
-      for (i = 0; i < words; ++i)
-	{
-	  emit_move_insn (change_address(orig_dst, DImode,
-					 plus_constant (XEXP (orig_dst, 0),
-							ofs + i*8)),
-			  const0_rtx);
-	}
-
-      bytes -= words * 8;
-      ofs += words * 8;
-    }
-  if (align >= 4 && bytes >= 4)
-    {
-      words = bytes / 4;
-
-      for (i = 0; i < words; ++i)
-	{
-	  emit_move_insn (change_address(orig_dst, SImode,
-					 plus_constant (XEXP (orig_dst, 0),
-							ofs + i*4)),
-			  const0_rtx);
-	}
-
-      bytes -= words * 4;
-      ofs += words * 4;
-    }
-  if (bytes >= 16)
-    {
-      words = bytes / 8;
-
-      alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
-
-      bytes -= words * 8;
-      ofs += words * 8;
-    }
-
-  /* Next clean up any trailing pieces.  We know from the contiguous
-     block move that there are no aligned SImode or DImode hunks left.  */
-
-  if (!TARGET_BWX && bytes >= 8)
-    {
-      alpha_expand_unaligned_store (orig_dst, const0_rtx, 8, ofs);
-      bytes -= 8;
-      ofs += 8;
-    }
-  if (!TARGET_BWX && bytes >= 4)
-    {
-      alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
-      bytes -= 4;
-      ofs += 4;
-    }
-  if (bytes >= 2)
-    {
-      if (align >= 2)
-	{
-	  do {
-	    emit_move_insn (change_address (orig_dst, HImode,
-					    plus_constant (XEXP (orig_dst, 0),
-							   ofs)),
-			    const0_rtx);
-	    bytes -= 2;
-	    ofs += 2;
-	  } while (bytes >= 2);
-	}
-      else if (!TARGET_BWX)
-	{
-	  alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
-	  bytes -= 2;
-	  ofs += 2;
-	}
-    }
-  while (bytes > 0)
-    {
-      emit_move_insn (change_address (orig_dst, QImode,
-				      plus_constant (XEXP (orig_dst, 0),
-						     ofs)),
-		      const0_rtx);
-      bytes -= 1;
-      ofs += 1;
-    }
-
-  return 1;
-}
-
-
-/* Adjust the cost of a scheduling dependency.  Return the new cost of
-   a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
-
-int
-alpha_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
-{
-  rtx set, set_src;
-  enum attr_type insn_type, dep_insn_type;
-
-  /* If the dependence is an anti-dependence, there is no cost.  For an
-     output dependence, there is sometimes a cost, but it doesn't seem
-     worth handling those few cases.  */
-
-  if (REG_NOTE_KIND (link) != 0)
-    return 0;
-
-  /* If we can't recognize the insns, we can't really do anything.  */
-  if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
-    return cost;
-
-  insn_type = get_attr_type (insn);
-  dep_insn_type = get_attr_type (dep_insn);
-
-  /* Bring in the user-defined memory latency.  */
-  if (dep_insn_type == TYPE_ILD
-      || dep_insn_type == TYPE_FLD
-      || dep_insn_type == TYPE_LDSYM)
-    cost += alpha_memory_latency-1;
-
-  switch (alpha_cpu)
-    {
-    case PROCESSOR_EV4:
-      /* On EV4, if INSN is a store insn and DEP_INSN is setting the data
-	 being stored, we can sometimes lower the cost.  */
-
-      if ((insn_type == TYPE_IST || insn_type == TYPE_FST)
-	  && (set = single_set (dep_insn)) != 0
-	  && GET_CODE (PATTERN (insn)) == SET
-	  && rtx_equal_p (SET_DEST (set), SET_SRC (PATTERN (insn))))
-	{
-	  switch (dep_insn_type)
-	    {
-	    case TYPE_ILD:
-	    case TYPE_FLD:
-	      /* No savings here.  */
-	      return cost;
-
-	    case TYPE_IMUL:
-	      /* In these cases, we save one cycle.  */
-	      return cost - 1;
-
-	    default:
-	      /* In all other cases, we save two cycles.  */
-	      return MAX (0, cost - 2);
-	    }
-	}
-
-      /* Another case that needs adjustment is an arithmetic or logical
-	 operation.  It's cost is usually one cycle, but we default it to
-	 two in the MD file.  The only case that it is actually two is
-	 for the address in loads, stores, and jumps.  */
-
-      if (dep_insn_type == TYPE_IADD || dep_insn_type == TYPE_ILOG)
-	{
-	  switch (insn_type)
-	    {
-	    case TYPE_ILD:
-	    case TYPE_IST:
-	    case TYPE_FLD:
-	    case TYPE_FST:
-	    case TYPE_JSR:
-	      return cost;
-	    default:
-	      return 1;
-	    }
-	}
-
-      /* The final case is when a compare feeds into an integer branch;
-	 the cost is only one cycle in that case.  */
-
-      if (dep_insn_type == TYPE_ICMP && insn_type == TYPE_IBR)
-	return 1;
-      break;
-
-    case PROCESSOR_EV5:
-      /* And the lord DEC saith:  "A special bypass provides an effective
-	 latency of 0 cycles for an ICMP or ILOG insn producing the test
-	 operand of an IBR or ICMOV insn." */
-
-      if ((dep_insn_type == TYPE_ICMP || dep_insn_type == TYPE_ILOG)
-	  && (set = single_set (dep_insn)) != 0)
-	{
-	  /* A branch only has one input.  This must be it.  */
-	  if (insn_type == TYPE_IBR)
-	    return 0;
-	  /* A conditional move has three, make sure it is the test.  */
-	  if (insn_type == TYPE_ICMOV
-	      && GET_CODE (set_src = PATTERN (insn)) == SET
-	      && GET_CODE (set_src = SET_SRC (set_src)) == IF_THEN_ELSE
-	      && rtx_equal_p (SET_DEST (set), XEXP (set_src, 0)))
-	    return 0;
-	}
-
-      /* "The multiplier is unable to receive data from IEU bypass paths.
-	 The instruction issues at the expected time, but its latency is
-	 increased by the time it takes for the input data to become
-	 available to the multiplier" -- which happens in pipeline stage
-	 six, when results are comitted to the register file.  */
-
-      if (insn_type == TYPE_IMUL)
-	{
-	  switch (dep_insn_type)
-	    {
-	    /* These insns produce their results in pipeline stage five.  */
-	    case TYPE_ILD:
-	    case TYPE_ICMOV:
-	    case TYPE_IMUL:
-	    case TYPE_MVI:
-	      return cost + 1;
-
-	    /* Other integer insns produce results in pipeline stage four.  */
-	    default:
-	      return cost + 2;
-	    }
-	}
-      break;
-
-    case PROCESSOR_EV6:
-      /* There is additional latency to move the result of (most) FP 
-         operations anywhere but the FP register file.  */
-
-      if ((insn_type == TYPE_FST || insn_type == TYPE_FTOI)
-	  && (dep_insn_type == TYPE_FADD ||
-	      dep_insn_type == TYPE_FMUL ||
-	      dep_insn_type == TYPE_FCMOV))
-        return cost + 2;
-
-      break;
-    }
-
-  /* Otherwise, return the default cost. */
-  return cost;
-}
-
-/* Functions to save and restore alpha_return_addr_rtx.  */
-
-struct machine_function
-{
-  rtx ra_rtx;
-};
-
-static void
-alpha_save_machine_status (p)
-     struct function *p;
-{
-  struct machine_function *machine =
-    (struct machine_function *) xmalloc (sizeof (struct machine_function));
-
-  p->machine = machine;
-  machine->ra_rtx = alpha_return_addr_rtx;
-}
-
-static void
-alpha_restore_machine_status (p)
-     struct function *p;
-{
-  struct machine_function *machine = p->machine;
-
-  alpha_return_addr_rtx = machine->ra_rtx;
-
-  free (machine);
-  p->machine = (struct machine_function *)0;
-}
-
-/* Do anything needed before RTL is emitted for each function.  */
-
-void
-alpha_init_expanders ()
-{
-  alpha_return_addr_rtx = NULL_RTX;
-  alpha_eh_epilogue_sp_ofs = NULL_RTX;
-
-  /* Arrange to save and restore machine status around nested functions.  */
-  save_machine_status = alpha_save_machine_status;
-  restore_machine_status = alpha_restore_machine_status;
-}
-
-/* Start the ball rolling with RETURN_ADDR_RTX.  */
-
-rtx
-alpha_return_addr (count, frame)
-     int count;
-     rtx frame ATTRIBUTE_UNUSED;
-{
-  rtx init;
-
-  if (count != 0)
-    return const0_rtx;
-
-  if (alpha_return_addr_rtx)
-    return alpha_return_addr_rtx;
-
-  /* No rtx yet.  Invent one, and initialize it from $26 in the prologue.  */
-  alpha_return_addr_rtx = gen_reg_rtx (Pmode);
-  init = gen_rtx_SET (VOIDmode, alpha_return_addr_rtx,
-		      gen_rtx_REG (Pmode, REG_RA));
-
-  /* Emit the insn to the prologue with the other argument copies.  */
-  push_topmost_sequence ();
-  emit_insn_after (init, get_insns ());
-  pop_topmost_sequence ();
-
-  return alpha_return_addr_rtx;
-}
-
-static int
-alpha_ra_ever_killed ()
-{
-  rtx top;
-
-#ifdef ASM_OUTPUT_MI_THUNK
-  if (current_function_is_thunk)
-    return 0;
-#endif
-  if (!alpha_return_addr_rtx)
-    return regs_ever_live[REG_RA];
-
-  push_topmost_sequence ();
-  top = get_insns ();
-  pop_topmost_sequence ();
-
-  return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
-}
-
-
-/* Print an operand.  Recognize special options, documented below.  */
-
-void
-print_operand (file, x, code)
-    FILE *file;
-    rtx x;
-    char code;
-{
-  int i;
-
-  switch (code)
-    {
-    case '&':
-      /* Generates fp-rounding mode suffix: nothing for normal, 'c' for
-	 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
-	 mode.  alpha_fprm controls which suffix is generated.  */
-      switch (alpha_fprm)
-	{
-	case ALPHA_FPRM_NORM:
-	  break;
-	case ALPHA_FPRM_MINF: 
-	  fputc ('m', file);
-	  break;
-	case ALPHA_FPRM_CHOP:
-	  fputc ('c', file);
-	  break;
-	case ALPHA_FPRM_DYN:
-	  fputc ('d', file);
-	  break;
-	}
-      break;
-
-    case '\'':
-      /* Generates trap-mode suffix for instructions that accept the su
-	 suffix only (cmpt et al).  */
-      if (alpha_tp == ALPHA_TP_INSN)
-	fputs ("su", file);
-      break;
-
-    case '`':
-      /* Generates trap-mode suffix for instructions that accept the
-	 v and sv suffix.  The only instruction that needs this is cvtql.  */
-      switch (alpha_fptm)
-	{
-	case ALPHA_FPTM_N:
-	  break;
-	case ALPHA_FPTM_U:
-	  fputs ("v", file);
-	  break;
-	case ALPHA_FPTM_SU:
-	case ALPHA_FPTM_SUI:
-	  fputs ("sv", file);
-	  break;
-	}
-      break;
-
-    case '(':
-      /* Generates trap-mode suffix for instructions that accept the
-	 v, sv, and svi suffix.  The only instruction that needs this
-	 is cvttq.  */
-      switch (alpha_fptm)
-	{
-	case ALPHA_FPTM_N:
-	  break;
-	case ALPHA_FPTM_U:
-	  fputs ("v", file);
-	  break;
-	case ALPHA_FPTM_SU:
-	  fputs ("sv", file);
-	  break;
-	case ALPHA_FPTM_SUI:
-	  fputs ("svi", file);
-	  break;
-	}
-      break;
-
-    case ')':
-      /* Generates trap-mode suffix for instructions that accept the u, su,
-	 and sui suffix.  This is the bulk of the IEEE floating point
-	 instructions (addt et al).  */
-      switch (alpha_fptm)
-	{
-	case ALPHA_FPTM_N:
-	  break;
-	case ALPHA_FPTM_U:
-	  fputc ('u', file);
-	  break;
-	case ALPHA_FPTM_SU:
-	  fputs ("su", file);
-	  break;
-	case ALPHA_FPTM_SUI:
-	  fputs ("sui", file);
-	  break;
-	}
-      break;
-
-    case '+':
-      /* Generates trap-mode suffix for instructions that accept the sui
-	 suffix (cvtqt and cvtqs).  */
-      switch (alpha_fptm)
-	{
-	case ALPHA_FPTM_N:
-	case ALPHA_FPTM_U:
-	case ALPHA_FPTM_SU:	/* cvtqt/cvtqs can't cause underflow */
-	  break;
-	case ALPHA_FPTM_SUI:
-	  fputs ("sui", file);
-	  break;
-	}
-      break;
-
-    case ',':
-      /* Generates single precision instruction suffix.  */
-      fprintf (file, "%c", (TARGET_FLOAT_VAX ? 'f' : 's'));
-      break;
-
-    case '-':
-      /* Generates double precision instruction suffix.  */
-      fprintf (file, "%c", (TARGET_FLOAT_VAX ? 'g' : 't'));
-      break;
-
-    case 'r':
-      /* If this operand is the constant zero, write it as "$31".  */
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", reg_names[REGNO (x)]);
-      else if (x == CONST0_RTX (GET_MODE (x)))
-	fprintf (file, "$31");
-      else
-	output_operand_lossage ("invalid %%r value");
-
-      break;
-
-    case 'R':
-      /* Similar, but for floating-point.  */
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", reg_names[REGNO (x)]);
-      else if (x == CONST0_RTX (GET_MODE (x)))
-	fprintf (file, "$f31");
-      else
-	output_operand_lossage ("invalid %%R value");
-
-      break;
-
-    case 'N':
-      /* Write the 1's complement of a constant.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%N value");
-
-      fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
-      break;
-
-    case 'P':
-      /* Write 1 << C, for a constant C.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%P value");
-
-      fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
-      break;
-
-    case 'h':
-      /* Write the high-order 16 bits of a constant, sign-extended.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%h value");
-
-      fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
-      break;
-
-    case 'L':
-      /* Write the low-order 16 bits of a constant, sign-extended.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%L value");
-
-      fprintf (file, HOST_WIDE_INT_PRINT_DEC,
-	       (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
-      break;
-
-    case 'm':
-      /* Write mask for ZAP insn.  */
-      if (GET_CODE (x) == CONST_DOUBLE)
-	{
-	  HOST_WIDE_INT mask = 0;
-	  HOST_WIDE_INT value;
-
-	  value = CONST_DOUBLE_LOW (x);
-	  for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
-	       i++, value >>= 8)
-	    if (value & 0xff)
-	      mask |= (1 << i);
-
-	  value = CONST_DOUBLE_HIGH (x);
-	  for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
-	       i++, value >>= 8)
-	    if (value & 0xff)
-	      mask |= (1 << (i + sizeof (int)));
-
-	  fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
-	}
-
-      else if (GET_CODE (x) == CONST_INT)
-	{
-	  HOST_WIDE_INT mask = 0, value = INTVAL (x);
-
-	  for (i = 0; i < 8; i++, value >>= 8)
-	    if (value & 0xff)
-	      mask |= (1 << i);
-
-	  fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
-	}
-      else
-	output_operand_lossage ("invalid %%m value");
-      break;
-
-    case 'M':
-      /* 'b', 'w', 'l', or 'q' as the value of the constant.  */
-      if (GET_CODE (x) != CONST_INT
-	  || (INTVAL (x) != 8 && INTVAL (x) != 16
-	      && INTVAL (x) != 32 && INTVAL (x) != 64))
-	output_operand_lossage ("invalid %%M value");
-
-      fprintf (file, "%s",
-	       (INTVAL (x) == 8 ? "b"
-		: INTVAL (x) == 16 ? "w"
-		: INTVAL (x) == 32 ? "l"
-		: "q"));
-      break;
-
-    case 'U':
-      /* Similar, except do it from the mask.  */
-      if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xff)
-	fprintf (file, "b");
-      else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffff)
-	fprintf (file, "w");
-      else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffffffff)
-	fprintf (file, "l");
-#if HOST_BITS_PER_WIDE_INT == 32
-      else if (GET_CODE (x) == CONST_DOUBLE
-	       && CONST_DOUBLE_HIGH (x) == 0
-	       && CONST_DOUBLE_LOW (x) == -1)
-	fprintf (file, "l");
-      else if (GET_CODE (x) == CONST_DOUBLE
-	       && CONST_DOUBLE_HIGH (x) == -1
-	       && CONST_DOUBLE_LOW (x) == -1)
-	fprintf (file, "q");
-#else
-      else if (GET_CODE (x) == CONST_INT && INTVAL (x) == -1)
-	fprintf (file, "q");
-      else if (GET_CODE (x) == CONST_DOUBLE
-	       && CONST_DOUBLE_HIGH (x) == 0
-	       && CONST_DOUBLE_LOW (x) == -1)
-	fprintf (file, "q");
-#endif
-      else
-	output_operand_lossage ("invalid %%U value");
-      break;
-
-    case 's':
-      /* Write the constant value divided by 8.  */
-      if (GET_CODE (x) != CONST_INT
-	  && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
-	  && (INTVAL (x) & 7) != 8)
-	output_operand_lossage ("invalid %%s value");
-
-      fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8);
-      break;
-
-    case 'S':
-      /* Same, except compute (64 - c) / 8 */
-
-      if (GET_CODE (x) != CONST_INT
-	  && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
-	  && (INTVAL (x) & 7) != 8)
-	output_operand_lossage ("invalid %%s value");
-
-      fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
-      break;
-
-    case 'C': case 'D': case 'c': case 'd':
-      /* Write out comparison name.  */
-      {
-	enum rtx_code c = GET_CODE (x);
-
-        if (GET_RTX_CLASS (c) != '<')
-	  output_operand_lossage ("invalid %%C value");
-
-	if (code == 'D')
-	  c = reverse_condition (c);
-	else if (code == 'c')
-	  c = swap_condition (c);
-	else if (code == 'd')
-	  c = swap_condition (reverse_condition (c));
-
-        if (c == LEU)
-	  fprintf (file, "ule");
-        else if (c == LTU)
-	  fprintf (file, "ult");
-        else
-	  fprintf (file, "%s", GET_RTX_NAME (c));
-      }
-      break;
-
-    case 'E':
-      /* Write the divide or modulus operator.  */
-      switch (GET_CODE (x))
-	{
-	case DIV:
-	  fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
-	  break;
-	case UDIV:
-	  fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
-	  break;
-	case MOD:
-	  fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
-	  break;
-	case UMOD:
-	  fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
-	  break;
-	default:
-	  output_operand_lossage ("invalid %%E value");
-	  break;
-	}
-      break;
-
-    case 'A':
-      /* Write "_u" for unaligned access.  */
-      if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
-	fprintf (file, "_u");
-      break;
-
-    case 0:
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", reg_names[REGNO (x)]);
-      else if (GET_CODE (x) == MEM)
-	output_address (XEXP (x, 0));
-      else
-	output_addr_const (file, x);
-      break;
-
-    default:
-      output_operand_lossage ("invalid %%xn code");
-    }
-}
-
-/* Emit RTL insns to initialize the variable parts of a trampoline at
-   TRAMP. FNADDR is an RTX for the address of the function's pure
-   code.  CXT is an RTX for the static chain value for the function.
-
-   The three offset parameters are for the individual template's
-   layout.  A JMPOFS < 0 indicates that the trampoline does not 
-   contain instructions at all.
-
-   We assume here that a function will be called many more times than
-   its address is taken (e.g., it might be passed to qsort), so we
-   take the trouble to initialize the "hint" field in the JMP insn.
-   Note that the hint field is PC (new) + 4 * bits 13:0.  */
-
-void
-alpha_initialize_trampoline (tramp, fnaddr, cxt, fnofs, cxtofs, jmpofs)
-     rtx tramp, fnaddr, cxt;
-     int fnofs, cxtofs, jmpofs;
-{
-  rtx temp, temp1, addr;
-  /* ??? Something is wrong with VMS codegen in that we get aborts when
-     using ptr_mode.  Hack around it for now.  */
-  enum machine_mode mode = TARGET_OPEN_VMS ? Pmode : ptr_mode;
-
-  /* Store function address and CXT.  */
-  addr = memory_address (mode, plus_constant (tramp, fnofs));
-  emit_move_insn (gen_rtx (MEM, mode, addr), fnaddr);
-  addr = memory_address (mode, plus_constant (tramp, cxtofs));
-  emit_move_insn (gen_rtx (MEM, mode, addr), cxt);
-
-  /* This has been disabled since the hint only has a 32k range, and in
-     no existing OS is the stack within 32k of the text segment. */
-  if (0 && jmpofs >= 0)
-    {
-      /* Compute hint value.  */
-      temp = force_operand (plus_constant (tramp, jmpofs+4), NULL_RTX);
-      temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1,
-			   OPTAB_WIDEN);
-      temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
-		           build_int_2 (2, 0), NULL_RTX, 1);
-      temp = expand_and (gen_lowpart (SImode, temp), GEN_INT (0x3fff), 0);
-
-      /* Merge in the hint.  */
-      addr = memory_address (SImode, plus_constant (tramp, jmpofs));
-      temp1 = force_reg (SImode, gen_rtx (MEM, SImode, addr));
-      temp1 = expand_and (temp1, GEN_INT (0xffffc000), NULL_RTX);
-      temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1,
-			    OPTAB_WIDEN);
-      emit_move_insn (gen_rtx (MEM, SImode, addr), temp1);
-    }
-
-#ifdef TRANSFER_FROM_TRAMPOLINE
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
-		     0, VOIDmode, 1, addr, Pmode);
-#endif
-
-  if (jmpofs >= 0)
-    emit_insn (gen_imb ());
-}
-
-/* Do what is necessary for `va_start'.  The argument is ignored;
-   We look at the current function to determine if stdarg or varargs
-   is used and fill in an initial va_list.  A pointer to this constructor
-   is returned.  */
-
-struct rtx_def *
-alpha_builtin_saveregs (arglist)
-     tree arglist ATTRIBUTE_UNUSED;
-{
-  rtx block, addr, dest, argsize;
-  tree fntype = TREE_TYPE (current_function_decl);
-  int stdarg = (TYPE_ARG_TYPES (fntype) != 0
-		&& (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
-		    != void_type_node));
-
-  /* Compute the current position into the args, taking into account
-     both registers and memory.  Both of these are already included in
-     NUM_ARGS.  */
-
-  argsize = GEN_INT (NUM_ARGS * UNITS_PER_WORD);
-
-  /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base up by 48,
-     storing fp arg registers in the first 48 bytes, and the integer arg
-     registers in the next 48 bytes.  This is only done, however, if any
-     integer registers need to be stored.
-
-     If no integer registers need be stored, then we must subtract 48 in
-     order to account for the integer arg registers which are counted in
-     argsize above, but which are not actually stored on the stack.  */
-
-  if (TARGET_OPEN_VMS)
-    addr = plus_constant (virtual_incoming_args_rtx,
-			  NUM_ARGS <= 5 + stdarg
-			  ? UNITS_PER_WORD : - 6 * UNITS_PER_WORD);
-  else
-    addr = (NUM_ARGS <= 5 + stdarg
-	    ? plus_constant (virtual_incoming_args_rtx,
-			     6 * UNITS_PER_WORD)
-	    : plus_constant (virtual_incoming_args_rtx,
-			     - (6 * UNITS_PER_WORD)));
-
-  /* For VMS, we include the argsize, while on Unix, it's handled as
-     a separate field.  */
-  if (TARGET_OPEN_VMS)
-    addr = plus_constant (addr, INTVAL (argsize));
-
-  addr = force_operand (addr, NULL_RTX);
-
-#ifdef POINTERS_EXTEND_UNSIGNED
-  addr = convert_memory_address (ptr_mode, addr);
-#endif
-
-  if (TARGET_OPEN_VMS)
-    return addr;
-  else
-    {
-      /* Allocate the va_list constructor */
-      block = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
-      RTX_UNCHANGING_P (block) = 1;
-      RTX_UNCHANGING_P (XEXP (block, 0)) = 1;
-
-      /* Store the address of the first integer register in the __base
-	 member.  */
-
-      dest = change_address (block, ptr_mode, XEXP (block, 0));
-      emit_move_insn (dest, addr);
-
-      if (current_function_check_memory_usage)
-	emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
-			   dest, ptr_mode,
-			   GEN_INT (GET_MODE_SIZE (ptr_mode)),
-			   TYPE_MODE (sizetype),
-			   GEN_INT (MEMORY_USE_RW), 
-			   TYPE_MODE (integer_type_node));
-  
-      /* Store the argsize as the __va_offset member.  */
-      dest = change_address (block, TYPE_MODE (integer_type_node),
-			     plus_constant (XEXP (block, 0),
-					    POINTER_SIZE/BITS_PER_UNIT));
-      emit_move_insn (dest, argsize);
-
-      if (current_function_check_memory_usage)
-	emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
-			   dest, ptr_mode,
-			   GEN_INT (GET_MODE_SIZE
-				    (TYPE_MODE (integer_type_node))),
-			   TYPE_MODE (sizetype),
-			   GEN_INT (MEMORY_USE_RW),
-			   TYPE_MODE (integer_type_node));
-
-      /* Return the address of the va_list constructor, but don't put it in a
-	 register.  Doing so would fail when not optimizing and produce worse
-	 code when optimizing.  */
-      return XEXP (block, 0);
-    }
-}
-
-/* This page contains routines that are used to determine what the function
-   prologue and epilogue code will do and write them out.  */
-
-/* Compute the size of the save area in the stack.  */
-
-/* These variables are used for communication between the following functions.
-   They indicate various things about the current function being compiled
-   that are used to tell what kind of prologue, epilogue and procedure
-   descriptior to generate. */
-
-/* Nonzero if we need a stack procedure.  */
-static int vms_is_stack_procedure;
-
-/* Register number (either FP or SP) that is used to unwind the frame.  */
-static int vms_unwind_regno;
-
-/* Register number used to save FP.  We need not have one for RA since
-   we don't modify it for register procedures.  This is only defined
-   for register frame procedures.  */
-static int vms_save_fp_regno;
-
-/* Register number used to reference objects off our PV.  */
-static int vms_base_regno;
-
-/* Compute register masks for saved registers.  */
-
-static void
-alpha_sa_mask (imaskP, fmaskP)
-    unsigned long *imaskP;
-    unsigned long *fmaskP;
-{
-  unsigned long imask = 0;
-  unsigned long fmask = 0;
-  int i;
-
-#ifdef ASM_OUTPUT_MI_THUNK
-  if (!current_function_is_thunk)
-#endif
-    {
-      if (TARGET_OPEN_VMS && vms_is_stack_procedure)
-	imask |= (1L << HARD_FRAME_POINTER_REGNUM);
-
-      /* One for every register we have to save.  */
-      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	if (! fixed_regs[i] && ! call_used_regs[i]
-	    && regs_ever_live[i] && i != REG_RA)
-	  {
-	    if (i < 32)
-	      imask |= (1L << i);
-	    else
-	      fmask |= (1L << (i - 32));
-	  }
-
-      if (imask || fmask || alpha_ra_ever_killed ())
-	imask |= (1L << REG_RA);
-    }
-
-  *imaskP = imask;
-  *fmaskP = fmask;
-}
-
-int
-alpha_sa_size ()
-{
-  int sa_size = 0;
-  int i;
-
-#ifdef ASM_OUTPUT_MI_THUNK
-  if (current_function_is_thunk)
-    sa_size = 0;
-  else
-#endif
-    {
-      /* One for every register we have to save.  */
-      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	if (! fixed_regs[i] && ! call_used_regs[i]
-	    && regs_ever_live[i] && i != REG_RA)
-	  sa_size++;
-    }
-
-  if (TARGET_OPEN_VMS)
-    {
-      /* Start by assuming we can use a register procedure if we don't
-	 make any calls (REG_RA not used) or need to save any
-	 registers and a stack procedure if we do.  */
-      vms_is_stack_procedure = sa_size != 0 || alpha_ra_ever_killed ();
-
-      /* Decide whether to refer to objects off our PV via FP or PV.
-	 If we need FP for something else or if we receive a nonlocal
-	 goto (which expects PV to contain the value), we must use PV.
-	 Otherwise, start by assuming we can use FP.  */
-      vms_base_regno = (frame_pointer_needed
-			|| current_function_has_nonlocal_label
-			|| vms_is_stack_procedure
-			|| current_function_outgoing_args_size
-			? REG_PV : HARD_FRAME_POINTER_REGNUM);
-
-      /* If we want to copy PV into FP, we need to find some register
-	 in which to save FP.  */
-
-      vms_save_fp_regno = -1;
-      if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
-	for (i = 0; i < 32; i++)
-	  if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
-	    vms_save_fp_regno = i;
-
-      if (vms_save_fp_regno == -1)
-	vms_base_regno = REG_PV, vms_is_stack_procedure = 1;
-
-      /* Stack unwinding should be done via FP unless we use it for PV.  */
-      vms_unwind_regno = (vms_base_regno == REG_PV
-			  ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
-
-      /* If this is a stack procedure, allow space for saving FP and RA.  */
-      if (vms_is_stack_procedure)
-	sa_size += 2;
-    }
-  else
-    {
-      /* If some registers were saved but not RA, RA must also be saved,
-	 so leave space for it.  */
-      if (sa_size != 0 || alpha_ra_ever_killed ())
-	sa_size++;
-
-      /* Our size must be even (multiple of 16 bytes).  */
-      if (sa_size & 1)
-	sa_size++;
-    }
-
-  return sa_size * 8;
-}
-
-int
-alpha_pv_save_size ()
-{
-  alpha_sa_size ();
-  return vms_is_stack_procedure ? 8 : 0;
-}
-
-int
-alpha_using_fp ()
-{
-  alpha_sa_size ();
-  return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM;
-}
-
-int
-vms_valid_decl_attribute_p (decl, attributes, identifier, args)
-     tree decl ATTRIBUTE_UNUSED;
-     tree attributes ATTRIBUTE_UNUSED;
-     tree identifier;
-     tree args;
-{
-  if (is_attribute_p ("overlaid", identifier))
-    return (args == NULL_TREE);
-  return 0;
-}
-
-static int
-alpha_does_function_need_gp ()
-{
-  rtx insn;
-
-  /* We never need a GP for Windows/NT or VMS.  */
-  if (TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
-    return 0;
-
-#ifdef TARGET_PROFILING_NEEDS_GP
-  if (profile_flag)
-    return 1;
-#endif
-
-#ifdef ASM_OUTPUT_MI_THUNK
-  if (current_function_is_thunk)
-    return 1;
-#endif
-
-  /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first. 
-     Even if we are a static function, we still need to do this in case
-     our address is taken and passed to something like qsort.  */
-
-  push_topmost_sequence ();
-  insn = get_insns ();
-  pop_topmost_sequence ();
-
-  for (; insn; insn = NEXT_INSN (insn))
-    if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
-	&& GET_CODE (PATTERN (insn)) != USE
-	&& GET_CODE (PATTERN (insn)) != CLOBBER)
-      {
-	enum attr_type type = get_attr_type (insn);
-	if (type == TYPE_LDSYM || type == TYPE_JSR)
-	  return 1;
-      }
-
-  return 0;
-}
-
-/* Write a version stamp.  Don't write anything if we are running as a
-   cross-compiler.  Otherwise, use the versions in /usr/include/stamp.h.  */
-
-#ifdef HAVE_STAMP_H
-#include <stamp.h>
-#endif
-
-void
-alpha_write_verstamp (file)
-     FILE *file;
-{
-#ifdef MS_STAMP
-  fprintf (file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
-#endif
-}
-
-/* Helper function to set RTX_FRAME_RELATED_P on instructions, including
-   sequences.  */
-
-static rtx
-set_frame_related_p ()
-{
-  rtx seq = gen_sequence ();
-  end_sequence ();
-
-  if (GET_CODE (seq) == SEQUENCE)
-    {
-      int i = XVECLEN (seq, 0);
-      while (--i >= 0)
-	RTX_FRAME_RELATED_P (XVECEXP (seq, 0, i)) = 1;
-     return emit_insn (seq);
-    }
-  else
-    {
-      seq = emit_insn (seq);
-      RTX_FRAME_RELATED_P (seq) = 1;
-      return seq;
-    }
-}
-
-#define FRP(exp)  (start_sequence (), exp, set_frame_related_p ())
-
-/* Write function prologue.  */
-
-/* On vms we have two kinds of functions:
-
-   - stack frame (PROC_STACK)
-	these are 'normal' functions with local vars and which are
-	calling other functions
-   - register frame (PROC_REGISTER)
-	keeps all data in registers, needs no stack
-
-   We must pass this to the assembler so it can generate the
-   proper pdsc (procedure descriptor)
-   This is done with the '.pdesc' command.
-
-   On not-vms, we don't really differentiate between the two, as we can
-   simply allocate stack without saving registers.  */
-
-void
-alpha_expand_prologue ()
-{
-  /* Registers to save.  */
-  unsigned long imask = 0;
-  unsigned long fmask = 0;
-  /* Stack space needed for pushing registers clobbered by us.  */
-  HOST_WIDE_INT sa_size;
-  /* Complete stack size needed.  */
-  HOST_WIDE_INT frame_size;
-  /* Offset from base reg to register save area.  */
-  HOST_WIDE_INT reg_offset;
-  rtx sa_reg, mem;
-  int i;
-
-  sa_size = alpha_sa_size ();
-
-  frame_size = get_frame_size ();
-  if (TARGET_OPEN_VMS)
-    frame_size = ALPHA_ROUND (sa_size 
-			      + (vms_is_stack_procedure ? 8 : 0)
-			      + frame_size
-			      + current_function_pretend_args_size);
-  else
-    frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
-		  + sa_size
-		  + ALPHA_ROUND (frame_size
-				 + current_function_pretend_args_size));
-
-  if (TARGET_OPEN_VMS)
-    reg_offset = 8;
-  else
-    reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
-
-  alpha_sa_mask (&imask, &fmask);
-
-  /* Adjust the stack by the frame size.  If the frame size is > 4096
-     bytes, we need to be sure we probe somewhere in the first and last
-     4096 bytes (we can probably get away without the latter test) and
-     every 8192 bytes in between.  If the frame size is > 32768, we
-     do this in a loop.  Otherwise, we generate the explicit probe
-     instructions. 
-
-     Note that we are only allowed to adjust sp once in the prologue.  */
-
-  if (frame_size <= 32768)
-    {
-      if (frame_size > 4096)
-	{
-	  int probed = 4096;
-
-	  do
-	    emit_insn (gen_probe_stack (GEN_INT (-probed)));
-	  while ((probed += 8192) < frame_size);
-
-	  /* We only have to do this probe if we aren't saving registers.  */
-	  if (sa_size == 0 && probed + 4096 < frame_size)
-	    emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
-	}
-
-      if (frame_size != 0)
-	{
-	  FRP (emit_move_insn (stack_pointer_rtx,
-			       plus_constant (stack_pointer_rtx, -frame_size)));
-	}
-    }
-  else
-    {
-      /* Here we generate code to set R22 to SP + 4096 and set R23 to the
-	 number of 8192 byte blocks to probe.  We then probe each block
-	 in the loop and then set SP to the proper location.  If the
-	 amount remaining is > 4096, we have to do one more probe if we
-	 are not saving any registers.  */
-
-      HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
-      HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
-      rtx ptr = gen_rtx_REG (DImode, 22);
-      rtx count = gen_rtx_REG (DImode, 23);
-
-      emit_move_insn (count, GEN_INT (blocks));
-      emit_move_insn (ptr, plus_constant (stack_pointer_rtx, 4096));
-
-      /* Because of the difficulty in emitting a new basic block this
-	 late in the compilation, generate the loop as a single insn.  */
-      emit_insn (gen_prologue_stack_probe_loop (count, ptr));
-
-      if (leftover > 4096 && sa_size == 0)
-	{
-	  rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover));
-	  MEM_VOLATILE_P (last) = 1;
-	  emit_move_insn (last, const0_rtx);
-	}
-
-      ptr = emit_move_insn (stack_pointer_rtx, plus_constant (ptr, -leftover));
-
-      /* This alternative is special, because the DWARF code cannot possibly
-	 intuit through the loop above.  So we invent this note it looks at
-	 instead.  */
-      RTX_FRAME_RELATED_P (ptr) = 1;
-      REG_NOTES (ptr)
-	= gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
-			     gen_rtx_SET (VOIDmode, stack_pointer_rtx,
-			       gen_rtx_PLUS (Pmode, stack_pointer_rtx,
-					     GEN_INT (-frame_size))),
-			     REG_NOTES (ptr));
-    }
-
-  /* Cope with very large offsets to the register save area.  */
-  sa_reg = stack_pointer_rtx;
-  if (reg_offset + sa_size > 0x8000)
-    {
-      int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
-      HOST_WIDE_INT bias;
-
-      if (low + sa_size <= 0x8000)
-	bias = reg_offset - low, reg_offset = low;
-      else 
-	bias = reg_offset, reg_offset = 0;
-
-      sa_reg = gen_rtx_REG (DImode, 24);
-      FRP (emit_move_insn (sa_reg, plus_constant (stack_pointer_rtx, bias)));
-    }
-    
-  /* Save regs in stack order.  Beginning with VMS PV.  */
-  if (TARGET_OPEN_VMS && vms_is_stack_procedure)
-    {
-      mem = gen_rtx_MEM (DImode, stack_pointer_rtx);
-      MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
-      FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_PV)));
-    }
-
-  /* Save register RA next.  */
-  if (imask & (1L << REG_RA))
-    {
-      mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
-      MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
-      FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
-      imask &= ~(1L << REG_RA);
-      reg_offset += 8;
-    }
-
-  /* Now save any other registers required to be saved.  */
-  for (i = 0; i < 32; i++)
-    if (imask & (1L << i))
-      {
-	mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
-	MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
-	FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
-	reg_offset += 8;
-      }
-
-  for (i = 0; i < 32; i++)
-    if (fmask & (1L << i))
-      {
-	mem = gen_rtx_MEM (DFmode, plus_constant (sa_reg, reg_offset));
-	MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
-	FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
-	reg_offset += 8;
-      }
-
-  if (TARGET_OPEN_VMS)
-    {
-      if (!vms_is_stack_procedure)
-	{
-	  /* Register frame procedures fave the fp.  */
-	  FRP (emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno),
-			       hard_frame_pointer_rtx));
-	}
-
-      if (vms_base_regno != REG_PV)
-	FRP (emit_move_insn (gen_rtx_REG (DImode, vms_base_regno),
-			     gen_rtx_REG (DImode, REG_PV)));
-
-      if (vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
-	{
-	  FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
-	}
-
-      /* If we have to allocate space for outgoing args, do it now.  */
-      if (current_function_outgoing_args_size != 0)
-	{
-	  FRP (emit_move_insn (stack_pointer_rtx, 
-	        plus_constant (hard_frame_pointer_rtx,
-	         - ALPHA_ROUND (current_function_outgoing_args_size))));
-	}
-    }
-  else
-    {
-      /* If we need a frame pointer, set it from the stack pointer.  */
-      if (frame_pointer_needed)
-	{
-	  if (TARGET_CAN_FAULT_IN_PROLOGUE)
-	    FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
-	  else
-	    {
-	      /* This must always be the last instruction in the
-		 prologue, thus we emit a special move + clobber.  */
-	      FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx,
-				           stack_pointer_rtx, sa_reg)));
-	    }
-	}
-    }
-
-  /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
-     the prologue, for exception handling reasons, we cannot do this for
-     any insn that might fault.  We could prevent this for mems with a
-     (clobber:BLK (scratch)), but this doesn't work for fp insns.  So we
-     have to prevent all such scheduling with a blockage.
-
-     Linux, on the other hand, never bothered to implement OSF/1's 
-     exception handling, and so doesn't care about such things.  Anyone
-     planning to use dwarf2 frame-unwind info can also omit the blockage.  */
-
-  if (! TARGET_CAN_FAULT_IN_PROLOGUE)
-    emit_insn (gen_blockage ());
-}
-
-/* Output the textual info surrounding the prologue.  */
-
-void
-alpha_start_function (file, fnname, decl)
-     FILE *file;
-     char *fnname;
-     tree decl ATTRIBUTE_UNUSED;
-{
-  unsigned long imask = 0;
-  unsigned long fmask = 0;
-  /* Stack space needed for pushing registers clobbered by us.  */
-  HOST_WIDE_INT sa_size;
-  /* Complete stack size needed.  */
-  HOST_WIDE_INT frame_size;
-  /* Offset from base reg to register save area.  */
-  HOST_WIDE_INT reg_offset;
-  char *entry_label = (char *) alloca (strlen (fnname) + 6);
-  int i;
-
-  sa_size = alpha_sa_size ();
-
-  frame_size = get_frame_size ();
-  if (TARGET_OPEN_VMS)
-    frame_size = ALPHA_ROUND (sa_size 
-			      + (vms_is_stack_procedure ? 8 : 0)
-			      + frame_size
-			      + current_function_pretend_args_size);
-  else
-    frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
-		  + sa_size
-		  + ALPHA_ROUND (frame_size
-				 + current_function_pretend_args_size));
-
-  if (TARGET_OPEN_VMS)
-    reg_offset = 8;
-  else
-    reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
-
-  alpha_sa_mask (&imask, &fmask);
-
-  /* Ecoff can handle multiple .file directives, so put out file and lineno.
-     We have to do that before the .ent directive as we cannot switch
-     files within procedures with native ecoff because line numbers are
-     linked to procedure descriptors.
-     Outputting the lineno helps debugging of one line functions as they
-     would otherwise get no line number at all. Please note that we would
-     like to put out last_linenum from final.c, but it is not accessible.  */
-
-  if (write_symbols == SDB_DEBUG)
-    {
-      ASM_OUTPUT_SOURCE_FILENAME (file,
-				  DECL_SOURCE_FILE (current_function_decl));
-      if (debug_info_level != DINFO_LEVEL_TERSE)
-        ASM_OUTPUT_SOURCE_LINE (file,
-				DECL_SOURCE_LINE (current_function_decl));
-    }
-
-  /* Issue function start and label.  */
-  if (TARGET_OPEN_VMS || !flag_inhibit_size_directive)
-    {
-      fputs ("\t.ent ", file);
-      assemble_name (file, fnname);
-      putc ('\n', file);
-    }
-
-  strcpy (entry_label, fnname);
-  if (TARGET_OPEN_VMS)
-    strcat (entry_label, "..en");
-  ASM_OUTPUT_LABEL (file, entry_label);
-  inside_function = TRUE;
-
-  if (TARGET_OPEN_VMS)
-    fprintf (file, "\t.base $%d\n", vms_base_regno);
-
-  if (!TARGET_OPEN_VMS && TARGET_IEEE_CONFORMANT
-      && !flag_inhibit_size_directive)
-    {
-      /* Set flags in procedure descriptor to request IEEE-conformant
-	 math-library routines.  The value we set it to is PDSC_EXC_IEEE
-	 (/usr/include/pdsc.h). */
-      fputs ("\t.eflag 48\n", file);
-    }
-
-  /* Set up offsets to alpha virtual arg/local debugging pointer.  */
-  alpha_auto_offset = -frame_size + current_function_pretend_args_size;
-  alpha_arg_offset = -frame_size + 48;
-
-  /* Describe our frame.  If the frame size is larger than an integer,
-     print it as zero to avoid an assembler error.  We won't be
-     properly describing such a frame, but that's the best we can do.  */
-  if (TARGET_OPEN_VMS)
-    {
-      fprintf (file, "\t.frame $%d,", vms_unwind_regno);
-      fprintf (file, HOST_WIDE_INT_PRINT_DEC,
-	       frame_size >= (1l << 31) ? 0 : frame_size);
-      fputs (",$26,", file);
-      fprintf (file, HOST_WIDE_INT_PRINT_DEC, reg_offset);
-      fputs ("\n", file);
-    }
-  else if (!flag_inhibit_size_directive)
-    {
-      fprintf (file, "\t.frame $%d,",
-	       (frame_pointer_needed
-		? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM));
-      fprintf (file, HOST_WIDE_INT_PRINT_DEC,
-	       frame_size >= (1l << 31) ? 0 : frame_size);
-      fprintf (file, ",$26,%d\n", current_function_pretend_args_size);
-    }
-
-  /* Describe which registers were spilled.  */
-  if (TARGET_OPEN_VMS)
-    {
-      if (imask)
-        /* ??? Does VMS care if mask contains ra?  The old code did'nt
-           set it, so I don't here.  */
-	fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1L << REG_RA));
-      if (fmask)
-	fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
-      if (!vms_is_stack_procedure)
-	fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno);
-    }
-  else if (!flag_inhibit_size_directive)
-    {
-      if (imask)
-	{
-	  fprintf (file, "\t.mask 0x%lx,", imask);
-	  fprintf (file, HOST_WIDE_INT_PRINT_DEC,
-		   frame_size >= (1l << 31) ? 0 : reg_offset - frame_size);
-	  putc ('\n', file);
-
-	  for (i = 0; i < 32; ++i)
-	    if (imask & (1L << i))
-	      reg_offset += 8;
-	}
-
-      if (fmask)
-	{
-	  fprintf (file, "\t.fmask 0x%lx,", fmask);
-	  fprintf (file, HOST_WIDE_INT_PRINT_DEC,
-		   frame_size >= (1l << 31) ? 0 : reg_offset - frame_size);
-	  putc ('\n', file);
-	}
-    }
-
-  /* Emit GP related things.  It is rather unfortunate about the alignment
-     issues surrounding a CODE_LABEL that forces us to do the label in 
-     plain text.  */
-  if (!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT)
-    {
-      alpha_function_needs_gp = alpha_does_function_need_gp ();
-      if (alpha_function_needs_gp)
-	fputs ("\tldgp $29,0($27)\n", file);
-
-      putc ('$', file);
-      assemble_name (file, fnname);
-      fputs ("..ng:\n", file);
-    }
-
-#ifdef OPEN_VMS
-  /* Ifdef'ed cause readonly_section and link_section are only
-     available then.  */
-  readonly_section ();
-  fprintf (file, "\t.align 3\n");
-  assemble_name (file, fnname); fputs ("..na:\n", file);
-  fputs ("\t.ascii \"", file);
-  assemble_name (file, fnname);
-  fputs ("\\0\"\n", file);
-      
-  link_section ();
-  fprintf (file, "\t.align 3\n");
-  fputs ("\t.name ", file);
-  assemble_name (file, fnname);
-  fputs ("..na\n", file);
-  ASM_OUTPUT_LABEL (file, fnname);
-  fprintf (file, "\t.pdesc ");
-  assemble_name (file, fnname);
-  fprintf (file, "..en,%s\n", vms_is_stack_procedure ? "stack" : "reg");
-  alpha_need_linkage (fnname, 1);
-  text_section ();
-#endif
-}
-
-/* Emit the .prologue note at the scheduled end of the prologue.  */
-
-void
-output_end_prologue (file)
-     FILE *file;
-{
-  if (TARGET_OPEN_VMS)
-    fputs ("\t.prologue\n", file);
-  else if (TARGET_WINDOWS_NT)
-    fputs ("\t.prologue 0\n", file);
-  else if (!flag_inhibit_size_directive)
-    fprintf (file, "\t.prologue %d\n", alpha_function_needs_gp);
-}
-
-/* Write function epilogue.  */
-
-/* ??? At some point we will want to support full unwind, and so will 
-   need to mark the epilogue as well.  At the moment, we just confuse
-   dwarf2out.  */
-#undef FRP
-#define FRP(exp) exp
-
-void
-alpha_expand_epilogue ()
-{
-  /* Registers to save.  */
-  unsigned long imask = 0;
-  unsigned long fmask = 0;
-  /* Stack space needed for pushing registers clobbered by us.  */
-  HOST_WIDE_INT sa_size;
-  /* Complete stack size needed.  */
-  HOST_WIDE_INT frame_size;
-  /* Offset from base reg to register save area.  */
-  HOST_WIDE_INT reg_offset;
-  int fp_is_frame_pointer, fp_offset;
-  rtx sa_reg, sa_reg_exp = NULL;
-  rtx sp_adj1, sp_adj2, mem;
-  int i;
-
-  sa_size = alpha_sa_size ();
-
-  frame_size = get_frame_size ();
-  if (TARGET_OPEN_VMS)
-    frame_size = ALPHA_ROUND (sa_size 
-			      + (vms_is_stack_procedure ? 8 : 0)
-			      + frame_size
-			      + current_function_pretend_args_size);
-  else
-    frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
-		  + sa_size
-		  + ALPHA_ROUND (frame_size
-				 + current_function_pretend_args_size));
-
-  if (TARGET_OPEN_VMS)
-    reg_offset = 8;
-  else
-    reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
-
-  alpha_sa_mask (&imask, &fmask);
-
-  fp_is_frame_pointer = ((TARGET_OPEN_VMS && vms_is_stack_procedure)
-			 || (!TARGET_OPEN_VMS && frame_pointer_needed));
-
-  if (sa_size)
-    {
-      /* If we have a frame pointer, restore SP from it.  */
-      if ((TARGET_OPEN_VMS
-	   && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
-	  || (!TARGET_OPEN_VMS && frame_pointer_needed))
-	{
-	  FRP (emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx));
-	}
-
-      /* Cope with very large offsets to the register save area.  */
-      sa_reg = stack_pointer_rtx;
-      if (reg_offset + sa_size > 0x8000)
-	{
-	  int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
-	  HOST_WIDE_INT bias;
-
-	  if (low + sa_size <= 0x8000)
-	    bias = reg_offset - low, reg_offset = low;
-	  else 
-	    bias = reg_offset, reg_offset = 0;
-
-	  sa_reg = gen_rtx_REG (DImode, 22);
-	  sa_reg_exp = plus_constant (stack_pointer_rtx, bias);
-
-	  FRP (emit_move_insn (sa_reg, sa_reg_exp));
-	}
-	  
-      /* Restore registers in order, excepting a true frame pointer. */
-
-      if (! alpha_eh_epilogue_sp_ofs)
-	{
-	  mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
-	  MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
-          FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
-	}
-      reg_offset += 8;
-      imask &= ~(1L << REG_RA);
-
-      for (i = 0; i < 32; ++i)
-	if (imask & (1L << i))
-	  {
-	    if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
-	      fp_offset = reg_offset;
-	    else
-	      {
-		mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
-		MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
-		FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
-	      }
-	    reg_offset += 8;
-	  }
-
-      for (i = 0; i < 32; ++i)
-	if (fmask & (1L << i))
-	  {
-	    mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
-	    MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
-	    FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
-	    reg_offset += 8;
-	  }
-    }
-
-  if (frame_size || alpha_eh_epilogue_sp_ofs)
-    {
-      sp_adj1 = stack_pointer_rtx;
-
-      if (alpha_eh_epilogue_sp_ofs)
-	{
-	  sp_adj1 = gen_rtx_REG (DImode, 23);
-	  emit_move_insn (sp_adj1,
-			  gen_rtx_PLUS (Pmode, stack_pointer_rtx,
-					alpha_eh_epilogue_sp_ofs));
-	}
-
-      /* If the stack size is large, begin computation into a temporary
-	 register so as not to interfere with a potential fp restore,
-	 which must be consecutive with an SP restore.  */
-      if (frame_size < 32768)
-	sp_adj2 = GEN_INT (frame_size);
-      else if (frame_size < 0x40007fffL)
-	{
-	  int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
-
-	  sp_adj2 = plus_constant (sp_adj1, frame_size - low);
-	  if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2))
-	    sp_adj1 = sa_reg;
-	  else
-	    {
-	      sp_adj1 = gen_rtx_REG (DImode, 23);
-	      FRP (emit_move_insn (sp_adj1, sp_adj2));
-	    }
-	  sp_adj2 = GEN_INT (low);
-	}
-      else
-	{
-	  rtx tmp = gen_rtx_REG (DImode, 23);
-	  FRP (sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3));
-	  if (!sp_adj2)
-	    {
-	      /* We can't drop new things to memory this late, afaik,
-		 so build it up by pieces.  */
-	      FRP (sp_adj2 = alpha_emit_set_long_const (tmp, frame_size,
-							-(frame_size < 0)));
-	      if (!sp_adj2)
-		abort ();
-	    }
-	}
-
-      /* From now on, things must be in order.  So emit blockages.  */
-
-      /* Restore the frame pointer.  */
-      if (fp_is_frame_pointer)
-	{
-	  emit_insn (gen_blockage ());
-	  mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, fp_offset));
-	  MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
-	  FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
-	}
-      else if (TARGET_OPEN_VMS)
-	{
-	  emit_insn (gen_blockage ());
-	  FRP (emit_move_insn (hard_frame_pointer_rtx,
-			       gen_rtx_REG (DImode, vms_save_fp_regno)));
-	}
-
-      /* Restore the stack pointer.  */
-      emit_insn (gen_blockage ());
-      FRP (emit_move_insn (stack_pointer_rtx,
-		           gen_rtx_PLUS (DImode, sp_adj1, sp_adj2)));
-    }
-  else 
-    {
-      if (TARGET_OPEN_VMS && !vms_is_stack_procedure)
-        {
-          emit_insn (gen_blockage ());
-          FRP (emit_move_insn (hard_frame_pointer_rtx,
-			       gen_rtx_REG (DImode, vms_save_fp_regno)));
-        }
-    }
-
-  /* Return.  */
-  emit_jump_insn (gen_return_internal ());
-}
-
-/* Output the rest of the textual info surrounding the epilogue.  */
-
-void
-alpha_end_function (file, fnname, decl)
-     FILE *file;
-     char *fnname;
-     tree decl ATTRIBUTE_UNUSED;
-{
-  /* End the function.  */
-  if (!flag_inhibit_size_directive)
-    {
-      fputs ("\t.end ", file);
-      assemble_name (file, fnname);
-      putc ('\n', file);
-    }
-  inside_function = FALSE;
-
-  /* Show that we know this function if it is called again. 
-
-     Don't do this for global functions in object files destined for a
-     shared library because the function may be overridden by the application
-     or other libraries.
-     ??? Is this just ELF?  */
-
-  if (!flag_pic || !TREE_PUBLIC (current_function_decl))
-    SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl), 0)) = 1;
-}
-
-/* Debugging support.  */
-
-#include "gstab.h"
-
-/* Count the number of sdb related labels are generated (to find block
-   start and end boundaries).  */
-
-int sdb_label_count = 0;
-
-/* Next label # for each statement.  */
-
-static int sym_lineno = 0;
-
-/* Count the number of .file directives, so that .loc is up to date.  */
-
-static int num_source_filenames = 0;
-
-/* Name of the file containing the current function.  */
-
-static char *current_function_file = "";
-
-/* Offsets to alpha virtual arg/local debugging pointers.  */
-
-long alpha_arg_offset;
-long alpha_auto_offset;
-
-/* Emit a new filename to a stream.  */
-
-void
-alpha_output_filename (stream, name)
-     FILE *stream;
-     char *name;
-{
-  static int first_time = TRUE;
-  char ltext_label_name[100];
-
-  if (first_time)
-    {
-      first_time = FALSE;
-      ++num_source_filenames;
-      current_function_file = name;
-      fprintf (stream, "\t.file\t%d ", num_source_filenames);
-      output_quoted_string (stream, name);
-      fprintf (stream, "\n");
-      if (!TARGET_GAS && write_symbols == DBX_DEBUG)
-	fprintf (stream, "\t#@stabs\n");
-    }
-
-  else if (write_symbols == DBX_DEBUG)
-    {
-      ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
-      fprintf (stream, "%s ", ASM_STABS_OP);
-      output_quoted_string (stream, name);
-      fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
-    }
-
-  else if (name != current_function_file
-	   && strcmp (name, current_function_file) != 0)
-    {
-      if (inside_function && ! TARGET_GAS)
-	fprintf (stream, "\t#.file\t%d ", num_source_filenames);
-      else
-	{
-	  ++num_source_filenames;
-	  current_function_file = name;
-	  fprintf (stream, "\t.file\t%d ", num_source_filenames);
-	}
-
-      output_quoted_string (stream, name);
-      fprintf (stream, "\n");
-    }
-}
-
-/* Emit a linenumber to a stream.  */
-
-void
-alpha_output_lineno (stream, line)
-     FILE *stream;
-     int line;
-{
-  if (write_symbols == DBX_DEBUG)
-    {
-      /* mips-tfile doesn't understand .stabd directives.  */
-      ++sym_lineno;
-      fprintf (stream, "$LM%d:\n\t%s %d,0,%d,$LM%d\n",
-	       sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno);
-    }
-  else
-    fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
-}
-
-/* Structure to show the current status of registers and memory.  */
-
-struct shadow_summary
-{
-  struct {
-    unsigned long i     : 31;	/* Mask of int regs */
-    unsigned long fp    : 31;	/* Mask of fp regs */
-    unsigned long mem   :  1;	/* mem == imem | fpmem */
-  } used, defd;
-};
-
-static void summarize_insn PROTO((rtx, struct shadow_summary *, int));
-static void alpha_handle_trap_shadows PROTO((rtx));
-
-/* Summary the effects of expression X on the machine.  Update SUM, a pointer
-   to the summary structure.  SET is nonzero if the insn is setting the
-   object, otherwise zero.  */
-
-static void
-summarize_insn (x, sum, set)
-     rtx x;
-     struct shadow_summary *sum;
-     int set;
-{
-  char *format_ptr;
-  int i, j;
-
-  if (x == 0)
-    return;
-
-  switch (GET_CODE (x))
-    {
-      /* ??? Note that this case would be incorrect if the Alpha had a
-	 ZERO_EXTRACT in SET_DEST.  */
-    case SET:
-      summarize_insn (SET_SRC (x), sum, 0);
-      summarize_insn (SET_DEST (x), sum, 1);
-      break;
-
-    case CLOBBER:
-      summarize_insn (XEXP (x, 0), sum, 1);
-      break;
-
-    case USE:
-      summarize_insn (XEXP (x, 0), sum, 0);
-      break;
-
-    case ASM_OPERANDS:
-      for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
-	summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
-      break;
-
-    case PARALLEL:
-      for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
-	summarize_insn (XVECEXP (x, 0, i), sum, 0);
-      break;
-
-    case SUBREG:
-      summarize_insn (SUBREG_REG (x), sum, 0);
-      break;
-
-    case REG:
-      {
-	int regno = REGNO (x);
-	unsigned long mask = 1UL << (regno % 32);
-
-	if (regno == 31 || regno == 63)
-	  break;
-
-	if (set)
-	  {
-	    if (regno < 32)
-	      sum->defd.i |= mask;
-	    else
-	      sum->defd.fp |= mask;
-	  }
-	else
-	  {
-	    if (regno < 32)
-	      sum->used.i  |= mask;
-	    else
-	      sum->used.fp |= mask;
-	  }
-	}
-      break;
-
-    case MEM:
-      if (set)
-	sum->defd.mem = 1;
-      else
-	sum->used.mem = 1;
-
-      /* Find the regs used in memory address computation: */
-      summarize_insn (XEXP (x, 0), sum, 0);
-      break;
-
-    case CONST_INT:   case CONST_DOUBLE:
-    case SYMBOL_REF:  case LABEL_REF:     case CONST:
-      break;
-
-      /* Handle common unary and binary ops for efficiency.  */
-    case COMPARE:  case PLUS:    case MINUS:   case MULT:      case DIV:
-    case MOD:      case UDIV:    case UMOD:    case AND:       case IOR:
-    case XOR:      case ASHIFT:  case ROTATE:  case ASHIFTRT:  case LSHIFTRT:
-    case ROTATERT: case SMIN:    case SMAX:    case UMIN:      case UMAX:
-    case NE:       case EQ:      case GE:      case GT:        case LE:
-    case LT:       case GEU:     case GTU:     case LEU:       case LTU:
-      summarize_insn (XEXP (x, 0), sum, 0);
-      summarize_insn (XEXP (x, 1), sum, 0);
-      break;
-
-    case NEG:  case NOT:  case SIGN_EXTEND:  case ZERO_EXTEND:
-    case TRUNCATE:  case FLOAT_EXTEND:  case FLOAT_TRUNCATE:  case FLOAT:
-    case FIX:  case UNSIGNED_FLOAT:  case UNSIGNED_FIX:  case ABS:
-    case SQRT:  case FFS: 
-      summarize_insn (XEXP (x, 0), sum, 0);
-      break;
-
-    default:
-      format_ptr = GET_RTX_FORMAT (GET_CODE (x));
-      for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
-	switch (format_ptr[i])
-	  {
-	  case 'e':
-	    summarize_insn (XEXP (x, i), sum, 0);
-	    break;
-
-	  case 'E':
-	    for (j = XVECLEN (x, i) - 1; j >= 0; j--)
-	      summarize_insn (XVECEXP (x, i, j), sum, 0);
-	    break;
-
-	  case 'i':
-	    break;
-
-	  default:
-	    abort ();
-	  }
-    }
-}
-
-/* Ensure a sufficient number of `trapb' insns are in the code when
-   the user requests code with a trap precision of functions or
-   instructions.
-
-   In naive mode, when the user requests a trap-precision of
-   "instruction", a trapb is needed after every instruction that may
-   generate a trap.  This ensures that the code is resumption safe but
-   it is also slow.
-
-   When optimizations are turned on, we delay issuing a trapb as long
-   as possible.  In this context, a trap shadow is the sequence of
-   instructions that starts with a (potentially) trap generating
-   instruction and extends to the next trapb or call_pal instruction
-   (but GCC never generates call_pal by itself).  We can delay (and
-   therefore sometimes omit) a trapb subject to the following
-   conditions:
-
-   (a) On entry to the trap shadow, if any Alpha register or memory
-   location contains a value that is used as an operand value by some
-   instruction in the trap shadow (live on entry), then no instruction
-   in the trap shadow may modify the register or memory location.
-
-   (b) Within the trap shadow, the computation of the base register
-   for a memory load or store instruction may not involve using the
-   result of an instruction that might generate an UNPREDICTABLE
-   result.
-
-   (c) Within the trap shadow, no register may be used more than once
-   as a destination register.  (This is to make life easier for the
-   trap-handler.)
-
-   (d) The trap shadow may not include any branch instructions.  */
-
-static void
-alpha_handle_trap_shadows (insns)
-     rtx insns;
-{
-  struct shadow_summary shadow;
-  int trap_pending, exception_nesting;
-  rtx i, n;
-
-  trap_pending = 0;
-  exception_nesting = 0;
-  shadow.used.i = 0;
-  shadow.used.fp = 0;
-  shadow.used.mem = 0;
-  shadow.defd = shadow.used;
-  
-  for (i = insns; i ; i = NEXT_INSN (i))
-    {
-      if (GET_CODE (i) == NOTE)
-	{
-	  switch (NOTE_LINE_NUMBER (i))
-	    {
-	    case NOTE_INSN_EH_REGION_BEG:
-	      exception_nesting++;
-	      if (trap_pending)
-		goto close_shadow;
-	      break;
-
-	    case NOTE_INSN_EH_REGION_END:
-	      exception_nesting--;
-	      if (trap_pending)
-		goto close_shadow;
-	      break;
-
-	    case NOTE_INSN_EPILOGUE_BEG:
-	      if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
-		goto close_shadow;
-	      break;
-	    }
-	}
-      else if (trap_pending)
-	{
-	  if (alpha_tp == ALPHA_TP_FUNC)
-	    {
-	      if (GET_CODE (i) == JUMP_INSN
-		  && GET_CODE (PATTERN (i)) == RETURN)
-		goto close_shadow;
-	    }
-	  else if (alpha_tp == ALPHA_TP_INSN)
-	    {
-	      if (optimize > 0)
-		{
-		  struct shadow_summary sum;
-
-		  sum.used.i = 0;
-		  sum.used.fp = 0;
-		  sum.used.mem = 0;
-		  sum.defd = sum.used;
-
-		  switch (GET_CODE (i))
-		    {
-		    case INSN:
-		      /* Annoyingly, get_attr_trap will abort on these.  */
-		      if (GET_CODE (PATTERN (i)) == USE
-			  || GET_CODE (PATTERN (i)) == CLOBBER)
-			break;
-
-		      summarize_insn (PATTERN (i), &sum, 0);
-
-		      if ((sum.defd.i & shadow.defd.i)
-			  || (sum.defd.fp & shadow.defd.fp))
-			{
-			  /* (c) would be violated */
-			  goto close_shadow;
-			}
-
-		      /* Combine shadow with summary of current insn: */
-		      shadow.used.i   |= sum.used.i;
-		      shadow.used.fp  |= sum.used.fp;
-		      shadow.used.mem |= sum.used.mem;
-		      shadow.defd.i   |= sum.defd.i;
-		      shadow.defd.fp  |= sum.defd.fp;
-		      shadow.defd.mem |= sum.defd.mem;
-
-		      if ((sum.defd.i & shadow.used.i)
-			  || (sum.defd.fp & shadow.used.fp)
-			  || (sum.defd.mem & shadow.used.mem))
-			{
-			  /* (a) would be violated (also takes care of (b))  */
-			  if (get_attr_trap (i) == TRAP_YES
-			      && ((sum.defd.i & sum.used.i)
-				  || (sum.defd.fp & sum.used.fp)))
-			    abort ();
-
-			  goto close_shadow;
-			}
-		      break;
-
-		    case JUMP_INSN:
-		    case CALL_INSN:
-		    case CODE_LABEL:
-		      goto close_shadow;
-
-		    default:
-		      abort ();
-		    }
-		}
-	      else
-		{
-		close_shadow:
-		  n = emit_insn_before (gen_trapb (), i);
-		  PUT_MODE (n, TImode);
-		  PUT_MODE (i, TImode);
-		  trap_pending = 0;
-		  shadow.used.i = 0;
-		  shadow.used.fp = 0;
-		  shadow.used.mem = 0;
-		  shadow.defd = shadow.used;
-		}
-	    }
-	}
-
-      if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
-	  && GET_CODE (i) == INSN
-	  && GET_CODE (PATTERN (i)) != USE
-	  && GET_CODE (PATTERN (i)) != CLOBBER
-	  && get_attr_trap (i) == TRAP_YES)
-	{
-	  if (optimize && !trap_pending)
-	    summarize_insn (PATTERN (i), &shadow, 0);
-	  trap_pending = 1;
-	}
-    }
-}
-
-#ifdef HAIFA
-/* Alpha can only issue instruction groups simultaneously if they are
-   suitibly aligned.  This is very processor-specific.  */
-
-enum alphaev4_pipe {
-  EV4_STOP = 0,
-  EV4_IB0 = 1,
-  EV4_IB1 = 2,
-  EV4_IBX = 4
-};
-
-enum alphaev5_pipe {
-  EV5_STOP = 0,
-  EV5_NONE = 1,
-  EV5_E01 = 2,
-  EV5_E0 = 4,
-  EV5_E1 = 8,
-  EV5_FAM = 16,
-  EV5_FA = 32,
-  EV5_FM = 64
-};
-
-static enum alphaev4_pipe alphaev4_insn_pipe PROTO((rtx));
-static enum alphaev5_pipe alphaev5_insn_pipe PROTO((rtx));
-static rtx alphaev4_next_group PROTO((rtx, int*, int*));
-static rtx alphaev5_next_group PROTO((rtx, int*, int*));
-static rtx alphaev4_next_nop PROTO((int*));
-static rtx alphaev5_next_nop PROTO((int*));
-
-static void alpha_align_insns
-  PROTO((rtx, int, rtx (*)(rtx, int*, int*), rtx (*)(int*), int));
-
-static enum alphaev4_pipe
-alphaev4_insn_pipe (insn)
-     rtx insn;
-{
-  if (recog_memoized (insn) < 0)
-    return EV4_STOP;
-  if (get_attr_length (insn) != 4)
-    return EV4_STOP;
-
-  switch (get_attr_type (insn))
-    {
-    case TYPE_ILD:
-    case TYPE_FLD:
-      return EV4_IBX;
-
-    case TYPE_LDSYM:
-    case TYPE_IADD:
-    case TYPE_ILOG:
-    case TYPE_ICMOV:
-    case TYPE_ICMP:
-    case TYPE_IST:
-    case TYPE_FST:
-    case TYPE_SHIFT:
-    case TYPE_IMUL:
-    case TYPE_FBR:
-      return EV4_IB0;
-
-    case TYPE_MISC:
-    case TYPE_IBR:
-    case TYPE_JSR:
-    case TYPE_FCPYS:
-    case TYPE_FCMOV:
-    case TYPE_FADD:
-    case TYPE_FDIV:
-    case TYPE_FMUL:
-      return EV4_IB1;
-
-    default:
-      abort();
-    }
-}
-
-static enum alphaev5_pipe
-alphaev5_insn_pipe (insn)
-     rtx insn;
-{
-  if (recog_memoized (insn) < 0)
-    return EV5_STOP;
-  if (get_attr_length (insn) != 4)
-    return EV5_STOP;
-
-  switch (get_attr_type (insn))
-    {
-    case TYPE_ILD:
-    case TYPE_FLD:
-    case TYPE_LDSYM:
-    case TYPE_IADD:
-    case TYPE_ILOG:
-    case TYPE_ICMOV:
-    case TYPE_ICMP:
-      return EV5_E01;
-
-    case TYPE_IST:
-    case TYPE_FST:
-    case TYPE_SHIFT:
-    case TYPE_IMUL:
-    case TYPE_MISC:
-    case TYPE_MVI:
-      return EV5_E0;
-
-    case TYPE_IBR:
-    case TYPE_JSR:
-      return EV5_E1;
-
-    case TYPE_FCPYS:
-      return EV5_FAM;
-
-    case TYPE_FBR:
-    case TYPE_FCMOV:
-    case TYPE_FADD:
-    case TYPE_FDIV:
-      return EV5_FA;
-
-    case TYPE_FMUL:
-      return EV5_FM;
-
-    default:
-      abort();
-    }
-}
-
-/* IN_USE is a mask of the slots currently filled within the insn group. 
-   The mask bits come from alphaev4_pipe above.  If EV4_IBX is set, then
-   the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1. 
-
-   LEN is, of course, the length of the group in bytes.  */
-
-static rtx
-alphaev4_next_group (insn, pin_use, plen)
-     rtx insn;
-     int *pin_use, *plen;
-{
-  int len, in_use;
-
-  len = in_use = 0;
-
-  if (GET_RTX_CLASS (GET_CODE (insn)) != 'i'
-      || GET_CODE (PATTERN (insn)) == CLOBBER
-      || GET_CODE (PATTERN (insn)) == USE)
-    goto next_and_done;
-
-  while (1)
-    {
-      enum alphaev4_pipe pipe;
-
-      pipe = alphaev4_insn_pipe (insn);
-      switch (pipe)
-	{
-	case EV4_STOP:
-	  /* Force complex instructions to start new groups.  */
-	  if (in_use)
-	    goto done;
-
-	  /* If this is a completely unrecognized insn, its an asm.
-	     We don't know how long it is, so record length as -1 to
-	     signal a needed realignment.  */
-	  if (recog_memoized (insn) < 0)
-	    len = -1;
-	  else
-	    len = get_attr_length (insn);
-	  goto next_and_done;
-
-	case EV4_IBX:
-	  if (in_use & EV4_IB0)
-	    {
-	      if (in_use & EV4_IB1)
-		goto done;
-	      in_use |= EV4_IB1;
-	    }
-	  else
-	    in_use |= EV4_IB0 | EV4_IBX;
-	  break;
-
-	case EV4_IB0:
-	  if (in_use & EV4_IB0)
-	    {
-	      if (!(in_use & EV4_IBX) || (in_use & EV4_IB1))
-		goto done;
-	      in_use |= EV4_IB1;
-	    }
-	  in_use |= EV4_IB0;
-	  break;
-
-	case EV4_IB1:
-	  if (in_use & EV4_IB1)
-	    goto done;
-	  in_use |= EV4_IB1;
-	  break;
-
-	default:
-	  abort();
-	}
-      len += 4;
-      
-      /* Haifa doesn't do well scheduling branches.  */
-      if (GET_CODE (insn) == JUMP_INSN)
-	goto next_and_done;
-
-    next:
-      insn = next_nonnote_insn (insn);
-
-      if (!insn || GET_RTX_CLASS (GET_CODE (insn)) != 'i')
-	goto done;
-
-      /* Let Haifa tell us where it thinks insn group boundaries are.  */
-      if (GET_MODE (insn) == TImode)
-	goto done;
-
-      if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
-	goto next;
-    }
-
- next_and_done:
-  insn = next_nonnote_insn (insn);
-
- done:
-  *plen = len;
-  *pin_use = in_use;
-  return insn;
-}
-
-/* IN_USE is a mask of the slots currently filled within the insn group. 
-   The mask bits come from alphaev5_pipe above.  If EV5_E01 is set, then
-   the insn in EV5_E0 can be swapped by the hardware into EV5_E1. 
-
-   LEN is, of course, the length of the group in bytes.  */
-
-static rtx
-alphaev5_next_group (insn, pin_use, plen)
-     rtx insn;
-     int *pin_use, *plen;
-{
-  int len, in_use;
-
-  len = in_use = 0;
-
-  if (GET_RTX_CLASS (GET_CODE (insn)) != 'i'
-      || GET_CODE (PATTERN (insn)) == CLOBBER
-      || GET_CODE (PATTERN (insn)) == USE)
-    goto next_and_done;
-
-  while (1)
-    {
-      enum alphaev5_pipe pipe;
-
-      pipe = alphaev5_insn_pipe (insn);
-      switch (pipe)
-	{
-	case EV5_STOP:
-	  /* Force complex instructions to start new groups.  */
-	  if (in_use)
-	    goto done;
-
-	  /* If this is a completely unrecognized insn, its an asm.
-	     We don't know how long it is, so record length as -1 to
-	     signal a needed realignment.  */
-	  if (recog_memoized (insn) < 0)
-	    len = -1;
-	  else
-	    len = get_attr_length (insn);
-	  goto next_and_done;
-
-	/* ??? Most of the places below, we would like to abort, as 
-	   it would indicate an error either in Haifa, or in the 
-	   scheduling description.  Unfortunately, Haifa never 
-	   schedules the last instruction of the BB, so we don't
-	   have an accurate TI bit to go off.  */
-	case EV5_E01:
-	  if (in_use & EV5_E0)
-	    {
-	      if (in_use & EV5_E1)
-		goto done;
-	      in_use |= EV5_E1;
-	    }
-	  else
-	    in_use |= EV5_E0 | EV5_E01;
-	  break;
-
-	case EV5_E0:
-	  if (in_use & EV5_E0)
-	    {
-	      if (!(in_use & EV5_E01) || (in_use & EV5_E1))
-		goto done;
-	      in_use |= EV5_E1;
-	    }
-	  in_use |= EV5_E0;
-	  break;
-
-	case EV5_E1:
-	  if (in_use & EV5_E1)
-	    goto done;
-	  in_use |= EV5_E1;
-	  break;
-
-	case EV5_FAM:
-	  if (in_use & EV5_FA)
-	    {
-	      if (in_use & EV5_FM)
-		goto done;
-	      in_use |= EV5_FM;
-	    }
-	  else
-	    in_use |= EV5_FA | EV5_FAM;
-	  break;
-
-	case EV5_FA:
-	  if (in_use & EV5_FA)
-	    goto done;
-	  in_use |= EV5_FA;
-	  break;
-
-	case EV5_FM:
-	  if (in_use & EV5_FM)
-	    goto done;
-	  in_use |= EV5_FM;
-	  break;
-
-	case EV5_NONE:
-	  break;
-
-	default:
-	  abort();
-	}
-      len += 4;
-      
-      /* Haifa doesn't do well scheduling branches.  */
-      /* ??? If this is predicted not-taken, slotting continues, except
-	 that no more IBR, FBR, or JSR insns may be slotted.  */
-      if (GET_CODE (insn) == JUMP_INSN)
-	goto next_and_done;
-
-    next:
-      insn = next_nonnote_insn (insn);
-
-      if (!insn || GET_RTX_CLASS (GET_CODE (insn)) != 'i')
-	goto done;
-
-      /* Let Haifa tell us where it thinks insn group boundaries are.  */
-      if (GET_MODE (insn) == TImode)
-	goto done;
-
-      if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
-	goto next;
-    }
-
- next_and_done:
-  insn = next_nonnote_insn (insn);
-
- done:
-  *plen = len;
-  *pin_use = in_use;
-  return insn;
-}
-
-static rtx
-alphaev4_next_nop (pin_use)
-     int *pin_use;
-{
-  int in_use = *pin_use;
-  rtx nop;
-
-  if (!(in_use & EV4_IB0))
-    {
-      in_use |= EV4_IB0;
-      nop = gen_nop ();
-    }
-  else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX)
-    {
-      in_use |= EV4_IB1;
-      nop = gen_nop ();
-    }
-  else if (TARGET_FP && !(in_use & EV4_IB1))
-    {
-      in_use |= EV4_IB1;
-      nop = gen_fnop ();
-    }
-  else
-    nop = gen_unop ();
-
-  *pin_use = in_use;
-  return nop;
-}
-
-static rtx
-alphaev5_next_nop (pin_use)
-     int *pin_use;
-{
-  int in_use = *pin_use;
-  rtx nop;
-
-  if (!(in_use & EV5_E1))
-    {
-      in_use |= EV5_E1;
-      nop = gen_nop ();
-    }
-  else if (TARGET_FP && !(in_use & EV5_FA))
-    {
-      in_use |= EV5_FA;
-      nop = gen_fnop ();
-    }
-  else if (TARGET_FP && !(in_use & EV5_FM))
-    {
-      in_use |= EV5_FM;
-      nop = gen_fnop ();
-    }
-  else
-    nop = gen_unop ();
-
-  *pin_use = in_use;
-  return nop;
-}
-
-/* The instruction group alignment main loop.  */
-
-static void
-alpha_align_insns (insns, max_align, next_group, next_nop, gp_in_use)
-     rtx insns;
-     int max_align;
-     rtx (*next_group) PROTO((rtx, int*, int*));
-     rtx (*next_nop) PROTO((int*));
-     int gp_in_use;
-{
-  /* ALIGN is the known alignment for the insn group.  */
-  int align;
-  /* OFS is the offset of the current insn in the insn group.  */
-  int ofs;
-  int prev_in_use, in_use, len;
-  rtx i, next;
-
-  /* Let shorten branches care for assigning alignments to code labels.  */
-  shorten_branches (insns);
-
-  align = (FUNCTION_BOUNDARY/BITS_PER_UNIT < max_align
-	   ? FUNCTION_BOUNDARY/BITS_PER_UNIT : max_align);
-
-  /* Account for the initial GP load, which happens before the scheduled
-     prologue we emitted as RTL.  */
-  ofs = prev_in_use = 0;
-  if (alpha_does_function_need_gp())
-    {
-      ofs = 8 & (align - 1);
-      prev_in_use = gp_in_use;
-    }
-
-  i = insns;
-  if (GET_CODE (i) == NOTE)
-    i = next_nonnote_insn (i);
-
-  while (i)
-    {
-      next = (*next_group)(i, &in_use, &len);
-
-      /* When we see a label, resync alignment etc.  */
-      if (GET_CODE (i) == CODE_LABEL)
-	{
-	  int new_align = 1 << label_to_alignment (i);
-	  if (new_align >= align)
-	    {
-	      align = new_align < max_align ? new_align : max_align;
-	      ofs = 0;
-	    }
-	  else if (ofs & (new_align-1))
-	    ofs = (ofs | (new_align-1)) + 1;
-	  if (len != 0)
-	    abort();
-	}
-
-      /* Handle complex instructions special.  */
-      else if (in_use == 0)
-	{
-	  /* Asms will have length < 0.  This is a signal that we have
-	     lost alignment knowledge.  Assume, however, that the asm
-	     will not mis-align instructions.  */
-	  if (len < 0)
-	    {
-	      ofs = 0;
-	      align = 4;
-	      len = 0;
-	    }
-	}
-
-      /* If the known alignment is smaller than the recognized insn group,
-	 realign the output.  */
-      else if (align < len)
-	{
-	  int new_log_align = len > 8 ? 4 : 3;
-	  rtx where;
-
-	  where = prev_nonnote_insn (i);
-	  if (!where || GET_CODE (where) != CODE_LABEL)
-	    where = i;
-
-	  emit_insn_before (gen_realign (GEN_INT (new_log_align)), where);
-	  align = 1 << new_log_align;
-	  ofs = 0;
-	}
-
-      /* If the group won't fit in the same INT16 as the previous,
-	 we need to add padding to keep the group together.  Rather
-	 than simply leaving the insn filling to the assembler, we
-	 can make use of the knowledge of what sorts of instructions
-	 were issued in the previous group to make sure that all of
-	 the added nops are really free.  */
-      else if (ofs + len > align)
-	{
-	  int nop_count = (align - ofs) / 4;
-	  rtx where;
-
-	  /* Insert nops before labels and branches to truely merge the
-	     execution of the nops with the previous instruction group.  */
-	  where = prev_nonnote_insn (i);
-	  if (where)
-	    {
-	      if (GET_CODE (where) == CODE_LABEL)
-		{
-		  rtx where2 = prev_nonnote_insn (where);
-		  if (where2 && GET_CODE (where2) == JUMP_INSN)
-		    where = where2;
-		}
-	      else if (GET_CODE (where) != JUMP_INSN)
-		where = i;
-	    }
-	  else
-	    where = i;
-
-	  do 
-	    emit_insn_before ((*next_nop)(&prev_in_use), where);
-	  while (--nop_count);
-	  ofs = 0;
-	}
-
-      ofs = (ofs + len) & (align - 1);
-      prev_in_use = in_use;
-      i = next;
-    }
-}
-#endif /* HAIFA */
-
-/* Machine dependant reorg pass.  */
-
-void
-alpha_reorg (insns)
-     rtx insns;
-{
-  if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
-    alpha_handle_trap_shadows (insns);
-
-#ifdef HAIFA
-  /* Due to the number of extra trapb insns, don't bother fixing up
-     alignment when trap precision is instruction.  Moreover, we can
-     only do our job when sched2 is run and Haifa is our scheduler.  */
-  if (optimize && !optimize_size
-      && alpha_tp != ALPHA_TP_INSN
-      && flag_schedule_insns_after_reload)
-    {
-      if (alpha_cpu == PROCESSOR_EV4)
-	alpha_align_insns (insns, 8, alphaev4_next_group,
-			   alphaev4_next_nop, EV4_IB0);
-      else if (alpha_cpu == PROCESSOR_EV5)
-	alpha_align_insns (insns, 16, alphaev5_next_group,
-			   alphaev5_next_nop, EV5_E01 | EV5_E0);
-    }
-#endif
-}
-
-
-/* Check a floating-point value for validity for a particular machine mode.  */
-
-static char * const float_strings[] =
-{
-  /* These are for FLOAT_VAX.  */
-   "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
-  "-1.70141173319264430e+38",
-   "2.93873587705571877e-39", /* 2^-128 */
-  "-2.93873587705571877e-39",
-  /* These are for the default broken IEEE mode, which traps
-     on infinity or denormal numbers.  */
-   "3.402823466385288598117e+38", /* 2^128 (1 - 2^-24) */
-  "-3.402823466385288598117e+38",
-   "1.1754943508222875079687e-38", /* 2^-126 */
-  "-1.1754943508222875079687e-38",
-};
-
-static REAL_VALUE_TYPE float_values[8];
-static int inited_float_values = 0;
-
-int
-check_float_value (mode, d, overflow)
-     enum machine_mode mode;
-     REAL_VALUE_TYPE *d;
-     int overflow ATTRIBUTE_UNUSED;
-{
-
-  if (TARGET_IEEE || TARGET_IEEE_CONFORMANT || TARGET_IEEE_WITH_INEXACT)
-    return 0;
-
-  if (inited_float_values == 0)
-    {
-      int i;
-      for (i = 0; i < 8; i++)
-	float_values[i] = REAL_VALUE_ATOF (float_strings[i], DFmode);
-
-      inited_float_values = 1;
-    }
-
-  if (mode == SFmode)
-    {
-      REAL_VALUE_TYPE r;
-      REAL_VALUE_TYPE *fvptr;
-
-      if (TARGET_FLOAT_VAX)
-	fvptr = &float_values[0];
-      else
-	fvptr = &float_values[4];
-
-      bcopy ((char *) d, (char *) &r, sizeof (REAL_VALUE_TYPE));
-      if (REAL_VALUES_LESS (fvptr[0], r))
-	{
-	  bcopy ((char *) &fvptr[0], (char *) d,
-		 sizeof (REAL_VALUE_TYPE));
-	  return 1;
-	}
-      else if (REAL_VALUES_LESS (r, fvptr[1]))
-	{
-	  bcopy ((char *) &fvptr[1], (char *) d,
-		 sizeof (REAL_VALUE_TYPE));
-	  return 1;
-	}
-      else if (REAL_VALUES_LESS (dconst0, r)
-		&& REAL_VALUES_LESS (r, fvptr[2]))
-	{
-	  bcopy ((char *) &dconst0, (char *) d, sizeof (REAL_VALUE_TYPE));
-	  return 1;
-	}
-      else if (REAL_VALUES_LESS (r, dconst0)
-		&& REAL_VALUES_LESS (fvptr[3], r))
-	{
-	  bcopy ((char *) &dconst0, (char *) d, sizeof (REAL_VALUE_TYPE));
-	  return 1;
-	}
-    }
-
-  return 0;
-}
-
-#if OPEN_VMS
-
-/* Return the VMS argument type corresponding to MODE.  */
-
-enum avms_arg_type
-alpha_arg_type (mode)
-     enum machine_mode mode;
-{
-  switch (mode)
-    {
-    case SFmode:
-      return TARGET_FLOAT_VAX ? FF : FS;
-    case DFmode:
-      return TARGET_FLOAT_VAX ? FD : FT;
-    default:
-      return I64;
-    }
-}
-
-/* Return an rtx for an integer representing the VMS Argument Information
-   register value.  */
-
-struct rtx_def *
-alpha_arg_info_reg_val (cum)
-     CUMULATIVE_ARGS cum;
-{
-  unsigned HOST_WIDE_INT regval = cum.num_args;
-  int i;
-
-  for (i = 0; i < 6; i++)
-    regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
-
-  return GEN_INT (regval);
-}
-
-/* Structure to collect function names for final output
-   in link section.  */
-
-enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
-
-
-struct alpha_links {
-  struct alpha_links *next;
-  char *name;
-  enum links_kind kind;
-};
-
-static struct alpha_links *alpha_links_base = 0;
-
-/* Make (or fake) .linkage entry for function call.
-
-   IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.  */
-
-void
-alpha_need_linkage (name, is_local)
-    char *name;
-    int is_local;
-{
-  rtx x;
-  struct alpha_links *lptr, *nptr;
-
-  if (name[0] == '*')
-    name++;
-
-  /* Is this name already defined ?  */
-
-  for (lptr = alpha_links_base; lptr; lptr = lptr->next)
-    if (strcmp (lptr->name, name) == 0)
-      {
-	if (is_local)
-	  {
-	    /* Defined here but external assumed.  */
-	    if (lptr->kind == KIND_EXTERN)
-	      lptr->kind = KIND_LOCAL;
-	  }
-	else
-	  {
-	    /* Used here but unused assumed.  */
-	    if (lptr->kind == KIND_UNUSED)
-	      lptr->kind = KIND_LOCAL;
-	  }
-	return;
-      }
-
-  nptr = (struct alpha_links *) xmalloc (sizeof (struct alpha_links));
-  nptr->next = alpha_links_base;
-  nptr->name = xstrdup (name);
-
-  /* Assume external if no definition.  */
-  nptr->kind = (is_local ? KIND_UNUSED : KIND_EXTERN);
-
-  /* Ensure we have an IDENTIFIER so assemble_name can mark is used.  */
-  get_identifier (name);
-
-  alpha_links_base = nptr;
-
-  return;
-}
-
-
-void
-alpha_write_linkage (stream)
-    FILE *stream;
-{
-  struct alpha_links *lptr, *nptr;
-
-  readonly_section ();
-
-  fprintf (stream, "\t.align 3\n");
-
-  for (lptr = alpha_links_base; lptr; lptr = nptr)
-    {
-      nptr = lptr->next;
-
-      if (lptr->kind == KIND_UNUSED
-	  || ! TREE_SYMBOL_REFERENCED (get_identifier (lptr->name)))
-	continue;
-
-      fprintf (stream, "$%s..lk:\n", lptr->name);
-      if (lptr->kind == KIND_LOCAL)   
-	{
-	  /*  Local and used, build linkage pair.  */
-	  fprintf (stream, "\t.quad %s..en\n", lptr->name);
-	  fprintf (stream, "\t.quad %s\n", lptr->name);
-	}
-      else
-	/* External and used, request linkage pair.  */
-	fprintf (stream, "\t.linkage %s\n", lptr->name);
-    }
-}
-
-#else
-
-void
-alpha_need_linkage (name, is_local)
-     char *name ATTRIBUTE_UNUSED;
-     int is_local ATTRIBUTE_UNUSED;
-{
-}
-
-#endif /* OPEN_VMS */
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
deleted file mode 100755
index dc9f3d3..0000000
--- a/gcc/config/alpha/alpha.h
+++ /dev/null
@@ -1,2518 +0,0 @@
-/* Definitions of target machine for GNU compiler, for DEC Alpha.
-   Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Write out the correct language type definition for the header files.  
-   Unless we have assembler language, write out the symbols for C.  */
-#define CPP_SPEC "\
-%{!undef:\
-%{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\
-%{.cc|.cxx|.C:-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus }\
-%{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\
-%{!.S:%{!.cc:%{!.cxx:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}\
-%{mieee:-D_IEEE_FP }\
-%{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\
-%(cpp_cpu) %(cpp_subtarget)"
-
-#ifndef CPP_SUBTARGET_SPEC
-#define CPP_SUBTARGET_SPEC ""
-#endif
-
-/* Set the spec to use for signed char.  The default tests the above macro
-   but DEC's compiler can't handle the conditional in a "constant"
-   operand.  */
-
-#define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
-
-#define WORD_SWITCH_TAKES_ARG(STR)		\
- (!strcmp (STR, "rpath") || !strcmp (STR, "include")	\
-  || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \
-  || !strcmp (STR, "idirafter") || !strcmp (STR, "iprefix") \
-  || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \
-  || !strcmp (STR, "isystem"))
-
-/* Print subsidiary information on the compiler version in use.  */
-#define TARGET_VERSION
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-/* Which processor to schedule for. The cpu attribute defines a list that
-   mirrors this list, so changes to alpha.md must be made at the same time.  */
-
-enum processor_type
- {PROCESSOR_EV4,			/* 2106[46]{a,} */
-  PROCESSOR_EV5,			/* 21164{a,pc,} */
-  PROCESSOR_EV6};			/* 21264 */
-
-extern enum processor_type alpha_cpu;
-
-enum alpha_trap_precision
-{
-  ALPHA_TP_PROG,	/* No precision (default).  */
-  ALPHA_TP_FUNC,      	/* Trap contained within originating function.  */
-  ALPHA_TP_INSN		/* Instruction accuracy and code is resumption safe. */
-};
-
-enum alpha_fp_rounding_mode
-{
-  ALPHA_FPRM_NORM,	/* Normal rounding mode.  */
-  ALPHA_FPRM_MINF,	/* Round towards minus-infinity.  */
-  ALPHA_FPRM_CHOP,	/* Chopped rounding mode (towards 0). */
-  ALPHA_FPRM_DYN	/* Dynamic rounding mode.  */
-};
-
-enum alpha_fp_trap_mode
-{
-  ALPHA_FPTM_N,		/* Normal trap mode. */
-  ALPHA_FPTM_U,		/* Underflow traps enabled.  */
-  ALPHA_FPTM_SU,	/* Software completion, w/underflow traps */
-  ALPHA_FPTM_SUI	/* Software completion, w/underflow & inexact traps */
-};
-
-extern int target_flags;
-
-extern enum alpha_trap_precision alpha_tp;
-extern enum alpha_fp_rounding_mode alpha_fprm;
-extern enum alpha_fp_trap_mode alpha_fptm;
-
-/* This means that floating-point support exists in the target implementation
-   of the Alpha architecture.  This is usually the default.  */
-
-#define MASK_FP		1
-#define TARGET_FP	(target_flags & MASK_FP)
-
-/* This means that floating-point registers are allowed to be used.  Note
-   that Alpha implementations without FP operations are required to
-   provide the FP registers.  */
-
-#define MASK_FPREGS	2
-#define TARGET_FPREGS	(target_flags & MASK_FPREGS)
-
-/* This means that gas is used to process the assembler file.  */
-
-#define MASK_GAS 4
-#define TARGET_GAS	(target_flags & MASK_GAS)
-
-/* This means that we should mark procedures as IEEE conformant. */
-
-#define MASK_IEEE_CONFORMANT 8
-#define TARGET_IEEE_CONFORMANT	(target_flags & MASK_IEEE_CONFORMANT)
-
-/* This means we should be IEEE-compliant except for inexact.  */
-
-#define MASK_IEEE	16
-#define TARGET_IEEE	(target_flags & MASK_IEEE)
-
-/* This means we should be fully IEEE-compliant.  */
-
-#define MASK_IEEE_WITH_INEXACT 32
-#define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
-
-/* This means we must construct all constants rather than emitting
-   them as literal data.  */
-
-#define MASK_BUILD_CONSTANTS 128
-#define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
-
-/* This means we handle floating points in VAX F- (float)
-   or G- (double) Format.  */
-
-#define MASK_FLOAT_VAX 512
-#define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
-
-/* This means that the processor has byte and half word loads and stores
-   (the BWX extension).  */
-
-#define MASK_BWX 1024
-#define TARGET_BWX	(target_flags & MASK_BWX)
-
-/* This means that the processor has the CIX extension.  */
-#define MASK_CIX 2048
-#define TARGET_CIX	(target_flags & MASK_CIX)
-
-/* This means that the processor has the MAX extension.  */
-#define MASK_MAX 4096
-#define TARGET_MAX	(target_flags & MASK_MAX)
-
-/* This means that the processor is an EV5, EV56, or PCA56.  This is defined
-   only in TARGET_CPU_DEFAULT.  */
-#define MASK_CPU_EV5 8192
-
-/* Likewise for EV6.  */
-#define MASK_CPU_EV6 16384
-
-/* This means we support the .arch directive in the assembler.  Only
-   defined in TARGET_CPU_DEFAULT.  */
-#define MASK_SUPPORT_ARCH 32768
-#define TARGET_SUPPORT_ARCH	(target_flags & MASK_SUPPORT_ARCH)
-
-/* These are for target os support and cannot be changed at runtime.  */
-#ifndef TARGET_WINDOWS_NT
-#define TARGET_WINDOWS_NT 0
-#endif
-#ifndef TARGET_OPEN_VMS
-#define TARGET_OPEN_VMS 0
-#endif
-
-#ifndef TARGET_AS_CAN_SUBTRACT_LABELS
-#define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
-#endif
-#ifndef TARGET_CAN_FAULT_IN_PROLOGUE
-#define TARGET_CAN_FAULT_IN_PROLOGUE 0
-#endif
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES							\
-  { {"no-soft-float", MASK_FP, "Use hardware fp"},			\
-    {"soft-float", - MASK_FP, "Do not use hardware fp"},		\
-    {"fp-regs", MASK_FPREGS, "Use fp registers"},			\
-    {"no-fp-regs", - (MASK_FP|MASK_FPREGS), "Do not use fp registers"},	\
-    {"alpha-as", -MASK_GAS, "Do not assume GAS"},			\
-    {"gas", MASK_GAS, "Assume GAS"},					\
-    {"ieee-conformant", MASK_IEEE_CONFORMANT,				\
-     "Request IEEE-conformant math library routines (OSF/1)"},		\
-    {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT,				\
-     "Emit IEEE-conformant code, without inexact exceptions"},		\
-    {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT,	\
-     "Emit IEEE-conformant code, with inexact exceptions"},		\
-    {"build-constants", MASK_BUILD_CONSTANTS,				\
-     "Do not emit complex integer constants to read-only memory"},	\
-    {"float-vax", MASK_FLOAT_VAX, "Use VAX fp"},			\
-    {"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"},		\
-    {"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"},	\
-    {"no-bwx", -MASK_BWX, ""},						\
-    {"cix", MASK_CIX, "Emit code for the counting ISA extension"},	\
-    {"no-cix", -MASK_CIX, ""},						\
-    {"max", MASK_MAX, "Emit code for the motion video ISA extension"},	\
-    {"no-max", -MASK_MAX, ""},						\
-    {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
-
-#define TARGET_DEFAULT MASK_FP|MASK_FPREGS
-
-#ifndef TARGET_CPU_DEFAULT
-#define TARGET_CPU_DEFAULT 0
-#endif
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an initializer
-   with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the fixed
-   part of the option name, and the address of a variable.  The
-   variable, type `char *', is set to the variable part of the given
-   option if the fixed part matches.  The actual option name is made
-   by appending `-m' to the specified name.
-
-   Here is an example which defines `-mshort-data-NUMBER'.  If the
-   given option is `-mshort-data-512', the variable `m88k_short_data'
-   will be set to the string `"512"'.
-
-	extern char *m88k_short_data;
-	#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } }  */
-
-extern char *alpha_cpu_string;  /* For -mcpu= */
-extern char *alpha_fprm_string;	/* For -mfp-rounding-mode=[n|m|c|d] */
-extern char *alpha_fptm_string;	/* For -mfp-trap-mode=[n|u|su|sui]  */
-extern char *alpha_tp_string;	/* For -mtrap-precision=[p|f|i] */
-extern char *alpha_mlat_string;	/* For -mmemory-latency= */
-
-#define TARGET_OPTIONS					\
-{							\
-  {"cpu=",		&alpha_cpu_string,		\
-   "Generate code for a given CPU"},			\
-  {"fp-rounding-mode=",	&alpha_fprm_string,		\
-   "Control the generated fp rounding mode"},		\
-  {"fp-trap-mode=",	&alpha_fptm_string,		\
-   "Control the IEEE trap mode"},			\
-  {"trap-precision=",	&alpha_tp_string,		\
-   "Control the precision given to fp exceptions"},	\
-  {"memory-latency=",	&alpha_mlat_string,		\
-   "Tune expected memory latency"},			\
-}
-
-/* Attempt to describe CPU characteristics to the preprocessor.  */
-
-/* Corresponding to amask... */
-#define CPP_AM_BWX_SPEC	"-D__alpha_bwx__ -Acpu(bwx)"
-#define CPP_AM_MAX_SPEC	"-D__alpha_max__ -Acpu(max)"
-#define CPP_AM_CIX_SPEC	"-D__alpha_cix__ -Acpu(cix)"
-
-/* Corresponding to implver... */
-#define CPP_IM_EV4_SPEC	"-D__alpha_ev4__ -Acpu(ev4)"
-#define CPP_IM_EV5_SPEC	"-D__alpha_ev5__ -Acpu(ev5)"
-#define CPP_IM_EV6_SPEC	"-D__alpha_ev6__ -Acpu(ev6)"
-
-/* Common combinations.  */
-#define CPP_CPU_EV4_SPEC	"%(cpp_im_ev4)"
-#define CPP_CPU_EV5_SPEC	"%(cpp_im_ev5)"
-#define CPP_CPU_EV56_SPEC	"%(cpp_im_ev5) %(cpp_am_bwx)"
-#define CPP_CPU_PCA56_SPEC	"%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
-#define CPP_CPU_EV6_SPEC	"%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_cix)"
-
-#ifndef CPP_CPU_DEFAULT_SPEC
-# if TARGET_CPU_DEFAULT & MASK_CPU_EV6
-#  define CPP_CPU_DEFAULT_SPEC		CPP_CPU_EV6_SPEC
-# else
-#  if TARGET_CPU_DEFAULT & MASK_CPU_EV5
-#   if TARGET_CPU_DEFAULT & MASK_MAX
-#    define CPP_CPU_DEFAULT_SPEC	CPP_CPU_PCA56_SPEC
-#   else
-#    if TARGET_CPU_DEFAULT & MASK_BWX
-#     define CPP_CPU_DEFAULT_SPEC	CPP_CPU_EV56_SPEC
-#    else
-#     define CPP_CPU_DEFAULT_SPEC	CPP_CPU_EV5_SPEC
-#    endif
-#   endif
-#  else
-#   define CPP_CPU_DEFAULT_SPEC		CPP_CPU_EV4_SPEC
-#  endif
-# endif
-#endif /* CPP_CPU_DEFAULT_SPEC */
-
-#ifndef CPP_CPU_SPEC
-#define CPP_CPU_SPEC "\
-%{!undef:-Acpu(alpha) -Amachine(alpha) -D__alpha -D__alpha__ \
-%{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
-%{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
-%{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
-%{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\
-%{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\
-%{!mcpu*:%(cpp_cpu_default) }}"
-#endif
-
-/* This macro defines names of additional specifications to put in the
-   specs that can be used in various specifications like CC1_SPEC.  Its
-   definition is an initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   specification name, and a string constant that used by the GNU CC driver
-   program.
-
-   Do not define this macro if it does not need to do anything.  */
-
-#ifndef SUBTARGET_EXTRA_SPECS
-#define SUBTARGET_EXTRA_SPECS
-#endif
-
-#define EXTRA_SPECS				\
-  { "cpp_am_bwx", CPP_AM_BWX_SPEC },		\
-  { "cpp_am_max", CPP_AM_MAX_SPEC },		\
-  { "cpp_am_cix", CPP_AM_CIX_SPEC },		\
-  { "cpp_im_ev4", CPP_IM_EV4_SPEC },		\
-  { "cpp_im_ev5", CPP_IM_EV5_SPEC },		\
-  { "cpp_im_ev6", CPP_IM_EV6_SPEC },		\
-  { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC },		\
-  { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC },		\
-  { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC },	\
-  { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC },	\
-  { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC },		\
-  { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC },	\
-  { "cpp_cpu", CPP_CPU_SPEC },			\
-  { "cpp_subtarget", CPP_SUBTARGET_SPEC },	\
-  SUBTARGET_EXTRA_SPECS
-
-
-/* Sometimes certain combinations of command options do not make sense
-   on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   On the Alpha, it is used to translate target-option strings into
-   numeric values.  */
-
-extern void override_options ();
-#define OVERRIDE_OPTIONS override_options ()
-
-
-/* Define this macro to change register usage conditional on target flags.
-
-   On the Alpha, we use this to disable the floating-point registers when
-   they don't exist.  */
-
-#define CONDITIONAL_REGISTER_USAGE	\
-  if (! TARGET_FPREGS)			\
-    for (i = 32; i < 63; i++)		\
-      fixed_regs[i] = call_used_regs[i] = 1;
-
-/* Show we can debug even without a frame pointer.  */
-#define CAN_DEBUG_WITHOUT_FP
-
-/* target machine storage layout */
-
-/* Define to enable software floating point emulation. */
-#define REAL_ARITHMETIC
-
-/* The following #defines are used when compiling the routines in
-   libgcc1.c.  Since the Alpha calling conventions require single
-   precision floats to be passed in the floating-point registers
-   (rather than in the general registers) we have to build the
-   libgcc1.c routines in such a way that they know the actual types
-   of their formal arguments and the actual types of their return
-   values.  Otherwise, gcc will generate calls to the libgcc1.c
-   routines, passing arguments in the floating-point registers,
-   but the libgcc1.c routines will expect their arguments on the
-   stack (where the Alpha calling conventions require structs &
-   unions to be passed).  */
-
-#define FLOAT_VALUE_TYPE	double
-#define INTIFY(FLOATVAL)	(FLOATVAL)
-#define FLOATIFY(INTVAL)	(INTVAL)
-#define FLOAT_ARG_TYPE		double
-
-/* Define the size of `int'.  The default is the same as the word size.  */
-#define INT_TYPE_SIZE 32
-
-/* Define the size of `long long'.  The default is the twice the word size.  */
-#define LONG_LONG_TYPE_SIZE 64
-
-/* The two floating-point formats we support are S-floating, which is
-   4 bytes, and T-floating, which is 8 bytes.  `float' is S and `double'
-   and `long double' are T.  */
-
-#define FLOAT_TYPE_SIZE 32
-#define DOUBLE_TYPE_SIZE 64
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-#define	WCHAR_TYPE "unsigned int"
-#define	WCHAR_TYPE_SIZE 32
-
-/* Define this macro if it is advisable to hold scalars in registers
-   in a wider mode than that declared by the program.  In such cases, 
-   the value is constrained to be within the bounds of the declared
-   type, but kept valid in the wider mode.  The signedness of the
-   extension may differ from that of the type.
-
-   For Alpha, we always store objects in a full register.  32-bit objects
-   are always sign-extended, but smaller objects retain their signedness.  */
-
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)  \
-  if (GET_MODE_CLASS (MODE) == MODE_INT		\
-      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)	\
-    {						\
-      if ((MODE) == SImode)			\
-	(UNSIGNEDP) = 0;			\
-      (MODE) = DImode;				\
-    }
-
-/* Define this if function arguments should also be promoted using the above
-   procedure.  */
-
-#define PROMOTE_FUNCTION_ARGS
-
-/* Likewise, if the function return value is promoted.  */
-
-#define PROMOTE_FUNCTION_RETURN
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-
-   There are no such instructions on the Alpha, but the documentation
-   is little endian.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.
-   This is false on the Alpha.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered.
-
-   For Alpha we can decide arbitrarily since there are no machine instructions
-   for them.  Might as well be consistent with bytes. */
-#define WORDS_BIG_ENDIAN 0
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 64
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 8
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 64
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 64
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 64
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 256
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 64
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Align loop starts for optimal branching.  
-
-   ??? Kludge this and the next macro for the moment by not doing anything if
-   we don't optimize and also if we are writing ECOFF symbols to work around
-   a bug in DEC's assembler. */
-
-#define LOOP_ALIGN(LABEL) \
-  (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
-
-/* This is how to align an instruction for optimal branching.  On
-   Alpha we'll get better performance by aligning on an octaword
-   boundary.  */
-
-#define LABEL_ALIGN_AFTER_BARRIER(FILE)	\
-  (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 64
-
-/* For atomic access to objects, must have at least 32-bit alignment
-   unless the machine has byte operations.  */
-#define MINIMUM_ATOMIC_ALIGNMENT (TARGET_BWX ? 8 : 32)
-
-/* Align all constants and variables to at least a word boundary so
-   we can pick up pieces of them faster.  */
-/* ??? Only if block-move stuff knows about different source/destination
-   alignment.  */
-#if 0
-#define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
-#define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
-#endif
-
-/* Set this non-zero if move instructions will actually fail to work
-   when given unaligned data.
-
-   Since we get an error message when we do one, call them invalid.  */
-
-#define STRICT_ALIGNMENT 1
-
-/* Set this non-zero if unaligned move instructions are extremely slow.
-
-   On the Alpha, they trap.  */
-
-#define SLOW_UNALIGNED_ACCESS 1
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   We define all 32 integer registers, even though $31 is always zero,
-   and all 32 floating-point registers, even though $f31 is also
-   always zero.  We do not bother defining the FP status register and
-   there are no other registers. 
-
-   Since $31 is always zero, we will use register number 31 as the
-   argument pointer.  It will never appear in the generated code
-   because we will always be eliminating it in favor of the stack
-   pointer or hardware frame pointer.
-
-   Likewise, we use $f31 for the frame pointer, which will always
-   be eliminated in favor of the hardware frame pointer or the
-   stack pointer.  */
-
-#define FIRST_PSEUDO_REGISTER 64
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.  */
-
-#define FIXED_REGISTERS  \
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS  \
- {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
-  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
-
-/* List the order in which to allocate registers.  Each register must be
-   listed once, even those in FIXED_REGISTERS.
-
-   We allocate in the following order:
-   $f10-$f15		(nonsaved floating-point register)
-   $f22-$f30		(likewise)
-   $f21-$f16		(likewise, but input args)
-   $f0			(nonsaved, but return value)
-   $f1			(nonsaved, but immediate before saved)
-   $f2-$f9		(saved floating-point registers)
-   $1-$8		(nonsaved integer registers)
-   $22-$25		(likewise)
-   $28			(likewise)
-   $0			(likewise, but return value)
-   $21-$16		(likewise, but input args)
-   $27			(procedure value in OSF, nonsaved in NT)
-   $9-$14		(saved integer registers)
-   $26			(return PC)
-   $15			(frame pointer)
-   $29			(global pointer)
-   $30, $31, $f31	(stack pointer and always zero/ap & fp)  */
-
-#define REG_ALLOC_ORDER		\
-  {42, 43, 44, 45, 46, 47,		\
-   54, 55, 56, 57, 58, 59, 60, 61, 62,	\
-   53, 52, 51, 50, 49, 48,		\
-   32, 33,				\
-   34, 35, 36, 37, 38, 39, 40, 41,	\
-   1, 2, 3, 4, 5, 6, 7, 8,		\
-   22, 23, 24, 25,			\
-   28,					\
-   0,					\
-   21, 20, 19, 18, 17, 16,		\
-   27,					\
-   9, 10, 11, 12, 13, 14,		\
-   26,					\
-   15,					\
-   29,					\
-   30, 31, 63 }
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On Alpha, the integer registers can hold any mode.  The floating-point
-   registers can hold 32-bit and 64-bit integers as well, but not 16-bit
-   or 8-bit values.  If we only allowed the larger integers into FP registers,
-   we'd have to say that QImode and SImode aren't tiable, which is a
-   pain.  So say all registers can hold everything and see how that works.  */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-
-#define MODES_TIEABLE_P(MODE1, MODE2) 1
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* Alpha pc isn't overloaded on a register that the compiler knows about.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 30
-
-/* Base register for access to local variables of the function.  */
-#define HARD_FRAME_POINTER_REGNUM 15
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 31
-
-/* Base register for access to local variables of function.  */
-#define FRAME_POINTER_REGNUM 63
-
-/* Register in which static-chain is passed to a function. 
-
-   For the Alpha, this is based on an example; the calling sequence
-   doesn't seem to specify this.  */
-#define STATIC_CHAIN_REGNUM 1
-
-/* Register in which address to store a structure value
-   arrives in the function.  On the Alpha, the address is passed
-   as a hidden argument.  */
-#define STRUCT_VALUE 0
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
-		 LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES				\
- {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS	\
-  { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) \
- ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS NO_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C)	\
- ((C) == 'f' ? FLOAT_REGS : NO_REGS)
-
-/* Define this macro to change register usage conditional on target flags.  */
-/* #define CONDITIONAL_REGISTER_USAGE  */
-
-/* The letters I, J, K, L, M, N, O, and P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   For Alpha:
-   `I' is used for the range of constants most insns can contain.
-   `J' is the constant zero.
-   `K' is used for the constant in an LDA insn.
-   `L' is used for the constant in a LDAH insn.
-   `M' is used for the constants that can be AND'ed with using a ZAP insn.
-   `N' is used for complemented 8-bit constants.
-   `O' is used for negated 8-bit constants.
-   `P' is used for the constants 1, 2 and 3.  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)				\
-  ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100	\
-   : (C) == 'J' ? (VALUE) == 0					\
-   : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000	\
-   : (C) == 'L' ? (((VALUE) & 0xffff) == 0			\
-                  && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
-   : (C) == 'M' ? zap_mask (VALUE)				\
-   : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100	\
-   : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100	\
-   : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3	\
-   : 0)
-
-/* Similar, but for floating or large integer constants, and defining letters
-   G and H.   Here VALUE is the CONST_DOUBLE rtx itself.
-
-   For Alpha, `G' is the floating-point constant zero.  `H' is a CONST_DOUBLE
-   that is the operand of a ZAP insn.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  			\
-  ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT	\
-		 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))		\
-   : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode				\
-		   && zap_mask (CONST_DOUBLE_LOW (VALUE))		\
-		   && zap_mask (CONST_DOUBLE_HIGH (VALUE)))		\
-   : 0)
-
-/* Optional extra constraints for this machine.
-
-   For the Alpha, `Q' means that this is a memory operand but not a
-   reference to an unaligned location.
-
-   `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
-   function.
-
-   'S' is a 6-bit constant (valid for a shift insn).  */
-
-#define EXTRA_CONSTRAINT(OP, C)				\
-  ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) != AND	\
-   : (C) == 'R' ? current_file_function_operand (OP, Pmode)		\
-   : (C) == 'S' ? (GET_CODE (OP) == CONST_INT				\
-		   && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64)	\
-   : 0)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.
-
-   On the Alpha, all constants except zero go into a floating-point
-   register via memory.  */
-
-#define PREFERRED_RELOAD_CLASS(X, CLASS)		\
-  (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
-   ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\
-   : (CLASS))
-
-/* Loading and storing HImode or QImode values to and from memory
-   usually requires a scratch register.  The exceptions are loading
-   QImode and HImode from an aligned address to a general register
-   unless byte instructions are permitted.
-   We also cannot load an unaligned address or a paradoxical SUBREG into an
-   FP register.   */
-
-#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN)			\
-(((GET_CODE (IN) == MEM 						\
-   || (GET_CODE (IN) == REG && REGNO (IN) >= FIRST_PSEUDO_REGISTER)	\
-   || (GET_CODE (IN) == SUBREG						\
-       && (GET_CODE (SUBREG_REG (IN)) == MEM				\
-	   || (GET_CODE (SUBREG_REG (IN)) == REG			\
-	       && REGNO (SUBREG_REG (IN)) >= FIRST_PSEUDO_REGISTER))))	\
-  && (((CLASS) == FLOAT_REGS						\
-       && ((MODE) == SImode || (MODE) == HImode || (MODE) == QImode))	\
-      || (((MODE) == QImode || (MODE) == HImode)			\
-	  && ! TARGET_BWX && unaligned_memory_operand (IN, MODE)))) \
- ? GENERAL_REGS								\
- : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == MEM			\
-    && GET_CODE (XEXP (IN, 0)) == AND) ? GENERAL_REGS			\
- : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == SUBREG			\
-    && (GET_MODE_SIZE (GET_MODE (IN))					\
-	> GET_MODE_SIZE (GET_MODE (SUBREG_REG (IN))))) ? GENERAL_REGS	\
- : NO_REGS)
-
-#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT)			\
-(((GET_CODE (OUT) == MEM 						\
-   || (GET_CODE (OUT) == REG && REGNO (OUT) >= FIRST_PSEUDO_REGISTER)	\
-   || (GET_CODE (OUT) == SUBREG						\
-       && (GET_CODE (SUBREG_REG (OUT)) == MEM				\
-	   || (GET_CODE (SUBREG_REG (OUT)) == REG			\
-	       && REGNO (SUBREG_REG (OUT)) >= FIRST_PSEUDO_REGISTER)))) \
-  && ((((MODE) == HImode || (MODE) == QImode)				\
-       && (! TARGET_BWX || (CLASS) == FLOAT_REGS))			\
-      || ((MODE) == SImode && (CLASS) == FLOAT_REGS)))			\
- ? GENERAL_REGS								\
- : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == MEM			\
-    && GET_CODE (XEXP (OUT, 0)) == AND) ? GENERAL_REGS			\
- : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == SUBREG			\
-    && (GET_MODE_SIZE (GET_MODE (OUT))					\
-	> GET_MODE_SIZE (GET_MODE (SUBREG_REG (OUT))))) ? GENERAL_REGS	\
- : NO_REGS)
-
-/* If we are copying between general and FP registers, we need a memory
-   location unless the CIX extension is available.  */
-
-#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
- (! TARGET_CIX && (CLASS1) != (CLASS2))
-
-/* Specify the mode to be used for memory when a secondary memory
-   location is needed.  If MODE is floating-point, use it.  Otherwise,
-   widen to a word like the default.  This is needed because we always
-   store integers in FP registers in quadword format.  This whole
-   area is very tricky! */
-#define SECONDARY_MEMORY_NEEDED_MODE(MODE)		\
-  (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE)		\
-   : GET_MODE_SIZE (MODE) >= 4 ? (MODE)			\
-   : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)				\
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* If defined, gives a class of registers that cannot be used as the
-   operand of a SUBREG that changes the size of the object.  */
-
-#define CLASS_CANNOT_CHANGE_SIZE	FLOAT_REGS
-
-/* Define the cost of moving between registers of various classes.  Moving
-   between FLOAT_REGS and anything else except float regs is expensive. 
-   In fact, we make it quite expensive because we really don't want to
-   do these moves unless it is clearly worth it.  Optimizations may
-   reduce the impact of not being able to allocate a pseudo to a
-   hard register.  */
-
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)		\
-  (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS)	\
-   ? 2							\
-   : TARGET_CIX ? 3 : 4+2*alpha_memory_latency)
-
-/* A C expressions returning the cost of moving data of MODE from a register to
-   or from memory.
-
-   On the Alpha, bump this up a bit.  */
-
-extern int alpha_memory_latency;
-#define MEMORY_MOVE_COST(MODE,CLASS,IN)  (2*alpha_memory_latency)
-
-/* Provide the cost of a branch.  Exact meaning under development.  */
-#define BRANCH_COST 5
-
-/* Adjust the cost of dependencies.  */
-
-#define ADJUST_COST(INSN,LINK,DEP,COST) \
-  (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST)
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-/* #define FRAME_GROWS_DOWNWARD */
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On Alpha, don't define this because there are no push insns.  */
-/*  #define PUSH_ROUNDING(BYTES) */
-
-/* Define this to be nonzero if stack checking is built into the ABI.  */
-#define STACK_CHECK_BUILTIN 1
-
-/* Define this if the maximum size of all the outgoing args is to be
-   accumulated and pushed during the prologue.  The amount can be
-   found in the variable current_function_outgoing_args_size.  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Offset of first parameter from the argument pointer register value.  */
-
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Definitions for register eliminations.
-
-   We have two registers that can be eliminated on the Alpha.  First, the
-   frame pointer register can often be eliminated in favor of the stack
-   pointer register.  Secondly, the argument pointer register can always be
-   eliminated; it is replaced with either the stack or frame pointer. */
-
-/* This is an array of structures.  Each structure initializes one pair
-   of eliminable registers.  The "from" register number is given first,
-   followed by "to".  Eliminations of the same "from" register are listed
-   in order of preference.  */
-
-#define ELIMINABLE_REGS				     \
-{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	     \
- { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},   \
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},	     \
- { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
-
-/* Given FROM and TO register numbers, say whether this elimination is allowed.
-   Frame pointer elimination is automatically handled.
-
-   All eliminations are valid since the cases where FP can't be
-   eliminated are already handled.  */
-
-#define CAN_ELIMINATE(FROM, TO) 1
-
-/* Round up to a multiple of 16 bytes.  */
-#define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
-
-/* Define the offset between two registers, one to be eliminated, and the other
-   its replacement, at the start of a routine.  */
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
-{ if ((FROM) == FRAME_POINTER_REGNUM)					\
-    (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size)	\
-		+ alpha_sa_size ());					\
-  else if ((FROM) == ARG_POINTER_REGNUM)				\
-    (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size)	\
-		+ alpha_sa_size ()					\
-		+ (ALPHA_ROUND (get_frame_size ()			\
-			       + current_function_pretend_args_size)	\
-		   - current_function_pretend_args_size));		\
-}
-
-/* Define this if stack space is still allocated for a parameter passed
-   in a register.  */
-/* #define REG_PARM_STACK_SPACE */
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.
-
-   On Alpha the value is found in $0 for integer functions and
-   $f0 for floating-point functions.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)	\
-  gen_rtx (REG,							\
-	   ((INTEGRAL_TYPE_P (VALTYPE)				\
-	     && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD)	\
-	    || POINTER_TYPE_P (VALTYPE))			\
-	   ? word_mode : TYPE_MODE (VALTYPE),			\
-	   ((TARGET_FPREGS					\
-	     && (TREE_CODE (VALTYPE) == REAL_TYPE		\
-		 || TREE_CODE (VALTYPE) == COMPLEX_TYPE))	\
-	    ? 32 : 0))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE)	\
-   gen_rtx (REG, MODE,						\
-	    (TARGET_FPREGS					\
-	     && (GET_MODE_CLASS (MODE) == MODE_FLOAT		\
-		 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
-	     ? 32 : 0))
-
-/* The definition of this macro implies that there are cases where
-   a scalar value cannot be returned in registers.
-
-   For the Alpha, any structure or union type is returned in memory, as
-   are integers whose size is larger than 64 bits.  */
-
-#define RETURN_IN_MEMORY(TYPE) \
-  (TYPE_MODE (TYPE) == BLKmode \
-   || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.  */
-
-#define FUNCTION_VALUE_REGNO_P(N)  \
-  ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
-
-/* 1 if N is a possible register number for function argument passing.
-   On Alpha, these are $16-$21 and $f16-$f21.  */
-
-#define FUNCTION_ARG_REGNO_P(N) \
-  (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On Alpha, this is a single integer, which is a number of words
-   of arguments scanned so far.
-   Thus 6 or more means all following args should go on the stack.  */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)  (CUM) = 0
-
-/* Define intermediate macro to compute the size (in registers) of an argument
-   for the Alpha.  */
-
-#define ALPHA_ARG_SIZE(MODE, TYPE, NAMED)				\
-((MODE) != BLKmode							\
- ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD 	\
- : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
-  if (MUST_PASS_IN_STACK (MODE, TYPE))					\
-    (CUM) = 6;								\
-  else									\
-    (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-
-   On Alpha the first 6 words of args are normally in registers
-   and the rest are pushed.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)	\
-((CUM) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE)	\
- ? gen_rtx(REG, (MODE),				\
-	   (CUM) + 16 + ((TARGET_FPREGS		\
-			  && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT  \
-			      || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
-			 * 32))			\
- : 0)
-
-/* Specify the padding direction of arguments.
-
-   On the Alpha, we must pad upwards in order to be able to pass args in
-   registers.  */
-
-#define FUNCTION_ARG_PADDING(MODE, TYPE)	upward
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)	\
-((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED)	\
- ? 6 - (CUM) : 0)
-
-/* Perform any needed actions needed for a function that is receiving a
-   variable number of arguments. 
-
-   CUM is as above.
-
-   MODE and TYPE are the mode and type of the current parameter.
-
-   PRETEND_SIZE is a variable that should be set to the amount of stack
-   that must be pushed by the prolog to pretend that our caller pushed
-   it.
-
-   Normally, this macro will push all remaining incoming registers on the
-   stack and set PRETEND_SIZE to the length of the registers pushed. 
-
-   On the Alpha, we allocate space for all 12 arg registers, but only
-   push those that are remaining.
-
-   However, if NO registers need to be saved, don't allocate any space.
-   This is not only because we won't need the space, but because AP includes
-   the current_pretend_args_size and we don't want to mess up any
-   ap-relative addresses already made.
-
-   If we are not to use the floating-point registers, save the integer
-   registers where we would put the floating-point registers.  This is
-   not the most efficient way to implement varargs with just one register
-   class, but it isn't worth doing anything more efficient in this rare
-   case.  */
-   
-
-#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL)	\
-{ if ((CUM) < 6)							\
-    {									\
-      if (! (NO_RTL))							\
-	{								\
-	  move_block_from_reg						\
-	    (16 + CUM,							\
-	     gen_rtx (MEM, BLKmode,					\
-		      plus_constant (virtual_incoming_args_rtx,		\
-				     ((CUM) + 6)* UNITS_PER_WORD)),	\
-	     6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD);			\
-	  move_block_from_reg						\
-	    (16 + (TARGET_FPREGS ? 32 : 0) + CUM,			\
-	     gen_rtx (MEM, BLKmode,					\
-		      plus_constant (virtual_incoming_args_rtx,		\
-				     (CUM) * UNITS_PER_WORD)),		\
-	     6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD);			\
-	   emit_insn (gen_blockage ());					\
-	 }								\
-      PRETEND_SIZE = 12 * UNITS_PER_WORD;				\
-    }									\
-}
-
-/* Try to output insns to set TARGET equal to the constant C if it can be
-   done in less than N insns.  Do all computations in MODE.  Returns the place
-   where the output has been placed if it can be done and the insns have been
-   emitted.  If it would take more than N insns, zero is returned and no
-   insns and emitted.  */
-extern struct rtx_def *alpha_emit_set_const ();
-extern struct rtx_def *alpha_emit_set_long_const ();
-extern struct rtx_def *alpha_emit_conditional_branch ();
-extern struct rtx_def *alpha_emit_conditional_move ();
-
-/* Generate necessary RTL for __builtin_saveregs().
-   ARGLIST is the argument list; see expr.c.  */
-extern struct rtx_def *alpha_builtin_saveregs ();
-#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) alpha_builtin_saveregs (ARGLIST)
-
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  Note that we can't use "rtx" here
-   since it hasn't been defined!  */
-
-extern struct rtx_def *alpha_compare_op0, *alpha_compare_op1;
-extern int alpha_compare_fp_p;
-
-/* Define the information needed to modify the epilogue for EH.  */
-
-extern struct rtx_def *alpha_eh_epilogue_sp_ofs;
-
-/* Make (or fake) .linkage entry for function call.
-   IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.  */
-extern void alpha_need_linkage ();
-
-/* This macro defines the start of an assembly comment.  */
-
-#define ASM_COMMENT_START " #"
-
-/* This macro produces the initial definition of a function.  */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
-  alpha_start_function(FILE,NAME,DECL);
-extern void alpha_start_function ();
-
-/* This macro closes up a function definition for the assembler.  */
-
-#define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
-  alpha_end_function(FILE,NAME,DECL)
-extern void alpha_end_function ();
-   
-/* This macro notes the end of the prologue.  */
-
-#define FUNCTION_END_PROLOGUE(FILE)  output_end_prologue (FILE)
-extern void output_end_prologue ();
-
-/* Output any profiling code before the prologue.  */
-
-#define PROFILE_BEFORE_PROLOGUE 1
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  Under OSF/1, profiling is enabled
-   by simply passing -pg to the assembler and linker.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.
-   This assumes that __bb_init_func doesn't garble a1-a5. */
-
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)			\
-    do {							\
-	ASM_OUTPUT_REG_PUSH (FILE, 16);				\
-	fputs ("\tlda $16,$PBX32\n", (FILE));			\
-	fputs ("\tldq $26,0($16)\n", (FILE));			\
-	fputs ("\tbne $26,1f\n", (FILE));			\
-	fputs ("\tlda $27,__bb_init_func\n", (FILE));		\
-	fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE));	\
-	fputs ("\tldgp $29,0($26)\n", (FILE));			\
-	fputs ("1:\n", (FILE));					\
-	ASM_OUTPUT_REG_POP (FILE, 16);				\
-    } while (0);
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  */
-
-#define BLOCK_PROFILER(FILE, BLOCKNO)				\
-    do {							\
-	int blockn = (BLOCKNO);					\
-	fputs ("\tsubq $30,16,$30\n", (FILE));			\
-	fputs ("\tstq $26,0($30)\n", (FILE));			\
-	fputs ("\tstq $27,8($30)\n", (FILE));			\
-	fputs ("\tlda $26,$PBX34\n", (FILE));			\
-	fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn);	\
-	fputs ("\taddq $27,1,$27\n", (FILE));			\
-	fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn);	\
-	fputs ("\tldq $26,0($30)\n", (FILE));			\
-	fputs ("\tldq $27,8($30)\n", (FILE));			\
-	fputs ("\taddq $30,16,$30\n", (FILE));			\
-    } while (0)
-
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.
-
-   The trampoline should set the static chain pointer to value placed
-   into the trampoline and should branch to the specified routine.  
-   Note that $27 has been set to the address of the trampoline, so we can
-   use it for addressability of the two data items.  Trampolines are always
-   aligned to FUNCTION_BOUNDARY, which is 64 bits.  */
-
-#define TRAMPOLINE_TEMPLATE(FILE)		\
-do {						\
-  fprintf (FILE, "\tldq $1,24($27)\n");		\
-  fprintf (FILE, "\tldq $27,16($27)\n");	\
-  fprintf (FILE, "\tjmp $31,($27),0\n");	\
-  fprintf (FILE, "\tnop\n");			\
-  fprintf (FILE, "\t.quad 0,0\n");		\
-} while (0)
-
-/* Section in which to place the trampoline.  On Alpha, instructions
-   may only be placed in a text segment.  */
-
-#define TRAMPOLINE_SECTION text_section
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE    32
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-  alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
-extern void alpha_initialize_trampoline ();
-
-/* A C expression whose value is RTL representing the value of the return
-   address for the frame COUNT steps up from the current frame.
-   FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
-   the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined.  */
-
-#define RETURN_ADDR_RTX  alpha_return_addr
-extern struct rtx_def *alpha_return_addr ();
-
-/* Before the prologue, RA lives in $26. */
-#define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (Pmode, 26)
-
-/* Initialize data used by insn expanders.  This is called from insn_emit,
-   once for every function before code is generated.  */
-
-#define INIT_EXPANDERS  alpha_init_expanders ()
-extern void alpha_init_expanders ();
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) 0
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32  \
- || (REGNO) == 63 || reg_renumber[REGNO] == 63)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-#define MAX_REGS_PER_ADDRESS 1
-
-/* Recognize any constant value that is a valid address.  For the Alpha,
-   there are only constants none since we want to use LDA to load any
-   symbolic addresses into registers.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == CONST_INT	\
-   && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
-
-/* Include all constant integers and constant doubles, but not
-   floating-point, except for floating-point zero.  */
-
-#define LEGITIMATE_CONSTANT_P(X)  		\
-  (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT	\
-   || (X) == CONST0_RTX (GET_MODE (X)))
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) 0
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X)  \
-  (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address. 
-
-   For Alpha, we have either a constant address or the sum of a register
-   and a constant address, or just a register.  For DImode, any of those
-   forms can be surrounded with an AND that clear the low-order three bits;
-   this is an "unaligned" access.
-
-   First define the basic valid address.  */
-
-#define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
-{ if (REG_P (X) && REG_OK_FOR_BASE_P (X))	\
-    goto ADDR;					\
-  if (CONSTANT_ADDRESS_P (X))			\
-    goto ADDR;					\
-  if (GET_CODE (X) == PLUS			\
-      && REG_P (XEXP (X, 0))			\
-      && REG_OK_FOR_BASE_P (XEXP (X, 0))	\
-      && CONSTANT_ADDRESS_P (XEXP (X, 1)))	\
-    goto ADDR;					\
-}
-
-/* Now accept the simple address, or, for DImode only, an AND of a simple
-   address that turns off the low three bits.  */
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \
-  if ((MODE) == DImode				\
-      && GET_CODE (X) == AND			\
-      && GET_CODE (XEXP (X, 1)) == CONST_INT	\
-      && INTVAL (XEXP (X, 1)) == -8)		\
-    GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output. 
-
-   For the Alpha, there are three cases we handle:
-
-   (1) If the address is (plus reg const_int) and the CONST_INT is not a
-       valid offset, compute the high part of the constant and add it to the
-       register.  Then our address is (plus temp low-part-const).
-   (2) If the address is (const (plus FOO const_int)), find the low-order
-       part of the CONST_INT.  Then load FOO plus any high-order part of the
-       CONST_INT into a register.  Our address is (plus reg low-part-const).
-       This is done to reduce the number of GOT entries.
-   (3) If we have a (plus reg const), emit the load as in (2), then add
-       the two registers, and finally generate (plus reg low-part-const) as
-       our address.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)			\
-{ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG	\
-      && GET_CODE (XEXP (X, 1)) == CONST_INT			\
-      && ! CONSTANT_ADDRESS_P (XEXP (X, 1)))			\
-    {								\
-      HOST_WIDE_INT val = INTVAL (XEXP (X, 1));			\
-      HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
-      HOST_WIDE_INT highpart = val - lowpart;			\
-      rtx high = GEN_INT (highpart);				\
-      rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0),	\
-			       high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \
-								\
-      (X) = plus_constant (temp, lowpart);			\
-      goto WIN;							\
-    }								\
-  else if (GET_CODE (X) == CONST				\
-	   && GET_CODE (XEXP (X, 0)) == PLUS			\
-	   && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT)	\
-    {								\
-      HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1));	\
-      HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
-      HOST_WIDE_INT highpart = val - lowpart;			\
-      rtx high = XEXP (XEXP (X, 0), 0);				\
-								\
-      if (highpart)						\
-	high = plus_constant (high, highpart);			\
-								\
-      (X) = plus_constant (force_reg (Pmode, high), lowpart);	\
-      goto WIN;							\
-    }								\
-  else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
-	   && GET_CODE (XEXP (X, 1)) == CONST			\
-	   && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS		\
-	   && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \
-    {								\
-      HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \
-      HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
-      HOST_WIDE_INT highpart = val - lowpart;			\
-      rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0);		\
-								\
-      if (highpart)						\
-	high = plus_constant (high, highpart);			\
-								\
-      high = expand_binop (Pmode, add_optab, XEXP (X, 0),	\
-			   force_reg (Pmode, high),		\
-			   high, 1, OPTAB_LIB_WIDEN);		\
-      (X) = plus_constant (high, lowpart);			\
-      goto WIN;							\
-    }								\
-}
-
-/* Try a machine-dependent way of reloading an illegitimate address
-   operand.  If we find one, push the reload and jump to WIN.  This
-   macro is used in only one place: `find_reloads_address' in reload.c.
-
-   For the Alpha, we wish to handle large displacements off a base
-   register by splitting the addend across an ldah and the mem insn.
-   This cuts number of extra insns needed from 3 to 1.  */
-   
-#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN)	\
-do {									\
-  /* We must recognize output that we have already generated ourselves.  */ \
-  if (GET_CODE (X) == PLUS						\
-      && GET_CODE (XEXP (X, 0)) == PLUS					\
-      && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG			\
-      && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT			\
-      && GET_CODE (XEXP (X, 1)) == CONST_INT)				\
-    {									\
-      push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR,	\
-		   BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0,	\
-		   OPNUM, TYPE);					\
-      goto WIN;								\
-    }									\
-  if (GET_CODE (X) == PLUS						\
-      && GET_CODE (XEXP (X, 0)) == REG					\
-      && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER			\
-      && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE)			\
-      && GET_CODE (XEXP (X, 1)) == CONST_INT)				\
-    {									\
-      HOST_WIDE_INT val = INTVAL (XEXP (X, 1));				\
-      HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;		\
-      HOST_WIDE_INT high						\
-	= (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;	\
-									\
-      /* Check for 32-bit overflow.  */					\
-      if (high + low != val)						\
-	break;								\
-									\
-      /* Reload the high part into a base reg; leave the low part	\
-	 in the mem directly.  */					\
-									\
-      X = gen_rtx_PLUS (GET_MODE (X),					\
-			gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0),	\
-				      GEN_INT (high)),			\
-			GEN_INT (low));					\
-	  								\
-      push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR,	\
-		   BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0,	\
-		   OPNUM, TYPE);					\
-      goto WIN;								\
-    }									\
-} while (0)
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the Alpha this is true only for the unaligned modes.   We can
-   simplify this test since we know that the address must be valid.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  \
-{ if (GET_CODE (ADDR) == AND) goto LABEL; }
-
-/* Compute the cost of an address.  For the Alpha, all valid addresses are
-   the same cost.  */
-
-#define ADDRESS_COST(X)  0
-
-/* Machine-dependent reorg pass.   */
-#define MACHINE_DEPENDENT_REORG(X)	alpha_reorg(X)
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-
-   Do not define this if the table should contain absolute addresses.
-   On the Alpha, the table is really GP-relative, not relative to the PC
-   of the table, but we pretend that it is PC-relative; this should be OK,
-   but we should try to find some better way sometime.  */
-#define CASE_VECTOR_PC_RELATIVE 1
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.
-
-   We actually lie a bit here as overflow conditions are different.  But
-   they aren't being checked anyway.  */
-
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move to or from memory
-   in one reasonably fast instruction.  */
-
-#define MOVE_MAX 8
-
-/* If a memory-to-memory move would take MOVE_RATIO or more simple
-   move-instruction pairs, we will do a movstr or libcall instead.
-
-   Without byte/word accesses, we want no more than four instructions;
-   with, several single byte accesses are better.   */
-
-#define MOVE_RATIO  (TARGET_BWX ? 7 : 2)
-
-/* Largest number of bytes of an object that can be placed in a register.
-   On the Alpha we have plenty of registers, so use TImode.  */
-#define MAX_FIXED_MODE_SIZE	GET_MODE_BITSIZE (TImode)
-
-/* Nonzero if access to memory by bytes is no faster than for words.
-   Also non-zero if doing byte operations (specifically shifts) in registers
-   is undesirable. 
-
-   On the Alpha, we want to not use the byte operation and instead use
-   masking operations to access fields; these will save instructions.  */
-
-#define SLOW_BYTE_ACCESS	1
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.  */
-#define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
-
-/* Define if loading short immediate values into registers sign extends.  */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
-/* Define the value returned by a floating-point comparison instruction.  */
-
-#define FLOAT_STORE_FLAG_VALUE (TARGET_FLOAT_VAX ? 0.5 : 2.0)
-
-/* Canonicalize a comparison from one we don't have to one we do have.  */
-
-#define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
-  do {									\
-    if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
-	&& (GET_CODE (OP1) == REG || (OP1) == const0_rtx))		\
-      {									\
-	rtx tem = (OP0);						\
-	(OP0) = (OP1);							\
-	(OP1) = tem;							\
-	(CODE) = swap_condition (CODE);					\
-      }									\
-    if (((CODE) == LT || (CODE) == LTU)					\
-	&& GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256)		\
-      {									\
-	(CODE) = (CODE) == LT ? LE : LEU;				\
-	(OP1) = GEN_INT (255);						\
-      }									\
-  } while (0)
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode DImode
-
-/* Mode of a function address in a call instruction (for indexing purposes). */
-
-#define FUNCTION_MODE Pmode
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.
-
-   We define this on the Alpha so that gen_call and gen_call_value
-   get to see the SYMBOL_REF (for the hint field of the jsr).  It will
-   then copy it into a register, thus actually letting the address be
-   cse'ed.  */
-
-#define NO_FUNCTION_CSE
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
-   few bits. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Use atexit for static constructors/destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
-/* The EV4 is dual issue; EV5/EV6 are quad issue.  */
-#define ISSUE_RATE  (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
-
-/* Describe the fact that MULTI instructions are multiple instructions
-   and so to assume they don't pair with anything.  */
-#define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
-  if (recog_memoized (INSN) < 0 || get_attr_type (INSN) == TYPE_MULTI)	   \
-     (CAN_ISSUE_MORE) = 0
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.
-
-   If this is an 8-bit constant, return zero since it can be used
-   nearly anywhere with no cost.  If it is a valid operand for an
-   ADD or AND, likewise return 0 if we know it will be used in that
-   context.  Otherwise, return 2 since it might be used there later.
-   All other constants take at least two insns.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256)		\
-      return 0;							\
-  case CONST_DOUBLE:						\
-    if ((RTX) == CONST0_RTX (GET_MODE (RTX)))			\
-      return 0;							\
-    else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
-	|| ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
-      return 0;							\
-    else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
-      return 2;							\
-    else							\
-      return COSTS_N_INSNS (2);					\
-  case CONST:							\
-  case SYMBOL_REF:						\
-  case LABEL_REF:						\
-  switch (alpha_cpu)						\
-    {								\
-    case PROCESSOR_EV4:						\
-      return COSTS_N_INSNS (3);					\
-    case PROCESSOR_EV5:						\
-    case PROCESSOR_EV6:						\
-      return COSTS_N_INSNS (2);					\
-    default: abort();						\
-    }
-    
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  */
-   
-#define RTX_COSTS(X,CODE,OUTER_CODE)			\
-  case PLUS:  case MINUS:				\
-    if (FLOAT_MODE_P (GET_MODE (X)))			\
-      switch (alpha_cpu)				\
-        {						\
-        case PROCESSOR_EV4:				\
-          return COSTS_N_INSNS (6);			\
-        case PROCESSOR_EV5:				\
-        case PROCESSOR_EV6:				\
-          return COSTS_N_INSNS (4); 			\
-	default: abort();				\
-	}						\
-    else if (GET_CODE (XEXP (X, 0)) == MULT		\
-	     && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
-      return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE)	\
-	      + rtx_cost (XEXP (X, 1), OUTER_CODE));	\
-    break;						\
-  case MULT:						\
-    switch (alpha_cpu)					\
-      {							\
-      case PROCESSOR_EV4:				\
-        if (FLOAT_MODE_P (GET_MODE (X)))		\
-          return COSTS_N_INSNS (6);			\
-        return COSTS_N_INSNS (23);			\
-      case PROCESSOR_EV5:				\
-        if (FLOAT_MODE_P (GET_MODE (X)))		\
-          return COSTS_N_INSNS (4);			\
-        else if (GET_MODE (X) == DImode)		\
-          return COSTS_N_INSNS (12);			\
-        else						\
-          return COSTS_N_INSNS (8);			\
-      case PROCESSOR_EV6:				\
-	if (FLOAT_MODE_P (GET_MODE (X)))		\
-	  return COSTS_N_INSNS (4);			\
-	else 						\
-	  return COSTS_N_INSNS (7);			\
-      default: abort();					\
-      }							\
-  case ASHIFT:						\
-    if (GET_CODE (XEXP (X, 1)) == CONST_INT		\
-	&& INTVAL (XEXP (X, 1)) <= 3)			\
-      break;						\
-    /* ... fall through ... */				\
-  case ASHIFTRT:  case LSHIFTRT:			\
-    switch (alpha_cpu)					\
-      {							\
-      case PROCESSOR_EV4:				\
-        return COSTS_N_INSNS (2);			\
-      case PROCESSOR_EV5:				\
-      case PROCESSOR_EV6:				\
-        return COSTS_N_INSNS (1); 			\
-      default: abort();					\
-      }							\
-  case IF_THEN_ELSE:					\
-    switch (alpha_cpu)					\
-      {							\
-      case PROCESSOR_EV4:				\
-      case PROCESSOR_EV6:				\
-        return COSTS_N_INSNS (2);			\
-      case PROCESSOR_EV5:				\
-        return COSTS_N_INSNS (1); 			\
-      default: abort();					\
-      }							\
-  case DIV:  case UDIV:  case MOD:  case UMOD:		\
-    switch (alpha_cpu)					\
-      {							\
-      case PROCESSOR_EV4:				\
-        if (GET_MODE (X) == SFmode)			\
-          return COSTS_N_INSNS (34);			\
-        else if (GET_MODE (X) == DFmode)		\
-          return COSTS_N_INSNS (63);			\
-        else						\
-          return COSTS_N_INSNS (70);			\
-      case PROCESSOR_EV5:				\
-        if (GET_MODE (X) == SFmode)			\
-          return COSTS_N_INSNS (15);			\
-        else if (GET_MODE (X) == DFmode)		\
-          return COSTS_N_INSNS (22);			\
-        else						\
-          return COSTS_N_INSNS (70);	/* ??? */	\
-      case PROCESSOR_EV6:				\
-	if (GET_MODE (X) == SFmode)			\
-	  return COSTS_N_INSNS (12);			\
-        else if (GET_MODE (X) == DFmode)		\
-          return COSTS_N_INSNS (15);			\
-        else						\
-          return COSTS_N_INSNS (70);	/* ??? */	\
-      default: abort();					\
-      }							\
-  case MEM:						\
-    switch (alpha_cpu)					\
-      {							\
-      case PROCESSOR_EV4:				\
-      case PROCESSOR_EV6:				\
-        return COSTS_N_INSNS (3);			\
-      case PROCESSOR_EV5:				\
-        return COSTS_N_INSNS (2); 			\
-      default: abort();					\
-      }							\
-  case NEG:  case ABS:					\
-    if (! FLOAT_MODE_P (GET_MODE (X)))			\
-      break;						\
-    /* ... fall through ... */				\
-  case FLOAT:  case UNSIGNED_FLOAT:  case FIX:  case UNSIGNED_FIX: \
-  case FLOAT_EXTEND:  case FLOAT_TRUNCATE:		\
-    switch (alpha_cpu)					\
-      {							\
-      case PROCESSOR_EV4:				\
-        return COSTS_N_INSNS (6);			\
-      case PROCESSOR_EV5:				\
-      case PROCESSOR_EV6:				\
-        return COSTS_N_INSNS (4); 			\
-      default: abort();					\
-      }
-
-/* Control the assembler format that we output.  */
-
-/* We don't emit these labels, so as to avoid getting linker errors about
-   missing exception handling info.  If we emit a gcc_compiled. label into
-   text, and the file has no code, then the DEC assembler gives us a zero
-   sized text section with no associated exception handling info.  The
-   DEC linker sees this text section, and gives a warning saying that
-   the exception handling info is missing.  */
-#define ASM_IDENTIFY_GCC(x)
-#define ASM_IDENTIFY_LANGUAGE(x)
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before read-only data.  */
-
-#define READONLY_DATA_SECTION_ASM_OP ".rdata"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* Define an extra section for read-only data, a routine to enter it, and
-   indicate that it is for read-only data.
-
-   The first time we enter the readonly data section for a file, we write
-   eight bytes of zero.  This works around a bug in DEC's assembler in
-   some versions of OSF/1 V3.x.  */
-
-#define EXTRA_SECTIONS	readonly_data
-
-#define EXTRA_SECTION_FUNCTIONS					\
-void								\
-literal_section ()						\
-{								\
-  if (in_section != readonly_data)				\
-    {								\
-      static int firsttime = 1;				        \
-								\
-      fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
-      if (firsttime)						\
-	{							\
-	  firsttime = 0;				        \
-	  ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx);	\
-	}							\
-								\
-      in_section = readonly_data;				\
-    }								\
-}								\
-
-#define READONLY_DATA_SECTION	literal_section
-
-/* If we are referencing a function that is static, make the SYMBOL_REF
-   special.  We use this to see indicate we can branch to this function
-   without setting PV or restoring GP.  */
-
-#define ENCODE_SECTION_INFO(DECL)  \
-  if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
-    SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES						\
-{"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",		\
- "$9", "$10", "$11", "$12", "$13", "$14", "$15",		\
- "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",	\
- "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP",		\
- "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8",	\
- "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",		\
- "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
- "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
-
-/* How to renumber registers for dbx and gdb.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX ""
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
-
-/* This is how to output a label for a jump table.  Arguments are the same as
-   for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
-   passed. */
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN)	\
-{ ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM))
-
-/* Check a floating-point value for validity for a particular machine mode.  */
-
-#define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
-  ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t[2];							\
-	REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);			\
-	fprintf (FILE, "\t.quad 0x%lx%08lx\n",				\
-		t[1] & 0xffffffff, t[0] & 0xffffffff);			\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str);			\
-	fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'g':'t', str);			\
-      }									\
-  }
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)				\
-  do {								\
-    long t;							\
-    REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
-    fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff);		\
-} while (0)
-  
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  		\
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line defining a `long' constant.  */
-
-#define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE)	\
-( fprintf (FILE, "\t.quad "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-  fprintf (FILE, "\t.word %d\n",		\
-    (int)(GET_CODE (VALUE) == CONST_INT		\
-     ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)		\
-  fprintf (FILE, "\t.byte %d\n",		\
-    (int)(GET_CODE (VALUE) == CONST_INT		\
-     ? INTVAL (VALUE) & 0xff : (abort (), 0)))
-
-/* We use the default ASCII-output routine, except that we don't write more
-   than 50 characters since the assembler doesn't support very long lines.  */
-
-#define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
-  do {									      \
-    FILE *_hide_asm_out_file = (MYFILE);				      \
-    unsigned char *_hide_p = (unsigned char *) (MYSTRING);		      \
-    int _hide_thissize = (MYLENGTH);					      \
-    int _size_so_far = 0;						      \
-    {									      \
-      FILE *asm_out_file = _hide_asm_out_file;				      \
-      unsigned char *p = _hide_p;					      \
-      int thissize = _hide_thissize;					      \
-      int i;								      \
-      fprintf (asm_out_file, "\t.ascii \"");				      \
-									      \
-      for (i = 0; i < thissize; i++)					      \
-	{								      \
-	  register int c = p[i];					      \
-									      \
-	  if (_size_so_far ++ > 50 && i < thissize - 4)			      \
-	    _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \"");      \
-									      \
-	  if (c == '\"' || c == '\\')					      \
-	    putc ('\\', asm_out_file);					      \
-	  if (c >= ' ' && c < 0177)					      \
-	    putc (c, asm_out_file);					      \
-	  else								      \
-	    {								      \
-	      fprintf (asm_out_file, "\\%o", c);			      \
-	      /* After an octal-escape, if a digit follows,		      \
-		 terminate one string constant and start another.	      \
-		 The Vax assembler fails to stop reading the escape	      \
-		 after three digits, so this is the only way we		      \
-		 can get it to parse the data properly.  */		      \
-	      if (i < thissize - 1					      \
-		  && p[i + 1] >= '0' && p[i + 1] <= '9')		      \
-		_size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \"");  \
-	  }								      \
-	}								      \
-      fprintf (asm_out_file, "\"\n");					      \
-    }									      \
-  }									      \
-  while (0)
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)					\
- fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n",		\
-	  (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "",		\
-	  (REGNO) & 31);
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)					\
-  fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n",		\
-	  (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "",		\
-	  (REGNO) & 31);
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff))
-
-/* This is how to output an element of a case-vector that is absolute.
-   (Alpha does not use such vectors, but we must define this macro anyway.)  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \
-	   (VALUE))
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", LOG);
-
-/* This is how to advance the location counter by SIZE bytes.  */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %d\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\t.comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED)	\
-( fputs ("\t.lcomm ", (FILE)),				\
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
-   Used for C++ multiple inheritance.  */
-
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION)	\
-do {									\
-  char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0);		\
-  int reg;								\
-									\
-  /* Mark end of prologue.  */						\
-  output_end_prologue (FILE);						\
-									\
-  /* Rely on the assembler to macro expand a large delta.  */		\
-  reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16;	\
-  fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg);	\
-									\
-  if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0)))	\
-    {									\
-      fprintf (FILE, "\tbr $31,$");					\
-      assemble_name (FILE, fn_name);					\
-      fprintf (FILE, "..ng\n");						\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\tjmp $31,");					\
-      assemble_name (FILE, fn_name);					\
-      fputc ('\n', FILE);						\
-    }									\
-} while (0)
-
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand (FILE, X, CODE)
-
-/* Determine which codes are valid without a following integer.  These must
-   not be alphabetic (the characters are chosen so that
-   PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
-   using ASCII).
-
-   &	Generates fp-rounding mode suffix: nothing for normal, 'c' for
-   	chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
-	mode.  alpha_fprm controls which suffix is generated.
-
-   '	Generates trap-mode suffix for instructions that accept the
-        su suffix only (cmpt et al).
-
-   `    Generates trap-mode suffix for instructions that accept the
-	v and sv suffix.  The only instruction that needs this is cvtql.
-
-   (	Generates trap-mode suffix for instructions that accept the
-	v, sv, and svi suffix.  The only instruction that needs this
-	is cvttq.
-
-   )    Generates trap-mode suffix for instructions that accept the
-	u, su, and sui suffix.  This is the bulk of the IEEE floating
-	point instructions (addt et al).
-
-   +    Generates trap-mode suffix for instructions that accept the
-	sui suffix (cvtqt and cvtqs).
-
-   ,    Generates single precision suffix for floating point
-	instructions (s for IEEE, f for VAX)
-
-   -	Generates double precision suffix for floating point
-	instructions (t for IEEE, g for VAX)
-   */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)				\
-  ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '('	\
-   || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)		\
-{ rtx addr = (ADDR);					\
-  int basereg = 31;					\
-  HOST_WIDE_INT offset = 0;				\
-							\
-  if (GET_CODE (addr) == AND)				\
-    addr = XEXP (addr, 0);				\
-							\
-  if (GET_CODE (addr) == REG)				\
-    basereg = REGNO (addr);				\
-  else if (GET_CODE (addr) == CONST_INT)		\
-    offset = INTVAL (addr);				\
-  else if (GET_CODE (addr) == PLUS			\
-	   && GET_CODE (XEXP (addr, 0)) == REG		\
-	   && GET_CODE (XEXP (addr, 1)) == CONST_INT)	\
-    basereg = REGNO (XEXP (addr, 0)), offset = INTVAL (XEXP (addr, 1)); \
-  else							\
-    abort ();						\
-							\
-  fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, offset);		\
-  fprintf (FILE, "($%d)", basereg);		\
-}
-/* Define the codes that are matched by predicates in alpha.c.  */
-
-#define PREDICATE_CODES 						\
-  {"reg_or_0_operand", {SUBREG, REG, CONST_INT}},			\
-  {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}},			\
-  {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}},			\
-  {"cint8_operand", {CONST_INT}},					\
-  {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}},			\
-  {"add_operand", {SUBREG, REG, CONST_INT}},				\
-  {"sext_add_operand", {SUBREG, REG, CONST_INT}},			\
-  {"const48_operand", {CONST_INT}},					\
-  {"and_operand", {SUBREG, REG, CONST_INT}},				\
-  {"or_operand", {SUBREG, REG, CONST_INT}},				\
-  {"mode_mask_operand", {CONST_INT}},					\
-  {"mul8_operand", {CONST_INT}},					\
-  {"mode_width_operand", {CONST_INT}},					\
-  {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}},			\
-  {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}},		\
-  {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}},	\
-  {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}},		\
-  {"divmod_operator", {DIV, MOD, UDIV, UMOD}},				\
-  {"fp0_operand", {CONST_DOUBLE}},					\
-  {"current_file_function_operand", {SYMBOL_REF}},			\
-  {"call_operand", {REG, SYMBOL_REF}},					\
-  {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE,		\
-		     SYMBOL_REF, CONST, LABEL_REF}},			\
-  {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE,		\
-		    SYMBOL_REF, CONST, LABEL_REF}},			\
-  {"aligned_memory_operand", {MEM}},					\
-  {"unaligned_memory_operand", {MEM}},					\
-  {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}},			\
-  {"any_memory_operand", {MEM}},					\
-  {"hard_fp_register_operand", {SUBREG, REG}},				\
-  {"reg_not_elim_operand", {SUBREG, REG}},
-
-/* Tell collect that the object format is ECOFF.  */
-#define OBJECT_FORMAT_COFF
-#define EXTENDED_COFF
-
-/* If we use NM, pass -g to it so it only lists globals.  */
-#define NM_FLAGS "-pg"
-
-/* Definitions for debugging.  */
-
-#define SDB_DEBUGGING_INFO		/* generate info for mips-tfile */
-#define DBX_DEBUGGING_INFO		/* generate embedded stabs */
-#define MIPS_DEBUGGING_INFO		/* MIPS specific debugging info */
-
-#ifndef PREFERRED_DEBUGGING_TYPE	/* assume SDB_DEBUGGING_INFO */
-#define PREFERRED_DEBUGGING_TYPE  SDB_DEBUG
-#endif
-
-
-/* Correct the offset of automatic variables and arguments.  Note that
-   the Alpha debug format wants all automatic variables and arguments
-   to be in terms of two different offsets from the virtual frame pointer,
-   which is the stack pointer before any adjustment in the function.
-   The offset for the argument pointer is fixed for the native compiler,
-   it is either zero (for the no arguments case) or large enough to hold
-   all argument registers.
-   The offset for the auto pointer is the fourth argument to the .frame
-   directive (local_offset).
-   To stay compatible with the native tools we use the same offsets
-   from the virtual frame pointer and adjust the debugger arg/auto offsets
-   accordingly. These debugger offsets are set up in output_prolog.  */
-
-extern long alpha_arg_offset;
-extern long alpha_auto_offset;
-#define DEBUGGER_AUTO_OFFSET(X) \
-  ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
-#define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
-
-
-#define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE)				\
-  alpha_output_lineno (STREAM, LINE)
-extern void alpha_output_lineno ();
-
-#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME)			\
-  alpha_output_filename (STREAM, NAME)
-extern void alpha_output_filename ();
-
-/* mips-tfile.c limits us to strings of one page.  We must underestimate this
-   number, because the real length runs past this up to the next
-   continuation point.  This is really a dbxout.c bug.  */
-#define DBX_CONTIN_LENGTH 3000
-
-/* By default, turn on GDB extensions.  */
-#define DEFAULT_GDB_EXTENSIONS 1
-
-/* Stabs-in-ECOFF can't handle dbxout_function_end().  */
-#define NO_DBX_FUNCTION_END 1
-
-/* If we are smuggling stabs through the ALPHA ECOFF object
-   format, put a comment in front of the .stab<x> operation so
-   that the ALPHA assembler does not choke.  The mips-tfile program
-   will correctly put the stab into the object file.  */
-
-#define ASM_STABS_OP	((TARGET_GAS) ? ".stabs" : " #.stabs")
-#define ASM_STABN_OP	((TARGET_GAS) ? ".stabn" : " #.stabn")
-#define ASM_STABD_OP	((TARGET_GAS) ? ".stabd" : " #.stabd")
-
-/* Forward references to tags are allowed.  */
-#define SDB_ALLOW_FORWARD_REFERENCES
-
-/* Unknown tags are also allowed.  */
-#define SDB_ALLOW_UNKNOWN_REFERENCES
-
-#define PUT_SDB_DEF(a)					\
-do {							\
-  fprintf (asm_out_file, "\t%s.def\t",			\
-	   (TARGET_GAS) ? "" : "#");			\
-  ASM_OUTPUT_LABELREF (asm_out_file, a); 		\
-  fputc (';', asm_out_file);				\
-} while (0)
-
-#define PUT_SDB_PLAIN_DEF(a)				\
-do {							\
-  fprintf (asm_out_file, "\t%s.def\t.%s;",		\
-	   (TARGET_GAS) ? "" : "#", (a));		\
-} while (0)
-
-#define PUT_SDB_TYPE(a)					\
-do {							\
-  fprintf (asm_out_file, "\t.type\t0x%x;", (a));	\
-} while (0)
-
-/* For block start and end, we create labels, so that
-   later we can figure out where the correct offset is.
-   The normal .ent/.end serve well enough for functions,
-   so those are just commented out.  */
-
-extern int sdb_label_count;		/* block start/end next label # */
-
-#define PUT_SDB_BLOCK_START(LINE)			\
-do {							\
-  fprintf (asm_out_file,				\
-	   "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n",		\
-	   sdb_label_count,				\
-	   (TARGET_GAS) ? "" : "#",			\
-	   sdb_label_count,				\
-	   (LINE));					\
-  sdb_label_count++;					\
-} while (0)
-
-#define PUT_SDB_BLOCK_END(LINE)				\
-do {							\
-  fprintf (asm_out_file,				\
-	   "$Le%d:\n\t%s.bend\t$Le%d\t%d\n",		\
-	   sdb_label_count,				\
-	   (TARGET_GAS) ? "" : "#",			\
-	   sdb_label_count,				\
-	   (LINE));					\
-  sdb_label_count++;					\
-} while (0)
-
-#define PUT_SDB_FUNCTION_START(LINE)
-
-#define PUT_SDB_FUNCTION_END(LINE)
-
-#define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
-
-/* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
-   mips-tdump.c to print them out.
-
-   These must match the corresponding definitions in gdb/mipsread.c.
-   Unfortunately, gcc and gdb do not currently share any directories. */
-
-#define CODE_MASK 0x8F300
-#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
-#define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
-#define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
-
-/* Override some mips-tfile definitions.  */
-
-#define SHASH_SIZE 511
-#define THASH_SIZE 55
-
-/* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints.  */
-
-#define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
-
-/* The linker will stick __main into the .init section.  */
-#define HAS_INIT_SECTION
-#define LD_INIT_SWITCH "-init"
-#define LD_FINI_SWITCH "-fini"
-
-/* The system headers under Alpha systems are generally C++-aware.  */
-#define NO_IMPLICIT_EXTERN_C
-
-/* Prototypes for alpha.c functions used in the md file & elsewhere.  */
-extern struct rtx_def *get_unaligned_address ();
-extern void alpha_write_verstamp ();
-extern void alpha_reorg ();
-extern int check_float_value ();
-extern int direct_return ();
-extern int const48_operand ();
-extern int add_operand ();
-extern int and_operand ();
-extern int unaligned_memory_operand ();
-extern int zap_mask ();
-extern int current_file_function_operand ();
-extern int alpha_sa_size ();
-extern int alpha_adjust_cost ();
-extern void print_operand ();
-extern int reg_or_0_operand ();
-extern int reg_or_8bit_operand ();
-extern int mul8_operand ();
-extern int reg_or_6bit_operand ();
-extern int alpha_comparison_operator ();
-extern int alpha_swapped_comparison_operator ();
-extern int sext_add_operand ();
-extern int cint8_operand ();
-extern int mode_mask_operand ();
-extern int or_operand ();
-extern int mode_width_operand ();
-extern int reg_or_fp0_operand ();
-extern int signed_comparison_operator ();
-extern int fp0_operand ();
-extern int some_operand ();
-extern int input_operand ();
-extern int divmod_operator ();
-extern int call_operand ();
-extern int reg_or_cint_operand ();
-extern int hard_fp_register_operand ();
-extern int reg_not_elim_operand ();
-extern void alpha_set_memflags ();
-extern int aligned_memory_operand ();
-extern void get_aligned_mem ();
-extern void alpha_expand_unaligned_load ();
-extern void alpha_expand_unaligned_store ();
-extern int alpha_expand_block_move ();
-extern int alpha_expand_block_clear ();
-extern void alpha_expand_prologue ();
-extern void alpha_expand_epilogue ();
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
deleted file mode 100755
index e0ff2c5..0000000
--- a/gcc/config/alpha/alpha.md
+++ /dev/null
@@ -1,5313 +0,0 @@
-;; Machine description for DEC Alpha for GNU C compiler
-;; Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
-;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; Uses of UNSPEC in this file:
-;;
-;;	0	arg_home
-;;	1	cttz
-;;	2	insxh
-;;	3	mskxh
-;;	4	cvtlq
-;;	5	cvtql
-;;	
-;; UNSPEC_VOLATILE:
-;;
-;;	0	imb
-;;	1	blockage
-;;	2	builtin_setjmp_receiver
-;;	3	builtin_longjmp
-;;	4	trapb
-;;	5	prologue_stack_probe_loop
-;;	6	realign
-;;	7	exception_receiver
-
-;; Processor type -- this attribute must exactly match the processor_type
-;; enumeration in alpha.h.
-
-(define_attr "cpu" "ev4,ev5,ev6"
-  (const (symbol_ref "alpha_cpu")))
-
-;; Define an insn type attribute.  This is used in function unit delay
-;; computations, among other purposes.  For the most part, we use the names
-;; defined in the EV4 documentation, but add a few that we have to know about
-;; separately.
-
-(define_attr "type"
-  "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
-  (const_string "iadd"))
-
-;; Describe a user's asm statement.
-(define_asm_attributes
-  [(set_attr "type" "multi")])
-
-;; Define the operand size an insn operates on.  Used primarily by mul
-;; and div operations that have size dependant timings.
-
-(define_attr "opsize" "si,di,udi" (const_string "di"))
-
-;; The TRAP_TYPE attribute marks instructions that may generate traps
-;; (which are imprecise and may need a trapb if software completion
-;; is desired).
-
-(define_attr "trap" "no,yes" (const_string "no"))
-
-;; The length of an instruction sequence in bytes.
-
-(define_attr "length" "" (const_int 4))
-
-;; On EV4 there are two classes of resources to consider: resources needed
-;; to issue, and resources needed to execute.  IBUS[01] are in the first
-;; category.  ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
-;; (There are a few other register-like resources, but ...)
-
-; First, describe all of the issue constraints with single cycle delays.
-; All insns need a bus, but all except loads require one or the other.
-(define_function_unit "ev4_ibus0" 1 0
-  (and (eq_attr "cpu" "ev4")
-       (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
-  1 1)
-
-(define_function_unit "ev4_ibus1" 1 0
-  (and (eq_attr "cpu" "ev4")
-       (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
-  1 1)
-
-; Memory delivers its result in three cycles.  Actually return one and
-; take care of this in adjust_cost, since we want to handle user-defined
-; memory latencies.
-(define_function_unit "ev4_abox" 1 0
-  (and (eq_attr "cpu" "ev4")
-       (eq_attr "type" "ild,fld,ldsym,ist,fst"))
-  1 1)
-
-; Branches have no delay cost, but do tie up the unit for two cycles.
-(define_function_unit "ev4_bbox" 1 1
-  (and (eq_attr "cpu" "ev4")
-       (eq_attr "type" "ibr,fbr,jsr"))
-  2 2)
-
-; Arithmetic insns are normally have their results available after
-; two cycles.  There are a number of exceptions.  They are encoded in
-; ADJUST_COST.  Some of the other insns have similar exceptions.
-(define_function_unit "ev4_ebox" 1 0
-  (and (eq_attr "cpu" "ev4")
-       (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
-  2 1)
-
-(define_function_unit "imul" 1 0
-  (and (eq_attr "cpu" "ev4")
-       (and (eq_attr "type" "imul")
-	    (eq_attr "opsize" "si")))
-  21 19)
-
-(define_function_unit "imul" 1 0
-  (and (eq_attr "cpu" "ev4")
-       (and (eq_attr "type" "imul")
-	    (eq_attr "opsize" "!si")))
-  23 21)
-
-(define_function_unit "ev4_fbox" 1 0
-  (and (eq_attr "cpu" "ev4")
-       (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
-  6 1)
-
-(define_function_unit "fdiv" 1 0
-  (and (eq_attr "cpu" "ev4")
-       (and (eq_attr "type" "fdiv")
-	    (eq_attr "opsize" "si")))
-  34 30)
-
-(define_function_unit "fdiv" 1 0
-  (and (eq_attr "cpu" "ev4")
-       (and (eq_attr "type" "fdiv")
-	    (eq_attr "opsize" "di")))
-  63 59)
-
-;; EV5 scheduling.  EV5 can issue 4 insns per clock.
-;;
-;; EV5 has two asymetric integer units.  Model this with E0 & E1 along
-;; with the combined resource EBOX.
-
-(define_function_unit "ev5_ebox" 2 0
-  (and (eq_attr "cpu" "ev5")
-       (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
-  1 1)
-
-; Memory takes at least 2 clocks.  Return one from here and fix up with
-; user-defined latencies in adjust_cost.
-; ??? How to: "An instruction of class LD cannot be issued in the _second_
-; cycle after an instruction of class ST is issued."
-(define_function_unit "ev5_ebox" 2 0
-  (and (eq_attr "cpu" "ev5")
-       (eq_attr "type" "ild,fld,ldsym"))
-  1 1)
-
-; Stores, shifts, multiplies can only issue to E0
-(define_function_unit "ev5_e0" 1 0
-  (and (eq_attr "cpu" "ev5")
-       (eq_attr "type" "ist,fst,shift,imul"))
-  1 1)
-
-; Motion video insns also issue only to E0, and take two ticks.
-(define_function_unit "ev5_e0" 1 0
-  (and (eq_attr "cpu" "ev5")
-       (eq_attr "type" "mvi"))
-  2 1)
-
-; Conditional moves always take 2 ticks.
-(define_function_unit "ev5_ebox" 2 0
-  (and (eq_attr "cpu" "ev5")
-       (eq_attr "type" "icmov"))
-  2 1)
-
-; Branches can only issue to E1
-(define_function_unit "ev5_e1" 1 0
-  (and (eq_attr "cpu" "ev5")
-       (eq_attr "type" "ibr,jsr"))
-  1 1)
-
-; Multiplies also use the integer multiplier.
-; ??? How to: "No instruction can be issued to pipe E0 exactly two
-; cycles before an integer multiplication completes."
-(define_function_unit "imul" 1 0
-  (and (eq_attr "cpu" "ev5")
-       (and (eq_attr "type" "imul")
-	    (eq_attr "opsize" "si")))
-  8 4)
-
-(define_function_unit "imul" 1 0
-  (and (eq_attr "cpu" "ev5")
-       (and (eq_attr "type" "imul")
-	    (eq_attr "opsize" "di")))
-  12 8)
-
-(define_function_unit "imul" 1 0
-  (and (eq_attr "cpu" "ev5")
-       (and (eq_attr "type" "imul")
-	    (eq_attr "opsize" "udi")))
-  14 8)
-
-;; Similarly for the FPU we have two asymetric units.  But fcpys can issue
-;; on either so we have to play the game again.
-
-(define_function_unit "ev5_fbox" 2 0
-  (and (eq_attr "cpu" "ev5")
-       (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
-  4 1)
-  
-(define_function_unit "ev5_fm" 1 0
-  (and (eq_attr "cpu" "ev5")
-       (eq_attr "type" "fmul"))
-  4 1)
-
-; Add and cmov as you would expect; fbr never produces a result;
-; fdiv issues through fa to the divider, 
-(define_function_unit "ev5_fa" 1 0
-  (and (eq_attr "cpu" "ev5")
-       (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
-  4 1)
-
-; ??? How to: "No instruction can be issued to pipe FA exactly five
-; cycles before a floating point divide completes."
-(define_function_unit "fdiv" 1 0
-  (and (eq_attr "cpu" "ev5")
-       (and (eq_attr "type" "fdiv")
-	    (eq_attr "opsize" "si")))
-  15 15)				; 15 to 31 data dependant
-
-(define_function_unit "fdiv" 1 0
-  (and (eq_attr "cpu" "ev5")
-       (and (eq_attr "type" "fdiv")
-	    (eq_attr "opsize" "di")))
-  22 22)				; 22 to 60 data dependant
-
-;; EV6 scheduling.  EV6 can issue 4 insns per clock.
-;;
-;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
-;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
-
-;; Conditional moves decompose into two independant primitives, each 
-;; taking one cycle.  Since ev6 is out-of-order, we can't see anything
-;; but two cycles.
-(define_function_unit "ev6_ebox" 4 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "icmov"))
-  2 1)
-
-(define_function_unit "ev6_ebox" 4 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
-  1 1)
-
-;; Integer loads take at least 3 clocks, and only issue to lower units.
-;; Return one from here and fix up with user-defined latencies in adjust_cost.
-(define_function_unit "ev6_l" 2 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "ild,ldsym,ist,fst"))
-  1 1)
-
-;; FP loads take at least 4 clocks.  Return two from here...
-(define_function_unit "ev6_l" 2 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "fld"))
-  2 1)
-
-;; Motion video insns also issue only to U0, and take three ticks.
-(define_function_unit "ev6_u0" 1 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "mvi"))
-  3 1)
-
-(define_function_unit "ev6_u" 2 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "mvi"))
-  3 1)
-
-;; Shifts issue to either upper pipe.
-(define_function_unit "ev6_u" 2 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "shift"))
-  1 1)
-
-;; Multiplies issue only to U1, and all take 7 ticks.
-;; Rather than create a new function unit just for U1, reuse IMUL
-(define_function_unit "imul" 1 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "imul"))
-  7 1)
-
-(define_function_unit "ev6_u" 2 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "imul"))
-  7 1)
-
-;; Branches issue to either upper pipe
-(define_function_unit "ev6_u" 2 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "ibr"))
-  3 1)
-
-;; Calls only issue to L0.
-(define_function_unit "ev6_l0" 1 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "jsr"))
-  1 1)
-
-(define_function_unit "ev6_l" 2 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "jsr"))
-  1 1)
-
-;; Ftoi/itof only issue to lower pipes
-(define_function_unit "ev6_l" 2 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "ftoi"))
-  3 1)
-
-(define_function_unit "ev6_l" 2 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "itof"))
-  4 1)
-
-;; For the FPU we are very similar to EV5, except there's no insn that
-;; can issue to fm & fa, so we get to leave that out.
-  
-(define_function_unit "ev6_fm" 1 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "fmul"))
-  4 1)
-
-(define_function_unit "ev6_fa" 1 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
-  4 1)
-
-(define_function_unit "ev6_fa" 1 0
-  (and (eq_attr "cpu" "ev6")
-       (eq_attr "type" "fcmov"))
-  8 1)
-
-(define_function_unit "fdiv" 1 0
-  (and (eq_attr "cpu" "ev6")
-       (and (eq_attr "type" "fdiv")
-	    (eq_attr "opsize" "si")))
-  12 10)
-
-(define_function_unit "fdiv" 1 0
-  (and (eq_attr "cpu" "ev6")
-       (and (eq_attr "type" "fdiv")
-	    (eq_attr "opsize" "di")))
-  15 13)
-
-(define_function_unit "fsqrt" 1 0
-  (and (eq_attr "cpu" "ev6")
-       (and (eq_attr "type" "fsqrt")
-	    (eq_attr "opsize" "si")))
-  16 14)
-
-(define_function_unit "fsqrt" 1 0
-  (and (eq_attr "cpu" "ev6")
-       (and (eq_attr "type" "fsqrt")
-	    (eq_attr "opsize" "di")))
-  32 30)
-
-; ??? The FPU communicates with memory and the integer register file
-; via two fp store units.  We need a slot in the fst immediately, and
-; a slot in LOW after the operand data is ready.  At which point the
-; data may be moved either to the store queue or the integer register
-; file and the insn retired.
-
-
-;; First define the arithmetic insns.  Note that the 32-bit forms also
-;; sign-extend.
-
-;; Handle 32-64 bit extension from memory to a floating point register
-;; specially, since this ocurrs frequently in int->double conversions.
-;; This is done with a define_split after reload converting the plain
-;; sign-extension into a load+unspec, which of course results in lds+cvtlq.
-;;
-;; Note that while we must retain the =f case in the insn for reload's
-;; benefit, it should be eliminated after reload, so we should never emit
-;; code for that case.  But we don't reject the possibility.
-
-(define_insn "extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=r,r,?f")
-	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
-  ""
-  "@
-   addl %1,$31,%0
-   ldl %0,%1
-   lds %0,%1\;cvtlq %0,%0"
-  [(set_attr "type" "iadd,ild,fld")
-   (set_attr "length" "*,*,8")])
-
-;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
-(define_split
-  [(set (match_operand:DI 0 "hard_fp_register_operand" "")
-	(sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (unspec:DI [(match_dup 2)] 4))]
-  "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-	(unspec:DI [(match_operand:SI 1 "register_operand" "f")] 4))]
-  ""
-  "cvtlq %1,%0"
-  [(set_attr "type" "fadd")])
-
-;; Do addsi3 the way expand_binop would do if we didn't have one.  This
-;; generates better code.  We have the anonymous addsi3 pattern below in
-;; case combine wants to make it.
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
-		 (match_operand:SI 2 "add_operand" "")))]
-  ""
-  "
-{
-  if (optimize)
-    {
-      rtx op1 = gen_lowpart (DImode, operands[1]);
-      rtx op2 = gen_lowpart (DImode, operands[2]);
-
-      if (! cse_not_expected)
-        {
-          rtx tmp = gen_reg_rtx (DImode);
-          emit_insn (gen_adddi3 (tmp, op1, op2));
-          emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
-        }
-      else
-        emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
-		 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
-  ""
-  "@
-   addl %r1,%2,%0
-   subl %r1,%n2,%0
-   lda %0,%2(%r1)
-   ldah %0,%h2(%r1)")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "const_int_operand" "")))]
-  "! add_operand (operands[2], SImode)"
-  [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
-   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[2]);
-  HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
-  HOST_WIDE_INT rest = val - low;
-
-  operands[3] = GEN_INT (rest);
-  operands[4] = GEN_INT (low);
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(sign_extend:DI
-	 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
-		  (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
-  ""
-  "@
-   addl %r1,%2,%0
-   subl %r1,%n2,%0")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI
-	 (plus:SI (match_operand:SI 1 "register_operand" "")
-		  (match_operand:SI 2 "const_int_operand" ""))))
-   (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
-  "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
-   && INTVAL (operands[2]) % 4 == 0"
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
-							(match_dup 5))
-					       (match_dup 1))))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
-  int mult = 4;
-
-  if (val % 2 == 0)
-    val /= 2, mult = 8;
-
-  operands[4] = GEN_INT (val);
-  operands[5] = GEN_INT (mult);
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI
-	 (plus:SI (match_operator:SI 1 "comparison_operator"
-				     [(match_operand 2 "" "")
-				      (match_operand 3 "" "")])
-		  (match_operand:SI 4 "add_operand" ""))))
-   (clobber (match_operand:DI 5 "register_operand" ""))]
-  ""
-  [(set (match_dup 5) (match_dup 6))
-   (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
-  "
-{
-  operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
-				operands[2], operands[3]);
-  operands[7] = gen_lowpart (SImode, operands[5]);
-}")
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
-	(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
-		 (match_operand:DI 2 "add_operand" "rI,O,K,L")))]
-  ""
-  "@
-   addq %r1,%2,%0
-   subq %r1,%n2,%0
-   lda %0,%2(%r1)
-   ldah %0,%h2(%r1)")
-
-;; Don't do this if we are adjusting SP since we don't want to do
-;; it in two steps. 
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(plus:DI (match_operand:DI 1 "register_operand" "")
-		 (match_operand:DI 2 "const_int_operand" "")))]
-  "! add_operand (operands[2], DImode)
-   && REGNO (operands[0]) != STACK_POINTER_REGNUM"
-  [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
-   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[2]);
-  HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
-  HOST_WIDE_INT rest = val - low;
-
-  operands[3] = GEN_INT (rest);
-  operands[4] = GEN_INT (low);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
-			  (match_operand:SI 2 "const48_operand" "I,I"))
-		 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
-  ""
-  "@
-   s%2addl %1,%3,%0
-   s%2subl %1,%n3,%0")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(sign_extend:DI
-	 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
-			   (match_operand:SI 2 "const48_operand" "I,I"))
-		  (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
-  ""
-  "@
-   s%2addl %1,%3,%0
-   s%2subl %1,%n3,%0")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI
-	 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
-					      [(match_operand 2 "" "")
-					       (match_operand 3 "" "")])
-			   (match_operand:SI 4 "const48_operand" ""))
-		  (match_operand:SI 5 "add_operand" ""))))
-   (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
-  ""
-  [(set (match_dup 6) (match_dup 7))
-   (set (match_dup 0)
-	(sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
-				 (match_dup 5))))]
-  "
-{
-  operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
-				operands[2], operands[3]);
-  operands[8] = gen_lowpart (SImode, operands[6]);
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
-			  (match_operand:DI 2 "const48_operand" "I,I"))
-		 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
-  ""
-  "@
-   s%2addq %1,%3,%0
-   s%2subq %1,%n3,%0")
-
-;; These variants of the above insns can occur if the third operand
-;; is the frame pointer.  This is a kludge, but there doesn't
-;; seem to be a way around it.  Only recognize them while reloading.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "some_operand" "=&r")
-	(plus:DI (plus:DI (match_operand:DI 1 "some_operand" "r")
-			  (match_operand:DI 2 "some_operand" "r"))
-		 (match_operand:DI 3 "some_operand" "rIOKL")))]
-  "reload_in_progress"
-  "#")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
-			  (match_operand:DI 2 "register_operand" ""))
-		 (match_operand:DI 3 "add_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
-  "")
-					   
-(define_insn ""
-  [(set (match_operand:SI 0 "some_operand" "=&r")
-	(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ")
-				   (match_operand:SI 2 "const48_operand" "I"))
-			  (match_operand:SI 3 "some_operand" "r"))
-		 (match_operand:SI 4 "some_operand" "rIOKL")))]
-  "reload_in_progress"
-  "#")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "r")
-	(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
-				   (match_operand:SI 2 "const48_operand" ""))
-			  (match_operand:SI 3 "register_operand" ""))
-		 (match_operand:SI 4 "add_operand" "rIOKL")))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "some_operand" "=&r")
-	(sign_extend:DI
-	 (plus:SI (plus:SI
-		   (mult:SI (match_operand:SI 1 "some_operand" "rJ")
-			    (match_operand:SI 2 "const48_operand" "I"))
-		   (match_operand:SI 3 "some_operand" "r"))
-		  (match_operand:SI 4 "some_operand" "rIOKL"))))]
-  "reload_in_progress"
-  "#")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI
-	 (plus:SI (plus:SI
-		   (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
-			    (match_operand:SI 2 "const48_operand" ""))
-		   (match_operand:SI 3 "register_operand" ""))
-		  (match_operand:SI 4 "add_operand" ""))))]
-  "reload_completed"
-  [(set (match_dup 5)
-	(plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
-  "operands[5] = gen_lowpart (SImode, operands[0]);")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "some_operand" "=&r")
-	(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ")
-				   (match_operand:DI 2 "const48_operand" "I"))
-			  (match_operand:DI 3 "some_operand" "r"))
-		 (match_operand:DI 4 "some_operand" "rIOKL")))]
-  "reload_in_progress"
-  "#")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "=")
-	(plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
-				   (match_operand:DI 2 "const48_operand" ""))
-			  (match_operand:DI 3 "register_operand" ""))
-		 (match_operand:DI 4 "add_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
-  "")
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
-  ""
-  "subl $31,%1,%0")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI (neg:SI
-			 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
-  ""
-  "subl $31,%1,%0")
-
-(define_insn "negdi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
-  ""
-  "subq $31,%1,%0")
-
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
-		  (match_operand:SI 2 "reg_or_8bit_operand" "")))]
-  ""
-  "
-{
-  if (optimize)
-    {
-      rtx op1 = gen_lowpart (DImode, operands[1]);
-      rtx op2 = gen_lowpart (DImode, operands[2]);
-
-      if (! cse_not_expected)
-        {
-          rtx tmp = gen_reg_rtx (DImode);
-          emit_insn (gen_subdi3 (tmp, op1, op2));
-          emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
-        }
-      else
-        emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
-      DONE;
-    }
-} ")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-		  (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
-  ""
-  "subl %r1,%2,%0")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-				  (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
-  ""
-  "subl %r1,%2,%0")
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		  (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
-  ""
-  "subq %r1,%2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
-			   (match_operand:SI 2 "const48_operand" "I"))
-		  (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
-  ""
-  "s%2subl %1,%3,%0")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI
-	 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
-			    (match_operand:SI 2 "const48_operand" "I"))
-		   (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
-  ""
-  "s%2subl %1,%3,%0")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
-			   (match_operand:DI 2 "const48_operand" "I"))
-		  (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
-  ""
-  "s%2subq %1,%3,%0")
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
-		 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
-  ""
-  "mull %r1,%2,%0"
-  [(set_attr "type" "imul")
-   (set_attr "opsize" "si")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI
-	  (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
-		   (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
-  ""
-  "mull %r1,%2,%0"
-  [(set_attr "type" "imul")
-   (set_attr "opsize" "si")])
-
-(define_insn "muldi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
-		 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
-  ""
-  "mulq %r1,%2,%0"
-  [(set_attr "type" "imul")])
-
-(define_insn "umuldi3_highpart"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(truncate:DI
-	 (lshiftrt:TI
-	  (mult:TI (zero_extend:TI
-		     (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
-		   (zero_extend:TI
-		     (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
-	  (const_int 64))))]
-  ""
-  "umulh %r1,%2,%0"
-  [(set_attr "type" "imul")
-   (set_attr "opsize" "udi")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(truncate:DI
-	 (lshiftrt:TI
-	  (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
-		   (match_operand:TI 2 "cint8_operand" "I"))
-	  (const_int 64))))]
-  ""
-  "umulh %1,%2,%0"
-  [(set_attr "type" "imul")
-   (set_attr "opsize" "udi")])
-
-;; The divide and remainder operations always take their inputs from
-;; r24 and r25, put their output in r27, and clobber r23 and r28.
-
-;; ??? Force sign-extension here because some versions of OSF/1 don't
-;; do the right thing if the inputs are not properly sign-extended.
-;; But Linux, for instance, does not have this problem.  Is it worth
-;; the complication here to eliminate the sign extension?
-
-(define_expand "divsi3"
-  [(set (reg:DI 24)
-	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
-   (set (reg:DI 25)
-	(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
-   (parallel [(set (reg:DI 27)
-		   (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
-	      (clobber (reg:DI 23))
-	      (clobber (reg:DI 28))])
-   (set (match_operand:SI 0 "general_operand" "")
-	(subreg:SI (reg:DI 27) 0))]
-  "!TARGET_OPEN_VMS"
-  "")
-
-(define_expand "udivsi3"
-  [(set (reg:DI 24)
-	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
-   (set (reg:DI 25)
-	(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
-   (parallel [(set (reg:DI 27)
-		   (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
-	      (clobber (reg:DI 23))
-	      (clobber (reg:DI 28))])
-   (set (match_operand:SI 0 "general_operand" "")
-	(subreg:SI (reg:DI 27) 0))]
-  "!TARGET_OPEN_VMS"
-  "")
-
-(define_expand "modsi3"
-  [(set (reg:DI 24)
-	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
-   (set (reg:DI 25)
-	(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
-   (parallel [(set (reg:DI 27)
-		   (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
-	      (clobber (reg:DI 23))
-	      (clobber (reg:DI 28))])
-   (set (match_operand:SI 0 "general_operand" "")
-	(subreg:SI (reg:DI 27) 0))]
-  "!TARGET_OPEN_VMS"
-  "")
-
-(define_expand "umodsi3"
-  [(set (reg:DI 24)
-	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
-   (set (reg:DI 25)
-	(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
-   (parallel [(set (reg:DI 27)
-		   (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
-	      (clobber (reg:DI 23))
-	      (clobber (reg:DI 28))])
-   (set (match_operand:SI 0 "general_operand" "")
-	(subreg:SI (reg:DI 27) 0))]
-  "!TARGET_OPEN_VMS"
-  "")
-
-(define_expand "divdi3"
-  [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
-   (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
-   (parallel [(set (reg:DI 27)
-		   (div:DI (reg:DI 24)
-			   (reg:DI 25)))
-	      (clobber (reg:DI 23))
-	      (clobber (reg:DI 28))])
-   (set (match_operand:DI 0 "general_operand" "")
-	(reg:DI 27))]
-  "!TARGET_OPEN_VMS"
-  "")
-
-(define_expand "udivdi3"
-  [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
-   (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
-   (parallel [(set (reg:DI 27)
-		   (udiv:DI (reg:DI 24)
-			    (reg:DI 25)))
-	      (clobber (reg:DI 23))
-	      (clobber (reg:DI 28))])
-   (set (match_operand:DI 0 "general_operand" "")
-	(reg:DI 27))]
-  "!TARGET_OPEN_VMS"
-  "")
-
-(define_expand "moddi3"
-  [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
-   (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
-   (parallel [(set (reg:DI 27)
-		   (mod:DI (reg:DI 24)
-			   (reg:DI 25)))
-	      (clobber (reg:DI 23))
-	      (clobber (reg:DI 28))])
-   (set (match_operand:DI 0 "general_operand" "")
-	(reg:DI 27))]
-  "!TARGET_OPEN_VMS"
-  "")
-
-(define_expand "umoddi3"
-  [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
-   (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
-   (parallel [(set (reg:DI 27)
-		   (umod:DI (reg:DI 24)
-			    (reg:DI 25)))
-	      (clobber (reg:DI 23))
-	      (clobber (reg:DI 28))])
-   (set (match_operand:DI 0 "general_operand" "")
-	(reg:DI 27))]
-  "!TARGET_OPEN_VMS"
-  "")
-
-;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
-;; expanded by the assembler.
-(define_insn ""
-  [(set (reg:DI 27)
-	(sign_extend:DI (match_operator:SI 1 "divmod_operator"
-			[(reg:DI 24) (reg:DI 25)])))
-   (clobber (reg:DI 23))
-   (clobber (reg:DI 28))]
-  "!TARGET_OPEN_VMS"
-  "%E1 $24,$25,$27"
-  [(set_attr "type" "jsr")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (reg:DI 27)
-	(match_operator:DI 1 "divmod_operator"
-			[(reg:DI 24) (reg:DI 25)]))
-   (clobber (reg:DI 23))
-   (clobber (reg:DI 28))]
-  "!TARGET_OPEN_VMS"
-  "%E1 $24,$25,$27"
-  [(set_attr "type" "jsr")
-   (set_attr "length" "8")])
-
-;; Next are the basic logical operations.  These only exist in DImode.
-
-(define_insn "anddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-	(and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
-		(match_operand:DI 2 "and_operand" "rI,N,MH")))]
-  ""
-  "@
-   and %r1,%2,%0
-   bic %r1,%N2,%0
-   zapnot %r1,%m2,%0"
-  [(set_attr "type" "ilog,ilog,shift")])
-
-;; There are times when we can split an AND into two AND insns.  This occurs
-;; when we can first clear any bytes and then clear anything else.  For
-;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
-;; Only do this when running on 64-bit host since the computations are
-;; too messy otherwise.
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(and:DI (match_operand:DI 1 "register_operand" "")
-		(match_operand:DI 2 "const_int_operand" "")))]
-  "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
-  [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
-   (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
-  "
-{
-  unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
-  unsigned HOST_WIDE_INT mask2 = mask1;
-  int i;
-
-  /* For each byte that isn't all zeros, make it all ones.  */
-  for (i = 0; i < 64; i += 8)
-    if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
-      mask1 |= (HOST_WIDE_INT) 0xff << i;
-
-  /* Now turn on any bits we've just turned off.  */
-  mask2 |= ~ mask1;
-
-  operands[3] = GEN_INT (mask1);
-  operands[4] = GEN_INT (mask2);
-}")
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
-  ""
-  "and %1,0xff,%0"
-  [(set_attr "type" "ilog")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
-  "TARGET_BWX"
-  "@
-   and %1,0xff,%0
-   ldbu %0,%1"
-  [(set_attr "type" "ilog,ild")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
-  "! TARGET_BWX"
-  "and %1,0xff,%0"
-  [(set_attr "type" "ilog")])
-
-(define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
-  "TARGET_BWX"
-  "@
-   and %1,0xff,%0
-   ldbu %0,%1"
-  [(set_attr "type" "ilog,ild")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
-  "! TARGET_BWX"
-  "and %1,0xff,%0"
-  [(set_attr "type" "ilog")])
-  
-(define_expand "zero_extendqidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
-  ""
-  "")
-  
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
-  "TARGET_BWX"
-  "@
-   zapnot %1,3,%0
-   ldwu %0,%1"
-  [(set_attr "type" "shift,ild")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
-  "! TARGET_BWX"
-  "zapnot %1,3,%0"
-  [(set_attr "type" "shift")])
-
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
-  "TARGET_BWX"
-  "@
-   zapnot %1,3,%0
-   ldwu %0,%1"
-  [(set_attr "type" "shift,ild")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
-  ""
-  "zapnot %1,3,%0"
-  [(set_attr "type" "shift")])
-
-(define_expand "zero_extendhidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn "zero_extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "zapnot %1,15,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn  ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
-		(match_operand:DI 2 "reg_or_0_operand" "rJ")))]
-  ""
-  "bic %r2,%1,%0"
-  [(set_attr "type" "ilog")])
-
-(define_insn "iordi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
-		(match_operand:DI 2 "or_operand" "rI,N")))]
-  ""
-  "@
-   bis %r1,%2,%0
-   ornot %r1,%N2,%0"
-  [(set_attr "type" "ilog")])
-
-(define_insn "one_cmpldi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
-  ""
-  "ornot $31,%1,%0"
-  [(set_attr "type" "ilog")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
-		(match_operand:DI 2 "reg_or_0_operand" "rJ")))]
-  ""
-  "ornot %r2,%1,%0"
-  [(set_attr "type" "ilog")])
-
-(define_insn "xordi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
-		(match_operand:DI 2 "or_operand" "rI,N")))]
-  ""
-  "@
-   xor %r1,%2,%0
-   eqv %r1,%N2,%0"
-  [(set_attr "type" "ilog")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
-			(match_operand:DI 2 "register_operand" "rI"))))]
-  ""
-  "eqv %r1,%2,%0"
-  [(set_attr "type" "ilog")])
-
-;; Handle the FFS insn if we support CIX. 
-
-(define_expand "ffsdi2"
-  [(set (match_dup 2)
-	(unspec [(match_operand:DI 1 "register_operand" "")] 1))
-   (set (match_dup 3)
-	(plus:DI (match_dup 2) (const_int 1)))
-   (set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI (eq (match_dup 1) (const_int 0))
-			 (const_int 0) (match_dup 3)))]
-  "TARGET_CIX"
-  "
-{
-  operands[2] = gen_reg_rtx (DImode);
-  operands[3] = gen_reg_rtx (DImode);
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(unspec [(match_operand:DI 1 "register_operand" "r")] 1))]
-  "TARGET_CIX"
-  "cttz %1,%0"
-  ; ev6 calls all mvi and cttz/ctlz/popc class imisc, so just 
-  ; reuse the existing type name.
-  [(set_attr "type" "mvi")])
-
-;; Next come the shifts and the various extract and insert operations.
-
-(define_insn "ashldi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
-		   (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (operands[2] == const1_rtx)
-	return \"addq %r1,%r1,%0\";
-      else
-	return \"s%P2addq %r1,0,%0\";
-    case 1:
-      return \"sll %r1,%2,%0\";
-    default:
-      abort();
-    }
-}"
-  [(set_attr "type" "iadd,shift")])
-
-;; ??? The following pattern is made by combine, but earlier phases
-;; (specifically flow) can't handle it.  This occurs in jump.c.  Deal
-;; with this in a better way at some point.
-;;(define_insn ""
-;;  [(set (match_operand:DI 0 "register_operand" "=r")
-;;	(sign_extend:DI
-;;	 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-;;			       (match_operand:DI 2 "const_int_operand" "P"))
-;;		    0)))]
-;;  "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
-;;  "*
-;;{
-;;  if (operands[2] == const1_rtx)
-;;    return \"addl %r1,%r1,%0\";
-;;  else
-;;    return \"s%P2addl %r1,0,%0\";
-;; }"
-;;  [(set_attr "type" "iadd")])
-			  
-(define_insn "lshrdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		     (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
-  ""
-  "srl %r1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "ashrdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		     (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
-  ""
-  "sra %r1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_expand "extendqihi2"
-  [(set (match_dup 2)
-	(ashift:DI (match_operand:QI 1 "some_operand" "")
-		   (const_int 56)))
-   (set (match_operand:HI 0 "register_operand" "")
-	(ashiftrt:DI (match_dup 2)
-		     (const_int 56)))]
-  ""
-  "
-{
-  if (TARGET_BWX)
-    {
-      emit_insn (gen_extendqihi2x (operands[0],
-				   force_reg (QImode, operands[1])));
-      DONE;
-    }
- 
- /* If we have an unaligned MEM, extend to DImode (which we do
-     specially) and then copy to the result.  */
-  if (unaligned_memory_operand (operands[1], HImode))
-    {
-      rtx temp = gen_reg_rtx (DImode);
-
-      emit_insn (gen_extendqidi2 (temp, operands[1]));
-      emit_move_insn (operands[0], gen_lowpart (HImode, temp));
-      DONE;
-    }
-
-  operands[0] = gen_lowpart (DImode, operands[0]);
-  operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
-  operands[2] = gen_reg_rtx (DImode);
-}")
-
-(define_insn "extendqidi2x"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
-  "TARGET_BWX"
-  "sextb %1,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "extendhidi2x"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
-  "TARGET_BWX"
-  "sextw %1,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "extendqisi2x"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
-  "TARGET_BWX"
-  "sextb %1,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "extendhisi2x"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
-  "TARGET_BWX"
-  "sextw %1,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "extendqihi2x"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
-  "TARGET_BWX"
-  "sextb %1,%0"
-  [(set_attr "type" "shift")])
-
-(define_expand "extendqisi2"
-  [(set (match_dup 2)
-	(ashift:DI (match_operand:QI 1 "some_operand" "")
-		   (const_int 56)))
-   (set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:DI (match_dup 2)
-		     (const_int 56)))]
-  ""
-  "
-{
-  if (TARGET_BWX)
-    {
-      emit_insn (gen_extendqisi2x (operands[0],
-				   force_reg (QImode, operands[1])));
-      DONE;
-    }
-
-  /* If we have an unaligned MEM, extend to a DImode form of
-     the result (which we do specially).  */
-  if (unaligned_memory_operand (operands[1], QImode))
-    {
-      rtx temp = gen_reg_rtx (DImode);
-
-      emit_insn (gen_extendqidi2 (temp, operands[1]));
-      emit_move_insn (operands[0], gen_lowpart (SImode, temp));
-      DONE;
-    }
-
-  operands[0] = gen_lowpart (DImode, operands[0]);
-  operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
-  operands[2] = gen_reg_rtx (DImode);
-}")
-
-(define_expand "extendqidi2"
-  [(set (match_dup 2)
-	(ashift:DI (match_operand:QI 1 "some_operand" "")
-		   (const_int 56)))
-   (set (match_operand:DI 0 "register_operand" "")
-	(ashiftrt:DI (match_dup 2)
-		     (const_int 56)))]
-  ""
-  "
-{
-  if (TARGET_BWX)
-    {
-      emit_insn (gen_extendqidi2x (operands[0],
-				   force_reg (QImode, operands[1])));
-      DONE;
-    }
-
-  if (unaligned_memory_operand (operands[1], QImode))
-    {
-      rtx seq
-	= gen_unaligned_extendqidi (operands[0],
-				    get_unaligned_address (operands[1], 1));
-
-      alpha_set_memflags (seq, operands[1]);
-      emit_insn (seq);
-      DONE;
-    }
-
-  operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
-  operands[2] = gen_reg_rtx (DImode);
-}")
-
-(define_expand "extendhisi2"
-  [(set (match_dup 2)
-	(ashift:DI (match_operand:HI 1 "some_operand" "")
-		   (const_int 48)))
-   (set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:DI (match_dup 2)
-		     (const_int 48)))]
-  ""
-  "
-{
-  if (TARGET_BWX)
-    {
-      emit_insn (gen_extendhisi2x (operands[0],
-				   force_reg (HImode, operands[1])));
-      DONE;
-    }
-
-  /* If we have an unaligned MEM, extend to a DImode form of
-     the result (which we do specially).  */
-  if (unaligned_memory_operand (operands[1], HImode))
-    {
-      rtx temp = gen_reg_rtx (DImode);
-
-      emit_insn (gen_extendhidi2 (temp, operands[1]));
-      emit_move_insn (operands[0], gen_lowpart (SImode, temp));
-      DONE;
-    }
-
-  operands[0] = gen_lowpart (DImode, operands[0]);
-  operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
-  operands[2] = gen_reg_rtx (DImode);
-}")
-
-(define_expand "extendhidi2"
-  [(set (match_dup 2)
-	(ashift:DI (match_operand:HI 1 "some_operand" "")
-		   (const_int 48)))
-   (set (match_operand:DI 0 "register_operand" "")
-	(ashiftrt:DI (match_dup 2)
-		     (const_int 48)))]
-  ""
-  "
-{
-  if (TARGET_BWX)
-    {
-      emit_insn (gen_extendhidi2x (operands[0],
-				   force_reg (HImode, operands[1])));
-      DONE;
-    }
-
-  if (unaligned_memory_operand (operands[1], HImode))
-    {
-      rtx seq
-	= gen_unaligned_extendhidi (operands[0],
-				    get_unaligned_address (operands[1], 2));
-
-      alpha_set_memflags (seq, operands[1]);
-      emit_insn (seq);
-      DONE;
-    }
-
-  operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
-  operands[2] = gen_reg_rtx (DImode);
-}")
-
-;; Here's how we sign extend an unaligned byte and halfword.  Doing this
-;; as a pattern saves one instruction.  The code is similar to that for
-;; the unaligned loads (see below).
-;;
-;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
-(define_expand "unaligned_extendqidi"
-  [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
-   (set (match_dup 3)
-	(mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
-			(const_int -8))))
-   (set (match_dup 4)
-	(ashift:DI (match_dup 3)
-		   (minus:DI (const_int 56)
-			     (ashift:DI
-			      (and:DI (plus:DI (match_dup 2) (const_int -1))
-				      (const_int 7))
-			      (const_int 3)))))
-   (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
-	(ashiftrt:DI (match_dup 4) (const_int 56)))]
-  ""
-  "
-{ operands[2] = gen_reg_rtx (DImode);
-  operands[3] = gen_reg_rtx (DImode);
-  operands[4] = gen_reg_rtx (DImode);
-}")
-
-(define_expand "unaligned_extendhidi"
-  [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
-   (set (match_dup 3)
-	(mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
-			(const_int -8))))
-   (set (match_dup 4)
-	(ashift:DI (match_dup 3)
-		   (minus:DI (const_int 56)
-			     (ashift:DI
-			      (and:DI (plus:DI (match_dup 2) (const_int -1))
-				      (const_int 7))
-			      (const_int 3)))))
-   (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
-	(ashiftrt:DI (match_dup 4) (const_int 48)))]
-  ""
-  "
-{ operands[2] = gen_reg_rtx (DImode);
-  operands[3] = gen_reg_rtx (DImode);
-  operands[4] = gen_reg_rtx (DImode);
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-			 (match_operand:DI 2 "mode_width_operand" "n")
-			 (match_operand:DI 3 "mul8_operand" "I")))]
-  ""
-  "ext%M2l %r1,%s3,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "extxl"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-			 (match_operand:DI 2 "mode_width_operand" "n")
-			 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
-				    (const_int 3))))]
-  ""
-  "ext%M2l %r1,%3,%0"
-  [(set_attr "type" "shift")])
-
-;; Combine has some strange notion of preserving existing undefined behaviour
-;; in shifts larger than a word size.  So capture these patterns that it 
-;; should have turned into zero_extracts.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		(ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			   (const_int 3)))
-	     (match_operand:DI 3 "mode_mask_operand" "n")))]
-  ""
-  "ext%U3l %1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-	  (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-		     (const_int 3))))]
-  ""
-  "extql %1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "extqh"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI
-	 (match_operand:DI 1 "reg_or_0_operand" "rJ")
-	  (minus:DI (const_int 56)
-		    (ashift:DI
-		     (and:DI
-		      (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			       (const_int -1))
-		      (const_int 7))
-		     (const_int 3)))))]
-  ""
-  "extqh %r1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "extlh"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI
-	 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		 (const_int 2147483647))
-	 (minus:DI (const_int 56)
-		    (ashift:DI
-		     (and:DI
-		      (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			       (const_int -1))
-		      (const_int 7))
-		     (const_int 3)))))]
-  ""
-  "extlh %r1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "extwh"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI
-	 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		 (const_int 65535))
-	 (minus:DI (const_int 56)
-		    (ashift:DI
-		     (and:DI
-		      (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			       (const_int -1))
-		      (const_int 7))
-		     (const_int 3)))))]
-  ""
-  "extwh %r1,%2,%0"
-  [(set_attr "type" "shift")])
-
-;; This converts an extXl into an extXh with an appropriate adjustment
-;; to the address calculation.
-
-;;(define_split
-;;  [(set (match_operand:DI 0 "register_operand" "")
-;;	(ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
-;;				    (match_operand:DI 2 "mode_width_operand" "")
-;;				    (ashift:DI (match_operand:DI 3 "" "")
-;;					       (const_int 3)))
-;;		   (match_operand:DI 4 "const_int_operand" "")))
-;;   (clobber (match_operand:DI 5 "register_operand" ""))]
-;;  "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
-;;  [(set (match_dup 5) (match_dup 6))
-;;   (set (match_dup 0)
-;;	(ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
-;;				    (ashift:DI (plus:DI (match_dup 5)
-;;							(match_dup 7))
-;;					       (const_int 3)))
-;;		   (match_dup 4)))]
-;;  "
-;;{
-;;  operands[6] = plus_constant (operands[3], 
-;;			       INTVAL (operands[2]) / BITS_PER_UNIT);
-;;  operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
-;;}")
-  
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
-		   (match_operand:DI 2 "mul8_operand" "I")))]
-  ""
-  "insbl %1,%s2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
-		   (match_operand:DI 2 "mul8_operand" "I")))]
-  ""
-  "inswl %1,%s2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
-		   (match_operand:DI 2 "mul8_operand" "I")))]
-  ""
-  "insll %1,%s2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "insbl"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
-		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			      (const_int 3))))]
-  ""
-  "insbl %1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "inswl"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
-		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			      (const_int 3))))]
-  ""
-  "inswl %1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "insll"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
-		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			      (const_int 3))))]
-  ""
-  "insll %1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "insql"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (match_operand:DI 1 "register_operand" "r")
-		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			      (const_int 3))))]
-  ""
-  "insql %1,%2,%0"
-  [(set_attr "type" "shift")])
-
-;; Combine has this sometimes habit of moving the and outside of the
-;; shift, making life more interesting.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
-		   	   (match_operand:DI 2 "mul8_operand" "I"))
-		(match_operand:DI 3 "immediate_operand" "i")))]
-  "HOST_BITS_PER_WIDE_INT == 64
-   && GET_CODE (operands[3]) == CONST_INT
-   && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
-        == INTVAL (operands[3]))
-       || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
-        == INTVAL (operands[3]))
-       || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
-        == INTVAL (operands[3])))"
-  "*
-{
-#if HOST_BITS_PER_WIDE_INT == 64
-  if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
-      == INTVAL (operands[3]))
-    return \"insbl %1,%s2,%0\";
-  if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
-      == INTVAL (operands[3]))
-    return \"inswl %1,%s2,%0\";
-  if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
-      == INTVAL (operands[3]))
-    return \"insll %1,%s2,%0\";
-#endif
-  abort();
-}"
-  [(set_attr "type" "shift")])
-
-;; We do not include the insXh insns because they are complex to express
-;; and it does not appear that we would ever want to generate them.
-;;
-;; Since we need them for block moves, though, cop out and use unspec.
-
-(define_insn "insxh"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(unspec [(match_operand:DI 1 "register_operand" "r")
-		 (match_operand:DI 2 "mode_width_operand" "n")
-		 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
-  ""
-  "ins%M2h %1,%3,%0"
-  [(set_attr "type" "shift")])
-
-(define_insn "mskxl"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI (not:DI (ashift:DI
-			 (match_operand:DI 2 "mode_mask_operand" "n")
-			 (ashift:DI
-			  (match_operand:DI 3 "reg_or_8bit_operand" "rI")
-			  (const_int 3))))
-		(match_operand:DI 1 "reg_or_0_operand" "rJ")))]
-  ""
-  "msk%U2l %r1,%3,%0"
-  [(set_attr "type" "shift")])
-
-;; We do not include the mskXh insns because it does not appear we would
-;; ever generate one.
-;;
-;; Again, we do for block moves and we use unspec again.
-
-(define_insn "mskxh"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(unspec [(match_operand:DI 1 "register_operand" "r")
-		 (match_operand:DI 2 "mode_width_operand" "n")
-		 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
-  ""
-  "msk%M2h %1,%3,%0"
-  [(set_attr "type" "shift")])
-
-;; Floating-point operations.  All the double-precision insns can extend
-;; from single, so indicate that.  The exception are the ones that simply
-;; play with the sign bits; it's not clear what to do there.
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "cpys $f31,%R1,%0"
-  [(set_attr "type" "fcpys")])
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "cpys $f31,%R1,%0"
-  [(set_attr "type" "fcpys")])
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "cpysn %R1,%R1,%0"
-  [(set_attr "type" "fadd")])
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "cpysn %R1,%R1,%0"
-  [(set_attr "type" "fadd")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=&f")
-	(plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "add%,%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "add%,%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=&f")
-	(plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "add%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "add%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (float_extend:DF
-		  (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
-		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "add%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (float_extend:DF
-		  (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
-		 (float_extend:DF
-		  (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "add%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-;; Define conversion operators between DFmode and SImode, using the cvtql
-;; instruction.  To allow combine et al to do useful things, we keep the
-;; operation as a unit until after reload, at which point we split the
-;; instructions.
-;;
-;; Note that we (attempt to) only consider this optimization when the
-;; ultimate destination is memory.  If we will be doing further integer
-;; processing, it is cheaper to do the truncation in the int regs.
-
-(define_insn "*cvtql"
-  [(set (match_operand:SI 0 "register_operand" "=f")
-	(unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
-  "TARGET_FP"
-  "cvtql%` %R1,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_split
-  [(set (match_operand:SI 0 "memory_operand" "")
-	(subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
-   (clobber (match_scratch:DI 2 ""))
-   (clobber (match_scratch:SI 3 ""))]
-  "TARGET_FP && reload_completed"
-  [(set (match_dup 2) (fix:DI (match_dup 1)))
-   (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
-   (set (match_dup 0) (match_dup 3))]
-  "")
-
-(define_split
-  [(set (match_operand:SI 0 "memory_operand" "")
-	(subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_FP && reload_completed"
-  [(set (match_dup 2) (fix:DI (match_dup 1)))
-   (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
-   (set (match_dup 0) (match_dup 3))]
-  ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
-  "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "memory_operand" "=m")
-	(subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
-   (clobber (match_scratch:DI 2 "=&f"))
-   (clobber (match_scratch:SI 3 "=&f"))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "#"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "memory_operand" "=m")
-	(subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
-   (clobber (match_scratch:DI 2 "=f"))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "#"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=&f")
-	(fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "cvt%-q%(c %R1,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn "fix_truncdfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=f")
-	(fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "cvt%-q%(c %R1,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-;; Likewise between SFmode and SImode.
-
-(define_split
-  [(set (match_operand:SI 0 "memory_operand" "")
-	(subreg:SI (fix:DI (float_extend:DF
-		 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
-   (clobber (match_scratch:DI 2 ""))
-   (clobber (match_scratch:SI 3 ""))]
-  "TARGET_FP && reload_completed"
-  [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
-   (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
-   (set (match_dup 0) (match_dup 3))]
-  "")
-
-(define_split
-  [(set (match_operand:SI 0 "memory_operand" "")
-	(subreg:SI (fix:DI (float_extend:DF
-		 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_FP && reload_completed"
-  [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
-   (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
-   (set (match_dup 0) (match_dup 3))]
-  ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
-  "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "memory_operand" "=m")
-	(subreg:SI (fix:DI (float_extend:DF
-		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
-   (clobber (match_scratch:DI 2 "=&f"))
-   (clobber (match_scratch:SI 3 "=&f"))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "#"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "memory_operand" "=m")
-	(subreg:SI (fix:DI (float_extend:DF
-		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
-   (clobber (match_scratch:DI 2 "=f"))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "#"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=&f")
-	(fix:DI (float_extend:DF
-		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "cvt%-q%(c %R1,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn "fix_truncsfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=f")
-	(fix:DI (float_extend:DF
-		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP"
-  "cvt%-q%(c %R1,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=&f")
-	(float:SF (match_operand:DI 1 "register_operand" "f")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "cvtq%,%+%& %1,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn "floatdisf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float:SF (match_operand:DI 1 "register_operand" "f")))]
-  "TARGET_FP"
-  "cvtq%,%+%& %1,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=&f")
-	(float:DF (match_operand:DI 1 "register_operand" "f")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "cvtq%-%+%& %1,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn "floatdidf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float:DF (match_operand:DI 1 "register_operand" "f")))]
-  "TARGET_FP"
-  "cvtq%-%+%& %1,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_expand "extendsfdf2"
-  [(use (match_operand:DF 0 "register_operand" ""))
-   (use (match_operand:SF 1 "nonimmediate_operand" ""))]
-  "TARGET_FP"
-"
-{
-  if (alpha_tp == ALPHA_TP_INSN)
-    emit_insn (gen_extendsfdf2_tp (operands[0],
-				   force_reg (SFmode, operands[1])));
-  else
-    emit_insn (gen_extendsfdf2_no_tp (operands[0], operands[1]));
-
-  DONE;
-}")
-;; FIXME
-(define_insn "extendsfdf2_tp"
-  [(set (match_operand:DF 0 "register_operand" "=&f")
-	(float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "cvtsts %1,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn "extendsfdf2_no_tp"
-  [(set (match_operand:DF 0 "register_operand" "=f,f,m")
-	(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "@
-   cpys %1,%1,%0
-   ld%, %0,%1
-   st%- %1,%0"
-  [(set_attr "type" "fcpys,fld,fst")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=&f")
-	(float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "cvt%-%,%)%& %R1,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "cvt%-%,%)%& %R1,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=&f")
-	(div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
-		(match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "div%,%)%& %R1,%R2,%0"
-  [(set_attr "type" "fdiv")
-   (set_attr "opsize" "si")
-   (set_attr "trap" "yes")])
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
-		(match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "div%,%)%& %R1,%R2,%0"
-  [(set_attr "type" "fdiv")
-   (set_attr "opsize" "si")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=&f")
-	(div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
-		(match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "div%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fdiv")
-   (set_attr "trap" "yes")])
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
-		(match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "div%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fdiv")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
-		(match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "div%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fdiv")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
-		(float_extend:DF
-		 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "div%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fdiv")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
-		(float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "div%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fdiv")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=&f")
-	(mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "mul%,%)%& %R1,%R2,%0"
-  [(set_attr "type" "fmul")
-   (set_attr "trap" "yes")])
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "mul%,%)%& %R1,%R2,%0"
-  [(set_attr "type" "fmul")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=&f")
-	(mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "mul%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fmul")
-   (set_attr "trap" "yes")])
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
-		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "mul%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fmul")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mult:DF (float_extend:DF
-		  (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
-		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "mul%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fmul")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mult:DF (float_extend:DF
-		  (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
-		 (float_extend:DF
-		  (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "mul%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fmul")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=&f")
-	(minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
-		  (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "sub%,%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
-		  (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "sub%,%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=&f")
-	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
-		  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "sub%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
-		  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "sub%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (float_extend:DF
-		   (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
-		  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "sub%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
-		  (float_extend:DF
-		   (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "sub%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (float_extend:DF
-		   (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
-		  (float_extend:DF
-		   (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "sub%-%)%& %R1,%R2,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=&f")
-	(sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN"
-  "sqrt%,%)%& %R1,%0"
-  [(set_attr "type" "fsqrt")
-   (set_attr "opsize" "si")
-   (set_attr "trap" "yes")])
-
-(define_insn "sqrtsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && TARGET_CIX"
-  "sqrt%,%)%& %R1,%0"
-  [(set_attr "type" "fsqrt")
-   (set_attr "opsize" "si")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=&f")
-	(sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN"
-  "sqrt%-%)%& %R1,%0"
-  [(set_attr "type" "fsqrt")
-   (set_attr "trap" "yes")])
-
-(define_insn "sqrtdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP && TARGET_CIX"
-  "sqrt%-%)%& %1,%0"
-  [(set_attr "type" "fsqrt")
-   (set_attr "trap" "yes")])
-
-;; Next are all the integer comparisons, and conditional moves and branches
-;; and some of the related define_expand's and define_split's.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(match_operator:DI 1 "alpha_comparison_operator"
-			   [(match_operand:DI 2 "reg_or_0_operand" "rJ")
-			    (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
-  ""
-  "cmp%C1 %r2,%3,%0"
-  [(set_attr "type" "icmp")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (match_operator:DI 1 "alpha_swapped_comparison_operator"
-			   [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			    (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
-  ""
-  "cmp%c1 %r3,%2,%0"
-  [(set_attr "type" "icmp")])
-
-;; This pattern exists so conditional moves of SImode values are handled.
-;; Comparisons are still done in DImode though.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(if_then_else:SI
-	 (match_operator 2 "signed_comparison_operator"
-			 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
-			  (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
-	 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
-	 (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
-  "operands[3] == const0_rtx || operands[4] == const0_rtx"
-  "@
-   cmov%C2 %r3,%1,%0
-   cmov%D2 %r3,%5,%0
-   cmov%c2 %r4,%1,%0
-   cmov%d2 %r4,%5,%0"
-  [(set_attr "type" "icmov")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
-	(if_then_else:DI
-	 (match_operator 2 "signed_comparison_operator"
-			 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
-			  (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
-	 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
-	 (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
-  "operands[3] == const0_rtx || operands[4] == const0_rtx"
-  "@
-   cmov%C2 %r3,%1,%0
-   cmov%D2 %r3,%5,%0
-   cmov%c2 %r4,%1,%0
-   cmov%d2 %r4,%5,%0"
-  [(set_attr "type" "icmov")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(if_then_else:DI
-	 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
-			      (const_int 1)
-			      (const_int 0))
-	     (const_int 0))
-	 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
-	 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
-  ""
-  "@
-   cmovlbc %r2,%1,%0
-   cmovlbs %r2,%3,%0"
-  [(set_attr "type" "icmov")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(if_then_else:DI
-	 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
-			      (const_int 1)
-			      (const_int 0))
-	     (const_int 0))
-	 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
-	 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
-  ""
-  "@
-   cmovlbs %r2,%1,%0
-   cmovlbc %r2,%3,%0"
-  [(set_attr "type" "icmov")])
-
-;; This form is added since combine thinks that an IF_THEN_ELSE with both
-;; arms constant is a single insn, so it won't try to form it if combine
-;; knows they are really two insns.  This occurs in divides by powers
-;; of two.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(if_then_else:DI
-	 (match_operator 2 "signed_comparison_operator"
-			 [(match_operand:DI 3 "reg_or_0_operand" "rJ")
-			  (const_int 0)])
-	 (plus:DI (match_dup 0)
-		  (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
-	 (match_dup 0)))
-   (clobber (match_scratch:DI 4 "=&r"))]
-  ""
-  "addq %0,%1,%4\;cmov%C2 %r3,%4,%0"
-  [(set_attr "type" "icmov")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI
-	 (match_operator 2 "signed_comparison_operator"
-			 [(match_operand:DI 3 "reg_or_0_operand" "")
-			  (const_int 0)])
-	 (plus:DI (match_dup 0)
-		  (match_operand:DI 1 "reg_or_8bit_operand" ""))
-	 (match_dup 0)))
-   (clobber (match_operand:DI 4 "register_operand" ""))]
-  ""
-  [(set (match_dup 4) (plus:DI (match_dup 0) (match_dup 1)))
-   (set (match_dup 0) (if_then_else:DI (match_op_dup 2
-						     [(match_dup 3)
-						      (const_int 0)])
-				       (match_dup 4) (match_dup 0)))]
-  "")
-
-(define_split
-  [(parallel
-    [(set (match_operand:DI 0 "register_operand" "")
-	  (if_then_else:DI
-	   (match_operator 1 "comparison_operator"
-			   [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
-					     (const_int 1)
-					     (match_operand:DI 3 "const_int_operand" ""))
-			    (const_int 0)])
-	   (match_operand:DI 4 "reg_or_8bit_operand" "")
-	   (match_operand:DI 5 "reg_or_8bit_operand" "")))
-     (clobber (match_operand:DI 6 "register_operand" ""))])]
-  "INTVAL (operands[3]) != 0"
-  [(set (match_dup 6)
-	(lshiftrt:DI (match_dup 2) (match_dup 3)))
-   (set (match_dup 0)
-	(if_then_else:DI (match_op_dup 1
-				       [(zero_extract:DI (match_dup 6)
-							 (const_int 1)
-							 (const_int 0))
-					(const_int 0)])
-			 (match_dup 4)
-			 (match_dup 5)))]
-  "")
-
-;; For ABS, we have two choices, depending on whether the input and output
-;; registers are the same or not.
-(define_expand "absdi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(abs:DI (match_operand:DI 1 "register_operand" "")))]
-  ""
-  "
-{ if (rtx_equal_p (operands[0], operands[1]))
-    emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
-  else
-    emit_insn (gen_absdi2_diff (operands[0], operands[1]));
-
-  DONE;
-}")
-
-(define_expand "absdi2_same"
-  [(set (match_operand:DI 1 "register_operand" "")
-	(neg:DI (match_operand:DI 0 "register_operand" "")))
-   (set (match_dup 0)
-	(if_then_else:DI (ge (match_dup 0) (const_int 0))
-			 (match_dup 0)
-			 (match_dup 1)))]
-  ""
-  "")
-
-(define_expand "absdi2_diff"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(neg:DI (match_operand:DI 1 "register_operand" "")))
-   (set (match_dup 0)
-	(if_then_else:DI (lt (match_dup 1) (const_int 0))
-			 (match_dup 0)
-			 (match_dup 1)))]
-  ""
-  "")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(abs:DI (match_dup 0)))
-   (clobber (match_operand:DI 2 "register_operand" ""))]
-  ""
-  [(set (match_dup 1) (neg:DI (match_dup 0)))
-   (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
-				       (match_dup 0) (match_dup 1)))]
-  "")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(abs:DI (match_operand:DI 1 "register_operand" "")))]
-  "! rtx_equal_p (operands[0], operands[1])"
-  [(set (match_dup 0) (neg:DI (match_dup 1)))
-   (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
-				       (match_dup 0) (match_dup 1)))]
-  "")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(neg:DI (abs:DI (match_dup 0))))
-   (clobber (match_operand:DI 2 "register_operand" ""))]
-  ""
-  [(set (match_dup 1) (neg:DI (match_dup 0)))
-   (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
-				       (match_dup 0) (match_dup 1)))]
-  "")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
-  "! rtx_equal_p (operands[0], operands[1])"
-  [(set (match_dup 0) (neg:DI (match_dup 1)))
-   (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
-				       (match_dup 0) (match_dup 1)))]
-  "")
-
-(define_insn "sminqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
-		 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
-  "TARGET_MAX"
-  "minsb8 %r1,%2,%0"
-  [(set_attr "type" "mvi")])
-
-(define_insn "uminqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
-		 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
-  "TARGET_MAX"
-  "minub8 %r1,%2,%0"
-  [(set_attr "type" "mvi")])
-
-(define_insn "smaxqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
-		 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
-  "TARGET_MAX"
-  "maxsb8 %r1,%2,%0"
-  [(set_attr "type" "mvi")])
-
-(define_insn "umaxqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
-		 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
-  "TARGET_MAX"
-  "maxub8 %r1,%2,%0"
-  [(set_attr "type" "mvi")])
-
-(define_insn "sminhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
-		 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
-  "TARGET_MAX"
-  "minsw4 %r1,%2,%0"
-  [(set_attr "type" "mvi")])
-
-(define_insn "uminhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
-		 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
-  "TARGET_MAX"
-  "minuw4 %r1,%2,%0"
-  [(set_attr "type" "mvi")])
-
-(define_insn "smaxhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
-		 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
-  "TARGET_MAX"
-  "maxsw4 %r1,%2,%0"
-  [(set_attr "type" "mvi")])
-
-(define_insn "umaxhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
-		 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
-  "TARGET_MAX"
-  "maxuw4 %r1,%2,%0"
-  [(set_attr "type" "shift")])
-
-(define_expand "smaxdi3"
-  [(set (match_dup 3)
-	(le:DI (match_operand:DI 1 "reg_or_0_operand" "")
-	       (match_operand:DI 2 "reg_or_8bit_operand" "")))
-   (set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI (eq (match_dup 3) (const_int 0))
-			 (match_dup 1) (match_dup 2)))]
-  ""
-  "
-{ operands[3] = gen_reg_rtx (DImode);
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
-		 (match_operand:DI 2 "reg_or_8bit_operand" "")))
-   (clobber (match_operand:DI 3 "register_operand" ""))]
-  "operands[2] != const0_rtx"
-  [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
-				       (match_dup 1) (match_dup 2)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(smax:DI (match_operand:DI 1 "register_operand" "0")
-		 (const_int 0)))]
-  ""
-  "cmovlt %0,0,%0"
-  [(set_attr "type" "icmov")])
-
-(define_expand "smindi3"
-  [(set (match_dup 3)
-	(lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
-	       (match_operand:DI 2 "reg_or_8bit_operand" "")))
-   (set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI (ne (match_dup 3) (const_int 0))
-			 (match_dup 1) (match_dup 2)))]
-  ""
-  "
-{ operands[3] = gen_reg_rtx (DImode);
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
-		 (match_operand:DI 2 "reg_or_8bit_operand" "")))
-   (clobber (match_operand:DI 3 "register_operand" ""))]
-  "operands[2] != const0_rtx"
-  [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
-				       (match_dup 1) (match_dup 2)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(smin:DI (match_operand:DI 1 "register_operand" "0")
-		 (const_int 0)))]
-  ""
-  "cmovgt %0,0,%0"
-  [(set_attr "type" "icmov")])
-
-(define_expand "umaxdi3"
-  [(set (match_dup 3) 
-	(leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
-		(match_operand:DI 2 "reg_or_8bit_operand" "")))
-   (set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI (eq (match_dup 3) (const_int 0))
-			 (match_dup 1) (match_dup 2)))]
-  ""
-  "
-{ operands[3] = gen_reg_rtx (DImode);
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
-		 (match_operand:DI 2 "reg_or_8bit_operand" "")))
-   (clobber (match_operand:DI 3 "register_operand" ""))]
-  "operands[2] != const0_rtx"
-  [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
-				       (match_dup 1) (match_dup 2)))]
-  "")
-
-(define_expand "umindi3"
-  [(set (match_dup 3)
-	(ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
-		(match_operand:DI 2 "reg_or_8bit_operand" "")))
-   (set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI (ne (match_dup 3) (const_int 0))
-			 (match_dup 1) (match_dup 2)))]
-  ""
-  "
-{ operands[3] = gen_reg_rtx (DImode);
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
-		 (match_operand:DI 2 "reg_or_8bit_operand" "")))
-   (clobber (match_operand:DI 3 "register_operand" ""))]
-  "operands[2] != const0_rtx"
-  [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
-				       (match_dup 1) (match_dup 2)))]
-  "")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 1 "signed_comparison_operator"
-			 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
-			  (const_int 0)])
-	 (label_ref (match_operand 0 "" ""))
-	 (pc)))]
-  ""
-  "b%C1 %r2,%0"
-  [(set_attr "type" "ibr")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 1 "signed_comparison_operator"
-			 [(const_int 0)
-			  (match_operand:DI 2 "register_operand" "r")])
-	 (label_ref (match_operand 0 "" ""))
-	 (pc)))]
-  ""
-  "b%c1 %2,%0"
-  [(set_attr "type" "ibr")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-			      (const_int 1)
-			      (const_int 0))
-	     (const_int 0))
-	 (label_ref (match_operand 0 "" ""))
-	 (pc)))]
-  ""
-  "blbs %r1,%0"
-  [(set_attr "type" "ibr")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-			      (const_int 1)
-			      (const_int 0))
-	     (const_int 0))
-	 (label_ref (match_operand 0 "" ""))
-	 (pc)))]
-  ""
-  "blbc %r1,%0"
-  [(set_attr "type" "ibr")])
-
-(define_split
-  [(parallel
-    [(set (pc)
-	  (if_then_else
-	   (match_operator 1 "comparison_operator"
-			   [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
-					     (const_int 1)
-					     (match_operand:DI 3 "const_int_operand" ""))
-			    (const_int 0)])
-	   (label_ref (match_operand 0 "" ""))
-	   (pc)))
-     (clobber (match_operand:DI 4 "register_operand" ""))])]
-  "INTVAL (operands[3]) != 0"
-  [(set (match_dup 4)
-	(lshiftrt:DI (match_dup 2) (match_dup 3)))
-   (set (pc)
-	(if_then_else (match_op_dup 1
-				    [(zero_extract:DI (match_dup 4)
-						      (const_int 1)
-						      (const_int 0))
-				     (const_int 0)])
-		      (label_ref (match_dup 0))
-		      (pc)))]
-  "")
-
-;; The following are the corresponding floating-point insns.  Recall
-;; we need to have variants that expand the arguments from SF mode
-;; to DFmode.
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=&f")
-	(match_operator:DF 1 "alpha_comparison_operator"
-			   [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
-			    (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "cmp%-%C1%' %R2,%R3,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(match_operator:DF 1 "alpha_comparison_operator"
-			   [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
-			    (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "cmp%-%C1%' %R2,%R3,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=&f")
-	(match_operator:DF 1 "alpha_comparison_operator"
-			   [(float_extend:DF
-			     (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
-			    (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "cmp%-%C1%' %R2,%R3,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(match_operator:DF 1 "alpha_comparison_operator"
-			   [(float_extend:DF
-			     (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
-			    (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "cmp%-%C1%' %R2,%R3,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=&f")
-	(match_operator:DF 1 "alpha_comparison_operator"
-			   [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
-			    (float_extend:DF
-			     (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "cmp%-%C1%' %R2,%R3,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(match_operator:DF 1 "alpha_comparison_operator"
-			   [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
-			    (float_extend:DF
-			     (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "cmp%-%C1%' %R2,%R3,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=&f")
-	(match_operator:DF 1 "alpha_comparison_operator"
-			   [(float_extend:DF
-			     (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
-			    (float_extend:DF
-			     (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
-  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
-  "cmp%-%C1%' %R2,%R3,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(match_operator:DF 1 "alpha_comparison_operator"
-			   [(float_extend:DF
-			     (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
-			    (float_extend:DF
-			     (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
-  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
-  "cmp%-%C1%' %R2,%R3,%0"
-  [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(if_then_else:DF 
-	 (match_operator 3 "signed_comparison_operator"
-			 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
-			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
-	 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
-  "TARGET_FP"
-  "@
-   fcmov%C3 %R4,%R1,%0
-   fcmov%D3 %R4,%R5,%0"
-  [(set_attr "type" "fcmov")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-	(if_then_else:SF 
-	 (match_operator 3 "signed_comparison_operator"
-			 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
-			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
-	 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
-  "TARGET_FP"
-  "@
-   fcmov%C3 %R4,%R1,%0
-   fcmov%D3 %R4,%R5,%0"
-  [(set_attr "type" "fcmov")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(if_then_else:DF 
-	 (match_operator 3 "signed_comparison_operator"
-			 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
-			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
-	 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
-  "TARGET_FP"
-  "@
-   fcmov%C3 %R4,%R1,%0
-   fcmov%D3 %R4,%R5,%0"
-  [(set_attr "type" "fcmov")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(if_then_else:DF 
-	 (match_operator 3 "signed_comparison_operator"
-			 [(float_extend:DF 
-			   (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
-			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
-	 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
-  "TARGET_FP"
-  "@
-   fcmov%C3 %R4,%R1,%0
-   fcmov%D3 %R4,%R5,%0"
-  [(set_attr "type" "fcmov")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-	(if_then_else:SF 
-	 (match_operator 3 "signed_comparison_operator"
-			 [(float_extend:DF
-			   (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
-			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
-	 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
-  "TARGET_FP"
-  "@
-   fcmov%C3 %R4,%R1,%0
-   fcmov%D3 %R4,%R5,%0"
-  [(set_attr "type" "fcmov")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(if_then_else:DF 
-	 (match_operator 3 "signed_comparison_operator"
-			 [(float_extend:DF
-			   (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
-			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
-	 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
-  "TARGET_FP"
-  "@
-   fcmov%C3 %R4,%R1,%0
-   fcmov%D3 %R4,%R5,%0"
-  [(set_attr "type" "fcmov")])
-
-(define_expand "maxdf3"
-  [(set (match_dup 3)
-	(le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
-	       (match_operand:DF 2 "reg_or_fp0_operand" "")))
-   (set (match_operand:DF 0 "register_operand" "")
-	(if_then_else:DF (eq (match_dup 3) (match_dup 4))
-			 (match_dup 1) (match_dup 2)))]
-  "TARGET_FP"
-  "
-{ operands[3] = gen_reg_rtx (DFmode);
-  operands[4] = CONST0_RTX (DFmode);
-}")
-
-(define_expand "mindf3"
-  [(set (match_dup 3)
-	(lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
-	       (match_operand:DF 2 "reg_or_fp0_operand" "")))
-   (set (match_operand:DF 0 "register_operand" "")
-	(if_then_else:DF (ne (match_dup 3) (match_dup 4))
-			 (match_dup 1) (match_dup 2)))]
-  "TARGET_FP"
-  "
-{ operands[3] = gen_reg_rtx (DFmode);
-  operands[4] = CONST0_RTX (DFmode);
-}")
-
-(define_expand "maxsf3"
-  [(set (match_dup 3)
-	(le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
-	       (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
-   (set (match_operand:SF 0 "register_operand" "")
-	(if_then_else:SF (eq (match_dup 3) (match_dup 4))
-			 (match_dup 1) (match_dup 2)))]
-  "TARGET_FP"
-  "
-{ operands[3] = gen_reg_rtx (DFmode);
-  operands[4] = CONST0_RTX (DFmode);
-}")
-
-(define_expand "minsf3"
-  [(set (match_dup 3)
-	(lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
-	       (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
-   (set (match_operand:SF 0 "register_operand" "")
-	(if_then_else:SF (ne (match_dup 3) (match_dup 4))
-		      (match_dup 1) (match_dup 2)))]
-  "TARGET_FP"
-  "
-{ operands[3] = gen_reg_rtx (DFmode);
-  operands[4] = CONST0_RTX (DFmode);
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 1 "signed_comparison_operator"
-			 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
-			  (match_operand:DF 3 "fp0_operand" "G")])
-	 (label_ref (match_operand 0 "" ""))
-	 (pc)))]
-  "TARGET_FP"
-  "fb%C1 %R2,%0"
-  [(set_attr "type" "fbr")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 1 "signed_comparison_operator"
-			 [(float_extend:DF
-			   (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
-			  (match_operand:DF 3 "fp0_operand" "G")])
-	 (label_ref (match_operand 0 "" ""))
-	 (pc)))]
-  "TARGET_FP"
-  "fb%C1 %R2,%0"
-  [(set_attr "type" "fbr")])
-
-;; These are the main define_expand's used to make conditional branches
-;; and compares.
-
-(define_expand "cmpdf"
-  [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
-		       (match_operand:DF 1 "reg_or_fp0_operand" "")))]
-  "TARGET_FP"
-  "
-{
-  alpha_compare_op0 = operands[0];
-  alpha_compare_op1 = operands[1];
-  alpha_compare_fp_p = 1;
-  DONE;
-}")
-
-(define_expand "cmpdi"
-  [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
-		       (match_operand:DI 1 "reg_or_8bit_operand" "")))]
-  ""
-  "
-{
-  alpha_compare_op0 = operands[0];
-  alpha_compare_op1 = operands[1];
-  alpha_compare_fp_p = 0;
-  DONE;
-}")
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{ operands[1] = alpha_emit_conditional_branch (NE); }")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{ operands[1] = alpha_emit_conditional_branch (LT); }")
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{ operands[1] = alpha_emit_conditional_branch (LE); }")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{ operands[1] = alpha_emit_conditional_branch (GT); }")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{ operands[1] = alpha_emit_conditional_branch (GE); }")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
-
-(define_expand "seq"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  if (alpha_compare_fp_p)
-    FAIL;
-
-  operands[1] = gen_rtx_EQ (DImode, alpha_compare_op0, alpha_compare_op1);
-}")
-
-(define_expand "sne"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_dup 1))
-   (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
-  ""
-  "
-{
-  if (alpha_compare_fp_p)
-    FAIL;
-
-  operands[1] = gen_rtx_EQ (DImode, alpha_compare_op0, alpha_compare_op1);
-}")
-
-(define_expand "slt"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  if (alpha_compare_fp_p)
-    FAIL;
-
-  operands[1] = gen_rtx_LT (DImode, alpha_compare_op0, alpha_compare_op1);
-}")
-
-(define_expand "sle"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  if (alpha_compare_fp_p)
-    FAIL;
-
-  operands[1] = gen_rtx_LE (DImode, alpha_compare_op0, alpha_compare_op1);
-}")
-
-(define_expand "sgt"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  if (alpha_compare_fp_p)
-    FAIL;
-
-  operands[1] = gen_rtx_LT (DImode, force_reg (DImode, alpha_compare_op1),
-			    alpha_compare_op0);
-}")
-
-(define_expand "sge"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  if (alpha_compare_fp_p)
-    FAIL;
-
-  operands[1] = gen_rtx_LE (DImode, force_reg (DImode, alpha_compare_op1),
-			    alpha_compare_op0);
-}")
-
-(define_expand "sltu"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  if (alpha_compare_fp_p)
-    FAIL;
-
-  operands[1] = gen_rtx_LTU (DImode, alpha_compare_op0, alpha_compare_op1);
-}")
-
-(define_expand "sleu"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  if (alpha_compare_fp_p)
-    FAIL;
-
-  operands[1] = gen_rtx_LEU (DImode, alpha_compare_op0, alpha_compare_op1);
-}")
-
-(define_expand "sgtu"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  if (alpha_compare_fp_p)
-    FAIL;
-
-  operands[1] = gen_rtx_LTU (DImode, force_reg (DImode, alpha_compare_op1),
-			     alpha_compare_op0);
-}")
-
-(define_expand "sgeu"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  if (alpha_compare_fp_p)
-    FAIL;
-
-  operands[1] = gen_rtx_LEU (DImode, force_reg (DImode, alpha_compare_op1),
-			     alpha_compare_op0);
-}")
-
-;; These are the main define_expand's used to make conditional moves.
-
-(define_expand "movsicc"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(if_then_else:SI (match_operand 1 "comparison_operator" "")
-			 (match_operand:SI 2 "reg_or_8bit_operand" "")
-			 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
-  ""
-  "
-{
-  if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
-    FAIL;
-}")
-
-(define_expand "movdicc"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI (match_operand 1 "comparison_operator" "")
-			 (match_operand:DI 2 "reg_or_8bit_operand" "")
-			 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
-  ""
-  "
-{
-  if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
-    FAIL;
-}")
-
-(define_expand "movsfcc"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(if_then_else:SF (match_operand 1 "comparison_operator" "")
-			 (match_operand:SF 2 "reg_or_8bit_operand" "")
-			 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
-  ""
-  "
-{
-  if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
-    FAIL;
-}")
-
-(define_expand "movdfcc"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(if_then_else:DF (match_operand 1 "comparison_operator" "")
-			 (match_operand:DF 2 "reg_or_8bit_operand" "")
-			 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
-  ""
-  "
-{
-  if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
-    FAIL;
-}")
-
-;; These define_split definitions are used in cases when comparisons have
-;; not be stated in the correct way and we need to reverse the second
-;; comparison.  For example, x >= 7 has to be done as x < 6 with the
-;; comparison that tests the result being reversed.  We have one define_split
-;; for each use of a comparison.  They do not match valid insns and need
-;; not generate valid insns.
-;;
-;; We can also handle equality comparisons (and inequality comparisons in
-;; cases where the resulting add cannot overflow) by doing an add followed by
-;; a comparison with zero.  This is faster since the addition takes one
-;; less cycle than a compare when feeding into a conditional move.
-;; For this case, we also have an SImode pattern since we can merge the add
-;; and sign extend and the order doesn't matter.
-;;
-;; We do not do this for floating-point, since it isn't clear how the "wrong"
-;; operation could have been generated.
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI
-	 (match_operator 1 "comparison_operator"
-			 [(match_operand:DI 2 "reg_or_0_operand" "")
-			  (match_operand:DI 3 "reg_or_cint_operand" "")])
-	 (match_operand:DI 4 "reg_or_cint_operand" "")
-	 (match_operand:DI 5 "reg_or_cint_operand" "")))
-   (clobber (match_operand:DI 6 "register_operand" ""))]
-  "operands[3] != const0_rtx"
-  [(set (match_dup 6) (match_dup 7))
-   (set (match_dup 0)
-	(if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
-  "
-{ enum rtx_code code = GET_CODE (operands[1]);
-  int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
-
-  /* If we are comparing for equality with a constant and that constant
-     appears in the arm when the register equals the constant, use the
-     register since that is more likely to match (and to produce better code
-     if both would).  */
-
-  if (code == EQ && GET_CODE (operands[3]) == CONST_INT
-      && rtx_equal_p (operands[4], operands[3]))
-    operands[4] = operands[2];
-
-  else if (code == NE && GET_CODE (operands[3]) == CONST_INT
-	   && rtx_equal_p (operands[5], operands[3]))
-    operands[5] = operands[2];
-
-  if (code == NE || code == EQ
-      || (extended_count (operands[2], DImode, unsignedp) >= 1
-	  && extended_count (operands[3], DImode, unsignedp) >= 1))
-    {
-      if (GET_CODE (operands[3]) == CONST_INT)
-	operands[7] = gen_rtx_PLUS (DImode, operands[2],
-				    GEN_INT (- INTVAL (operands[3])));
-      else
-	operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
-
-      operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
-    }
-
-  else if (code == EQ || code == LE || code == LT
-	   || code == LEU || code == LTU)
-    {
-      operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
-      operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
-    }
-  else
-    {
-      operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
-				    operands[2], operands[3]);
-      operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
-    }
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI
-	 (match_operator 1 "comparison_operator"
-			 [(match_operand:SI 2 "reg_or_0_operand" "")
-			  (match_operand:SI 3 "reg_or_cint_operand" "")])
-	 (match_operand:DI 4 "reg_or_8bit_operand" "")
-	 (match_operand:DI 5 "reg_or_8bit_operand" "")))
-   (clobber (match_operand:DI 6 "register_operand" ""))]
-  "operands[3] != const0_rtx
-   && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
-  [(set (match_dup 6) (match_dup 7))
-   (set (match_dup 0)
-	(if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
-  "
-{ enum rtx_code code = GET_CODE (operands[1]);
-  int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
-  rtx tem;
-
-  if ((code != NE && code != EQ
-       && ! (extended_count (operands[2], DImode, unsignedp) >= 1
-	     && extended_count (operands[3], DImode, unsignedp) >= 1)))
-    FAIL;
- 
-  if (GET_CODE (operands[3]) == CONST_INT)
-    tem = gen_rtx_PLUS (SImode, operands[2],
-			GEN_INT (- INTVAL (operands[3])));
-  else
-    tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
-
-  operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
-  operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
-				operands[6], const0_rtx);
-}")
-
-(define_split
-  [(set (pc)
-	(if_then_else
-	 (match_operator 1 "comparison_operator"
-			 [(match_operand:DI 2 "reg_or_0_operand" "")
-			  (match_operand:DI 3 "reg_or_cint_operand" "")])
-	 (label_ref (match_operand 0 "" ""))
-	 (pc)))
-   (clobber (match_operand:DI 4 "register_operand" ""))]
-  "operands[3] != const0_rtx"
-  [(set (match_dup 4) (match_dup 5))
-   (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
-  "
-{ enum rtx_code code = GET_CODE (operands[1]);
-  int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
-
-  if (code == NE || code == EQ
-      || (extended_count (operands[2], DImode, unsignedp) >= 1
-	  && extended_count (operands[3], DImode, unsignedp) >= 1))
-    {
-      if (GET_CODE (operands[3]) == CONST_INT)
-	operands[5] = gen_rtx_PLUS (DImode, operands[2],
-				    GEN_INT (- INTVAL (operands[3])));
-      else
-	operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
-
-      operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
-    }
-
-  else if (code == EQ || code == LE || code == LT
-	   || code == LEU || code == LTU)
-    {
-      operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
-      operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
-    }
-  else
-    {
-      operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
-				    operands[2], operands[3]);
-      operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
-    }
-}")
-
-(define_split
-  [(set (pc)
-	(if_then_else
-	 (match_operator 1 "comparison_operator"
-			 [(match_operand:SI 2 "reg_or_0_operand" "")
-			  (match_operand:SI 3 "const_int_operand" "")])
-	 (label_ref (match_operand 0 "" ""))
-	 (pc)))
-   (clobber (match_operand:DI 4 "register_operand" ""))]
-  "operands[3] != const0_rtx
-   && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
-  [(set (match_dup 4) (match_dup 5))
-   (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
-  "
-{ rtx tem;
-
-  if (GET_CODE (operands[3]) == CONST_INT)
-    tem = gen_rtx_PLUS (SImode, operands[2],
-			GEN_INT (- INTVAL (operands[3])));
-  else
-    tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
-  
-  operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
-  operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
-				operands[4], const0_rtx);
-}")
-
-;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
-;; This eliminates one, and sometimes two, insns when the AND can be done
-;; with a ZAP.
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_operator 1 "comparison_operator"
-			[(match_operand:DI 2 "register_operand" "")
-			 (match_operand:DI 3 "const_int_operand" "")]))
-   (clobber (match_operand:DI 4 "register_operand" ""))]
-  "exact_log2 (INTVAL (operands[3]) + 1) >= 0
-   && (GET_CODE (operands[1]) == GTU
-       || GET_CODE (operands[1]) == LEU
-       || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
-	   && extended_count (operands[2], DImode, 1) > 0))"
-  [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
-   (set (match_dup 0) (match_dup 6))]
-  "
-{
-  operands[5] = GEN_INT (~ INTVAL (operands[3]));
-  operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
-				  || GET_CODE (operands[1]) == GT)
-				 ? NE : EQ),
-				DImode, operands[4], const0_rtx);
-}")
-
-;; Here are the CALL and unconditional branch insns.  Calls on NT and OSF
-;; work differently, so we have different patterns for each.
-
-(define_expand "call"
-  [(use (match_operand:DI 0 "" ""))
-   (use (match_operand 1 "" ""))
-   (use (match_operand 2 "" ""))
-   (use (match_operand 3 "" ""))]
-  ""
-  "
-{ if (TARGET_WINDOWS_NT)
-    emit_call_insn (gen_call_nt (operands[0], operands[1]));
-  else if (TARGET_OPEN_VMS)
-    emit_call_insn (gen_call_vms (operands[0], operands[2]));
-  else
-    emit_call_insn (gen_call_osf (operands[0], operands[1]));
-
-  DONE;
-}")
-
-(define_expand "call_osf"
-  [(parallel [(call (mem:DI (match_operand 0 "" ""))
-		    (match_operand 1 "" ""))
-	      (clobber (reg:DI 27))
-	      (clobber (reg:DI 26))])]
-  ""
-  "
-{ if (GET_CODE (operands[0]) != MEM)
-    abort ();
-
-  operands[0] = XEXP (operands[0], 0);
-
-  if (GET_CODE (operands[0]) != SYMBOL_REF
-      && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
-    {
-      rtx tem = gen_rtx_REG (DImode, 27);
-      emit_move_insn (tem, operands[0]);
-      operands[0] = tem;
-    }
-}")
-
-(define_expand "call_nt"
-  [(parallel [(call (mem:DI (match_operand 0 "" ""))
-		    (match_operand 1 "" ""))
-	      (clobber (reg:DI 26))])]
-  ""
-  "
-{ if (GET_CODE (operands[0]) != MEM)
-    abort ();
-
-  operands[0] = XEXP (operands[0], 0);
-  if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
-    operands[0] = force_reg (DImode, operands[0]);
-}")
-
-;;
-;; call openvms/alpha
-;; op 0: symbol ref for called function
-;; op 1: next_arg_reg (argument information value for R25)
-;;
-(define_expand "call_vms"
-  [(parallel [(call (mem:DI (match_operand 0 "" ""))
-		    (match_operand 1 "" ""))
-	      (use (match_dup 2))
-	      (use (reg:DI 25))
-	      (use (reg:DI 26))
-	      (clobber (reg:DI 27))])]
-  ""
-  "
-{ if (GET_CODE (operands[0]) != MEM)
-    abort ();
-
-  operands[0] = XEXP (operands[0], 0);
-
-  /* Always load AI with argument information, then handle symbolic and
-     indirect call differently.  Load RA and set operands[2] to PV in
-     both cases.  */
-
-  emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
-  if (GET_CODE (operands[0]) == SYMBOL_REF)
-    {
-      extern char *savealloc ();
-      char *linksym, *symbol = XSTR (operands[0], 0);
-      rtx linkage;
-
-      if (*symbol == '*')
-	symbol++;
-      linksym = savealloc (strlen (symbol) + 6);
-
-      alpha_need_linkage (symbol, 0);
-
-      linksym[0] = '$';
-      strcpy (linksym+1, symbol);
-      strcat (linksym, \"..lk\");
-      linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
-
-      emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
-
-      operands[2]
-	= validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
-    }
-  else
-    {
-      emit_move_insn (gen_rtx_REG (Pmode, 26),
-		      gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
-
-      operands[2] = operands[0];
-    }
-
-}")
-
-(define_expand "call_value"
-  [(use (match_operand 0 "" ""))
-   (use (match_operand:DI 1 "" ""))
-   (use (match_operand 2 "" ""))
-   (use (match_operand 3 "" ""))
-   (use (match_operand 4 "" ""))]
-  ""
-  "
-{ if (TARGET_WINDOWS_NT)
-    emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
-  else if (TARGET_OPEN_VMS)
-    emit_call_insn (gen_call_value_vms (operands[0], operands[1],
-					operands[3]));
-  else
-    emit_call_insn (gen_call_value_osf (operands[0], operands[1],
-					operands[2]));
-  DONE;
-}")
-
-(define_expand "call_value_osf"
-  [(parallel [(set (match_operand 0 "" "")
-		   (call (mem:DI (match_operand 1 "" ""))
-			 (match_operand 2 "" "")))
-	      (clobber (reg:DI 27))
-	      (clobber (reg:DI 26))])]
-  ""
-  "
-{ if (GET_CODE (operands[1]) != MEM)
-    abort ();
-
-  operands[1] = XEXP (operands[1], 0);
-
-  if (GET_CODE (operands[1]) != SYMBOL_REF
-      && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
-    {
-      rtx tem = gen_rtx_REG (DImode, 27);
-      emit_move_insn (tem, operands[1]);
-      operands[1] = tem;
-    }
-}")
-
-(define_expand "call_value_nt"
-  [(parallel [(set (match_operand 0 "" "")
-		   (call (mem:DI (match_operand 1 "" ""))
-			 (match_operand 2 "" "")))
-	      (clobber (reg:DI 26))])]
-  ""
-  "
-{ if (GET_CODE (operands[1]) != MEM)
-    abort ();
-
-  operands[1] = XEXP (operands[1], 0);
-  if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
-    operands[1] = force_reg (DImode, operands[1]);
-}")
-
-(define_expand "call_value_vms"
-  [(parallel [(set (match_operand 0 "" "")
-		   (call (mem:DI (match_operand:DI 1 "" ""))
-			 (match_operand 2 "" "")))
-	      (use (match_dup 3))
-	      (use (reg:DI 25))
-	      (use (reg:DI 26))
-	      (clobber (reg:DI 27))])]
-  ""
-  "
-{ if (GET_CODE (operands[1]) != MEM)
-    abort ();
-
-  operands[1] = XEXP (operands[1], 0);
-
-  /* Always load AI with argument information, then handle symbolic and
-     indirect call differently.  Load RA and set operands[3] to PV in
-     both cases.  */
-
-  emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
-  if (GET_CODE (operands[1]) == SYMBOL_REF)
-    {
-      extern char *savealloc ();
-      char *linksym, *symbol = XSTR (operands[1], 0);
-      rtx linkage;
-
-      if (*symbol == '*')
-	symbol++;
-      linksym = savealloc (strlen (symbol) + 6);
-
-      alpha_need_linkage (symbol, 0);
-      linksym[0] = '$';
-      strcpy (linksym+1, symbol);
-      strcat (linksym, \"..lk\");
-      linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
-
-      emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
-
-      operands[3]
-	= validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
-    }
-  else
-    {
-      emit_move_insn (gen_rtx_REG (Pmode, 26),
-		      gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
-
-      operands[3] = operands[1];
-    }
-}")
-
-(define_insn ""
-  [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
-	 (match_operand 1 "" ""))
-   (clobber (reg:DI 27))
-   (clobber (reg:DI 26))]
-  "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
-  "@
-   jsr $26,($27),0\;ldgp $29,0($26)
-   bsr $26,$%0..ng
-   jsr $26,%0\;ldgp $29,0($26)"
-  [(set_attr "type" "jsr")
-   (set_attr "length" "12,*,16")])
-      
-(define_insn ""
-  [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
-	 (match_operand 1 "" ""))
-   (clobber (reg:DI 26))]
-  "TARGET_WINDOWS_NT"
-  "@
-   jsr $26,(%0)
-   bsr $26,%0
-   jsr $26,%0"
-  [(set_attr "type" "jsr")
-   (set_attr "length" "*,*,12")])
-      
-(define_insn ""
-  [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
-	 (match_operand 1 "" ""))
-   (use (match_operand:DI 2 "general_operand" "r,m"))
-   (use (reg:DI 25))
-   (use (reg:DI 26))
-   (clobber (reg:DI 27))]
-  "TARGET_OPEN_VMS"
-  "@
-   bis %2,%2,$27\;jsr $26,0\;ldq $27,0($29)
-   ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
-  [(set_attr "type" "jsr")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand 0 "register_operand" "=rf,rf,rf")
-	(call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
-	      (match_operand 2 "" "")))
-   (clobber (reg:DI 27))
-   (clobber (reg:DI 26))]
-  "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
-  "@
-   jsr $26,($27),0\;ldgp $29,0($26)
-   bsr $26,$%1..ng
-   jsr $26,%1\;ldgp $29,0($26)"
-  [(set_attr "type" "jsr")
-   (set_attr "length" "12,*,16")])
-
-(define_insn ""
-  [(set (match_operand 0 "register_operand" "=rf,rf,rf")
-	(call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
-	      (match_operand 2 "" "")))
-   (clobber (reg:DI 26))]
-  "TARGET_WINDOWS_NT"
-  "@
-   jsr $26,(%1)
-   bsr $26,%1
-   jsr $26,%1"
-  [(set_attr "type" "jsr")
-   (set_attr "length" "*,*,12")])
-
-(define_insn ""
-  [(set (match_operand 0 "register_operand" "")
-	(call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
-	      (match_operand 2 "" "")))
-   (use (match_operand:DI 3 "general_operand" "r,m"))
-   (use (reg:DI 25))
-   (use (reg:DI 26))
-   (clobber (reg:DI 27))]
-  "TARGET_OPEN_VMS"
-  "@
-   bis %3,%3,$27\;jsr $26,0\;ldq $27,0($29)
-   ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
-  [(set_attr "type" "jsr")
-   (set_attr "length" "12,16")])
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 1)]
-  ""
-  ""
-  [(set_attr "length" "0")])
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "br $31,%l0"
-  [(set_attr "type" "ibr")])
-
-(define_insn "return"
-  [(return)]
-  "direct_return ()"
-  "ret $31,($26),1"
-  [(set_attr "type" "ibr")])
-
-;; Use a different pattern for functions which have non-trivial
-;; epilogues so as not to confuse jump and reorg.
-(define_insn "return_internal"
-  [(use (reg:DI 26))
-   (return)]
-  ""
-  "ret $31,($26),1"
-  [(set_attr "type" "ibr")])
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
-  ""
-  "jmp $31,(%0),0"
-  [(set_attr "type" "ibr")])
-
-(define_expand "tablejump"
-  [(use (match_operand:SI 0 "register_operand" ""))
-   (use (match_operand:SI 1 "" ""))]
-  ""
-  "
-{
-  if (TARGET_WINDOWS_NT)
-    emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
-  else if (TARGET_OPEN_VMS)
-    emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
-  else
-    emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
-
-  DONE;
-}")
-
-(define_expand "tablejump_osf"
-  [(set (match_dup 3)
-	(sign_extend:DI (match_operand:SI 0 "register_operand" "")))
-   (parallel [(set (pc)
-		   (plus:DI (match_dup 3)
-			    (label_ref:DI (match_operand 1 "" ""))))
-	      (clobber (match_scratch:DI 2 "=r"))])]
-  ""
-  "
-{ operands[3] = gen_reg_rtx (DImode); }")
-
-(define_expand "tablejump_nt"
-  [(set (match_dup 3)
-	(sign_extend:DI (match_operand:SI 0 "register_operand" "")))
-   (parallel [(set (pc)
-		   (match_dup 3))
-	      (use (label_ref (match_operand 1 "" "")))])]
-  ""
-  "
-{ operands[3] = gen_reg_rtx (DImode); }")
-
-;;
-;; tablejump, openVMS way
-;; op 0: offset
-;; op 1: label preceding jump-table
-;;
-(define_expand "tablejump_vms"
-  [(set (match_dup 2)
-      (match_operand:DI 0 "register_operand" ""))
-        (set (pc)
-	(plus:DI (match_dup 2)
-		(label_ref:DI (match_operand 1 "" ""))))]
-  ""
-  "
-{ operands[2] = gen_reg_rtx (DImode); }")
-
-(define_insn ""
-  [(set (pc)
-	(plus:DI (match_operand:DI 0 "register_operand" "r")
-		 (label_ref:DI (match_operand 1 "" ""))))
-   (clobber (match_scratch:DI 2 "=r"))]
-  "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
-   && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
-   && PREV_INSN (next_active_insn (insn)) == operands[1]"
-  "*
-{ rtx best_label = 0;
-  rtx jump_table_insn = next_active_insn (operands[1]);
-
-  if (GET_CODE (jump_table_insn) == JUMP_INSN
-      && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
-    {
-      rtx jump_table = PATTERN (jump_table_insn);
-      int n_labels = XVECLEN (jump_table, 1);
-      int best_count = -1;
-      int i, j;
-
-      for (i = 0; i < n_labels; i++)
-	{
-	  int count = 1;
-
-	  for (j = i + 1; j < n_labels; j++)
-	    if (XEXP (XVECEXP (jump_table, 1, i), 0)
-		== XEXP (XVECEXP (jump_table, 1, j), 0))
-	      count++;
-
-	  if (count > best_count)
-	    best_count = count, best_label = XVECEXP (jump_table, 1, i);
-	}
-    }
-
-  if (best_label)
-    {
-      operands[3] = best_label;
-      return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
-    }
-  else
-    return \"addq %0,$29,%2\;jmp $31,(%2),0\";
-}"
-  [(set_attr "type" "ibr")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (pc)
-	(match_operand:DI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
-   && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
-   && PREV_INSN (next_active_insn (insn)) == operands[1]"
-  "*
-{ rtx best_label = 0;
-  rtx jump_table_insn = next_active_insn (operands[1]);
-
-  if (GET_CODE (jump_table_insn) == JUMP_INSN
-      && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
-    {
-      rtx jump_table = PATTERN (jump_table_insn);
-      int n_labels = XVECLEN (jump_table, 1);
-      int best_count = -1;
-      int i, j;
-
-      for (i = 0; i < n_labels; i++)
-	{
-	  int count = 1;
-
-	  for (j = i + 1; j < n_labels; j++)
-	    if (XEXP (XVECEXP (jump_table, 1, i), 0)
-		== XEXP (XVECEXP (jump_table, 1, j), 0))
-	      count++;
-
-	  if (count > best_count)
-	    best_count = count, best_label = XVECEXP (jump_table, 1, i);
-	}
-    }
-
-  if (best_label)
-    {
-      operands[2] = best_label;
-      return \"jmp $31,(%0),%2\";
-    }
-  else
-    return \"jmp $31,(%0),0\";
-}"
-  [(set_attr "type" "ibr")])
-
-;;
-;; op 0 is table offset
-;; op 1 is table label
-;;
-
-(define_insn ""
-  [(set (pc)
-	(plus:DI (match_operand 0 "register_operand" "r")
-		(label_ref (match_operand 1 "" ""))))]
-  "TARGET_OPEN_VMS"
-  "jmp $31,(%0),0"
-  [(set_attr "type" "ibr")])
-
-;; Cache flush.  Used by INITIALIZE_TRAMPOLINE.  0x86 is PAL_imb, but we don't
-;; want to have to include pal.h in our .s file.
-;;
-;; Technically the type for call_pal is jsr, but we use that for determining
-;; if we need a GP.  Use ibr instead since it has the same EV5 scheduling
-;; characteristics.
-(define_insn "imb"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "call_pal 0x86"
-  [(set_attr "type" "ibr")])
-
-;; Finally, we have the basic data motion insns.  The byte and word insns
-;; are done via define_expand.  Start with the floating-point insns, since
-;; they are simpler.
-
-(define_insn ""
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
-	(match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
-  "! TARGET_CIX
-   && (register_operand (operands[0], SFmode)
-       || reg_or_fp0_operand (operands[1], SFmode))"
-  "@
-   bis %r1,%r1,%0
-   ldl %0,%1
-   stl %r1,%0
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0
-   ld%, %0,%1
-   st%, %R1,%0"
-  [(set_attr "type" "ilog,ild,ist,fcpys,fcpys,fld,fst")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m,f,*r")
-	(match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG,r,*f"))]
-  "TARGET_CIX
-   && (register_operand (operands[0], SFmode)
-       || reg_or_fp0_operand (operands[1], SFmode))"
-  "@
-   bis %r1,%r1,%0
-   ldl %0,%1
-   stl %r1,%0
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0
-   ld%, %0,%1
-   st%, %R1,%0
-   itofs %1,%0
-   ftois %1,%0"
-  [(set_attr "type" "ilog,ild,ist,fcpys,fcpys,fld,fst,itof,ftoi")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
-	(match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
-  "! TARGET_CIX
-   && (register_operand (operands[0], DFmode)
-       || reg_or_fp0_operand (operands[1], DFmode))"
-  "@
-   bis %r1,%r1,%0
-   ldq %0,%1
-   stq %r1,%0
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0
-   ld%- %0,%1
-   st%- %R1,%0"
-  [(set_attr "type" "ilog,ild,ist,fcpys,fcpys,fld,fst")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m,f,*r")
-	(match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG,r,*f"))]
-  "TARGET_CIX
-   && (register_operand (operands[0], DFmode)
-       || reg_or_fp0_operand (operands[1], DFmode))"
-  "@
-   bis %r1,%r1,%0
-   ldq %0,%1
-   stq %r1,%0
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0
-   ld%- %0,%1
-   st%- %R1,%0
-   itoft %1,%0
-   ftoit %1,%0"
-  [(set_attr "type" "ilog,ild,ist,fcpys,fcpys,fld,fst,itof,ftoi")])
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM
-      && ! reg_or_fp0_operand (operands[1], SFmode))
-    operands[1] = force_reg (SFmode, operands[1]);
-}")
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM
-      && ! reg_or_fp0_operand (operands[1], DFmode))
-    operands[1] = force_reg (DFmode, operands[1]);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m")
-	(match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG"))]
-  "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_CIX
-   && (register_operand (operands[0], SImode)
-       || reg_or_0_operand (operands[1], SImode))"
-  "@
-   bis %1,%1,%0
-   bis $31,$31,%0
-   bis $31,%1,%0
-   lda %0,%1
-   ldah %0,%h1
-   ldl %0,%1
-   stl %r1,%0
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0
-   ld%, %0,%1
-   st%, %R1,%0"
-  [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ild,ist,fcpys,fcpys,fld,fst")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m,r,*f")
-	(match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG,f,*r"))]
-  "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_CIX
-   && (register_operand (operands[0], SImode)
-       || reg_or_0_operand (operands[1], SImode))"
-  "@
-   bis %1,%1,%0
-   bis $31,$31,%0
-   bis $31,%1,%0
-   lda %0,%1
-   ldah %0,%h1
-   ldl %0,%1
-   stl %r1,%0
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0
-   ld%, %0,%1
-   st%, %R1,%0
-   ftois %1,%0
-   itofs %1,%0"
-  [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ild,ist,fcpys,fcpys,fld,fst,ftoi,itof")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,f,f,f,m")
-	(match_operand:SI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,m,fG"))]
-  "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
-    && (register_operand (operands[0], SImode)
-        || reg_or_0_operand (operands[1], SImode))"
-  "@
-   bis %1,%1,%0
-   bis $31,$31,%0
-   bis $31,%1,%0
-   lda %0,%1
-   ldah %0,%h1
-   lda %0,%1
-   ldl %0,%1
-   stl %r1,%0
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0
-   ld%, %0,%1
-   st%, %R1,%0"
-  [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ldsym,ild,ist,fcpys,fcpys,fld,fst")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
-	(match_operand:HI 1 "input_operand" "r,J,I,n,f,J"))]
-  "! TARGET_BWX
-   && (register_operand (operands[0], HImode)
-       || register_operand (operands[1], HImode))"
-  "@
-   bis %1,%1,%0
-   bis $31,$31,%0
-   bis $31,%1,%0
-   lda %0,%L1
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0"
-  [(set_attr "type" "ilog,ilog,ilog,iadd,fcpys,fcpys")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f")
-	(match_operand:HI 1 "input_operand" "r,J,I,n,m,rJ,f,J"))]
-  "TARGET_BWX
-   && (register_operand (operands[0], HImode)
-       || reg_or_0_operand (operands[1], HImode))"
-  "@
-   bis %1,%1,%0
-   bis $31,$31,%0
-   bis $31,%1,%0
-   lda %0,%L1
-   ldwu %0,%1
-   stw %r1,%0
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0"
-  [(set_attr "type" "ilog,ilog,ilog,iadd,ild,ist,fcpys,fcpys")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
-	(match_operand:QI 1 "input_operand" "r,J,I,n,f,J"))]
-  "! TARGET_BWX
-   && (register_operand (operands[0], QImode)
-       || register_operand (operands[1], QImode))"
-  "@
-   bis %1,%1,%0
-   bis $31,$31,%0
-   bis $31,%1,%0
-   lda %0,%L1
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0"
-  [(set_attr "type" "ilog,ilog,ilog,iadd,fcpys,fcpys")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f")
-	(match_operand:QI 1 "input_operand" "r,J,I,n,m,rJ,f,J"))]
-  "TARGET_BWX
-   && (register_operand (operands[0], QImode)
-       || reg_or_0_operand (operands[1], QImode))"
-  "@
-   bis %1,%1,%0
-   bis $31,$31,%0
-   bis $31,%1,%0
-   lda %0,%L1
-   ldbu %0,%1
-   stb %r1,%0
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0"
-  [(set_attr "type" "ilog,ilog,ilog,iadd,ild,ist,fcpys,fcpys")])
-
-;; We do two major things here: handle mem->mem and construct long
-;; constants.
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM
-      && ! reg_or_0_operand (operands[1], SImode))
-    operands[1] = force_reg (SImode, operands[1]);
-
-  if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
-    ;
-  else if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      operands[1]
-	= alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
-      if (rtx_equal_p (operands[0], operands[1]))
-	DONE;
-    }
-}")
-
-;; Split a load of a large constant into the appropriate two-insn
-;; sequence.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operand:SI 1 "const_int_operand" ""))]
-  "! add_operand (operands[1], SImode)"
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
-  "
-{ rtx tem
-    = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
-
-  if (tem == operands[0])
-    DONE;
-  else
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q")
-	(match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG"))]
-  "! TARGET_CIX
-   && (register_operand (operands[0], DImode)
-       || reg_or_0_operand (operands[1], DImode))"
-  "@
-   bis %1,%1,%0
-   bis $31,$31,%0
-   bis $31,%1,%0
-   lda %0,%1
-   ldah %0,%h1
-   lda %0,%1
-   ldq%A1 %0,%1
-   stq%A0 %r1,%0
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0
-   ldt %0,%1
-   stt %R1,%0"
-  [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ldsym,ild,ist,fcpys,fcpys,fld,fst")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q,r,*f")
-	(match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG,f,*r"))]
-  "TARGET_CIX
-   && (register_operand (operands[0], DImode)
-       || reg_or_0_operand (operands[1], DImode))"
-  "@
-   bis %1,%1,%0
-   bis $31,$31,%0
-   bis $31,%1,%0
-   lda %0,%1
-   ldah %0,%h1
-   lda %0,%1
-   ldq%A1 %0,%1
-   stq%A0 %r1,%0
-   cpys %1,%1,%0
-   cpys $f31,$f31,%0
-   ldt %0,%1
-   stt %R1,%0
-   ftoit %1,%0
-   itoft %1,%0"
-  [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ldsym,ild,ist,fcpys,fcpys,fld,fst,ftoi,itof")])
-
-;; We do three major things here: handle mem->mem, put 64-bit constants in
-;; memory, and construct long 32-bit constants.
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  rtx tem;
-
-  if (GET_CODE (operands[0]) == MEM
-      && ! reg_or_0_operand (operands[1], DImode))
-    operands[1] = force_reg (DImode, operands[1]);
-
-  if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
-    ;
-  else if (GET_CODE (operands[1]) == CONST_INT
-	   && (tem = alpha_emit_set_const (operands[0], DImode,
-					   INTVAL (operands[1]), 3)) != 0)
-    {
-      if (rtx_equal_p (tem, operands[0]))
-	DONE;
-      else
-	operands[1] = tem;
-    }
-  else if (CONSTANT_P (operands[1]))
-    {
-      if (TARGET_BUILD_CONSTANTS)
-	{
-	  HOST_WIDE_INT i0, i1;
-
-	  if (GET_CODE (operands[1]) == CONST_INT)
-	    {
-	      i0 = INTVAL (operands[1]);
-	      i1 = -(i0 < 0);
-	    }
-	  else if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	    {
-#if HOST_BITS_PER_WIDE_INT >= 64
-	      i0 = CONST_DOUBLE_LOW (operands[1]);
-	      i1 = -(i0 < 0);
-#else
-	      i0 = CONST_DOUBLE_LOW (operands[1]);
-	      i1 = CONST_DOUBLE_HIGH (operands[1]);
-#endif
-	    }
-	  else
-	    abort();
-	  
-          tem = alpha_emit_set_long_const (operands[0], i0, i1);
-          if (rtx_equal_p (tem, operands[0]))
-	    DONE;
-          else
-	    operands[1] = tem;
-	}
-      else
-	{
-	  operands[1] = force_const_mem (DImode, operands[1]);
-	  if (reload_in_progress)
-	    {
-	      emit_move_insn (operands[0], XEXP (operands[1], 0));
-	      operands[1] = copy_rtx (operands[1]);
-	      XEXP (operands[1], 0) = operands[0];
-	    }
-	  else
-	    operands[1] = validize_mem (operands[1]);
-	}
-    }
-  else
-    abort ();
-}")
-
-;; Split a load of a large constant into the appropriate two-insn
-;; sequence.
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_operand:DI 1 "const_int_operand" ""))]
-  "! add_operand (operands[1], DImode)"
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
-  "
-{ rtx tem
-    = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
-
-  if (tem == operands[0])
-    DONE;
-  else
-    FAIL;
-}")
-
-;; These are the partial-word cases.
-;;
-;; First we have the code to load an aligned word.  Operand 0 is the register
-;; in which to place the result.  It's mode is QImode or HImode.  Operand 1
-;; is an SImode MEM at the low-order byte of the proper word.  Operand 2 is the
-;; number of bits within the word that the value is.  Operand 3 is an SImode
-;; scratch register.  If operand 0 is a hard register, operand 3 may be the
-;; same register.  It is allowed to conflict with operand 1 as well.
-
-(define_expand "aligned_loadqi"
-  [(set (match_operand:SI 3 "register_operand" "")
-	(match_operand:SI 1 "memory_operand" ""))
-   (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
-	(zero_extract:DI (subreg:DI (match_dup 3) 0)
-			 (const_int 8)
-			 (match_operand:DI 2 "const_int_operand" "")))]
-	 
-  ""
-  "")
-  
-(define_expand "aligned_loadhi"
-  [(set (match_operand:SI 3 "register_operand" "")
-	(match_operand:SI 1 "memory_operand" ""))
-   (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
-	(zero_extract:DI (subreg:DI (match_dup 3) 0)
-			 (const_int 16)
-			 (match_operand:DI 2 "const_int_operand" "")))]
-	 
-  ""
-  "")
-  
-;; Similar for unaligned loads, where we use the sequence from the
-;; Alpha Architecture manual.
-;;
-;; Operand 1 is the address.  Operands 2 and 3 are temporaries, where
-;; operand 3 can overlap the input and output registers.
-
-(define_expand "unaligned_loadqi"
-  [(set (match_operand:DI 2 "register_operand" "")
-	(mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
-			(const_int -8))))
-   (set (match_operand:DI 3 "register_operand" "")
-	(match_dup 1))
-   (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
-	(zero_extract:DI (match_dup 2)
-			 (const_int 8)
-			 (ashift:DI (match_dup 3) (const_int 3))))]
-  ""
-  "")
-
-(define_expand "unaligned_loadhi"
-  [(set (match_operand:DI 2 "register_operand" "")
-	(mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
-			(const_int -8))))
-   (set (match_operand:DI 3 "register_operand" "")
-	(match_dup 1))
-   (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
-	(zero_extract:DI (match_dup 2)
-			 (const_int 16)
-			 (ashift:DI (match_dup 3) (const_int 3))))]
-  ""
-  "")
-
-;; Storing an aligned byte or word requires two temporaries.  Operand 0 is the
-;; aligned SImode MEM.  Operand 1 is the register containing the 
-;; byte or word to store.  Operand 2 is the number of bits within the word that
-;; the value should be placed.  Operands 3 and 4 are SImode temporaries.
-
-(define_expand "aligned_store"
-  [(set (match_operand:SI 3 "register_operand" "")
-	(match_operand:SI 0 "memory_operand" ""))
-   (set (subreg:DI (match_dup 3) 0)
-	(and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
-   (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
-	(ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
-		   (match_operand:DI 2 "const_int_operand" "")))
-   (set (subreg:DI (match_dup 4) 0)
-	(ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
-   (set (match_dup 0) (match_dup 4))]
-  ""
-  "
-{ operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
-			    << INTVAL (operands[2])));
-}")
-
-;; For the unaligned byte and halfword cases, we use code similar to that
-;; in the ;; Architecture book, but reordered to lower the number of registers
-;; required.  Operand 0 is the address.  Operand 1 is the data to store.
-;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
-;; be the same temporary, if desired.  If the address is in a register,
-;; operand 2 can be that register.
-
-(define_expand "unaligned_storeqi"
-  [(set (match_operand:DI 3 "register_operand" "")
-	(mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
-			(const_int -8))))
-   (set (match_operand:DI 2 "register_operand" "")
-	(match_dup 0))
-   (set (match_dup 3)
-	(and:DI (not:DI (ashift:DI (const_int 255)
-				   (ashift:DI (match_dup 2) (const_int 3))))
-		(match_dup 3)))
-   (set (match_operand:DI 4 "register_operand" "")
-	(ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
-		   (ashift:DI (match_dup 2) (const_int 3))))
-   (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
-   (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
-	(match_dup 4))]
-  ""
-  "")
-
-(define_expand "unaligned_storehi"
-  [(set (match_operand:DI 3 "register_operand" "")
-	(mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
-			(const_int -8))))
-   (set (match_operand:DI 2 "register_operand" "")
-	(match_dup 0))
-   (set (match_dup 3)
-	(and:DI (not:DI (ashift:DI (const_int 65535)
-				   (ashift:DI (match_dup 2) (const_int 3))))
-		(match_dup 3)))
-   (set (match_operand:DI 4 "register_operand" "")
-	(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
-		   (ashift:DI (match_dup 2) (const_int 3))))
-   (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
-   (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
-	(match_dup 4))]
-  ""
-  "")
-
-;; Here are the define_expand's for QI and HI moves that use the above
-;; patterns.  We have the normal sets, plus the ones that need scratch
-;; registers for reload.
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_BWX)
-    {
-      if (GET_CODE (operands[0]) == MEM
-	  && ! reg_or_0_operand (operands[1], QImode))
-	operands[1] = force_reg (QImode, operands[1]);
-
-      if (GET_CODE (operands[1]) == CONST_INT
-	       && ! input_operand (operands[1], QImode))
-	{
-	  operands[1] = alpha_emit_set_const (operands[0], QImode,
-					      INTVAL (operands[1]), 3);
-
-	  if (rtx_equal_p (operands[0], operands[1]))
-	    DONE;
-	}
-
-      goto def;
-    }
-
-  /* If the output is not a register, the input must be.  */
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (QImode, operands[1]);
-
-  /* Handle four memory cases, unaligned and aligned for either the input
-     or the output.  The only case where we can be called during reload is
-     for aligned loads; all other cases require temporaries.  */
-
-  if (GET_CODE (operands[1]) == MEM
-      || (GET_CODE (operands[1]) == SUBREG
-	  && GET_CODE (SUBREG_REG (operands[1])) == MEM)
-      || (reload_in_progress && GET_CODE (operands[1]) == REG
-	  && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
-      || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
-	  && GET_CODE (SUBREG_REG (operands[1])) == REG
-	  && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
-    {
-      if (aligned_memory_operand (operands[1], QImode))
-	{
-	  rtx aligned_mem, bitnum;
-	  rtx scratch = (reload_in_progress
-			 ? gen_rtx_REG (SImode, REGNO (operands[0]))
-			 : gen_reg_rtx (SImode));
-
-	  get_aligned_mem (operands[1], &aligned_mem, &bitnum);
-
-	  emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
-					 scratch));
-	}
-      else
-	{
-	  /* Don't pass these as parameters since that makes the generated
-	     code depend on parameter evaluation order which will cause
-	     bootstrap failures.  */
-
-	  rtx temp1 = gen_reg_rtx (DImode);
-	  rtx temp2 = gen_reg_rtx (DImode);
-	  rtx seq
-	    = gen_unaligned_loadqi (operands[0],
-				    get_unaligned_address (operands[1], 0),
-				    temp1, temp2);
-
-	  alpha_set_memflags (seq, operands[1]);
-	  emit_insn (seq);
-	}
-
-      DONE;
-    }
-
-  else if (GET_CODE (operands[0]) == MEM
-	   || (GET_CODE (operands[0]) == SUBREG 
-	       && GET_CODE (SUBREG_REG (operands[0])) == MEM)
-	   || (reload_in_progress && GET_CODE (operands[0]) == REG
-	       && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
-	   || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
-	       && GET_CODE (SUBREG_REG (operands[0])) == REG
-	       && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
-    {
-      if (aligned_memory_operand (operands[0], QImode))
-	{
-	  rtx aligned_mem, bitnum;
-	  rtx temp1 = gen_reg_rtx (SImode);
-	  rtx temp2 = gen_reg_rtx (SImode);
-
-	  get_aligned_mem (operands[0], &aligned_mem, &bitnum);
-
-	  emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
-					temp1, temp2));
-	}
-      else
-	{
-	  rtx temp1 = gen_reg_rtx (DImode);
-	  rtx temp2 = gen_reg_rtx (DImode);
-	  rtx temp3 = gen_reg_rtx (DImode);
-	  rtx seq
-	    = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
-					   operands[1], temp1, temp2, temp3);
-
-	  alpha_set_memflags (seq, operands[0]);
-	  emit_insn (seq);
-	}
-      DONE;
-    }
- def:;
-}")
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_BWX)
-    {
-      if (GET_CODE (operands[0]) == MEM
-	  && ! reg_or_0_operand (operands[1], HImode))
-	operands[1] = force_reg (HImode, operands[1]);
-
-      if (GET_CODE (operands[1]) == CONST_INT
-	       && ! input_operand (operands[1], HImode))
-	{
-	  operands[1] = alpha_emit_set_const (operands[0], HImode,
-					      INTVAL (operands[1]), 3);
-
-	  if (rtx_equal_p (operands[0], operands[1]))
-	    DONE;
-	}
-
-      goto def;
-    }
-
-  /* If the output is not a register, the input must be.  */
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (HImode, operands[1]);
-
-  /* Handle four memory cases, unaligned and aligned for either the input
-     or the output.  The only case where we can be called during reload is
-     for aligned loads; all other cases require temporaries.  */
-
-  if (GET_CODE (operands[1]) == MEM
-      || (GET_CODE (operands[1]) == SUBREG
-	  && GET_CODE (SUBREG_REG (operands[1])) == MEM)
-      || (reload_in_progress && GET_CODE (operands[1]) == REG
-	  && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
-      || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
-	  && GET_CODE (SUBREG_REG (operands[1])) == REG
-	  && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
-    {
-      if (aligned_memory_operand (operands[1], HImode))
-	{
-	  rtx aligned_mem, bitnum;
-	  rtx scratch = (reload_in_progress
-			 ? gen_rtx_REG (SImode, REGNO (operands[0]))
-			 : gen_reg_rtx (SImode));
-
-	  get_aligned_mem (operands[1], &aligned_mem, &bitnum);
-
-	  emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
-					 scratch));
-	}
-      else
-	{
-	  /* Don't pass these as parameters since that makes the generated
-	     code depend on parameter evaluation order which will cause
-	     bootstrap failures.  */
-
-	  rtx temp1 = gen_reg_rtx (DImode);
-	  rtx temp2 = gen_reg_rtx (DImode);
-	  rtx seq
-	    = gen_unaligned_loadhi (operands[0],
-				    get_unaligned_address (operands[1], 0),
-				    temp1, temp2);
-
-	  alpha_set_memflags (seq, operands[1]);
-	  emit_insn (seq);
-	}
-
-      DONE;
-    }
-
-  else if (GET_CODE (operands[0]) == MEM
-	   || (GET_CODE (operands[0]) == SUBREG 
-	       && GET_CODE (SUBREG_REG (operands[0])) == MEM)
-	   || (reload_in_progress && GET_CODE (operands[0]) == REG
-	       && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
-	   || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
-	       && GET_CODE (SUBREG_REG (operands[0])) == REG
-	       && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
-    {
-      if (aligned_memory_operand (operands[0], HImode))
-	{
-	  rtx aligned_mem, bitnum;
-	  rtx temp1 = gen_reg_rtx (SImode);
-	  rtx temp2 = gen_reg_rtx (SImode);
-
-	  get_aligned_mem (operands[0], &aligned_mem, &bitnum);
-
-	  emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
-					temp1, temp2));
-	}
-      else
-	{
-	  rtx temp1 = gen_reg_rtx (DImode);
-	  rtx temp2 = gen_reg_rtx (DImode);
-	  rtx temp3 = gen_reg_rtx (DImode);
-	  rtx seq
-	    = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
-				     operands[1], temp1, temp2, temp3);
-
-	  alpha_set_memflags (seq, operands[0]);
-	  emit_insn (seq);
-	}
-
-      DONE;
-    }
- def:;
-}")
-
-;; Here are the versions for reload.  Note that in the unaligned cases
-;; we know that the operand must not be a pseudo-register because stack
-;; slots are always aligned references.
-
-(define_expand "reload_inqi"
-  [(parallel [(match_operand:QI 0 "register_operand" "=r")
-	      (match_operand:QI 1 "unaligned_memory_operand" "m")
-	      (match_operand:TI 2 "register_operand" "=&r")])]
-  "! TARGET_BWX"
-  "
-{
-  rtx addr = get_unaligned_address (operands[1], 0);
-
-  /* It is possible that one of the registers we got for operands[2]
-     might coincide with that of operands[0] (which is why we made
-     it TImode).  Pick the other one to use as our scratch.  */
-  rtx scratch = gen_rtx_REG (DImode,
-			     REGNO (operands[0]) == REGNO (operands[2]) 
-			     ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
-
-  rtx seq = gen_unaligned_loadqi (operands[0], addr, scratch,
-				  gen_rtx_REG (DImode, REGNO (operands[0])));
-
-  alpha_set_memflags (seq, operands[1]);
-  emit_insn (seq);
-  DONE;
-}")
-
-(define_expand "reload_inhi"
-  [(parallel [(match_operand:HI 0 "register_operand" "=r")
-	      (match_operand:HI 1 "unaligned_memory_operand" "m")
-	      (match_operand:TI 2 "register_operand" "=&r")])]
-  "! TARGET_BWX"
-  "
-{
-  rtx addr = get_unaligned_address (operands[1], 0);
-
-  /* It is possible that one of the registers we got for operands[2]
-     might coincide with that of operands[0] (which is why we made
-     it TImode).  Pick the other one to use as our scratch.  */
-  rtx scratch = gen_rtx_REG (DImode,
-			     REGNO (operands[0]) == REGNO (operands[2]) 
-			     ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
-
-  rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch,
-				  gen_rtx_REG (DImode, REGNO (operands[0])));
-
-  alpha_set_memflags (seq, operands[1]);
-  emit_insn (seq);
-  DONE;
-}")
-
-(define_expand "reload_outqi"
-  [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
-	      (match_operand:QI 1 "register_operand" "r")
-	      (match_operand:TI 2 "register_operand" "=&r")])]
-  "! TARGET_BWX"
-  "
-{
-  if (aligned_memory_operand (operands[0], QImode))
-    {
-      rtx aligned_mem, bitnum;
-
-      get_aligned_mem (operands[0], &aligned_mem, &bitnum);
-
-      emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
-				    gen_rtx_REG (SImode, REGNO (operands[2])),
-				    gen_rtx_REG (SImode,
-						 REGNO (operands[2]) + 1)));
-    }
-  else
-    {
-      rtx addr = get_unaligned_address (operands[0], 0);
-      rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
-      rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
-      rtx scratch3 = scratch1;
-      rtx seq;
-
-      if (GET_CODE (addr) == REG)
-	scratch1 = addr;
-
-      seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
-				   scratch2, scratch3);
-      alpha_set_memflags (seq, operands[0]);
-      emit_insn (seq);
-    }
-
-  DONE;
-}")
-
-(define_expand "reload_outhi"
-  [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
-	      (match_operand:HI 1 "register_operand" "r")
-	      (match_operand:TI 2 "register_operand" "=&r")])]
-  "! TARGET_BWX"
-  "
-{
-  if (aligned_memory_operand (operands[0], HImode))
-    {
-      rtx aligned_mem, bitnum;
-
-      get_aligned_mem (operands[0], &aligned_mem, &bitnum);
-
-      emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
-				    gen_rtx_REG (SImode, REGNO (operands[2])),
-				    gen_rtx_REG (SImode,
-						 REGNO (operands[2]) + 1)));
-    }
-  else
-    {
-      rtx addr = get_unaligned_address (operands[0], 0);
-      rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
-      rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
-      rtx scratch3 = scratch1;
-      rtx seq;
-
-      if (GET_CODE (addr) == REG)
-	scratch1 = addr;
-
-      seq = gen_unaligned_storehi (addr, operands[1], scratch1,
-				   scratch2, scratch3);
-      alpha_set_memflags (seq, operands[0]);
-      emit_insn (seq);
-    }
-
-  DONE;
-}")
-
-;; Bit field extract patterns which use ext[wlq][lh]
-
-(define_expand "extv"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extract:DI (match_operand:QI 1 "memory_operand" "")
-			 (match_operand:DI 2 "immediate_operand" "")
-			 (match_operand:DI 3 "immediate_operand" "")))]
-  ""
-  "
-{
-  /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries.  */
-  if (INTVAL (operands[3]) % 8 != 0
-      || (INTVAL (operands[2]) != 16
-	  && INTVAL (operands[2]) != 32
-	  && INTVAL (operands[2]) != 64))
-    FAIL;
-
-  /* From mips.md: extract_bit_field doesn't verify that our source
-     matches the predicate, so we force it to be a MEM here.  */
-  if (GET_CODE (operands[1]) != MEM)
-    FAIL;
-
-  alpha_expand_unaligned_load (operands[0], operands[1],
-			       INTVAL (operands[2]) / 8,
-			       INTVAL (operands[3]) / 8, 1);
-  DONE;
-}")
-
-(define_expand "extzv"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extract:DI (match_operand:DI 1 "general_operand" "")
-			 (match_operand:DI 2 "immediate_operand" "")
-			 (match_operand:DI 3 "immediate_operand" "")))]
-  ""
-  "
-{
-  /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries.  */
-  if (INTVAL (operands[3]) % 8 != 0
-      || (INTVAL (operands[2]) != 8
-	  && INTVAL (operands[2]) != 16
-	  && INTVAL (operands[2]) != 32
-	  && INTVAL (operands[2]) != 64))
-    FAIL;
-
-  if (GET_CODE (operands[1]) == MEM)
-    {
-      /* Fail 8 bit fields, falling back on a simple byte load.  */
-      if (INTVAL (operands[2]) == 8)
-	FAIL;
-
-      alpha_expand_unaligned_load (operands[0], operands[1],
-			           INTVAL (operands[2]) / 8,
-			           INTVAL (operands[3]) / 8, 0);
-      DONE;
-    }
-}")
-
-(define_expand "insv"
-  [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
-			 (match_operand:DI 1 "immediate_operand" "")
-			 (match_operand:DI 2 "immediate_operand" ""))
-	(match_operand:DI 3 "register_operand" ""))]
-  ""
-  "
-{
-  /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries.  */
-  if (INTVAL (operands[2]) % 8 != 0
-      || (INTVAL (operands[1]) != 16
-	  && INTVAL (operands[1]) != 32
-	  && INTVAL (operands[1]) != 64))
-    FAIL;
-
-  /* From mips.md: store_bit_field doesn't verify that our source
-     matches the predicate, so we force it to be a MEM here.  */
-  if (GET_CODE (operands[0]) != MEM)
-    FAIL;
-
-  alpha_expand_unaligned_store (operands[0], operands[3],
-			        INTVAL (operands[1]) / 8,
-			        INTVAL (operands[2]) / 8);
-  DONE;
-}")
-
-
-
-;; Block move/clear, see alpha.c for more details.
-;; Argument 0 is the destination
-;; Argument 1 is the source
-;; Argument 2 is the length
-;; Argument 3 is the alignment
-
-(define_expand "movstrqi"
-  [(parallel [(set (match_operand:BLK 0 "general_operand" "")
-		   (match_operand:BLK 1 "general_operand" ""))
-	      (use (match_operand:DI 2 "immediate_operand" ""))
-	      (use (match_operand:DI 3 "immediate_operand" ""))])]
-  ""
-  "
-{
-  if (alpha_expand_block_move (operands))
-    DONE;
-  else
-    FAIL;
-}")
-
-(define_expand "clrstrqi"
-  [(parallel [(set (match_operand:BLK 0 "general_operand" "")
-		   (const_int 0))
-	      (use (match_operand:DI 1 "immediate_operand" ""))
-	      (use (match_operand:DI 2 "immediate_operand" ""))])]
-  ""
-  "
-{
-  if (alpha_expand_block_clear (operands))
-    DONE;
-  else
-    FAIL;
-}")
-
-;; Subroutine of stack space allocation.  Perform a stack probe.
-(define_expand "probe_stack"
-  [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
-  ""
-  "
-{
-  operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
-						    INTVAL (operands[0])));
-  MEM_VOLATILE_P (operands[1]) = 1;
-
-  operands[0] = const0_rtx;
-}")
-
-;; This is how we allocate stack space.  If we are allocating a
-;; constant amount of space and we know it is less than 4096
-;; bytes, we need do nothing.
-;;
-;; If it is more than 4096 bytes, we need to probe the stack
-;; periodically. 
-(define_expand "allocate_stack"
-  [(set (reg:DI 30)
-	(plus:DI (reg:DI 30)
-		 (match_operand:DI 1 "reg_or_cint_operand" "")))
-   (set (match_operand:DI 0 "register_operand" "=r")
-	(match_dup 2))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL (operands[1]) < 32768)
-    {
-      if (INTVAL (operands[1]) >= 4096)
-	{
-	  /* We do this the same way as in the prologue and generate explicit
-	     probes.  Then we update the stack by the constant.  */
-
-	  int probed = 4096;
-
-	  emit_insn (gen_probe_stack (GEN_INT (- probed)));
-	  while (probed + 8192 < INTVAL (operands[1]))
-	    emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
-
-	  if (probed + 4096 < INTVAL (operands[1]))
-	    emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
-	}
-
-      operands[1] = GEN_INT (- INTVAL (operands[1]));
-      operands[2] = virtual_stack_dynamic_rtx;
-    }
-  else
-    {
-      rtx out_label = 0;
-      rtx loop_label = gen_label_rtx ();
-      rtx want = gen_reg_rtx (Pmode);
-      rtx tmp = gen_reg_rtx (Pmode);
-      rtx memref;
-
-      emit_insn (gen_subdi3 (want, stack_pointer_rtx,
-			     force_reg (Pmode, operands[1])));
-      emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
-
-      if (GET_CODE (operands[1]) != CONST_INT)
-	{
-	  out_label = gen_label_rtx ();
-	  emit_insn (gen_cmpdi (want, tmp));
-	  emit_jump_insn (gen_bgeu (out_label));
-	}
-
-      emit_label (loop_label);
-      memref = gen_rtx_MEM (DImode, tmp);
-      MEM_VOLATILE_P (memref) = 1;
-      emit_move_insn (memref, const0_rtx);
-      emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
-      emit_insn (gen_cmpdi (tmp, want));
-      emit_jump_insn (gen_bgtu (loop_label));
-      if (obey_regdecls)
-	gen_rtx_USE (VOIDmode, tmp);
-
-      memref = gen_rtx_MEM (DImode, want);
-      MEM_VOLATILE_P (memref) = 1;
-      emit_move_insn (memref, const0_rtx);
-
-      if (out_label)
-	emit_label (out_label);
-
-      emit_move_insn (stack_pointer_rtx, want);
-      emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
-      DONE;
-    }
-}")
-
-;; This is used by alpha_expand_prolog to do the same thing as above,
-;; except we cannot at that time generate new basic blocks, so we hide
-;; the loop in this one insn.
-
-(define_insn "prologue_stack_probe_loop"
-  [(unspec_volatile [(match_operand 0 "register_operand" "r")
-		     (match_operand 1 "register_operand" "r")] 5)]
-  ""
-  "*
-{
-  operands[2] = gen_label_rtx ();
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
-			     CODE_LABEL_NUMBER (operands[2]));
-
-  return \"stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2\";
-}"
-  [(set_attr "length" "16")
-   (set_attr "type" "multi")])
-
-(define_expand "prologue"
-  [(clobber (const_int 0))]
-  ""
-  "alpha_expand_prologue (); DONE;")
-
-(define_insn "init_fp"
-  [(set (match_operand:DI 0 "register_operand" "r")
-        (match_operand:DI 1 "register_operand" "r"))
-   (clobber (mem:BLK (match_operand:DI 2 "register_operand" "r")))]
-  ""
-  "bis %1,%1,%0")
-
-(define_expand "epilogue"
-  [(clobber (const_int 0))]
-  ""
-  "alpha_expand_epilogue (); DONE;")
-
-(define_expand "eh_epilogue"
-  [(use (match_operand:DI 0 "register_operand" "r"))
-   (use (match_operand:DI 1 "register_operand" "r"))
-   (use (match_operand:DI 2 "register_operand" "r"))]
-  "! TARGET_OPEN_VMS"
-  "
-{
-  alpha_eh_epilogue_sp_ofs = operands[1];
-  if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 26)
-    {
-      rtx ra = gen_rtx_REG (Pmode, 26);
-      emit_move_insn (ra, operands[2]);
-      operands[2] = ra;
-    }
-}")
-
-(define_expand "builtin_longjmp"
-  [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
-  "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
-  "
-{
-  /* The elements of the buffer are, in order:  */
-  rtx fp = gen_rtx_MEM (Pmode, operands[0]);
-  rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
-  rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
-  rtx pv = gen_rtx_REG (Pmode, 27);
-
-  /* This bit is the same as expand_builtin_longjmp.  */
-  emit_move_insn (hard_frame_pointer_rtx, fp);
-  emit_move_insn (pv, lab);
-  emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
-  emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
-  emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
-
-  /* Load the label we are jumping through into $27 so that we know
-     where to look for it when we get back to setjmp's function for
-     restoring the gp.  */
-  emit_indirect_jump (pv);
-  DONE;
-}")
-
-(define_insn "builtin_setjmp_receiver"
-  [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
-  "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
-  "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
-  [(set_attr "length" "8")
-   (set_attr "type" "multi")])
-
-(define_insn ""
-  [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
-  "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
-  "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
-  [(set_attr "length" "12")
-   (set_attr "type" "multi")])
-
-(define_insn "exception_receiver"
-  [(unspec_volatile [(const_int 0)] 7)]
-  "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
-  "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
-  [(set_attr "length" "12")
-   (set_attr "type" "multi")])
-
-(define_expand "nonlocal_goto_receiver"
-  [(unspec_volatile [(const_int 0)] 1)
-   (set (reg:DI 27) (mem:DI (reg:DI 29)))
-   (unspec_volatile [(const_int 0)] 1)
-   (use (reg:DI 27))]
-  "TARGET_OPEN_VMS"
-  "")
-
-(define_insn "arg_home"
-  [(unspec [(const_int 0)] 0)
-   (use (reg:DI 1))
-   (use (reg:DI 25))
-   (use (reg:DI 16))
-   (use (reg:DI 17))
-   (use (reg:DI 18))
-   (use (reg:DI 19))
-   (use (reg:DI 20))
-   (use (reg:DI 21))
-   (use (reg:DI 48))
-   (use (reg:DI 49))
-   (use (reg:DI 50))
-   (use (reg:DI 51))
-   (use (reg:DI 52))
-   (use (reg:DI 53))
-   (clobber (mem:BLK (const_int 0)))
-   (clobber (reg:DI 24))
-   (clobber (reg:DI 25))
-   (clobber (reg:DI 0))]
-  "TARGET_OPEN_VMS"
-  "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
-  [(set_attr "length" "16")
-   (set_attr "type" "multi")])
-
-;; Close the trap shadow of preceeding instructions.  This is generated
-;; by alpha_reorg.
-
-(define_insn "trapb"
-  [(unspec_volatile [(const_int 0)] 4)]
-  ""
-  "trapb"
-  [(set_attr "type" "misc")])
-
-;; No-op instructions used by machine-dependant reorg to preserve
-;; alignment for instruction issue.
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-  [(set_attr "type" "ilog")])
-
-(define_insn "fnop"
-  [(const_int 1)]
-  "TARGET_FP"
-  "fnop"
-  [(set_attr "type" "fcpys")])
-
-(define_insn "unop"
-  [(const_int 2)]
-  ""
-  "unop")
-
-(define_insn "realign"
-  [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
-  ""
-  ".align %0 #realign")
-
-;; Peepholes go at the end.
-
-;; Optimize sign-extension of SImode loads.  This shows up in the wake of
-;; reload when converting fp->int.
-;;
-;; ??? What to do now that we actually care about the packing and
-;; alignment of instructions?  Perhaps reload can be enlightened, or
-;; the peephole pass moved up after reload but before sched2?
-;
-;(define_peephole
-;  [(set (match_operand:SI 0 "register_operand" "=r")
-;        (match_operand:SI 1 "memory_operand" "m"))
-;   (set (match_operand:DI 2 "register_operand" "=r")
-;        (sign_extend:DI (match_dup 0)))]
-;  "dead_or_set_p (insn, operands[0])"
-;  "ldl %2,%1")
-;
-;(define_peephole
-;  [(set (match_operand:SI 0 "register_operand" "=r")
-;        (match_operand:SI 1 "hard_fp_register_operand" "f"))
-;   (set (match_operand:DI 2 "register_operand" "=r")
-;        (sign_extend:DI (match_dup 0)))]
-;  "TARGET_CIX && dead_or_set_p (insn, operands[0])"
-;  "ftois %1,%2")
diff --git a/gcc/config/alpha/config-nt.sed b/gcc/config/alpha/config-nt.sed
deleted file mode 100755
index 62a85fb..0000000
--- a/gcc/config/alpha/config-nt.sed
+++ /dev/null
@@ -1,33 +0,0 @@
-/^Makefile/,/^	rm -f config.run/d
-s/rm -f/del/
-s/|| cp/|| copy/
-/^config.status/,/	fi/d
-s/config.status//g
-s/\/dev\/null/NUL/g
-s/$(srcdir)\/c-parse/c-parse/g
-s/$(srcdir)\/c-gperf/c-gperf/g
-/^multilib.h/ s/multilib/not-multilib/
-/^target=/ c\
-target=winnt3.5
-/^xmake_file=/ d
-/^tmake_file=/ d
-/^out_file/ c\
-out_file=config/alpha/alpha.c
-/^out_object_file/ c\
-out_object_file=alpha.obj
-/^md_file/ c\
-md_file=config/alpha/alpha.md
-/^tm_file/ c\
-tm_file=config/alpha/alpha.h config/alpha/winnt.h
-/^build_xm_file/ c\
-build_xm_file=config/alpha/xm-alpha.h config/winnt/xm-winnt.h config/alpha/xm-winnt.h
-/^host_xm_file/ c\
-host_xm_file=config/alpha/xm-alpha.h config/winnt/xm-winnt.h config/alpha/xm-winnt.h
-/^####target/ i\
-CC = cl \
-CLIB = libc.lib kernel32.lib \
-CFLAGS = -Dalpha -DWIN32 -D_WIN32 -D_ALPHA_ -D_M_ALPHA \\\
- -DALMOST_STDC \
-LDFLAGS = -subsystem:console -entry:mainCRTStartup \\\
- -stack:1000000,1000 \
-
diff --git a/gcc/config/alpha/crtbegin.asm b/gcc/config/alpha/crtbegin.asm
deleted file mode 100755
index f954f1a..0000000
--- a/gcc/config/alpha/crtbegin.asm
+++ /dev/null
@@ -1,192 +0,0 @@
- # Copyright (C) 1996, 1998 Free Software Foundation, Inc.
- #  Contributed by Richard Henderson (rth@tamu.edu)
- #
- # This file is free software; you can redistribute it and/or modify it
- # under the terms of the GNU General Public License as published by the
- # Free Software Foundation; either version 2, or (at your option) any
- # later version.
- # 
- # In addition to the permissions in the GNU General Public License, the
- # Free Software Foundation gives you unlimited permission to link the
- # compiled version of this file with other programs, and to distribute
- # those programs without any restriction coming from the use of this
- # file.  (The General Public License restrictions do apply in other
- # respects; for example, they cover modification of the file, and
- # distribution when not linked into another program.)
- # 
- # This file is distributed in the hope that it will be useful, but
- # WITHOUT ANY WARRANTY; without even the implied warranty of
- # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- # General Public License for more details.
- # 
- # You should have received a copy of the GNU General Public License
- # along with this program; see the file COPYING.  If not, write to
- # the Free Software Foundation, 59 Temple Place - Suite 330,
- # Boston, MA 02111-1307, USA.
- # 
- #    As a special exception, if you link this library with files
- #    compiled with GCC to produce an executable, this does not cause
- #    the resulting executable to be covered by the GNU General Public License.
- #    This exception does not however invalidate any other reasons why
- #    the executable file might be covered by the GNU General Public License.
-
- #
- # Heads of the constructor/destructor lists.
- #
-
- # The __*TOR_LIST__ symbols are not global because when this file is used
- # in a shared library, we do not want the symbol to fall over to the
- # application's lists.
-
-.section .ctors,"aw"
-
-	.align 3
-__CTOR_LIST__:
-	.quad -1
-
-.section .dtors,"aw"
-
-	.align 3
-__DTOR_LIST__:
-	.quad -1
-
-.section .eh_frame,"aw"
-__EH_FRAME_BEGIN__:
-
- #
- # Fragment of the ELF _fini routine that invokes our dtor cleanup.
- #
-
-.section .fini,"ax"
-
-	# Since the bits of the _fini function are spread across many
-	# object files, each potentially with its own GP, we must
-	# assume we need to load ours.  Further, our .fini section
-	# can easily be more than 4MB away from our .text bits so we
-	# can't use bsr.
-
-	br      $29,1f
-1:	ldgp    $29,0($29)
-	jsr     $26,__do_global_dtors_aux
-
-	# Ideally this call would go in crtend.o, except that we can't
-	# get hold of __EH_FRAME_BEGIN__ there.
-
-	jsr	$26,__do_frame_takedown
-
-	# Must match the alignment we got from crti.o else we get
-	# zero-filled holes in our _fini function and then SIGILL.
-	.align 3
-
- #
- # Fragment of the ELF _init routine that sets up the frame info.
- #
-
-.section .init,"ax"
-       br      $29,1f
-1:     ldgp    $29,0($29)
-       jsr     $26,__do_frame_setup
-       .align 3
-
- #
- # Invoke our destructors in order.
- #
-
-.data
-
- # Support recursive calls to exit.
-$ptr:	.quad	__DTOR_LIST__
-
-.text
-
-	.align 3
-	.ent __do_global_dtors_aux
-
-__do_global_dtors_aux:
-	lda     $30,-16($30)
-	.frame  $30,16,$26,0
-	stq	$9,8($30)
-	stq     $26,0($30)
-	.mask   0x4000200,-16
-	.prologue 0
-
-	lda     $9,$ptr
-	br      1f
-0:	stq	$1,0($9)
-	jsr     $26,($27)
-1:	ldq	$1,0($9)
-	ldq     $27,8($1)
-	addq    $1,8,$1
-	bne     $27,0b
-
-	ldq     $26,0($30)
-	ldq	$9,8($30)
-	lda     $30,16($30)
-	ret
-
-	.end __do_global_dtors_aux
-
- #
- # Install our frame info.
- #
-
- # ??? How can we rationally keep this size correct?
-
-.section .bss
-	.type $object,@object
-	.align 3
-$object:
-	.zero 48
-	.size $object, 48
-
-.text 
-
-	.align 3
-	.ent __do_frame_setup
-
-__do_frame_setup:
-	ldgp	$29,0($27)
-	lda     $30,-16($30)
-	.frame  $30,16,$26,0
-	stq     $26,0($30)
-	.mask   0x4000000,-16
-	.prologue 1
-
-	lda	$1,__register_frame_info
-	beq	$1,0f
-	lda	$16,__EH_FRAME_BEGIN__
-	lda	$17,$object
-	jsr	$26,__register_frame_info
-	ldq     $26,0($30)
-0:	lda     $30,16($30)
-	ret
-
-	.end __do_frame_setup
-
- #
- # Remove our frame info.
- #
-
-	.align 3
-	.ent __do_frame_takedown
-
-__do_frame_takedown:
-	ldgp	$29,0($27)
-	lda     $30,-16($30)
-	.frame  $30,16,$26,0
-	stq     $26,0($30)
-	.mask   0x4000000,-16
-	.prologue 1
-
-	lda	$1,__deregister_frame_info
-	beq	$1,0f
-	lda	$16,__EH_FRAME_BEGIN__
-	jsr	$26,__deregister_frame_info
-	ldq     $26,0($30)
-0:	lda     $30,16($30)
-	ret
-
-	.end __do_frame_takedown
-
-.weak __register_frame_info
-.weak __deregister_frame_info
diff --git a/gcc/config/alpha/crtend.asm b/gcc/config/alpha/crtend.asm
deleted file mode 100755
index 4a0cc5e..0000000
--- a/gcc/config/alpha/crtend.asm
+++ /dev/null
@@ -1,108 +0,0 @@
- # Copyright (C) 1996 Free Software Foundation, Inc.
- #  Contributed by Richard Henderson (rth@tamu.edu)
- #
- # This file is free software; you can redistribute it and/or modify it
- # under the terms of the GNU General Public License as published by the
- # Free Software Foundation; either version 2, or (at your option) any
- # later version.
- # 
- # In addition to the permissions in the GNU General Public License, the
- # Free Software Foundation gives you unlimited permission to link the
- # compiled version of this file with other programs, and to distribute
- # those programs without any restriction coming from the use of this
- # file.  (The General Public License restrictions do apply in other
- # respects; for example, they cover modification of the file, and
- # distribution when not linked into another program.)
- # 
- # This file is distributed in the hope that it will be useful, but
- # WITHOUT ANY WARRANTY; without even the implied warranty of
- # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- # General Public License for more details.
- # 
- # You should have received a copy of the GNU General Public License
- # along with this program; see the file COPYING.  If not, write to
- # the Free Software Foundation, 59 Temple Place - Suite 330,
- # Boston, MA 02111-1307, USA.
- # 
- #    As a special exception, if you link this library with files
- #    compiled with GCC to produce an executable, this does not cause
- #    the resulting executable to be covered by the GNU General Public License.
- #    This exception does not however invalidate any other reasons why
- #    the executable file might be covered by the GNU General Public License.
-
- #
- # Tails of the constructor/destructor lists.
- #
-
- # The __*TOR_END__ symbols are not global because when this file is used
- # in a shared library, we do not want the symbol to fall over to the
- # application's lists.
-
-.section .ctors,"aw"
-
-	.align 3
-__CTOR_END__:
-	.quad   0
-
-.section .dtors,"aw"
-
-	.align 3
-__DTOR_END__:
-	.quad   0
-
-.section .eh_frame,"aw"
-__FRAME_END__:
-	.quad	0
-
- #
- # Fragment of the ELF _init routine that invokes our ctor startup
- #
-
-.section .init,"ax"
-
-	# Since the bits of the _init function are spread across many
-	# object files, each potentially with its own GP, we must
-	# assume we need to load ours.  Further, our .init section
-	# can easily be more than 4MB away from our .text bits so we
-	# can't use bsr.
-
-	br      $29,1f
-1:	ldgp    $29,0($29)
-	jsr     $26,__do_global_ctors_aux
-
-	# Must match the alignment we got from crti.o else we get
-	# zero-filled holes in our _init function and thense SIGILL.
-	.align 3
-
- #
- # Invoke our destructors in order.
- #
-
-.text
-
-	.align 3
-	.ent __do_global_ctors_aux
-
-__do_global_ctors_aux:
-	ldgp	$29,0($27)
-	lda     $30,-16($30)
-	.frame  $30,16,$26,0
-	stq     $9,8($30)
-	stq     $26,0($30)
-	.mask   0x4000200,-16
-	.prologue 1
-
-	lda     $9,__CTOR_END__
-	br      1f
-0:	jsr     $26,($27)
-1:	ldq     $27,-8($9)
-	subq    $9,8,$9
-	not     $27,$0
-	bne     $0,0b
-
-	ldq     $26,0($30)
-	ldq     $9,8($30)
-	lda     $30,16($30)
-	ret
-
-	.end __do_global_ctors_aux
diff --git a/gcc/config/alpha/elf.h b/gcc/config/alpha/elf.h
deleted file mode 100755
index d32ca41..0000000
--- a/gcc/config/alpha/elf.h
+++ /dev/null
@@ -1,527 +0,0 @@
-/* Definitions of target machine for GNU compiler, for DEC Alpha w/ELF.
-   Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-   Contributed by Richard Henderson (rth@tamu.edu).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.    */
-
-#undef OBJECT_FORMAT_COFF
-#undef EXTENDED_COFF
-#define OBJECT_FORMAT_ELF
-
-#define DBX_DEBUGGING_INFO
-#define DWARF2_DEBUGGING_INFO
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#undef ASM_FINAL_SPEC
-
-#undef CC1_SPEC
-#define CC1_SPEC  "%{G*}"
-
-#undef ASM_SPEC
-#define ASM_SPEC  "%{G*} %{relax:-relax} %{gdwarf*:-no-mdebug}"
-
-#undef LINK_SPEC
-#define LINK_SPEC "-m elf64alpha %{G*} %{relax:-relax}		\
-  %{O*:-O3} %{!O*:-O1}						\
-  %{shared:-shared}						\
-  %{!shared:							\
-    %{!static:							\
-      %{rdynamic:-export-dynamic}				\
-      %{!dynamic-linker:-dynamic-linker %(elf_dynamic_linker)}}	\
-    %{static:-static}}"
-
-/* Output at beginning of assembler file.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)					\
-do {								\
-  if (write_symbols != DWARF2_DEBUG)				\
-    {								\
-      alpha_write_verstamp (FILE);				\
-      output_file_directive (FILE, main_input_filename);	\
-    }								\
-  fprintf (FILE, "\t.set noat\n");				\
-  fprintf (FILE, "\t.set noreorder\n");				\
-  if (TARGET_BWX | TARGET_MAX | TARGET_CIX)			\
-    {								\
-      fprintf (FILE, "\t.arch %s\n",				\
-               (alpha_cpu == PROCESSOR_EV6 ? "ev6"		\
-                : TARGET_MAX ? "pca56" : "ev56"));		\
-    }								\
-} while (0)
-
-extern void output_file_directive ();
-
-/* Attach a special .ident directive to the end of the file to identify
-   the version of GCC which compiled this code.  The format of the
-   .ident string is patterned after the ones produced by native svr4
-   C compilers.  */
-
-#define IDENT_ASM_OP ".ident"
-
-#ifdef IDENTIFY_WITH_IDENT
-#define ASM_IDENTIFY_GCC(FILE) /* nothing */
-#define ASM_IDENTIFY_LANGUAGE(FILE)			\
- fprintf(FILE, "\t%s \"GCC (%s) %s\"\n", IDENT_ASM_OP,	\
-	 lang_identify(), version_string)
-#else
-#define ASM_FILE_END(FILE)					\
-do {				 				\
-     fprintf ((FILE), "\t%s\t\"GCC: (GNU) %s\"\n",		\
-	      IDENT_ASM_OP, version_string);			\
-   } while (0)
-#endif
-
-/* Allow #sccs in preprocessor.  */
-#define SCCS_DIRECTIVE
-
-/* Output #ident as a .ident.  */
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
-
-/* This is how to allocate empty space in some section.  The .zero
-   pseudo-op is used for this on most svr4 assemblers.  */
-
-#define SKIP_ASM_OP	".zero"
-
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
-  fprintf (FILE, "\t%s\t%u\n", SKIP_ASM_OP, (SIZE))
-
-/* Output the label which precedes a jumptable.  Note that for all svr4
-   systems where we actually generate jumptables (which is to say every
-   svr4 target except i386, where we use casesi instead) we put the jump-
-   tables into the .rodata section and since other stuff could have been
-   put into the .rodata section prior to any given jumptable, we have to
-   make sure that the location counter for the .rodata section gets pro-
-   perly re-aligned prior to the actual beginning of the jump table.  */
-
-#define ALIGN_ASM_OP ".align"
-
-#ifndef ASM_OUTPUT_BEFORE_CASE_LABEL
-#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
-  ASM_OUTPUT_ALIGN ((FILE), 2);
-#endif
-
-#undef ASM_OUTPUT_CASE_LABEL
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,JUMPTABLE)		\
-  do {									\
-    ASM_OUTPUT_BEFORE_CASE_LABEL (FILE, PREFIX, NUM, JUMPTABLE)		\
-    ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM);			\
-  } while (0)
-
-/* The standard SVR4 assembler seems to require that certain builtin
-   library routines (e.g. .udiv) be explicitly declared as .globl
-   in each assembly file where they are referenced.  */
-
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN)				\
-  ASM_GLOBALIZE_LABEL (FILE, XSTR (FUN, 0))
-
-/* This says how to output assembler code to declare an
-   uninitialized external linkage data object.  Under SVR4,
-   the linker seems to want the alignment of data objects
-   to depend on their types.  We do exactly that here.  */
-
-#define COMMON_ASM_OP	".comm"
-
-#undef ASM_OUTPUT_ALIGNED_COMMON
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fprintf ((FILE), "\t%s\t", COMMON_ASM_OP);				\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
-} while (0)
-
-/* This says how to output assembler code to declare an
-   uninitialized internal linkage data object.  Under SVR4,
-   the linker seems to want the alignment of data objects
-   to depend on their types.  We do exactly that here.  */
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  if ((SIZE) <= g_switch_value)						\
-    sbss_section();							\
-  else									\
-    bss_section();							\
-  fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-  assemble_name (FILE, NAME);						\
-  putc (',', FILE);							\
-  fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
-  putc ('\n', FILE);							\
-  if (!flag_inhibit_size_directive)					\
-    {									\
-      fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-      assemble_name (FILE, NAME);					\
-      fprintf (FILE, ",%d\n", (SIZE));					\
-    }									\
-  ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT));	\
-  ASM_OUTPUT_LABEL(FILE, NAME);						\
-  ASM_OUTPUT_SKIP((FILE), (SIZE));					\
-} while (0)
-
-/* This is the pseudo-op used to generate a 64-bit word of data with a
-   specific value in some section.  */
-
-#define INT_ASM_OP		".quad"
-
-/* Biggest alignment supported by the object file format of this
-   machine.  Use this macro to limit the alignment which can be
-   specified using the `__attribute__ ((aligned (N)))' construct.  If
-   not defined, the default value is `BIGGEST_ALIGNMENT'. 
-
-   This value is really 2^63.  Since gcc figures the alignment in bits,
-   we could only potentially get to 2^60 on suitible hosts.  Due to other
-   considerations in varasm, we must restrict this to what fits in an int.  */
-
-#define MAX_OFILE_ALIGNMENT \
-  (1 << (HOST_BITS_PER_INT < 64 ? HOST_BITS_PER_INT - 2 : 62))
-
-/* This is the pseudo-op used to generate a contiguous sequence of byte
-   values from a double-quoted string WITHOUT HAVING A TERMINATING NUL
-   AUTOMATICALLY APPENDED.  This is the same for most svr4 assemblers.  */
-
-#undef ASCII_DATA_ASM_OP
-#define ASCII_DATA_ASM_OP	".ascii"
-
-/* Support const sections and the ctors and dtors sections for g++.
-   Note that there appears to be two different ways to support const
-   sections at the moment.  You can either #define the symbol
-   READONLY_DATA_SECTION (giving it some code which switches to the
-   readonly data section) or else you can #define the symbols
-   EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
-   SELECT_RTX_SECTION.  We do both here just to be on the safe side.  */
-
-#define USE_CONST_SECTION	1
-
-#define CONST_SECTION_ASM_OP	".section\t.rodata"
-
-/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
-
-   Note that we want to give these sections the SHF_WRITE attribute
-   because these sections will actually contain data (i.e. tables of
-   addresses of functions in the current root executable or shared library
-   file) and, in the case of a shared library, the relocatable addresses
-   will have to be properly resolved/relocated (and then written into) by
-   the dynamic linker when it actually attaches the given shared library
-   to the executing process.  (Note that on SVR4, you may wish to use the
-   `-z text' option to the ELF linker, when building a shared library, as
-   an additional check that you are doing everything right.  But if you do
-   use the `-z text' option when building a shared library, you will get
-   errors unless the .ctors and .dtors sections are marked as writable
-   via the SHF_WRITE attribute.)  */
-
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"aw\""
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"aw\""
-
-/* Handle the small data sections.  */
-#define BSS_SECTION_ASM_OP	".section\t.bss"
-#define SBSS_SECTION_ASM_OP	".section\t.sbss,\"aw\""
-#define SDATA_SECTION_ASM_OP	".section\t.sdata,\"aw\""
-
-/* On svr4, we *do* have support for the .init and .fini sections, and we
-   can put stuff in there to be executed before and after `main'.  We let
-   crtstuff.c and other files know this by defining the following symbols.
-   The definitions say how to change sections to the .init and .fini
-   sections.  This is the same for all known svr4 assemblers.  */
-
-#define INIT_SECTION_ASM_OP	".section\t.init"
-#define FINI_SECTION_ASM_OP	".section\t.fini"
-
-/* A default list of other sections which we might be "in" at any given
-   time.  For targets that use additional sections (e.g. .tdesc) you
-   should override this definition in the target-specific file which
-   includes this file.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_ctors, in_dtors, in_sbss, in_sdata
-
-/* A default list of extra section function definitions.  For targets
-   that use additional sections (e.g. .tdesc) you should override this
-   definition in the target-specific file which includes this file.  */
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CONST_SECTION_FUNCTION						\
-  SECTION_FUNCTION_TEMPLATE(ctors_section, in_ctors, CTORS_SECTION_ASM_OP) \
-  SECTION_FUNCTION_TEMPLATE(dtors_section, in_dtors, DTORS_SECTION_ASM_OP) \
-  SECTION_FUNCTION_TEMPLATE(sbss_section, in_sbss, SBSS_SECTION_ASM_OP)	\
-  SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP)
-
-#undef READONLY_DATA_SECTION
-#define READONLY_DATA_SECTION() const_section ()
-
-extern void text_section ();
-
-#define CONST_SECTION_FUNCTION						\
-void									\
-const_section ()							\
-{									\
-  if (!USE_CONST_SECTION)						\
-    text_section();							\
-  else if (in_section != in_const)					\
-    {									\
-      fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP);		\
-      in_section = in_const;						\
-    }									\
-}
-
-#define SECTION_FUNCTION_TEMPLATE(FN, ENUM, OP)				\
-void FN ()								\
-{									\
-  if (in_section != ENUM)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", OP);				\
-      in_section = ENUM;						\
-    }									\
-}
-
-
-/* Switch into a generic section.
-   This is currently only used to support section attributes.
-
-   We make the section read-only and executable for a function decl,
-   read-only for a const data decl, and writable for a non-const data decl.  */
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
-  fprintf (FILE, ".section\t%s,\"%s\",@progbits\n", NAME, \
-	   (DECL) && TREE_CODE (DECL) == FUNCTION_DECL ? "ax" : \
-	   (DECL) && DECL_READONLY_SECTION (DECL, RELOC) ? "a" : "aw")
-
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement or statements to switch to the appropriate
-   section for output of DECL.  DECL is either a `VAR_DECL' node
-   or a constant of some sort.  RELOC indicates whether forming
-   the initial value of DECL requires link-time relocations.  */
-
-#define SELECT_SECTION(DECL,RELOC)					\
-{									\
-  if (TREE_CODE (DECL) == STRING_CST)					\
-    {									\
-      if (! flag_writable_strings)					\
-	const_section ();						\
-      else								\
-	data_section ();						\
-    }									\
-  else if (TREE_CODE (DECL) == VAR_DECL)				\
-    {									\
-      if ((flag_pic && RELOC)						\
-	  || !TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)		\
-	  || !DECL_INITIAL (DECL)					\
-	  || (DECL_INITIAL (DECL) != error_mark_node			\
-	      && !TREE_CONSTANT (DECL_INITIAL (DECL))))			\
-	{								\
-	  int size = int_size_in_bytes (TREE_TYPE (DECL));		\
-	  if (size >= 0 && size <= g_switch_value)			\
-	    sdata_section ();						\
-	  else								\
-	    data_section ();						\
-	}								\
-      else								\
-	const_section ();						\
-    }									\
-  else									\
-    const_section ();							\
-}
-
-/* A C statement or statements to switch to the appropriate
-   section for output of RTX in mode MODE.  RTX is some kind
-   of constant in RTL.  The argument MODE is redundant except
-   in the case of a `const_int' rtx.  Currently, these always
-   go into the const section.  */
-
-#undef SELECT_RTX_SECTION
-#define SELECT_RTX_SECTION(MODE,RTX) const_section()
-
-/* Define the strings used for the special svr4 .type and .size directives.
-   These strings generally do not vary from one system running svr4 to
-   another, but if a given system (e.g. m88k running svr) needs to use
-   different pseudo-op names for these, they may be overridden in the
-   file which includes this one.  */
-
-#define TYPE_ASM_OP	".type"
-#define SIZE_ASM_OP	".size"
-
-/* This is how we tell the assembler that a symbol is weak.  */
-
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
-  do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \
-       fputc ('\n', FILE); } while (0)
-
-/* This is how we tell the assembler that two symbols have the same value.  */
-
-#define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
-  do { assemble_name(FILE, NAME1); 	 \
-       fputs(" = ", FILE);		 \
-       assemble_name(FILE, NAME2);	 \
-       fputc('\n', FILE); } while (0)
-
-/* The following macro defines the format used to output the second
-   operand of the .type assembler directive.  Different svr4 assemblers
-   expect various different forms for this operand.  The one given here
-   is just a default.  You may need to override it in your machine-
-   specific tm.h file (depending upon the particulars of your assembler).  */
-
-#define TYPE_OPERAND_FMT	"@%s"
-
-/* Write the extra assembler code needed to declare a function's result.
-   Most svr4 assemblers don't require any special declaration of the
-   result value, but there are exceptions.  */
-
-#ifndef ASM_DECLARE_RESULT
-#define ASM_DECLARE_RESULT(FILE, RESULT)
-#endif
-
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare an object properly.  */
-
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
-    putc ('\n', FILE);							\
-    size_directive_output = 0;						\
-    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-      {									\
-	size_directive_output = 1;					\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-	fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));	\
-      }									\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	\
-do {									\
-  char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			\
-  if (!flag_inhibit_size_directive && DECL_SIZE (DECL)			\
-      && ! AT_END && TOP_LEVEL						\
-      && DECL_INITIAL (DECL) == error_mark_node				\
-      && !size_directive_output)					\
-    {									\
-      size_directive_output = 1;					\
-      fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-      assemble_name (FILE, name);					\
-      putc (',', FILE);							\
-      fprintf (FILE, HOST_WIDE_INT_PRINT_DEC,				\
-	       int_size_in_bytes (TREE_TYPE (DECL)));			\
-      putc ('\n', FILE);						\
-    }									\
-} while (0)
-
-/* A table of bytes codes used by the ASM_OUTPUT_ASCII and
-   ASM_OUTPUT_LIMITED_STRING macros.  Each byte in the table
-   corresponds to a particular byte value [0..255].  For any
-   given byte value, if the value in the corresponding table
-   position is zero, the given character can be output directly.
-   If the table value is 1, the byte must be output as a \ooo
-   octal escape.  If the tables value is anything else, then the
-   byte value should be output as a \ followed by the value
-   in the table.  Note that we can use standard UN*X escape
-   sequences for many control characters, but we don't use
-   \a to represent BEL because some svr4 assemblers (e.g. on
-   the i386) don't know about that.  Also, we don't use \v
-   since some versions of gas, such as 2.2 did not accept it.  */
-
-#define ESCAPES \
-"\1\1\1\1\1\1\1\1btn\1fr\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\0\0\"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
-\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\\\0\0\0\
-\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1"
-
-/* Some svr4 assemblers have a limit on the number of characters which
-   can appear in the operand of a .string directive.  If your assembler
-   has such a limitation, you should define STRING_LIMIT to reflect that
-   limit.  Note that at least some svr4 assemblers have a limit on the
-   actual number of bytes in the double-quoted string, and that they
-   count each character in an escape sequence as one byte.  Thus, an
-   escape sequence like \377 would count as four bytes.
-
-   If your target assembler doesn't support the .string directive, you
-   should define this to zero.  */
-
-#define STRING_LIMIT	((unsigned) 256)
-#define STRING_ASM_OP	".string"
-
-/* GAS is the only Alpha/ELF assembler.  */
-#undef TARGET_GAS
-#define TARGET_GAS	(1)
-
-/* Provide a STARTFILE_SPEC appropriate for ELF.  Here we add the
-   (even more) magical crtbegin.o file which provides part of the
-   support for getting C++ file-scope static object constructed before
-   entering `main'. 
-
-   Don't bother seeing crtstuff.c -- there is absolutely no hope of
-   getting that file to understand multiple GPs.  GNU Libc provides a
-   hand-coded version that is used on Linux; it could be copied here
-   if there is ever a need. */
-   
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{!shared: \
-     %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\
-   crti.o%s crtbegin.o%s"
-
-/* Provide a ENDFILE_SPEC appropriate for ELF.  Here we tack on the
-   magical crtend.o file which provides part of the support for
-   getting C++ file-scope static object constructed before entering
-   `main', followed by a normal ELF "finalizer" file, `crtn.o'.  */
-
-#undef	ENDFILE_SPEC
-#define ENDFILE_SPEC \
-  "crtend.o%s crtn.o%s"
-
-/* We support #pragma.  */
-#define HANDLE_SYSV_PRAGMA
diff --git a/gcc/config/alpha/lib1funcs.asm b/gcc/config/alpha/lib1funcs.asm
deleted file mode 100755
index 355c610..0000000
--- a/gcc/config/alpha/lib1funcs.asm
+++ /dev/null
@@ -1,327 +0,0 @@
-/* This file is CYGNUS LOCAL. */
-
-/* DEC Alpha division and remainder support.
-   Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-/* As a special exception, if you link this library with other files,
-   some of which are compiled with GCC, to produce an executable,
-   this library does not by itself cause the resulting executable
-   to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-/* This had to be written in assembler because the division functions 
-   use a non-standard calling convention. 
-
-   This file provides an implementation of __divqu, __divq, __divlu, 
-   __divl, __remqu, __remq, __remlu and __reml.  CPP macros control
-   the exact operation.
-
-   Operation performed: $27 := $24 o $25, clobber $28, return address to
-   caller in $23, where o one of the operations.
-
-   The following macros need to be defined: 
-
-	SIZE, the number of bits, 32 or 64.
-
-	TYPE, either UNSIGNED or SIGNED
-
-	OPERATION, either DIVISION or REMAINDER
-   
-	SPECIAL_CALLING_CONVENTION, 0 or 1.  It is useful for debugging to
-	define this to 0.  That removes the `__' prefix to make the function
-	name not collide with the existing libc.a names, and uses the
-	standard Alpha procedure calling convention.
-*/
-
-#ifndef SPECIAL_CALLING_CONVENTION
-#define SPECIAL_CALLING_CONVENTION 1
-#endif
-
-#ifdef L_divl
-#if SPECIAL_CALLING_CONVENTION
-#define FUNCTION_NAME __divl
-#else
-#define FUNCTION_NAME divl
-#endif
-#define SIZE 32
-#define TYPE SIGNED
-#define OPERATION DIVISION
-#endif
-
-#ifdef L_divlu
-#if SPECIAL_CALLING_CONVENTION
-#define FUNCTION_NAME __divlu
-#else
-#define FUNCTION_NAME divlu
-#endif
-#define SIZE 32
-#define TYPE UNSIGNED
-#define OPERATION DIVISION
-#endif
-
-#ifdef L_divq
-#if SPECIAL_CALLING_CONVENTION
-#define FUNCTION_NAME __divq
-#else
-#define FUNCTION_NAME divq
-#endif
-#define SIZE 64
-#define TYPE SIGNED
-#define OPERATION DIVISION
-#endif
-
-#ifdef L_divqu
-#if SPECIAL_CALLING_CONVENTION
-#define FUNCTION_NAME __divqu
-#else
-#define FUNCTION_NAME divqu
-#endif
-#define SIZE 64
-#define TYPE UNSIGNED
-#define OPERATION DIVISION
-#endif
-
-#ifdef L_reml
-#if SPECIAL_CALLING_CONVENTION
-#define FUNCTION_NAME __reml
-#else
-#define FUNCTION_NAME reml
-#endif
-#define SIZE 32
-#define TYPE SIGNED
-#define OPERATION REMAINDER
-#endif
-
-#ifdef L_remlu
-#if SPECIAL_CALLING_CONVENTION
-#define FUNCTION_NAME __remlu
-#else
-#define FUNCTION_NAME remlu
-#endif
-#define SIZE 32
-#define TYPE UNSIGNED
-#define OPERATION REMAINDER
-#endif
-
-#ifdef L_remq
-#if SPECIAL_CALLING_CONVENTION
-#define FUNCTION_NAME __remq
-#else
-#define FUNCTION_NAME remq
-#endif
-#define SIZE 64
-#define TYPE SIGNED
-#define OPERATION REMAINDER
-#endif
-
-#ifdef L_remqu
-#if SPECIAL_CALLING_CONVENTION
-#define FUNCTION_NAME __remqu
-#else
-#define FUNCTION_NAME remqu
-#endif
-#define SIZE 64
-#define TYPE UNSIGNED
-#define OPERATION REMAINDER
-#endif
-
-#define tmp0 $3
-#define tmp1 $28
-#define cnt $1
-#define result_sign $2
-
-#if SPECIAL_CALLING_CONVENTION
-#define N $24
-#define D $25
-#define Q RETREG
-#define RETREG $27
-#else
-#define N $16
-#define D $17
-#define Q RETREG
-#define RETREG $0
-#endif
-
-/* Misc symbols to make alpha assembler easier to read.  */
-#define zero $31
-#define sp $30
-
-/* Symbols to make interface nicer.  */
-#define UNSIGNED 0
-#define SIGNED 1
-#define DIVISION 0
-#define REMAINDER 1
-
-	.set noreorder
-	.set noat
-.text
-	.align 3
-	.globl FUNCTION_NAME
-	.ent FUNCTION_NAME
-FUNCTION_NAME:
-
-	.frame	$30,0,$26,0
-	.prologue 0
-
-/* Under the special calling convention, we have to preserve all register
-   values but $23 and $28.  */
-#if SPECIAL_CALLING_CONVENTION
-	lda	sp,-64(sp)
-#if OPERATION == DIVISION
-	stq	N,0(sp)
-#endif
-	stq	D,8(sp)
-	stq	cnt,16(sp)
-	stq	result_sign,24(sp)
-	stq	tmp0,32(sp)
-#endif
-
-/* If we are computing the remainder, move N to the register that is used
-   for the return value, and redefine what register is used for N.  */
-#if OPERATION == REMAINDER
-	bis	N,N,RETREG
-#undef N
-#define N RETREG
-#endif
-
-/* Perform conversion from 32 bit types to 64 bit types.  */
-#if SIZE == 32
-#if TYPE == SIGNED
-	/* If there are problems with the signed case, add these instructions.
-	   The caller should already have done this.
-	addl	N,0,N		# sign extend N
-	addl	D,0,D		# sign extend D
-	*/
-#else /* UNSIGNED */
-	zap	N,0xf0,N	# zero extend N (caller required to sign extend)
-	zap	D,0xf0,D	# zero extend D
-#endif
-#endif
-
-/* Check for divide by zero.  */
-	bne	D,$34
-	lda	$16,-2(zero)
-	call_pal 0xaa
-$34:
-
-#if TYPE == SIGNED
-#if OPERATION == DIVISION
-	xor	N,D,result_sign
-#else
-	bis	N,N,result_sign
-#endif
-/* Get the absolute values of N and D.  */
-	subq	zero,N,tmp0
-	cmovlt	N,tmp0,N
-	subq	zero,D,tmp0
-	cmovlt	D,tmp0,D
-#endif
-
-/* Compute CNT = ceil(log2(N)) - ceil(log2(D)).  This is the number of
-   divide iterations we will have to perform.  Should you wish to optimize
-   this, check a few bits at a time, preferably using zap/zapnot.  Be
-   careful though, this code runs fast fro the most common cases, when the
-   quotient is small.  */
-	bge	N,$35
-	bis	zero,1,cnt
-	blt	D,$40
-	.align	3
-$39:	addq	D,D,D
-	addl	cnt,1,cnt
-	bge	D,$39
-	br	zero,$40
-$35:	cmpult	N,D,tmp0
-	bis	zero,zero,cnt
-	bne	tmp0,$42
-	.align	3
-$44:	addq	D,D,D
-	cmpult	N,D,tmp0
-	addl	cnt,1,cnt
-	beq	tmp0,$44
-$42:	srl	D,1,D
-$40:
-	subl	cnt,1,cnt
-
-
-/* Actual divide.  Could be optimized with unrolling.  */
-#if OPERATION == DIVISION
-	bis	zero,zero,Q
-#endif
-	blt	cnt,$46
-	.align	3
-$49:	cmpule	D,N,tmp1
-	subq	N,D,tmp0
-	srl	D,1,D
-	subl	cnt,1,cnt
-	cmovne	tmp1,tmp0,N
-#if OPERATION == DIVISION
-	addq	Q,Q,Q
-	bis	Q,tmp1,Q
-#endif
-	bge	cnt,$49
-$46:
-
-
-/* The result is now in RETREG.  NOTE!  It was written to RETREG using
-   either N or Q as a synonym!  */
-
-
-/* Change the sign of the result as needed.  */
-#if TYPE == SIGNED
-	subq	zero,RETREG,tmp0
-	cmovlt	result_sign,tmp0,RETREG
-#endif
-
-
-/* Restore clobbered registers.  */
-#if SPECIAL_CALLING_CONVENTION
-#if OPERATION == DIVISION
-	ldq	N,0(sp)
-#endif
-	ldq	D,8(sp)
-	ldq	cnt,16(sp)
-	ldq	result_sign,24(sp)
-	ldq	tmp0,32(sp)
-
-	lda	sp,64(sp)
-#endif
-
-
-/* Sign extend an *unsigned* 32 bit result, as required by the Alpha
-   conventions.  */
-#if TYPE == UNSIGNED && SIZE == 32
-	/* This could be avoided by adding some CPP hair to the divide loop.
-	   It is probably not worth the added complexity.    */
-	addl	RETREG,0,RETREG
-#endif
-
-
-#if SPECIAL_CALLING_CONVENTION
-	ret	zero,($23),1
-#else
-	ret	zero,($26),1
-#endif
-	.end	FUNCTION_NAME
diff --git a/gcc/config/alpha/linux-ecoff.h b/gcc/config/alpha/linux-ecoff.h
deleted file mode 100755
index 824d028..0000000
--- a/gcc/config/alpha/linux-ecoff.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Definitions of target machine for GNU compiler
-   for Alpha Linux-based GNU systems using ECOFF.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Bob Manson.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (Alpha GNU/Linux for ECOFF)");
-
-#undef CPP_SUBTARGET_SPEC
-#define CPP_SUBTARGET_SPEC "-D__ECOFF__"
-
-#undef LINK_SPEC
-#define LINK_SPEC "-G 8 %{O*:-O3} %{!O*:-O1}"
-
-/* stabs get slurped by the assembler into a queer ecoff format.  */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* We support #pragma.  */
-#define HANDLE_SYSV_PRAGMA
diff --git a/gcc/config/alpha/linux-elf.h b/gcc/config/alpha/linux-elf.h
deleted file mode 100755
index fc07127..0000000
--- a/gcc/config/alpha/linux-elf.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Definitions of target machine for GNU compiler
-   for Alpha Linux-based GNU systems using ELF.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Richard Henderson.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (Alpha GNU/Linux for ELF)");
-
-#undef SUBTARGET_EXTRA_SPECS
-#define SUBTARGET_EXTRA_SPECS \
-{ "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
-
-#undef SUB_CPP_PREDEFINES
-#define SUB_CPP_PREDEFINES	"-D__ELF__"
-
-#ifdef USE_GNULIBC_1
-#define ELF_DYNAMIC_LINKER	"/lib/ld.so.1"
-#else
-#define ELF_DYNAMIC_LINKER	"/lib/ld-linux.so.2"
-#endif
-
-#ifndef USE_GNULIBC_1
-#undef DEFAULT_VTABLE_THUNKS
-#define DEFAULT_VTABLE_THUNKS 1
-#endif
-
-#ifndef USE_GNULIBC_1
-#undef LIB_SPEC
-#define LIB_SPEC \
-"%{shared:-lc}%{!shared:%{pthread:-lpthread }%{profile:-lc_p}%{!profile:-lc}} "
-#endif
diff --git a/gcc/config/alpha/linux.h b/gcc/config/alpha/linux.h
deleted file mode 100755
index b8eb9e9..0000000
--- a/gcc/config/alpha/linux.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Definitions of target machine for GNU compiler,
-   for Alpha Linux-based GNU systems.
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Richard Henderson.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_FP | MASK_FPREGS | MASK_GAS)
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-"-Dlinux -Dunix -Asystem(linux) -D_LONGLONG -D__alpha__ " \
-SUB_CPP_PREDEFINES
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{pg:-lgmon} %{pg:-lc_p} %{!pg:-lc}"
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS 1
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)			\
-	fputs ("\tlda $28,_mcount\n\tjsr $28,($28),_mcount\n", (FILE))
-
-/* Show that we need a GP when profiling.  */
-#define TARGET_PROFILING_NEEDS_GP 1
-
-/* Don't care about faults in the prologue.  */
-#undef TARGET_CAN_FAULT_IN_PROLOGUE
-#define TARGET_CAN_FAULT_IN_PROLOGUE 1
diff --git a/gcc/config/alpha/netbsd-elf.h b/gcc/config/alpha/netbsd-elf.h
deleted file mode 100755
index 6e4f4da..0000000
--- a/gcc/config/alpha/netbsd-elf.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Definitions of target machine for GNU compiler
-   for Alpha NetBSD systems using ELF.
-   Copyright (C) 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (Alpha NetBSD/ELF)");
-
-#undef SUB_CPP_PREDEFINES
-#define SUB_CPP_PREDEFINES "-D__ELF__"
-
-#undef SUBTARGET_EXTRA_SPECS
-#define SUBTARGET_EXTRA_SPECS \
-{ "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
-
-#define ELF_DYNAMIC_LINKER	"/usr/libexec/ld.elf_so"
diff --git a/gcc/config/alpha/netbsd.h b/gcc/config/alpha/netbsd.h
deleted file mode 100755
index 5189064..0000000
--- a/gcc/config/alpha/netbsd.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Definitions of target machine for GNU compiler,
-   for Alpha NetBSD systems.
-   Copyright (C) 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_FP | MASK_FPREGS | MASK_GAS)
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D_LONGLONG -Dnetbsd -Dunix " SUB_CPP_PREDEFINES
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{pg:-lgmon} %{pg:-lc_p} %{!pg:-lc}"
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)			\
-	fputs ("\tlda $28,_mcount\n\tjsr $28,($28),_mcount\n", (FILE))
-
-/* Show that we need a GP when profiling.  */
-#define TARGET_PROFILING_NEEDS_GP
diff --git a/gcc/config/alpha/osf.h b/gcc/config/alpha/osf.h
deleted file mode 100755
index 956961f..0000000
--- a/gcc/config/alpha/osf.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Definitions of target machine for GNU compiler, for DEC Alpha on OSF/1.
-   Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As of OSF 4.0, as can subtract adjacent labels.  */
-
-#undef TARGET_AS_CAN_SUBTRACT_LABELS
-#define TARGET_AS_CAN_SUBTRACT_LABELS 1
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "\
--Dunix -D__osf__ -D_LONGLONG -DSYSTYPE_BSD \
--D_SYSTYPE_BSD -Asystem(unix) -Asystem(xpg4)"
-
-/* Under OSF4, -p and -pg require -lprof1, and -lprof1 requires -lpdf.  */
-
-#define LIB_SPEC "%{p:-lprof1 -lpdf} %{pg:-lprof1 -lpdf} %{a:-lprof2} -lc"
-
-/* Pass "-G 8" to ld because Alpha's CC does.  Pass -O3 if we are
-   optimizing, -O1 if we are not.  Pass -shared, -non_shared or
-   -call_shared as appropriate.  Also pass -pg.  */
-#define LINK_SPEC  \
-  "-G 8 %{O*:-O3} %{!O*:-O1} %{static:-non_shared} \
-   %{!static:%{shared:-shared} %{!shared:-call_shared}} %{pg} %{taso} \
-   %{rpath*}"
-
-#define STARTFILE_SPEC  \
-  "%{!shared:%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}"
-
-#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
-
-#define ASM_FILE_START(FILE)					\
-{								\
-  alpha_write_verstamp (FILE);					\
-  fprintf (FILE, "\t.set noreorder\n");				\
-  fprintf (FILE, "\t.set volatile\n");                          \
-  fprintf (FILE, "\t.set noat\n");				\
-  if (TARGET_SUPPORT_ARCH)					\
-    fprintf (FILE, "\t.arch %s\n",				\
-             alpha_cpu == PROCESSOR_EV6 ? "ev6"			\
-	     : (alpha_cpu == PROCESSOR_EV5			\
-		? (TARGET_MAX ? "pca56" : TARGET_BWX ? "ev56" : "ev5") \
-		: "ev4"));					\
-								\
-  ASM_OUTPUT_SOURCE_FILENAME (FILE, main_input_filename);	\
-}
-
-/* No point in running CPP on our assembler output.  */
-#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_GAS) != 0
-/* Don't pass -g to GNU as, because some versions don't accept this option.  */
-#define ASM_SPEC "%{malpha-as:-g} -nocpp %{pg}"
-#else
-/* In OSF/1 v3.2c, the assembler by default does not output file names which
-   causes mips-tfile to fail.  Passing -g to the assembler fixes this problem.
-   ??? Strictly speaking, we need -g only if the user specifies -g.  Passing
-   it always means that we get slightly larger than necessary object files
-   if the user does not specify -g.  If we don't pass -g, then mips-tfile
-   will need to be fixed to work in this case.  Pass -O0 since some
-   optimization are broken and don't help us anyway.  */
-#define ASM_SPEC "%{!mgas:-g} -nocpp %{pg} -O0"
-#endif
-
-/* Specify to run a post-processor, mips-tfile after the assembler
-   has run to stuff the ecoff debug information into the object file.
-   This is needed because the Alpha assembler provides no way
-   of specifying such information in the assembly file.  */
-
-#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_GAS) != 0
-
-#define ASM_FINAL_SPEC "\
-%{malpha-as: %{!mno-mips-tfile: \
-	\n mips-tfile %{v*: -v} \
-		%{K: -I %b.o~} \
-		%{!K: %{save-temps: -I %b.o~}} \
-		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
-		%{.s:%i} %{!.s:%g.s}}}"
-
-#else
-#define ASM_FINAL_SPEC "\
-%{!mgas: %{!mno-mips-tfile: \
-	\n mips-tfile %{v*: -v} \
-		%{K: -I %b.o~} \
-		%{!K: %{save-temps: -I %b.o~}} \
-		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
-		%{.s:%i} %{!.s:%g.s}}}"
-
-#endif
-
-/* Indicate that we have a stamp.h to use.  */
-#ifndef CROSS_COMPILE
-#define HAVE_STAMP_H 1
-#endif
-
-/* Attempt to turn on access permissions for the stack.  */
-
-#define TRANSFER_FROM_TRAMPOLINE					\
-void									\
-__enable_execute_stack (addr)						\
-     void *addr;							\
-{									\
-  long size = getpagesize ();						\
-  long mask = ~(size-1);						\
-  char *page = (char *) (((long) addr) & mask);				\
-  char *end  = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \
-									\
-  /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */				\
-  if (mprotect (page, end - page, 7) < 0)				\
-    perror ("mprotect of trampoline code");				\
-}
diff --git a/gcc/config/alpha/osf12.h b/gcc/config/alpha/osf12.h
deleted file mode 100755
index 87e2111..0000000
--- a/gcc/config/alpha/osf12.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Definitions of target machine for GNU compiler, for DEC Alpha.
-   Copyright (C) 1992, 1993, 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* In OSF 1.2, there is a linker bug that prevents use of -O3 to
-   the linker.  */
-
-#undef LINK_SPEC
-#define LINK_SPEC  \
-  "-G 8 -O1 %{static:-non_shared} %{rpath*} \
-   %{!static:%{shared:-shared} %{!shared:-call_shared}} %{taso}"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
diff --git a/gcc/config/alpha/osf2or3.h b/gcc/config/alpha/osf2or3.h
deleted file mode 100755
index 5abdb0e..0000000
--- a/gcc/config/alpha/osf2or3.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Definitions of target machine for GNU compiler, for DEC Alpha, osf[23].
-   Copyright (C) 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* In OSF 2 or 3, linking with -lprof1 doesn't require -lpdf.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} %{a:-lprof2} -lc"
-
-/* As of OSF 3.2, as still can't subtract adjacent labels.  */
-
-#undef TARGET_AS_CAN_SUBTRACT_LABELS
-#define TARGET_AS_CAN_SUBTRACT_LABELS 0
-
diff --git a/gcc/config/alpha/t-crtbe b/gcc/config/alpha/t-crtbe
deleted file mode 100755
index 5e82b92..0000000
--- a/gcc/config/alpha/t-crtbe
+++ /dev/null
@@ -1,9 +0,0 @@
-# Effectively disable the crtbegin/end rules using crtstuff.c
-T = disable
-
-# Assemble startup files.
-crtbegin.o: $(srcdir)/config/alpha/crtbegin.asm $(GCC_PASSES)
-	$(GCC_FOR_TARGET) -c -o crtbegin.o -x assembler $(srcdir)/config/alpha/crtbegin.asm
-
-crtend.o: $(srcdir)/config/alpha/crtend.asm $(GCC_PASSES)
-	$(GCC_FOR_TARGET) -c -o crtend.o -x assembler $(srcdir)/config/alpha/crtend.asm
diff --git a/gcc/config/alpha/t-linux b/gcc/config/alpha/t-linux
deleted file mode 100755
index f488477..0000000
--- a/gcc/config/alpha/t-linux
+++ /dev/null
@@ -1,5 +0,0 @@
-# Do not build libgcc1. Let gcc generate those functions. The GNU/Linux
-# C library can handle them.
-LIBGCC1 = 
-CROSS_LIBGCC1 =
-LIBGCC1_TEST =
diff --git a/gcc/config/alpha/t-vms b/gcc/config/alpha/t-vms
deleted file mode 100755
index 12ac240..0000000
--- a/gcc/config/alpha/t-vms
+++ /dev/null
@@ -1,6 +0,0 @@
-# Do not build libgcc1.
-LIBGCC1 = 
-CROSS_LIBGCC1 =
-
-LIB2FUNCS_EXTRA = tramp.s
-
diff --git a/gcc/config/alpha/va_list.h b/gcc/config/alpha/va_list.h
deleted file mode 100755
index c9ab2b0..0000000
--- a/gcc/config/alpha/va_list.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* A replacement for Digital Unix's <va_list.h>.  */
-
-#include <va-alpha.h>
-
-#if !defined(_VA_LIST) && !defined(_HIDDEN_VA_LIST)
-#define _VA_LIST
-typedef __gnuc_va_list va_list;
-
-#elif defined(_HIDDEN_VA_LIST) && !defined(_HIDDEN_VA_LIST_DONE)
-#define _HIDDEN_VA_LIST_DONE
-typedef __gnuc_va_list __va_list;
-
-#elif defined(_HIDDEN_VA_LIST) && defined(_VA_LIST)
-#undef _HIDDEN_VA_LIST
-
-#endif
diff --git a/gcc/config/alpha/vms-tramp.asm b/gcc/config/alpha/vms-tramp.asm
deleted file mode 100755
index fce9ec5..0000000
--- a/gcc/config/alpha/vms-tramp.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-;# New Alpha OpenVMS trampoline
-;#
-	.set noreorder
-	.set volatile
-	.set noat
-	.file 1 "tramp.s"
-.text
-	.align 3
-	.globl __tramp
-	.ent __tramp
-__tramp..en:
-
-.link
-	.align 3
-__tramp:
-	.pdesc __tramp..en,null
-.text
-	ldq $1,24($27)
-	ldq $27,16($27)
-	ldq $28,8($27)
-	jmp $31,($28),0
-	.end __tramp
diff --git a/gcc/config/alpha/vms.h b/gcc/config/alpha/vms.h
deleted file mode 100755
index 44cf5bf..0000000
--- a/gcc/config/alpha/vms.h
+++ /dev/null
@@ -1,510 +0,0 @@
-/* Output variables, constants and external declarations, for GNU compiler.
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define OPEN_VMS 1
-
-/* This enables certain macros in alpha.h, which will make an indirect
-   reference to an external symbol an invalid address.  This needs to be
-   defined before we include alpha.h, since it determines which macros
-   are used for GO_IF_*.  */
-
-#define NO_EXTERNAL_INDIRECT_ADDRESS
-
-#include "alpha/alpha.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-"-D__ALPHA -Dvms -DVMS -D__vms__ -D__VMS__ -Asystem(vms)"
-
-#undef CPP_SUBTARGET_SPEC
-#define CPP_SUBTARGET_SPEC "\
-%{mfloat-ieee:-D__IEEE_FLOAT} \
-%{mfloat-vax:-D__G_FLOAT} \
-%{!mfloat-vax:-D__IEEE_FLOAT}"
-
-/* Under OSF4, -p and -pg require -lprof1, and -lprof1 requires -lpdf.  */
-
-#define LIB_SPEC "%{p:-lprof1 -lpdf} %{pg:-lprof1 -lpdf} %{a:-lprof2} -lc"
-
-/* Pass "-G 8" to ld because Alpha's CC does.  Pass -O3 if we are
-   optimizing, -O1 if we are not.  Pass -shared, -non_shared or
-   -call_shared as appropriate.  Also pass -pg.  */
-#define LINK_SPEC  \
-  "-G 8 %{O*:-O3} %{!O*:-O1} %{static:-non_shared} \
-   %{!static:%{shared:-shared} %{!shared:-call_shared}} %{pg} %{taso} \
-   %{rpath*}"
-
-/* We allow $'s in identifiers unless -ansi is used .. */
-
-#define DOLLARS_IN_IDENTIFIERS 2
-
-/* These match the definitions used in DECCRTL, the VMS C run-time library
-
-#define SIZE_TYPE	"unsigned int"
-#define PTRDIFF_TYPE	"int"
-*/
-
-/* Use memcpy for structure copying, and so forth.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* By default, allow $ to be part of an identifier.  */
-#define DOLLARS_IN_IDENTIFIERS 2
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_FP|MASK_FPREGS|MASK_GAS)
-#undef TARGET_OPEN_VMS
-#define TARGET_OPEN_VMS 1
-
-#undef TARGET_NAME   
-#define TARGET_NAME "OpenVMS/Alpha"
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (%s)", TARGET_NAME);           
-
-/* The structure return address arrives as an "argument" on VMS.  */
-#undef STRUCT_VALUE_REGNUM
-#define STRUCT_VALUE 0
-#undef PCC_STATIC_STRUCT_RETURN
-
-/* no floating emulation.  */
-#undef REAL_ARITHMETIC
-
-/* "long" is 32 bits.  */
-#undef LONG_TYPE_SIZE
-#define LONG_TYPE_SIZE 32
-
-/* Pointer is 32 bits but the hardware has 64-bit addresses, sign extended. */
-#undef POINTER_SIZE
-#define POINTER_SIZE 32
-#define POINTERS_EXTEND_UNSIGNED 0
-
-#define MAX_OFILE_ALIGNMENT 524288  /* 8 x 2^16 by DEC Ada Test CD40VRA */
-
-#undef FIXED_REGISTERS
-#define FIXED_REGISTERS  \
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
-
-#undef CALL_USED_REGISTERS
-#define CALL_USED_REGISTERS  \
- {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
-
-#undef HARD_FRAME_POINTER_REGNUM
-#define HARD_FRAME_POINTER_REGNUM 29
-
-#undef CAN_ELIMINATE
-#define CAN_ELIMINATE(FROM, TO)  \
-((TO) != STACK_POINTER_REGNUM || ! alpha_using_fp ())
-
-#undef INITIAL_ELIMINATION_OFFSET
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
-{ if ((FROM) == FRAME_POINTER_REGNUM)					\
-    (OFFSET) = alpha_sa_size () + alpha_pv_save_size ();		\
-  else if ((FROM) == ARG_POINTER_REGNUM)				\
-    (OFFSET) = (ALPHA_ROUND (alpha_sa_size () + alpha_pv_save_size ()	\
-			     + get_frame_size ()			\
-			     + current_function_pretend_args_size)	\
-		- current_function_pretend_args_size);			\
-  if ((TO) == STACK_POINTER_REGNUM)					\
-    (OFFSET) += ALPHA_ROUND (current_function_outgoing_args_size);	\
-}
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On Alpha/VMS, this is a structure that contains the number of
-   arguments and, for each argument, the datatype of that argument.
-
-   The number of arguments is a number of words of arguments scanned so far.
-   Thus 6 or more means all following args should go on the stack.  */
-
-enum avms_arg_type {I64, FF, FD, FG, FS, FT};
-typedef struct {char num_args; enum avms_arg_type atypes[6];} avms_arg_info;
-
-#undef CUMULATIVE_ARGS
-#define CUMULATIVE_ARGS avms_arg_info
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-
-#undef INIT_CUMULATIVE_ARGS
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
-  (CUM).num_args = 0;						\
-  (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64;	\
-  (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64;
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-extern enum avms_arg_type alpha_arg_type ();
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode (or VOIDmode for no more args).
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-
-   On Alpha the first 6 words of args are normally in registers
-   and the rest are pushed.  */
-
-extern struct rtx_def *alpha_arg_info_reg_val ();
-#undef FUNCTION_ARG
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)	\
-((MODE) == VOIDmode ? alpha_arg_info_reg_val (CUM)		\
- : ((CUM.num_args) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE)	\
-    ? gen_rtx(REG, (MODE),					\
-	      ((CUM).num_args + 16				\
-	       + ((TARGET_FPREGS				\
-		   && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
-		       || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
-		  * 32)))			\
-    : 0))
-
-#undef FUNCTION_ARG_ADVANCE
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
-  if (MUST_PASS_IN_STACK (MODE, TYPE))					\
-    (CUM).num_args += 6;						\
-  else									\
-    {									\
-      if ((CUM).num_args < 6)						\
-        (CUM).atypes[(CUM).num_args] = alpha_arg_type (MODE);		\
-									\
-     (CUM).num_args += ALPHA_ARG_SIZE (MODE, TYPE, NAMED);		\
-    }
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#undef FUNCTION_ARG_PARTIAL_NREGS
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)		\
-((CUM).num_args < 6 && 6 < (CUM).num_args				\
-   + ALPHA_ARG_SIZE (MODE, TYPE, NAMED)					\
- ? 6 - (CUM).num_args : 0)
-
-/* Perform any needed actions needed for a function that is receiving a
-   variable number of arguments. 
-
-   CUM is as for INIT_CUMULATIVE_ARGS.
-
-   MODE and TYPE are the mode and type of the current parameter.
-
-   PRETEND_SIZE is a variable that should be set to the amount of stack
-   that must be pushed by the prolog to pretend that our caller pushed
-   it.
-
-   Normally, this macro will push all remaining incoming registers on the
-   stack and set PRETEND_SIZE to the length of the registers pushed. 
-
-   For VMS, we allocate space for all 6 arg registers plus a count.
-
-   However, if NO registers need to be saved, don't allocate any space.
-   This is not only because we won't need the space, but because AP includes
-   the current_pretend_args_size and we don't want to mess up any
-   ap-relative addresses already made.   */
-
-#undef SETUP_INCOMING_VARARGS
-#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL)	\
-{ if ((CUM).num_args < 6)				\
-    {							\
-      if (! (NO_RTL))					\
-	{						\
-	  emit_move_insn (gen_rtx (REG, DImode, 1),	\
-			  virtual_incoming_args_rtx);	\
-	  emit_insn (gen_arg_home ());			\
-	}						\
-						        \
-      PRETEND_SIZE = 7 * UNITS_PER_WORD;		\
-    }							\
-}
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)					\
-{								\
-  alpha_write_verstamp (FILE);					\
-  fprintf (FILE, "\t.set noreorder\n");				\
-  fprintf (FILE, "\t.set volatile\n");				\
-  ASM_OUTPUT_SOURCE_FILENAME (FILE, main_input_filename);	\
-}
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t;								\
-	REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
-	fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff);		\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);			\
-	fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'f':'s', str);	\
-      }									\
-  }
-
-#define LINK_SECTION_ASM_OP ".link"
-#define READONLY_SECTION_ASM_OP ".rdata"
-#define LITERALS_SECTION_ASM_OP ".literals"
-#define CTORS_SECTION_ASM_OP ".ctors"
-#define DTORS_SECTION_ASM_OP ".dtors"
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS	in_link, in_rdata, in_literals, in_ctors, in_dtors
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS					\
-void								\
-readonly_section ()						\
-{								\
-  if (in_section != in_rdata)				\
-    {								\
-      fprintf (asm_out_file, "%s\n", READONLY_SECTION_ASM_OP);	\
-      in_section = in_rdata;				\
-    }								\
-}								\
-void								\
-link_section ()							\
-{								\
-  if (in_section != in_link)					\
-    {								\
-      fprintf (asm_out_file, "%s\n", LINK_SECTION_ASM_OP); 	\
-      in_section = in_link;					\
-    }								\
-}                                                               \
-void								\
-literals_section ()						\
-{								\
-  if (in_section != in_literals)				\
-    {								\
-      fprintf (asm_out_file, "%s\n", LITERALS_SECTION_ASM_OP); 	\
-      in_section = in_literals;					\
-    }								\
-}								\
-void								\
-ctors_section ()						\
-{								\
-  if (in_section != in_ctors)					\
-    {								\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);	\
-      in_section = in_ctors;					\
-    }								\
-}								\
-void								\
-dtors_section ()						\
-{								\
-  if (in_section != in_dtors)					\
-    {								\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);	\
-      in_section = in_dtors;					\
-    }								\
-}
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) abort ()
-
-#undef ASM_OUTPUT_ADDR_VEC_ELT
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-  fprintf (FILE, "\t.quad $L%d\n", (VALUE))
-
-#undef READONLY_DATA_SECTION
-#define READONLY_DATA_SECTION readonly_section
-
-#define ASM_FILE_END(FILE) alpha_write_linkage (FILE);
-
-#undef CASE_VECTOR_MODE
-#define CASE_VECTOR_MODE DImode
-#undef CASE_VECTOR_PC_RELATIVE
-
-#undef ASM_OUTPUT_CASE_LABEL
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN)	\
-{ ASM_OUTPUT_ALIGN (FILE, 3); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
-
-/* This says how to output assembler code to declare an                
-   uninitialized external linkage data object.  */ 
-
-#define COMMON_ASM_OP ".comm"
-
-#undef ASM_OUTPUT_ALIGNED_COMMON
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fprintf ((FILE), "\t%s\t", COMMON_ASM_OP);				\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
-} while (0)
-
-#define NO_MD_PROTOTYPES
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.
-
-   The trampoline should set the static chain pointer to value placed
-   into the trampoline and should branch to the specified routine.  
-   Note that $27 has been set to the address of the trampoline, so we can
-   use it for addressability of the two data items.  Trampolines are always
-   aligned to FUNCTION_BOUNDARY, which is 64 bits.  */
-
-#undef TRAMPOLINE_TEMPLATE
-#define TRAMPOLINE_TEMPLATE(FILE)		\
-{						\
-  fprintf (FILE, "\t.quad 0\n");		\
-  fprintf (FILE, "\t.linkage __tramp\n");	\
-  fprintf (FILE, "\t.quad 0\n");		\
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#undef TRAMPOLINE_SIZE
-#define TRAMPOLINE_SIZE    32
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#undef INITIALIZE_TRAMPOLINE
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-  alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, -1)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)		\
-  do {							\
-    ctors_section ();					\
-    fprintf (FILE, "\t.quad "); 			\
-    assemble_name (FILE, NAME); 			\
-    fprintf (FILE, "\n");				\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.	*/
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)		\
-  do {							\
-    dtors_section ();					\
-    fprintf (FILE, "\t.quad "); 			\
-    assemble_name (FILE, NAME); 			\
-    fprintf (FILE, "\n");				\
-  } while (0)
-
-#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, NAME, ARGS) \
-  (vms_valid_decl_attribute_p (DECL, ATTRIBUTES, NAME, ARGS))
-extern int vms_valid_decl_attribute_p ();
-
-#undef SDB_DEBUGGING_INFO
-#undef MIPS_DEBUGGING_INFO
-#undef DBX_DEBUGGING_INFO
-
-#define DWARF2_DEBUGGING_INFO
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-    fprintf (FILE, "\t.align %d\n", LOG);
-
-#define UNALIGNED_SHORT_ASM_OP	".word"
-#define UNALIGNED_INT_ASM_OP	".long"
-#define UNALIGNED_DOUBLE_INT_ASM_OP	".quad"
-
-#define ASM_OUTPUT_SECTION(FILE,SECTION)			\
-   (strcmp (SECTION, ".text") == 0)				\
-     ? text_section ()						\
-     : named_section (NULL_TREE, SECTION, 0),			\
-       ASM_OUTPUT_ALIGN (FILE, 0)				\
-
-#define ASM_OUTPUT_SECTION_NAME(FILE,DECL,NAME,RELOC)		\
-  do								\
-    {								\
-      char *flags;					 	\
-      int ovr = 0;						\
-      if (DECL && DECL_MACHINE_ATTRIBUTES (DECL)		\
-	  && lookup_attribute					\
-	      ("overlaid", DECL_MACHINE_ATTRIBUTES (DECL)))	\
-	flags = ",OVR", ovr = 1;				\
-      else if (strncmp (NAME,".debug", 6) == 0)			\
-	flags = ",NOWRT";					\
-      else							\
-	flags = "";						\
-      fputc ('\n', (FILE));					\
-      fprintf (FILE, ".section\t%s%s\n", NAME, flags);		\
-      if (ovr)							\
-        (NAME) = "";						\
-    } while (0)
-
-#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)				\
-  do {	literals_section();                                             \
-	fprintf ((FILE), "\t");						\
-	assemble_name (FILE, LABEL1);					\
-	fprintf (FILE, " = ");						\
-	assemble_name (FILE, LABEL2);					\
-	fprintf (FILE, "\n");						\
-  } while (0)
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-#undef ASM_FORMAT_PRIVATE_NAME
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12),	\
-  sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
-
-/* ??? VMS uses different linkage.  */
-#undef ASM_OUTPUT_MI_THUNK
-
-#undef ASM_SPEC
-#undef ASM_FINAL_SPEC
-#undef LINK_SPEC
-#undef STARTFILE_SPEC
-#define ASM_SPEC "-nocpp %{pg}"
-#define LINK_SPEC "%{g3:-g3} %{g0:-g0} %{shared:-shared} %{v:-v}"
-
-/* Define the names of the division and modulus functions.  */
-#define DIVSI3_LIBCALL "OTS$DIV_I"
-#define DIVDI3_LIBCALL "OTS$DIV_L"
-#define UDIVSI3_LIBCALL "OTS$DIV_UI"
-#define UDIVDI3_LIBCALL "OTS$DIV_UL"
-#define MODSI3_LIBCALL "OTS$REM_I"
-#define MODDI3_LIBCALL "OTS$REM_L"
-#define UMODSI3_LIBCALL "OTS$REM_UI"
-#define UMODDI3_LIBCALL "OTS$REM_UL"
-
-#define DIR_SEPARATOR ']'
-
-#define PREFIX "GNU_ROOT:"
diff --git a/gcc/config/alpha/vxworks.h b/gcc/config/alpha/vxworks.h
deleted file mode 100755
index 6dee4b3..0000000
--- a/gcc/config/alpha/vxworks.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Vxworks Alpha version.
-   Copyright (C) 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file just exists to give specs for the Alpha running on VxWorks.  */
-
-#undef CPP_SUBTARGET_SPEC
-#define CPP_SUBTARGET_SPEC "\
-%{mvxsim:-DCPU=SIMALPHADUNIX} \
-%{!mvxsim: %{!mcpu*|mcpu=21064:-DCPU=21064} %{mcpu=21164:-DCPU=21164}} \
-%{posix: -D_POSIX_SOURCE}"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "\
--D__vxworks -D__alpha_vxworks -Asystem(vxworks) \
--Asystem(embedded) -D_LONGLONG"
-
-/* VxWorks does all the library stuff itself.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC ""
-
-/* VxWorks uses object files, not loadable images.  make linker just
-   combine objects. */
-
-#undef LINK_SPEC
-#define LINK_SPEC "-r"
-
-/* VxWorks provides the functionality of crt0.o and friends itself.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC ""
diff --git a/gcc/config/alpha/win-nt.h b/gcc/config/alpha/win-nt.h
deleted file mode 100755
index a3aa275..0000000
--- a/gcc/config/alpha/win-nt.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* Definitions of target machine for GNU compiler, for DEC Alpha
-   running Windows/NT.
-   Copyright (C) 1995, 1996, 1998 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_FP | MASK_FPREGS)
-
-#undef TARGET_WINDOWS_NT
-#define TARGET_WINDOWS_NT 1
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-DWIN32 -D_WIN32 -DWINNT -D__STDC__=0 -DALMOST_STDC \
--D_M_ALPHA -D_ALPHA_ -D_LONGLONG -D__unaligned= -D__stdcall= -Asystem(winnt)"
-
-#undef ASM_SPEC
-#undef ASM_FINAL_SPEC
-#define ASM_SPEC "-nopp -nologo %{g:-Zi}"
-
-/* Pointer is 32 bits but the hardware has 64-bit addresses, sign extended. */
-#undef POINTER_SIZE
-#define POINTER_SIZE 32
-#define POINTERS_EXTEND_UNSIGNED 0
-
-/* "long" is 32 bits.  */
-#undef LONG_TYPE_SIZE
-#define LONG_TYPE_SIZE 32
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
-
-/* We can't do any debugging.  */
-#undef SDB_DEBUGGING_INFO
-#undef DBX_DEBUGGING_INFO
-#undef MIPS_DEBUGGING_INFO
-
-#include "winnt/win-nt.h"
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)					\
-{								\
-  alpha_write_verstamp (FILE);					\
-  fprintf (FILE, "\t.set noreorder\n");				\
-  fprintf (FILE, "\t.set volatile\n");                          \
-  fprintf (FILE, "\t.set noat\n");				\
-  fprintf (FILE, "\t.globl\t__fltused\n");			\
-  ASM_OUTPUT_SOURCE_FILENAME (FILE, main_input_filename);	\
-}
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{mwindows:-subsystem windows -e _WinMainCRTStartup \
-  USER32.LIB%s GDI32.LIB%s COMDLG32.LIB%s WINSPOOL.LIB%s} \
- %{!mwindows:-subsystem console -e _mainCRTStartup} \
- %{mcrtmt:LIBCMT.LIB%s KERNEL32.LIB%s} %{!mcrtmt:LIBC.LIB%s KERNEL32.LIB%s} \
- %{v}"
-
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.
-
-   The trampoline should set the static chain pointer to value placed
-   into the trampoline and should branch to the specified routine.  */
-
-#undef TRAMPOLINE_TEMPLATE
-#define TRAMPOLINE_TEMPLATE(FILE)			\
-{							\
-  fprintf (FILE, "\tbr $27,$LTRAMPP\n");		\
-  fprintf (FILE, "$LTRAMPP:\n\tldl $1,12($27)\n");	\
-  fprintf (FILE, "\tldl $27,16($27)\n");		\
-  fprintf (FILE, "\tjmp $31,($27),0\n");		\
-  fprintf (FILE, "\t.long 0,0\n");			\
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#undef TRAMPOLINE_SIZE
-#define TRAMPOLINE_SIZE    24
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.   */
-
-#undef INITIALIZE_TRAMPOLINE
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-  alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 20, 12)
-
-/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
-   Used for C++ multiple inheritance.  */
-
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION)	\
-do {									\
-  char *op, *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0);		\
-  int reg;								\
-									\
-  /* Mark end of prologue.  */						\
-  output_end_prologue (FILE);						\
-									\
-  /* Rely on the assembler to macro expand a large delta.  */		\
-  reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16; \
-  fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg);      \       
-									\
-  op = "jsr";								\
-  if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0)))	\
-    op = "br";								\
-  fprintf (FILE, "\t%s $31,", op);					\
-  assemble_name (FILE, fn_name);					\
-  fputc ('\n', FILE);							\
-} while (0)
diff --git a/gcc/config/alpha/x-alpha b/gcc/config/alpha/x-alpha
deleted file mode 100755
index 9686ab9..0000000
--- a/gcc/config/alpha/x-alpha
+++ /dev/null
@@ -1,2 +0,0 @@
-CLIB=-lmld
-EXTRA_HEADERS = $(srcdir)/config/alpha/va_list.h
diff --git a/gcc/config/alpha/xm-alpha.h b/gcc/config/alpha/xm-alpha.h
deleted file mode 100755
index 7665127..0000000
--- a/gcc/config/alpha/xm-alpha.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Configuration for GNU C-compiler for DEC Alpha.
-   Copyright (C) 1990, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define	FALSE	0
-#define	TRUE	1
-
-/* This describes the machine the compiler is hosted on.  */
-#define	HOST_BITS_PER_CHAR	8
-#define	HOST_BITS_PER_SHORT	16
-#define	HOST_BITS_PER_INT	32
-#define	HOST_BITS_PER_LONG	64
-#define HOST_BITS_PER_LONGLONG  64
-
-/* #define	HOST_WORDS_BIG_ENDIAN  */
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define	SUCCESS_EXIT_CODE	0
-#define	FATAL_EXIT_CODE		33
-
-/* If compiled with GNU C, use the builtin alloca.  */
-#ifndef alloca
-#if defined(__GNUC__) && !defined(USE_C_ALLOCA)
-#define alloca __builtin_alloca
-#else
-#if !defined(_WIN32) && !defined(USE_C_ALLOCA) && !defined(OPEN_VMS)
-#include <alloca.h>
-#else
-extern void *alloca ();
-#endif
-#endif
-#endif
-
-/* The host compiler has problems with enum bitfields since it makes
-   them signed so we can't fit all our codes in.  */
-
-#ifndef __GNUC__
-#define ONLY_INT_FIELDS
-#endif
-
-/* Declare some functions needed for this machine.  We don't want to
-   include these in the sources since other machines might define them
-   differently.  */
-
-extern void *malloc (), *realloc (), *calloc ();
-
-#ifndef inhibit_libc
-#include "string.h"
-#endif
-
-/* OSF/1 is POSIX.1 compliant.  */
-
-#define POSIX
diff --git a/gcc/config/alpha/xm-linux.h b/gcc/config/alpha/xm-linux.h
deleted file mode 100755
index b85269b..0000000
--- a/gcc/config/alpha/xm-linux.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#undef USE_BFD
-#define USE_BFD
diff --git a/gcc/config/alpha/xm-vms.h b/gcc/config/alpha/xm-vms.h
deleted file mode 100755
index 472a225..0000000
--- a/gcc/config/alpha/xm-vms.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Configuration for GNU C-compiler for openVMS/Alpha.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Klaus Kaempf (kkaempf@progis.de).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* If compiling with DECC, need to fix problem with <stdio.h>
-   which defines a macro called FILE_TYPE that breaks "tree.h".
-   Fortunately it uses #ifndef to suppress multiple inclusions.
-   Three possible cases:
-        1) <stdio.h> has already been included -- ours will be no-op;
-        2) <stdio.h> will be included after us -- "theirs" will be no-op;
-        3) <stdio.h> isn't needed -- including it here shouldn't hurt.
-   In all three cases, the problem macro will be removed here.  */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#ifdef __DECC
-#undef FILE_TYPE
-#endif
-
-#undef HOST_BITS_PER_LONG
-#define HOST_BITS_PER_LONG 32
-
-#define HOST_WIDE_INT long long
-#define HOST_BITS_PER_WIDE_INT 64
-
-#undef SUCCESS_EXIT_CODE
-#define SUCCESS_EXIT_CODE 1
-#undef FATAL_EXIT_CODE
-#define FATAL_EXIT_CODE (44 | 0x10000000)  /* Abort, and no DCL message.  */
-
-/* A couple of conditionals for execution machine are controlled here.  */
-#ifndef VMS
-#define VMS
-#endif
-
-#define GCC_INCLUDE_DIR ""
-/* Specify the list of include file directories.  */
-#define INCLUDE_DEFAULTS		\
-{					\
-  { "GNU_GXX_INCLUDE:", "G++", 1, 1 },	\
-  { "GNU_CC_INCLUDE:", "GCC", 0, 0 },	\
-  { ".", 0, 0, 1 },			\
-  { 0, 0, 0, 0 }			\
-}
-
-/* Define a local equivalent (sort of) for unlink */
-#define unlink remove
-
-#define NEED_ATEXIT
-#define HAVE_VPRINTF
-#define HAVE_PUTENV
-#define HAVE_STRERROR
-#define HAVE_ATOLL
-
-#define NO_SYS_PARAMS_H		/* Don't have <sys/params.h> */
-#define USE_C_ALLOCA		/* Using alloca.c */
-
-#define HAVE_FCNTL_H 1
-#define HAVE_STDLIB_H 1
-#define HAVE_UNISTD_H 1
-#define HAVE_STRING_H 1
-#define HAVE_LIMITS_H 1
-#define HAVE_STDDEF_H 1
-#define HAVE_TIME_H 1
-#define STDC_HEADERS 1
-#define HAVE_CPP_STRINGIFY 1
-
-#if __STDC__
-extern void *alloca (size_t);
-#else
-extern char *alloca (unsigned int);
-#endif
-
-#define OBJECT_SUFFIX ".obj"
-#define EXECUTABLE_SUFFIX ".exe"
diff --git a/gcc/config/alpha/xm-winnt.h b/gcc/config/alpha/xm-winnt.h
deleted file mode 100755
index f84be8d..0000000
--- a/gcc/config/alpha/xm-winnt.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Configuration for GNU compiler for an Alpha running Windows NT 3.x.
-   Copyright (C) 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Douglas B. Rupp (drupp@cs.washington.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef HOST_BITS_PER_LONG
-#define	HOST_BITS_PER_LONG	32
-
-#undef POSIX
-
-#define access _access
-#define close _close
-#define mktemp _mktemp
-#define open _open
-#define read _read
-#define write _write
-
-#undef HAS_INIT_SECTION
diff --git a/gcc/config/aoutos.h b/gcc/config/aoutos.h
deleted file mode 100755
index e9caa71..0000000
--- a/gcc/config/aoutos.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* aoutos.h  --  operating system specific defines to be used when
-   targeting GCC for some system that uses a.out file format.
-   Copyright (C) 1992 Free Software Foundation, Inc.
-
-   Written by Ron Guilmette (rfg@netcom.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* To use this file, make up a file with a name like:
-
-	?????aout.h
-
-   where ????? is replaced by the name of the basic hardware that you
-   are targeting for.  Then, in the file ?????aout.h, put something
-   like:
-
-	#include "?????.h"
-	#include "aoutos.h"
-
-   followed by any really system-specific defines (or overrides of
-   defines) which you find that you need.  Now, modify the configure
-   or configure.in script to properly use the new ?????aout.h file
-   when configuring for the system.  */
-
-/* Define a symbol indicating that we are using aoutos.h.  */
-#define USING_AOUTOS_H
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors. 
-   If using GNU LD, tell it that this is part of the static destructor set. 
-   This code works for any machine provided you use GNU as/ld.
-   If not using GNU LD, rely on a "collect" program to look for names defined
-   in the particular form we choose as global constructor function names.  */
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    if (flag_gnu_linker)						\
-      {									\
-	/* Output an N_SETT (0x16, 22.) for the name.  */		\
-	fprintf (FILE, "%s \"___CTOR_LIST__\",22,0,0,", ASM_STABS_OP);	\
-	assemble_name (FILE, NAME);					\
-	fputc ('\n', FILE);						\
-      }									\
-  } while (0)
-
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    if (flag_gnu_linker)						\
-      {									\
-	/* Output an N_SETT (0x16, 22.) for the name.  */		\
-	fprintf (FILE, "%s \"___DTOR_LIST__\",22,0,0,", ASM_STABS_OP);	\
-	assemble_name (FILE, NAME);					\
-	fputc ('\n', FILE);						\
-      }									\
-  } while (0)
-
-/* Likewise for entries we want to record for garbage collection.
-   Garbage collection is still under development.  */
-
-#define ASM_OUTPUT_GC_ENTRY(FILE,NAME)       				\
-  do {									\
-    if (flag_gnu_linker)						\
-      {									\
-	/* Output an N_SETT (0x16, 22.) for the name.  */		\
-	fprintf (FILE, "%s \"___PTR_LIST__\",22,0,0,", ASM_STABS_OP);	\
-	assemble_name (FILE, NAME);					\
-	fputc ('\n', FILE);						\
-      }									\
-  } while (0)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
deleted file mode 100755
index 64aec44..0000000
--- a/gcc/config/arc/arc.c
+++ /dev/null
@@ -1,2203 +0,0 @@
-/* Subroutines used for code generation on the Argonaut ARC cpu.
-   Copyright (C) 1994, 1995, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* ??? This is an old port, and is undoubtedly suffering from bit rot.  */
-
-#include <stdio.h>
-#include "config.h"
-#include "tree.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "expr.h"
-#include "recog.h"
-
-/* Which cpu we're compiling for (NULL(=base), ???).  */
-char *arc_cpu_string;
-int arc_cpu_type;
-
-/* Name of mangle string to add to symbols to separate code compiled for each
-   cpu (or NULL).  */
-char *arc_mangle_cpu;
-
-/* Save the operands last given to a compare for use when we
-   generate a scc or bcc insn.  */
-rtx arc_compare_op0, arc_compare_op1;
-
-/* Name of text, data, and rodata sections, as specified on command line.
-   Selected by -m{text,data,rodata} flags.  */
-char *arc_text_string = ARC_DEFAULT_TEXT_SECTION;
-char *arc_data_string = ARC_DEFAULT_DATA_SECTION;
-char *arc_rodata_string = ARC_DEFAULT_RODATA_SECTION;
-
-/* Name of text, data, and rodata sections used in varasm.c.  */
-char *arc_text_section;
-char *arc_data_section;
-char *arc_rodata_section;
-
-/* Array of valid operand punctuation characters.  */
-char arc_punct_chars[256];
-
-/* Variables used by arc_final_prescan_insn to implement conditional
-   execution.  */
-static int arc_ccfsm_state;
-static int arc_ccfsm_current_cc;
-static rtx arc_ccfsm_target_insn;
-static int arc_ccfsm_target_label;
-
-/* The maximum number of insns skipped which will be conditionalised if
-   possible.  */
-#define MAX_INSNS_SKIPPED 3
-
-/* A nop is needed between a 4 byte insn that sets the condition codes and
-   a branch that uses them (the same isn't true for an 8 byte insn that sets
-   the condition codes).  Set by arc_final_prescan_insn.  Used by
-   arc_print_operand.  */
-static int last_insn_set_cc_p;
-static int current_insn_set_cc_p;
-static void record_cc_ref ();
-
-void arc_init_reg_tables ();
-
-/* Called by OVERRIDE_OPTIONS to initialize various things.  */
-
-void
-arc_init (void)
-{
-  if (arc_cpu_string == 0
-      || !strcmp (arc_cpu_string, "base"))
-    {
-      /* Ensure we have a printable value for the .cpu pseudo-op.  */
-      arc_cpu_string = "base";
-      arc_cpu_type = 0;
-      arc_mangle_cpu = NULL;
-    }
-  else if (ARC_EXTENSION_CPU (arc_cpu_string))
-    ; /* nothing to do */
-  else
-    {
-      error ("bad value (%s) for -mcpu switch", arc_cpu_string);
-      arc_cpu_string = "base";
-      arc_cpu_type = 0;
-      arc_mangle_cpu = NULL;
-    }
-
-  /* Set the pseudo-ops for the various standard sections.  */
-  arc_text_section = xmalloc (strlen (arc_text_string) + sizeof (ARC_SECTION_FORMAT) + 1);
-  sprintf (arc_text_section, ARC_SECTION_FORMAT, arc_text_string);
-  arc_data_section = xmalloc (strlen (arc_data_string) + sizeof (ARC_SECTION_FORMAT) + 1);
-  sprintf (arc_data_section, ARC_SECTION_FORMAT, arc_data_string);
-  arc_rodata_section = xmalloc (strlen (arc_rodata_string) + sizeof (ARC_SECTION_FORMAT) + 1);
-  sprintf (arc_rodata_section, ARC_SECTION_FORMAT, arc_rodata_string);
-
-  arc_init_reg_tables ();
-
-  /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P.  */
-  memset (arc_punct_chars, 0, sizeof (arc_punct_chars));
-  arc_punct_chars['#'] = 1;
-  arc_punct_chars['*'] = 1;
-  arc_punct_chars['?'] = 1;
-  arc_punct_chars['!'] = 1;
-  arc_punct_chars['~'] = 1;
-}
-
-/* The condition codes of the ARC, and the inverse function.  */
-static char *arc_condition_codes[] =
-{
-  "al", 0, "eq", "ne", "p", "n", "c", "nc", "v", "nv",
-  "gt", "le", "ge", "lt", "hi", "ls", "pnz", 0
-};
-
-#define ARC_INVERSE_CONDITION_CODE(X)  ((X) ^ 1)
-
-/* Returns the index of the ARC condition code string in
-   `arc_condition_codes'.  COMPARISON should be an rtx like
-   `(eq (...) (...))'.  */
-
-static int
-get_arc_condition_code (comparison)
-     rtx comparison;
-{
-  switch (GET_CODE (comparison))
-    {
-    case EQ : return 2;
-    case NE : return 3;
-    case GT : return 10;
-    case LE : return 11;
-    case GE : return 12;
-    case LT : return 13;
-    case GTU : return 14;
-    case LEU : return 15;
-    case LTU : return 6;
-    case GEU : return 7;
-    default : abort ();
-    }
-  /*NOTREACHED*/
-  return (42);
-}
-
-/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
-   return the mode to be used for the comparison.  */
-
-enum machine_mode
-arc_select_cc_mode (op, x, y)
-     enum rtx_code op;
-     rtx x, y;
-{
-  switch (op)
-    {
-    case EQ :
-    case NE :
-      return CCZNmode;
-    default :
-      switch (GET_CODE (x))
-	{
-	case AND :
-	case IOR :
-	case XOR :
-	case SIGN_EXTEND :
-	case ZERO_EXTEND :
-	  return CCZNmode;
-	case ASHIFT :
-	case ASHIFTRT :
-	case LSHIFTRT :
-	  return CCZNCmode;
-	}
-    }
-  return CCmode;
-}
-
-/* Vectors to keep interesting information about registers where it can easily
-   be got.  We use to use the actual mode value as the bit number, but there
-   is (or may be) more than 32 modes now.  Instead we use two tables: one
-   indexed by hard register number, and one indexed by mode.  */
-
-/* The purpose of arc_mode_class is to shrink the range of modes so that
-   they all fit (as bit numbers) in a 32 bit word (again).  Each real mode is
-   mapped into one arc_mode_class mode.  */
-
-enum arc_mode_class {
-  C_MODE,
-  S_MODE, D_MODE, T_MODE, O_MODE,
-  SF_MODE, DF_MODE, TF_MODE, OF_MODE
-};
-
-/* Modes for condition codes.  */
-#define C_MODES (1 << (int) C_MODE)
-
-/* Modes for single-word and smaller quantities.  */
-#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
-
-/* Modes for double-word and smaller quantities.  */
-#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
-
-/* Modes for quad-word and smaller quantities.  */
-#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
-
-/* Value is 1 if register/mode pair is acceptable on arc.  */
-
-unsigned int arc_hard_regno_mode_ok[] = {
-  T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
-  T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
-  T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, D_MODES,
-  D_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
-
-  /* ??? Leave these as S_MODES for now.  */
-  S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
-  S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
-  S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
-  S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, C_MODES
-};
-
-unsigned int arc_mode_class [NUM_MACHINE_MODES];
-
-enum reg_class arc_regno_reg_class[FIRST_PSEUDO_REGISTER];
-
-void
-arc_init_reg_tables ()
-{
-  int i;
-
-  for (i = 0; i < NUM_MACHINE_MODES; i++)
-    {
-      switch (GET_MODE_CLASS (i))
-	{
-	case MODE_INT:
-	case MODE_PARTIAL_INT:
-	case MODE_COMPLEX_INT:
-	  if (GET_MODE_SIZE (i) <= 4)
-	    arc_mode_class[i] = 1 << (int) S_MODE;
-	  else if (GET_MODE_SIZE (i) == 8)
-	    arc_mode_class[i] = 1 << (int) D_MODE;
-	  else if (GET_MODE_SIZE (i) == 16)
-	    arc_mode_class[i] = 1 << (int) T_MODE;
-	  else if (GET_MODE_SIZE (i) == 32)
-	    arc_mode_class[i] = 1 << (int) O_MODE;
-	  else 
-	    arc_mode_class[i] = 0;
-	  break;
-	case MODE_FLOAT:
-	case MODE_COMPLEX_FLOAT:
-	  if (GET_MODE_SIZE (i) <= 4)
-	    arc_mode_class[i] = 1 << (int) SF_MODE;
-	  else if (GET_MODE_SIZE (i) == 8)
-	    arc_mode_class[i] = 1 << (int) DF_MODE;
-	  else if (GET_MODE_SIZE (i) == 16)
-	    arc_mode_class[i] = 1 << (int) TF_MODE;
-	  else if (GET_MODE_SIZE (i) == 32)
-	    arc_mode_class[i] = 1 << (int) OF_MODE;
-	  else 
-	    arc_mode_class[i] = 0;
-	  break;
-	case MODE_CC:
-	default:
-	  /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
-	     we must explicitly check for them here.  */
-	  if (i == (int) CCmode || i == (int) CCZNmode || i == (int) CCZNCmode)
-	    arc_mode_class[i] = 1 << (int) C_MODE;
-	  else
-	    arc_mode_class[i] = 0;
-	  break;
-	}
-    }
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      if (i < 60)
-	arc_regno_reg_class[i] = GENERAL_REGS;
-      else if (i == 60)
-	arc_regno_reg_class[i] = LPCOUNT_REG;
-      else if (i == 61)
-	arc_regno_reg_class[i] = NO_REGS /* CC_REG: must be NO_REGS */;
-      else
-	arc_regno_reg_class[i] = NO_REGS;
-    }
-}
-
-/* ARC specific attribute support.
-
-   The ARC has these attributes:
-   interrupt - for interrupt functions
-*/
-
-/* Return nonzero if IDENTIFIER is a valid decl attribute.  */
-
-int
-arc_valid_machine_decl_attribute (type, attributes, identifier, args)
-     tree type;
-     tree attributes;
-     tree identifier;
-     tree args;
-{
-  if (identifier == get_identifier ("__interrupt__")
-      && list_length (args) == 1
-      && TREE_CODE (TREE_VALUE (args)) == STRING_CST)
-    {
-      tree value = TREE_VALUE (args);
-
-      if (!strcmp (TREE_STRING_POINTER (value), "ilink1")
-	   || !strcmp (TREE_STRING_POINTER (value), "ilink2"))
-	return 1;
-    }
-  return 0;
-}
-
-/* Return zero if TYPE1 and TYPE are incompatible, one if they are compatible,
-   and two if they are nearly compatible (which causes a warning to be
-   generated).  */
-
-int
-arc_comp_type_attributes (type1, type2)
-     tree type1, type2;
-{
-  return 1;
-}
-
-/* Set the default attributes for TYPE.  */
-
-void
-arc_set_default_type_attributes (type)
-     tree type;
-{
-}
-
-/* Acceptable arguments to the call insn.  */
-
-int
-call_address_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (symbolic_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && LEGITIMATE_CONSTANT_P (op))
-	  || (GET_CODE (op) == REG));
-}
-
-int
-call_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != MEM)
-    return 0;
-  op = XEXP (op, 0);
-  return call_address_operand (op, mode);
-}
-
-/* Returns 1 if OP is a symbol reference.  */
-
-int
-symbolic_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case CONST :
-      return 1;
-    default:
-      return 0;
-    }
-}
-
-/* Return truth value of statement that OP is a symbolic memory
-   operand of mode MODE.  */
-
-int
-symbolic_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  if (GET_CODE (op) != MEM)
-    return 0;
-  op = XEXP (op, 0);
-  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
-	  || GET_CODE (op) == LABEL_REF);
-}
-
-/* Return true if OP is a short immediate (shimm) value.  */
-
-int
-short_immediate_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  return SMALL_INT (INTVAL (op));
-}
-
-/* Return true if OP will require a long immediate (limm) value.
-   This is currently only used when calculating length attributes.  */
-
-int
-long_immediate_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF :
-    case LABEL_REF :
-    case CONST :
-      return 1;
-    case CONST_INT :
-      return !SMALL_INT (INTVAL (op));
-    case CONST_DOUBLE :
-      /* These can happen because large unsigned 32 bit constants are
-	 represented this way (the multiplication patterns can cause these
-	 to be generated).  They also occur for SFmode values.  */
-      return 1;
-    }
-  return 0;
-}
-
-/* Return true if OP is a MEM that when used as a load or store address will
-   require an 8 byte insn.
-   Load and store instructions don't allow the same possibilities but they're
-   similar enough that this one function will do.
-   This is currently only used when calculating length attributes.  */
-
-int
-long_immediate_loadstore_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != MEM)
-    return 0;
-
-  op = XEXP (op, 0);
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF :
-    case LABEL_REF :
-    case CONST :
-      return 1;
-    case CONST_INT :
-      /* This must be handled as "st c,[limm]".  Ditto for load.
-	 Technically, the assembler could translate some possibilities to
-	 "st c,[limm/2 + limm/2]" if limm/2 will fit in a shimm, but we don't
-	 assume that it does.  */
-      return 1;
-    case CONST_DOUBLE :
-      /* These can happen because large unsigned 32 bit constants are
-	 represented this way (the multiplication patterns can cause these
-	 to be generated).  They also occur for SFmode values.  */
-      return 1;
-    case REG :
-      return 0;
-    case PLUS :
-      if (GET_CODE (XEXP (op, 1)) == CONST_INT
-	  && !SMALL_INT (INTVAL (XEXP (op, 1))))
-	return 1;
-      return 0;
-    }
-  return 0;
-}
-
-/* Return true if OP is an acceptable argument for a single word
-   move source.  */
-
-int
-move_src_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF :
-    case LABEL_REF :
-    case CONST :
-      return 1;
-    case CONST_INT :
-      return (LARGE_INT (INTVAL (op)));
-    case CONST_DOUBLE :
-      /* We can handle DImode integer constants in SImode if the value
-	 (signed or unsigned) will fit in 32 bits.  This is needed because
-	 large unsigned 32 bit constants are represented as CONST_DOUBLEs.  */
-      if (mode == SImode)
-	return arc_double_limm_p (op);
-      /* We can handle 32 bit floating point constants.  */
-      if (mode == SFmode)
-	return GET_MODE (op) == SFmode;
-      return 0;
-    case REG :
-      return register_operand (op, mode);
-    case SUBREG :
-      /* (subreg (mem ...) ...) can occur here if the inner part was once a
-	 pseudo-reg and is now a stack slot.  */
-      if (GET_CODE (SUBREG_REG (op)) == MEM)
-	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
-      else
-	return register_operand (op, mode);
-    case MEM :
-      return address_operand (XEXP (op, 0), mode);
-    default :
-      return 0;
-    }
-}
-
-/* Return true if OP is an acceptable argument for a double word
-   move source.  */
-
-int
-move_double_src_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case REG :
-      return register_operand (op, mode);
-    case SUBREG :
-      /* (subreg (mem ...) ...) can occur here if the inner part was once a
-	 pseudo-reg and is now a stack slot.  */
-      if (GET_CODE (SUBREG_REG (op)) == MEM)
-	return move_double_src_operand (SUBREG_REG (op), mode);
-      else
-	return register_operand (op, mode);
-    case MEM :
-      /* Disallow auto inc/dec for now.  */
-      if (GET_CODE (XEXP (op, 0)) == PRE_DEC
-	  || GET_CODE (XEXP (op, 0)) == PRE_INC)
-	return 0;
-      return address_operand (XEXP (op, 0), mode);
-    case CONST_INT :
-    case CONST_DOUBLE :
-      return 1;
-    default :
-      return 0;
-    }
-}
-
-/* Return true if OP is an acceptable argument for a move destination.  */
-
-int
-move_dest_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case REG :
-      return register_operand (op, mode);
-    case SUBREG :
-      /* (subreg (mem ...) ...) can occur here if the inner part was once a
-	 pseudo-reg and is now a stack slot.  */
-      if (GET_CODE (SUBREG_REG (op)) == MEM)
-	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
-      else
-	return register_operand (op, mode);
-    case MEM :
-      return address_operand (XEXP (op, 0), mode);
-    default :
-      return 0;
-    }
-}
-
-/* Return true if OP is valid load with update operand.  */
-
-int
-load_update_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != MEM
-      || GET_MODE (op) != mode)
-    return 0;
-  op = XEXP (op, 0);
-  if (GET_CODE (op) != PLUS
-      || GET_MODE (op) != Pmode
-      || !register_operand (XEXP (op, 0), Pmode)
-      || !nonmemory_operand (XEXP (op, 1), Pmode))
-    return 0;
-  return 1;
-}
-
-/* Return true if OP is valid store with update operand.  */
-
-int
-store_update_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != MEM
-      || GET_MODE (op) != mode)
-    return 0;
-  op = XEXP (op, 0);
-  if (GET_CODE (op) != PLUS
-      || GET_MODE (op) != Pmode
-      || !register_operand (XEXP (op, 0), Pmode)
-      || !(GET_CODE (XEXP (op, 1)) == CONST_INT
-	   && SMALL_INT (INTVAL (XEXP (op, 1)))))
-    return 0;
-  return 1;
-}
-
-/* Return true if OP is a non-volatile non-immediate operand.
-   Volatile memory refs require a special "cache-bypass" instruction
-   and only the standard movXX patterns are set up to handle them.  */
-
-int
-nonvol_nonimm_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == MEM && MEM_VOLATILE_P (op))
-    return 0;
-  return nonimmediate_operand (op, mode);
-}
-
-/* Accept integer operands in the range -0x80000000..0x7fffffff.  We have
-   to check the range carefully since this predicate is used in DImode
-   contexts.  */
-
-int
-const_sint32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  /* All allowed constants will fit a CONST_INT.  */
-  return (GET_CODE (op) == CONST_INT
-	  && (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
-}
-
-/* Accept integer operands in the range 0..0xffffffff.  We have to check the
-   range carefully since this predicate is used in DImode contexts.  Also, we
-   need some extra crud to make it work when hosted on 64-bit machines.  */
-
-int
-const_uint32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-#if HOST_BITS_PER_WIDE_INT > 32
-  /* All allowed constants will fit a CONST_INT.  */
-  return (GET_CODE (op) == CONST_INT
-	  && (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
-#else
-  return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0)
-	  || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
-#endif
-}
-
-/* Return 1 if OP is a comparison operator valid for the mode of CC.
-   This allows the use of MATCH_OPERATOR to recognize all the branch insns.
-
-   Some insns only set a few bits in the condition code.  So only allow those
-   comparisons that use the bits that are valid.  */
-
-int
-proper_comparison_operator (op, mode)
-    rtx op;
-    enum machine_mode mode;
-{
-  enum rtx_code code = GET_CODE (op);
-
-  if (GET_RTX_CLASS (code) != '<')
-    return 0;
-
-  if (GET_MODE (XEXP (op, 0)) == CCZNmode)
-    return (code == EQ || code == NE);
-  if (GET_MODE (XEXP (op, 0)) == CCZNCmode)
-    return (code == EQ || code == NE
-	    || code == LTU || code == GEU || code == GTU || code == LEU);
-  return 1;
-}
-
-/* Misc. utilities.  */
-
-/* X and Y are two things to compare using CODE.  Emit the compare insn and
-   return the rtx for the cc reg in the proper mode.  */
-
-rtx
-gen_compare_reg (code, x, y)
-     enum rtx_code code;
-     rtx x, y;
-{
-  enum machine_mode mode = SELECT_CC_MODE (code, x, y);
-  rtx cc_reg;
-
-  cc_reg = gen_rtx (REG, mode, 61);
-
-  emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
-		      gen_rtx (COMPARE, mode, x, y)));
-
-  return cc_reg;
-}
-
-/* Return 1 if VALUE, a const_double, will fit in a limm (4 byte number).
-   We assume the value can be either signed or unsigned.  */
-
-int
-arc_double_limm_p (value)
-     rtx value;
-{
-  HOST_WIDE_INT low, high;
-
-  if (GET_CODE (value) != CONST_DOUBLE)
-    abort ();
-
-  low = CONST_DOUBLE_LOW (value);
-  high = CONST_DOUBLE_HIGH (value);
-
-  if (low & 0x80000000)
-    {
-      return (((unsigned HOST_WIDE_INT) low <= 0xffffffff && high == 0)
-	      || (((low & - (unsigned HOST_WIDE_INT) 0x80000000)
-		   == - (unsigned HOST_WIDE_INT) 0x80000000)
-		  && high == -1));
-    }
-  else
-    {
-      return (unsigned HOST_WIDE_INT) low <= 0x7fffffff && high == 0;
-    }
-}
-
-/* Do any needed setup for a variadic function.  For the ARC, we must
-   create a register parameter block, and then copy any anonymous arguments
-   in registers to memory.
-
-   CUM has not been updated for the last named argument which has type TYPE
-   and mode MODE, and we rely on this fact.
-
-   We do things a little weird here.  We're supposed to only allocate space
-   for the anonymous arguments.  However we need to keep the stack eight byte
-   aligned.  So we round the space up if necessary, and leave it to va-arc.h
-   to compensate.  */
-
-void
-arc_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int *pretend_size;
-     int no_rtl;
-{
-  int first_anon_arg;
-
-  /* All BLKmode values are passed by reference.  */
-  if (mode == BLKmode)
-    abort ();
-
-  /* We must treat `__builtin_va_alist' as an anonymous arg.  */
-  if (current_function_varargs)
-    first_anon_arg = *cum;
-  else
-    first_anon_arg = *cum + ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
-			     / UNITS_PER_WORD);
-
-  if (first_anon_arg < MAX_ARC_PARM_REGS && !no_rtl)
-    {
-      /* Note that first_reg_offset < MAX_ARC_PARM_REGS.  */
-      int first_reg_offset = first_anon_arg;
-      /* Size in words to "pretend" allocate.  */
-      int size = MAX_ARC_PARM_REGS - first_reg_offset;
-      /* Extra slop to keep stack eight byte aligned.  */
-      int align_slop = size & 1;
-      rtx regblock;
-
-      regblock = gen_rtx (MEM, BLKmode,
-			  plus_constant (arg_pointer_rtx,
-					 FIRST_PARM_OFFSET (0)
-					 + align_slop * UNITS_PER_WORD));
-      move_block_from_reg (first_reg_offset, regblock,
-			   MAX_ARC_PARM_REGS - first_reg_offset,
-			   ((MAX_ARC_PARM_REGS - first_reg_offset)
-			    * UNITS_PER_WORD));
-
-      *pretend_size = ((MAX_ARC_PARM_REGS - first_reg_offset + align_slop)
-		       * UNITS_PER_WORD);
-    }
-}
-
-/* Cost functions.  */
-
-/* Provide the costs of an addressing mode that contains ADDR.
-   If ADDR is not a valid address, its cost is irrelevant.  */
-
-int
-arc_address_cost (addr)
-     rtx addr;
-{
-  switch (GET_CODE (addr))
-    {
-    case REG :
-      /* This is handled in the macro that calls us.
-	 It's here for documentation.  */
-      return 1;
-
-    case LABEL_REF :
-    case SYMBOL_REF :
-    case CONST :
-      return 2;
-
-    case PLUS :
-      {
-	register rtx plus0 = XEXP (addr, 0);
-	register rtx plus1 = XEXP (addr, 1);
-
-	if (GET_CODE (plus0) != REG)
-	  break;
-
-	switch (GET_CODE (plus1))
-	  {
-	  case CONST_INT :
-	    return SMALL_INT (plus1) ? 1 : 2;
-	  case CONST :
-	  case SYMBOL_REF :
-	  case LABEL_REF :
-	    return 2;
-	  default:
-	    break;
-	  }
-	break;
-      }
-    }
-
-  return 4;
-}
-
-/* Function prologue/epilogue handlers.  */
-
-/* ARC stack frames look like:
-
-             Before call                       After call
-        +-----------------------+       +-----------------------+
-        |                       |       |                       |
-   high |  local variables,     |       |  local variables,     |
-   mem  |  reg save area, etc.  |       |  reg save area, etc.  |
-        |                       |       |                       |
-        +-----------------------+       +-----------------------+
-        |                       |       |                       |
-        |  arguments on stack.  |       |  arguments on stack.  |
-        |                       |       |                       |
- SP+16->+-----------------------+FP+48->+-----------------------+
-        | 4 word save area for  |       |  reg parm save area,  |
-        | return addr, prev %fp |       |  only created for     |    
-  SP+0->+-----------------------+       |  variable argument    |    
-                                        |  functions            |    
-                                 FP+16->+-----------------------+    
-                                        | 4 word save area for  |    
-                                        | return addr, prev %fp |    
-                                  FP+0->+-----------------------+    
-                                        |                       |    
-                                        |  local variables      |    
-                                        |                       |    
-                                        +-----------------------+    
-                                        |                       |    
-                                        |  register save area   |    
-                                        |                       |    
-                                        +-----------------------+    
-                                        |                       |    
-                                        |  alloca allocations   |    
-                                        |                       |    
-                                        +-----------------------+    
-                                        |                       |    
-                                        |  arguments on stack   |    
-                                        |                       |    
-                                 SP+16->+-----------------------+
-   low                                  | 4 word save area for  |    
-   memory                               | return addr, prev %fp |    
-                                  SP+0->+-----------------------+    
-
-Notes:
-1) The "reg parm save area" does not exist for non variable argument fns.
-   The "reg parm save area" can be eliminated completely if we created our
-   own va-arc.h, but that has tradeoffs as well (so it's not done).  */
-
-/* Structure to be filled in by arc_compute_frame_size with register
-   save masks, and offsets for the current function.  */
-struct arc_frame_info
-{
-  unsigned int total_size;	/* # bytes that the entire frame takes up.  */
-  unsigned int extra_size;	/* # bytes of extra stuff.  */
-  unsigned int pretend_size;	/* # bytes we push and pretend caller did.  */
-  unsigned int args_size;	/* # bytes that outgoing arguments take up.  */
-  unsigned int reg_size;	/* # bytes needed to store regs.  */
-  unsigned int var_size;	/* # bytes that variables take up.  */
-  unsigned int reg_offset;	/* Offset from new sp to store regs.  */
-  unsigned int gmask;		/* Mask of saved gp registers.  */
-  int          initialized;	/* Nonzero if frame size already calculated.  */
-};
-
-/* Current frame information calculated by arc_compute_frame_size.  */
-static struct arc_frame_info current_frame_info;
-
-/* Zero structure to initialize current_frame_info.  */
-static struct arc_frame_info zero_frame_info;
-
-/* Type of function DECL.
-
-   The result is cached.  To reset the cache at the end of a function,
-   call with DECL = NULL_TREE.  */
-
-enum arc_function_type
-arc_compute_function_type (decl)
-     tree decl;
-{
-  tree a;
-  /* Cached value.  */
-  static enum arc_function_type fn_type = ARC_FUNCTION_UNKNOWN;
-  /* Last function we were called for.  */
-  static tree last_fn = NULL_TREE;
-
-  /* Resetting the cached value?  */
-  if (decl == NULL_TREE)
-    {
-      fn_type = ARC_FUNCTION_UNKNOWN;
-      last_fn = NULL_TREE;
-      return fn_type;
-    }
-
-  if (decl == last_fn && fn_type != ARC_FUNCTION_UNKNOWN)
-    return fn_type;
-
-  /* Assume we have a normal function (not an interrupt handler).  */
-  fn_type = ARC_FUNCTION_NORMAL;
-
-  /* Now see if this is an interrupt handler.  */
-  for (a = DECL_MACHINE_ATTRIBUTES (current_function_decl);
-       a;
-       a = TREE_CHAIN (a))
-    {
-      tree name = TREE_PURPOSE (a), args = TREE_VALUE (a);
-
-      if (name == get_identifier ("__interrupt__")
-	  && list_length (args) == 1
-	  && TREE_CODE (TREE_VALUE (args)) == STRING_CST)
-	{
-	  tree value = TREE_VALUE (args);
-
-	  if (!strcmp (TREE_STRING_POINTER (value), "ilink1"))
-	    fn_type = ARC_FUNCTION_ILINK1;
-	  else if (!strcmp (TREE_STRING_POINTER (value), "ilink2"))
-	    fn_type = ARC_FUNCTION_ILINK2;
-	  else
-	    abort ();
-	  break;
-	}
-    }
-
-  last_fn = decl;
-  return fn_type;
-}
-
-#define ILINK1_REGNUM 29
-#define ILINK2_REGNUM 30
-#define RETURN_ADDR_REGNUM 31
-#define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
-#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
-
-/* Tell prologue and epilogue if register REGNO should be saved / restored.
-   The return address and frame pointer are treated separately.
-   Don't consider them here.  */
-#define MUST_SAVE_REGISTER(regno, interrupt_p) \
-((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
- && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
-
-#define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM])
-
-/* Return the bytes needed to compute the frame pointer from the current
-   stack pointer.
-
-   SIZE is the size needed for local variables.  */
-
-unsigned int
-arc_compute_frame_size (size)
-     int size;			/* # of var. bytes allocated.  */
-{
-  int regno;
-  unsigned int total_size, var_size, args_size, pretend_size, extra_size;
-  unsigned int reg_size, reg_offset;
-  unsigned int gmask;
-  enum arc_function_type fn_type;
-  int interrupt_p;
-
-  var_size	= size;
-  args_size	= current_function_outgoing_args_size;
-  pretend_size	= current_function_pretend_args_size;
-  extra_size	= FIRST_PARM_OFFSET (0);
-  total_size	= extra_size + pretend_size + args_size + var_size;
-  reg_offset	= FIRST_PARM_OFFSET(0) + current_function_outgoing_args_size;
-  reg_size	= 0;
-  gmask		= 0;
-
-  /* See if this is an interrupt handler.  Call used registers must be saved
-     for them too.  */
-  fn_type = arc_compute_function_type (current_function_decl);
-  interrupt_p = ARC_INTERRUPT_P (fn_type);
-
-  /* Calculate space needed for registers.
-     ??? We ignore the extension registers for now.  */
-
-  for (regno = 0; regno <= 31; regno++)
-    {
-      if (MUST_SAVE_REGISTER (regno, interrupt_p))
-	{
-	  reg_size += UNITS_PER_WORD;
-	  gmask |= 1 << regno;
-	}
-    }
-
-  total_size += reg_size;
-
-  /* If the only space to allocate is the fp/blink save area this is an
-     empty frame.  However, if we'll be making a function call we need to
-     allocate a stack frame for our callee's fp/blink save area.  */
-  if (total_size == extra_size
-      && !MUST_SAVE_RETURN_ADDR)
-    total_size = extra_size = 0;
-
-  total_size = ARC_STACK_ALIGN (total_size);
-
-  /* Save computed information.  */
-  current_frame_info.total_size   = total_size;
-  current_frame_info.extra_size   = extra_size;
-  current_frame_info.pretend_size = pretend_size;
-  current_frame_info.var_size     = var_size;
-  current_frame_info.args_size    = args_size;
-  current_frame_info.reg_size	  = reg_size;
-  current_frame_info.reg_offset	  = reg_offset;
-  current_frame_info.gmask	  = gmask;
-  current_frame_info.initialized  = reload_completed;
-
-  /* Ok, we're done.  */
-  return total_size;
-}
-
-/* Common code to save/restore registers.  */
-
-void
-arc_save_restore (file, base_reg, offset, gmask, op)
-     FILE *file;
-     char *base_reg;
-     unsigned int offset;
-     unsigned int gmask;
-     char *op;
-{
-  int regno;
-
-  if (gmask == 0)
-    return;
-
-  for (regno = 0; regno <= 31; regno++)
-    {
-      if ((gmask & (1L << regno)) != 0)
-	{
-	  fprintf (file, "\t%s %s,[%s,%d]\n",
-		     op, reg_names[regno], base_reg, offset);
-	  offset += UNITS_PER_WORD;
-	}
-    }
-}
-
-/* Set up the stack and frame pointer (if desired) for the function.  */
-
-void
-arc_output_function_prologue (file, size)
-     FILE *file;
-     int size;
-{
-  char *sp_str = reg_names[STACK_POINTER_REGNUM];
-  char *fp_str = reg_names[FRAME_POINTER_REGNUM];
-  unsigned int gmask = current_frame_info.gmask;
-  enum arc_function_type fn_type = arc_compute_function_type (current_function_decl);
-
-  /* If this is an interrupt handler, set up our stack frame.
-     ??? Optimize later.  */
-  if (ARC_INTERRUPT_P (fn_type))
-    {
-      fprintf (file, "\t%s interrupt handler\n",
-	       ASM_COMMENT_START);
-      fprintf (file, "\tsub %s,%s,16\n", sp_str, sp_str);
-    }
-
-  /* This is only for the human reader.  */
-  fprintf (file, "\t%s BEGIN PROLOGUE %s vars= %d, regs= %d, args= %d, extra= %d\n",
-	   ASM_COMMENT_START, ASM_COMMENT_START,
-	   current_frame_info.var_size,
-	   current_frame_info.reg_size / 4,
-	   current_frame_info.args_size,
-	   current_frame_info.extra_size);
-
-  size = ARC_STACK_ALIGN (size);
-  size = (! current_frame_info.initialized
-	   ? arc_compute_frame_size (size)
-	   : current_frame_info.total_size);
-
-  /* These cases shouldn't happen.  Catch them now.  */
-  if (size == 0 && gmask)
-    abort ();
-
-  /* Allocate space for register arguments if this is a variadic function.  */
-  if (current_frame_info.pretend_size != 0)
-    fprintf (file, "\tsub %s,%s,%d\n",
-	     sp_str, sp_str, current_frame_info.pretend_size);
-
-  /* The home-grown ABI says link register is saved first.  */
-  if (MUST_SAVE_RETURN_ADDR)
-    fprintf (file, "\tst %s,[%s,%d]\n",
-	     reg_names[RETURN_ADDR_REGNUM], sp_str, UNITS_PER_WORD);
-
-  /* Set up the previous frame pointer next (if we need to).  */
-  if (frame_pointer_needed)
-    {
-      fprintf (file, "\tst %s,[%s]\n", fp_str, sp_str);
-      fprintf (file, "\tmov %s,%s\n", fp_str, sp_str);
-    }
-
-  /* ??? We don't handle the case where the saved regs are more than 252
-     bytes away from sp.  This can be handled by decrementing sp once, saving
-     the regs, and then decrementing it again.  The epilogue doesn't have this
-     problem as the `ld' insn takes reg+limm values (though it would be more
-     efficient to avoid reg+limm).  */
-
-  /* Allocate the stack frame.  */
-  if (size - current_frame_info.pretend_size > 0)
-    fprintf (file, "\tsub %s,%s,%d\n",
-	     sp_str, sp_str, size - current_frame_info.pretend_size);
-
-  /* Save any needed call-saved regs (and call-used if this is an
-     interrupt handler).  */
-  arc_save_restore (file, sp_str, current_frame_info.reg_offset,
-		    /* The zeroing of these two bits is unnecessary,
-		       but leave this in for clarity.  */
-		    gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
-		    "st");
-
-  fprintf (file, "\t%s END PROLOGUE\n", ASM_COMMENT_START);
-}
-
-/* Do any necessary cleanup after a function to restore stack, frame,
-   and regs. */
-
-void
-arc_output_function_epilogue (file, size)
-     FILE *file;
-     int size;
-{
-  rtx epilogue_delay = current_function_epilogue_delay_list;
-  int noepilogue = FALSE;
-  enum arc_function_type fn_type = arc_compute_function_type (current_function_decl);
-
-  /* This is only for the human reader.  */
-  fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
-
-  size = ARC_STACK_ALIGN (size);
-  size = (!current_frame_info.initialized
-	   ? arc_compute_frame_size (size)
-	   : current_frame_info.total_size);
-
-  if (size == 0 && epilogue_delay == 0)
-    {
-      rtx insn = get_last_insn ();
-
-      /* If the last insn was a BARRIER, we don't have to write any code
-	 because a jump (aka return) was put there.  */
-      if (GET_CODE (insn) == NOTE)
-	insn = prev_nonnote_insn (insn);
-      if (insn && GET_CODE (insn) == BARRIER)
-	noepilogue = TRUE;
-    }
-
-  if (!noepilogue)
-    {
-      unsigned int pretend_size = current_frame_info.pretend_size;
-      unsigned int frame_size = size - pretend_size;
-      int restored, fp_restored_p;
-      int can_trust_sp_p = !current_function_calls_alloca;
-      char *sp_str = reg_names[STACK_POINTER_REGNUM];
-      char *fp_str = reg_names[FRAME_POINTER_REGNUM];
-
-      /* ??? There are lots of optimizations that can be done here.
-	 EG: Use fp to restore regs if it's closer.
-	 Maybe in time we'll do them all.  For now, always restore regs from
-	 sp, but don't restore sp if we don't have to.  */
-
-      if (!can_trust_sp_p)
-	{
-	  if (!frame_pointer_needed)
-	    abort ();
-	  fprintf (file,"\tsub %s,%s,%d\t\t%s sp not trusted here\n",
-		   sp_str, fp_str, frame_size, ASM_COMMENT_START);
-	}
-
-      /* Restore any saved registers.  */
-      arc_save_restore (file, sp_str, current_frame_info.reg_offset,
-			/* The zeroing of these two bits is unnecessary,
-			   but leave this in for clarity.  */
-			current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
-			"ld");
-
-      if (MUST_SAVE_RETURN_ADDR)
-	fprintf (file, "\tld %s,[%s,%d]\n",
-		 reg_names[RETURN_ADDR_REGNUM],
-		 frame_pointer_needed ? fp_str : sp_str,
-		 UNITS_PER_WORD + (frame_pointer_needed ? 0 : frame_size));
-
-      /* Keep track of how much of the stack pointer we've restored.
-	 It makes the following a lot more readable.  */
-      restored = 0;
-      fp_restored_p = 0;
-
-      /* We try to emit the epilogue delay slot insn right after the load
-	 of the return address register so that it can execute with the
-	 stack intact.  Secondly, loads are delayed.  */
-      /* ??? If stack intactness is important, always emit now.  */
-      if (MUST_SAVE_RETURN_ADDR && epilogue_delay != NULL_RTX)
-	{
-	  final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
-	  epilogue_delay = NULL_RTX;
-	}
-
-      if (frame_pointer_needed)
-	{
-	  /* Try to restore the frame pointer in the delay slot.  We can't,
-	     however, if any of these is true.  */
-	  if (epilogue_delay != NULL_RTX
-	      || !SMALL_INT (frame_size)
-	      || pretend_size
-	      || ARC_INTERRUPT_P (fn_type))
-	    {
-	      /* Note that we restore fp and sp here!  */
-	      fprintf (file, "\tld.a %s,[%s,%d]\n", fp_str, sp_str, frame_size);
-	      restored += frame_size;
-	      fp_restored_p = 1;
-	    }
-	}
-      else if (!SMALL_INT (size /* frame_size + pretend_size */)
-	       || ARC_INTERRUPT_P (fn_type))
-	{
-	  fprintf (file, "\tadd %s,%s,%d\n", sp_str, sp_str, frame_size);
-	  restored += frame_size;
-	}
-
-      /* These must be done before the return insn because the delay slot
-	 does the final stack restore.  */
-      if (ARC_INTERRUPT_P (fn_type))
-	{
-	  if (epilogue_delay)
-	    {
-	      final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
-	    }
-	}
-
-      /* Emit the return instruction.  */
-      {
-	static int regs[4] = {
-	  0, RETURN_ADDR_REGNUM, ILINK1_REGNUM, ILINK2_REGNUM
-	};
-	fprintf (file, "\tj.d %s\n", reg_names[regs[fn_type]]);
-      }
-
-      /* If the only register saved is the return address, we need a
-	 nop, unless we have an instruction to put into it.  Otherwise
-	 we don't since reloading multiple registers doesn't reference
-	 the register being loaded.  */
-
-      if (ARC_INTERRUPT_P (fn_type))
-	fprintf (file, "\tadd %s,%s,16\n", sp_str, sp_str);
-      else if (epilogue_delay != NULL_RTX)
-	{
-	  if (frame_pointer_needed && !fp_restored_p)
-	    abort ();
-	  if (restored < size)
-	    abort ();
-	  final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
-	}
-      else if (frame_pointer_needed && !fp_restored_p)
-	{
-	  if (!SMALL_INT (frame_size))
-	    abort ();
-	  /* Note that we restore fp and sp here!  */
-	  fprintf (file, "\tld.a %s,[%s,%d]\n", fp_str, sp_str, frame_size);
-	}
-      else if (restored < size)
-	{
-	  if (!SMALL_INT (size - restored))
-	    abort ();
-	  fprintf (file, "\tadd %s,%s,%d\n",
-		   sp_str, sp_str, size - restored);
-	}
-      else
-	fprintf (file, "\tnop\n");
-    }
-
-  /* Reset state info for each function.  */
-  current_frame_info = zero_frame_info;
-  arc_compute_function_type (NULL_TREE);
-}
-
-/* Define the number of delay slots needed for the function epilogue.
-
-   Interrupt handlers can't have any epilogue delay slots (it's always needed
-   for something else, I think).  For normal functions, we have to worry about
-   using call-saved regs as they'll be restored before the delay slot insn.
-   Functions with non-empty frames already have enough choices for the epilogue
-   delay slot so for now we only consider functions with empty frames.  */
-
-int
-arc_delay_slots_for_epilogue ()
-{
-  if (arc_compute_function_type (current_function_decl) != ARC_FUNCTION_NORMAL)
-    return 0;
-  if (!current_frame_info.initialized)
-    (void) arc_compute_frame_size (get_frame_size ());
-  if (current_frame_info.total_size == 0)
-    return 1;
-  return 0;
-}
-
-/* Return true if TRIAL is a valid insn for the epilogue delay slot.
-   Any single length instruction which doesn't reference the stack or frame
-   pointer or any call-saved register is OK.  SLOT will always be 0.  */
-
-int
-arc_eligible_for_epilogue_delay (trial, slot)
-     rtx trial;
-     int slot;
-{
-  if (slot != 0)
-    abort ();
-
-  if (get_attr_length (trial) == 1
-      /* If registers where saved, presumably there's more than enough
-	 possibilities for the delay slot.  The alternative is something
-	 more complicated (of course, if we expanded the epilogue as rtl
-	 this problem would go away).  */
-      /* ??? Note that this will always be true since only functions with
-	 empty frames have epilogue delay slots.  See
-	 arc_delay_slots_for_epilogue.  */
-      && current_frame_info.gmask == 0
-      && ! reg_mentioned_p (stack_pointer_rtx, PATTERN (trial))
-      && ! reg_mentioned_p (frame_pointer_rtx, PATTERN (trial)))
-    return 1;
-  return 0;
-}
-
-/* PIC */
-
-/* Emit special PIC prologues and epilogues.  */
-
-void
-arc_finalize_pic ()
-{
-  /* nothing to do */
-}
-
-/* Return true if OP is a shift operator.  */
-
-int
-shift_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case ASHIFTRT:
-    case LSHIFTRT:
-    case ASHIFT:
-      return 1;
-    default:
-      return 0;
-    }
-}
-
-/* Output the assembler code for doing a shift.
-   We go to a bit of trouble to generate efficient code as the ARC only has
-   single bit shifts.  This is taken from the h8300 port.  We only have one
-   mode of shifting and can't access individual bytes like the h8300 can, so
-   this is greatly simplified (at the expense of not generating hyper-
-   efficient code).
-
-   This function is not used if the variable shift insns are present.  */
-
-/* ??? We assume the output operand is the same as operand 1.
-   This can be optimized (deleted) in the case of 1 bit shifts.  */
-/* ??? We use the loop register here.  We don't use it elsewhere (yet) and
-   using it here will give us a chance to play with it.  */
-
-char *
-output_shift (operands)
-     rtx *operands;
-{
-  static int loopend_lab;
-  rtx shift = operands[3];
-  enum machine_mode mode = GET_MODE (shift);
-  enum rtx_code code = GET_CODE (shift);
-  char *shift_one;
-
-  if (mode != SImode)
-    abort ();
-
-  switch (code)
-    {
-    case ASHIFT:   shift_one = "asl %0,%0"; break;
-    case ASHIFTRT: shift_one = "asr %0,%0"; break;
-    case LSHIFTRT: shift_one = "lsr %0,%0"; break;
-    default:       abort ();
-    }
-
-  if (GET_CODE (operands[2]) != CONST_INT)
-    {
-      if (optimize)
-	output_asm_insn ("mov lp_count,%2", operands);
-      else
-	output_asm_insn ("mov %4,%2", operands);
-      goto shiftloop;
-    }
-  else
-    {
-      int n = INTVAL (operands[2]);
-
-      /* If the count is negative, make it 0.  */
-      if (n < 0)
-	n = 0;
-      /* If the count is too big, truncate it.
-         ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
-	 do the intuitive thing.  */
-      else if (n > GET_MODE_BITSIZE (mode))
-	n = GET_MODE_BITSIZE (mode);
-
-      /* First see if we can do them inline.  */
-      if (n <= 8)
-	{
-	  while (--n >= 0)
-	    output_asm_insn (shift_one, operands);
-	}
-      /* See if we can use a rotate/and.  */
-      else if (n == BITS_PER_WORD - 1)
-	{
-	  switch (code)
-	    {
-	    case ASHIFT :
-	      output_asm_insn ("and %0,%0,1\n\tror %0,%0", operands);
-	      break;
-	    case ASHIFTRT :
-	      /* The ARC doesn't have a rol insn.  Use something else.  */
-	      output_asm_insn ("asl.f 0,%0\n\tsbc %0,0,0", operands);
-	      break;
-	    case LSHIFTRT :
-	      /* The ARC doesn't have a rol insn.  Use something else.  */
-	      output_asm_insn ("asl.f 0,%0\n\tadc %0,0,0", operands);
-	      break;
-	    }
-	}
-      /* Must loop.  */
-      else
-	{
-	  char buf[100];
-
-	  if (optimize)
-	    output_asm_insn ("mov lp_count,%c2", operands);
-	  else
-	    output_asm_insn ("mov %4,%c2", operands);
-	shiftloop:
-	  if (optimize)
-	    {
-	      if (flag_pic)
-		sprintf ("lr %%4,[status]\n\tadd %%4,%%4,6\t%s single insn loop start",
-			 ASM_COMMENT_START);
-	      else
-		sprintf (buf, "mov %%4,%%%%st(1f)\t%s (single insn loop start) >> 2",
-			 ASM_COMMENT_START);
-	      output_asm_insn (buf, operands);
-	      output_asm_insn ("sr %4,[lp_start]", operands);
-	      output_asm_insn ("add %4,%4,1", operands);
-	      output_asm_insn ("sr %4,[lp_end]", operands);
-	      output_asm_insn ("nop\n\tnop", operands);
-	      if (flag_pic)
-		asm_fprintf (asm_out_file, "\t%s single insn loop\n",
-			     ASM_COMMENT_START);
-	      else
-		asm_fprintf (asm_out_file, "1:\t%s single insn loop\n",
-			     ASM_COMMENT_START);
-	      output_asm_insn (shift_one, operands);
-	    }
-	  else 
-	    {
-	      asm_fprintf (asm_out_file, "1:\t%s begin shift loop\n",
-			   ASM_COMMENT_START);
-	      output_asm_insn ("sub.f %4,%4,1", operands);
-	      output_asm_insn ("nop", operands);
-	      output_asm_insn ("bn.nd 2f", operands);
-	      output_asm_insn (shift_one, operands);
-	      output_asm_insn ("b.nd 1b", operands);
-	      asm_fprintf (asm_out_file, "2:\t%s end shift loop\n",
-			   ASM_COMMENT_START);
-	    }
-	}
-    }
-
-  return "";
-}
-
-/* Nested function support.  */
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-void
-arc_initialize_trampoline (tramp, fnaddr, cxt)
-     rtx tramp, fnaddr, cxt;
-{
-}
-
-/* Set the cpu type and print out other fancy things,
-   at the top of the file.  */
-
-void
-arc_asm_file_start (file)
-     FILE *file;
-{
-  fprintf (file, "\t.cpu %s\n", arc_cpu_string);
-}
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-void
-arc_print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
-{
-  switch (code)
-    {
-    case '#' :
-      /* Conditional branches.  For now these are equivalent.  */
-    case '*' :
-      /* Unconditional branches.  Output the appropriate delay slot suffix.  */
-      if (!final_sequence || XVECLEN (final_sequence, 0) == 1)
-	{
-	  /* There's nothing in the delay slot.  */
-	  fputs (".nd", file);
-	}
-      else
-	{
-	  rtx jump = XVECEXP (final_sequence, 0, 0);
-	  rtx delay = XVECEXP (final_sequence, 0, 1);
-	  if (INSN_ANNULLED_BRANCH_P (jump))
-	    fputs (INSN_FROM_TARGET_P (delay) ? ".jd" : ".nd", file);
-	  else
-	    fputs (".d", file);
-	}
-      return;
-    case '?' : /* with leading "." */
-    case '!' : /* without leading "." */
-      /* This insn can be conditionally executed.  See if the ccfsm machinery
-	 says it should be conditionalized.  */
-      if (arc_ccfsm_state == 3 || arc_ccfsm_state == 4)
-	{
-	  /* Is this insn in a delay slot?  */
-	  if (final_sequence && XVECLEN (final_sequence, 0) == 2)
-	    {
-	      rtx insn = XVECEXP (final_sequence, 0, 1);
-
-	      /* If the insn is annulled and is from the target path, we need
-		 to inverse the condition test.  */
-	      if (INSN_ANNULLED_BRANCH_P (insn))
-		{
-		  if (INSN_FROM_TARGET_P (insn))
-		    fprintf (file, "%s%s",
-			     code == '?' ? "." : "",
-			     arc_condition_codes[ARC_INVERSE_CONDITION_CODE (arc_ccfsm_current_cc)]);
-		  else
-		    fprintf (file, "%s%s",
-			     code == '?' ? "." : "",
-			     arc_condition_codes[arc_ccfsm_current_cc]);
-		}
-	      else
-		/* This insn is executed for either path, so don't
-		   conditionalize it at all.  */
-		; /* nothing to do */
-	    }
-	  else
-	    {
-	      /* This insn isn't in a delay slot.  */
-	      fprintf (file, "%s%s",
-		       code == '?' ? "." : "",
-		       arc_condition_codes[arc_ccfsm_current_cc]);
-	    }
-	}
-      return;
-    case '~' :
-      /* Output a nop if we're between a set of the condition codes,
-	 and a conditional branch.  */
-      if (last_insn_set_cc_p)
-	fputs ("nop\n\t", file);
-      return;
-    case 'd' :
-      fputs (arc_condition_codes[get_arc_condition_code (x)], file);
-      return;
-    case 'D' :
-      fputs (arc_condition_codes[ARC_INVERSE_CONDITION_CODE
-				 (get_arc_condition_code (x))],
-	     file);
-      return;
-    case 'R' :
-      /* Write second word of DImode or DFmode reference,
-	 register or memory.  */
-      if (GET_CODE (x) == REG)
-	fputs (reg_names[REGNO (x)+1], file);
-      else if (GET_CODE (x) == MEM)
-	{
-	  fputc ('[', file);
-	  /* Handle possible auto-increment.  Since it is pre-increment and
-	     we have already done it, we can just use an offset of four.  */
-	  /* ??? This is taken from rs6000.c I think.  I don't think it is
-	     currently necessary, but keep it around.  */
-	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
-	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
-	    output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
-	  else
-	    output_address (plus_constant (XEXP (x, 0), 4));
-	  fputc (']', file);
-	}
-      else
-	output_operand_lossage ("invalid operand to %R code");
-      return;
-    case 'S' :
-      if ((GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_FLAG (x))
-	  || GET_CODE (x) == LABEL_REF)
-	{
-	  fprintf (file, "%%st(");
-	  output_addr_const (file, x);
-	  fprintf (file, ")");
-	  return;
-	}
-      break;
-    case 'H' :
-    case 'L' :
-      if (GET_CODE (x) == REG)
-	{
-	  /* L = least significant word, H = most significant word */
-	  if ((TARGET_BIG_ENDIAN != 0) ^ (code == 'L'))
-	    fputs (reg_names[REGNO (x)], file);
-	  else
-	    fputs (reg_names[REGNO (x)+1], file);
-	}
-      else if (GET_CODE (x) == CONST_INT
-	       || GET_CODE (x) == CONST_DOUBLE)
-	{
-	  rtx first, second;
-
-	  split_double (x, &first, &second);
-	  fprintf (file, "0x%08lx",
-		   code == 'L' ? INTVAL (first) : INTVAL (second));
-	}
-      else
-	output_operand_lossage ("invalid operand to %H/%L code");
-      return;
-    case 'A' :
-      {
-	REAL_VALUE_TYPE d;
-	char str[30];
-
-	if (GET_CODE (x) != CONST_DOUBLE
-	    || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
-	  abort ();
-	REAL_VALUE_FROM_CONST_DOUBLE (d, x);
-	REAL_VALUE_TO_DECIMAL (d, "%.20e", str);
-	fprintf (file, "%s", str);
-	return;
-      }
-    case 'U' :
-      /* Output a load/store with update indicator if appropriate.  */
-      if (GET_CODE (x) == MEM)
-	{
-	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
-	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
-	    fputs (".a", file);
-	}
-      else
-	output_operand_lossage ("invalid operand to %U code");
-      return;
-    case 'V' :
-      /* Output cache bypass indicator for a load/store insn.  Volatile memory
-	 refs are defined to use the cache bypass mechanism.  */
-      if (GET_CODE (x) == MEM)
-	{
-	  if (MEM_VOLATILE_P (x))
-	    fputs (".di", file);
-	}
-      else
-	output_operand_lossage ("invalid operand to %V code");
-      return;
-    case 0 :
-      /* Do nothing special.  */
-      break;
-    default :
-      /* Unknown flag.  */
-      output_operand_lossage ("invalid operand output code");
-    }
-
-  switch (GET_CODE (x))
-    {
-    case REG :
-      fputs (reg_names[REGNO (x)], file);
-      break;
-    case MEM :
-      fputc ('[', file);
-      if (GET_CODE (XEXP (x, 0)) == PRE_INC)
-	output_address (plus_constant (XEXP (XEXP (x, 0), 0),
-				       GET_MODE_SIZE (GET_MODE (x))));
-      else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
-	output_address (plus_constant (XEXP (XEXP (x, 0), 0),
-				       - GET_MODE_SIZE (GET_MODE (x))));
-      else
-	output_address (XEXP (x, 0));
-      fputc (']', file);
-      break;
-    case CONST_DOUBLE :
-      /* We handle SFmode constants here as output_addr_const doesn't.  */
-      if (GET_MODE (x) == SFmode)
-	{
-	  REAL_VALUE_TYPE d;
-	  long l;
-
-	  REAL_VALUE_FROM_CONST_DOUBLE (d, x);
-	  REAL_VALUE_TO_TARGET_SINGLE (d, l);
-	  fprintf (file, "0x%08lx", l);
-	  break;
-	}
-      /* Fall through.  Let output_addr_const deal with it.  */
-    default :
-      output_addr_const (file, x);
-      break;
-    }
-}
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-void
-arc_print_operand_address (file, addr)
-     FILE *file;
-     rtx addr;
-{
-  register rtx base, index = 0;
-  int offset = 0;
-
-  switch (GET_CODE (addr))
-    {
-    case REG :
-      fputs (reg_names[REGNO (addr)], file);
-      break;
-    case SYMBOL_REF :
-      if (/*???*/ 0 && SYMBOL_REF_FLAG (addr))
-	{
-	  fprintf (file, "%%st(");
-	  output_addr_const (file, addr);
-	  fprintf (file, ")");
-	}
-      else
-	output_addr_const (file, addr);
-      break;
-    case PLUS :
-      if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
-	offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
-      else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
-	offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
-      else
-	base = XEXP (addr, 0), index = XEXP (addr, 1);
-      if (GET_CODE (base) != REG)
-	abort ();
-      fputs (reg_names[REGNO (base)], file);
-      if (index == 0)
-	{
-	  if (offset != 0)
-	    fprintf (file, ",%d", offset);
-	}
-      else if (GET_CODE (index) == REG)
-	fprintf (file, ",%s", reg_names[REGNO (index)]);
-      else if (GET_CODE (index) == SYMBOL_REF)
-	fputc (',', file), output_addr_const (file, index);
-      else
-	abort ();
-      break;
-    case PRE_INC :
-    case PRE_DEC :
-      /* We shouldn't get here as we've lost the mode of the memory object
-	 (which says how much to inc/dec by.  */
-      abort ();
-      break;
-    default :
-      output_addr_const (file, addr);
-      break;
-    }
-}
-
-/* Update compare/branch separation marker.  */
-
-static void
-record_cc_ref (insn)
-     rtx insn;
-{
-  last_insn_set_cc_p = current_insn_set_cc_p;
-
-  switch (get_attr_cond (insn))
-    {
-    case COND_SET :
-    case COND_SET_ZN :
-    case COND_SET_ZNC :
-      if (get_attr_length (insn) == 1)
-	current_insn_set_cc_p = 1;
-      else
-	current_insn_set_cc_p = 0;
-      break;
-    default :
-      current_insn_set_cc_p = 0;
-      break;
-    }
-}
-
-/* Conditional execution support.
-
-   This is based on the ARM port but for now is much simpler.
-
-   A finite state machine takes care of noticing whether or not instructions
-   can be conditionally executed, and thus decrease execution time and code
-   size by deleting branch instructions.  The fsm is controlled by
-   final_prescan_insn, and controls the actions of PRINT_OPERAND.  The patterns
-   in the .md file for the branch insns also have a hand in this.  */
-
-/* The state of the fsm controlling condition codes are:
-   0: normal, do nothing special
-   1: don't output this insn
-   2: don't output this insn
-   3: make insns conditional
-   4: make insns conditional
-
-   State transitions (state->state by whom, under what condition):
-   0 -> 1 final_prescan_insn, if insn is conditional branch
-   0 -> 2 final_prescan_insn, if the `target' is an unconditional branch
-   1 -> 3 branch patterns, after having not output the conditional branch
-   2 -> 4 branch patterns, after having not output the conditional branch
-   3 -> 0 ASM_OUTPUT_INTERNAL_LABEL, if the `target' label is reached
-          (the target label has CODE_LABEL_NUMBER equal to
-	  arc_ccfsm_target_label).
-   4 -> 0 final_prescan_insn, if `target' unconditional branch is reached
-
-   If the jump clobbers the conditions then we use states 2 and 4.
-
-   A similar thing can be done with conditional return insns.
-
-   We also handle separating branches from sets of the condition code.
-   This is done here because knowledge of the ccfsm state is required,
-   we may not be outputting the branch.  */
-
-void
-arc_final_prescan_insn (insn, opvec, noperands)
-     rtx insn;
-     rtx *opvec;
-     int noperands;
-{
-  /* BODY will hold the body of INSN.  */
-  register rtx body = PATTERN (insn);
-
-  /* This will be 1 if trying to repeat the trick (ie: do the `else' part of
-     an if/then/else), and things need to be reversed.  */
-  int reverse = 0;
-
-  /* If we start with a return insn, we only succeed if we find another one. */
-  int seeking_return = 0;
-  
-  /* START_INSN will hold the insn from where we start looking.  This is the
-     first insn after the following code_label if REVERSE is true.  */
-  rtx start_insn = insn;
-
-  /* Update compare/branch separation marker.  */
-  record_cc_ref (insn);
-
-  /* Allow -mdebug-ccfsm to turn this off so we can see how well it does.
-     We can't do this in macro FINAL_PRESCAN_INSN because its called from
-     final_scan_insn which has `optimize' as a local.  */
-  if (optimize < 2 || TARGET_NO_COND_EXEC)
-    return;
-
-  /* If in state 4, check if the target branch is reached, in order to
-     change back to state 0.  */
-  if (arc_ccfsm_state == 4)
-    {
-      if (insn == arc_ccfsm_target_insn)
-	{
-	  arc_ccfsm_target_insn = NULL;
-	  arc_ccfsm_state = 0;
-	}
-      return;
-    }
-
-  /* If in state 3, it is possible to repeat the trick, if this insn is an
-     unconditional branch to a label, and immediately following this branch
-     is the previous target label which is only used once, and the label this
-     branch jumps to is not too far off.  Or in other words "we've done the
-     `then' part, see if we can do the `else' part."  */
-  if (arc_ccfsm_state == 3)
-    {
-      if (simplejump_p (insn))
-	{
-	  start_insn = next_nonnote_insn (start_insn);
-	  if (GET_CODE (start_insn) == BARRIER)
-	    {
-	      /* ??? Isn't this always a barrier?  */
-	      start_insn = next_nonnote_insn (start_insn);
-	    }
-	  if (GET_CODE (start_insn) == CODE_LABEL
-	      && CODE_LABEL_NUMBER (start_insn) == arc_ccfsm_target_label
-	      && LABEL_NUSES (start_insn) == 1)
-	    reverse = TRUE;
-	  else
-	    return;
-	}
-      else if (GET_CODE (body) == RETURN)
-        {
-	  start_insn = next_nonnote_insn (start_insn);
-	  if (GET_CODE (start_insn) == BARRIER)
-	    start_insn = next_nonnote_insn (start_insn);
-	  if (GET_CODE (start_insn) == CODE_LABEL
-	      && CODE_LABEL_NUMBER (start_insn) == arc_ccfsm_target_label
-	      && LABEL_NUSES (start_insn) == 1)
-	    {
-	      reverse = TRUE;
-	      seeking_return = 1;
-	    }
-	  else
-	    return;
-        }
-      else
-	return;
-    }
-
-  if (GET_CODE (insn) != JUMP_INSN)
-    return;
-
-  /* This jump might be paralleled with a clobber of the condition codes,
-     the jump should always come first.  */
-  if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
-    body = XVECEXP (body, 0, 0);
-
-  if (reverse
-      || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
-	  && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
-    {
-      int insns_skipped = 0, fail = FALSE, succeed = FALSE;
-      /* Flag which part of the IF_THEN_ELSE is the LABEL_REF.  */
-      int then_not_else = TRUE;
-      /* Nonzero if next insn must be the target label.  */
-      int next_must_be_target_label_p;
-      rtx this_insn = start_insn, label = 0;
-
-      /* Register the insn jumped to.  */
-      if (reverse)
-        {
-	  if (!seeking_return)
-	    label = XEXP (SET_SRC (body), 0);
-        }
-      else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
-	label = XEXP (XEXP (SET_SRC (body), 1), 0);
-      else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
-	{
-	  label = XEXP (XEXP (SET_SRC (body), 2), 0);
-	  then_not_else = FALSE;
-	}
-      else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
-	seeking_return = 1;
-      else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
-        {
-	  seeking_return = 1;
-	  then_not_else = FALSE;
-        }
-      else
-	abort ();
-
-      /* See how many insns this branch skips, and what kind of insns.  If all
-	 insns are okay, and the label or unconditional branch to the same
-	 label is not too far away, succeed.  */
-      for (insns_skipped = 0, next_must_be_target_label_p = FALSE;
-	   !fail && !succeed && insns_skipped < MAX_INSNS_SKIPPED;
-	   insns_skipped++)
-	{
-	  rtx scanbody;
-
-	  this_insn = next_nonnote_insn (this_insn);
-	  if (!this_insn)
-	    break;
-
-	  if (next_must_be_target_label_p)
-	    {
-	      if (GET_CODE (this_insn) == BARRIER)
-		continue;
-	      if (GET_CODE (this_insn) == CODE_LABEL
-		  && this_insn == label)
-		{
-		  arc_ccfsm_state = 1;
-		  succeed = TRUE;
-		}
-	      else
-		fail = TRUE;
-	      break;
-	    }
-
-	  scanbody = PATTERN (this_insn);
-
-	  switch (GET_CODE (this_insn))
-	    {
-	    case CODE_LABEL:
-	      /* Succeed if it is the target label, otherwise fail since
-		 control falls in from somewhere else.  */
-	      if (this_insn == label)
-		{
-		  arc_ccfsm_state = 1;
-		  succeed = TRUE;
-		}
-	      else
-		fail = TRUE;
-	      break;
-
-	    case BARRIER:
-	      /* Succeed if the following insn is the target label.
-		 Otherwise fail.  
-		 If return insns are used then the last insn in a function 
-		 will be a barrier. */
-	      next_must_be_target_label_p = TRUE;
-	      break;
-
-	    case CALL_INSN:
-	      /* Can handle a call insn if there are no insns after it.
-		 IE: The next "insn" is the target label.  We don't have to
-		 worry about delay slots as such insns are SEQUENCE's inside
-		 INSN's.  ??? It is possible to handle such insns though.  */
-	      if (get_attr_cond (this_insn) == COND_CANUSE)
-		next_must_be_target_label_p = TRUE;
-	      else
-		fail = TRUE;
-	      break;
-
-	    case JUMP_INSN:
-      	      /* If this is an unconditional branch to the same label, succeed.
-		 If it is to another label, do nothing.  If it is conditional,
-		 fail.  */
-	      /* ??? Probably, the test for the SET and the PC are unnecessary. */
-
-	      if (GET_CODE (scanbody) == SET
-		  && GET_CODE (SET_DEST (scanbody)) == PC)
-		{
-		  if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
-		      && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
-		    {
-		      arc_ccfsm_state = 2;
-		      succeed = TRUE;
-		    }
-		  else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
-		    fail = TRUE;
-		}
-	      else if (GET_CODE (scanbody) == RETURN
-		       && seeking_return)
-	        {
-		  arc_ccfsm_state = 2;
-		  succeed = TRUE;
-	        }
-	      else if (GET_CODE (scanbody) == PARALLEL)
-	        {
-		  if (get_attr_cond (this_insn) != COND_CANUSE)
-		    fail = TRUE;
-		}
-	      break;
-
-	    case INSN:
-	      /* We can only do this with insns that can use the condition
-		 codes (and don't set them).  */
-	      if (GET_CODE (scanbody) == SET
-		  || GET_CODE (scanbody) == PARALLEL)
-		{
-		  if (get_attr_cond (this_insn) != COND_CANUSE)
-		    fail = TRUE;
-		}
-	      /* We can't handle other insns like sequences.  */
-	      else
-		fail = TRUE;
-	      break;
-
-	    default:
-	      break;
-	    }
-	}
-
-      if (succeed)
-	{
-	  if ((!seeking_return) && (arc_ccfsm_state == 1 || reverse))
-	    arc_ccfsm_target_label = CODE_LABEL_NUMBER (label);
-	  else if (seeking_return || arc_ccfsm_state == 2)
-	    {
-	      while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
-	        {
-		  this_insn = next_nonnote_insn (this_insn);
-		  if (this_insn && (GET_CODE (this_insn) == BARRIER
-				    || GET_CODE (this_insn) == CODE_LABEL))
-		    abort ();
-	        }
-	      if (!this_insn)
-	        {
-		  /* Oh dear! we ran off the end, give up.  */
-		  insn_extract (insn);
-		  arc_ccfsm_state = 0;
-		  arc_ccfsm_target_insn = NULL;
-		  return;
-	        }
-	      arc_ccfsm_target_insn = this_insn;
-	    }
-	  else
-	    abort ();
-
-	  /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
-	     what it was.  */
-	  if (!reverse)
-	    arc_ccfsm_current_cc = get_arc_condition_code (XEXP (SET_SRC (body),
-								 0));
-
-	  if (reverse || then_not_else)
-	    arc_ccfsm_current_cc = ARC_INVERSE_CONDITION_CODE (arc_ccfsm_current_cc);
-	}
-
-      /* Restore recog_operand.  Getting the attributes of other insns can
-	 destroy this array, but final.c assumes that it remains intact
-	 across this call; since the insn has been recognized already we
-	 call insn_extract direct. */
-      insn_extract (insn);
-    }
-}
-
-/* Record that we are currently outputting label NUM with prefix PREFIX.
-   It it's the label we're looking for, reset the ccfsm machinery.
-
-   Called from ASM_OUTPUT_INTERNAL_LABEL.  */
-
-void
-arc_ccfsm_at_label (prefix, num)
-     char *prefix;
-     int num;
-{
-  if (arc_ccfsm_state == 3 && arc_ccfsm_target_label == num
-      && !strcmp (prefix, "L"))
-    {
-      arc_ccfsm_state = 0;
-      arc_ccfsm_target_insn = NULL_RTX;
-    }
-}
-
-/* See if the current insn, which is a conditional branch, is to be
-   deleted.  */
-
-int
-arc_ccfsm_branch_deleted_p ()
-{
-  if (arc_ccfsm_state == 1 || arc_ccfsm_state == 2)
-    return 1;
-  return 0;
-}
-
-/* Record a branch isn't output because subsequent insns can be
-   conditionalized.  */
-
-void
-arc_ccfsm_record_branch_deleted ()
-{
-  /* Indicate we're conditionalizing insns now.  */
-  arc_ccfsm_state += 2;
-
-  /* If the next insn is a subroutine call, we still need a nop between the
-     cc setter and user.  We need to undo the effect of calling record_cc_ref
-     for the just deleted branch.  */
-  current_insn_set_cc_p = last_insn_set_cc_p;
-}
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
deleted file mode 100755
index 49d9fe2..0000000
--- a/gcc/config/arc/arc.h
+++ /dev/null
@@ -1,1642 +0,0 @@
-/* Definitions of target machine for GNU compiler, Argonaut ARC cpu.
-   Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* ??? This is an old port, and is undoubtedly suffering from bit rot.  */
-
-/* Things to do:
-
-   - PREDICATE_CODES
-   - incscc, decscc?
-   - print active compiler options in assembler output
-*/
-
-/* ??? Create elf.h and have svr4.h include it.  */
-#include "svr4.h"
-
-#undef ASM_SPEC
-#undef LINK_SPEC
-#undef STARTFILE_SPEC
-#undef ENDFILE_SPEC
-#undef SIZE_TYPE
-#undef PTRDIFF_TYPE
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-
-/* Print subsidiary information on the compiler version in use.  */
-#define TARGET_VERSION fprintf (stderr, " (arc)")
-
-/* Names to predefine in the preprocessor for this target machine.  */
-#define CPP_PREDEFINES "-Acpu(arc) -Amachine(arc) -D__arc__"
-
-/* Additional flags for the preprocessor.  */
-#define CPP_SPEC "\
-%{!mcpu=*:-D__base__} %{mcpu=base:-D__base__} \
-%{EB:-D__big_endian__} \
-"
-
-/* Pass -mmangle-cpu if we get -mcpu=*.
-   Doing it this way lets one have it on as default with -mcpu=*,
-   but also lets one turn it off with -mno-mangle-cpu.  */
-#define CC1_SPEC "\
-%{mcpu=*:-mmangle-cpu} \
-%{EB:%{EL:%emay not use both -EB and -EL}} \
-%{EB:-mbig-endian} %{EL:-mlittle-endian} \
-"
-
-#define ASM_SPEC "%{v} %{EB} %{EL}"
-
-#define LINK_SPEC "%{v} %{EB} %{EL}"
-
-#define STARTFILE_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
-
-#define ENDFILE_SPEC "crtfini.o%s"
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Mangle all user symbols for the specified cpu.
-   ARC's can be shipped in which a collection of cpus are coupled together.
-   Each CPU may be different in some way, and thus we may need to distinguish
-   code compiled for one to ensure it isn't linked with code compiled for
-   another.  */
-#define TARGET_MASK_MANGLE_CPU 1
-#define TARGET_MANGLE_CPU (target_flags & TARGET_MASK_MANGLE_CPU)
-
-#if 0
-/* Mangle libgcc symbols by adding a suffix for the specified cpu.  */
-#define TARGET_MASK_MANGLE_CPU_LIBGCC 2
-#define TARGET_MANGLE_CPU_LIBGCC (target_flags & TARGET_MASK_MANGLE_CPU_LIBGCC)
-#endif
-
-/* Align loops to 32 byte boundaries (cache line size).  */
-#define TARGET_MASK_ALIGN_LOOPS 4
-#define TARGET_ALIGN_LOOPS (target_flags & TARGET_MASK_ALIGN_LOOPS)
-
-/* Big Endian.  */
-#define TARGET_MASK_BIG_ENDIAN 8
-#define TARGET_BIG_ENDIAN (target_flags & TARGET_MASK_BIG_ENDIAN)
-
-/* Turn off conditional execution optimization,
-   so we can see how well it does, or in case it's buggy.  */
-#define TARGET_MASK_NO_COND_EXEC 0x10
-#define TARGET_NO_COND_EXEC (target_flags & TARGET_MASK_NO_COND_EXEC)
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES \
-{ \
-    { "mangle-cpu",		TARGET_MASK_MANGLE_CPU },		\
-    { "no-mangle-cpu",		-TARGET_MASK_MANGLE_CPU },		\
-/*  { "mangle-cpu-libgcc",	TARGET_MASK_MANGLE_CPU_LIBGCC }, */	\
-/*  { "no-mangle-cpu-libgcc",	-TARGET_MASK_MANGLE_CPU_LIBGCC }, */	\
-    { "align-loops",		TARGET_MASK_ALIGN_LOOPS },		\
-    { "no-align-loops",		-TARGET_MASK_ALIGN_LOOPS },		\
-    { "big-endian",		TARGET_MASK_BIG_ENDIAN },		\
-    { "little-endian",		-TARGET_MASK_BIG_ENDIAN },		\
-    { "no-cond-exec",		TARGET_MASK_NO_COND_EXEC },		\
-    SUBTARGET_SWITCHES							\
-    { "", TARGET_DEFAULT }						\
-}
-
-#define TARGET_DEFAULT (0)
-
-#define SUBTARGET_SWITCHES
-
-/* Instruction set characteristics.
-   These are internal macros, set by the appropriate -mcpu= option.  */
-
-/* Non-zero means the cpu has a barrel shifter.  */
-#define TARGET_SHIFTER 0
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an
-   initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   fixed part of the option name, and the address of a variable. 
-   The variable, type `char *', is set to the variable part of the
-   given option if the fixed part matches.  The actual option name
-   is made by appending `-m' to the specified name.
-
-   Here is an example which defines `-mshort-data-NUMBER'.  If the
-   given option is `-mshort-data-512', the variable `m88k_short_data'
-   will be set to the string `"512"'.
-
-	extern char *m88k_short_data;
-	#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } }  */
-
-extern char *arc_cpu_string;
-extern char *arc_text_string,*arc_data_string,*arc_rodata_string;
-
-#define TARGET_OPTIONS \
-{						\
-  { "cpu=",	&arc_cpu_string		},	\
-  { "text=",	&arc_text_string	},	\
-  { "data=",	&arc_data_string	},	\
-  { "rodata=",	&arc_rodata_string	},	\
-}
-
-/* Which cpu we're compiling for.  */
-extern int arc_cpu_type;
-
-/* Check if CPU is an extension and set `arc_cpu_type' and `arc_mangle_cpu'
-   appropriately.  The result should be non-zero if the cpu is recognized,
-   otherwise zero.  This is intended to be redefined in a cover file.
-   This is used by arc_init.  */
-#define ARC_EXTENSION_CPU(cpu) 0
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-
-extern void arc_init ();
-
-#define OVERRIDE_OPTIONS \
-do {				\
-  /* These need to be done at start up.  It's convenient to do them here.  */ \
-  arc_init ();			\
-} while (0)
-
-/* Target machine storage layout.  */
-
-/* Define to use software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion. */
-#define REAL_ARITHMETIC
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.  */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.  */
-#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
-
-/* Define this to set the endianness to use in libgcc2.c, which can
-   not depend on target_flags.  */
-#ifdef __big_endian__
-#define LIBGCC2_WORDS_BIG_ENDIAN 1
-#else
-#define LIBGCC2_WORDS_BIG_ENDIAN 0
-#endif
-
-/* Number of bits in an addressable storage unit.  */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Define this macro if it is advisable to hold scalars in registers
-   in a wider mode than that declared by the program.  In such cases, 
-   the value is constrained to be within the bounds of the declared
-   type, but kept valid in the wider mode.  The signedness of the
-   extension may differ from that of the type.  */
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
-if (GET_MODE_CLASS (MODE) == MODE_INT		\
-    && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)	\
-{						\
-  (MODE) = SImode;				\
-}
-
-/* Define this macro if the promotion described by `PROMOTE_MODE'
-   should also be done for outgoing function arguments.  */
-#define PROMOTE_FUNCTION_ARGS
-
-/* Likewise, if the function return value is promoted.  */
-#define PROMOTE_FUNCTION_RETURN
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 64
-
-/* ALIGN FRAMES on word boundaries */
-#define ARC_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* No data type wants to be aligned rounder than this.  */
-/* This is bigger than currently necessary for the ARC.  If 8 byte floats are
-   ever added it's not clear whether they'll need such alignment or not.  For
-   now we assume they will.  We can always relax it if necessary but the
-   reverse isn't true.  */
-#define BIGGEST_ALIGNMENT 64
-
-/* The best alignment to use in cases where we have a choice.  */
-#define FASTEST_ALIGNMENT 32
-
-/* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  ((TREE_CODE (EXP) == STRING_CST	\
-    && (ALIGN) < FASTEST_ALIGNMENT)	\
-   ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-/* On the ARC the lower address bits are masked to 0 as necessary.  The chip
-   won't croak when given an unaligned address, but the insn will still fail
-   to produce the correct result.  */
-#define STRICT_ALIGNMENT 1
-
-/* Layout of source language data types.  */
-
-#define SHORT_TYPE_SIZE		16
-#define INT_TYPE_SIZE		32
-#define LONG_TYPE_SIZE		32
-#define LONG_LONG_TYPE_SIZE	64
-#define FLOAT_TYPE_SIZE		32
-#define DOUBLE_TYPE_SIZE	64
-#define LONG_DOUBLE_TYPE_SIZE	64
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-#define SIZE_TYPE "long unsigned int"
-#define PTRDIFF_TYPE "long int"
-#define WCHAR_TYPE "short unsigned int"
-#define WCHAR_TYPE_SIZE 16
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  */
-/* Registers 61, 62, and 63 are not really registers and we needn't treat
-   them as such.  We still need a register for the condition code.  */
-#define FIRST_PSEUDO_REGISTER 62
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   0-28  - general purpose registers
-   29    - ilink1 (interrupt link register)
-   30    - ilink2 (interrupt link register)
-   31    - blink (branch link register)
-   32-59 - reserved for extensions
-   60    - LP_COUNT
-   61    - condition code
-
-   For doc purposes:
-   61    - short immediate data indicator (setting flags)
-   62    - long immediate data indicator
-   63    - short immediate data indicator (not setting flags).
-
-   The general purpose registers are further broken down into:
-   0-7   - arguments/results
-   8-15  - call used
-   16-23 - call saved
-   24    - call used, static chain pointer
-   25    - call used, gptmp
-   26    - global pointer
-   27    - frame pointer
-   28    - stack pointer
-
-   By default, the extension registers are not available.  */
-
-#define FIXED_REGISTERS \
-{ 0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 1, 1, 1, 1, 0,	\
-				\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1 }
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-
-#define CALL_USED_REGISTERS \
-{ 1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-				\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1 }
-
-/* If defined, an initializer for a vector of integers, containing the
-   numbers of hard registers in the order in which GNU CC should
-   prefer to use them (from most preferred to least).  */
-#define REG_ALLOC_ORDER \
-{ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1,			\
-  16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 31,			\
-  32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,	\
-  48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,		\
-  27, 28, 29, 30 }
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.  */
-#define HARD_REGNO_NREGS(REGNO, MODE) \
-((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.  */
-extern unsigned int arc_hard_regno_mode_ok[];
-extern unsigned int arc_mode_class[];
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-((arc_hard_regno_mode_ok[REGNO] & arc_mode_class[MODE]) != 0)
-
-/* A C expression that is nonzero if it is desirable to choose
-   register allocation so as to avoid move instructions between a
-   value of mode MODE1 and a value of mode MODE2.
-
-   If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
-   MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
-   MODE2)' must be zero.  */
-
-/* Tie QI/HI/SI modes together.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-(GET_MODE_CLASS (MODE1) == MODE_INT		\
- && GET_MODE_CLASS (MODE2) == MODE_INT		\
- && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD	\
- && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
-
-/* Register classes and constants.  */
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.
-
-   It is important that any condition codes have class NO_REGS.
-   See `register_operand'.  */
-
-enum reg_class {
-  NO_REGS, LPCOUNT_REG, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-#define REG_CLASS_NAMES \
-{ "NO_REGS", "LPCOUNT_REG", "GENERAL_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS \
-{ {0, 0}, {0, 0x10000000}, {0xffffffff, 0xfffffff}, \
-  {0xffffffff, 0x1fffffff} }
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-extern enum reg_class arc_regno_reg_class[];
-#define REGNO_REG_CLASS(REGNO) \
-(arc_regno_reg_class[REGNO])
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-#define REG_CLASS_FROM_LETTER(C) \
-((C) == 'l' ? LPCOUNT_REG /* ??? needed? */ \
- : NO_REGS)
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-((REGNO) < 29 || (unsigned) reg_renumber[REGNO] < 29)
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-((REGNO) < 29 || (unsigned) reg_renumber[REGNO] < 29)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
-(CLASS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-#define CLASS_MAX_NREGS(CLASS, MODE) \
-((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* The letters I, J, K, L, M, N, O, P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.  */
-/* 'I' is used for short immediates (always signed).
-   'J' is used for long immediates.
-   'K' is used for any constant up to 64 bits (for 64x32 situations?).  */
-
-/* local to this file */
-#define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200)
-/* local to this file */
-#define LARGE_INT(X) \
-((X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \
- && (X) <= (unsigned HOST_WIDE_INT) 0xffffffff)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
-((C) == 'I' ? SMALL_INT (VALUE)		\
- : (C) == 'J' ? LARGE_INT (VALUE)	\
- : (C) == 'K' ? 1			\
- : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-/* 'G' is used for integer values for the multiplication insns where the
-   operands are extended from 4 bytes to 8 bytes.
-   'H' is used when any 64 bit constant is allowed.  */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
-((C) == 'G' ? arc_double_limm_p (VALUE) \
- : (C) == 'H' ? 1 \
- : 0)
-
-/* A C expression that defines the optional machine-dependent constraint
-   letters that can be used to segregate specific types of operands,
-   usually memory references, for the target machine.  It should return 1 if
-   VALUE corresponds to the operand type represented by the constraint letter
-   C.  If C is not defined as an extra constraint, the value returned should
-   be 0 regardless of VALUE.  */
-/* ??? This currently isn't used.  Waiting for PIC.  */
-#if 0
-#define EXTRA_CONSTRAINT(VALUE, C) \
-((C) == 'R' ? (SYMBOL_REF_FLAG (VALUE) || GET_CODE (VALUE) == LABEL_REF) \
- : 0)
-#endif
-
-/* Stack layout and stack pointer usage.  */
-
-/* Define this macro if pushing a word onto the stack moves the stack
-   pointer to a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET 0
-
-/* Offset from the stack pointer register to the first location at which
-   outgoing arguments are placed.  */
-#define STACK_POINTER_OFFSET FIRST_PARM_OFFSET (0)
-
-/* Offset of first parameter from the argument pointer register value.  */
-/* 4 bytes for each of previous fp, return address, and previous gp.
-   4 byte reserved area for future considerations.  */
-#define FIRST_PARM_OFFSET(FNDECL) 16
-
-/* A C expression whose value is RTL representing the address in a
-   stack frame where the pointer to the caller's frame is stored.
-   Assume that FRAMEADDR is an RTL expression for the address of the
-   stack frame itself.
-
-   If you don't define this macro, the default is to return the value
-   of FRAMEADDR--that is, the stack frame address is also the address
-   of the stack word that points to the previous frame.  */
-/* ??? unfinished */
-/*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
-
-/* A C expression whose value is RTL representing the value of the
-   return address for the frame COUNT steps up from the current frame.
-   FRAMEADDR is the frame pointer of the COUNT frame, or the frame
-   pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
-   is defined.  */
-/* The current return address is in r31.  The return address of anything
-   farther back is at [%fp,4].  */
-#if 0 /* The default value should work.  */
-#define RETURN_ADDR_RTX(COUNT, FRAME) \
-(((COUNT) == -1)				\
- ? gen_rtx (REG, Pmode, 31)			\
- : copy_to_reg (gen_rtx (MEM, Pmode,		\
-			 memory_address (Pmode, plus_constant ((FRAME), UNITS_PER_WORD)))))
-#endif
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 28
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 27
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
-
-/* Register in which static-chain is passed to a function.  This must
-   not be a register used by the prologue.  */
-#define STATIC_CHAIN_REGNUM 24
-
-/* A C expression which is nonzero if a function must have and use a
-   frame pointer.  This expression is evaluated in the reload pass.
-   If its value is nonzero the function will have a frame pointer.  */
-#define FRAME_POINTER_REQUIRED \
-(current_function_calls_alloca)
-
-/* C statement to store the difference between the frame pointer
-   and the stack pointer values immediately after the function prologue.  */
-#define INITIAL_FRAME_POINTER_OFFSET(VAR) \
-((VAR) = arc_compute_frame_size (get_frame_size ()))
-
-/* Function argument passing.  */
-
-/* When a prototype says `char' or `short', really pass an `int'.  */
-#define PROMOTE_PROTOTYPES
-
-/* If defined, the maximum amount of space required for outgoing
-   arguments will be computed and placed into the variable
-   `current_function_outgoing_args_size'.  No space will be pushed
-   onto the stack for each call; instead, the function prologue should
-   increase the stack frame size by this amount.  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-#define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.  */
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
-((CUM) = 0)
-
-/* The number of registers used for parameter passing.  Local to this file.  */
-#define MAX_ARC_PARM_REGS 8
-
-/* 1 if N is a possible register number for function argument passing.  */
-#define FUNCTION_ARG_REGNO_P(N) \
-((unsigned) (N) < MAX_ARC_PARM_REGS)
-
-/* The ROUND_ADVANCE* macros are local to this file.  */
-/* Round SIZE up to a word boundary.  */
-#define ROUND_ADVANCE(SIZE) \
-(((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Round arg MODE/TYPE up to the next word boundary.  */
-#define ROUND_ADVANCE_ARG(MODE, TYPE) \
-((MODE) == BLKmode				\
- ? ROUND_ADVANCE (int_size_in_bytes (TYPE))	\
- : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
-
-/* Round CUM up to the necessary point for argument MODE/TYPE.  */
-#define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \
-((((MODE) == BLKmode ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) \
-  > BITS_PER_WORD)	\
- ? ((CUM) + 1 & ~1)	\
- : (CUM))
-
-/* Return boolean indicating arg of type TYPE and mode MODE will be passed in
-   a reg.  This includes arguments that have to be passed by reference as the
-   pointer to them is passed in a reg if one is available (and that is what
-   we're given).
-   When passing arguments NAMED is always 1.  When receiving arguments NAMED
-   is 1 for each argument except the last in a stdarg/varargs function.  In
-   a stdarg function we want to treat the last named arg as named.  In a
-   varargs function we want to treat the last named arg (which is
-   `__builtin_va_alist') as unnamed.
-   This macro is only used in this file.  */
-extern int current_function_varargs;
-#define PASS_IN_REG_P(CUM, MODE, TYPE, NAMED) \
-((!current_function_varargs || (NAMED))					\
- && (CUM) < MAX_ARC_PARM_REGS						\
- && ((ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))				\
-      + ROUND_ADVANCE_ARG ((MODE), (TYPE))				\
-      <= MAX_ARC_PARM_REGS)))
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-/* On the ARC the first MAX_ARC_PARM_REGS args are normally in registers
-   and the rest are pushed.  */
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-(PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED))				\
- ? gen_rtx (REG, (MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)))	\
- : 0)
-
-/* A C expression for the number of words, at the beginning of an
-   argument, must be put in registers.  The value must be zero for
-   arguments that are passed entirely in registers or that are entirely
-   pushed on the stack.
-
-   On some machines, certain arguments must be passed partially in
-   registers and partially in memory.  On these machines, typically the
-   first @var{n} words of arguments are passed in registers, and the rest
-   on the stack.  If a multi-word argument (a @code{double} or a
-   structure) crosses that boundary, its first few words must be passed
-   in registers and the rest must be pushed.  This macro tells the
-   compiler when this occurs, and how many of the words should go in
-   registers.  */
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
-/* A C expression that indicates when an argument must be passed by
-   reference.  If nonzero for an argument, a copy of that argument is
-   made in memory and a pointer to the argument is passed instead of
-   the argument itself.  The pointer is passed in whatever way is
-   appropriate for passing a pointer to that type.  */
-/* All aggregates and arguments greater than 8 bytes are passed this way.  */
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
-(TYPE					\
- && (AGGREGATE_TYPE_P (TYPE)		\
-     || int_size_in_bytes (TYPE) > 8))
-
-/* A C expression that indicates when it is the called function's
-   responsibility to make copies of arguments passed by reference.
-   If the callee can determine that the argument won't be modified, it can
-   avoid the copy.  */
-/* ??? We'd love to be able to use NAMED here.  Unfortunately, it doesn't
-   include the last named argument so we keep track of the args ourselves.  */
-
-#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
-FUNCTION_ARG_PASS_BY_REFERENCE ((CUM), (MODE), (TYPE), (NAMED))
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
-((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
-	  + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
-
-/* If defined, a C expression that gives the alignment boundary, in bits,
-   of an argument with the specified mode and type.  If it is not defined, 
-   PARM_BOUNDARY is used for all arguments.  */
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
-(((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
- ? PARM_BOUNDARY \
- : 2 * PARM_BOUNDARY)
-
-/* This macro offers an alternative
-   to using `__builtin_saveregs' and defining the macro
-   `EXPAND_BUILTIN_SAVEREGS'.  Use it to store the anonymous register
-   arguments into the stack so that all the arguments appear to have
-   been passed consecutively on the stack.  Once this is done, you
-   can use the standard implementation of varargs that works for
-   machines that pass all their arguments on the stack.
-
-   The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure,
-   containing the values that obtain after processing of the named
-   arguments.  The arguments MODE and TYPE describe the last named
-   argument--its machine mode and its data type as a tree node.
-
-   The macro implementation should do two things: first, push onto the
-   stack all the argument registers *not* used for the named
-   arguments, and second, store the size of the data thus pushed into
-   the `int'-valued variable whose name is supplied as the argument
-   PRETEND_SIZE.  The value that you store here will serve as
-   additional offset for setting up the stack frame.
-
-   If the argument NO_RTL is nonzero, it means that the
-   arguments of the function are being analyzed for the second time.
-   This happens for an inline function, which is not actually
-   compiled until the end of the source file.  The macro
-   `SETUP_INCOMING_VARARGS' should not generate any instructions in
-   this case.  */
-
-#define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
-arc_setup_incoming_varargs(&ARGS_SO_FAR, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
-
-/* Function results.  */
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-#define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.  */
-/* ??? What about r1 in DI/DF values.  */
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-/* A C expression which can inhibit the returning of certain function
-   values in registers, based on the type of value.  A nonzero value says
-   to return the function value in memory, just as large structures are
-   always returned.  Here TYPE will be a C expression of type `tree',
-   representing the data type of the value.  */
-#define RETURN_IN_MEMORY(TYPE) \
-(AGGREGATE_TYPE_P (TYPE) \
- || int_size_in_bytes (TYPE) > 8 \
- || TREE_ADDRESSABLE (TYPE))
-
-/* Tell GCC to use RETURN_IN_MEMORY.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Register in which address to store a structure value
-   is passed to a function, or 0 to use `invisible' first argument.  */
-#define STRUCT_VALUE 0
-
-/* Function entry and exit.  */
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-#define FUNCTION_PROLOGUE(FILE, SIZE) \
-arc_output_function_prologue (FILE, SIZE)
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-#define EXIT_IGNORE_STACK 0
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-arc_output_function_epilogue (FILE, SIZE)
-
-/* Epilogue delay slots.  */
-#define DELAY_SLOTS_FOR_EPILOGUE arc_delay_slots_for_epilogue ()
-
-#define ELIGIBLE_FOR_EPILOGUE_DELAY(TRIAL, SLOTS_FILLED) \
-arc_eligible_for_epilogue_delay (TRIAL, SLOTS_FILLED)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-#define FUNCTION_PROFILER(FILE, LABELNO)
-
-/* Trampolines.  */
-/* ??? This doesn't work yet because GCC will use as the address of a nested
-   function the address of the trampoline.  We need to use that address
-   right shifted by 2.  It looks like we'll need PSImode after all. :-(  */
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  */
-/* On the ARC, the trampoline is quite simple as we have 32 bit immediate
-   constants.
-
-	mov r24,STATIC
-	j.nd FUNCTION
-*/
-#define TRAMPOLINE_TEMPLATE(FILE) \
-do { \
-  ASM_OUTPUT_INT (FILE, GEN_INT (0x631f7c00)); \
-  ASM_OUTPUT_INT (FILE, const0_rtx); \
-  ASM_OUTPUT_INT (FILE, GEN_INT (0x381f0000)); \
-  ASM_OUTPUT_INT (FILE, const0_rtx); \
-} while (0)
-
-/* Length in units of the trampoline for entering a nested function.  */
-#define TRAMPOLINE_SIZE 16
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-do { \
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), CXT); \
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), FNADDR); \
-  emit_insn (gen_flush_icache (validize_mem (gen_rtx (MEM, SImode, TRAMP)))); \
-} while (0)
-
-/* Library calls.  */
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-/* The `ld' insn allows 2, but the `st' insn only allows 1.  */
-#define MAX_REGS_PER_ADDRESS 1
-
-/* We have pre inc/dec (load/store with update).  */
-#define HAVE_PRE_INCREMENT 1
-#define HAVE_PRE_DECREMENT 1
-
-/* Recognize any constant value that is a valid address.  */
-#define CONSTANT_ADDRESS_P(X) \
-(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF	\
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   We can handle any 32 or 64 bit constant.  */
-/* "1" should work since the largest constant should be a 64 bit critter.  */
-/* ??? Not sure what to do for 64x32 compiler.  */
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) \
-((unsigned) REGNO (X) - 29 >= FIRST_PSEUDO_REGISTER - 29)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-((unsigned) REGNO (X) - 29 >= FIRST_PSEUDO_REGISTER - 29)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.  */
-/* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm]
-   but the `st' insn only allows [reg],[reg+shimm],[limm].
-   The only thing we can do is only allow the most strict case `st' and hope
-   other parts optimize out the restrictions for `ld'.  */
-
-/* local to this file */
-#define RTX_OK_FOR_BASE_P(X) \
-(REG_P (X) && REG_OK_FOR_BASE_P (X))
-
-/* local to this file */
-#define RTX_OK_FOR_INDEX_P(X) \
-(0 && /*???*/ REG_P (X) && REG_OK_FOR_INDEX_P (X))
-
-/* local to this file */
-/* ??? Loads can handle any constant, stores can only handle small ones.  */
-#define RTX_OK_FOR_OFFSET_P(X) \
-(GET_CODE (X) == CONST_INT && SMALL_INT (INTVAL (X)))
-
-#define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
-(GET_CODE (X) == PLUS				\
- && RTX_OK_FOR_BASE_P (XEXP (X, 0))		\
- && (RTX_OK_FOR_INDEX_P (XEXP (X, 1))		\
-     || RTX_OK_FOR_OFFSET_P (XEXP (X, 1))))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)		\
-{ if (RTX_OK_FOR_BASE_P (X))				\
-    goto ADDR;						\
-  if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X)))	\
-    goto ADDR;						\
-  if (GET_CODE (X) == CONST_INT && LARGE_INT (INTVAL (X))) \
-    goto ADDR;						\
-  if (GET_CODE (X) == SYMBOL_REF			\
-	   || GET_CODE (X) == LABEL_REF			\
-	   || GET_CODE (X) == CONST)			\
-    goto ADDR;						\
-  if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
-      /* We're restricted here by the `st' insn.  */	\
-      && RTX_OK_FOR_BASE_P (XEXP ((X), 0)))		\
-    goto ADDR;						\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.  */
-
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.  */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
-{ if (GET_CODE (ADDR) == PRE_DEC)	\
-    goto LABEL;				\
-  if (GET_CODE (ADDR) == PRE_INC)	\
-    goto LABEL;				\
-}
-
-/* Condition code usage.  */
-
-/* Some insns set all condition code flags, some only set the ZNC flags, and
-   some only set the ZN flags.  */
-
-#define EXTRA_CC_MODES CCZNCmode, CCZNmode
-
-#define EXTRA_CC_NAMES "CCZNC", "CCZN"
-
-/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
-   return the mode to be used for the comparison.  */
-extern enum machine_mode arc_select_cc_mode ();
-#define SELECT_CC_MODE(OP, X, Y) \
-arc_select_cc_mode (OP, X, Y)
-
-/* Return non-zero if SELECT_CC_MODE will never return MODE for a
-   floating point inequality comparison.  */
-#define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
-
-/* Costs.  */
-
-/* An insn is define to cost 4 "units", and we work from there.
-   COSTS_N_INSNS (N) is defined as (N) * 4 - 2 so that seems reasonable.
-   Some values are supposed to be defined relative to each other and thus
-   aren't necessarily related to COSTS_N_INSNS.  */
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-/* Small integers are as cheap as registers.  4 byte values can be fetched
-   as immediate constants - let's give that the cost of an extra insn. */
-#define CONST_COSTS(X, CODE, OUTER_CODE) \
-  case CONST_INT :						\
-    if (SMALL_INT (INTVAL (X)))					\
-      return 0;							\
-    /* fall through */						\
-  case CONST :							\
-  case LABEL_REF :						\
-  case SYMBOL_REF :						\
-    return 4;							\
-  case CONST_DOUBLE :						\
-    {								\
-      rtx high, low;						\
-      split_double (X, &high, &low);				\
-      return 4 * (!SMALL_INT (INTVAL (high))			\
-		  + !SMALL_INT (INTVAL (low)));			\
-    }
-
-/* Compute the cost of an address.  */
-#define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : arc_address_cost (ADDR))
-
-/* Compute extra cost of moving data between one register class
-   and another.  */
-#define REGISTER_MOVE_COST(CLASS1, CLASS2) 2
-
-/* Compute the cost of moving data between registers and memory.  */
-/* Memory is 3 times as expensive as registers.
-   ??? Is that the right way to look at it?  */
-#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
-(GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
-
-/* The cost of a branch insn.  */
-/* ??? What's the right value here?  Branches are certainly more
-   expensive than reg->reg moves.  */
-#define BRANCH_COST 2
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  The purpose for the cost of MULT is to encourage
-   `synth_mult' to find a synthetic multiply when reasonable.
-
-   If we need more than 12 insns to do a multiply, then go out-of-line,
-   since the call overhead will be < 10% of the cost of the multiply.  */
-#define RTX_COSTS(X, CODE, OUTER_CODE) \
-  case ASHIFT :						\
-  case ASHIFTRT :					\
-  case LSHIFTRT :					\
-    if (TARGET_SHIFTER)					\
-      return COSTS_N_INSNS (1);				\
-    if (GET_CODE (XEXP ((X), 1)) != CONST_INT)		\
-      return COSTS_N_INSNS (16);			\
-    return COSTS_N_INSNS (INTVAL (XEXP ((X), 1)));
-
-/* Nonzero if access to memory by bytes is slow and undesirable.
-   For RISC chips, it means that access to memory by bytes is no
-   better than access by words when possible, so grab a whole word
-   and maybe make use of that.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* Define this macro if it is as good or better to call a constant
-   function address than to call an address kept in a register.  */
-/* On the ARC, calling through registers is slow.  */
-#define NO_FUNCTION_CSE
-
-/* Define this macro if it is as good or better for a function to call
-   itself with an explicit address than to call an address kept in a
-   register.  */
-/* On the ARC, calling through registers is slow.  */
-#define NO_RECURSIVE_FUNCTION_CSE
-
-/* Section selection.  */
-/* WARNING: These section names also appear in dwarfout.c.  */
-
-/* The names of the text, data, and readonly-data sections are runtime
-   selectable.  */
-
-#define ARC_SECTION_FORMAT		"\t.section %s"
-#define ARC_DEFAULT_TEXT_SECTION	".text"
-#define ARC_DEFAULT_DATA_SECTION	".data"
-#define ARC_DEFAULT_RODATA_SECTION	".rodata"
-
-extern char *arc_text_section,*arc_data_section,*arc_rodata_section;
-
-/* initfini.c uses this in an asm.  */
-#if defined (CRT_INIT) || defined (CRT_FINI)
-#define TEXT_SECTION_ASM_OP	"\t.section .text"
-#else
-#define TEXT_SECTION_ASM_OP	arc_text_section /*"\t.section .text"*/
-#endif
-#define DATA_SECTION_ASM_OP	arc_data_section /*"\t.section .data"*/
-
-#undef CONST_SECTION_ASM_OP
-#define CONST_SECTION_ASM_OP	arc_rodata_section /*"\t.section .rodata"*/
-
-#define BSS_SECTION_ASM_OP	"\t.section .bss"
-
-/* Define this macro if jump tables (for tablejump insns) should be
-   output in the text section, along with the assembler instructions.
-   Otherwise, the readonly data section is used.
-   This macro is irrelevant if there is no separate readonly data section.  */
-/*#define JUMP_TABLES_IN_TEXT_SECTION*/
-
-/* Define this macro if references to a symbol must be treated
-   differently depending on something about the variable or
-   function named by the symbol (such as what section it is in).
-
-   The macro definition, if any, is executed immediately after the
-   rtl for DECL or other node is created.
-   The value of the rtl will be a `mem' whose address is a
-   `symbol_ref'.
-
-   The usual thing for this macro to do is to store a flag in the
-   `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
-   name string in the `symbol_ref' (if one bit is not enough
-   information).  */
-
-/* On the ARC, function addresses are not the same as normal addresses.
-   Branch to absolute address insns take an address that is right-shifted
-   by 2.  We encode the fact that we have a function here, and then emit a
-   special assembler op when outputting the address.  */
-#define ENCODE_SECTION_INFO(DECL) \
-do {							\
-  if (TREE_CODE (DECL) == FUNCTION_DECL)		\
-    SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;	\
-} while (0)
-
-/* Decode SYM_NAME and store the real name part in VAR, sans
-   the characters that encode section info.  Define this macro if
-   ENCODE_SECTION_INFO alters the symbol's name string.  */
-/*#define STRIP_NAME_ENCODING(VAR, SYM_NAME)*/
-
-/* For DWARF.  Marginally different than default so output is "prettier"
-   (and consistent with above).  */
-#define PUSHSECTION_FORMAT "\t%s %s\n"
-
-/* Tell crtstuff.c we're using ELF.  */
-#define OBJECT_FORMAT_ELF
-
-/* PIC */
-
-/* The register number of the register used to address a table of static
-   data addresses in memory.  In some cases this register is defined by a
-   processor's ``application binary interface'' (ABI).  When this macro
-   is defined, RTL is generated for this register once, as with the stack
-   pointer and frame pointer registers.  If this macro is not defined, it
-   is up to the machine-dependent files to allocate such a register (if
-   necessary).  */
-#define PIC_OFFSET_TABLE_REGNUM 26
-
-/* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
-   clobbered by calls.  Do not define this macro if PIC_OFFSET_TABLE_REGNUM
-   is not defined.  */
-/* This register is call-saved on the ARC.  */
-/*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
-
-/* By generating position-independent code, when two different programs (A
-   and B) share a common library (libC.a), the text of the library can be
-   shared whether or not the library is linked at the same address for both
-   programs.  In some of these environments, position-independent code
-   requires not only the use of different addressing modes, but also
-   special code to enable the use of these addressing modes.
-
-   The FINALIZE_PIC macro serves as a hook to emit these special
-   codes once the function is being compiled into assembly code, but not
-   before.  (It is not done before, because in the case of compiling an
-   inline function, it would lead to multiple PIC prologues being
-   included in functions which used inline functions and were compiled to
-   assembly language.)  */
-
-#define FINALIZE_PIC arc_finalize_pic ()
-
-/* A C expression that is nonzero if X is a legitimate immediate
-   operand on the target machine when generating position independent code.
-   You can assume that X satisfies CONSTANT_P, so you need not
-   check this.  You can also assume `flag_pic' is true, so you need not
-   check it either.  You need not define this macro if all constants
-   (including SYMBOL_REF) can be immediate operands when generating
-   position independent code.  */
-/*#define LEGITIMATE_PIC_OPERAND_P(X)*/
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-extern void arc_asm_file_start ();
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) arc_asm_file_start (FILE)
-
-/* A C statement to output assembler commands which will identify the
-   object file as having been compiled with GNU CC (or another GNU
-   compiler).  */
-#undef ASM_IDENTIFY_GCC
-#define ASM_IDENTIFY_GCC(FILE) /* nothing */
-
-/* Needed because we define ASM_IDENTIFY_GCC.  */
-#define ASM_IDENTIFY_LANGUAGE(FILE) output_lang_identify (FILE)
-
-/* A C string constant describing how to begin a comment in the target
-   assembler language.  The compiler assumes that the comment will
-   end at the end of the line.  */
-#define ASM_COMMENT_START ";"
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-#define ASM_APP_OFF ""
-
-/* This is how to output an assembler line defining a `char' constant.  */
-#define ASM_OUTPUT_CHAR(FILE, VALUE) \
-( fprintf (FILE, "\t.byte\t"),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line defining a `short' constant.  */
-#define ASM_OUTPUT_SHORT(FILE, VALUE) \
-( fprintf (FILE, "\t.hword\t"),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line defining an `int' constant.
-   We also handle symbol output here.  Code addresses must be right shifted
-   by 2 because that's how the jump instruction wants them.  */
-#define ASM_OUTPUT_INT(FILE, VALUE) \
-do {									\
-  fprintf (FILE, "\t.word\t");						\
-  if ((GET_CODE (VALUE) == SYMBOL_REF && SYMBOL_REF_FLAG (VALUE))	\
-      || GET_CODE (VALUE) == LABEL_REF)					\
-    {									\
-      fprintf (FILE, "%%st(");						\
-      output_addr_const (FILE, (VALUE));				\
-      fprintf (FILE, ")");						\
-    }									\
-  else									\
-    output_addr_const (FILE, (VALUE));					\
-  fprintf (FILE, "\n");							\
-} while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE, VALUE) \
-{							\
-  long t;						\
-  char str[30];						\
-  REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);		\
-  REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);	\
-  fprintf (FILE, "\t.word\t0x%lx %s %s\n",		\
-	   t, ASM_COMMENT_START, str);			\
-}
-
-/* This is how to output an assembler line defining a `double' constant.  */
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
-{							\
-  long t[2];						\
-  char str[30];						\
-  REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);		\
-  REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);	\
-  fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n", \
-	   t[0], ASM_COMMENT_START, str, t[1]);		\
-}
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-#define ASM_BYTE_OP	".byte"
-#define ASM_OUTPUT_BYTE(FILE, VALUE)  \
-  fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
-
-/* The assembler's parentheses characters.  */
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-#define ASM_OUTPUT_LABEL(FILE, NAME) \
-do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-#define ASM_GLOBALIZE_LABEL(FILE, NAME) \
-do {				\
-  fputs ("\t.global\t", FILE);	\
-  assemble_name (FILE, NAME);	\
-  fputs ("\n", FILE);		\
-} while (0)
-
-/* A C statement (sans semicolon) to output on FILE an assembler pseudo-op to
-   declare a library function name external.  The name of the library function
-   is given by SYMREF, which has type RTX and is a SYMBOL_REF.  */
-#if 0
-/* On the ARC we want to have libgcc's for multiple cpus in one binary.
-   We can't use `assemble_name' here as that will call ASM_OUTPUT_LABELREF
-   and we'll get another suffix added on if -mmangle-cpu.  */
-extern char *arc_mangle_cpu;
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, SYMREF) \
-do {							\
-  if (TARGET_MANGLE_CPU_LIBGCC)				\
-    {							\
-      fprintf (FILE, "\t.rename\t_%s, _%s%s\n",		\
-	       XSTR (SYMREF, 0), XSTR (SYMREF, 0),	\
-	       arc_mangle_suffix);			\
-    }							\
-} while (0)
-#endif
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-/* We mangle all user labels to provide protection from linking code
-   compiled for different cpus.  */
-/* We work around a dwarfout.c deficiency by watching for labels from it and
-   not adding the '_' prefix nor the cpu suffix.  There is a comment in
-   dwarfout.c that says it should be using ASM_OUTPUT_INTERNAL_LABEL.  */
-extern char *arc_mangle_cpu;
-#define ASM_OUTPUT_LABELREF(FILE, NAME) \
-do {							\
-  if ((NAME)[0] == '.' && (NAME)[1] == 'L')		\
-    fprintf (FILE, "%s", NAME);				\
-  else							\
-    {							\
-      fputc ('_', FILE);				\
-      if (TARGET_MANGLE_CPU && arc_mangle_cpu != NULL)	\
-	fprintf (FILE, "%s_", arc_mangle_cpu);		\
-      fprintf (FILE, "%s", NAME);			\
-    }							\
-} while (0)
-
-/* This is how to output a definition of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) \
-do {						\
-  arc_ccfsm_at_label (PREFIX, NUM);		\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM);	\
-} while (0)
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Assembler pseudo-op to equate one value with another.  */
-/* ??? This is needed because dwarfout.c provides a default definition too
-   late for defaults.h (which contains the default definition of ASM_OUTPUT_DEF
-   that we use).  */
-#define SET_ASM_OP ".set"
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#undef ASM_OUTPUT_CONSTRUCTOR
-#define ASM_OUTPUT_CONSTRUCTOR(FILE, NAME) \
-do {					\
-  ctors_section ();			\
-  fprintf (FILE, "\t.word\t%%st(");	\
-  assemble_name (FILE, NAME);		\
-  fprintf (FILE, ")\n");		\
-} while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#undef ASM_OUTPUT_DESTRUCTOR
-#define ASM_OUTPUT_DESTRUCTOR(FILE, NAME) \
-do {					\
-  dtors_section ();			\
-  fprintf (FILE, "\t.word\t%%st(");	\
-  assemble_name (FILE, NAME);		\
-  fprintf (FILE, ")\n");		\
-} while (0)
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-#define REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",		\
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",		\
- "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",	\
- "r24", "r25", "r26", "fp", "sp", "ilink1", "ilink2", "blink",	\
- "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",	\
- "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",	\
- "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",	\
- "r56", "r57", "r58", "r59", "lp_count", "cc"}
-
-/* Entry to the insn conditionalizer.  */
-#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
-arc_final_prescan_insn (INSN, OPVEC, NOPERANDS)
-
-/* A C expression which evaluates to true if CODE is a valid
-   punctuation character for use in the `PRINT_OPERAND' macro.  */
-extern char arc_punct_chars[];
-#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
-arc_punct_chars[(unsigned char) (CHAR)]
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-#define PRINT_OPERAND(FILE, X, CODE) \
-arc_print_operand (FILE, X, CODE)
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand that is a memory
-   reference whose address is ADDR.  ADDR is an RTL expression.
-
-   On some machines, the syntax for a symbolic address depends on
-   the section that the address refers to.  On these machines,
-   define the macro `ENCODE_SECTION_INFO' to store the information
-   into the `symbol_ref', and then check for it here.  */
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
-arc_print_operand_address (FILE, ADDR)
-
-/* This is how to output an element of a case-vector that is absolute.  */
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-do {							\
-  char label[30];					\
-  ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);	\
-  fprintf (FILE, "\t.word %%st(");			\
-  assemble_name (FILE, label);				\
-  fprintf (FILE, ")\n");				\
-} while (0)
-
-/* This is how to output an element of a case-vector that is relative.  */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-do {							\
-  char label[30];					\
-  ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);	\
-  fprintf (FILE, "\t.word %%st(");			\
-  assemble_name (FILE, label);				\
-  fprintf (FILE, "-");					\
-  ASM_GENERATE_INTERNAL_LABEL (label, "L", REL);	\
-  assemble_name (FILE, label);				\
-  fprintf (FILE, ")\n");				\
-} while (0)
-
-/* The desired alignment for the location counter at the beginning
-   of a loop.  */
-/* On the ARC, align loops to 32 byte boundaries (cache line size)
-   if -malign-loops.  */
-#define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
-do { if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); } while (0)
-
-/* Debugging information.  */
-
-/* Generate DBX and DWARF debugging information.  */
-#define DBX_DEBUGGING_INFO
-#define DWARF_DEBUGGING_INFO
-
-/* Prefer STABS (for now).  */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* How to renumber registers for dbx and gdb.  */
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Turn off splitting of long stabs.  */
-#define DBX_CONTIN_LENGTH 0
-
-/* Miscellaneous.  */
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE Pmode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* It's not clear what PIC will look like or whether we want to use -fpic
-   for the embedded form currently being talked about.  For now require -fpic
-   to get pc relative switch tables.  */
-/*#define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.  */
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 4
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
-   few bits. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-#define STORE_FLAG_VALUE 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-/* ??? The arc doesn't have full 32 bit pointers, but making this PSImode has
-   its own problems (you have to add extendpsisi2 and trucnsipsi2 but how does
-   one do it without getting excess code?).  Try to avoid it.  */
-#define Pmode SImode
-
-/* A function address in a call instruction.  */
-#define FUNCTION_MODE SImode
-
-/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
-   is a valid machine specific attribute for DECL.
-   The attributes in ATTRIBUTES have previously been assigned to TYPE.  */
-extern int arc_valid_machine_attribute ();
-#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
-arc_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
-
-/* A C expression that returns zero if the attributes on TYPE1 and TYPE2 are
-   incompatible, one if they are compatible, and two if they are
-   nearly compatible (which causes a warning to be generated).  */
-extern int arc_comp_type_attributes ();
-#define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
-arc_comp_type_attributes (TYPE1, TYPE2)
-
-/* Give newly defined TYPE some default attributes.  */
-extern void arc_set_default_type_attributes ();
-#define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
-arc_set_default_type_attributes (TYPE)
-
-/* Define this if the target system supports the function
-   atexit from the ANSI C standard.  If this is not defined,
-   and INIT_SECTION_ASM_OP is not defined, a default
-   exit function will be provided to support C++.  */
-#define HAVE_ATEXIT
-
-/* alloca should avoid clobbering the old register save area.  */
-/* ??? Not defined in tm.texi.  */
-#define SETJMP_VIA_SAVE_AREA
-
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  Note that we can't use "rtx" here
-   since it hasn't been defined!  */
-extern struct rtx_def *arc_compare_op0, *arc_compare_op1;
-
-/* Define the function that build the compare insn for scc and bcc.  */
-extern struct rtx_def *gen_compare_reg ();
-
-/* Declarations for various fns used in the .md file.  */
-extern char *output_shift ();
-
-/* ARC function types.   */
-enum arc_function_type {
-  ARC_FUNCTION_UNKNOWN, ARC_FUNCTION_NORMAL,
-  /* These are interrupt handlers.  The name corresponds to the register
-     name that contains the return address.  */
-  ARC_FUNCTION_ILINK1, ARC_FUNCTION_ILINK2
-};
-#define ARC_INTERRUPT_P(TYPE) \
-((TYPE) == ARC_FUNCTION_ILINK1 || (TYPE) == ARC_FUNCTION_ILINK2)
-/* Compute the type of a function from its DECL.  */
-enum arc_function_type arc_compute_function_type ();
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
deleted file mode 100755
index 328b1eb..0000000
--- a/gcc/config/arc/arc.md
+++ /dev/null
@@ -1,1630 +0,0 @@
-;; Machine description of the Argonaut ARC cpu for GNU C compiler
-;; Copyright (C) 1994, 1997 Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; ??? This is an old port, and is undoubtedly suffering from bit rot.
-
-;; Insn type.  Used to default other attribute values.
-
-(define_attr "type"
-  "move,load,store,cmove,unary,binary,compare,shift,mul,uncond_branch,branch,call,call_no_delay_slot,multi,misc"
-  (const_string "binary"))
-
-;; Length (in # of insns, long immediate constants counted too).
-;; ??? There's a nasty interaction between the conditional execution fsm
-;; and insn lengths: insns with shimm values cannot be conditionally executed.
-(define_attr "length" ""
-  (cond [(eq_attr "type" "load")
-	 (if_then_else (match_operand 1 "long_immediate_loadstore_operand" "")
-		       (const_int 2) (const_int 1))
-
-	 (eq_attr "type" "store")
-	 (if_then_else (match_operand 0 "long_immediate_loadstore_operand" "")
-		       (const_int 2) (const_int 1))
-
-	 (eq_attr "type" "move,unary,compare")
-	 (if_then_else (match_operand 1 "long_immediate_operand" "")
-		       (const_int 2) (const_int 1))
-
-	 (eq_attr "type" "binary,mul")
-	 (if_then_else (match_operand 2 "long_immediate_operand" "")
-		       (const_int 2) (const_int 1))
-
-	 (eq_attr "type" "cmove")
-	 (if_then_else (match_operand 2 "register_operand" "")
-		       (const_int 1) (const_int 2))
-
-	 (eq_attr "type" "multi") (const_int 2)
-	]
-
-	(const_int 1)))
-
-;; The length here is the length of a single asm.  Unfortunately it might be
-;; 1 or 2 so we must allow for 2.  That's ok though.  How often will users
-;; lament asm's not being put in delay slots?
-(define_asm_attributes
-  [(set_attr "length" "2")
-   (set_attr "type" "multi")])
-
-;; Condition codes: this one is used by final_prescan_insn to speed up
-;; conditionalizing instructions.  It saves having to scan the rtl to see if
-;; it uses or alters the condition codes.
-
-;; USE: This insn uses the condition codes (eg: a conditional branch).
-;; CANUSE: This insn can use the condition codes (for conditional execution).
-;; SET: All condition codes are set by this insn.
-;; SET_ZN: the Z and N flags are set by this insn.
-;; SET_ZNC: the Z, N, and C flags are set by this insn.
-;; CLOB: The condition codes are set to unknown values by this insn.
-;; NOCOND: This insn can't use and doesn't affect the condition codes.
-
-(define_attr "cond" "use,canuse,set,set_zn,set_znc,clob,nocond"
-  (cond [(and (eq_attr "type" "unary,binary,move")
-	      (eq_attr "length" "1"))
-	 (const_string "canuse")
-
-	 (eq_attr "type" "compare")
-	 (const_string "set")
-
-	 (eq_attr "type" "cmove,branch")
-	 (const_string "use")
-
-	 (eq_attr "type" "multi,misc")
-	 (const_string "clob")
-	 ]
-
-	 (const_string "nocond")))
-
-;; Delay slots.
-
-(define_attr "in_delay_slot" "false,true"
-  (cond [(eq_attr "type" "uncond_branch,branch,call,call_no_delay_slot,multi")
-	 (const_string "false")
-	 ]
-
-	 (if_then_else (eq_attr "length" "1")
-		       (const_string "true")
-		       (const_string "false"))))
-
-(define_delay (eq_attr "type" "call")
-  [(eq_attr "in_delay_slot" "true")
-   (eq_attr "in_delay_slot" "true")
-   (eq_attr "in_delay_slot" "true")])
-
-(define_delay (eq_attr "type" "branch,uncond_branch")
-  [(eq_attr "in_delay_slot" "true")
-   (eq_attr "in_delay_slot" "true")
-   (eq_attr "in_delay_slot" "true")])
-   
-;; Function units of the ARC
-
-;; (define_function_unit {name} {num-units} {n-users} {test}
-;;                       {ready-delay} {issue-delay} [{conflict-list}])
-
-;; 1) A conditional jump cannot immediately follow the insn setting the flags.
-;; This isn't a complete solution as it doesn't come with guarantees.  That
-;; is done in the branch patterns and in arc_print_operand.  This exists to
-;; avoid inserting a nop when we can.
-(define_function_unit "compare" 1 0 (eq_attr "type" "compare") 2 2 [(eq_attr "type" "branch")])
-
-;; 2) References to loaded registers should wait a cycle.
-
-;; Memory with load-delay of 1 (i.e., 2 cycle load).
-(define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
-
-;; Units that take one cycle do not need to be specified.
-
-;; Move instructions.
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Everything except mem = const or mem = mem can be done easily.  */
-
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (QImode, operands[1]);
-}")
-
-(define_insn "*movqi_insn"
-  [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,m")
-	(match_operand:QI 1 "move_src_operand" "rI,Ji,m,r"))]
-;; ??? Needed?
-  "register_operand (operands[0], QImode)
-   || register_operand (operands[1], QImode)"
-  "@
-   mov%? %0,%1
-   mov%? %0,%1
-   ldb%U1%V1 %0,%1
-   stb%U0%V0 %1,%0"
-  [(set_attr "type" "move,move,load,store")])
-
-;; ??? This may never match since there's no cmpqi insn.
-
-(define_insn "*movqi_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (sign_extend:SI (match_operand:QI 1 "move_src_operand" "rIJi"))
-		       (const_int 0)))
-   (set (match_operand:QI 0 "move_dest_operand" "=r")
-	(match_dup 1))]
-  ""
-  "mov%?.f %0,%1"
-  [(set_attr "type" "move")
-   (set_attr "cond" "set_zn")])
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Everything except mem = const or mem = mem can be done easily.  */
-
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (HImode, operands[1]);
-}")
-
-(define_insn "*movhi_insn"
-  [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,m")
-	(match_operand:HI 1 "move_src_operand" "rI,Ji,m,r"))]
-  "register_operand (operands[0], HImode)
-   || register_operand (operands[1], HImode)"
-  "@
-   mov%? %0,%1
-   mov%? %0,%1
-   ldw%U1%V1 %0,%1
-   stw%U0%V0 %1,%0"
-  [(set_attr "type" "move,move,load,store")])
-
-;; ??? Will this ever match?
-
-(define_insn "*movhi_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (sign_extend:SI (match_operand:HI 1 "move_src_operand" "rIJi"))
-		       (const_int 0)))
-   (set (match_operand:HI 0 "move_dest_operand" "=r")
-	(match_dup 1))]
-;; ??? Needed?
-  "register_operand (operands[0], HImode)
-   || register_operand (operands[1], HImode)"
-  "mov%?.f %0,%1"
-  [(set_attr "type" "move")
-   (set_attr "cond" "set_zn")])
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Everything except mem = const or mem = mem can be done easily.  */
-
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (SImode, operands[1]);
-}")
-
-(define_insn "*movsi_insn"
-  [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,m")
-	(match_operand:SI 1 "move_src_operand" "rI,GJi,m,r"))]
-  "register_operand (operands[0], SImode)
-   || register_operand (operands[1], SImode)"
-  "@
-   mov%? %0,%1
-   mov%? %0,%S1
-   ld%U1%V1 %0,%1
-   st%U0%V0 %1,%0"
-  [(set_attr "type" "move,move,load,store")])
-
-(define_insn "*movsi_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (match_operand:SI 1 "move_src_operand" "rIJi")
-		       (const_int 0)))
-   (set (match_operand:SI 0 "move_dest_operand" "=r")
-	(match_dup 1))]
-  "register_operand (operands[0], SImode)
-   || register_operand (operands[1], SImode)"
-  "mov%?.f %0,%S1"
-  [(set_attr "type" "move")
-   (set_attr "cond" "set_zn")])
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Everything except mem = const or mem = mem can be done easily.  */
-
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (DImode, operands[1]);
-}")
-
-(define_insn "*movdi_insn"
-  [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,m")
-	(match_operand:DI 1 "move_double_src_operand" "r,HK,m,r"))]
-  "register_operand (operands[0], DImode)
-   || register_operand (operands[1], DImode)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0 :
-      /* We normally copy the low-numbered register first.  However, if
-	 the first register operand 0 is the same as the second register of
-	 operand 1, we must copy in the opposite order.  */
-      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
-	return \"mov %R0,%R1\;mov %0,%1\";
-      else
-	return \"mov %0,%1\;mov %R0,%R1\";
-    case 1 :
-      return \"mov %0,%L1\;mov %R0,%H1\";
-    case 2 :
-      /* If the low-address word is used in the address, we must load it
-	 last.  Otherwise, load it first.  Note that we cannot have
-	 auto-increment in that case since the address register is known to be
-	 dead.  */
-      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			     operands [1], 0))
-	  return \"ld%V1 %R0,%R1\;ld%V1 %0,%1\";
-      else
-	  return \"ld%V1 %0,%1\;ld%V1 %R0,%R1\";
-    case 3 :
-      return \"st%V0 %1,%0\;st%V0 %R1,%R0\";
-    }
-}"
-  [(set_attr "type" "move,move,load,store")
-   ;; ??? The ld/st values could be 4 if it's [reg,bignum].
-   (set_attr "length" "2,4,2,2")])
-
-;(define_expand "movdi"
-;  [(set (match_operand:DI 0 "general_operand" "")
-;	(match_operand:DI 1 "general_operand" ""))]
-;  ""
-;  "
-;{
-;  /* Flow doesn't understand that this is effectively a DFmode move.
-;     It doesn't know that all of `operands[0]' is set.  */
-;  emit_insn (gen_rtx (CLOBBER, VOIDmode, operands[0]));
-;
-;  /* Emit insns that movsi_insn can handle.  */
-;  emit_insn (gen_movsi (operand_subword (operands[0], 0, 0, DImode),
-;			operand_subword (operands[1], 0, 0, DImode)));
-;  emit_insn (gen_movsi (operand_subword (operands[0], 1, 0, DImode),
-;			operand_subword (operands[1], 1, 0, DImode)));
-;  DONE;
-;}")
-
-;; Floating point move insns.
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Everything except mem = const or mem = mem can be done easily.  */
-
-#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    operands[1] = force_const_mem (SFmode, operands[1]);
-#endif
-
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (SFmode, operands[1]);
-}")
-
-(define_insn "*movsf_insn"
-  [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,m")
-	(match_operand:SF 1 "move_src_operand" "r,E,m,r"))]
-  "register_operand (operands[0], SFmode)
-   || register_operand (operands[1], SFmode)"
-  "@
-   mov%? %0,%1
-   mov%? %0,%1 ; %A1
-   ld%U1%V1 %0,%1
-   st%U0%V0 %1,%0"
-  [(set_attr "type" "move,move,load,store")])
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Everything except mem = const or mem = mem can be done easily.  */
-
-#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    operands[1] = force_const_mem (DFmode, operands[1]);
-#endif
-
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (DFmode, operands[1]);
-}")
-
-(define_insn "*movdf_insn"
-  [(set (match_operand:DF 0 "move_dest_operand" "=r,r,r,m")
-	(match_operand:DF 1 "move_double_src_operand" "r,E,m,r"))]
-  "register_operand (operands[0], DFmode)
-   || register_operand (operands[1], DFmode)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0 :
-      /* We normally copy the low-numbered register first.  However, if
-	 the first register operand 0 is the same as the second register of
-	 operand 1, we must copy in the opposite order.  */
-      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
-	return \"mov %R0,%R1\;mov %0,%1\";
-      else
-	return \"mov %0,%1\;mov %R0,%R1\";
-    case 1 :
-      return \"mov %0,%L1\;mov %R0,%H1 ; %A1\";
-    case 2 :
-      /* If the low-address word is used in the address, we must load it
-	 last.  Otherwise, load it first.  Note that we cannot have
-	 auto-increment in that case since the address register is known to be
-	 dead.  */
-      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			     operands [1], 0))
-	return \"ld%V1 %R0,%R1\;ld%V1 %0,%1\";
-      else
-	return \"ld%V1 %0,%1\;ld%V1 %R0,%R1\";
-    case 3 :
-      return \"st%V0 %1,%0\;st%V0 %R1,%R0\";
-    }
-}"
-  [(set_attr "type" "move,move,load,store")
-   ;; ??? The ld/st values could be 4 if it's [reg,bignum].
-   (set_attr "length" "2,4,2,2")])
-
-;(define_expand "movdf"
-;  [(set (match_operand:DF 0 "general_operand" "")
-;	(match_operand:DF 1 "general_operand" ""))]
-;  ""
-;  "
-;{
-;  /* Flow doesn't understand that this is effectively a DFmode move.
-;     It doesn't know that all of `operands[0]' is set.  */
-;  emit_insn (gen_rtx (CLOBBER, VOIDmode, operands[0]));
-;
-;  /* Emit insns that movsi_insn can handle.  */
-;  emit_insn (gen_movsi (operand_subword (operands[0], 0, 0, DFmode),
-;			operand_subword (operands[1], 0, 0, DFmode)));
-;  emit_insn (gen_movsi (operand_subword (operands[0], 1, 0, DFmode),
-;			operand_subword (operands[1], 1, 0, DFmode)));
-;  DONE;
-;}")
-
-;; Load/Store with update instructions.
-;;
-;; Some of these we can get by using pre-decrement or pre-increment, but the
-;; hardware can also do cases where the increment is not the size of the
-;; object.
-;;
-;; In all these cases, we use operands 0 and 1 for the register being
-;; incremented because those are the operands that local-alloc will
-;; tie and these are the pair most likely to be tieable (and the ones
-;; that will benefit the most).
-;;
-;; We use match_operator here because we need to know whether the memory
-;; object is volatile or not.
-
-(define_insn "*loadqi_update"
-  [(set (match_operand:QI 3 "register_operand" "=r,r")
-	(match_operator:QI 4 "load_update_operand"
-	 [(match_operand:SI 1 "register_operand" "0,0")
-	  (match_operand:SI 2 "nonmemory_operand" "rI,J")]))
-   (set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldb.a%V4 %3,[%0,%2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "1,2")])
-
-(define_insn "*load_zeroextendqisi_update"
-  [(set (match_operand:SI 3 "register_operand" "=r,r")
-	(zero_extend:SI (match_operator:QI 4 "load_update_operand"
-			 [(match_operand:SI 1 "register_operand" "0,0")
-			  (match_operand:SI 2 "nonmemory_operand" "rI,J")])))
-   (set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldb.a%V4 %3,[%0,%2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "1,2")])
-
-(define_insn "*load_signextendqisi_update"
-  [(set (match_operand:SI 3 "register_operand" "=r,r")
-	(sign_extend:SI (match_operator:QI 4 "load_update_operand"
-			 [(match_operand:SI 1 "register_operand" "0,0")
-			  (match_operand:SI 2 "nonmemory_operand" "rI,J")])))
-   (set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldb.x.a%V4 %3,[%0,%2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "1,2")])
-
-(define_insn "*storeqi_update"
-  [(set (match_operator:QI 4 "store_update_operand"
-	 [(match_operand:SI 1 "register_operand" "0")
-	  (match_operand:SI 2 "short_immediate_operand" "I")])
-	(match_operand:QI 3 "register_operand" "r"))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "stb.a%V4 %3,[%0,%2]"
-  [(set_attr "type" "store")
-   (set_attr "length" "1")])
-
-(define_insn "*loadhi_update"
-  [(set (match_operand:HI 3 "register_operand" "=r,r")
-	(match_operator:HI 4 "load_update_operand"
-	 [(match_operand:SI 1 "register_operand" "0,0")
-	  (match_operand:SI 2 "nonmemory_operand" "rI,J")]))
-   (set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldw.a%V4 %3,[%0,%2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "1,2")])
-
-(define_insn "*load_zeroextendhisi_update"
-  [(set (match_operand:SI 3 "register_operand" "=r,r")
-	(zero_extend:SI (match_operator:HI 4 "load_update_operand"
-			 [(match_operand:SI 1 "register_operand" "0,0")
-			  (match_operand:SI 2 "nonmemory_operand" "rI,J")])))
-   (set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldw.a%V4 %3,[%0,%2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "1,2")])
-
-(define_insn "*load_signextendhisi_update"
-  [(set (match_operand:SI 3 "register_operand" "=r,r")
-	(sign_extend:SI (match_operator:HI 4 "load_update_operand"
-			 [(match_operand:SI 1 "register_operand" "0,0")
-			  (match_operand:SI 2 "nonmemory_operand" "rI,J")])))
-   (set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldw.x.a%V4 %3,[%0,%2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "1,2")])
-
-(define_insn "*storehi_update"
-  [(set (match_operator:HI 4 "store_update_operand"
-	 [(match_operand:SI 1 "register_operand" "0")
-	  (match_operand:SI 2 "short_immediate_operand" "I")])
-	(match_operand:HI 3 "register_operand" "r"))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "stw.a%V4 %3,[%0,%2]"
-  [(set_attr "type" "store")
-   (set_attr "length" "1")])
-
-(define_insn "*loadsi_update"
-  [(set (match_operand:SI 3 "register_operand" "=r,r")
-	(match_operator:SI 4 "load_update_operand"
-	 [(match_operand:SI 1 "register_operand" "0,0")
-	  (match_operand:SI 2 "nonmemory_operand" "rI,J")]))
-   (set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ld.a%V4 %3,[%0,%2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "1,2")])
-
-(define_insn "*storesi_update"
-  [(set (match_operator:SI 4 "store_update_operand"
-	 [(match_operand:SI 1 "register_operand" "0")
-	  (match_operand:SI 2 "short_immediate_operand" "I")])
-	(match_operand:SI 3 "register_operand" "r"))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "st.a%V4 %3,[%0,%2]"
-  [(set_attr "type" "store")
-   (set_attr "length" "1")])
-
-(define_insn "*loadsf_update"
-  [(set (match_operand:SF 3 "register_operand" "=r,r")
-	(match_operator:SF 4 "load_update_operand"
-	 [(match_operand:SI 1 "register_operand" "0,0")
-	  (match_operand:SI 2 "nonmemory_operand" "rI,J")]))
-   (set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ld.a%V4 %3,[%0,%2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "1,2")])
-
-(define_insn "*storesf_update"
-  [(set (match_operator:SF 4 "store_update_operand"
-	 [(match_operand:SI 1 "register_operand" "0")
-	  (match_operand:SI 2 "short_immediate_operand" "I")])
-	(match_operand:SF 3 "register_operand" "r"))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "st.a%V4 %3,[%0,%2]"
-  [(set_attr "type" "store")
-   (set_attr "length" "1")])
-
-;; Conditional move instructions.
-
-(define_expand "movsicc"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(if_then_else (match_operand 1 "comparison_operator" "")
-		      (match_operand:SI 2 "nonmemory_operand" "")
-		      (match_operand:SI 3 "register_operand" "")))]
-  ""
-  "
-{
-  enum rtx_code code = GET_CODE (operands[1]);
-  rtx ccreg = gen_rtx (REG,
-		       SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
-		       61);
-
-  operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
-}")
-
-;(define_expand "movdicc"
-;  [(set (match_operand:DI 0 "register_operand" "")
-;	(if_then_else (match_operand 1 "comparison_operator" "")
-;		      (match_operand:DI 2 "nonmemory_operand" "")
-;		      (match_operand:DI 3 "register_operand" "")))]
-;  "0 /* ??? this would work better if we had cmpdi */"
-;  "
-;{
-;  enum rtx_code code = GET_CODE (operands[1]);
-;  rtx ccreg = gen_rtx (REG,
-;		       SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
-;		       61);
-;
-;  operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
-;}")
-
-(define_expand "movsfcc"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(if_then_else (match_operand 1 "comparison_operator" "")
-		      (match_operand:SF 2 "nonmemory_operand" "")
-		      (match_operand:SF 3 "register_operand" "")))]
-  ""
-  "
-{
-  enum rtx_code code = GET_CODE (operands[1]);
-  rtx ccreg = gen_rtx (REG,
-		       SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
-		       61);
-
-  operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
-}")
-
-;(define_expand "movdfcc"
-;  [(set (match_operand:DF 0 "register_operand" "")
-;	(if_then_else (match_operand 1 "comparison_operator" "")
-;		      (match_operand:DF 2 "nonmemory_operand" "")
-;		      (match_operand:DF 3 "register_operand" "")))]
-;  "0 /* ??? can generate less efficient code if constants involved */"
-;  "
-;{
-;  enum rtx_code code = GET_CODE (operands[1]);
-;  rtx ccreg = gen_rtx (REG,
-;		       SELECT_CC_MODE (code, arc_compare_op0, arc_compare_op1),
-;		       61);
-;
-;  operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
-;}")
-
-(define_insn "*movsicc_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(if_then_else (match_operand 1 "comparison_operator" "")
-		      (match_operand:SI 2 "nonmemory_operand" "rJi")
-		      (match_operand:SI 3 "register_operand" "0")))]
-  ""
-  "mov.%d1 %0,%S2"
-  [(set_attr "type" "cmove")])
-
-; ??? This doesn't properly handle constants.
-;(define_insn "*movdicc_insn"
-;  [(set (match_operand:DI 0 "register_operand" "=r,r")
-;	(if_then_else (match_operand 1 "comparison_operator" "")
-;		      (match_operand:DI 2 "nonmemory_operand" "r,Ji")
-;		      (match_operand:DI 3 "register_operand" "0,0")))]
-;  "0"
-;  "*
-;{
-;  switch (which_alternative)
-;    {
-;    case 0 :
-;      /* We normally copy the low-numbered register first.  However, if
-;	 the first register operand 0 is the same as the second register of
-;	 operand 1, we must copy in the opposite order.  */
-;      if (REGNO (operands[0]) == REGNO (operands[2]) + 1)
-;	return \"mov.%d1 %R0,%R2\;mov.%d1 %0,%2\";
-;      else
-;	return \"mov.%d1 %0,%2\;mov.%d1 %R0,%R2\";
-;    case 1 :
-;      return \"mov.%d1 %0,%2\;mov.%d1 %R0,%R2\";
-;    }
-;}"
-;  [(set_attr "type" "cmove,cmove")
-;   (set_attr "length" "2,4")])
-
-(define_insn "*movsfcc_insn"
-  [(set (match_operand:SF 0 "register_operand" "=r,r")
-	(if_then_else (match_operand 1 "comparison_operator" "")
-		      (match_operand:SF 2 "nonmemory_operand" "r,E")
-		      (match_operand:SF 3 "register_operand" "0,0")))]
-  ""
-  "@
-   mov.%d1 %0,%2
-   mov.%d1 %0,%2 ; %A2"
-  [(set_attr "type" "cmove,cmove")])
-
-;(define_insn "*movdfcc_insn"
-;  [(set (match_operand:DF 0 "register_operand" "=r,r")
-;	(if_then_else (match_operand 1 "comparison_operator" "")
-;		      (match_operand:DF 2 "nonmemory_operand" "r,E")
-;		      (match_operand:DF 3 "register_operand" "0,0")))]
-;  "0"
-;  "*
-;{
-;  switch (which_alternative)
-;    {
-;    case 0 :
-;      /* We normally copy the low-numbered register first.  However, if
-;	 the first register operand 0 is the same as the second register of
-;	 operand 1, we must copy in the opposite order.  */
-;      if (REGNO (operands[0]) == REGNO (operands[2]) + 1)
-;	return \"mov.%d1 %R0,%R2\;mov.%d1 %0,%2\";
-;      else
-;	return \"mov.%d1 %0,%2\;mov.%d1 %R0,%R2\";
-;    case 1 :
-;      return \"mov.%d1 %0,%L2\;mov.%d1 %R0,%H2 ; %A2\";
-;    }
-;}"
-;  [(set_attr "type" "cmove,cmove")
-;   (set_attr "length" "2,4")])
-
-;; Zero extension instructions.
-;; ??? We don't support volatile memrefs here, but I'm not sure why.
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(zero_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "r,m")))]
-  ""
-  "@
-   extb%? %0,%1
-   ldb%U1 %0,%1"
-  [(set_attr "type" "unary,load")])
-
-(define_insn "*zero_extendqihi2_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
-		       (const_int 0)))
-   (set (match_operand:HI 0 "register_operand" "=r")
-	(zero_extend:HI (match_dup 1)))]
-  ""
-  "extb%?.f %0,%1"
-  [(set_attr "type" "unary")
-   (set_attr "cond" "set_zn")])
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "r,m")))]
-  ""
-  "@
-   extb%? %0,%1
-   ldb%U1 %0,%1"
-  [(set_attr "type" "unary,load")])
-
-(define_insn "*zero_extendqisi2_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
-		       (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (match_dup 1)))]
-  ""
-  "extb%?.f %0,%1"
-  [(set_attr "type" "unary")
-   (set_attr "cond" "set_zn")])
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "r,m")))]
-  ""
-  "@
-   extw%? %0,%1
-   ldw%U1 %0,%1"
-  [(set_attr "type" "unary,load")])
-
-(define_insn "*zero_extendhisi2_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
-		       (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (match_dup 1)))]
-  ""
-  "extw%?.f %0,%1"
-  [(set_attr "type" "unary")
-   (set_attr "cond" "set_zn")])
-
-;; Sign extension instructions.
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "r,m")))]
-  ""
-  "@
-   sexb%? %0,%1
-   ldb.x%U1 %0,%1"
-  [(set_attr "type" "unary,load")])
-
-(define_insn "*extendqihi2_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (sign_extend:SI (match_operand:QI 1 "register_operand" "r"))
-		       (const_int 0)))
-   (set (match_operand:HI 0 "register_operand" "=r")
-	(sign_extend:HI (match_dup 1)))]
-  ""
-  "sexb%?.f %0,%1"
-  [(set_attr "type" "unary")
-   (set_attr "cond" "set_zn")])
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(sign_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "r,m")))]
-  ""
-  "@
-   sexb%? %0,%1
-   ldb.x%U1 %0,%1"
-  [(set_attr "type" "unary,load")])
-
-(define_insn "*extendqisi2_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (sign_extend:SI (match_operand:QI 1 "register_operand" "r"))
-		       (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI (match_dup 1)))]
-  ""
-  "sexb%?.f %0,%1"
-  [(set_attr "type" "unary")
-   (set_attr "cond" "set_zn")])
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "r,m")))]
-  ""
-  "@
-   sexw%? %0,%1
-   ldw.x%U1 %0,%1"
-  [(set_attr "type" "unary,load")])
-
-(define_insn "*extendhisi2_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (sign_extend:SI (match_operand:HI 1 "register_operand" "r"))
-		       (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI (match_dup 1)))]
-  ""
-  "sexw%?.f %0,%1"
-  [(set_attr "type" "unary")
-   (set_attr "cond" "set_zn")])
-
-;; Arithmetic instructions.
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_operand:SI 1 "register_operand" "%r")
-		 (match_operand:SI 2 "nonmemory_operand" "rIJ")))]
-  ""
-  "add%? %0,%1,%2")
-
-(define_insn "*addsi3_set_cc_insn"
-  [(set (reg:CC 61) (compare:CC
-		     (plus:SI (match_operand:SI 1 "register_operand" "%r")
-			      (match_operand:SI 2 "nonmemory_operand" "rIJ"))
-		     (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 1)
-		 (match_dup 2)))]
-  ""
-  "add%?.f %0,%1,%2"
-  [(set_attr "cond" "set")])
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_operand:DI 1 "nonmemory_operand" "%r")
-		 (match_operand:DI 2 "nonmemory_operand" "ri")))
-   (clobber (reg:CC 61))]
-  ""
-  "*
-{
-  rtx op2 = operands[2];
-
-  if (GET_CODE (op2) == CONST_INT)
-    {
-      int sign = INTVAL (op2);
-      if (sign < 0)
-	return \"add.f %L0,%L1,%2\;adc %H0,%H1,-1\";
-      else
-	return \"add.f %L0,%L1,%2\;adc %H0,%H1,0\";
-    }
-  else
-    return \"add.f %L0,%L1,%L2\;adc %H0,%H1,%H2\";
-}"
-  [(set_attr "length" "2")])
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (match_operand:SI 2 "nonmemory_operand" "rIJ")))]
-  ""
-  "sub%? %0,%1,%2")
-
-(define_insn "*subsi3_set_cc_insn"
-  [(set (reg:CC 61) (compare:CC
-		     (minus:SI (match_operand:SI 1 "register_operand" "%r")
-			       (match_operand:SI 2 "nonmemory_operand" "rIJ"))
-		     (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_dup 1)
-		  (match_dup 2)))]
-  ""
-  "sub%?.f %0,%1,%2"
-  [(set_attr "cond" "set")])
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "nonmemory_operand" "r")
-		  (match_operand:DI 2 "nonmemory_operand" "ri")))
-   (clobber (reg:CC 61))]
-  ""
-  "*
-{
-  rtx op2 = operands[2];
-
-  if (GET_CODE (op2) == CONST_INT)
-    {
-      int sign = INTVAL (op2);
-      if (sign < 0)
-	return \"sub.f %L0,%L1,%2\;sbc %H0,%H1,-1\";
-      else
-	return \"sub.f %L0,%L1,%2\;sbc %H0,%H1,0\";
-    }
-  else
-    return \"sub.f %L0,%L1,%L2\;sbc %H0,%H1,%H2\";
-}"
-  [(set_attr "length" "2")])
-
-;; Boolean instructions.
-;;
-;; We don't define the DImode versions as expand_binop does a good enough job.
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (match_operand:SI 1 "register_operand" "%r")
-		(match_operand:SI 2 "nonmemory_operand" "rIJ")))]
-  ""
-  "and%? %0,%1,%2")
-
-(define_insn "*andsi3_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (and:SI (match_operand:SI 1 "register_operand" "%r")
-			       (match_operand:SI 2 "nonmemory_operand" "rIJ"))
-		       (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (match_dup 1)
-		(match_dup 2)))]
-  ""
-  "and%?.f %0,%1,%2"
-  [(set_attr "cond" "set_zn")])
-
-(define_insn "*bicsi3_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(and:SI (match_operand:SI 1 "nonmemory_operand" "r,r,I,J")
-		(not:SI (match_operand:SI 2 "nonmemory_operand" "rI,J,r,r"))))]
-  ""
-  "bic%? %0,%1,%2"
-  [(set_attr "length" "1,2,1,2")])
-
-(define_insn "*bicsi3_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (and:SI (match_operand:SI 1 "register_operand" "%r")
-			       (not:SI (match_operand:SI 2 "nonmemory_operand" "rIJ")))
-		       (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (match_dup 1)
-		(not:SI (match_dup 2))))]
-  ""
-  "bic%?.f %0,%1,%2"
-  [(set_attr "cond" "set_zn")])
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (match_operand:SI 1 "register_operand" "%r")
-		(match_operand:SI 2 "nonmemory_operand" "rIJ")))]
-  ""
-  "or%? %0,%1,%2")
-
-(define_insn "*iorsi3_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (ior:SI (match_operand:SI 1 "register_operand" "%r")
-			       (match_operand:SI 2 "nonmemory_operand" "rIJ"))
-		       (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (match_dup 1)
-		(match_dup 2)))]
-  ""
-  "or%?.f %0,%1,%2"
-  [(set_attr "cond" "set_zn")])
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(xor:SI (match_operand:SI 1 "register_operand" "%r")
-		(match_operand:SI 2 "nonmemory_operand" "rIJ")))]
-  ""
-  "xor%? %0,%1,%2")
-
-(define_insn "*xorsi3_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CCZN
-		       (xor:SI (match_operand:SI 1 "register_operand" "%r")
-			       (match_operand:SI 2 "nonmemory_operand" "rIJ"))
-		       (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(xor:SI (match_dup 1)
-		(match_dup 2)))]
-  ""
-  "xor%?.f %0,%1,%2"
-  [(set_attr "cond" "set_zn")])
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "sub%? %0,0,%1"
-  [(set_attr "type" "unary")])
-
-(define_insn "*negsi2_set_cc_insn"
-  [(set (reg:CC 61) (compare:CC
-		     (neg:SI (match_operand:SI 1 "register_operand" "r"))
-		     (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_dup 1)))]
-  ""
-  "sub%?.f %0,0,%1"
-  [(set_attr "type" "unary")
-   (set_attr "cond" "set")])
-
-(define_insn "negdi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(neg:DI (match_operand:DI 1 "register_operand" "r")))
-   (clobber (reg:SI 61))]
-  ""
-  "sub.f %L0,0,%L1\;sbc %H0,0,%H1"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "xor%? %0,%1,-1"
-  [(set_attr "type" "unary")])
-
-(define_insn "*one_cmplsi2_set_cc_insn"
-  [(set (reg:CCZN 61) (compare:CC
-		       (not:SI (match_operand:SI 1 "register_operand" "r"))
-		       (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_dup 1)))]
-  ""
-  "xor%?.f %0,%1,-1"
-  [(set_attr "type" "unary")
-   (set_attr "cond" "set_zn")])
-
-;; Shift instructions.
-
-(define_expand "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashift:SI (match_operand:SI 1 "register_operand" "")
-		   (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (! TARGET_SHIFTER)
-    {
-      emit_insn (gen_rtx
-		 (PARALLEL, VOIDmode,
-		  gen_rtvec (2,
-			     gen_rtx (SET, VOIDmode, operands[0],
-				      gen_rtx (ASHIFT, SImode, operands[1], operands[2])),
-			     gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)))));
-      DONE;
-    }
-}")
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (! TARGET_SHIFTER)
-    {
-      emit_insn (gen_rtx
-		 (PARALLEL, VOIDmode,
-		  gen_rtvec (2,
-			     gen_rtx (SET, VOIDmode, operands[0],
-				      gen_rtx (ASHIFTRT, SImode, operands[1], operands[2])),
-			     gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)))));
-      DONE;
-    }
-}")
-
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (! TARGET_SHIFTER)
-    {
-      emit_insn (gen_rtx
-		 (PARALLEL, VOIDmode,
-		  gen_rtvec (2,
-			     gen_rtx (SET, VOIDmode, operands[0],
-				      gen_rtx (LSHIFTRT, SImode, operands[1], operands[2])),
-			     gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)))));
-      DONE;
-    }
-}")
-
-(define_insn "*ashlsi3_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(ashift:SI (match_operand:SI 1 "nonmemory_operand" "r,r,I,J")
-		   (match_operand:SI 2 "nonmemory_operand" "rI,J,r,r")))]
-  "TARGET_SHIFTER"
-  "asl%? %0,%1,%2"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1,2,1,2")])
-
-(define_insn "*ashrsi3_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(ashiftrt:SI (match_operand:SI 1 "nonmemory_operand" "r,r,I,J")
-		     (match_operand:SI 2 "nonmemory_operand" "rI,J,r,r")))]
-  "TARGET_SHIFTER"
-  "asr%? %0,%1,%2"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1,2,1,2")])
-
-(define_insn "*lshrsi3_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(lshiftrt:SI (match_operand:SI 1 "nonmemory_operand" "r,r,I,J")
-		     (match_operand:SI 2 "nonmemory_operand" "rI,J,r,r")))]
-  "TARGET_SHIFTER"
-  "lsr%? %0,%1,%2"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1,2,1,2")])
-
-(define_insn "*shift_si3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operator:SI 3 "shift_operator"
-			   [(match_operand:SI 1 "register_operand" "0")
-			    (match_operand:SI 2 "nonmemory_operand" "rIJ")]))
-   (clobber (match_scratch:SI 4 "=&r"))]
-  "! TARGET_SHIFTER"
-  "* return output_shift (operands);"
-  [(set_attr "type" "shift")
-   (set_attr "length" "8")])
-
-;; Compare instructions.
-;; This controls RTL generation and register allocation.
-
-;; We generate RTL for comparisons and branches by having the cmpxx 
-;; patterns store away the operands.  Then, the scc and bcc patterns
-;; emit RTL for both the compare and the branch.
-
-(define_expand "cmpsi"
-  [(set (reg:CC 61)
-	(compare:CC (match_operand:SI 0 "register_operand" "")
-		    (match_operand:SI 1 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  arc_compare_op0 = operands[0];
-  arc_compare_op1 = operands[1];
-  DONE;
-}")
-
-;; ??? We may be able to relax this a bit by adding a new constant 'K' for 0.
-;; This assumes sub.f 0,symbol,0 is a valid insn.
-;; Note that "sub.f 0,r0,1" is an 8 byte insn.  To avoid unnecessarily
-;; creating 8 byte insns we duplicate %1 in the destination reg of the insn
-;; if it's a small constant.
-
-(define_insn "*cmpsi_cc_insn"
-  [(set (reg:CC 61)
-	(compare:CC (match_operand:SI 0 "register_operand" "r,r,r")
-		    (match_operand:SI 1 "nonmemory_operand" "r,I,J")))]
-  ""
-  "@
-   sub.f 0,%0,%1
-   sub.f %1,%0,%1
-   sub.f 0,%0,%1"
-  [(set_attr "type" "compare,compare,compare")])
-
-(define_insn "*cmpsi_cczn_insn"
-  [(set (reg:CCZN 61)
-	(compare:CCZN (match_operand:SI 0 "register_operand" "r,r,r")
-		      (match_operand:SI 1 "nonmemory_operand" "r,I,J")))]
-  ""
-  "@
-   sub.f 0,%0,%1
-   sub.f %1,%0,%1
-   sub.f 0,%0,%1"
-  [(set_attr "type" "compare,compare,compare")])
-
-(define_insn "*cmpsi_ccznc_insn"
-  [(set (reg:CCZNC 61)
-	(compare:CCZNC (match_operand:SI 0 "register_operand" "r,r,r")
-		       (match_operand:SI 1 "nonmemory_operand" "r,I,J")))]
-  ""
-  "@
-   sub.f 0,%0,%1
-   sub.f %1,%0,%1
-   sub.f 0,%0,%1"
-  [(set_attr "type" "compare,compare,compare")])
-
-;; Next come the scc insns.
-
-(define_expand "seq"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (EQ, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "sne"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ne:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (NE, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "sgt"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(gt:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (GT, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "sle"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(le:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (LE, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "sge"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ge:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (GE, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "slt"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lt:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (LT, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "sgtu"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(gtu:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (GTU, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "sleu"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(leu:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (LEU, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "sgeu"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(geu:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (GEU, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "sltu"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ltu:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (LTU, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_insn "*scc_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operator:SI 1 "comparison_operator" [(reg 61) (const_int 0)]))]
-  ""
-  "mov %0,1\;sub.%D1 %0,%0,%0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
-
-;; ??? Look up negscc insn.  See pa.md for example.
-(define_insn "*neg_scc_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operator:SI 1 "comparison_operator"
-		 [(reg 61) (const_int 0)])))]
-  ""
-  "mov %0,-1\;sub.%D1 %0,%0,%0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
-
-(define_insn "*not_scc_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operator:SI 1 "comparison_operator"
-		 [(reg 61) (const_int 0)])))]
-  ""
-  "mov %0,1\;sub.%d1 %0,%0,%0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
-
-;; These control RTL generation for conditional jump insns
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (EQ, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (NE, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (GT, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (LE, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (GE, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (LT, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (GTU, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (LEU, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (GEU, arc_compare_op0, arc_compare_op1);
-}")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (LTU, arc_compare_op0, arc_compare_op1);
-}")
-
-;; Now match both normal and inverted jump.
-
-(define_insn "*branch_insn"
-  [(set (pc)
-	(if_then_else (match_operator 1 "proper_comparison_operator"
-				      [(reg 61) (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  if (arc_ccfsm_branch_deleted_p ())
-    {
-      arc_ccfsm_record_branch_deleted ();
-      return \"; branch deleted, next insns conditionalized\";
-    }
-  else
-    return \"%~b%d1%# %l0\";
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn "*rev_branch_insn"
-  [(set (pc)
-	(if_then_else (match_operator 1 "proper_comparison_operator"
-				      [(reg 61) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  "REVERSIBLE_CC_MODE (GET_MODE (XEXP (operands[1], 0)))"
-  "*
-{
-  if (arc_ccfsm_branch_deleted_p ())
-    {
-      arc_ccfsm_record_branch_deleted ();
-      return \"; branch deleted, next insns conditionalized\";
-    }
-  else
-    return \"%~b%D1%# %l0\";
-}"
-  [(set_attr "type" "branch")])
-
-;; Unconditional and other jump instructions.
-
-(define_insn "jump"
-  [(set (pc) (label_ref (match_operand 0 "" "")))]
-  ""
-  "b%* %l0"
-  [(set_attr "type" "uncond_branch")])
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
-  ""
-  "j%* %a0"
-  [(set_attr "type" "uncond_branch")])
- 
-;; Implement a switch statement.
-;; This wouldn't be necessary in the non-pic case if we could distinguish
-;; label refs of the jump table from other label refs.  The problem is that
-;; label refs are output as "%st(.LL42)" but we don't want the %st - we want
-;; the real address since it's the address of the table.
-
-(define_expand "casesi"
-  [(set (match_dup 5)
-	(minus:SI (match_operand:SI 0 "register_operand" "")
-		  (match_operand:SI 1 "nonmemory_operand" "")))
-   (set (reg:CC 61)
-	(compare:CC (match_dup 5)
-		    (match_operand:SI 2 "nonmemory_operand" "")))
-   (set (pc)
-	(if_then_else (gtu (reg:CC 61)
-			   (const_int 0))
-		      (label_ref (match_operand 4 "" ""))
-		      (pc)))
-   (parallel
-    [(set (pc)
-	  (mem:SI (plus:SI (mult:SI (match_dup 5)
-				    (const_int 4))
-			   (label_ref (match_operand 3 "" "")))))
-     (clobber (match_scratch:SI 6 ""))
-     (clobber (match_scratch:SI 7 ""))])]
-  ""
-  "
-{
-  operands[5] = gen_reg_rtx (SImode);
-}")
-
-(define_insn "*casesi_insn"
-  [(set (pc)
-	(mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "r")
-				  (const_int 4))
-			 (label_ref (match_operand 1 "" "")))))
-   (clobber (match_scratch:SI 2 "=r"))
-   (clobber (match_scratch:SI 3 "=r"))]
-  ""
-  "*
-{
-  output_asm_insn (\"mov %2,%1\", operands);
-  if (TARGET_SHIFTER)
-    output_asm_insn (\"asl %3,%0,2\", operands);
-  else
-    output_asm_insn (\"asl %3,%0\;asl %3,%3\", operands);
-  output_asm_insn (\"ld %2,[%2,%3]\", operands);
-  output_asm_insn (\"j.nd %a2\", operands);
-  return \"\";
-}"
-  [(set_attr "type" "uncond_branch")
-   (set_attr "length" "6")])
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "address_operand" "p"))
-   (use (label_ref (match_operand 1 "" "")))]
-  "0 /* disabled -> using casesi now */"
-  "j%* %a0"
-  [(set_attr "type" "uncond_branch")])
-
-(define_expand "call"
-  ;; operands[1] is stack_size_rtx
-  ;; operands[2] is next_arg_register
-  [(parallel [(call (match_operand:SI 0 "call_operand" "")
-		    (match_operand 1 "" ""))
-	     (clobber (reg:SI 31))])]
-  ""
-  "")
-
-(define_insn "*call_via_reg"
-  [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
-	 (match_operand 1 "" ""))
-   (clobber (reg:SI 31))]
-  ""
-  "lr blink,[status]\;j.d %0\;add blink,blink,2"
-  [(set_attr "type" "call_no_delay_slot")
-   (set_attr "length" "3")])
-
-(define_insn "*call_via_label"
-  [(call (mem:SI (match_operand:SI 0 "call_address_operand" ""))
-	 (match_operand 1 "" ""))
-   (clobber (reg:SI 31))]
-  ""
-  ; The %~ is necessary in case this insn gets conditionalized and the previous
-  ; insn is the cc setter.
-  "%~bl%!%* %0"
-  [(set_attr "type" "call")
-   (set_attr "cond" "canuse")])
-
-(define_expand "call_value"
-  ;; operand 2 is stack_size_rtx
-  ;; operand 3 is next_arg_register
-  [(parallel [(set (match_operand 0 "register_operand" "=r")
-		   (call (match_operand:SI 1 "call_operand" "")
-			 (match_operand 2 "" "")))
-	     (clobber (reg:SI 31))])]
-  ""
-  "")
-
-(define_insn "*call_value_via_reg"
-  [(set (match_operand 0 "register_operand" "=r")
-	(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
-	      (match_operand 2 "" "")))
-   (clobber (reg:SI 31))]
-  ""
-  "lr blink,[status]\;j.d %1\;add blink,blink,2"
-  [(set_attr "type" "call_no_delay_slot")
-   (set_attr "length" "3")])
-
-(define_insn "*call_value_via_label"
-  [(set (match_operand 0 "register_operand" "=r")
-	(call (mem:SI (match_operand:SI 1 "call_address_operand" ""))
-	      (match_operand 2 "" "")))
-   (clobber (reg:SI 31))]
-  ""
-  ; The %~ is necessary in case this insn gets conditionalized and the previous
-  ; insn is the cc setter.
-  "%~bl%!%* %1"
-  [(set_attr "type" "call")
-   (set_attr "cond" "canuse")])
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-  [(set_attr "type" "misc")])
-
-;; Special pattern to flush the icache.
-;; ??? Not sure what to do here.  Some ARC's are known to support this.
-
-(define_insn "flush_icache"
-  [(unspec_volatile [(match_operand 0 "memory_operand" "m")] 0)]
-  ""
-  "* return \"\";"
-  [(set_attr "type" "misc")])
-
-;; Split up troublesome insns for better scheduling.
-
-;; Peepholes go at the end.
diff --git a/gcc/config/arc/initfini.c b/gcc/config/arc/initfini.c
deleted file mode 100755
index 084e229..0000000
--- a/gcc/config/arc/initfini.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* .init/.fini section handling + C++ global constructor/destructor handling.
-   This file is based on crtstuff.c, sol2-crti.asm, sol2-crtn.asm.
-
-Copyright (C) 1995, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this file with files
-   compiled with GCC to produce an executable, this does not cause
-   the resulting executable to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-/*  Declare a pointer to void function type.  */
-typedef void (*func_ptr) (void);
-
-#ifdef CRT_INIT
-
-/* NOTE:  In order to be able to support SVR4 shared libraries, we arrange
-   to have one set of symbols { __CTOR_LIST__, __DTOR_LIST__, __CTOR_END__,
-   __DTOR_END__ } per root executable and also one set of these symbols
-   per shared library.  So in any given whole process image, we may have
-   multiple definitions of each of these symbols.  In order to prevent
-   these definitions from conflicting with one another, and in order to
-   ensure that the proper lists are used for the initialization/finalization
-   of each individual shared library (respectively), we give these symbols
-   only internal (i.e. `static') linkage, and we also make it a point to
-   refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__
-   symbol in crtinit.o, where they are defined.  */
-
-static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors")))
-     = { (func_ptr) (-1) };
-
-static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors")))
-     = { (func_ptr) (-1) };
-
-/* Run all the global destructors on exit from the program.  */
- 
-/* Some systems place the number of pointers in the first word of the
-   table.  On SVR4 however, that word is -1.  In all cases, the table is
-   null-terminated.  On SVR4, we start from the beginning of the list and
-   invoke each per-compilation-unit destructor routine in order
-   until we find that null.
-
-   Note that this function MUST be static.  There will be one of these
-   functions in each root executable and one in each shared library, but
-   although they all have the same code, each one is unique in that it
-   refers to one particular associated `__DTOR_LIST__' which belongs to the
-   same particular root executable or shared library file.  */
-
-static void __do_global_dtors ()
-asm ("__do_global_dtors") __attribute__ ((section (".text")));
-
-static void
-__do_global_dtors ()
-{
-  func_ptr *p;
-  for (p = __DTOR_LIST__ + 1; *p; p++)
-    (*p) ();
-}
-
-/* .init section start.
-   This must appear at the start of the .init section.  */
-
-asm ("
-	.section .init\n
-	.global init\n
-	.word 0\n
-init:\n
-	st blink,[sp,4]\n
-	st fp,[sp]\n
-	mov fp,sp\n
-	sub sp,sp,16\n
-");
-
-/* .fini section start.
-   This must appear at the start of the .init section.  */
-
-asm ("
-	.section .fini\n
-	.global fini\n
-	.word 0\n
-fini:\n
-	st blink,[sp,4]\n
-	st fp,[sp]\n
-	mov fp,sp\n
-	sub sp,sp,16\n
-	bl.nd __do_global_dtors
-");
-
-#endif /* CRT_INIT */
-
-#ifdef CRT_FINI
-
-/* Put a word containing zero at the end of each of our two lists of function
-   addresses.  Note that the words defined here go into the .ctors and .dtors
-   sections of the crtend.o file, and since that file is always linked in
-   last, these words naturally end up at the very ends of the two lists
-   contained in these two sections.  */
-
-static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors")))
-     = { (func_ptr) 0 };
-
-static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors")))
-     = { (func_ptr) 0 };
-
-/* Run all global constructors for the program.
-   Note that they are run in reverse order.  */
-
-static void __do_global_ctors ()
-asm ("__do_global_ctors") __attribute__ ((section (".text")));
-
-static void
-__do_global_ctors ()
-{
-  func_ptr *p;
-  for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--)
-    (*p) ();
-}
-
-/* .init section end.
-   This must live at the end of the .init section.  */
-
-asm ("
-	.section .init\n
-	bl.nd __do_global_ctors
-	ld blink,[fp,4]\n
-	j.d blink\n
-	ld.a fp,[sp,16]\n
-");
-
-/* .fini section end.
-   This must live at the end of the .fini section.  */
-
-asm ("
-	.section .fini\n
-	ld blink,[fp,4]\n
-	j.d blink\n
-	ld.a fp,[sp,16]\n
-");
-
-#endif /* CRT_FINI */
diff --git a/gcc/config/arc/lib1funcs.asm b/gcc/config/arc/lib1funcs.asm
deleted file mode 100755
index a2d509a..0000000
--- a/gcc/config/arc/lib1funcs.asm
+++ /dev/null
@@ -1,273 +0,0 @@
-; libgcc1 routines for ARC cpu.
-
-/* Copyright (C) 1995, 1997 Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with other files,
-   some of which are compiled with GCC, to produce an executable,
-   this library does not by itself cause the resulting executable
-   to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-#ifdef  L_mulsi3
-	.section .text
-	.align 4
-
-#ifdef __base__
-	.cpu base
-	.global ___mulsi3
-___mulsi3:
-
-/* This the simple version.
-
-  while (a) 
-    {
-      if (a & 1)
-        r += b;
-      a >>= 1;
-      b <<= 1;
-    }
-*/
-	mov r2,0		; Accumulate result here.
-.Lloop:
-	sub.f 0,r0,0		; while (a)
-	nop
-	beq.nd .Ldone
-	and.f 0,r0,1		; if (a & 1)
-	add.nz r2,r2,r1		; r += b
-	lsr r0,r0		; a >>= 1
-	b.d .Lloop
-	lsl r1,r1		; b <<= 1
-.Ldone:
-	j.d blink
-	mov r0,r2
-#endif
-
-#endif /* L_mulsi3 */
-
-#ifdef  L_umulsidi3
-	.section .text
-	.align 4
-
-#ifdef __base__
-	.cpu base
-	.global ___umulsidi3
-___umulsidi3:
-
-/* This the simple version.
-
-  while (a) 
-    {
-      if (a & 1)
-        r += b;
-      a >>= 1;
-      b <<= 1;
-    }
-*/
-	mov r2,0		; Top part of b.
-	mov r3,0		; Accumulate result here.
-	mov r4,0
-.Lloop:
-	sub.f 0,r0,0		; while (a)
-	nop
-	beq.nd .Ldone
-	and.f 0,r0,1		; if (a & 1)
-	add.nz r4,r4,r1		; r += b
-	adc.nz r3,r3,r2
-	lsr r0,r0		; a >>= 1
-	lsl.f r1,r1		; b <<= 1
-	b.d .Lloop
-	rlc r2,r2
-.Ldone:
-#ifdef __big_endian__
-	mov r1,r4
-	j.d blink
-	mov r0,r3
-#else
-	mov r0,r4
-	j.d blink
-	mov r1,r3
-#endif
-#endif
-
-#endif /* L_umulsidi3 */
-
-#ifdef L_divmod_tools
-
-; Utilities used by all routines.
-
-	.section .text
-	.align 4
-
-; inputs: r0 = numerator, r1 = denominator
-; outputs: positive r0/r1,
-;          r6.bit1 = sign of numerator, r6.bit0 = sign of result
-
-	.global ___divnorm
-___divnorm:
-	mov r6,0		; keep sign in r6
-	sub.f 0,r0,0		; is numerator -ve?
-	sub.lt r0,0,r0		; negate numerator
-	mov.lt r6,3		; sign is -ve
-	sub.f 0,r1,0		; is denominator -ve?
-	sub.lt r1,0,r1		; negate denominator
-	xor.lt r6,r6,1		; toggle sign
-	j.nd blink
-
-/*
-unsigned long
-udivmodsi4(int modwanted, unsigned long num, unsigned long den)
-{
-  unsigned long bit = 1;
-  unsigned long res = 0;
-
-  while (den < num && bit && !(den & (1L<<31)))
-    {
-      den <<=1;
-      bit <<=1;
-    }
-  while (bit)
-    {
-      if (num >= den)
-	{
-	  num -= den;
-	  res |= bit;
-	}
-      bit >>=1;
-      den >>=1;
-    }
-  if (modwanted) return num;
-  return res;
-}
-*/
-
-; inputs: r0 = numerator, r1 = denominator
-; outputs: r0 = quotient, r1 = remainder, r2/r3 trashed
-
-	.global ___udivmodsi4
-___udivmodsi4:
-	mov r2,1		; bit = 1
-	mov r3,0		; res = 0
-.Lloop1:
-	sub.f 0,r1,r0		; while (den < num
-	nop
-	bnc.nd .Lloop2
-	sub.f 0,r2,0		; && bit
-	nop
-	bz.nd .Lloop2
-	lsl.f 0,r1		; && !(den & (1<<31))
-	nop
-	bc.nd .Lloop2
-	lsl r1,r1		; den <<= 1
-	b.d .Lloop1
-	lsl r2,r2		; bit <<= 1
-.Lloop2:
-	sub.f 0,r2,0		; while (bit)
-	nop
-	bz.nd .Ldivmodend
-	sub.f 0,r0,r1		; if (num >= den)
-	nop
-	bc.nd .Lshiftdown
-	sub r0,r0,r1		; num -= den
-	or r3,r3,r2		; res |= bit
-.Lshiftdown:
-	lsr r2,r2		; bit >>= 1
-	b.d .Lloop2
-	lsr r1,r1		; den >>= 1
-.Ldivmodend:
-	mov r1,r0		; r1 = mod
-	j.d blink
-	mov r0,r3		; r0 = res
-
-#endif
-
-#ifdef  L_udivsi3
-	.section .text
-	.align 4
-
-#ifdef __base__
-	.cpu base
-	.global ___udivsi3
-___udivsi3:
-	mov r7,blink
-	bl.nd ___udivmodsi4
-	j.nd r7
-#endif
-
-#endif /* L_udivsi3 */
-
-#ifdef  L_divsi3
-	.section .text
-	.align 4
-
-#ifdef __base__
-	.cpu base
-	.global ___divsi3
-___divsi3:
-	mov r7,blink
-	bl.nd ___divnorm
-	bl.nd ___udivmodsi4
-	and.f 0,r6,1
-	sub.nz r0,0,r0		; cannot go in delay slot, has limm value
-	j.nd r7
-#endif
-
-#endif /* L_divsi3 */
-
-#ifdef  L_umodsi3
-	.section .text
-	.align 4
-
-#ifdef __base__
-	.cpu base
-	.global ___umodsi3
-___umodsi3:
-	mov r7,blink
-	bl.nd ___udivmodsi4
-	j.d r7
-	mov r0,r1
-#endif
-
-#endif /* L_umodsi3 */
-
-#ifdef  L_modsi3
-	.section .text
-	.align 4
-
-#ifdef __base__
-	.cpu base
-	.global ___modsi3
-___modsi3:
-	mov r7,blink
-	bl.nd ___divnorm
-	bl.nd ___udivmodsi4
-	and.f 0,r6,2
-	sub.nz r1,0,r1
-	j.d r7
-	mov r0,r1
-#endif
-
-#endif /* L_modsi3 */
diff --git a/gcc/config/arc/t-arc b/gcc/config/arc/t-arc
deleted file mode 100755
index d922c27..0000000
--- a/gcc/config/arc/t-arc
+++ /dev/null
@@ -1,72 +0,0 @@
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = arc/lib1funcs.asm
-LIB1ASMFUNCS = _mulsi3 _umulsidi3 _udivsi3 _divsi3 _umodsi3 _modsi3 _divmod_tools
-
-# We need libgcc routines to be mangled according to which cpu they
-# were compiled for.
-# ??? -mmangle-cpu passed by default for now.
-#LIBGCC2_CFLAGS = -g1 -O2 $(LIBGCC2_INCLUDES) $(GCC_CFLAGS) -mmangle-cpu
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#ifndef __big_endian__' > dp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
-	echo '#endif' >> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#ifndef __big_endian__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
-	echo '#endif' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# .init/.fini section routines
-
-x-crtinit.o: $(srcdir)/config/arc/initfini.c $(GCC_PASSES) $(CONFIG_H)
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(CRTSTUFF_T_CFLAGS) \
-	  -DCRT_INIT -finhibit-size-directive -fno-inline-functions \
-	  -g0 -c $(srcdir)/config/arc/initfini.c -o $(dir)/crtinit.o
-
-x-crtfini.o: $(srcdir)/config/arc/initfini.c $(GCC_PASSES) $(CONFIG_H)
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(CRTSTUFF_T_CFLAGS) \
-	  -DCRT_FINI -finhibit-size-directive -fno-inline-functions \
-	  -g0 -c $(srcdir)/config/arc/initfini.c -o $(dir)/crtfini.o
-
-MULTILIB_OPTIONS = EB
-MULTILIB_DIRNAMES = be
-
-# We need our own versions to build multiple copies of crt*.o.
-# ??? Use new support in Makefile.
-
-LIBGCC = stmp-multilib-arc
-INSTALL_LIBGCC = install-multilib-arc
-
-stmp-multilib-arc: stmp-multilib
-	for i in `$(GCC_FOR_TARGET) --print-multi-lib`; do \
-	  dir=`echo $$i | sed -e 's/;.*$$//'`; \
-	  flags=`echo $$i | sed -e 's/^[^;]*;//' -e 's/@/ -/g'`; \
-	  $(MAKE) GCC_FOR_TARGET="$(GCC_FOR_TARGET)" \
-	    CC="$(CC)" CFLAGS="$(CFLAGS)" \
-	    HOST_PREFIX="$(HOST_PREFIX)" HOST_PREFIX_1="$(HOST_PREFIX_1)" \
-	    GCC_CFLAGS="$(GCC_CFLAGS) $${flags}" \
-	    INCLUDES="$(INCLUDES)" CRTSTUFF_T_CFLAGS=$(CRTSTUFF_T_CFLAGS) \
-	    dir="$${dir}" x-crtinit.o x-crtfini.o; \
-	  if [ $$? -eq 0 ] ; then true; else exit 1; fi; \
-	done
-	touch stmp-multilib-arc
-
-install-multilib-arc: install-multilib
-	for i in `$(GCC_FOR_TARGET) --print-multi-lib`; do \
-	  dir=`echo $$i | sed -e 's/;.*$$//'`; \
-	  rm -f $(libsubdir)/$${dir}/crtinit.o; \
-	  $(INSTALL_DATA) $${dir}/crtinit.o $(libsubdir)/$${dir}/crtinit.o; \
-	  chmod a-x $(libsubdir)/$${dir}/crtinit.o; \
-	  rm -f $(libsubdir)/$${dir}/crtfini.o; \
-	  $(INSTALL_DATA) $${dir}/crtfini.o $(libsubdir)/$${dir}/crtfini.o; \
-	  chmod a-x $(libsubdir)/$${dir}/crtfini.o; \
-	done
diff --git a/gcc/config/arc/xm-arc.h b/gcc/config/arc/xm-arc.h
deleted file mode 100755
index ba011e9..0000000
--- a/gcc/config/arc/xm-arc.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Configuration for GNU C-compiler for the ARC processor.
-   Copyright (C) 1994, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Doubles are stored in memory with the high order word first.  This
-   matters when cross-compiling.  */
-#define HOST_WORDS_BIG_ENDIAN 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* If compiled with Sun CC, the use of alloca requires this #include.  */
-#ifndef __GNUC__
-#include "alloca.h"
-#endif
diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c
deleted file mode 100755
index abbfba1..0000000
--- a/gcc/config/c4x/c4x.c
+++ /dev/null
@@ -1,4341 +0,0 @@
-/* Subroutines for assembler code output on the TMS320C[34]x
-   Copyright (C) 1994-98, 1999 Free Software Foundation, Inc.
-
-   Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
-              and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
-
-   This file is part of GNU CC.
-
-   GNU CC is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GNU CC is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GNU CC; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
-
-/* Some output-actions in c4x.md need these.  */
-#include "config.h"
-#include "system.h"
-#include "toplev.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "basic-block.h"
-#include "real.h"
-#include "insn-config.h"
-#include "insn-attr.h"
-#include "insn-codes.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "tree.h"
-#include "expr.h"
-#include "flags.h"
-#include "loop.h"
-#include "recog.h"
-#include "c-tree.h"
-
-static int c4x_leaf_function;
-
-static char *float_reg_names[] = FLOAT_REGISTER_NAMES;
-
-/* Array of the smallest class containing reg number REGNO, indexed by
-   REGNO.  Used by REGNO_REG_CLASS in c4x.h.  We assume that all these
-   registers are available and set the class to NO_REGS for registers 
-   that the target switches say are unavailable.  */
-
-enum reg_class c4x_regclass_map[FIRST_PSEUDO_REGISTER] =
-{
-                                /* Reg          Modes           Saved  */
-  R0R1_REGS,			/* R0           QI, QF, HF      No  */
-  R0R1_REGS,			/* R1           QI, QF, HF      No  */
-  R2R3_REGS,			/* R2           QI, QF, HF      No  */
-  R2R3_REGS,			/* R3           QI, QF, HF      No  */
-  EXT_LOW_REGS,			/* R4           QI, QF, HF      QI  */
-  EXT_LOW_REGS,			/* R5           QI, QF, HF      QI  */
-  EXT_LOW_REGS,			/* R6           QI, QF, HF      QF  */
-  EXT_LOW_REGS,			/* R7           QI, QF, HF      QF  */
-  ADDR_REGS,			/* AR0          QI              No  */
-  ADDR_REGS,			/* AR1          QI              No  */
-  ADDR_REGS,			/* AR2          QI              No  */
-  ADDR_REGS,			/* AR3          QI              QI  */
-  ADDR_REGS,			/* AR4          QI              QI  */
-  ADDR_REGS,			/* AR5          QI              QI  */
-  ADDR_REGS,			/* AR6          QI              QI  */
-  ADDR_REGS,			/* AR7          QI              QI  */
-  DP_REG,			/* DP           QI              No  */
-  INDEX_REGS,			/* IR0          QI              No  */
-  INDEX_REGS,			/* IR1          QI              No  */
-  BK_REG,			/* BK           QI              QI  */
-  SP_REG,			/* SP           QI              No  */
-  ST_REG,			/* ST           CC              No  */
-  NO_REGS,			/* DIE/IE                       No  */
-  NO_REGS,			/* IIE/IF                       No  */
-  NO_REGS,			/* IIF/IOF                      No  */
-  INT_REGS,			/* RS           QI              No  */
-  INT_REGS,			/* RE           QI              No  */
-  RC_REG,			/* RC           QI              No  */
-  EXT_REGS,			/* R8           QI, QF, HF      QI  */
-  EXT_REGS,			/* R9           QI, QF, HF      No  */
-  EXT_REGS,			/* R10          QI, QF, HF      No  */
-  EXT_REGS,			/* R11          QI, QF, HF      No  */
-};
-
-enum machine_mode c4x_caller_save_map[FIRST_PSEUDO_REGISTER] =
-{
-                                /* Reg          Modes           Saved  */
-  HFmode,			/* R0           QI, QF, HF      No  */
-  HFmode,			/* R1           QI, QF, HF      No  */
-  HFmode,			/* R2           QI, QF, HF      No  */
-  HFmode,			/* R3           QI, QF, HF      No  */
-  QFmode,			/* R4           QI, QF, HF      QI  */
-  QFmode,			/* R5           QI, QF, HF      QI  */
-  QImode,			/* R6           QI, QF, HF      QF  */
-  QImode,			/* R7           QI, QF, HF      QF  */
-  QImode,			/* AR0          QI              No  */
-  QImode,			/* AR1          QI              No  */
-  QImode,			/* AR2          QI              No  */
-  QImode,			/* AR3          QI              QI  */
-  QImode,			/* AR4          QI              QI  */
-  QImode,			/* AR5          QI              QI  */
-  QImode,			/* AR6          QI              QI  */
-  QImode,			/* AR7          QI              QI  */
-  VOIDmode,			/* DP           QI              No  */
-  QImode,			/* IR0          QI              No  */
-  QImode,			/* IR1          QI              No  */
-  QImode,			/* BK           QI              QI  */
-  VOIDmode,			/* SP           QI              No  */
-  VOIDmode,			/* ST           CC              No  */
-  VOIDmode,			/* DIE/IE                       No  */
-  VOIDmode,			/* IIE/IF                       No  */
-  VOIDmode,			/* IIF/IOF                      No  */
-  QImode,			/* RS           QI              No  */
-  QImode,			/* RE           QI              No  */
-  VOIDmode,			/* RC           QI              No  */
-  QFmode,			/* R8           QI, QF, HF      QI  */
-  HFmode,			/* R9           QI, QF, HF      No  */
-  HFmode,			/* R10          QI, QF, HF      No  */
-  HFmode,			/* R11          QI, QF, HF      No  */
-};
-
-
-/* Test and compare insns in c4x.md store the information needed to
-   generate branch and scc insns here.  */
-
-struct rtx_def *c4x_compare_op0 = NULL_RTX;
-struct rtx_def *c4x_compare_op1 = NULL_RTX;
-
-char *c4x_rpts_cycles_string;
-int c4x_rpts_cycles = 0;	/* Max. cycles for RPTS */
-char *c4x_cpu_version_string;
-int c4x_cpu_version = 40;	/* CPU version C30/31/32/40/44 */
-
-/* Pragma definitions.  */
-
-tree code_tree = NULL_TREE;
-tree data_tree = NULL_TREE;
-tree pure_tree = NULL_TREE;
-tree noreturn_tree = NULL_TREE;
-tree interrupt_tree = NULL_TREE;
-
-
-/* Override command line options.
-   Called once after all options have been parsed.
-   Mostly we process the processor
-   type and sometimes adjust other TARGET_ options.  */
-
-void
-c4x_override_options ()
-{
-  if (c4x_rpts_cycles_string)
-    c4x_rpts_cycles = atoi (c4x_rpts_cycles_string);
-  else
-    c4x_rpts_cycles = 0;
-
-  if (TARGET_C30)
-    c4x_cpu_version = 30;
-  else if (TARGET_C31)
-    c4x_cpu_version = 31;
-  else if (TARGET_C32)
-    c4x_cpu_version = 32;
-  else if (TARGET_C40)
-    c4x_cpu_version = 40;
-  else if (TARGET_C44)
-    c4x_cpu_version = 44;
-  else
-    c4x_cpu_version = 40;	       
-
-  /* -mcpu=xx overrides -m40 etc.  */
-  if (c4x_cpu_version_string)
-    c4x_cpu_version = atoi (c4x_cpu_version_string);
-
-  target_flags &= ~(C30_FLAG | C31_FLAG | C32_FLAG | C40_FLAG | C44_FLAG);
-
-  switch (c4x_cpu_version)
-    {
-    case 30: target_flags |= C30_FLAG; break;
-    case 31: target_flags |= C31_FLAG; break;
-    case 32: target_flags |= C32_FLAG; break;
-    case 40: target_flags |= C40_FLAG; break;
-    case 44: target_flags |= C44_FLAG; break;
-    default:
-      warning ("Unknown CPU version %d, using 40.\n", c4x_cpu_version);
-      c4x_cpu_version = 40;
-      target_flags |= C40_FLAG;
-    }
-
-  if (TARGET_C30 || TARGET_C31 || TARGET_C32)
-    target_flags |= C3X_FLAG;
-  else
-    target_flags &= ~C3X_FLAG;
-
-  /* Convert foo / 8.0 into foo * 0.125, etc.  */
-  flag_fast_math = 1;
-
-  /* We should phase out the following at some stage.
-     This provides compatibility with the old -mno-aliases option.  */
-  if (! TARGET_ALIASES && ! flag_argument_noalias)
-    flag_argument_noalias = 1;
-}
-
-/* This is called before c4x_override_options.  */
-void
-c4x_optimization_options (level, size)
-     int level;
-     int size ATTRIBUTE_UNUSED;
-{
-  /* Scheduling before register allocation can screw up global
-     register allocation, especially for functions that use MPY||ADD
-     instructions.  The benefit we gain we get by scheduling before
-     register allocation is probably marginal anyhow.  */
-  flag_schedule_insns = 0;
-
-  /* When optimizing, enable use of RPTB instruction.  */
-  if (level >= 1)
-    flag_branch_on_count_reg = 1;
-}
-
-/* Write an ASCII string.  */
-
-#define C4X_ASCII_LIMIT 40
-
-void
-c4x_output_ascii (stream, ptr, len)
-     FILE *stream;
-     unsigned char *ptr;
-     int len;
-{
-  char sbuf[C4X_ASCII_LIMIT + 1];
-  int s, first, onlys;
-
-  if (len)
-    {
-      fprintf (stream, "\t.byte\t");
-      first = 1;
-    }
-
-  for (s = 0; len > 0; --len, ++ptr)
-    {
-      onlys = 0;
-
-      /* Escape " and \ with a \".  */
-      if (*ptr == '\"' || *ptr == '\\')
-	sbuf[s++] = '\\';
-
-      /* If printable - add to buff.  */
-      if (*ptr >= 0x20 && *ptr < 0x7f)
-	{
-	  sbuf[s++] = *ptr;
-	  if (s < C4X_ASCII_LIMIT - 1)
-	    continue;
-	  onlys = 1;
-	}
-      if (s)
-	{
-	  if (first)
-	    first = 0;
-	  else
-	    fputc (',', stream);
-
-	  sbuf[s] = 0;
-	  fprintf (stream, "\"%s\"", sbuf);
-	  s = 0;
-	}
-      if (onlys)
-	continue;
-
-      if (first)
-	first = 0;
-      else
-	fputc (',', stream);
-
-      fprintf (stream, "%d", *ptr);
-    }
-  if (s)
-    {
-      if (! first)
-	fputc (',', stream);
-
-      sbuf[s] = 0;
-      fprintf (stream, "\"%s\"", sbuf);
-      s = 0;
-    }
-  fputc ('\n', stream);
-}
-
-
-int
-c4x_hard_regno_mode_ok (regno, mode)
-     int regno;
-     enum machine_mode mode;
-{
-  switch (mode)
-    {
-#if Pmode != QImode
-    case Pmode:			/* Pointer (24/32 bits) */
-#endif
-    case QImode:		/* Integer (32 bits) */
-      return IS_INT_REG (regno);
-
-    case QFmode:		/* Float, Double (32 bits) */
-    case HFmode:		/* Long Double (40 bits) */
-      return IS_EXT_REG (regno);
-
-    case CCmode:		/* Condition Codes */
-    case CC_NOOVmode:		/* Condition Codes */
-      return IS_ST_REG (regno);
-
-    case HImode:		/* Long Long (64 bits) */
-      /* We need two registers to store long longs.  Note that 
-	 it is much easier to constrain the first register
-	 to start on an even boundary.  */
-      return IS_INT_REG (regno)
-	&& IS_INT_REG (regno + 1)
-	&& (regno & 1) == 0;
-
-    default:
-      return 0;			/* We don't support these modes */
-    }
-
-  return 0;
-}
-
-
-/* The TI C3x C compiler register argument runtime model uses 6 registers,
-   AR2, R2, R3, RC, RS, RE.
-
-   The first two floating point arguments (float, double, long double)
-   that are found scanning from left to right are assigned to R2 and R3.
-
-   The remaining integer (char, short, int, long) or pointer arguments
-   are assigned to the remaining registers in the order AR2, R2, R3,
-   RC, RS, RE when scanning left to right, except for the last named
-   argument prior to an ellipsis denoting variable number of
-   arguments.  We don't have to worry about the latter condition since
-   function.c treats the last named argument as anonymous (unnamed).
-
-   All arguments that cannot be passed in registers are pushed onto
-   the stack in reverse order (right to left).  GCC handles that for us.
-
-   c4x_init_cumulative_args() is called at the start, so we can parse
-   the args to see how many floating point arguments and how many
-   integer (or pointer) arguments there are.  c4x_function_arg() is
-   then called (sometimes repeatedly) for each argument (parsed left
-   to right) to obtain the register to pass the argument in, or zero
-   if the argument is to be passed on the stack.  Once the compiler is
-   happy, c4x_function_arg_advance() is called.
-
-   Don't use R0 to pass arguments in, we use 0 to indicate a stack
-   argument.  */
-
-static int c4x_int_reglist[3][6] =
-{
-  {AR2_REGNO, R2_REGNO, R3_REGNO, RC_REGNO, RS_REGNO, RE_REGNO},
-  {AR2_REGNO, R3_REGNO, RC_REGNO, RS_REGNO, RE_REGNO, 0},
-  {AR2_REGNO, RC_REGNO, RS_REGNO, RE_REGNO, 0, 0}
-};
-
-static int c4x_fp_reglist[2] = {R2_REGNO, R3_REGNO};
-
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a
-   function whose data type is FNTYPE.
-   For a library call, FNTYPE is  0.  */
-
-void
-c4x_init_cumulative_args (cum, fntype, libname)
-     CUMULATIVE_ARGS *cum;	/* argument info to initialize */
-     tree fntype;		/* tree ptr for function decl */
-     rtx libname;		/* SYMBOL_REF of library name or 0 */
-{
-  tree param, next_param;
-
-  cum->floats = cum->ints = 0;
-  cum->init = 0;
-  cum->var = 0;
-  cum->args = 0;
-
-  if (TARGET_DEBUG)
-    {
-      fprintf (stderr, "\nc4x_init_cumulative_args (");
-      if (fntype)
-	{
-	  tree ret_type = TREE_TYPE (fntype);
-
-	  fprintf (stderr, "fntype code = %s, ret code = %s",
-		   tree_code_name[(int) TREE_CODE (fntype)],
-		   tree_code_name[(int) TREE_CODE (ret_type)]);
-	}
-      else
-	fprintf (stderr, "no fntype");
-
-      if (libname)
-	fprintf (stderr, ", libname = %s", XSTR (libname, 0));
-    }
-
-  cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
-
-  for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
-       param; param = next_param)
-    {
-      tree type;
-
-      next_param = TREE_CHAIN (param);
-
-      type = TREE_VALUE (param);
-      if (type && type != void_type_node)
-	{
-	  enum machine_mode mode;
-
-	  /* If the last arg doesn't have void type then we have
-	     variable arguments.  */
-	  if (! next_param)
-	    cum->var = 1;
-
-	  if ((mode = TYPE_MODE (type)))
-	    {
-	      if (! MUST_PASS_IN_STACK (mode, type))
-		{
-		  /* Look for float, double, or long double argument.  */
-		  if (mode == QFmode || mode == HFmode)
-		    cum->floats++;
-		  /* Look for integer, enumeral, boolean, char, or pointer
-		     argument.  */
-		  else if (mode == QImode || mode == Pmode)
-		    cum->ints++;
-		}
-	    }
-	  cum->args++;
-	}
-    }
-
-  if (TARGET_DEBUG)
-    fprintf (stderr, "%s%s, args = %d)\n",
-	     cum->prototype ? ", prototype" : "",
-	     cum->var ? ", variable args" : "",
-	     cum->args);
-}
-
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-void
-c4x_function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;	/* current arg information */
-     enum machine_mode mode;	/* current arg mode */
-     tree type;			/* type of the argument or 0 if lib support */
-     int named;			/* whether or not the argument was named */
-{
-  if (TARGET_DEBUG)
-    fprintf (stderr, "c4x_function_adv(mode=%s, named=%d)\n\n",
-	     GET_MODE_NAME (mode), named);
-  if (! TARGET_MEMPARM 
-      && named
-      && type
-      && ! MUST_PASS_IN_STACK (mode, type))
-    {
-      /* Look for float, double, or long double argument.  */
-      if (mode == QFmode || mode == HFmode)
-	cum->floats++;
-      /* Look for integer, enumeral, boolean, char, or pointer argument.  */
-      else if (mode == QImode || mode == Pmode)
-	cum->ints++;
-    }
-  else if (! TARGET_MEMPARM && ! type)
-    {
-      /* Handle libcall arguments.  */
-      if (mode == QFmode || mode == HFmode)
-	cum->floats++;
-      else if (mode == QImode || mode == Pmode)
-	cum->ints++;
-    }
-  return;
-}
-
-
-/* Define where to put the arguments to a function.  Value is zero to
-   push the argument on the stack, or a hard register in which to
-   store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-   This is null for libcalls where that information may
-   not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-   the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-   (otherwise it is an extra parameter matching an ellipsis).  */
-
-struct rtx_def *
-c4x_function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;	/* current arg information */
-     enum machine_mode mode;	/* current arg mode */
-     tree type;			/* type of the argument or 0 if lib support */
-     int named;			/* != 0 for normal args, == 0 for ... args */
-{
-  int reg = 0;			/* default to passing argument on stack */
-
-  if (! cum->init)
-    {
-      /* We can handle at most 2 floats in R2, R3 */
-      cum->maxfloats = (cum->floats > 2) ? 2 : cum->floats;
-
-      /* We can handle at most 6 integers minus number of floats passed 
-	 in registers.  */
-      cum->maxints = (cum->ints > 6 - cum->maxfloats) ? 
-	6 - cum->maxfloats : cum->ints;
-
-      /* If there is no prototype, assume all the arguments are integers. */
-      if (! cum->prototype)
-	cum->maxints = 6;
-
-      cum->ints = cum->floats = 0;
-      cum->init = 1;
-    }
-
-  if (! TARGET_MEMPARM 
-      && named 
-      && type
-      && ! MUST_PASS_IN_STACK (mode, type))
-    {
-      /* Look for float, double, or long double argument.  */
-      if (mode == QFmode || mode == HFmode)
-	{
-	  if (cum->floats < cum->maxfloats)
-	    reg = c4x_fp_reglist[cum->floats];
-	}
-      /* Look for integer, enumeral, boolean, char, or pointer argument.  */
-      else if (mode == QImode || mode == Pmode)
-	{
-	  if (cum->ints < cum->maxints)
-	    reg = c4x_int_reglist[cum->maxfloats][cum->ints];
-	}
-    }
-  else if (! TARGET_MEMPARM && ! type)
-    {
-      /* We could use a different argument calling model for libcalls,
-         since we're only calling functions in libgcc.  Thus we could
-         pass arguments for long longs in registers rather than on the
-         stack.  In the meantime, use the odd TI format.  We make the
-         assumption that we won't have more than two floating point
-         args, six integer args, and that all the arguments are of the
-         same mode.  */
-      if (mode == QFmode || mode == HFmode)
-	reg = c4x_fp_reglist[cum->floats];
-      else if (mode == QImode || mode == Pmode)
-	reg = c4x_int_reglist[0][cum->ints];
-    }
-
-  if (TARGET_DEBUG)
-    {
-      fprintf (stderr, "c4x_function_arg(mode=%s, named=%d",
-	       GET_MODE_NAME (mode), named);
-      if (reg)
-	fprintf (stderr, ", reg=%s", reg_names[reg]);
-      else
-	fprintf (stderr, ", stack");
-      fprintf (stderr, ")\n");
-    }
-  if (reg)
-    return gen_rtx_REG (mode, reg);
-  else
-    return NULL_RTX;
-}
-
-
-static int
-c4x_isr_reg_used_p (regno)
-     int regno;
-{
-  /* Don't save/restore FP or ST, we handle them separately.  */
-  if (regno == FRAME_POINTER_REGNUM
-      || IS_ST_REG (regno))
-    return 0;
-
-  /* We could be a little smarter abut saving/restoring DP.
-     We'll only save if for the big memory model or if
-     we're paranoid. ;-)  */
-  if (IS_DP_REG (regno))
-    return ! TARGET_SMALL || TARGET_PARANOID;
-
-  /* Only save/restore regs in leaf function that are used.  */
-  if (c4x_leaf_function)
-    return regs_ever_live[regno] && fixed_regs[regno] == 0;
-
-  /* Only save/restore regs that are used by the ISR and regs
-     that are likely to be used by functions the ISR calls
-     if they are not fixed.  */
-  return IS_EXT_REG (regno)
-    || ((regs_ever_live[regno] || call_used_regs[regno]) 
-	&& fixed_regs[regno] == 0);
-}
-
-
-static int
-c4x_leaf_function_p ()
-{
-  /* A leaf function makes no calls, so we only need
-     to save/restore the registers we actually use.
-     For the global variable leaf_function to be set, we need
-     to define LEAF_REGISTERS and all that it entails.
-     Let's check ourselves...   */
-
-  if (lookup_attribute ("leaf_pretend",
-			TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
-    return 1;
-
-  /* Use the leaf_pretend attribute at your own risk.  This is a hack
-     to speed up ISRs that call a function infrequently where the
-     overhead of saving and restoring the additional registers is not
-     warranted.  You must save and restore the additional registers
-     required by the called function.  Caveat emptor.  Here's enough
-     rope...  */
-
-  if (leaf_function_p ())
-    return 1;
-
-  return 0;
-}
-
-
-static int
-c4x_assembler_function_p ()
-{
-  tree type;
-
-  type = TREE_TYPE (current_function_decl);
-  return lookup_attribute ("assembler", TYPE_ATTRIBUTES (type)) != NULL;
-}
-
-
-static int
-c4x_interrupt_function_p ()
-{
-  if (lookup_attribute ("interrupt",
-			TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
-    return 1;
-
-  /* Look for TI style c_intnn  */
-  return current_function_name[0] == 'c'
-    && current_function_name[1] == '_'
-    && current_function_name[2] == 'i'
-    && current_function_name[3] == 'n' 
-    && current_function_name[4] == 't'
-    && isdigit (current_function_name[5])
-    && isdigit (current_function_name[6]);
-}
-
-
-/* Write function prologue.  */
-
-void
-c4x_function_prologue (file, size)
-     FILE *file;
-     int size;
-{
-  int regno;
-
-/* In functions where ar3 is not used but frame pointers are still
-   specified, frame pointers are not adjusted (if >= -O2) and this is
-   used so it won't be needlessly push the frame pointer.  */
-  int dont_push_ar3;
-
-  /* For __assembler__ function don't build a prologue.  */
-  if (c4x_assembler_function_p ())
-    {
-      fprintf (file, "; *** Assembler Function ***\n");
-      return;
-    }
-
-  /* For __interrupt__ function build specific prologue.  */
-  if (c4x_interrupt_function_p ())
-    {
-      c4x_leaf_function = c4x_leaf_function_p ();
-      fprintf (file, "; *** Interrupt Entry %s ***\n",
-	       c4x_leaf_function ? "(leaf)" : "");
-
-      fprintf (file, "\tpush\tst\n");
-      if (size)
-	{
-	  fprintf (file, "\tpush\tar3\n\tldi\tsp,ar3\n");
-	  /* FIXME: Assume ISR doesn't require more than 32767 words
-	     of local variables.  */
-	  if (size > 32767)
-	    error ("ISR %s requires %d words of local variables, "
-		   "maximum is 32767.", current_function_name, size);
-	  fprintf (file, "\taddi\t%d,sp\n", size);
-	}
-      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-	{
-	  if (c4x_isr_reg_used_p (regno))
-	    {
-	      fprintf (file, "\tpush\t%s\n", reg_names[regno]);
-	      if (IS_EXT_REG (regno))	/* save 32MSB of R0--R11 */
-		fprintf (file, "\tpushf\t%s\n", float_reg_names[regno]);
-	    }
-	}
-      /* We need to clear the repeat mode flag if the ISR is
-         going to use a RPTB instruction or uses the RC, RS, or RE
-         registers.  */
-      if (regs_ever_live[RC_REGNO] 
-	  || regs_ever_live[RS_REGNO] 
-	  || regs_ever_live[RE_REGNO])
-	fprintf (file, "\tandn\t0100h,st\n");
-
-      /* Reload DP reg if we are paranoid about some turkey
-         violating small memory model rules.  */
-      if (TARGET_SMALL && TARGET_PARANOID)
-	fprintf (file, TARGET_C3X ?
-		 "\tldp\t@data_sec\n" :
-		 "\tldpk\t@data_sec\n");
-    }
-  else
-    {
-      if (frame_pointer_needed)
-	{
-	  if ((size != 0)
-	      || (current_function_args_size != 0)
-	      || (optimize < 2))
-	    {
-	      fprintf (file, "\tpush\tar3\n");
-	      fprintf (file, "\tldi\tsp,ar3\n");
-	      dont_push_ar3 = 1;
-	    }
-	  else
-	    {
-	      /* Since ar3 is not used, we don't need to push it.  */
-	      dont_push_ar3 = 1;
-	    }
-	}
-      else
-	{
-	  /* If we use ar3, we need to push it.   */
-	  dont_push_ar3 = 0;
-	  if ((size != 0) || (current_function_args_size != 0))
-	    {
-	      /* If we are omitting the frame pointer, we still have
-	         to make space for it so the offsets are correct
-	         unless we don't use anything on the stack at all.  */
-	      size += 1;
-	    }
-	}
-
-      if (size > 32767)
-	{
-	  /* Local vars are too big, it will take multiple operations
-	     to increment SP.  */
-	  if (TARGET_C3X)
-	    {
-	      fprintf (file, "\tldi\t%d,r1\n", size >> 16);
-	      fprintf (file, "\tlsh\t16,r1\n");
-	    }
-	  else
-	    fprintf (file, "\tldhi\t%d,r1\n", size >> 16);
-	  fprintf (file, "\tor\t%d,r1\n", size & 0xffff);
-	  fprintf (file, "\taddi\tr1,sp\n");
-	}
-      else if (size != 0)
-	{
-	  /* Local vars take up less than 32767 words, so we can directly
-	     add the number.  */
-	  fprintf (file, "\taddi\t%d,sp\n", size);
-	}
-
-      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-	{
-	  if (regs_ever_live[regno] && ! call_used_regs[regno])
-	    {
-	      if ((regno == R6_REGNO) || (regno == R7_REGNO))
-		{
-		  /* R6 and R7 are saved as floating point */
-		  if (TARGET_PRESERVE_FLOAT)
-		    fprintf (file, "\tpush\t%s\n", reg_names[regno]);
-		  fprintf (file, "\tpushf\t%s\n", float_reg_names[regno]);
-		}
-	      else if ((! dont_push_ar3) || (regno != AR3_REGNO))
-		{
-		  fprintf (file, "\tpush\t%s\n", reg_names[regno]);
-		}
-	    }
-	}
-    }
-}
-
-
-/* Write function epilogue.  */
-
-void
-c4x_function_epilogue (file, size)
-     FILE *file;
-     int size;
-{
-  int regno;
-  int restore_count = 0;
-  int delayed_jump = 0;
-  int dont_pop_ar3;
-  rtx insn;
-
-  insn = get_last_insn ();
-  if (insn && GET_CODE (insn) == NOTE)
-    insn = prev_nonnote_insn (insn);
-
-  if (insn && GET_CODE (insn) == BARRIER)
-    return;
-
-  /* For __assembler__ function build no epilogue.  */
-  if (c4x_assembler_function_p ())
-    {
-      fprintf (file, "\trets\n");	/* Play it safe */
-      return;
-    }
-
-#ifdef FUNCTION_BLOCK_PROFILER_EXIT
-  if (profile_block_flag == 2)
-    {
-      FUNCTION_BLOCK_PROFILER_EXIT (file);
-    }
-#endif
-
-  /* For __interrupt__ function build specific epilogue.  */
-  if (c4x_interrupt_function_p ())
-    {
-      for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; --regno)
-	{
-	  if (! c4x_isr_reg_used_p (regno))
-	    continue;
-	  if (IS_EXT_REG (regno))
-	    fprintf (file, "\tpopf\t%s\n", float_reg_names[regno]);
-	  fprintf (file, "\tpop\t%s\n", reg_names[regno]);
-	}
-      if (size)
-	{
-	  fprintf (file, "\tsubi\t%d,sp\n", size);
-	  fprintf (file, "\tpop\tar3\n");
-	}
-      fprintf (file, "\tpop\tst\n");
-      fprintf (file, "\treti\n");
-    }
-  else
-    {
-      if (frame_pointer_needed)
-	{
-	  if ((size != 0) 
-	      || (current_function_args_size != 0) 
-	      || (optimize < 2))
-	    {
-	      /* R2 holds the return value.  */
-	      fprintf (file, "\tldi\t*-ar3(1),r2\n");
-
-	      /* We already have the return value and the fp,
-	         so we need to add those to the stack.  */
-	      size += 2;
-	      delayed_jump = 1;
-	      restore_count = 1;
-	      dont_pop_ar3 = 1;
-	    }
-	  else
-	    {
-	      /* Since ar3 is not used for anything, we don't need to
-	         pop it.  */
-	      dont_pop_ar3 = 1;
-	    }
-	}
-      else
-	{
-	  dont_pop_ar3 = 0;	/* If we use ar3, we need to pop it */
-	  if (size || current_function_args_size)
-	    {
-	      /* If we are ommitting the frame pointer, we still have
-	         to make space for it so the offsets are correct
-	         unless we don't use anything on the stack at all.  */
-	      size += 1;
-	    }
-	}
-
-      /* Now get the number of instructions required to restore the
-         registers.  */
-      for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
-	{
-	  if ((regs_ever_live[regno] && ! call_used_regs[regno])
-	      && ((! dont_pop_ar3) || (regno != AR3_REGNO)))
-	    {
-	      restore_count++;
-	      if (TARGET_PRESERVE_FLOAT
-		  && ((regno == R6_REGNO) || (regno == R7_REGNO)))
-	        restore_count++;
-	    }
-	}
-
-      /* Get the number of instructions required to restore the stack.  */
-      if (size > 32767)
-	restore_count += (TARGET_C3X ? 4 : 3);
-      else if (size != 0)
-	restore_count += 1;
-
-      if (delayed_jump && (restore_count < 3))
-	{
-	  /* We don't have enough instructions to account for the delayed
-	     branch, so put some nops in.  */
-
-	  fprintf (file, "\tbud\tr2\n");
-	  while (restore_count < 3)
-	    {
-	      fprintf (file, "\tnop\n");
-	      restore_count++;
-	    }
-	  restore_count = 0;
-	}
-
-      /* Now restore the saved registers, putting in the delayed branch
-         where required.  */
-      for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
-	{
-	  if (regs_ever_live[regno] && ! call_used_regs[regno])
-	    {
-	      if (regno == AR3_REGNO && dont_pop_ar3)
-		continue;
-
-	      if (delayed_jump && (restore_count == 3))
-		fprintf (file, "\tbud\tr2\n");
-
-	      /* R6 and R7 are saved as floating point.  */
-	      if ((regno == R6_REGNO) || (regno == R7_REGNO))
-		{
-		  fprintf (file, "\tpopf\t%s\n", float_reg_names[regno]);
-		  if (TARGET_PRESERVE_FLOAT)
-		    {
-	              restore_count--;
-	              if (delayed_jump && (restore_count == 3))
-		        fprintf (file, "\tbud\tr2\n");
-		      fprintf (file, "\tpop\t%s\n", reg_names[regno]);
-		    }
-		}
-	      else
-		fprintf (file, "\tpop\t%s\n", reg_names[regno]);
-	      restore_count--;
-	    }
-	}
-
-      if (delayed_jump && (restore_count == 3))
-	fprintf (file, "\tbud\tr2\n");
-
-      if (frame_pointer_needed)
-	{
-	  if ((size != 0)
-	      || (current_function_args_size != 0)
-	      || (optimize < 2))
-	    {
-	      /* Restore the old FP.  */
-	      fprintf (file, "\tldi\t*ar3,ar3\n");
-	      restore_count--;
-
-	      if (delayed_jump && (restore_count == 3))
-		fprintf (file, "\tbud\tr2\n");
-	    }
-	}
-
-      if (size > 32767)
-	{
-	  /* Local vars are too big, it will take multiple operations
-	     to decrement SP.  */
-	  if (TARGET_C3X)
-	    {
-	      fprintf (file, "\tldi\t%d,r3\n", size >> 16);
-	      if (delayed_jump)
-		fprintf (file, "\tbud\tr2\n");
-	      fprintf (file, "\tlsh\t16,r3\n");
-	    }
-	  else
-	    fprintf (file, "\tldhi\t%d,r3\n", size >> 16);
-	  fprintf (file, "\tor\t%d,r3\n", size & 0xffff);
-	  fprintf (file, "\tsubi\tr3,sp\n");
-	}
-      else if (size != 0)
-	{
-	  /* Local vars take up less than 32768 words, so we can directly
-	     subtract the number.  */
-	  fprintf (file, "\tsubi\t%d,sp\n", size);
-	}
-
-      if (! delayed_jump)
-	fprintf (file, "\trets\n");
-    }
-}
-
-int
-c4x_null_epilogue_p ()
-{
-  int regno;
-
-  if (reload_completed
-      && ! c4x_assembler_function_p ()
-      && ! c4x_interrupt_function_p ()
-      && ! current_function_calls_alloca
-      && ! current_function_args_size
-      && ! (profile_block_flag == 2)
-      && ! (optimize < 2)
-      && ! get_frame_size ())
-    {
-      for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
-	if (regs_ever_live[regno] && ! call_used_regs[regno]
-	    && (regno != AR3_REGNO))
-	  return 0;
-      return 1;
-    }
-  return 0;
-}
-
-
-void
-c4x_emit_libcall (name, code, dmode, smode, noperands, operands)
-     char *name;
-     enum rtx_code code;
-     enum machine_mode dmode;
-     enum machine_mode smode;
-     int noperands;
-     rtx *operands;
-{
-  rtx ret;
-  rtx insns;
-  rtx libcall;
-  rtx equiv;
-
-  start_sequence ();
-  libcall = gen_rtx_SYMBOL_REF (Pmode, name);
-  switch (noperands)
-    {
-    case 2:
-      ret = emit_library_call_value (libcall, NULL_RTX, 1, dmode, 1,
-				     operands[1], smode);
-      equiv = gen_rtx (code, dmode, operands[1]);
-      break;
-
-    case 3:
-      ret = emit_library_call_value (libcall, NULL_RTX, 1, dmode, 2,
-				     operands[1], smode, operands[2], smode);
-      equiv = gen_rtx (code, dmode, operands[1], operands[2]);
-      break;
-
-    default:
-      fatal ("c4x_emit_libcall: Bad number of operands");
-    }
-
-  insns = get_insns ();
-  end_sequence ();
-  emit_libcall_block (insns, operands[0], ret, equiv);
-}
-
-
-void
-c4x_emit_libcall3 (name, code, mode, operands)
-     const char *name;
-     enum rtx_code code;
-     enum machine_mode mode;
-     rtx *operands;
-{
-  return c4x_emit_libcall (name, code, mode, mode, 3, operands);
-}
-
-void
-c4x_emit_libcall_mulhi (name, code, mode, operands)
-     char *name;
-     enum rtx_code code;
-     enum machine_mode mode;
-     rtx *operands;
-{
-  rtx ret;
-  rtx insns;
-  rtx libcall;
-  rtx equiv;
-
-  start_sequence ();
-  libcall = gen_rtx_SYMBOL_REF (Pmode, name);
-  ret = emit_library_call_value (libcall, NULL_RTX, 1, mode, 2,
-                                 operands[1], mode, operands[2], mode);
-  equiv = gen_rtx_TRUNCATE (mode,
-                   gen_rtx_LSHIFTRT (HImode,
-                            gen_rtx_MULT (HImode,
-                                     gen_rtx (code, HImode, operands[1]),
-                                     gen_rtx (code, HImode, operands[2])),
-                                     GEN_INT (32)));
-  insns = get_insns ();
-  end_sequence ();
-  emit_libcall_block (insns, operands[0], ret, equiv);
-}
-
-
-enum reg_class
-c4x_preferred_reload_class (x, class)
-     rtx x;
-     enum reg_class class;
-{
-  return class;
-}
-
-
-enum reg_class
-c4x_limit_reload_class (mode, class)
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     enum reg_class class;
-{
-  return class;
-}
-
-
-enum reg_class
-c4x_secondary_memory_needed (class1, class2, mode)
-     enum reg_class class1 ATTRIBUTE_UNUSED;
-     enum reg_class class2 ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return 0;
-}
-
-
-int
-c4x_check_legit_addr (mode, addr, strict)
-     enum machine_mode mode;
-     rtx addr;
-     int strict;
-{
-  rtx base = NULL_RTX;		/* Base register (AR0-AR7) */
-  rtx indx = NULL_RTX;		/* Index register (IR0,IR1) */
-  rtx disp = NULL_RTX;		/* Displacement */
-  enum rtx_code code;
-
-  code = GET_CODE (addr);
-  switch (code)
-    {
-      /* Register indirect with auto increment/decrement.  We don't
-	 allow SP here---push_operand should recognise an operand
-	 being pushed on the stack.  */
-
-    case PRE_DEC:
-    case POST_DEC:
-      if (mode != QImode && mode != QFmode)
-	return 0;
-    case PRE_INC:
-    case POST_INC:
-      base = XEXP (addr, 0);
-      if (! REG_P (base))
-	return 0;
-      break;
-
-    case PRE_MODIFY:
-    case POST_MODIFY:
-      {
-	rtx op0 = XEXP (addr, 0);
-	rtx op1 = XEXP (addr, 1);
-
-	if (mode != QImode && mode != QFmode)
-	  return 0;
-
-	if (! REG_P (op0) 
-	    || (GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS))
-	  return 0;
-	base = XEXP (op1, 0);
-	if (base != op0)
-	  return 0;
-	if (REG_P (XEXP (op1, 1)))
-	  indx = XEXP (op1, 1);
-	else
-	  disp = XEXP (op1, 1);
-      }
-      break;
-	
-      /* Register indirect.  */
-    case REG:
-      base = addr;
-      break;
-
-      /* Register indirect with displacement or index.  */
-    case PLUS:
-      {
-	rtx op0 = XEXP (addr, 0);
-	rtx op1 = XEXP (addr, 1);
-	enum rtx_code code0 = GET_CODE (op0);
-
-	switch (code0)
-	  {
-	  case USE:
-	    /* The uses are put in to avoid problems
-	       with referenced things disappearing.  */
-	    return c4x_check_legit_addr (mode, op1, strict);
-
-	  case PLUS:
-	    /* This is another reference to keep things
-	       from disappearing, but it contains a plus
-	       of a use and DP.  */
-	    if (GET_CODE (XEXP (op0, 0)) == USE)
-	      return c4x_check_legit_addr (mode, op1, strict);
-	    return 0;
-
-	  case REG:
-	    if (REG_P (op1))
-	      {
-		base = op0;	/* base + index */
-		indx = op1;
-		if (IS_INDEX_REGNO (base) || IS_ADDR_REGNO (indx))
-		  {
-		    base = op1;
-		    indx = op0;
-		  }
-	      }
-	    else
-	      {
-		base = op0;	/* base + displacement */
-		disp = op1;
-	      }
-	    break;
-
-	  default:
-	    return 0;
-	  }
-      }
-      break;
-
-      /* Direct addressing with some work for the assembler...  */
-    case CONST:
-      if (GET_CODE (XEXP (addr, 0)) == PLUS
-	  && (GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
-	      || GET_CODE (XEXP (XEXP (addr, 0), 0)) == LABEL_REF)
-	  && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
-	return 1;
-
-      /* Direct addressing.  */
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return 1;
-
-      /* Do not allow direct memory access to absolute addresses.
-         This is more pain than its worth, especially for the
-         small memory model where we can't guarantee that
-         this address is within the data page---we don't want
-         to modify the DP register in the small memory model,
-         even temporarily, since an interrupt can sneak in....  */
-    case CONST_INT:
-      return 0;
-
-      /* Indirect indirect addressing.  */
-    case MEM:
-      return 0;
-
-    case CONST_DOUBLE:
-      fatal_insn ("Using CONST_DOUBLE for address", addr);
-
-    default:
-      return 0;
-    }
-
-  /* Validate the base register.  */
-  if (base)
-    {
-      /* Check that the address is offsettable for HImode and HFmode.  */
-      if (indx && (mode == HImode || mode == HFmode))
-	return 0;
-
-      /* Handle DP based stuff.  */
-      if (REGNO (base) == DP_REGNO)
-	return 1;
-      if (strict && ! REGNO_OK_FOR_BASE_P (REGNO (base)))
-	return 0;
-      else if (! strict && ! IS_ADDR_OR_PSEUDO_REGNO (base))
-	return 0;
-    }
-
-  /* Now validate the index register.  */
-  if (indx)
-    {
-      if (GET_CODE (indx) != REG)
-	return 0;
-      if (strict && ! REGNO_OK_FOR_INDEX_P (REGNO (indx)))
-	return 0;
-      else if (! strict && ! IS_INDEX_OR_PSEUDO_REGNO (indx))
-	return 0;
-    }
-
-  /* Validate displacement.  */
-  if (disp)
-    {
-      if (GET_CODE (disp) != CONST_INT)
-	return 0;
-      if (mode == HImode || mode == HFmode)
-	{
-	  /* The offset displacement must be legitimate.  */
-	  if (! IS_DISP8_OFF_CONST (INTVAL (disp)))
-	    return 0;
-	}
-      else
-	{
-	  if (! IS_DISP8_CONST (INTVAL (disp)))
-	    return 0;
-	}
-      /* Can't add an index with a disp.  */
-      if (indx)
-	return 0;		
-    }
-  return 1;
-}
-
-
-rtx
-c4x_legitimize_address (orig, mode)
-     rtx orig ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return NULL_RTX;
-}
-
-
-/* Provide the costs of an addressing mode that contains ADDR.
-   If ADDR is not a valid address, its cost is irrelevant.  
-   This is used in cse and loop optimisation to determine
-   if it is worthwhile storing a common address into a register. 
-   Unfortunately, the C4x address cost depends on other operands.  */
-
-int 
-c4x_address_cost (addr)
-rtx addr;
-{
-  switch (GET_CODE (addr))
-    {
-    case REG:
-      return 1;
-
-    case CONST:
-      {
-	rtx offset = const0_rtx;
-	addr = eliminate_constant_term (addr, &offset);
-	
-	if (GET_CODE (addr) == LABEL_REF)
-	  return 3;
-	
-	if (GET_CODE (addr) != SYMBOL_REF)
-	  return 4;
-
-	if (INTVAL (offset) == 0)
-	  return 3;
-      }
-      
-      /* fall through */
-      
-    case POST_INC:
-    case POST_DEC:
-    case PRE_INC:
-    case PRE_DEC:
-      return 1;
-      
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return TARGET_SMALL ? 3 : 4;
-      
-    case PLUS:
-      {
-	register rtx op0 = XEXP (addr, 0);
-	register rtx op1 = XEXP (addr, 1);
-	
-	if (GET_CODE (op0) != REG)
-	  break;
-	
-	switch (GET_CODE (op1))
-	  {
-	  default:
-	    break;
-
-	  case REG:
-	    return 2;
-
-	  case CONST_INT:
-	    if (IS_DISP1_CONST (INTVAL (op1)))
-	      return 1;
-
-	    if (! TARGET_C3X && IS_UINT5_CONST (INTVAL (op1)))
-	      return 2;
-
-	    return 3;
-	  }
-      }
-    default:
-    }
-  
-  return 4;
-}
-
-
-rtx
-c4x_gen_compare_reg (code, x, y)
-     enum rtx_code code;
-     rtx x, y;
-{
-  enum machine_mode mode = SELECT_CC_MODE (code, x, y);
-  rtx cc_reg;
-
-  if (mode == CC_NOOVmode
-      && (code == LE || code == GE || code == LT || code == GT))
-    return NULL_RTX;
-
-  cc_reg = gen_rtx_REG (mode, ST_REGNO);
-  emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
-			  gen_rtx_COMPARE (mode, x, y)));
-  return cc_reg;
-}
-
-char *
-c4x_output_cbranch (form, seq)
-     char *form;
-     rtx seq;
-{
-  int delayed = 0;
-  int annultrue = 0;
-  int annulfalse = 0;
-  rtx delay;
-  char *cp;
-  static char str[100];
-  
-  if (final_sequence)
-    {
-      delay = XVECEXP (final_sequence, 0, 1);
-      delayed = ! INSN_ANNULLED_BRANCH_P (seq);
-      annultrue = INSN_ANNULLED_BRANCH_P (seq) && ! INSN_FROM_TARGET_P (delay);
-      annulfalse = INSN_ANNULLED_BRANCH_P (seq) && INSN_FROM_TARGET_P (delay);
-    }
-  strcpy (str, form);
-  cp = &str [strlen (str)];
-  if (delayed)
-    {
-      *cp++ = '%';
-      *cp++ = '#';
-    }
-  if (annultrue)
-    {
-      *cp++ = 'a';
-      *cp++ = 't';
-    }
-  if (annulfalse)
-    {
-      *cp++ = 'a'; 
-      *cp++ = 'f';
-    }
-  *cp++ = '\t';
-  *cp++ = '%'; 
-  *cp++ = 'l';
-  *cp++ = '1';
-  *cp = 0;
-  return str;
-}
-
-void
-c4x_print_operand (file, op, letter)
-     FILE *file;		/* file to write to */
-     rtx op;			/* operand to print */
-     int letter;		/* %<letter> or 0 */
-{
-  rtx op1;
-  enum rtx_code code;
-
-  switch (letter)
-    {
-    case '#':			/* delayed */
-      if (final_sequence)
-	asm_fprintf (file, "d");
-      return;
-    }
-
-  code = GET_CODE (op);
-  switch (letter)
-    {
-    case 'A':			/* direct address */
-      if (code == CONST_INT || code == SYMBOL_REF)
-	asm_fprintf (file, "@");
-      break;
-
-    case 'C':			/* call */
-      if (code != MEM)
-	fatal_insn ("c4x_print_operand: %%C inconsistency", op);
-      op1 = XEXP (op, 0);
-      SYMBOL_REF_FLAG (op1) = 1;
-      output_addr_const (file, op1);
-      return;
-
-    case 'H':			/* sethi */
-      if (code == SYMBOL_REF)
-	SYMBOL_REF_FLAG (op) = 1;
-      break;
-
-    case 'I':			/* reversed condition */
-      code = reverse_condition (code);
-      break;
-
-    case 'L':			/* log 2 of constant */
-      if (code != CONST_INT)
-	fatal_insn ("c4x_print_operand: %%L inconsistency", op);
-      fprintf (file, "%d", exact_log2 (INTVAL (op)));
-      return;
-
-    case 'N':			/* ones complement of small constant */
-      if (code != CONST_INT)
-	fatal_insn ("c4x_print_operand: %%N inconsistency", op);
-      fprintf (file, "%d", ~INTVAL (op));
-      return;
-
-    case 'K':			/* generate ldp(k) if direct address */
-      if (! TARGET_SMALL
-	  && code == MEM
-	  && GET_CODE (XEXP (op, 0)) == PLUS
-	  && GET_CODE(XEXP (XEXP (op, 0), 0)) == REG
-	  && REGNO(XEXP (XEXP (op, 0), 0)) == DP_REGNO)
-	{
-	  op1 = XEXP (XEXP (op, 0), 1);
-          if (GET_CODE(op1) == CONST_INT || GET_CODE(op1) == SYMBOL_REF)
-	    {
-	      asm_fprintf (file, "\t%s\t", TARGET_C3X ? "ldp" : "ldpk");
-	      output_address (XEXP (adj_offsettable_operand (op, 1), 0));
-	      asm_fprintf (file, "\n");
-	    }
-	}
-      return;
-
-    case 'M':			/* generate ldp(k) if direct address */
-      if (! TARGET_SMALL		/* only used in asm statements */
-	  && code == MEM
-	  && (GET_CODE (XEXP (op, 0)) == CONST
-	      || GET_CODE (XEXP (op, 0)) == SYMBOL_REF))
-	{
-	  asm_fprintf (file, "%s\t", TARGET_C3X ? "ldp" : "ldpk");
-          output_address (XEXP (op, 0));
-	  asm_fprintf (file, "\n\t");
-	}
-      return;
-
-    case 'O':			/* offset address */
-      if (code == MEM && c4x_autoinc_operand (op, Pmode))
-	break;
-      else if (code == MEM)
-	output_address (XEXP (adj_offsettable_operand (op, 1), 0));
-      else if (code == REG)
-	fprintf (file, "%s", reg_names[REGNO (op) + 1]);
-      else
-	fatal_insn ("c4x_print_operand: %%O inconsistency", op);
-      return;
-
-    case 'R':			/* call register */
-      op1 = XEXP (op, 0);
-      if (code != MEM || GET_CODE (op1) != REG)
-	fatal_insn ("c4x_print_operand: %%R inconsistency", op);
-      else
-	fprintf (file, "%s", reg_names[REGNO (op1)]);
-      return;
-
-    default:
-      break;
-    }
-  
-  switch (code)
-    {
-    case REG:
-      if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
-	fprintf (file, "%s", float_reg_names[REGNO (op)]);
-      else
-	fprintf (file, "%s", reg_names[REGNO (op)]);
-      break;
-      
-    case MEM:
-      output_address (XEXP (op, 0));
-      break;
-      
-    case CONST_DOUBLE:
-      {
-	char str[30];
-	REAL_VALUE_TYPE r;
-	
-	REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-	REAL_VALUE_TO_DECIMAL (r, "%20f", str);
-	fprintf (file, "%s", str);
-      }
-      break;
-      
-    case CONST_INT:
-      fprintf (file, "%d", INTVAL (op));
-      break;
-      
-    case NE:
-      asm_fprintf (file, "ne");
-      break;
-      
-    case EQ:
-      asm_fprintf (file, "eq");
-      break;
-      
-    case GE:
-      asm_fprintf (file, "ge");
-      break;
-
-    case GT:
-      asm_fprintf (file, "gt");
-      break;
-
-    case LE:
-      asm_fprintf (file, "le");
-      break;
-
-    case LT:
-      asm_fprintf (file, "lt");
-      break;
-
-    case GEU:
-      asm_fprintf (file, "hs");
-      break;
-
-    case GTU:
-      asm_fprintf (file, "hi");
-      break;
-
-    case LEU:
-      asm_fprintf (file, "ls");
-      break;
-
-    case LTU:
-      asm_fprintf (file, "lo");
-      break;
-
-    case SYMBOL_REF:
-      output_addr_const (file, op);
-      break;
-
-    case CONST:
-      output_addr_const (file, XEXP (op, 0));
-      break;
-
-    case CODE_LABEL:
-      break;
-
-    default:
-      fatal_insn ("c4x_print_operand: Bad operand case", op);
-      break;
-    }
-}
-
-
-void
-c4x_print_operand_address (file, addr)
-     FILE *file;
-     rtx addr;
-{
-  switch (GET_CODE (addr))
-    {
-    case REG:
-      fprintf (file, "*%s", reg_names[REGNO (addr)]);
-      break;
-
-    case PRE_DEC:
-      fprintf (file, "*--%s", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case POST_INC:
-      fprintf (file, "*%s++", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case POST_MODIFY:
-      {
-	rtx op0 = XEXP (XEXP (addr, 1), 0);
-	rtx op1 = XEXP (XEXP (addr, 1), 1);
-	
-	if (GET_CODE (XEXP (addr, 1)) == PLUS && REG_P (op1))
-	  fprintf (file, "*%s++(%s)", reg_names[REGNO (op0)],
-		   reg_names[REGNO (op1)]);
-	else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) > 0)
-	  fprintf (file, "*%s++(%d)", reg_names[REGNO (op0)],
-		   INTVAL (op1));
-	else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) < 0)
-	  fprintf (file, "*%s--(%d)", reg_names[REGNO (op0)],
-		   -INTVAL (op1));
-	else if (GET_CODE (XEXP (addr, 1)) == MINUS && REG_P (op1))
-	  fprintf (file, "*%s--(%s)", reg_names[REGNO (op0)],
-		   reg_names[REGNO (op1)]);
-	else
-	  fatal_insn ("c4x_print_operand_address: Bad post_modify", addr);
-      }
-      break;
-      
-    case PRE_MODIFY:
-      {
-	rtx op0 = XEXP (XEXP (addr, 1), 0);
-	rtx op1 = XEXP (XEXP (addr, 1), 1);
-	
-	if (GET_CODE (XEXP (addr, 1)) == PLUS && REG_P (op1))
-	  fprintf (file, "*++%s(%s)", reg_names[REGNO (op0)],
-		   reg_names[REGNO (op1)]);
-	else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) > 0)
-	  fprintf (file, "*++%s(%d)", reg_names[REGNO (op0)],
-		   INTVAL (op1));
-	else if (GET_CODE (XEXP (addr, 1)) == PLUS && INTVAL (op1) < 0)
-	  fprintf (file, "*--%s(%d)", reg_names[REGNO (op0)],
-		   -INTVAL (op1));
-	else if (GET_CODE (XEXP (addr, 1)) == MINUS && REG_P (op1))
-	  fprintf (file, "*--%s(%s)", reg_names[REGNO (op0)],
-		   reg_names[REGNO (op1)]);
-	else
-	  fatal_insn ("c4x_print_operand_address: Bad pre_modify", addr);
-      }
-      break;
-      
-    case PRE_INC:
-      fprintf (file, "*++%s", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case POST_DEC:
-      fprintf (file, "*%s--", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case PLUS:			/* Indirect with displacement.  */
-      {
-	rtx op0 = XEXP (addr, 0);
-	rtx op1 = XEXP (addr, 1);
-	enum rtx_code code0 = GET_CODE (op0);
-
-	if (code0 == USE || code0 == PLUS)
-	  {
-	    asm_fprintf (file, "@");
-	    output_addr_const (file, op1);
-	  }
-	else if (REG_P (op0))
-	  {
-	    if (REGNO (op0) == DP_REGNO)
-	      {
-		c4x_print_operand_address (file, op1);
-	      }
-	    else if (REG_P (op1))
-	      {
-		if (IS_INDEX_REGNO (op0))
-		  {
-		    fprintf (file, "*+%s(%s)",
-			     reg_names[REGNO (op1)],
-			     reg_names[REGNO (op0)]);	/* index + base */
-		  }
-		else
-		  {
-		    fprintf (file, "*+%s(%s)",
-			     reg_names[REGNO (op0)],
-			     reg_names[REGNO (op1)]);	/* base + index */
-		  }
-	      }
-	    else if (INTVAL (op1) < 0)
-	      {
-		fprintf (file, "*-%s(%d)",
-			 reg_names[REGNO (op0)],
-			 -INTVAL (op1));	/* base - displacement */
-	      }
-	    else
-	      {
-		fprintf (file, "*+%s(%d)",
-			 reg_names[REGNO (op0)],
-			 INTVAL (op1));		/* base + displacement */
-	      }
-	  }
-      }
-      break;
-
-    case CONST:
-    case SYMBOL_REF:
-    case LABEL_REF:
-      if (! SYMBOL_REF_FLAG (addr))
-	fprintf (file, "@");
-      output_addr_const (file, addr);
-      SYMBOL_REF_FLAG (addr) = 0;
-      break;
-
-      /* We shouldn't access CONST_INT addresses.  */
-    case CONST_INT:
-
-    default:
-      fatal_insn ("c4x_print_operand_address: Bad operand case", addr);
-      break;
-    }
-}
-
-
-static int
-c4x_immed_float_p (operand)
-     rtx operand;
-{
-  long convval[2];
-  int exponent;
-  REAL_VALUE_TYPE r;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
-  if (GET_MODE (operand) == HFmode)
-    REAL_VALUE_TO_TARGET_DOUBLE (r, convval);
-  else
-    {
-      REAL_VALUE_TO_TARGET_SINGLE (r, convval[0]);
-      convval[1] = 0;
-    }
-
-  /* sign extend exponent */
-  exponent = (((convval[0] >> 24) & 0xff) ^ 0x80) - 0x80;
-  if (exponent == -128)
-    return 1;			/* 0.0 */
-  if ((convval[0] & 0x00000fff) != 0 || convval[1] != 0)
-    return 0;			/* Precision doesn't fit */
-  return (exponent <= 7)	/* Positive exp */
-    && (exponent >= -7);	/* Negative exp */
-}
-
-
-/* This function checks for an insn operand that requires direct
-   addressing and inserts a load of the DP register prior to the
-   insn if the big memory model is being compiled for.  Immediate
-   operands that do not fit within the opcode field get changed
-   into memory references using direct addressing.  At this point
-   all pseudos have been converted to hard registers.  */
-
-int
-c4x_scan_for_ldp (newop, insn, operand0)
-     rtx *newop;
-     rtx insn;
-     rtx operand0;
-{
-  int i;
-  char *format_ptr;
-  rtx op0, op1, op2, addr;
-  rtx operand = *newop;
-
-  switch (GET_CODE (operand))
-    {
-    case MEM:
-      op0 = XEXP (operand, 0);
-
-      /* We have something we need to emit a load dp insn for.
-         The first operand should hold the rtx for the instruction
-         required.  */
-
-      switch (GET_CODE (op0))
-	{
-	case CONST_INT:
-	  fatal_insn ("c4x_scan_for_ldp: Direct memory access to const_int",
-		     op0);
-	  break;
-
-	case CONST:
-	case SYMBOL_REF:
-	  if (! TARGET_C3X && ! TARGET_SMALL
-	      && recog_memoized (insn) == CODE_FOR_movqi_noclobber
-	      && ((addr = find_reg_note (insn, REG_EQUAL, NULL_RTX))
-		  || (addr = find_reg_note (insn, REG_EQUIV, NULL_RTX)))
-	      && (IS_STD_OR_PSEUDO_REGNO (operand0)))
-	    {
-	      addr = XEXP (addr, 0);
-	      if (GET_CODE (addr) == CONST_INT)
-		{
-		  op1 = GEN_INT (INTVAL (addr) & ~0xffff);
-		  emit_insn_before (gen_movqi (operand0, op1), insn);
-		  op1 = GEN_INT (INTVAL (addr) & 0xffff);
-		  emit_insn_before (gen_iorqi3_noclobber (operand0,
-						      operand0, op1), insn);
-		  delete_insn (insn);
-		  return 1;
-		}
-	      else if (GET_CODE (addr) == SYMBOL_REF)
-		{
-		  emit_insn_before (gen_set_high_use (operand0, addr, addr),
-				    insn);
-		  emit_insn_before (gen_set_ior_lo_use (operand0, addr, addr),
-				    insn);
-		  delete_insn (insn);
-		  return 1;
-		}
-	      else if (GET_CODE (addr) == CONST
-		       && GET_CODE (op1 = XEXP (addr, 0)) == PLUS
-		       && GET_CODE (op2 = XEXP (op1, 0)) == SYMBOL_REF
-		       && GET_CODE (XEXP (op1, 1)) == CONST_INT)
-		{
-		  emit_insn_before (gen_set_high_use (operand0, addr, op2),
-				    insn);
-		  emit_insn_before (gen_set_ior_lo_use (operand0, addr, op2),
-				    insn);
-		  delete_insn (insn);
-		  return 1;
-		}
-	    }
-	  if (! TARGET_SMALL)
-	    emit_insn_before (gen_set_ldp (gen_rtx_REG (Pmode, DP_REGNO),
-					   operand), insn);
-
-	  /* Replace old memory reference with direct reference.  */
-	  *newop = gen_rtx_MEM (GET_MODE (operand),
-				gen_rtx_PLUS (Pmode,
-					      gen_rtx_REG (Pmode, DP_REGNO),
-					      op0));
-
-	  /* Use change_address?  */
-	  RTX_UNCHANGING_P (*newop) = RTX_UNCHANGING_P (operand);
-	  MEM_COPY_ATTRIBUTES (*newop, operand);
-	  break;
-
-	default:
-	  break;
-	}
-
-      return 0;
-
-    case CONST_INT:
-      if (SMALL_CONST (INTVAL (operand), insn))
-	break;
-      fatal_insn ("Immediate integer too large", insn);
-
-    case CONST_DOUBLE:
-      if (c4x_immed_float_p (operand))
-	break;
-
-      /* We'll come here if a CONST_DOUBLE integer has slipped
-         though the net...  */
-      fatal_insn ("Immediate CONST_DOUBLE integer too large", insn);
-
-    case CONST:
-      fatal_insn ("Immediate integer not known", insn);
-
-      /* Symbol and label immediate addresses cannot be stored
-         within a C[34]x instruction, so we store them in memory
-         and use direct addressing instead.  */
-    case LABEL_REF:
-    case SYMBOL_REF:
-      if (GET_CODE (operand0) != REG)
-	break;
-
-      op0 = XEXP (force_const_mem (Pmode, operand), 0);
-      *newop = gen_rtx_MEM (GET_MODE (operand),
-			    gen_rtx_PLUS (Pmode,
-					  gen_rtx_PLUS (Pmode,
-					      gen_rtx_USE (VOIDmode, operand),
-					      gen_rtx_REG (Pmode, DP_REGNO)),
-					  op0));
-      
-      if (! TARGET_SMALL)
-	emit_insn_before (gen_set_ldp_use (gen_rtx_REG (Pmode, DP_REGNO),
-					   *newop, operand), insn);
-      return 0;
-
-    default:
-      break;
-    }
-
-  format_ptr = GET_RTX_FORMAT (GET_CODE (operand));
-
-  /* Recursively hunt for required loads of DP.  */
-  for (i = 0; i < GET_RTX_LENGTH (GET_CODE (operand)); i++)
-    {
-      if (*format_ptr++ == 'e')	/* rtx expression */
-	if (c4x_scan_for_ldp (&XEXP (operand, i), insn, operand0))
-	  break;
-    }
-  return 0;
-}
-
-
-/* The last instruction in a repeat block cannot be a Bcond, DBcound,
-   CALL, CALLCond, TRAPcond, RETIcond, RETScond, IDLE, RPTB or RPTS.
-
-   None of the last four instructions from the bottom of the block can
-   be a BcondD, BRD, DBcondD, RPTBD, LAJ, LAJcond, LATcond, BcondAF,
-   BcondAT or RETIcondD.
-
-   This routine scans the four previous insns for a jump insn, and if
-   one is found, returns 1 so that we bung in a nop instruction.
-   This simple minded strategy will add a nop, when it may not
-   be required.  Say when there is a JUMP_INSN near the end of the
-   block that doesn't get converted into a delayed branch.
-
-   Note that we cannot have a call insn, since we don't generate
-   repeat loops with calls in them (although I suppose we could, but
-   there's no benefit.)  
-
-   !!! FIXME.  The rptb_top insn may be sucked into a SEQUENCE.  */
-
-int
-c4x_rptb_nop_p (insn)
-     rtx insn;
-{
-  rtx start_label;
-  int i;
-
-  /* Extract the start label from the jump pattern (rptb_end).  */
-  start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 1), 0);
-
-  /* If there is a label at the end of the loop we must insert
-     a NOP.  */
-  insn = prev_nonnote_insn (insn);
-  if (GET_CODE (insn) == CODE_LABEL)
-    return 1;
-
-  for (i = 0; i < 4; i++)
-    {
-      /* Search back for prev non-note and non-label insn.  */
-      while (GET_CODE (insn) == NOTE || GET_CODE (insn) == CODE_LABEL
-	     || GET_CODE (insn) == USE || GET_CODE (insn) == CLOBBER)
-	{
-	  if (insn == start_label)
-	    return i == 0;
-
-	  insn = PREV_INSN (insn);
-	};
-
-      /* If we have a jump instruction we should insert a NOP. If we
-	 hit repeat block top we should only insert a NOP if the loop
-	 is empty. */
-      if (GET_CODE (insn) == JUMP_INSN)
-	return 1;
-      insn = PREV_INSN (insn);
-    }
-  return 0;
-}
-
-
-void
-c4x_rptb_insert (insn)
-     rtx insn;
-{
-  rtx end_label;
-  rtx start_label;
-  rtx count_reg;
-
-  /* If the count register has not been allocated to RC, say if
-     there is a movstr pattern in the loop, then do not insert a
-     RPTB instruction.  Instead we emit a decrement and branch
-     at the end of the loop.  */
-  count_reg = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 0), 0);
-  if (REGNO (count_reg) != RC_REGNO)
-    return;
-
-  /* Extract the start label from the jump pattern (rptb_end).  */
-  start_label = XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 1), 0);
-  
-  /* We'll have to update the basic blocks.  */
-  end_label = gen_label_rtx ();
-  emit_label_after (end_label, insn);
-
-  for (; insn; insn = PREV_INSN (insn))
-    if (insn == start_label)
-      break;
-  if (! insn)
-    fatal_insn ("c4x_rptb_insert: Cannot find start label", start_label);
-
-  /* We'll have to update the basic blocks.  */
-  emit_insn_before (gen_rptb_top (start_label, end_label), insn);
-}
-
-/* This function is a C4x special. It scans through all the insn
-   operands looking for places where the DP register needs to be
-   reloaded and for large immediate operands that need to be converted
-   to memory references.  The latter should be avoidable with proper
-   definition of patterns in machine description.  We come here right
-   near the end of things, immediately before delayed branch
-   scheduling.  */
-
-void
-c4x_process_after_reload (first)
-     rtx first;
-{
-  rtx insn;
-  int i;
-
-  for (insn = first; insn; insn = NEXT_INSN (insn))
-    {
-      /* Look for insn.  */
-      if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
-	{
-	  int insn_code_number;
-
-	  insn_code_number = recog_memoized (insn);
-
-	  if (insn_code_number < 0)
-	    continue;
-
-	  /* Insert the RTX for RPTB at the top of the loop
-	     and a label at the end of the loop. */
-	  if (insn_code_number == CODE_FOR_rptb_end)
-	    c4x_rptb_insert(insn);
-
-	  /* We split all insns here if they have a # for the output
-	     template if we are using the big memory model since there
-	     is a chance that we might be accessing memory across a
-	     page boundary.  */
-
-	  if (! TARGET_SMALL)
-	    {
-	      char *template;
-
-	      template = insn_template[insn_code_number];
-	      if (template && template[0] == '#' && template[1] == '\0')
-		{
-		  rtx new = try_split (PATTERN(insn), insn, 0);
-		  
-		  /* If we didn't split the insn, go away.  */
-		  if (new == insn && PATTERN (new) == PATTERN(insn))
-		    fatal_insn ("Couldn't split pattern", insn);
-
-		  PUT_CODE (insn, NOTE);
-		  NOTE_SOURCE_FILE (insn) = 0;
-		  NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
-
-		  /* Do we have to update the basic block info here? 
-		     Maybe reorg wants it sorted out... */
-
-		  /* Continue with the first of the new insns generated
-                     by the split. */
-		  insn = new;
-
-		  insn_code_number = recog_memoized (insn);
-		  
-		  if (insn_code_number < 0)
-		    continue;
-		}
-	    }
-
-	  /* Ignore jumps and calls.  */
-	  if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
-	      continue;	
-
-	  insn_extract (insn);
-	  for (i = 0; i < insn_n_operands[insn_code_number]; i++)
-	    if (c4x_scan_for_ldp (recog_operand_loc[i], insn, 
-				  recog_operand[0]))
-	      break;
-	}
-    }
-}
-
-
-static int
-c4x_a_register (op)
-     rtx op;
-{
-  return REG_P (op) && IS_ADDR_OR_PSEUDO_REGNO (op);
-}
-
-
-static int
-c4x_x_register (op)
-     rtx op;
-{
-  return REG_P (op) && IS_INDEX_OR_PSEUDO_REGNO (op);
-}
-
-
-static int
-c4x_int_constant (op)
-     rtx op;
-{
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  return GET_MODE (op) == VOIDmode
-    || GET_MODE_CLASS (op) == MODE_INT
-    || GET_MODE_CLASS (op) == MODE_PARTIAL_INT;
-}
-
-
-static int
-c4x_float_constant (op)
-     rtx op;
-{
-  if (GET_CODE (op) != CONST_DOUBLE)
-    return 0;
-  return GET_MODE (op) == QFmode || GET_MODE (op) == HFmode;
-}
-
-
-int
-c4x_H_constant (op)
-     rtx op;
-{
-  return c4x_float_constant (op) && c4x_immed_float_p (op);
-}
-
-
-int
-c4x_I_constant (op)
-     rtx op;
-{
-  return c4x_int_constant (op) && IS_INT16_CONST (INTVAL (op));
-}
-
-
-int
-c4x_J_constant (op)
-     rtx op;
-{
-  if (TARGET_C3X)
-    return 0;
-  return c4x_int_constant (op) && IS_INT8_CONST (INTVAL (op));
-}
-
-
-static int
-c4x_K_constant (op)
-     rtx op;
-{
-  if (TARGET_C3X)
-    return 0;
-  return c4x_int_constant (op) && IS_INT5_CONST (INTVAL (op));
-}
-
-
-int
-c4x_L_constant (op)
-     rtx op;
-{
-  return c4x_int_constant (op) && IS_UINT16_CONST (INTVAL (op));
-}
-
-
-static int
-c4x_N_constant (op)
-     rtx op;
-{
-  return c4x_int_constant (op) && IS_NOT_UINT16_CONST (INTVAL (op));
-}
-
-
-static int
-c4x_O_constant (op)
-     rtx op;
-{
-  return c4x_int_constant (op) && IS_HIGH_CONST (INTVAL (op));
-}
-
-
-/* The constraints do not have to check the register class,
-   except when needed to discriminate between the constraints.
-   The operand has been checked by the predicates to be valid.  */
-
-/* ARx + 9-bit signed const or IRn
-   *ARx, *+ARx(n), *-ARx(n), *+ARx(IRn), *-Arx(IRn) for -256 < n < 256
-   We don't include the pre/post inc/dec forms here since
-   they are handled by the <> constraints.  */
-
-int
-c4x_Q_constraint (op)
-     rtx op;
-{
-  enum machine_mode mode = GET_MODE (op);
-
-  if (GET_CODE (op) != MEM)
-    return 0;
-  op = XEXP (op, 0);
-  switch (GET_CODE (op))
-    {
-    case REG:
-      return 1;
-
-    case PLUS:
-      {
-	rtx op0 = XEXP (op, 0);
-	rtx op1 = XEXP (op, 1);
-
-	if (! REG_P (op0))
-	  return 0;
-
-	if (REG_P (op1))
-	  return 1;
-
-	if (GET_CODE (op1) != CONST_INT)
-	  return 0;
-
-	/* HImode and HFmode must be offsettable.  */
-	if (mode == HImode || mode == HFmode)
-	  return IS_DISP8_OFF_CONST (INTVAL (op1));
-	
-	return IS_DISP8_CONST (INTVAL (op1));
-      }
-      break;
-    default:
-      break;
-    }
-  return 0;
-}
-
-
-/* ARx + 5-bit unsigned const
-   *ARx, *+ARx(n) for n < 32 */
-
-int
-c4x_R_constraint (op)
-     rtx op;
-{
-  enum machine_mode mode = GET_MODE (op);
-
-  if (TARGET_C3X)
-    return 0;
-  if (GET_CODE (op) != MEM)
-    return 0;
-  op = XEXP (op, 0);
-  switch (GET_CODE (op))
-    {
-    case REG:
-      return 1;
-
-    case PLUS:
-      {
-	rtx op0 = XEXP (op, 0);
-	rtx op1 = XEXP (op, 1);
-
-	if (! REG_P (op0))
-	  return 0;
-
-	if (GET_CODE (op1) != CONST_INT)
-	  return 0;
-
-	/* HImode and HFmode must be offsettable.  */
-	if (mode == HImode || mode == HFmode)
-	  return IS_UINT5_CONST (INTVAL (op1) + 1);
-	
-	return IS_UINT5_CONST (INTVAL (op1));
-      }
-      break;
-    default:
-      break;
-    }
-  return 0;
-}
-
-
-static int
-c4x_R_indirect (op)
-     rtx op;
-{
-  enum machine_mode mode = GET_MODE (op);
-
-  if (TARGET_C3X || GET_CODE (op) != MEM)
-    return 0;
-
-  op = XEXP (op, 0);
-  switch (GET_CODE (op))
-    {
-    case REG:
-      return IS_ADDR_OR_PSEUDO_REGNO (op);
-
-    case PLUS:
-      {
-	rtx op0 = XEXP (op, 0);
-	rtx op1 = XEXP (op, 1);
-
-	/* HImode and HFmode must be offsettable.  */
-	if (mode == HImode || mode == HFmode)
-	  return IS_ADDR_OR_PSEUDO_REGNO (op0)
-	    && GET_CODE (op1) == CONST_INT 
-	    && IS_UINT5_CONST (INTVAL (op1) + 1);
-
-	return REG_P (op0)
-	  && IS_ADDR_OR_PSEUDO_REGNO (op0)
-	  && GET_CODE (op1) == CONST_INT
-	  && IS_UINT5_CONST (INTVAL (op1));
-      }
-      break;
-
-    default:
-      break;
-    }
-  return 0;
-}
-
-
-/* ARx + 1-bit unsigned const or IRn
-   *ARx, *+ARx(1), *-ARx(1), *+ARx(IRn), *-Arx(IRn)
-   We don't include the pre/post inc/dec forms here since
-   they are handled by the <> constraints.  */
-
-int
-c4x_S_constraint (op)
-     rtx op;
-{
-  enum machine_mode mode = GET_MODE (op);
-  if (GET_CODE (op) != MEM)
-    return 0;
-  op = XEXP (op, 0);
-  switch (GET_CODE (op))
-    {
-    case REG:
-      return 1;
-
-    case PRE_MODIFY:
-    case POST_MODIFY:
-      {
-	rtx op0 = XEXP (op, 0);
-	rtx op1 = XEXP (op, 1);
-	
-	if ((GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS)
-	    || (op0 != XEXP (op1, 0)))
-	  return 0;
-	
-	op0 = XEXP (op1, 0);
-	op1 = XEXP (op1, 1);
-	return REG_P (op0) && REG_P (op1);
-	/* pre or post_modify with a displacement of 0 or 1 
-	   should not be generated.  */
-      }
-      break;
-
-    case PLUS:
-      {
-	rtx op0 = XEXP (op, 0);
-	rtx op1 = XEXP (op, 1);
-
-	if (!REG_P (op0))
-	  return 0;
-
-	if (REG_P (op1))
-	  return 1;
-
-	if (GET_CODE (op1) != CONST_INT)
-	  return 0;
-	
-	/* HImode and HFmode must be offsettable.  */
-	if (mode == HImode || mode == HFmode)
-	  return IS_DISP1_OFF_CONST (INTVAL (op1));
-	
-	return IS_DISP1_CONST (INTVAL (op1));
-      }
-      break;
-    default:
-      break;
-    }
-  return 0;
-}
-
-
-static int
-c4x_S_indirect (op)
-     rtx op;
-{
-  enum machine_mode mode = GET_MODE (op);
-  if (GET_CODE (op) != MEM)
-    return 0;
-
-  op = XEXP (op, 0);
-  switch (GET_CODE (op))
-    {
-    case PRE_DEC:
-    case POST_DEC:
-      if (mode != QImode && mode != QFmode)
-	return 0;
-    case PRE_INC:
-    case POST_INC:
-      op = XEXP (op, 0);
-
-    case REG:
-      return IS_ADDR_OR_PSEUDO_REGNO (op);
-
-    case PRE_MODIFY:
-    case POST_MODIFY:
-      {
-	rtx op0 = XEXP (op, 0);
-	rtx op1 = XEXP (op, 1);
-	
-	if (mode != QImode && mode != QFmode)
-	  return 0;
-
-	if ((GET_CODE (op1) != PLUS && GET_CODE (op1) != MINUS)
-	    || (op0 != XEXP (op1, 0)))
-	  return 0;
-	
-	op0 = XEXP (op1, 0);
-	op1 = XEXP (op1, 1);
-	return REG_P (op0) && IS_ADDR_OR_PSEUDO_REGNO (op0)
-	  && REG_P (op1) && IS_INDEX_OR_PSEUDO_REGNO (op1);
-	/* pre or post_modify with a displacement of 0 or 1 
-	   should not be generated.  */
-      }
-
-    case PLUS:
-      {
-	rtx op0 = XEXP (op, 0);
-	rtx op1 = XEXP (op, 1);
-
-	if (REG_P (op0))
-	  {
-	    /* HImode and HFmode must be offsettable.  */
-	    if (mode == HImode || mode == HFmode)
-	      return IS_ADDR_OR_PSEUDO_REGNO (op0)
-		&& GET_CODE (op1) == CONST_INT 
-		&& IS_DISP1_OFF_CONST (INTVAL (op1));
-
-	    if (REG_P (op1))
-	      return (IS_INDEX_OR_PSEUDO_REGNO (op1)
-		      && IS_ADDR_OR_PSEUDO_REGNO (op0))
-		|| (IS_ADDR_OR_PSEUDO_REGNO (op1)
-		    && IS_INDEX_OR_PSEUDO_REGNO (op0));
-	    
-	    return IS_ADDR_OR_PSEUDO_REGNO (op0)
-	      && GET_CODE (op1) == CONST_INT 
-	      && IS_DISP1_CONST (INTVAL (op1));
-	  }
-      }
-      break;
-
-    default:
-      break;
-    }
-  return 0;
-}
-
-
-/* Symbol ref.  */
-
-int
-c4x_T_constraint (op)
-     rtx op;
-{
-  if (GET_CODE (op) != MEM)
-    return 0;
-  op = XEXP (op, 0);
-
-  if ((GET_CODE (op) == PLUS)
-      && (GET_CODE (XEXP (op, 0)) == REG)
-      && (REGNO (XEXP (op, 0)) == DP_REGNO))
-    {
-      op = XEXP (op, 1);
-    }
-  else if ((GET_CODE (op) == PLUS)
-	   && (GET_CODE (XEXP (op, 0)) == PLUS)
-	   && (GET_CODE (XEXP (XEXP (op, 0), 0)) == USE))
-    {
-      op = XEXP (op, 1);
-    }
-  else if ((GET_CODE (op) == PLUS) && (GET_CODE (XEXP (op, 0)) == USE))
-    {
-      op = XEXP (op, 1);
-    }
-
-  /* Don't allow direct addressing to an arbitrary constant.  */
-  if (GET_CODE (op) == CONST
-      && GET_CODE (XEXP (op, 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
-      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
-    return 1;
-
-  return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
-}
-
-
-int
-c4x_autoinc_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) == MEM)
-    {
-      enum rtx_code code = GET_CODE (XEXP (op, 0));
-      
-      if (code == PRE_INC
-	  || code == PRE_DEC
-	  || code == POST_INC
-	  || code == POST_DEC
-	  || code == PRE_MODIFY
-	  || code == POST_MODIFY
-	  )
-	return 1;
-    }
-  return 0;
-}
-
-
-/* Match any operand.  */
-
-int
-any_operand (op, mode)
-     register rtx op ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return 1;
-}
-
-
-/* Nonzero if OP is a floating point value with value 0.0.  */
-
-int
-fp_zero_operand (op)
-     rtx op;
-{
-  REAL_VALUE_TYPE r;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-  return REAL_VALUES_EQUAL (r, dconst0);
-}
-
-
-int
-const_operand (op, mode)
-     register rtx op;
-     register enum machine_mode mode;
-{
-  switch (mode)
-    {
-    case QFmode:
-    case HFmode:
-      if (GET_CODE (op) != CONST_DOUBLE
-	  || GET_MODE (op) != mode
-	  || GET_MODE_CLASS (mode) != MODE_FLOAT)
-	return 0;
-
-      return c4x_immed_float_p (op);
-
-#if Pmode != QImode
-    case Pmode:
-#endif
-    case QImode:
-      if (GET_CODE (op) != CONST_INT
-	  || (GET_MODE (op) != VOIDmode && GET_MODE (op) != mode)
-	  || GET_MODE_CLASS (mode) != MODE_INT)
-	return 0;
-
-      return IS_HIGH_CONST (INTVAL (op)) || IS_INT16_CONST (INTVAL (op));
-
-    case HImode:
-      return 0;
-
-    default:
-      return 0;
-    }
-}
-
-
-int
-stik_const_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return c4x_K_constant (op);
-}
-
-
-int
-not_const_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return c4x_N_constant (op);
-}
-
-
-int
-reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return register_operand (op, mode);
-}
-
-int
-reg_imm_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (REG_P (op) || CONSTANT_P (op))
-    return 1;
-  return 0;
-}
-
-int
-not_modify_reg (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (REG_P (op) || CONSTANT_P (op))
-    return 1;
-  if (GET_CODE (op) != MEM)
-    return 0;
-  op = XEXP (op, 0);
-  switch (GET_CODE (op))
-    {
-    case REG:
-      return 1;
-
-    case PLUS:
-      {
-	rtx op0 = XEXP (op, 0);
-	rtx op1 = XEXP (op, 1);
-
-	if (! REG_P (op0))
-	  return 0;
-	
-	if (REG_P (op1) || GET_CODE (op1) == CONST_INT)
-	  return 1;
-      }
-    case CONST:
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return 1;
-    default:
-      break;
-    }
-  return 0;
-}
-
-int
-not_rc_reg (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (REG_P (op) && REGNO (op) == RC_REGNO)
-    return 0;
-  return 1;
-}
-
-/* Extended precision register R0-R1.  */
-
-int
-r0r1_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (! register_operand (op, mode))
-    return 0;
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  return REG_P (op) && IS_R0R1_OR_PSEUDO_REGNO (op);
-}
-
-
-/* Extended precision register R2-R3.  */
-
-int
-r2r3_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (! register_operand (op, mode))
-    return 0;
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  return REG_P (op) && IS_R2R3_OR_PSEUDO_REGNO (op);
-}
-
-
-/* Low extended precision register R0-R7.  */
-
-int
-ext_low_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (! register_operand (op, mode))
-    return 0;
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  return REG_P (op) && IS_EXT_LOW_OR_PSEUDO_REGNO (op);
-}
-
-
-/* Extended precision register.  */
-
-int
-ext_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (! register_operand (op, mode))
-    return 0;
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  if (! REG_P (op))
-    return 0;
-  return IS_EXT_OR_PSEUDO_REGNO (op);
-}
-
-
-/* Standard precision register.  */
-
-int
-std_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (! register_operand (op, mode))
-    return 0;
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  return REG_P (op) && IS_STD_OR_PSEUDO_REGNO (op);
-}
-
-
-/* Address register.  */
-
-int
-addr_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (! register_operand (op, mode))
-    return 0;
-  return c4x_a_register (op);
-}
-
-
-/* Index register.  */
-
-int
-index_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (! register_operand (op, mode))
-    return 0;
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  return c4x_x_register (op);
-}
-
-
-/* DP register.  */
-
-int
-dp_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return REG_P (op) && IS_DP_OR_PSEUDO_REGNO (op);
-}
-
-
-/* SP register.  */
-
-int
-sp_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return REG_P (op) && IS_SP_OR_PSEUDO_REGNO (op);
-}
-
-
-/* ST register.  */
-
-int
-st_reg_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return REG_P (op) && IS_ST_OR_PSEUDO_REGNO (op);
-}
-
-
-/* RC register.  */
-
-int
-rc_reg_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return REG_P (op) && IS_RC_OR_PSEUDO_REGNO (op);
-}
-
-
-int
-call_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) != MEM)
-    return 0;
-  op = XEXP (op, 0);
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-    case REG:
-      return 1;
-    default:
-    }
-  return 0;
-}
-
-
-/* Check src operand of two operand arithmetic instructions.  */
-
-int
-src_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (REG_P (op))
-    return reg_operand (op, mode);
-
-  if (mode == VOIDmode)
-    mode = GET_MODE (op);
-
-  /* We could allow certain CONST_INT values for HImode...  */
-  if (GET_CODE (op) == CONST_INT)
-    return (mode == QImode || mode == Pmode) && c4x_I_constant (op);
-
-  /* We don't like CONST_DOUBLE integers.  */
-  if (GET_CODE (op) == CONST_DOUBLE)
-    return c4x_H_constant (op);
-
-  return general_operand (op, mode);
-}
-
-
-int
-src_hi_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (c4x_O_constant (op))
-    return 1;
-  return src_operand (op, mode);
-}
-
-
-/* Check src operand of two operand logical instructions.  */
-
-int
-lsrc_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (mode == VOIDmode)
-    mode = GET_MODE (op);
-
-  if (mode != QImode && mode != Pmode)
-    fatal_insn ("Mode not QImode", op);
-
-  if (REG_P (op))
-    return reg_operand (op, mode);
-
-  if (GET_CODE (op) == CONST_INT)
-    return c4x_L_constant (op) || c4x_J_constant (op);
-
-  return general_operand (op, mode);
-}
-
-
-/* Check src operand of two operand tricky instructions.  */
-
-int
-tsrc_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (mode == VOIDmode)
-    mode = GET_MODE (op);
-
-  if (mode != QImode && mode != Pmode)
-    fatal_insn ("Mode not QImode", op);
-
-  if (REG_P (op))
-    return reg_operand (op, mode);
-
-  if (GET_CODE (op) == CONST_INT)
-    return c4x_L_constant (op) || c4x_N_constant (op) || c4x_J_constant (op);
-
-  return general_operand (op, mode);
-}
-
-
-int
-reg_or_const_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return reg_operand (op, mode) || const_operand (op, mode);
-}
-
-
-/* Check for indirect operands allowable in parallel instruction.  */
-
-int
-par_ind_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-
-  return c4x_S_indirect (op);
-}
-
-
-/* Check for operands allowable in parallel instruction.  */
-
-int
-parallel_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return ext_low_reg_operand (op, mode) || par_ind_operand (op, mode);
-}
-
-
-static void 
-c4x_S_address_parse (op, base, incdec, index, disp)
-     rtx op;
-     int *base;
-     int *incdec;
-     int *index;
-     int *disp;
-{
-  *base = 0;
-  *incdec = 0;
-  *index = 0;
-  *disp = 0;
-       
-  if (GET_CODE (op) != MEM)
-    fatal_insn ("Invalid indirect memory address", op);
-  
-  op = XEXP (op, 0);
-  switch (GET_CODE (op))
-    {
-    case PRE_DEC:
-      *base = REGNO (XEXP (op, 0));
-      *incdec = 1;
-      *disp = -1;
-      return;
-
-    case POST_DEC:
-      *base = REGNO (XEXP (op, 0));
-      *incdec = 1;
-      *disp = 0;
-      return;
-
-    case PRE_INC:
-      *base = REGNO (XEXP (op, 0));
-      *incdec = 1;
-      *disp = 1;
-      return;
-
-    case POST_INC:
-      *base = REGNO (XEXP (op, 0));
-      *incdec = 1;
-      *disp = 0;
-      return;
-
-    case POST_MODIFY:
-      *base = REGNO (XEXP (op, 0));
-      if (REG_P (XEXP (XEXP (op, 1), 1)))
-	{
-	  *index = REGNO (XEXP (XEXP (op, 1), 1));
-	  *disp = 0;		/* ??? */
-	}
-      else
-	  *disp = INTVAL (XEXP (XEXP (op, 1), 1));
-      *incdec = 1;
-      return;
-
-    case PRE_MODIFY:
-      *base = REGNO (XEXP (op, 0));
-      if (REG_P (XEXP (XEXP (op, 1), 1)))
-	{
-	  *index = REGNO (XEXP (XEXP (op, 1), 1));
-	  *disp = 1;		/* ??? */
-	}
-      else
-	  *disp = INTVAL (XEXP (XEXP (op, 1), 1));
-      *incdec = 1;
-
-      return;
-
-    case REG:
-      *base = REGNO (op);
-      return;
-
-    case PLUS:
-      {
-	rtx op0 = XEXP (op, 0);
-	rtx op1 = XEXP (op, 1);
-
-	if (c4x_a_register (op0))
-	  {
-	    if (c4x_x_register (op1))
-	      {
-		*base = REGNO (op0);
-		*index = REGNO (op1);
-		return;
-	      }
-	    else if ((GET_CODE (op1) == CONST_INT 
-		      && IS_DISP1_CONST (INTVAL (op1))))
-	      {
-		*base = REGNO (op0);
-		*disp = INTVAL (op1);
-		return;
-	      }
-	  }
-	else if (c4x_x_register (op0) && c4x_a_register (op1))
-	  {
-	    *base = REGNO (op1);
-	    *index = REGNO (op0);
-	    return;
-	  }
-      }
-      /* Fallthrough  */
-
-    default:
-      fatal_insn ("Invalid indirect (S) memory address", op);
-    }
-}
-
-
-int
-c4x_address_conflict (op0, op1, store0, store1)
-     rtx op0;
-     rtx op1;
-     int store0;
-     int store1;
-{
-  int base0;
-  int base1;
-  int incdec0;
-  int incdec1;
-  int index0;
-  int index1;
-  int disp0;
-  int disp1;
-  
-  if (MEM_VOLATILE_P (op0) && MEM_VOLATILE_P (op1))
-    return 1;
-
-  c4x_S_address_parse (op0, &base0, &incdec0, &index0, &disp0);
-  c4x_S_address_parse (op1, &base1, &incdec1, &index1, &disp1);
-
-  if (store0 && store1)
-    {
-      /* If we have two stores in parallel to the same address, then
-	 the C4x only executes one of the stores.  This is unlikely to
-	 cause problems except when writing to a hardware device such
-	 as a FIFO since the second write will be lost.  The user
-	 should flag the hardware location as being volatile so that
-	 we don't do this optimisation.  While it is unlikely that we
-	 have an aliased address if both locations are not marked
-	 volatile, it is probably safer to flag a potential conflict
-	 if either location is volatile.  */
-      if (! flag_argument_noalias)
-	{
-	  if (MEM_VOLATILE_P (op0) || MEM_VOLATILE_P (op1))
-	    return 1;
-	}
-    }
-
-  /* If have a parallel load and a store to the same address, the load
-     is performed first, so there is no conflict.  Similarly, there is
-     no conflict if have parallel loads from the same address.  */
-
-  /* Cannot use auto increment or auto decrement twice for same
-     base register.  */
-  if (base0 == base1 && incdec0 && incdec0)
-    return 1;
-
-  /* It might be too confusing for GCC if we have use a base register
-     with a side effect and a memory reference using the same register
-     in parallel.  */
-  if (! TARGET_DEVEL && base0 == base1 && (incdec0 || incdec1))
-    return 1;
-
-  /* We can not optimize the case where op1 and op2 refer to the same
-     address. */
-  if (base0 == base1 && disp0 == disp1 && index0 == index1)
-    return 1;
-
-  /* No conflict.  */
-  return 0;
-}
-
-
-/* Check for while loop inside a decrement and branch loop.  */
-
-int
-c4x_label_conflict (insn, jump, db)
-     rtx insn;
-     rtx jump;
-     rtx db;
-{
-  while (insn)
-    {
-      if (GET_CODE (insn) == CODE_LABEL)
-	{
-          if (CODE_LABEL_NUMBER (jump) == CODE_LABEL_NUMBER (insn))
-	    return 1;
-          if (CODE_LABEL_NUMBER (db) == CODE_LABEL_NUMBER (insn))
-	    return 0;
-	}
-      insn = PREV_INSN (insn);
-    }
-  return 1;
-}
-
-
-/* Validate combination of operands for parallel load/store instructions.  */
-
-int
-valid_parallel_load_store (operands, mode)
-     rtx *operands;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-  rtx op2 = operands[2];
-  rtx op3 = operands[3];
-
-  if (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-  if (GET_CODE (op1) == SUBREG)
-    op1 = SUBREG_REG (op1);
-  if (GET_CODE (op2) == SUBREG)
-    op2 = SUBREG_REG (op2);
-  if (GET_CODE (op3) == SUBREG)
-    op3 = SUBREG_REG (op3);
-
-  /* The patterns should only allow ext_low_reg_operand() or
-     par_ind_operand() operands.  Thus of the 4 operands, only 2
-     should be REGs and the other 2 should be MEMs.  */
-
-  /* This test prevents the multipack pass from using this pattern if
-     op0 is used as an index or base register in op2 or op3, since
-     this combination will require reloading.  */
-  if (GET_CODE (op0) == REG
-      && ((GET_CODE (op2) == MEM && reg_mentioned_p (op0, XEXP (op2, 0)))
-	  || (GET_CODE (op3) == MEM && reg_mentioned_p (op0, XEXP (op3, 0)))))
-    return 0;
-
-  /* LDI||LDI  */
-  if (GET_CODE (op0) == REG && GET_CODE (op2) == REG)
-    return (REGNO (op0) != REGNO (op2))
-      && GET_CODE (op1) == MEM && GET_CODE (op3) == MEM
-      && ! c4x_address_conflict (op1, op3, 0, 0);
-
-  /* STI||STI  */
-  if (GET_CODE (op1) == REG && GET_CODE (op3) == REG)
-    return GET_CODE (op0) == MEM && GET_CODE (op2) == MEM
-      && ! c4x_address_conflict (op0, op2, 1, 1);
-
-  /* LDI||STI  */
-  if (GET_CODE (op0) == REG && GET_CODE (op3) == REG)
-    return GET_CODE (op1) == MEM && GET_CODE (op2) == MEM
-      && ! c4x_address_conflict (op1, op2, 0, 1);
-
-  /* STI||LDI  */
-  if (GET_CODE (op1) == REG && GET_CODE (op2) == REG)
-    return GET_CODE (op0) == MEM && GET_CODE (op3) == MEM
-      && ! c4x_address_conflict (op0, op3, 1, 0);
-
-  return 0;
-}
-
-
-int
-valid_parallel_operands_4 (operands, mode)
-     rtx *operands;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  rtx op0 = operands[0];
-  rtx op2 = operands[2];
-
-  if (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-  if (GET_CODE (op2) == SUBREG)
-    op2 = SUBREG_REG (op2);
-
-  /* This test prevents the multipack pass from using this pattern if
-     op0 is used as an index or base register in op2, since this combination
-     will require reloading.  */
-  if (GET_CODE (op0) == REG
-      && GET_CODE (op2) == MEM
-      && reg_mentioned_p (op0, XEXP (op2, 0)))
-    return 0;
-
-  return 1;
-}
-
-
-int
-valid_parallel_operands_5 (operands, mode)
-     rtx *operands;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  int regs = 0;
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-  rtx op2 = operands[2];
-  rtx op3 = operands[3];
-
-  if (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-  if (GET_CODE (op1) == SUBREG)
-    op1 = SUBREG_REG (op1);
-  if (GET_CODE (op2) == SUBREG)
-    op2 = SUBREG_REG (op2);
-
-  /* The patterns should only allow ext_low_reg_operand() or
-     par_ind_operand() operands.  Operands 1 and 2 may be commutative
-     but only one of them can be a register.  */
-  if (GET_CODE (op1) == REG)
-    regs++;
-  if (GET_CODE (op2) == REG)
-    regs++;
-
-  if (regs != 1)
-    return 0;
-
-  /* This test prevents the multipack pass from using this pattern if
-     op0 is used as an index or base register in op3, since this combination
-     will require reloading.  */
-  if (GET_CODE (op0) == REG
-      && GET_CODE (op3) == MEM
-      && reg_mentioned_p (op0, XEXP (op3, 0)))
-    return 0;
-
-  return 1;
-}
-
-
-int
-valid_parallel_operands_6 (operands, mode)
-     rtx *operands;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  int regs = 0;
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-  rtx op2 = operands[2];
-  rtx op4 = operands[4];
-  rtx op5 = operands[5];
-
-  if (GET_CODE (op1) == SUBREG)
-    op1 = SUBREG_REG (op1);
-  if (GET_CODE (op2) == SUBREG)
-    op2 = SUBREG_REG (op2);
-  if (GET_CODE (op4) == SUBREG)
-    op4 = SUBREG_REG (op4);
-  if (GET_CODE (op5) == SUBREG)
-    op5 = SUBREG_REG (op5);
-
-  /* The patterns should only allow ext_low_reg_operand() or
-     par_ind_operand() operands.  Thus of the 4 input operands, only 2
-     should be REGs and the other 2 should be MEMs.  */
-
-  if (GET_CODE (op1) == REG)
-    regs++;
-  if (GET_CODE (op2) == REG)
-    regs++;
-  if (GET_CODE (op4) == REG)
-    regs++;
-  if (GET_CODE (op5) == REG)
-    regs++;
-
-  /* The new C30/C40 silicon dies allow 3 regs of the 4 input operands. 
-     Perhaps we should count the MEMs as well?  */
-  if (regs != 2)
-    return 0;
-
-  /* This test prevents the multipack pass from using this pattern if
-     op0 is used as an index or base register in op4 or op5, since
-     this combination will require reloading.  */
-  if (GET_CODE (op0) == REG
-      && ((GET_CODE (op4) == MEM && reg_mentioned_p (op0, XEXP (op4, 0)))
-	  || (GET_CODE (op5) == MEM && reg_mentioned_p (op0, XEXP (op5, 0)))))
-    return 0;
-
-  return 1;
-}
-
-
-/* Validate combination of src operands.  Note that the operands have
-   been screened by the src_operand predicate.  We just have to check
-   that the combination of operands is valid.  If FORCE is set, ensure
-   that the destination regno is valid if we have a 2 operand insn.  */
-
-static int
-c4x_valid_operands (code, operands, mode, force)
-     enum rtx_code code;
-     rtx *operands;
-     enum machine_mode mode;
-     int force;
-{
-  rtx op1;
-  rtx op2;
-  enum rtx_code code1;
-  enum rtx_code code2;
-
-  if (code == COMPARE)
-    {
-      op1 = operands[0];
-      op2 = operands[1];
-    }
-  else
-    {
-      op1 = operands[1];
-      op2 = operands[2];
-    }
-
-  if (GET_CODE (op1) == SUBREG)
-    op1 = SUBREG_REG (op1);
-  if (GET_CODE (op2) == SUBREG)
-    op2 = SUBREG_REG (op2);
-
-  code1 = GET_CODE (op1);
-  code2 = GET_CODE (op2);
-
-  if (code1 == REG && code2 == REG)
-    return 1;
-
-  if (code1 == MEM && code2 == MEM)
-    {
-      if (c4x_S_indirect (op1, mode) && c4x_S_indirect (op2, mode))
-	return 1;
-      return c4x_R_indirect (op1, mode) && c4x_R_indirect (op2, mode);
-    }
-
-  if (code1 == code2)
-    return 0;
-
-  if (code1 == REG)
-    {
-      switch (code2)
-	{
-	case CONST_INT:
-	  if (c4x_J_constant (op2) && c4x_R_indirect (op1))
-	    return 1;
-	  break;
-	  
-	case CONST_DOUBLE:
-	  if (! c4x_H_constant (op2))
-	    return 0;
-	  break;
-
-	  /* Any valid memory operand screened by src_operand is OK.  */
-  	case MEM:
-	  
-	  /* After CSE, any remaining (ADDRESSOF:P reg) gets converted
-	     into a stack slot memory address comprising a PLUS and a
-	     constant.  */
-	case ADDRESSOF:
-	  break;
-	  
-	default:
-	  fatal ("c4x_valid_operands: Internal error");
-	  break;
-	}
-      
-      /* Check that we have a valid destination register for a two operand
-	 instruction.  */
-      return ! force || code == COMPARE || REGNO (op1) == REGNO (operands[0]);
-    }
-
-  /* We assume MINUS is commutative since the subtract patterns
-     also support the reverse subtract instructions.  Since op1
-     is not a register, and op2 is a register, op1 can only
-     be a restricted memory operand for a shift instruction.  */
-  if (code == ASHIFTRT || code == LSHIFTRT
-      || code == ASHIFT || code == COMPARE)
-    return code2 == REG
-      && (c4x_S_indirect (op1) || c4x_R_indirect (op1));
-  
-  switch (code1)
-    {
-    case CONST_INT:
-      if (c4x_J_constant (op1) && c4x_R_indirect (op2))
-	return 1;
-      break;
-      
-    case CONST_DOUBLE:
-      if (! c4x_H_constant (op1))
-	return 0;
-      break;
-
-      /* Any valid memory operand screened by src_operand is OK. */      
-    case MEM:
-
-      /* After CSE, any remaining (ADDRESSOF:P reg) gets converted
-	 into a stack slot memory address comprising a PLUS and a
-	 constant.  */
-    case ADDRESSOF:
-      break;
-      
-    default:
-      fatal ("c4x_valid_operands: Internal error");
-      break;
-    }
-      
-  /* Check that we have a valid destination register for a two operand
-     instruction.  */
-  return ! force || REGNO (op1) == REGNO (operands[0]);
-}
-
-
-int valid_operands (code, operands, mode)
-     enum rtx_code code;
-     rtx *operands;
-     enum machine_mode mode;
-{
-
-  /* If we are not optimizing then we have to let anything go and let
-     reload fix things up.  instantiate_decl in function.c can produce
-     invalid insns by changing the offset of a memory operand from a
-     valid one into an invalid one, when the second operand is also a
-     memory operand.  The alternative is not to allow two memory
-     operands for an insn when not optimizing.  The problem only rarely
-     occurs, for example with the C-torture program DFcmp.c  */
-
-  return ! optimize || c4x_valid_operands (code, operands, mode, 0);
-}
-
-
-int
-legitimize_operands (code, operands, mode)
-     enum rtx_code code;
-     rtx *operands;
-     enum machine_mode mode;
-{
-  /* Compare only has 2 operands.  */
-  if (code == COMPARE)
-    {
-      /* During RTL generation, force constants into pseudos so that
-	 they can get hoisted out of loops.  This will tie up an extra
-	 register but can save an extra cycle.  Only do this if loop
-	 optimisation enabled.  (We cannot pull this trick for add and
-	 sub instructions since the flow pass won't find
-	 autoincrements etc.)  This allows us to generate compare
-	 instructions like CMPI R0, *AR0++ where R0 = 42, say, instead
-	 of LDI *AR0++, R0; CMPI 42, R0. 
-
-	 Note that expand_binops will try to load an expensive constant
-	 into a register if it is used within a loop.  Unfortunately,
-	 the cost mechanism doesn't allow us to look at the other
-	 operand to decide whether the constant is expensive.  */
-      
-      if (! reload_in_progress
-	  && TARGET_HOIST
-	  && optimize > 0
-	  && ((GET_CODE (operands[1]) == CONST_INT 
-	       && ! c4x_J_constant (operands[1])
-	       && INTVAL (operands[1]) != 0)
-	      || GET_CODE (operands[1]) == CONST_DOUBLE))
-	operands[1] = force_reg (mode, operands[1]);
-      
-      if (! reload_in_progress
-          && ! c4x_valid_operands (code, operands, mode, 0))
-	operands[0] = force_reg (mode, operands[0]);
-      return 1;
-    }
-  
-  /* We cannot do this for ADDI/SUBI insns since we will
-     defeat the flow pass from finding autoincrement addressing
-     opportunities.  */
-  if (! reload_in_progress
-      && ! ((code == PLUS || code == MINUS) && mode == Pmode)
-      && (TARGET_HOIST && optimize > 1
-       && ((GET_CODE (operands[2]) == CONST_INT 
-	    && ! c4x_J_constant (operands[2])
-	    && INTVAL (operands[2]) != 0)
-	   || GET_CODE (operands[2]) == CONST_DOUBLE)))
-    operands[2] = force_reg (mode, operands[2]);
-
-  /* We can get better code on a C30 if we force constant shift counts
-     into a register.  This way they can get hoisted out of loops,
-     tying up a register, but saving an instruction.  The downside is
-     that they may get allocated to an address or index register, and
-     thus we will get a pipeline conflict if there is a nearby
-     indirect address using an address register. 
-
-     Note that expand_binops will not try to load an expensive constant
-     into a register if it is used within a loop for a shift insn.  */
-  
-  if (! reload_in_progress
-      && ! c4x_valid_operands (code, operands, mode, TARGET_FORCE))
-    {
-      /* If the operand combination is invalid, we force operand1 into a
-         register, preventing reload from having doing to do this at a
-         later stage.  */
-      operands[1] = force_reg (mode, operands[1]);
-      if (TARGET_FORCE)
-	{
-	  emit_move_insn (operands[0], operands[1]);
-	  operands[1] = copy_rtx (operands[0]);
-	}
-      else
-	{
-	  /* Just in case...  */
-	  if (! c4x_valid_operands (code, operands, mode, 0))
-	    operands[2] = force_reg (mode, operands[2]);
-	}
-    }
-
-  /* Right shifts require a negative shift count, but GCC expects
-     a positive count, so we emit a NEG.  */
-  if ((code == ASHIFTRT || code == LSHIFTRT)
-      && (GET_CODE (operands[2]) != CONST_INT))
-    operands[2] = gen_rtx_NEG (mode, negate_rtx (mode, operands[2]));
-  
-  return 1;
-}
-
-
-/* The following predicates are used for instruction scheduling.  */
-
-int
-group1_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  return REG_P (op) && IS_GROUP1_REG (REGNO (op));
-}
-
-
-int
-group1_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-
-  if (GET_CODE (op) == MEM)
-    {
-      op = XEXP (op, 0);
-      if (GET_CODE (op) == PLUS)
-	{
-	  rtx op0 = XEXP (op, 0);
-	  rtx op1 = XEXP (op, 1);
-
-	  if (((GET_CODE (op0) == REG) && IS_GROUP1_REGNO (op0))
-	      || ((GET_CODE (op1) == REG) && IS_GROUP1_REGNO (op1)))
-	    return 1;
-	}
-      else if ((REG_P (op)) && IS_GROUP1_REGNO (op))
-	return 1;
-    }
-
-  return 0;
-}
-
-
-/* Return true if any one of the address registers.  */
-
-int
-arx_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  return REG_P (op) && IS_ADDR_REGNO (op);
-}
-
-
-static int
-c4x_arn_reg_operand (op, mode, regno)
-     rtx op;
-     enum machine_mode mode;
-     int regno;
-{
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  return REG_P (op) && (REGNO (op) == regno);
-}
-
-
-static int
-c4x_arn_mem_operand (op, mode, regno)
-     rtx op;
-     enum machine_mode mode;
-     int regno;
-{
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-
-  if (GET_CODE (op) == MEM)
-    {
-      op = XEXP (op, 0);
-      switch (GET_CODE (op))
-	{
-	case PRE_DEC:
-	case POST_DEC:
-	case PRE_INC:
-	case POST_INC:
-	  op = XEXP (op, 0);
-
-	case REG:
-          if (REG_P (op) && (REGNO (op) == regno))
-	    return 1;
-	  break;
-
-	case PRE_MODIFY:
-	case POST_MODIFY:
-          if (REG_P (XEXP (op, 0)) && (REGNO (XEXP (op, 0)) == regno))
-	    return 1;
-          if (REG_P (XEXP (XEXP (op, 1), 1))
-	      && (REGNO (XEXP (XEXP (op, 1), 1)) == regno))
-	    return 1;
-	  break;
-
-	case PLUS:
-	  {
-	    rtx op0 = XEXP (op, 0);
-	    rtx op1 = XEXP (op, 1);
-
-	    if (((GET_CODE (op0) == REG) && (REGNO (op0) == regno)) 
-	        || ((GET_CODE (op1) == REG) && (REGNO (op1) == regno)))
-	      return 1;
-	  }
-	  break;
-	default:
-	  break;
-	}
-    }
-  return 0;
-}
-
-
-int
-ar0_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_reg_operand (op, mode, AR0_REGNO);
-}
-
-
-int
-ar0_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_mem_operand (op, mode, AR0_REGNO);
-}
-
-
-int
-ar1_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_reg_operand (op, mode, AR1_REGNO);
-}
-
-
-int
-ar1_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_mem_operand (op, mode, AR1_REGNO);
-}
-
-
-int
-ar2_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_reg_operand (op, mode, AR2_REGNO);
-}
-
-
-int
-ar2_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_mem_operand (op, mode, AR2_REGNO);
-}
-
-
-int
-ar3_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_reg_operand (op, mode, AR3_REGNO);
-}
-
-
-int
-ar3_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_mem_operand (op, mode, AR3_REGNO);
-}
-
-
-int
-ar4_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_reg_operand (op, mode, AR4_REGNO);
-}
-
-
-int
-ar4_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_mem_operand (op, mode, AR4_REGNO);
-}
-
-
-int
-ar5_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_reg_operand (op, mode, AR5_REGNO);
-}
-
-
-int
-ar5_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_mem_operand (op, mode, AR5_REGNO);
-}
-
-
-int
-ar6_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_reg_operand (op, mode, AR6_REGNO);
-}
-
-
-int
-ar6_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_mem_operand (op, mode, AR6_REGNO);
-}
-
-
-int
-ar7_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_reg_operand (op, mode, AR7_REGNO);
-}
-
-
-int
-ar7_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_mem_operand (op, mode, AR7_REGNO);
-}
-
-
-int
-ir0_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_reg_operand (op, mode, IR0_REGNO);
-}
-
-
-int
-ir0_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_mem_operand (op, mode, IR0_REGNO);
-}
-
-
-int
-ir1_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_reg_operand (op, mode, IR1_REGNO);
-}
-
-
-int
-ir1_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return c4x_arn_mem_operand (op, mode, IR1_REGNO);
-}
-
-
-/* We allow autoincrement addressing.  */
-
-rtx
-c4x_operand_subword (op, i, validate_address, mode)
-     rtx op;
-     int i;
-     int validate_address;
-     enum machine_mode mode;
-{
-  if (mode != HImode && mode != HFmode)
-    fatal_insn ("c4x_operand_subword: invalid mode", op);
-
-  if (mode == HFmode && REG_P (op))
-    fatal_insn ("c4x_operand_subword: invalid operand", op);
-
-  if (GET_CODE (op) == MEM)
-    {
-      enum rtx_code code = GET_CODE (XEXP (op, 0));
-      enum machine_mode mode = GET_MODE (XEXP (op, 0));
-
-      switch (code)
-	{
-	case POST_INC:
-	case PRE_INC:
-	  if (mode == HImode)
-	    mode = QImode;
-	  else if (mode == HFmode)
-	    mode = QFmode;
-	  return gen_rtx_MEM (mode, XEXP (op, 0));
-	  
-	case POST_DEC:
-	case PRE_DEC:
-	case PRE_MODIFY:
-	case POST_MODIFY:
-	  /* We could handle these with some difficulty.
-	     e.g., *p-- => *(p-=2); *(p+1).  */
-	  fatal_insn ("c4x_operand_subword: invalid autoincrement", op);
-
-	default:
-	  break;
-	}
-    }
-  
-  return operand_subword (op, i, validate_address, mode);
-}
-
-/* Handle machine specific pragmas for compatibility with existing
-   compilers for the C3x/C4x.
-
-   pragma				   attribute
-   ----------------------------------------------------------
-   CODE_SECTION(symbol,"section")          section("section")
-   DATA_SECTION(symbol,"section")          section("section")
-   FUNC_CANNOT_INLINE(function)            
-   FUNC_EXT_CALLED(function)               
-   FUNC_IS_PURE(function)                  const
-   FUNC_IS_SYSTEM(function)                
-   FUNC_NEVER_RETURNS(function)            noreturn
-   FUNC_NO_GLOBAL_ASG(function)            
-   FUNC_NO_IND_ASG(function)               
-   INTERRUPT(function)                     interrupt
-
-   */
-
-int
-c4x_handle_pragma (p_getc, p_ungetc, pname)
-     int (*  p_getc) PROTO ((void));
-     void (* p_ungetc) PROTO ((int)) ATTRIBUTE_UNUSED;
-     char *pname;
-{
-  int i;
-  int c;
-  int namesize;
-  char *name;
-  tree func;
-  tree sect = NULL_TREE;
-  tree new;
-
-  c = p_getc ();
-  while (c == ' ' || c == '\t') c = p_getc ();
-  if (c != '(')
-    return 0;
-
-  c = p_getc ();
-  while (c == ' ' || c == '\t') c = p_getc ();
-  if (! (isalpha(c) || c == '_' || c == '$' || c == '@'))
-    return 0;
-
-  i = 0;
-  namesize = 16;
-  name = xmalloc (namesize);
-  while (isalnum (c) || c == '_' || c == '$' || c == '@')
-    {
-      if (i >= namesize-1)
-	{
-	  namesize += 16;
-	  name = xrealloc (name, namesize);
-	}
-      name[i++] = c;
-      c = p_getc ();
-    }
-  name[i] = 0;
-  func = get_identifier (name);
-  free (name);
-  
-  if (strcmp (pname, "CODE_SECTION") == 0
-      || strcmp (pname, "DATA_SECTION") == 0)
-    {
-      while (c == ' ' || c == '\t') c = p_getc ();
-      if (c != ',')
-        return 0;
-
-      c = p_getc ();
-      while (c == ' ' || c == '\t') c = p_getc ();
-      if (c != '"')
-        return 0;
-
-      i = 0;
-      namesize = 16;
-      name = xmalloc (namesize);
-      c = p_getc ();
-      while (c != '"' && c != '\n' && c != '\r' && c != EOF)
-        {
-          if (i >= namesize-1)
-	    {
-	      namesize += 16;
-	      name = xrealloc (name, namesize);
-	    }
-          name[i++] = c;
-          c = p_getc ();
-        }
-      name[i] = 0;
-      sect = build_string (i, name);
-      free (name);
-      sect = build_tree_list (NULL_TREE, sect);
-      
-      if (c != '"')
-        return 0;
-      c = p_getc ();
-    }
-  while (c == ' ' || c == '\t') c = p_getc ();
-  if (c != ')')
-    return 0;
-  
-  new = build_tree_list (func, sect);
-  if (strcmp (pname, "CODE_SECTION") == 0)
-    code_tree = chainon (code_tree, new);
-  
-  else if (strcmp (pname, "DATA_SECTION") == 0)
-    data_tree = chainon (data_tree, new);
-  
-  else if (strcmp (pname, "FUNC_CANNOT_INLINE") == 0)
-      ; /* ignore */
-  
-  else if (strcmp (pname, "FUNC_EXT_CALLED") == 0)
-      ; /* ignore */
-  
-  else if (strcmp (pname, "FUNC_IS_PURE") == 0)
-     pure_tree = chainon (pure_tree, new);
-  
-  else if (strcmp (pname, "FUNC_IS_SYSTEM") == 0)
-      ; /* ignore */
-  
-  else if (strcmp (pname, "FUNC_NEVER_RETURNS") == 0)
-    noreturn_tree = chainon (noreturn_tree, new);
-  
-  else if (strcmp (pname, "FUNC_NO_GLOBAL_ASG") == 0)
-      ; /* ignore */
-  
-  else if (strcmp (pname, "FUNC_NO_IND_ASG") == 0)
-      ; /* ignore */
-  
-  else if (strcmp (pname, "INTERRUPT") == 0)
-    interrupt_tree = chainon (interrupt_tree, new);
-  
-  else
-    return 0;
-  
-  return 1;
-}
-
-
-static void
-c4x_check_attribute(attrib, list, decl, attributes)
-     char *attrib;
-     tree list, decl, *attributes;
-{
-  while (list != NULL_TREE
-         && IDENTIFIER_POINTER (TREE_PURPOSE (list))
-	 != IDENTIFIER_POINTER (DECL_NAME (decl)))
-    list = TREE_CHAIN(list);
-  if (list)
-    *attributes = chainon (*attributes,
-			   build_tree_list (get_identifier (attrib),
-					    TREE_VALUE(list)));
-}
-
-
-void
-c4x_set_default_attributes(decl, attributes)
-     tree decl, *attributes;
-{
-  switch (TREE_CODE (decl))
-    {
-    case FUNCTION_DECL:
-      c4x_check_attribute ("section", code_tree, decl, attributes);
-      c4x_check_attribute ("const", pure_tree, decl, attributes);
-      c4x_check_attribute ("noreturn", noreturn_tree, decl, attributes);
-      c4x_check_attribute ("interrupt", interrupt_tree, decl, attributes);
-      break;
-
-    case VAR_DECL:
-      c4x_check_attribute ("section", data_tree, decl, attributes);
-      break;
-
-    default:
-      break;
-    }
-}
-
-
-/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine
-   specific attribute for TYPE.  The attributes in ATTRIBUTES have
-   previously been assigned to TYPE.  */
-
-int
-c4x_valid_type_attribute_p (type, attributes, identifier, args)
-     tree type;
-     tree attributes ATTRIBUTE_UNUSED;
-     tree identifier;
-     tree args ATTRIBUTE_UNUSED;
-{
-  if (TREE_CODE (type) != FUNCTION_TYPE)
-    return 0;
-  
-  if (is_attribute_p ("interrupt", identifier))
-    return 1;
-  
-  if (is_attribute_p ("assembler", identifier))
-    return 1;
-  
-  if (is_attribute_p ("leaf_pretend", identifier))
-    return 1;
-  
-  return 0;
-}
-
-
-/* !!! FIXME to emit RPTS correctly.  */
-int
-c4x_rptb_rpts_p (insn, op)
-     rtx insn, op;
-{
-  /* The next insn should be our label marking where the
-     repeat block starts.  */
-  insn = NEXT_INSN (insn);
-  if (GET_CODE (insn) != CODE_LABEL)
-    {
-      /* Some insns may have been shifted between the RPTB insn
-         and the top label... They were probably destined to
-         be moved out of the loop.  For now, let's leave them
-         where they are and print a warning.  We should
-         probably move these insns before the repeat block insn.  */
-      if (TARGET_DEBUG)
-	fatal_insn("c4x_rptb_rpts_p: Repeat block top label moved\n",
-		   insn);
-      return 0;
-    }
-
-  /* Skip any notes.  */
-  insn = next_nonnote_insn (insn);
-
-  /* This should be our first insn in the loop.  */
-  if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
-    return 0;
-
-  /* Skip any notes.  */
-  insn = next_nonnote_insn (insn);
-
-  if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
-    return 0;
-
-  if (recog_memoized (insn) != CODE_FOR_rptb_end)
-    return 0;
-
-  if (TARGET_RPTS)
-    return 1;
-
-  return (GET_CODE (op) == CONST_INT) && TARGET_RPTS_CYCLES (INTVAL (op));
-}
-
-
-/* Adjust the cost of a scheduling dependency.  Return the new cost of
-   a dependency LINK or INSN on DEP_INSN.  COST is the current cost. 
-   A set of an address register followed by a use occurs a 2 cycle
-   stall (reduced to a single cycle on the c40 using LDA), while
-   a read of an address register followed by a use occurs a single cycle.  */
-#define	SET_USE_COST	3
-#define	SETLDA_USE_COST	2
-#define	READ_USE_COST	2
-
-int
-c4x_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
-{
-  /* Don't worry about this until we know what registers have been
-     assigned.  */
-  if (! reload_completed)
-    return 0;
-
-  /* How do we handle dependencies where a read followed by another
-     read causes a pipeline stall?  For example, a read of ar0 followed
-     by the use of ar0 for a memory reference.  It looks like we
-     need to extend the scheduler to handle this case.  */
-
-  /* Reload sometimes generates a CLOBBER of a stack slot, e.g.,
-     (clobber (mem:QI (plus:QI (reg:QI 11 ar3) (const_int 261)))),
-     so only deal with insns we know about.  */
-  if (recog_memoized (dep_insn) < 0)
-    return 0;
-
-  if (REG_NOTE_KIND (link) == 0)
-    {
-      int max = 0;
-
-      /* Data dependency; DEP_INSN writes a register that INSN reads some
-	 cycles later.  */
-
-      if (TARGET_C3X)
-	{
-	  if (get_attr_setgroup1 (dep_insn) && get_attr_usegroup1 (insn))
-	    max = SET_USE_COST > max ? SET_USE_COST : max;
-	  if (get_attr_readarx (dep_insn) && get_attr_usegroup1 (insn))
-	    max = READ_USE_COST > max ? READ_USE_COST : max;
-	}
-      else
-	{
-	  /* This could be significantly optimized. We should look
-	     to see if dep_insn sets ar0-ar7 or ir0-ir1 and if
-	     insn uses ar0-ar7.  We then test if the same register
-	     is used.  The tricky bit is that some operands will
-	     use several registers...  */
-
-	  if (get_attr_setar0 (dep_insn) && get_attr_usear0 (insn))
-	    max = SET_USE_COST > max ? SET_USE_COST : max;
-	  if (get_attr_setlda_ar0 (dep_insn) && get_attr_usear0 (insn))
-	    max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
-	  if (get_attr_readar0 (dep_insn) && get_attr_usear0 (insn))
-	    max = READ_USE_COST > max ? READ_USE_COST : max;
-
-	  if (get_attr_setar1 (dep_insn) && get_attr_usear1 (insn))
-	    max = SET_USE_COST > max ? SET_USE_COST : max;
-	  if (get_attr_setlda_ar1 (dep_insn) && get_attr_usear1 (insn))
-	    max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
-	  if (get_attr_readar1 (dep_insn) && get_attr_usear1 (insn))
-	    max = READ_USE_COST > max ? READ_USE_COST : max;
-
-	  if (get_attr_setar2 (dep_insn) && get_attr_usear2 (insn))
-	    max = SET_USE_COST > max ? SET_USE_COST : max;
-	  if (get_attr_setlda_ar2 (dep_insn) && get_attr_usear2 (insn))
-	    max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
-	  if (get_attr_readar2 (dep_insn) && get_attr_usear2 (insn))
-	    max = READ_USE_COST > max ? READ_USE_COST : max;
-
-	  if (get_attr_setar3 (dep_insn) && get_attr_usear3 (insn))
-	    max = SET_USE_COST > max ? SET_USE_COST : max;
-	  if (get_attr_setlda_ar3 (dep_insn) && get_attr_usear3 (insn))
-	    max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
-	  if (get_attr_readar3 (dep_insn) && get_attr_usear3 (insn))
-	    max = READ_USE_COST > max ? READ_USE_COST : max;
-
-	  if (get_attr_setar4 (dep_insn) && get_attr_usear4 (insn))
-	    max = SET_USE_COST > max ? SET_USE_COST : max;
-	  if (get_attr_setlda_ar4 (dep_insn) && get_attr_usear4 (insn))
-	    max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
-	  if (get_attr_readar4 (dep_insn) && get_attr_usear4 (insn))
-	    max = READ_USE_COST > max ? READ_USE_COST : max;
-
-	  if (get_attr_setar5 (dep_insn) && get_attr_usear5 (insn))
-	    max = SET_USE_COST > max ? SET_USE_COST : max;
-	  if (get_attr_setlda_ar5 (dep_insn) && get_attr_usear5 (insn))
-	    max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
-	  if (get_attr_readar5 (dep_insn) && get_attr_usear5 (insn))
-	    max = READ_USE_COST > max ? READ_USE_COST : max;
-
-	  if (get_attr_setar6 (dep_insn) && get_attr_usear6 (insn))
-	    max = SET_USE_COST > max ? SET_USE_COST : max;
-	  if (get_attr_setlda_ar6 (dep_insn) && get_attr_usear6 (insn))
-	    max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
-	  if (get_attr_readar6 (dep_insn) && get_attr_usear6 (insn))
-	    max = READ_USE_COST > max ? READ_USE_COST : max;
-
-	  if (get_attr_setar7 (dep_insn) && get_attr_usear7 (insn))
-	    max = SET_USE_COST > max ? SET_USE_COST : max;
-	  if (get_attr_setlda_ar7 (dep_insn) && get_attr_usear7 (insn))
-	    max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
-	  if (get_attr_readar7 (dep_insn) && get_attr_usear7 (insn))
-	    max = READ_USE_COST > max ? READ_USE_COST : max;
-
-	  if (get_attr_setir0 (dep_insn) && get_attr_useir0 (insn))
-	    max = SET_USE_COST > max ? SET_USE_COST : max;
-	  if (get_attr_setlda_ir0 (dep_insn) && get_attr_useir0 (insn))
-	    max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
-
-	  if (get_attr_setir1 (dep_insn) && get_attr_useir1 (insn))
-	    max = SET_USE_COST > max ? SET_USE_COST : max;
-	  if (get_attr_setlda_ir1 (dep_insn) && get_attr_useir1 (insn))
-	    max = SETLDA_USE_COST > max ? SETLDA_USE_COST : max;
-	}
-
-      if (max)
-	cost = max;
-
-      /* For other data dependencies, the default cost specified in the
-	 md is correct.  */
-      return cost;
-    }
-  else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
-    {
-      /* Anti dependency; DEP_INSN reads a register that INSN writes some
-	 cycles later.  */
-
-      /* For c4x anti dependencies, the cost is 0.  */
-      return 0;
-    }
-  else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
-    {
-      /* Output dependency; DEP_INSN writes a register that INSN writes some
-	 cycles later.  */
-
-      /* For c4x output dependencies, the cost is 0.  */
-      return 0;
-    }
-  else
-    abort ();
-}
diff --git a/gcc/config/c4x/c4x.h b/gcc/config/c4x/c4x.h
deleted file mode 100755
index 2a0a7c0..0000000
--- a/gcc/config/c4x/c4x.h
+++ /dev/null
@@ -1,2671 +0,0 @@
-/* Definitions of target machine for GNU compiler.  TMS320C[34]x
-   Copyright (C) 1994-98, 1999 Free Software Foundation, Inc.
-
-   Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
-              and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
-
-   This file is part of GNU CC.
-
-   GNU CC is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 1, or (at your option)
-   any later version.
-
-   GNU CC is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GNU CC; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
-
-/* Set the following so that some of the macros expand to function
-   calls to simplify debugging.  */
-#define C4X_DEBUG 1
-
-/* RUN-TIME TARGET SPECIFICATION */
-
-#define C4x   1
-
-/* Name of the c4x assembler */
-
-#define ASM_PROG "c4x-as"
-
-/* Name of the c4x linker */
-
-#define LD_PROG "c4x-ld"
-
-/* Define assembler options */
-
-#define ASM_SPEC "\
-%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=40:%{!mcpu=44:\
-%{!m30:%{!m40:-m40}}}}}}} \
-%{mcpu=30:-m30} \
-%{mcpu=31:-m31} \
-%{mcpu=32:-m32} \
-%{mcpu=40:-m40} \
-%{mcpu=44:-m44} \
-%{m30:-m30} \
-%{m31:-m31} \
-%{m32:-m32} \
-%{m40:-m40} \
-%{m44:-m44} \
-%{mmemparm:-p} %{mregparm:-r} \
-%{!mmemparm:%{!mregparm:-r}} \
-%{mbig:-b} %{msmall:-s} \
-%{!msmall:%{!mbig:-b}}"
-
-/* Define linker options */
-
-#define LINK_SPEC "\
-%{m30:--architecture c3x} \
-%{m31:--architecture c3x} \
-%{m32:--architecture c3x} \
-%{mcpu=30:--architecture c3x} \
-%{mcpu=31:--architecture c3x} \
-%{mcpu=32:--architecture c3x}"
-
-/* Define C preprocessor options. */
-
-#define CPP_SPEC "\
-%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=40:%{!mcpu=44:\
-  %{!m40:%{!m44:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 }}}}}}}}}} \
-%{mcpu=30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
-%{m30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
-%{mcpu=31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
-%{m31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
-%{mcpu=32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
-%{m32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
-%{mcpu=40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
-%{m40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
-%{mcpu=44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
-%{m44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
-%{mmemparm:-U_REGPARM }%{mregparm:-D_REGPARM } \
-%{!mmemparm:%{!mregparm:-D_REGPARM }} \
-%{msmall:-U_BIGMODEL } %{mbig:-D_BIGMODEL } \
-%{!msmall:%{!mbig:-D_BIGMODEL }} \
-%{finline-functions:-D_INLINE }"
-
-/* Specify the startup file to link with. */
-
-#define STARTFILE_SPEC "\
-%{!mmemparm:%{m30:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
-%{mmemparm:%{m30:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
-%{!mmemparm:%{m31:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
-%{mmemparm:%{m31:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
-%{!mmemparm:%{m32:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
-%{mmemparm:%{m32:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
-%{!mmemparm:%{mcpu=30:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
-%{mmemparm:%{mcpu=30:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
-%{!mmemparm:%{mcpu=31:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
-%{mmemparm:%{mcpu=31:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
-%{!mmemparm:%{mcpu=32:%{msmall:crt0_3sr%O%s} %{!msmall:crt0_3br%O%s}}} \
-%{mmemparm:%{mcpu=32:%{msmall:crt0_3sm%O%s} %{!msmall:crt0_3bm%O%s}}} \
-%{!mmemparm:%{m40:%{msmall:crt0_4sr%O%s} %{!msmall:crt0_4br%O%s}}} \
-%{mmemparm:%{m40:%{msmall:crt0_4sm%O%s} %{!msmall:crt0_4bm%O%s}}} \
-%{!mmemparm:%{m44:%{msmall:crt0_4sr%O%s} %{!msmall:crt0_4br%O%s}}} \
-%{mmemparm:%{m44:%{msmall:crt0_4sm%O%s} %{!msmall:crt0_4bm%O%s}}} \
-%{!mmemparm:%{mcpu=40:%{msmall:crt0_4sr%O%s} %{!msmall:crt0_4br%O%s}}} \
-%{mmemparm:%{mcpu=40:%{msmall:crt0_4sm%O%s} %{!msmall:crt0_4bm%O%s}}} \
-%{!mmemparm:%{mcpu=44:%{msmall:crt0_4sr%O%s} %{!msmall:crt0_4br%O%s}}} \
-%{mmemparm:%{mcpu=44:%{msmall:crt0_4sm%O%s} %{!msmall:crt0_4bm%O%s}}} \
-%{!mmemparm:%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32: \
-  %{!mcpu=40:%{!mcpu=44:%{!m40:%{!m44:%{msmall:crt0_4sr%O%s}}}}}}}}}}}} \
-%{mmemparm:%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32: \
-  %{!mcpu=40:%{!mcpu=44:%{!m40:%{!m44:%{msmall:crt0_4sm%O%s}}}}}}}}}}}} \
-%{!mmemparm:%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32: \
-  %{!mcpu=40:%{!mcpu=44:%{!m40:%{!m44:%{!msmall:crt0_4br%O%s}}}}}}}}}}}} \
-%{mmemparm:%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32: \
-  %{!mcpu=40:%{!mcpu=44:%{!m40:%{!m44:%{!msmall:crt0_4bm%O%s}}}}}}}}}}}}"
-
-/* Specify the end file to link with */
-
-#define ENDFILE_SPEC ""
-
-/* Target compilation option flags */
-
-#define SMALL_MEMORY_FLAG   0x0000001 /* small memory model */
-#define MPYI_FLAG           0x0000002 /* use 24-bit MPYI for C3x */
-#define FAST_FIX_FLAG       0x0000004 /* fast fixing of floats */
-#define RPTS_FLAG           0x0000008 /* allow use of RPTS */
-#define C3X_FLAG            0x0000010 /* emit C3x code */
-#define TI_FLAG             0x0000020 /* be compatible with TI assembler */
-#define PARANOID_FLAG       0x0000040 /* be paranoid about DP reg. in ISRs */
-#define MEMPARM_FLAG        0x0000080 /* pass arguments on stack */
-#define DEVEL_FLAG          0x0000100 /* enable features under development */
-#define RPTB_FLAG           0x0000200 /* enable repeat block */
-#define BK_FLAG             0x0000400 /* use BK as general register */
-#define DB_FLAG             0x0000800 /* use decrement and branch for C3x */
-#define DEBUG_FLAG          0x0001000 /* enable debugging of GCC */
-#define HOIST_FLAG          0x0002000 /* force constants into registers */
-#define LOOP_UNSIGNED_FLAG  0x0004000 /* allow unsigned loop counters */
-#define FORCE_FLAG          0x0008000 /* force op0 and op1 to be same */
-#define PRESERVE_FLOAT_FLAG 0x0010000 /* save all 40 bits for floats */
-#define PARALLEL_PACK_FLAG  0x0020000 /* allow parallel insn packing */
-#define PARALLEL_MPY_FLAG   0x0040000 /* allow MPY||ADD, MPY||SUB insns */
-#define ALIASES_FLAG	    0x0080000 /* assume mem refs possibly aliased */
-
-#define C30_FLAG            0x0100000 /* emit C30 code */
-#define C31_FLAG            0x0200000 /* emit C31 code */
-#define C32_FLAG            0x0400000 /* emit C32 code */
-#define C40_FLAG            0x1000000 /* emit C40 code */
-#define C44_FLAG            0x2000000 /* emit C44 code */
-
-/* Run-time compilation parameters selecting different hardware subsets.
-
-   Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES \
-{ { "small", SMALL_MEMORY_FLAG }, \
-  { "big", -SMALL_MEMORY_FLAG }, \
-  { "mpyi", MPYI_FLAG}, \
-  { "no-mpyi", -MPYI_FLAG}, \
-  { "fast-fix", FAST_FIX_FLAG}, \
-  { "no-fast-fix", -FAST_FIX_FLAG}, \
-  { "rpts", RPTS_FLAG}, \
-  { "no-rpts", -RPTS_FLAG}, \
-  { "rptb", RPTB_FLAG}, \
-  { "no-rptb", -RPTB_FLAG}, \
-  { "30", C30_FLAG}, \
-  { "31", C31_FLAG}, \
-  { "32", C32_FLAG}, \
-  { "40", C40_FLAG}, \
-  { "44", C44_FLAG}, \
-  { "ti", TI_FLAG}, \
-  { "no-ti", -TI_FLAG}, \
-  { "paranoid", PARANOID_FLAG}, \
-  { "no-paranoid", -PARANOID_FLAG}, \
-  { "isr-dp-reload", PARANOID_FLAG}, \
-  { "no-isr-dp-reload", -PARANOID_FLAG}, \
-  { "memparm", MEMPARM_FLAG}, \
-  { "regparm", -MEMPARM_FLAG}, \
-  { "devel", DEVEL_FLAG}, \
-  { "no-devel", -DEVEL_FLAG}, \
-  { "bk", BK_FLAG}, \
-  { "no-bk", -BK_FLAG}, \
-  { "db", DB_FLAG}, \
-  { "no-db", -DB_FLAG}, \
-  { "debug", DEBUG_FLAG}, \
-  { "no-debug", -DEBUG_FLAG}, \
-  { "hoist", HOIST_FLAG}, \
-  { "no-hoist", -HOIST_FLAG}, \
-  { "no-force", -FORCE_FLAG}, \
-  { "force", FORCE_FLAG}, \
-  { "loop-unsigned", LOOP_UNSIGNED_FLAG}, \
-  { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG}, \
-  { "preserve-float", PRESERVE_FLOAT_FLAG}, \
-  { "no-preserve-float", -PRESERVE_FLOAT_FLAG}, \
-  { "parallel-insns", PARALLEL_PACK_FLAG}, \
-  { "no-parallel-mpy", -PARALLEL_MPY_FLAG}, \
-  { "parallel-mpy", PARALLEL_MPY_FLAG}, \
-  { "no-parallel-insns", -PARALLEL_PACK_FLAG}, \
-  { "aliases", ALIASES_FLAG}, \
-  { "no-aliases", -ALIASES_FLAG}, \
-  { "", TARGET_DEFAULT} }
-
-/* Default target switches */
-
-/* Play safe, not the fastest code. */
-#define TARGET_DEFAULT		ALIASES_FLAG | PARALLEL_PACK_FLAG \
-				| PARALLEL_MPY_FLAG | RPTB_FLAG
-
-/* Caveats:
-   Max iteration count for RPTB/RPTS is 2^31 + 1.
-   Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
-   RPTS blocks interrupts.  */
-
-
-extern int target_flags;
-
-#define TARGET_INLINE		1 /* Inline MPYI */
-#define TARGET_PARALLEL	        1 /* Enable parallel insns in MD */
-#define TARGET_SMALL_REG_CLASS	0
-
-#define TARGET_SMALL		(target_flags & SMALL_MEMORY_FLAG)
-#define TARGET_MPYI		(!TARGET_C3X || (target_flags & MPYI_FLAG))
-#define TARGET_FAST_FIX		(target_flags & FAST_FIX_FLAG)
-#define TARGET_RPTS		(target_flags & RPTS_FLAG)
-#define TARGET_TI		(target_flags & TI_FLAG)
-#define TARGET_PARANOID		(target_flags & PARANOID_FLAG)
-#define TARGET_MEMPARM		(target_flags & MEMPARM_FLAG)
-#define TARGET_DEVEL		(target_flags & DEVEL_FLAG)
-#define TARGET_RPTB		(target_flags & RPTB_FLAG \
-				 && optimize >= 2)
-#define TARGET_BK		(target_flags & BK_FLAG)
-#define TARGET_DB		(! TARGET_C3X || (target_flags & DB_FLAG))
-#define TARGET_DEBUG		(target_flags & DEBUG_FLAG)
-#define TARGET_HOIST		(target_flags & HOIST_FLAG)
-#define TARGET_LOOP_UNSIGNED	(target_flags & LOOP_UNSIGNED_FLAG)
-#define TARGET_FORCE		(target_flags & FORCE_FLAG)
-#define	TARGET_PRESERVE_FLOAT	(target_flags & PRESERVE_FLOAT_FLAG)
-#define TARGET_PARALLEL_PACK	(TARGET_RPTB \
-				 && (target_flags & PARALLEL_PACK_FLAG) \
-				 && optimize >= 2)
-#define TARGET_PARALLEL_MPY	(TARGET_PARALLEL_PACK \
-				 && (target_flags & PARALLEL_MPY_FLAG))
-#define	TARGET_ALIASES		(target_flags & ALIASES_FLAG)
-
-#define TARGET_C3X		(target_flags & C3X_FLAG)
-#define TARGET_C30		(target_flags & C30_FLAG)
-#define TARGET_C31		(target_flags & C31_FLAG)
-#define TARGET_C32		(target_flags & C32_FLAG)
-#define TARGET_C40		(target_flags & C40_FLAG)
-#define TARGET_C44		(target_flags & C44_FLAG)
-
-/* -mrpts            allows the use of the RPTS instruction irregardless.
-   -mrpts=max-cycles will use RPTS if the number of cycles is constant
-   and less than max-cycles. */
-
-#define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
-
-/* -mcpu=XX    with XX = target DSP version number */
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an
-   initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   fixed part of the option name, and the address of a variable.
-   The variable, type `char *', is set to the variable part of the
-   given option if the fixed part matches.  The actual option name
-   is made by appending `-m' to the specified name.
-
-   Here is an example which defines `-mshort-data-NUMBER'.  If the
-   given option is `-mshort-data-512', the variable `m88k_short_data'
-   will be set to the string `"512"'.
-
-   extern char *m88k_short_data;
-   #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } }  */
-
-extern char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
-
-#define TARGET_OPTIONS		\
-{ {"rpts=", &c4x_rpts_cycles_string},\
-  {"cpu=", &c4x_cpu_version_string} }
-
-/* Sometimes certain combinations of command options do not make sense
-   on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed. */
-
-extern void c4x_override_options ();
-#define OVERRIDE_OPTIONS c4x_override_options ()
-
-/* Define this to change the optimizations performed by default.  */
-extern void c4x_optimization_options ();
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL,SIZE)
-
-/* Run Time Target Specification  */
-
-#define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)" );
-
-/* Storage Layout  */
-
-#define BITS_BIG_ENDIAN		0
-#define BYTES_BIG_ENDIAN	0
-#define WORDS_BIG_ENDIAN	0
-
-/* Technically, we are little endian, but we put the floats out as
-   whole longs and this makes GCC put them out in the right order. */
-
-#define FLOAT_WORDS_BIG_ENDIAN	1
-
-/* Note the ANSI C standard requires sizeof(char) = 1.  On the C[34]x
-   all integral and floating point data types are stored in memory as
-   32-bits (floating point types can be stored as 40-bits in the
-   extended precision registers), so sizeof(char) = sizeof(short) =
-   sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
-
-#define BITS_PER_UNIT		32
-#define BITS_PER_WORD		32
-#define UNITS_PER_WORD		1
-#define POINTER_SIZE		32
-#define PARM_BOUNDARY	        32
-#define STACK_BOUNDARY		32
-#define FUNCTION_BOUNDARY	32
-#define BIGGEST_ALIGNMENT	32
-#define EMPTY_FIELD_BOUNDARY	32
-#define STRICT_ALIGNMENT	0
-#define TARGET_FLOAT_FORMAT	C4X_FLOAT_FORMAT
-#define MAX_FIXED_MODE_SIZE	64 /* HImode */
-
-/* Use the internal floating point stuff in the compiler and not the
-   host floating point stuff. */
-
-#define REAL_ARITHMETIC
-
-/* Define register numbers */
-
-/* Extended-precision registers */
-
-#define R0_REGNO   0
-#define R1_REGNO   1
-#define R2_REGNO   2
-#define R3_REGNO   3
-#define R4_REGNO   4
-#define R5_REGNO   5
-#define R6_REGNO   6
-#define R7_REGNO   7
-
-/* Auxiliary (address) registers */
-
-#define AR0_REGNO  8
-#define AR1_REGNO  9
-#define AR2_REGNO 10
-#define AR3_REGNO 11
-#define AR4_REGNO 12
-#define AR5_REGNO 13
-#define AR6_REGNO 14
-#define AR7_REGNO 15
-
-/* Data page register */
-
-#define DP_REGNO  16
-
-/* Index registers */
-
-#define IR0_REGNO 17
-#define IR1_REGNO 18
-
-/* Block size register */
-
-#define BK_REGNO  19
-
-/* Stack pointer */
-
-#define SP_REGNO  20
-
-/* Status register */
-
-#define ST_REGNO  21
-
-/* Misc. interrupt registers */
-
-#define DIE_REGNO 22		/* C4x only */
-#define IE_REGNO  22		/* C3x only */
-#define IIE_REGNO 23		/* C4x only */
-#define IF_REGNO  23		/* C3x only */
-#define IIF_REGNO 24		/* C4x only */
-#define IOF_REGNO 24		/* C3x only */
-
-/* Repeat block registers */
-
-#define RS_REGNO  25
-#define RE_REGNO  26
-#define RC_REGNO  27
-
-/* Additional extended-precision registers */
-
-#define R8_REGNO  28		/* C4x only */
-#define R9_REGNO  29		/* C4x only */
-#define R10_REGNO 30		/* C4x only */
-#define R11_REGNO 31		/* C4x only */
-
-#define FIRST_PSEUDO_REGISTER	32
-
-/* Extended precision registers (low set) */
-
-#define IS_R0R1_REG(r)             ((((r) >= R0_REGNO) && ((r) <= R1_REGNO)))
-#define IS_R2R3_REG(r)             ((((r) >= R2_REGNO) && ((r) <= R3_REGNO)))
-#define IS_EXT_LOW_REG(r)          ((((r) >= R0_REGNO) && ((r) <= R7_REGNO)))
-
-/* Extended precision registers (high set) */
-
-#define IS_EXT_HIGH_REG(r)         (! TARGET_C3X \
-			            && ((r) >= R8_REGNO) && ((r) <= R11_REGNO))
-/* Address registers */
-
-#define IS_AUX_REG(r)    (((r) >= AR0_REGNO) && ((r) <= AR7_REGNO))
-#define IS_ADDR_REG(r)   IS_AUX_REG(r)
-#define IS_DP_REG(r)     ((r) == DP_REGNO)
-#define IS_INDEX_REG(r)  (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
-#define IS_SP_REG(r)     ((r) == SP_REGNO)
-#define IS_BK_REG(r)     (TARGET_BK && (r) == BK_REGNO)
-
-/* Misc registers */
-
-#define IS_ST_REG(r)     ((r) == ST_REGNO)
-#define IS_RC_REG(r)     ((r) == RC_REGNO)
-#define IS_REPEAT_REG(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
-
-/* Composite register sets */
-
-#define IS_ADDR_OR_INDEX_REG(r) (IS_ADDR_REG(r) || IS_INDEX_REG(r))
-#define IS_EXT_REG(r)           (IS_EXT_LOW_REG(r) || IS_EXT_HIGH_REG(r))
-#define IS_STD_REG(r)           (IS_ADDR_OR_INDEX_REG(r) || IS_REPEAT_REG(r) \
-                                 || IS_SP_REG(r) || IS_BK_REG(r))
-#define IS_INT_REG(r)           (IS_EXT_REG(r) || IS_STD_REG(r))
-#define IS_GROUP1_REG(r)        (IS_ADDR_OR_INDEX_REG(r) || IS_BK_REG(r))
-
-
-#define IS_PSEUDO_REG(r)            ((r) >= FIRST_PSEUDO_REGISTER)
-#define IS_R0R1_OR_PSEUDO_REG(r)    (IS_R0R1_REG(r) || IS_PSEUDO_REG(r))
-#define IS_R2R3_OR_PSEUDO_REG(r)    (IS_R2R3_REG(r) || IS_PSEUDO_REG(r))
-#define IS_EXT_OR_PSEUDO_REG(r)     (IS_EXT_REG(r) || IS_PSEUDO_REG(r))
-#define IS_STD_OR_PSEUDO_REG(r)     (IS_STD_REG(r) || IS_PSEUDO_REG(r))
-#define IS_INT_OR_PSEUDO_REG(r)     (IS_INT_REG(r) || IS_PSEUDO_REG(r))
-#define IS_ADDR_OR_PSEUDO_REG(r)    (IS_ADDR_REG(r) || IS_PSEUDO_REG(r))
-#define IS_INDEX_OR_PSEUDO_REG(r)   (IS_INDEX_REG(r) || IS_PSEUDO_REG(r))
-#define IS_EXT_LOW_OR_PSEUDO_REG(r) (IS_EXT_LOW_REG(r) || IS_PSEUDO_REG(r))
-#define IS_DP_OR_PSEUDO_REG(r)      (IS_DP_REG(r) || IS_PSEUDO_REG(r))
-#define IS_SP_OR_PSEUDO_REG(r)      (IS_SP_REG(r) || IS_PSEUDO_REG(r))
-#define IS_ST_OR_PSEUDO_REG(r)      (IS_ST_REG(r) || IS_PSEUDO_REG(r))
-#define IS_RC_OR_PSEUDO_REG(r)      (IS_RC_REG(r) || IS_PSEUDO_REG(r))
-
-#define IS_PSEUDO_REGNO(op)          (IS_PSEUDO_REG(REGNO(op)))
-#define IS_ADDR_REGNO(op)            (IS_ADDR_REG(REGNO(op)))
-#define IS_INDEX_REGNO(op)           (IS_INDEX_REG(REGNO(op)))
-#define IS_GROUP1_REGNO(r)           (IS_GROUP1_REG(REGNO(op)))
-
-#define IS_R0R1_OR_PSEUDO_REGNO(op)  (IS_R0R1_OR_PSEUDO_REG(REGNO(op)))
-#define IS_R2R3_OR_PSEUDO_REGNO(op)  (IS_R2R3_OR_PSEUDO_REG(REGNO(op)))
-#define IS_EXT_OR_PSEUDO_REGNO(op)   (IS_EXT_OR_PSEUDO_REG(REGNO(op)))
-#define IS_STD_OR_PSEUDO_REGNO(op)   (IS_STD_OR_PSEUDO_REG(REGNO(op)))
-#define IS_EXT_LOW_OR_PSEUDO_REGNO(op) (IS_EXT_LOW_OR_PSEUDO_REG(REGNO(op)))
-#define IS_INT_OR_PSEUDO_REGNO(op)   (IS_INT_OR_PSEUDO_REG(REGNO(op)))
-
-#define IS_ADDR_OR_PSEUDO_REGNO(op)  (IS_ADDR_OR_PSEUDO_REG(REGNO(op)))
-#define IS_INDEX_OR_PSEUDO_REGNO(op) (IS_INDEX_OR_PSEUDO_REG(REGNO(op)))
-#define IS_DP_OR_PSEUDO_REGNO(op)    (IS_DP_OR_PSEUDO_REG(REGNO(op)))
-#define IS_SP_OR_PSEUDO_REGNO(op)    (IS_SP_OR_PSEUDO_REG(REGNO(op)))
-#define IS_ST_OR_PSEUDO_REGNO(op)    (IS_ST_OR_PSEUDO_REG(REGNO(op)))
-#define IS_RC_OR_PSEUDO_REGNO(op)    (IS_RC_OR_PSEUDO_REG(REGNO(op)))
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator. */
-
-#define FIXED_REGISTERS \
-{									\
-/* R0  R1  R2  R3  R4  R5  R6  R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 */	\
-    0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,	\
-/* DP IR0 IR1  BK  SP  ST DIE IIE IIF  RS  RE  RC  R8  R9 R10 R11 */	\
-    1,  0,  0,  0,  1,  1,  1,  1,  1,  0,  0,  0,  0,  0,  0,  0	\
-}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  
-   
-   Note that the extended precision registers are only saved in some
-   modes.  The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
-   get clobbered for a given regno.  */
-
-#define CALL_USED_REGISTERS \
-{									\
-/* R0  R1  R2  R3  R4  R5  R6  R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 */	\
-    1,  1,  1,  1,  0,  0,  0,  0,  1,  1,  1,  0,  0,  0,  0,  0,	\
-/* DP IR0 IR1  BK  SP  ST DIE IIE IIF  RS  RE  RC  R8  R9 R10 R11 */	\
-    1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  1,  0,  1,  1,  1	\
-}
-
-/* Macro to conditionally modify fixed_regs/call_used_regs. */
-
-#define CONDITIONAL_REGISTER_USAGE			\
-  {							\
-    if (! TARGET_BK)					\
-      {							\
-	fixed_regs[BK_REGNO] = 1;			\
-        call_used_regs[BK_REGNO] = 1;			\
-        c4x_regclass_map[BK_REGNO] = NO_REGS;		\
-      }							\
-    if (TARGET_C3X)					\
-      {							\
-	 int i;                                          \
-							 \
-	 reg_names[DIE_REGNO] = "ie";  /* clobber die */ \
-	 reg_names[IF_REGNO] = "if";   /* clobber iie */ \
-	 reg_names[IOF_REGNO] = "iof"; /* clobber iif */ \
-	 						\
-	 for (i = R8_REGNO; i <= R11_REGNO; i++)	\
-	 {						\
-	     fixed_regs[i] = call_used_regs[i] = 1;	\
-	     c4x_regclass_map[i] = NO_REGS;		\
-	 }						\
-      }							\
-    if (TARGET_PRESERVE_FLOAT)				\
-      {							\
-	c4x_caller_save_map[R6_REGNO] = HFmode;		\
-	c4x_caller_save_map[R7_REGNO] = HFmode;		\
-      }							\
-   }
-
-/* Order of Allocation of Registers  */
-
-/* List the order in which to allocate registers.  Each register must be
-   listed once, even those in FIXED_REGISTERS.
-
-   First allocate registers that don't need preservation across calls,
-   except index and address registers.  Then allocate data registers
-   that require preservation across calls (even though this invokes an
-   extra overhead of having to save/restore these registers).  Next
-   allocate the address and index registers, since using these
-   registers for arithmetic can cause pipeline stalls.  Finally
-   allocated the fixed registers which won't be allocated anyhow.  */
-
-#define REG_ALLOC_ORDER					\
-{R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, 		\
- R9_REGNO, R10_REGNO, R11_REGNO,			\
- RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO,		\
- R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO,	\
- AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO,		\
- AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO,		\
- IR0_REGNO, IR1_REGNO,					\
- SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
-
-
-/* Determine which register classes are very likely used by spill registers.
-   local-alloc.c won't allocate pseudos that have these classes as their
-   preferred class unless they are "preferred or nothing".  */
-
-#define CLASS_LIKELY_SPILLED_P(CLASS) \
- ((CLASS) == INDEX_REGS)
-
-/* CCmode is wrongly defined in machmode.def  It should have a size
-   of UNITS_PER_WORD. */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)				\
-(((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
-((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-
-/* A C expression that is nonzero if the hard register REGNO is preserved
-   across a call in mode MODE.  This does not have to include the call used
-   registers.  */
-
-#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE)		              \
-     ((((REGNO) == R6_REGNO || (REGNO) == R7_REGNO) && ! ((MODE) == QFmode))  \
-      || (((REGNO) == R4_REGNO || (REGNO) == R5_REGNO || (REGNO == R8_REGNO)) \
-	  && ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
-
-/* Specify the modes required to caller save a given hard regno.  */
-
-#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS) (c4x_caller_save_map[REGNO])
-
-int c4x_hard_regno_mode_ok ();
-#define HARD_REGNO_MODE_OK(REGNO, MODE)  c4x_hard_regno_mode_ok(REGNO, MODE)
-
-
-/* A C expression that is nonzero if it is desirable to choose
-   register allocation so as to avoid move instructions between a
-   value of mode MODE1 and a value of mode MODE2.
-
-   Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-
-#define MODES_TIEABLE_P(MODE1, MODE2)		0
-
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-enum reg_class
-  {
-    NO_REGS,
-    R0R1_REGS,			/* 't' */
-    R2R3_REGS,			/* 'u' */
-    EXT_LOW_REGS,		/* 'q' */
-    EXT_REGS,			/* 'f' */
-    ADDR_REGS,			/* 'a' */
-    INDEX_REGS,			/* 'x' */
-    BK_REG,			/* 'k' */
-    SP_REG,			/* 'b' */
-    RC_REG,			/* 'v' */
-    INT_REGS,			/* 'c' */
-    GENERAL_REGS,		/* 'r' */
-    DP_REG,			/* 'z' */
-    ST_REG,			/* 'y' */
-    ALL_REGS,
-    LIM_REG_CLASSES
-  };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-#define REG_CLASS_NAMES \
-{			\
-   "NO_REGS",		\
-   "R0R1_REGS",		\
-   "R2R3_REGS",		\
-   "EXT_LOW_REGS",	\
-   "EXT_REGS",		\
-   "ADDR_REGS",		\
-   "INDEX_REGS",	\
-   "BK_REG",		\
-   "SP_REG",		\
-   "RC_REG",		\
-   "INT_REGS",		\
-   "GENERAL_REGS",	\
-   "DP_REG",		\
-   "ST_REG",		\
-   "ALL_REGS"		\
-}
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  RC is not included in GENERAL_REGS
-   since the register allocator will often choose a general register
-   in preference to RC for the decrement_and_branch_on_count pattern.  */
-
-#define REG_CLASS_CONTENTS \
-{						\
- {0x00000000}, /*     No registers */		\
- {0x00000003}, /* 't' R0-R1	 */		\
- {0x0000000c}, /* 'u' R2-R3	 */		\
- {0x000000ff}, /* 'q' R0-R7	 */		\
- {0xf00000ff}, /* 'f' R0-R11       */		\
- {0x0000ff00}, /* 'a' AR0-AR7 */		\
- {0x00060000}, /* 'x' IR0-IR1 */		\
- {0x00080000}, /* 'k' BK */			\
- {0x00100000}, /* 'b' SP */			\
- {0x08000000}, /* 'v' RC */			\
- {0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC */	\
- {0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC */\
- {0x00010000}, /* 'z' DP */			\
- {0x00200000}, /* 'y' ST */			\
- {0xffffffff}, /*     All registers */		\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
-
-/* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
-   explicitly used in the rtl is kept as short as possible.
-
-   We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
-   is defined since the MPY|ADD insns require the classes R0R1_REGS and
-   R2R3_REGS which are used by the function return registers (R0,R1) and
-   the register arguments (R2,R3), respectively.  I'm reluctant to define
-   this macro since it stomps on many potential optimisations.  Ideally
-   it should have a register class argument so that not all the register
-   classes gets penalised for the sake of a naughty few...  For long
-   double arithmetic we need two additional registers that we can use as
-   spill registers.  */
-
-#define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
-
-#define BASE_REG_CLASS	ADDR_REGS
-#define INDEX_REG_CLASS INDEX_REGS
-
-/*
-  Register constraints for the C4x
- 
-  a - address reg (ar0-ar7)
-  b - stack reg (sp)
-  c - other gp int-only reg
-  d - data/int reg (equiv. to f)
-  f - data/float reg
-  h - data/long double reg (equiv. to f)
-  k - block count (bk)
-  q - r0-r7
-  t - r0-r1
-  u - r2-r3
-  v - repeat count (rc)
-  x - index register (ir0-ir1)
-  y - status register (st)
-  z - dp reg (dp) 
-
-  Memory/constant constraints for the C4x
-
-  G - short float 16-bit
-  I - signed 16-bit constant (sign extended)
-  J - signed 8-bit constant (sign extended)  (C4x only)
-  K - signed 5-bit constant (sign extended)  (C4x only for stik)
-  L - unsigned 16-bit constant
-  M - unsigned 8-bit constant                (C4x only)
-  N - ones complement of unsigned 16-bit constant
-  Q - indirect arx + 9-bit signed displacement
-      (a *-arx(n) or *+arx(n) is used to account for the sign bit)
-  R - indirect arx + 5-bit unsigned displacement  (C4x only)
-  S - indirect arx + 0, 1, or irn displacement
-  T - direct symbol ref
-  > - indirect with autoincrement
-  < - indirect with autodecrement
-  } - indirect with post-modify
-  { - indirect with pre-modify
-  */
-
-#define REG_CLASS_FROM_LETTER(CC)				\
-     ( ((CC) == 'a') ? ADDR_REGS				\
-     : ((CC) == 'b') ? SP_REG					\
-     : ((CC) == 'c') ? INT_REGS					\
-     : ((CC) == 'd') ? EXT_REGS					\
-     : ((CC) == 'f') ? EXT_REGS					\
-     : ((CC) == 'h') ? EXT_REGS					\
-     : ((CC) == 'k') ? BK_REG					\
-     : ((CC) == 'q') ? EXT_LOW_REGS				\
-     : ((CC) == 't') ? R0R1_REGS				\
-     : ((CC) == 'u') ? R2R3_REGS				\
-     : ((CC) == 'v') ? RC_REG					\
-     : ((CC) == 'x') ? INDEX_REGS				\
-     : ((CC) == 'y') ? ST_REG					\
-     : ((CC) == 'z') ? DP_REG					\
-     : NO_REGS )
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_BASE_P(REGNO)  \
-     (IS_ADDR_REG(REGNO) || IS_ADDR_REG((unsigned)reg_renumber[REGNO]))
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-     (IS_INDEX_REG(REGNO) || IS_INDEX_REG((unsigned)reg_renumber[REGNO]))
-
-extern enum reg_class c4x_preferred_reload_class ();
-#define PREFERRED_RELOAD_CLASS(X, CLASS) c4x_preferred_reload_class(X, CLASS)
-
-extern enum reg_class c4x_limit_reload_class ();
-#define LIMIT_RELOAD_CLASS(X, CLASS) c4x_limit_reload_class(X, CLASS)
-
-extern enum reg_class c4x_secondary_memory_needed ();
-#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 	\
-c4x_secondary_memory_needed(CLASS1, CLASS2, MODE)
-
-#define CLASS_MAX_NREGS(CLASS, MODE)			\
-(((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
-((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-#define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16))	/* 'K' */
-
-#define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0))	/* 'R' */
-
-#define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128))	/* 'J' */
-
-#define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0))	/* 'M' */
-
-#define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I' */
-
-#define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0))	/* 'L' */
-
-#define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL))	/* 'N' */
-
-#define IS_HIGH_CONST(VAL) (! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O' */
-
-
-#define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S' */
-
-#define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255))	/* 'Q' */
-
-#define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
-				 && IS_DISP1_CONST (VAL + 1))
-
-#define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
-				 && IS_DISP8_CONST (VAL + 1))
-
-#define CONST_OK_FOR_LETTER_P(VAL, C)					\
-        ( ((C) == 'I') ? (IS_INT16_CONST (VAL))				\
-	: ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL))		\
-	: ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL))		\
-        : ((C) == 'L') ? (IS_UINT16_CONST (VAL))			\
-	: ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL))		\
-	: ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL))		        \
-	: ((C) == 'O') ? (IS_HIGH_CONST (VAL))			        \
-        : 0 )	
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VAL, C) 				\
-        ( ((C) == 'G') ? (fp_zero_operand (VAL))			\
-	: ((C) == 'H') ? (c4x_H_constant (VAL)) 			\
-	: 0 )
-
-#define EXTRA_CONSTRAINT(VAL, C) \
-        ( ((C) == 'Q') ? (c4x_Q_constraint (VAL))			\
-	: ((C) == 'R') ? (c4x_R_constraint (VAL))			\
-	: ((C) == 'S') ? (c4x_S_constraint (VAL))			\
-	: ((C) == 'T') ? (c4x_T_constraint (VAL))			\
-	: 0 )
-
-#define SMALL_CONST(VAL, insn)						\
-     (  ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16))	\
-	? IS_INT16_CONST (VAL)						\
-	: ( (get_attr_data (insn) == DATA_NOT_UINT16)			\
-	    ? IS_NOT_UINT16_CONST (VAL)					\
-	    :  ( (get_attr_data (insn) == DATA_HIGH_16)			\
-	       ? IS_HIGH_CONST (VAL)					\
-	       : IS_UINT16_CONST (VAL)					\
-	    )								\
-	  )								\
-	)
-
-/*
-   I. Routine calling with arguments in registers
-   ----------------------------------------------
-
-   The TI C3x compiler has a rather unusual register passing algorithm.
-   Data is passed in the following registers (in order):
-
-   AR2, R2, R3, RC, RS, RE
-
-   However, the first and second floating point values are always in R2
-   and R3 (and all other floats are on the stack).  Structs are always
-   passed on the stack.  If the last argument is an ellipsis, the
-   previous argument is passed on the stack so that its address can be
-   taken for the stdargs macros.
-
-   Because of this, we have to pre-scan the list of arguments to figure
-   out what goes where in the list.
-
-   II. Routine calling with arguments on stack
-   -------------------------------------------
-
-   Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
-   variables loc0, loc1, and loc2.  After the function prologue has
-   been executed, the stack frame will look like:
-
-   [stack grows towards increasing addresses]
-       I-------------I
-   5   I saved reg1  I  <= SP points here
-       I-------------I
-   4   I saved reg0  I  
-       I-------------I
-   3   I       loc2  I  
-       I-------------I  
-   2   I       loc1  I  
-       I-------------I  
-   1   I       loc0  I  
-       I-------------I
-   0   I     old FP  I <= FP (AR3) points here
-       I-------------I
-   -1  I  return PC  I
-       I-------------I
-   -2  I       arg0  I  
-       I-------------I  
-   -3  I       arg1  I
-       I-------------I  
-   -4  I       arg2  I 
-       I-------------I  
-
-   All local variables (locn) are accessible by means of +FP(n+1)
-   addressing, where n is the local variable number.
-
-   All stack arguments (argn) are accessible by means of -FP(n-2).
-
-   The stack pointer (SP) points to the last register saved in the
-   prologue (regn).
-
-   Note that a push instruction performs a preincrement of the stack
-   pointer.  (STACK_PUSH_CODE == PRE_INC)
-
-   III. Registers used in function calling convention
-   --------------------------------------------------
-
-   Preserved across calls: R4...R5 (only by PUSH,  i.e. lower 32 bits)
-   R6...R7 (only by PUSHF, i.e. upper 32 bits)
-   AR3...AR7
-
-   (Because of this model, we only assign FP values in R6, R7 and
-   only assign integer values in R4, R5.)
-
-   These registers are saved at each function entry and restored at
-   the exit. Also it is expected any of these not affected by any
-   call to user-defined (not service) functions.
-
-   Not preserved across calls: R0...R3
-   R4...R5 (upper 8 bits)
-   R6...R7 (lower 8 bits)
-   AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
-
-   These registers are used arbitrary in a function without being preserved.
-   It is also expected that any of these can be clobbered by any call.
-
-   Not used by GCC (except for in user "asm" statements):
-   IE (DIE), IF (IIE), IOF (IIF)
-
-   These registers are never used by GCC for any data, but can be used
-   with "asm" statements.  */
-
-#define C4X_ARG0 -2
-#define C4X_LOC0 1
-
-/* Basic Stack Layout  */
-     
-/* The stack grows upward, stack frame grows upward, and args grow
-   downward. */
-
-#define STARTING_FRAME_OFFSET		C4X_LOC0
-#define FIRST_PARM_OFFSET(FNDECL)      (C4X_ARG0 + 1)
-#define ARGS_GROW_DOWNWARD
-#define STACK_POINTER_OFFSET 1
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-
-/* #define STACK_GROWS_DOWNWARD */
-/* Like the dsp16xx, i370, i960, and we32k ports */
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-
-/* #define FRAME_GROWS_DOWNWARD */
-
-
-/* Registers That Address the Stack Frame  */
-
-#define STACK_POINTER_REGNUM	SP_REGNO	/* SP */
-#define FRAME_POINTER_REGNUM	AR3_REGNO	/* AR3 */
-#define ARG_POINTER_REGNUM	AR3_REGNO	/* AR3 */
-#define STATIC_CHAIN_REGNUM	AR0_REGNO	/* AR0 */
-
-/* Eliminating Frame Pointer and Arg Pointer  */
-
-#define FRAME_POINTER_REQUIRED	0
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)			\
-{								\
- int regno;							\
- int offset = 0;						\
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)	\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      offset += TARGET_PRESERVE_FLOAT				\
-		&& ((regno == R6_REGNO) || (regno == R7_REGNO)) \
-		? 2 : 1;					\
-  (DEPTH) = -(offset + get_frame_size ());			\
-}
-
-/* This is a hack... We need to specify a register.  */
-#define	ELIMINABLE_REGS 					\
-  {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
-
-#define	CAN_ELIMINATE(FROM, TO)					\
-  (! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
-  || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)	 	\
-{								\
- int regno;							\
- int offset = 0;						\
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)	\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      offset += TARGET_PRESERVE_FLOAT				\
-		&& ((regno == R6_REGNO) || (regno == R7_REGNO)) \
-		? 2 : 1;					\
-  (OFFSET) = -(offset + get_frame_size ());			\
-}
-
-
-/* Passing Function Arguments on the Stack  */
-
-#if 0
-#define PUSH_ROUNDING(BYTES) (BYTES)
-#endif
-#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
-
-/* The following structure is used by calls.c, function.c, c4x.c  */
-
-typedef struct c4x_args
-{
-  int floats;
-  int ints;
-  int maxfloats;
-  int maxints;
-  int init;
-  int var;
-  int prototype;
-  int args;
-}
-CUMULATIVE_ARGS;
-
-extern void c4x_init_cumulative_args();
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
-  (c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
-
-extern void c4x_function_arg_advance();
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
-  (c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
-
-extern struct rtx_def *c4x_function_arg();
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  (c4x_function_arg(&CUM, MODE, TYPE, NAMED))
-
-/* Define the profitability of saving registers around calls.
-   NOTE: For now we turn this off because caller-save assumes
-   that a register with a QFmode quantity can be saved/restored
-   using QImode.  */
-
-/* #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0 */
-
-/* Never pass data by reference.  */
-
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
-/* 1 if N is a possible register number for function argument passing. */
-
-#define FUNCTION_ARG_REGNO_P(REGNO) \
-	(  (   ((REGNO) == AR2_REGNO)	/* AR2 */	\
-	    || ((REGNO) == R2_REGNO)	/* R2 */	\
-	    || ((REGNO) == R3_REGNO)	/* R3 */	\
-	    || ((REGNO) == RC_REGNO)	/* RC */	\
-	    || ((REGNO) == RS_REGNO)	/* RS */	\
-	    || ((REGNO) == RE_REGNO))	/* RE */	\
-	 ? 1						\
-	 : 0)
-
-/* How Scalar Function Values Are Returned  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-	gen_rtx(REG, TYPE_MODE(VALTYPE), R0_REGNO)	/* Return in R0 */
-
-#define LIBCALL_VALUE(MODE) \
-	gen_rtx(REG, MODE, R0_REGNO)	/* Return in R0 */
-
-#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
-
-/* How Large Values Are Returned  */
-
-#define DEFAULT_PCC_STRUCT_RETURN	0
-#define STRUCT_VALUE_REGNUM		AR0_REGNO	/* AR0 */
-
-
-/* Function Entry and Exit  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)	c4x_function_prologue(FILE, SIZE)
-#define FUNCTION_EPILOGUE(FILE, SIZE)	c4x_function_epilogue(FILE, SIZE)
-
-
-/* Generating Code for Profiling  */
-
-/* Note that the generated assembly uses the ^ operator to load the 16
-   MSBs of the address.  This is not supported by the TI assembler.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) 			\
-     if (! TARGET_C3X)						\
-     {								\
-	fprintf (FILE, "\tpush\tar2\n");			\
-	fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO));	\
-	fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO));		\
-	fprintf (FILE, "\tcall\tmcount\n");			\
-	fprintf (FILE, "\tpop\tar2\n");				\
-     }								\
-     else							\
-     {								\
-	fprintf (FILE, "\tpush\tar2\n");			\
-	fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO));	\
-	fprintf (FILE, "\tlsh\t16,ar2\n");			\
-	fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO));		\
-	fprintf (FILE, "\tcall\tmcount\n");			\
-	fprintf (FILE, "\tpop\tar2\n");				\
-     }
-
-/* There are three profiling modes for basic blocks available.
-   The modes are selected at compile time by using the options
-   -a or -ax of the gnu compiler.
-   The variable `profile_block_flag' will be set according to the
-   selected option.
-
-   profile_block_flag == 0, no option used:
-
-      No profiling done.
-
-   profile_block_flag == 1, -a option used.
-
-      Count frequency of execution of every basic block.
-
-   profile_block_flag == 2, -ax option used.
-
-      Generate code to allow several different profiling modes at run time. 
-      Available modes are:
-             Produce a trace of all basic blocks.
-             Count frequency of jump instructions executed.
-      In every mode it is possible to start profiling upon entering
-      certain functions and to disable profiling of some other functions.
-
-    The result of basic-block profiling will be written to a file `bb.out'.
-    If the -ax option is used parameters for the profiling will be read
-    from file `bb.in'.
-
-*/
-
-#define FUNCTION_BLOCK_PROFILER(FILE, BLOCKNO) 			\
-  if (profile_block_flag == 2)					\
-    {								\
-      if (! TARGET_C3X)						\
-      {								\
-	fprintf (FILE, "\tpush\tst\n");				\
-	fprintf (FILE, "\tpush\tar2\n");			\
-	fprintf (FILE, "\tpush\tr2\n");				\
-	fprintf (FILE, "\tldhi\t^LPBX0,ar2\n");			\
-	fprintf (FILE, "\tor\t#LPBX0,ar2\n");			\
-	if (BLOCKNO > 32767)					\
-	  {							\
-	    fprintf (FILE, "\tldhi\t%d,r2\n", (BLOCKNO) >> 16);	\
-	    fprintf (FILE, "\tor\t%d,r2\n", (BLOCKNO));		\
-	  }							\
- 	else							\
-	  {							\
-	    fprintf (FILE, "\tldiu\t%d,r2\n", (BLOCKNO));	\
-	  }							\
-	fprintf (FILE, "\tcall\t___bb_init_trace_func\n");	\
-	fprintf (FILE, "\tpop\tr2\n");				\
-	fprintf (FILE, "\tpop\tar2\n");				\
-	fprintf (FILE, "\tpop\tst\n");				\
-      }								\
-      else							\
-      {								\
-	fprintf (FILE, "\tpush\tst\n");				\
-	fprintf (FILE, "\tpush\tar2\n");			\
-	fprintf (FILE, "\tpush\tr2\n");				\
-	fprintf (FILE, "\tldiu\t^LPBX0,ar2\n");			\
-	fprintf (FILE, "\tlsh\t16,ar2\n");			\
-	fprintf (FILE, "\tor\t#LPBX0,ar2\n");			\
-	if (BLOCKNO > 32767)					\
-	  {							\
-	    fprintf (FILE, "\tldi\t%d,r2\n", (BLOCKNO) >> 16);	\
-	    fprintf (FILE, "\tlsh\t16,r2\n");			\
-	    fprintf (FILE, "\tor\t%d,r2\n", (BLOCKNO));		\
-	  }							\
- 	else							\
-	  {							\
-	    fprintf (FILE, "\tldiu\t%d,r2\n", (BLOCKNO));	\
-	  }							\
-	fprintf (FILE, "\tcall\t___bb_init_trace_func\n");	\
-	fprintf (FILE, "\tpop\tr2\n");				\
-	fprintf (FILE, "\tpop\tar2\n");				\
-	fprintf (FILE, "\tpop\tst\n");				\
-      }								\
-    }								\
-  else								\
-    {								\
-      if (! TARGET_C3X)						\
-      {								\
-	fprintf (FILE, "\tpush\tst\n");				\
-	fprintf (FILE, "\tpush\tar2\n");			\
-	fprintf (FILE, "\tldhi\t^LPBX0,ar2\n");			\
-	fprintf (FILE, "\tor\t#LPBX0,ar2\n");			\
-	fprintf (FILE, "\tcmpi\t0,*ar2\n");			\
-	fprintf (FILE, "\tbne\t$+2\n");				\
-	fprintf (FILE, "\tcall\t___bb_init_func\n");		\
-	fprintf (FILE, "\tpop\tar2\n");				\
-	fprintf (FILE, "\tpop\tst\n");				\
-      }								\
-      else							\
-      {								\
-	fprintf (FILE, "\tpush\tst\n");				\
-	fprintf (FILE, "\tpush\tar2\n");			\
-	fprintf (FILE, "\tpush\tr2\n");				\
-	fprintf (FILE, "\tldiu\t^LPBX0,ar2\n");			\
-	fprintf (FILE, "\tlsh\t16,ar2\n");			\
-	fprintf (FILE, "\tor\t#LPBX0,ar2\n");			\
-	fprintf (FILE, "\tldi\t*ar2,r2\n");			\
-	fprintf (FILE, "\tbne\t$+2\n");				\
-	fprintf (FILE, "\tcall\t___bb_init_func\n");		\
-	fprintf (FILE, "\tpop\tr2\n");				\
-	fprintf (FILE, "\tpop\tar2\n");				\
-	fprintf (FILE, "\tpop\tst\n");				\
-      }								\
-    }
-
-#define BLOCK_PROFILER(FILE, BLOCKNO) 				\
-  if (profile_block_flag == 2)					\
-    {								\
-      if (! TARGET_C3X)						\
-      {								\
-	fprintf (FILE, "\tpush\tst\n");				\
-	fprintf (FILE, "\tpush\tar2\n");			\
-	fprintf (FILE, "\tpush\tar0\n");			\
-	fprintf (FILE, "\tldhi\t^___bb,ar2\n");			\
-	fprintf (FILE, "\tor\t#___bb,ar2\n");			\
-	if (BLOCKNO > 32767)					\
-	  {							\
-	    fprintf (FILE, "\tldhi\t%d,ar0\n", (BLOCKNO) >> 16);\
-	    fprintf (FILE, "\tor\t%d,ar0\n", (BLOCKNO));	\
-	  }							\
- 	else							\
-	  {							\
-	    fprintf (FILE, "\tldiu\t%d,ar0\n", (BLOCKNO));	\
-	  }							\
-	fprintf (FILE, "\tsti\tar0,*ar2\n");			\
-	fprintf (FILE, "\tldhi\t^LPBX0,ar0\n");			\
-	fprintf (FILE, "\tor\t#LPBX0,ar0\n");			\
-	fprintf (FILE, "\tsti\tar0,*+ar2(1)\n");		\
-	fprintf (FILE, "\tcall\t___bb_trace_func\n");		\
-	fprintf (FILE, "\tpop\tar0\n");				\
-        fprintf (FILE, "\tpop\tar2\n");				\
-	fprintf (FILE, "\tpop\tst\n");				\
-      }								\
-      else							\
-      {								\
-	fprintf (FILE, "\tpush\tst\n");				\
-	fprintf (FILE, "\tpush\tar2\n");			\
-	fprintf (FILE, "\tpush\tar0\n");			\
-	fprintf (FILE, "\tldiu\t^___bb,ar2\n");			\
-	fprintf (FILE, "\tlsh\t16,ar2\n");			\
-	fprintf (FILE, "\tor\t#___bb,ar2\n");			\
-	if (BLOCKNO > 32767)					\
-	  {							\
-	    fprintf (FILE, "\tldi\t%d,ar0\n", (BLOCKNO) >> 16);	\
-	    fprintf (FILE, "\tlsh\t16,ar0\n");			\
-	    fprintf (FILE, "\tor\t%d,ar0\n", (BLOCKNO));	\
-	  }							\
- 	else							\
-	  {							\
-	    fprintf (FILE, "\tldiu\t%d,ar0\n", (BLOCKNO));	\
-	  }							\
-	fprintf (FILE, "\tsti\tar0,*ar2\n");			\
-	fprintf (FILE, "\tldiu\t^LPBX0,ar0\n");			\
-	fprintf (FILE, "\tlsh\t16,ar0\n");			\
-	fprintf (FILE, "\tor\t#LPBX0,ar0\n");			\
-	fprintf (FILE, "\tsti\tar0,*+ar2(1)\n");		\
-	fprintf (FILE, "\tcall\t___bb_trace_func\n");		\
-	fprintf (FILE, "\tpop\tar0\n");				\
-        fprintf (FILE, "\tpop\tar2\n");				\
-	fprintf (FILE, "\tpop\tst\n");				\
-      }								\
-    }								\
-  else								\
-    {								\
-      if (! TARGET_C3X)						\
-      {								\
-	fprintf (FILE, "\tpush\tar2\n");			\
-	fprintf (FILE, "\tpush\tar0\n");			\
-	fprintf (FILE, "\tldhi\t^LPBX2+%d,ar2\n", (BLOCKNO));	\
-	fprintf (FILE, "\tor\t#LPBX2+%d,ar2\n", (BLOCKNO));	\
-	fprintf (FILE, "\taddi3\t1,*ar2,ar0\n");		\
-	fprintf (FILE, "\tsti\tar0,*ar2\n");			\
-	fprintf (FILE, "\tpop\tar0\n");				\
-        fprintf (FILE, "\tpop\tar2\n");				\
-      }								\
-      else							\
-      {								\
-	fprintf (FILE, "\tpush\tar2\n");			\
-	fprintf (FILE, "\tpush\tar0\n");			\
-	fprintf (FILE, "\tldiu\t^LPBX2+%d,ar2\n", (BLOCKNO));	\
-	fprintf (FILE, "\tlsh\t16,ar2\n");			\
-	fprintf (FILE, "\tor\t#LPBX2+%d,ar2\n", (BLOCKNO));	\
-	fprintf (FILE, "\tldiu\t*ar2,ar0\n");			\
-	fprintf (FILE, "\taddi\t1,ar0\n");			\
-	fprintf (FILE, "\tsti\tar0,*ar2\n");			\
-	fprintf (FILE, "\tpop\tar0\n");				\
-        fprintf (FILE, "\tpop\tar2\n");				\
-      }								\
-    }
-
-#define FUNCTION_BLOCK_PROFILER_EXIT(FILE)			\
-    {								\
-	fprintf (FILE, "\tpush\tst\n");				\
-	fprintf (FILE, "\tpush\tar2\n");			\
-	fprintf (FILE, "\tcall\t___bb_trace_ret\n");		\
-	fprintf (FILE, "\tpop\tar2\n");				\
-	fprintf (FILE, "\tpop\tst\n");				\
-    }
-
-#define	MACHINE_STATE_SAVE(ID)		\
-	asm("	push	r0");		\
-	asm("	pushf	r0");		\
-	asm("	push	r1");		\
-	asm("	pushf	r1");		\
-	asm("	push	r2");		\
-	asm("	pushf	r2");		\
-	asm("	push	r3");		\
-	asm("	pushf	r3");		\
-	asm("	push	ar0");		\
-	asm("	push	ar1");		\
-	asm("	.if	.BIGMODEL");	\
-	asm("	push	dp");		\
-	asm("	.endif");		\
-	asm("	push	ir0");		\
-	asm("	push	ir1");		\
-	asm("	push	bk");		\
-	asm("	push	rs");		\
-	asm("	push	re");		\
-	asm("	push	rc");		\
-	asm("	.if	.tms320C40");	\
-	asm("	push	r9");		\
-	asm("	pushf	r9");		\
-	asm("	push	r10");		\
-	asm("	pushf	r10");		\
-	asm("	push	r11");		\
-	asm("	pushf	r11");		\
-	asm("	.endif");
-
-#define	MACHINE_STATE_RESTORE(ID)	\
-	asm("	.if	.tms320C40");	\
-	asm("	popf	r11");		\
-	asm("	pop	r11");		\
-	asm("	popf	r10");		\
-	asm("	pop	r10");		\
-	asm("	popf	r9");		\
-	asm("	pop	r9");		\
-	asm("	.endif");		\
-	asm("	pop	rc");		\
-	asm("	pop	re");		\
-	asm("	pop	rs");		\
-	asm("	pop	bk");		\
-	asm("	pop	ir1");		\
-	asm("	pop	ir0");		\
-	asm("	.if	.BIGMODEL");	\
-	asm("	pop	dp");		\
-	asm("	.endif");		\
-	asm("	pop	ar1");		\
-	asm("	pop	ar0");		\
-	asm("	popf	r3");		\
-	asm("	pop	r3");		\
-	asm("	popf	r2");		\
-	asm("	pop	r2");		\
-	asm("	popf	r1");		\
-	asm("	pop	r1");		\
-	asm("	popf	r0");		\
-	asm("	pop	r0");		\
-
-/* Implicit Calls to Library Routines  */
-
-#define MULQI3_LIBCALL      "__mulqi3"
-#define DIVQI3_LIBCALL      "__divqi3"
-#define UDIVQI3_LIBCALL     "__udivqi3"
-#define MODQI3_LIBCALL      "__modqi3"
-#define UMODQI3_LIBCALL     "__umodqi3"
-
-#define DIVQF3_LIBCALL      "__divqf3"
-
-#define MULHF3_LIBCALL      "__mulhf3"
-#define DIVHF3_LIBCALL      "__divhf3"
-
-#define MULHI3_LIBCALL      "__mulhi3"
-#define SMULHI3_LIBCALL     "__smulhi3_high"
-#define UMULHI3_LIBCALL     "__umulhi3_high"
-#define DIVHI3_LIBCALL      "__divhi3"
-#define UDIVHI3_LIBCALL     "__udivhi3"
-#define MODHI3_LIBCALL      "__modhi3"
-#define UMODHI3_LIBCALL     "__umodhi3"
-
-#define FLOATHIQF2_LIBCALL  "__floathiqf2"
-#define FLOATUNSHIQF2_LIBCALL  "__ufloathiqf2"
-#define FIX_TRUNCQFHI2_LIBCALL "__fix_truncqfhi2"
-#define FIXUNS_TRUNCQFHI2_LIBCALL "__ufix_truncqfhi2"
-
-#define FLOATHIHF2_LIBCALL  "__floathihf2"
-#define FLOATUNSHIHF2_LIBCALL  "__ufloathihf2"
-#define FIX_TRUNCHFHI2_LIBCALL "__fix_trunchfhi2"
-#define FIXUNS_TRUNCHFHI2_LIBCALL "__ufix_trunchfhi2"
-
-#define FFS_LIBCALL	    "__ffs"
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Add any extra modes needed to represent the condition code.
-
-   On the C4x, we have a "no-overflow" mode which is used when an ADD,
-   SUB, NEG, or MPY insn is used to set the condition code.  This is
-   to prevent the combiner from optimising away a following CMP of the
-   result with zero when a signed conditional branch or load insn
-   follows.
-
-   The problem is a subtle one and deals with the manner in which the
-   negative condition (N) flag is used on the C4x.  This flag does not
-   reflect the status of the actual result but of the ideal result had
-   no overflow occured (when considering signed operands).
-
-   For example, 0x7fffffff + 1 => 0x80000000 Z=0 V=1 N=0 C=0.  Here
-   the flags reflect the untruncated result, not the actual result.
-   While the actual result is less than zero, the N flag is not set
-   since the ideal result of the addition without truncation would
-   have been positive.
-   
-   Note that the while the N flag is handled differently to most other
-   architectures, the use of it is self consistent and is not the
-   cause of the problem.
-
-   Logical operations set the N flag to the MSB of the result so if
-   the result is negative, N is 1.  However, integer and floating
-   point operations set the N flag to be the MSB of the result
-   exclusive ored with the overflow (V) flag.  Thus if an overflow
-   occurs and the result does not have the MSB set (i.e., the result
-   looks like a positive number), the N flag is set.  Conversely, if
-   an overflow occurs and the MSB of the result is set, N is set to 0.
-   Thus the N flag represents the sign of the result if it could have
-   been stored without overflow but does not represent the apparent
-   sign of the result.  Note that most architectures set the N flag to
-   be the MSB of the result.
-
-   The C4x approach to setting the N flag simplifies signed
-   conditional branches and loads which only have to test the state of
-   the N flag, whereas most architectures have to look at both the N
-   and V flags.  The disadvantage is that there is no flag giving the
-   status of the sign bit of the operation.  However, there are no
-   conditional load or branch instructions that make use of this
-   feature (e.g., BMI---branch minus) instruction.  Note that BN and
-   BLT are identical in the C4x.
-   
-   To handle the problem where the N flag is set differently whenever
-   there is an overflow we use a different CC mode, CC_NOOVmode which
-   says that the CC reflects the comparison of the result against zero
-   if no overflow occured.
-
-   For example, 
-
-   [(set (reg:CC_NOOV 21)
-         (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "")
-                                    (match_operand:QI 2 "src_operand" ""))
-                          (const_int 0)))
-    (set (match_operand:QI 0 "ext_reg_operand" "")
-         (minus:QI (match_dup 1)
-                   (match_dup 2)))]
-
-   Note that there is no problem for insns that don't return a result
-   like CMP, since the CC reflects the effect of operation.
-
-   An example of a potential problem is when GCC
-   converts   (LTU (MINUS (0x80000000) (0x7fffffff) (0x80000000)))
-   to         (LEU (MINUS (0x80000000) (0x7fffffff) (0x7fffffff)))
-   to         (GE  (MINUS (0x80000000) (0x7fffffff) (0x00000000)))
-
-   Now (MINUS (0x80000000) (0x7fffffff)) returns 0x00000001 but the
-   C4x sets the N flag since the result without overflow would have
-   been 0xffffffff when treating the operands as signed integers.
-   Thus (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000))) sets the N
-   flag but (GE (0x00000001)) does not set the N flag.
-
-   The upshot is that we can not use signed branch and conditional
-   load instructions after an add, subtract, neg, abs or multiply.
-   We must emit a compare insn to check the result against 0.  */
-
-#define EXTRA_CC_MODES CC_NOOVmode
-
-/* Define the names for the modes specified above.  */
-
-#define EXTRA_CC_NAMES "CC_NOOV"
-
-/* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
-   or MULT.
-   CCmode should be used when no special processing is needed. */
-#define SELECT_CC_MODE(OP,X,Y) \
-  ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS		\
-    || GET_CODE (X) == NEG || GET_CODE (X) == MULT		\
-    || GET_MODE (X) == ABS					\
-    || GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS		\
-    || GET_CODE (Y) == NEG || GET_CODE (Y) == MULT		\
-    || GET_MODE (Y) == ABS)					\
-    ? CC_NOOVmode : CCmode)
-
-extern struct rtx_def *c4x_gen_compare_reg ();
-
-/* Addressing Modes  */
-
-#define HAVE_POST_INCREMENT 1
-#define HAVE_PRE_INCREMENT 1
-#define HAVE_POST_DECREMENT 1
-#define HAVE_PRE_DECREMENT 1
-#define HAVE_PRE_MODIFY_REG 1
-#define HAVE_POST_MODIFY_REG 1
-#define HAVE_PRE_MODIFY_DISP 1
-#define HAVE_POST_MODIFY_DISP 1
-
-#define HAVE_MULTIPLE_PACK 2
-
-/* What about LABEL_REF?  */
-#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
-
-#define MAX_REGS_PER_ADDRESS	2
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-extern int c4x_check_legit_addr ();
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard or pseudo reg that can be used as an base.  */
-
-#define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(REGNO(X))
-
-/* Nonzero if X is a hard or pseudo reg that can be used as an index.  */
-
-#define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(REGNO(X))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-{									\
-  if (c4x_check_legit_addr (MODE, X, 0))				\
-    goto ADDR;								\
-}
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-{									\
-  if (c4x_check_legit_addr (MODE, X, 1))				\
-    goto ADDR;								\
-}
-
-#endif
-
-extern struct rtx_def *c4x_legitimize_address ();
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
-{									\
-  rtx new;								\
-  new = c4x_legitimize_address (X, MODE);				\
-  if (new != NULL_RTX)							\
-  {									\
-    (X) = new;								\
-    goto WIN;								\
-  }									\
-}
-
-
-/* No mode-dependent addresses on the C4x are autoincrements.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)	\
-  if (GET_CODE (ADDR) == PRE_DEC	\
-      || GET_CODE (ADDR) == POST_DEC	\
-      || GET_CODE (ADDR) == PRE_INC	\
-      || GET_CODE (ADDR) == POST_INC	\
-      || GET_CODE (ADDR) == POST_MODIFY	\
-      || GET_CODE (ADDR) == PRE_MODIFY)	\
-    goto LABEL
-
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 
-
-   The C4x can only load 16-bit immediate values, so we only allow
-   a restricted subset of CONST_INT and CONST_DOUBLE and reject
-   LABEL_REF, SYMBOL_REF, CONST, and HIGH codes.  */
-
-#define LEGITIMATE_CONSTANT_P(X)				\
-  ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X))		\
-  || (GET_CODE (X) == CONST_INT && c4x_I_constant (X)))
-
-
-#define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
-
-/* Descripting Relative Cost of Operations  */
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE. 
-
-   Note that we return, rather than break so that rtx_cost doesn't
-   include CONST_COSTS otherwise expand_mult will think that it is
-   cheaper to synthesise a multiply rather than to use a multiply
-   instruction.  I think this is because the algorithm synth_mult
-   doesn't take into account the loading of the operands, whereas the
-   calculation of mult_cost does. 
-*/
-
-
-#define RTX_COSTS(RTX, CODE, OUTER_CODE)				\
-    case MULT:								\
-    return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
-			  || TARGET_MPYI ? 1 : 14);			\
-    case DIV:  case UDIV: case MOD: case UMOD: 				\
-    return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT	\
-			  ? 15 : 50);
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.
-
-   An insn is assumed to cost 4 units.
-   COSTS_N_INSNS (N) is defined as (N) * 4 - 2.
-
-   Some small integers are effectively free for the C40.  We should
-   also consider if we are using the small memory model.  With
-   the big memory model we require an extra insn for a constant
-   loaded from memory.  */
-
-#define SHIFT_CODE_P(C) ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
-
-#define LOGICAL_CODE_P(C) ((C) == NOT || (C) == AND \
-                           || (C) == IOR || (C) == XOR)
-
-#define NON_COMMUTATIVE_CODE_P ((C) == MINUS || (C) == COMPARE)
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE)			\
-	case CONST_INT:						\
-           if (c4x_J_constant (RTX))				\
-	     return 0;						\
-           if (TARGET_C3X && SHIFT_CODE_P (OUTER_CODE))		\
-	     return 3;						\
-           if (LOGICAL_CODE_P (OUTER_CODE) 			\
-               ? c4x_L_constant (RTX) : c4x_I_constant (RTX))	\
-	     return 2;						\
-	case CONST:						\
-	case LABEL_REF:						\
-	case SYMBOL_REF:					\
-	   return 4;						\
-	case CONST_DOUBLE:					\
-	   if (c4x_H_constant (RTX))				\
-	     return 2;						\
-           if (GET_MODE (RTX) == QFmode)			\
-	     return 4;						\
-           else							\
-	     return 8;
-
-/* Compute the cost of an address.  This is meant to approximate the size
-   and/or execution delay of an insn using that address.  If the cost is
-   approximated by the RTL complexity, including CONST_COSTS above, as
-   is usually the case for CISC machines, this macro should not be defined.
-   For aggressively RISCy machines, only one insn format is allowed, so
-   this macro should be a constant.  The value of this macro only matters
-   for valid addresses.  We handle the most common address without 
-   a call to c4x_address_cost.  */
-
-extern int c4x_address_cost ();
-
-#define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : c4x_address_cost (ADDR))
-
-#define	CANONICALIZE_COMPARISON(CODE, OP0, OP1)		\
-if (REG_P (OP1) && ! REG_P (OP0))			\
-{							\
-  rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp;			\
-  CODE = swap_condition (CODE);				\
-}
-
-#define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
-#define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
-#define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
-#define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
-                          || INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
-
-/* Compute extra cost of moving data between one register class
-   and another.  */
-
-#define REGISTER_MOVE_COST(FROM, TO)	2
-
-/* Memory move cost is same as fast register move.  Maybe this should
-   be bumped up? */
-
-#define MEMORY_MOVE_COST(M,C,I)		4
-
-/* Branches are kind of expensive (even with delayed branching) so
-   make their cost higher.  */
-
-#define BRANCH_COST			8
-
-/* Adjust the cost of dependencies.  */
-
-#define ADJUST_COST(INSN,LINK,DEP,COST) \
-  (COST) = c4x_adjust_cost (INSN, LINK, DEP, COST)
-
-#define	WORD_REGISTER_OPERATIONS
-
-/* Dividing the Output into Sections  */
-
-#define TEXT_SECTION_ASM_OP "\t.text"
-
-#define DATA_SECTION_ASM_OP "\t.data"
-
-#define USE_CONST_SECTION 1
-
-#define CONST_SECTION_ASM_OP "\t.sect\t\".const\""
-
-/* Do not use .init section so __main will be called on startup. This will
-   call __do_global_ctors and prepare for __do_global_dtors on exit. */
-
-#if 0
-#define INIT_SECTION_ASM_OP  "\t.sect\t\".init\""
-#endif
-
-#define FINI_SECTION_ASM_OP  "\t.sect\t\".fini\""
-
-/* Support const sections and the ctors and dtors sections for g++.
-   Note that there appears to be two different ways to support const
-   sections at the moment.  You can either #define the symbol
-   READONLY_DATA_SECTION (giving it some code which switches to the
-   readonly data section) or else you can #define the symbols
-   EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
-   SELECT_RTX_SECTION.  We do both here just to be on the safe side. */
-
-/* Define a few machine-specific details of the implementation of
-   constructors.
-
-   The __CTORS_LIST__ goes in the .ctors section.  Define CTOR_LIST_BEGIN
-   and CTOR_LIST_END to contribute to the .ctors section an instruction to
-   push a word containing 0 (or some equivalent of that).
-
-   Define ASM_OUTPUT_CONSTRUCTOR to push the address of the constructor.  */
-
-#define CTORS_SECTION_ASM_OP	"\t.sect\t\".ctors\""
-#define DTORS_SECTION_ASM_OP    "\t.sect\t\".dtors\""
-
-/* Constructor list on stack is in reverse order.  Go to the end of the
-   list and go backwards to call constructors in the right order.  */
-
-#define DO_GLOBAL_CTORS_BODY					\
-do {								\
-  extern func_ptr __CTOR_LIST__[];				\
-  func_ptr *p, *beg = __CTOR_LIST__ + 1;			\
-  for (p = beg; *p ; p++) ;					\
-  while (p != beg)						\
-    (*--p) ();							\
-} while (0)
-
-/* The TI tooling uses atexit. */
-#define	HAVE_ATEXIT
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_init, in_fini, in_ctors, in_dtors
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS					\
-  CONST_SECTION_FUNCTION					\
-  INIT_SECTION_FUNCTION						\
-  FINI_SECTION_FUNCTION						\
-  CTORS_SECTION_FUNCTION					\
-  DTORS_SECTION_FUNCTION
-
-#define INIT_SECTION_FUNCTION					\
-void								\
-init_section ()							\
-{								\
-  if (in_section != in_init)					\
-    {								\
-      fprintf (asm_out_file, ";\t.init\n");			\
-      in_section = in_init;					\
-    }								\
-}
-
-#define FINI_SECTION_FUNCTION					\
-void								\
-fini_section ()							\
-{								\
-  if (in_section != in_fini)					\
-    {								\
-      fprintf (asm_out_file, "\t%s\n", FINI_SECTION_ASM_OP);	\
-      in_section = in_fini;					\
-    }								\
-}
-
-#define READONLY_DATA_SECTION() const_section ()
-
-#define CONST_SECTION_FUNCTION						\
-void									\
-const_section ()							\
-{									\
-  extern void text_section();						\
-  if (! USE_CONST_SECTION)						\
-    text_section();							\
-  else if (in_section != in_const)					\
-    {									\
-      fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP);		\
-      in_section = in_const;						\
-    }									\
-}
-
-#define ASM_STABS_OP "\t.stabs"
-
-/* The ctors and dtors sections are not normally put into use 
-   by EXTRA_SECTIONS and EXTRA_SECTION_FUNCTIONS as defined in svr3.h,
-   but it can't hurt to define these macros for whatever systems use them.  */
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
-   fprintf (FILE, "\t.sect\t\"%s\"\n", NAME);
-
-/* This is machine-dependent because it needs to push something
-   on the stack.  */
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t.word\t ");					\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t.word\t ");					\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement or statements to switch to the appropriate
-   section for output of DECL.  DECL is either a `VAR_DECL' node
-   or a constant of some sort.  RELOC indicates whether forming
-   the initial value of DECL requires link-time relocations.  */
-
-#define SELECT_SECTION(DECL, RELOC)					\
-{									\
-  if (TREE_CODE (DECL) == STRING_CST)					\
-    {									\
-      if (! flag_writable_strings)					\
-	const_section ();						\
-      else								\
-	data_section ();						\
-    }									\
-  else if (TREE_CODE (DECL) == VAR_DECL)				\
-    {									\
-      if ((0 && RELOC)	/* should be (flag_pic && RELOC) */		\
-	  || ! TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)		\
-	  || ! DECL_INITIAL (DECL)					\
-	  || (DECL_INITIAL (DECL) != error_mark_node			\
-	      && ! TREE_CONSTANT (DECL_INITIAL (DECL))))			\
-	data_section ();						\
-      else								\
-	const_section ();						\
-    }									\
-  else									\
-    const_section ();							\
-}
-
-/* A C statement or statements to switch to the appropriate
-   section for output of RTX in mode MODE.  RTX is some kind
-   of constant in RTL.  The argument MODE is redundant except
-   in the case of a `const_int' rtx.  Currently, these always
-   go into the const section.  */
-
-#define SELECT_RTX_SECTION(MODE, RTX) const_section()
-
-
-/* Overall Framework of an Assembler File  */
-
-#define ASM_FILE_START(FILE)					\
-{								\
-    int dspversion = 0;						\
-    if (TARGET_C30) dspversion = 30;				\
-    if (TARGET_C31) dspversion = 31;				\
-    if (TARGET_C32) dspversion = 32;				\
-    if (TARGET_C40) dspversion = 40;				\
-    if (TARGET_C44) dspversion = 44;				\
-    fprintf (FILE, "\t.version\t%d\n", dspversion);		\
-    fprintf (FILE, "\t.file\t");				\
-    if (TARGET_TI)						\
-      {								\
-        char *p;						\
-        char *after_dir = main_input_filename;			\
-	for (p = main_input_filename; *p; p++)			\
-	  if (*p == '/')					\
-	    after_dir = p + 1;					\
-	output_quoted_string (FILE, after_dir);			\
-      }								\
-    else							\
-      output_quoted_string (FILE, main_input_filename);		\
-    fprintf (FILE, "\n");					\
-}
-
-#define ASM_FILE_END(FILE)   fprintf (FILE, "\t.end\n")
-
-/* We need to have a data section we can identify so that we can set
-   the DP register back to a data pointer in the small memory model.
-   This is only required for ISRs if we are paranoid that someone
-   may have quietly changed this register on the sly. */
-
-#define ASM_IDENTIFY_GCC(FILE) \
-    if (! TARGET_TI) fputs ("gcc2_compiled.:\n", FILE);	\
-      fputs ("\t.data\ndata_sec:\n", FILE);
-
-#define ASM_COMMENT_START	";"
-
-#define ASM_APP_ON ""
-#define ASM_APP_OFF ""
-
-/* Output float/double constants  QFmode.  */
-
-#define ASM_OUTPUT_BYTE_FLOAT(FILE, VALUE)		\
-{   long l;						\
-    char str[30];					\
-    REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-    REAL_VALUE_TO_DECIMAL (VALUE, "%20lf", str);	\
-    if (sizeof (int) == sizeof (long))			\
-      fprintf (FILE, "\t.word\t0%08xh\t; %s\n", l, str);\
-    else						\
-      fprintf (FILE, "\t.word\t0%08lxh\t; %s\n", l, str);\
-}
-
-/* Output long double constants  HFmode. 
-   The first word contains the exponent and first part of the mantissa
-   in the same manner as QFmode.  The second word contains the full
-   mantissa.  We should ensure that the two words are allocated within
-   the same page for the large memory model since we only output a single
-   LDP instruction.  FIXME.  The simplest solution probably is to output
-   a LDP for each load.  */
-
-#define ASM_OUTPUT_SHORT_FLOAT(FILE, VALUE)		\
-{   long l[2];						\
-    char str[30];					\
-    REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l);		\
-    REAL_VALUE_TO_DECIMAL (VALUE, "%20lf", str);	\
-    l[1] = (l[0] << 8) | ((l[1] >> 24) & 0xff);		\
-    if (sizeof (int) == sizeof (long))			\
-      fprintf (FILE, "\t.word\t0%08xh\t; %s\n\t.word\t0%08xh\n", \
-               l[0], str, l[1]);				\
-    else							\
-      fprintf (FILE, "\t.word\t0%08lxh\t; %s\n\t.word\t0%08lxh\n", \
-               l[0], str, l[1]);				\
-}
-
-#define ASM_OUTPUT_CHAR(FILE, VALUE)			\
-{    fprintf (FILE, "\t.word\t");			\
-     output_addr_const (FILE, VALUE);			\
-     if (GET_CODE (VALUE) != SYMBOL_REF)		\
-       fprintf (FILE, " ; 0%08xh\n", INTVAL (VALUE));	\
-     else						\
-       fputc ('\n', FILE);				\
-}
-
-#define ASM_OUTPUT_BYTE(FILE, VALUE)  \
-  fprintf (FILE, "\t.word\t0%xh\n", (VALUE))
-
-extern void c4x_output_ascii ();
-#define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-
-/* Output and Generation of Labels  */
-
-#define NO_DOT_IN_LABEL		/* Only required for TI format */
-
-#define ASM_OUTPUT_LABEL(FILE, NAME)	\
-{ assemble_name (FILE, NAME); fputs (":\n", FILE); }
-
-#define ASM_GLOBALIZE_LABEL(FILE, NAME) \
-{                                       \
-    fprintf (FILE, "\t.global\t");	\
-    assemble_name (FILE, NAME);		\
-    fputs ("\n", FILE); 	        \
-}
-
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)	\
-{                                            	\
-    fprintf (FILE, "\t.ref\t");			\
-    assemble_name (FILE, NAME);	             	\
-    fputc ('\n', FILE);  	               	\
-}
-
-/* A C statement to output on FILE an assembler pseudo-op to
-   declare a library function named external.
-   (Only needed to keep asm30 happy for ___divqf3 etc.) */
-
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN)  \
-{						\
-    fprintf (FILE, "\t.ref\t");			\
-    assemble_name (FILE, XSTR (FUN, 0));	\
-    fprintf (FILE, "\n");			\
-}
-
-/* The prefix to add to user-visible assembler symbols.  */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM)	\
-asm_fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
-    sprintf (BUFFER, "*%s%d", PREFIX, NUM)
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)  \
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),    \
-  sprintf ((OUTPUT), "%s%d", (NAME), (LABELNO)))
-
-
-/* Output of Dispatch Tables  */
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-    fprintf (FILE, "\t.long\tL%d\n", VALUE);
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-    fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 32
-
-#define INT_TYPE_SIZE		32
-#define LONG_LONG_TYPE_SIZE	64
-#define FLOAT_TYPE_SIZE		32
-#define DOUBLE_TYPE_SIZE	32
-#define LONG_DOUBLE_TYPE_SIZE	64 /* actually only 40 */
-
-/* Allow #sccs in preprocessor.  */
-
-#define SCCS_DIRECTIVE
-
-/* Output #ident as a .ident.  */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-
-#define CPP_PREDEFINES ""
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\t.bss\t", FILE),			\
-  assemble_name (FILE, (NAME)),		\
-  fprintf (FILE, ",%u\n", (ROUNDED)))
-
-/* Output of Uninitialized Variables  */
-
-#undef ASM_OUTPUT_COMMON
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-(  fputs ("\t.globl\t", FILE),	\
-   assemble_name (FILE, (NAME)),	\
-   fputs ("\n\t.bss\t", FILE),	\
-   assemble_name (FILE, (NAME)),	\
-   fprintf (FILE, ",%u\n", (ROUNDED)))
-
-/* Macros Controlling Initialization Routines  */
-
-#define OBJECT_FORMAT_COFF
-#define REAL_NM_FILE_NAME "c4x-nm"
-
-/* Output of Assembler Instructions  */
-
-/* Register names when used for integer modes.  */
-
-#define REGISTER_NAMES \
-{								\
- "r0",   "r1", "r2",   "r3",  "r4",  "r5",  "r6",  "r7",	\
- "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7",	\
- "dp",  "ir0", "ir1",  "bk",  "sp",  "st", "die", "iie",	\
- "iif",	 "rs",  "re",  "rc",  "r8",  "r9", "r10", "r11"		\
-}
-
-/* Alternate register names when used for floating point modes.  */
-
-#define FLOAT_REGISTER_NAMES \
-{								\
- "f0",   "f1", "f2",   "f3",  "f4",  "f5",  "f6",  "f7",	\
- "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7",	\
- "dp",  "ir0", "ir1",  "bk",  "sp",  "st", "die", "iie",	\
- "iif",	 "rs",  "re",  "rc",  "f8",  "f9", "f10", "f11"		\
-}
-
-
-extern void c4x_print_operand ();
-#define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
-
-/* Determine which codes are valid without a following integer.  These must
-   not be alphabetic. */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
-
-extern void c4x_print_operand_address ();
-#define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
-
-/* Define this macro if you want to implement any pragmas.  If defined, it
-   should be a C expression to be executed when #pragma is seen.  The
-   argument STREAM is the stdio input stream from which the source
-   text can be read.  CH is the first character after the #pragma.  The
-   result of the expression is the terminating character found
-   (newline or EOF).  */
-extern int c4x_handle_pragma ();
-#define HANDLE_PRAGMA(GETC, UNGETC, NAME) \
-  c4x_handle_pragma (GETC, UNGETC, NAME)
-
-extern void c4x_set_default_attributes ();
-#define SET_DEFAULT_DECL_ATTRIBUTES(DECL, ATTRIBUTES) \
-  c4x_set_default_attributes (DECL, &ATTRIBUTES)
-
-extern int c4x_valid_type_attribute_p ();
-#define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
-  (c4x_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
-
-/* Assembler Commands for Alignment  */
-
-#define ASM_OUTPUT_SKIP(FILE, SIZE) \
-{ int c = SIZE; \
-  for (; c > 0; --c) \
-   fprintf (FILE,"\t.word\t0\n"); \
-}
-
-#define ASM_NO_SKIP_IN_TEXT 1
-
-/* I'm not sure about this one.  FIXME. */
-
-#define ASM_OUTPUT_ALIGN(FILE, LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
-
-
-/* Macros for SDB and DWARF Output  (use .sdef instead of .def
-   to avoid conflict with TI's use of .def)  */
-
-#define SDB_DELIM "\n"
-#define SDB_DEBUGGING_INFO
-
-#define PUT_SDB_DEF(A)				\
-do { fprintf (asm_out_file, "\t.sdef\t");	\
-     ASM_OUTPUT_LABELREF (asm_out_file, A); 	\
-     fprintf (asm_out_file, SDB_DELIM); } while (0)
-
-#define PUT_SDB_PLAIN_DEF(A)			\
-  fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
-
-#define PUT_SDB_BLOCK_START(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_BLOCK_END(LINE)			\
-  fprintf (asm_out_file,			\
-	   "\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_FUNCTION_START(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_FUNCTION_END(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_EPILOGUE_END(NAME)			\
-do { fprintf (asm_out_file, "\t.sdef\t");		\
-     ASM_OUTPUT_LABELREF (asm_out_file, NAME);		\
-     fprintf (asm_out_file,				\
-	      "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n",	\
-	      SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
-
-
-/* Define results of standard character escape sequences.  */
-
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-
-#define DEFAULT_SIGNED_CHAR 1
-
-/* A function address in a call instruction is a byte address (for
-   indexing purposes) so give the MEM rtx a byte's mode.  */
-
-#define FUNCTION_MODE QImode
-
-#define SLOW_BYTE_ACCESS 0
-
-/* Specify the machine mode that pointers have.  After generation of
-   RTL, the compiler makes no further distinction between pointers and
-   any other objects of this machine mode.  */
-
-#define Pmode QImode
-
-/* On the C4x we can write the following code. We have to clear the cache
-   every time we execute it because the data in the stack could change.
-
-   laj   $+4
-   addi3 4,r11,ar0
-   lda   *ar0,ar1
-   lda   *+ar0(1),ar0
-   bud   ar1
-   nop
-   nop
-   or   1000h,st
-   .word FNADDR
-   .word CXT
-
-   On the c3x this is a bit more difficult. We have to write self
-   modifying code here. So we have to clear the cache every time
-   we execute it because the data in the stack could change.
-
-   ldiu TOP_OF_FUNCTION,ar1
-   lsh  16,ar1
-   or   BOTTOM_OF_FUNCTION,ar1
-   ldiu TOP_OF_STATIC,ar0
-   bud  ar1
-   lsh  16,ar0
-   or   BOTTOM_OF_STATIC,ar0
-   or   1000h,st
-   
-  */
-
-#define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
-
-#define TRAMPOLINE_TEMPLATE(FILE)				\
-{								\
-  if (TARGET_C3X)						\
-    {								\
-      asm_fprintf (FILE, "\tldiu\t0,ar1\n");			\
-      asm_fprintf (FILE, "\tlsh\t16,ar1\n");			\
-      asm_fprintf (FILE, "\tor\t0,ar1\n");			\
-      asm_fprintf (FILE, "\tldiu\t0,ar0\n");			\
-      asm_fprintf (FILE, "\tbud\tar1\n");			\
-      asm_fprintf (FILE, "\tlsh\t16,ar0\n");			\
-      asm_fprintf (FILE, "\tor\t0,ar0\n");			\
-      asm_fprintf (FILE, "\tor\t1000h,st\n");			\
-    }								\
-  else								\
-    {								\
-      asm_fprintf (FILE, "\tlaj\t$+4\n");			\
-      asm_fprintf (FILE, "\taddi3\t4,r11,ar0\n");		\
-      asm_fprintf (FILE, "\tlda\t*ar0,ar1\n");			\
-      asm_fprintf (FILE, "\tlda\t*+ar0(1),ar0\n");		\
-      asm_fprintf (FILE, "\tbud\tar1\n");			\
-      asm_fprintf (FILE, "\tnop\n");				\
-      asm_fprintf (FILE, "\tnop\n");				\
-      asm_fprintf (FILE, "\tor\t1000h,st\n");			\
-      asm_fprintf (FILE, "\t.word\t0\n");			\
-      asm_fprintf (FILE, "\t.word\t0\n");			\
-    }								\
-}
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  if (TARGET_C3X)							\
-    {									\
-      rtx tmp1, tmp2;							\
-      tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR,			\
-			   size_int (16), 0, 1);			\
-      tmp2 = expand_shift (LSHIFT_EXPR, QImode,				\
-			   gen_rtx (CONST_INT, VOIDmode, 0x5069),	\
-			   size_int (16), 0, 1);			\
-      emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2));			\
-      emit_move_insn (gen_rtx (MEM, QImode,				\
-			       plus_constant (tramp, 0)), tmp1);	\
-      tmp1 = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode,		\
-					  0xffff), 0);			\
-      tmp2 = expand_shift (LSHIFT_EXPR, QImode,				\
-			   gen_rtx (CONST_INT, VOIDmode, 0x1069),	\
-			   size_int (16), 0, 1);			\
-      emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2));			\
-      emit_move_insn (gen_rtx (MEM, QImode,				\
-			       plus_constant (tramp, 2)), tmp1);	\
-      tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT,			\
-			   size_int (16), 0, 1);			\
-      tmp2 = expand_shift (LSHIFT_EXPR, QImode,				\
-			   gen_rtx (CONST_INT, VOIDmode, 0x5068),	\
-			   size_int (16), 0, 1);			\
-      emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2));			\
-      emit_move_insn (gen_rtx (MEM, QImode,				\
-			       plus_constant (tramp, 3)), tmp1);	\
-      tmp1 = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode,		\
-				       0xffff), 0);			\
-      tmp2 = expand_shift (LSHIFT_EXPR, QImode,				\
-			   gen_rtx (CONST_INT, VOIDmode, 0x1068),	\
-			   size_int (16), 0, 1);			\
-      emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2));			\
-      emit_move_insn (gen_rtx (MEM, QImode,				\
-			       plus_constant (tramp, 6)), tmp1);	\
-    }									\
-  else									\
-    {									\
-      emit_move_insn (gen_rtx (MEM, QImode,				\
-			       plus_constant (TRAMP, 8)), FNADDR); 	\
-      emit_move_insn (gen_rtx (MEM, QImode,				\
-			       plus_constant (TRAMP, 9)), CXT); 	\
-    }									\
-}
-
-/* Specify the machine mode that this machine uses for the index in
-   the tablejump instruction.  */
-
-#define CASE_VECTOR_MODE Pmode
-
-/* Max number of (32-bit) bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-
-#define MOVE_MAX 1
-
-/* MOVE_RATIO is the number of move instructions that is better than a
-   block move. */
-
-#define MOVE_RATIO 2		/* Default value */
-
-#define BSS_SECTION_ASM_OP ".bss"
-
-#define ASM_OUTPUT_REG_PUSH(FILE, REGNO)  \
-  asm_fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE, REGNO)  \
-  asm_fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* We need to use direct addressing for large constants and addresses
-   that cannot fit within an instruction.  We must check for these
-   after after the final jump optimisation pass, since this may
-   introduce a local_move insn for a SYMBOL_REF.  This pass
-   must come before delayed branch slot filling since it can generate
-   additional instructions.  */
-
-#define MACHINE_DEPENDENT_REORG(INSNS) c4x_process_after_reload(INSNS)
-
-#define MACHINE_DEPENDENT_COMBINE(INSNS) c4x_combine_parallel(INSNS)
-
-#define DBR_OUTPUT_SEQEND(FILE)		\
-if (final_sequence != NULL_RTX)		\
-{					\
- int count;				\
- int laj = GET_CODE (XEXP (XEXP (final_sequence, 0), 0)) == CALL_INSN; \
-					\
- count = dbr_sequence_length();		\
- while (count < (laj ? 2 : 3))		\
- {					\
-    fputs("\tnop\n", FILE);		\
-    count++;				\
- }					\
- if (laj)				\
-    fputs("\tpush\tr11\n", FILE);	\
-}
-
-#define NO_FUNCTION_CSE
-
-/* We don't want a leading tab.  */
-
-#define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
-
-/* Define the codes that are matched by predicates in c4x.c.  */
-
-#define PREDICATE_CODES						\
-  {"fp_zero_operand", {CONST_DOUBLE}},				\
-  {"const_operand", {CONST_INT, CONST_DOUBLE}},			\
-  {"stik_const_operand", {CONST_INT}},				\
-  {"not_const_operand", {CONST_INT}},				\
-  {"reg_operand", {REG, SUBREG}},				\
-  {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
-  {"r0r1_reg_operand", {REG, SUBREG}},				\
-  {"r2r3_reg_operand", {REG, SUBREG}},				\
-  {"ext_low_reg_operand", {REG, SUBREG}},			\
-  {"ext_reg_operand", {REG, SUBREG}},				\
-  {"std_reg_operand", {REG, SUBREG}},				\
-  {"addr_reg_operand", {REG, SUBREG}},				\
-  {"index_reg_operand", {REG, SUBREG}},				\
-  {"dp_reg_operand", {REG}},					\
-  {"sp_reg_operand", {REG}},					\
-  {"st_reg_operand", {REG}},					\
-  {"rc_reg_operand", {REG}},					\
-  {"call_operand", {REG, SYMBOL_REF}},				\
-  {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
-  {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, 	\
-  {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
-  {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
-  {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
-  {"par_ind_operand", {MEM}},					\
-  {"parallel_operand", {SUBREG, REG, MEM}},			\
-  {"mem_operand", {MEM}},					\
-
-
-/* Variables in c4x.c */
-
-extern enum reg_class c4x_regclass_map[];/* smallest class containing REGNO */
-extern enum machine_mode c4x_caller_save_map[];
-
-extern struct rtx_def *c4x_compare_op0;	/* operand 0 for comparisons */
-extern struct rtx_def *c4x_compare_op1;	/* operand 1 for comparisons */
-
-extern int c4x_rpts_cycles;	        /* max cycles for RPTS */
-extern int c4x_cpu_version;		/* cpu version C30/31/32/40/44 */
-
-/* Functions in c4x.c */
-
-extern void c4x_function_prologue ();
-
-extern void c4x_function_epilogue ();
-
-extern struct rtx_def *c4x_operand_subword ();
-
-extern struct rtx_def *c4x_adj_offsettable_operand ();
-
-extern char *c4x_output_cbranch ();
-
-extern int c4x_null_epilogue_p ();
-
-extern int c4x_autoinc_operand ();
-
-extern int c4x_label_conflict ();
-
-extern int c4x_address_conflict ();
-
-extern int c4x_adjust_cost ();
-
-extern void c4x_process_after_reload ();
-
-extern void c4x_combine_parallel ();
-
-extern int c4x_rptb_nop_p ();
-
-extern int c4x_rptb_rpts_p ();
-
-extern int fp_zero_operand ();
-
-extern int const_operand ();
-
-extern int stik_const_operand ();
-
-extern int not_const_operand ();
-
-extern int parallel_operand ();
-
-extern int reg_or_const_operand ();
-
-extern int reg_operand ();
-
-extern int reg_imm_operand ();
-
-extern int r0r1_reg_operand ();
-
-extern int r2r3_reg_operand ();
-
-extern int ext_low_reg_operand ();
-
-extern int ext_reg_operand ();
-
-extern int std_reg_operand ();
-
-extern int src_operand ();
-
-extern int src_hi_operand ();
-
-extern int lsrc_operand ();
-
-extern int tsrc_operand ();
-
-extern int addr_reg_operand ();
-
-extern int index_reg_operand ();
-
-extern int dp_reg_operand ();
-
-extern int sp_reg_operand ();
-
-extern int rc_reg_operand ();
-
-extern int st_reg_operand ();
-
-extern int ar0_reg_operand ();
-
-extern int ar0_mem_operand ();
-
-extern int ar1_reg_operand ();
-
-extern int ar1_mem_operand ();
-
-extern int ar2_reg_operand ();
-
-extern int ar2_mem_operand ();
-
-extern int ar3_reg_operand ();
-
-extern int ar3_mem_operand ();
-
-extern int ar4_reg_operand ();
-
-extern int ar4_mem_operand ();
-
-extern int ar5_reg_operand ();
-
-extern int ar5_mem_operand ();
-
-extern int ar6_reg_operand ();
-
-extern int ar6_mem_operand ();
-
-extern int ar7_reg_operand ();
-
-extern int ar7_mem_operand ();
-
-extern int ir0_reg_operand ();
-
-extern int ir0_mem_operand ();
-
-extern int ir1_reg_operand ();
-
-extern int ir1_mem_operand ();
-
-extern int group1_reg_operand ();
-
-extern int group1_mem_operand ();
-
-extern int arx_reg_operand ();
-
-extern int call_operand ();
-
-extern int par_ind_operand ();
-
-extern int not_rc_reg ();
-
-extern int not_modify_reg ();
-
-extern int c4x_H_constant ();
-
-extern int c4x_I_constant ();
-
-extern int c4x_J_constant ();
-
-extern int c4x_L_constant ();
-
-extern int c4x_Q_constraint ();
-
-extern int c4x_R_constraint ();
-
-extern int c4x_S_constraint ();
-
-extern int c4x_T_constraint ();
-
-extern void c4x_emit_libcall ();
-
-extern void c4x_emit_libcall3 ();
-
-extern void c4x_emit_libcall_mulhi ();
-
-extern int legitimize_operands ();
-
-extern int valid_operands ();
-
-extern int valid_parallel_load_store ();
-
-extern int valid_parallel_operands_4 ();
-
-extern int valid_parallel_operands_5 ();
-
-extern int valid_parallel_operands_6 ();
diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md
deleted file mode 100755
index 1e3d343..0000000
--- a/gcc/config/c4x/c4x.md
+++ /dev/null
@@ -1,6877 +0,0 @@
-;; Machine description for the TMS320C[34]x for GNU C compiler
-;; Copyright (C) 1994-98, 1999 Free Software Foundation, Inc.
-
-;; Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
-;;            and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;
-; TODO :
-;        Set up addressing macros to handle direct memory references properly.
-;        Try using PQImode again for addresses since C30 only uses
-;        24-bit addresses.   Ideally GCC would emit different insns
-;        for QImode and Pmode, whether Pmode was QImode or PQImode.
-;        For addresses we wouldn't have to have a clobber of the CC
-;        associated with each insn and we could use MPYI in address
-;        calculations without having to synthesise a proper 32 bit multiply.
-
-; Additional C30/C40 instructions not coded:
-; CALLcond, IACK, IDLE, LDE, LDFI, LDII, LDM, NORM, RETIcond
-; ROLC, RORC, SIGI, STFI, STII, SUBC, SWI, TRAPcond
-
-; Additional C40 instructions not coded:
-; LDEP, LDPE, LWRct, FRIEEE, TOIEEE, LAJcond, LATcond, RETIcondD
-
-;
-; C4x MODES
-;
-; QImode                char, short, int, long (32-bits)
-; HImode                long long              (64-bits)
-; QFmode                float, double          (32-bits)
-; HFmode                long double            (40-bits)
-; CCmode		
-; CC_NOOVmode		
-
-;
-; C4x PREDICATES:
-;
-; comparison_operator   LT, GT, LE, GE, LTU, GTU, LEU, GEU, EQ, NE
-; memory_operand        memory                                     [m]
-; immediate_operand     immediate constant                         [IKN]
-; register_operand      register                                   [rf]
-; general_operand       register, memory, constant                 [rfmI]
-
-; addr_reg_operand      AR0-AR7, pseudo reg                        [a]
-; sp_reg_operand        SP                                         [b]
-; std_reg_operand       AR0-AR7, IR0-IR1, RC, RS, RE, SP, pseudo   [c]
-; ext_reg_operand       R0-R11, pseudo reg                         [f]
-; ext_low_reg_operand   R0-R7, pseudo reg                          [q]
-; index_reg_operand     IR0-IR1, pseudo reg                        [x]
-; st_reg_operand        ST                                         [y]
-; dp_reg_operand        DP                                         [z]
-; stik_const_operand    5-bit const                                [K]
-; src_operand           general operand                            [rfmHI]
-; par_ind_operand       indirect S mode (ARx + 0, 1, IRx)          [S<>]
-; parallel_operand      par_ind_operand or ext_low_reg_operand
-
-; ADDI src2, src1, dst  three operand op
-; ADDI src, dst         two operand op
-
-;  Note that the predicates are only used when selecting a pattern
-;  to determine if an operand is valid.
-
-;  The constraints then select which of the possible valid operands
-;  is present (and guide register selection). The actual assembly
-;  instruction is then selected on the basis of the constraints.
-
-;  The extra constraint (valid_operands) is used to determine if
-;  the combination of operands is legitimate for the pattern.
-
-;
-; C4x CONSTRAINTS:
-;
-; a   address reg          AR0-AR7
-; b   stack pointer        SP
-; c   other int reg        AR0-AR7, IR0-IR1, RC, RS, RE
-; d   fp reg               R0-R11 (sets CC when dst) 
-; e
-; f   fp reg               R0-R11 (sets CC when dst)
-; g   general reg, memory, constant
-; h   fp reg (HFmode)      R0-R11 (sets CC when dst) 
-; i   immediate int constant
-; j
-; k   block count          BK
-; l
-; m   memory
-; n   immediate int constant with known numeric value
-; o   offsettable memory
-; p   memory address
-; q   low fp reg           R0-R7  (sets CC when dst)
-; r   general reg          R0-R11, AR0-AR7, IR0-IR1, RC, RS, RE
-; s   immediate int constant (value not explicit)
-; t                        R0-R1
-; u                        R2-R3
-; v   repeat count reg     RC
-; w
-; x   index reg            IR0-IR1
-; y   status (CC) reg      ST
-; z   data pointer         DP
-
-; G   fp zero
-; H   fp 16-bit constant
-; I   signed 16-bit
-; J   signed 8-bit    (C4x only)
-; K   signed 5-bit    (C4x only)
-; L   unsigned 16-bit
-; M   unsigned 8-bit  (C4x only)
-; N   ones complement of unsigned 16-bit
-; O   16 bit high constant
-; Q   ARx + 9-bit signed disp
-; R   ARx + 5-bit unsigned disp  (C4x only)
-; S   ARx + 0, 1, IRx disp
-; T   symbol ref (direct)
-; V   non offsettable memory
-; X   any operand
-; <   memory operand with autodecrement addressing
-; >   memory operand with autoincrement addressing
-; {   memory operand with pre-modify addressing
-; }   memory operand with post-modify addressing
-
-;  Note that the d, f, and h constraints are equivalent.
-;  The m constraint is equivalent to QT<>{}
-
-;  Note that the constraints are used to select the operands
-;  for a chosen pattern.  The constraint that requires the fewest
-;  instructions to load an operand is chosen.
-
-;  Note that the 'r' constraint is mostly only used for src integer register 
-;  operands,  while 'c' and 'd' constraints are generally only used for dst
-;  integer register operands (the 'r' constraint is the union of the 'c' and
-;  'd' constraints).  When a register satisfying the 'd' constraint
-;  is used as a dst operand, the CC gets clobbered (except for LDIcond)---but 
-;  not for 'c'.
-
-;  The 'f' constraint is only for float register operands---when 
-;  a register satisying the 'f' constraint is used as a dst operand,
-;  the CC gets clobbered (except for LDFcond).
-
-;  The ! in front of the 'b' constaint says to GCC to disparage the
-;  use of this constraint.  The 'b' constraint applies only to the SP.
-
-;  Note that we deal with the condition code CC like some of the RISC
-;  architectures (arm, sh, sparc) where it is stored in a general register,
-;  in this case the hard register ST (21).  Unlike these other architectures
-;  that do not set the CC with many instructions, the C[34]x architectures
-;  sets the CC for many instructions when the destination register is
-;  an extended precision register.  While it would have been easier
-;  to use the generic cc0 register to store the CC, as with most of
-;  the other ported architectures, this constrains the setting and testing
-;  of the CC to be consecutive insns.  Thus we would reduce the benefit
-;  of scheduling instructions to avoid pipeline conflicts and filling of
-;  delayed branch slots.
-
-;  Since the C[34]x has many instructions that set the CC, we pay the
-;  price of having to explicity define which insns clobber the CC
-;  (rather than using the macro NOTICE_UPDATE_CC). 
-
-;  Note that many patterns say that the CC is clobbered when in fact
-;  that it may not be (depending on the destination register).
-;  We have to cover ourselves if an extended precision register
-;  is allocated to the destination register.
-;  Unfortunately, it is not easy to tell GCC that the clobbering of CC
-;  is register dependent.  If we could tolerate the ST register being
-;  copied about, then we could store the CC in a pseudo register and
-;  use constructs such as (clobber (match_scratch:CC N "&y,X")) to
-;  indicate that the 'y' class (ST register) is clobbered for the
-;  first combination of operands, but not with the second.
-;  I tried this approach for a while but reload got unhappy since I
-;  didn't allow it to move the CC around.
-
-;  Note that fundamental operations, such as moves, must not clobber the
-;  CC.  Thus movqi choses a move instruction that doesn't clobber the CC.
-;  If GCC wants to combine a move with a compare, it is smart enough to
-;  chose the move instruction that sets the CC.
-
-;  Unfortunately, the C[34]x instruction set does not have arithmetic or
-;  logical operations that never touch the CC.  We thus have to assume
-;  that the CC may be clobbered at all times.  If we define patterns
-;  such as addqi without the clobber of CC, then GCC will be forced
-;  to use registers such as the auxiliary registers which can cause
-;  horrible pipeline conflicts.  The tradeoff is that GCC can't now
-;  sneak in an add instruction between setting and testing of the CC.
-
-;  Most of the C[34]x instructions require operands of the following formats,
-;  where imm represents an immediate constant, dir a direct memory reference,
-;  ind an indirect memory reference, and reg a register:
-
-;        src2 (op2)             src1 (op1)      dst (op0)
-; imm  dir  ind  reg  |  imm  dir  ind  reg  |  reg      Notes
-;---------------------+----------------------+------
-; ILH   T   Q<>   r   |   -    -    -    0   |   r       2 operand
-;  -    -   S<>   r   |   -    -   S<>   r   |   r       
-;  J    -    R    -   |   -    -    R    r   |   r       C4x
-
-;  Arithmetic operations use the I, J constraints for immediate constants,
-;  while logical operations use the L, J constraints.  Floating point
-;  operations use the H constraint for immediate constants.
-
-;  With most instructions the src2 and src1 operands are commutative
-;  (except for SUB, SUBR, ANDN).  The assembler considers
-;  ADDI 10, R0, R1 and ADDI R0, 10, R1 to be equivalent.
-;  We thus match src2 and src1 with the src_operand predicate and
-;  use valid_operands as the extra constraint to reject invalid
-;  operand combinations.  For example, ADDI @foo, @bar, R0.
-
-;  Note that we use the ? modifier so that reload doesn't preferentially
-;  try the alternative where three registers are acceptable as
-;  operands (whenever an operand requires reloading).  Instead it will try
-;  the 2 operand form which will produce better code since it won't require
-;  a new spill register.
-
-;  Note that the floating point representation of 0.0 on the C4x
-;  is 0x80000000 (-2147483648).  This value produces an warning
-;  message on 32-bit machines about the decimal constant being so large
-;  that it is unsigned.
-
-;  With two operand instructions patterns having two sets,
-;  the compare set must come first to keep the combiner happy.
-;  While the combiner seems to cope most of the time with the
-;  compare set coming second, it's best to have it first.
-
-;
-; C4x CONSTANT attributes
-;
-(define_attr "cpu" "c4x,c3x"
- (const
-  (cond [(symbol_ref "TARGET_C3X") (const_string "c3x")]
-         (const_string "c4x"))))
-
-;
-; C4x INSN ATTRIBUTES:
-;
-; lda           load address, non-clobber CC
-; store         memory store, non-clobber CC
-; load_load     parallel memory loads, non-clobber CC
-; load_store    parallel memory load and store, non-clobber CC
-; store_load    parallel memory store and load, non-clobber CC
-; store_store   parallel memory stores, non-clobber CC
-; unary         two operand arithmetic, non-clobber CC
-; unarycc       two operand arithmetic, clobber CC
-; binary        three operand arithmetic, non-clobber CC
-; binarycc      three operand arithmetic, clobber CC
-; compare       compare, clobber CC
-; call          function call
-; rets          return from subroutine
-; jump          unconditional branch
-; jmpc          conditional branch
-; db            decrement and branch (unconditional)
-; dbc           decrement and branch (conditional)
-; ldp           load DP
-; push		stack push
-; pop		stack pop
-; repeat        block repeat
-; repeat_top    block repeat top
-; laj           link and jump
-; multi         multiple instruction
-; misc          nop		(default)
-
-;  The only real instructions that affect things are the ones that modify
-;  address registers and ones that call or jump.  Note that the number
-;  of operands refers to the RTL insn pattern, not the number of explicit
-;  operands in the machine instruction.
-;
-(define_attr "type" "lda,store,unary,unarycc,binary,binarycc,compare,call,rets,jump,jmpc,db,dbc,misc,ldp,repeat,repeat_top,laj,load_load,load_store,store_load,store_store,push,pop,multi"
-             (const_string "misc"))
-
-
-; Some instructions operate on unsigned data constants, some on signed data
-; constants, or the ones complement of unsigned constants.
-; This differentiates them.  Default to signed.  This attribute
-; is used by the macro SMALL_CONST () (defined in c4x.h) to determine
-; whether an immediate integer constant will fit within the instruction,
-; or will have to be loaded using direct addressing from memory.
-; Note that logical operations assume unsigned integers whereas
-; arithmetic operations assume signed integers.  Note that the C4x
-; small immediate constant (J) used as src2 in three operand instructions
-; is always signed.  not_uint16 refers to a number that fits into 16-bits
-; when one's complemented.
-;
-(define_attr "data" "int16,uint16,high_16,not_uint16" (const_string "int16"))
-
-(define_asm_attributes
-  [(set_attr "type" "multi")])
-
-;
-; C4x DELAY SLOTS
-;
-; Define delay slot scheduling for branch and call instructions.
-; The C[34]x has three delay slots. Note that none of the three instructions
-; that follow a delayed branch can be a Bcond, BcondD, BR, BRD, DBcond,
-; DBcondD, CALL, CALLcond, TRAPcond, RETIcond, RETScond, RPTB, RPTS, or IDLE.
-;
-; Annulled branches are a bit difficult because the next instructions
-; are preprocessed.
-; The table below shows what phase of the c4x is executed.
-;        BccA[TF] label
-;        op1             fetch, decode and read executed
-;        op2             fetch and decode executed
-;        op3             fetch executed
-; This means that we can allow any instruction in the last delay slot
-; and only instructions which modify registers in the first two. 
-; lda can not be executed in the first delay slot 
-; and ldpk can not be executed in the first two delay slots.
-
-(define_attr "onlyreg" "false,true"
-       (cond [(eq_attr "type" "unary,unarycc")
-                       (if_then_else (and (match_operand 0 "reg_imm_operand" "")
-                                          (match_operand 1 "reg_imm_operand" ""))
-                                     (const_string "true") (const_string "false"))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (and (match_operand 0 "reg_imm_operand" "")
-                                          (and (match_operand 1 "reg_imm_operand" "")
-                                               (match_operand 2 "reg_imm_operand" "")))
-                                     (const_string "true") (const_string "false"))]
-             (const_string "false")))
-
-(define_attr "onlyreg_nomod" "false,true"
-       (cond [(eq_attr "type" "unary,unarycc,compare,lda,store")
-                       (if_then_else (and (match_operand 0 "not_modify_reg" "")
-                                          (match_operand 1 "not_modify_reg" ""))
-                                     (const_string "true") (const_string "false"))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (and (match_operand 0 "not_modify_reg" "")
-                                          (and (match_operand 1 "not_modify_reg" "")
-                                               (match_operand 2 "not_modify_reg" "")))
-                                     (const_string "true") (const_string "false"))]
-             (const_string "false")))
-
-(define_attr "not_repeat_reg" "false,true"
-       (cond [(eq_attr "type" "unary,unarycc,compare,lda,store")
-                       (if_then_else (and (match_operand 0 "not_rc_reg" "")
-                                          (match_operand 1 "not_rc_reg" ""))
-                                     (const_string "true") (const_string "false"))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (and (match_operand 0 "not_rc_reg" "")
-                                          (and (match_operand 1 "not_rc_reg" "")
-                                               (match_operand 2 "not_rc_reg" "")))
-                                     (const_string "true") (const_string "false"))]
-             (const_string "false")))
-
-(define_attr "in_annul_slot_1" "false,true"
-  (if_then_else (and (and (eq_attr "cpu" "c4x")
-		          (eq_attr "type" "!jump,call,rets,jmpc,compare,db,dbc,repeat,repeat_top,laj,push,pop,lda,ldp,multi"))
-		     (eq_attr "onlyreg" "true"))
-		(const_string "true")
-		(const_string "false")))
-
-(define_attr "in_annul_slot_2" "false,true"
-  (if_then_else (and (and (eq_attr "cpu" "c4x")
-		          (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,push,pop,ldp,multi"))
-		     (eq_attr "onlyreg_nomod" "true"))
-		(const_string "true")
-		(const_string "false")))
-
-(define_attr "in_annul_slot_3" "false,true"
-  (if_then_else (and (eq_attr "cpu" "c4x")
-		     (eq_attr "type" "!jump,call,rets,jmpc,unarycc,binarycc,db,dbc,repeat,repeat_top,laj,push,pop,multi"))
-		(const_string "true")
-		(const_string "false")))
-
-(define_attr "in_delay_slot" "false,true"
-  (if_then_else (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,multi")
-		(const_string "true")
-		(const_string "false")))
-
-(define_attr "in_repeat_slot" "false,true"
-  (if_then_else (and (eq_attr "cpu" "c4x")
-		     (and (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,multi")
-		          (eq_attr "not_repeat_reg" "true")))
-		(const_string "true")
-		(const_string "false")))
-
-(define_attr "in_dbc_slot" "false,true"
-  (if_then_else (eq_attr "type" "!jump,call,rets,jmpc,unarycc,binarycc,compare,db,dbc,repeat,repeat_top,laj,multi")
-		(const_string "true")
-		(const_string "false")))
-
-(define_delay (eq_attr "type" "jmpc")
-              [(eq_attr "in_delay_slot" "true")
-               (eq_attr "in_annul_slot_1" "true")
-               (eq_attr "in_annul_slot_1" "true")
-
-               (eq_attr "in_delay_slot" "true")
-               (eq_attr "in_annul_slot_2" "true")
-               (eq_attr "in_annul_slot_2" "true")
-
-               (eq_attr "in_delay_slot" "true")
-               (eq_attr "in_annul_slot_3" "true")
-               (eq_attr "in_annul_slot_3" "true") ])
-
-
-(define_delay (eq_attr "type" "repeat_top")
-              [(eq_attr "in_repeat_slot" "true") (nil) (nil)
-               (eq_attr "in_repeat_slot" "true") (nil) (nil)
-               (eq_attr "in_repeat_slot" "true") (nil) (nil)])
-
-(define_delay (eq_attr "type" "jump,db")
-              [(eq_attr "in_delay_slot" "true") (nil) (nil)
-               (eq_attr "in_delay_slot" "true") (nil) (nil)
-               (eq_attr "in_delay_slot" "true") (nil) (nil)])
-
-
-; Decrement and branch conditional instructions cannot modify the
-; condition codes for the cycles in the delay slots.
-;
-(define_delay (eq_attr "type" "dbc")
-              [(eq_attr "in_dbc_slot" "true") (nil) (nil)
-               (eq_attr "in_dbc_slot" "true") (nil) (nil)
-               (eq_attr "in_dbc_slot" "true") (nil) (nil)])
-
-; The LAJ instruction has three delay slots but the last slot is
-; used for pushing the return address.  Thus we can only use two slots.
-;
-(define_delay (eq_attr "type" "laj")
-              [(eq_attr "in_delay_slot" "true") (nil) (nil)
-               (eq_attr "in_delay_slot" "true") (nil) (nil)])
-
-;
-; C4x UNSPEC NUMBERS
-;
-;  1 BU/BUD
-;  2 RPTS
-;  3 LSH
-;  4 cmphi
-;  5 RCPF
-;  6 RND
-;  7 repeat block filler
-;  8 loadhf_int
-;  9 storehf_int
-; 10 RSQRF
-
-
-;
-; C4x FUNCTIONAL UNITS
-;
-; Define functional units for instruction scheduling to minimise
-; pipeline conflicts.
-;
-; With the C3x, an external memory write (with no wait states) takes
-; two cycles and an external memory read (with no wait states) takes
-; one cycle.  However, an external read following an external write
-; takes two cycles.  With internal memory, reads and writes take
-; half a cycle.
-;
-; When a C4x address register is loaded it will not be available for
-; an extra machine cycle.  Calculating with a C4x address register
-; makes it unavailable for 2 machine cycles.  To notify GCC of these
-; pipeline delays, each of the auxiliary and index registers are declared
-; as separate functional units.
-;
-; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
-;			TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
-;
-; MULTIPLICITY 1 (C4x has no independent identical function units)
-; SIMULTANEITY 0 (C4x is pipelined)
-; READY_DELAY  1 (Results usually ready after every cyle)
-; ISSUE_DELAY  1 (Can issue insns every cycle)
-
-; Just some dummy definitions. The real work is done in c4x_adjust_cost.
-; These are needed so the min/max READY_DELAY is known.
-
-(define_function_unit "dummy" 1 0 (const_int 0) 1 1)
-(define_function_unit "dummy" 1 0 (const_int 0) 2 1)
-(define_function_unit "dummy" 1 0 (const_int 0) 3 1)
-
-;(define_function_unit "ar0" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setar0" "1")
-;                 (eq_attr "usear0" "1")))
-;       3 1 )
-
-;(define_function_unit "ar0" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setlda_ar0" "1")
-;                 (eq_attr "usear0" "1")))
-;       2 1 )
-
-;(define_function_unit "ar0" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "usear0" "1")
-;                 (eq_attr "readar0" "1")))
-;       2 1 )
-
-; The attribute setar0 is set to 1 for insns where ar0 is a dst operand.
-; Note that the attributes unarycc and binarycc do not apply
-; if ar0 is a dst operand (only loading an ext. prec. reg. sets CC)
-(define_attr "setar0" ""
-       (cond [(eq_attr "type" "unary,binary")
-                       (if_then_else (match_operand 0 "ar0_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "setlda_ar0" ""
-       (cond [(eq_attr "type" "lda")
-                       (if_then_else (match_operand 0 "ar0_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-; The attribute usear0 is set to 1 for insns where ar0 is used
-; for addressing, as a src operand, or as a dst operand.
-(define_attr "usear0" ""
-       (cond [(eq_attr "type" "compare,store")
-                       (if_then_else (match_operand 0 "ar0_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar0_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar0_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "db,dbc")
-                       (if_then_else (match_operand 0 "ar0_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-; The attribute readar0 is set to 1 for insns where ar0 is a src operand.
-(define_attr "readar0" ""
-       (cond [(eq_attr "type" "compare")
-                       (if_then_else (match_operand 0 "ar0_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar0_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar0_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-;(define_function_unit "ar1" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setar1" "1")
-;                 (eq_attr "usear1" "1")))
-;       3 1 )
-
-;(define_function_unit "ar1" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setlda_ar1" "1")
-;                 (eq_attr "usear1" "1")))
-;       2 1 )
-
-;(define_function_unit "ar1" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "usear1" "1")
-;                 (eq_attr "readar1" "1")))
-;       2 1 )
-
-(define_attr "setar1" ""
-       (cond [(eq_attr "type" "unary,binary")
-                       (if_then_else (match_operand 0 "ar1_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "setlda_ar1" ""
-       (cond [(eq_attr "type" "lda")
-                       (if_then_else (match_operand 0 "ar1_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "usear1" ""
-       (cond [(eq_attr "type" "compare,store")
-                       (if_then_else (match_operand 0 "ar1_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar1_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar1_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "db,dbc")
-                       (if_then_else (match_operand 0 "ar1_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "readar1" ""
-       (cond [(eq_attr "type" "compare")
-                       (if_then_else (match_operand 0 "ar1_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar1_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar1_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-;(define_function_unit "ar2" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setar2" "1")
-;                 (eq_attr "usear2" "1")))
-;       3 1 )
-
-;(define_function_unit "ar2" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setlda_ar2" "1")
-;                 (eq_attr "usear2" "1")))
-;       2 1 )
-
-;(define_function_unit "ar2" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "usear2" "1")
-;                 (eq_attr "readar2" "1")))
-;       2 1 )
-
-(define_attr "setar2" ""
-       (cond [(eq_attr "type" "unary,binary")
-                       (if_then_else (match_operand 0 "ar2_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "setlda_ar2" ""
-       (cond [(eq_attr "type" "lda")
-                       (if_then_else (match_operand 0 "ar2_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "usear2" ""
-       (cond [(eq_attr "type" "compare,store")
-                       (if_then_else (match_operand 0 "ar2_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar2_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar2_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "db,dbc")
-                       (if_then_else (match_operand 0 "ar2_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "readar2" ""
-       (cond [(eq_attr "type" "compare")
-                       (if_then_else (match_operand 0 "ar2_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar2_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar2_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-;(define_function_unit "ar3" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setar3" "1")
-;                 (eq_attr "usear3" "1")))
-;       3 1 )
-
-;(define_function_unit "ar3" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setlda_ar3" "1")
-;                 (eq_attr "usear3" "1")))
-;       2 1 )
-
-;(define_function_unit "ar3" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "usear3" "1")
-;                 (eq_attr "readar3" "1")))
-;       2 1 )
-
-(define_attr "setar3" ""
-       (cond [(eq_attr "type" "unary,binary")
-                       (if_then_else (match_operand 0 "ar3_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "setlda_ar3" ""
-       (cond [(eq_attr "type" "lda")
-                       (if_then_else (match_operand 0 "ar3_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "usear3" ""
-       (cond [(eq_attr "type" "compare,store")
-                       (if_then_else (match_operand 0 "ar3_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar3_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar3_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "db,dbc")
-                       (if_then_else (match_operand 0 "ar3_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "readar3" ""
-       (cond [(eq_attr "type" "compare")
-                       (if_then_else (match_operand 0 "ar3_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar3_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar3_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-;(define_function_unit "ar4" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setar4" "1")
-;                 (eq_attr "usear4" "1")))
-;       3 1 )
-
-;(define_function_unit "ar4" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setlda_ar4" "1")
-;                 (eq_attr "usear4" "1")))
-;       2 1 )
-
-;(define_function_unit "ar4" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "usear4" "1")
-;                 (eq_attr "readar4" "1")))
-;       2 1 )
-
-(define_attr "setar4" ""
-       (cond [(eq_attr "type" "unary,binary")
-                       (if_then_else (match_operand 0 "ar4_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "setlda_ar4" ""
-       (cond [(eq_attr "type" "lda")
-                       (if_then_else (match_operand 0 "ar4_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "usear4" ""
-       (cond [(eq_attr "type" "compare,store")
-                       (if_then_else (match_operand 0 "ar4_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar4_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar4_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "db,dbc")
-                       (if_then_else (match_operand 0 "ar4_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "readar4" ""
-       (cond [(eq_attr "type" "compare")
-                       (if_then_else (match_operand 0 "ar4_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar4_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar4_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-;(define_function_unit "ar5" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setar5" "1")
-;                 (eq_attr "usear5" "1")))
-;       3 1 )
-
-;(define_function_unit "ar5" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setlda_ar5" "1")
-;                 (eq_attr "usear5" "1")))
-;       2 1 )
-
-;(define_function_unit "ar5" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "usear5" "1")
-;                 (eq_attr "readar5" "1")))
-;       2 1 )
-
-(define_attr "setar5" ""
-       (cond [(eq_attr "type" "unary,binary")
-                       (if_then_else (match_operand 0 "ar5_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "setlda_ar5" ""
-       (cond [(eq_attr "type" "lda")
-                       (if_then_else (match_operand 0 "ar5_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "usear5" ""
-       (cond [(eq_attr "type" "compare,store")
-                       (if_then_else (match_operand 0 "ar5_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar5_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar5_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "db,dbc")
-                       (if_then_else (match_operand 0 "ar5_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "readar5" ""
-       (cond [(eq_attr "type" "compare")
-                       (if_then_else (match_operand 0 "ar5_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar5_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar5_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-;(define_function_unit "ar6" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setar6" "1")
-;                 (eq_attr "usear6" "1")))
-;       3 1 )
-
-;(define_function_unit "ar6" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setlda_ar6" "1")
-;                 (eq_attr "usear6" "1")))
-;       2 1 )
-
-;(define_function_unit "ar6" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "usear6" "1")
-;                 (eq_attr "readar6" "1")))
-;       2 1 )
-
-(define_attr "setar6" ""
-       (cond [(eq_attr "type" "unary,binary")
-                       (if_then_else (match_operand 0 "ar6_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "setlda_ar6" ""
-       (cond [(eq_attr "type" "lda")
-                       (if_then_else (match_operand 0 "ar6_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "usear6" ""
-       (cond [(eq_attr "type" "compare,store")
-                       (if_then_else (match_operand 0 "ar6_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar6_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar6_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "db,dbc")
-                       (if_then_else (match_operand 0 "ar6_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "readar6" ""
-       (cond [(eq_attr "type" "compare")
-                       (if_then_else (match_operand 0 "ar6_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar6_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar6_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-;(define_function_unit "ar7" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setar7" "1")
-;                 (eq_attr "usear7" "1")))
-;       3 1 )
-
-;(define_function_unit "ar7" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setlda_ar7" "1")
-;                 (eq_attr "usear7" "1")))
-;       2 1 )
-
-;(define_function_unit "ar7" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "usear7" "1")
-;                 (eq_attr "readar7" "1")))
-;       2 1 )
-
-(define_attr "setar7" ""
-       (cond [(eq_attr "type" "unary,binary")
-                       (if_then_else (match_operand 0 "ar7_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "setlda_ar7" ""
-       (cond [(eq_attr "type" "lda")
-                       (if_then_else (match_operand 0 "ar7_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "usear7" ""
-       (cond [(eq_attr "type" "compare,store")
-                       (if_then_else (match_operand 0 "ar7_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar7_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar7_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "db,dbc")
-                       (if_then_else (match_operand 0 "ar7_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "readar7" ""
-       (cond [(eq_attr "type" "compare")
-                       (if_then_else (match_operand 0 "ar7_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ar7_reg_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ar7_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-;(define_function_unit "ir0" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setir0" "1")
-;                 (eq_attr "useir0" "1")))
-;       3 1 )
-
-;(define_function_unit "ir0" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setlda_ir0" "1")
-;                 (eq_attr "useir0" "1")))
-;       2 1 )
-
-(define_attr "setir0" ""
-       (cond [(eq_attr "type" "unary,binary")
-                       (if_then_else (match_operand 0 "ir0_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "setlda_ir0" ""
-       (cond [(eq_attr "type" "lda")
-                       (if_then_else (match_operand 0 "ir0_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "useir0" ""
-       (cond [(eq_attr "type" "compare,store")
-                       (if_then_else (match_operand 0 "ir0_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ir0_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ir0_mem_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-;(define_function_unit "ir1" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setir1" "1")
-;                 (eq_attr "useir1" "1")))
-;       3 1 )
-
-;(define_function_unit "ir1" 1 0
-;       (and (eq_attr "cpu" "c4x")
-;            (and (eq_attr "setlda_ir1" "1")
-;                 (eq_attr "useir1" "1")))
-;       2 1 )
-
-(define_attr "setir1" ""
-       (cond [(eq_attr "type" "unary,binary")
-                       (if_then_else (match_operand 0 "ir1_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "setlda_ir1" ""
-       (cond [(eq_attr "type" "lda")
-                       (if_then_else (match_operand 0 "ir1_reg_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "useir1" ""
-       (cond [(eq_attr "type" "compare,store")
-                       (if_then_else (match_operand 0 "ir1_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
-                       (if_then_else (match_operand 1 "ir1_mem_operand" "")
-                                     (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-                       (if_then_else (match_operand 2 "ir1_mem_operand" "")
-                                     (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-; With the C3x, things are simpler, but slower, i.e. more pipeline conflicts :(
-; There are three functional groups:
-; (1) AR0-AR7, IR0-IR1, BK
-; (2) DP
-; (3) SP
-;
-; When a register in one of these functional groups is loaded,
-; the contents of that or any other register in its group
-; will not be available to the next instruction for 2 machine cycles.
-; Similarly, when a register in one of the functional groups is read
-; excepting (IR0-IR1, BK, DP) the contents of that or any other register
-; in its group will not be available to the next instruction for
-; 1 machine cycle.
-;
-; Let's ignore functional groups 2 and 3 for now, since they are not
-; so important.
-
-;(define_function_unit "group1" 1 0
-;       (and (eq_attr "cpu" "c3x")
-;            (and (eq_attr "setgroup1" "1")
-;                 (eq_attr "usegroup1" "1")))
-;       3 1)
-
-;(define_function_unit "group1" 1 0
-;       (and (eq_attr "cpu" "c3x")
-;            (and (eq_attr "usegroup1" "1")
-;                 (eq_attr "readarx" "1")))
-;       2 1)
-
-(define_attr "setgroup1" ""
-       (cond [(eq_attr "type" "lda,unary,binary")
-                  (if_then_else (match_operand 0 "group1_reg_operand" "")
-                                (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "usegroup1" ""
-       (cond [(eq_attr "type" "compare,store,store_store,store_load")
-              (if_then_else (match_operand 0 "group1_mem_operand" "")
-                            (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc,load_load,load_store")
-              (if_then_else (match_operand 1 "group1_mem_operand" "")
-                            (const_int 1) (const_int 0))
-              (eq_attr "type" "store_store,load_store")
-              (if_then_else (match_operand 2 "group1_mem_operand" "")
-                            (const_int 1) (const_int 0))
-              (eq_attr "type" "load_load,store_load")
-              (if_then_else (match_operand 3 "group1_mem_operand" "")
-                            (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-(define_attr "readarx" ""
-       (cond [(eq_attr "type" "compare")
-              (if_then_else (match_operand 0 "arx_reg_operand" "")
-                            (const_int 1) (const_int 0))
-              (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
-              (if_then_else (match_operand 1 "arx_reg_operand" "")
-                            (const_int 1) (const_int 0))
-              (eq_attr "type" "binary,binarycc")
-              (if_then_else (match_operand 2 "arx_reg_operand" "")
-                            (const_int 1) (const_int 0))]
-             (const_int 0)))
-
-
-;
-; C4x INSN PATTERNS:
-;
-; Note that the movMM and addP patterns can be called during reload
-; so we need to take special care with theses patterns since
-; we cannot blindly clobber CC or generate new pseudo registers.
-
-;
-; TWO OPERAND INTEGER INSTRUCTIONS
-;
-
-;
-; LDP/LDPK
-;
-(define_insn "set_ldp"
-  [(set (match_operand:QI 0 "dp_reg_operand" "=z")
-        (high:QI (match_operand:QI 1 "" "")))]
-  "! TARGET_SMALL"
-  "* return (TARGET_C3X) ? \"ldp\\t%A1\" : \"ldpk\\t%A1\";"
-  [(set_attr "type" "ldp")])
-
-
-; Used when moving a constant label reference to an external
-; location, this will make sure the original label is still
-; used so the optimizer will not optimize it away.
-;
-(define_insn "set_ldp_use"
-  [(parallel [(set (match_operand:QI 0 "dp_reg_operand" "=z")
-                   (high:QI (match_operand:QI 1 "" "")))
-              (use (match_operand 2 "" ""))])]
-  "! TARGET_SMALL"
-  "* return (TARGET_C3X) ? \"ldp\\t%A1\" : \"ldpk\\t%A1\";"
-  [(set_attr "type" "ldp")])
-
-(define_insn "set_high_use"
-  [(parallel [(set (match_operand:QI 0 "std_reg_operand" "=c")
-                   (high:QI (match_operand:QI 1 "" "")))
-              (use (match_operand 2 "" ""))])]
-  "! TARGET_C3X && ! TARGET_SMALL"
-  "ldhi\\t^%H1,%0"
-  [(set_attr "type" "unary")])
-
-(define_insn "set_ior_lo_use"
-  [(parallel [(set (match_operand:QI 0 "std_reg_operand" "=c")
-                   (ior:QI (match_dup 0)
-                           (and:QI (match_operand:QI 1 "" "")
-                                   (const_int 65535))))
-              (use (match_operand 2 "" ""))])]
-  "! TARGET_C3X && ! TARGET_SMALL"
-  "or\\t#%H1,%0"
-  [(set_attr "type" "unary")])
-
-;
-; LDIU/LDA/STI/STIK
-;
-; The following moves will not set the condition codes register.
-;
-
-; This must come before the general case
-(define_insn "*movqi_stik"
-  [(set (match_operand:QI 0 "memory_operand" "=m")
-        (match_operand:QI 1 "stik_const_operand" "K"))]
-  "! TARGET_C3X"
-  "stik\\t%1,%0"
-  [(set_attr "type" "store")])
-
-; We must provide an alternative to store to memory in case we have to
-; spill a register.
-(define_insn "movqi_noclobber"
-  [(set (match_operand:QI 0 "src_operand" "=d,*c,m,r")
-        (match_operand:QI 1 "src_hi_operand" "rmI,rmI,r,O"))]
-  "reg_operand (operands[0], QImode)
-   || reg_operand (operands[1], QImode)"
-  "*
-   if (which_alternative == 2)
-     return \"sti\\t%1,%0\";
-
-   if (! TARGET_C3X && which_alternative == 3)
-     {
-       operands[1] = GEN_INT ((INTVAL (operands[1]) >> 16) & 0xffff);
-       return \"ldhi\\t%1,%0\";
-     }
-
-   /* The lda instruction cannot use the same register as source
-      and destination.  */
-   if (! TARGET_C3X && which_alternative == 1
-       && (   IS_ADDR_REG (REGNO (operands[0]))
-           || IS_INDEX_REG (REGNO (operands[0]))
-           || IS_SP_REG (REGNO (operands[0])))
-       && (REGNO (operands[0]) != REGNO (operands[1])))
-      return \"lda\\t%1,%0\";
-   return \"ldiu\\t%1,%0\";
-  "
-  [(set_attr "type" "unary,lda,store,unary")
-   (set_attr "data" "int16,int16,int16,high_16")])
-
-;
-; LDI
-;
-
-; We shouldn't need these peepholes, but the combiner seems to miss them...
-(define_peephole
-  [(set (match_operand:QI 0 "ext_reg_operand" "=d")
-        (match_operand:QI 1 "src_operand" "g"))
-   (set (reg:CC 21)
-        (compare:CC (match_dup 0) (const_int 0)))]
-  ""
-  "@
-  ldi\\t%1,%0"
-  [(set_attr "type" "unarycc")
-   (set_attr "data" "int16")])
-
-(define_insn "*movqi_set"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:QI 1 "src_operand" "g") 
-                    (const_int 0)))
-   (set (match_operand:QI 0 "ext_reg_operand" "=d")
-        (match_dup 1))]
-  ""
-  "@
-  ldi\\t%1,%0"
-  [(set_attr "type" "unarycc")
-   (set_attr "data" "int16")])
-
-; This pattern probably gets in the way and requires a scratch register
-; when a simple compare with zero will suffice.
-;(define_insn "*movqi_test"
-; [(set (reg:CC 21)
-;       (compare:CC (match_operand:QI 1 "src_operand" "g") 
-;                   (const_int 0)))
-;  (clobber (match_scratch:QI 0 "=d"))]
-; ""
-; "@
-;  ldi\\t%1,%0"
-;  [(set_attr "type" "unarycc")
-;   (set_attr "data" "int16")])
-
-;  If one of the operands is not a register, then we should
-;  emit two insns, using a scratch register.  This will produce
-;  better code in loops if the source operand is invariant, since
-;  the source reload can be optimised out.  During reload we cannot
-;  use change_address or force_reg which will allocate new pseudo regs.
-
-;  Unlike most other insns, the move insns can't be split with
-;  different predicates, because register spilling and other parts of
-;  the compiler, have memoized the insn number already.
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "src_operand" "")
-        (match_operand:QI 1 "src_operand" ""))]
-  ""
-  "
-   /* We shouldn't have to do this, since reload is supposed to
-      be able to do this if we have a memory constraint.  */
-   if (CONSTANT_P (operands[1])
-       && ! const_operand (operands[1], QImode))
-     {
-        operands[1] = force_const_mem (QImode, operands[1]);
-        if (! memory_address_p (QImode, XEXP (operands[1], 0))
-            && ! reload_in_progress)
-          operands[1] = change_address (operands[1], QImode,
-                                        XEXP (operands[1], 0));
-     }
-
-   if (! reload_in_progress
-       && ! reg_operand (operands[0], QImode) 
-       && ! reg_operand (operands[1], QImode)
-       && ! (stik_const_operand (operands[1], QImode) 
-            && ! push_operand (operands[0], QImode)))
-     operands[1] = force_reg (QImode, operands[1]);")
-
-(define_insn "*movqi_update"
-  [(set (match_operand:QI 0 "reg_operand" "=r") 
-        (mem:QI (plus:QI (match_operand:QI 1 "addr_reg_operand" "a")
-                         (match_operand:QI 2 "index_reg_operand" "x"))))
-   (set (match_dup 1)
-        (plus:QI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldiu\\t*%1++(%2),%0"
-  [(set_attr "type" "unary")
-   (set_attr "data" "int16")])
-
-(define_insn "movqi_parallel"
-  [(set (match_operand:QI 0 "parallel_operand" "=q,S<>,q,S<>")
-        (match_operand:QI 1 "parallel_operand" "S<>,q,S<>,q"))
-   (set (match_operand:QI 2 "parallel_operand" "=q,S<>,S<>,q")
-        (match_operand:QI 3 "parallel_operand" "S<>,q,q,S<>"))]
-  "valid_parallel_load_store (operands, QImode)"
-  "@
-   ldi1\\t%1,%0\\n||\\tldi2\\t%3,%2
-   sti1\\t%1,%0\\n||\\tsti2\\t%3,%2
-   ldi\\t%1,%0\\n||\\tsti\\t%3,%2
-   ldi\\t%3,%2\\n||\\tsti\\t%1,%0"
-  [(set_attr "type" "load_load,store_store,load_store,store_load")])
-
-;
-; PUSH/POP
-;
-(define_insn "*pushqi"
-  [(set (mem:QI (pre_inc:QI (reg:QI 20)))
-        (match_operand:QI 0 "reg_operand" "r"))]
-  ""
-  "push\\t%0"
-  [(set_attr "type" "push")])
-
-(define_insn "*popqi"
-  [(set (match_operand:QI 0 "reg_operand" "=r")
-        (mem:QI (post_dec:QI (reg:QI 20))))
-   (clobber (reg:CC 21))]
-  ""
-  "pop\\t%0"
-  [(set_attr "type" "pop")])
-
-;
-; ABSI
-;
-(define_expand "absqi2"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (abs:QI (match_operand:QI 1 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-  ""
-  "")
-
-(define_insn "*absqi2_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,c")
-        (abs:QI (match_operand:QI 1 "src_operand" "g,g")))
-   (clobber (reg:CC_NOOV 21))]
-  ""
-  "absi\\t%1,%0"
-  [(set_attr "type" "unarycc,unary")
-   (set_attr "data" "int16,int16")])
-
-(define_insn "*absqi2_test"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (abs:QI (match_operand:QI 1 "src_operand" "g"))
-                         (const_int 0)))
-   (clobber (match_scratch:QI 0 "=d"))]
-  ""
-  "absi\\t%1,%0"
-  [(set_attr "type" "unarycc")
-   (set_attr "data" "int16")])
-
-(define_insn "*absqi2_set"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (abs:QI (match_operand:QI 1 "src_operand" "g"))
-                         (const_int 0)))
-   (set (match_operand:QI 0 "ext_reg_operand" "=d")
-        (abs:QI (match_dup 1)))]
-  ""
-  "absi\\t%1,%0"
-  [(set_attr "type" "unarycc")
-   (set_attr "data" "int16")])        
-
-;
-; NEGI
-;
-(define_expand "negqi2"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (neg:QI (match_operand:QI 1 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-""
-"")
-
-(define_insn "*negqi2_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,c")
-        (neg:QI (match_operand:QI 1 "src_operand" "g,g")))
-   (clobber (reg:CC_NOOV 21))]
-  ""
-  "negi\\t%1,%0"
-  [(set_attr "type" "unarycc,unary")
-   (set_attr "data" "int16,int16")])
-
-(define_insn "*negqi2_test"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (neg:QI (match_operand:QI 1 "src_operand" "g"))
-                         (const_int 0)))
-   (clobber (match_scratch:QI 0 "=d"))]
-  ""
-  "negi\\t%1,%0"
-  [(set_attr "type" "unarycc")
-   (set_attr "data" "int16")])
-
-(define_insn "*negqi2_set"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (neg:QI (match_operand:QI 1 "src_operand" "g"))
-                         (const_int 0)))
-   (set (match_operand:QI 0 "ext_reg_operand" "=d")
-        (neg:QI (match_dup 1)))]
-  ""
-  "negi\\t%1,%0"
-  [(set_attr "type" "unarycc")
-   (set_attr "data" "int16")])        
-
-(define_insn "*negbqi2_clobber"
-  [(set (match_operand:QI 0 "ext_reg_operand" "=d")
-        (neg:QI (match_operand:QI 1 "src_operand" "g")))
-   (use (reg:CC_NOOV 21))
-   (clobber (reg:CC_NOOV 21))]
-  ""
-  "negb\\t%1,%0"
-  [(set_attr "type" "unarycc")
-   (set_attr "data" "int16")])        
-
-;
-; NOT
-;
-(define_expand "one_cmplqi2"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (not:QI (match_operand:QI 1 "lsrc_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "")
-
-(define_insn "*one_cmplqi2_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,c")
-        (not:QI (match_operand:QI 1 "lsrc_operand" "g,g")))
-   (clobber (reg:CC 21))]
-  ""
-  "not\\t%1,%0"
-  [(set_attr "type" "unarycc,unary")
-   (set_attr "data" "uint16,uint16")])
-
-(define_insn "*one_cmplqi2_test"
-  [(set (reg:CC 21)
-        (compare:CC (not:QI (match_operand:QI 1 "lsrc_operand" "g"))
-                    (const_int 0)))
-   (clobber (match_scratch:QI 0 "=d"))]
-  ""
-  "not\\t%1,%0"
-  [(set_attr "type" "unarycc")
-   (set_attr "data" "uint16")])
-
-(define_insn "*one_cmplqi2_set"
-  [(set (reg:CC 21)
-        (compare:CC (not:QI (match_operand:QI 1 "lsrc_operand" "g"))
-                    (const_int 0)))
-   (set (match_operand:QI 0 "ext_reg_operand" "=d")        
-        (not:QI (match_dup 1)))]
-  ""
-  "not\\t%1,%0"
-  [(set_attr "type" "unarycc")
-   (set_attr "data" "uint16")])        
-
-(define_insn "*one_cmplqi2_const_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,c")
-        (match_operand:QI 1 "not_const_operand" "N,N"))
-   (clobber (reg:CC 21))]
-  ""
-  "@
-   not\\t%N1,%0
-   not\\t%N1,%0"
-   [(set_attr "type" "unarycc,unary")
-    (set_attr "data" "not_uint16,not_uint16")])
-
-; movqi can use this for loading an integer that can't normally
-; fit into a 16-bit signed integer.  The drawback is that it cannot
-; go into R0-R11 since that will clobber the CC and movqi shouldn't
-; do that.  This can cause additional reloading but in most cases
-; this will cause only an additional register move.  With the large
-; memory model we require an extra instruction to load DP anyway,
-; if we're loading the constant from memory.  The big advantage of
-; allowing constants that satisfy not_const_operand in movqi, is that
-; it allows andn to be generated more often.
-; However, there is a problem if GCC has decided that it wants
-; to use R0-R11, since we won't have a matching pattern...
-; In interim, we prevent immed_const allowing `N' constants.
-(define_insn "*one_cmplqi2_const_noclobber"
-  [(set (match_operand:QI 0 "std_reg_operand" "=c")
-        (match_operand:QI 1 "not_const_operand" "N"))]
-  ""
-  "not\\t%N1,%0"
-  [(set_attr "type" "unary")
-   (set_attr "data" "not_uint16")])
-
-;
-; ROL
-;
-(define_expand "rotlqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (rotate:QI (match_operand:QI 1 "reg_operand" "")
-                              (match_operand:QI 2 "const_int_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "if (INTVAL (operands[2]) > 4)
-     FAIL; /* Open code as two shifts and an or */
-   if (INTVAL (operands[2]) > 1)
-     {
-        int i;
-	rtx tmp;
-
-        /* If we have 4 or fewer shifts, then it is probably faster
-           to emit separate ROL instructions.  A C3x requires
-           at least 4 instructions (a C4x requires at least 3), to
-           perform a rotation by shifts.  */
-
-	tmp = operands[1];
-        for (i = 0; i < INTVAL (operands[2]) - 1; i++)
-	  {
-   	    tmp = gen_reg_rtx (QImode);
-            emit_insn (gen_rotl_1_clobber (tmp, operands[1]));
-	    operands[1] = tmp;
-	  }
-        emit_insn (gen_rotl_1_clobber (operands[0], tmp));
-        DONE;
-     }")
-
-(define_insn "rotl_1_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,c")
-        (rotate:QI (match_operand:QI 1 "reg_operand" "0,0")
-                   (const_int 1)))
-   (clobber (reg:CC 21))]
-  ""
-  "rol\\t%0"
-  [(set_attr "type" "unarycc,unary")])
-; Default to int16 data attr.
-
-;
-; ROR
-;
-(define_expand "rotrqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (rotatert:QI (match_operand:QI 1 "reg_operand" "")
-                                (match_operand:QI 2 "const_int_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "if (INTVAL (operands[2]) > 4)
-     FAIL; /* Open code as two shifts and an or */
-   if (INTVAL (operands[2]) > 1)
-     {
-        int i;
-	rtx tmp;
- 
-        /* If we have 4 or fewer shifts, then it is probably faster
-           to emit separate ROL instructions.  A C3x requires
-           at least 4 instructions (a C4x requires at least 3), to
-           perform a rotation by shifts.  */
- 
-	tmp = operands[1];
-        for (i = 0; i < INTVAL (operands[2]) - 1; i++)
-	  {
-   	    tmp = gen_reg_rtx (QImode);
-            emit_insn (gen_rotr_1_clobber (tmp, operands[1]));
-	    operands[1] = tmp;
-	  }
-        emit_insn (gen_rotr_1_clobber (operands[0], tmp));
-        DONE;
-     }")
-
-(define_insn "rotr_1_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,c")
-        (rotatert:QI (match_operand:QI 1 "reg_operand" "0,0")
-                     (const_int 1)))
-   (clobber (reg:CC 21))]
-  ""
-  "ror\\t%0"
-  [(set_attr "type" "unarycc,unary")])
-; Default to int16 data attr.
-
-
-;
-; THREE OPERAND INTEGER INSTRUCTIONS
-;
-
-;
-; ADDI
-;
-; This is used by reload when it calls gen_add2_insn for address arithmetic
-; so we must emit the pattern that doesn't clobber CC.
-;
-(define_expand "addqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (plus:QI (match_operand:QI 1 "src_operand" "")
-                            (match_operand:QI 2 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-  ""
-  "legitimize_operands (PLUS, operands, QImode);
-   if (reload_in_progress
-       || (! IS_PSEUDO_REGNO (operands[0]) 
-           && ! IS_EXT_REG (REGNO (operands[0]))))
-   {
-      emit_insn (gen_addqi3_noclobber (operands[0], operands[1], operands[2]));
-      DONE;
-   }")
-
-(define_insn "*addqi3_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0")
-                 (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")))
-   (clobber (reg:CC_NOOV 21))]
-  "valid_operands (PLUS, operands, QImode)"
-  "@
-   addi3\\t%2,%1,%0
-   addi3\\t%2,%1,%0
-   addi\\t%2,%0
-   addi3\\t%2,%1,%0
-   addi3\\t%2,%1,%0
-   addi\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
-; Default to int16 data attr.
-
-(define_insn "*addqi3_test"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                                  (match_operand:QI 2 "src_operand" "JR,rS<>,g"))
-                         (const_int 0)))
-   (clobber (match_scratch:QI 0 "=d,?d,d"))]
-  "valid_operands (PLUS, operands, QImode)"
-  "@
-   addi3\\t%2,%1,%0
-   addi3\\t%2,%1,%0
-   addi\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-; Default to int16 data attr.
-
-; gcc does this in combine.c we just reverse it here
-(define_insn "*cmp_neg"
-  [(set (reg:CC_NOOV 21)
-	(compare:CC_NOOV (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-		         (neg: QI (match_operand:QI 2 "src_operand" "JR,rS<>,g"))))
-   (clobber (match_scratch:QI 0 "=d,?d,d"))]
-  "valid_operands (PLUS, operands, QImode)"
-  "@
-   addi3\\t%2,%1,%0
-   addi3\\t%2,%1,%0
-   addi\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-  
-(define_peephole
-  [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
-                   (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                            (match_operand:QI 2 "src_operand" "JR,rS<>,g")))
-              (clobber (reg:CC_NOOV 21))])
-   (set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (match_dup 0) (const_int 0)))]
-  "valid_operands (PLUS, operands, QImode)"
-  "@
-   addi3\\t%2,%1,%0
-   addi3\\t%2,%1,%0
-   addi\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-
-(define_insn "*addqi3_set"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                                  (match_operand:QI 2 "src_operand" "JR,rS<>,g"))
-                         (const_int 0)))
-   (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
-        (plus:QI (match_dup 1) (match_dup 2)))]
-  "valid_operands (PLUS, operands, QImode)"
-  "@
-   addi3\\t%2,%1,%0
-   addi3\\t%2,%1,%0
-   addi\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-; Default to int16 data attr.
-
-; This pattern is required primarily for manipulating the stack pointer
-; where GCC doesn't expect CC to be clobbered or for calculating
-; addresses during reload.
-(define_insn "addqi3_noclobber"
-  [(set (match_operand:QI 0 "std_reg_operand" "=c,?c,c")
-        (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                 (match_operand:QI 2 "src_operand" "JR,rS<>,g")))]
-  "valid_operands (PLUS, operands, QImode)"
-  "@
-   addi3\\t%2,%1,%0
-   addi3\\t%2,%1,%0
-   addi\\t%2,%0"
-  [(set_attr "type" "binary,binary,binary")])
-; Default to int16 data attr.
-
-
-; This pattern is required during reload when eliminate_regs_in_insn
-; effectively converts a move insn into an add insn when the src
-; operand is the frame pointer plus a constant.  Without this
-; pattern, gen_addqi3 can be called with a register for operand0
-; that can clobber CC.
-; For example, we may have (set (mem (reg ar0)) (reg 99))
-; with (set (reg 99) (plus (reg ar3) (const_int 8)))
-; Now since ar3, the frame pointer, is unchanging within the function,
-; (plus (reg ar3) (const_int 8)) is considered a constant.
-; eliminate_regs_in_insn substitutes this constant to give
-; (set (mem (reg ar0)) (plus (reg ar3) (const_int 8))).
-; This is an invalid C4x insn but if we don't provide a pattern
-; for it, it will be considered to be a move insn for reloading.
-; The nasty bit is that a GENERAL_REGS class register, say r0,
-; may be allocated to reload the PLUS and thus gen_reload will
-; emit an add insn that may clobber CC.
-(define_insn "*addqi3_noclobber_reload"
-  [(set (match_operand:QI 0 "general_operand" "=c,?c,c")
-        (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                 (match_operand:QI 2 "src_operand" "JR,rS<>,g")))]
-  "reload_in_progress"
-  "@
-   addi3\\t%2,%1,%0
-   addi3\\t%2,%1,%0
-   addi\\t%2,%0"
-  [(set_attr "type" "binary,binary,binary")])
-; Default to int16 data attr.
-
-
-(define_insn "*addqi3_carry_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0")
-                 (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")))
-   (use (reg:CC_NOOV 21))
-   (clobber (reg:CC_NOOV 21))]
-  "valid_operands (PLUS, operands, QImode)"
-  "@
-   addc3\\t%2,%1,%0
-   addc3\\t%2,%1,%0
-   addc\\t%2,%0
-   addc3\\t%2,%1,%0
-   addc3\\t%2,%1,%0
-   addc\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
-; Default to int16 data attr.
-
-
-;
-; SUBI/SUBRI
-;
-(define_expand "subqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (minus:QI (match_operand:QI 1 "src_operand" "")
-                             (match_operand:QI 2 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-  ""
-  "legitimize_operands (MINUS, operands, QImode);")
-
-(define_insn "*subqi3_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,d,c,?c,c,c")
-        (minus:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,g,rR,rS<>,0,g")
-                  (match_operand:QI 2 "src_operand" "JR,rS<>,g,0,JR,rS<>,g,0")))
-   (clobber (reg:CC_NOOV 21))]
-  "valid_operands (MINUS, operands, QImode)"
-  "@
-   subi3\\t%2,%1,%0
-   subi3\\t%2,%1,%0
-   subi\\t%2,%0
-   subri\\t%1,%0
-   subi3\\t%2,%1,%0
-   subi3\\t%2,%1,%0
-   subi\\t%2,%0
-   subri\\t%1,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc,binary,binary,binary,binary")])
-; Default to int16 data attr.
-
-(define_insn "*subqi3_test"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,g")
-                                   (match_operand:QI 2 "src_operand" "JR,rS<>,g,0"))
-                         (const_int 0)))
-   (clobber (match_scratch:QI 0 "=d,?d,d,d"))]
-  "valid_operands (MINUS, operands, QImode)"
-  "@
-   subi3\\t%2,%1,%0
-   subi3\\t%2,%1,%0
-   subi\\t%2,%0
-   subri\\t%1,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
-; Default to int16 data attr.
-
-(define_peephole
-  [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d,d")
-                   (minus:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,g")
-                             (match_operand:QI 2 "src_operand" "JR,rS<>,g,0")))
-              (clobber (reg:CC_NOOV 21))])
-   (set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (match_dup 0) (const_int 0)))]
-  "valid_operands (MINUS, operands, QImode)"
-  "@
-   subi3\\t%2,%1,%0
-   subi3\\t%2,%1,%0
-   subi\\t%2,%0
-   subri\\t%1,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
-  
-(define_insn "*subqi3_set"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,g")
-                                   (match_operand:QI 2 "src_operand" "JR,rS<>,g,0"))
-                         (const_int 0)))
-   (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d,d")
-        (minus:QI (match_dup 1)
-                  (match_dup 2)))]
-  "valid_operands (MINUS, operands, QImode)"
-  "@
-   subi3\\t%2,%1,%0
-   subi3\\t%2,%1,%0
-   subi\\t%2,%0
-   subri\\t%1,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
-; Default to int16 data attr.
-
-(define_insn "*subqi3_carry_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,d,c,?c,c,c")
-        (minus:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,g,rR,rS<>,0,g")
-                  (match_operand:QI 2 "src_operand" "JR,rS<>,g,0,JR,rS<>,g,0")))
-   (use (reg:CC_NOOV 21))
-   (clobber (reg:CC_NOOV 21))]
-  "valid_operands (MINUS, operands, QImode)"
-  "@
-   subb3\\t%2,%1,%0
-   subb3\\t%2,%1,%0
-   subb\\t%2,%0
-   subrb\\t%1,%0
-   subb3\\t%2,%1,%0
-   subb3\\t%2,%1,%0
-   subb\\t%2,%0
-   subrb\\t%1,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc,binary,binary,binary,binary")])
-; Default to int16 data attr.
-
-(define_insn "*subqi3_carry_set"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,g")
-                                   (match_operand:QI 2 "src_operand" "JR,rS<>,g,0"))
-                         (const_int 0)))
-   (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d,d")
-        (minus:QI (match_dup 1)
-                  (match_dup 2)))
-   (use (reg:CC_NOOV 21))]
-  "valid_operands (MINUS, operands, QImode)"
-  "@
-   subb3\\t%2,%1,%0
-   subb3\\t%2,%1,%0
-   subb\\t%2,%0
-   subrb\\t%1,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
-; Default to int16 data attr.
-
-;
-; MPYI
-;
-(define_expand "mulqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (mult:QI (match_operand:QI 1 "src_operand" "")
-                            (match_operand:QI 2 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-  ""
-  "if (TARGET_MPYI || (GET_CODE (operands[2]) == CONST_INT
-       && exact_log2 (INTVAL (operands[2])) >= 0))
-     legitimize_operands (MULT, operands, QImode);
-   else
-     {        
-       if (GET_CODE (operands[2]) == CONST_INT)
-         {
-          /* Let GCC try to synthesise the multiplication using shifts
-             and adds.  In most cases this will be more profitable than
-             using the C3x MPYI.  */
-            FAIL;
-         }
-       if (operands[1] == operands[2])
-         {
-            /* Do the squaring operation in-line.  */
-            emit_insn (gen_sqrqi2_inline (operands[0], operands[1]));
-            DONE;
-         }
-       if (TARGET_INLINE)
-         {
-            emit_insn (gen_mulqi3_inline (operands[0], operands[1],
-                                          operands[2]));
-            DONE;
-         }
-       c4x_emit_libcall3 (MULQI3_LIBCALL, MULT, QImode, operands);
-       DONE;
-     }
-  ")
-
-(define_insn "*mulqi3_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (mult:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0")
-                 (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")))
-   (clobber (reg:CC_NOOV 21))]
-  "valid_operands (MULT, operands, QImode)"
-  "*
-  if (which_alternative == 2 || which_alternative == 5)
-    {
-      if (TARGET_C3X
-          && GET_CODE (operands[2]) == CONST_INT
-          && exact_log2 (INTVAL (operands[2])) >= 0)
-        return \"ash\\t%L2,%0\";
-      else
-        return \"mpyi\\t%2,%0\";
-    }
-  else
-      return \"mpyi3\\t%2,%1,%0\";"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
-; Default to int16 data attr.
-
-(define_insn "*mulqi3_test"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (mult:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                                  (match_operand:QI 2 "src_operand" "JR,rS<>,g"))
-                         (const_int 0)))
-   (clobber (match_scratch:QI 0 "=d,?d,d"))]
-  "valid_operands (MULT, operands, QImode)"
-  "*
-  if (which_alternative == 2)
-    {
-      if (TARGET_C3X 
-          && GET_CODE (operands[2]) == CONST_INT
-          && exact_log2 (INTVAL (operands[2])) >= 0)
-        return \"ash\\t%L2,%0\";
-      else
-        return \"mpyi\\t%2,%0\";
-    } 
-  else
-      return \"mpyi3\\t%2,%1,%0\";"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-; Default to int16 data attr.
-
-(define_insn "*mulqi3_set"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (mult:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                                  (match_operand:QI 2 "src_operand" "JR,rS<>,g"))
-                         (const_int 0)))
-   (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
-        (mult:QI (match_dup 1)
-                 (match_dup 2)))]
-  "valid_operands (MULT, operands, QImode)"
-  "*
-  if (which_alternative == 2)
-    {
-      if (TARGET_C3X 
-          && GET_CODE (operands[2]) == CONST_INT
-          && exact_log2 (INTVAL (operands[2])) >= 0)
-        return \"ash\\t%L2,%0\";
-      else
-        return \"mpyi\\t%2,%0\";
-    }
-    else
-        return \"mpyi3\\t%2,%1,%0\";"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-; Default to int16 data attr.
-
-; The C3x multiply instruction assumes 24-bit signed integer operands
-; and the 48-bit result is truncated to 32-bits.
-(define_insn "*mulqi3_24_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (mult:QI
-         (sign_extend:QI
-          (and:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0")
-                  (const_int 16777215)))
-         (sign_extend:QI
-          (and:QI (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")
-                  (const_int 16777215)))))
-   (clobber (reg:CC_NOOV 21))]
-  "TARGET_C3X && valid_operands (MULT, operands, QImode)"
-  "@
-   mpyi3\\t%2,%1,%0
-   mpyi3\\t%2,%1,%0
-   mpyi\\t%2,%0
-   mpyi3\\t%2,%1,%0
-   mpyi3\\t%2,%1,%0
-   mpyi\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
-; Default to int16 data attr.
-
-
-; Fast square function for C3x where TARGET_MPYI not asserted
-(define_expand "sqrqi2_inline"
-  [(set (match_dup 7) (match_operand:QI 1 "src_operand" ""))
-   (parallel [(set (match_dup 3)
-                   (lshiftrt:QI (match_dup 7) (const_int 16)))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_dup 2)
-                   (and:QI (match_dup 7) (const_int 65535)))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_dup 4)
-                   (mult:QI (sign_extend:QI (and:QI (match_dup 2) 
-                                                    (const_int 16777215)))
-                            (sign_extend:QI (and:QI (match_dup 2) 
-                                                    (const_int 16777215)))))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 5)
-                   (mult:QI (sign_extend:QI (and:QI (match_dup 2) 
-                                                    (const_int 16777215)))
-                            (sign_extend:QI (and:QI (match_dup 3) 
-                                                    (const_int 16777215)))))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 6)
-                   (ashift:QI (match_dup 5) (const_int 17)))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (plus:QI (match_dup 4) (match_dup 6)))
-              (clobber (reg:CC_NOOV 21))])]
-  ""
-  "
-  operands[2] = gen_reg_rtx (QImode); /* a = val & 0xffff */
-  operands[3] = gen_reg_rtx (QImode); /* b = val >> 16 */
-  operands[4] = gen_reg_rtx (QImode); /* a * a */
-  operands[5] = gen_reg_rtx (QImode); /* a * b */
-  operands[6] = gen_reg_rtx (QImode); /* (a * b) << 17 */
-  operands[7] = gen_reg_rtx (QImode); /* val */
-  ")
-
-; Inlined integer multiply for C3x
-(define_expand "mulqi3_inline"
-  [(set (match_dup 12) (const_int -16))
-   (set (match_dup 13) (match_operand:QI 1 "src_operand" ""))
-   (set (match_dup 14) (match_operand:QI 2 "src_operand" ""))
-   (parallel [(set (match_dup 4)
-                   (lshiftrt:QI (match_dup 13) (neg:QI (match_dup 12))))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_dup 6)
-                   (lshiftrt:QI (match_dup 14) (neg:QI (match_dup 12))))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_dup 3)
-                   (and:QI (match_dup 13)
-                           (const_int 65535)))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_dup 5)
-                   (and:QI (match_dup 14) 
-                           (const_int 65535)))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_dup 7)
-                   (mult:QI (sign_extend:QI (and:QI (match_dup 4) 
-                                                    (const_int 16777215)))
-                            (sign_extend:QI (and:QI (match_dup 5) 
-                                                    (const_int 16777215)))))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 8)
-                   (mult:QI (sign_extend:QI (and:QI (match_dup 3) 
-                                                    (const_int 16777215)))
-                            (sign_extend:QI (and:QI (match_dup 5) 
-                                                    (const_int 16777215)))))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 9)
-                   (mult:QI (sign_extend:QI (and:QI (match_dup 3) 
-                                                    (const_int 16777215)))
-                            (sign_extend:QI (and:QI (match_dup 6) 
-                                                    (const_int 16777215)))))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 10)
-                   (plus:QI (match_dup 7) (match_dup 9)))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 11)
-                   (ashift:QI (match_dup 10) (const_int 16)))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (plus:QI (match_dup 8) (match_dup 11)))
-              (clobber (reg:CC_NOOV 21))])]
-  "TARGET_C3X"
-  "
-  operands[3] = gen_reg_rtx (QImode); /* a = arg1 & 0xffff */
-  operands[4] = gen_reg_rtx (QImode); /* b = arg1 >> 16 */
-  operands[5] = gen_reg_rtx (QImode); /* a = arg2 & 0xffff */
-  operands[6] = gen_reg_rtx (QImode); /* b = arg2 >> 16 */
-  operands[7] = gen_reg_rtx (QImode); /* b * c */
-  operands[8] = gen_reg_rtx (QImode); /* a * c */
-  operands[9] = gen_reg_rtx (QImode); /* a * d */
-  operands[10] = gen_reg_rtx (QImode); /* b * c + a * d */
-  operands[11] = gen_reg_rtx (QImode); /* (b *c + a * d) << 16 */
-  operands[12] = gen_reg_rtx (QImode); /* -16 */
-  operands[13] = gen_reg_rtx (QImode); /* arg1 */
-  operands[14] = gen_reg_rtx (QImode); /* arg2 */
-  ")
-
-;
-; MPYSHI (C4x only)
-;
-(define_expand "smulqi3_highpart"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (truncate:QI
-                    (lshiftrt:HI
-                     (mult:HI
-                      (sign_extend:HI (match_operand:QI 1 "src_operand" ""))
-                      (sign_extend:HI (match_operand:QI 2 "src_operand" "")))
-                 (const_int 32))))
-              (clobber (reg:CC_NOOV 21))])]
- ""
- "legitimize_operands (MULT, operands, QImode);
-  if (TARGET_C3X)
-    {
-       c4x_emit_libcall_mulhi (SMULHI3_LIBCALL, SIGN_EXTEND, QImode, operands);
-       DONE;
-    }
- ")
-
-(define_insn "*smulqi3_highpart_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (truncate:QI 
-         (lshiftrt:HI
-          (mult:HI
-           (sign_extend:HI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0"))
-           (sign_extend:HI (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")))
-      (const_int 32))))
-   (clobber (reg:CC_NOOV 21))]
-  "! TARGET_C3X && valid_operands (MULT, operands, QImode)"
-  "@
-   mpyshi3\\t%2,%1,%0
-   mpyshi3\\t%2,%1,%0
-   mpyshi\\t%2,%0
-   mpyshi3\\t%2,%1,%0
-   mpyshi3\\t%2,%1,%0
-   mpyshi\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
-   (set_attr "data" "int16,int16,int16,int16,int16,int16")])
-
-;
-; MPYUHI (C4x only)
-;
-(define_expand "umulqi3_highpart"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-               (truncate:QI
-                (lshiftrt:HI
-                 (mult:HI
-                  (zero_extend:HI (match_operand:QI 1 "src_operand" ""))
-                  (zero_extend:HI (match_operand:QI 2 "lsrc_operand" "")))
-                 (const_int 32))))
-              (clobber (reg:CC_NOOV 21))])]
- ""
- "legitimize_operands (MULT, operands, QImode);
-  if (TARGET_C3X) 
-    {
-      c4x_emit_libcall_mulhi (UMULHI3_LIBCALL, ZERO_EXTEND, QImode, operands);
-      DONE;
-    }
- ")
-
-(define_insn "*umulqi3_highpart_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (truncate:QI
-         (lshiftrt:HI
-          (mult:HI 
-           (zero_extend:HI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0"))
-           (zero_extend:HI (match_operand:QI 2 "lsrc_operand" "JR,rS<>,g,JR,rS<>,g")))
-          (const_int 32))))
-   (clobber (reg:CC_NOOV 21))]
-  "! TARGET_C3X && valid_operands (MULT, operands, QImode)"
-  "@
-   mpyuhi3\\t%2,%1,%0
-   mpyuhi3\\t%2,%1,%0
-   mpyuhi\\t%2,%0
-   mpyuhi3\\t%2,%1,%0
-   mpyuhi3\\t%2,%1,%0
-   mpyuhi\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
-   (set_attr "data" "uint16,uint16,uint16,uint16,uint16,uint16")])
-
-;
-; AND
-;
-(define_expand "andqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (and:QI (match_operand:QI 1 "src_operand" "")
-                           (match_operand:QI 2 "tsrc_operand" "")))
-              (clobber (reg:CC 21))])]
- ""
- "legitimize_operands (AND, operands, QImode);")
-
-(define_insn "*andqi3_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,d,c,?c,c,c")
-        (and:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,0,rR,rS<>,0,0")
-                (match_operand:QI 2 "tsrc_operand" "JR,rS<>,N,rLm,JR,rS<>,N,rLm")))
-   (clobber (reg:CC 21))]
-  "valid_operands (AND, operands, QImode)"
-  "@
-   and3\\t%2,%1,%0
-   and3\\t%2,%1,%0
-   andn\\t%N2,%0
-   and\\t%2,%0
-   and3\\t%2,%1,%0
-   and3\\t%2,%1,%0
-   andn\\t%N2,%0
-   and\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc,binary,binary,binary,binary")
-   (set_attr "data" "int16,uint16,not_uint16,uint16,int16,uint16,not_uint16,uint16")])
-
-(define_insn "*andqi3_test"
-  [(set (reg:CC 21)
-        (compare:CC (and:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,r")
-                            (match_operand:QI 2 "tsrc_operand" "JR,rS<>,N,rLm"))
-                    (const_int 0)))
-   (clobber (match_scratch:QI 0 "=X,X,d,X"))]
-  "valid_operands (AND, operands, QImode)"
-  "@
-   tstb3\\t%2,%1
-   tstb3\\t%2,%1
-   andn\\t%N2,%0
-   tstb\\t%2,%1"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")
-   (set_attr "data" "int16,uint16,not_uint16,uint16")])
-
-(define_peephole
-  [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d,d")
-                   (and:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,0")
-                           (match_operand:QI 2 "tsrc_operand" "JR,rS<>,N,rLm")))
-              (clobber (reg:CC 21))])
-   (set (reg:CC 21)
-        (compare:CC (match_dup 0) (const_int 0)))]
-  "valid_operands (AND, operands, QImode)"
-  "@
-   and3\\t%2,%1,%0
-   and3\\t%2,%1,%0
-   andn\\t%N2,%0
-   and\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")
-   (set_attr "data" "int16,uint16,not_uint16,uint16")])
-  
-(define_insn "*andqi3_set"
-  [(set (reg:CC 21)
-        (compare:CC (and:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,0")
-                            (match_operand:QI 2 "tsrc_operand" "JR,rS<>,N,rLm"))
-                    (const_int 0)))
-   (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d,d")
-        (and:QI (match_dup 1)
-                (match_dup 2)))]
-  "valid_operands (AND, operands, QImode)"
-  "@
-   and3\\t%2,%1,%0
-   and3\\t%2,%1,%0
-   andn\\t%N2,%0
-   and\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")
-   (set_attr "data" "int16,uint16,not_uint16,uint16")])
-
-;
-; ANDN
-;
-; NB, this insn doesn't have commutative operands, but valid_operands
-; assumes that the code AND does.  We might have to kludge this if
-; we make valid_operands stricter.
-(define_insn "*andnqi3_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm,JR,rS<>,rLm"))
-                (match_operand:QI 1 "src_operand" "rR,rS<>,0,rR,rS<>,0")))
-   (clobber (reg:CC 21))]
-  "valid_operands (AND, operands, QImode)"
-  "@
-   andn3\\t%2,%1,%0
-   andn3\\t%2,%1,%0
-   andn\\t%2,%0
-   andn3\\t%2,%1,%0
-   andn3\\t%2,%1,%0
-   andn\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
-   (set_attr "data" "int16,uint16,uint16,int16,uint16,uint16")])
-
-(define_insn "*andnqi3_test"
-  [(set (reg:CC 21)
-        (compare:CC (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm"))
-                            (match_operand:QI 1 "src_operand" "rR,rS<>,0"))
-                    (const_int 0)))
-   (clobber (match_scratch:QI 0 "=d,?d,d"))]
-  "valid_operands (AND, operands, QImode)"
-  "@
-   andn3\\t%2,%1,%0
-   andn3\\t%2,%1,%0
-   andn\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")
-   (set_attr "data" "int16,uint16,uint16")])
-
-(define_insn "*andnqi3_set"
-  [(set (reg:CC 21)
-        (compare:CC (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm"))
-                            (match_operand:QI 1 "src_operand" "rR,rS<>,0"))
-                    (const_int 0)))
-   (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
-        (and:QI (not:QI (match_dup 2))
-                (match_dup 1)))]
-  "valid_operands (AND, operands, QImode)"
-  "@
-   andn3\\t%2,%1,%0
-   andn3\\t%2,%1,%0
-   andn\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")
-   (set_attr "data" "int16,uint16,uint16")])
-
-;
-; OR
-;
-(define_expand "iorqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (ior:QI (match_operand:QI 1 "src_operand" "")
-                           (match_operand:QI 2 "lsrc_operand" "")))
-              (clobber (reg:CC 21))])]
- ""
- "legitimize_operands (IOR, operands, QImode);")
-
-(define_insn "*iorqi3_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (ior:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0")
-                (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm,JR,rS<>,rLm")))
-   (clobber (reg:CC 21))]
-  "valid_operands (IOR, operands, QImode)"
-  "@
-   or3\\t%2,%1,%0
-   or3\\t%2,%1,%0
-   or\\t%2,%0
-   or3\\t%2,%1,%0
-   or3\\t%2,%1,%0
-   or\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
-   (set_attr "data" "int16,uint16,uint16,int16,uint16,uint16")])
-
-(define_insn "*iorqi3_test"
-  [(set (reg:CC 21)
-        (compare:CC (ior:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                            (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm"))
-                    (const_int 0)))
-   (clobber (match_scratch:QI 0 "=d,?d,d"))]
-  "valid_operands (IOR, operands, QImode)"
-  "@
-   or3\\t%2,%1,%0
-   or3\\t%2,%1,%0
-   or\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")
-   (set_attr "data" "int16,uint16,uint16")])
-
-(define_peephole
-  [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
-                   (ior:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                           (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm")))
-              (clobber (reg:CC 21))])
-   (set (reg:CC 21)
-        (compare:CC (match_dup 0) (const_int 0)))]
-  "valid_operands (IOR, operands, QImode)"
-  "@
-   or3\\t%2,%1,%0
-   or3\\t%2,%1,%0
-   or\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")
-   (set_attr "data" "int16,uint16,uint16")])
-  
-(define_insn "*iorqi3_set"
-  [(set (reg:CC 21)
-        (compare:CC (ior:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                            (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm"))
-                    (const_int 0)))
-   (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
-        (ior:QI (match_dup 1)
-                (match_dup 2)))]
-  "valid_operands (IOR, operands, QImode)"
-  "@
-   or3\\t%2,%1,%0
-   or3\\t%2,%1,%0
-   or\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")
-   (set_attr "data" "int16,uint16,uint16")])
-
-; This pattern is used for loading symbol references in several parts. 
-(define_insn "iorqi3_noclobber"
-  [(set (match_operand:QI 0 "std_reg_operand" "=c,?c,c")
-        (ior:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm")))]
-  "valid_operands (IOR, operands, QImode)"
-  "@
-   or3\\t%2,%1,%0
-   or3\\t%2,%1,%0
-   or\\t%2,%0"
-  [(set_attr "type" "binary,binary,binary")
-   (set_attr "data" "int16,uint16,uint16")])
-
-;
-; XOR
-;
-(define_expand "xorqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (xor:QI (match_operand:QI 1 "src_operand" "")
-                           (match_operand:QI 2 "lsrc_operand" "")))
-              (clobber (reg:CC 21))])]
- ""
- "legitimize_operands (XOR, operands, QImode);")
-
-(define_insn "*xorqi3_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (xor:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0,rR,rS<>,0")
-                (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm,JR,rS<>,rLm")))
-   (clobber (reg:CC 21))]
-  "valid_operands (XOR, operands, QImode)"
-  "@
-   xor3\\t%2,%1,%0
-   xor3\\t%2,%1,%0
-   xor\\t%2,%0
-   xor3\\t%2,%1,%0
-   xor3\\t%2,%1,%0
-   xor\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
-   (set_attr "data" "int16,uint16,uint16,int16,uint16,uint16")])
-
-(define_insn "*xorqi3_test"
-  [(set (reg:CC 21)
-        (compare:CC (xor:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                            (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm"))
-                    (const_int 0)))
-   (clobber (match_scratch:QI 0 "=d,?d,d"))]
-  "valid_operands (XOR, operands, QImode)"
-  "@
-   xor3\\t%2,%1,%0
-   xor3\\t%2,%1,%0
-   xor\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")
-   (set_attr "data" "int16,uint16,uint16")])
-
-(define_insn "*xorqi3_set"
-  [(set (reg:CC 21)
-        (compare:CC (xor:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
-                            (match_operand:QI 2 "lsrc_operand" "JR,rS<>,rLm"))
-                    (const_int 0)))
-   (set (match_operand:QI 0 "ext_reg_operand" "=d,?d,d")
-        (xor:QI (match_dup 1)
-                (match_dup 2)))]
-  "valid_operands (XOR, operands, QImode)"
-  "@
-   xor3\\t%2,%1,%0
-   xor3\\t%2,%1,%0
-   xor\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")
-   (set_attr "data" "int16,uint16,uint16")])
-
-;
-; LSH/ASH (left)
-;
-; The C3x and C4x have two shift instructions ASH and LSH
-; If the shift count is positive, a left shift is performed
-; otherwise a right shift is performed.  The number of bits
-; shifted is determined by the seven LSBs of the shift count.
-; If the absolute value of the count is 32 or greater, the result
-; using the LSH instruction is zero; with the ASH insn the result
-; is zero or negative 1.   Note that the ISO C standard allows 
-; the result to be machine dependent whenever the shift count
-; exceeds the size of the object.
-(define_expand "ashlqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (ashift:QI (match_operand:QI 1 "src_operand" "")
-                              (match_operand:QI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
- ""
- "legitimize_operands (ASHIFT, operands, QImode);")
-
-(define_insn "*ashlqi3_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (ashift:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,rR,rS<>,0")
-                   (match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")))
-   (clobber (reg:CC 21))]
-  "valid_operands (ASHIFT, operands, QImode)"
-  "@
-   ash3\\t%2,%1,%0
-   ash3\\t%2,%1,%0
-   ash\\t%2,%0
-   ash3\\t%2,%1,%0
-   ash3\\t%2,%1,%0
-   ash\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
-; Default to int16 data attr.
-
-(define_insn "*ashlqi3_set"
-  [(set (reg:CC 21)
-        (compare:CC
-          (ashift:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0")
-                     (match_operand:QI 2 "src_operand" "JR,rS<>,g"))
-          (const_int 0)))
-   (set (match_operand:QI 0 "reg_operand" "=d,?d,d")
-        (ashift:QI (match_dup 1)
-                   (match_dup 2)))]
-  "valid_operands (ASHIFT, operands, QImode)"
-  "@
-   ash3\\t%2,%1,%0
-   ash3\\t%2,%1,%0
-   ash\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-; Default to int16 data attr.
-
-; This is only used by lshrhi3_reg where we need a LSH insn that will
-; shift both ways.
-(define_insn "*lshlqi3_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (ashift:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,rR,rS<>,0")
-                   (unspec [(match_operand:QI 2 "src_operand" "JR,rS<>,g,JR,rS<>,g")] 3)))
-   (clobber (reg:CC 21))]
-  "valid_operands (ASHIFT, operands, QImode)"
-  "@
-   lsh3\\t%2,%1,%0
-   lsh3\\t%2,%1,%0
-   lsh\\t%2,%0
-   lsh3\\t%2,%1,%0
-   lsh3\\t%2,%1,%0
-   lsh\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
-; Default to int16 data attr.
-
-;
-; LSH (right)
-;
-; Logical right shift on the C[34]x works by negating the shift count,
-; then emitting a right shift with the shift count negated.  This means
-; that all actual shift counts in the RTL will be positive.
-;
-(define_expand "lshrqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (lshiftrt:QI (match_operand:QI 1 "src_operand" "")
-                                (match_operand:QI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "legitimize_operands (LSHIFTRT, operands, QImode);")
-
-; When the shift count is greater than the size of the word
-; the result can be implementation specific
-(define_insn "*lshrqi3_const_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,c,?d,?c")
-        (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,0,r,r")
-                     (match_operand:QI 2 "const_int_operand" "n,n,J,J")))
-   (clobber (reg:CC 21))]
-  "valid_operands (LSHIFTRT, operands, QImode)"
-  "@
-   lsh\\t%n2,%0
-   lsh\\t%n2,%0
-   lsh3\\t%n2,%1,%0
-   lsh3\\t%n2,%1,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
-
-; When the shift count is greater than the size of the word
-; the result can be implementation specific
-(define_insn "*lshrqi3_const_set"
-  [(set (reg:CC 21)
-        (compare:CC
-          (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,r")
-                       (match_operand:QI 2 "const_int_operand" "n,J"))
-          (const_int 0)))
-   (set (match_operand:QI 0 "reg_operand" "=?d,d")
-        (lshiftrt:QI (match_dup 1)
-                     (match_dup 2)))]
-  "valid_operands (LSHIFTRT, operands, QImode)"
-  "@
-   lsh\\t%n2,%0
-   lsh3\\t%n2,%1,%0"
-  [(set_attr "type" "binarycc,binarycc")])
-
-(define_insn "*lshrqi3_nonconst_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (lshiftrt:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,rR,rS<>,0")
-                     (neg:QI (match_operand:QI 2 "src_operand" "R,rS<>,rm,R,rS<>,rm"))))
-   (clobber (reg:CC 21))]
-  "valid_operands (LSHIFTRT, operands, QImode)"
-  "@
-   lsh3\\t%2,%1,%0
-   lsh3\\t%2,%1,%0
-   lsh\\t%2,%0
-   lsh3\\t%2,%1,%0
-   lsh3\\t%2,%1,%0
-   lsh\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
-; Default to int16 data attr.
-
-;
-; ASH (right)
-;
-; Arithmetic right shift on the C[34]x works by negating the shift count,
-; then emitting a right shift with the shift count negated.  This means
-; that all actual shift counts in the RTL will be positive.
-
-(define_expand "ashrqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (ashiftrt:QI (match_operand:QI 1 "src_operand" "")
-                                (match_operand:QI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "legitimize_operands (ASHIFTRT, operands, QImode);")
-
-; When the shift count is greater than the size of the word
-; the result can be implementation specific
-(define_insn "*ashrqi3_const_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,c,?d,?c")
-        (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,0,r,r")
-                     (match_operand:QI 2 "const_int_operand" "n,n,J,J")))
-   (clobber (reg:CC 21))]
-  "valid_operands (ASHIFTRT, operands, QImode)"
-  "@
-   ash\\t%n2,%0
-   ash\\t%n2,%0
-   ash3\\t%n2,%1,%0
-   ash3\\t%n2,%1,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
-
-; When the shift count is greater than the size of the word
-; the result can be implementation specific
-(define_insn "*ashrqi3_const_set"
-  [(set (reg:CC 21)
-        (compare:CC
-          (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,r")
-                       (match_operand:QI 2 "const_int_operand" "n,J"))
-          (const_int 0)))
-   (set (match_operand:QI 0 "reg_operand" "=?d,d")
-        (ashiftrt:QI (match_dup 1)
-                     (match_dup 2)))]
-  "valid_operands (ASHIFTRT, operands, QImode)"
-  "@
-   ash\\t%n2,%0
-   ash3\\t%n2,%1,%0"
-  [(set_attr "type" "binarycc,binarycc")])
-
-(define_insn "*ashrqi3_nonconst_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,?d,d,c,?c,c")
-        (ashiftrt:QI (match_operand:QI 1 "src_operand" "rR,rS<>,0,rR,rS<>,0")
-                     (neg:QI (match_operand:QI 2 "src_operand" "R,rS<>,rm,R,rS<>,rm"))))
-   (clobber (reg:CC 21))]
-  "valid_operands (ASHIFTRT, operands, QImode)"
-  "@
-   ash3\\t%2,%1,%0
-   ash3\\t%2,%1,%0
-   ash\\t%2,%0
-   ash3\\t%2,%1,%0
-   ash3\\t%2,%1,%0
-   ash\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
-; Default to int16 data attr.
-
-;
-; CMPI
-;
-; Unfortunately the C40 doesn't allow cmpi3 7, *ar0++ so the next best
-; thing would be to get the small constant loaded into a register (say r0)
-; so that it could be hoisted out of the loop so that we only
-; would need to do cmpi3 *ar0++, r0.  Now the loop optimisation pass
-; comes before the flow pass (which finds autoincrements) so we're stuck.
-; Ideally, GCC requires another loop optimisation pass (preferably after
-; reload) so that it can hoist invariants out of loops.
-; The current solution modifies legitimize_operands () so that small
-; constants are forced into a pseudo register.
-; 
-(define_expand "cmpqi"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:QI 0 "src_operand" "")
-                    (match_operand:QI 1 "src_operand" "")))]
-  ""
-  "legitimize_operands (COMPARE, operands, QImode);
-   c4x_compare_op0 = operands[0];
-   c4x_compare_op1 = operands[1];
-   DONE;")
-
-(define_insn "*cmpqi_test"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:QI 0 "src_operand" "rR,?rS<>,r")
-                    (match_operand:QI 1 "src_operand" "JR,rS<>,g")))]
-  "valid_operands (COMPARE, operands, QImode)"
-  "@
-   cmpi3\\t%1,%0
-   cmpi3\\t%1,%0
-   cmpi\\t%1,%0"
-  [(set_attr "type" "compare,compare,compare")])
-
-(define_insn "*cmpqi_test_noov"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (match_operand:QI 0 "src_operand" "rR,?rS<>,r")
-                         (match_operand:QI 1 "src_operand" "JR,rS<>,g")))]
-  "valid_operands (COMPARE, operands, QImode)"
-  "@
-   cmpi3\\t%1,%0
-   cmpi3\\t%1,%0
-   cmpi\\t%1,%0"
-  [(set_attr "type" "compare,compare,compare")])
-
-(define_expand "udivqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (udiv:QI (match_operand:QI 1 "src_operand" "")
-                            (match_operand:QI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall3 (UDIVQI3_LIBCALL, UDIV, QImode, operands);
-   DONE;")
-
-(define_expand "divqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (div:QI (match_operand:QI 1 "src_operand" "")
-                            (match_operand:QI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall3 (DIVQI3_LIBCALL, DIV, QImode, operands);
-   DONE;")
-
-(define_expand "umodqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (umod:QI (match_operand:QI 1 "src_operand" "")
-                            (match_operand:QI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall3 (UMODQI3_LIBCALL, UMOD, QImode, operands);
-   DONE;")
-
-(define_expand "modqi3"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (mod:QI (match_operand:QI 1 "src_operand" "")
-                           (match_operand:QI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall3 (MODQI3_LIBCALL, MOD, QImode, operands);
-   DONE;")
-
-(define_expand "ffsqi2"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (ffs:QI (match_operand:QI 1 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall (FFS_LIBCALL, FFS, QImode, QImode, 2, operands);
-   DONE;")
-
-;
-; BIT-FIELD INSTRUCTIONS
-;
-
-;
-; LBx/LHw (C4x only)
-;
-(define_expand "extv"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (sign_extract:QI (match_operand:QI 1 "src_operand" "")
-                                    (match_operand:QI 2 "const_int_operand" "")
-                                    (match_operand:QI 3 "const_int_operand" "")))
-              (clobber (reg:CC 21))])]
- "! TARGET_C3X"
- "if ((INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
-      || (INTVAL (operands[3]) % INTVAL (operands[2]) != 0))
-        FAIL;
- ")
-
-(define_insn "*extv_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,c")
-        (sign_extract:QI (match_operand:QI 1 "src_operand" "g,g")
-                         (match_operand:QI 2 "const_int_operand" "n,n")
-                         (match_operand:QI 3 "const_int_operand" "n,n")))
-   (clobber (reg:CC 21))]
-  "! TARGET_C3X
-   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
-  "*
-   if (INTVAL (operands[2]) == 8)
-     {
-       operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
-       return \"lb%3\\t%1,%0\";
-     }
-   operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
-   return \"lh%3\\t%1,%0\";
-  "
-  [(set_attr "type" "binarycc,binary")
-   (set_attr "data" "int16,int16")])
-
-(define_insn "*extv_clobber_test"
-  [(set (reg:CC 21)
-        (compare:CC (sign_extract:QI (match_operand:QI 1 "src_operand" "g")
-                                     (match_operand:QI 2 "const_int_operand" "n")
-                                     (match_operand:QI 3 "const_int_operand" "n"))
-   		    (const_int 0)))
-   (clobber (match_scratch:QI 0 "=d"))]
-  "! TARGET_C3X
-   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
-  "*
-   if (INTVAL (operands[2]) == 8)
-     {
-       operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
-       return \"lb%3\\t%1,%0\";
-     }
-   operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
-   return \"lh%3\\t%1,%0\";
-  "
-  [(set_attr "type" "binarycc")
-   (set_attr "data" "int16")])
-
-(define_insn "*extv_clobber_set"
-  [(set (reg:CC 21)
-        (compare:CC (sign_extract:QI (match_operand:QI 1 "src_operand" "g")
-                                     (match_operand:QI 2 "const_int_operand" "n")
-                                     (match_operand:QI 3 "const_int_operand" "n"))
-   		    (const_int 0)))
-   (set (match_operand:QI 0 "reg_operand" "=d")
-        (sign_extract:QI (match_dup 1)
-                         (match_dup 2)
-                         (match_dup 3)))]
-  "! TARGET_C3X
-   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
-  "*
-   if (INTVAL (operands[2]) == 8)
-     {
-       operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
-       return \"lb%3\\t%1,%0\";
-     }
-   operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
-   return \"lh%3\\t%1,%0\";
-  "
-  [(set_attr "type" "binarycc")
-   (set_attr "data" "int16")])
-
-;
-; LBUx/LHUw (C4x only)
-;
-(define_expand "extzv"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (zero_extract:QI (match_operand:QI 1 "src_operand" "")
-                                    (match_operand:QI 2 "const_int_operand" "")
-                                    (match_operand:QI 3 "const_int_operand" "")))
-              (clobber (reg:CC 21))])]
- "! TARGET_C3X"
- "if ((INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
-      || (INTVAL (operands[3]) % INTVAL (operands[2]) != 0))
-        FAIL;
- ")
-
-(define_insn "*extzv_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,c")
-        (zero_extract:QI (match_operand:QI 1 "src_operand" "g,g")
-                         (match_operand:QI 2 "const_int_operand" "n,n")
-                         (match_operand:QI 3 "const_int_operand" "n,n")))
-   (clobber (reg:CC 21))]
-  "! TARGET_C3X
-   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
-  "*
-   if (INTVAL (operands[2]) == 8)
-     {
-       operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
-       return \"lbu%3\\t%1,%0\";
-     }
-   operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
-   return \"lhu%3\\t%1,%0\";
-  "
-  [(set_attr "type" "binarycc,binary")
-   (set_attr "data" "uint16,uint16")])
-
-(define_insn "*extzv_test"
-  [(set (reg:CC 21)
-        (compare:CC (zero_extract:QI (match_operand:QI 1 "src_operand" "g")
-                                     (match_operand:QI 2 "const_int_operand" "n")
-                                     (match_operand:QI 3 "const_int_operand" "n"))
-   		    (const_int 0)))
-   (clobber (match_scratch:QI 0 "=d"))]
-  "! TARGET_C3X
-   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
-  "*
-   if (INTVAL (operands[2]) == 8)
-     {
-       operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
-       return \"lbu%3\\t%1,%0\";
-     }
-   operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
-   return \"lhu%3\\t%1,%0\";
-  "
-  [(set_attr "type" "binarycc")
-   (set_attr "data" "uint16")])
-
-(define_insn "*extzv_set"
-  [(set (reg:CC 21)
-        (compare:CC (zero_extract:QI (match_operand:QI 1 "src_operand" "g")
-                                     (match_operand:QI 2 "const_int_operand" "n")
-                                     (match_operand:QI 3 "const_int_operand" "n"))
-   		    (const_int 0)))
-   (set (match_operand:QI 0 "reg_operand" "=d")
-        (zero_extract:QI (match_dup 1)
-                         (match_dup 2)
-                         (match_dup 3)))]
-  "! TARGET_C3X
-   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
-  "*
-   if (INTVAL (operands[2]) == 8)
-     {
-       operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
-       return \"lbu%3\\t%1,%0\";
-     }
-   operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
-   return \"lhu%3\\t%1,%0\";
-  "
-  [(set_attr "type" "binarycc")
-   (set_attr "data" "uint16")])
-
-;
-; MBx/MHw (C4x only)
-;
-(define_expand "insv"
-  [(parallel [(set (zero_extract:QI (match_operand:QI 0 "reg_operand" "")
-                                    (match_operand:QI 1 "const_int_operand" "")
-                                    (match_operand:QI 2 "const_int_operand" ""))
-                   (match_operand:QI 3 "src_operand" ""))
-              (clobber (reg:CC 21))])]
- "! TARGET_C3X"
- "if (! (((INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
-         && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0))
-        || (INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)))
-    FAIL;
- ")
-
-(define_insn "*insv_clobber"
-  [(set (zero_extract:QI (match_operand:QI 0 "reg_operand" "=d,c")
-                         (match_operand:QI 1 "const_int_operand" "n,n")
-                         (match_operand:QI 2 "const_int_operand" "n,n"))
-        (match_operand:QI 3 "src_operand" "g,g"))
-   (clobber (reg:CC 21))]
-  "! TARGET_C3X
-   && (((INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
-        && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0))
-       || (INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8))"
-  "*
-   if (INTVAL (operands[1]) == 8)
-     {
-       operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
-       return \"mb%2\\t%3,%0\";
-     }
-   else if (INTVAL (operands[1]) == 16)
-     {
-       operands[2] = GEN_INT (INTVAL (operands[2]) / 16);
-       return \"mh%2\\t%3,%0\";
-     }
-   return \"lwl1\\t%3,%0\";
-  "
-  [(set_attr "type" "binarycc,binary")
-   (set_attr "data" "uint16,uint16")])
-
-(define_peephole
-  [(parallel [(set (zero_extract:QI (match_operand:QI 0 "reg_operand" "=d")
-                                    (match_operand:QI 1 "const_int_operand" "n")
-                                    (match_operand:QI 2 "const_int_operand" "n"))
-                   (match_operand:QI 3 "src_operand" "g"))
-	      (clobber (reg:CC 21))])
-   (set (reg:CC 21)
-        (compare:CC (match_dup 0) (const_int 0)))]
-  "! TARGET_C3X
-   && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
-   && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0)"
-  "*
-   if (INTVAL (operands[1]) == 8)
-     {
-       operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
-       return \"mb%2\\t%3,%0\";
-     }
-   operands[2] = GEN_INT (INTVAL (operands[2]) / 16);
-   return \"mh%2\\t%3,%0\";
-  "
-  [(set_attr "type" "binarycc")
-   (set_attr "data" "uint16")])
-
-;
-; TWO OPERAND FLOAT INSTRUCTIONS
-;
-
-;
-; LDF/STF
-;
-;  If one of the operands is not a register, then we should
-;  emit two insns, using a scratch register.  This will produce
-;  better code in loops if the source operand is invariant, since
-;  the source reload can be optimised out.  During reload we cannot
-;  use change_address or force_reg.
-(define_expand "movqf"
-  [(set (match_operand:QF 0 "src_operand" "")
-        (match_operand:QF 1 "src_operand" ""))]
- ""
- "
-  if (CONSTANT_P (operands[1]) && ! const_operand (operands[1], QFmode))
-    {
-      operands[1] = force_const_mem (QFmode, operands[1]);
-      if (! memory_address_p (QFmode, XEXP (operands[1], 0))
-          && ! reload_in_progress)
-        operands[1] = change_address (operands[1], QFmode,
-                                      XEXP (operands[1], 0));
-    }
-
-  if (! reload_in_progress
-      && ! reg_operand (operands[0], QFmode)
-      && ! reg_operand (operands[1], QFmode))
-    operands[1] = force_reg (QFmode, operands[1]);
- ")
-
-; We must provide an alternative to store to memory in case we have to
-; spill a register.
-(define_insn "*movqf_noclobber"
- [(set (match_operand:QF 0 "src_operand" "=f,m")
-       (match_operand:QF 1 "src_operand" "fmH,f"))]
- "reg_operand (operands[0], QFmode)
-  || reg_operand (operands[1], QFmode)"
- "@
-  ldfu\\t%1,%0
-  stf\\t%1,%0"
-  [(set_attr "type" "unary,store")])
-
-;(define_insn "*movqf_clobber"
-;  [(set (match_operand:QF 0 "reg_operand" "=f")
-;        (match_operand:QF 1 "src_operand" "fmH"))
-;   (clobber (reg:CC 21))]
-; "0"
-; "ldf\\t%1,%0"
-;  [(set_attr "type" "unarycc")])
-
-(define_insn "*movqf_test"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:QF 1 "src_operand" "fmH")
-                    (const_int 0)))
-   (clobber (match_scratch:QF 0 "=f"))]
- ""
- "ldf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*movqf_set"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:QF 1 "src_operand" "fmH")
-                    (match_operand:QF 2 "fp_zero_operand" "G")))
-    (set (match_operand:QF 0 "reg_operand" "=f")
-         (match_dup 1))]
- ""
- "ldf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*movqf_update"
-  [(set (match_operand:QF 0 "reg_operand" "=r") 
-        (mem:QF (plus:QI (match_operand:QI 1 "addr_reg_operand" "a")
-                         (match_operand:QI 2 "index_reg_operand" "x"))))
-   (set (match_dup 1)
-        (plus:QI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldfu\\t*%1++(%2),%0"
-  [(set_attr "type" "unary")])
-
-(define_insn "*movqf_parallel"
- [(set (match_operand:QF 0 "parallel_operand" "=q,S<>,q,S<>")
-       (match_operand:QF 1 "parallel_operand" "S<>,q,S<>,q"))
-  (set (match_operand:QF 2 "parallel_operand" "=q,S<>,S<>,q")
-       (match_operand:QF 3 "parallel_operand" "S<>,q,q,S<>"))]
- "valid_parallel_load_store (operands, QFmode)"
- "@
-  ldf1\\t%1,%0\\n||\\tldf2\\t%3,%2
-  stf1\\t%1,%0\\n||\\tstf2\\t%3,%2
-  ldf\\t%1,%0\\n||\\tstf\\t%3,%2
-  ldf\\t%3,%2\\n||\\tstf\\t%1,%0"
-  [(set_attr "type" "load_load,store_store,load_store,store_load")])
-
-
-;
-; PUSH/POP
-;
-(define_insn "*pushqf"
-  [(set (mem:QF (pre_inc:QI (reg:QI 20)))
-        (match_operand:QF 0 "reg_operand" "f"))]
- ""
- "pushf\\t%0"
- [(set_attr "type" "push")])
-
-(define_insn "*popqf"
-  [(set (match_operand:QF 0 "reg_operand" "=f")
-        (mem:QF (post_dec:QI (reg:QI 20))))
-   (clobber (reg:CC 21))]
- ""
- "popf\\t%0"
- [(set_attr "type" "pop")])
-
-
-;
-; ABSF
-;
-(define_expand "absqf2"
-  [(parallel [(set (match_operand:QF 0 "reg_operand" "")
-                   (abs:QF (match_operand:QF 1 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-""
-"")
-
-(define_insn "*absqf2_clobber"
-  [(set (match_operand:QF 0 "reg_operand" "=f")
-        (abs:QF (match_operand:QF 1 "src_operand" "fmH")))
-   (clobber (reg:CC_NOOV 21))]
-  ""
-  "absf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*absqf2_test"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (abs:QF (match_operand:QF 1 "src_operand" "fmH"))
-                         (match_operand:QF 2 "fp_zero_operand" "G")))
-   (clobber (match_scratch:QF 0 "=f"))]
-  ""
-  "absf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*absqf2_set"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (abs:QF (match_operand:QF 1 "src_operand" "fmH"))
-                         (match_operand:QF 2 "fp_zero_operand" "G")))
-   (set (match_operand:QF 0 "reg_operand" "=f")
-        (abs:QF (match_dup 1)))]
-
-  ""
-  "absf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-;
-; NEGF
-;
-(define_expand "negqf2"
-  [(parallel [(set (match_operand:QF 0 "reg_operand" "")
-                   (neg:QF (match_operand:QF 1 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-""
-"")
-
-(define_insn "*negqf2_clobber"
-  [(set (match_operand:QF 0 "reg_operand" "=f")
-        (neg:QF (match_operand:QF 1 "src_operand" "fmH")))
-   (clobber (reg:CC_NOOV 21))]
-  ""
-  "negf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*negqf2_test"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (neg:QF (match_operand:QF 1 "src_operand" "fmH"))
-                         (match_operand:QF 2 "fp_zero_operand" "G")))
-   (clobber (match_scratch:QF 0 "=f"))]
-  ""
-  "negf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*negqf2_set"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (neg:QF (match_operand:QF 1 "src_operand" "fmH"))
-                         (match_operand:QF 2 "fp_zero_operand" "G")))
-   (set (match_operand:QF 0 "reg_operand" "=f")
-        (neg:QF (match_dup 1)))]
-  ""
-  "negf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-;
-; FLOAT
-;
-(define_insn "floatqiqf2"
-  [(set (match_operand:QF 0 "reg_operand" "=f")
-        (float:QF (match_operand:QI 1 "src_operand" "g")))
-   (clobber (reg:CC 21))]
- ""
- "float\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*floatqiqf2_set"
-  [(set (reg:CC 21)
-        (compare:CC (float:QF (match_operand:QI 1 "src_operand" "g"))
-                    (match_operand:QF 2 "fp_zero_operand" "G")))
-   (set (match_operand:QF 0 "reg_operand" "=f")
-        (float:QF (match_dup 1)))]
-
- ""
- "float\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-; Unsigned conversions are a little tricky because we need to
-; add the value for the high bit if necessary.
-;
-(define_expand "floatunsqiqf2"
- [(set (match_dup 2) (match_dup 3))
-  (parallel [(set (reg:CC 21)
-                  (compare:CC (float:QF (match_operand:QI 1 "src_operand" ""))
-                              (match_dup 3)))
-             (set (match_dup 4)
-                  (float:QF (match_dup 1)))])
-  (set (match_dup 2)
-       (if_then_else:QF (lt (reg:CC 21) (const_int 0))
-                        (mem:QF (symbol_ref:QF "*___unsfltconst"))
-                        (match_dup 2)))
-  (parallel [(set (match_operand:QF 0 "reg_operand" "")
-                  (plus:QF (match_dup 2) (match_dup 4)))
-             (clobber (reg:CC_NOOV 21))])]
- ""
- "operands[2] = gen_reg_rtx (QFmode);
-  operands[3] = CONST0_RTX (QFmode); 
-  operands[4] = gen_reg_rtx (QFmode);
- ")
-
-(define_insn "floatqihf2"
-  [(set (match_operand:HF 0 "reg_operand" "=h")
-        (float:HF (match_operand:QI 1 "src_operand" "g")))
-   (clobber (reg:CC 21))]
- ""
- "float\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-;
-; FIX
-;
-(define_insn "fixqfqi_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=d,c")
-        (fix:QI (match_operand:QF 1 "src_operand" "fmH,fmH")))
-   (clobber (reg:CC 21))]
- ""
- "fix\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*fixqfqi_set"
-  [(set (reg:CC 21)
-        (compare:CC (fix:QI (match_operand:QF 1 "src_operand" "fmH"))
-                    (const_int 0)))
-   (set (match_operand:QI 0 "reg_operand" "=d")
-        (fix:QI (match_dup 1)))]
- ""
- "fix\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-;
-; The C[34]x fix instruction implements a floor, not a straight trunc,
-; so we have to invert the number, fix it, and reinvert it if negative
-;
-(define_expand "fix_truncqfqi2"
-  [(parallel [(set (match_dup 2)
-                   (fix:QI (match_operand:QF 1 "src_operand" "")))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_dup 3) (neg:QF (match_dup 1)))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (fix:QI (match_dup 3)))
-              (clobber (reg:CC 21))])
-   (parallel [(set (reg:CC_NOOV 21)
-                   (compare:CC_NOOV (neg:QI (match_dup 4)) (const_int 0)))
-              (set (match_dup 5) (neg:QI (match_dup 4)))])
-   (set (match_dup 2)
-        (if_then_else:QI (le (reg:CC 21) (const_int 0))
-                         (match_dup 5)
-                         (match_dup 2)))
-   (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 2))]
- ""
- "if (TARGET_FAST_FIX)
-    {
-       emit_insn (gen_fixqfqi_clobber (operands[0], operands[1]));
-       DONE;
-    }
-  operands[2] = gen_reg_rtx (QImode);
-  operands[3] = gen_reg_rtx (QFmode);
-  operands[4] = gen_reg_rtx (QImode);
-  operands[5] = gen_reg_rtx (QImode);
- ")
-
-(define_expand "fix_truncqfhi2"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-                   (fix:HI (match_operand:QF 1 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall (FIX_TRUNCQFHI2_LIBCALL, FIX, HImode, QFmode, 2, operands);
-   DONE;")
-
-(define_expand "fixuns_truncqfqi2"
- [(set (match_dup 2) (match_dup 4))
-  (set (reg:CC 21)
-       (compare:CC (match_operand:QF 1 "reg_operand" "")
-                   (mem:QF (symbol_ref "*___unsfltcompare"))))
-  (set (match_dup 2)
-       (if_then_else:QF (ge (reg:CC 21) (const_int 0))
-                        (mem:QF (symbol_ref "*___unsfltconst"))
-                        (match_dup 2)))
-  (parallel [(set (match_dup 3)
-                  (minus:QF (match_dup 1) (match_dup 2)))
-             (clobber (reg:CC_NOOV 21))])
-  (parallel [(set (match_operand:QI 0 "reg_operand" "")
-                  (fix:QI (match_dup 3)))
-             (clobber (reg:CC 21))])]
- ""
- "operands[2] = gen_reg_rtx (QFmode);
-  operands[3] = gen_reg_rtx (QFmode);
-  operands[4] = CONST0_RTX (QFmode);
- ")
-
-(define_expand "fixuns_truncqfhi2"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-                   (unsigned_fix:HI (match_operand:QF 1 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall (FIXUNS_TRUNCQFHI2_LIBCALL, UNSIGNED_FIX, 
-                     HImode, QFmode, 2, operands);
-   DONE;")
-
-;
-; RCPF
-;
-(define_insn "*rcpfqf_clobber"
-  [(set (match_operand:QF 0 "reg_operand" "=f")
-        (unspec [(match_operand:QF 1 "src_operand" "fmH")] 5))
-   (clobber (reg:CC_NOOV 21))]
-  "! TARGET_C3X"
-  "rcpf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-;
-; RSQRF
-;
-(define_insn "*rsqrfqf_clobber"
-  [(set (match_operand:QF 0 "reg_operand" "=f")
-        (unspec [(match_operand:QF 1 "src_operand" "fmH")] 10))
-   (clobber (reg:CC_NOOV 21))]
-  "! TARGET_C3X"
-  "rsqrf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-;
-; RNDF
-;
-(define_insn "*rndqf_clobber"
-  [(set (match_operand:QF 0 "reg_operand" "=f")
-        (unspec [(match_operand:QF 1 "src_operand" "fmH")] 6))
-   (clobber (reg:CC_NOOV 21))]
-  "! TARGET_C3X"
-  "rnd\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-
-; Inlined float square root for C4x
-(define_expand "sqrtqf2_inline"
-  [(parallel [(set (match_dup 2)
-	           (unspec [(match_operand:QF 1 "src_operand" "")] 10))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 3) (mult:QF (match_dup 5) (match_dup 1)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 4)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (minus:QF (match_dup 6) (match_dup 4)))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 2) (mult:QF (match_dup 2) (match_dup 4)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 4)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (minus:QF (match_dup 6) (match_dup 4)))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 2) (mult:QF (match_dup 2) (match_dup 4)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 1)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_operand:QF 0 "reg_operand" "")
-	           (unspec [(match_dup 4)] 6))
-	      (clobber (reg:CC_NOOV 21))])]
-  "! TARGET_C3X"
-  "if (! reload_in_progress
-       && ! reg_operand (operands[1], QFmode))
-     operands[1] = force_reg (QFmode, operands[1]);
-   operands[2] = gen_reg_rtx (QFmode);
-   operands[3] = gen_reg_rtx (QFmode);
-   operands[4] = gen_reg_rtx (QFmode);
-   operands[5] = immed_real_const_1 (REAL_VALUE_ATOF (\"0.5\", QFmode),
-                                     QFmode);
-   operands[6] = immed_real_const_1 (REAL_VALUE_ATOF (\"1.5\", QFmode),
-                                     QFmode);")
-
-(define_expand "sqrtqf2"
-  [(parallel [(set (match_operand:QF 0 "reg_operand" "")
-                   (sqrt:QF (match_operand:QF 1 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "if (TARGET_C3X || ! TARGET_INLINE)
-     FAIL;
-   else
-     {
-       emit_insn (gen_sqrtqf2_inline (operands[0], operands[1]));
-       DONE;
-     }
-  ")
-
-;
-; THREE OPERAND FLOAT INSTRUCTIONS
-;
-
-;
-; ADDF
-;
-(define_expand "addqf3"
-  [(parallel [(set (match_operand:QF 0 "reg_operand" "")
-                   (plus:QF (match_operand:QF 1 "src_operand" "")
-                            (match_operand:QF 2 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-  ""
-  "legitimize_operands (PLUS, operands, QFmode);")
-
-(define_insn "*addqf3_clobber"
-  [(set (match_operand:QF 0 "reg_operand" "=f,?f,f")
-        (plus:QF (match_operand:QF 1 "src_operand" "%fR,fS<>,0")
-                 (match_operand:QF 2 "src_operand" "R,fS<>,fmH")))
-   (clobber (reg:CC_NOOV 21))]
-  "valid_operands (PLUS, operands, QFmode)"
-  "@
-   addf3\\t%2,%1,%0
-   addf3\\t%2,%1,%0
-   addf\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-
-(define_insn "*addqf3_test"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (plus:QF (match_operand:QF 1 "src_operand" "%fR,fS<>,0")
-                                  (match_operand:QF 2 "src_operand" "R,fS<>,fmH"))
-                         (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
-   (clobber (match_scratch:QF 0 "=f,?f,f"))]
-  "valid_operands (PLUS, operands, QFmode)"
-  "@
-   addf3\\t%2,%1,%0
-   addf3\\t%2,%1,%0
-   addf\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-
-(define_insn "*addqf3_set"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (plus:QF (match_operand:QF 1 "src_operand" "%fR,fS<>,0")
-                                  (match_operand:QF 2 "src_operand" "R,fS<>,fmH"))
-                         (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
-   (set (match_operand:QF 0 "reg_operand" "=f,?f,f")
-        (plus:QF (match_dup 1)
-                 (match_dup 2)))]
-  "valid_operands (PLUS, operands, QFmode)"
-  "@
-   addf3\\t%2,%1,%0
-   addf3\\t%2,%1,%0
-   addf\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-
-;
-; SUBF/SUBRF
-;
-(define_expand "subqf3"
-  [(parallel [(set (match_operand:QF 0 "reg_operand" "")
-                   (minus:QF (match_operand:QF 1 "src_operand" "")
-                             (match_operand:QF 2 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-  ""
-  "legitimize_operands (MINUS, operands, QFmode);")
-
-(define_insn "*subqf3_clobber"
-   [(set (match_operand:QF 0 "reg_operand" "=f,?f,f,f")
-         (minus:QF (match_operand:QF 1 "src_operand" "fR,fS<>,0,fmH")
-                   (match_operand:QF 2 "src_operand" "R,fS<>,fmH,0")))
-   (clobber (reg:CC_NOOV 21))]
-  "valid_operands (MINUS, operands, QFmode)"
-  "@
-   subf3\\t%2,%1,%0
-   subf3\\t%2,%1,%0
-   subf\\t%2,%0
-   subrf\\t%1,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
-
-(define_insn "*subqf3_test"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (minus:QF (match_operand:QF 1 "src_operand" "fR,fS<>,0,fmH")
-                                   (match_operand:QF 2 "src_operand" "R,fS<>,fmH,0"))
-                         (match_operand:QF 3 "fp_zero_operand" "G,G,G,G")))
-   (clobber (match_scratch:QF 0 "=f,?f,f,f"))]
-  "valid_operands (MINUS, operands, QFmode)"
-  "@
-   subf3\\t%2,%1,%0
-   subf3\\t%2,%1,%0
-   subf\\t%2,%0
-   subrf\\t%1,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
-
-(define_insn "*subqf3_set"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (minus:QF (match_operand:QF 1 "src_operand" "fR,fS<>,0,fmH")
-                                   (match_operand:QF 2 "src_operand" "R,fS<>,fmH,0"))
-                         (match_operand:QF 3 "fp_zero_operand" "G,G,G,G")))
-   (set (match_operand:QF 0 "reg_operand" "=f,?f,f,f")
-        (minus:QF (match_dup 1)
-                 (match_dup 2)))]
-  "valid_operands (MINUS, operands, QFmode)"
-  "@
-   subf3\\t%2,%1,%0
-   subf3\\t%2,%1,%0
-   subf\\t%2,%0
-   subrf\\t%1,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
-
-;
-; MPYF
-;
-(define_expand "mulqf3"
-  [(parallel [(set (match_operand:QF 0 "reg_operand" "")
-                   (mult:QF (match_operand:QF 1 "src_operand" "")
-                            (match_operand:QF 2 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-  ""
-  "legitimize_operands (MULT, operands, QFmode);")
-
-(define_insn "*mulqf3_clobber"
-  [(set (match_operand:QF 0 "reg_operand" "=f,?f,f")
-        (mult:QF (match_operand:QF 1 "src_operand" "%fR,fS<>,0")
-                 (match_operand:QF 2 "src_operand" "R,fS<>,fmH")))
-   (clobber (reg:CC_NOOV 21))]
-  "valid_operands (MULT, operands, QFmode)"
-  "@
-   mpyf3\\t%2,%1,%0
-   mpyf3\\t%2,%1,%0
-   mpyf\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-
-(define_insn "*mulqf3_test"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (mult:QF (match_operand:QF 1 "src_operand" "%fR,fS<>,0")
-                                  (match_operand:QF 2 "src_operand" "R,fS<>,fmH"))
-                         (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
-   (clobber (match_scratch:QF 0 "=f,?f,f"))]
-  "valid_operands (MULT, operands, QFmode)"
-  "@
-   mpyf3\\t%2,%1,%0
-   mpyf3\\t%2,%1,%0
-   mpyf\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-
-(define_insn "*mulqf3_set"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (mult:QF (match_operand:QF 1 "src_operand" "%fR,fS<>,0")
-                                  (match_operand:QF 2 "src_operand" "R,fS<>,fmH"))
-                         (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
-   (set (match_operand:QF 0 "reg_operand" "=f,?f,f")
-        (mult:QF (match_dup 1)
-                 (match_dup 2)))]
-  "valid_operands (MULT, operands, QFmode)"
-  "@
-   mpyf3\\t%2,%1,%0
-   mpyf3\\t%2,%1,%0
-   mpyf\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-
-;
-; CMPF
-;
-(define_expand "cmpqf"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:QF 0 "src_operand" "")
-                    (match_operand:QF 1 "src_operand" "")))]
-  ""
-  "legitimize_operands (COMPARE, operands, QFmode);
-   c4x_compare_op0 = operands[0];
-   c4x_compare_op1 = operands[1];
-   DONE;")
-
-(define_insn "*cmpqf"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:QF 0 "src_operand" "fR,?fS<>,f")
-                    (match_operand:QF 1 "src_operand" "R,fS<>,fmH")))]
-  "valid_operands (COMPARE, operands, QFmode)"
-  "@
-   cmpf3\\t%1,%0
-   cmpf3\\t%1,%0
-   cmpf\\t%1,%0"
-  [(set_attr "type" "compare,compare,compare")])
-
-(define_insn "*cmpqf_noov"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (match_operand:QF 0 "src_operand" "fR,?fS<>,f")
-                         (match_operand:QF 1 "src_operand" "R,fS<>,fmH")))]
-  "valid_operands (COMPARE, operands, QFmode)"
-  "@
-   cmpf3\\t%1,%0
-   cmpf3\\t%1,%0
-   cmpf\\t%1,%0"
-  [(set_attr "type" "compare,compare,compare")])
-
-; Inlined float divide for C4x
-(define_expand "divqf3_inline"
-  [(parallel [(set (match_dup 3)
-	           (unspec [(match_operand:QF 2 "src_operand" "")] 5))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (minus:QF (match_dup 5) (match_dup 4)))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 3) (mult:QF (match_dup 3) (match_dup 4)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (minus:QF (match_dup 5) (match_dup 4)))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 3) (mult:QF (match_dup 3) (match_dup 4)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 3)
-		   (mult:QF (match_operand:QF 1 "src_operand" "")
-	         	    (match_dup 3)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_operand:QF 0 "reg_operand" "")
-	           (unspec [(match_dup 3)] 6))
-	      (clobber (reg:CC_NOOV 21))])]
-  "! TARGET_C3X"
-  "if (! reload_in_progress
-      && ! reg_operand (operands[2], QFmode))
-     operands[2] = force_reg (QFmode, operands[2]);
-   operands[3] = gen_reg_rtx (QFmode);
-   operands[4] = gen_reg_rtx (QFmode);
-   operands[5] = CONST2_RTX (QFmode);")
-
-(define_expand "divqf3"
-  [(parallel [(set (match_operand:QF 0 "reg_operand" "")
-                   (div:QF (match_operand:QF 1 "src_operand" "")
-                            (match_operand:QF 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "if (TARGET_C3X || ! TARGET_INLINE)
-     {
-       c4x_emit_libcall3 (DIVQF3_LIBCALL, DIV, QFmode, operands);
-       DONE;
-     }
-   else
-     {
-       emit_insn (gen_divqf3_inline (operands[0], operands[1], operands[2]));
-       DONE;
-     }
-  ")
-
-;
-; CONDITIONAL MOVES
-;
-
-(define_insn "*ldi_conditional"
-  [(set (match_operand:QI 0 "reg_operand" "=r,r")
-        (if_then_else:QI (match_operator 1 "comparison_operator"
-                          [(reg:CC 21) (const_int 0)])
-                         (match_operand:QI 2 "src_operand" "g,0")
-                         (match_operand:QI 3 "src_operand" "0,g")))]
- ""
- "@
-  ldi%1\\t%2,%0
-  ldi%I1\\t%3,%0"
- [(set_attr "type" "binary")])
-
-(define_insn "*ldi_conditional_noov"
-  [(set (match_operand:QI 0 "reg_operand" "=r,r")
-        (if_then_else:QI (match_operator 1 "comparison_operator"
-                          [(reg:CC_NOOV 21) (const_int 0)])
-                         (match_operand:QI 2 "src_operand" "g,0")
-                         (match_operand:QI 3 "src_operand" "0,g")))]
- "GET_CODE (operands[1]) != LE
-  && GET_CODE (operands[1]) != GE
-  && GET_CODE (operands[1]) != LT
-  && GET_CODE (operands[1]) != GT"
- "@
-  ldi%1\\t%2,%0
-  ldi%I1\\t%3,%0"
- [(set_attr "type" "binary")])
-
-; Move operand 2 to operand 0 if condition (operand 1) is true
-; else move operand 3 to operand 0.
-; The temporary register is required below because some of the operands
-; might be identical (namely 0 and 2). 
-;
-(define_expand "movqicc"
-  [(set (match_operand:QI 0 "reg_operand" "")
-        (if_then_else:QI (match_operand 1 "comparison_operator" "")
-                         (match_operand:QI 2 "src_operand" "")
-                         (match_operand:QI 3 "src_operand" "")))]
- ""
- "{ 
-    enum rtx_code code = GET_CODE (operands[1]);
-    rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
-    if (ccreg == NULL_RTX) FAIL;
-    emit_insn (gen_rtx_SET (QImode, operands[0],
-                            gen_rtx_IF_THEN_ELSE (QImode,
-                                 gen_rtx (code, VOIDmode, ccreg, const0_rtx),
-                                          operands[2], operands[3])));
-    DONE;}")
-                      
-(define_insn "*ldf_conditional"
-  [(set (match_operand:QF 0 "reg_operand" "=f,f")
-        (if_then_else:QF (match_operator 1 "comparison_operator"
-                          [(reg:CC 21) (const_int 0)])
-                         (match_operand:QF 2 "src_operand" "fmH,0")
-                         (match_operand:QF 3 "src_operand" "0,fmH")))]
- ""
- "@
-  ldf%1\\t%2,%0
-  ldf%I1\\t%3,%0"
- [(set_attr "type" "binary")])
-
-(define_insn "*ldf_conditional_noov"
-  [(set (match_operand:QF 0 "reg_operand" "=f,f")
-        (if_then_else:QF (match_operator 1 "comparison_operator"
-                          [(reg:CC_NOOV 21) (const_int 0)])
-                         (match_operand:QF 2 "src_operand" "fmH,0")
-                         (match_operand:QF 3 "src_operand" "0,fmH")))]
- "GET_CODE (operands[1]) != LE
-  && GET_CODE (operands[1]) != GE
-  && GET_CODE (operands[1]) != LT
-  && GET_CODE (operands[1]) != GT"
- "@
-  ldf%1\\t%2,%0
-  ldf%I1\\t%3,%0"
- [(set_attr "type" "binary")])
-
-(define_expand "movqfcc"
-  [(set (match_operand:QF 0 "reg_operand" "")
-        (if_then_else:QF (match_operand 1 "comparison_operator" "")
-                         (match_operand:QF 2 "src_operand" "")
-                         (match_operand:QF 3 "src_operand" "")))]
- ""
- "{ 
-    enum rtx_code code = GET_CODE (operands[1]);
-    rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
-    if (ccreg == NULL_RTX) FAIL;
-    emit_insn (gen_rtx_SET (QFmode, operands[0],
-                            gen_rtx_IF_THEN_ELSE (QFmode,
-                                 gen_rtx (code, VOIDmode, ccreg, const0_rtx),
-                                          operands[2], operands[3])));
-    DONE;}")
-
-(define_expand "seq"
- [(set (match_operand:QI 0 "reg_operand" "")
-       (const_int 0))
-  (set (match_dup 0)
-       (if_then_else:QI (eq (match_dup 1) (const_int 0))
-		        (const_int 1)
-		        (match_dup 0)))]
- ""
- "operands[1] = c4x_gen_compare_reg (EQ, c4x_compare_op0, c4x_compare_op1);")
-
-(define_expand "sne"
- [(set (match_operand:QI 0 "reg_operand" "")
-       (const_int 0))
-  (set (match_dup 0)
-       (if_then_else:QI (ne (match_dup 1) (const_int 0))
-		        (const_int 1)
-		        (match_dup 0)))]
- ""
- "operands[1] = c4x_gen_compare_reg (NE, c4x_compare_op0, c4x_compare_op1);")
-
-(define_expand "slt"
-  [(set (match_operand:QI 0 "reg_operand" "")
-        (const_int 0))
-   (set (match_dup 0)
-        (if_then_else:QI (lt (match_dup 1) (const_int 0))
-	 	        (const_int 1)
-		         (match_dup 0)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (LT, c4x_compare_op0, c4x_compare_op1);
-   if (operands[1] == NULL_RTX) FAIL;")
-
-(define_expand "sltu"
-  [(set (match_operand:QI 0 "reg_operand" "")
-        (const_int 0))
-   (set (match_dup 0)
-        (if_then_else:QI (ltu (match_dup 1) (const_int 0))
-	 	        (const_int 1)
-		         (match_dup 0)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (LTU, c4x_compare_op0, c4x_compare_op1);")
-
-(define_expand "sgt"
-  [(set (match_operand:QI 0 "reg_operand" "")
-        (const_int 0))
-   (set (match_dup 0)
-        (if_then_else:QI (gt (match_dup 1) (const_int 0))
-	 	        (const_int 1)
-		         (match_dup 0)))]
-  "" 
-  "operands[1] = c4x_gen_compare_reg (GT, c4x_compare_op0, c4x_compare_op1);
-   if (operands[1] == NULL_RTX) FAIL;")
-
-(define_expand "sgtu"
-  [(set (match_operand:QI 0 "reg_operand" "")
-        (const_int 0))
-   (set (match_dup 0)
-        (if_then_else:QI (gtu (match_dup 1) (const_int 0))
-	 	        (const_int 1)
-		         (match_dup 0)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (GTU, c4x_compare_op0, c4x_compare_op1);")
-
-(define_expand "sle"
-  [(set (match_operand:QI 0 "reg_operand" "")
-        (const_int 0))
-   (set (match_dup 0)
-        (if_then_else:QI (le (match_dup 1) (const_int 0))
-	 	         (const_int 1)
-		         (match_dup 0)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (LE, c4x_compare_op0, c4x_compare_op1);
-   if (operands[1] == NULL_RTX) FAIL;")
-
-(define_expand "sleu"
-  [(set (match_operand:QI 0 "reg_operand" "")
-        (const_int 0))
-   (set (match_dup 0)
-        (if_then_else:QI (leu (match_dup 1) (const_int 0))
-	 	         (const_int 1)
-		         (match_dup 0)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (LEU, c4x_compare_op0, c4x_compare_op1);")
-
-(define_expand "sge"
-  [(set (match_operand:QI 0 "reg_operand" "")
-        (const_int 0))
-   (set (match_dup 0)
-        (if_then_else:QI (ge (match_dup 1) (const_int 0))
-	 	         (const_int 1)
-		         (match_dup 0)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (GE, c4x_compare_op0, c4x_compare_op1);
-   if (operands[1] == NULL_RTX) FAIL;")
-
-(define_expand "sgeu"
-  [(set (match_operand:QI 0 "reg_operand" "")
-        (const_int 0))
-   (set (match_dup 0)
-        (if_then_else:QI (geu (match_dup 1) (const_int 0))
-	 	         (const_int 1)
-		         (match_dup 0)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (GEU, c4x_compare_op0, c4x_compare_op1);")
-
-(define_split
-  [(set (match_operand:QI 0 "reg_operand" "")
-        (match_operator 1 "comparison_operator" [(reg:CC 21) (const_int 0)]))]
-  "reload_completed"
-  [(set (match_dup 0) (const_int 0))
-   (set (match_dup 0)
-        (if_then_else:QI (match_op_dup 1 [(reg:CC 21) (const_int 0)])
-	 	        (const_int 1)
-		         (match_dup 0)))]
-  "")
-
-(define_split
-  [(set (match_operand:QI 0 "reg_operand" "")
-        (match_operator 1 "comparison_operator" [(reg:CC_NOOV 21) (const_int 0)]))]
-  "reload_completed"
-  [(set (match_dup 0) (const_int 0))
-   (set (match_dup 0)
-        (if_then_else:QI (match_op_dup 1 [(reg:CC_NOOV 21) (const_int 0)])
-	 	         (const_int 1)
-		         (match_dup 0)))]
-  "")
-
-(define_insn "*bu"
-  [(set (pc)
-        (unspec [(match_operand:QI 0 "reg_operand" "r")] 1))]
-  ""
-  "bu%#\\t%0"
-  [(set_attr "type" "jump")])
-
-(define_expand "caseqi"
-  [(parallel [(set (match_dup 5)
-                   (minus:QI (match_operand:QI 0 "reg_operand" "")
-                             (match_operand:QI 1 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])
-   (set (reg:CC 21)
-        (compare:CC (match_dup 5)
-                    (match_operand:QI 2 "src_operand" "")))
-   (set (pc)
-        (if_then_else (gtu (reg:CC 21)
-                           (const_int 0))
-                      (label_ref (match_operand 4 "" ""))
-                      (pc)))
-   (parallel [(set (match_dup 6)
-                   (plus:QI (match_dup 5)
-                            (label_ref:QI (match_operand 3 "" ""))))
-              (clobber (reg:CC_NOOV 21))])
-   (set (match_dup 7)
-        (mem:QI (match_dup 6)))
-   (set (pc) (match_dup 7))]
-  ""
-  "operands[5] = gen_reg_rtx (QImode);
-   operands[6] = gen_reg_rtx (QImode);
-   operands[7] = gen_reg_rtx (QImode);")
-                
-;
-; PARALLEL FLOAT INSTRUCTIONS
-;
-; This patterns are under development
-
-;
-; ABSF/STF
-;
-
-(define_insn "*absqf2_movqf_clobber"
-  [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
-        (abs:QF (match_operand:QF 1 "par_ind_operand" "S<>")))
-   (set (match_operand:QF 2 "par_ind_operand" "=S<>")
-        (match_operand:QF 3 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC_NOOV 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
-  "absf\\t%1,%0\\n||\\tstf\\t%3,%2"
-  [(set_attr "type" "binarycc")])
-
-;
-; ADDF/STF
-;
-
-(define_insn "*addqf3_movqf_clobber"
-  [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
-        (plus:QF (match_operand:QF 1 "parallel_operand" "%q")
-                 (match_operand:QF 2 "parallel_operand" "S<>")))
-   (set (match_operand:QF 3 "par_ind_operand" "=S<>")
-        (match_operand:QF 4 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
-  "addf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; FLOAT/STF
-;
-
-(define_insn "*floatqiqf2_movqf_clobber"
-  [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
-        (float:QF (match_operand:QI 1 "par_ind_operand" "S<>")))
-   (set (match_operand:QF 2 "par_ind_operand" "=S<>")
-        (match_operand:QF 3 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
-  "float\\t%1,%0\\n||\\tstf\\t%3,%2"
-  [(set_attr "type" "binarycc")])
-
-;
-; MPYF/ADDF
-;
-
-(define_insn "*mulqf3_addqf3_clobber"
-  [(set (match_operand:QF 0 "r0r1_reg_operand" "=t")
-        (mult:QF (match_operand:QF 1 "parallel_operand" "%S<>q")
-                 (match_operand:QF 2 "parallel_operand" "S<>q")))
-   (set (match_operand:QF 3 "r2r3_reg_operand" "=u")
-        (plus:QF (match_operand:QF 4 "parallel_operand" "%S<>q")
-                 (match_operand:QF 5 "parallel_operand" "S<>q")))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL_MPY && valid_parallel_operands_6 (operands, QFmode)"
-  "mpyf3\\t%2,%1,%0\\n||\\taddf3\\t%5,%4,%3"
-  [(set_attr "type" "binarycc")])
-
-
-;
-; MPYF/STF
-;
-
-(define_insn "*mulqf3_movqf_clobber"
-  [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
-        (mult:QF (match_operand:QF 1 "parallel_operand" "%q")
-                 (match_operand:QF 2 "parallel_operand" "S<>")))
-   (set (match_operand:QF 3 "par_ind_operand" "=S<>")
-        (match_operand:QF 4 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
-  "mpyf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; MPYF/SUBF
-;
-
-(define_insn "*mulqf3_subqf3_clobber"
-  [(set (match_operand:QF 0 "r0r1_reg_operand" "=t")
-        (mult:QF (match_operand:QF 1 "parallel_operand" "S<>q")
-                 (match_operand:QF 2 "parallel_operand" "S<>q")))
-   (set (match_operand:QF 3 "r2r3_reg_operand" "=u")
-        (minus:QF (match_operand:QF 4 "parallel_operand" "S<>q")
-                  (match_operand:QF 5 "parallel_operand" "S<>q")))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL_MPY && valid_parallel_operands_6 (operands, QFmode)"
-  "mpyf3\\t%2,%1,%0\\n||\\tsubf3\\t%5,%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; NEGF/STF
-;
-
-(define_insn "*negqf2_movqf_clobber"
-  [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
-        (neg:QF (match_operand:QF 1 "par_ind_operand" "S<>")))
-   (set (match_operand:QF 2 "par_ind_operand" "=S<>")
-        (match_operand:QF 3 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
-  "negf\\t%1,%0\\n||\\tstf\\t%3,%2"
-  [(set_attr "type" "binarycc")])
-
-;
-; SUBF/STF
-;
-
-(define_insn "*subqf3_movqf_clobber"
-  [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
-        (minus:QF (match_operand:QF 1 "ext_low_reg_operand" "q")
-                  (match_operand:QF 2 "par_ind_operand" "S<>")))
-   (set (match_operand:QF 3 "par_ind_operand" "=S<>")
-        (match_operand:QF 4 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
-  "subf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; PARALLEL INTEGER INSTRUCTIONS
-;
-; These patterns are under development
-
-;
-; ABSI/STI
-;
-
-(define_insn "*absqi2_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (abs:QI (match_operand:QI 1 "par_ind_operand" "S<>")))
-   (set (match_operand:QI 2 "par_ind_operand" "=S<>")
-        (match_operand:QI 3 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC_NOOV 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
-  "absi\\t%1,%0\\n||\\tsti\\t%3,%2"
-  [(set_attr "type" "binarycc")])
-
-;
-; ADDI/STI
-;
-
-(define_insn "*addqi3_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (plus:QI (match_operand:QI 1 "parallel_operand" "%q")
-                 (match_operand:QI 2 "parallel_operand" "S<>")))
-   (set (match_operand:QI 3 "par_ind_operand" "=S<>")
-        (match_operand:QI 4 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
-  "addi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; AND/STI
-;
-
-(define_insn "*andqi3_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (and:QI (match_operand:QI 1 "parallel_operand" "%q")
-                (match_operand:QI 2 "parallel_operand" "S<>")))
-   (set (match_operand:QI 3 "par_ind_operand" "=S<>")
-        (match_operand:QI 4 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
-  "and3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; ASH(left)/STI 
-;
-
-(define_insn "*ashlqi3_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (ashift:QI (match_operand:QI 1 "par_ind_operand" "S<>")
-                   (match_operand:QI 2 "ext_low_reg_operand" "q")))
-   (set (match_operand:QI 3 "par_ind_operand" "=S<>")
-        (match_operand:QI 4 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
-  "ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; ASH(right)/STI 
-;
-
-(define_insn "*ashrqi3_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (ashiftrt:QI (match_operand:QI 1 "par_ind_operand" "S<>")
-                     (neg:QI (match_operand:QI 2 "ext_low_reg_operand" "q"))))
-   (set (match_operand:QI 3 "par_ind_operand" "=S<>")
-        (match_operand:QI 4 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
-  "ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; FIX/STI
-;
-
-(define_insn "*fixqfqi2_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (fix:QI (match_operand:QF 1 "par_ind_operand" "S<>")))
-   (set (match_operand:QI 2 "par_ind_operand" "=S<>")
-        (match_operand:QI 3 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
-  "fix\\t%1,%0\\n||\\tsti\\t%3,%2"
-  [(set_attr "type" "binarycc")])
-
-;
-; LSH(right)/STI 
-;
-
-(define_insn "*lshrqi3_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (lshiftrt:QI (match_operand:QI 1 "par_ind_operand" "S<>")
-                     (neg:QI (match_operand:QI 2 "ext_low_reg_operand" "q"))))
-   (set (match_operand:QI 3 "par_ind_operand" "=S<>")
-        (match_operand:QI 4 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
-  "lsh3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; MPYI/ADDI
-;
-
-(define_insn "*mulqi3_addqi3_clobber"
-  [(set (match_operand:QI 0 "r0r1_reg_operand" "=t")
-        (mult:QI (match_operand:QI 1 "parallel_operand" "S<>q")
-                 (match_operand:QI 2 "parallel_operand" "S<>q")))
-   (set (match_operand:QI 3 "r2r3_reg_operand" "=u")
-        (plus:QI (match_operand:QI 4 "parallel_operand" "S<>q")
-                 (match_operand:QI 5 "parallel_operand" "S<>q")))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL_MPY && TARGET_MPYI 
-   && valid_parallel_operands_6 (operands, QImode)"
-  "mpyi3\\t%2,%1,%0\\n||\\taddi3\\t%5,%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; MPYI/STI
-;
-
-(define_insn "*mulqi3_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (mult:QI (match_operand:QI 1 "parallel_operand" "%q")
-                 (match_operand:QI 2 "parallel_operand" "S<>")))
-   (set (match_operand:QI 3 "par_ind_operand" "=S<>")
-        (match_operand:QI 4 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && TARGET_MPYI
-   && valid_parallel_operands_5 (operands, QImode)"
-  "mpyi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; MPYI/SUBI
-;
-
-(define_insn "*mulqi3_subqi3_clobber"
-  [(set (match_operand:QI 0 "r0r1_reg_operand" "=t")
-        (mult:QI (match_operand:QI 1 "parallel_operand" "S<>q")
-                 (match_operand:QI 2 "parallel_operand" "S<>q")))
-   (set (match_operand:QI 3 "r2r3_reg_operand" "=u")
-        (minus:QI (match_operand:QI 4 "parallel_operand" "S<>q")
-                  (match_operand:QI 5 "parallel_operand" "S<>q")))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL_MPY && TARGET_MPYI
-   && valid_parallel_operands_6 (operands, QImode)"
-  "mpyi3\\t%2,%1,%0\\n||\\tsubi3\\t%5,%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; NEGI/STI
-;
-
-(define_insn "*negqi2_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (neg:QI (match_operand:QI 1 "par_ind_operand" "S<>")))
-   (set (match_operand:QI 2 "par_ind_operand" "=S<>")
-        (match_operand:QI 3 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
-  "negi\\t%1,%0\\n||\\tsti\\t%3,%2"
-  [(set_attr "type" "binarycc")])
-
-;
-; NOT/STI
-;
-
-(define_insn "*notqi2_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (not:QI (match_operand:QI 1 "par_ind_operand" "S<>")))
-   (set (match_operand:QI 2 "par_ind_operand" "=S<>")
-        (match_operand:QI 3 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
-  "not\\t%1,%0\\n||\\tsti\\t%3,%2"
-  [(set_attr "type" "binarycc")])
-
-;
-; OR/STI
-;
-
-(define_insn "*iorqi3_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (ior:QI (match_operand:QI 1 "parallel_operand" "%q")
-                (match_operand:QI 2 "parallel_operand" "S<>")))
-   (set (match_operand:QI 3 "par_ind_operand" "=S<>")
-        (match_operand:QI 4 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
-  "or3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; SUBI/STI
-;
-
-(define_insn "*subqi3_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (minus:QI (match_operand:QI 1 "ext_low_reg_operand" "q")
-                  (match_operand:QI 2 "par_ind_operand" "S<>")))
-   (set (match_operand:QI 3 "par_ind_operand" "=S<>")
-        (match_operand:QI 4 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
-  "subi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; XOR/STI
-;
-
-(define_insn "*xorqi3_movqi_clobber"
-  [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
-        (xor:QI (match_operand:QI 1 "parallel_operand" "%q")
-                (match_operand:QI 2 "parallel_operand" "S<>")))
-   (set (match_operand:QI 3 "par_ind_operand" "=S<>")
-        (match_operand:QI 4 "ext_low_reg_operand" "q"))
-   (clobber (reg:CC 21))]
-  "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
-  "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
-  [(set_attr "type" "binarycc")])
-
-;
-; BRANCH/CALL INSTRUCTIONS
-;
-
-;
-; Branch instructions
-;
-(define_insn "*b"
-  [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
-			   [(reg:CC 21) (const_int 0)])
-                           (label_ref (match_operand 1 "" ""))
-                           (pc)))]
-  ""
-  "*
-   return c4x_output_cbranch (\"b%0\", insn);"
-  [(set_attr "type" "jmpc")])
-
-(define_insn "*b_rev"
-  [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
-			   [(reg:CC 21) (const_int 0)])
-                           (pc)
-                           (label_ref (match_operand 1 "" ""))))]
-  ""
-  "*
-   return c4x_output_cbranch (\"b%I0\", insn);"
-  [(set_attr "type" "jmpc")])
-
-(define_insn "*b_noov"
-  [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
-			   [(reg:CC_NOOV 21) (const_int 0)])
-                           (label_ref (match_operand 1 "" ""))
-                           (pc)))]
- "GET_CODE (operands[0]) != LE
-  && GET_CODE (operands[0]) != GE
-  && GET_CODE (operands[0]) != LT
-  && GET_CODE (operands[0]) != GT"
-  "*
-   return c4x_output_cbranch (\"b%0\", insn);"
-  [(set_attr "type" "jmpc")])
-
-(define_insn "*b_noov_rev"
-  [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
-			   [(reg:CC_NOOV 21) (const_int 0)])
-                           (pc)
-                           (label_ref (match_operand 1 "" ""))))]
- "GET_CODE (operands[0]) != LE
-  && GET_CODE (operands[0]) != GE
-  && GET_CODE (operands[0]) != LT
-  && GET_CODE (operands[0]) != GT"
-  "*
-   return c4x_output_cbranch (\"b%I0\", insn);"
-  [(set_attr "type" "jmpc")])
-
-(define_expand "beq"
-  [(set (pc) (if_then_else (eq (match_dup 1) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (EQ, c4x_compare_op0, c4x_compare_op1);")
-
-(define_expand "bne"
-  [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (NE, c4x_compare_op0, c4x_compare_op1);")
-
-(define_expand "blt"
-  [(set (pc) (if_then_else (lt (match_dup 1) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (LT, c4x_compare_op0, c4x_compare_op1);
-   if (operands[1] == NULL_RTX) FAIL;")
-
-(define_expand "bltu"
-  [(set (pc) (if_then_else (ltu (match_dup 1) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (LTU, c4x_compare_op0, c4x_compare_op1);")
-
-(define_expand "bgt"
-  [(set (pc) (if_then_else (gt (match_dup 1) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (GT, c4x_compare_op0, c4x_compare_op1);
-   if (operands[1] == NULL_RTX) FAIL;")
-
-(define_expand "bgtu"
-  [(set (pc) (if_then_else (gtu (match_dup 1) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (GTU, c4x_compare_op0, c4x_compare_op1);")
-
-(define_expand "ble"
-  [(set (pc) (if_then_else (le (match_dup 1) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (LE, c4x_compare_op0, c4x_compare_op1);
-   if (operands[1] == NULL_RTX) FAIL;")
-
-(define_expand "bleu"
-  [(set (pc) (if_then_else (leu (match_dup 1) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (LEU, c4x_compare_op0, c4x_compare_op1);")
-
-(define_expand "bge"
-  [(set (pc) (if_then_else (ge (match_dup 1) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (GE, c4x_compare_op0, c4x_compare_op1);
-   if (operands[1] == NULL_RTX) FAIL;")
-
-(define_expand "bgeu"
-  [(set (pc) (if_then_else (geu (match_dup 1) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "operands[1] = c4x_gen_compare_reg (GEU, c4x_compare_op0, c4x_compare_op1);")
-
-(define_insn "*b_reg"
- [(set (pc) (match_operand:QI 0 "reg_operand" "r"))]
- ""
- "bu%#\\t%0"
-  [(set_attr "type" "jump")])
-
-(define_expand "indirect_jump"
- [(set (pc) (match_operand:QI 0 "reg_operand" ""))]
- ""
- "")
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:QI 0 "src_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "bu%#\\t%0"
-  [(set_attr "type" "jump")])
-
-;
-; CALL
-;
-(define_insn "*call_c3x"
- [(call (match_operand:QI 0 "call_operand" "T,!o")
-        (match_operand:QI 1 "general_operand" ""))
-  (clobber (reg:QI 31))]
-  ;; Operand 1 not really used on the C4x.  The C30 doesn't have reg 31.
-
-  "TARGET_C3X"
-  "@
-   call\\t%C0
-   callu\\t%R0"
-  [(set_attr "type" "call,call")])
-
-; LAJ requires R11 (31) for the return address
-(define_insn "*laj"
- [(call (match_operand:QI 0 "call_operand" "T,!o")
-        (match_operand:QI 1 "general_operand" ""))
-  (clobber (reg:QI 31))]
-  ;; Operand 1 not really used on the C4x.
-
-  "! TARGET_C3X"
-  "*
-   if (which_alternative == 0)
-     {
-       if (final_sequence)
-         return \"laj\\t%C0\";
-       else
-         return \"call\\t%C0\";
-     }
-   else
-     {
-       if (final_sequence)
-         return \"laju\\t%R0\";
-       else
-         return \"callu\\t%R0\";
-     }"
-  [(set_attr "type" "laj,laj")])
-
-(define_expand "call"
- [(parallel [(call (match_operand:QI 0 "call_operand" "")
-                   (match_operand:QI 1 "general_operand" ""))
-             (clobber (reg:QI 31))])]
- ""
- "")
-
-(define_insn "*callv_c3x"
- [(set (match_operand 0 "" "=r,r")
-       (call (match_operand:QI 1 "call_operand" "T,!o")
-             (match_operand:QI 2 "general_operand" "")))
-  (clobber (reg:QI 31))]
-  ;; Operand 0 and 2 not really used for the C4x. 
-  ;; The C30 doesn't have reg 31.
-
-  "TARGET_C3X"
-  "@
-   call\\t%C1
-   callu\\t%R1"
-  [(set_attr "type" "call,call")])
-
-; LAJ requires R11 (31) for the return address
-(define_insn "*lajv"
- [(set (match_operand 0 "" "=r,r")
-       (call (match_operand:QI 1 "call_operand" "T,!o")
-             (match_operand:QI 2 "general_operand" "")))
-  (clobber (reg:QI 31))]
-  ;; Operand 0 and 2 not really used in the C30 instruction.
-
-  "! TARGET_C3X"
-  "*
-   if (which_alternative == 0)
-     {
-       if (final_sequence)
-         return \"laj\\t%C1\";
-       else
-         return \"call\\t%C1\";
-     }
-   else
-     {
-       if (final_sequence)
-         return \"laju\\t%R1\";
-       else
-         return \"callu\\t%R1\";
-     }"
-  [(set_attr "type" "laj,laj")])
-
-(define_expand "call_value"
- [(parallel [(set (match_operand 0 "" "")
-                  (call (match_operand:QI 1 "call_operand" "")
-                        (match_operand:QI 2 "general_operand" "")))
-             (clobber (reg:QI 31))])]
- ""
- "")
-
-(define_insn "return"
-  [(return)]
-  "c4x_null_epilogue_p ()"
-  "rets"
-  [(set_attr "type" "rets")])
-
-(define_insn "*return_cc"
-  [(set (pc)
-        (if_then_else (match_operator 0 "comparison_operator"
-                      [(reg:CC 21) (const_int 0)])
-                      (return)
-                       (pc)))]
-  "c4x_null_epilogue_p ()"
-  "rets%0"
-  [(set_attr "type" "rets")])
-
-(define_insn "*return_cc_noov"
-  [(set (pc)
-        (if_then_else (match_operator 0 "comparison_operator"
-                      [(reg:CC_NOOV 21) (const_int 0)])
-                      (return)
-                       (pc)))]
-  "GET_CODE (operands[0]) != LE
-   && GET_CODE (operands[0]) != GE
-   && GET_CODE (operands[0]) != LT
-   && GET_CODE (operands[0]) != GT
-   && c4x_null_epilogue_p ()"
-  "rets%0"
-  [(set_attr "type" "rets")])
-
-(define_insn "*return_cc_inverse"
-  [(set (pc)
-        (if_then_else (match_operator 0 "comparison_operator"
-                      [(reg:CC 21) (const_int 0)])
-                       (pc)
-                      (return)))]
-  "c4x_null_epilogue_p ()"
-  "rets%I0"
-  [(set_attr "type" "rets")])
-
-(define_insn "*return_cc_noov_inverse"
-  [(set (pc)
-        (if_then_else (match_operator 0 "comparison_operator"
-                      [(reg:CC_NOOV 21) (const_int 0)])
-                       (pc)
-                      (return)))]
-  "GET_CODE (operands[0]) != LE
-   && GET_CODE (operands[0]) != GE
-   && GET_CODE (operands[0]) != LT
-   && GET_CODE (operands[0]) != GT
-   && c4x_null_epilogue_p ()"
-  "rets%I0"
-  [(set_attr "type" "rets")])
-
-(define_insn "jump"
-  [(set (pc) (label_ref (match_operand 0 "" "")))]
-  ""
-  "br%#\\t%l0"
-  [(set_attr "type" "jump")])
-
-;
-; DBcond
-;
-; Note we have to emit a dbu instruction if there are no delay slots
-; to fill.
-; Also note that GCC will try to reverse a loop to see if it can
-; utilise this instruction.  However, if there are more than one
-; memory reference in the loop, it cannot guarantee that reversing
-; the loop will work :(  (see check_dbra_loop() in loop.c)
-; Note that the C3x only decrements the 24 LSBs of the address register
-; and the 8 MSBs are untouched.  The C4x uses all 32-bits.  We thus
-; have an option to disable this instruction.
-(define_insn "*db"
-  [(set (pc)
-        (if_then_else (ne (match_operand:QI 0 "addr_reg_operand" "+a,?*d,??*r,!m")
-                          (const_int 0))
-                      (label_ref (match_operand 1 "" ""))
-                      (pc)))
-   (set (match_dup 0)
-        (plus:QI (match_dup 0)
-                 (const_int -1)))
-   (clobber (reg:CC_NOOV 21))]
-  "TARGET_DB && TARGET_LOOP_UNSIGNED"
-  "*
-  if (which_alternative == 0)
-    return \"dbu%#\\t%0,%l1\";
-  else if (which_alternative == 1)
-    return c4x_output_cbranch (\"subi\\t1,%0\\n\\tbge\", insn);
-  else if (which_alternative == 2)
-    return c4x_output_cbranch (\"subi\\t1,%0\\n\\tcmpi\\t0,%0\\n\\tbge\", insn);
-  else
-    return c4x_output_cbranch (\"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs\", insn);
-  "
-  [(set_attr "type" "db,jmpc,jmpc,jmpc")])
-
-
-; This insn is used for some loop tests, typically loops reversed when
-; strength reduction is used.  It is actually created when the instruction
-; combination phase combines the special loop test.  Since this insn
-; is both a jump insn and has an output, it must deal with its own
-; reloads, hence the `m' constraints. 
-
-; The C4x does the decrement and then compares the result against zero.
-; It branches if the result was greater than or equal to zero.
-; In the RTL the comparison and decrement are assumed to happen
-; at the same time so we bias the iteration counter with by -1
-; when we make the test.
-(define_insn "decrement_and_branch_until_zero"
-  [(set (pc)
-        (if_then_else (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "+a,?*d,??*r,!m")
-			           (const_int -1))
-			  (const_int 0))
-                      (label_ref (match_operand 1 "" ""))
-                      (pc)))
-   (set (match_dup 0)
-        (plus:QI (match_dup 0)
-                 (const_int -1)))
-   (clobber (reg:CC_NOOV 21))]
-  "TARGET_DB && find_reg_note (insn, REG_NONNEG, 0)"
-  "*
-  if (which_alternative == 0)
-    return \"dbu%#\\t%0,%l1\";
-  else if (which_alternative == 1)
-    return c4x_output_cbranch (\"subi\\t1,%0\\n\\tbge\", insn);
-  else if (which_alternative == 2)
-    return c4x_output_cbranch (\"subi\\t1,%0\\n\\tcmpi\\t0,%0\\n\\tbge\", insn);
-  else
-    return c4x_output_cbranch (\"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs\", insn);
-  "
-  [(set_attr "type" "db,jmpc,jmpc,jmpc")])
-
-;
-; MISC INSTRUCTIONS
-;
-
-;
-; NOP
-;
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
-; Default to misc type attr.
-
-
-;
-; RPTB
-;
-(define_insn "rptb_top"
-  [(use (label_ref (match_operand 0 "" "")))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "*
-   return ! final_sequence && c4x_rptb_rpts_p (insn, operands[0])
-	 ? \"rpts\\trc\" : \"rptb%#\\t%l1-1\";
-  "
-  [(set_attr "type" "repeat_top")])
-
-; This pattern needs to be emitted at the start of the loop to
-; say that RS and RE are loaded.
-(define_insn "init_branch_on_count"
-  [(unspec[(match_operand:QI 0 "rc_reg_operand" "v")] 22)
-   (clobber (reg:QI 25))
-   (clobber (reg:QI 26))]
-  ""
-  ""
-  [(set_attr "type" "repeat")])
-
-; The RS (25) and RE (26) registers must be unviolate from the top of the loop
-; to here.
-(define_insn "rptb_end"
-  [(set (pc)
-        (if_then_else (ge (match_operand:QI 2 "rc_reg_operand" "0,0,0,0,0")
-                          (const_int 0))
-                      (label_ref (match_operand 1 "" ""))
-                      (pc)))
-   (set (match_operand:QI 0 "rc_reg_operand" "+v,*a,*d,*x*k,*m")
-        (plus:QI (match_dup 0)
-                 (const_int -1)))
-   (use (reg:QI 25))
-   (use (reg:QI 26))
-   (clobber (reg:CC_NOOV 21))]
-  ""
-  "*
-   if (which_alternative == 0)
-     return c4x_rptb_nop_p (insn) ? \"nop\" : \"\";
-   else if (which_alternative == 1)
-     return \"dbu%#\\t%0,%l1\";
-   else if (which_alternative == 2)
-     return c4x_output_cbranch (\"subi\\t1,%0\\n\\tbge\", insn);
-   else if (which_alternative == 3)
-     return c4x_output_cbranch (\"subi\\t1,%0\\n\\tcmpi\\t0,%0\\n\\tbge\", insn);
-   else
-     return c4x_output_cbranch (\"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs\", insn);
-  "
-  [(set_attr "type" "repeat,db,jmpc,jmpc,jmpc")])
-
-
-(define_expand "decrement_and_branch_on_count"
-  [(parallel [(set (pc)
-                   (if_then_else (ge (match_operand:QI 0 "rc_reg_operand" "")
-                                     (const_int 0))
-                                 (label_ref (match_operand 1 "" ""))
-                                 (pc)))
-              (set (match_dup 0)
-		   (plus:QI (match_dup 0)
-			    (const_int -1)))
-              (use (reg:QI 25))
-              (use (reg:QI 26))
-              (clobber (reg:CC_NOOV 21))])]
-  ""
-  "")
-
-
-(define_expand "movstrqi_small2"
-  [(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" ""))
-                   (mem:BLK (match_operand:BLK 1 "src_operand" "")))
-              (use (match_operand:QI 2 "immediate_operand" ""))
-              (use (match_operand:QI 3 "immediate_operand" ""))
-              (clobber (match_operand:QI 4 "ext_low_reg_operand" ""))])]
-  ""
-  "
- {
-    rtx src, dst, tmp;
-    rtx src_mem, dst_mem;    
-    int len;
-    int i;
-
-    dst = operands[0];
-    src = operands[1];
-    len = INTVAL (operands[2]);
-    tmp = operands[4];
-
-    src_mem = gen_rtx_MEM (QImode, src);
-    dst_mem = gen_rtx_MEM (QImode, dst);
-
-    emit_insn (gen_movqi (tmp, src_mem));	
-    emit_insn (gen_addqi3_noclobber (src, src, const1_rtx));	
-    for (i = 1; i < len; i++)
-      {
-         emit_insn (gen_movqi_parallel (tmp, src_mem, dst_mem, tmp));
-         emit_insn (gen_addqi3_noclobber (src, src, const1_rtx));	
-         emit_insn (gen_addqi3_noclobber (dst, dst, const1_rtx));	
-      }
-    emit_insn (gen_movqi (dst_mem, tmp));	
-    emit_insn (gen_addqi3_noclobber (dst, dst, const1_rtx));	
-    DONE;
-  }
-  ")
-
-
-;
-; BLOCK MOVE
-; We should probably get RC loaded when using RPTB automagically...
-; There's probably no need to call _memcpy() if we don't get
-; a immediate operand for the size.  We could do a better job here
-; than most memcpy() implementations.
-; operand 2 is the number of bytes
-; operand 3 is the shared alignment
-; operand 4 is a scratch register
-
-(define_insn "movstrqi_small"
-  [(set (mem:BLK (match_operand:QI 0 "addr_reg_operand" "a"))
-        (mem:BLK (match_operand:QI 1 "addr_reg_operand" "a")))
-   (use (match_operand:QI 2 "immediate_operand" "i"))
-   (use (match_operand:QI 3 "immediate_operand" ""))
-   (clobber (match_operand:QI 4 "ext_low_reg_operand" "=&q"))
-   (clobber (match_dup 0))
-   (clobber (match_dup 1))]
-  ""
-  "*
- {
-   int i;
-   int len = INTVAL (operands[2]);
-   int first = 1;
-
-   for (i = 0; i < len; i++)
-    {
-      if (first)
-        output_asm_insn (\"ldiu\\t*%1++,%4\", operands);
-      else
-        output_asm_insn (\"|| ldi\\t*%1++,%4\", operands);
-      output_asm_insn (\"sti\\t%4,*%0++\", operands);
-      first = 0;
-    } 
-  return \"\";
-  }
-  "
-  [(set_attr "type" "multi")])
-
-(define_insn "movstrqi_large"
-  [(set (mem:BLK (match_operand:QI 0 "addr_reg_operand" "a"))
-        (mem:BLK (match_operand:QI 1 "addr_reg_operand" "a")))
-   (use (match_operand:QI 2 "immediate_operand" "i"))
-   (use (match_operand:QI 3 "immediate_operand" ""))
-   (clobber (match_operand:QI 4 "ext_low_reg_operand" "=&q"))
-   (clobber (match_dup 0))
-   (clobber (match_dup 1))
-   (clobber (reg:QI 25))
-   (clobber (reg:QI 26))
-   (clobber (reg:QI 27))]
-  ""
-  "*
- {
-   int len = INTVAL (operands[2]);
-
-   output_asm_insn (\"ldiu\\t*%1++,%4\", operands);
-   if (TARGET_RPTS_CYCLES (len))
-     {
-        output_asm_insn (\"rpts\\t%2-2\", operands);  
-        output_asm_insn (\"sti\\t%4,*%0++\", operands);
-        output_asm_insn (\"|| ldi\\t*%1++,%4\", operands);
-        return \"sti\\t%4,*%0++\";
-     }
-   else
-     {
-        output_asm_insn (\"ldiu\\t%2-2,rc\", operands);
-        output_asm_insn (\"rptb\\t$+1\", operands);  
-        output_asm_insn (\"sti\\t%4,*%0++\", operands);
-        output_asm_insn (\"|| ldi\\t*%1++,%4\", operands);
-
-        return \"sti\\t%4,*%0++\";
-     }
-  }
-  "
-  [(set_attr "type" "multi")])
-
-; Operand 2 is the count, operand 3 is the alignment.
-(define_expand "movstrqi"
-  [(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" ""))
-                   (mem:BLK (match_operand:BLK 1 "src_operand" "")))
-              (use (match_operand:QI 2 "immediate_operand" ""))
-              (use (match_operand:QI 3 "immediate_operand" ""))])]
-  ""
-  "
- {
-   rtx tmp;
-   if (GET_CODE (operands[2]) != CONST_INT 
-       || INTVAL (operands[2]) > 32767 
-       || INTVAL (operands[2]) <= 0)
-     {
-        FAIL;  /* Try to call _memcpy */
-     }
-
-   operands[0] = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
-   operands[1] = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
-   tmp = gen_reg_rtx (QImode);
-   if (INTVAL (operands[2]) < 8)
-     emit_insn (gen_movstrqi_small (operands[0], operands[1], operands[2],
-                                    operands[3], tmp));
-   else
-     {
-      emit_insn (gen_movstrqi_large (operands[0], operands[1], operands[2],
-                                     operands[3], tmp));
-     }
-   DONE;
- }")
-
-
-(define_insn "*cmpstrqi"
-  [(set (match_operand:QI 0 "reg_operand" "=d")
-        (compare:QI (mem:BLK (match_operand:QI 1 "addr_reg_operand" "a"))
-                    (mem:BLK (match_operand:QI 2 "addr_reg_operand" "a"))))
-   (use (match_operand:QI 3 "immediate_operand" "i"))
-   (use (match_operand:QI 4 "immediate_operand" ""))
-   (clobber (match_operand:QI 5 "std_reg_operand" "=&c"))
-   (clobber (reg:QI 21))]
-  ""
-  "*
- {
-    output_asm_insn (\"ldi\\t%3-1,%5\", operands);
-    output_asm_insn (\"$1:\tsubi3\\t*%1++,*%2++,%0\", operands);
-    output_asm_insn (\"dbeq\\t%5,$1\", operands);
-    return \"\";
- }")
-
-(define_expand "cmpstrqi"
-  [(parallel [(set (match_operand:QI 0 "reg_operand" "")
-                   (compare:QI (match_operand:BLK 1 "general_operand" "")
-                               (match_operand:BLK 2 "general_operand" "")))
-              (use (match_operand:QI 3 "immediate_operand" ""))
-              (use (match_operand:QI 4 "immediate_operand" ""))
-              (clobber (match_dup 5))
-              (clobber (reg:QI 21))])]
-  ""
-  "
-{
-   if (GET_CODE (operands[3]) != CONST_INT
-       || INTVAL (operands[3]) > 32767 
-       || INTVAL (operands[3]) <= 0)
-     {
-        FAIL;
-     }
-   operands[1] = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
-   operands[2] = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
-   operands[5] = gen_reg_rtx (QImode);
-}")
-
-;
-; TWO OPERAND LONG DOUBLE INSTRUCTIONS
-;
-
-(define_expand "movhf"
-  [(set (match_operand:HF 0 "src_operand" "")
-        (match_operand:HF 1 "src_operand" ""))]
- ""
- "if (CONSTANT_P (operands[1]))
-    {
-      operands[1] = force_const_mem (HFmode, operands[1]); 
-      if (! memory_address_p (HFmode, XEXP (operands[1], 0))
-          && ! reload_in_progress)
-        operands[1] = change_address (operands[1], HFmode,
-                                      XEXP (operands[1], 0));
-     }
-
-  /* Memory to memory copies must go through a register.  */
-  if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[0]) == MEM
-      && ! reload_in_progress)
-    operands[1] = force_reg (HFmode, operands[1]); 
-")
-
-(define_insn "*movhf_noclobber_reg"
-  [(set (match_operand:HF 0 "reg_operand" "=h")
-        (match_operand:HF 1 "reg_operand" "h"))]
- ""
- "ldfu\\t%1,%0"
-  [(set_attr "type" "unary")])
-
-; The predicates could be tightened to disallow constants
-(define_insn "*movhf_noclobber"
- [(set (match_operand:HF 0 "src_operand" "=h,m")
-       (match_operand:HF 1 "src_operand" "m,h"))]
- "reg_operand (operands[0], HFmode) ^ reg_operand (operands[1], HFmode)"
- "#"
- [(set_attr "type" "multi,multi")])
-
-(define_insn "*movhf_test"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:HF 1 "reg_operand" "h")
-                    (const_int 0)))
-   (clobber (match_scratch:HF 0 "=h"))]
- ""
- "ldf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*movhf_set"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:HF 1 "reg_operand" "h")
-                    (match_operand:HF 2 "fp_zero_operand" "G")))
-    (set (match_operand:HF 0 "reg_operand" "=h")
-         (match_dup 1))]
- ""
- "ldf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_split
- [(set (match_operand:HF 0 "reg_operand" "")
-       (match_operand:HF 1 "memory_operand" ""))]
- "reload_completed"
- [(set (match_dup 0) (float_extend:HF (match_dup 2)))
-  (set (match_dup 0) (unspec[(subreg:QI (match_dup 0) 0) (match_dup 3)] 8))]
- "operands[2] = c4x_operand_subword (operands[1], 0, 1, HFmode);
-  operands[3] = c4x_operand_subword (operands[1], 1, 1, HFmode);
-  PUT_MODE (operands[2], QFmode);
-  PUT_MODE (operands[3], QImode);")
-
-(define_split
- [(set (match_operand:HF 0 "reg_operand" "")
-       (match_operand:HF 1 "const_operand" ""))]
- "reload_completed && 0"
- [(set (match_dup 0) (float_extend:HF (match_dup 2)))
-  (set (match_dup 0) (unspec[(subreg:QI (match_dup 0) 0) (match_dup 3)] 8))]
- "operands[2] = c4x_operand_subword (operands[1], 0, 1, HFmode);
-  operands[3] = c4x_operand_subword (operands[1], 1, 1, HFmode);
-  PUT_MODE (operands[2], QFmode);
-  PUT_MODE (operands[3], QImode);")
-
-(define_split
- [(set (match_operand:HF 0 "memory_operand" "")
-       (match_operand:HF 1 "reg_operand" ""))]
-  "reload_completed"
-  [(set (match_dup 2) (float_truncate:QF (match_dup 1)))
-   (set (match_dup 3) (unspec [(match_dup 1)] 9))]
- "operands[2] = c4x_operand_subword (operands[0], 0, 1, HFmode);
-  operands[3] = c4x_operand_subword (operands[0], 1, 1, HFmode);
-  PUT_MODE (operands[2], QFmode);
-  PUT_MODE (operands[3], QImode);")
-
-(define_insn "*loadhf_float"
- [(set (match_operand:HF 0 "reg_operand" "=h")
-       (float_extend:HF (match_operand:QF 1 "src_operand" "fmH")))]
- ""
- "@
-  ldfu\\t%1,%0"
-  [(set_attr "type" "unary")])
-
-(define_insn "*loadhf_int"
- [(set (match_operand:HF 0 "reg_operand" "=h")
-       (unspec[(subreg:QI (match_dup 0) 0)
-               (match_operand:QI 1 "src_operand" "g")] 8))]
- ""
- "@
-  ldiu\\t%1,%0"
-  [(set_attr "type" "unary")])
-
-(define_insn "*storehf_float"
-  [(set (match_operand:QF 0 "memory_operand" "=m")
-        (float_truncate:QF (match_operand:HF 1 "reg_operand" "h")))]
-  ""
-  "stf\\t%1,%0"
-  [(set_attr "type" "store")])
-
-(define_insn "*storehf_int"
- [(set (match_operand:QI 0 "memory_operand" "=m")
-       (unspec [(match_operand:HF 1 "reg_operand" "h")] 9))]
- ""
- "@
-  sti\\t%1,%0"
-  [(set_attr "type" "store")])
-
-(define_insn "extendqfhf2"
-  [(set (match_operand:HF 0 "reg_operand" "=h")
-        (float_extend:HF (match_operand:QF 1 "reg_operand" "h")))]
-  ""
-  "ldfu\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "trunchfqf2"
-  [(set (match_operand:QF 0 "reg_operand" "=h")
-        (float_truncate:QF (match_operand:HF 1 "reg_operand" "0")))
-   (clobber (reg:CC 21))]
-  ""
-  "andn\\t0ffh,%0"
-  [(set_attr "type" "unarycc")])
-
-;
-; PUSH/POP
-;
-(define_insn "*pushhf"
-  [(set (mem:HF (pre_inc:QI (reg:QI 20)))
-        (match_operand:HF 0 "reg_operand" "h"))]
- ""
- "#"
- [(set_attr "type" "multi")])
-
-(define_split
- [(set (mem:HF (pre_inc:QI (reg:QI 20)))
-        (match_operand:HF 0 "reg_operand" ""))]
-  "reload_completed"
-  [(set (mem:QF (pre_inc:QI (reg:QI 20)))
-        (float_truncate:QF (match_dup 0)))
-   (set (mem:QI (pre_inc:QI (reg:QI 20)))
-        (unspec [(match_dup 0)] 9))]
- "")
-
-(define_insn "pushhf_trunc"
-  [(set (mem:QF (pre_inc:QI (reg:QI 20)))
-        (float_truncate:QF (match_operand:HF 0 "reg_operand" "h")))]
- ""
- "pushf\\t%0"
- [(set_attr "type" "push")])
-
-(define_insn "pushhf_int"
-  [(set (mem:QI (pre_inc:QI (reg:QI 20)))
-        (unspec [(match_operand:HF 0 "reg_operand" "h")] 9))]
- ""
- "push\\t%0"
- [(set_attr "type" "push")])
-
-; we can not use this because the popf will destroy the low 8 bits
-;(define_insn "*pophf"
-;  [(set (match_operand:HF 0 "reg_operand" "=h")
-;        (mem:HF (post_dec:QI (reg:QI 20))))
-;   (clobber (reg:CC 21))]
-; ""
-; "#"
-; [(set_attr "type" "multi")])
-
-(define_split
- [(set (match_operand:HF 0 "reg_operand" "")
-       (mem:HF (post_dec:QI (reg:QI 20))))
-   (clobber (reg:CC 21))]
-  "reload_completed"
-  [(parallel [(set (match_operand:HF 0 "reg_operand" "=h")
-                   (float_extend:HF (mem:QF (post_dec:QI (reg:QI 20)))))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_dup 0)
-                   (unspec[(subreg:QI (match_dup 0) 0)
-                   (mem:QI (post_dec:QI (reg:QI 20)))] 8))
-              (clobber (reg:CC 21))])]
- "")
-
-(define_insn "*pophf_int"
- [(set (match_operand:HF 0 "reg_operand" "=h")
-       (unspec[(subreg:QI (match_dup 0) 0)
-               (mem:QI (post_dec:QI (reg:QI 20)))] 8))
-  (clobber (reg:CC 21))]
- ""
- "@
-  pop\\t%0"
-  [(set_attr "type" "pop")])
-
-(define_insn "*pophf_float"
- [(set (match_operand:HF 0 "reg_operand" "=h")
-       (float_extend:HF (mem:QF (post_dec:QI (reg:QI 20)))))
-  (clobber (reg:CC 21))]
- ""
- "@
-  popf\\t%0"
-  [(set_attr "type" "unary")])
-
-;
-; FIX
-;
-(define_insn "fixhfqi_clobber"
-  [(set (match_operand:QI 0 "reg_operand" "=dc")
-        (fix:QI (match_operand:HF 1 "reg_or_const_operand" "hH")))
-   (clobber (reg:CC 21))]
- ""
- "fix\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-;
-; ABSF
-;
-(define_expand "abshf2"
-  [(parallel [(set (match_operand:HF 0 "reg_operand" "")
-                   (abs:HF (match_operand:HF 1 "reg_or_const_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-""
-"")
-
-(define_insn "*abshf2_clobber"
-  [(set (match_operand:HF 0 "reg_operand" "=h")
-        (abs:HF (match_operand:HF 1 "reg_or_const_operand" "hH")))
-   (clobber (reg:CC_NOOV 21))]
-  ""
-  "absf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*abshf2_test"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (abs:HF (match_operand:HF 1 "reg_operand" "h"))
-                         (match_operand:HF 2 "fp_zero_operand" "G")))
-   (clobber (match_scratch:HF 0 "=h"))]
-  ""
-  "absf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*abshf2_set"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (abs:HF (match_operand:HF 1 "reg_or_const_operand" "hH"))
-                         (match_operand:HF 2 "fp_zero_operand" "G")))
-   (set (match_operand:HF 0 "reg_operand" "=h")
-        (abs:HF (match_dup 1)))]
-
-  ""
-  "absf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-;
-; NEGF
-;
-(define_expand "neghf2"
-  [(parallel [(set (match_operand:HF 0 "reg_operand" "")
-                   (neg:HF (match_operand:HF 1 "reg_or_const_operand" "")))
-              (clobber (reg:CC 21))])]
-""
-"")
-
-(define_insn "*neghf2_clobber"
-  [(set (match_operand:HF 0 "reg_operand" "=h")
-        (neg:HF (match_operand:HF 1 "reg_or_const_operand" "hH")))
-   (clobber (reg:CC 21))]
-  ""
-  "negf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*neghf2_test"
-  [(set (reg:CC 21)
-        (compare:CC (neg:HF (match_operand:HF 1 "reg_or_const_operand" "hH"))
-                    (match_operand:HF 2 "fp_zero_operand" "G")))
-   (clobber (match_scratch:HF 0 "=h"))]
-  ""
-  "negf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-(define_insn "*neghf2_set"
-  [(set (reg:CC 21)
-        (compare:CC (neg:HF (match_operand:HF 1 "reg_or_const_operand" "hH"))
-                    (match_operand:HF 2 "fp_zero_operand" "G")))
-   (set (match_operand:HF 0 "reg_operand" "=h")
-        (neg:HF (match_dup 1)))]
-  ""
-  "negf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-;
-; RCPF
-;
-(define_insn "*rcpfhf_clobber"
-  [(set (match_operand:HF 0 "reg_operand" "=h")
-        (unspec [(match_operand:HF 1 "reg_or_const_operand" "hH")] 5))
-   (clobber (reg:CC_NOOV 21))]
-  "! TARGET_C3X"
-  "rcpf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-;
-; RSQRF
-;
-(define_insn "*rsqrfhf_clobber"
-  [(set (match_operand:HF 0 "reg_operand" "=h")
-        (unspec [(match_operand:HF 1 "reg_or_const_operand" "hH")] 10))
-   (clobber (reg:CC_NOOV 21))]
-  "! TARGET_C3X"
-  "rsqrf\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-;
-; RNDF
-;
-(define_insn "*rndhf_clobber"
-  [(set (match_operand:HF 0 "reg_operand" "=h")
-        (unspec [(match_operand:HF 1 "reg_or_const_operand" "hH")] 6))
-   (clobber (reg:CC_NOOV 21))]
-  "! TARGET_C3X"
-  "rnd\\t%1,%0"
-  [(set_attr "type" "unarycc")])
-
-
-; Inlined float square root for C4x
-(define_expand "sqrthf2_inline"
-  [(parallel [(set (match_dup 2)
-	           (unspec [(match_operand:HF 1 "reg_operand" "")] 10))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 3) (mult:HF (match_dup 5) (match_dup 1)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 4)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (minus:HF (match_dup 6) (match_dup 4)))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 2) (mult:HF (match_dup 2) (match_dup 4)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 4)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (minus:HF (match_dup 6) (match_dup 4)))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 2) (mult:HF (match_dup 2) (match_dup 4)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_operand:HF 0 "reg_operand" "")
-		   (mult:HF (match_dup 2) (match_dup 1)))
-	      (clobber (reg:CC_NOOV 21))])]
-  "! TARGET_C3X"
-  "
-  operands[2] = gen_reg_rtx (HFmode);
-  operands[3] = gen_reg_rtx (HFmode);
-  operands[4] = gen_reg_rtx (HFmode);
-  operands[5] = immed_real_const_1 (REAL_VALUE_ATOF (\"0.5\", HFmode), HFmode);
-  operands[6] = immed_real_const_1 (REAL_VALUE_ATOF (\"1.5\", HFmode), HFmode);
-  ")
-
-
-(define_expand "sqrthf2"
-  [(parallel [(set (match_operand:HF 0 "reg_operand" "")
-                   (sqrt:HF (match_operand:HF 1 "reg_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "if (TARGET_C3X || ! TARGET_INLINE)
-     FAIL;
-   else
-     {
-       emit_insn (gen_sqrthf2_inline (operands[0], operands[1]));
-       DONE;
-     }
-  ")
-
-(define_expand "fix_trunchfhi2"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-                   (fix:HI (match_operand:HF 1 "reg_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall (FIX_TRUNCHFHI2_LIBCALL, FIX, HImode, HFmode, 2, operands);
-   DONE;")
-
-(define_expand "fixuns_trunchfhi2"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-                   (unsigned_fix:HI (match_operand:HF 1 "reg_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall (FIXUNS_TRUNCHFHI2_LIBCALL, UNSIGNED_FIX, 
-                     HImode, HFmode, 2, operands);
-   DONE;")
-
-;
-; THREE OPERAND LONG DOUBLE INSTRUCTIONS
-;
-
-;
-; ADDF
-;
-(define_insn "addhf3"
-  [(set (match_operand:HF 0 "reg_operand" "=?h,h")
-        (plus:HF (match_operand:HF 1 "reg_operand" "%h,0")
-                 (match_operand:HF 2 "reg_or_const_operand" "h,H")))
-   (clobber (reg:CC_NOOV 21))]
-  ""
-  "@
-   addf3\\t%2,%1,%0
-   addf\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc")])
-
-;
-; SUBF
-;
-(define_insn "subhf3"
-  [(set (match_operand:HF 0 "reg_operand" "=?h,h,h")
-        (minus:HF (match_operand:HF 1 "reg_or_const_operand" "h,0,H")
-                  (match_operand:HF 2 "reg_or_const_operand" "h,H,0")))
-   (clobber (reg:CC_NOOV 21))]
-  ""
-  "@
-   subf3\\t%2,%1,%0
-   subf\\t%2,%0
-   subrf\\t%1,%0"
-  [(set_attr "type" "binarycc,binarycc,binarycc")])
-
-;
-; MULF
-;
-; The C3x MPYF only uses 24 bit precision while the C4x uses 32 bit precison.
-;
-(define_expand "mulhf3"
-  [(parallel [(set (match_operand:HF 0 "reg_operand" "=h")
-                   (mult:HF (match_operand:HF 1 "reg_operand" "h")
-                            (match_operand:HF 2 "reg_operand" "h")))
-              (clobber (reg:CC_NOOV 21))])]
-  ""
-  "if (TARGET_C3X)
-     {
-       c4x_emit_libcall3 (MULHF3_LIBCALL, MULT, HFmode, operands);
-       DONE;
-     }
-  ")
-
-(define_insn "*mulhf3_c40"
-  [(set (match_operand:HF 0 "reg_operand" "=?h,h")
-        (mult:HF (match_operand:HF 1 "reg_operand" "%h,0")
-                 (match_operand:HF 2 "reg_or_const_operand" "h,hH")))
-   (clobber (reg:CC_NOOV 21))]
-  ""
-  "@
-   mpyf3\\t%2,%1,%0
-   mpyf\\t%2,%0"
-  [(set_attr "type" "binarycc,binarycc")])
-
-;
-; CMPF
-;
-(define_expand "cmphf"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:HF 0 "reg_operand" "")
-                    (match_operand:HF 1 "reg_or_const_operand" "")))]
-  ""
-  "c4x_compare_op0 = operands[0];
-   c4x_compare_op1 = operands[1];
-   DONE;")
-
-(define_insn "*cmphf"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:HF 0 "reg_operand" "h")
-                    (match_operand:HF 1 "reg_or_const_operand" "hH")))]
-  ""
-  "cmpf\\t%1,%0"
-  [(set_attr "type" "compare")])
-
-(define_insn "*cmphf_noov"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (match_operand:HF 0 "reg_operand" "h")
-                         (match_operand:HF 1 "reg_or_const_operand" "hH")))]
-  ""
-  "cmpf\\t%1,%0"
-  [(set_attr "type" "compare")])
-
-; Inlined float divide for C4x
-(define_expand "divhf3_inline"
-  [(parallel [(set (match_dup 3)
-	           (unspec [(match_operand:HF 2 "reg_operand" "")] 5))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (minus:HF (match_dup 5) (match_dup 4)))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 3) (mult:HF (match_dup 3) (match_dup 4)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 4) (minus:HF (match_dup 5) (match_dup 4)))
-              (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_dup 3) (mult:HF (match_dup 3) (match_dup 4)))
-	      (clobber (reg:CC_NOOV 21))])
-   (parallel [(set (match_operand:HF 0 "reg_operand" "")
-		   (mult:HF (match_operand:HF 1 "reg_operand" "")
-	         	    (match_dup 3)))
-	      (clobber (reg:CC_NOOV 21))])]
-  "! TARGET_C3X"
-  "
-  operands[3] = gen_reg_rtx (HFmode);
-  operands[4] = gen_reg_rtx (HFmode);
-  operands[5] = CONST2_RTX (HFmode);
-  ")
-
-(define_expand "divhf3"
-  [(parallel [(set (match_operand:HF 0 "reg_operand" "")
-                   (div:HF (match_operand:HF 1 "reg_operand" "")
-                           (match_operand:HF 2 "reg_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "if (TARGET_C3X || ! TARGET_INLINE)
-     {
-       c4x_emit_libcall3 (DIVHF3_LIBCALL, DIV, HFmode, operands);
-       DONE;
-     }
-   else
-     {
-       emit_insn (gen_divhf3_inline (operands[0], operands[1], operands[2]));
-       DONE;
-     }
-  ")
-
-
-;
-; TWO OPERAND LONG LONG INSTRUCTIONS
-;
-
-; We could load some constants using define_splits for the C30
-; in the large memory model---these would emit shift and or insns.
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "src_operand" "")
-        (match_operand:HI 1 "src_operand" ""))]
- ""
- "if (CONSTANT_P (operands[1]))
-    {
-      /* We don't need to force all constants into memory.
-         This could be improved.... */
-      operands[1] = force_const_mem (HImode, operands[1]); 
-      if (! memory_address_p (HImode, XEXP (operands[1], 0))
-          && ! reload_in_progress)
-        operands[1] = change_address (operands[1], HImode,
-                                      XEXP (operands[1], 0));
-     }
-
-  /* Memory to memory copies must go through a register.  */
-  if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[0]) == MEM
-      && ! reload_in_progress)
-    operands[1] = force_reg (HImode, operands[1]); 
-")
-
-; The constraints for movhi must include 'r' if we don't
-; restrict HImode regnos to start on an even number, since
-; we can get RC, R8 allocated as a pair.  We want more
-; votes for FP_REGS so we use dr as the constraints.
-(define_insn "*movhi_noclobber"
-  [(set (match_operand:HI 0 "src_operand" "=dr,m")
-        (match_operand:HI 1 "src_operand" "drm,r"))]
-  "reg_operand (operands[0], HImode)
-   || reg_operand (operands[1], HImode)"
-  "#"
-  [(set_attr "type" "multi,multi")])
-
-(define_split
-  [(set (match_operand:HI 0 "src_operand" "")
-	(match_operand:HI 1 "src_operand" ""))]
-  "reload_completed
-   && (reg_operand (operands[0], HImode) || reg_operand (operands[1], HImode))"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 5))]
-  "operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
-   operands[3] = c4x_operand_subword (operands[1], 0, 1, HImode);
-   operands[4] = c4x_operand_subword (operands[0], 1, 1, HImode);
-   operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);")
-
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "reg_operand" "=dc")
-        (sign_extend:HI (match_operand:QI 1 "src_operand" "g")))
-   (clobber (reg:CC 21))]
-  ""
-  "#"
-  [(set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:HI 0 "reg_operand" "=?dc")
-        (sign_extend:HI (match_operand:QI 1 "src_operand" "g")))
-   (clobber (reg:CC 21))]
-  "reload_completed && TARGET_C3X"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 3) (match_dup 2))
-   (parallel [(set (match_dup 3) (ashiftrt:QI (match_dup 3) (const_int 31)))
-              (clobber (reg:CC 21))])]
-  "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
-   operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
-
-(define_split
-  [(set (match_operand:HI 0 "reg_operand" "=?dc")
-        (sign_extend:HI (match_operand:QI 1 "src_operand" "g")))
-   (clobber (reg:CC 21))]
-  "reload_completed && ! TARGET_C3X"
-  [(set (match_dup 2) (match_dup 1))
-   (parallel [(set (match_dup 3) (ashiftrt:QI (match_dup 2) (const_int 31)))
-              (clobber (reg:CC 21))])]
-  "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
-   operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "reg_operand" "=?dc")
-        (zero_extend:HI (match_operand:QI 1 "src_operand" "g")))
-   (clobber (reg:CC 21))]
-  ""
-  "#"
-  [(set_attr "type" "multi")])
-
-; If operand0 and operand1 are the same register we don't need
-; the first set.
-(define_split
-  [(set (match_operand:HI 0 "reg_operand" "=?dc")
-        (zero_extend:HI (match_operand:QI 1 "src_operand" "g")))
-   (clobber (reg:CC 21))]
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 3) (const_int 0))]
-  "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
-   operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
-
-;
-; PUSH/POP
-;
-(define_insn "*pushhi"
-  [(set (mem:HI (pre_inc:QI (reg:QI 20)))
-        (match_operand:HI 0 "reg_operand" "r"))]
-  ""
-  "#"
-  [(set_attr "type" "multi")])
-
-(define_split
-  [(set (mem:HI (pre_inc:QI (reg:QI 20)))
-        (match_operand:HI 0 "reg_operand" ""))]
-  "reload_completed"
-  [(set (mem:QI (pre_inc:QI (reg:QI 20))) (match_dup 2))
-   (set (mem:QI (pre_inc:QI (reg:QI 20))) (match_dup 3))]
-  "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
-   operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
-
-(define_insn "*pophi"
-  [(set (match_operand:HI 0 "reg_operand" "=r")
-        (mem:HI (post_dec:QI (reg:QI 20))))
-   (clobber (reg:CC 21))]
-  ""
-  "#"
-  [(set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:HI 0 "reg_operand" "")
-       (mem:HI (pre_inc:QI (reg:QI 20))))]
-  "reload_completed"
-  [(set (match_dup 2) (mem:QI (pre_inc:QI (reg:QI 20))))
-   (set (match_dup 3) (mem:QI (pre_inc:QI (reg:QI 20))))]
-  "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
-   operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
-
-;
-; NEG
-;
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "ext_reg_operand" "=d")
-        (neg:HI (match_operand:HI 1 "src_operand" "rm")))
-   (clobber (reg:CC_NOOV 21))]
-  ""
-  "#"
-  [(set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:HI 0 "ext_reg_operand" "")
-        (neg:HI (match_operand:HI 1 "src_operand" "")))
-   (clobber (reg:CC_NOOV 21))]
-  "reload_completed"
-   [(parallel [(set (reg:CC_NOOV 21)
-                    (compare:CC_NOOV (neg:QI (match_dup 3))
-                                     (const_int 0)))
-               (set (match_dup 2) (neg:QI (match_dup 3)))])
-   (parallel [(set (match_dup 4) (neg:QI (match_dup 5)))
-              (use (reg:CC_NOOV 21))
-              (clobber (reg:CC_NOOV 21))])]
-  "operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
-   operands[3] = c4x_operand_subword (operands[1], 0, 1, HImode);
-   operands[4] = c4x_operand_subword (operands[0], 1, 1, HImode);
-   operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);")
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "reg_operand" "=r")
-        (not:HI (match_operand:HI 1 "src_operand" "rm")))
-   (clobber (reg:CC 21))]
-  ""
-  "#"
-  [(set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:HI 0 "reg_operand" "")
-        (not:HI (match_operand:HI 1 "src_operand" "")))
-   (clobber (reg:CC 21))]
-  "reload_completed"
-   [(parallel [(set (match_dup 2) (not:QI (match_dup 3)))
-               (clobber (reg:CC 21))])
-    (parallel [(set (match_dup 4) (not:QI (match_dup 5)))
-               (clobber (reg:CC 21))])]
-  "operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
-   operands[3] = c4x_operand_subword (operands[1], 0, 1, HImode);
-   operands[4] = c4x_operand_subword (operands[0], 1, 1, HImode);
-   operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);")
-
-(define_expand "floathiqf2"
-  [(parallel [(set (match_operand:QF 0 "reg_operand" "")
-                   (float:QF (match_operand:HI 1 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall (FLOATHIQF2_LIBCALL, FLOAT, QFmode, HImode, 2, operands);
-   DONE;")
-
-(define_expand "floatunshiqf2"
-  [(parallel [(set (match_operand:QF 0 "reg_operand" "")
-                   (unsigned_float:QF (match_operand:HI 1 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall (FLOATUNSHIQF2_LIBCALL, UNSIGNED_FLOAT,
-                     QFmode, HImode, 2, operands);
-   DONE;")
-
-(define_expand "floathihf2"
-  [(parallel [(set (match_operand:HF 0 "reg_operand" "")
-                   (float:HF (match_operand:HI 1 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall (FLOATHIHF2_LIBCALL, FLOAT, HFmode, HImode, 2, operands);
-   DONE;")
-
-(define_expand "floatunshihf2"
-  [(parallel [(set (match_operand:HF 0 "reg_operand" "")
-                   (unsigned_float:HF (match_operand:HI 1 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall (FLOATUNSHIHF2_LIBCALL, UNSIGNED_FLOAT,
-                     HFmode, HImode, 2, operands);
-   DONE;")
-
-
-;
-; THREE OPERAND LONG LONG INSTRUCTIONS
-;
-
-(define_expand "addhi3"
-  [(parallel [(set (match_operand:HI 0 "ext_reg_operand" "")
-                   (plus:HI (match_operand:HI 1 "src_operand" "")
-                            (match_operand:HI 2 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-  ""
-  "legitimize_operands (PLUS, operands, HImode);")
-
-(define_insn "*addhi3_clobber"
-  [(set (match_operand:HI 0 "ext_reg_operand" "=d,?d,d")
-        (plus:HI (match_operand:HI 1 "src_operand" "%rR,rS<>,0")
-                 (match_operand:HI 2 "src_operand" "R,rS<>,rm")))
-   (clobber (reg:CC_NOOV 21))]
-  "valid_operands (PLUS, operands, HImode)"
-  "#"
-  [(set_attr "type" "multi,multi,multi")])
-
-(define_split
- [(set (match_operand:HI 0 "ext_reg_operand" "")
-       (plus:HI (match_operand:HI 1 "src_operand" "")
-                (match_operand:HI 2 "src_operand" "")))
-  (clobber (reg:CC_NOOV 21))]
- "reload_completed"
-  [(parallel [(set (reg:CC_NOOV 21)
-                   (compare:CC_NOOV (plus:QI (match_dup 4) (match_dup 5))
-                                    (const_int 0)))
-              (set (match_dup 3) (plus:QI (match_dup 4) (match_dup 5)))])
-   (parallel [(set (match_dup 6) (plus:QI (match_dup 7) (match_dup 8)))
-              (use (reg:CC_NOOV 21))
-              (clobber (reg:CC_NOOV 21))])]
-  "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
-   operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
-   operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
-   operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
-   operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
-   operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
-
-(define_expand "subhi3"
-  [(parallel [(set (match_operand:HI 0 "ext_reg_operand" "")
-                   (minus:HI (match_operand:HI 1 "src_operand" "")
-                             (match_operand:HI 2 "src_operand" "")))
-              (clobber (reg:CC_NOOV 21))])]
-  ""
-  "legitimize_operands (MINUS, operands, HImode);")
-
-
-(define_insn "*subhi3_clobber"
-  [(set (match_operand:HI 0 "ext_reg_operand" "=d,?d,d")
-        (minus:HI (match_operand:HI 1 "src_operand" "rR,rS<>,0")
-                  (match_operand:HI 2 "src_operand" "R,rS<>,rm")))
-   (clobber (reg:CC_NOOV 21))]
-  "valid_operands (MINUS, operands, HImode)"
-  "#"
-  [(set_attr "type" "multi,multi,multi")])
-
-(define_split
- [(set (match_operand:HI 0 "ext_reg_operand" "")
-       (minus:HI (match_operand:HI 1 "src_operand" "")
-                 (match_operand:HI 2 "src_operand" "")))
-  (clobber (reg:CC_NOOV 21))]
- "reload_completed"
-  [(parallel [(set (reg:CC_NOOV 21)
-                   (compare:CC_NOOV (minus:QI (match_dup 4) (match_dup 5))
-                                    (const_int 0)))
-              (set (match_dup 3) (minus:QI (match_dup 4) (match_dup 5)))])
-   (parallel [(set (match_dup 6) (minus:QI (match_dup 7) (match_dup 8)))
-              (use (reg:CC_NOOV 21))
-              (clobber (reg:CC_NOOV 21))])]
-  "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
-   operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
-   operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
-   operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
-   operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
-   operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
-
-(define_expand "iorhi3"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-                   (ior:HI (match_operand:HI 1 "src_operand" "")
-                           (match_operand:HI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "legitimize_operands (IOR, operands, HImode);")
-
-(define_insn "*iorhi3_clobber"
-  [(set (match_operand:HI 0 "reg_operand" "=d,?d,d")
-        (ior:HI (match_operand:HI 1 "src_operand" "%rR,rS<>,0")
-                (match_operand:HI 2 "src_operand" "R,rS<>,rm")))
-   (clobber (reg:CC 21))]
-  "valid_operands (IOR, operands, HImode)"
-  "#"
-  [(set_attr "type" "multi,multi,multi")])
-
-(define_split
- [(set (match_operand:HI 0 "reg_operand" "")
-       (ior:HI (match_operand:HI 1 "src_operand" "")
-               (match_operand:HI 2 "src_operand" "")))
-  (clobber (reg:CC 21))]
- "reload_completed"
-  [(parallel [(set (match_dup 3) (ior:QI (match_dup 4) (match_dup 5)))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_dup 6) (ior:QI (match_dup 7) (match_dup 8)))
-              (clobber (reg:CC 21))])]
-  "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
-   operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
-   operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
-   operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
-   operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
-   operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
-
-(define_expand "andhi3"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-                   (and:HI (match_operand:HI 1 "src_operand" "")
-                           (match_operand:HI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "legitimize_operands (AND, operands, HImode);")
-
-(define_insn "*andhi3_clobber"
-  [(set (match_operand:HI 0 "reg_operand" "=d,?d,d")
-        (and:HI (match_operand:HI 1 "src_operand" "%rR,rS<>,0")
-                (match_operand:HI 2 "src_operand" "R,rS<>,rm")))
-   (clobber (reg:CC 21))]
-  "valid_operands (AND, operands, HImode)"
-  "#"
-  [(set_attr "type" "multi,multi,multi")])
-
-(define_split
- [(set (match_operand:HI 0 "reg_operand" "")
-       (and:HI (match_operand:HI 1 "src_operand" "")
-                (match_operand:HI 2 "src_operand" "")))
-  (clobber (reg:CC 21))]
- "reload_completed"
-  [(parallel [(set (match_dup 3) (and:QI (match_dup 4) (match_dup 5)))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_dup 6) (and:QI (match_dup 7) (match_dup 8)))
-              (clobber (reg:CC 21))])]
-  "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
-   operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
-   operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
-   operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
-   operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
-   operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
-
-(define_expand "xorhi3"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-                   (xor:HI (match_operand:HI 1 "src_operand" "")
-                           (match_operand:HI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "legitimize_operands (AND, operands, HImode);")
-
-
-(define_insn "*xorhi3_clobber"
-  [(set (match_operand:HI 0 "reg_operand" "=d,?d,d")
-        (xor:HI (match_operand:HI 1 "src_operand" "%rR,rS<>,0")
-                (match_operand:HI 2 "src_operand" "R,rS<>,rm")))
-   (clobber (reg:CC 21))]
-  "valid_operands (XOR, operands, HImode)"
-  "#"
-  [(set_attr "type" "multi,multi,multi")])
-
-(define_split
- [(set (match_operand:HI 0 "reg_operand" "")
-       (xor:HI (match_operand:HI 1 "src_operand" "")
-               (match_operand:HI 2 "src_operand" "")))
-  (clobber (reg:CC 21))]
- "reload_completed"
-  [(parallel [(set (match_dup 3) (xor:QI (match_dup 4) (match_dup 5)))
-              (clobber (reg:CC 21))])
-   (parallel [(set (match_dup 6) (xor:QI (match_dup 7) (match_dup 8)))
-              (clobber (reg:CC 21))])]
-  "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
-   operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
-   operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
-   operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
-   operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
-   operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
-
-; This should do all the dirty work with define_split
-(define_expand "ashlhi3"
- [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-             (ashift:HI (match_operand:HI 1 "src_operand" "")
-                        (match_operand:QI 2 "src_operand" "")))
-             (clobber (reg:CC 21))])]
- ""
- "if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32)
-    {
-       rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
-       rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
-       rtx op1lo = operand_subword (operands[1], 0, 0, HImode);
-       rtx count = GEN_INT ((INTVAL (operands[2]) - 32));
-
-       if (INTVAL (count))
-         emit_insn (gen_ashlqi3 (op0hi, op1lo, count));
-       else
-         emit_insn (gen_movqi (op0hi, op1lo));
-       emit_insn (gen_movqi (op0lo, const0_rtx));
-       DONE;
-    }
-    emit_insn (gen_ashlhi3_reg (operands[0], operands[1], operands[2]));
-    DONE;")
-
-; %0.lo = %1.lo << %2
-; %0.hi = (%1.hi << %2 ) | (%1.lo >> (32 - %2))
-; This algorithm should work for shift counts greater than 32
-(define_expand "ashlhi3_reg" 
- [(use (match_operand:HI 1 "src_operand" ""))
-  (use (match_operand:HI 0 "reg_operand" ""))
-  /* If the shift count is greater than 32 this will give zero.  */
-  (parallel [(set (match_dup 7)
-                  (ashift:QI (match_dup 3)
-                             (match_operand:QI 2 "reg_operand" "")))
-             (clobber (reg:CC 21))])
-  /* If the shift count is greater than 32 this will give zero.  */
-  (parallel [(set (match_dup 8)
-                  (ashift:QI (match_dup 4) (match_dup 2)))
-             (clobber (reg:CC 21))])
-  (parallel [(set (match_dup 10)
-                  (plus:QI (match_dup 2) (const_int -32)))
-             (clobber (reg:CC_NOOV 21))])
-  /* If the shift count is greater than 32 this will do a left shift.  */
-  (parallel [(set (match_dup 9)
-                  (lshiftrt:QI (match_dup 3) (neg:QI (match_dup 10))))
-             (clobber (reg:CC 21))])
-  (set (match_dup 5) (match_dup 7))
-  (parallel [(set (match_dup 6)
-                  (ior:QI (match_dup 8) (match_dup 9)))
-             (clobber (reg:CC 21))])]
- ""
- " 
-  operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
-  operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
-  operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
-  operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
-  operands[7] = gen_reg_rtx (QImode); /* lo << count */
-  operands[8] = gen_reg_rtx (QImode); /* hi << count */
-  operands[9] = gen_reg_rtx (QImode); /* lo >> (32 - count) */
-  operands[10] = gen_reg_rtx (QImode); /* 32 - count */
- ")
-
-; This should do all the dirty work with define_split
-(define_expand "lshrhi3"
- [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-             (lshiftrt:HI (match_operand:HI 1 "src_operand" "")
-                          (match_operand:QI 2 "src_operand" "")))
-             (clobber (reg:CC 21))])]
- ""
- "if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32)
-    {
-       rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
-       rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
-       rtx op1hi = operand_subword (operands[1], 1, 0, HImode);
-       rtx count = GEN_INT ((INTVAL (operands[2]) - 32));
-
-       if (INTVAL (count))
-         emit_insn (gen_lshrqi3 (op0lo, op1hi, count));
-       else
-         emit_insn (gen_movqi (op0lo, op1hi));
-       emit_insn (gen_movqi (op0hi, const0_rtx));
-       DONE;
-    }
-    emit_insn (gen_lshrhi3_reg (operands[0], operands[1], operands[2]));
-    DONE;")
-
-; %0.hi = %1.hi >> %2
-; %0.lo = (%1.lo >> %2 ) | (%1.hi << (32 - %2))
-; This algorithm should work for shift counts greater than 32
-(define_expand "lshrhi3_reg" 
- [(use (match_operand:HI 1 "src_operand" ""))
-  (use (match_operand:HI 0 "reg_operand" ""))
-  (parallel [(set (match_dup 11)
-                  (neg:QI (match_operand:QI 2 "reg_operand" "")))
-             (clobber (reg:CC_NOOV 21))])
-  /* If the shift count is greater than 32 this will give zero.  */
-  (parallel [(set (match_dup 7)
-                  (lshiftrt:QI (match_dup 3)
-                               (neg:QI (match_dup 11))))
-             (clobber (reg:CC 21))])
-  /* If the shift count is greater than 32 this will give zero.  */
-  (parallel [(set (match_dup 8)
-                  (lshiftrt:QI (match_dup 4) 
-                               (neg:QI (match_dup 11))))
-             (clobber (reg:CC 21))])
-  (parallel [(set (match_dup 10)
-                  (plus:QI (match_dup 11) (const_int 32)))
-             (clobber (reg:CC_NOOV 21))])
-  /* If the shift count is greater than 32 this will do an arithmetic
-     right shift.  However, we need a logical right shift.  */
-  (parallel [(set (match_dup 9)
-                  (ashift:QI (match_dup 4) (unspec [(match_dup 10)] 3)))
-             (clobber (reg:CC 21))])
-  (set (match_dup 6) (match_dup 8))
-  (parallel [(set (match_dup 5)
-                  (ior:QI (match_dup 7) (match_dup 9)))
-             (clobber (reg:CC 21))])]
- ""
- " 
-  operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
-  operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
-  operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
-  operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
-  operands[7] = gen_reg_rtx (QImode); /* lo >> count */
-  operands[8] = gen_reg_rtx (QImode); /* hi >> count */
-  operands[9] = gen_reg_rtx (QImode); /* hi << (32 - count) */
-  operands[10] = gen_reg_rtx (QImode); /* 32 - count */
-  operands[11] = gen_reg_rtx (QImode); /* -count */
- ")
-
-; This should do all the dirty work with define_split
-(define_expand "ashrhi3"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-              (ashiftrt:HI (match_operand:HI 1 "src_operand" "")
-                           (match_operand:QI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
- ""
- "if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32)
-    {
-       rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
-       rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
-       rtx op1hi = operand_subword (operands[1], 1, 0, HImode);
-       rtx count = GEN_INT ((INTVAL (operands[2]) - 32));
-
-       if (INTVAL (count))
-         emit_insn (gen_ashrqi3 (op0lo, op1hi, count));
-       else
-         emit_insn (gen_movqi (op0lo, op1hi));
-       emit_insn (gen_ashrqi3 (op0hi, op1hi, GEN_INT (31)));
-       DONE;
-    }
-    emit_insn (gen_ashrhi3_reg (operands[0], operands[1], operands[2]));
-    DONE;")
-
-; %0.hi = %1.hi >> %2
-; %0.lo = (%1.lo >> %2 ) | (%1.hi << (32 - %2))
-; This algorithm should work for shift counts greater than 32
-(define_expand "ashrhi3_reg" 
- [(use (match_operand:HI 1 "src_operand" ""))
-  (use (match_operand:HI 0 "reg_operand" ""))
-  (parallel [(set (match_dup 11)
-                  (neg:QI (match_operand:QI 2 "reg_operand" "")))
-             (clobber (reg:CC_NOOV 21))])
-  /* If the shift count is greater than 32 this will give zero.  */
-  (parallel [(set (match_dup 7)
-                  (lshiftrt:QI (match_dup 3)
-                               (neg:QI (match_dup 11))))
-             (clobber (reg:CC 21))])
-  /* If the shift count is greater than 32 this will give zero.  */
-  (parallel [(set (match_dup 8)
-                  (ashiftrt:QI (match_dup 4) 
-                               (neg:QI (match_dup 11))))
-             (clobber (reg:CC 21))])
-  (parallel [(set (match_dup 10)
-                  (plus:QI (match_dup 11) (const_int 32)))
-             (clobber (reg:CC_NOOV 21))])
-  /* If the shift count is greater than 32 this will do an arithmetic
-     right shift.  */
-  (parallel [(set (match_dup 9)
-                  (ashift:QI (match_dup 4) (match_dup 10)))
-             (clobber (reg:CC 21))])
-  (set (match_dup 6) (match_dup 8))
-  (parallel [(set (match_dup 5)
-                  (ior:QI (match_dup 7) (match_dup 9)))
-             (clobber (reg:CC 21))])]
- ""
- " 
-  operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
-  operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
-  operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
-  operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
-  operands[7] = gen_reg_rtx (QImode); /* lo >> count */
-  operands[8] = gen_reg_rtx (QImode); /* hi >> count */
-  operands[9] = gen_reg_rtx (QImode); /* hi << (32 - count) */
-  operands[10] = gen_reg_rtx (QImode); /* 32 - count */
-  operands[11] = gen_reg_rtx (QImode); /* -count */
- ")
-
-(define_expand "cmphi"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:HI 0 "src_operand" "")
-                    (match_operand:HI 1 "src_operand" "")))]
-  ""
-  "legitimize_operands (COMPARE, operands, HImode);
-   c4x_compare_op0 = operands[0];
-   c4x_compare_op1 = operands[1];
-   DONE;")
-
-; This works only before reload because we need 2 extra registers.
-; Use unspec to avoid recursive split.
-(define_split
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:HI 0 "src_operand" "")
-                    (match_operand:HI 1 "src_operand" "")))]
-  "! reload_completed"
-  [(parallel [(set (reg:CC 21)
-                   (unspec [(compare:CC (match_dup 0)
-                                        (match_dup 1))] 4))
-              (clobber (match_scratch:QI 2 ""))
-	      (clobber (match_scratch:QI 3 ""))])]
-  "")
-
-(define_split
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (match_operand:HI 0 "src_operand" "")
-                         (match_operand:HI 1 "src_operand" "")))]
-  "! reload_completed"
-  [(parallel [(set (reg:CC_NOOV 21)
-                   (unspec [(compare:CC_NOOV (match_dup 0)
-                                             (match_dup 1))] 4))
-              (clobber (match_scratch:QI 2 ""))
-	      (clobber (match_scratch:QI 3 ""))])]
-  "")
-
-; This is normally not used. The define splits above are used first.
-(define_insn "*cmphi"
-  [(set (reg:CC 21)
-        (compare:CC (match_operand:HI 0 "src_operand" "rR,rS<>")
-                    (match_operand:HI 1 "src_operand" "R,rS<>")))]
-  "valid_operands (COMPARE, operands, HImode)"
-  "*
-   {
-     int use_ir1 = (reg_operand (operands[0], HImode)
-	            && REG_P (operands[0])
-		    && REGNO (operands[0]) == IR1_REGNO)
-		    || (reg_operand (operands[1], HImode)
-		        && REG_P (operands[1])
-		        && REGNO (operands[1]) == IR1_REGNO);
-
-     if (use_ir1)
-       output_asm_insn (\"push\\tir1\", operands);
-     else
-       output_asm_insn (\"push\\tbk\", operands);
-     output_asm_insn (\"push\\tr0\", operands);
-     output_asm_insn (\"subi3\\t%1,%0,r0\", operands);
-     if (use_ir1)
-       {
-         output_asm_insn (\"ldiu\\tst,ir1\", operands);
-         output_asm_insn (\"or\\t07bh,ir1\", operands);
-       }
-     else
-       {
-         output_asm_insn (\"ldiu\\tst,bk\", operands);
-         output_asm_insn (\"or\\t07bh,bk\", operands);
-       }
-     output_asm_insn (\"subb3\\t%O1,%O0,r0\", operands);
-     if (use_ir1)
-       output_asm_insn (\"and3\\tir1,st,ir1\", operands);
-     else
-       output_asm_insn (\"and3\\tbk,st,bk\", operands);
-     output_asm_insn (\"pop\\tr0\", operands);
-     if (use_ir1)
-       {
-         output_asm_insn (\"ldiu\\tir1,st\", operands);
-         output_asm_insn (\"pop\\tir1\", operands);
-       }
-     else
-       {
-         output_asm_insn (\"ldiu\\tbk,st\", operands);
-         output_asm_insn (\"pop\\tbk\", operands);
-       }
-     return \"\";
-   }"
-  [(set_attr "type" "multi")])
- 
-(define_insn "*cmphi_noov"
-  [(set (reg:CC_NOOV 21)
-        (compare:CC_NOOV (match_operand:HI 0 "src_operand" "rR,rS<>")
-                    (match_operand:HI 1 "src_operand" "R,rS<>")))]
-  "valid_operands (COMPARE, operands, HImode)"
-  "*
-   {
-     int use_ir1 = (reg_operand (operands[0], HImode)
-	            && REG_P (operands[0])
-		    && REGNO (operands[0]) == IR1_REGNO)
-		    || (reg_operand (operands[1], HImode)
-		        && REG_P (operands[1])
-		        && REGNO (operands[1]) == IR1_REGNO);
-
-     if (use_ir1)
-       output_asm_insn (\"push\\tir1\", operands);
-     else
-       output_asm_insn (\"push\\tbk\", operands);
-     output_asm_insn (\"push\\tr0\", operands);
-     output_asm_insn (\"subi3\\t%1,%0,r0\", operands);
-     if (use_ir1)
-       {
-         output_asm_insn (\"ldiu\\tst,ir1\", operands);
-         output_asm_insn (\"or\\t07bh,ir1\", operands);
-       }
-     else
-       {
-         output_asm_insn (\"ldiu\\tst,bk\", operands);
-         output_asm_insn (\"or\\t07bh,bk\", operands);
-       }
-     output_asm_insn (\"subb3\\t%O1,%O0,r0\", operands);
-     if (use_ir1)
-       output_asm_insn (\"and3\\tir1,st,ir1\", operands);
-     else
-       output_asm_insn (\"and3\\tbk,st,bk\", operands);
-     output_asm_insn (\"pop\\tr0\", operands);
-     if (use_ir1)
-       {
-         output_asm_insn (\"ldiu\\tir1,st\", operands);
-         output_asm_insn (\"pop\\tir1\", operands);
-       }
-     else
-       {
-         output_asm_insn (\"ldiu\\tbk,st\", operands);
-         output_asm_insn (\"pop\\tbk\", operands);
-       }
-     return \"\";
-   }"
-  [(set_attr "type" "multi")])
-
- 
-(define_insn "cmphi_cc"
-  [(set (reg:CC 21)
-        (unspec [(compare:CC (match_operand:HI 0 "src_operand" "rR,rS<>")
-                             (match_operand:HI 1 "src_operand" "R,rS<>"))] 4))
-   (clobber (match_scratch:QI 2 "=&d,&d"))
-   (clobber (match_scratch:QI 3 "=&c,&c"))]
-  "valid_operands (COMPARE, operands, HImode)"
-  "*
-   output_asm_insn (\"subi3\\t%1,%0,%2\", operands);
-   output_asm_insn (\"ldiu\\tst,%3\", operands);
-   output_asm_insn (\"or\\t07bh,%3\", operands);
-   output_asm_insn (\"subb3\\t%O1,%O0,%2\", operands);
-   output_asm_insn (\"and\\t%3,st\", operands);
-   return \"\";"
-  [(set_attr "type" "multi")])
-
-(define_insn "cmphi_cc_noov"
-  [(set (reg:CC_NOOV 21)
-        (unspec [(compare:CC_NOOV (match_operand:HI 0 "src_operand" "rR,rS<>")
-                                  (match_operand:HI 1 "src_operand" "R,rS<>"))] 4))
-   (clobber (match_scratch:QI 2 "=&d,&d"))
-   (clobber (match_scratch:QI 3 "=&c,&c"))]
-  "valid_operands (COMPARE, operands, HImode)"
-  "*
-   output_asm_insn (\"subi3\\t%1,%0,%2\", operands);
-   output_asm_insn (\"ldiu\\tst,%3\", operands);
-   output_asm_insn (\"or\\t07bh,%3\", operands);
-   output_asm_insn (\"subb3\\t%O1,%O0,%2\", operands);
-   output_asm_insn (\"and\\t%3,st\", operands);
-   return \"\";"
-  [(set_attr "type" "multi")])
-
-(define_expand "mulhi3"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-                   (mult:HI (match_operand:HI 1 "src_operand" "")
-                            (match_operand:HI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall3 (MULHI3_LIBCALL, MULT, HImode, operands);
-   DONE;")
-
-(define_expand "udivhi3"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-                   (udiv:HI (match_operand:HI 1 "src_operand" "")
-                            (match_operand:HI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall3 (UDIVHI3_LIBCALL, UDIV, HImode, operands);
-   DONE;")
-
-(define_expand "divhi3"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-                   (div:HI (match_operand:HI 1 "src_operand" "")
-                            (match_operand:HI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall3 (DIVHI3_LIBCALL, DIV, HImode, operands);
-   DONE;")
-
-(define_expand "umodhi3"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-                   (umod:HI (match_operand:HI 1 "src_operand" "")
-                            (match_operand:HI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall3 (UMODHI3_LIBCALL, UMOD, HImode, operands);
-   DONE;")
-
-(define_expand "modhi3"
-  [(parallel [(set (match_operand:HI 0 "reg_operand" "")
-                   (mod:HI (match_operand:HI 1 "src_operand" "")
-                            (match_operand:HI 2 "src_operand" "")))
-              (clobber (reg:CC 21))])]
-  ""
-  "c4x_emit_libcall3 (MODHI3_LIBCALL, MOD, HImode, operands);
-   DONE;")
-
-;
-; PEEPHOLES
-;
-
-; dbCC peepholes
-;
-; Turns
-;   loop:
-;           [ ... ]
-;           bCC label           ; abnormal loop termination
-;           dbu aN, loop        ; normal loop termination
-;
-; Into
-;   loop:
-;           [ ... ]
-;           dbCC aN, loop
-;           bCC label
-;
-; Which moves the bCC condition outside the inner loop for free.
-;
-(define_peephole
-  [(set (pc) (if_then_else (match_operator 3 "comparison_operator"
-                           [(reg:CC 21) (const_int 0)])
-                           (label_ref (match_operand 2 "" ""))
-                           (pc)))
-   (parallel
-    [(set (pc)
-          (if_then_else
-            (ge (plus:QI (match_operand:QI 4 "addr_reg_operand" "0")
-                         (const_int -1))
-                (const_int 0))
-            (label_ref (match_operand 1 "" ""))
-            (pc)))
-     (set (match_operand:QI 0 "addr_reg_operand" "+a")
-          (plus:QI (match_dup 0)
-                   (const_int -1)))
-     (clobber (reg:CC_NOOV 21))])]
-  "! c4x_label_conflict (insn, operands[2], operands[1])"
-  "db%I3\\t%0,%l1\\n\\tb%3\\t%l2"
-  [(set_attr "type" "multi")])
-
-(define_peephole
-  [(set (pc) (if_then_else (match_operator 3 "comparison_operator"
-                           [(reg:CC 21) (const_int 0)])
-                           (label_ref (match_operand 2 "" ""))
-                           (pc)))
-   (parallel
-    [(set (pc)
-          (if_then_else
-            (ne (match_operand:QI 4 "addr_reg_operand" "0")
-                (const_int 0))
-            (label_ref (match_operand 1 "" ""))
-            (pc)))
-     (set (match_operand:QI 0 "addr_reg_operand" "+a")
-          (plus:QI (match_dup 0)
-                   (const_int -1)))
-     (clobber (reg:CC_NOOV 21))])]
-  "! c4x_label_conflict (insn, operands[2], operands[1])"
-  "db%I3\\t%0,%l1\\n\\tb%3\\t%l2"
-  [(set_attr "type" "multi")])
-
-;
-; Peepholes to convert 'call label; rets' into jump label
-;
-(define_peephole
-  [(parallel [(call (match_operand:QI 0 "call_operand" "T,!o")
-                    (match_operand:QI 1 "general_operand" ""))
-              (clobber (reg:QI 31))])
-   (return)]
-  "c4x_null_epilogue_p ()"
-  "@
-   br%#\\t%C0
-   bu%#\\t%R0"
-  [(set_attr "type" "jump,jump")])
-
-(define_peephole
-  [(parallel [(set (match_operand 0 "" "")
-                   (call (match_operand:QI 1 "call_operand" "T,!o")
-                         (match_operand:QI 2 "general_operand" "")))
-              (clobber (reg:QI 31))])
-   (return)]
-  "c4x_null_epilogue_p ()"
-  "@
-   br%#\\t%C1
-   bu%#\\t%R1"
-  [(set_attr "type" "jump,jump")])
-
-;
-; Peepholes for parallel instructions
-;
-(define_peephole
- [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-       (match_operand:QI 1 "par_ind_operand" ""))
-  (set (match_operand:QI 2 "ext_low_reg_operand" "")
-       (match_operand:QI 3 "par_ind_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[2])) 
-  && ! c4x_address_conflict (operands[1], operands[3], 0, 0)"
- "ldi1\\t%1,%0\\n||\\tldi2\\t%3,%2")
-
-; load occurs before store if 1 and 2 point to same address
-(define_peephole
- [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-       (match_operand:QI 1 "par_ind_operand" ""))
-  (set (match_operand:QI 2 "par_ind_operand" "")
-       (match_operand:QI 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))
-  && ! c4x_address_conflict (operands[1], operands[2], 0, 1)"
- "ldi\\t%1,%0\\n||\\tsti\\t%3,%2")
-
-; load occurs before store if 0 and 3 point to same address
-(define_peephole
- [(set (match_operand:QI 0 "par_ind_operand" "")
-       (match_operand:QI 1 "ext_low_reg_operand" ""))
-  (set (match_operand:QI 2 "ext_low_reg_operand" "")
-       (match_operand:QI 3 "par_ind_operand" ""))]
- "(REGNO (operands[1]) != REGNO (operands[2]))
-  && ! c4x_address_conflict (operands[0], operands[3], 1, 0)"
- "ldi\\t%3,%2\\n||\\tsti\\t%1,%0")
-
-(define_peephole
- [(set (match_operand:QI 0 "par_ind_operand" "")
-       (match_operand:QI 1 "ext_low_reg_operand" ""))
-  (set (match_operand:QI 2 "par_ind_operand" "")
-       (match_operand:QI 3 "ext_low_reg_operand" ""))]
- "! c4x_address_conflict (operands[0], operands[2], 1, 1)"
- "sti\\t%1,%0\\n||\\tsti\\t%3,%2")
-
-; This peephole should be unnecessary with my patches to flow.c
-; for better autoincrement detection
-(define_peephole
- [(set (match_operand:QF 0 "ext_low_reg_operand" "")
-       (mem:QF (match_operand:QI 1 "addr_reg_operand" "")))
-  (set (match_operand:QF 2 "ext_low_reg_operand" "")
-       (mem:QF (plus:QI (match_dup 1) (const_int 1))))
-  (parallel [(set (match_dup 1) (plus:QI (match_dup 1) (const_int 2)))
-             (clobber (reg:CC_NOOV 21))])]
- ""
- "ldf\\t*%1++,%0\\n\\tldf\\t*%1++,%2")
-
-(define_peephole
- [(set (match_operand:QF 0 "ext_low_reg_operand" "")
-       (match_operand:QF 1 "par_ind_operand" ""))
-  (set (match_operand:QF 2 "ext_low_reg_operand" "")
-       (match_operand:QF 3 "par_ind_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[2]))
-  && ! c4x_address_conflict (operands[1], operands[3], 0, 1)"
- "ldf1\\t%1,%0\\n||\\tldf2\\t%3,%2")
-
-; This peephole should be unnecessary with my patches to flow.c
-; for better autoincrement detection
-(define_peephole
- [(set (mem:QF (match_operand:QI 0 "addr_reg_operand" ""))
-       (match_operand:QF 1 "ext_low_reg_operand" ""))
-  (set (mem:QF (plus:QI (match_dup 0) (const_int 1)))
-       (match_operand:QF 2 "ext_low_reg_operand" ""))
-  (parallel [(set (match_dup 0) (plus:QI (match_dup 0) (const_int 2)))
-             (clobber (reg:CC_NOOV 21))])]
- ""
- "stf\\t%1,*%0++\\n\\tstf\\t%2,*%0++")
-
-(define_peephole
- [(set (match_operand:QF 0 "ext_low_reg_operand" "")
-       (match_operand:QF 1 "par_ind_operand" ""))
-  (set (match_operand:QF 2 "par_ind_operand" "")
-       (match_operand:QF 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))"
- "ldf\\t%1,%0\\n||\\tstf\\t%3,%2")
-
-(define_peephole
- [(set (match_operand:QF 0 "par_ind_operand" "")
-       (match_operand:QF 1 "ext_low_reg_operand" ""))
-  (set (match_operand:QF 2 "ext_low_reg_operand" "")
-       (match_operand:QF 3 "par_ind_operand" ""))]
- "! c4x_address_conflict (operands[0], operands[3], 1, 1)"
- "ldf\\t%3,%2\\n||\\tstf\\t%1,%0")
-
-(define_peephole
- [(set (match_operand:QF 0 "par_ind_operand" "")
-       (match_operand:QF 1 "ext_low_reg_operand" ""))
-  (set (match_operand:QF 2 "par_ind_operand" "")
-       (match_operand:QF 3 "ext_low_reg_operand" ""))]
- "! c4x_address_conflict (operands[0], operands[2], 1, 1)"
- "stf1\\t%1,%0\\n||\\tstf2\\t%3,%2")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (abs:QF (match_operand:QF 1 "par_ind_operand" ""))
-				   (match_operand:QF 2 "fp_zero_operand" "")))
-	     (set (match_operand:QF 0 "ext_low_reg_operand" "")
-		  (abs:QF (match_dup 1)))])
-  (set (match_operand:QF 3 "par_ind_operand" "")
-       (match_operand:QF 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "absf\\t%1,%0\\n||\\tstf\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
-                  (abs:QF (match_operand:QF 1 "par_ind_operand" "")))
-             (clobber (reg:CC_NOOV 21))])
-  (set (match_operand:QF 2 "par_ind_operand" "")
-       (match_operand:QF 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))"
- "absf\\t%1,%0\\n||\\tstf\\t%3,%2")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (abs:QI (match_operand:QI 1 "par_ind_operand" ""))
-				   (const_int 0)))
-	     (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (abs:QI (match_dup 1)))])
-  (set (match_operand:QI 2 "par_ind_operand" "")
-       (match_operand:QI 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))"
- "absi\\t%1,%0\\n||\\tsti\\t%3,%2")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (abs:QI (match_operand:QI 1 "par_ind_operand" "")))
-             (clobber (reg:CC_NOOV 21))])
-  (set (match_operand:QI 2 "par_ind_operand" "")
-       (match_operand:QI 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))"
- "absi\\t%1,%0\\n||\\tsti\\t%3,%2")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (plus:QI (match_operand:QI 1 "ext_low_reg_operand" "")
-                                            (match_operand:QI 2 "par_ind_operand" ""))
-				   (const_int 0)))
-             (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (plus:QI (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "addi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (plus:QI (match_operand:QI 1 "par_ind_operand" "")
-                                            (match_operand:QI 2 "ext_low_reg_operand" ""))
-				   (const_int 0)))
-             (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (plus:QI (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "addi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (plus:QI (match_operand:QI 1 "ext_low_reg_operand" "")
-                           (match_operand:QI 2 "par_ind_operand" "")))
-             (clobber (reg:CC_NOOV 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "addi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (plus:QI (match_operand:QI 1 "par_ind_operand" "")
-                           (match_operand:QI 2 "ext_low_reg_operand" "")))
-             (clobber (reg:CC_NOOV 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "addi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (plus:QF (match_operand:QF 1 "ext_low_reg_operand" "")
-                           		    (match_operand:QF 2 "par_ind_operand" ""))
-				   (match_operand:QF 3 "fp_zero_operand" "")))
-	     (set (match_operand:QF 0 "ext_low_reg_operand" "")
-                  (plus:QF (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QF 4 "par_ind_operand" "")
-       (match_operand:QF 5 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[5]))"
- "addf3\\t%2,%1,%0\\n||\\tstf\\t%5,%4")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (plus:QF (match_operand:QF 1 "par_ind_operand" "")
-                           		    (match_operand:QF 2 "ext_low_reg_operand" ""))
-				   (match_operand:QF 3 "fp_zero_operand" "")))
-	     (set (match_operand:QF 0 "ext_low_reg_operand" "")
-                  (plus:QF (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QF 4 "par_ind_operand" "")
-       (match_operand:QF 5 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[5]))"
- "addf3\\t%2,%1,%0\\n||\\tstf\\t%5,%4")
-
-(define_peephole
- [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
-                  (plus:QF (match_operand:QF 1 "ext_low_reg_operand" "")
-                           (match_operand:QF 2 "par_ind_operand" "")))
-             (clobber (reg:CC_NOOV 21))])
-  (set (match_operand:QF 3 "par_ind_operand" "")
-       (match_operand:QF 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "addf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
-                  (plus:QF (match_operand:QF 1 "par_ind_operand" "")
-                           (match_operand:QF 2 "ext_low_reg_operand" "")))
-             (clobber (reg:CC_NOOV 21))])
-  (set (match_operand:QF 3 "par_ind_operand" "")
-       (match_operand:QF 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "addf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC 21)
-                  (compare:CC (and:QI (match_operand:QI 1 "ext_low_reg_operand" "")
-                                      (match_operand:QI 2 "par_ind_operand" ""))
-			      (const_int 0)))
-	     (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (and:QI (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "and3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC 21)
-                  (compare:CC (and:QI (match_operand:QI 1 "par_ind_operand" "")
-                                      (match_operand:QI 2 "ext_low_reg_operand" ""))
-			      (const_int 0)))
-	     (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (and:QI (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "and3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (and:QI (match_operand:QI 1 "ext_low_reg_operand" "")
-                          (match_operand:QI 2 "par_ind_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "and3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (and:QI (match_operand:QI 1 "par_ind_operand" "")
-                          (match_operand:QI 2 "ext_low_reg_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "and3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (ashift:QI (match_operand:QI 1 "par_ind_operand" "")
-                             (match_operand:QI 2 "ext_low_reg_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (ashiftrt:QI (match_operand:QI 1 "par_ind_operand" "")
-                               (neg:QI (match_operand:QI 2 "ext_low_reg_operand" ""))))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC 21)
-                  (compare:CC (fix:QI (match_operand:QF 1 "par_ind_operand" ""))
-			      (const_int 0)))
-             (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (fix:QI (match_dup 1)))])
-  (set (match_operand:QI 2 "par_ind_operand" "")
-       (match_operand:QI 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))"
- "fix\\t%1,%0\\n||\\tsti\\t%3,%2")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (fix:QI (match_operand:QF 1 "par_ind_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QI 2 "par_ind_operand" "")
-       (match_operand:QI 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))"
- "fix\\t%1,%0\\n||\\tsti\\t%3,%2")
-
-(define_peephole
- [(parallel [(set (reg:CC 21)
-                  (compare:CC (float:QF (match_operand:QI 1 "par_ind_operand" ""))
-                              (match_operand:QF 2 "fp_zero_operand" "")))
-	     (set (match_operand:QF 0 "ext_low_reg_operand" "")
-		  (float:QF (match_dup 1)))])
-  (set (match_operand:QF 3 "par_ind_operand" "")
-       (match_operand:QF 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "float\\t%1,%0\\n||\\tstf\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
-                  (float:QF (match_operand:QI 1 "par_ind_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QF 2 "par_ind_operand" "")
-       (match_operand:QF 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))"
- "float\\t%1,%0\\n||\\tstf\\t%3,%2")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (mult:QI (match_operand:QI 1 "ext_low_reg_operand" "")
-                                            (match_operand:QI 2 "par_ind_operand" ""))
-				   (const_int 0)))
-	     (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (mult:QI (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "mpyi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (mult:QI (match_operand:QI 1 "par_ind_operand" "")
-                                            (match_operand:QI 2 "ext_low_reg_operand" ""))
-				   (const_int 0)))
-	     (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (mult:QI (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "mpyi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (mult:QI (match_operand:QI 1 "ext_low_reg_operand" "")
-                           (match_operand:QI 2 "par_ind_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "mpyi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (mult:QI (match_operand:QI 1 "par_ind_operand" "")
-                           (match_operand:QI 2 "ext_low_reg_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "mpyi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (mult:QF (match_operand:QF 1 "ext_low_reg_operand" "")
-                                            (match_operand:QF 2 "par_ind_operand" ""))
-			           (match_operand:QF 3 "fp_zero_operand" "")))
-             (set (match_operand:QF 0 "ext_low_reg_operand" "")
-		  (mult:QF (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QF 4 "par_ind_operand" "")
-       (match_operand:QF 5 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[5]))"
- "mpyf3\\t%2,%1,%0\\n||\\tstf\\t%5,%4")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (mult:QF (match_operand:QF 1 "par_ind_operand" "")
-                                            (match_operand:QF 2 "ext_low_reg_operand" ""))
-			           (match_operand:QF 3 "fp_zero_operand" "")))
-             (set (match_operand:QF 0 "ext_low_reg_operand" "")
-		  (mult:QF (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QF 4 "par_ind_operand" "")
-       (match_operand:QF 5 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[5]))"
- "mpyf3\\t%2,%1,%0\\n||\\tstf\\t%5,%4")
-
-(define_peephole
- [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
-                  (mult:QF (match_operand:QF 1 "ext_low_reg_operand" "")
-                           (match_operand:QF 2 "par_ind_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QF 3 "par_ind_operand" "")
-       (match_operand:QF 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "mpyf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
-                  (mult:QF (match_operand:QF 1 "par_ind_operand" "")
-                           (match_operand:QF 2 "ext_low_reg_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QF 3 "par_ind_operand" "")
-       (match_operand:QF 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "mpyf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (neg:QF (match_operand:QF 1 "par_ind_operand" ""))
-				   (match_operand:QF 2 "fp_zero_operand" "")))
-	     (set (match_operand:QF 0 "ext_low_reg_operand" "")
-                  (neg:QF (match_dup 1)))])
-  (set (match_operand:QF 3 "par_ind_operand" "")
-       (match_operand:QF 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "negf\\t%1,%0\\n||\\tstf\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
-                  (neg:QF (match_operand:QF 1 "par_ind_operand" "")))
-             (clobber (reg:CC_NOOV 21))])
-  (set (match_operand:QF 2 "par_ind_operand" "")
-       (match_operand:QF 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))"
- "negf\\t%1,%0\\n||\\tstf\\t%3,%2")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (neg:QI (match_operand:QI 1 "par_ind_operand" ""))
-             			   (const_int 0)))
-	     (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (neg:QI (match_dup 1)))])
-  (set (match_operand:QI 2 "par_ind_operand" "")
-       (match_operand:QI 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))"
- "negi\\t%1,%0\\n||\\tsti\\t%3,%2")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (neg:QI (match_operand:QI 1 "par_ind_operand" "")))
-             (clobber (reg:CC_NOOV 21))])
-  (set (match_operand:QI 2 "par_ind_operand" "")
-       (match_operand:QI 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))"
- "negi\\t%1,%0\\n||\\tsti\\t%3,%2")
-
-(define_peephole
- [(parallel [(set (reg:CC 21)
-                  (compare:CC (not:QI (match_operand:QI 1 "par_ind_operand" ""))
-             		      (const_int 0)))
-	     (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (not:QI (match_dup 1)))])
-  (set (match_operand:QI 2 "par_ind_operand" "")
-       (match_operand:QI 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))"
- "not\\t%1,%0\\n||\\tsti\\t%3,%2")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (not:QI (match_operand:QI 1 "par_ind_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QI 2 "par_ind_operand" "")
-       (match_operand:QI 3 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[3]))"
- "not\\t%1,%0\\n||\\tsti\\t%3,%2")
-
-(define_peephole
- [(parallel [(set (reg:CC 21)
-                  (compare:CC (ior:QI (match_operand:QI 1 "ext_low_reg_operand" "")
-				      (match_operand:QI 2 "par_ind_operand" ""))
-			      (const_int 0)))
-	     (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (ior:QI (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "or3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC 21)
-                  (compare:CC (ior:QI (match_operand:QI 1 "par_ind_operand" "")
-				      (match_operand:QI 2 "ext_low_reg_operand" ""))
-			      (const_int 0)))
-	     (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (ior:QI (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "or3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (ior:QI (match_operand:QI 1 "ext_low_reg_operand" "")
-                          (match_operand:QI 2 "par_ind_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "or3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (ior:QI (match_operand:QI 1 "par_ind_operand" "")
-                          (match_operand:QI 2 "ext_low_reg_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "or3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-		  (compare:CC_NOOV (minus:QI (match_operand:QI 1 "ext_low_reg_operand" "")
-					     (match_operand:QI 2 "par_ind_operand" ""))
-				   (const_int 0)))
-	     (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (minus:QI (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "subi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (minus:QI (match_operand:QI 1 "ext_low_reg_operand" "")
-                            (match_operand:QI 2 "par_ind_operand" "")))
-             (clobber (reg:CC_NOOV 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "subi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC_NOOV 21)
-                  (compare:CC_NOOV (minus:QF (match_operand:QF 1 "ext_low_reg_operand" "")
-					     (match_operand:QF 2 "par_ind_operand" ""))
-				   (match_operand:QF 3 "fp_zero_operand" "")))
-	    (set (match_operand:QF 0 "ext_low_reg_operand" "")
-		 (minus:QF (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QF 4 "par_ind_operand" "")
-       (match_operand:QF 5 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[5]))"
- "subf3\\t%2,%1,%0\\n||\\tstf\\t%5,%4")
-
-(define_peephole
- [(parallel [(set (match_operand:QF 0 "ext_low_reg_operand" "")
-                  (minus:QF (match_operand:QF 1 "ext_low_reg_operand" "")
-                            (match_operand:QF 2 "par_ind_operand" "")))
-             (clobber (reg:CC_NOOV 21))])
-  (set (match_operand:QF 3 "par_ind_operand" "")
-       (match_operand:QF 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "subf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC 21)
-                  (compare:CC (xor:QI (match_operand:QI 1 "ext_low_reg_operand" "")
-                          	      (match_operand:QI 2 "par_ind_operand" ""))
-             		      (const_int 0)))
-	     (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (xor:QI (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (reg:CC 21)
-                  (compare:CC (xor:QI (match_operand:QI 1 "par_ind_operand" "")
-                          	      (match_operand:QI 2 "ext_low_reg_operand" ""))
-             		      (const_int 0)))
-	     (set (match_operand:QI 0 "ext_low_reg_operand" "")
-		  (xor:QI (match_dup 1) (match_dup 2)))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (xor:QI (match_operand:QI 1 "ext_low_reg_operand" "")
-                          (match_operand:QI 2 "par_ind_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-(define_peephole
- [(parallel [(set (match_operand:QI 0 "ext_low_reg_operand" "")
-                  (xor:QI (match_operand:QI 1 "par_ind_operand" "")
-                          (match_operand:QI 2 "ext_low_reg_operand" "")))
-             (clobber (reg:CC 21))])
-  (set (match_operand:QI 3 "par_ind_operand" "")
-       (match_operand:QI 4 "ext_low_reg_operand" ""))]
- "(REGNO (operands[0]) != REGNO (operands[4]))"
- "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3")
-
-
diff --git a/gcc/config/c4x/libgcc.S b/gcc/config/c4x/libgcc.S
deleted file mode 100755
index fb79cf8..0000000
--- a/gcc/config/c4x/libgcc.S
+++ /dev/null
@@ -1,1501 +0,0 @@
-/* libgcc1 routines for the Texas Instruments TMS320C[34]x
-   Copyright (C) 1997,98 Free Software Foundation, Inc.
-
- Contributed by Michael Hayes (m.hayes@elec.canterbury.cri.nz)
-            and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
-
-	
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with files
-   compiled with GCC to produce an executable, this does not cause
-   the resulting executable to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-	
-; These routines are called using the standard TI register argument
-; passing model.
-; The following registers do not have to be saved:
-; r0, r1, r2, r3, ar0, ar1, ar2, ir0, ir1, bk, rs, rc, re, (r9, r10, r11)
-;
-; Perform floating point divqf3
-;
-; This routine performs a reciprocal of the divisor using the method
-; described in the C30/C40 user manuals.  It then multiplies that
-; result by the dividend.
-; 
-; Let r be the reciprocal of the divisor v and let the ith estimate
-; of r be denoted by r[i].  An iterative approach can be used to
-; improve the estimate of r, given an initial estimate r[0], where
-;
-; r[i + 1] = r[i] * (2.0 - v * r[i])
-;
-; The normalised error e[i] at the ith iteration is
-;
-; e[i] = (r - r[i]) / r = (1 / v - r[i]) * v = (1 - v * r[i])
-;
-; Note that 
-;
-; e[i + 1]  = (1 - v * r[i + 1]) = 1 - 2 * v * r[i] + v^2 + (r[i])^2
-;           = (1 - v * r[i])^2 = (e[i])^2
-
-; r2 dividend, r3 divisor, r0 quotient
-; clobbers r1, ar1
-#ifdef L_divqf3
-	.text
-        .global ___divqf3
-___divqf3:
-
-#ifdef _TMS320C4x
-	.if .REGPARM == 0
-	lda	sp,ar0
-	ldf	*-ar0(2), r3
-	.endif
-
-	pop	ar1		; Pop return address
-
-; r0 = estimate of r, r1 = tmp, r2 = dividend, r3 = divisor
-        rcpf    r3, r0		; Compute initial estimate r[0]
-
-	mpyf3	r0, r3, r1	; r1 = r[0] * v
-	subrf	2.0, r1		; r1 = 2.0 - r[0] * v
-	mpyf	r1, r0		; r0 = r[0] * (2.0 - r[0] * v) = r[1]
-; End of 1st iteration (16 bits accuracy)
-
-	mpyf3	r0, r3, r1	; r1 = r[1] * v
-	subrf	2.0, r1		; r1 = 2.0 - r[1] * v
-
-	bud	ar1		; Delayed branch
-	mpyf	r1, r0		; r0 = r[1] * (2.0 - r[1] * v) = r[2]
-; End of 2nd iteration (32 bits accuracy)
-	.if .REGPARM == 0
-	mpyf	*-ar0(1), r0	; Multiply by the dividend
-	.else
-	mpyf	r2, r0		; Multiply by the dividend
-	.endif
-	rnd	r0
-	; Branch occurs here
-#else
-	.if .REGPARM == 0
-	ldiu	sp,ar0
-	ldf	*-ar0(2), r3
-	.endif
-
-	pop	ar1		; Pop return address
-
-; Initial estimate       r[0] = 1.0 * 2^(-e - 1)
-; where                  v = m * 2^e
-
-; r0 = estimate of r, r1 = tmp, r2 = dividend, r3 = divisor
-
-; Calculate initial estimate r[0]
-	pushf	r3
-	pop	r0
-	not	r0		; r0 = -e
-				; complement exponent = -e -1
-				; complement sign (side effect)
-				; complement mantissa (almost 3 bit accurate)
-	push	r0
-	popf	r0		; r0 = 1.0 * e^(-e - 1) + inverted mantissa
-	ldf	-1.0, r1	; undo complement sign bit
-	xor	r1, r0
-
-	mpyf3	r0, r3, r1	; r1 = r[0] * v
-	subrf	2.0, r1		; r1 = 2.0 - r[0] * v
-	mpyf	r1, r0		; r0 = r[0] * (2.0 - r[0] * v) = r[1]
-; End of 1st iteration
-
-	mpyf3	r0, r3, r1	; r1 = r[1] * v
-	subrf	2.0, r1		; r1 = 2.0 - r[1] * v
-	mpyf	r1, r0		; r0 = r[1] * (2.0 - r[1] * v) = r[2]
-; End of 2nd iteration
-
-	mpyf3	r0, r3, r1	; r1 = r[2] * v
-	subrf	2.0, r1		; r1 = 2.0 - r[2] * v
-	mpyf	r1, r0		; r0 = r[2] * (2.0 - r[2] * v) = r[3]
-; End of 3rd iteration
-
-	or	080h, r0	; add 1 lsb to result. needed when complemeting
-				; 1.0 / 2.0
-	rnd	r0
-
-; Use modified last iteration
-; r[4] = (r[3] * (1.0 - (v * r[3]))) + r[3]
-	mpyf3	r0, r3, r1	; r1 = r[3] * v
-	subrf	1.0, r1		; r1 = 1.0 - r[3] * v
-	mpyf	r0, r1		; r1 = r[3] * (1.0 - r[3] * v)
-
-	bud	ar1		; Delayed branch
-	addf	r1, r0		; r0 = r[3] * (1.0 - r[3] * v) + r[3] = r[4]
-	.if .REGPARM == 0
-	mpyf	*-ar0(1), r0	; Multiply by the dividend
-	.else
-	mpyf	r2, r0		; Multiply by the dividend
-	.endif
-	rnd	r0
-	; Branch occurs here
-#endif
-
-#endif
-;
-; Integer signed division
-;
-; ar2 dividend, r2 divisor, r0 quotient
-; clobbers r1, r3, ar0, ar1, ir0, ir1, rc, rs, re
-#ifdef L_divqi3
-	.text
-	.global ___divqi3
-	.ref	udivqi3n
-___divqi3:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldi	*-ar0(1), ar2
-	ldi	*-ar0(2), r2
-	.endif
-
-	xor3	ar2, r2, r3	; Get the sign
-	absi	ar2, r0
-	bvd	divq32
-	ldi	r0, ar2
-	absi	r2, r2
-	cmpi	ar2, r2		; Divisor > dividend?
-
-	pop	ir1
-	bhid	zero		; If so, return 0
-
-;
-; Normalize oeprands.  Use difference exponents as shift count
-; for divisor, and as repeat count for "subc"
-;
-	float	ar2, r1		; Normalize dividend
-	pushf	r1		; Get as integer
-	pop	ar0
-	lsh	-24, ar0	; Get exponent
-	
-	float	r2, r1		; Normalize divisor
-	pushf	r1		; Get as integer
-	pop	ir0
-	lsh	-24, ir0	; Get exponent
-
-	subi	ir0, ar0	; Get difference of exponents
-	lsh	ar0, r2		; Align divisor with dividend
-
-;
-; Do count + 1 subtracts and shifts
-;
-	rpts	ar0
-		subc	r2, ar2
-
-;
-; Mask off the lower count+1 bits of ar2
-;
-	subri	31, ar0		; Shift count is (32 - (ar0 + 1))
-	lsh	ar0, ar2	; Shift left
-	negi	ar0, ar0
-	lsh3	ar0, ar2, r0	; Shift right and put result in r0
-
-;
-; Check sign and negate result if necessary
-;
-	bud	ir1		; Delayed return
-	negi	r0, r1		; Negate result
-	ash	-31, r3		; Check sign
-	ldinz	r1, r0		; If set, use negative result
-	; Branch occurs here
-
-zero:	bud	ir1		; Delayed branch
-	ldi	0, r0
-	nop
-	nop
-	; Branch occurs here
-;
-; special case where ar2 = abs(ar2) = 0x80000000.  We handle this by
-; calling unsigned divide and negating the result if necessary.
-;
-divq32:
-	push	r3		; Save sign
-	call	udivqi3n
-	pop	r3
-	pop	ir1
-	bd	ir1
-	negi	r0, r1		; Negate result
-	ash	-31, r3		; Check sign
-	ldinz	r1, r0		; If set, use negative result
-	; Branch occurs here
-#endif
-;
-;
-; ar2 dividend, r2 divisor, r0 quotient, 
-; clobbers r1, r3, ar0, ar1, ir0, ir1, rc, rs, re
-#ifdef L_udivqi3
-	.text
-	.global ___udivqi3
-	.global udivqi3n
-___udivqi3:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldi	*-ar0(1), ar2
-	ldi	*-ar0(2), r2
-	.endif
-
-udivqi3n:
-	pop	ir1
-
-	cmpi	ar2, r2		; If divisor > dividend
-	bhi	qzero		; return zero
-	ldi	r2, ar1		; Store divisor in ar1
-
-	tstb	ar2, ar2	; Check top bit, jump if set to special handler
-	bld	div_32		; Delayed branch
-
-;
-; Get divisor exponent
-;
-	float	ar1, r1		; Normalize the divisor
-	pushf	r1		; Get into int register
-	pop	rc
-	; branch occurs here
-
-	bzd	qzero		; if (float) divisor zero, return zero
-
-	float	ar2, r1		; Normalize the dividend
-	pushf	r1		; Get into int register
-	pop	ar0
-	lsh	-24, ar0	; Get both the exponents
-	lsh	-24, rc
-
-	subi	rc, ar0		; Get the difference between the exponents
-	lsh	ar0, ar1	; Normalize the divisor with the dividend
-
-;
-; Do count_1 subtracts and shifts
-;
-	rpts	ar0
-		subc	ar1, ar2
-
-;
-; mask off the lower count+1 bits
-;
-	subri	31, ar0		; Shift count (31 - (ar0+1))
-	bud	ir1		; Delayed return
-	lsh3	ar0, ar2, r0
-	negi	ar0, ar0
-	lsh	ar0, r0
-	; Branch occurs here
-
-;
-; Handle a full 32-bit dividend
-;
-div_32:	tstb	ar1, ar1
-	bld	qone		; if divisor high bit is one, the result is one
-	lsh	-24, rc
-	subri	31, rc
-	lsh	rc, ar1		; Line up the divisor
-
-;
-; Now divisor and dividend are aligned.  Do first SUBC by hand, save
-; of the forst quotient digit.  Then, shift divisor right rather
-; than shifting dividend left.  This leaves a zero in the top bit of
-; the divident
-;
-	ldi	1, ar0		; Initizialize MSB of quotient
-	lsh	rc, ar0		; create a mask for MSBs
-	subi	1, ar0		; mask is (2 << count) - 1
-
-	subi3	ar1, ar2, r1
-	ldihs	r1, ar2
-	ldihs	1, r1
-	ldilo	0, r1
-	lsh	rc, r1
-
-	lsh	-1, ar1
-	subi	1, rc
-;
-; do the rest of the shifts and subtracts
-;
-	rpts	rc
-		subc	ar1, ar2
-
-	bud	ir1
-	and	ar0, ar2
-	or3	r1, ar2, r0
-	nop
-
-qone:
-	bud	ir1
-	ldi	1, r0
-	nop
-	nop
-
-qzero:
-	bud	ir1
-	ldi	0, r0
-	nop
-	nop
-#endif
-
-#ifdef L_umodqi3
-	.text
-	.global	___umodqi3
-	.global	umodqi3n
-___umodqi3:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldi	*-ar0(1), ar2
-	ldi	*-ar0(2), r2
-	.endif
-
-umodqi3n:
-	pop     ir1		; return address
-        cmpi    ar2, r2		; divisor > dividend ? 
-	bhi     uzero		;    if so, return dividend
-	ldi     r2, ar1		; load divisor
-;
-; If top bit of dividend is set, handle specially.
-;
-        tstb    ar2, ar2	; check top bit
-	bld     umod_32		; get divisor exponent, then jump.
-;
-; Get divisor exponent by converting to float.
-;
-	float   ar1, r1		; normalize divisor
-	pushf   r1		; push as float
-	pop     rc		; pop as int to get exponent
-        bzd     uzero		; if (float)divisor was zero, return
-;
-; 31 or less bits in dividend.  Get dividend exponent.
-;
-        float   ar2, r1		; normalize dividend
-	pushf   r1		; push as float
-	pop     ar0		; pop as int to get exponent
-;
-; Use difference in exponents as shift count to line up MSBs.
-;
-	lsh     -24, rc		; divisor exponent
-	lsh     -24, ar0	; dividend exponent
-	subi    rc, ar0		; difference
-        lsh     ar0, ar1	; shift divisor up
-; 
-; Do COUNT+1 subtract & shifts.
-;
-	rpts    ar0
-		subc    ar1, ar2  
-;
-;  Remainder is in upper 31-COUNT bits.
-;
-	bud     ir1		; delayed branch to return
-	addi    1, ar0		; shift count is COUNT+1
-	negi    ar0, ar0	; negate for right shift
-	lsh3    ar0, ar2, r0	; shift to get result
-	; Return occurs here
-
-;
-; The following code handles cases of a full 32-bit dividend.  Before
-; SUBC can be used, the top bit must be cleared (otherwise SUBC can
-; possibly shift a significant 1 out the top of the dividend).  This
-; is accomplished by first doing a normal subtraction, then proceeding
-; with SUBCs. 
-;
-umod_32:
-;
-; If the top bit of the divisor is set too, the remainder is simply
-; the difference between the dividend and divisor.  Otherwise, shift 
-; the divisor up to line up the MSBs.
-;
-	tstb    ar1, ar1	; check divisor
-	bld     uone		; if negative, remainder is diff
-
-	lsh     -24, rc		; divisor exponent
-	subri   31, rc		; shift count = 31 - exp
-	negi    rc, ar0		; used later as shift count
-	lsh     rc, ar1		; shift up to line up MSBs
-;
-; Now MSBs are aligned.  Do first SUBC by hand using a plain subtraction.
-; Then, shift divisor right rather than shifting dividend left.  This leaves
-; a 0 in the top bit of the dividend.
-;
-	subi3   ar1, ar2, r1	; subtract 
-	ldihs   r1, ar2		; if positive, replace dividend
-	subi    1, rc		; first iteration is done
-	lsh     -1, ar1		; shift divisor down
-; 
-; Do EXP subtract & shifts.
-;
-	rpts    rc  
-		subc    ar1, ar2   
-;
-;  Quotient is in EXP+1 LSBs; shift remainder (in MSBs) down.
-;
-	bud	ir1
-	lsh3    ar0, ar2, r0	; COUNT contains -(EXP+1)
-	nop
-	nop
-;
-;  Return (dividend - divisor).
-;
-uone:	bud	ir1
-	subi3   r2, ar2, r0  
-	nop
-	nop
-;
-;  Return dividend.
-;
-uzero:	bud	ir1
-	ldi     ar2, r0		; set status from result
-	nop
-	nop
-#endif
-
-#ifdef L_modqi3
-	.text
-	.global	___modqi3
-	.ref umodqi3n
-___modqi3:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldi	*-ar0(1), ar2
-	ldi	*-ar0(2), r2
-	.endif
-
-; 
-; Determine sign of result.  Get absolute value of operands.
-; 
-	ldi     ar2, ar0	; sign of result same as dividend
-	absi    ar2, r0		; make dividend positive
-	bvd     mod_32		; if still negative, escape
-	absi    r2, r1		; make divisor positive
-	ldi     r1, ar1		; save in ar1       
-        cmpi    r0, ar1		; divisor > dividend ? 
-
-        pop     ir1            ; return address
-	bhid    return 		;   if so, return dividend
-; 
-; Normalize operands.  Use difference in exponents as shift count
-; for divisor, and as repeat count for SUBC.
-;
-        float   r1, r1		; normalize divisor
-        pushf   r1		; push as float 
-	pop     rc		; pop as int
-        bzd     return		; if (float)divisor was zero, return
-
-        float   r0, r1		; normalize dividend
-        pushf   r1		; push as float
-        pop     r1		; pop as int 
-
-	lsh     -24, rc		; get divisor exponent
-	lsh     -24, r1		; get dividend exponent
-	subi    rc, r1		; get difference in exponents
-	lsh     r1, ar1		; align divisor with dividend
-; 
-; Do COUNT+1 subtract & shifts.
-;
-	rpts    r1
-		subc    ar1, r0
-;
-;  Remainder is in upper bits of R0
-;
-	addi    1, r1		; shift count is -(r1+1)
-	negi    r1, r1 
-	lsh     r1, r0		; shift right
-;
-;  Check sign and negate result if necessary.
-;
-return:
-	bud     ir1		; delayed branch to return
-        negi    r0, r1		; negate result
-	cmpi    0, ar0		; check sign
-	ldin    r1, r0		; if set, use negative result
-	; Return occurs here
-;
-; The following code handles cases of a full 32-bit dividend.  This occurs
-; when R0 = abs(R0) = 080000000h.  Handle this by calling the unsigned mod
-; function, then negating the result if necessary.
-;
-mod_32:
-        push    ar0		; remember sign
-	call    umodqi3n	; do divide
-
-	brd     return		; return
-	pop     ar0		; restore sign
-        pop     ir1             ; return address
-	nop
-#endif
-
-#ifdef L_unsfltconst
-	.section .const
-        .global ___unsfltconst
-___unsfltconst:   .float 4294967296.0
-#endif
-
-#ifdef L_unsfltcompare
-	.section .const
-        .global ___unsfltcompare
-___unsfltcompare: .float 2147483648.0
-#endif
-
-; Integer 32-bit signed multiplication
-;
-; The TMS320C3x MPYI instruction takes two 24-bit signed integers
-; and produces a 48-bit signed result which is truncated to 32-bits.
-;
-; A 32-bit by 32-bit multiplication thus requires a number of steps.
-;
-; Consider the product of two 32-bit signed integers,
-;
-;	z = x * y
-;
-; where x = (b << 16) + a,  y = (d << 16) + c
-;
-; This can be expressed as
-;
-;	z = ((b << 16) + a) * ((d << 16) + c)
-;
-;          = ((b * d) << 32) + ((b * c + a * d) << 16) + a * c
-;
-; Let z = (f << 16) + e where f < (1 << 16).
-;
-; Since we are only interested in a 32-bit result, we can ignore the 
-; (b * d) << 32 term, and thus
-;
-;	f = b * c + a * d,  e = a * c
-;
-; We can simplify things if we have some a priori knowledge of the
-; operands, for example, if -32768 <= y <= 32767, then y = c and d = 0 and thus
-;
-;	f = b * c,  e = a * c
-;
-; ar2 multiplier, r2 multiplicand, r0 product
-; clobbers r1, r2, r3
-#ifdef L_mulqi3	
-	.text
-	.global	___mulqi3
-___mulqi3:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldi	*-ar0(1), ar2
-	ldi	*-ar0(2), r2
-	.endif
-
-        pop     ir1		; return address
-	ldi	ar2, r0		;
-	and	0ffffh, r0	; a
-	lsh	-16, ar2	; b
-	ldi	r2, r3		; 
-	and	0ffffh, r3	; c
-	mpyi	r3, ar2		; c * b		
-	lsh	-16, r2		; d
-	mpyi	r0, r2		; a * d
-	addi	ar2, r2		; c * b + a * d
-	bd	ir1		; delayed branch to return
-	lsh	16, r2		; (c * b + a * d) << 16
-	mpyi	r3, r0		; a * c
-	addi	r2, r0		; a * c + (c * b + a * d) << 16
-; branch occurs here
-
-#endif	
-
-;
-; Integer 64 by 64 multiply
-; long1 and long2 on stack
-; result in r0,r1
-;
-#ifdef L_mulhi3
-	.text
-	.global	___mulhi3
-#ifdef _TMS320C4x
-___mulhi3:
-	pop	ar0
-	ldi	sp,ar2
-	ldi	*-ar2(1),r2
-	ldi	*-ar2(3),r3
-	mpyi3	r2,r3,r0
-	mpyuhi3	r2,r3,r1
-	mpyi	*-ar2(2),r2
-	bd	ar0
-	mpyi	*-ar2(0),r3
-	addi	r2,r1
-	addi	r3,r1
-#else
-___mulhi3:
-	ldi	sp,ar2
-	ldi	-16,rs
-	ldi	*-ar2(2),ar0
-	ldi	*-ar2(4),ar1
-	ldi	ar0,r2
-	and	0ffffh,r2
-	ldi	ar1,r3
-	and	0ffffh,r3
-	lsh	rs,ar0
-	lsh	rs,ar1
-
-	mpyi	r2,r3,r0
-	mpyi	ar0,ar1,r1
-	mpyi	r2,ar1,rc
-	lsh	rs,rc,re
-	addi	re,r1
-	lsh	16,rc
-	addi	rc,r0
-	addc	0,r1
-	mpyi	r3,ar0,rc
-	lsh	rs,rc,re
-	addi	re,r1
-	lsh	16,rc
-	addi	rc,r0
-	addc	0,r1
-
-	ldi	*-ar2(1),ar0
-	ldi	ar0,r2
-	and	0ffffh,r2
-	lsh	rs,ar0
-	mpyi	r2,r3,rc
-	addi	rc,r1
-	mpyi	r2,ar1,rc
-	mpyi	r3,ar0,re
-	addi	re,rc
-	lsh	16,rc
-	addi	rc,r1
-
-	ldi	*-ar2(2),ar0
-	ldi	*-ar2(3),ar1
-	ldi	ar0,r2
-	and	0ffffh,r2
-	ldi	ar1,r3
-	and	0ffffh,r3
-	lsh	rs,ar0
-	lsh	rs,ar1
-	mpyi	r2,r3,rc
-	addi	rc,r1
-	mpyi	r2,ar1,rc
-	mpyi	r3,ar0,re
-	pop	ar0
-	bd	ar0
-	addi	re,rc
-	lsh	16,rc
-	addi	rc,r1
-#endif
-#endif
-
-;
-; Integer 32 by 32 multiply highpart unsigned
-; src1 in ar2
-; src2 in r2
-; result in r0
-;
-#ifdef L_umulhi3_high
-	.text
-	.global	___umulhi3_high
-___umulhi3_high:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldi	*-ar0(1), ar2
-	ldi	*-ar0(2), r2
-	.endif
-
-	ldi	-16,rs
-	ldi	r2,r3
-	and	0ffffh,r2
-	ldi	ar2,ar1
-	and	0ffffh,ar2
-	lsh	rs,r3
-	lsh	rs,ar1
-
-	mpyi	ar2,r2,r1
-	mpyi	ar1,r3,r0
-	mpyi	ar2,r3,rc
-	lsh	rs,rc,re
-	addi	re,r0
-	lsh	16,rc
-	addi	rc,r1
-	addc	0,r0
-	mpyi	r2,ar1,rc
-	lsh	rs,rc,re
-	addi	re,r0
-	pop	ar0
-	bd	ar0
-	lsh	16,rc
-	addi	rc,r1
-	addc	0,r0
-#endif
-
-;
-; Integer 32 by 32 multiply highpart signed
-; src1 in ar2
-; src2 in r2
-; result in r0
-;
-#ifdef L_smulhi3_high
-	.text
-	.global	___smulhi3_high
-___smulhi3_high:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldi	*-ar0(1), ar2
-	ldi	*-ar0(2), r2
-	.endif
-
-	ldi	-16,rs
-	ldi	0,rc
-	subi3	ar2,rc,r0
-	ldi	r2,r3
-	ldilt	r0,rc
-	subi3	r2,rc,r0
-	ldi	ar2,ar1
-	tstb	ar1,ar1
-	ldilt	r0,rc
-	and	0ffffh,r2
-	and	0ffffh,ar2
-	lsh	rs,r3
-	lsh	rs,ar1
-
-	mpyi	ar2,r2,r1
-	mpyi	ar1,r3,r0
-	addi	rc,r0
-	mpyi	ar2,r3,rc
-	lsh	rs,rc,re
-	addi	re,r0
-	lsh	16,rc
-	addi	rc,r1
-	addc	0,r0
-	mpyi	r2,ar1,rc
-	lsh	rs,rc,re
-	addi	re,r0
-	pop	ar0
-	bd	ar0
-	lsh	16,rc
-	addi	rc,r1
-	addc	0,r0
-#endif
-
-;
-; Integer 64 by 64 unsigned divide
-; long1 and long2 on stack
-; divide in r0,r1
-; modulo in r2,r3
-; routine takes a maximum of 64*9+21=597 cycles = 24 us @ 50Mhz
-;
-#ifdef L_udivhi3
-	.text
-	.global	___udivhi3
-	.global	___udivide
-	.global	___umodulo
-	.ref udivqi3n
-	.ref umodqi3n
-___udivhi3:
-	ldi	sp,ar2
-	ldi     *-ar2(4),ar0
-	ldi     *-ar2(3),ar1
-	ldi     *-ar2(2),r0
-	ldi     *-ar2(1),r1
-
-___udivide:
-	or	r1,ar1,r2
-	bne	udiv0
-	ldi	ar0,r2
-	ldi	r0,ar2
-	call	udivqi3n
-	ldiu	0,r1
-	rets
-
-___umodulo:
-	or	r1,ar1,r2
-	bne	udiv0
-	ldi	ar0,r2
-	ldi	r0,ar2
-	call	umodqi3n
-	ldi	r0,r2
-	ldiu	0,r3
-	rets
-
-udiv0:
-	tstb	ar1,ar1
-	bne	udiv1
-	tstb	ar0,ar0
-	bn	udiv1
-
-	ldiu	63,rc
-#ifdef _TMS320C4x
-	rptbd	udivend0
-	ldiu	0,r2
-	addi	r0,r0
-	rolc	r1
-#else
-	ldiu	0,r2
-	addi	r0,r0
-	rolc	r1
-	rptb	udivend0
-#endif
-
-	rolc	r2
-	subi3	ar0,r2,r3
-	xor	1,st
-	ldic	r3,r2
-	rolc	r0
-udivend0:
-	rolc	r1
-
-	ldiu	0,r3
-	rets
-udiv1:
-	push	r4
-	push	r5
-	ldiu	63,rc
-	ldiu	0,r2
-#ifdef _TMS320C4x
-	rptbd	udivend1
-	ldiu	0,r3
-	addi	r0,r0
-	rolc	r1
-#else
-	ldiu	0,r3
-	addi	r0,r0
-	rolc	r1
-	rptb	udivend1
-#endif
-
-	rolc	r2
-	rolc	r3
-	subi3	ar0,r2,r4
-	subb3	ar1,r3,r5
-	xor	1,st
-	ldic	r4,r2
-	ldic	r5,r3
-	rolc	r0
-udivend1:
-	rolc	r1
-
-	pop	r5
-	pop	r4
-	rets
-#endif
-
-;
-; Integer 64 by 64 unsigned modulo
-; long1 and long2 on stack
-; result in r0,r1
-;
-#ifdef L_umodhi3
-	.text
-	.global	___umodhi3
-	.ref ___modulo
-___umodhi3:
-	ldi	sp,ar2
-	ldi     *-ar2(4),ar0
-	ldi     *-ar2(3),ar1
-	ldi     *-ar2(2),r0
-	ldi     *-ar2(1),r1
-	call	___umodulo
-	pop	ar0
-	bd	ar0
-	ldi	r2,r0
-	ldi	r3,r1
-	nop
-#endif
-
-;
-; Integer 64 by 64 signed divide
-; long1 and long2 on stack
-; result in r0,r1
-;
-#ifdef L_divhi3
-	.text
-	.global	___divhi3
-	.ref ___udivide
-___divhi3:
-	ldi	0,ir0
-	ldi	sp,ar2
-	ldi     *-ar2(4),r0
-	ldi     *-ar2(3),r1
-	bge	div1
-	negi	ir0
-	negi	r0
-	negb	r1
-div1:
-	ldi	r0,ar0
-	ldi	r1,ar1
-	ldi     *-ar2(2),r0
-	ldi     *-ar2(1),r1
-	bge	div2
-	negi	ir0
-	negi	r0
-	negb	r1
-div2:
-	call	___udivide
-	tstb	ir0,ir0
-	bge	div3
-	negi	r0
-	negb	r1
-div3:	
-	rets
-#endif
-
-;
-; Integer 64 by 64 signed modulo
-; long1 and long2 on stack
-; result in r0,r1
-;
-#ifdef L_modhi3
-	.text
-	.global	___modhi3
-	.ref ___umodulo
-___modhi3:
-	ldi	0,ir0
-	ldi	sp,ar2
-	ldi     *-ar2(4),r0
-	ldi     *-ar2(3),r1
-	bge	mod1
-	negi	ir0
-	negi	r0
-	negb	r1
-mod1:
-	ldi	r0,ar0
-	ldi	r1,ar1
-	ldi     *-ar2(2),r0
-	ldi     *-ar2(1),r1
-	bge	mod2
-	negi	ir0
-	negi	r0
-	negb	r1
-mod2:
-	call	___umodulo
-	ldi	r2,r0
-	ldi	r3,r1
-	tstb	ir0,ir0
-	bge	mod3
-	negi	r0
-	negb	r1
-mod3:	
-	rets
-#endif
-
-;
-; double to signed long long converion
-; input in r2
-; result in r0,r1
-;
-#ifdef L_fix_truncqfhi2
-	.text
-	.global	___fix_truncqfhi2
-	.ref ufix_truncqfhi2n
-___fix_truncqfhi2:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldf	*-ar0(1), r2
-	.endif
-
-	cmpf	0.0,r2
-	bge	ufix_truncqfhi2n
-	negf	r2
-	call	ufix_truncqfhi2n
-	negi	r0
-	negb	r1
-	rets
-#endif
-
-;
-; double to unsigned long long converion
-; input in r2
-; result in r0,r1
-;
-#ifdef L_ufix_truncqfhi2
-	.text
-	.global	___ufix_truncqfhi2
-	.global	ufix_truncqfhi2n
-___ufix_truncqfhi2:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldf	*-ar0(1), r2
-	.endif
-
-ufix_truncqfhi2n:
-	cmpf	0.0,r2
-	ble	ufix1
-	pushf	r2
-	pop	r3
-	ash	-24,r3
-	subi	31,r3
-	cmpi	32,r3
-	bge	ufix1
-	cmpi	-32,r3
-	ble	ufix1
-	ldi	1,r0
-	ash	31,r0
-	or3	r0,r2,r0
-	ldi	r0,r1
-	lsh3	r3,r0,r0
-	subi	32,r3
-	cmpi	-32,r3
-	ldile	0,r1
-	lsh3	r3,r1,r1
-	rets
-ufix1:
-	ldi	0,r0
-	ldi	0,r1
-	rets
-#endif
-
-;
-; signed long long to double converion
-; input on stack
-; result in r0
-;
-#ifdef L_floathiqf2
-	.text
-	.global	___floathiqf2
-	.ref ufloathiqf2n
-___floathiqf2:
-	ldi	sp,ar2
-	ldi	*-ar2(2),r0
-	ldi	*-ar2(1),r1
-	bge	ufloathiqf2n
-	negi	r0
-	negb	r1
-	call	ufloathiqf2n
-	negf	r0
-	rets
-#endif
-
-;
-; unsigned long long to double converion
-; input on stack
-; result in r0
-;
-#ifdef L_ufloathiqf2
-	.text
-	.global	___ufloathiqf2
-	.global	ufloathiqf2n
-	.ref ___unsfltconst
-___ufloathiqf2:
-	ldi	sp,ar2
-	ldi	*-ar2(2),r0
-	ldi	*-ar2(1),r1
-ufloathiqf2n:
-	.if .BIGMODEL
-#ifdef _TMS320C4x
-	ldpk	@___unsfltconst
-#else
-	ldp	@___unsfltconst
-#endif
-	.endif
-	ldf	@___unsfltconst,r2
-	float	r0
-	bge	uflt1
-	addf	r2,r0
-uflt1:
-	float	r1
-	bge	uflt2
-	addf	r2,r1
-uflt2:
-#ifdef _TMS320C4x
-	pop	r3
-	bd	r3
-	mpyf	r2,r1
-	addf	r1,r0
-	nop
-#else
-	ldf	r1,r3
-	and	0ffh,r3
-	norm	r3,r3
-	mpyf	r2,r3
-	pop	ar2
-	bd	ar2
-	addf	r3,r0
-	mpyf	r2,r1
-	addf	r1,r0
-#endif
-#endif
-
-;
-; long double to signed long long converion
-; input in r2
-; result in r0,r1
-;
-#ifdef L_fix_trunchfhi2
-	.text
-	.global	___fix_trunchfhi2
-	.ref ufix_trunchfhi2n
-___fix_trunchfhi2:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldf	*-ar0(2), r2
-	ldi	*-ar0(1), r2
-	.endif
-
-	cmpf	0.0,r2
-	bge	ufix_trunchfhi2n
-	negf	r2
-	call	ufix_trunchfhi2n
-	negi	r0
-	negb	r1
-	rets
-#endif
-
-;
-; long double to unsigned long long converion
-; input in r2
-; result in r0,r1
-;
-#ifdef L_ufix_trunchfhi2
-	.text
-	.global	___ufix_trunchfhi2
-	.global	ufix_trunchfhi2n
-___ufix_trunchfhi2:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldf	*-ar0(2), r2
-	ldi	*-ar0(1), r2
-	.endif
-
-ufix_trunchfhi2n:
-	cmpf	0.0,r2
-	ble	ufixh1
-	pushf	r2
-	pop	r3
-	ash	-24,r3
-	subi	31,r3
-	cmpi	32,r3
-	bge	ufixh1
-	cmpi	-32,r3
-	ble	ufixh1
-	ldi	1,r0
-	ash	31,r0
-	or3	r0,r2,r0
-	ldi	r0,r1
-	lsh3	r3,r0,r0
-	subi	32,r3
-	cmpi	-32,r3
-	ldile	0,r1
-	lsh3	r3,r1,r1
-	rets
-ufixh1:
-	ldi	0,r0
-	ldi	0,r1
-	rets
-#endif
-
-;
-; signed long long to long double converion
-; input on stack
-; result in r0
-;
-#ifdef L_floathihf2
-	.text
-	.global	___floathihf2
-	.ref ufloathihf2n
-___floathihf2:
-	ldi	sp,ar2
-	ldi	*-ar2(2),r0
-	ldi	*-ar2(1),r1
-	bge	ufloathihf2n
-	negi	r0
-	negb	r1
-	call	ufloathihf2n
-	negf	r0
-	rets
-#endif
-
-;
-; unsigned long long to double converion
-; input on stack
-; result in r0
-;
-#ifdef L_ufloathihf2
-	.text
-	.global	___ufloathihf2
-	.global	ufloathihf2n
-	.ref ___unsfltconst
-___ufloathihf2:
-	ldi	sp,ar2
-	ldi	*-ar2(2),r0
-	ldi	*-ar2(1),r1
-ufloathihf2n
-	.if .BIGMODEL
-#ifdef _TMS320C4x
-	ldpk	@___unsfltconst
-#else
-	ldp	@___unsfltconst
-#endif
-	.endif
-	ldf	@___unsfltconst,r2
-	float	r0
-	bge	uflth1
-	addf	r2,r0
-uflth1:
-	float	r1
-	bge	uflth2
-	addf	r2,r1
-uflth2:
-#ifdef _TMS320C4x
-	pop	r3
-	bd	r3
-	mpyf	r2,r1
-	addf	r1,r0
-	nop
-#else
-	ldf	r1,r3
-	and	0ffh,r3
-	norm	r3,r3
-	mpyf	r2,r3
-	pop	ar2
-	bd	ar2
-	addf	r3,r0
-	mpyf	r2,r1
-	addf	r1,r0
-#endif
-#endif
-
-;
-; calculate ffs
-; input in ar2
-; result in r0
-;
-#ifdef L_ffs
-	.global	___ffs
-	.ref ___unsfltconst
-	.text
-___ffs:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldi	*-ar0(1), ar2
-	.endif
-
-	negi	ar2,r0
-	and	ar2,r0
-	float	r0,r0
-	ldfu	0.0,r1
-	.if .BIGMODEL
-#ifdef _TMS320C4x
-	ldpk	@___unsfltconst
-#else
-	ldp	@___unsfltconst
-#endif
-	.endif
-	ldflt	@___unsfltconst,r1
-	addf	r1,r0
-	pushf	r0
-	pop	r0
-	pop	ar0
-	bd	ar0
-	ash	-24,r0
-	ldilt	-1,r0
-	addi	1,r0
-#endif
-
-;
-; calculate long double * long double
-; input in r2, r3
-; output in r0
-;
-#ifdef L_mulhf3
-	.global ___mulhf3
-	.text
-___mulhf3:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldf	*-ar0(2), r2
-	ldi	*-ar0(1), r2
-	ldf	*-ar0(4), r3
-	ldi	*-ar0(3), r3
-	.endif
-
-	pop	ar2		; return ad
-	ldf	r2,r0		; copy lsb0
-	ldf	r3,r1		; copy lsb1
-	and	0ffh,r0		; mask lsb0
-	and	0ffh,r1		; mask lsb1
-	norm	r0,r0		; correct lsb0
-	norm	r1,r1		; correct lsb1
-	mpyf	r2,r1		; arg0*lsb1
-	mpyf	r3,r0		; arg1*lsb0
-	bd	ar2		; return (delayed)
-	addf	r0,r1		; arg0*lsb1 + arg1*lsb0
-	mpyf	r2,r3,r0	; msb0*msb1
-	addf	r1,r0		; msb0*msb1 + arg0*lsb1 + arg1*lsb0
-#endif
-
-;
-; calculate long double / long double
-; r2 dividend, r3 divisor, r0 quotient
-;
-#ifdef L_divhf3
-	.global ___divhf3
-	.text
-___divhf3:
-	.if .REGPARM == 0
-#ifdef _TMS320C4x
-	lda	sp,ar0
-#else
-	ldiu	sp,ar0
-#endif
-	ldf	*-ar0(2), r2
-	ldi	*-ar0(1), r2
-	ldf	*-ar0(4), r3
-	ldi	*-ar0(3), r3
-	.endif
-
-#ifdef _TMS320C4x
-	pop	ar1
-        rcpf    r3, r0
-	mpyf3	r0, r3, r1
-	subrf	2.0, r1		
-	mpyf	r1, r0	
-	mpyf3	r0, r3, r1
-	bud	ar1
-	subrf	2.0, r1	
-	mpyf	r1, r0
-	mpyf	r2, r0
-#else
-	pop	ar1
-	pushf	r3
-	pop	r0
-	not	r0	
-	push	r0
-	popf	r0
-	ldf	-1.0, r1
-	xor	r1, r0
-
-	mpyf3	r0, r3, r1	; r1 = r[0] * v
-	subrf	2.0, r1		; r1 = 2.0 - r[0] * v
-	mpyf	r1, r0		; r0 = r[0] * (2.0 - r[0] * v) = r[1]
-; End of 1st iteration
-
-	mpyf3	r0, r3, r1	; r1 = r[1] * v
-	subrf	2.0, r1		; r1 = 2.0 - r[1] * v
-	mpyf	r1, r0		; r0 = r[1] * (2.0 - r[1] * v) = r[2]
-; End of 2nd iteration
-
-	mpyf3	r0, r3, r1	; r1 = r[2] * v
-	subrf	2.0, r1		; r1 = 2.0 - r[2] * v
-	mpyf	r1, r0		; r0 = r[2] * (2.0 - r[2] * v) = r[3]
-; End of 3rd iteration
-
-	or	080h, r0
-	rnd	r0
-
-;	mpyf3	r0, r3, r1	; r1 = r[3] * v
-	push	r4
-	pushf	r4
-	mpyf	r0, r3, r1
-
-	ldf	r0, r4
-	and	0ffh, r4
-	norm	r4, r4
-	mpyf	r3, r4
-	addf	r4, r1
-
-	ldf	r3, r4
-	and	0ffh, r4
-	norm 	r4, r4
-	mpyf	r0, r4
-	addf	r4, r1
-	
-	subrf	2.0, r1		; r1 = 2.0 - r[3] * v
-
-	mpyf	r1, r0, r3	; r3 = r[3] * (2.0 - r[3] * v) = r[5]
-
-	ldf	r1, r4
-	and	0ffh, r4
-	norm	r4, r4
-	mpyf	r0, r4
-	addf	r4, r3
-
-	ldf	r0, r4
-	and	0ffh, r4
-	norm 	r4, r4
-	mpyf	r1, r4
-	addf	r4, r3
-
-	mpyf	r2, r3, r0	; Multiply by the dividend
-
-	ldf	r2, r4
-	and	0ffh, r4
-	norm	r4, r4
-	mpyf	r3, r4
-	addf	r4, r0
-
-	ldf	r3, r4
-	and	0ffh, r4
-	norm 	r4, r4
-	mpyf	r2, r4
-	bd	ar1
-	addf	r4, r0
-
-	popf	r4
-	pop	r4
-#endif
-#endif
diff --git a/gcc/config/c4x/t-c4x b/gcc/config/c4x/t-c4x
deleted file mode 100755
index 39e316e..0000000
--- a/gcc/config/c4x/t-c4x
+++ /dev/null
@@ -1,22 +0,0 @@
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = c4x/libgcc.S
-LIB1ASMFUNCS = _divqf3 _divqi3 _udivqi3 _umodqi3 _modqi3 _mulqi3 \
-	_mulhf3 _divhf3 _unsfltconst _unsfltcompare \
-	_mulhi3 _umulhi3_high _smulhi3_high _divhi3 _modhi3 _umodhi3 _udivhi3 \
-	_fix_truncqfhi2 _ufix_truncqfhi2 _floathiqf2 _ufloathiqf2 \
-	_floathihf2 _ufloathihf2 _fix_trunchfhi2 _ufix_trunchfhi2 _ffs
-
-# We do not have DF or DI types (or SF and SI for that matter),
-# so fake out the libgcc2 compilation.
-LIBGCC2_CFLAGS = -O2 -Dexit=unused_exit $(GCC_CFLAGS) $(LIBGCC2_INCLUDES) -DDF=HF -DDI=HI -DSF=QF -DSI=QI -Dinhibit_libc
-
-MULTILIB_OPTIONS = m30 msmall mmemparm
-MULTILIB_DIRNAMES = c3x small mem
-MULTILIB_MATCHES = m30=mcpu?30 m30=mcpu?31 m30=mcpu?32 m30=m31 m30=m32
-MULTILIB_EXCEPTIONS =
-MULTILIB_EXTRA_OPTS =
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# Don't make libgcc1-test since require crt0.o
-LIBGCC1_TEST =
diff --git a/gcc/config/c4x/xm-c4x.h b/gcc/config/c4x/xm-c4x.h
deleted file mode 100755
index dc329eb..0000000
--- a/gcc/config/c4x/xm-c4x.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 32
-#define HOST_BITS_PER_SHORT 32
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_WORDS_BIG_ENDIAN
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
diff --git a/gcc/config/clipper/clipper.c b/gcc/config/clipper/clipper.c
deleted file mode 100755
index d59d3f1..0000000
--- a/gcc/config/clipper/clipper.c
+++ /dev/null
@@ -1,508 +0,0 @@
-/* Subroutines for insn-output.c for Clipper
-   Copyright (C) 1987, 1988, 1991, 1997 Free Software Foundation, Inc.
-   Contributed by Holger Teutsch (holger@hotbso.rhein-main.de)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "tree.h"
-#include "c-tree.h"
-#include "expr.h"
-#include "flags.h"
-#include "machmode.h"
-
-extern char regs_ever_live[];
-
-extern int frame_pointer_needed;
-
-static int frame_size;
-
-/*
- * compute size of a clipper stack frame where 'lsize' is the required
- * space for local variables.
- */
-
-int
-clipper_frame_size (lsize)
-     int lsize;
-{
-  int i,size;				/* total size of frame */
-  int save_size;
-  save_size = 0;			/* compute size for reg saves */
-
-  for (i = 16; i < 32; i++)
-    if (regs_ever_live[i] && !call_used_regs[i])
-      save_size += 8;
-
-  for (i = 0; i < 16; i++)
-    if (regs_ever_live[i] && !call_used_regs[i])
-      save_size += 4;
-
-  size = lsize + save_size;
-
-  size = (size + 7) & ~7;		/* align to 64 Bit */
-  return size;
-}
-
-/*
- * prologue and epilogue output
- * function is entered with pc pushed, i.e. stack is 32 bit aligned
- *
- * current_function_args_size == 0 means that the current function's args
- * are passed totally in registers i.e fp is not used as ap.
- * If frame_size is also 0 the current function does not push anything and
- * can run with misaligned stack -> subq $4,sp / add $4,sp on entry and exit
- * can be omitted.
- *
- */
-void
-output_function_prologue (file, lsize)
-     FILE *file;
-     int lsize;				/* size for locals */
-{
-  int i, offset;
-  int size;
-
-  frame_size = size = clipper_frame_size (lsize);
-
-  if (frame_pointer_needed)
-    {
-      fputs ("\tpushw  fp,sp\n", file);
-      fputs ("\tmovw   sp,fp\n", file);
-    }
-  else if (size != 0 || current_function_args_size != 0)
-    {
-      size += 4;			/* keep stack aligned */
-      frame_size = size;		/* must push data or access args */
-    }
-
-  if (size)
-    {
-      if (size < 16)
-	fprintf (file, "\tsubq   $%d,sp\n", size);
-      else
-	fprintf (file, "\tsubi   $%d,sp\n", size);
-
-      /* register save slots are relative to sp, because we have small positive
-	 displacements and this works whether we have a frame pointer or not */
-
-      offset = 0;
-      for (i = 16; i < 32; i++)
-	if (regs_ever_live[i] && !call_used_regs[i])
-	  {
-	    if (offset == 0)
-	      fprintf (file, "\tstord  f%d,(sp)\n", i-16);
-	    else
-	      fprintf (file, "\tstord  f%d,%d(sp)\n", i-16, offset);
-	    offset += 8;
-	  }
-
-      for (i = 0; i < 16; i++)
-	if (regs_ever_live[i] && !call_used_regs[i])
-	  {
-	    if (offset == 0)
-	      fprintf (file, "\tstorw  r%d,(sp)\n", i);
-	    else
-	      fprintf (file, "\tstorw  r%d,%d(sp)\n", i, offset);
-	    offset += 4;
-	  }
-    }
-}
-
-void
-output_function_epilogue (file, size)
-     FILE *file;
-     int size;				/* ignored */
-{
-  int i, offset;
-
-  if (frame_pointer_needed)
-    {
-      offset = -frame_size;
-
-      for (i = 16; i < 32; i++)
-	if (regs_ever_live[i] && !call_used_regs[i])
-	  {
-	    fprintf (file, "\tloadd  %d(fp),f%d\n", offset, i-16);
-	    offset += 8;
-	  }
-
-      for (i = 0; i < 16; i++)
-	if (regs_ever_live[i] && !call_used_regs[i])
-	  {
-	    fprintf (file, "\tloadw  %d(fp),r%d\n", offset, i);
-	    offset += 4;
-	  }
-
-      fputs ("\tmovw   fp,sp\n\tpopw   sp,fp\n\tret    sp\n",
-	     file);
-    }
-
-  else					/* no frame pointer */
-    {
-      offset = 0;
-
-      for (i = 16; i < 32; i++)
-	if (regs_ever_live[i] && !call_used_regs[i])
-	  {
-	    if (offset == 0)
-	      fprintf (file, "\tloadd  (sp),f%d\n", i-16);
-	    else
-	      fprintf (file, "\tloadd  %d(sp),f%d\n", offset, i-16);
-	    offset += 8;
-	  }
-
-      for (i = 0; i < 16; i++)
-	if (regs_ever_live[i] && !call_used_regs[i])
-	  {
-	    if (offset == 0)
-	      fprintf (file, "\tloadw  (sp),r%d\n", i);
-	    else
-	      fprintf (file, "\tloadw  %d(sp),r%d\n", offset, i);
-	    offset += 4;
-	  }
-
-      if (frame_size > 0)
-	{
-	  if (frame_size < 16)
-	    fprintf (file, "\taddq   $%d,sp\n", frame_size);
-	  else
-	    fprintf (file, "\taddi   $%d,sp\n", frame_size);
-	}
-
-      fputs ("\tret    sp\n", file);
-    }
-}
-
-/*
- * blockmove
- *
- * clipper_movstr ()
- */
-void
-clipper_movstr (operands)
-     rtx *operands;
-{
-  rtx dst,src,cnt,tmp,top,bottom,xops[3];
-  int align;
-  int fixed;
-
-  extern FILE *asm_out_file;
-
-  dst = operands[0];
-  src = operands[1];
-  /* don't change this operands[2]; gcc 2.3.3 doesn't honor clobber note */
-  align = INTVAL (operands[3]);
-  tmp = operands[4];
-  cnt = operands[5];
-
-  if (GET_CODE (operands[2]) == CONST_INT) /* fixed size move */
-    {
-      if ((fixed = INTVAL (operands[2])) <= 0)
-	abort ();
-
-      if (fixed <16)
-	output_asm_insn ("loadq  %2,%5", operands);
-      else
-	output_asm_insn ("loadi  %2,%5", operands);
-    }
-  else
-    {
-      fixed = 0;
-      bottom = (rtx)gen_label_rtx ();	/* need a bottom label */
-      xops[0] = cnt; xops[1] = bottom;
-      output_asm_insn ("movw   %2,%5", operands); /* count is scratch reg 5 */
-      output_asm_insn ("brle   %l1", xops);
-    }
-
-
-  top = (rtx)gen_label_rtx ();		/* top of loop label */
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (top));
-
-
-  xops[0] = src; xops[1] = tmp; xops[2] = dst;
-
-  if (fixed && (align & 0x3) == 0)	/* word aligned move with known size */
-    {
-      if (fixed >= 4)
-	{
-	  rtx xops1[2];
-	  output_asm_insn(
-	    "loadw  %a0,%1\n\taddq   $4,%0\n\tstorw  %1,%a2\n\taddq   $4,%2",
-			  xops);
-
-	  xops1[0] = cnt; xops1[1] = top;
-	  output_asm_insn ("subq   $4,%0\n\tbrgt   %l1", xops1);
-	}
-
-      if (fixed & 0x2)
-	{
-	  output_asm_insn ("loadh  %a0,%1\n\tstorh  %1,%a2", xops);
-	  if (fixed & 0x1)
-	    output_asm_insn ("loadb  2%a0,%1\n\tstorb  %1,2%a2", xops);
-	}
-      else
-	if (fixed & 0x1)
-	  output_asm_insn ("loadb  %a0,%1\n\tstorb  %1,%a2", xops);
-    }
-  else
-    {
-      output_asm_insn(
-	  "loadb  %a0,%1\n\taddq   $1,%0\n\tstorb  %1,%a2\n\taddq   $1,%2",
-		      xops);
-
-      xops[0] = cnt; xops[1] = top;
-      output_asm_insn ("subq   $1,%0\n\tbrgt   %l1", xops);
-    }
-
-  if (fixed == 0)
-    ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (bottom));
-}
-
-
-print_operand_address (file, addr)
-     FILE *file;
-     register rtx addr;
-{
-  rtx op0,op1;
-
- retry:
-  switch (GET_CODE (addr))
-    {
-    case REG:
-      fprintf (file, "(%s)", reg_names[REGNO (addr)]);
-      break;
-
-    case PLUS:
-      /* can be 'symbol + reg' or 'reg + reg' */
-
-      op0 = XEXP (addr, 0);
-      op1 = XEXP (addr, 1);
-
-      if (GET_CODE (op0) == REG && GET_CODE (op1) == REG)
-	{
-	  fprintf (file, "[%s](%s)",
-		   reg_names[REGNO (op0)], reg_names[REGNO (op1)]);
-	  break;
-	}
-
-      if (GET_CODE (op0) == REG && CONSTANT_ADDRESS_P (op1))
-	{
-	  output_addr_const (file, op1);
-	  fprintf (file, "(%s)", reg_names[REGNO (op0)]);
-	  break;
-	}
-
-      if (GET_CODE (op1) == REG && CONSTANT_ADDRESS_P (op0))
-	{
-	  output_addr_const (file, op0);
-	  fprintf (file, "(%s)", reg_names[REGNO (op1)]);
-	  break;
-	}
-      abort ();				/* Oh no */
-
-    default:
-      output_addr_const (file, addr);
-    }
-}
-
-
-char *
-rev_cond_name (op)
-     rtx op;
-{
-  switch (GET_CODE (op))
-    {
-    case EQ:
-      return "ne";
-    case NE:
-      return "eq";
-    case LT:
-      return "ge";
-    case LE:
-      return "gt";
-    case GT:
-      return "le";
-    case GE:
-      return "lt";
-    case LTU:
-      return "geu";
-    case LEU:
-      return "gtu";
-    case GTU:
-      return "leu";
-    case GEU:
-      return "ltu";
-
-    default:
-      abort ();
-    }
-}
-
-
-/* Do what is necessary for `va_start'.  The argument is ignored;
-   We fill in an initial va_list.  A pointer to this constructor
-   is returned. */
-
-
-struct rtx_def *
-clipper_builtin_saveregs (arglist)
-     tree arglist;
-{
-  extern int current_function_varargs;
-  rtx block, addr, argsize, scratch, r0_addr,r1_addr,f0_addr,f1_addr;
-
-  /* Allocate the va_list constructor + save area for r0,r1,f0,f1 */
-
-  block = assign_stack_local (BLKmode,
-			      (6 + 6) * UNITS_PER_WORD, 2 * BITS_PER_WORD);
-
-  RTX_UNCHANGING_P (block) = 1;
-  RTX_UNCHANGING_P (XEXP (block, 0)) = 1;
-
-  addr = copy_to_reg (XEXP (block, 0));
-
-  f0_addr =  gen_rtx (PLUS, Pmode, addr, GEN_INT (24));
-  f1_addr =  gen_rtx (PLUS, Pmode, addr, GEN_INT (32));
-  r0_addr =  gen_rtx (PLUS, Pmode, addr, GEN_INT (40));
-  r1_addr =  gen_rtx (PLUS, Pmode, addr, GEN_INT (44));
-
-
-  /* Store float regs  */
-
-  emit_move_insn (gen_rtx (MEM, DFmode, f0_addr), gen_rtx (REG, DFmode, 16));
-  emit_move_insn (gen_rtx (MEM, DFmode, f1_addr), gen_rtx (REG, DFmode, 17));
-
-  /* Store int regs  */
-
-  emit_move_insn (gen_rtx (MEM, SImode, r0_addr), gen_rtx (REG, SImode, 0));
-  emit_move_insn (gen_rtx (MEM, SImode, r1_addr), gen_rtx (REG, SImode, 1));
-
-  /* Store the arg pointer in the __va_stk member.  */
-
-  emit_move_insn (gen_rtx (MEM, SImode, addr),
-		  copy_to_reg (virtual_incoming_args_rtx));
-		  
-
-  /* now move addresses of the saved regs into the pointer array */
-
-  scratch = gen_reg_rtx (Pmode);
-
-  emit_move_insn (scratch, r0_addr);
-  emit_move_insn (gen_rtx (MEM, SImode,
-			   gen_rtx (PLUS, Pmode, addr,
-				    GEN_INT (4))),
-		  scratch);
-		  
-  emit_move_insn (scratch, f0_addr);
-  emit_move_insn (gen_rtx (MEM, SImode,
-			   gen_rtx (PLUS, Pmode, addr,
-				    GEN_INT (8))),
-		  scratch);
-		  
-  emit_move_insn (scratch, r1_addr);
-  emit_move_insn (gen_rtx (MEM, SImode,
-			   gen_rtx (PLUS, Pmode, addr,
-				    GEN_INT (12))),
-		  scratch);
-		  
-  emit_move_insn (scratch, f1_addr);
-  emit_move_insn (gen_rtx (MEM, SImode,
-			   gen_rtx (PLUS, Pmode, addr,
-				    GEN_INT (16))),
-		  scratch);
-
-
-  if (current_function_check_memory_usage)
-    {
-      emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
-			 addr, ptr_mode,
-			 GEN_INT (5 * GET_MODE_SIZE (SImode)),
-			 TYPE_MODE (sizetype),
-			 GEN_INT (MEMORY_USE_RW),
-			 TYPE_MODE (integer_type_node));
-
-      emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
-			 f0_addr, ptr_mode,
-			 GEN_INT (GET_MODE_SIZE (DFmode)),
-			 TYPE_MODE (sizetype),
-			 GEN_INT (MEMORY_USE_RW), 
-			 TYPE_MODE (integer_type_node));
-      emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
-			 f1_addr, ptr_mode,
-			 GEN_INT (GET_MODE_SIZE (DFmode)),
-			 TYPE_MODE (sizetype),
-			 GEN_INT (MEMORY_USE_RW), 
-			 TYPE_MODE (integer_type_node));
-      emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
-			 r0_addr, ptr_mode,
-			 GEN_INT (GET_MODE_SIZE (SImode)),
-			 TYPE_MODE (sizetype),
-			 GEN_INT (MEMORY_USE_RW),
-			 TYPE_MODE (integer_type_node));
-      emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
-			 r1_addr, ptr_mode,
-			 GEN_INT (GET_MODE_SIZE (SImode)),
-			 TYPE_MODE (sizetype),
-			 GEN_INT (MEMORY_USE_RW),
-			 TYPE_MODE (integer_type_node));
-    }
-
-  /* Return the address of the va_list constructor, but don't put it in a
-     register.  This fails when not optimizing and produces worse code when
-     optimizing.  */
-  return XEXP (block, 0);
-}
-
-
-/* Return truth value of whether OP can be used as an word register
-   operand. Reject (SUBREG:SI (REG:SF )) */
-
-int
-int_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode) &&
-	  (GET_CODE (op) != SUBREG ||
-	   GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) == MODE_INT));
-}
-
-/* Return truth value of whether OP can be used as a float register
-   operand. Reject (SUBREG:SF (REG:SI )) )) */
-
-int
-fp_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode) &&
-	  (GET_CODE (op) != SUBREG ||
-	   GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) == MODE_FLOAT));
-}
-
diff --git a/gcc/config/clipper/clipper.h b/gcc/config/clipper/clipper.h
deleted file mode 100755
index 666e96d..0000000
--- a/gcc/config/clipper/clipper.h
+++ /dev/null
@@ -1,1125 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Clipper version.
-   Copyright (C) 1987, 88, 91, 93-95, 1996 Free Software Foundation, Inc.
-   Contributed by Holger Teutsch (holger@hotbso.rhein-main.de)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-extern struct rtx_def *clipper_builtin_saveregs ();
-extern int clipper_frame_size ();
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fprintf (stderr, " (clipper)");
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES		\
-  { { "c400", 1 },		\
-    { "c300", -1 },		\
-    { "", TARGET_DEFAULT} }
-
-#define TARGET_C400 1
-#define TARGET_C300 0
-
-/* Default target_flags if no switches specified.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT TARGET_C300
-#endif
-
-/* Show that we can debug generated code without a frame pointer.  */
-#define CAN_DEBUG_WITHOUT_FP
-
-/* Target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields. */
-
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.  */
-
-#define WORDS_BIG_ENDIAN 0
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Largest alignment for stack parameters (if greater than PARM_BOUNDARY).  */
-#define MAX_PARM_BOUNDARY 64
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 128
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 64
-
-/* No structure field wants to be aligned rounder than this.  */
-#define BIGGEST_FIELD_ALIGNMENT 64
-
-/*  Make strcpy of constants fast. */
-#define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
-  ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Let's keep the stack somewhat aligned.  */
-#define STACK_BOUNDARY 64
-
-/* Define this macro if it is advisable to hold scalars in registers
-   in a wider mode than that declared by the program.  In such cases, 
-   the value is constrained to be within the bounds of the declared
-   type, but kept valid in the wider mode.  The signedness of the
-   extension may differ from that of the type.
-
-   For Clipper, we always store objects in a full register. */
-
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)  \
-  if (GET_MODE_CLASS (MODE) == MODE_INT		\
-      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)	\
-    {						\
-      (UNSIGNEDP) = 0;				\
-      (MODE) = SImode;				\
-    }
-
-
-/* Define this if function arguments should also be promoted using the above
-   procedure.  */
-
-/* FIXME: do we loose compatibility to acc if we define this? */
-
-/* #define PROMOTE_FUNCTION_ARGS */
-
-/* Likewise, if the function return value is promoted.  */
-
-/* #define PROMOTE_FUNCTION_RETURN */
-
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  */
-#define FIRST_PSEUDO_REGISTER 32
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   On the clipper, these are the FP and SP .  */
-#define FIXED_REGISTERS \
-{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,\
- 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1} /* Default: C300 */
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS \
-{1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,\
- 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1} /* default: C300 */
-
-/* Zero or more C statements that may conditionally modify two
-   variables `fixed_regs' and `call_used_regs' (both of type `char
-   []') after they have been initialized from the two preceding
-   macros. A C400 has additional floating registers f8 -> f15 */
-
-#define CONDITIONAL_REGISTER_USAGE	\
-   if (target_flags & TARGET_C400)	\
-     { int i;				\
-       for (i = 24; i < 32; i++) fixed_regs[i] = call_used_regs[i] = 0; }
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-   On the clipper, fp registers are 64 bits.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((REGNO) >= 16 ? 1 \
-   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On the clipper 0-15 may hold any mode but DImode and DFmode must be even.
-   Registers 16-31 hold SFmode and DFmode */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE)					\
-  ((REGNO) < 16 							\
-   ? ((MODE) != DImode && (MODE) != DFmode || ((REGNO) & 1) == 0)	\
-   : ((MODE) == SFmode || (MODE) == DFmode))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2)  ((MODE1) == (MODE2))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* clipper has extra PC  */
-/* #define PC_REGNUM */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 15
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 14
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED \
-   (! leaf_function_p ())
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 2
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 0
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-/* The clipper has general and FP regs.  */
-
-enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS {0, 0x0000ffff, 0xffff0000, 0xffffffff}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) ((REGNO) >= 16 ? FLOAT_REGS : GENERAL_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'r' ? GENERAL_REGS : ((C) == 'f' ? FLOAT_REGS: NO_REGS))
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C. */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) 0
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself. */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
-
-/* Optional extra constraints for this machine. */
-
-/* #define EXTRA_CONSTRAINT(OP, C) */
-
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)  (CLASS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- ((CLASS) == FLOAT_REGS			\
-  ? 1					\
-  : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if longjmp restores from saved registers
-   rather than from what setjmp saved.  */
-/* #define LONGJMP_RESTORE_FROM_STACK */
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET 0
-
-/* Given an rtx for the address of a frame,
-   return an rtx for the address of the word in the frame
-   that holds the dynamic chain--the previous frame's address.  */
-#define DYNAMIC_CHAIN_ADDRESS(frame) (frame)
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by. */
-
-/* #define PUSH_ROUNDING(BYTES) (BYTES) */
-
-/* Keep the stack pointer constant throughout the function. */
-/* we can't set this for clipper as library calls may have 3 args and we pass
-   only 2 args in regs. */
-
-/* #define ACCUMULATE_OUTGOING_ARGS */
-  
-
-/* Offset of first parameter from the argument pointer register value.
-   size of PC + FP  */
-
-#define FIRST_PARM_OFFSET(FNDECL) 8
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), ((TYPE_MODE (VALTYPE) == SFmode ||\
-				       TYPE_MODE (VALTYPE) == DFmode) ? \
-				        16 : 0))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE)  \
-  gen_rtx (REG, (MODE), ((MODE) == SFmode || (MODE) == DFmode ? 16 : 0))
-
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 16)
-
-/* 1 if N is a possible register number for function argument passing.  */
-
-#define FUNCTION_ARG_REGNO_P(N) \
-  ((N) == 0 || (N) == 1 || (N) == 16 || (N) == 17)
-
-/* Define this if PCC uses the nonreentrant convention for returning
-   structure and union values. Old Green Hills C-Clipper returns static
-   structs but the newer Apogee compiler passes structs as hidden arg 0.
-   Structs etc are always passed in memory */
-
-/* #define PCC_STATIC_STRUCT_RETURN */
-
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   Clipper uses 2 register 'slots' that pass arguments in r0/r1 or f0/f1.
-   An argument that must be passed in memory (struct... ) leaves that slot
-   free.
-   We pass 'long long' only in registers when both slots are free.
-   Returned structs must be allocated by the caller, the address is passed
-   in r0.
-
-   struct ss {..}
-
-   fun (i,j,k)		i in r0, j in r1, k on stack
-   fun (s,j,k)		s on stack, j in r1, k on stack
-   fun (i,s,k)		i in r0, s on stack, k on stack
-   s1 = fun (i,s,k)	&s1 in r0, i in r1, s on stack, k on stack
-
-   We must keep enough information for varargs/stdargs.
-
-   _clipper_cum_args is a struct of 2 integers, with
-	num =  slots used
-	size = size of all stack args = offset to next arg without alignment
-
-   If we use stdarg.h, size points to the first unnamed arg,
-   see va-clipper.h */
-
-struct _clipper_cum_args { int num; int size; };
-
-#define CUMULATIVE_ARGS struct _clipper_cum_args
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   clipper passes the address of a struct in r0, set num = 1 in this case */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
-  ((CUM).num = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE (FNTYPE))), \
-   (CUM).size = 0)
-
-/* internal helper : size of an argument */
-
-#define CLIPPER_ARG_SIZE(MODE, TYPE)				\
-(((MODE) != BLKmode							\
-  ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD 	\
-  : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)	\
- * UNITS_PER_WORD)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			      \
-do									      \
-{									      \
-  int reg = 0;								      \
-									      \
-  if ((CUM).num < 2							      \
-      && (GET_MODE_CLASS(MODE)==MODE_INT || GET_MODE_CLASS(MODE)==MODE_FLOAT) \
-      && (GET_MODE_SIZE (MODE) <= 8)					      \
-      && ((TYPE) == NULL || !AGGREGATE_TYPE_P(TYPE))			      \
-      && ((MODE) != DImode || (CUM).num == 0))				      \
-    {									      \
-      reg = 1;								      \
-      if ((MODE) == DImode)						      \
-	(CUM).num = 1;							      \
-    }									      \
-									      \
-  (CUM).num++;								      \
-									      \
-  if (! reg)								      \
-    {									      \
-      int align = FUNCTION_ARG_BOUNDARY (MODE, TYPE) / BITS_PER_UNIT;	      \
-      (CUM).size += align - 1;						      \
-      (CUM).size &= ~(align - 1);					      \
-      (CUM).size += CLIPPER_ARG_SIZE (MODE, TYPE);			      \
-    }									      \
-} while (0)
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-
-   2 args may go into regs. These must be MODE_INT or MODE_FLOAT but only
-   if they really fit into ONE register. The exception is a DImode arg
-   that occupies both register slots. */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)				     \
-  (((CUM).num < 2							     \
-    && (GET_MODE_CLASS(MODE)==MODE_INT || GET_MODE_CLASS(MODE)==MODE_FLOAT)  \
-    && (GET_MODE_SIZE (MODE) <= 8)					     \
-    && ((TYPE) == NULL || !AGGREGATE_TYPE_P(TYPE))			     \
-    && ((MODE) != DImode || (CUM).num == 0))				     \
-   ? gen_rtx (REG, (MODE),						     \
-	      GET_MODE_CLASS(MODE) == MODE_FLOAT ? (CUM).num+16 : (CUM).num) \
-   : 0)
-
-/* If defined, a C expression that gives the alignment boundary, in bits,
-   of an argument with the specified mode and type.  If it is not defined,
-   `PARM_BOUNDARY' is used for all arguments.  */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
-  (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_SIZE (MODE)) <= PARM_BOUNDARY \
-    ? PARM_BOUNDARY : 2 * PARM_BOUNDARY)
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.
-   Clipper never passed args partially in regs/mem. */
-
-/* #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)  0 */
-
-/* Generate necessary RTL for __builtin_saveregs().
-   ARGLIST is the argument list; see expr.c.  */
-
-#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) clipper_builtin_saveregs (ARGLIST)
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue (FILE,SIZE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  /* FIXME */
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.  */
-
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  /* FIXME */
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  */
-
-#define BLOCK_PROFILER(FILE, BLOCKNO)	/* FIXME */
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue(FILE,SIZE)
-
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved. */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
-  DEPTH = clipper_frame_size (get_frame_size ())
-
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  */
-
-#define TRAMPOLINE_TEMPLATE(FILE)					      \
-{									      \
-  fputs ("\t.word  0x459F,0x0004\t# call   sp,.+4\n", FILE);		      \
-  fputs ("\tmovw   (sp),r3\n", FILE);					      \
-  fputs ("\taddq   $4,sp\n", FILE);					      \
-  fputs ("\tloadw  20(r3),r2\n", FILE);					      \
-  fputs ("\tloadw  24(r3),r3\n", FILE);					      \
-  fputs ("\tb      (r3)\n", FILE);					      \
-  fputs ("\t.long  0,0\n", FILE);					      \
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 32
-
-/* Alignment required for a trampoline.  128 is used to find the
-   beginning of a line in the instruction cache and to allow for
-   instruction cache lines of up to 128 bytes.  */
-
-#define TRAMPOLINE_ALIGNMENT 128
-
-/* Section in which to place the trampoline.  */
-
-#define TRAMPOLINE_SECTION text_section
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 24)), CXT); \
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 28)), FNADDR); \
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(regno)  \
-((regno) < 16 || (unsigned)reg_renumber[regno] < 16)
-#define REGNO_OK_FOR_BASE_P(regno) \
-((regno) < 16 || (unsigned)reg_renumber[regno] < 16)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* 1 if X is an rtx for a constant that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-  /* clipper doesn't have true indexing */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-
-#define REG_OK_FOR_INDEX_P(X) \
-  (REGNO (X) < 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
-
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-
-#define REG_OK_FOR_BASE_P(X) \
-  (REGNO (X) < 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) (REGNO(X) < 16)
-
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) (REGNO(X) < 16)
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
-   except for CONSTANT_ADDRESS_P which is actually machine-independent.  */
-
-/* Non-zero if X is an address which can be indirected. */
-
-#define INDIRECTABLE_CONSTANT_ADDRESS_P(X) 0
-
-#define INDIRECTABLE_ADDRESS_P(X)  \
-  (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
-
-/* Go to ADDR if X is a valid address not using indexing.
-   (This much is the easy part.)  */
-
-#define GO_IF_NONINDEXED_ADDRESS(X, ADDR)	\
-{ if (CONSTANT_ADDRESS_P (X)) goto ADDR;	\
-  if (INDIRECTABLE_ADDRESS_P (X)) goto ADDR; }
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ register rtx xfoo = (X);			\
-  GO_IF_NONINDEXED_ADDRESS (xfoo, ADDR);	\
-  if (GET_CODE (xfoo) == PLUS)			\
-    { register rtx xfoo0, xfoo1;		\
-      xfoo0 = XEXP (xfoo, 0);			\
-      xfoo1 = XEXP (xfoo, 1);			\
-    /* handle reg + reg -> [r1](r0) */		\
-      if (INDIRECTABLE_ADDRESS_P (xfoo0) && INDIRECTABLE_ADDRESS_P (xfoo1)) \
-	goto ADDR;							\
-    /* Handle <symbol>(reg) -> xxx(r0) */				\
-      if (INDIRECTABLE_ADDRESS_P (xfoo0) && CONSTANT_ADDRESS_P (xfoo1))	\
-	goto ADDR;							\
-      if (INDIRECTABLE_ADDRESS_P (xfoo1) && CONSTANT_ADDRESS_P (xfoo0))	\
-	goto ADDR; }}
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the clipper, nothing needs to be done.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)  {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
-
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define this if the case instruction drops through after the table
-   when the index is out of range.  Don't define it if the case insn
-   jumps to the default label instead.  */
-/* #define CASE_DROPS_THROUGH */
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.  */
-#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.  */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 4
-
-/* If a memory-to-memory move would take MOVE_RATIO or more simple
-   move-instruction pairs, we will do a movstr or libcall instead.
-
-   Make this large on clipper, since the block move is very
-   inefficient with small blocks, and the hard register needs of the
-   block move require much reload work. */
-
-#define MOVE_RATIO 20
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* This machine uses IEEE floats.  */
-
-#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
-
-/* Check a `double' value for validity for a particular machine mode.
-   This is defined to avoid crashes outputting certain constants.
-   Since we output the number in hex, the assembler won't choke on it.  */
-/* #define CHECK_FLOAT_VALUE(MODE,VALUE) */
-
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-/* On a Clipper, constants from 0..15 are cheap because they can use the
-   'quick' mode. */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    if (0 <= INTVAL (RTX) && INTVAL(RTX) <= 15 ) return 0;	\
-      return 1;							\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 3;							\
-  case CONST_DOUBLE:						\
-    return 5;
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  */
-
-#define RTX_COSTS(X,CODE,OUTER_CODE)			\
-  case MULT:						\
-    return COSTS_N_INSNS (4);				\
-  case DIV:						\
-  case UDIV:						\
-  case MOD:						\
-  case UMOD:						\
-    return COSTS_N_INSNS (40);				\
-  case ASHIFT:						\
-  case LSHIFTRT:					\
-  case ASHIFTRT:					\
-    return COSTS_N_INSNS (2);				\
- case SIGN_EXTEND:					\
-    return (GET_CODE (XEXP (X,0)) == REG ? COSTS_N_INSNS (3) : 4);
-
-/* Specify the cost of a branch insn; roughly the number of extra insns that
-   should be added to avoid a branch */
-
-/* #define BRANCH_COST 0 */
-
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  No extra ones are needed for the clipper.  */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-{									      \
-  enum attr_cc cc = get_attr_cc (INSN);					      \
-  rtx dest = SET_DEST (EXP);						      \
-  switch (cc)								      \
-    {									      \
-    case CC_CHANGE0:							      \
-      if (GET_CODE (EXP) == PARALLEL) abort();				      \
-      if (cc_status.value1 && rtx_equal_p (dest, cc_status.value1) ||	      \
-	  cc_status.value2 && rtx_equal_p (dest, cc_status.value2))	      \
-	CC_STATUS_INIT;							      \
-      break;								      \
-									      \
-    case CC_SET1:							      \
-      if (GET_CODE (EXP) == PARALLEL) abort();				      \
-      cc_status.flags = 0;						      \
-      cc_status.value1 = dest;						      \
-      cc_status.value2 = 0;						      \
-      break;								      \
-									      \
-    case CC_SET2:							      \
-      if (GET_CODE (EXP) == PARALLEL) abort();				      \
-      cc_status.flags = 0;						      \
-      cc_status.value1 = dest;						      \
-      cc_status.value2 = SET_SRC (EXP);					      \
-      break;								      \
-									      \
-    case CC_UNCHANGED:							      \
-      break;								      \
-									      \
-    case CC_CLOBBER:							      \
-      CC_STATUS_INIT;							      \
-      break;								      \
-									      \
-    default:								      \
-      abort ();								      \
-    }									      \
-}
-
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(FILE) fprintf (FILE, "#NO_APP\n");
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", \
- "r9", "r10", "r11", "r12", "r13", "fp", "sp", \
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", \
- "f9", "f10", "f11", "f12", "f13", "f14", "f15" }
-
-/* How to renumber registers for dbx and gdb.
-   Clipper needs no change in the numeration.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tsubq   $8,sp\n\t%s  %s,(sp)\n",	\
-	   (REGNO) < 16 ? "storw" : "stord", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\t%s  (sp),%s\n\t\addq  $8,sp\n",	\
-	   (REGNO) < 16 ? "loadw" : "loadd", reg_names[REGNO])
-/* This is how to output an element of a case-vector that is absolute */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.long .L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter by SIZE bytes.  */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %u\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-/* ??? The use of .bss here seems odd.  */
-
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE,NAME,SIZE,ALIGN)	\
-( data_section (),					\
-  fputs ("\t.bss\t", (FILE)),				\
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN)/BITS_PER_UNIT))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print an instruction operand X on file FILE.
-   CODE is the code from the %-spec that requested printing this operand;
-   if `%z3' was used to print operand 3, then CODE is 'z'.
-
-Clipper operand formatting codes:
-
- letter	   print
-   C	reverse branch condition
-*/
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)				\
-  ((CODE) == 'C')
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ extern char *rev_cond_name ();					\
-  if (CODE == 'C')							\
-    fputs (rev_cond_name (X), FILE);					\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else { putc ('$', FILE); output_addr_const (FILE, X); }}
-
-/* Print a memory operand whose address is X, on file FILE.
-   This uses a function in output-clipper.c.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
- print_operand_address (FILE, ADDR)
-
-/* Define the codes that are matched by predicates in clipper.c */
-
-#define PREDICATE_CODES \
-  {"int_reg_operand", {SUBREG, REG}},	\
-  {"fp_reg_operand", {SUBREG, REG}},
diff --git a/gcc/config/clipper/clipper.md b/gcc/config/clipper/clipper.md
deleted file mode 100755
index 87f30fa..0000000
--- a/gcc/config/clipper/clipper.md
+++ /dev/null
@@ -1,1421 +0,0 @@
-;;- Machine description for GNU compiler, Clipper Version
-;;   Copyright (C) 1987, 88, 91, 93, 94, 1997 Free Software Foundation, Inc.
-;; Contributed by Holger Teutsch (holger@hotbso.rhein-main.de)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- Instruction patterns.  When multiple patterns apply,
-;;- the first one in the file is chosen.
-;;-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-;;-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-;;
-;; define attributes
-;;
-;; instruction type
-;;
-;; unknown is temporary in order to generate 'cc clobber' until attribute
-;; assignment is consistent
-;;
-(define_attr "type" "load,store,arith,fp,branch,unknown"
- (const_string "unknown"))
-
-;; condition code setting
-;;
-;; clobber	destroyed
-;; unchanged
-;; set1		set cc_status.value1, e.g. sub r0,r1
-;; set2		set value1 and value2, e.g. mov r0,r1
-;; change0	may be side effect, i.e. load mem,r0
-;;
-;; note: loadi and loadq are 'arith' instructions that set the condition codes
-;;       mul,div,mod do NOT set the condition codes
-;;
-(define_attr "cc" "clobber,unchanged,set1,set2,change0"
- (cond [(eq_attr "type" "load")	(const_string "change0")
-	(eq_attr "type" "store,branch") (const_string "unchanged")
-	(eq_attr "type" "arith") (if_then_else (match_operand:SI 0 "" "")
-				  (const_string "set1")
-				  (const_string "clobber"))
-	]
-  (const_string "clobber")))
-
-;;
-;; clipper seems to be a traditional risc processor
-;; we define a functional unit 'memory'
-;;
-(define_function_unit "memory" 1 1 (eq_attr "type" "load") 4 0)     
-
-
-;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
-;; be folded while optimizing anyway.
-
-(define_insn "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "int_reg_operand" "r"))]
-  ""
-  "cmpq   $0,%0")
-
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "r,r,n")
-		 (match_operand:SI 1 "nonmemory_operand" "r,n,r")))]
-  ""
-  "*
-{
-  int val;
-
-  if (which_alternative == 0)
-    return \"cmpw   %1,%0\";
-
-  if (which_alternative == 1)
-    {
-      val = INTVAL (operands[1]);
-      if (0 <= val && val < 16)
-	return \"cmpq   %1,%0\";
-      return \"cmpi   %1,%0\";
-    }
-
-  cc_status.flags |= CC_REVERSED;	/* immediate must be first */
-
-  val = INTVAL (operands[0]);
-
-  if (0 <= val && val < 16)
-    return \"cmpq   %0,%1\";
-
-  return \"cmpi   %0,%1\";
-}")
-
-(define_insn "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "fp_reg_operand" "f")
-		 (match_operand:DF 1 "fp_reg_operand" "f")))]
-  ""
-  "cmpd   %1,%0")
-
-(define_insn "cmpsf"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "fp_reg_operand" "f")
-		 (match_operand:SF 1 "fp_reg_operand" "f")))]
-  ""
-  "cmps   %1,%0")
-
-
-;;
-;; double and single float move
-;;
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	operands[1] = force_reg (DFmode,
-				 force_const_mem (DFmode, operands[1]));
-      else if (GET_CODE (operands[1]) != REG)
-	operands[1] = force_reg (DFmode, operands[1]);
-    }
-
-  else if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    operands[1] = force_const_mem (DFmode, operands[1]);
-}")
-
-;;
-;; provide two patterns with different predicates as we don't want combine
-;; to recombine a mem -> mem move
-;; 
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=*rf")
-	(match_operand:DF 1 "nonimmediate_operand" "*rfo"))]
-  ""
-  "*
-{
-#define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16)
-
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))	/* f -> f */
-	return \"movd   %1,%0\";
-
-      if (GET_CODE (operands[1]) == REG) /* r -> f */
-	return \"movld  %1,%0\";
-
-      return \"loadd  %1,%0\";		/* m -> f */
-    }
-
-  if (FP_REG_P (operands[1]))
-    {
-      if (GET_CODE (operands[0]) == REG) /* f -> r */
-	return \"movdl  %1,%0\";
-
-      abort ();
-    }
-
-  if (GET_CODE (operands[1]) == MEM)	/* m -> r */
-    {
-      rtx xops[4];
-      xops[0] = operands[0];
-      xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-      xops[2] = operands[1];
-      xops[3] = adj_offsettable_operand (operands[1], 4);
-      output_asm_insn (\"loadw  %2,%0\;loadw  %3,%1\", xops);
-      return \"\";
-    }
-
-  if (GET_CODE (operands[1]) == REG)	/* r -> r */
-    {
-      rtx xops[4];
-      xops[0] = operands[0];
-      xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-      xops[2] = operands[1];
-      xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-      output_asm_insn (\"movw   %2,%0\;movw   %3,%1\", xops);
-      return \"\";
-    }
-
-  abort ();
-#undef FP_REG_P
-}")
-
-
-(define_insn ""
-  [(set (match_operand:DF 0 "memory_operand" "=o,m")
-	(match_operand:DF 1 "register_operand" "*rf,f"))]
-  ""
-  "*
-{
-  rtx xops[4];
-
-  if (REGNO (operands[1]) >= 16)	/* f -> m */
-    return \"stord  %1,%0\";
-
-  xops[0] = operands[0];		/* r -> o */
-  xops[1] = adj_offsettable_operand (operands[0], 4);
-  xops[2] = operands[1];
-  xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-  output_asm_insn (\"storw  %2,%0\;storw  %3,%1\", xops);
-  return \"\";
-}"
-[(set_attr "type" "store,store")
- (set_attr "cc" "clobber,unchanged")])
-
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	operands[1] = force_reg (SFmode,
-				 force_const_mem (SFmode, operands[1]));
-      else if (GET_CODE (operands[1]) != REG)
-	operands[1] = force_reg (SFmode, operands[1]);
-    }
-
-  else if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    operands[1] = force_const_mem (SFmode, operands[1]);
-}")
-
-;;
-;; provide two patterns with different predicates as we don't want combine
-;; to recombine a mem -> mem move
-;; 
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=*rf")
-	(match_operand:SF 1 "nonimmediate_operand" "*rfm"))]
-  ""
-  "*
-{
-#define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16)
-
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))	/* f -> f */
-	return \"movs   %1,%0\";
-      if (GET_CODE (operands[1]) == REG) /* r -> f */
-	return
-	  \"subq   $8,sp\;storw  %1,(sp)\;loads  (sp),%0\;addq   $8,sp\";
-      return \"loads  %1,%0\";		/* m -> f */
-    }
-
-  if (FP_REG_P (operands[1]))
-    {
-      if (GET_CODE (operands[0]) == REG) /* f -> r */
-	return
-	  \"subq   $8,sp\;stors  %1,(sp)\;loadw  (sp),%0\;addq   $8,sp\";
-      abort ();
-    }
-
-  if (GET_CODE (operands[1]) == MEM)	/* m -> r */
-    return \"loadw   %1,%0\";
-
-  if (GET_CODE (operands[1]) == REG)	/* r -> r */
-    return \"movw    %1,%0\";
-
-  abort ();
-#undef FP_REG_P
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "memory_operand" "=m")
-	(match_operand:SF 1 "register_operand" "*rf"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) >= 16)
-    return \"stors  %1,%0\";		/* f-> m */
-
-  return \"storw   %1,%0\";		/* r -> m */
-}"
-[(set_attr "type" "store")])
-
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG)
-    operands[1] = force_reg (DImode, operands[1]);
-}")
-
-;; If an operand is a MEM but not offsettable, we can't load it into
-;; a register, so we must force the third alternative to be the one
-;; reloaded.  Hence we show the first as more expensive.
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=?r,r,r")
-	(match_operand:DI 1 "general_operand"   "r,n,o"))]
-  ""
-  "*
-{
-  rtx xoperands[2],yoperands[2];
-
-  xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-
-  if (which_alternative == 0)		/* r -> r */
-    {
-      output_asm_insn (\"movw   %1,%0\", operands);
-      xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-      output_asm_insn (\"movw   %1,%0\", xoperands);
-      return \"\";
-    }
-
-  if (which_alternative == 1)		/* n -> r */
-    {
-      if (GET_CODE (operands[1]) == CONST_INT)
-	{
-	  output_asm_insn (\"loadi   %1,%0\", operands);
-	  output_asm_insn (\"loadq   $0,%0\", xoperands);
-	  return \"\";
-	}
-
-      if (GET_CODE (operands[1]) != CONST_DOUBLE)
-	abort ();
-
-      yoperands[0] = operands[0];
-      yoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-      output_asm_insn (\"loadi  %1,%0\", yoperands);
-
-      xoperands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
-      output_asm_insn (\"loadi  %1,%0\", xoperands);
-      return \"\";
-    }
-					/* m -> r */
-  output_asm_insn (\"loadw  %1,%0\", operands);
-  xoperands[1] = adj_offsettable_operand (operands[1], 4);
-  output_asm_insn (\"loadw  %1,%0\", xoperands);
-  return \"\";
-}" 
-[(set_attr "type" "arith,arith,load")
-  (set_attr "cc" "clobber,clobber,clobber")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "memory_operand" "=o")
-	(match_operand:DI 1 "register_operand" "r"))]
-  ""
-  "*
-{
-  rtx xops[4];
-  xops[0] = operands[0];
-  xops[1] = adj_offsettable_operand (operands[0], 4);
-  xops[2] = operands[1];
-  xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-  output_asm_insn (\"storw  %2,%0\;storw  %3,%1\", xops);
-  return \"\";
-}"
-[(set_attr "type" "store")
- (set_attr "cc" "clobber")])
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM &&
-      GET_CODE (operands[1]) != REG)
-    operands[1] = force_reg (SImode, operands[1]);
-}")
-
-;; Reject both args with `general_operand' if not reloading because a
-;; mem -> mem move that was split by 'movsi' can be recombined to
-;; mem -> mem by the combiner.
-;;
-;; As a pseudo register can end up in a stack slot during reloading we must
-;; allow a r->m move for the next pattern. 
-;; The first predicate must be `general_operand' because a predicate must
-;; be true for each constraint.
-;;  
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,m")
-	(match_operand:SI 1 "general_operand"  "r,m,n,i,r"))]
-  "reload_in_progress || register_operand (operands[0], SImode)"
-  "*
-{
-  int val;
-
-  if (which_alternative == 0)
-    return \"movw   %1,%0\";		/* reg -> reg */
-
-  if (which_alternative == 1)
-    return \"loadw  %1,%0\";		/* mem -> reg */
-
-  if (which_alternative == 2)
-    {
-      val = INTVAL (operands[1]);	/* known const ->reg */
-
-      if (val == -1)
-	return \"notq   $0,%0\";
-
-      if (val < 0 || val >= 16)
-	return \"loadi  %1,%0\";
-
-      return \"loadq  %1,%0\";
-    }
-
-  if (which_alternative == 3)		/* unknown const */
-    return \"loada  %a1,%0\";
-
-  return \"storw  %1,%0\";
-}"
-[(set_attr "type" "arith,load,arith,load,store")
- (set_attr "cc" "set2,change0,set1,change0,unchanged")])
-
-
-(define_insn ""
-  [(set (match_operand:SI 0 "memory_operand" "=m")
-	(match_operand:SI 1 "int_reg_operand" "r"))]
-  ""
-  "storw  %1,%0"
-[(set_attr "type" "store")])
-
-;; movhi
-;;
-;; loadh  mem to reg
-;; storh  reg to mem
-;;
-;;
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM
-      && ! register_operand (operands[1], HImode))
-    operands[1] = force_reg (HImode, operands[1]);
-}")
-
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
-	(match_operand:HI 1 "general_operand"   "r,m,n"))]
-  ""
-  "@
-   movw   %1,%0
-   loadh  %1,%0
-   loadi  %1,%0"
-[(set_attr "type" "arith,load,arith")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "memory_operand"  "=m")
-	(match_operand:HI 1 "register_operand" "r"))]
-  ""
-  "storh  %1,%0"
- [(set_attr "type" "store")])
-
-;; movqi
-;;
-;; loadb  mem to reg
-;; storb  reg to mem
-;;
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM && 
-      ! register_operand (operands[1], QImode))
-    operands[1] = force_reg (QImode, operands[1]);
-}")
-
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r,r,r")
-	(match_operand:QI 1 "general_operand"   "r,m,n"))]
-  ""
-  "@
-   movw   %1,%0
-   loadb  %1,%0
-   loadi  %1,%0"
-[(set_attr "type" "arith,load,arith")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "memory_operand" "=m")
-	(match_operand:QI 1 "register_operand" "r"))]
-  ""
-  "storb  %1,%0"
-[(set_attr "type" "store")])
-
-
-;;
-;; block move
-;;
-(define_expand "movstrsi"
-  [(parallel
-    [(set (match_operand:BLK 0 "memory_operand" "")
-          (match_operand:BLK 1 "memory_operand" ""))
-     (use (match_operand:SI 2 "general_operand" ""))
-     (use (match_operand:SI 3 "const_int_operand" ""))
-     (clobber (match_scratch:SI 4 ""))
-     (clobber (match_scratch:SI 5 ""))
-     (clobber (match_dup 6))
-     (clobber (match_dup 7))])]
-  ""
-  "
-{
-  rtx addr0, addr1;
-
-  addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
-  addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
-
-  operands[6] = addr0;
-  operands[7] = addr1;
-
-  operands[0] = change_address (operands[0], VOIDmode, addr0);
-  operands[1] = change_address (operands[1], VOIDmode, addr1);
-
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = force_reg (SImode, operands[2]);
-}")
-
-;;
-;; there is a problem with this insn in gcc-2.2.3
-;; (clobber (match_dup 2)) does not prevent use of this operand later
-;; we always use a scratch register and leave operand 2 unchanged
-;;
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "r")))
-   (use (match_operand:SI 2 "nonmemory_operand" "rn"))
-   (use (match_operand:SI 3 "const_int_operand" "n"))
-   (clobber (match_scratch:SI 4 "=r"))
-   (clobber (match_scratch:SI 5 "=r"))
-   (clobber (match_dup 0))
-   (clobber (match_dup 1))]
-  ""
-  "*
-{
-  extern void clipper_movstr ();
-  clipper_movstr (operands);
-  return \"\";
-}"
-[(set_attr "cc" "clobber")])
-
-
-
-;; Extension and truncation insns.
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
-	(sign_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
-  ""
-  "@
-   andi   $65535,%0\;xori   $32768,%0\;subi   $32768,%0
-   loadh  %1,%0"
-[(set_attr "type" "arith,load")])
-
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "int_reg_operand" "=r,r")
-	(sign_extend:HI (match_operand:QI 1 "general_operand" "0,m")))]
-  ""
-  "@
-   andi   $255,%0\;xori   $128,%0\;subi   $128,%0
-   loadb  %1,%0"
-[(set_attr "type" "arith,load")
- (set_attr "cc" "set1,change0")])
-
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
-	(sign_extend:SI (match_operand:QI 1 "general_operand" "0,m")))]
-  ""
-  "@
-   andi   $255,%0\;xori   $128,%0\;subi   $128,%0
-   loadb  %1,%0"
-[(set_attr "type" "arith,load")])
-
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
-	(float_extend:DF (match_operand:SF 1 "fp_reg_operand" "f")))]
-  ""
-  "cnvsd  %1,%0")
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
-	(float_truncate:SF (match_operand:DF 1 "fp_reg_operand" "f")))]
-  ""
-  "cnvds  %1,%0")
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
-	(zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
-  ""
-  "@
-   andi   $65535,%0
-   loadhu %1,%0"
-[(set_attr "type" "arith,load")])
-
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "int_reg_operand" "=r,r")
-	(zero_extend:HI (match_operand:QI 1 "general_operand" "0,m")))]
-  ""
-  "@
-   andi   $255,%0
-   loadbu %1,%0"
-[(set_attr "type" "arith,load")
- (set_attr "cc" "clobber,clobber")])
-
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
-	(zero_extend:SI (match_operand:QI 1 "general_operand" "0,m")))]
-  ""
-  "@
-   andi   $255,%0
-   loadbu %1,%0"
-[(set_attr "type" "arith,load")])
-
-
-
-;; Fix-to-float conversion insns.
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
-	(float:SF (match_operand:SI 1 "int_reg_operand" "r")))]
-  ""
-  "cnvws  %1,%0")
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
-	(float:DF (match_operand:SI 1 "int_reg_operand" "r")))]
-  ""
-  "cnvwd  %1,%0")
-
-
-;; Float-to-fix conversion insns.
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" "f"))))]
-  ""
-  "cnvtsw %1,%0")
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(fix:SI (fix:DF (match_operand:DF 1 "fp_reg_operand" "f"))))]
-  ""
-  "cnvtdw %1,%0")
-
-;;- All kinds of add instructions.
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
-	(plus:DF (match_operand:DF 1 "fp_reg_operand" "0")
-		 (match_operand:DF 2 "fp_reg_operand" "f")))]
-  ""
-  "addd   %2,%0"
- [(set_attr "type" "fp")])
-
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
-	(plus:SF (match_operand:SF 1 "fp_reg_operand" "0")
-		 (match_operand:SF 2 "fp_reg_operand" "f")))]
-  ""
-  "adds   %2,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "int_reg_operand" "=r")
-	(plus:DI (match_operand:DI 1 "int_reg_operand" "%0")
-		 (match_operand:DI 2 "int_reg_operand" "r")))]
-  ""
-  "*
-{
-  rtx xoperands[4];
-
-  xoperands[0] = operands[0];
-  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  xoperands[2] = operands[2];
-  xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
-  output_asm_insn (\"addw   %2,%0\;addwc  %3,%1\", xoperands);
-  return \"\";
-}"
-[(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r,r,r")
-	(plus:SI (match_operand:SI 1 "int_reg_operand" "%0,r,r")
-		 (match_operand:SI 2 "nonmemory_operand" "rn,0,rn")))]
-  ""
-  "*
-{
-  if (which_alternative == 2)		/* 3 address version */
-    {
-      if (GET_CODE (operands[2]) == CONST_INT)
-	return \"loada  %a2(%1),%0\";
-      return \"loada  [%2](%1),%0\";
-    }
-					/* 2 address version */
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int val = INTVAL (operands[2]);
-
-      if (val >= 16 || val == 0x80000000)
-	return \"addi   %2,%0\";
-
-      if (val < 0)			/* change to sub */
-	{
-	  rtx xops[2];
-
-	  val = -val;
-
-	  xops[0] = operands[0];
-	  xops[1] = GEN_INT (val);
-
-	  if (val >= 16)
-	    output_asm_insn (\"subi   %1,%0\", xops);
-	  else
-	    output_asm_insn (\"subq   %1,%0\", xops);
-
-	  return \"\";
-	}
-
-      return \"addq   %2,%0\";
-    }
-
-  if (which_alternative == 0)
-    return \"addw   %2,%0\";
-
-  return \"addw   %1,%0\";
-}"
-[(set_attr "type" "arith,arith,arith")
- (set_attr "cc" "set1,set1,change0")])
-
-
-;;- All kinds of subtract instructions.
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "int_reg_operand" "=r")
-	(minus:DI (match_operand:DI 1 "int_reg_operand" "0")
-		  (match_operand:DI 2 "int_reg_operand" "r")))]
-  ""
-  "*
-{
-  rtx xoperands[4];
-
-  xoperands[0] = operands[0];
-  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  xoperands[2] = operands[2];
-  xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
-  output_asm_insn (\"subw   %2,%0\;subwc  %3,%1\", xoperands);
-  return \"\";
-}"
-[(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(minus:SI (match_operand:SI 1 "int_reg_operand" "0")
-		  (match_operand:SI 2 "nonmemory_operand" "rn")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int val = INTVAL (operands[2]);
-
-      if (val < 0 || val >= 16)
-	return \"subi   %2,%0\";
-      else
-	return \"subq   %2,%0\";
-    }
-
-  return \"subw   %2,%0\";
-}"
-[(set_attr "type" "arith")])
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
-	(minus:DF (match_operand:DF 1 "fp_reg_operand" "0")
-		  (match_operand:DF 2 "fp_reg_operand" "f")))]
-  ""
-  "subd   %2,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
-	(minus:SF (match_operand:SF 1 "fp_reg_operand" "0")
-		  (match_operand:SF 2 "fp_reg_operand" "f")))]
-  ""
-  "subs   %2,%0"
- [(set_attr "type" "fp")])
-
-
-;;- Multiply instructions.
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
-	(mult:DF (match_operand:DF 1 "fp_reg_operand" "0")
-		 (match_operand:DF 2 "fp_reg_operand" "f")))]
-  ""
-  "muld   %2,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
-	(mult:SF (match_operand:SF 1 "fp_reg_operand" "0")
-		 (match_operand:SF 2 "fp_reg_operand" "f")))]
-  ""
-  "muls   %2,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "mulsidi3"
-  [(set (match_operand:DI 0 "int_reg_operand" "=r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
-	         (sign_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
-  ""
-  "mulwx  %2,%0"
-[(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-
-(define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "int_reg_operand" "=r")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
-	         (zero_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
-  ""
-  "mulwux %2,%0"
-[(set_attr "type" "arith")
- (set_attr "cc" "clobber")])
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(mult:SI (match_operand:SI 1 "int_reg_operand" "%0")
-	         (match_operand:SI 2 "int_reg_operand" "r")))]
-  ""
-  "mulw   %2,%0"
- [(set_attr "type" "arith")
-  (set_attr "cc" "clobber")])
-
-
-;;- Divide and mod instructions.
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
-	(div:DF (match_operand:DF 1 "fp_reg_operand" "0")
-		(match_operand:DF 2 "fp_reg_operand" "f")))]
-  ""
-  "divd   %2,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
-	(div:SF (match_operand:SF 1 "fp_reg_operand" "0")
-		(match_operand:SF 2 "fp_reg_operand" "f")))]
-  ""
-  "divs   %2,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(div:SI (match_operand:SI 1 "int_reg_operand" "0")
-		(match_operand:SI 2 "int_reg_operand" "r")))]
-  ""
-  "divw   %2,%0"
- [(set_attr "type" "arith")
-  (set_attr "cc" "clobber")])
-
-(define_insn "udivsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(udiv:SI (match_operand:SI 1 "int_reg_operand" "0")
-	         (match_operand:SI 2 "int_reg_operand" "r")))]
-  ""
-  "divwu  %2,%0"
- [(set_attr "type" "arith")
-  (set_attr "cc" "clobber")])
-
-
-(define_insn "modsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(mod:SI (match_operand:SI 1 "int_reg_operand" "0")
-		(match_operand:SI 2 "int_reg_operand" "r")))]
-  ""
-  "modw   %2,%0"
- [(set_attr "type" "arith")
-  (set_attr "cc" "clobber")])
-
-(define_insn "umodsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(umod:SI (match_operand:SI 1 "int_reg_operand" "0")
-	         (match_operand:SI 2 "int_reg_operand" "r")))]
-  ""
-  "modwu  %2,%0"
- [(set_attr "type" "arith")
-  (set_attr "cc" "clobber")])
-
-;;
-;; bit and/or instructions
-;;
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
-        (and:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
-		(match_operand:SI 2 "nonmemory_operand" "r,n")))]
-  ""
-  "@
-   andw   %2,%0
-   andi   %2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
-	(ior:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
-	        (match_operand:SI 2 "nonmemory_operand" "r,n")))]
-  ""
-  "@
-   orw    %2,%0
-   ori    %2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
-	(xor:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
-		(match_operand:SI 2 "nonmemory_operand" "r,n")))]
-  ""
-  "@
-   xorw   %2,%0
-   xori   %2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "fp_reg_operand" "=f")
-	(neg:DF (match_operand:DF 1 "fp_reg_operand" "f")))]
-  ""
-  "negd   %1,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "fp_reg_operand" "=f")
-	(neg:SF (match_operand:SF 1 "fp_reg_operand" "f")))]
-  ""
-  "negs   %1,%0"
- [(set_attr "type" "fp")])
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(neg:SI (match_operand:SI 1 "int_reg_operand" "r")))]
-  ""
-  "negw   %1,%0"
- [(set_attr "type" "arith")])
-
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(not:SI (match_operand:SI 1 "int_reg_operand" "r")))]
-  ""
-  "notw   %1,%0"
- [(set_attr "type" "arith")])
-
-
-
-;; Right shift on the clipper works by negating the shift count,
-;; then emitting a right shift with the shift count negated.  This means
-;; that all actual shift counts in the RTL will be positive.
-
-(define_expand "ashrdi3"
-  [(set (match_operand:DI 0 "int_reg_operand" "")
-	(ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
-	             (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "int_reg_operand" "=r")
-	(ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "n")))]
-  ""
-  "shali  $%n2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "int_reg_operand" "=r")
-	(ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
-		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
-  ""
-  "shal   %2,%0"
- [(set_attr "type" "arith")])
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "")
-	(ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
-	             (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "n")))]
-  ""
-  "shai   $%n2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
-		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
-  ""
-  "shaw   %2,%0"
- [(set_attr "type" "arith")])
-
-;;
-;; left shift
-;;
-
-(define_insn "ashldi3"
-  [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
-	(ashift:DI (match_operand:DI 1 "int_reg_operand" "0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "r,n")))]
-  ""
-  "@
-   shal   %2,%0
-   shali  %2,%0"
- [(set_attr "type" "arith")])
-
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
-	(ashift:SI (match_operand:SI 1 "int_reg_operand" "0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "r,n")))]
-  ""
-  "*
-{
-  int val;
-
-  if (which_alternative == 0)
-   return \"shaw   %2,%0\";
-
-  val = INTVAL (operands[2]);
-
-  if (val == 2)
-    return \"addw   %0,%0\;addw   %0,%0\";
-
-  if (val == 1)
-    return \"addw   %0,%0\";
-
-  return \"shai   %2,%0\";
-}"
-[(set_attr "type" "arith")])
-
-;;
-;; logical shift
-;;
-
-(define_expand "lshrdi3"
-  [(set (match_operand:DI 0 "int_reg_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
-	             (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "int_reg_operand" "=r")
-	(lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "n")))]
-  ""
-  "shlli  $%n2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "int_reg_operand" "=r")
-	(lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
-		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
-  ""
-  "shll   %2,%0"
- [(set_attr "type" "arith")])
-
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "")
-	(lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
-	             (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "n")))]
-  ""
-  "shli   $%n2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
-		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
-  ""
-  "shlw   %2,%0"
- [(set_attr "type" "arith")])
-
-
-;;
-;; rotate insn
-;;
-(define_expand "rotrdi3"
-  [(set (match_operand:DI 0 "int_reg_operand" "")
-	(rotatert:DI (match_operand:DI 1 "int_reg_operand" "")
-	             (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "int_reg_operand" "=r")
-	(rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "n")))]
-  ""
-  "rotli  $%n2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "int_reg_operand" "=r")
-	(rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
-		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
-  ""
-  "rotl   %2,%0"
- [(set_attr "type" "arith")])
-
-(define_expand "rotrsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "")
-	(rotatert:SI (match_operand:SI 1 "int_reg_operand" "")
-	             (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(rotatert:SI (match_operand:SI 1 "int_reg_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "n")))]
-  ""
-  "roti   $%n2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "int_reg_operand" "=r")
-	(rotatert:SI (match_operand:SI 1 "int_reg_operand" "0")
-		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
-  ""
-  "rotw   %2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn "rotldi3"
-  [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
-	(rotate:DI (match_operand:DI 1 "int_reg_operand" "0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "r,n")))]
-  ""
-  "@
-   rotl   %2,%0
-   rotli  %2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn "rotlsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
-	(rotate:SI (match_operand:SI 1 "int_reg_operand" "0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "r,n")))]
-  ""
-  "@
-   rotw   %2,%0
-   roti   %2,%0"
- [(set_attr "type" "arith")])
-
-
-;;
-;; jump and branch insns
-;;
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "b      %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "b      (%0)"
- [(set_attr "type" "branch")])
-
-(define_insn "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "breq   %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "brne   %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "brgt   %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "brgtu  %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "brlt   %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "brltu  %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "brge   %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "brgeu  %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
- ""
- "brle   %l0"
- [(set_attr "type" "branch")])
-
-(define_insn "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
- ""
- "brleu  %l0"
- [(set_attr "type" "branch")])
-
-;; Recognize reversed jumps.
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
-				      [(cc0)
-				       (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 1 "" ""))))]
- ""
- "br%C0    %l1" ; %C0 negates condition
- [(set_attr "type" "branch")])
-
-;;
-;; call instructions
-;;
-(define_insn "call"
-  [(call (match_operand:QI 0 "general_operand" "m")
-	 (match_operand:SI 1 "general_operand" ""))]
-  ;; Operand 1 not used on the clipper.
-  ""
-  "call   sp,%0")
-
-(define_insn "call_value"
-  [(set (match_operand 0 "" "=rf")
-	(call (match_operand:QI 1 "general_operand" "m")
-	      (match_operand:SI 2 "general_operand" "g")))]
-  ;; Operand 2 not used on the clipper
-  ""
-  "call   sp,%1")
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
-  ""
-  "b      (%0)"
- [(set_attr "type" "branch")])
-
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "noop"
- [(set_attr "type" "arith")
-  (set_attr "cc" "unchanged")])
-
-
-
-;; while (--foo >= 0)
-;;
-;; Combiners for 'decrement test and branch' do not work for clipper.
-;; These patters are jump_insns that do not allow output reloads and clipper
-;; can only decrement and test registers.
-;;
diff --git a/gcc/config/clipper/clix.h b/gcc/config/clipper/clix.h
deleted file mode 100755
index c36e4de..0000000
--- a/gcc/config/clipper/clix.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Clipper/Clix version.
-   Copyright (C) 1988, 1993, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dclipper -Dunix -Asystem(unix) -Asystem(svr3) -Acpu(clipper) -Amachine(clipper)"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC  \
-  "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} crtbegin.o%s"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
-
-#undef LIB_SPEC
-
-#define TARGET_MEM_FUNCTIONS
-
-#undef HAVE_ATEXIT
-#define HAVE_ATEXIT
-
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)			\
-do {							\
-  unsigned char *s;					\
-  int i;						\
-  for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++)	\
-    {							\
-      if ((i % 8) == 0)					\
-	fputs ("\n\t.byte\t", (FILE));			\
-      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
-    }							\
-  fputs ("\n", (FILE));					\
-} while (0)
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)	\
-{					\
-  union { int i[2]; double d; } _d_;	\
-  _d_.d = VALUE;				\
-  fprintf (FILE, "\t.long 0x%08x,0x%08x\n", _d_.i[0],_d_.i[1]); \
-}
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)	\
-{					\
-  union { int i; float f; } _f_;	\
-  _f_.f = VALUE;				\
-  fprintf (FILE, "\t.long 0x%08x\n", _f_.i); \
-}
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
-  fprintf(FILE, "\t.align %d\n", 1 << (LOG))
-
-
-#define ASM_LONG ".long"
-#define BSS_SECTION_ASM_OP  ".bss"
-#undef INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP ".section .init,\"x\""
-
-
-/* Define a few machine-specific details of the implementation of
-   constructors.
-
-   The __CTORS_LIST__ goes in the .init section.  Define CTOR_LIST_BEGIN
-   and CTOR_LIST_END to contribute to the .init section an instruction to
-   push a word containing 0 (or some equivalent of that).
-
-   ASM_OUTPUT_CONSTRUCTOR should be defined to push the address of the
-   constructor.  */
-
-#define CTOR_LIST_BEGIN				\
-  asm (INIT_SECTION_ASM_OP);			\
-  asm ("subq   $8,sp");				\
-  asm ("loadq  $0,r0");				\
-  asm ("storw  r0,(sp)")
-
-/* don't need end marker */
-
-#undef CTOR_LIST_END
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)	\
-  do {						\
-    init_section ();				\
-    fputs ("\tloada  ", FILE);			\
-    assemble_name (FILE, NAME);			\
-    fputs (",r0\n\tsubq   $8,sp\n\tstorw   r0,(sp)\n", FILE);	\
-  } while (0)
-
-
-/* fini psect is 8 aligned */
-
-#define DTOR_LIST_BEGIN	\
-  asm (DTORS_SECTION_ASM_OP);				\
-  func_ptr __DTOR_LIST__[2] = { (func_ptr) (-1), 0 };
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-
-#undef ASM_OUTPUT_DESTRUCTOR
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    fini_section ();                   					\
-    fprintf (FILE, "%s\t ", ASM_LONG);					\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, ",0\n");						\
-  } while (0)
-
-
-/* On clix crt1.o first calls init code and then sets environ and a valid
-   chrclass. Unfortunately stdio routines bomb with unset chrclass.
-   Therefore we set chrclass prior to calling global constructors. */
-
-#undef DO_GLOBAL_CTORS_BODY
-#define DO_GLOBAL_CTORS_BODY					\
-do {								\
-  func_ptr *p, *beg = alloca (0);				\
-  _setchrclass (0);						\
-  for (p = beg; *p; p+=2)					\
-    ;								\
-  while (p != beg)						\
-    { p-= 2; (*p) (); }						\
-} while (0)
-
-
-#undef DO_GLOBAL_DTORS_BODY
-#define DO_GLOBAL_DTORS_BODY	\
-  func_ptr *f = &__DTOR_LIST__[2];	/* 0,1 contains -1,0 */	\
-  int n = 0;							\
-  while (*f)							\
-    {								\
-     f+= 2;				/* skip over alignment 0 */	\
-     n++;							\
-    }								\
-  f -= 2;							\
-  while (--n >= 0)						\
-    {								\
-     (*f) ();							\
-     f-= 2;				/* skip over alignment 0 */	\
-    }
-
-
diff --git a/gcc/config/clipper/x-clix b/gcc/config/clipper/x-clix
deleted file mode 100755
index 155161f..0000000
--- a/gcc/config/clipper/x-clix
+++ /dev/null
@@ -1 +0,0 @@
-ALLOCA = alloca.o
diff --git a/gcc/config/clipper/xm-clix.h b/gcc/config/clipper/xm-clix.h
deleted file mode 100755
index 726660d..0000000
--- a/gcc/config/clipper/xm-clix.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Config file for Clipper running Clix, system V. 3.2 clone  */
-
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-
-#include "tm.h"
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* This machine uses IEEE floats.  */
-/* #define HOST_FLOAT_FORMAT IEEE_FLOAT_FORMAT */
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* isinf isn't there, but finite is. */
-#define isinf(x) (!finite(x))
-
-#define USG
diff --git a/gcc/config/convex/convex.c b/gcc/config/convex/convex.c
deleted file mode 100755
index cd2eb55..0000000
--- a/gcc/config/convex/convex.c
+++ /dev/null
@@ -1,675 +0,0 @@
-/* Subroutines for insn-output.c for Convex.
-   Copyright (C) 1988, 1993, 1994, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include "tree.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "insn-attr.h"
-#include "output.h"
-#include "expr.h"
-
-/* Tables used in convex.h */
-
-char regno_ok_for_index_p_base[1 + LAST_VIRTUAL_REGISTER + 1];
-enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
-enum reg_class reg_class_from_letter[256];
-
-/* Target cpu index. */
-
-int target_cpu;
-
-/* Boolean to keep track of whether the current section is .text or not.
-   Used by .align handler in convex.h. */
-
-int current_section_is_text;
-
-/* Communication between output_compare and output_condjump. */
-
-static rtx cmp_operand0, cmp_operand1;
-static char cmp_modech;
-
-/* Forwards */
-
-static rtx frame_argblock;
-static int frame_argblock_size;
-static rtx convert_arg_pushes ();
-static void expand_movstr_call ();
-
-/* Here from OVERRIDE_OPTIONS at startup.  Initialize constant tables. */
-
-init_convex ()
-{
-  int regno;
-
-  /* Set A and S reg classes. */
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-    if (A_REGNO_P (regno))
-      {
-	regno_ok_for_index_p[regno] = 1;
-	regno_reg_class[regno] = INDEX_REGS;
-      }
-    else
-      {
-	regno_ok_for_index_p[regno] = 0;
-	regno_reg_class[regno] = S_REGS;
-      }
-
-  /* Can't index off the stack pointer, register 0. */
-  regno_ok_for_index_p[STACK_POINTER_REGNUM] = 0;
-  regno_reg_class[STACK_POINTER_REGNUM] = SP_REGS;
-
-  /* Can't index off aliases of the stack pointer.  */
-  regno_ok_for_index_p[VIRTUAL_INCOMING_ARGS_REGNUM] = 1;
-  regno_ok_for_index_p[VIRTUAL_STACK_VARS_REGNUM] = 1;
-  regno_ok_for_index_p[VIRTUAL_STACK_DYNAMIC_REGNUM] = 0;
-  regno_ok_for_index_p[VIRTUAL_OUTGOING_ARGS_REGNUM] = 0;
-
-  /* Can't index off hard reg -1 == pseudos not assigned */
-  regno_ok_for_index_p[-1] = 0;
-
-  /* Set reg class letters */
-  reg_class_from_letter['a'] = A_REGS;
-  reg_class_from_letter['A'] = INDEX_REGS;
-  reg_class_from_letter['d'] = S_REGS;
-
-  /* Turn off floating point exception enables in the psw. */
-  psw_disable_float ();
-}
-
-psw_disable_float ()
-{
-#if __convex__ && __GNUC__
-  register int *p;
-  asm ("mov fp,%0" : "=a" (p));
-  while (p)
-    {
-      p[1] &= ~0x1000c400;
-      p = (int *) p[2];
-    }
-#endif  
-}
-
-/* Here to output code for a compare insn.  Output nothing, just
-   record the operands and their mode. */
-
-char *
-output_cmp (operand0, operand1, modech)
-     rtx operand0, operand1;
-     char modech;
-{
-  cmp_operand0 = operand0;
-  cmp_operand1 = operand1;
-  cmp_modech = modech;
-  return "";
-}
-
-/* Output code for a conditional jump.  The preceding instruction
-   is necessarily a compare.  Output two instructions, for example
-       eq.w a1,a2
-       jbra.t L5
-   for
-       (cmpsi a1 a2)
-       (beq L5)
- */
-
-char *
-output_condjump (label, cond, jbr_sense)
-     rtx label;
-     char *cond;
-     char jbr_sense;
-{
-  rtx operands[3];
-  char cmp_op[4];
-  char buf[80];
-  char jbr_regch;
-
-  strcpy (cmp_op, cond);
-
-  /* [BL] mean the value is being compared against immediate 0.
-     Use neg.x, which produces the same carry that eq.x #0 would if it
-     existed.  In this case operands[1] is a scratch register, not a
-     compare operand. */
-
-  if (cmp_modech == 'B' || cmp_modech == 'L')
-    {
-      cmp_modech = cmp_modech - 'A' + 'a';
-      strcpy (cmp_op, "neg");
-    }
-
-  /* [WH] mean the value being compared resulted from "add.[wh] #-1,rk"
-     when rk was nonnegative -- we can omit equality compares against -1
-     or inequality compares against 0. */
-
-  else if (cmp_modech == 'W' || cmp_modech == 'H')
-    {
-      if (! strcmp (cmp_op, "eq") && cmp_operand1 == constm1_rtx)
-	jbr_sense ^= 't' ^ 'f';
-      else if (! strcmp (cmp_op, "lt") && cmp_operand1 == const0_rtx)
-	;
-      else
-	cmp_modech = cmp_modech - 'A' + 'a';
-    }
-
-  /* Constant must be first; swap operands if necessary.
-     If lt, le, ltu, leu are swapped, change to le, lt, leu, ltu
-     and reverse the sense of the jump. */
-
-  if (! REG_P (cmp_operand1))
-    {
-      operands[0] = cmp_operand1;
-      operands[1] = cmp_operand0;
-      if (cmp_op[0] == 'l')
-	{
-	  cmp_op[1] ^= 'e' ^ 't';
-	  jbr_sense ^= 't' ^ 'f';
-	}
-    }
-  else
-    {
-      operands[0] = cmp_operand0;
-      operands[1] = cmp_operand1;
-    }
-
-  operands[2] = label;
-
-  if (S_REG_P (operands[1]))
-    jbr_regch = 's';
-  else if (A_REG_P (operands[1]))
-    jbr_regch = 'a';
-  else
-    abort ();
-
-  if (cmp_modech == 'W' || cmp_modech == 'H')
-    sprintf (buf, "jbr%c.%c %%l2", jbr_regch, jbr_sense);
-  else
-    sprintf (buf, "%s.%c %%0,%%1\n\tjbr%c.%c %%l2",
-	     cmp_op, cmp_modech, jbr_regch, jbr_sense);
-  output_asm_insn (buf, operands);
-  return "";
-}
-
-/* Return 1 if OP is valid for cmpsf.
-   In IEEE mode, +/- zero compares are not handled by 
-     the immediate versions of eq.s and on some machines, lt.s, and le.s.  
-   So disallow 0.0 as the immediate operand of xx.s compares in IEEE mode. */
-
-int
-nonmemory_cmpsf_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-#if _IEEE_FLOAT_
-  if (op == CONST0_RTX (SFmode))
-    return 0;
-#endif
-
-  return nonmemory_operand (op, mode);
-}
-
-/* Convex /bin/as does not like unary minus in some contexts.
-   Simplify CONST addresses to remove it. */
-
-rtx
-simplify_for_convex (x)
-     rtx x;
-{
-  switch (GET_CODE (x))
-    {
-    case MINUS:
-      if (GET_CODE (XEXP (x, 1)) == CONST_INT
-	  && INTVAL (XEXP (x, 1)) < 0)
-	{
-	  PUT_CODE (x, PLUS);
-	  XEXP (x, 1) = GEN_INT (- INTVAL (XEXP (x, 1)));
-	}
-      break;
-
-    case CONST:
-      return simplify_for_convex (XEXP (x, 0));
-    }
-
-  return x;
-}
-
-/* Routines to separate CONST_DOUBLEs into component parts. */
-
-int
-const_double_high_int (x)
-     rtx x;
-{
-  if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
-    return CONST_DOUBLE_LOW (x);
-  else
-    return CONST_DOUBLE_HIGH (x);
-}
-
-int
-const_double_low_int (x)
-     rtx x;
-{
-  if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
-    return CONST_DOUBLE_HIGH (x);
-  else
-    return CONST_DOUBLE_LOW (x);
-}
-
-/* Inline block copy. */
-
-void
-expand_movstr (operands)
-     rtx *operands;
-{
-  rtx dest = operands[0];
-  rtx src = operands[1];
-  int align = INTVAL (operands[3]);
-  int nregs, maxsize;
-  unsigned len;
-  enum machine_mode mode;
-  rtx reg, load, store, prev_store, prev_store_2;
-  int size;
-
-  /* Decide how many regs to use, depending on load latency, and what
-     size pieces to move, depending on whether machine does unaligned
-     loads and stores efficiently. */
-
-  if (TARGET_C1)
-    {
-      /* ld.l latency is 4, no alignment problems. */
-      nregs = 3, maxsize = 8;
-    }
-  else if (TARGET_C2)
-    {
-      /* loads are latency 2 if we avoid ld.l not at least word aligned. */
-      if (align >= 4)
-	nregs = 2, maxsize = 8;
-      else
-	nregs = 2, maxsize = 4;
-    }
-  else if (TARGET_C34)
-    {
-      /* latency is 4 if aligned, horrible if not. */
-      nregs = 3, maxsize = align;
-    }
-  else if (TARGET_C38)
-    {
-      /* latency is 2 if at least word aligned, 3 or 4 if unaligned. */
-      if (align >= 4)
-	nregs = 2, maxsize = 8;
-      else
-	nregs = 3, maxsize = 8;
-    }
-  else
-    abort ();
-
-  /* Caller is not necessarily prepared for us to fail in this
-     expansion.  So fall back by generating memcpy call here. */
-
-  if (GET_CODE (operands[2]) != CONST_INT
-      || (len = INTVAL (operands[2])) > (unsigned) 32 * maxsize)
-    {
-      expand_movstr_call (operands);
-      return;
-    }
-
-  reg = 0;
-  prev_store = prev_store_2 = 0;
-
-  while (len > 0)
-    {
-      if (len >= 8 && maxsize >= 8)
-	mode = DImode;
-      else if (len >= 4 && maxsize >= 4)
-	mode = SImode;
-      else if (len >= 2 && maxsize >= 2)
-	mode = HImode;
-      else
-	mode = QImode;
-
-      /* If no temp pseudo to reuse, or not the right mode, make one */
-      if (! reg || GET_MODE (reg) != mode)
-	reg = gen_reg_rtx (mode);
-
-      /* Get src and dest in the right mode */
-      if (GET_MODE (src) != mode)
-	src = change_address (src, mode, 0),
-	dest = change_address (dest, mode, 0);
-
-      /* Make load and store patterns for this piece */
-      load = gen_rtx (SET, VOIDmode, reg, src);
-      store = gen_rtx (SET, VOIDmode, dest, reg);
-
-      /* Emit the load and the store from last time. 
-	 When we emit a store, we can reuse its temp reg. */
-      emit_insn (load);
-      if (prev_store)
-	{
-	  reg = SET_SRC (prev_store);
-	  emit_insn (prev_store);
-	}
-      else
-	reg = 0;
-
-      /* Queue up the store, for next time or the time after that. */
-      if (nregs == 2)
-	prev_store = store;
-      else
-	prev_store = prev_store_2, prev_store_2 = store;
-
-      /* Advance to next piece. */
-      size = GET_MODE_SIZE (mode);
-      src = adj_offsettable_operand (src, size);
-      dest = adj_offsettable_operand (dest, size);
-      len -= size;
-    }
-
-  /* Finally, emit the last stores. */
-  if (prev_store)
-    emit_insn (prev_store);
-  if (prev_store_2)
-    emit_insn (prev_store_2);
-}
-
-static void
-expand_movstr_call (operands)
-     rtx *operands;
-{
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
-		     VOIDmode, 3,
-		     XEXP (operands[0], 0), Pmode,
-		     XEXP (operands[1], 0), Pmode,
-		     convert_to_mode (TYPE_MODE (sizetype), operands[2],
-				      TREE_UNSIGNED (sizetype)),
-		     TYPE_MODE (sizetype));
-}
-
-#if _IEEE_FLOAT_
-#define MAX_FLOAT 3.4028234663852886e+38
-#define MIN_FLOAT 1.1754943508222875e-38
-#else
-#define MAX_FLOAT 1.7014117331926443e+38
-#define MIN_FLOAT 2.9387358770557188e-39
-#endif
-
-int
-check_float_value (mode, dp, overflow)
-     enum machine_mode mode;
-     REAL_VALUE_TYPE *dp;
-     int overflow;
-{
-  REAL_VALUE_TYPE d = *dp;
-
-  if (overflow)
-    {
-      *dp = MAX_FLOAT;
-      return 1;
-    }
-
-  if (mode == SFmode)
-    {
-      if (d > MAX_FLOAT)
-	{
-	  *dp = MAX_FLOAT;
-	  return 1;
-	}
-      else if (d < -MAX_FLOAT)
-	{
-	  *dp = -MAX_FLOAT;
-	  return 1;
-	}	
-      else if ((d > 0 && d < MIN_FLOAT) || (d < 0 && d > -MIN_FLOAT))
-	{
-	  *dp = 0.0;
-	  return 1;
-	}
-    }
-
-  return 0;
-}
-
-/* Output the label at the start of a function.
-   Precede it with the number of formal args so debuggers will have
-   some idea of how many args to print. */
-
-void
-asm_declare_function_name (file, name, decl)
-    FILE *file;
-    char *name;
-    tree decl;
-{
-  tree parms;
-  int nargs = list_length (DECL_ARGUMENTS (decl));
-
-  char *p, c;
-  extern char *version_string;
-  static char vers[4];
-  int i;
-  
-  p = version_string;
-  for (i = 0; i < 3; ) {
-    c = *p;
-    if (c - '0' < (unsigned) 10)
-      vers[i++] = c;
-    if (c == 0 || c == ' ')
-      vers[i++] = '0';
-    else
-      p++;
-  }
-  fprintf (file, "\tds.b \"g%s\"\n", vers);
-
-  if (nargs < 100)
-    fprintf (file, "\tds.b \"+%02d\\0\"\n", nargs);
-  else
-    fprintf (file, "\tds.b \"+00\\0\"\n");
-
-  ASM_OUTPUT_LABEL (file, name);
-}
-
-/* Print an instruction operand X on file FILE.
-   CODE is the code from the %-spec that requested printing this operand;
-   if `%z3' was used to print operand 3, then CODE is 'z'. */
-/* Convex codes:
-    %u prints a CONST_DOUBLE's high word
-    %v prints a CONST_DOUBLE's low word
-    %z prints a CONST_INT shift count as a multiply operand -- viz. 1 << n.
- */
-
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     char code;
-{
-  long u[2];
-  REAL_VALUE_TYPE d;
-
-  switch (GET_CODE (x))
-    {
-    case REG:
-      fprintf (file, "%s", reg_names[REGNO (x)]);
-      break;
-
-    case MEM:
-      output_address (XEXP (x, 0));
-      break;
-
-    case CONST_DOUBLE:
-      REAL_VALUE_FROM_CONST_DOUBLE (d, x);
-      switch (GET_MODE (x)) {
-      case DFmode:
-#if 0 /* doesn't work, produces dfloats */
-	REAL_VALUE_TO_TARGET_DOUBLE (d, u); 
-#else
-	{
-	  union { double d; int i[2]; } t;
-	  t.d = d;
-	  u[0] = t.i[0];
-	  u[1] = t.i[1];
-	}
-#endif
-	if (code == 'u')
-	  fprintf (file, "#%#x", u[0]);
-	else if (code == 'v')
-	  fprintf (file, "#%#x", u[1]);
-	else
-	  outfloat (file, d, "%.17e", "#", "");
-	break;
-      case SFmode:
-	outfloat (file, d, "%.9e", "#", "");
-	break;
-      default:
-	if (code == 'u')
-	  fprintf (file, "#%d", CONST_DOUBLE_HIGH (x));
-	else
-	  fprintf (file, "#%d", CONST_DOUBLE_LOW (x));
-      }
-      break;
-
-    default:
-      if (code == 'z')
-	{
-	  if (GET_CODE (x) != CONST_INT)
-	    abort ();
-	  fprintf (file, "#%d", 1 << INTVAL (x));
-	}
-      else
-	{
-	  putc ('#', file);
-	  output_addr_const (file, x);
-	}
-    }
-}
-
-/* Print a memory operand whose address is X, on file FILE. */
-
-print_operand_address (file, addr)
-     FILE *file;
-     rtx addr;
-{
-  rtx index = 0;
-  rtx offset = 0;
-
-  if (GET_CODE (addr) == MEM)
-    {
-      fprintf (file, "@");
-      addr = XEXP (addr, 0);
-    }
-
-  switch (GET_CODE (addr))
-    {
-    case REG:
-      index = addr;
-      break;
-
-    case PLUS:
-      index = XEXP (addr, 0);
-      if (REG_P (index))
-	offset = XEXP (addr, 1);
-      else
-	{
-	  offset = XEXP (addr, 0);
-	  index = XEXP (addr, 1);
-	  if (! REG_P (index))
-	    abort ();
-        }
-      break;
-
-    default:
-      offset = addr;
-      break;
-    }
-
-  if (offset)
-    output_addr_const (file, offset);
-
-  if (index)
-    fprintf (file, "(%s)", reg_names[REGNO (index)]);
-}
-
-/* Output a float to FILE, value VALUE, format FMT, preceded by PFX
-   and followed by SFX. */
-
-outfloat (file, value, fmt, pfx, sfx)
-     FILE *file;
-     REAL_VALUE_TYPE value;
-     char *fmt, *pfx, *sfx;
-{
-  char buf[64];
-  fputs (pfx, file);
-  REAL_VALUE_TO_DECIMAL (value, fmt, buf);
-  fputs (buf, file);
-  fputs (sfx, file);
-}
-
-/* Here during RTL generation of return.  If we are at the final return
-   in a function, go through the function and replace pushes with stores
-   into a frame arg block.  This is similar to what ACCUMULATE_OUTGOING_ARGS
-   does, but we must index off the frame pointer, not the stack pointer,
-   and the calling sequence does not require the arg block to be at the
-   top of the stack.  */
-
-replace_arg_pushes ()
-{
-  /* Doesn't work yet. */
-}
-
-/* Output the insns needed to do a call.  operands[] are
-     0 - MEM, the place to call
-     1 - CONST_INT, the number of bytes in the arg list
-     2 - CONST_INT, the number of arguments
-     3 - CONST_INT, the number of bytes to pop
-     4 - address of the arg list.  
- */
-
-char *
-output_call (insn, operands)
-     rtx insn, *operands;
-{
-  if (operands[4] == stack_pointer_rtx)
-    output_asm_insn ("mov sp,ap", operands);
-  else
-    abort ();
-
-  if (TARGET_ARGCOUNT)
-    output_asm_insn ("pshea %a2", operands);
-
-  output_asm_insn ("calls %0", operands);
-
-  output_asm_insn ("ld.w 12(fp),ap", operands);
-
-  if (operands[4] == stack_pointer_rtx && operands[3] != const0_rtx)
-    output_asm_insn ("add.w %3,sp", operands);
-
-  return "";
-}
-
-
-/* Here after reloading, before the second scheduling pass. */
-
-emit_ap_optimizations ()
-{
-  /* Removed for now. */
-}
-
diff --git a/gcc/config/convex/convex.h b/gcc/config/convex/convex.h
deleted file mode 100755
index f455f96..0000000
--- a/gcc/config/convex/convex.h
+++ /dev/null
@@ -1,1503 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Convex version.
-   Copyright (C) 1988, 1994, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Standard GCC variables that we reference. */
-
-extern int target_flags;
-
-/* Convex machine-specific flags
-   -mc1		      target instruction set, libraries, scheduling 
-   -mc2	
-   -mc32
-   -mc34
-   -mc38
-   -margcount	      use standard calling sequence, with arg count word
-   -mno-argcount      don't push arg count, depend on symbol table
-   -margcount-nop     place arg count in a nop instruction (faster than push)
-   -mvolatile-cache   use data cache for volatile mem refs (default)
-   -mvolatile-nocache  bypass data cache for volatile mem refs
-   -mlong32	      cc- and libc-compatible 32-bit longs
-   -mlong64	      64-bit longs
-*/
-
-/* Macro to define tables used to set -mXXX flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 0
-#endif
-
-#define TARGET_SWITCHES \
-  { { "c1", 001 }, 	\
-    { "c2", 002 },	\
-    { "c32", 004 },	\
-    { "c34", 010 },	\
-    { "c38", 020 },	\
-    { "argcount", 0100 }, \
-    { "argcount-nop", 0200 }, \
-    { "no-argcount", -0300 }, \
-    { "volatile-cache", -0400 }, \
-    { "no-volatile-cache", 0400 }, \
-    { "volatile-nocache", 0400 }, \
-    { "long64", 01000 }, \
-    { "long32", -01000 }, \
-    { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}}
-
-/* Macros used in the machine description to test the flags.  */
-
-#define TARGET_C1 (target_cpu == 0)
-#define TARGET_C2 (target_cpu == 1)
-#define TARGET_C34 (target_cpu == 2)
-#define TARGET_C38 (target_cpu == 3)
-#define TARGET_ARGCOUNT (target_flags & 0100)
-#define TARGET_ARGCOUNT_NOP (target_flags & 0200)
-#define TARGET_LONG64 (target_flags & 01000)
-#define TARGET_VOLATILE_NOCACHE (target_flags & 0400)
-
-#define OVERRIDE_OPTIONS						\
-{									\
-  init_convex ();							\
-  if ((target_flags & 077) != ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 077)) \
-    target_flags &= ~ (TARGET_DEFAULT | TARGET_CPU_DEFAULT);		\
-  if (target_flags & 001)						\
-    target_cpu = 0;							\
-  else if (target_flags & 006)						\
-    target_cpu = 1;							\
-  else if (target_flags & 010)						\
-    target_cpu = 2;							\
-  else if (target_flags & 020)						\
-    target_cpu = 3;							\
-}
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dconvex -Dunix -Asystem(unix) -Acpu(convex) -Amachine(convex)"
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fprintf (stderr, " (convex)");
-
-/* Target-dependent specs.
-   Some libraries come in c1 and c2+ versions; use the appropriate ones.
-   Make a target-dependent __convex_cxx__ define to relay the target cpu
-   to the program being compiled. */
-
-#if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 1
-
-/* C1 default */
-
-#if _IEEE_FLOAT_
-
-#define CPP_SPEC							\
-"%{!mc2:%{!mc32:%{!mc34:%{!mc38:-D__convex_c1__}}}}			\
- %{mc2:-D__convex_c2__}							\
- %{mc32:-D__convex_c32__}						\
- %{mc34:-D__convex_c34__}						\
- %{mc38:-D__convex_c38__}						\
- %{fno-builtin:-D__NO_INLINE}						\
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB				\
- -D_IEEE_FLOAT_								\
- %{.S:-P}								\
- %{!traditional:-D__stdc__}						\
- %{!traditional:-D_LONGLONG}						\
- %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long}	\
- %{!ansi:-D_POSIX_SOURCE}						\
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#else
-
-#define CPP_SPEC							\
-"%{!mc2:%{!mc32:%{!mc34:%{!mc38:-D__convex_c1__}}}}			\
- %{mc2:-D__convex_c2__}							\
- %{mc32:-D__convex_c32__}						\
- %{mc34:-D__convex_c34__}						\
- %{mc38:-D__convex_c38__}						\
- %{fno-builtin:-D__NO_INLINE}						\
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB				\
- -D_CONVEX_FLOAT_							\
- %{.S:-P}								\
- %{!traditional:-D__stdc__}						\
- %{!traditional:-D_LONGLONG}						\
- %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long}	\
- %{!ansi:-D_POSIX_SOURCE}						\
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#endif
-
-#define LIB_SPEC							\
-"%{!mc2:%{!mc32:%{!mc34:%{!mc38:-lC1%{traditional:_old}%{p:_p}%{pg:_p}}}}} \
- %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- -lc%{traditional:_old}%{p:_p}%{pg:_p}"
-
-#endif
-
-#if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 2
-
-/* C2 default */
-
-#if _IEEE_FLOAT_
-
-#define CPP_SPEC							\
-"%{mc1:-D__convex_c1__}							\
- %{!mc1:%{!mc32:%{!mc34:%{!mc38:-D__convex_c2__}}}}			\
- %{mc32:-D__convex_c32__}						\
- %{mc34:-D__convex_c34__}						\
- %{mc38:-D__convex_c38__}						\
- %{fno-builtin:-D__NO_INLINE}						\
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB				\
- -D_IEEE_FLOAT_								\
- %{.S:-P}								\
- %{!traditional:-D__stdc__}						\
- %{!traditional:-D_LONGLONG}						\
- %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long}	\
- %{!ansi:-D_POSIX_SOURCE}						\
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#else
-
-#define CPP_SPEC							\
-"%{mc1:-D__convex_c1__}							\
- %{!mc1:%{!mc32:%{!mc34:%{!mc38:-D__convex_c2__}}}}			\
- %{mc32:-D__convex_c32__}						\
- %{mc34:-D__convex_c34__}						\
- %{mc38:-D__convex_c38__}						\
- %{fno-builtin:-D__NO_INLINE}						\
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB				\
- -D_CONVEX_FLOAT_							\
- %{.S:-P}								\
- %{!traditional:-D__stdc__}						\
- %{!traditional:-D_LONGLONG}						\
- %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long}	\
- %{!ansi:-D_POSIX_SOURCE}						\
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#endif
-
-#define LIB_SPEC							\
-"%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{!mc1:%{!mc32:%{!mc34:%{!mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \
- %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- -lc%{traditional:_old}%{p:_p}%{pg:_p}"
-
-#endif
-
-#if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 4
-
-/* C32 default */
-
-#if _IEEE_FLOAT_
-
-#define CPP_SPEC							\
-"%{mc1:-D__convex_c1__}							\
- %{mc2:-D__convex_c2__}							\
- %{!mc1:%{!mc2:%{!mc34:%{!mc38:-D__convex_c32__}}}}			\
- %{mc34:-D__convex_c34__}						\
- %{mc38:-D__convex_c38__}						\
- %{fno-builtin:-D__NO_INLINE}						\
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB				\
- -D_IEEE_FLOAT_								\
- %{.S:-P}								\
- %{!traditional:-D__stdc__}						\
- %{!traditional:-D_LONGLONG}						\
- %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long}	\
- %{!ansi:-D_POSIX_SOURCE}						\
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#else
-
-#define CPP_SPEC							\
-"%{mc1:-D__convex_c1__}							\
- %{mc2:-D__convex_c2__}							\
- %{!mc1:%{!mc2:%{!mc34:%{!mc38:-D__convex_c32__}}}}			\
- %{mc34:-D__convex_c34__}						\
- %{mc38:-D__convex_c38__}						\
- %{fno-builtin:-D__NO_INLINE}						\
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB				\
- -D_CONVEX_FLOAT_							\
- %{.S:-P}								\
- %{!traditional:-D__stdc__}						\
- %{!traditional:-D_LONGLONG}						\
- %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long}	\
- %{!ansi:-D_POSIX_SOURCE}						\
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#endif
-
-#define LIB_SPEC							\
-"%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{!mc1:%{!mc2:%{!mc34:%{!mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \
- %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- -lc%{traditional:_old}%{p:_p}%{pg:_p}"
-
-#endif
-
-#if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 010
-
-/* C34 default */
-
-#if _IEEE_FLOAT_
-
-#define CPP_SPEC							\
-"%{mc1:-D__convex_c1__}							\
- %{mc2:-D__convex_c2__}							\
- %{mc32:-D__convex_c32__}						\
- %{!mc1:%{!mc2:%{!mc32:%{!mc38:-D__convex_c34__}}}}			\
- %{mc38:-D__convex_c38__}						\
- %{fno-builtin:-D__NO_INLINE}						\
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB				\
- -D_IEEE_FLOAT_								\
- %{.S:-P}								\
- %{!traditional:-D__stdc__}						\
- %{!traditional:-D_LONGLONG}						\
- %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long}	\
- %{!ansi:-D_POSIX_SOURCE}						\
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#else
-
-#define CPP_SPEC							\
-"%{mc1:-D__convex_c1__}							\
- %{mc2:-D__convex_c2__}							\
- %{mc32:-D__convex_c32__}						\
- %{!mc1:%{!mc2:%{!mc32:%{!mc38:-D__convex_c34__}}}}			\
- %{mc38:-D__convex_c38__}						\
- %{fno-builtin:-D__NO_INLINE}						\
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB				\
- -D_CONVEX_FLOAT_							\
- %{.S:-P}								\
- %{!traditional:-D__stdc__}						\
- %{!traditional:-D_LONGLONG}						\
- %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long}	\
- %{!ansi:-D_POSIX_SOURCE}						\
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#endif
-
-#define LIB_SPEC							\
-"%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{!mc1:%{!mc2:%{!mc32:%{!mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \
- %{mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- -lc%{traditional:_old}%{p:_p}%{pg:_p}"
-
-#endif
-
-#if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 020
-
-/* C38 default */
-
-#if _IEEE_FLOAT_
-
-#define CPP_SPEC							\
-"%{mc1:-D__convex_c1__}							\
- %{mc2:-D__convex_c2__}							\
- %{mc32:-D__convex_c32__}						\
- %{mc34:-D__convex_c34__}						\
- %{fno-builtin:-D__NO_INLINE}						\
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB				\
- -D_IEEE_FLOAT_								\
- %{!mc1:%{!mc2:%{!mc32:%{!mc34:-D__convex_c38__}}}}			\
- %{.S:-P}								\
- %{!traditional:-D__stdc__}						\
- %{!traditional:-D_LONGLONG}						\
- %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long}	\
- %{!ansi:-D_POSIX_SOURCE}						\
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#else
-
-#define CPP_SPEC							\
-"%{mc1:-D__convex_c1__}							\
- %{mc2:-D__convex_c2__}							\
- %{mc32:-D__convex_c32__}						\
- %{mc34:-D__convex_c34__}						\
- %{fno-builtin:-D__NO_INLINE}						\
- -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB				\
- -D_CONVEX_FLOAT_							\
- %{!mc1:%{!mc2:%{!mc32:%{!mc34:-D__convex_c38__}}}}			\
- %{.S:-P}								\
- %{!traditional:-D__stdc__}						\
- %{!traditional:-D_LONGLONG}						\
- %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long}	\
- %{!ansi:-D_POSIX_SOURCE}						\
- %{!ansi:-D_CONVEX_SOURCE}"
-
-#endif
-
-#define LIB_SPEC							\
-"%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
- %{!mc1:%{!mc2:%{!mc32:%{!mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \
- -lc%{traditional:_old}%{p:_p}%{pg:_p}"
-
-#endif
-
-#if _IEEE_FLOAT_
-
-/* ieee default */
-
-#define ASM_SPEC "-fi"
-
-#define LINK_SPEC							\
-"-E%{traditional:no}posix						\
- -X									\
- %{F} %{M*} %{y*}							\
- -fi									\
- -A__iob=___ap$iob							\
- -A_use_libc_sema=___ap$use_libc_sema					\
- %{traditional:-A___gcc_cleanup=__cleanup}				\
- %{!traditional:-A___gcc_cleanup=___ap$do_registered_functions}		\
- -L/usr/lib"
-
-#define STARTFILE_SPEC							\
-"%{!pg:%{!p:/usr/lib/crt/crt0.o}}					\
- %{!pg:%{p:/usr/lib/crt/mcrt0.o}}					\
- %{pg:/usr/lib/crt/gcrt0.o}						\
- /usr/lib/crt/fpmode_i.o"
-
-#else
-
-/* native default */
-
-#define ASM_SPEC "-fn"
-
-#define LINK_SPEC							\
-"-E%{traditional:no}posix						\
- -X									\
- %{F} %{M*} %{y*}							\
- -fn									\
- -A__iob=___ap$iob							\
- -A_use_libc_sema=___ap$use_libc_sema					\
- %{traditional:-A___gcc_cleanup=__cleanup}				\
- %{!traditional:-A___gcc_cleanup=___ap$do_registered_functions}		\
- -L/usr/lib"
-
-#define STARTFILE_SPEC							\
-"%{!pg:%{!p:/usr/lib/crt/crt0.o}}					\
- %{!pg:%{p:/usr/lib/crt/mcrt0.o}}					\
- %{pg:/usr/lib/crt/gcrt0.o}"
-
-#endif
-
-/* Use /path/libgcc.a instead of -lgcc, makes bootstrap work more smoothly. */
-
-#define LINK_LIBGCC_SPECIAL_1
-
-/* Since IEEE support was added to gcc, most things seem to like it
-   better if we disable exceptions and check afterward for infinity. */
-
-#if __convex__
-#if _IEEE_FLOAT_
-#define REAL_VALUE_ISNAN(x) 0
-#define REAL_VALUE_ISINF(x) ((*(short *) &(x) & 0x7ff0) == 0x7ff0)
-#else
-#define REAL_VALUE_ISNAN(x) 0
-#define REAL_VALUE_ISINF(x) ((*(short *) &(x) & 0xfff0) == 0x8000)
-#endif
-#endif
-
-/* Target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields. */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is numbered.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 64
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 8
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 64
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 16
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* No data type wants to be aligned rounder than this.  */
-/* beware of doubles in structs -- 64 is incompatible with cc */
-#define BIGGEST_ALIGNMENT 32
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 0
-
-/* Define sizes of basic C types to conform to ordinary usage -- these
-   types depend on BITS_PER_WORD otherwise.  */
-#define CHAR_TYPE_SIZE		8
-#define SHORT_TYPE_SIZE		16
-#define INT_TYPE_SIZE		32
-#define LONG_TYPE_SIZE		(TARGET_LONG64 ? 64 : 32)
-#define LONG_LONG_TYPE_SIZE	64
-#define FLOAT_TYPE_SIZE		32
-#define DOUBLE_TYPE_SIZE	64
-#define LONG_DOUBLE_TYPE_SIZE	64
-/* This prevents cexp.c from depending on LONG_TYPE_SIZE.  */
-#define MAX_LONG_TYPE_SIZE      64
-
-/* Declare the standard types used by builtins to match convex stddef.h --
-   with int rather than long.  */
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  */
-#define FIRST_PSEUDO_REGISTER 16
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   For Convex, these are AP, FP, and SP.  */
-#define FIXED_REGISTERS \
-  { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1 }
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS \
-  { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
-
-/* List the order in which to allocate registers.  Each register must be
-   listed once, even those in FIXED_REGISTERS.
-   For Convex, put S0 (the return register) last. */
-#define REG_ALLOC_ORDER \
-  { 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 0, 8, 14, 15 }
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers. */
-#define HARD_REGNO_NREGS(REGNO, MODE) \
-   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On Convex, S registers can hold any type, A registers any nonfloat. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-  (S_REGNO_P (REGNO)							\
-   || (GET_MODE_SIZE (MODE) <= 4 && (MODE) != SFmode))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2)  \
-  ((GET_MODE_SIZE (MODE1) <= 4 && (MODE1) != SFmode)			\
-   == (GET_MODE_SIZE (MODE2) <= 4 && (MODE2) != SFmode))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-#define S0_REGNUM 0
-#define A0_REGNUM 8
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM A0_REGNUM
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM (A0_REGNUM + 7)
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 1
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM (A0_REGNUM + 6)
-
-/* Register in which static-chain is passed to a function.
-   Use S0, not an A reg, because this rare use would otherwise prevent
-   an A reg from being available to global-alloc across calls.  */
-#define STATIC_CHAIN_REGNUM S0_REGNUM
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM (A0_REGNUM + 1)
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-/* Convex has classes A (address) and S (scalar).
-   A is further divided into SP_REGS (stack pointer) and INDEX_REGS.
-   SI_REGS is S_REGS + INDEX_REGS -- all the regs except SP. */
-
-enum reg_class {
-  NO_REGS, S_REGS, INDEX_REGS, SP_REGS, A_REGS, SI_REGS,
-  ALL_REGS, LIM_REG_CLASSES 
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Since GENERAL_REGS is the same class as ALL_REGS,
-   don't give it a different class number; just make it an alias.  */
-
-#define GENERAL_REGS ALL_REGS
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "S_REGS", "INDEX_REGS", "SP_REGS", "A_REGS", "SI_REGS", \
-  "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS \
-  { 0, 0x00ff, 0xfe00, 0x0100, 0xff00, 0xfeff, 0xffff }
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) (regno_reg_class[REGNO])
-
-#define S_REGNO_P(REGNO) (((REGNO) - S0_REGNUM) < (unsigned) 8)
-#define A_REGNO_P(REGNO) (((REGNO) - A0_REGNUM) < (unsigned) 8)
-
-#define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X)))
-#define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS INDEX_REGS
-#define BASE_REG_CLASS INDEX_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-/* a => A_REGS
-   d => S_REGS  ('s' is taken)
-   A => INDEX_REGS  (i.e., A_REGS except sp) */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  reg_class_from_letter[(unsigned char) (C)]
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.  */
-/* 'I' is used to pass any CONST_INT and reject any CONST_DOUBLE.
-   CONST_DOUBLE integers are handled by G and H constraint chars. */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  1
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-/* Convex uses G, H:
-   value usable in ld.d (low word 0) or ld.l (high word all sign) */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)				\
-  (((C) == 'G' && LD_D_P (VALUE)) ||					\
-   ((C) == 'H' && LD_L_P (VALUE)) ||					\
-   0)
-
-#define LD_D_P(X) (const_double_low_int (X) == 0)
-
-#define LD_L_P(X) (const_double_low_int (X) >= 0 \
-		   ? const_double_high_int (X) == 0 \
-		   : const_double_high_int (X) == -1)
-
-/* Optional extra constraints for this machine.
-   For Convex, 'Q' means that OP is a volatile MEM.
-   For volatile scalars, we use instructions that bypass the data cache. */
-
-#define EXTRA_CONSTRAINT(OP, C) \
-  ((C) == 'Q' ? (GET_CODE (OP) == MEM && MEM_VOLATILE_P (OP)		\
-		 && ! TARGET_C1 && TARGET_VOLATILE_NOCACHE)   		\
-   : 0)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-/* Put 2-word constants that can't be immediate operands into memory. */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)	\
-  ((GET_CODE (X) != CONST_DOUBLE					\
-    || GET_MODE (X) == SFmode						\
-    || LD_L_P (X) || LD_D_P (X))  ? (CLASS) : NO_REGS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)  ((GET_MODE_SIZE (MODE) + 7) / 8)
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Define this if should default to -fcaller-saves.  */
-#define DEFAULT_CALLER_SAVES
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by. */
-#define PUSH_ROUNDING(BYTES) (((BYTES) + 3) & ~3)
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), S0_REGNUM)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, S0_REGNUM)
-
-/* Define this if PCC uses the nonreentrant convention for returning
-   structure and union values.  */
-
-#define PCC_STATIC_STRUCT_RETURN
-
-/* 1 if N is a possible register number for a function value.
-   On the Convex, S0 is the only register thus used.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == S0_REGNUM)
-
-/* 1 if N is a possible register number for function argument passing. */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go. */
-/* On convex, simply count the arguments in case TARGET_ARGCOUNT is set. */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0. */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
-  ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
-  ((CUM) += 1)
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-
-    Convex: all args go on the stack.  But return the arg count
-    as the "next arg register" to be passed to gen_call.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  ((MODE) == VOIDmode ? GEN_INT ((CUM)) : 0)
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) 					\
-{									\
-  int size = ((SIZE) + 7) & -8;						\
-  if (size != 0)							\
-    fprintf (FILE, "\tsub.w #%d,sp\n", size);				\
-}
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE)					\
-{									\
-  /* Follow function with a zero to stop c34 icache prefetching. */	\
-  fprintf (FILE, "\tds.h 0\n");						\
-}
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  */
-
-/* On convex, the code for a trampoline is
-       ld.w #<link>,s0
-       jmp <func>  */
-
-#define TRAMPOLINE_TEMPLATE(FILE) \
-{									\
-  fprintf (FILE, "\tld.w #69696969,s0\n");				\
-  fprintf (FILE, "\tjmp 52525252\n");					\
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 12
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-{									\
-  emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 2)), CXT);	\
-  emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 8)), FNADDR); \
-  emit_call_insn (gen_call_pop (gen_rtx (MEM, QImode,			\
-					 gen_rtx (SYMBOL_REF, Pmode,	\
-						  "__enable_execute_stack")), \
-				const0_rtx, const0_rtx, const0_rtx));	\
-}
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   fprintf (FILE, "\tldea LP%d,a1\n\tcallq mcount\n", (LABELNO));
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved.  */
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)			\
-{ (DEPTH) = (get_frame_size () + 7) & -8; }
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(regno)  \
-  ((regno) <= LAST_VIRTUAL_REGISTER					\
-    ? regno_ok_for_index_p[regno]					\
-    : regno_ok_for_index_p[reg_renumber[regno]])
-
-#define REGNO_OK_FOR_BASE_P(regno)  REGNO_OK_FOR_INDEX_P (regno)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 1
-
-/* 1 if X is an rtx for a constant that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-/* For convex, bounce 2-word constants that can't be immediate operands. */
-
-#define LEGITIMATE_CONSTANT_P(X) \
-  (GET_CODE (X) != CONST_DOUBLE						\
-   || GET_MODE (X) == SFmode						\
-   || LD_L_P (X) || LD_D_P (X))
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) \
-  (REGNO (X) > LAST_VIRTUAL_REGISTER || regno_ok_for_index_p[REGNO (X)])
-
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   For Convex, valid addresses are
-       indirectable or (MEM indirectable)
-   where indirectable is 
-       const, reg, (PLUS reg const)
-
-   We don't use indirection since with insn scheduling, load + indexing
-   is better. */
-
-/* 1 if X is an address that we could indirect through.  */
-#define INDIRECTABLE_ADDRESS_P(X)  \
-  (CONSTANT_ADDRESS_P (X)						\
-   || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
-   || (GET_CODE (X) == PLUS						\
-       && GET_CODE (XEXP (X, 0)) == REG					\
-       && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
-       && CONSTANT_ADDRESS_P (XEXP (X, 1)))				\
-   || (GET_CODE (X) == PLUS						\
-       && GET_CODE (XEXP (X, 1)) == REG					\
-       && REG_OK_FOR_BASE_P (XEXP (X, 1))				\
-       && CONSTANT_ADDRESS_P (XEXP (X, 0))))
-
-/* Go to ADDR if X is a valid address. */
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
-{ register rtx xfoob = (X);						\
-  if (INDIRECTABLE_ADDRESS_P (xfoob))					\
-    goto ADDR;								\
-  if (GET_CODE (xfoob) == PRE_DEC && XEXP (xfoob, 0) == stack_pointer_rtx) \
-    goto ADDR;								\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For Convex, nothing needs to be done.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)  {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  {}
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define this if the case instruction drops through after the table
-   when the index is out of range.  Don't define it if the case insn
-   jumps to the default label instead.  */
-/* #define CASE_DROPS_THROUGH */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.  */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 8
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS (! TARGET_C2)
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* On Convex, it is as good to call a constant function address as to
-   call an address kept in a register. */
-#define NO_FUNCTION_CSE
-
-/* When a prototype says `char' or `short', really pass an `int'.  */
-#define PROMOTE_PROTOTYPES
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST: \
-  case LABEL_REF: \
-  case SYMBOL_REF: \
-  case CONST_INT: \
-  case CONST_DOUBLE: \
-    return 0;
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  */
-
-#define RTX_COSTS(RTX,CODE,OUTER_CODE) \
-  case PLUS:								\
-    if (regno_pointer_flag != 0						\
-	&& GET_CODE (XEXP (RTX, 0)) == REG				\
-	&& REGNO_POINTER_FLAG (REGNO (XEXP (RTX, 0)))			\
-	&& GET_CODE (XEXP (RTX, 1)) == CONST_INT)			\
-      return 0;								\
-    else break;								\
-  case MULT:								\
-    return 4 * (char) (0x03060403 >> target_cpu * 8);			\
-  case ASHIFT:								\
-  case LSHIFTRT:							\
-  case ASHIFTRT:							\
-    return 4 * (char) (0x03010403 >> target_cpu * 8);			\
-  case MEM:								\
-    return 5;
-
-/* Compute the cost of an address.  This is meant to approximate the size
-   and/or execution delay of an insn using that address.  If the cost is
-   approximated by the RTL complexity, including CONST_COSTS above, as
-   is usually the case for CISC machines, this macro should not be defined.
-   For aggressively RISCy machines, only one insn format is allowed, so
-   this macro should be a constant.  The value of this macro only matters
-   for valid addresses.  */
-
-#define ADDRESS_COST(RTX) 0
-
-/* Specify the cost of a branch insn; roughly the number of extra insns that
-   should be added to avoid a branch.  */
-
-#define BRANCH_COST 0
-
-/* Adjust the cost of dependences. */
-
-#define ADJUST_COST(INSN,LINK,DEP,COST) 				\
-{									\
-  /* Antidependencies don't block issue. */				\
-  if (REG_NOTE_KIND (LINK) != 0)					\
-    (COST) = 0;								\
-  /* C38 situations where delay depends on context */			\
-  else if (TARGET_C38							\
-	   && GET_CODE (PATTERN (INSN)) == SET				\
-	   && GET_CODE (PATTERN (DEP)) == SET)				\
-    {									\
-      enum attr_type insn_type = get_attr_type (INSN);			\
-      enum attr_type dep_type = get_attr_type (DEP);			\
-      /* index register must be ready one cycle early */		\
-      if (insn_type == TYPE_MLDW || insn_type == TYPE_MLDL		\
-          || (insn_type == TYPE_MST					\
-	      && reg_mentioned_p (SET_DEST (PATTERN (DEP)),		\
-				  SET_SRC (PATTERN (INSN)))))		\
-	(COST) += 1;							\
-      /* alu forwarding off alu takes two */				\
-      if (dep_type == TYPE_ALU						\
-	  && insn_type != TYPE_ALU					\
-	  && ! (insn_type == TYPE_MST					\
-		&& SET_DEST (PATTERN (DEP)) == SET_SRC (PATTERN (INSN)))) \
-	(COST) += 1;							\
-    }									\
-}
-
-/* Convex uses Vax or IEEE floats.
-   Follow the host format. */
-#define TARGET_FLOAT_FORMAT HOST_FLOAT_FORMAT
-
-/* But must prevent real.c from constructing Vax dfloats */
-#define REAL_VALUE_ATOF(X,S) atof (X)
-extern double atof();
-
-/* Check a `double' value for validity for a particular machine mode.  */
-#define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
-   OVERFLOW = check_float_value (MODE, &D, OVERFLOW)
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  No extra ones are needed for convex.  */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define NOTICE_UPDATE_CC(EXP,INSN)  {}
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#if _IEEE_FLOAT_
-#define ASM_FILE_START(FILE)  fprintf (FILE, ";NO_APP\n.fpmode ieee\n")
-#else
-#define ASM_FILE_START(FILE)  fprintf (FILE, ";NO_APP\n.fpmode native\n")
-#endif
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ";APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ";NO_APP\n"
-
-/* Alignment with Convex's assembler goes like this:
-   .text can be .aligned up to a halfword.
-   .data and .bss can be .aligned up to a longword.
-   .lcomm is not supported, explicit declarations in .bss must be used instead.
-   We get alignment for word and longword .text data by conventionally
-   using .text 2 for word-aligned data and .text 3 for longword-aligned
-   data.  This requires that the data's size be a multiple of its alignment,
-   which seems to be always true.  */
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP (current_section_is_text = 1, ".text")
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP (current_section_is_text = 0, ".data") 
-
-/* Output before uninitialized data.  */
-
-#define BSS_SECTION_ASM_OP (current_section_is_text = 0, ".bss") 
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
-  if (current_section_is_text && (LOG) > 1)				\
-    fprintf (FILE, ".text %d\n", LOG);					\
-  else if (current_section_is_text)					\
-    fprintf (FILE, ".text\n.align %d\n", 1 << (LOG));			\
-  else									\
-    fprintf (FILE, ".align %d\n", 1 << (LOG))
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES							\
-{									\
-  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 			\
-  "sp", "a1", "a2", "a3", "a4", "a5", "ap", "fp",			\
-}
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* How to renumber registers for dbx and gdb. */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Do not break .stabs pseudos into continuations.  */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* This is the char to use for continuation (in case we need to turn
-   continuation back on).  */
-
-#define DBX_CONTIN_CHAR '?'
-
-/* Don't use stab extensions until GDB v4 port is available for convex. */
-
-#define DEFAULT_GDB_EXTENSIONS 0
-#define DBX_NO_XREFS
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* Put case tables in .text 2, where they will be word-aligned */
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
-  ASM_OUTPUT_ALIGN (FILE, 2); \
-  ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM)
-
-#define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \
-  ASM_OUTPUT_ALIGN (FILE, 1)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
-  outfloat (FILE, VALUE, "%.17e", "\tds.d ", "\n")
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
-  outfloat (FILE, VALUE, "%.9e", "\tds.s ", "\n")
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-{									\
-  fprintf (FILE, "\tds.w ");						\
-  output_addr_const (FILE, simplify_for_convex (VALUE));		\
-  fprintf (FILE, "\n");							\
-}
-
-/* Likewise for a `long long int' constant.  */
-
-#define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE)  \
-{									\
-  if (GET_CODE (VALUE) == CONST_DOUBLE)					\
-    fprintf (FILE, "\tds.w %d,%d\n",					\
-	     const_double_high_int (VALUE), const_double_low_int (VALUE)); \
-  else if (GET_CODE (VALUE) == CONST_INT)				\
-    {									\
-      int val = INTVAL (VALUE);						\
-      fprintf (FILE, "\tds.w %d,%d\n", val < 0 ? -1 : 0, val);		\
-    }									\
-  else									\
-    abort ();								\
-}
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\tds.h "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\tds.b "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\tds.b %#x\n", (VALUE))
-
-/* This is how to output a string */
-
-#define ASM_OUTPUT_ASCII(FILE,STR,SIZE) do {				\
-  int i;								\
-  fprintf ((FILE), "\tds.b \"");					\
-  for (i = 0; i < (SIZE); i++) {					\
-      register int c = (STR)[i] & 0377;					\
-      if (c >= ' ' && c < 0177 && c != '\\' && c != '"')		\
-	  putc (c, (FILE));						\
-      else								\
-	  fprintf ((FILE), "\\%03o", c);}				\
-  fprintf ((FILE), "\"\n");} while (0)
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  	\
-   fprintf (FILE, "\tpsh.%c %s\n",		\
-	    S_REGNO_P (REGNO) ? 'l' : 'w',	\
-	    reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)		\
-   fprintf (FILE, "\tpop.%c %s\n",		\
-	    S_REGNO_P (REGNO) ? 'l' : 'w',	\
-	    reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute. */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\tds.w L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  
-   (not used on Convex) */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\tds.w L%d-L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter by SIZE bytes.  */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\tds.b %u(0)\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( bss_section (),				\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ":\tbs.b %u\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Output an arg count before function entries. */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)	\
-  asm_declare_function_name (FILE, NAME, DECL)
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print an instruction operand X on file FILE.
-   CODE is the code from the %-spec that requested printing this operand;
-   if `%z3' was used to print operand 3, then CODE is 'z'. */
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-    print_operand (FILE, X, CODE)
-
-/* Print a memory operand whose address is X, on file FILE. */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)				\
-    print_operand_address (FILE, ADDR)
-
-/* Do not put out GNU stabs for constructors and destructors.
-   ld bounces them.  */
-
-#define FASCIST_ASSEMBLER
-
-/* __gcc_cleanup is loader-aliased to __ap$do_registered_functions if we
-   are linking against standard libc, 0 if old (-traditional) libc. */
-
-#define EXIT_BODY \
-{									\
-  extern void __gcc_cleanup ();						\
-  if (__gcc_cleanup != _cleanup)					\
-    __gcc_cleanup ();							\
-  _cleanup ();								\
-}
-
-/* Header for convex.c.
-   Here at the end so we can use types defined above. */
-
-extern int target_cpu;
-extern int current_section_is_text;
-extern enum reg_class regno_reg_class[];
-extern enum reg_class reg_class_from_letter[];
-extern char regno_ok_for_index_p_base[];
-#define regno_ok_for_index_p (regno_ok_for_index_p_base + 1)
-
-extern int const_double_low_int ();
-extern int const_double_high_int ();
-extern char *output_cmp ();
-extern char *output_condjump ();
-extern char *output_call ();
-extern void gen_ap_for_call ();
-extern int check_float_value ();
-extern void asm_declare_function_name ();
diff --git a/gcc/config/convex/convex.md b/gcc/config/convex/convex.md
deleted file mode 100755
index cb6f64d..0000000
--- a/gcc/config/convex/convex.md
+++ /dev/null
@@ -1,1885 +0,0 @@
-;;- Machine description for GNU compiler, Convex Version
-;;  Copyright (C) 1988, 1994, 1995 Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;; Attribute specifications
-
-; Target CPU
-(define_attr "cpu" "c1,c32,c34,c38"
-  (const (symbol_ref "(enum attr_cpu) target_cpu")))
-
-;; Instruction classification
-
-(define_attr "type"
-  "alu,xalu,mldw,mldl,mldb,mst,adds,addd,mulw,mull,muls,muld,divw,divl,divs,divd,shfw,shfl,cvts,cvtd"
-  (const_string "alu"))
-
-;; Instruction times
-
-(define_function_unit "mem" 1 0
-  (and (eq_attr "cpu" "c1") (eq_attr "type" "mldw")) 2 0)
-(define_function_unit "mem" 1 0
-  (and (eq_attr "cpu" "c1") (eq_attr "type" "mldl")) 4 0)
-(define_function_unit "mem" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "mldw,mldl")) 2 0)
-(define_function_unit "mem" 1 0
-  (and (eq_attr "cpu" "c34") (eq_attr "type" "mldw,mldl")) 4 0)
-(define_function_unit "mem" 1 0
-  (and (eq_attr "cpu" "c38") (eq_attr "type" "mldw,mldl")) 2 0)
-
-(define_function_unit "mem" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "mldb")) 9 0)
-(define_function_unit "mem" 1 0
-  (and (eq_attr "cpu" "c34") (eq_attr "type" "mldb")) 36 0)
-(define_function_unit "mem" 1 0
-  (and (eq_attr "cpu" "c38") (eq_attr "type" "mldb")) 21 0)
-
-(define_function_unit "mem" 1 0
-  (and (eq_attr "cpu" "c1") (eq_attr "type" "xalu")) 1 0)
-(define_function_unit "mem" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "xalu")) 1 0)
-(define_function_unit "mem" 1 0
-  (and (eq_attr "cpu" "c34") (eq_attr "type" "xalu")) 5 0)
-(define_function_unit "mem" 1 0
-  (and (eq_attr "cpu" "c38") (eq_attr "type" "xalu")) 2 0)
-
-(define_function_unit "add" 1 0
-  (and (eq_attr "cpu" "c1") (eq_attr "type" "adds,addd")) 3 2)
-(define_function_unit "add" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "adds,addd")) 2 1)
-(define_function_unit "add" 1 0
-  (and (eq_attr "cpu" "c34") (eq_attr "type" "adds,addd")) 5 2)
-(define_function_unit "add" 1 0
-  (and (eq_attr "cpu" "c38") (eq_attr "type" "adds,addd")) 2 1)
-
-(define_function_unit "mul" 1 0
-  (and (eq_attr "cpu" "c1") (eq_attr "type" "mulw,muls")) 3 2)
-(define_function_unit "mul" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "mulw,muls")) 4 2)
-(define_function_unit "mul" 1 0
-  (and (eq_attr "cpu" "c34") (eq_attr "type" "mulw,muls")) 6 2)
-(define_function_unit "mul" 1 0
-  (and (eq_attr "cpu" "c38") (eq_attr "type" "mulw,muls")) 3 2)
-
-(define_function_unit "mul" 1 0
-  (and (eq_attr "cpu" "c1") (eq_attr "type" "mull,muld")) 4 3)
-(define_function_unit "mul" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "mull")) 10 7)
-(define_function_unit "mul" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "muld")) 5 2)
-(define_function_unit "mul" 1 0
-  (and (eq_attr "cpu" "c34") (eq_attr "type" "mull,muld")) 7 3)
-(define_function_unit "mul" 1 0
-  (and (eq_attr "cpu" "c38") (eq_attr "type" "mull,muld")) 4 3)
-
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c1") (eq_attr "type" "divw")) 24 24)
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "divw")) 44 6)
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c34") (eq_attr "type" "divw")) 14 10)
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c38") (eq_attr "type" "divw")) 11 10)
-
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c1") (eq_attr "type" "divl")) 41 42)
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "divl")) 76 5)
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c34") (eq_attr "type" "divl")) 22 18)
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c38") (eq_attr "type" "divl")) 19 18)
-
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c1") (eq_attr "type" "divs")) 22 22)
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "divs")) 8 6)
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c34") (eq_attr "type" "divs")) 13 9)
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c38") (eq_attr "type" "divs")) 10 9)
-
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c1") (eq_attr "type" "divd")) 37 38)
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "divd")) 12 8)
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c34") (eq_attr "type" "divd")) 20 16)
-(define_function_unit "div" 1 0
-  (and (eq_attr "cpu" "c38") (eq_attr "type" "divd")) 17 16)
-
-(define_function_unit "misc" 1 0
-  (and (eq_attr "cpu" "c1") (eq_attr "type" "cvts,cvtd")) 4 3)
-(define_function_unit "misc" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "cvts")) 9 7)
-(define_function_unit "misc" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "cvtd")) 9 6)
-(define_function_unit "misc" 1 0
-  (and (eq_attr "cpu" "c34") (eq_attr "type" "cvts")) 6 2)
-(define_function_unit "misc" 1 0
-  (and (eq_attr "cpu" "c34") (eq_attr "type" "cvtd")) 6 1)
-(define_function_unit "misc" 1 0
-  (and (eq_attr "cpu" "c38") (eq_attr "type" "cvts,cvtd")) 3 1)
-
-(define_function_unit "misc" 1 0
-  (and (eq_attr "cpu" "c1") (eq_attr "type" "shfw,shfl")) 3 2)
-(define_function_unit "misc" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "shfw")) 7 5)
-(define_function_unit "misc" 1 0
-  (and (eq_attr "cpu" "c32") (eq_attr "type" "shfl")) 7 4)
-(define_function_unit "misc" 1 0
-  (and (eq_attr "cpu" "c38") (eq_attr "type" "shfw,shfl")) 3 1)
-
-(define_function_unit "mystery_latch" 1 1
-  (and (eq_attr "type" "!alu,mldw,mldl,adds,addd") (eq_attr "cpu" "c32")) 2 2)
-
-;(define_function_unit "ip" 1 1
-;  (and (eq_attr "cpu" "c1")
-;       (eq_attr "type" "divw,divl,divs,divd,xalu")) 2 2)
-;(define_function_unit "ip" 1 1
-;  (and (eq_attr "cpu" "c1")
-;       (eq_attr "type" "!divw,divl,divs,divd,xalu")) 1 1)
-;(define_function_unit "ip" 1 1
-;  (and (eq_attr "cpu" "c32")
-;       (eq_attr "type" "mull,muld,divl,divd,shfl,cvtd,xalu")) 2 2)
-;(define_function_unit "ip" 1 1
-;  (and (eq_attr "cpu" "c32")
-;       (eq_attr "type" "!mull,muld,divl,divd,shfl,cvtd,xalu")) 1 1)
-;(define_function_unit "ip" 1 1
-;  (and (eq_attr "cpu" "c34")
-;       (eq_attr "type" "addd,mull,muld,divl,divd,cvtd,xalu")) 2 2)
-;(define_function_unit "ip" 1 1
-;  (and (eq_attr "cpu" "c34")
-;       (eq_attr "type" "!addd,mull,muld,divl,divd,cvtd,xalu")) 1 1)
-
-;; Make the first thing a real insn in case of genattrtab bug
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
-
-;; Moves
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "if (GET_CODE (operands[0]) != REG)
-     operands[1] = force_reg (DFmode, operands[1]);")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=d,d,d,d,d,<,m")
-	(match_operand:DF 1 "general_operand"  "d,Q,m,G,H,d,d"))]
-  "register_operand (operands[0], DFmode)
-   || register_operand (operands[1], DFmode)"
-  "@
-   mov %1,%0
-   ldb.d %1,%0
-   ld.d %1,%0
-   ld.d %u1,%0
-   ld.l %v1,%0
-   psh.l %1
-   st.d %1,%0"
-  [(set_attr "type" "alu,mldb,mldl,alu,alu,alu,mst")])
-
-;; This is here so we can load any result of RTL constant folding
-;; but do not use it on constants that can be loaded from memory.
-;; It is never better and can be worse.
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(match_operand:DF 1 "const_double_operand" "F"))]
-  "CONST_DOUBLE_MEM (operands[1]) == const0_rtx"
-  "ld.u %u1,%0\;ld.w %v1,%0"
-  [(set_attr "type" "xalu")])
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "if (GET_CODE (operands[0]) != REG)
-     operands[1] = force_reg (SFmode, operands[1]);")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=d,d,d,d,<,m")
-	(match_operand:SF 1 "general_operand" "d,Q,m,F,d,d"))]
-  "register_operand (operands[0], SFmode)
-   || register_operand (operands[1], SFmode)"
-  "@
-   mov.s %1,%0
-   ldb.s %1,%0
-   ld.s %1,%0
-   ld.s %1,%0
-   psh.w %1
-   st.s %1,%0"
-  [(set_attr "type" "alu,mldb,mldw,alu,alu,mst")])
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "if (GET_CODE (operands[0]) != REG)
-     operands[1] = force_reg (DImode, operands[1]);")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,d,<,m")
-	(match_operand:DI 1 "general_operand" "d,Q,m,G,HI,d,d"))]
-  "register_operand (operands[0], DImode)
-   || register_operand (operands[1], DImode)"
-  "@
-   mov %1,%0
-   ldb.l %1,%0
-   ld.l %1,%0
-   ld.d %u1,%0
-   ld.l %1,%0
-   psh.l %1
-   st.l %1,%0"
-  [(set_attr "type" "alu,mldb,mldl,alu,alu,alu,mst")])
-
-;; This is here so we can load any result of RTL constant folding
-;; but do not use it on constants that can be loaded from memory.
-;; It is never better and can be worse.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(match_operand:DI 1 "const_double_operand" "F"))]
-  "CONST_DOUBLE_MEM (operands[1]) == const0_rtx"
-  "ld.u %u1,%0\;ld.w %v1,%0"
-  [(set_attr "type" "xalu")])
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "if (GET_CODE (operands[0]) != REG)
-     operands[1] = force_reg (SImode, operands[1]);")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "push_operand" "=<,<")
-	(match_operand:SI 1 "nonmemory_operand" "Ad,i"))]
-  ""
-  "@
-   psh.w %1
-   pshea %a1")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d,r,d,r,r,m")
-	(match_operand:SI 1 "general_operand" "d,r,Q,m,i,r"))]
-  "register_operand (operands[0], SImode)
-   || register_operand (operands[1], SImode)"
-  "@
-   mov.w %1,%0
-   mov %1,%0
-   ldb.w %1,%0
-   ld.w %1,%0
-   ld.w %1,%0
-   st.w %1,%0"
-  [(set_attr "type" "alu,alu,mldb,mldw,alu,mst")])
-
-(define_expand "movstrictsi"
-  [(set (strict_low_part (match_operand:SI 0 "general_operand" ""))
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "if (GET_CODE (operands[0]) != REG)
-     operands[1] = force_reg (SImode, operands[1]);")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:SI 0 "general_operand" "=d,r,d,r,r,m"))
-	(match_operand:SI 1 "general_operand" "d,r,Q,m,i,r"))]
-  "register_operand (operands[0], SImode)
-   || register_operand (operands[1], SImode)"
-  "@
-   mov.w %1,%0
-   mov %1,%0
-   ldb.w %1,%0
-   ld.w %1,%0
-   ld.w %1,%0
-   st.w %1,%0"
-  [(set_attr "type" "alu,alu,mldb,mldw,alu,mst")])
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "if (GET_CODE (operands[0]) != REG)
-     operands[1] = force_reg (HImode, operands[1]);")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d,r,d,r,r,<,m")
-	(match_operand:HI 1 "general_operand" "d,r,Q,m,i,Ad,r"))]
-  "register_operand (operands[0], HImode)
-   || register_operand (operands[1], HImode)"
-  "@
-   mov.w %1,%0
-   mov %1,%0
-   ldb.h %1,%0
-   ld.h %1,%0
-   ld.w %1,%0
-   psh.w %1
-   st.h %1,%0"
-  [(set_attr "type" "alu,alu,mldb,mldw,alu,alu,mst")])
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "if (GET_CODE (operands[0]) != REG)
-     operands[1] = force_reg (QImode, operands[1]);")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d,r,d,r,r,<,m")
-	(match_operand:QI 1 "general_operand" "d,r,Q,m,i,Ad,r"))]
-  "register_operand (operands[0], QImode)
-   || register_operand (operands[1], QImode)"
-  "@
-   mov.w %1,%0
-   mov %1,%0
-   ldb.b %1,%0
-   ld.b %1,%0
-   ld.w %1,%0
-   psh.w %1
-   st.b %1,%0"
-  [(set_attr "type" "alu,alu,mldb,mldw,alu,alu,mst")])
-
-;; Expand block moves manually to get code that pipelines the loads.
-
-(define_expand "movstrsi"
-  [(set (match_operand:BLK 0 "memory_operand" "=m")
-	(match_operand:BLK 1 "memory_operand" "m"))
-   (use (match_operand:SI 2 "const_int_operand" "i"))
-   (use (match_operand:SI 3 "const_int_operand" "i"))]
-  ""
-  " expand_movstr (operands); DONE; ")
-
-;; Extension and truncation insns.
-;; Those for integer source operand
-;; are ordered widest source type first.
-
-(define_insn "truncsiqi2"
-  [(set (match_operand:QI 0 "register_operand" "=d,a")
-	(truncate:QI (match_operand:SI 1 "register_operand" "d,a")))]
-  ""
-  "cvtw.b %1,%0")
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "register_operand" "=d,a")
-	(truncate:HI (match_operand:SI 1 "register_operand" "d,a")))]
-  ""
-  "cvtw.h %1,%0")
-
-(define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(truncate:QI (match_operand:HI 1 "register_operand" "0")))]
-  ""
-  "")
-
-(define_insn "truncdisi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI (match_operand:DI 1 "register_operand" "d")))]
-  ""
-  "cvtl.w %1,%0")
-
-(define_insn "extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
-  ""
-  "cvtw.l %1,%0")
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(sign_extend:SI (match_operand:HI 1 "register_operand" "d,a")))]
-  ""
-  "cvth.w %1,%0")
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=d,a")
-	(sign_extend:HI (match_operand:QI 1 "register_operand" "d,a")))]
-  ""
-  "cvtb.w %1,%0")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(sign_extend:SI (match_operand:QI 1 "register_operand" "d,a")))]
-  ""
-  "cvtb.w %1,%0")
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(float_extend:DF (match_operand:SF 1 "register_operand" "d")))]
-  ""
-  "cvts.d %1,%0"
-  [(set_attr "type" "cvts")])
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(float_truncate:SF (match_operand:DF 1 "register_operand" "d")))]
-  ""
-  "cvtd.s %1,%0"
-  [(set_attr "type" "cvtd")])
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
-  ""
-  "and #0xffff,%0")
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(zero_extend:HI (match_operand:QI 1 "register_operand" "0")))]
-  ""
-  "and #0xff,%0")
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
-  ""
-  "and #0xff,%0")
-
-(define_insn "zero_extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(zero_extend:DI (match_operand:SI 1 "register_operand" "0")))]
-  ""
-  "ld.u #0,%0")
-
-;; Fix-to-float conversion insns.
-;; Note that the ones that start with SImode come first.
-;; That is so that an operand that is a CONST_INT
-;; (and therefore lacks a specific machine mode).
-;; will be recognized as SImode (which is always valid)
-;; rather than as QImode or HImode.
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(float:SF (match_operand:SI 1 "register_operand" "d")))]
-  ""
-  "cvtw.s %1,%0"
-  [(set_attr "type" "cvts")])
-
-(define_insn "floatdisf2"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(float:SF (match_operand:DI 1 "register_operand" "d")))]
-  ""
-  "cvtl.s %1,%0"
-  [(set_attr "type" "cvtd")])
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(float:DF (match_operand:SI 1 "register_operand" "d")))]
-  "! TARGET_C1"
-  "cvtw.d %1,%0"
-  [(set_attr "type" "cvts")])
-
-(define_insn "floatdidf2"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(float:DF (match_operand:DI 1 "register_operand" "d")))]
-  ""
-  "cvtl.d %1,%0"
-  [(set_attr "type" "cvtd")])
-
-;; These are a little slower than gcc's normal way of doing unsigned
-;; DI floats (if the DI number is "negative") but they avoid double
-;; rounding and they avoid explicit constants.
-
-(define_expand "floatunsdidf2"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(float:DF (match_operand:DI 1 "register_operand" "d")))
-   (set (cc0) (compare:DI (match_dup 3) (match_dup 1)))
-   (set (pc)
-	(if_then_else (le (cc0) (const_int 0))
-		      (label_ref (match_dup 4))
-		      (pc)))
-   (set (match_dup 2) (lshiftrt:DI (match_dup 1) (const_int 1)))
-   (set (match_dup 0) (float:DF (match_dup 2)))
-   (set (match_dup 0) (plus:DF (match_dup 0) (match_dup 0)))
-   (match_dup 4)
-   (set (match_dup 0) (match_dup 0))]
-  ""
-  "
-{
-  operands[2] = gen_reg_rtx (DImode);
-  operands[3] = force_reg (DImode, const0_rtx);
-  operands[4] = gen_label_rtx ();
-}")
-
-(define_expand "floatunsdisf2"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(float:SF (match_operand:DI 1 "register_operand" "d")))
-   (set (cc0) (compare:DI (match_dup 3) (match_dup 1)))
-   (set (pc)
-	(if_then_else (le (cc0) (const_int 0))
-		      (label_ref (match_dup 4))
-		      (pc)))
-   (set (match_dup 2) (lshiftrt:DI (match_dup 1) (const_int 1)))
-   (set (match_dup 0) (float:SF (match_dup 2)))
-   (set (match_dup 0) (plus:SF (match_dup 0) (match_dup 0)))
-   (match_dup 4)
-   (set (match_dup 0) (match_dup 0))]
-  ""
-  "
-{
-  operands[2] = gen_reg_rtx (DImode);
-  operands[3] = force_reg (DImode, const0_rtx);
-  operands[4] = gen_label_rtx ();
-}")
-
-;; These patterns are identical to gcc's default action 
-;; if DI->DF and DI->SF are not present.  There are here
-;; only to prevent SI->*F from promoting to DI->*F.
-
-(define_expand "floatunssidf2"
-  [(set (match_dup 2)
-	(zero_extend:DI (match_operand:SI 1 "register_operand" "")))
-   (set (match_operand:DF 0 "register_operand" "")
-	(float:DF (match_dup 2)))]
-  ""
-  "operands[2] = gen_reg_rtx (DImode);")
-
-(define_expand "floatunssisf2"
-  [(set (match_dup 2)
-        (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
-   (set (match_operand:SF 0 "register_operand" "")
-        (float:SF (match_dup 2)))]
-  ""
-  "operands[2] = gen_reg_rtx (DImode);")
-
-;; Float-to-fix conversion insns.
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "d"))))]
-  ""
-  "cvts.w %1,%0"
-  [(set_attr "type" "cvts")])
-
-(define_insn "fix_truncsfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "d"))))]
-  ""
-  "cvts.l %1,%0"
-  [(set_attr "type" "cvts")])
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
-  ""
-  "cvtd.l %1,%0"
-  [(set_attr "type" "cvtd")])
-
-(define_insn "fix_truncdfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
-  ""
-  "cvtd.l %1,%0"
-  [(set_attr "type" "cvtd")])
-
-;;- All kinds of add instructions.
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(plus:DF (match_operand:DF 1 "register_operand" "%0")
-		 (match_operand:DF 2 "register_operand" "d")))]
-  ""
-  "add.d %2,%0"
-  [(set_attr "type" "addd")])
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(plus:SF (match_operand:SF 1 "register_operand" "%0")
-		 (match_operand:SF 2 "nonmemory_operand" "dF")))]
-  ""
-  "add.s %2,%0"
-  [(set_attr "type" "adds")])
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(plus:DI (match_operand:DI 1 "register_operand" "%0")
-		 (match_operand:DI 2 "register_operand" "d")))]
-  ""
-  "add.l %2,%0")
-
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(plus:SI (match_operand:SI 1 "register_operand" "%A")
-		 (match_operand:SI 2 "immediate_operand" "i")))]
-  "operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx"
-  "ldea %a2(%1),%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(plus:SI (match_operand:SI 1 "register_operand" "%a")
-		 (match_operand:SI 2 "nonmemory_operand" "ri")))]
-  "operands[1] == stack_pointer_rtx && operands[0] != stack_pointer_rtx"
-  "mov %1,%0\;add.w %2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "push_operand" "=<")
-	(plus:SI (match_operand:SI 1 "register_operand" "A")
-		 (match_operand:SI 2 "immediate_operand" "i")))]
-  "operands[1] != stack_pointer_rtx"
-  "pshea %a2(%1)"
-  [(set_attr "type" "mst")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,a,a")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,A")
-		 (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))]
-  "TARGET_C1"
-  "@
-   add.w %2,%0
-   add.w %2,%0
-   ldea %a2(%1),%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,a,r")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,A")
-		 (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))]
-  ""
-  "@
-   add.w %2,%0
-   add.w %2,%0
-   ldea %a2(%1),%0")
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d,a")
-	(plus:HI (match_operand:HI 1 "register_operand" "%0,0")
-		 (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "add.h %2,%0")
-
-(define_insn "addqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d,d")
-	(plus:QI (match_operand:QI 1 "register_operand" "%0,0")
-		 (match_operand:QI 2 "nonmemory_operand" "d,i")))]
-  ""
-  "@
-   add.b %2,%0
-   add.w %2,%0")
-
-;;- All kinds of subtract instructions.
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(minus:DF (match_operand:DF 1 "register_operand" "0")
-		  (match_operand:DF 2 "register_operand" "d")))]
-  ""
-  "sub.d %2,%0"
-  [(set_attr "type" "addd")])
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(minus:SF (match_operand:SF 1 "register_operand" "0")
-		  (match_operand:SF 2 "nonmemory_operand" "dF")))]
-  ""
-  "sub.s %2,%0"
-  [(set_attr "type" "adds")])
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(minus:DI (match_operand:DI 1 "register_operand" "0")
-		  (match_operand:DI 2 "register_operand" "d")))]
-  ""
-  "sub.l %2,%0")
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d,a,?d,?a")
-	(minus:SI (match_operand:SI 1 "nonmemory_operand" "0,0,di,ai")
-		  (match_operand:SI 2 "nonmemory_operand" "di,ai,0,0")))]
-  ""
-  "@
-  sub.w %2,%0
-  sub.w %2,%0
-  sub.w %1,%0\;neg.w %0,%0
-  sub.w %1,%0\;neg.w %0,%0")
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d,a")
-	(minus:HI (match_operand:HI 1 "register_operand" "0,0")
-		  (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "sub.h %2,%0")
-
-(define_insn "subqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d,d")
-	(minus:QI (match_operand:QI 1 "register_operand" "0,0")
-		  (match_operand:QI 2 "nonmemory_operand" "d,i")))]
-  ""
-  "@
-   sub.b %2,%0
-   sub.w %2,%0")
-
-;;- Multiply instructions.
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(mult:DF (match_operand:DF 1 "register_operand" "%0")
-		 (match_operand:DF 2 "register_operand" "d")))]
-  ""
-  "mul.d %2,%0"
-  [(set_attr "type" "muld")])
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(mult:SF (match_operand:SF 1 "register_operand" "%0")
-		 (match_operand:SF 2 "nonmemory_operand" "dF")))]
-  ""
-  "mul.s %2,%0"
-  [(set_attr "type" "muls")])
-
-(define_insn "muldi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(mult:DI (match_operand:DI 1 "register_operand" "%0")
-		 (match_operand:DI 2 "register_operand" "d")))]
-  ""
-  "mul.l %2,%0"
-  [(set_attr "type" "mull")])
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(mult:SI (match_operand:SI 1 "register_operand" "%0,0")
-		 (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "mul.w %2,%0"
-  [(set_attr "type" "mulw")])
-
-(define_insn "mulhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d,a")
-	(mult:HI (match_operand:HI 1 "register_operand" "%0,0")
-		 (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "mul.h %2,%0"
-  [(set_attr "type" "mulw")])
-
-(define_insn "mulqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d,d")
-	(mult:QI (match_operand:QI 1 "register_operand" "%0,0")
-		 (match_operand:QI 2 "nonmemory_operand" "d,i")))]
-  ""
-  "@
-   mul.b %2,%0
-   mul.w %2,%0"
-  [(set_attr "type" "mulw,mulw")])
-
-;;- Divide instructions.
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(div:DF (match_operand:DF 1 "register_operand" "0")
-		(match_operand:DF 2 "register_operand" "d")))]
-  ""
-  "div.d %2,%0"
-  [(set_attr "type" "divd")])
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(div:SF (match_operand:SF 1 "register_operand" "0")
-		(match_operand:SF 2 "nonmemory_operand" "dF")))]
-  ""
-  "div.s %2,%0"
-  [(set_attr "type" "divs")])
-
-(define_insn "divdi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(div:DI (match_operand:DI 1 "register_operand" "0")
-		(match_operand:DI 2 "register_operand" "d")))]
-  ""
-  "div.l %2,%0"
-  [(set_attr "type" "divl")])
-
-(define_expand "udivsi3"
-  [(set (match_dup 3)
-	(zero_extend:DI (match_operand:SI 1 "register_operand" "")))
-   (set (match_dup 4)
-	(zero_extend:DI (match_operand:SI 2 "register_operand" "")))
-   (set (match_dup 3)
-	(div:DI (match_dup 3) (match_dup 4)))
-   (set (match_operand:SI 0 "register_operand" "")
-	(subreg:SI (match_dup 3) 0))]
-  ""
-  "operands[3] = gen_reg_rtx (DImode);
-   operands[4] = gen_reg_rtx (DImode); ")
-
-(define_insn "udivdi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(udiv:DI (match_operand:DI 1 "register_operand" "d")
-		 (match_operand:DI 2 "register_operand" "d")))]
-  ""
-  "psh.l %2\;psh.l %1\;callq udiv64\;pop.l %0\;add.w #8,sp")
-
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(div:SI (match_operand:SI 1 "register_operand" "0,0")
-		(match_operand:SI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "div.w %2,%0"
-  [(set_attr "type" "divw")])
-
-(define_insn "divhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d,a")
-	(div:HI (match_operand:HI 1 "register_operand" "0,0")
-		(match_operand:HI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "div.h %2,%0"
-  [(set_attr "type" "divw")])
-
-(define_insn "divqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d")
-	(div:QI (match_operand:QI 1 "register_operand" "0")
-		(match_operand:QI 2 "register_operand" "d")))]
-  ""
-  "div.b %2,%0"
-  [(set_attr "type" "divw")])
-
-;;- Bit clear instructions.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(and:DI (match_operand:DI 1 "register_operand" "%0")
-		(match_operand:DI 2 "" "")))]
-  "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-   || (GET_CODE (operands[2]) == CONST_DOUBLE
-       && CONST_DOUBLE_HIGH (operands[2]) == -1)"
-  "and %2,%0")
-
-(define_insn "anddi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(and:DI (match_operand:DI 1 "register_operand" "%0")
-		(match_operand:DI 2 "register_operand" "d")))]
-  ""
-  "and %2,%0")
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(and:SI (match_operand:SI 1 "register_operand" "%0,0")
-		(match_operand:SI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "and %2,%0")
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d,a")
-	(and:HI (match_operand:HI 1 "register_operand" "%0,0")
-		(match_operand:HI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "and %2,%0")
-
-(define_insn "andqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d,a")
-	(and:QI (match_operand:QI 1 "register_operand" "%0,0")
-		(match_operand:QI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "and %2,%0")
-
-;;- Bit set instructions.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ior:DI (match_operand:DI 1 "register_operand" "%0")
-		(match_operand:DI 2 "" "")))]
-  "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0)
-   || (GET_CODE (operands[2]) == CONST_DOUBLE
-       && CONST_DOUBLE_HIGH (operands[2]) == 0)"
-  "or %2,%0")
-
-(define_insn "iordi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ior:DI (match_operand:DI 1 "register_operand" "%0")
-		(match_operand:DI 2 "register_operand" "d")))]
-  ""
-  "or %2,%0")
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
-		(match_operand:SI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "or %2,%0")
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d,a")
-	(ior:HI (match_operand:HI 1 "register_operand" "%0,0")
-		(match_operand:HI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "or %2,%0")
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d,a")
-	(ior:QI (match_operand:QI 1 "register_operand" "%0,0")
-		(match_operand:QI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "or %2,%0")
-
-;;- xor instructions.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(xor:DI (match_operand:DI 1 "register_operand" "%0")
-		(match_operand:DI 2 "" "")))]
-  "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0)
-   || (GET_CODE (operands[2]) == CONST_DOUBLE
-       && CONST_DOUBLE_HIGH (operands[2]) == 0)"
-  "xor %2,%0")
-
-(define_insn "xordi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(xor:DI (match_operand:DI 1 "register_operand" "%0")
-		(match_operand:DI 2 "register_operand" "d")))]
-  ""
-  "xor %2,%0")
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(xor:SI (match_operand:SI 1 "register_operand" "%0,0")
-		(match_operand:SI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "xor %2,%0")
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d,a")
-	(xor:HI (match_operand:HI 1 "register_operand" "%0,0")
-		(match_operand:HI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "xor %2,%0")
-
-(define_insn "xorqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d,a")
-	(xor:QI (match_operand:QI 1 "register_operand" "%0,0")
-		(match_operand:QI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "xor %2,%0")
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(neg:DF (match_operand:DF 1 "register_operand" "d")))]
-  ""
-  "neg.d %1,%0"
-  [(set_attr "type" "addd")])
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(neg:SF (match_operand:SF 1 "register_operand" "d")))]
-  ""
-  "neg.s %1,%0"
-  [(set_attr "type" "adds")])
-
-(define_insn "negdi2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
-  ""
-  "neg.l %1,%0")
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(neg:SI (match_operand:SI 1 "register_operand" "d,a")))]
-  ""
-  "neg.w %1,%0")
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "register_operand" "=d,a")
-	(neg:HI (match_operand:HI 1 "register_operand" "d,a")))]
-  ""
-  "neg.h %1,%0")
-
-(define_insn "negqi2"
-  [(set (match_operand:QI 0 "register_operand" "=d")
-	(neg:QI (match_operand:QI 1 "register_operand" "d")))]
-  ""
-  "neg.b %1,%0")
-
-(define_insn "one_cmpldi2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(not:DI (match_operand:DI 1 "register_operand" "d")))]
-  ""
-  "not %1,%0")
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(not:SI (match_operand:SI 1 "register_operand" "d,a")))]
-  ""
-  "not %1,%0")
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "register_operand" "=d,a")
-	(not:HI (match_operand:HI 1 "register_operand" "d,a")))]
-  ""
-  "not %1,%0")
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "register_operand" "=d,a")
-	(not:QI (match_operand:QI 1 "register_operand" "d,a")))]
-  ""
-  "not %1,%0")
-
-;;- Shifts
-;;
-;; The extreme profusion of patterns here is due to the different-speed
-;; shifts on different machines, and the C1's lack of word shift S-register
-;; instructions.
-
-;; SImode
-
-;; Arithmetic left 1, 1 cycle on all machines via add
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0")
-		   (const_int 1)))]
-  ""
-  "add.w %0,%0")
-
-;; C34 general shift is 1 cycle
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
-  "TARGET_C34"
-  "@
-   shf.w %2,%0
-   shf %2,%0"
-  [(set_attr "type" "shfw,shfw")])
-
-;; else shift left 0..7 is 1 cycle if we use an A register
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=a,?d")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
-		   (match_operand:SI 2 "immediate_operand" "ai,di")))]
-  "TARGET_C1 && INTVAL (operands[2]) < (unsigned) 8"
-  "@
-   shf %2,%0
-   shf %2,%0"
-  [(set_attr "type" "alu,shfl")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=a,?d")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
-		   (match_operand:SI 2 "immediate_operand" "ai,di")))]
-  "INTVAL (operands[2]) < (unsigned) 8"
-  "@
-   shf %2,%0
-   shf.w %2,%0"
-  [(set_attr "type" "alu,shfw")])
-
-;; else general left shift
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
-  "TARGET_C1"
-  "@
-   shf %2,%0
-   shf %2,%0"
-  [(set_attr "type" "shfl,shfw")])
-
-;; but C2 left shift by a constant is faster via multiply
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:SI 2 "const_int_operand" "i")))]
-  "TARGET_C2 && INTVAL (operands[2]) < (unsigned) 32"
-  "mul.w %z2,%0"
-  [(set_attr "type" "mulw")])
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "@
-   shf.w %2,%0
-   shf %2,%0"
-  [(set_attr "type" "shfw,shfw")])
-
-;; Logical right, general
-;; The hardware wants the negative of the shift count
-
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
-  ""
-  "operands[2] = negate_rtx (SImode, operands[2]);")
-
-;; C1 lacks word shift S reg
-
-(define_insn ""
-  [(set
-    (match_operand:SI 0 "register_operand" "=a,?d")
-    (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
-		 (neg:SI (match_operand:SI 2 "nonmemory_operand" "ai,di"))))]
-  "TARGET_C1"
-  "@
-   shf %2,%0
-   ld.u #0,%0\;shf %2,%0"
-  [(set_attr "type" "shfw,shfl")])
-
-;; general case
-
-(define_insn ""
-  [(set
-    (match_operand:SI 0 "register_operand" "=d,a")
-    (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
-		 (neg:SI (match_operand:SI 2 "nonmemory_operand" "di,ai"))))]
-  ""
-  "@
-   shf.w %2,%0
-   shf %2,%0"
-  [(set_attr "type" "shfw,shfw")])
-
-;; Patterns without neg produced by constant folding
-
-(define_insn ""
-  [(set
-    (match_operand:SI 0 "register_operand" "=a,?d")
-    (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
-		 (match_operand:SI 2 "immediate_operand" "i,i")))]
-  "TARGET_C1"
-  "@
-   shf #%n2,%0
-   ld.u #0,%0\;shf #%n2,%0"
-  [(set_attr "type" "shfw,shfl")])
-
-(define_insn ""
-  [(set
-    (match_operand:SI 0 "register_operand" "=d,a")
-    (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
-		 (match_operand:SI 2 "immediate_operand" "i,i")))]
-  ""
-  "@
-   shf.w #%n2,%0
-   shf #%n2,%0"
-  [(set_attr "type" "shfw,shfw")])
-
-;; Arithmetic right, general
-;; Sign-extend to 64 bits, then shift that.  Works for 0..32.
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
-  ""
-  "operands[2] = negate_rtx (SImode, operands[2]);")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,&d")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
-		     (neg:SI
-		      (match_operand:SI 2 "nonmemory_operand" "di,di"))))]
-  ""
-  "cvtw.l %1,%0\;shf %2,%0"
-  [(set_attr "type" "shfl,shfl")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "cvtw.l %1,%0\;shf #%n2,%0"
-  [(set_attr "type" "shfl")])
-
-;; DImode
-;; Arithmetic left, 1-cycle
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ashift:DI (match_operand:DI 1 "register_operand" "0")
-		   (const_int 1)))]
-  ""
-  "add.l %0,%0")
-
-;; Arithmetic left, general
-
-(define_insn "ashldi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ashift:DI (match_operand:DI 1 "register_operand" "0")
-		   (match_operand:SI 2 "nonmemory_operand" "di")))]
-  ""
-  "shf %2,%0"
-  [(set_attr "type" "shfl")])
-
-;; Can omit zero- or sign-extend if shift is 32 or more.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
-		   (match_operand:SI 2 "const_int_operand" "i")))]
-  "INTVAL (operands[2]) >= 32"
-  "shf %2,%0"
-  [(set_attr "type" "shfl")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ashift:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
-		   (match_operand:SI 2 "const_int_operand" "i")))]
-  "INTVAL (operands[2]) >= 32"
-  "shf %2,%0"
-  [(set_attr "type" "shfl")])
-
-;; Logical right, general
-
-(define_expand "lshrdi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
-  ""
-  "operands[2] = negate_rtx (SImode, operands[2]);")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
-		     (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))]
-  ""
-  "shf %2,%0"
-  [(set_attr "type" "shfl")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "shf #%n2,%0"
-  [(set_attr "type" "shfl")])
-
-;; Arithmetic right, general
-;; Use
-;;     ((a >> b) ^ signbit) - signbit
-;; where signbit is (1 << 63) >> b
-;; Works for 0..63.  Does not work for 64; unfortunate but valid.
-
-(define_expand "ashrdi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))
-   (set (match_dup 3) (lshiftrt:DI (match_dup 3) (neg:SI (match_dup 2))))
-   (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 3)))
-   (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    switch (INTVAL (operands[2]))
-      {
-      case 32:
-	emit_insn (gen_ashrdi3_32 (operands[0], operands[1]));
-	DONE;
-      }
-
-  operands[2] = negate_rtx (SImode, operands[2]);
-  operands[3] = force_reg (DImode, immed_double_const (0, 1 << 31, DImode));
-}")
-
-;; Arithmetic right 32, a common case that can save a couple of insns.
-
-(define_expand "ashrdi3_32"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (const_int 32)))
-   (set (match_dup 0)
-	(sign_extend:DI (subreg:SI (match_dup 0) 0)))]
-  ""
-  "")
-
-;; __builtin instructions
-
-(define_insn "sqrtdf2"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
-  "! TARGET_C1 && flag_fast_math"
-  "sqrt.d %0"
-  [(set_attr "type" "divd")])
-
-(define_insn "sqrtsf2"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
-  "! TARGET_C1 && flag_fast_math"
-  "sqrt.s %0"
-  [(set_attr "type" "divs")])
-
-(define_insn "sindf2"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
-  "! TARGET_C1 && flag_fast_math"
-  "sin.d %0")
-
-(define_insn "sinsf2"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
-  "! TARGET_C1 && flag_fast_math"
-  "sin.s %0")
-
-(define_insn "cosdf2"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
-  "! TARGET_C1 && flag_fast_math"
-  "cos.d %0")
-
-(define_insn "cossf2"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
-  "! TARGET_C1 && flag_fast_math"
-  "cos.s %0")
-
-(define_insn "ftruncdf2"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(fix:DF (match_operand:DF 1 "register_operand" "d")))]
-  "! TARGET_C1"
-  "frint.d %1,%0"
-  [(set_attr "type" "cvtd")])
-
-(define_insn "ftruncsf2"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(fix:SF (match_operand:SF 1 "register_operand" "d")))]
-  "! TARGET_C1"
-  "frint.s %1,%0"
-  [(set_attr "type" "cvts")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
-		  (const_int 1)))]
-  ""
-  "tzc %1,%0\;le.w #32,%0\;jbrs.f L0%=\;ld.w #-1,%0\\nL0%=:")
-
-(define_expand "ffssi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
-		  (const_int 1)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int 1)))]
-  ""
-  "")
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(abs:SF (match_operand:SF 1 "register_operand" "0")))]
-  ""
-  "and #0x7fffffff,%0")
-
-(define_expand "absdf2"
-  [(set (subreg:DI (match_operand:DF 0 "register_operand" "=d") 0)
-	(and:DI (subreg:DI (match_operand:DF 1 "register_operand" "d") 0)
-		(match_dup 2)))]
-  ""
-  "operands[2] = force_reg (DImode,
-                            immed_double_const (-1, 0x7fffffff, DImode));")
-
-;;- Compares
-
-(define_insn "cmpdi"
-  [(set (cc0)
-	(compare (match_operand:DI 0 "register_operand" "d")
-		 (match_operand:DI 1 "register_operand" "d")))]
-  ""
-  "* return output_cmp (operands[0], operands[1], 'l');")
-
-(define_insn ""
-  [(set (cc0) (match_operand:DI 0 "register_operand" "d"))
-   (clobber (match_scratch:DI 1 "=d"))]
-  "next_insn_tests_no_inequality (insn)"
-  "* return output_cmp (operands[0], operands[1], 'L');")
-
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "register_operand" "d,a")
-		 (match_operand:SI 1 "nonmemory_operand" "di,ai")))]
-  ""
-  "* return output_cmp (operands[0], operands[1], 'w');")
-
-(define_insn "cmphi"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "register_operand" "d,a")
-		 (match_operand:HI 1 "nonmemory_operand" "di,ai")))]
-  ""
-  "* return output_cmp (operands[0], operands[1], 'h');")
-
-; cmpqi is intentionally omitted.
-;
-; gcc will sign-extend or zero-extend the operands to the next
-; wider mode, HImode.
-;
-; For reg .cmp. constant, we just go with the halfword immediate
-; instruction.  Perhaps the widening insn can be cse'd or combined away.
-; If not, we're still as good as loading a byte constant into a register
-; to do a reg-reg byte compare.
-;
-; The following patterns pick up cases that can use reg .cmp. reg after all.
-
-(define_insn ""
-  [(set (cc0)
-	(compare
-	 (sign_extend:HI (match_operand:QI 0 "register_operand" "d"))
-	 (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))))]
-  ""
-  "* return output_cmp (operands[0], operands[1], 'b');")
-
-(define_insn ""
-  [(set (cc0)
-	(compare
-	 (ashift:HI (subreg:HI (match_operand:QI 0 "register_operand" "d") 0)
-		    (const_int 8))
-	 (ashift:HI (subreg:HI (match_operand:QI 1 "register_operand" "d") 0)
-		    (const_int 8))))]
-  ""
-  "* return output_cmp (operands[0], operands[1], 'b');")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:QI 0 "register_operand" "d")
-		 (match_operand:QI 1 "register_operand" "d")))]
-  ""
-  "* return output_cmp (operands[0], operands[1], 'b');")
-
-(define_insn ""
-  [(set (cc0) (match_operand:QI 0 "register_operand" "d"))
-   (clobber (match_scratch:QI 1 "=d"))]
-  "next_insn_tests_no_inequality (insn)"
-  "* return output_cmp (operands[0], operands[1], 'B');")
-
-(define_insn ""
-  [(set (cc0) (subreg (match_operand:QI 0 "register_operand" "d") 0))
-   (clobber (match_scratch:QI 1 "=d"))]
-  "next_insn_tests_no_inequality (insn)"
-  "* return output_cmp (operands[0], operands[1], 'B');")
-
-(define_insn ""
-  [(set (cc0)
-	(zero_extend (subreg (match_operand:QI 0 "register_operand" "d") 0)))
-   (clobber (match_scratch:QI 1 "=d"))]
-  "next_insn_tests_no_inequality (insn)"
-  "* return output_cmp (operands[0], operands[1], 'B');")
-
-(define_insn "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "register_operand" "d")
-		 (match_operand:DF 1 "register_operand" "d")))]
-  ""
-  "* return output_cmp (operands[0], operands[1], 'd');")
-
-(define_insn "cmpsf"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "register_operand" "d")
-		 (match_operand:SF 1 "nonmemory_cmpsf_operand" "dF")))]
-  ""
-  "* return output_cmp (operands[0], operands[1], 's');")
-
-;; decrement-and-set-cc0 insns.
-;;
-;; The most important case where we can use the carry bit from an
-;; arithmetic insn to eliminate a redundant compare is the decrement in
-;; constructs like while (n--) and while (--n >= 0).  
-;;
-;; We do it with combine patterns instead of NOTICE_UPDATE_CC because
-;; the decrement needs to be kept at the end of the block during scheduling.
-;; 
-;; These patterns must have memory alternatives because reload refuses
-;; to do output reloads for an insn that sets cc0 (since it does not
-;; want to clobber cc0 with its moves).  Convex moves do not clobber
-;; cc0, but there is no evident way to get reload to know that.
-
-(define_insn ""
-  [(set (cc0)
-	(match_operand:SI 0 "register_operand" "+r,*m"))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  "next_insn_tests_no_inequality (insn)"
-  "*
-{
-  if (which_alternative == 0)
-    {
-      output_cmp (operands[0], constm1_rtx, 'W');
-      return \"add.w #-1,%0\";
-    }
-  else
-    {
-      output_cmp (gen_rtx (REG, SImode, 7), constm1_rtx, 'W');
-      return \"psh.w s7\;ld.w %0,s7\;add.w #-1,s7\;st.w s7,%0\;pop.w s7\";
-    }
-}")
-     
-(define_insn ""
-  [(set (cc0)
-	(plus:SI (match_operand:SI 0 "register_operand" "+r,*m")
-		 (const_int -1)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  "find_reg_note (next_cc0_user (insn), REG_NONNEG, 0)"
-  "*
-{
-  if (which_alternative == 0)
-    {
-      output_cmp (operands[0], const0_rtx, 'W');
-      return \"add.w #-1,%0\";
-    }
-  else
-    {
-      output_cmp (gen_rtx (REG, SImode, 7), const0_rtx, 'W');
-      return \"psh.w s7\;ld.w %0,s7\;add.w #-1,s7\;st.w s7,%0\;pop.w s7\";
-    }
-}")
-
-(define_insn ""
-  [(set (cc0)
-	(match_operand:HI 0 "register_operand" "+r,*m"))
-   (set (match_dup 0)
-	(plus:HI (match_dup 0)
-		 (const_int -1)))]
-  "next_insn_tests_no_inequality (insn)"
-  "*
-{
-  if (which_alternative == 0)
-    {
-      output_cmp (operands[0], constm1_rtx, 'H');
-      return \"add.h #-1,%0\";
-    }
-  else
-    {
-      output_cmp (gen_rtx (REG, HImode, 7), constm1_rtx, 'H');
-      return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\";
-    }
-}")
-     
-(define_insn ""
-  [(set (cc0)
-	(plus:HI (match_operand:HI 0 "register_operand" "+r,*m")
-		 (const_int -1)))
-   (set (match_dup 0)
-	(plus:HI (match_dup 0)
-		 (const_int -1)))]
-  "find_reg_note (next_cc0_user (insn), REG_NONNEG, 0)"
-  "*
-{
-  if (which_alternative == 0)
-    {
-      output_cmp (operands[0], const0_rtx, 'H');
-      return \"add.h #-1,%0\";
-    }
-  else
-    {
-      output_cmp (gen_rtx (REG, HImode, 7), const0_rtx, 'H');
-      return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\";
-    }
-}")
-
-;;- Jumps
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "jbr %l0")
-
-(define_insn "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_condjump (operands[0], \"eq\", 't'); ")
-
-(define_insn "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_condjump (operands[0], \"eq\", 'f'); ")
-
-(define_insn "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_condjump (operands[0], \"le\", 'f'); ")
-
-(define_insn "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_condjump (operands[0], \"leu\", 'f'); ")
-
-(define_insn "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_condjump (operands[0], \"lt\", 't'); ")
-
-(define_insn "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_condjump (operands[0], \"ltu\", 't'); ")
-
-(define_insn "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_condjump (operands[0], \"lt\", 'f'); ")
-
-(define_insn "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_condjump (operands[0], \"ltu\", 'f'); ")
-
-(define_insn "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_condjump (operands[0], \"le\", 't'); ")
-
-(define_insn "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_condjump (operands[0], \"leu\", 't'); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_condjump (operands[0], \"eq\", 'f'); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_condjump (operands[0], \"eq\", 't'); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_condjump (operands[0], \"le\", 't'); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_condjump (operands[0], \"leu\", 't'); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_condjump (operands[0], \"lt\", 'f'); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_condjump (operands[0], \"ltu\", 'f'); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_condjump (operands[0], \"lt\", 't'); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_condjump (operands[0], \"ltu\", 't'); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_condjump (operands[0], \"le\", 'f'); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_condjump (operands[0], \"leu\", 'f'); ")
-
-;;- Calls
-
-(define_expand "call_pop"
-  [(parallel [(call (match_operand:QI 0 "memory_operand" "m")
-		    (match_operand:SI 1 "const_int_operand" "i"))
-	      (match_operand:SI 2 "const_int_operand" "i")
-	      (match_operand:SI 3 "const_int_operand" "i")
-	      (reg:SI 8)])]
-  ""
-  "")
-
-(define_insn ""
-  [(call (match_operand:QI 0 "memory_operand" "m")
-	 (match_operand:SI 1 "const_int_operand" "i"))
-   (match_operand:SI 2 "const_int_operand" "i")
-   (match_operand:SI 3 "const_int_operand" "i")
-   (match_operand:SI 4 "" "")]
-  ""
-  "* return output_call (insn, &operands[0]);")
-
-(define_expand "call_value_pop"
-  [(parallel [(set (match_operand 0 "" "=g")
-		   (call (match_operand:QI 1 "memory_operand" "m")
-			 (match_operand:SI 2 "const_int_operand" "i")))
-	      (match_operand:SI 3 "const_int_operand" "i")
-	      (match_operand:SI 4 "const_int_operand" "i")
-	      (reg:SI 8)])]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand 0 "" "=g")
-	(call (match_operand:QI 1 "memory_operand" "m")
-	      (match_operand:SI 2 "const_int_operand" "i")))
-   (match_operand:SI 3 "const_int_operand" "i")
-   (match_operand:SI 4 "const_int_operand" "i")
-   (match_operand:SI 5 "" "")]
-  ""
-  "* return output_call (insn, &operands[1]); ")
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-                  (const_int 0))
-            (match_operand 1 "" "")
-            (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call_pop (operands[0], const0_rtx,
-				const0_rtx, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-(define_expand "return"
-  [(return)]
-  ""
-  " replace_arg_pushes (); ")
-
-(define_insn ""
-  [(return)]
-  ""
-  "rtn")
-
-(define_expand "prologue"
-  [(const_int 0)]
-  ""
-  "
-{
-  emit_ap_optimizations ();
-  DONE; 
-}")
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "address_operand" "p"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmp %a0")
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
-  ""
-  "jmp %a0")
diff --git a/gcc/config/convex/fixinc.convex b/gcc/config/convex/fixinc.convex
deleted file mode 100755
index 0dc5f30..0000000
--- a/gcc/config/convex/fixinc.convex
+++ /dev/null
@@ -1,416 +0,0 @@
-
-# This is a shell archive.  Remove anything before this line,
-# then unpack it by saving it in a file and typing "sh file".
-#
-# Wrapped by  on Fri Mar 12 08:41:28 CST 1993
-# Contents:  include/ include/limits.h include/math.h include/stddef.h
-#	include/stdlib.h
- 
-echo mkdir - include
-mkdir include
-chmod u=rwx,g=rwx,o=rx include
- 
-echo x - include/limits.h
-sed 's/^@//' > "include/limits.h" <<'@//E*O*F include/limits.h//'
-#ifndef _LIMITS_H
-#define _LIMITS_H
-
-#include_next <limits.h>
-
-/* Minimum and maximum values a `char' can hold.  */
-#ifdef __CHAR_UNSIGNED__
-#undef CHAR_MIN
-#define CHAR_MIN 0
-#undef CHAR_MAX
-#define CHAR_MAX 255
-#endif
-
-#endif /* _LIMITS_H */
-@//E*O*F include/limits.h//
-chmod u=rw,g=rw,o=r include/limits.h
- 
-echo x - include/math.h
-sed 's/^@//' > "include/math.h" <<'@//E*O*F include/math.h//'
-#ifndef _MATH_H
-#define _MATH_H
-
-#include_next <math.h>
-
-#undef HUGE_VAL
-
-#if _IEEE_FLOAT_
-#define HUGE_VAL 1.79769313486231570e+308
-#else
-#define HUGE_VAL 8.98846567431157854e+307
-#endif
-
-#if __OPTIMIZE__ && ! __NO_INLINE
-
-#define frexp(x,y)	__inline_frexp ((x), (y))
-#define ldexp(x,y)	__inline_ldexp ((x), (y))
-#define irint(x)	__inline_irint (x)
-#define frexpf(x,y)	__inline_frexpf ((x), (y))
-#define ldexpf(x,y)	__inline_ldexpf ((x), (y))
-#define irintf(x)	__inline_irintf (x)
-
-#if __convex_c2__ || __convex_c32__ || __convex_c34__ || __convex_c38__
-
-#define atan(x)		__inline_atan (x)
-#define ceil(x)		__inline_ceil (x)
-#define cos(x)		__inline_cos (x)
-#define exp(x)		__inline_exp (x)
-#define floor(x)	__inline_floor (x)
-#define log(x)		__inline_log (x)
-#define log10(x)	__inline_log10 (x)
-#define modf(x,y)	__inline_modf ((x), (y))
-#define rint(x)		__inline_rint (x)
-#define sin(x)		__inline_sin (x)
-#define sqrt(x)		__inline_sqrt (x)
-
-#define atanf(x)	__inline_atanf (x)
-#define ceilf(x)	__inline_ceilf (x)
-#define cosf(x)		__inline_cosf (x)
-#define expf(x)		__inline_expf (x)
-#define floorf(x)	__inline_floorf (x)
-#define logf(x)		__inline_logf (x)
-#define log10f(x)	__inline_log10f (x)
-#define modff(x,y)	__inline_modff ((x), (y))
-#define rintf(x)	__inline_rintf (x)
-#define sinf(x)		__inline_sinf (x)
-#define sqrtf(x)	__inline_sqrtf (x)
-
-#endif /* __convex_c[23*]__ */
-
-#endif /* __OPTIMIZE__ */
-
-static __inline__ __const__ double __inline_atan (double x)
-{
-  double z;
-  __asm__ ("atan.d %0" : "=d" (z) : "0" (x));
-  return z;
-}
-
-static __inline__ __const__ float __inline_atanf (float x)
-{
-  float z;
-  __asm__ ("atan.s %0" : "=d" (z) : "0" (x));
-  return z;
-}
-
-static __inline__ __const__ double __inline_cos (double x)
-{
-  double z;
-  __asm__ ("cos.d %0" : "=d" (z) : "0" (x));
-  return z;
-}
-
-static __inline__ __const__ float __inline_cosf (float x)
-{
-  float z;
-  __asm__ ("cos.s %0" : "=d" (z) : "0" (x));
-  return z;
-}
-
-static __inline__ __const__ double __inline_exp (double x)
-{
-  double z;
-  __asm__ ("exp.d %0" : "=d" (z) : "0" (x));
-  return z;
-}
-
-static __inline__ __const__ float __inline_expf (float x)
-{
-  float z;
-  __asm__ ("exp.s %0" : "=d" (z) : "0" (x));
-  return z;
-}
-
-static __inline__ __const__ double __inline_log (double x)
-{
-  double z;
-  __asm__ ("ln.d %0" : "=d" (z) : "0" (x));
-  return z;
-}
-
-static __inline__ __const__ float __inline_logf (float x)
-{
-  float z;
-  __asm__ ("ln.s %0" : "=d" (z) : "0" (x));
-  return z;
-}
-
-static __inline__ __const__ double __inline_sin (double x)
-{
-  double z;
-  __asm__ ("sin.d %0" : "=d" (z) : "0" (x));
-  return z;
-}
-
-static __inline__ __const__ float __inline_sinf (float x)
-{
-  float z;
-  __asm__ ("sin.s %0" : "=d" (z) : "0" (x));
-  return z;
-}
-
-static __inline__ __const__ double __inline_sqrt (double x)
-{
-  double z;
-  __asm__ ("sqrt.d %0" : "=d" (z) : "0" (x));
-  return z;
-}
-
-static __inline__ __const__ float __inline_sqrtf (float x)
-{
-  float z;
-  __asm__ ("sqrt.s %0" : "=d" (z) : "0" (x));
-  return z;
-}
-
-static __inline__ __const__ double __inline_ceil (double x)
-{
-  double z;
-  __asm__ ("frint.d %1,%0" : "=d" (z) : "d" (x));
-  if (z < x) z += 1.0;
-  return z;
-}
-
-static __inline__ __const__ float __inline_ceilf (float x)
-{
-  float z;
-  __asm__ ("frint.s %1,%0" : "=d" (z) : "d" (x));
-  if (z < x) z += 1.0F;
-  return z;
-}
-
-static __inline__ __const__ double __inline_floor (double x)
-{
-  double z;
-  __asm__ ("frint.d %1,%0" : "=d" (z) : "d" (x));
-  if (z > x) z -= 1.0;
-  return z;
-}
-
-static __inline__ __const__ float __inline_floorf (float x)
-{
-  float z;
-  __asm__ ("frint.s %1,%0" : "=d" (z) : "d" (x));
-  if (z > x) z -= 1.0F;
-  return z;
-}
-
-static __inline__ __const__ double __inline_log10 (double x)
-{
-  return 0.43429448190325182765 * __inline_log (x);
-}
-
-static __inline__ __const__ float __inline_log10f (float x)
-{
-  return 0.43429448190325182765F * __inline_logf (x);
-}
-
-static __inline__ double __inline_modf (double x, double *np)
-{
-  double intpart;
-  __asm__ ("frint.d %1,%0" : "=d" (intpart) : "d" (x));
-  *np = intpart;
-  return x - intpart;
-}
-
-static __inline__ float __inline_modff (float x, float *np)
-{
-  float intpart;
-  __asm__ ("frint.s %1,%0" : "=d" (intpart) : "d" (x));
-  *np = intpart;
-  return x - intpart;
-}
-
-static __inline__ double __inline_frexp (double x, int *np)
-{
-  union u { double d; unsigned long long ll; } u;
-  if ((u.d = x) == 0)
-    *np = 0;
-  else
-    {
-#if _IEEE_FLOAT_
-      *np = ((u.ll >> 52) & 03777) - 01776;
-      u.ll = (u.ll & 0x800fffffffffffffLL) | 0x3fe0000000000000LL;
-#else
-      *np = ((u.ll >> 52) & 03777) - 02000;
-      u.ll = (u.ll & 0x800fffffffffffffLL) | 0x4000000000000000LL;
-#endif
-    }
-  return u.d;
-}
-
-static __inline__ float __inline_frexpf (float x, int *np)
-{
-  union u { float f; unsigned int i; } u;
-  if ((u.f = x) == 0)
-    *np = 0;
-  else
-    {
-#if _IEEE_FLOAT_
-      *np = ((u.i >> 23) & 0377) - 0176;
-      u.i = (u.i & 0x807fffff) | 0x3f000000;
-#else
-      *np = ((u.i >> 23) & 0377) - 0200;
-      u.i = (u.i & 0x807fffff) | 0x40000000;
-#endif
-    }
-  return u.f;
-}
-
-static __inline__ double __inline_ldexp (double x, int n)
-{
-  extern int errno;
-  union { double d; long long ll; unsigned sexp : 12; } u;
-  if ((u.d = x) != 0)
-    {
-      int exp = n + (u.sexp & 03777);
-      long long nn = (long long) n << 52;
-#if _IEEE_FLOAT_
-      if (exp <= 0)
-	u.ll &= 0x8000000000000000LL, errno = 34;
-      else if (exp > 03776)
-	u.ll = u.ll & 0x8000000000000000LL | 0x7fefffffffffffffLL, errno = 34;
-#else
-      if (exp <= 0)
-	u.ll = 0, errno = 34;
-      else if (exp > 03777)
-	u.ll |= 0x7fffffffffffffffLL, errno = 34;
-#endif
-      else
-	u.ll += nn;
-    }
-  return u.d;
-}
-
-static __inline__ float __inline_ldexpf (float x, int n)
-{
-  extern int errno;
-  union { float f; int i; unsigned sexp : 9; } u;
-  if ((u.f = x) != 0)
-    {
-      int exp = n + (u.sexp & 0377);
-      int nn = n << 23;
-#if _IEEE_FLOAT_
-      if (exp <= 0)
-	u.i &= 0x80000000, errno = 34;
-      else if (exp > 0376)
-	u.i = u.i & 0x80000000 | 0x7f7fffff, errno = 34;
-#else
-      if (exp <= 0)
-	u.i = 0, errno = 34;
-      else if (exp > 0377)
-	u.i |= 0x7fffffff, errno = 34;
-#endif
-      else
-	u.i += nn;
-    }
-  return u.f;
-}
-
-static __inline__ __const__ double __inline_rint (double x)
-{
-  double z;
-  union { double d; unsigned long long ll; } u;
-  u.d = x;
-#if _IEEE_FLOAT_
-  u.ll = (u.ll & 0x8000000000000000LL) | 0x3fe0000000000000LL;
-#else
-  u.ll = (u.ll & 0x8000000000000000LL) | 0x4000000000000000LL;
-#endif
-  __asm__ ("frint.d %1,%0" : "=d" (z) : "d" (x + u.d));
-  return z;
-}
-
-static __inline__ __const__ float __inline_rintf (float x)
-{
-  float z;
-  union { float f; unsigned int i; } u;
-  u.f = x;
-#if _IEEE_FLOAT_
-  u.i = (u.i & 0x80000000) | 0x3f000000;
-#else
-  u.i = (u.i & 0x80000000) | 0x40000000;
-#endif
-  __asm__ ("frint.s %1,%0" : "=d" (z) : "d" (x + u.f));
-  return z;
-}
-
-static __inline__ __const__ int __inline_irint (double x)
-{
-  union { double d; unsigned long long ll; } u;
-  u.d = x;
-#if _IEEE_FLOAT_
-  u.ll = (u.ll & 0x8000000000000000LL) | 0x3fe0000000000000LL;
-#else
-  u.ll = (u.ll & 0x8000000000000000LL) | 0x4000000000000000LL;
-#endif
-  return x + u.d;
-}
-
-static __inline__ __const__ int __inline_irintf (float x)
-{
-  union { float f; unsigned int i; } u;
-  u.f = x;
-#if _IEEE_FLOAT_
-  u.i = (u.i & 0x80000000) | 0x3f000000;
-#else
-  u.i = (u.i & 0x80000000) | 0x40000000;
-#endif
-  return x + u.f;
-}
-
-#endif /* _MATH_H */
-@//E*O*F include/math.h//
-chmod u=rw,g=rw,o=r include/math.h
- 
-echo x - include/stddef.h
-sed 's/^@//' > "include/stddef.h" <<'@//E*O*F include/stddef.h//'
-#ifndef _STDDEF_H
-#define _STDDEF_H
-
-#ifndef __WCHAR_T
-#define __WCHAR_T
-
-#ifdef __GNUG__
-/* In C++, wchar_t is a distinct basic type,
-   and we can expect __wchar_t to be defined by cc1plus.  */
-typedef __wchar_t wchar_t;
-#else
-/* In C, cpp tells us which type to make an alias for.  */
-typedef __WCHAR_TYPE__ wchar_t;
-#endif
-
-#endif /* __WCHAR_T */
-
-#include_next <stddef.h>
-
-#endif /* _STDDEF_H */
-@//E*O*F include/stddef.h//
-chmod u=rw,g=rw,o=r include/stddef.h
- 
-echo x - include/stdlib.h
-sed 's/^@//' > "include/stdlib.h" <<'@//E*O*F include/stdlib.h//'
-#ifndef	_STDLIB_H
-#define _STDLIB_H
-
-#if _CONVEX_SOURCE
-
-#define alloca __non_builtin_alloca
-#include_next <stdlib.h>
-#undef alloca
-
-#else
-
-#include_next <stdlib.h>
-
-#endif  /* _CONVEX_SOURCE */
-
-#endif	/* _STDLIB_H */
-@//E*O*F include/stdlib.h//
-chmod u=rw,g=rw,o=r include/stdlib.h
- 
-exit 0
diff --git a/gcc/config/convex/x-convex b/gcc/config/convex/x-convex
deleted file mode 100755
index 8029ac5..0000000
--- a/gcc/config/convex/x-convex
+++ /dev/null
@@ -1,5 +0,0 @@
-# ld can make exe's c2-only if this lib is searched even though not loaded
-CCLIBFLAGS = -tm c1
-
-# Use -pcc to avoid surprises.
-CC = cc -pcc
diff --git a/gcc/config/convex/xm-convex.h b/gcc/config/convex/xm-convex.h
deleted file mode 100755
index aaaa3b1..0000000
--- a/gcc/config/convex/xm-convex.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Configuration for GNU C-compiler for Convex.
-   Copyright (C) 1989, 1993, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* Convex ships /tmp as a separate file system - thus it
-   usually has more free space than /usr/tmp */
-
-#define P_tmpdir	"/tmp/"
-
-/* Convex uses Vax or IEEE floats.
-   Both formats have Vax semantics. */
-
-#define HOST_FLOAT_FORMAT VAX_FLOAT_FORMAT
diff --git a/gcc/config/d10v/abi b/gcc/config/d10v/abi
deleted file mode 100755
index 70ae6dc..0000000
--- a/gcc/config/d10v/abi
+++ /dev/null
@@ -1,131 +0,0 @@
- -*- Text -*-
-
-This document describes the proposed ABI for the d10v.
-
-The register calling convention is:
-
-	+-------+-----------------------+-----------------------+
-	| Reg.  | At prologue		| After epilogue	|
-	+-------+-----------------------+-----------------------+
-	|  R0   | Argument #1           | Return value, word 1  |
-	+-------+-----------------------+-----------------------+
-	|  R1   | Argument #2           | Return value, word 2  |
-	+-------+-----------------------+-----------------------+
-	|  R2   | Argument #3           | Return value, word 3  |
-	+-------+-----------------------+-----------------------+
-	|  R3   | Argument #4           | Return value, word 4  |
-	+-------+-----------------------+-----------------------+
-	|  R4   | Static chain if needed| Don't care		|
-	+-------+-----------------------+-----------------------+
-	|  R5   | Work                  | Don't care		|
-	+-------+-----------------------+-----------------------+
-	|  R6   | Work                  | Previous value	|
-	+-------+-----------------------+-----------------------+
-	|  R7   | Work			| Previous value	|
-	+-------+-----------------------+-----------------------+
-	|  R8   | Work                  | Previous value        |
-	+-------+-----------------------+-----------------------+
-	|  R9   | Work          	| Previous value        |
-	+-------+-----------------------+-----------------------+
-	|  R10  | Work          	| Previous value        |
-	+-------+-----------------------+-----------------------+
-        |  R11  | Frame ptr if needed   | Previous value        |
-	+-------+-----------------------+-----------------------+
-	|  R12  | Work          	| Don't care            |
-	+-------+-----------------------+-----------------------+
-	|  R13  | Return address	| Don't care   	        |
-	+-------+-----------------------+-----------------------+
-        |  R14  | memory base (0)       | memory base (0)       |
-	+-------+-----------------------+-----------------------+
-	|  R15  | Stack pointer 	| Previous value        |
-	+-------+-----------------------+-----------------------+
-	|  A0   | Work		 	| Previous value	|
-	+-------+-----------------------+-----------------------+
-	|  A1   | Work		 	| Previous value	|
-	+-------+-----------------------+-----------------------+
-
-
-The 'int' type is 16 bits, unless the -mint32 switch is used.  The 'long' type
-is always 32 bits, the 'short' type is always 16 bits, and pointers are 16
-bits.
-
-The 'double' type is treated as 'float' and uses 32-bits unless the -mdouble64
-switch is used.  The long double type still uses 64 bits.
-
-If more than 4 words of arguments are passed, they are passed on the stack.
-
-The GCC compiler will omit the frame pointer for all functions except those
-that dynamically grow the stack frame (ie, the GNU extensions of variable sized
-arrays or calls to alloca).  The GCC compiler will always eliminate the
-pseudo argument pointer the compiler synthesizes in favor of the stack or frame
-pointer.
-
-The GCC compiler only passes the static chain when calling nested functions,
-which is a GNU extension.
-
-The stack starts at high memory and descends downward.  The heap starts at the
-end of the bss section and ascends upward.  The stack is assumed to be aligned
-to a word boundary.
-
-Register r14 will be used as the index register in accessing global/static
-variables if no index register is used.  The crt0 that we provide will place a
-zero in it, and the compiler will expect that.
-
-The varargs/stdarg support defines the va_list type as follows:
-
-	typedef struct __va_list_tag {
-	  short *__va_arg_ptr;		/* start of the register save area */
-	  int __va_arg_num;		/* argument number */
-	} va_list[1];
-
-It is an array so that passing it to vprintf and friends passes just a pointer
-to the structure.  Calls to varargs/stdarg functions push the four words
-corresponding to the first four arguments on the stack immediately before
-adjusting the stack pointer any further.
-
-The stack frame when a function is called looks like:
-
-high		|  ....				|
-		+-------------------------------+
-		| Argument word #8		|
-		+-------------------------------+
-		| Argument word #7		|
-		+-------------------------------+
-		| Argument word #6		|
-		+-------------------------------+
-		| Argument word #5		|
-low	SP---->	+-------------------------------+
-
-After the prologue is executed, the stack frame will look like:
-
-high		|  ....				|
-		+-------------------------------+
-		| Argument word #8		|
-		+-------------------------------+
-		| Argument word #7		|
-		+-------------------------------+
-		| Argument word #6		|
-		+-------------------------------+
-		| Argument word #5		|
-	Prev sp	+-------------------------------+
-		|				|
-		| Save for arguments 1..4 if	|
-		| the func. uses stdarg/varargs	|
-		|				|
-		+-------------------------------+
-		|				|
-		| Local variables		|
-		|				|
-		+-------------------------------+
-		|				|
-		| Save area for preserved regs	|
-		|				|
-		+-------------------------------+
-		|				|
-		| alloca space if used		|
-		|				|
-		+-------------------------------+
-		|				|
-		| Space for outgoing arguments	|
-		|				|
-low	SP---->	+-------------------------------+
diff --git a/gcc/config/d10v/d10v.c b/gcc/config/d10v/d10v.c
deleted file mode 100755
index 27deaf7..0000000
--- a/gcc/config/d10v/d10v.c
+++ /dev/null
@@ -1,3880 +0,0 @@
-/* CYGNUS LOCAL -- meissner/d10v abi change */
-/* Subroutines used for Mitsubishi D10V.
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include "system.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#include "tree.h"
-#include "expr.h"
-#include "obstack.h"
-#include "except.h"
-#include "function.h"
-
-/* Operands to compare before the appropriate branch is done.  */
-struct rtx_def *compare_op0;
-struct rtx_def *compare_op1;
-
-/* Whether or not a hard register can accept a register */
-unsigned char hard_regno_mode_ok[ (int)MAX_MACHINE_MODE ][FIRST_PSEUDO_REGISTER];
-
-/* Whether to try and avoid moves between two different modes */
-unsigned char modes_tieable_p[ (NUM_MACHINE_MODES) * (NUM_MACHINE_MODES) ];
-
-/* Map register number to smallest register class.  */
-enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
-
-/* Map class letter into register class */
-enum reg_class reg_class_from_letter[256];
-
-/* Values of the -mbranch-cost=n string.  */
-int d10v_branch_cost = 1;
-char *d10v_branch_cost_string = (char *)0;
-
-/* Values of the -mcond-exec=n string.  */
-int d10v_cond_exec = 4;
-char *d10v_cond_exec_string = (char *)0;
-
-static void d10v_split_constant32 PROTO ((rtx x, int values[]));
-static void d10v_split_constant64 PROTO ((rtx x, int values[]));
-
-/* Cached value of d10v_stack_info */
-static d10v_stack_t *d10v_stack_cache = (d10v_stack_t *)0;
-
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-
-void
-override_options ()
-{
-  int regno, i, ok_p;
-  enum machine_mode mode1, mode2;
-
-  /* Set up the branch cost information */
-  if (d10v_branch_cost_string)
-    d10v_branch_cost = atoi (d10v_branch_cost_string);
-
-  /* Set up max # instructions to use with conditional execution */
-  if (d10v_cond_exec_string)
-    d10v_cond_exec = atoi (d10v_cond_exec_string);
-
-  /* Setup hard_regno_mode_ok/modes_tieable_p */
-  for (mode1 = VOIDmode;
-       (int)mode1 < NUM_MACHINE_MODES;
-       mode1 = (enum machine_mode)((int)mode1 + 1))
-    {
-      int size = GET_MODE_SIZE (mode1);
-      int int_p = GET_MODE_CLASS (mode1) == MODE_INT;
-
-      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-	{
-	  if (mode1 == CCmode || mode1 == CC_REVmode)
-	    ok_p = (regno == F0_REGNUM);
-
-	  else if (CR_P (regno))
-	    ok_p = 0;
-
-	  else if (ACCUM_P (regno))
-	    ok_p = (mode1 == SImode);
-
-	  else if (GPR_P (regno))
-	    {
-	      if (mode1 == QImode || mode1 == HImode)
-		ok_p = 1;
-	      else
-		ok_p = GPR_EVEN_P (regno);
-	    }
-	  else
-	    ok_p = 0;
-
-	  hard_regno_mode_ok[ (int)mode1 ][ regno ] = ok_p;
-	}
-
-      /* A C expression that is nonzero if it is desirable to choose
-	 register allocation so as to avoid move instructions between a
-	 value of mode MODE1 and a value of mode MODE2.
-
-	 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
-	 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
-	 MODE2)' must be zero. */
-      for (mode2 = VOIDmode;
-	   (int)mode2 <= NUM_MACHINE_MODES;
-	   mode2 = (enum machine_mode)((int)mode2 + 1))
-	{
-	  if (mode1 == mode2)
-	    ok_p = 1;
-
-	  else if (mode1 == HImode || mode2 == QImode)
-	    ok_p = (mode2 == HImode || mode2 == QImode);
-
-	  else
-	    ok_p = 0;
-
-	  modes_tieable_p[ ((int)mode1 * (NUM_MACHINE_MODES)) + (int)mode2 ] = ok_p;
-	}
-    }
-
-  /* A C expression whose value is a register class containing hard
-     register REGNO.  In general there is more than one such class;
-     choose a class which is "minimal", meaning that no smaller class
-     also contains the register. */
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-    {
-      enum reg_class class;
-
-      switch (regno)
-	{
-	case GPR_FIRST + 4:
-	case GPR_FIRST + 5:
-	case GPR_FIRST + 6:
-	case GPR_FIRST + 7:
-	case GPR_FIRST + 8:
-	case GPR_FIRST + 9:
-	case GPR_FIRST + 10:
-	case GPR_FIRST + 11:
-	case GPR_FIRST + 12:
-	case GPR_FIRST + 14:
-	case GPR_FIRST + 15:
-	  class = EVEN_REGS;
-	  break;
-
-	case ARG_FIRST + 0:	/* r0 */
-	  class = ARG0_REGS;
-	  break;
-
-	case ARG_FIRST + 1:	/* r1 */
-	  class = ARG1_REGS;
-	  break;
-
-	case ARG_FIRST + 2:	/* r2 */
-	  class = ARG2_REGS;
-	  break;
-
-	case ARG_FIRST + 3:	/* r3 */
-	  class = ARG3_REGS;
-	  break;
-
-	case GPR_FIRST + 13:	/* r13 */
-	  class = RETURN_REGS;
-	  break;
-
-	case AP_FIRST:
-	  class = GENERAL_REGS;
-	  break;
-
-	case ACCUM_FIRST + 0:
-	case ACCUM_FIRST + 1:
-	  class = ACCUM_REGS;
-	  break;
-
-	case CR_FIRST + 7:
-	  class = REPEAT_REGS;
-	  break;
-
-	case CR_FIRST + 0:
-	case CR_FIRST + 1:
-	case CR_FIRST + 2:
-	case CR_FIRST + 3:
-	case CR_FIRST + 4:
-	case CR_FIRST + 5:
-	case CR_FIRST + 6:
-	case CR_FIRST + 8:
-	case CR_FIRST + 9:
-	case CR_FIRST + 10:
-	case CR_FIRST + 11:
-	case CR_FIRST + 12:
-	case CR_FIRST + 13:
-	case CR_FIRST + 14:
-	case CR_FIRST + 15:
-	  class = CR_REGS;
-	  break;
-
-	case F0_REGNUM:
-	  class = F0_REGS;
-	  break;
-
-	case F1_REGNUM:
-	  class = F1_REGS;
-	  break;
-
-	case CARRY_REGNUM:
-	  class = CARRY_REGS;
-	  break;
-	}
-
-      regno_reg_class[regno] = class;
-    }
-
-  /* A C expression which defines the machine-dependent operand
-     constraint letters for register classes.  If CHAR is such a
-     letter, the value should be the register class corresponding to
-     it.  Otherwise, the value should be `NO_REGS'.  The register
-     letter `r', corresponding to class `GENERAL_REGS', will not be
-     passed to this macro; you do not need to handle it.
-
-     The following letters are unavailable, due to being used as
-     constraints:
-	'0'..'9'
-	'<', '>'
-	'E', 'F', 'G', 'H'
-	'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
-	'Q', 'R', 'S', 'T', 'U'
-	'V', 'X'
-	'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
-
-  for (i = 0; i < 256; i++)
-    reg_class_from_letter[i] = NO_REGS;
-
-  reg_class_from_letter['C'] = CARRY_REGS;
-  reg_class_from_letter['a'] = ACCUM_REGS;
-  reg_class_from_letter['b'] = ARG0_REGS;
-  reg_class_from_letter['c'] = CR_REGS;
-  reg_class_from_letter['d'] = GENERAL_REGS;
-  reg_class_from_letter['e'] = EVEN_REGS;
-  reg_class_from_letter['f'] = F0_REGS;
-  reg_class_from_letter['h'] = ARG1_REGS;
-  reg_class_from_letter['j'] = ARG2_REGS;
-  reg_class_from_letter['l'] = RETURN_REGS;
-  reg_class_from_letter['q'] = ARG3_REGS;
-  reg_class_from_letter['x'] = CC_REGS;
-  reg_class_from_letter['y'] = F1_REGS;
-  reg_class_from_letter['z'] = REPEAT_REGS;
-}
-
-
-/* Define this macro if references to a symbol must be treated
-   differently depending on something about the variable or function
-   named by the symbol (such as what section it is in).
-
-   The macro definition, if any, is executed immediately after the
-   rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
-   The value of the rtl will be a `mem' whose address is a
-   `symbol_ref'.
-
-   The usual thing for this macro to do is to record a flag in the
-   `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
-   name string in the `symbol_ref' (if one bit is not enough
-   information). */
-
-void
-encode_section_info (decl)
-     tree decl;
-{
-  /* Mark functions so that we use the @word modifier to get a word
-     address instead of a byte address.  We use the side_effects bit
-     on the identifier node to indicate word addresses are needed.  */
-  if (TREE_CODE (decl) == FUNCTION_DECL)
-    {
-      rtx symref = XEXP (DECL_RTL (decl), 0);
-      tree symid = get_identifier (XSTR (symref, 0));
-
-      SYMBOL_REF_FLAG (symref) = TRUE;
-      TREE_SIDE_EFFECTS (symid) = TRUE;
-    }
-}
-
-
-/* Return true if the register is a GPR */
-
-int
-gpr_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == REG)
-    {
-      int regno = REGNO (op);
-      if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
-	return GPR_P (regno);
-
-      return register_operand (op, mode);
-    }
-
-  else if (GET_CODE (op) == SUBREG)
-    {
-      rtx inner = SUBREG_REG (op);
-      if (GET_CODE (inner) == REG)
-	{
-	  int regno = REGNO (SUBREG_REG (op));
-	  if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
-	    return GPR_P (regno);
-
-	  return register_operand (op, mode);
-	}
-
-      else if (GET_CODE (inner) == MEM && !reload_completed)
-	return d10v_legitimate_address_p (GET_MODE (inner), inner, 0);
-    }
-
-  return FALSE;
-}
-
-/* Return true if the register is an accumulator */
-
-int
-accum_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == REG)
-    {
-      int regno = REGNO (op);
-      if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
-	return ACCUM_P (regno);
-
-      return register_operand (op, mode);
-    }
-
-  else if (GET_CODE (op) == SUBREG)
-    {
-      rtx inner = SUBREG_REG (op);
-      if (GET_CODE (inner) == REG)
-	{
-	  int regno = REGNO (SUBREG_REG (op));
-	  if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
-	    return ACCUM_P (regno);
-
-	  return register_operand (op, mode);
-	}
-
-      else if (GET_CODE (inner) == MEM && !reload_completed)
-	return d10v_legitimate_address_p (GET_MODE (inner), inner, 0);
-    }
-
-  return FALSE;
-}
-
-/* Return true if an operand is a register or is the constant 0.  */
-
-int
-reg_or_0_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return INTVAL (op) == 0;
-
-  else
-    return gpr_operand (op, mode);
-}
-
-/* Return true if an operand is a register or a signed 16-bit constant.  */
-
-int
-arith16_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return IN_RANGE_P (INTVAL (op), -32768, 32767);
-
-  else
-    return gpr_operand (op, mode);
-}
-
-/* Return true if an operand is a register or a  4-bit unsigned constants,
-   or 4-bit negative unsigned constants.  */
-
-int
-arith_4bit_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return IN_RANGE_P (INTVAL (op), -16, 16) && INTVAL (op) != 0;
-
-  else
-    return gpr_operand (op, mode);
-}
-
-/* Return true if an operand is a register or a non negative constant. */
-
-int
-arith_nonnegative_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return (INTVAL (op) >= 0);
-
-  else
-    return gpr_operand (op, mode);
-}
-
-/* Return true if an operand is a register or a signed 32-bit constant.  */
-
-int
-arith32_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return TRUE;
-
-  else
-    return gpr_operand (op, mode);
-}
-
-/* Return true if an operand is a register or a signed 64-bit constant.  */
-
-int
-arith64_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
-    return TRUE;
-
-  else
-    return gpr_operand (op, mode);
-}
-
-/* Return true if an operand is a register or a constant with the lower 16-bits of 0.  */
-
-int
-arith_lower0_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return ((INTVAL (op) & 0xffff) == 0);
-
-  else
-    return gpr_operand (op, mode);
-}
-
-int
-ldi_shift_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (TARGET_SMALL_INSNS && optimize && GET_CODE (op) == CONST_INT)
-    {
-      HOST_WIDE_INT value = INTVAL (op);
-      int i;
-
-      if (IN_RANGE_P (value, -8, 7))
-	return FALSE;
-
-      for (i = 1; i < 16; i++)
-	{
-	  if (((value >> i) << i) == value && IN_RANGE_P (value >> i, -8, 7))
-	    return i;
-	}
-    }
-
-  return FALSE;
-}
-
-/* Return true if the operand is either the PC, a return, or a label_ref.  */
-
-int
-pc_or_label_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (op == pc_rtx)
-    return TRUE;
-
-  if (GET_CODE (op) == LABEL_REF)
-    return TRUE;
-
-  if (GET_CODE (op) == RETURN && direct_return () && (d10v_stack_info ())->total_size == 0)
-    return TRUE;
-
-  return FALSE;
-}
-
-/* Return true if a memory operand is a short memory operand.  */
-
-int
-short_memory_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  rtx addr;
-
-  if (GET_CODE (op) != MEM)
-    return FALSE;
-
-  addr = XEXP (op, 0);
-  switch (GET_CODE (addr))
-    {
-    default:
-      break;
-
-    case POST_INC:
-    case POST_DEC:
-    case PRE_DEC:
-    case REG:
-      return TRUE;
-    }
-
-  return FALSE;
-}
-
-/* Return true if an operand is simple, suitable for use in a conditional move */
-
-int
-cond_move_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
-    return FALSE;
-
-  else if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
-    return gpr_operand (op, mode) || (mode == SImode && accum_operand (op, mode));
-
-  else if (GET_CODE (op) == CONST_INT && (mode == QImode || mode == HImode))
-    return IN_RANGE_P (INTVAL (op), -8, 7);
-
-  /* Don't allow post dec/inc, since we might not get the side effects correct. */
-  else if (GET_CODE (op) == MEM)
-    return (GET_CODE (XEXP (op, 0)) == REG);
-
-  return FALSE;
-}
-
-/* Return true if an operand is simple, suitable for use in conditional execution.
-   Unlike cond_move, we can allow auto inc/dec.  */
-
-int
-cond_exec_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
-    return FALSE;
-
-  else if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
-    return gpr_operand (op, mode) || (mode == SImode && accum_operand (op, mode));
-
-  else if (GET_CODE (op) == CONST_INT && (mode == QImode || mode == HImode))
-    return IN_RANGE_P (INTVAL (op), -8, 7);
-
-  else if (GET_CODE (op) == MEM)
-    return short_memory_operand (op, mode);
-
-  return FALSE;
-}
-
-/* Return true if an operand is F0.  */
-
-int
-carry_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  if (GET_MODE (op) != CCmode && GET_MODE (op) != CC_REVmode)
-    return FALSE;
-
-  if (REGNO (op) != CARRY_REGNUM)
-    return FALSE;
-
-  return 1;
-}
-
-int
-f0_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  if (GET_MODE (op) != CCmode && GET_MODE (op) != CC_REVmode)
-    return FALSE;
-
-  if (REGNO (op) != F0_REGNUM)
-    return FALSE;
-
-  return 1;
-}
-
-/* Return true if an operand is F1.  */
-
-int
-f1_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  if (GET_MODE (op) != CCmode && GET_MODE (op) != CC_REVmode)
-    return FALSE;
-
-  if (REGNO (op) != F1_REGNUM)
-    return FALSE;
-
-  return 1;
-}
-
-/* Return true if an operand is F0 or F1.  */
-
-int
-f_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  if (GET_MODE (op) != CCmode && GET_MODE (op) != CC_REVmode)
-    return FALSE;
-
-  if (REGNO (op) != F0_REGNUM && REGNO (op) != F1_REGNUM)
-    return FALSE;
-
-  return 1;
-}
-
-/* Return true if the code is a test of f0 */
-
-int
-f0_compare_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int i;
-  rtx x;
-
-  if (GET_MODE (op) != CCmode && GET_MODE (op) != CC_REVmode)
-    return FALSE;
-
-  if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
-    return FALSE;
-
-  x = XEXP (op, 0);
-  if (GET_CODE (x) != REG || REGNO (x) != F0_REGNUM)
-    return FALSE;
-
-  x = XEXP (op, 1);
-  if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
-    return FALSE;
-
-  return TRUE;
-}
-
-/* Return true if the code is a relational operations (EQ, LE, etc.)  */
-
-int
-compare_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int i;
-  rtx x;
-
-  if (GET_MODE (op) != CCmode && GET_MODE (op) != CC_REVmode)
-    return FALSE;
-
-  if (GET_RTX_CLASS (GET_CODE (op)) != '<')
-    return FALSE;
-
-  /* Don't allow paradoxical SUBREGs */
-  for (i = 0; i < 2; i++)
-    {
-      x = XEXP (op, i);
-      while (GET_CODE (x) == SUBREG)
-	x = SUBREG_REG (x);
-
-      if (!(GET_CODE (x) == REG || (i == 1 && GET_CODE (x) == CONST_INT)))
-	return FALSE;
-    }
-
-  return TRUE;
-}
-
-/* Return true if the code is a equality operation (EQ, NE) */
-
-int
-equality_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int i;
-  rtx x;
-
-  if (GET_MODE (op) != CCmode && GET_MODE (op) != CC_REVmode)
-    return FALSE;
-
-  switch (GET_CODE (op))
-    {
-    default:
-      return FALSE;
-
-    case EQ:
-    case NE:
-      break;
-    }
-
-  /* Don't allow paradoxical SUBREGs */
-  for (i = 0; i < 2; i++)
-    {
-      x = XEXP (op, i);
-      while (GET_CODE (x) == SUBREG)
-	x = SUBREG_REG (x);
-
-      if (!(GET_CODE (x) == REG || (i == 1 && GET_CODE (x) == CONST_INT)))
-	return FALSE;
-    }
-
-  return TRUE;
-}
-
-/* Return true if the code is a signed relational operations (LT, LE, etc.) */
-
-int
-signed_compare_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int i;
-  rtx x;
-
-  if (GET_MODE (op) != CCmode && GET_MODE (op) != CC_REVmode)
-    return FALSE;
-
-  switch (GET_CODE (op))
-    {
-    default:
-      return FALSE;
-
-    case LT:
-    case LE:
-    case GT:
-    case GE:
-      break;
-    }
-
-  /* Don't allow paradoxical SUBREGs */
-  for (i = 0; i < 2; i++)
-    {
-      x = XEXP (op, i);
-      while (GET_CODE (x) == SUBREG)
-	x = SUBREG_REG (x);
-
-      if (!(GET_CODE (x) == REG || (i == 1 && GET_CODE (x) == CONST_INT)))
-	return FALSE;
-    }
-
-  return TRUE;
-}
-
-/* Return true if the code is a unsigned relational operations (LEU, etc.) */
-
-int
-unsigned_compare_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int i;
-  rtx x;
-
-  if (GET_MODE (op) != CCmode && GET_MODE (op) != CC_REVmode)
-    return FALSE;
-
-  switch (GET_CODE (op))
-    {
-    default:
-      return FALSE;
-
-    case LTU:
-    case LEU:
-    case GTU:
-    case GEU:
-      break;
-    }
-
-  /* Don't allow paradoxical SUBREGs */
-  for (i = 0; i < 2; i++)
-    {
-      x = XEXP (op, i);
-      while (GET_CODE (x) == SUBREG)
-	x = SUBREG_REG (x);
-
-      if (!(GET_CODE (x) == REG || (i == 1 && GET_CODE (x) == CONST_INT)))
-	return FALSE;
-    }
-
-  return TRUE;
-}
-
-/* Return true if the unary operator can go inside of a exef0{f,t} || operation.  */
-
-int
-unary_parallel_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  rtx op0;
-
-  /* Only do this after register allocation, so that we can look at the register # */
-  if (!reload_completed)
-    return FALSE;
-
-  if (GET_RTX_CLASS (GET_CODE (op)) != '1')
-    return FALSE;
-
-  op0 = XEXP (op, 0);
-  while (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-
-  switch (GET_CODE (op))
-    {
-    case NEG:
-    case NOT:
-    case SIGN_EXTEND:
-    case ZERO_EXTEND:
-      if (GET_MODE (op) == HImode && GET_CODE (op0) == REG && GPR_P (REGNO (op0)))
-	return TRUE;
-
-      break;
-    }
-
-  return FALSE;
-}
-
-/* Return true if the binary operator can go inside of a exef0{f,t} || operation.  */
-
-int
-binary_parallel_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  rtx op0, op1;
-
-  /* Only do this after register allocation, so that we can look at the register # */
-  if (!reload_completed)
-    return FALSE;
-
-  if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
-    return FALSE;
-
-  op0 = XEXP (op, 0);
-  op1 = XEXP (op, 1);
-
-  while (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-
-  while (GET_CODE (op1) == SUBREG)
-    op1 = SUBREG_REG (op1);
-
-  if (GET_CODE (op0) != REG)
-    return FALSE;
-
-  /* reg1 op= reg2 */
-  if (GET_CODE (op1) == REG)
-    {
-      switch (GET_CODE (op))
-	{
-	case PLUS:
-	case MINUS:
-	  if (GET_MODE (op) == SImode && GPR_P (REGNO (op0)) && GPR_P (REGNO (op1)))
-	    return TRUE;
-
-	  /* fall through */
-
-	case MULT:
-	case AND:
-	case IOR:
-	case XOR:
-	case ASHIFT:
-	case ASHIFTRT:
-	case LSHIFTRT:
-	  return (GET_MODE (op) == HImode && GPR_P (REGNO (op0)) && GPR_P (REGNO (op1)));
-	}
-    }
-
-  /* reg op= constant */
-  else if (GET_CODE (op1) == CONST_INT)
-    {
-      HOST_WIDE_INT value = INTVAL (op1);
-      int log;
-
-      if (GET_MODE (op) == HImode)
-	switch (GET_CODE (op))
-	  {
-	  case PLUS:
-	  case MINUS:
-	    return IN_RANGE_P (value, -16, 16);
-
-	  case IOR:
-	  case XOR:
-	    if (value == 0)
-	      return TRUE;
-
-	    log = exact_log2 (value);
-	    return IN_RANGE_P (log, 0, 15);
-
-	  case AND:
-	    if ((value & 0xffff) == 0xffff)
-	      return TRUE;
-
-	    log = exact_log2 (~value);
-	    return IN_RANGE_P (log, 0, 15);
-	  }
-    }
-
-  return FALSE;
-}
-
-/* Return true if the {sign,zero} extend operator from memory can go inside
-   of a exef0{f,t} || operation.  */
-
-int
-extend_parallel_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  /* Only do this after register allocation, so that we can look at the register # */
-  if (!reload_completed)
-    return FALSE;
-
-  if (GET_RTX_CLASS (GET_CODE (op)) != '1')
-    return FALSE;
-
-  switch (GET_CODE (op))
-    {
-    case SIGN_EXTEND:
-    case ZERO_EXTEND:
-      if (GET_MODE (op) == HImode && short_memory_operand (XEXP (op, 0), QImode))
-	return TRUE;
-
-      break;
-    }
-
-  return FALSE;
-}
-
-/* Return true if the {smin,smax} operator can go inside of a exef0{f,t} || operation.  */
-
-int
-minmax_parallel_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  /* Only do this after register allocation, so that we can look at the register # */
-  if (!reload_completed)
-    return FALSE;
-
-  if (GET_RTX_CLASS (GET_CODE (op)) != 'c')
-    return FALSE;
-
-  switch (GET_CODE (op))
-    {
-    case SMIN:
-    case SMAX:
-      if (GET_MODE (op) == HImode
-	  && gpr_operand (XEXP (op,0), mode)
-	  && gpr_operand (XEXP (op, 1)))
-	return TRUE;
-
-      if (GET_MODE (op) == SImode
-	  && accum_operand (XEXP (op,0), mode)
-	  && accum_operand (XEXP (op, 1)))
-	return TRUE;
-
-      break;
-    }
-
-  return FALSE;
-}
-
-
-/* Return true if a 32-bit integer constant can be loaded by two parallel
-   ldi constants.  */
-
-int
-parallel_ldi (value)
-     HOST_WIDE_INT value;
-{
-  int low = SIGN_EXTEND_SHORT (value);
-  int high = SIGN_EXTEND_SHORT (value >> 16);
-
-  return IN_RANGE_P (low, -8, 7) && IN_RANGE_P (high, -8, 7);
-}
-
-
-/* Return true if the two operands reference adjacement memory locations so that
-   a ld2w/st2w instruction can be used.  The insn argument is the last insn of
-   the peephole, so that REG_DEAD notes are useful.  */
-
-int
-adjacent_memory_operands (op1, op2, insn)
-     rtx op1;
-     rtx op2;
-     rtx insn;
-{
-  rtx addr1, addr2;
-  rtx const1, const2;
-  enum rtx_code code1, code2;
-
-  if (GET_CODE (op1) != MEM || GET_MODE (op1) != HImode)
-    return FALSE;
-
-  if (GET_CODE (op2) != MEM || GET_MODE (op2) != HImode)
-    return FALSE;
-
-  addr1 = XEXP (op1, 0);
-  addr2 = XEXP (op2, 0);
-  code1 = GET_CODE (addr1);
-  code2 = GET_CODE (addr2);
-  if (((code1 == POST_INC && code2 == POST_INC))
-      || ((code1 == POST_DEC && code2 == POST_DEC))
-      || ((code1 == PRE_DEC && code2 == PRE_DEC)))
-    {
-      addr1 = XEXP (addr1, 0);
-      addr2 = XEXP (addr2, 0);
-      return (GET_CODE (addr1) == REG && GET_CODE (addr2) == REG
-	      && REGNO (addr1) == REGNO (addr2));
-    }
-
-  else if ((code1 == POST_INC || code1 == POST_DEC || code1 == PRE_DEC)
-	   && code2 != POST_INC && code2 != POST_DEC && code2 != PRE_DEC)
-    {
-      addr1 = XEXP (addr1, 0);
-      return (GET_CODE (addr1) == REG && code2 == REG
-	      && REGNO (addr1) == REGNO (addr2)
-	      && find_reg_note (insn, REG_DEAD, addr1)); 
-    }
-
-  else if (code1 == POST_INC || code1 == POST_DEC || code1 == PRE_DEC
-	   || code2 == POST_INC || code2 == POST_DEC || code2 == PRE_DEC)
-    return FALSE;
-
-  if (code1 == CONST)
-    addr1 = XEXP (addr1, 0);
-
-  if (code2 == CONST)
-    code2 = GET_CODE (addr2);
-
-  const1 = const0_rtx;
-  const2 = const0_rtx;
-  addr1 = eliminate_constant_term (addr1, &const1);
-  addr2 = eliminate_constant_term (addr2, &const2);
-
-  if (!rtx_equal_p (addr1, addr2))
-    return FALSE;
-
-  if (GET_CODE (const1) == CONST_INT
-      && GET_CODE (const2) == CONST_INT
-      && INTVAL (const1) == INTVAL (const2) - 2)
-    return TRUE;
-
-  return FALSE;
-}
-
-
-/* Expand a divmod operation */
-
-void
-d10v_expand_divmod (operands, unsigned_p)
-     rtx operands[];
-     int unsigned_p;
-{
-  rtx ret = emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, (unsigned_p) ? "__udivmodhi4" : "__divmodhi4"),
-				     NULL_RTX, TRUE, SImode, 2,
-				     operands[1], HImode,
-				     operands[2], HImode);
-
-  emit_move_insn (operands[0], gen_rtx (SUBREG, HImode, ret, 1));
-  emit_move_insn (operands[3], gen_rtx (SUBREG, HImode, ret, 0));
-}
-
-
-/* A C statement to initialize the variable parts of a trampoline.
-   ADDR is an RTX for the address of the trampoline; FNADDR is an RTX
-   for the address of the nested function; STATIC_CHAIN is an RTX for
-   the static chain value that should be passed to the function when
-   it is called. */
-
-void
-initialize_trampoline (addr, fnaddr, static_chain)
-     rtx addr;
-     rtx fnaddr;
-     rtx static_chain;
-{
-  rtx byte_addr = gen_reg_rtx (Pmode);
-  rtx reg1 = gen_reg_rtx (Pmode);
-  rtx reg2 = gen_reg_rtx (Pmode);
-
-  emit_move_insn (byte_addr, addr);
-
-  /* ldi.l r7,<static chain> */
-  emit_move_insn (gen_rtx (MEM, HImode, gen_rtx (POST_INC, HImode, byte_addr)),
-		  GEN_INT (0xE000 | ((STATIC_CHAIN_REGNUM - GPR_FIRST) << 4)));
-
-  emit_move_insn (gen_rtx (MEM, HImode, gen_rtx (POST_INC, HImode, byte_addr)),
-		  static_chain);
-
-  /* bra.l <function> */
-  emit_move_insn (gen_rtx (MEM, HImode, gen_rtx (POST_INC, HImode, byte_addr)),
-		  GEN_INT (0xE400));
-
-  emit_move_insn (reg1, fnaddr);
-  emit_move_insn (reg2, addr);
-  emit_insn (gen_subhi3 (reg1, reg1, reg2));
-  emit_move_insn (gen_rtx (MEM, HImode, byte_addr), reg1);
-
-  error ("Trampolines currently don't work");
-}
-
-
-/* Emit the appropriate comparison code for two operands.  Return TRUE if
-   F0 contains a true value for the condition to be successful, FALSE if
-   not.
-
-   Arguments:
-
-	code		Which comparison to emit
-	op{0,1}		Operands
-	temp		Temporary register that we can clobber (not used right now)
-	insn		Whole insn
-	mode		Mode of the operands
-	output_p	Whether to actually emit code or just return true/false.  */
-
-int
-emit_comparison (code, op0, op1, temp, insn, mode, output_p)
-     enum rtx_code code;
-     rtx op0, op1, temp, insn;
-     enum machine_mode mode;
-     int output_p;
-{
-  int ret = FALSE;
-  char *template = (char *)0;
-  int op1_int_p = CONSTANT_P (op1);
-  rtx xop[10];
-
-  /* Skip subregs that we find.  */
-  while (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-
-  while (GET_CODE (op1) == SUBREG)
-    op1 = SUBREG_REG (op1);
-
-  xop[0] = op0;
-  xop[1] = op1;
-  xop[2] = temp;
-
-  /* 16-bit comparisons */
-  if (mode == HImode)
-    {
-      switch (code)
-	{
-	default:
-	  break;
-
-	case EQ:
-	  template = (!op1_int_p) ? "cmpeq %0,%1" : "cmpeqi %0,%1";
-	  ret = TRUE;
-	  break;
-
-	case NE:
-	  template = (!op1_int_p) ? "cmpeq %0,%1" : "cmpeqi %0,%1";
-	  ret = FALSE;
-	  break;
-
-	case LT:
-	  template = (!op1_int_p) ? "cmp %0,%1" : "cmpi %0,%1";
-	  ret = TRUE;
-	  break;
-
-	case LE:
-	  if (!op1_int_p)
-	    {			/* convert LE x,y to !GT x,y (ie, LT y,x) */
-	      template = "cmp %1,%0";
-	      ret = FALSE;
-	      break;
-	    }
-	  else if (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 32767)
-	    {
-	      /* If some sum of a symbol/label and a constant ends up
-		 as 32768, it would be the linker's task to fix that up.  */
-	      if (output_p)
-		xop[3] = plus_constant_for_output (op1, 1);
-
-	      template = "cmpi %0,%3";
-	      ret = TRUE;
-	      break;
-	    }
-	  else
-	    {
-	      template = "cmpeqi %0,%1";
-	      ret = TRUE;
-	      break;
-	    }
-
-	case GT:
-	  if (!op1_int_p)
-	    {			/* convert GT x,y to LT y,x */
-	      template = "cmp %1,%0";
-	      ret = TRUE;
-	      break;
-	    }
-	  else if (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 32767)
-	    {
-	      if (output_p)
-		xop[3] = plus_constant_for_output (op1, 1);
-
-	      template = "cmpi %0,%3";
-	      ret = FALSE;
-	      break;
-	    }
-	  else
-	    {
-	      template = "cmpeq %0,%0";
-	      ret = FALSE;
-	      break;
-	    }
-
-	case GE:
-	  template = (!op1_int_p) ? "cmp %0,%1" : "cmpi %0,%1";
-	  ret = FALSE;
-	  break;
-
-	case LTU:
-	  template = (!op1_int_p) ? "cmpu %0,%1" : "cmpui %0,%1";
-	  ret = TRUE;
-	  break;
-
-	case LEU:
-	  if (!op1_int_p)
-	    {			/* convert LEU x,y to !GTU x,y (ie, LTU y,x) */
-	      template = "cmpu %1,%0";
-	      ret = FALSE;
-	      break;
-	    }
-	  else if (GET_CODE (op1) != CONST_INT || ~INTVAL (op1) & 65535)
-	    {
-	      if (output_p)
-		xop[3] = plus_constant_for_output (op1, 1);
-
-	      template = "cmpui %0,%3";
-	      ret = TRUE;
-	      break;
-	    }
-	  else
-	    {
-	      template = "cmpeq %0,%0";
-	      ret = TRUE;
-	      break;
-	    }
-
-	case GTU:
-	  if (!op1_int_p)
-	    {			/* convert GTU x,y to LTU y,x */
-	      template = "cmpu %1,%0";
-	      ret = TRUE;
-	      break;
-	    }
-	  else if (GET_CODE (op1) != CONST_INT || ~INTVAL (op1) & 65535)
-	    {			/* convert GTU x,y to !LTU x,y+1 */
-	      if (output_p)
-		xop[3] = plus_constant_for_output (op1, 1);
-
-	      template = "cmpui %0,%3";
-	      ret = FALSE;
-	      break;
-	    }
-	  else
-	    {
-	      /* Convert GTU x,65535 to !EQ x,x */
-	      template = "cmpeq %0,%0";
-	      ret = FALSE;
-	      break;
-	    }
-
-	case GEU:
-	  template = (!op1_int_p) ? "cmpu %0,%1" : "cmpui %0,%1";
-	  ret = FALSE;
-	  break;
-	}
-    }
-
-  /* 32-bit comparisons in the accumulators. */
-  else if (mode == SImode
-	   && GET_CODE (op0) == REG && ACCUM_P (REGNO (op0))
-	   && GET_CODE (op1) == REG && ACCUM_P (REGNO (op1)))
-    {
-      switch (code)
-	{
-	default:
-	  break;
-
-	case EQ:
-	  template = "cmpeq %0,%1";
-	  ret = TRUE;
-	  break;
-
-	case NE:
-	  template = "cmpeq %0,%1";
-	  ret = FALSE;
-	  break;
-
-	case LT:
-	  template = "cmp %0,%1";
-	  ret = TRUE;
-	  break;
-
-	case LE:
-	  /* convert LE x,y to !GT x,y (ie, LT y,x) */
-	  template = "cmp %1,%0";
-	  ret = FALSE;
-	  break;
-
-	case GT:
-	  /* convert GT x,y to LT y,x */
-	  template = "cmp %1,%0";
-	  ret = TRUE;
-	  break;
-
-	case GE:
-	  template = "cmp %0,%1";
-	  ret = FALSE;
-	  break;
-	}
-    }
-
-  /* 32-bit comparisons in the general purpose registers. */
-  else if (mode == SImode
-	   && GET_CODE (op0) == REG && GPR_OR_PSEUDO_P (REGNO (op0))
-	   && GET_CODE (op1) == REG && GPR_OR_PSEUDO_P (REGNO (op1)))
-    {
-      switch (code)
-	{
-	default:
-	  break;
-
-	case EQ:
-	  template = "cmpeq %U0,%U1\n\texef0t || cmpeq %L0,%L1";
-	  ret = TRUE;
-	  break;
-
-	case NE:
-	  template = "cmpeq %U0,%U1\n\texef0t || cmpeq %L0,%L1";
-	  ret = FALSE;
-	  break;
-
-	case LT:
-	  template = "cmpeq %U0,%U1\n\tcmp %U0,%U1\n\texef1t || cmpu %L0,%L1";
-	  ret = TRUE;
-	  break;
-
-	case LE:
-	  /* convert LE x,y to !GT x,y (ie, LT y,x) */
-	  template = "cmpeq %U1,%U0\n\tcmp %U1,%U0\n\texef1t || cmpu %L1,%L0";
-	  ret = FALSE;
-	  break;
-
-	case GT:
-	  /* convert GT x,y to LT y,x */
-	  template = "cmpeq %U1,%U0\n\tcmp %U1,%U0\n\texef1t || cmpu %L1,%L0";
-	  ret = TRUE;
-	  break;
-
-	case GE:
-	  /* convert GE x,y to !LT x,y */
-	  template = "cmpeq %U0,%U1\n\tcmp %U0,%U1\n\texef1t || cmpu %L0,%L1";
-	  ret = FALSE;
-	  break;
-
-	case LTU:
-	  template = "cmpeq %U0,%U1\n\tcmpu %U0,%U1\n\texef1t || cmpu %L0,%L1";
-	  ret = TRUE;
-	  break;
-
-	case LEU:
-	  /* convert LEU x,y to !GTU x,y (ie, LTU y,x) */
-	  template = "cmpeq %U1,%U0\n\tcmpu %U1,%U0\n\texef1t || cmpu %L1,%L0";
-	  ret = FALSE;
-	  break;
-
-	case GTU:
-	  /* convert GTU x,y to LTU y,x */
-	  template = "cmpeq %U1,%U0\n\tcmpu %U1,%U0\n\texef1t || cmpu %L1,%L0";
-	  ret = TRUE;
-	  break;
-
-	case GEU:
-	  /* convert GEU x,y to !LTU x,y */
-	  template = "cmpeq %U0,%U1\n\tcmpu %U0,%U1\n\texef1t || cmpu %L0,%L1";
-	  ret = FALSE;
-	  break;
-	}
-    }
-
-  /* 32-bit comparison against 0 in the general purpose registers. */
-  else if (mode == SImode
-	   && GET_CODE (op0) == REG && GPR_OR_PSEUDO_P (REGNO (op0))
-	   && GET_CODE (op1) == CONST_INT && INTVAL (op1) == 0)
-    {
-      switch (code)
-	{
-	default:
-	  break;
-
-	case EQ:
-	case LEU:	/* convert LEU x,0 to EQ x,0 */
-	  template = "cmpeqi %U0,0\n\texef0t || cmpeqi %L0,0";
-	  ret = TRUE;
-	  break;
-
-	case NE:
-	case GTU:	/* convert GTU x,0 to NE x,0 */
-	  template = "cmpeqi %U0,0\n\texef0t || cmpeqi %L0,0";
-	  ret = FALSE;
-	  break;
-
-	case LT:
-	  template = "cmpi %U0,0";
-	  ret = TRUE;
-	  break;
-
-	case LE:
-	  template = "cmpeqi %U0,0\n\tcmpi %U0,0\n\texef1t || cmpeqi %L0,0";
-	  ret = TRUE;
-	  break;
-
-	case GT:
-	  /* convert GT x,0 to !LE x,0 */
-	  template = "cmpeqi %U0,0\n\tcmpi %U0,0\n\texef1t || cmpeqi %L0,0";
-	  ret = FALSE;
-	  break;
-
-	case GE:
-	  /* convert GE x,0 to !LT x,0 */
-	  template = "cmpi %U0,0\n";
-	  ret = FALSE;
-	  break;
-
-	case LTU:
-	  /* LTU x,0 is always false */
-	  template = "cmpeq %U0,%U0";
-	  ret = FALSE;
-	  break;
-
-	case GEU:
-	  /* GEU x,0 is always true */
-	  template = "cmpeq %U0,%U0";
-	  ret = TRUE;
-	  break;
-	}
-    }
-
-  /* 32-bit comparison against a constant with -8..7 in the lower 16 bits */
-  else if (mode == SImode
-	   && GET_CODE (op0) == REG && GPR_OR_PSEUDO_P (REGNO (op0))
-	   && GET_CODE (op1) == CONST_INT
-	   && IN_RANGE_P (SIGN_EXTEND_SHORT (INTVAL (op1)), -8, 7))
-    {
-      switch (code)
-	{
-	default:
-	  break;
-
-	case EQ:
-	  template = "cmpeqi %U0,%U1\n\texef0t || cmpeqi %L0,%L1";
-	  ret = TRUE;
-	  break;
-
-	case NE:
-	  template = "cmpeqi %U0,%U1\n\texef0t || cmpeqi %L0,%L1";
-	  ret = FALSE;
-	  break;
-	}
-    }
-
-  /* Abort on unhandled cases.  */
-  if (!template)
-    {
-      if (!insn)
-	insn = gen_rtx (SET, VOIDmode,
-			gen_rtx (REG, CCmode, F0_REGNUM),
-			gen_rtx (code, CCmode, op0, op1));
-
-      fatal_insn ("emit_comparison:", insn);
-      return TRUE;
-    }
-
-  /* If we are outputing, do it now.  */
-  if (output_p)
-    output_asm_insn (template, xop);
-
-  return ret;
-}
-
-
-/* Returns a mode from class `MODE_CC' to be used when comparison
-   operation code OP is applied to rtx X and Y.  For example, on the
-   Sparc, `SELECT_CC_MODE' is defined as (see *note Jump Patterns::.
-   for a description of the reason for this definition)
-
-        #define SELECT_CC_MODE(OP,X,Y) \
-          (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT          \
-           ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode)    \
-           : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS    \
-               || GET_CODE (X) == NEG) \
-              ? CC_NOOVmode : CCmode))
-
-   You need not define this macro if `EXTRA_CC_MODES' is not defined. */
-int
-select_cc_mode (op, x, y)
-     enum rtx_code op;
-     rtx x;
-     rtx y;
-{
-  int ret = emit_comparison (op, x, y, NULL_RTX, NULL_RTX, GET_MODE (x), FALSE);
-
-  fprintf (stderr, "select_cc_mode: emit_comparison returned %d\n", ret);
-  debug_rtx (x);
-  debug_rtx (y);
-
-  return (ret ? (int)CCmode : (int)CC_REVmode);
-}
-
-
-/* Emit the code to set F0 based on comparing op0 and op1.  Use CCmode for
-   comparisons that set F0 to 1 if the comparison is true, and CC_REVmode
-   for comparisons that set F0 to 0 if the comparison is true.  */
-
-Rtx
-expand_comparison (code, op0, op1, reg_p)
-     enum rtx_code code;
-     rtx op0;
-     rtx op1;
-     rtx *reg_p;
-{
-  rtx f0, seq;
-  enum machine_mode mode;
-
-  start_sequence ();
-  if (GET_MODE (op0) == DImode)
-    {
-      int unsigned_p = (code == GTU || code == GEU || code == LTU || code == LEU);
-
-      if (op1 == CONST0_RTX (DImode))
-	op0 = emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, (unsigned_p) ? "__ucmpdi0" : "__cmpdi0"),
-				       NULL_RTX, TRUE, HImode, 1, op0, DImode);
-      else
-	op0 = emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, (unsigned_p) ? "__ucmpdi" : "__cmpdi"),
-				       NULL_RTX, TRUE, HImode, 2,
-				       op0, DImode,
-				       op1, DImode);
-
-      op1 = const1_rtx;
-    }
-
-  mode = (emit_comparison (code, op0, op1, NULL_RTX, NULL_RTX, GET_MODE (op0), FALSE) ? CCmode : CC_REVmode);
-  f0 = gen_rtx (REG, mode, F0_REGNUM);
-
-  emit_insn (gen_rtx (SET, VOIDmode, f0, gen_rtx (code, mode, op0, op1)));
-  seq = gen_sequence ();
-  end_sequence ();
-
-  *reg_p = f0;
-  return seq;
-}
-
-
-/* Emit the instructions to move 1 word.  */
-
-char *
-emit_move_word (op0, op1, insn)
-     rtx op0;
-     rtx op1;
-     rtx insn;
-{
-  char *ret = "";
-  int shift;
-
-  if (REG_P (op0) && REG_P (op1))
-    {
-      int reg0 = REGNO (op0);
-      int reg1 = REGNO (op1);
-
-      if (GPR_P (reg0) && GPR_P (reg1))
-	ret = "mv %0,%1";
-
-      else if (GPR_P (reg0) && CR_P (reg1))
-	ret = "mvfc %0,%1";
-
-      else if (CR_P (reg0) && GPR_P (reg1))
-	ret = "mvtc %1,%0";
-
-      else if (GPR_P (reg0) && reg1 == F0_REGNUM)
-	ret = "setf0t %0";
-
-      else
-	fatal_insn ("emit_move_word:", insn);
-    }
-
-  else if (REG_P (op0) && GPR_P (REGNO (op0)) && GET_CODE (op1) == MEM)
-    ret = "ld %0,%M1";
-
-  else if (GET_CODE (op0) == MEM && REG_P (op1) && GPR_P (REGNO (op1)))
-    ret = "st %1,%M0";
-
-  else if (GET_CODE (op0) == MEM && GET_CODE (op1) == CONST_INT && INTVAL (op1) == 0)
-    ret = "st %.,%M0";
-
-  /* XXX: We should do LABEL_REF's that are not part switch statements with the
-     @word modifier, but if we do, that breaks switch statements which need to
-     index into the array of labels.  Using casesi is clumsy because it converts
-     the switch value to SI before the call.  */
-  else if (REG_P (op0) && GPR_P (REGNO (op0))
-	   && GET_CODE (op1) == SYMBOL_REF && SYMBOL_REF_FLAG (op1))
-    ret = "ldi %0,%1@word";
-
-  else if (REG_P (op0) && GPR_P (REGNO (op0))
-	   && GET_CODE (op1) == CONST_INT
-	   && ldi_shift_operand (op1, HImode))
-    ret = "ldi %0,%s1\n\tslli %0,%S1";
-
-  else if (REG_P (op0) && GPR_P (REGNO (op0))
-	   && (GET_CODE (op1) == CONST_INT
-	       || GET_CODE (op1) == SYMBOL_REF
-	       || GET_CODE (op1) == LABEL_REF
-	       || GET_CODE (op1) == CONST))
-    ret = "ldi %0,%1";
-
-  else
-    fatal_insn ("emit_move_word:", insn);
-
-  return ret;
-}
-
-
-
-/* Emit the instructions to move 2 words.  */
-
-char *
-emit_move_2words (op0, op1, insn)
-     rtx op0;
-     rtx op1;
-     rtx insn;
-{
-  char *ret = "";
-
-  if (REG_P (op0) && REG_P (op1))
-    {
-      int reg0 = REGNO (op0);
-      int reg1 = REGNO (op1);
-
-      if (GPR_P (reg0) && GPR_P (reg1))
-	ret = "mv2w %0,%1";
-
-      else if (GPR_P (reg0) && ACCUM_P (reg1))
-	ret = "mv2wfac %0,%1";
-
-      else if (ACCUM_P (reg0) && GPR_P (reg1))
-	ret = "mv2wtac %1,%0";
-
-      else
-	fatal_insn ("emit_move_2words:", insn);
-    }
-
-  else if (REG_P (op0) && GPR_P (REGNO (op0)) && GET_CODE (op1) == MEM)
-    ret = "ld2w %0,%M1";
-
-  else if (GET_CODE (op0) == MEM && REG_P (op1) && GPR_P (REGNO (op1)))
-    ret = "st2w %1,%M0";
-
-  else if (REG_P (op0) && GPR_P (REGNO (op0))
-	   && (GET_CODE (op1) == CONST_INT || GET_CODE (op1) == CONST_DOUBLE))
-    ret = "#";
-
-  else if (REG_P (op0) && ACCUM_P (REGNO (op0)) && GET_CODE (op1) == CONST_INT && INTVAL (op1) == 0)
-    ret = "clrac %0";
-
-  else
-    fatal_insn ("emit_move_2words:", insn);
-
-  return ret;
-}
-
-
-
-/* Emit the instructions to move 4 words.  */
-
-char *
-emit_move_4words (op0, op1, tmp_si, tmp_hi, insn)
-     rtx op0;
-     rtx op1;
-     rtx tmp_si;
-     rtx tmp_hi;
-     rtx insn;
-{
-  char *ret = "";
-  int gpr0_p = (REG_P (op0) && GPR_P (REGNO (op0)));
-  int gpr1_p = (REG_P (op1) && GPR_P (REGNO (op1)));
-  int mem0_p = (GET_CODE (op0) == MEM);
-  int mem1_p = (GET_CODE (op1) == MEM);
-  int const1_p = (GET_CODE (op1) == CONST_INT || GET_CODE (op1) == CONST_DOUBLE);
-
-  /* Check for overlap */
-  if (gpr0_p && refers_to_regno_p (REGNO (op0), REGNO (op0)+2, op1, (rtx *)0))
-    {
-      if (TARGET_DEBUG_MOVE4)
-	{
-	  fprintf (stderr, "\n%s: overlap found in emit_move_4words\n",
-		   IDENTIFIER_POINTER (DECL_NAME (current_function_decl)));
-	  debug_rtx (insn);
-	  fprintf (stderr, "----------\n");
-	}
-
-      if (gpr1_p)
-	{
-	  if (REGNO (op0) == REGNO (op1) + 2)
-	    ret = "mv2w %C0,%C1\n\tmv2w %A0,%A1";
-	  else
-	    ret = "mv2w %A0,%A1\n\tmv2w %C0,%C1";
-	}
-
-      else if (mem1_p)
-	ret = "ld2w %C0,%C1\n\tld2w %A0,%A1";
-
-      else
-	fatal_insn ("move 4 words overlap", insn);
-    }
-
-  else if (gpr0_p && gpr1_p)
-    {
-      if (REGNO (op0) == REGNO (op1) + 2)
-	ret = "mv2w %C0,%C1\n\tmv2w %A0,%A1";
-      else
-	ret = "mv2w %A0,%A1\n\tmv2w %C0,%C1";
-    }
-
-  else if (gpr0_p && mem1_p)
-    {
-      /* If we use post increment/post decrement, it allows the second instruction
-	 to also be a 16-bit instruction */
-      rtx addr = XEXP (op1, 0);
-
-      if (GET_CODE (addr) == REG && REGNO (addr) != STACK_POINTER_REGNUM
-	  && !IN_RANGE_P (REGNO (addr), REGNO (op0), REGNO (op0)+3))
-	ret = "ld2w %A0,@%1+\n\tld2w %C0,@%1-";
-
-      else if (GET_CODE (addr) == REG && REGNO (addr) != STACK_POINTER_REGNUM
-	       && IN_RANGE_P (REGNO (addr), REGNO (op0)+2, REGNO (op0)+3))
-	ret = "ld2w %A0,@%1+\n\tld2w %C0,@%1";
-
-      else
-	ret = "ld2w %A0,%A1\n\tld2w %C0,%C1";
-    }
-
-  else if (mem0_p && gpr1_p)
-    {
-      /* If we use post increment/post decrement, it allows the second instruction
-	 to also be a 16-bit instruction */
-      rtx addr = XEXP (op0, 0);
-
-      if (GET_CODE (addr) == REG && REGNO (addr) != STACK_POINTER_REGNUM
-	  && !IN_RANGE_P (REGNO (addr), REGNO (op1), REGNO (op1)+3))
-	ret = "st2w %A1,@%0+\n\tst2w %C1,@%0-";
-      else
-	ret = "st2w %A1,%A0\n\tst2w %C1,%C0";
-    }
-
-  else if (mem0_p && mem1_p)
-    {
-      if (TARGET_DEBUG_MOVE4)
-	{
-	  fprintf (stderr, "\n%s: memory to memory move in emit_move_4wordsn",
-		   IDENTIFIER_POINTER (DECL_NAME (current_function_decl)));
-
-	  debug_rtx (insn);
-	  fprintf (stderr, "----------\n");
-	}
-
-      /* Check for the scratch space overlapping registers used for pointers.  */
-      if (GET_CODE (tmp_si) == REG && GET_MODE (tmp_si) == SImode)
-	{
-	  int reg = REGNO (tmp_si);
-
-	  if (refers_to_regno_p (reg, reg+2, op0, (rtx *)0)
-	      || refers_to_regno_p (reg, reg+2, op1, (rtx *)0))
-	    {
-	      if (!refers_to_regno_p (reg, reg+1, op0, (rtx *)0)
-		  && !refers_to_regno_p (reg, reg+1, op1, (rtx *)0))
-		{
-		  tmp_si = NULL_RTX;
-		  tmp_hi = gen_rtx (REG, HImode, reg);
-		}
-	      else if (!refers_to_regno_p (reg+1, reg+2, op0, (rtx *)0)
-		       && !refers_to_regno_p (reg+1, reg+2, op1, (rtx *)0))
-		{
-		  tmp_si = NULL_RTX;
-		  tmp_hi = gen_rtx (REG, HImode, reg+1);
-		}
-	      else
-		fatal_insn ("emit_move_4words:", insn);
-	    }
-	}
-      else if (GET_CODE (tmp_hi) == REG && GET_MODE (tmp_hi) == HImode)
-	{
-	  if (refers_to_regno_p (REGNO (tmp_hi), REGNO (tmp_hi)+1, op0, (rtx *)0)
-	      || refers_to_regno_p (REGNO (tmp_hi), REGNO (tmp_hi)+1, op1, (rtx *)0))
-	    fatal_insn ("emit_move_4words:", insn);
-	}
-
-      if (tmp_si && GET_CODE (tmp_si) == REG && GET_MODE (tmp_si) == SImode)
-	ret = "ld2w %2,%A1\n\tst2w %2,%A0\n\tld2w %2,%C1\n\tst2w %2,%C0";
-
-      else if (tmp_hi && GET_CODE (tmp_hi) == REG && GET_MODE (tmp_hi) == HImode)
-	ret = "ld %3,%A1\nst %3,%A0\nld %3,%B1\nst %3,%B0\nld %3,%C1\nst %3,%C0\nld %3,%D1\nst %3,%D0\n";
-
-      else
-	fatal_insn ("emit_move_4words:", insn);
-    }
-
-  else if (gpr0_p
-	   && (GET_CODE (op1) == CONST_INT || GET_CODE (op1) == CONST_DOUBLE))
-    ret = "ldi %A0,%A1\n\tldi %B0,%B1\n\tldi %C0,%C1\n\tldi %D0,%D1";
-
-  else if (mem0_p
-	   && ((GET_CODE (op1) == CONST_INT && INTVAL (op1) == 0)
-	       || (GET_CODE (op1) == CONST_DOUBLE
-		   && CONST_DOUBLE_LOW (op1) == 0
-		   && CONST_DOUBLE_HIGH (op1) == 0)))
-    ret = "st %.,%A0\n\tst %.,%B0\n\tst %.,%C0\n\tst %.,%D0";
-
-  else if (mem0_p && const1_p && GET_CODE (tmp_si) == REG && GET_MODE (tmp_si) == SImode)
-    {
-      int part0, part1, part2, part3;
-
-      if (GET_CODE (op1) == CONST_INT && INTVAL (op1) < 0)
-	{
-	  HOST_WIDE_INT value = INTVAL (op1);
-	  part0 = 0xffff;
-	  part1 = 0xffff;
-	  part2 = (value >> 16) & 0xffff;
-	  part3 = value & 0xffff;
-	}
-
-      else if (GET_CODE (op1) == CONST_INT)
-	{
-	  HOST_WIDE_INT value = INTVAL (op1);
-	  part0 = 0;
-	  part1 = 0;
-	  part2 = (value >> 16) & 0xffff;
-	  part3 = value & 0xffff;
-	}
-
-      else
-	{
-	  part0 = (CONST_DOUBLE_HIGH (op1) >> 16) & 0xffff;
-	  part1 = CONST_DOUBLE_HIGH (op1) & 0xffff;
-	  part2 = (CONST_DOUBLE_LOW (op1) >> 16) & 0xffff;
-	  part3 = CONST_DOUBLE_LOW (op1) & 0xffff;
-	}
-
-      if (part0 == part2 && part1 == part3)
-	ret = "ldi %U2,%A1\n\tldi %L2,%B1\n\tst2w %2,%A0\n\tst2w %2,%C0";
-
-      else if (part0 == part2)
-	ret = "ldi %U2,%A1\n\tldi %L2,%B1\n\tst2w %2,%A0\n\tldi %L2,%D1\n\tst2w %2,%C0";
-
-      else if (part1 == part3)
-	ret = "ldi %U2,%A1\n\tldi %L2,%B1\n\tst2w %2,%A0\n\tldi %U2,%C1\n\tst2w %2,%C0";
-
-      else
-	ret = "ldi %U2,%A1\n\tldi %L2,%B1\n\tst2w %2,%A0\n\tldi %U2,%C1\n\tldi %L2,%D1\n\tst2w %2,%C0";
-    }
-
-  else
-    fatal_insn ("emit_move_4words:", insn);
-
-  return ret;
-}
-
-
-
-/* Emit code to do add of multiword values */
-
-char *
-emit_add (operands, insn)
-     rtx operands[], insn;
-{
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-  rtx op2 = operands[2];
-  enum machine_mode mode = GET_MODE (op0);
-  int regno0 = (GET_CODE (op0) == REG) ? REGNO (op0) : -1;
-  int regno1 = (GET_CODE (op1) == REG) ? REGNO (op1) : -1;
-  int regno2 = (GET_CODE (op2) == REG) ? REGNO (op2) : -1;
-  HOST_WIDE_INT value;
-
-  if (mode == SImode)
-    {
-      if (GET_CODE (op2) != CONST_INT)
-	{
-	  if (GPR_P (regno0) && regno0 == regno1 && GPR_P (regno2))
-	    return "add2w %0,%2";
-
-	  else if (ACCUM_P (regno0) && regno0 == regno1 && (GPR_P (regno2) || ACCUM_P (regno2)))
-	    return "add %0,%2";
-
-	  else if (GPR_P (regno0) && (GPR_P (regno1) || ACCUM_P (regno1)) && ACCUM_P (regno2) && TARGET_ADDAC3)
-	    return "addac3 %0,%1,%2";
-	}
-
-      else if (regno0 != regno1)
-	return "ldi %U0,%U2\n\tldi %L0,%L2\n\tadd2w %0,%1";
-
-      else if (INTVAL (op2) < 0)
-	fatal_insn ("emit_add, negative constant", insn);
-
-      else if (GPR_P (regno0) && GPR_P (regno1))
-	{
-	  value = INTVAL (op2);
-	  if (IN_RANGE_P (value, 1, 16) && regno0 == regno1)
-	    return "addi %L0,%2\n\tcpfg f0,c\n\texef0t || addi %U0,1";
-
-	  else if (regno0 == regno1)
-	    return "add3 %L0,%L0,%2\n\tcpfg f0,c\n\texef0t || addi %U0,1";
-
-	  else
-	    return "add3 %L0,%L1,%2\n\tcpfg f0,c || mv %U0,%U1\n\texef0t || addi %U0,1";
-	}
-    }
-
-  else if (mode == DImode && regno0 == regno1 && GPR_P (regno0))
-    {
-      int num_carries = 0;
-      if (GPR_P (regno2))
-	{
-	  output_asm_insn ("add2w %A0,%A2", operands);
-	  output_asm_insn ("add2w %C0,%C2", operands);
-	  num_carries = 2;
-	}
-
-      else if (GET_CODE (op2) == CONST_INT && INTVAL (op2) >= 0)
-	{
-	  num_carries = 3;
-	  value = INTVAL (op2);
-	  if (IN_RANGE_P (value, 1, 16) && regno0 == regno1)
-	    output_asm_insn ("addi %D0,%2", operands);
-
-	  else if (IN_RANGE_P (value, 1, 16) && TARGET_SMALL_INSNS && optimize)
-	    output_asm_insn ("mv %D0,%D1\n\taddi %D0,%2", operands);
-
-	  else
-	    output_asm_insn ("add3 %D0,%D1,%2", operands);
-	}
-
-      else if (GET_CODE (op2) == CONST_DOUBLE
-	       && CONST_DOUBLE_HIGH (op2) == 0
-	       && CONST_DOUBLE_LOW (op2) >= 0)
-	{
-	  num_carries = 3;
-	  value = CONST_DOUBLE_LOW (op2);
-	  if (IN_RANGE_P (value, 1, 16) && regno0 == regno1)
-	    output_asm_insn ("addi %D0,%2", operands);
-
-	  else if (IN_RANGE_P (value, 1, 16) && TARGET_SMALL_INSNS && optimize)
-	    output_asm_insn ("mv %D0,%D1\n\taddi %D0,%2", operands);
-
-	  else
-	    output_asm_insn ("add3 %D0,%D1,%2", operands);
-	}
-
-      if (num_carries)
-	{
-	  output_asm_insn ("cpfg f0,c", operands);
-
-	  if (num_carries == 3)
-	    {
-	      output_asm_insn ("exef0t || addi %C0,1", operands);
-	      output_asm_insn ("cpfg f0,c || exef0t", operands);
-	    }
-
-	  output_asm_insn ("exef0t || addi %B0,1", operands);
-	  output_asm_insn ("cpfg f0,c || exef0t", operands);
-	  output_asm_insn ("exef0t || addi %A0,1", operands);
-	  return "";
-	}
-    }
-
-  fatal_insn ("emit_add:", insn);
-}
-
-
-/* Emit code to do subtract of multiword values */
-
-char *
-emit_subtract (operands, insn)
-     rtx operands[], insn;
-{
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-  rtx op2 = operands[2];
-  enum machine_mode mode = GET_MODE (op0);
-  int regno0 = (GET_CODE (op0) == REG) ? REGNO (op0) : -1;
-  int regno1 = (GET_CODE (op1) == REG) ? REGNO (op1) : -1;
-  int regno2 = (GET_CODE (op2) == REG) ? REGNO (op2) : -1;
-  HOST_WIDE_INT value;
-
-  if (mode == SImode)
-    {
-      if (GPR_P (regno0) && regno0 == regno1 && GPR_P (regno2))
-	return "sub2w %0,%2";
-
-      else if (ACCUM_P (regno0) && regno0 == regno1 && (GPR_P (regno2) || ACCUM_P (regno2)))
-	return "sub %0,%2";
-
-      else if (GPR_P (regno0) && (GPR_P (regno1) || ACCUM_P (regno1)) && ACCUM_P (regno2) && TARGET_ADDAC3)
-	return "subac3 %0,%1,%2";
-    }
-
-  else if (mode == DImode && GPR_P (regno0) && regno0 == regno1 && GPR_P (regno2))
-    return "sub2w %A0,%A2\n\tsub2w %C0,%C2\n\tcpfg f0,c\n\texef0f || subi %B0,1\n\tcpfg f0,c || exef0f\n\texef0f || subi %A0,1";
-
-  fatal_insn ("emit_subtract:", insn);
-}
-
-
-/* Output a conditional move instruction
-   operands[0] is the destination
-   operands[1] is the NE test
-   operands[2] is f0
-   operands[3] is the value to move if the test was true
-   operands[4] is the value to move if the test was false  */
-
-char *
-emit_cond_move (operands, insn)
-     rtx operands[];
-     rtx insn;
-{
-  char *load = (char *)0;
-  char *store = (char *)0;
-  char *move_false = (char *)0;
-  char *move_true = (char *)0;
-  rtx dest = operands[0];
-  rtx xop[10];
-  rtx op_true;
-  rtx op_false;
-  enum machine_mode mode = GET_MODE (dest);
-  char buffer[80];
-
-  if (GET_MODE (operands[1]) == CC_REVmode)
-    {
-      op_true = operands[4];
-      op_false = operands[3];
-    }
-  else
-    {
-      op_true = operands[3];
-      op_false = operands[4];
-    }
-
-  switch (mode)
-    {
-    case QImode:
-      load = "ldub";
-      store = "stb";
-      move_false = "mvf0f %0,%1";
-      move_true = "mvf0t %0,%1";
-      break;
-
-    case HImode:
-      load = "ld";
-      store = "st";
-      move_false = "mvf0f %0,%1";
-      move_true = "mvf0t %0,%1";
-      break;
-
-    case SImode:
-    case SFmode:
-      load = "ld2w";
-      store = "st2w";
-      move_false = "exef0f || mv2w %0,%1";
-      move_true = "exef0t || mv2w %0,%1";
-      break;
-
-    default:
-      fatal_insn ("emit_cond_move", insn);
-    }
-
-  xop[0] = dest;
-  if (GET_CODE (dest) == REG
-      && GET_CODE (op_false) == CONST_INT
-      && !refers_to_regno_p (REGNO (dest), REGNO (dest)+1, op_true, (rtx *)0))
-    {
-      xop[1] = op_false;
-      output_asm_insn ("ldi %0,%1", xop);
-
-      xop[1] = op_true;
-      switch (GET_CODE (op_true))
-	{
-	case REG:
-	  output_asm_insn (move_true, xop);
-	  break;
-
-	case MEM:
-	  sprintf (buffer, "%s %%0,%%M1 || exef0t", load);
-	  output_asm_insn (buffer, xop);
-	  break;
-
-	case CONST_INT:
-	  output_asm_insn ("exef0t || ldi %0,%1", xop);
-	  break;
-
-	default:
-	  fatal_insn ("emit_cond_move", insn);
-	}
-    }
-
-  else if (GET_CODE (dest) == REG
-	   && GET_CODE (op_true) == CONST_INT
-	   && !refers_to_regno_p (REGNO (dest), REGNO (dest)+1, op_false, (rtx *)0))
-    {
-      xop[1] = op_true;
-      output_asm_insn ("ldi %0,%1", xop);
-
-      xop[1] = op_false;
-      switch (GET_CODE (op_false))
-	{
-	case REG:
-	  output_asm_insn (move_false, xop);
-	  break;
-
-	case MEM:
-	  sprintf (buffer, "%s %%0,%%M1 || exef0f", load);
-	  output_asm_insn (buffer, xop);
-	  break;
-
-	default:
-	  fatal_insn ("emit_cond_move", insn);
-	}
-    }
-
-  else if (GET_CODE (dest) == REG)
-    {
-      int dest_reg = REGNO (dest);
-
-      /* Move value into register for false condition */
-      xop[1] = op_false;
-      switch (GET_CODE (op_false))
-	{
-	case REG:
-	  if (REGNO (op_false) != dest_reg)
-	    output_asm_insn (move_false, xop);
-	  break;
-
-	case MEM:
-	  sprintf (buffer, "%s %%0,%%M1 || exef0f", load);
-	  output_asm_insn (buffer, xop);
-	  break;
-
-	case CONST_INT:
-	  output_asm_insn ("exef0f || ldi %0,%1", xop);
-	  break;
-
-	default:
-	  fatal_insn ("emit_cond_move", insn);
-	}
-
-      /* Move value into register for true condition */
-      xop[1] = op_true;
-      switch (GET_CODE (op_true))
-	{
-	case REG:
-	  if (REGNO (op_true) != dest_reg)
-	    output_asm_insn (move_true, xop);
-	  break;
-
-	case MEM:
-	  sprintf (buffer, "%s %%0,%%M1 || exef0t", load);
-	  output_asm_insn (buffer, xop);
-	  break;
-
-	case CONST_INT:
-	  output_asm_insn ("exef0t || ldi %0,%1", xop);
-	  break;
-
-	default:
-	  fatal_insn ("emit_cond_move", insn);
-	}
-    }
-
-  else if (GET_CODE (dest) == MEM
-	   && (GET_CODE (op_false) == REG
-	       || (GET_CODE (op_false) == CONST_INT
-		   && INTVAL (op_false) == 0
-		   && GET_MODE_SIZE (mode) <= 2))
-	   && (GET_CODE (op_true) == REG
-	       || (GET_CODE (op_true) == CONST_INT
-		   && INTVAL (op_true) == 0
-		   && GET_MODE_SIZE (mode) <= 2)))
-    {
-      xop[1] = op_false;
-      sprintf (buffer, "%s %s,%%M0 || exef0f", store, (GET_CODE (op_false) == CONST_INT ? "%." : "%1"));
-      output_asm_insn (buffer, xop);
-
-      xop[1] = op_true;
-      sprintf (buffer, "%s %s,%%M0 || exef0t", store, (GET_CODE (op_true) == CONST_INT ? "%." : "%1"));
-      output_asm_insn (buffer, xop);
-    }
-
-  else
-    fatal_insn ("emit_cond_move", insn);
-
-  return "";
-}
-
-
-/* Split a multiword logical operation into its component parts */
-
-Rtx
-d10v_split_logical_op (operands, code)
-     rtx operands[];
-     enum rtx_code code;
-{
-  rtx ret;
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-  rtx op2 = operands[2];
-  rtx split_op0;
-  rtx split_op1;
-  rtx split_op2;
-  int split_values[4];
-  int i, max_words;
-  int off0 = 0, off1 = 0, off2 = 0;
-  enum machine_mode mode = GET_MODE (op0);
-  rtx insn;
-
-  if (GET_CODE (op0) == SUBREG)
-    {
-      off0 = SUBREG_WORD (op0);
-      op0 = SUBREG_REG (op0);
-    }
-
-  if (GET_CODE (op0) != REG)
-    goto fail;
-
-  if (GET_CODE (op1) == SUBREG)
-    {
-      off1 = SUBREG_WORD (op1);
-      op1 = SUBREG_REG (op1);
-    }
-
-  if (GET_CODE (op1) != REG)
-    goto fail;
-
-  if (code != NOT)
-    {
-      if (GET_CODE (op2) == SUBREG)
-	{
-	  off2 = SUBREG_WORD (op2);
-	  op2 = SUBREG_REG (op2);
-	}
-
-      if (GET_CODE (op2) == CONST_INT || GET_CODE (op2) == CONST_DOUBLE)
-	{
-	  if (mode == DImode)
-	    d10v_split_constant64 (op2, split_values);
-
-	  else if (mode == SImode)
-	    d10v_split_constant32 (op2, split_values);
-
-	  else
-	    goto fail;
-	}
-      else if (GET_CODE (op2) != REG)
-	goto fail;
-    }
-  else
-    op2 = NULL_RTX;
-
-  max_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
-  start_sequence ();
-
-  for (i = 0; i < max_words; i++)
-    {
-      if (!reload_completed)
-	{
-	  split_op0 = gen_rtx (SUBREG, HImode, op0, i+off0);
-	  split_op1 = gen_rtx (SUBREG, HImode, op1, i+off1);
-	}
-      else
-	{
-	  split_op0 = gen_rtx (REG, HImode, REGNO (op0) + i+off0);
-	  split_op1 = gen_rtx (REG, HImode, REGNO (op1) + i+off1);
-	}
-
-      if (code == NOT)
-	{
-	  emit_insn (gen_rtx (SET, VOIDmode,
-			      split_op0,
-			      gen_rtx (NOT, HImode, split_op1)));
-	  continue;
-	}
-
-      if (GET_CODE (op2) != REG)
-	{
-	  /* Optimize <reg> <op>= <value> operations to skip NOPs */
-	  if ((REGNO (op0) + i + off0) == (REGNO (op1) + i + off1))
-	    {
-	      if (split_values[i] == 0 && code == IOR)
-		continue;
-
-	      if ((split_values[i] & 0xffff) == 0xffff && code == AND)
-		continue;
-	    }
-	  
-	  /* Optimize <reg1> = <reg2> <op> <value> that turn into moves */
-	  else if ((split_values[i] == 0 && code == IOR)
-		   || ((split_values[i] & 0xffff) == 0xffff && code == AND))
-	    {
-	      emit_insn (gen_rtx (SET, VOIDmode, split_op0, split_op1));
-	      continue;
-	    }
-
-	  split_op2 = GEN_INT (split_values[i]);
-	}
-      else
-	split_op2 = gen_rtx (SUBREG, HImode, op2, i+off2);
-
-      emit_insn (gen_rtx (SET, VOIDmode,
-			  split_op0,
-			  gen_rtx (code, HImode, split_op1, split_op2)));
-    }
-
-  ret = gen_sequence ();
-  end_sequence ();
-  return ret;
-
-fail:
-  if (code != NOT)
-    insn = gen_rtx (SET, VOIDmode,
-		    operands[0],
-		    gen_rtx (code, mode, operands[1], operands[2]));
-  else
-    insn = gen_rtx (SET, VOIDmode,
-		    operands[0],
-		    gen_rtx (NOT, mode, operands[1]));
-
-  fatal_insn ("bad insn to d10v_split_logical_op", insn);
-  return NULL_RTX;
-}
-
-
-/* Split a 32-bit constant into 2 16-bit values.  */
-
-static void
-d10v_split_constant32 (x, values)
-     rtx x;
-     int values[];
-{
-  enum rtx_code code = GET_CODE (x);
-  HOST_WIDE_INT v;
-
-  if (code == CONST_INT)
-    {
-      v = INTVAL (x);
-      values[0] = SIGN_EXTEND_SHORT (v >> 16);
-      values[1] = SIGN_EXTEND_SHORT (v);
-    }
-
-  else if (code == CONST_DOUBLE && GET_MODE (x) == SFmode)
-    {
-      REAL_VALUE_TYPE rv;
-
-      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-      REAL_VALUE_TO_TARGET_SINGLE (rv, v);
-      values[0] = SIGN_EXTEND_SHORT (v >> 16);
-      values[1] = SIGN_EXTEND_SHORT (v);
-    }
-
-  else
-    fatal_insn ("Bad rtx passed to d10v_split_constant32:", x);
-}
-
-
-/* Split a 64-bit constant into 4 16-bit values.  */
-
-static void
-d10v_split_constant64 (x, values)
-     rtx x;
-     int values[];
-{
-  enum rtx_code code = GET_CODE (x);
-  HOST_WIDE_INT v;
-
-  if (code == CONST_INT)
-    {
-      v = INTVAL (x);
-      if (v < 0)
-	values[0] = values[1] = -1;
-      else
-	values[0] = values[1] = 0;
-
-      values[2] = SIGN_EXTEND_SHORT (v >> 16);
-      values[3] = SIGN_EXTEND_SHORT (v);
-    }
-
-  else if (code == CONST_DOUBLE && GET_MODE (x) == DFmode)
-    {
-      long t[2];
-      REAL_VALUE_TYPE rv;
-
-      /* d10v is big endian, so the high word is first */
-      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-      REAL_VALUE_TO_TARGET_DOUBLE (rv, t);
-      values[0] = SIGN_EXTEND_SHORT (t[0] >> 16);
-      values[1] = SIGN_EXTEND_SHORT (t[0]);
-      values[2] = SIGN_EXTEND_SHORT (t[1] >> 16);
-      values[3] = SIGN_EXTEND_SHORT (t[1]);
-    }
-
-  else if (code == CONST_DOUBLE
-	   && (GET_MODE (x) == DImode || GET_MODE (x) == VOIDmode))
-    {
-      v = CONST_DOUBLE_HIGH (x);
-      values[0] = SIGN_EXTEND_SHORT (v >> 16);
-      values[1] = SIGN_EXTEND_SHORT (v);
-
-      v = CONST_DOUBLE_LOW (x);
-      values[2] = SIGN_EXTEND_SHORT (v >> 16);
-      values[3] = SIGN_EXTEND_SHORT (v);
-    }
-
-  else
-    fatal_insn ("Bad rtx passed to d10v_split_constant64:", x);
-}
-
-
-/* Print an integer constant expression in assembler syntax.
-   Note, for the d10v, we need to explicitly truncate integer
-   constants to 16 bits.  */
-
-void
-d10v_output_addr_const (file, x)
-     FILE *file;
-     rtx x;
-{
-  char buf[256];
-
- restart:
-  switch (GET_CODE (x))
-    {
-    default:
-      output_addr_const (file, x);
-      break;
-
-    case SYMBOL_REF:
-      /* We could use parentheses only for symbols whose names conflict
-         with the register names.  But it would make the compiler
-         slower. */
-      fputc ('(', file);
-      assemble_name (file, XSTR (x, 0));
-      fputc (')', file);
-      break;
-
-    case LABEL_REF:
-      ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (x, 0)));
-      assemble_name (file, buf);
-      break;
-
-    case CODE_LABEL:
-      ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
-      assemble_name (file, buf);
-      break;
-
-    case CONST_INT:
-      fprintf (file, "%d", SIGN_EXTEND_SHORT (INTVAL (x)));
-      break;
-
-    case CONST:
-      d10v_output_addr_const (file, XEXP (x, 0));
-      break;
-
-    case PLUS:
-      /* Some assemblers need integer constants to appear last (eg masm).  */
-      if (GET_CODE (XEXP (x, 0)) == CONST_INT)
-	{
-	  d10v_output_addr_const (file, XEXP (x, 1));
-	  if (INTVAL (XEXP (x, 0)) >= 0)
-	    fprintf (file, "+");
-	  d10v_output_addr_const (file, XEXP (x, 0));
-	}
-      else
-	{
-	  d10v_output_addr_const (file, XEXP (x, 0));
-	  if (INTVAL (XEXP (x, 1)) >= 0)
-	    fprintf (file, "+");
-	  d10v_output_addr_const (file, XEXP (x, 1));
-	}
-      break;
-
-    case MINUS:
-      /* Avoid outputting things like x-x or x+5-x,
-	 since some assemblers can't handle that.  */
-      x = simplify_subtraction (x);
-      if (GET_CODE (x) != MINUS)
-	goto restart;
-
-      d10v_output_addr_const (file, XEXP (x, 0));
-      fprintf (file, "-");
-      if (GET_CODE (XEXP (x, 1)) == CONST_INT
-	  && INTVAL (XEXP (x, 1)) < 0)
-	{
-	  fprintf (file, ASM_OPEN_PAREN);
-	  d10v_output_addr_const (file, XEXP (x, 1));
-	  fprintf (file, ASM_CLOSE_PAREN);
-	}
-      else
-	d10v_output_addr_const (file, XEXP (x, 1));
-      break;
-
-    case ZERO_EXTEND:
-    case SIGN_EXTEND:
-      d10v_output_addr_const (file, XEXP (x, 0));
-      break;
-    }
-}
-
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand that is a memory
-   reference whose address is X.  X is an RTL expression.
-
-   On some machines, the syntax for a symbolic address depends on the
-   section that the address refers to.  On these machines, define the
-   macro `ENCODE_SECTION_INFO' to store the information into the
-   `symbol_ref', and then check for it here.  *Note Assembler
-   Format::.  */
-
-void
-print_operand_address (stream, x)
-     FILE *stream;
-     rtx x;
-{
-  rtx x0, x1;
-
-  if (GET_CODE (x) == MEM)
-    x = XEXP (x, 0);
-
-  switch (GET_CODE (x))
-    {
-    default:
-      break;
-
-    case REG:
-      fputs (reg_names[ REGNO (x) ], stream);
-      return;
-
-    case CONST_INT:
-      fprintf (stream, "%d", SIGN_EXTEND_SHORT (INTVAL (x)));
-      return;
-
-    case SYMBOL_REF:
-    case CONST:
-    case LABEL_REF:
-      d10v_output_addr_const (stream, x);
-      return;
-    }
-
-  fatal_insn ("Bad insn to print_operand_address:", x);
-}
-
-
-/* Print a memory reference suitable for the ld/st instructions.  */
-
-static void
-print_operand_memory_reference (stream, x)
-     FILE *stream;
-     rtx x;
-{
-  rtx x0, x1;
-  int offset;
-
-  switch (GET_CODE (x))
-    {
-    default:
-      fatal_insn ("Bad insn to print_operand_memory_reference:", x);
-      break;
-
-    case SUBREG:
-      offset = 0;
-      do {
-	offset += SUBREG_WORD (x);
-	x = SUBREG_REG (x);
-      } while (GET_CODE (x) == SUBREG);
-      fprintf (stream, "@%s", reg_names[ REGNO (x)+offset ]);
-      break;
-
-    case REG:
-      fprintf (stream, "@%s", reg_names[ REGNO (x) ]);
-      break;
-
-    case CONST_INT:
-      fprintf (stream, "@(%d,%s)", SIGN_EXTEND_SHORT (INTVAL (x)), reg_names[ GPR_ZERO_REGNUM ]);
-      break;
-
-    case SYMBOL_REF:
-    case CONST:
-    case LABEL_REF:
-      fputs ("@(", stream);
-      d10v_output_addr_const (stream, x);
-      fprintf (stream, ",%s)", reg_names[ GPR_ZERO_REGNUM ]);
-      break;
-
-    case PLUS:
-      x0 = XEXP (x, 0);
-      x1 = XEXP (x, 1);
-      offset = 0;
-      while (GET_CODE (x0) == SUBREG)
-	{
-	  offset += SUBREG_WORD (x0);
-	  x0 = SUBREG_REG (x0);
-	}
-
-      if (CONSTANT_ADDRESS_P (x1) && GET_CODE (x0) == REG && GPR_P (REGNO (x0)))
-	{
-	  if (GET_CODE (x1) == CONST_INT && INTVAL (x1) == 0)
-	    fprintf (stream, "@%s", reg_names[ REGNO (x0)+offset ]);
-	  else if (GET_CODE (x1) == CONST_INT)
-	    fprintf (stream, "@(%d,%s)", SIGN_EXTEND_SHORT (INTVAL (x1)),
-		     reg_names[ REGNO (x0)+offset ]);
-	  else
-	    {
-	      fputs ("@(", stream);
-	      d10v_output_addr_const (stream, x1);
-	      fprintf (stream, ",%s)", reg_names[ REGNO (x0)+offset ]);
-	      return;
-	    }
-	}
-      else
-	fatal_insn ("Bad insn to print_operand_memory_reference:", x);
-
-      break;
-
-    case POST_INC:
-      x0 = XEXP (x, 0);
-      if (GET_CODE (x0) == REG && GPR_P (REGNO (x0)))
-	fprintf (stream, "@%s+", reg_names[ REGNO (x0) ]);
-      else
-	fatal_insn ("Bad insn to print_operand_memory_reference:", x);
-
-      break;
-
-    case POST_DEC:
-      x0 = XEXP (x, 0);
-      if (GET_CODE (x0) == REG && GPR_P (REGNO (x0))
-	  && REGNO (x0) != STACK_POINTER_REGNUM)
-	fprintf (stream, "@%s-", reg_names[ REGNO (x0) ]);
-      else
-	fatal_insn ("Bad insn to print_operand_memory_reference:", x);
-
-      break;
-
-    case PRE_DEC:
-      x0 = XEXP (x, 0);
-      if (GET_CODE (x0) == REG && REGNO (x0) == STACK_POINTER_REGNUM)
-	fprintf (stream, "@-%s", reg_names[ REGNO (x0) ]);
-      else
-	fatal_insn ("Bad insn to print_operand_memory_reference:", x);
-
-      break;
-
-    }
-}
-
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand X.  X is an RTL
-   expression.
-
-   LETTER is a value that can be used to specify one of several ways of
-   printing the operand.  It is used when identical operands must be
-   printed differently depending on the context.  LETTER comes from the
-   `%' specification that was used to request printing of the
-   operand.  If the specification was just `%DIGIT' then LETTER is 0;
-   if the specification was `%LTR DIGIT' then LETTER is the ASCII code
-   for LTR.
-
-   If X is a register, this macro should print the register's name.
-   The names can be found in an array `reg_names' whose type is `char
-   *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
-
-   When the machine description has a specification `%PUNCT' (a `%'
-   followed by a punctuation character), this macro is called with a
-   null pointer for X and the punctuation character for LETTER.  */
-
-void
-print_operand (stream, x, letter)
-    FILE *stream;
-    rtx x;
-    int letter;
-{
-  enum rtx_code code = (x) ? GET_CODE (x) : NIL;
-  int regadd;
-  int split_values[4];
-  int shift, log;
-  rtx x0;
-
-  switch (letter)
-    {
-    case '|':	/* Issue parallel instructions */
-      fputs (" || ", stream);
-      break;
-
-    case '.':	/* Output r14 */
-      fputs (reg_names[GPR_ZERO_REGNUM], stream);
-      break;
-
-    case 'U':	/* Extract the upper part (word 0) of a 32-bit value */
-      regadd = 0;
-      goto common_32bit;
-
-    case 'L':	/* Extract the lower part (word 1) of a 32-bit value */
-      regadd = 1;
-      /* fall through */
-
-    common_32bit:
-      if (code == CONST_INT || code == CONST_DOUBLE)
-	{
-	  d10v_split_constant32 (x, split_values);
-	  fprintf (stream, "%d", SIGN_EXTEND_SHORT (split_values[regadd]));
-	}
-
-      else if (code == REG)
-	fprintf (stream, "%s", reg_names[ REGNO (x)+regadd ]);
-
-      else if (code == MEM && offsettable_memref_p (x))
-	print_operand_address (stream, plus_constant (XEXP (x, 0), regadd * UNITS_PER_WORD));
-
-      else
-	fatal_insn ("Bad insn for %U/%L:", x);
-
-      break;
-
-    case 'A':	/* Extract word 0 of a 64-bit value */
-    case 'B':	/* Extract word 1 of a 64-bit value */
-    case 'C':	/* Extract word 2 of a 64-bit value */
-    case 'D':	/* Extract word 3 of a 64-bit value */
-      regadd = letter - 'A';
-      if (code == CONST_INT || code == CONST_DOUBLE)
-	{
-	  d10v_split_constant64 (x, split_values);
-	  fprintf (stream, "%d", split_values[regadd]);
-	}
-
-      else if (code == REG)
-	fprintf (stream, "%s", reg_names[ REGNO (x)+regadd ]);
-
-      else if (code == MEM && offsettable_memref_p (x))
-	print_operand_memory_reference (stream, plus_constant (XEXP (x, 0), regadd * UNITS_PER_WORD));
-
-      else
-	fatal_insn ("Bad insn for %A/%B/%C/%D:", x);
-
-      break;
-
-    case 'M':	/* Print a memory reference for ld/st instructions */
-      if (GET_CODE (x) != MEM)
-	fatal_insn ("Bad insn to print_operand 'M' modifier:", x);
-
-      print_operand_memory_reference (stream, XEXP (x, 0));
-      break;
-
-    case 'F':	/* Print an appropriate 'f' or 't' for a false comparision instruction.  */
-    case 'T':	/* Print an appropriate 'f' or 't' for a true  comparision instruction.  */
-      if ((GET_CODE (x) == NE || GET_CODE (x) == EQ)
-	  && (GET_MODE (x) == CCmode || GET_MODE (x) == CC_REVmode)
-	  && GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == F0_REGNUM
-	  && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
-	{
-	  int true_false = (GET_MODE (x) == CC_REVmode);
-
-	  if (letter == 'F')
-	    true_false = !true_false;
-
-	  if (GET_CODE (x) == EQ)
-	    true_false = !true_false;
-
-	  putc ((true_false) ? 't' : 'f', stream);
-	}
-
-      else
-	fatal_insn ("Bad insn to print_operand 'F' or 'T' modifier:", x);
-      break;
-
-    case 'b':	/* emit offset single bit to change */
-      if (GET_CODE (x) == CONST_INT && (log = exact_log2 (INTVAL (x))) >= 0)
-	fprintf (stream, "%d", 15 - log);
-
-      else if (GET_CODE (x) == CONST_INT && (log = exact_log2 (~ INTVAL (x))) >= 0)
-	fprintf (stream, "%d", 15 - log);
-
-      else
-	fatal_insn ("Bad insn to print_operand 'b' modifier:", x);
-      break;
-
-    case 's':	/* print ldi.s value for composing ldi.l out of ldi.s and slli */
-      if (GET_CODE (x) == CONST_INT
-	  && (shift = ldi_shift_operand (x, HImode)) > 0)
-	{
-	  fprintf (stream, "%d", ((int) INTVAL (x)) >> shift);
-	}
-
-      else
-	fatal_insn ("Bad insn to print_operand 'S' modifier:", x);
-      break;
-
-    case 'S':	/* print shift value for composing ldi.l out of ldi.s and slli */
-      if (GET_CODE (x) == CONST_INT
-	  && (shift = ldi_shift_operand (x, HImode)) > 0)
-	{
-	  fprintf (stream, "%d", shift);
-	}
-
-      else
-	fatal_insn ("Bad insn to print_operand 'S' modifier:", x);
-      break;
-
-    case 'u':	/* print a 'u' if the operator is ZERO_EXTEND */
-      if (GET_CODE (x) == ZERO_EXTEND)
-	putc ('u', stream);
-      break;
-
-    case 0:
-      if (code == REG)
-	fputs (reg_names[ REGNO (x) ], stream);
-
-      else if (code == CONST_INT)
-	fprintf (stream, "%d", (int)INTVAL (x));
-
-      else if (code == MEM)
-	print_operand_address (stream, XEXP (x, 0));
-
-      else if (CONSTANT_ADDRESS_P (x))
-	print_operand_address (stream, x);
-
-      else
-	fatal_insn ("Bad insn in print_operand, 0 case", x);
-
-      return;
-
-    default:
-      {
-	char buf[80];
-
-	sprintf (buf, "Invalid asm template character '%%%c'", letter);
-	fatal_insn (buf, x);
-      }
-    }
-}
-
-
-/* A C statement (sans semicolon) for initializing the variable CUM
-   for the state at the beginning of the argument list.  The variable
-   has type `CUMULATIVE_ARGS'.  The value of FNTYPE is the tree node
-   for the data type of the function which will receive the args, or 0
-   if the args are to a compiler support library function.  The value
-   of INDIRECT is nonzero when processing an indirect call, for
-   example a call through a function pointer.  The value of INDIRECT
-   is zero for a call to an explicitly named function, a library
-   function call, or when `INIT_CUMULATIVE_ARGS' is used to find
-   arguments for the function being compiled.
-
-   When processing a call to a compiler support library function,
-   LIBNAME identifies which one.  It is a `symbol_ref' rtx which
-   contains the name of the function, as a string.  LIBNAME is 0 when
-   an ordinary C function call is being processed.  Thus, each time
-   this macro is called, either LIBNAME or FNTYPE is nonzero, but
-   never both of them at once. */
-
-void
-init_cumulative_args (cum, fntype, libname, indirect, incoming)
-     CUMULATIVE_ARGS *cum;
-     tree fntype;
-     rtx libname;
-     int indirect;
-     int incoming;
-{
-  cum->reg = 0;
-  cum->stack = 4;
-
-  if (TARGET_DEBUG_ARG)
-    {
-      fprintf (stderr, "\ninit_cumulative_args:");
-      if (indirect)
-	fputs (" indirect", stderr);
-
-      if (incoming)
-	fputs (" incoming", stderr);
-
-      if (fntype)
-	{
-	  tree ret_type = TREE_TYPE (fntype);
-	  fprintf (stderr, " return=%s,",
-		   tree_code_name[ (int)TREE_CODE (ret_type) ]);
-	}
-
-      if (libname && GET_CODE (libname) == SYMBOL_REF)
-	fprintf (stderr, " libname=%s", XSTR (libname, 0));
-
-      putc ('\n', stderr);
-    }
-}
-
-
-/* If defined, a C expression that gives the alignment boundary, in
-   bits, of an argument with the specified mode and type.  If it is
-   not defined, `PARM_BOUNDARY' is used for all arguments. */
-
-int
-function_arg_boundary (mode, type)
-     enum machine_mode mode;
-     tree type;
-{
-  int size = ((mode == BLKmode && type)
-	      ? int_size_in_bytes (type)
-	      : GET_MODE_SIZE (mode));
-
-  return ((size >= 2 * UNITS_PER_WORD) ? 2*BITS_PER_WORD : BITS_PER_WORD);
-}
-
-
-/* A C expression that controls whether a function argument is passed
-   in a register, and which register.
-
-   The arguments are CUM, which summarizes all the previous
-   arguments; MODE, the machine mode of the argument; TYPE, the data
-   type of the argument as a tree node or 0 if that is not known
-   (which happens for C support library functions); and NAMED, which
-   is 1 for an ordinary argument and 0 for nameless arguments that
-   correspond to `...' in the called function's prototype.
-
-   The value of the expression should either be a `reg' RTX for the
-   hard register in which to pass the argument, or zero to pass the
-   argument on the stack.
-
-   For machines like the Vax and 68000, where normally all arguments
-   are pushed, zero suffices as a definition.
-
-   The usual way to make the ANSI library `stdarg.h' work on a machine
-   where some arguments are usually passed in registers, is to cause
-   nameless arguments to be passed on the stack instead.  This is done
-   by making `FUNCTION_ARG' return 0 whenever NAMED is 0.
-
-   You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the
-   definition of this macro to determine if this argument is of a
-   type that must be passed in the stack.  If `REG_PARM_STACK_SPACE'
-   is not defined and `FUNCTION_ARG' returns non-zero for such an
-   argument, the compiler will abort.  If `REG_PARM_STACK_SPACE' is
-   defined, the argument will be computed in the stack and then
-   loaded into a register. */
-
-struct rtx_def *
-function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int align = ((cum->reg & 1) != 0
-	       && function_arg_boundary (mode, type) >= (2*BITS_PER_WORD));
-  int size = ((mode == BLKmode && type)
-	      ? int_size_in_bytes (type)
-	      : GET_MODE_SIZE (mode));
-
-  rtx ret;
-
-  if ((cum->reg + align) * 2 + size > (ARG_LAST - ARG_FIRST + 1) * 2)
-    ret = NULL_RTX;
-
-  else
-    ret = gen_rtx (REG, mode, ARG_FIRST + cum->reg + align);
-
-  if (TARGET_DEBUG_ARG)
-    fprintf (stderr,
-	     "function_arg: words = %2d %2d, mode = %4s, named = %d, align = %d, size = %3d, arg = %s\n",
-	     cum->reg, cum->stack, GET_MODE_NAME (mode), named, align, size,
-	     (ret) ? reg_names[ REGNO (ret) ] : "memory");
-
-  return ret;
-}
-
-
-
-/* If defined, a C expression that indicates when it is the called
-   function's responsibility to make a copy of arguments passed by
-   invisible reference.  Normally, the caller makes a copy and passes
-   the address of the copy to the routine being called.  When
-   FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller
-   does not make a copy.  Instead, it passes a pointer to the "live"
-   value.  The called function must not modify this value.  If it can
-   be determined that the value won't be modified, it need not make a
-   copy; otherwise a copy must be made. */
-
-int
-function_arg_callee_copies (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  return TARGET_CALLEE_COPIES != 0;
-}
-
-
-/* A C statement (sans semicolon) to update the summarizer variable
-   CUM to advance past an argument in the argument list.  The values
-   MODE, TYPE and NAMED describe that argument.  Once this is done,
-   the variable CUM is suitable for analyzing the *following*
-   argument with `FUNCTION_ARG', etc.
-
-   This macro need not do anything if the argument in question was
-   passed on the stack.  The compiler knows how to track the amount
-   of stack space used for arguments without any special help. */
-
-void
-function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int align = ((cum->reg & 1) != 0
-	       && function_arg_boundary (mode, type) >= (2*BITS_PER_WORD));
-
-  int size = ((mode == BLKmode && type)
-	      ? int_size_in_bytes (type)
-	      : GET_MODE_SIZE (mode));
-
-  int words = (size + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
-
-  if (cum->reg + align + words <= (ARG_LAST - ARG_FIRST + 1))
-    cum->reg += align + words;
-  else
-#if 0 /* ??? there should be no such alignment here, but there appears to be.
-         This is probably a backend bug.  */
-    cum->stack += words;
-#else
-    cum->stack += align + words;
-#endif
-
-  if (TARGET_DEBUG_ARG)
-    fprintf (stderr,
-	     "function_adv: words = %2d %2d, mode = %4s, named = %d, align = %d, size = %3d\n",
-	     cum->reg, cum->stack, GET_MODE_NAME (mode), named, align, size);
-}
-
-
-/* Perform any needed actions needed for a function that is receiving a
-   variable number of arguments. 
-
-   CUM is as above.
-
-   MODE and TYPE are the mode and type of the current parameter.
-
-   PRETEND_SIZE is a variable that should be set to the amount of stack
-   that must be pushed by the prolog to pretend that our caller pushed
-   it.
-
-   Normally, this macro will push all remaining incoming registers on the
-   stack and set PRETEND_SIZE to the length of the registers pushed.  */
-
-void
-setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int *pretend_size;
-     int no_rtl;
-
-{
-  if (TARGET_DEBUG_ARG)
-    fprintf (stderr,
-	     "setup_vararg: words = %2d %2d, mode = %4s, no_rtl= %d\n",
-	     cum->reg, cum->stack, GET_MODE_NAME (mode), no_rtl);
-}
-
-
-/* If defined, is a C expression that produces the machine-specific
-   code for a call to `__builtin_saveregs'.  This code will be moved
-   to the very beginning of the function, before any parameter access
-   are made.  The return value of this function should be an RTX that
-   contains the value to use as the return of `__builtin_saveregs'.
-
-   The argument ARGS is a `tree_list' containing the arguments that
-   were passed to `__builtin_saveregs'.
-
-   If this macro is not defined, the compiler will output an ordinary
-   call to the library function `__builtin_saveregs'.
-   
-   On the D10V return the start address of the area on the stack
-   used to hold arguments (including the 4 words pushed at the start
-   of the function for the arguments passed in registers.  */
-
-struct rtx_def *
-expand_builtin_saveregs (args)
-     tree args;
-{
-  return gen_rtx (PLUS, Pmode,
-		  virtual_incoming_args_rtx,
-		  GEN_INT (- UNITS_PER_WORD * (ARG_LAST + 1 - ARG_FIRST)));
-}
-
-
-/* A C compound statement with a conditional `goto LABEL;' executed
-   if X (an RTX) is a legitimate memory address on the target machine
-   for a memory operand of mode MODE.
-
-   It usually pays to define several simpler macros to serve as
-   subroutines for this one.  Otherwise it may be too complicated to
-   understand.
-
-   This macro must exist in two variants: a strict variant and a
-   non-strict one.  The strict variant is used in the reload pass.  It
-   must be defined so that any pseudo-register that has not been
-   allocated a hard register is considered a memory reference.  In
-   contexts where some kind of register is required, a pseudo-register
-   with no hard register must be rejected.
-
-   The non-strict variant is used in other passes.  It must be
-   defined to accept all pseudo-registers in every context where some
-   kind of register is required.
-
-   Compiler source files that want to use the strict variant of this
-   macro define the macro `REG_OK_STRICT'.  You should use an `#ifdef
-   REG_OK_STRICT' conditional to define the strict variant in that
-   case and the non-strict variant otherwise.
-
-   Subroutines to check for acceptable registers for various purposes
-   (one for base registers, one for index registers, and so on) are
-   typically among the subroutines used to define
-   `GO_IF_LEGITIMATE_ADDRESS'.  Then only these subroutine macros
-   need have two variants; the higher levels of macros may be the
-   same whether strict or not.  */
-
-#define XREGNO_OK_FOR_BASE_P(REGNO, STRICT_P)				\
-  (GPR_P (REGNO) ||							\
-   (!STRICT_P && ((REGNO) == ARG_POINTER_REGNUM				\
-		  || (REGNO) >= FIRST_PSEUDO_REGISTER)))
-
-int
-d10v_legitimate_address_p (mode, x, strict_p)
-     enum machine_mode mode;
-     rtx x;
-     int strict_p;
-{
-  rtx x0, x1;
-  int ret = 0;
-
-  switch (GET_CODE (x))
-    {
-    default:
-      break;
-
-    case PLUS:
-      x0 = XEXP (x, 0);
-      x1 = XEXP (x, 1);
-
-      while (GET_CODE (x0) == SUBREG)
-	x0 = SUBREG_REG (x0);
-
-      while (GET_CODE (x1) == SUBREG)
-	x1 = SUBREG_REG (x1);
-
-      if (GET_CODE (x0) == REG
-	  && XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p)
-	  && CONSTANT_P (x1)
-	  && LEGITIMATE_CONSTANT_P (x1))
-	ret = 1;
-
-      break;
-
-    case SUBREG:
-      do
-	{
-	  x = SUBREG_REG (x);
-	}
-      while (GET_CODE (x) == SUBREG);	/* fall through */
-
-    case REG:
-      ret = XREGNO_OK_FOR_BASE_P (REGNO (x), strict_p);
-      break;
-
-    case CONST_INT:
-      ret = IN_RANGE_P (INTVAL (x), -32768, 32767);
-      break;
-
-    case CONST:
-    case SYMBOL_REF:
-    case LABEL_REF:
-      ret = 1;
-      break;
-
-    case POST_INC:
-      x0 = XEXP (x, 0);
-      if ((mode == HImode || mode == SImode || mode == SFmode)
-	  && GET_CODE (x0) == REG && XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
-	ret = 1;
-      break;
-
-    case POST_DEC:
-      x0 = XEXP (x, 0);
-      if ((mode == HImode || mode == SImode || mode == SFmode)
-	  && GET_CODE (x0) == REG && XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p)
-	  && REGNO (x0) != STACK_POINTER_REGNUM)
-	ret = 1;
-      break;
-
-    case PRE_DEC:
-      x0 = XEXP (x, 0);
-      if ((mode == HImode || mode == SImode || mode == SFmode)
-	  && GET_CODE (x0) == REG && REGNO (x0) == STACK_POINTER_REGNUM)
-	ret = 1;
-      break;
-    }
-
-  if (TARGET_DEBUG_ADDR)
-    {
-      fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict\n",
-	       GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ");
-      debug_rtx (x);
-    }
-
-  return ret;
-}
-
-
-
-/* A C compound statement that attempts to replace X with a valid
-   memory address for an operand of mode MODE.  WIN will be a C
-   statement label elsewhere in the code; the macro definition may use
-
-        GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
-
-   to avoid further processing if the address has become legitimate.
-
-   X will always be the result of a call to `break_out_memory_refs',
-   and OLDX will be the operand that was given to that function to
-   produce X.
-
-   The code generated by this macro should not alter the substructure
-   of X.  If it transforms X into a more legitimate form, it should
-   assign X (which will always be a C variable) a new value.
-
-   It is not necessary for this macro to come up with a legitimate
-   address.  The compiler has standard ways of doing so in all cases.
-   In fact, it is safe for this macro to do nothing.  But often a
-   machine-dependent strategy can generate better code. */
-
-struct rtx_def *
-d10v_legitimize_address (x, oldx, mode, strict_p)
-     rtx x;
-     rtx oldx;
-     enum machine_mode mode;
-     int strict_p;
-{
-  rtx ret = NULL_RTX;
-
-  if (TARGET_DEBUG_ADDR)
-    {
-      if (ret)
-	{
-	  fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, transformed:\n");
-	  debug_rtx (x);
-	  fprintf (stderr, "\ninto:\n");
-	  debug_rtx (ret);
-	}
-      else
-	{
-	  fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, did nothing with:\n");
-	  debug_rtx (x);
-	}
-    }
-
-  return ret;
-}
-
-
-/* A C statement or compound statement with a conditional `goto
-   LABEL;' executed if memory address X (an RTX) can have different
-   meanings depending on the machine mode of the memory reference it
-   is used for or if the address is valid for some modes but not
-   others.
-
-   Autoincrement and autodecrement addresses typically have
-   mode-dependent effects because the amount of the increment or
-   decrement is the size of the operand being addressed.  Some
-   machines have other mode-dependent addresses.  Many RISC machines
-   have no mode-dependent addresses.
-
-   You may assume that ADDR is a valid address for the machine. */
-
-int
-d10v_mode_dependent_address_p (addr)
-     rtx addr;
-{
-  switch (GET_CODE (addr))
-    {
-    default:
-      break;
-
-    case POST_INC:
-    case POST_DEC:
-    case PRE_DEC:
-      return 1;
-    }
-  return 0;
-}
-
-
-/* Return an RTX that refers to the nth subword of a multiword
-   expression.  This is similar to operand_subword, but that
-   has a bias that SImode is a word.  */
-
-struct rtx_def *
-d10v_subword (op, word_num, target_mode, source_mode)
-     rtx op;
-     int word_num;
-     enum machine_mode target_mode;
-     enum machine_mode source_mode;
-{
-  enum rtx_code code = GET_CODE (op);
-  enum machine_mode mode = GET_MODE (op);
-  int split_values[4];
-
-  if (!IN_RANGE_P (word_num, 0, 3))
-    error ("div10_subword_mode: Internal error -- word_num (%d) should be >= 0 && <= 3", word_num);
-
-  if (target_mode == SImode && word_num != 0 && word_num != 2)
-    error ("div10_subword_mode: Internal error -- word_num (%d) should be 0 or 2 for SImode", word_num);
-
-  if (target_mode != HImode && target_mode != SImode)
-    error ("d10v_subword_mode: Internal error -- target_mode (%s) must be HImode or SImode", GET_MODE_NAME (target_mode));
-
-  if (code == REG)
-    {
-      if ((UNITS_PER_WORD * word_num) >= GET_MODE_SIZE (mode))
-	error ("div10_subword: Internal error -- word_num (%d) is too large for mode %s",
-	       word_num, GET_MODE_NAME (mode));
-
-      if (!reload_completed)
-	return gen_rtx (SUBREG, target_mode, op, word_num);
-
-      return gen_rtx (REG, target_mode, REGNO (op) + word_num);
-    }
-
-  else if (code == SUBREG)
-    {
-      if ((UNITS_PER_WORD * word_num) >= GET_MODE_SIZE (mode))
-	error ("div10_subword: Internal error -- word_num (%d) is too large for mode %s",
-	       word_num, GET_MODE_NAME (mode));
-
-      if (!reload_completed)
-	return gen_rtx (SUBREG, target_mode, op, word_num);
-
-      do
-	{
-	  word_num += SUBREG_WORD (op);
-	  op = SUBREG_REG (op);
-	}
-      while (GET_CODE (op) == SUBREG);
-
-      return gen_rtx (REG, target_mode, REGNO (op) + word_num);
-    }
-
-  else if ((code == CONST_INT || code == CONST_DOUBLE) && GET_MODE_SIZE (source_mode) == 2)
-    {
-      if (word_num > 1)
-	error ("div10_subword: Internal error -- word_num (%d) is too large for 32-bit constants", word_num);
-
-      d10v_split_constant32 (op, split_values);
-      return GEN_INT (SIGN_EXTEND_SHORT (split_values[word_num]));
-    }
-
-  else if ((code == CONST_INT || code == CONST_DOUBLE) && GET_MODE_SIZE (source_mode) == 4)
-    {
-      d10v_split_constant32 (op, split_values);
-      return GEN_INT (SIGN_EXTEND_SHORT (split_values[word_num]));
-    }
-
-  else if ((code == CONST_INT || code == CONST_DOUBLE) && GET_MODE_SIZE (source_mode) == 8)
-    {
-      HOST_WIDE_INT value;
-
-      d10v_split_constant64 (op, split_values);
-      value = SIGN_EXTEND_SHORT (split_values[word_num]);
-      if (GET_MODE_SIZE (target_mode) == 4)
-	value = (value << 16) & (split_values[word_num+1] & 0xffff);
-
-      return GEN_INT (value);
-    }
-
-  else if (code == MEM && word_num == 0)
-    return op;
-
-  else if (code == MEM)
-    return change_address (op, target_mode, plus_constant (XEXP (op, 0), word_num * 16));
-
-  else
-    fatal_insn ("Cannot get subword of:", op);
-
-  return NULL_RTX;
-}
-
-
-/* Calculate the stack information for the current function.
-
-   D10V stack frames look like:
-
-	high		|  ....				|
-			+-------------------------------+
-			| Argument word #8		|
-			+-------------------------------+
-			| Argument word #7		|
-			+-------------------------------+
-			| Argument word #6		|
-			+-------------------------------+
-			| Argument word #5		|
-		Prev sp	+-------------------------------+
-			|				|
-			| Save for arguments 1..4 if	|
-			| the func. uses stdarg/varargs	|
-			|				|
-			+-------------------------------+
-			|				|
-			| Save area for preserved regs	|
-			|				|
-			+-------------------------------+
-			|				|
-			| Local variables		|
-			|				|
-			+-------------------------------+
-			|				|
-			| alloca space if used		|
-			|				|
-			+-------------------------------+
-			|				|
-			| Space for outgoing arguments	|
-			|				|
-			+-------------------------------+
-			| Return address if -mnew-stack	|
-			+-------------------------------+
-			| Previous sp if -mnew-stack	|
-	low	SP---->	+-------------------------------+
-*/
-
-d10v_stack_t *
-d10v_stack_info ()
-{
-  static d10v_stack_t info, zero_info;
-  d10v_stack_t *info_ptr = &info;
-  tree fndecl		 = current_function_decl;
-  tree fntype		 = TREE_TYPE (fndecl);
-  int varargs_p		 = 0;
-  tree cur_arg;
-  tree next_arg;
-  int saved_gprs;
-  int saved_accs;
-  int i;
-
-  /* If we've already calculated the values and reload is complete, just return now */
-  if (d10v_stack_cache)
-    return d10v_stack_cache;
-
-  /* Zero all fields portably */
-  info = zero_info;
-
-  if (profile_flag)
-    regs_ever_live[RETURN_ADDRESS_REGNUM] = 1;
-
-  /* Determine if this is a stdarg function */
-  if (TYPE_ARG_TYPES (fntype) != 0
-      && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
-    varargs_p = 1;
-  else
-    {
-      /* Find the last argument, and see if it is __builtin_va_alist.  */
-      for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
-	{
-	  next_arg = TREE_CHAIN (cur_arg);
-	  if (next_arg == (tree)0)
-	    {
-	      if (DECL_NAME (cur_arg)
-		  && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
-		varargs_p = 1;
-
-	      break;
-	    }
-	}
-    }
-
-  /* Calculate which registers need to be saved & save area size */
-  saved_accs = 0;
-  for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
-    {
-      if (regs_ever_live[i] && !call_used_regs[i])
-	{
-	  info_ptr->save_p[i] = 1;
-	  saved_accs++;
-	}
-    }
-
-  /* If any accumulators are to be saved, we need a one two word register
-     pair to save the main portion of the accs and another register to
-     save the guard digits.  */
-  if (saved_accs)
-    {
-      regs_ever_live[SAVE_GUARD_REGNUM] = 1;
-      regs_ever_live[SAVE_ACC_REGNUM] = 1;
-      regs_ever_live[SAVE_ACC_REGNUM+1] = 1;
-    }
-
-  saved_gprs = 0;
-  for (i = GPR_FIRST; i <= GPR_LAST; i++)
-    {
-      if (regs_ever_live[i] && (!call_used_regs[i] || i == RETURN_ADDRESS_REGNUM))
-	{
-	  info_ptr->save_p[i] = 1;
-	  saved_gprs++;
-	}
-    }
-
-  /* Determine various sizes */
-  info_ptr->varargs_p	 = varargs_p;
-  info_ptr->varargs_size = D10V_ALIGN (((varargs_p)
-					? (ARG_LAST + 1 - ARG_FIRST) * UNITS_PER_WORD
-					: 0), UNITS_PER_WORD);
-
-  info_ptr->gpr_size	 = D10V_ALIGN (UNITS_PER_WORD * saved_gprs, UNITS_PER_WORD);
-  info_ptr->accum_size	 = D10V_ALIGN (3 * UNITS_PER_WORD * saved_accs, UNITS_PER_WORD);
-  info_ptr->vars_size    = D10V_ALIGN (get_frame_size (), UNITS_PER_WORD);
-  info_ptr->parm_size    = D10V_ALIGN (current_function_outgoing_args_size, UNITS_PER_WORD);
-  info_ptr->total_size	 = D10V_ALIGN (info_ptr->gpr_size
-				       + info_ptr->accum_size
-				       + info_ptr->vars_size
-				       + info_ptr->parm_size
-				       + info_ptr->varargs_size, (STACK_BOUNDARY / BITS_PER_UNIT));
-
-  if (reload_completed)
-    d10v_stack_cache = info_ptr;
-
-  return info_ptr;
-}
-
-
-/* Internal function to print all of the information about the stack */
-
-void
-debug_stack_info (info)
-     d10v_stack_t *info;
-{
-  int i;
-
-  if (!info)
-    info = d10v_stack_info ();
-
-  fprintf (stderr, "\nStack information for function %s:\n",
-	   ((current_function_decl && DECL_NAME (current_function_decl))
-	    ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
-	    : "<unknown>"));
-
-  fprintf (stderr, "\tvarargs_p       = %d\n", info->varargs_p);
-  fprintf (stderr, "\tvarargs_size    = %d\n", info->varargs_size);
-  fprintf (stderr, "\tvars_size       = %d\n", info->vars_size);
-  fprintf (stderr, "\tparm_size       = %d\n", info->parm_size);
-  fprintf (stderr, "\tgpr_size        = %d\n", info->gpr_size);
-  fprintf (stderr, "\taccum_size      = %d\n", info->accum_size);
-  fprintf (stderr, "\ttotal_size      = %d\n", info->total_size);
-  fprintf (stderr, "\tsaved registers =");
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    if (info->save_p[i])
-      fprintf (stderr, " %s", reg_names[i]);
-
-  putc ('\n', stderr);
-  fflush (stderr);
-}
-
-
-/* Return non-zero if this function is known to have a null or 1 instruction epilogue.  */
-
-int
-direct_return ()
-{
-  if (reload_completed)
-    {
-      d10v_stack_t *info = d10v_stack_info ();
-
-      /* If no epilogue code is needed, can use just a simple jump */
-      if (info->total_size == 0)
-	return 1;
-
-      /* Also allow the common case where r13 is reloaded before the return,
-	 since we take the same space as a forward branch for the two.  */
-      if (info->total_size == UNITS_PER_WORD && info->save_p[RETURN_ADDRESS_REGNUM])
-	return 1;
-
-      /* Using similar logic, if just a small amount of local stack was allocated
-	 and no registers saved, skip forward branch */
-      if (info->total_size == info->vars_size
-	  && IN_RANGE_P (info->total_size, 1, 16))
-	return 1;
-    }
-
-  return 0;
-}
-
-
-/* Internal function to print a memory reference.  */
-
-static void
-print_memory_ref (stream, instruction, reg, offset, index_reg)
-     FILE *stream;
-     char *instruction;
-     int reg;
-     int offset;
-     int index_reg;
-{
-  if (offset == 0)
-    fprintf (stream, "\t%s %s,@%s\n", instruction, reg_names[reg],
-	     reg_names[index_reg]);
-  else
-    fprintf (stream, "\t%s %s,@(%d,%s)\n", instruction, reg_names[reg], offset,
-	     reg_names[index_reg]);
-}
-
-
-/* A C compound statement that outputs the assembler code for entry
-   to a function.  The prologue is responsible for setting up the
-   stack frame, initializing the frame pointer register, saving
-   registers that must be saved, and allocating SIZE additional bytes
-   of storage for the local variables.  SIZE is an integer.  FILE is
-   a stdio stream to which the assembler code should be output. */
-
-void
-function_prologue (stream, size)
-     FILE *stream;
-     int size;
-{
-  int i, offset;
-  d10v_stack_t *info	= d10v_stack_info ();
-  char *sp_name		= reg_names[STACK_POINTER_REGNUM];
-  int total_size	= info->total_size;
-  int gpr_size		= info->gpr_size;
-  int accum_size	= info->accum_size;
-
-  if (TARGET_DEBUG_STACK)
-    debug_stack_info (info);
-
-  /* Save any variable arguments */
-  if (info->varargs_p)
-    {
-      offset = 0;
-      for (i = ARG_LAST-1; i >= ARG_FIRST; i -= 2)
-	{
-	  fprintf (stream, "\tst2w %s,@-%s\n", reg_names[i], sp_name);
-	  offset -= 2 * UNITS_PER_WORD;
-	  total_size -= 2 * UNITS_PER_WORD;
-	}
-    }
-
-  /* Save the GPRs by pushing */
-  for (i = GPR_FIRST; i <= GPR_LAST; i++)
-    {
-      if (info->save_p[i])
-	{
-	  if (GPR_EVEN_P (i) && info->save_p[i+1])
-	    {
-	      total_size -= 2 * UNITS_PER_WORD;
-	      fprintf (stream, "\tst2w %s,@-%s\n", reg_names[i++], sp_name);
-	    }
-	  else
-	    {
-	      total_size -= UNITS_PER_WORD;
-	      fprintf (stream, "\tst %s,@-%s\n", reg_names[i], sp_name);
-	    }
-	}
-    }
-
-  /* Now save the ACs (both guard digits and 32-bit value) by moving into r12/r13 and pushing */
-  for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
-    {
-      if (info->save_p[i])
-	{
-	  total_size -= 3 * UNITS_PER_WORD;
-	  fprintf (stream, "\tmvfacg %s,%s\n", reg_names[SAVE_GUARD_REGNUM],
-		   reg_names[i]);
-
-	  fprintf (stream, "\tmv2wfac %s,%s\n", reg_names[SAVE_ACC_REGNUM],
-		   reg_names[i]);
-
-	  fprintf (stream, "\tst %s,@-%s\n", reg_names[SAVE_GUARD_REGNUM],
-		   sp_name);
-
-	  fprintf (stream, "\tst2w %s,@-%s\n", reg_names[SAVE_ACC_REGNUM],
-		   sp_name);
-	}
-    }
-
-  if (total_size > 0)
-    {
-      if (total_size <= 16)
-	fprintf (stream, "\tsubi %s,%d\n", sp_name, total_size);
-
-      else
-	fprintf (stream, "\tadd3 %s,%s,%d\n", sp_name, sp_name, -total_size);
-    }
-
-  /* Update frame pointer if needed */
-  if (frame_pointer_needed)
-    fprintf (stream, "\tmv %s,%s\n", reg_names[FRAME_POINTER_REGNUM], sp_name);
-}
-
-
-/* A C compound statement that outputs the assembler code for exit
-   from a function.  The epilogue is responsible for restoring the
-   saved registers and stack pointer to their values when the
-   function was called, and returning control to the caller.  This
-   macro takes the same arguments as the macro `FUNCTION_PROLOGUE',
-   and the registers to restore are determined from `regs_ever_live'
-   and `CALL_USED_REGISTERS' in the same way. */
-
-void
-function_epilogue (stream, size)
-     FILE *stream;
-     int size;
-{
-  int i;
-  rtx insn	= get_last_insn ();
-  char *sp_name = reg_names[STACK_POINTER_REGNUM];
-
-  /* If the last insn was a BARRIER, we don't have to write anything except
-     the trace table.  */
-  if (GET_CODE (insn) == NOTE)
-    insn = prev_nonnote_insn (insn);
-
-  if (insn == 0 ||  GET_CODE (insn) != BARRIER)
-    {
-      d10v_stack_t *info  = d10v_stack_info ();
-      int varargs_size    = info->varargs_size;
-      int stack_size	  = info->total_size - varargs_size;
-      int gpr_size	  = info->gpr_size;
-      int accum_size	  = info->accum_size;
-
-      /* If we have a varargs area, but no saved registers (ie, this is a stub)
-	 fold the varargs area back into stack size */
-      if (varargs_size && !gpr_size)
-	{
-	  stack_size += varargs_size;
-	  varargs_size = 0;
-	}
-
-      /* Restore stack pointer if needed */
-      if (frame_pointer_needed)
-	{
-	  char *fp_name = reg_names[FRAME_POINTER_REGNUM];
-
-	  /* We can combine restoring the stack pointer with the adjustment directly.  */
-	  if (stack_size > 0)
-	    {
-	      fprintf (stream, "\tadd3 %s,%s,%d\n", sp_name, fp_name, stack_size - gpr_size - accum_size);
-	      stack_size = gpr_size + accum_size;
-	    }
-	  else
-	    fprintf (stream, "\tmv %s,%s\n", sp_name, fp_name);
-	}
-
-      /* Restore stack pointer, other than the space needed to load registers w/postdecrement */
-      stack_size -= gpr_size + accum_size;
-      if (stack_size > 0)
-	{
-	  if (stack_size <= 16)
-	    fprintf (stream, "\taddi %s,%d\n", sp_name, stack_size);
-	  else
-	    fprintf (stream, "\tadd3 %s,%s,%d\n", sp_name, sp_name, stack_size);
-	}
-
-      /* Restore any saved accumulators.  We must restore both the accumulator and the guard digits */
-      for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
-	{
-	  if (info->save_p[i])
-	    {
-	      fprintf (stream, "\tld2w %s,@%s+\n", reg_names[SAVE_ACC_REGNUM],
-		       sp_name);
-
-	      fprintf (stream, "\tld %s,@%s+\n", reg_names[SAVE_GUARD_REGNUM],
-		       sp_name);
-
-	      fprintf (stream, "\tmv2wtac %s,%s\n", reg_names[SAVE_ACC_REGNUM],
-		       reg_names[i]);
-
-	      fprintf (stream, "\tmvtacg %s,%s\n", reg_names[SAVE_GUARD_REGNUM],
-		       reg_names[i]);
-	    }
-	}
-
-      /* Restore the gprs by poping the registers.  */
-      for (i = GPR_LAST; i >= GPR_FIRST; i--)
-	{
-	  if (info->save_p[i])
-	    {
-	      if (GPR_ODD_P (i) && info->save_p[i-1])
-		fprintf (stream, "\tld2w %s,@%s+\n", reg_names[--i], sp_name);
-	      else
-		fprintf (stream, "\tld %s,@%s+\n", reg_names[i], sp_name);
-	    }
-	}
-
-      /* Finally remove varargs area */
-      if (varargs_size)
-	fprintf (stream, "\taddi %s,%d\n", sp_name, varargs_size);
-
-      /* Return to the user */
-      fprintf (stream, "\tjmp %s\n", reg_names[RETURN_ADDRESS_REGNUM]);
-    }
-
-  /* Clear out stack cache */
-  d10v_stack_cache = (d10v_stack_t *)0;
-}
-/* END CYGNUS LOCAL -- meissner/d10v abi change */
diff --git a/gcc/config/d10v/d10v.h b/gcc/config/d10v/d10v.h
deleted file mode 100755
index bd77ba9..0000000
--- a/gcc/config/d10v/d10v.h
+++ /dev/null
@@ -1,5065 +0,0 @@
-/* CYGNUS LOCAL -- meissner/d10v abi change */
-/* Definitions of target machine for Mitsubishi D10V.
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Include generic ELF definitions */
-
-#include "svr4.h"
-
-/* D10v specific macros */
-
-/* Align an address */
-#define D10V_ALIGN(addr,align) (((addr) + (align) - 1) & ~((align) - 1))
-
-/* Truncate and sign extend a value to 16 bits.  */
-#define SIGN_EXTEND_SHORT(VALUE) ((int)((((VALUE) & 0xffff) ^ 0x8000) - 0x8000))
-
-
-/* Driver configuration */
-
-/* A C string constant that tells the GNU CC driver program options to
-   pass to CPP.  It can also specify how to translate options you
-   give to GNU CC into options for GNU CC to pass to the CPP.
-
-   Do not define this macro if it does not need to do anything.  */
-#define CPP_SPEC "\
-%{mint32:  -D__INT__=32 -D__INT_MAX__=2147483647} \
-%{!mint32: -D__INT__=16 -D__INT_MAX__=32767} \
-%{mdouble64: -D__DOUBLE__=64} \
-%{!mdouble64: -D__DOUBLE__=32}"
-
-/* A C string constant that tells the GNU CC driver program options to
-   pass to `cc1'.  It can also specify how to translate options you
-   give to GNU CC into options for GNU CC to pass to the `cc1'.
-
-   Do not define this macro if it does not need to do anything.  */
-/* #define CC1_SPEC */
-
-/* A C string constant that tells the GNU CC driver program options to
-   pass to `cc1plus'.  It can also specify how to translate options
-   you give to GNU CC into options for GNU CC to pass to the
-   `cc1plus'.
-
-   Do not define this macro if it does not need to do anything.  */
-/* #define CC1PLUS_SPEC */
-
-/* A C string constant that tells the GNU CC driver program options to
-   pass to the assembler.  It can also specify how to translate
-   options you give to GNU CC into options for GNU CC to pass to the
-   assembler.  See the file `sun3.h' for an example of this.
-
-   Do not define this macro if it does not need to do anything.  */
-#undef	ASM_SPEC
-#if 1
-#define ASM_SPEC "%{!mno-asm-optimize: %{O*: %{!O0: -O} %{O0: %{masm-optimize: -O}}}}"
-
-#else
-#define ASM_SPEC "%{masm-optimize: %{O*: %{!O0: -O}}} %{mno-asm-optimize: }"
-#endif
-
-/* A C string constant that tells the GNU CC driver program how to
-   run any programs which cleanup after the normal assembler.
-   Normally, this is not needed.  See the file `mips.h' for an
-   example of this.
-
-   Do not define this macro if it does not need to do anything.  */
-/* #define ASM_FINAL_SPEC */
-
-/* A C string constant that tells the GNU CC driver program options to
-   pass to the linker.  It can also specify how to translate options
-   you give to GNU CC into options for GNU CC to pass to the linker.
-
-   Do not define this macro if it does not need to do anything.  */
-/* #define LINK_SPEC */
-
-/* Another C string constant used much like `LINK_SPEC'.  The
-   difference between the two is that `LIB_SPEC' is used at the end
-   of the command given to the linker.
-
-   If this macro is not defined, a default is provided that loads the
-   standard C library from the usual place.  See `gcc.c'.  */
-#undef	LIB_SPEC
-#define LIB_SPEC "%{msim: %e-msim is no longer supported} -lc -lnosys"
-
-/* Another C string constant that tells the GNU CC driver program how
-   and when to place a reference to `libgcc.a' into the linker
-   command line.  This constant is placed both before and after the
-   value of `LIB_SPEC'.
-
-   If this macro is not defined, the GNU CC driver provides a default
-   that passes the string `-lgcc' to the linker unless the `-shared'
-   option is specified.  */
-/* #define LIBGCC_SPEC */
-
-/* Another C string constant used much like `LINK_SPEC'.  The
-   difference between the two is that `STARTFILE_SPEC' is used at the
-   very beginning of the command given to the linker.
-
-   If this macro is not defined, a default is provided that loads the
-   standard C startup file from the usual place.  See `gcc.c'.  */
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC "crt0%O%s"
-
-
-/* Another C string constant used much like `LINK_SPEC'.  The
-   difference between the two is that `ENDFILE_SPEC' is used at the
-   very end of the command given to the linker.
-
-   Do not define this macro if it does not need to do anything.  */
-#undef	ENDFILE_SPEC
-#define ENDFILE_SPEC ""
-
-/* Define this macro to provide additional specifications to put in
-   the `specs' file that can be used in various specifications like
-   `CC1_SPEC'.
-
-   The definition should be an initializer for an array of structures,
-   containing a string constant, that defines the specification name,
-   and a string constant that provides the specification.
-
-   Do not define this macro if it does not need to do anything.  */
-/* #define EXTRA_SPECS */
-
-/* Define this macro as a C expression for the initializer of an
-   array of string to tell the driver program which options are
-   defaults for this target and thus do not need to be handled
-   specially when using `MULTILIB_OPTIONS'.
-
-   Do not define this macro if `MULTILIB_OPTIONS' is not defined in
-   the target makefile fragment or if none of the options listed in
-   `MULTILIB_OPTIONS' are set by default.  *Note Target Fragment::.  */
-#define MULTILIB_DEFAULTS { "mint16", "mdouble32" }
-
-
-/* Run-time target specifications */
-
-/* Define this to be a string constant containing `-D' options to
-   define the predefined macros that identify this machine and system.
-   These macros will be predefined unless the `-ansi' option is
-   specified.
-
-   In addition, a parallel set of macros are predefined, whose names
-   are made by appending `__' at the beginning and at the end.  These
-   `__' macros are permitted by the ANSI standard, so they are
-   predefined regardless of whether `-ansi' is specified.  */
-#define CPP_PREDEFINES "-D__D10V__ -Amachine(d10v)"
-
-/* Variable to hold flag bits.  */
-extern int target_flags;
-
-/* Machine dependent switche bits */
-#define MASK_INT32		0x00000001		/* ints are 32 bits */
-#define MASK_DOUBLE64		0x00000002		/* double is 64 bits */
-#define MASK_ADDAC3		0x00000004		/* enable ADDAC3/SUBAC3 instructions */
-#define MASK_ACCUM		0x00000008		/* allow use of the accumulators */
-#define MASK_NO_CALLEE_COPIES	0x00000010		/* disable callee copies */
-#define MASK_NO_SMALL_INSNS	0x00000020		/* disable replacing 1 long insn with 2 short ones */
-#define MASK_NO_COND_MOVE	0x00000040		/* disable conditional moves */
-#define MASK_NO_LONGLONG_ALU	0x00000080		/* disable long long plus/minus */
-
-#define MASK_DEBUG_MOVE4	0x04000000		/* debug emit_move4_words */
-#define MASK_DEBUG_STACK	0x08000000		/* debug stack offsets */
-#define MASK_DEBUG_ARG		0x10000000		/* debug FUNCTION_ARG */
-#define MASK_DEBUG_ADDR		0x20000000		/* debug GO_IF_LEGITIMATE_ADDRESS */
-#define MASK_DEBUG		0x40000000		/* general debug flag */
-
-#ifndef TARGET_DEFAULT
-/* XXX: The normal scheduler seems to have a bug regarding no callee copies, so for
-   now, just set the default appropriately.  */
-#ifndef HAIFA
-#define TARGET_DEFAULT	MASK_NO_CALLEE_COPIES
-#else
-#define TARGET_DEFAULT 0
-#endif
-#endif
-
-/* Machine dependent switches */
-#define TARGET_INT32			(target_flags & MASK_INT32)
-#define TARGET_DOUBLE64			(target_flags & MASK_DOUBLE64)
-#define TARGET_ADDAC3			(target_flags & MASK_ADDAC3)
-#define TARGET_ACCUM			(target_flags & MASK_ACCUM)
-#define TARGET_NO_CALLEE_COPIES		(target_flags & MASK_NO_CALLEE_COPIES)
-#define TARGET_NO_SMALL_INSNS		(target_flags & MASK_NO_SMALL_INSNS)
-#define TARGET_NO_COND_MOVE		(target_flags & MASK_NO_COND_MOVE)
-#define TARGET_NO_LONGLONG_ALU		(target_flags & MASK_NO_LONGLONG_ALU)
-#define TARGET_DEBUG_MOVE4		(target_flags & MASK_DEBUG_MOVE4)
-#define TARGET_DEBUG_STACK		(target_flags & MASK_DEBUG_STACK)
-#define TARGET_DEBUG_ARG		(target_flags & MASK_DEBUG_ARG)
-#define TARGET_DEBUG_ADDR		(target_flags & MASK_DEBUG_ADDR)
-#define TARGET_DEBUG			(target_flags & MASK_DEBUG)
-
-#define TARGET_INT16			(! TARGET_INT32)
-#define TARGET_DOUBLE32			(! TARGET_DOUBLE64)
-#define TARGET_CALLEE_COPIES		(! TARGET_NO_CALLEE_COPIES)
-#define TARGET_SMALL_INSNS		(! TARGET_NO_SMALL_INSNS)
-#define TARGET_COND_MOVE		(! TARGET_NO_COND_MOVE)
-#define TARGET_LONGLONG_ALU		(! TARGET_NO_LONGLONG_ALU)
-
-/* This macro defines names of command options to set and clear bits
-   in `target_flags'.  Its definition is an initializer with a
-   subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   option name, and a number, which contains the bits to set in
-   `target_flags'.  A negative number says to clear bits instead; the
-   negative of the number is which bits to clear.  The actual option
-   name is made by appending `-m' to the specified name.
-
-   One of the subgroupings should have a null string.  The number in
-   this grouping is the default value for `target_flags'.  Any target
-   options act starting with that value.  */
-#define TARGET_SWITCHES							\
-{									\
-  { "int16",		-MASK_INT32 },					\
-  { "int32",		 MASK_INT32 },					\
-  { "double64",		 MASK_DOUBLE64 },				\
-  { "double32",		-MASK_DOUBLE64 },				\
-  { "addac3",		 MASK_ADDAC3 | MASK_ACCUM },			\
-  { "no-addac3",	-MASK_ADDAC3 },					\
-  { "accum",		 MASK_ACCUM },					\
-  { "no-accum",		-MASK_ACCUM },					\
-  { "callee-copies",	-MASK_NO_CALLEE_COPIES },			\
-  { "no-callee-copies",	 MASK_NO_CALLEE_COPIES },			\
-  { "small-insns",	-MASK_NO_SMALL_INSNS },				\
-  { "no-small-insns",	 MASK_NO_SMALL_INSNS },				\
-  { "cond-move",	-MASK_NO_COND_MOVE },				\
-  { "no-cond-move",	 MASK_NO_COND_MOVE },				\
-  { "longlong-alu",	-MASK_NO_LONGLONG_ALU },			\
-  { "no-longlong-alu",	 MASK_NO_LONGLONG_ALU },			\
-  { "debug",		 MASK_DEBUG },					\
-  { "debug-arg",	 MASK_DEBUG_ARG },				\
-  { "debug-addr",	 MASK_DEBUG_ADDR },				\
-  { "debug-stack",	 MASK_DEBUG_STACK },				\
-  { "debug-move4",	 MASK_DEBUG_MOVE4 },				\
-  { "asm-optimize",	 0 },						\
-  { "no-asm-optimize",	 0 },						\
-  { "",			 TARGET_DEFAULT }				\
-}
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an
-   initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   fixed part of the option name, and the address of a variable.  The
-   variable, type `char *', is set to the variable part of the given
-   option if the fixed part matches.  The actual option name is made
-   by appending `-m' to the specified name.  */
-
-#define TARGET_OPTIONS							\
-{									\
-   {"branch-cost=",  &d10v_branch_cost_string},				\
-   {"cond-exec=",    &d10v_cond_exec_string},				\
-}
-
-/* This macro is a C statement to print on `stderr' a string
-   describing the particular machine description choice.  Every
-   machine description should define `TARGET_VERSION'.  */
-#define TARGET_VERSION fprintf (stderr, " (D10V)")
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-#define OVERRIDE_OPTIONS override_options ()
-
-/* Some machines may desire to change what optimizations are
-   performed for various optimization levels.   This macro, if
-   defined, is executed once just after the optimization level is
-   determined and before the remainder of the command options have
-   been parsed.  Values set in this macro are used as the default
-   values for the other command line options.
-
-   LEVEL is the optimization level specified; 2 if `-O2' is
-   specified, 1 if `-O' is specified, and 0 if neither is specified.
-
-   SIZE is non-zero if `-Os' is specified, 0 otherwise.  
-
-   On the d10v, turn off scheduling before register allocation, since
-   it makes for more spills and increases the register pressure.  There
-   is also a bug between passing 64 bit values by reference that the
-   scheduler tweaks.  */
-
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)				\
-do {									\
-  if ((LEVEL) > 1)							\
-    flag_schedule_insns = 0;						\
-} while (0)
-
-/* Define this macro if debugging can be performed even without a
-   frame pointer.  If this macro is defined, GNU CC will turn on the
-   `-fomit-frame-pointer' option whenever `-O' is specified.  */
-#define CAN_DEBUG_WITHOUT_FP 1
-
-
-/* Storage layout */
-
-/* Define this macro to have the value 1 if the most significant bit
-   in a byte has the lowest number; otherwise define it to have the
-   value zero.  This means that bit-field instructions count from the
-   most significant bit.  If the machine has no bit-field
-   instructions, then this must still be defined, but it doesn't
-   matter which value it is defined to.  This macro need not be a
-   constant.
-
-   This macro does not affect the way structure fields are packed into
-   bytes or words; that is controlled by `BYTES_BIG_ENDIAN'.  */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this macro to have the value 1 if the most significant byte
-   in a word has the lowest number.  This macro need not be a
-   constant.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this macro to have the value 1 if, in a multiword object,
-   the most significant word has the lowest number.  This applies to
-   both memory locations and registers; GNU CC fundamentally assumes
-   that the order of words in memory is the same as the order in
-   registers.  This macro need not be a constant.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* Define this macro if WORDS_BIG_ENDIAN is not constant.  This must
-   be a constant value with the same meaning as WORDS_BIG_ENDIAN,
-   which will be used only when compiling libgcc2.c.  Typically the
-   value will be set based on preprocessor defines.  */
-/* #define LIBGCC2_WORDS_BIG_ENDIAN 1 */
-
-/* Define this macro to have the value 1 if `DFmode', `XFmode' or
-   `TFmode' floating point numbers are stored in memory with the word
-   containing the sign bit at the lowest address; otherwise define it
-   to have the value 0.  This macro need not be a constant.
-
-   You need not define this macro if the ordering is the same as for
-   multi-word integers. */
-/* #define FLOAT_WORDS_BIG_ENDIAN 1 */
-
-/* Define this macro to be the number of bits in an addressable
-   storage unit (byte); normally 8.  */
-#define BITS_PER_UNIT 8
-
-/* Number of bits in a word; normally 32. */
-#define BITS_PER_WORD 16
-
-/* Maximum number of bits in a word.  If this is undefined, the
-   default is `BITS_PER_WORD'.  Otherwise, it is the constant value
-   that is the largest value that `BITS_PER_WORD' can have at
-   run-time.  */
-#define MAX_BITS_PER_WORD 16
-
-/* Number of storage units in a word; normally 4.  */
-#define UNITS_PER_WORD 2
-
-/* Minimum number of units in a word.  If this is undefined, the
-   default is `UNITS_PER_WORD'.  Otherwise, it is the constant value
-   that is the smallest value that `UNITS_PER_WORD' can have at
-   run-time.  */
-#define MIN_UNITS_PER_WORD 2
-
-/* Normal alignment required for function parameters on the stack, in
-   bits.  All stack parameters receive at least this much alignment
-   regardless of data type.  On most machines, this is the same as the
-   size of an integer. */
-#define PARM_BOUNDARY 16
-
-/* Define this macro if you wish to preserve a certain alignment for
-   the stack pointer.  The definition is a C expression for the
-   desired alignment (measured in bits).
-
-   If `PUSH_ROUNDING' is not defined, the stack will always be aligned
-   to the specified boundary.  If `PUSH_ROUNDING' is defined and
-   specifies a less strict alignment than `STACK_BOUNDARY', the stack
-   may be momentarily unaligned while pushing arguments. */
-#define STACK_BOUNDARY 16
-
-/* Alignment required for a function entry point, in bits. */
-#define FUNCTION_BOUNDARY 32
-
-/* Biggest alignment that any data type can require on this machine,
-   in bits. */
-#define BIGGEST_ALIGNMENT 16
-
-/* Biggest alignment that any structure field can require on this
-   machine, in bits.  If defined, this overrides `BIGGEST_ALIGNMENT'
-   for structure fields only. */
-/* #define BIGGEST_FIELD_ALIGNMENT */
-
-/* An expression for the alignment of a structure field FIELD if the
-   alignment computed in the usual way is COMPUTED.  GNU CC uses this
-   value instead of the value in `BIGGEST_ALIGNMENT' or
-   `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
-/* #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) */
-
-/* Biggest alignment supported by the object file format of this
-   machine.  Use this macro to limit the alignment which can be
-   specified using the `__attribute__ ((aligned (N)))' construct.  If
-   not defined, the default value is `BIGGEST_ALIGNMENT'. */
-/* #define MAX_OFILE_ALIGNMENT */
-
-/* If defined, a C expression to compute the alignment for a static
-   variable.  TYPE is the data type, and BASIC-ALIGN is the alignment
-   that the object would ordinarily have.  The value of this macro is
-   used instead of that alignment to align the object.
-
-   If this macro is not defined, then BASIC-ALIGN is used.
-
-   One use of this macro is to increase alignment of medium-size data
-   to make it all fit in fewer cache lines.  Another is to cause
-   character arrays to be word-aligned so that `strcpy' calls that
-   copy constants to character arrays can be done inline. */
-/* #define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) */
-
-/* If defined, a C expression to compute the alignment given to a
-   constant that is being placed in memory.  CONSTANT is the constant
-   and BASIC-ALIGN is the alignment that the object would ordinarily
-   have.  The value of this macro is used instead of that alignment to
-   align the object.
-
-   If this macro is not defined, then BASIC-ALIGN is used.
-
-   The typical use of this macro is to increase alignment for string
-   constants to be word aligned so that `strcpy' calls that copy
-   constants can be done inline. */
-/* #define CONSTANT_ALIGNMENT(CONSTANT, BASIC-ALIGN) */
-
-/* Alignment in bits to be given to a structure bit field that
-   follows an empty field such as `int : 0;'.
-
-   Note that `PCC_BITFIELD_TYPE_MATTERS' also affects the alignment
-   that results from an empty field. */
-/* #define EMPTY_FIELD_BOUNDARY */
-
-/* Number of bits which any structure or union's size must be a
-   multiple of.  Each structure or union's size is rounded up to a
-   multiple of this.
-
-   If you do not define this macro, the default is the same as
-   `BITS_PER_UNIT'.  */
-/* #define STRUCTURE_SIZE_BOUNDARY */
-
-/* Define this macro to be the value 1 if instructions will fail to
-   work if given data not on the nominal alignment.  If instructions
-   will merely go slower in that case, define this macro as 0. */
-#define STRICT_ALIGNMENT 1
-
-/* Define this if you wish to imitate the way many other C compilers
-   handle alignment of bitfields and the structures that contain them.
-
-   The behavior is that the type written for a bitfield (`int',
-   `short', or other integer type) imposes an alignment for the
-   entire structure, as if the structure really did contain an
-   ordinary field of that type.  In addition, the bitfield is placed
-   within the structure so that it would fit within such a field, not
-   crossing a boundary for it.
-
-   Thus, on most machines, a bitfield whose type is written as `int'
-   would not cross a four-byte boundary, and would force four-byte
-   alignment for the whole structure.  (The alignment used may not be
-   four bytes; it is controlled by the other alignment parameters.)
-
-   If the macro is defined, its definition should be a C expression;
-   a nonzero value for the expression enables this behavior.
-
-   Note that if this macro is not defined, or its value is zero, some
-   bitfields may cross more than one alignment boundary.  The
-   compiler can support such references if there are `insv', `extv',
-   and `extzv' insns that can directly reference memory.
-
-   The other known way of making bitfields work is to define
-   `STRUCTURE_SIZE_BOUNDARY' as large as `BIGGEST_ALIGNMENT'.  Then
-   every structure can be accessed with fullwords.
-
-   Unless the machine has bitfield instructions or you define
-   `STRUCTURE_SIZE_BOUNDARY' that way, you must define
-   `PCC_BITFIELD_TYPE_MATTERS' to have a nonzero value.  */
-/* #define PCC_BITFIELD_TYPE_MATTERS */
-
-/* Like PCC_BITFIELD_TYPE_MATTERS except that its effect is limited to
-   aligning a bitfield within the structure. */
-/* #define BITFIELD_NBYTES_LIMITED */
-
-/* Define this macro as an expression for the overall size of a
-   structure (given by STRUCT as a tree node) when the size computed
-   from the fields is SIZE and the alignment is ALIGN.
-
-   The default is to round SIZE up to a multiple of ALIGN. */
-/* #define ROUND_TYPE_SIZE(STRUCT, SIZE, ALIGN) */
-
-/* Define this macro as an expression for the alignment of a structure
-   (given by STRUCT as a tree node) if the alignment computed in the
-   usual way is COMPUTED and the alignment explicitly specified was
-   SPECIFIED.
-
-   The default is to use SPECIFIED if it is larger; otherwise, use
-   the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
-/* #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) */
-
-/* An integer expression for the size in bits of the largest integer
-   machine mode that should actually be used.  All integer machine
-   modes of this size or smaller can be used for structures and
-   unions with the appropriate sizes.  If this macro is undefined,
-   `GET_MODE_BITSIZE (DImode)' is assumed. */
-/* #define MAX_FIXED_MODE_SIZE */
-
-/* A C statement to validate the value VALUE (of type `double') for
-   mode MODE.  This means that you check whether VALUE fits within
-   the possible range of values for mode MODE on this target machine.
-   The mode MODE is always a mode of class `MODE_FLOAT'.  OVERFLOW
-   is nonzero if the value is already known to be out of range.
-
-   If VALUE is not valid or if OVERFLOW is nonzero, you should set
-   OVERFLOW to 1 and then assign some valid value to VALUE.  Allowing
-   an invalid value to go through the compiler can produce incorrect
-   assembler code which may even cause Unix assemblers to crash.
-
-   This macro need not be defined if there is no work for it to do. */
-/* #define CHECK_FLOAT_VALUE(MODE, VALUE, OVERFLOW) */
-
-/* A code distinguishing the floating point format of the target
-   machine.  There are three defined values:
-
-  `IEEE_FLOAT_FORMAT'
-        This code indicates IEEE floating point.  It is the default;
-        there is no need to define this macro when the format is IEEE.
-
-  `VAX_FLOAT_FORMAT'
-        This code indicates the peculiar format used on the Vax.
-
-  `UNKNOWN_FLOAT_FORMAT'
-        This code indicates any other format.
-
-   The value of this macro is compared with `HOST_FLOAT_FORMAT'
-   (*note Config::.) to determine whether the target machine has the
-   same format as the host machine.  If any other formats are
-   actually in use on supported machines, new codes should be defined
-   for them.
-
-   The ordering of the component words of floating point values
-   stored in memory is controlled by `FLOAT_WORDS_BIG_ENDIAN' for the
-   target machine and `HOST_FLOAT_WORDS_BIG_ENDIAN' for the host. */
-#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
-
-
-/* Layout of Source Language Data Types */
-
-/* Width of a pointer, in bits.  You must specify a value no wider
-   than the width of `Pmode'.  If it is not equal to the width of
-   `Pmode', you must define `POINTERS_EXTEND_UNSIGNED'.  */
-#define POINTER_SIZE 16
-
-/* A C expression whose value is nonzero if pointers that need to be
-   extended from being `POINTER_SIZE' bits wide to `Pmode' are
-   sign-extended and zero if they are zero-extended.
-
-   You need not define this macro if the `POINTER_SIZE' is equal to
-   the width of `Pmode'.  */
-#define POINTERS_EXTEND_UNSIGNED 1
-
-/* A C expression for the size in bits of the type `int' on the
-   target machine.  If you don't define this, the default is one word.  */
-#define INT_TYPE_SIZE (TARGET_INT32 ? 32 : 16)
-
-/* Maximum number for the size in bits of the type `int' on the target
-   machine.  If this is undefined, the default is `INT_TYPE_SIZE'.
-   Otherwise, it is the constant value that is the largest value that
-   `INT_TYPE_SIZE' can have at run-time.  This is used in `cpp'.  */
-#define MAX_INT_TYPE_SIZE 32
-
-/* A C expression for the size in bits of the type `short' on the
-   target machine.  If you don't define this, the default is half a
-   word.  (If this would be less than one storage unit, it is rounded
-   up to one unit.)  */
-#define SHORT_TYPE_SIZE 16
-
-/* A C expression for the size in bits of the type `long' on the
-   target machine.  If you don't define this, the default is one word.  */
-#define LONG_TYPE_SIZE 32
-
-/* Maximum number for the size in bits of the type `long' on the
-   target machine.  If this is undefined, the default is
-   `LONG_TYPE_SIZE'.  Otherwise, it is the constant value that is the
-   largest value that `LONG_TYPE_SIZE' can have at run-time.  This is
-   used in `cpp'.  */
-#define MAX_LONG_TYPE_SIZE 32
-
-/* A C expression for the size in bits of the type `long long' on the
-   target machine.  If you don't define this, the default is two
-   words.  If you want to support GNU Ada on your machine, the value
-   of macro must be at least 64.  */
-#define LONG_LONG_TYPE_SIZE 64
-
-/* A C expression for the size in bits of the type `char' on the
-   target machine.  If you don't define this, the default is one
-   quarter of a word.  (If this would be less than one storage unit,
-   it is rounded up to one unit.)  */
-#define CHAR_TYPE_SIZE 8
-
-/* Maximum number for the size in bits of the type `char' on the
-   target machine.  If this is undefined, the default is
-   `CHAR_TYPE_SIZE'.  Otherwise, it is the constant value that is the
-   largest value that `CHAR_TYPE_SIZE' can have at run-time.  This is
-   used in `cpp'.  */
-#define MAX_CHAR_TYPE_SIZE 8
-
-/* A C expression for the size in bits of the type `float' on the
-   target machine.  If you don't define this, the default is one word. */
-#define FLOAT_TYPE_SIZE 32
-
-/* A C expression for the size in bits of the type `double' on the
-   target machine.  If you don't define this, the default is two
-   words.  */
-#define DOUBLE_TYPE_SIZE ((TARGET_DOUBLE64) ? 64 : 32)
-
-/* A C expression for the size in bits of the type `long double' on
-   the target machine.  If you don't define this, the default is two
-   words.  */
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* An expression whose value is 1 or 0, according to whether the type
-   `char' should be signed or unsigned by default.  The user can
-   always override this default with the options `-fsigned-char' and
-   `-funsigned-char'.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* A C expression to determine whether to give an `enum' type only as
-   many bytes as it takes to represent the range of possible values
-   of that type.  A nonzero value means to do that; a zero value
-   means all `enum' types should be allocated like `int'.
-
-   If you don't define the macro, the default is 0.  */
-#define DEFAULT_SHORT_ENUMS 0
-
-/* A C expression for a string describing the name of the data type
-   to use for size values.  The typedef name `size_t' is defined
-   using the contents of the string.
-
-   The string can contain more than one keyword.  If so, separate
-   them with spaces, and write first any length keyword, then
-   `unsigned' if appropriate, and finally `int'.  The string must
-   exactly match one of the data type names defined in the function
-   `init_decl_processing' in the file `c-decl.c'.  You may not omit
-   `int' or change the order--that would cause the compiler to crash
-   on startup.
-
-   If you don't define this macro, the default is `"long unsigned
-   int"'.
-
-   On the D10V, ints can be either 16 or 32 bits, so we need to adjust
-   size_t appropriately.  */
-#undef	SIZE_TYPE
-#define SIZE_TYPE "short unsigned int"
-
-/* A C expression for a string describing the name of the data type
-   to use for the result of subtracting two pointers.  The typedef
-   name `ptrdiff_t' is defined using the contents of the string.  See
-   `SIZE_TYPE' above for more information.
-
-   If you don't define this macro, the default is `"long int"'.  */
-#undef	PTRDIFF_TYPE
-#define PTRDIFF_TYPE "short int"
-
-/* A C expression for a string describing the name of the data type
-   to use for wide characters.  The typedef name `wchar_t' is defined
-   using the contents of the string.  See `SIZE_TYPE' above for more
-   information.
-
-   If you don't define this macro, the default is `"int"'.  */
-#undef	WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-
-/* A C expression for the size in bits of the data type for wide
-   characters.  This is used in `cpp', which cannot make use of
-   `WCHAR_TYPE'.  */
-#undef	WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
-
-/* Maximum number for the size in bits of the data type for wide
-   characters.  If this is undefined, the default is
-   `WCHAR_TYPE_SIZE'.  Otherwise, it is the constant value that is the
-   largest value that `WCHAR_TYPE_SIZE' can have at run-time.  This is
-   used in `cpp'.  */
-#define MAX_WCHAR_TYPE_SIZE 16
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-
-/* Basic Characteristics of Registers */
-
-/* Return true if a value is inside a range */
-#define IN_RANGE_P(VALUE, LOW, HIGH) \
-  (((unsigned)((VALUE) - (LOW))) <= ((unsigned)((HIGH) - (LOW))))
-
-/* First/last general purpose registers */
-#define GPR_FIRST	0
-#define GPR_LAST	15
-#define GPR_ZERO_REGNUM	(GPR_FIRST + 14)	/* register that holds 0 */
-#define GPR_P(REGNO)	IN_RANGE_P (REGNO, GPR_FIRST, GPR_LAST)
-#define GPR_OR_PSEUDO_P(REGNO) (GPR_P (REGNO) || REGNO >= FIRST_PSEUDO_REGISTER)
-
-/* Registers arguments are passed in */
-#define ARG_FIRST	(GPR_FIRST + 0)
-#define ARG_LAST	(GPR_FIRST + 3)
-#define RETURN_REGNUM	ARG_FIRST
-
-/* Register pair to save accumulators in */
-#define SAVE_ACC_REGNUM	(GPR_FIRST + 12)
-
-/* Register to save accumulator guard digits in */
-#define SAVE_GUARD_REGNUM (GPR_FIRST + 5)
-
-/* Even/odd registers for multiword items */
-#define GPR_EVEN_P(REGNO) (GPR_P(REGNO) && ((((REGNO) - GPR_FIRST) & 1) == 0))
-#define GPR_ODD_P(REGNO)  (GPR_P(REGNO) && ((((REGNO) - GPR_FIRST) & 1) != 0))
-
-/* First/last control registers */
-#define CR_FIRST	16
-#define CR_LAST		31
-#define CR_P(REGNO)	IN_RANGE_P (REGNO, CR_FIRST, CR_LAST)
-
-#define REPEAT_REGNUM	(CR_FIRST + 7)
-
-/* First/last accumulator registers */
-#define ACCUM_FIRST	32
-#define ACCUM_LAST	33
-#define ACCUM_P(REGNO)	IN_RANGE_P (REGNO, ACCUM_FIRST, ACCUM_LAST)
-
-/* Argument pointer pseudo register */
-#define AP_FIRST	34
-
-/* Condition/carry code 'registers'.  We ignore the fact that these
-   are actually stored in CR0.  */
-#define CC_FIRST	35
-#define CC_LAST		37
-#define CC_P(REGNO)	IN_RANGE_P (REGNO, CC_FIRST, CC_LAST)
-
-#define F0_REGNUM	(CC_FIRST + 0)
-#define F1_REGNUM	(CC_FIRST + 1)
-#define CARRY_REGNUM	(CC_FIRST + 2)
-
-/* Number of hardware registers known to the compiler.  They receive
-   numbers 0 through `FIRST_PSEUDO_REGISTER-1'; thus, the first
-   pseudo register's number really is assigned the number
-   `FIRST_PSEUDO_REGISTER'. */
-#define FIRST_PSEUDO_REGISTER 38
-
-/* An initializer that says which registers are used for fixed
-   purposes all throughout the compiled code and are therefore not
-   available for general allocation.  These would include the stack
-   pointer, the frame pointer (except on machines where that can be
-   used as a general register when no frame pointer is needed), the
-   program counter on machines where that is considered one of the
-   addressable registers, and any other numbered register with a
-   standard use.
-
-   This information is expressed as a sequence of numbers, separated
-   by commas and surrounded by braces.  The Nth number is 1 if
-   register N is fixed, 0 otherwise.
-
-   The table initialized from this macro, and the table initialized by
-   the following one, may be overridden at run time either
-   automatically, by the actions of the macro
-   `CONDITIONAL_REGISTER_USAGE', or by the user with the command
-   options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */
-#define FIXED_REGISTERS							\
-{									\
-  0, /* r0   */	0, /* r1   */	0, /* r2   */	0, /* r3   */		\
-  0, /* r4   */	0, /* r5   */	0, /* r6   */	0, /* r7   */		\
-  0, /* r8   */	0, /* r9   */	0, /* r10  */	0, /* r11  */		\
-  0, /* r12  */	0, /* r13  */	1, /* r14  */	1, /* r15  */		\
-  1, /* cr0  */	1, /* cr1  */	1, /* cr2  */	1, /* cr3  */		\
-  1, /* cr4  */	1, /* cr5  */	1, /* cr6  */	1, /* cr7  */		\
-  1, /* cr8  */	1, /* cr9  */	1, /* cr10 */	1, /* cr11 */		\
-  1, /* cr12 */	1, /* cr13 */	1, /* cr14 */	1, /* cr15 */		\
-  1, /* a0   */	1, /* a1   */						\
-  1, /* ap   */								\
-  1, /* f0   */	1, /* f1   */	1, /* c    */				\
-}
-
-/* Like `FIXED_REGISTERS' but has 1 for each register that is
-   clobbered (in general) by function calls as well as for fixed
-   registers.  This macro therefore identifies the registers that are
-   not available for general allocation of values that must live
-   across function calls.
-
-   If a register has 0 in `CALL_USED_REGISTERS', the compiler
-   automatically saves it on function entry and restores it on
-   function exit, if the register is used within the function. */
-#define CALL_USED_REGISTERS						\
-{									\
-  1, /* r0   */	1, /* r1   */	1, /* r2   */	1, /* r3   */		\
-  1, /* r4   */ 1, /* r5   */	0, /* r6   */	0, /* r7   */		\
-  0, /* r8   */	0, /* r9   */	0, /* r10  */	0, /* r11  */		\
-  1, /* r12  */	1, /* r13  */	1, /* r14  */	1, /* r15  */		\
-  1, /* cr0  */	1, /* cr1  */	1, /* cr2  */	1, /* cr3  */		\
-  1, /* cr4  */	1, /* cr5  */	1, /* cr6  */	1, /* cr7  */		\
-  1, /* cr8  */	1, /* cr9  */	1, /* cr10 */	1, /* cr11 */		\
-  1, /* cr12 */	1, /* cr13 */	1, /* cr14 */	1, /* cr15 */		\
-  1, /* a0   */	1, /* a1   */						\
-  1, /* ap   */								\
-  1, /* f0   */	1, /* f1   */	1, /* c    */				\
-}
-
-/* Zero or more C statements that may conditionally modify two
-   variables `fixed_regs' and `call_used_regs' (both of type `char
-   []') after they have been initialized from the two preceding
-   macros.
-
-   This is necessary in case the fixed or call-clobbered registers
-   depend on target flags. */
-#define CONDITIONAL_REGISTER_USAGE					\
-do									\
-  {									\
-    if (TARGET_ACCUM)							\
-      {									\
-	int i;								\
-	for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)			\
-	  fixed_regs[i] = call_used_regs[i] = 0;			\
-      }									\
-  }									\
-while (0)
-
-/* If this macro is defined and has a nonzero value, it means that
-   `setjmp' and related functions fail to save the registers, or that
-   `longjmp' fails to restore them.  To compensate, the compiler
-   avoids putting variables in registers in functions that use
-   `setjmp'. */
-/* #define NON_SAVING_SETJMP */
-
-
-/* Order of allocating registers */
-
-/* If defined, an initializer for a vector of integers, containing the
-   numbers of hard registers in the order in which GNU CC should
-   prefer to use them (from most preferred to least).
-
-   If this macro is not defined, registers are used lowest numbered
-   first (all else being equal).
-
-   One use of this macro is on machines where the highest numbered
-   registers must always be saved and the save-multiple-registers
-   instruction supports only sequences of consecutive registers.  On
-   such machines, define `REG_ALLOC_ORDER' to be an initializer that
-   lists the highest numbered allocatable register first.
-
-   On the d10v, we save some time by putting the fixed registers at
-   the end of the list.  Also, we put the odd registers whose even
-   register is fixed before the even/odd register pairs.  */
-#define REG_ALLOC_ORDER							\
-{									\
-  /* Volatile GPR registers */						\
-  GPR_FIRST+0,								\
-  GPR_FIRST+1,								\
-  GPR_FIRST+2,								\
-  GPR_FIRST+3,								\
-  GPR_FIRST+4,								\
-  GPR_FIRST+5,								\
-  GPR_FIRST+12,								\
-  GPR_FIRST+13,								\
-									\
-  /* Callee preserved GPR registers */					\
-  GPR_FIRST+6,								\
-  GPR_FIRST+7,								\
-  GPR_FIRST+8,								\
-  GPR_FIRST+9,								\
-  GPR_FIRST+10,								\
-  GPR_FIRST+11,								\
-									\
-  /* Accumulators */							\
-  ACCUM_FIRST+0,							\
-  ACCUM_FIRST+1,							\
-									\
-  /* Repeat count register */						\
-  REPEAT_REGNUM,							\
-									\
-  /* Condition code, carry registers */					\
-  F0_REGNUM,								\
-  F1_REGNUM,								\
-  CARRY_REGNUM,								\
-									\
-  /* Fixed registers */							\
-  GPR_FIRST+14,			/* zero register */			\
-  GPR_FIRST+15,			/* stack pointer */			\
-  CR_FIRST+0,								\
-  CR_FIRST+1,								\
-  CR_FIRST+2,								\
-  CR_FIRST+3,								\
-  CR_FIRST+4,								\
-  CR_FIRST+5,								\
-  CR_FIRST+6,								\
-  CR_FIRST+8,								\
-  CR_FIRST+9,								\
-  CR_FIRST+10,								\
-  CR_FIRST+11,								\
-  CR_FIRST+12,								\
-  CR_FIRST+13,								\
-  CR_FIRST+14,								\
-  CR_FIRST+15,								\
-  ARG_POINTER_REGNUM,							\
-}
-
-/* A C statement (sans semicolon) to choose the order in which to
-   allocate hard registers for pseudo-registers local to a basic
-   block.
-
-   Store the desired register order in the array `reg_alloc_order'.
-   Element 0 should be the register to allocate first; element 1, the
-   next register; and so on.
-
-   The macro body should not assume anything about the contents of
-   `reg_alloc_order' before execution of the macro.
-
-   On most machines, it is not necessary to define this macro. */
-/* #define ORDER_REGS_FOR_LOCAL_ALLOC */
-
-
-/* How values fit in registers */
-
-/* A C expression for the number of consecutive hard registers,
-   starting at register number REGNO, required to hold a value of mode
-   MODE. */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)					\
-  ((ACCUM_P (REGNO))							\
-   ? ((GET_MODE_SIZE (MODE) + 4 - 1) / 4)				\
-   : ((GET_MODE_SIZE (MODE) + 2 - 1) / 2))
-
-/* A C expression that is nonzero if it is permissible to store a
-   value of mode MODE in hard register number REGNO (or in several
-   registers starting with that one).  */
-
-extern unsigned char hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
-#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok[ (int)MODE ][ REGNO ]
-
-/* A C expression that is nonzero if it is desirable to choose
-   register allocation so as to avoid move instructions between a
-   value of mode MODE1 and a value of mode MODE2.
-
-   If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
-   MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
-   MODE2)' must be zero. */
-
-extern unsigned char modes_tieable_p[];
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  modes_tieable_p[ (((int)(MODE1)) * (NUM_MACHINE_MODES)) + (int)(MODE2) ]
-
-
-/* Register classes */
-
-/* An enumeral type that must be defined with all the register class
-   names as enumeral values.  `NO_REGS' must be first.  `ALL_REGS'
-   must be the last register class, followed by one more enumeral
-   value, `LIM_REG_CLASSES', which is not a register class but rather
-   tells how many classes there are.
-
-   Each register class has a number, which is the value of casting
-   the class name to type `int'.  The number serves as an index in
-   many of the tables described below.
-
-   All things being equal, the register allocator prefers the higher
-   register class, so put all of the general registers higher than
-   the accumulators and CRs.  */
-
-enum reg_class
-{
-  NO_REGS,
-  REPEAT_REGS,
-  CR_REGS,
-  ACCUM_REGS,
-  F0_REGS,
-  F1_REGS,
-  F_REGS,
-  CARRY_REGS,
-  CC_REGS,
-  ARG0_REGS,
-  ARG1_REGS,
-  ARG2_REGS,
-  ARG3_REGS,
-  RETURN_REGS,
-  EVEN_REGS,
-  GENERAL_REGS,
-  ALL_REGS,
-  LIM_REG_CLASSES
-};
-
-
-/* The number of distinct register classes */
-#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
-
-/* An initializer containing the names of the register classes as C
-   string constants.  These names are used in writing some of the
-   debugging dumps. */
-#define REG_CLASS_NAMES							\
-{									\
-  "NO_REGS",								\
-  "REPEAT_REGS",							\
-  "CR_REGS",								\
-  "ACCUM_REGS",								\
-  "F0_REGS",								\
-  "F1_REGS",								\
-  "F_REGS",								\
-  "CARRY_REGS",								\
-  "CC_REGS",								\
-  "ARG0_REGS",								\
-  "ARG1_REGS",								\
-  "ARG2_REGS",								\
-  "ARG3_REGS",								\
-  "RETURN_REGS",							\
-  "EVEN_REGS",								\
-  "GENERAL_REGS",							\
-  "ALL_REGS"								\
-}
-
-/* An initializer containing the contents of the register classes, as
-   integers which are bit masks.  The Nth integer specifies the
-   contents of class N.  The way the integer MASK is interpreted is
-   that register R is in the class if `MASK & (1 << R)' is 1.
-
-   When the machine has more than 32 registers, an integer does not
-   suffice.  Then the integers are replaced by sub-initializers,
-   braced groupings containing several integers.  Each
-   sub-initializer must be suitable as an initializer for the type
-   `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
-#define REG_CLASS_CONTENTS						\
-{									\
-  { 0x00000000, 0x00000000 },	/* NO_REGS */				\
-  { 0x00800000, 0x00000000 },	/* REPEAT_REGS */			\
-  { 0xffff0000, 0x00000000 },	/* CR_REGS */				\
-  { 0x00000000, 0x00000003 },	/* ACCUM_REGS */			\
-  { 0x00000000, 0x00000008 },	/* F0_REGS */				\
-  { 0x00000000, 0x00000010 },	/* F1_REGS */				\
-  { 0x00000000, 0x00000018 },	/* F_REGS */				\
-  { 0x00000000, 0x00000020 },	/* CARRY_REGS */			\
-  { 0x00000000, 0x00000038 },	/* CC_REGS */				\
-  { 0x00000001, 0x00000000 },	/* ARG0_REGS */				\
-  { 0x00000002, 0x00000000 },	/* ARG1_REGS */				\
-  { 0x00000004, 0x00000000 },	/* ARG2_REGS */				\
-  { 0x00000008, 0x00000000 },	/* ARG3_REGS */				\
-  { 0x00002000, 0x00000000 },	/* R13_REGS */				\
-  { 0x0000ffff, 0x00000000 },	/* EVEN_REGS */				\
-  { 0x0000ffff, 0x00000004 },	/* GENERAL_REGS */			\
-  { 0xffffffff, 0x0000001f },	/* ALL_REGS */				\
-}
-
-/* A C expression whose value is a register class containing hard
-   register REGNO.  In general there is more than one such class;
-   choose a class which is "minimal", meaning that no smaller class
-   also contains the register. */
-
-extern enum reg_class regno_reg_class[];
-#define REGNO_REG_CLASS(REGNO) regno_reg_class[ (REGNO) ]
-
-/* A macro whose definition is the name of the class to which a valid
-   base register must belong.  A base register is one used in an
-   address which is the register value plus a displacement. */
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* A macro whose definition is the name of the class to which a valid
-   index register must belong.  An index register is one used in an
-   address where its value is either multiplied by a scale factor or
-   added to another register (as well as added to a displacement). */
-#define INDEX_REG_CLASS GENERAL_REGS
-
-/* A C expression which defines the machine-dependent operand
-   constraint letters for register classes.  If CHAR is such a
-   letter, the value should be the register class corresponding to
-   it.  Otherwise, the value should be `NO_REGS'.  The register
-   letter `r', corresponding to class `GENERAL_REGS', will not be
-   passed to this macro; you do not need to handle it. */
-
-extern enum reg_class reg_class_from_letter[];
-#define REG_CLASS_FROM_LETTER(CHAR) reg_class_from_letter[ CHAR ]
-
-/* A C expression which is nonzero if register number NUM is suitable
-   for use as a base register in operand addresses.  It may be either
-   a suitable hard register or a pseudo register that has been
-   allocated such a hard register. */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_BASE_P(REGNO)					\
-((REGNO) < FIRST_PSEUDO_REGISTER					\
- ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM			\
- : (reg_renumber[REGNO] >= 0 && GPR_P (reg_renumber[REGNO])))
-
-/* A C expression which is nonzero if register number NUM is suitable
-   for use as an index register in operand addresses.  It may be
-   either a suitable hard register or a pseudo register that has been
-   allocated such a hard register.
-
-   The difference between an index register and a base register is
-   that the index register may be scaled.  If an address involves the
-   sum of two registers, neither one of them scaled, then either one
-   may be labeled the "base" and the other the "index"; but whichever
-   labeling is used must fit the machine's constraints of which
-   registers may serve in each capacity.  The compiler will try both
-   labelings, looking for one that is valid, and will reload one or
-   both registers only if neither labeling works.  */
-#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P (REGNO)
-
-/* A C expression that places additional restrictions on the register
-   class to use when it is necessary to copy value X into a register
-   in class CLASS.  The value is a register class; perhaps CLASS, or
-   perhaps another, smaller class.  On many machines, the following
-   definition is safe:
-
-        #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
-
-   Sometimes returning a more restrictive class makes better code.
-   For example, on the 68000, when X is an integer constant that is
-   in range for a `moveq' instruction, the value of this macro is
-   always `DATA_REGS' as long as CLASS includes the data registers.
-   Requiring a data register guarantees that a `moveq' will be used.
-
-   If X is a `const_double', by returning `NO_REGS' you can force X
-   into a memory constant.  This is useful on certain machines where
-   immediate floating values cannot be loaded into certain kinds of
-   registers. */
-#define PREFERRED_RELOAD_CLASS(X, CLASS) \
-  ((CLASS == EVEN_REGS || CLASS == ACCUM_REGS) ? EVEN_REGS : GENERAL_REGS)
-
-/* Like `PREFERRED_RELOAD_CLASS', but for output reloads instead of
-   input reloads.  If you don't define this macro, the default is to
-   use CLASS, unchanged. */
-/* #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) */
-
-/* A C expression that places additional restrictions on the register
-   class to use when it is necessary to be able to hold a value of
-   mode MODE in a reload register for which class CLASS would
-   ordinarily be used.
-
-   Unlike `PREFERRED_RELOAD_CLASS', this macro should be used when
-   there are certain modes that simply can't go in certain reload
-   classes.
-
-   The value is a register class; perhaps CLASS, or perhaps another,
-   smaller class.
-
-   Don't define this macro unless the target machine has limitations
-   which require the macro to do something nontrivial. */
-/* #define LIMIT_RELOAD_CLASS (MODE, CLASS) */
-
-/* Many machines have some registers that cannot be copied directly
-   to or from memory or even from other types of registers.  An
-   example is the `MQ' register, which on most machines, can only be
-   copied to or from general registers, but not memory.  Some
-   machines allow copying all registers to and from memory, but
-   require a scratch register for stores to some memory locations
-   (e.g., those with symbolic address on the RT, and those with
-   certain symbolic address on the Sparc when compiling PIC).  In
-   some cases, both an intermediate and a scratch register are
-   required.
-
-   You should define these macros to indicate to the reload phase
-   that it may need to allocate at least one register for a reload in
-   addition to the register to contain the data.  Specifically, if
-   copying X to a register CLASS in MODE requires an intermediate
-   register, you should define `SECONDARY_INPUT_RELOAD_CLASS' to
-   return the largest register class all of whose registers can be
-   used as intermediate registers or scratch registers.
-
-   If copying a register CLASS in MODE to X requires an intermediate
-   or scratch register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be
-   defined to return the largest register class required.  If the
-   requirements for input and output reloads are the same, the macro
-   `SECONDARY_RELOAD_CLASS' should be used instead of defining both
-   macros identically.
-
-   The values returned by these macros are often `GENERAL_REGS'.
-   Return `NO_REGS' if no spare register is needed; i.e., if X can be
-   directly copied to or from a register of CLASS in MODE without
-   requiring a scratch register.  Do not define this macro if it
-   would always return `NO_REGS'.
-
-   If a scratch register is required (either with or without an
-   intermediate register), you should define patterns for
-   `reload_inM' or `reload_outM', as required (*note Standard
-   Names::..  These patterns, which will normally be implemented with
-   a `define_expand', should be similar to the `movM' patterns,
-   except that operand 2 is the scratch register.
-
-   Define constraints for the reload register and scratch register
-   that contain a single register class.  If the original reload
-   register (whose class is CLASS) can meet the constraint given in
-   the pattern, the value returned by these macros is used for the
-   class of the scratch register.  Otherwise, two additional reload
-   registers are required.  Their classes are obtained from the
-   constraints in the insn pattern.
-
-   X might be a pseudo-register or a `subreg' of a pseudo-register,
-   which could either be in a hard register or in memory.  Use
-   `true_regnum' to find out; it will return -1 if the pseudo is in
-   memory and the hard register number if it is in a register.
-
-   These macros should not be used in the case where a particular
-   class of registers can only be copied to memory and not to another
-   class of registers.  In that case, secondary reload registers are
-   not needed and would not be helpful.  Instead, a stack location
-   must be used to perform the copy and the `movM' pattern should use
-   memory as a intermediate storage.  This case often occurs between
-   floating-point and general registers. */
-#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X)				\
- ((CLASS) == ACCUM_REGS ? EVEN_REGS					\
-  : ((CLASS) == GENERAL_REGS || (CLASS) == EVEN_REGS) ? NO_REGS		\
-  : GENERAL_REGS)
-
-/* #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) */
-/* #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) */
-
-/* Certain machines have the property that some registers cannot be
-   copied to some other registers without using memory.  Define this
-   macro on those machines to be a C expression that is non-zero if
-   objects of mode M in registers of CLASS1 can only be copied to
-   registers of class CLASS2 by storing a register of CLASS1 into
-   memory and loading that memory location into a register of CLASS2.
-
-   Do not define this macro if its value would always be zero. */
-/* #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, M) */
-
-/* Normally when `SECONDARY_MEMORY_NEEDED' is defined, the compiler
-   allocates a stack slot for a memory location needed for register
-   copies.  If this macro is defined, the compiler instead uses the
-   memory location defined by this macro.
-
-   Do not define this macro if you do not define
-   `SECONDARY_MEMORY_NEEDED'. */
-/* #define SECONDARY_MEMORY_NEEDED_RTX(MODE) */
-
-/* When the compiler needs a secondary memory location to copy
-   between two registers of mode MODE, it normally allocates
-   sufficient memory to hold a quantity of `BITS_PER_WORD' bits and
-   performs the store and load operations in a mode that many bits
-   wide and whose class is the same as that of MODE.
-
-   This is right thing to do on most machines because it ensures that
-   all bits of the register are copied and prevents accesses to the
-   registers in a narrower mode, which some machines prohibit for
-   floating-point registers.
-
-   However, this default behavior is not correct on some machines,
-   such as the DEC Alpha, that store short integers in floating-point
-   registers differently than in integer registers.  On those
-   machines, the default widening will not work correctly and you
-   must define this macro to suppress that widening in some cases.
-   See the file `alpha.h' for details.
-
-   Do not define this macro if you do not define
-   `SECONDARY_MEMORY_NEEDED' or if widening MODE to a mode that is
-   `BITS_PER_WORD' bits wide is correct for your machine. */
-/* #define SECONDARY_MEMORY_NEEDED_MODE(MODE) */
-
-/* Normally the compiler avoids choosing registers that have been
-   explicitly mentioned in the rtl as spill registers (these
-   registers are normally those used to pass parameters and return
-   values).  However, some machines have so few registers of certain
-   classes that there would not be enough registers to use as spill
-   registers if this were done.
-
-   Define `SMALL_REGISTER_CLASSES' on these machines.  When it is
-   defined, the compiler allows registers explicitly used in the rtl
-   to be used as spill registers but avoids extending the lifetime of
-   these registers.
-
-   It is always safe to define this macro, but if you unnecessarily
-   define it, you will reduce the amount of optimizations that can be
-   performed in some cases.  If you do not define this macro when it
-   is required, the compiler will run out of spill registers and
-   print a fatal error message.  For most machines, you should not
-   define this macro. */
-#define SMALL_REGISTER_CLASSES 1
-
-/* A C expression whose value is nonzero if pseudos that have been
-   assigned to registers of class CLASS would likely be spilled
-   because registers of CLASS are needed for spill registers.
-
-   The default value of this macro returns 1 if CLASS has exactly one
-   register and zero otherwise.  On most machines, this default
-   should be used.  Only define this macro to some other expression
-   if pseudo allocated by `local-alloc.c' end up in memory because
-   their hard registers were needed for spill registers.  If this
-   macro returns nonzero for those classes, those pseudos will only
-   be allocated by `global.c', which knows how to reallocate the
-   pseudo to another register.  If there would not be another
-   register available for reallocation, you should not change the
-   definition of this macro since the only effect of such a
-   definition would be to slow down register allocation. */
-/* #define CLASS_LIKELY_SPILLED_P(CLASS) */
-
-/* A C expression for the maximum number of consecutive registers of
-   class CLASS needed to hold a value of mode MODE.
-
-   This is closely related to the macro `HARD_REGNO_NREGS'.  In fact,
-   the value of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be
-   the maximum value of `HARD_REGNO_NREGS (REGNO, MODE)' for all
-   REGNO values in the class CLASS.
-
-   This macro helps control the handling of multiple-word values in
-   the reload pass. */
-#define CLASS_MAX_NREGS(CLASS, MODE)					\
-(((CLASS) == ACCUM_REGS)						\
- ? ((GET_MODE_SIZE (MODE) + 4 - 1) / 4)					\
- : ((GET_MODE_SIZE (MODE) + 2 - 1) / 2))
-
-/* If defined, a C expression for a class that contains registers
-   which the compiler must always access in a mode that is the same
-   size as the mode in which it loaded the register.
-
-   For the example, loading 32-bit integer or floating-point objects
-   into floating-point registers on the Alpha extends them to 64-bits.
-   Therefore loading a 64-bit object and then storing it as a 32-bit
-   object does not store the low-order 32-bits, as would be the case
-   for a normal register.  Therefore, `alpha.h' defines this macro as
-   `FLOAT_REGS'. */
-/* #define CLASS_CANNOT_CHANGE_SIZE */
-
-/* A C expression that defines the machine-dependent operand
-   constraint letters that specify particular ranges of integer
-   values.  If C is one of those letters, the expression should check
-   that VALUE, an integer, is in the appropriate range and return 1
-   if so, 0 otherwise.  If C is not one of those letters, the value
-   should be 0 regardless of VALUE.
-
-   'I' is for 4-bit unsigned constants (imm4), note bit pattern 0 == 16.
-   'J' is for ~ (1 << n), for n <= 15
-   'K' is for 32-bit constants with the lower 8 bits in the range -8..7.
-   'L' is for 4-bit signed constants (imm4).
-   'M' is for 16-bit non-negative constants.
-   'N' is for 4-bit negative unsigned constants (imm4), note bit pattern 0 == 16.
-   'O' is zero.
-   'P' is for (1 << n), where n <= 15.  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)					\
-((C) == 'I'   ? IN_RANGE_P (VALUE, 1, 16)				\
- : (C) == 'J' ? IN_RANGE_P (exact_log2 (~ (VALUE)), 0, 15)		\
- : (C) == 'K' ? IN_RANGE_P (SIGN_EXTEND_SHORT (VALUE), -8, 7)		\
- : (C) == 'L' ? IN_RANGE_P (VALUE, -8, 7)				\
- : (C) == 'M' ? IN_RANGE_P (VALUE, 0, 32767)				\
- : (C) == 'N' ? IN_RANGE_P (VALUE, -16, -1)				\
- : (C) == 'O' ? ((VALUE) == 0)						\
- : (C) == 'P' ? IN_RANGE_P (exact_log2 (VALUE), 0, 15)			\
- : 0)
-
-/* A C expression that defines the machine-dependent operand
-   constraint letters that specify particular ranges of
-   `const_double' values.
-
-   If C is one of those letters, the expression should check that
-   VALUE, an RTX of code `const_double', is in the appropriate range
-   and return 1 if so, 0 otherwise.  If C is not one of those
-   letters, the value should be 0 regardless of VALUE.
-
-   `const_double' is used for all floating-point constants and for
-   `DImode' fixed-point constants.  A given letter can accept either
-   or both kinds of values.  It can use `GET_MODE' to distinguish
-   between these kinds. */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
-((C) == 'G' ? (CONST_DOUBLE_LOW (VALUE) == 0 && CONST_DOUBLE_HIGH (VALUE) == 0) \
- : 0)
-
-/* A C expression that defines the optional machine-dependent
-     constraint letters that can be used to segregate specific types of
-     operands, usually memory references, for the target machine.
-     Normally this macro will not be defined.  If it is required for a
-     particular target machine, it should return 1 if VALUE corresponds
-     to the operand type represented by the constraint letter C.  If C
-     is not defined as an extra constraint, the value returned should
-     be 0 regardless of VALUE.
-
-     'Q' is for memory references that are short.  */
-
-#define EXTRA_CONSTRAINT(VALUE, C)					\
-  ((C) == 'Q'	? short_memory_operand (VALUE, GET_MODE (VALUE))	\
-   :		  0)
-
-
-/* Stack layout */
-
-/* Structure used to define the d10v stack */
-typedef struct d10v_stack {
-  int varargs_p;		/* whether this is a varargs function */
-  int varargs_size;		/* size to hold varargs args passed in regs */
-  int vars_size;		/* variable save area size */
-  int parm_size;		/* outgoing parameter size */
-  int gpr_size;			/* size of saved GPR registers */
-  int accum_size;		/* size of saved ACCUM registers */
-  int total_size;		/* total bytes allocated for stack */
-				/* which registers are to be saved */
-  unsigned char save_p[FIRST_PSEUDO_REGISTER];
-} d10v_stack_t;
-
-/* Define this macro if pushing a word onto the stack moves the stack
-   pointer to a smaller address.
-
-   When we say, "define this macro if ...," it means that the
-   compiler checks this macro only with `#ifdef' so the precise
-   definition used does not matter. */
-
-#define STACK_GROWS_DOWNWARD 1
-
-/* Define this macro if the addresses of local variable slots are at
-   negative offsets from the frame pointer.
-
-   On the D10v, we grow upwards, from the area before the outgoing
-   arguments.  */
-/* #define FRAME_GROWS_DOWNWARD */
-
-/* Define this macro if successive arguments to a function occupy
-   decreasing addresses on the stack. */
-/* #define ARGS_GROW_DOWNWARD */
-
-/* Offset from the frame pointer to the first local variable slot to
-   be allocated.
-
-   If `FRAME_GROWS_DOWNWARD', find the next slot's offset by
-   subtracting the first slot's length from `STARTING_FRAME_OFFSET'.
-   Otherwise, it is found by adding the length of the first slot to
-   the value `STARTING_FRAME_OFFSET'.
-
-   On the D10V, the frame pointer is the same as the stack pointer,
-   except for dynamic allocations.  So we start after the outgoing
-   parameter area.  */
-
-#define STARTING_FRAME_OFFSET						\
-  (D10V_ALIGN (current_function_outgoing_args_size, 2))
-
-/* Offset from the stack pointer register to the first location at
-   which outgoing arguments are placed.  If not specified, the
-   default value of zero is used.  This is the proper value for most
-   machines.
-
-   If `ARGS_GROW_DOWNWARD', this is the offset to the location above
-   the first location at which outgoing arguments are placed. */
-/* #define STACK_POINTER_OFFSET */
-
-/* Offset from the argument pointer register to the first argument's
-   address.  On some machines it may depend on the data type of the
-   function.
-
-   If `ARGS_GROW_DOWNWARD', this is the offset to the location above
-   the first argument's address. */
-#define FIRST_PARM_OFFSET(FUNDECL) 0
-
-/* Offset from the stack pointer register to an item dynamically
-   allocated on the stack, e.g., by `alloca'.
-
-   The default value for this macro is `STACK_POINTER_OFFSET' plus the
-   length of the outgoing arguments.  The default is correct for most
-   machines.  See `function.c' for details. */
-/* #define STACK_DYNAMIC_OFFSET (FUNDECL) */
-
-/* A C expression whose value is RTL representing the address in a
-   stack frame where the pointer to the caller's frame is stored.
-   Assume that FRAMEADDR is an RTL expression for the address of the
-   stack frame itself.
-
-   If you don't define this macro, the default is to return the value
-   of FRAMEADDR--that is, the stack frame address is also the address
-   of the stack word that points to the previous frame. */
-/* #define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR) */
-
-/* If defined, a C expression that produces the machine-specific code
-   to setup the stack so that arbitrary frames can be accessed.  For
-   example, on the Sparc, we must flush all of the register windows
-   to the stack before we can access arbitrary stack frames.  This
-   macro will seldom need to be defined. */
-/* #define SETUP_FRAME_ADDRESSES() */
-
-/* A C expression whose value is RTL representing the value of the
-   return address for the frame COUNT steps up from the current frame.
-   FRAMEADDR is the frame pointer of the COUNT frame, or the frame
-   pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
-   is defined. */
-/* #define RETURN_ADDR_RTX (COUNT, FRAMEADDR) */
-
-/* Define this if the return address of a particular stack frame is
-   accessed from the frame pointer of the previous stack frame. */
-/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
-
-
-/* Stack based registers */
-
-/* The register number of the stack pointer register, which must also
-   be a fixed register according to `FIXED_REGISTERS'.  On most
-   machines, the hardware determines which register this is. */
-#define STACK_POINTER_REGNUM (GPR_FIRST + 15)
-
-/* The register number of the frame pointer register, which is used to
-   access automatic variables in the stack frame.  On some machines,
-   the hardware determines which register this is.  On other
-   machines, you can choose any register you wish for this purpose. */
-#define FRAME_POINTER_REGNUM (GPR_FIRST + 11)
-
-/* On some machines the offset between the frame pointer and starting
-   offset of the automatic variables is not known until after register
-   allocation has been done (for example, because the saved registers
-   are between these two locations).  On those machines, define
-   `FRAME_POINTER_REGNUM' the number of a special, fixed register to
-   be used internally until the offset is known, and define
-   `HARD_FRAME_POINTER_REGNUM' to be actual the hard register number
-   used for the frame pointer.
-
-   You should define this macro only in the very rare circumstances
-   when it is not possible to calculate the offset between the frame
-   pointer and the automatic variables until after register
-   allocation has been completed.  When this macro is defined, you
-   must also indicate in your definition of `ELIMINABLE_REGS' how to
-   eliminate `FRAME_POINTER_REGNUM' into either
-   `HARD_FRAME_POINTER_REGNUM' or `STACK_POINTER_REGNUM'.
-
-   Do not define this macro if it would be the same as
-   `FRAME_POINTER_REGNUM'. */
-/* #define HARD_FRAME_POINTER_REGNUM */
-
-/* The register number of the arg pointer register, which is used to
-   access the function's argument list.  On some machines, this is
-   the same as the frame pointer register.  On some machines, the
-   hardware determines which register this is.  On other machines,
-   you can choose any register you wish for this purpose.  If this is
-   not the same register as the frame pointer register, then you must
-   mark it as a fixed register according to `FIXED_REGISTERS', or
-   arrange to be able to eliminate it (*note Elimination::.). */
-#define ARG_POINTER_REGNUM AP_FIRST
-
-/* The register number of the return address pointer register, which
-   is used to access the current function's return address from the
-   stack.  On some machines, the return address is not at a fixed
-   offset from the frame pointer or stack pointer or argument
-   pointer.  This register can be defined to point to the return
-   address on the stack, and then be converted by `ELIMINABLE_REGS'
-   into either the frame pointer or stack pointer.
-
-   Do not define this macro unless there is no other way to get the
-   return address from the stack. */
-/* #define RETURN_ADDRESS_POINTER_REGNUM */
-
-/* Register numbers used for passing a function's static chain
-   pointer.
-
-   The static chain register need not be a fixed register.
-
-   If the static chain is passed in memory, these macros should not be
-   defined; instead, the next two macros should be defined. */
-#define STATIC_CHAIN_REGNUM (GPR_FIRST + 4)
-
-/* If the static chain is passed in memory, these macros provide rtx
-   giving `mem' expressions that denote where they are stored.
-   `STATIC_CHAIN' and `STATIC_CHAIN_INCOMING' give the locations as
-   seen by the calling and called functions, respectively.  Often the
-   former will be at an offset from the stack pointer and the latter
-   at an offset from the frame pointer.
-
-   The variables `stack_pointer_rtx', `frame_pointer_rtx', and
-   `arg_pointer_rtx' will have been initialized prior to the use of
-   these macros and should be used to refer to those items.
-
-   If the static chain is passed in a register, the two previous
-   macros should be defined instead. */
-/* #define STATIC_CHAIN_INCOMING */
-/* #define STATIC_CHAIN */
-
-/* Local d10v return link register number */
-#define RETURN_ADDRESS_REGNUM (GPR_FIRST + 13)
-
-
-/* Eliminating the frame and arg pointers */
-
-/* A C expression which is nonzero if a function must have and use a
-   frame pointer.  This expression is evaluated  in the reload pass.
-   If its value is nonzero the function will have a frame pointer.
-
-   The expression can in principle examine the current function and
-   decide according to the facts, but on most machines the constant 0
-   or the constant 1 suffices.  Use 0 when the machine allows code to
-   be generated with no frame pointer, and doing so saves some time
-   or space.  Use 1 when there is no possible advantage to avoiding a
-   frame pointer.
-
-   In certain cases, the compiler does not know how to produce valid
-   code without a frame pointer.  The compiler recognizes those cases
-   and automatically gives the function a frame pointer regardless of
-   what `FRAME_POINTER_REQUIRED' says.  You don't need to worry about
-   them.
-
-   In a function that does not require a frame pointer, the frame
-   pointer register can be allocated for ordinary usage, unless you
-   mark it as a fixed register.  See `FIXED_REGISTERS' for more
-   information. */
-#define FRAME_POINTER_REQUIRED 0
-
-/* A C statement to store in the variable DEPTH-VAR the difference
-   between the frame pointer and the stack pointer values immediately
-   after the function prologue.  The value would be computed from
-   information such as the result of `get_frame_size ()' and the
-   tables of registers `regs_ever_live' and `call_used_regs'.
-
-   If `ELIMINABLE_REGS' is defined, this macro will be not be used and
-   need not be defined.  Otherwise, it must be defined even if
-   `FRAME_POINTER_REQUIRED' is defined to always be true; in that
-   case, you may set DEPTH-VAR to anything. */
-/* #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) */
-
-/* If defined, this macro specifies a table of register pairs used to
-   eliminate unneeded registers that point into the stack frame.  If
-   it is not defined, the only elimination attempted by the compiler
-   is to replace references to the frame pointer with references to
-   the stack pointer.
-
-   The definition of this macro is a list of structure
-   initializations, each of which specifies an original and
-   replacement register.
-
-   On some machines, the position of the argument pointer is not
-   known until the compilation is completed.  In such a case, a
-   separate hard register must be used for the argument pointer.
-   This register can be eliminated by replacing it with either the
-   frame pointer or the argument pointer, depending on whether or not
-   the frame pointer has been eliminated.
-
-   In this case, you might specify:
-        #define ELIMINABLE_REGS  \
-        {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
-         {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
-         {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
-
-   Note that the elimination of the argument pointer with the stack
-   pointer is specified first since that is the preferred elimination. */
-
-#define ELIMINABLE_REGS							\
-{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },			\
- { ARG_POINTER_REGNUM,	 STACK_POINTER_REGNUM },			\
- { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM }}			\
-
-/* A C expression that returns non-zero if the compiler is allowed to
-   try to replace register number FROM-REG with register number
-   TO-REG.  This macro need only be defined if `ELIMINABLE_REGS' is
-   defined, and will usually be the constant 1, since most of the
-   cases preventing register elimination are things that the compiler
-   already knows about. */
-
-#define CAN_ELIMINATE(FROM, TO)						\
- ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM		\
-  ? ! frame_pointer_needed						\
-  : 1)
-
-/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'.  It
-   specifies the initial difference between the specified pair of
-   registers.  This macro must be defined if `ELIMINABLE_REGS' is
-   defined. */
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
-{									\
-  d10v_stack_t *info = d10v_stack_info ();				\
-									\
- if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	\
-   (OFFSET) = 0;							\
- else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)	\
-   (OFFSET) = info->total_size;						\
- else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	\
-   (OFFSET) = info->total_size;						\
-  else									\
-    abort ();								\
-}
-
-
-/* Define this macro if the `longjmp' function restores registers from
-   the stack frames, rather than from those saved specifically by
-   `setjmp'.  Certain quantities must not be kept in registers across
-   a call to `setjmp' on such machines. */
-/* #define LONGJMP_RESTORE_FROM_STACK */
-
-
-/* Passing arguments */
-
-/* Define this macro if an argument declared in a prototype as an
-   integral type smaller than `int' should actually be passed as an
-   `int'.  In addition to avoiding errors in certain cases of
-   mismatch, it also makes for better code on certain machines. */
-/* #define PROMOTE_PROTOTYPES */
-
-/* A C expression that is the number of bytes actually pushed onto the
-   stack when an instruction attempts to push NPUSHED bytes.
-
-   If the target machine does not have a push instruction, do not
-   define this macro.  That directs GNU CC to use an alternate
-   strategy: to allocate the entire argument block and then store the
-   arguments into it.
-
-   On some machines, the definition
-
-        #define PUSH_ROUNDING(BYTES) (BYTES)
-
-   will suffice.  But on other machines, instructions that appear to
-   push one byte actually push two bytes in an attempt to maintain
-   alignment.  Then the definition should be
-
-        #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) */
-/* #define PUSH_ROUNDING(NPUSHED) */
-
-/* If defined, the maximum amount of space required for outgoing
-   arguments will be computed and placed into the variable
-   `current_function_outgoing_args_size'.  No space will be pushed
-   onto the stack for each call; instead, the function prologue should
-   increase the stack frame size by this amount.
-
-   Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is
-   not proper. */
-#define ACCUMULATE_OUTGOING_ARGS 1
-
-/* Define this macro if functions should assume that stack space has
-   been allocated for arguments even when their values are passed in
-   registers.
-
-   The value of this macro is the size, in bytes, of the area
-   reserved for arguments passed in registers for the function
-   represented by FNDECL.
-
-   This space can be allocated by the caller, or be a part of the
-   machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
-   which. */
-/* Currently, emit_library_call(,_value} always think that a definition of
-   REG_PARM_STACK_SPACE means that all register values need stack space,
-   so defining it to always 0 doesn't work; e.g. ashldi3 is affected.  */
-/* #define REG_PARM_STACK_SPACE(FNDECL) 0 */
-
-/* Define these macros in addition to the one above if functions might
-   allocate stack space for arguments even when their values are
-   passed in registers.  These should be used when the stack space
-   allocated for arguments in registers is not a simple constant
-   independent of the function declaration.
-
-   The value of the first macro is the size, in bytes, of the area
-   that we should initially assume would be reserved for arguments
-   passed in registers.
-
-   The value of the second macro is the actual size, in bytes, of the
-   area that will be reserved for arguments passed in registers.
-   This takes two arguments: an integer representing the number of
-   bytes of fixed sized arguments on the stack, and a tree
-   representing the number of bytes of variable sized arguments on
-   the stack.
-
-   When these macros are defined, `REG_PARM_STACK_SPACE' will only be
-   called for libcall functions, the current function, or for a
-   function being called when it is known that such stack space must
-   be allocated.  In each case this value can be easily computed.
-
-   When deciding whether a called function needs such stack space,
-   and how much space to reserve, GNU CC uses these two macros
-   instead of `REG_PARM_STACK_SPACE'. */
-/* #define MAYBE_REG_PARM_STACK_SPACE */
-/* #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) */
-
-/* Define this if it is the responsibility of the caller to allocate
-   the area reserved for arguments passed in registers.
-
-   If `ACCUMULATE_OUTGOING_ARGS' is defined, this macro controls
-   whether the space for these arguments counts in the value of
-   `current_function_outgoing_args_size'. */
-#define OUTGOING_REG_PARM_STACK_SPACE 1
-
-/* Define this macro if `REG_PARM_STACK_SPACE' is defined, but the
-   stack parameters don't skip the area specified by it.
-
-   Normally, when a parameter is not passed in registers, it is
-   placed on the stack beyond the `REG_PARM_STACK_SPACE' area.
-   Defining this macro suppresses this behavior and causes the
-   parameter to be passed on the stack in its natural location. */
-/* #define STACK_PARMS_IN_REG_PARM_AREA */
-
-/* A C expression that should indicate the number of bytes of its own
-   arguments that a function pops on returning, or 0 if the function
-   pops no arguments and the caller must therefore pop them all after
-   the function returns.
-
-   FUNDECL is a C variable whose value is a tree node that describes
-   the function in question.  Normally it is a node of type
-   `FUNCTION_DECL' that describes the declaration of the function.
-   From this it is possible to obtain the DECL_MACHINE_ATTRIBUTES of
-   the function.
-
-   FUNTYPE is a C variable whose value is a tree node that describes
-   the function in question.  Normally it is a node of type
-   `FUNCTION_TYPE' that describes the data type of the function.
-   From this it is possible to obtain the data types of the value and
-   arguments (if known).
-
-   When a call to a library function is being considered, FUNTYPE
-   will contain an identifier node for the library function.  Thus, if
-   you need to distinguish among various library functions, you can
-   do so by their names.  Note that "library function" in this
-   context means a function used to perform arithmetic, whose name is
-   known specially in the compiler and was not mentioned in the C
-   code being compiled.
-
-   STACK-SIZE is the number of bytes of arguments passed on the
-   stack.  If a variable number of bytes is passed, it is zero, and
-   argument popping will always be the responsibility of the calling
-   function.
-
-   On the Vax, all functions always pop their arguments, so the
-   definition of this macro is STACK-SIZE.  On the 68000, using the
-   standard calling convention, no functions pop their arguments, so
-   the value of the macro is always 0 in this case.  But an
-   alternative calling convention is available in which functions
-   that take a fixed number of arguments pop them but other functions
-   (such as `printf') pop nothing (the caller pops all).  When this
-   convention is in use, FUNTYPE is examined to determine whether a
-   function takes a fixed number of arguments. */
-#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACKSIZE) 0
-
-
-/* Function arguments */
-
-/* Nonzero if we do not know how to pass TYPE solely in registers.
-   Values that come in registers with inconvenient padding are stored
-   to memory at the function start.  */
-
-#define MUST_PASS_IN_STACK(MODE,TYPE)			\
-  ((TYPE) != 0						\
-   && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST	\
-       || TREE_ADDRESSABLE (TYPE)))
-
-/* A C expression that controls whether a function argument is passed
-   in a register, and which register.
-
-   The arguments are CUM, which summarizes all the previous
-   arguments; MODE, the machine mode of the argument; TYPE, the data
-   type of the argument as a tree node or 0 if that is not known
-   (which happens for C support library functions); and NAMED, which
-   is 1 for an ordinary argument and 0 for nameless arguments that
-   correspond to `...' in the called function's prototype.
-
-   The value of the expression should either be a `reg' RTX for the
-   hard register in which to pass the argument, or zero to pass the
-   argument on the stack.
-
-   For machines like the Vax and 68000, where normally all arguments
-   are pushed, zero suffices as a definition.
-
-   The usual way to make the ANSI library `stdarg.h' work on a machine
-   where some arguments are usually passed in registers, is to cause
-   nameless arguments to be passed on the stack instead.  This is done
-   by making `FUNCTION_ARG' return 0 whenever NAMED is 0.
-
-   You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the
-   definition of this macro to determine if this argument is of a
-   type that must be passed in the stack.  If `REG_PARM_STACK_SPACE'
-   is not defined and `FUNCTION_ARG' returns non-zero for such an
-   argument, the compiler will abort.  If `REG_PARM_STACK_SPACE' is
-   defined, the argument will be computed in the stack and then
-   loaded into a register. */
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  function_arg(&CUM, MODE, TYPE, NAMED)
-
-/* Define this macro if the target machine has "register windows", so
-   that the register in which a function sees an arguments is not
-   necessarily the same as the one in which the caller passed the
-   argument.
-
-   For such machines, `FUNCTION_ARG' computes the register in which
-   the caller passes the value, and `FUNCTION_INCOMING_ARG' should be
-   defined in a similar fashion to tell the function being called
-   where the arguments will arrive.
-
-   If `FUNCTION_INCOMING_ARG' is not defined, `FUNCTION_ARG' serves
-   both purposes. */
-/* #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) */
-
-/* A C expression for the number of words, at the beginning of an
-   argument, must be put in registers.  The value must be zero for
-   arguments that are passed entirely in registers or that are
-   entirely pushed on the stack.
-
-   On some machines, certain arguments must be passed partially in
-   registers and partially in memory.  On these machines, typically
-   the first N words of arguments are passed in registers, and the
-   rest on the stack.  If a multi-word argument (a `double' or a
-   structure) crosses that boundary, its first few words must be
-   passed in registers and the rest must be pushed.  This macro tells
-   the compiler when this occurs, and how many of the words should go
-   in registers.
-
-   `FUNCTION_ARG' for these arguments should return the first
-   register to be used by the caller for this argument; likewise
-   `FUNCTION_INCOMING_ARG', for the called function. */
-/* #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) */
-
-/* If defined, a C expression that indicates when it is the called
-   function's responsibility to make a copy of arguments passed by
-   invisible reference.  Normally, the caller makes a copy and passes
-   the address of the copy to the routine being called.  When
-   FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller
-   does not make a copy.  Instead, it passes a pointer to the "live"
-   value.  The called function must not modify this value.  If it can
-   be determined that the value won't be modified, it need not make a
-   copy; otherwise a copy must be made. */
-#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
-  function_arg_callee_copies(&CUM, MODE, TYPE, NAMED)
-
-/* If defined, a C expression that indicates whether items passed by
-   reference should be kept as a reference, or should be allocated to
-   a pseudo register.  */
-#define FUNCTION_ARG_KEEP_AS_REFERENCE(CUM, MODE, TYPE, NAMED) 1
-
-/* A C type for declaring a variable that is used as the first
-   argument of `FUNCTION_ARG' and other related values.  For some
-   target machines, the type `int' suffices and can hold the number
-   of bytes of argument so far.
-
-   There is no need to record in `CUMULATIVE_ARGS' anything about the
-   arguments that have been passed on the stack.  The compiler has
-   other variables to keep track of that.  For target machines on
-   which all arguments are passed on the stack, there is no need to
-   store anything in `CUMULATIVE_ARGS'; however, the data structure
-   must exist and should not be empty, so use `int'. */
-typedef struct { int reg, stack; } d10v_cumulative_args;
-#define CUMULATIVE_ARGS d10v_cumulative_args
-
-/* A C statement (sans semicolon) for initializing the variable CUM
-   for the state at the beginning of the argument list.  The variable
-   has type `CUMULATIVE_ARGS'.  The value of FNTYPE is the tree node
-   for the data type of the function which will receive the args, or 0
-   if the args are to a compiler support library function.  The value
-   of INDIRECT is nonzero when processing an indirect call, for
-   example a call through a function pointer.  The value of INDIRECT
-   is zero for a call to an explicitly named function, a library
-   function call, or when `INIT_CUMULATIVE_ARGS' is used to find
-   arguments for the function being compiled.
-
-   When processing a call to a compiler support library function,
-   LIBNAME identifies which one.  It is a `symbol_ref' rtx which
-   contains the name of the function, as a string.  LIBNAME is 0 when
-   an ordinary C function call is being processed.  Thus, each time
-   this macro is called, either LIBNAME or FNTYPE is nonzero, but
-   never both of them at once. */
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
-  init_cumulative_args (&CUM, FNTYPE, LIBNAME, INDIRECT, FALSE)
-
-/* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of
-   finding the arguments for the function being compiled.  If this
-   macro is undefined, `INIT_CUMULATIVE_ARGS' is used instead.
-
-   The value passed for LIBNAME is always 0, since library routines
-   with special calling conventions are never compiled with GNU CC.
-   The argument LIBNAME exists for symmetry with
-   `INIT_CUMULATIVE_ARGS'. */
-#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
-  init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, TRUE)
-
-/* A C statement (sans semicolon) to update the summarizer variable
-   CUM to advance past an argument in the argument list.  The values
-   MODE, TYPE and NAMED describe that argument.  Once this is done,
-   the variable CUM is suitable for analyzing the *following*
-   argument with `FUNCTION_ARG', etc.
-
-   This macro need not do anything if the argument in question was
-   passed on the stack.  The compiler knows how to track the amount
-   of stack space used for arguments without any special help. */
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
-  function_arg_advance (&CUM, MODE, TYPE, NAMED)
-
-/* If defined, a C expression which determines whether, and in which
-   direction, to pad out an argument with extra space.  The value
-   should be of type `enum direction': either `upward' to pad above
-   the argument, `downward' to pad below, or `none' to inhibit
-   padding.
-
-   The *amount* of padding is always just enough to reach the next
-   multiple of `FUNCTION_ARG_BOUNDARY'; this macro does not control
-   it.
-
-   This macro has a default definition which is right for most
-   systems.  For little-endian machines, the default is to pad
-   upward.  For big-endian machines, the default is to pad downward
-   for an argument of constant size shorter than an `int', and upward
-   otherwise. */
-/* #define FUNCTION_ARG_PADDING(MODE, TYPE) */
-
-/* If defined, a C expression that gives the alignment boundary, in
-   bits, of an argument with the specified mode and type.  If it is
-   not defined, `PARM_BOUNDARY' is used for all arguments. */
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
-  function_arg_boundary (MODE, TYPE)
-
-/* A C expression that is nonzero if REGNO is the number of a hard
-   register in which function arguments are sometimes passed.  This
-   does *not* include implicit arguments such as the static chain and
-   the structure-value address.  On many machines, no registers can be
-   used for this purpose since all function arguments are pushed on
-   the stack. */
-#define FUNCTION_ARG_REGNO_P(REGNO) IN_RANGE_P (REGNO, ARG_FIRST, ARG_LAST)
-
-
-/* How values are returned */
-
-/* Define this macro if `-traditional' should not cause functions
-   declared to return `float' to convert the value to `double'. */
-/* #define TRADITIONAL_RETURN_FLOAT */
-
-/* A C expression to create an RTX representing the place where a
-   function returns a value of data type VALTYPE.  VALTYPE is a tree
-   node representing a data type.  Write `TYPE_MODE (VALTYPE)' to get
-   the machine mode used to represent that type.  On many machines,
-   only the mode is relevant.  (Actually, on most machines, scalar
-   values are returned in the same place regardless of mode).
-
-   If `PROMOTE_FUNCTION_RETURN' is defined, you must apply the same
-   promotion rules specified in `PROMOTE_MODE' if VALTYPE is a scalar
-   type.
-
-   If the precise function being called is known, FUNC is a tree node
-   (`FUNCTION_DECL') for it; otherwise, FUNC is a null pointer.  This
-   makes it possible to use a different value-returning convention
-   for specific functions when all their calls are known.
-
-   `FUNCTION_VALUE' is not used for return vales with aggregate data
-   types, because these are returned in another way.  See
-   `STRUCT_VALUE_REGNUM' and related macros, below. */
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), RETURN_REGNUM)
-
-/* Define this macro if the target machine has "register windows" so
-   that the register in which a function returns its value is not the
-   same as the one in which the caller sees the value.
-
-   For such machines, `FUNCTION_VALUE' computes the register in which
-   the caller will see the value.  `FUNCTION_OUTGOING_VALUE' should be
-   defined in a similar fashion to tell the function where to put the
-   value.
-
-   If `FUNCTION_OUTGOING_VALUE' is not defined, `FUNCTION_VALUE'
-   serves both purposes.
-
-   `FUNCTION_OUTGOING_VALUE' is not used for return vales with
-   aggregate data types, because these are returned in another way.
-   See `STRUCT_VALUE_REGNUM' and related macros, below. */
-/* #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) */
-
-/* A C expression to create an RTX representing the place where a
-   library function returns a value of mode MODE.  If the precise
-   function being called is known, FUNC is a tree node
-   (`FUNCTION_DECL') for it; otherwise, FUNC is a null pointer.  This
-   makes it possible to use a different value-returning convention
-   for specific functions when all their calls are known.
-
-   Note that "library function" in this context means a compiler
-   support routine, used to perform arithmetic, whose name is known
-   specially by the compiler and was not mentioned in the C code being
-   compiled.
-
-   The definition of `LIBRARY_VALUE' need not be concerned aggregate
-   data types, because none of the library functions returns such
-   types. */
-
-#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, RETURN_REGNUM)
-
-/* A C expression that is nonzero if REGNO is the number of a hard
-   register in which the values of called function may come back.
-
-   A register whose use for returning values is limited to serving as
-   the second of a pair (for a value of type `double', say) need not
-   be recognized by this macro.  So for most machines, this definition
-   suffices:
-
-        #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-   If the machine has register windows, so that the caller and the
-   called function use different registers for the return value, this
-   macro should recognize only the caller's register numbers. */
-#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == RETURN_REGNUM)
-
-/* Define this macro if `untyped_call' and `untyped_return' need more
-   space than is implied by `FUNCTION_VALUE_REGNO_P' for saving and
-   restoring an arbitrary return value. */
-/* #define APPLY_RESULT_SIZE */
-
-/* A C expression which can inhibit the returning of certain function
-   values in registers, based on the type of value.  A nonzero value
-   says to return the function value in memory, just as large
-   structures are always returned.  Here TYPE will be a C expression
-   of type `tree', representing the data type of the value.
-
-   Note that values of mode `BLKmode' must be explicitly handled by
-   this macro.  Also, the option `-fpcc-struct-return' takes effect
-   regardless of this macro.  On most systems, it is possible to
-   leave the macro undefined; this causes a default definition to be
-   used, whose value is the constant 1 for `BLKmode' values, and 0
-   otherwise.
-
-   Do not use this macro to indicate that structures and unions
-   should always be returned in memory.  You should instead use
-   `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
-/* #define RETURN_IN_MEMORY(TYPE) */
-
-/* Define this macro to be 1 if all structure and union return values
-   must be in memory.  Since this results in slower code, this should
-   be defined only if needed for compatibility with other compilers
-   or with an ABI.  If you define this macro to be 0, then the
-   conventions used for structure and union return values are decided
-   by the `RETURN_IN_MEMORY' macro.
-
-   If not defined, this defaults to the value 1. */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* If the structure value address is passed in a register, then
-   `STRUCT_VALUE_REGNUM' should be the number of that register. */
-#define STRUCT_VALUE_REGNUM (GPR_FIRST + 2)
-
-/* If the structure value address is not passed in a register, define
-   `STRUCT_VALUE' as an expression returning an RTX for the place
-   where the address is passed.  If it returns 0, the address is
-   passed as an "invisible" first argument. */
-#define STRUCT_VALUE 0
-
-/* On some architectures the place where the structure value address
-   is found by the called function is not the same place that the
-   caller put it.  This can be due to register windows, or it could
-   be because the function prologue moves it to a different place.
-
-   If the incoming location of the structure value address is in a
-   register, define this macro as the register number. */
-/* #define STRUCT_VALUE_INCOMING_REGNUM */
-
-/* If the incoming location is not a register, then you should define
-   `STRUCT_VALUE_INCOMING' as an expression for an RTX for where the
-   called function should find the value.  If it should find the
-   value on the stack, define this to create a `mem' which refers to
-   the frame pointer.  A definition of 0 means that the address is
-   passed as an "invisible" first argument. */
-/* #define STRUCT_VALUE_INCOMING */
-
-/* Define this macro if the usual system convention on the target
-   machine for returning structures and unions is for the called
-   function to return the address of a static variable containing the
-   value.
-
-   Do not define this if the usual system convention is for the
-   caller to pass an address to the subroutine.
-
-   This macro has effect in `-fpcc-struct-return' mode, but it does
-   nothing when you use `-freg-struct-return' mode. */
-/* #define PCC_STATIC_STRUCT_RETURN */
-
-
-/* Caller saves */
-
-/* Define this macro if function calls on the target machine do not
-   preserve any registers; in other words, if `CALL_USED_REGISTERS'
-   has 1 for all registers.  This macro enables `-fcaller-saves' by
-   default.  Eventually that option will be enabled by default on all
-   machines and both the option and this macro will be eliminated. */
-/* #define DEFAULT_CALLER_SAVES */
-
-/* A C expression to determine whether it is worthwhile to consider
-     placing a pseudo-register in a call-clobbered hard register and
-     saving and restoring it around each function call.  The expression
-     should be 1 when this is worth doing, and 0 otherwise.
-
-     If you don't define this macro, a default is used which is good on
-     most machines: `4 * CALLS < REFS'.  */
-/* #define CALLER_SAVE_PROFITABLE (REFS, CALLS) */
-
-
-/* Prologues and epilogues */
-
-/* A C compound statement that outputs the assembler code for entry
-   to a function.  The prologue is responsible for setting up the
-   stack frame, initializing the frame pointer register, saving
-   registers that must be saved, and allocating SIZE additional bytes
-   of storage for the local variables.  SIZE is an integer.  FILE is
-   a stdio stream to which the assembler code should be output. */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue (FILE, SIZE)
-
-/* Define this macro as a C expression that is nonzero if the return
-   instruction or the function epilogue ignores the value of the stack
-   pointer; in other words, if it is safe to delete an instruction to
-   adjust the stack pointer before a return from the function.
-
-   Note that this macro's value is relevant only for functions for
-   which frame pointers are maintained.  It is never safe to delete a
-   final stack adjustment in a function that has no frame pointer,
-   and the compiler knows this regardless of `EXIT_IGNORE_STACK'. */
-/* #define EXIT_IGNORE_STACK */
-
-/* A C compound statement that outputs the assembler code for exit
-   from a function.  The epilogue is responsible for restoring the
-   saved registers and stack pointer to their values when the
-   function was called, and returning control to the caller.  This
-   macro takes the same arguments as the macro `FUNCTION_PROLOGUE',
-   and the registers to restore are determined from `regs_ever_live'
-   and `CALL_USED_REGISTERS' in the same way. */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue (FILE, SIZE)
-
-/* Define this macro if the function epilogue contains delay slots to
-   which instructions from the rest of the function can be "moved".
-   The definition should be a C expression whose value is an integer
-   representing the number of delay slots there. */
-/* #define DELAY_SLOTS_FOR_EPILOGUE */
-
-/* A C expression that returns 1 if INSN can be placed in delay slot
-   number N of the epilogue.
-
-   The argument N is an integer which identifies the delay slot now
-   being considered (since different slots may have different rules of
-   eligibility).  It is never negative and is always less than the
-   number of epilogue delay slots (what `DELAY_SLOTS_FOR_EPILOGUE'
-   returns).  If you reject a particular insn for a given delay slot,
-   in principle, it may be reconsidered for a subsequent delay slot.
-   Also, other insns may (at least in principle) be considered for
-   the so far unfilled delay slot.
-
-   The insns accepted to fill the epilogue delay slots are put in an
-   RTL list made with `insn_list' objects, stored in the variable
-   `current_function_epilogue_delay_list'.  The insn for the first
-   delay slot comes first in the list.  Your definition of the macro
-   `FUNCTION_EPILOGUE' should fill the delay slots by outputting the
-   insns in this list, usually by calling `final_scan_insn'.
-
-   You need not define this macro if you did not define
-   `DELAY_SLOTS_FOR_EPILOGUE'. */
-/* #define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN, N) */
-
-/* A C compound statement that outputs the assembler code for a thunk
-   function, used to implement C++ virtual function calls with
-   multiple inheritance.  The thunk acts as a wrapper around a
-   virtual function, adjusting the implicit object parameter before
-   handing control off to the real function.
-
-   First, emit code to add the integer DELTA to the location that
-   contains the incoming first argument.  Assume that this argument
-   contains a pointer, and is the one used to pass the `this' pointer
-   in C++.  This is the incoming argument *before* the function
-   prologue, e.g. `%o0' on a sparc.  The addition must preserve the
-   values of all other incoming arguments.
-
-   After the addition, emit code to jump to FUNCTION, which is a
-   `FUNCTION_DECL'.  This is a direct pure jump, not a call, and does
-   not touch the return address.  Hence returning from FUNCTION will
-   return to whoever called the current `thunk'.
-
-   The effect must be as if FUNCTION had been called directly with
-   the adjusted first argument.  This macro is responsible for
-   emitting all of the code for a thunk function; `FUNCTION_PROLOGUE'
-   and `FUNCTION_EPILOGUE' are not invoked.
-
-   The THUNK_FNDECL is redundant.  (DELTA and FUNCTION have already
-   been extracted from it.)  It might possibly be useful on some
-   targets, but probably not.
-
-   For many targets, the target-independent code in the C++ frontend
-   will be sufficient and you can leave this macro undefined.  You
-   need to define this macro if the code generated by default would
-   clobber any of the incoming arguments; this is only likely if
-   parameters can be passed in registers.  You should also define
-   this macro if the default code is sub-optimal. */
-/* #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) */
-
-
-/* Profiling */
-
-/* A C statement or compound statement to output to FILE some
-   assembler code to call the profiling subroutine `mcount'.  Before
-   calling, the assembler code must load the address of a counter
-   variable into a register where `mcount' expects to find the
-   address.  The name of this variable is `LP' followed by the number
-   LABELNO, so you would generate the name using `LP%d' in a
-   `fprintf'.
-
-   The details of how the address should be passed to `mcount' are
-   determined by your operating system environment, not by GNU CC.  To
-   figure them out, compile a small program for profiling using the
-   system's installed C compiler and look at the assembler code that
-   results. */
-#define FUNCTION_PROFILER(FILE, LABELNO) abort ()
-
-/* Define this macro if the code for function profiling should come
-   before the function prologue.  Normally, the profiling code comes
-   after. */
-/* #define PROFILE_BEFORE_PROLOGUE */
-
-/* A C statement or compound statement to output to FILE some
-   assembler code to initialize basic-block profiling for the current
-   object module.  The global compile flag `profile_block_flag'
-   distingishes two profile modes.
-
-  `profile_block_flag != 2'
-        Output code to call the subroutine `__bb_init_func' once per
-        object module, passing it as its sole argument the address of
-        a block allocated in the object module.
-
-        The name of the block is a local symbol made with this
-        statement:
-
-             ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
-
-        Of course, since you are writing the definition of
-        `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro,
-        you can take a short cut in the definition of this macro and
-        use the name that you know will result.
-
-        The first word of this block is a flag which will be nonzero
-        if the object module has already been initialized.  So test
-        this word first, and do not call `__bb_init_func' if the flag
-        is nonzero.  BLOCK_OR_LABEL contains a unique number which
-        may be used to generate a label as a branch destination when
-        `__bb_init_func' will not be called.
-
-        Described in assembler language, the code to be output looks
-        like:
-
-               cmp (LPBX0),0
-               bne local_label
-               parameter1 <- LPBX0
-               call __bb_init_func
-             local_label:
-
-  `profile_block_flag == 2'
-        Output code to call the subroutine `__bb_init_trace_func' and
-        pass two parameters to it.  The first parameter is the same as
-        for `__bb_init_func'.  The second parameter is the number of
-        the first basic block of the function as given by
-        BLOCK_OR_LABEL.  Note that `__bb_init_trace_func' has to be
-        called, even if the object module has been initialized
-        already.
-
-        Described in assembler language, the code to be output looks
-        like:
-             parameter1 <- LPBX0
-             parameter2 <- BLOCK_OR_LABEL
-             call __bb_init_trace_func */
-/* #define FUNCTION_BLOCK_PROFILER (FILE, LABELNO) */
-
-/* A C statement or compound statement to output to FILE some
-   assembler code to increment the count associated with the basic
-   block number BLOCKNO. */
-/* #define BLOCK_PROFILER(FILE, BLOCKNO) */
-
-/* A C statement or compound statement to output to FILE assembler
-   code to call function `__bb_trace_ret'.  The assembler code should
-   only be output if the global compile flag `profile_block_flag' ==
-   2.  This macro has to be used at every place where code for
-   returning from a function is generated (e.g. `FUNCTION_EPILOGUE').
-   Although you have to write the definition of `FUNCTION_EPILOGUE'
-   as well, you have to define this macro to tell the compiler, that
-   the proper call to `__bb_trace_ret' is produced. */
-/* #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) */
-
-/* A C statement or compound statement to save all registers, which
-   may be clobbered by a function call, including condition codes.
-   The `asm' statement will be mostly likely needed to handle this
-   task.  Local labels in the assembler code can be concatenated with
-   the string ID, to obtain a unique lable name.
-
-   Registers or condition codes clobbered by `FUNCTION_PROLOGUE' or
-   `FUNCTION_EPILOGUE' must be saved in the macros
-   `FUNCTION_BLOCK_PROFILER', `FUNCTION_BLOCK_PROFILER_EXIT' and
-   `BLOCK_PROFILER' prior calling `__bb_init_trace_func',
-   `__bb_trace_ret' and `__bb_trace_func' respectively. */
-/* #define MACHINE_STATE_SAVE(ID) */
-
-/* A C statement or compound statement to restore all registers,
-   including condition codes, saved by `MACHINE_STATE_SAVE'.
-
-   Registers or condition codes clobbered by `FUNCTION_PROLOGUE' or
-   `FUNCTION_EPILOGUE' must be restored in the macros
-   `FUNCTION_BLOCK_PROFILER', `FUNCTION_BLOCK_PROFILER_EXIT' and
-   `BLOCK_PROFILER' after calling `__bb_init_trace_func',
-   `__bb_trace_ret' and `__bb_trace_func' respectively. */
-/* #define MACHINE_STATE_RESTORE(ID) */
-
-/* A C function or functions which are needed in the library to
-   support block profiling. */
-/* #define BLOCK_PROFILER_CODE */
-
-
-/* Variable arguments */
-
-/* If defined, is a C expression that produces the machine-specific
-   code for a call to `__builtin_saveregs'.  This code will be moved
-   to the very beginning of the function, before any parameter access
-   are made.  The return value of this function should be an RTX that
-   contains the value to use as the return of `__builtin_saveregs'.
-
-   The argument ARGS is a `tree_list' containing the arguments that
-   were passed to `__builtin_saveregs'.
-
-   If this macro is not defined, the compiler will output an ordinary
-   call to the library function `__builtin_saveregs'. */
-#define EXPAND_BUILTIN_SAVEREGS(ARGS) expand_builtin_saveregs (ARGS)
-
-
-/* This macro offers an alternative to using `__builtin_saveregs' and
-   defining the macro `EXPAND_BUILTIN_SAVEREGS'.  Use it to store the
-   anonymous register arguments into the stack so that all the arguments
-   appear to have been passed consecutively on the stack.  Once this is done,
-   you can use the standard implementation of varargs that works for machines
-   that pass all their arguments on the stack. */
-#define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \
-  setup_incoming_varargs (&ARGS_SO_FAR, MODE, TYPE, &PRETEND_ARGS_SIZE, SECOND_TIME)
-
-/* Define this macro if the location where a function argument is
-   passed depends on whether or not it is a named argument.
-
-   This macro controls how the NAMED argument to `FUNCTION_ARG' is
-   set for varargs and stdarg functions.  With this macro defined,
-   the NAMED argument is always true for named arguments, and false
-   for unnamed arguments.  If this is not defined, but
-   `SETUP_INCOMING_VARARGS' is defined, then all arguments are
-   treated as named.  Otherwise, all named arguments except the last
-   are treated as named. */
-/* #define STRICT_ARGUMENT_NAMING */
-
-
-/* Trampolines */
-
-/* A C statement to output, on the stream FILE, assembler code for a
-   block of data that contains the constant parts of a trampoline.
-   This code should not include a label--the label is taken care of
-   automatically.
-
-   If you do not define this macro, it means no template is needed
-   for the target.  Do not define this macro on systems where the
-   block move code to copy the trampoline into place would be larger
-   than the code to generate it on the spot. */
-/* #define TRAMPOLINE_TEMPLATE(FILE) */
-
-/* The name of a subroutine to switch to the section in which the
-   trampoline template is to be placed (*note Sections::.).  The
-   default is a value of `readonly_data_section', which places the
-   trampoline in the section containing read-only data. */
-/* #define TRAMPOLINE_SECTION */
-
-/* A C expression for the size in bytes of the trampoline, as an
-   integer. */
-#define TRAMPOLINE_SIZE 8
-
-/* Alignment required for trampolines, in bits.
-
-   If you don't define this macro, the value of `BIGGEST_ALIGNMENT'
-   is used for aligning trampolines. */
-#define TRAMPOLINE_ALIGNMENT 32
-
-/* A C statement to initialize the variable parts of a trampoline.
-   ADDR is an RTX for the address of the trampoline; FNADDR is an RTX
-   for the address of the nested function; STATIC_CHAIN is an RTX for
-   the static chain value that should be passed to the function when
-   it is called. */
-
-#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
-  initialize_trampoline (ADDR, FNADDR, STATIC_CHAIN)
-
-/* A C expression to allocate run-time space for a trampoline.  The
-   expression value should be an RTX representing a memory reference
-   to the space for the trampoline.
-
-   If this macro is not defined, by default the trampoline is
-   allocated as a stack slot.  This default is right for most
-   machines.  The exceptions are machines where it is impossible to
-   execute instructions in the stack area.  On such machines, you may
-   have to implement a separate stack, using this macro in
-   conjunction with `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE'.
-
-   FP points to a data structure, a `struct function', which
-   describes the compilation status of the immediate containing
-   function of the function which the trampoline is for.  Normally
-   (when `ALLOCATE_TRAMPOLINE' is not defined), the stack slot for the
-   trampoline is in the stack frame of this containing function.
-   Other allocation strategies probably must do something analogous
-   with this information.
-
-   Implementing trampolines is difficult on many machines because they
-   have separate instruction and data caches.  Writing into a stack
-   location fails to clear the memory in the instruction cache, so when
-   the program jumps to that location, it executes the old contents.
-
-   Here are two possible solutions.  One is to clear the relevant parts
-   of the instruction cache whenever a trampoline is set up.  The other is
-   to make all trampolines identical, by having them jump to a standard
-   subroutine.  The former technique makes trampoline execution faster; the
-   latter makes initialization faster.
-
-   To clear the instruction cache when a trampoline is initialized,
-   define the following macros which describe the shape of the cache. */
-/* #define ALLOCATE_TRAMPOLINE(FP) allocate_trampoline(FP) */
-
-/* The total size in bytes of the cache. */
-/* #define INSN_CACHE_SIZE */
-
-/* The length in bytes of each cache line.  The cache is divided into
-   cache lines which are disjoint slots, each holding a contiguous
-   chunk of data fetched from memory.  Each time data is brought into
-   the cache, an entire line is read at once.  The data loaded into a
-   cache line is always aligned on a boundary equal to the line size. */
-/* #define INSN_CACHE_LINE_WIDTH */
-
-/* The number of alternative cache lines that can hold any particular
-   memory location.
-
-   Alternatively, if the machine has system calls or instructions to
-   clear the instruction cache directly, you can define the following
-   macro.  */
-/* #define INSN_CACHE_DEPTH */
-
-/* If defined, expands to a C expression clearing the *instruction
-   cache* in the specified interval.  If it is not defined, and the
-   macro INSN_CACHE_SIZE is defined, some generic code is generated
-   to clear the cache.  The definition of this macro would typically
-   be a series of `asm' statements.  Both BEG and END are both pointer
-   expressions.
-
-   To use a standard subroutine, define the following macro.  In
-   addition, you must make sure that the instructions in a trampoline fill
-   an entire cache line with identical instructions, or else ensure that
-   the beginning of the trampoline code is always aligned at the same
-   point in its cache line.  Look in `m68k.h' as a guide.
-/* #define CLEAR_INSN_CACHE (BEG, END) */
-
-/* Define this macro if trampolines need a special subroutine to do
-   their work.  The macro should expand to a series of `asm'
-   statements which will be compiled with GNU CC.  They go in a
-   library function named `__transfer_from_trampoline'.
-
-   If you need to avoid executing the ordinary prologue code of a
-   compiled C function when you jump to the subroutine, you can do so
-   by placing a special label of your own in the assembler code.  Use
-   one `asm' statement to generate an assembler label, and another to
-   make the label global.  Then trampolines can use that label to
-   jump directly to your special assembler code. */
-/* #define TRANSFER_FROM_TRAMPOLINE */
-
-
-/* Address modes */
-
-/* Define this macro if the machine supports post-increment,
-   pre-increment, post-decrement, and/or pre-decrement
-   addressing.  */
-#define HAVE_POST_INCREMENT 1
-#define HAVE_POST_DECREMENT 1
-#define HAVE_PRE_DECREMENT 1
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/** A C expression that is 1 if the RTX X is a constant which is a
-   valid address.  On most machines, this can be defined as
-   `CONSTANT_P (X)', but a few machines are more restrictive in which
-   constant addresses are supported.
-
-   `CONSTANT_P' accepts integer-values expressions whose values are
-   not explicitly known, such as `symbol_ref', `label_ref', and
-   `high' expressions and `const' arithmetic expressions, in addition
-   to `const_int' and `const_double' expressions. */
-#define CONSTANT_ADDRESS_P(X) CONSTANT_P(X)
-
-/* A number, the maximum number of registers that can appear in a
-   valid memory address.  Note that it is up to you to specify a
-   value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS'
-   would ever accept. */
-#define MAX_REGS_PER_ADDRESS 1
-
-/* A C compound statement with a conditional `goto LABEL;' executed
-   if X (an RTX) is a legitimate memory address on the target machine
-   for a memory operand of mode MODE.
-
-   It usually pays to define several simpler macros to serve as
-   subroutines for this one.  Otherwise it may be too complicated to
-   understand.
-
-   This macro must exist in two variants: a strict variant and a
-   non-strict one.  The strict variant is used in the reload pass.  It
-   must be defined so that any pseudo-register that has not been
-   allocated a hard register is considered a memory reference.  In
-   contexts where some kind of register is required, a pseudo-register
-   with no hard register must be rejected.
-
-   The non-strict variant is used in other passes.  It must be
-   defined to accept all pseudo-registers in every context where some
-   kind of register is required.
-
-   Compiler source files that want to use the strict variant of this
-   macro define the macro `REG_OK_STRICT'.  You should use an `#ifdef
-   REG_OK_STRICT' conditional to define the strict variant in that
-   case and the non-strict variant otherwise.
-
-   Subroutines to check for acceptable registers for various purposes
-   (one for base registers, one for index registers, and so on) are
-   typically among the subroutines used to define
-   `GO_IF_LEGITIMATE_ADDRESS'.  Then only these subroutine macros
-   need have two variants; the higher levels of macros may be the
-   same whether strict or not.  */
-
-#ifdef	REG_OK_STRICT
-#define REG_OK_STRICT_P 1
-#else
-#define REG_OK_STRICT_P 0
-#endif
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-do {									\
-    if (d10v_legitimate_address_p (MODE, X, REG_OK_STRICT_P))		\
-      goto ADDR;							\
-} while (0)
-
-/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is
-   valid for use as a base register.  For hard registers, it should
-   always accept those which the hardware permits and reject the
-   others.  Whether the macro accepts or rejects pseudo registers
-   must be controlled by `REG_OK_STRICT' as described above.  This
-   usually requires two variant definitions, of which `REG_OK_STRICT'
-   controls the one actually used.  */
-
-#ifdef REG_OK_STRICT
-#define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
-#else
-#define REG_OK_FOR_BASE_P(X)						\
- (GPR_P (REGNO (X))							\
-  || REGNO (X) == ARG_POINTER_REGNUM					\
-  || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-#endif
-
-/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is
-   valid for use as an index register.
-
-   The difference between an index register and a base register is
-   that the index register may be scaled.  If an address involves the
-   sum of two registers, neither one of them scaled, then either one
-   may be labeled the "base" and the other the "index"; but whichever
-   labeling is used must fit the machine's constraints of which
-   registers may serve in each capacity.  The compiler will try both
-   labelings, looking for one that is valid, and will reload one or
-   both registers only if neither labeling works.  */
-#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P(X)
-
-/* A C compound statement that attempts to replace X with a valid
-   memory address for an operand of mode MODE.  WIN will be a C
-   statement label elsewhere in the code; the macro definition may use
-
-        GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
-
-   to avoid further processing if the address has become legitimate.
-
-   X will always be the result of a call to `break_out_memory_refs',
-   and OLDX will be the operand that was given to that function to
-   produce X.
-
-   The code generated by this macro should not alter the substructure
-   of X.  If it transforms X into a more legitimate form, it should
-   assign X (which will always be a C variable) a new value.
-
-   It is not necessary for this macro to come up with a legitimate
-   address.  The compiler has standard ways of doing so in all cases.
-   In fact, it is safe for this macro to do nothing.  But often a
-   machine-dependent strategy can generate better code. */
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)				\
-do {									\
-  rtx y = d10v_legitimize_address (X, OLDX, MODE, REG_OK_STRICT_P);	\
-  if (y)								\
-    {									\
-      X = y;								\
-      GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);				\
-    }									\
-} while (0)
-
-/* A C statement or compound statement with a conditional `goto
-   LABEL;' executed if memory address X (an RTX) can have different
-   meanings depending on the machine mode of the memory reference it
-   is used for or if the address is valid for some modes but not
-   others.
-
-   Autoincrement and autodecrement addresses typically have
-   mode-dependent effects because the amount of the increment or
-   decrement is the size of the operand being addressed.  Some
-   machines have other mode-dependent addresses.  Many RISC machines
-   have no mode-dependent addresses.
-
-   You may assume that ADDR is a valid address for the machine. */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)			\
-do {									\
-  if (d10v_mode_dependent_address_p (ADDR))				\
-    goto LABEL;								\
-} while (0)								\
-
-/* A C expression that is nonzero if X is a legitimate constant for
-   an immediate operand on the target machine.  You can assume that X
-   satisfies `CONSTANT_P', so you need not check this.  In fact, `1'
-   is a suitable definition for this macro on machines where anything
-   `CONSTANT_P' is valid. */
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-
-/* Condition codes */
-
-/* C code for a data type which is used for declaring the `mdep'
-   component of `cc_status'.  It defaults to `int'.
-
-   This macro is not used on machines that do not use `cc0'. */
-/* #define CC_STATUS_MDEP */
-
-/* A C expression to initialize the `mdep' field to "empty".  The
-   default definition does nothing, since most machines don't use the
-   field anyway.  If you want to use the field, you should probably
-   define this macro to initialize it.
-
-   This macro is not used on machines that do not use `cc0'. */
-/* #define CC_STATUS_MDEP_INIT */
-
-/* A C compound statement to set the components of `cc_status'
-   appropriately for an insn INSN whose body is EXP.  It is this
-   macro's responsibility to recognize insns that set the condition
-   code as a byproduct of other activity as well as those that
-   explicitly set `(cc0)'.
-
-   This macro is not used on machines that do not use `cc0'.
-
-   If there are insns that do not set the condition code but do alter
-   other machine registers, this macro must check to see whether they
-   invalidate the expressions that the condition code is recorded as
-   reflecting.  For example, on the 68000, insns that store in address
-   registers do not set the condition code, which means that usually
-   `NOTICE_UPDATE_CC' can leave `cc_status' unaltered for such insns.
-   But suppose that the previous insn set the condition code based
-   on location `a4@(102)' and the current insn stores a new value in
-   `a4'.  Although the condition code is not changed by this, it will
-   no longer be true that it reflects the contents of `a4@(102)'.
-   Therefore, `NOTICE_UPDATE_CC' must alter `cc_status' in this case
-   to say that nothing is known about the condition code value.
-
-   The definition of `NOTICE_UPDATE_CC' must be prepared to deal with
-   the results of peephole optimization: insns whose patterns are
-   `parallel' RTXs containing various `reg', `mem' or constants which
-   are just the operands.  The RTL structure of these insns is not
-   sufficient to indicate what the insns actually do.  What
-   `NOTICE_UPDATE_CC' should do when it sees one is just to run
-   `CC_STATUS_INIT'.
-
-   A possible definition of `NOTICE_UPDATE_CC' is to call a function
-   that looks at an attribute (*note Insn Attributes::.) named, for
-   example, `cc'.  This avoids having detailed information about
-   patterns in two places, the `md' file and in `NOTICE_UPDATE_CC'. */
-/* #define NOTICE_UPDATE_CC (EXP, INSN) */
-
-/* A list of names to be used for additional modes for condition code
-   values in registers (*note Jump Patterns::.).  These names are
-   added to `enum machine_mode' and all have class `MODE_CC'.  By
-   convention, they should start with `CC' and end with `mode'.
-
-   You should only define this macro if your machine does not use
-   `cc0' and only if additional modes are required. */
-#define EXTRA_CC_MODES CC_REVmode
-
-/* A list of C strings giving the names for the modes listed in
-   `EXTRA_CC_MODES'.  For example, the Sparc defines this macro and
-   `EXTRA_CC_MODES' as
-
-        #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
-        #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
-
-   This macro is not required if `EXTRA_CC_MODES' is not defined. */
-#define EXTRA_CC_NAMES "CC_REV"
-
-/* Returns a mode from class `MODE_CC' to be used when comparison
-   operation code OP is applied to rtx X and Y.  For example, on the
-   Sparc, `SELECT_CC_MODE' is defined as (see *note Jump Patterns::.
-   for a description of the reason for this definition)
-
-        #define SELECT_CC_MODE(OP,X,Y) \
-          (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT          \
-           ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode)    \
-           : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS    \
-               || GET_CODE (X) == NEG) \
-              ? CC_NOOVmode : CCmode))
-
-   You need not define this macro if `EXTRA_CC_MODES' is not defined. */
-#define SELECT_CC_MODE(OP, X, Y) ((enum machine_mode) select_cc_mode (OP, X, Y))
-
-/* One some machines not all possible comparisons are defined, but
-   you can convert an invalid comparison into a valid one.  For
-   example, the Alpha does not have a `GT' comparison, but you can
-   use an `LT' comparison instead and swap the order of the operands.
-
-   On such machines, define this macro to be a C statement to do any
-   required conversions.  CODE is the initial comparison code and OP0
-   and OP1 are the left and right operands of the comparison,
-   respectively.  You should modify CODE, OP0, and OP1 as required.
-
-   GNU CC will not assume that the comparison resulting from this
-   macro is valid but will see if the resulting insn matches a
-   pattern in the `md' file.
-
-   You need not define this macro if it would never change the
-   comparison code or operands. */
-
-#if 0
-#define CANONICALIZE_COMPARISON(CODE,OP0,OP1)				\
-  do {									\
-    if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
-	&& (GET_CODE (OP1) == REG || (OP1) == const0_rtx))		\
-      {									\
-	rtx tem = (OP0);						\
-	(OP0) = (OP1);							\
-	(OP1) = tem;							\
-	(CODE) = swap_condition (CODE);					\
-      }									\
-    if (((CODE) == LT || (CODE) == LTU)					\
-	&& GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256)		\
-      {									\
-	(CODE) = (CODE) == LT ? LE : LEU;				\
-	(OP1) = GEN_INT (255);						\
-      }									\
-  } while (0)
-#endif
-
-
-/*   A C expression whose value is one if it is always safe to reverse a
-     comparison whose mode is MODE.  If `SELECT_CC_MODE' can ever
-     return MODE for a floating-point inequality comparison, then
-     `REVERSIBLE_CC_MODE (MODE)' must be zero.
-
-     You need not define this macro if it would always returns zero or
-     if the floating-point format is anything other than
-     `IEEE_FLOAT_FORMAT'.  For example, here is the definition used on
-     the Sparc, where floating-point inequality comparisons are always
-     given `CCFPEmode':
-
-          #define REVERSIBLE_CC_MODE(MODE)  ((MODE) != CCFPEmode) */
-/* #define REVERSIBLE_CC_MODE (MODE) */
-
-
-/* Describing Relative Costs of Operations  */
-
-/* A part of a C `switch' statement that describes the relative costs
-   of constant RTL expressions.  It must contain `case' labels for
-   expression codes `const_int', `const', `symbol_ref', `label_ref'
-   and `const_double'.  Each case must ultimately reach a `return'
-   statement to return the relative cost of the use of that kind of
-   constant value in an expression.  The cost may depend on the
-   precise value of the constant, which is available for examination
-   in X, and the rtx code of the expression in which it is contained,
-   found in OUTER_CODE. */
-#define CONST_COSTS(X, CODE, OUTER_CODE)				\
-  return COSTS_N_INSNS (1);
-
-/* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
-   This can be used, for example, to indicate how costly a multiply
-   instruction is.  In writing this macro, you can use the construct
-   `COSTS_N_INSNS (N)' to specify a cost equal to N fast
-   instructions.  OUTER_CODE is the code of the expression in which X
-   is contained.
-
-   This macro is optional; do not define it if the default cost
-   assumptions are adequate for the target machine.  */
-#define RTX_COSTS(X, CODE, OUTER_CODE)					\
-  case MULT:								\
-    return COSTS_N_INSNS (2);						\
-  case DIV:								\
-  case MOD:								\
-  case UDIV:								\
-  case UMOD:								\
-    return COSTS_N_INSNS (TARGET_DEBUG ? 2 : 16);
-
-/* An expression giving the cost of an addressing mode that contains
-   ADDRESS.  If not defined, the cost is computed from the ADDRESS
-   expression and the `CONST_COSTS' values.
-
-   For most CISC machines, the default cost is a good approximation
-   of the true cost of the addressing mode.  However, on RISC
-   machines, all instructions normally have the same length and
-   execution time.  Hence all addresses will have equal costs.
-
-   In cases where more than one form of an address is known, the form
-   with the lowest cost will be used.  If multiple forms have the
-   same, lowest, cost, the one that is the most complex will be used.
-
-   This macro will normally either not be defined or be defined as a
-   constant.  */
-/* #define ADDRESS_COST (ADDRESS) */
-
-/* A C expression for the cost of moving data from a register in class
-   FROM to one in class TO.  The classes are expressed using the
-   enumeration values such as `GENERAL_REGS'.  A value of 2 is the
-   default; other values are interpreted relative to that.
-
-   It is not required that the cost always equal 2 when FROM is the
-   same as TO; on some machines it is expensive to move between
-   registers if they are not general registers.
-
-   If reload sees an insn consisting of a single `set' between two
-   hard registers, and if `REGISTER_MOVE_COST' applied to their
-   classes returns a value of 2, reload does not check to ensure that
-   the constraints of the insn are met.  Setting a cost of other than
-   2 will allow reload to verify that the constraints are met.  You
-   should do this if the `movM' pattern's constraints do not allow
-   such copying.  */
-/* #define REGISTER_MOVE_COST (FROM, TO) */
-
-/* A C expression for the cost of moving data of mode M between a
-   register and memory.  A value of 4 is the default; this cost is
-   relative to those in `REGISTER_MOVE_COST'.
-
-   If moving between registers and memory is more expensive than
-   between two registers, you should define this macro to express the
-   relative cost.  */
-/* #define MEMORY_MOVE_COST (M,C,I) */
-
-/* A C expression for the cost of a branch instruction.  A value of 1
-   is the default; other values are interpreted relative to that.  */
-#define BRANCH_COST d10v_branch_cost
-
-/* Values of the -mbranch-cost=n string.  */
-extern int d10v_branch_cost;
-extern char *d10v_branch_cost_string;
-
-/* A C expression for the maximum number of instructions to execute via
-   conditional execution instructions instead of a branch.  A value of
-   BRANCH_COST+1 is the default if the machine does not use cc0, and 1 if it
-   does use cc0. */
-#define MAX_CONDITIONAL_EXECUTE d10v_cond_exec
-
-/* Values of the -mcond-exec=n string.  */
-extern int d10v_cond_exec;
-extern char *d10v_cond_exec_string;
-
-
-/* Define this macro as a C expression which is nonzero if accessing
-   less than a word of memory (i.e. a `char' or a `short') is no
-   faster than accessing a word of memory, i.e., if such access
-   require more than one instruction or if there is no difference in
-   cost between byte and (aligned) word loads.
-
-   When this macro is not defined, the compiler will access a field by
-   finding the smallest containing object; when it is defined, a
-   fullword load will be used if alignment permits.  Unless bytes
-   accesses are faster than word accesses, using word accesses is
-   preferable since it may eliminate subsequent memory access if
-   subsequent accesses occur to other fields in the same word of the
-   structure, but to different bytes.  */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define this macro if zero-extension (of a `char' or `short' to an
-   `int') can be done faster if the destination is a register that is
-   known to be zero.
-
-   If you define this macro, you must have instruction patterns that
-   recognize RTL structures like this:
-
-          (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
-   and likewise for `HImode'.  */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Define this macro to be the value 1 if unaligned accesses have a
-   cost many times greater than aligned accesses, for example if they
-   are emulated in a trap handler.
-   
-   When this macro is non-zero, the compiler will act as if
-   `STRICT_ALIGNMENT' were non-zero when generating code for block
-   moves.  This can cause significantly more instructions to be
-   produced.  Therefore, do not set this macro non-zero if unaligned
-   accesses only add a cycle or two to the time for a memory access.
-   
-   If the value of this macro is always zero, it need not be defined. */
-/* #define SLOW_UNALIGNED_ACCESS */
-
-/* Define this macro to inhibit strength reduction of memory
-   addresses.  (On some machines, such strength reduction seems to do
-   harm rather than good.)  */
-/* #define DONT_REDUCE_ADDR */
-
-/* The number of scalar move insns which should be generated instead
-   of a string move insn or a library call.  Increasing the value
-   will always make code faster, but eventually incurs high cost in
-   increased code size.
-
-   If you don't define this, a reasonable default is used. */
-#define MOVE_RATIO 4
-
-/* Define this macro if it is as good or better to call a constant
-   function address than to call an address kept in a register. */
-#define NO_FUNCTION_CSE
-
-/* Define this macro if it is as good or better for a function to call
-   itself with an explicit address than to call an address kept in a
-   register. */
-#define NO_RECURSIVE_FUNCTION_CSE
-
-/* A C statement (sans semicolon) to update the integer variable COST
-   based on the relationship between INSN that is dependent on
-   DEP_INSN through the dependence LINK.  The default is to make no
-   adjustment to COST.  This can be used for example to specify to
-   the scheduler that an output- or anti-dependence does not incur
-   the same cost as a data-dependence. */
-/* #define ADJUST_COST (INSN, LINK, DEP_INSN, COST) */
-
-/* A C statement (sans semicolon) to update the integer scheduling
-   priority `INSN_PRIORITY(INSN)'.  Reduce the priority to execute
-   the INSN earlier, increase the priority to execute INSN later.
-   Do not define this macro if you do not need to adjust the
-   scheduling priorities of insns. */
-/* #define ADJUST_PRIORITY (INSN) */
-
-
-/* Dividing the Output into Sections (Texts, Data, ...) */
-
-/* A C expression whose value is a string containing the assembler
-   operation that should precede instructions and read-only data.
-   Normally `".text"' is right.  */
-#define TEXT_SECTION_ASM_OP "\t.text"
-
-
-/* A C expression whose value is a string containing the assembler
-   operation to identify the following data as writable initialized
-   data.  Normally `".data"' is right.  */
-#define DATA_SECTION_ASM_OP "\t.data"
-
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as shared data.
-   If not defined, `DATA_SECTION_ASM_OP' will be used. */
-/* #define SHARED_SECTION_ASM_OP */
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as
-   uninitialized global data.  If not defined, and neither
-   `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
-   uninitialized global data will be output in the data section if
-   `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
-   used.  */
-#ifndef BSS_SECTION_ASM_OP
-#define BSS_SECTION_ASM_OP ".section\t.bss"
-#endif
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as
-   uninitialized global shared data.  If not defined, and
-   `BSS_SECTION_ASM_OP' is, the latter will be used. */
-/* #define SHARED_BSS_SECTION_ASM_OP */
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as
-   initialization code.  If not defined, GNU CC will assume such a
-   section does not exist. */
-/* #define INIT_SECTION_ASM_OP */
-
-/* A list of names for sections other than the standard two, which are
-   `in_text' and `in_data'.  You need not define this macro on a
-   system with no other sections (that GCC needs to use). */
-/* #define EXTRA_SECTIONS */
-
-/* One or more functions to be defined in `varasm.c'.  These
-   functions should do jobs analogous to those of `text_section' and
-   `data_section', for your additional sections.  Do not define this
-   macro if you do not define `EXTRA_SECTIONS'. */
-/* #define EXTRA_SECTION_FUNCTIONS */
-
-/* On most machines, read-only variables, constants, and jump tables
-   are placed in the text section.  If this is not the case on your
-   machine, this macro should be defined to be the name of a function
-   (either `data_section' or a function defined in `EXTRA_SECTIONS')
-   that switches to the section to be used for read-only items.
-
-   If these items should be placed in the text section, this macro
-   should not be defined. */
-/* #define READONLY_DATA_SECTION */
-
-/* A C statement or statements to switch to the appropriate section
-   for output of EXP.  You can assume that EXP is either a `VAR_DECL'
-   node or a constant of some sort.  RELOC indicates whether the
-   initial value of EXP requires link-time relocations.  Select the
-   section by calling `text_section' or one of the alternatives for
-   other sections.
-
-   Do not define this macro if you put all read-only variables and
-   constants in the read-only data section (usually the text section). */
-/* #define SELECT_SECTION (EXP, RELOC) */
-
-/* A C statement or statements to switch to the appropriate section
-   for output of RTX in mode MODE.  You can assume that RTX is some
-   kind of constant in RTL.  The argument MODE is redundant except in
-   the case of a `const_int' rtx.  Select the section by calling
-   `text_section' or one of the alternatives for other sections.
-
-   Do not define this macro if you put all constants in the read-only
-   data section. */
-/* #define SELECT_RTX_SECTION (MODE, RTX) */
-
-/* Define this macro if jump tables (for `tablejump' insns) should be
-   output in the text section, along with the assembler instructions.
-   Otherwise, the readonly data section is used.
-
-   This macro is irrelevant if there is no separate readonly data
-   section. */
-/* #define JUMP_TABLES_IN_TEXT_SECTION */
-
-/* Define this macro if references to a symbol must be treated
-   differently depending on something about the variable or function
-   named by the symbol (such as what section it is in).
-
-   The macro definition, if any, is executed immediately after the
-   rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
-   The value of the rtl will be a `mem' whose address is a
-   `symbol_ref'.
-
-   The usual thing for this macro to do is to record a flag in the
-   `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
-   name string in the `symbol_ref' (if one bit is not enough
-   information). */
-#define ENCODE_SECTION_INFO(DECL) encode_section_info (DECL)
-
-/* Decode SYM_NAME and store the real name part in VAR, sans the
-   characters that encode section info.  Define this macro if
-   `ENCODE_SECTION_INFO' alters the symbol's name string. */
-/* #define STRIP_NAME_ENCODING (VAR, SYM_NAME) */
-
-/* For objects going into their own sections, a C expression of the
-   name of the section, expressed as a STRING_CST node, to put DECL
-   into.  The STRING_CST node must be allocated in the saveable
-   obstack.  Function `build_string' can be used to do this.  If you
-   do not define this macro, GNU CC will use the symbol name as the
-   section name. */
-/* #define UNIQUE_SECTION (DECL) */
-
-
-/* Position Independent Code */
-
-/* The register number of the register used to address a table of
-   static data addresses in memory.  In some cases this register is
-   defined by a processor's "application binary interface" (ABI).
-   When this macro is defined, RTL is generated for this register
-   once, as with the stack pointer and frame pointer registers.  If
-   this macro is not defined, it is up to the machine-dependent files
-   to allocate such a register (if necessary). */
-/* #define PIC_OFFSET_TABLE_REGNUM */
-
-/* Define this macro if the register defined by
-   `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls.  Do not define
-   this macro if `PPIC_OFFSET_TABLE_REGNUM' is not defined. */
-/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
-
-/* By generating position-independent code, when two different
-   programs (A and B) share a common library (libC.a), the text of
-   the library can be shared whether or not the library is linked at
-   the same address for both programs.  In some of these
-   environments, position-independent code requires not only the use
-   of different addressing modes, but also special code to enable the
-   use of these addressing modes.
-
-   The `FINALIZE_PIC' macro serves as a hook to emit these special
-   codes once the function is being compiled into assembly code, but
-   not before.  (It is not done before, because in the case of
-   compiling an inline function, it would lead to multiple PIC
-   prologues being included in functions which used inline functions
-   and were compiled to assembly language.) */
-/* #define FINALIZE_PIC */
-
-/* A C expression that is nonzero if X is a legitimate immediate
-   operand on the target machine when generating position independent
-   code.  You can assume that X satisfies `CONSTANT_P', so you need
-   not check this.  You can also assume FLAG_PIC is true, so you need
-   not check it either.  You need not define this macro if all
-   constants (including `SYMBOL_REF') can be immediate operands when
-   generating position independent code. */
-/* #define LEGITIMATE_PIC_OPERAND_P (X) */
-
-
-/* The Overall Framework of an Assembler File */
-
-/* A C expression which outputs to the stdio stream STREAM some
-   appropriate text to go at the start of an assembler file.
-
-   Normally this macro is defined to output a line containing
-   `#NO_APP', which is a comment that has no effect on most
-   assemblers but tells the GNU assembler that it can save time by not
-   checking for certain assembler constructs.
-
-   On systems that use SDB, it is necessary to output certain
-   commands; see `attasm.h'. */
-/* #define ASM_FILE_START (STREAM) */
-
-/* A C expression which outputs to the stdio stream STREAM some
-   appropriate text to go at the end of an assembler file.
-
-   If this macro is not defined, the default is to output nothing
-   special at the end of the file.  Most systems don't require any
-   definition.
-
-   On systems that use SDB, it is necessary to output certain
-   commands; see `attasm.h'. */
-/* #define ASM_FILE_END (STREAM) */
-
-/* A C statement to output assembler commands which will identify the
-   object file as having been compiled with GNU CC (or another GNU
-   compiler).
-
-   If you don't define this macro, the string `gcc_compiled.:' is
-   output.  This string is calculated to define a symbol which, on
-   BSD systems, will never be defined for any other reason.  GDB
-   checks for the presence of this symbol when reading the symbol
-   table of an executable.
-
-   On non-BSD systems, you must arrange communication with GDB in
-   some other fashion.  If GDB is not used on your system, you can
-     define this macro with an empty body */
-/* #define ASM_IDENTIFY_GCC (FILE) */
-
-/* A C string constant describing how to begin a comment in the target
-   assembler language.  The compiler assumes that the comment will
-   end at the end of the line.  */
-#define ASM_COMMENT_START ";"
-
-/* A C string constant for text to be output before each `asm'
-   statement or group of consecutive ones.  Normally this is
-   `"#APP"', which is a comment that has no effect on most assemblers
-   but tells the GNU assembler that it must check the lines that
-   follow for all valid assembler constructs.  */
-#define ASM_APP_ON ";APP_ON\n"
-
-/* A C string constant for text to be output after each `asm'
-   statement or group of consecutive ones.  Normally this is
-   `"#NO_APP"', which tells the GNU assembler to resume making the
-   time-saving assumptions that are valid for ordinary compiler
-   output.  */
-#define ASM_APP_OFF ";APP_OFF\n"
-
-/* A C statement to output COFF information or DWARF debugging
-   information which indicates that filename NAME is the current
-   source file to the stdio stream STREAM.
-
-   This macro need not be defined if the standard form of output for
-   the file format in use is appropriate. */
-/* #define ASM_OUTPUT_SOURCE_FILENAME (STREAM, NAME) */
-
-/* A C statement to output DBX or SDB debugging information before
-   code for line number LINE of the current source file to the stdio
-   stream STREAM.
-
-   This macro need not be defined if the standard form of debugging
-     information for the debugger in use is appropriate */
-/* #define ASM_OUTPUT_SOURCE_LINE (STREAM, LINE) */
-
-/* A C statement to output something to the assembler file to handle a
-   `#ident' directive containing the text STRING.  If this macro is
-   not defined, nothing is output for a `#ident' directive. */
-/* #define ASM_OUTPUT_IDENT (STREAM, STRING) */
-
-/* A C statement to output something to the assembler file to switch
-   to section NAME for object DECL which is either a `FUNCTION_DECL',
-   a `VAR_DECL' or `NULL_TREE'.  Some target formats do not support
-   arbitrary sections.  Do not define this macro in such cases.
-
-   At present this macro is only used to support section attributes.
-   When this macro is undefined, section attributes are disabled. */
-/* #define ASM_OUTPUT_SECTION_NAME (STREAM, DECL, NAME, RELOC) */
-
-/* A C statement to output any assembler statements which are
-    required to precede any Objective C object definitions or message
-    sending.  The statement is executed only when compiling an
-    Objective C program. */
-/* #define `BJC_PROLOGUE */
-
-
-/* Output of Data */
-
-/* A C statement to output to the stdio stream STREAM an assembler
-   instruction to assemble a floating-point constant of `TFmode',
-   `DFmode', `SFmode', `TQFmode', `HFmode', or `QFmode',
-   respectively, whose value is VALUE.  VALUE will be a C expression
-   of type `REAL_VALUE_TYPE'.  Macros such as
-   `REAL_VALUE_TO_TARGET_DOUBLE' are useful for writing these
-   definitions.
-
-/* #define ASM_OUTPUT_LONG_DOUBLE (STREAM, VALUE) */
-/* #define ASM_OUTPUT_DOUBLE (STREAM, VALUE) */
-/* #define ASM_OUTPUT_FLOAT (STREAM, VALUE) */
-/* #define ASM_OUTPUT_THREE_QUARTER_FLOAT (STREAM, VALUE) */
-/* #define ASM_OUTPUT_SHORT_FLOAT (STREAM, VALUE) */
-/* #define ASM_OUTPUT_BYTE_FLOAT (STREAM, VALUE) */
-
-#if 1
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t[2];							\
-	REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);			\
-	fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n",		\
-		t[0] & 0xffffffff, t[1] & 0xffffffff);			\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str);			\
-	fprintf (FILE, "\t.double 0d%s\n", str);			\
-      }									\
-  }
-
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t;								\
-	REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
-	fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff);		\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);			\
-	fprintf (FILE, "\t.float 0d%s\n", str);				\
-      }									\
-  }
-
-#else
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)					\
-do									\
-  {									\
-    long t[2];								\
-    char str[30];							\
-									\
-    REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);				\
-    if (REAL_VALUE_ISINF (VALUE))					\
-      strcpy (str, "Infinity");						\
-    else if (REAL_VALUE_ISNAN (VALUE))					\
-      strcpy (str, "NaN");						\
-    else if (REAL_VALUE_MINUS_ZERO (VALUE))				\
-      strcpy (str, "-0");						\
-    else								\
-      REAL_VALUE_TO_DECIMAL ((VALUE), "%.20g", str);			\
-    									\
-    fprintf (FILE, "\t.long 0x%lx,0x%lx\t; %s\n",			\
-	     t[0] & 0xffffffff, t[1] & 0xffffffff, str);		\
-  }									\
-while (0)
-
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)					\
-do									\
-  {									\
-    long t;								\
-    char str[30];							\
-									\
-    if (REAL_VALUE_ISINF (VALUE))					\
-      strcpy (str, "Infinity");						\
-    else if (REAL_VALUE_ISNAN (VALUE))					\
-      strcpy (str, "NaN");						\
-    else if (REAL_VALUE_MINUS_ZERO (VALUE))				\
-      strcpy (str, "-0");						\
-    else								\
-      REAL_VALUE_TO_DECIMAL ((VALUE), "%.20g", str);			\
-    									\
-    REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);				\
-    fprintf (FILE, "\t.long 0x%lx\t; %s\n", t & 0xffffffff, str);	\
-  }									\
-while (0)
-#endif
-
-/* A C statement to output to the stdio stream STREAM an assembler
-   instruction to assemble an integer of 16, 8, 4, 2 or 1 bytes,
-   respectively, whose value is VALUE.  The argument EXP will be an
-   RTL expression which represents a constant value.  Use
-   `output_addr_const (STREAM, EXP)' to output this value as an
-   assembler expression.
-
-   For sizes larger than `UNITS_PER_WORD', if the action of a macro
-   would be identical to repeatedly calling the macro corresponding to
-   a size of `UNITS_PER_WORD', once for each word, you need not define
-   the macro.
-
-   On the D10V, we want to emit word addresses for functions & labels,
-   not byte addresses.  ENCODE_SECTION_INFO has set TREE_SIDE_EFFECT on
-   function nodes.  */
-
-/* #define ASM_OUTPUT_QUADRUPLE_INT (STREAM, EXP) */
-/* #define ASM_OUTPUT_DOUBLE_INT (STREAM, EXP) */
-
-#define ASM_OUTPUT_INT(STREAM, EXP)					\
-do {									\
-  fputs ("\t.long ", STREAM);						\
-  output_addr_const (STREAM, EXP);					\
-  putc ('\n', STREAM);							\
-} while (0)
-
-/* Use d10v_output_addr_const, not output_addr_const for HI values
-   to insure proper truncation and sign extension of negative offsets,
-   which sometimes get converted to unsigned HI values.  */
-#define ASM_OUTPUT_SHORT(STREAM, EXP)					\
-do {									\
-  fputs ("\t.word ", STREAM);						\
-  if (GET_CODE (EXP) == LABEL_REF)					\
-    {									\
-      d10v_output_addr_const (STREAM, EXP);				\
-      fputs ("@word", STREAM);						\
-    }									\
-									\
-  else if (GET_CODE (EXP) != SYMBOL_REF)				\
-    d10v_output_addr_const (STREAM, EXP);				\
-									\
-  else									\
-    {									\
-      tree id = get_identifier (XSTR (EXP, 0));				\
-      if (TREE_SIDE_EFFECTS (id))					\
-	fprintf (STREAM, "%s@word", XSTR (EXP, 0));			\
-      else								\
-	d10v_output_addr_const (STREAM, EXP);				\
-    }									\
-									\
-  putc ('\n', STREAM);							\
-} while (0)
-
-#define ASM_OUTPUT_CHAR(STREAM, EXP)					\
-do {									\
-  fputs ("\t.byte ", STREAM);						\
-  output_addr_const (STREAM, EXP);					\
-  putc ('\n', STREAM);							\
-} while (0)
-
-/* A C statement to output to the stdio stream STREAM an assembler
-   instruction to assemble a single byte containing the number VALUE.  */
-#define ASM_OUTPUT_BYTE(STREAM, VALUE) \
-  fprintf (STREAM, "\t%s %d\n", ASM_BYTE_OP, VALUE)
-
-/* A C string constant giving the pseudo-op to use for a sequence of
-   single-byte constants.  If this macro is not defined, the default
-   is `"byte"'.  */
-/* #define ASM_BYTE_OP */
-
-/* A C statement to output to the stdio stream STREAM an assembler
-   instruction to assemble a string constant containing the LEN bytes
-   at PTR.  PTR will be a C expression of type `char *' and LEN a C
-   expression of type `int'.
-
-   If the assembler has a `.ascii' pseudo-op as found in the Berkeley
-   Unix assembler, do not define the macro `ASM_OUTPUT_ASCII'. */
-/* #define ASM_OUTPUT_ASCII (STREAM, PTR, LEN) */
-
-/* A C statement to output assembler commands to define the start of
-   the constant pool for a function.  FUNNAME is a string giving the
-   name of the function.  Should the return type of the function be
-   required, it can be obtained via FUNDECL.  SIZE is the size, in
-   bytes, of the constant pool that will be written immediately after
-   this call.
-
-   If no constant-pool prefix is required, the usual case, this macro
-   need not be defined. */
-/* #define ASM_OUTPUT_POOL_PROLOGUE (FILE FUNNAME FUNDECL SIZE) */
-
-/* A C statement (with or without semicolon) to output a constant in
-   the constant pool, if it needs special treatment.  (This macro
-   need not do anything for RTL expressions that can be output
-   normally.)
-
-   The argument FILE is the standard I/O stream to output the
-   assembler code on.  X is the RTL expression for the constant to
-   output, and MODE is the machine mode (in case X is a `const_int').
-   ALIGN is the required alignment for the value X; you should
-   output an assembler directive to force this much alignment.
-
-   The argument LABELNO is a number to use in an internal label for
-   the address of this pool entry.  The definition of this macro is
-   responsible for outputting the label definition at the proper
-   place.  Here is how to do this:
-
-        ASM_OUTPUT_INTERNAL_LABEL (FILE, "LC", LABELNO);
-
-   When you output a pool entry specially, you should end with a
-   `goto' to the label JUMPTO.  This will prevent the same pool entry
-   from being output a second time in the usual manner.
-
-   You need not define this macro if it would do nothing. */
-/* #define ASM_OUTPUT_SPECIAL_POOL_ENTRY (FILE, X, MODE, ALIGN, LABELNO, JUMPTO) */
-
-/* Define this macro as a C expression which is nonzero if C is used
-   as a logical line separator by the assembler.
-
-   If you do not define this macro, the default is that only the
-   character `;' is treated as a logical line separator. */
-/* #define IS_ASM_LOGICAL_LINE_SEPARATOR (C) */
-
-/* These macros are defined as C string constant, describing the
-   syntax in the assembler for grouping arithmetic expressions. */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-
-/* Output of Uninitialized Variables */
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   STREAM the assembler definition of a common-label named NAME whose
-   size is SIZE bytes.  The variable ROUNDED is the size rounded up
-   to whatever alignment the caller wants.
-
-   Use the expression `assemble_name (STREAM, NAME)' to output the
-   name itself; before and after that, output the additional
-   assembler syntax for defining the name, and a newline.
-
-   This macro controls how the assembler definitions of uninitialized
-   common global variables are output. */
-/* #define ASM_OUTPUT_COMMON (STREAM, NAME, SIZE, ROUNDED) */
-
-/* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
-   separate, explicit argument.  If you define this macro, it is used
-   in place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
-   handling the required alignment of the variable.  The alignment is
-   specified as the number of bits. */
-/* #define ASM_OUTPUT_ALIGNED_COMMON (STREAM, NAME, SIZE, ALIGNMENT) */
-
-/* If defined, it is similar to `ASM_OUTPUT_COMMON', except that it
-   is used when NAME is shared.  If not defined, `ASM_OUTPUT_COMMON'
-   will be used. */
-/* #define ASM_OUTPUT_SHARED_COMMON (STREAM, NAME, SIZE, ROUNDED) */
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   STREAM the assembler definition of uninitialized global DECL named
-   NAME whose size is SIZE bytes.  The variable ROUNDED is the size
-   rounded up to whatever alignment the caller wants.
-
-   Try to use function `asm_output_bss' defined in `varasm.c' when
-   defining this macro.  If unable, use the expression `assemble_name
-   (STREAM, NAME)' to output the name itself; before and after that,
-   output the additional assembler syntax for defining the name, and
-   a newline.
-
-   This macro controls how the assembler definitions of uninitialized
-   global variables are output.  This macro exists to properly
-   support languages like `c++' which do not have `common' data.
-   However, this macro currently is not defined for all targets.  If
-   this macro and `ASM_OUTPUT_ALIGNED_BSS' are not defined then
-   `ASM_OUTPUT_COMMON' or `ASM_OUTPUT_ALIGNED_COMMON' is used. */
-/* #define ASM_OUTPUT_BSS (STREAM, DECL, NAME, SIZE, ROUNDED) */
-
-/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
-   separate, explicit argument.  If you define this macro, it is used
-   in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
-   handling the required alignment of the variable.  The alignment is
-   specified as the number of bits.
-
-   Try to use function `asm_output_aligned_bss' defined in file
-   `varasm.c' when defining this macro. */
-#ifndef ASM_OUTPUT_ALIGNED_BSS
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGNMENT) \
-  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGNMENT)
-#endif
-
-/* If defined, it is similar to `ASM_OUTPUT_BSS', except that it is
-   used when NAME is shared.  If not defined, `ASM_OUTPUT_BSS' will
-   be used. */
-/* #define ASM_OUTPUT_SHARED_BSS (STREAM, DECL, NAME, SIZE, ROUNDED) */
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   STREAM the assembler definition of a local-common-label named NAME
-   whose size is SIZE bytes.  The variable ROUNDED is the size
-   rounded up to whatever alignment the caller wants.
-
-   Use the expression `assemble_name (STREAM, NAME)' to output the
-   name itself; before and after that, output the additional
-   assembler syntax for defining the name, and a newline.
-
-   This macro controls how the assembler definitions of uninitialized
-   static variables are output. */
-/* #define ASM_OUTPUT_LOCAL (STREAM, NAME, SIZE, ROUNDED) */
-
-/* Like `ASM_OUTPUT_LOCAL' except takes the required alignment as a
-   separate, explicit argument.  If you define this macro, it is used
-   in place of `ASM_OUTPUT_LOCAL', and gives you more flexibility in
-   handling the required alignment of the variable.  The alignment is
-   specified as the number of bits. */
-/* #define ASM_OUTPUT_ALIGNED_LOCAL (STREAM, NAME, SIZE, ALIGNMENT) */
-
-/* If defined, it is similar to `ASM_OUTPUT_LOCAL', except that it is
-   used when NAME is shared.  If not defined, `ASM_OUTPUT_LOCAL' will
-   be used. */
-/* #define ASM_OUTPUT_SHARED_LOCAL (STREAM, NAME, SIZE, ROUNDED) */
-
-
-/* Output and Generation of Labels */
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   STREAM the assembler definition of a label named NAME.  Use the
-   expression `assemble_name (STREAM, NAME)' to output the name
-   itself; before and after that, output the additional assembler
-   syntax for defining the name, and a newline.  */
-#define ASM_OUTPUT_LABEL(STREAM, NAME)					\
-do {									\
-  assemble_name (STREAM, NAME);						\
-  fputs (":\n", STREAM);						\
-} while (0)
-
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   STREAM any text necessary for declaring the name NAME of a
-   function which is being defined.  This macro is responsible for
-   outputting the label definition (perhaps using
-   `ASM_OUTPUT_LABEL').  The argument DECL is the `FUNCTION_DECL'
-   tree node representing the function.
-
-   If this macro is not defined, then the function name is defined in
-   the usual manner as a label (by means of `ASM_OUTPUT_LABEL').  */
-/* #define ASM_DECLARE_FUNCTION_NAME (STREAM, NAME, DECL) */
-
-
-/*
-`ASM_DECLARE_FUNCTION_SIZE (STREAM, NAME, DECL)'
-     A C statement (sans semicolon) to output to the stdio stream
-     STREAM any text necessary for declaring the size of a function
-     which is being defined.  The argument NAME is the name of the
-     function.  The argument DECL is the `FUNCTION_DECL' tree node
-     representing the function.
-
-     If this macro is not defined, then the function size is not
-     defined.
-
-`ASM_DECLARE_OBJECT_NAME (STREAM, NAME, DECL)'
-     A C statement (sans semicolon) to output to the stdio stream
-     STREAM any text necessary for declaring the name NAME of an
-     initialized variable which is being defined.  This macro must
-     output the label definition (perhaps using `ASM_OUTPUT_LABEL').
-     The argument DECL is the `VAR_DECL' tree node representing the
-     variable.
-
-     If this macro is not defined, then the variable name is defined in
-     the usual manner as a label (by means of `ASM_OUTPUT_LABEL').
-
-`ASM_FINISH_DECLARE_OBJECT (STREAM, DECL, TOPLEVEL, ATEND)'
-     A C statement (sans semicolon) to finish up declaring a variable
-     name once the compiler has processed its initializer fully and
-     thus has had a chance to determine the size of an array when
-     controlled by an initializer.  This is used on systems where it's
-     necessary to declare something about the size of the object.
-
-     If you don't define this macro, that is equivalent to defining it
-     to do nothing.
-*/
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   STREAM some commands that will make the label NAME global; that
-   is, available for reference from other files.  Use the expression
-   `assemble_name (STREAM, NAME)' to output the name itself; before
-   and after that, output the additional assembler syntax for making
-   that name global, and a newline.  */
-
-#define ASM_GLOBALIZE_LABEL(STREAM,NAME)				\
-do {									\
-  fputs ("\t.globl ", STREAM);						\
-  assemble_name (STREAM, NAME);						\
-  fputs ("\n", STREAM);							\
-} while (0)
-
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   STREAM some commands that will make the label NAME weak; that is,
-   available for reference from other files but only used if no other
-   definition is available.  Use the expression `assemble_name
-   (STREAM, NAME)' to output the name itself; before and after that,
-   output the additional assembler syntax for making that name weak,
-   and a newline.
-
-   If you don't define this macro, GNU CC will not support weak
-   symbols and you should not define the `SUPPORTS_WEAK' macro. */
-/* #define ASM_WEAKEN_LABEL */
-
-/* A C expression which evaluates to true if the target supports weak
-   symbols.
-
-   If you don't define this macro, `defaults.h' provides a default
-   definition.  If `ASM_WEAKEN_LABEL' is defined, the default
-   definition is `1'; otherwise, it is `0'.  Define this macro if you
-   want to control weak symbol support with a compiler flag such as
-   `-melf'. */
-/* #define SUPPORTS_WEAK */
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   STREAM any text necessary for declaring the name of an external
-   symbol named NAME which is referenced in this compilation but not
-   defined.  The value of DECL is the tree node for the declaration.
-
-   This macro need not be defined if it does not need to output
-   anything.  The GNU assembler and most Unix assemblers don't
-   require anything. */
-
-/* #define ASM_OUTPUT_EXTERNAL(STREAM, DECL, NAME) */
-
-/* A C statement (sans semicolon) to output on STREAM an assembler
-   pseudo-op to declare a library function name external.  The name
-   of the library function is given by SYMREF, which has type `rtx'
-   and is a `symbol_ref'.
-
-   This macro need not be defined if it does not need to output
-   anything.  The GNU assembler and most Unix assemblers don't
-   require anything. */
-
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-/* #define ASM_OUTPUT_EXTERNAL_LIBCALL(STREAM, SYMREF) */
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   STREAM a reference in assembler syntax to a label named NAME.
-   This should add `_' to the front of the name, if that is customary
-   on your operating system, as it is in most Berkeley Unix systems.
-   This macro is used in `assemble_name'.  */
-/* #define ASM_OUTPUT_LABELREF(STREAM, NAME) */
-
-/* A C statement to output to the stdio stream STREAM a label whose
-   name is made from the string PREFIX and the number NUM.
-
-   It is absolutely essential that these labels be distinct from the
-   labels used for user-level functions and variables.  Otherwise,
-   certain programs will have name conflicts with internal labels.
-
-   It is desirable to exclude internal labels from the symbol table
-   of the object file.  Most assemblers have a naming convention for
-   labels that should be excluded; on many systems, the letter `L' at
-   the beginning of a label has this effect.  You should find out what
-   convention your system uses, and follow it.
-
-   The usual definition of this macro is as follows:
-
-          fprintf (STREAM, "L%s%d:\n", PREFIX, NUM) */
-/* #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) */
-
-/* A C statement to store into the string STRING a label whose name
-   is made from the string PREFIX and the number NUM.
-
-   This string, when output subsequently by `assemble_name', should
-   produce the output that `ASM_OUTPUT_INTERNAL_LABEL' would produce
-   with the same PREFIX and NUM.
-
-   If the string begins with `*', then `assemble_name' will output
-   the rest of the string unchanged.  It is often convenient for
-   `ASM_GENERATE_INTERNAL_LABEL' to use `*' in this way.  If the
-   string doesn't start with `*', then `ASM_OUTPUT_LABELREF' gets to
-   output the string, and may change it.  (Of course,
-   `ASM_OUTPUT_LABELREF' is also part of your machine description, so
-   you should know what it does on your machine.) */
-/* #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) */
-
-/* A C expression to assign to OUTVAR (which is a variable of type
-   `char *') a newly allocated string made from the string NAME and
-   the number NUMBER, with some suitable punctuation added.  Use
-   `alloca' to get space for the string.
-
-   The string will be used as an argument to `ASM_OUTPUT_LABELREF' to
-   produce an assembler label for an internal static variable whose
-   name is NAME.  Therefore, the string must be such as to result in
-   valid assembler code.  The argument NUMBER is different each time
-   this macro is executed; it prevents conflicts between
-   similarly-named internal static variables in different scopes.
-
-   Ideally this string should not be a valid C identifier, to prevent
-   any conflict with the user's own symbols.  Most assemblers allow
-   periods or percent signs in assembler symbols; putting at least
-   one of these between the name and the number will suffice.  */
-#define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER)			\
-do {									\
-  (OUTVAR) = (char *) alloca (strlen ((NAME)) + 12);			\
-  sprintf ((OUTVAR), "%s.%ld", (NAME), (long)(NUMBER));			\
-} while (0)
-
-/*
-`ASM_OUTPUT_DEF (STREAM, NAME, VALUE)'
-     A C statement to output to the stdio stream STREAM assembler code
-     which defines (equates) the symbol NAME to have the value VALUE.
-
-     If SET_ASM_OP is defined, a default definition is provided which is
-     correct for most systems.
-
-`OBJC_GEN_METHOD_LABEL (BUF, IS_INST, CLASS_NAME, CAT_NAME, SEL_NAME)'
-     Define this macro to override the default assembler names used for
-     Objective C methods.
-
-     The default name is a unique method number followed by the name of
-     the class (e.g. `_1_Foo').  For methods in categories, the name of
-     the category is also included in the assembler name (e.g.
-     `_1_Foo_Bar').
-
-     These names are safe on most systems, but make debugging difficult
-     since the method's selector is not present in the name.
-     Therefore, particular systems define other ways of computing names.
-
-     BUF is an expression of type `char *' which gives you a buffer in
-     which to store the name; its length is as long as CLASS_NAME,
-     CAT_NAME and SEL_NAME put together, plus 50 characters extra.
-
-     The argument IS_INST specifies whether the method is an instance
-     method or a class method; CLASS_NAME is the name of the class;
-     CAT_NAME is the name of the category (or NULL if the method is not
-     in a category); and SEL_NAME is the name of the selector.
-
-     On systems where the assembler can handle quoted names, you can
-     use this macro to provide more human-readable names.
-*/
-
-
-/* Macros Controlling Initialization Routines  */
-
-/*
-`INIT_SECTION_ASM_OP'
-     If defined, a C string constant for the assembler operation to
-     identify the following data as initialization code.  If not
-     defined, GNU CC will assume such a section does not exist.  When
-     you are using special sections for initialization and termination
-     functions, this macro also controls how `crtstuff.c' and
-     `libgcc2.c' arrange to run the initialization functions.
-
-`HAS_INIT_SECTION'
-     If defined, `main' will not call `__main' as described above.
-     This macro should be defined for systems that control the contents
-     of the init section on a symbol-by-symbol basis, such as OSF/1,
-     and should not be defined explicitly for systems that support
-     `INIT_SECTION_ASM_OP'.
-
-`LD_INIT_SWITCH'
-     If defined, a C string constant for a switch that tells the linker
-     that the following symbol is an initialization routine.
-
-`LD_FINI_SWITCH'
-     If defined, a C string constant for a switch that tells the linker
-     that the following symbol is a finalization routine.
-
-`INVOKE__main'
-     If defined, `main' will call `__main' despite the presence of
-     `INIT_SECTION_ASM_OP'.  This macro should be defined for systems
-     where the init section is not actually run automatically, but is
-     still useful for collecting the lists of constructors and
-     destructors.
-
-`ASM_OUTPUT_CONSTRUCTOR (STREAM, NAME)'
-     Define this macro as a C statement to output on the stream STREAM
-     the assembler code to arrange to call the function named NAME at
-     initialization time.
-
-     Assume that NAME is the name of a C function generated
-     automatically by the compiler.  This function takes no arguments.
-     Use the function `assemble_name' to output the name NAME; this
-     performs any system-specific syntactic transformations such as
-     adding an underscore.
-
-     If you don't define this macro, nothing special is output to
-     arrange to call the function.  This is correct when the function
-     will be called in some other manner--for example, by means of the
-     `collect2' program, which looks through the symbol table to find
-     these functions by their names.
-
-`ASM_OUTPUT_DESTRUCTOR (STREAM, NAME)'
-     This is like `ASM_OUTPUT_CONSTRUCTOR' but used for termination
-     functions rather than initialization functions.
-
-   If your system uses `collect2' as the means of processing
-constructors, then that program normally uses `nm' to scan an object
-file for constructor functions to be called.  On certain kinds of
-systems, you can define these macros to make `collect2' work faster
-(and, in some cases, make it work at all):
-
-`OBJECT_FORMAT_COFF'
-     Define this macro if the system uses COFF (Common Object File
-     Format) object files, so that `collect2' can assume this format
-     and scan object files directly for dynamic constructor/destructor
-     functions.
-
-`OBJECT_FORMAT_ROSE'
-     Define this macro if the system uses ROSE format object files, so
-     that `collect2' can assume this format and scan object files
-     directly for dynamic constructor/destructor functions.
-
-     These macros are effective only in a native compiler; `collect2' as
-     part of a cross compiler always uses `nm' for the target machine.
-
-`REAL_NM_FILE_NAME'
-     Define this macro as a C string constant containing the file name
-     to use to execute `nm'.  The default is to search the path
-     normally for `nm'.
-
-     If your system supports shared libraries and has a program to list
-     the dynamic dependencies of a given library or executable, you can
-     define these macros to enable support for running initialization
-     and termination functions in shared libraries:
-
-`LDD_SUFFIX'
-     Define this macro to a C string constant containing the name of the
-     program which lists dynamic dependencies, like `"ldd"' under SunOS
-     4.
-
-`PARSE_LDD_OUTPUT (PTR)'
-     Define this macro to be C code that extracts filenames from the
-     output of the program denoted by `LDD_SUFFIX'.  PTR is a variable
-     of type `char *' that points to the beginning of a line of output
-     from `LDD_SUFFIX'.  If the line lists a dynamic dependency, the
-     code must advance PTR to the beginning of the filename on that
-     line.  Otherwise, it must set PTR to `NULL'.
-*/
-
-
-/* Output of Assembler Instructions */
-
-/* A C initializer containing the assembler's names for the machine
-   registers, each one as a C string constant.  This is what
-   translates register numbers in the compiler into assembler
-   language.  */
-
-#define REGISTER_NAMES							\
-{									\
-  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",		\
-  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "sp",		\
-  "cr0",  "cr1",  "cr2",  "cr3",  "cr4",  "cr5",  "cr6",  "cr7",	\
-  "cr8",  "cr9",  "cr10", "cr11", "cr12", "cr13", "cr14", "cr15",	\
-  "a0",   "a1",								\
-  "ap",									\
-  "f0",   "f1",   "c",							\
-}
-
-/* If defined, a C initializer for an array of structures containing
-   a name and a register number.  This macro defines additional names
-   for hard registers, thus allowing the `asm' option in declarations
-   to refer to registers using alternate names.  */
-#define ADDITIONAL_REGISTER_NAMES					\
-{									\
-  "r15",	STACK_POINTER_REGNUM,					\
-  "repeat",	REPEAT_REGNUM,						\
-  "carry",	CARRY_REGNUM,						\
-}
-
-
-/*
-`ASM_OUTPUT_OPCODE (STREAM, PTR)'
-     Define this macro if you are using an unusual assembler that
-     requires different names for the machine instructions.
-
-     The definition is a C statement or statements which output an
-     assembler instruction opcode to the stdio stream STREAM.  The
-     macro-operand PTR is a variable of type `char *' which points to
-     the opcode name in its "internal" form--the form that is written
-     in the machine description.  The definition should output the
-     opcode name to STREAM, performing any translation you desire, and
-     increment the variable PTR to point at the end of the opcode so
-     that it will not be output twice.
-
-     In fact, your macro definition may process less than the entire
-     opcode name, or more than the opcode name; but if you want to
-     process text that includes `%'-sequences to substitute operands,
-     you must take care of the substitution yourself.  Just be sure to
-     increment PTR over whatever text should not be output normally.
-
-     If you need to look at the operand values, they can be found as the
-     elements of `recog_operand'.
-
-     If the macro definition does nothing, the instruction is output in
-     the usual way.
-
-`FINAL_PRESCAN_INSN (INSN, OPVEC, NOPERANDS)'
-     If defined, a C statement to be executed just prior to the output
-     of assembler code for INSN, to modify the extracted operands so
-     they will be output differently.
-
-     Here the argument OPVEC is the vector containing the operands
-     extracted from INSN, and NOPERANDS is the number of elements of
-     the vector which contain meaningful data for this insn.  The
-     contents of this vector are what will be used to convert the insn
-     template into assembler code, so you can change the assembler
-     output by changing the contents of the vector.
-
-     This macro is useful when various assembler syntaxes share a single
-     file of instruction patterns; by defining this macro differently,
-     you can cause a large class of instructions to be output
-     differently (such as with rearranged operands).  Naturally,
-     variations in assembler syntax affecting individual insn patterns
-     ought to be handled by writing conditional output routines in
-     those patterns.
-
-     If this macro is not defined, it is equivalent to a null statement.
-
-`FINAL_PRESCAN_LABEL'
-     If defined, `FINAL_PRESCAN_INSN' will be called on each
-     `CODE_LABEL'.  In that case, OPVEC will be a null pointer and
-     NOPERANDS will be zero.
-*/
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand X.  X is an RTL
-   expression.
-
-   CODE is a value that can be used to specify one of several ways of
-   printing the operand.  It is used when identical operands must be
-   printed differently depending on the context.  CODE comes from the
-   `%' specification that was used to request printing of the
-   operand.  If the specification was just `%DIGIT' then CODE is 0;
-   if the specification was `%LTR DIGIT' then CODE is the ASCII code
-   for LTR.
-
-   If X is a register, this macro should print the register's name.
-   The names can be found in an array `reg_names' whose type is `char
-   *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
-
-   When the machine description has a specification `%PUNCT' (a `%'
-   followed by a punctuation character), this macro is called with a
-   null pointer for X and the punctuation character for CODE.  */
-
-#define PRINT_OPERAND(STREAM, X, CODE) print_operand (STREAM, X, CODE)
-
-/* A C expression which evaluates to true if CODE is a valid
-     punctuation character for use in the `PRINT_OPERAND' macro.  If
-     `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
-     punctuation characters (except for the standard one, `%') are used
-     in this way. */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '|' || (CODE) == '.')
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand that is a memory
-   reference whose address is X.  X is an RTL expression.
-
-   On some machines, the syntax for a symbolic address depends on the
-   section that the address refers to.  On these machines, define the
-   macro `ENCODE_SECTION_INFO' to store the information into the
-   `symbol_ref', and then check for it here.  *Note Assembler
-   Format::.  */
-
-#define PRINT_OPERAND_ADDRESS(STREAM, X) print_operand_address (STREAM, X)
-
-/*
-`DBR_OUTPUT_SEQEND(FILE)'
-     A C statement, to be executed after all slot-filler instructions
-     have been output.  If necessary, call `dbr_sequence_length' to
-     determine the number of slots filled in a sequence (zero if not
-     currently outputting a sequence), to decide how many no-ops to
-     output, or whatever.
-
-     Don't define this macro if it has nothing to do, but it is helpful
-     in reading assembly output if the extent of the delay sequence is
-     made explicit (e.g. with white space).
-
-     Note that output routines for instructions with delay slots must be
-     prepared to deal with not being output as part of a sequence (i.e.
-     when the scheduling pass is not run, or when no slot fillers could
-     be found.)  The variable `final_sequence' is null when not
-     processing a sequence, otherwise it contains the `sequence' rtx
-     being output.
-
-`REGISTER_PREFIX'
-`LOCAL_LABEL_PREFIX'
-`USER_LABEL_PREFIX'
-`IMMEDIATE_PREFIX'
-     If defined, C string expressions to be used for the `%R', `%L',
-     `%U', and `%I' options of `asm_fprintf' (see `final.c').  These
-     are useful when a single `md' file must support multiple assembler
-     formats.  In that case, the various `tm.h' files can define these
-     macros differently.
-
-`ASSEMBLER_DIALECT'
-     If your target supports multiple dialects of assembler language
-     (such as different opcodes), define this macro as a C expression
-     that gives the numeric index of the assembler language dialect to
-     use, with zero as the first variant.
-
-     If this macro is defined, you may use
-     `{option0|option1|option2...}' constructs in the output templates
-     of patterns (*note Output Template::.) or in the first argument of
-     `asm_fprintf'.  This construct outputs `option0', `option1' or
-     `option2', etc., if the value of `ASSEMBLER_DIALECT' is zero, one
-     or two, etc.  Any special characters within these strings retain
-     their usual meaning.
-
-     If you do not define this macro, the characters `{', `|' and `}'
-     do not have any special meaning when used in templates or operands
-     to `asm_fprintf'.
-
-     Define the macros `REGISTER_PREFIX', `LOCAL_LABEL_PREFIX',
-     `USER_LABEL_PREFIX' and `IMMEDIATE_PREFIX' if you can express the
-     variations in assemble language syntax with that mechanism.  Define
-     `ASSEMBLER_DIALECT' and use the `{option0|option1}' syntax if the
-     syntax variant are larger and involve such things as different
-     opcodes or operand order.
-*/
-
-/* A C expression to output to STREAM some assembler code which will
-   push hard register number REGNO onto the stack.  The code need not
-   be optimal, since this macro is used only when profiling.  */
-
-#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO)				\
-  fprintf (STREAM, "\tsubi %s,-2\n\tst %s,@-%s\n",			\
-	   reg_names[STACK_POINTER_REGNUM],				\
-	   reg_names[REGNO],						\
-	   reg_names[STACK_POINTER_REGNUM])
-
-/* A C expression to output to STREAM some assembler code which will
-   pop hard register number REGNO off of the stack.  The code need
-   not be optimal, since this macro is used only when profiling.  */
-
-#define ASM_OUTPUT_REG_POP(STREAM, REGNO)				\
-  fprintf (STREAM, "\tld %s,@%s+\n\taddi %s,2\n",			\
-	   reg_names[REGNO],						\
-	   reg_names[STACK_POINTER_REGNUM],				\
-	   reg_names[STACK_POINTER_REGNUM])
-
-
-/* Output of Dispatch Tables */
-
-/* A C statement to output to the stdio stream STREAM an assembler
-   pseudo-instruction to generate a difference between two labels.
-   vALUE and REL are the numbers of two internal labels.  The
-   definitions of these labels are output using
-   `ASM_OUTPUT_INTERNAL_LABEL', and they must be printed in the same
-   way here.  For example,
-
-          fprintf (STREAM, "\t.word L%d-L%d\n",
-                   VALUE, REL)
-
-     You must provide this macro on machines where the addresses in a
-     dispatch table are relative to the table's own address.  If
-     defined, GNU CC will also use this macro on all machines when
-     producing PIC.  */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
-  fprintf (STREAM, "\t.word .L%d@word-.L%d@word\n", VALUE, REL)
-
-
-/* This macro should be provided on machines where the addresses in a
-   dispatch table are absolute.
-
-   The definition should be a C statement to output to the stdio
-   stream STREAM an assembler pseudo-instruction to generate a
-   reference to a label.  VALUE is the number of an internal label
-   whose definition is output using `ASM_OUTPUT_INTERNAL_LABEL'.  */
-#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
-  fprintf (STREAM, "\t.word .L%d@word\n", VALUE)
-
-/*
-`ASM_OUTPUT_CASE_LABEL (STREAM, PREFIX, NUM, TABLE)'
-     Define this if the label before a jump-table needs to be output
-     specially.  The first three arguments are the same as for
-     `ASM_OUTPUT_INTERNAL_LABEL'; the fourth argument is the jump-table
-     which follows (a `jump_insn' containing an `addr_vec' or
-     `addr_diff_vec').
-
-     This feature is used on system V to output a `swbeg' statement for
-     the table.
-
-     If this macro is not defined, these labels are output with
-     `ASM_OUTPUT_INTERNAL_LABEL'.
-
-`ASM_OUTPUT_CASE_END (STREAM, NUM, TABLE)'
-     Define this if something special must be output at the end of a
-     jump-table.  The definition should be a C statement to be executed
-     after the assembler code for the table is written.  It should write
-     the appropriate code to stdio stream STREAM.  The argument TABLE
-     is the jump-table insn, and NUM is the label-number of the
-     preceding label.
-
-     If this macro is not defined, nothing special is output at the end
-     of the jump-table.
-*/
-
-
-/* Assembler Commands for Alignment  */
-
-/*
-`LABEL_ALIGN_AFTER_BARRIER(LABEL)'
-     The alignment (log base 2) to put in front of LABEL, which follows
-     a BARRIER.
-
-     A C expression to output text to align the location counter in the
-     way that is desirable at a point in the code that is reached only
-     by jumping.
-
-     This macro need not be defined if you don't want any special
-     alignment to be done at such a time.  Most machine descriptions do
-     not currently define the macro.
-
-`LOOP_ALIGN (LABEL)'
-     The desired alignment for the location counter at the beginning
-     of a loop.
-
-     This macro need not be defined if you don't want any special
-     alignment to be done at such a time.  Most machine descriptions do
-     not currently define the macro.
-
-`ASM_OUTPUT_SKIP (STREAM, NBYTES)'
-     A C statement to output to the stdio stream STREAM an assembler
-     instruction to advance the location counter by NBYTES bytes.
-     Those bytes should be zero when loaded.  NBYTES will be a C
-     expression of type `int'.
-
-`ASM_NO_SKIP_IN_TEXT'
-     Define this macro if `ASM_OUTPUT_SKIP' should not be used in the
-     text section because it fails put zeros in the bytes that are
-     skipped.  This is true on many Unix systems, where the pseudo-op
-     to skip bytes produces no-op instructions rather than zeros when
-     used in the text section.
-*/
-
-/* A C statement to output to the stdio stream STREAM an assembler
-   command to advance the location counter to a multiple of 2 to the
-   POWER bytes.  POWER will be a C expression of type `int'.  */
-
-#define ASM_OUTPUT_ALIGN(STREAM, POWER)					\
-do {									\
-  if ((POWER) != 0)							\
-    fprintf (STREAM, "\t.align %d\n", (POWER));				\
-} while (0)
-
-
-/* Macros Affecting All Debugging Formats */
-
-/* A C expression that returns the DBX register number for the
-   compiler register number REGNO.  In simple cases, the value of this
-   expression may be REGNO itself.  But sometimes there are some
-   registers that the compiler knows about and DBX does not, or vice
-   versa.  In such cases, some register may need to have one number in
-   the compiler and another for DBX.
-
-   If two registers have consecutive numbers inside GNU CC, and they
-   can be used as a pair to hold a multiword value, then they *must*
-   have consecutive numbers after renumbering with
-   `DBX_REGISTER_NUMBER'.  Otherwise, debuggers will be unable to
-   access such a pair, because they expect register pairs to be
-   consecutive in their own numbering scheme.
-
-   If you find yourself defining `DBX_REGISTER_NUMBER' in way that
-   does not preserve register pairs, then what you must do instead is
-   redefine the actual register numbering scheme.  */
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/*
-`DEBUGGER_AUTO_OFFSET (X)'
-     A C expression that returns the integer offset value for an
-     automatic variable having address X (an RTL expression).  The
-     default computation assumes that X is based on the frame-pointer
-     and gives the offset from the frame-pointer.  This is required for
-     targets that produce debugging output for DBX or COFF-style
-     debugging output for SDB and allow the frame-pointer to be
-     eliminated when the `-g' options is used.
-
-`DEBUGGER_ARG_OFFSET (OFFSET, X)'
-     A C expression that returns the integer offset value for an
-     argument having address X (an RTL expression).  The nominal offset
-     is OFFSET.
-*/
-
-/* A C expression that returns the type of debugging output GNU CC
-   produces when the user specifies `-g' or `-ggdb'.  Define this if
-   you have arranged for GNU CC to support more than one format of
-   debugging output.  Currently, the allowable values are `DBX_DEBUG',
-   `SDB_DEBUG', `DWARF_DEBUG', and `XCOFF_DEBUG'.
-
-   The value of this macro only affects the default debugging output;
-   the user can always get a specific type of output by using
-   `-gstabs', `-gcoff', `-gdwarf', or `-gxcoff'.  */
-#undef	PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* Disable Dwarf2 right now, since it wants a fixed size for DOUBLE and INT */
-#undef DWARF2_DEBUGGING_INFO
-
-
-/* Specific Options for DBX Output */
-
-/*
-`DBX_DEBUGGING_INFO'
-     Define this macro if GNU CC should produce debugging output for DBX
-     in response to the `-g' option.
-
-`XCOFF_DEBUGGING_INFO'
-     Define this macro if GNU CC should produce XCOFF format debugging
-     output in response to the `-g' option.  This is a variant of DBX
-     format.
-
-`DEFAULT_GDB_EXTENSIONS'
-     Define this macro to control whether GNU CC should by default
-     generate GDB's extended version of DBX debugging information
-     (assuming DBX-format debugging information is enabled at all).  If
-     you don't define the macro, the default is 1: always generate the
-     extended information if there is any occasion to.
-
-`DEBUG_SYMS_TEXT'
-     Define this macro if all `.stabs' commands should be output while
-     in the text section.
-
-`ASM_STABS_OP'
-     A C string constant naming the assembler pseudo op to use instead
-     of `.stabs' to define an ordinary debugging symbol.  If you don't
-     define this macro, `.stabs' is used.  This macro applies only to
-     DBX debugging information format.
-
-`ASM_STABD_OP'
-     A C string constant naming the assembler pseudo op to use instead
-     of `.stabd' to define a debugging symbol whose value is the current
-     location.  If you don't define this macro, `.stabd' is used.  This
-     macro applies only to DBX debugging information format.
-
-`ASM_STABN_OP'
-     A C string constant naming the assembler pseudo op to use instead
-     of `.stabn' to define a debugging symbol with no name.  If you
-     don't define this macro, `.stabn' is used.  This macro applies
-     only to DBX debugging information format.
-
-`DBX_NO_XREFS'
-     Define this macro if DBX on your system does not support the
-     construct `xsTAGNAME'.  On some systems, this construct is used to
-     describe a forward reference to a structure named TAGNAME.  On
-     other systems, this construct is not supported at all.
-
-`DBX_CONTIN_LENGTH'
-     A symbol name in DBX-format debugging information is normally
-     continued (split into two separate `.stabs' directives) when it
-     exceeds a certain length (by default, 80 characters).  On some
-     operating systems, DBX requires this splitting; on others,
-     splitting must not be done.  You can inhibit splitting by defining
-     this macro with the value zero.  You can override the default
-     splitting-length by defining this macro as an expression for the
-     length you desire.
-
-`DBX_CONTIN_CHAR'
-     Normally continuation is indicated by adding a `\' character to
-     the end of a `.stabs' string when a continuation follows.  To use
-     a different character instead, define this macro as a character
-     constant for the character you want to use.  Do not define this
-     macro if backslash is correct for your system.
-
-`DBX_STATIC_STAB_DATA_SECTION'
-     Define this macro if it is necessary to go to the data section
-     before outputting the `.stabs' pseudo-op for a non-global static
-     variable.
-
-`DBX_TYPE_DECL_STABS_CODE'
-     The value to use in the "code" field of the `.stabs' directive for
-     a typedef.  The default is `N_LSYM'.
-
-`DBX_STATIC_CONST_VAR_CODE'
-     The value to use in the "code" field of the `.stabs' directive for
-     a static variable located in the text section.  DBX format does not
-     provide any "right" way to do this.  The default is `N_FUN'.
-
-`DBX_REGPARM_STABS_CODE'
-     The value to use in the "code" field of the `.stabs' directive for
-     a parameter passed in registers.  DBX format does not provide any
-     "right" way to do this.  The default is `N_RSYM'.
-
-`DBX_REGPARM_STABS_LETTER'
-     The letter to use in DBX symbol data to identify a symbol as a
-     parameter passed in registers.  DBX format does not customarily
-     provide any way to do this.  The default is `'P''.
-
-`DBX_MEMPARM_STABS_LETTER'
-     The letter to use in DBX symbol data to identify a symbol as a
-     stack parameter.  The default is `'p''.
-
-`DBX_FUNCTION_FIRST'
-     Define this macro if the DBX information for a function and its
-     arguments should precede the assembler code for the function.
-     Normally, in DBX format, the debugging information entirely
-     follows the assembler code.
-
-`DBX_LBRAC_FIRST'
-     Define this macro if the `N_LBRAC' symbol for a block should
-     precede the debugging information for variables and functions
-     defined in that block.  Normally, in DBX format, the `N_LBRAC'
-     symbol comes first.
-
-`DBX_BLOCKS_FUNCTION_RELATIVE'
-     Define this macro if the value of a symbol describing the scope of
-     a block (`N_LBRAC' or `N_RBRAC') should be relative to the start
-     of the enclosing function.  Normally, GNU C uses an absolute
-     address.
-
-`DBX_USE_BINCL'
-     Define this macro if GNU C should generate `N_BINCL' and `N_EINCL'
-     stabs for included header files, as on Sun systems.  This macro
-     also directs GNU C to output a type number as a pair of a file
-     number and a type number within the file.  Normally, GNU C does not
-     generate `N_BINCL' or `N_EINCL' stabs, and it outputs a single
-     number for a type number.
-*/
-
-
- /* Open-Ended Hooks for DBX Format */
-
-/*
-`DBX_OUTPUT_LBRAC (STREAM, NAME)'
-     Define this macro to say how to output to STREAM the debugging
-     information for the start of a scope level for variable names.  The
-     argument NAME is the name of an assembler symbol (for use with
-     `assemble_name') whose value is the address where the scope begins.
-
-`DBX_OUTPUT_RBRAC (STREAM, NAME)'
-     Like `DBX_OUTPUT_LBRAC', but for the end of a scope level.
-
-`DBX_OUTPUT_ENUM (STREAM, TYPE)'
-     Define this macro if the target machine requires special handling
-     to output an enumeration type.  The definition should be a C
-     statement (sans semicolon) to output the appropriate information
-     to STREAM for the type TYPE.
-
-`DBX_OUTPUT_FUNCTION_END (STREAM, FUNCTION)'
-     Define this macro if the target machine requires special output at
-     the end of the debugging information for a function.  The
-     definition should be a C statement (sans semicolon) to output the
-     appropriate information to STREAM.  FUNCTION is the
-     `FUNCTION_DECL' node for the function.
-
-`DBX_OUTPUT_STANDARD_TYPES (SYMS)'
-     Define this macro if you need to control the order of output of the
-     standard data types at the beginning of compilation.  The argument
-     SYMS is a `tree' which is a chain of all the predefined global
-     symbols, including names of data types.
-
-     Normally, DBX output starts with definitions of the types for
-     integers and characters, followed by all the other predefined
-     types of the particular language in no particular order.
-
-     On some machines, it is necessary to output different particular
-     types first.  To do this, define `DBX_OUTPUT_STANDARD_TYPES' to
-     output those symbols in the necessary order.  Any predefined types
-     that you don't explicitly output will be output afterward in no
-     particular order.
-
-     Be careful not to define this macro so that it works only for C.
-     There are no global variables to access most of the built-in
-     types, because another language may have another set of types.
-     The way to output a particular type is to look through SYMS to see
-     if you can find it.  Here is an example:
-
-          {
-            tree decl;
-            for (decl = syms; decl; decl = TREE_CHAIN (decl))
-              if (!strcmp (IDENTIFIER_POINTER (DECL_NAME (decl)),
-                           "long int"))
-                dbxout_symbol (decl);
-            ...
-          }
-
-     This does nothing if the expected type does not exist.
-
-     See the function `init_decl_processing' in `c-decl.c' to find the
-     names to use for all the built-in C types.
-*/
-
-
-/* File Names in DBX Format */
-
-/*
-`DBX_WORKING_DIRECTORY'
-     Define this if DBX wants to have the current directory recorded in
-     each object file.
-
-     Note that the working directory is always recorded if GDB
-     extensions are enabled.
-
-`DBX_OUTPUT_MAIN_SOURCE_FILENAME (STREAM, NAME)'
-     A C statement to output DBX debugging information to the stdio
-     stream STREAM which indicates that file NAME is the main source
-     file--the file specified as the input file for compilation.  This
-     macro is called only once, at the beginning of compilation.
-
-     This macro need not be defined if the standard form of output for
-     DBX debugging information is appropriate.
-
-`DBX_OUTPUT_MAIN_SOURCE_DIRECTORY (STREAM, NAME)'
-     A C statement to output DBX debugging information to the stdio
-     stream STREAM which indicates that the current directory during
-     compilation is named NAME.
-
-     This macro need not be defined if the standard form of output for
-     DBX debugging information is appropriate.
-
-`DBX_OUTPUT_MAIN_SOURCE_FILE_END (STREAM, NAME)'
-     A C statement to output DBX debugging information at the end of
-     compilation of the main source file NAME.
-
-     If you don't define this macro, nothing special is output at the
-     end of compilation, which is correct for most machines.
-
-`DBX_OUTPUT_SOURCE_FILENAME (STREAM, NAME)'
-     A C statement to output DBX debugging information to the stdio
-     stream STREAM which indicates that file NAME is the current source
-     file.  This output is generated each time input shifts to a
-     different source file as a result of `#include', the end of an
-     included file, or a `#line' command.
-
-     This macro need not be defined if the standard form of output for
-     DBX debugging information is appropriate.
-*/
-
-
-/* Macros for SDB and DWARF Output */
-
-/*
-`SDB_DEBUGGING_INFO'
-     Define this macro if GNU CC should produce COFF-style debugging
-     output for SDB in response to the `-g' option.
-
-`DWARF_DEBUGGING_INFO'
-     Define this macro if GNU CC should produce dwarf format debugging
-     output in response to the `-g' option.
-
-`PUT_SDB_...'
-     Define these macros to override the assembler syntax for the
-     special SDB assembler directives.  See `sdbout.c' for a list of
-     these macros and their arguments.  If the standard syntax is used,
-     you need not define them yourself.
-
-`SDB_DELIM'
-     Some assemblers do not support a semicolon as a delimiter, even
-     between SDB assembler directives.  In that case, define this macro
-     to be the delimiter to use (usually `\n').  It is not necessary to
-     define a new set of `PUT_SDB_OP' macros if this is the only change
-     required.
-
-`SDB_GENERATE_FAKE'
-     Define this macro to override the usual method of constructing a
-     dummy name for anonymous structure and union types.  See
-     `sdbout.c' for more information.
-
-`SDB_ALLOW_UNKNOWN_REFERENCES'
-     Define this macro to allow references to unknown structure, union,
-     or enumeration tags to be emitted.  Standard COFF does not allow
-     handling of unknown references, MIPS ECOFF has support for it.
-
-`SDB_ALLOW_FORWARD_REFERENCES'
-     Define this macro to allow references to structure, union, or
-     enumeration tags that have not yet been seen to be handled.  Some
-     assemblers choke if forward tags are used, while some require it.
-*/
-
-
-/* Miscellaneous Parameters  */
-
-/* Use the software emulation of floating point.  */
-#define REAL_ARITHMETIC
-
-/* Define this if you have defined special-purpose predicates in the
-   file `MACHINE.c'.  This macro is called within an initializer of an
-   array of structures.  The first field in the structure is the name
-   of a predicate and the second field is an array of rtl codes.  For
-   each predicate, list all rtl codes that can be in expressions
-   matched by the predicate.  The list should have a trailing comma.  */
-
-#define PREDICATE_CODES							\
-{ "short_memory_operand",	{ MEM }},				\
-{ "reg_or_0_operand",		{ REG, SUBREG, CONST_INT }},		\
-{ "arith16_operand",		{ REG, SUBREG, CONST_INT }},		\
-{ "arith32_operand",		{ REG, SUBREG, CONST_INT }},		\
-{ "arith64_operand",		{ REG, SUBREG, CONST_INT, CONST_DOUBLE }}, \
-{ "arith_4bit_operand",		{ REG, SUBREG, CONST_INT }},		\
-{ "arith_lower0_operand",	{ REG, SUBREG, CONST_INT }},		\
-{ "arith_nonnegative_operand",	{ REG, SUBREG, CONST_INT }},		\
-{ "gpr_operand",		{ REG, SUBREG }},			\
-{ "accum_operand",		{ REG, SUBREG }},			\
-{ "ldi_shift_operand",		{ CONST_INT }},				\
-{ "cond_move_operand",		{ REG, SUBREG, CONST_INT, MEM }},	\
-{ "cond_exec_operand",		{ REG, SUBREG, CONST_INT, MEM }},	\
-{ "pc_or_label_operand",	{ PC, LABEL_REF }},			\
-{ "carry_operand",		{ REG }},				\
-{ "f0_operand",			{ REG }},				\
-{ "f1_operand",			{ REG }},				\
-{ "f_operand",			{ REG }},				\
-{ "carry_operand",		{ REG }},				\
-{ "f0_compare_operator",	{ EQ, NE }},				\
-{ "compare_operator",		{ EQ, NE, GT, GE, GTU, GEU, LT, LE,	\
-				  LTU, LEU }},				\
-{ "equality_operator",		{ EQ, NE, GT, GE, GTU, GEU, LT, LE,	\
-				  LTU, LEU }},				\
-{ "unsigned_compare_operator",	{ EQ, NE, GT, GE, GTU, GEU, LT, LE,	\
-				  LTU, LEU }},				\
-{ "signed_compare_operator",	{ EQ, NE, GT, GE, GTU, GEU, LT, LE,	\
-				  LTU, LEU }},				\
-{ "unary_parallel_operator",	{ ABS, NEG, NOT, REG, SUBREG,		\
-				  CONST_INT, MEM,			\
-				  SIGN_EXTEND, ZERO_EXTEND  }},		\
-{ "binary_parallel_operator",	{ PLUS, MINUS, MULT,			\
-				  AND, IOR, XOR,			\
-				  ASHIFT, ASHIFTRT, LSHIFTRT }},	\
-{ "extend_parallel_operator",	{ SIGN_EXTEND, ZERO_EXTEND }},		\
-{ "minmax_parallel_operator",	{ SMIN, SMAX }},
-
-/* An alias for a machine mode name.  This is the machine mode that
-   elements of a jump-table should have.  */
-#define CASE_VECTOR_MODE Pmode
-
-/*
-`CASE_VECTOR_PC_RELATIVE'
-     Define this macro if jump-tables should contain relative addresses.
-
-`CASE_DROPS_THROUGH'
-     Define this if control falls through a `case' insn when the index
-     value is out of range.  This means the specified default-label is
-     actually ignored by the `case' insn proper.
-
-`CASE_VALUES_THRESHOLD'
-     Define this to be the smallest number of different values for
-     which it is best to use a jump-table instead of a tree of
-     conditional branches.  The default is four for machines with a
-     `casesi' instruction and five otherwise.  This is best for most
-     machines.
-*/
-
-/* Define this macro if operations between registers with integral
-   mode smaller than a word are always performed on the entire
-   register.  Most RISC machines have this property and most CISC
-   machines do not. */
-#define WORD_REGISTER_OPERATIONS 1
-
-/* Define this macro to be a C expression indicating when insns that
-   read memory in MODE, an integral mode narrower than a word, set the
-   bits outside of MODE to be either the sign-extension or the
-   zero-extension of the data read.  Return `SIGN_EXTEND' for values
-   of MODE for which the insn sign-extends, `ZERO_EXTEND' for which
-   it zero-extends, and `NIL' for other modes.
-
-   This macro is not called with MODE non-integral or with a width
-   greater than or equal to `BITS_PER_WORD', so you may return any
-   value in this case.  Do not define this macro if it would always
-   return `NIL'.  On machines where this macro is defined, you will
-   normally define it as the constant `SIGN_EXTEND' or `ZERO_EXTEND'.  */
-#define LOAD_EXTEND_OP(MODE) (((MODE) == QImode) ? ZERO_EXTEND : NIL)
-
-/* An alias for a tree code that should be used by default for
-   conversion of floating point values to fixed point.  Normally,
-   `FIX_ROUND_EXPR' is used.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-
-/* Define this macro if the same instructions that convert a floating
-   point number to a signed fixed point number also convert validly
-   to an unsigned one.  */
-/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
-
-
-/* An alias for a tree code that is the easiest kind of division to
-     compile code for in the general case.  It may be `TRUNC_DIV_EXPR',
-     `FLOOR_DIV_EXPR', `CEIL_DIV_EXPR' or `ROUND_DIV_EXPR'.  These four
-     division operators differ in how they round the result to an
-     integer.  `EASY_DIV_EXPR' is used when it is permissible to use
-     any of those kinds of division and the choice should be made on
-     the basis of efficiency. */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* The maximum number of bytes that a single instruction can move
-   quickly from memory to memory.  */
-#define MOVE_MAX 4
-
-
-/* The maximum number of bytes that a single instruction can move
-   quickly from memory to memory.  If this is undefined, the default
-   is `MOVE_MAX'.  Otherwise, it is the constant value that is the
-   largest value that `MOVE_MAX' can have at run-time.  */
-/* #define MAX_MOVE_MAX */
-
-/*
-`SHIFT_COUNT_TRUNCATED'
-     A C expression that is nonzero if on this machine the number of
-     bits actually used for the count of a shift operation is equal to
-     the number of bits needed to represent the size of the object
-     being shifted.  When this macro is non-zero, the compiler will
-     assume that it is safe to omit a sign-extend, zero-extend, and
-     certain bitwise `and' instructions that truncates the count of a
-     shift operation.  On machines that have instructions that act on
-     bitfields at variable positions, which may include `bit test'
-     instructions, a nonzero `SHIFT_COUNT_TRUNCATED' also enables
-     deletion of truncations of the values that serve as arguments to
-     bitfield instructions.
-
-     If both types of instructions truncate the count (for shifts) and
-     position (for bitfield operations), or if no variable-position
-     bitfield instructions exist, you should define this macro.
-
-     However, on some machines, such as the 80386 and the 680x0,
-     truncation only applies to shift operations and not the (real or
-     pretended) bitfield operations.  Define `SHIFT_COUNT_TRUNCATED' to
-     be zero on such machines.  Instead, add patterns to the `md' file
-     that include the implied truncation of the shift instructions.
-
-     You need not define this macro if it would always have the value
-     of zero.
-*/
-
-/* A C expression which is nonzero if on this machine it is safe to
-   "convert" an integer of INPREC bits to one of OUTPREC bits (where
-   OUTPREC is smaller than INPREC) by merely operating on it as if it
-   had only OUTPREC bits.
-
-   On many machines, this expression can be 1.
-
-   When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for
-   modes for which `MODES_TIEABLE_P' is 0, suboptimal code can result.
-   If this is the case, making `TRULY_NOOP_TRUNCATION' return 0 in
-   such cases may improve things.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-
-/* A C expression describing the value returned by a comparison
-   operator with an integral mode and stored by a store-flag
-   instruction (`sCOND') when the condition is true.  This
-   description must apply to *all* the `sCOND' patterns and all the
-   comparison operators whose results have a `MODE_INT' mode.
-
-   A value of 1 or -1 means that the instruction implementing the
-   comparison operator returns exactly 1 or -1 when the comparison is
-   true and 0 when the comparison is false.  Otherwise, the value
-   indicates which bits of the result are guaranteed to be 1 when the
-   comparison is true.  This value is interpreted in the mode of the
-   comparison operation, which is given by the mode of the first
-   operand in the `sCOND' pattern.  Either the low bit or the sign
-   bit of `STORE_FLAG_VALUE' be on.  Presently, only those bits are
-   used by the compiler.
-
-   If `STORE_FLAG_VALUE' is neither 1 or -1, the compiler will
-   generate code that depends only on the specified bits.  It can also
-   replace comparison operators with equivalent operations if they
-   cause the required bits to be set, even if the remaining bits are
-   undefined.  For example, on a machine whose comparison operators
-   return an `SImode' value and where `STORE_FLAG_VALUE' is defined as
-   `0x80000000', saying that just the sign bit is relevant, the
-   expression
-
-          (ne:SI (and:SI X (const_int POWER-OF-2)) (const_int 0))
-
-   can be converted to
-
-          (ashift:SI X (const_int N))
-
-   where N is the appropriate shift count to move the bit being
-   tested into the sign bit.
-
-   There is no way to describe a machine that always sets the
-   low-order bit for a true value, but does not guarantee the value
-   of any other bits, but we do not know of any machine that has such
-   an instruction.  If you are trying to port GNU CC to such a
-   machine, include an instruction to perform a logical-and of the
-   result with 1 in the pattern for the comparison operators and let
-   us know (*note How to Report Bugs: Bug Reporting.).
-     
-   Often, a machine will have multiple instructions that obtain a
-   value from a comparison (or the condition codes).  Here are rules
-   to guide the choice of value for `STORE_FLAG_VALUE', and hence the
-   instructions to be used:
-
-        * Use the shortest sequence that yields a valid definition for
-          `STORE_FLAG_VALUE'.  It is more efficient for the compiler to
-          "normalize" the value (convert it to, e.g., 1 or 0) than for
-          the comparison operators to do so because there may be
-          opportunities to combine the normalization with other
-          operations.
-
-        * For equal-length sequences, use a value of 1 or -1, with -1
-          being slightly preferred on machines with expensive jumps and
-          1 preferred on other machines.
-
-        * As a second choice, choose a value of `0x80000001' if
-          instructions exist that set both the sign and low-order bits
-          but do not define the others.
-
-        * Otherwise, use a value of `0x80000000'.
-
-   Many machines can produce both the value chosen for
-   `STORE_FLAG_VALUE' and its negation in the same number of
-   instructions.  On those machines, you should also define a pattern
-   for those cases, e.g., one matching
-
-          (set A (neg:M (ne:M B C)))
-
-   Some machines can also perform `and' or `plus' operations on
-   condition code values with less instructions than the corresponding
-   `sCOND' insn followed by `and' or `plus'.  On those machines,
-   define the appropriate patterns.  Use the names `incscc' and
-   `decscc', respectively, for the patterns which perform `plus' or
-   `minus' operations on condition code values.  See `rs6000.md' for
-   some examples.  The GNU Superoptizer can be used to find such
-   instruction sequences on other machines.
-
-   You need not define `STORE_FLAG_VALUE' if the machine has no
-   store-flag instructions.  */
-#define STORE_FLAG_VALUE 1
-
-/*
-`FLOAT_STORE_FLAG_VALUE'
-     A C expression that gives a non-zero floating point value that is
-     returned when comparison operators with floating-point results are
-     true.  Define this macro on machine that have comparison
-     operations that return floating-point values.  If there are no
-     such operations, do not define this macro.
-*/
-
-/* An alias for the machine mode for pointers.  On most machines,
-   define this to be the integer mode corresponding to the width of a
-   hardware pointer; `SImode' on 32-bit machine or `DImode' on 64-bit
-   machines.  On some machines you must define this to be one of the
-   partial integer modes, such as `PSImode'.
-
-   The width of `Pmode' must be at least as large as the value of
-   `POINTER_SIZE'.  If it is not equal, you must define the macro
-   `POINTERS_EXTEND_UNSIGNED' to specify how pointers are extended to
-   `Pmode'.  */
-#define Pmode HImode
-
-/* An alias for the machine mode used for memory references to
-   functions being called, in `call' RTL expressions.  On most
-   machines this should be `QImode'.  */
-#define FUNCTION_MODE Pmode
-
-/*
-`INTEGRATE_THRESHOLD (DECL)'
-     A C expression for the maximum number of instructions above which
-     the function DECL should not be inlined.  DECL is a
-     `FUNCTION_DECL' node.
-
-     The default definition of this macro is 64 plus 8 times the number
-     of arguments that the function accepts.  Some people think a larger
-     threshold should be used on RISC machines.
-
-`SCCS_DIRECTIVE'
-     Define this if the preprocessor should ignore `#sccs' directives
-     and print no error message.
-
-`NO_IMPLICIT_EXTERN_C'
-     Define this macro if the system header files support C++ as well
-     as C.  This macro inhibits the usual method of using system header
-     files in C++, which is to pretend that the file's contents are
-     enclosed in `extern "C" {...}'.
-
-`HANDLE_PRAGMA (STREAM, NODE)'
-     Define this macro if you want to implement any pragmas.  If
-     defined, it is a C expression whose value is 1 if the pragma was
-     handled by the function.  The argument STREAM is the stdio input
-     stream from which the source text can be read.  NODE is the tree
-     node for the identifier after the `#pragma'.
-
-     It is generally a bad idea to implement new uses of `#pragma'.  The
-     only reason to define this macro is for compatibility with other
-     compilers that do support `#pragma' for the sake of any user
-     programs which already use it.
-
-`VALID_MACHINE_DECL_ATTRIBUTE (DECL, ATTRIBUTES, IDENTIFIER, ARGS)'
-     If defined, a C expression whose value is nonzero if IDENTIFIER
-     with arguments ARGS is a valid machine specific attribute for DECL.
-     The attributes in ATTRIBUTES have previously been assigned to DECL.
-
-`VALID_MACHINE_TYPE_ATTRIBUTE (TYPE, ATTRIBUTES, IDENTIFIER, ARGS)'
-     If defined, a C expression whose value is nonzero if IDENTIFIER
-     with arguments ARGS is a valid machine specific attribute for TYPE.
-     The attributes in ATTRIBUTES have previously been assigned to TYPE.
-
-`COMP_TYPE_ATTRIBUTES (TYPE1, TYPE2)'
-     If defined, a C expression whose value is zero if the attributes on
-     TYPE1 and TYPE2 are incompatible, one if they are compatible, and
-     two if they are nearly compatible (which causes a warning to be
-     generated).
-
-`SET_DEFAULT_TYPE_ATTRIBUTES (TYPE)'
-     If defined, a C statement that assigns default attributes to newly
-     defined TYPE.
-
-`MERGE_MACHINE_TYPE_ATTRIBUTES (TYPE1, TYPE2)'
-     Define this macro if the merging of type attributes needs special
-     handling.  If defined, the result is a list of the combined
-     TYPE_ATTRIBUTES of TYPE1 and TYPE2.  It is assumed that comptypes
-     has already been called and returned 1.
-
-`MERGE_MACHINE_DECL_ATTRIBUTES (OLDDECL, NEWDECL)'
-     Define this macro if the merging of decl attributes needs special
-     handling.  If defined, the result is a list of the combined
-     DECL_MACHINE_ATTRIBUTES of OLDDECL and NEWDECL.  NEWDECL is a
-     duplicate declaration of OLDDECL.  Examples of when this is needed
-     are when one attribute overrides another, or when an attribute is
-     nullified by a subsequent definition.
-
-`DOLLARS_IN_IDENTIFIERS'
-     Define this macro to control use of the character `$' in identifier
-     names.  The value should be 0, 1, or 2.  0 means `$' is not allowed
-     by default; 1 means it is allowed by default if `-traditional' is
-     used; 2 means it is allowed by default provided `-ansi' is not
-     used.  1 is the default; there is no need to define this macro in
-     that case.
-
-`NO_DOLLAR_IN_LABEL'
-     Define this macro if the assembler does not accept the character
-     `$' in label names.  By default constructors and destructors in
-     G++ have `$' in the identifiers.  If this macro is defined, `.' is
-     used instead.
-
-`NO_DOT_IN_LABEL'
-     Define this macro if the assembler does not accept the character
-     `.' in label names.  By default constructors and destructors in G++
-     have names that use `.'.  If this macro is defined, these names
-     are rewritten to avoid `.'.
-
-`DEFAULT_MAIN_RETURN'
-     Define this macro if the target system expects every program's
-     `main' function to return a standard "success" value by default
-     (if no other value is explicitly returned).
-
-     The definition should be a C statement (sans semicolon) to
-     generate the appropriate rtl instructions.  It is used only when
-     compiling the end of `main'.
-
-`HAVE_ATEXIT'
-     Define this if the target system supports the function `atexit'
-     from the ANSI C standard.  If this is not defined, and
-     `INIT_SECTION_ASM_OP' is not defined, a default `exit' function
-     will be provided to support C++.
-
-`EXIT_BODY'
-     Define this if your `exit' function needs to do something besides
-     calling an external function `_cleanup' before terminating with
-     `_exit'.  The `EXIT_BODY' macro is only needed if netiher
-     `HAVE_ATEXIT' nor `INIT_SECTION_ASM_OP' are defined.
-
-`INSN_SETS_ARE_DELAYED (INSN)'
-     Define this macro as a C expression that is nonzero if it is safe
-     for the delay slot scheduler to place instructions in the delay
-     slot of INSN, even if they appear to use a resource set or
-     clobbered in INSN.  INSN is always a `jump_insn' or an `insn'; GNU
-     CC knows that every `call_insn' has this behavior.  On machines
-     where some `insn' or `jump_insn' is really a function call and
-     hence has this behavior, you should define this macro.
-
-     You need not define this macro if it would always return zero.
-
-`INSN_REFERENCES_ARE_DELAYED (INSN)'
-     Define this macro as a C expression that is nonzero if it is safe
-     for the delay slot scheduler to place instructions in the delay
-     slot of INSN, even if they appear to set or clobber a resource
-     referenced in INSN.  INSN is always a `jump_insn' or an `insn'.
-     On machines where some `insn' or `jump_insn' is really a function
-     call and its operands are registers whose use is actually in the
-     subroutine it calls, you should define this macro.  Doing so
-     allows the delay slot scheduler to move instructions which copy
-     arguments into the argument registers into the delay slot of INSN.
-
-     You need not define this macro if it would always return zero.
-
-`MACHINE_DEPENDENT_REORG (INSN)'
-     In rare cases, correct code generation requires extra machine
-     dependent processing between the second jump optimization pass and
-     delayed branch scheduling.  On those machines, define this macro
-     as a C statement to act on the code starting at INSN.
-*/
-
-
-/* Hack to omit compiling L_shtab in libgcc2.  Shtab is an array mapping
-   n -> 1<<n that is used in the Tahoe, but it assumes that int can handle
-   32-bits.  */
-
-#undef L_shtab
-
-
-/* Haifa scheduler options */
-
-/* uncomment for disabling the corresponding default options */
-/* #define  MACHINE_no_sched_interblock */
-/* #define  MACHINE_no_sched_speculative */
-/* #define  MACHINE_no_sched_speculative_load */
-
-/* indicate that issue rate is defined for this machine
-   (no need to use the default) */
-#define ISSUE_RATE 2
-
-
-/* External functions which don't have a proper prototype.  */
-extern int offsettable_memref_p ();
-
-/* External data */
-extern int optimize;
-
-/* Variables to hold compare operators until the appropriate branch or scc
-   operation is done.  */
-extern struct rtx_def *compare_op0;
-extern struct rtx_def *compare_op1;
-
-/* Functions defined in d10v.c  */
-#define Rtx struct rtx_def *
-
-extern void override_options ();
-extern void encode_section_info ();
-extern int  short_memory_operand ();
-extern int  reg_or_0_operand ();
-extern int  arith16_operand ();
-extern int  arith32_operand ();
-extern int  arith64_operand ();
-extern int  arith_4bit_operand ();
-extern int  arith_lower0_operand ();
-extern int  arith_nonnegative_operand ();
-extern int  gpr_operand ();
-extern int  accum_operand ();
-extern int  ldi_shift_operand ();
-extern int  cond_move_operand ();
-extern int  cond_exec_operand ();
-extern int  pc_or_label_operand ();
-extern int  f0_operand ();
-extern int  f1_operand ();
-extern int  f_operand ();
-extern int  carry_operand ();
-extern int  f0_compare_operator ();
-extern int  compare_operator ();
-extern int  equality_operator ();
-extern int  signed_compare_operator ();
-extern int  unsigned_compare_operator ();
-extern int  unary_parallel_operator ();
-extern int  binary_parallel_operator ();
-extern int  extend_parallel_operator ();
-extern int  parallel_ldi ();
-extern int  adjacent_memory_operands ();
-extern void d10v_expand_divmod ();
-extern void initialize_trampoline ();
-extern int  emit_comparison ();
-extern int  select_cc_mode ();
-extern Rtx  expand_comparison ();
-extern char *emit_move_word ();
-extern char *emit_move_2words ();
-extern char *emit_move_4words ();
-extern char *emit_add ();
-extern char *emit_subtract ();
-extern char *emit_cond_move ();
-extern Rtx  d10v_split_logical_op ();
-extern void d10v_output_addr_const ();
-extern void print_operand ();
-extern void print_operand_address ();
-extern void init_cumulative_args ();
-extern Rtx  function_arg ();
-extern int  function_arg_partial_nregs ();
-extern int  function_arg_pass_by_reference ();
-extern int  function_arg_callee_copies ();
-extern void function_arg_advance ();
-extern int  function_arg_boundary ();
-extern void setup_incoming_varargs ();
-extern struct rtx_def *expand_builtin_saveregs ();
-extern int  d10v_legitimate_address_p ();
-extern Rtx  d10v_legitimize_address ();
-extern int  d10v_mode_dependent_address_p ();
-extern Rtx  d10v_subword_mode ();
-extern Rtx  d10v_subword ();
-extern int  direct_return ();
-extern void function_prologue ();
-extern void function_epilogue ();
-extern d10v_stack_t *d10v_stack_info ();
-/* END CYGNUS LOCAL -- meissner/d10v abi change */
diff --git a/gcc/config/d10v/d10v.md b/gcc/config/d10v/d10v.md
deleted file mode 100755
index 4999d87..0000000
--- a/gcc/config/d10v/d10v.md
+++ /dev/null
@@ -1,3758 +0,0 @@
-;; CYGNUS LOCAL -- meissner/d10v abi change
-;; Machine description for Mitsubishi D10V for GNU C compiler
-;; Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-;; Contributed by Cygnus Support.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; Machine dependent register classes used:
-;;	'C'	CARRY_REGS
-;;	'a'	ACCUM_REGS
-;;	'b'	R2_REGS
-;;	'c'	CR_REGS
-;;	'd'	GENERAL_REGS
-;;	'e'	EVEN_REGS
-;;	'f'	F0_REGS
-;;	'h'	R3_REGS
-;;	'j'	R4_REGS
-;;	'l'	R13_REGS
-;;	'q'	R5_REGS
-;;	'x'	CC_REGS
-;;	'y'	F1_REGS
-;;	'z'	REPEAT_REGS
-
-
-;; Function unit attributes
-;; Note, we lie a little bit here to make it simpler to optimize.  We pretend there
-;; is a separate long functional unit for long instructions that uses both the IU & MU.
-(define_attr "type" "iu,mu,either,long,unknown"
-  (const_string "unknown"))
-
-;; Length in word units
-(define_attr "length" ""
-  (if_then_else (eq_attr "type" "long,unknown")
-		(const_int 2)
-		(const_int 1)))
-
-;; (define_function_unit NAME MULTIPLICITY SIMULTANEITY TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
-(define_function_unit "iu" 1 1
-  (and (eq_attr "type" "iu,either")
-       (eq_attr "length" "1"))
-  2 2
-  [(eq_attr "type" "long,unknown")])
-
-(define_function_unit "mu" 1 1
-  (and (eq_attr "type" "mu,either")
-       (eq_attr "length" "1"))
-  2 2
-  [(eq_attr "type" "long,unknown")])
-
-(define_function_unit "long" 1 1
-  (eq_attr "type" "long,unknown")
-  2 2
-  [(and (eq_attr "type" "iu,mu,either")
-	(eq_attr "length" "1"))])
-
-(define_function_unit "long" 1 1
-  (not (eq_attr "length" "1"))
-  2 2
-  [(and (eq_attr "type" "iu,mu,either")
-	(eq_attr "length" "1"))])
-
-
-
-;;  ....................
-;;
-;;	Move operations
-;;
-;;  ....................
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) != REG
-      && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
-    operands[1] = force_reg (QImode, operands[1]);
-}")
-
-(define_insn "*movqi_internal"
-  [(set (match_operand:QI 0 "general_operand" "=d,d,d,Q,m,d,d,Q,m")
-	(match_operand:QI 1 "general_operand"  "d,Q,m,d,d,L,i,O,O"))]
-  "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)
-   || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)"
-  "@
-  mv %0,%1
-  ldub %0,%M1
-  ldub %0,%M1
-  stb %1,%M0
-  stb %1,%M0
-  ldi %0,%1
-  ldi %0,%1
-  stb %.,%M0
-  stb %.,%M0"
-  [(set_attr "type" "either,mu,long,mu,long,either,mu,mu,mu")
-   (set_attr "length" "1,1,2,1,2,1,2,1,2")])
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) != REG
-      && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
-      && ! reload_in_progress)
-    operands[1] = force_reg (HImode, operands[1]);
-}")
-
-(define_insn "*movhi_internal"
-  [(set (match_operand:HI 0 "general_operand" "=d,d,d,Q,m,c,d,d,d,Q,m")
-	(match_operand:HI 1 "general_operand"  "d,Q,m,d,d,d,c,L,i,O,O"))]
-  "register_operand (operands[0], HImode) || register_operand (operands[1], HImode)
-   || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)"
-  "* return emit_move_word (operands[0], operands[1], insn);"
-  [(set_attr "type" "either,mu,long,mu,long,mu,mu,either,mu,mu,mu")
-   (set_attr "length" "1,1,2,1,2,1,1,1,2,1,2")])
-
-;; Split constants that we can into a small ldi and a shift.  This may seem
-;; counter intuitive to replace one instruction by two, but the reasoning is
-;; that it helps avoid nops caused by the long form of ldi and is the same
-;; space if no nops where needed, and also allows such constants to be set up
-;; with conditional execution.
-
-(define_split
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(match_operand:HI 1 "ldi_shift_operand" ""))]
-  ""
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (ashift:HI (match_dup 0) (match_dup 3)))]
-  "
-{
-  int shift = ldi_shift_operand (operands[1], HImode);
-  operands[2] = GEN_INT (INTVAL (operands[1]) >> shift);
-  operands[3] = GEN_INT (shift);
-}")
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) != REG)
-    operands[1] = force_reg (SImode, operands[1]);
-  /* reload might ask us to use something like (subreg:SI (reg/v:DI 0 r0) 1) .
-     Example: unsorted/dilayout.c -O1 */
-  if (reload_in_progress)
-    {
-      int reg0 = true_regnum (operands[0]);
-      int reg1 = true_regnum (operands[1]);
-
-      if ((reg0 >= 0 && reg0 < FIRST_PSEUDO_REGISTER && (reg0 & 1))
-	  || (reg1 >= 0 && reg1 < FIRST_PSEUDO_REGISTER && (reg1 & 1)))
-	{
-	  rtx high, low;
-	  int word0 = 0, word1 = 0;
-
-	  if (GET_CODE (operands[0]) == SUBREG)
-	    {
-	      word0 = SUBREG_WORD (operands[0]);
-	      operands[0] = SUBREG_REG (operands[0]);
-	    }
-	  if (GET_CODE (operands[1]) == SUBREG)
-	    {
-	      word1 = SUBREG_WORD (operands[1]);
-	      operands[1] = SUBREG_REG (operands[1]);
-	    }
-	  high = gen_movhi (gen_rtx (SUBREG, HImode, operands[0], word0),
-			    gen_rtx (SUBREG, HImode, operands[1], word1));
-	  operands[0] = copy_rtx (operands[0]);
-	  operands[1] = copy_rtx (operands[1]);
-	  low = gen_movhi (gen_rtx (SUBREG, HImode, operands[0], word0 + 1),
-			   gen_rtx (SUBREG, HImode, operands[1], word1 + 1));
-	  /* Check for overlap.  We know this is big endian.  */
-	  if (reg0 == reg1 + 1)
-	    {
-	      emit_insn (low);
-	      emit_insn (high);
-	    }
-	  else
-	    {
-	      emit_insn (high);
-	      emit_insn (low);
-	    }
-	  DONE;
-	}
-    }
-}")
-
-(define_insn "*movsi_internal"
-  [(set (match_operand:SI 0 "general_operand" "=e,e,e,Q,m,a,a,e,e,a")
-	(match_operand:SI 1 "general_operand" "e,Q,m,e,e,e,a,a,i,O"))]
-  "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
-  "* return emit_move_2words (operands[0], operands[1], insn);"
-  [(set_attr "type" "either,mu,long,mu,long,mu,iu,mu,long,iu")
-   (set_attr "length" "1,1,2,1,2,1,1,1,4,1")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operand:SI 1 "const_int_operand" ""))]
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (match_dup 5))]
-  "
-{
-  operands[2] = d10v_subword (operands[0], 0, HImode, SImode);
-  operands[3] = d10v_subword (operands[0], 1, HImode, SImode);
-  operands[4] = GEN_INT (SIGN_EXTEND_SHORT (INTVAL (operands[1]) >> 16));
-  operands[5] = GEN_INT (SIGN_EXTEND_SHORT (INTVAL (operands[1])));
-}")
-
-(define_insn "reload_insi"
-  [(set (match_operand:SI 0 "register_operand" "=a,a")
-	(match_operand:SI 1 "memory_operand" "Q,m"))
-   (clobber (match_operand:SI 2 "gpr_operand" "=e,e"))]
-  "TARGET_ACCUM"
-  "#"
-  [(set_attr "type" "long,long")
-   (set_attr "length" "2,3")])
-
-(define_insn "reload_outsi"
-  [(set (match_operand:SI 0 "memory_operand" "=Q,m")
-	(match_operand:SI 1 "accum_operand" "a,a"))
-   (clobber (match_operand:SI 2 "gpr_operand" "=&e,e"))]
-  "TARGET_ACCUM"
-  "#"
-  [(set_attr "type" "long,long")
-   (set_attr "length" "2,3")])
-
-(define_split
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))
-   (clobber (match_operand:SI 2 "gpr_operand" ""))]
-  "TARGET_ACCUM && reload_completed"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (match_dup 2))]
-  "")
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) != REG)
-    operands[1] = force_reg (SFmode, operands[1]);
-}")
-
-(define_insn "*movsf_internal"
-  [(set (match_operand:SF 0 "general_operand" "=e,e,e,Q,m,e")
-	(match_operand:SF 1 "general_operand" "e,Q,m,e,e,F"))]
-  "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)"
-  "* return emit_move_2words (operands[0], operands[1], insn);"
-  [(set_attr "type" "either,mu,long,mu,long,long")
-   (set_attr "length" "1,1,2,1,2,4")])
-
-(define_split
-  [(set (match_operand:SF 0 "gpr_operand" "")
-	(match_operand:SF 1 "const_double_operand" ""))]
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (match_dup 5))]
-  "
-{
-  REAL_VALUE_TYPE rv;
-  HOST_WIDE_INT value;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-  REAL_VALUE_TO_TARGET_SINGLE (rv, value);
-
-  operands[2] = d10v_subword (operands[0], 0, HImode, SFmode);
-  operands[3] = d10v_subword (operands[0], 1, HImode, SFmode);
-  operands[4] = GEN_INT (SIGN_EXTEND_SHORT (value >> 16));
-  operands[5] = GEN_INT (SIGN_EXTEND_SHORT (value));
-}")
-
-(define_expand "movdi"
-  [(parallel [(set (match_operand:DI 0 "general_operand" "")
-		   (match_operand:DI 1 "general_operand" ""))
-	      (clobber (match_scratch:SI 2 ""))
-	      (clobber (match_scratch:HI 3 ""))])]
-  ""
-  "")
-
-(define_insn "*movdi_internal"
-  [(set (match_operand:DI 0 "general_operand" "=e,e,o,e,o,o,o,??o,??o")
-	(match_operand:DI 1 "general_operand" "e,o,e,iF,o,OG,iF,o,o"))
-   (clobber (match_scratch:SI 2 "=X,X,X,X,&e,X,&e,X,e"))
-   (clobber (match_scratch:HI 3 "=X,X,X,X,X,X,X,&d,X"))]
-  ""
-  "* return emit_move_4words (operands[0], operands[1], operands[2], operands[3], insn);"
-  [(set_attr "type" "long,long,long,long,long,long,long,long,long")
-   (set_attr "length" "4,4,4,4,8,8,16,32,32")])
-
-(define_expand "movdf"
-  [(parallel [(set (match_operand:DF 0 "general_operand" "")
-		   (match_operand:DF 1 "general_operand" ""))
-	      (clobber (match_scratch:SI 2 ""))
-	      (clobber (match_scratch:HI 3 ""))])]
-  ""
-  "")
-
-(define_insn "*movdf_internal"
-  [(set (match_operand:DF 0 "general_operand" "=e,e,o,e,o,o,o,??o,??o")
-	(match_operand:DF 1 "general_operand" "e,o,e,iF,o,OG,F,o,o"))
-   (clobber (match_scratch:SI 2 "=X,X,X,X,&e,X,&e,X,e"))
-   (clobber (match_scratch:HI 3 "=X,X,X,X,X,X,X,&d,X"))]
-  ""
-  "* return emit_move_4words (operands[0], operands[1], operands[2], operands[3], insn);"
-  [(set_attr "type" "long,long,long,long,long,long,long,long,long")
-   (set_attr "length" "4,4,4,4,8,8,16,32,32")])
-
-(define_insn "movcc"
-  [(set (match_operand:CC 0 "general_operand" "=x")
-	(match_operand:CC 1 "general_operand" "x"))]
-  ""
-  "cpfg %0,%1"
-  [(set_attr "type" "mu")
-   (set_attr "length" "1")])
-
-
-;;  ....................
-;;
-;;	Unconditional branch, return, and case table
-;;
-;;  ....................
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "bra %l0"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-;; Note, do not list a dependency on r13, since jump.c currently can't handle a parallel
-;; operation.
-(define_expand "return"
-  [(return)]
-  "direct_return ()"
-  "")
-
-(define_insn "*return_1"
-  [(return)]
-  "direct_return () && (d10v_stack_info ())->total_size == 0"
-  "*
-{
-  operands[0] = gen_rtx (REG, Pmode, RETURN_ADDRESS_REGNUM);
-  return \"jmp %0\";
-}"
-  [(set_attr "type" "mu")
-   (set_attr "length" "1")])
-
-(define_insn "*return_2"
-  [(return)]
-  "direct_return () && (d10v_stack_info ())->total_size != 0"
-  "*
-{
-  d10v_stack_t *info = d10v_stack_info ();
-
-  operands[0] = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
-  operands[1] = gen_rtx (REG, Pmode, RETURN_ADDRESS_REGNUM);
-  if (info->total_size == UNITS_PER_WORD && info->save_p[RETURN_ADDRESS_REGNUM])
-    return \"ld %1,@%0+\;jmp %1\";
-
-  else if (info->total_size == info->vars_size
-	   && IN_RANGE_P (info->total_size, 1, 16))
-    {
-      operands[2] = GEN_INT (info->total_size);
-      return \"addi %0,%2\;jmp %1\";
-    }
-
-  else
-    fatal_insn (\"return_2 unexpected return stack\", insn);
-
-  return \"\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:HI 0 "gpr_operand" "d"))]
-  ""
-  "jmp %0"
-  [(set_attr "type" "mu")
-   (set_attr "length" "1")])
-
-;; No operation
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-;; Table jump for switch statements:
-(define_insn "tablejump"
-  [(set (pc) (match_operand:HI 0 "gpr_operand" "d"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmp %0"
-  [(set_attr "type" "mu")
-   (set_attr "length" "1")])
-
-
-;;  ....................
-;;
-;;	Calls
-;;
-;;  ....................
-
-(define_expand "call"
-  [(parallel [(call (match_operand 0 "memory_operand" "")
-		    (match_operand 1 "" ""))
-	      (clobber (match_scratch:HI 2 "=l"))])]
-  ""
-  "
-{
-  rtx addr;
-
-  addr = XEXP (operands[0], 0);
-  if (GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
-    {
-      rtx reg = gen_reg_rtx (Pmode);
-      emit_move_insn (reg, addr);
-      operands[0] = gen_rtx (MEM, FUNCTION_MODE, reg);
-    }
-}")
-
-(define_insn "*call_internal1"
-  [(call (match_operand 0 "memory_operand" "m")
-	 (match_operand 1 "" "i"))
-   (clobber (match_scratch:HI 2 "=l"))]			;; return address, r13
-  "GET_CODE (XEXP (operands[0], 0)) == REG"
-  "jl %0"
-  [(set_attr "type" "mu")
-   (set_attr "length" "1")])
-
-(define_insn "*call_internal2"
-  [(call (match_operand 0 "memory_operand" "m")
-	 (match_operand 1 "" "i"))
-   (clobber (match_scratch:HI 2 "=l"))]			;; return address, r13
-  "CONSTANT_ADDRESS_P (XEXP (operands[0], 0))"
-  "bl %0"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_expand "call_value"
-  [(parallel [(set (match_operand 0 "gpr_operand" "")
-		   (call (match_operand 1 "memory_operand" "m")
-			 (match_operand 2 "" "i")))
-	      (clobber (match_scratch:HI 3 "=l"))])]
-  ""
-  "
-{
-  rtx addr;
-
-  addr = XEXP (operands[1], 0);
-  if (GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
-    {
-      rtx reg = gen_reg_rtx (Pmode);
-      emit_move_insn (reg, addr);
-      operands[1] = gen_rtx (MEM, FUNCTION_MODE, reg);
-    }
-}")
-
-(define_insn "*call_value_internal1"
-  [(set (match_operand 0 "gpr_operand" "=e")
-	(call (match_operand 1 "memory_operand" "m")
-	      (match_operand 2 "" "i")))
-   (clobber (match_scratch:HI 3 "=l"))]			;; return address, r13
-  "GET_CODE (XEXP (operands[1], 0)) == REG"
-  "jl %1"
-  [(set_attr "type" "mu")
-   (set_attr "length" "1")])
-
-(define_insn "*call_value_internal2"
-  [(set (match_operand 0 "gpr_operand" "=e")
-	(call (match_operand 1 "memory_operand" "m")
-	      (match_operand 2 "" "i")))
-   (clobber (match_scratch:HI 3 "=l"))]			;; return address, r13
-  "CONSTANT_ADDRESS_P (XEXP (operands[1], 0))"
-  "bl %1"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-
-;;
-;;  ....................
-;;
-;;	Comparisons
-;;
-;;  ....................
-
-;; Flow here is rather complex:
-;;
-;;  1)	The cmp{hi,si,di,sf,df} routine is called.  It deposits the
-;;	arguments into global variables, and the type into
-;;	branch_type.  No RTL is generated.
-;;
-;;  2)	The appropriate branch define_expand is called, which then
-;;	creates the appropriate RTL for the comparison and branch.
-
-(define_expand "cmphi"
-  [(set (cc0)
-	(compare:CC (match_operand:HI 0 "gpr_operand" "")
-		    (match_operand:HI 1 "arith16_operand" "")))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code message */
-    {
-      compare_op0 = operands[0];
-      compare_op1 = operands[1];
-      DONE;
-    }
-}")
-
-(define_expand "tsthi"
-  [(set (cc0)
-	(match_operand:HI 0 "gpr_operand" ""))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code message */
-    {
-      compare_op0 = operands[0];
-      compare_op1 = const0_rtx;
-      DONE;
-    }
-}")
-
-(define_expand "cmpsi"
-  [(set (cc0)
-	(compare:CC (match_operand:SI 0 "gpr_operand" "")
-		    (match_operand:SI 1 "reg_or_0_operand" "")))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code message */
-    {
-      compare_op0 = operands[0];
-      compare_op1 = operands[1];
-      DONE;
-    }
-}")
-
-(define_expand "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "gpr_operand" ""))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code message */
-    {
-      compare_op0 = operands[0];
-      compare_op1 = const0_rtx;
-      DONE;
-    }
-}")
-
-(define_expand "cmpdi"
-  [(set (cc0)
-	(compare:CC (match_operand:DI 0 "general_operand" "")
-		    (match_operand:DI 1 "reg_or_0_operand" "")))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code message */
-    {
-      compare_op0 = operands[0];
-      compare_op1 = operands[1];
-      DONE;
-    }
-}")
-
-(define_expand "tstdi"
-  [(set (cc0) (match_operand:DI 0 "general_operand" ""))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code message */
-    {
-      compare_op0 = operands[0];
-      compare_op1 = const0_rtx;
-      DONE;
-    }
-}")
-
-(define_insn "*tst_ne_true"
-  [(set (match_operand:CC 0 "f0_operand" "")
-	(ne:CC (and:HI (match_operand:HI 1 "gpr_operand" "d,d")
-		       (match_operand:HI 2 "const_int_operand" "P,n"))
-		   (const_int 0)))]
-  ""
-  "*
-{
-  int log = exact_log2 (INTVAL (operands[2]));
-
-  if (IN_RANGE_P (log, 0, 15))
-    {
-      operands[3] = GEN_INT (15 - log);
-      return \"btsti %1,%3\";
-    }
-
-  return \"tst0i %1,%2\";
-}"
-  [(set_attr "type" "iu,long")
-   (set_attr "length" "1,2")])
-
-; the following is wrong
-;(define_insn "*tst_eq_true"
-;  [(set (match_operand:CC 0 "f0_operand" "")
-;	(eq:CC (and:HI (match_operand:HI 1 "gpr_operand" "d")
-;		       (match_operand:HI 2 "const_int_operand" "n"))
-;	       (const_int 0)))]
-;  ""
-;  "tst0i %1,%2"
-;  [(set_attr "type" "long")
-;   (set_attr "length" "2")])
-;
-;(define_insn "*tst_ne_false"
-;  [(set (match_operand:CC_REV 0 "f0_operand" "")
-;	(ne:CC_REV (and:HI (match_operand:HI 1 "gpr_operand" "d")
-;			   (match_operand:HI 2 "const_int_operand" "n"))
-;		   (const_int 0)))]
-;  ""
-;  "tst0i %1,%2"
-;  [(set_attr "type" "long")
-;   (set_attr "length" "2")])
-
-(define_insn "*tst_eq_false"
-  [(set (match_operand:CC_REV 0 "f0_operand" "")
-	(eq:CC_REV (and:HI (match_operand:HI 1 "gpr_operand" "d,d")
-			   (match_operand:HI 2 "const_int_operand" "P,n"))
-		   (const_int 0)))]
-  ""
-  "*
-{
-  int log = exact_log2 (INTVAL (operands[2]));
-
-  if (IN_RANGE_P (log, 0, 15))
-    {
-      operands[3] = GEN_INT (15 - log);
-      return \"btsti %1,%3\";
-    }
-
-  return \"tst0i %1,%2\";
-}"
-  [(set_attr "type" "iu,long")
-   (set_attr "length" "1,2")])
-
-(define_insn "*eq_hi_true"
-  [(set (match_operand:CC 0 "f0_operand" "")
-	(eq:CC (match_operand:HI 1 "gpr_operand" "d,d")
-	       (match_operand:HI 2 "arith16_operand" "dL,i")))]
-  "emit_comparison (EQ, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (EQ, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "either,long")
-   (set_attr "length" "1,2")])
-
-(define_insn "*lt_hi_true"
-  [(set (match_operand:CC 0 "f0_operand" "")
-	(lt:CC (match_operand:HI 1 "gpr_operand" "d,d")
-	       (match_operand:HI 2 "arith16_operand" "dL,i")))]
-  "emit_comparison (LT, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (LT, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "either,long")
-   (set_attr "length" "1,2")])
-
-(define_insn "*le_hi_true"
-  [(set (match_operand:CC 0 "f0_operand" "")
-	(le:CC (match_operand:HI 1 "gpr_operand" "d,d")
-	       (match_operand:HI 2 "const_int_operand" "O,i")))]
-  "emit_comparison (LE, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (LE, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "either,long")
-   (set_attr "length" "1,2")])
-
-(define_insn "*gt_hi_true"
-  [(set (match_operand:CC 0 "f0_operand" "")
-	(gt:CC (match_operand:HI 1 "gpr_operand" "d")
-	       (match_operand:HI 2 "gpr_operand" "d")))]
-  "emit_comparison (GT, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (GT, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-(define_insn "*ltu_hi_true"
-  [(set (match_operand:CC 0 "f0_operand" "")
-	(ltu:CC (match_operand:HI 1 "gpr_operand" "d,d")
-		(match_operand:HI 2 "arith16_operand" "d,i")))]
-  "emit_comparison (LTU, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (LTU, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "either,long")
-   (set_attr "length" "1,2")])
-
-(define_insn "*leu_hi_true"
-  [(set (match_operand:CC 0 "f0_operand" "")
-	(leu:CC (match_operand:HI 1 "gpr_operand" "d")
-		(match_operand:HI 2 "const_int_operand" "i")))]
-  "emit_comparison (LEU, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (LEU, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*gtu_hi_true"
-  [(set (match_operand:CC 0 "f0_operand" "")
-	(gtu:CC (match_operand:HI 1 "gpr_operand" "d")
-		(match_operand:HI 2 "gpr_operand" "d")))]
-  "emit_comparison (GTU, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (GTU, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-(define_insn "*ne_hi_false"
-  [(set (match_operand:CC_REV 0 "f0_operand" "")
-	(ne:CC_REV (match_operand:HI 1 "gpr_operand" "d,d")
-		   (match_operand:HI 2 "arith16_operand" "dL,i")))]
-  "!emit_comparison (NE, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (NE, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "either,long")
-   (set_attr "length" "1,2")])
-
-(define_insn "*le_hi_false"
-  [(set (match_operand:CC_REV 0 "f0_operand" "")
-	(le:CC_REV (match_operand:HI 1 "gpr_operand" "d")
-		   (match_operand:HI 2 "gpr_operand" "d")))]
-  "!emit_comparison (LE, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (LE, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-(define_insn "*gt_hi_false"
-  [(set (match_operand:CC_REV 0 "f0_operand" "")
-	(gt:CC_REV (match_operand:HI 1 "gpr_operand" "d,d")
-		   (match_operand:HI 2 "const_int_operand" "O,i")))]
-  "!emit_comparison (GT, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (GT, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "either,long")
-   (set_attr "length" "1,2")])
-
-(define_insn "*ge_hi_false"
-  [(set (match_operand:CC_REV 0 "f0_operand" "")
-	(ge:CC_REV (match_operand:HI 1 "gpr_operand" "d,d")
-		   (match_operand:HI 2 "arith16_operand" "dL,i")))]
-  "!emit_comparison (GE, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (GE, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "either,long")
-   (set_attr "length" "1,2")])
-
-(define_insn "*leu_hi_false"
-  [(set (match_operand:CC_REV 0 "f0_operand" "")
-	(leu:CC_REV (match_operand:HI 1 "gpr_operand" "d")
-		    (match_operand:HI 2 "gpr_operand" "d")))]
-  "!emit_comparison (LEU, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (LEU, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-(define_insn "*gtu_hi_false"
-  [(set (match_operand:CC_REV 0 "f0_operand" "")
-	(gtu:CC_REV (match_operand:HI 1 "gpr_operand" "d")
-		    (match_operand:HI 2 "const_int_operand" "i")))]
-  "!emit_comparison (GTU, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (GTU, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*geu_hi_false"
-  [(set (match_operand:CC_REV 0 "f0_operand" "")
-	(geu:CC_REV (match_operand:HI 1 "gpr_operand" "d,d")
-		    (match_operand:HI 2 "arith16_operand" "dL,i")))]
-  "!emit_comparison (GEU, operands[1], operands[2], NULL_RTX, NULL_RTX, HImode, FALSE)"
-  "*
-{
-  emit_comparison (GEU, operands[1], operands[2], NULL_RTX, insn, HImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "either,long")
-   (set_attr "length" "1,2")])
-
-(define_insn "*equality_si_true"
-  [(set (match_operand:CC 0 "f0_operand" "")
-	(match_operator:CC 1 "equality_operator"
-			   [(match_operand:SI 2 "gpr_operand" "e,e,e")
-			    (match_operand:SI 3 "arith_lower0_operand" "e,O,K")]))]
-  "emit_comparison (GET_CODE (operands[1]), operands[2], operands[3], NULL_RTX, NULL_RTX, SImode, FALSE)"
-  "*
-{
-  !emit_comparison (GET_CODE (operands[1]), operands[2], operands[3], NULL_RTX, insn, SImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "4,4,4")])
-
-(define_insn "*signed_si_true"
-  [(set (match_operand:CC 0 "f0_operand" "")
-	(match_operator:CC 1 "signed_compare_operator"
-			   [(match_operand:SI 2 "gpr_operand" "e,e")
-			    (match_operand:SI 3 "reg_or_0_operand" "e,O")]))]
-  "emit_comparison (GET_CODE (operands[1]), operands[2], operands[3], NULL_RTX, NULL_RTX, SImode, FALSE)"
-  "*
-{
-  emit_comparison (GET_CODE (operands[1]), operands[2], operands[3], NULL_RTX, insn, SImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "long,long")
-   (set_attr "length" "4,4")])
-
-(define_insn "*unsigned_si_true"
-  [(set (match_operand:CC 0 "f0_operand" "")
-	(match_operator:CC 1 "unsigned_compare_operator"
-			   [(match_operand:SI 2 "gpr_operand" "e,e")
-			    (match_operand:SI 3 "reg_or_0_operand" "e,O")]))]
-  "emit_comparison (GET_CODE (operands[1]), operands[2], operands[3], NULL_RTX, NULL_RTX, SImode, FALSE)"
-  "*
-{
-  emit_comparison (GET_CODE (operands[1]), operands[2], operands[3], NULL_RTX, insn, SImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "long,long")
-   (set_attr "length" "4,4")])
-
-(define_insn "*equality_si_false"
-  [(set (match_operand:CC_REV 0 "f0_operand" "")
-	(match_operator:CC_REV 1 "equality_operator"
-			       [(match_operand:SI 2 "gpr_operand" "e,e,e")
-				(match_operand:SI 3 "arith_lower0_operand" "e,O,K")]))]
-  "!emit_comparison (GET_CODE (operands[1]), operands[2], operands[3], NULL_RTX, NULL_RTX, SImode, FALSE)"
-  "*
-{
-  emit_comparison (GET_CODE (operands[1]), operands[2], operands[3], NULL_RTX, insn, SImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "4,4,4")])
-
-(define_insn "*signed_si_false"
-  [(set (match_operand:CC_REV 0 "f0_operand" "")
-	(match_operator:CC_REV 1 "signed_compare_operator"
-			       [(match_operand:SI 2 "gpr_operand" "e,e")
-				(match_operand:SI 3 "reg_or_0_operand" "e,O")]))]
-  "!emit_comparison (GET_CODE (operands[1]), operands[2], operands[3], NULL_RTX, NULL_RTX, SImode, FALSE)"
-  "*
-{
-  emit_comparison (GET_CODE (operands[1]), operands[2], operands[3], NULL_RTX, insn, SImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "long,long")
-   (set_attr "length" "4,4")])
-
-(define_insn "*unsigned_si_false"
-  [(set (match_operand:CC_REV 0 "f0_operand" "")
-	(match_operator:CC_REV 1 "unsigned_compare_operator"
-			       [(match_operand:SI 2 "gpr_operand" "e,e")
-				(match_operand:SI 3 "reg_or_0_operand" "e,O")]))]
-  "!emit_comparison (GET_CODE (operands[1]), operands[2], operands[3], NULL_RTX, NULL_RTX, SImode, FALSE)"
-  "*
-{
-  emit_comparison (GET_CODE (operands[1]), operands[2], operands[3], NULL_RTX, insn, SImode, TRUE);
-  return \"\";
-}"
-  [(set_attr "type" "long,long")
-   (set_attr "length" "4,4")])
-
-
-
-;;
-;;  ....................
-;;
-;;	Conditional moves
-;;
-;;  ....................
-
-(define_expand "movqicc"
-  [(match_dup 4)
-   (set (match_operand:QI 0 "cond_move_operand" "")
-	(if_then_else:QI (match_operand 1 "" "")
-			 (match_operand:QI 2 "cond_move_operand" "")
-			 (match_operand:QI 3 "cond_move_operand" "")))]
-  "TARGET_COND_MOVE"
-  "
-{
-  rtx f0;
-
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (GET_CODE (operands[2]) != REG && !(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0))
-	FAIL;
-
-      if (GET_CODE (operands[3]) != REG && !(GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0))
-	FAIL;
-    }
-
-  operands[4] = expand_comparison (GET_CODE (operands[1]), compare_op0, compare_op1, &f0);
-  operands[1] = gen_rtx (NE, GET_MODE (f0), f0, const0_rtx);
-}")
-
-(define_insn "*movqicc_internal"
-  [(set (match_operand:QI 0 "cond_move_operand" "=d,d,?d,d,d,?d,Q")
-	(if_then_else:QI (match_operator:CC 1 "f0_compare_operator"
-					    [(match_operand:CC 2 "f0_operand" "")
-					     (const_int 0)])
-			 (match_operand:QI 3 "cond_move_operand" "0,d,d,0,LQ,LQd,Od")
-			 (match_operand:QI 4 "cond_move_operand" "d,0,d,LQ,0,LQd,Od")))]
-  "TARGET_COND_MOVE
-   && (GET_CODE (operands[0]) != MEM
-       || GET_CODE (operands[3]) == REG
-       || (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0)
-       || GET_CODE (operands[4]) == REG
-       || (GET_CODE (operands[4]) == CONST_INT && INTVAL (operands[4]) == 0))"
-  "* return emit_cond_move (operands, insn);"
-  [(set_attr "type" "either,either,long,long,long,long,long")
-   (set_attr "length" "1,1,2,2,2,4,4")])
-
-(define_expand "movhicc"
-  [(match_dup 4)
-   (set (match_operand:HI 0 "cond_move_operand" "")
-	(if_then_else:HI (match_operand 1 "" "")
-			 (match_operand:HI 2 "cond_move_operand" "")
-			 (match_operand:HI 3 "cond_move_operand" "")))]
-  "TARGET_COND_MOVE"
-  "
-{
-  rtx f0;
-
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (GET_CODE (operands[2]) != REG && !(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0))
-	FAIL;
-
-      if (GET_CODE (operands[3]) != REG && !(GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0))
-	FAIL;
-    }
-
-  operands[4] = expand_comparison (GET_CODE (operands[1]), compare_op0, compare_op1, &f0);
-  operands[1] = gen_rtx (NE, GET_MODE (f0), f0, const0_rtx);
-}")
-
-(define_insn "*movhicc_internal"
-  [(set (match_operand:HI 0 "cond_move_operand" "=d,d,?d,d,d,?d,Q")
-	(if_then_else:HI (match_operator:CC 1 "f0_compare_operator"
-					    [(match_operand:CC 2 "f0_operand" "")
-					     (const_int 0)])
-			 (match_operand:HI 3 "cond_move_operand" "0,d,d,0,LQ,LQd,Od")
-			 (match_operand:HI 4 "cond_move_operand" "d,0,d,LQ,0,LQd,Od")))]
-  "TARGET_COND_MOVE
-   && (GET_CODE (operands[0]) != MEM
-       || GET_CODE (operands[3]) == REG
-       || (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0)
-       || GET_CODE (operands[4]) == REG
-       || (GET_CODE (operands[4]) == CONST_INT && INTVAL (operands[4]) == 0))"
-  "* return emit_cond_move (operands, insn);"
-  [(set_attr "type" "either,either,long,long,long,long,long")
-   (set_attr "length" "1,1,2,2,2,4,4")])
-
-(define_expand "movsicc"
-  [(match_dup 4)
-   (set (match_operand:SI 0 "cond_move_operand" "")
-	(if_then_else:SI (match_operand 1 "" "")
-			 (match_operand:SI 2 "cond_move_operand" "")
-			 (match_operand:SI 3 "cond_move_operand" "")))]
-  "TARGET_COND_MOVE"
-  "
-{
-  rtx f0;
-
-  if (GET_CODE (operands[0]) == MEM
-      && (GET_CODE (operands[2]) != REG || GET_CODE (operands[3]) != REG))
-    {
-      FAIL;
-    }
-
-  operands[4] = expand_comparison (GET_CODE (operands[1]), compare_op0, compare_op1, &f0);
-  operands[1] = gen_rtx (NE, GET_MODE (f0), f0, const0_rtx);
-}")
-
-(define_insn "*movsicc_internal"
-  [(set (match_operand:SI 0 "cond_move_operand" "=e,e,?e,Q")
-	(if_then_else:SI (match_operator:CC 1 "f0_compare_operator"
-					    [(match_operand:CC 2 "f0_operand" "")
-					     (const_int 0)])
-			 (match_operand:SI 3 "cond_move_operand" "0,Qe,Qe,e")
-			 (match_operand:SI 4 "cond_move_operand" "Qe,0,Qe,e")))]
-  "TARGET_COND_MOVE
-   && (GET_CODE (operands[0]) != MEM
-       || GET_CODE (operands[3]) == REG
-       || GET_CODE (operands[4]) == REG)"
-  "* return emit_cond_move (operands, insn);"
-  [(set_attr "type" "long,long,long,long")
-   (set_attr "length" "2,2,4,4")])
-
-(define_expand "movsfcc"
-  [(match_dup 4)
-   (set (match_operand:SF 0 "cond_move_operand" "")
-	(if_then_else:SF (match_operand 1 "" "")
-			 (match_operand:SF 2 "cond_move_operand" "")
-			 (match_operand:SF 3 "cond_move_operand" "")))]
-  "TARGET_COND_MOVE"
-  "
-{
-  rtx f0;
-
-  if (GET_CODE (operands[0]) == MEM
-      && (GET_CODE (operands[2]) != REG || GET_CODE (operands[3]) != REG))
-    {
-      FAIL;
-    }
-
-  operands[4] = expand_comparison (GET_CODE (operands[1]), compare_op0, compare_op1, &f0);
-  operands[1] = gen_rtx (NE, GET_MODE (f0), f0, const0_rtx);
-}")
-
-(define_insn "*movsfcc_internal"
-  [(set (match_operand:SF 0 "cond_move_operand" "=e,e,?e,Q")
-	(if_then_else:SF (match_operator:CC 1 "f0_compare_operator"
-					    [(match_operand:CC 2 "f0_operand" "")
-					     (const_int 0)])
-			 (match_operand:SF 3 "cond_move_operand" "0,Qe,Qe,e")
-			 (match_operand:SF 4 "cond_move_operand" "Qe,0,Qe,e")))]
-  "TARGET_COND_MOVE
-   && (GET_CODE (operands[0]) != MEM
-       || GET_CODE (operands[3]) == REG
-       || GET_CODE (operands[4]) == REG)"
-  "* return emit_cond_move (operands, insn);"
-  [(set_attr "type" "long,long,long,long")
-   (set_attr "length" "2,2,4,4")])
-
-
-;;
-;;  ....................
-;;
-;;	Conditional execution
-;;
-;;  ....................
-
-(define_insn "*cond_exec_qi_store_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (set (match_operand:QI 0 "short_memory_operand" "=Q,Q")
-		      (match_operand:QI 1 "reg_or_0_operand" "d,O"))
-		 (const_int 0))]
-  ""
-  "@
-   stb %1,%M0 || exef0%T2
-   stb %.,%M0 || exef0%T2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_qi_store_false"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:QI 0 "short_memory_operand" "=Q,Q")
-		      (match_operand:QI 1 "reg_or_0_operand" "d,O")))]
-  ""
-  "@
-   stb %1,%M0 || exef0%F2
-   stb %.,%M0 || exef0%F2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_qi_load_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (set (match_operand:QI 0 "gpr_operand" "=d,d,d")
-		      (match_operand:QI 1 "cond_exec_operand" "d,L,Q"))
-		 (const_int 0))]
-  ""
-  "@
-   exef0%T2 || mv %0,%1
-   exef0%T2 || ldi %0,%1
-   ldub %0,%M1 || exef0%T2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_qi_load_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:QI 0 "gpr_operand" "=d,d,d")
-		      (match_operand:QI 1 "cond_exec_operand" "d,L,Q")))]
-  ""
-  "@
-   exef0%F2 || mv %0,%1
-   exef0%F2 || ldi %0,%1
-   ldub %0,%M1 || exef0%F2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_binary_true"
-  [(if_then_else (match_operator 3 "f0_compare_operator"
-				 [(match_operand:CC 4 "f0_operand" "")
-				  (const_int 0)])
-		 (set (match_operand:HI 0 "gpr_operand" "=d")
-		      (match_operator:HI 5 "binary_parallel_operator"
-					 [(match_operand:HI 1 "gpr_operand" "0")
-					  (match_operand:HI 2 "arith16_operand" "di")]))
-		 (const_int 0))]
-  "rtx_equal_p (operands[0], operands[1])"
-  "*
-{
-  if (GET_CODE (operands[2]) == REG || GET_CODE (operands[2]) == SUBREG)
-    switch (GET_CODE (operands[5]))
-      {
-      case PLUS:	return \"exef0%T3 || add %0,%2\";
-      case MINUS:	return \"exef0%T3 || sub %0,%2\";
-      case MULT:	return \"exef0%T3 || mul %0,%2\";
-      case AND:		return \"exef0%T3 || and %0,%2\";
-      case IOR:		return \"exef0%T3 || or %0,%2\";
-      case XOR:		return \"exef0%T3 || xor %0,%2\";
-      case ASHIFT:	return \"exef0%T3 || sll %0,%2\";
-      case ASHIFTRT:	return \"exef0%T3 || sra %0,%2\";
-      case LSHIFTRT:	return \"exef0%T3 || srl %0,%2\";
-      }
-
-  else if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      HOST_WIDE_INT value = INTVAL (operands[2]);
-      int log;
-
-      switch (GET_CODE (operands[5]))
-	{
-	case PLUS:
-	  if (IN_RANGE_P (value, 1, 16))
-	    return \"exef0%T3 || addi %0,%2\";
-
-	  else if (IN_RANGE_P (value, -16, -1))
-	    return \"exef0%T3 || subi %0,%n2\";
-
-	  else if (value == 0)
-	    return \"\";
-
-	  else
-	    break;
-
-	case MINUS:
-	  if (IN_RANGE_P (value, 1, 16))
-	    return \"exef0%T3 || subi %0,%2\";
-
-	  else if (IN_RANGE_P (value, -16, -1))
-	    return \"exef0%T3 || addi %0,%n2\";
-
-	  else if (value == 0)
-	    return \"\";
-
-	  else
-	    break;
-
-	case IOR:
-	case XOR:
-	  if (value == 0)
-	    return \"\";
-
-	  log = exact_log2 (value);
-	  if (IN_RANGE_P (log, 0, 15))
-	    {
-	      operands[2] = GEN_INT (15 - log);
-	      return ((GET_CODE (operands[5]) == IOR)
-		      ? \"exef0%T3 || bseti %0,%2\"
-		      : \"exef0%T3 || bnoti %0,%2\");
-	    }
-	  break;
-
-	case AND:
-	  if ((value & 0xffff) == 0xffff)
-	    return \"\";
-
-	  log = exact_log2 (~value);
-	  if (IN_RANGE_P (log, 0, 15))
-	    {
-	      operands[2] = GEN_INT (15 - log);
-	      return \"exef0%T3 || bclri %0,%2\";
-	    }
-	  break;
-	}
-    }
-
-  fatal_insn (\"cond_exec_hi_binary_true\", insn);
-  return \"\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_binary_false"
-  [(if_then_else (match_operator 3 "f0_compare_operator"
-				 [(match_operand:CC 4 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:HI 0 "gpr_operand" "=d")
-		      (match_operator:HI 5 "binary_parallel_operator"
-					 [(match_operand:HI 1 "gpr_operand" "0")
-					  (match_operand:HI 2 "arith16_operand" "di")])))]
-  "rtx_equal_p (operands[0], operands[1])"
-  "*
-{
-  if (GET_CODE (operands[2]) == REG || GET_CODE (operands[2]) == SUBREG)
-    switch (GET_CODE (operands[5]))
-      {
-      case PLUS:	return \"exef0%F3 || add %0,%2\";
-      case MINUS:	return \"exef0%F3 || sub %0,%2\";
-      case MULT:	return \"exef0%F3 || mul %0,%2\";
-      case AND:		return \"exef0%F3 || and %0,%2\";
-      case IOR:		return \"exef0%F3 || or %0,%2\";
-      case XOR:		return \"exef0%F3 || xor %0,%2\";
-      case ASHIFT:	return \"exef0%F3 || sll %0,%2\";
-      case ASHIFTRT:	return \"exef0%F3 || sra %0,%2\";
-      case LSHIFTRT:	return \"exef0%F3 || srl %0,%2\";
-      }
-
-  else if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      HOST_WIDE_INT value = INTVAL (operands[2]);
-      int log;
-
-      switch (GET_CODE (operands[5]))
-	{
-	case PLUS:
-	  if (IN_RANGE_P (value, 1, 16))
-	    return \"exef0%F3 || addi %0,%2\";
-
-	  else if (IN_RANGE_P (value, -16, -1))
-	    return \"exef0%F3 || subi %0,%n2\";
-
-	  else if (value == 0)
-	    return \"\";
-
-	  else
-	    break;
-
-	case MINUS:
-	  if (IN_RANGE_P (value, 1, 16))
-	    return \"exef0%F3 || subi %0,%2\";
-
-	  else if (IN_RANGE_P (value, -16, -1))
-	    return \"exef0%F3 || addi %0,%n2\";
-
-	  else if (value == 0)
-	    return \"\";
-
-	  else
-	    break;
-
-	case IOR:
-	case XOR:
-	  if (value == 0)
-	    return \"\";
-
-	  log = exact_log2 (value);
-	  if (IN_RANGE_P (log, 0, 15))
-	    {
-	      operands[2] = GEN_INT (15 - log);
-	      return ((GET_CODE (operands[5]) == IOR)
-		      ? \"exef0%F3 || bseti %0,%2\"
-		      : \"exef0%F3 || bnoti %0,%2\");
-	    }
-	  break;
-
-	case AND:
-	  if ((value & 0xffff) == 0xffff)
-	    return \"\";
-
-	  log = exact_log2 (~value);
-	  if (IN_RANGE_P (log, 0, 15))
-	    {
-	      operands[2] = GEN_INT (15 - log);
-	      return \"exef0%F3 || bclri %0,%2\";
-	    }
-	  break;
-	}
-    }
-
-  fatal_insn (\"cond_exec_hi_binary_false\", insn);
-  return \"\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_unary_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (set (match_operand:HI 0 "gpr_operand" "=d")
-		      (match_operator:HI 4 "unary_parallel_operator"
-					 [(match_operand:HI 1 "gpr_operand" "0")]))
-		 (const_int 0))]
-  "rtx_equal_p (operands[0], operands[1])"
-  "*
-{
-  switch (GET_CODE (operands[4]))
-    {
-    case NEG: return \"exef0%T2 || neg %0\";
-    case NOT: return \"exef0%T2 || not %0\";
-
-    case SIGN_EXTEND:
-      if (GET_CODE (operands[1]) == MEM)
-	return \"ldb %0,%M1 || exef0%T2\";
-      else if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)
-	return \"exef0%T2 || mvb %0,%1\";
-      break;
-
-    case ZERO_EXTEND:
-      if (GET_CODE (operands[1]) == MEM)
-	return \"ldub %0,%M1 || exef0%T2\";
-      else if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)
-	return \"exef0%T2 || mvub %0,%1\";
-      break;
-    }
-
-  fatal_insn (\"cond_exec_hi_unary_true\", insn);
-  return \"\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_unary_false"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:HI 0 "gpr_operand" "=d")
-		      (match_operator:HI 4 "unary_parallel_operator"
-					 [(match_operand:HI 1 "gpr_operand" "0")])))]
-  "rtx_equal_p (operands[0], operands[1])"
-  "*
-{
-  switch (GET_CODE (operands[4]))
-    {
-    case NEG: return \"exef0%F2 || neg %0\";
-    case NOT: return \"exef0%F2 || not %0\";
-
-    case SIGN_EXTEND:
-      if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)
-	return \"exef0%F2 || mvb %0,%1\";
-      break;
-
-    case ZERO_EXTEND:
-      if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)
-	return \"exef0%F2 || mvub %0,%1\";
-      break;
-    }
-
-  fatal_insn (\"cond_exec_hi_unary_false\", insn);
-  return \"\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_abs_true"
-  [(if_then_else (match_operator 3 "f0_compare_operator"
-				 [(match_operand:CC 4 "f0_operand" "")
-				  (const_int 0)])
-		 (parallel [(set (match_operand:HI 0 "gpr_operand" "=d")
-				 (abs:HI (match_operand:HI 1 "gpr_operand" "0")))
-			    (clobber (match_operand:CC 2 "f0_operand" ""))])
-		 (const_int 0))]
-  "rtx_equal_p (operands[0], operands[1])"
-  "exef0%T3 || abs %0"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_abs_false"
-  [(if_then_else (match_operator 3 "f0_compare_operator"
-				 [(match_operand:CC 4 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (parallel [(set (match_operand:HI 0 "gpr_operand" "=d")
-				 (abs:HI (match_operand:HI 1 "gpr_operand" "0")))
-			    (clobber (match_operand:CC 2 "f0_operand" ""))]))]
-  "rtx_equal_p (operands[0], operands[1])"
-  "exef0%F3 || abs %0"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_minmax_true"
-  [(if_then_else (match_operator 5 "f0_compare_operator"
-				 [(match_operand:CC 6 "f0_operand" "")
-				  (const_int 0)])
-		 (parallel [(set (match_operand:HI 0 "gpr_operand" "=d")
-				 (match_operator:HI 3 "minmax_parallel_operator"
-						    [(match_operand:HI 1 "gpr_operand" "%0")
-						     (match_operand:HI 2 "gpr_operand" "d")]))
-			    (clobber (match_operand:CC 4 "f0_operand" ""))])
-		 (const_int 0))]
-  "rtx_equal_p (operands[0], operands[1])"
-  "*
-{
-  if (GET_CODE (operands[3]) == SMIN)
-    return \"exef0%T5 || min %0,%2\";
-  else
-    return \"exef0%T5 || max %0,%2\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_minmax_false"
-  [(if_then_else (match_operator 5 "f0_compare_operator"
-				 [(match_operand:CC 6 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (parallel [(set (match_operand:HI 0 "gpr_operand" "=d")
-				 (match_operator:HI 3 "minmax_parallel_operator"
-						    [(match_operand:HI 1 "gpr_operand" "%0")
-						     (match_operand:HI 2 "gpr_operand" "d")]))
-			    (clobber (match_operand:CC 4 "f0_operand" ""))]))]
-  "rtx_equal_p (operands[0], operands[1])"
-  "*
-{
-  if (GET_CODE (operands[3]) == SMIN)
-    return \"exef0%F5 || min %0,%2\";
-  else
-    return \"exef0%F5 || max %0,%2\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_extend_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (set (match_operand:HI 0 "gpr_operand" "=d")
-		      (match_operator:HI 4 "extend_parallel_operator"
-					 [(match_operand:QI 1 "short_memory_operand" "Q")]))
-		 (const_int 0))]
-  ""
-  "ld%u4b %0,%M1 || exef0%T2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_extend_false"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:HI 0 "gpr_operand" "=d")
-		      (match_operator:HI 4 "extend_parallel_operator"
-					 [(match_operand:QI 1 "short_memory_operand" "Q")])))]
-  ""
-  "ld%u4b %0,%M1 || exef0%F2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_store_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (set (match_operand:HI 0 "short_memory_operand" "=Q,Q")
-		      (match_operand:HI 1 "reg_or_0_operand" "d,O"))
-		 (const_int 0))]
-  ""
-  "@
-   st %1,%M0 || exef0%T2
-   st %.,%M0 || exef0%T2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_store_false"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:HI 0 "short_memory_operand" "=Q,Q")
-		      (match_operand:HI 1 "reg_or_0_operand" "d,O")))]
-  ""
-  "@
-   st %1,%M0 || exef0%F2
-   st %.,%M0 || exef0%F2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_load_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (set (match_operand:HI 0 "gpr_operand" "=d,d,d")
-		      (match_operand:HI 1 "cond_exec_operand" "d,L,Q"))
-		 (const_int 0))]
-  ""
-  "@
-   exef0%T2 || mv %0,%1
-   exef0%T2 || ldi %0,%1
-   ld %0,%M1 || exef0%T2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_hi_load_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:HI 0 "gpr_operand" "=d,d,d")
-		      (match_operand:HI 1 "cond_exec_operand" "d,L,Q")))]
-  ""
-  "@
-   exef0%F2 || mv %0,%1
-   exef0%F2 || ldi %0,%1
-   ld %0,%M1 || exef0%F2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_si_binary_true"
-  [(if_then_else (match_operator 3 "f0_compare_operator"
-				 [(match_operand:CC 4 "f0_operand" "")
-				  (const_int 0)])
-		 (set (match_operand:SI 0 "gpr_operand" "=e")
-		      (match_operator:SI 5 "binary_parallel_operator"
-					 [(match_operand:SI 1 "gpr_operand" "0")
-					  (match_operand:SI 2 "gpr_operand" "e")]))
-		 (const_int 0))]
-  "rtx_equal_p (operands[0], operands[1])"
-  "*
-{
-  if (GET_CODE (operands[2]) == REG || GET_CODE (operands[2]) == SUBREG)
-    switch (GET_CODE (operands[5]))
-      {
-      case PLUS:	return \"exef0%T3 || add2w %0,%2\";
-      case MINUS:	return \"exef0%T3 || sub2w %0,%2\";
-      }
-
-  fatal_insn (\"cond_exec_si_binary_true\", insn);
-  return \"\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_si_binary_false"
-  [(if_then_else (match_operator 3 "f0_compare_operator"
-				 [(match_operand:CC 4 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SI 0 "gpr_operand" "=d")
-		      (match_operator:SI 5 "binary_parallel_operator"
-					 [(match_operand:SI 1 "gpr_operand" "0")
-					  (match_operand:SI 2 "arith16_operand" "di")])))]
-  "rtx_equal_p (operands[0], operands[1])"
-  "*
-{
-  if (GET_CODE (operands[2]) == REG || GET_CODE (operands[2]) == SUBREG)
-    switch (GET_CODE (operands[5]))
-      {
-      case PLUS:	return \"exef0%F3 || add2w %0,%2\";
-      case MINUS:	return \"exef0%F3 || sub2w %0,%2\";
-      }
-
-  fatal_insn (\"cond_exec_si_binary_false\", insn);
-  return \"\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_si_store_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (set (match_operand:SI 0 "short_memory_operand" "=Q")
-		      (match_operand:SI 1 "gpr_operand" "e"))
-		 (const_int 0))]
-  ""
-  "st2w %1,%M0 || exef0%T2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_si_store_false"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SI 0 "short_memory_operand" "=Q")
-		      (match_operand:SI 1 "gpr_operand" "d")))]
-  ""
-  "st2w %1,%M0 || exef0%F2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_si_load_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (set (match_operand:SI 0 "gpr_operand" "=e,e")
-		      (match_operand:SI 1 "cond_exec_operand" "e,Q"))
-		 (const_int 0))]
-  ""
-  "@
-   exef0%T2 || mv2w %0,%1
-   ld2w %0,%M1 || exef0%T2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_si_load_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SI 0 "gpr_operand" "=e,e")
-		      (match_operand:SI 1 "cond_exec_operand" "e,Q")))]
-  ""
-  "@
-   exef0%F2 || mv2w %0,%1
-   ld2w %0,%M1 || exef0%F2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_sf_store_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (set (match_operand:SF 0 "short_memory_operand" "=Q")
-		      (match_operand:SF 1 "gpr_operand" "e"))
-		 (const_int 0))]
-  ""
-  "st2w %1,%M0 || exef0%T2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_sf_store_false"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SF 0 "short_memory_operand" "=Q")
-		      (match_operand:SF 1 "gpr_operand" "d")))]
-  ""
-  "st2w %1,%M0 || exef0%F2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_sf_load_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (set (match_operand:SF 0 "gpr_operand" "=e,e")
-		      (match_operand:SF 1 "cond_exec_operand" "e,Q"))
-		 (const_int 0))]
-  ""
-  "@
-   exef0%T2 || mv2w %0,%1
-   ld2w %0,%M1 || exef0%T2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_sf_load_true"
-  [(if_then_else (match_operator 2 "f0_compare_operator"
-				 [(match_operand:CC 3 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SF 0 "gpr_operand" "=e,e")
-		      (match_operand:SF 1 "cond_exec_operand" "e,Q")))]
-  ""
-  "@
-   exef0%F2 || mv2w %0,%1
-   ld2w %0,%M1 || exef0%F2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_call_true"
-  [(if_then_else (match_operator 3 "f0_compare_operator"
-				 [(match_operand:CC 4 "f0_operand" "")
-				  (const_int 0)])
-		 (parallel [(call (match_operand 0 "memory_operand" "m")
-				  (match_operand 1 "" "i"))
-			    (clobber (match_scratch:HI 2 "=l"))])			;; return address, r13
-		 (const_int 0))]
-  "GET_CODE (XEXP (operands[0], 0)) == REG"
-  "jl %0 || exef0%T3"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_call_false"
-  [(if_then_else (match_operator 3 "f0_compare_operator"
-				 [(match_operand:CC 4 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (parallel [(call (match_operand 0 "memory_operand" "m")
-				  (match_operand 1 "" "i"))
-			    (clobber (match_scratch:HI 2 "=l"))]))]			;; return address, r13
-  "GET_CODE (XEXP (operands[0], 0)) == REG"
-  "jl %0 || exef0%F3"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_call_value_true"
-  [(if_then_else (match_operator 4 "f0_compare_operator"
-				 [(match_operand:CC 5 "f0_operand" "")
-				  (const_int 0)])
-		 (parallel [(set (match_operand 0 "gpr_operand" "=r")
-				 (call (match_operand 1 "memory_operand" "m")
-				       (match_operand 2 "" "i")))
-			    (clobber (match_scratch:HI 3 "=l"))])			;; return address, r13
-		 (const_int 0))]
-  "GET_CODE (XEXP (operands[1], 0)) == REG"
-  "jl %1 || exef0%T4"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_insn "*cond_exec_call_value_false"
-  [(if_then_else (match_operator 4 "f0_compare_operator"
-				 [(match_operand:CC 5 "f0_operand" "")
-				  (const_int 0)])
-		 (const_int 0)
-		 (parallel [(set (match_operand 0 "gpr_operand" "=r")
-				 (call (match_operand 1 "memory_operand" "m")
-				       (match_operand 2 "" "i")))
-			    (clobber (match_scratch:HI 3 "=l"))]))]			;; return address, r13
-  "GET_CODE (XEXP (operands[1], 0)) == REG"
-  "jl %1 || exef0%F4"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-;;
-;;  ....................
-;;
-;;	Conditional branches
-;;
-;;  ....................
-
-(define_expand "beq"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (EQ, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "bne"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (NE, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "bgt"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (GT, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "bge"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (GE, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "blt"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (LT, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "ble"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (LE, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "bgtu"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (GTU, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "bgeu"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (GEU, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "bltu"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (LTU, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "bleu"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (match_dup 1)
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (LEU, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_insn "*cond_branch"
-  [(set (pc)
-	(if_then_else (match_operator:CC 0 "f0_compare_operator"
-					 [(match_operand:CC 1 "f0_operand" "")
-					  (const_int 0)])
-		      (match_operand 2 "pc_or_label_operand" "")
-		      (match_operand 3 "pc_or_label_operand" "")))]
-  ""
-  "*
-{
-  if (operands[2] == pc_rtx)
-    return (GET_CODE (operands[3]) == RETURN) ? \"jmp r13 || exef0%T0\" : \"brf0%T0 %l3\";
-  else
-    return (GET_CODE (operands[2]) == RETURN) ? \"jmp r13 || exef0%F0\" : \"brf0%F0 %l2\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-
-;;
-;;  ....................
-;;
-;;	Set from condition code
-;;
-;;  ....................
-
-(define_expand "seq"
-  [(match_dup 2)
-   (set (match_operand:HI 0 "gpr_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (EQ, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "sne"
-  [(match_dup 2)
-   (set (match_operand:HI 0 "gpr_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (NE, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "sgt"
-  [(match_dup 2)
-   (set (match_operand:HI 0 "gpr_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (GT, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "sge"
-  [(match_dup 2)
-   (set (match_operand:HI 0 "gpr_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (GE, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "slt"
-  [(match_dup 2)
-   (set (match_operand:HI 0 "gpr_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (LT, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "sle"
-  [(match_dup 2)
-   (set (match_operand:HI 0 "gpr_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (LE, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "sgtu"
-  [(match_dup 2)
-   (set (match_operand:HI 0 "gpr_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (GTU, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "sgeu"
-  [(match_dup 2)
-   (set (match_operand:HI 0 "gpr_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (GEU, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "sltu"
-  [(match_dup 2)
-   (set (match_operand:HI 0 "gpr_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (LTU, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_expand "sleu"
-  [(match_dup 2)
-   (set (match_operand:HI 0 "gpr_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  rtx reg;
-  operands[2] = expand_comparison (LEU, compare_op0, compare_op1, &reg);
-  operands[1] = gen_rtx (NE, GET_MODE (reg), reg, const0_rtx);
-}")
-
-(define_insn "*scc"
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(match_operator 1 "f0_compare_operator"
-			[(match_operand:CC 2 "f0_operand" "")
-			 (const_int 0)]))]
-  ""
-  "setf0%F1 %0"
-  [(set_attr "type" "mu")
-   (set_attr "length" "1")])
-
-
-;;
-;;  ....................
-;;
-;;	Data conversion
-;;
-;;  ....................
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,Q,m")))]
-  ""
-  "@
-   mvub %0,%1
-   ldub %0,%M1
-   ldub %0,%M1"
-  [(set_attr "type" "iu,mu,long")
-   (set_attr "length" "1,1,2")])
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,Q,m")))]
-  ""
-  "@
-   mvub %L0,%1\;ldi %U0,0
-   ldub %L0,%M1\;ldi %U0,0
-   ldub %L0,%M1\;ldi %U0,0"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "2,2,3")])
-
-(define_split
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 3) (zero_extend:HI (match_dup 1)))
-   (set (match_dup 2) (const_int 0))]
-  "
-{
-  operands[2] = d10v_subword (operands[0], 0, HImode, SImode);
-  operands[3] = d10v_subword (operands[0], 1, HImode, SImode);
-}")
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "gpr_operand" "=e,e,e")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "e,Q,m")))]
-  ""
-  "@
-   mv %L0,%1\;ldi %U0,0
-   ld %L0,%M1\;ldi %U0,0
-   ld %L0,%M1\;ldi %U0,0"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "2,2,3")])
-
-(define_split
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 3) (match_dup 1))
-   (set (match_dup 2) (const_int 0))]   
-  "
-{
-  operands[2] = d10v_subword (operands[0], 0, HImode, SImode);
-  operands[3] = d10v_subword (operands[0], 1, HImode, SImode);
-}")
-
-(define_insn "zero_extendqidi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,Q,m")))]
-  ""
-  "@
-   mvub %D0,%1\;ldi %C0,0\;ldi %B0,0\;ldi %A0,0
-   ldub %D0,%M1\;ldi %C0,0\;ldi %B0,0\;ldi %A0,0
-   ldub %D0,%M1\;ldi %C0,0\;ldi %B0,0\;ldi %A0,0"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "4,4,5")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(zero_extend:DI (match_operand:QI 1 "gpr_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 5) (zero_extend:HI (match_dup 1)))
-   (set (match_dup 2) (const_int 0))
-   (set (match_dup 3) (const_int 0))
-   (set (match_dup 4) (const_int 0))]
-  "
-{
-  operands[2] = d10v_subword (operands[0], 0, HImode, DImode);
-  operands[3] = d10v_subword (operands[0], 1, HImode, DImode);
-  operands[4] = d10v_subword (operands[0], 2, HImode, DImode);
-  operands[5] = d10v_subword (operands[0], 3, HImode, DImode);
-}")
-
-(define_insn "zero_extendhidi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,Q,m")))]
-  ""
-  "@
-   mv %D0,%1\;ldi %C0,0\;ldi %B0,0\;ldi %A0,0
-   ld %D0,%M1\;ldi %C0,0\;ldi %B0,0\;ldi %A0,0
-   ld %D0,%M1\;ldi %C0,0\;ldi %B0,0\;ldi %A0,0"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "4,4,5")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 5) (match_dup 1))
-   (set (match_dup 2) (const_int 0))
-   (set (match_dup 3) (const_int 0))
-   (set (match_dup 4) (const_int 0))]
-  "
-{
-  operands[2] = d10v_subword (operands[0], 0, HImode, DImode);
-  operands[3] = d10v_subword (operands[0], 1, HImode, DImode);
-  operands[4] = d10v_subword (operands[0], 2, HImode, DImode);
-  operands[5] = d10v_subword (operands[0], 3, HImode, DImode);
-}")
-
-(define_insn "zero_extendsidi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "e,Q,m")))]
-  ""
-  "@
-   mv2w %C0,%1\;ldi %B0,0\;ldi %A0,0
-   ld2w %C0,%M1\;ldi %B0,0\;ldi %A0,0
-   ld2w %C0,%M1\;ldi %B0,0\;ldi %A0,0"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "3,3,4")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 4) (match_dup 1))
-   (set (match_dup 2) (const_int 0))
-   (set (match_dup 3) (const_int 0))]
-  "
-{
-  operands[2] = d10v_subword (operands[0], 0, HImode, DImode);
-  operands[3] = d10v_subword (operands[0], 1, HImode, DImode);
-  operands[4] = d10v_subword (operands[0], 2, SImode, DImode);
-}")
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d")
-	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,Q,m")))]
-  ""
-  "@
-   mvb %0,%1
-   ldb %0,%M1
-   ldb %0,%M1"
-  [(set_attr "type" "iu,mu,long")
-   (set_attr "length" "1,1,2")])
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "gpr_operand" "=e,e,e")
-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "e,Q,m")))]
-  ""
-  "@
-   mvb %L0,%1\;mv %U0,%L0\;srai %U0,15
-   ldb %L0,%M1\;mv %U0,%L0\;srai %U0,15
-   ldb %L0,%M1\;mv %U0,%L0\;srai %U0,15"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "3,3,4")])
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "gpr_operand" "=e,e,e,a")
-	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "e,Q,m,e")))]
-  ""
-  "*
-{
-  if (ACCUM_P (REGNO (operands[0])))
-    return \"mvtaclo %1,%0\";
-
-  if (GET_CODE (operands[1]) == MEM)
-    return \"ld %L0,%M1\;mv %U0,%L0\;srai %U0,15\";
-
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"mv %L0,%1\;srai %U0,15\";
-
-  return \"mv %L0,%1\;mv %U0,%L0\;srai %U0,15\";
-}"
-  [(set_attr "type" "long,long,long,iu")
-   (set_attr "length" "3,3,4,1")])
-
-(define_insn "extendqidi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "e,Q,m")))]
-  ""
-  "@
-   mvb %D0,%1\;mv %C0,%D0\;srai %C0,15\;mv %B0,%C0\;mv %A0,%C0
-   ldb %D0,%M1\;mv %C0,%D0\;srai %C0,15\;mv %B0,%C0\;mv %A0,%C0
-   ldb %D0,%M1\;mv %C0,%D0\;srai %C0,15\;mv %B0,%C0\;mv %A0,%C0"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "5,5,6")])
-
-(define_insn "extendhidi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "e,Q,m")))]
-  ""
-  "@
-   mv %D0,%1\;mv %C0,%D0\;srai %C0,15\;mv %B0,%C0\;mv %A0,%C0
-   ld %D0,%M1\;mv %C0,%D0\;srai %C0,15\;mv %B0,%C0\;mv %A0,%C0
-   ld %D0,%M1\;mv %C0,%D0\;srai %C0,15\;mv %B0,%C0\;mv %A0,%C0"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "5,5,6")])
-
-(define_insn "extendsidi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "e,Q,m")))]
-  ""
-  "@
-   mv2w %C0,%1\;mv %B0,%C0\;srai %B0,15\;mv %A0,%B0
-   ld2w %C0,%M1\;mv %B0,%C0\;srai %B0,15\;mv %A0,%B0
-   ld2w %C0,%M1\;mv %B0,%C0\;srai %B0,15\;mv %A0,%B0"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "4,4,5")])
-
-
-;;
-;;  ....................
-;;
-;;	Addition
-;;
-;;  ....................
-
-(define_expand "addhi3"
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(plus:HI (match_operand:HI 1 "gpr_operand" "")
-		 (match_operand:HI 2 "arith16_operand" "")))]
-  ""
-  "")
-
-(define_insn "*addhi3_no_small_insns"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d,d")
-	(plus:HI (match_operand:HI 1 "gpr_operand" "%0,0,0,d")
-		 (match_operand:HI 2 "arith16_operand" "d,I,N,i")))]
-  "TARGET_NO_SMALL_INSNS || !optimize"
-  "@
-   add %0,%2
-   addi %0,%2
-   subi %0,%n2
-   add3 %0,%1,%2"
-  [(set_attr "type" "either,either,either,long")
-   (set_attr "length" "1,1,1,2")])
-
-(define_insn "*addhi3_small_insns"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d,d,d,d")
-	(plus:HI (match_operand:HI 1 "gpr_operand" "%0,0,0,d,d,d")
-		 (match_operand:HI 2 "arith16_operand" "d,I,N,I,N,i")))]
-  "TARGET_SMALL_INSNS && optimize"
-  "@
-   add %0,%2
-   addi %0,%2
-   subi %0,%n2
-   mv %0,%1\;addi %0,%2
-   mv %0,%1\;subi %0,%n2
-   add3 %0,%1,%2"
-  [(set_attr "type" "either,either,either,long,long,long")
-   (set_attr "length" "1,1,1,2,2,2")])
-
-(define_split
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(plus:HI (match_operand:HI 1 "gpr_operand" "")
-		 (match_operand:HI 2 "const_int_operand" "")))]
-  "reload_completed && TARGET_SMALL_INSNS && optimize
-   && REGNO (operands[0]) != REGNO (operands[1])
-   && IN_RANGE_P (INTVAL (operands[2]), -16, 16)
-   && INTVAL (operands[2]) != 0"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0) (plus:HI (match_dup 0) (match_dup 2)))]
-  "")
-
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn "*addsi3_noaccum"
-  [(set (match_operand:SI 0 "gpr_operand" "=e")
-	(plus:SI (match_operand:SI 1 "gpr_operand" "%0")
-		 (match_operand:SI 2 "gpr_operand" "e")))]
-  "!TARGET_ACCUM"
-  "add2w %0,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "*addsi3_noaddac3"
-  [(set (match_operand:SI 0 "register_operand" "=e,a")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,0")
-		 (match_operand:SI 2 "register_operand" "e,ea")))]
-  "TARGET_ACCUM && !TARGET_ADDAC3"
-  "@
-   add2w %0,%2
-   add %0,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "*addsi3_addac3"
-  [(set (match_operand:SI 0 "register_operand" "=e,e,a")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,ea,0")
-		 (match_operand:SI 2 "register_operand" "e,a,ea")))]
-  "TARGET_ACCUM && TARGET_ADDAC3"
-  "@
-   add2w %0,%2
-   addac3 %0,%1,%2
-   add %0,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_expand "adddi3"
-  [(parallel [(set (match_operand:DI 0 "gpr_operand" "")
-		   (plus:DI (match_operand:DI 1 "gpr_operand" "")
-			    (match_operand:DI 2 "arith_nonnegative_operand" "")))
-	      (clobber (match_dup 3))])]
-  "TARGET_LONGLONG_ALU"
-  "operands[3] = gen_rtx (REG, CCmode, F0_REGNUM);")
-
-(define_insn "*adddi3_internal"
-  [(parallel [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-		   (plus:DI (match_operand:DI 1 "gpr_operand" "%0,0,0")
-			    (match_operand:DI 2 "arith_nonnegative_operand" "e,I,M")))
-	      (clobber (match_operand:CC 3 "f0_operand" ""))])]
-  "TARGET_LONGLONG_ALU"
-  "* return emit_add (operands, insn);"
-  [(set_attr "type" "long")
-   (set_attr "length" "10,10,12")])
-
-
-;;
-;;  ....................
-;;
-;;	Subtraction
-;;
-;;  ....................
-
-(define_expand "subhi3"
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(minus:HI (match_operand:HI 1 "gpr_operand" "")
-		  (match_operand:HI 2 "arith16_operand" "")))]
-  ""
-  "")
-
-(define_insn "*subhi3_no_small_insns"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d,d")
-	(minus:HI (match_operand:HI 1 "gpr_operand" "0,0,0,d")
-		  (match_operand:HI 2 "arith16_operand" "d,I,N,i")))]
-  "TARGET_NO_SMALL_INSNS || !optimize"
-  "@
-   sub %0,%2
-   subi %0,%2
-   addi %0,%n2
-   add3 %0,%1,%n2"
-  [(set_attr "type" "either,either,either,long")
-   (set_attr "length" "1,1,1,2")])
-
-(define_insn "*subhi3_small_insns"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d,d,d,d")
-	(minus:HI (match_operand:HI 1 "gpr_operand" "0,0,0,d,d,d")
-		  (match_operand:HI 2 "arith16_operand" "d,I,N,I,N,i")))]
-  "TARGET_SMALL_INSNS && optimize"
-  "@
-   sub %0,%2
-   subi %0,%2
-   addi %0,%n2
-   mv %0,%1\;subi %0,%2
-   mv %0,%1\;addi %0,%n2
-   add3 %0,%1,%n2"
-  [(set_attr "type" "either,either,either,long,long,long")
-   (set_attr "length" "1,1,1,2,2,2")])
-
-(define_split
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(minus:HI (match_operand:HI 1 "gpr_operand" "")
-		  (match_operand:HI 2 "const_int_operand" "")))]
-  "reload_completed && TARGET_SMALL_INSNS && optimize
-   && REGNO (operands[0]) != REGNO (operands[1])
-   && IN_RANGE_P (INTVAL (operands[2]), -16, 16)
-   && INTVAL (operands[2]) != 0"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0) (minus:HI (match_dup 0) (match_dup 2)))]
-  "")
-
-
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 1 "register_operand" "")
-		  (match_operand:SI 2 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn "*subsi3_noaccum"
-  [(set (match_operand:SI 0 "gpr_operand" "=e")
-	(minus:SI (match_operand:SI 1 "gpr_operand" "0")
-		  (match_operand:SI 2 "gpr_operand" "e")))]
-  "!TARGET_ACCUM"
-  "sub2w %0,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "*subsi3_noaddac3"
-  [(set (match_operand:SI 0 "register_operand" "=e,a")
-	(minus:SI (match_operand:SI 1 "register_operand" "0,0")
-		 (match_operand:SI 2 "register_operand" "e,ea")))]
-  "TARGET_ACCUM && !TARGET_ADDAC3"
-  "@
-   sub2w %0,%2
-   sub %0,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "*subsi3_addac3"
-  [(set (match_operand:SI 0 "register_operand" "=e,e,a")
-	(minus:SI (match_operand:SI 1 "register_operand" "0,ea,0")
-		  (match_operand:SI 2 "register_operand" "e,a,ea")))]
-  "TARGET_ACCUM && TARGET_ADDAC3"
-  "@
-   sub2w %0,%2
-   subac3 %0,%1,%2
-   sub %0,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_expand "subdi3"
-  [(parallel [(set (match_operand:DI 0 "gpr_operand" "")
-		   (minus:DI (match_operand:DI 1 "gpr_operand" "")
-			     (match_operand:DI 2 "gpr_operand" "")))
-	      (clobber (match_dup 3))])]
-  "TARGET_LONGLONG_ALU"
-  "operands[3] = gen_rtx (REG, CCmode, F0_REGNUM);")
-
-(define_insn "*subdi3_internal1"
-  [(parallel [(set (match_operand:DI 0 "gpr_operand" "=e")
-		   (minus:DI (match_operand:DI 1 "gpr_operand" "0")
-			     (match_operand:DI 2 "gpr_operand" "e")))
-	      (clobber (match_operand:CC 3 "f0_operand" ""))])]
-  "TARGET_LONGLONG_ALU"
-  "* return emit_subtract (operands, insn);"
-  [(set_attr "type" "long")
-   (set_attr "length" "10")])
-
-
-;;
-;;  ....................
-;;
-;;	Negation
-;;
-;;  ....................
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(neg:HI (match_operand:HI 1 "gpr_operand" "0")))]
-  ""
-  "neg %0"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-(define_expand "negsi2"
-  [(parallel [(set (match_operand:SI 0 "register_operand" "")
-		   (neg:SI (match_operand:SI 1 "register_operand" "")))
-	      (clobber (match_dup 2))])]
-  ""
-  "operands[2] = gen_rtx (REG, CCmode, F0_REGNUM);")
-
-(define_insn "*negsi2_internal"
-  [(set (match_operand:SI 0 "register_operand" "=a,e")
-	(neg:SI (match_operand:SI 1 "register_operand" "0,0")))
-   (clobber (match_operand:CC 2 "f0_operand" ""))]
-  ""
-  "@
-   neg %0
-   not %U0\;neg %L0\;cmpeqi %L0,0\;exef0t || addi %U0,1"
-  [(set_attr "type" "iu,long")
-   (set_attr "length" "1,6")])
-
-(define_expand "negdi2"
-  [(parallel [(set (match_operand:DI 0 "gpr_operand" "")
-		   (neg:DI (match_operand:DI 1 "gpr_operand" "")))
-	      (clobber (match_dup 2))])]
-  "TARGET_LONGLONG_ALU"
-  "operands[2] = gen_rtx (REG, CCmode, F0_REGNUM);")
-
-(define_insn "*negdi2_internal"
-  [(set (match_operand:DI 0 "gpr_operand" "=e")
-	(neg:DI (match_operand:DI 1 "gpr_operand" "0")))
-   (clobber (match_operand:CC 2 "f0_operand" ""))]
-  "TARGET_LONGLONG_ALU"
-  "not %A0\;not %B0\;not %C0\;neg %D0\;cmpeqi %D0,0\;exef0t || addi %C0,1\;exef0t || cmpeqi %C0,0\;exef0t || addi %B0,1\;exef0t || cmpeqi %B0,0\;exef0t || addi %A0,1"
-  [(set_attr "type" "long")
-   (set_attr "length" "16")])
-
-
-;;
-;;  ....................
-;;
-;;	Multiplication
-;;
-;;  ....................
-
-(define_insn "mulhi3"
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(mult:HI (match_operand:HI 1 "gpr_operand" "%0")
-		 (match_operand:HI 2 "gpr_operand" "d")))]
-  ""
-  "mul %0,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "*mulhisi3_add"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(plus:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "gpr_operand" "%d"))
-			  (sign_extend:SI (match_operand:HI 2 "gpr_operand" "d")))
-		 (match_operand:SI 3 "register_operand" "0")))]
-  "TARGET_ACCUM"
-  "mac %0,%1,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "mulhisi3"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(mult:SI (sign_extend:SI (match_operand:HI 1 "gpr_operand" "%d"))
-		 (sign_extend:SI (match_operand:HI 2 "gpr_operand" "d"))))]
-  "TARGET_ACCUM"
-  "mulx %0,%1,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "*umulhisi3_add"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(plus:SI (mult:SI (zero_extend:SI (match_operand:HI 1 "gpr_operand" "%d"))
-			  (zero_extend:SI (match_operand:HI 2 "gpr_operand" "d")))
-		 (match_operand:SI 3 "register_operand" "0")))]
-  "TARGET_ACCUM"
-  "macu %0,%1,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "umulhisi3"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(mult:SI (zero_extend:SI (match_operand:HI 1 "gpr_operand" "%d"))
-		 (zero_extend:SI (match_operand:HI 2 "gpr_operand" "d"))))]
-  "TARGET_ACCUM"
-  "mulxu %0,%1,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "*mulhisi3_mixed_add1"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(plus:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "gpr_operand" "%d"))
-			  (zero_extend:SI (match_operand:HI 2 "gpr_operand" "d")))
-		 (match_operand:SI 3 "register_operand" "0")))]
-  "TARGET_ACCUM"
-  "macsu %0,%1,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "*mulhisi3_mixed1"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(mult:SI (sign_extend:SI (match_operand:HI 1 "gpr_operand" "%d"))
-		 (zero_extend:SI (match_operand:HI 2 "gpr_operand" "d"))))]
-  "TARGET_ACCUM"
-  "mulxsu %0,%1,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "*mulhisi3_mixed_add2"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(plus:SI (mult:SI (zero_extend:SI (match_operand:HI 1 "gpr_operand" "%d"))
-			  (sign_extend:SI (match_operand:HI 2 "gpr_operand" "d")))
-		 (match_operand:SI 3 "register_operand" "0")))]
-  "TARGET_ACCUM"
-  "macsu %0,%2,%1"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "*mulhisi3_mixed2"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(mult:SI (zero_extend:SI (match_operand:HI 1 "gpr_operand" "%d"))
-		 (sign_extend:SI (match_operand:HI 2 "gpr_operand" "d"))))]
-  "TARGET_ACCUM"
-  "mulxsu %0,%2,%1"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(mult:SI (match_operand:SI 1 "gpr_operand" "e")
-		 (match_operand:SI 2 "gpr_operand" "e")))]
-  "TARGET_ACCUM"
-  "#"
-  [(set_attr "type" "long")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(mult:SI (match_operand:SI 1 "gpr_operand" "")
-		 (match_operand:SI 2 "gpr_operand" "")))]
-  "TARGET_ACCUM && reload_completed"
-  [(set (match_dup 0)
-	(mult:SI (zero_extend:SI (match_dup 3))
-		 (zero_extend:SI (match_dup 6))))
-   (set (match_dup 0)
-	(plus:SI (mult:SI (zero_extend:SI (match_dup 4))
-			  (zero_extend:SI (match_dup 5)))
-		 (match_dup 0)))
-   (set (match_dup 0)
-	(ashift:SI (match_dup 0)
-		   (const_int 16)))
-   (set (match_dup 0)
-	(plus:SI (mult:SI (zero_extend:SI (match_dup 4))
-			  (zero_extend:SI (match_dup 6)))
-		 (match_dup 0)))]
-  "
-{
-  operands[3] = d10v_subword (operands[1], 0, HImode, SImode);
-  operands[4] = d10v_subword (operands[1], 1, HImode, SImode);
-
-  operands[5] = d10v_subword (operands[2], 0, HImode, SImode);
-  operands[6] = d10v_subword (operands[2], 1, HImode, SImode);
-}")
-
-
-;;
-;;  ....................
-;;
-;;	Division
-;;
-;;  ....................
-
-(define_expand "divmodhi4"
-  [(parallel [(set (match_operand:HI 0 "gpr_operand" "")
-		   (div:HI (match_operand:HI 1 "general_operand" "")
-			   (match_operand:HI 2 "general_operand" "")))
-	      (set (match_operand:HI 3 "gpr_operand" "")
-		   (mod:HI (match_dup 1)
-			   (match_dup 2)))])]
-  ""
-  "
-{
-  d10v_expand_divmod (operands, FALSE);
-  DONE;
-}")
-
-(define_expand "udivmodhi4"
-  [(parallel [(set (match_operand:HI 0 "gpr_operand" "")
-		   (udiv:HI (match_operand:HI 1 "general_operand" "")
-			    (match_operand:HI 2 "general_operand" "")))
-	      (set (match_operand:HI 3 "gpr_operand" "")
-		   (umod:HI (match_dup 1)
-			    (match_dup 2)))])]
-  ""
-  "
-{
-  d10v_expand_divmod (operands, TRUE);
-  DONE;
-}")
-
-
-;;
-;;  ....................
-;;
-;;	Logical operations
-;;
-;;  ....................
-
-(define_expand "andhi3"
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(and:HI (match_operand:HI 1 "gpr_operand" "")
-		(match_operand:HI 2 "arith16_operand" "")))]
-  ""
-  "")
-
-(define_insn "*andhi3_register"
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(and:HI (match_operand:HI 1 "gpr_operand" "%0")
-		(match_operand:HI 2 "gpr_operand" "d")))]
-  ""
-  "and %0,%2"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-(define_insn "*andhi3_move"
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(and:HI (match_operand:HI 1 "gpr_operand" "%d")
-		(match_operand:HI 2 "const_int_operand" "n")))]
-  "(INTVAL (operands[2]) & 0xffff) == 0xffff"
-  "mv %0,%1"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-(define_insn "*andhi3_constant"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d")
-	(and:HI (match_operand:HI 1 "gpr_operand" "%d,0,d")
-		(match_operand:HI 2 "const_int_operand" "O,J,n")))]
-  ""
-  "*
-{
-  HOST_WIDE_INT value = INTVAL (operands[2]);
-
-  if (value == 0)
-    return \"ldi %0,0\";
-
-  if ((value & 0xffff) == 0xffff)
-    return \"mv %0,%1\";
-
-  if (IN_RANGE_P (exact_log2 (~value), 0, 15))
-    {
-      if (REGNO (operands[0]) == REGNO (operands[1]))
-	return \"bclri %0,%b2\";
-
-      if (TARGET_SMALL_INSNS && optimize)
-	return \"mv %0,%1\;bclri %0,%b2\";
-    }
-
-  return \"and3 %0,%1,%2\";
-}"
-  [(set_attr "type" "either,iu,long")
-   (set_attr "length" "1,1,2")])
-
-(define_split
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(and:HI (match_operand:HI 1 "gpr_operand" "")
-		(match_operand:HI 2 "const_int_operand" "")))]
-  "reload_completed && TARGET_SMALL_INSNS && optimize
-   && !rtx_equal_p (operands[0], operands[1])
-   && IN_RANGE_P (exact_log2 (~ INTVAL (operands[2])), 0, 15)"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0) (and:HI (match_dup 0) (match_dup 2)))]
-  "")
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "gpr_operand" "=e,e,e")
-	(and:SI (match_operand:SI 1 "gpr_operand" "%0,0,?e")
-		(match_operand:SI 2 "arith32_operand" "e,n,n")))]
-  ""
-  "#"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "2,4,4")])
-
-(define_split
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(and:SI (match_operand:SI 1 "gpr_operand" "")
-		(match_operand:SI 2 "arith32_operand" "")))]
-  "reload_completed"
-  [(match_dup 3)]
-  "operands[3] = d10v_split_logical_op (operands, AND);")
-
-(define_insn "anddi3"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(and:DI (match_operand:DI 1 "gpr_operand" "0,0,?e")
-		(match_operand:DI 2 "arith64_operand" "e,nF,nF")))]
-  ""
-  "#"
-  [(set_attr "type" "long")
-   (set_attr "length" "4,8,8")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(and:DI (match_operand:DI 1 "gpr_operand" "")
-		(match_operand:DI 2 "arith64_operand" "")))]
-  "reload_completed"
-  [(match_dup 3)]
-  "operands[3] = d10v_split_logical_op (operands, AND);")
-
-(define_expand "iorhi3"
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(ior:HI (match_operand:HI 1 "gpr_operand" "")
-		(match_operand:HI 2 "arith16_operand" "")))]
-  ""
-  "")
-
-(define_insn "*iorhi3_register"
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(ior:HI (match_operand:HI 1 "gpr_operand" "%0")
-		(match_operand:HI 2 "gpr_operand" "d")))]
-  ""
-  "or %0,%2"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-(define_insn "*iorhi3_neg1"
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(ior:HI (match_operand:HI 1 "gpr_operand" "d")
-		(match_operand:HI 2 "const_int_operand" "n")))]
-  "(INTVAL (operands[2]) & 0xffff) == 0xffff"
-  "ldi %0,-1"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-(define_insn "*iorhi3_constant"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d")
-	(ior:HI (match_operand:HI 1 "gpr_operand" "%d,0,d")
-		(match_operand:HI 2 "const_int_operand" "O,P,n")))]
-  ""
-  "*
-{
-  HOST_WIDE_INT value = INTVAL (operands[2]);
-  int log = exact_log2 (value);
-
-  if (value == 0)
-    return \"mv %0,%1\";
-
-  if ((value & 0xffff) == 0xffff)
-    return \"ldi %0,-1\";
-
-  if (IN_RANGE_P (exact_log2 (value), 0, 15))
-    {
-      if (REGNO (operands[0]) == REGNO (operands[1]))
-	return \"bseti %0,%b2\";
-
-      if (TARGET_SMALL_INSNS && optimize)
-	return \"mv %0,%1\;bseti %0,%b2\";
-    }
-
-  return \"or3 %0,%1,%2\";
-}"
-  [(set_attr "type" "either,iu,long")
-   (set_attr "length" "1,1,2")])
-
-(define_split
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(ior:HI (match_operand:HI 1 "gpr_operand" "")
-		(match_operand:HI 2 "const_int_operand" "")))]
-  "reload_completed && TARGET_SMALL_INSNS && optimize
-   && !rtx_equal_p (operands[0], operands[1])
-   && IN_RANGE_P (exact_log2 (INTVAL (operands[2])), 0, 15)"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0) (ior:HI (match_dup 0) (match_dup 2)))]
-  "")
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "gpr_operand" "=e,e")
-	(ior:SI (match_operand:SI 1 "gpr_operand" "%0,e")
-		(match_operand:SI 2 "arith32_operand" "e,i")))]
-  ""
-  "#"
-  [(set_attr "type" "long,long")
-   (set_attr "length" "2,4")])
-
-(define_split
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(ior:SI (match_operand:SI 1 "gpr_operand" "")
-		(match_operand:SI 2 "arith32_operand" "")))]
-  "reload_completed"
-  [(match_dup 3)]
-  "operands[3] = d10v_split_logical_op (operands, IOR);")
-
-(define_insn "iordi3"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(ior:DI (match_operand:DI 1 "gpr_operand" "0,0,?e")
-		(match_operand:DI 2 "arith64_operand" "e,nF,nF")))]
-  ""
-  "#"
-  [(set_attr "type" "long")
-   (set_attr "length" "4,8,8")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(ior:DI (match_operand:DI 1 "gpr_operand" "")
-		(match_operand:DI 2 "arith64_operand" "")))]
-  "reload_completed"
-  [(match_dup 3)]
-  "operands[3] = d10v_split_logical_op (operands, IOR);")
-
-(define_expand "xorhi3"
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(xor:HI (match_operand:HI 1 "gpr_operand" "")
-		(match_operand:HI 2 "arith16_operand" "")))]
-  ""
-  "")
-
-(define_insn "*xorhi3_register"
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(xor:HI (match_operand:HI 1 "gpr_operand" "%0")
-		(match_operand:HI 2 "gpr_operand" "d")))]
-  ""
-  "xor %0,%2"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-(define_insn "*xorhi3_not"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,?d")
-	(xor:HI (match_operand:HI 1 "gpr_operand" "%0,d")
-		(match_operand:HI 2 "const_int_operand" "n,n")))]
-  "(INTVAL (operands[2]) & 0xffff) == 0xffff"
-  "@
-   not %0
-   mv %0,%1\;not %0"
-  [(set_attr "type" "either,long")
-   (set_attr "length" "1,2")])
-
-(define_split
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(xor:HI (match_operand:HI 1 "gpr_operand" "")
-		(match_operand:HI 2 "const_int_operand" "n")))]
-  "(INTVAL (operands[2]) & 0xffff) == 0xffff
-   && !rtx_equal_p (operands[0], operands[1])"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0) (not:HI (match_dup 0)))]
-  "")
-
-(define_insn "*xorhi3_constant"
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(xor:HI (match_operand:HI 1 "gpr_operand" "%d")
-		(match_operand:HI 2 "const_int_operand" "n")))]
-  ""
-  "*
-{
-  HOST_WIDE_INT value = INTVAL (operands[2]);
-  int log = exact_log2 (value);
-
-  if (value == 0)
-    return \"mv %0,%1\";
-
-  if ((value & 0xffff) == 0xffff && REGNO (operands[0]) == REGNO (operands[1]))
-    return \"not %0\";
-
-  if (IN_RANGE_P (exact_log2 (value), 0, 15))
-    {
-      if (REGNO (operands[0]) == REGNO (operands[1]))
-	return \"bnoti %0,%b2\";
-
-      if (TARGET_SMALL_INSNS && optimize)
-	return \"mv %0,%1\;bnoti %0,%b2\";
-    }
-
-  return \"xor3 %0,%1,%2\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(xor:HI (match_operand:HI 1 "gpr_operand" "")
-		(match_operand:HI 2 "const_int_operand" "")))]
-  "reload_completed && TARGET_SMALL_INSNS && optimize
-   && !rtx_equal_p (operands[0], operands[1])
-   && IN_RANGE_P (exact_log2 (INTVAL (operands[2])), 0, 15)"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0) (xor:HI (match_dup 0) (match_dup 2)))]
-  "")
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "gpr_operand" "=e,e")
-	(xor:SI (match_operand:SI 1 "gpr_operand" "%0,e")
-		(match_operand:SI 2 "arith32_operand" "e,i")))]
-  ""
-  "#"
-  [(set_attr "type" "long,long")
-   (set_attr "length" "2,4")])
-
-(define_split
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(xor:SI (match_operand:SI 1 "gpr_operand" "")
-		(match_operand:SI 2 "arith32_operand" "")))]
-  "reload_completed"
-  [(match_dup 3)]
-  "operands[3] = d10v_split_logical_op (operands, XOR);")
-
-(define_insn "xordi3"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(xor:DI (match_operand:DI 1 "gpr_operand" "0,0,?e")
-		(match_operand:DI 2 "arith64_operand" "e,nF,nF")))]
-  ""
-  "#"
-  [(set_attr "type" "long")
-   (set_attr "length" "4,8,8")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(xor:DI (match_operand:DI 1 "gpr_operand" "")
-		(match_operand:DI 2 "arith64_operand" "")))]
-  "reload_completed"
-  [(match_dup 3)]
-  "operands[3] = d10v_split_logical_op (operands, XOR);")
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(not:HI (match_operand:HI 1 "gpr_operand" "0")))]
-  ""
-  "not %0"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "gpr_operand" "=e")
-	(not:SI (match_operand:SI 1 "gpr_operand" "0")))]
-  ""
-  "#"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(not:SI (match_operand:SI 1 "gpr_operand" "")))]
-  "reload_completed"
-  [(match_dup 2)]
-  "operands[2] = d10v_split_logical_op (operands, NOT);")
-
-(define_insn "one_cmpldi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e")
-	(not:DI (match_operand:DI 1 "gpr_operand" "0")))]
-  ""
-  "#"
-  [(set_attr "type" "long")
-   (set_attr "length" "4")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(not:DI (match_operand:SI 1 "gpr_operand" "")))]
-  "reload_completed"
-  [(match_dup 2)]
-  "operands[2] = d10v_split_logical_op (operands, NOT);")
-
-
-;;
-;;  ....................
-;;
-;;	Shifts
-;;
-;;  ....................
-
-(define_expand "ashlhi3"
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(ashift:HI (match_operand:HI 1 "gpr_operand" "")
-		   (match_operand:HI 2 "arith16_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT && !IN_RANGE_P (INTVAL (operands[2]), 0, 15))
-    operands[2] = force_reg (HImode, operands[2]);
-}")
-
-(define_insn "*ashlhi3_internal"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d")
-	(ashift:HI (match_operand:HI 1 "gpr_operand" "0,0,0")
-		   (match_operand:HI 2 "arith16_operand" "I,O,d")))]
-  "GET_CODE (operands[2]) != CONST_INT || IN_RANGE_P (INTVAL (operands[2]), 0, 15)"
-  "@
-   slli %0,%2
-   nop
-   sll %0,%2"
-  [(set_attr "type" "iu,either,iu")
-   (set_attr "length" "1,1,1")])
-
-(define_expand "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashift:SI (match_operand:SI 1 "register_operand" "")
-		   (match_operand:HI 2 "arith16_operand" "")))]
-  ""
-  "
-{
-  if (!TARGET_ACCUM && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16))
-    FAIL;
-
-  if (GET_CODE (operands[2]) == CONST_INT && ((unsigned long)INTVAL (operands[2])) > 31)
-    operands[2] = force_reg (HImode, operands[2]);
-
-  if (GET_CODE (operands[2]) != CONST_INT)
-    {
-      emit_insn (gen_ashlsi3_variable (operands[0], operands[1], operands[2],
-				       gen_reg_rtx (HImode),
-				       gen_rtx (REG, CCmode, F0_REGNUM),
-				       gen_rtx (REG, HImode, GPR_ZERO_REGNUM)));
-      DONE;
-    }
-}")
-
-(define_insn "*ashlsi3_16"
-  [(set (match_operand:SI 0 "register_operand" "=e,a")
-	(ashift:SI (match_operand:SI 1 "register_operand" "e,0")
-		   (const_int 16)))]
-  ""
-  "@
-   mv %U0,%L1\;ldi %L0,0
-   slli %0,16"
-  [(set_attr "type" "long,long")
-   (set_attr "length" "2,2")])
-
-(define_insn "*ashlsi3_constant"
-  [(set (match_operand:SI 0 "accum_operand" "=a,a,a")
-	(ashift:SI (match_operand:SI 1 "accum_operand" "0,0,0")
-		   (match_operand:SI 2 "const_int_operand" "I,O,n")))]
-  "TARGET_ACCUM && ((unsigned HOST_WIDE_INT)INTVAL (operands[2])) <= 31"
-  "*
-{
-  HOST_WIDE_INT shift_value = INTVAL (operands[2]);
-
-  if (shift_value == 0)
-    return \"\";
-
-  if (shift_value <= 16)
-    return \"slli %0,%2\";
-
-  operands[3] = GEN_INT (16);
-  operands[4] = GEN_INT (shift_value - 16);
-  return \"slli %0,%3\;slli %0,%4\";
-}"
-  [(set_attr "type" "iu,either,long")
-   (set_attr "length" "1,1,2")])
-
-(define_insn "ashlsi3_variable"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(ashift:SI (match_operand:SI 1 "accum_operand" "0")
-		   (match_operand:HI 2 "gpr_operand" "d")))
-   (clobber (match_operand:HI 3 "gpr_operand" "=&d"))
-   (clobber (match_operand:CC 4 "f0_operand" ""))
-   (use (match_operand:HI 5 "gpr_operand" "d"))
-   (use (const_int 0))]
-  "TARGET_ACCUM"
-  "#"
-  [(set_attr "type" "long")
-   (set_attr "length" "10")])
-
-(define_insn "*ashlsi3_variable2"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(ashift:SI (match_operand:SI 1 "accum_operand" "0")
-		   (match_operand:HI 2 "gpr_operand" "d")))
-   (use (const_int 1))]
-  "TARGET_ACCUM"
-  "sll %0,%2"
-  [(set_attr "type" "long")
-   (set_attr "length" "1")])
-
-(define_split
-  [(set (match_operand:SI 0 "accum_operand" "")
-	(ashift:SI (match_operand:SI 1 "accum_operand" "")
-		   (match_operand:HI 2 "gpr_operand" "")))
-   (clobber (match_operand:HI 3 "gpr_operand" ""))
-   (clobber (match_operand:CC 4 "f0_operand" ""))
-   (use (match_operand:HI 5 "gpr_operand" ""))
-   (use (const_int 0))]
-  "TARGET_ACCUM && reload_completed"
-  [(set (match_dup 3)
-	(and:HI (match_dup 2)
-		(const_int 15)))
-   (parallel [(set (match_dup 0)
-		   (ashift:SI (match_dup 0)
-			      (match_dup 3)))
-	      (use (const_int 1))])
-   (set (match_dup 3)
-	(plus:HI (match_dup 2)
-		 (const_int -15)))
-   (parallel [(set (match_dup 3)
-		   (smax:HI (match_dup 3)
-			    (match_dup 5)))
-	      (clobber (match_dup 4))])
-   (parallel [(set (match_dup 0)
-		   (ashift:SI (match_dup 0)
-			      (match_dup 3)))
-	      (use (const_int 1))])]
-  "")
-
-(define_expand "ashrhi3"
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(ashiftrt:HI (match_operand:HI 1 "gpr_operand" "")
-		     (match_operand:HI 2 "arith16_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT && !IN_RANGE_P (INTVAL (operands[2]), 0, 15))
-    operands[2] = force_reg (HImode, operands[2]);
-}")
-
-(define_insn "*ashrhi3_internal"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d")
-	(ashiftrt:HI (match_operand:HI 1 "gpr_operand" "0,0,0")
-		     (match_operand:HI 2 "arith16_operand" "I,O,d")))]
-  "GET_CODE (operands[2]) != CONST_INT || IN_RANGE_P (INTVAL (operands[2]), 0, 15)"
-  "@
-   srai %0,%2
-   nop
-   sra %0,%2"
-  [(set_attr "type" "iu,either,iu")
-   (set_attr "length" "1,1,1")])
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:HI 2 "arith16_operand" "")))]
-  ""
-  "
-{
-  if (!TARGET_ACCUM && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16))
-    FAIL;
-
-  if (GET_CODE (operands[2]) == CONST_INT && ((unsigned long)INTVAL (operands[2])) > 31)
-    operands[2] = force_reg (HImode, operands[2]);
-
-  if (GET_CODE (operands[2]) != CONST_INT)
-    {
-      emit_insn (gen_ashrsi3_variable (operands[0], operands[1], operands[2],
-				       gen_reg_rtx (HImode),
-				       gen_rtx (REG, CCmode, F0_REGNUM),
-				       gen_rtx (REG, HImode, GPR_ZERO_REGNUM)));
-      DONE;
-    }
-}")
-
-(define_insn "*ashrsi3_16"
-  [(set (match_operand:SI 0 "register_operand" "=e,e,a")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,e,0")
-		     (const_int 16)))]
-  ""
-  "@
-   mv %L0,%U1\;srai %U0,15
-   mv %L0,%U1\;mv %U0,%U1\;srai %U0,15
-   srai %0,16"
-  [(set_attr "type" "long,long,long")
-   (set_attr "length" "2,3,2")])
-
-(define_insn "*ashrsi3_constant"
-  [(set (match_operand:SI 0 "accum_operand" "=a,a,a")
-	(ashiftrt:SI (match_operand:SI 1 "accum_operand" "0,0,0")
-		     (match_operand:SI 2 "const_int_operand" "I,O,n")))]
-  "TARGET_ACCUM && ((unsigned HOST_WIDE_INT)INTVAL (operands[2])) <= 31"
-  "*
-{
-  HOST_WIDE_INT shift_value = INTVAL (operands[2]);
-
-  if (shift_value == 0)
-    return \"\";
-
-  if (shift_value <= 16)
-    return \"srai %0,%2\";
-
-  operands[3] = GEN_INT (16);
-  operands[4] = GEN_INT (shift_value - 16);
-  return \"srai %0,%3\;srai %0,%4\";
-}"
-  [(set_attr "type" "iu,either,long")
-   (set_attr "length" "1,1,2")])
-
-(define_insn "ashrsi3_variable"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(ashiftrt:SI (match_operand:SI 1 "accum_operand" "0")
-		     (match_operand:HI 2 "gpr_operand" "d")))
-   (clobber (match_operand:HI 3 "gpr_operand" "=&d"))
-   (clobber (match_operand:CC 4 "f0_operand" ""))
-   (use (match_operand:HI 5 "gpr_operand" "d"))
-   (use (const_int 0))]
-  "TARGET_ACCUM"
-  "#"
-  [(set_attr "type" "long")
-   (set_attr "length" "10")])
-
-(define_insn "*ashrsi3_variable2"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(ashiftrt:SI (match_operand:SI 1 "accum_operand" "0")
-		     (match_operand:HI 2 "gpr_operand" "d")))
-   (use (const_int 1))]
-  "TARGET_ACCUM"
-  "sra %0,%2"
-  [(set_attr "type" "long")
-   (set_attr "length" "1")])
-
-(define_split
-  [(set (match_operand:SI 0 "accum_operand" "")
-	(ashiftrt:SI (match_operand:SI 1 "accum_operand" "")
-		     (match_operand:HI 2 "gpr_operand" "")))
-   (clobber (match_operand:HI 3 "gpr_operand" ""))
-   (clobber (match_operand:CC 4 "f0_operand" ""))
-   (use (match_operand:HI 5 "gpr_operand" ""))
-   (use (const_int 0))]
-  "TARGET_ACCUM && reload_completed"
-  [(set (match_dup 3)
-	(and:HI (match_dup 2)
-		(const_int 15)))
-   (parallel [(set (match_dup 0)
-		   (ashiftrt:SI (match_dup 0)
-				(match_dup 3)))
-	      (use (const_int 1))])
-   (set (match_dup 3)
-	(plus:HI (match_dup 2)
-		 (const_int -15)))
-   (parallel [(set (match_dup 3)
-		   (smax:HI (match_dup 3)
-			    (match_dup 5)))
-	      (clobber (match_dup 4))])
-   (parallel [(set (match_dup 0)
-		   (ashiftrt:SI (match_dup 0)
-				(match_dup 3)))
-	      (use (const_int 1))])]
-  "")
-
-(define_expand "lshrhi3"
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(lshiftrt:HI (match_operand:HI 1 "gpr_operand" "")
-		     (match_operand:HI 2 "arith16_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT && !IN_RANGE_P (INTVAL (operands[2]), 0, 15))
-    operands[2] = force_reg (HImode, operands[2]);
-}")
-
-(define_insn "*lshrhi3_internal"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d")
-	(lshiftrt:HI (match_operand:HI 1 "gpr_operand" "0,0,0")
-		     (match_operand:HI 2 "arith16_operand" "I,O,d")))]
-  "GET_CODE (operands[2]) != CONST_INT || IN_RANGE_P (INTVAL (operands[2]), 0, 15)"
-  "@
-   srli %0,%2
-   nop
-   srl %0,%2"
-  [(set_attr "type" "iu,either,iu")
-   (set_attr "length" "1,1,1")])
-
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:HI 2 "arith16_operand" "")))]
-  ""
-  "
-{
-  if (!TARGET_ACCUM && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16))
-    FAIL;
-
-  if (GET_CODE (operands[2]) == CONST_INT && ((unsigned long)INTVAL (operands[2])) > 31)
-    operands[2] = force_reg (HImode, operands[2]);
-
-  if (GET_CODE (operands[2]) != CONST_INT)
-    {
-      emit_insn (gen_lshrsi3_variable (operands[0], operands[1], operands[2],
-				       gen_reg_rtx (HImode),
-				       gen_rtx (REG, CCmode, F0_REGNUM),
-				       gen_rtx (REG, HImode, GPR_ZERO_REGNUM)));
-      DONE;
-    }
-}")
-
-(define_insn "*lshlsi3_16"
-  [(set (match_operand:SI 0 "register_operand" "=e,a")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "e,0")
-		     (const_int 16)))]
-  ""
-  "@
-   mv %L0,%U1\;ldi %U0,0
-   srli %0,16"
-  [(set_attr "type" "long,long")
-   (set_attr "length" "2,2")])
-
-(define_insn "*lshlsi3_constant"
-  [(set (match_operand:SI 0 "accum_operand" "=a,a,a")
-	(lshiftrt:SI (match_operand:SI 1 "accum_operand" "0,0,0")
-		     (match_operand:SI 2 "const_int_operand" "I,O,n")))]
-  "TARGET_ACCUM && ((unsigned HOST_WIDE_INT)INTVAL (operands[2])) <= 31"
-  "*
-{
-  HOST_WIDE_INT shift_value = INTVAL (operands[2]);
-
-  if (shift_value == 0)
-    return \"\";
-
-  if (shift_value <= 16)
-    return \"srli %0,%2\";
-
-  operands[3] = GEN_INT (16);
-  operands[4] = GEN_INT (shift_value - 16);
-  return \"srli %0,%3\;srli %0,%4\";
-}"
-  [(set_attr "type" "iu,either,long")
-   (set_attr "length" "1,1,2")])
-
-(define_insn "lshrsi3_variable"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(lshiftrt:SI (match_operand:SI 1 "accum_operand" "0")
-		     (match_operand:HI 2 "gpr_operand" "d")))
-   (clobber (match_operand:HI 3 "gpr_operand" "=&d"))
-   (clobber (match_operand:CC 4 "f0_operand" ""))
-   (use (match_operand:HI 5 "gpr_operand" "d"))
-   (use (const_int 0))]
-  "TARGET_ACCUM"
-  "#"
-  [(set_attr "type" "long")
-   (set_attr "length" "10")])
-
-(define_insn "*lshrsi3_variable2"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(lshiftrt:SI (match_operand:SI 1 "accum_operand" "0")
-		     (match_operand:HI 2 "gpr_operand" "d")))
-   (use (const_int 1))]
-  "TARGET_ACCUM"
-  "srl %0,%2"
-  [(set_attr "type" "long")
-   (set_attr "length" "1")])
-
-(define_split
-  [(set (match_operand:SI 0 "accum_operand" "")
-	(lshiftrt:SI (match_operand:SI 1 "accum_operand" "")
-		     (match_operand:HI 2 "gpr_operand" "")))
-   (clobber (match_operand:HI 3 "gpr_operand" ""))
-   (clobber (match_operand:CC 4 "f0_operand" ""))
-   (use (match_operand:HI 5 "gpr_operand" ""))
-   (use (const_int 0))]
-  "TARGET_ACCUM && reload_completed"
-  [(set (match_dup 3)
-	(and:HI (match_dup 2)
-		(const_int 15)))
-   (parallel [(set (match_dup 0)
-		   (lshiftrt:SI (match_dup 0)
-				(match_dup 3)))
-	      (use (const_int 1))])
-   (set (match_dup 3)
-	(plus:HI (match_dup 2)
-		 (const_int -15)))
-   (parallel [(set (match_dup 3)
-		   (smax:HI (match_dup 3)
-			    (match_dup 5)))
-	      (clobber (match_dup 4))])
-   (parallel [(set (match_dup 0)
-		   (lshiftrt:SI (match_dup 0)
-				(match_dup 3)))
-	      (use (const_int 1))])]
-  "")
-
-
-;;
-;;  ....................
-;;
-;;	Min/max/abs
-;;
-;;  ....................
-
-(define_expand "sminhi3"
-  [(parallel [(set (match_operand:HI 0 "gpr_operand" "")
-		   (smin:HI (match_operand:HI 1 "gpr_operand" "")
-			    (match_operand:HI 2 "reg_or_0_operand" "")))
-	      (clobber (match_dup 3))])]
-  ""
-  "operands[3] = gen_rtx (REG, CCmode, F0_REGNUM);")
-
-(define_insn "*sminhi3_internal"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d")
-	(smin:HI (match_operand:HI 1 "gpr_operand" "%0,0")
-		 (match_operand:HI 2 "reg_or_0_operand" "d,O")))
-   (clobber (match_operand:CC 3 "f0_operand" ""))]
-  ""
-  "@
-   min %0,%2
-   min %0,%."
-  [(set_attr "type" "iu,iu")
-   (set_attr "length" "1,1")])
-
-(define_expand "sminsi3"
-  [(parallel [(set (match_operand:SI 0 "gpr_operand" "")
-		   (smin:SI (match_operand:SI 1 "gpr_operand" "")
-			    (match_operand:SI 2 "gpr_operand" "")))
-	      (clobber (match_dup 3))])]
-  "TARGET_ACCUM"
-  "operands[3] = gen_rtx (REG, CCmode, F0_REGNUM);")
-
-(define_insn "*sminsi3_internal"
-  [(set (match_operand:SI 0 "gpr_operand" "=a")
-	(smin:SI (match_operand:SI 1 "gpr_operand" "%0")
-		 (match_operand:SI 2 "gpr_operand" "ad")))
-   (clobber (match_operand:CC 3 "f0_operand" ""))]
-  "TARGET_ACCUM"
-  "min %0,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_expand "smaxhi3"
-  [(parallel [(set (match_operand:HI 0 "gpr_operand" "")
-		   (smax:HI (match_operand:HI 1 "gpr_operand" "")
-			    (match_operand:HI 2 "reg_or_0_operand" "")))
-	      (clobber (match_dup 3))])]
-  ""
-  "operands[3] = gen_rtx (REG, CCmode, F0_REGNUM);")
-
-(define_insn "*smaxhi3_internal"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d")
-	(smax:HI (match_operand:HI 1 "gpr_operand" "%0,0")
-		 (match_operand:HI 2 "reg_or_0_operand" "d,O")))
-   (clobber (match_operand:CC 3 "f0_operand" ""))]
-  ""
-  "@
-   max %0,%2
-   max %0,%."
-  [(set_attr "type" "iu,iu")
-   (set_attr "length" "1,1")])
-
-(define_expand "smaxsi3"
-  [(parallel [(set (match_operand:SI 0 "register_operand" "")
-		   (smax:SI (match_operand:SI 1 "register_operand" "")
-			    (match_operand:SI 2 "register_operand" "")))
-	      (clobber (match_dup 3))])]
-  "TARGET_ACCUM"
-  "operands[3] = gen_rtx (REG, CCmode, F0_REGNUM);")
-
-(define_insn "*smaxsi3_internal"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(smax:SI (match_operand:SI 1 "register_operand" "%0")
-		 (match_operand:SI 2 "register_operand" "ad")))
-   (clobber (match_operand:CC 3 "f0_operand" ""))]
-  "TARGET_ACCUM"
-  "max %0,%2"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_expand "abshi2"
-  [(parallel [(set (match_operand:HI 0 "gpr_operand" "")
-		   (abs:HI (match_operand:HI 1 "gpr_operand" "")))
-	      (clobber (match_dup 3))])]
-  ""
-  "operands[3] = gen_rtx (REG, CCmode, F0_REGNUM);")
-
-(define_insn "*abshi2_internal"
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(abs:HI (match_operand:HI 1 "gpr_operand" "0")))
-   (clobber (match_operand:CC 3 "f0_operand" ""))]
-  ""
-  "abs %0"
-  [(set_attr "type" "either")
-   (set_attr "length" "1")])
-
-(define_expand "abssi2"
-  [(parallel [(set (match_operand:SI 0 "register_operand" "")
-		   (abs:SI (match_operand:SI 1 "register_operand" "")))
-	      (clobber (match_dup 3))])]
-  "TARGET_ACCUM"
-  "operands[3] = gen_rtx (REG, CCmode, F0_REGNUM);")
-
-(define_insn "*abssi2_internal"
-  [(set (match_operand:SI 0 "accum_operand" "=a")
-	(abs:SI (match_operand:SI 1 "register_operand" "0")))
-   (clobber (match_operand:CC 3 "f0_operand" ""))]
-  "TARGET_ACCUM"
-  "abs %0"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-
-;;
-;;  ....................
-;;
-;;	Peepholes
-;;
-;;  ....................
-
-(define_peephole
-  [(set (match_operand:HI 0 "gpr_operand" "=e") (match_operand:HI 1 "gpr_operand" "e"))
-   (set (match_operand:HI 2 "gpr_operand" "=d") (match_operand:HI 3 "gpr_operand" "d"))]
-  "((REGNO (operands[0]) & 1) == 0 && (REGNO (operands[2]) == REGNO (operands[0]) + 1)
-    && (REGNO (operands[1]) & 1) == 0 && (REGNO (operands[3]) == REGNO (operands[1]) + 1))"
-  "mv2w %0,%1"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_peephole
-  [(set (match_operand:HI 0 "gpr_operand" "=d") (match_operand:HI 1 "gpr_operand" "d"))
-   (set (match_operand:HI 2 "gpr_operand" "=e") (match_operand:HI 3 "gpr_operand" "e"))]
-  "((REGNO (operands[2]) & 1) == 0 && (REGNO (operands[2]) == REGNO (operands[0]) - 1)
-    && (REGNO (operands[3]) & 1) == 0 && (REGNO (operands[3]) == REGNO (operands[1]) - 1))"
-  "mv2w %2,%3"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_peephole
-  [(set (match_operand:HI 0 "gpr_operand" "=e,e") (match_operand:HI 1 "memory_operand" "Q,m"))
-   (set (match_operand:HI 2 "gpr_operand" "=d,d") (match_operand:HI 3 "memory_operand" "Q,m"))]
-  "((REGNO (operands[0]) & 1) == 0 && (REGNO (operands[2]) == REGNO (operands[0]) + 1)
-   && adjacent_memory_operands (operands[1], operands[3], insn)
-   && !reg_mentioned_p (operands[0], operands[3]))"
-  "ld2w %0,%M1"
-  [(set_attr "type" "mu,mu")
-   (set_attr "length" "1,2")])
-
-(define_peephole
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d") (match_operand:HI 1 "memory_operand" "Q,m"))
-   (set (match_operand:HI 2 "gpr_operand" "=e,e") (match_operand:HI 3 "memory_operand" "Q,m"))]
-  "((REGNO (operands[2]) & 1) == 0 && (REGNO (operands[2]) == REGNO (operands[0]) - 1)
-   && adjacent_memory_operands (operands[3], operands[1], insn)
-   && !reg_mentioned_p (operands[0], operands[3]))"
-  "ld2w %2,%M3"
-  [(set_attr "type" "mu,mu")
-   (set_attr "length" "1,2")])
-
-(define_peephole
-  [(set (match_operand:HI 0 "memory_operand" "=Q,m") (match_operand:HI 1 "gpr_operand" "e,e"))
-   (set (match_operand:HI 2 "memory_operand" "=Q,m") (match_operand:HI 3 "gpr_operand" "d,d"))]
-  "((REGNO (operands[1]) & 1) == 0 && (REGNO (operands[3]) == REGNO (operands[1]) + 1)
-   && adjacent_memory_operands (operands[0], operands[2], insn))"
-  "st2w %1,%M0"
-  [(set_attr "type" "mu,mu")
-   (set_attr "length" "1,2")])
-
-(define_peephole
-  [(set (match_operand:HI 0 "memory_operand" "=Q,m") (match_operand:HI 1 "gpr_operand" "d,d"))
-   (set (match_operand:HI 2 "memory_operand" "=Q,m") (match_operand:HI 3 "gpr_operand" "e,e"))]
-  "((REGNO (operands[3]) & 1) == 0 && (REGNO (operands[3]) == REGNO (operands[1]) - 1)
-   && adjacent_memory_operands (operands[2], operands[0], insn))"
-  "st2w %3,%M2"
-  [(set_attr "type" "mu,mu")
-   (set_attr "length" "1,2")])
-
-;; Peepholes for tst0i, tst1i, and btsti instructions
-(define_peephole
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(and:HI (match_operand:HI 1 "gpr_operand" "d")
-		(match_operand:HI 2 "const_int_operand" "n")))
-   (set (match_operand:CC_REV 3 "f0_operand" "")
-	(ne:CC_REV (match_dup 0)
-		   (const_int 0)))
-   (set (pc)
-	(if_then_else (match_operator:CC 4 "f0_compare_operator"
-					 [(match_dup 3)
-					  (const_int 0)])
-		      (match_operand 5 "pc_or_label_operand" "")
-		      (match_operand 6 "pc_or_label_operand" "")))]
-  "IN_RANGE_P (exact_log2 (INTVAL (operands[2])), 0, 15)
-   && find_regno_note (prev_nonnote_insn (insn), REG_DEAD, REGNO (operands[0]))
-   && find_regno_note (insn, REG_DEAD, F0_REGNUM)"
-  "*
-{
-  operands[7] = GEN_INT (15 - exact_log2 (INTVAL (operands[2])));
-  output_asm_insn (\"btsti %1,%7\", operands);
-
-  if (operands[5] == pc_rtx)
-    return (GET_CODE (operands[6]) == RETURN) ? \"jmp r13 || exef0%T4\" : \"brf0%F4 %l6\";
-  else
-    return (GET_CODE (operands[5]) == RETURN) ? \"jmp r13 || exef0%F4\" : \"brf0%T4 %l5\";
-}"
-  [(set_attr "type" "long")
-   (set_attr "length" "4")])
-
-(define_peephole
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(and:HI (not:HI (match_operand:HI 1 "gpr_operand" "d"))
-		(match_operand:HI 2 "const_int_operand" "n")))
-   (set (match_operand:CC_REV 3 "f0_operand" "")
-	(ne:CC (match_dup 0)
-	       (const_int 0)))]
-  "find_regno_note (insn, REG_DEAD, REGNO (operands[0]))"
-  "tst1i %1,%2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-
-(define_peephole
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(and:HI (match_operand:HI 1 "gpr_operand" "d")
-		(match_operand:HI 2 "const_int_operand" "n")))
-   (set (match_operand:CC 3 "f0_operand" "")
-	(eq:CC_REV (match_dup 0)
-		   (const_int 0)))]
-  "IN_RANGE_P (exact_log2 (INTVAL (operands[2])), 0, 15)
-   && find_regno_note (insn, REG_DEAD, REGNO (operands[0]))"
-  "*
-{
-  operands[4] = GEN_INT (15 - exact_log2 (INTVAL (operands[2])));
-  return \"btsti %1,%4\";
-}"
-  [(set_attr "type" "iu")
-   (set_attr "length" "1")])
-
-(define_peephole
-  [(set (match_operand:HI 0 "gpr_operand" "=d")
-	(and:HI (match_operand:HI 1 "gpr_operand" "d")
-		(match_operand:HI 2 "const_int_operand" "n")))
-   (set (match_operand:CC 3 "f0_operand" "")
-	(eq:CC_REV (match_dup 0)
-		   (const_int 0)))]
-  "!IN_RANGE_P (exact_log2 (INTVAL (operands[2])), 0, 15)
-   && find_regno_note (insn, REG_DEAD, REGNO (operands[0]))"
-  "tst0i %1,%2"
-  [(set_attr "type" "long")
-   (set_attr "length" "2")])
-;; END CYGNUS LOCAL -- meissner/d10v abi change
diff --git a/gcc/config/d10v/libgcc1.asm b/gcc/config/d10v/libgcc1.asm
deleted file mode 100755
index 2ee2040..0000000
--- a/gcc/config/d10v/libgcc1.asm
+++ /dev/null
@@ -1,556 +0,0 @@
-/* Assembly support functions for libgcc1.
- *
- *   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
- *   Contributed by Cygnus Support
- * 
- * This file is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- * 
- * In addition to the permissions in the GNU General Public License, the
- * Free Software Foundation gives you unlimited permission to link the
- * compiled version of this file with other programs, and to distribute
- * those programs without any restriction coming from the use of this
- * file.  (The General Public License restrictions do apply in other
- * respects; for example, they cover modification of the file, and
- * distribution when not linked into another program.)
- * 
- * This file is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, 59 Temple Place - Suite 330,
- * Boston, MA 02111-1307, USA.
- * 
- *    As a special exception, if you link this library with files
- *    compiled with GCC to produce an executable, this does not cause
- *    the resulting executable to be covered by the GNU General Public License.
- *    This exception does not however invalidate any other reasons why
- *    the executable file might be covered by the GNU General Public License.
- */
-
-
-#ifdef L_ashlsi3
-/* Shift of 32 bit int left, r0-r1 == value to be shifted, r2 = shift amount */	
-
-	.file	"_ashlsi3.s"
-	.text
-	.globl	__ashlsi3
-	.type	__ashlsi3,@function
-__ashlsi3:
-	mv2wfac r4,a0				/* preserve accumulator & guard digits */
-	mvfacg	r12,a0
-	mv2wtac r0,a0
-	cmpui	r2,16
-	and3	r0,r2,15
-	exef0f || slli a0,16
-	sll	a0,r0
-	mv2wfac r0,a0
-	mv2wtac	r4,a0
-	mvtacg	r12,a0
-	jmp	r13
-	.size	__ashlsi3,.-__ashlsi3
-#endif
-
-#ifdef L_ashrsi3
-/* Shift of 32 bit signed int right, r0-r1 == value to be shifted, r2 = shift amount */	
-
-	.file	"_ashrsi3.s"
-	.text
-	.globl	__ashrsi3
-	.type	__ashrsi3,@function
-__ashrsi3:
-	mv2wfac r4,a0				/* preserve accumulator & guard digits */
-	mvfacg	r12,a0
-	mv2wtac r0,a0
-	cmpui	r2,16
-	and3	r0,r2,15
-	exef0f || srai a0,16
-	sra	a0,r0
-	mv2wfac r0,a0
-	mv2wtac	r4,a0
-	mvtacg	r12,a0
-	jmp	r13
-	.size	__ashrsi3,.-__ashrsi3
-#endif
-
-#ifdef L_lshrsi3
-/* Shift of 32 bit unsigned int right, r0-r1 == value to be shifted, r2 = shift amount */	
-
-	.file	"_lshrsi3.s"
-	.text
-	.globl	__lshrsi3
-	.type	__lshrsi3,@function
-__lshrsi3:
-	mv2wfac r4,a0				/* preserve accumulator & guard digits */
-	mvfacg	r12,a0
-	mv2wtac r0,a0
-	mvtacg	r14,a0				/* zero guard digits */
-	cmpui	r2,16
-	and3	r0,r2,15
-	exef0f || srli a0,16
-	srl	a0,r0
-	mv2wfac r0,a0
-	mv2wtac	r4,a0
-	mvtacg	r12,a0
-	jmp	r13
-	.size	__lshrsi3,.-__lshrsi3
-#endif
-
-#ifdef L_mulsi3
-/* Multiply 2 32-bit signed integers with a 32-bit result, r0-r1 = first number,
-   r2-r3 = second number.  */
-
-	.file	"_mulsi3.s"
-	.text
-	.globl	__mulsi3
-	.type	__mulsi3,@function
-__mulsi3:
-	mv2wfac r4,a0				/* preserve accumulator & guard digits */
-	mvfacg	r12,a0
-	mulxu	a0,r0,r3
-	macu	a0,r1,r2
-	slli	a0,16
-	macu	a0,r1,r3
-	mv2wfac r0,a0
-	mv2wtac	r4,a0
-	mvtacg	r12,a0
-	jmp	r13
-	.size	__mulsi3,.-__mulsi3
-#endif
-
-
-#ifdef L_udivmodhi4
-/* Unsigned divide 2 16-bit numbers, leaving the remainder in r0, and quotient
-   in r1.  */
-
-	.file	"_udivmodhi4.s"
-	.text
-	.globl	__udivmodhi4
-	.type	__udivmodhi4,@function
-	.globl	__umodhi3
-	.type	__umodhi3,@function
-__udivmodhi4:
-__umodhi3:
-	mv	r2,r1 -> mv r1,r0	/* move divisor to safe register & create 32-bit value for dividend */
-	ldi	r0,0			/* high part of dividend */
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	jmp	r13
-	.size	__udivmodhi4,.-__udivmodhi4
-	.size	__umodhi3,.-__umodhi3
-
-	.globl	__udivhi3
-	.type	__udivhi3,@function
-__udivhi3:
-	st	r13,@-sp
-	bl	__udivmodhi4
-	mv	r0,r1
-	ld	r13,@sp+
-	jmp	r13
-	.size	__udivhi3,.-__udivhi3
-#endif
-
-
-#ifdef L_divmodhi4
-/* Signed divide 2 16-bit numbers, leaving the remainder in r0, and quotient
-   in r1.  */
-
-	.file	"_divmodhi4.s"
-	.text
-	.globl	__divmodhi4
-	.type	__divmodhi4,@function
-	.globl	__modhi3
-	.type	__modhi3,@function
-__divmodhi4:
-__modhi3:
-	mv	r2,r1	-> mv r1,r0	/* move divisor to safe register & create 32-bit value for dividend */
-	ldi	r0,0	|| abs r1	/* high part of dividend */
-	abs	r2	|| nop		/* make sure divisor & dividend are positive (F0/F1 indicate if args were negative) */
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	divs	r0,r2
-	exef1t || neg r0
-	exef0t || neg r1
-	exef1t || neg r1
-	jmp	r13
-	.size	__divmodhi4,.-__divmodhi4
-	.size	__modhi3,.-__modhi3
-
-	.globl	__divhi3
-	.type	__divhi3,@function
-__divhi3:
-	st	r13,@-sp
-	bl	__divmodhi4
-	mv	r0,r1
-	ld	r13,@sp+
-	jmp	r13
-	.size	__divhi3,.-__divhi3
-#endif
-
-
-#ifdef L_udivmodsi4
-/* Unsigned divide 2 32-bit numbers, leaving the remainder in r0-r1, and quotient
-   in r2-r3.  */
-
-	.file	"_udivmodsi4.s"
-	.text
-	.globl	__udivmodsi4
-	.type	__udivmodsi4,@function
-	.globl	__udivsi3
-	.type	__udivsi3,@function
-	/* input:	r0-r1 = dividend, r2-r3 = divisor */
-	/* output:	r0-r1 = quotient, r2-r3 = remainder */
-__udivmodsi4:
-__udivsi3:
-	cmpeqi	r0,0 ->	brf0f.s	.Llong	/* if we are doing short/short do it with divs */
-	cmpeqi	r2,0 -> brf0f.s	.Llong
-
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	divs	r0,r3
-	mv	r3,r0
-	ldi	r0,0
-	jmp	r13
-
-.Llong:
-	st2w	r6,@-sp
-	st2w	r8,@-sp
-	mv2w	r4,r2			/* divisor (b) */
-	ldi	r2,0			/* high part of dividend (ah) */
-	ldi	r3,0
-	ldi	r12,32			/* number of iterations */
-.Lloop:
-	mv2w	r6,r2			/* tmp1 = (ah << 1) | (al >> 31) */
-	add2w	r6,r6
-	cmpi	r0,0
-	exef0t || addi r7,1
-
-	mv2w	r8,r6			/* tmp2 = tmp1 - b */
-	sub2w	r8,r4
-
-	cmpeq	r6,r4			/* tmpf = (tmp1 >= b), ie f0 = !(tmp1 < b) */
-	cmpu	r6,r4
-	exef1t || cmpu r7,r5
-
-	mv2w	r2,r6			/* ah = (tmpf) ? tmp1 : tmp2 */
-	exef0f || mv2w r2,r8
-
-	add2w	r0,r0			/* al = (al << 1) | tmpf */
-	exef0f || addi r1,1
-
-	subi	r12,1			/* decrement and loop */
-	cmpeqi	r12,0
-	brf0f.s	.Lloop			/* work around simulator bug with .s version of brf0f */
-
-	ld2w	r8,@sp+
-	ld2w	r6,@sp+
-	jmp	r13
-	.size	__udivmodsi4,.-__udivmodsi4
-	.size	__udivsi3,.-__udivsi3
-
-	.globl	__umodsi3
-	.type	__umodsi3,@function
-__umodsi3:
-	st	r13,@-sp
-	bl	__udivmodsi4
-	mv2w	r0,r2
-	ld	r13,@sp+
-	jmp	r13
-	.size	__modvsi3,.-__modvsi3
-#endif
-
-
-#ifdef L_divmodsi4
-/* Signed divide 2 32-bit numbers, leaving the remainder in r0-r1, and quotient
-   in r2-r3.  */
-
-	.file	"_divmodsi4.s"
-	.text
-	.globl	__divmodsi4
-	.type	__divmodsi4,@function
-	.globl	__divsi3
-	.type	__divsi3,@function
-__divmodsi4:
-__divsi3:
-	cmpi	r0,0				/* divisor negative? */
-	brf0t.s	.Lneg1
-
-	cmpi	r2,0				/* dividend negative? */
-	brf0t.s	.Lneg3
-
-	bra	__udivmodsi4			/* both positive, just do division, __udivmodsi4 will return to caller */
-
-.Lneg1:						/* divisor negative, dividend sign not yet checked */
-	st	r13,@-sp
-	not	r0				/* negate divisor */
-	neg	r1
-	cmpeqi	r1,0
-	exef0t || addi r0,1
-
-	cmpi	r2,0				/* dividend negative? */
-	brf0t.s	.Lneg2
-
-	bl	__udivmodsi4			/* do division */
-
-	not	r0				/* negate quotient */
-	neg	r1
-	cmpeqi	r1,0
-	exef0t || addi r0,1
-
-	not	r2				/* negate remainder */
-	neg	r3
-	cmpeqi	r3,0
-	exef0t || addi r2,1
-	ld	r13,@sp+
-	jmp	r13
-
-.Lneg2:						/* divisor & dividend negative */
-	not	r2				/* negate dividend */
-	neg	r3
-	cmpeqi	r3,0
-	exef0t || addi r2,1
-
-	bl	__udivmodsi4			/* do division */
-
-	not	r2				/* negate remainder */
-	neg	r3
-	cmpeqi	r3,0
-	exef0t || addi r2,1
-	ld	r13,@sp+
-	jmp	r13
-
-.Lneg3:						/* divisor positive, dividend negative */
-	st	r13,@-sp
-	not	r2				/* negate dividend */
-	neg	r3
-	cmpeqi	r3,0
-	exef0t || addi r2,1
-
-	bl	__udivmodsi4			/* do division */	
-
-	not	r0				/* negate quotient */
-	neg	r1
-	cmpeqi	r1,0
-	exef0t || addi r0,1
-	ld	r13,@sp+
-	jmp	r13
-	.size	__divmodsi4,.-__divmodsi4
-	.size	__divsi3,.-__divsi3
-
-	.globl	__modsi3
-	.type	__modsi3,@function
-__modsi3:
-	st	r13,@-sp
-	bl	__divmodsi4
-	mv2w	r0,r2
-	ld	r13,@sp+
-	jmp	r13
-	.size	__modsi3,.-__modsi3
-#endif
-
-
-#ifdef L_cmpdi
-/* Signed compare 2 64-bit ints */
-
-	.file	"__cmpdi.s"
-	.text
-	.globl	__cmpdi
-	.type	__cmpdi,@function
-	/* input:	r0-r3 is first value to compare, second value to compare on stack */
-	/* output:	r0 is 0 if op0 < op1, 1 if op0 == op1, 2 if op0 > op1 */
-__cmpdi:
-	ld2w	r4,@sp			/* compare first word */
-	cmp	r0,r4
-	brf0t.s	.Lneg
-	cmp	r4,r0
-	brf0t.s	.Lpos
-
-	cmpu	r1,r5			/* compare second word */
-	brf0t.s	.Lneg
-	cmpu	r5,r1
-	brf0t.s	.Lpos
-	
-	ld2w	r4,@(4,sp)		/* compare third word */
-	cmpu	r2,r4
-	brf0t.s	.Lneg
-	cmpu	r4,r2
-	brf0t.s	.Lpos
-	
-	cmpu	r3,r5			/* compare fourth word */
-	brf0t.s	.Lneg
-	cmpu	r5,r3
-	brf0t.s	.Lpos
-
-	ldi	r0,1			/* op1 == op2 */
-	jmp	r13
-
-.Lneg:
-	ldi	r0,0			/* op1 < op2 */
-	jmp	r13
-
-.Lpos:
-	ldi	r0,2			/* op1 > op2 */
-	jmp	r13
-	.size	__cmpdi,.-__cmpdi
-#endif
-
-
-#ifdef L_cmpdi0
-/* Signed compare 64-bit int against 0 */
-
-	.file	"__cmpdi0.s"
-	.text
-	.globl	__cmpdi0
-	.type	__cmpdi0,@function
-	/* input:	r0-r3 is value to compare */
-	/* output:	r0 is -1 if op0 < 0, 0 if op0 == 0, 1 if op0 > 0 */
-__cmpdi0:
-	cmpi	r0,0			/* compare first word */
-	brf0t.s	.Lneg
-	cmpeqi	r0,0
-	brf0f.s	.Lpos
-
-	cmpeqi	r1,0			/* compare second word */
-	brf0f.s	.Lpos
-
-	cmpeqi	r2,0			/* compare third word */
-	brf0f.s	.Lpos
-
-	cmpeqi	r3,0			/* compare fourth word */
-	brf0f.s	.Lpos
-	
-	ldi	r0,1			/* op1 == 0 */
-	jmp	r13
-
-.Lneg:
-	ldi	r0,0			/* op1 < 0 */
-	jmp	r13
-
-.Lpos:
-	ldi	r0,2			/* op1 > 0 */
-	jmp	r13
-	.size	__cmpdi0,.-__cmpdi0
-#endif
-
-
-#ifdef L_ucmpdi
-/* Unsigned compare 2 64-bit ints */
-
-	.file	"__ucmpdi.s"
-	.text
-	.globl	__ucmpdi
-	.type	__ucmpdi,@function
-	/* input:	r0-r3 is first value to compare, second value to compare on stack */
-	/* output:	r0 is -1 if (unsigned)op0 < (unsigned)op1, 0 if op0 == op1, 1 if (unsigned)op0 > (unsigned)op1 */
-__ucmpdi:
-	ld2w	r4,@sp			/* compare first word */
-	cmpu	r0,r4
-	brf0t.s	.Lneg
-	cmpu	r4,r0
-	brf0t.s	.Lpos
-
-	cmpu	r1,r5			/* compare second word */
-	brf0t.s	.Lneg
-	cmpu	r5,r1
-	brf0t.s	.Lpos
-	
-	ld2w	r4,@(4,sp)		/* compare third word */
-	cmpu	r2,r4
-	brf0t.s	.Lneg
-	cmpu	r4,r2
-	brf0t.s	.Lpos
-	
-	cmpu	r3,r5			/* compare fourth word */
-	brf0t.s	.Lneg
-	cmpu	r5,r3
-	brf0t.s	.Lpos
-
-	ldi	r0,1			/* op1 == op2 */
-	jmp	r13
-
-.Lneg:
-	ldi	r0,0			/* op1 < op2 */
-	jmp	r13
-
-.Lpos:
-	ldi	r0,2			/* op1 > op2 */
-	jmp	r13
-	.size	__ucmpdi,.-__ucmpdi
-#endif
-
-
-#ifdef L_ucmpdi0
-/* Unsigned compare 64-bit int against 0 */
-
-	.file	"__ucmpdi0.s"
-	.text
-	.globl	__ucmpdi0
-	.type	__ucmpdi0,@function
-	/* input:	r0-r3 is value to compare */
-	/* output:	r0 is 0 if op0 == 0, 1 if op0 > 0 */
-__ucmpdi0:
-	cmpeqi	r0,0			/* compare first word */
-	brf0f.s	.Lpos
-
-	cmpeqi	r1,0			/* compare second word */
-	brf0f.s	.Lpos
-
-	cmpeqi	r2,0			/* compare third word */
-	brf0f.s	.Lpos
-
-	cmpeqi	r3,0			/* compare fourth word */
-	brf0f.s	.Lpos
-	
-	ldi	r0,1			/* op1 == 0 */
-	jmp	r13
-
-.Lpos:
-	ldi	r0,2			/* op1 > 0 */
-	jmp	r13
-	.size	__ucmpdi0,.-__ucmpdi0
-#endif
diff --git a/gcc/config/d10v/scrt0.asm b/gcc/config/d10v/scrt0.asm
deleted file mode 100755
index 1aea69a..0000000
--- a/gcc/config/d10v/scrt0.asm
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * special crt0 support for simulator
- *
- *   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
- *   Written By Michael Meissner
- * 
- * This file is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- * 
- * In addition to the permissions in the GNU General Public License, the
- * Free Software Foundation gives you unlimited permission to link the
- * compiled version of this file with other programs, and to distribute
- * those programs without any restriction coming from the use of this
- * file.  (The General Public License restrictions do apply in other
- * respects; for example, they cover modification of the file, and
- * distribution when not linked into another program.)
- * 
- * This file is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, 59 Temple Place - Suite 330,
- * Boston, MA 02111-1307, USA.
- * 
- *    As a special exception, if you link this library with files
- *    compiled with GCC to produce an executable, this does not cause
- *    the resulting executable to be covered by the GNU General Public License.
- *    This exception does not however invalidate any other reasons why
- *    the executable file might be covered by the GNU General Public License.
- */
-
-	.file	"scrt0.s"
-	.text
-	.type	_start,@function
-	.globl	_start
-_start:	ldi	r14,0
-	ldi	sp, _stack
-	bl	main
-	stop
-	.size	_start,.-_start
diff --git a/gcc/config/d10v/sim.asm b/gcc/config/d10v/sim.asm
deleted file mode 100755
index 08393ed..0000000
--- a/gcc/config/d10v/sim.asm
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * special support for simulator
- *
- *   Copyright (C) 1996 Free Software Foundation, Inc.
- *   Written By Michael Meissner
- * 
- * This file is free software * you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation * either version 2, or (at your option) any
- * later version.
- * 
- * In addition to the permissions in the GNU General Public License, the
- * Free Software Foundation gives you unlimited permission to link the
- * compiled version of this file with other programs, and to distribute
- * those programs without any restriction coming from the use of this
- * file.  (The General Public License restrictions do apply in other
- * respects * for example, they cover modification of the file, and
- * distribution when not linked into another program.)
- * 
- * This file is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY * without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program * see the file COPYING.  If not, write to
- * the Free Software Foundation, 59 Temple Place - Suite 330,
- * Boston, MA 02111-1307, USA.
- * 
- *    As a special exception, if you link this library with files
- *    compiled with GCC to produce an executable, this does not cause
- *    the resulting executable to be covered by the GNU General Public License.
- *    This exception does not however invalidate any other reasons why
- *    the executable file might be covered by the GNU General Public License.
- */
-
-	.file	"sim.s"
-	.text
-
-	.globl	printf
-	.type	printf,@function
-printf:
-	trap	2
-	jmp	r13
-	.size	printf,.-printf
-
-	.globl	putchar
-	.type	putchar,@function
-putchar:
-	trap	3
-	jmp	r13
-	.size	putchar,.-putchar
-
-	.globl	putstr
-	.type	putstr,@function
-putstr:
-	trap	1
-	jmp	r13
-	.size	putstr,.-putstr
-
-	.globl	exit
-	.type	exit,@function
-	.globl	_exit
-	.type	_exit,@function
-exit:
-_exit:
-	ldi	r6,1 -> trap 0			/* SYS_exit */
-	stop
-	.size	exit,.-exit
-	.size	_exit,.-_exit
-
-	.globl	abort
-	.type	aobrt,@function
-abort:
-	ldi	r2,amsg
-	trap	1
-	ldi	r6,1 || ldi r2,1		/* SYS_exit & non-zero return code */
-	trap	0 -> stop
-
-	.section .rodata
-amsg:	.ascii	"Abort called\n\0"
diff --git a/gcc/config/d10v/t-d10v b/gcc/config/d10v/t-d10v
deleted file mode 100755
index 8693aaa..0000000
--- a/gcc/config/d10v/t-d10v
+++ /dev/null
@@ -1,30 +0,0 @@
-# Build libgcc1 from assembler sources
-LIBGCC1 = libgcc1-asm.a
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = d10v/libgcc1.asm
-LIB1ASMFUNCS = _ashlsi3 _ashrsi3 _lshrsi3 _mulsi3 _udivmodhi4 _divmodhi4 _udivmodsi4 _divmodsi4 _cmpdi _cmpdi0 _ucmpdi _ucmpdi0
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... 
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define CMPtype HItype' > dp-bit.c
-	echo '#define SMALL_MACHINE' >> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#define CMPtype HItype' >> fp-bit.c
-	echo '#define SMALL_MACHINE' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# Build libgcc.a with different options.
-
-MULTILIB_OPTIONS	= mint16/mint32 mdouble32/mdouble64
-MULTILIB_DIRNAMES	= int16 int32	dbl32 dbl64
-MULTILIB_MATCHES	=
-MULTILIB_EXCEPTIONS	=
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/d10v/xm-d10v.h b/gcc/config/d10v/xm-d10v.h
deleted file mode 100755
index 46c3f97..0000000
--- a/gcc/config/d10v/xm-d10v.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Configuration for Mitsubishi D10V. 
-   Copyright (C) 1996 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#if __INT_MAX__==32767
-#define HOST_BITS_PER_INT 16
-#else
-#define HOST_BITS_PER_INT 32
-#endif
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* Declare all of the functions in string.h and malloc functions when
-   compiling libgcc2 with -mint32 so that we account for size_t being
-   a short.  */
-#ifdef __D10V__
-#include <stddef.h>
-
-void	*memchr(const void *, int, size_t);
-int 	 memcmp(const void *, const void *, size_t);
-void	*memcpy(void *, const void *, size_t);
-void	*memmove(void *, const void *, size_t);
-void	*memset(void *, int, size_t);
-char 	*strcat(char *, const char *);
-char 	*strchr(const char *, int);
-int	 strcmp(const char *, const char *);
-int	 strcoll(const char *, const char *);
-char 	*strcpy(char *, const char *);
-size_t	 strcspn(const char *, const char *);
-char 	*strerror(int);
-size_t	 strlen(const char *);
-char 	*strncat(char *, const char *, size_t);
-int	 strncmp(const char *, const char *, size_t);
-char 	*strncpy(char *, const char *, size_t);
-char 	*strpbrk(const char *, const char *);
-char 	*strrchr(const char *, int);
-size_t	 strspn(const char *, const char *);
-char 	*strstr(const char *, const char *);
-int     ffs(int);
-
-extern void *malloc (size_t);
-extern void *realloc (void *, size_t);
-extern void free (void *);
-#endif
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-
-#include "tm.h"
diff --git a/gcc/config/d30v/abi b/gcc/config/d30v/abi
deleted file mode 100755
index a434483..0000000
--- a/gcc/config/d30v/abi
+++ /dev/null
@@ -1,234 +0,0 @@
-CYGNUS LOCAL -- meissner/d30v
- -*- Text -*-
-
-This document describes the proposed ABI for the D30V processor.  This is
-revision 2 of the document.
-
-Revision history:
-
-Revision 1:
-	Original revision of this document.
-
-Revision 2:
-	Done after consultation with Mitsubshi about the calling sequence.
-	This revision now reduces the number of registers the compiler will not
-	touch from 18 registers down to 8.
-
-	Register 1 is now a normal temporary register, since mvfacc rx,ay,32 is
-	legal.
-
-	Arguments greater than 4 bytes must be passed in an even register or at
-	a double word alignment.
-
-	The va_list type is a structure, not a char *.
-
-	The stack must be aligned to 8 byte boundary.  Doubles and long longs
-	must also be aligned to 8 byte boundaries.
-
-	System calls are specified via trap 31.
-
-Revision 3:
-	I added discussion about compiler switches.
-
-Register usage:
-===============
-
-	Registers	Call Status	Usage
-	---------	-----------	-----
-	R0		hardware	Hardwired to 0
-	R1		volatile	temp
-	R2		volatile	Arg 1 and main return value.
-	R3		volatile	Arg 2 and low bits of 64 bit returns
-	R4 - R17	volatile	Args 3-16
-	R18		volatile	Static chain if used
-	R19 - R25	volatile	temps
-	R26 - R33	saved		Reserved for user use
-	R34 - R60	saved		Registers preserved across calls
-	R61		saved		Frame pointer if needed.
-	R62		saved		Return address pointer (hardware)
-	R63		saved		Stack pointer
-	CR0 - CR3	hardware	{normal,backup} {psw,pc}
-	CR4 - CR6	hardware	Reserved for future use
-	CR7 - CR9	volatile	Repeat count, addresses
-	CR10 - CR11	saved		Modulo start/end
-	CR12 - CR14	hardware	Reserved for future use
-	CR15 - CR17	hardware	Interrupt support
-	F0 - F1		volatile	Execution flags
-	F2 - F3		volatile	General flags
-	F4 - F7		volatile	Special purpose flags
-	A0		volatile	Accumulator
-	A1		saved		Accumulator
-
-Notes on the register usage:
-============================
-
-   1)	R61 will hold the frame pointer if it is needed.  Normally the frame
-	pointer will not be needed, in which case this will become another
-	saved register.
-
-   2)	Repeat instructions and delayed branches cannot cross call boundaries.
-	Similarly, all flags are assumed to not be preserved across calls.
-
-   3)	Since so many registers are available, I reserved 8 registers (r26-r33)
-	for the user to use for any purpose (global variables, interrupt
-	routines, thread pointer, etc.).  These registers will not be used by
-	the compiler for any purpose.
-
-   4)	One of the two accumulators is saved across calls.
-
-   5)	Doubles and long longs will only be allocated to even/odd register
-	pairs to allow use of the ld2w/st2w instructions.
-
-Miscellaneous call information:
-===============================
-
-   1)	Structures are passed in registers, rounding them up to word
-	boundaries.
-
-   2)	Any argument that is greater than word size (4 bytes) must be aligned
-	to a double word boundary and/or start in an even register.  The
-	intention here is to be able to use the ld2w/st2w instructions for
-	moving doubles and long longs.
-
-   3)	Variable argument functions are called with the same calling sequence
-	as non-variable argument functions.  When called, a variable argument
-	function first saves the 16 registers (R2 - R17) used for passing
-	arguments.  The va_list type is a structure.  The first element of the
-	structure is a pointer to the first word saved on the stack, and the
-	second element is a number that gives which argument number is being
-	processed.
-
-   4)	Word and double word sized structures/unions are returned in registers,
-	other functions returning structures expect a temporary area address to
-	be passed as the first argument.
-
-
-The stack frame when a function is called looks like:
-
-high		|  ....				|
-		+-------------------------------+
-		| Argument word #20		|
-		+-------------------------------+
-		| Argument word #19		|
-		+-------------------------------+
-		| Argument word #18		|
-		+-------------------------------+
-		| Argument word #17		|
-low	SP---->	+-------------------------------+
-
-After the prologue is executed, the stack frame will look like:
-
-high		|  ....				|
-		+-------------------------------+
-		| Argument word #20		|
-		+-------------------------------+
-		| Argument word #19		|
-		+-------------------------------+
-		| Argument word #18		|
-		+-------------------------------+
-		| Argument word #17		|
-	Prev sp	+-------------------------------+
-		|				|
-		| Save for arguments 1..16 if	|
-		| the func. uses stdarg/varargs	|
-		|				|
-		+-------------------------------+
-		|				|
-		| Save area for preserved regs	|
-		|				|
-		+-------------------------------+
-		|				|
-		| Local variables		|
-		|				|
-		+-------------------------------+
-		|				|
-		| alloca space if used		|
-		|				|
-		+-------------------------------+
-		|				|
-		| Space for outgoing arguments	|
-		|				|
-low	SP---->	+-------------------------------+
-
-System Calls
-============
-
-System calls will be done using "TRAP 31".  Input arguments will be in R2 - R5,
-and the system call number will be in R6.  Return values from the system call
-will be in R2.  Negative values of the return indicate the system call failed,
-and the value is the negative of the error code.  Here are the assigned system
-call numbers (value in R6):
-
-	exit	1
-	open	2
-	close	3
-	read	4
-	write	5
-	lseek	6
-	unlink	7
-	getpid	8
-	kill	9
-	fstat   10
-			(11 is reserved for sbrk)
-	argvlen	12
-	argv	13
-	chdir	14
-	stat	15
-	chmod 	16
-	utime 	17
-	time 	18
-
-Compiler Switches
-=================
-
-The following d30v specific compiler switches are currently supported:
-
-    -mextmem		Link .text/.data/.bss/etc in external memory.
-
-    -mextmemory		Same as -mextmem.
-
-    -monchip		Link .text/.data/.bss/etc in the onchip data/text
-			memory.
-
-    -mno-asm-optimize	Do not pass -O to the assembler when optimizing (the -O
-			switch will mark two short instructions that don't
-			interfere with each other as being done parallel
-			instead of sequentially).
-
-    -masm-optimize	[default] If optimizing, pass -O to the assembler.
-
-    -mbranch-cost=n	Increase the internal costs of branches to n.  Higher
-			costs means that the compiler will issue more
-			instructions to avoid doing a branch. The default is
-			2.
-
-    -mcond-exec=n	Replace branches around n insns with conditional
-			execution if we can.  Default is 4.
-
-
-Sections
-========
-
-You can override the effect of the -mextmem/-monchip options by putting
-functions into either the ".stext" or ".etext" sections.  If you put them into
-the ".stext" section, the linker will always link the function into the onchip
-memory area.  Similarly, if you put the function in the ".etext" section, the
-linker will always link the function into the external memory area.
-
-Data can be controlled as well.  If you put the data in the ".sdata" section,
-the linker will put the data into the onchip data area.  Similarly, if you put
-the data in the ".edata" section, the linker will put the data into the
-external memory.
-
-
-Stack pointer
-=============
-
-The crt0.o that we ship loads up the stack pointer with the value of the label
-__stack.  If you do not define a value for __stack, the linker will choose the
-top of the onchip data area (0x20008000) for the stack pointer.  You can set a
-new value via the options:
-
-	-Wl,-defsym,__stack=0x20008000
-
-END CYGNUS LOCAL -- meissner/d30v
diff --git a/gcc/config/d30v/d30v.c b/gcc/config/d30v/d30v.c
deleted file mode 100755
index 8e70c4a..0000000
--- a/gcc/config/d30v/d30v.c
+++ /dev/null
@@ -1,3514 +0,0 @@
-/* CYGNUS LOCAL -- meissner/d30v */
-/* Definitions of target machine for use as an example.
-   Hack to fit.
-   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Solutions.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include "system.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#include "expr.h"
-#include "obstack.h"
-#include "tree.h"
-#include "except.h"
-#include "function.h"
-
-static void d30v_print_operand_memory_reference PROTO((FILE *, rtx));
-static void d30v_build_long_insn PROTO((HOST_WIDE_INT, HOST_WIDE_INT, rtx, rtx));
-
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  */
-
-struct rtx_def *d30v_compare_op0;
-struct rtx_def *d30v_compare_op1;
-
-/* Define the information needed to modify the epilogue for EH.  */
-
-rtx d30v_eh_epilogue_sp_ofs;
-
-/* Cached value of d30v_stack_info */
-static d30v_stack_t *d30v_stack_cache = (d30v_stack_t *)0;
-
-/* Cache for __builtin_return_addr */
-static rtx d30v_return_addr_rtx;
-
-/* Values of the -mbranch-cost=n string.  */
-int d30v_branch_cost = D30V_DEFAULT_BRANCH_COST;
-char *d30v_branch_cost_string = (char *)0;
-
-/* Values of the -mcond-exec=n string.  */
-int d30v_cond_exec = D30V_DEFAULT_MAX_CONDITIONAL_EXECUTE;
-char *d30v_cond_exec_string = (char *)0;
-
-/* Whether or not a hard register can accept a register */
-unsigned char hard_regno_mode_ok[ (int)MAX_MACHINE_MODE ][FIRST_PSEUDO_REGISTER];
-
-/* Whether to try and avoid moves between two different modes */
-unsigned char modes_tieable_p[ (NUM_MACHINE_MODES) * (NUM_MACHINE_MODES) ];
-
-/* Map register number to smallest register class.  */
-enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
-
-/* Map class letter into register class */
-enum reg_class reg_class_from_letter[256];
-
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-
-void
-override_options ()
-{
-  int regno, i, ok_p;
-  enum machine_mode mode1, mode2;
-
-  /* Set up the branch cost information */
-  if (d30v_branch_cost_string)
-    d30v_branch_cost = atoi (d30v_branch_cost_string);
-
-  /* Set up max # instructions to use with conditional execution */
-  if (d30v_cond_exec_string)
-    d30v_cond_exec = atoi (d30v_cond_exec_string);
-
-  /* Setup hard_regno_mode_ok/modes_tieable_p */
-  for (mode1 = VOIDmode;
-       (int)mode1 < NUM_MACHINE_MODES;
-       mode1 = (enum machine_mode)((int)mode1 + 1))
-    {
-      int size = GET_MODE_SIZE (mode1);
-      int large_p = size > UNITS_PER_WORD;
-      int int_p = GET_MODE_CLASS (mode1) == MODE_INT;
-
-      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-	{
-	  if (mode1 == VOIDmode)
-	    ok_p = FALSE;
-
-	  else if (GPR_P (regno))
-	    {
-	      if (!large_p)
-		ok_p = TRUE;
-	      else
-		ok_p = (((regno - GPR_FIRST) & 1) == 0);
-	    }
-
-	  else if (FLAG_P (regno))
-	    ok_p = (mode1 == CCmode);
-
-	  else if (CR_P (regno))
-	    ok_p = int_p && !large_p;
-
-	  else if (ACCUM_P (regno))
-	    ok_p = (mode1 == DImode);
-
-	  else if (SPECIAL_REG_P (regno))
-	    ok_p = (mode1 == SImode);
-
-	  else
-	    ok_p = FALSE;
-
-	  hard_regno_mode_ok[ (int)mode1 ][ regno ] = ok_p;
-	}
-
-      /* A C expression that is nonzero if it is desirable to choose
-	 register allocation so as to avoid move instructions between a
-	 value of mode MODE1 and a value of mode MODE2.
-
-	 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
-	 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
-	 MODE2)' must be zero. */
-      for (mode2 = VOIDmode;
-	   (int)mode2 <= NUM_MACHINE_MODES;
-	   mode2 = (enum machine_mode)((int)mode2 + 1))
-	{
-	  if (mode1 == mode2)
-	    ok_p = TRUE;
-
-#if 0
-	  else if (GET_MODE_CLASS (mode1) == MODE_INT
-		   && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD
-		   && GET_MODE_CLASS (mode2) == MODE_INT
-		   && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
-	    ok_p = TRUE;
-#endif
-
-	  else
-	    ok_p = FALSE;
-
-	  modes_tieable_p[ ((int)mode1 * (NUM_MACHINE_MODES)) + (int)mode2 ] = ok_p;
-	}
-    }
-
-#if 0
-  for (mode1 = VOIDmode;
-       (int)mode1 < NUM_MACHINE_MODES;
-       mode1 = (enum machine_mode)((int)mode1 + 1))
-    {
-      for (mode2 = VOIDmode;
-	   (int)mode2 <= NUM_MACHINE_MODES;
-	   mode2 = (enum machine_mode)((int)mode2 + 1))
-	{
-	  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-	    if (ok_p
-		&& (hard_regno_mode_ok[(int)mode1][regno]
-		    != hard_regno_mode_ok[(int)mode2][regno]))
-	      error ("Bad modes_tieable_p for register %s, mode1 %s, mode2 %s",
-		     reg_names[regno], GET_MODE_NAME (mode1),
-		     GET_MODE_NAME (mode2));
-	}
-    }
-#endif
-
-  /* A C expression whose value is a register class containing hard
-     register REGNO.  In general there is more than one such class;
-     choose a class which is "minimal", meaning that no smaller class
-     also contains the register. */
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-    {
-      enum reg_class class;
-
-      if (GPR_P (regno))
-	class = (IN_RANGE_P (regno, GPR_FIRST+2, GPR_FIRST+62)
-		 && ((regno - GPR_FIRST) & 1) == 0) ? EVEN_REGS : GPR_REGS;
-
-      else if (regno == FLAG_F0)
-	class = F0_REGS;
-
-      else if (regno == FLAG_F1)
-	class = F1_REGS;
-
-      else if (FLAG_P (regno))
-	class = OTHER_FLAG_REGS;
-
-      else if (ACCUM_P (regno))
-	class = ACCUM_REGS;
-
-      else if (regno == CR_RPT_C)
-	class = REPEAT_REGS;
-
-      else if (CR_P (regno))
-	class = CR_REGS;
-
-      else if (SPECIAL_REG_P (regno))
-	class = GPR_REGS;
-
-      else
-	class = NO_REGS;
-
-      regno_reg_class[regno] = class;
-
-#if 0
-      {
-	static char *names[] = REG_CLASS_NAMES;
-	fprintf (stderr, "Register %s class is %s, can hold modes", reg_names[regno], names[class]);
-	for (mode1 = VOIDmode;
-	     (int)mode1 < NUM_MACHINE_MODES;
-	     mode1 = (enum machine_mode)((int)mode1 + 1))
-	  {
-	    if (hard_regno_mode_ok[ (int)mode1 ][ regno ])
-	      fprintf (stderr, " %s", GET_MODE_NAME (mode1));
-	  }
-	fprintf (stderr, "\n");
-      }
-#endif
-    }
-
-  /* A C expression which defines the machine-dependent operand
-     constraint letters for register classes.  If CHAR is such a
-     letter, the value should be the register class corresponding to
-     it.  Otherwise, the value should be `NO_REGS'.  The register
-     letter `r', corresponding to class `GENERAL_REGS', will not be
-     passed to this macro; you do not need to handle it.
-
-     The following letters are unavailable, due to being used as
-     constraints:
-	'0'..'9'
-	'<', '>'
-	'E', 'F', 'G', 'H'
-	'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
-	'Q', 'R', 'S', 'T', 'U'
-	'V', 'X'
-	'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
-
-  for (i = 0; i < 256; i++)
-    reg_class_from_letter[i] = NO_REGS;
-
-  reg_class_from_letter['a'] = ACCUM_REGS;
-  reg_class_from_letter['b'] = BR_FLAG_REGS;
-  reg_class_from_letter['c'] = CR_REGS;
-  reg_class_from_letter['d'] = GPR_REGS;
-  reg_class_from_letter['e'] = EVEN_REGS;
-  reg_class_from_letter['f'] = FLAG_REGS;
-  reg_class_from_letter['l'] = REPEAT_REGS;
-  reg_class_from_letter['x'] = F0_REGS;
-  reg_class_from_letter['y'] = F1_REGS;
-  reg_class_from_letter['z'] = OTHER_FLAG_REGS;
-}
-
-
-/* Return true if a memory operand is a short memory operand.  */
-
-int
-short_memory_operand (op, mode_int)
-     register rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_CODE (op) != MEM)
-    return FALSE;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  return (d30v_legitimate_address_p (mode_int, XEXP (op, 0), reload_completed)
-	  == 1);
-}
-
-/* Return true if a memory operand is a long operand.  */
-
-int
-long_memory_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_CODE (op) != MEM)
-    return FALSE;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  return (d30v_legitimate_address_p (mode_int, XEXP (op, 0), reload_completed)
-	  == 2);
-}
-
-/* Return true if a memory operand is valid for the D30V.  */
-
-int
-d30v_memory_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_CODE (op) != MEM)
-    return FALSE;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  return (d30v_legitimate_address_p (mode_int, XEXP (op, 0), reload_completed)
-	  != 0);
-}
-
-/* Return true if a memory operand uses a single register for the
-   address.  */
-
-int
-single_reg_memory_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx addr;
-  int regno;
-
-  if (GET_CODE (op) != MEM)
-    return FALSE;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  addr = XEXP (op, 0);
-  if (! d30v_legitimate_address_p (mode_int, addr, reload_completed))
-    return FALSE;
-
-  if (GET_CODE (addr) == SUBREG)
-    addr = SUBREG_REG (addr);
-
-  return (GET_CODE (addr) == REG);
-}
-
-/* Return true if a memory operand uses a constant address.  */
-
-int
-const_addr_memory_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_CODE (op) != MEM)
-    return FALSE;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (! d30v_legitimate_address_p (mode_int, XEXP (op, 0), reload_completed))
-    return FALSE;
-
-  switch (GET_CODE (XEXP (op, 0)))
-    {
-    default:
-      break;
-
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case CONST_INT:
-    case CONST:
-      return TRUE;
-    }
-
-  return FALSE;
-}
-
-/* Return true if operand is a memory reference suitable for a call.  */
-
-int
-call_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_CODE (op) != MEM)
-    return FALSE;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (! d30v_legitimate_address_p (mode_int, XEXP (op, 0), reload_completed))
-    return FALSE;
-
-  switch (GET_CODE (XEXP (op, 0)))
-    {
-    default:
-      break;
-
-    case SUBREG:
-      op = SUBREG_REG (op);
-      if (GET_CODE (op) != REG)
-	return FALSE;
-
-      /* fall through */
-
-    case REG:
-      return (GPR_OR_PSEUDO_P (REGNO (XEXP (op, 0))));
-
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case CONST_INT:
-    case CONST:
-      return TRUE;
-    }
-
-  return FALSE;
-}
-
-/* Return true if operand is a GPR register.  */
-
-int
-gpr_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  return GPR_OR_PSEUDO_P (REGNO (op));
-}
-
-/* Return true if operand is an accumulator register.  */
-
-int
-accum_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  return ACCUM_OR_PSEUDO_P (REGNO (op));
-}
-
-/* Return true if operand is a GPR or an accumulator register.  */
-
-int
-gpr_or_accum_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  if (ACCUM_P (REGNO (op)))
-    return TRUE;
-
-  return GPR_OR_PSEUDO_P (REGNO (op));
-}
-
-/* Return true if operand is a CR register.  */
-
-int
-cr_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  return CR_OR_PSEUDO_P (REGNO (op));
-}
-
-/* Return true if operand is the repeat count register.  */
-
-int
-repeat_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  return (REGNO (op) == CR_RPT_C || REGNO (op) >= FIRST_PSEUDO_REGISTER);
-}
-
-/* Return true if operand is a FLAG register.  */
-
-int
-flag_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  return FLAG_OR_PSEUDO_P (REGNO (op));
-}
-
-/* Return true if operand is either F0 or F1.  */
-
-int
-br_flag_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  return BR_FLAG_OR_PSEUDO_P (REGNO (op));
-}
-
-/* Return true if operand is either F0/F1 or the constants 0/1.  */
-
-int
-br_flag_or_constant_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) == CONST_INT)
-    return (INTVAL (op) == 0 || INTVAL (op) == 1);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  return BR_FLAG_OR_PSEUDO_P (REGNO (op));
-}
-
-/* Return true if operand is either F0 or F1, or a GPR register.  */
-
-int
-gpr_or_br_flag_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  return GPR_OR_PSEUDO_P (REGNO (op)) || BR_FLAG_P (REGNO (op));
-}
-
-/* Return true if operand is the F0 register.  */
-
-int
-f0_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  return (REGNO (op) == FLAG_F0 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
-}
-
-/* Return true if operand is the F1 register.  */
-
-int
-f1_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  return (REGNO (op) == FLAG_F1 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
-}
-
-/* Return true if operand is the F1 register.  */
-
-int
-carry_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  return (REGNO (op) == FLAG_CARRY || REGNO (op) >= FIRST_PSEUDO_REGISTER);
-}
-
-/* Return true if operand is a register of any flavor or a 0 of the
-   appropriate type.  */
-
-int
-reg_or_0_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  switch (GET_CODE (op))
-    {
-    case REG:
-    case SUBREG:
-      if (GET_MODE (op) != mode && mode != VOIDmode)
-	return FALSE;
-
-      return register_operand (op, mode);
-
-    case CONST_INT:
-      return INTVAL (op) == 0;
-
-    case CONST_DOUBLE:
-      return CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == 0;
-    }
-
-  return FALSE;
-}
-
-/* Return true if operand is a GPR register or a signed 6 bit immediate.  */
-
-int
-gpr_or_signed6_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) == CONST_INT)
-    return IN_RANGE_P (INTVAL (op), -32, 31);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  return GPR_OR_PSEUDO_P (REGNO (op));
-}
-
-/* Return true if operand is a GPR register or an unsigned 5 bit immediate.  */
-
-int
-gpr_or_unsigned5_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) == CONST_INT)
-    return IN_RANGE_P (INTVAL (op), 0, 31);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  return GPR_OR_PSEUDO_P (REGNO (op));
-}
-
-/* Return true if operand is a GPR register or an unsigned 6 bit immediate.  */
-
-int
-gpr_or_unsigned6_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) == CONST_INT)
-    return IN_RANGE_P (INTVAL (op), 0, 63);
-
-  if (GET_CODE (op) != REG)
-    return FALSE;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  return GPR_OR_PSEUDO_P (REGNO (op));
-}
-
-/* Return true if operand is a GPR register or a constant of some form.  */
-
-int
-gpr_or_constant_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  switch (GET_CODE (op))
-    {
-    default:
-      break;
-
-    case CONST_INT:
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case CONST:
-      return TRUE;
-
-    case SUBREG:
-      op = SUBREG_REG (op);
-      if (GET_CODE (op) != REG)
-	break;
-
-      /* fall through */
-
-    case REG:
-      if (GET_MODE (op) != mode && mode != VOIDmode)
-	return FALSE;
-
-      return GPR_OR_PSEUDO_P (REGNO (op));
-    }
-
-  return FALSE;
-}
-
-/* Return true if operand is a GPR register or a constant of some form,
-   including a CONST_DOUBLE, which gpr_or_constant_operand doesn't recognize.  */
-
-int
-gpr_or_dbl_const_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  switch (GET_CODE (op))
-    {
-    default:
-      break;
-
-    case CONST_INT:
-    case CONST_DOUBLE:
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case CONST:
-      return TRUE;
-
-    case SUBREG:
-      op = SUBREG_REG (op);
-      if (GET_CODE (op) != REG)
-	break;
-
-      /* fall through */
-
-    case REG:
-      if (GET_MODE (op) != mode && mode != VOIDmode)
-	return FALSE;
-
-      return GPR_OR_PSEUDO_P (REGNO (op));
-    }
-
-  return FALSE;
-}
-
-/* Return true if operand is a gpr register or a valid memory operation.  */
-
-int
-gpr_or_memory_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  switch (GET_CODE (op))
-    {
-    default:
-      break;
-
-    case SUBREG:
-      op = SUBREG_REG (op);
-      if (GET_CODE (op) != REG)
-	break;
-
-      /* fall through */
-
-    case REG:
-      if (GET_MODE (op) != mode && mode != VOIDmode)
-	return FALSE;
-
-      return GPR_OR_PSEUDO_P (REGNO (op));
-
-    case MEM:
-      return d30v_legitimate_address_p (mode_int, XEXP (op, 0), reload_completed);
-    }
-
-  return FALSE;
-}
-
-/* Return true if operand is something that can be an input for a move
-   operation.  */
-
-int
-move_input_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  switch (GET_CODE (op))
-    {
-    default:
-      break;
-
-    case CONST_INT:
-    case CONST_DOUBLE:
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case CONST:
-      return TRUE;
-
-    case SUBREG:
-      if (GET_MODE (op) != mode && mode != VOIDmode)
-	return FALSE;
-
-      op = SUBREG_REG (op);
-      if (GET_CODE (op) != REG)
-	break;
-
-      return TRUE;
-
-    case REG:
-      if (GET_MODE (op) != mode && mode != VOIDmode)
-	return FALSE;
-
-      return TRUE;
-
-    case MEM:
-      if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
-	return TRUE;
-      return d30v_legitimate_address_p (mode_int, XEXP (op, 0),
-					reload_completed);
-    }
-
-  return FALSE;
-}
-
-/* Return true if operand is something that can be an output for a move
-   operation.  */
-
-int
-move_output_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  switch (GET_CODE (op))
-    {
-    default:
-      break;
-
-    case SUBREG:
-      if (GET_MODE (op) != mode && mode != VOIDmode)
-	return FALSE;
-
-      op = SUBREG_REG (op);
-      if (GET_CODE (op) != REG)
-	break;
-
-      return TRUE;
-
-    case REG:
-      if (GET_MODE (op) != mode && mode != VOIDmode)
-	return FALSE;
-
-      return TRUE;
-
-    case MEM:
-      if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
-	return TRUE;
-      return d30v_legitimate_address_p (mode_int, XEXP (op, 0),
-					reload_completed);
-    }
-
-  return FALSE;
-}
-
-/* Return true if operand is a signed 6 bit immediate.  */
-
-int
-signed6_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return IN_RANGE_P (INTVAL (op), -32, 31);
-
-  return FALSE;
-}
-
-/* Return true if operand is an unsigned 5 bit immediate.  */
-
-int
-unsigned5_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return IN_RANGE_P (INTVAL (op), 0, 31);
-
-  return FALSE;
-}
-
-/* Return true if operand is an unsigned 6 bit immediate.  */
-
-int
-unsigned6_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return IN_RANGE_P (INTVAL (op), 0, 63);
-
-  return FALSE;
-}
-
-/* Return true if operand is a constant with a single bit set.  */
-
-int
-bitset_operand (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return IN_RANGE_P (exact_log2 (INTVAL (op)), 0, 31);
-
-  return FALSE;
-}
-
-/* Return true if the operator is a ==/!= test against f0 or f1 that can be
-   used in conditional execution.  */
-
-int
-condexec_test_operator (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx x0, x1;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
-    return FALSE;
-
-  x0 = XEXP (op, 0);
-  if (GET_CODE (x0) != REG || !BR_FLAG_OR_PSEUDO_P (REGNO (x0)))
-    return FALSE;
-
-  x1 = XEXP (op, 1);
-  if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
-    return FALSE;
-
-  return TRUE;
-}
-
-/* Return true if the operator is a ==/!= test against f0, f1, or a general
-   register that can be used in a branch instruction.  */
-
-int
-condexec_branch_operator (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx x0, x1;
-  int regno;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
-    return FALSE;
-
-  x0 = XEXP (op, 0);
-  if (GET_CODE (x0) != REG)
-    return FALSE;
-
-  regno = REGNO (x0);
-  if (!GPR_OR_PSEUDO_P (regno) && !BR_FLAG_P (regno))
-    return FALSE;
-
-  x1 = XEXP (op, 1);
-  if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
-    return FALSE;
-
-  return TRUE;
-}
-
-/* Return true if the unary operator can be executed with conditional
-   execution.  */
-
-int
-condexec_unary_operator (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx op0;
-
-  /* Only do this after register allocation, so that we can look at the register # */
-  if (!reload_completed)
-    return FALSE;
-
-  if (GET_RTX_CLASS (GET_CODE (op)) != '1')
-    return FALSE;
-
-  op0 = XEXP (op, 0);
-  if (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-
-  switch (GET_CODE (op))
-    {
-    default:
-      break;
-
-    case ABS:
-    case NEG:
-    case NOT:
-      if (GET_MODE (op) == SImode && GET_CODE (op0) == REG && GPR_P (REGNO (op0)))
-	return TRUE;
-
-      break;
-    }
-
-  return FALSE;
-}
-
-/* Return true if the add or subtraction can be executed with conditional
-   execution.  */
-
-int
-condexec_addsub_operator (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx op0, op1;
-
-  /* Only do this after register allocation, so that we can look at the register # */
-  if (!reload_completed)
-    return FALSE;
-
-  if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
-    return FALSE;
-
-  op0 = XEXP (op, 0);
-  op1 = XEXP (op, 1);
-
-  if (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-
-  if (GET_CODE (op1) == SUBREG)
-    op1 = SUBREG_REG (op1);
-
-  if (GET_CODE (op0) != REG)
-    return FALSE;
-
-  switch (GET_CODE (op))
-    {
-    default:
-      break;
-
-    case PLUS:
-    case MINUS:
-      return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
-	      && gpr_or_constant_operand (op1, SImode));
-    }
-
-  return FALSE;
-}
-
-/* Return true if the binary operator can be executed with conditional
-   execution.  We don't include add/sub here, since they have extra
-   clobbers for the flags registers.  */
-
-int
-condexec_binary_operator (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx op0, op1;
-
-  /* Only do this after register allocation, so that we can look at the register # */
-  if (!reload_completed)
-    return FALSE;
-
-  if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
-    return FALSE;
-
-  op0 = XEXP (op, 0);
-  op1 = XEXP (op, 1);
-
-  if (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-
-  if (GET_CODE (op1) == SUBREG)
-    op1 = SUBREG_REG (op1);
-
-  if (GET_CODE (op0) != REG)
-    return FALSE;
-
-  /* MULT is not included here, because it is an IU only instruction.  */
-  switch (GET_CODE (op))
-    {
-    case AND:
-    case IOR:
-    case XOR:
-    case ASHIFTRT:
-    case LSHIFTRT:
-    case ROTATERT:
-      return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
-	      && gpr_or_constant_operand (op1, SImode));
-
-    case ASHIFT:
-    case ROTATE:
-      return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
-	      && GET_CODE (op1) == CONST_INT);
-    }
-
-  return FALSE;
-}
-
-/* Return true if the shift/rotate left operator can be executed with
-   conditional execution.  */
-
-int
-condexec_shiftl_operator (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx op0, op1;
-
-  /* Only do this after register allocation, so that we can look at the register # */
-  if (!reload_completed)
-    return FALSE;
-
-  if (GET_RTX_CLASS (GET_CODE (op)) != '2' && GET_RTX_CLASS (GET_CODE (op)) != 'c')
-    return FALSE;
-
-  op0 = XEXP (op, 0);
-  op1 = XEXP (op, 1);
-
-  if (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-
-  if (GET_CODE (op1) == SUBREG)
-    op1 = SUBREG_REG (op1);
-
-  if (GET_CODE (op0) != REG)
-    return FALSE;
-
-  switch (GET_CODE (op))
-    {
-    case ASHIFT:
-    case ROTATE:
-      return (GET_MODE (op) == SImode && GPR_P (REGNO (op0))
-	      && GET_CODE (op1) == NEG
-	      && GET_CODE (XEXP (op1, 0)) == REG
-	      && GPR_P (REGNO (XEXP (op1, 0))));
-    }
-
-  return FALSE;
-}
-
-/* Return true if the {sign,zero} extend operator from memory can be
-   conditionally executed.  */
-
-int
-condexec_extend_operator (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-
-  /* Only do this after register allocation, so that we can look at the register # */
-  if (!reload_completed)
-    return FALSE;
-
-  if (GET_RTX_CLASS (GET_CODE (op)) != '1')
-    return FALSE;
-
-  switch (GET_CODE (op))
-    {
-    default:
-      break;
-
-    case SIGN_EXTEND:
-    case ZERO_EXTEND:
-      if ((GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == QImode)
-	  || (GET_MODE (op) == SImode && GET_MODE (XEXP (op, 0)) == HImode)
-	  || (GET_MODE (op) == HImode && GET_MODE (XEXP (op, 0)) == QImode))
-	return TRUE;
-
-      break;
-    }
-
-  return FALSE;
-}
-
-/* Return true for comparisons against 0 that can be turned into a
-   bratnz/bratzr instruction.  */
-
-int
-branch_zero_operator (op, mode_int)
-     rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx x0, x1;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) != EQ && GET_CODE (op) != NE)
-    return FALSE;
-
-  x0 = XEXP (op, 0);
-  if (GET_CODE (x0) != REG || !GPR_OR_PSEUDO_P (REGNO (x0)))
-    return FALSE;
-
-  x1 = XEXP (op, 1);
-  if (GET_CODE (x1) != CONST_INT || INTVAL (x1) != 0)
-    return FALSE;
-
-  return TRUE;
-}
-
-/* Return true if an operand is simple, suitable for use in a conditional move */
-
-int
-cond_move_operand (op, mode_int)
-     register rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx addr;
-
-  if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
-    return FALSE;
-
-  switch (GET_CODE (op))
-    {
-    case REG:
-    case SUBREG:
-      return gpr_operand (op, mode);
-
-    case CONST_DOUBLE:
-      return GET_MODE (op) == SFmode;
-
-    case CONST_INT:
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case CONST:
-      return TRUE;
-
-    /* Don't allow post dec/inc, since we might not get the side effects correct. */
-    case MEM:
-      addr = XEXP (op, 0);
-      return GET_CODE (addr) != POST_DEC && GET_CODE (addr) != POST_INC;
-    }
-
-  return FALSE;
-}
-
-/* Return true if an operand is simple, suitable for use in conditional execution.
-   Unlike cond_move, we can allow auto inc/dec.  */
-
-int
-cond_exec_operand (op, mode_int)
-     register rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx addr;
-
-  if (mode != QImode && mode != HImode && mode != SImode && mode != SFmode)
-    return FALSE;
-
-  switch (GET_CODE (op))
-    {
-    case REG:
-    case SUBREG:
-      return gpr_operand (op, mode);
-
-    case CONST_DOUBLE:
-      return GET_MODE (op) == SFmode;
-
-    case CONST_INT:
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case CONST:
-      return TRUE;
-
-    case MEM:
-      return memory_operand (op, mode);
-    }
-
-  return FALSE;
-}
-
-/* Return true if operand is a SI mode signed relational test.  */
-
-int
-srelational_si_operator (op, mode_int)
-     register rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx x0, x1;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  switch (GET_CODE (op))
-    {
-    default:
-      return FALSE;
-
-    case EQ:
-    case NE:
-    case LT:
-    case LE:
-    case GT:
-    case GE:
-      break;
-    }
-
-  x0 = XEXP (op, 0);
-  if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
-    return FALSE;
-
-  if (GET_MODE (x0) != SImode)
-    return FALSE;
-
-  x1 = XEXP (op, 1);
-  switch (GET_CODE (x1))
-    {
-    default:
-      return FALSE;
-
-    case REG:
-    case SUBREG:
-    case CONST_INT:
-    case LABEL_REF:
-    case SYMBOL_REF:
-    case CONST:
-      break;
-    }
-
-  return TRUE;
-}
-
-/* Return true if operand is a SI mode unsigned relational test.  */
-
-int
-urelational_si_operator (op, mode_int)
-     register rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx x0, x1;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  switch (GET_CODE (op))
-    {
-    default:
-      return FALSE;
-
-    case LTU:
-    case LEU:
-    case GTU:
-    case GEU:
-      break;
-    }
-
-  x0 = XEXP (op, 0);
-  if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
-    return FALSE;
-
-  if (GET_MODE (x0) != SImode)
-    return FALSE;
-
-  x1 = XEXP (op, 1);
-  switch (GET_CODE (x1))
-    {
-    default:
-      return FALSE;
-
-    case REG:
-    case SUBREG:
-    case CONST_INT:
-    case LABEL_REF:
-    case SYMBOL_REF:
-    case CONST:
-      break;
-    }
-
-  return TRUE;
-}
-
-/* Return true if operand is a DI mode relational test.  */
-
-int
-relational_di_operator (op, mode_int)
-     register rtx op;
-     int mode_int;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx x0, x1;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return FALSE;
-
-  if (GET_RTX_CLASS (GET_CODE (op)) != '<')
-    return FALSE;
-
-  x0 = XEXP (op, 0);
-  if (GET_CODE (x0) != REG && GET_CODE (x0) != SUBREG)
-    return FALSE;
-
-  if (GET_MODE (x0) != DImode)
-    return FALSE;
-
-  x1 = XEXP (op, 1);
-  if (GET_CODE (x1) != REG && GET_CODE (x1) != SUBREG
-      && GET_CODE (x1) != CONST_INT && GET_CODE (x1) != CONST_DOUBLE)
-    return FALSE;
-
-  return TRUE;
-}
-
-
-/* Calculate the stack information for the current function.
-
-   D30V stack frames look like:
-
-	high		|  ....				|
-			+-------------------------------+
-			| Argument word #19		|
-			+-------------------------------+
-			| Argument word #18		|
-			+-------------------------------+
-			| Argument word #17		|
-			+-------------------------------+
-			| Argument word #16		|
-		Prev sp	+-------------------------------+
-			|				|
-			| Save for arguments 1..16 if	|
-			| the func. uses stdarg/varargs	|
-			|				|
-			+-------------------------------+
-			|				|
-			| Save area for GPR registers	|
-			|				|
-			+-------------------------------+
-			|				|
-			| Save area for accumulators	|
-			|				|
-			+-------------------------------+
-			|				|
-			| Local variables		|
-			|				|
-			+-------------------------------+
-			|				|
-			| alloca space if used		|
-			|				|
-			+-------------------------------+
-			|				|
-			| Space for outgoing arguments	|
-			|				|
-	low	SP---->	+-------------------------------+
-*/
-
-d30v_stack_t *
-d30v_stack_info ()
-{
-  static d30v_stack_t info, zero_info;
-  d30v_stack_t *info_ptr = &info;
-  tree fndecl		 = current_function_decl;
-  tree fntype		 = TREE_TYPE (fndecl);
-  int varargs_p		 = 0;
-  tree cur_arg;
-  tree next_arg;
-  int saved_gprs;
-  int saved_accs;
-  int memrefs_2words;
-  int memrefs_1word;
-  unsigned char save_gpr_p[GPR_LAST];
-  int i;
-
-  /* If we've already calculated the values and reload is complete, just return now */
-  if (d30v_stack_cache)
-    return d30v_stack_cache;
-
-  /* Zero all fields */
-  info = zero_info;
-
-  if (profile_flag)
-    regs_ever_live[GPR_LINK] = 1;
-
-  /* Determine if this is a stdarg function */
-  if (TYPE_ARG_TYPES (fntype) != 0
-      && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
-    varargs_p = 1;
-  else
-    {
-      /* Find the last argument, and see if it is __builtin_va_alist.  */
-      for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
-	{
-	  next_arg = TREE_CHAIN (cur_arg);
-	  if (next_arg == (tree)0)
-	    {
-	      if (DECL_NAME (cur_arg)
-		  && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
-		varargs_p = 1;
-
-	      break;
-	    }
-	}
-    }
-
-  /* Calculate which registers need to be saved & save area size */
-  saved_accs = 0;
-  memrefs_2words = 0;
-  memrefs_1word = 0;
-  for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
-    {
-      if (regs_ever_live[i] && !call_used_regs[i])
-	{
-	  info_ptr->save_p[i] = 2;
-	  saved_accs++;
-	  memrefs_2words++;
-	}
-    }
-
-  saved_gprs = 0;
-  for (i = GPR_FIRST; i <= GPR_LAST; i++)
-    {
-      if (regs_ever_live[i] && (!call_used_regs[i] || i == GPR_LINK))
-	{
-	  save_gpr_p[i] = 1;
-	  saved_gprs++;
-	}
-      else
-	save_gpr_p[i] = 0;
-    }
-
-  /* Determine which register pairs can be saved together with ld2w/st2w  */
-  for (i = GPR_FIRST; i <= GPR_LAST; i++)
-    {
-      if (((i - GPR_FIRST) & 1) == 0 && save_gpr_p[i] && save_gpr_p[i+1])
-	{
-	  memrefs_2words++;
-	  info_ptr->save_p[i++] = 2;
-	}
-      else if (save_gpr_p[i])
-	{
-	  memrefs_1word++;
-	  info_ptr->save_p[i] = 1;
-	}
-    }
-
-  /* Determine various sizes */
-  info_ptr->varargs_p	 = varargs_p;
-  info_ptr->varargs_size = ((varargs_p)
-			    ? (GPR_ARG_LAST + 1 - GPR_ARG_FIRST) * UNITS_PER_WORD
-			    : 0);
-
-  info_ptr->accum_size	 = 2 * UNITS_PER_WORD * saved_accs;
-  info_ptr->gpr_size	 = D30V_ALIGN (UNITS_PER_WORD * saved_gprs,
-				       2 * UNITS_PER_WORD);
-  info_ptr->vars_size    = D30V_ALIGN (get_frame_size (), 2 * UNITS_PER_WORD);
-  info_ptr->parm_size    = D30V_ALIGN (current_function_outgoing_args_size,
-				       2 * UNITS_PER_WORD);
-
-  info_ptr->total_size	 = D30V_ALIGN ((info_ptr->gpr_size
-					+ info_ptr->accum_size
-					+ info_ptr->vars_size
-					+ info_ptr->parm_size
-					+ info_ptr->varargs_size),
-				       (STACK_BOUNDARY / BITS_PER_UNIT));
-
-  info_ptr->save_offset  = (info_ptr->total_size
-			    - (info_ptr->varargs_size
-			       + info_ptr->gpr_size
-			       + info_ptr->accum_size));
-
-  /* The link register is the last GPR saved, but there might be some padding
-     bytes after it, so account for that.  */
-  info_ptr->link_offset  = (info_ptr->total_size
-			    - (info_ptr->varargs_size
-			       + (info_ptr->gpr_size
-				  - UNITS_PER_WORD * saved_gprs)
-			       + UNITS_PER_WORD));
-
-  info_ptr->memrefs_varargs = info_ptr->varargs_size / (2 * UNITS_PER_WORD);
-  info_ptr->memrefs_2words  = memrefs_2words;
-  info_ptr->memrefs_1word   = memrefs_1word;
-
-  if (reload_completed)
-    d30v_stack_cache = info_ptr;
-
-  return info_ptr;
-}
-
-
-/* Internal function to print all of the information about the stack */
-
-void
-debug_stack_info (info)
-     d30v_stack_t *info;
-{
-  int i;
-
-  if (!info)
-    info = d30v_stack_info ();
-
-  fprintf (stderr, "\nStack information for function %s:\n",
-	   ((current_function_decl && DECL_NAME (current_function_decl))
-	    ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
-	    : "<unknown>"));
-
-  fprintf (stderr, "\tsave_offset     = %d\n", info->save_offset);
-  fprintf (stderr, "\tmemrefs_varargs = %d\n", info->memrefs_varargs);
-  fprintf (stderr, "\tmemrefs_2words  = %d\n", info->memrefs_2words);
-  fprintf (stderr, "\tmemrefs_1word   = %d\n", info->memrefs_1word);
-  fprintf (stderr, "\tvarargs_p       = %d\n", info->varargs_p);
-  fprintf (stderr, "\tvarargs_size    = %d\n", info->varargs_size);
-  fprintf (stderr, "\tvars_size       = %d\n", info->vars_size);
-  fprintf (stderr, "\tparm_size       = %d\n", info->parm_size);
-  fprintf (stderr, "\tgpr_size        = %d\n", info->gpr_size);
-  fprintf (stderr, "\taccum_size      = %d\n", info->accum_size);
-  fprintf (stderr, "\ttotal_size      = %d\n", info->total_size);
-  fprintf (stderr, "\tsaved registers =");
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      if (info->save_p[i] == 2)
-	{
-	  fprintf (stderr, " %s-%s", reg_names[i], reg_names[i+1]);
-	  i++;
-	}
-      else if (info->save_p[i])
-	fprintf (stderr, " %s", reg_names[i]);
-    }
-
-  putc ('\n', stderr);
-  fflush (stderr);
-}
-
-
-/* Return non-zero if this function is known to have a null or 1 instruction epilogue.  */
-
-int
-direct_return ()
-{
-  if (reload_completed)
-    {
-      d30v_stack_t *info = d30v_stack_info ();
-
-      /* If no epilogue code is needed, can use just a simple jump */
-      if (info->total_size == 0)
-	return 1;
-
-#if 0
-      /* If just a small amount of local stack was allocated and no registers
-         saved, skip forward branch */
-      if (info->total_size == info->vars_size
-	  && IN_RANGE_P (info->total_size, 1, 31))
-	return 1;
-#endif
-    }
-
-  return 0;
-}
-
-
-/* A C statement (sans semicolon) for initializing the variable CUM for the
-   state at the beginning of the argument list.  The variable has type
-   `CUMULATIVE_ARGS'.  The value of FNTYPE is the tree node for the data type
-   of the function which will receive the args, or 0 if the args are to a
-   compiler support library function.  The value of INDIRECT is nonzero when
-   processing an indirect call, for example a call through a function pointer.
-   The value of INDIRECT is zero for a call to an explicitly named function, a
-   library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
-   arguments for the function being compiled.
-
-   When processing a call to a compiler support library function, LIBNAME
-   identifies which one.  It is a `symbol_ref' rtx which contains the name of
-   the function, as a string.  LIBNAME is 0 when an ordinary C function call is
-   being processed.  Thus, each time this macro is called, either LIBNAME or
-   FNTYPE is nonzero, but never both of them at once.  */
-
-void
-d30v_init_cumulative_args (cum, fntype, libname, indirect, incoming)
-     CUMULATIVE_ARGS *cum;
-     tree fntype;
-     rtx libname;
-     int indirect;
-     int incoming;
-{
-  *cum = GPR_ARG_FIRST;
-
-  if (TARGET_DEBUG_ARG)
-    {
-      fprintf (stderr, "\ninit_cumulative_args:");
-      if (indirect)
-	fputs (" indirect", stderr);
-
-      if (incoming)
-	fputs (" incoming", stderr);
-
-      if (fntype)
-	{
-	  tree ret_type = TREE_TYPE (fntype);
-	  fprintf (stderr, " return=%s,",
-		   tree_code_name[ (int)TREE_CODE (ret_type) ]);
-	}
-
-      if (libname && GET_CODE (libname) == SYMBOL_REF)
-	fprintf (stderr, " libname=%s", XSTR (libname, 0));
-
-      putc ('\n', stderr);
-    }
-}
-
-
-/* If defined, a C expression that gives the alignment boundary, in bits, of an
-   argument with the specified mode and type.  If it is not defined,
-   `PARM_BOUNDARY' is used for all arguments.  */
-
-int
-d30v_function_arg_boundary (mode_int, type)
-     int mode_int;
-     tree type;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  int size = ((mode == BLKmode && type)
-	      ? int_size_in_bytes (type)
-	      : GET_MODE_SIZE (mode));
-
-  return (size > UNITS_PER_WORD) ? 2*UNITS_PER_WORD : UNITS_PER_WORD;
-}
-
-
-/* A C expression that controls whether a function argument is passed in a
-   register, and which register.
-
-   The arguments are CUM, which summarizes all the previous arguments; MODE,
-   the machine mode of the argument; TYPE, the data type of the argument as a
-   tree node or 0 if that is not known (which happens for C support library
-   functions); and NAMED, which is 1 for an ordinary argument and 0 for
-   nameless arguments that correspond to `...' in the called function's
-   prototype.
-
-   The value of the expression should either be a `reg' RTX for the hard
-   register in which to pass the argument, or zero to pass the argument on the
-   stack.
-
-   For machines like the Vax and 68000, where normally all arguments are
-   pushed, zero suffices as a definition.
-
-   The usual way to make the ANSI library `stdarg.h' work on a machine where
-   some arguments are usually passed in registers, is to cause nameless
-   arguments to be passed on the stack instead.  This is done by making
-   `FUNCTION_ARG' return 0 whenever NAMED is 0.
-
-   You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
-   this macro to determine if this argument is of a type that must be passed in
-   the stack.  If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
-   returns non-zero for such an argument, the compiler will abort.  If
-   `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
-   stack and then loaded into a register.  */
-
-Rtx
-d30v_function_arg (cum, mode_int, type, named, incoming)
-     CUMULATIVE_ARGS *cum;
-     int mode_int;
-     tree type;
-     int named;
-     int incoming;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  int size = ((mode == BLKmode && type)
-	      ? int_size_in_bytes (type)
-	      : GET_MODE_SIZE (mode));
-  int adjust = (size > UNITS_PER_WORD && (*cum & 1) != 0);
-  rtx ret;
-
-  /* Return a marker for use in the call instruction.  */
-  if (mode == VOIDmode)
-    ret = const0_rtx;
-
-  else if (*cum + adjust <= GPR_ARG_LAST)
-    ret = gen_rtx (REG, mode, *cum + adjust);
-
-  else
-    ret = NULL_RTX;
-
-  if (TARGET_DEBUG_ARG)
-    fprintf (stderr,
-	     "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d, arg = %s\n",
-	     *cum, GET_MODE_NAME (mode), named, size, adjust,
-	     (ret) ? ((ret == const0_rtx) ? "<0>" : reg_names[ REGNO (ret) ]) : "memory");
-
-  return ret;
-}
-
-
-/* A C expression for the number of words, at the beginning of an argument,
-   must be put in registers.  The value must be zero for arguments that are
-   passed entirely in registers or that are entirely pushed on the stack.
-
-   On some machines, certain arguments must be passed partially in registers
-   and partially in memory.  On these machines, typically the first N words of
-   arguments are passed in registers, and the rest on the stack.  If a
-   multi-word argument (a `double' or a structure) crosses that boundary, its
-   first few words must be passed in registers and the rest must be pushed.
-   This macro tells the compiler when this occurs, and how many of the words
-   should go in registers.
-
-   `FUNCTION_ARG' for these arguments should return the first register to be
-   used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
-   the called function.  */
-
-int
-d30v_function_arg_partial_nregs (cum, mode_int, type, named)
-     CUMULATIVE_ARGS *cum;
-     int mode_int;
-     tree type;
-     int named;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  int bytes = ((mode == BLKmode)
-	       ? int_size_in_bytes (type)
-	       : GET_MODE_SIZE (mode));
-  int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-  int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
-  int arg_num = *cum + adjust;
-  int ret;
-
-  ret = ((arg_num <= GPR_ARG_LAST && arg_num + words > GPR_ARG_LAST+1)
-	 ? GPR_ARG_LAST - arg_num + 1
-	 : 0);
-
-  if (TARGET_DEBUG_ARG && ret)
-    fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
-
-  return ret;
-}
-
-
-/* A C expression that indicates when an argument must be passed by reference.
-   If nonzero for an argument, a copy of that argument is made in memory and a
-   pointer to the argument is passed instead of the argument itself.  The
-   pointer is passed in whatever way is appropriate for passing a pointer to
-   that type.
-
-   On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
-   definition of this macro might be
-        #define FUNCTION_ARG_PASS_BY_REFERENCE\
-        (CUM, MODE, TYPE, NAMED)  \
-          MUST_PASS_IN_STACK (MODE, TYPE)  */
-
-int
-d30v_function_arg_pass_by_reference (cum, mode_int, type, named)
-     CUMULATIVE_ARGS *cum;
-     int mode_int;
-     tree type;
-     int named;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  int ret = MUST_PASS_IN_STACK (mode, type);
-
-  if (TARGET_DEBUG_ARG && ret)
-    fprintf (stderr, "function_arg_pass_by_reference: %d\n", ret);
-
-  return ret;
-}
-
-
-/* A C statement (sans semicolon) to update the summarizer variable CUM to
-   advance past an argument in the argument list.  The values MODE, TYPE and
-   NAMED describe that argument.  Once this is done, the variable CUM is
-   suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
-
-   This macro need not do anything if the argument in question was passed on
-   the stack.  The compiler knows how to track the amount of stack space used
-   for arguments without any special help.  */
-
-void
-d30v_function_arg_advance (cum, mode_int, type, named)
-     CUMULATIVE_ARGS *cum;
-     int mode_int;
-     tree type;
-     int named;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  int bytes = ((mode == BLKmode)
-	       ? int_size_in_bytes (type)
-	       : GET_MODE_SIZE (mode));
-  int words = D30V_ALIGN (bytes, UNITS_PER_WORD) / UNITS_PER_WORD;
-  int adjust = (bytes > UNITS_PER_WORD && (*cum & 1) != 0);
-
-  *cum += words + adjust;
-
-  if (TARGET_DEBUG_ARG)
-    fprintf (stderr,
-	     "function_adv: words = %2d, mode = %4s, named = %d, size = %3d, adjust = %1d\n",
-	     *cum, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD, adjust);
-}
-
-
-/* If defined, is a C expression that produces the machine-specific code for a
-   call to `__builtin_saveregs'.  This code will be moved to the very beginning
-   of the function, before any parameter access are made.  The return value of
-   this function should be an RTX that contains the value to use as the return
-   of `__builtin_saveregs'.
-
-   The argument ARGS is a `tree_list' containing the arguments that were passed
-   to `__builtin_saveregs'.
-
-   If this macro is not defined, the compiler will output an ordinary call to
-   the library function `__builtin_saveregs'.  */
-
-Rtx
-d30v_expand_builtin_saveregs (args)
-     tree args;
-{
-  int offset = UNITS_PER_WORD * (GPR_ARG_LAST + 1 - GPR_ARG_FIRST);
-
-  if (TARGET_DEBUG_ARG)
-    fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
-	     offset);
-
-  return gen_rtx (PLUS, Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
-}
-
-
-/* This macro offers an alternative to using `__builtin_saveregs' and defining
-   the macro `EXPAND_BUILTIN_SAVEREGS'.  Use it to store the anonymous register
-   arguments into the stack so that all the arguments appear to have been
-   passed consecutively on the stack.  Once this is done, you can use the
-   standard implementation of varargs that works for machines that pass all
-   their arguments on the stack.
-
-   The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
-   the values that obtain after processing of the named arguments.  The
-   arguments MODE and TYPE describe the last named argument--its machine mode
-   and its data type as a tree node.
-
-   The macro implementation should do two things: first, push onto the stack
-   all the argument registers *not* used for the named arguments, and second,
-   store the size of the data thus pushed into the `int'-valued variable whose
-   name is supplied as the argument PRETEND_ARGS_SIZE.  The value that you
-   store here will serve as additional offset for setting up the stack frame.
-
-   Because you must generate code to push the anonymous arguments at compile
-   time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
-   useful on machines that have just a single category of argument register and
-   use it uniformly for all data types.
-
-   If the argument SECOND_TIME is nonzero, it means that the arguments of the
-   function are being analyzed for the second time.  This happens for an inline
-   function, which is not actually compiled until the end of the source file.
-   The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
-   this case.  */
-
-void
-d30v_setup_incoming_varargs (cum, mode_int, type, pretend_size, second_time)
-     CUMULATIVE_ARGS *cum;
-     int mode_int;
-     tree type;
-     int *pretend_size;
-     int second_time;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  if (TARGET_DEBUG_ARG)
-    fprintf (stderr,
-	     "setup_vararg: words = %2d, mode = %4s, second_time = %d\n",
-	     *cum, GET_MODE_NAME (mode), second_time);
-}
-
-
-
-/* A C compound statement that outputs the assembler code for entry to a
-   function.  The prologue is responsible for setting up the stack frame,
-   initializing the frame pointer register, saving registers that must be
-   saved, and allocating SIZE additional bytes of storage for the local
-   variables.  SIZE is an integer.  FILE is a stdio stream to which the
-   assembler code should be output.
-
-   The label for the beginning of the function need not be output by this
-   macro.  That has already been done when the macro is run.
-
-   To determine which registers to save, the macro can refer to the array
-   `regs_ever_live': element R is nonzero if hard register R is used anywhere
-   within the function.  This implies the function prologue should save
-   register R, provided it is not one of the call-used registers.
-   (`FUNCTION_EPILOGUE' must likewise use `regs_ever_live'.)
-
-   On machines that have "register windows", the function entry code does not
-   save on the stack the registers that are in the windows, even if they are
-   supposed to be preserved by function calls; instead it takes appropriate
-   steps to "push" the register stack, if any non-call-used registers are used
-   in the function.
-
-   On machines where functions may or may not have frame-pointers, the function
-   entry code must vary accordingly; it must set up the frame pointer if one is
-   wanted, and not otherwise.  To determine whether a frame pointer is in
-   wanted, the macro can refer to the variable `frame_pointer_needed'.  The
-   variable's value will be 1 at run time in a function that needs a frame
-   pointer.  *Note Elimination::.
-
-   The function entry code is responsible for allocating any stack space
-   required for the function.  This stack space consists of the regions listed
-   below.  In most cases, these regions are allocated in the order listed, with
-   the last listed region closest to the top of the stack (the lowest address
-   if `STACK_GROWS_DOWNWARD' is defined, and the highest address if it is not
-   defined).  You can use a different order for a machine if doing so is more
-   convenient or required for compatibility reasons.  Except in cases where
-   required by standard or by a debugger, there is no reason why the stack
-   layout used by GCC need agree with that used by other compilers for a
-   machine.
-
-      * A region of `current_function_pretend_args_size' bytes of
-        uninitialized space just underneath the first argument
-        arriving on the stack.  (This may not be at the very start of
-        the allocated stack region if the calling sequence has pushed
-        anything else since pushing the stack arguments.  But
-        usually, on such machines, nothing else has been pushed yet,
-        because the function prologue itself does all the pushing.)
-        This region is used on machines where an argument may be
-        passed partly in registers and partly in memory, and, in some
-        cases to support the features in `varargs.h' and `stdargs.h'.
-
-      * An area of memory used to save certain registers used by the
-        function.  The size of this area, which may also include
-        space for such things as the return address and pointers to
-        previous stack frames, is machine-specific and usually
-        depends on which registers have been used in the function.
-        Machines with register windows often do not require a save
-        area.
-
-      * A region of at least SIZE bytes, possibly rounded up to an
-        allocation boundary, to contain the local variables of the
-        function.  On some machines, this region and the save area
-        may occur in the opposite order, with the save area closer to
-        the top of the stack.
-
-      * Optionally, when `ACCUMULATE_OUTGOING_ARGS' is defined, a
-        region of `current_function_outgoing_args_size' bytes to be
-        used for outgoing argument lists of the function.  *Note
-        Stack Arguments::.
-
-   Normally, it is necessary for the macros `FUNCTION_PROLOGUE' and
-   `FUNCTION_EPILOGUE' to treat leaf functions specially.  The C variable
-   `leaf_function' is nonzero for such a function.  */
-
-/* For the d30v, move all of the prologue processing into separate insns.  */
-void
-d30v_function_prologue (stream, size)
-     FILE *stream;
-     int size;
-{
-}
-
-
-/* Called after register allocation to add any instructions needed for the
-   prologue.  Using a prologue insn is favored compared to putting all of the
-   instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
-   to intermix instructions with the saves of the caller saved registers.  In
-   some cases, it might be necessary to emit a barrier instruction as the last
-   insn to prevent such scheduling.  */
-
-void
-d30v_expand_prologue ()
-{
-  rtx sp = stack_pointer_rtx;
-  d30v_stack_t *info = d30v_stack_info ();
-  int i;
-  rtx mem_di = NULL_RTX;
-  rtx mem_si = NULL_RTX;
-  int num_memrefs = (info->memrefs_2words
-		     + info->memrefs_1word
-		     + info->memrefs_varargs);
-
-  if (TARGET_DEBUG_STACK)
-    debug_stack_info (info);
-
-  /* Grow the stack.  */
-  if (info->total_size)
-    emit_insn (gen_addsi3 (sp, sp, GEN_INT (- info->total_size)));
-
-  /* If there is more than one save, use post-increment addressing which will
-     result in smaller code, than would the normal references.  If there is
-     only one save, just do the store as normal.  */
-
-  if (num_memrefs > 1)
-    {
-      rtx save_tmp = gen_rtx (REG, Pmode, GPR_STACK_TMP);
-      rtx post_inc = gen_rtx (POST_INC, Pmode, save_tmp);
-      mem_di = gen_rtx (MEM, DImode, post_inc);
-      mem_si = gen_rtx (MEM, SImode, post_inc);
-      emit_insn (gen_addsi3 (save_tmp, sp, GEN_INT (info->save_offset)));
-    }
-  else if (num_memrefs == 1)
-    {
-      rtx addr = plus_constant (sp, info->save_offset);
-      mem_di = gen_rtx (MEM, DImode, addr);
-      mem_si = gen_rtx (MEM, SImode, addr);
-    }
-
-  /* Save the accumulators.  */
-  for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
-    if (info->save_p[i])
-      {
-	rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
-	emit_insn (gen_movdi (acc_tmp, gen_rtx (REG, DImode, i)));
-	emit_insn (gen_movdi (mem_di, acc_tmp));
-      }
-
-  /* Save the GPR registers that are adjacent to each other with st2w.  */
-  for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
-    if (info->save_p[i] == 2)
-      emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
-
-  /* Save the GPR registers that need to be saved with a single word store.  */
-  for (i = GPR_FIRST; i <= GPR_LAST; i++)
-    if (info->save_p[i] == 1)
-      emit_insn (gen_movsi (mem_si, gen_rtx (REG, SImode, i)));
-
-  /* Save the argument registers if this function accepts variable args.  */
-  if (info->varargs_p)
-    {
-      /* Realign r22 if an odd # of GPRs were saved.  */
-      if ((info->memrefs_1word & 1) != 0)
-	{
-	  rtx save_tmp = XEXP (XEXP (mem_si, 0), 0);
-	  emit_insn (gen_addsi3 (save_tmp, save_tmp, GEN_INT (UNITS_PER_WORD)));
-	}
-
-      for (i = GPR_ARG_FIRST; i <= GPR_ARG_LAST; i += 2)
-	emit_insn (gen_movdi (mem_di, gen_rtx (REG, DImode, i)));
-    }
-
-  /* Update the frame pointer.  */
-  if (frame_pointer_needed)
-    emit_move_insn (frame_pointer_rtx, sp);
-
-  /* Hack for now, to prevent scheduler from being too cleaver */
-  emit_insn (gen_blockage ());
-}
-
-
-/* A C compound statement that outputs the assembler code for exit from a
-   function.  The epilogue is responsible for restoring the saved registers and
-   stack pointer to their values when the function was called, and returning
-   control to the caller.  This macro takes the same arguments as the macro
-   `FUNCTION_PROLOGUE', and the registers to restore are determined from
-   `regs_ever_live' and `CALL_USED_REGISTERS' in the same way.
-
-   On some machines, there is a single instruction that does all the work of
-   returning from the function.  On these machines, give that instruction the
-   name `return' and do not define the macro `FUNCTION_EPILOGUE' at all.
-
-   Do not define a pattern named `return' if you want the `FUNCTION_EPILOGUE'
-   to be used.  If you want the target switches to control whether return
-   instructions or epilogues are used, define a `return' pattern with a
-   validity condition that tests the target switches appropriately.  If the
-   `return' pattern's validity condition is false, epilogues will be used.
-
-   On machines where functions may or may not have frame-pointers, the function
-   exit code must vary accordingly.  Sometimes the code for these two cases is
-   completely different.  To determine whether a frame pointer is wanted, the
-   macro can refer to the variable `frame_pointer_needed'.  The variable's
-   value will be 1 when compiling a function that needs a frame pointer.
-
-   Normally, `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' must treat leaf
-   functions specially.  The C variable `leaf_function' is nonzero for such a
-   function.  *Note Leaf Functions::.
-
-   On some machines, some functions pop their arguments on exit while others
-   leave that for the caller to do.  For example, the 68020 when given `-mrtd'
-   pops arguments in functions that take a fixed number of arguments.
-
-   Your definition of the macro `RETURN_POPS_ARGS' decides which functions pop
-   their own arguments.  `FUNCTION_EPILOGUE' needs to know what was decided.
-   The variable that is called `current_function_pops_args' is the number of
-   bytes of its arguments that a function should pop.  *Note Scalar Return::.  */
-
-/* For the d30v, move all processing to be as insns, but do any cleanup
-   here, since it is done after handling all of the insns.  */
-void
-d30v_function_epilogue (stream, size)
-     FILE *stream;
-     int size;
-{
-  d30v_stack_cache = (d30v_stack_t *)0;	/* reset stack cache */
-}
-
-
-
-/* Called after register allocation to add any instructions needed for the
-   epilogue.  Using a epilogue insn is favored compared to putting all of the
-   instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
-   to intermix instructions with the saves of the caller saved registers.  In
-   some cases, it might be necessary to emit a barrier instruction as the last
-   insn to prevent such scheduling.  */
-
-void
-d30v_expand_epilogue ()
-{
-  rtx sp = stack_pointer_rtx;
-  d30v_stack_t *info = d30v_stack_info ();
-  int i;
-  rtx mem_di = NULL_RTX;
-  rtx mem_si = NULL_RTX;
-  int num_memrefs = info->memrefs_2words + info->memrefs_1word;
-  rtx post_inc;
-  int extra_stack;
-
-  /* Hack for now, to prevent scheduler from being too cleaver */
-  emit_insn (gen_blockage ());
-
-  /* Restore sp from fp.  */
-  if (frame_pointer_needed)
-    emit_move_insn (sp, frame_pointer_rtx);
-
-  /* For the epilogue, use post-increment addressing all of the time.  First
-     adjust the sp, to eliminate all of the stack, except for the save area.  */
-
-  if (info->save_offset)
-    emit_insn (gen_addsi3 (sp, sp, GEN_INT (info->save_offset)));
-
-  post_inc = gen_rtx (POST_INC, Pmode, sp);
-  mem_di = gen_rtx (MEM, DImode, post_inc);
-  mem_si = gen_rtx (MEM, SImode, post_inc);
-
-  /* Restore the accumulators.  */
-  for (i = ACCUM_FIRST; i <= ACCUM_LAST; i++)
-    if (info->save_p[i])
-      {
-	rtx acc_tmp = gen_rtx (REG, DImode, GPR_ATMP_FIRST);
-	emit_insn (gen_movdi (acc_tmp, mem_di));
-	emit_insn (gen_movdi (gen_rtx (REG, DImode, i), acc_tmp));
-      }
-
-  /* Restore the GPR registers that are adjacent to each other with ld2w.  */
-  for (i = GPR_FIRST; i <= GPR_LAST; i += 2)
-    if (info->save_p[i] == 2)
-      emit_insn (gen_movdi (gen_rtx (REG, DImode, i), mem_di));
-
-  /* Save the GPR registers that need to be saved with a single word store.  */
-  for (i = GPR_FIRST; i <= GPR_LAST; i++)
-    if (info->save_p[i] == 1
-	&& ! (d30v_eh_epilogue_sp_ofs && i == GPR_LINK))
-      emit_insn (gen_movsi (gen_rtx (REG, SImode, i), mem_si));
-
-  /* Release any remaining stack that was allocated for saving the
-     varargs registers or because an odd # of registers were stored.  */
-  extra_stack = info->varargs_size;
-  if ((info->memrefs_1word & 1) != 0)
-    extra_stack += UNITS_PER_WORD;
-
-  if (extra_stack)
-    emit_insn (gen_addsi3 (sp, sp, GEN_INT (extra_stack)));
-
-  /* ??? Should try to combine this with the above add?  */
-  if (d30v_eh_epilogue_sp_ofs)
-    emit_insn (gen_addsi3 (sp, sp, d30v_eh_epilogue_sp_ofs));
-
-  /* Hack for now, to prevent scheduler from being too cleaver */
-  emit_insn (gen_blockage ());
-
-  /* Now emit the return instruction.  */
-  emit_jump_insn (gen_indirect_jump (gen_rtx (REG, Pmode, GPR_LINK)));
-}
-
-
-/* A C statement or compound statement to output to FILE some assembler code to
-   call the profiling subroutine `mcount'.  Before calling, the assembler code
-   must load the address of a counter variable into a register where `mcount'
-   expects to find the address.  The name of this variable is `LP' followed by
-   the number LABELNO, so you would generate the name using `LP%d' in a
-   `fprintf'.
-
-   The details of how the address should be passed to `mcount' are determined
-   by your operating system environment, not by GNU CC.  To figure them out,
-   compile a small program for profiling using the system's installed C
-   compiler and look at the assembler code that results.  */
-
-void
-d30v_function_profiler (stream, labelno)
-     FILE *stream;
-     int labelno;
-{
-  fprintf (stream, "# profile\n");
-}
-
-
-/* Split a 64 bit item into an upper and a lower part.  We specifically do not
-   want to call gen_highpart/gen_lowpart on CONST_DOUBLEs since it will give us
-   the wrong part for floating point in cross compilers, and split_double does
-   not handle registers.  Also abort if the register is not a general purpose
-   register.  */
-
-void
-d30v_split_double (value, p_high, p_low)
-     rtx value;
-     rtx *p_high;
-     rtx *p_low;
-{
-  int offset = 0;
-  int regno;
-
-  if (!reload_completed)
-    abort ();
-
-  switch (GET_CODE (value))
-    {
-    case SUBREG:
-      offset = SUBREG_WORD (value);
-      value = SUBREG_REG (value);
-      if (GET_CODE (value) != REG)
-	abort ();
-
-      /* fall through */
-
-    case REG:
-      regno = REGNO (value) + offset;
-      if (!GPR_P (regno))
-	abort ();
-
-      *p_high = gen_rtx (REG, SImode, regno);
-      *p_low =  gen_rtx (REG, SImode, regno+1);
-      break;
-
-    case CONST_INT:
-    case CONST_DOUBLE:
-      split_double (value, p_high, p_low);
-      break;
-
-    default:
-      abort ();
-    }
-}
-
-
-/* A C compound statement to output to stdio stream STREAM the assembler syntax
-   for an instruction operand that is a memory reference whose address is X.  X
-   is an RTL expression.
-
-   On some machines, the syntax for a symbolic address depends on the section
-   that the address refers to.  On these machines, define the macro
-   `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
-   then check for it here.  *Note Assembler Format::.  */
-
-void
-d30v_print_operand_address (stream, x)
-     FILE *stream;
-     rtx x;
-{
-  if (GET_CODE (x) == MEM)
-    x = XEXP (x, 0);
-
-  switch (GET_CODE (x))
-    {
-    default:
-      break;
-
-    case REG:
-      fputs (reg_names[ REGNO (x) ], stream);
-      return;
-
-    case CONST_INT:
-      fprintf (stream, "%ld", (long) INTVAL (x));
-      return;
-
-    /* We wrap simple symbol refs inside a parenthesis, so that a name
-       like `r2' is not taken for a register name.  */
-    case SYMBOL_REF:
-      fputs ("(", stream);
-      assemble_name (stream, XSTR (x, 0));
-      fputs (")", stream);
-      return;
-
-    case LABEL_REF:
-    case CONST:
-      output_addr_const (stream, x);
-      return;
-    }
-
-  fatal_insn ("Bad insn to d30v_print_operand_address:", x);
-}
-
-
-/* Print a memory reference suitable for the ld/st instructions.  */
-
-static void
-d30v_print_operand_memory_reference (stream, x)
-     FILE *stream;
-     rtx x;
-{
-  rtx x0 = NULL_RTX;
-  rtx x1 = NULL_RTX;
-
-  switch (GET_CODE (x))
-    {
-    default:
-      fatal_insn ("Bad insn to d30v_print_operand_memory_reference:", x);
-      break;
-
-    case SUBREG:
-    case REG:
-    case POST_DEC:
-    case POST_INC:
-      x0 = x;
-      break;
-
-    case CONST_INT:
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case CONST:
-      x1 = x;
-      break;
-
-    case PLUS:
-      x0 = XEXP (x, 0);
-      x1 = XEXP (x, 1);
-      if (GET_CODE (x0) == CONST_INT || GET_CODE (x0) == SYMBOL_REF
-	  || GET_CODE (x0) == CONST || GET_CODE (x0) == LABEL_REF)
-	{
-	  x0 = XEXP (x, 1);
-	  x1 = XEXP (x, 0);
-	}
-      break;
-    }
-
-  fputs ("@(", stream);
-  if (!x0)
-    fputs (reg_names[GPR_R0], stream);
-
-  else
-    {
-      char *suffix = "";
-      int offset0  = 0;
-
-      if (GET_CODE (x0) == SUBREG)
-	{
-	  offset0 = SUBREG_WORD (x0);
-	  x0 = SUBREG_REG (x0);
-	}
-
-      if (GET_CODE (x0) == POST_INC)
-	{
-	  x0 = XEXP (x0, 0);
-	  suffix = "+";
-	}
-      else if (GET_CODE (x0) == POST_DEC)
-	{
-	  x0 = XEXP (x0, 0);
-	  suffix = "-";
-	}
-
-      if (GET_CODE (x0) == REG && GPR_P (REGNO (x0)))
-	fprintf (stream, "%s%s", reg_names[REGNO (x0) + offset0], suffix);
-      else
-	fatal_insn ("Bad insn to d30v_print_operand_memory_reference:", x);
-    }
-
-  fputs (",", stream);
-
-  if (!x1)
-    fputs (reg_names[GPR_R0], stream);
-
-  else
-    {
-      int offset1 = 0;
-
-      switch (GET_CODE (x1))
-	{
-	case SUBREG:
-	  offset1 = SUBREG_WORD (x1);
-	  x1 = SUBREG_REG (x1);
-	  if (GET_CODE (x1) != REG)
-	    fatal_insn ("Bad insn to d30v_print_operand_memory_reference:", x);
-
-	  /* fall through */
-	case REG:
-	  fputs (reg_names[REGNO (x1) + offset1], stream);
-	  break;
-
-	case CONST_INT:
-	  fprintf (stream, "%ld", (long) INTVAL (x1));
-	  break;
-
-	case SYMBOL_REF:
-	case LABEL_REF:
-	case CONST:
-	  d30v_print_operand_address (stream, x1);
-	  break;
-
-	default:
-	  fatal_insn ("Bad insn to d30v_print_operand_memory_reference:", x);
-	}
-    }
-
-  fputs (")", stream);
-}
-
-
-/* A C compound statement to output to stdio stream STREAM the assembler syntax
-   for an instruction operand X.  X is an RTL expression.
-
-   LETTER is a value that can be used to specify one of several ways of
-   printing the operand.  It is used when identical operands must be printed
-   differently depending on the context.  LETTER comes from the `%'
-   specification that was used to request printing of the operand.  If the
-   specification was just `%DIGIT' then LETTER is 0; if the specification was
-   `%LTR DIGIT' then LETTER is the ASCII code for LTR.
-
-   If X is a register, this macro should print the register's name.  The names
-   can be found in an array `reg_names' whose type is `char *[]'.  `reg_names'
-   is initialized from `REGISTER_NAMES'.
-
-   When the machine description has a specification `%PUNCT' (a `%' followed by
-   a punctuation character), this macro is called with a null pointer for X and
-   the punctuation character for LETTER.
-
-   Standard operand flags that are handled elsewhere:
-	`='  Output a number unique to each instruction in the compilation.
-	`a'  Substitute an operand as if it were a memory reference.
-	`c'  Omit the syntax that indicates an immediate operand.
-	`l'  Substitute a LABEL_REF into a jump instruction.
-	`n'  Like %cDIGIT, except negate the value before printing.
-
-   The d30v specific operand flags are:
-	`.'  Print r0.
-	`f'  Print a SF constant as an int.
-	`s'  Subtract 32 and negate.
-	`A'  Print accumulator number without an `a' in front of it.
-	`B'  Print bit offset for BSET, etc. instructions.
-	`E'  Print u if this is zero extend, nothing if this is sign extend.
-	`F'  Emit /{f,t,x}{f,t,x} for executing a false condition.
-	`L'  Print the lower half of a 64 bit item.
-	`M'  Print a memory reference for ld/st instructions.
-	`R'  Return appropriate cmp instruction for relational test.
-	`S'  Subtract 32.
-	`T'  Emit /{f,t,x}{f,t,x} for executing a true condition.
-	`U'  Print the upper half of a 64 bit item.  */
-
-void
-d30v_print_operand (stream, x, letter)
-     FILE *stream;
-     rtx x;
-     int letter;
-{
-  enum rtx_code code = (x) ? GET_CODE (x) : NIL;
-  rtx split_values[2];
-  REAL_VALUE_TYPE rv;
-  long num;
-  int log;
-
-  switch (letter)
-    {
-    case '.':	/* Output r0 */
-      fputs (reg_names[GPR_R0], stream);
-      break;
-
-    case 'f':	/* Print a SF floating constant as an int */
-      if (GET_CODE (x) != CONST_DOUBLE)
-	fatal_insn ("Bad insn to d30v_print_operand, 'f' modifier:", x);
-
-      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-      REAL_VALUE_TO_TARGET_SINGLE (rv, num);
-      fprintf (stream, "%ld", num);
-      break;
-
-    case 'A':	/* Print accumulator number without an `a' in front of it.  */
-      if (GET_CODE (x) != REG || !ACCUM_P (REGNO (x)))
-	fatal_insn ("Bad insn to d30v_print_operand, 'A' modifier:", x);
-
-      putc ('0' + REGNO (x) - ACCUM_FIRST, stream);
-      break;
-
-    case 'M':	/* Print a memory reference for ld/st */
-      if (GET_CODE (x) != MEM)
-	fatal_insn ("Bad insn to d30v_print_operand, 'M' modifier:", x);
-
-      d30v_print_operand_memory_reference (stream, XEXP (x, 0));
-      break;
-
-    case 'L':	/* print lower part of 64 bit item. */
-    case 'U':	/* print upper part of 64 bit item. */
-      d30v_split_double (x, &split_values[0], &split_values[1]);
-      d30v_print_operand (stream, split_values[ letter == 'L' ], '\0');
-      break;
-
-    case 'F':	/* Print an appropriate suffix for a false comparision.  */
-    case 'T':	/* Print an appropriate suffix for a true  comparision.  */
-      /* Note that the sense of appropriate suffix is for conditional execution
-	 and opposite of what branches want.  Branches just use the inverse
-	 operation.  */
-      if ((GET_CODE (x) == NE || GET_CODE (x) == EQ)
-	  && GET_MODE (x) == CCmode
-	  && GET_CODE (XEXP (x, 0)) == REG
-	  && (GPR_P (REGNO (XEXP (x, 0))) || BR_FLAG_P (REGNO (XEXP (x, 0))))
-	  && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
-	{
-	  int true_false = (letter == 'T');
-
-	  if (GET_CODE (x) == EQ)
-	    true_false = !true_false;
-
-	  if (REGNO (XEXP (x, 0)) == FLAG_F0)
-	    fprintf (stream, "/%cx", (true_false) ? 'f' : 't');
-
-	  else if (REGNO (XEXP (x, 0)) == FLAG_F1)
-	    fprintf (stream, "/x%c", (true_false) ? 'f' : 't');
-
-	  else
-	    fputs ((true_false) ? "tnz" : "tzr", stream);
-	}
-
-      else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F0)
-	fprintf (stream, "/%cx", (letter == 'T') ? 't' : 'f');
-
-      else if (GET_CODE (x) == REG && REGNO (x) == FLAG_F1)
-	fprintf (stream, "/x%c", (letter == 'T') ? 't' : 'f');
-
-      else if (GET_CODE (x) == REG && GPR_P (REGNO (x)))
-	fputs ((letter == 'T') ? "tnz" : "tzr", stream);
-
-      else
-	fatal_insn ("Bad insn to print_operand, 'F' or 'T' modifier:", x);
-      break;
-
-    case 'B':	/* emit offset single bit to change */
-      if (GET_CODE (x) == CONST_INT && (log = exact_log2 (INTVAL (x))) >= 0)
-	fprintf (stream, "%d", 31 - log);
-
-      else if (GET_CODE (x) == CONST_INT && (log = exact_log2 (~ INTVAL (x))) >= 0)
-	fprintf (stream, "%d", 31 - log);
-
-      else
-	fatal_insn ("Bad insn to print_operand, 'B' modifier:", x);
-      break;
-
-    case 'E':	/* Print u if this is zero extend, nothing if sign extend. */
-      if (GET_CODE (x) == ZERO_EXTEND)
-	putc ('u', stream);
-      else if (GET_CODE (x) != SIGN_EXTEND)
-	fatal_insn ("Bad insn to print_operand, 'E' modifier:", x);
-      break;
-
-    case 'R':	/* Return appropriate cmp instruction for relational test.  */
-      switch (GET_CODE (x))
-	{
-	case EQ:  fputs ("cmpeq",  stream); break;
-	case NE:  fputs ("cmpne",  stream); break;
-	case LT:  fputs ("cmplt",  stream); break;
-	case LE:  fputs ("cmple",  stream); break;
-	case GT:  fputs ("cmpgt",  stream); break;
-	case GE:  fputs ("cmpge",  stream); break;
-	case LTU: fputs ("cmpult", stream); break;
-	case LEU: fputs ("cmpule", stream); break;
-	case GTU: fputs ("cmpugt", stream); break;
-	case GEU: fputs ("cmpuge", stream); break;
-
-	default:
-	  fatal_insn ("Bad insn to print_operand, 'R' modifier:", x);
-	}
-      break;
-
-    case 's':	/* Subtract 32 and negate (for 64 bit shifts).  */
-      if (GET_CODE (x) == CONST_INT)
-	fprintf (stream, "%d", (int) (32 - INTVAL (x)));
-
-      else
-	fatal_insn ("Bad insn to print_operand, 's' modifier:", x);
-      break;
-
-    case 'S':	/* Subtract 32.  */
-      if (GET_CODE (x) == CONST_INT)
-	fprintf (stream, "%d", (int)(INTVAL (x) - 32));
-
-      else
-	fatal_insn ("Bad insn to print_operand, 's' modifier:", x);
-      break;
-
-
-    case '\0':
-      if (code == REG)
-	fputs (reg_names[ REGNO (x) ], stream);
-
-      else if (code == CONST_INT)
-	fprintf (stream, "%d", (int)INTVAL (x));
-
-      else if (code == MEM)
-	d30v_print_operand_address (stream, XEXP (x, 0));
-
-      else if (CONSTANT_ADDRESS_P (x))
-	d30v_print_operand_address (stream, x);
-
-      else
-	fatal_insn ("Bad insn in d30v_print_operand, 0 case", x);
-
-      return;
-
-    default:
-      {
-	char buf[80];
-
-	sprintf (buf, "Invalid asm template character '%%%c'", letter);
-	fatal_insn (buf, x);
-      }
-    }
-}
-
-
-/* A C expression for the size in bytes of the trampoline, as an integer.  */
-
-int
-d30v_trampoline_size ()
-{
-  return 16;
-}
-
-
-/* Create a long instruction for building up a trampoline.  */
-
-static void
-d30v_build_long_insn (high_bits, low_bits, imm, mem)
-     HOST_WIDE_INT high_bits;
-     HOST_WIDE_INT low_bits;
-     rtx imm;
-     rtx mem;
-{
-  rtx reg = gen_reg_rtx (DImode);
-  rtx high_word = gen_highpart (SImode, reg);
-  rtx low_word = gen_lowpart (SImode, reg);
-  rtx tmp1 = gen_reg_rtx (SImode);
-  rtx tmp2 = gen_reg_rtx (SImode);
-  rtx tmp3 = gen_reg_rtx (SImode);
-  rtx tmp4 = gen_reg_rtx (SImode);
-  rtx tmp5 = gen_reg_rtx (SImode);
-  rtx tmp6 = gen_reg_rtx (SImode);
-
-  imm = force_reg (SImode, imm);
-
-  /* Stuff top 6 bits of immediate value into high word */
-  emit_insn (gen_lshrsi3 (tmp1, imm, GEN_INT (26)));
-  emit_insn (gen_andsi3 (tmp2, tmp1, GEN_INT (0x3F)));
-  emit_insn (gen_iorsi3 (high_word, tmp2, GEN_INT (high_bits)));
-
-  /* Now get the next 8 bits for building the low word */
-  emit_insn (gen_andsi3 (tmp3, imm, GEN_INT (0x03FC0000)));
-  emit_insn (gen_ashlsi3 (tmp4, tmp3, GEN_INT (2)));
-
-  /* And the bottom 18 bits */
-  emit_insn (gen_andsi3 (tmp5, imm, GEN_INT (0x0003FFFF)));
-  emit_insn (gen_iorsi3 (tmp6, tmp4, tmp5));
-  emit_insn (gen_iorsi3 (low_word, tmp6, GEN_INT (low_bits)));
-
-  /* Store the instruction */
-  emit_insn (gen_movdi (mem, reg));
-}
-
-
-/* A C statement to initialize the variable parts of a trampoline.  ADDR is an
-   RTX for the address of the trampoline; FNADDR is an RTX for the address of
-   the nested function; STATIC_CHAIN is an RTX for the static chain value that
-   should be passed to the function when it is called.  */
-
-void
-d30v_initialize_trampoline (addr, fnaddr, static_chain)
-     rtx addr;
-     rtx fnaddr;
-     rtx static_chain;
-{
-  /* The instruction space can only be accessed by ld2w/st2w.
-     Generate on the fly:
-	or r18,r0,<static-chain>
-	jmp <fnaddr> */
-  d30v_build_long_insn (0x83A80000 | ((STATIC_CHAIN_REGNUM - GPR_FIRST) << 12),
-			0x80000000, static_chain,
-			gen_rtx (MEM, DImode, addr));
-
-  d30v_build_long_insn (0x80180000, 0x80000000, fnaddr,
-			gen_rtx (MEM, DImode, plus_constant (addr, 8)));
-}
-
-
-/* A C compound statement with a conditional `goto LABEL;' executed if X (an
-   RTX) is a legitimate memory address on the target machine for a memory
-   operand of mode MODE.
-
-   It usually pays to define several simpler macros to serve as subroutines for
-   this one.  Otherwise it may be too complicated to understand.
-
-   This macro must exist in two variants: a strict variant and a non-strict
-   one.  The strict variant is used in the reload pass.  It must be defined so
-   that any pseudo-register that has not been allocated a hard register is
-   considered a memory reference.  In contexts where some kind of register is
-   required, a pseudo-register with no hard register must be rejected.
-
-   The non-strict variant is used in other passes.  It must be defined to
-   accept all pseudo-registers in every context where some kind of register is
-   required.
-
-   Compiler source files that want to use the strict variant of this macro
-   define the macro `REG_OK_STRICT'.  You should use an `#ifdef REG_OK_STRICT'
-   conditional to define the strict variant in that case and the non-strict
-   variant otherwise.
-
-   Subroutines to check for acceptable registers for various purposes (one for
-   base registers, one for index registers, and so on) are typically among the
-   subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'.  Then only these
-   subroutine macros need have two variants; the higher levels of macros may be
-   the same whether strict or not.
-
-   Normally, constant addresses which are the sum of a `symbol_ref' and an
-   integer are stored inside a `const' RTX to mark them as constant.
-   Therefore, there is no need to recognize such sums specifically as
-   legitimate addresses.  Normally you would simply recognize any `const' as
-   legitimate.
-
-   Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
-   are not marked with `const'.  It assumes that a naked `plus' indicates
-   indexing.  If so, then you *must* reject such naked constant sums as
-   illegitimate addresses, so that none of them will be given to
-   `PRINT_OPERAND_ADDRESS'.
-
-   On some machines, whether a symbolic address is legitimate depends on the
-   section that the address refers to.  On these machines, define the macro
-   `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
-   then check for it here.  When you see a `const', you will have to look
-   inside it to find the `symbol_ref' in order to determine the section.  *Note
-   Assembler Format::.
-
-   The best way to modify the name string is by adding text to the beginning,
-   with suitable punctuation to prevent any ambiguity.  Allocate the new name
-   in `saveable_obstack'.  You will have to modify `ASM_OUTPUT_LABELREF' to
-   remove and decode the added text and output the name accordingly, and define
-   `STRIP_NAME_ENCODING' to access the original name string.
-
-   You can check the information stored here into the `symbol_ref' in the
-   definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
-   `PRINT_OPERAND_ADDRESS'.
-
-   Return 0 if the address is not legitimate, 1 if the address would fit
-   in a short instruction, or 2 if the address would fit in a long
-   instruction.  */
-
-#define XREGNO_OK_FOR_BASE_P(REGNO, STRICT_P)				\
-((STRICT_P)								\
- ? REGNO_OK_FOR_BASE_P (REGNO)						\
- : GPR_OR_PSEUDO_P (REGNO))
-
-int
-d30v_legitimate_address_p (mode_int, x, strict_p)
-     int mode_int;
-     rtx x;
-     int strict_p;
-{
-  enum machine_mode mode = (enum machine_mode) mode_int;
-  rtx x0, x1;
-  int ret = 0;
-
-  switch (GET_CODE (x))
-    {
-    default:
-      break;
-
-    case SUBREG:
-      x = SUBREG_REG (x);
-      if (GET_CODE (x) != REG)
-	break;
-
-      /* fall through */
-
-    case REG:
-      ret = XREGNO_OK_FOR_BASE_P (REGNO (x), strict_p);
-      break;
-
-    case PLUS:
-      x0 = XEXP (x, 0);
-      x1 = XEXP (x, 1);
-
-      if (GET_CODE (x0) == SUBREG)
-	x0 = SUBREG_REG (x0);
-
-      if (GET_CODE (x0) == POST_INC || GET_CODE (x0) == POST_DEC)
-	x0 = XEXP (x0, 0);
-
-      if (GET_CODE (x0) != REG || !XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
-	break;
-
-      switch (GET_CODE (x1))
-	{
-	default:
-	  break;
-
-	case SUBREG:
-	  x1 = SUBREG_REG (x1);
-	  if (GET_CODE (x1) != REG)
-	    break;
-
-	  /* fall through */
-
-	case REG:
-	  ret = XREGNO_OK_FOR_BASE_P (REGNO (x1), strict_p);
-	  break;
-
-	case CONST_INT:
-	  ret = (IN_RANGE_P (INTVAL (x1), -32, 31)) ? 1 : 2;
-	  break;
-
-	case SYMBOL_REF:
-	case LABEL_REF:
-	case CONST:
-	  ret = 2;
-	  break;
-	}
-      break;
-
-    case CONST_INT:
-      ret = (IN_RANGE_P (INTVAL (x), -32, 31)) ? 1 : 2;
-      break;
-
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case CONST:
-      ret = 2;
-      break;
-
-    case POST_INC:
-    case POST_DEC:
-      x0 = XEXP (x, 0);
-      if (GET_CODE (x0) == REG && XREGNO_OK_FOR_BASE_P (REGNO (x0), strict_p))
-	ret = 1;
-      break;
-    }
-
-  if (TARGET_DEBUG_ADDR)
-    {
-      fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict\n",
-	       GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ");
-      debug_rtx (x);
-    }
-
-  return ret;
-}
-
-
-/* A C compound statement that attempts to replace X with a valid memory
-   address for an operand of mode MODE.  WIN will be a C statement label
-   elsewhere in the code; the macro definition may use
-
-        GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
-
-   to avoid further processing if the address has become legitimate.
-
-   X will always be the result of a call to `break_out_memory_refs', and OLDX
-   will be the operand that was given to that function to produce X.
-
-   The code generated by this macro should not alter the substructure of X.  If
-   it transforms X into a more legitimate form, it should assign X (which will
-   always be a C variable) a new value.
-
-   It is not necessary for this macro to come up with a legitimate address.
-   The compiler has standard ways of doing so in all cases.  In fact, it is
-   safe for this macro to do nothing.  But often a machine-dependent strategy
-   can generate better code.  */
-
-Rtx
-d30v_legitimize_address (x, oldx, mode_int, strict_p)
-     rtx x;
-     rtx oldx;
-     int mode_int;
-     int strict_p;
-{
-  enum machine_mode mode = (enum machine_mode)mode_int;
-  rtx ret = NULL_RTX;
-
-  if (TARGET_DEBUG_ADDR)
-    {
-      if (ret)
-	{
-	  fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, transformed:\n");
-	  debug_rtx (x);
-	  fprintf (stderr, "\ninto:\n");
-	  debug_rtx (ret);
-	}
-      else
-	{
-	  fprintf (stderr, "\n========== LEGITIMIZE_ADDRESS, did nothing with:\n");
-	  debug_rtx (x);
-	}
-    }
-
-  return ret;
-}
-
-
-/* A C statement or compound statement with a conditional `goto LABEL;'
-   executed if memory address X (an RTX) can have different meanings depending
-   on the machine mode of the memory reference it is used for or if the address
-   is valid for some modes but not others.
-
-   Autoincrement and autodecrement addresses typically have mode-dependent
-   effects because the amount of the increment or decrement is the size of the
-   operand being addressed.  Some machines have other mode-dependent addresses.
-   Many RISC machines have no mode-dependent addresses.
-
-   You may assume that ADDR is a valid address for the machine.  */
-
-int
-d30v_mode_dependent_address_p (addr)
-     rtx addr;
-{
-  switch (GET_CODE (addr))
-    {
-    default:
-      break;
-
-    case POST_INC:
-    case POST_DEC:
-      return TRUE;
-    }
-
-  return FALSE;
-}
-
-
-/* Generate the appropriate comparison code for a test.  */
-
-rtx
-d30v_emit_comparison (test_int, result, arg1, arg2)
-     int test_int;
-     rtx result;
-     rtx arg1;
-     rtx arg2;
-{
-  enum rtx_code test = (enum rtx_code) test_int;
-  enum machine_mode mode = GET_MODE (arg1);
-  rtx rtx_test = gen_rtx (SET, VOIDmode, result, gen_rtx (test, CCmode, arg1, arg2));
-
-  if (mode == SImode
-      || (mode == DImode && (test == EQ || test == NE))
-      || (mode == DImode && (test == LT || test == GE)
-	  && GET_CODE (arg2) == CONST_INT && INTVAL (arg2) == 0))
-    return rtx_test;
-
-  else if (mode == DImode)
-    return gen_rtx (PARALLEL, VOIDmode,
-		    gen_rtvec (2,
-			       rtx_test,
-			       gen_rtx (CLOBBER, VOIDmode,
-					gen_reg_rtx (CCmode))));
-
-  else
-    fatal_insn ("d30v_emit_comparison", rtx_test);
-}
-
-
-/* Return appropriate code to move 2 words.  Since DImode registers must start
-   on even register numbers, there is no possibility of overlap.  */
-
-char *
-d30v_move_2words (operands, insn)
-     rtx operands[];
-     rtx insn;
-{
-  if (GET_CODE (operands[0]) == REG && GPR_P (REGNO (operands[0])))
-    {
-      if (GET_CODE (operands[1]) == REG && GPR_P (REGNO (operands[1])))
-	return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
-
-      else if (GET_CODE (operands[1]) == REG && ACCUM_P (REGNO (operands[1])))
-	return "mvfacc %L0,%1,%.\n\tmvfacc %U0,%1,32";
-
-      else if (GET_CODE (operands[1]) == MEM)
-	return "ld2w %0,%M1";
-
-      else if (GET_CODE (operands[1]) == CONST_INT
-	       || GET_CODE (operands[1]) == CONST_DOUBLE)
-	return "or %U0,%.,%U1\n\tor %L0,%.,%L1";
-    }
-
-  else if (GET_CODE (operands[0]) == REG && ACCUM_P (REGNO (operands[0])))
-    {
-      if (GET_CODE (operands[1]) == REG
-	  && GPR_P (REGNO (operands[1])))
-	return "mvtacc %0,%U1,%L1";
-
-      if (GET_CODE (operands[1]) == CONST_INT
-	  && INTVAL (operands[1]) == 0)
-	return "mvtacc %0,%.,%.";
-    }
-
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (operands[1]) == REG
-	   && GPR_P (REGNO (operands[1])))
-    return "st2w %1,%M0";
-
-  fatal_insn ("Bad call to d30v_move_2words", insn);
-}
-
-
-/* Emit the code to do a conditional move instruction.  Return FALSE
-   if the conditional move could not be executed.  */
-
-int
-d30v_emit_cond_move (dest, test, true_value, false_value)
-     rtx dest;
-     rtx test;
-     rtx true_value;
-     rtx false_value;
-{
-  rtx br_reg;
-  enum machine_mode mode = GET_MODE (dest);
-
-  if (GET_CODE (dest) == MEM)
-    {
-      if (!reg_or_0_operand (true_value, mode))
-	return FALSE;
-
-      if (!reg_or_0_operand (false_value, mode))
-	return FALSE;
-    }
-
-  br_reg = gen_reg_rtx (CCmode);
-
-  /* Recognize simple sequences better done with mvfsys.  */
-  if ((true_value == const1_rtx && false_value == const0_rtx)
-      || (true_value == const0_rtx && false_value == const1_rtx
-	  && GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT))
-    {
-      enum rtx_code code = GET_CODE (test);
-
-      if (true_value == const0_rtx)
-	code = reverse_condition (code);
-
-      emit_insn (d30v_emit_comparison (code, br_reg,
-				       d30v_compare_op0, d30v_compare_op1));
-
-      if (mode != SImode)
-	dest = gen_rtx (SUBREG, SImode, dest, 0);
-
-      emit_insn (gen_rtx (SET, SImode, dest,
-			  gen_rtx (EQ, SImode, br_reg, const1_rtx)));
-      return TRUE;
-    }
-
-  emit_insn (d30v_emit_comparison (GET_CODE (test), br_reg,
-				   d30v_compare_op0, d30v_compare_op1));
-
-  emit_insn (gen_rtx (SET, VOIDmode,
-		      dest,
-		      gen_rtx (IF_THEN_ELSE, mode,
-			       gen_rtx (NE, CCmode, br_reg, const0_rtx),
-			       true_value,
-			       false_value)));
-  return TRUE;
-}
-
-
-/* Output a conditional move instruction
-   operands[0] is the destination
-   operands[1] is the NE test
-   operands[2] is f0 or f1
-   operands[3] is the value to move if the test was true
-   operands[4] is the value to move if the test was false  */
-
-char *
-d30v_cond_move (operands, insn, load, store)
-     rtx operands[];
-     rtx insn;
-     char *load;
-     char *store;
-{
-  rtx dest = operands[0];
-  enum machine_mode mode = GET_MODE (dest);
-  char buffer[80];
-
-  if (GET_CODE (dest) == REG)
-    {
-      /* Move value into register for false condition */
-      switch (GET_CODE (operands[4]))
-	{
-	case REG:
-	  if (REGNO (operands[4]) != REGNO (operands[0]))
-	    output_asm_insn ("or%T1 %0,%.,%4", operands);
-	  break;
-
-	case MEM:
-	  sprintf (buffer, "%s%%T1 %%0,%%M4", load);
-	  output_asm_insn (buffer, operands);
-	  break;
-
-	case CONST_INT:
-	case SYMBOL_REF:
-	case LABEL_REF:
-	case CONST:
-	  output_asm_insn ("or%T1 %0,%.,%4", operands);
-	  break;
-
-	case CONST_DOUBLE:
-	  output_asm_insn ("or%T1 %0,%.,%f4", operands);
-	  break;
-
-	default:
-	  fatal_insn ("d30v_cond_move", insn);
-	}
-
-      /* Move value into register for true condition */
-      switch (GET_CODE (operands[3]))
-	{
-	case REG:
-	  if (REGNO (operands[3]) != REGNO (operands[0]))
-	    output_asm_insn ("or%F1 %0,%.,%3", operands);
-	  break;
-
-	case MEM:
-	  sprintf (buffer, "%s%%F1 %%0,%%M3", load);
-	  output_asm_insn (buffer, operands);
-	  break;
-
-	case CONST_INT:
-	case SYMBOL_REF:
-	case LABEL_REF:
-	case CONST:
-	  output_asm_insn ("or%F1 %0,%.,%3", operands);
-	  break;
-
-	case CONST_DOUBLE:
-	  output_asm_insn ("or%F1 %0,%.,%f3", operands);
-	  break;
-
-	default:
-	  fatal_insn ("d30v_cond_move", insn);
-	}
-    }
-
-  else if (GET_CODE (dest) == MEM)
-    {
-      sprintf (buffer, "%s%%T1 %s,%M0", store,
-	       (GET_CODE (operands[4]) == CONST_INT ? "%." : "%4"));
-      output_asm_insn (buffer, operands);
-
-      sprintf (buffer, "%s%%F1 %s,%M0", store,
-	       (GET_CODE (operands[3]) == CONST_INT ? "%." : "%3"));
-      output_asm_insn (buffer, operands);
-    }
-
-  else
-    fatal_insn ("d30v_cond_move", insn);
-
-  return "";
-}
-
-
-/* In rare cases, correct code generation requires extra machine dependent
-   processing between the second jump optimization pass and delayed branch
-   scheduling.  On those machines, define this macro as a C statement to act on
-   the code starting at INSN.  */
-
-void
-d30v_machine_dependent_reorg (insn)
-     rtx insn;
-{
-}
-
-
-/* A C statement (sans semicolon) to update the integer variable COST based on
-   the relationship between INSN that is dependent on DEP_INSN through the
-   dependence LINK.  The default is to make no adjustment to COST.  This can be
-   used for example to specify to the scheduler that an output- or
-   anti-dependence does not incur the same cost as a data-dependence.  */
-
-/* For the d30v, try to insure that the source operands for a load/store are
-   set 2 cycles before the memory reference.  */
-
-int
-d30v_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
-{
-  rtx set_dep = single_set (dep_insn);
-  rtx set_insn = single_set (insn);
-
-  if (set_dep != NULL_RTX && set_insn != NULL_RTX
-      && GET_CODE (SET_DEST (set_dep)) == REG)
-    {
-      rtx reg = SET_DEST (set_dep);
-      rtx mem;
-
-      if ((GET_CODE (mem = SET_SRC (set_insn)) == MEM
-	   && reg_mentioned_p (reg, XEXP (mem, 0)))
-	  || (GET_CODE (mem = SET_DEST (set_insn)) == MEM
-	      && reg_mentioned_p (reg, XEXP (mem, 0))))
-	{
-	  return cost + ((HAIFA_P) ? 2 : 4);
-	}
-    }
-
-  return cost;
-}
-
-
-/* Functions to save and restore d30v_return_addr_rtx.  */
-
-struct machine_function
-{
-  rtx ra_rtx;
-};
-
-static void
-d30v_save_machine_status (p)
-     struct function *p;
-{
-  struct machine_function *machine =
-    (struct machine_function *) xmalloc (sizeof (struct machine_function));
-
-  p->machine = machine;
-  machine->ra_rtx = d30v_return_addr_rtx;
-}
-
-static void
-d30v_restore_machine_status (p)
-     struct function *p;
-{
-  struct machine_function *machine = p->machine;
-
-  d30v_return_addr_rtx = machine->ra_rtx;
-
-  free (machine);
-  p->machine = (struct machine_function *)0;
-}
-
-/* Do anything needed before RTL is emitted for each function.  */
-
-void
-d30v_init_expanders ()
-{
-  d30v_return_addr_rtx = NULL_RTX;
-  d30v_eh_epilogue_sp_ofs = NULL_RTX;
-
-  /* Arrange to save and restore machine status around nested functions.  */
-  save_machine_status = d30v_save_machine_status;
-  restore_machine_status = d30v_restore_machine_status;
-}
-
-/* Find the current function's return address.
-
-   ??? It would be better to arrange things such that if we would ordinarily
-   have been a leaf function and we didn't spill the hard reg that we
-   wouldn't have to save the register in the prolog.  But it's not clear
-   how to get the right information at the right time.  */
-
-rtx
-d30v_return_addr ()
-{
-  rtx ret;
-
-  if ((ret = d30v_return_addr_rtx) == NULL)
-    {
-      rtx init;
-
-      d30v_return_addr_rtx = ret = gen_reg_rtx (Pmode);
-
-      init = gen_rtx (SET, VOIDmode, ret, gen_rtx (REG, Pmode, GPR_LINK));
-      push_topmost_sequence ();
-      emit_insn_after (init, get_insns ());
-      pop_topmost_sequence ();
-    }
-
-  return ret;
-}
-
-/* END CYGNUS LOCAL -- meissner/d30v */
diff --git a/gcc/config/d30v/d30v.h b/gcc/config/d30v/d30v.h
deleted file mode 100755
index af55b04..0000000
--- a/gcc/config/d30v/d30v.h
+++ /dev/null
@@ -1,6245 +0,0 @@
-/* CYGNUS LOCAL -- meissner/d30v */
-/* Definitions of target machine for use as an example.
-   Hack to fit.
-   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Solutions.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* D30V specific macros */
-
-/* Align an address */
-#define D30V_ALIGN(addr,align) (((addr) + (align) - 1) & ~((align) - 1))
-
-
-/* Set up System V.4 (aka ELF) defaults.  */
-#include "svr4.h"
-
-/* Set up System V.3 (aka COFF) defaults.  */
-/* #include "svr3.h" */
-
-/* Set up a.out defaults.  */
-/* #include "aoutos.h" */
-
-/* Set up GNU defaults for the Hurd.  */
-/* #include "gnu.h" */
-
-/* Set up Linux defaults.  */
-/* #include "linux.h" */
-
-/* Set up Netbsd defaults.  */
-/* #include "netbsd.h" */
-
-
-
-/* Driver configuration */
-
-/* A C expression which determines whether the option `-CHAR' takes arguments.
-   The value should be the number of arguments that option takes-zero, for many
-   options.
-
-   By default, this macro is defined to handle the standard options properly.
-   You need not define it unless you wish to add additional options which take
-   arguments.
-
-   Defined in svr4.h.  */
-/* #define SWITCH_TAKES_ARG(CHAR) */
-
-/* A C expression which determines whether the option `-NAME' takes arguments.
-   The value should be the number of arguments that option takes-zero, for many
-   options.  This macro rather than `SWITCH_TAKES_ARG' is used for
-   multi-character option names.
-
-   By default, this macro is defined as `DEFAULT_WORD_SWITCH_TAKES_ARG', which
-   handles the standard options properly.  You need not define
-   `WORD_SWITCH_TAKES_ARG' unless you wish to add additional options which take
-   arguments.  Any redefinition should call `DEFAULT_WORD_SWITCH_TAKES_ARG' and
-   then check for additional options.
-
-   Defined in svr4.h.  */
-/* #define WORD_SWITCH_TAKES_ARG(NAME) */
-
-/* A string-valued C expression which is nonempty if the linker needs a space
-   between the `-L' or `-o' option and its argument.
-
-   If this macro is not defined, the default value is 0.  */
-/* #define SWITCHES_NEED_SPACES "" */
-
-/* A C string constant that tells the GNU CC driver program options to pass to
-   CPP.  It can also specify how to translate options you give to GNU CC into
-   options for GNU CC to pass to the CPP.
-
-   Do not define this macro if it does not need to do anything.  */
-/* #define CPP_SPEC "" */
-
-/* If this macro is defined, the preprocessor will not define the builtin macro
-   `__SIZE_TYPE__'.  The macro `__SIZE_TYPE__' must then be defined by
-   `CPP_SPEC' instead.
-
-   This should be defined if `SIZE_TYPE' depends on target dependent flags
-   which are not accessible to the preprocessor.  Otherwise, it should not be
-   defined.  */
-/* #define NO_BUILTIN_SIZE_TYPE */
-
-/* If this macro is defined, the preprocessor will not define the builtin macro
-   `__PTRDIFF_TYPE__'.  The macro `__PTRDIFF_TYPE__' must then be defined by
-   `CPP_SPEC' instead.
-
-   This should be defined if `PTRDIFF_TYPE' depends on target dependent flags
-   which are not accessible to the preprocessor.  Otherwise, it should not be
-   defined.  */
-/* #define NO_BUILTIN_PTRDIFF_TYPE */
-
-/* A C string constant that tells the GNU CC driver program options to pass to
-   CPP.  By default, this macro is defined to pass the option
-   `-D__CHAR_UNSIGNED__' to CPP if `char' will be treated as `unsigned char' by
-   `cc1'.
-
-   Do not define this macro unless you need to override the default definition.  */
-/* #if DEFAULT_SIGNED_CHAR
-   #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
-   #else
-   #define SIGNED_CHAR_SPEC "%{!fsigned-char:-D__CHAR_UNSIGNED__}"
-   #endif */
-
-/* A C string constant that tells the GNU CC driver program options to pass to
-   `cc1'.  It can also specify how to translate options you give to GNU CC into
-   options for GNU CC to pass to the `cc1'.
-
-   Do not define this macro if it does not need to do anything.  */
-/* #define CC1_SPEC "" */
-
-/* A C string constant that tells the GNU CC driver program options to pass to
-   `cc1plus'.  It can also specify how to translate options you give to GNU CC
-   into options for GNU CC to pass to the `cc1plus'.
-
-   Do not define this macro if it does not need to do anything.  */
-/* #define CC1PLUS_SPEC "" */
-
-/* A C string constant that tells the GNU CC driver program options to pass to
-   the assembler.  It can also specify how to translate options you give to GNU
-   CC into options for GNU CC to pass to the assembler.  See the file `sun3.h'
-   for an example of this.
-
-   Do not define this macro if it does not need to do anything.
-
-   Defined in svr4.h.  */
-#undef	ASM_SPEC
-#define ASM_SPEC "\
-%{!mno-asm-optimize: %{O*: %{!O0: -O} %{O0: %{masm-optimize: -O}}}} \
-%{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*}"
-
-/* A C string constant that tells the GNU CC driver program how to run any
-   programs which cleanup after the normal assembler.  Normally, this is not
-   needed.  See the file `mips.h' for an example of this.
-
-   Do not define this macro if it does not need to do anything.
-
-   Defined in svr4.h.  */
-/* #define ASM_FINAL_SPEC "" */
-
-/* A C string constant that tells the GNU CC driver program options to pass to
-   the linker.  It can also specify how to translate options you give to GNU CC
-   into options for GNU CC to pass to the linker.
-
-   Do not define this macro if it does not need to do anything.
-
-   Defined in svr4.h.  */
-#undef	LINK_SPEC
-#define LINK_SPEC "\
-%{h*} %{v:-V} \
-%{b} %{Wl,*:%*} \
-%{static:-dn -Bstatic} \
-%{shared:-G -dy -z text} \
-%{symbolic:-Bsymbolic -G -dy -z text} \
-%{G:-G} \
-%{YP,*} \
-%{Qy:} %{!Qn:-Qy} \
-%{mextmem: -m d30v_e} %{mextmemory: -m d30v_e} %{monchip: -m d30v_o}"
-
-/* Another C string constant used much like `LINK_SPEC'.  The difference
-   between the two is that `LIB_SPEC' is used at the end of the command given
-   to the linker.
-
-   If this macro is not defined, a default is provided that loads the standard
-   C library from the usual place.  See `gcc.c'.
-
-   Defined in svr4.h.  */
-#undef	LIB_SPEC
-#define LIB_SPEC "--start-group -lsim -lc --end-group"
-
-/* Another C string constant that tells the GNU CC driver program how and when
-   to place a reference to `libgcc.a' into the linker command line.  This
-   constant is placed both before and after the value of `LIB_SPEC'.
-
-   If this macro is not defined, the GNU CC driver provides a default that
-   passes the string `-lgcc' to the linker unless the `-shared' option is
-   specified.  */
-/* #define LIBGCC_SPEC "" */
-
-/* Another C string constant used much like `LINK_SPEC'.  The difference
-   between the two is that `STARTFILE_SPEC' is used at the very beginning of
-   the command given to the linker.
-
-   If this macro is not defined, a default is provided that loads the standard
-   C startup file from the usual place.  See `gcc.c'.
-
-   Defined in svr4.h.  */
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC "crt0%O%s crtbegin%O%s"
-
-/* Another C string constant used much like `LINK_SPEC'.  The difference
-   between the two is that `ENDFILE_SPEC' is used at the very end of the
-   command given to the linker.
-
-   Do not define this macro if it does not need to do anything.
-
-   Defined in svr4.h.  */
-
-#undef	ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend%O%s"
-
-/* Define this macro if the driver program should find the library `libgcc.a'
-   itself and should not pass `-L' options to the linker.  If you do not define
-   this macro, the driver program will pass the argument `-lgcc' to tell the
-   linker to do the search and will pass `-L' options to it.  */
-/* #define LINK_LIBGCC_SPECIAL */
-
-/* Define this macro if the driver program should find the library `libgcc.a'.
-   If you do not define this macro, the driver program will pass the argument
-   `-lgcc' to tell the linker to do the search.  This macro is similar to
-   `LINK_LIBGCC_SPECIAL', except that it does not affect `-L' options.  */
-/* #define LINK_LIBGCC_SPECIAL_1 */
-
-/* Define this macro to provide additional specifications to put in the `specs'
-   file that can be used in various specifications like `CC1_SPEC'.
-
-   The definition should be an initializer for an array of structures,
-   containing a string constant, that defines the specification name, and a
-   string constant that provides the specification.
-
-   Do not define this macro if it does not need to do anything.  */
-/* #define EXTRA_SPECS {{}} */
-
-/* Define this macro as a C expression for the initializer of an array of
-   string to tell the driver program which options are defaults for this target
-   and thus do not need to be handled specially when using `MULTILIB_OPTIONS'.
-
-   Do not define this macro if `MULTILIB_OPTIONS' is not defined in the target
-   makefile fragment or if none of the options listed in `MULTILIB_OPTIONS' are
-   set by default.  *Note Target Fragment::.  */
-/* #define MULTILIB_DEFAULTS {} */
-
-/* Define this macro to tell `gcc' that it should only translate a `-B' prefix
-   into a `-L' linker option if the prefix indicates an absolute file name. */
-/* #define RELATIVE_PREFIX_NOT_LINKDIR */
-
-/* Define this macro as a C string constant if you wish to override the
-   standard choice of `/usr/local/lib/gcc-lib/' as the default prefix to try
-   when searching for the executable files of the compiler. */
-/* #define STANDARD_EXEC_PREFIX "" */
-
-/* If defined, this macro is an additional prefix to try after
-   `STANDARD_EXEC_PREFIX'.  `MD_EXEC_PREFIX' is not searched when the `-b'
-   option is used, or the compiler is built as a cross compiler.
-
-   Defined in svr4.h for host compilers.  */
-/* #define MD_EXEC_PREFIX "" */
-
-/* Define this macro as a C string constant if you wish to override the
-   standard choice of `/usr/local/lib/' as the default prefix to try when
-   searching for startup files such as `crt0.o'. */
-/* #define STANDARD_STARTFILE_PREFIX "" */
-
-/* If defined, this macro supplies an additional prefix to try after the
-   standard prefixes.  `MD_EXEC_PREFIX' is not searched when the `-b' option is
-   used, or when the compiler is built as a cross compiler.
-
-   Defined in svr4.h for host compilers.  */
-/* #define MD_STARTFILE_PREFIX "" */
-
-/* If defined, this macro supplies yet another prefix to try after the standard
-   prefixes.  It is not searched when the `-b' option is used, or when the
-   compiler is built as a cross compiler. */
-/* #define MD_STARTFILE_PREFIX_1 "" */
-
-/* Define this macro as a C string constant if you with to set environment
-   variables for programs called by the driver, such as the assembler and
-   loader.  The driver passes the value of this macro to `putenv' to initialize
-   the necessary environment variables. */
-/* #define INIT_ENVIRONMENT "" */
-
-/* Define this macro as a C string constant if you wish to override the
-   standard choice of `/usr/local/include' as the default prefix to try when
-   searching for local header files.  `LOCAL_INCLUDE_DIR' comes before
-   `SYSTEM_INCLUDE_DIR' in the search order.
-
-   Cross compilers do not use this macro and do not search either
-   `/usr/local/include' or its replacement.  */
-/* #define LOCAL_INCLUDE_DIR "" */
-
-/* Define this macro as a C string constant if you wish to specify a
-   system-specific directory to search for header files before the standard
-   directory.  `SYSTEM_INCLUDE_DIR' comes before `STANDARD_INCLUDE_DIR' in the
-   search order.
-
-   Cross compilers do not use this macro and do not search the directory
-   specified. */
-/* #define SYSTEM_INCLUDE_DIR "" */
-
-/* Define this macro as a C string constant if you wish to override the
-   standard choice of `/usr/include' as the default prefix to try when
-   searching for header files.
-
-   Cross compilers do not use this macro and do not search either
-   `/usr/include' or its replacement. */
-/* #define STANDARD_INCLUDE_DIR "" */
-
-/* Define this macro if you wish to override the entire default search path for
-   include files.  The default search path includes `GCC_INCLUDE_DIR',
-   `LOCAL_INCLUDE_DIR', `SYSTEM_INCLUDE_DIR', `GPLUSPLUS_INCLUDE_DIR', and
-   `STANDARD_INCLUDE_DIR'.  In addition, `GPLUSPLUS_INCLUDE_DIR' and
-   `GCC_INCLUDE_DIR' are defined automatically by `Makefile', and specify
-   private search areas for GCC.  The directory `GPLUSPLUS_INCLUDE_DIR' is used
-   only for C++ programs.
-
-     The definition should be an initializer for an array of structures.  Each
-     array element should have two elements: the directory name (a string
-     constant) and a flag for C++-only directories.  Mark the end of the array
-     with a null element.  For example, here is the definition used for VMS:
-
-          #define INCLUDE_DEFAULTS \
-          {                                       \
-            { "GNU_GXX_INCLUDE:", 1},             \
-            { "GNU_CC_INCLUDE:", 0},              \
-            { "SYS$SYSROOT:[SYSLIB.]", 0},        \
-            { ".", 0},                            \
-            { 0, 0}                               \
-          }
-
-   Here is the order of prefixes tried for exec files:
-
-  1. Any prefixes specified by the user with `-B'.
-
-  2. The environment variable `GCC_EXEC_PREFIX', if any.
-
-  3. The directories specified by the environment variable
-     `COMPILER_PATH'.
-
-  4. The macro `STANDARD_EXEC_PREFIX'.
-
-  5. `/usr/lib/gcc/'.
-
-  6. The macro `MD_EXEC_PREFIX', if any.
-
-   Here is the order of prefixes tried for startfiles:
-
-  1. Any prefixes specified by the user with `-B'.
-
-  2. The environment variable `GCC_EXEC_PREFIX', if any.
-
-  3. The directories specified by the environment variable
-     `LIBRARY_PATH' (native only, cross compilers do not use this).
-
-  4. The macro `STANDARD_EXEC_PREFIX'.
-
-  5. `/usr/lib/gcc/'.
-
-  6. The macro `MD_EXEC_PREFIX', if any.
-
-  7. The macro `MD_STARTFILE_PREFIX', if any.
-
-  8. The macro `STANDARD_STARTFILE_PREFIX'.
-
-  9. `/lib/'.
-
- 10. `/usr/lib/'.  */
-/* #define INCLUDE_DEFAULTS {{ }} */
-
-
-/* Run-time target specifications */
-
-/* Define this to be a string constant containing `-D' options to define the
-   predefined macros that identify this machine and system.  These macros will
-   be predefined unless the `-ansi' option is specified.
-
-   In addition, a parallel set of macros are predefined, whose names are made
-   by appending `__' at the beginning and at the end.  These `__' macros are
-   permitted by the ANSI standard, so they are predefined regardless of whether
-   `-ansi' is specified.
-
-   For example, on the Sun, one can use the following value:
-
-        "-Dmc68000 -Dsun -Dunix"
-
-   The result is to define the macros `__mc68000__', `__sun__' and `__unix__'
-   unconditionally, and the macros `mc68000', `sun' and `unix' provided `-ansi'
-   is not specified.  */
-#define CPP_PREDEFINES "-D__D30V__ -Amachine(d30v)"
-
-/* This declaration should be present.  */
-extern int target_flags;
-
-/* This series of macros is to allow compiler command arguments to enable or
-   disable the use of optional features of the target machine.  For example,
-   one machine description serves both the 68000 and the 68020; a command
-   argument tells the compiler whether it should use 68020-only instructions or
-   not.  This command argument works by means of a macro `TARGET_68020' that
-   tests a bit in `target_flags'.
-
-   Define a macro `TARGET_FEATURENAME' for each such option.  Its definition
-   should test a bit in `target_flags'; for example:
-
-        #define TARGET_68020 (target_flags & 1)
-
-   One place where these macros are used is in the condition-expressions of
-   instruction patterns.  Note how `TARGET_68020' appears frequently in the
-   68000 machine description file, `m68k.md'.  Another place they are used is
-   in the definitions of the other macros in the `MACHINE.h' file.  */
-
-#define MASK_NO_COND_MOVE	0x00000001	/* disable conditional moves */
-
-#define MASK_DEBUG_ARG		0x10000000	/* debug argument handling */
-#define MASK_DEBUG_STACK	0x20000000	/* debug stack allocations */
-#define MASK_DEBUG_ADDR		0x40000000	/* debug GO_IF_LEGITIMATE_ADDRESS */
-
-#define TARGET_NO_COND_MOVE	(target_flags & MASK_NO_COND_MOVE)
-#define TARGET_DEBUG_ARG	(target_flags & MASK_DEBUG_ARG)
-#define TARGET_DEBUG_STACK	(target_flags & MASK_DEBUG_STACK)
-#define TARGET_DEBUG_ADDR	(target_flags & MASK_DEBUG_ADDR)
-
-#define TARGET_COND_MOVE	(! TARGET_NO_COND_MOVE)
-
-/* Default switches used.  */
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 0
-#endif
-
-/* This macro defines names of command options to set and clear bits in
-   `target_flags'.  Its definition is an initializer with a subgrouping for
-   each command option.
-
-   Each subgrouping contains a string constant, that defines the option name,
-   and a number, which contains the bits to set in `target_flags'.  A negative
-   number says to clear bits instead; the negative of the number is which bits
-   to clear.  The actual option name is made by appending `-m' to the specified
-   name.
-
-   One of the subgroupings should have a null string.  The number in this
-   grouping is the default value for `target_flags'.  Any target options act
-   starting with that value.
-
-   Here is an example which defines `-m68000' and `-m68020' with opposite
-   meanings, and picks the latter as the default:
-
-        #define TARGET_SWITCHES \
-          { { "68020", 1},      \
-            { "68000", -1},     \
-            { "", 1}}  */
-
-#define TARGET_SWITCHES							\
-{									\
-  { "cond-move",	-MASK_NO_COND_MOVE },				\
-  { "no-cond-move",	 MASK_NO_COND_MOVE },				\
-  { "debug-arg",	 MASK_DEBUG_ARG },				\
-  { "debug-stack",	 MASK_DEBUG_STACK }, 				\
-  { "debug-addr",	 MASK_DEBUG_ADDR },				\
-  { "asm-optimize",	 0 },						\
-  { "no-asm-optimize",	 0 },						\
-  { "extmem",		 0 },						\
-  { "extmemory",	 0 },						\
-  { "onchip",		 0 },						\
-  { "",			 TARGET_DEFAULT },				\
-}
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of command
-   options that have values.  Its definition is an initializer with a
-   subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the fixed part of
-   the option name, and the address of a variable.  The variable, type `char
-   *', is set to the variable part of the given option if the fixed part
-   matches.  The actual option name is made by appending `-m' to the specified
-   name.
-
-   Here is an example which defines `-mshort-data-NUMBER'.  If the given option
-   is `-mshort-data-512', the variable `m88k_short_data' will be set to the
-   string `"512"'.
-
-        extern char *m88k_short_data;
-        #define TARGET_OPTIONS \
-         { { "short-data-", &m88k_short_data } }  */
-
-#define TARGET_OPTIONS							\
-{									\
-   {"branch-cost=",  &d30v_branch_cost_string},				\
-   {"cond-exec=",    &d30v_cond_exec_string},				\
-}
-
-/* This macro is a C statement to print on `stderr' a string describing the
-   particular machine description choice.  Every machine description should
-   define `TARGET_VERSION'.  For example:
-
-        #ifdef MOTOROLA
-        #define TARGET_VERSION \
-          fprintf (stderr, " (68k, Motorola syntax)");
-        #else
-        #define TARGET_VERSION \
-          fprintf (stderr, " (68k, MIT syntax)");
-        #endif  */
-#define TARGET_VERSION fprintf (stderr, " d30v")
-
-/* Sometimes certain combinations of command options do not make sense on a
-   particular target machine.  You can define a macro `OVERRIDE_OPTIONS' to
-   take account of this.  This macro, if defined, is executed once just after
-   all the command options have been parsed.
-
-   Don't use this macro to turn on various extra optimizations for `-O'.  That
-   is what `OPTIMIZATION_OPTIONS' is for.  */
-
-#define OVERRIDE_OPTIONS override_options ()
-
-/* Some machines may desire to change what optimizations are performed for
-   various optimization levels.  This macro, if defined, is executed once just
-   after the optimization level is determined and before the remainder of the
-   command options have been parsed.  Values set in this macro are used as the
-   default values for the other command line options.
-
-   LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
-   `-O' is specified, and 0 if neither is specified.
-
-   SIZE is non-zero if `-Os' is specified, 0 otherwise.  
-
-   You should not use this macro to change options that are not
-   machine-specific.  These should uniformly selected by the same optimization
-   level on all supported machines.  Use this macro to enable machbine-specific
-   optimizations.
-
-   *Do not examine `write_symbols' in this macro!* The debugging options are
-   *not supposed to alter the generated code.  */
-/* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
-
-/* Define this macro if debugging can be performed even without a frame
-   pointer.  If this macro is defined, GNU CC will turn on the
-   `-fomit-frame-pointer' option whenever `-O' is specified.  */
-#define CAN_DEBUG_WITHOUT_FP
-
-
-/* Storage Layout */
-
-/* Define this macro to have the value 1 if the most significant bit in a byte
-   has the lowest number; otherwise define it to have the value zero.  This
-   means that bit-field instructions count from the most significant bit.  If
-   the machine has no bit-field instructions, then this must still be defined,
-   but it doesn't matter which value it is defined to.  This macro need not be
-   a constant.
-
-   This macro does not affect the way structure fields are packed into bytes or
-   words; that is controlled by `BYTES_BIG_ENDIAN'.  */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this macro to have the value 1 if the most significant byte in a word
-   has the lowest number.  This macro need not be a constant.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this macro to have the value 1 if, in a multiword object, the most
-   significant word has the lowest number.  This applies to both memory
-   locations and registers; GNU CC fundamentally assumes that the order of
-   words in memory is the same as the order in registers.  This macro need not
-   be a constant.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* Define this macro if WORDS_BIG_ENDIAN is not constant.  This must be a
-   constant value with the same meaning as WORDS_BIG_ENDIAN, which will be used
-   only when compiling libgcc2.c.  Typically the value will be set based on
-   preprocessor defines.  */
-/* #define LIBGCC2_WORDS_BIG_ENDIAN */
-
-/* Define this macro to have the value 1 if `DFmode', `XFmode' or `TFmode'
-   floating point numbers are stored in memory with the word containing the
-   sign bit at the lowest address; otherwise define it to have the value 0.
-   This macro need not be a constant.
-
-   You need not define this macro if the ordering is the same as for multi-word
-   integers.  */
-/* #define FLOAT_WORDS_BIG_EnNDIAN */
-
-/* Define this macro to be the number of bits in an addressable storage unit
-   (byte); normally 8.  */
-#define BITS_PER_UNIT 8
-
-/* Number of bits in a word; normally 32.  */
-#define BITS_PER_WORD 32
-
-/* Maximum number of bits in a word.  If this is undefined, the default is
-   `BITS_PER_WORD'.  Otherwise, it is the constant value that is the largest
-   value that `BITS_PER_WORD' can have at run-time.  */
-/* #define MAX_BITS_PER_WORD */
-
-/* Number of storage units in a word; normally 4.  */
-#define UNITS_PER_WORD 4
-
-/* Minimum number of units in a word.  If this is undefined, the default is
-   `UNITS_PER_WORD'.  Otherwise, it is the constant value that is the smallest
-   value that `UNITS_PER_WORD' can have at run-time.  */
-/* #define MIN_UNITS_PER_WORD */
-
-/* Width of a pointer, in bits.  You must specify a value no wider than the
-   width of `Pmode'.  If it is not equal to the width of `Pmode', you must
-   define `POINTERS_EXTEND_UNSIGNED'.  */
-#define POINTER_SIZE 32
-
-/* A C expression whose value is nonzero if pointers that need to be extended
-   from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and zero if
-   they are zero-extended.
-
-   You need not define this macro if the `POINTER_SIZE' is equal to the width
-   of `Pmode'.  */
-/* #define POINTERS_EXTEND_UNSIGNED */
-
-/* A macro to update M and UNSIGNEDP when an object whose type is TYPE and
-   which has the specified mode and signedness is to be stored in a register.
-   This macro is only called when TYPE is a scalar type.
-
-   On most RISC machines, which only have operations that operate on a full
-   register, define this macro to set M to `word_mode' if M is an integer mode
-   narrower than `BITS_PER_WORD'.  In most cases, only integer modes should be
-   widened because wider-precision floating-point operations are usually more
-   expensive than their narrower counterparts.
-
-   For most machines, the macro definition does not change UNSIGNEDP.  However,
-   some machines, have instructions that preferentially handle either signed or
-   unsigned quantities of certain modes.  For example, on the DEC Alpha, 32-bit
-   loads from memory and 32-bit add instructions sign-extend the result to 64
-   bits.  On such machines, set UNSIGNEDP according to which kind of extension
-   is more efficient.
-
-   Do not define this macro if it would never modify M.  */
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)				\
-do {									\
-  if (GET_MODE_CLASS (MODE) == MODE_INT					\
-      && GET_MODE_SIZE (MODE) < 4)					\
-    (MODE) = SImode;							\
-} while (0)
-
-/* Define this macro if the promotion described by `PROMOTE_MODE' should also
-   be done for outgoing function arguments.  */
-/* #define PROMOTE_FUNCTION_ARGS */
-
-/* Define this macro if the promotion described by `PROMOTE_MODE' should also
-   be done for the return value of functions.
-
-   If this macro is defined, `FUNCTION_VALUE' must perform the same promotions
-   done by `PROMOTE_MODE'.  */
-/* #define PROMOTE_FUNCTION_RETURN */
-
-/* Define this macro if the promotion described by `PROMOTE_MODE' should *only*
-   be performed for outgoing function arguments or function return values, as
-   specified by `PROMOTE_FUNCTION_ARGS' and `PROMOTE_FUNCTION_RETURN',
-   respectively.  */
-/* #define PROMOTE_FOR_CALL_ONLY */
-
-/* Normal alignment required for function parameters on the stack, in bits.
-   All stack parameters receive at least this much alignment regardless of data
-   type.  On most machines, this is the same as the size of an integer.  */
-
-#define PARM_BOUNDARY 32
-
-/* Define this macro if you wish to preserve a certain alignment for the stack
-   pointer.  The definition is a C expression for the desired alignment
-   (measured in bits).
-
-   If `PUSH_ROUNDING' is not defined, the stack will always be aligned to the
-   specified boundary.  If `PUSH_ROUNDING' is defined and specifies a less
-   strict alignment than `STACK_BOUNDARY', the stack may be momentarily
-   unaligned while pushing arguments.  */
-
-#define STACK_BOUNDARY 64
-
-/* Alignment required for a function entry point, in bits.  */
-
-#define FUNCTION_BOUNDARY 64
-
-/* Biggest alignment that any data type can require on this machine,
-   in bits.  */
-
-#define BIGGEST_ALIGNMENT 64
-
-/* Biggest alignment that any structure field can require on this machine, in
-   bits.  If defined, this overrides `BIGGEST_ALIGNMENT' for structure fields
-   only.  */
-/* #define BIGGEST_FIELD_ALIGNMENT */
-
-/* Biggest alignment supported by the object file format of this machine.  Use
-   this macro to limit the alignment which can be specified using the
-   `__attribute__ ((aligned (N)))' construct.  If not defined, the default
-   value is `BIGGEST_ALIGNMENT'.
-
-   Defined in svr4.h.  */
-/* #define MAX_OFILE_ALIGNMENT */
-
-/* If defined, a C expression to compute the alignment for a static variable.
-   TYPE is the data type, and BASIC-ALIGN is the alignment that the object
-   would ordinarily have.  The value of this macro is used instead of that
-   alignment to align the object.
-
-   If this macro is not defined, then BASIC-ALIGN is used.
-
-   One use of this macro is to increase alignment of medium-size data to make
-   it all fit in fewer cache lines.  Another is to cause character arrays to be
-   word-aligned so that `strcpy' calls that copy constants to character arrays
-   can be done inline.  */
-
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* If defined, a C expression to compute the alignment given to a constant that
-   is being placed in memory.  CONSTANT is the constant and BASIC-ALIGN is the
-   alignment that the object would ordinarily have.  The value of this macro is
-   used instead of that alignment to align the object.
-
-   If this macro is not defined, then BASIC-ALIGN is used.
-
-   The typical use of this macro is to increase alignment for string constants
-   to be word aligned so that `strcpy' calls that copy constants can be done
-   inline.  */
-
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  (TREE_CODE (EXP) == STRING_CST	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Alignment in bits to be given to a structure bit field that follows an empty
-   field such as `int : 0;'.
-
-   Note that `PCC_BITFIELD_TYPE_MATTERS' also affects the alignment that
-   results from an empty field.  */
-/* #define EMPTY_FIELD_BOUNDARY */
-
-/* Number of bits which any structure or union's size must be a multiple of.
-   Each structure or union's size is rounded up to a multiple of this.
-
-   If you do not define this macro, the default is the same as `BITS_PER_UNIT'.  */
-/* #define STRUCTURE_SIZE_BOUNDARY */
-
-/* Define this macro to be the value 1 if instructions will fail to work if
-   given data not on the nominal alignment.  If instructions will merely go
-   slower in that case, define this macro as 0.  */
-
-#define STRICT_ALIGNMENT 1
-
-/* Define this if you wish to imitate the way many other C compilers handle
-   alignment of bitfields and the structures that contain them.
-
-   The behavior is that the type written for a bitfield (`int', `short', or
-   other integer type) imposes an alignment for the entire structure, as if the
-   structure really did contain an ordinary field of that type.  In addition,
-   the bitfield is placed within the structure so that it would fit within such
-   a field, not crossing a boundary for it.
-
-   Thus, on most machines, a bitfield whose type is written as `int' would not
-   cross a four-byte boundary, and would force four-byte alignment for the
-   whole structure.  (The alignment used may not be four bytes; it is
-   controlled by the other alignment parameters.)
-
-   If the macro is defined, its definition should be a C expression; a nonzero
-   value for the expression enables this behavior.
-
-   Note that if this macro is not defined, or its value is zero, some bitfields
-   may cross more than one alignment boundary.  The compiler can support such
-   references if there are `insv', `extv', and `extzv' insns that can directly
-   reference memory.
-
-   The other known way of making bitfields work is to define
-   `STRUCTURE_SIZE_BOUNDARY' as large as `BIGGEST_ALIGNMENT'.  Then every
-   structure can be accessed with fullwords.
-
-   Unless the machine has bitfield instructions or you define
-   `STRUCTURE_SIZE_BOUNDARY' that way, you must define
-   `PCC_BITFIELD_TYPE_MATTERS' to have a nonzero value.
-
-   If your aim is to make GNU CC use the same conventions for laying out
-   bitfields as are used by another compiler, here is how to investigate what
-   the other compiler does.  Compile and run this program:
-
-        struct foo1
-        {
-          char x;
-          char :0;
-          char y;
-        };
-
-        struct foo2
-        {
-          char x;
-          int :0;
-          char y;
-        };
-
-        main ()
-        {
-          printf ("Size of foo1 is %d\n",
-                  sizeof (struct foo1));
-          printf ("Size of foo2 is %d\n",
-                  sizeof (struct foo2));
-          exit (0);
-        }
-
-   If this prints 2 and 5, then the compiler's behavior is what you would get
-   from `PCC_BITFIELD_TYPE_MATTERS'.
-
-   Defined in svr4.h.  */
-
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Like PCC_BITFIELD_TYPE_MATTERS except that its effect is limited to aligning
-   a bitfield within the structure.  */
-/* #define BITFIELD_NBYTES_LIMITED */
-
-/* Define this macro as an expression for the overall size of a structure
-   (given by STRUCT as a tree node) when the size computed from the fields is
-   SIZE and the alignment is ALIGN.
-
-   The default is to round SIZE up to a multiple of ALIGN.  */
-/* #define ROUND_TYPE_SIZE(STRUCT, SIZE, ALIGN) */
-
-/* Define this macro as an expression for the alignment of a structure (given
-   by STRUCT as a tree node) if the alignment computed in the usual way is
-   COMPUTED and the alignment explicitly specified was SPECIFIED.
-
-   The default is to use SPECIFIED if it is larger; otherwise, use the smaller
-   of COMPUTED and `BIGGEST_ALIGNMENT' */
-/* #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) */
-
-/* An integer expression for the size in bits of the largest integer machine
-   mode that should actually be used.  All integer machine modes of this size
-   or smaller can be used for structures and unions with the appropriate sizes.
-   If this macro is undefined, `GET_MODE_BITSIZE (DImode)' is assumed.  */
-/* #define MAX_FIXED_MODE_SIZE */
-
-/* A C statement to validate the value VALUE (of type `double') for mode MODE.
-   This means that you check whether VALUE fits within the possible range of
-   values for mode MODE on this target machine.  The mode MODE is always a mode
-   of class `MODE_FLOAT'.  OVERFLOW is nonzero if the value is already known to
-   be out of range.
-
-   If VALUE is not valid or if OVERFLOW is nonzero, you should set OVERFLOW to
-   1 and then assign some valid value to VALUE.  Allowing an invalid value to
-   go through the compiler can produce incorrect assembler code which may even
-   cause Unix assemblers to crash.
-
-   This macro need not be defined if there is no work for it to do.  */
-/* #define CHECK_FLOAT_VALUE(MODE, VALUE, OVERFLOW) */
-
-/* A code distinguishing the floating point format of the target machine.
-   There are three defined values:
-
-   IEEE_FLOAT_FORMAT'
-        This code indicates IEEE floating point.  It is the default;
-        there is no need to define this macro when the format is IEEE.
-
-   VAX_FLOAT_FORMAT'
-        This code indicates the peculiar format used on the Vax.
-
-   UNKNOWN_FLOAT_FORMAT'
-        This code indicates any other format.
-
-   The value of this macro is compared with `HOST_FLOAT_FORMAT' (*note
-   Config::.) to determine whether the target machine has the same format as
-   the host machine.  If any other formats are actually in use on supported
-   machines, new codes should be defined for them.
-
-   The ordering of the component words of floating point values stored in
-   memory is controlled by `FLOAT_WORDS_BIG_ENDIAN' for the target machine and
-   `HOST_FLOAT_WORDS_BIG_ENDIAN' for the host.  */
-#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
-
-/* GNU CC supports two ways of implementing C++ vtables: traditional or with
-   so-called "thunks".  The flag `-fvtable-thunk' chooses between them.  Define
-   this macro to be a C expression for the default value of that flag.  If
-   `DEFAULT_VTABLE_THUNKS' is 0, GNU CC uses the traditional implementation by
-   default.  The "thunk" implementation is more efficient (especially if you
-   have provided an implementation of `ASM_OUTPUT_MI_THUNK', see *Note Function
-   Entry::), but is not binary compatible with code compiled using the
-   traditional implementation.  If you are writing a new ports, define
-   `DEFAULT_VTABLE_THUNKS' to 1.
-
-   If you do not define this macro, the default for `-fvtable-thunk' is 0.  */
-#define DEFAULT_VTABLE_THUNKS 1
-
-
-/* Layout of Source Language Data Types */
-
-/* A C expression for the size in bits of the type `int' on the target machine.
-   If you don't define this, the default is one word.  */
-#define INT_TYPE_SIZE 32
-
-/* Maximum number for the size in bits of the type `int' on the target machine.
-   If this is undefined, the default is `INT_TYPE_SIZE'.  Otherwise, it is the
-   constant value that is the largest value that `INT_TYPE_SIZE' can have at
-   run-time.  This is used in `cpp'.  */
-/* #define MAX_INT_TYPE_SIZE */
-
-/* A C expression for the size in bits of the type `short' on the target
-   machine.  If you don't define this, the default is half a word.  (If this
-   would be less than one storage unit, it is rounded up to one unit.)  */
-#define SHORT_TYPE_SIZE 16
-
-/* A C expression for the size in bits of the type `long' on the target
-   machine.  If you don't define this, the default is one word.  */
-#define LONG_TYPE_SIZE 32
-
-/* Maximum number for the size in bits of the type `long' on the target
-   machine.  If this is undefined, the default is `LONG_TYPE_SIZE'.  Otherwise,
-   it is the constant value that is the largest value that `LONG_TYPE_SIZE' can
-   have at run-time.  This is used in `cpp'.  */
-/* #define MAX_LONG_TYPE_SIZE */
-
-/* A C expression for the size in bits of the type `long long' on the target
-   machine.  If you don't define this, the default is two words.  If you want
-   to support GNU Ada on your machine, the value of macro must be at least 64.  */
-#define LONG_LONG_TYPE_SIZE 64
-
-/* A C expression for the size in bits of the type `char' on the target
-   machine.  If you don't define this, the default is one quarter of a word.
-   (If this would be less than one storage unit, it is rounded up to one unit.)  */
-#define CHAR_TYPE_SIZE 8
-
-/* Maximum number for the size in bits of the type `char' on the target
-   machine.  If this is undefined, the default is `CHAR_TYPE_SIZE'.  Otherwise,
-   it is the constant value that is the largest value that `CHAR_TYPE_SIZE' can
-   have at run-time.  This is used in `cpp'.  */
-/* #define MAX_CHAR_TYPE_SIZE */
-
-/* A C expression for the size in bits of the type `float' on the target
-   machine.  If you don't define this, the default is one word.  */
-#define FLOAT_TYPE_SIZE 32
-
-/* A C expression for the size in bits of the type `double' on the target
-   machine.  If you don't define this, the default is two words.  */
-#define DOUBLE_TYPE_SIZE 64
-
-/* A C expression for the size in bits of the type `long double' on the target
-   machine.  If you don't define this, the default is two words.  */
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* An expression whose value is 1 or 0, according to whether the type `char'
-   should be signed or unsigned by default.  The user can always override this
-   default with the options `-fsigned-char' and `-funsigned-char'.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* A C expression to determine whether to give an `enum' type only as many
-   bytes as it takes to represent the range of possible values of that type.  A
-   nonzero value means to do that; a zero value means all `enum' types should
-   be allocated like `int'.
-
-   If you don't define the macro, the default is 0.  */
-/* #define DEFAULT_SHORT_ENUMS */
-
-/* A C expression for a string describing the name of the data type to use for
-   size values.  The typedef name `size_t' is defined using the contents of the
-   string.
-
-   The string can contain more than one keyword.  If so, separate them with
-   spaces, and write first any length keyword, then `unsigned' if appropriate,
-   and finally `int'.  The string must exactly match one of the data type names
-   defined in the function `init_decl_processing' in the file `c-decl.c'.  You
-   may not omit `int' or change the order--that would cause the compiler to
-   crash on startup.
-
-   If you don't define this macro, the default is `"long unsigned int"'.
-
-   Defined in svr4.h.  */
-/* #define SIZE_TYPE */
-
-/* A C expression for a string describing the name of the data type to use for
-   the result of subtracting two pointers.  The typedef name `ptrdiff_t' is
-   defined using the contents of the string.  See `SIZE_TYPE' above for more
-   information.
-
-   If you don't define this macro, the default is `"long int"'.
-
-   Defined in svr4.h.  */
-/* #define PTRDIFF_TYPE */
-
-/* A C expression for a string describing the name of the data type to use for
-   wide characters.  The typedef name `wchar_t' is defined using the contents
-   of the string.  See `SIZE_TYPE' above for more information.
-
-   If you don't define this macro, the default is `"int"'.
-
-   Defined in svr4.h.  */
-/* #define WCHAR_TYPE */
-
-/* A C expression for the size in bits of the data type for wide characters.
-   This is used in `cpp', which cannot make use of `WCHAR_TYPE'.
-
-   Defined in svr4.h.  */
-/* #define WCHAR_TYPE_SIZE */
-
-/* Maximum number for the size in bits of the data type for wide characters.
-   If this is undefined, the default is `WCHAR_TYPE_SIZE'.  Otherwise, it is
-   the constant value that is the largest value that `WCHAR_TYPE_SIZE' can have
-   at run-time.  This is used in `cpp'.  */
-/* #define MAX_WCHAR_TYPE_SIZE */
-
-/* Define this macro if the type of Objective C selectors should be `int'.
-
-   If this macro is not defined, then selectors should have the type `struct
-   objc_selector *'.  */
-/* #define OBJC_INT_SELECTORS */
-
-/* Define this macro if the compiler can group all the selectors together into
-   a vector and use just one label at the beginning of the vector.  Otherwise,
-   the compiler must give each selector its own assembler label.
-
-   On certain machines, it is important to have a separate label for each
-   selector because this enables the linker to eliminate duplicate selectors.  */
-/* #define OBJC_SELECTORS_WITHOUT_LABELS */
-
-/* A C constant expression for the integer value for escape sequence
-   `\a'.  */
-#define TARGET_BELL 0x7
-
-/* C constant expressions for the integer values for escape sequences
-   `\b', `\t' and `\n'.  */
-#define TARGET_BS	0x8
-#define TARGET_TAB	0x9
-#define TARGET_NEWLINE	0xa
-
-/* C constant expressions for the integer values for escape sequences
-   `\v', `\f' and `\r'.  */
-#define TARGET_VT	0xb
-#define TARGET_FF	0xc
-#define TARGET_CR	0xd
-
-
-/* D30V register layout.  */
-
-/* Return true if a value is inside a range */
-#define IN_RANGE_P(VALUE, LOW, HIGH) \
-  (((unsigned)((VALUE) - (LOW))) <= ((unsigned)((HIGH) - (LOW))))
-
-/* General purpose registers.  */
-#define GPR_FIRST	0			/* First gpr */
-#define GPR_LAST	(GPR_FIRST + 63)	/* Last gpr */
-#define GPR_R0		GPR_FIRST		/* R0, constant 0 */
-#define GPR_ARG_FIRST	(GPR_FIRST + 2)		/* R2, first argument reg */
-#define GPR_ARG_LAST	(GPR_FIRST + 17)	/* R17, last argument reg */
-#define GPR_RET_VALUE	GPR_ARG_FIRST		/* R2, function return reg */
-#define GPR_ATMP_FIRST	(GPR_FIRST + 20)	/* R20, tmp to save accs */
-#define GPR_ATMP_LAST	(GPR_FIRST + 21)	/* R21, tmp to save accs */
-#define GPR_STACK_TMP	(GPR_FIRST + 22)	/* R22, tmp for saving stack */
-#define GPR_RES_FIRST	(GPR_FIRST + 32)	/* R32, first reserved reg */
-#define GPR_RES_LAST	(GPR_FIRST + 35)	/* R35, last reserved reg */
-#define GPR_FP		(GPR_FIRST + 61)	/* Frame pointer */
-#define GPR_LINK	(GPR_FIRST + 62)	/* Return address register */
-#define GPR_SP		(GPR_FIRST + 63)	/* Stack pointer */
-
-/* Argument register that is eliminated in favor of the frame and/or stack
-   pointer.  Also add register to point to where the return address is
-   stored.  */
-#define SPECIAL_REG_FIRST		(GPR_LAST + 1)
-#define SPECIAL_REG_LAST		(SPECIAL_REG_FIRST)
-#define ARG_POINTER_REGNUM		(SPECIAL_REG_FIRST + 0)
-#define SPECIAL_REG_P(R)		((R) == SPECIAL_REG_FIRST)
-
-#define GPR_OR_SPECIAL_REG_P(R)		IN_RANGE_P (R, GPR_FIRST, SPECIAL_REG_LAST)
-#define GPR_P(R)			IN_RANGE_P (R, GPR_FIRST, GPR_LAST)
-#define GPR_OR_PSEUDO_P(R)		(GPR_OR_SPECIAL_REG_P (R)	\
-					 || (R) >= FIRST_PSEUDO_REGISTER)
-
-/* Flag bits.  */
-#define FLAG_FIRST	(SPECIAL_REG_LAST + 1)	/* First flag */
-#define FLAG_LAST	(FLAG_FIRST + 7)	/* Last flag */
-#define FLAG_F0		(FLAG_FIRST)		/* F0, used in prediction */
-#define FLAG_F1		(FLAG_FIRST + 1)	/* F1, used in prediction */
-#define FLAG_F2		(FLAG_FIRST + 2)	/* F2, general flag */
-#define FLAG_F3		(FLAG_FIRST + 3)	/* F3, general flag */
-#define FLAG_SAT	(FLAG_FIRST + 4)	/* F4, saturation flag */
-#define FLAG_OVERFLOW	(FLAG_FIRST + 5)	/* F5, overflow flag */
-#define FLAG_ACC_OVER	(FLAG_FIRST + 6)	/* F6, accumulated overflow */
-#define FLAG_CARRY	(FLAG_FIRST + 7)	/* F7, carry/borrow flag */
-#define FLAG_BORROW	FLAG_CARRY
-
-#define FLAG_P(R)		IN_RANGE_P (R, FLAG_FIRST, FLAG_LAST)
-#define FLAG_OR_PSEUDO_P(R)	(FLAG_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
-
-#define BR_FLAG_P(R)		IN_RANGE_P (R, FLAG_F0, FLAG_F1)
-#define BR_FLAG_OR_PSEUDO_P(R)	(BR_FLAG_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
-
-/* Accumulators */
-#define ACCUM_FIRST	(FLAG_LAST + 1)		/* First accumulator */
-#define ACCUM_A0	ACCUM_FIRST		/* Register A0 */
-#define ACCUM_A1	(ACCUM_FIRST + 1)	/* Register A1 */
-#define ACCUM_LAST	(ACCUM_FIRST + 1)	/* Last accumulator */
-
-#define ACCUM_P(R)		IN_RANGE_P (R, ACCUM_FIRST, ACCUM_LAST)
-#define ACCUM_OR_PSEUDO_P(R)	(ACCUM_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
-
-/* Special registers.  Note, we only define the registers that can actually
-   be used.  */
-#define CR_FIRST	(ACCUM_LAST + 1)	/* First CR */
-#define CR_LAST		(CR_FIRST + 14)		/* Last CR */
-#define CR_PSW		(CR_FIRST + 0)		/* CR0, Program status word */
-#define CR_BPSW		(CR_FIRST + 1)		/* CR1, Backup PSW */
-#define CR_PC		(CR_FIRST + 2)		/* CR2, Program counter */
-#define CR_BPC		(CR_FIRST + 3)		/* CR3, Backup PC */
-#define CR_DPSW		(CR_FIRST + 4)		/* CR4, Debug PSW */
-#define CR_DPC		(CR_FIRST + 5)		/* CR5, Debug PC */
-#define CR_RPT_C	(CR_FIRST + 6)		/* CR7, loop count register */
-#define CR_RPT_S	(CR_FIRST + 7)		/* CR8, loop start address */
-#define CR_RPT_E	(CR_FIRST + 8)		/* CR9, loop end address */
-#define CR_MOD_S	(CR_FIRST + 9)		/* CR10, modulo address start*/
-#define CR_MOD_E	(CR_FIRST + 10)		/* CR11, modulo address */
-#define CR_IBA		(CR_FIRST + 11)		/* CR14, Interrupt break addr */
-#define CR_EIT_VB	(CR_FIRST + 12)		/* CR15, EIT vector address */
-#define CR_INT_S	(CR_FIRST + 13)		/* CR16, Interrupt status */
-#define CR_INT_M	(CR_FIRST + 14)		/* CR17, Interrupt mask */
-
-#define CR_P(R)			IN_RANGE_P (R, CR_FIRST, CR_LAST)
-#define CR_OR_PSEUDO_P(R)	(CR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
-
-
-/* Register Basics */
-
-/* Number of hardware registers known to the compiler.  They receive numbers 0
-   through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number
-   really is assigned the number `FIRST_PSEUDO_REGISTER'.  */
-#define FIRST_PSEUDO_REGISTER (CR_LAST + 1)
-
-/* An initializer that says which registers are used for fixed purposes all
-   throughout the compiled code and are therefore not available for general
-   allocation.  These would include the stack pointer, the frame pointer
-   (except on machines where that can be used as a general register when no
-   frame pointer is needed), the program counter on machines where that is
-   considered one of the addressable registers, and any other numbered register
-   with a standard use.
-
-   This information is expressed as a sequence of numbers, separated by commas
-   and surrounded by braces.  The Nth number is 1 if register N is fixed, 0
-   otherwise.
-
-   The table initialized from this macro, and the table initialized by the
-   following one, may be overridden at run time either automatically, by the
-   actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the
-   command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'.  */
-#define FIXED_REGISTERS							\
-{									\
-  1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  /* R0  - R15 */	\
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1,  /* R16 - R31 */	\
-  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  /* R32 - R47 */	\
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,  /* R48 - R63 */	\
-  1,						   /* ARG ptr */	\
-  0, 0, 0, 0, 1, 1, 1, 1,			   /* F0 - F7 */	\
-  0, 0,						   /* A0 - A1 */	\
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,	   /* CRs */		\
-}
-
-/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in
-   general) by function calls as well as for fixed registers.  This macro
-   therefore identifies the registers that are not available for general
-   allocation of values that must live across function calls.
-
-   If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically
-   saves it on function entry and restores it on function exit, if the register
-   is used within the function.  */
-#define CALL_USED_REGISTERS		        			\
-{					        			\
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,  /* R0  - R15 */	\
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,  /* R16 - R31 */	\
-  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,  /* R32 - R47 */	\
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,  /* R48 - R63 */	\
-  1,						   /* ARG ptr */	\
-  1, 1, 1, 1, 1, 1, 1, 1,			   /* F0 - F7 */	\
-  1, 0,						   /* A0 - A1 */	\
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,	   /* CRs */		\
-}
-
-/* Zero or more C statements that may conditionally modify two variables
-   `fixed_regs' and `call_used_regs' (both of type `char []') after they have
-   been initialized from the two preceding macros.
-
-   This is necessary in case the fixed or call-clobbered registers depend on
-   target flags.
-
-   You need not define this macro if it has no work to do.
-
-   If the usage of an entire class of registers depends on the target flags,
-   you may indicate this to GCC by using this macro to modify `fixed_regs' and
-   `call_used_regs' to 1 for each of the registers in the classes which should
-   not be used by GCC.  Also define the macro `REG_CLASS_FROM_LETTER' to return
-   `NO_REGS' if it is called with a letter for a class that shouldn't be used.
-
-   (However, if this class is not included in `GENERAL_REGS' and all of the
-   insn patterns whose constraints permit this class are controlled by target
-   switches, then GCC will automatically avoid using these registers when the
-   target switches are opposed to them.)  */
-/* #define CONDITIONAL_REGISTER_USAGE */
-
-/* If this macro is defined and has a nonzero value, it means that `setjmp' and
-   related functions fail to save the registers, or that `longjmp' fails to
-   restore them.  To compensate, the compiler avoids putting variables in
-   registers in functions that use `setjmp'.  */
-/* #define NON_SAVING_SETJMP */
-
-/* Define this macro if the target machine has register windows.  This C
-   expression returns the register number as seen by the called function
-   corresponding to the register number OUT as seen by the calling function.
-   Return OUT if register number OUT is not an outbound register.  */
-/* #define INCOMING_REGNO(OUT) */
-
-/* Define this macro if the target machine has register windows.  This C
-   expression returns the register number as seen by the calling function
-   corresponding to the register number IN as seen by the called function.
-   Return IN if register number IN is not an inbound register.  */
-/* #define OUTGOING_REGNO(IN) */
-
-
-/* Order of allocation of registers */
-
-/* If defined, an initializer for a vector of integers, containing the numbers
-   of hard registers in the order in which GNU CC should prefer to use them
-   (from most preferred to least).
-
-   If this macro is not defined, registers are used lowest numbered first (all
-   else being equal).
-
-   One use of this macro is on machines where the highest numbered registers
-   must always be saved and the save-multiple-registers instruction supports
-   only sequences of consecutive registers.  On such machines, define
-   `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
-   allocatable register first.  */
-
-#define REG_ALLOC_ORDER							\
-{									\
-  /* volatile registers */						\
-  GPR_FIRST + 2,    GPR_FIRST + 3,    GPR_FIRST + 4,    GPR_FIRST + 5,	\
-  GPR_FIRST + 6,    GPR_FIRST + 7,    GPR_FIRST + 8,    GPR_FIRST + 9,	\
-  GPR_FIRST + 10,   GPR_FIRST + 11,   GPR_FIRST + 12,   GPR_FIRST + 13,	\
-  GPR_FIRST + 14,   GPR_FIRST + 15,   GPR_FIRST + 16,   GPR_FIRST + 17,	\
-  GPR_FIRST + 18,   GPR_FIRST + 19,   GPR_FIRST + 20,   GPR_FIRST + 21,	\
-  GPR_FIRST + 22,   GPR_FIRST + 23,   GPR_FIRST + 24,   GPR_FIRST + 25, \
-  GPR_FIRST + 1,							\
-									\
-  /* saved registers */							\
-  GPR_FIRST + 34,   GPR_FIRST + 35,   GPR_FIRST + 36,   GPR_FIRST + 37,	\
-  GPR_FIRST + 38,   GPR_FIRST + 39,   GPR_FIRST + 40,   GPR_FIRST + 41,	\
-  GPR_FIRST + 42,   GPR_FIRST + 43,   GPR_FIRST + 44,   GPR_FIRST + 45,	\
-  GPR_FIRST + 46,   GPR_FIRST + 47,   GPR_FIRST + 48,   GPR_FIRST + 49,	\
-  GPR_FIRST + 50,   GPR_FIRST + 51,   GPR_FIRST + 52,   GPR_FIRST + 53,	\
-  GPR_FIRST + 54,   GPR_FIRST + 55,   GPR_FIRST + 56,   GPR_FIRST + 57,	\
-  GPR_FIRST + 58,   GPR_FIRST + 59,   GPR_FIRST + 60,   GPR_FIRST + 61,	\
-  GPR_FIRST + 62,							\
-									\
-  /* flags */								\
-  FLAG_F2,          FLAG_F3,          FLAG_F0,          FLAG_F1,	\
-  FLAG_SAT,         FLAG_OVERFLOW,    FLAG_ACC_OVER,    FLAG_CARRY,	\
-									\
-  /* accumultors */							\
-  ACCUM_FIRST + 0,  ACCUM_FIRST + 1,					\
-									\
-  /* fixed registers */							\
-  GPR_FIRST + 0,    GPR_FIRST + 26,   GPR_FIRST + 27,   GPR_FIRST + 28,	\
-  GPR_FIRST + 29,   GPR_FIRST + 30,   GPR_FIRST + 31,   GPR_FIRST + 32,	\
-  GPR_FIRST + 33,   GPR_FIRST + 63,					\
-  CR_PSW,	    CR_BPSW,	      CR_PC,		CR_BPC,		\
-  CR_DPSW,	    CR_DPC,	      CR_RPT_C,		CR_RPT_S,	\
-  CR_RPT_E,	    CR_MOD_S,	      CR_MOD_E,		CR_IBA,		\
-  CR_EIT_VB,	    CR_INT_S,	      CR_INT_M,				\
-  ARG_POINTER_REGNUM,							\
-}
-
-/* A C statement (sans semicolon) to choose the order in which to allocate hard
-   registers for pseudo-registers local to a basic block.
-
-   Store the desired register order in the array `reg_alloc_order'.  Element 0
-   should be the register to allocate first; element 1, the next register; and
-   so on.
-
-   The macro body should not assume anything about the contents of
-   `reg_alloc_order' before execution of the macro.
-
-   On most machines, it is not necessary to define this macro.  */
-/* #define ORDER_REGS_FOR_LOCAL_ALLOC */
-
-
-/* How Values Fit in Registers */
-
-/* A C expression for the number of consecutive hard registers, starting at
-   register number REGNO, required to hold a value of mode MODE.
-
-   On a machine where all registers are exactly one word, a suitable definition
-   of this macro is
-
-        #define HARD_REGNO_NREGS(REGNO, MODE)            \
-           ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1)  \
-            / UNITS_PER_WORD))  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)					\
-(ACCUM_P (REGNO) ? ((GET_MODE_SIZE (MODE) + 2*UNITS_PER_WORD - 1)	\
-		    / (2*UNITS_PER_WORD))				\
-		 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1)		\
-		    / UNITS_PER_WORD))
-
-/* A C expression that is nonzero if it is permissible to store a value of mode
-   MODE in hard register number REGNO (or in several registers starting with
-   that one).  For a machine where all registers are equivalent, a suitable
-   definition is
-
-        #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
-   It is not necessary for this macro to check for the numbers of fixed
-   registers, because the allocation mechanism considers them to be always
-   occupied.
-
-   On some machines, double-precision values must be kept in even/odd register
-   pairs.  The way to implement that is to define this macro to reject odd
-   register numbers for such modes.
-
-   The minimum requirement for a mode to be OK in a register is that the
-   `movMODE' instruction pattern support moves between the register and any
-   other hard register for which the mode is OK; and that moving a value into
-   the register and back out not alter it.
-
-   Since the same instruction used to move `SImode' will work for all narrower
-   integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
-   to distinguish between these modes, provided you define patterns `movhi',
-   etc., to take advantage of this.  This is useful because of the interaction
-   between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
-   all integer modes to be tieable.
-
-   Many machines have special registers for floating point arithmetic.  Often
-   people assume that floating point machine modes are allowed only in floating
-   point registers.  This is not true.  Any registers that can hold integers
-   can safely *hold* a floating point machine mode, whether or not floating
-   arithmetic can be done on it in those registers.  Integer move instructions
-   can be used to move the values.
-
-   On some machines, though, the converse is true: fixed-point machine modes
-   may not go in floating registers.  This is true if the floating registers
-   normalize any value stored in them, because storing a non-floating value
-   there would garble it.  In this case, `HARD_REGNO_MODE_OK' should reject
-   fixed-point machine modes in floating registers.  But if the floating
-   registers do not automatically normalize, if you can store any bit pattern
-   in one and retrieve it unchanged without a trap, then any machine mode may
-   go in a floating register, so you can define this macro to say so.
-
-   The primary significance of special floating registers is rather that they
-   are the registers acceptable in floating point arithmetic instructions.
-   However, this is of no concern to `HARD_REGNO_MODE_OK'.  You handle it by
-   writing the proper constraints for those instructions.
-
-   On some machines, the floating registers are especially slow to access, so
-   that it is better to store a value in a stack frame than in such a register
-   if floating point arithmetic is not being done.  As long as the floating
-   registers are not in class `GENERAL_REGS', they will not be used unless some
-   pattern's constraint asks for one.  */
-
-extern unsigned char hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
-#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok[ (int)MODE ][ REGNO ]
-
-/* A C expression that is nonzero if it is desirable to choose register
-   allocation so as to avoid move instructions between a value of mode MODE1
-   and a value of mode MODE2.
-
-   If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
-   ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
-   zero.  */
-
-extern unsigned char modes_tieable_p[];
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  modes_tieable_p[ (((int)(MODE1)) * (NUM_MACHINE_MODES)) + (int)(MODE2) ]
-
-/* Define this macro if the compiler should avoid copies to/from CCmode
-   registers.  You should only define this macro if support fo copying to/from
-   CCmode is incomplete.  */
-   
-/* On the D30V, copying to/from CCmode is complete, but since there are only
-   two CC registers usable for conditional tests, this helps gcse not compound
-   the reload problem.  */
-#define AVOID_CCMODE_COPIES
-
-
-/* Handling Leaf Functions */
-
-/* A C initializer for a vector, indexed by hard register number, which
-   contains 1 for a register that is allowable in a candidate for leaf function
-   treatment.
-
-   If leaf function treatment involves renumbering the registers, then the
-   registers marked here should be the ones before renumbering--those that GNU
-   CC would ordinarily allocate.  The registers which will actually be used in
-   the assembler code, after renumbering, should not be marked with 1 in this
-   vector.
-
-   Define this macro only if the target machine offers a way to optimize the
-   treatment of leaf functions.  */
-/* #define LEAF_REGISTERS */
-
-/* A C expression whose value is the register number to which REGNO should be
-   renumbered, when a function is treated as a leaf function.
-
-   If REGNO is a register number which should not appear in a leaf function
-   before renumbering, then the expression should yield -1, which will cause
-   the compiler to abort.
-
-   Define this macro only if the target machine offers a way to optimize the
-   treatment of leaf functions, and registers need to be renumbered to do this.  */
-/* #define LEAF_REG_REMAP(REGNO) */
-
-
-/* Registers That Form a Stack.  */
-
-/* Define this if the machine has any stack-like registers.  */
-/* #define STACK_REGS */
-
-/* The number of the first stack-like register.  This one is the top
-   of the stack.  */
-/* #define FIRST_STACK_REG */
-
-/* The number of the last stack-like register.  This one is the
-   bottom of the stack.  */
-/* #define LAST_STACK_REG */
-
-
-/* Register Classes */
-
-/* An enumeral type that must be defined with all the register class names as
-   enumeral values.  `NO_REGS' must be first.  `ALL_REGS' must be the last
-   register class, followed by one more enumeral value, `LIM_REG_CLASSES',
-   which is not a register class but rather tells how many classes there are.
-
-   Each register class has a number, which is the value of casting the class
-   name to type `int'.  The number serves as an index in many of the tables
-   described below.  */
-enum reg_class
-{
-  NO_REGS,
-  REPEAT_REGS,
-  CR_REGS,
-  ACCUM_REGS,
-  OTHER_FLAG_REGS,
-  F0_REGS,
-  F1_REGS,
-  BR_FLAG_REGS,
-  FLAG_REGS,
-  EVEN_REGS,
-  GPR_REGS,
-  ALL_REGS,
-  LIM_REG_CLASSES
-};
-
-#define GENERAL_REGS GPR_REGS
-
-/* The number of distinct register classes, defined as follows:
-
-        #define N_REG_CLASSES (int) LIM_REG_CLASSES  */
-#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
-
-/* An initializer containing the names of the register classes as C string
-   constants.  These names are used in writing some of the debugging dumps.  */
-#define REG_CLASS_NAMES							\
-{									\
-  "NO_REGS",								\
-  "REPEAT_REGS",							\
-  "CR_REGS",								\
-  "ACCUM_REGS",								\
-  "OTHER_FLAG_REGS",							\
-  "F0_REGS",								\
-  "F1_REGS",								\
-  "BR_FLAG_REGS",							\
-  "FLAG_REGS",								\
-  "EVEN_REGS",								\
-  "GPR_REGS",								\
-  "ALL_REGS",								\
-}
-
-/* Create mask bits for 3rd word of REG_CLASS_CONTENTS */
-#define MASK_WORD3(REG) ((long)1 << ((REG) - 64))
-
-#define NO_MASK		0
-#define REPEAT_MASK	MASK_WORD3 (CR_RPT_C)
-#define CR_MASK		(MASK_WORD3 (CR_PSW)	 | MASK_WORD3 (CR_BPSW)	  \
-			 | MASK_WORD3 (CR_PC)	 | MASK_WORD3 (CR_BPC)	  \
-			 | MASK_WORD3 (CR_DPSW)	 | MASK_WORD3 (CR_DPC)	  \
-			 | MASK_WORD3 (CR_RPT_C) | MASK_WORD3 (CR_RPT_S)  \
-			 | MASK_WORD3 (CR_RPT_E) | MASK_WORD3 (CR_MOD_S)  \
-			 | MASK_WORD3 (CR_MOD_E) | MASK_WORD3 (CR_IBA)	  \
-			 | MASK_WORD3 (CR_EIT_VB) | MASK_WORD3 (CR_INT_S) \
-			 | MASK_WORD3 (CR_INT_M))
-
-#define ACCUM_MASK	(MASK_WORD3 (ACCUM_A0)	 | MASK_WORD3 (ACCUM_A1))
-#define OTHER_FLAG_MASK	(MASK_WORD3 (FLAG_F2)	 | MASK_WORD3 (FLAG_F3)	\
-			 | MASK_WORD3 (FLAG_SAT) | MASK_WORD3 (FLAG_OVERFLOW) \
-			 | MASK_WORD3 (FLAG_ACC_OVER) | MASK_WORD3 (FLAG_CARRY))
-
-#define F0_MASK		MASK_WORD3 (FLAG_F0)
-#define F1_MASK		MASK_WORD3 (FLAG_F1)
-#define BR_FLAG_MASK	(F0_MASK | F1_MASK)
-#define FLAG_MASK	(BR_FLAG_MASK | OTHER_FLAG_MASK)
-#define SPECIAL_MASK	MASK_WORD3 (ARG_POINTER_REGNUM)
-
-#define ALL_MASK	(CR_MASK | ACCUM_MASK | FLAG_MASK | SPECIAL_MASK)
-
-/* An initializer containing the contents of the register classes, as integers
-   which are bit masks.  The Nth integer specifies the contents of class N.
-   The way the integer MASK is interpreted is that register R is in the class
-   if `MASK & (1 << R)' is 1.
-
-   When the machine has more than 32 registers, an integer does not suffice.
-   Then the integers are replaced by sub-initializers, braced groupings
-   containing several integers.  Each sub-initializer must be suitable as an
-   initializer for the type `HARD_REG_SET' which is defined in
-   `hard-reg-set.h'.  */
-#define REG_CLASS_CONTENTS						\
-{									\
-  { 0x00000000, 0x00000000, NO_MASK },		/* NO_REGS */		\
-  { 0x00000000, 0x00000000, REPEAT_MASK },	/* REPEAT_REGS */	\
-  { 0x00000000, 0x00000000, CR_MASK },		/* CR_REGS */		\
-  { 0x00000000, 0x00000000, ACCUM_MASK },	/* ACCUM_REGS */	\
-  { 0x00000000, 0x00000000, OTHER_FLAG_MASK },	/* OTHER_FLAG_REGS */	\
-  { 0x00000000, 0x00000000, F0_MASK },		/* F0_REGS */		\
-  { 0x00000000, 0x00000000, F1_MASK },		/* F1_REGS */		\
-  { 0x00000000, 0x00000000, BR_FLAG_MASK },	/* BR_FLAG_REGS */	\
-  { 0x00000000, 0x00000000, FLAG_MASK },	/* FLAG_REGS */		\
-  { 0xfffffffc, 0x3fffffff, NO_MASK },		/* EVEN_REGS */		\
-  { 0xffffffff, 0xffffffff, SPECIAL_MASK },	/* GPR_REGS */		\
-  { 0xffffffff, 0xffffffff, ALL_MASK },		/* ALL_REGS */		\
-}
-
-/* A C expression whose value is a register class containing hard register
-   REGNO.  In general there is more than one such class; choose a class which
-   is "minimal", meaning that no smaller class also contains the register.  */
-
-extern enum reg_class regno_reg_class[];
-#define REGNO_REG_CLASS(REGNO) regno_reg_class[ (REGNO) ]
-
-/* A macro whose definition is the name of the class to which a valid base
-   register must belong.  A base register is one used in an address which is
-   the register value plus a displacement.  */
-#define BASE_REG_CLASS GPR_REGS
-
-/* A macro whose definition is the name of the class to which a valid index
-   register must belong.  An index register is one used in an address where its
-   value is either multiplied by a scale factor or added to another register
-   (as well as added to a displacement).  */
-#define INDEX_REG_CLASS GPR_REGS
-
-/* A C expression which defines the machine-dependent operand constraint
-   letters for register classes.  If CHAR is such a letter, the value should be
-   the register class corresponding to it.  Otherwise, the value should be
-   `NO_REGS'.  The register letter `r', corresponding to class `GENERAL_REGS',
-   will not be passed to this macro; you do not need to handle it.
-
-   The following letters are unavailable, due to being used as
-   constraints:
-	'0'..'9'
-	'<', '>'
-	'E', 'F', 'G', 'H'
-	'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
-	'Q', 'R', 'S', 'T', 'U'
-	'V', 'X'
-	'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
-
-extern enum reg_class reg_class_from_letter[];
-#define REG_CLASS_FROM_LETTER(CHAR) reg_class_from_letter[ CHAR ]
-
-/* A C expression which is nonzero if register number NUM is suitable for use
-   as a base register in operand addresses.  It may be either a suitable hard
-   register or a pseudo register that has been allocated such a hard register.  */
-
-#define REGNO_OK_FOR_BASE_P(NUM) 					\
-((NUM) < FIRST_PSEUDO_REGISTER						\
- ? GPR_P (NUM)								\
- : (reg_renumber[NUM] >= 0 && GPR_P (reg_renumber[NUM])))
-
-
-/* A C expression which is nonzero if register number NUM is suitable for use
-   as an index register in operand addresses.  It may be either a suitable hard
-   register or a pseudo register that has been allocated such a hard register.
-
-   The difference between an index register and a base register is that the
-   index register may be scaled.  If an address involves the sum of two
-   registers, neither one of them scaled, then either one may be labeled the
-   "base" and the other the "index"; but whichever labeling is used must fit
-   the machine's constraints of which registers may serve in each capacity.
-   The compiler will try both labelings, looking for one that is valid, and
-   will reload one or both registers only if neither labeling works.  */
-
-#define REGNO_OK_FOR_INDEX_P(NUM)					\
-((NUM) < FIRST_PSEUDO_REGISTER						\
- ? GPR_P (NUM)								\
- : (reg_renumber[NUM] >= 0 && GPR_P (reg_renumber[NUM])))
-
-/* A C expression that places additional restrictions on the register class to
-   use when it is necessary to copy value X into a register in class CLASS.
-   The value is a register class; perhaps CLASS, or perhaps another, smaller
-   class.  On many machines, the following definition is safe:
-
-        #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
-
-   Sometimes returning a more restrictive class makes better code.  For
-   example, on the 68000, when X is an integer constant that is in range for a
-   `moveq' instruction, the value of this macro is always `DATA_REGS' as long
-   as CLASS includes the data registers.  Requiring a data register guarantees
-   that a `moveq' will be used.
-
-   If X is a `const_double', by returning `NO_REGS' you can force X into a
-   memory constant.  This is useful on certain machines where immediate
-   floating values cannot be loaded into certain kinds of registers.  */
-#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
-
-/* Like `PREFERRED_RELOAD_CLASS', but for output reloads instead of input
-   reloads.  If you don't define this macro, the default is to use CLASS,
-   unchanged.  */
-/* #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) */
-
-/* A C expression that places additional restrictions on the register class to
-   use when it is necessary to be able to hold a value of mode MODE in a reload
-   register for which class CLASS would ordinarily be used.
-
-   Unlike `PREFERRED_RELOAD_CLASS', this macro should be used when there are
-   certain modes that simply can't go in certain reload classes.
-
-   The value is a register class; perhaps CLASS, or perhaps another, smaller
-   class.
-
-   Don't define this macro unless the target machine has limitations which
-   require the macro to do something nontrivial.  */
-/* #define LIMIT_RELOAD_CLASS(MODE, CLASS) */
-
-/* Many machines have some registers that cannot be copied directly to or from
-   memory or even from other types of registers.  An example is the `MQ'
-   register, which on most machines, can only be copied to or from general
-   registers, but not memory.  Some machines allow copying all registers to and
-   from memory, but require a scratch register for stores to some memory
-   locations (e.g., those with symbolic address on the RT, and those with
-   certain symbolic address on the Sparc when compiling PIC).  In some cases,
-   both an intermediate and a scratch register are required.
-
-   You should define these macros to indicate to the reload phase that it may
-   need to allocate at least one register for a reload in addition to the
-   register to contain the data.  Specifically, if copying X to a register
-   CLASS in MODE requires an intermediate register, you should define
-   `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
-   whose registers can be used as intermediate registers or scratch registers.
-
-   If copying a register CLASS in MODE to X requires an intermediate or scratch
-   register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
-   largest register class required.  If the requirements for input and output
-   reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
-   instead of defining both macros identically.
-
-   The values returned by these macros are often `GENERAL_REGS'.  Return
-   `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
-   to or from a register of CLASS in MODE without requiring a scratch register.
-   Do not define this macro if it would always return `NO_REGS'.
-
-   If a scratch register is required (either with or without an intermediate
-   register), you should define patterns for `reload_inM' or `reload_outM', as
-   required (*note Standard Names::..  These patterns, which will normally be
-   implemented with a `define_expand', should be similar to the `movM'
-   patterns, except that operand 2 is the scratch register.
-
-   Define constraints for the reload register and scratch register that contain
-   a single register class.  If the original reload register (whose class is
-   CLASS) can meet the constraint given in the pattern, the value returned by
-   these macros is used for the class of the scratch register.  Otherwise, two
-   additional reload registers are required.  Their classes are obtained from
-   the constraints in the insn pattern.
-
-   X might be a pseudo-register or a `subreg' of a pseudo-register, which could
-   either be in a hard register or in memory.  Use `true_regnum' to find out;
-   it will return -1 if the pseudo is in memory and the hard register number if
-   it is in a register.
-
-   These macros should not be used in the case where a particular class of
-   registers can only be copied to memory and not to another class of
-   registers.  In that case, secondary reload registers are not needed and
-   would not be helpful.  Instead, a stack location must be used to perform the
-   copy and the `movM' pattern should use memory as a intermediate storage.
-   This case often occurs between floating-point and general registers.  */
-
-#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X)				\
-((CLASS) == GPR_REGS		? NO_REGS				\
- : (CLASS) == EVEN_REGS		? NO_REGS				\
- : (CLASS) == ACCUM_REGS	? EVEN_REGS				\
- :				  GPR_REGS)
-
-/* #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) */
-/* #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) */
-
-/* Certain machines have the property that some registers cannot be copied to
-   some other registers without using memory.  Define this macro on those
-   machines to be a C expression that is non-zero if objects of mode M in
-   registers of CLASS1 can only be copied to registers of class CLASS2 by
-   storing a register of CLASS1 into memory and loading that memory location
-   into a register of CLASS2.
-
-   Do not define this macro if its value would always be zero.  */
-/* #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, M) */
-
-/* Normally when `SECONDARY_MEMORY_NEEDED' is defined, the compiler allocates a
-   stack slot for a memory location needed for register copies.  If this macro
-   is defined, the compiler instead uses the memory location defined by this
-   macro.
-
-   Do not define this macro if you do not define
-   `SECONDARY_MEMORY_NEEDED'.  */
-/* #define SECONDARY_MEMORY_NEEDED_RTX(MODE) */
-
-/* When the compiler needs a secondary memory location to copy between two
-   registers of mode MODE, it normally allocates sufficient memory to hold a
-   quantity of `BITS_PER_WORD' bits and performs the store and load operations
-   in a mode that many bits wide and whose class is the same as that of MODE.
-
-   This is right thing to do on most machines because it ensures that all bits
-   of the register are copied and prevents accesses to the registers in a
-   narrower mode, which some machines prohibit for floating-point registers.
-
-   However, this default behavior is not correct on some machines, such as the
-   DEC Alpha, that store short integers in floating-point registers differently
-   than in integer registers.  On those machines, the default widening will not
-   work correctly and you must define this macro to suppress that widening in
-   some cases.  See the file `alpha.h' for details.
-
-   Do not define this macro if you do not define `SECONDARY_MEMORY_NEEDED' or
-   if widening MODE to a mode that is `BITS_PER_WORD' bits wide is correct for
-   your machine.  */
-/* #define SECONDARY_MEMORY_NEEDED_MODE(MODE) */
-
-/* Normally the compiler avoids choosing registers that have been explicitly
-   mentioned in the rtl as spill registers (these registers are normally those
-   used to pass parameters and return values).  However, some machines have so
-   few registers of certain classes that there would not be enough registers to
-   use as spill registers if this were done.
-
-   Define `SMALL_REGISTER_CLASSES' to be an expression with a non-zero value on
-   these machines.  When this macro has a non-zero value, the compiler allows
-   registers explicitly used in the rtl to be used as spill registers but
-   avoids extending the lifetime of these registers.
-
-   It is always safe to define this macro with a non-zero value, but if you
-   unnecessarily define it, you will reduce the amount of optimizations that
-   can be performed in some cases.  If you do not define this macro with a
-   non-zero value when it is required, the compiler will run out of spill
-   registers and print a fatal error message.  For most machines, you should
-   not define this macro at all.  */
-/* #define SMALL_REGISTER_CLASSES */
-
-/* A C expression whose value is nonzero if pseudos that have been assigned to
-   registers of class CLASS would likely be spilled because registers of CLASS
-   are needed for spill registers.
-
-   The default value of this macro returns 1 if CLASS has exactly one register
-   and zero otherwise.  On most machines, this default should be used.  Only
-   define this macro to some other expression if pseudo allocated by
-   `local-alloc.c' end up in memory because their hard registers were needed
-   for spill registers.  If this macro returns nonzero for those classes, those
-   pseudos will only be allocated by `global.c', which knows how to reallocate
-   the pseudo to another register.  If there would not be another register
-   available for reallocation, you should not change the definition of this
-   macro since the only effect of such a definition would be to slow down
-   register allocation.  */
-#define CLASS_LIKELY_SPILLED_P(CLASS) \
-  ((CLASS) != GPR_REGS && (CLASS) != EVEN_REGS)
-
-/* A C expression for the maximum number of consecutive registers of
-   class CLASS needed to hold a value of mode MODE.
-
-   This is closely related to the macro `HARD_REGNO_NREGS'.  In fact, the value
-   of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
-   `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
-
-   This macro helps control the handling of multiple-word values in
-   the reload pass.  */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)					\
-(((CLASS) == ACCUM_REGS)						\
- ? ((GET_MODE_SIZE (MODE) + 8 - 1) / 8)					\
- : ((GET_MODE_SIZE (MODE) + 4 - 1) / 4))
-
-/* If defined, a C expression for a class that contains registers which the
-   compiler must always access in a mode that is the same size as the mode in
-   which it loaded the register.
-
-   For the example, loading 32-bit integer or floating-point objects into
-   floating-point registers on the Alpha extends them to 64-bits.  Therefore
-   loading a 64-bit object and then storing it as a 32-bit object does not
-   store the low-order 32-bits, as would be the case for a normal register.
-   Therefore, `alpha.h' defines this macro as `FLOAT_REGS'.  */
-/* #define CLASS_CANNOT_CHANGE_SIZE */
-
-/* A C expression that defines the machine-dependent operand constraint letters
-   (`I', `J', `K', .. 'P') that specify particular ranges of integer values.
-   If C is one of those letters, the expression should check that VALUE, an
-   integer, is in the appropriate range and return 1 if so, 0 otherwise.  If C
-   is not one of those letters, the value should be 0 regardless of VALUE.  */
-#define CONST_OK_FOR_LETTER_P(VALUE, C)					\
-((C) == 'I'	? IN_RANGE_P (VALUE, -32, 31)				\
- : (C) == 'J'	? IN_RANGE_P (VALUE, 0, 31)				\
- : (C) == 'K'	? IN_RANGE_P (exact_log2 (VALUE), 0, 31)		\
- : (C) == 'L'	? IN_RANGE_P (exact_log2 (~ (VALUE)), 0, 31)		\
- : (C) == 'M'	? ((VALUE) == 32)					\
- : (C) == 'N'	? ((VALUE) == 1)					\
- : (C) == 'O'	? ((VALUE) == 0)					\
- : (C) == 'P'	? IN_RANGE_P (VALUE, 32, 63)				\
- :		  FALSE)
-
-/* A C expression that defines the machine-dependent operand constraint letters
-   (`G', `H') that specify particular ranges of `const_double' values.
-
-   If C is one of those letters, the expression should check that VALUE, an RTX
-   of code `const_double', is in the appropriate range and return 1 if so, 0
-   otherwise.  If C is not one of those letters, the value should be 0
-   regardless of VALUE.
-
-   `const_double' is used for all floating-point constants and for `DImode'
-   fixed-point constants.  A given letter can accept either or both kinds of
-   values.  It can use `GET_MODE' to distinguish between these kinds.  */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)				\
-((C) == 'G'	? (CONST_DOUBLE_LOW (VALUE) == 0			\
-		   && CONST_DOUBLE_HIGH (VALUE) == 0)			\
- : (C) == 'H'	? FALSE							\
- :		  FALSE)
-
-/* A C expression that defines the optional machine-dependent constraint
-   letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
-   types of operands, usually memory references, for the target machine.
-   Normally this macro will not be defined.  If it is required for a particular
-   target machine, it should return 1 if VALUE corresponds to the operand type
-   represented by the constraint letter C.  If C is not defined as an extra
-   constraint, the value returned should be 0 regardless of VALUE.
-
-   For example, on the ROMP, load instructions cannot have their output in r0
-   if the memory reference contains a symbolic address.  Constraint letter `Q'
-   is defined as representing a memory address that does *not* contain a
-   symbolic address.  An alternative is specified with a `Q' constraint on the
-   input and `r' on the output.  The next alternative specifies `m' on the
-   input and a register class that does not include r0 on the output.  */
-
-#define EXTRA_CONSTRAINT(VALUE, C)					\
-(((C) == 'Q')	? short_memory_operand ((VALUE), GET_MODE (VALUE))	\
- : ((C) == 'R')	? single_reg_memory_operand ((VALUE), GET_MODE (VALUE))	\
- : ((C) == 'S')	? const_addr_memory_operand ((VALUE), GET_MODE (VALUE))	\
- : ((C) == 'T')	? long_memory_operand ((VALUE), GET_MODE (VALUE))	\
- : ((C) == 'U')	? FALSE							\
- :		  FALSE)
-
-
-/* Basic Stack Layout */
-
-/* Stack layout */
-
-/* Structure used to define the d30v stack */
-typedef struct d30v_stack {
-  int varargs_p;		/* whether this is a varargs function */
-  int varargs_size;		/* size to hold varargs args passed in regs */
-  int vars_size;		/* variable save area size */
-  int parm_size;		/* outgoing parameter size */
-  int gpr_size;			/* size of saved GPR registers */
-  int accum_size;		/* size of saved ACCUM registers */
-  int total_size;		/* total bytes allocated for stack */
-				/* which registers are to be saved */
-  int save_offset;		/* offset from new sp to start saving vars at */
-  int link_offset;		/* offset r62 is saved at */
-  int memrefs_varargs;		/* # of 2 word memory references for varargs */
-  int memrefs_2words;		/* # of 2 word memory references */
-  int memrefs_1word;		/* # of 1 word memory references */
-				/* 1 for ldw/stw ops; 2 for ld2w/st2w ops */
-  unsigned char save_p[FIRST_PSEUDO_REGISTER];
-} d30v_stack_t;
-
-/* Define this macro if pushing a word onto the stack moves the stack pointer
-   to a smaller address.
-
-   When we say, "define this macro if ...," it means that the compiler checks
-   this macro only with `#ifdef' so the precise definition used does not
-   matter.  */
-#define STACK_GROWS_DOWNWARD 1
-
-/* Define this macro if the addresses of local variable slots are at negative
-   offsets from the frame pointer.  */
-/* #define FRAME_GROWS_DOWNWARD */
-
-/* Define this macro if successive arguments to a function occupy decreasing
-   addresses on the stack.  */
-/* #define ARGS_GROW_DOWNWARD */
-
-/* Offset from the frame pointer to the first local variable slot to be
-   allocated.
-
-   If `FRAME_GROWS_DOWNWARD', find the next slot's offset by subtracting the
-   first slot's length from `STARTING_FRAME_OFFSET'.  Otherwise, it is found by
-   adding the length of the first slot to the value `STARTING_FRAME_OFFSET'.  */
-
-#define STARTING_FRAME_OFFSET						\
-  (D30V_ALIGN (current_function_outgoing_args_size,			\
-	       (STACK_BOUNDARY / BITS_PER_UNIT)))
-
-/* Offset from the stack pointer register to the first location at which
-   outgoing arguments are placed.  If not specified, the default value of zero
-   is used.  This is the proper value for most machines.
-
-   If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first
-   location at which outgoing arguments are placed.  */
-/* #define STACK_POINTER_OFFSET */
-
-/* Offset from the argument pointer register to the first argument's address.
-   On some machines it may depend on the data type of the function.
-
-   If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first
-   argument's address.  */
-#define FIRST_PARM_OFFSET(FUNDECL) 0
-
-/* Offset from the stack pointer register to an item dynamically allocated on
-   the stack, e.g., by `alloca'.
-
-   The default value for this macro is `STACK_POINTER_OFFSET' plus the length
-   of the outgoing arguments.  The default is correct for most machines.  See
-   `function.c' for details.  */
-/* #define STACK_DYNAMIC_OFFSET(FUNDECL) */
-
-/* A C expression whose value is RTL representing the address in a stack frame
-   where the pointer to the caller's frame is stored.  Assume that FRAMEADDR is
-   an RTL expression for the address of the stack frame itself.
-
-   If you don't define this macro, the default is to return the value of
-   FRAMEADDR--that is, the stack frame address is also the address of the stack
-   word that points to the previous frame.  */
-/* #define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) */
-
-/* If defined, a C expression that produces the machine-specific code to setup
-   the stack so that arbitrary frames can be accessed.  For example, on the
-   Sparc, we must flush all of the register windows to the stack before we can
-   access arbitrary stack frames.  This macro will seldom need to be defined.  */
-/* #define SETUP_FRAME_ADDRESSES() */
-
-/* A C expression whose value is RTL representing the value of the return
-   address for the frame COUNT steps up from the current frame, after the
-   prologue.  FRAMEADDR is the frame pointer of the COUNT frame, or the frame
-   pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
-   defined.
-
-   The value of the expression must always be the correct address when COUNT is
-   zero, but may be `NULL_RTX' if there is not way to determine the return
-   address of other frames.  */
-
-/* ??? This definition fails for leaf functions.  There is currently no
-   general solution for this problem.  */
-
-/* ??? There appears to be no way to get the return address of any previous
-   frame except by disassembling instructions in the prologue/epilogue.
-   So currently we support only the current frame.  */
-
-#define RETURN_ADDR_RTX(COUNT, FRAME)					\
-  ((COUNT) == 0 ? d30v_return_addr() : const0_rtx)
-
-/* Define this if the return address of a particular stack frame is
-   accessed from the frame pointer of the previous stack frame.  */
-/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
-
-/* A C expression whose value is RTL representing the location of the incoming
-   return address at the beginning of any function, before the prologue.  This
-   RTL is either a `REG', indicating that the return value is saved in `REG',
-   or a `MEM' representing a location in the stack.
-
-   You only need to define this macro if you want to support call frame
-   debugging information like that provided by DWARF 2.  */
-
-/* Before the prologue, RA lives in r62.  */
-#define INCOMING_RETURN_ADDR_RTX  gen_rtx (REG, Pmode, GPR_LINK)
-
-/* A C expression whose value is an integer giving the offset, in bytes, from
-   the value of the stack pointer register to the top of the stack frame at the
-   beginning of any function, before the prologue.  The top of the frame is
-   defined to be the value of the stack pointer in the previous frame, just
-   before the call instruction.
-
-   You only need to define this macro if you want to support call frame
-   debugging information like that provided by DWARF 2.  */
-#define INCOMING_FRAME_SP_OFFSET 0
-
-/* Initialize data used by insn expanders.  This is called from insn_emit,
-   once for every function before code is generated.  */
-
-#define INIT_EXPANDERS  d30v_init_expanders ()
-extern void d30v_init_expanders ();
-
-/* Stack Checking.  */
-
-/* A nonzero value if stack checking is done by the configuration files in a
-   machine-dependent manner.  You should define this macro if stack checking is
-   require by the ABI of your machine or if you would like to have to stack
-   checking in some more efficient way than GNU CC's portable approach.  The
-   default value of this macro is zero.  */
-/* #define STACK_CHECK_BUILTIN */
-
-/* An integer representing the interval at which GNU CC must generate stack
-   probe instructions.  You will normally define this macro to be no larger
-   than the size of the "guard pages" at the end of a stack area.  The default
-   value of 4096 is suitable for most systems.  */
-/* #define STACK_CHECK_PROBE_INTERVAL */
-
-/* A integer which is nonzero if GNU CC should perform the stack probe as a
-   load instruction and zero if GNU CC should use a store instruction.  The
-   default is zero, which is the most efficient choice on most systems.  */
-/* #define STACK_CHECK_PROBE_LOAD */
-
-/* The number of bytes of stack needed to recover from a stack overflow, for
-   languages where such a recovery is supported.  The default value of 75 words
-   should be adequate for most machines.  */
-/* #define STACK_CHECK_PROTECT */
-
-/* The maximum size of a stack frame, in bytes.  GNU CC will generate probe
-   instructions in non-leaf functions to ensure at least this many bytes of
-   stack are available.  If a stack frame is larger than this size, stack
-   checking will not be reliable and GNU CC will issue a warning.  The default
-   is chosen so that GNU CC only generates one instruction on most systems.
-   You should normally not change the default value of this macro.  */
-/* #define STACK_CHECK_MAX_FRAME_SIZE */
-
-/* GNU CC uses this value to generate the above warning message.  It represents
-   the amount of fixed frame used by a function, not including space for any
-   callee-saved registers, temporaries and user variables.  You need only
-   specify an upper bound for this amount and will normally use the default of
-   four words.  */
-/* #define STACK_CHECK_FIXED_FRAME_SIZE */
-
-/* The maximum size, in bytes, of an object that GNU CC will place in the fixed
-   area of the stack frame when the user specifies `-fstack-check'.  GNU CC
-   computed the default from the values of the above macros and you will
-   normally not need to override that default.  */
-/* #define STACK_CHECK_MAX_VAR_SIZE */
-
-
-/* Register That Address the Stack Frame.  */
-
-/* The register number of the stack pointer register, which must also be a
-   fixed register according to `FIXED_REGISTERS'.  On most machines, the
-   hardware determines which register this is.  */
-#define STACK_POINTER_REGNUM GPR_SP
-
-/* The register number of the frame pointer register, which is used to access
-   automatic variables in the stack frame.  On some machines, the hardware
-   determines which register this is.  On other machines, you can choose any
-   register you wish for this purpose.  */
-#define FRAME_POINTER_REGNUM GPR_FP
-
-/* On some machines the offset between the frame pointer and starting offset of
-   the automatic variables is not known until after register allocation has
-   been done (for example, because the saved registers are between these two
-   locations).  On those machines, define `FRAME_POINTER_REGNUM' the number of
-   a special, fixed register to be used internally until the offset is known,
-   and define `HARD_FRAME_POINTER_REGNUM' to be actual the hard register number
-   used for the frame pointer.
-
-   You should define this macro only in the very rare circumstances when it is
-   not possible to calculate the offset between the frame pointer and the
-   automatic variables until after register allocation has been completed.
-   When this macro is defined, you must also indicate in your definition of
-   `ELIMINABLE_REGS' how to eliminate `FRAME_POINTER_REGNUM' into either
-   `HARD_FRAME_POINTER_REGNUM' or `STACK_POINTER_REGNUM'.
-
-   Do not define this macro if it would be the same as `FRAME_POINTER_REGNUM'.  */
-/* #define HARD_FRAME_POINTER_REGNUM */
-
-/* The register number of the arg pointer register, which is used to access the
-   function's argument list.  On some machines, this is the same as the frame
-   pointer register.  On some machines, the hardware determines which register
-   this is.  On other machines, you can choose any register you wish for this
-   purpose.  If this is not the same register as the frame pointer register,
-   then you must mark it as a fixed register according to `FIXED_REGISTERS', or
-   arrange to be able to eliminate it (*note Elimination::.).  */
-/* #define ARG_POINTER_REGNUM */
-
-/* The register number of the return address pointer register, which is used to
-   access the current function's return address from the stack.  On some
-   machines, the return address is not at a fixed offset from the frame pointer
-   or stack pointer or argument pointer.  This register can be defined to point
-   to the return address on the stack, and then be converted by
-   `ELIMINABLE_REGS' into either the frame pointer or stack pointer.
-
-   Do not define this macro unless there is no other way to get the return
-   address from the stack.  */
-/* #define RETURN_ADDRESS_POINTER_REGNUM */
-
-/* Register numbers used for passing a function's static chain pointer.  If
-   register windows are used, the register number as seen by the called
-   function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as
-   seen by the calling function is `STATIC_CHAIN_REGNUM'.  If these registers
-   are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined.
-
-   The static chain register need not be a fixed register.
-
-   If the static chain is passed in memory, these macros should not be defined;
-   instead, the next two macros should be defined.  */
-
-#define STATIC_CHAIN_REGNUM (GPR_FIRST + 18)
-/* #define STATIC_CHAIN_INCOMING_REGNUM */
-
-/* If the static chain is passed in memory, these macros provide rtx giving
-   `mem' expressions that denote where they are stored.  `STATIC_CHAIN' and
-   `STATIC_CHAIN_INCOMING' give the locations as seen by the calling and called
-   functions, respectively.  Often the former will be at an offset from the
-   stack pointer and the latter at an offset from the frame pointer.
-
-   The variables `stack_pointer_rtx', `frame_pointer_rtx', and
-   `arg_pointer_rtx' will have been initialized prior to the use of these
-   macros and should be used to refer to those items.
-
-   If the static chain is passed in a register, the two previous
-   macros should be defined instead.  */
-/* #define STATIC_CHAIN */
-/* #define STATIC_CHAIN_INCOMING */
-
-
-/* Eliminating the Frame Pointer and the Arg Pointer */
-
-/* A C expression which is nonzero if a function must have and use a frame
-   pointer.  This expression is evaluated in the reload pass.  If its value is
-   nonzero the function will have a frame pointer.
-
-   The expression can in principle examine the current function and decide
-   according to the facts, but on most machines the constant 0 or the constant
-   1 suffices.  Use 0 when the machine allows code to be generated with no
-   frame pointer, and doing so saves some time or space.  Use 1 when there is
-   no possible advantage to avoiding a frame pointer.
-
-   In certain cases, the compiler does not know how to produce valid code
-   without a frame pointer.  The compiler recognizes those cases and
-   automatically gives the function a frame pointer regardless of what
-   `FRAME_POINTER_REQUIRED' says.  You don't need to worry about them.
-
-   In a function that does not require a frame pointer, the frame pointer
-   register can be allocated for ordinary usage, unless you mark it as a fixed
-   register.  See `FIXED_REGISTERS' for more information.  */
-#define FRAME_POINTER_REQUIRED 0
-
-/* A C statement to store in the variable DEPTH-VAR the difference between the
-   frame pointer and the stack pointer values immediately after the function
-   prologue.  The value would be computed from information such as the result
-   of `get_frame_size ()' and the tables of registers `regs_ever_live' and
-   `call_used_regs'.
-
-   If `ELIMINABLE_REGS' is defined, this macro will be not be used and need not
-   be defined.  Otherwise, it must be defined even if `FRAME_POINTER_REQUIRED'
-   is defined to always be true; in that case, you may set DEPTH-VAR to
-   anything.  */
-/* #define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) */
-
-/* If defined, this macro specifies a table of register pairs used to eliminate
-   unneeded registers that point into the stack frame.  If it is not defined,
-   the only elimination attempted by the compiler is to replace references to
-   the frame pointer with references to the stack pointer.
-
-   The definition of this macro is a list of structure initializations, each of
-   which specifies an original and replacement register.
-
-   On some machines, the position of the argument pointer is not known until
-   the compilation is completed.  In such a case, a separate hard register must
-   be used for the argument pointer.  This register can be eliminated by
-   replacing it with either the frame pointer or the argument pointer,
-   depending on whether or not the frame pointer has been eliminated.
-
-   In this case, you might specify:
-        #define ELIMINABLE_REGS  \
-        {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
-         {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
-         {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
-
-   Note that the elimination of the argument pointer with the stack pointer is
-   specified first since that is the preferred elimination.  */
-#define ELIMINABLE_REGS							\
-{									\
-  { ARG_POINTER_REGNUM,		STACK_POINTER_REGNUM },			\
-  { ARG_POINTER_REGNUM,		FRAME_POINTER_REGNUM },			\
-  { FRAME_POINTER_REGNUM,	STACK_POINTER_REGNUM }			\
-}
-
-/* A C expression that returns non-zero if the compiler is allowed to try to
-   replace register number FROM-REG with register number TO-REG.  This macro
-   need only be defined if `ELIMINABLE_REGS' is defined, and will usually be
-   the constant 1, since most of the cases preventing register elimination are
-   things that the compiler already knows about.  */
-
-#define CAN_ELIMINATE(FROM, TO)						\
- ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM		\
-  ? ! frame_pointer_needed						\
-  : 1)
-
-/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'.  It specifies the
-   initial difference between the specified pair of registers.  This macro must
-   be defined if `ELIMINABLE_REGS' is defined.  */
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
-{									\
-  d30v_stack_t *info = d30v_stack_info ();				\
-									\
-  if ((FROM) == FRAME_POINTER_REGNUM)					\
-    (OFFSET) = 0;							\
-  else if ((FROM) == ARG_POINTER_REGNUM)				\
-    (OFFSET) = info->total_size;					\
-  else									\
-    abort ();								\
-}
-
-/* Define this macro if the `longjmp' function restores registers from the
-   stack frames, rather than from those saved specifically by `setjmp'.
-   Certain quantities must not be kept in registers across a call to `setjmp'
-   on such machines.  */
-/* #define LONGJMP_RESTORE_FROM_STACK */
-
-
-/* Passing Function Arguments on the Stack */
-
-/* Define this macro if an argument declared in a prototype as an integral type
-   smaller than `int' should actually be passed as an `int'.  In addition to
-   avoiding errors in certain cases of mismatch, it also makes for better code
-   on certain machines.  */
-/* #define PROMOTE_PROTOTYPES */
-
-/* A C expression that is the number of bytes actually pushed onto the stack
-   when an instruction attempts to push NPUSHED bytes.
-
-   If the target machine does not have a push instruction, do not define this
-   macro.  That directs GNU CC to use an alternate strategy: to allocate the
-   entire argument block and then store the arguments into it.
-
-   On some machines, the definition
-
-        #define PUSH_ROUNDING(BYTES) (BYTES)
-
-   will suffice.  But on other machines, instructions that appear to push one
-   byte actually push two bytes in an attempt to maintain alignment.  Then the
-   definition should be
-
-        #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)  */
-/* #define PUSH_ROUNDING(NPUSHED) */
-
-/* If defined, the maximum amount of space required for outgoing arguments will
-   be computed and placed into the variable
-   `current_function_outgoing_args_size'.  No space will be pushed onto the
-   stack for each call; instead, the function prologue should increase the
-   stack frame size by this amount.
-
-   Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not
-   proper.  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Define this macro if functions should assume that stack space has been
-   allocated for arguments even when their values are passed in registers.
-
-   The value of this macro is the size, in bytes, of the area reserved for
-   arguments passed in registers for the function represented by FNDECL.
-
-   This space can be allocated by the caller, or be a part of the
-   machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
-   which.  */
-/* #define REG_PARM_STACK_SPACE(FNDECL) */
-
-/* Define these macros in addition to the one above if functions might allocate
-   stack space for arguments even when their values are passed in registers.
-   These should be used when the stack space allocated for arguments in
-   registers is not a simple constant independent of the function declaration.
-
-   The value of the first macro is the size, in bytes, of the area that we
-   should initially assume would be reserved for arguments passed in registers.
-
-   The value of the second macro is the actual size, in bytes, of the area that
-   will be reserved for arguments passed in registers.  This takes two
-   arguments: an integer representing the number of bytes of fixed sized
-   arguments on the stack, and a tree representing the number of bytes of
-   variable sized arguments on the stack.
-
-   When these macros are defined, `REG_PARM_STACK_SPACE' will only be called
-   for libcall functions, the current function, or for a function being called
-   when it is known that such stack space must be allocated.  In each case this
-   value can be easily computed.
-
-   When deciding whether a called function needs such stack space, and how much
-   space to reserve, GNU CC uses these two macros instead of
-   `REG_PARM_STACK_SPACE'.  */
-/* #define MAYBE_REG_PARM_STACK_SPACE */
-/* #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) */
-
-/* Define this if it is the responsibility of the caller to allocate the area
-   reserved for arguments passed in registers.
-
-   If `ACCUMULATE_OUTGOING_ARGS' is defined, this macro controls whether the
-   space for these arguments counts in the value of
-   `current_function_outgoing_args_size'.  */
-/* #define OUTGOING_REG_PARM_STACK_SPACE */
-
-/* Define this macro if `REG_PARM_STACK_SPACE' is defined, but the stack
-   parameters don't skip the area specified by it.
-
-   Normally, when a parameter is not passed in registers, it is placed on the
-   stack beyond the `REG_PARM_STACK_SPACE' area.  Defining this macro
-   suppresses this behavior and causes the parameter to be passed on the stack
-   in its natural location.  */
-/* #define STACK_PARMS_IN_REG_PARM_AREA */
-
-/* A C expression that should indicate the number of bytes of its own arguments
-   that a function pops on returning, or 0 if the function pops no arguments
-   and the caller must therefore pop them all after the function returns.
-
-   FUNDECL is a C variable whose value is a tree node that describes the
-   function in question.  Normally it is a node of type `FUNCTION_DECL' that
-   describes the declaration of the function.  From this it is possible to
-   obtain the DECL_MACHINE_ATTRIBUTES of the function.
-
-   FUNTYPE is a C variable whose value is a tree node that describes the
-   function in question.  Normally it is a node of type `FUNCTION_TYPE' that
-   describes the data type of the function.  From this it is possible to obtain
-   the data types of the value and arguments (if known).
-
-   When a call to a library function is being considered, FUNTYPE will contain
-   an identifier node for the library function.  Thus, if you need to
-   distinguish among various library functions, you can do so by their names.
-   Note that "library function" in this context means a function used to
-   perform arithmetic, whose name is known specially in the compiler and was
-   not mentioned in the C code being compiled.
-
-   STACK-SIZE is the number of bytes of arguments passed on the stack.  If a
-   variable number of bytes is passed, it is zero, and argument popping will
-   always be the responsibility of the calling function.
-
-   On the Vax, all functions always pop their arguments, so the definition of
-   this macro is STACK-SIZE.  On the 68000, using the standard calling
-   convention, no functions pop their arguments, so the value of the macro is
-   always 0 in this case.  But an alternative calling convention is available
-   in which functions that take a fixed number of arguments pop them but other
-   functions (such as `printf') pop nothing (the caller pops all).  When this
-   convention is in use, FUNTYPE is examined to determine whether a function
-   takes a fixed number of arguments.  */
-#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
-
-
-/* Function Arguments in Registers */
-
-/* A C expression that controls whether a function argument is passed in a
-   register, and which register.
-
-   The arguments are CUM, which summarizes all the previous arguments; MODE,
-   the machine mode of the argument; TYPE, the data type of the argument as a
-   tree node or 0 if that is not known (which happens for C support library
-   functions); and NAMED, which is 1 for an ordinary argument and 0 for
-   nameless arguments that correspond to `...' in the called function's
-   prototype.
-
-   The value of the expression should either be a `reg' RTX for the hard
-   register in which to pass the argument, or zero to pass the argument on the
-   stack.
-
-   For machines like the Vax and 68000, where normally all arguments are
-   pushed, zero suffices as a definition.
-
-   The usual way to make the ANSI library `stdarg.h' work on a machine where
-   some arguments are usually passed in registers, is to cause nameless
-   arguments to be passed on the stack instead.  This is done by making
-   `FUNCTION_ARG' return 0 whenever NAMED is 0.
-
-   You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
-   this macro to determine if this argument is of a type that must be passed in
-   the stack.  If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
-   returns non-zero for such an argument, the compiler will abort.  If
-   `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
-   stack and then loaded into a register.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  d30v_function_arg (&CUM, (int)MODE, TYPE, NAMED, FALSE)
-
-/* Define this macro if the target machine has "register windows", so that the
-   register in which a function sees an arguments is not necessarily the same
-   as the one in which the caller passed the argument.
-
-   For such machines, `FUNCTION_ARG' computes the register in which the caller
-   passes the value, and `FUNCTION_INCOMING_ARG' should be defined in a similar
-   fashion to tell the function being called where the arguments will arrive.
-
-   If `FUNCTION_INCOMING_ARG' is not defined, `FUNCTION_ARG' serves both
-   purposes.  */
-
-#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
-  d30v_function_arg (&CUM, (int)MODE, TYPE, NAMED, TRUE)
-
-/* A C expression for the number of words, at the beginning of an argument,
-   must be put in registers.  The value must be zero for arguments that are
-   passed entirely in registers or that are entirely pushed on the stack.
-
-   On some machines, certain arguments must be passed partially in registers
-   and partially in memory.  On these machines, typically the first N words of
-   arguments are passed in registers, and the rest on the stack.  If a
-   multi-word argument (a `double' or a structure) crosses that boundary, its
-   first few words must be passed in registers and the rest must be pushed.
-   This macro tells the compiler when this occurs, and how many of the words
-   should go in registers.
-
-   `FUNCTION_ARG' for these arguments should return the first register to be
-   used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
-   the called function.  */
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-  d30v_function_arg_partial_nregs (&CUM, (int)MODE, TYPE, NAMED)
-
-/* A C expression that indicates when an argument must be passed by reference.
-   If nonzero for an argument, a copy of that argument is made in memory and a
-   pointer to the argument is passed instead of the argument itself.  The
-   pointer is passed in whatever way is appropriate for passing a pointer to
-   that type.
-
-   On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
-   definition of this macro might be
-        #define FUNCTION_ARG_PASS_BY_REFERENCE\
-        (CUM, MODE, TYPE, NAMED)  \
-          MUST_PASS_IN_STACK (MODE, TYPE)  */
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
-
-/* If defined, a C expression that indicates when it is more
-   desirable to keep an argument passed by invisible reference as a
-   reference, rather than copying it to a pseudo register.  */
-/* #define FUNCTION_ARG_KEEP_AS_REFERENCE(CUM, MODE, TYPE, NAMED) */
-
-/* If defined, a C expression that indicates when it is the called function's
-   responsibility to make a copy of arguments passed by invisible reference.
-   Normally, the caller makes a copy and passes the address of the copy to the
-   routine being called.  When FUNCTION_ARG_CALLEE_COPIES is defined and is
-   nonzero, the caller does not make a copy.  Instead, it passes a pointer to
-   the "live" value.  The called function must not modify this value.  If it
-   can be determined that the value won't be modified, it need not make a copy;
-   otherwise a copy must be made.  */
-/* #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) */
-
-/* If defined, a C expression that indicates when it is more desirable to keep
-   an argument passed by invisible reference as a reference, rather than
-   copying it to a pseudo register.  */
-/* #define FUNCTION_ARG_KEEP_AS_REFERENCE(CUM, MODE, TYPE, NAMED) */
-
-/* A C type for declaring a variable that is used as the first argument of
-   `FUNCTION_ARG' and other related values.  For some target machines, the type
-   `int' suffices and can hold the number of bytes of argument so far.
-
-   There is no need to record in `CUMULATIVE_ARGS' anything about the arguments
-   that have been passed on the stack.  The compiler has other variables to
-   keep track of that.  For target machines on which all arguments are passed
-   on the stack, there is no need to store anything in `CUMULATIVE_ARGS';
-   however, the data structure must exist and should not be empty, so use
-   `int'.  */
-typedef int CUMULATIVE_ARGS;
-
-/* A C statement (sans semicolon) for initializing the variable CUM for the
-   state at the beginning of the argument list.  The variable has type
-   `CUMULATIVE_ARGS'.  The value of FNTYPE is the tree node for the data type
-   of the function which will receive the args, or 0 if the args are to a
-   compiler support library function.  The value of INDIRECT is nonzero when
-   processing an indirect call, for example a call through a function pointer.
-   The value of INDIRECT is zero for a call to an explicitly named function, a
-   library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
-   arguments for the function being compiled.
-
-   When processing a call to a compiler support library function, LIBNAME
-   identifies which one.  It is a `symbol_ref' rtx which contains the name of
-   the function, as a string.  LIBNAME is 0 when an ordinary C function call is
-   being processed.  Thus, each time this macro is called, either LIBNAME or
-   FNTYPE is nonzero, but never both of them at once.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
-  d30v_init_cumulative_args (&CUM, FNTYPE, LIBNAME, INDIRECT, FALSE)
-
-/* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
-   arguments for the function being compiled.  If this macro is undefined,
-   `INIT_CUMULATIVE_ARGS' is used instead.
-
-   The value passed for LIBNAME is always 0, since library routines with
-   special calling conventions are never compiled with GNU CC.  The argument
-   LIBNAME exists for symmetry with `INIT_CUMULATIVE_ARGS'.  */
-
-#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
-  d30v_init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, TRUE)
-
-/* A C statement (sans semicolon) to update the summarizer variable CUM to
-   advance past an argument in the argument list.  The values MODE, TYPE and
-   NAMED describe that argument.  Once this is done, the variable CUM is
-   suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
-
-   This macro need not do anything if the argument in question was passed on
-   the stack.  The compiler knows how to track the amount of stack space used
-   for arguments without any special help.  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
-  d30v_function_arg_advance (&CUM, (int) MODE, TYPE, NAMED)
-
-/* If defined, a C expression which determines whether, and in which direction,
-   to pad out an argument with extra space.  The value should be of type `enum
-   direction': either `upward' to pad above the argument, `downward' to pad
-   below, or `none' to inhibit padding.
-
-   The *amount* of padding is always just enough to reach the next multiple of
-   `FUNCTION_ARG_BOUNDARY'; this macro does not control it.
-
-   This macro has a default definition which is right for most systems.  For
-   little-endian machines, the default is to pad upward.  For big-endian
-   machines, the default is to pad downward for an argument of constant size
-   shorter than an `int', and upward otherwise.  */
-/* #define FUNCTION_ARG_PADDING(MODE, TYPE) */
-
-/* If defined, a C expression that gives the alignment boundary, in bits, of an
-   argument with the specified mode and type.  If it is not defined,
-   `PARM_BOUNDARY' is used for all arguments.  */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
-  d30v_function_arg_boundary ((int) MODE, TYPE)
-
-/* A C expression that is nonzero if REGNO is the number of a hard register in
-   which function arguments are sometimes passed.  This does *not* include
-   implicit arguments such as the static chain and the structure-value address.
-   On many machines, no registers can be used for this purpose since all
-   function arguments are pushed on the stack.  */
-
-#define FUNCTION_ARG_REGNO_P(REGNO) \
-  IN_RANGE_P (REGNO, GPR_ARG_FIRST, GPR_ARG_LAST)
-
-
-/* How Scalar Function Values are Returned */
-
-/* Define this macro if `-traditional' should not cause functions declared to
-   return `float' to convert the value to `double'.  */ /* #define
-   TRADITIONAL_RETURN_FLOAT */
-
-/* A C expression to create an RTX representing the place where a function
-   returns a value of data type VALTYPE.  VALTYPE is a tree node representing a
-   data type.  Write `TYPE_MODE (VALTYPE)' to get the machine mode used to
-   represent that type.  On many machines, only the mode is relevant.
-   (Actually, on most machines, scalar values are returned in the same place
-   regardless of mode).
-
-   If `PROMOTE_FUNCTION_RETURN' is defined, you must apply the same promotion
-   rules specified in `PROMOTE_MODE' if VALTYPE is a scalar type.
-
-   If the precise function being called is known, FUNC is a tree node
-   (`FUNCTION_DECL') for it; otherwise, FUNC is a null pointer.  This makes it
-   possible to use a different value-returning convention for specific
-   functions when all their calls are known.
-
-   `FUNCTION_VALUE' is not used for return vales with aggregate data types,
-   because these are returned in another way.  See `STRUCT_VALUE_REGNUM' and
-   related macros, below.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), GPR_RET_VALUE)
-
-/* Define this macro if the target machine has "register windows" so that the
-   register in which a function returns its value is not the same as the one in
-   which the caller sees the value.
-
-   For such machines, `FUNCTION_VALUE' computes the register in which the
-   caller will see the value.  `FUNCTION_OUTGOING_VALUE' should be defined in a
-   similar fashion to tell the function where to put the value.
-
-   If `FUNCTION_OUTGOING_VALUE' is not defined, `FUNCTION_VALUE' serves both
-   purposes.
-
-   `FUNCTION_OUTGOING_VALUE' is not used for return vales with aggregate data
-   types, because these are returned in another way.  See `STRUCT_VALUE_REGNUM'
-   and related macros, below.  */
-/* #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) */
-
-/* A C expression to create an RTX representing the place where a library
-   function returns a value of mode MODE.  If the precise function being called
-   is known, FUNC is a tree node (`FUNCTION_DECL') for it; otherwise, FUNC is a
-   null pointer.  This makes it possible to use a different value-returning
-   convention for specific functions when all their calls are known.
-
-   Note that "library function" in this context means a compiler support
-   routine, used to perform arithmetic, whose name is known specially by the
-   compiler and was not mentioned in the C code being compiled.
-
-   The definition of `LIBRARY_VALUE' need not be concerned aggregate data
-   types, because none of the library functions returns such types.  */
-
-#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, GPR_RET_VALUE)
-
-/* A C expression that is nonzero if REGNO is the number of a hard register in
-   which the values of called function may come back.
-
-   A register whose use for returning values is limited to serving as the
-   second of a pair (for a value of type `double', say) need not be recognized
-   by this macro.  So for most machines, this definition suffices:
-
-        #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-   If the machine has register windows, so that the caller and the called
-   function use different registers for the return value, this macro should
-   recognize only the caller's register numbers.  */
-
-#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == GPR_RET_VALUE)
-
-/* Define this macro if `untyped_call' and `untyped_return' need more space
-   than is implied by `FUNCTION_VALUE_REGNO_P' for saving and restoring an
-   arbitrary return value.  */
-/* #define APPLY_RESULT_SIZE */
-
-
-/* How Large Values are Returned */
-
-/* A C expression which can inhibit the returning of certain function values in
-   registers, based on the type of value.  A nonzero value says to return the
-   function value in memory, just as large structures are always returned.
-   Here TYPE will be a C expression of type `tree', representing the data type
-   of the value.
-
-   Note that values of mode `BLKmode' must be explicitly handled by this macro.
-   Also, the option `-fpcc-struct-return' takes effect regardless of this
-   macro.  On most systems, it is possible to leave the macro undefined; this
-   causes a default definition to be used, whose value is the constant 1 for
-   `BLKmode' values, and 0 otherwise.
-
-   Do not use this macro to indicate that structures and unions should always
-   be returned in memory.  You should instead use `DEFAULT_PCC_STRUCT_RETURN'
-   to indicate this.  */
-/* #define RETURN_IN_MEMORY(TYPE) */
-
-/* Define this macro to be 1 if all structure and union return values must be
-   in memory.  Since this results in slower code, this should be defined only
-   if needed for compatibility with other compilers or with an ABI.  If you
-   define this macro to be 0, then the conventions used for structure and union
-   return values are decided by the `RETURN_IN_MEMORY' macro.
-
-   If not defined, this defaults to the value 1.  */
-/* #define DEFAULT_PCC_STRUCT_RETURN */
-
-/* If the structure value address is passed in a register, then
-   `STRUCT_VALUE_REGNUM' should be the number of that register.  */
-
-#define STRUCT_VALUE_REGNUM GPR_ARG_FIRST
-
-/* If the structure value address is not passed in a register, define
-   `STRUCT_VALUE' as an expression returning an RTX for the place where the
-   address is passed.  If it returns 0, the address is passed as an "invisible"
-   first argument.  */
-
-#define STRUCT_VALUE 0
-
-/* On some architectures the place where the structure value address is found
-   by the called function is not the same place that the caller put it.  This
-   can be due to register windows, or it could be because the function prologue
-   moves it to a different place.
-
-   If the incoming location of the structure value address is in a register,
-   define this macro as the register number.  */
-/* #define STRUCT_VALUE_INCOMING_REGNUM */
-
-/* If the incoming location is not a register, then you should define
-   `STRUCT_VALUE_INCOMING' as an expression for an RTX for where the called
-   function should find the value.  If it should find the value on the stack,
-   define this to create a `mem' which refers to the frame pointer.  A
-   definition of 0 means that the address is passed as an "invisible" first
-   argument.  */
-/* #define STRUCT_VALUE_INCOMING */
-
-/* Define this macro if the usual system convention on the target machine for
-   returning structures and unions is for the called function to return the
-   address of a static variable containing the value.
-
-   Do not define this if the usual system convention is for the caller to pass
-   an address to the subroutine.
-
-   This macro has effect in `-fpcc-struct-return' mode, but it does nothing
-   when you use `-freg-struct-return' mode.  */
-/* #define PCC_STATIC_STRUCT_RETURN */
-
-
-/* Caller-Saves Register Allocation */
-
-/* Define this macro if function calls on the target machine do not preserve
-   any registers; in other words, if `CALL_USED_REGISTERS' has 1 for all
-   registers.  This macro enables `-fcaller-saves' by default.  Eventually that
-   option will be enabled by default on all machines and both the option and
-   this macro will be eliminated.  */
-/* #define DEFAULT_CALLER_SAVES */
-
-/* A C expression to determine whether it is worthwhile to consider placing a
-   pseudo-register in a call-clobbered hard register and saving and restoring
-   it around each function call.  The expression should be 1 when this is worth
-   doing, and 0 otherwise.
-
-   If you don't define this macro, a default is used which is good on most
-   machines: `4 * CALLS < REFS'.  */
-/* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
-
-
-/* Function Entry and Exit */
-
-/* A C compound statement that outputs the assembler code for entry to a
-   function.  The prologue is responsible for setting up the stack frame,
-   initializing the frame pointer register, saving registers that must be
-   saved, and allocating SIZE additional bytes of storage for the local
-   variables.  SIZE is an integer.  FILE is a stdio stream to which the
-   assembler code should be output.
-
-   The label for the beginning of the function need not be output by this
-   macro.  That has already been done when the macro is run.
-
-   To determine which registers to save, the macro can refer to the array
-   `regs_ever_live': element R is nonzero if hard register R is used anywhere
-   within the function.  This implies the function prologue should save
-   register R, provided it is not one of the call-used registers.
-   (`FUNCTION_EPILOGUE' must likewise use `regs_ever_live'.)
-
-   On machines that have "register windows", the function entry code does not
-   save on the stack the registers that are in the windows, even if they are
-   supposed to be preserved by function calls; instead it takes appropriate
-   steps to "push" the register stack, if any non-call-used registers are used
-   in the function.
-
-   On machines where functions may or may not have frame-pointers, the function
-   entry code must vary accordingly; it must set up the frame pointer if one is
-   wanted, and not otherwise.  To determine whether a frame pointer is in
-   wanted, the macro can refer to the variable `frame_pointer_needed'.  The
-   variable's value will be 1 at run time in a function that needs a frame
-   pointer.  *Note Elimination::.
-
-   The function entry code is responsible for allocating any stack space
-   required for the function.  This stack space consists of the regions listed
-   below.  In most cases, these regions are allocated in the order listed, with
-   the last listed region closest to the top of the stack (the lowest address
-   if `STACK_GROWS_DOWNWARD' is defined, and the highest address if it is not
-   defined).  You can use a different order for a machine if doing so is more
-   convenient or required for compatibility reasons.  Except in cases where
-   required by standard or by a debugger, there is no reason why the stack
-   layout used by GCC need agree with that used by other compilers for a
-   machine.
-
-      * A region of `current_function_pretend_args_size' bytes of
-        uninitialized space just underneath the first argument
-        arriving on the stack.  (This may not be at the very start of
-        the allocated stack region if the calling sequence has pushed
-        anything else since pushing the stack arguments.  But
-        usually, on such machines, nothing else has been pushed yet,
-        because the function prologue itself does all the pushing.)
-        This region is used on machines where an argument may be
-        passed partly in registers and partly in memory, and, in some
-        cases to support the features in `varargs.h' and `stdargs.h'.
-
-      * An area of memory used to save certain registers used by the
-        function.  The size of this area, which may also include
-        space for such things as the return address and pointers to
-        previous stack frames, is machine-specific and usually
-        depends on which registers have been used in the function.
-        Machines with register windows often do not require a save
-        area.
-
-      * A region of at least SIZE bytes, possibly rounded up to an
-        allocation boundary, to contain the local variables of the
-        function.  On some machines, this region and the save area
-        may occur in the opposite order, with the save area closer to
-        the top of the stack.
-
-      * Optionally, when `ACCUMULATE_OUTGOING_ARGS' is defined, a
-        region of `current_function_outgoing_args_size' bytes to be
-        used for outgoing argument lists of the function.  *Note
-        Stack Arguments::.
-
-   Normally, it is necessary for the macros `FUNCTION_PROLOGUE' and
-   `FUNCTION_EPILOGUE' to treat leaf functions specially.  The C variable
-   `leaf_function' is nonzero for such a function.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) d30v_function_prologue (FILE, SIZE)
-
-/* Define this macro as a C expression that is nonzero if the return
-   instruction or the function epilogue ignores the value of the stack pointer;
-   in other words, if it is safe to delete an instruction to adjust the stack
-   pointer before a return from the function.
-
-   Note that this macro's value is relevant only for functions for which frame
-   pointers are maintained.  It is never safe to delete a final stack
-   adjustment in a function that has no frame pointer, and the compiler knows
-   this regardless of `EXIT_IGNORE_STACK'.  */
-/* #define EXIT_IGNORE_STACK */
-
-/* Define this macro as a C expression that is nonzero for registers
-   are used by the epilogue or the `return' pattern.  The stack and
-   frame pointer registers are already be assumed to be used as
-   needed.  */
-/* #define EPILOGUE_USES(REGNO) */
-
-/* A C compound statement that outputs the assembler code for exit from a
-   function.  The epilogue is responsible for restoring the saved registers and
-   stack pointer to their values when the function was called, and returning
-   control to the caller.  This macro takes the same arguments as the macro
-   `FUNCTION_PROLOGUE', and the registers to restore are determined from
-   `regs_ever_live' and `CALL_USED_REGISTERS' in the same way.
-
-   On some machines, there is a single instruction that does all the work of
-   returning from the function.  On these machines, give that instruction the
-   name `return' and do not define the macro `FUNCTION_EPILOGUE' at all.
-
-   Do not define a pattern named `return' if you want the `FUNCTION_EPILOGUE'
-   to be used.  If you want the target switches to control whether return
-   instructions or epilogues are used, define a `return' pattern with a
-   validity condition that tests the target switches appropriately.  If the
-   `return' pattern's validity condition is false, epilogues will be used.
-
-   On machines where functions may or may not have frame-pointers, the function
-   exit code must vary accordingly.  Sometimes the code for these two cases is
-   completely different.  To determine whether a frame pointer is wanted, the
-   macro can refer to the variable `frame_pointer_needed'.  The variable's
-   value will be 1 when compiling a function that needs a frame pointer.
-
-   Normally, `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' must treat leaf
-   functions specially.  The C variable `leaf_function' is nonzero for such a
-   function.  *Note Leaf Functions::.
-
-   On some machines, some functions pop their arguments on exit while others
-   leave that for the caller to do.  For example, the 68020 when given `-mrtd'
-   pops arguments in functions that take a fixed number of arguments.
-
-   Your definition of the macro `RETURN_POPS_ARGS' decides which functions pop
-   their own arguments.  `FUNCTION_EPILOGUE' needs to know what was decided.
-   The variable that is called `current_function_pops_args' is the number of
-   bytes of its arguments that a function should pop.  *Note Scalar Return::.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) d30v_function_epilogue (FILE, SIZE)
-
-/* Define this macro if the function epilogue contains delay slots to which
-   instructions from the rest of the function can be "moved".  The definition
-   should be a C expression whose value is an integer representing the number
-   of delay slots there.  */
-/* #define DELAY_SLOTS_FOR_EPILOGUE */
-
-/* A C expression that returns 1 if INSN can be placed in delay slot number N
-   of the epilogue.
-
-   The argument N is an integer which identifies the delay slot now being
-   considered (since different slots may have different rules of eligibility).
-   It is never negative and is always less than the number of epilogue delay
-   slots (what `DELAY_SLOTS_FOR_EPILOGUE' returns).  If you reject a particular
-   insn for a given delay slot, in principle, it may be reconsidered for a
-   subsequent delay slot.  Also, other insns may (at least in principle) be
-   considered for the so far unfilled delay slot.
-
-   The insns accepted to fill the epilogue delay slots are put in an
-   RTL list made with `insn_list' objects, stored in the variable
-   `current_function_epilogue_delay_list'.  The insn for the first
-   delay slot comes first in the list.  Your definition of the macro
-   `FUNCTION_EPILOGUE' should fill the delay slots by outputting the
-   insns in this list, usually by calling `final_scan_insn'.
-
-   You need not define this macro if you did not define
-   `DELAY_SLOTS_FOR_EPILOGUE'.  */
-/* #define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN, N) */
-
-/* A C compound statement that outputs the assembler code for a thunk function,
-   used to implement C++ virtual function calls with multiple inheritance.  The
-   thunk acts as a wrapper around a virtual function, adjusting the implicit
-   object parameter before handing control off to the real function.
-
-   First, emit code to add the integer DELTA to the location that contains the
-   incoming first argument.  Assume that this argument contains a pointer, and
-   is the one used to pass the `this' pointer in C++.  This is the incoming
-   argument *before* the function prologue, e.g. `%o0' on a sparc.  The
-   addition must preserve the values of all other incoming arguments.
-
-   After the addition, emit code to jump to FUNCTION, which is a
-   `FUNCTION_DECL'.  This is a direct pure jump, not a call, and does not touch
-   the return address.  Hence returning from FUNCTION will return to whoever
-   called the current `thunk'.
-
-   The effect must be as if FUNCTION had been called directly with the adjusted
-   first argument.  This macro is responsible for emitting all of the code for
-   a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not
-   invoked.
-
-   The THUNK_FNDECL is redundant.  (DELTA and FUNCTION have already been
-   extracted from it.)  It might possibly be useful on some targets, but
-   probably not.
-
-   If you do not define this macro, the target-independent code in the C++
-   frontend will generate a less efficient heavyweight thunk that calls
-   FUNCTION instead of jumping to it.  The generic approach does not support
-   varargs.  */
-/* #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) */
-
-
-/* Generating Code for Profiling.  */
-
-/* A C statement or compound statement to output to FILE some assembler code to
-   call the profiling subroutine `mcount'.  Before calling, the assembler code
-   must load the address of a counter variable into a register where `mcount'
-   expects to find the address.  The name of this variable is `LP' followed by
-   the number LABELNO, so you would generate the name using `LP%d' in a
-   `fprintf'.
-
-   The details of how the address should be passed to `mcount' are determined
-   by your operating system environment, not by GNU CC.  To figure them out,
-   compile a small program for profiling using the system's installed C
-   compiler and look at the assembler code that results.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) d30v_function_profiler (FILE, LABELNO)
-
-/* Define this macro if the code for function profiling should come before the
-   function prologue.  Normally, the profiling code comes after.  */
-/* #define PROFILE_BEFORE_PROLOGUE */
-
-/* A C statement or compound statement to output to FILE some assembler code to
-   initialize basic-block profiling for the current object module.  The global
-   compile flag `profile_block_flag' distingishes two profile modes.
-
-   profile_block_flag != 2'
-        Output code to call the subroutine `__bb_init_func' once per
-        object module, passing it as its sole argument the address of
-        a block allocated in the object module.
-
-        The name of the block is a local symbol made with this
-        statement:
-
-             ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
-
-        Of course, since you are writing the definition of
-        `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro,
-        you can take a short cut in the definition of this macro and
-        use the name that you know will result.
-
-        The first word of this block is a flag which will be nonzero
-        if the object module has already been initialized.  So test
-        this word first, and do not call `__bb_init_func' if the flag
-        is nonzero.  BLOCK_OR_LABEL contains a unique number which
-        may be used to generate a label as a branch destination when
-        `__bb_init_func' will not be called.
-
-        Described in assembler language, the code to be output looks
-        like:
-
-               cmp (LPBX0),0
-               bne local_label
-               parameter1 <- LPBX0
-               call __bb_init_func
-             local_label:
-
-   profile_block_flag == 2'
-        Output code to call the subroutine `__bb_init_trace_func' and
-        pass two parameters to it.  The first parameter is the same as
-        for `__bb_init_func'.  The second parameter is the number of
-        the first basic block of the function as given by
-        BLOCK_OR_LABEL.  Note that `__bb_init_trace_func' has to be
-        called, even if the object module has been initialized
-        already.
-
-        Described in assembler language, the code to be output looks
-        like:
-             parameter1 <- LPBX0
-             parameter2 <- BLOCK_OR_LABEL
-             call __bb_init_trace_func  */
-/* #define FUNCTION_BLOCK_PROFILER (FILE, LABELNO) */
-
-/* A C statement or compound statement to output to FILE some assembler code to
-   increment the count associated with the basic block number BLOCKNO.  The
-   global compile flag `profile_block_flag' distingishes two profile modes.
-
-   profile_block_flag != 2'
-        Output code to increment the counter directly.  Basic blocks
-        are numbered separately from zero within each compilation.
-        The count associated with block number BLOCKNO is at index
-        BLOCKNO in a vector of words; the name of this array is a
-        local symbol made with this statement:
-
-             ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
-
-        Of course, since you are writing the definition of
-        `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro,
-        you can take a short cut in the definition of this macro and
-        use the name that you know will result.
-
-        Described in assembler language, the code to be output looks
-        like:
-
-             inc (LPBX2+4*BLOCKNO)
-
-   profile_block_flag == 2'
-        Output code to initialize the global structure `__bb' and
-        call the function `__bb_trace_func', which will increment the
-        counter.
-
-        `__bb' consists of two words.  In the first word, the current
-        basic block number, as given by BLOCKNO, has to be stored.  In
-        the second word, the address of a block allocated in the
-        object module has to be stored.  The address is given by the
-        label created with this statement:
-
-             ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
-
-        Described in assembler language, the code to be output looks
-        like:
-             move BLOCKNO -> (__bb)
-             move LPBX0 -> (__bb+4)
-             call __bb_trace_func  */
-/* #define BLOCK_PROFILER(FILE, BLOCKNO) */
-
-/* A C statement or compound statement to output to FILE assembler
-   code to call function `__bb_trace_ret'.  The assembler code should
-   only be output if the global compile flag `profile_block_flag' ==
-   2.  This macro has to be used at every place where code for
-   returning from a function is generated (e.g. `FUNCTION_EPILOGUE').
-   Although you have to write the definition of `FUNCTION_EPILOGUE'
-   as well, you have to define this macro to tell the compiler, that
-   the proper call to `__bb_trace_ret' is produced.  */
-/* #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) */
-
-/* A C statement or compound statement to save all registers, which may be
-   clobbered by a function call, including condition codes.  The `asm'
-   statement will be mostly likely needed to handle this task.  Local labels in
-   the assembler code can be concatenated with the string ID, to obtain a
-   unique lable name.
-
-   Registers or condition codes clobbered by `FUNCTION_PROLOGUE' or
-   `FUNCTION_EPILOGUE' must be saved in the macros `FUNCTION_BLOCK_PROFILER',
-   `FUNCTION_BLOCK_PROFILER_EXIT' and `BLOCK_PROFILER' prior calling
-   `__bb_init_trace_func', `__bb_trace_ret' and `__bb_trace_func' respectively.  */
-/* #define MACHINE_STATE_SAVE(ID) */
-
-/* A C statement or compound statement to restore all registers, including
-   condition codes, saved by `MACHINE_STATE_SAVE'.
-
-   Registers or condition codes clobbered by `FUNCTION_PROLOGUE' or
-   `FUNCTION_EPILOGUE' must be restored in the macros
-   `FUNCTION_BLOCK_PROFILER', `FUNCTION_BLOCK_PROFILER_EXIT' and
-   `BLOCK_PROFILER' after calling `__bb_init_trace_func', `__bb_trace_ret' and
-   `__bb_trace_func' respectively.  */
-/* #define MACHINE_STATE_RESTORE(ID) */
-
-/* A C function or functions which are needed in the library to support block
-   profiling.  */
-/* #define BLOCK_PROFILER_CODE */
-
-
-/* Implementing the Varargs Macros.  */
-
-/* If defined, is a C expression that produces the machine-specific code for a
-   call to `__builtin_saveregs'.  This code will be moved to the very beginning
-   of the function, before any parameter access are made.  The return value of
-   this function should be an RTX that contains the value to use as the return
-   of `__builtin_saveregs'.
-
-   The argument ARGS is a `tree_list' containing the arguments that were passed
-   to `__builtin_saveregs'.
-
-   If this macro is not defined, the compiler will output an ordinary call to
-   the library function `__builtin_saveregs'.  */
-
-#define EXPAND_BUILTIN_SAVEREGS(ARGS) d30v_expand_builtin_saveregs (ARGS)
-
-/* This macro offers an alternative to using `__builtin_saveregs' and defining
-   the macro `EXPAND_BUILTIN_SAVEREGS'.  Use it to store the anonymous register
-   arguments into the stack so that all the arguments appear to have been
-   passed consecutively on the stack.  Once this is done, you can use the
-   standard implementation of varargs that works for machines that pass all
-   their arguments on the stack.
-
-   The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
-   the values that obtain after processing of the named arguments.  The
-   arguments MODE and TYPE describe the last named argument--its machine mode
-   and its data type as a tree node.
-
-   The macro implementation should do two things: first, push onto the stack
-   all the argument registers *not* used for the named arguments, and second,
-   store the size of the data thus pushed into the `int'-valued variable whose
-   name is supplied as the argument PRETEND_ARGS_SIZE.  The value that you
-   store here will serve as additional offset for setting up the stack frame.
-
-   Because you must generate code to push the anonymous arguments at compile
-   time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
-   useful on machines that have just a single category of argument register and
-   use it uniformly for all data types.
-
-   If the argument SECOND_TIME is nonzero, it means that the arguments of the
-   function are being analyzed for the second time.  This happens for an inline
-   function, which is not actually compiled until the end of the source file.
-   The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
-   this case.  */
-
-#define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \
-  d30v_setup_incoming_varargs (&ARGS_SO_FAR, (int) MODE, TYPE,		\
-			       &PRETEND_ARGS_SIZE, SECOND_TIME)
-
-/* Define this macro if the location where a function argument is passed
-   depends on whether or not it is a named argument.
-
-   This macro controls how the NAMED argument to `FUNCTION_ARG' is set for
-   varargs and stdarg functions.  With this macro defined, the NAMED argument
-   is always true for named arguments, and false for unnamed arguments.  If
-   this is not defined, but `SETUP_INCOMING_VARARGS' is defined, then all
-   arguments are treated as named.  Otherwise, all named arguments except the
-   last are treated as named.  */
-/* #define STRICT_ARGUMENT_NAMING */
-
-
-/* Trampolines for Nested Functions.  */
-
-/* A C statement to output, on the stream FILE, assembler code for a block of
-   data that contains the constant parts of a trampoline.  This code should not
-   include a label--the label is taken care of automatically.  */
-/* #define TRAMPOLINE_TEMPLATE(FILE) d30v_trampoline_template (FILE) */
-
-/* The name of a subroutine to switch to the section in which the trampoline
-   template is to be placed (*note Sections::.).  The default is a value of
-   `readonly_data_section', which places the trampoline in the section
-   containing read-only data.  */
-/* #define TRAMPOLINE_SECTION */
-
-/* A C expression for the size in bytes of the trampoline, as an integer.  */
-#define TRAMPOLINE_SIZE (d30v_trampoline_size ())
-
-/* Alignment required for trampolines, in bits.
-
-   If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for
-   aligning trampolines.  */
-#define TRAMPOLINE_ALIGNMENT 64
-
-/* A C statement to initialize the variable parts of a trampoline.  ADDR is an
-   RTX for the address of the trampoline; FNADDR is an RTX for the address of
-   the nested function; STATIC_CHAIN is an RTX for the static chain value that
-   should be passed to the function when it is called.  */
-#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
-  d30v_initialize_trampoline (ADDR, FNADDR, STATIC_CHAIN)
-
-/* A C expression to allocate run-time space for a trampoline.  The expression
-   value should be an RTX representing a memory reference to the space for the
-   trampoline.
-
-   If this macro is not defined, by default the trampoline is allocated as a
-   stack slot.  This default is right for most machines.  The exceptions are
-   machines where it is impossible to execute instructions in the stack area.
-   On such machines, you may have to implement a separate stack, using this
-   macro in conjunction with `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE'.
-
-   FP points to a data structure, a `struct function', which describes the
-   compilation status of the immediate containing function of the function
-   which the trampoline is for.  Normally (when `ALLOCATE_TRAMPOLINE' is not
-   defined), the stack slot for the trampoline is in the stack frame of this
-   containing function.  Other allocation strategies probably must do something
-   analogous with this information.  */
-/* #define ALLOCATE_TRAMPOLINE(FP) */
-
-/* Implementing trampolines is difficult on many machines because they have
-   separate instruction and data caches.  Writing into a stack location fails
-   to clear the memory in the instruction cache, so when the program jumps to
-   that location, it executes the old contents.
-
-   Here are two possible solutions.  One is to clear the relevant parts of the
-   instruction cache whenever a trampoline is set up.  The other is to make all
-   trampolines identical, by having them jump to a standard subroutine.  The
-   former technique makes trampoline execution faster; the latter makes
-   initialization faster.
-
-   To clear the instruction cache when a trampoline is initialized, define the
-   following macros which describe the shape of the cache.  */
-
-/* The total size in bytes of the cache.  */
-/* #define INSN_CACHE_SIZE */
-
-/* The length in bytes of each cache line.  The cache is divided into cache
-   lines which are disjoint slots, each holding a contiguous chunk of data
-   fetched from memory.  Each time data is brought into the cache, an entire
-   line is read at once.  The data loaded into a cache line is always aligned
-   on a boundary equal to the line size.  */
-/* #define INSN_CACHE_LINE_WIDTH */
-
-/* The number of alternative cache lines that can hold any particular memory
-   location.  */
-/* #define INSN_CACHE_DEPTH */
-
-/* Alternatively, if the machine has system calls or instructions to clear the
-   instruction cache directly, you can define the following macro.  */
-
-/* If defined, expands to a C expression clearing the *instruction cache* in
-   the specified interval.  If it is not defined, and the macro INSN_CACHE_SIZE
-   is defined, some generic code is generated to clear the cache.  The
-   definition of this macro would typically be a series of `asm' statements.
-   Both BEG and END are both pointer expressions.  */
-/* #define CLEAR_INSN_CACHE (BEG, END) */
-
-/* To use a standard subroutine, define the following macro.  In addition, you
-   must make sure that the instructions in a trampoline fill an entire cache
-   line with identical instructions, or else ensure that the beginning of the
-   trampoline code is always aligned at the same point in its cache line.  Look
-   in `m68k.h' as a guide.  */
-
-/* Define this macro if trampolines need a special subroutine to do their work.
-   The macro should expand to a series of `asm' statements which will be
-   compiled with GNU CC.  They go in a library function named
-   `__transfer_from_trampoline'.
-
-   If you need to avoid executing the ordinary prologue code of a compiled C
-   function when you jump to the subroutine, you can do so by placing a special
-   label of your own in the assembler code.  Use one `asm' statement to
-   generate an assembler label, and another to make the label global.  Then
-   trampolines can use that label to jump directly to your special assembler
-   code.  */
-/* #define TRANSFER_FROM_TRAMPOLINE */
-
-
-/* Implicit Calls to Library Routines */
-
-/* A C string constant giving the name of the function to call for
-   multiplication of one signed full-word by another.  If you do not define
-   this macro, the default name is used, which is `__mulsi3', a function
-   defined in `libgcc.a'.  */
-/* #define MULSI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for division of
-   one signed full-word by another.  If you do not define this macro, the
-   default name is used, which is `__divsi3', a function defined in `libgcc.a'.  */
-/* #define DIVSI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for division of
-   one unsigned full-word by another.  If you do not define this macro, the
-   default name is used, which is `__udivsi3', a function defined in
-   `libgcc.a'.  */
-/* #define UDIVSI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for the
-   remainder in division of one signed full-word by another.  If you do not
-   define this macro, the default name is used, which is `__modsi3', a function
-   defined in `libgcc.a'.  */
-/* #define MODSI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for the
-   remainder in division of one unsigned full-word by another.  If you do not
-   define this macro, the default name is used, which is `__umodsi3', a
-   function defined in `libgcc.a'.  */
-/* #define UMODSI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for
-   multiplication of one signed double-word by another.  If you do not define
-   this macro, the default name is used, which is `__muldi3', a function
-   defined in `libgcc.a'.  */
-/* #define MULDI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for division of
-   one signed double-word by another.  If you do not define this macro, the
-   default name is used, which is `__divdi3', a function defined in `libgcc.a'.  */
-/* #define DIVDI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for division of
-   one unsigned full-word by another.  If you do not define this macro, the
-   default name is used, which is `__udivdi3', a function defined in
-   `libgcc.a'.  */
-/* #define UDIVDI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for the
-   remainder in division of one signed double-word by another.  If you do not
-   define this macro, the default name is used, which is `__moddi3', a function
-   defined in `libgcc.a'.  */
-/* #define MODDI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for the
-   remainder in division of one unsigned full-word by another.  If you do not
-   define this macro, the default name is used, which is `__umoddi3', a
-   function defined in `libgcc.a'.  */
-/* #define UMODDI3_LIBCALL */
-
-/* Define this macro as a C statement that declares additional library routines
-   renames existing ones. `init_optabs' calls this macro after initializing all
-   the normal library routines.  */
-/* #define INIT_TARGET_OPTABS */
-
-/* The value of `EDOM' on the target machine, as a C integer constant
-   expression.  If you don't define this macro, GNU CC does not attempt to
-   deposit the value of `EDOM' into `errno' directly.  Look in
-   `/usr/include/errno.h' to find the value of `EDOM' on your system.
-
-   If you do not define `TARGET_EDOM', then compiled code reports domain errors
-   by calling the library function and letting it report the error.  If
-   mathematical functions on your system use `matherr' when there is an error,
-   then you should leave `TARGET_EDOM' undefined so that `matherr' is used
-   normally.  */
-/* #define TARGET_EDOM */
-
-/* Define this macro as a C expression to create an rtl expression that refers
-   to the global "variable" `errno'.  (On certain systems, `errno' may not
-   actually be a variable.)  If you don't define this macro, a reasonable
-   default is used.  */
-/* #define GEN_ERRNO_RTX */
-
-/* Define this macro if GNU CC should generate calls to the System V (and ANSI
-   C) library functions `memcpy' and `memset' rather than the BSD functions
-   `bcopy' and `bzero'.
-
-   Defined in svr4.h.  */
-/* #define TARGET_MEM_FUNCTIONS */
-
-/* Define this macro if only `float' arguments cannot be passed to library
-   routines (so they must be converted to `double').  This macro affects both
-   how library calls are generated and how the library routines in `libgcc1.c'
-   accept their arguments.  It is useful on machines where floating and fixed
-   point arguments are passed differently, such as the i860.  */
-/* #define LIBGCC_NEEDS_DOUBLE */
-
-/* Define this macro to override the type used by the library routines to pick
-   up arguments of type `float'.  (By default, they use a union of `float' and
-   `int'.)
-
-   The obvious choice would be `float'--but that won't work with traditional C
-   compilers that expect all arguments declared as `float' to arrive as
-   `double'.  To avoid this conversion, the library routines ask for the value
-   as some other type and then treat it as a `float'.
-
-   On some systems, no other type will work for this.  For these systems, you
-   must use `LIBGCC_NEEDS_DOUBLE' instead, to force conversion of the values
-   `double' before they are passed.  */
-/* #define FLOAT_ARG_TYPE */
-
-/* Define this macro to override the way library routines redesignate a `float'
-   argument as a `float' instead of the type it was passed as.  The default is
-   an expression which takes the `float' field of the union.  */
-/* #define FLOATIFY(PASSED_VALUE) */
-
-/* Define this macro to override the type used by the library routines to
-   return values that ought to have type `float'.  (By default, they use
-   `int'.)
-
-   The obvious choice would be `float'--but that won't work with traditional C
-   compilers gratuitously convert values declared as `float' into `double'.  */
-/* #define FLOAT_VALUE_TYPE */
-
-/* Define this macro to override the way the value of a `float'-returning
-   library routine should be packaged in order to return it.  These functions
-   are actually declared to return type `FLOAT_VALUE_TYPE' (normally `int').
-
-   These values can't be returned as type `float' because traditional C
-   compilers would gratuitously convert the value to a `double'.
-
-   A local variable named `intify' is always available when the macro `INTIFY'
-   is used.  It is a union of a `float' field named `f' and a field named `i'
-   whose type is `FLOAT_VALUE_TYPE' or `int'.
-
-   If you don't define this macro, the default definition works by copying the
-   value through that union.  */
-/* #define INTIFY(FLOAT_VALUE) */
-
-/* Define this macro as the name of the data type corresponding to `SImode' in
-   the system's own C compiler.
-
-   You need not define this macro if that type is `long int', as it usually is.  */
-/* #define nongcc_SI_type */
-
-/* Define this macro as the name of the data type corresponding to the
-   word_mode in the system's own C compiler.
-
-   You need not define this macro if that type is `long int', as it usually is.  */
-/* #define nongcc_word_type */
-
-/* Define these macros to supply explicit C statements to carry out various
-   arithmetic operations on types `float' and `double' in the library routines
-   in `libgcc1.c'.  See that file for a full list of these macros and their
-   arguments.
-
-   On most machines, you don't need to define any of these macros, because the
-   C compiler that comes with the system takes care of doing them.  */
-/* #define perform_... */
-
-/* Define this macro to generate code for Objective C message sending using the
-   calling convention of the NeXT system.  This calling convention involves
-   passing the object, the selector and the method arguments all at once to the
-   method-lookup library function.
-
-   The default calling convention passes just the object and the selector to
-   the lookup function, which returns a pointer to the method.  */
-/* #define NEXT_OBJC_RUNTIME */
-
-
-/* Addressing Modes */
-
-/* Define this macro if the machine supports post-increment addressing.  */
-#define HAVE_POST_INCREMENT 1
-
-/* Similar for other kinds of addressing.  */
-/* #define HAVE_PRE_INCREMENT 0 */
-#define HAVE_POST_DECREMENT 1
-/* #define HAVE_PRE_DECREMENT 0 */
-
-/* A C expression that is 1 if the RTX X is a constant which is a valid
-   address.  On most machines, this can be defined as `CONSTANT_P (X)', but a
-   few machines are more restrictive in which constant addresses are supported.
-
-   `CONSTANT_P' accepts integer-values expressions whose values are not
-   explicitly known, such as `symbol_ref', `label_ref', and `high' expressions
-   and `const' arithmetic expressions, in addition to `const_int' and
-   `const_double' expressions.  */
-#define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
-
-/* A number, the maximum number of registers that can appear in a valid memory
-   address.  Note that it is up to you to specify a value equal to the maximum
-   number that `GO_IF_LEGITIMATE_ADDRESS' would ever accept.  */
-#define MAX_REGS_PER_ADDRESS 2
-
-/* A C compound statement with a conditional `goto LABEL;' executed if X (an
-   RTX) is a legitimate memory address on the target machine for a memory
-   operand of mode MODE.
-
-   It usually pays to define several simpler macros to serve as subroutines for
-   this one.  Otherwise it may be too complicated to understand.
-
-   This macro must exist in two variants: a strict variant and a non-strict
-   one.  The strict variant is used in the reload pass.  It must be defined so
-   that any pseudo-register that has not been allocated a hard register is
-   considered a memory reference.  In contexts where some kind of register is
-   required, a pseudo-register with no hard register must be rejected.
-
-   The non-strict variant is used in other passes.  It must be defined to
-   accept all pseudo-registers in every context where some kind of register is
-   required.
-
-   Compiler source files that want to use the strict variant of this macro
-   define the macro `REG_OK_STRICT'.  You should use an `#ifdef REG_OK_STRICT'
-   conditional to define the strict variant in that case and the non-strict
-   variant otherwise.
-
-   Subroutines to check for acceptable registers for various purposes (one for
-   base registers, one for index registers, and so on) are typically among the
-   subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'.  Then only these
-   subroutine macros need have two variants; the higher levels of macros may be
-   the same whether strict or not.
-
-   Normally, constant addresses which are the sum of a `symbol_ref' and an
-   integer are stored inside a `const' RTX to mark them as constant.
-   Therefore, there is no need to recognize such sums specifically as
-   legitimate addresses.  Normally you would simply recognize any `const' as
-   legitimate.
-
-   Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
-   are not marked with `const'.  It assumes that a naked `plus' indicates
-   indexing.  If so, then you *must* reject such naked constant sums as
-   illegitimate addresses, so that none of them will be given to
-   `PRINT_OPERAND_ADDRESS'.
-
-   On some machines, whether a symbolic address is legitimate depends on the
-   section that the address refers to.  On these machines, define the macro
-   `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
-   then check for it here.  When you see a `const', you will have to look
-   inside it to find the `symbol_ref' in order to determine the section.  *Note
-   Assembler Format::.
-
-   The best way to modify the name string is by adding text to the beginning,
-   with suitable punctuation to prevent any ambiguity.  Allocate the new name
-   in `saveable_obstack'.  You will have to modify `ASM_OUTPUT_LABELREF' to
-   remove and decode the added text and output the name accordingly, and define
-   `STRIP_NAME_ENCODING' to access the original name string.
-
-   You can check the information stored here into the `symbol_ref' in the
-   definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
-   `PRINT_OPERAND_ADDRESS'.  */
-
-#ifdef	REG_OK_STRICT
-#define REG_OK_STRICT_P 1
-#else
-#define REG_OK_STRICT_P 0
-#endif
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-do {									\
-    if (d30v_legitimate_address_p ((int)MODE, X, REG_OK_STRICT_P))	\
-      goto ADDR;							\
-} while (0)
-
-/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
-   use as a base register.  For hard registers, it should always accept those
-   which the hardware permits and reject the others.  Whether the macro accepts
-   or rejects pseudo registers must be controlled by `REG_OK_STRICT' as
-   described above.  This usually requires two variant definitions, of which
-   `REG_OK_STRICT' controls the one actually used.  */
-
-#ifdef REG_OK_STRICT
-#define REG_OK_FOR_BASE_P(X) (GPR_P (REGNO (X)))
-#else
-#define REG_OK_FOR_BASE_P(X) (GPR_OR_PSEUDO_P (REGNO (X)))
-#endif
-
-/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
-   use as an index register.
-
-   The difference between an index register and a base register is that the
-   index register may be scaled.  If an address involves the sum of two
-   registers, neither one of them scaled, then either one may be labeled the
-   "base" and the other the "index"; but whichever labeling is used must fit
-   the machine's constraints of which registers may serve in each capacity.
-   The compiler will try both labelings, looking for one that is valid, and
-   will reload one or both registers only if neither labeling works.  */
-
-#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
-
-/* A C compound statement that attempts to replace X with a valid memory
-   address for an operand of mode MODE.  WIN will be a C statement label
-   elsewhere in the code; the macro definition may use
-
-        GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
-
-   to avoid further processing if the address has become legitimate.
-
-   X will always be the result of a call to `break_out_memory_refs', and OLDX
-   will be the operand that was given to that function to produce X.
-
-   The code generated by this macro should not alter the substructure of X.  If
-   it transforms X into a more legitimate form, it should assign X (which will
-   always be a C variable) a new value.
-
-   It is not necessary for this macro to come up with a legitimate address.
-   The compiler has standard ways of doing so in all cases.  In fact, it is
-   safe for this macro to do nothing.  But often a machine-dependent strategy
-   can generate better code.  */
-
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)				\
-do {									\
-  rtx y = d30v_legitimize_address (X, OLDX, (int)MODE, REG_OK_STRICT_P); \
-  if (y)								\
-    {									\
-      X = y;								\
-      GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);				\
-    }									\
-} while (0)
-
-/* A C statement or compound statement with a conditional `goto LABEL;'
-   executed if memory address X (an RTX) can have different meanings depending
-   on the machine mode of the memory reference it is used for or if the address
-   is valid for some modes but not others.
-
-   Autoincrement and autodecrement addresses typically have mode-dependent
-   effects because the amount of the increment or decrement is the size of the
-   operand being addressed.  Some machines have other mode-dependent addresses.
-   Many RISC machines have no mode-dependent addresses.
-
-   You may assume that ADDR is a valid address for the machine.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)			\
-do {									\
-  if (d30v_mode_dependent_address_p (ADDR))				\
-    goto LABEL;								\
-} while (0)								\
-
-/* A C expression that is nonzero if X is a legitimate constant for an
-   immediate operand on the target machine.  You can assume that X satisfies
-   `CONSTANT_P', so you need not check this.  In fact, `1' is a suitable
-   definition for this macro on machines where anything `CONSTANT_P' is valid.  */
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-
-/* Condition Code Status */
-
-/* C code for a data type which is used for declaring the `mdep' component of
-   `cc_status'.  It defaults to `int'.
-
-   This macro is not used on machines that do not use `cc0'.  */
-/* #define CC_STATUS_MDEP */
-
-/* A C expression to initialize the `mdep' field to "empty".  The default
-   definition does nothing, since most machines don't use the field anyway.  If
-   you want to use the field, you should probably define this macro to
-   initialize it.
-
-   This macro is not used on machines that do not use `cc0'.  */
-/* #define CC_STATUS_MDEP_INIT */
-
-/* A C compound statement to set the components of `cc_status' appropriately
-   for an insn INSN whose body is EXP.  It is this macro's responsibility to
-   recognize insns that set the condition code as a byproduct of other activity
-   as well as those that explicitly set `(cc0)'.
-
-   This macro is not used on machines that do not use `cc0'.
-
-   If there are insns that do not set the condition code but do alter other
-   machine registers, this macro must check to see whether they invalidate the
-   expressions that the condition code is recorded as reflecting.  For example,
-   on the 68000, insns that store in address registers do not set the condition
-   code, which means that usually `NOTICE_UPDATE_CC' can leave `cc_status'
-   unaltered for such insns.  But suppose that the previous insn set the
-   condition code based on location `a4@(102)' and the current insn stores a
-   new value in `a4'.  Although the condition code is not changed by this, it
-   will no longer be true that it reflects the contents of `a4@(102)'.
-   Therefore, `NOTICE_UPDATE_CC' must alter `cc_status' in this case to say
-   that nothing is known about the condition code value.
-
-   The definition of `NOTICE_UPDATE_CC' must be prepared to deal with the
-   results of peephole optimization: insns whose patterns are `parallel' RTXs
-   containing various `reg', `mem' or constants which are just the operands.
-   The RTL structure of these insns is not sufficient to indicate what the
-   insns actually do.  What `NOTICE_UPDATE_CC' should do when it sees one is
-   just to run `CC_STATUS_INIT'.
-
-   A possible definition of `NOTICE_UPDATE_CC' is to call a function that looks
-   at an attribute (*note Insn Attributes::.) named, for example, `cc'.  This
-   avoids having detailed information about patterns in two places, the `md'
-   file and in `NOTICE_UPDATE_CC'.  */
-/* #define NOTICE_UPDATE_CC(EXP, INSN) */
-
-/* A list of names to be used for additional modes for condition code values in
-   registers (*note Jump Patterns::.).  These names are added to `enum
-   machine_mode' and all have class `MODE_CC'.  By convention, they should
-   start with `CC' and end with `mode'.
-
-   You should only define this macro if your machine does not use `cc0' and
-   only if additional modes are required.  */
-/* #define EXTRA_CC_MODES */
-
-/* A list of C strings giving the names for the modes listed in
-   `EXTRA_CC_MODES'.  For example, the Sparc defines this macro and
-   `EXTRA_CC_MODES' as
-
-        #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
-        #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
-
-   This macro is not required if `EXTRA_CC_MODES' is not defined.  */
-/* #define EXTRA_CC_NAMES */
-
-/* Returns a mode from class `MODE_CC' to be used when comparison operation
-   code OP is applied to rtx X and Y.  For example, on the Sparc,
-   `SELECT_CC_MODE' is defined as (see *note Jump Patterns::.  for a
-   description of the reason for this definition)
-
-        #define SELECT_CC_MODE(OP,X,Y) \
-          (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT          \
-           ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode)    \
-           : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS    \
-               || GET_CODE (X) == NEG) \
-              ? CC_NOOVmode : CCmode))
-
-   You need not define this macro if `EXTRA_CC_MODES' is not defined.  */
-/* #define SELECT_CC_MODE(OP, X, Y) */
-
-/* One some machines not all possible comparisons are defined, but you can
-   convert an invalid comparison into a valid one.  For example, the Alpha does
-   not have a `GT' comparison, but you can use an `LT' comparison instead and
-   swap the order of the operands.
-
-   On such machines, define this macro to be a C statement to do any required
-   conversions.  CODE is the initial comparison code and OP0 and OP1 are the
-   left and right operands of the comparison, respectively.  You should modify
-   CODE, OP0, and OP1 as required.
-
-   GNU CC will not assume that the comparison resulting from this macro is
-   valid but will see if the resulting insn matches a pattern in the `md' file.
-
-   You need not define this macro if it would never change the comparison code
-   or operands.  */
-/* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
-
-/* A C expression whose value is one if it is always safe to reverse a
-   comparison whose mode is MODE.  If `SELECT_CC_MODE' can ever return MODE for
-   a floating-point inequality comparison, then `REVERSIBLE_CC_MODE (MODE)'
-   must be zero.
-
-   You need not define this macro if it would always returns zero or if the
-   floating-point format is anything other than `IEEE_FLOAT_FORMAT'.  For
-   example, here is the definition used on the Sparc, where floating-point
-   inequality comparisons are always given `CCFPEmode':
-
-        #define REVERSIBLE_CC_MODE(MODE)  ((MODE) != CCFPEmode)  */
-/* #define REVERSIBLE_CC_MODE(MODE) */
-
-
-/* Describing Relative Costs of Operations */
-
-/* A part of a C `switch' statement that describes the relative costs of
-   constant RTL expressions.  It must contain `case' labels for expression
-   codes `const_int', `const', `symbol_ref', `label_ref' and `const_double'.
-   Each case must ultimately reach a `return' statement to return the relative
-   cost of the use of that kind of constant value in an expression.  The cost
-   may depend on the precise value of the constant, which is available for
-   examination in X, and the rtx code of the expression in which it is
-   contained, found in OUTER_CODE.
-
-   CODE is the expression code--redundant, since it can be obtained with
-   `GET_CODE (X)'.  */
-
-/* On the d30v, consider operatnds that fit in a short instruction very
-   cheap.  However, at this time, it causes cse to generate incorrect
-   code, so disable it for now.  */
-#if 0
-#define CONST_COSTS(X, CODE, OUTER_CODE)				\
-  case CONST_INT:							\
-    if (IN_RANGE_P (INTVAL (X), 0, 31))					\
-      return 0;								\
-    else if ((OUTER_CODE) == LEU && (OUTER_CODE) == LTU			\
-	     && (OUTER_CODE) == GEU && (OUTER_CODE) == GTU)		\
-      return IN_RANGE_P (INTVAL (X), 32, 63) ? 0 : COSTS_N_INSNS (2);	\
-    else								\
-      return IN_RANGE_P (INTVAL (X), -31, -1) ? 0 : COSTS_N_INSNS (2);	\
-  case SYMBOL_REF:							\
-  case LABEL_REF:							\
-  case CONST:								\
-    return COSTS_N_INSNS (2);						\
-  case CONST_DOUBLE:							\
-    return COSTS_N_INSNS ((GET_MODE (X) == SFmode) ? 2 : 4);
-#else
-#define CONST_COSTS(X, CODE, OUTER_CODE)
-#endif
-
-/* Like `CONST_COSTS' but applies to nonconstant RTL expressions.  This can be
-   used, for example, to indicate how costly a multiply instruction is.  In
-   writing this macro, you can use the construct `COSTS_N_INSNS (N)' to specify
-   a cost equal to N fast instructions.  OUTER_CODE is the code of the
-   expression in which X is contained.
-
-   This macro is optional; do not define it if the default cost assumptions are
-   adequate for the target machine.  */
-#define RTX_COSTS(X, CODE, OUTER_CODE)					\
-  case MULT:								\
-    return COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT		\
-			   && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)	\
-			  ? 1 : 2);
-
-/* An expression giving the cost of an addressing mode that contains ADDRESS.
-   If not defined, the cost is computed from the ADDRESS expression and the
-   `CONST_COSTS' values.
-
-   For most CISC machines, the default cost is a good approximation of the true
-   cost of the addressing mode.  However, on RISC machines, all instructions
-   normally have the same length and execution time.  Hence all addresses will
-   have equal costs.
-
-   In cases where more than one form of an address is known, the form with the
-   lowest cost will be used.  If multiple forms have the same, lowest, cost,
-   the one that is the most complex will be used.
-
-   For example, suppose an address that is equal to the sum of a register and a
-   constant is used twice in the same basic block.  When this macro is not
-   defined, the address will be computed in a register and memory references
-   will be indirect through that register.  On machines where the cost of the
-   addressing mode containing the sum is no higher than that of a simple
-   indirect reference, this will produce an additional instruction and possibly
-   require an additional register.  Proper specification of this macro
-   eliminates this overhead for such machines.
-
-   Similar use of this macro is made in strength reduction of loops.
-
-   ADDRESS need not be valid as an address.  In such a case, the cost is not
-   relevant and can be any value; invalid addresses need not be assigned a
-   different cost.
-
-   On machines where an address involving more than one register is as cheap as
-   an address computation involving only one register, defining `ADDRESS_COST'
-   to reflect this can cause two registers to be live over a region of code
-   where only one would have been if `ADDRESS_COST' were not defined in that
-   manner.  This effect should be considered in the definition of this macro.
-   Equivalent costs should probably only be given to addresses with different
-   numbers of registers on machines with lots of registers.
-
-   This macro will normally either not be defined or be defined as a constant.  */
-#define ADDRESS_COST(ADDRESS) 0
-
-/* A C expression for the cost of moving data from a register in class FROM to
-   one in class TO.  The classes are expressed using the enumeration values
-   such as `GENERAL_REGS'.  A value of 4 is the default; other values are
-   interpreted relative to that.
-
-   It is not required that the cost always equal 2 when FROM is the same as TO;
-   on some machines it is expensive to move between registers if they are not
-   general registers.
-
-   If reload sees an insn consisting of a single `set' between two hard
-   registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
-   value of 2, reload does not check to ensure that the constraints of the insn
-   are met.  Setting a cost of other than 2 will allow reload to verify that
-   the constraints are met.  You should do this if the `movM' pattern's
-   constraints do not allow such copying.  */
-
-#define REGISTER_MOVE_COST(FROM, TO)					\
-  (((FROM) != GPR_REGS && (FROM) != EVEN_REGS				\
-   && (TO) != GPR_REGS && (TO) != EVEN_REGS) ? 4 : 2)
-
-/* A C expression for the cost of moving data of mode M between a register and
-   memory.  A value of 2 is the default; this cost is relative to those in
-   `REGISTER_MOVE_COST'.
-
-   If moving between registers and memory is more expensive than between two
-   registers, you should define this macro to express the relative cost.  */
-#define MEMORY_MOVE_COST(M,C,I) 4
-
-/* A C expression for the cost of a branch instruction.  A value of 1 is the
-   default; other values are interpreted relative to that.  */
-
-#define BRANCH_COST d30v_branch_cost
-
-#define D30V_DEFAULT_BRANCH_COST 2
-
-/* Values of the -mbranch-cost=n string.  */
-extern int d30v_branch_cost;
-extern char *d30v_branch_cost_string;
-
-/* Here are additional macros which do not specify precise relative costs, but
-   only that certain actions are more expensive than GNU CC would ordinarily
-   expect.  */
-
-/* Define this macro as a C expression which is nonzero if accessing less than
-   a word of memory (i.e. a `char' or a `short') is no faster than accessing a
-   word of memory, i.e., if such access require more than one instruction or if
-   there is no difference in cost between byte and (aligned) word loads.
-
-   When this macro is not defined, the compiler will access a field by finding
-   the smallest containing object; when it is defined, a fullword load will be
-   used if alignment permits.  Unless bytes accesses are faster than word
-   accesses, using word accesses is preferable since it may eliminate
-   subsequent memory access if subsequent accesses occur to other fields in the
-   same word of the structure, but to different bytes.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* Define this macro if zero-extension (of a `char' or `short' to an `int') can
-   be done faster if the destination is a register that is known to be zero.
-
-   If you define this macro, you must have instruction patterns that recognize
-   RTL structures like this:
-
-        (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
-   and likewise for `HImode'.  */
-#define SLOW_ZERO_EXTEND 0
-
-/* Define this macro to be the value 1 if unaligned accesses have a cost many
-   times greater than aligned accesses, for example if they are emulated in a
-   trap handler.
-
-   When this macro is non-zero, the compiler will act as if `STRICT_ALIGNMENT'
-   were non-zero when generating code for block moves.  This can cause
-   significantly more instructions to be produced.  Therefore, do not set this
-   macro non-zero if unaligned accesses only add a cycle or two to the time for
-   a memory access.
-
-   If the value of this macro is always zero, it need not be defined.  */
-/* #define SLOW_UNALIGNED_ACCESS */
-
-/* Define this macro to inhibit strength reduction of memory addresses.  (On
-   some machines, such strength reduction seems to do harm rather than good.)  */
-/* #define DONT_REDUCE_ADDR */
-
-/* The number of scalar move insns which should be generated instead of a
-   string move insn or a library call.  Increasing the value will always make
-   code faster, but eventually incurs high cost in increased code size.
-
-   If you don't define this, a reasonable default is used.  */
-/* #define MOVE_RATIO */
-
-/* Define this macro if it is as good or better to call a constant function
-   address than to call an address kept in a register.  */
-#define NO_FUNCTION_CSE
-
-/* Define this macro if it is as good or better for a function to call itself
-   with an explicit address than to call an address kept in a register.  */
-/* #define NO_RECURSIVE_FUNCTION_CSE */
-
-/* A C statement (sans semicolon) to update the integer variable COST based on
-   the relationship between INSN that is dependent on DEP_INSN through the
-   dependence LINK.  The default is to make no adjustment to COST.  This can be
-   used for example to specify to the scheduler that an output- or
-   anti-dependence does not incur the same cost as a data-dependence.  */
-
-#define ADJUST_COST(INSN,LINK,DEP_INSN,COST)				\
-  (COST) = d30v_adjust_cost (INSN, LINK, DEP_INSN, COST)
-
-/* A C statement (sans semicolon) to update the integer scheduling
-   priority `INSN_PRIORITY(INSN)'.  Reduce the priority to execute
-   the INSN earlier, increase the priority to execute INSN later.
-   Do not define this macro if you do not need to adjust the
-   scheduling priorities of insns.  */
-/* #define ADJUST_PRIORITY (INSN) */
-
-/* Macro to determine whether the Haifa scheduler is used.  */
-#ifdef HAIFA
-#define HAIFA_P 1
-#else
-#define HAIFA_P 0
-#endif
-
-
-/* Dividing the output into sections.  */
-
-/* A C expression whose value is a string containing the assembler operation
-   that should precede instructions and read-only data.  Normally `".text"' is
-   right.  */
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* A C expression whose value is a string containing the assembler operation to
-   identify the following data as writable initialized data.  Normally
-   `".data"' is right.  */
-#define DATA_SECTION_ASM_OP ".data"
-
-/* if defined, a C expression whose value is a string containing the assembler
-   operation to identify the following data as shared data.  If not defined,
-   `DATA_SECTION_ASM_OP' will be used.  */
-/* #define SHARED_SECTION_ASM_OP */
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as
-   uninitialized global data.  If not defined, and neither
-   `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
-   uninitialized global data will be output in the data section if
-   `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
-   used.  */
-#define BSS_SECTION_ASM_OP ".bss"
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as
-   uninitialized global shared data.  If not defined, and
-   `BSS_SECTION_ASM_OP' is, the latter will be used.  */
-/* #define SHARED_BSS_SECTION_ASM_OP */
-
-/* A list of names for sections other than the standard two, which are
-   `in_text' and `in_data'.  You need not define this macro on a system with no
-   other sections (that GCC needs to use).
-
-   Defined in svr4.h.  */
-/* #define EXTRA_SECTIONS */
-
-/* One or more functions to be defined in `varasm.c'.  These functions should
-   do jobs analogous to those of `text_section' and `data_section', for your
-   additional sections.  Do not define this macro if you do not define
-   `EXTRA_SECTIONS'.
-
-   Defined in svr4.h.  */
-/* #define EXTRA_SECTION_FUNCTIONS */
-
-/* On most machines, read-only variables, constants, and jump tables are placed
-   in the text section.  If this is not the case on your machine, this macro
-   should be defined to be the name of a function (either `data_section' or a
-   function defined in `EXTRA_SECTIONS') that switches to the section to be
-   used for read-only items.
-
-   If these items should be placed in the text section, this macro should not
-   be defined.  */
-/* #define READONLY_DATA_SECTION */
-
-/* A C statement or statements to switch to the appropriate section for output
-   of EXP.  You can assume that EXP is either a `VAR_DECL' node or a constant
-   of some sort.  RELOC indicates whether the initial value of EXP requires
-   link-time relocations.  Select the section by calling `text_section' or one
-   of the alternatives for other sections.
-
-   Do not define this macro if you put all read-only variables and constants in
-   the read-only data section (usually the text section).
-
-   Defined in svr4.h.  */
-/* #define SELECT_SECTION(EXP, RELOC) */
-
-/* A C statement or statements to switch to the appropriate section for output
-   of RTX in mode MODE.  You can assume that RTX is some kind of constant in
-   RTL.  The argument MODE is redundant except in the case of a `const_int'
-   rtx.  Select the section by calling `text_section' or one of the
-   alternatives for other sections.
-
-   Do not define this macro if you put all constants in the read-only data
-   section.
-
-   Defined in svr4.h.  */
-/* #define SELECT_RTX_SECTION(MODE, RTX) */
-
-/* Define this macro if jump tables (for `tablejump' insns) should be output in
-   the text section, along with the assembler instructions.  Otherwise, the
-   readonly data section is used.
-
-   This macro is irrelevant if there is no separate readonly data section.  */
-/* #define JUMP_TABLES_IN_TEXT_SECTION */
-
-/* Define this macro if references to a symbol must be treated differently
-   depending on something about the variable or function named by the symbol
-   (such as what section it is in).
-
-   The macro definition, if any, is executed immediately after the rtl for DECL
-   has been created and stored in `DECL_RTL (DECL)'.  The value of the rtl will
-   be a `mem' whose address is a `symbol_ref'.
-
-   The usual thing for this macro to do is to record a flag in the `symbol_ref'
-   (such as `SYMBOL_REF_FLAG') or to store a modified name string in the
-   `symbol_ref' (if one bit is not enough information).  */
-/* #define ENCODE_SECTION_INFO(DECL) */
-
-/* Decode SYM_NAME and store the real name part in VAR, sans the characters
-   that encode section info.  Define this macro if `ENCODE_SECTION_INFO' alters
-   the symbol's name string.  */
-/* #define STRIP_NAME_ENCODING(VAR, SYM_NAME) */
-
-/* A C expression which evaluates to true if DECL should be placed
-   into a unique section for some target-specific reason.  If you do
-   not define this macro, the default is `0'.  Note that the flag
-   `-ffunction-sections' will also cause functions to be placed into
-   unique sections.
-
-   Defined in svr4.h.  */
-/* #define UNIQUE_SECTION_P(DECL) */
-
-/* A C statement to build up a unique section name, expressed as a
-   STRING_CST node, and assign it to `DECL_SECTION_NAME (DECL)'.
-   RELOC indicates whether the initial value of EXP requires
-   link-time relocations.  If you do not define this macro, GNU CC
-   will use the symbol name prefixed by `.' as the section name.
-
-   Defined in svr4.h.  */
-/* #define UNIQUE_SECTION(DECL, RELOC) */
-
-
-/* Position Independent Code.  */
-
-/* The register number of the register used to address a table of static data
-   addresses in memory.  In some cases this register is defined by a
-   processor's "application binary interface" (ABI).  When this macro is
-   defined, RTL is generated for this register once, as with the stack pointer
-   and frame pointer registers.  If this macro is not defined, it is up to the
-   machine-dependent files to allocate such a register (if necessary).  */
-/* #define PIC_OFFSET_TABLE_REGNUM */
-
-/* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
-   clobbered by calls.  Do not define this macro if `PIC_OFFSET_TABLE_REGNUM'
-   is not defined.  */
-/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
-
-/* By generating position-independent code, when two different programs (A and
-   B) share a common library (libC.a), the text of the library can be shared
-   whether or not the library is linked at the same address for both programs.
-   In some of these environments, position-independent code requires not only
-   the use of different addressing modes, but also special code to enable the
-   use of these addressing modes.
-
-   The `FINALIZE_PIC' macro serves as a hook to emit these special codes once
-   the function is being compiled into assembly code, but not before.  (It is
-   not done before, because in the case of compiling an inline function, it
-   would lead to multiple PIC prologues being included in functions which used
-   inline functions and were compiled to assembly language.)  */
-/* #define FINALIZE_PIC */
-
-/* A C expression that is nonzero if X is a legitimate immediate operand on the
-   target machine when generating position independent code.  You can assume
-   that X satisfies `CONSTANT_P', so you need not check this.  You can also
-   assume FLAG_PIC is true, so you need not check it either.  You need not
-   define this macro if all constants (including `SYMBOL_REF') can be immediate
-   operands when generating position independent code.  */
-/* #define LEGITIMATE_PIC_OPERAND_P(X) */
-
-
-/* The Overall Framework of an Assembler File.  */
-
-/* A C expression which outputs to the stdio stream STREAM some appropriate
-   text to go at the start of an assembler file.
-
-   Normally this macro is defined to output a line containing `#NO_APP', which
-   is a comment that has no effect on most assemblers but tells the GNU
-   assembler that it can save time by not checking for certain assembler
-   constructs.
-
-   On systems that use SDB, it is necessary to output certain commands; see
-   `attasm.h'.
-
-   Defined in svr4.h.  */
-
-/* #define ASM_FILE_START(STREAM) \
-  output_file_directive ((STREAM), main_input_filename) */
-
-/* A C expression which outputs to the stdio stream STREAM some appropriate
-   text to go at the end of an assembler file.
-
-   If this macro is not defined, the default is to output nothing special at
-   the end of the file.  Most systems don't require any definition.
-
-   On systems that use SDB, it is necessary to output certain commands; see
-   `attasm.h'.
-
-   Defined in svr4.h.  */
-/* #define ASM_FILE_END(STREAM) */
-
-/* A C statement to output assembler commands which will identify the object
-   file as having been compiled with GNU CC (or another GNU compiler).
-
-   If you don't define this macro, the string `gcc_compiled.:' is output.  This
-   string is calculated to define a symbol which, on BSD systems, will never be
-   defined for any other reason.  GDB checks for the presence of this symbol
-   when reading the symbol table of an executable.
-
-   On non-BSD systems, you must arrange communication with GDB in some other
-   fashion.  If GDB is not used on your system, you can define this macro with
-   an empty body.
-
-   Defined in svr4.h.  */
-/* #define ASM_IDENTIFY_GCC(FILE) */
-
-/* Like ASM_IDENTIFY_GCC, but used when dbx debugging is selected to emit
-   a stab the debugger uses to identify gcc as the compiler that is emitted
-   after the stabs for the filename, which makes it easier for GDB to parse.
-
-   Defined in svr4.h.  */
-/* #define ASM_IDENTIFY_GCC_AFTER_SOURCE(FILE) */
-
-/* A C string constant describing how to begin a comment in the target
-   assembler language.  The compiler assumes that the comment will end at the
-   end of the line.  */
-#define ASM_COMMENT_START ";"
-
-/* A C string constant for text to be output before each `asm' statement or
-   group of consecutive ones.  Normally this is `"#APP"', which is a comment
-   that has no effect on most assemblers but tells the GNU assembler that it
-   must check the lines that follow for all valid assembler constructs.  */
-#define ASM_APP_ON "#APP\n"
-
-/* A C string constant for text to be output after each `asm' statement or
-   group of consecutive ones.  Normally this is `"#NO_APP"', which tells the
-   GNU assembler to resume making the time-saving assumptions that are valid
-   for ordinary compiler output.  */
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* A C statement to output COFF information or DWARF debugging information
-   which indicates that filename NAME is the current source file to the stdio
-   stream STREAM.
-
-   This macro need not be defined if the standard form of output for the file
-   format in use is appropriate.  */
-/* #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) */
-
-/* A C statement to output DBX or SDB debugging information before code for
-   line number LINE of the current source file to the stdio stream STREAM.
-
-   This macro need not be defined if the standard form of debugging information
-   for the debugger in use is appropriate.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) */
-
-/* A C statement to output something to the assembler file to handle a `#ident'
-   directive containing the text STRING.  If this macro is not defined, nothing
-   is output for a `#ident' directive.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_IDENT(STREAM, STRING) */
-
-/* A C statement to output something to the assembler file to switch to section
-   NAME for object DECL which is either a `FUNCTION_DECL', a `VAR_DECL' or
-   `NULL_TREE'.  Some target formats do not support arbitrary sections.  Do not
-   define this macro in such cases.
-
-   At present this macro is only used to support section attributes.  When this
-   macro is undefined, section attributes are disabled.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_SECTION_NAME(STREAM, DECL, NAME) */
-
-/* A C statement to output any assembler statements which are required to
-   precede any Objective C object definitions or message sending.  The
-   statement is executed only when compiling an Objective C program.  */
-/* #define OBJC_PROLOGUE */
-
-
-/* Output of Data.  */
-
-/* A C statement to output to the stdio stream STREAM an assembler instruction
-   to assemble a floating-point constant of `TFmode', `DFmode', `SFmode',
-   `TQFmode', `HFmode', or `QFmode', respectively, whose value is VALUE.  VALUE
-   will be a C expression of type `REAL_VALUE_TYPE'.  Macros such as
-   `REAL_VALUE_TO_TARGET_DOUBLE' are useful for writing these definitions.  */
-
-/* #define ASM_OUTPUT_LONG_DOUBLE(STREAM, VALUE) */
-
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t[2];							\
-	REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);			\
-	fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n",		\
-		t[0] & 0xffffffff, t[1] & 0xffffffff);			\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str);			\
-	fprintf (FILE, "\t.double 0d%s\n", str);			\
-      }									\
-  }
-
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t;								\
-	REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
-	fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff);		\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);			\
-	fprintf (FILE, "\t.float 0d%s\n", str);				\
-      }									\
-  }
-
-/* #define ASM_OUTPUT_THREE_QUARTER_FLOAT(STREAM, VALUE) */
-/* #define ASM_OUTPUT_SHORT_FLOAT(STREAM, VALUE) */
-/* #define ASM_OUTPUT_BYTE_FLOAT(STREAM, VALUE) */
-
-/* A C statement to output to the stdio stream STREAM an assembler instruction
-   to assemble an integer of 16, 8, 4, 2 or 1 bytes, respectively, whose value
-   is VALUE.  The argument EXP will be an RTL expression which represents a
-   constant value.  Use `output_addr_const (STREAM, EXP)' to output this value
-   as an assembler expression.
-
-   For sizes larger than `UNITS_PER_WORD', if the action of a macro would be
-   identical to repeatedly calling the macro corresponding to a size of
-   `UNITS_PER_WORD', once for each word, you need not define the macro.  */
-
-/* #define ASM_OUTPUT_QUADRUPLE_INT(STREAM, EXP) */
-/* #define ASM_OUTPUT_DOUBLE_INT(STREAM, EXP) */
-
-#define ASM_OUTPUT_INT(STREAM, EXP)					\
-do {									\
-  fputs ("\t.word ", STREAM);						\
-  output_addr_const (STREAM, EXP);					\
-  putc ('\n', STREAM);							\
-} while (0)
-
-#define ASM_OUTPUT_SHORT(STREAM, EXP)					\
-do {									\
-  fputs ("\t.hword ", STREAM);						\
-  output_addr_const (STREAM, EXP);					\
-  putc ('\n', STREAM);							\
-} while (0)
-
-#define ASM_OUTPUT_CHAR(STREAM, EXP)					\
-do {									\
-  fputs ("\t.byte ", STREAM);						\
-  output_addr_const (STREAM, EXP);					\
-  putc ('\n', STREAM);							\
-} while (0)
-
-/* A C statement to output to the stdio stream STREAM an assembler instruction
-   to assemble a single byte containing the number VALUE.  */
-
-#define ASM_OUTPUT_BYTE(STREAM, VALUE) \
-  fprintf (STREAM, "\t%s %d\n", ASM_BYTE_OP, VALUE)
-
-/* A C string constant giving the pseudo-op to use for a sequence of
-   single-byte constants.  If this macro is not defined, the default
-   is `"byte"'.
-
-   Defined in svr4.h.  */
-/* #define ASM_BYTE_OP */
-
-/* A C statement to output to the stdio stream STREAM an assembler instruction
-   to assemble a string constant containing the LEN bytes at PTR.  PTR will be
-   a C expression of type `char *' and LEN a C expression of type `int'.
-
-   If the assembler has a `.ascii' pseudo-op as found in the Berkeley Unix
-   assembler, do not define the macro `ASM_OUTPUT_ASCII'.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) */
-
-/* You may define this macro as a C expression.  You should define the
-   expression to have a non-zero value if GNU CC should output the
-   constant pool for a function before the code for the function, or
-   a zero value if GNU CC should output the constant pool after the
-   function.  If you do not define this macro, the usual case, GNU CC
-   will output the constant pool before the function.  */
-/* #define CONSTANT_POOL_BEFORE_FUNCTION */
-
-/* A C statement to output assembler commands to define the start of the
-   constant pool for a function.  FUNNAME is a string giving the name of the
-   function.  Should the return type of the function be required, it can be
-   obtained via FUNDECL.  SIZE is the size, in bytes, of the constant pool that
-   will be written immediately after this call.
-
-   If no constant-pool prefix is required, the usual case, this macro need not
-   be defined.  */
-/* #define ASM_OUTPUT_POOL_PROLOGUE(FILE FUNNAME FUNDECL SIZE) */
-
-/* A C statement (with or without semicolon) to output a constant in the
-   constant pool, if it needs special treatment.  (This macro need not do
-   anything for RTL expressions that can be output normally.)
-
-   The argument FILE is the standard I/O stream to output the assembler code
-   on.  X is the RTL expression for the constant to output, and MODE is the
-   machine mode (in case X is a `const_int').  ALIGN is the required alignment
-   for the value X; you should output an assembler directive to force this much
-   alignment.
-
-   The argument LABELNO is a number to use in an internal label for the address
-   of this pool entry.  The definition of this macro is responsible for
-   outputting the label definition at the proper place.  Here is how to do
-   this:
-
-        ASM_OUTPUT_INTERNAL_LABEL (FILE, "LC", LABELNO);
-
-   When you output a pool entry specially, you should end with a `goto' to the
-   label JUMPTO.  This will prevent the same pool entry from being output a
-   second time in the usual manner.
-
-   You need not define this macro if it would do nothing.  */
-/* #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) */
-
-/* Define this macro as a C expression which is nonzero if the constant EXP, of
-   type `tree', should be output after the code for a function.  The compiler
-   will normally output all constants before the function; you need not define
-   this macro if this is OK.  */
-/* #define CONSTANT_AFTER_FUNCTION_P(EXP) */
-
-/* A C statement to output assembler commands to at the end of the constant
-   pool for a function.  FUNNAME is a string giving the name of the function.
-   Should the return type of the function be required, you can obtain it via
-   FUNDECL.  SIZE is the size, in bytes, of the constant pool that GNU CC wrote
-   immediately before this call.
-
-   If no constant-pool epilogue is required, the usual case, you need not
-   define this macro.  */
-/* #define ASM_OUTPUT_POOL_EPILOGUE (FILE FUNNAME FUNDECL SIZE) */
-
-/* Define this macro as a C expression which is nonzero if C is used as a
-   logical line separator by the assembler.
-
-   If you do not define this macro, the default is that only the character `;'
-   is treated as a logical line separator.  */
-/* #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) */
-
-/* These macros are defined as C string constant, describing the syntax in the
-   assembler for grouping arithmetic expressions.  The following definitions
-   are correct for most assemblers:
-
-        #define ASM_OPEN_PAREN "("
-        #define ASM_CLOSE_PAREN ")"  */
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* These macros are provided by `real.h' for writing the definitions of
-   `ASM_OUTPUT_DOUBLE' and the like: */
-
-/* These translate X, of type `REAL_VALUE_TYPE', to the target's floating point
-   representation, and store its bit pattern in the array of `long int' whose
-   address is L.  The number of elements in the output array is determined by
-   the size of the desired target floating point data type: 32 bits of it go in
-   each `long int' array element.  Each array element holds 32 bits of the
-   result, even if `long int' is wider than 32 bits on the host machine.
-
-   The array element values are designed so that you can print them out using
-   `fprintf' in the order they should appear in the target machine's memory.  */
-/* #define REAL_VALUE_TO_TARGET_SINGLE(X, L) */
-/* #define REAL_VALUE_TO_TARGET_DOUBLE(X, L) */
-/* #define REAL_VALUE_TO_TARGET_LONG_DOUBLE(X, L) */
-
-/* This macro converts X, of type `REAL_VALUE_TYPE', to a decimal number and
-   stores it as a string into STRING.  You must pass, as STRING, the address of
-   a long enough block of space to hold the result.
-
-   The argument FORMAT is a `printf'-specification that serves as a suggestion
-   for how to format the output string.  */
-/* #define REAL_VALUE_TO_DECIMAL(X, FORMAT, STRING) */
-
-
-/* Output of Uninitialized Variables.  */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM the
-   assembler definition of a common-label named NAME whose size is SIZE bytes.
-   The variable ROUNDED is the size rounded up to whatever alignment the caller
-   wants.
-
-   Use the expression `assemble_name (STREAM, NAME)' to output the name itself;
-   before and after that, output the additional assembler syntax for defining
-   the name, and a newline.
-
-   This macro controls how the assembler definitions of uninitialized global
-   variables are output.  */
-/* #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) */
-
-/* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a separate,
-   explicit argument.  If you define this macro, it is used in place of
-   `ASM_OUTPUT_COMMON', and gives you more flexibility in handling the required
-   alignment of the variable.  The alignment is specified as the number of
-   bits.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_ALIGNED_COMMON(STREAM, NAME, SIZE, ALIGNMENT) */
-
-/* Like ASM_OUTPUT_ALIGNED_COMMON except that it takes an additional argument -
-   the DECL of the variable to be output, if there is one.  This macro can be
-   called with DECL == NULL_TREE.  If you define this macro, it is used in
-   place of both ASM_OUTPUT_COMMON and ASM_OUTPUT_ALIGNED_COMMON, and gives you
-   more flexibility in handling the destination of the variable.  */
-/* #define ASM_OUTPUT_DECL_COMMON (STREAM, DECL, NAME, SIZE, ALIGNMENT) */
-
-/* If defined, it is similar to `ASM_OUTPUT_COMMON', except that it is used
-   when NAME is shared.  If not defined, `ASM_OUTPUT_COMMON' will be used.  */
-/* #define ASM_OUTPUT_SHARED_COMMON(STREAM, NAME, SIZE, ROUNDED) */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM the
-   assembler definition of uninitialized global DECL named NAME whose size is
-   SIZE bytes.  The variable ROUNDED is the size rounded up to whatever
-   alignment the caller wants.
-
-   Try to use function `asm_output_bss' defined in `varasm.c' when defining
-   this macro.  If unable, use the expression `assemble_name (STREAM, NAME)' to
-   output the name itself; before and after that, output the additional
-   assembler syntax for defining the name, and a newline.
-
-   This macro controls how the assembler definitions of uninitialized global
-   variables are output.  This macro exists to properly support languages like
-   `c++' which do not have `common' data.  However, this macro currently is not
-   defined for all targets.  If this macro and `ASM_OUTPUT_ALIGNED_BSS' are not
-   defined then `ASM_OUTPUT_COMMON' or `ASM_OUTPUT_ALIGNED_COMMON' or
-   `ASM_OUTPUT_DECL_COMMON' is used.  */
-/* #define ASM_OUTPUT_BSS(STREAM, DECL, NAME, SIZE, ROUNDED) */
-
-/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a separate,
-   explicit argument.  If you define this macro, it is used in place of
-   `ASM_OUTPUT_BSS', and gives you more flexibility in handling the required
-   alignment of the variable.  The alignment is specified as the number of
-   bits.
-
-   Try to use function `asm_output_aligned_bss' defined in file `varasm.c' when
-   defining this macro.  */
-/* #define ASM_OUTPUT_ALIGNED_BSS(STREAM, DECL, NAME, SIZE, ALIGNMENT) */
-
-/* If defined, it is similar to `ASM_OUTPUT_BSS', except that it is used when
-   NAME is shared.  If not defined, `ASM_OUTPUT_BSS' will be used.  */
-/* #define ASM_OUTPUT_SHARED_BSS(STREAM, DECL, NAME, SIZE, ROUNDED) */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM the
-   assembler definition of a local-common-label named NAME whose size is SIZE
-   bytes.  The variable ROUNDED is the size rounded up to whatever alignment
-   the caller wants.
-
-   Use the expression `assemble_name (STREAM, NAME)' to output the name itself;
-   before and after that, output the additional assembler syntax for defining
-   the name, and a newline.
-
-   This macro controls how the assembler definitions of uninitialized static
-   variables are output.  */
-/* #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) */
-
-/* Like `ASM_OUTPUT_LOCAL' except takes the required alignment as a separate,
-   explicit argument.  If you define this macro, it is used in place of
-   `ASM_OUTPUT_LOCAL', and gives you more flexibility in handling the required
-   alignment of the variable.  The alignment is specified as the number of
-   bits.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGNMENT) */
-
-/* Like `ASM_OUTPUT_ALIGNED_LOCAL' except that it takes an additional
-   parameter - the DECL of variable to be output, if there is one.
-   This macro can be called with DECL == NULL_TREE.  If you define
-   this macro, it is used in place of `ASM_OUTPUT_LOCAL' and
-   `ASM_OUTPUT_ALIGNED_LOCAL', and gives you more flexibility in
-   handling the destination of the variable.  */
-/* #define ASM_OUTPUT_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) */
-
-/* If defined, it is similar to `ASM_OUTPUT_LOCAL', except that it is used when
-   NAME is shared.  If not defined, `ASM_OUTPUT_LOCAL' will be used.  */
-/* #define ASM_OUTPUT_SHARED_LOCAL (STREAM, NAME, SIZE, ROUNDED) */
-
-
-/* Output and Generation of Labels.  */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM the
-   assembler definition of a label named NAME.  Use the expression
-   `assemble_name (STREAM, NAME)' to output the name itself; before and after
-   that, output the additional assembler syntax for defining the name, and a
-   newline.  */
-
-#define ASM_OUTPUT_LABEL(STREAM, NAME)					\
-do {									\
-  assemble_name (STREAM, NAME);						\
-  fputs (":\n", STREAM);						\
-} while (0)
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM any text
-   necessary for declaring the name NAME of a function which is being defined.
-   This macro is responsible for outputting the label definition (perhaps using
-   `ASM_OUTPUT_LABEL').  The argument DECL is the `FUNCTION_DECL' tree node
-   representing the function.
-
-   If this macro is not defined, then the function name is defined in the usual
-   manner as a label (by means of `ASM_OUTPUT_LABEL').
-
-   Defined in svr4.h.  */
-/* #define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM any text
-   necessary for declaring the size of a function which is being defined.  The
-   argument NAME is the name of the function.  The argument DECL is the
-   `FUNCTION_DECL' tree node representing the function.
-
-   If this macro is not defined, then the function size is not defined.
-
-   Defined in svr4.h.  */
-/* #define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM any text
-   necessary for declaring the name NAME of an initialized variable which is
-   being defined.  This macro must output the label definition (perhaps using
-   `ASM_OUTPUT_LABEL').  The argument DECL is the `VAR_DECL' tree node
-   representing the variable.
-
-   If this macro is not defined, then the variable name is defined in the usual
-   manner as a label (by means of `ASM_OUTPUT_LABEL').
-
-   Defined in svr4.h.  */
-/* #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) */
-
-/* A C statement (sans semicolon) to finish up declaring a variable name once
-   the compiler has processed its initializer fully and thus has had a chance
-   to determine the size of an array when controlled by an initializer.  This
-   is used on systems where it's necessary to declare something about the size
-   of the object.
-
-   If you don't define this macro, that is equivalent to defining it to do
-   nothing.
-
-   Defined in svr4.h.  */
-/* #define ASM_FINISH_DECLARE_OBJECT(STREAM, DECL, TOPLEVEL, ATEND) */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM some
-   commands that will make the label NAME global; that is, available for
-   reference from other files.  Use the expression `assemble_name (STREAM,
-   NAME)' to output the name itself; before and after that, output the
-   additional assembler syntax for making that name global, and a newline.  */
-
-#define ASM_GLOBALIZE_LABEL(STREAM,NAME)				\
-do {									\
-  fputs ("\t.globl ", STREAM);						\
-  assemble_name (STREAM, NAME);						\
-  fputs ("\n", STREAM);							\
-} while (0)
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM some
-   commands that will make the label NAME weak; that is, available for
-   reference from other files but only used if no other definition is
-   available.  Use the expression `assemble_name (STREAM, NAME)' to output the
-   name itself; before and after that, output the additional assembler syntax
-   for making that name weak, and a newline.
-
-   If you don't define this macro, GNU CC will not support weak symbols and you
-   should not define the `SUPPORTS_WEAK' macro.
-
-   Defined in svr4.h.  */
-/* #define ASM_WEAKEN_LABEL */
-
-/* A C expression which evaluates to true if the target supports weak symbols.
-
-   If you don't define this macro, `defaults.h' provides a default definition.
-   If `ASM_WEAKEN_LABEL' is defined, the default definition is `1'; otherwise,
-   it is `0'.  Define this macro if you want to control weak symbol support
-   with a compiler flag such as `-melf'.  */
-/* #define SUPPORTS_WEAK */
-
-/* A C statement (sans semicolon) to mark DECL to be emitted as a
-   public symbol such that extra copies in multiple translation units
-   will be discarded by the linker.  Define this macro if your object
-   file format provides support for this concept, such as the `COMDAT'
-   section flags in the Microsoft Windows PE/COFF format, and this
-   support requires changes to DECL, such as putting it in a separate
-   section.
-
-   Defined in svr4.h.  */
-/* #define MAKE_DECL_ONE_ONLY */
-
-/* A C expression which evaluates to true if the target supports one-only
-   semantics.
-
-   If you don't define this macro, `varasm.c' provides a default definition.
-   If `MAKE_DECL_ONE_ONLY' is defined, the default definition is `1';
-   otherwise, it is `0'.  Define this macro if you want to control one-only
-   symbol support with a compiler flag, or if setting the `DECL_ONE_ONLY' flag
-   is enough to mark a declaration to be emitted as one-only.  */
-/* #define SUPPORTS_ONE_ONLY */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM any text
-   necessary for declaring the name of an external symbol named NAME which is
-   referenced in this compilation but not defined.  The value of DECL is the
-   tree node for the declaration.
-
-   This macro need not be defined if it does not need to output anything.  The
-   GNU assembler and most Unix assemblers don't require anything.  */
-/* #define ASM_OUTPUT_EXTERNAL(STREAM, DECL, NAME) */
-
-/* A C statement (sans semicolon) to output on STREAM an assembler pseudo-op to
-   declare a library function name external.  The name of the library function
-   is given by SYMREF, which has type `rtx' and is a `symbol_ref'.
-
-   This macro need not be defined if it does not need to output anything.  The
-   GNU assembler and most Unix assemblers don't require anything.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_EXTERNAL_LIBCALL(STREAM, SYMREF) */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM a
-   reference in assembler syntax to a label named NAME.  This should add `_' to
-   the front of the name, if that is customary on your operating system, as it
-   is in most Berkeley Unix systems.  This macro is used in `assemble_name'.  */
-/* #define ASM_OUTPUT_LABELREF(STREAM, NAME) */
-
-/* A C statement to output to the stdio stream STREAM a label whose name is
-   made from the string PREFIX and the number NUM.
-
-   It is absolutely essential that these labels be distinct from the labels
-   used for user-level functions and variables.  Otherwise, certain programs
-   will have name conflicts with internal labels.
-
-   It is desirable to exclude internal labels from the symbol table of the
-   object file.  Most assemblers have a naming convention for labels that
-   should be excluded; on many systems, the letter `L' at the beginning of a
-   label has this effect.  You should find out what convention your system
-   uses, and follow it.
-
-   The usual definition of this macro is as follows:
-
-        fprintf (STREAM, "L%s%d:\n", PREFIX, NUM)
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) */
-
-/* A C statement to store into the string STRING a label whose name is made
-   from the string PREFIX and the number NUM.
-
-   This string, when output subsequently by `assemble_name', should produce the
-   output that `ASM_OUTPUT_INTERNAL_LABEL' would produce with the same PREFIX
-   and NUM.
-
-   If the string begins with `*', then `assemble_name' will output the rest of
-   the string unchanged.  It is often convenient for
-   `ASM_GENERATE_INTERNAL_LABEL' to use `*' in this way.  If the string doesn't
-   start with `*', then `ASM_OUTPUT_LABELREF' gets to output the string, and
-   may change it.  (Of course, `ASM_OUTPUT_LABELREF' is also part of your
-   machine description, so you should know what it does on your machine.)
-
-   Defined in svr4.h.  */
-
-/*
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)			\
-do {									\
-  sprintf (LABEL, "*.%s%d", PREFIX, NUM);				\
-} while (0)
-*/
-
-/* A C expression to assign to OUTVAR (which is a variable of type `char *') a
-   newly allocated string made from the string NAME and the number NUMBER, with
-   some suitable punctuation added.  Use `alloca' to get space for the string.
-
-   The string will be used as an argument to `ASM_OUTPUT_LABELREF' to produce
-   an assembler label for an internal static variable whose name is NAME.
-   Therefore, the string must be such as to result in valid assembler code.
-   The argument NUMBER is different each time this macro is executed; it
-   prevents conflicts between similarly-named internal static variables in
-   different scopes.
-
-   Ideally this string should not be a valid C identifier, to prevent any
-   conflict with the user's own symbols.  Most assemblers allow periods or
-   percent signs in assembler symbols; putting at least one of these between
-   the name and the number will suffice.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER)			\
-do {									\
-  (OUTVAR) = (char *) alloca (strlen ((NAME)) + 12);			\
-  sprintf ((OUTVAR), "%s.%ld", (NAME), (long)(NUMBER));			\
-} while (0)
-
-/* A C statement to output to the stdio stream STREAM assembler code which
-   defines (equates) the symbol NAME to have the value VALUE.
-
-   If SET_ASM_OP is defined, a default definition is provided which is correct
-   for most systems.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) */
-
-/* A C statement to output to the stdio stream STREAM assembler code which
-   defines (equates) the weak symbol NAME to have the value VALUE.
-
-   Define this macro if the target only supports weak aliases; define
-   ASM_OUTPUT_DEF instead if possible.  */
-/* #define ASM_OUTPUT_WEAK_ALIAS (STREAM, NAME, VALUE) */
-
-/* Define this macro to override the default assembler names used for Objective
-   C methods.
-
-   The default name is a unique method number followed by the name of the class
-   (e.g. `_1_Foo').  For methods in categories, the name of the category is
-   also included in the assembler name (e.g.  `_1_Foo_Bar').
-
-   These names are safe on most systems, but make debugging difficult since the
-   method's selector is not present in the name.  Therefore, particular systems
-   define other ways of computing names.
-
-   BUF is an expression of type `char *' which gives you a buffer in which to
-   store the name; its length is as long as CLASS_NAME, CAT_NAME and SEL_NAME
-   put together, plus 50 characters extra.
-
-   The argument IS_INST specifies whether the method is an instance method or a
-   class method; CLASS_NAME is the name of the class; CAT_NAME is the name of
-   the category (or NULL if the method is not in a category); and SEL_NAME is
-   the name of the selector.
-
-   On systems where the assembler can handle quoted names, you can use this
-   macro to provide more human-readable names.  */
-/* #define OBJC_GEN_METHOD_LABEL(BUF, IS_INST, CLASS_NAME, CAT_NAME, SEL_NAME) */
-
-
-/* Macros Controlling Initialization Routines.  */
-
-/* If defined, a C string constant for the assembler operation to identify the
-   following data as initialization code.  If not defined, GNU CC will assume
-   such a section does not exist.  When you are using special sections for
-   initialization and termination functions, this macro also controls how
-   `crtstuff.c' and `libgcc2.c' arrange to run the initialization functions.
-
-   Defined in svr4.h.  */
-/* #define INIT_SECTION_ASM_OP */
-#undef INIT_SECTION_ASM_OP
-
-/* If defined, `main' will not call `__main' as described above.  This macro
-   should be defined for systems that control the contents of the init section
-   on a symbol-by-symbol basis, such as OSF/1, and should not be defined
-   explicitly for systems that support `INIT_SECTION_ASM_OP'.  */
-/* #define HAS_INIT_SECTION */
-
-/* If defined, a C string constant for a switch that tells the linker that the
-   following symbol is an initialization routine.  */
-/* #define LD_INIT_SWITCH */
-
-/* If defined, a C string constant for a switch that tells the linker that the
-   following symbol is a finalization routine.  */
-/* #define LD_FINI_SWITCH */
-
-/* If defined, `main' will call `__main' despite the presence of
-   `INIT_SECTION_ASM_OP'.  This macro should be defined for systems where the
-   init section is not actually run automatically, but is still useful for
-   collecting the lists of constructors and destructors.  */
-#define INVOKE__main
-
-/* Define this macro as a C statement to output on the stream STREAM the
-   assembler code to arrange to call the function named NAME at initialization
-   time.
-
-   Assume that NAME is the name of a C function generated automatically by the
-   compiler.  This function takes no arguments.  Use the function
-   `assemble_name' to output the name NAME; this performs any system-specific
-   syntactic transformations such as adding an underscore.
-
-   If you don't define this macro, nothing special is output to arrange to call
-   the function.  This is correct when the function will be called in some
-   other manner--for example, by means of the `collect2' program, which looks
-   through the symbol table to find these functions by their names.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_CONSTRUCTOR(STREAM, NAME) */
-
-/* This is like `ASM_OUTPUT_CONSTRUCTOR' but used for termination functions
-   rather than initialization functions.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_DESTRUCTOR(STREAM, NAME) */
-
-/* If your system uses `collect2' as the means of processing constructors, then
-   that program normally uses `nm' to scan an object file for constructor
-   functions to be called.  On certain kinds of systems, you can define these
-   macros to make `collect2' work faster (and, in some cases, make it work at
-   all): */
-
-/* Define this macro if the system uses COFF (Common Object File Format) object
-   files, so that `collect2' can assume this format and scan object files
-   directly for dynamic constructor/destructor functions.  */
-/* #define OBJECT_FORMAT_COFF */
-
-/* Define this macro if the system uses ROSE format object files, so that
-   `collect2' can assume this format and scan object files directly for dynamic
-   constructor/destructor functions.
-
-   These macros are effective only in a native compiler; `collect2' as
-   part of a cross compiler always uses `nm' for the target machine.  */
-/* #define OBJECT_FORMAT_ROSE */
-
-/* Define this macro if the system uses ELF format object files.
-
-   Defined in svr4.h.  */
-/* #define OBJECT_FORMAT_ELF */
-
-/* Define this macro as a C string constant containing the file name to use to
-   execute `nm'.  The default is to search the path normally for `nm'.
-
-   If your system supports shared libraries and has a program to list the
-   dynamic dependencies of a given library or executable, you can define these
-   macros to enable support for running initialization and termination
-   functions in shared libraries: */
-/* #define REAL_NM_FILE_NAME */
-
-/* Define this macro to a C string constant containing the name of the program
-   which lists dynamic dependencies, like `"ldd"' under SunOS 4.  */
-/* #define LDD_SUFFIX */
-
-/* Define this macro to be C code that extracts filenames from the output of
-   the program denoted by `LDD_SUFFIX'.  PTR is a variable of type `char *'
-   that points to the beginning of a line of output from `LDD_SUFFIX'.  If the
-   line lists a dynamic dependency, the code must advance PTR to the beginning
-   of the filename on that line.  Otherwise, it must set PTR to `NULL'.  */
-/* #define PARSE_LDD_OUTPUT (PTR) */
-
-
-/* Output of Assembler Instructions.  */
-
-/* A C initializer containing the assembler's names for the machine registers,
-   each one as a C string constant.  This is what translates register numbers
-   in the compiler into assembler language.  */
-#define REGISTER_NAMES							\
-{									\
-  "r0",		"r1",		"r2",		"r3",			\
-  "r4",		"r5",		"r6",		"r7",			\
-  "r8",		"r9",		"r10",		"r11",			\
-  "r12",	"r13",		"r14",		"r15",			\
-  "r16",	"r17",		"r18",		"r19",			\
-  "r20",	"r21",		"r22",		"r23",			\
-  "r24",	"r25",		"r26",		"r27",			\
-  "r28",	"r29",		"r30",		"r31",			\
-  "r32",	"r33",		"r34",		"r35",			\
-  "r36",	"r37",		"r38",		"r39",			\
-  "r40",	"r41",		"r42",		"r43",			\
-  "r44",	"r45",		"r46",		"r47",			\
-  "r48",	"r49",		"r50",		"r51",			\
-  "r52",	"r53",		"r54",		"r55",			\
-  "r56",	"r57",		"r58",		"r59",			\
-  "r60",	"r61",		"link",		"sp",			\
-  "ap",									\
-  "f0",		"f1",		"f2",		"f3",			\
-  "s",		"v",		"va",		"c",			\
-  "a0",		"a1",							\
-  "psw",	"bpsw",		"pc",		"bpc",			\
-  "dpsw",	"dpc",		"rpt_c",	"rpt_s",		\
-  "rpt_e",	"mod_s",	"mod_e",	"iba",			\
-  "eit_vb",	"int_s",	"int_m",				\
-}
-
-/* If defined, a C initializer for an array of structures containing a name and
-   a register number.  This macro defines additional names for hard registers,
-   thus allowing the `asm' option in declarations to refer to registers using
-   alternate names.  */
-#define ADDITIONAL_REGISTER_NAMES					\
-{									\
-  "r62",	GPR_LINK,						\
-  "r63",	GPR_SP,							\
-  "f4",		FLAG_SAT,						\
-  "f5",		FLAG_OVERFLOW,						\
-  "f6",		FLAG_ACC_OVER,						\
-  "f7",		FLAG_CARRY,						\
-  "carry",	FLAG_CARRY,						\
-  "borrow",	FLAG_BORROW,						\
-  "b",		FLAG_BORROW,						\
-  "cr0",	CR_PSW,							\
-  "cr1",	CR_BPSW,						\
-  "cr2",	CR_PC,							\
-  "cr3",	CR_BPC,							\
-  "cr4",	CR_DPSW,						\
-  "cr5",	CR_DPC,							\
-  "cr7",	CR_RPT_C,						\
-  "cr8",	CR_RPT_S,						\
-  "cr9",	CR_RPT_E,						\
-  "cr10",	CR_MOD_S,						\
-  "cr11",	CR_MOD_E,						\
-  "cr14",	CR_IBA,							\
-  "cr15",	CR_EIT_VB,						\
-  "cr16",	CR_INT_S,						\
-  "cr17",	CR_INT_M						\
-}
-
-/* Define this macro if you are using an unusual assembler that requires
-   different names for the machine instructions.
-
-   The definition is a C statement or statements which output an assembler
-   instruction opcode to the stdio stream STREAM.  The macro-operand PTR is a
-   variable of type `char *' which points to the opcode name in its "internal"
-   form--the form that is written in the machine description.  The definition
-   should output the opcode name to STREAM, performing any translation you
-   desire, and increment the variable PTR to point at the end of the opcode so
-   that it will not be output twice.
-
-   In fact, your macro definition may process less than the entire opcode name,
-   or more than the opcode name; but if you want to process text that includes
-   `%'-sequences to substitute operands, you must take care of the substitution
-   yourself.  Just be sure to increment PTR over whatever text should not be
-   output normally.
-
-   If you need to look at the operand values, they can be found as the elements
-   of `recog_operand'.
-
-   If the macro definition does nothing, the instruction is output in the usual
-   way.  */
-/* #define ASM_OUTPUT_OPCODE(STREAM, PTR) */
-
-/* If defined, a C statement to be executed just prior to the output of
-   assembler code for INSN, to modify the extracted operands so they will be
-   output differently.
-
-   Here the argument OPVEC is the vector containing the operands extracted from
-   INSN, and NOPERANDS is the number of elements of the vector which contain
-   meaningful data for this insn.  The contents of this vector are what will be
-   used to convert the insn template into assembler code, so you can change the
-   assembler output by changing the contents of the vector.
-
-   This macro is useful when various assembler syntaxes share a single file of
-   instruction patterns; by defining this macro differently, you can cause a
-   large class of instructions to be output differently (such as with
-   rearranged operands).  Naturally, variations in assembler syntax affecting
-   individual insn patterns ought to be handled by writing conditional output
-   routines in those patterns.
-
-   If this macro is not defined, it is equivalent to a null statement.  */
-/* #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) */
-
-/* If defined, `FINAL_PRESCAN_INSN' will be called on each
-   `CODE_LABEL'.  In that case, OPVEC will be a null pointer and
-   NOPERANDS will be zero.  */
-/* #define FINAL_PRESCAN_LABEL */
-
-/* A C compound statement to output to stdio stream STREAM the assembler syntax
-   for an instruction operand X.  X is an RTL expression.
-
-   CODE is a value that can be used to specify one of several ways of printing
-   the operand.  It is used when identical operands must be printed differently
-   depending on the context.  CODE comes from the `%' specification that was
-   used to request printing of the operand.  If the specification was just
-   `%DIGIT' then CODE is 0; if the specification was `%LTR DIGIT' then CODE is
-   the ASCII code for LTR.
-
-   If X is a register, this macro should print the register's name.  The names
-   can be found in an array `reg_names' whose type is `char *[]'.  `reg_names'
-   is initialized from `REGISTER_NAMES'.
-
-   When the machine description has a specification `%PUNCT' (a `%' followed by
-   a punctuation character), this macro is called with a null pointer for X and
-   the punctuation character for CODE.
-
-   Standard operand flags that are handled elsewhere:
-	`='  Output a number unique to each instruction in the compilation.
-	`a'  Substitute an operand as if it were a memory reference.
-	`c'  Omit the syntax that indicates an immediate operand.
-	`l'  Substitute a LABEL_REF into a jump instruction.
-	`n'  Like %cDIGIT, except negate the value before printing.
-
-   The d30v specific operand flags are:
-	`.'  Print r0.
-	`f'  Print a SF constant as an int.
-	`s'  Subtract 32 and negate.
-	`A'  Print accumulator number without an `a' in front of it.
-	`B'  Print bit offset for BSET, etc. instructions.
-	`E'  Print u if this is zero extend, nothing if this is sign extend.
-	`F'  Emit /{f,t,x}{f,t,x} for executing a false condition.
-	`L'  Print the lower half of a 64 bit item.
-	`M'  Print a memory reference for ld/st instructions.
-	`R'  Return appropriate cmp instruction for relational test.
-	`S'  Subtract 32.
-	`T'  Emit /{f,t,x}{f,t,x} for executing a true condition.
-	`U'  Print the upper half of a 64 bit item.  */
-
-#define PRINT_OPERAND(STREAM, X, CODE) d30v_print_operand (STREAM, X, CODE)
-
-/* A C expression which evaluates to true if CODE is a valid punctuation
-   character for use in the `PRINT_OPERAND' macro.  If
-   `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no punctuation
-   characters (except for the standard one, `%') are used in this way.  */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '.')
-
-/* A C compound statement to output to stdio stream STREAM the assembler syntax
-   for an instruction operand that is a memory reference whose address is X.  X
-   is an RTL expression.
-
-   On some machines, the syntax for a symbolic address depends on the section
-   that the address refers to.  On these machines, define the macro
-   `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
-   then check for it here.  *Note Assembler Format::.  */
-
-#define PRINT_OPERAND_ADDRESS(STREAM, X) d30v_print_operand_address (STREAM, X)
-
-/* A C statement, to be executed after all slot-filler instructions have been
-   output.  If necessary, call `dbr_sequence_length' to determine the number of
-   slots filled in a sequence (zero if not currently outputting a sequence), to
-   decide how many no-ops to output, or whatever.
-
-   Don't define this macro if it has nothing to do, but it is helpful in
-   reading assembly output if the extent of the delay sequence is made explicit
-   (e.g. with white space).
-
-   Note that output routines for instructions with delay slots must be prepared
-   to deal with not being output as part of a sequence (i.e.  when the
-   scheduling pass is not run, or when no slot fillers could be found.)  The
-   variable `final_sequence' is null when not processing a sequence, otherwise
-   it contains the `sequence' rtx being output.  */
-/* #define DBR_OUTPUT_SEQEND(FILE) */
-
-/* If defined, C string expressions to be used for the `%R', `%L', `%U', and
-   `%I' options of `asm_fprintf' (see `final.c').  These are useful when a
-   single `md' file must support multiple assembler formats.  In that case, the
-   various `tm.h' files can define these macros differently.
-
-   USER_LABEL_PREFIX is defined in svr4.h.  */
-
-#define REGISTER_PREFIX "%"
-#define LOCAL_LABEL_PREFIX "."
-#define USER_LABEL_PREFIX ""
-#define IMMEDIATE_PREFIX ""
-
-/* If your target supports multiple dialects of assembler language (such as
-   different opcodes), define this macro as a C expression that gives the
-   numeric index of the assembler language dialect to use, with zero as the
-   first variant.
-
-   If this macro is defined, you may use `{option0|option1|option2...}'
-   constructs in the output templates of patterns (*note Output Template::.) or
-   in the first argument of `asm_fprintf'.  This construct outputs `option0',
-   `option1' or `option2', etc., if the value of `ASSEMBLER_DIALECT' is zero,
-   one or two, etc.  Any special characters within these strings retain their
-   usual meaning.
-
-   If you do not define this macro, the characters `{', `|' and `}' do not have
-   any special meaning when used in templates or operands to `asm_fprintf'.
-
-   Define the macros `REGISTER_PREFIX', `LOCAL_LABEL_PREFIX',
-   `USER_LABEL_PREFIX' and `IMMEDIATE_PREFIX' if you can express the variations
-   in assemble language syntax with that mechanism.  Define `ASSEMBLER_DIALECT'
-   and use the `{option0|option1}' syntax if the syntax variant are larger and
-   involve such things as different opcodes or operand order.  */
-/* #define ASSEMBLER_DIALECT */
-
-/* A C expression to output to STREAM some assembler code which will push hard
-   register number REGNO onto the stack.  The code need not be optimal, since
-   this macro is used only when profiling.  */
-/* #define ASM_OUTPUT_REG_PUSH (STREAM, REGNO) */
-
-/* A C expression to output to STREAM some assembler code which will pop hard
-   register number REGNO off of the stack.  The code need not be optimal, since
-   this macro is used only when profiling.  */
-/* #define ASM_OUTPUT_REG_POP (STREAM, REGNO) */
-
-
-/* Output of dispatch tables.  */
-
-/* This macro should be provided on machines where the addresses in a dispatch
-   table are relative to the table's own address.
-
-   The definition should be a C statement to output to the stdio stream STREAM
-   an assembler pseudo-instruction to generate a difference between two labels.
-   VALUE and REL are the numbers of two internal labels.  The definitions of
-   these labels are output using `ASM_OUTPUT_INTERNAL_LABEL', and they must be
-   printed in the same way here.  For example,
-
-        fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL)  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
-fprintf (STREAM, "\t.word .L%d-.L%d\n", VALUE, REL)
-
-/* This macro should be provided on machines where the addresses in a dispatch
-   table are absolute.
-
-   The definition should be a C statement to output to the stdio stream STREAM
-   an assembler pseudo-instruction to generate a reference to a label.  VALUE
-   is the number of an internal label whose definition is output using
-   `ASM_OUTPUT_INTERNAL_LABEL'.  For example,
-
-        fprintf (STREAM, "\t.word L%d\n", VALUE)  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
-fprintf (STREAM, "\t.word .L%d\n", VALUE)
-
-/* Define this if the label before a jump-table needs to be output specially.
-   The first three arguments are the same as for `ASM_OUTPUT_INTERNAL_LABEL';
-   the fourth argument is the jump-table which follows (a `jump_insn'
-   containing an `addr_vec' or `addr_diff_vec').
-
-   This feature is used on system V to output a `swbeg' statement for the
-   table.
-
-   If this macro is not defined, these labels are output with
-   `ASM_OUTPUT_INTERNAL_LABEL'.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) */
-
-/* Define this if something special must be output at the end of a jump-table.
-   The definition should be a C statement to be executed after the assembler
-   code for the table is written.  It should write the appropriate code to
-   stdio stream STREAM.  The argument TABLE is the jump-table insn, and NUM is
-   the label-number of the preceding label.
-
-   If this macro is not defined, nothing special is output at the end of the
-   jump-table.  */
-/* #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) */
-
-
-/* Assembler Commands for Exception Regions.  */
-
-/* A C expression to output text to mark the start of an exception region.
-
-   This macro need not be defined on most platforms.  */
-/* #define ASM_OUTPUT_EH_REGION_BEG() */
-
-/* A C expression to output text to mark the end of an exception region.
-
-   This macro need not be defined on most platforms.  */
-/* #define ASM_OUTPUT_EH_REGION_END() */
-
-/* A C expression to switch to the section in which the main exception table is
-   to be placed (*note Sections::.).  The default is a section named
-   `.gcc_except_table' on machines that support named sections via
-   `ASM_OUTPUT_SECTION_NAME', otherwise if `-fpic' or `-fPIC' is in effect, the
-   `data_section', otherwise the `readonly_data_section'.  */
-/* #define EXCEPTION_SECTION() */
-
-/* If defined, a C string constant for the assembler operation to switch to the
-   section for exception handling frame unwind information.  If not defined,
-   GNU CC will provide a default definition if the target supports named
-   sections.  `crtstuff.c' uses this macro to switch to the appropriate
-   section.
-
-   You should define this symbol if your target supports DWARF 2 frame unwind
-   information and the default definition does not work.  */
-/* #define EH_FRAME_SECTION_ASM_OP */
-
-/* A C expression that is nonzero if the normal exception table output should
-   be omitted.
-
-   This macro need not be defined on most platforms.  */
-/* #define OMIT_EH_TABLE() */
-
-/* Alternate runtime support for looking up an exception at runtime and finding
-   the associated handler, if the default method won't work.
-
-   This macro need not be defined on most platforms.  */
-/* #define EH_TABLE_LOOKUP() */
-
-/* A C expression that decides whether or not the current function needs to
-   have a function unwinder generated for it.  See the file `except.c' for
-   details on when to define this, and how.  */
-/* #define DOESNT_NEED_UNWINDER */
-
-/* An rtx used to mask the return address found via RETURN_ADDR_RTX, so that it
-   does not contain any extraneous set bits in it.  */
-/* #define MASK_RETURN_ADDR */
-
-/* Define this macro to 0 if your target supports DWARF 2 frame unwind
-   information, but it does not yet work with exception handling.  Otherwise,
-   if your target supports this information (if it defines
-   `INCOMING_RETURN_ADDR_RTX' and either `UNALIGNED_INT_ASM_OP' or
-   `OBJECT_FORMAT_ELF'), GCC will provide a default definition of 1.
-
-   If this macro is defined to 1, the DWARF 2 unwinder will be the default
-   exception handling mechanism; otherwise, setjmp/longjmp will be used by
-   default.
-
-   If this macro is defined to anything, the DWARF 2 unwinder will be used
-   instead of inline unwinders and __unwind_function in the non-setjmp case.  */
-/* #define DWARF2_UNWIND_INFO */
-
-
-/* Assembler Commands for Alignment.  */
-
-/* The alignment (log base 2) to put in front of LABEL, which follows
-   a BARRIER.
-
-   This macro need not be defined if you don't want any special alignment to be
-   done at such a time.  Most machine descriptions do not currently define the
-   macro.  */
-/* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
-
-/* The desired alignment for the location counter at the beginning
-   of a loop.
-
-   This macro need not be defined if you don't want any special alignment to be
-   done at such a time.  Most machine descriptions do not currently define the
-   macro.  */
-/* #define LOOP_ALIGN(LABEL) */
-
-/* A C statement to output to the stdio stream STREAM an assembler instruction
-   to advance the location counter by NBYTES bytes.  Those bytes should be zero
-   when loaded.  NBYTES will be a C expression of type `int'.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
-  fprintf (STREAM, "\t.zero\t%u\n", (NBYTES)) */
-
-/* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
-   section because it fails put zeros in the bytes that are skipped.  This is
-   true on many Unix systems, where the pseudo-op to skip bytes produces no-op
-   instructions rather than zeros when used in the text section.  */
-/* #define ASM_NO_SKIP_IN_TEXT */
-
-/* A C statement to output to the stdio stream STREAM an assembler command to
-   advance the location counter to a multiple of 2 to the POWER bytes.  POWER
-   will be a C expression of type `int'.  */
-#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
-  fprintf ((STREAM), "\t.p2align %d\n", (POWER))
-
-
-/* Macros Affecting all Debug Formats.  */
-
-/* A C expression that returns the DBX register number for the compiler
-   register number REGNO.  In simple cases, the value of this expression may be
-   REGNO itself.  But sometimes there are some registers that the compiler
-   knows about and DBX does not, or vice versa.  In such cases, some register
-   may need to have one number in the compiler and another for DBX.
-
-   If two registers have consecutive numbers inside GNU CC, and they can be
-   used as a pair to hold a multiword value, then they *must* have consecutive
-   numbers after renumbering with `DBX_REGISTER_NUMBER'.  Otherwise, debuggers
-   will be unable to access such a pair, because they expect register pairs to
-   be consecutive in their own numbering scheme.
-
-   If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not
-   preserve register pairs, then what you must do instead is redefine the
-   actual register numbering scheme.  */
-#define DBX_REGISTER_NUMBER(REGNO)					\
-(GPR_P (REGNO)			 ? ((REGNO) - GPR_FIRST)		\
- : ACCUM_P (REGNO)		 ? ((REGNO) - ACCUM_FIRST + 84)		\
- : FLAG_P (REGNO)		 ? 66 /* return psw for all flags */	\
- : (REGNO) == ARG_POINTER_REGNUM ? (GPR_SP - GPR_FIRST)			\
- : (REGNO) == CR_PSW		 ? (66 + 0)				\
- : (REGNO) == CR_BPSW		 ? (66 + 1)				\
- : (REGNO) == CR_PC		 ? (66 + 2)				\
- : (REGNO) == CR_BPC		 ? (66 + 3)				\
- : (REGNO) == CR_DPSW		 ? (66 + 4)				\
- : (REGNO) == CR_DPC		 ? (66 + 5)				\
- : (REGNO) == CR_RPT_C		 ? (66 + 7)				\
- : (REGNO) == CR_RPT_S		 ? (66 + 8)				\
- : (REGNO) == CR_RPT_E		 ? (66 + 9)				\
- : (REGNO) == CR_MOD_S		 ? (66 + 10)				\
- : (REGNO) == CR_MOD_E		 ? (66 + 11)				\
- : (REGNO) == CR_IBA		 ? (66 + 14)				\
- : (REGNO) == CR_EIT_VB		 ? (66 + 15)				\
- : (REGNO) == CR_INT_S		 ? (66 + 16)				\
- : (REGNO) == CR_INT_M		 ? (66 + 17)				\
- :				   -1)
-
-/* A C expression that returns the integer offset value for an automatic
-   variable having address X (an RTL expression).  The default computation
-   assumes that X is based on the frame-pointer and gives the offset from the
-   frame-pointer.  This is required for targets that produce debugging output
-   for DBX or COFF-style debugging output for SDB and allow the frame-pointer
-   to be eliminated when the `-g' options is used.  */
-/* #define DEBUGGER_AUTO_OFFSET(X) */
-
-/* A C expression that returns the integer offset value for an argument having
-   address X (an RTL expression).  The nominal offset is OFFSET.  */
-/* #define DEBUGGER_ARG_OFFSET(OFFSET, X) */
-
-/* A C expression that returns the type of debugging output GNU CC produces
-   when the user specifies `-g' or `-ggdb'.  Define this if you have arranged
-   for GNU CC to support more than one format of debugging output.  Currently,
-   the allowable values are `DBX_DEBUG', `SDB_DEBUG', `DWARF_DEBUG',
-   `DWARF2_DEBUG', and `XCOFF_DEBUG'.
-
-   The value of this macro only affects the default debugging output; the user
-   can always get a specific type of output by using `-gstabs', `-gcoff',
-   `-gdwarf-1', `-gdwarf-2', or `-gxcoff'.
-
-   Defined in svr4.h.  */
-
-#undef	PREFERRED_DEBUGGING_TYPE
-#define	PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-
-/* Specific Options for DBX Output.  */
-
-/* Define this macro if GNU CC should produce debugging output for DBX in
-   response to the `-g' option.
-
-   Defined in svr4.h.  */
-/* #define DBX_DEBUGGING_INFO */
-
-/* Define this macro if GNU CC should produce XCOFF format debugging output in
-   response to the `-g' option.  This is a variant of DBX format.  */
-/* #define XCOFF_DEBUGGING_INFO */
-
-/* Define this macro to control whether GNU CC should by default generate GDB's
-   extended version of DBX debugging information (assuming DBX-format debugging
-   information is enabled at all).  If you don't define the macro, the default
-   is 1: always generate the extended information if there is any occasion to.  */
-/* #define DEFAULT_GDB_EXTENSIONS */
-
-/* Define this macro if all `.stabs' commands should be output while in the
-   text section.  */
-/* #define DEBUG_SYMS_TEXT */
-
-/* A C string constant naming the assembler pseudo op to use instead of
-   `.stabs' to define an ordinary debugging symbol.  If you don't define this
-   macro, `.stabs' is used.  This macro applies only to DBX debugging
-   information format.  */
-/* #define ASM_STABS_OP */
-
-/* A C string constant naming the assembler pseudo op to use instead of
-   `.stabd' to define a debugging symbol whose value is the current location.
-   If you don't define this macro, `.stabd' is used.  This macro applies only
-   to DBX debugging information format.  */
-/* #define ASM_STABD_OP */
-
-/* A C string constant naming the assembler pseudo op to use instead of
-   `.stabn' to define a debugging symbol with no name.  If you don't define
-   this macro, `.stabn' is used.  This macro applies only to DBX debugging
-   information format.  */
-/* #define ASM_STABN_OP */
-
-/* Define this macro if DBX on your system does not support the construct
-   `xsTAGNAME'.  On some systems, this construct is used to describe a forward
-   reference to a structure named TAGNAME.  On other systems, this construct is
-   not supported at all.  */
-/* #define DBX_NO_XREFS */
-
-/* A symbol name in DBX-format debugging information is normally continued
-   (split into two separate `.stabs' directives) when it exceeds a certain
-   length (by default, 80 characters).  On some operating systems, DBX requires
-   this splitting; on others, splitting must not be done.  You can inhibit
-   splitting by defining this macro with the value zero.  You can override the
-   default splitting-length by defining this macro as an expression for the
-   length you desire.  */
-/* #define DBX_CONTIN_LENGTH */
-
-/* Normally continuation is indicated by adding a `\' character to the end of a
-   `.stabs' string when a continuation follows.  To use a different character
-   instead, define this macro as a character constant for the character you
-   want to use.  Do not define this macro if backslash is correct for your
-   system.  */
-/* #define DBX_CONTIN_CHAR */
-
-/* Define this macro if it is necessary to go to the data section before
-   outputting the `.stabs' pseudo-op for a non-global static variable.  */
-/* #define DBX_STATIC_STAB_DATA_SECTION */
-
-/* The value to use in the "code" field of the `.stabs' directive for a
-   typedef.  The default is `N_LSYM'.  */
-/* #define DBX_TYPE_DECL_STABS_CODE */
-
-/* The value to use in the "code" field of the `.stabs' directive for a static
-   variable located in the text section.  DBX format does not provide any
-   "right" way to do this.  The default is `N_FUN'.  */
-/* #define DBX_STATIC_CONST_VAR_CODE */
-
-/* The value to use in the "code" field of the `.stabs' directive for a
-   parameter passed in registers.  DBX format does not provide any "right" way
-   to do this.  The default is `N_RSYM'.  */
-/* #define DBX_REGPARM_STABS_CODE */
-
-/* The letter to use in DBX symbol data to identify a symbol as a parameter
-   passed in registers.  DBX format does not customarily provide any way to do
-   this.  The default is `'P''.  */
-/* #define DBX_REGPARM_STABS_LETTER */
-
-/* The letter to use in DBX symbol data to identify a symbol as a stack
-   parameter.  The default is `'p''.  */
-/* #define DBX_MEMPARM_STABS_LETTER */
-
-/* Define this macro if the DBX information for a function and its arguments
-   should precede the assembler code for the function.  Normally, in DBX
-   format, the debugging information entirely follows the assembler code.
-
-   Defined in svr4.h.  */
-/* #define DBX_FUNCTION_FIRST */
-
-/* Define this macro if the `N_LBRAC' symbol for a block should precede the
-   debugging information for variables and functions defined in that block.
-   Normally, in DBX format, the `N_LBRAC' symbol comes first.  */
-/* #define DBX_LBRAC_FIRST */
-
-/* Define this macro if the value of a symbol describing the scope of a block
-   (`N_LBRAC' or `N_RBRAC') should be relative to the start of the enclosing
-   function.  Normally, GNU C uses an absolute address.
-
-   Defined in svr4.h.  */
-/* #define DBX_BLOCKS_FUNCTION_RELATIVE */
-
-/* Define this macro if GNU C should generate `N_BINCL' and `N_EINCL'
-   stabs for included header files, as on Sun systems.  This macro
-   also directs GNU C to output a type number as a pair of a file
-   number and a type number within the file.  Normally, GNU C does not
-   generate `N_BINCL' or `N_EINCL' stabs, and it outputs a single
-   number for a type number.  */
-/* #define DBX_USE_BINCL */
-
-
-/* Open ended Hooks for DBX Output.  */
-
-/* Define this macro to say how to output to STREAM the debugging information
-   for the start of a scope level for variable names.  The argument NAME is the
-   name of an assembler symbol (for use with `assemble_name') whose value is
-   the address where the scope begins.  */
-/* #define DBX_OUTPUT_LBRAC(STREAM, NAME) */
-
-/* Like `DBX_OUTPUT_LBRAC', but for the end of a scope level.  */
-/* #define DBX_OUTPUT_RBRAC(STREAM, NAME) */
-
-/* Define this macro if the target machine requires special handling to output
-   an enumeration type.  The definition should be a C statement (sans
-   semicolon) to output the appropriate information to STREAM for the type
-   TYPE.  */
-/* #define DBX_OUTPUT_ENUM(STREAM, TYPE) */
-
-/* Define this macro if the target machine requires special output at the end
-   of the debugging information for a function.  The definition should be a C
-   statement (sans semicolon) to output the appropriate information to STREAM.
-   FUNCTION is the `FUNCTION_DECL' node for the function.  */
-/* #define DBX_OUTPUT_FUNCTION_END(STREAM, FUNCTION) */
-
-/* Define this macro if you need to control the order of output of the standard
-   data types at the beginning of compilation.  The argument SYMS is a `tree'
-   which is a chain of all the predefined global symbols, including names of
-   data types.
-
-   Normally, DBX output starts with definitions of the types for integers and
-   characters, followed by all the other predefined types of the particular
-   language in no particular order.
-
-   On some machines, it is necessary to output different particular types
-   first.  To do this, define `DBX_OUTPUT_STANDARD_TYPES' to output those
-   symbols in the necessary order.  Any predefined types that you don't
-   explicitly output will be output afterward in no particular order.
-
-   Be careful not to define this macro so that it works only for C.  There are
-   no global variables to access most of the built-in types, because another
-   language may have another set of types.  The way to output a particular type
-   is to look through SYMS to see if you can find it.  Here is an example:
-
-        {
-          tree decl;
-          for (decl = syms; decl; decl = TREE_CHAIN (decl))
-            if (!strcmp (IDENTIFIER_POINTER (DECL_NAME (decl)),
-                         "long int"))
-              dbxout_symbol (decl);
-          ...
-        }
-
-   This does nothing if the expected type does not exist.
-
-   See the function `init_decl_processing' in `c-decl.c' to find the names to
-   use for all the built-in C types. */
-/* #define DBX_OUTPUT_STANDARD_TYPES(SYMS) */
-
-/* Some stabs encapsulation formats (in particular ECOFF), cannot
-   handle the `.stabs "",N_FUN,,0,0,Lscope-function-1' gdb dbx
-   extention construct.  On those machines, define this macro to turn
-   this feature off without disturbing the rest of the gdb extensions.  */
-/* #define NO_DBX_FUNCTION_END */
-
-
-/* File names in DBX format.  */
-
-/* Define this if DBX wants to have the current directory recorded in each
-   object file.
-
-   Note that the working directory is always recorded if GDB extensions are
-   enabled.  */
-/* #define DBX_WORKING_DIRECTORY */
-
-/* A C statement to output DBX debugging information to the stdio stream STREAM
-   which indicates that file NAME is the main source file--the file specified
-   as the input file for compilation.  This macro is called only once, at the
-   beginning of compilation.
-
-   This macro need not be defined if the standard form of output for DBX
-   debugging information is appropriate.
-
-   Defined in svr4.h.  */
-/* #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM, NAME) */
-
-/* A C statement to output DBX debugging information to the stdio stream STREAM
-   which indicates that the current directory during compilation is named NAME.
-
-   This macro need not be defined if the standard form of output for DBX
-   debugging information is appropriate.  */
-/* #define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(STREAM, NAME) */
-
-/* A C statement to output DBX debugging information at the end of compilation
-   of the main source file NAME.
-
-   If you don't define this macro, nothing special is output at the end of
-   compilation, which is correct for most machines.  */
-/* #define DBX_OUTPUT_MAIN_SOURCE_FILE_END(STREAM, NAME) */
-
-/* A C statement to output DBX debugging information to the stdio stream STREAM
-   which indicates that file NAME is the current source file.  This output is
-   generated each time input shifts to a different source file as a result of
-   `#include', the end of an included file, or a `#line' command.
-
-   This macro need not be defined if the standard form of output for DBX
-   debugging information is appropriate.  */
-/* #define DBX_OUTPUT_SOURCE_FILENAME(STREAM, NAME) */
-
-
-/* Macros for SDB and Dwarf Output.  */
-
-/* Define this macro if GNU CC should produce COFF-style debugging output for
-   SDB in response to the `-g' option.  */
-/* #define SDB_DEBUGGING_INFO */
-
-/* Define this macro if GNU CC should produce dwarf format debugging output in
-   response to the `-g' option.
-
-   Defined in svr4.h.  */
-/* #define DWARF_DEBUGGING_INFO */
-
-/* Define this macro if GNU CC should produce dwarf version 2 format debugging
-   output in response to the `-g' option.
-
-   To support optional call frame debugging information, you must also define
-   `INCOMING_RETURN_ADDR_RTX' and either set `RTX_FRAME_RELATED_P' on the
-   prologue insns if you use RTL for the prologue, or call `dwarf2out_def_cfa'
-   and `dwarf2out_reg_save' as appropriate from `FUNCTION_PROLOGUE' if you
-   don't.
-
-   Defined in svr4.h.  */
-/* #define DWARF2_DEBUGGING_INFO */
-
-/* Define these macros to override the assembler syntax for the special SDB
-   assembler directives.  See `sdbout.c' for a list of these macros and their
-   arguments.  If the standard syntax is used, you need not define them
-   yourself.  */
-/* #define PUT_SDB_... */
-
-/* Some assemblers do not support a semicolon as a delimiter, even between SDB
-   assembler directives.  In that case, define this macro to be the delimiter
-   to use (usually `\n').  It is not necessary to define a new set of
-   `PUT_SDB_OP' macros if this is the only change required.  */
-/* #define SDB_DELIM */
-
-/* Define this macro to override the usual method of constructing a dummy name
-   for anonymous structure and union types.  See `sdbout.c' for more
-   information.  */
-/* #define SDB_GENERATE_FAKE */
-
-/* Define this macro to allow references to unknown structure, union, or
-   enumeration tags to be emitted.  Standard COFF does not allow handling of
-   unknown references, MIPS ECOFF has support for it.  */
-/* #define SDB_ALLOW_UNKNOWN_REFERENCES */
-
-/* Define this macro to allow references to structure, union, or enumeration
-   tags that have not yet been seen to be handled.  Some assemblers choke if
-   forward tags are used, while some require it.  */
-/* #define SDB_ALLOW_FORWARD_REFERENCES */
-
-
-/* Cross Compilation and Floating Point.  */
-
-/* While all modern machines use 2's complement representation for integers,
-   there are a variety of representations for floating point numbers.  This
-   means that in a cross-compiler the representation of floating point numbers
-   in the compiled program may be different from that used in the machine doing
-   the compilation.
-
-   Because different representation systems may offer different amounts of
-   range and precision, the cross compiler cannot safely use the host machine's
-   floating point arithmetic.  Therefore, floating point constants must be
-   represented in the target machine's format.  This means that the cross
-   compiler cannot use `atof' to parse a floating point constant; it must have
-   its own special routine to use instead.  Also, constant folding must emulate
-   the target machine's arithmetic (or must not be done at all).
-
-   The macros in the following table should be defined only if you are cross
-   compiling between different floating point formats.
-
-   Otherwise, don't define them.  Then default definitions will be set up which
-   use `double' as the data type, `==' to test for equality, etc.
-
-   You don't need to worry about how many times you use an operand of any of
-   these macros.  The compiler never uses operands which have side effects.  */
-
-/* A macro for the C data type to be used to hold a floating point value in the
-   target machine's format.  Typically this would be a `struct' containing an
-   array of `int'.  */
-/* #define REAL_VALUE_TYPE */
-
-/* A macro for a C expression which compares for equality the two values, X and
-   Y, both of type `REAL_VALUE_TYPE'.  */
-/* #define REAL_VALUES_EQUAL(X, Y) */
-
-/* A macro for a C expression which tests whether X is less than Y, both values
-   being of type `REAL_VALUE_TYPE' and interpreted as floating point numbers in
-   the target machine's representation.  */
-/* #define REAL_VALUES_LESS(X, Y) */
-
-/* A macro for a C expression which performs the standard library function
-   `ldexp', but using the target machine's floating point representation.  Both
-   X and the value of the expression have type `REAL_VALUE_TYPE'.  The second
-   argument, SCALE, is an integer.  */
-/* #define REAL_VALUE_LDEXP(X, SCALE) */
-
-/* A macro whose definition is a C expression to convert the target-machine
-   floating point value X to a signed integer.  X has type `REAL_VALUE_TYPE'.  */
-/* #define REAL_VALUE_FIX(X) */
-
-/* A macro whose definition is a C expression to convert the target-machine
-   floating point value X to an unsigned integer.  X has type
-   `REAL_VALUE_TYPE'.  */
-/* #define REAL_VALUE_UNSIGNED_FIX(X) */
-
-/* A macro whose definition is a C expression to round the target-machine
-   floating point value X towards zero to an integer value (but still as a
-   floating point number).  X has type `REAL_VALUE_TYPE', and so does the
-   value.  */
-/* #define REAL_VALUE_RNDZINT(X) */
-
-/* A macro whose definition is a C expression to round the target-machine
-   floating point value X towards zero to an unsigned integer value (but still
-   represented as a floating point number).  X has type `REAL_VALUE_TYPE', and
-   so does the value.  */
-/* #define REAL_VALUE_UNSIGNED_RNDZINT(X) */
-
-/* A macro for a C expression which converts STRING, an expression of type
-   `char *', into a floating point number in the target machine's
-   representation for mode MODE.  The value has type `REAL_VALUE_TYPE'.  */
-/* #define REAL_VALUE_ATOF(STRING, MODE) */
-
-/* Define this macro if infinity is a possible floating point value, and
-   therefore division by 0 is legitimate.  */
-/* #define REAL_INFINITY */
-
-/* A macro for a C expression which determines whether X, a floating point
-   value, is infinity.  The value has type `int'.  By default, this is defined
-   to call `isinf'.  */
-/* #define REAL_VALUE_ISINF(X) */
-
-/* A macro for a C expression which determines whether X, a floating point
-   value, is a "nan" (not-a-number).  The value has type `int'.  By default,
-   this is defined to call `isnan'.  */
-/* #define REAL_VALUE_ISNAN(X) */
-
-/* Define the following additional macros if you want to make floating point
-   constant folding work while cross compiling.  If you don't define them,
-   cross compilation is still possible, but constant folding will not happen
-   for floating point values.  */
-
-/* A macro for a C statement which calculates an arithmetic operation of the
-   two floating point values X and Y, both of type `REAL_VALUE_TYPE' in the
-   target machine's representation, to produce a result of the same type and
-   representation which is stored in OUTPUT (which will be a variable).
-
-   The operation to be performed is specified by CODE, a tree code which will
-   always be one of the following: `PLUS_EXPR', `MINUS_EXPR', `MULT_EXPR',
-   `RDIV_EXPR', `MAX_EXPR', `MIN_EXPR'.
-
-   The expansion of this macro is responsible for checking for overflow.  If
-   overflow happens, the macro expansion should execute the statement `return
-   0;', which indicates the inability to perform the arithmetic operation
-   requested.  */
-/* #define REAL_ARITHMETIC(OUTPUT, CODE, X, Y) */
-
-/* The real.h file actually defines REAL_ARITHMETIC appropriately if it was
-   defined at all before entering into the code, by using #undef first.  */
-#define REAL_ARITHMETIC
-
-/* A macro for a C expression which returns the negative of the floating point
-   value X.  Both X and the value of the expression have type `REAL_VALUE_TYPE'
-   and are in the target machine's floating point representation.
-
-   There is no way for this macro to report overflow, since overflow can't
-   happen in the negation operation.  */
-/* #define REAL_VALUE_NEGATE(X) */
-
-/* A macro for a C expression which converts the floating point value X to mode
-   MODE.
-
-   Both X and the value of the expression are in the target machine's floating
-   point representation and have type `REAL_VALUE_TYPE'.  However, the value
-   should have an appropriate bit pattern to be output properly as a floating
-   constant whose precision accords with mode MODE.
-
-   There is no way for this macro to report overflow.  */
-/* #define REAL_VALUE_TRUNCATE(MODE, X) */
-
-/* A macro for a C expression which converts a floating point value X into a
-   double-precision integer which is then stored into LOW and HIGH, two
-   variables of type INT.  */
-/* #define REAL_VALUE_TO_INT(LOW, HIGH, X) */
-
-/* A macro for a C expression which converts a double-precision integer found
-   in LOW and HIGH, two variables of type INT, into a floating point value
-   which is then stored into X.  */
-/* #define REAL_VALUE_FROM_INT(X, LOW, HIGH) */
-
-
-/* Miscellaneous Parameters.  */
-
-/* Define this if you have defined special-purpose predicates in the file
-   `MACHINE.c'.  This macro is called within an initializer of an array of
-   structures.  The first field in the structure is the name of a predicate and
-   the second field is an array of rtl codes.  For each predicate, list all rtl
-   codes that can be in expressions matched by the predicate.  The list should
-   have a trailing comma.  Here is an example of two entries in the list for a
-   typical RISC machine:
-
-        #define PREDICATE_CODES \
-          {"gen_reg_rtx_operand", {SUBREG, REG}},  \
-          {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
-
-   Defining this macro does not affect the generated code (however, incorrect
-   definitions that omit an rtl code that may be matched by the predicate can
-   cause the compiler to malfunction).  Instead, it allows the table built by
-   `genrecog' to be more compact and efficient, thus speeding up the compiler.
-   The most important predicates to include in the list specified by this macro
-   are thoses used in the most insn patterns.  */
-
-#define PREDICATE_CODES							\
-  { "short_memory_operand",		{ MEM }},			\
-  { "long_memory_operand",		{ MEM }},			\
-  { "d30v_memory_operand",		{ MEM }},			\
-  { "single_reg_memory_operand",	{ MEM }},			\
-  { "const_addr_memory_operand",	{ MEM }},			\
-  { "call_operand",			{ MEM }},			\
-  { "gpr_operand",			{ REG, SUBREG }},		\
-  { "accum_operand",			{ REG, SUBREG }},		\
-  { "gpr_or_accum_operand",		{ REG, SUBREG }},		\
-  { "cr_operand",			{ REG, SUBREG }},		\
-  { "repeat_operand",			{ REG, SUBREG }},		\
-  { "flag_operand",			{ REG, SUBREG }},		\
-  { "br_flag_operand",			{ REG, SUBREG }},		\
-  { "br_flag_or_constant_operand",	{ REG, SUBREG, CONST_INT }},	\
-  { "gpr_or_br_flag_operand",		{ REG, SUBREG }},		\
-  { "f0_operand",			{ REG, SUBREG }},		\
-  { "f1_operand",			{ REG, SUBREG }},		\
-  { "carry_operand",			{ REG, SUBREG }},		\
-  { "reg_or_0_operand",			{ REG, SUBREG, CONST_INT,	\
-					  CONST_DOUBLE }},		\
-  { "gpr_or_signed6_operand",		{ REG, SUBREG, CONST_INT }},	\
-  { "gpr_or_unsigned5_operand",		{ REG, SUBREG, CONST_INT }},	\
-  { "gpr_or_unsigned6_operand",		{ REG, SUBREG, CONST_INT }},	\
-  { "gpr_or_constant_operand",		{ REG, SUBREG, CONST_INT,	\
-					  CONST, SYMBOL_REF,		\
-					  LABEL_REF }},			\
-  { "gpr_or_dbl_const_operand",		{ REG, SUBREG, CONST_INT,	\
-					  CONST, SYMBOL_REF,		\
-					  LABEL_REF, CONST_DOUBLE }},	\
-  { "gpr_or_memory_operand",		{ REG, SUBREG, MEM }},		\
-  { "move_input_operand",		{ REG, SUBREG, MEM, CONST_INT,	\
-					  CONST, SYMBOL_REF,		\
-					  LABEL_REF, CONST_DOUBLE }},	\
-  { "move_output_operand",		{ REG, SUBREG, MEM }},		\
-  { "signed6_operand",			{ CONST_INT }},			\
-  { "unsigned5_operand",		{ CONST_INT }},			\
-  { "unsigned6_operand",		{ CONST_INT }},			\
-  { "bitset_operand",			{ CONST_INT }},			\
-  { "condexec_test_operator",		{ EQ, NE }},			\
-  { "condexec_branch_operator",		{ EQ, NE }},			\
-  { "condexec_unary_operator",		{ ABS, NEG, NOT, ZERO_EXTEND }}, \
-  { "condexec_addsub_operator",		{ PLUS, MINUS }},		\
-  { "condexec_binary_operator",		{ MULT, AND, IOR, XOR,		\
-					  ASHIFT, ASHIFTRT, LSHIFTRT,	\
-					  ROTATE, ROTATERT }},		\
-  { "condexec_shiftl_operator",		{ ASHIFT, ROTATE }},		\
-  { "condexec_extend_operator",		{ SIGN_EXTEND, ZERO_EXTEND }},	\
-  { "branch_zero_operator",		{ EQ, NE }},			\
-  { "cond_move_operand",		{ REG, SUBREG, CONST_INT,	\
-					  CONST, SYMBOL_REF,		\
-					  LABEL_REF, MEM }},		\
-  { "cond_exec_operand",		{ REG, SUBREG, CONST_INT,	\
-					  CONST, SYMBOL_REF,		\
-					  LABEL_REF, MEM }},		\
-  { "srelational_si_operator",		{ EQ, NE, LT, LE, GT, GE }},	\
-  { "urelational_si_operator",		{ LTU, LEU, GTU, GEU }},	\
-  { "relational_di_operator",		{ EQ, NE, LT, LE, GT, GE,	\
-					  LTU, LEU, GTU, GEU }},
-
-/* An alias for a machine mode name.  This is the machine mode that elements of
-   a jump-table should have.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define this if control falls through a `case' insn when the index value is
-   out of range.  This means the specified default-label is actually ignored by
-   the `case' insn proper.  */
-/* #define CASE_DROPS_THROUGH */
-
-/* Define this to be the smallest number of different values for which it is
-   best to use a jump-table instead of a tree of conditional branches.  The
-   default is four for machines with a `casesi' instruction and five otherwise.
-   This is best for most machines.  */
-/* #define CASE_VALUES_THRESHOLD */
-
-/* Define this macro if operations between registers with integral mode smaller
-   than a word are always performed on the entire register.  Most RISC machines
-   have this property and most CISC machines do not.  */
-#define WORD_REGISTER_OPERATIONS 1
-
-/* Define this macro to be a C expression indicating when insns that read
-   memory in MODE, an integral mode narrower than a word, set the bits outside
-   of MODE to be either the sign-extension or the zero-extension of the data
-   read.  Return `SIGN_EXTEND' for values of MODE for which the insn
-   sign-extends, `ZERO_EXTEND' for which it zero-extends, and `NIL' for other
-   modes.
-
-   This macro is not called with MODE non-integral or with a width greater than
-   or equal to `BITS_PER_WORD', so you may return any value in this case.  Do
-   not define this macro if it would always return `NIL'.  On machines where
-   this macro is defined, you will normally define it as the constant
-   `SIGN_EXTEND' or `ZERO_EXTEND'.  */
-
-#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
-
-/* Define if loading short immediate values into registers sign extends.  */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
-
-/* An alias for a tree code that should be used by default for conversion of
-   floating point values to fixed point.  Normally, `FIX_ROUND_EXPR' is used.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* Define this macro if the same instructions that convert a floating point
-   number to a signed fixed point number also convert validly to an unsigned
-   one.  */
-/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
-
-/* An alias for a tree code that is the easiest kind of division to compile
-   code for in the general case.  It may be `TRUNC_DIV_EXPR', `FLOOR_DIV_EXPR',
-   `CEIL_DIV_EXPR' or `ROUND_DIV_EXPR'.  These four division operators differ
-   in how they round the result to an integer.  `EASY_DIV_EXPR' is used when it
-   is permissible to use any of those kinds of division and the choice should
-   be made on the basis of efficiency.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* The maximum number of bytes that a single instruction can move quickly from
-   memory to memory.  */
-#define MOVE_MAX 8
-
-/* The maximum number of bytes that a single instruction can move quickly from
-   memory to memory.  If this is undefined, the default is `MOVE_MAX'.
-   Otherwise, it is the constant value that is the largest value that
-   `MOVE_MAX' can have at run-time.  */
-/* #define MAX_MOVE_MAX */
-
-/* A C expression that is nonzero if on this machine the number of bits
-   actually used for the count of a shift operation is equal to the number of
-   bits needed to represent the size of the object being shifted.  When this
-   macro is non-zero, the compiler will assume that it is safe to omit a
-   sign-extend, zero-extend, and certain bitwise `and' instructions that
-   truncates the count of a shift operation.  On machines that have
-   instructions that act on bitfields at variable positions, which may include
-   `bit test' instructions, a nonzero `SHIFT_COUNT_TRUNCATED' also enables
-   deletion of truncations of the values that serve as arguments to bitfield
-   instructions.
-
-   If both types of instructions truncate the count (for shifts) and position
-   (for bitfield operations), or if no variable-position bitfield instructions
-   exist, you should define this macro.
-
-   However, on some machines, such as the 80386 and the 680x0, truncation only
-   applies to shift operations and not the (real or pretended) bitfield
-   operations.  Define `SHIFT_COUNT_TRUNCATED' to be zero on such machines.
-   Instead, add patterns to the `md' file that include the implied truncation
-   of the shift instructions.
-
-   You need not define this macro if it would always have the value of zero.  */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* A C expression which is nonzero if on this machine it is safe to "convert"
-   an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
-   than INPREC) by merely operating on it as if it had only OUTPREC bits.
-
-   On many machines, this expression can be 1.
-
-   When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for
-   which `MODES_TIEABLE_P' is 0, suboptimal code can result.  If this is the
-   case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve
-   things.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* A C expression describing the value returned by a comparison operator with
-   an integral mode and stored by a store-flag instruction (`sCOND') when the
-   condition is true.  This description must apply to *all* the `sCOND'
-   patterns and all the comparison operators whose results have a `MODE_INT'
-   mode.
-
-   A value of 1 or -1 means that the instruction implementing the comparison
-   operator returns exactly 1 or -1 when the comparison is true and 0 when the
-   comparison is false.  Otherwise, the value indicates which bits of the
-   result are guaranteed to be 1 when the comparison is true.  This value is
-   interpreted in the mode of the comparison operation, which is given by the
-   mode of the first operand in the `sCOND' pattern.  Either the low bit or the
-   sign bit of `STORE_FLAG_VALUE' be on.  Presently, only those bits are used
-   by the compiler.
-
-   If `STORE_FLAG_VALUE' is neither 1 or -1, the compiler will generate code
-   that depends only on the specified bits.  It can also replace comparison
-   operators with equivalent operations if they cause the required bits to be
-   set, even if the remaining bits are undefined.  For example, on a machine
-   whose comparison operators return an `SImode' value and where
-   `STORE_FLAG_VALUE' is defined as `0x80000000', saying that just the sign bit
-   is relevant, the expression
-
-        (ne:SI (and:SI X (const_int POWER-OF-2)) (const_int 0))
-
-   can be converted to
-
-        (ashift:SI X (const_int N))
-
-   where N is the appropriate shift count to move the bit being tested into the
-   sign bit.
-
-   There is no way to describe a machine that always sets the low-order bit for
-   a true value, but does not guarantee the value of any other bits, but we do
-   not know of any machine that has such an instruction.  If you are trying to
-   port GNU CC to such a machine, include an instruction to perform a
-   logical-and of the result with 1 in the pattern for the comparison operators
-   and let us know (*note How to Report Bugs: Bug Reporting.).
-
-   Often, a machine will have multiple instructions that obtain a value from a
-   comparison (or the condition codes).  Here are rules to guide the choice of
-   value for `STORE_FLAG_VALUE', and hence the instructions to be used:
-
-      * Use the shortest sequence that yields a valid definition for
-        `STORE_FLAG_VALUE'.  It is more efficient for the compiler to
-        "normalize" the value (convert it to, e.g., 1 or 0) than for
-        the comparison operators to do so because there may be
-        opportunities to combine the normalization with other
-        operations.
-
-      * For equal-length sequences, use a value of 1 or -1, with -1
-        being slightly preferred on machines with expensive jumps and
-        1 preferred on other machines.
-
-      * As a second choice, choose a value of `0x80000001' if
-        instructions exist that set both the sign and low-order bits
-        but do not define the others.
-
-      * Otherwise, use a value of `0x80000000'.
-
-   Many machines can produce both the value chosen for `STORE_FLAG_VALUE' and
-   its negation in the same number of instructions.  On those machines, you
-   should also define a pattern for those cases, e.g., one matching
-
-        (set A (neg:M (ne:M B C)))
-
-   Some machines can also perform `and' or `plus' operations on condition code
-   values with less instructions than the corresponding `sCOND' insn followed
-   by `and' or `plus'.  On those machines, define the appropriate patterns.
-   Use the names `incscc' and `decscc', respectively, for the the patterns
-   which perform `plus' or `minus' operations on condition code values.  See
-   `rs6000.md' for some examples.  The GNU Superoptizer can be used to find
-   such instruction sequences on other machines.
-
-   You need not define `STORE_FLAG_VALUE' if the machine has no store-flag
-   instructions.  */
-/* #define STORE_FLAG_VALUE */
-
-/* A C expression that gives a non-zero floating point value that is returned
-   when comparison operators with floating-point results are true.  Define this
-   macro on machine that have comparison operations that return floating-point
-   values.  If there are no such operations, do not define this macro.  */
-/* #define FLOAT_STORE_FLAG_VALUE */
-
-/* An alias for the machine mode for pointers.  On most machines, define this
-   to be the integer mode corresponding to the width of a hardware pointer;
-   `SImode' on 32-bit machine or `DImode' on 64-bit machines.  On some machines
-   you must define this to be one of the partial integer modes, such as
-   `PSImode'.
-
-   The width of `Pmode' must be at least as large as the value of
-   `POINTER_SIZE'.  If it is not equal, you must define the macro
-   `POINTERS_EXTEND_UNSIGNED' to specify how pointers are extended to `Pmode'.  */
-#define Pmode SImode
-
-/* An alias for the machine mode used for memory references to functions being
-   called, in `call' RTL expressions.  On most machines this should be
-   `QImode'.  */
-#define FUNCTION_MODE QImode
-
-/* A C expression for the maximum number of instructions above which the
-   function DECL should not be inlined.  DECL is a `FUNCTION_DECL' node.
-
-   The default definition of this macro is 64 plus 8 times the number of
-   arguments that the function accepts.  Some people think a larger threshold
-   should be used on RISC machines.  */
-/* #define INTEGRATE_THRESHOLD(DECL) */
-
-/* Define this if the preprocessor should ignore `#sccs' directives and print
-   no error message.
-
-   Defined in svr4.h.  */
-/* #define SCCS_DIRECTIVE */
-
-/* Define this macro if the system header files support C++ as well as C.  This
-   macro inhibits the usual method of using system header files in C++, which
-   is to pretend that the file's contents are enclosed in `extern "C" {...}'.  */
-/* #define NO_IMPLICIT_EXTERN_C */
-
-/* Define this macro if you want to implement any pragmas.  If defined, it
-   should be a C statement to be executed when `#pragma' is seen.  The argument
-   STREAM is the stdio input stream from which the source text can be read.
-
-   It is generally a bad idea to implement new uses of `#pragma'.  The only
-   reason to define this macro is for compatibility with other compilers that
-   do support `#pragma' for the sake of any user programs which already use it.  */
-/* #define HANDLE_PRAGMA(STREAM) */
-
-/* Define this macro to handle System V style pragmas (particularly #pack).
-
-   Defined in svr4.h.  */
-#define HANDLE_SYSV_PRAGMA
-
-/* Define this macro if you want to handle #pragma weak (HANDLE_SYSV_PRAGMA
-   must also be defined).  */
-/* #define HANDLE_WEAK_PRAGMA */
-
-/* If defined, a C expression whose value is nonzero if IDENTIFIER with
-   arguments ARGS is a valid machine specific attribute for DECL.  The
-   attributes in ATTRIBUTES have previously been assigned to DECL.  */
-/* #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) */
-
-/* If defined, a C expression whose value is nonzero if IDENTIFIER with
-   arguments ARGS is a valid machine specific attribute for TYPE.  The
-   attributes in ATTRIBUTES have previously been assigned to TYPE.  */
-/* #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, IDENTIFIER, ARGS) */
-
-/* If defined, a C expression whose value is zero if the attributes on TYPE1
-   and TYPE2 are incompatible, one if they are compatible, and two if they are
-   nearly compatible (which causes a warning to be generated).  */
-/* #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) */
-
-/* If defined, a C statement that assigns default attributes to newly defined
-   TYPE.  */
-/* #define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) */
-
-/* Define this macro to control use of the character `$' in identifier names.
-   The value should be 0, 1, or 2.  0 means `$' is not allowed by default; 1
-   means it is allowed by default if `-traditional' is used; 2 means it is
-   allowed by default provided `-ansi' is not used.  1 is the default; there is
-   no need to define this macro in that case.  */
-/* #define DOLLARS_IN_IDENTIFIERS */
-
-/* Define this macro if the assembler does not accept the character `$' in
-   label names.  By default constructors and destructors in G++ have `$' in the
-   identifiers.  If this macro is defined, `.' is used instead.
-
-   Defined in svr4.h.  */
-/* #define NO_DOLLAR_IN_LABEL */
-
-/* Define this macro if the assembler does not accept the character `.' in
-   label names.  By default constructors and destructors in G++ have names that
-   use `.'.  If this macro is defined, these names are rewritten to avoid `.'.  */
-/* #define NO_DOT_IN_LABEL */
-
-/* Define this macro if the target system expects every program's `main'
-   function to return a standard "success" value by default (if no other value
-   is explicitly returned).
-
-   The definition should be a C statement (sans semicolon) to generate the
-   appropriate rtl instructions.  It is used only when compiling the end of
-   `main'.  */
-/* #define DEFAULT_MAIN_RETURN */
-
-/* Define this if the target system supports the function `atexit' from the
-   ANSI C standard.  If this is not defined, and `INIT_SECTION_ASM_OP' is not
-   defined, a default `exit' function will be provided to support C++.
-
-   Defined by svr4.h */
-/* #define HAVE_ATEXIT */
-
-/* Define this if your `exit' function needs to do something besides calling an
-   external function `_cleanup' before terminating with `_exit'.  The
-   `EXIT_BODY' macro is only needed if netiher `HAVE_ATEXIT' nor
-   `INIT_SECTION_ASM_OP' are defined.  */
-/* #define EXIT_BODY */
-
-/* Define this macro as a C expression that is nonzero if it is safe for the
-   delay slot scheduler to place instructions in the delay slot of INSN, even
-   if they appear to use a resource set or clobbered in INSN.  INSN is always a
-   `jump_insn' or an `insn'; GNU CC knows that every `call_insn' has this
-   behavior.  On machines where some `insn' or `jump_insn' is really a function
-   call and hence has this behavior, you should define this macro.
-
-   You need not define this macro if it would always return zero.  */
-/* #define INSN_SETS_ARE_DELAYED(INSN) */
-
-/* Define this macro as a C expression that is nonzero if it is safe for the
-   delay slot scheduler to place instructions in the delay slot of INSN, even
-   if they appear to set or clobber a resource referenced in INSN.  INSN is
-   always a `jump_insn' or an `insn'.  On machines where some `insn' or
-   `jump_insn' is really a function call and its operands are registers whose
-   use is actually in the subroutine it calls, you should define this macro.
-   Doing so allows the delay slot scheduler to move instructions which copy
-   arguments into the argument registers into the delay slot of INSN.
-
-   You need not define this macro if it would always return zero.  */
-/* #define INSN_REFERENCES_ARE_DELAYED(INSN) */
-
-/* In rare cases, correct code generation requires extra machine dependent
-   processing between the second jump optimization pass and delayed branch
-   scheduling.  On those machines, define this macro as a C statement to act on
-   the code starting at INSN.  */
-#define MACHINE_DEPENDENT_REORG(INSN) d30v_machine_dependent_reorg (INSN)
-
-/* Define this macro if in some cases global symbols from one translation unit
-   may not be bound to undefined symbols in another translation unit without
-   user intervention.  For instance, under Microsoft Windows symbols must be
-   explicitly imported from shared libraries (DLLs).  */
-/* #define MULTIPLE_SYMBOL_SPACES */
-
-/* A C expression for the maximum number of instructions to execute via
-   conditional execution instructions instead of a branch.  A value of
-   BRANCH_COST+1 is the default if the machine does not use cc0, and 1 if it
-   does use cc0. */
-#define MAX_CONDITIONAL_EXECUTE d30v_cond_exec
-
-#define D30V_DEFAULT_MAX_CONDITIONAL_EXECUTE 4
-
-/* Values of the -mcond-exec=n string.  */
-extern int d30v_cond_exec;
-extern char *d30v_cond_exec_string;
-
-/* Indicate how many instructions can be issued at the same time.  */
-#define ISSUE_RATE 2
-
-
-/* External functions called.  */
-
-#ifndef PROTO
-#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__)
-#define PROTO(ARGS) ARGS
-#else
-#define PROTO(ARGS) ()
-#endif
-#endif
-
-#ifdef BUFSIZ		/* stdio.h has been included, ok to use FILE * */
-#define STDIO_PROTO(ARGS) PROTO(ARGS)
-#else
-#define STDIO_PROTO(ARGS) ()
-#endif
-
-#ifndef TREE_CODE
-union tree_node;
-#define Tree union tree_node *
-#else
-#define Tree tree
-#endif
-
-#ifndef RTX_CODE
-struct rtx_def;
-#define Rtx struct rtx_def *
-#else
-#define Rtx rtx
-#endif
-
-extern void override_options			PROTO((void));
-extern int short_memory_operand			PROTO((Rtx, int));
-extern int long_memory_operand			PROTO((Rtx, int));
-extern int d30v_memory_operand			PROTO((Rtx, int));
-extern int single_reg_memory_operand		PROTO((Rtx, int));
-extern int const_addr_memory_operand		PROTO((Rtx, int));
-extern int call_operand				PROTO((Rtx, int));
-extern int gpr_operand				PROTO((Rtx, int));
-extern int accum_operand			PROTO((Rtx, int));
-extern int gpr_or_accum_operand			PROTO((Rtx, int));
-extern int cr_operand				PROTO((Rtx, int));
-extern int repeat_operand			PROTO((Rtx, int));
-extern int flag_operand				PROTO((Rtx, int));
-extern int br_flag_operand			PROTO((Rtx, int));
-extern int br_flag_or_constant_operand		PROTO((Rtx, int));
-extern int gpr_br_flag_operand			PROTO((Rtx, int));
-extern int f0_operand				PROTO((Rtx, int));
-extern int f1_operand				PROTO((Rtx, int));
-extern int carry_operand			PROTO((Rtx, int));
-extern int reg_or_0_operand			PROTO((Rtx, int));
-extern int gpr_or_signed6_operand		PROTO((Rtx, int));
-extern int gpr_or_unsigned5_operand		PROTO((Rtx, int));
-extern int gpr_or_unsigned6_operand		PROTO((Rtx, int));
-extern int gpr_or_constant_operand		PROTO((Rtx, int));
-extern int gpr_or_dbl_const_operand		PROTO((Rtx, int));
-extern int gpr_or_memory_operand		PROTO((Rtx, int));
-extern int move_input_operand			PROTO((Rtx, int));
-extern int move_output_operand			PROTO((Rtx, int));
-extern int signed6_operand			PROTO((Rtx, int));
-extern int unsigned5_operand			PROTO((Rtx, int));
-extern int unsigned6_operand			PROTO((Rtx, int));
-extern int bitset_operand			PROTO((Rtx, int));
-extern int condexec_test_operator		PROTO((Rtx, int));
-extern int condexec_branch_operator		PROTO((Rtx, int));
-extern int condexec_unary_operator		PROTO((Rtx, int));
-extern int condexec_addsub_operator		PROTO((Rtx, int));
-extern int condexec_binary_operator		PROTO((Rtx, int));
-extern int condexec_shiftl_operator		PROTO((Rtx, int));
-extern int condexec_extend_operator		PROTO((Rtx, int));
-extern int branch_zero_operator			PROTO((Rtx, int));
-extern int cond_move_operand			PROTO((Rtx, int));
-extern int cond_exec_operand			PROTO((Rtx, int));
-extern int srelational_si_operand		PROTO((Rtx, int));
-extern int urelational_si_operand		PROTO((Rtx, int));
-extern int relational_di_operand		PROTO((Rtx, int));
-extern d30v_stack_t *d30v_stack_info		PROTO((void));
-extern int direct_return			PROTO((void));
-
-extern void d30v_init_cumulative_args		PROTO((CUMULATIVE_ARGS *, Tree,
-						       Rtx, int, int));
-
-extern int d30v_function_arg_boundary		PROTO((int, Tree));
-extern Rtx d30v_function_arg			PROTO((CUMULATIVE_ARGS *, int,
-						       Tree, int, int));
-
-extern int d30v_function_arg_partial_nregs	PROTO((CUMULATIVE_ARGS *, int,
-						       Tree, int));
-
-extern int d30v_function_arg_pass_by_reference	PROTO((CUMULATIVE_ARGS *, int,
-						       Tree, int));
-
-extern void d30v_function_arg_advance		PROTO((CUMULATIVE_ARGS *, int,
-						       Tree, int));
-
-
-extern Rtx d30v_expand_builtin_saveregs		PROTO((Tree));
-extern void d30v_setup_incoming_varargs		PROTO((CUMULATIVE_ARGS *, int,
-						       Tree, int *, int));
-
-extern void d30v_function_prologue		STDIO_PROTO((FILE *, int));
-extern void d30v_function_epilogue		STDIO_PROTO((FILE *, int));
-extern void d30v_function_profiler		STDIO_PROTO((FILE *, int));
-extern void d30v_split_double			PROTO((Rtx, Rtx *, Rtx *));
-extern void d30v_print_operand			STDIO_PROTO((FILE *, Rtx, int));
-extern void d30v_print_operand_address		STDIO_PROTO((FILE *, Rtx));
-extern int d30v_trampoline_size			PROTO((void));
-extern void d30v_initialize_trampoline		PROTO((Rtx, Rtx, Rtx));
-extern int d30v_legitimate_address_p		PROTO((int, Rtx, int));
-extern Rtx d30v_legitimize_address		PROTO((Rtx, Rtx, int, int));
-extern int d30v_mode_dependent_address_p	PROTO((Rtx));
-extern Rtx d30v_emit_comparison			PROTO((int, Rtx, Rtx, Rtx));
-extern char *d30v_move_2words			PROTO((Rtx *, Rtx));
-extern int d30v_emit_cond_move			PROTO((Rtx, Rtx, Rtx, Rtx));
-extern char *d30v_cond_move			PROTO((Rtx *, Rtx, char *, char *));
-extern void d30v_machine_dependent_reorg	PROTO((Rtx));
-extern int d30v_adjust_cost			PROTO((Rtx, Rtx, Rtx, int));
-extern Rtx d30v_return_addr			PROTO((void));
-
-
-/* External variables referenced */
-
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  Note that we can't use "rtx" here
-   since it hasn't been defined!  */
-
-extern Rtx d30v_compare_op0;
-extern Rtx d30v_compare_op1;
-
-/* Define the information needed to modify the epilogue for EH.  */
-
-extern Rtx d30v_eh_epilogue_sp_ofs;
-
-/* Size of the accumulated function arguments.  */
-extern int current_function_outgoing_args_size;
-
-/* End of d30v.h */
-/* END CYGNUS LOCAL -- meissner/d30v */
diff --git a/gcc/config/d30v/d30v.md b/gcc/config/d30v/d30v.md
deleted file mode 100755
index 35d5b30..0000000
--- a/gcc/config/d30v/d30v.md
+++ /dev/null
@@ -1,3910 +0,0 @@
-;; CYGNUS LOCAL -- meissner/d30v
-;; D30v Machine description template
-;; Copyright (C) 1997, 1998 Free Software Foundation, Inc.
-;; Contributed by Cygnus Solutions.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Constraints
-;; ::
-;; ::::::::::::::::::::
-
-;; Standard Constraints
-;;
-;; `m' A memory operand is allowed, with any kind of address that the
-;;     machine supports in general.
-;;
-;; `o' A memory operand is allowed, but only if the address is
-;;     "offsettable".  This means that adding a small integer (actually, the
-;;     width in bytes of the operand, as determined by its machine mode) may be
-;;     added to the address and the result is also a valid memory address.
-;;
-;; `V' A memory operand that is not offsettable.  In other words,
-;;     anything that would fit the `m' constraint but not the `o' constraint.
-;;
-;; `<' A memory operand with autodecrement addressing (either
-;;     predecrement or postdecrement) is allowed.
-;;
-;; `>' A memory operand with autoincrement addressing (either
-;;     preincrement or postincrement) is allowed.
-;;
-;; `r' A register operand is allowed provided that it is in a general
-;;     register.
-;;
-;; `d', `a', `f', ...
-;;     Other letters can be defined in machine-dependent fashion to stand for
-;;     particular classes of registers.  `d', `a' and `f' are defined on the
-;;     68000/68020 to stand for data, address and floating point registers.
-;;
-;; `i' An immediate integer operand (one with constant value) is allowed.
-;;     This includes symbolic constants whose values will be known only at
-;;     assembly time.
-;;
-;; `n' An immediate integer operand with a known numeric value is allowed.
-;;     Many systems cannot support assembly-time constants for operands less
-;;     than a word wide.  Constraints for these operands should use `n' rather
-;;     than `i'.
-;;
-;; 'I' First machine-dependent integer constant.
-;; 'J' Second machine-dependent integer constant.
-;; 'K' Third machine-dependent integer constant.
-;; 'L' Fourth machine-dependent integer constant.
-;; 'M' Fifth machine-dependent integer constant.
-;; 'N' Sixth machine-dependent integer constant.
-;; 'O' Seventh machine-dependent integer constant.
-;; 'P' Eighth machine-dependent integer constant.
-;;
-;;     Other letters in the range `I' through `P' may be defined in a
-;;     machine-dependent fashion to permit immediate integer operands with
-;;     explicit integer values in specified ranges.  For example, on the 68000,
-;;     `I' is defined to stand for the range of values 1 to 8.  This is the
-;;     range permitted as a shift count in the shift instructions.
-;;
-;; `E' An immediate floating operand (expression code `const_double') is
-;;     allowed, but only if the target floating point format is the same as
-;;     that of the host machine (on which the compiler is running).
-;;
-;; `F' An immediate floating operand (expression code `const_double') is
-;;     allowed.
-;;
-;; 'G' First machine-dependent const_double.
-;; 'H' Second machine-dependent const_double.
-;;
-;; `s' An immediate integer operand whose value is not an explicit
-;;     integer is allowed.
-;;
-;;     This might appear strange; if an insn allows a constant operand with a
-;;     value not known at compile time, it certainly must allow any known
-;;     value.  So why use `s' instead of `i'?  Sometimes it allows better code
-;;     to be generated.
-;;
-;;     For example, on the 68000 in a fullword instruction it is possible to
-;;     use an immediate operand; but if the immediate value is between -128 and
-;;     127, better code results from loading the value into a register and
-;;     using the register.  This is because the load into the register can be
-;;     done with a `moveq' instruction.  We arrange for this to happen by
-;;     defining the letter `K' to mean "any integer outside the range -128 to
-;;     127", and then specifying `Ks' in the operand constraints.
-;;
-;; `g' Any register, memory or immediate integer operand is allowed,
-;;     except for registers that are not general registers.
-;;
-;; `X' Any operand whatsoever is allowed, even if it does not satisfy
-;;     `general_operand'.  This is normally used in the constraint of a
-;;     `match_scratch' when certain alternatives will not actually require a
-;;     scratch register.
-;;
-;; `0' Match operand 0.
-;; `1' Match operand 1.
-;; `2' Match operand 2.
-;; `3' Match operand 3.
-;; `4' Match operand 4.
-;; `5' Match operand 5.
-;; `6' Match operand 6.
-;; `7' Match operand 7.
-;; `8' Match operand 8.
-;; `9' Match operand 9.
-;;
-;;     An operand that matches the specified operand number is allowed.  If a
-;;     digit is used together with letters within the same alternative, the
-;;     digit should come last.
-;;
-;;     This is called a "matching constraint" and what it really means is that
-;;     the assembler has only a single operand that fills two roles considered
-;;     separate in the RTL insn.  For example, an add insn has two input
-;;     operands and one output operand in the RTL, but on most CISC machines an
-;;     add instruction really has only two operands, one of them an
-;;     input-output operand:
-;;
-;;          addl #35,r12
-;;
-;;     Matching constraints are used in these circumstances.  More precisely,
-;;     the two operands that match must include one input-only operand and one
-;;     output-only operand.  Moreover, the digit must be a smaller number than
-;;     the number of the operand that uses it in the constraint.
-;;
-;;     For operands to match in a particular case usually means that they are
-;;     identical-looking RTL expressions.  But in a few special cases specific
-;;     kinds of dissimilarity are allowed.  For example, `*x' as an input
-;;     operand will match `*x++' as an output operand.  For proper results in
-;;     such cases, the output template should always use the output-operand's
-;;     number when printing the operand.
-;;
-;; `p' An operand that is a valid memory address is allowed.  This is for
-;;     "load address" and "push address" instructions.
-;;
-;;     `p' in the constraint must be accompanied by `address_operand' as the
-;;     predicate in the `match_operand'.  This predicate interprets the mode
-;;     specified in the `match_operand' as the mode of the memory reference for
-;;     which the address would be valid.
-;;
-;; `Q` First non constant, non register machine-dependent insns
-;; `R` Second non constant, non register machine-dependent insns
-;; `S` Third non constant, non register machine-dependent insns
-;; `T` Fourth non constant, non register machine-dependent insns
-;; `U` Fifth non constant, non register machine-dependent insns
-;;
-;;     Letters in the range `Q' through `U' may be defined in a
-;;     machine-dependent fashion to stand for arbitrary operand types.  The
-;;     machine description macro `EXTRA_CONSTRAINT' is passed the operand as
-;;     its first argument and the constraint letter as its second operand.
-;;
-;;     A typical use for this would be to distinguish certain types of memory
-;;     references that affect other insn operands.
-;;
-;;     Do not define these constraint letters to accept register references
-;;     (`reg'); the reload pass does not expect this and would not handle it
-;;     properly.
-
-;; Multiple Alternative Constraints
-;; `?' Disparage slightly the alternative that the `?' appears in, as a
-;;     choice when no alternative applies exactly.  The compiler regards this
-;;     alternative as one unit more costly for each `?' that appears in it.
-;;
-;; `!' Disparage severely the alternative that the `!' appears in.  This
-;;     alternative can still be used if it fits without reloading, but if
-;;     reloading is needed, some other alternative will be used.
-
-;; Constraint modifiers
-;; `=' Means that this operand is write-only for this instruction: the
-;;     previous value is discarded and replaced by output data.
-;;
-;; `+' Means that this operand is both read and written by the
-;;     instruction.
-;;
-;;     When the compiler fixes up the operands to satisfy the constraints, it
-;;     needs to know which operands are inputs to the instruction and which are
-;;     outputs from it.  `=' identifies an output; `+' identifies an operand
-;;     that is both input and output; all other operands are assumed to be
-;;     input only.
-;;
-;; `&' Means (in a particular alternative) that this operand is written
-;;     before the instruction is finished using the input operands.  Therefore,
-;;     this operand may not lie in a register that is used as an input operand
-;;     or as part of any memory address.
-;;
-;;     `&' applies only to the alternative in which it is written.  In
-;;     constraints with multiple alternatives, sometimes one alternative
-;;     requires `&' while others do not.
-;;
-;;     `&' does not obviate the need to write `='.
-;;
-;; `%' Declares the instruction to be commutative for this operand and the
-;;     following operand.  This means that the compiler may interchange the two
-;;     operands if that is the cheapest way to make all operands fit the
-;;     constraints.  This is often used in patterns for addition instructions
-;;     that really have only two operands: the result must go in one of the
-;;     arguments.
-;;
-;; `#' Says that all following characters, up to the next comma, are to be
-;;     ignored as a constraint.  They are significant only for choosing
-;;     register preferences.
-;;
-;; `*' Says that the following character should be ignored when choosing
-;;     register preferences.  `*' has no effect on the meaning of the
-;;     constraint as a constraint, and no effect on reloading.
-
-;; ::::::::::::::::::::
-;; ::
-;; :: D30V register classes
-;; ::
-;; ::::::::::::::::::::
-
-;; `a'	Accumulator registers (a0, a1)
-;; `b'	Flag registers for speculative execution (f0, f1)
-;; `c'	CR registers
-;; `d'	GPR registers
-;; `e'	Even GPR registers
-;; `f'	Any flag registers (f0, f1, ..., c)
-;; `l'	CR7, the repeat count
-;; `x'	F0
-;; `y'	F1
-;; `z'	Flag registers other than F0 and F1.
-
-;; ::::::::::::::::::::
-;; ::
-;; :: D30V special constraints
-;; ::
-;; ::::::::::::::::::::
-
-;; `G'	Const double with 0 in both low & high part.
-;; `H'	Unused.
-;; `I'	Signed 6 bit integer constant (>= -32 && <= 31).
-;; `J'	Unsigned 5 bit integer constant (>= 0 && <= 31).
-;; `K'	Integer constant with 1 bit set (for bset).
-;; `L'	Integer constant with 1 bit clear (for bclr).
-;; `M'	Integer constant 32.
-;; `N'	Integer constant 1.
-;; `O'	Integer constant 0.
-;; `P'	Integer constant >= 32 && <= 63.
-;; `Q'	Short memory operand (can be done in small insn).
-;; `R'	Memory operand using a single register for address.
-;; `S'	Memory operand to constant address.
-;; `T'	Unused.
-;; `U'	Unused.
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Standard operand flags
-;; ::
-;; ::::::::::::::::::::
-
-;; `='  Output a number unique to each instruction in the compilation.
-;; `a'  Substitute an operand as if it were a memory reference.
-;; `c'  Omit the syntax that indicates an immediate operand.
-;; `l'  Substitute a LABEL_REF into a jump instruction.
-;; `n'  Like %cDIGIT, except negate the value before printing.
-
-;; ::::::::::::::::::::
-;; ::
-;; :: D30V print_operand flags
-;; ::
-;; ::::::::::::::::::::
-
-;; `.'	Print r0
-;; `f'  Print a SF constant as an int.
-;; `s'  Subtract 32 and negate.
-;; `A'  Print accumulator number without an `a' in front of it.
-;; `B'  Print bit offset for BSET, etc. instructions.
-;; `E'  Print u if this is zero extend, nothing if this is sign extend.
-;; `F'  Emit /{f,t,x}{f,t,x} for executing a false condition.
-;; `L'  Print the lower half of a 64 bit item.
-;; `M'  Print a memory reference for ld/st instructions.
-;; `R'  Return appropriate cmp instruction for relational test.
-;; `S'  Subtract 32.
-;; `T'  Emit /{f,t,x}{f,t,x} for executing a true condition.
-;; `U'  Print the upper half of a 64 bit item.
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Attributes
-;; ::
-;; ::::::::::::::::::::
-
-;; The `define_attr' expression is used to define each attribute required by
-;; the target machine.  It looks like:
-;;
-;; (define_attr NAME LIST-OF-VALUES DEFAULT)
-
-;; NAME is a string specifying the name of the attribute being defined.
-
-;; LIST-OF-VALUES is either a string that specifies a comma-separated list of
-;; values that can be assigned to the attribute, or a null string to indicate
-;; that the attribute takes numeric values.
-
-;; DEFAULT is an attribute expression that gives the value of this attribute
-;; for insns that match patterns whose definition does not include an explicit
-;; value for this attribute.
-
-;; For each defined attribute, a number of definitions are written to the
-;; `insn-attr.h' file.  For cases where an explicit set of values is specified
-;; for an attribute, the following are defined:
-
-;; * A `#define' is written for the symbol `HAVE_ATTR_NAME'.
-;;
-;; * An enumeral class is defined for `attr_NAME' with elements of the
-;;   form `UPPER-NAME_UPPER-VALUE' where the attribute name and value are first
-;;   converted to upper case.
-;;
-;; * A function `get_attr_NAME' is defined that is passed an insn and
-;;   returns the attribute value for that insn.
-
-;; For example, if the following is present in the `md' file:
-;;
-;; (define_attr "type" "branch,fp,load,store,arith" ...)
-;;
-;; the following lines will be written to the file `insn-attr.h'.
-;;
-;; #define HAVE_ATTR_type
-;; enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, TYPE_STORE, TYPE_ARITH};
-;; extern enum attr_type get_attr_type ();
-
-;; If the attribute takes numeric values, no `enum' type will be defined and
-;; the function to obtain the attribute's value will return `int'.
-
-;; Whether we are using the haifa scheduler
-(define_attr "haifa" "no,yes"
-  (const (symbol_ref "HAIFA_P")))
-
-;; Note, we lie a little bit here to make it simpler to optimize.  We pretend there
-;; is a separate long functional unit for long instructions that uses both the IU & MU.
-
-(define_attr "type" "iu,mu,br,br2,either,scarry,lcarry,scmp,lcmp,sload,lload,mul,long,multi,unknown"
-  (const_string "unknown"))
-
-;; Length in word units
-(define_attr "length" ""
-  (cond [(eq_attr "type" "iu,mu,either,scmp,sload,mul,scarry,")
-						(const_int 4)
-	 (eq_attr "type" "long,lcmp,lload,lcarry")
-						(const_int 8)
-	 (eq_attr "type" "multi,unknown")	(const_int 64)	;; set higher to give a fudge factor
-	 (eq_attr "type" "br")			(if_then_else (and (ge (minus (pc) (match_dup 0))
-								       (const_int -1048576))
-								   (lt (minus (pc) (match_dup 0))
-								       (const_int 1048575)))
-							      (const_int 4)
-							      (const_int 8))
-	 (eq_attr "type" "br2")			(if_then_else (and (ge (minus (pc) (match_dup 0))
-								       (const_int -16384))
-								   (lt (minus (pc) (match_dup 0))
-								       (const_int 16383)))
-							      (const_int 4)
-							      (const_int 8))]
-	(const_int 8)))
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Function Units
-;; ::
-;; ::::::::::::::::::::
-
-;; On most RISC machines, there are instructions whose results are not
-;; available for a specific number of cycles.  Common cases are instructions
-;; that load data from memory.  On many machines, a pipeline stall will result
-;; if the data is referenced too soon after the load instruction.
-
-;; In addition, many newer microprocessors have multiple function units,
-;; usually one for integer and one for floating point, and often will incur
-;; pipeline stalls when a result that is needed is not yet ready.
-
-;; The descriptions in this section allow the specification of how much time
-;; must elapse between the execution of an instruction and the time when its
-;; result is used.  It also allows specification of when the execution of an
-;; instruction will delay execution of similar instructions due to function
-;; unit conflicts.
-
-;; For the purposes of the specifications in this section, a machine is divided
-;; into "function units", each of which execute a specific class of
-;; instructions in first-in-first-out order.  Function units that accept one
-;; instruction each cycle and allow a result to be used in the succeeding
-;; instruction (usually via forwarding) need not be specified.  Classic RISC
-;; microprocessors will normally have a single function unit, which we can call
-;; `memory'.  The newer "superscalar" processors will often have function units
-;; for floating point operations, usually at least a floating point adder and
-;; multiplier.
-
-;; Each usage of a function units by a class of insns is specified with a
-;; `define_function_unit' expression, which looks like this:
-
-;; (define_function_unit NAME MULTIPLICITY SIMULTANEITY TEST READY-DELAY
-;;   ISSUE-DELAY [CONFLICT-LIST])
-
-;; NAME is a string giving the name of the function unit.
-
-;; MULTIPLICITY is an integer specifying the number of identical units in the
-;; processor.  If more than one unit is specified, they will be scheduled
-;; independently.  Only truly independent units should be counted; a pipelined
-;; unit should be specified as a single unit.  (The only common example of a
-;; machine that has multiple function units for a single instruction class that
-;; are truly independent and not pipelined are the two multiply and two
-;; increment units of the CDC 6600.)
-
-;; SIMULTANEITY specifies the maximum number of insns that can be executing in
-;; each instance of the function unit simultaneously or zero if the unit is
-;; pipelined and has no limit.
-
-;; All `define_function_unit' definitions referring to function unit NAME must
-;; have the same name and values for MULTIPLICITY and SIMULTANEITY.
-
-;; TEST is an attribute test that selects the insns we are describing in this
-;; definition.  Note that an insn may use more than one function unit and a
-;; function unit may be specified in more than one `define_function_unit'.
-
-;; READY-DELAY is an integer that specifies the number of cycles after which
-;; the result of the instruction can be used without introducing any stalls.
-
-;; ISSUE-DELAY is an integer that specifies the number of cycles after the
-;; instruction matching the TEST expression begins using this unit until a
-;; subsequent instruction can begin.  A cost of N indicates an N-1 cycle delay.
-;; A subsequent instruction may also be delayed if an earlier instruction has a
-;; longer READY-DELAY value.  This blocking effect is computed using the
-;; SIMULTANEITY, READY-DELAY, ISSUE-DELAY, and CONFLICT-LIST terms.  For a
-;; normal non-pipelined function unit, SIMULTANEITY is one, the unit is taken
-;; to block for the READY-DELAY cycles of the executing insn, and smaller
-;; values of ISSUE-DELAY are ignored.
-
-;; CONFLICT-LIST is an optional list giving detailed conflict costs for this
-;; unit.  If specified, it is a list of condition test expressions to be
-;; applied to insns chosen to execute in NAME following the particular insn
-;; matching TEST that is already executing in NAME.  For each insn in the list,
-;; ISSUE-DELAY specifies the conflict cost; for insns not in the list, the cost
-;; is zero.  If not specified, CONFLICT-LIST defaults to all instructions that
-;; use the function unit.
-
-;; Typical uses of this vector are where a floating point function unit can
-;; pipeline either single- or double-precision operations, but not both, or
-;; where a memory unit can pipeline loads, but not stores, etc.
-
-;; As an example, consider a classic RISC machine where the result of a load
-;; instruction is not available for two cycles (a single "delay" instruction is
-;; required) and where only one load instruction can be executed
-;; simultaneously.  This would be specified as:
-
-;; (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
-
-;; For the case of a floating point function unit that can pipeline
-;; either single or double precision, but not both, the following could be
-;; specified:
-;;
-;; (define_function_unit "fp" 1 0
-;;   (eq_attr "type" "sp_fp") 4 4
-;;   [(eq_attr "type" "dp_fp")])
-;;
-;; (define_function_unit "fp" 1 0
-;;   (eq_attr "type" "dp_fp") 4 4
-;;   [(eq_attr "type" "sp_fp")])
-
-;; Note: The scheduler attempts to avoid function unit conflicts and uses all
-;; the specifications in the `define_function_unit' expression.  It has
-;; recently come to our attention that these specifications may not allow
-;; modeling of some of the newer "superscalar" processors that have insns using
-;; multiple pipelined units.  These insns will cause a potential conflict for
-;; the second unit used during their execution and there is no way of
-;; representing that conflict.  We welcome any examples of how function unit
-;; conflicts work in such processors and suggestions for their representation.
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "haifa" "no")
-       (eq_attr "type" "iu,either"))
-  2 2
-  [(eq_attr "type" "long,lcmp,lload,multi,unknown")])
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "haifa" "yes")
-       (eq_attr "type" "iu,either"))
-  1 1
-  [(eq_attr "type" "long,lcmp,lload,multi,unknown")])
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "haifa" "no")
-       (eq_attr "type" "scmp,mul,scarry"))
-  4 2
-  [(eq_attr "type" "long,lcmp,lload,multi,unknown")])
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "haifa" "yes")
-       (eq_attr "type" "scmp,mul,scarry"))
-  2 1
-  [(eq_attr "type" "long,lcmp,lload,multi,unknown")])
-
-(define_function_unit "mu" 1 0
-  (and (eq_attr "haifa" "no")
-       (eq_attr "type" "mu,br,br2,scarry,scmp,sload,either"))
-  2 2
-  [(eq_attr "type" "long,lcmp,lload,multi,unknown")])
-
-(define_function_unit "mu" 1 0
-  (and (eq_attr "haifa" "yes")
-       (eq_attr "type" "mu,br,br2,either"))
-  1 1
-  [(eq_attr "type" "long,lcmp,lload,multi,unknown")])
-
-(define_function_unit "mu" 1 0
-  (and (eq_attr "haifa" "no")
-       (eq_attr "type" "scarry,scmp,sload"))
-  4 2
-  [(eq_attr "type" "long,lcmp,lload,multi,unknown")])
-
-(define_function_unit "mu" 1 0
-  (and (eq_attr "haifa" "yes")
-       (eq_attr "type" "scarry,scmp,sload"))
-  2 1
-  [(eq_attr "type" "long,lcmp,lload,multi,unknown")])
-
-(define_function_unit "long" 1 0
-  (and (eq_attr "haifa" "no")
-       (eq_attr "type" "long,multi,unknown"))
-  2 2
-  [(eq_attr "type" "iu,mu,scarry,scmp,sload,mul,br,br2,either")])
-
-(define_function_unit "long" 1 0
-  (and (eq_attr "haifa" "yes")
-       (eq_attr "type" "long,multi,unknown"))
-  1 1
-  [(eq_attr "type" "iu,mu,scarry,scmp,sload,mul,br,br2,either")])
-
-(define_function_unit "long" 1 0
-  (and (eq_attr "haifa" "no")
-       (eq_attr "type" "lcmp,lload,lcarry"))
-  4 2
-  [(eq_attr "type" "iu,mu,scarry,scmp,sload,mul,br,br2,either")])
-
-(define_function_unit "long" 1 0
-  (and (eq_attr "haifa" "yes")
-       (eq_attr "type" "lcmp,lload,lcarry"))
-  2 1
-  [(eq_attr "type" "iu,mu,scarry,scmp,sload,mul,br,br2,either")])
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Delay Slots
-;; ::
-;; ::::::::::::::::::::
-
-;; The insn attribute mechanism can be used to specify the requirements for
-;; delay slots, if any, on a target machine.  An instruction is said to require
-;; a "delay slot" if some instructions that are physically after the
-;; instruction are executed as if they were located before it.  Classic
-;; examples are branch and call instructions, which often execute the following
-;; instruction before the branch or call is performed.
-
-;; On some machines, conditional branch instructions can optionally "annul"
-;; instructions in the delay slot.  This means that the instruction will not be
-;; executed for certain branch outcomes.  Both instructions that annul if the
-;; branch is true and instructions that annul if the branch is false are
-;; supported.
-
-;; Delay slot scheduling differs from instruction scheduling in that
-;; determining whether an instruction needs a delay slot is dependent only
-;; on the type of instruction being generated, not on data flow between the
-;; instructions.  See the next section for a discussion of data-dependent
-;; instruction scheduling.
-
-;; The requirement of an insn needing one or more delay slots is indicated via
-;; the `define_delay' expression.  It has the following form:
-;;
-;; (define_delay TEST
-;;   [DELAY-1 ANNUL-TRUE-1 ANNUL-FALSE-1
-;;    DELAY-2 ANNUL-TRUE-2 ANNUL-FALSE-2
-;;    ...])
-
-;; TEST is an attribute test that indicates whether this `define_delay' applies
-;; to a particular insn.  If so, the number of required delay slots is
-;; determined by the length of the vector specified as the second argument.  An
-;; insn placed in delay slot N must satisfy attribute test DELAY-N.
-;; ANNUL-TRUE-N is an attribute test that specifies which insns may be annulled
-;; if the branch is true.  Similarly, ANNUL-FALSE-N specifies which insns in
-;; the delay slot may be annulled if the branch is false.  If annulling is not
-;; supported for that delay slot, `(nil)' should be coded.
-
-;; For example, in the common case where branch and call insns require a single
-;; delay slot, which may contain any insn other than a branch or call, the
-;; following would be placed in the `md' file:
-
-;; (define_delay (eq_attr "type" "branch,call")
-;;		 [(eq_attr "type" "!branch,call") (nil) (nil)])
-
-;; Multiple `define_delay' expressions may be specified.  In this case, each
-;; such expression specifies different delay slot requirements and there must
-;; be no insn for which tests in two `define_delay' expressions are both true.
-
-;; For example, if we have a machine that requires one delay slot for branches
-;; but two for calls, no delay slot can contain a branch or call insn, and any
-;; valid insn in the delay slot for the branch can be annulled if the branch is
-;; true, we might represent this as follows:
-
-;; (define_delay (eq_attr "type" "branch")
-;;   [(eq_attr "type" "!branch,call")
-;;    (eq_attr "type" "!branch,call")
-;;    (nil)])
-;;
-;; (define_delay (eq_attr "type" "call")
-;;   [(eq_attr "type" "!branch,call") (nil) (nil)
-;;    (eq_attr "type" "!branch,call") (nil) (nil)])
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Moves
-;; ::
-;; ::::::::::::::::::::
-
-;; Wrap moves in define_expand to prevent memory->memory moves from being
-;; generated at the RTL level, which generates better code for most machines
-;; which can't do mem->mem moves.
-
-;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
-;; than M, the effect of this instruction is to store the specified value in
-;; the part of the register that corresponds to mode M.  The effect on the rest
-;; of the register is undefined.
-
-;; This class of patterns is special in several ways.  First of all, each of
-;; these names *must* be defined, because there is no other way to copy a datum
-;; from one place to another.
-
-;; Second, these patterns are not used solely in the RTL generation pass.  Even
-;; the reload pass can generate move insns to copy values from stack slots into
-;; temporary registers.  When it does so, one of the operands is a hard
-;; register and the other is an operand that can need to be reloaded into a
-;; register.
-
-;; Therefore, when given such a pair of operands, the pattern must
-;; generate RTL which needs no reloading and needs no temporary
-;; registers--no registers other than the operands.  For example, if
-;; you support the pattern with a `define_expand', then in such a
-;; case the `define_expand' mustn't call `force_reg' or any other such
-;; function which might generate new pseudo registers.
-
-;; This requirement exists even for subword modes on a RISC machine
-;; where fetching those modes from memory normally requires several
-;; insns and some temporary registers.  Look in `spur.md' to see how
-;; the requirement can be satisfied.
-
-;; During reload a memory reference with an invalid address may be passed as an
-;; operand.  Such an address will be replaced with a valid address later in the
-;; reload pass.  In this case, nothing may be done with the address except to
-;; use it as it stands.  If it is copied, it will not be replaced with a valid
-;; address.  No attempt should be made to make such an address into a valid
-;; address and no routine (such as `change_address') that will do so may be
-;; called.  Note that `general_operand' will fail when applied to such an
-;; address.
-;;
-;; The global variable `reload_in_progress' (which must be explicitly declared
-;; if required) can be used to determine whether such special handling is
-;; required.
-;;
-;; The variety of operands that have reloads depends on the rest of
-;; the machine description, but typically on a RISC machine these can
-;; only be pseudo registers that did not get hard registers, while on
-;; other machines explicit memory references will get optional
-;; reloads.
-;;
-;; If a scratch register is required to move an object to or from memory, it
-;; can be allocated using `gen_reg_rtx' prior to reload.  But this is
-;; impossible during and after reload.  If there are cases needing scratch
-;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
-;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
-;; patterns `reload_inM' or `reload_outM' to handle them.  *Note Register
-;; Classes::.
-
-;; The constraints on a `moveM' must permit moving any hard register to any
-;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
-;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
-;; value of 2.
-
-;; It is obligatory to support floating point `moveM' instructions
-;; into and out of any registers that can hold fixed point values,
-;; because unions and structures (which have modes `SImode' or
-;; `DImode') can be in those registers and they may have floating
-;; point members.
-
-;; There may also be a need to support fixed point `moveM' instructions in and
-;; out of floating point registers.  Unfortunately, I have forgotten why this
-;; was so, and I don't know whether it is still true.  If `HARD_REGNO_MODE_OK'
-;; rejects fixed point values in floating point registers, then the constraints
-;; of the fixed point `moveM' instructions must be designed to avoid ever
-;; trying to reload into a floating point register.
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (!reload_in_progress && !reload_completed
-      && !register_operand (operands[0], QImode)
-      && !reg_or_0_operand (operands[1], QImode))
-    operands[1] = copy_to_mode_reg (QImode, operands[1]);
-}")
-
-(define_insn "*movqi_internal"
-  [(set (match_operand:QI 0 "move_output_operand" "=d,d,d,d,Q,m,Q,m,d,c")
-	(match_operand:QI 1 "move_input_operand" "dI,i,Q,m,d,d,O,O,c,d"))]
-  "register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode)"
-  "@
-    or %0,%.,%1
-    or %0,%.,%1
-    ldb %0,%M1
-    ldb %0,%M1
-    stb %1,%M0
-    stb %1,%M0
-    stb %.,%M0
-    stb %.,%M0
-    mvfsys %0,%1
-    mvtsys %0,%1"
-  [(set_attr "length" "4,8,4,8,4,8,4,8,4,4")
-   (set_attr "type" "either,long,sload,lload,mu,long,mu,long,mu,mu")])
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (!reload_in_progress && !reload_completed
-      && !register_operand (operands[0], HImode)
-      && !reg_or_0_operand (operands[1], HImode))
-    operands[1] = copy_to_mode_reg (HImode, operands[1]);
-}")
-
-(define_insn "*movhi_internal"
-  [(set (match_operand:HI 0 "move_output_operand" "=d,d,d,d,Q,m,Q,m,d,c")
-	(match_operand:HI 1 "move_input_operand" "dI,i,Q,m,d,d,O,O,c,d"))]
-  "register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode)"
-  "@
-    or %0,%.,%1
-    or %0,%.,%1
-    ldh %0,%M1
-    ldh %0,%M1
-    sth %1,%M0
-    sth %1,%M0
-    sth %.,%M0
-    sth %.,%M0
-    mvfsys %0,%1
-    mvtsys %0,%1"
-  [(set_attr "length" "4,8,4,8,4,8,4,8,4,4")
-   (set_attr "type" "either,long,sload,lload,mu,long,mu,long,mu,mu")])
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (!reload_in_progress && !reload_completed
-      && !register_operand (operands[0], SImode)
-      && !reg_or_0_operand (operands[1], SImode))
-    operands[1] = copy_to_mode_reg (SImode, operands[1]);
-
-  /* Convert addressing modes into the appropriate add/sub with the clobbers
-     needed.  This is generated by builtin_setjmp in the exception handling. */
-  if (GET_CODE (operands[1]) == PLUS)
-    {
-      emit_insn (gen_addsi3 (operands[0], XEXP (operands[1], 0),
-			     XEXP (operands[1], 1)));
-      DONE;
-    }
-
-  else if (GET_CODE (operands[1]) == MINUS)
-    {
-      emit_insn (gen_subsi3 (operands[0], XEXP (operands[1], 0),
-			     XEXP (operands[1], 1)));
-      DONE;
-    }
-}")
-
-(define_insn "*movsi_internal"
-  [(set (match_operand:SI 0 "move_output_operand" "=d,d,d,d,d,Q,m,Q,m,d,c")
-	(match_operand:SI 1 "move_input_operand" "dI,F,i,Q,m,d,d,O,O,c,d"))]
-  "register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)"
-  "@
-    or %0,%.,%1
-    or %0,%.,%L1
-    or %0,%.,%1
-    ldw %0,%M1
-    ldw %0,%M1
-    stw %1,%M0
-    stw %1,%M0
-    stw %.,%M0
-    stw %.,%M0
-    mvfsys %0,%1
-    mvtsys %0,%1"
-  [(set_attr "length" "4,8,8,4,8,4,8,4,8,4,4")
-   (set_attr "type" "either,long,long,sload,lload,mu,long,mu,long,mu,mu")])
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (!reload_in_progress && !reload_completed
-      && !register_operand (operands[0], DImode)
-      && !register_operand (operands[1], DImode))
-    operands[1] = copy_to_mode_reg (DImode, operands[1]);
-}")
-
-(define_insn "*movdi_internal"
-  [(set (match_operand:DI 0 "move_output_operand" "=e,e,e,e,Q,m,e,a,a")
-	(match_operand:DI 1 "move_input_operand" "eI,iF,Q,m,e,e,a,e,O"))]
-  "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
-  "* return d30v_move_2words (operands, insn);"
-  [(set_attr "length" "8,16,4,8,4,8,8,4,4")
-   (set_attr "type" "multi,multi,sload,lload,mu,long,multi,iu,iu")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(match_operand:DI 1 "gpr_or_dbl_const_operand" ""))]
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 5))]
-  "
-{
-  d30v_split_double (operands[0], &operands[2], &operands[4]);
-  d30v_split_double (operands[1], &operands[3], &operands[5]);
-}")
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (!reload_in_progress && !reload_completed
-      && !register_operand (operands[0], SFmode)
-      && !reg_or_0_operand (operands[1], SFmode))
-    operands[1] = copy_to_mode_reg (SFmode, operands[1]);
-}")
-
-(define_insn "*movsf_internal"
-  [(set (match_operand:SF 0 "move_output_operand" "=d,d,d,d,d,Q,m,Q,m")
-	(match_operand:SF 1 "move_input_operand" "d,G,F,Q,m,d,d,G,G"))]
-  "register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode)"
-  "@
-    or %0,%.,%1
-    or %0,%.,0
-    or %0,%.,%f1
-    ldw %0,%M1
-    ldw %0,%M1
-    stw %1,%M0
-    stw %1,%M0
-    stw %.,%M0
-    stw %.,%M0"
-  [(set_attr "length" "4,4,8,4,8,4,8,4,8")
-   (set_attr "type" "either,either,long,sload,lload,mu,long,mu,long")])
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (!reload_in_progress && !reload_completed
-      && !register_operand (operands[0], DFmode)
-      && !register_operand (operands[1], DFmode))
-    operands[1] = copy_to_mode_reg (DFmode, operands[1]);
-}")
-
-(define_insn "*movdf_internal"
-  [(set (match_operand:DF 0 "move_output_operand" "=e,e,e,e,Q,m,!*e,!*a")
-	(match_operand:DF 1 "move_input_operand" "eG,F,Q,m,e,e,!*a,!*e"))]
-  "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)"
-  "* return d30v_move_2words (operands, insn);"
-  [(set_attr "length" "8,16,4,8,4,8,8,4")
-   (set_attr "type" "multi,multi,sload,lload,mu,long,multi,iu")])
-
-(define_split
-  [(set (match_operand:DF 0 "gpr_operand" "")
-	(match_operand:DF 1 "gpr_or_dbl_const_operand" ""))]
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 5))]
-  "
-{
-  d30v_split_double (operands[0], &operands[2], &operands[4]);
-  d30v_split_double (operands[1], &operands[3], &operands[5]);
-}")
-
-(define_expand "movcc"
-  [(set (match_operand:CC 0 "general_operand" "")
-	(match_operand:CC 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (!reload_in_progress && !reload_completed
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    operands[1] = copy_to_mode_reg (CCmode, operands[1]);
-}")
-
-(define_insn "*movcc_internal"
-  [(set (match_operand:CC 0 "move_output_operand" "=f,f,f,d,f,d,*d,*d,*Q,*m")
-	(match_operand:CC 1 "move_input_operand" "f,O,N,f,d,dON,*Q,*m,*d,*d"))]
-  "!memory_operand (operands[0], CCmode) || !memory_operand (operands[1], CCmode)"
-  "@
-    orfg %0,%1,%1
-    andfg %0,%0,0
-    orfg %0,%0,1
-    mvfsys %0,%1
-    mvtsys %0,%1
-    or %0,%.,%1
-    ldb %0,%M1
-    ldb %0,%M1
-    stb %1,%M0
-    stb %1,%M0"
-  [(set_attr "length" "4,4,4,4,4,4,4,8,4,8")
-   (set_attr "type" "either,either,either,mu,mu,either,sload,lload,mu,long")])
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Conversions
-;; ::
-;; ::::::::::::::::::::
-
-;; Signed conversions from a smaller integer to a larger integer
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d")
-	(sign_extend:HI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))]
-  ""
-  "@
-    #
-    ldb %0,%M1
-    ldb %0,%M1"
-  [(set_attr "type" "multi,sload,lload")
-   (set_attr "length" "16,4,8")])
-
-(define_split
-  [(set (match_operand:HI 0 "gpr_operand" "")
-	(sign_extend:HI (match_operand:QI 1 "gpr_operand" "")))]
-  "reload_completed"
-  [(match_dup 2)
-   (match_dup 3)]
-  "
-{
-  rtx op0   = gen_lowpart (SImode, operands[0]);
-  rtx op1   = gen_lowpart (SImode, operands[1]);
-  rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
-
-  operands[2] = gen_ashlsi3 (op0, op1, shift);
-  operands[3] = gen_ashrsi3 (op0, op0, shift);
-}")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d")
-	(sign_extend:SI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))]
-  ""
-  "@
-    #
-    ldb %0,%M1
-    ldb %0,%M1"
-  [(set_attr "type" "multi,sload,lload")
-   (set_attr "length" "16,4,8")])
-
-(define_split
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(sign_extend:SI (match_operand:QI 1 "gpr_operand" "")))]
-  "reload_completed"
-  [(match_dup 2)
-   (match_dup 3)]
-  "
-{
-  rtx op0   = gen_lowpart (SImode, operands[0]);
-  rtx op1   = gen_lowpart (SImode, operands[1]);
-  rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
-
-  operands[2] = gen_ashlsi3 (op0, op1, shift);
-  operands[3] = gen_ashrsi3 (op0, op0, shift);
-}")
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d")
-	(sign_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "d,Q,m")))]
-  ""
-  "@
-    #
-    ldh %0,%M1
-    ldh %0,%M1"
-  [(set_attr "type" "multi,sload,lload")
-   (set_attr "length" "16,4,8")])
-
-(define_split
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(sign_extend:SI (match_operand:HI 1 "gpr_operand" "")))]
-  "reload_completed"
-  [(match_dup 2)
-   (match_dup 3)]
-  "
-{
-  rtx op0   = gen_lowpart (SImode, operands[0]);
-  rtx op1   = gen_lowpart (SImode, operands[1]);
-  rtx shift = gen_rtx (CONST_INT, VOIDmode, 16);
-
-  operands[2] = gen_ashlsi3 (op0, op1, shift);
-  operands[3] = gen_ashrsi3 (op0, op0, shift);
-}")
-
-(define_insn "extendqidi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(sign_extend:DI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))]
-  ""
-  "#"
-  [(set_attr "length" "12,8,12")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(sign_extend:DI (match_operand:QI 1 "gpr_or_memory_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
-   (set (match_dup 3) (ashiftrt:SI (match_dup 2) (const_int 31)))]
-  "
-{
-  d30v_split_double (operands[0], &operands[3], &operands[2]);
-}")
-
-(define_insn "extendhidi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(sign_extend:DI (match_operand:HI 1 "gpr_or_memory_operand" "d,Q,m")))]
-  ""
-  "#"
-  [(set_attr "length" "12,8,12")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(sign_extend:DI (match_operand:HI 1 "gpr_or_memory_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
-   (set (match_dup 3) (ashiftrt:SI (match_dup 2) (const_int 31)))]
-  "
-{
-  d30v_split_double (operands[0], &operands[3], &operands[2]);
-}")
-
-(define_insn "extendsidi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(sign_extend:DI (match_operand:SI 1 "gpr_or_memory_operand" "d,Q,m")))]
-  ""
-  "#"
-  [(set_attr "length" "8,8,12")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(sign_extend:DI (match_operand:SI 1 "gpr_or_memory_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 3) (ashiftrt:SI (match_dup 2) (const_int 31)))]
-  "
-{
-  d30v_split_double (operands[0], &operands[3], &operands[2]);
-}")
-	
-;; Unsigned conversions from a smaller integer to a larger integer
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "gpr_operand" "=d,d,d")
-	(zero_extend:HI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))]
-  ""
-  "@
-    and %0,%1,0xff
-    ldbu %0,%M1
-    ldbu %0,%M1"
-  [(set_attr "length" "8,4,8")
-   (set_attr "type" "long,sload,lload")])
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d")
-	(zero_extend:SI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))]
-  ""
-  "@
-    and %0,%1,0xff
-    ldbu %0,%M1
-    ldbu %0,%M1"
-  [(set_attr "length" "8,4,8")
-   (set_attr "type" "long,sload,lload")])
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d")
-	(zero_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "d,Q,m")))]
-  ""
-  "@
-    and %0,%1,0xffff
-    ldhu %0,%M1
-    ldhu %0,%M1"
-  [(set_attr "length" "8,4,8")
-   (set_attr "type" "long,sload,lload")])
-
-(define_insn "zero_extendqidi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(zero_extend:DI (match_operand:QI 1 "gpr_or_memory_operand" "d,Q,m")))]
-  ""
-  "#"
-  [(set_attr "length" "12,8,12")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(zero_extend:DI (match_operand:QI 1 "gpr_or_memory_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
-   (set (match_dup 3) (const_int 0))]
-  "
-{
-  d30v_split_double (operands[0], &operands[3], &operands[2]);
-}")
-
-(define_insn "zero_extendhidi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(zero_extend:DI (match_operand:HI 1 "gpr_or_memory_operand" "d,Q,m")))]
-  ""
-  "#"
-  [(set_attr "length" "8,8,12")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(zero_extend:DI (match_operand:HI 1 "gpr_or_memory_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
-   (set (match_dup 3) (const_int 0))]
-  "
-{
-  d30v_split_double (operands[0], &operands[3], &operands[2]);
-}")
-
-(define_insn "zero_extendsidi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(zero_extend:DI (match_operand:SI 1 "gpr_or_memory_operand" "d,Q,m")))]
-  ""
-  "#"
-  [(set_attr "length" "8,8,12")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(zero_extend:DI (match_operand:SI 1 "gpr_or_memory_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 3) (const_int 0))]
-  "
-{
-  d30v_split_double (operands[0], &operands[3], &operands[2]);
-}")
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: 32 bit Integer arithmetic
-;; ::
-;; ::::::::::::::::::::
-
-;; Addition
-(define_expand "addsi3"
-  [(parallel [(set (match_operand:SI 0 "gpr_operand" "")
-		   (plus:SI (match_operand:SI 1 "gpr_operand" "")
-			    (match_operand:SI 2 "gpr_or_constant_operand" "")))
-	      (clobber (match_dup 3))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))])]
-  ""
-  "
-{
-  operands[3] = gen_rtx (REG, CCmode, FLAG_CARRY);
-  operands[4] = gen_rtx (REG, CCmode, FLAG_OVERFLOW);
-  operands[5] = gen_rtx (REG, CCmode, FLAG_ACC_OVER);
-}")
-
-(define_insn "*addsi3_internal"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d")
-	(plus:SI (match_operand:SI 1 "gpr_operand" "%d,d")
-		 (match_operand:SI 2 "gpr_or_constant_operand" "dI,i")))
-   (clobber (match_operand:CC 3 "flag_operand" "f,f"))
-   (clobber (match_operand:CC 4 "flag_operand" "f,f"))
-   (clobber (match_operand:CC 5 "flag_operand" "f,f"))]
-  ""
-  "add %0,%1,%2"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "either,long")])
-
-;; Subtraction
-(define_expand "subsi3"
-  [(parallel [(set (match_operand:SI 0 "gpr_operand" "")
-		   (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
-			     (match_operand:SI 2 "gpr_or_constant_operand" "")))
-	      (clobber (match_dup 3))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))])]
-  ""
-  "
-{
-  operands[3] = gen_rtx (REG, CCmode, FLAG_CARRY);
-  operands[4] = gen_rtx (REG, CCmode, FLAG_OVERFLOW);
-  operands[5] = gen_rtx (REG, CCmode, FLAG_ACC_OVER);
-}")
-
-(define_insn "*subsi3_internal"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d,d")
-	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "d,d,O,O")
-		  (match_operand:SI 2 "gpr_or_constant_operand" "dI,i,dI,i")))
-   (clobber (match_operand:CC 3 "flag_operand" "f,f,f,f"))
-   (clobber (match_operand:CC 4 "flag_operand" "f,f,f,f"))
-   (clobber (match_operand:CC 5 "flag_operand" "f,f,f,f"))]
-  ""
-  "@
-    sub %0,%1,%2
-    sub %0,%1,%2
-    sub %0,%.,%2
-    sub %0,%.,%2"
-  [(set_attr "length" "4,8,4,8")
-   (set_attr "type" "either,long,either,long")])
-
-;; Multiplication (same size)
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(mult:SI (match_operand:SI 1 "gpr_operand" "%d")
-		 (match_operand:SI 2 "gpr_or_signed6_operand" "dI")))]
-  ""
-  "mul %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "mul")])
-
-;; Signed multiplication producing 64 bit results from 32 bit inputs
-(define_insn "mulsidi3"
-  [(set (match_operand:DI 0 "accum_operand" "=a")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "d"))
-		 (sign_extend:DI (match_operand:SI 2 "gpr_operand" "d"))))]
-  ""
-  "mulx %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "mul")])
-
-(define_insn "*mulsidi3_const"
-  [(set (match_operand:DI 0 "accum_operand" "=a")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "%d"))
-		 (match_operand:DI 2 "signed6_operand" "I")))]
-  ""
-  "mulx %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "mul")])
-
-;; Signed multiplication producing just the upper 32 bits from a 32x32->64
-;; bit multiply.  We specifically allow any integer constant here so
-;; allow division by constants to be done by multiplying by a large constant.
-
-(define_expand "smulsi3_highpart"
-  [(set (match_dup 3)
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" ""))
-		 (match_operand:SI 2 "gpr_or_constant_operand" "")))
-   (set (match_operand:SI 0 "gpr_operand" "")
-	(truncate:SI (lshiftrt:DI (match_dup 3)
-				  (const_int 32))))]
-  ""
-  "
-{
-  operands[3] = gen_reg_rtx (DImode);
-
-  if (GET_CODE (operands[2]) == CONST_INT &&
-      !IN_RANGE_P (INTVAL (operands[2]), -32, 31))
-    operands[2] = force_reg (SImode, operands[2]);
-
-  if (GET_CODE (operands[2]) == REG || GET_CODE (operands[2]) == SUBREG)
-    operands[2] = gen_rtx (SIGN_EXTEND, DImode, operands[2]);
-}")
-
-(define_insn "*di_highpart"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d")
-	(truncate:SI (lshiftrt:DI (match_operand:DI 1 "gpr_or_accum_operand" "e,a")
-		      (const_int 32))))]
-  ""
-  "@
-    or %0,%.,%U1
-    mvfacc %0,%1,32"
-  [(set_attr "length" "4")
-   (set_attr "type" "either,iu")])
-
-;; Negation
-(define_expand "negsi2"
-  [(parallel [(set (match_operand:SI 0 "gpr_operand" "")
-		   (neg:SI (match_operand:SI 1 "gpr_operand" "")))
-	      (clobber (match_dup 2))
-	      (clobber (match_dup 3))
-	      (clobber (match_dup 4))])]
-  ""
-  "
-{
-  operands[2] = gen_rtx (REG, CCmode, FLAG_CARRY);
-  operands[3] = gen_rtx (REG, CCmode, FLAG_OVERFLOW);
-  operands[4] = gen_rtx (REG, CCmode, FLAG_ACC_OVER);
-}")
-
-(define_insn "*negsi2_internal"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(neg:SI (match_operand:SI 1 "gpr_operand" "d")))
-   (clobber (match_operand:CC 2 "flag_operand" "=f"))
-   (clobber (match_operand:CC 3 "flag_operand" "=f"))
-   (clobber (match_operand:CC 4 "flag_operand" "=f"))]
-  ""
-  "sub %0,%.,%1"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-;; Absolute value
-(define_insn "abssi2"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(abs:SI (match_operand:SI 1 "gpr_operand" "d")))]
-  ""
-  "abs %0,%1"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: 64 bit Integer arithmetic
-;; ::
-;; ::::::::::::::::::::
-
-;; Addition
-(define_expand "adddi3"
-  [(parallel [(set (match_operand:DI 0 "gpr_operand" "")
-		   (plus:DI (match_operand:DI 1 "gpr_operand" "")
-			    (match_operand:DI 2 "gpr_or_constant_operand" "")))
-	      (clobber (match_dup 3))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))])]
-  ""
-  "
-{
-  operands[3] = gen_rtx (REG, CCmode, FLAG_CARRY);
-  operands[4] = gen_rtx (REG, CCmode, FLAG_OVERFLOW);
-  operands[5] = gen_rtx (REG, CCmode, FLAG_ACC_OVER);
-}")
-
-(define_insn "*adddi3_internal"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e,e")
-	(plus:DI (match_operand:DI 1 "gpr_operand" "%e,e,e,e")
-		 (match_operand:DI 2 "gpr_or_constant_operand" "I,i,e,F")))
-   (clobber (match_operand:CC 3 "flag_operand" "=f,f,f,f"))
-   (clobber (match_operand:CC 4 "flag_operand" "=f,f,f,f"))
-   (clobber (match_operand:CC 5 "flag_operand" "=f,f,f,f"))]
-  ""
-  "#"
-  [(set_attr "length" "8,12,8,16")
-   (set_attr "type" "multi")])
-
-(define_insn "addsi3_set_carry"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d")
-	(plus:SI (match_operand:SI 1 "gpr_operand" "%d,d")
-		 (match_operand:SI 2 "gpr_or_constant_operand" "dI,i")))
-   (set (match_operand:CC 3 "carry_operand" "=f,f")
-	(unspec [(match_dup 1)
-		 (match_dup 2)] 1))
-   (clobber (match_operand:CC 4 "flag_operand" "=f,f"))
-   (clobber (match_operand:CC 5 "flag_operand" "=f,f"))]
-  ""
-  "add %0,%1,%2"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "scarry,lcarry")])
-
-(define_insn "addsi3_use_carry"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d")
-	(unspec [(match_operand:SI 1 "gpr_operand" "%d,d")
-		 (match_operand:SI 2 "gpr_or_constant_operand" "dI,i")
-		 (match_operand:CC 3 "carry_operand" "+f,f")] 2))
-   (clobber (match_operand:CC 4 "flag_operand" "=f,f"))
-   (clobber (match_operand:CC 5 "flag_operand" "=f,f"))]
-  ""
-  "addc %0,%1,%2"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "scarry,lcarry")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(plus:DI (match_operand:DI 1 "gpr_operand" "")
-		 (match_operand:DI 2 "gpr_or_constant_operand" "")))
-   (clobber (match_operand:CC 3 "flag_operand" ""))
-   (clobber (match_operand:CC 4 "flag_operand" ""))
-   (clobber (match_operand:CC 5 "flag_operand" ""))]
-  "reload_completed"
-  [(match_dup 6)
-   (match_dup 7)]
-  "
-{
-  rtx high[3];
-  rtx low[3];
-
-  d30v_split_double (operands[0], &high[0], &low[0]);
-  d30v_split_double (operands[1], &high[1], &low[1]);
-  d30v_split_double (operands[2], &high[2], &low[2]);
-
-  operands[6] = gen_addsi3_set_carry (low[0], low[1], low[2], operands[3],
-				      operands[4], operands[5]);
-
-  operands[7] = gen_addsi3_use_carry (high[0], high[1], high[2], operands[3],
-				      operands[4], operands[5]);
-}")
-
-;; Subtraction
-(define_expand "subdi3"
-  [(parallel [(set (match_operand:DI 0 "gpr_operand" "")
-		   (minus:DI (match_operand:DI 1 "gpr_operand" "")
-			     (match_operand:DI 2 "gpr_or_constant_operand" "")))
-	      (clobber (match_dup 3))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))])]
-  ""
-  "
-{
-  operands[3] = gen_rtx (REG, CCmode, FLAG_CARRY);
-  operands[4] = gen_rtx (REG, CCmode, FLAG_OVERFLOW);
-  operands[5] = gen_rtx (REG, CCmode, FLAG_ACC_OVER);
-}")
-
-(define_insn "*subdi3_internal"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e,e")
-	(minus:DI (match_operand:DI 1 "gpr_operand" "e,e,e,e")
-		  (match_operand:DI 2 "gpr_or_constant_operand" "I,i,e,F")))
-   (clobber (match_operand:CC 3 "flag_operand" "=f,f,f,f"))
-   (clobber (match_operand:CC 4 "flag_operand" "=f,f,f,f"))
-   (clobber (match_operand:CC 5 "flag_operand" "=f,f,f,f"))]
-  ""
-  "#"
-  [(set_attr "length" "8,12,8,16")
-   (set_attr "type" "multi")])
-
-(define_insn "subsi3_set_carry"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d,d")
-	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "d,d,O,O")
-		  (match_operand:SI 2 "gpr_or_constant_operand" "dI,i,dI,i")))
-   (set (match_operand:CC 3 "carry_operand" "=f,f,f,f")
-	(unspec [(match_dup 1)
-		 (match_dup 2)] 3))
-   (clobber (match_operand:CC 4 "flag_operand" "=f,f,f,f"))
-   (clobber (match_operand:CC 5 "flag_operand" "=f,f,f,f"))]
-  ""
-  "@
-    sub %0,%1,%2
-    sub %0,%1,%2
-    sub %0,%.,%2
-    sub %0,%.,%2"
-  [(set_attr "length" "4,8,4,8")
-   (set_attr "type" "scarry,lcarry,scarry,lcarry")])
-
-(define_insn "subsi3_use_carry"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d,d")
-	(unspec [(match_operand:SI 1 "reg_or_0_operand" "d,d,O,O")
-		 (match_operand:SI 2 "gpr_operand" "dI,i,dI,i")
-		 (match_operand:CC 3 "carry_operand" "+f,f,f,f")] 4))
-   (clobber (match_operand:CC 4 "flag_operand" "=f,f,f,f"))
-   (clobber (match_operand:CC 5 "flag_operand" "=f,f,f,f"))]
-  ""
-  "@
-    subb %0,%1,%2
-    subb %0,%1,%2
-    subb %0,%.,%2
-    subb %0,%.,%2"
-  [(set_attr "length" "4,8,4,8")
-   (set_attr "type" "scarry,lcarry,scarry,lcarry")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(minus:DI (match_operand:DI 1 "gpr_operand" "")
-		  (match_operand:DI 2 "gpr_or_constant_operand" "")))
-   (clobber (match_operand:CC 3 "flag_operand" ""))
-   (clobber (match_operand:CC 4 "flag_operand" ""))
-   (clobber (match_operand:CC 5 "flag_operand" ""))]
-  "reload_completed"
-  [(match_dup 6)
-   (match_dup 7)]
-  "
-{
-  rtx high[3];
-  rtx low[3];
-
-  d30v_split_double (operands[0], &high[0], &low[0]);
-  d30v_split_double (operands[1], &high[1], &low[1]);
-  d30v_split_double (operands[2], &high[2], &low[2]);
-
-  operands[6] = gen_subsi3_set_carry (low[0], low[1], low[2], operands[3],
-				      operands[4], operands[5]);
-
-  operands[7] = gen_subsi3_use_carry (high[0], high[1], high[2], operands[3],
-				      operands[4], operands[5]);
-}")
-
-;; Negation
-(define_expand "negdi2"
-  [(parallel [(set (match_operand:DI 0 "gpr_operand" "")
-		   (neg:DI (match_operand:DI 1 "gpr_operand" "")))
-	      (clobber (match_dup 2))
-	      (clobber (match_dup 3))
-	      (clobber (match_dup 4))])]
-  ""
-  "
-{
-  operands[2] = gen_rtx (REG, CCmode, FLAG_CARRY);
-  operands[3] = gen_rtx (REG, CCmode, FLAG_OVERFLOW);
-  operands[4] = gen_rtx (REG, CCmode, FLAG_ACC_OVER);
-}")
-
-(define_insn "*negdi2_internal"
-  [(set (match_operand:DI 0 "gpr_operand" "=e")
-	(neg:DI (match_operand:DI 1 "gpr_operand" "e")))
-   (clobber (match_operand:CC 2 "flag_operand" "=f"))
-   (clobber (match_operand:CC 3 "flag_operand" "=f"))
-   (clobber (match_operand:CC 4 "flag_operand" "=f"))]
-  ""
-  "#"
-  [(set_attr "length" "8")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "=e")
-	(neg:DI (match_operand:DI 1 "gpr_operand" "e")))
-   (clobber (match_operand:CC 2 "flag_operand" "=f"))
-   (clobber (match_operand:CC 3 "flag_operand" "=f"))
-   (clobber (match_operand:CC 4 "flag_operand" "=f"))]
-  "reload_completed"
-  [(match_dup 5)
-   (match_dup 6)]
-  "
-{
-  rtx high[2];
-  rtx low[2];
-  rtx r0 = const0_rtx;
-
-  d30v_split_double (operands[0], &high[0], &low[0]);
-  d30v_split_double (operands[1], &high[1], &low[1]);
-
-  operands[5] = gen_subsi3_set_carry (low[0], r0, low[1], operands[2],
-				      operands[3], operands[4]);
-
-  operands[6] = gen_subsi3_use_carry (high[0], r0, high[1], operands[2],
-				      operands[3], operands[4]);
-}")
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: 32 bit Integer Shifts and Rotates
-;; ::
-;; ::::::::::::::::::::
-
-;; Arithmetic Shift Left (negate the shift value and use shift right)
-(define_expand "ashlsi3"
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(ashift:SI (match_operand:SI 1 "gpr_operand" "")
-		   (match_operand:SI 2 "gpr_or_unsigned5_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn "*ashlsi3_constant"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(ashift:SI (match_operand:SI 1 "gpr_operand" "d")
-		   (match_operand:SI 2 "unsigned5_operand" "J")))]
-  ""
-  "sra %0,%1,%n2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-(define_insn "*ashlsi3_register"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(ashift:SI (match_operand:SI 1 "gpr_operand" "d")
-		   (neg:SI (match_operand:SI 2 "gpr_operand" "d"))))]
-  ""
-  "sra %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-;; Arithmetic Shift Right
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(ashiftrt:SI (match_operand:SI 1 "gpr_operand" "d")
-		     (match_operand:SI 2 "gpr_or_unsigned5_operand" "dJ")))]
-  ""
-  "sra %0,%1,%2"
-  [(set_attr "length" "4")])
-
-;; Logical Shift Right
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(lshiftrt:SI (match_operand:SI 1 "gpr_operand" "d")
-		     (match_operand:SI 2 "gpr_or_unsigned5_operand" "dJ")))]
-  ""
-  "srl %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-;; Rotate Left (negate the shift value and use rotate right)
-(define_expand "rotlsi3"
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(rotate:SI (match_operand:SI 1 "gpr_operand" "")
-		   (match_operand:SI 2 "gpr_or_unsigned5_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn "*rotlsi3_constant"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(rotate:SI (match_operand:SI 1 "gpr_operand" "d")
-		   (match_operand:SI 2 "unsigned5_operand" "J")))]
-  ""
-  "rot %0,%1,%n2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-(define_insn "*rotlsi3_register"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(rotate:SI (match_operand:SI 1 "gpr_operand" "d")
-		   (neg:SI (match_operand:SI 2 "gpr_operand" "d"))))]
-  ""
-  "rot %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-;; Rotate Right
-(define_insn "rotrsi3"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(rotatert:SI (match_operand:SI 1 "gpr_operand" "d")
-		     (match_operand:SI 2 "gpr_or_unsigned5_operand" "dJ")))]
-  ""
-  "rot %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: 64 bit Integer Shifts and Rotates
-;; ::
-;; ::::::::::::::::::::
-
-;; Arithmetic Shift Left
-(define_expand "ashldi3"
-  [(parallel [(set (match_operand:DI 0 "gpr_operand" "")
-		   (ashift:DI (match_operand:DI 1 "gpr_operand" "")
-			      (match_operand:SI 2 "gpr_or_unsigned6_operand" "")))
-	      (clobber (match_scratch:CC 3 ""))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (IN_RANGE_P (INTVAL (operands[2]), 0, 63))
-	{
-	  emit_insn (gen_ashldi3_constant (operands[0], operands[1], operands[2]));
-	  DONE;
-	}
-      else
-	operands[2] = copy_to_mode_reg (SImode, operands[2]);
-    }
-
-  operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn "ashldi3_constant"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e")
-	(ashift:DI (match_operand:DI 1 "gpr_operand" "0,e")
-		   (match_operand:SI 2 "unsigned6_operand" "J,P")))]
-  ""
-  "@
-    src %U0,%L0,%n2\;sra %L0,%L0,%n2
-    sra %U0,%L1,%s2\;or %L0,%.,0"
-  [(set_attr "length" "8")
-   (set_attr "type" "multi")])
-
-(define_insn "*ashldi3_register"
-  [(set (match_operand:DI 0 "gpr_operand" "=e")
-	(ashift:DI (match_operand:DI 1 "gpr_operand" "0")
-		   (neg:SI (match_operand:SI 2 "gpr_operand" "d"))))
-   (clobber (match_scratch:CC 3 "=b"))]
-  ""
-  "cmpge %3,%2,-31\;src%T3 %U0,%L0,%2\;sra%T3 %L0,%L0,%2\;sub%F3 %U0,%2,-32\;sra%F3 %U0,%L0,%U0\;or%F3 %L0,%.,0"
-  [(set_attr "length" "32")
-   (set_attr "type" "multi")])
-
-;; Arithmetic Shift Right
-(define_insn "ashrdi3"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(ashiftrt:DI (match_operand:DI 1 "gpr_operand" "0,e,0")
-		     (match_operand:SI 2 "gpr_or_unsigned6_operand" "J,P,d")))
-   (clobber (match_scratch:CC 3 "=X,X,b"))]
-  ""
-  "@
-    src %L0,%U0,%2\;sra %U0,%U0,%2
-    sra %L0,%U1,%S2\;sra %U0,%L0,31
-    cmple %3,%2,31\;src%T3 %L0,%U0,%2\;sra%T3 %U0,%U0,%2\;add%F3 %L0,%2,-32\;sra%F3 %L0,%U0,%L0\;sra%F3 %U0,%U0,31"
-  [(set_attr "length" "8,8,28")
-   (set_attr "type" "multi")])
-
-;; Logical Shift Right
-
-(define_insn "lshrdi3"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,e")
-	(lshiftrt:DI (match_operand:DI 1 "gpr_operand" "0,e,0")
-		     (match_operand:SI 2 "gpr_or_unsigned6_operand" "J,P,d")))
-   (clobber (match_scratch:CC 3 "=X,X,b"))]
-  ""
-  "@
-    src %L0,%U0,%2\;srl %U0,%U0,%2
-    srl %L0,%U1,%S2\;or %U0,%.,0
-    cmple %3,%2,31\;src%T3 %L0,%U0,%2\;srl%T3 %U0,%U0,%2\;add%F3 %L0,%2,-32\;srl%F3 %L0,%U0,%L0\;or%F3 %U0,%.,0"
-  [(set_attr "length" "8,8,28")
-   (set_attr "type" "multi")])
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: 32 Bit Integer Logical operations
-;; ::
-;; ::::::::::::::::::::
-
-;; Logical AND, 32 bit integers
-(define_expand "andsi3"
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(and:SI (match_operand:SI 1 "gpr_operand" "")
-		(match_operand:SI 2 "gpr_or_constant_operand" "")))]
-  ""
-  "")
-
-(define_insn "*andsi3_register"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(and:SI (match_operand:SI 1 "gpr_operand" "%d")
-		(match_operand:SI 2 "gpr_operand" "d")))]
-  ""
-  "and %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-(define_insn "*andsi3_move"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d")
-	(and:SI (match_operand:SI 1 "gpr_operand" "%0,d")
-		(match_operand:SI 2 "const_int_operand" "n,n")))]
-  "((INTVAL (operands[2]) & 0xffffffff) == 0xffffffff)"
-  "@
-    ; and 0xffffffff to same register
-    and %0,%1,-1"
-  [(set_attr "length" "0,4")
-   (set_attr "type" "either")])
-
-(define_insn "*andsi3_constant"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d,d")
-	(and:SI (match_operand:SI 1 "gpr_operand" "%d,d,d,d")
-		(match_operand:SI 2 "const_int_operand" "L,O,I,i")))]
-  ""
-  "@
-    bclr %0,%1,%B2
-    or %0,%.,0
-    and %0,%1,%2
-    and %0,%1,%2"
-  [(set_attr "length" "4,4,4,8")
-   (set_attr "type" "either,either,either,long")])
-
-(define_insn "*andsi3_bclr"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(and:SI (match_operand:SI 1 "gpr_operand" "d")
-		(not:SI (lshiftrt:SI (const_int -2147483648)
-				     (match_operand:SI 2 "gpr_operand" "d")))))]
-  ""
-  "bclr %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-;; Inclusive OR, 32 bit integers
-(define_expand "iorsi3"
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(ior:SI (match_operand:SI 1 "gpr_operand" "")
-		(match_operand:SI 2 "gpr_or_constant_operand" "")))]
-  ""
-  "")
-
-(define_insn "*iorsi3_register"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(ior:SI (match_operand:SI 1 "gpr_operand" "%d")
-		(match_operand:SI 2 "gpr_operand" "d")))]
-  ""
-  "or %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-(define_insn "*iorsi3_constant"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d,d")
-	(ior:SI (match_operand:SI 1 "gpr_operand" "%d,0,d,d")
-		(match_operand:SI 2 "const_int_operand" "K,O,I,i")))]
-  ""
-  "@
-    bset %0,%1,%B2
-    ; or 0 to same register (%0)
-    or %0,%1,%2
-    or %0,%1,%2"
-  [(set_attr "length" "4,0,4,8")
-   (set_attr "type" "either,either,either,long")])
-
-(define_insn "*iorsi3_bset"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(ior:SI (match_operand:SI 1 "gpr_operand" "d")
-		(lshiftrt:SI (const_int -2147483648)
-			     (match_operand:SI 2 "gpr_operand" "d"))))]
-  ""
-  "bset %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-;; Exclusive OR, 32 bit integers
-(define_expand "xorsi3"
-  [(set (match_operand:SI 0 "gpr_operand" "")
-	(xor:SI (match_operand:SI 1 "gpr_operand" "")
-		(match_operand:SI 2 "gpr_or_constant_operand" "")))]
-  ""
-  "")
-
-(define_insn "*xorsi3_register"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(xor:SI (match_operand:SI 1 "gpr_operand" "%d")
-		(match_operand:SI 2 "gpr_operand" "d")))]
-  ""
-  "xor %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-(define_insn "*xorsi3_constant"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d,d,d")
-	(xor:SI (match_operand:SI 1 "gpr_operand" "%d,0,d,d")
-		(match_operand:SI 2 "const_int_operand" "K,O,I,i")))]
-  ""
-  "@
-    bnot %0,%1,%B2
-    ; xor 0 to same register (%0)
-    xor %0,%1,%2
-    xor %0,%1,%2"
-  [(set_attr "length" "4,0,4,8")
-   (set_attr "type" "either,either,either,long")])
-
-(define_insn "*iorsi3_bnot"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(xor:SI (match_operand:SI 1 "gpr_operand" "d")
-		(lshiftrt:SI (const_int -2147483648)
-			     (match_operand:SI 2 "gpr_operand" "d"))))]
-  ""
-  "bnot %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-;; One's complement, 32 bit integers
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(not:SI (match_operand:SI 1 "gpr_operand" "d")))]
-  ""
-  "not %0,%1"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: 64 Bit Integer Logical operations
-;; ::
-;; ::::::::::::::::::::
-
-;; Logical AND, 64 bit integers
-(define_insn "anddi3"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,&e,e,e,e")
-	(and:DI (match_operand:DI 1 "gpr_operand" "%e,0,e,e,e,e")
-		(match_operand:DI 2 "gpr_or_dbl_const_operand" "0,e,e,I,i,F")))]
-  ""
-  "#"
-  [(set_attr "length" "8,8,8,8,12,16")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(and:DI (match_operand:DI 1 "gpr_operand" "")
-		(match_operand:DI 2 "gpr_or_dbl_const_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 3) (and:SI (match_dup 4) (match_dup 5)))
-   (set (match_dup 6) (and:SI (match_dup 7) (match_dup 8)))]
-  "
-{
-  d30v_split_double (operands[0], &operands[3], &operands[6]);
-  d30v_split_double (operands[1], &operands[4], &operands[7]);
-  d30v_split_double (operands[2], &operands[5], &operands[8]);
-}")
-
-;; Includive OR, 64 bit integers
-(define_insn "iordi3"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,&e,e,e,e")
-	(ior:DI (match_operand:DI 1 "gpr_operand" "%e,0,e,e,e,e")
-		(match_operand:DI 2 "gpr_or_dbl_const_operand" "0,e,e,I,i,F")))]
-  ""
-  "#"
-  [(set_attr "length" "8,8,8,8,12,16")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(ior:DI (match_operand:DI 1 "gpr_operand" "")
-		(match_operand:DI 2 "gpr_or_dbl_const_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 3) (ior:SI (match_dup 4) (match_dup 5)))
-   (set (match_dup 6) (ior:SI (match_dup 7) (match_dup 8)))]
-  "
-{
-  d30v_split_double (operands[0], &operands[3], &operands[6]);
-  d30v_split_double (operands[1], &operands[4], &operands[7]);
-  d30v_split_double (operands[2], &operands[5], &operands[8]);
-}")
-
-;; Excludive OR, 64 bit integers
-(define_insn "xordi3"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,e,&e,e,e,e")
-	(xor:DI (match_operand:DI 1 "gpr_operand" "%e,0,e,e,e,e")
-		(match_operand:DI 2 "gpr_or_dbl_const_operand" "0,e,e,I,i,F")))]
-  ""
-  "#"
-  [(set_attr "length" "8,8,8,8,12,16")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(xor:DI (match_operand:DI 1 "gpr_operand" "")
-		(match_operand:DI 2 "gpr_or_dbl_const_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 3) (xor:SI (match_dup 4) (match_dup 5)))
-   (set (match_dup 6) (xor:SI (match_dup 7) (match_dup 8)))]
-  "
-{
-  d30v_split_double (operands[0], &operands[3], &operands[6]);
-  d30v_split_double (operands[1], &operands[4], &operands[7]);
-  d30v_split_double (operands[2], &operands[5], &operands[8]);
-}")
-
-;; One's complement, 64 bit integers
-(define_insn "one_cmpldi2"
-  [(set (match_operand:DI 0 "gpr_operand" "=e,&e")
-	(not:DI (match_operand:DI 1 "gpr_operand" "0,e")))]
-  ""
-  "#"
-  [(set_attr "length" "8")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpr_operand" "")
-	(not:DI (match_operand:DI 1 "gpr_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 3) (not:SI (match_dup 4)))
-   (set (match_dup 5) (not:SI (match_dup 6)))]
-  "
-{
-  d30v_split_double (operands[0], &operands[3], &operands[5]);
-  d30v_split_double (operands[1], &operands[4], &operands[6]);
-}")
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Multiply and accumulate instructions
-;; ::
-;; ::::::::::::::::::::
-
-(define_insn "*mac_reg"
-  [(set (match_operand:DI 0 "accum_operand" "+a")
-	(plus:DI (match_dup 0)
-		 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "%d"))
-			  (sign_extend:DI (match_operand:SI 2 "gpr_operand" "d")))))]
-  ""
-  "mac%A0 %.,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "mul")])
-
-(define_insn "*mac_const"
-  [(set (match_operand:DI 0 "accum_operand" "+a")
-	(plus:DI (match_dup 0)
-		 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "%d"))
-			  (match_operand:DI 2 "signed6_operand" "I"))))]
-  ""
-  "mac%A0 %.,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "mul")])
-
-(define_insn "*macs_reg"
-  [(set (match_operand:DI 0 "accum_operand" "+a")
-	(plus:DI (match_dup 0)
-		 (ashift:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "%d"))
-				     (sign_extend:DI (match_operand:SI 2 "gpr_operand" "d")))
-			    (const_int 1))))]
-  ""
-  "macs%A0 %.,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "mul")])
-
-(define_insn "*macs_const"
-  [(set (match_operand:DI 0 "accum_operand" "+a")
-	(plus:DI (match_dup 0)
-		 (ashift:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "%d"))
-				     (match_operand:DI 2 "signed6_operand" "I"))
-			    (const_int 1))))]
-  ""
-  "macs%A0 %.,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "mul")])
-
-(define_insn "*msub_reg"
-  [(set (match_operand:DI 0 "accum_operand" "+a")
-	(minus:DI (match_dup 0)
-		  (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "d"))
-			   (sign_extend:DI (match_operand:SI 2 "gpr_operand" "d")))))]
-  ""
-  "msub%A0 %.,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "mul")])
-
-(define_insn "*msub_const"
-  [(set (match_operand:DI 0 "accum_operand" "+a")
-	(minus:DI (match_dup 0)
-		  (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "d"))
-			   (match_operand:DI 2 "signed6_operand" "I"))))]
-  ""
-  "msub%A0 %.,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "mul")])
-
-(define_insn "*msubs_reg"
-  [(set (match_operand:DI 0 "accum_operand" "+a")
-	(minus:DI (match_dup 0)
-		  (ashift:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "d"))
-				      (sign_extend:DI (match_operand:SI 2 "gpr_operand" "d")))
-			     (const_int 1))))]
-  ""
-  "msubs%A0 %.,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "mul")])
-
-(define_insn "*msubs_const"
-  [(set (match_operand:DI 0 "accum_operand" "+a")
-	(minus:DI (match_dup 0)
-		  (ashift:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "gpr_operand" "d"))
-				      (match_operand:DI 2 "signed6_operand" "I"))
-			     (const_int 1))))]
-  ""
-  "msubs%A0 %.,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "mul")])
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Comparisons
-;; ::
-;; ::::::::::::::::::::
-
-;; Note, we store the operands in the comparison insns, and use them later
-;; when generating the branch or scc operation.
-
-;; First the routines called by the machine independent part of the compiler
-(define_expand "cmpsi"
-  [(set (cc0)
-        (compare (match_operand:SI 0 "gpr_operand" "")
-  		 (match_operand:SI 1 "gpr_or_constant_operand" "")))]
-  ""
-  "
-{
-  d30v_compare_op0 = operands[0];
-  d30v_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "cmpdi"
-  [(set (cc0)
-        (compare (match_operand:DI 0 "gpr_operand" "")
-  		 (match_operand:DI 1 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  d30v_compare_op0 = operands[0];
-  d30v_compare_op1 = operands[1];
-  DONE;
-}")
-
-;; Now, the actual comparisons, generated by the branch and/or scc operations
-
-;; 32 bit integer tests
-(define_insn "*srelational"
-  [(set (match_operand:CC 0 "flag_operand" "=f,f")
-	(match_operator:CC 1 "srelational_si_operator"
-			   [(match_operand:SI 2 "gpr_operand" "d,d")
-			    (match_operand:SI 3 "gpr_or_constant_operand" "dI,i")]))]
-  ""
-  "%R1 %0,%2,%3"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "scmp,lcmp")])
-
-(define_insn "*urelational"
-  [(set (match_operand:CC 0 "flag_operand" "=f,f")
-	(match_operator:CC 1 "urelational_si_operator"
-			   [(match_operand:SI 2 "gpr_operand" "d,d")
-			    (match_operand:SI 3 "gpr_or_constant_operand" "dJP,i")]))]
-  ""
-  "%R1 %0,%2,%3"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "scmp,lcmp")])
-
-;; Code used after splitting DI compares
-
-(define_insn "*movcccc_signed_true"
-  [(set (match_operand:CC 0 "flag_operand" "=f,f")
-	(if_then_else:CC (match_operand:CC 1 "br_flag_operand" "f,f")
-			 (match_operator:CC 3 "srelational_si_operator"
-					    [(match_operand:SI 4 "gpr_operand" "d,d")
-					     (match_operand:SI 5 "gpr_or_constant_operand" "dI,i")])
-			 (match_dup 0)))]
-  ""
-  "%R3%T1 %0,%4,%5"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "scmp,lcmp")])
-
-(define_insn "*movcccc_signed_false"
-  [(set (match_operand:CC 0 "flag_operand" "=f,f")
-	(if_then_else:CC (match_operand:CC 1 "br_flag_operand" "f,f")
-			 (match_dup 0)
-			 (match_operator:CC 3 "srelational_si_operator"
-					    [(match_operand:SI 4 "gpr_operand" "d,d")
-					     (match_operand:SI 5 "gpr_or_constant_operand" "dI,i")])))]
-  ""
-  "%R3%F1 %0,%4,%5"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "scmp,lcmp")])
-
-(define_insn "*movcccc_unsigned_true"
-  [(set (match_operand:CC 0 "flag_operand" "=f,f")
-	(if_then_else:CC (match_operand:CC 1 "br_flag_operand" "f,f")
-			 (match_operator:CC 3 "urelational_si_operator"
-					    [(match_operand:SI 4 "gpr_operand" "d,d")
-					     (match_operand:SI 5 "gpr_or_constant_operand" "dJP,i")])
-			 (match_dup 0)))]
-  ""
-  "%R3%T1 %0,%4,%5"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "scmp,lcmp")])
-
-(define_insn "*movcccc_unsigned_false"
-  [(set (match_operand:CC 0 "flag_operand" "=f,f")
-	(if_then_else:CC (match_operand:CC 1 "br_flag_operand" "f,f")
-			 (match_dup 0)
-			 (match_operator:CC 3 "urelational_si_operator"
-					    [(match_operand:SI 4 "gpr_operand" "d,d")
-					     (match_operand:SI 5 "gpr_or_constant_operand" "dJP,i")])))]
-  ""
-  "%R3%F1 %0,%4,%5"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "scmp,lcmp")])
-
-;; 64 bit integer tests
-(define_insn "*eqdi_internal"
-  [(set (match_operand:CC 0 "br_flag_operand" "=b,b,b")
-	(eq:CC (match_operand:DI 1 "gpr_operand" "e,e,e")
-	       (match_operand:DI 2 "gpr_or_dbl_const_operand" "eI,i,F")))]
-  ""
-  "#"
-  [(set_attr "length" "8,12,16")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:CC 0 "br_flag_operand" "")
-	(eq:CC (match_operand:DI 1 "gpr_operand" "")
-	       (match_operand:DI 2 "gpr_or_dbl_const_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(eq:CC (match_dup 3)
-	       (match_dup 4)))
-   (set (match_dup 0)
-	(if_then_else:CC (match_dup 0)
-			 (eq:CC (match_dup 5)
-				(match_dup 6))
-			 (match_dup 0)))]
-  "
-{
-  d30v_split_double (operands[1], &operands[3], &operands[5]);
-  d30v_split_double (operands[2], &operands[4], &operands[6]);
-}")
-
-(define_insn "*nedi_internal"
-  [(set (match_operand:CC 0 "br_flag_operand" "=b,b,b")
-	(ne:CC (match_operand:DI 1 "gpr_operand" "e,e,e")
-	       (match_operand:DI 2 "gpr_or_dbl_const_operand" "eI,i,F")))]
-  ""
-  "#"
-  [(set_attr "length" "8,12,16")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:CC 0 "br_flag_operand" "")
-	(ne:CC (match_operand:DI 1 "gpr_operand" "")
-	       (match_operand:DI 2 "gpr_or_dbl_const_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(ne:CC (match_dup 3)
-	       (match_dup 4)))
-   (set (match_dup 0)
-	(if_then_else:CC (match_dup 0)
-			 (match_dup 0)
-			 (ne:CC (match_dup 5)
-				(match_dup 6))))]
-  "
-{
-  d30v_split_double (operands[1], &operands[3], &operands[5]);
-  d30v_split_double (operands[2], &operands[4], &operands[6]);
-}")
-
-(define_insn "*ltdi_zero"
-  [(set (match_operand:CC 0 "flag_operand" "=f")
-	(lt:CC (match_operand:DI 1 "gpr_operand" "e")
-	       (const_int 0)))]
-  ""
-  "cmplt %0,%U1,0"
-  [(set_attr "length" "4")
-   (set_attr "type" "scmp")])
-
-(define_insn "*ltdi_internal"
-  [(set (match_operand:CC 0 "flag_operand" "=&f,&f,&f")
-	(lt:CC (match_operand:DI 1 "gpr_operand" "e,e,e")
-	       (match_operand:DI 2 "gpr_or_dbl_const_operand" "eJP,i,F")))
-   (clobber (match_operand:CC 3 "br_flag_operand" "=&b,&b,&b"))]
-  ""
-  "#"
-  [(set_attr "length" "12,16,24")
-   (set_attr "type" "multi")])
-
-(define_insn "*ledi_internal"
-  [(set (match_operand:CC 0 "flag_operand" "=&f,&f,&f")
-	(le:CC (match_operand:DI 1 "gpr_operand" "e,e,e")
-	       (match_operand:DI 2 "gpr_or_dbl_const_operand" "eJP,i,F")))
-   (clobber (match_operand:CC 3 "br_flag_operand" "=&b,&b,&b"))]
-  ""
-  "#"
-  [(set_attr "length" "12,16,24")
-   (set_attr "type" "multi")])
-
-(define_insn "*gtdi_internal"
-  [(set (match_operand:CC 0 "flag_operand" "=&f,&f,&f")
-	(gt:CC (match_operand:DI 1 "gpr_operand" "e,e,e")
-	       (match_operand:DI 2 "gpr_or_dbl_const_operand" "eJP,i,F")))
-   (clobber (match_operand:CC 3 "br_flag_operand" "=&b,&b,&b"))]
-  ""
-  "#"
-  [(set_attr "length" "12,16,24")
-   (set_attr "type" "multi")])
-
-(define_insn "*gedi_zero"
-  [(set (match_operand:CC 0 "flag_operand" "=f")
-	(ge:CC (match_operand:DI 1 "gpr_operand" "e")
-	       (const_int 0)))]
-  ""
-  "cmpge %0,%U1,0"
-  [(set_attr "length" "4")
-   (set_attr "type" "scmp")])
-
-(define_insn "*gedi_internal"
-  [(set (match_operand:CC 0 "flag_operand" "=&f,&f,&f")
-	(ge:CC (match_operand:DI 1 "gpr_operand" "e,e,e")
-	       (match_operand:DI 2 "gpr_or_dbl_const_operand" "eJP,i,F")))
-   (clobber (match_operand:CC 3 "br_flag_operand" "=&b,&b,&b"))]
-  ""
-  "#"
-  [(set_attr "length" "12,16,24")
-   (set_attr "type" "multi")])
-
-(define_insn "*ltudi_internal"
-  [(set (match_operand:CC 0 "flag_operand" "=&f,&f,&f")
-	(ltu:CC (match_operand:DI 1 "gpr_operand" "e,e,e")
-		(match_operand:DI 2 "gpr_or_dbl_const_operand" "eJP,i,F")))
-   (clobber (match_operand:CC 3 "br_flag_operand" "=&b,&b,&b"))]
-  ""
-  "#"
-  [(set_attr "length" "12,16,24")
-   (set_attr "type" "multi")])
-
-(define_insn "*leudi_internal"
-  [(set (match_operand:CC 0 "flag_operand" "=&f,&f,&f")
-	(leu:CC (match_operand:DI 1 "gpr_operand" "e,e,e")
-		(match_operand:DI 2 "gpr_or_dbl_const_operand" "eJP,i,F")))
-   (clobber (match_operand:CC 3 "br_flag_operand" "=&b,&b,&b"))]
-  ""
-  "#"
-  [(set_attr "length" "12,16,24")
-   (set_attr "type" "multi")])
-
-(define_insn "*gtudi_internal"
-  [(set (match_operand:CC 0 "flag_operand" "=&f,&f,&f")
-	(gtu:CC (match_operand:DI 1 "gpr_operand" "e,e,e")
-		(match_operand:DI 2 "gpr_or_dbl_const_operand" "eJP,i,F")))
-   (clobber (match_operand:CC 3 "br_flag_operand" "=&b,&b,&b"))]
-  ""
-  "#"
-  [(set_attr "length" "12,16,24")
-   (set_attr "type" "multi")])
-
-(define_insn "*geudi_internal"
-  [(set (match_operand:CC 0 "flag_operand" "=&f,&f,&f")
-	(geu:CC (match_operand:DI 1 "gpr_operand" "e,e,e")
-		(match_operand:DI 2 "gpr_or_dbl_const_operand" "eJP,i,F")))
-   (clobber (match_operand:CC 3 "br_flag_operand" "=&b,&b,&b"))]
-  ""
-  "#"
-  [(set_attr "length" "12,16,24")
-   (set_attr "type" "multi")])
-
-(define_split
-  [(set (match_operand:CC 0 "flag_operand" "")
-	(match_operator:CC 1 "relational_di_operator"
-			   [(match_operand:DI 2 "gpr_operand" "")
-			    (match_operand:DI 3 "gpr_or_dbl_const_operand" "")]))
-   (clobber (match_operand:CC 4 "br_flag_operand" ""))]
-  "reload_completed"
-  [(match_dup 5)
-   (match_dup 6)
-   (match_dup 7)]
-  "
-{
-  enum rtx_code cond = GET_CODE (operands[1]);
-  enum rtx_code ucond = unsigned_condition (cond);
-  rtx tmpflag = operands[4];
-  rtx outflag = operands[0];
-  rtx high[2];
-  rtx low[2];
-
-  d30v_split_double (operands[2], &high[0], &low[0]);
-  d30v_split_double (operands[3], &high[1], &low[1]);
-
-  operands[5] = gen_rtx (SET, VOIDmode,
-			 tmpflag,
-			 gen_rtx (EQ, CCmode, high[0], high[1]));
-
-  operands[6] = gen_rtx (SET, VOIDmode,
-			 outflag,
-			 gen_rtx (IF_THEN_ELSE, CCmode,
-				  tmpflag,
-				  outflag,
-				  gen_rtx (cond, CCmode, high[0], high[1])));
-
-  operands[7] = gen_rtx (SET, VOIDmode,
-			 outflag,
-			 gen_rtx (IF_THEN_ELSE, CCmode,
-				  tmpflag,
-				  gen_rtx (ucond, CCmode, low[0], low[1]),
-				  outflag));
-}")
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Branches
-;; ::
-;; ::::::::::::::::::::
-
-;; Define_expands called by the machine independent part of the compiler
-;; to allocate a new comparison register
-
-(define_expand "beq"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (EQ, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "bne"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (NE, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "bgt"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (GT, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "bge"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (GE, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "blt"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (LT, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "ble"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (LE, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "bgtu"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (GTU, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "bgeu"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (GEU, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "bltu"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (LTU, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "bleu"
-  [(match_dup 2)
-   (set (pc)
-	(if_then_else (ne:CC (match_dup 1)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (LEU, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-;; Actual branches.  We must allow for the (label_ref) and the (pc) to be
-;; swapped.  If they are swapped, it reverses the sense of the branch.
-;; Also handle changing the ne to eq.
-;; In order for the length calculations to be correct, the label must be
-;; operand 0.
-
-;; We used to handle branches against 0 to be folded directly into
-;; bratnz/bratzr instruction, but this dimisses the possibility of doing
-;; conditional execution.  Instead handle these via peepholes.
-
-;; Branches based off of the flag bits
-(define_insn "*bra_true"
-  [(set (pc)
-	(if_then_else (match_operator:CC 1 "condexec_branch_operator"
-					 [(match_operand:CC 2 "br_flag_or_constant_operand" "b,I,N")
-					  (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == REG || GET_CODE (operands[2]) == SUBREG)
-    return \"bra%F1 %l0\";
-
-  if (GET_CODE (operands[1]) != CONST_INT)
-    fatal_insn (\"bad jump\", insn);
-
-  if ((GET_CODE (operands[1]) == EQ && INTVAL (operands[2]) == 0)
-      || (GET_CODE (operands[1]) == NE && INTVAL (operands[2]) != 0))
-    return \"bra %l0\";
-
-  return \"; jump to %l0 optimized away\";
-}"
-  [(set_attr "type" "br")])
-
-(define_insn "*bra_false"
-  [(set (pc)
-	(if_then_else (match_operator:CC 1 "condexec_branch_operator"
-					 [(match_operand:CC 2 "br_flag_or_constant_operand" "b,I,N")
-					  (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == REG || GET_CODE (operands[2]) == SUBREG)
-    return \"bra%T1 %l0\";
-
-  if (GET_CODE (operands[1]) != CONST_INT)
-    fatal_insn (\"bad jump\", insn);
-
-  if ((GET_CODE (operands[1]) == EQ && INTVAL (operands[2]) != 0)
-      || (GET_CODE (operands[1]) == NE && INTVAL (operands[2]) == 0))
-    return \"bra %l0\";
-
-  return \"; jump to %l0 optimized away\";
-}"
-  [(set_attr "type" "br")])
-
-;; Peepholes to turn set flag, cond. jumps into branch if register ==/!= 0.
-
-(define_peephole
-  [(set (match_operand:CC 1 "br_flag_operand" "=b")
-	(match_operator:CC 2 "branch_zero_operator"
-			   [(match_operand:SI 3 "gpr_operand" "d")
-			    (const_int 0)]))
-   (set (pc)
-	(if_then_else (match_operator:CC 4 "condexec_test_operator"
-					 [(match_dup 1)
-					  (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  "(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) != 0)"
-  "*
-{
-  int true_false = 1;
-
-  if (GET_CODE (operands[2]) == EQ)
-    true_false = !true_false;
-
-  if (GET_CODE (operands[4]) == EQ)
-    true_false = !true_false;
-
-  return (true_false) ? \"bratnz %3,%l0\" : \"bratzr %3,%l0\";
-}"
-  [(set_attr "type" "br2")])
-
-(define_peephole
-  [(set (match_operand:CC 1 "br_flag_operand" "=b")
-	(match_operator:CC 2 "branch_zero_operator"
-			   [(match_operand:SI 3 "gpr_operand" "d")
-			    (const_int 0)]))
-   (set (pc)
-	(if_then_else (match_operator:CC 4 "condexec_test_operator"
-					 [(match_dup 1)
-					  (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  "(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) != 0)"
-  "*
-{
-  int true_false = 0;
-
-  if (GET_CODE (operands[2]) == EQ)
-    true_false = !true_false;
-
-  if (GET_CODE (operands[4]) == EQ)
-    true_false = !true_false;
-
-  return (true_false) ? \"bratnz %3,%l0\" : \"bratzr %3,%l0\";
-}"
-  [(set_attr "type" "br2")])
-
-;; Convert if (a & mask) into btst.  */
-(define_peephole
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-	(and:SI (match_operand:SI 1 "gpr_operand" "%d")
-		(match_operand:SI 2 "bitset_operand" "K")))
-   (set (match_operand:CC 3 "flag_operand" "=f")
-	(ne:CC (match_dup 0)
-	       (const_int 0)))]
-  "(find_regno_note (prev_nonnote_insn (insn), REG_DEAD, REGNO (operands[0])) != 0)"
-  "btst %3,%1,%B2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Set flag operations
-;; ::
-;; ::::::::::::::::::::
-
-;; Define_expands called by the machine independent part of the compiler
-;; to allocate a new comparison register
-
-;; ??? These patterns should all probably use (ne:SI ... (const_int 0)) instead
-;; of (eq:SI ... (const_int 1)), because the former is the canonical form.
-;; The non-canonical form was used here because I was just trying to get the
-;; port working again after it broke, and the non-canonical form was the
-;; safer faster way to fix this.
-
-
-(define_expand "seq"
-  [(match_dup 2)
-   (set (match_operand:SI 0 "gpr_operand" "")
-	(eq:SI (match_dup 1) (const_int 1)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (EQ, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "sne"
-  [(match_dup 2)
-   (set (match_operand:SI 0 "gpr_operand" "")
-	(eq:SI (match_dup 1) (const_int 1)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (NE, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "sgt"
-  [(match_dup 2)
-   (set (match_operand:SI 0 "gpr_operand" "")
-	(eq:SI (match_dup 1) (const_int 1)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (GT, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "sge"
-  [(match_dup 2)
-   (set (match_operand:SI 0 "gpr_operand" "")
-	(eq:SI (match_dup 1) (const_int 1)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (GE, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "slt"
-  [(match_dup 2)
-   (set (match_operand:SI 0 "gpr_operand" "")
-	(eq:SI (match_dup 1) (const_int 1)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (LT, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "sle"
-  [(match_dup 2)
-   (set (match_operand:SI 0 "gpr_operand" "")
-	(eq:SI (match_dup 1) (const_int 1)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (LE, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "sgtu"
-  [(match_dup 2)
-   (set (match_operand:SI 0 "gpr_operand" "")
-	(eq:SI (match_dup 1) (const_int 1)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (GTU, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "sgeu"
-  [(match_dup 2)
-   (set (match_operand:SI 0 "gpr_operand" "")
-	(eq:SI (match_dup 1) (const_int 1)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (GEU, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "sltu"
-  [(match_dup 2)
-   (set (match_operand:SI 0 "gpr_operand" "")
-	(eq:SI (match_dup 1) (const_int 1)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (LTU, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-(define_expand "sleu"
-  [(match_dup 2)
-   (set (match_operand:SI 0 "gpr_operand" "")
-	(eq:SI (match_dup 1) (const_int 1)))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (CCmode);
-  operands[2] = d30v_emit_comparison (LEU, operands[1],
-				      d30v_compare_op0,
-				      d30v_compare_op1);
-}")
-
-;; Set flag operations We purposely prefer using flag registers other than f0
-;; and f1 to allow the setcc operations not add to the register pressure on
-;; f0/f1.
-(define_insn "*setcc_internal"
-  [(set (match_operand:SI 0 "gpr_operand" "=d,d,!*d")
-	(eq:SI (match_operand:CC 1 "flag_operand" "z,!b,!*d")
-	       (const_int 1)))]
-  ""
-  "@
-    mvfsys %0,%1
-    mvfsys %0,%1
-    or %0,%.,%1"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Operations on flags
-;; ::
-;; ::::::::::::::::::::
-
-(define_insn "andcc3"
-  [(set (match_operand:CC 0 "flag_operand" "=f")
-	(and:CC (match_operand:CC 1 "flag_operand" "f")
-		(match_operand:CC 2 "flag_operand" "f")))]
-  ""
-  "andfg %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-(define_insn "iorcc3"
-  [(set (match_operand:CC 0 "flag_operand" "=f")
-	(ior:CC (match_operand:CC 1 "flag_operand" "f")
-		(match_operand:CC 2 "flag_operand" "f")))]
-  ""
-  "orfg %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-(define_insn "xorcc3"
-  [(set (match_operand:CC 0 "flag_operand" "=f")
-	(xor:CC (match_operand:CC 1 "flag_operand" "f")
-		(match_operand:CC 2 "flag_operand" "f")))]
-  ""
-  "xorfg %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-;; This is the canonical form produced by combine.
-
-(define_insn "incscc"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-        (plus:SI (eq:SI (match_operand:CC 1 "br_flag_operand" "b")
-			(const_int 1))
-		 (match_operand:SI 2 "gpr_operand" "d")))]
-  ""
-  "add%T1 %0,%2,1"
-[(set_attr "length" "4")
- (set_attr "type" "either")])
-
-(define_insn "decscc"
-  [(set (match_operand:SI 0 "gpr_operand" "=d")
-        (minus:SI (match_operand:SI 1 "gpr_operand" "d")
-		  (eq:SI (match_operand:CC 2 "br_flag_operand" "b")
-			 (const_int 1))))]
-  ""
-  "sub%T2 %0,%1,1"
-[(set_attr "length" "4")
- (set_attr "type" "either")])
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Call and branch instructions
-;; ::
-;; ::::::::::::::::::::
-
-;; Subroutine call instruction returning no value.  Operand 0 is the function
-;; to call; operand 1 is the number of bytes of arguments pushed (in mode
-;; `SImode', except it is normally a `const_int'); operand 2 is the number of
-;; registers used as operands.
-
-;; On most machines, operand 2 is not actually stored into the RTL pattern.  It
-;; is supplied for the sake of some RISC machines which need to put this
-;; information into the assembler code; they can put it in the RTL instead of
-;; operand 1.
-
-(define_expand "call"
-  [(parallel [(call (match_operand 0 "call_operand" "")
-		    (match_operand 1 "" ""))
-	      (use (match_operand 2 "" ""))
-	      (clobber (match_dup 3))])]
-  ""
-  "
-{
-  if (GET_CODE (XEXP (operands[0], 0)) == SUBREG)
-    XEXP (operands[0], 0) = copy_addr_to_reg (XEXP (operands[0], 0));
-
-  if (!operands[2])
-    operands[2] = const0_rtx;
-
-  operands[3] = gen_rtx (REG, Pmode, GPR_LINK);
-}")
-
-(define_insn "*call_internal"
-  [(call (match_operand 0 "call_operand" "R,S")
-	 (match_operand 1 "" ""))
-   (use (match_operand 2 "" ""))
-   (clobber (match_operand 3 "" "=d,d"))]
-  ""
-  "@
-    jsr %0
-    bsr %0"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "mu,long")])
-
-;; Subroutine call instruction returning a value.  Operand 0 is the hard
-;; register in which the value is returned.  There are three more operands, the
-;; same as the three operands of the `call' instruction (but with numbers
-;; increased by one).
-
-;; Subroutines that return `BLKmode' objects use the `call' insn.
-
-(define_expand "call_value"
-  [(parallel [(set (match_operand 0 "gpr_operand" "")
-		   (call (match_operand 1 "call_operand" "")
-			 (match_operand 2 "" "")))
-	     (use (match_operand 3 "" ""))
-	     (clobber (match_dup 4))])]
-  ""
-  "
-{
-  if (GET_CODE (XEXP (operands[1], 0)) == SUBREG)
-    XEXP (operands[1], 0) = copy_addr_to_reg (XEXP (operands[1], 0));
-
-  if (!operands[3])
-    operands[3] = const0_rtx;
-
-  operands[4] = gen_rtx (REG, Pmode, GPR_LINK);
-}")
-
-(define_insn "*call_value_internal"
-  [(set (match_operand 0 "gpr_operand" "=d,d")
-	(call (match_operand 1 "call_operand" "R,S")
-	      (match_operand 2 "" "")))
-	(use (match_operand 3 "" ""))
-	(clobber (match_operand 4 "" "=d,d"))]
-  ""
-  "@
-    jsr %1
-    bsr %1"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "mu,long")])
-
-;; Subroutine return
-(define_insn "return"
-  [(return)]
-  "direct_return ()"
-  "jmp link"
-  [(set_attr "length" "4")])
-
-;; Normal unconditional jump
-(define_insn "jump"
-  [(set (pc) (label_ref (match_operand 0 "" "")))]
-  ""
-  "bra %l0"
-  [(set_attr "type" "br")])
-
-;; Indirect jump through a register
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "gpr_operand" "d"))]
-  ""
-  "jmp %0"
-  [(set_attr "length" "4")
-   (set_attr "type" "mu")])
-
-;; Instruction to jump to a variable address.  This is a low-level capability
-;; which can be used to implement a dispatch table when there is no `casesi'
-;; pattern.
-
-;; This pattern requires two operands: the address or offset, and a label which
-;; should immediately precede the jump table.  If the macro
-;; `CASE_VECTOR_PC_RELATIVE' is defined then the first operand is an offset
-;; which counts from the address of the table; otherwise, it is an absolute
-;; address to jump to.  In either case, the first operand has mode `Pmode'.
-
-;; The `tablejump' insn is always the last insn before the jump table it uses.
-;; Its assembler code normally has no need to use the second operand, but you
-;; should incorporate it in the RTL pattern so that the jump optimizer will not
-;; delete the table as unreachable code.
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "gpr_operand" "d"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmp %0"
-  [(set_attr "length" "4")
-   (set_attr "type" "mu")])
-
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Prologue and Epilogue instructions
-;; ::
-;; ::::::::::::::::::::
-
-;; Called after register allocation to add any instructions needed for the
-;; prologue.  Using a prologue insn is favored compared to putting all of the
-;; instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
-;; to intermix instructions with the saves of the caller saved registers.  In
-;; some cases, it might be necessary to emit a barrier instruction as the last
-;; insn to prevent such scheduling.
-
-(define_expand "prologue"
-  [(const_int 1)]
-  ""
-  "
-{
-  d30v_expand_prologue ();
-  DONE;
-}")
-
-;; Called after register allocation to add any instructions needed for the
-;; epilogue.  Using a epilogue insn is favored compared to putting all of the
-;; instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
-;; to intermix instructions with the saves of the caller saved registers.  In
-;; some cases, it might be necessary to emit a barrier instruction as the last
-;; insn to prevent such scheduling.
-
-(define_expand "epilogue"
-  [(const_int 2)]
-  ""
-  "
-{
-  d30v_expand_epilogue ();
-  DONE;
-}")
-
-(define_expand "eh_epilogue"
-  [(use (match_operand:DI 0 "register_operand" "r"))
-   (use (match_operand:DI 1 "register_operand" "r"))
-   (use (match_operand:DI 2 "register_operand" "r"))]
-  ""
-  "
-{
-  d30v_eh_epilogue_sp_ofs = operands[1];
-  if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != GPR_LINK)
-    {
-      rtx ra = gen_rtx_REG (Pmode, GPR_LINK);
-      emit_move_insn (ra, operands[2]);
-      operands[2] = ra;
-    }
-}")
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Conditional move instructions
-;; ::
-;; ::::::::::::::::::::
-
-;; Conditionally move operand 2 or operand 3 into operand 0 according to the
-;; comparison in operand 1.  If the comparison is true, operand 2 is moved into
-;; operand 0, otherwise operand 3 is moved.
-
-;; The mode of the operands being compared need not be the same as the operands
-;; being moved.  Some machines, sparc64 for example, have instructions that
-;; conditionally move an integer value based on the floating point condition
-;; codes and vice versa.
-
-;; If the machine does not have conditional move instructions, do not
-;; define these patterns.
-
-(define_expand "movqicc"
-  [(set (match_operand:QI 0 "cond_move_operand" "")
-	(if_then_else:QI (match_operand 1 "" "")
-			 (match_operand:QI 2 "cond_move_operand" "")
-			 (match_operand:QI 3 "cond_move_operand" "")))]
-  "TARGET_COND_MOVE"
-  "
-{
-  if (!d30v_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_insn "*movqicc_internal"
-  [(set (match_operand:QI 0 "cond_move_operand" "=d,d,d,d,&d,Q,m")
-	(if_then_else:QI (match_operator:CC 1 "condexec_test_operator"
-					    [(match_operand:CC 2 "br_flag_operand" "b,b,b,b,b,b,b")
-					     (const_int 0)])
-			 (match_operand:QI 3 "cond_move_operand" "0,dIQ,0,im,dim,dO,dO")
-			 (match_operand:QI 4 "cond_move_operand" "dIQ,0,im,0,dim,dO,dO")))]
-  "TARGET_COND_MOVE
-   && (GET_CODE (operands[0]) != MEM
-       || (reg_or_0_operand (operands[2], QImode)
-	   && reg_or_0_operand (operands[3], QImode)))"
-  "* return d30v_cond_move (operands, insn, \"ldbu\", \"stb\");"
-  [(set_attr "type" "either,either,long,long,multi,multi,multi")
-   (set_attr "length" "4,4,8,8,16,8,16")])
-
-(define_expand "movhicc"
-  [(set (match_operand:HI 0 "cond_move_operand" "")
-	(if_then_else:HI (match_operand 1 "" "")
-			 (match_operand:HI 2 "cond_move_operand" "")
-			 (match_operand:HI 3 "cond_move_operand" "")))]
-  "TARGET_COND_MOVE"
-  "
-{
-  if (!d30v_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_insn "*movhicc_internal"
-  [(set (match_operand:HI 0 "cond_move_operand" "=d,d,d,d,&d,Q,m")
-	(if_then_else:HI (match_operator:CC 1 "condexec_test_operator"
-					    [(match_operand:CC 2 "br_flag_operand" "b,b,b,b,b,b,b")
-					     (const_int 0)])
-			 (match_operand:HI 3 "cond_move_operand" "0,dIQ,0,im,dim,dO,dO")
-			 (match_operand:HI 4 "cond_move_operand" "dIQ,0,im,0,dim,dO,dO")))]
-  "TARGET_COND_MOVE
-   && (GET_CODE (operands[0]) != MEM
-       || (reg_or_0_operand (operands[2], HImode)
-	   && reg_or_0_operand (operands[3], HImode)))"
-  "* return d30v_cond_move (operands, insn, \"ldhu\", \"sth\");"
-  [(set_attr "type" "either,either,long,long,multi,multi,multi")
-   (set_attr "length" "4,4,8,8,16,8,16")])
-
-(define_expand "movsicc"
-  [(set (match_operand:SI 0 "cond_move_operand" "")
-	(if_then_else:SI (match_operand 1 "" "")
-			 (match_operand:SI 2 "cond_move_operand" "")
-			 (match_operand:SI 3 "cond_move_operand" "")))]
-  "TARGET_COND_MOVE"
-  "
-{
-  if (!d30v_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
-    FAIL;
-
-  DONE;
-}")
-
-(define_insn "*movsicc_internal"
-  [(set (match_operand:SI 0 "cond_move_operand" "=d,d,d,d,&d,Q,m")
-	(if_then_else:SI (match_operator:CC 1 "condexec_test_operator"
-					    [(match_operand:CC 2 "br_flag_operand" "b,b,b,b,b,b,b")
-					     (const_int 0)])
-			 (match_operand:SI 3 "cond_move_operand" "0,dIQ,0,im,dim,dO,dO")
-			 (match_operand:SI 4 "cond_move_operand" "dIQ,0,im,0,dim,dO,dO")))]
-  "TARGET_COND_MOVE
-   && (GET_CODE (operands[0]) != MEM
-       || (reg_or_0_operand (operands[2], SImode)
-	   && reg_or_0_operand (operands[3], SImode)))"
-  "* return d30v_cond_move (operands, insn, \"ldw\", \"stw\");"
-  [(set_attr "type" "either,either,long,long,multi,multi,multi")
-   (set_attr "length" "4,4,8,8,16,8,16")])
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Conditional execution
-;; ::
-;; ::::::::::::::::::::
-
-(define_insn "*cond_exec_qi_store_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (set (match_operand:QI 0 "memory_operand" "=Q,Q,m,m")
-		      (match_operand:QI 1 "reg_or_0_operand" "d,O,d,O"))
-		 (const_int 0))]
-  ""
-  "@
-    stb%T2 %1,%M0
-    stb%T2 %.,%M0
-    stb%T2 %1,%M0
-    stb%T2 %.,%M0"
-  [(set_attr "length" "4,4,8,8")
-   (set_attr "type" "mu,mu,long,long")])
-
-(define_insn "*cond_exec_qi_store_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:QI 0 "memory_operand" "=Q,Q,m,m")
-		      (match_operand:QI 1 "reg_or_0_operand" "d,O,d,O")))]
-  ""
-  "@
-    stb%F2 %1,%M0
-    stb%F2 %.,%M0
-    stb%F2 %1,%M0
-    stb%F2 %.,%M0"
-  [(set_attr "length" "4,4,8,8")
-   (set_attr "type" "mu,mu,long,long")])
-
-(define_insn "*cond_exec_qi_load_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (set (match_operand:QI 0 "gpr_operand" "=d,d,d,d")
-		      (match_operand:QI 1 "cond_exec_operand" "dI,i,Q,m"))
-		 (const_int 0))]
-  ""
-  "@
-    or%T2 %0,%.,%1
-    or%T2 %0,%.,%1
-    ldb%T2 %0,%M1
-    ldb%T2 %0,%M1"
-  [(set_attr "length" "4,8,4,8")
-   (set_attr "type" "either,long,sload,lload")])
-
-(define_insn "*cond_exec_qi_load_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:QI 0 "gpr_operand" "=d,d,d,d")
-		      (match_operand:QI 1 "cond_exec_operand" "dI,i,Q,m")))]
-  ""
-  "@
-    or%F2 %0,%.,%1
-    or%F2 %0,%.,%1
-    ldb%F2 %0,%M1
-    ldb%F2 %0,%M1"
-  [(set_attr "length" "4,8,4,8")
-   (set_attr "type" "either,long,sload,lload")])
-
-(define_insn "*cond_exec_hi_store_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (set (match_operand:HI 0 "memory_operand" "=Q,Q,m,m")
-		      (match_operand:HI 1 "reg_or_0_operand" "d,O,d,O"))
-		 (const_int 0))]
-  ""
-  "@
-    sth%T2 %1,%M0
-    sth%T2 %.,%M0
-    sth%T2 %1,%M0
-    sth%T2 %.,%M0"
-  [(set_attr "length" "4,4,8,8")
-   (set_attr "type" "mu,mu,long,long")])
-
-(define_insn "*cond_exec_hi_store_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:HI 0 "memory_operand" "=Q,Q,m,m")
-		      (match_operand:HI 1 "reg_or_0_operand" "d,O,d,O")))]
-  ""
-  "@
-    sth%F2 %1,%M0
-    sth%F2 %.,%M0
-    sth%F2 %1,%M0
-    sth%F2 %.,%M0"
-  [(set_attr "length" "4,4,8,8")
-   (set_attr "type" "mu,mu,long,long")])
-
-(define_insn "*cond_exec_hi_load_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (set (match_operand:HI 0 "gpr_operand" "=d,d,d,d")
-		      (match_operand:HI 1 "cond_exec_operand" "dI,i,Q,m"))
-		 (const_int 0))]
-  ""
-  "@
-    or%T2 %0,%.,%1
-    or%T2 %0,%.,%1
-    ldh%T2 %0,%M1
-    ldh%T2 %0,%M1"
-  [(set_attr "length" "4,8,4,8")
-   (set_attr "type" "either,long,sload,lload")])
-
-(define_insn "*cond_exec_hi_load_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:HI 0 "gpr_operand" "=d,d,d,d")
-		      (match_operand:HI 1 "cond_exec_operand" "dI,i,Q,m")))]
-  ""
-  "@
-    or%F2 %0,%.,%1
-    or%F2 %0,%.,%1
-    ldh%F2 %0,%M1
-    ldh%F2 %0,%M1"
-  [(set_attr "length" "4,8,4,8")
-   (set_attr "type" "either,long,sload,lload")])
-
-(define_insn "*cond_exec_hi_extend_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b")
-				  (const_int 0)])
-		 (set (match_operand:HI 0 "gpr_operand" "=d,d")
-		      (match_operator:HI 4 "condexec_extend_operator"
-					 [(match_operand 1 "d30v_memory_operand" "Q,m")]))
-		 (const_int 0))]
-  ""
-  "ldb%E4%T2 %0,%M1"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "sload,lload")])
-
-(define_insn "*cond_exec_hi_extend_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:HI 0 "gpr_operand" "=d,d")
-		      (match_operator:HI 4 "condexec_extend_operator"
-					 [(match_operand 1 "d30v_memory_operand" "Q,m")])))]
-  ""
-  "ldb%E4%F2 %0,%M1"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "sload,lload")])
-
-(define_insn "*cond_exec_hi_extend2_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b")
-				  (const_int 0)])
-		 (set (match_operand:HI 0 "gpr_operand" "=d")
-		      (zero_extend:HI (match_operand:QI 1 "gpr_operand" "d")))
-		 (const_int 0))]
-  ""
-  "and%T2 %0,%1,0xff"
-  [(set_attr "length" "8")
-   (set_attr "type" "long")])
-
-(define_insn "*cond_exec_hi_extend2_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:HI 0 "gpr_operand" "=d")
-		      (zero_extend:HI (match_operand:QI 1 "gpr_operand" "d"))))]
-  ""
-  "and%F2 %0,%1,0xff"
-  [(set_attr "length" "8")
-   (set_attr "type" "long")])
-
-(define_insn "*cond_exec_si_store_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (set (match_operand:SI 0 "memory_operand" "=Q,Q,m,m")
-		      (match_operand:SI 1 "reg_or_0_operand" "d,O,d,O"))
-		 (const_int 0))]
-  ""
-  "@
-    stw%T2 %1,%M0
-    stw%T2 %.,%M0
-    stw%T2 %1,%M0
-    stw%T2 %.,%M0"
-  [(set_attr "length" "4,4,8,8")
-   (set_attr "type" "mu,mu,long,long")])
-
-(define_insn "*cond_exec_si_store_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SI 0 "memory_operand" "=Q,Q,m,m")
-		      (match_operand:SI 1 "reg_or_0_operand" "d,O,d,O")))]
-  ""
-  "@
-    stw%F2 %1,%M0
-    stw%F2 %.,%M0
-    stw%F2 %1,%M0
-    stw%F2 %.,%M0"
-  [(set_attr "length" "4,4,8,8")
-   (set_attr "type" "mu,mu,long,long")])
-
-(define_insn "*cond_exec_si_load_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (set (match_operand:SI 0 "gpr_operand" "=d,d,d,d")
-		      (match_operand:SI 1 "cond_exec_operand" "dI,i,Q,m"))
-		 (const_int 0))]
-  ""
-  "@
-    or%T2 %0,%.,%1
-    or%T2 %0,%.,%1
-    ldw%T2 %0,%M1
-    ldw%T2 %0,%M1"
-  [(set_attr "length" "4,8,4,8")
-   (set_attr "type" "either,long,sload,lload")])
-
-(define_insn "*cond_exec_si_load_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SI 0 "gpr_operand" "=d,d,d,d")
-		      (match_operand:SI 1 "cond_exec_operand" "dI,i,Q,m")))]
-  ""
-  "@
-    or%F2 %0,%.,%1
-    or%F2 %0,%.,%1
-    ldw%F2 %0,%M1
-    ldw%F2 %0,%M1"
-  [(set_attr "length" "4,8,4,8")
-   (set_attr "type" "either,long,sload,lload")])
-
-(define_insn "*cond_exec_si_unary_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b")
-				  (const_int 0)])
-		 (set (match_operand:SI 0 "gpr_operand" "=d")
-		      (match_operator:SI 4 "condexec_unary_operator"
-					 [(match_operand:SI 1 "gpr_operand" "d")]))
-		 (const_int 0))]
-  ""
-  "*
-{
-  switch (GET_CODE (operands[4]))
-    {
-    default:
-      fatal_insn (\"cond_exec_si_unary_true:\", insn);
-
-    case ABS: return \"abs%T2 %0,%1\";
-    case NOT: return \"not%T2 %0,%1\";
-    case NEG: return \"sub%T2 %0,%.,%1\";
-    }
-}"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-(define_insn "*cond_exec_si_unary_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SI 0 "gpr_operand" "=d")
-		      (match_operator:SI 4 "condexec_unary_operator"
-					 [(match_operand:SI 1 "gpr_operand" "d")])))]
-  ""
-  "*
-{
-  switch (GET_CODE (operands[4]))
-    {
-    default:
-      fatal_insn (\"cond_exec_si_unary_false:\", insn);
-
-    case ABS: return \"abs%F2 %0,%1\";
-    case NOT: return \"not%F2 %0,%1\";
-    case NEG: return \"sub%F2 %0,%.,%1\";
-    }
-}"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-(define_insn "*cond_exec_si_extend_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b")
-				  (const_int 0)])
-		 (set (match_operand:SI 0 "gpr_operand" "=d,d")
-		      (match_operator:SI 4 "condexec_extend_operator"
-					 [(match_operand 1 "d30v_memory_operand" "Q,m")]))
-		 (const_int 0))]
-  ""
-  "*
-{
-  return ((GET_MODE (operands[1]) == QImode)
-	  ? \"ldb%E4%T2 %0,%M1\"
-	  : \"ldh%E4%T2 %0,%M1\");
-}"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "sload,lload")])
-
-(define_insn "*cond_exec_si_extend_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SI 0 "gpr_operand" "=d,d")
-		      (match_operator:SI 4 "condexec_extend_operator"
-					 [(match_operand 1 "d30v_memory_operand" "Q,m")])))]
-  ""
-  "*
-{
-  return ((GET_MODE (operands[1]) == QImode)
-	  ? \"ldb%E4%F2 %0,%M1\"
-	  : \"ldh%E4%F2 %0,%M1\");
-}"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "sload,lload")])
-
-(define_insn "*cond_exec_si_extend2_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b")
-				  (const_int 0)])
-		 (set (match_operand:SI 0 "gpr_operand" "=d")
-		      (zero_extend:SI (match_operand:QI 1 "gpr_operand" "d")))
-		 (const_int 0))]
-  ""
-  "and%T2 %0,%1,0xff"
-  [(set_attr "length" "8")
-   (set_attr "type" "long")])
-
-(define_insn "*cond_exec_si_extend2_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SI 0 "gpr_operand" "=d")
-		      (zero_extend:SI (match_operand:QI 1 "gpr_operand" "d"))))]
-  ""
-  "and%F2 %0,%1,0xff"
-  [(set_attr "length" "8")
-   (set_attr "type" "long")])
-
-(define_insn "*cond_exec_si_extend3_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b")
-				  (const_int 0)])
-		 (set (match_operand:SI 0 "gpr_operand" "=d")
-		      (zero_extend:SI (match_operand:HI 1 "gpr_operand" "d")))
-		 (const_int 0))]
-  ""
-  "and%T2 %0,%1,0xffff"
-  [(set_attr "length" "8")
-   (set_attr "type" "long")])
-
-(define_insn "*cond_exec_si_extend3_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SI 0 "gpr_operand" "=d")
-		      (zero_extend:SI (match_operand:HI 1 "gpr_operand" "d"))))]
-  ""
-  "and%F2 %0,%1,0xffff"
-  [(set_attr "length" "8")
-   (set_attr "type" "long")])
-
-(define_insn "*cond_exec_si_addsub_true"
-  [(if_then_else (match_operator 6 "condexec_test_operator"
-				 [(match_operand:CC 7 "br_flag_operand" "b,b")
-				  (const_int 0)])
-		 (parallel [(set (match_operand:SI 0 "gpr_operand" "=d,d")
-				 (match_operator:SI 8 "condexec_addsub_operator"
-						    [(match_operand:SI 1 "gpr_operand" "d,d")
-						     (match_operand:SI 2 "gpr_or_constant_operand" "dI,i")]))
-			    (clobber (match_operand:CC 3 "flag_operand" ""))
-			    (clobber (match_operand:CC 4 "flag_operand" ""))
-			    (clobber (match_operand:CC 5 "flag_operand" ""))])
-		 (const_int 0))]
-  ""
-  "*
-{
-  switch (GET_CODE (operands[8]))
-    {
-    default:
-      fatal_insn (\"cond_exec_si_addsub_true:\", insn);
-
-    case PLUS:  return \"add%T6 %0,%1,%2\";
-    case MINUS: return \"sub%T6 %0,%1,%2\";
-    }
-}"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "either,long")])
-
-(define_insn "*cond_exec_si_addsub_false"
-  [(if_then_else (match_operator 6 "condexec_test_operator"
-				 [(match_operand:CC 7 "br_flag_operand" "b,b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (parallel [(set (match_operand:SI 0 "gpr_operand" "=d,d")
-				 (match_operator:SI 8 "condexec_addsub_operator"
-						    [(match_operand:SI 1 "gpr_operand" "d,d")
-						     (match_operand:SI 2 "gpr_or_constant_operand" "dI,i")]))
-			    (clobber (match_operand:CC 3 "flag_operand" ""))
-			    (clobber (match_operand:CC 4 "flag_operand" ""))
-			    (clobber (match_operand:CC 5 "flag_operand" ""))]))]
-  ""
-  "*
-{
-  switch (GET_CODE (operands[8]))
-    {
-    default:
-      fatal_insn (\"cond_exec_si_addsub_false:\", insn);
-
-    case PLUS:  return \"add%F6 %0,%1,%2\";
-    case MINUS: return \"sub%F6 %0,%1,%2\";
-    }
-}"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "either,long")])
-
-(define_insn "*cond_exec_si_binary_true"
-  [(if_then_else (match_operator 3 "condexec_test_operator"
-				 [(match_operand:CC 4 "br_flag_operand" "b,b")
-				  (const_int 0)])
-		 (set (match_operand:SI 0 "gpr_operand" "=d,d")
-		      (match_operator:SI 5 "condexec_binary_operator"
-					 [(match_operand:SI 1 "gpr_operand" "d,d")
-					  (match_operand:SI 2 "gpr_or_constant_operand" "dI,i")]))
-		 (const_int 0))]
-  ""
-  "*
-{
-  switch (GET_CODE (operands[5]))
-    {
-    default:
-      fatal_insn (\"cond_exec_si_binary_true:\", insn);
-
-    case AND:      return \"and%T3 %0,%1,%2\";
-    case IOR:      return \"or%T3 %0,%1,%2\";
-    case XOR:      return \"xor%T3 %0,%1,%2\";
-    case ASHIFT:   return \"sra%T3 %0,%1,%n2\";
-    case ASHIFTRT: return \"sra%T3 %0,%1,%2\";
-    case LSHIFTRT: return \"srl%T3 %0,%1,%2\";
-    case ROTATE:   return \"rot%T3 %0,%1,%n2\";
-    case ROTATERT: return \"rot%T3 %0,%1,%2\";
-    }
-}"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "either,long")])
-
-(define_insn "*cond_exec_si_binary_false"
-  [(if_then_else (match_operator 3 "condexec_test_operator"
-				 [(match_operand:CC 4 "br_flag_operand" "b,b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SI 0 "gpr_operand" "=d,d")
-		      (match_operator:SI 5 "condexec_binary_operator"
-					 [(match_operand:SI 1 "gpr_operand" "d,d")
-					  (match_operand:SI 2 "gpr_or_constant_operand" "dI,i")])))]
-  ""
-  "*
-{
-  switch (GET_CODE (operands[5]))
-    {
-    default:
-      fatal_insn (\"cond_exec_si_binary_false:\", insn);
-
-    case AND:      return \"and%F3 %0,%1,%2\";
-    case IOR:      return \"or%F3 %0,%1,%2\";
-    case XOR:      return \"xor%F3 %0,%1,%2\";
-    case ASHIFT:   return \"sra%F3 %0,%1,%n2\";
-    case ASHIFTRT: return \"sra%F3 %0,%1,%2\";
-    case LSHIFTRT: return \"srl%F3 %0,%1,%2\";
-    case ROTATE:   return \"rot%F3 %0,%1,%n2\";
-    case ROTATERT: return \"rot%F3 %0,%1,%2\";
-    }
-}"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "either,long")])
-
-(define_insn "*cond_exec_si_shiftl_true"
-  [(if_then_else (match_operator 3 "condexec_test_operator"
-				 [(match_operand:CC 4 "br_flag_operand" "b")
-				  (const_int 0)])
-		 (set (match_operand:SI 0 "gpr_operand" "=d")
-		      (match_operator:SI 5 "condexec_shiftl_operator"
-					 [(match_operand:SI 1 "gpr_operand" "d")
-					  (neg:SI (match_operand:SI 2 "gpr_operand" "d"))]))
-		 (const_int 0))]
-  ""
-  "*
-{
-  switch (GET_CODE (operands[5]))
-    {
-    default:
-      fatal_insn (\"cond_exec_si_shiftl_true:\", insn);
-
-    case ASHIFT:   return \"sra%T3 %0,%1,%2\";
-    case ROTATE:   return \"rot%T3 %0,%1,%2\";
-    }
-}"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-(define_insn "*cond_exec_si_shiftl_false"
-  [(if_then_else (match_operator 3 "condexec_test_operator"
-				 [(match_operand:CC 4 "br_flag_operand" "b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SI 0 "gpr_operand" "=d")
-		      (match_operator:SI 5 "condexec_shiftl_operator"
-					 [(match_operand:SI 1 "gpr_operand" "d")
-					  (neg:SI (match_operand:SI 2 "gpr_operand" "d"))])))]
-  ""
-  "*
-{
-  switch (GET_CODE (operands[5]))
-    {
-    default:
-      fatal_insn (\"cond_exec_si_shiftl_false:\", insn);
-
-    case ASHIFT:   return \"sra%F3 %0,%1,%2\";
-    case ROTATE:   return \"rot%F3 %0,%1,%2\";
-    }
-}"
-  [(set_attr "length" "4")
-   (set_attr "type" "either")])
-
-(define_insn "*cond_exec_si_mul_true"
-  [(if_then_else (match_operator 3 "condexec_test_operator"
-				 [(match_operand:CC 4 "br_flag_operand" "b")
-				  (const_int 0)])
-		 (set (match_operand:SI 0 "gpr_operand" "=d")
-		      (mult:SI (match_operand:SI 1 "gpr_operand" "%d")
-			       (match_operand:SI 2 "gpr_or_signed6_operand" "dI")))
-		 (const_int 0))]
-  ""
-  "mul%T3 %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "iu")])
-
-(define_insn "*cond_exec_si_mul_false"
-  [(if_then_else (match_operator 3 "condexec_test_operator"
-				 [(match_operand:CC 4 "br_flag_operand" "b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SI 0 "gpr_operand" "=d")
-		      (mult:SI (match_operand:SI 1 "gpr_operand" "%d")
-			       (match_operand:SI 2 "gpr_or_signed6_operand" "dI"))))]
-  ""
-  "mul%F3 %0,%1,%2"
-  [(set_attr "length" "4")
-   (set_attr "type" "iu")])
-
-(define_insn "*cond_exec_sf_store_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (set (match_operand:SF 0 "memory_operand" "=Q,Q,m,m")
-		      (match_operand:SF 1 "reg_or_0_operand" "d,G,d,G"))
-		 (const_int 0))]
-  ""
-  "@
-    stw%T2 %1,%M0
-    stw%T2 %.,%M0
-    stw%T2 %1,%M0
-    stw%T2 %.,%M0"
-  [(set_attr "length" "4,4,8,8")
-   (set_attr "type" "mu,mu,long,long")])
-
-(define_insn "*cond_exec_sf_store_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SF 0 "memory_operand" "=Q,Q,m,m")
-		      (match_operand:SF 1 "reg_or_0_operand" "d,G,d,G")))]
-  ""
-  "@
-    stw%F2 %1,%M0
-    stw%F2 %.,%M0
-    stw%F2 %1,%M0
-    stw%F2 %.,%M0"
-  [(set_attr "length" "4,4,8,8")
-   (set_attr "type" "mu,mu,long,long")])
-
-(define_insn "*cond_exec_sf_load_true"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (set (match_operand:SF 0 "gpr_operand" "=d,d,d,d")
-		      (match_operand:SF 1 "cond_exec_operand" "d,F,Q,m"))
-		 (const_int 0))]
-  ""
-  "@
-    or%T2 %0,%.,%1
-    or%T2 %0,%.,%f1
-    ldw%T2 %0,%M1
-    ldw%T2 %0,%M1"
-  [(set_attr "length" "4,8,4,8")
-   (set_attr "type" "either,long,sload,lload")])
-
-(define_insn "*cond_exec_sf_load_false"
-  [(if_then_else (match_operator 2 "condexec_test_operator"
-				 [(match_operand:CC 3 "br_flag_operand" "b,b,b,b")
-				  (const_int 0)])
-		 (const_int 0)
-		 (set (match_operand:SF 0 "gpr_operand" "=d,d,d,d")
-		      (match_operand:SF 1 "cond_exec_operand" "d,F,Q,m")))]
-  ""
-  "@
-    or%F2 %0,%.,%1
-    or%F2 %0,%.,%f1
-    ldw%F2 %0,%M1
-    ldw%F2 %0,%M1"
-  [(set_attr "length" "4,8,4,8")
-   (set_attr "type" "either,long,sload,lload")])
-
-(define_insn "*cond_exec_call_true"
-  [(if_then_else (match_operator 4 "condexec_test_operator"
-				 [(match_operand:CC 5 "br_flag_operand" "b,b")
-				  (const_int 0)])
-		 (parallel [(call (match_operand 0 "call_operand" "R,S")
-				  (match_operand 1 "" ""))
-			    (use (match_operand 2 "" ""))
-			    (clobber (match_operand 3 "" ""))])		;; return address, r63
-		 (const_int 0))]
-  ""
-  "jsr%T4 %0"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "mu,long")])
-
-(define_insn "*cond_exec_call_false"
-  [(if_then_else (match_operator 4 "condexec_test_operator"
-				 [(match_operand:CC 5 "br_flag_operand" "b,b")
-				  (const_int 0)])
-		 (const_int 0)		;; return address, r63
-		 (parallel [(call (match_operand 0 "call_operand" "R,S")
-				  (match_operand 1 "" ""))
-			    (use (match_operand 2 "" ""))
-			    (clobber (match_operand 3 "" ""))]))]
-  ""
-  "jsr%F4 %0"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "mu,long")])
-
-(define_insn "*cond_exec_call_value_true"
-  [(if_then_else (match_operator 5 "condexec_test_operator"
-				 [(match_operand:CC 6 "br_flag_operand" "b,b")
-				  (const_int 0)])
-		 (parallel [(set (match_operand 0 "gpr_operand" "=d,d")
-				 (call (match_operand 1 "call_operand" "R,S")
-				       (match_operand 2 "" "")))
-			    (use (match_operand 3 "" ""))
-			    (clobber (match_operand 4 "" ""))])		;; return address, r63
-		 (const_int 0))]
-  ""
-  "jsr%T5 %1"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "mu,long")])
-
-(define_insn "*cond_exec_call_value_false"
-  [(if_then_else (match_operator 5 "condexec_test_operator"
-				 [(match_operand:CC 6 "br_flag_operand" "b,b")
-				  (const_int 0)])
-		 (const_int 0)		;; return address, r63
-		 (parallel [(set (match_operand 0 "gpr_operand" "=d,d")
-				 (call (match_operand 1 "call_operand" "R,S")
-				       (match_operand 2 "" "")))
-			    (use (match_operand 3 "" ""))
-			    (clobber (match_operand 4 "" ""))]))]
-  ""
-  "jsr%F5 %1"
-  [(set_attr "length" "4,8")
-   (set_attr "type" "mu,long")])
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Miscellaneous instructions
-;; ::
-;; ::::::::::::::::::::
-
-;; No operation, needed in case the user uses -g but not -O.
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop || nop"
-  [(set_attr "length" "8")
-   (set_attr "type" "long")])
-
-;; Pseudo instruction that prevents the scheduler from moving code above this
-;; point.
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  ""
-  [(set_attr "length" "0")
-   (set_attr "type" "unknown")])
-
-
-;; END CYGNUS LOCAL -- meissner/d30v
diff --git a/gcc/config/d30v/libgcc1.asm b/gcc/config/d30v/libgcc1.asm
deleted file mode 100755
index dd18248..0000000
--- a/gcc/config/d30v/libgcc1.asm
+++ /dev/null
@@ -1,193 +0,0 @@
-/* CYGNUS LOCAL -- meissner/d30v */
-/* Assembly support functions for libgcc1.
- *
- *   Copyright (C) 1997 Free Software Foundation, Inc.
- *   Contributed by Cygnus Support
- * 
- * This file is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- * 
- * In addition to the permissions in the GNU General Public License, the
- * Free Software Foundation gives you unlimited permission to link the
- * compiled version of this file with other programs, and to distribute
- * those programs without any restriction coming from the use of this
- * file.  (The General Public License restrictions do apply in other
- * respects; for example, they cover modification of the file, and
- * distribution when not linked into another program.)
- * 
- * This file is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, 59 Temple Place - Suite 330,
- * Boston, MA 02111-1307, USA.
- * 
- *    As a special exception, if you link this library with files
- *    compiled with GCC to produce an executable, this does not cause
- *    the resulting executable to be covered by the GNU General Public License.
- *    This exception does not however invalidate any other reasons why
- *    the executable file might be covered by the GNU General Public License.
- */
-
-
-#ifdef L_udivsi3
-
-/* For division, we use the following algorithm:
- *
- *	unsigned
- *	__divsi3 (unsigned a, unsigned b)
- *	{
- *	  unsigned al = a;
- *	  unsigned ah = 0;
- *	  unsigned tmpf;
- *	  int i;
- *
- *	  for (i = 32; i > 0; i--)
- *	    {
- *	      ah = (ah << 1) | (al >> 31);
- *	      tmpf = (ah >= b) ? 1 : 0;
- *	      ah -= ((tmpf) ? b : 0);
- *	      al = (al << 1) | tmpf;
- *	    }
- *
- *	  return al;	// for __udivsi3
- *	  return ah;	// for __umodsi3
- *	}
- */
-
-	.file	"_udivsi3"
-	.text
-	.globl	__umodsi3
-	.globl	__udivsi3
-	.type	__umodsi3,@function
-	.type	__udivsi3,@function
-	.stabs	"libgcc1.asm",100,0,0,__umodsi3
-	.stabs	"int:t(0,1)=r(0,1);-2147483648;2147483647;",128,0,0,0
-	.stabs	"__umodsi3:F(0,1)",36,0,1,__umodsi3
-	.stabs	"a:P(0,1)",64,0,1,2
-	.stabs	"b:P(0,1)",64,0,1,3
-
-__umodsi3:
-	bra.s .Lmerge		|| orfg	f1,f1,1		; indicate this is __umodsi3
-.Lumod:
-	.size	__umodsi3,.Lumod-__umodsi3
-	.stabs	"",36,0,0,.Lumod-__umodsi3
-
-	.stabs	"__udivsi3:F(0,1)",36,0,1,__udivsi3
-	.stabs	"a:P(0,1)",64,0,1,2
-	.stabs	"b:P(0,1)",64,0,1,3
-__udivsi3:
-	andfg	f1,f1,0		|| nop			; indicate this is __udivsi3
-
-.Lmerge:
-	; r2 = al
-	; r3 = b
-	; r4 = ah
-	; r5 = loop counter
-	; f0 = tmpf
-	; f1 = 1 if this is mod, 0 if this is div
-	or	 r4,r0,0	|| sub	 r5,r0,-32	; ah = 0, loop = 32
-
-.Lloop:
-	src	 r4,r2,-1	|| sub	 r5,r5,1	; ah = (ah << 1) | (al >> 31); decrement loop count
-	cmpuge	 f0,r4,r3	|| sra	 r2,r2,-1	; f0 = (ah >= b); al <<= 1
-	sub/tx	 r4,r4,r3	|| or/tx r2,r2,1	; ah -= (tmpf) ? b : 0; al |= tmpf
-	bratnz.s r5,.Lloop	|| nop			; loop back if not done
-	jmp	 link           || or/xt r2,r0,r4	; if mod, update register, then return to user
-.Ludiv:
-	.size	 __udivsi3,.Ludiv-__udivsi3
-	.stabs	"",36,0,0,.Ludiv-__udivsi3
-
-#endif /* L_udivsi3 */
-
-
-#ifdef L_divsi3
-
-/* For division, we use the following algorithm:
- *
- *	unsigned
- *	__divsi3 (unsigned a, unsigned b)
- *	{
- *	  unsigned al = __builtin_abs (a);
- *	  unsigned b2 = __builtin_abs (b);
- *	  unsigned ah = 0;
- *	  unsigned tmpf;
- *	  int i;
- *
- *	  for (i = 32; i > 0; i--)
- *	    {
- *	      ah = (ah << 1) | (al >> 31);
- *	      tmpf = (ah >= b2) ? 1 : 0;
- *	      ah -= ((tmpf) ? b2 : 0);
- *	      al = (al << 1) | tmpf;
- *	    }
- *
- *	  if (a < 0)
- *	    ah = -ah, al = -al;
- *
- *	  if (b < 0)
- *	    al = -al;
- *
- *	  return al;	// for __divsi3
- *	  return ah;	// for __modsi3
- *	}
- */
-
-	.file	"_divsi3"
-	.text
-	.globl	__modsi3
-	.globl	__divsi3
-	.type	__modsi3,@function
-	.type	__divsi3,@function
-	.stabs	"libgcc1.asm",100,0,0,__modsi3
-	.stabs	"int:t(0,1)=r(0,1);-2147483648;2147483647;",128,0,0,0
-	.stabs	"__modsi3:F(0,1)",36,0,1,__modsi3
-	.stabs	"a:P(0,1)",64,0,1,2
-	.stabs	"b:P(0,1)",64,0,1,3
-
-__modsi3:
-	bra.s .Lmerge		|| orfg	f1,f1,1		; indicate this is __modsi3
-.Lmod:
-	.size	__modsi3,.Lmod-__modsi3
-	.stabs	"",36,0,0,.Lmod-__modsi3
-
-	.stabs	"__divsi3:F(0,1)",36,0,1,__divsi3
-	.stabs	"a:P(0,1)",64,0,1,2
-	.stabs	"b:P(0,1)",64,0,1,3
-__divsi3:
-	andfg	f1,f1,0		|| nop			; indicate this is __divsi3
-
-.Lmerge:
-	; r2 = al
-	; r3 = b2
-	; r4 = ah
-	; r5 = loop counter
-	; r6 = a
-	; r7 = b
-	; f0 = tmpf
-	; f1 = 1 if this is mod, 0 if this is div
-	or	 r6,r0,r2	|| or	  r7,r0,r3	; copy original inputs
-	abs	 r2,r2		|| abs	  r3,r3		; make both postive
-	or	 r4,r0,0	|| sub	 r5,r0,-32	; ah = 0, loop = 32
-
-.Lloop:
-	src	 r4,r2,-1	|| sub	  r5,r5,1	; ah = (ah << 1) | (al >> 31); decrement loop count
-	cmpuge	 f0,r4,r3	|| sra	  r2,r2,-1	; f0 = (ah >= b); al <<= 1
-	sub/tx	 r4,r4,r3	|| or/tx  r2,r2,1	; ah -= (tmpf) ? b : 0; al |= tmpf
-	bratnz.s r5,.Lloop	|| nop			; loop back if not done
-	cmplt    f0,r6,0	|| nop			; f0 = (a < 0)
-
-	sub/tx	 r2,r0,r2	|| sub/tx r4,r0,r4	; negate both al, ah if (a < 0)
-	cmplt	 f0,r7,0	-> sub/tx r2,r0,r2	; negate al if (b < 0)
-	jmp	 link		|| or/xt  r2,r0,r4	; update result if mod; return to user
-.Ldiv:
-	.size	 __divsi3,.Ldiv-__divsi3
-	.stabs	"",36,0,0,.Ldiv-__divsi3
-
-#endif /* L_divsi3 */
-/* END CYGNUS LOCAL -- meissner/d30v */
diff --git a/gcc/config/d30v/t-d30v b/gcc/config/d30v/t-d30v
deleted file mode 100755
index feeb96f..0000000
--- a/gcc/config/d30v/t-d30v
+++ /dev/null
@@ -1,36 +0,0 @@
-# CYGNUS LOCAL -- meissner/d30v
-# Build libgcc1 from assembler sources
-LIBGCC1 = libgcc1-asm.a
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = d30v/libgcc1.asm
-LIB1ASMFUNCS = _udivsi3 _divsi3
-
-# Turn on full debug for libgcc.a.
-LIBGCC2_DEBUG_CFLAGS = -g
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... 
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c config.status
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c config.status
-	echo '#define FLOAT' > fp-bit.c
-	echo '#define _fpadd_parts _fpadd_parts_sf' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# For svr4 we build crtbegin.o and crtend.o which serve to add begin and
-# end labels to the .ctors and .dtors section when we link using gcc.
-
-EXTRA_PARTS=crtbegin.o crtend.o
-
-# We need to use -fPIC when we are using gcc to compile the routines in
-# crtstuff.c.  This is only really needed when we are going to use gcc/g++
-# to produce a shared library, but since we don't know ahead of time when
-# we will be doing that, we just always use -fPIC when compiling the
-# routines in crtstuff.c.
-
-# Right now, disable, since we don't support shared libraries on d30v yet.
-#CRTSTUFF_T_CFLAGS = -fPIC
-# END CYGNUS LOCAL --meissner/d30v
diff --git a/gcc/config/d30v/xm-d30v.h b/gcc/config/d30v/xm-d30v.h
deleted file mode 100755
index 905d843..0000000
--- a/gcc/config/d30v/xm-d30v.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/* CYGNUS LOCAL -- meissner/d30v */
-/* Definitions of target machine for use as an example.
-   Hack to fit.
-   Copyright (C) 1997 Free Software Foundation, Inc.
-   Contributed by Cygnus Solutions.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define	FALSE	0
-#define	TRUE	1
-
-/* Define this macro if the host system is System V.  */
-/* #define USG */
-
-/* Define this macro if the host system is VMS.  */
-/* #define VMS */
-
-/* A C expression for the status code to be returned when the compiler exits
-   after serious errors.  */
-#define FATAL_EXIT_CODE 33
-
-/* A C expression for the status code to be returned when the compiler exits
-   without serious errors.  */
-#define SUCCESS_EXIT_CODE 0
-
-/* Defined if the host machine stores words of multi-word values in big-endian
-   order.  (GNU CC does not depend on the host byte ordering within a word.)  */
-#define HOST_WORDS_BIG_ENDIAN
-
-/* Define this macro to be 1 if the host machine stores `DFmode', `XFmode' or
-   `TFmode' floating point numbers in memory with the word containing the sign
-   bit at the lowest address; otherwise, define it to be zero.
-
-   This macro need not be defined if the ordering is the same as for multi-word
-   integers.  */
-/* #define HOST_FLOAT_WORDS_BIG_ENDIAN */
-
-/* A numeric code distinguishing the floating point format for the host
-   machine.  See `TARGET_FLOAT_FORMAT' in *Note Storage Layout:: for the
-   alternatives and default.  */
-/* #define HOST_FLOAT_FORMAT */
-
-/* A C expression for the number of bits in `char' on the host machine.  */
-#define HOST_BITS_PER_CHAR 8
-
-/* A C expression for the number of bits in `short' on the host machine.  */
-#define HOST_BITS_PER_SHORT 16
-
-/* A C expression for the number of bits in `int' on the host machine.  */
-#define HOST_BITS_PER_INT 32
-
-/* A C expression for the number of bits in `long' on the host machine.  */
-#define HOST_BITS_PER_LONG 32
-
-/* Define this macro to indicate that the host compiler only supports `int' bit
-   fields, rather than other integral types, including `enum', as do most C
-   compilers.  */
-/* #define ONLY_INT_FIELDS */
-
-/* A C expression for the size of ordinary obstack chunks.  If you don't define
-   this, a usually-reasonable default is used.  */
-/* #define OBSTACK_CHUNK_SIZE */
-
-/* The function used to allocate obstack chunks.  If you don't define this,
-   `xmalloc' is used.  */
-/* #define OBSTACK_CHUNK_ALLOC */
-
-/* The function used to free obstack chunks.  If you don't define this, `free'
-   is used.  */
-/* #define OBSTACK_CHUNK_FREE */
-
-/* Define this macro to indicate that the compiler is running with the `alloca'
-   implemented in C.  This version of `alloca' can be found in the file
-   `alloca.c'; to use it, you must also alter the `Makefile' variable `ALLOCA'.
-   (This is done automatically for the systems on which we know it is needed.)
-
-   If you do define this macro, you should probably do it as follows:
-
-        #ifndef __GNUC__
-        #define USE_C_ALLOCA
-        #else
-        #define alloca __builtin_alloca
-        #endif
-
-   so that when the compiler is compiled with GNU CC it uses the more efficient
-   built-in `alloca' function.  */
-
-#ifndef __GNUC__
-#define USE_C_ALLOCA
-#else
-#define alloca __builtin_alloca
-#endif
-
-/* Define this macro to indicate that the host compiler does not properly
-   handle converting a function value to a pointer-to-function when it is used
-   in an expression.  */
-/* #define FUNCTION_CONVERSION_BUG */
-
-/* Define this if the library function `vprintf' is available on your system.  */
-/* #define HAVE_VPRINTF */
-
-/* Define this macro to enable support for multibyte characters in the input to
-   GNU CC.  This requires that the host system support the ANSI C library
-   functions for converting multibyte characters to wide characters.  */
-/* #define MULTIBYTE_CHARS */
-
-/* Define this if the library function `putenv' is available on your system.  */
-/* #define HAVE_PUTENV */
-
-/* Define this if your system is POSIX.1 compliant.  */
-/* #define POSIX */
-
-/* Define this if your system *does not* provide the variable `sys_siglist'.  */
-/* #define NO_SYS_SIGLIST */
-
-/* Define this if your system has the variable `sys_siglist', and there is
-   already a declaration of it in the system header files.  */
-/* #define DONT_DECLARE_SYS_SIGLIST */
-
-/* Define this to be 1 if you know that the host compiler supports prototypes,
-   even if it doesn't define __STDC__, or define it to be 0 if you do not want
-   any prototypes used in compiling GNU CC.  If `USE_PROTOTYPES' is not
-   defined, it will be determined automatically whether your compiler supports
-   prototypes by checking if `__STDC__' is defined.  */
-/* #define USE_PROTOTYPES */
-
-/* Define this if you wish suppression of prototypes generated from the machine
-   description file, but to use other prototypes within GNU CC.  If
-   `USE_PROTOTYPES' is defined to be 0, or the host compiler does not support
-   prototypes, this macro has no effect.  */
-/* #define NO_MD_PROTOTYPES */
-
-/* Define this if you wish to generate prototypes for the `gen_call' or
-   `gen_call_value' functions generated from the machine description file.  If
-   `USE_PROTOTYPES' is defined to be 0, or the host compiler does not support
-   prototypes, or `NO_MD_PROTOTYPES' is defined, this macro has no effect.  As
-   soon as all of the machine descriptions are modified to have the appropriate
-   number of arguments, this macro will be removed.
-
-   Some systems do provide this variable, but with a different name such as
-   `_sys_siglist'.  On these systems, you can define `sys_siglist' as a macro
-   which expands into the name actually provided.  */
-/* #define MD_CALL_PROTOTYPES */
-
-/* Define this macro to be a C character constant representing the character
-   used to separate components in paths.  The default value is.  the colon
-   character */
-/* #define PATH_SEPARATOR */
-
-/* If your system uses some character other than slash to separate directory
-   names within a file specification, define this macro to be a C character
-   constant specifying that character.  When GNU CC displays file names, the
-   character you specify will be used.  GNU CC will test for both slash and the
-   character you specify when parsing filenames.  */
-/* #define DIR_SEPARATOR */
-
-/* Define this macro to be a C string representing the suffix for object files
-   on your machine.  If you do not define this macro, GNU CC will use `.o' as
-   the suffix for object files.  */
-/* #define OBJECT_SUFFIX */
-
-/* Define this macro to be a C string representing the suffix for executable
-   files on your machine.  If you do not define this macro, GNU CC will use the
-   null string as the suffix for object files.  */
-/* #define EXECUTABLE_SUFFIX */
-
-/* If defined, `collect2' will scan the individual object files specified on
-   its command line and create an export list for the linker.  Define this
-   macro for systems like AIX, where the linker discards object files that are
-   not referenced from `main' and uses export lists.  */
-/* #define COLLECT_EXPORT_LIST */
-
-/* In addition, configuration files for system V define `bcopy', `bzero' and
-   `bcmp' as aliases.  Some files define `alloca' as a macro when compiled with
-   GNU CC, in order to take advantage of the benefit of GNU CC's built-in
-   `alloca'.  */
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* end of xm-generic.h */
-/* END CYGNUS LOCAL -- meissner/d30v */
diff --git a/gcc/config/dbx.h b/gcc/config/dbx.h
deleted file mode 100755
index c5cd3b5..0000000
--- a/gcc/config/dbx.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Prefer DBX (stabs) debugging information.
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file causes gcc to prefer using DBX (stabs) debugging
-   information.  The configure script will add a #include of this file
-   to tm.h when --with-stabs is used for certain targets.  */
-
-#ifndef DBX_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-#endif
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
diff --git a/gcc/config/dbxcoff.h b/gcc/config/dbxcoff.h
deleted file mode 100755
index 9497a70..0000000
--- a/gcc/config/dbxcoff.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Definitions needed when using stabs embedded in COFF sections.
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file may be included by any COFF target which wishes to
-   support -gstabs generating stabs in sections, as produced by gas
-   and understood by gdb.  */
-
-/* Output DBX (stabs) debugging information if doing -gstabs.  */
-
-#undef DBX_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-
-/* Generate SDB debugging information by default. */
-
-#ifndef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
-#endif
-
-/* Be function-relative for block and source line stab directives.  */
-
-#undef DBX_BLOCKS_FUNCTION_RELATIVE
-#define DBX_BLOCKS_FUNCTION_RELATIVE 1
-
-/* but, to make this work, functions must appear prior to line info.  */
-
-#undef DBX_FUNCTION_FIRST
-#define DBX_FUNCTION_FIRST
-
-/* Generate a blank trailing N_SO to mark the end of the .o file, since
-   we can't depend upon the linker to mark .o file boundaries with
-   embedded stabs.  */
-
-#undef DBX_OUTPUT_MAIN_SOURCE_FILE_END
-#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME)			\
-  fprintf (FILE,							\
-	   "\t.text\n\t.stabs \"\",%d,0,0,Letext\nLetext:\n", N_SO)
-
-/* Like block addresses, stabs line numbers are relative to the
-   current function.  */
-
-#undef ASM_OUTPUT_SOURCE_LINE
-#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE)			\
-{ if (write_symbols == SDB_DEBUG) {				\
-    fprintf ((FILE), "\t.ln\t%d\n",				\
-	     ((sdb_begin_function_line > -1)			\
-	      ? (LINE) - sdb_begin_function_line : 1));		\
-  } else if (write_symbols == DBX_DEBUG) {			\
-    static int sym_lineno = 1;					\
-    char buffer[256];						\
-    ASM_GENERATE_INTERNAL_LABEL (buffer, "LM", sym_lineno);	\
-    fprintf (FILE, ".stabn 68,0,%d,", LINE);			\
-    assemble_name (FILE, buffer);				\
-    putc ('-', FILE);						\
-    assemble_name (FILE,					\
-		   XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
-    putc ('\n', FILE);						\
-    ASM_OUTPUT_INTERNAL_LABEL (FILE, "LM", sym_lineno);		\
-    sym_lineno++;						\
-  } }
-
-/* When generating stabs debugging, use N_BINCL entries.  */
-
-#undef DBX_USE_BINCL
-#define DBX_USE_BINCL
-
-/* There is no limit to the length of stabs strings.  */
-
-#ifndef DBX_CONTIN_LENGTH
-#define DBX_CONTIN_LENGTH 0
-#endif
diff --git a/gcc/config/dsp16xx/dsp16xx.c b/gcc/config/dsp16xx/dsp16xx.c
deleted file mode 100755
index e7bcdce..0000000
--- a/gcc/config/dsp16xx/dsp16xx.c
+++ /dev/null
@@ -1,2241 +0,0 @@
-/* Subroutines for assembler code output on the DSP1610.
-   Copyright (C) 1994, 1995, 1997 Free Software Foundation, Inc.
-   Contributed by Michael Collison (collison@world.std.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Some output-actions in dsp1600.md need these.  */
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "tree.h"
-#include "expr.h"
-#include "flags.h"
-
-char *text_seg_name;
-char *rsect_text;
-char *data_seg_name;
-char *rsect_data;
-char *bss_seg_name;
-char *rsect_bss;
-char *const_seg_name;
-char *rsect_const;
-
-char *chip_name;
-char *save_chip_name;
-
-/* Save the operands of a compare. The 16xx has not lt or gt, so
-   in these cases we swap the operands and reverse the condition */
-
-rtx dsp16xx_compare_op0;
-rtx dsp16xx_compare_op1;
-struct rtx_def *(*dsp16xx_compare_gen)();
-
-static char *fp;
-static char *sp;
-static char *rr;
-static char *a1h;
-
-struct dsp16xx_frame_info current_frame_info;
-struct dsp16xx_frame_info zero_frame_info;
-
-rtx dsp16xx_addhf3_libcall = (rtx) 0;
-rtx dsp16xx_subhf3_libcall = (rtx) 0;
-rtx dsp16xx_mulhf3_libcall = (rtx) 0;
-rtx dsp16xx_divhf3_libcall = (rtx) 0;
-rtx dsp16xx_cmphf3_libcall = (rtx) 0;
-rtx dsp16xx_fixhfhi2_libcall = (rtx) 0;
-rtx dsp16xx_floathihf2_libcall = (rtx) 0;
-rtx dsp16xx_neghf2_libcall = (rtx) 0;
-
-rtx dsp16xx_mulhi3_libcall = (rtx) 0;
-rtx dsp16xx_udivqi3_libcall = (rtx) 0;
-rtx dsp16xx_udivhi3_libcall = (rtx) 0;
-rtx dsp16xx_divqi3_libcall = (rtx) 0;
-rtx dsp16xx_divhi3_libcall = (rtx) 0;
-rtx dsp16xx_modqi3_libcall = (rtx) 0;
-rtx dsp16xx_modhi3_libcall = (rtx) 0;
-rtx dsp16xx_umodqi3_libcall = (rtx) 0;
-rtx dsp16xx_umodhi3_libcall = (rtx) 0;
-rtx dsp16xx_ashrhi3_libcall = (rtx) 0;
-rtx dsp16xx_ashlhi3_libcall = (rtx) 0;
-rtx dsp16xx_ucmphi2_libcall = (rtx) 0;
-rtx dsp16xx_lshrhi3_libcall = (rtx) 0;
-
-char *himode_reg_name[] = HIMODE_REGISTER_NAMES;
-
-#define SHIFT_INDEX_1   0
-#define SHIFT_INDEX_4   1
-#define SHIFT_INDEX_8   2
-#define SHIFT_INDEX_16  3
-
-static char *ashift_right_asm[] = 
-{
-  "%0=%0>>1",
-  "%0=%0>>4",
-  "%0=%0>>8",
-  "%0=%0>>16"
-};
-
-static char *ashift_right_asm_first[] = 
-{
-  "%0=%1>>1",
-  "%0=%1>>4",
-  "%0=%1>>8",
-  "%0=%1>>16"
-};
-
-static char *ashift_left_asm[] = 
-{
-  "%0=%0<<1",
-  "%0=%0<<4",
-  "%0=%0<<8",
-  "%0=%0<<16"
-};
-
-static char *ashift_left_asm_first[] = 
-{
-  "%0=%1<<1",
-  "%0=%1<<4",
-  "%0=%1<<8",
-  "%0=%1<<16"
-};
-
-static char *lshift_right_asm[] = 
-{
-  "%0=%0>>1\n\t%0=%b0&0x7fff",
-  "%0=%0>>4\n\t%0=%b0&0x0fff",
-  "%0=%0>>8\n\t%0=%b0&0x00ff",
-  "%0=%0>>16\n\t%0=%b0&0x0000"
-};
-
-static char *lshift_right_asm_first[] = 
-{
-  "%0=%1>>1\n\t%0=%b0&0x7fff",
-  "%0=%1>>4\n\t%0=%b0&0x0fff",
-  "%0=%1>>8\n\t%0=%b0&0x00ff",
-  "%0=%1>>16\n\t%0=%b0&0x0000"
-};
-
-int 
-hard_regno_mode_ok (regno, mode)
-int regno;
-enum machine_mode mode;
-{
-  switch ((int) mode)
-    {
-    case VOIDmode:
-      return 1;
-      
-      /* 
-	We can't use the c0-c2 for QImode, since they are only
-	8 bits in length */
-
-    case QImode:
-      if (regno != REG_C0 && regno != REG_C1 && regno != REG_C2)
-	return 1;
-      else
-	return 0;
-      
-      /* We only allow a0, a1, y, and p to be allocated for 32-bit modes.
-         Additionally we allow the virtual ybase registers to be used for 32-bit
-	 modes. */
-      
-    case HFmode:
-    case SFmode:
-    case DFmode:
-    case XFmode:
-    case HImode:
-    case SImode:
-    case DImode:
-      if (regno == REG_A0 || regno == REG_A1 || regno == REG_Y || regno == REG_PROD
-	  || (IS_YBASE_REGISTER_WINDOW(regno) && ((regno & 1) == 0)))
-	return 1;
-      else
-	return 0;
-      
-    default:
-      return 0;
-    }
-}
-
-enum reg_class
-dsp16xx_reg_class_from_letter (c)
-int c;
-{
-  switch (c)
-    {
-    case 'A':
-      return ACCUM_REGS;
-      
-    case 'h':
-      return ACCUM_HIGH_REGS;
-      
-    case 'j':
-      return A0H_REG;
-      
-    case 'k':
-      return A0L_REG;
-      
-    case 'q':
-      return A1H_REG;
-      
-    case 'u':
-      return A1L_REG;
-      
-    case 'x':
-      return X_REG;
-
-    case 'y':
-      return YH_REG;
-
-    case 'z':
-      return YL_REG;
-
-    case 't':
-      return P_REG;
-
-    case 'Z':
-      return Y_OR_P_REGS;
-
-    case 'd':
-      return ACCUM_Y_OR_P_REGS;
-
-    case 'C':
-      return NO_FRAME_Y_ADDR_REGS;
-
-    case 'a':
-      return Y_ADDR_REGS;
-
-    case 'B':
-      return (TARGET_BMU ? BMU_REGS : NO_REGS);
-
-    case 'Y':
-      return YBASE_VIRT_REGS;
-
-    case 'v':
-      return PH_REG;
-
-    case 'w':
-      return PL_REG;
-
-    case 'W':
-      return J_REG;
-
-    case 'e':
-      return YBASE_ELIGIBLE_REGS;
-
-    case 'b':
-      return ACCUM_LOW_REGS;
-
-    case 'c':
-      return NON_YBASE_REGS;
-
-    case 'f':
-      return Y_REG;
-
-    case 'D':
-      return SLOW_MEM_LOAD_REGS;
-
-    default:
-      fatal ("Invalid register class letter %c", c);
-      return NO_REGS;
-    }
-}
-/* Return the class number of the smallest class containing
-   reg number REGNO. */
-
-int 
-regno_reg_class(regno)
-int regno;
-{
-  switch (regno)
-    {
-    case REG_A0L:
-      return (int) A0L_REG;
-    case REG_A1L:
-      return (int) A1L_REG;
-      
-    case REG_A0:
-      return (int) A0H_REG;
-    case REG_A1:
-      return (int) A1H_REG;
-      
-    case REG_X:
-      return (int) X_REG;
-      
-    case REG_Y:
-      return (int) YH_REG;
-    case REG_YL:
-      return (int) YL_REG;
-      
-    case REG_PROD:
-      return (int) PH_REG;
-    case REG_PRODL:
-      return (int) PL_REG;
-      
-    case REG_R0: case REG_R1: case REG_R2: case REG_R3:
-      return (int) Y_ADDR_REGS;
-      
-    case REG_J:
-      return (int) J_REG;
-    case REG_K:
-      return (int) GENERAL_REGS;
-      
-    case REG_YBASE:
-      return (int) GENERAL_REGS;
-      
-    case REG_PT:
-      return (int) GENERAL_REGS;
-      
-    case REG_AR0: case REG_AR1: case REG_AR2: case REG_AR3:
-      return (int) BMU_REGS;
-      
-    case REG_C0: case REG_C1: case REG_C2:
-      return (int) GENERAL_REGS;
-      
-    case REG_PR:
-      return (int) GENERAL_REGS;
-      
-    case REG_RB:
-      return (int) GENERAL_REGS;
-      
-    case REG_YBASE0: case REG_YBASE1: case REG_YBASE2: case REG_YBASE3:
-    case REG_YBASE4: case REG_YBASE5: case REG_YBASE6: case REG_YBASE7:
-    case REG_YBASE8: case REG_YBASE9: case REG_YBASE10: case REG_YBASE11:
-    case REG_YBASE12: case REG_YBASE13: case REG_YBASE14: case REG_YBASE15:
-    case REG_YBASE16: case REG_YBASE17: case REG_YBASE18: case REG_YBASE19:
-    case REG_YBASE20: case REG_YBASE21: case REG_YBASE22: case REG_YBASE23:
-    case REG_YBASE24: case REG_YBASE25: case REG_YBASE26: case REG_YBASE27:
-    case REG_YBASE28: case REG_YBASE29: case REG_YBASE30: case REG_YBASE31:
-      return (int) YBASE_VIRT_REGS;
-      
-    default:
-      return (int) NO_REGS;
-    }
-}
-
-/* A C expression for the maximum number of consecutive registers of class CLASS
-   needed to hold a value of mode MODE */
-
-int
-class_max_nregs(class, mode)
-enum reg_class class;
-enum machine_mode mode;
-{
-    return (GET_MODE_SIZE(mode));
-}
-
-enum reg_class
-limit_reload_class (mode, class)
-enum machine_mode mode;
-enum reg_class class;
-{
-  switch ((int) class)
-    {
-    case NO_REGS:
-    case A0H_REG:
-    case A0L_REG:
-    case A0_REG:
-    case A1H_REG:
-      return class;
-
-    case ACCUM_HIGH_REGS:
-      fatal ("ACCUM_HIGH_REGS class in limit_reload_class");
-
-    case A1L_REG:
-    case ACCUM_LOW_REGS:
-    case A1_REG:
-      return class;
-
-    case ACCUM_REGS:
-      if (GET_MODE_SIZE(mode) == 1)
-	return ACCUM_LOW_REGS;
-      else
-	return class;
-
-    case X_REG:
-    case X_OR_ACCUM_LOW_REGS:
-      return class;
-
-    case X_OR_ACCUM_REGS:
-      if (GET_MODE_SIZE(mode) == 1)
-	return X_OR_ACCUM_LOW_REGS;
-      else
-	return class;
-
-    case YH_REG:
-      return class;
-
-    case YH_OR_ACCUM_HIGH_REGS:
-      fatal ("YH_OR_ACCUM_HIGH_REGS found in limit_reload_class");
-
-    case X_OR_YH_REGS:
-      return class;
-
-    case YL_REG:
-      /* Register 'yl' is invalid for QImode, so we should never
-	 see it. */
-
-      fatal ("YL found in limit_reload_class");
-
-    case YL_OR_ACCUM_LOW_REGS:
-    case X_OR_YL_REGS:
-      return class;
-
-    case Y_REG:
-      if (GET_MODE_SIZE(mode) > 1)
-	return class;
-      else
-	return YH_REG;
-
-    case ACCUM_OR_Y_REGS:
-      if (GET_MODE_SIZE(mode) > 1)
-	return class;
-      else
-	return YL_OR_ACCUM_LOW_REGS;
-
-    case PH_REG:
-    case X_OR_PH_REGS:
-    case PL_REG:
-    case PL_OR_ACCUM_LOW_REGS:
-    case X_OR_PL_REGS:
-      return class;
-
-    case P_REG:
-      if (GET_MODE_SIZE(mode) > 1)
-	return class;
-      else
-	return PL_REG;
-
-    case ACCUM_OR_P_REGS:
-      if (GET_MODE_SIZE(mode) > 1)
-	return class;
-      else
-	return PL_OR_ACCUM_LOW_REGS;
-
-    case YL_OR_P_REGS:
-    case ACCUM_LOW_OR_YL_OR_P_REGS:
-      return class;
-
-    case Y_OR_P_REGS:
-      return class;
-
-    case ACCUM_Y_OR_P_REGS:
-      if (GET_MODE_SIZE(mode) > 1)
-	return class;
-      else
-	return ACCUM_LOW_OR_YL_OR_P_REGS;
-
-    case NO_FRAME_Y_ADDR_REGS:
-    case Y_ADDR_REGS: 
-    case ACCUM_LOW_OR_Y_ADDR_REGS:
-      return class;
-
-    case ACCUM_OR_Y_ADDR_REGS:
-      if (GET_MODE_SIZE(mode) > 1)
-	return ACCUM_REGS;
-      else
-	return ACCUM_LOW_OR_Y_ADDR_REGS;
-
-    case X_OR_Y_ADDR_REGS:
-      return class;
-
-    case Y_OR_Y_ADDR_REGS:
-    case P_OR_Y_ADDR_REGS:
-    case NON_HIGH_YBASE_ELIGIBLE_REGS:
-
-    case J_REG:
-      return class;
-
-    case YBASE_ELIGIBLE_REGS:
-      if (GET_MODE_SIZE(mode) > 1)
-	return ACCUM_Y_P_OR_YBASE_REGS;
-      else
-	return NON_HIGH_YBASE_ELIGIBLE_REGS;
-
-    case J_OR_DAU_16_BIT_REGS:
-      if (GET_MODE_SIZE(mode) == 1)
-	return J_REG;
-      else
-	return class;
-
-    case BMU_REGS:
-    case NOHIGH_NON_ADDR_REGS:
-      return class;
-
-    case NON_ADDR_REGS:
-      if (GET_MODE_SIZE(mode) > 1)
-	return class;
-      else
-	return NOHIGH_NON_ADDR_REGS;
-
-    case NOHIGH_NON_YBASE_REGS:
-      return class;
-
-    case NON_YBASE_REGS:
-      if (GET_MODE_SIZE(mode) > 1)
-	return class;
-      else
-	return NOHIGH_NON_YBASE_REGS;
-
-    case YBASE_VIRT_REGS:
-    case ACCUM_LOW_OR_YBASE_REGS:
-      return class;
-      
-    case ACCUM_OR_YBASE_REGS:
-      if (GET_MODE_SIZE(mode) > 1)
-	return class;
-      else
-	return ACCUM_LOW_OR_YBASE_REGS;
-
-    case X_OR_YBASE_REGS:
-      return class;
-
-    case Y_OR_YBASE_REGS:
-    case ACCUM_LOW_YL_PL_OR_YBASE_REGS:
-    case P_OR_YBASE_REGS:
-      return class;
-
-    case ACCUM_Y_P_OR_YBASE_REGS:
-      return ACCUM_LOW_YL_PL_OR_YBASE_REGS;
-
-    case Y_ADDR_OR_YBASE_REGS:
-    case YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS:
-      return class;
-
-    case YBASE_OR_YBASE_ELIGIBLE_REGS:
-      if (GET_MODE_SIZE(mode) > 1)
-	return class;
-      else
-	return YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS;
-
-    case NO_HIGH_ALL_REGS:
-      return class;
-
-    case ALL_REGS:
-      if (GET_MODE_SIZE(mode) > 1)
-	return class;
-      else
-	return NO_HIGH_ALL_REGS;
-
-    default:
-      return class;
-    }
-}
-
-int
-dsp16xx_register_move_cost (from, to)
-enum reg_class from, to;
-{
-#if 0
-  if (from == NO_REGS || to == NO_REGS || (from == to))
-    return 2;
-#endif
-
-  if (from == A0H_REG || from == A0L_REG || from == A0_REG ||
-      from == A1H_REG || from == ACCUM_HIGH_REGS || from == A1L_REG ||
-      from == ACCUM_LOW_REGS || from == A1_REG || from == ACCUM_REGS)
-    {
-      if (to == Y_REG || to == P_REG)
-	return 4;
-      else
-	return 2;
-    }
-
-  if (to == A0H_REG || to == A0L_REG || to == A0_REG ||
-      to == A1H_REG || to == ACCUM_HIGH_REGS || to == A1L_REG ||
-      to == ACCUM_LOW_REGS || to == A1_REG || to == ACCUM_REGS)
-    {
-      return 2;
-    }
-
-#if 0
-  if (from == YBASE_VIRT_REGS)
-    {
-      if (to == X_REG || to == YH_REG || to == YL_REG ||
-	  to == Y_REG || to == PL_REG || to == PH_REG ||
-	  to == P_REG || to == Y_ADDR_REGS || to == YBASE_ELIGIBLE_REGS ||
-	  to == Y_OR_P_REGS)
-	{
-	  return 2;
-	}
-      else
-	return 4;
-    }
-
-  if (to == YBASE_VIRT_REGS)
-    {
-      if (from == X_REG || from == YH_REG || from == YL_REG ||
-	  from == Y_REG || from == PL_REG || from == PH_REG ||
-	  from == P_REG || from == Y_ADDR_REGS || from == YBASE_ELIGIBLE_REGS ||
-	  from == Y_OR_P_REGS)
-	{
-	  return 2;
-	}
-      else
-	return 4;
-    }
-#endif
-  return 4;
-}
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.
-   Also, we must ensure that a PLUS is reloaded either
-   into an accumulator or an address register.  */
-
-enum reg_class
-preferred_reload_class (x, class)
-     rtx x;
-     enum reg_class class;
-{
-  /* The ybase registers cannot have constants copied directly
-     to them. */
-
-  if (CONSTANT_P (x))
-    {
-      if (class == ALL_REGS)
-	return NON_YBASE_REGS;
-    }
-
-  if (class == ALL_REGS && REG_P (x) && !TARGET_RESERVE_YBASE
-      && IS_YBASE_REGISTER_WINDOW (REGNO(x)))
-    return YBASE_ELIGIBLE_REGS;
-
-  if (GET_CODE (x) == PLUS)
-    {
-      if (GET_MODE (x) == QImode
-	  && REG_P (XEXP (x,0))
-	  && (XEXP (x,0) == frame_pointer_rtx
-	      || XEXP (x,0) == stack_pointer_rtx)
-	  && (GET_CODE (XEXP (x,1)) == CONST_INT))
-	{
-	  if (class == ACCUM_HIGH_REGS)
-	    return class;
-
-	  if (reg_class_subset_p (ACCUM_HIGH_REGS, class))
-	    return ACCUM_HIGH_REGS;
-
-	  /* We will use accumulator 'a1l' for reloading a
-	     PLUS. We can only use one accumulator because
-	     'reload_inqi' only allows one alternative to be
-	     used. */
-
-	  else if (class == ACCUM_LOW_REGS)
-	    return A1L_REG;
-	  else if (class == A0L_REG)
-	    return NO_REGS;
-	  else
-	    return class;
-	}
-
-      if (class == NON_YBASE_REGS || class == YBASE_ELIGIBLE_REGS)
-	return Y_ADDR_REGS;
-      else
-	return class;
-    }
-  else if (GET_CODE (x) == MEM)
-    {
-      if (class == ALL_REGS)
-	{
-#if 0
-	  if (GET_MODE(x) == HImode)
-	    return NO_ACCUM_NON_YBASE_REGS;
-	  else
-#endif
-	    return NON_YBASE_REGS;
-	}
-      else
-	return class;
-    }
-  else
-    return class;
-}
-	
-/* Return the register class of a scratch register needed to copy IN into
-   or out of a register in CLASS in MODE.  If it can be done directly,
-   NO_REGS is returned.  */
-
-enum reg_class
-secondary_reload_class (class, mode, in)
-     enum reg_class class;
-     enum machine_mode mode;
-     rtx in;
-{
-  int regno = -1;
-
-  if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
-    regno = true_regnum (in);
-
-  if (class == ACCUM_HIGH_REGS 
-      || class == ACCUM_LOW_REGS
-      || class == A1L_REG
-      || class == A0L_REG
-      || class == A1H_REG
-      || class == A0H_REG)
-    {
-      if (GET_CODE (in) == PLUS && mode == QImode)
-	{
-	  rtx addr0 = XEXP (in, 0);
-	  rtx addr1 = XEXP (in, 1);
-	  
-	  /* If we are reloading a plus (reg:QI) (reg:QI)
-	     we need an additional register. */ 
-	  if (REG_P (addr0) && REG_P (addr1))
-	    return NO_REGS;
-	}
-    }
-
-  /* We can place anything into ACCUM_REGS and can put ACCUM_REGS
-     into anything.  */
-
-  if ((class == ACCUM_REGS || class == ACCUM_HIGH_REGS ||
-       class == ACCUM_LOW_REGS || class == A0H_REG || class == A0L_REG ||
-       class == A1H_REG || class == A1_REG) || 
-      (regno >= REG_A0 && regno < REG_A1L + 1))
-    return NO_REGS;
-
-  /* We can copy the ybase registers into:
-     r0-r3, a0-a1, y, p, & x or the union of
-     any of these. */
-
-  if (!TARGET_RESERVE_YBASE && IS_YBASE_REGISTER_WINDOW(regno))
-    {
-      switch ((int) class)
-	{
-	case (int) X_REG:
-	case (int) X_OR_ACCUM_LOW_REGS:
-	case (int) X_OR_ACCUM_REGS:
-	case (int) YH_REG:
-	case (int) YH_OR_ACCUM_HIGH_REGS:
-	case (int) X_OR_YH_REGS:
-	case (int) YL_REG:
-	case (int) YL_OR_ACCUM_LOW_REGS:
-	case (int) X_OR_Y_REGS:
-	case (int) X_OR_YL_REGS:
-	case (int) Y_REG:
-	case (int) ACCUM_OR_Y_REGS:
-	case (int) PH_REG:
-	case (int) X_OR_PH_REGS:
-	case (int) PL_REG:
-	case (int) PL_OR_ACCUM_LOW_REGS:
-	case (int) X_OR_PL_REGS:
-	case (int) YL_OR_PL_OR_ACCUM_LOW_REGS:
-	case (int) P_REG:
-	case (int) ACCUM_OR_P_REGS:
-	case (int) YL_OR_P_REGS:
-	case (int) ACCUM_LOW_OR_YL_OR_P_REGS:
-	case (int) Y_OR_P_REGS:
-	case (int) ACCUM_Y_OR_P_REGS:
-	case (int) Y_ADDR_REGS:
-	case (int) ACCUM_LOW_OR_Y_ADDR_REGS:
-	case (int) ACCUM_OR_Y_ADDR_REGS:
-	case (int) X_OR_Y_ADDR_REGS:
-	case (int) Y_OR_Y_ADDR_REGS:
-	case (int) P_OR_Y_ADDR_REGS:
-	case (int) YBASE_ELIGIBLE_REGS:
-	  return NO_REGS;
-
-	default:
-	  return ACCUM_HIGH_REGS;
-	}
-    }
-
-  /* We can copy r0-r3, a0-a1, y, & p
-     directly to the ybase registers. In addition
-     we can use any of the ybase virtual registers
-     as the secondary reload registers when copying
-     between any of these registers. */
-
-  if (!TARGET_RESERVE_YBASE && regno != -1)
-    {
-      switch (regno)
-	{
-	case REG_A0:
-	case REG_A0L:
-	case REG_A1:
-	case REG_A1L:
-	case REG_X:
-	case REG_Y:
-	case REG_YL:
-	case REG_PROD:
-	case REG_PRODL:
-	case REG_R0:
-	case REG_R1:
-	case REG_R2:
-	case REG_R3:
-	  if (class == YBASE_VIRT_REGS)
-	    return NO_REGS;
-	  else
-	    {
-	      switch ((int) class)
-		{
-		case (int) X_REG:
-		case (int) X_OR_ACCUM_LOW_REGS:
-		case (int) X_OR_ACCUM_REGS:
-		case (int) YH_REG:
-		case (int) YH_OR_ACCUM_HIGH_REGS:
-		case (int) X_OR_YH_REGS:
-		case (int) YL_REG:
-		case (int) YL_OR_ACCUM_LOW_REGS:
-		case (int) X_OR_Y_REGS:
-		case (int) X_OR_YL_REGS:
-		case (int) Y_REG:
-		case (int) ACCUM_OR_Y_REGS:
-		case (int) PH_REG:
-		case (int) X_OR_PH_REGS:
-		case (int) PL_REG:
-		case (int) PL_OR_ACCUM_LOW_REGS:
-		case (int) X_OR_PL_REGS:
-		case (int) YL_OR_PL_OR_ACCUM_LOW_REGS:
-		case (int) P_REG:
-		case (int) ACCUM_OR_P_REGS:
-		case (int) YL_OR_P_REGS:
-		case (int) ACCUM_LOW_OR_YL_OR_P_REGS:
-		case (int) Y_OR_P_REGS:
-		case (int) ACCUM_Y_OR_P_REGS:
-		case (int) Y_ADDR_REGS:
-		case (int) ACCUM_LOW_OR_Y_ADDR_REGS:
-		case (int) ACCUM_OR_Y_ADDR_REGS:
-		case (int) X_OR_Y_ADDR_REGS:
-		case (int) Y_OR_Y_ADDR_REGS:
-		case (int) P_OR_Y_ADDR_REGS:
-		case (int) YBASE_ELIGIBLE_REGS:
-		  return YBASE_VIRT_REGS;
-
-		default:
-		  break;
-		}
-	    }
-	}
-    }
-
-  /* Memory or constants can be moved from or to any register
-     except the ybase virtual registers */
-  if (regno == -1 && GET_CODE(in) != PLUS)
-    {
-      if (class == YBASE_VIRT_REGS)
-	return NON_YBASE_REGS;
-      else
-        return NO_REGS;
-    }
-
-  if (GET_CODE (in) == PLUS && mode == QImode)
-    {
-      rtx addr0 = XEXP (in, 0);
-      rtx addr1 = XEXP (in, 1);
-
-      /* If we are reloading a plus (reg:QI) (reg:QI)
-	 we need a low accumulator, not a high one. */
-      if (REG_P (addr0) && REG_P (addr1))
-	return ACCUM_LOW_REGS;
-    }
-
-#if 0
-  if (REG_P(in))
-    return ACCUM_REGS;
-#endif
-
-  /* Otherwise, we need a high accumulator(s).  */
-  return ACCUM_HIGH_REGS;
-}
-
-int
-symbolic_address_operand (op, mode)
-rtx op;
-enum machine_mode mode;
-{
-    return (symbolic_address_p (op));
-
-}
-
-int symbolic_address_p (op)
-rtx op;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return 1;
-
-    case CONST:
-      op = XEXP (op, 0);
-      return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
-	       || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-	      && GET_CODE (XEXP (op, 1)) == CONST_INT
-              && INTVAL (XEXP (op,1)) < 0x20);
-
-    default:
-      return 0;
-    }
-}
-
-/* For a Y address space operand we allow only *rn, *rn++, *rn--.
-   This routine only recognizes *rn, the '<>' constraints recognize
-   *rn++, *rn-- */
-
-int
-Y_address_operand (op, mode)
-rtx op;
-enum machine_mode mode;
-{
-   return (memory_address_p (mode, op) && !symbolic_address_p (op));
-}	     
-
-int
-sp_operand (op, mode)
-rtx op;
-enum machine_mode mode;
-{
-    return (GET_CODE (op) == PLUS
-	    && (XEXP (op, 0) == stack_pointer_rtx
-		|| XEXP (op, 0) == frame_pointer_rtx)
-	    && GET_CODE (XEXP (op,1)) == CONST_INT);
-}
-
-int
-sp_operand2 (op, mode)
-rtx op;
-enum machine_mode mode;
-{
-  if ((GET_CODE (op) == PLUS 
-       && (XEXP (op, 0) == stack_pointer_rtx
-	   || XEXP (op, 0) == frame_pointer_rtx)
-       && (REG_P (XEXP (op,1))
-	   && IS_ADDRESS_REGISTER (REGNO (XEXP(op, 1))))))
-    return 1;
-  else if ((GET_CODE (op) == PLUS
-       && (XEXP (op, 1) == stack_pointer_rtx
-	   || XEXP (op, 1) == frame_pointer_rtx)
-       && (REG_P (XEXP (op,0))
-	   && IS_ADDRESS_REGISTER (REGNO (XEXP(op, 1))))))
-    return 1;
-  else
-    return 0;
-}
-
-int
-nonmemory_arith_operand (op, mode)
-rtx op;
-enum machine_mode mode;
-{
-  return (immediate_operand (op, mode) || arith_reg_operand (op, mode));
-}
-
-int
-arith_reg_operand (op, mode)
-rtx op;
-enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  && (GET_CODE (op) != REG
-	      || REGNO (op) >= FIRST_PSEUDO_REGISTER
-	      || (!(IS_YBASE_REGISTER_WINDOW (REGNO (op)))
-		  && REGNO (op) != FRAME_POINTER_REGNUM)));
-}
-
-int
-call_address_operand (op, mode)
-rtx op;
-enum machine_mode mode;
-{
-    if (symbolic_address_p (op) || REG_P(op))
-    {
-	return 1;
-    }
-
-    return 0;
-}
-
-int
-dsp16xx_comparison_operator (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  return ((mode == VOIDmode || GET_MODE (op) == mode)
-	  && GET_RTX_CLASS (GET_CODE (op)) == '<'
-	  && (GET_CODE(op) != GE && GET_CODE (op) != LT &&
-	      GET_CODE (op) != GEU && GET_CODE (op) != LTU));
-}
-
-void
-notice_update_cc(exp)
-rtx exp;
-{
-    if (GET_CODE (exp) == SET)
-    {
-	/* Jumps do not alter the cc's.  */
-
-	if (SET_DEST (exp) == pc_rtx)
-	    return;
-
-	/* Moving register or memory into a register:
-	   it doesn't alter the cc's, but it might invalidate
-	   the RTX's which we remember the cc's came from.
-	   (Note that moving a constant 0 or 1 MAY set the cc's).  */
-	if (REG_P (SET_DEST (exp))
-	    && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM))
-	{
-	    if (cc_status.value1
-		&& reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
-		cc_status.value1 = 0;
-	    if (cc_status.value2
-		&& reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
-		cc_status.value2 = 0;
-	    return;
-	}
-	/* Moving register into memory doesn't alter the cc's.
-	   It may invalidate the RTX's which we remember the cc's came from.  */
-	if (GET_CODE (SET_DEST (exp)) == MEM && REG_P (SET_SRC (exp)))
-	{
-	    if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM)
-		cc_status.value1 = 0;
-	    if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM)
-		cc_status.value2 = 0;
-	    return;
-	}
-	/* Function calls clobber the cc's.  */
-	else if (GET_CODE (SET_SRC (exp)) == CALL)
-	{
-	    CC_STATUS_INIT;
-	    return;
-	}
-	/* Tests and compares set the cc's in predictable ways.  */
-	else if (SET_DEST (exp) == cc0_rtx)
-	{
-	    CC_STATUS_INIT;
-	    cc_status.value1 = SET_SRC (exp);
-	    return;
-	}
-	/* Certain instructions effect the condition codes. */
-	else if (GET_MODE_CLASS (GET_MODE (SET_SRC (exp))) == MODE_INT)
-	    switch( GET_CODE (SET_SRC (exp)) )
-	    {
-	    case PLUS: 
-	    case MINUS:
-	      if (REG_P (SET_DEST (exp)))
-		{
-		  /* Address registers don't set the condition codes */
-		  if (IS_ADDRESS_REGISTER (REGNO (SET_DEST (exp))))
-		    {
-		      CC_STATUS_INIT;
-		      break;
-		    }
-		}
-	    case ASHIFTRT: 
-	    case LSHIFTRT:
-	    case ASHIFT: 
-	    case AND: 
-	    case IOR: 
-	    case XOR:
-	    case MULT:
-	    case NEG:
-	    case NOT:
-	      cc_status.value1 = SET_SRC (exp);
-	      cc_status.value2 = SET_DEST (exp);
-	      break;
-	      
-	    default:
-	      CC_STATUS_INIT;
-	    }
-	else
-	{
-	    CC_STATUS_INIT;
-	}
-    }
-    else if (GET_CODE (exp) == PARALLEL
-	     && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
-    {
-	if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
-	    return;
-
-	if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
-	{
-	    CC_STATUS_INIT;
-	    cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
-	    return;
-	}
-
-	CC_STATUS_INIT;
-    }
-    else
-    {
-	CC_STATUS_INIT;
-    }
-}
-
-int
-dsp16xx_makes_calls ()
-{
-  rtx insn;
-
-  for (insn = get_insns (); insn; insn = next_insn (insn))
-    if (GET_CODE (insn) == CALL_INSN)
-      return (1);
-
-  return 0;
-}
-
-long compute_frame_size (size)
-int size;
-{
-  long total_size;
-  long var_size;
-  long args_size;
-  long extra_size;
-  long reg_size;
-
-  reg_size = 0;
-  extra_size = 0;
-  var_size = size;
-  args_size = current_function_outgoing_args_size;
-  reg_size = reg_save_size ();  
-
-  total_size = var_size + args_size + extra_size + reg_size;
-
-
-  /* Save other computed information.  */
-  current_frame_info.total_size  = total_size;
-  current_frame_info.var_size    = var_size;
-  current_frame_info.args_size   = args_size;
-  current_frame_info.extra_size  = extra_size;
-  current_frame_info.reg_size    = reg_size;
-  current_frame_info.initialized = reload_completed;
-  current_frame_info.reg_size	 = reg_size / UNITS_PER_WORD;
-  current_frame_info.function_makes_calls = dsp16xx_makes_calls ();
-
-  if (reg_size)
-    {
-      unsigned long offset = args_size + var_size + reg_size;
-      current_frame_info.sp_save_offset = offset;
-      current_frame_info.fp_save_offset = offset - total_size;
-    }
-
-  return total_size;
-}
-
-int
-dsp16xx_call_saved_register (regno)
-int regno;
-{
-  return (regs_ever_live[regno] && !call_used_regs[regno] &&
-	  !IS_YBASE_REGISTER_WINDOW(regno));
-
-}
-
-int
-ybase_regs_ever_used ()
-{
-  int regno;
-  int live = 0;
-
-  for (regno = REG_YBASE0; regno <= REG_YBASE31; regno++)
-    if (regs_ever_live[regno])
-      {
-	live = 1;
-	break;
-      }
-
-  return live;
-}
-
-void 
-function_prologue (file, size)
-FILE *file;
-int  size;
-{
-  int regno;
-  long total_size;
-  fp = reg_names[FRAME_POINTER_REGNUM];
-  sp = reg_names[STACK_POINTER_REGNUM];
-  rr = reg_names[RETURN_ADDRESS_REGNUM];   /* return address register */
-  a1h = reg_names[REG_A1];
-  
-  total_size = compute_frame_size (size);
-  
-  fprintf( file, "\t/* FUNCTION PROLOGUE: */\n" );
-  fprintf (file, "\t/* total=%d, vars= %d, regs= %d, args=%d, extra= %d */\n",
-	   current_frame_info.total_size,
-	   current_frame_info.var_size,
-	   current_frame_info.reg_size,
-	   current_function_outgoing_args_size,
-	   current_frame_info.extra_size);
-  
-  fprintf (file, "\t/* fp save offset= %d, sp save_offset= %d */\n\n",
-	   current_frame_info.fp_save_offset,
-	   current_frame_info.sp_save_offset);
-  /* Set up the 'ybase' register window. */
-  
-  if (ybase_regs_ever_used())
-    {
-      fprintf (file, "\t%s=%s\n", a1h, reg_names[REG_YBASE]);
-      if (TARGET_YBASE_HIGH)
-	fprintf (file, "\t%s=%sh-32\n", reg_names[REG_A1], a1h);
-      else
-	fprintf (file, "\t%s=%sh+32\n", reg_names[REG_A1], a1h);
-      fprintf (file, "\t%s=%s\n", reg_names[REG_YBASE], a1h);
-    }
-  
-#if 0
-  if (current_frame_info.function_makes_calls)
-    fprintf( file, "\t*%s++=%s\n", sp, rr );   /* Push return address */
-#endif
-  
-  
-  if (current_frame_info.var_size)
-    {
-      if (current_frame_info.var_size == 1)
-	fprintf (file, "\t*%s++\n", sp);
-      else
-        {
-	  if(SMALL_INTVAL(current_frame_info.var_size) && ((current_frame_info.var_size & 0x8000) == 0))
-	    fprintf (file, "\t%s=%d\n\t*%s++%s\n", reg_names[REG_J], current_frame_info.var_size, sp, reg_names[REG_J]);
-	  else
-	    fatal ("Stack size > 32k");
-	}
-    }
-  
-  /* Save any registers this function uses, unless they are
-   * used in a call, in which case we don't need to
-   */
-  
-  for( regno = 0; regno < FIRST_PSEUDO_REGISTER; ++ regno )
-    if (dsp16xx_call_saved_register (regno)) 
-      {
-#if OLD_REGISTER_SAVE
-	fprintf( file, "\t*%s++=%s\n", sp, reg_names[regno] );
-#else
-	fprintf( file, "\tpush(*%s)=%s\n", sp, reg_names[regno] );
-#endif
-      }
-  
-  if (current_frame_info.args_size)
-    {
-      if (current_frame_info.args_size == 1)
-	fprintf (file, "\t*%s++\n", sp);
-      else
-        {
-	  if(SMALL_INTVAL(current_frame_info.args_size) && ((current_frame_info.args_size & 0x8000) == 0))
-	    fprintf (file, "\t%s=%d\n\t*%s++%s\n", reg_names[REG_J], current_frame_info.args_size, sp, reg_names[REG_J]);
-	  else
-	    fatal ("Stack size > 32k");
-	}
-    }
-  
-  if (frame_pointer_needed)
-    {
-      fprintf( file, "\t%s=%s\n", a1h, sp );
-      fprintf( file, "\t%s=%s\n", fp, a1h );  /* Establish new base frame */
-      fprintf( file, "\t%s=%d\n", reg_names[REG_J], -total_size);
-      fprintf( file, "\t*%s++%s\n", fp, reg_names[REG_J]);
-    }
-  
-  fprintf( file, "\t/* END FUNCTION PROLOGUE: */\n\n" );
-}
-
-void
-init_emulation_routines ()
-{
- dsp16xx_addhf3_libcall = (rtx) 0;
- dsp16xx_subhf3_libcall = (rtx) 0;
- dsp16xx_mulhf3_libcall = (rtx) 0;
- dsp16xx_divhf3_libcall = (rtx) 0;
- dsp16xx_cmphf3_libcall = (rtx) 0;
- dsp16xx_fixhfhi2_libcall = (rtx) 0;
- dsp16xx_floathihf2_libcall = (rtx) 0;
- dsp16xx_neghf2_libcall = (rtx) 0;
-
- dsp16xx_mulhi3_libcall = (rtx) 0;
- dsp16xx_udivqi3_libcall = (rtx) 0;
- dsp16xx_udivhi3_libcall = (rtx) 0;
- dsp16xx_divqi3_libcall = (rtx) 0;
- dsp16xx_divhi3_libcall = (rtx) 0;
- dsp16xx_modqi3_libcall = (rtx) 0;
- dsp16xx_modhi3_libcall = (rtx) 0;
- dsp16xx_umodqi3_libcall = (rtx) 0;
- dsp16xx_umodhi3_libcall = (rtx) 0;
- dsp16xx_ashrhi3_libcall = (rtx) 0;
- dsp16xx_ashlhi3_libcall = (rtx) 0;
- dsp16xx_ucmphi2_libcall = (rtx) 0;
- dsp16xx_lshrhi3_libcall = (rtx) 0;
-
-}
-void
-function_epilogue (file, size)
-FILE *file;
-int   size;
-{
-  int regno;
-  int initial_stack_dec = 0;
-  
-  fp = reg_names[FRAME_POINTER_REGNUM];
-  sp = reg_names[STACK_POINTER_REGNUM];
-  rr = reg_names[RETURN_ADDRESS_REGNUM];   /* return address register */
-  a1h = reg_names[REG_A1];
-  
-  fprintf( file, "\n\t/* FUNCTION EPILOGUE: */\n" );
-  
-  if (current_frame_info.args_size)
-    {
-      if (current_frame_info.args_size == 1)
-	fprintf (file, "\t*%s--\n", sp);
-      else
-	{
-	  fprintf (file, "\t%s=%d\n\t*%s++%s\n", 
-		   reg_names[REG_J], -current_frame_info.args_size, sp, reg_names[REG_J]);
-	}
-    }
-  
-  if (ybase_regs_ever_used())
-    {
-      fprintf (file, "\t%s=%s\n", a1h, reg_names[REG_YBASE]);
-      if (TARGET_YBASE_HIGH)
-	fprintf (file, "\t%s=%sh+32\n", reg_names[REG_A1], a1h);
-      else
-	fprintf (file, "\t%s=%sh-32\n", reg_names[REG_A1], a1h);
-      fprintf (file, "\t%s=%s\n", reg_names[REG_YBASE], a1h);
-    }
-  
-  for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; --regno)
-    if (dsp16xx_call_saved_register(regno))
-      {
-#if OLD_REGISTER_SAVE
-	if (!initial_stack_dec)
-	  {
-	    initial_stack_dec = 1;
-	    fprintf (file, "\t*%s--\n", sp);
-	  }
-#endif
-
-#if OLD_REGISTER_SAVE
-	fprintf( file, "\t%s=*%s--\n", reg_names[regno], sp );
-#else
-	fprintf( file, "\t%s=pop(*%s)\n", reg_names[regno], sp );
-#endif
-      }
-  
-  /* If we restored any registers we have to account for the
-     initial pre-decrement. But only if we had any local variables
-     or spills. */
-#if OLD_REGISTER_SAVE  
-  if (initial_stack_dec) 
-    fprintf (file, "\t*%s++\n", sp);
-#endif
-  
-  if (current_frame_info.var_size)
-    {
-      if (current_frame_info.var_size == 1)
-	fprintf (file, "\t*%s--\n", sp);
-      else
-	{
-	  fprintf (file, "\t%s=%d\n\t*%s++%s\n", 
-		   reg_names[REG_J], -current_frame_info.var_size, sp, reg_names[REG_J]);
-	}
-    }
-  
-  fprintf (file, "\treturn\n");
-  /* Reset the frame info for the next function */
-  current_frame_info = zero_frame_info;
-  init_emulation_routines ();
-}
-
-/* Emit insns to move operands[1] into operands[0].
-
-   Return 1 if we have written out everything that needs to be done to
-   do the move.  Otherwise, return 0 and the caller will emit the move
-   normally.  */
-
-int
-emit_move_sequence (operands, mode)
-     rtx *operands;
-     enum machine_mode mode;
-{
-  register rtx operand0 = operands[0];
-  register rtx operand1 = operands[1];
-
-  /* We can only store registers to memory.  */
-
-  if (GET_CODE (operand0) == MEM && GET_CODE (operand1) != REG)
-    operands[1] = force_reg (mode, operand1);
-
-  return 0;
-}
-
-void
-double_reg_from_memory (operands)
-rtx operands[];
-{
-    rtx xoperands[4];
-
-    if (GET_CODE(XEXP(operands[1],0)) == POST_INC)
-    {
-	output_asm_insn ("%u0=%1", operands);
-	output_asm_insn ("%w0=%1", operands);
-    }
-    else if (GET_CODE(XEXP(operands[1],0)) == POST_DEC)
-    {
-	xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
-	xoperands[0] = operands[0];
-	
-	/* We can't use j anymore since the compiler can allocate it. */
-/*	output_asm_insn ("j=-3\n\t%u0=*%1++\n\t%w0=*%1++j", xoperands); */
-	output_asm_insn ("%u0=*%1++\n\t%w0=*%1--\n\t*%1--\n\t*%1--", xoperands);
-    }
-    else if (GET_CODE(XEXP(operands[1],0)) == PLUS)
-    {
-      rtx addr;
-      rtx base;
-      int offset;
-
-      output_asm_insn ("%u0=%1", operands);
-
-
-      /* In order to print out the least significant word we must
-	 use 'offset + 1'.  */
-      addr = XEXP (operands[1], 0);
-      if (GET_CODE (XEXP(addr,0)) == CONST_INT)
-	offset = INTVAL(XEXP(addr,0)) + 1;
-      else if (GET_CODE (XEXP(addr,1)) == CONST_INT)
-	offset = INTVAL(XEXP(addr,1)) + 1;
-
-      fprintf (asm_out_file, "\t%s=*(%d)\n", reg_names[REGNO(operands[0]) + 1], offset + 31);
-    }
-    else
-    {
-	xoperands[1] = XEXP(operands[1],0);
-	xoperands[0] = operands[0];
-
-	output_asm_insn ("%u0=*%1++\n\t%w0=*%1--", xoperands);
-    }
-}
-
-
-void
-double_reg_to_memory (operands)
-rtx operands[];
-{
-    rtx xoperands[4];
-
-    if (GET_CODE(XEXP(operands[0],0)) == POST_INC)
-    {
-	output_asm_insn ("%0=%u1", operands);
-	output_asm_insn ("%0=%w1", operands);
-    }
-    else if (GET_CODE(XEXP(operands[0],0)) == POST_DEC)
-    {
-	xoperands[0] = XEXP (XEXP (operands[0], 0), 0);
-	xoperands[1] = operands[1];
-	
-	/* We can't use j anymore since the compiler can allocate it. */
-
-/*	output_asm_insn ("j=-3\n\t*%0++=%u1\n\t*%0++j=%w1", xoperands); */
-	output_asm_insn ("*%0++=%u1\n\t*%0--=%w1\n\t*%0--\n\t*%0--", xoperands);
-
-    }
-    else if (GET_CODE(XEXP(operands[0],0)) == PLUS)
-    {
-      rtx addr;
-      int offset;
-
-      output_asm_insn ("%0=%u1", operands);
-
-      /* In order to print out the least significant word we must
-	 use 'offset + 1'.  */
-      addr = XEXP (operands[0], 0);
-      if (GET_CODE (XEXP(addr,0)) == CONST_INT)
-	offset = INTVAL(XEXP(addr,0)) + 1;
-      else if (GET_CODE (XEXP(addr,1)) == CONST_INT)
-	offset = INTVAL(XEXP(addr,1)) + 1;
-      else
-	fatal ("Invalid addressing mode");
-
-      fprintf (asm_out_file, "\t*(%d)=%s\n", offset + 31, reg_names[REGNO(operands[1]) + 1]);
-    }
-    else
-    {
-	xoperands[0] = XEXP(operands[0],0);
-	xoperands[1] = operands[1];
-
-	output_asm_insn ("*%0++=%u1\n\t*%0--=%w1", xoperands);
-    }
-}
-
-void
-override_options ()
-{
-  if (chip_name == (char *) 0)
-    chip_name = DEFAULT_CHIP_NAME;
-
-  if (text_seg_name == (char *) 0)
-    text_seg_name = DEFAULT_TEXT_SEG_NAME;
-  
-  if (data_seg_name == (char *) 0)
-    data_seg_name = DEFAULT_DATA_SEG_NAME;
-  
-  if (bss_seg_name == (char *) 0)
-    bss_seg_name = DEFAULT_BSS_SEG_NAME;
-  
-  if (const_seg_name == (char *) 0)
-    const_seg_name = DEFAULT_CONST_SEG_NAME;
-  
-  save_chip_name = (char *) xmalloc (strlen(chip_name) + 1);
-  strcpy (save_chip_name, chip_name);
-
-  rsect_text = (char *) xmalloc (strlen(".rsect ") + 
-				 strlen(text_seg_name) + 3);
-  rsect_data = (char *) xmalloc (strlen(".rsect ") + 
-				 strlen(data_seg_name) + 3);
-  rsect_bss = (char *) xmalloc (strlen(".rsect ") + 
-				strlen(bss_seg_name) + 3);
-  rsect_const = (char *) xmalloc (strlen(".rsect ") + 
-				  strlen(const_seg_name) + 3);
-  
-  sprintf (rsect_text, ".rsect \"%s\"", text_seg_name);
-  sprintf (rsect_data, ".rsect \"%s\"", data_seg_name);
-  sprintf (rsect_bss,  ".rsect \"%s\"", bss_seg_name);
-  sprintf (rsect_const, ".rsect \"%s\"", const_seg_name);
-  
-  if (optimize)
-    {
-      if (TARGET_OPTIMIZE_SPEED)
-	{
-	  flag_unroll_loops = 1;
-	  flag_inline_functions = 1;
-	}
-    }
-}
-
-enum rtx_code
-next_cc_user_code (insn)
-rtx insn;
-{
-  if ( !(insn = next_cc0_user (insn)))
-    abort ();
-  else if (GET_CODE (insn) == JUMP_INSN
-	   && GET_CODE (PATTERN (insn)) == SET
-	   && GET_CODE (SET_SRC (PATTERN (insn))) == IF_THEN_ELSE)
-    return GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0));
-  else if (GET_CODE (insn) == INSN
-	   && GET_CODE (PATTERN (insn)) == SET
-	   && comparison_operator (SET_SRC (PATTERN (insn)), VOIDmode))
-    return GET_CODE (SET_SRC (PATTERN (insn)));
-  else
-    abort ();
-}
-
-int
-next_cc_user_unsigned (insn)
-     rtx insn;
-{
-  switch (next_cc_user_code (insn))
-    {
-    case GTU:
-    case GEU:
-    case LTU:
-    case LEU:
-      return 1;
-    default:
-      return 0;
-    }
-}
-
-void
-print_operand(file, op, letter)
-FILE *file;
-rtx op;
-int letter;
-{
-    enum rtx_code code;
-
-    code = GET_CODE(op);
-
-    switch (letter)
-    {
-       case 'I':
-	  code = reverse_condition (code);
-	  /* Fallthrough */
-
-       case 'C':
-          if (code == EQ) 
-          { 
-	      fputs ("eq", file); 
-	      return; 
-	  }
-          else if (code == NE)  
-	  { 
-	      fputs ("ne", file); 
-	      return; 
-	  }
-          else if (code == GT || code == GTU)  
-	  { 
-	      fputs ("gt", file); 
-	      return; 
-	  }
-          else if (code == LT || code == LTU)  
-	  { 
-	      fputs ("mi", file); 
-	      return; 
-	  }
-          else if (code == GE || code == GEU)  
-	  {
-	      fputs ("pl", file); 
-	      return; 
-	  }
-          else if (code == LE || code == LEU)  
-	  { 
-	      fputs ("le", file); 
-	      return; 
-	  }
-          else 
-	      abort ();
-	  break;
-
-       default:
-          break;  
-    }
-
-    if( code == REG )
-    {
-	/* Print the low half of a 32-bit register pair */
-        if (letter == 'w')
-           fprintf( file, "%s", reg_names[REGNO(op)+1] );
-        else if (letter == 'u' || !letter)
-           fprintf( file, "%s", reg_names[REGNO(op)]);
-	else if (letter == 'b')
-	    fprintf ( file, "%sh", reg_names[REGNO(op)]);
-	else if (letter == 'm')
-	  fprintf (file, "%s", himode_reg_name[REGNO(op)]);
-        else
-           fatal("Bad register extension code");
-    }
-    else if( code == MEM )
-        output_address( XEXP(op,0) );
-    else if( code == CONST_INT )
-    { 
-	HOST_WIDE_INT val = INTVAL (op);
-        if( letter == 'H' )
-            fprintf( file, HOST_WIDE_INT_PRINT_HEX, val & 0xffff);
-	else if (letter == 'h')
-            fprintf( file, HOST_WIDE_INT_PRINT_DEC, val);
-        else if( letter == 'U' )
-            fprintf( file, HOST_WIDE_INT_PRINT_HEX, (val >> 16) & 0xffff);
-        else
-           output_addr_const( file, op );
-    }
-    else if( code == CONST_DOUBLE && GET_MODE(op) != DImode )
-    {
-	  union { double d; int i[2]; } u;
-	  union { float f; int i; } u1;
-	  u.i[0] = CONST_DOUBLE_LOW (op);
-	  u.i[1] = CONST_DOUBLE_HIGH (op);
-	  u1.f = u.d;
-          fprintf( file, "0x%x", u1.i );
-    }
-    else output_addr_const( file, op);
-}
-
-
-void
-print_operand_address(file, addr)
-FILE *file;
-rtx addr;
-{
-  rtx base;
-  int offset;
-  
-  switch (GET_CODE (addr))
-    {
-    case REG:
-      fprintf (file, "*%s", reg_names[REGNO (addr)]);
-      break;
-    case POST_DEC:
-      fprintf (file, "*%s--", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-    case POST_INC:
-      fprintf (file, "*%s++", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-    case PLUS:
-      if (GET_CODE (XEXP(addr,0)) == CONST_INT)
-	offset = INTVAL(XEXP(addr,0)), base = XEXP(addr,1);
-      else if (GET_CODE (XEXP(addr,1)) == CONST_INT)
-	offset = INTVAL(XEXP(addr,1)), base = XEXP(addr,0);
-      if (GET_CODE (base) == REG && REGNO(base) == STACK_POINTER_REGNUM)
-	{
-	  if (offset >= -31 && offset <= 0)
-	    offset = 31 + offset;
-	  else
-	    fatal ("Invalid offset in ybase addressing");
-	}
-      else
-	fatal ("Invalid register in ybase addressing");
-      
-      fprintf (file, "*(%d)", offset);
-      break;
-      
-    default:
-      if( FITS_5_BITS( addr ) )
-	fprintf( file, "*(0x%x)", (INTVAL(addr) & 0x20) );
-      else
-	output_addr_const(file, addr);
-    }
-}
-
-void
-output_dsp16xx_float_const(operands)
-rtx *operands;
-{
-  rtx dst = operands[0];
-  rtx src = operands[1];
-  
-#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
-  REAL_VALUE_TYPE d;
-  long value;
-  
-  REAL_VALUE_FROM_CONST_DOUBLE (d, src);
-  REAL_VALUE_TO_TARGET_SINGLE (d, value);
-  
-  operands[1] = GEN_INT (value);
-  output_asm_insn ("%u0=%U1\n\t%w0=%H1", operands);
-#else
-  fatal ("inline float constants not supported on this host");
-#endif
-}
-
-int
-reg_save_size ()
-{
-  int reg_save_size = 0;
- int regno;
- 
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-    if (dsp16xx_call_saved_register (regno))
-      {
-	reg_save_size += UNITS_PER_WORD;
-      }
-
-  return (reg_save_size);
-}
-
-int
-dsp16xx_starting_frame_offset()
-{
-  int reg_save_size = 0;
- int regno;
- 
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-    if (dsp16xx_call_saved_register (regno))
-      {
-	reg_save_size += UNITS_PER_WORD;
-      }
-
-  return (reg_save_size);
-}
-
-int
-initial_frame_pointer_offset()
-{
-  int frame_size;
-  int regno;
-  int offset = 0;
-  
-  offset = compute_frame_size (get_frame_size());
-
-#ifdef STACK_GROWS_DOWNWARD
-  return (offset);
-#else
-  return (-offset);
-#endif
-}
-
-/* Generate the minimum number of 1600 core shift instructions
-   to shift by 'shift_amount'. */
-
-#if 0
-void
-emit_1600_core_shift (shift_op, operands, shift_amount, mode)
-enum rtx_code shift_op;
-rtx *operands;
-int shift_amount;
-enum machine_mode mode;
-{
-  int quotient;
-  int i;
-  int first_shift_emitted = 0;
-  
-  while (shift_amount != 0)
-    {
-      if (shift_amount/16)
-	{
-	  quotient = shift_amount/16;
-	  shift_amount = shift_amount - (quotient * 16);
-	  for (i = 0; i < quotient; i++)
-	    emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-				gen_rtx (shift_op, mode, 
-					 first_shift_emitted ? operands[0] : operands[1],
-					 GEN_INT (16))));
-	  first_shift_emitted = 1;
-	}
-      else if (shift_amount/8)
-	{
-	  quotient = shift_amount/8;
-	  shift_amount = shift_amount - (quotient * 8);
-	  for (i = 0; i < quotient; i++)
-	    emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-				gen_rtx (shift_op, mode, 
-					 first_shift_emitted ? operands[0] : operands[1],
-					 GEN_INT (8))));
-	  first_shift_emitted = 1;
-	}
-      else if (shift_amount/4)
-	{
-	  quotient = shift_amount/4;
-	  shift_amount = shift_amount - (quotient * 4);
-	  for (i = 0; i < quotient; i++)
-	    emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-				gen_rtx (shift_op, mode, 
-					 first_shift_emitted ? operands[0] : operands[1],
-					 GEN_INT (4))));
-	  first_shift_emitted = 1;
-	}
-      else if (shift_amount/1)
-	{
-	  quotient = shift_amount/1;
-	  shift_amount = shift_amount - (quotient * 1);
-	  for (i = 0; i < quotient; i++)
-	    emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-				gen_rtx (shift_op, mode, 
-					 first_shift_emitted ? operands[0] : operands[1],
-					 GEN_INT (1))));
-	  first_shift_emitted = 1;
-	}
-    }
-}
-#else
-void
-emit_1600_core_shift (shift_op, operands, shift_amount)
-enum rtx_code shift_op;
-rtx *operands;
-int shift_amount;
-{
-  int quotient;
-  int i;
-  int first_shift_emitted = 0;
-  char **shift_asm_ptr;
-  char **shift_asm_ptr_first;
-
-  if (shift_op == ASHIFT)
-    {
-      shift_asm_ptr = ashift_left_asm;
-      shift_asm_ptr_first = ashift_left_asm_first;
-    }
-  else if (shift_op == ASHIFTRT)
-    {
-      shift_asm_ptr = ashift_right_asm;
-      shift_asm_ptr_first = ashift_right_asm_first;
-    }
-  else if (shift_op == LSHIFTRT)
-    {
-      shift_asm_ptr = lshift_right_asm;
-      shift_asm_ptr_first = lshift_right_asm_first;
-    }
-  else
-    fatal ("Invalid shift operator in emit_1600_core_shift");
-
-  while (shift_amount != 0)
-    {
-      if (shift_amount/16)
-	{
-	  quotient = shift_amount/16;
-	  shift_amount = shift_amount - (quotient * 16);
-	  for (i = 0; i < quotient; i++)
-	    output_asm_insn ((first_shift_emitted ? shift_asm_ptr[SHIFT_INDEX_16]
-			      : shift_asm_ptr_first[SHIFT_INDEX_16]), operands);
-	  first_shift_emitted = 1;
-	}
-      else if (shift_amount/8)
-	{
-	  quotient = shift_amount/8;
-	  shift_amount = shift_amount - (quotient * 8);
-	  for (i = 0; i < quotient; i++)
-	    output_asm_insn ((first_shift_emitted ? shift_asm_ptr[SHIFT_INDEX_8]
-			      : shift_asm_ptr_first[SHIFT_INDEX_8]), operands);
-	  first_shift_emitted = 1;
-	}
-      else if (shift_amount/4)
-	{
-	  quotient = shift_amount/4;
-	  shift_amount = shift_amount - (quotient * 4);
-	  for (i = 0; i < quotient; i++)
-	    output_asm_insn ((first_shift_emitted ? shift_asm_ptr[SHIFT_INDEX_4]
-			      : shift_asm_ptr_first[SHIFT_INDEX_4]), operands);
-	  first_shift_emitted = 1;
-	}
-      else if (shift_amount/1)
-	{
-	  quotient = shift_amount/1;
-	  shift_amount = shift_amount - (quotient * 1);
-	  for (i = 0; i < quotient; i++)
-	    output_asm_insn ((first_shift_emitted ? shift_asm_ptr[SHIFT_INDEX_1]
-			      : shift_asm_ptr_first[SHIFT_INDEX_1]), operands);
-	  first_shift_emitted = 1;
-	}
-    }
-}
-#endif
-void
-  asm_output_common(file, name, size, rounded)
-FILE *file;
-char *name;
-int size;
-int rounded;
-{
-    bss_section ();
-    ASM_GLOBALIZE_LABEL (file, name);
-    assemble_name (file, name);
-    fputs (":", file);
-    if (rounded > 1)
-	fprintf (file, "%d * int\n", rounded);
-    else
-	fprintf (file, "int\n");
-}
-
-void
-asm_output_local(file, name, size, rounded)
-FILE *file;
-char *name;
-int size;
-int rounded;
-{
-    bss_section ();
-    assemble_name (file, name);
-    fputs (":", file);
-    if (rounded > 1)
-	fprintf (file, "%d * int\n", rounded);
-    else
-	fprintf (file, "int\n");
-}
-
-void
-asm_output_float (file, fp_const)
-FILE *file;
-double fp_const;
-{
-#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
-      REAL_VALUE_TYPE d = fp_const;
-      long value;
-
-      REAL_VALUE_TO_TARGET_SINGLE (d, value);
-      fputs ("\tint ", file);
-#ifdef WORDS_BIG_ENDIAN
-      fprintf (file, "0x%-4.4x, 0x%-4.4x", (value >> 16) & 0xffff, (value & 0xffff));
-#else
-      fprintf (file, "0x%-4.4x, 0x%-4.4x", (value & 0xffff), (value >> 16) & 0xffff);
-#endif
-      fputs ("\n", file);
-#else
-      fatal ("inline float constants not supported on this host");
-#endif
-}
-
-void
-asm_output_long (file, value)
-FILE *file;
-long value;
-{
-      fputs ("\tint ", file);
-#ifdef WORDS_BIG_ENDIAN
-      fprintf (file, "0x%-4.4x, 0x%-4.4x", (value >> 16) & 0xffff, (value & 0xffff));
-#else
-      fprintf (file, "0x%-4.4x, 0x%-4.4x", (value & 0xffff), (value >> 16) & 0xffff);
-#endif
-      fputs ("\n", file);
-}
-
-int
-dsp16xx_address_cost (addr)
-rtx addr;
-{
-    switch (GET_CODE (addr))
-    {
-	  default:
-	     break;
-
-	  case REG:
-	     return 1;
-
-	  case CONST:
-	     {
-	        rtx offset = const0_rtx;
-	        addr = eliminate_constant_term (addr, &offset);
-
-	        if (GET_CODE (addr) == LABEL_REF)
-	            return 2;
-
-	        if (GET_CODE (addr) != SYMBOL_REF)
-	            return 4;
-
-	        if (INTVAL (offset) == 0)
-	            return 2;
-             }
-	     /* fall through */
-
-	  case POST_INC: case POST_DEC:
-	     return (GET_MODE (addr) == QImode ? 1 : 2);
-
-	  case SYMBOL_REF: case LABEL_REF:
-	     return 2;
-
-	  case PLUS:
-	  {
-	     register rtx plus0 = XEXP (addr, 0);
-	     register rtx plus1 = XEXP (addr, 1);
-	     
-	     if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
-	     {
-		 plus0 = XEXP (addr, 1);
-		 plus1 = XEXP (addr, 0);
-	     }
-	     
-	     if (GET_CODE (plus0) != REG)
-		 break;
-	     
-	     switch (GET_CODE (plus1))
-	     {
-		   default:
-		      break;
-		 
-		   case CONST_INT:
-		      return 4;
-
-		   case CONST:
-		   case SYMBOL_REF:
-		   case LABEL_REF:
-		      return dsp16xx_address_cost (plus1) + 1;
-	     }
-	  }
-     }
-	     
-     return 4;
-}
-
-
-/* Determine whether a function argument is passed in a register, and
-   which register.
-
-   The arguments are CUM, which summarizes all the previous
-   arguments; MODE, the machine mode of the argument; TYPE,
-   the data type of the argument as a tree node or 0 if that is not known
-   (which happens for C support library functions); and NAMED,
-   which is 1 for an ordinary argument and 0 for nameless arguments that
-   correspond to `...' in the called function's prototype.
-
-   The value of the expression should either be a `reg' RTX for the
-   hard register in which to pass the argument, or zero to pass the
-   argument on the stack.
-
-   On the dsp1610 the first four words of args are normally in registers
-   and the rest are pushed. If we a long or on float mode, the argument
-   must begin on a even register boundary
-
-   Note that FUNCTION_ARG and FUNCTION_INCOMING_ARG were different.
-   For structures that are passed in memory, but could have been
-   passed in registers, we first load the structure into the
-   register, and then when the last argument is passed, we store
-   the registers into the stack locations.  This fixes some bugs
-   where GCC did not expect to have register arguments, followed */
-
-
-struct rtx_def *
-dsp16xx_function_arg (args_so_far, mode, type, named)
-     CUMULATIVE_ARGS args_so_far;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  if (TARGET_REGPARM)
-    {
-      if ((args_so_far & 1) != 0
-	  && (mode == HImode || GET_MODE_CLASS(mode) == MODE_FLOAT))
-	args_so_far++;
-
-      if (named && args_so_far < 4 && !MUST_PASS_IN_STACK (mode,type))
-	return gen_rtx (REG, mode, args_so_far + FIRST_REG_FOR_FUNCTION_ARG);
-      else
-	return (struct rtx_def *) 0;
-    }
-  else
-    return (struct rtx_def *) 0;
-}
-
-/* Advance the argument to the next argument position.  */
-
-void
-dsp16xx_function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;	/* current arg information */
-     enum machine_mode mode;	/* current arg mode */
-     tree type;			/* type of the argument or 0 if lib support */
-     int named;			/* whether or not the argument was named */
-{
-  if (TARGET_REGPARM)
-    {
-      if ((*cum & 1) != 0
-	  && (mode == HImode || GET_MODE_CLASS(mode) == MODE_FLOAT))
-	*cum += 1;
-
-      if (mode != BLKmode)
-	*cum += GET_MODE_SIZE (mode);
-      else
-	*cum += int_size_in_bytes (type);
-    }
-}
-
-void
-dsp16xx_file_start ()
-{
-  fprintf (asm_out_file, "#include <%s.h>\n", save_chip_name);
-#if 0
-	if (TARGET_BMU)
-		fprintf (asm_out_file, "#include <1610.h>\n");
-#endif
-}
-
-rtx
-gen_tst_reg (x)
-     rtx x;
-{
-  enum machine_mode mode;
-
-  mode = GET_MODE (x);
-
-  if (mode == QImode)
-    {
-	  emit_insn (gen_rtx (PARALLEL, VOIDmode,
-			gen_rtvec (2,
-				   gen_rtx (SET, VOIDmode, cc0_rtx, x),
-				   gen_rtx (CLOBBER, VOIDmode,
-					    gen_rtx (SCRATCH, QImode, 0)))));
-	}
-  else if (mode == HImode)
-    emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, x));
-  else
-    fatal ("Invalid mode for gen_tst_reg");
-
-  return cc0_rtx;
-}
-
-rtx
-gen_compare_reg (code, x, y)
-     enum rtx_code code;
-     rtx x, y;
-{
-  enum machine_mode mode;
-
-  mode = GET_MODE (x);
-  /* For floating point compare insns, a call is generated so don't
-     do anything here. */
-
-  if (GET_MODE_CLASS (mode) == MODE_FLOAT)
-    return cc0_rtx;
-
-  if (mode == QImode)
-    {
-      if (code == GTU || code == GEU ||
-	  code == LTU || code == LEU)
-	{
-	  emit_insn (gen_rtx (PARALLEL, VOIDmode,
-			gen_rtvec (3,
-				   gen_rtx (SET, VOIDmode, cc0_rtx,
-					    gen_rtx (COMPARE, mode, x, y)),
-				   gen_rtx (CLOBBER, VOIDmode,
-					    gen_rtx (SCRATCH, QImode, 0)),
-				   gen_rtx (CLOBBER, VOIDmode,
-					    gen_rtx (SCRATCH, QImode, 0)))));
-	}
-      else
-	{
-	  emit_insn (gen_rtx (PARALLEL, VOIDmode,
-			gen_rtvec (3,
-				   gen_rtx (SET, VOIDmode, cc0_rtx,
-					    gen_rtx (COMPARE, mode, x, y)),
-				   gen_rtx (CLOBBER, VOIDmode,
-					    gen_rtx (SCRATCH, QImode, 0)),
-				   gen_rtx (CLOBBER, VOIDmode,
-					    gen_rtx (SCRATCH, QImode, 0)))));
-	}
-    }
-  else if (mode == HImode)
-    {
-      if (code == GTU || code == GEU ||
-	  code == LTU || code == LEU)
-	{
-#if 1
-	  emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5,
-			     gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, x, y)),
-		             gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, QImode, 0)),
-		             gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, QImode, 0)),
-		             gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, QImode, 0)),
-		             gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, QImode, 0)))));
-#else
-	  if (!dsp16xx_ucmphi2_libcall)
-	    dsp16xx_ucmphi2_libcall = gen_rtx (SYMBOL_REF, Pmode, UCMPHI2_LIBCALL);
-	  emit_library_call (dsp16xx_ucmphi2_libcall, 1, HImode, 2,
-			     x, HImode, y, HImode);
-	  emit_insn (gen_tsthi_1 (copy_to_reg(hard_libcall_value (HImode))));
-#endif
-	}
-      else
-	emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx,
-			    gen_rtx (COMPARE, VOIDmode, force_reg(HImode, x), 
-				     force_reg(HImode,y))));
-    }
-  else
-    fatal ("Invalid mode for integer comparison in gen_compare_reg");
-
-  return cc0_rtx;
-}
-
-char *
-output_block_move (operands)
-     rtx operands[];
-{
-  int loop_count = INTVAL(operands[2]);
-  rtx xoperands[4];
-
-  fprintf (asm_out_file, "\tdo %d {\n", loop_count);
-  xoperands[0] = operands[4];
-  xoperands[1] = operands[1];
-  output_asm_insn ("%0=*%1++", xoperands);
-
-  xoperands[0] = operands[0];
-  xoperands[1] = operands[4];
-  output_asm_insn ("*%0++=%1", xoperands);
-
-  fprintf (asm_out_file, "\t}\n");
-  return "";
-}
diff --git a/gcc/config/dsp16xx/dsp16xx.h b/gcc/config/dsp16xx/dsp16xx.h
deleted file mode 100755
index f71ed37..0000000
--- a/gcc/config/dsp16xx/dsp16xx.h
+++ /dev/null
@@ -1,1972 +0,0 @@
-/* Definitions of target machine for GNU compiler.  AT&T DSP1600.
-   Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Michael Collison (collison@world.std.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-extern char *low_reg_names[];
-extern char *text_seg_name;
-extern char *rsect_text;
-extern char *data_seg_name;
-extern char *rsect_data;
-extern char *bss_seg_name;
-extern char *rsect_bss;
-extern char *const_seg_name;
-extern char *rsect_const;
-extern char *chip_name;
-extern char *save_chip_name;
-extern struct rtx_def *dsp16xx_compare_op0, *dsp16xx_compare_op1;
-extern struct rtx_def *(*dsp16xx_compare_gen)();
-extern struct rtx_def *gen_compare_reg();
-extern struct rtx_def *dsp16xx_addhf3_libcall;
-extern struct rtx_def *dsp16xx_subhf3_libcall;
-extern struct rtx_def *dsp16xx_mulhf3_libcall;
-extern struct rtx_def *dsp16xx_divhf3_libcall;
-extern struct rtx_def *dsp16xx_cmphf3_libcall;
-extern struct rtx_def *dsp16xx_fixhfhi2_libcall;
-extern struct rtx_def *dsp16xx_floathihf2_libcall;
-extern struct rtx_def *dsp16xx_neghf2_libcall;
-extern struct rtx_def *dsp16xx_umulhi3_libcall;
-extern struct rtx_def *dsp16xx_mulhi3_libcall;
-extern struct rtx_def *dsp16xx_udivqi3_libcall;
-extern struct rtx_def *dsp16xx_udivhi3_libcall;
-extern struct rtx_def *dsp16xx_divqi3_libcall;
-extern struct rtx_def *dsp16xx_divhi3_libcall;
-extern struct rtx_def *dsp16xx_modqi3_libcall;
-extern struct rtx_def *dsp16xx_modhi3_libcall;
-extern struct rtx_def *dsp16xx_umodqi3_libcall;
-extern struct rtx_def *dsp16xx_umodhi3_libcall;
-
-extern struct rtx_def *dsp16xx_ashrhi3_libcall;
-extern struct rtx_def *dsp16xx_ashlhi3_libcall;
-extern struct rtx_def *dsp16xx_lshrhi3_libcall;
-
-
-extern int hard_regno_mode_ok ();
-extern enum reg_class dsp16xx_reg_class_from_letter ();
-extern enum reg_class dsp16xx_limit_reload_class ();
-extern int hard_regno_nregs ();
-extern int regno_reg_class ();
-extern int move_operand ();
-extern int symbolic_address_p ();
-extern int Y_address ();
-extern int call_address_operand ();
-extern void notice_update_cc();
-extern void function_prologue ();
-extern void function_epilogue ();
-extern int  dsp1600_comparison_reverse ();
-extern void double_reg_from_memory ();
-extern void double_reg_to_memory ();
-extern void bss_section ();
-extern struct rtx_def *dsp16xx_function_arg ();
-extern void dsp16xx_function_arg_advance ();
-extern enum rtx_code next_cc_user_code ();
-extern int next_cc_user_unsigned ();
-extern struct rtx_def *gen_tst_reg ();
-extern char *output_block_move();
-
-/* RUN-TIME TARGET SPECIFICATION */
-#define DSP16XX   1
-
-/* Name of the AT&T assembler */
-
-#define ASM_PROG "as1600"
-
-/* Name of the AT&T linker */
-
-#define LD_PROG "ld1600"
-
-/* Define which switches take word arguments */
-#define WORD_SWITCH_TAKES_ARG(STR)              \
-  (!strcmp (STR, "ifile") ? 1 :                 \
-   0)
-
-#ifdef  CC1_SPEC
-#undef  CC1_SPEC
-#endif
-#define CC1_SPEC       ""
-
-/* Define this as a spec to call the AT&T assembler */
-
-#define CROSS_ASM_SPEC   "%{!S:as1600 %a %i\n }"
-
-/* Define this as a spec to call the AT&T linker */
-
-#define CROSS_LINK_SPEC  "%{!c:%{!M:%{!MM:%{!E:%{!S:ld1600 %l %X %{o*} %{m} \
-			%{r} %{s} %{t} %{u*} %{x}\
-			%{!A:%{!nostdlib:%{!nostartfiles:%S}}} %{static:}\
-			%{L*} %D %o %{!nostdlib:-le1600 %L -le1600}\
-			%{!A:%{!nostdlib:%{!nostartfiles:%E}}}\n }}}}}"
-
-/* Nothing complicated here, just link with libc.a under normal
-   circumstances */
-#define LIB_SPEC "-lc"
-
-/* Specify the startup file to link with. */
-#define STARTFILE_SPEC "%{mmap1:m1_crt0.o%s}  \
-%{mmap2:m2_crt0.o%s}                          \
-%{mmap3:m3_crt0.o%s}                          \
-%{mmap4:m4_crt0.o%s}                          \
-%{!mmap*: %{!ifile*: m4_crt0.o%s} %{ifile*:     \
-%eA -ifile option requires a -map option}}"
-
-/* Specify the end file to link with */
-
-#define ENDFILE_SPEC "%{mmap1:m1_crtn.o%s}  \
-%{mmap2:m2_crtn.o%s}                          \
-%{mmap3:m3_crtn.o%s}                          \
-%{mmap4:m4_crtn.o%s}                          \
-%{!mmap*: %{!ifile*: m4_crtn.o%s} %{ifile*:     \
-%eA -ifile option requires a -map option}}"
-
-
-/* Tell gcc where to look for the startfile */
-#define STANDARD_STARTFILE_PREFIX   "/d1600/lib"
-
-/* Tell gcc where to look for its executables */
-#define STANDARD_EXEC_PREFIX  "/d1600/bin"
-
-/* Command line options to the AT&T assembler */
-#define ASM_SPEC  "%{v:-V} %{g*:-g}"
-
-/* Command line options for the AT&T linker */
-#define LINK_SPEC "%{v:-V} %{minit:-i}  \
-%{!ifile*:%{mmap1:-ifile m1_deflt.if%s}         \
-          %{mmap2:-ifile m2_deflt.if%s}         \
-          %{mmap3:-ifile m3_deflt.if%s}         \
-          %{mmap4:-ifile m4_deflt.if%s}         \
-          %{!mmap*:-ifile m4_deflt.if%s}}       \
-%{ifile*} %{!r:-a}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-#ifdef __MSDOS__
-#define CPP_PREDEFINES "-Ddsp1600 -DDSP1600 -DMSDOS"
-#else
-#define CPP_PREDEFINES "-Ddsp1600 -DDSP1600 -Ddsp1610 -DDSP1610"
-#endif
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-#define MASK_REGPARM         0x00000001    /* Pass parameters in registers */
-#define MASK_NEAR_CALL       0x00000002    /* The call is on the same 4k page */
-#define MASK_NEAR_JUMP       0x00000004    /* The jump is on the same 4k page */
-#define MASK_BMU             0x00000008    /* Use the 'bmu' shift instructions */
-#define MASK_OPTIMIZE_MEMORY 0x00000010    /* Optimize to conserve memory */
-#define MASK_OPTIMIZE_SPEED  0x00000020    /* Optimize for speed */
-#define MASK_MAP1            0x00000040    /* Link with map1 */
-#define MASK_MAP2            0x00000080    /* Link with map2 */
-#define MASK_MAP3            0x00000100    /* Link with map3 */
-#define MASK_MAP4            0x00000200    /* Link with map4 */
-#define MASK_YBASE_HIGH      0x00000400    /* The ybase register window starts high */
-#define MASK_INIT	     0x00000800    /* Have the linker generate tables to
-					      initialize data at startup */
-#define MASK_INLINE_MULT     0x00001000    /* Inline 32 bit multiplies */
-#define MASK_RESERVE_YBASE   0x00002000    /* Reserved the ybase registers */
-
-/* Compile passing first two args in regs 0 and 1.
-   This exists only to test compiler features that will
-   be needed for RISC chips.  It is not usable
-   and is not intended to be usable on this cpu.  */
-#define TARGET_REGPARM   (target_flags & MASK_REGPARM)
-
-/* The call is on the same 4k page, so instead of loading
-   the 'pt' register and branching, we can branch directly */
-
-#define TARGET_NEAR_CALL (target_flags & MASK_NEAR_CALL)
-
-/* The jump is on the same 4k page, so instead of loading
-   the 'pt' register and branching, we can branch directly */
-
-#define TARGET_NEAR_JUMP (target_flags & MASK_NEAR_JUMP)
-
-/* Generate shift instructions to use the 1610 Bit Manipulation
-   Unit. */
-#define TARGET_BMU (target_flags & MASK_BMU)
-
-/* Optimize to conserve memory */
-#define TARGET_OPTIMIZE_MEMORY (target_flags & MASK_OPTIMIZE_MEMORY)
-
-/* Optimize for maximum speed */
-#define TARGET_OPTIMIZE_SPEED   (target_flags & MASK_OPTIMIZE_SPEED)
-
-#define TARGET_YBASE_HIGH (target_flags & MASK_YBASE_HIGH)
-
-/* Direct the linker to output extra info for initialized data */
-#define TARGET_MASK_INIT (target_flags & MASK_INIT)
-
-#define TARGET_INLINE_MULT (target_flags & MASK_INLINE_MULT)
-
-/* Reserve the ybase registers *(0) - *(31) */
-#define TARGET_RESERVE_YBASE (target_flags & MASK_RESERVE_YBASE)
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-
-#define TARGET_SWITCHES                        \
-  {				               \
-    { "regparm",       MASK_REGPARM},	       \
-    { "no-regparm",   -MASK_REGPARM},	       \
-    { "no-near-call", -MASK_NEAR_CALL},        \
-    { "near-jump",     MASK_NEAR_JUMP},        \
-    { "no-near-jump", -MASK_NEAR_JUMP},        \
-    { "bmu",           MASK_BMU},              \
-    { "no-bmu",       -MASK_BMU},              \
-    { "Om",            MASK_OPTIMIZE_MEMORY},  \
-    { "Os",            MASK_OPTIMIZE_SPEED},   \
-    { "map1",          MASK_MAP1},             \
-    { "map2",          MASK_MAP2},             \
-    { "map3",          MASK_MAP3},             \
-    { "map4",          MASK_MAP4},             \
-    { "ybase-high",    MASK_YBASE_HIGH},       \
-    { "init",          MASK_INIT},             \
-    { "inline-mult",   MASK_INLINE_MULT},      \
-    { "reserve-ybase", MASK_RESERVE_YBASE},    \
-    { "",              TARGET_DEFAULT}         \
-  }
-
-/* Default target_flags if no switches are specified */
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT  MASK_OPTIMIZE_MEMORY|MASK_REGPARM|MASK_YBASE_HIGH
-#endif
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an
-   initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   fixed part of the option name, and the address of a variable. 
-   The variable, type `char *', is set to the variable part of the
-   given option if the fixed part matches.  The actual option name
-   is made by appending `-m' to the specified name.
-
-   Here is an example which defines `-mshort-data-NUMBER'.  If the
-   given option is `-mshort-data-512', the variable `m88k_short_data'
-   will be set to the string `"512"'.
-
-	extern char *m88k_short_data;
-	#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } }  */
-
-#define TARGET_OPTIONS						\
-{								\
-  { "text=",	&text_seg_name	},				\
-  { "data=",	&data_seg_name	},				\
-  { "bss=",	&bss_seg_name	},				\
-  { "const=",   &const_seg_name },                              \
-  { "chip=",    &chip_name      }                               \
-}
-
-/* Sometimes certain combinations of command options do not make sense
-   on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-  
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-
-#define OVERRIDE_OPTIONS override_options ()
-
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)		\
-do							\
-  {							\
-    flag_gnu_linker             = FALSE;		\
-							\
-    if (SIZE)						\
-      {							\
-	flag_strength_reduce    = FALSE;		\
-	flag_inline_functions   = FALSE;		\
-      }							\
-  }							\
-while (0)
-
-/* STORAGE LAYOUT */
-
-/* Define if you don't want extended real, but do want to use the
-   software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion. */
-#define REAL_ARITHMETIC
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
- */
-#define BITS_BIG_ENDIAN  1
-
-/* Define this if most significant byte of a word is the lowest numbered.
-   We define big-endian, but since the 1600 series cannot address bytes
-   it does not matter. */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is numbered.
-   For the 1600 we can decide arbitrarily since there are no machine instructions for them. */
-#define WORDS_BIG_ENDIAN 1
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 16
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 16
-
-/* Maximum number of bits in a word. */
-#define MAX_BITS_PER_WORD 16
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 1
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 16
-
-/* Allocation boundary (in *bits*) for storing pointers in memory.  */
-#define POINTER_BOUNDARY 16
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 16
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 16
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 16
-
-/* Biggest alignment that any data type can require on this machine, in bits.  */
-#define BIGGEST_ALIGNMENT 16
-
-/* Biggest alignment that any structure field can require on this machine, in bits */
-#define BIGGEST_FIELD_ALIGNMENT 16
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* Number of bits which any structure or union's size must be a multiple of. Each structure
-   or union's size is rounded up to a multiple of this */
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Define this if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT  1
-
-/* An integer expression for the size in bits of the largest integer machine mode that
-   should actually be used. All integer machine modes of this size or smaller can be
-   used for structures and unions with the appropriate sizes. */
-#define MAX_FIXED_MODE_SIZE 32
-
-/* LAYOUT OF SOURCE LANGUAGE DATA TYPES */
-
-#define CHAR_TYPE_SIZE         16
-#define SHORT_TYPE_SIZE        16
-#define INT_TYPE_SIZE          16
-#define LONG_TYPE_SIZE         32
-#define LONG_LONG_TYPE_SIZE    32
-#define FLOAT_TYPE_SIZE        32
-#define DOUBLE_TYPE_SIZE       32
-#define LONG_DOUBLE_TYPE_SIZE  32
-
-/* An expression whose value is 1 or 0, according to whether the type char should be
-   signed or unsigned by default. */
-
-#define DEFAULT_SIGNED_CHAR 1
-
-/* A C expression to determine whether to give an enum type only as many bytes
-   as it takes to represent the range of possible values of that type. A nonzero
-   value means to do that; a zero value means all enum types should be allocated
-   like int. */
-
-#define DEFAULT_SHORT_ENUMS 0
-
-/* A C expression for a string describing the name of the data type to use for
-   size values. */
-
-#define SIZE_TYPE    "long unsigned int"
-
-/* A C expression for a string describing the name of the datat type to use for the
-   result of subtracting two pointers */
-
-#define PTRDIFF_TYPE "long int"
-
-#define TARGET_BELL     '\a'
-#define TARGET_BS       '\b'
-#define TARGET_TAB      '\t'
-#define TARGET_NEWLINE  '\n'
-#define TARGET_VT       '\v'
-#define TARGET_FF       '\f'
-#define TARGET_CR       '\r'
-
-
-/* REGISTER USAGE.  */
-
-#define ALL_16_BIT_REGISTERS  1
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to FIRST_PSEUDO_REGISTER-1 */
-
-#define FIRST_PSEUDO_REGISTER (REG_YBASE31 + 1)
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   The registers are laid out as follows:
-
-   {a0,a0l,a1,a1l,x,y,yl,p,pl} - Data Arithmetic Unit
-   {r0,r1,r2,r3,j,k,ybase} - Y Space Address Arithmetic Unit
-   {pt} - X Space Address Arithmetic Unit
-   {ar0,ar1,ar2,ar3} - Bit Manipulation UNit
-   {pr} - Return Address Register
-
-   We reserve r2 for the Stack Pointer.
-   We specify r3 for the Frame Pointer but allow the compiler
-   to omit it when possible since we have so few pointer registers. */
-
-#define REG_A0     0
-#define REG_A0L    1
-#define REG_A1     2
-#define REG_A1L    3 
-#define REG_X      4
-#define REG_Y      5
-#define REG_YL     6
-#define REG_PROD   7
-#define REG_PRODL  8
-#define REG_R0     9
-#define REG_R1     10
-#define REG_R2     11
-#define REG_R3     12
-#define REG_J      13
-#define REG_K      14
-#define REG_YBASE  15
-#define REG_PT     16
-#define REG_AR0    17
-#define REG_AR1    18
-#define REG_AR2    19
-#define REG_AR3    20
-#define REG_C0     21
-#define REG_C1     22
-#define REG_C2     23
-#define REG_PR     24
-#define REG_RB     25
-#define REG_YBASE0 26
-#define REG_YBASE1 27
-#define REG_YBASE2 28
-#define REG_YBASE3 29
-#define REG_YBASE4 30
-#define REG_YBASE5 31
-#define REG_YBASE6 32
-#define REG_YBASE7 33
-#define REG_YBASE8 34
-#define REG_YBASE9 35
-#define REG_YBASE10 36
-#define REG_YBASE11 37
-#define REG_YBASE12 38
-#define REG_YBASE13 39
-#define REG_YBASE14 40
-#define REG_YBASE15 41
-#define REG_YBASE16 42
-#define REG_YBASE17 43
-#define REG_YBASE18 44
-#define REG_YBASE19 45
-#define REG_YBASE20 46
-#define REG_YBASE21 47
-#define REG_YBASE22 48
-#define REG_YBASE23 49
-#define REG_YBASE24 50
-#define REG_YBASE25 51
-#define REG_YBASE26 52
-#define REG_YBASE27 53
-#define REG_YBASE28 54
-#define REG_YBASE29 55
-#define REG_YBASE30 56
-#define REG_YBASE31 57
-
-/* Do we have a accumulator register? */
-#define IS_ACCUM_REG(REGNO) ((REGNO) >= REG_A0 && (REGNO) <= REG_A1L)
-#define IS_ACCUM_LOW_REG(REGNO) ((REGNO) == REG_A0L || (REGNO) == REG_A1L)
-
-/* Do we have a virtual ybase register */
-#define IS_YBASE_REGISTER_WINDOW(REGNO) ((REGNO) >= REG_YBASE0 && (REGNO) <= REG_YBASE31)
-
-#define IS_ADDRESS_REGISTER(REGNO) ((REGNO) >= REG_R0 && (REGNO) <= REG_R3)
-
-#define FIXED_REGISTERS     \
-{0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 1, 0, 0, 1,       \
- 1,                         \
- 0, 0, 0, 0,                \
- 1, 1, 1,                   \
- 0, 0,                      \
- 0, 0, 0, 0, 0, 0, 0, 0,    \
- 0, 0, 0, 0, 0, 0, 0, 0,    \
- 0, 0, 0, 0, 0, 0, 0, 0,    \
- 0, 0, 0, 0, 0, 0, 0, 0}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   On the 1610 'a0' holds return values from functions. 'r0' holds
-   structure-value addresses.
-
-   In addition we don't save either j, k, ybase or any of the
-   bit manipulation registers.  */
-
-
-#define CALL_USED_REGISTERS   \
-{1, 1, 1, 1, 0, 1, 1, 1, 1,   \
- 1, 0, 0, 1, 1, 1, 1,         \
- 1,                           \
- 0, 0, 1, 1,                  \
- 1, 1, 1,                     \
- 0, 1,                        \
- 0, 0, 0, 0, 0, 0, 0, 0,      \
- 0, 0, 0, 0, 0, 0, 0, 0,      \
- 0, 0, 0, 0, 0, 0, 0, 0,      \
- 0, 0, 0, 0, 0, 0, 0, 0}
-
-/* List the order in which to allocate registers.  Each register must be
-   listed once, even those in FIXED_REGISTERS.
-
-   We allocate in the following order:
- */
-
-#define REG_ALLOC_ORDER					\
-{ REG_R0, REG_R1, REG_R2, REG_PROD, REG_Y, REG_X,       \
-  REG_PRODL, REG_YL, REG_AR0, REG_AR1,                  \
-  REG_RB, REG_A0, REG_A1, REG_A0L,                      \
-  REG_A1L, REG_AR2, REG_AR3,                            \
-  REG_YBASE, REG_J, REG_K, REG_PR, REG_PT, REG_C0,      \
-  REG_C1, REG_C2, REG_R3,				\
-  REG_YBASE0, REG_YBASE1, REG_YBASE2, REG_YBASE3,       \
-  REG_YBASE4, REG_YBASE5, REG_YBASE6, REG_YBASE7,       \
-  REG_YBASE8, REG_YBASE9, REG_YBASE10, REG_YBASE11,     \
-  REG_YBASE12, REG_YBASE13, REG_YBASE14, REG_YBASE15,   \
-  REG_YBASE16, REG_YBASE17, REG_YBASE18, REG_YBASE19,   \
-  REG_YBASE20, REG_YBASE21, REG_YBASE22, REG_YBASE23,   \
-  REG_YBASE24, REG_YBASE25, REG_YBASE26, REG_YBASE27,   \
-  REG_YBASE28, REG_YBASE29, REG_YBASE30, REG_YBASE31 }
-
-/* Zero or more C statements that may conditionally modify two
-   variables `fixed_regs' and `call_used_regs' (both of type `char
-   []') after they have been initialized from the two preceding
-   macros.
-
-   This is necessary in case the fixed or call-clobbered registers
-   depend on target flags.
-
-   You need not define this macro if it has no work to do.
-
-   If the usage of an entire class of registers depends on the target
-   flags, you may indicate this to GCC by using this macro to modify
-   `fixed_regs' and `call_used_regs' to 1 for each of the registers in
-   the classes which should not be used by GCC.  Also define the macro
-   `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
-   letter for a class that shouldn't be used.
-
-   (However, if this class is not included in `GENERAL_REGS' and all
-   of the insn patterns whose constraints permit this class are
-   controlled by target switches, then GCC will automatically avoid
-   using these registers when the target switches are opposed to
-   them.)  If the user tells us there is no BMU, we can't use
-   ar0-ar3 for register allocation */
-
-#define CONDITIONAL_REGISTER_USAGE					\
-do									\
-  {									\
-    if (!TARGET_BMU)						        \
-      {									\
-	int regno;							\
-									\
-	for (regno = REG_AR0; regno <= REG_AR3; regno++)	        \
-	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
-      }									\
-    if (TARGET_RESERVE_YBASE)						\
-      {									\
-	int regno;							\
-									\
-	for (regno = REG_YBASE0; regno <= REG_YBASE31; regno++)	        \
-	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
-      }									\
-  }									\
-while (0)
-
-/* Determine which register classes are very likely used by spill registers.
-   local-alloc.c won't allocate pseudos that have these classes as their
-   preferred class unless they are "preferred or nothing".  */
-
-#define CLASS_LIKELY_SPILLED_P(CLASS) \
- ((CLASS) != ALL_REGS && (CLASS) != YBASE_VIRT_REGS)
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers. */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)                                 \
-  (GET_MODE_SIZE(MODE))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok(REGNO, MODE)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2)		     \
-  (((MODE1) == (MODE2)) ||                           \
-   (GET_MODE_CLASS((MODE1)) == MODE_FLOAT)           \
-    == (GET_MODE_CLASS((MODE2)) == MODE_FLOAT))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* DSP1600 pc isn't overloaded on a register.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  
-   This is r3 in our case */
-#define STACK_POINTER_REGNUM  REG_R3
-
-/* Base register for access to local variables of the function.
-   This is r2 in our case   */
-#define FRAME_POINTER_REGNUM  REG_R2
-
-/* We can debug without the frame pointer */
-#define CAN_DEBUG_WITHOUT_FP 1
-
-/* The 1610 saves the return address in this register */
-#define RETURN_ADDRESS_REGNUM REG_PR
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
-
-/* Register in which static-chain is passed to a function.  */
-
-#define STATIC_CHAIN_REGNUM 4
-
-/* Register in which address to store a structure value
-   is passed to a function.  This is 'r0' in our case */
-#define STRUCT_VALUE_REGNUM   REG_R0
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-
-enum reg_class 
-{ 
-    NO_REGS, 
-    A0H_REG,
-    A0L_REG,
-    A0_REG,
-    A1H_REG,
-    ACCUM_HIGH_REGS,
-    A1L_REG,
-    ACCUM_LOW_REGS, 
-    A1_REG,
-    ACCUM_REGS, 
-    X_REG, 
-    X_OR_ACCUM_LOW_REGS,
-    X_OR_ACCUM_REGS,
-    YH_REG,
-    YH_OR_ACCUM_HIGH_REGS,
-    X_OR_YH_REGS,
-    YL_REG,
-    YL_OR_ACCUM_LOW_REGS,
-    X_OR_YL_REGS,
-    X_OR_Y_REGS,
-    Y_REG,
-    ACCUM_OR_Y_REGS,
-    PH_REG,
-    X_OR_PH_REGS, 
-    PL_REG, 
-    PL_OR_ACCUM_LOW_REGS,
-    X_OR_PL_REGS,
-    YL_OR_PL_OR_ACCUM_LOW_REGS,
-    P_REG,
-    ACCUM_OR_P_REGS,
-    YL_OR_P_REGS,
-    ACCUM_LOW_OR_YL_OR_P_REGS,
-    Y_OR_P_REGS,
-    ACCUM_Y_OR_P_REGS, 
-    NO_FRAME_Y_ADDR_REGS,
-    Y_ADDR_REGS, 
-    ACCUM_LOW_OR_Y_ADDR_REGS,
-    ACCUM_OR_Y_ADDR_REGS,
-    X_OR_Y_ADDR_REGS,
-    Y_OR_Y_ADDR_REGS,
-    P_OR_Y_ADDR_REGS,
-    NON_HIGH_YBASE_ELIGIBLE_REGS,
-    YBASE_ELIGIBLE_REGS,
-    J_REG,
-    J_OR_DAU_16_BIT_REGS,
-    BMU_REGS, 
-    NOHIGH_NON_ADDR_REGS,
-    NON_ADDR_REGS,
-    SLOW_MEM_LOAD_REGS,
-    NOHIGH_NON_YBASE_REGS,
-    NO_ACCUM_NON_YBASE_REGS,
-    NON_YBASE_REGS,
-    YBASE_VIRT_REGS,
-    ACCUM_LOW_OR_YBASE_REGS,
-    ACCUM_OR_YBASE_REGS,
-    X_OR_YBASE_REGS,
-    Y_OR_YBASE_REGS,
-    ACCUM_LOW_YL_PL_OR_YBASE_REGS,
-    P_OR_YBASE_REGS,
-    ACCUM_Y_P_OR_YBASE_REGS,
-    Y_ADDR_OR_YBASE_REGS,
-    YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS,
-    YBASE_OR_YBASE_ELIGIBLE_REGS,
-    NO_HIGH_ALL_REGS,
-    ALL_REGS, 
-    LIM_REG_CLASSES 
-};
-
-/* GENERAL_REGS must be the name of a register class */
-#define GENERAL_REGS ALL_REGS
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES        \
-{                              \
-    "NO_REGS",                 \
-    "A0H_REG",                 \
-    "A0L_REG",                 \
-    "A0_REG",                  \
-    "A1H_REG",                 \
-    "ACCUM_HIGH_REGS",         \
-    "A1L_REG",                 \
-    "ACCUM_LOW_REGS",          \
-    "A1_REG",                  \
-    "ACCUM_REGS",              \
-    "X_REG",                   \
-    "X_OR_ACCUM_LOW_REGS",     \
-    "X_OR_ACCUM_REGS",         \
-    "YH_REG",                  \
-    "YH_OR_ACCUM_HIGH_REGS",   \
-    "X_OR_YH_REGS",            \
-    "YL_REG",                  \
-    "YL_OR_ACCUM_LOW_REGS",    \
-    "X_OR_YL_REGS",            \
-    "X_OR_Y_REGS",             \
-    "Y_REG",                   \
-    "ACCUM_OR_Y_REGS",         \
-    "PH_REG",                  \
-    "X_OR_PH_REGS",            \
-    "PL_REG",                  \
-    "PL_OR_ACCUM_LOW_REGS",    \
-    "X_OR_PL_REGS",            \
-    "PL_OR_YL_OR_ACCUM_LOW_REGS", \
-    "P_REG",                   \
-    "ACCUM_OR_P_REGS",         \
-    "YL_OR_P_REGS",            \
-    "ACCUM_LOW_OR_YL_OR_P_REGS", \
-    "Y_OR_P_REGS",             \
-    "ACCUM_Y_OR_P_REGS",       \
-    "NO_FRAME_Y_ADDR_REGS",      \
-    "Y_ADDR_REGS",               \
-    "ACCUM_LOW_OR_Y_ADDR_REGS",  \
-    "ACCUM_OR_Y_ADDR_REGS",    \
-    "X_OR_Y_ADDR_REGS",        \
-    "Y_OR_Y_ADDR_REGS",        \
-    "P_OR_Y_ADDR_REGS",        \
-    "NON_HIGH_YBASE_ELIGIBLE_REGS", \
-    "YBASE_ELIGIBLE_REGS",     \
-    "J_REG",                   \
-    "J_OR_DAU_16_BIT_REGS",    \
-    "BMU_REGS",                \
-    "NOHIGH_NON_ADDR_REGS",    \
-    "NON_ADDR_REGS",           \
-    "SLOW_MEM_LOAD_REGS",      \
-    "NOHIGH_NON_YBASE_REGS",   \
-    "NO_ACCUM_NON_YBASE_REGS", \
-    "NON_YBASE_REGS",          \
-    "YBASE_VIRT_REGS",         \
-    "ACCUM_LOW_OR_YBASE_REGS", \
-    "ACCUM_OR_YBASE_REGS",     \
-    "X_OR_YBASE_REGS",         \
-    "Y_OR_YBASE_REGS",         \
-    "ACCUM_LOW_YL_PL_OR_YBASE_REGS", \
-    "P_OR_YBASE_REGS",         \
-    "ACCUM_Y_P_OR_YBASE_REGS", \
-    "Y_ADDR_OR_YBASE_REGS",    \
-    "YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS", \
-    "YBASE_OR_YBASE_ELIGIBLE_REGS", \
-    "NO_HIGH_ALL_REGS",        \
-    "ALL_REGS"                 \
-}
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS   \
-{                            \
-    {0x00000000,  0x00000000},      /* no reg */                             \
-    {0x00000001,  0x00000000},      /* a0h */                                \
-    {0x00000002,  0x00000000},      /* a0l */                                \
-    {0x00000003,  0x00000000},      /* a0h:a0l */                            \
-    {0x00000004,  0x00000000},      /* a1h */                                \
-    {0x00000005,  0x00000000},      /* accum high */                         \
-    {0x00000008,  0x00000000},      /* a1l */                                \
-    {0x0000000A,  0x00000000},      /* accum low */                          \
-    {0x0000000c,  0x00000000},      /* a1h:a1l */                            \
-    {0x0000000f,  0x00000000},      /* accum regs */                         \
-    {0x00000010,  0x00000000},      /* x reg */                              \
-    {0x0000001A,  0x00000000},      /* x & accum_low_regs */                 \
-    {0x0000001f,  0x00000000},      /* x & accum regs */                     \
-    {0x00000020,  0x00000000},      /* y high */                             \
-    {0x00000025,  0x00000000},      /* yh, accum high */                     \
-    {0x00000030,  0x00000000},      /* x & yh */                             \
-    {0x00000040,  0x00000000},      /* y low */                              \
-    {0x0000004A,  0x00000000},      /* y low, accum_low */                   \
-    {0x00000050,  0x00000000},      /* x & yl */                             \
-    {0x00000060,  0x00000000},      /* yl:yh */                              \
-    {0x00000070,  0x00000000},      /* x, yh,a nd yl */                      \
-    {0x0000006F,  0x00000000},      /* accum, y */                           \
-    {0x00000080,  0x00000000},      /* p high */                             \
-    {0x00000090,  0x00000000},      /* x & ph */                             \
-    {0x00000100,  0x00000000},      /* p low */                              \
-    {0x0000010A,  0x00000000},      /* p_low and accum_low */                \
-    {0x00000110,  0x00000000},      /* x & pl */                             \
-    {0x0000014A,  0x00000000},      /* pl,yl,a1l,a0l */                      \
-    {0x00000180,  0x00000000},      /* pl:ph */                              \
-    {0x0000018F,  0x00000000},      /* accum, p */                           \
-    {0x000001C0,  0x00000000},      /* pl:ph and yl */                       \
-    {0x000001CA,  0x00000000},      /* pl:ph, yl, a0l, a1l */                \
-    {0x000001E0,  0x00000000},      /* y or p */                             \
-    {0x000001EF,  0x00000000},      /* accum, y or p */                      \
-    {0x00000E00,  0x00000000},      /* r0-r2 */                              \
-    {0x00001E00,  0x00000000},      /* r0-r3 */                              \
-    {0x00001E0A,  0x00000000},      /* r0-r3, accum_low */                   \
-    {0x00001E0F,  0x00000000},      /* accum,r0-r3 */                        \
-    {0x00001E10,  0x00000000},      /* x,r0-r3 */                            \
-    {0x00001E60,  0x00000000},      /* y,r0-r3 */                            \
-    {0x00001F80,  0x00000000},      /* p,r0-r3 */                            \
-    {0x00001FDA,  0x00000000},      /* ph:pl, r0-r3, x,a0l,a1l */            \
-    {0x00001fff,  0x00000000},      /* accum,x,y,p,r0-r3 */                  \
-    {0x00002000,  0x00000000},      /* j */                                  \
-    {0x00002025,  0x00000000},      /* j, yh, a1h, a0h */                    \
-    {0x001E0000,  0x00000000},      /* ar0-ar3 */                            \
-    {0x03FFE1DA,  0x00000000},      /* non_addr except yh,a0h,a1h */         \
-    {0x03FFE1FF,  0x00000000},      /* non_addr regs */                      \
-    {0x03FFFF8F,  0x00000000},      /* non ybase except yh, yl, and x */     \
-    {0x03FFFFDA,  0x00000000},      /* non ybase regs except yh,a0h,a1h */   \
-    {0x03FFFFF0,  0x00000000},      /* non ybase except a0,a0l,a1,a1l */     \
-    {0x03FFFFFF,  0x00000000},      /* non ybase regs */                     \
-    {0xFC000000,  0x03FFFFFF},      /* virt ybase regs */                    \
-    {0xFC00000A,  0x03FFFFFF},      /* accum_low, virt ybase regs */         \
-    {0xFC00000F,  0x03FFFFFF},      /* accum, virt ybase regs */             \
-    {0xFC000010,  0x03FFFFFF},      /* x,virt ybase regs */                  \
-    {0xFC000060,  0x03FFFFFF},      /* y,virt ybase regs */                  \
-    {0xFC00014A,  0x03FFFFFF},      /* accum_low, yl, pl, ybase */           \
-    {0xFC000180,  0x03FFFFFF},      /* p,virt ybase regs */                  \
-    {0xFC0001EF,  0x03FFFFFF},      /* accum,y,p,ybase regs */               \
-    {0xFC001E00,  0x03FFFFFF},      /* r0-r3, ybase regs */                  \
-    {0xFC001FDA,  0x03FFFFFF},      /* r0-r3, pl:ph,yl,x,a1l,a0l */          \
-    {0xFC001FFF,  0x03FFFFFF},      /* virt ybase, ybase eligible regs */    \
-    {0xFCFFFFDA,  0x03FFFFFF},      /* all regs except yh,a0h,a1h */         \
-    {0xFFFFFFFF,  0x03FFFFFF}       /* all regs */                           \
-}
-
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) regno_reg_class(REGNO)
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS NO_REGS
-#define BASE_REG_CLASS  Y_ADDR_REGS
-
-/* Get reg_class from a letter such as appears in the machine description. */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  dsp16xx_reg_class_from_letter(C)
-
-#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X)  \
-   secondary_reload_class(CLASS, MODE, X)
-
-/* When defined, the compiler allows registers explicitly used in the
-   rtl to be used as spill registers but prevents the compiler from
-   extending the lifetime of these registers. */
-
-#define SMALL_REGISTER_CLASSES 1
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-/* A C expression which is nonzero if register REGNO is suitable for use
-   as a base register in operand addresses. It may be either a suitable
-   hard register or a pseudo register that has been allocated such a
-   hard register. 
-
-  On the 1610 the Y address pointers can be used as a base registers */
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-(((REGNO) >= REG_R0 && (REGNO) < REG_R3 + 1) || ((unsigned) reg_renumber[REGNO] >= REG_R0  \
-                                   && (unsigned) reg_renumber[REGNO] < REG_R3 + 1))
-
-#define REGNO_OK_FOR_YBASE_P(REGNO) \
-  (((REGNO) == REG_YBASE) || ((unsigned) reg_renumber[REGNO] == REG_YBASE))
-
-#define REGNO_OK_FOR_INDEX_P(REGNO)  0
-
-#ifdef ALL_16_BIT_REGISTERS
-#define IS_32_BIT_REG(REGNO)  0
-#else
-#define IS_32_BIT_REG(REGNO)     \
-  ((REGNO) == REG_A0 || (REGNO) == REG_A1 || (REGNO) == REG_Y || (REGNO) == REG_PROD)
-#endif
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.
-   Also, we must ensure that a PLUS is reloaded either
-   into an accumulator or an address register.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)	 preferred_reload_class (X, CLASS)
-
-/*   A C expression that places additional restrictions on the register
-     class to use when it is necessary to be able to hold a value of
-     mode MODE in a reload register for which class CLASS would
-     ordinarily be used.
-
-     Unlike `PREFERRED_RELOAD_CLASS', this macro should be used when
-     there are certain modes that simply can't go in certain reload
-     classes.
-
-     The value is a register class; perhaps CLASS, or perhaps another,
-     smaller class.
-
-     Don't define this macro unless the target machine has limitations
-     which require the macro to do something nontrivial. */
-
-#if 0
-#define LIMIT_RELOAD_CLASS(MODE, CLASS) dsp16xx_limit_reload_class (MODE, CLASS)
-#endif
-
-/* A C expression for the maximum number of consecutive registers of class CLASS
-   needed to hold a value of mode MODE */
-#define CLASS_MAX_NREGS(CLASS, MODE)                                \
-    class_max_nregs(CLASS, MODE)
-
-/* The letters 'I' through 'P' in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   For the 16xx, the following constraints are used:
-   'I' requires a non-negative 16-bit value.
-   'J' requires a non-negative 9-bit value
-   'K' requires a constant 0 operand.
-   'L' requires 16-bit value
-   'M' 32-bit value -- low 16-bits zero
- */
-
-#define SMALL_INT(X) (SMALL_INTVAL (INTVAL (X)))
-#define SMALL_INTVAL(I) ((unsigned) (I) < 0x10000)
-#define SHORT_IMMEDIATE(X)  (SHORT_INTVAL (INTVAL(X)))
-#define SHORT_INTVAL(I)     ((unsigned) (I) < 0x100)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)                           \
-   ((C) == 'I' ? (SMALL_INTVAL(VALUE))                            \
-    : (C) == 'J' ? (SHORT_INTVAL(VALUE))                          \
-    : (C) == 'K' ? ((VALUE) == 0)                                 \
-    : (C) == 'L' ? ! ((VALUE) & ~0x0000ffff)	                  \
-    : (C) == 'M' ? ! ((VALUE) & ~0xffff0000)	                  \
-    : (C) == 'N' ? ((VALUE) == -1 || (VALUE) == 1 ||              \
-                    (VALUE) == -2 || (VALUE) == 2)                \
-    : 0)
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)   1
-
-/* Optional extra constraints for this machine */
-#define EXTRA_CONSTRAINT(OP,C)                                    \
-  ((C) == 'R' ? symbolic_address_p (OP)                           \
-   : 0)
-
-/* DESCRIBING STACK LAYOUT AND CALLING CONVENTIONS */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-/* #define STACK_GROWS_DOWNWARD */
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-/* #define FRAME_GROWS_DOWNWARD */
-
-#define ARGS_GROW_DOWNWARD
-
-/* We use post decrement on the 1600 because there isn't
-   a pre-decrement addressing mode. This means that we
-   assume the stack pointer always points at the next
-   FREE location on the stack. */
-#define STACK_PUSH_CODE POST_INC
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET  0
-
-/* Offset from the stack pointer register to the first
-   location at which outgoing arguments are placed. */
-#define STACK_POINTER_OFFSET (0)
-
-struct dsp16xx_frame_info
-{
-  unsigned long total_size;	/* # bytes that the entire frame takes up */
-  unsigned long var_size;	/* # bytes that variables take up */
-  unsigned long args_size;	/* # bytes that outgoing arguments take up */
-  unsigned long extra_size;	/* # bytes of extra gunk */
-  unsigned int  reg_size;	/* # bytes needed to store regs */
-  long		fp_save_offset;	/* offset from vfp to store registers */
-  unsigned long sp_save_offset;	/* offset from new sp to store registers */
-  int		initialized;	/* != 0 if frame size already calculated */
-  int		num_regs;	/* number of registers saved */
-  int           function_makes_calls;  /* Does the function make calls */
-};
-
-extern struct dsp16xx_frame_info current_frame_info;
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by. */
-/* #define PUSH_ROUNDING(BYTES) ((BYTES)) */
-
-/* If defined, the maximum amount of space required for outgoing
-   arguments will be computed and placed into the variable
-   'current_function_outgoing_args_size'. No space will be pushed
-   onto the stack for each call; instead, the function prologue should
-   increase the stack frame size by this amount.
-
-   It is not proper to define both 'PUSH_ROUNDING' and
-   'ACCUMULATE_OUTGOING_ARGS'. */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Offset of first parameter from the argument pointer
-   register value. */
-
-#define FIRST_PARM_OFFSET(FNDECL)   (0)
-
-/* Value is 1 if returning from a function call automatically
-   pops the arguments described by the number-of-args field in the call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0. On the 1610 all function return their values
-   in a0 (i.e. the upper 16 bits). If the return value is 32-bits the
-   entire register is significant. */
-
-#define VALUE_REGNO(MODE)  (REG_Y)
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx_REG (TYPE_MODE (VALTYPE), VALUE_REGNO(TYPE_MODE(VALTYPE)))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-#define LIBCALL_VALUE(MODE)  gen_rtx_REG (MODE, VALUE_REGNO(MODE))
-
-/* 1 if N is a possible register number for a function value. */
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_Y)
-
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On the 1610 all args are pushed, except if -mregparm is specified
-   then the first two words of arguments are passed in a0, a1. */
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  dsp16xx_function_arg (CUM, MODE, TYPE, NAMED)
-
-/* Define the first register to be used for argument passing */
-#define FIRST_REG_FOR_FUNCTION_ARG REG_Y
-
-/* Define the profitability of saving registers around calls.
-   NOTE: For now we turn this off because of a bug in the
-   caller-saves code and also because i'm not sure it is helpful
-   on the 1610. */
-
-#define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
-
-/* This indicates that an argument is to be passed with an invisible reference
-   (i.e., a pointer to the object is passed).
-
-   On the dsp16xx, we do this if it must be passed on the stack.  */
-
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)	\
-  (MUST_PASS_IN_STACK (MODE, TYPE))
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)  (0)
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go. */
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0. */
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)  ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
-  dsp16xx_function_arg_advance (&CUM, MODE,TYPE, NAMED)
-
-/* 1 if N is a possible register number for function argument passing. */
-#define FUNCTION_ARG_REGNO_P(N)   \
-  ((N) == REG_Y || (N) == REG_YL || (N) == REG_PROD || (N) == REG_PRODL)
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used. */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)     function_prologue(FILE, SIZE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry. */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)        fatal("Profiling not implemented yet.")
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done. */
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  fatal("Profiling not implemented yet.")
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file. */
-#define BLOCK_PROFILER(FILE, BLOCKNO)	        fatal("Profiling not implemented yet.")
-
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK  (0)
-
-#define TRAMPOLINE_TEMPLATE(FILE) fatal ("Trampolines not yet implemented");
-
-/* Length in units of the trampoline for entering a nested function.
-   This is a dummy value  */
-
-#define TRAMPOLINE_SIZE 20
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function. */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-  fatal ("Trampolines not yet implemented");
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning. */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE)   function_epilogue(FILE, SIZE)
-
-/* A C expression which is nonzero if a function must have and use a
-   frame pointer. If its value is nonzero the functions will have a
-   frame pointer. */
-#define FRAME_POINTER_REQUIRED  (current_function_calls_alloca)
-
-/* A C statement to store in the variable 'DEPTH' the difference
-   between the frame pointer and the stack pointer values immediately
-   after the function prologue. */
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)                     \
-{  (DEPTH) = initial_frame_pointer_offset();	                \
-}
-
-/* IMPLICIT CALLS TO LIBRARY ROUTINES */
-
-#define ADDHF3_LIBCALL      "__Emulate_addhf3"
-#define SUBHF3_LIBCALL      "__Emulate_subhf3"
-#define MULHF3_LIBCALL      "__Emulate_mulhf3"
-#define DIVHF3_LIBCALL      "__Emulate_divhf3"
-#define CMPHF3_LIBCALL      "__Emulate_cmphf3"
-#define FIXHFHI2_LIBCALL    "__Emulate_fixhfhi2"
-#define FLOATHIHF2_LIBCALL  "__Emulate_floathihf2"
-#define NEGHF2_LIBCALL      "__Emulate_neghf2"
-
-#define UMULHI3_LIBCALL     "__Emulate_umulhi3"
-#define MULHI3_LIBCALL      "__Emulate_mulhi3"
-#define UDIVQI3_LIBCALL     "__Emulate_udivqi3"
-#define UDIVHI3_LIBCALL     "__Emulate_udivhi3"
-#define DIVQI3_LIBCALL      "__Emulate_divqi3"
-#define DIVHI3_LIBCALL      "__Emulate_divhi3"
-#define MODQI3_LIBCALL      "__Emulate_modqi3"
-#define MODHI3_LIBCALL      "__Emulate_modhi3"
-#define UMODQI3_LIBCALL     "__Emulate_umodqi3"
-#define UMODHI3_LIBCALL     "__Emulate_umodhi3"
-#define ASHRHI3_LIBCALL     "__Emulate_ashrhi3"
-#define LSHRHI3_LIBCALL     "__Emulate_lshrhi3"
-#define ASHLHI3_LIBCALL     "__Emulate_ashlhi3"
-#define LSHLHI3_LIBCALL     "__Emulate_lshlhi3"   /* NOT USED */
-
-/* Define this macro if calls to the ANSI C library functions memcpy and
-   memset should be generated instead of the BSD function bcopy & bzero. */
-#define TARGET_MEM_FUNCTIONS
-
-
-/* ADDRESSING MODES */
-
-/* The 1610 has post-increment and decrement, but no pre-modify */
-#define HAVE_POST_INCREMENT 1
-#define HAVE_POST_DECREMENT 1
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Recognize any constant value that is a valid address.  */
-#define CONSTANT_ADDRESS_P(X)  CONSTANT_P (X)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-#define MAX_REGS_PER_ADDRESS 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X)  0
-
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X)    \
-    ((REGNO (X) >= REG_R0 && REGNO (X) < REG_R3 + 1 )          \
-       || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
-
-/* Nonzero if X is the 'ybase' register */
-#define REG_OK_FOR_YBASE_P(X)   \
-  (REGNO(X) == REG_YBASE || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-/* Nonzero if X is the 'ybase' register */
-#define REG_OK_FOR_YBASE_P(X) REGNO_OK_FOR_YBASE_P (REGNO(X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   On the 1610, the actual legitimate addresses must be N (N must fit in
-   5 bits), *rn (register indirect), *rn++, or *rn-- */
-
-#define INT_FITS_5_BITS(I)    ((unsigned long) (I) < 0x20)
-#define INT_FITS_16_BITS(I)   ((unsigned long) (I) < 0x10000)
-#define YBASE_CONST_OFFSET(I)       ((I) >= -31 && (I) <= 0)
-#define YBASE_OFFSET(X)       (GET_CODE (X) == CONST_INT && YBASE_CONST_OFFSET (INTVAL(X)))
-
-#define FITS_16_BITS(X)       (GET_CODE (X) == CONST_INT && INT_FITS_16_BITS(INTVAL(X)))
-#define FITS_5_BITS(X)        (GET_CODE (X) == CONST_INT && INT_FITS_5_BITS(INTVAL(X)))
-#define ILLEGAL_HIMODE_ADDR(MODE, CONST)  ((MODE) == HImode && CONST == -31)
-
-#define INDIRECTABLE_ADDRESS_P(X)                            \
-    ((GET_CODE(X) == REG && REG_OK_FOR_BASE_P(X))            \
-  || ((GET_CODE(X) == POST_DEC || GET_CODE(X) == POST_INC)   \
-       && REG_P(XEXP(X,0)) && REG_OK_FOR_BASE_P(XEXP(X,0)))  \
-  || (GET_CODE(X) == CONST_INT && (unsigned long) (X) < 0x20))
-
-
-#define INDEXABLE_ADDRESS_P(X,MODE)                                 \
-   ((GET_CODE(X) == PLUS && GET_CODE (XEXP (X,0)) == REG &&         \
-     XEXP(X,0) == stack_pointer_rtx && YBASE_OFFSET(XEXP(X,1)) &&   \
-     !ILLEGAL_HIMODE_ADDR(MODE, INTVAL(XEXP(X,1)))) ||              \
-    (GET_CODE(X) == PLUS && GET_CODE (XEXP (X,1)) == REG &&         \
-     XEXP(X,1) == stack_pointer_rtx && YBASE_OFFSET(XEXP(X,0)) &&  \
-     !ILLEGAL_HIMODE_ADDR(MODE, INTVAL(XEXP(X,0)))))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)                     \
-{							            \
-    if (INDIRECTABLE_ADDRESS_P(X))                                  \
-        goto ADDR;                                                  \
-}
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the 1610, we need not do anything.  However, if we don't,
-   `memory_address' will try lots of things to get a valid address, most of
-   which will result in dead code and extra pseudos.  So we make the address
-   valid here.
-
-   This is easy:  The only valid addresses are an offset from a register
-   and we know the address isn't valid.  So just call either `force_operand'
-   or `force_reg' unless this is a (plus (reg ...) (const_int 0)).  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)			\
-{ if (GET_CODE (X) == PLUS && XEXP (X, 1) == const0_rtx)	\
-    X = XEXP (x, 0);						\
-  if (GET_CODE (X) == MULT || GET_CODE (X) == PLUS)		\
-    X = force_operand (X, 0);					\
-  else								\
-    X = force_reg (Pmode, X);					\
-  goto WIN;							\
-}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the 1610, only postdecrement and postincrement address depend thus
-   (the amount of decrement or increment being the length of the operand).  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
- if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-#define LEGITIMATE_CONSTANT_P(X) (1)
-
-
-/* CONDITION CODE INFORMATION */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's. */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-   notice_update_cc( (EXP) )
-
-/* DESCRIBING RELATIVE COSTS OF OPERATIONS */
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement. */
-#define CONST_COSTS(RTX,CODE,OUTER_CODE)                                \
-  case CONST_INT:						        \
-    return 0;                                                           \
-  case LABEL_REF:						        \
-  case SYMBOL_REF:						        \
-  case CONST:								\
-    return COSTS_N_INSNS (1);						\
-                                                                        \
-  case CONST_DOUBLE:						        \
-    return COSTS_N_INSNS (2);
-
-/* Like CONST_COSTS but applies to nonconstant RTL expressions.
-   This can be used, for example to indicate how costly a multiply
-   instruction is. */
-#define RTX_COSTS(X,CODE,OUTER_CODE)                            \
-  case MEM:                                                     \
-    return GET_MODE (X) == QImode ? COSTS_N_INSNS (2) :         \
-                                    COSTS_N_INSNS (4);          \
-  case DIV:                                                     \
-  case MOD:                                                     \
-    return COSTS_N_INSNS (38);                                  \
-  case MULT:                                                    \
-    if (GET_MODE (X) == QImode)                                 \
-        return COSTS_N_INSNS (2);                               \
-    else                                                        \
-        return COSTS_N_INSNS (38);                              \
-  case PLUS:                                                    \
-    if (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT)              \
-    {                                                           \
-        if (GET_CODE (XEXP (X,1)) == CONST_INT)                 \
-        {                                                       \
-            int number = INTVAL(XEXP (X,1));                    \
-            if (number == 1)                                    \
-               return COSTS_N_INSNS (1);                        \
-            if (INT_FITS_16_BITS(number))                       \
-                return COSTS_N_INSNS (2);                       \
-            else                                                \
-                return COSTS_N_INSNS (4);                       \
-        }                                                       \
-        return COSTS_N_INSNS (1);                               \
-    }                                                           \
-    else                                                        \
-        return COSTS_N_INSNS (38);                              \
-  case MINUS:                                                   \
-    if (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT)              \
-    {                                                           \
-        if (GET_CODE (XEXP (X,1)) == CONST_INT)                 \
-        {                                                       \
-            if (INT_FITS_16_BITS(INTVAL(XEXP(X,1))))            \
-                return COSTS_N_INSNS (2);                       \
-            else                                                \
-                return COSTS_N_INSNS (4);                       \
-        }                                                       \
-        return COSTS_N_INSNS (1);                               \
-    }                                                           \
-    else                                                        \
-        return COSTS_N_INSNS (38);                              \
-  case AND: case IOR: case XOR:                                 \
-    if (GET_CODE (XEXP (X,1)) == CONST_INT)                     \
-      {                                                         \
-        if (INT_FITS_16_BITS(INTVAL(XEXP(X,1))))                \
-            return COSTS_N_INSNS (2);                           \
-        else                                                    \
-            return COSTS_N_INSNS (4);                           \
-      }                                                         \
-    return COSTS_N_INSNS (1);                                   \
-  case NEG: case NOT:                                           \
-    return COSTS_N_INSNS (1);                                   \
-  case ASHIFT:                                                  \
-  case ASHIFTRT:                                                \
-  case LSHIFTRT:                                                \
-    if (GET_CODE (XEXP (X,1)) == CONST_INT)                     \
-      {                                                         \
-        int number = INTVAL(XEXP (X,1));                        \
-        if (number == 1 || number == 4 || number == 8 ||        \
-            number == 16)                                       \
-            return COSTS_N_INSNS (1);                           \
-        else                                                    \
-            return COSTS_N_INSNS (2);                           \
-      }                                                         \
-    return COSTS_N_INSNS (1);
-
-/* An expression giving the cost of an addressing mode that contains
-   address. */
-#define ADDRESS_COST(ADDR)  dsp16xx_address_cost (ADDR)
-
-/* A c expression for the cost of moving data from a register in
-   class FROM to one in class TO. The classes are expressed using
-   the enumeration values such as GENERAL_REGS. A value of 2 is
-   the default. */
-#define REGISTER_MOVE_COST(FROM,TO)  dsp16xx_register_move_cost (FROM, TO)
-
-/* A C expression for the cost of moving data of mode MODE between
-   a register and memory. A value of 2 is the default. */
-#define MEMORY_MOVE_COST(MODE,CLASS,IN)                          \
-  (GET_MODE_CLASS(MODE) == MODE_INT && MODE == QImode ? 12       \
-   : 16)
-
-/* A C expression for the cost of a branch instruction. A value of
-   1 is the default; */
-#define BRANCH_COST 2
-
-
-/* Define this because otherwise gcc will try to put the function address
-   in any old pseudo register. We can only use pt. */
-#define NO_FUNCTION_CSE
-
-/* Define this macro as a C expression which is nonzero if accessing less
-   than a word of memory (i.e a char or short) is no faster than accessing
-   a word of memory, i.e if such access require more than one instruction
-   or if ther is no difference in cost between byte and (aligned) word
-   loads. */
-#define SLOW_BYTE_ACCESS 1
-
-/* Define this macro if zero-extension (of a char or short to an int) can
-   be done faster if the destination is a register that is know to be zero. */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Define this macro if unaligned accesses have a cost many times greater than
-   aligned accesses, for example if they are emulated in a trap handler */
-/* define SLOW_UNALIGNED_ACCESS */
-
-/* Define this macro to inhibit strength reduction of memory addresses */
-/* #define DONT_REDUCE_ADDR */
-
-
-/* DIVIDING THE OUTPUT IN SECTIONS */
-/* Output before read-only data.  */
-
-#define DEFAULT_TEXT_SEG_NAME ".text"
-#define TEXT_SECTION_ASM_OP  rsect_text
-
-/* Output before constants and strings */
-#define DEFAULT_CONST_SEG_NAME  ".const"
-#define READONLY_SECTION_ASM_OP rsect_const
-#define READONLY_DATA_SECTION   const_section
-
-/* Output before writable data.  */
-#define DEFAULT_DATA_SEG_NAME ".data"
-#define DATA_SECTION_ASM_OP  rsect_data
-
-#define DEFAULT_BSS_SEG_NAME ".bss"
-#define BSS_SECTION_ASM_OP rsect_bss
-
-/* We will default to using 1610 if the user doesn't
-   specify it. */
-#define DEFAULT_CHIP_NAME "1610"
-
-/* A list of names for sections other than the standard ones, which are
-   'in_text' and 'in_data' (and .bss if BSS_SECTION_ASM_OP is defined). */
-#define EXTRA_SECTIONS in_const
-
-#define EXTRA_SECTION_FUNCTIONS  \
-void                                                               \
-const_section ()                                                   \
-{                                                                  \
-    if (in_section != in_const)                                    \
-    {                                                              \
-        fprintf (asm_out_file, "%s\n", READONLY_SECTION_ASM_OP);   \
-	in_section = in_const;                                     \
-    }                                                              \
-}
-
-/* THE OVERALL FRAMEWORK OF AN ASSEMBLER FILE */
-
-/* Output at beginning of assembler file.  */
-#define ASM_FILE_START(FILE) dsp16xx_file_start () 
-
-/* Prevent output of .gcc_compiled */
-#define ASM_IDENTIFY_GCC(FILE)   
-
-/* A C string constant describing how to begin a comment in the target
-   assembler language. */
-/* define ASM_COMMENT_START */
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-#define ASM_APP_OFF ""
-
-/* OUTPUT OF DATA */
-
-/* This is how to output an assembler line defining a `double' constant.  */
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  asm_output_float (FILE,VALUE)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  asm_output_float (FILE, VALUE)
-
-/* This is how to output an assembler line defining a 'float' constant of
-   size HFmode. */
-#define ASM_OUTPUT_SHORT_FLOAT(FILE,VALUE)  asm_output_float (FILE, VALUE)
-
-/* This is how to output an assembler line defining an `char' constant.  */
-#define ASM_OUTPUT_CHAR(FILE,VALUE)              \
-( fprintf (FILE, "\tint "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line defining an `short' constant.  */
-#define ASM_OUTPUT_SHORT(FILE,EXP)   asm_output_long(FILE,INTVAL(EXP))
-
-/* This is how to output an assembler line defining a 'int' constant. */
-#define ASM_OUTPUT_INT(FILE, EXP)    asm_output_long(FILE,INTVAL(EXP))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-#define ASM_OUTPUT_BYTE(FILE,VALUE) \
-  fprintf ((FILE), "\tint %ld\n", (long)(VALUE))
-
-
-/* This is how we output a 'c' character string. For the 16xx
-   assembler we have to do it one letter at a time */
-
-#define ASCII_LENGTH 10
-
-#define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
-  do {									      \
-    FILE *_hide_asm_out_file = (MYFILE);				      \
-    unsigned char *_hide_p = (unsigned char *) (MYSTRING);		      \
-    int _hide_thissize = (MYLENGTH);					      \
-    {									      \
-      FILE *asm_out_file = _hide_asm_out_file;				      \
-      unsigned char *p = _hide_p;					      \
-      int thissize = _hide_thissize;					      \
-      int i;								      \
-									      \
-      for (i = 0; i < thissize; i++)					      \
-	{								      \
-	  register int c = p[i];					      \
-	  								      \
-	  if (i % ASCII_LENGTH == 0) \
-	    fprintf (asm_out_file, "\tint ");				      \
-	    								\
-	  if (c >= ' ' && c < 0177 && c != '\'')			      \
-	  {								      \
-	    putc ('\'', asm_out_file);					      \
-	    putc (c, asm_out_file);					      \
-	    putc ('\'', asm_out_file);					      \
-	  }								      \
-	  else								      \
-	    {								      \
-	      fprintf (asm_out_file, "%d", c);			              \
-	      /* After an octal-escape, if a digit follows,		      \
-		 terminate one string constant and start another.	      \
-		 The Vax assembler fails to stop reading the escape	      \
-		 after three digits, so this is the only way we		      \
-		 can get it to parse the data properly.  		      \
-	      if (i < thissize - 1					      \
-		  && p[i + 1] >= '0' && p[i + 1] <= '9')		      \
-		fprintf (asm_out_file, "\'\n\tint \'");		              \
-		*/ \
-	  }								      \
-	  /* if: \
-	     we are not at the last char (i != thissize -1) \
-	     and (we are not at a line break multiple  \
-	     but i == 0) (it will be the very first time) \
-	     then put out a comma to extend. \
-	   */ \
-	  if ((i != thissize - 1) && ((i + 1) % ASCII_LENGTH))	      \
-	    fprintf(asm_out_file, ",");	 	                      \
-	  if (!((i + 1) % ASCII_LENGTH)) \
-	    fprintf (asm_out_file, "\n");			      \
-	}								      \
-      fprintf (asm_out_file, "\n");					      \
-    }									      \
-  }									      \
-  while (0)
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable or function
-   named NAME. LABELNO is an integer which is different for
-   each call. */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)			\
-  do {									\
-    int len = strlen (NAME);						\
-    char *temp = (char *) alloca (len + 3);				\
-    temp[0] = 'L';							\
-    strcpy (&temp[1], (NAME));						\
-    temp[len + 1] = '_';						\
-    temp[len + 2] = 0;							\
-    (OUTPUT) = (char *) alloca (strlen (NAME) + 11);			\
-    ASM_GENERATE_INTERNAL_LABEL (OUTPUT, temp, LABELNO);		\
-  } while (0)
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-
-/* OUTPUT OF UNINITIALIZED VARIABLES */
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-  asm_output_common (FILE, NAME, SIZE, ROUNDED);
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-  asm_output_local (FILE, NAME, SIZE, ROUNDED);
-
-/* OUTPUT AND GENERATION OF LABELS */
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs (".global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* A C statement to output to the stdio stream any text necessary
-   for declaring the name of an external symbol named name which
-   is referenced in this compilation but not defined. */
-
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)   \
-{					\
-	fprintf (FILE, ".extern ");	\
-	assemble_name (FILE, NAME);	\
-	fprintf (FILE, "\n");		\
-}
-/* A C statement to output on stream an assembler pseudo-op to
-   declare a library function named external. */
-
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN)    \
-{						\
-	fprintf (FILE, ".extern ");		\
-	assemble_name (FILE, XSTR (FUN, 0));	\
-	fprintf (FILE, "\n");			\
-}
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-
-/* OUTPUT OF ASSEMBLER INSTRUCTIONS */
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"a0", "a0l", "a1", "a1l", "x", "y", "yl", "p", "pl",  \
- "r0", "r1", "r2",  "r3", "j", "k", "ybase", "pt",     \
- "ar0", "ar1", "ar2", "ar3",                           \
- "c0", "c1", "c2", "pr", "rb",                         \
- "*(0)", "*(1)", "*(2)", "*(3)", "*(4)", "*(5)",       \
- "*(6)", "*(7)", "*(8)", "*(9)", "*(10)", "*(11)",     \
- "*(12)", "*(13)", "*(14)", "*(15)", "*(16)", "*(17)", \
- "*(18)", "*(19)", "*(20)", "*(21)", "*(22)", "*(23)", \
- "*(24)", "*(25)", "*(26)", "*(27)", "*(28)", "*(29)", \
- "*(30)", "*(31)" }
-
-#define HIMODE_REGISTER_NAMES \
-{"a0", "a0", "a1", "a1", "x", "y", "y", "p", "p",  \
- "r0", "r1", "r2",  "r3", "j", "k", "ybase", "pt",     \
- "ar0", "ar1", "ar2", "ar3",                           \
- "c0", "c1", "c2", "pr", "rb",                         \
- "*(0)", "*(1)", "*(2)", "*(3)", "*(4)", "*(5)",       \
- "*(6)", "*(7)", "*(8)", "*(9)", "*(10)", "*(11)",     \
- "*(12)", "*(13)", "*(14)", "*(15)", "*(16)", "*(17)", \
- "*(18)", "*(19)", "*(20)", "*(21)", "*(22)", "*(23)", \
- "*(24)", "*(25)", "*(26)", "*(27)", "*(28)", "*(29)", \
- "*(30)", "*(31)" }
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)  0
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.
-   
-   DSP1610 extensions for operand codes:
-
-   %H - print lower 16 bits of constant
-   %U - print upper 16 bits of constant
-   %w - print low half of register (e.g 'a0l')
-   %u - print upper half of register (e.g 'a0')
-   %b - print high half of accumulator for F3 ALU instructions
-   %h - print constant in decimal   */
-
-#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE)
-
-
-/* Print a memory address as an operand to reference that memory location. */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  print_operand_address (FILE, ADDR)
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code since it is used only for profiling  */
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)    fatal("Profiling not implemented yet.");
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code since it is used only for profiling  */
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)     fatal("Profiling not implemented yet."); 
-
-/* OUTPUT OF DISPATCH TABLES */
-
-/* This macro should be provided on machines where the addresses in a dispatch
-   table are relative to the table's own address. */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\tint L%d-L%d\n", VALUE, REL)
-
-/* This macro should be provided on machines where the addresses in a dispatch
-   table are absolute. */
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\tint L%d\n", VALUE)
-
-/* ASSEMBLER COMMANDS FOR ALIGNMENT */
-
-/* This is how to output an assembler line that says to advance 
-   the location counter to a multiple of 2**LOG bytes. We should
-   not have to do any alignment since the 1610 is a word machine. */
-#define ASM_OUTPUT_ALIGN(FILE,LOG)
-
-/* Define this macro if ASM_OUTPUT_SKIP should not be used in the text section
-   because it fails to put zero1 in the bytes that are skipped. */
-#define ASM_NO_SKIP_IN_TEXT 1
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t%d * int 0\n", (SIZE))
-
-/* CONTROLLING DEBUGGING INFORMATION FORMAT */
-
-/* Define this macro if GCC should produce COFF-style debugging output
-   for SDB in response to the '-g' option */
-#define SDB_DEBUGGING_INFO
-
-/* Support generating stabs for the listing file generator */
-#define DBX_DEBUGGING_INFO
-
-/* The default format when -g is given is still COFF debug info */
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
-
-#define DBX_REGISTER_NUMBER(REGNO)   (REGNO)
-
-/* MISCELLANEOUS PARAMETERS */
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE QImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 1
-
-/* Defining this macro causes the compiler to omit a sign-extend, zero-extend,
-   or bitwise 'and' instruction that truncates the count of a shift operation
-   to a width equal to the number of bits needed to represent the size of the
-   object being shifted. Do not define this macro unless the truncation applies
-   to both shift operations and bit-field operations (if any). */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* When a prototype says `char' or `short', really pass an `int'.  */
-#define PROMOTE_PROTOTYPES
-
-/* An alias for the machine mode used for pointers */
-#define Pmode  QImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE  QImode
-
-#if !defined(__DATE__)
-#define TARGET_VERSION fprintf (stderr, " (%s)", VERSION_INFO1)
-#else
-#define TARGET_VERSION fprintf (stderr, " (%s, %s)", VERSION_INFO1, __DATE__)
-#endif
-
-#define VERSION_INFO1 "AT&T DSP16xx C Cross Compiler, version 1.2.0"
-
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* If this macro is defined, GNU CC gathers statistics about the number and
-   kind of tree node it allocates during each run. The option '-fstats' will
-   tell the compiler to print these statistics about the sizes of it obstacks. */
-#define GATHER_STATISTICS
-
-/* Define this so gcc does not output a call to __main, since we
-   are not currently supporting c++. */
-#define INIT_SECTION_ASM_OP  1
diff --git a/gcc/config/dsp16xx/dsp16xx.md b/gcc/config/dsp16xx/dsp16xx.md
deleted file mode 100755
index 9923178..0000000
--- a/gcc/config/dsp16xx/dsp16xx.md
+++ /dev/null
@@ -1,2171 +0,0 @@
-;;- Machine description for the AT&T DSP1600 for GNU C compiler
-;;  Copyright (C) 1994, 1995, 1997 Free Software Foundation, Inc.
-;;  Contributed by Michael Collison (collison@world.std.com).
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; Attribute specifications
-
-; Type of each instruction.  Default is arithmetic.
-; I'd like to write the list as this, but genattrtab won't accept it.
-;
-; "jump,cond_jump,call,			; flow-control instructions
-;  load_i,load, store, move		; Y space address arithmetic instructions
-;  malu,special,f3_alu,f3_alu_i		; data arithmetic unit instructions
-;  shift_i,shift, bfield_i, bfield	; bit manipulation unit instructions
-;  arith,				; integer unit instructions
-;  nop
-
-; Classification of each insn.  Some insns of TYPE_BRANCH are multi-word.
-(define_attr "type"
-  "jump,cond_jump,call,load_i,load,move,store,malu,malu_mul,special,f3_alu,f3_alu_i,shift_i,shift,bfield_i,bfield,nop,ld_short_i"
-  (const_string "malu"))
-
-; Length in # of instructions of each insn.  The values are not exact, but
-; are safe.
-(define_attr "length" ""
-  (cond [(eq_attr "type" "cond_jump,f3_alu_i,shift_i,bfield_i,load_i")
-	 (const_int 2)]
-	(const_int 1)))
-
-
-;;  ....................
-;;
-;;  Test against 0 instructions
-;;
-;;  ....................
-
-(define_expand "tsthi"
-  [(set (cc0)
-        (match_operand:HI 0 "register_operand" ""))]
-  ""
-  "
-{
-  dsp16xx_compare_gen = gen_tst_reg;
-  dsp16xx_compare_op0 = operands[0];
-  dsp16xx_compare_op1 = const0_rtx;
-  DONE;
-}")
-
-(define_insn "tsthi_1"
-  [(set (cc0)
-	(match_operand:HI 0 "register_operand" "A"))]
-  ""
-  "%0=%0"
-  [(set_attr "type" "malu")])
-
-(define_expand "tstqi"
-  [(set (cc0)
-        (match_operand:QI 0 "register_operand" ""))]
-  ""
-  "
-{
-  dsp16xx_compare_gen = gen_tst_reg;
-  dsp16xx_compare_op0 = operands[0];
-  dsp16xx_compare_op1 = const0_rtx;
-  DONE;
-}")
-
-(define_insn "tstqi_1"
-  [(set (cc0)
-	(match_operand:QI 0 "register_operand" "j,q"))
-   (clobber (match_scratch:QI 1 "=k,u"))]
-  ""
-  "@
-   %1=0\;%b0-0
-   %1=0\;%b0-0"
-  [(set_attr "type" "malu,malu")])
-
-
-;;
-;;  ....................
-;;
-;;  Bit test instructions
-;;
-;;  ....................
-
-(define_insn ""
-  [(set (cc0)
-	(and:HI (match_operand:HI 0 "register_operand" "A,!A,A")
-		(match_operand:HI 1 "nonmemory_operand" "Z,A,I")))]
-  "" 
-  "*
-{
-	switch (which_alternative)
-	{
-	   case 0:
-	   case 1:
-   	      return \"%0&%1\";
-
-	   case 2:
-   	      return \"%0&%H1\";
-         }
-}"
-  [(set_attr "type" "f3_alu,malu,f3_alu_i")])
-
-
-;;(define_insn ""
-;;  [(set (cc0)
-;;	(and:QI (match_operand:QI 0 "register_operand" "h")
-;;		(match_operand:QI 1 "const_int_operand" "I")))]
-;;  "" 
-;;  "%b0&%H1"
-;;  [(set_attr "type" "f3_alu_i")])
-
-;;
-;;
-;; Compare Instructions
-;;
-
-(define_expand "cmphi"
-  [(parallel [(set (cc0)
-		   (compare (match_operand:HI 0 "general_operand" "")
-			    (match_operand:HI 1 "general_operand" "")))
-	      (clobber (match_scratch:QI 2 ""))
-	      (clobber (match_scratch:QI 3 ""))
-	      (clobber (match_scratch:QI 4 ""))
-	      (clobber (match_scratch:QI 5 ""))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    operands[1] = force_reg (HImode, operands[1]);
-
-  dsp16xx_compare_gen = gen_compare_reg;
-  dsp16xx_compare_op0 = operands[0];
-  dsp16xx_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_insn ""
-  [(set (cc0) 
-	(compare (match_operand:HI 0 "general_operand" "Z*r*m*i")
-		 (match_operand:HI 1 "general_operand" "Z*r*m*i")))
-   (clobber (match_scratch:QI 2 "=&A"))
-   (clobber (match_scratch:QI 3 "=&A"))
-   (clobber (match_scratch:QI 4 "=&A"))
-   (clobber (match_scratch:QI 5 "=&A"))]
-  "next_cc_user_unsigned (insn)"
-  "*
-{
-  if (GET_CODE(operands[0]) == REG)
-    {
-      if (REGNO (operands[0]) == REG_Y ||
-	  REGNO (operands[0]) == REG_PROD)
-	{
-	  output_asm_insn (\"a0=%0\", operands);
-	}
-      else if (IS_YBASE_REGISTER_WINDOW (REGNO(operands[0])))
-	{
-	  output_asm_insn (\"a0=%u0\;a0l=%w0\", operands);
-	}
-      else
-	fatal (\"Invalid register for compare\");
-    }
-  else if (GET_CODE(operands[0]) == CONST_INT)
-    {
-      output_asm_insn (\"a0=%U0\;a0l=%H0\", operands);
-    }
-  else if (GET_CODE (operands[0]) == MEM)
-    {
-      rtx xoperands[2];
-
-      xoperands[0] = gen_rtx_REG (HImode, REG_A0);
-      xoperands[1] = operands[0];
-      double_reg_from_memory (xoperands);
-    }
-
-  if (GET_CODE(operands[1]) == REG)
-    {
-      if (REGNO (operands[1]) == REG_Y ||
-	  REGNO (operands[1]) == REG_PROD)
-	{
-	  output_asm_insn (\"a1=%1\", operands);
-	}
-      else if (IS_YBASE_REGISTER_WINDOW (REGNO(operands[1])))
-	{
-	  output_asm_insn (\"a1=%u1\;a1l=%w1\", operands);
-	}
-      else
-	fatal (\"Invalid register for compare\");
-    }
-  else if (GET_CODE (operands[1]) == MEM)
-    {
-      rtx xoperands[2];
-
-      xoperands[0] = gen_rtx_REG (HImode, REG_A1);
-      xoperands[1] = operands[1];
-      double_reg_from_memory (xoperands);
-    }
-  else if (GET_CODE(operands[1]) == CONST_INT)
-    {
-      output_asm_insn (\"a1=%U1\;a1l=%H1\", operands);
-    }
-  
-  return \"psw = 0\;a0 - a1\";
-}")
-
-(define_insn ""
-  [(set (cc0) (compare (match_operand:HI 0 "register_operand" "A,!A")
-		       (match_operand:HI 1 "register_operand" "Z,*A")))]
-  ""
-  "@
-   %0-%1
-   %0-%1"
-  [(set_attr "type" "malu,f3_alu")])
-
-(define_expand "cmpqi"
-  [(parallel [(set (cc0)
-		   (compare (match_operand:QI 0 "register_operand" "")
-			    (match_operand:QI 1 "nonmemory_operand" "")))
-	      (clobber (match_operand:QI 2 "register_operand" ""))
-	      (clobber (match_operand:QI 3 "register_operand" ""))])]
-  ""
-  "
- {
-  if (operands[0])	/* Avoid unused code warning */
-    {
-      dsp16xx_compare_gen = gen_compare_reg;
-      dsp16xx_compare_op0 = operands[0];
-      dsp16xx_compare_op1 = operands[1];
-      DONE;
-    }
- }")
-
-(define_insn ""
-  [(set (cc0) (compare (match_operand:QI 0 "register_operand"  "k,k,!k,k,u,u,!u,u")
-                       (match_operand:QI 1 "nonmemory_operand" "w,z,u,i,w,z,k,i")))
-	(clobber (match_scratch:QI 2 "=j,j,j,j,q,q,q,q"))
-	(clobber (match_scratch:QI 3 "=v,y,q,X,v,y,j,X"))]
-  "next_cc_user_unsigned (insn)"
-  "@
-   %2=0\;%3=0\;%2-%3
-   %2=0\;%3=0\;%2-%3
-   %2=0\;%3=0\;%2-%3
-   %2=0\;%0-%H1
-   %2=0\;%3=0\;%2-%3
-   %2=0\;%3=0\;%2-%3
-   %2=0\;%3=0\;%2-%3
-   %2=0\;%0-%H1")
-
-
-(define_insn ""
-  [(set (cc0) (compare (match_operand:QI 0 "register_operand"  "j,j,!j,j,q,q,!q,q")
-                       (match_operand:QI 1 "nonmemory_operand" "v,y,q,i,v,y,j,i")))
-	(clobber (match_scratch:QI 2 "=k,k,k,k,u,u,u,u"))
-	(clobber (match_scratch:QI 3 "=w,z,u,X,w,z,k,X"))]
-  ""
-  "@
-   %2=0\;%3=0\;%0-%1
-   %2=0\;%3=0\;%0-%1
-   %2=0\;%3=0\;%0-%1
-   %2=0\;%b0-%H1
-   %2=0\;%3=0\;%0-%1
-   %2=0\;%3=0\;%0-%1
-   %2=0\;%3=0\;%0-%1
-   %2=0\;%b0-%H1")
-
-
-(define_expand "cmphf"
-  [(set (cc0)
-	(compare (match_operand:HF 0 "register_operand" "")
-		 (match_operand:HF 1 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_cmphf3_libcall)
-    dsp16xx_cmphf3_libcall = gen_rtx_SYMBOL_REF (Pmode, CMPHF3_LIBCALL);
-
-   dsp16xx_compare_gen = gen_compare_reg;
-   dsp16xx_compare_op0 = operands[0];
-   dsp16xx_compare_op1 = operands[1];
-   emit_library_call (dsp16xx_cmphf3_libcall, 1, HImode, 2,
-		      operands[0], HFmode,
-		      operands[1], HFmode);
-   emit_insn (gen_tsthi_1 (copy_to_reg(hard_libcall_value (HImode))));
-   DONE;
-}")
-
-
-;;  ....................
-;;
-;;  Add instructions
-;;
-;;  ....................
-
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "register_operand" "=A,A,A")
-	(plus:HI (match_operand:HI 1 "register_operand" "%A,A,A")
-		 (match_operand:HI 2 "nonmemory_operand" "Z,d,i")))]
-  ""
-  "@
-   %0=%1+%2
-   %0=%1+%2
-   %0=%w1+%H2\;%0=%b0+%U2"
-  [(set_attr "type" "malu,malu,f3_alu_i")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=k,u,!k,!u")
-	(plus:QI (plus:QI (match_operand:QI 1 "register_operand" "uk,uk,uk,uk")
-			  (match_operand:QI 2 "register_operand" "wz,wz,uk,uk"))
-		 (match_operand:QI 3 "immediate_operand" "i,i,i,i")))
-   (clobber (match_scratch:QI 4 "=j,q,j,q"))]
-  ""
-  "@
-   %m0=%m1+%m2\;%m0=%0+%H3
-   %m0=%m1+%m2\;%m0=%0+%H3
-   %m0=%m1+%m2\;%m0=%0+%H3
-   %m0=%m1+%m2\;%m0=%0+%H3")
-
-(define_expand "addqi3"
-  [(parallel [(set (match_operand:QI 0 "register_operand" "")
-		   (plus:QI (match_operand:QI 1 "register_operand" "")
-			    (match_operand:QI 2 "nonmemory_operand" "")))
-	      (clobber (match_scratch:QI 3 ""))])]
-  ""
-  "
-{
-  if (reload_in_progress)
-    {
-      if (REG_P (operands[1]) && 
-	  (REGNO(operands[1]) == STACK_POINTER_REGNUM ||
-	   REGNO(operands[1]) == FRAME_POINTER_REGNUM) &&
-	  GET_CODE (operands[2]) == CONST_INT)
-	{
-	  if (REG_P (operands[0]) && IS_ACCUM_REG(REGNO(operands[0])))
-	    emit_move_insn (operands[0], operands[1]);
-
-	  operands[1] = operands[0];
-	}
-    }
-}")
-
-	
-(define_insn "match_addqi3"
-  [(set (match_operand:QI 0 "register_operand" "=!a,!a,k,u,!k,!u,h,!a")
-	(plus:QI (match_operand:QI 1 "register_operand" "0,0,uk,uk,uk,uk,h,0")
-		 (match_operand:QI 2 "nonmemory_operand" "W,N,wzi,wzi,uk,uk,i,n")))
-	(clobber (match_scratch:QI 3 "=X,X,j,q,j,q,X,W"))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      return \"*%0++%2\";
-
-    case 1:
-      switch (INTVAL (operands[2]))
-	{
-	case -1:
-	  return \"*%0--\";
-
-	case 1:
-	  return \"*%0++\";
-
-	case -2:
-	  return \"*%0--\;*%0--\";
-
-	case 2:
-	  return \"*%0++\;*%0++\";
-	}
-
-    case 2:
-    case 3:
-      if (!CONSTANT_P(operands[2]))
-        return \"%m0=%m1+%m2\";
-      else
-        return \"%m0=%1+%H2\";
-
-    case 4:
-    case 5:
-      return \"%m0=%m1+%m2\";
-
-    case 6:
-      return \"%0=%b1+%H2\";
-
-    case 7:
-      return \"%3=%2\;*%0++%3\";
-    }
-}")
-
-(define_expand "addhf3"
-  [(set (match_operand:HF 0 "register_operand" "")
-	(plus:HF (match_operand:HF 1 "register_operand" "")
-		 (match_operand:HF 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_addhf3_libcall)
-    dsp16xx_addhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, ADDHF3_LIBCALL);
-
-   emit_library_call (dsp16xx_addhf3_libcall, 1, HFmode, 2,
-		      operands[1], HFmode,
-		      operands[2], HFmode);
-   emit_move_insn (operands[0], hard_libcall_value(HFmode));
-   DONE;
-}")
-		      
-
-;;
-;;  ....................
-;;
-;;  Subtract instructions
-;;
-;;  ....................
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "register_operand" "=A,A,A")
-	(minus:HI (match_operand:HI 1 "register_operand" "A,A,A")
-		  (match_operand:HI 2 "nonmemory_operand" "Z,d,i")))]
-  ""
-  "@
-   %0=%1-%2
-   %0=%1-%2
-   %0=%w1-%H2\;%0=%b0-%U2"
-  [(set_attr "type" "malu,malu,f3_alu_i")])
-
-(define_insn "subqi3"
-  [(set (match_operand:QI 0 "register_operand" "=?*a,k,u,!k,!u")
-	(minus:QI (match_operand:QI 1 "register_operand" "0,uk,uk,uk,uk")
-		 (match_operand:QI 2 "nonmemory_operand" "n,wzi,wzi,uk,uk")))
-	(clobber (match_scratch:QI 3 "=W,j,q,j,q"))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      switch (INTVAL (operands[2]))
-	{
-	case 0:
-	  return \"\";
-	  
-	case 1:
-	  return \"*%0--\";
-	  
-	case -1:
-	  return \"*%0++\";
-	  
-	default:
-	  operands[2] = GEN_INT (-INTVAL (operands[2]));
-	  
-	  if (SHORT_IMMEDIATE(operands[2]))
-	    return \"set %3=%H2\;*%0++%3\";
-	  else
-	    return \"%3=%H2\;*%0++%3\";
-	}
-      
-    case 1:
-    case 2:
-      if (!CONSTANT_P(operands[2]))
-        return \"%m0=%m1-%m2\";
-      else
-        return \"%m0=%1-%H2\";
-
-    case 3:
-    case 4:
-      return \"%m0=%m1-%m2\";
-    }
-}")
-
-(define_expand "subhf3"
-  [(set (match_operand:HF 0 "register_operand" "")
-	(minus:HF (match_operand:HF 1 "register_operand" "")
-		 (match_operand:HF 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_subhf3_libcall)
-    dsp16xx_subhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, SUBHF3_LIBCALL);
-  
-  emit_library_call (dsp16xx_subhf3_libcall, 1, HFmode, 2,
-		     operands[1], HFmode,
-		     operands[2], HFmode);
-  emit_move_insn (operands[0], hard_libcall_value(HFmode));
-  DONE;
-}")
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (neg:HI (match_operand:HI 1 "register_operand" "A")))]
-  ""
-  "%0=-%1"
-  [(set_attr "type" "special")])
-
-(define_expand "neghf2"
-  [(set (match_operand:HF 0 "general_operand" "")
-	(neg:HF (match_operand:HF 1 "general_operand" "")))]
-  ""
-"
-{
-  if (!dsp16xx_neghf2_libcall)
-    dsp16xx_neghf2_libcall = gen_rtx_SYMBOL_REF (Pmode, NEGHF2_LIBCALL);
-  
-  emit_library_call (dsp16xx_neghf2_libcall, 1, HFmode, 1,
-		     operands[1], HFmode);
-  emit_move_insn (operands[0], hard_libcall_value(HFmode));
-  DONE;
-}")
-
-
-
-;;
-;;  ....................
-;;
-;;  Multiply instructions
-;;
-
-(define_expand "mulhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(mult:HI (match_operand:HI 1 "register_operand" "")
-		 (match_operand:HI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_mulhi3_libcall)
-    dsp16xx_mulhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, MULHI3_LIBCALL);
-
-   emit_library_call (dsp16xx_mulhi3_libcall, 1, HImode, 2,
-		      operands[1], HImode,
-		      operands[2], HImode);
-   emit_move_insn (operands[0], hard_libcall_value(HImode));
-   DONE;
-}")
-
-(define_insn "mulqi3"
-  [(set (match_operand:QI 0 "register_operand" "=w")
-        (mult:QI (match_operand:QI 1 "register_operand" "%x")
-                 (match_operand:QI 2 "register_operand" "y")))
-   (clobber (match_scratch:QI 3 "=v"))]
-  ""
-  "%m0=%1*%2"
-  [(set_attr "type" "malu_mul")])
-
-(define_insn "mulqihi3"
-  [(set (match_operand:HI 0 "register_operand" "=t")
-        (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%x"))
-                 (sign_extend:HI (match_operand:QI 2 "register_operand" "y"))))]
-  ""
-  "%0=%1*%2"
-  [(set_attr "type" "malu_mul")])
-
-(define_insn "umulqihi3"
-  [(set (match_operand:HI 0 "register_operand" "=t")
-        (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%x"))
-                 (zero_extend:HI (match_operand:QI 2 "register_operand" "y"))))]
-  ""
-  "%0=%1*%2"
-  [(set_attr "type" "malu_mul")])
-
-(define_expand "mulhf3"
-  [(set (match_operand:HF 0 "register_operand" "")
-	(mult:HF (match_operand:HF 1 "register_operand" "")
-		 (match_operand:HF 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_mulhf3_libcall)
-    dsp16xx_mulhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, MULHF3_LIBCALL);
-  
-  emit_library_call (dsp16xx_mulhf3_libcall, 1, HFmode, 2,
-		     operands[1], HFmode,
-		     operands[2], HFmode);
-  emit_move_insn (operands[0], hard_libcall_value(HFmode));
-  DONE;
-}")
-
-
-
-;;
-;; *******************
-;;
-;; Divide Instructions
-;;
-
-(define_expand "divhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(div:HI (match_operand:HI 1 "register_operand" "")
-		 (match_operand:HI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_divhi3_libcall)
-    dsp16xx_divhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, DIVHI3_LIBCALL);
-
-   emit_library_call (dsp16xx_divhi3_libcall, 1, HImode, 2,
-		      operands[1], HImode,
-		      operands[2], HImode);
-   emit_move_insn (operands[0], hard_libcall_value(HImode));
-   DONE;
-}")
-
-(define_expand "udivhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(udiv:HI (match_operand:HI 1 "register_operand" "")
-		 (match_operand:HI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_udivhi3_libcall)
-    dsp16xx_udivhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, UDIVHI3_LIBCALL);
-  
-  emit_library_call (dsp16xx_udivhi3_libcall, 1, HImode, 2,
-		     operands[1], HImode,
-		     operands[2], HImode);
-  emit_move_insn (operands[0], hard_libcall_value(HImode));
-  DONE;
-}")
-
-(define_expand "divqi3"
-  [(set (match_operand:QI 0 "register_operand" "")
-	(div:QI (match_operand:QI 1 "register_operand" "")
-		 (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_divqi3_libcall)
-    dsp16xx_divqi3_libcall = gen_rtx_SYMBOL_REF (Pmode, DIVQI3_LIBCALL);
-  
-  emit_library_call (dsp16xx_divqi3_libcall, 1, QImode, 2,
-		     operands[1], QImode,
-		     operands[2], QImode);
-  emit_move_insn (operands[0], hard_libcall_value(QImode));
-  DONE;
-}")
-
-(define_expand "udivqi3"
-  [(set (match_operand:QI 0 "register_operand" "")
-	(udiv:QI (match_operand:QI 1 "register_operand" "")
-		 (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_udivqi3_libcall)
-    dsp16xx_udivqi3_libcall = gen_rtx_SYMBOL_REF (Pmode, UDIVQI3_LIBCALL);
-
-   emit_library_call (dsp16xx_udivqi3_libcall, 1, QImode, 2,
-		      operands[1], QImode,
-		      operands[2], QImode);
-   emit_move_insn (operands[0], hard_libcall_value(QImode));
-   DONE;
-}")
-
-;;
-;;  ....................
-;;
-;;  Modulo instructions
-;;
-;;  ....................
-
-(define_expand "modhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(mod:HI (match_operand:HI 1 "register_operand" "")
-		(match_operand:HI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_modhi3_libcall)
-    dsp16xx_modhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, MODHI3_LIBCALL);
-  
-  emit_library_call (dsp16xx_modhi3_libcall, 1, HImode, 2,
-		     operands[1], HImode,
-		     operands[2], HImode);
-  emit_move_insn (operands[0], hard_libcall_value(HImode));
-  DONE;
-}")
-
-(define_expand "umodhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(umod:HI (match_operand:HI 1 "register_operand" "")
-		 (match_operand:HI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_umodhi3_libcall)
-    dsp16xx_umodhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, UMODHI3_LIBCALL);
-  
-  emit_library_call (dsp16xx_umodhi3_libcall, 1, HImode, 2,
-		     operands[1], HImode,
-		     operands[2], HImode);
-  emit_move_insn (operands[0], hard_libcall_value(HImode));
-  DONE;
-}")
-
-(define_expand "modqi3"
-  [(set (match_operand:QI 0 "register_operand" "")
-	(mod:QI (match_operand:QI 1 "register_operand" "")
-		(match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_modqi3_libcall)
-    dsp16xx_modqi3_libcall = gen_rtx_SYMBOL_REF (Pmode, MODQI3_LIBCALL);
-  
-  emit_library_call (dsp16xx_modqi3_libcall, 1, QImode, 2,
-		     operands[1], QImode,
-		     operands[2], QImode);
-  emit_move_insn (operands[0], hard_libcall_value(QImode));
-  DONE;
-}")
-
-(define_expand "umodqi3"
-  [(set (match_operand:QI 0 "register_operand" "")
-	(umod:QI (match_operand:QI 1 "register_operand" "")
-		 (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_umodqi3_libcall)
-    dsp16xx_umodqi3_libcall = gen_rtx_SYMBOL_REF (Pmode, UMODQI3_LIBCALL);
-  
-  emit_library_call (dsp16xx_umodqi3_libcall, 1, QImode, 2,
-		     operands[1], QImode,
-		     operands[2], QImode);
-  emit_move_insn (operands[0], hard_libcall_value(QImode));
-  DONE;
-}")
-
-(define_expand "divhf3"
-  [(set (match_operand:HF 0 "register_operand" "")
-	(div:HF (match_operand:HF 1 "register_operand" "")
-		(match_operand:HF 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_divhf3_libcall)
-    dsp16xx_divhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, DIVHF3_LIBCALL);
-  
-  emit_library_call (dsp16xx_divhf3_libcall, 1, HFmode, 2,
-		     operands[1], HFmode,
-		     operands[2], HFmode);
-  emit_move_insn (operands[0], hard_libcall_value(HFmode));
-  DONE;
-}")
-
-
-
-;;
-;; ********************
-;;
-;; Logical Instructions
-;;
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "register_operand" "=A,A,?A")
-        (and:HI (match_operand:HI 1 "register_operand" "%A,!A,A")
-                (match_operand:HI 2 "nonmemory_operand" "Z,A,i")))]
-  ""
-  "@
-   %0=%1&%2
-   %0=%1&%2
-   %0=%w1&%H2\;%0=%b0&%U2"
-  [(set_attr "type" "f3_alu,f3_alu,f3_alu_i")])
-
-(define_insn "andqi3"
-  [(set (match_operand:QI 0 "register_operand" "=k,u,uk,!k,!u,j,q,jq,!j,!q")
-	(and:QI (match_operand:QI 1 "register_operand" "uk,uk,uk,uk,uk,jq,jq,jq,jq,jq")
-		(match_operand:QI 2 "nonmemory_operand" "wz,wz,i,uk,uk,yv,yv,i,jq,jq")))
-	(clobber (match_scratch:QI 3 "=j,q,X,j,q,k,u,X,k,u"))]
-   ""
-   "@
-    %m0=%m1&%m2
-    %m0=%m1&%m2
-    %m0=%1&%H2
-    %m0=%m1&%m2
-    %m0=%m1&%m2
-    %m0=%m1&%m2
-    %m0=%m1&%m2
-    %m0=%b1&%H2
-    %m0=%m1&%m2
-    %m0=%m1&%m2")
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "register_operand" "=A,A,A,?A")
-        (ior:HI (match_operand:HI 1 "register_operand" "%A,!A,A,A")
-                (match_operand:HI 2 "nonmemory_operand" "Z,A,I,i")))]
- ""
- "@
-   %0=%u1|%u2
-   %0=%u1|%u2
-   %0=%w1|%H2
-   %0=%w1|%H2\;%0=%b0|%U2"
-  [(set_attr "type" "f3_alu,f3_alu,f3_alu_i,f3_alu_i")])
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "register_operand" "=k,u,uk,!k,!u,j,q,jq,!j,!q")
-	(ior:QI (match_operand:QI 1 "register_operand" "uk,uk,uk,uk,uk,jq,jq,jq,jq,jq")
-		(match_operand:QI 2 "nonmemory_operand" "wz,wz,i,uk,uk,yv,yv,i,jq,jq")))
-	(clobber (match_scratch:QI 3 "=j,q,X,j,q,k,u,X,k,u"))]
-   ""
-   "@
-    %m0=%m1|%m2
-    %m0=%m1|%m2
-    %m0=%1|%H2
-    %m0=%m1|%m2
-    %m0=%m1|%m2
-    %m0=%m1|%m2
-    %m0=%m1|%m2
-    %m0=%b1|%H2
-    %m0=%m1|%m2
-    %m0=%m1|%m2")
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "register_operand" "=A,A,A,?A")
-        (xor:HI (match_operand:HI 1 "register_operand" "%A,!A,A,A")
-                (match_operand:HI 2 "nonmemory_operand" "Z,A,I,i")))]
-  ""
-  "@
-   %0=%1^%2
-   %0=%1^%2
-   %0=%w1^%H2
-   %0=%w1^%H2\;%0=%b0^%U2"
-  [(set_attr "type" "f3_alu,f3_alu,f3_alu_i,f3_alu_i")])
-
-(define_insn "xorqi3"
-  [(set (match_operand:QI 0 "register_operand" "=k,u,uk,!k,!u,j,q,jq,!j,!q")
-	(xor:QI (match_operand:QI 1 "register_operand" "uk,uk,uk,uk,uk,jq,jq,jq,jq,jq")
-		(match_operand:QI 2 "nonmemory_operand" "wz,wz,i,uk,uk,yv,yv,i,jq,jq")))
-	(clobber (match_scratch:QI 3 "=j,q,X,j,q,k,u,X,k,u"))]
-   ""
-   "@
-    %m0=%m1^%m2
-    %m0=%m1^%m2
-    %m0=%1^%H2
-    %m0=%m1^%m2
-    %m0=%m1^%m2
-    %m0=%m1^%m2
-    %m0=%m1^%m2
-    %m0=%b1^%H2
-    %m0=%m1^%m2
-    %m0=%m1^%m2")
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (not:HI (match_operand:HI 1 "register_operand" "A")))]
-  ""
-  "%0= ~%1"
-  [(set_attr "type" "special")])
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "register_operand" "=ku,jq")
-        (not:QI (match_operand:QI 1 "register_operand" "ku,jq")))]
-  ""
-  "@
-   %m0= %1 ^ 0xffff
-   %m0= %b1 ^ 0xffff"
-  [(set_attr "type" "special")])
-
-
-;;
-;; MOVE INSTRUCTIONS
-;;
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, HImode))
-    DONE;
-}")
-
-
-(define_insn "match_movhi1"
-  [(set (match_operand:HI 0 "nonimmediate_operand"  "=A,Z,A,d,d,m,?d,*Y,t,f")
-	(match_operand:HI 1 "general_operand"        "d,A,K,i,m,d,*Y,?d,t,f"))]
-  "register_operand(operands[0], HImode)
-   || register_operand(operands[1], HImode)"
-  "*
-{
-	switch (which_alternative)
-        {
-		/* register to accumulator */
-		case 0:
- 		   return \"%0=%1\";
-		case 1:
-		   return \"%u0=%u1\;%w0=%w1\";
-	        case 2:
-	           return \"%0=%0^%0\";
-		case 3:
-		     return \"%u0=%U1\;%w0=%H1\";
-		case 4:
-		   double_reg_from_memory(operands);
-		   return \"\";
-		case 5:
-		   double_reg_to_memory(operands);
-		   return \"\";
-		case 6:
-		case 7:
-		   return \"%u0=%u1\;%w0=%w1\";
-		case 8:
-		case 9:
-		   return \"\";
-        }
-}"
-[(set_attr "type" "move,move,load_i,load_i,load,store,load,store,move,move")])
-
-
-;; NOTE: It is cheaper to do 'y = *r0', than 'r0 = *r0'.
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, QImode))
-    DONE;
-}")
-
-;; The movqi pattern with the parallel is used for addqi insns (which have a parallel)
-;; that are turned into moveqi insns by the flow phase. This happens when a auto-increment
-;; is detected.
-
-(define_insn "match_movqi1"
-  [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "=A,r,aW,c,?D,m<>,e,Y,r,xyz,m<>")
-		   (match_operand:QI 1 "general_operand"       "r,A,J,i,m<>,D,Y,e,0,m<>,xyz"))
-	      (clobber (match_scratch:QI 2 "=X,X,X,X,X,X,X,X,X,X,X"))])]
-  "register_operand(operands[0], QImode)
-   || register_operand(operands[1], QImode)"
-  "*
-{
-	switch (which_alternative)
-	{
-		case 0:
-		   /* We have to use the move mnemonic otherwise the 1610 will
-		      attempt to transfer all 32-bits of 'y', 'p' or an accumulator
-		      , which we don't want */
-		   if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD
-			|| IS_ACCUM_REG(REGNO(operands[1])))
-		       return \"move %0=%1\";
-		   else
-		       return \"%0=%1\";
-
-		case 1:
- 		   return \"%0=%1\";
-
-		case 2:
-		   return \"set %0=%H1\";
-
-		case 3:
-                   return \"%0=%H1\";
-
-		case 4:
-		   return \"%0=%1\";
-
-		case 5:
-		case 6:
-                   return \"%0=%1\";
-
-		case 7:
-		   return \"%0=%1\";
-
-		case 8:
-		   return \"\";
-
-                case 9: case 10:
-		   return \"%0=%1\";
-	}
-}")
-
-(define_insn "match_movqi2"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=A,r,aW,c,?D,m<>,e,Y,r,xyz,m<>")
-	(match_operand:QI 1 "general_operand"       "r,A,J,i,m<>,D,Y,e,0,m<>,xyz"))]
-  "register_operand(operands[0], QImode)
-   || register_operand(operands[1], QImode)"
-  "*
-{
-	switch (which_alternative)
-	{
-		case 0:
-		   /* We have to use the move mnemonic otherwise the 1610 will
-		      attempt to transfer all 32-bits of 'y', 'p' or an accumulator
-		      , which we don't want */
-		   if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD
-			|| IS_ACCUM_REG(REGNO(operands[1])))
-		       return \"move %0=%1\";
-		   else
-		       return \"%0=%1\";
-
-		case 1:
- 		   return \"%0=%1\";
-
-		case 2:
-		   return \"set %0=%H1\";
-
-		case 3:
-                   return \"%0=%H1\";
-
-		case 4:
-		   return \"%0=%1\";
-
-		case 5:
-		case 6:
-                   return \"%0=%1\";
-
-		case 7:
-		   return \"%0=%1\";
-
-		case 8:
-		   return \"\";
-
-                case 9: case 10:
-		   return \"%0=%1\";
-	}
-}")
-
-(define_expand "reload_inqi"
-  [(set (match_operand:QI 0 "register_operand" "=u")
-        (match_operand:QI 1 "sp_operand" ""))
-   (clobber (match_operand:QI 2 "register_operand" "=&q"))]
-  ""
-  "
-{
-  rtx addr_reg = XEXP (operands[1], 0);
-  rtx offset = XEXP (operands[1], 1);
-
-  /* First, move the frame or stack pointer to the accumulator */
-  emit_move_insn (operands[0], addr_reg);
-
-  /* Then generate the add insn */
-  emit_insn (gen_rtx (PARALLEL, VOIDmode, 
-		      gen_rtvec (2,
-				 gen_rtx (SET, VOIDmode, operands[0], 
-					  gen_rtx (PLUS, QImode, operands[0], offset)),
-				 gen_rtx (CLOBBER, VOIDmode, operands[2]))));
-  DONE;
-}")
-
-(define_expand "reload_inhi"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-        (match_operand:HI 1 "register_operand" "r"))
-   (clobber (match_operand:QI 2 "register_operand" "=&h"))]
-  ""
-  "
-{
-  /* Check for an overlap of operand 2 (an accumulator) with
-     the msw of operand 0. If we have an overlap we must reverse
-     the order of the moves. */
-
-  if (REGNO(operands[2]) == REGNO(operands[0]))
-    {
-      emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HImode));
-      emit_move_insn (operand_subword (operands[0], 1, 0, HImode), operands[2]);
-      emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HImode));
-      emit_move_insn (operand_subword (operands[0], 0, 0, HImode), operands[2]);
-    }
-  else
-    {
-      emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HImode));
-      emit_move_insn (operand_subword (operands[0], 0, 0, HImode), operands[2]);
-      emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HImode));
-      emit_move_insn (operand_subword (operands[0], 1, 0, HImode), operands[2]);
-    }
-
-  DONE;
-}")
-
-
-(define_expand "reload_outhi"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-        (match_operand:HI 1 "register_operand" "r"))
-   (clobber (match_operand:QI 2 "register_operand" "=&h"))]
-  ""
-  "
-{
-	emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HImode));
-	emit_move_insn (operand_subword (operands[0], 0, 0, HImode), operands[2]);
-	emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HImode));
-	emit_move_insn (operand_subword (operands[0], 1, 0, HImode), operands[2]);
-	DONE;
-}")
-
-(define_expand "movstrqi"
-  [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
-		   (match_operand:BLK 1 "memory_operand" ""))
-	      (use (match_operand:QI 2 "const_int_operand" ""))
-	      (use (match_operand:QI 3 "const_int_operand" ""))
-	      (clobber (match_scratch:QI 4 ""))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))])]
-  ""
-  "
-{
-  rtx addr0, addr1;
-
-  if (GET_CODE (operands[2]) != CONST_INT)
-    FAIL;
-
-  if (INTVAL(operands[2]) > 127)
-    FAIL;
-
-  addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
-  addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
-
-  operands[5] = addr0;
-  operands[6] = addr1;
-
-  operands[0] = change_address (operands[0], VOIDmode, addr0);
-  operands[1] = change_address (operands[1], VOIDmode, addr1);
-}")
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:QI 0 "register_operand" "a"))
-	(mem:BLK (match_operand:QI 1 "register_operand" "a")))
-   (use (match_operand:QI 2 "const_int_operand" "n"))
-   (use (match_operand:QI 3 "immediate_operand" "i"))
-   (clobber (match_scratch:QI 4 "=x"))
-   (clobber (match_dup 0))
-   (clobber (match_dup 1))]
-  ""
-  "*
-{ return output_block_move (operands); }")
-
-
-;; Floating point move insns
-
-
-(define_expand "movhf"
-  [(set (match_operand:HF 0 "general_operand" "")
-	(match_operand:HF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, HFmode))
-    DONE;
-}")
-
-(define_insn "match_movhf"
-  [(set (match_operand:HF 0 "nonimmediate_operand" "=A,Z,d,d,m,d,Y")
-	(match_operand:HF 1 "general_operand"       "d,A,F,m,d,Y,d"))]
-  ""
-  "*
-{
-	/* NOTE: When loading the register 16 bits at a time we
-	   MUST load the high half FIRST (because the 1610 zeros
-	   the low half) and then load the low half */
-
-	switch (which_alternative)
-        {
-		/* register to accumulator */
-		case 0:
- 		   return \"%0=%1\";
-		case 1:
-		   return \"%u0=%u1\;%w0=%w1\";
-		case 2:
-		   output_dsp16xx_float_const(operands);
-		   return \"\";
-		case 3:
-		   double_reg_from_memory(operands);
-		   return \"\";
-		case 4:
-		   double_reg_to_memory(operands);
-		   return \"\";
-		case 5:
-		case 6:
-		   return \"%u0=%u1\;%w0=%w1\";
-        }
-}"
-[(set_attr "type" "move,move,load_i,load,store,load,store")])
-
-
-
-(define_expand "reload_inhf"
-  [(set (match_operand:HF 0 "register_operand" "=r")
-        (match_operand:HF 1 "register_operand" "r"))
-   (clobber (match_operand:QI 2 "register_operand" "=&h"))]
-  ""
-  "
-{
-  /* Check for an overlap of operand 2 (an accumulator) with
-     the msw of operand 0. If we have an overlap we must reverse
-     the order of the moves. */
-
-  if (REGNO(operands[2]) == REGNO(operands[0]))
-    {
-      emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HFmode));
-      emit_move_insn (operand_subword (operands[0], 1, 0, HFmode), operands[2]);
-      emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HFmode));
-      emit_move_insn (operand_subword (operands[0], 0, 0, HFmode), operands[2]);
-    }
-  else
-    {
-      emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HFmode));
-      emit_move_insn (operand_subword (operands[0], 0, 0, HFmode), operands[2]);
-      emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HFmode));
-      emit_move_insn (operand_subword (operands[0], 1, 0, HFmode), operands[2]);
-    }
-  
-  DONE;
-}")
-
-(define_expand "reload_outhf"
-  [(set (match_operand:HF 0 "register_operand" "=r")
-        (match_operand:HF 1 "register_operand" "r"))
-   (clobber (match_operand:QI 2 "register_operand" "=&h"))]
-  ""
-  "
-{
-	emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HFmode));
-	emit_move_insn (operand_subword (operands[0], 0, 0, HFmode), operands[2]);
-	emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HFmode));
-	emit_move_insn (operand_subword (operands[0], 1, 0, HFmode), operands[2]);
-	DONE;
-}")
-
-
-;;
-;; CONVERSION INSTRUCTIONS
-;;
-
-(define_expand "extendqihi2"
-  [(clobber (match_dup 2))
-   (set (match_dup 3) (match_operand:QI 1 "register_operand" ""))
-   (set (match_operand:HI 0 "register_operand" "")
-	(ashift:HI (match_dup 2)
-		   (const_int 16)))
-   (set (match_dup 0)
-	(ashiftrt:HI (match_dup 0) (const_int 16)))]
-  ""
-  "
-{
-	operands[2] = gen_reg_rtx (HImode);
-	operands[3] = gen_rtx (SUBREG, QImode, operands[2], 1);
-}")
-
-;;(define_insn "extendqihi2"
-;;  [(set (match_operand:HI 0 "register_operand" "=A")
-;;        (sign_extend:HI (match_operand:QI 1 "register_operand" "h")))]
-;;  ""
-;;  "%0 = %1 >> 16")
-
-;;(define_insn "zero_extendqihi2"
-;;  [(set (match_operand:HI 0 "register_operand" "=t,f,A,?d,?A")
-;;        (zero_extend:HI (match_operand:QI 1 "register_operand" "w,z,ku,A,r")))]
-;;  ""
-;;  "*
-;; {
-;;  switch (which_alternative)
-;;    {
-;;    case 0:
-;;    case 1:
-;;      return \"%0=0\";
-;;
-;;    case 2:
-;;      if (REGNO(operands[1]) == (REGNO(operands[0]) + 1))
-;;        return \"%0=0\";
-;;      else
-;;	return \"%w0=%1\;%0=0\";
-;;    case 3:
-;;      return \"%w0=%1\;%0=0\";
-;;
-;;    case 4:
-;;      if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD
-;;	  || IS_ACCUM_REG(REGNO(operands[1])))
-;;	return \"move %w0=%1\;%0=0\";
-;;      else
-;;	return \"%w0=%1\;%0=0\";
-;;    }
-;; }")
-
-(define_expand "zero_extendqihi2"
-  [(clobber (match_dup 2))
-   (set (match_dup 3) (match_operand:QI 1 "register_operand" ""))
-   (set (match_operand:HI 0 "register_operand" "")
-	(ashift:HI (match_dup 2)
-		   (const_int 16)))
-   (set (match_dup 0)
-	(lshiftrt:HI (match_dup 0) (const_int 16)))]
-  ""
-  "
-{
-	operands[2] = gen_reg_rtx (HImode);
-	operands[3] = gen_rtx (SUBREG, QImode, operands[2], 1);
-}")
-
-
-(define_expand "floathihf2"
-  [(set (match_operand:HF 0 "register_operand" "")
-	(float:HF (match_operand:HI 1 "register_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_floathihf2_libcall)
-    dsp16xx_floathihf2_libcall = gen_rtx_SYMBOL_REF (Pmode, FLOATHIHF2_LIBCALL);
-  
-  emit_library_call (dsp16xx_floathihf2_libcall, 1, HFmode, 1,
-		     operands[1], HImode);
-  emit_move_insn (operands[0], hard_libcall_value(HFmode));
-  DONE;
-}")
-
-(define_expand "fix_trunchfhi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(fix:HI (match_operand:HF 1 "register_operand" "")))]
-  ""
-  "
-{
-  if (!dsp16xx_fixhfhi2_libcall)
-    dsp16xx_fixhfhi2_libcall = gen_rtx_SYMBOL_REF (Pmode, FIXHFHI2_LIBCALL);
-  
-  emit_library_call (dsp16xx_fixhfhi2_libcall, 1, HImode, 1,
-		     operands[1], HFmode);
-  emit_move_insn (operands[0], hard_libcall_value(HImode));
-  DONE;
-}")
-
-(define_expand "fixuns_trunchfhi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(unsigned_fix:HI (match_operand:HF 1 "register_operand" "")))]
-  ""
-  "
-{
-  rtx reg1 = gen_reg_rtx (HFmode);
-  rtx reg2 = gen_reg_rtx (HFmode);
-  rtx reg3 = gen_reg_rtx (HImode);
-  rtx label1 = gen_label_rtx ();
-  rtx label2 = gen_label_rtx ();
-  REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
-
-  if (reg1)			/* turn off complaints about unreached code */
-    {
-      emit_move_insn (reg1, immed_real_const_1 (offset, HFmode));
-      do_pending_stack_adjust ();
-
-      emit_insn (gen_cmphf (operands[1], reg1));
-      emit_jump_insn (gen_bge (label1));
-
-      emit_insn (gen_fix_trunchfhi2 (operands[0], operands[1]));
-      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
-			       gen_rtx (LABEL_REF, VOIDmode, label2)));
-      emit_barrier ();
-
-      emit_label (label1);
-      emit_insn (gen_subhf3 (reg2, operands[1], reg1));
-      emit_move_insn (reg3, GEN_INT (0x80000000));;
-
-      emit_insn (gen_fix_trunchfhi2 (operands[0], reg2));
-      emit_insn (gen_iorhi3 (operands[0], operands[0], reg3));
-
-      emit_label (label2);
-
-      /* allow REG_NOTES to be set on last insn (labels don't have enough
-	 fields, and can't be used for REG_NOTES anyway).  */
-      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
-      DONE;
-    }
-}")
-
-;;
-;; SHIFT INSTRUCTIONS
-;;
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (ashiftrt:HI (match_operand:HI 1 "register_operand" "A")
-                     (const_int 1)))]
-  ""
-  "%0=%1>>1"
-  [(set_attr "type" "special")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (ashiftrt:HI (match_operand:HI 1 "register_operand" "A")
-                     (const_int 4)))]
-  ""
-  "%0=%1>>4"
-  [(set_attr "type" "special")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (ashiftrt:HI (match_operand:HI 1 "register_operand" "A")
-                     (const_int 8)))]
-  ""
-  "%0=%1>>8"
-  [(set_attr "type" "special")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (ashiftrt:HI (match_operand:HI 1 "register_operand" "A")
-                     (const_int 16)))]
-  ""
-  "%0=%1>>16"
-  [(set_attr "type" "special")])
-
-;;
-;; Arithmetic Right shift
-
-(define_expand "ashrhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-        (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
-                     (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!TARGET_BMU)
-  {
-      /* If we are shifting by a constant we can do it in 1 or more
-	 1600 core shift instructions. The core instructions can
-	 shift by 1, 4, 8, or 16. */
-      
-      if (GET_CODE(operands[2]) == CONST_INT)
-	;
-      else
-      {
-	rtx label1 = gen_label_rtx ();
-	rtx label2 = gen_label_rtx ();
-
-#if 0
-	if (!dsp16xx_ashrhi3_libcall)
-	  dsp16xx_ashrhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, ASHRHI3_LIBCALL);
-
-	  emit_library_call (dsp16xx_ashrhi3_libcall, 1, HImode, 2,
-			     operands[1], HImode,
-			     operands[2], QImode);
-	  emit_move_insn (operands[0], hard_libcall_value(HImode));
-	  DONE;
-#else
-	do_pending_stack_adjust ();
-	emit_insn (gen_tstqi (operands[2]));
-	emit_jump_insn (gen_bne (label1));
-	emit_move_insn (operands[0], operands[1]);
-	emit_jump_insn (gen_jump (label2));
-	emit_barrier ();
-	emit_label (label1);
-
-	if (GET_CODE(operands[2]) != MEM)
-	  {
-	    rtx stack_slot;
-	    
-	    stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode), 0);
-	    stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot, 0));
-	    emit_move_insn (stack_slot, operands[2]);
-	    operands[2] = stack_slot;
-	  }
-
-	emit_insn (gen_match_ashrhi3_nobmu (operands[0], operands[1], operands[2]));
-	emit_label (label2);
-	DONE;
-#endif
-      }
-  }
-}")
-
-(define_insn "match_ashrhi3_bmu"
-  [(set (match_operand:HI 0 "register_operand" "=A,A,A")
-        (ashiftrt:HI (match_operand:HI 1 "register_operand" "A,A,!A")
-                     (match_operand:QI 2 "nonmemory_operand" "B,I,h")))]
-  "TARGET_BMU"
-  "@
-   %0=%1>>%2
-   %0=%1>>%H2
-   %0=%1>>%2"
-  [(set_attr "type" "shift,shift_i,shift")])
-
-(define_insn "match_ashrhi3_nobmu"
-  [(set (match_operand:HI 0 "register_operand" "=A,A")
-        (ashiftrt:HI (match_operand:HI 1 "register_operand" "A,0")
-                     (match_operand:QI 2 "general_operand" "n,m")))]
-  "!TARGET_BMU"
-  "*
-{
-  if (which_alternative == 0)
-    {
-      emit_1600_core_shift (ASHIFTRT, operands, INTVAL(operands[2]));
-      return \"\";
-    }
-  else
-    {
-      output_asm_insn (\"cloop=%2\", operands);
-      output_asm_insn (\"do 0 \{\", operands);
-      output_asm_insn (\"%0=%0>>1\", operands);
-      return \"\}\";
-    }
-}")
-		   
-
-
-;;
-;; Logical Right Shift
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (lshiftrt:HI (match_operand:HI 1 "register_operand" "A")
-                     (const_int 1)))]
-  ""
-  "%0=%1>>1\;%0=%b0&0x7fff"
-  [(set_attr "type" "special")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (lshiftrt:HI (match_operand:HI 1 "register_operand" "A")
-                     (const_int 4)))]
-  ""
-  "%0=%1>>4\;%0=%b0&0x0fff"
-  [(set_attr "type" "special")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (lshiftrt:HI (match_operand:HI 1 "register_operand" "A")
-                     (const_int 8)))]
-  ""
-  "%0=%1>>8\;%0=%b0&0x00ff"
-  [(set_attr "type" "special")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (lshiftrt:HI (match_operand:HI 1 "register_operand" "A")
-                     (const_int 16)))]
-  ""
-  "%0=%1>>16\;%0=%b0&0x0000"
-  [(set_attr "type" "special")])
-
-(define_expand "lshrhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-        (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
-                     (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!TARGET_BMU)
-    {
-      /* If we are shifting by a constant we can do it in 1 or more
-	 1600 core shift instructions. The core instructions can
-	 shift by 1, 4, 8, or 16. */
-      
-      if (GET_CODE(operands[2]) == CONST_INT)
-	emit_insn (gen_match_lshrhi3_nobmu (operands[0], operands[1], operands[2]));	
-      else
-	{
-	  rtx label1 = gen_label_rtx ();
-	  rtx label2 = gen_label_rtx ();
-#if 0
-	  if (!dsp16xx_lshrhi3_libcall)
-	    dsp16xx_lshrhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, LSHRHI3_LIBCALL);
-	  
-	  emit_library_call (dsp16xx_lshrhi3_libcall, 1, HImode, 2,
-			     operands[1], HImode,
-			     operands[2], QImode);
-	  emit_move_insn (operands[0], hard_libcall_value(HImode));
-	  DONE;
-#else
-	  do_pending_stack_adjust ();
-	  emit_insn (gen_tstqi (operands[2]));
-	  emit_jump_insn (gen_bne (label1));
-	  emit_move_insn (operands[0], operands[1]);
-	  emit_jump_insn (gen_jump (label2));
-	  emit_barrier ();
-	  emit_label (label1);
-
-	  if (GET_CODE(operands[2]) != MEM)
-	    {
-	      rtx stack_slot;
-	    
-	      stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode), 0);
-	      stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot, 0));
-	      emit_move_insn (stack_slot, operands[2]);
-	      operands[2] = stack_slot;
-	    }
-
-	  emit_insn (gen_match_lshrhi3_nobmu (operands[0], operands[1], operands[2]));
-	  emit_label (label2);
-	  DONE;
-#endif
-	}
-    }
-}")
-
-(define_insn "match_lshrhi3"
-  [(set (match_operand:HI 0 "register_operand" "=A,A,A")
-        (lshiftrt:HI (match_operand:HI 1 "register_operand" "A,A,!A")
-                     (match_operand:QI 2 "nonmemory_operand" "B,I,h")))]
-  "TARGET_BMU"
-  "@
-   %0=%1>>>%2
-   %0=%1>>>%H2
-   %0=%1>>>%2"
-  [(set_attr "type" "shift,shift_i,shift")])
-
-(define_insn "match_lshrhi3_nobmu"
-  [(set (match_operand:HI 0 "register_operand" "=A,A")
-        (lshiftrt:HI (match_operand:HI 1 "register_operand" "A,0")
-                     (match_operand:QI 2 "general_operand" "n,m")))
-   (clobber (match_scratch:QI 3 "=X,Y"))]
-  "!TARGET_BMU"
-  "*
-{
-  if (which_alternative == 0)
-    {
-      emit_1600_core_shift (LSHIFTRT, operands, INTVAL(operands[2]));
-      return \"\";
-    }
-  else
-    {
-      output_asm_insn (\"%3=psw\;psw=0\",operands);
-      output_asm_insn (\"cloop=%2\", operands);
-      output_asm_insn (\"do 0 \{\", operands);
-      output_asm_insn (\"%0=%0>>1\", operands);
-      output_asm_insn (\"\}\", operands);
-      return \"psw=%3\";
-    }
-}")
-
-
-;;
-;; Arithmetic Left shift
-
-;; Start off with special case arithmetic left shift by 1,4,8 or 16.
-
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (ashift:HI (match_operand:HI 1 "register_operand" "A")
-                   (const_int 1)))]
-  ""
-  "%0=%1<<1"
-  [(set_attr "type" "special")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (ashift:HI (match_operand:HI 1 "register_operand" "A")
-                   (const_int 4)))]
-  ""
-  "%0=%1<<4"
-  [(set_attr "type" "special")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (ashift:HI (match_operand:HI 1 "register_operand" "A")
-                   (const_int 8)))]
-  ""
-  "%0=%1<<8"
-  [(set_attr "type" "special")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-	(ashift:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "A"))
-		   (const_int 16)))]
-  ""
-  "%0=%1<<16"
-  [(set_attr "type" "special")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=A")
-        (ashift:HI (match_operand:HI 1 "general_operand" "A")
-                   (const_int 16)))]
-  ""
-  "%0=%1<<16"
-  [(set_attr "type" "special")])
-
-
-
-;; Normal Arithmetic Shift Left
-
-
-(define_expand "ashlhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-        (ashift:HI (match_operand:HI 1 "register_operand" "")
-                   (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (!TARGET_BMU)
-  {
-      /* If we are shifting by a constant we can do it in 1 or more
-	 1600 core shift instructions. The core instructions can
-	 shift by 1, 4, 8, or 16. */
-      
-      if (GET_CODE(operands[2]) == CONST_INT)
-	;
-      else
-      {
-	rtx label1 = gen_label_rtx ();
-	rtx label2 = gen_label_rtx ();
-#if 0
-	if (!dsp16xx_ashlhi3_libcall)
-	  dsp16xx_ashlhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, ASHLHI3_LIBCALL);
-
-	  emit_library_call (dsp16xx_ashlhi3_libcall, 1, HImode, 2,
-			     operands[1], HImode,
-			     operands[2], QImode);
-	  emit_move_insn (operands[0], hard_libcall_value(HImode));
-	  DONE;
-#else
-	do_pending_stack_adjust ();
-	emit_insn (gen_tstqi (operands[2]));
-	emit_jump_insn (gen_bne (label1));
-	emit_move_insn (operands[0], operands[1]);
-	emit_jump_insn (gen_jump (label2));
-	emit_barrier ();
-	emit_label (label1);
-
-	if (GET_CODE(operands[2]) != MEM)
-	  {
-	    rtx stack_slot;
-	    
-	    stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode), 0);
-	    stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot, 0));
-	    emit_move_insn (stack_slot, operands[2]);
-	    operands[2] = stack_slot;
-	  }
-	emit_insn (gen_match_ashlhi3_nobmu (operands[0], operands[1], operands[2]));
-	emit_label (label2);
-	DONE;
-#endif
-      }
-  }
-}")
-
-(define_insn "match_ashlhi3"
-  [(set (match_operand:HI 0 "register_operand" "=A,A,A")
-        (ashift:HI (match_operand:HI 1 "register_operand" "A,A,A")
-                   (match_operand:QI 2 "nonmemory_operand" "B,I,!h")))]
-  "TARGET_BMU"
-  "@
-   %0=%1<<%2\;move %u0=%u0
-   %0=%1<<%H2\;move %u0=%u0
-   %0=%1<<%2\;move %u0=%u0"
-  [(set_attr "type" "shift,shift_i,shift")])
-
-(define_insn "match_ashlhi3_nobmu"
-  [(set (match_operand:HI 0 "register_operand" "=A,A")
-        (ashift:HI (match_operand:HI 1 "register_operand" "A,0")
-		   (match_operand:QI 2 "general_operand" "n,m")))]
-  "!TARGET_BMU"
-  "*
-{
-  if (which_alternative == 0)
-    {
-      emit_1600_core_shift (ASHIFT, operands, INTVAL(operands[2]));
-      return \"\";
-    }
-  else
-    {
-      output_asm_insn (\"cloop=%2\", operands);
-      output_asm_insn (\"do 0 \{\", operands);
-      output_asm_insn (\"%0=%0<<1\", operands);
-      return \"\}\";
-    }
-}")
-
-
-
-;;
-;; Jump Instructions
-;;
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (match_dup 1)
-	                  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ 
-   if (dsp16xx_compare_gen == gen_compare_reg)
-     operands[1] = (*dsp16xx_compare_gen)(EQ, dsp16xx_compare_op0, dsp16xx_compare_op1);
-   else
-     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
-}")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (match_dup 1)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ 
-   if (dsp16xx_compare_gen == gen_compare_reg)
-     operands[1] = (*dsp16xx_compare_gen)(NE, dsp16xx_compare_op0, dsp16xx_compare_op1);
-   else
-     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
-}")
-
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (match_dup 1)
-	                  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ 
-   if (dsp16xx_compare_gen == gen_compare_reg)
-     operands[1] = (*dsp16xx_compare_gen)(GT, dsp16xx_compare_op0, dsp16xx_compare_op1);
-   else
-     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
-}")
-
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (match_dup 1)
-	                  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ 
-   if (dsp16xx_compare_gen == gen_compare_reg)
-     operands[1] = (*dsp16xx_compare_gen)(GE, dsp16xx_compare_op0, dsp16xx_compare_op1);
-   else
-     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
-}")
-
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (match_dup 1)
-	                  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ 
-   if (dsp16xx_compare_gen == gen_compare_reg)
-     operands[1] = (*dsp16xx_compare_gen)(LT, dsp16xx_compare_op0, dsp16xx_compare_op1);
-   else
-     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
-}")
-
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (match_dup 1)
-	                  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ 
-   if (dsp16xx_compare_gen == gen_compare_reg)
-     operands[1] = (*dsp16xx_compare_gen)(LE, dsp16xx_compare_op0, dsp16xx_compare_op1);
-   else
-     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
-}")
-
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (match_dup 1)
-	                   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ 
-   if (dsp16xx_compare_gen == gen_compare_reg)
-     operands[1] = (*dsp16xx_compare_gen)(GTU, dsp16xx_compare_op0, dsp16xx_compare_op1);
-   else
-     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
-}")
-
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (match_dup 1)
-	                   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ 
-   if (dsp16xx_compare_gen == gen_compare_reg)
-     operands[1] = (*dsp16xx_compare_gen)(GEU, dsp16xx_compare_op0, dsp16xx_compare_op1);
-   else
-     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
-}")
-
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (match_dup 1)
-	                   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ 
-   if (dsp16xx_compare_gen == gen_compare_reg)
-     operands[1] = (*dsp16xx_compare_gen)(LTU, dsp16xx_compare_op0, dsp16xx_compare_op1);
-   else
-     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
-}")
-
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (match_dup 1)
-	                   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ 
-   if (dsp16xx_compare_gen == gen_compare_reg)
-     operands[1] = (*dsp16xx_compare_gen)(LEU, dsp16xx_compare_op0, dsp16xx_compare_op1);
-   else
-     operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
-}")
-
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator" 
-                                      [(cc0) (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  "!TARGET_NEAR_JUMP"
-  "pt=%l0\;if %C1 goto pt"
-  [(set_attr "type" "cond_jump")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator" 
-                                      [(cc0) (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  "TARGET_NEAR_JUMP"
-  "if %C1 goto %l0"
-  [(set_attr "type" "cond_jump")])
-
-;;
-;; Negated conditional jump instructions.
-;; These are necessary because jump optimization can turn
-;; direct-conditional branches into reverse-conditional
-;; branches.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator" 
-                                      [(cc0) (const_int 0)])
-	              (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  "!TARGET_NEAR_JUMP"
-  "pt=%l0\;if %I1 goto pt"
-  [(set_attr "type" "cond_jump")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator" 
-                                      [(cc0) (const_int 0)])
-	              (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  "TARGET_NEAR_JUMP"
-  "if %I1 goto %l0"
-  [(set_attr "type" "cond_jump")])
-
-
-;;
-;; JUMPS
-;;
-
-(define_insn "jump"
-  [(set (pc)
-        (label_ref (match_operand 0 "" "")))]
-  ""
-  "*
-   {
-	if (TARGET_NEAR_JUMP)
-	    return \"goto %l0\";
-        else
-	    return \"pt=%l0\;goto pt\";
-   }"
-   [(set_attr "type" "jump")])
-
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:QI 0 "register_operand" "A"))]
-  ""
-  "pt=%0\;goto pt"
-   [(set_attr "type" "jump")])
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:QI 0 "register_operand" "A"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "pt=%0\;goto pt"
-   [(set_attr "type" "jump")])
-
-;;
-;; FUNCTION CALLS
-;;
-
-;; Call subroutine with no return value.
-
-
-(define_expand "call"
-  [(parallel [(call (match_operand:QI 0 "" "")
-	            (match_operand 1 "" ""))
-	     (clobber (reg:QI 24))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM
-      && ! call_address_operand (XEXP (operands[0], 0), QImode))
-    operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
-			   force_reg (Pmode, XEXP (operands[0], 0)));
-}")
-
-(define_insn ""
-  [(parallel [(call (mem:QI (match_operand:QI 0 "call_address_operand" "hR"))
-	                    (match_operand 1 "" ""))
-	      (clobber (reg:QI 24))])]
-  ""
-  "*
-{
-    if (GET_CODE (operands[0]) == REG || 
-	(GET_CODE(operands[0]) == SYMBOL_REF && !TARGET_NEAR_CALL))
-	return \"pt=%0\;call pt\";
-    else
-        return \"call %0\";
-}"
-[(set_attr "type" "call")])
-
-;; Call subroutine with return value.
-
-(define_expand "call_value"
-  [(parallel [(set (match_operand 0 "register_operand" "=f")
-		  (call (match_operand:QI 1 "call_address_operand" "hR")
-	                (match_operand:QI 2 "" "")))
-	      (clobber (reg:QI 24))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == MEM
-      && ! call_address_operand (XEXP (operands[1], 0), QImode))
-    operands[1] = gen_rtx (MEM, GET_MODE (operands[1]),
-			   force_reg (Pmode, XEXP (operands[1], 0)));
-}")
-
-(define_insn ""
-  [(parallel [(set (match_operand 0 "register_operand" "=f")
-		  (call (mem:QI (match_operand:QI 1 "call_address_operand" "hR"))
-	                        (match_operand:QI 2 "" "")))
-	      (clobber (reg:QI 24))])]
-  ""
-  "*
-{
-    if (GET_CODE (operands[1]) == REG ||
-	(GET_CODE(operands[1]) == SYMBOL_REF && !TARGET_NEAR_CALL))
-	return \"pt=%1\;call pt\";
-    else
-        return \"call %1\";
-}"
-[(set_attr "type" "call")])
-
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-  [(set_attr "type"     "nop")])
-
-;;
-;; PEEPHOLE PATTERNS
-;;
-
-
-(define_peephole
-  [(set (match_operand:QI 0 "register_operand" "=A")
-        (reg:QI 16))
-   (call (mem:QI (match_dup 0))
-	 (match_operand 1 "" "i"))]
-   ""
-   "call pt")
-
-
-(define_peephole
-  [(set (match_operand:QI 0 "register_operand" "=A")
-        (reg:QI 16))
-   (set (match_operand 1 "" "")
-        (call (mem:QI (match_dup 0))
-	      (match_operand 2 "" "i")))]
-   ""
-   "call pt")
-
-(define_peephole
-  [(set (match_operand:HI 0 "register_operand" "=A")
-	(ashift:HI (match_operand:HI 1 "register_operand" "A")
-		   (const_int 16)))
-   (set (match_operand:HI 2 "register_operand" "")
-	(match_dup 0))
-   (set (match_dup 0)
-	(ashiftrt:HI (match_dup 0) (const_int 16)))
-   (set (match_dup 2)
-	(match_dup 0))]
-  ""
-  "%0=%1<<16\;%0=%0>>16\;%u2=%u0\;%w2=%w0")
-
-(define_peephole
-  [(set (match_operand:HI 0 "register_operand" "=A")
-	(ashift:HI (match_operand:HI 1 "register_operand" "A")
-		   (const_int 16)))
-   (set (match_operand:HI 2 "register_operand" "")
-	(match_dup 0))
-   (set (match_dup 0)
-	(lshiftrt:HI (match_dup 0) (const_int 16)))
-   (set (match_dup 2)
-	(match_dup 0))]
-  ""
-  "%0=%1<<16\;%0=%0>>16\;%0=%b0&0x0000\;%u2=%u0\;%w2=%w0")
diff --git a/gcc/config/dsp16xx/xm-dsp16xx.h b/gcc/config/dsp16xx/xm-dsp16xx.h
deleted file mode 100755
index 00f86b4..0000000
--- a/gcc/config/dsp16xx/xm-dsp16xx.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Configuration file for GNU CC for AT&T DSP1600.
-   Copyright (C) 1993 Free Software Foundation, Inc.
-   Contributed by Michael Collison (collison@world.std.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 16
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* If compiled with GNU C, use the built-in alloca */
-#ifdef __GNUC__
-#define alloca __builtin_alloca
-#else
-#define USE_C_ALLOCA
-#endif
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
diff --git a/gcc/config/elfos.h b/gcc/config/elfos.h
deleted file mode 100755
index a149ab1..0000000
--- a/gcc/config/elfos.h
+++ /dev/null
@@ -1,754 +0,0 @@
-/* elfos.h  --  operating system specific defines to be used when
-   targeting GCC for some generic ELF system
-   Copyright (C) 1991, 1994, 1995 Free Software Foundation, Inc.
-   Based on svr4.h contributed by Ron Guilmette (rfg@netcom.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* For the sake of libgcc2.c, indicate target supports atexit.  */
-#define HAVE_ATEXIT
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s"
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared: \
-			 %{!symbolic: \
-			  %{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}}\
-			crtbegin.o%s"
-
-/* Attach a special .ident directive to the end of the file to identify
-   the version of GCC which compiled this code.  The format of the
-   .ident string is patterned after the ones produced by native svr4
-   C compilers.  */
-
-#define IDENT_ASM_OP ".ident"
-
-#define ASM_FILE_END(FILE)					\
-do {				 				\
-     fprintf ((FILE), "\t%s\t\"GCC: (GNU) %s\"\n",		\
-	      IDENT_ASM_OP, version_string);			\
-   } while (0)
-
-/* Output #ident as a .ident.  */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
-
-/* Use periods rather than dollar signs in special g++ assembler names.  */
-
-#define NO_DOLLAR_IN_LABEL
-
-/* Writing `int' for a bitfield forces int alignment for the structure.  */
-
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Implicit library calls should use memcpy, not bcopy, etc.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Handle #pragma weak and #pragma pack.  */
-
-#define HANDLE_SYSV_PRAGMA
-
-/* System V Release 4 uses DWARF debugging info.  */
-
-#define DWARF_DEBUGGING_INFO
-
-/* All ELF targets can support DWARF-2.  */
-
-#define DWARF2_DEBUGGING_INFO
-
-/* gas on SVR4 supports the use of .stabs.  Permit -gstabs to be used
-   in general, although it will only work when using gas.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* The GNU tools operate better with stabs.  Since we don't have
-   any native tools to be compatible with, default to stabs.  */
-
-#ifndef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-#endif
-
-/* Make LBRAC and RBRAC addresses relative to the start of the
-   function.  The native Solaris stabs debugging format works this
-   way, gdb expects it, and it reduces the number of relocation
-   entries.  */
-
-#define DBX_BLOCKS_FUNCTION_RELATIVE 1
-
-/* When using stabs, gcc2_compiled must be a stabs entry, not an
-   ordinary symbol, or gdb won't see it.  Furthermore, since gdb reads
-   the input piecemeal, starting with each N_SO, it's a lot easier if
-   the gcc2 flag symbol is *after* the N_SO rather than before it.  So
-   we emit an N_OPT stab there.  */
-
-#define ASM_IDENTIFY_GCC(FILE)						\
-do									\
-  {									\
-    if (write_symbols != DBX_DEBUG)					\
-      fputs ("gcc2_compiled.:\n", FILE);				\
-  }									\
-while (0)
-
-#define ASM_IDENTIFY_GCC_AFTER_SOURCE(FILE)				\
-do									\
-  {									\
-    if (write_symbols == DBX_DEBUG)					\
-      fputs ("\t.stabs\t\"gcc2_compiled.\", 0x3c, 0, 0, 0\n", FILE);	\
-  }									\
-while (0)
-
-/* Like block addresses, stabs line numbers are relative to the
-   current function.  */
-
-#undef  ASM_OUTPUT_SOURCE_LINE
-#define ASM_OUTPUT_SOURCE_LINE(file, line)				\
-do									\
-  {									\
-    static int sym_lineno = 1;						\
-    fprintf (file, "\t.stabn 68,0,%d,.LM%d-",				\
-	     line, sym_lineno);						\
-    assemble_name (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
-    fprintf (file, "\n.LM%d:\n", sym_lineno);				\
-    sym_lineno += 1;							\
-  }									\
-while (0)
-
-/* In order for relative line numbers to work, we must output the
-   stabs entry for the function name first.  */
-
-#define DBX_FUNCTION_FIRST
-
-#undef ASM_BYTE_OP
-#define ASM_BYTE_OP	".byte"
-
-#undef SET_ASM_OP
-#define SET_ASM_OP	".set"
-
-/* This is how to begin an assembly language file.  Most svr4 assemblers want
-   at least a .file directive to come first, and some want to see a .version
-   directive come right after that.  Here we just establish a default
-   which generates only the .file directive.  If you need a .version
-   directive for any specific target, you should override this definition
-   in the target-specific file which includes this one.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)                                    \
-  output_file_directive ((FILE), main_input_filename)
-
-/* This is how to allocate empty space in some section.  The .zero
-   pseudo-op is used for this on most svr4 assemblers.  */
-
-#define SKIP_ASM_OP	".zero"
-
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
-  fprintf (FILE, "\t%s\t%u\n", SKIP_ASM_OP, (SIZE))
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.
-
-   For System V Release 4 the convention is *not* to prepend a leading
-   underscore onto user-level symbol names.  */
-
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "%s", NAME)
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-
-   For most svr4 systems, the convention is that any symbol which begins
-   with a period is not put into the linker symbol table by the assembler.  */
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM)			\
-do {									\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM);				\
-} while (0)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.
-
-   For most svr4 systems, the convention is that any symbol which begins
-   with a period is not put into the linker symbol table by the assembler.  */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)			\
-do {									\
-  sprintf (LABEL, "*.%s%d", PREFIX, NUM);				\
-} while (0)
-
-/* Output the label which precedes a jumptable.  Note that for all svr4
-   systems where we actually generate jumptables (which is to say every
-   svr4 target except i386, where we use casesi instead) we put the jump-
-   tables into the .rodata section and since other stuff could have been
-   put into the .rodata section prior to any given jumptable, we have to
-   make sure that the location counter for the .rodata section gets pro-
-   perly re-aligned prior to the actual beginning of the jump table.  */
-
-#define ALIGN_ASM_OP ".align"
-
-#ifndef ASM_OUTPUT_BEFORE_CASE_LABEL
-#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
-  ASM_OUTPUT_ALIGN ((FILE), 2);
-#endif
-
-#undef ASM_OUTPUT_CASE_LABEL
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,JUMPTABLE)		\
-  do {									\
-    ASM_OUTPUT_BEFORE_CASE_LABEL (FILE, PREFIX, NUM, JUMPTABLE)		\
-    ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM);			\
-  } while (0)
-
-/* The standard SVR4 assembler seems to require that certain builtin
-   library routines (e.g. .udiv) be explicitly declared as .globl
-   in each assembly file where they are referenced.  */
-
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN)				\
-  ASM_GLOBALIZE_LABEL (FILE, XSTR (FUN, 0))
-
-/* This says how to output assembler code to declare an
-   uninitialized external linkage data object.  Under SVR4,
-   the linker seems to want the alignment of data objects
-   to depend on their types.  We do exactly that here.  */
-
-#define COMMON_ASM_OP	".comm"
-
-#undef ASM_OUTPUT_ALIGNED_COMMON
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fprintf ((FILE), "\t%s\t", COMMON_ASM_OP);				\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
-} while (0)
-
-/* This says how to output assembler code to declare an
-   uninitialized internal linkage data object.  Under SVR4,
-   the linker seems to want the alignment of data objects
-   to depend on their types.  We do exactly that here.  */
-
-#define LOCAL_ASM_OP	".local"
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fprintf ((FILE), "\t%s\t", LOCAL_ASM_OP);				\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), "\n");						\
-  ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);			\
-} while (0)
-
-/* This is the pseudo-op used to generate a 32-bit word of data with a
-   specific value in some section.  This is the same for all known svr4
-   assemblers.  */
-
-#define INT_ASM_OP		".long"
-
-/* This is the pseudo-op used to generate a contiguous sequence of byte
-   values from a double-quoted string WITHOUT HAVING A TERMINATING NUL
-   AUTOMATICALLY APPENDED.  This is the same for most svr4 assemblers.  */
-
-#undef ASCII_DATA_ASM_OP
-#define ASCII_DATA_ASM_OP	".ascii"
-
-/* Support const sections and the ctors and dtors sections for g++.
-   Note that there appears to be two different ways to support const
-   sections at the moment.  You can either #define the symbol
-   READONLY_DATA_SECTION (giving it some code which switches to the
-   readonly data section) or else you can #define the symbols
-   EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
-   SELECT_RTX_SECTION.  We do both here just to be on the safe side.  */
-
-#define USE_CONST_SECTION	1
-
-#define CONST_SECTION_ASM_OP	".section\t.rodata"
-
-/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
-
-   Note that we want to give these sections the SHF_WRITE attribute
-   because these sections will actually contain data (i.e. tables of
-   addresses of functions in the current root executable or shared library
-   file) and, in the case of a shared library, the relocatable addresses
-   will have to be properly resolved/relocated (and then written into) by
-   the dynamic linker when it actually attaches the given shared library
-   to the executing process.  (Note that on SVR4, you may wish to use the
-   `-z text' option to the ELF linker, when building a shared library, as
-   an additional check that you are doing everything right.  But if you do
-   use the `-z text' option when building a shared library, you will get
-   errors unless the .ctors and .dtors sections are marked as writable
-   via the SHF_WRITE attribute.)  */
-
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"aw\""
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"aw\""
-
-/* On svr4, we *do* have support for the .init and .fini sections, and we
-   can put stuff in there to be executed before and after `main'.  We let
-   crtstuff.c and other files know this by defining the following symbols.
-   The definitions say how to change sections to the .init and .fini
-   sections.  This is the same for all known svr4 assemblers.  */
-
-#define INIT_SECTION_ASM_OP	".section\t.init"
-#define FINI_SECTION_ASM_OP	".section\t.fini"
-
-/* A default list of other sections which we might be "in" at any given
-   time.  For targets that use additional sections (e.g. .tdesc) you
-   should override this definition in the target-specific file which
-   includes this file.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_ctors, in_dtors
-
-/* A default list of extra section function definitions.  For targets
-   that use additional sections (e.g. .tdesc) you should override this
-   definition in the target-specific file which includes this file.  */
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CONST_SECTION_FUNCTION						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-#define READONLY_DATA_SECTION() const_section ()
-
-extern void text_section ();
-
-#define CONST_SECTION_FUNCTION						\
-void									\
-const_section ()							\
-{									\
-  if (!USE_CONST_SECTION)						\
-    text_section();							\
-  else if (in_section != in_const)					\
-    {									\
-      fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP);		\
-      in_section = in_const;						\
-    }									\
-}
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-/* Switch into a generic section.
-   This is currently only used to support section attributes.  */
-
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC)		\
-do {									\
-  static struct section_info						\
-    {									\
-      struct section_info *next;				        \
-      char *name;						        \
-      enum sect_enum {SECT_RW, SECT_RO, SECT_EXEC} type;		\
-    } *sections;							\
-  struct section_info *s;						\
-  char *mode;								\
-  enum sect_enum type;							\
-									\
-  for (s = sections; s; s = s->next)					\
-    if (!strcmp (NAME, s->name))					\
-      break;								\
-									\
-  if (DECL && TREE_CODE (DECL) == FUNCTION_DECL)			\
-    type = SECT_EXEC, mode = "ax";					\
-  else if (DECL && DECL_READONLY_SECTION (DECL, RELOC))			\
-    type = SECT_RO, mode = "a";						\
-  else									\
-    type = SECT_RW, mode = "aw";					\
-									\
-  if (s == 0)								\
-    {									\
-      s = (struct section_info *) xmalloc (sizeof (struct section_info));  \
-      s->name = xmalloc ((strlen (NAME) + 1) * sizeof (*NAME));		\
-      strcpy (s->name, NAME);						\
-      s->type = type;							\
-      s->next = sections;						\
-      sections = s;							\
-      fprintf (FILE, ".section\t%s,\"%s\",@progbits\n", NAME, mode);	\
-    }									\
-  else									\
-    {									\
-      if (DECL && s->type != type)					\
-	error_with_decl (DECL, "%s causes a section type conflict");	\
-									\
-      fprintf (FILE, ".section\t%s\n", NAME);				\
-    }									\
-} while (0)
-
-#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
-#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
-#define UNIQUE_SECTION(DECL,RELOC)				\
-do {								\
-  int len;							\
-  char *name, *string, *prefix;					\
-								\
-  name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL));	\
-								\
-  if (! DECL_ONE_ONLY (DECL))					\
-    {								\
-      if (TREE_CODE (DECL) == FUNCTION_DECL)			\
-	prefix = ".text.";					\
-      else if (DECL_READONLY_SECTION (DECL, RELOC))		\
-	prefix = ".rodata.";					\
-      else							\
-	prefix = ".data.";					\
-    }								\
-  else if (TREE_CODE (DECL) == FUNCTION_DECL)			\
-    prefix = ".gnu.linkonce.t.";				\
-  else if (DECL_READONLY_SECTION (DECL, RELOC))			\
-    prefix = ".gnu.linkonce.r.";				\
-  else								\
-    prefix = ".gnu.linkonce.d.";				\
-								\
-  len = strlen (name) + strlen (prefix);			\
-  string = alloca (len + 1);					\
-  sprintf (string, "%s%s", prefix, name);			\
-								\
-  DECL_SECTION_NAME (DECL) = build_string (len, string);	\
-} while (0)
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement or statements to switch to the appropriate
-   section for output of DECL.  DECL is either a `VAR_DECL' node
-   or a constant of some sort.  RELOC indicates whether forming
-   the initial value of DECL requires link-time relocations.  */
-
-#define SELECT_SECTION(DECL,RELOC)					\
-{									\
-  if (TREE_CODE (DECL) == STRING_CST)					\
-    {									\
-      if (! flag_writable_strings)					\
-	const_section ();						\
-      else								\
-	data_section ();						\
-    }									\
-  else if (TREE_CODE (DECL) == VAR_DECL)				\
-    {									\
-      if ((flag_pic && RELOC)						\
-	  || !TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)		\
-	  || !DECL_INITIAL (DECL)					\
-	  || (DECL_INITIAL (DECL) != error_mark_node			\
-	      && !TREE_CONSTANT (DECL_INITIAL (DECL))))			\
-	data_section ();						\
-      else								\
-	const_section ();						\
-    }									\
-  else									\
-    const_section ();							\
-}
-
-/* A C statement or statements to switch to the appropriate
-   section for output of RTX in mode MODE.  RTX is some kind
-   of constant in RTL.  The argument MODE is redundant except
-   in the case of a `const_int' rtx.  Currently, these always
-   go into the const section.  */
-
-#undef SELECT_RTX_SECTION
-#define SELECT_RTX_SECTION(MODE,RTX) const_section()
-
-/* Define the strings used for the special svr4 .type and .size directives.
-   These strings generally do not vary from one system running svr4 to
-   another, but if a given system (e.g. m88k running svr) needs to use
-   different pseudo-op names for these, they may be overridden in the
-   file which includes this one.  */
-
-#define TYPE_ASM_OP	".type"
-#define SIZE_ASM_OP	".size"
-
-/* This is how we tell the assembler that a symbol is weak.  */
-
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
-  do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \
-       fputc ('\n', FILE); } while (0)
-
-/* The following macro defines the format used to output the second
-   operand of the .type assembler directive.  Different svr4 assemblers
-   expect various different forms for this operand.  The one given here
-   is just a default.  You may need to override it in your machine-
-   specific tm.h file (depending upon the particulars of your assembler).  */
-
-#define TYPE_OPERAND_FMT	"@%s"
-
-/* Write the extra assembler code needed to declare a function's result.
-   Most svr4 assemblers don't require any special declaration of the
-   result value, but there are exceptions.  */
-
-#ifndef ASM_DECLARE_RESULT
-#define ASM_DECLARE_RESULT(FILE, RESULT)
-#endif
-
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare a function properly.
-   Some svr4 assemblers need to also have something extra said about the
-   function's return value.  We allow for that here.  */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "function");			\
-    putc ('\n', FILE);							\
-    ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));			\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Write the extra assembler code needed to declare an object properly.  */
-
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
-    putc ('\n', FILE);							\
-    size_directive_output = 0;						\
-    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-      {									\
-	size_directive_output = 1;					\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-	fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));	\
-      }									\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
-	 assemble_name (FILE, name);					 \
-	 fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL))); \
-       }								 \
-   } while (0)
-
-/* This is how to declare the size of a function.  */
-
-#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)			\
-  do {									\
-    if (!flag_inhibit_size_directive)					\
-      {									\
-        char label[256];						\
-	static int labelno;						\
-	labelno++;							\
-	ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno);		\
-	ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno);		\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, (FNAME));					\
-        fprintf (FILE, ",");						\
-	assemble_name (FILE, label);					\
-        fprintf (FILE, "-");						\
-	assemble_name (FILE, (FNAME));					\
-	putc ('\n', FILE);						\
-      }									\
-  } while (0)
-
-/* A table of bytes codes used by the ASM_OUTPUT_ASCII and
-   ASM_OUTPUT_LIMITED_STRING macros.  Each byte in the table
-   corresponds to a particular byte value [0..255].  For any
-   given byte value, if the value in the corresponding table
-   position is zero, the given character can be output directly.
-   If the table value is 1, the byte must be output as a \ooo
-   octal escape.  If the tables value is anything else, then the
-   byte value should be output as a \ followed by the value
-   in the table.  Note that we can use standard UN*X escape
-   sequences for many control characters, but we don't use
-   \a to represent BEL because some svr4 assemblers (e.g. on
-   the i386) don't know about that.  Also, we don't use \v
-   since some versions of gas, such as 2.2 did not accept it.  */
-
-#define ESCAPES \
-"\1\1\1\1\1\1\1\1btn\1fr\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\0\0\"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
-\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\\\0\0\0\
-\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1"
-
-/* Some svr4 assemblers have a limit on the number of characters which
-   can appear in the operand of a .string directive.  If your assembler
-   has such a limitation, you should define STRING_LIMIT to reflect that
-   limit.  Note that at least some svr4 assemblers have a limit on the
-   actual number of bytes in the double-quoted string, and that they
-   count each character in an escape sequence as one byte.  Thus, an
-   escape sequence like \377 would count as four bytes.
-
-   If your target assembler doesn't support the .string directive, you
-   should define this to zero.
-*/
-
-#define STRING_LIMIT	((unsigned) 256)
-
-#define STRING_ASM_OP	".string"
-
-/* The routine used to output NUL terminated strings.  We use a special
-   version of this for most svr4 targets because doing so makes the
-   generated assembly code more compact (and thus faster to assemble)
-   as well as more readable, especially for targets like the i386
-   (where the only alternative is to output character sequences as
-   comma separated lists of numbers).   */
-
-#define ASM_OUTPUT_LIMITED_STRING(FILE, STR)				\
-  do									\
-    {									\
-      register unsigned char *_limited_str = (unsigned char *) (STR);	\
-      register unsigned ch;						\
-      fprintf ((FILE), "\t%s\t\"", STRING_ASM_OP);			\
-      for (; ch = *_limited_str; _limited_str++)			\
-        {								\
-	  register int escape;						\
-	  switch (escape = ESCAPES[ch])					\
-	    {								\
-	    case 0:							\
-	      putc (ch, (FILE));					\
-	      break;							\
-	    case 1:							\
-	      fprintf ((FILE), "\\%03o", ch);				\
-	      break;							\
-	    default:							\
-	      putc ('\\', (FILE));					\
-	      putc (escape, (FILE));					\
-	      break;							\
-	    }								\
-        }								\
-      fprintf ((FILE), "\"\n");						\
-    }									\
-  while (0)
-
-/* The routine used to output sequences of byte values.  We use a special
-   version of this for most svr4 targets because doing so makes the
-   generated assembly code more compact (and thus faster to assemble)
-   as well as more readable.  Note that if we find subparts of the
-   character sequence which end with NUL (and which are shorter than
-   STRING_LIMIT) we output those using ASM_OUTPUT_LIMITED_STRING.  */
-
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH)				\
-  do									\
-    {									\
-      register unsigned char *_ascii_bytes = (unsigned char *) (STR);	\
-      register unsigned char *limit = _ascii_bytes + (LENGTH);		\
-      register unsigned bytes_in_chunk = 0;				\
-      for (; _ascii_bytes < limit; _ascii_bytes++)			\
-        {								\
-	  register unsigned char *p;					\
-	  if (bytes_in_chunk >= 60)					\
-	    {								\
-	      fprintf ((FILE), "\"\n");					\
-	      bytes_in_chunk = 0;					\
-	    }								\
-	  for (p = _ascii_bytes; p < limit && *p != '\0'; p++)		\
-	    continue;							\
-	  if (p < limit && (p - _ascii_bytes) <= STRING_LIMIT)		\
-	    {								\
-	      if (bytes_in_chunk > 0)					\
-		{							\
-		  fprintf ((FILE), "\"\n");				\
-		  bytes_in_chunk = 0;					\
-		}							\
-	      ASM_OUTPUT_LIMITED_STRING ((FILE), _ascii_bytes);		\
-	      _ascii_bytes = p;						\
-	    }								\
-	  else								\
-	    {								\
-	      register int escape;					\
-	      register unsigned ch;					\
-	      if (bytes_in_chunk == 0)					\
-		fprintf ((FILE), "\t%s\t\"", ASCII_DATA_ASM_OP);	\
-	      switch (escape = ESCAPES[ch = *_ascii_bytes])		\
-		{							\
-		case 0:							\
-		  putc (ch, (FILE));					\
-		  bytes_in_chunk++;					\
-		  break;						\
-		case 1:							\
-		  fprintf ((FILE), "\\%03o", ch);			\
-		  bytes_in_chunk += 4;					\
-		  break;						\
-		default:						\
-		  putc ('\\', (FILE));					\
-		  putc (escape, (FILE));				\
-		  bytes_in_chunk += 2;					\
-		  break;						\
-		}							\
-	    }								\
-	}								\
-      if (bytes_in_chunk > 0)						\
-        fprintf ((FILE), "\"\n");					\
-    }									\
-  while (0)
-
-/* All SVR4 targets use the ELF object file format.  */
-#define OBJECT_FORMAT_ELF
diff --git a/gcc/config/elxsi/elxsi.c b/gcc/config/elxsi/elxsi.c
deleted file mode 100755
index b881853..0000000
--- a/gcc/config/elxsi/elxsi.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Subroutines for insn-output.c for GNU compiler.  Elxsi version.
-   Copyright (C) 1987, 1992, 1997 Free Software Foundation, Inc
-   This port, done by Mike Stump <mrs@cygnus.com> in 1988, and is the first
-   64 bit port of GNU CC.
-   Based upon the VAX port.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-
-extern char *reg_names[];
-rtx cmp_op0=0, cmp_op1=0;
-
-/* table of relations for compares and branches */
-char *cmp_tab[] = {
-    "gt", "gt", "eq", "eq", "ge", "ge", "lt", "lt", "ne", "ne",
-    "le", "le" };
-
-/* type is the index into the above table */
-/* s is "" for signed, or "u" for unsigned */
-char *cmp_jmp(s, type, where) char *s; rtx where; {
-    rtx br_ops[3];
-    char template[50];
-    char *f = "";
-    char *bits = "64";
-    if (GET_MODE (cmp_op0) == SFmode) f = "f", bits = "32";
-    if (GET_MODE (cmp_op0) == DFmode) f = "f";
-    br_ops[0] = where;
-    br_ops[1] = cmp_op0;
-    br_ops[2] = cmp_op1;
-    if (cmp_op1)
-	sprintf(template, "%scmp%s.br.%s\t%%1,%%2:j%s\t%%l0",
-		f, s, bits, cmp_tab[type]);
-    else if (*f)
-	sprintf(template, "fcmp.br.%s\t%%1,=0:j%s\t%%l0",
-		bits, cmp_tab[type]);
-    else if (*s) /* can turn the below in to a jmp ... */
-	sprintf(template, "cmpu.br.64\t%%1,=0:j%s\t%%l0", s, cmp_tab[type]);
-    else
-	sprintf(template, "jmp.%s\t%%1,%%l0", cmp_tab[type+1]);
-    output_asm_insn(template, br_ops);
-    return "";
-}
-
-char *cmp_set(s, type, reg) char *s, *type; rtx reg; {
-    rtx br_ops[3];
-    char template[50];
-    char *f = "";
-    char *bits = "64";
-    if (GET_MODE (cmp_op0) == SFmode) f = "f", bits = "32";
-    else if (GET_MODE (cmp_op0) == DFmode) f = "f";
-    else if (GET_MODE (cmp_op0) == SImode) bits = "32";
-    else if (GET_MODE (cmp_op0) == HImode) bits = "16";
-    else if (GET_MODE (cmp_op0) == QImode) bits = "8";
-    br_ops[0] = reg;
-    br_ops[1] = cmp_op0;
-    br_ops[2] = cmp_op1;
-    if (cmp_op1)
-	sprintf(template, "%scmp%s.%s\t%%0,%%1,%%2:%s",
-		f, s, bits, type);
-    else
-	sprintf(template, "%scmp%s.%s\t%%0,%%1,=0:%s",
-		f, s, bits, type);
-    output_asm_insn(template, br_ops);
-    return "";
-}
-
-print_operand_address (file, addr)
-     FILE *file;
-     register rtx addr;
-{
-  register rtx reg1, reg2, breg, ireg;
-  rtx offset;
-
- retry:
-  switch (GET_CODE (addr))
-    {
-
-    case MEM:
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-        fprintf (file, "%s", reg_names[REGNO (addr)]);
-      else abort();
-      break;
-
-    case REG:
-      fprintf (file, "[%s]", reg_names[REGNO (addr)]);
-      break;
-
-    case PLUS:
-      reg1 = 0;	reg2 = 0;
-      ireg = 0;	breg = 0;
-      offset = 0;
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-	{
-	  offset = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	{
-	  offset = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
-	}
-      fprintf (file, "[%s]", reg_names[REGNO (addr)]);
-      output_address (offset);
-      break;
-
-    default:
-      output_addr_const (file, addr);
-    }
-}
diff --git a/gcc/config/elxsi/elxsi.h b/gcc/config/elxsi/elxsi.h
deleted file mode 100755
index 6e8da32..0000000
--- a/gcc/config/elxsi/elxsi.h
+++ /dev/null
@@ -1,967 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Elxsi version.
-   Copyright (C) 1987, 1988, 1992, 1995, 1996 Free Software Foundation, Inc.
-   This port, contributed by Mike Stump <mrs@cygnus.com> in 1988, is the first
-   64 bit port of GNU CC.
-   Based upon the VAX port.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Delxsi -Dunix -Asystem(unix) -Acpu(elxsi) -Amachine(elxsi)"
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fprintf (stderr, " (elxsi)");
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Nonzero if compiling code that Unix assembler can assemble.  */
-#define TARGET_UNIX_ASM (target_flags & 1)
-
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  { {"unix", 1},  \
-    {"embos", -1},  \
-    { "", TARGET_DEFAULT}}
-
-/* Default target_flags if no switches specified.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 1
-#endif
-
-/* Target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is not true on the vax.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is numbered.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 64
-#define Rmode DImode
-
-#define INT_TYPE_SIZE 32
-
-#define LONG_TYPE_SIZE 32
-
-#define LONG_LONG_TYPE_SIZE 64
-
-#define FLOAT_TYPE_SIZE 32
-
-#define DOUBLE_TYPE_SIZE 64
-
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 8
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing pointers in memory.  */
-#define POINTER_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 8
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 8
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 32
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 32
-
-/* Define this if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 0
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  */
-#define FIRST_PSEUDO_REGISTER 16
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   On the elxsi, these is the .r15 (aka .sp).  */
-#define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS {1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-   On the vax, all registers are one word long.  */
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2)  1
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 15
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 14
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 0
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)			\
-{ int regno;							\
-  int offset = 0;						\
-  for( regno=0; regno < FIRST_PSEUDO_REGISTER;  regno++ )	\
-    if( regs_ever_live[regno] && !call_used_regs[regno] )	\
-      offset += 8;						\
-  (DEPTH) = (offset + ((get_frame_size() + 3) & ~3) );		\
-  (DEPTH) = 0;							\
-}
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 14
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 0
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 1
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-/* The vax has only one kind of registers, so NO_REGS and ALL_REGS
-   are the only classes.  */
-
-enum reg_class { NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "GENERAL_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS {0, 0x07fff, 0xffff}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) (REGNO == 15 ? ALL_REGS : GENERAL_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) NO_REGS
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
-    ((C) == 'I' ? (VALUE) >=-16 && (VALUE) <=15 : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)  (CLASS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-/* On the vax, this is always the size of MODE in words,
-   since all registers are the same size.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET -4
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 4
-
-/* Value is 1 if returning from a function call automatically
-   pops the arguments described by the number-of-args field in the call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-
-   On the Vax, the RET insn always pops all the args for any function.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-/* On the Vax the return value is in R0 regardless.  */   
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-/* On the Vax the return value is in R0 regardless.  */   
-
-#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, 0)
-
-/* Define this if PCC uses the nonreentrant convention for returning
-   structure and union values.  */
-
-#define PCC_STATIC_STRUCT_RETURN
-
-/* 1 if N is a possible register number for a function value.
-   On the Vax, R0 is the only register thus used.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-/* 1 if N is a possible register number for function argument passing.
-   On the Vax, no registers are used in this way.  */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the vax, this is a single integer, which is a number of bytes
-   of arguments scanned so far.  */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the vax, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,x,INDIRECT)	\
- ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM) += ((MODE) != BLKmode			\
-	    ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
-	    : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On the vax all args are pushed.  */   
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)					\
-{ register int regno;							\
-  register int cnt = 0;							\
-  extern char call_used_regs[];						\
-  /* the below two lines are a HACK, and should be deleted, but 	\
-     for now are very much needed (1.35) */				\
-  if (frame_pointer_needed)						\
-    regs_ever_live[14]=1, call_used_regs[14]=0;				\
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)		\
-    if (regs_ever_live[regno] && !call_used_regs[regno])		\
-	cnt+=8;								\
-  if ((SIZE)+cnt)							\
-    fprintf (FILE, "\tadd.64\t.sp,=%d\n", -(SIZE)-cnt);			\
-  cnt = 0;								\
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)		\
-    if (regs_ever_live[regno] && !call_used_regs[regno])		\
-      fprintf (FILE, "\tst.64\t.r%d,[.sp]%d\n", regno, (cnt+=8)-12); 	\
-  if (frame_pointer_needed)						\
-    fprintf (FILE, "\tadd.64\t.r14,.sp,=%d\n", (SIZE)+cnt);		\
-}
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   fprintf (FILE, "\tld.64\t.r0,.LP%d\n\tcall\tmcount\n", (LABELNO));
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 0
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE)					\
-{ register int regno;							\
-  register int cnt = 0;							\
-  extern char call_used_regs[];						\
-  extern int current_function_calls_alloca;						\
-  /* this conditional is ONLY here because there is a BUG;		\
-	     EXIT_IGNORE_STACK is ignored itself when the first part of		\
-	     the condition is true! (at least in version 1.35) */		\
-  /* the 8*10 is for 64 bits of .r5 - .r14 */				\
-  if (current_function_calls_alloca || (SIZE)>=(256-8*10)) {		\
-    /* use .r4 as a temporary! Ok for now.... */			\
-    fprintf (FILE, "\tld.64\t.r4,.r14\n");				\
-    for (regno = FIRST_PSEUDO_REGISTER-1; regno >= 0; --regno)		\
-      if (regs_ever_live[regno] && !call_used_regs[regno])		\
-       	cnt+=8;								\
-    for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)		\
-      if (regs_ever_live[regno] && !call_used_regs[regno])		\
-       fprintf (FILE, "\tld.64\t.r%d,[.r14]%d\n", regno,		\
-		-((cnt-=8) + 8)-4-(SIZE));				\
-    fprintf (FILE, "\tld.64\t.sp,.r4\n\texit\t0\n");			\
-  } else {								\
-    for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)		\
-      if (regs_ever_live[regno] && !call_used_regs[regno])		\
-         fprintf (FILE, "\tld.64\t.r%d,[.sp]%d\n", regno, (cnt+=8)-12);	\
-    fprintf (FILE, "\texit\t%d\n", (SIZE)+cnt);				\
-  } }
-
-/* If the memory address ADDR is relative to the frame pointer,
-   correct it to be relative to the stack pointer instead.
-   This is for when we don't use a frame pointer.
-   ADDR should be a variable name.  */
-
-#define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \
-{ int offset = -1;							\
-  rtx regs = stack_pointer_rtx;						\
-  if (ADDR == frame_pointer_rtx)					\
-    offset = 0;								\
-  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx \
-	   && GET_CODE (XEXP (ADDR, 0)) == CONST_INT)			\
-    offset = INTVAL (XEXP (ADDR, 0));					\
-  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
-	   && GET_CODE (XEXP (ADDR, 1)) == CONST_INT)			\
-    offset = INTVAL (XEXP (ADDR, 1));					\
-  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
-    { rtx other_reg = XEXP (ADDR, 1);					\
-      offset = 0;							\
-      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }	\
-  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
-    { rtx other_reg = XEXP (ADDR, 0);					\
-      offset = 0;							\
-      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }	\
-  if (offset >= 0)							\
-    { int regno;							\
-      extern char call_used_regs[];					\
-      offset += 4; /* I don't know why??? */				\
-      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)		\
-        if (regs_ever_live[regno] && ! call_used_regs[regno])		\
-          offset += 8;							\
-      ADDR = plus_constant (regs, offset + (DEPTH)); } }
-
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(regno)  \
-((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
-#define REGNO_OK_FOR_BASE_P(regno) \
-((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* 1 if X is an rtx for a constant that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) \
-    (GET_CODE (X) != CONST_DOUBLE)
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) 1
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) 1
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   CONSTANT_ADDRESS_P is actually machine-independent.  */
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
-{ 									\
-  if (GET_CODE (X) == REG) goto ADDR;					\
-  if (CONSTANT_ADDRESS_P (X)) goto ADDR; 				\
-  if (GET_CODE (X) == PLUS)						\
-    {									\
-      /* Handle [index]<address> represented with index-sum outermost */\
-      if (GET_CODE (XEXP (X, 0)) == REG					\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
-	  && GET_CODE (XEXP (X, 1)) == CONST_INT)			\
-	goto ADDR;							\
-      if (GET_CODE (XEXP (X, 1)) == REG					\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
-	  && GET_CODE (XEXP (X, 0)) == CONST_INT)			\
-	goto ADDR;							\
-    }									\
- }
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the vax, nothing needs to be done.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)  {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for. */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.  */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 8
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    /* Constant zero is super cheap due to clr instruction.  */	\
-    if (RTX == const0_rtx) return 0;				\
-    if ((unsigned) INTVAL (RTX) < 077) return 1;		\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 3;							\
-  case CONST_DOUBLE:						\
-    return 5;
-
-/*
- * We can use the BSD C library routines for the gnulib calls that are
- * still generated, since that's what they boil down to anyways.
- */
-
-/* #define UDIVSI3_LIBCALL "*udiv" */
-/* #define UMODSI3_LIBCALL "*urem" */
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  No extra ones are needed for the vax.  */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-	CC_STATUS_INIT;
-
-
-/* Control the assembler format that we output.  */
-
-/* Output the name of the file we are compiling.  */
-#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
-  do {	fprintf (STREAM, "\t.file\t");			\
-	output_quoted_string (STREAM, NAME);		\
-	fprintf (STREAM, "\n");				\
-  } while (0)
-
-/* Output at beginning of assembler file.  */
-#define ASM_FILE_START(FILE) fprintf (FILE, "");
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP "\t.inst"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP "\t.var"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{".r0", ".r1", ".r2", ".r3", ".r4", ".r5", ".r6", ".r7", ".r8", \
- ".r9", ".r10", ".r11", ".r12", ".r13", ".r14", ".sp"}
-
-/* This is BSD, so it wants DBX format.  */
-
-/* #define DBX_DEBUGGING_INFO */
-
-/* How to renumber registers for dbx and gdb.
-   Vax needs no change in the numeration.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Do not break .stabs pseudos into continuations.  */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* This is the char to use for continuation (in case we need to turn
-   continuation back on).  */
-
-#define DBX_CONTIN_CHAR '?'
-
-/* Don't use the `xsfoo;' construct in DBX output; this system
-   doesn't support it.  */
-
-#define DBX_NO_XREFS
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs ("\t.extdef\t", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX ""
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, ".%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.
-   It is .dfloat or .gfloat, depending.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-{ union {double d; int i[2]; } tem;				\
-  tem.d = (VALUE);						\
-  fprintf (FILE, "\t.data\t%d{32}, %d{32}\n", tem.i[0], tem.i[1]); }
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-{ union {float f; int i; } tem;					\
-  tem.f = (VALUE);						\
-  fprintf (FILE, "\t.data %d{32}\n", tem.i); }
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( \
-	fprintf (FILE, "\t.data\t"),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "{32}\n"))
-
-#define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE)			\
-{								\
-	fprintf (FILE, "\t.data\t");				\
-	if (GET_CODE (VALUE) == CONST_DOUBLE)			\
-	{							\
-		fprintf (FILE, "%d", CONST_DOUBLE_HIGH (VALUE)); \
-		fprintf (FILE, "{32}, ");			\
-		fprintf (FILE, "%d", CONST_DOUBLE_LOW (VALUE)); \
-		fprintf (FILE, "{32}\n");			\
-	} else if (GET_CODE (VALUE) == CONST_INT)		\
-	{							\
-		int val = INTVAL (VALUE);			\
-		fprintf (FILE, "%d", val < 0 ? -1 : 0);		\
-		fprintf (FILE, "{32}, ");			\
-		fprintf (FILE, "%d", val);			\
-		fprintf (FILE, "{32}\n");			\
-	} else abort ();					\
-}
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.data\t"),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "{16}\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.data\t"),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "{8}\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.data\t%d{8}\n", (VALUE))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tsubi.64\t4,.sp\n\tst.32\t%s,[.sp]\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tld.32\t%s,[.sp]\n\taddi.64\t4,.sp\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute.
-   (The Vax does not use such vectors,
-   but we must define this macro anyway.)  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.data .L%d{32}\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.data .L%d-.L%d{32}\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
-  if (LOG!=0) fprintf (FILE, "\t.align\t%d\n", (LOG)); else 0
-
-/* This is how to output an assembler line
-   that says to advance the location counter by SIZE bytes.  */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %d\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%d\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".bss ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%d,%d\n", (SIZE),(ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print an instruction operand X on file FILE.
-   CODE is the code from the %-spec that requested printing this operand;
-   if `%z3' was used to print operand 3, then CODE is 'z'.  */
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ \
-  if (CODE == 'r' && GET_CODE (X) == MEM && GET_CODE (XEXP (X, 0)) == REG)							\
-    fprintf (FILE, "%s", reg_names[REGNO (XEXP (X, 0))]);		\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else \
-  { \
-	/*debug_rtx(X);*/ \
-	putc ('=', FILE); \
-	output_addr_const (FILE, X); } \
-   }
-
-/* Print a memory operand whose address is X, on file FILE.
-   This uses a function in output-vax.c.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
- print_operand_address (FILE, ADDR)
-
-/* Functions used in the md file. */
-
-extern char *cmp_set();
-extern char *cmp_jmp();
-
-/* These are stubs, and have yet to bee written. */
-
-#define TRAMPOLINE_SIZE 26
-#define TRAMPOLINE_TEMPLATE(FILE)
-#define  INITIALIZE_TRAMPOLINE(TRAMP,FNADDR,CXT)
diff --git a/gcc/config/elxsi/elxsi.md b/gcc/config/elxsi/elxsi.md
deleted file mode 100755
index b6969e9..0000000
--- a/gcc/config/elxsi/elxsi.md
+++ /dev/null
@@ -1,1420 +0,0 @@
-;;- Machine description for GNU compiler, Elxsi Version
-;;  Copyright (C) 1987, 1988, 1992, 1994 Free Software Foundation, Inc.
-;;  Contributed by Mike Stump <mrs@cygnus.com> in 1988, and is the first
-;;  64 bit port of GNU CC.
-;;  Based upon the VAX port.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 1, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- Instruction patterns.  When multiple patterns apply,
-;;- the first one in the file is chosen.
-;;-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-;;-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-
-(define_insn ""
-  [(set (reg:SI 15)
-	 (plus:SI (reg:SI 15)
-		  (match_operand:SI 0 "general_operand" "g")))]
-  ""
-  "add.64\\t.sp,%0")
-
-(define_insn ""
-  [(set (reg:SI 15)
-	 (plus:SI (match_operand:SI 0 "general_operand" "g")
-		  (reg:SI 15)))]
-  ""
-  "add.64\\t.sp,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "r")
-	 (plus:SI (reg:SI 15)
-		  (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "ld.32\\t%0,.sp\;add.64\\t%0,%1")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "r")
-	 (plus:SI (match_operand:SI 1 "general_operand" "g")
-		  (reg:SI 15)))]
-  ""
-  "ld.32\\t%0,.sp\;add.64\\t%0,%1")
-
-(define_insn ""
-  [(set (reg:SI 15)
-	 (minus:SI (reg:SI 15)
-		   (match_operand:SI 0 "general_operand" "g")))]
-  ""
-  "sub.64\\t.sp,%0")
-
-(define_insn ""
-  [(set (reg:SI 15)
-	 (match_operand:SI 0 "general_operand" "rm"))]
-  ""
-  "ld.32\\t.sp,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "m,r")
-	 (reg:SI 15))]
-  ""
-  "*
-  if (which_alternative == 0)
-    return \"st.32\\t.sp,%0\";
-  return \"ld.32\\t%0,.sp\";
-")
-
-; tstdi is first test insn so that it is the one to match
-; a constant argument.
-
-(define_insn "tstdi"
-  [(set (cc0)
-	(match_operand:DI 0 "register_operand" "r"))]
-  ""
-  "*
-    extern rtx cmp_op0, cmp_op1;
-    cmp_op0=operands[0]; cmp_op1=0;
-    return \";\\ttstdi\\t%0\";
-")
-
-(define_insn "tstdf"
-  [(set (cc0)
-	(match_operand:DF 0 "register_operand" "r"))]
-  ""
-  "*
-    extern rtx cmp_op0, cmp_op1;
-    cmp_op0=operands[0]; cmp_op1=0;
-    return \";\\ttstdf\\t%0\";
-")
-
-(define_insn "tstsf"
-  [(set (cc0)
-	(match_operand:SF 0 "register_operand" "r"))]
-  ""
-  "*
-    extern rtx cmp_op0, cmp_op1;
-    cmp_op0=operands[0]; cmp_op1=0;
-    return \";\\ttstsf\\t%0\";
-")
-
-(define_insn "cmpdi"
-  [(set (cc0)
-	(compare (match_operand:DI 0 "register_operand" "r")
-		 (match_operand:DI 1 "general_operand" "rm")))]
-  ""
-  "*
-    extern rtx cmp_op0, cmp_op1;
-    cmp_op0=operands[0]; cmp_op1=operands[1];
-    return \";\\tcmpdi\\t%0,%1\";
-")
-
-(define_insn "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "register_operand" "r")
-		 (match_operand:DF 1 "general_operand" "rm")))]
-  ""
-  "*
-    extern rtx cmp_op0, cmp_op1;
-    cmp_op0=operands[0]; cmp_op1=operands[1];
-    return \";\\tcmpdf\\t%0,%1\";
-")
-
-(define_insn "cmpsf"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "register_operand" "r")
-		 (match_operand:SF 1 "general_operand" "rm")))]
-  ""
-  "*
-    extern rtx cmp_op0, cmp_op1;
-    cmp_op0=operands[0]; cmp_op1=operands[1];
-    return \";\\tcmpsf\\t%0,%1\";
-")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (eq (match_operand:DI 1 "register_operand" "r")
-	         (match_operand:DI 2 "general_operand" "g")))]
-  ""
-  "cmp.64\\t%0,%1,%2:eq")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (ne (match_operand:DI 1 "register_operand" "r")
-	         (match_operand:DI 2 "general_operand" "g")))]
-  ""
-  "cmp.64\\t%0,%1,%2:ne")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (le (match_operand:DI 1 "register_operand" "r")
-	         (match_operand:DI 2 "general_operand" "g")))]
-  ""
-  "cmp.64\\t%0,%1,%2:le")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (leu (match_operand:DI 1 "register_operand" "r")
-	         (match_operand:DI 2 "general_operand" "g")))]
-  ""
-  "cmpu.64\\t%0,%1,%2:le")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (lt (match_operand:DI 1 "register_operand" "r")
-	         (match_operand:DI 2 "general_operand" "g")))]
-  ""
-  "cmp.64\\t%0,%1,%2:lt")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (ltu (match_operand:DI 1 "register_operand" "r")
-	         (match_operand:DI 2 "general_operand" "g")))]
-  ""
-  "cmpu.64\\t%0,%1,%2:lt")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (ge (match_operand:DI 1 "register_operand" "r")
-	         (match_operand:DI 2 "general_operand" "g")))]
-  ""
-  "cmp.64\\t%0,%1,%2:ge")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (geu (match_operand:DI 1 "register_operand" "r")
-	         (match_operand:DI 2 "general_operand" "g")))]
-  ""
-  "cmpu.64\\t%0,%1,%2:ge")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (gt (match_operand:DI 1 "register_operand" "r")
-	         (match_operand:DI 2 "general_operand" "g")))]
-  ""
-  "cmp.64\\t%0,%1,%2:gt")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (gtu (match_operand:DI 1 "register_operand" "r")
-	         (match_operand:DI 2 "general_operand" "g")))]
-  ""
-  "cmpu.64\\t%0,%1,%2:gt")
-
-(define_insn "seq"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(eq (cc0) (const_int 0)))]
-  ""
-  "* return cmp_set(\"\", \"eq\", operands[0]); ")
-
-(define_insn "sne"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ne (cc0) (const_int 0)))]
-  ""
-  "* return cmp_set(\"\", \"ne\", operands[0]); ")
-
-(define_insn "sle"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(le (cc0) (const_int 0)))]
-  ""
-  "* return cmp_set(\"\", \"le\", operands[0]); ")
-
-(define_insn "sleu"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(leu (cc0) (const_int 0)))]
-  ""
-  "* return cmp_set(\"u\", \"le\", operands[0]); ")
-
-(define_insn "slt"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(lt (cc0) (const_int 0)))]
-  ""
-  "* return cmp_set(\"\", \"lt\", operands[0]); ")
-
-(define_insn "sltu"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ltu (cc0) (const_int 0)))]
-  ""
-  "* return cmp_set(\"u\", \"lt\", operands[0]); ")
-
-(define_insn "sge"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ge (cc0) (const_int 0)))]
-  ""
-  "* return cmp_set(\"\", \"ge\", operands[0]); ")
-
-(define_insn "sgeu"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(geu (cc0) (const_int 0)))]
-  ""
-  "* return cmp_set(\"u\", \"ge\", operands[0]); ")
-
-(define_insn "sgt"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(gt (cc0) (const_int 0)))]
-  ""
-  "* return cmp_set(\"\", \"gt\", operands[0]); ")
-
-(define_insn "sgtu"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(gtu (cc0) (const_int 0)))]
-  ""
-  "* return cmp_set(\"u\", \"gt\", operands[0]); ")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(eq (match_operand:SI 1 "register_operand" "r")
-	    (match_operand:SI 2 "general_operand" "m")))]
-  ""
-  "cmp.32\\t%0,%1,%2:eq")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ne (match_operand:SI 1 "register_operand" "r")
-	    (match_operand:SI 2 "general_operand" "m")))]
-  ""
-  "cmp.32\\t%0,%1,%2:ne")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(le (match_operand:SI 1 "register_operand" "r")
-	    (match_operand:SI 2 "general_operand" "m")))]
-  ""
-  "cmp.32\\t%0,%1,%2:le")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(leu (match_operand:SI 1 "register_operand" "r")
-	    (match_operand:SI 2 "general_operand" "m")))]
-  ""
-  "cmpu.32\\t%0,%1,%2:le")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lt (match_operand:SI 1 "register_operand" "r")
-	    (match_operand:SI 2 "general_operand" "m")))]
-  ""
-  "cmp.32\\t%0,%1,%2:lt")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ltu (match_operand:SI 1 "register_operand" "r")
-	    (match_operand:SI 2 "general_operand" "m")))]
-  ""
-  "cmpu.32\\t%0,%1,%2:lt")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ge (match_operand:SI 1 "register_operand" "r")
-	    (match_operand:SI 2 "general_operand" "m")))]
-  ""
-  "cmp.32\\t%0,%1,%2:ge")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(geu (match_operand:SI 1 "register_operand" "r")
-	    (match_operand:SI 2 "general_operand" "m")))]
-  ""
-  "cmpu.32\\t%0,%1,%2:ge")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(gt (match_operand:SI 1 "register_operand" "r")
-	    (match_operand:SI 2 "general_operand" "m")))]
-  ""
-  "cmp.32\\t%0,%1,%2:gt")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(gtu (match_operand:SI 1 "register_operand" "r")
-	    (match_operand:SI 2 "general_operand" "m")))]
-  ""
-  "cmpu.32\\t%0,%1,%2:gt")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(eq (match_operand:HI 1 "register_operand" "r")
-	    (match_operand:HI 2 "general_operand" "m")))]
-  ""
-  "cmp.16\\t%0,%1,%2:eq")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(ne (match_operand:HI 1 "register_operand" "r")
-	    (match_operand:HI 2 "general_operand" "m")))]
-  ""
-  "cmp.16\\t%0,%1,%2:ne")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(le (match_operand:HI 1 "register_operand" "r")
-	    (match_operand:HI 2 "general_operand" "m")))]
-  ""
-  "cmp.16\\t%0,%1,%2:le")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(leu (match_operand:HI 1 "register_operand" "r")
-	    (match_operand:HI 2 "general_operand" "m")))]
-  ""
-  "cmpu.16\\t%0,%1,%2:le")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(lt (match_operand:HI 1 "register_operand" "r")
-	    (match_operand:HI 2 "general_operand" "m")))]
-  ""
-  "cmp.16\\t%0,%1,%2:lt")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(ltu (match_operand:HI 1 "register_operand" "r")
-	    (match_operand:HI 2 "general_operand" "m")))]
-  ""
-  "cmpu.16\\t%0,%1,%2:lt")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(ge (match_operand:HI 1 "register_operand" "r")
-	    (match_operand:HI 2 "general_operand" "m")))]
-  ""
-  "cmp.16\\t%0,%1,%2:ge")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(geu (match_operand:HI 1 "register_operand" "r")
-	    (match_operand:HI 2 "general_operand" "m")))]
-  ""
-  "cmpu.16\\t%0,%1,%2:ge")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(gt (match_operand:HI 1 "register_operand" "r")
-	    (match_operand:HI 2 "general_operand" "m")))]
-  ""
-  "cmp.16\\t%0,%1,%2:gt")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(gtu (match_operand:HI 1 "register_operand" "r")
-	    (match_operand:HI 2 "general_operand" "m")))]
-  ""
-  "cmpu.16\\t%0,%1,%2:gt")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(eq (match_operand:QI 1 "register_operand" "r")
-	    (match_operand:QI 2 "general_operand" "m")))]
-  ""
-  "cmp.8\\t%0,%1,%2:eq")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(ne (match_operand:QI 1 "register_operand" "r")
-	    (match_operand:QI 2 "general_operand" "m")))]
-  ""
-  "cmp.8\\t%0,%1,%2:ne")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(le (match_operand:QI 1 "register_operand" "r")
-	    (match_operand:QI 2 "general_operand" "m")))]
-  ""
-  "cmp.8\\t%0,%1,%2:le")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(leu (match_operand:QI 1 "register_operand" "r")
-	    (match_operand:QI 2 "general_operand" "m")))]
-  ""
-  "cmpu.8\\t%0,%1,%2:le")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(lt (match_operand:QI 1 "register_operand" "r")
-	    (match_operand:QI 2 "general_operand" "m")))]
-  ""
-  "cmp.8\\t%0,%1,%2:lt")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(ltu (match_operand:QI 1 "register_operand" "r")
-	    (match_operand:QI 2 "general_operand" "m")))]
-  ""
-  "cmpu.8\\t%0,%1,%2:lt")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(ge (match_operand:QI 1 "register_operand" "r")
-	    (match_operand:QI 2 "general_operand" "m")))]
-  ""
-  "cmp.8\\t%0,%1,%2:ge")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(geu (match_operand:QI 1 "register_operand" "r")
-	    (match_operand:QI 2 "general_operand" "m")))]
-  ""
-  "cmpu.8\\t%0,%1,%2:ge")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(gt (match_operand:QI 1 "register_operand" "r")
-	    (match_operand:QI 2 "general_operand" "m")))]
-  ""
-  "cmp.8\\t%0,%1,%2:gt")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(gtu (match_operand:QI 1 "register_operand" "r")
-	    (match_operand:QI 2 "general_operand" "m")))]
-  ""
-  "cmpu.8\\t%0,%1,%2:gt")
-
-
-
-(define_insn "movdf"  [(set (match_operand:DF 0 "general_operand" "=r,m")
-	(match_operand:DF 1 "general_operand" "rm,r"))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"ld.64\\t%0,%1\";
-  return \"st.64\\t%1,%0\";
-}")
-
-(define_insn "movsf"
-  [(set (match_operand:SF 0 "general_operand" "=r,m")
-	(match_operand:SF 1 "general_operand" "rm,r"))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"ld.32\\t%0,%1\";
-  return \"st.32\\t%1,%0\";
-}")
-
-(define_insn "movdi"
-  [(set (match_operand:DI 0 "general_operand" "=r,m,rm")
-	(match_operand:DI 1 "general_operand" "g,r,I"))]
-  ""
-  "*
-  if (which_alternative == 0)
-    return \"ld.64\\t%0,%1\";
-  else if (which_alternative == 1)
-    return \"st.64\\t%1,%0\";
-  else
-    if (GET_CODE(operands[1])==CONST_INT) {
-      if (INTVAL(operands[1]) >= 0)
-        return \"sti.64\\t%c1,%0\";
-      else
-        return \"stin.64\\t%n1,%0\";
-    }
-")
-
-(define_insn "movsi"
-  [(set (match_operand:SI 0 "general_operand" "=r,m,r")
-	(match_operand:SI 1 "general_operand" "rm,rI,i"))]
-  ""
-  "*
-  if (which_alternative == 0)
-    return \"ld.32\\t%0,%1\";
-  else if (which_alternative == 1) {
-    if (GET_CODE(operands[1])==CONST_INT) {
-      if (INTVAL(operands[1]) >= 0)
-        return \"sti.32\\t%c1,%0\";
-      else
-        return \"stin.32\\t%n1,%0\";
-    }
-    return \"st.32\\t%1,%0\";
-  } else
-    return \"ld.64\\t%0,%1 ; I only want 32\";
-")
-
-(define_insn "movhi"
-  [(set (match_operand:HI 0 "general_operand" "=r,m,r")
-	(match_operand:HI 1 "general_operand" "m,rI,ri"))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"ld.16\\t%0,%1\";
-  if (which_alternative == 2)
-    return \"ld.64\\t%0,%1\\t; I only want 16\";
-  if (GET_CODE(operands[1])==CONST_INT) {
-    if (INTVAL(operands[1]) >= 0)
-      return \"sti.16\\t%c1,%0\";
-    else
-      return \"stin.16\\t%n1,%0\";
-  }
-  return \"st.16\\t%1,%0\";
-}")
-
-(define_insn "movqi"
-  [(set (match_operand:QI 0 "general_operand" "=r,m,r")
-	(match_operand:QI 1 "general_operand" "m,rI,ri"))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"ld.8\\t%0,%1\";
-  if (which_alternative == 2)
-    return \"ld.64\\t%0,%1\\t; I only want 8\";
-  if (GET_CODE(operands[1])==CONST_INT) {
-    if (INTVAL(operands[1]) >= 0)
-      return \"sti.8\\t%c1,%0\";
-    else
-      return \"stin.8\\t%n1,%0\";
-  }
-  return \"st.8\\t%1,%0\";
-}")
-
-;; Extension and truncation insns.
-;; Those for integer source operand
-;; are ordered widest source type first.
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(truncate:SF (match_operand:DF 1 "general_operand" "rm")))]
-  ""
-  "cvt.ds\\t%0,%1")
-
-(define_insn "truncdiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=r,m,r")
-	(truncate:QI (match_operand:DI 1 "general_operand" "m,r,0")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"ld.8\\t%0,%1\";
-  else if (which_alternative == 1)
-    return \"st.8\\t%1,%0\";
-  return \"\";
-}")
-
-(define_insn "truncdihi2"
-  [(set (match_operand:HI 0 "general_operand" "=r,m,r")
-	(truncate:HI (match_operand:DI 1 "general_operand" "m,r,0")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"ld.16\\t%0,%1\";
-  if (which_alternative == 1)
-    return \"st.16\\t%1,%0\";
-  return \"\";
-}")
-
-(define_insn "truncdisi2"
-  [(set (match_operand:SI 0 "general_operand" "=r,m")
-	(truncate:SI (match_operand:DI 1 "general_operand" "rm,r")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"ld.32\\t%0,%1\";
-  return \"st.32\\t%1,%0\";
-}")
-
-(define_insn "truncsiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=r,m,r")
-	(truncate:QI (match_operand:SI 1 "general_operand" "m,r,0")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"ld.8\\t%0,%1\";
-  if (which_alternative == 1)
-    return \"st.8\\t%1,%0\";
-  return \"\";
-}")
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "general_operand" "=r,m,r")
-	(truncate:HI (match_operand:SI 1 "general_operand" "m,r,0")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"ld.16\\t%0,%1\";
-  if (which_alternative == 1)
-    return \"st.16\\t%1,%0\";
-  return \"\";
-}")
-
-(define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=r,m,r")
-	(truncate:QI (match_operand:HI 1 "general_operand" "m,r,0")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"ld.8\\t%0,%1\";
-  if (which_alternative == 1)
-    return \"st.8\\t%1,%0\";
-  return \"\";
-}")
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(sign_extend:DF (match_operand:SF 1 "general_operand" "rm")))]
-  ""
-  "cvt.sd\\t%0,%1")
-
-(define_insn "extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
-  ""
-  "ld.32\\t%0,%1")
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(sign_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
-  ""
-  "*
-     if (which_alternative==0)
-       return \"ld.16\\t%0,%1\";
-     return \"extract\\t%0,%1:bit 48,16\";
-")
-
-(define_insn "extendhidi2"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(sign_extend:DI (match_operand:HI 1 "general_operand" "m,r")))]
-  ""
-  "*
-     if (which_alternative==0)
-       return \"ld.16\\t%0,%1\";
-     return \"extract\\t%0,%1:bit 48,16\";
-")
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(sign_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
-  ""
-  "*
-     if (which_alternative==0)
-       return \"ld.8\\t%0,%1\";
-     return \"extract\\t%0,%1:bit 56,8\";
-")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(sign_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
-  ""
-  "*
-     if (which_alternative==0)
-       return \"ld.8\\t%0,%1\";
-     return \"extract\\t%0,%1:bit 56,8\";
-")
-
-(define_insn "extendqidi2"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(sign_extend:DI (match_operand:QI 1 "general_operand" "m,r")))]
-  ""
-  "*
-     if (which_alternative==0)
-       return \"ld.8\\t%0,%1\";
-     return \"extract\\t%0,%1:bit 56,8\";
-")
-
-(define_insn "zero_extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
-  ""
-  "ldz.32\\t%0,%1")
-
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(zero_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
-  ""
-  "*
-     if (which_alternative==0)
-       return \"ldz.16\\t%0,%1\";
-     return \"extractz\\t%0,%1:bit 48,16\";
-")
-
-(define_insn "zero_extendhidi2"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(zero_extend:DI (match_operand:HI 1 "general_operand" "m,r")))]
-  ""
-  "*
-     if (which_alternative==0)
-       return \"ldz.16\\t%0,%1\";
-     return \"extractz\\t%0,%1:bit 48,16\";
-")
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(zero_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
-  ""
-  "*
-     if (which_alternative==0)
-       return \"ldz.8\\t%0,%1\";
-     return \"extractz\\t%0,%1:bit 56,8\";
-")
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(zero_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
-  ""
-  "*
-     if (which_alternative==0)
-       return \"ldz.8\\t%0,%1\";
-     return \"extractz\\t%0,%1:bit 56,8\";
-")
-
-(define_insn "zero_extendqidi2"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(zero_extend:DI (match_operand:QI 1 "general_operand" "m,r")))]
-  ""
-  "*
-     if (which_alternative==0)
-       return \"ldz.8\\t%0,%1\";
-     return \"extractz\\t%0,%1:bit 56,8\";
-")
-
-
-(define_insn "ashrdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
-		   (match_operand:SI 2 "general_operand" "rn")))]
-  ""
-  "sra\\t%0,%1,%2")
-
-(define_insn "lshrdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
-		   (match_operand:SI 2 "general_operand" "rn")))]
-  ""
-  "srl\\t%0,%1,%2")
-
-(define_insn "ashldi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (match_operand:DI 1 "register_operand" "r")
-		   (match_operand:SI 2 "general_operand" "rn")))]
-  ""
-  "sla\\t%0,%1,%2")
-
-(define_insn "anddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(and:DI (match_operand:DI 1 "general_operand" "%0,r")
-		(match_operand:DI 2 "general_operand" "g,g")))]
-  "1 /*which_alternative == 0 || check356(operands[2])*/"
-  "*
-    if (which_alternative == 0)
-      return \"and\\t%0,%2\";
-    return \"and\\t%0,%1,%2\";
-")
-
-(define_insn "iordi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(ior:DI (match_operand:DI 1 "general_operand" "%0,r")
-		(match_operand:DI 2 "general_operand" "g,g")))]
-  "1 /*which_alternative == 0 || check356(operands[2])*/"
-  "*
-    if (which_alternative == 0)
-      return \"or\\t%0,%2\";
-    return \"or\\t%0,%1,%2\";
-")
-
-(define_insn "xordi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(xor:DI (match_operand:DI 1 "general_operand" "%0,r")
-		(match_operand:DI 2 "general_operand" "g,g")))]
-  "1 /*which_alternative == 0 || check356(operands[2])*/"
-  "*
-    if (which_alternative == 0)
-      return \"xor\\t%0,%2\";
-    return \"xor\\t%0,%1,%2\";
-")
-
-(define_insn "one_cmpldi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(not:DI (match_operand:DI 1 "general_operand" "rm")))]
-  ""
-  "not\\t%0,%1")
-
-;; gcc 2.1 does not widen ~si into ~di.
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "not\\t%0,%1")
-
-(define_insn "negdi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(neg:DI (match_operand:DI 1 "general_operand" "rm")))]
-  ""
-  "neg.64\\t%0,%1")
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(neg:SI (match_operand:SI 1 "general_operand" "m,r")))]
-  ""
-  "*
-    if (which_alternative == 0)
-      return \"neg.32\\t%0,%1\";
-    return \"neg.64\\t%0,%1 ; I only want 32\";
-")
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(neg:HI (match_operand:HI 1 "general_operand" "m,r")))]
-  ""
-  "*
-    if (which_alternative == 0)
-      return \"neg.16\\t%0,%1\";
-    return \"neg.64\\t%0,%1 ; I only want 16\";
-")
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(plus:DF (match_operand:DF 1 "general_operand" "%0")
-		  (match_operand:DF 2 "general_operand" "rm")))]
-  ""
-  "fadd.64\\t%0,%2")
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(plus:SF (match_operand:SF 1 "general_operand" "%0")
-		 (match_operand:SF 2 "general_operand" "rm")))]
-  ""
-  "fadd.32\\t%0,%2")
-
-;; There is also an addi.64  4,.r0'' optimization
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(plus:DI (match_operand:DI 1 "general_operand" "%0,r")
-		 (match_operand:DI 2 "general_operand" "g,g")))]
-  "1 /*which_alternative == 0 || check356(operands[2])*/"
-  "*
-    if (which_alternative == 0)
-      return \"add.64\\t%0,%2\";
-    return \"add.64\\t%0,%1,%2\";
-")
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(plus:SI (match_operand:SI 1 "general_operand" "%0,r,0")
-		 (match_operand:SI 2 "general_operand" "m,m,g")))]
-  "1 /*which_alternative != 1 || check356(operands[2])*/"
-  "*
-    if (which_alternative == 0)
-      return \"add.32\\t%0,%2\";
-    if (which_alternative == 1)
-      return \"add.32\\t%0,%1,%2\";
-    return \"add.64\\t%0,%2 ; I only want 32\";
-")
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
-	(plus:HI (match_operand:HI 1 "general_operand" "%0,r,0")
-		 (match_operand:HI 2 "general_operand" "m,m,g")))]
-  "1 /*which_alternative != 1 || check356(operands[2])*/"
-  "*
-    if (which_alternative == 0)
-      return \"add.16\\t%0,%2\";
-    if (which_alternative == 1)
-      return \"add.16\\t%0,%1,%2\";
-    return \"add.64\\t%0,%2 ; I only want 16\";
-")
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(minus:DF (match_operand:DF 1 "general_operand" "0")
-		  (match_operand:DF 2 "general_operand" "rm")))]
-  ""
-  "fsub.64\\t%0,%2")
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(minus:SF (match_operand:SF 1 "general_operand" "0")
-		  (match_operand:SF 2 "general_operand" "rm")))]
-  ""
-  "fsub.32\\t%0,%2")
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-	(minus:DI (match_operand:DI 1 "general_operand" "0,g,r")
-		  (match_operand:DI 2 "general_operand" "g,r,g")))]
-  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
-  "*
-    if (which_alternative == 0)
-      return \"sub.64\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"subr.64\\t%0,%2,%1\";
-    else
-      return \"sub.64\\t%0,%1,%2\";
-")
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(minus:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
-		  (match_operand:SI 2 "general_operand" "m,r,m,g")))]
-  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
-  "*
-    if (which_alternative == 0)
-      return \"sub.32\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"subr.32\\t%0,%2,%1\";
-    else if (which_alternative == 2)
-      return \"sub.32\\t%0,%1,%2\";
-    else
-      return \"sub.64\\t%0,%2 ; I only want 32\";
-")
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
-	(minus:HI (match_operand:HI 1 "general_operand" "0,m,r,0")
-		  (match_operand:HI 2 "general_operand" "m,r,m,g")))]
-  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
-  "*
-    if (which_alternative == 0)
-      return \"sub.16\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"subr.16\\t%0,%2,%1\";
-    else if (which_alternative == 2)
-      return \"sub.16\\t%0,%1,%2\";
-    else
-      return \"sub.64\\t%0,%2 ; I only want 16\";
-")
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(mult:DF (match_operand:DF 1 "general_operand" "%0")
-		 (match_operand:DF 2 "general_operand" "rm")))]
-  ""
-  "fmul.64\\t%0,%2")
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(mult:SF (match_operand:SF 1 "general_operand" "%0")
-		 (match_operand:SF 2 "general_operand" "rm")))]
-  ""
-  "fmul.32\\t%0,%2")
-
-(define_insn "muldi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(mult:DI (match_operand:DI 1 "general_operand" "%0,r")
-		 (match_operand:DI 2 "general_operand" "g,g")))]
-  "1 /*which_alternative == 0 || check356(operands[2])*/"
-  "*
-    if (which_alternative == 0)
-      return \"mul.64\\t%0,%2\";
-    return \"mul.64\\t%0,%1,%2\";
-")
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(mult:SI (match_operand:SI 1 "general_operand" "%0,r,0")
-		 (match_operand:SI 2 "general_operand" "m,m,g")))]
-  "1 /*which_alternative == 0 || check356(operands[2])*/"
-  "*
-    if (which_alternative == 0)
-      return \"mul.32\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"mul.32\\t%0,%1,%2\";
-    else
-      return \"mul.64\\t%0,%2 ; I only want 32\";
-")
-
-(define_insn "mulhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
-	(mult:HI (match_operand:HI 1 "general_operand" "%0,r,0")
-		 (match_operand:HI 2 "general_operand" "m,m,g")))]
-  "1 /*which_alternative == 0 || check356(operands[2])*/"
-  "*
-    if (which_alternative == 0)
-      return \"mul.16\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"mul.16\\t%0,%1,%2\";
-    else
-      return \"mul.64\\t%0,%2 ; I only want 16\";
-")
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(div:DF (match_operand:DF 1 "general_operand" "0")
-		(match_operand:DF 2 "general_operand" "rm")))]
-  ""
-  "fdiv.64\\t%0,%2")
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(div:SF (match_operand:SF 1 "general_operand" "0")
-		(match_operand:SF 2 "general_operand" "rm")))]
-  ""
-  "fdiv.32\\t%0,%2")
-
-(define_insn "divdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-	(div:DI (match_operand:DI 1 "general_operand" "0,g,r")
-		(match_operand:DI 2 "general_operand" "g,r,g")))]
-  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
-  "*
-    if (which_alternative == 0)
-      return \"div.64\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"divr.64\\t%0,%2,%1\";
-    else
-      return \"div.64\\t%0,%1,%2\";
-")
-
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(div:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
-		(match_operand:SI 2 "general_operand" "m,r,m,g")))]
-  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
-  "*
-/* We don't ignore high bits. */
-if (0) {
-    if (which_alternative == 0)
-      return \"div.32\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"divr.32\\t%0,%2,%1\";
-    else if (which_alternative == 2)
-      return \"div.32\\t%0,%1,%2\";
-    else
-      return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\";
-} else {
-    if (which_alternative == 0)
-      return \"ld.32\\t%0,%0\;div.32\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"ld.32\\t%2,%2\;divr.32\\t%0,%2,%1\";
-    else if (which_alternative == 2)
-      return \"ld.32\\t%1,%1\;div.32\\t%0,%1,%2\";
-    else
-      return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\";
-}
-")
-
-(define_insn "divhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
-	(div:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0")
-		(match_operand:HI 2 "general_operand" "m,r,m,r,i")))]
-  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
-  "*
-    if (which_alternative == 0)
-      return \"extract\\t%0,%0:bit 48,16\;div.16\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"extract\\t%2,%2:bit 48,16\;divr.16\\t%0,%2,%1\";
-    else if (which_alternative == 2)
-      return \"extract\\t%1,%1:bit 48,16\;div.16\\t%0,%1,%2\";
-    else if (which_alternative == 3)
-      return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;div.64\\t%0,%2 ; I only want 16\";
-    else
-      return \"extract\\t%0,%0:bit 48,16\;div.64\\t%0,%2 ; I only want 16\";
-")
-
-(define_insn "modhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
-	(mod:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0")
-		(match_operand:HI 2 "general_operand" "m,r,m,r,i")))]
-  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
-  "*
-    if (which_alternative == 0)
-      return \"extract\\t%0,%0:bit 48,16\;rem.16\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"extract\\t%2,%2:bit 48,16\;remr.16\\t%0,%2,%1\";
-    else if (which_alternative == 2)
-      return \"extract\\t%1,%1:bit 48,16\;rem.16\\t%0,%1,%2\";
-    else if (which_alternative == 3)
-      return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\";
-    else
-      return \"extract\\t%0,%0:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\";
-")
-
-(define_insn "moddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-	(mod:DI (match_operand:DI 1 "general_operand" "0,g,r")
-		(match_operand:DI 2 "general_operand" "g,r,g")))]
-  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
-  "*
-    if (which_alternative == 0)
-      return \"rem.64\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"remr.64\\t%0,%2,%1\";
-    else
-      return \"rem.64\\t%0,%1,%2\";
-")
-
-(define_insn "modsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(mod:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
-		(match_operand:SI 2 "general_operand" "m,r,m,g")))]
-  "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
-  "*
-/* There is a micro code bug with the below... */
-if (0) {
-    if (which_alternative == 0)
-      return \"rem.32\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"remr.32\\t%0,%2,%1\";
-    else if (which_alternative == 2)
-      return \"rem.32\\t%0,%1,%2\";
-    else
-      return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\";
-} else {
-    if (which_alternative == 0)
-      return \"ld.32\\t%0,%0\;rem.32\\t%0,%2\";
-    else if (which_alternative == 1)
-      return \"ld.32\\t%2,%2\;remr.32\\t%0,%2,%1\";
-    else if (which_alternative == 2)
-      return \"ld.32\\t%1,%1\;rem.32\\t%0,%1,%2\";
-    else
-      return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\";
-}
-")
-
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "jmp\\t%l0")
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
-  ""
-;; Maybe %l0 is better, maybe we can relax register only.
-  "verify this before use ld.32\\t.r0,%0\;br.reg\\t.r0")
-
-(define_insn "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return cmp_jmp(\"\", 2, operands[0]); ")
-
-(define_insn "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return cmp_jmp(\"\", 8, operands[0]); ")
-
-(define_insn "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return cmp_jmp(\"\", 0, operands[0]); ")
-
-(define_insn "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return cmp_jmp(\"u\", 0, operands[0]); ")
-
-(define_insn "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return cmp_jmp(\"\", 6, operands[0]); ")
-
-(define_insn "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return cmp_jmp(\"u\", 6, operands[0]); ")
-
-(define_insn "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return cmp_jmp(\"\", 4, operands[0]); ")
-
-(define_insn "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return cmp_jmp(\"u\", 4, operands[0]); ")
-
-(define_insn "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return cmp_jmp(\"\", 10, operands[0]); ")
-
-(define_insn "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return cmp_jmp(\"u\", 10, operands[0]); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return cmp_jmp(\"\", 8, operands[0]); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return cmp_jmp(\"\", 2, operands[0]); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return cmp_jmp(\"\", 10, operands[0]); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return cmp_jmp(\"u\", 10, operands[0]); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return cmp_jmp(\"\", 4, operands[0]); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return cmp_jmp(\"u\", 4, operands[0]); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return cmp_jmp(\"\", 6, operands[0]); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return cmp_jmp(\"u\", 6, operands[0]); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return cmp_jmp(\"\", 0, operands[0]); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return cmp_jmp(\"u\", 0, operands[0]); ")
-
-;; Note that operand 1 is total size of args, in bytes,
-;; and what the call insn wants is the number of words.
-(define_insn "call"
-  [(call (match_operand:QI 0 "general_operand" "m")
-	 (match_operand:QI 1 "general_operand" "g"))]
-  ""
-  "*
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == REG)
-    if (REGNO (XEXP (operands[0], 0)) != 0)
-      return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
-    else
-      return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
-  else
-    return \"add.64\\t.sp,=-4\;call\\t%0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
-  ")
-
-(define_insn "call_value"
-  [(set (match_operand 0 "" "g")
-	(call (match_operand:QI 1 "general_operand" "m")
-	      (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-  if (GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1], 0)) == REG)
-    if (REGNO (XEXP (operands[1], 0)) != 0)
-      return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
-    else
-      return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
-  else
-    return \"add.64\\t.sp,=-4\;call\\t%1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
-  ")
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "br.reg\\t%0")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
diff --git a/gcc/config/elxsi/x-elxsi b/gcc/config/elxsi/x-elxsi
deleted file mode 100755
index 30a458d..0000000
--- a/gcc/config/elxsi/x-elxsi
+++ /dev/null
@@ -1,9 +0,0 @@
-# Our make needs a little help...
-MAKE=make
-
-# We don't support -g yet, so don't try and use it.
-CFLAGS =
-LIBGCC2_CFLAGS = -O2 $(GCC_CFLAGS)
-
-# Hide xmalloc so that it does not conflict with the one in libc.a, Ick!
-X_CFLAGS = -Dxmalloc=my_xmalloc
diff --git a/gcc/config/elxsi/xm-elxsi.h b/gcc/config/elxsi/xm-elxsi.h
deleted file mode 100755
index ab35a68..0000000
--- a/gcc/config/elxsi/xm-elxsi.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Configuration for GNU C-compiler for Elxsi.
-   Copyright (C) 1987, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
diff --git a/gcc/config/float-d10v.h b/gcc/config/float-d10v.h
deleted file mode 100755
index 92403a5..0000000
--- a/gcc/config/float-d10v.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* CYGNUS LOCAL */
-/* float.h for target d10v which defaults to float==double */
-#ifndef _FLOAT_H_
-#define _FLOAT_H_
-/* Produced by enquire version 4.3, CWI, Amsterdam */
-
-   /* Radix of exponent representation */
-#undef FLT_RADIX
-#define FLT_RADIX 2
-   /* Number of base-FLT_RADIX digits in the significand of a float */
-#undef FLT_MANT_DIG
-#define FLT_MANT_DIG 24
-   /* Number of decimal digits of precision in a float */
-#undef FLT_DIG
-#define FLT_DIG 6
-   /* Addition rounds to 0: zero, 1: nearest, 2: +inf, 3: -inf, -1: unknown */
-#undef FLT_ROUNDS
-#define FLT_ROUNDS 1
-   /* Difference between 1.0 and the minimum float greater than 1.0 */
-#undef FLT_EPSILON
-#define FLT_EPSILON 1.19209290e-07F
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised float */
-#undef FLT_MIN_EXP
-#define FLT_MIN_EXP (-125)
-   /* Minimum normalised float */
-#undef FLT_MIN
-#define FLT_MIN 1.17549435e-38F
-   /* Minimum int x such that 10**x is a normalised float */
-#undef FLT_MIN_10_EXP
-#define FLT_MIN_10_EXP (-37)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable float */
-#undef FLT_MAX_EXP
-#define FLT_MAX_EXP 128
-   /* Maximum float */
-#undef FLT_MAX
-#define FLT_MAX 3.40282347e+38F
-   /* Maximum int x such that 10**x is a representable float */
-#undef FLT_MAX_10_EXP
-#define FLT_MAX_10_EXP 38
-
-#if __DOUBLE__!=64
-
-   /* Number of base-FLT_RADIX digits in the significand of a double */
-#undef DBL_MANT_DIG
-#define DBL_MANT_DIG 24
-   /* Number of decimal digits of precision in a double */
-#undef DBL_DIG
-#define DBL_DIG 6
-   /* Difference between 1.0 and the minimum double greater than 1.0 */
-#undef DBL_EPSILON
-#define DBL_EPSILON 1.19209290e-07F
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised double */
-#undef DBL_MIN_EXP
-#define DBL_MIN_EXP (-125)
-   /* Minimum normalised double */
-#undef DBL_MIN
-#define DBL_MIN 1.17549435e-38F
-   /* Minimum int x such that 10**x is a normalised double */
-#undef DBL_MIN_10_EXP
-#define DBL_MIN_10_EXP (-37)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable double */
-#undef DBL_MAX_EXP
-#define DBL_MAX_EXP 128
-   /* Maximum double */
-#undef DBL_MAX
-#define DBL_MAX 3.40282347e+38F
-   /* Maximum int x such that 10**x is a representable double */
-#undef DBL_MAX_10_EXP
-#define DBL_MAX_10_EXP 38
-
-#else
-
-   /* Number of base-FLT_RADIX digits in the significand of a double */
-#undef DBL_MANT_DIG
-#define DBL_MANT_DIG 53
-   /* Number of decimal digits of precision in a double */
-#undef DBL_DIG
-#define DBL_DIG 15
-   /* Difference between 1.0 and the minimum double greater than 1.0 */
-#undef DBL_EPSILON
-#define DBL_EPSILON 2.2204460492503131e-16
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised double */
-#undef DBL_MIN_EXP
-#define DBL_MIN_EXP (-1021)
-   /* Minimum normalised double */
-#undef DBL_MIN
-#define DBL_MIN 2.2250738585072014e-308
-   /* Minimum int x such that 10**x is a normalised double */
-#undef DBL_MIN_10_EXP
-#define DBL_MIN_10_EXP (-307)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable double */
-#undef DBL_MAX_EXP
-#define DBL_MAX_EXP 1024
-   /* Maximum double */
-#undef DBL_MAX
-#define DBL_MAX 1.7976931348623157e+308
-   /* Maximum int x such that 10**x is a representable double */
-#undef DBL_MAX_10_EXP
-#define DBL_MAX_10_EXP 308
-
-#endif
-
-   /* Number of base-FLT_RADIX digits in the significand of a long double */
-#undef LDBL_MANT_DIG
-#define LDBL_MANT_DIG 53
-   /* Number of decimal digits of precision in a long double */
-#undef LDBL_DIG
-#define LDBL_DIG 15
-   /* Difference between 1.0 and the minimum long double greater than 1.0 */
-#undef LDBL_EPSILON
-#define LDBL_EPSILON 2.2204460492503131e-16
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised long double */
-#undef LDBL_MIN_EXP
-#define LDBL_MIN_EXP (-1021)
-   /* Minimum normalised long double */
-#undef LDBL_MIN
-#define LDBL_MIN 2.2250738585072014e-308
-   /* Minimum int x such that 10**x is a normalised long double */
-#undef LDBL_MIN_10_EXP
-#define LDBL_MIN_10_EXP (-307)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable long double */
-#undef LDBL_MAX_EXP
-#define LDBL_MAX_EXP 1024
-   /* Maximum long double */
-#undef LDBL_MAX
-#define LDBL_MAX 1.7976931348623157e+308
-   /* Maximum int x such that 10**x is a representable long double */
-#undef LDBL_MAX_10_EXP
-#define LDBL_MAX_10_EXP 308
-
-#endif /*  _FLOAT_H_ */
diff --git a/gcc/config/float-i128.h b/gcc/config/float-i128.h
deleted file mode 100755
index 6a9dd48..0000000
--- a/gcc/config/float-i128.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* float.h for target with IEEE 32, 64 and 128 bit floating point formats */
-#ifndef _FLOAT_H_
-#define _FLOAT_H_
-/* Produced by enquire version 4.3, CWI, Amsterdam */
-
-   /* Radix of exponent representation */
-#undef FLT_RADIX
-#define FLT_RADIX 2
-   /* Number of base-FLT_RADIX digits in the significand of a float */
-#undef FLT_MANT_DIG
-#define FLT_MANT_DIG 24
-   /* Number of decimal digits of precision in a float */
-#undef FLT_DIG
-#define FLT_DIG 6
-   /* Addition rounds to 0: zero, 1: nearest, 2: +inf, 3: -inf, -1: unknown */
-#undef FLT_ROUNDS
-#define FLT_ROUNDS 1
-   /* Difference between 1.0 and the minimum float greater than 1.0 */
-#undef FLT_EPSILON
-#define FLT_EPSILON 1.19209290e-07F
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised float */
-#undef FLT_MIN_EXP
-#define FLT_MIN_EXP (-125)
-   /* Minimum normalised float */
-#undef FLT_MIN
-#define FLT_MIN 1.17549435e-38F
-   /* Minimum int x such that 10**x is a normalised float */
-#undef FLT_MIN_10_EXP
-#define FLT_MIN_10_EXP (-37)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable float */
-#undef FLT_MAX_EXP
-#define FLT_MAX_EXP 128
-   /* Maximum float */
-#undef FLT_MAX
-#define FLT_MAX 3.40282347e+38F
-   /* Maximum int x such that 10**x is a representable float */
-#undef FLT_MAX_10_EXP
-#define FLT_MAX_10_EXP 38
-
-   /* Number of base-FLT_RADIX digits in the significand of a double */
-#undef DBL_MANT_DIG
-#define DBL_MANT_DIG 53
-   /* Number of decimal digits of precision in a double */
-#undef DBL_DIG
-#define DBL_DIG 15
-   /* Difference between 1.0 and the minimum double greater than 1.0 */
-#undef DBL_EPSILON
-#define DBL_EPSILON 2.2204460492503131e-16
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised double */
-#undef DBL_MIN_EXP
-#define DBL_MIN_EXP (-1021)
-   /* Minimum normalised double */
-#undef DBL_MIN
-#define DBL_MIN 2.2250738585072014e-308
-   /* Minimum int x such that 10**x is a normalised double */
-#undef DBL_MIN_10_EXP
-#define DBL_MIN_10_EXP (-307)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable double */
-#undef DBL_MAX_EXP
-#define DBL_MAX_EXP 1024
-   /* Maximum double */
-#undef DBL_MAX
-#define DBL_MAX 1.7976931348623157e+308
-   /* Maximum int x such that 10**x is a representable double */
-#undef DBL_MAX_10_EXP
-#define DBL_MAX_10_EXP 308
-
-   /* Number of base-FLT_RADIX digits in the significand of a long double */
-#undef LDBL_MANT_DIG
-#define LDBL_MANT_DIG 113
-   /* Number of decimal digits of precision in a long double */
-#undef LDBL_DIG
-#define LDBL_DIG 33
-   /* Difference between 1.0 and the minimum long double greater than 1.0 */
-#undef LDBL_EPSILON
-#define LDBL_EPSILON 1.925929944387235853055977942584927319E-34L
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised long double */
-#undef LDBL_MIN_EXP
-#define LDBL_MIN_EXP (-16381)
-   /* Minimum normalised long double */
-#undef LDBL_MIN
-#define LDBL_MIN 3.362103143112093506262677817321752603E-4932L
-   /* Minimum int x such that 10**x is a normalised long double */
-#undef LDBL_MIN_10_EXP
-#define LDBL_MIN_10_EXP (-4931)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable long double */
-#undef LDBL_MAX_EXP
-#define LDBL_MAX_EXP 16384
-   /* Maximum long double */
-#undef LDBL_MAX
-#define LDBL_MAX 1.189731495357231765085759326628007016E+4932L
-   /* Maximum int x such that 10**x is a representable long double */
-#undef LDBL_MAX_10_EXP
-#define LDBL_MAX_10_EXP 4932
-
-#endif /*  _FLOAT_H_ */
diff --git a/gcc/config/float-i32.h b/gcc/config/float-i32.h
deleted file mode 100755
index c834926..0000000
--- a/gcc/config/float-i32.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* float.h for target with only IEEE 32 bit floating point format */
-#ifndef _FLOAT_H_
-#define _FLOAT_H_
-/* Produced by enquire version 4.3, CWI, Amsterdam */
-
-   /* Radix of exponent representation */
-#undef FLT_RADIX
-#define FLT_RADIX 2
-   /* Number of base-FLT_RADIX digits in the significand of a float */
-#undef FLT_MANT_DIG
-#define FLT_MANT_DIG 24
-   /* Number of decimal digits of precision in a float */
-#undef FLT_DIG
-#define FLT_DIG 6
-   /* Addition rounds to 0: zero, 1: nearest, 2: +inf, 3: -inf, -1: unknown */
-#undef FLT_ROUNDS
-#define FLT_ROUNDS 1
-   /* Difference between 1.0 and the minimum float greater than 1.0 */
-#undef FLT_EPSILON
-#define FLT_EPSILON 1.19209290e-07F
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised float */
-#undef FLT_MIN_EXP
-#define FLT_MIN_EXP (-125)
-   /* Minimum normalised float */
-#undef FLT_MIN
-#define FLT_MIN 1.17549435e-38F
-   /* Minimum int x such that 10**x is a normalised float */
-#undef FLT_MIN_10_EXP
-#define FLT_MIN_10_EXP (-37)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable float */
-#undef FLT_MAX_EXP
-#define FLT_MAX_EXP 128
-   /* Maximum float */
-#undef FLT_MAX
-#define FLT_MAX 3.40282347e+38F
-   /* Maximum int x such that 10**x is a representable float */
-#undef FLT_MAX_10_EXP
-#define FLT_MAX_10_EXP 38
-
-   /* Number of base-FLT_RADIX digits in the significand of a double */
-#undef DBL_MANT_DIG
-#define DBL_MANT_DIG 24
-   /* Number of decimal digits of precision in a double */
-#undef DBL_DIG
-#define DBL_DIG 6
-   /* Difference between 1.0 and the minimum double greater than 1.0 */
-#undef DBL_EPSILON
-#define DBL_EPSILON 1.19209290e-07F
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised double */
-#undef DBL_MIN_EXP
-#define DBL_MIN_EXP (-125)
-   /* Minimum normalised double */
-#undef DBL_MIN
-#define DBL_MIN 1.17549435e-38F
-   /* Minimum int x such that 10**x is a normalised double */
-#undef DBL_MIN_10_EXP
-#define DBL_MIN_10_EXP (-37)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable double */
-#undef DBL_MAX_EXP
-#define DBL_MAX_EXP 128
-   /* Maximum double */
-#undef DBL_MAX
-#define DBL_MAX 3.40282347e+38F
-   /* Maximum int x such that 10**x is a representable double */
-#undef DBL_MAX_10_EXP
-#define DBL_MAX_10_EXP 38
-
-   /* Number of base-FLT_RADIX digits in the significand of a long double */
-#undef LDBL_MANT_DIG
-#define LDBL_MANT_DIG 24
-   /* Number of decimal digits of precision in a long double */
-#undef LDBL_DIG
-#define LDBL_DIG 6
-   /* Difference between 1.0 and the minimum long double greater than 1.0 */
-#undef LDBL_EPSILON
-#define LDBL_EPSILON 1.19209290e-07F
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised long double */
-#undef LDBL_MIN_EXP
-#define LDBL_MIN_EXP (-125)
-   /* Minimum normalised long double */
-#undef LDBL_MIN
-#define LDBL_MIN 1.17549435e-38F
-   /* Minimum int x such that 10**x is a normalised long double */
-#undef LDBL_MIN_10_EXP
-#define LDBL_MIN_10_EXP (-37)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable long double */
-#undef LDBL_MAX_EXP
-#define LDBL_MAX_EXP 128
-   /* Maximum long double */
-#undef LDBL_MAX
-#define LDBL_MAX 3.40282347e+38F
-   /* Maximum int x such that 10**x is a representable long double */
-#undef LDBL_MAX_10_EXP
-#define LDBL_MAX_10_EXP 38
-
-#endif /*  _FLOAT_H_ */
diff --git a/gcc/config/float-i386.h b/gcc/config/float-i386.h
deleted file mode 100755
index 2d14f70..0000000
--- a/gcc/config/float-i386.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* float.h for target with IEEE 32/64 bit and Intel 386 style 80 bit
-   floating point formats */
-#ifndef _FLOAT_H_
-#define _FLOAT_H_
-/* Produced by enquire version 4.3, CWI, Amsterdam */
-
-   /* Radix of exponent representation */
-#undef FLT_RADIX
-#define FLT_RADIX 2
-   /* Number of base-FLT_RADIX digits in the significand of a float */
-#undef FLT_MANT_DIG
-#define FLT_MANT_DIG 24
-   /* Number of decimal digits of precision in a float */
-#undef FLT_DIG
-#define FLT_DIG 6
-   /* Addition rounds to 0: zero, 1: nearest, 2: +inf, 3: -inf, -1: unknown */
-#undef FLT_ROUNDS
-#define FLT_ROUNDS 1
-   /* Difference between 1.0 and the minimum float greater than 1.0 */
-#undef FLT_EPSILON
-#define FLT_EPSILON 1.19209290e-07F
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised float */
-#undef FLT_MIN_EXP
-#define FLT_MIN_EXP (-125)
-   /* Minimum normalised float */
-#undef FLT_MIN
-#define FLT_MIN 1.17549435e-38F
-   /* Minimum int x such that 10**x is a normalised float */
-#undef FLT_MIN_10_EXP
-#define FLT_MIN_10_EXP (-37)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable float */
-#undef FLT_MAX_EXP
-#define FLT_MAX_EXP 128
-   /* Maximum float */
-#undef FLT_MAX
-#define FLT_MAX 3.40282347e+38F
-   /* Maximum int x such that 10**x is a representable float */
-#undef FLT_MAX_10_EXP
-#define FLT_MAX_10_EXP 38
-
-   /* Number of base-FLT_RADIX digits in the significand of a double */
-#undef DBL_MANT_DIG
-#define DBL_MANT_DIG 53
-   /* Number of decimal digits of precision in a double */
-#undef DBL_DIG
-#define DBL_DIG 15
-   /* Difference between 1.0 and the minimum double greater than 1.0 */
-#undef DBL_EPSILON
-#define DBL_EPSILON 2.2204460492503131e-16
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised double */
-#undef DBL_MIN_EXP
-#define DBL_MIN_EXP (-1021)
-   /* Minimum normalised double */
-#undef DBL_MIN
-#define DBL_MIN 2.2250738585072014e-308
-   /* Minimum int x such that 10**x is a normalised double */
-#undef DBL_MIN_10_EXP
-#define DBL_MIN_10_EXP (-307)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable double */
-#undef DBL_MAX_EXP
-#define DBL_MAX_EXP 1024
-   /* Maximum double */
-#undef DBL_MAX
-#define DBL_MAX 1.7976931348623157e+308
-   /* Maximum int x such that 10**x is a representable double */
-#undef DBL_MAX_10_EXP
-#define DBL_MAX_10_EXP 308
-
-   /* Number of base-FLT_RADIX digits in the significand of a long double */
-#undef LDBL_MANT_DIG
-#define LDBL_MANT_DIG 64
-   /* Number of decimal digits of precision in a long double */
-#undef LDBL_DIG
-#define LDBL_DIG 18
-   /* Difference between 1.0 and the minimum long double greater than 1.0 */
-#undef LDBL_EPSILON
-#ifndef __LDBL_UNION__
-#define __LDBL_UNION__
-union __convert_long_double {
-  unsigned __convert_long_double_i[4];
-  long double __convert_long_double_d;
-};
-#endif
-#define LDBL_EPSILON (__extension__ ((union __convert_long_double) {__convert_long_double_i: {0x0, 0x80000000, 0x3fc0, 0x0}}).__convert_long_double_d)
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised long double */
-#undef LDBL_MIN_EXP
-#define LDBL_MIN_EXP (-16381)
-   /* Minimum normalised long double */
-#undef LDBL_MIN
-#define LDBL_MIN (__extension__ ((union __convert_long_double) {__convert_long_double_i: {0x0, 0x80000000, 0x1, 0x0}}).__convert_long_double_d)
-   /* Minimum int x such that 10**x is a normalised long double */
-#undef LDBL_MIN_10_EXP
-#define LDBL_MIN_10_EXP (-4931)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable long double */
-#undef LDBL_MAX_EXP
-#define LDBL_MAX_EXP 16384
-   /* Maximum long double */
-#undef LDBL_MAX
-#define LDBL_MAX (__extension__ ((union __convert_long_double) {__convert_long_double_i: {0xffffffff, 0xffffffff, 0x107ffe, 0x0}}).__convert_long_double_d)
-   /* Maximum int x such that 10**x is a representable long double */
-#undef LDBL_MAX_10_EXP
-#define LDBL_MAX_10_EXP 4932
-
-#endif /*  _FLOAT_H___ */
diff --git a/gcc/config/float-m68k.h b/gcc/config/float-m68k.h
deleted file mode 100755
index b36d447..0000000
--- a/gcc/config/float-m68k.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* float.h for target with IEEE 32 bit and 64 bit and Motorola style 96 bit
-   floating point formats */
-#ifndef _FLOAT_H_
-#define _FLOAT_H_
-/* Produced by enquire version 4.3, CWI, Amsterdam */
-
-   /* Radix of exponent representation */
-#undef FLT_RADIX
-#define FLT_RADIX 2
-   /* Number of base-FLT_RADIX digits in the significand of a float */
-#undef FLT_MANT_DIG
-#define FLT_MANT_DIG 24
-   /* Number of decimal digits of precision in a float */
-#undef FLT_DIG
-#define FLT_DIG 6
-   /* Addition rounds to 0: zero, 1: nearest, 2: +inf, 3: -inf, -1: unknown */
-#undef FLT_ROUNDS
-#define FLT_ROUNDS 1
-   /* Difference between 1.0 and the minimum float greater than 1.0 */
-#undef FLT_EPSILON
-#define FLT_EPSILON 1.19209290e-07F
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised float */
-#undef FLT_MIN_EXP
-#define FLT_MIN_EXP (-125)
-   /* Minimum normalised float */
-#undef FLT_MIN
-#define FLT_MIN 1.17549435e-38F
-   /* Minimum int x such that 10**x is a normalised float */
-#undef FLT_MIN_10_EXP
-#define FLT_MIN_10_EXP (-37)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable float */
-#undef FLT_MAX_EXP
-#define FLT_MAX_EXP 128
-   /* Maximum float */
-#undef FLT_MAX
-#define FLT_MAX 3.40282347e+38F
-   /* Maximum int x such that 10**x is a representable float */
-#undef FLT_MAX_10_EXP
-#define FLT_MAX_10_EXP 38
-
-   /* Number of base-FLT_RADIX digits in the significand of a double */
-#undef DBL_MANT_DIG
-#define DBL_MANT_DIG 53
-   /* Number of decimal digits of precision in a double */
-#undef DBL_DIG
-#define DBL_DIG 15
-   /* Difference between 1.0 and the minimum double greater than 1.0 */
-#undef DBL_EPSILON
-#define DBL_EPSILON 2.2204460492503131e-16
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised double */
-#undef DBL_MIN_EXP
-#define DBL_MIN_EXP (-1021)
-   /* Minimum normalised double */
-#undef DBL_MIN
-#define DBL_MIN 2.2250738585072014e-308
-   /* Minimum int x such that 10**x is a normalised double */
-#undef DBL_MIN_10_EXP
-#define DBL_MIN_10_EXP (-307)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable double */
-#undef DBL_MAX_EXP
-#define DBL_MAX_EXP 1024
-   /* Maximum double */
-#undef DBL_MAX
-#define DBL_MAX 1.7976931348623157e+308
-   /* Maximum int x such that 10**x is a representable double */
-#undef DBL_MAX_10_EXP
-#define DBL_MAX_10_EXP 308
-
-   /* Number of base-FLT_RADIX digits in the significand of a long double */
-#undef LDBL_MANT_DIG
-#define LDBL_MANT_DIG 64
-   /* Number of decimal digits of precision in a long double */
-#undef LDBL_DIG
-#define LDBL_DIG 18
-   /* Difference between 1.0 and the minimum long double greater than 1.0 */
-#undef LDBL_EPSILON
-#define LDBL_EPSILON 1.08420217248550443401e-19L
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised long double */
-#undef LDBL_MIN_EXP
-#define LDBL_MIN_EXP (-16382)
-   /* Minimum normalised long double */
-#undef LDBL_MIN
-#define LDBL_MIN 1.68105157155604675313e-4932L
-   /* Minimum int x such that 10**x is a normalised long double */
-#undef LDBL_MIN_10_EXP
-#define LDBL_MIN_10_EXP (-4931)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable long double */
-#undef LDBL_MAX_EXP
-#define LDBL_MAX_EXP 16384
-   /* Maximum long double */
-#undef LDBL_MAX
-#define LDBL_MAX 1.18973149535723176502e+4932L
-   /* Maximum int x such that 10**x is a representable long double */
-#undef LDBL_MAX_10_EXP
-#define LDBL_MAX_10_EXP 4932
-
-#endif /*  _FLOAT_H_ */
diff --git a/gcc/config/float-sh.h b/gcc/config/float-sh.h
deleted file mode 100755
index 4466924..0000000
--- a/gcc/config/float-sh.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* float.h for target sh3e with optional IEEE 32 bit double format */
-#ifndef _FLOAT_H_
-#define _FLOAT_H_
-/* Produced by enquire version 4.3, CWI, Amsterdam */
-
-   /* Radix of exponent representation */
-#undef FLT_RADIX
-#define FLT_RADIX 2
-   /* Number of base-FLT_RADIX digits in the significand of a float */
-#undef FLT_MANT_DIG
-#define FLT_MANT_DIG 24
-   /* Number of decimal digits of precision in a float */
-#undef FLT_DIG
-#define FLT_DIG 6
-   /* Addition rounds to 0: zero, 1: nearest, 2: +inf, 3: -inf, -1: unknown */
-#undef FLT_ROUNDS
-#define FLT_ROUNDS 1
-   /* Difference between 1.0 and the minimum float greater than 1.0 */
-#undef FLT_EPSILON
-#define FLT_EPSILON 1.19209290e-07F
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised float */
-#undef FLT_MIN_EXP
-#define FLT_MIN_EXP (-125)
-   /* Minimum normalised float */
-#undef FLT_MIN
-#define FLT_MIN 1.17549435e-38F
-   /* Minimum int x such that 10**x is a normalised float */
-#undef FLT_MIN_10_EXP
-#define FLT_MIN_10_EXP (-37)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable float */
-#undef FLT_MAX_EXP
-#define FLT_MAX_EXP 128
-   /* Maximum float */
-#undef FLT_MAX
-#define FLT_MAX 3.40282347e+38F
-   /* Maximum int x such that 10**x is a representable float */
-#undef FLT_MAX_10_EXP
-#define FLT_MAX_10_EXP 38
-
-#if defined (__SH3E__) || defined (__SH4_SINGLE_ONLY__)
-
-   /* Number of base-FLT_RADIX digits in the significand of a double */
-#undef DBL_MANT_DIG
-#define DBL_MANT_DIG 24
-   /* Number of decimal digits of precision in a double */
-#undef DBL_DIG
-#define DBL_DIG 6
-   /* Difference between 1.0 and the minimum double greater than 1.0 */
-#undef DBL_EPSILON
-#define DBL_EPSILON 1.19209290e-07F
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised double */
-#undef DBL_MIN_EXP
-#define DBL_MIN_EXP (-125)
-   /* Minimum normalised double */
-#undef DBL_MIN
-#define DBL_MIN 1.17549435e-38F
-   /* Minimum int x such that 10**x is a normalised double */
-#undef DBL_MIN_10_EXP
-#define DBL_MIN_10_EXP (-37)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable double */
-#undef DBL_MAX_EXP
-#define DBL_MAX_EXP 128
-   /* Maximum double */
-#undef DBL_MAX
-#define DBL_MAX 3.40282347e+38F
-   /* Maximum int x such that 10**x is a representable double */
-#undef DBL_MAX_10_EXP
-#define DBL_MAX_10_EXP 38
-
-#else
-
-   /* Number of base-FLT_RADIX digits in the significand of a double */
-#undef DBL_MANT_DIG
-#define DBL_MANT_DIG 53
-   /* Number of decimal digits of precision in a double */
-#undef DBL_DIG
-#define DBL_DIG 15
-   /* Difference between 1.0 and the minimum double greater than 1.0 */
-#undef DBL_EPSILON
-#define DBL_EPSILON 2.2204460492503131e-16
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised double */
-#undef DBL_MIN_EXP
-#define DBL_MIN_EXP (-1021)
-   /* Minimum normalised double */
-#undef DBL_MIN
-#define DBL_MIN 2.2250738585072014e-308
-   /* Minimum int x such that 10**x is a normalised double */
-#undef DBL_MIN_10_EXP
-#define DBL_MIN_10_EXP (-307)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable double */
-#undef DBL_MAX_EXP
-#define DBL_MAX_EXP 1024
-   /* Maximum double */
-#undef DBL_MAX
-#define DBL_MAX 1.7976931348623157e+308
-   /* Maximum int x such that 10**x is a representable double */
-#undef DBL_MAX_10_EXP
-#define DBL_MAX_10_EXP 308
-
-#endif
-
-   /* Number of base-FLT_RADIX digits in the significand of a long double */
-#undef LDBL_MANT_DIG
-#define LDBL_MANT_DIG 53
-   /* Number of decimal digits of precision in a long double */
-#undef LDBL_DIG
-#define LDBL_DIG 15
-   /* Difference between 1.0 and the minimum long double greater than 1.0 */
-#undef LDBL_EPSILON
-#define LDBL_EPSILON 2.2204460492503131e-16
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised long double */
-#undef LDBL_MIN_EXP
-#define LDBL_MIN_EXP (-1021)
-   /* Minimum normalised long double */
-#undef LDBL_MIN
-#define LDBL_MIN 2.2250738585072014e-308
-   /* Minimum int x such that 10**x is a normalised long double */
-#undef LDBL_MIN_10_EXP
-#define LDBL_MIN_10_EXP (-307)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable long double */
-#undef LDBL_MAX_EXP
-#define LDBL_MAX_EXP 1024
-   /* Maximum long double */
-#undef LDBL_MAX
-#define LDBL_MAX 1.7976931348623157e+308
-   /* Maximum int x such that 10**x is a representable long double */
-#undef LDBL_MAX_10_EXP
-#define LDBL_MAX_10_EXP 308
-
-#endif /*  _FLOAT_H_ */
diff --git a/gcc/config/float-vax.h b/gcc/config/float-vax.h
deleted file mode 100755
index 3c87f79..0000000
--- a/gcc/config/float-vax.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* float.h for target with VAX floating point formats */
-#ifndef _FLOAT_H_
-#define _FLOAT_H_
-/* Produced by enquire version 4.3, CWI, Amsterdam */
-
-   /* Radix of exponent representation */
-#undef FLT_RADIX
-#define FLT_RADIX 2
-   /* Number of base-FLT_RADIX digits in the significand of a float */
-#undef FLT_MANT_DIG
-#define FLT_MANT_DIG 24
-   /* Number of decimal digits of precision in a float */
-#undef FLT_DIG
-#define FLT_DIG 6
-   /* Addition rounds to 0: zero, 1: nearest, 2: +inf, 3: -inf, -1: unknown */
-#undef FLT_ROUNDS
-#define FLT_ROUNDS 1
-   /* Difference between 1.0 and the minimum float greater than 1.0 */
-#undef FLT_EPSILON
-#define FLT_EPSILON 1.19209290e-07F
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised float */
-#undef FLT_MIN_EXP
-#define FLT_MIN_EXP (-127)
-   /* Minimum normalised float */
-#undef FLT_MIN
-#define FLT_MIN 2.93873588e-39F
-   /* Minimum int x such that 10**x is a normalised float */
-#undef FLT_MIN_10_EXP
-#define FLT_MIN_10_EXP (-38)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable float */
-#undef FLT_MAX_EXP
-#define FLT_MAX_EXP 127
-   /* Maximum float */
-#undef FLT_MAX
-#define FLT_MAX 1.70141173e+38F
-   /* Maximum int x such that 10**x is a representable float */
-#undef FLT_MAX_10_EXP
-#define FLT_MAX_10_EXP 38
-
-   /* Number of base-FLT_RADIX digits in the significand of a double */
-#undef DBL_MANT_DIG
-#define DBL_MANT_DIG 56
-   /* Number of decimal digits of precision in a double */
-#undef DBL_DIG
-#define DBL_DIG 16
-   /* Difference between 1.0 and the minimum double greater than 1.0 */
-#undef DBL_EPSILON
-#define DBL_EPSILON 2.77555756156289135e-17
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised double */
-#undef DBL_MIN_EXP
-#define DBL_MIN_EXP (-127)
-   /* Minimum normalised double */
-#undef DBL_MIN
-#define DBL_MIN 2.93873587705571877e-39
-   /* Minimum int x such that 10**x is a normalised double */
-#undef DBL_MIN_10_EXP
-#define DBL_MIN_10_EXP (-38)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable double */
-#undef DBL_MAX_EXP
-#define DBL_MAX_EXP 127
-   /* Maximum double */
-#undef DBL_MAX
-#define DBL_MAX 1.70141183460469229e+38
-   /* Maximum int x such that 10**x is a representable double */
-#undef DBL_MAX_10_EXP
-#define DBL_MAX_10_EXP 38
-
-   /* Number of base-FLT_RADIX digits in the significand of a long double */
-#undef LDBL_MANT_DIG
-#define LDBL_MANT_DIG 56
-   /* Number of decimal digits of precision in a long double */
-#undef LDBL_DIG
-#define LDBL_DIG 16
-   /* Difference between 1.0 and the minimum long double greater than 1.0 */
-#undef LDBL_EPSILON
-#define LDBL_EPSILON 2.77555756156289135e-17
-   /* Minimum int x such that FLT_RADIX**(x-1) is a normalised long double */
-#undef LDBL_MIN_EXP
-#define LDBL_MIN_EXP (-127)
-   /* Minimum normalised long double */
-#undef LDBL_MIN
-#define LDBL_MIN 2.93873587705571877e-39
-   /* Minimum int x such that 10**x is a normalised long double */
-#undef LDBL_MIN_10_EXP
-#define LDBL_MIN_10_EXP (-38)
-   /* Maximum int x such that FLT_RADIX**(x-1) is a representable long double */
-#undef LDBL_MAX_EXP
-#define LDBL_MAX_EXP 127
-   /* Maximum long double */
-#undef LDBL_MAX
-#define LDBL_MAX 1.70141183460469229e+38
-   /* Maximum int x such that 10**x is a representable long double */
-#undef LDBL_MAX_10_EXP
-#define LDBL_MAX_10_EXP 38
-
-#endif /*  _FLOAT_H_ */
diff --git a/gcc/config/fr30/crti.asm b/gcc/config/fr30/crti.asm
deleted file mode 100755
index 9182366..0000000
--- a/gcc/config/fr30/crti.asm
+++ /dev/null
@@ -1,75 +0,0 @@
-# crti.s for ELF
-
-#   Copyright (C) 1992, 1998 Free Software Foundation, Inc.
-#   Written By David Vinayak Henkel-Wallace, June 1992
-# 
-# This file is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License as published by the
-# Free Software Foundation; either version 2, or (at your option) any
-# later version.
-# 
-# In addition to the permissions in the GNU General Public License, the
-# Free Software Foundation gives you unlimited permission to link the
-# compiled version of this file with other programs, and to distribute
-# those programs without any restriction coming from the use of this
-# file.  (The General Public License restrictions do apply in other
-# respects; for example, they cover modification of the file, and
-# distribution when not linked into another program.)
-# 
-# This file is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-# General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with this program; see the file COPYING.  If not, write to
-# the Free Software Foundation, 59 Temple Place - Suite 330,
-# Boston, MA 02111-1307, USA.
-# 
-#    As a special exception, if you link this library with files
-#    compiled with GCC to produce an executable, this does not cause
-#    the resulting executable to be covered by the GNU General Public License.
-#    This exception does not however invalidate any other reasons why
-#    the executable file might be covered by the GNU General Public License.
-# 
-
-# This file just make a stack frame for the contents of the .fini and
-# .init sections.  Users may put any desired instructions in those
-# sections.
-
-	.file		"crti.asm"
-
-	.section	".init"
-	.global	_init
-	.type	_init,#function
-	.align	4
-_init:
-	st	rp, @-r15
-	enter	#0
-
-	# These nops are here to align the end of this code with a 16 byte
-	# boundary.  The linker will start inserting code into the .init
-	# section at such a boundary.
-	
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	
-	.section	".fini"
-	.global	_fini
-	.type	_fini,#function
-	.align	4
-_fini:
-	st	rp, @-r15
-	enter	#0
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	
\ No newline at end of file
diff --git a/gcc/config/fr30/crtn.asm b/gcc/config/fr30/crtn.asm
deleted file mode 100755
index 93b52c2..0000000
--- a/gcc/config/fr30/crtn.asm
+++ /dev/null
@@ -1,57 +0,0 @@
-# crtn.asm for ELF 
-
-#   Copyright (C) 1992, 1999 Free Software Foundation, Inc.
-#   Written By David Vinayak Henkel-Wallace, June 1992
-# 
-# This file is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License as published by the
-# Free Software Foundation; either version 2, or (at your option) any
-# later version.
-# 
-# In addition to the permissions in the GNU General Public License, the
-# Free Software Foundation gives you unlimited permission to link the
-# compiled version of this file with other programs, and to distribute
-# those programs without any restriction coming from the use of this
-# file.  (The General Public License restrictions do apply in other
-# respects; for example, they cover modification of the file, and
-# distribution when not linked into another program.)
-# 
-# This file is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-# General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with this program; see the file COPYING.  If not, write to
-# the Free Software Foundation, 59 Temple Place - Suite 330,
-# Boston, MA 02111-1307, USA.
-# 
-#    As a special exception, if you link this library with files
-#    compiled with GCC to produce an executable, this does not cause
-#    the resulting executable to be covered by the GNU General Public License.
-#    This exception does not however invalidate any other reasons why
-#    the executable file might be covered by the GNU General Public License.
-# 
-
-# This file just makes sure that the .fini and .init sections do in
-# fact return.  Users may put any desired instructions in those sections.
-# This file is the last thing linked into any executable.
-
-	.file		"crtn.s"
-
-	.section	".init"
-	.align		4
-
-	leave
-	ld @r15+,rp
-	ret
-
-	
-	.section	".fini"
-	.align		4
-
-	leave
-	ld @r15+,rp
-	ret
-
-# Th-th-th-that is all folks!
diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c
deleted file mode 100755
index dcf8a39..0000000
--- a/gcc/config/fr30/fr30.c
+++ /dev/null
@@ -1,804 +0,0 @@
-/* CYGNUS LOCAL -- nickc/fr30 */
-
-/*{{{  Introduction */ 
-
-/* FR30 specific functions.
-   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
-   Contributed by Cygnus Solutions.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/*}}}*/
-/*{{{  Includes */ 
-
-#include <stdio.h>
-#include <ctype.h>
-#include <sys/param.h> /* so that MIn and MAX are defined before machmode.h */
-#include "config.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#include "expr.h"
-#include "obstack.h"
-#include "tree.h"
-#include "except.h"
-#include "function.h"
-
-/*}}}*/
-/*{{{  Function Prologues & Epilogues */ 
-
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  */
-
-struct rtx_def * fr30_compare_op0;
-struct rtx_def * fr30_compare_op1;
-
-/* The FR30 stack looks like this:
-
-             Before call                       After call
-   FP ->|                       |       |                       |
-        +-----------------------+       +-----------------------+       high 
-        |                       |       |                       |       memory
-        |  local variables,     |       |  local variables,     |
-        |  reg save area, etc.  |       |  reg save area, etc.  |
-        |                       |       |                       |
-        +-----------------------+       +-----------------------+
-        |                       |       |                       |
-        | args to the func that |       |  args to this func.   |
-        | is being called that  |       |                       |
-   SP ->| do not fit in regs    |       |                       |
-        +-----------------------+       +-----------------------+
-                                        |  args that used to be |  \
-                                        | in regs; only created |   |  pretend_size 
-                                   AP-> |   for vararg funcs    |  /  
-                                        +-----------------------+    
-                                        |                       |  \  
-                                        |  register save area   |   |
-                                        |                       |   |
-					+-----------------------+   |  reg_size
-                                        |    return address     |   | 
-					+-----------------------+   |
-                                   FP ->|   previous frame ptr  |  /
-                                        +-----------------------+    
-                                        |                       |  \   
-                                        |  local variables      |   |  var_size 
-                                        |                       |  /  
-                                        +-----------------------+    
-                                        |                       |  \       
-     low                                |  room for args to     |   |
-     memory                             |  other funcs called   |   |  args_size     
-                                        |  from this one        |   |
-                                   SP ->|                       |  /  
-                                        +-----------------------+    
-   
-   Note, AP is a fake hard register.  It will be eliminated in favour of
-   SP or FP as appropriate.
-
-   Note, Some or all of the stack sections above may be omitted if they 
-   are not needed.  */
-
-/* Structure to be filled in by fr30_compute_frame_size() with register
-   save masks, and offsets for the current function.  */
-struct fr30_frame_info
-{
-  unsigned int total_size;	/* # Bytes that the entire frame takes up. */
-  unsigned int pretend_size;	/* # Bytes we push and pretend caller did. */
-  unsigned int args_size;	/* # Bytes that outgoing arguments take up. */
-  unsigned int reg_size;	/* # Bytes needed to store regs. */
-  unsigned int var_size;	/* # Bytes that variables take up. */
-  unsigned int frame_size;      /* # Bytes in current frame.  */
-  unsigned int gmask;		/* Mask of saved registers. */
-  unsigned int save_fp;		/* Nonzero if frame pointer must be saved. */
-  unsigned int save_rp;		/* Nonzero if return popinter must be saved. */
-  int          initialised;	/* Nonzero if frame size already calculated. */
-};
-
-/* Current frame information calculated by fr30_compute_frame_size().  */
-static struct fr30_frame_info 	current_frame_info;
-
-/* Zero structure to initialize current_frame_info.  */
-static struct fr30_frame_info 	zero_frame_info;
-
-#define FRAME_POINTER_MASK 	(1 << (FRAME_POINTER_REGNUM))
-#define RETURN_POINTER_MASK 	(1 << (RETURN_POINTER_REGNUM))
-
-/* Tell prologue and epilogue if register REGNO should be saved / restored.
-   The return address and frame pointer are treated separately.
-   Don't consider them here.  */
-#define MUST_SAVE_REGISTER(regno)      \
-  (   (regno) != RETURN_POINTER_REGNUM \
-   && (regno) != FRAME_POINTER_REGNUM  \
-   &&   regs_ever_live [regno]         \
-   && ! call_used_regs [regno]         )
-
-#define MUST_SAVE_FRAME_POINTER	 (regs_ever_live [FRAME_POINTER_REGNUM]  || frame_pointer_needed)
-#define MUST_SAVE_RETURN_POINTER (regs_ever_live [RETURN_POINTER_REGNUM] || profile_flag)
-
-#if UNITS_PER_WORD == 4
-#define WORD_ALIGN(SIZE) (((SIZE) + 3) & ~3)
-#endif
-     
-/* Returns the number of bytes offset between FROM_REG and TO_REG
-   for the current function.  As a side effect it fills in the 
-   current_frame_info structure, if the data is available.  */
-unsigned int
-fr30_compute_frame_size (from_reg, to_reg)
-     int from_reg;
-     int to_reg;
-{
-  int 		regno;
-  unsigned int 	return_value;
-  unsigned int	var_size;
-  unsigned int	args_size;
-  unsigned int	pretend_size;
-  unsigned int	extra_size;
-  unsigned int 	reg_size;
-  unsigned int 	gmask;
-
-  var_size	= WORD_ALIGN (get_frame_size ());
-  args_size	= WORD_ALIGN (current_function_outgoing_args_size);
-  pretend_size	= current_function_pretend_args_size;
-
-  reg_size	= 0;
-  gmask		= 0;
-
-  /* Calculate space needed for registers.  */
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++)
-    {
-      if (MUST_SAVE_REGISTER (regno))
-	{
-	  reg_size += UNITS_PER_WORD;
-	  gmask |= 1 << regno;
-	}
-    }
-
-  current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
-  current_frame_info.save_rp = MUST_SAVE_RETURN_POINTER;
-
-  reg_size += (current_frame_info.save_fp + current_frame_info.save_rp)
-	       * UNITS_PER_WORD;
-
-  /* Save computed information.  */
-  current_frame_info.pretend_size = pretend_size;
-  current_frame_info.var_size     = var_size;
-  current_frame_info.args_size    = args_size;
-  current_frame_info.reg_size	  = reg_size;
-  current_frame_info.frame_size   = args_size + var_size;
-  current_frame_info.total_size   = args_size + var_size + reg_size + pretend_size;
-  current_frame_info.gmask	  = gmask;
-  current_frame_info.initialised  = reload_completed;
-
-  /* Calculate the required distance.  */
-  return_value = 0;
-  
-  if (to_reg == STACK_POINTER_REGNUM)
-    return_value += args_size + var_size;
-  
-  if (from_reg == ARG_POINTER_REGNUM)
-    return_value += reg_size;
-
-  return return_value;
-}
-
-/* Called after register allocation to add any instructions needed for the
-   prologue.  Using a prologue insn is favored compared to putting all of the
-   instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
-   to intermix instructions with the saves of the caller saved registers.  In
-   some cases, it might be necessary to emit a barrier instruction as the last
-   insn to prevent such scheduling.  */
-
-void
-fr30_expand_prologue ()
-{
-  int regno;
-
-  if (! current_frame_info.initialised)
-    fr30_compute_frame_size (0, 0);
-
-  /* This cases shouldn't happen.  Catch it now.  */
-  if (current_frame_info.total_size == 0
-      && current_frame_info.gmask)
-    abort ();
-
-  /* Allocate space for register arguments if this is a variadic function.  */
-  if (current_frame_info.pretend_size)
-    {
-      int regs_to_save = current_frame_info.pretend_size / UNITS_PER_WORD;
-      
-      /* Push argument registers into the pretend arg area.  */
-      for (regno = FIRST_ARG_REGNUM + FR30_NUM_ARG_REGS; regno --, regs_to_save --;)
-	emit_insn (gen_movsi_push (gen_rtx_REG (Pmode, regno)));
-    }
-
-  if (current_frame_info.gmask)
-    {
-      /* Save any needed call-saved regs.  */
-      for (regno = STACK_POINTER_REGNUM; regno--;)
-	{
-	  if ((current_frame_info.gmask & (1 << regno)) != 0)
-	    emit_insn (gen_movsi_push (gen_rtx_REG (Pmode, regno)));
-	}
-    }
-
-  /* Save return address if necessary.  */
-  if (current_frame_info.save_rp)
-    emit_insn (gen_movsi_push (gen_rtx_REG (Pmode, RETURN_POINTER_REGNUM)));
-
-  /* Save old frame pointer and create new one, if necessary.  */
-  if (current_frame_info.save_fp)
-    {
-      if (current_frame_info.frame_size < ((1 << 10) - UNITS_PER_WORD))
-	emit_insn (gen_enter_func (GEN_INT (current_frame_info.frame_size + UNITS_PER_WORD)));
-      else
-	{
-	  emit_insn (gen_movsi_push (frame_pointer_rtx));
-	  emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
-	}
-    }
-
-  /* Allocate the stack frame.  */
-  if (current_frame_info.frame_size == 0)
-    ; /* Nothing to do.  */
-  else if (current_frame_info.save_fp
-	   && current_frame_info.frame_size < ((1 << 10) - UNITS_PER_WORD))
-    ; /* Nothing to do.  */
-  else if (current_frame_info.frame_size <= 512)
-    emit_insn (gen_add_to_stack (GEN_INT (- current_frame_info.frame_size)));
-  else
-    {
-      rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
-      emit_insn (gen_movsi (tmp, GEN_INT (current_frame_info.frame_size)));
-      emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
-    }
-
-  if (profile_flag || profile_block_flag)
-    emit_insn (gen_blockage ());
-}
-
-/* Called after register allocation to add any instructions needed for the
-   epilogue.  Using a epilogue insn is favored compared to putting all of the
-   instructions in the FUNCTION_EPILOGUE macro, since it allows the scheduler
-   to intermix instructions with the restores of the caller saved registers.
-   In some cases, it might be necessary to emit a barrier instruction as the
-   first insn to prevent such scheduling.  */
-void
-fr30_expand_epilogue ()
-{
-  int regno;
-
-  /* Perform the inversion operations of the prologue.  */
-  if (! current_frame_info.initialised)
-    abort ();
-
-  /* Pop local variables and arguments off the stack.
-     If frame_pointer_needed is TRUE then the frame pointer register
-     has actually been used as a frame pointer, and we can recover
-     the stack pointer from it, otherwise we must unwind the stack
-     manually.  */
-  if (current_frame_info.frame_size > 0)
-    {
-      if (current_frame_info.save_fp && frame_pointer_needed)
-	{
-	  emit_insn (gen_leave_func ());
-	  current_frame_info.save_fp = 0;
-	}
-      else if (current_frame_info.frame_size <= 508)
-	emit_insn (gen_add_to_stack
-		   (GEN_INT (current_frame_info.frame_size)));
-      else
-	{
-	  rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
-	  emit_insn (gen_movsi (tmp, GEN_INT (current_frame_info.frame_size)));
-	  emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
-	}
-    }
-  
-  if (current_frame_info.save_fp)
-    emit_insn (gen_movsi_pop (frame_pointer_rtx));
-  
-  /* Pop all the registers that were pushed.  */
-  if (current_frame_info.save_rp)
-    emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, RETURN_POINTER_REGNUM)));
-    
-  for (regno = 0; regno < STACK_POINTER_REGNUM; regno ++)
-    if (current_frame_info.gmask & (1 << regno))
-      emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, regno)));
-  
-  if (current_frame_info.pretend_size)
-    emit_insn (gen_add_to_stack (GEN_INT (current_frame_info.pretend_size)));
-
-  /* Reset state info for each function.  */
-  current_frame_info = zero_frame_info;
-
-  emit_insn (gen_return_from_func ());
-}
-
-/* Do any needed setup for a variadic function.  We must create a register
-   parameter block, and then copy any anonymous arguments, plus the last
-   named argument, from registers into memory.  * copying actually done in
-   fr30_expand_prologue().
-
-   ARG_REGS_USED_SO_FAR has *not* been updated for the last named argument
-   which has type TYPE and mode MODE, and we rely on this fact.  */
-void
-fr30_setup_incoming_varargs (arg_regs_used_so_far, int_mode, type, pretend_size)
-     CUMULATIVE_ARGS arg_regs_used_so_far;
-     int             int_mode;
-     tree            type;
-     int *           pretend_size;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-  int               first_anon_arg;
-  int               size;
-  rtx               regblock;
-
-  
-  /* All BLKmode values are passed by reference.  */
-  if (mode == BLKmode)
-    abort ();
-
-#if STRICT_ARGUMENT_NAMING
-  /* We must treat `__builtin_va_alist' as an anonymous arg.
-     But otherwise if STRICT_ARGUMENT_NAMING is true then the
-     last named arg must not be treated as an anonymous arg. */
-  if (! current_function_varargs)
-    arg_regs_used_so_far += fr30_num_arg_regs (int_mode, type);
-#endif
-  
-  size = FR30_NUM_ARG_REGS - arg_regs_used_so_far;
-
-  if (size <= 0)
-    return;
-
-  * pretend_size = (size * UNITS_PER_WORD);
-}
-
-/*}}}*/
-/*{{{  Printing operands */ 
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-void
-fr30_print_operand_address (stream, address)
-     FILE * stream;
-     rtx    address;
-{
-  switch (GET_CODE (address))
-    {
-    case SYMBOL_REF:
-      output_addr_const (stream, address);
-      break;
-      
-    default:
-      fprintf (stderr, "code = %x\n", GET_CODE (address));
-      debug_rtx (address);
-      output_operand_lossage ("fr30_print_operand_address: unhandled address");
-      break;
-    }
-}
-
-/* Print an operand.  */
-
-void
-fr30_print_operand (file, x, code)
-     FILE * file;
-     rtx    x;
-     int    code;
-{
-  rtx x0;
-  
-  switch (code)
-    {
-    case '#':
-      /* Output a :D if this instruction is delayed.  */
-      if (dbr_sequence_length () != 0)
-	fputs (":D", file);
-      return;
-      
-    case 'p':
-      /* Compute the register name of the second register in a hi/lo
-	 register pair.  */
-      if (GET_CODE (x) != REG)
-	output_operand_lossage ("fr30_print_operand: unrecognised %p code");
-      else
-	fprintf (file, "r%d", REGNO (x) + 1);
-      return;
-      
-    case 'b':
-      /* Convert GCC's comparison operators into FR30 comparison codes.  */
-      switch (GET_CODE (x))
-	{
-	case EQ:  fprintf (file, "eq"); break;
-	case NE:  fprintf (file, "ne"); break;
-	case LT:  fprintf (file, "lt"); break;
-	case LE:  fprintf (file, "le"); break;
-	case GT:  fprintf (file, "gt"); break;
-	case GE:  fprintf (file, "ge"); break;
-	case LTU: fprintf (file, "c"); break;
-	case LEU: fprintf (file, "ls"); break;
-	case GTU: fprintf (file, "hi"); break;
-	case GEU: fprintf (file, "nc");  break;
-	default:
-	  output_operand_lossage ("fr30_print_operand: unrecognised %b code");
-	  break;
-	}
-      return;
-      
-    case 'B':
-      /* Convert GCC's comparison operators into the complimentary FR30
-	 comparison codes.  */
-      switch (GET_CODE (x))
-	{
-	case EQ:  fprintf (file, "ne"); break;
-	case NE:  fprintf (file, "eq"); break;
-	case LT:  fprintf (file, "ge"); break;
-	case LE:  fprintf (file, "gt"); break;
-	case GT:  fprintf (file, "le"); break;
-	case GE:  fprintf (file, "lt"); break;
-	case LTU: fprintf (file, "nc"); break;
-	case LEU: fprintf (file, "hi"); break;
-	case GTU: fprintf (file, "ls"); break;
-	case GEU: fprintf (file, "c"); break;
-	default:
-	  output_operand_lossage ("fr30_print_operand: unrecognised %B code");
-	  break;
-	}
-      return;
-
-    case 'A':
-      /* Print a signed byte value as an unsigned value.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("fr30_print_operand: invalid operand to %A code");
-      else
-	{
-	  HOST_WIDE_INT val;
-	  
-	  val = INTVAL (x);
-
-	  val &= 0xff;
-
-	  fprintf (file, "%d", val);
-	}
-      return;
-      
-    case 'x':
-      if (GET_CODE (x) != CONST_INT
-	  || INTVAL (x) < 16
-	  || INTVAL (x) > 32)
-	output_operand_lossage ("fr30_print_operand: invalid %x code");
-      else
-	fprintf (file, "%d", INTVAL (x) - 16);
-      return;
-
-    case 'F':
-      if (GET_CODE (x) != CONST_DOUBLE)
-	output_operand_lossage ("fr30_print_operand: invalid %F code");
-      else
-	{
-	  REAL_VALUE_TYPE d;
-
-	  REAL_VALUE_FROM_CONST_DOUBLE (d, x);
-	  fprintf (file, "%.8f", d);
-	}
-      return;
-      
-    case 0:
-      /* Handled below.  */
-      break;
-      
-    default:
-      fprintf (stderr, "unknown code = %x\n", code);
-      output_operand_lossage ("fr30_print_operand: unknown code");
-      return;
-    }
-
-  switch (GET_CODE (x))
-    {
-    case REG:
-      fputs (reg_names [REGNO (x)], file);
-      break;
-
-    case MEM:
-      x0 = XEXP (x,0);
-      
-      switch (GET_CODE (x0))
-	{
-	case REG:
-	  if (REGNO (x0) >= (sizeof (reg_names) / sizeof (reg_names[0])))
-	    abort ();
-	  fprintf (file, "@%s", reg_names [REGNO (x0)]);
-	  break;
-
-	case PLUS:
-	  if (GET_CODE (XEXP (x0, 0)) != REG
-	      || REGNO (XEXP (x0, 0)) < FRAME_POINTER_REGNUM
-	      || REGNO (XEXP (x0, 0)) > STACK_POINTER_REGNUM
-	      || GET_CODE (XEXP (x0, 1)) != CONST_INT)
-	    {
-	      fprintf (stderr, "bad INDEXed address:");
-	      debug_rtx (x);
-	      output_operand_lossage ("fr30_print_operand: unhandled MEM");
-	    }
-	  else if (REGNO (XEXP (x0, 0)) == FRAME_POINTER_REGNUM)
-	    {
-	      HOST_WIDE_INT val = INTVAL (XEXP (x0, 1));
-	      if (val < -(1 << 9) || val > ((1 << 9) - 4))
-		{
-		  fprintf (stderr, "frame INDEX out of range:");
-		  debug_rtx (x);
-		  output_operand_lossage ("fr30_print_operand: unhandled MEM");
-		}
-	      fprintf (file, "@(r14, #%d)", val);
-	    }
-	  else
-	    {
-	      HOST_WIDE_INT val = INTVAL (XEXP (x0, 1));
-	      if (val < 0 || val > ((1 << 6) - 4))
-		{
-		  fprintf (stderr, "stack INDEX out of range:");
-		  debug_rtx (x);
-		  output_operand_lossage ("fr30_print_operand: unhandled MEM");
-		}
-	      fprintf (file, "@(r15, #%d)", val);
-	    }
-	  break;
-	  
-	case SYMBOL_REF:
-	  output_address (x0);
-	  break;
-	  
-	default:
-	  fprintf (stderr, "bad MEM code = %x\n", GET_CODE (x0));
-	  debug_rtx (x);
-	  output_operand_lossage ("fr30_print_operand: unhandled MEM");
-	  break;
-	}
-      break;
-      
-    case CONST_DOUBLE :
-      /* We handle SFmode constants here as output_addr_const doesn't.  */
-      if (GET_MODE (x) == SFmode)
-	{
-	  REAL_VALUE_TYPE d;
-	  long l;
-
-	  REAL_VALUE_FROM_CONST_DOUBLE (d, x);
-	  REAL_VALUE_TO_TARGET_SINGLE (d, l);
-	  fprintf (file, "0x%08lx", l);
-	  break;
-	}
-
-      /* Fall through.  Let output_addr_const deal with it.  */
-    default:
-      output_addr_const (file, x);
-      break;
-    }
-
-  return;
-}
-
-/*}}}*/
-/*{{{  Function arguments */ 
-
-/* Compute the number of word sized registers needed to hold a
-   function argument of mode INT_MODE and tree type TYPE.  */
-int
-fr30_num_arg_regs (int_mode, type)
-     int int_mode;
-     tree type;
-{
-  enum machine_mode mode = (enum machine_mode) int_mode;
-  int size;
-
-  if (MUST_PASS_IN_STACK (mode, type))
-    return 0;
-
-  if (type && mode == BLKmode)
-    size = int_size_in_bytes (type);
-  else
-    size = GET_MODE_SIZE (mode);
-
-  return (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-}
-
-/* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.
-   Returns the number of argument registers required to hold *part* of
-   a parameter of machine mode MODE and tree type TYPE (which may be
-   NULL if the type is not known).  If the argument fits entirly in
-   the argument registers, or entirely on the stack, then 0 is returned.
-   CUM is the number of argument registers already used by earlier
-   parameters to the function.  */
-
-int
-fr30_function_arg_partial_nregs (cum, int_mode, type, named)
-     CUMULATIVE_ARGS cum;
-     int int_mode;
-     tree type;
-     int named;
-{
-  /* Unnamed arguments, ie those that are prototyped as ...
-     are always passed on the stack.
-     Also check here to see if all the argument registers are full.  */
-  if (named == 0 || cum >= FR30_NUM_ARG_REGS)
-    return 0;
-
-  /* Work out how many argument registers would be needed if this
-     parameter were to be passed entirely in registers.  If there
-     are sufficient argument registers available (or if no registers
-     are needed because the parameter must be passed on the stack)
-     then return zero, as this parameter does not require partial
-     register, partial stack stack space.  */
-  if (cum + fr30_num_arg_regs (int_mode, type) <= FR30_NUM_ARG_REGS)
-    return 0;
-  
-  /* Otherwise return the number of registers that would be used.  */
-  return FR30_NUM_ARG_REGS - cum;
-}
-
-/*}}}*/
-/*{{{  Operand predicates */ 
-
-/* Returns true if OPERAND is an integer value suitable for use in
-   an ADDSP instruction.  */
-int
-stack_add_operand (operand, int_mode)
-     rtx operand;
-     int int_mode;
-{
-  return
-    (GET_CODE (operand) == CONST_INT
-     && INTVAL (operand) >= -512
-     && INTVAL (operand) <=  508
-     && ((INTVAL (operand) & 3) == 0));
-}
-
-/* Returns true if OPERAND is an integer value suitable for use in
-   an ADD por ADD2 instruction, or if it is a register.  */
-int
-add_immediate_operand (operand, int_mode)
-     rtx operand;
-     int int_mode;
-{
-  return
-    (GET_CODE (operand) == REG
-     || (GET_CODE (operand) == CONST_INT
-	 && INTVAL (operand) >= -16
-	 && INTVAL (operand) <=  15));
-}
-
-/* Returns true if OPERAND is hard register in the range 8 - 15.  */
-int
-high_register_operand (operand, int_mode)
-     rtx operand;
-     int int_mode;
-{
-  return
-    (GET_CODE (operand) == REG
-     && REGNO (operand) <= 15
-     && REGNO (operand) >= 8);
-}
-
-/* Returns true if OPERAND is hard register in the range 0 - 7.  */
-int
-low_register_operand (operand, int_mode)
-     rtx operand;
-     int int_mode;
-{
-  return
-    (GET_CODE (operand) == REG
-     && REGNO (operand) <= 7
-     && REGNO (operand) >= 0);
-}
-
-/* Returns true if OPERAND is suitable for use in a CALL insn.  */
-int
-call_operand (operand, int_mode)
-     rtx operand;
-     int int_mode;
-{
-  enum machine_mode mode = (enum machine_mode) int_mode;
-  
-  return nonimmediate_operand (operand, mode)
-    || (GET_CODE (operand) == MEM
-	&& GET_CODE (XEXP (operand, 0)) == SYMBOL_REF);
-}
-
-/* Returns true if OPERAND is a displacement suitable for use in a
-   frame pointer based load or store.  */
-int
-fp_displacement_operand (operand, int_mode)
-     rtx operand;
-     int int_mode;
-{
-  return (GET_CODE (operand) == CONST_INT
-	  && ((INTVAL (operand) & 0x3) == 0)
-	  && (INTVAL (operand) <= ((1 << 9) - 1))
-	  && (INTVAL (operand) >= (- (1 << 9))));
-}
-
-/* Returns true if OPERAND is a displacement suitable for use in a
-   stack pointer based load or store.  */
-int
-sp_displacement_operand (operand, int_mode)
-     rtx operand;
-     int int_mode;
-{
-  return (GET_CODE (operand) == CONST_INT
-	  && ((INTVAL (operand) & 0x3) == 0)
-	  && (INTVAL (operand) <= ((1 << 6) - 1))
-	  && (INTVAL (operand) >= 0));
-}
-
-/* Returns true iff all the registers in the operands array
-   are in descending or ascending order.  */
-int
-fr30_check_multiple_regs (operands, num_operands, descending)
-     rtx * operands;
-     int   num_operands;
-     int   descending;
-{
-  if (descending)
-    {
-      int prev_regno = -1;
-      
-      while (num_operands--)
-	{
-	  if (GET_CODE (operands [num_operands]) != REG)
-	    return 0;
-	  
-	  if (REGNO (operands [num_operands]) < prev_regno)
-	    return 0;
-	  
-	  prev_regno = REGNO (operands [num_operands]);
-	}
-    }
-  else
-    {
-      int prev_regno = CONDITION_CODE_REGNUM;
-      
-      while (num_operands--)
-	{
-	  if (GET_CODE (operands [num_operands]) != REG)
-	    return 0;
-	  
-	  if (REGNO (operands [num_operands]) > prev_regno)
-	    return 0;
-	  
-	  prev_regno = REGNO (operands [num_operands]);
-	}
-    }
-
-  return 1;
-}
-
-/*}}}*/
-
-/* Local Variables: */
-/* folded-file: t   */
-/* End:		    */
-
-/* END CYGNUS LOCAL -- nickc/fr30 */
-
diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h
deleted file mode 100755
index e0b37b1..0000000
--- a/gcc/config/fr30/fr30.h
+++ /dev/null
@@ -1,4496 +0,0 @@
-/* CYGNUS LOCAL -- nickc/entire file */
-
-/*{{{  Comment */ 
-
-/* Definitions of FR30 target. 
-   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
-   Contributed by Cygnus Solutions.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/*}}}*/ 
-/*{{{  Includes */ 
-
-/* Set up System V.4 (aka ELF) defaults.  */
-#include "svr4.h"
-
-/* Include prototyping macros */
-#include "gansidecl.h"
-
-/*}}}*/ 
-/*{{{  Forward strcuture declarations for use in prototypes.  */ 
-
-#ifdef BUFSIZ		/* stdio.h has been included, ok to use FILE * */
-#define STDIO_PROTO(ARGS) PROTO(ARGS)
-#else
-#define STDIO_PROTO(ARGS) ()
-#endif
-
-#ifndef RTX_CODE
-struct rtx_def;
-#define Rtx struct rtx_def *
-#else
-#define Rtx rtx
-#endif
-
-#ifndef TREE_CODE
-union tree_node;
-#define Tree union tree_node *
-#else
-#define Tree tree
-#endif
-
-/*}}}*/ 
-/*{{{  Driver configuration */ 
-
-/* A C expression which determines whether the option `-CHAR' takes arguments.
-   The value should be the number of arguments that option takes-zero, for many
-   options.
-
-   By default, this macro is defined to handle the standard options properly.
-   You need not define it unless you wish to add additional options which take
-   arguments.
-
-   Defined in svr4.h.  */
-#undef SWITCH_TAKES_ARG
-
-/* A C expression which determines whether the option `-NAME' takes arguments.
-   The value should be the number of arguments that option takes-zero, for many
-   options.  This macro rather than `SWITCH_TAKES_ARG' is used for
-   multi-character option names.
-
-   By default, this macro is defined as `DEFAULT_WORD_SWITCH_TAKES_ARG', which
-   handles the standard options properly.  You need not define
-   `WORD_SWITCH_TAKES_ARG' unless you wish to add additional options which take
-   arguments.  Any redefinition should call `DEFAULT_WORD_SWITCH_TAKES_ARG' and
-   then check for additional options.
-
-   Defined in svr4.h.  */
-#undef WORD_SWITCH_TAKES_ARG
-
-/*}}}*/ 
-/*{{{  Run-time target specifications */ 
-
-#undef  ASM_SPEC
-#define ASM_SPEC "%{v}"
-
-/* Define this to be a string constant containing `-D' options to define the
-   predefined macros that identify this machine and system.  These macros will
-   be predefined unless the `-ansi' option is specified. */
-
-#define CPP_PREDEFINES "-Dfr30 -D__fr30__ -Amachine(fr30)"
-
-/* Use LDI:20 instead of LDI:32 to load addresses.  */
-#define TARGET_SMALL_MODEL_MASK	(1 << 0)
-#define TARGET_SMALL_MODEL	(target_flags & TARGET_SMALL_MODEL_MASK)
-
-#define TARGET_DEFAULT		0
-
-/* This declaration should be present.  */
-extern int target_flags;
-
-#define TARGET_SWITCHES \
-{	\
-  { "small-model",      TARGET_SMALL_MODEL_MASK, "Assume small address space" }, \
-  { "no-small-model", - TARGET_SMALL_MODEL_MASK, "" },			 	 \
-  { "",                 TARGET_DEFAULT }					 \
-}
-
-#define TARGET_VERSION fprintf (stderr, " (fr30)");
-
-/* Define this macro if debugging can be performed even without a frame
-   pointer.  If this macro is defined, GNU CC will turn on the
-   `-fomit-frame-pointer' option whenever `-O' is specified.  */
-#define CAN_DEBUG_WITHOUT_FP
-
-#undef  STARTFILE_SPEC
-#define STARTFILE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
-
-/* Include the OS stub library, so that the code can be simulated.
-   This is not the right way to do this.  Ideally this kind of thing
-   should be done in the linker script - but I have not worked out how
-   to specify the location of a linker script in a gcc command line yet... */
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC  "-lsim crtend.o%s crtn.o%s"
-
-/*}}}*/ 
-/*{{{  Storage Layout */ 
-
-/* Define this macro to have the value 1 if the most significant bit in a byte
-   has the lowest number; otherwise define it to have the value zero.  This
-   means that bit-field instructions count from the most significant bit.  If
-   the machine has no bit-field instructions, then this must still be defined,
-   but it doesn't matter which value it is defined to.  This macro need not be
-   a constant.
-
-   This macro does not affect the way structure fields are packed into bytes or
-   words; that is controlled by `BYTES_BIG_ENDIAN'.  */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this macro to have the value 1 if the most significant byte in a word
-   has the lowest number.  This macro need not be a constant.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this macro to have the value 1 if, in a multiword object, the most
-   significant word has the lowest number.  This applies to both memory
-   locations and registers; GNU CC fundamentally assumes that the order of
-   words in memory is the same as the order in registers.  This macro need not
-   be a constant.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* Define this macro to be the number of bits in an addressable storage unit
-   (byte); normally 8.  */
-#define BITS_PER_UNIT 	8
-
-/* Number of bits in a word; normally 32.  */
-#define BITS_PER_WORD 	32
-
-/* Number of storage units in a word; normally 4.  */
-#define UNITS_PER_WORD 	4
-
-/* Width of a pointer, in bits.  You must specify a value no wider than the
-   width of `Pmode'.  If it is not equal to the width of `Pmode', you must
-   define `POINTERS_EXTEND_UNSIGNED'.  */
-#define POINTER_SIZE 	32
-
-/* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
-   which has the specified mode and signedness is to be stored in a register.
-   This macro is only called when TYPE is a scalar type.
-
-   On most RISC machines, which only have operations that operate on a full
-   register, define this macro to set M to `word_mode' if M is an integer mode
-   narrower than `BITS_PER_WORD'.  In most cases, only integer modes should be
-   widened because wider-precision floating-point operations are usually more
-   expensive than their narrower counterparts.
-
-   For most machines, the macro definition does not change UNSIGNEDP.  However,
-   some machines, have instructions that preferentially handle either signed or
-   unsigned quantities of certain modes.  For example, on the DEC Alpha, 32-bit
-   loads from memory and 32-bit add instructions sign-extend the result to 64
-   bits.  On such machines, set UNSIGNEDP according to which kind of extension
-   is more efficient.
-
-   Do not define this macro if it would never modify MODE.  */
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)				\
-do {									\
-  if (GET_MODE_CLASS (MODE) == MODE_INT					\
-      && GET_MODE_SIZE (MODE) < 4)					\
-    (MODE) = SImode;							\
-} while (0)
-
-/* Normal alignment required for function parameters on the stack, in bits.
-   All stack parameters receive at least this much alignment regardless of data
-   type.  On most machines, this is the same as the size of an integer.  */
-#define PARM_BOUNDARY 32
-
-/* Define this macro if you wish to preserve a certain alignment for the stack
-   pointer.  The definition is a C expression for the desired alignment
-   (measured in bits).
-
-   If `PUSH_ROUNDING' is not defined, the stack will always be aligned to the
-   specified boundary.  If `PUSH_ROUNDING' is defined and specifies a less
-   strict alignment than `STACK_BOUNDARY', the stack may be momentarily
-   unaligned while pushing arguments.  */
-#define STACK_BOUNDARY 32
-
-/* Alignment required for a function entry point, in bits.  */
-#define FUNCTION_BOUNDARY 32
-
-/* Biggest alignment that any data type can require on this machine,
-   in bits.  */
-#define BIGGEST_ALIGNMENT 32
-
-/* If defined, a C expression to compute the alignment for a static variable.
-   TYPE is the data type, and ALIGN is the alignment that the object
-   would ordinarily have.  The value of this macro is used instead of that
-   alignment to align the object.
-
-   If this macro is not defined, then ALIGN is used.
-
-   One use of this macro is to increase alignment of medium-size data to make
-   it all fit in fewer cache lines.  Another is to cause character arrays to be
-   word-aligned so that `strcpy' calls that copy constants to character arrays
-   can be done inline.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* If defined, a C expression to compute the alignment given to a constant that
-   is being placed in memory.  CONSTANT is the constant and ALIGN is the
-   alignment that the object would ordinarily have.  The value of this macro is
-   used instead of that alignment to align the object.
-
-   If this macro is not defined, then ALIGN is used.
-
-   The typical use of this macro is to increase alignment for string constants
-   to be word aligned so that `strcpy' calls that copy constants can be done
-   inline.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  (TREE_CODE (EXP) == STRING_CST	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Alignment in bits to be given to a structure bit field that follows an empty
-   field such as `int : 0;'.
-
-   Note that `PCC_BITFIELD_TYPE_MATTERS' also affects the alignment that
-   results from an empty field.  */
-/* #define EMPTY_FIELD_BOUNDARY */
-
-/* Number of bits which any structure or union's size must be a multiple of.
-   Each structure or union's size is rounded up to a multiple of this.
-
-   If you do not define this macro, the default is the same as `BITS_PER_UNIT'.  */
-/* #define STRUCTURE_SIZE_BOUNDARY */
-
-/* Define this macro to be the value 1 if instructions will fail to work if
-   given data not on the nominal alignment.  If instructions will merely go
-   slower in that case, define this macro as 0.  */
-#define STRICT_ALIGNMENT 1
-
-/* Define this if you wish to imitate the way many other C compilers handle
-   alignment of bitfields and the structures that contain them.
-
-   The behavior is that the type written for a bitfield (`int', `short', or
-   other integer type) imposes an alignment for the entire structure, as if the
-   structure really did contain an ordinary field of that type.  In addition,
-   the bitfield is placed within the structure so that it would fit within such
-   a field, not crossing a boundary for it.
-
-   Thus, on most machines, a bitfield whose type is written as `int' would not
-   cross a four-byte boundary, and would force four-byte alignment for the
-   whole structure.  (The alignment used may not be four bytes; it is
-   controlled by the other alignment parameters.)
-
-   If the macro is defined, its definition should be a C expression; a nonzero
-   value for the expression enables this behavior.
-
-   Note that if this macro is not defined, or its value is zero, some bitfields
-   may cross more than one alignment boundary.  The compiler can support such
-   references if there are `insv', `extv', and `extzv' insns that can directly
-   reference memory.
-
-   The other known way of making bitfields work is to define
-   `STRUCTURE_SIZE_BOUNDARY' as large as `BIGGEST_ALIGNMENT'.  Then every
-   structure can be accessed with fullwords.
-
-   Unless the machine has bitfield instructions or you define
-   `STRUCTURE_SIZE_BOUNDARY' that way, you must define
-   `PCC_BITFIELD_TYPE_MATTERS' to have a nonzero value.
-
-   If your aim is to make GNU CC use the same conventions for laying out
-   bitfields as are used by another compiler, here is how to investigate what
-   the other compiler does.  Compile and run this program:
-
-        struct foo1
-        {
-          char x;
-          char :0;
-          char y;
-        };
-
-        struct foo2
-        {
-          char x;
-          int :0;
-          char y;
-        };
-
-        main ()
-        {
-          printf ("Size of foo1 is %d\n",
-                  sizeof (struct foo1));
-          printf ("Size of foo2 is %d\n",
-                  sizeof (struct foo2));
-          exit (0);
-        }
-
-   If this prints 2 and 5, then the compiler's behavior is what you would get
-   from `PCC_BITFIELD_TYPE_MATTERS'.
-
-   Defined in svr4.h.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* A code distinguishing the floating point format of the target machine.
-   There are three defined values:
-
-   IEEE_FLOAT_FORMAT'
-        This code indicates IEEE floating point.  It is the default;
-        there is no need to define this macro when the format is IEEE.
-
-   VAX_FLOAT_FORMAT'
-        This code indicates the peculiar format used on the Vax.
-
-   UNKNOWN_FLOAT_FORMAT'
-        This code indicates any other format.
-
-   The value of this macro is compared with `HOST_FLOAT_FORMAT'
-   to determine whether the target machine has the same format as
-   the host machine.  If any other formats are actually in use on supported
-   machines, new codes should be defined for them.
-
-   The ordering of the component words of floating point values stored in
-   memory is controlled by `FLOAT_WORDS_BIG_ENDIAN' for the target machine and
-   `HOST_FLOAT_WORDS_BIG_ENDIAN' for the host.  */
-#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
-
-/* GNU CC supports two ways of implementing C++ vtables: traditional or with
-   so-called "thunks".  The flag `-fvtable-thunk' chooses between them.  Define
-   this macro to be a C expression for the default value of that flag.  If
-   `DEFAULT_VTABLE_THUNKS' is 0, GNU CC uses the traditional implementation by
-   default.  The "thunk" implementation is more efficient (especially if you
-   have provided an implementation of `ASM_OUTPUT_MI_THUNK', but is not binary
-   compatible with code compiled using the traditional implementation.  If you
-   are writing a new ports, define `DEFAULT_VTABLE_THUNKS' to 1.
-
-   If you do not define this macro, the default for `-fvtable-thunk' is 0.  */
-#define DEFAULT_VTABLE_THUNKS 1
-
-/*}}}*/ 
-/*{{{  Layout of Source Language Data Types */ 
-
-#define CHAR_TYPE_SIZE 		 8
-#define SHORT_TYPE_SIZE 	16
-#define INT_TYPE_SIZE 		32
-#define LONG_TYPE_SIZE 		32
-#define LONG_LONG_TYPE_SIZE 	64
-#define FLOAT_TYPE_SIZE 	32
-#define DOUBLE_TYPE_SIZE 	64
-#define LONG_DOUBLE_TYPE_SIZE 	64
-
-/* An expression whose value is 1 or 0, according to whether the type `char'
-   should be signed or unsigned by default.  The user can always override this
-   default with the options `-fsigned-char' and `-funsigned-char'.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-#define TARGET_BELL     0x7	/*  '\a'  */
-#define TARGET_BS	0x8	/*  '\b'  */
-#define TARGET_TAB	0x9	/*  '\t'  */
-#define TARGET_NEWLINE	0xa	/*  '\n'  */
-#define TARGET_VT	0xb	/*  '\v'  */
-#define TARGET_FF	0xc	/*  '\f'  */
-#define TARGET_CR	0xd	/*  '\r'  */
-
-/*}}}*/ 
-/*{{{  Register Basics */ 
-
-/* Number of hardware registers known to the compiler.  They receive numbers 0
-   through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number
-   really is assigned the number `FIRST_PSEUDO_REGISTER'.  */
-#define FIRST_PSEUDO_REGISTER	21
-
-/* Fixed register assignments: */
-
-/* Here we do a bad thing - reserve a register for use by the machine
-   description file.  There are too many places in compiler where it
-   assumes that it can issue a branch or jump instruction without
-   providing a scratch register for it, and reload just cannot cope, so
-   we keepo a register back for these situations.  */
-#define COMPILER_SCRATCH_REGISTER 0
-
-/* The register that contains the result of a function call.  */
-#define RETURN_VALUE_REGNUM	 4
-
-/* The first register that can contain the arguments to a function.  */
-#define FIRST_ARG_REGNUM	 4
-
-/* A call-used register that can be used during the function prologue.  */
-#define PROLOGUE_TMP_REGNUM	 COMPILER_SCRATCH_REGISTER
-     
-/* Register numbers used for passing a function's static chain pointer.  If
-   register windows are used, the register number as seen by the called
-   function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as
-   seen by the calling function is `STATIC_CHAIN_REGNUM'.  If these registers
-   are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined.
-
-   The static chain register need not be a fixed register.
-
-   If the static chain is passed in memory, these macros should not be defined;
-   instead, the next two macros should be defined.  */
-#define STATIC_CHAIN_REGNUM 	12
-/* #define STATIC_CHAIN_INCOMING_REGNUM */
-
-/* An FR30 specific hardware register.  */
-#define ACCUMULATOR_REGNUM	13
-
-/* The register number of the frame pointer register, which is used to access
-   automatic variables in the stack frame.  On some machines, the hardware
-   determines which register this is.  On other machines, you can choose any
-   register you wish for this purpose.  */
-#define FRAME_POINTER_REGNUM	14
-     
-/* The register number of the stack pointer register, which must also be a
-   fixed register according to `FIXED_REGISTERS'.  On most machines, the
-   hardware determines which register this is.  */
-#define STACK_POINTER_REGNUM	15
-
-/* The following a fake hard registers that describe some of the dedicated
-   registers on the FR30.  */
-#define CONDITION_CODE_REGNUM	16
-#define RETURN_POINTER_REGNUM	17
-#define MD_HIGH_REGNUM		18
-#define MD_LOW_REGNUM		19
-
-/* An initializer that says which registers are used for fixed purposes all
-   throughout the compiled code and are therefore not available for general
-   allocation.  These would include the stack pointer, the frame pointer
-   (except on machines where that can be used as a general register when no
-   frame pointer is needed), the program counter on machines where that is
-   considered one of the addressable registers, and any other numbered register
-   with a standard use.
-
-   This information is expressed as a sequence of numbers, separated by commas
-   and surrounded by braces.  The Nth number is 1 if register N is fixed, 0
-   otherwise.
-
-   The table initialized from this macro, and the table initialized by the
-   following one, may be overridden at run time either automatically, by the
-   actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the
-   command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'.  */
-#define FIXED_REGISTERS 			\
-  { 1, 0, 0, 0, 0, 0, 0, 0, 	/*  0 -  7 */ 	\
-    0, 0, 0, 0, 0, 0, 0, 1,	/*  8 - 15 */ 	\
-    1, 1, 1, 1, 1 }		/* 16 - 20 */
-
-/* XXX - MDL and MDH set as fixed for now - this is until I can get the
-   mul patterns working.  */
-
-/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in
-   general) by function calls as well as for fixed registers.  This macro
-   therefore identifies the registers that are not available for general
-   allocation of values that must live across function calls.
-
-   If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically
-   saves it on function entry and restores it on function exit, if the register
-   is used within the function.  */
-#define CALL_USED_REGISTERS 			\
-  { 1, 1, 1, 1, 1, 1, 1, 1,	/*  0 -  7 */ 	\
-    0, 0, 0, 0, 1, 1, 0, 1,	/*  8 - 15 */ 	\
-    1, 1, 1, 1, 1 }		/* 16 - 20 */
-
-/* A C initializer containing the assembler's names for the machine registers,
-   each one as a C string constant.  This is what translates register numbers
-   in the compiler into assembler language.  */
-#define REGISTER_NAMES 						\
-{   "r0", "r1", "r2",  "r3",  "r4",  "r5", "r6", "r7",	\
-    "r8", "r9", "r10", "r11", "r12", "ac", "fp", "sp",	\
-    "cc", "rp", "mdh", "mdl", "ap"			\
-}
-
-/* If defined, a C initializer for an array of structures containing a name and
-   a register number.  This macro defines additional names for hard registers,
-   thus allowing the `asm' option in declarations to refer to registers using
-   alternate names.  */
-#define ADDITIONAL_REGISTER_NAMES 				\
-{								\
-  {"r13", 13}, {"r14", 14}, {"r15", 15}, {"usp", 15}, {"ps", 16}\
-}
-
-/*}}}*/ 
-/*{{{  How Values Fit in Registers */ 
-
-/* A C expression for the number of consecutive hard registers, starting at
-   register number REGNO, required to hold a value of mode MODE.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE) 			\
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* A C expression that is nonzero if it is permissible to store a value of mode
-   MODE in hard register number REGNO (or in several registers starting with
-   that one).  */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
-/* A C expression that is nonzero if it is desirable to choose register
-   allocation so as to avoid move instructions between a value of mode MODE1
-   and a value of mode MODE2.
-
-   If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
-   ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
-   zero.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) 1
-
-/* Define this macro if the compiler should avoid copies to/from CCmode
-   registers.  You should only define this macro if support fo copying to/from
-   CCmode is incomplete.  */
-/* #define AVOID_CCMODE_COPIES */
-
-/*}}}*/ 
-/*{{{  Register Classes */ 
-
-/* An enumeral type that must be defined with all the register class names as
-   enumeral values.  `NO_REGS' must be first.  `ALL_REGS' must be the last
-   register class, followed by one more enumeral value, `LIM_REG_CLASSES',
-   which is not a register class but rather tells how many classes there are.
-
-   Each register class has a number, which is the value of casting the class
-   name to type `int'.  The number serves as an index in many of the tables
-   described below.  */
-enum reg_class
-{
-  NO_REGS,
-  MULTIPLY_32_REG,	/* the MDL register as used by the MULH, MULUH insns */
-  MULTIPLY_64_REG,	/* the MDH,MDL register pair as used by MUL and MULU */
-  LOW_REGS,		/* registers 0 through 7 */
-  HIGH_REGS,		/* registers 8 through 15 */
-  REAL_REGS,		/* ie all the general hardware registers on the FR30 */
-  ALL_REGS,
-  LIM_REG_CLASSES
-};
-
-#define GENERAL_REGS 	REAL_REGS
-#define N_REG_CLASSES 	((int) LIM_REG_CLASSES)
-
-/* An initializer containing the names of the register classes as C string
-   constants.  These names are used in writing some of the debugging dumps.  */
-#define REG_CLASS_NAMES \
-{			\
-  "NO_REGS",		\
-  "MULTIPLY_32_REG",	\
-  "MULTIPLY_64_REG",	\
-  "LOW_REGS", 		\
-  "HIGH_REGS", 		\
-  "REAL_REGS",		\
-  "ALL_REGS"		\
- }
-
-/* An initializer containing the contents of the register classes, as integers
-   which are bit masks.  The Nth integer specifies the contents of class N.
-   The way the integer MASK is interpreted is that register R is in the class
-   if `MASK & (1 << R)' is 1.
-
-   When the machine has more than 32 registers, an integer does not suffice.
-   Then the integers are replaced by sub-initializers, braced groupings
-   containing several integers.  Each sub-initializer must be suitable as an
-   initializer for the type `HARD_REG_SET' which is defined in
-   `hard-reg-set.h'.  */
-#define REG_CLASS_CONTENTS 			\
-{ 						\
-  0,						\
-  1 << MD_LOW_REGNUM,				\
-  (1 << MD_LOW_REGNUM) | (1 << MD_HIGH_REGNUM),	\
-  (1 << 8) - 1,					\
-  ((1 << 8) - 1) << 8,				\
-  (1 << CONDITION_CODE_REGNUM) - 1,		\
-  (1 << FIRST_PSEUDO_REGISTER) - 1		\
-}
-
-/* A C expression whose value is a register class containing hard register
-   REGNO.  In general there is more than one such class; choose a class which
-   is "minimal", meaning that no smaller class also contains the register.  */
-#define REGNO_REG_CLASS(REGNO) 			\
-  ( (REGNO) < 8 ? LOW_REGS			\
-  : (REGNO) < CONDITION_CODE_REGNUM ? HIGH_REGS	\
-  : (REGNO) == MD_LOW_REGNUM ? MULTIPLY_32_REG	\
-  : (REGNO) == MD_HIGH_REGNUM ? MULTIPLY_64_REG	\
-  : ALL_REGS)
-
-/* A macro whose definition is the name of the class to which a valid base
-   register must belong.  A base register is one used in an address which is
-   the register value plus a displacement.  */
-#define BASE_REG_CLASS 	REAL_REGS
-
-/* A macro whose definition is the name of the class to which a valid index
-   register must belong.  An index register is one used in an address where its
-   value is either multiplied by a scale factor or added to another register
-   (as well as added to a displacement).  */
-#define INDEX_REG_CLASS REAL_REGS
-
-/* A C expression which defines the machine-dependent operand constraint
-   letters for register classes.  If CHAR is such a letter, the value should be
-   the register class corresponding to it.  Otherwise, the value should be
-   `NO_REGS'.  The register letter `r', corresponding to class `GENERAL_REGS',
-   will not be passed to this macro; you do not need to handle it.
-
-   The following letters are unavailable, due to being used as
-   constraints:
-	'0'..'9'
-	'<', '>'
-	'E', 'F', 'G', 'H'
-	'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
-	'Q', 'R', 'S', 'T', 'U'
-	'V', 'X'
-	'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
-
-#define REG_CLASS_FROM_LETTER(CHAR) 	\
-     (  (CHAR) == 'd' ? MULTIPLY_64_REG	\
-      : (CHAR) == 'e' ? MULTIPLY_32_REG	\
-      : (CHAR) == 'h' ? HIGH_REGS	\
-      : (CHAR) == 'l' ? LOW_REGS	\
-      : (CHAR) == 'a' ? ALL_REGS	\
-      : NO_REGS)
-
-/* A C expression which is nonzero if register number NUM is suitable for use
-   as a base register in operand addresses.  It may be either a suitable hard
-   register or a pseudo register that has been allocated such a hard register.  */
-#define REGNO_OK_FOR_BASE_P(NUM) 1
-
-/* A C expression which is nonzero if register number NUM is suitable for use
-   as an index register in operand addresses.  It may be either a suitable hard
-   register or a pseudo register that has been allocated such a hard register.
-
-   The difference between an index register and a base register is that the
-   index register may be scaled.  If an address involves the sum of two
-   registers, neither one of them scaled, then either one may be labeled the
-   "base" and the other the "index"; but whichever labeling is used must fit
-   the machine's constraints of which registers may serve in each capacity.
-   The compiler will try both labelings, looking for one that is valid, and
-   will reload one or both registers only if neither labeling works.  */
-#define REGNO_OK_FOR_INDEX_P(NUM) 1
-
-/* A C expression that places additional restrictions on the register class to
-   use when it is necessary to copy value X into a register in class CLASS.
-   The value is a register class; perhaps CLASS, or perhaps another, smaller
-   class.  On many machines, the following definition is safe:
-
-        #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
-
-   Sometimes returning a more restrictive class makes better code.  For
-   example, on the 68000, when X is an integer constant that is in range for a
-   `moveq' instruction, the value of this macro is always `DATA_REGS' as long
-   as CLASS includes the data registers.  Requiring a data register guarantees
-   that a `moveq' will be used.
-
-   If X is a `const_double', by returning `NO_REGS' you can force X into a
-   memory constant.  This is useful on certain machines where immediate
-   floating values cannot be loaded into certain kinds of registers.  */
-#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
-
-/* Like `PREFERRED_RELOAD_CLASS', but for output reloads instead of input
-   reloads.  If you don't define this macro, the default is to use CLASS,
-   unchanged.  */
-/* #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) */
-
-/* A C expression that places additional restrictions on the register class to
-   use when it is necessary to be able to hold a value of mode MODE in a reload
-   register for which class CLASS would ordinarily be used.
-
-   Unlike `PREFERRED_RELOAD_CLASS', this macro should be used when there are
-   certain modes that simply can't go in certain reload classes.
-
-   The value is a register class; perhaps CLASS, or perhaps another, smaller
-   class.
-
-   Don't define this macro unless the target machine has limitations which
-   require the macro to do something nontrivial.  */
-/* #define LIMIT_RELOAD_CLASS(MODE, CLASS) */
-
-/* Many machines have some registers that cannot be copied directly to or from
-   memory or even from other types of registers.  An example is the `MQ'
-   register, which on most machines, can only be copied to or from general
-   registers, but not memory.  Some machines allow copying all registers to and
-   from memory, but require a scratch register for stores to some memory
-   locations (e.g., those with symbolic address on the RT, and those with
-   certain symbolic address on the Sparc when compiling PIC).  In some cases,
-   both an intermediate and a scratch register are required.
-
-   You should define these macros to indicate to the reload phase that it may
-   need to allocate at least one register for a reload in addition to the
-   register to contain the data.  Specifically, if copying X to a register
-   CLASS in MODE requires an intermediate register, you should define
-   `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
-   whose registers can be used as intermediate registers or scratch registers.
-
-   If copying a register CLASS in MODE to X requires an intermediate or scratch
-   register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
-   largest register class required.  If the requirements for input and output
-   reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
-   instead of defining both macros identically.
-
-   The values returned by these macros are often `GENERAL_REGS'.  Return
-   `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
-   to or from a register of CLASS in MODE without requiring a scratch register.
-   Do not define this macro if it would always return `NO_REGS'.
-
-   If a scratch register is required (either with or without an intermediate
-   register), you should define patterns for `reload_inM' or `reload_outM', as
-   required.  These patterns, which will normally be implemented with a
-   `define_expand', should be similar to the `movM' patterns, except that
-   operand 2 is the scratch register.
-
-   Define constraints for the reload register and scratch register that contain
-   a single register class.  If the original reload register (whose class is
-   CLASS) can meet the constraint given in the pattern, the value returned by
-   these macros is used for the class of the scratch register.  Otherwise, two
-   additional reload registers are required.  Their classes are obtained from
-   the constraints in the insn pattern.
-
-   X might be a pseudo-register or a `subreg' of a pseudo-register, which could
-   either be in a hard register or in memory.  Use `true_regnum' to find out;
-   it will return -1 if the pseudo is in memory and the hard register number if
-   it is in a register.
-
-   These macros should not be used in the case where a particular class of
-   registers can only be copied to memory and not to another class of
-   registers.  In that case, secondary reload registers are not needed and
-   would not be helpful.  Instead, a stack location must be used to perform the
-   copy and the `movM' pattern should use memory as a intermediate storage.
-   This case often occurs between floating-point and general registers.  */
-/* #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) */
-/* #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) */
-/* #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) */
-
-/* Normally the compiler avoids choosing registers that have been explicitly
-   mentioned in the rtl as spill registers (these registers are normally those
-   used to pass parameters and return values).  However, some machines have so
-   few registers of certain classes that there would not be enough registers to
-   use as spill registers if this were done.
-
-   Define `SMALL_REGISTER_CLASSES' to be an expression with a non-zero value on
-   these machines.  When this macro has a non-zero value, the compiler allows
-   registers explicitly used in the rtl to be used as spill registers but
-   avoids extending the lifetime of these registers.
-
-   It is always safe to define this macro with a non-zero value, but if you
-   unnecessarily define it, you will reduce the amount of optimizations that
-   can be performed in some cases.  If you do not define this macro with a
-   non-zero value when it is required, the compiler will run out of spill
-   registers and print a fatal error message.  For most machines, you should
-   not define this macro at all.  */
-/* #define SMALL_REGISTER_CLASSES */
-
-/* A C expression whose value is nonzero if pseudos that have been assigned to
-   registers of class CLASS would likely be spilled because registers of CLASS
-   are needed for spill registers.
-
-   The default value of this macro returns 1 if CLASS has exactly one register
-   and zero otherwise.  On most machines, this default should be used.  Only
-   define this macro to some other expression if pseudo allocated by
-   `local-alloc.c' end up in memory because their hard registers were needed
-   for spill registers.  If this macro returns nonzero for those classes, those
-   pseudos will only be allocated by `global.c', which knows how to reallocate
-   the pseudo to another register.  If there would not be another register
-   available for reallocation, you should not change the definition of this
-   macro since the only effect of such a definition would be to slow down
-   register allocation.  */
-/* #define CLASS_LIKELY_SPILLED_P(CLASS) */
-
-/* A C expression for the maximum number of consecutive registers of
-   class CLASS needed to hold a value of mode MODE.
-
-   This is closely related to the macro `HARD_REGNO_NREGS'.  In fact, the value
-   of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
-   `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
-
-   This macro helps control the handling of multiple-word values in
-   the reload pass.  */
-#define CLASS_MAX_NREGS(CLASS, MODE) HARD_REGNO_NREGS (0, MODE)
-
-/* If defined, a C expression for a class that contains registers which the
-   compiler must always access in a mode that is the same size as the mode in
-   which it loaded the register.
-
-   For the example, loading 32-bit integer or floating-point objects into
-   floating-point registers on the Alpha extends them to 64-bits.  Therefore
-   loading a 64-bit object and then storing it as a 32-bit object does not
-   store the low-order 32-bits, as would be the case for a normal register.
-   Therefore, `alpha.h' defines this macro as `FLOAT_REGS'.  */
-/* #define CLASS_CANNOT_CHANGE_SIZE */
-
-/*}}}*/ 
-/*{{{  CONSTANTS */ 
-
-/* Return true if a value is inside a range */
-#define IN_RANGE(VALUE, LOW, HIGH)					\
-  (   ((unsigned HOST_WIDE_INT)((VALUE) - (LOW)))			\
-   <= ((unsigned HOST_WIDE_INT)( (HIGH) - (LOW))))
-
-/* A C expression that defines the machine-dependent operand constraint letters
-   (`I', `J', `K', .. 'P') that specify particular ranges of integer values.
-   If C is one of those letters, the expression should check that VALUE, an
-   integer, is in the appropriate range and return 1 if so, 0 otherwise.  If C
-   is not one of those letters, the value should be 0 regardless of VALUE.  */
-#define CONST_OK_FOR_LETTER_P(VALUE, C) 			\
- (  (C) == 'I' ? IN_RANGE (VALUE,    0,       15)		\
-  : (C) == 'J' ? IN_RANGE (VALUE,  -16,       -1)		\
-  : (C) == 'K' ? IN_RANGE (VALUE,   16,       31)		\
-  : (C) == 'L' ? IN_RANGE (VALUE,    0,       (1 <<  8) - 1)	\
-  : (C) == 'M' ? IN_RANGE (VALUE,    0,       (1 << 20) - 1)	\
-  : (C) == 'P' ? IN_RANGE (VALUE,  -(1 << 8), (1 <<  8) - 1)	\
-  : 0)
-     
-/* A C expression that defines the machine-dependent operand constraint letters
-   (`G', `H') that specify particular ranges of `const_double' values.
-
-   If C is one of those letters, the expression should check that VALUE, an RTX
-   of code `const_double', is in the appropriate range and return 1 if so, 0
-   otherwise.  If C is not one of those letters, the value should be 0
-   regardless of VALUE.
-
-   `const_double' is used for all floating-point constants and for `DImode'
-   fixed-point constants.  A given letter can accept either or both kinds of
-   values.  It can use `GET_MODE' to distinguish between these kinds.  */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
-
-/* A C expression that defines the optional machine-dependent constraint
-   letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
-   types of operands, usually memory references, for the target machine.
-   Normally this macro will not be defined.  If it is required for a particular
-   target machine, it should return 1 if VALUE corresponds to the operand type
-   represented by the constraint letter C.  If C is not defined as an extra
-   constraint, the value returned should be 0 regardless of VALUE.
-
-   For example, on the ROMP, load instructions cannot have their output in r0
-   if the memory reference contains a symbolic address.  Constraint letter `Q'
-   is defined as representing a memory address that does *not* contain a
-   symbolic address.  An alternative is specified with a `Q' constraint on the
-   input and `r' on the output.  The next alternative specifies `m' on the
-   input and a register class that does not include r0 on the output.  */
-#define EXTRA_CONSTRAINT(VALUE, C) \
-   ((C) == 'Q' ? (GET_CODE (VALUE) == MEM && GET_CODE (XEXP (VALUE, 0)) == SYMBOL_REF) : 0)
-
-/*}}}*/ 
-/*{{{  Basic Stack Layout */ 
-
-/* Define this macro if pushing a word onto the stack moves the stack pointer
-   to a smaller address.  */
-#define STACK_GROWS_DOWNWARD 1
-
-/* Define this macro if the addresses of local variable slots are at negative
-   offsets from the frame pointer.  */
-#define FRAME_GROWS_DOWNWARD 1
-
-/* Define this macro if successive arguments to a function occupy decreasing
-   addresses on the stack.  */
-/* #define ARGS_GROW_DOWNWARD */
-
-/* Offset from the frame pointer to the first local variable slot to be
-   allocated.
-
-   If `FRAME_GROWS_DOWNWARD', find the next slot's offset by subtracting the
-   first slot's length from `STARTING_FRAME_OFFSET'.  Otherwise, it is found by
-   adding the length of the first slot to the value `STARTING_FRAME_OFFSET'.  */
-/* #define STARTING_FRAME_OFFSET -4 */
-#define STARTING_FRAME_OFFSET 0
-
-/* Offset from the stack pointer register to the first location at which
-   outgoing arguments are placed.  If not specified, the default value of zero
-   is used.  This is the proper value for most machines.
-
-   If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first
-   location at which outgoing arguments are placed.  */
-#define STACK_POINTER_OFFSET 0
-
-/* Offset from the argument pointer register to the first argument's address.
-   On some machines it may depend on the data type of the function.
-
-   If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first
-   argument's address.  */
-#define FIRST_PARM_OFFSET(FUNDECL) 0
-
-/* Offset from the stack pointer register to an item dynamically allocated on
-   the stack, e.g., by `alloca'.
-
-   The default value for this macro is `STACK_POINTER_OFFSET' plus the length
-   of the outgoing arguments.  The default is correct for most machines.  See
-   `function.c' for details.  */
-/* #define STACK_DYNAMIC_OFFSET(FUNDECL) */
-
-/* A C expression whose value is RTL representing the address in a stack frame
-   where the pointer to the caller's frame is stored.  Assume that FRAMEADDR is
-   an RTL expression for the address of the stack frame itself.
-
-   If you don't define this macro, the default is to return the value of
-   FRAMEADDR--that is, the stack frame address is also the address of the stack
-   word that points to the previous frame.  */
-/* #define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) */
-
-/* A C expression whose value is RTL representing the value of the return
-   address for the frame COUNT steps up from the current frame, after the
-   prologue.  FRAMEADDR is the frame pointer of the COUNT frame, or the frame
-   pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
-   defined.
-
-   The value of the expression must always be the correct address when COUNT is
-   zero, but may be `NULL_RTX' if there is not way to determine the return
-   address of other frames.  */
-/* #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) */
-
-/* Define this if the return address of a particular stack frame is
-   accessed from the frame pointer of the previous stack frame.  */
-/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
-
-/* A C expression whose value is RTL representing the location of the incoming
-   return address at the beginning of any function, before the prologue.  This
-   RTL is either a `REG', indicating that the return value is saved in `REG',
-   or a `MEM' representing a location in the stack.
-
-   You only need to define this macro if you want to support call frame
-   debugging information like that provided by DWARF 2.  */
-#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, RETURN_POINTER_REGNUM)
-
-/* A C expression whose value is an integer giving the offset, in bytes, from
-   the value of the stack pointer register to the top of the stack frame at the
-   beginning of any function, before the prologue.  The top of the frame is
-   defined to be the value of the stack pointer in the previous frame, just
-   before the call instruction.
-
-   You only need to define this macro if you want to support call frame
-   debugging information like that provided by DWARF 2.  */
-/* #define INCOMING_FRAME_SP_OFFSET */
-
-/*}}}*/ 
-/*{{{  Register That Address the Stack Frame.  */ 
-
-/* On some machines the offset between the frame pointer and starting offset of
-   the automatic variables is not known until after register allocation has
-   been done (for example, because the saved registers are between these two
-   locations).  On those machines, define `FRAME_POINTER_REGNUM' the number of
-   a special, fixed register to be used internally until the offset is known,
-   and define `HARD_FRAME_POINTER_REGNUM' to be actual the hard register number
-   used for the frame pointer.
-
-   You should define this macro only in the very rare circumstances when it is
-   not possible to calculate the offset between the frame pointer and the
-   automatic variables until after register allocation has been completed.
-   When this macro is defined, you must also indicate in your definition of
-   `ELIMINABLE_REGS' how to eliminate `FRAME_POINTER_REGNUM' into either
-   `HARD_FRAME_POINTER_REGNUM' or `STACK_POINTER_REGNUM'.
-
-   Do not define this macro if it would be the same as `FRAME_POINTER_REGNUM'.  */
-/* #define HARD_FRAME_POINTER_REGNUM */
-
-/* The register number of the arg pointer register, which is used to access the
-   function's argument list.  On some machines, this is the same as the frame
-   pointer register.  On some machines, the hardware determines which register
-   this is.  On other machines, you can choose any register you wish for this
-   purpose.  If this is not the same register as the frame pointer register,
-   then you must mark it as a fixed register according to `FIXED_REGISTERS', or
-   arrange to be able to eliminate it.  */
-#define ARG_POINTER_REGNUM 20
-
-/* The register number of the return address pointer register, which is used to
-   access the current function's return address from the stack.  On some
-   machines, the return address is not at a fixed offset from the frame pointer
-   or stack pointer or argument pointer.  This register can be defined to point
-   to the return address on the stack, and then be converted by
-   `ELIMINABLE_REGS' into either the frame pointer or stack pointer.
-
-   Do not define this macro unless there is no other way to get the return
-   address from the stack.  */
-/* #define RETURN_ADDRESS_POINTER_REGNUM */
-
-/* If the static chain is passed in memory, these macros provide rtx giving
-   `mem' expressions that denote where they are stored.  `STATIC_CHAIN' and
-   `STATIC_CHAIN_INCOMING' give the locations as seen by the calling and called
-   functions, respectively.  Often the former will be at an offset from the
-   stack pointer and the latter at an offset from the frame pointer.
-
-   The variables `stack_pointer_rtx', `frame_pointer_rtx', and
-   `arg_pointer_rtx' will have been initialized prior to the use of these
-   macros and should be used to refer to those items.
-
-   If the static chain is passed in a register, the two previous
-   macros should be defined instead.  */
-/* #define STATIC_CHAIN */
-/* #define STATIC_CHAIN_INCOMING */
-
-/*}}}*/ 
-/*{{{  Eliminating the Frame Pointer and the Arg Pointer */ 
-
-/* A C expression which is nonzero if a function must have and use a frame
-   pointer.  This expression is evaluated in the reload pass.  If its value is
-   nonzero the function will have a frame pointer.
-
-   The expression can in principle examine the current function and decide
-   according to the facts, but on most machines the constant 0 or the constant
-   1 suffices.  Use 0 when the machine allows code to be generated with no
-   frame pointer, and doing so saves some time or space.  Use 1 when there is
-   no possible advantage to avoiding a frame pointer.
-
-   In certain cases, the compiler does not know how to produce valid code
-   without a frame pointer.  The compiler recognizes those cases and
-   automatically gives the function a frame pointer regardless of what
-   `FRAME_POINTER_REQUIRED' says.  You don't need to worry about them.
-
-   In a function that does not require a frame pointer, the frame pointer
-   register can be allocated for ordinary usage, unless you mark it as a fixed
-   register.  See `FIXED_REGISTERS' for more information.  */
-/* #define FRAME_POINTER_REQUIRED 0 */
-#define FRAME_POINTER_REQUIRED \
-     (flag_omit_frame_pointer == 0 || current_function_pretend_args_size > 0)
-
-/* A C statement to store in the variable DEPTH_VAR the difference between the
-   frame pointer and the stack pointer values immediately after the function
-   prologue.  The value would be computed from information such as the result
-   of `get_frame_size ()' and the tables of registers `regs_ever_live' and
-   `call_used_regs'.
-
-   If `ELIMINABLE_REGS' is defined, this macro will be not be used and need not
-   be defined.  Otherwise, it must be defined even if `FRAME_POINTER_REQUIRED'
-   is defined to always be true; in that case, you may set DEPTH-VAR to
-   anything.  */
-/* #define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) */
-
-/* If defined, this macro specifies a table of register pairs used to eliminate
-   unneeded registers that point into the stack frame.  If it is not defined,
-   the only elimination attempted by the compiler is to replace references to
-   the frame pointer with references to the stack pointer.
-
-   The definition of this macro is a list of structure initializations, each of
-   which specifies an original and replacement register.
-
-   On some machines, the position of the argument pointer is not known until
-   the compilation is completed.  In such a case, a separate hard register must
-   be used for the argument pointer.  This register can be eliminated by
-   replacing it with either the frame pointer or the argument pointer,
-   depending on whether or not the frame pointer has been eliminated.
-
-   In this case, you might specify:
-        #define ELIMINABLE_REGS  \
-        {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
-         {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
-         {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
-
-   Note that the elimination of the argument pointer with the stack pointer is
-   specified first since that is the preferred elimination.  */
-
-#define ELIMINABLE_REGS							\
-{									\
-  {ARG_POINTER_REGNUM,	 STACK_POINTER_REGNUM},				\
-  {ARG_POINTER_REGNUM,	 FRAME_POINTER_REGNUM},				\
-  {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}				\
-}
-
-/* A C expression that returns non-zero if the compiler is allowed to try to
-   replace register number FROM with register number TO.  This macro
-   need only be defined if `ELIMINABLE_REGS' is defined, and will usually be
-   the constant 1, since most of the cases preventing register elimination are
-   things that the compiler already knows about.  */
-
-#define CAN_ELIMINATE(FROM, TO)						\
- ((TO) == FRAME_POINTER_REGNUM || ! frame_pointer_needed)
-
-/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'.  It specifies the
-   initial difference between the specified pair of registers.  This macro must
-   be defined if `ELIMINABLE_REGS' is defined.  */
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
-     (OFFSET) = fr30_compute_frame_size (FROM, TO)
-
-/* Define this macro if the `longjmp' function restores registers from the
-   stack frames, rather than from those saved specifically by `setjmp'.
-   Certain quantities must not be kept in registers across a call to `setjmp'
-   on such machines.  */
-/* #define LONGJMP_RESTORE_FROM_STACK */
-
-/*}}}*/ 
-/*{{{  Passing Function Arguments on the Stack */ 
-
-/* Define this macro if an argument declared in a prototype as an integral type
-   smaller than `int' should actually be passed as an `int'.  In addition to
-   avoiding errors in certain cases of mismatch, it also makes for better code
-   on certain machines.  */
-#define PROMOTE_PROTOTYPES 
-
-/* A C expression that is the number of bytes actually pushed onto the stack
-   when an instruction attempts to push NPUSHED bytes.
-
-   If the target machine does not have a push instruction, do not define this
-   macro.  That directs GNU CC to use an alternate strategy: to allocate the
-   entire argument block and then store the arguments into it.
-
-   On some machines, the definition
-
-        #define PUSH_ROUNDING(BYTES) (BYTES)
-
-   will suffice.  But on other machines, instructions that appear to push one
-   byte actually push two bytes in an attempt to maintain alignment.  Then the
-   definition should be
-
-        #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)  */
-/* #define PUSH_ROUNDING(NPUSHED) */
-
-/* If defined, the maximum amount of space required for outgoing arguments will
-   be computed and placed into the variable
-   `current_function_outgoing_args_size'.  No space will be pushed onto the
-   stack for each call; instead, the function prologue should increase the
-   stack frame size by this amount.
-
-   Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not
-   proper.  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Define this macro if functions should assume that stack space has been
-   allocated for arguments even when their values are passed in registers.
-
-   The value of this macro is the size, in bytes, of the area reserved for
-   arguments passed in registers for the function represented by FNDECL.
-
-   This space can be allocated by the caller, or be a part of the
-   machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
-   which.  */
-/* #define REG_PARM_STACK_SPACE(FNDECL) */
-
-/* Define these macros in addition to the one above if functions might allocate
-   stack space for arguments even when their values are passed in registers.
-   These should be used when the stack space allocated for arguments in
-   registers is not a simple constant independent of the function declaration.
-
-   The value of the first macro is the size, in bytes, of the area that we
-   should initially assume would be reserved for arguments passed in registers.
-
-   The value of the second macro is the actual size, in bytes, of the area that
-   will be reserved for arguments passed in registers.  This takes two
-   arguments: an integer representing the number of bytes of fixed sized
-   arguments on the stack, and a tree representing the number of bytes of
-   variable sized arguments on the stack.
-
-   When these macros are defined, `REG_PARM_STACK_SPACE' will only be called
-   for libcall functions, the current function, or for a function being called
-   when it is known that such stack space must be allocated.  In each case this
-   value can be easily computed.
-
-   When deciding whether a called function needs such stack space, and how much
-   space to reserve, GNU CC uses these two macros instead of
-   `REG_PARM_STACK_SPACE'.  */
-/* #define MAYBE_REG_PARM_STACK_SPACE */
-/* #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) */
-
-/* Define this if it is the responsibility of the caller to allocate the area
-   reserved for arguments passed in registers.
-
-   If `ACCUMULATE_OUTGOING_ARGS' is defined, this macro controls whether the
-   space for these arguments counts in the value of
-   `current_function_outgoing_args_size'.  */
-/* #define OUTGOING_REG_PARM_STACK_SPACE */
-
-/* Define this macro if `REG_PARM_STACK_SPACE' is defined, but the stack
-   parameters don't skip the area specified by it.
-
-   Normally, when a parameter is not passed in registers, it is placed on the
-   stack beyond the `REG_PARM_STACK_SPACE' area.  Defining this macro
-   suppresses this behavior and causes the parameter to be passed on the stack
-   in its natural location.  */
-/* #define STACK_PARMS_IN_REG_PARM_AREA */
-
-/* A C expression that should indicate the number of bytes of its own arguments
-   that a function pops on returning, or 0 if the function pops no arguments
-   and the caller must therefore pop them all after the function returns.
-
-   FUNDECL is a C variable whose value is a tree node that describes the
-   function in question.  Normally it is a node of type `FUNCTION_DECL' that
-   describes the declaration of the function.  From this it is possible to
-   obtain the DECL_MACHINE_ATTRIBUTES of the function.
-
-   FUNTYPE is a C variable whose value is a tree node that describes the
-   function in question.  Normally it is a node of type `FUNCTION_TYPE' that
-   describes the data type of the function.  From this it is possible to obtain
-   the data types of the value and arguments (if known).
-
-   When a call to a library function is being considered, FUNTYPE will contain
-   an identifier node for the library function.  Thus, if you need to
-   distinguish among various library functions, you can do so by their names.
-   Note that "library function" in this context means a function used to
-   perform arithmetic, whose name is known specially in the compiler and was
-   not mentioned in the C code being compiled.
-
-   STACK-SIZE is the number of bytes of arguments passed on the stack.  If a
-   variable number of bytes is passed, it is zero, and argument popping will
-   always be the responsibility of the calling function.
-
-   On the Vax, all functions always pop their arguments, so the definition of
-   this macro is STACK-SIZE.  On the 68000, using the standard calling
-   convention, no functions pop their arguments, so the value of the macro is
-   always 0 in this case.  But an alternative calling convention is available
-   in which functions that take a fixed number of arguments pop them but other
-   functions (such as `printf') pop nothing (the caller pops all).  When this
-   convention is in use, FUNTYPE is examined to determine whether a function
-   takes a fixed number of arguments.  */
-#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
-
-/*}}}*/ 
-/*{{{  Function Arguments in Registers */ 
-
-/* Nonzero if we do not know how to pass TYPE solely in registers.
-   We cannot do so in the following cases:
-
-   - if the type has variable size
-   - if the type is marked as addressable (it is required to be constructed
-     into the stack)
-   - if the type is a structure or union. */
-
-#define MUST_PASS_IN_STACK(MODE,TYPE)				\
-   (((MODE) == BLKmode)						\
-    || ((TYPE) != 0						\
-         && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST	\
-	     || TREE_CODE (TYPE) == RECORD_TYPE			\
-	     || TREE_CODE (TYPE) == UNION_TYPE			\
-	     || TREE_CODE (TYPE) == QUAL_UNION_TYPE		\
-             || TREE_ADDRESSABLE (TYPE))))
-
-/* The number of register assigned to holding function arguments.  */
-     
-#define FR30_NUM_ARG_REGS	 4
-
-/* A C expression that controls whether a function argument is passed in a
-   register, and which register.
-
-   The usual way to make the ANSI library `stdarg.h' work on a machine where
-   some arguments are usually passed in registers, is to cause nameless
-   arguments to be passed on the stack instead.  This is done by making
-   `FUNCTION_ARG' return 0 whenever NAMED is 0.
-
-   You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
-   this macro to determine if this argument is of a type that must be passed in
-   the stack.  If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
-   returns non-zero for such an argument, the compiler will abort.  If
-   `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
-   stack and then loaded into a register.  */
-     
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)			\
-  (  (NAMED) == 0                    ? NULL_RTX			\
-   : MUST_PASS_IN_STACK (MODE, TYPE) ? NULL_RTX			\
-   : (CUM) >= FR30_NUM_ARG_REGS      ? NULL_RTX			\
-   : gen_rtx (REG, MODE, CUM + FIRST_ARG_REGNUM))
-
-/* A C type for declaring a variable that is used as the first argument of
-   `FUNCTION_ARG' and other related values.  For some target machines, the type
-   `int' suffices and can hold the number of bytes of argument so far.
-
-   There is no need to record in `CUMULATIVE_ARGS' anything about the arguments
-   that have been passed on the stack.  The compiler has other variables to
-   keep track of that.  For target machines on which all arguments are passed
-   on the stack, there is no need to store anything in `CUMULATIVE_ARGS';
-   however, the data structure must exist and should not be empty, so use
-   `int'.  */
-/* On the FR30 this value is an accumulating count of the number of argument
-   registers that have been filled with argument values, as opposed to say,
-   the number of bytes of argument accumulated so far.  */
-typedef int CUMULATIVE_ARGS;
-
-/* A C expression for the number of words, at the beginning of an argument,
-   must be put in registers.  The value must be zero for arguments that are
-   passed entirely in registers or that are entirely pushed on the stack.
-
-   On some machines, certain arguments must be passed partially in registers
-   and partially in memory.  On these machines, typically the first N words of
-   arguments are passed in registers, and the rest on the stack.  If a
-   multi-word argument (a `double' or a structure) crosses that boundary, its
-   first few words must be passed in registers and the rest must be pushed.
-   This macro tells the compiler when this occurs, and how many of the words
-   should go in registers.
-
-   `FUNCTION_ARG' for these arguments should return the first register to be
-   used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
-   the called function.  */
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 	\
-  fr30_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
-
-extern int fr30_function_arg_partial_nregs PROTO ((CUMULATIVE_ARGS, int, Tree, int));
-
-/* A C expression that indicates when an argument must be passed by reference.
-   If nonzero for an argument, a copy of that argument is made in memory and a
-   pointer to the argument is passed instead of the argument itself.  The
-   pointer is passed in whatever way is appropriate for passing a pointer to
-   that type.
-
-   On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
-   definition of this macro might be:
-        #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)  \
-          MUST_PASS_IN_STACK (MODE, TYPE)  */
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
-  MUST_PASS_IN_STACK (MODE, TYPE)
-
-/* If defined, a C expression that indicates when it is more
-   desirable to keep an argument passed by invisible reference as a
-   reference, rather than copying it to a pseudo register.  */
-/* #define FUNCTION_ARG_KEEP_AS_REFERENCE(CUM, MODE, TYPE, NAMED) */
-
-/* If defined, a C expression that indicates when it is the called function's
-   responsibility to make a copy of arguments passed by invisible reference.
-   Normally, the caller makes a copy and passes the address of the copy to the
-   routine being called.  When FUNCTION_ARG_CALLEE_COPIES is defined and is
-   nonzero, the caller does not make a copy.  Instead, it passes a pointer to
-   the "live" value.  The called function must not modify this value.  If it
-   can be determined that the value won't be modified, it need not make a copy;
-   otherwise a copy must be made.  */
-/* #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) */
-
-/* If defined, a C expression that indicates when it is more desirable to keep
-   an argument passed by invisible reference as a reference, rather than
-   copying it to a pseudo register.  */
-/* #define FUNCTION_ARG_KEEP_AS_REFERENCE(CUM, MODE, TYPE, NAMED) */
-
-/* A C statement (sans semicolon) for initializing the variable CUM for the
-   state at the beginning of the argument list.  The variable has type
-   `CUMULATIVE_ARGS'.  The value of FNTYPE is the tree node for the data type
-   of the function which will receive the args, or 0 if the args are to a
-   compiler support library function.  The value of INDIRECT is nonzero when
-   processing an indirect call, for example a call through a function pointer.
-   The value of INDIRECT is zero for a call to an explicitly named function, a
-   library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
-   arguments for the function being compiled.
-
-   When processing a call to a compiler support library function, LIBNAME
-   identifies which one.  It is a `symbol_ref' rtx which contains the name of
-   the function, as a string.  LIBNAME is 0 when an ordinary C function call is
-   being processed.  Thus, each time this macro is called, either LIBNAME or
-   FNTYPE is nonzero, but never both of them at once.  */
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) (CUM) = 0
-
-/* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
-   arguments for the function being compiled.  If this macro is undefined,
-   `INIT_CUMULATIVE_ARGS' is used instead.
-
-   The value passed for LIBNAME is always 0, since library routines with
-   special calling conventions are never compiled with GNU CC.  The argument
-   LIBNAME exists for symmetry with `INIT_CUMULATIVE_ARGS'.  */
-/* #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) */
-
-/* A C statement (sans semicolon) to update the summarizer variable CUM to
-   advance past an argument in the argument list.  The values MODE, TYPE and
-   NAMED describe that argument.  Once this is done, the variable CUM is
-   suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
-
-   This macro need not do anything if the argument in question was passed on
-   the stack.  The compiler knows how to track the amount of stack space used
-   for arguments without any special help.  */
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
-  (CUM) += (NAMED) * fr30_num_arg_regs (MODE, TYPE)
-
-extern int fr30_num_arg_regs PROTO ((int, Tree));
-
-/* If defined, a C expression which determines whether, and in which direction,
-   to pad out an argument with extra space.  The value should be of type `enum
-   direction': either `upward' to pad above the argument, `downward' to pad
-   below, or `none' to inhibit padding.
-
-   The *amount* of padding is always just enough to reach the next multiple of
-   `FUNCTION_ARG_BOUNDARY'; this macro does not control it.
-
-   This macro has a default definition which is right for most systems.  For
-   little-endian machines, the default is to pad upward.  For big-endian
-   machines, the default is to pad downward for an argument of constant size
-   shorter than an `int', and upward otherwise.  */
-/* #define FUNCTION_ARG_PADDING(MODE, TYPE) */
-
-/* If defined, a C expression that gives the alignment boundary, in bits, of an
-   argument with the specified mode and type.  If it is not defined,
-   `PARM_BOUNDARY' is used for all arguments.  */
-/* #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) */
-
-/* A C expression that is nonzero if REGNO is the number of a hard register in
-   which function arguments are sometimes passed.  This does *not* include
-   implicit arguments such as the static chain and the structure-value address.
-   On many machines, no registers can be used for this purpose since all
-   function arguments are pushed on the stack.  */
-#define FUNCTION_ARG_REGNO_P(REGNO) \
-  ((REGNO) >= FIRST_ARG_REGNUM && ((REGNO) < FIRST_ARG_REGNUM + FR30_NUM_ARG_REGS))
-
-/*}}}*/ 
-/*{{{  How Scalar Function Values are Returned */ 
-
-/* Define this macro if `-traditional' should not cause functions declared to
-   return `float' to convert the value to `double'.  */
-/* #define TRADITIONAL_RETURN_FLOAT */
-
-/* A C expression to create an RTX representing the place where a function
-   returns a value of data type VALTYPE.  VALTYPE is a tree node representing a
-   data type.  Write `TYPE_MODE (VALTYPE)' to get the machine mode used to
-   represent that type.  On many machines, only the mode is relevant.
-   (Actually, on most machines, scalar values are returned in the same place
-   regardless of mode).
-
-   If `PROMOTE_FUNCTION_RETURN' is defined, you must apply the same promotion
-   rules specified in `PROMOTE_MODE' if VALTYPE is a scalar type.
-
-   If the precise function being called is known, FUNC is a tree node
-   (`FUNCTION_DECL') for it; otherwise, FUNC is a null pointer.  This makes it
-   possible to use a different value-returning convention for specific
-   functions when all their calls are known.
-
-   `FUNCTION_VALUE' is not used for return vales with aggregate data types,
-   because these are returned in another way.  See `STRUCT_VALUE_REGNUM' and
-   related macros, below.  */
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-     gen_rtx_REG (TYPE_MODE (VALTYPE), RETURN_VALUE_REGNUM)
-
-/* A C expression to create an RTX representing the place where a library
-   function returns a value of mode MODE.  If the precise function being called
-   is known, FUNC is a tree node (`FUNCTION_DECL') for it; otherwise, FUNC is a
-   null pointer.  This makes it possible to use a different value-returning
-   convention for specific functions when all their calls are known.
-
-   Note that "library function" in this context means a compiler support
-   routine, used to perform arithmetic, whose name is known specially by the
-   compiler and was not mentioned in the C code being compiled.
-
-   The definition of `LIBRARY_VALUE' need not be concerned aggregate data
-   types, because none of the library functions returns such types.  */
-#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, RETURN_VALUE_REGNUM)
-
-/* A C expression that is nonzero if REGNO is the number of a hard register in
-   which the values of called function may come back. */
-
-#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == RETURN_VALUE_REGNUM)
-
-/* Define this macro if `untyped_call' and `untyped_return' need more space
-   than is implied by `FUNCTION_VALUE_REGNO_P' for saving and restoring an
-   arbitrary return value.  */
-/* #define APPLY_RESULT_SIZE */
-
-/*}}}*/ 
-/*{{{  How Large Values are Returned */ 
-
-/* A C expression which can inhibit the returning of certain function values in
-   registers, based on the type of value.  A nonzero value says to return the
-   function value in memory, just as large structures are always returned.
-   Here TYPE will be a C expression of type `tree', representing the data type
-   of the value.
-
-   Note that values of mode `BLKmode' must be explicitly handled by this macro.
-   Also, the option `-fpcc-struct-return' takes effect regardless of this
-   macro.  On most systems, it is possible to leave the macro undefined; this
-   causes a default definition to be used, whose value is the constant 1 for
-   `BLKmode' values, and 0 otherwise.
-
-   Do not use this macro to indicate that structures and unions should always
-   be returned in memory.  You should instead use `DEFAULT_PCC_STRUCT_RETURN'
-   to indicate this.  */
-/* #define RETURN_IN_MEMORY(TYPE) */
-
-/* Define this macro to be 1 if all structure and union return values must be
-   in memory.  Since this results in slower code, this should be defined only
-   if needed for compatibility with other compilers or with an ABI.  If you
-   define this macro to be 0, then the conventions used for structure and union
-   return values are decided by the `RETURN_IN_MEMORY' macro.
-
-   If not defined, this defaults to the value 1.  */
-#define DEFAULT_PCC_STRUCT_RETURN 1
-
-/* If the structure value address is passed in a register, then
-   `STRUCT_VALUE_REGNUM' should be the number of that register.  */
-/* #define STRUCT_VALUE_REGNUM */
-
-/* If the structure value address is not passed in a register, define
-   `STRUCT_VALUE' as an expression returning an RTX for the place where the
-   address is passed.  If it returns 0, the address is passed as an "invisible"
-   first argument.  */
-#define STRUCT_VALUE 0
-
-/* On some architectures the place where the structure value address is found
-   by the called function is not the same place that the caller put it.  This
-   can be due to register windows, or it could be because the function prologue
-   moves it to a different place.
-
-   If the incoming location of the structure value address is in a register,
-   define this macro as the register number.  */
-/* #define STRUCT_VALUE_INCOMING_REGNUM */
-
-/* If the incoming location is not a register, then you should define
-   `STRUCT_VALUE_INCOMING' as an expression for an RTX for where the called
-   function should find the value.  If it should find the value on the stack,
-   define this to create a `mem' which refers to the frame pointer.  A
-   definition of 0 means that the address is passed as an "invisible" first
-   argument.  */
-/* #define STRUCT_VALUE_INCOMING */
-
-/* Define this macro if the usual system convention on the target machine for
-   returning structures and unions is for the called function to return the
-   address of a static variable containing the value.
-
-   Do not define this if the usual system convention is for the caller to pass
-   an address to the subroutine.
-
-   This macro has effect in `-fpcc-struct-return' mode, but it does nothing
-   when you use `-freg-struct-return' mode.  */
-/* #define PCC_STATIC_STRUCT_RETURN */
-
-/*}}}*/ 
-/*{{{  Caller-Saves Register Allocation */ 
-
-/* Define this macro if function calls on the target machine do not preserve
-   any registers; in other words, if `CALL_USED_REGISTERS' has 1 for all
-   registers.  This macro enables `-fcaller-saves' by default.  Eventually that
-   option will be enabled by default on all machines and both the option and
-   this macro will be eliminated.  */
-/* #define DEFAULT_CALLER_SAVES */
-
-/* A C expression to determine whether it is worthwhile to consider placing a
-   pseudo-register in a call-clobbered hard register and saving and restoring
-   it around each function call.  The expression should be 1 when this is worth
-   doing, and 0 otherwise.
-
-   If you don't define this macro, a default is used which is good on most
-   machines: `4 * CALLS < REFS'.  */
-/* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
-
-/*}}}*/ 
-/*{{{  Function Entry and Exit */ 
-
-/* A C compound statement that outputs the assembler code for entry to a
-   function.  The prologue is responsible for setting up the stack frame,
-   initializing the frame pointer register, saving registers that must be
-   saved, and allocating SIZE additional bytes of storage for the local
-   variables.  SIZE is an integer.  FILE is a stdio stream to which the
-   assembler code should be output.
-
-   The label for the beginning of the function need not be output by this
-   macro.  That has already been done when the macro is run.
-
-   To determine which registers to save, the macro can refer to the array
-   `regs_ever_live': element R is nonzero if hard register R is used anywhere
-   within the function.  This implies the function prologue should save
-   register R, provided it is not one of the call-used registers.
-   (`FUNCTION_EPILOGUE' must likewise use `regs_ever_live'.)
-
-   On machines that have "register windows", the function entry code does not
-   save on the stack the registers that are in the windows, even if they are
-   supposed to be preserved by function calls; instead it takes appropriate
-   steps to "push" the register stack, if any non-call-used registers are used
-   in the function.
-
-   On machines where functions may or may not have frame-pointers, the function
-   entry code must vary accordingly; it must set up the frame pointer if one is
-   wanted, and not otherwise.  To determine whether a frame pointer is in
-   wanted, the macro can refer to the variable `frame_pointer_needed'.  The
-   variable's value will be 1 at run time in a function that needs a frame
-   pointer.  *Note Elimination::.
-
-   The function entry code is responsible for allocating any stack space
-   required for the function.  This stack space consists of the regions listed
-   below.  In most cases, these regions are allocated in the order listed, with
-   the last listed region closest to the top of the stack (the lowest address
-   if `STACK_GROWS_DOWNWARD' is defined, and the highest address if it is not
-   defined).  You can use a different order for a machine if doing so is more
-   convenient or required for compatibility reasons.  Except in cases where
-   required by standard or by a debugger, there is no reason why the stack
-   layout used by GCC need agree with that used by other compilers for a
-   machine.
-
-      * A region of `current_function_pretend_args_size' bytes of
-        uninitialized space just underneath the first argument
-        arriving on the stack.  (This may not be at the very start of
-        the allocated stack region if the calling sequence has pushed
-        anything else since pushing the stack arguments.  But
-        usually, on such machines, nothing else has been pushed yet,
-        because the function prologue itself does all the pushing.)
-        This region is used on machines where an argument may be
-        passed partly in registers and partly in memory, and, in some
-        cases to support the features in `varargs.h' and `stdargs.h'.
-
-      * An area of memory used to save certain registers used by the
-        function.  The size of this area, which may also include
-        space for such things as the return address and pointers to
-        previous stack frames, is machine-specific and usually
-        depends on which registers have been used in the function.
-        Machines with register windows often do not require a save
-        area.
-
-      * A region of at least SIZE bytes, possibly rounded up to an
-        allocation boundary, to contain the local variables of the
-        function.  On some machines, this region and the save area
-        may occur in the opposite order, with the save area closer to
-        the top of the stack.
-
-      * Optionally, when `ACCUMULATE_OUTGOING_ARGS' is defined, a
-        region of `current_function_outgoing_args_size' bytes to be
-        used for outgoing argument lists of the function.
-
-   Normally, it is necessary for the macros `FUNCTION_PROLOGUE' and
-   `FUNCTION_EPILOGUE' to treat leaf functions specially.  The C variable
-   `leaf_function' is nonzero for such a function.  */
-/* #define FUNCTION_PROLOGUE(FILE, SIZE) */
-
-/* Define this macro as a C expression that is nonzero if the return
-   instruction or the function epilogue ignores the value of the stack pointer;
-   in other words, if it is safe to delete an instruction to adjust the stack
-   pointer before a return from the function.
-
-   Note that this macro's value is relevant only for functions for which frame
-   pointers are maintained.  It is never safe to delete a final stack
-   adjustment in a function that has no frame pointer, and the compiler knows
-   this regardless of `EXIT_IGNORE_STACK'.  */
-/* #define EXIT_IGNORE_STACK */
-
-/* Define this macro as a C expression that is nonzero for registers
-   are used by the epilogue or the `return' pattern.  The stack and
-   frame pointer registers are already be assumed to be used as
-   needed.  */
-/* #define EPILOGUE_USES(REGNO) */
-
-/* A C compound statement that outputs the assembler code for exit from a
-   function.  The epilogue is responsible for restoring the saved registers and
-   stack pointer to their values when the function was called, and returning
-   control to the caller.  This macro takes the same arguments as the macro
-   `FUNCTION_PROLOGUE', and the registers to restore are determined from
-   `regs_ever_live' and `CALL_USED_REGISTERS' in the same way.
-
-   On some machines, there is a single instruction that does all the work of
-   returning from the function.  On these machines, give that instruction the
-   name `return' and do not define the macro `FUNCTION_EPILOGUE' at all.
-
-   Do not define a pattern named `return' if you want the `FUNCTION_EPILOGUE'
-   to be used.  If you want the target switches to control whether return
-   instructions or epilogues are used, define a `return' pattern with a
-   validity condition that tests the target switches appropriately.  If the
-   `return' pattern's validity condition is false, epilogues will be used.
-
-   On machines where functions may or may not have frame-pointers, the function
-   exit code must vary accordingly.  Sometimes the code for these two cases is
-   completely different.  To determine whether a frame pointer is wanted, the
-   macro can refer to the variable `frame_pointer_needed'.  The variable's
-   value will be 1 when compiling a function that needs a frame pointer.
-
-   Normally, `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' must treat leaf
-   functions specially.  The C variable `leaf_function' is nonzero for such a
-   function.
-
-   On some machines, some functions pop their arguments on exit while others
-   leave that for the caller to do.  For example, the 68020 when given `-mrtd'
-   pops arguments in functions that take a fixed number of arguments.
-
-   Your definition of the macro `RETURN_POPS_ARGS' decides which functions pop
-   their own arguments.  `FUNCTION_EPILOGUE' needs to know what was decided.
-   The variable that is called `current_function_pops_args' is the number of
-   bytes of its arguments that a function should pop.  *Note Scalar Return::.  */
-/* #define FUNCTION_EPILOGUE(FILE, SIZE) */
-
-/* Define this macro if the function epilogue contains delay slots to which
-   instructions from the rest of the function can be "moved".  The definition
-   should be a C expression whose value is an integer representing the number
-   of delay slots there.  */
-/* #define DELAY_SLOTS_FOR_EPILOGUE */
-
-/* A C expression that returns 1 if INSN can be placed in delay slot number N
-   of the epilogue.
-
-   The argument N is an integer which identifies the delay slot now being
-   considered (since different slots may have different rules of eligibility).
-   It is never negative and is always less than the number of epilogue delay
-   slots (what `DELAY_SLOTS_FOR_EPILOGUE' returns).  If you reject a particular
-   insn for a given delay slot, in principle, it may be reconsidered for a
-   subsequent delay slot.  Also, other insns may (at least in principle) be
-   considered for the so far unfilled delay slot.
-
-   The insns accepted to fill the epilogue delay slots are put in an
-   RTL list made with `insn_list' objects, stored in the variable
-   `current_function_epilogue_delay_list'.  The insn for the first
-   delay slot comes first in the list.  Your definition of the macro
-   `FUNCTION_EPILOGUE' should fill the delay slots by outputting the
-   insns in this list, usually by calling `final_scan_insn'.
-
-   You need not define this macro if you did not define
-   `DELAY_SLOTS_FOR_EPILOGUE'.  */
-/* #define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN, N) */
-
-/* A C compound statement that outputs the assembler code for a thunk function,
-   used to implement C++ virtual function calls with multiple inheritance.  The
-   thunk acts as a wrapper around a virtual function, adjusting the implicit
-   object parameter before handing control off to the real function.
-
-   First, emit code to add the integer DELTA to the location that contains the
-   incoming first argument.  Assume that this argument contains a pointer, and
-   is the one used to pass the `this' pointer in C++.  This is the incoming
-   argument *before* the function prologue, e.g. `%o0' on a sparc.  The
-   addition must preserve the values of all other incoming arguments.
-
-   After the addition, emit code to jump to FUNCTION, which is a
-   `FUNCTION_DECL'.  This is a direct pure jump, not a call, and does not touch
-   the return address.  Hence returning from FUNCTION will return to whoever
-   called the current `thunk'.
-
-   The effect must be as if FUNCTION had been called directly with the adjusted
-   first argument.  This macro is responsible for emitting all of the code for
-   a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not
-   invoked.
-
-   The THUNK_FNDECL is redundant.  (DELTA and FUNCTION have already been
-   extracted from it.)  It might possibly be useful on some targets, but
-   probably not.
-
-   If you do not define this macro, the target-independent code in the C++
-   frontend will generate a less efficient heavyweight thunk that calls
-   FUNCTION instead of jumping to it.  The generic approach does not support
-   varargs.  */
-/* #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) */
-
-/*}}}*/ 
-/*{{{  Generating Code for Profiling.  */ 
-
-/* A C statement or compound statement to output to FILE some assembler code to
-   call the profiling subroutine `mcount'.  Before calling, the assembler code
-   must load the address of a counter variable into a register where `mcount'
-   expects to find the address.  The name of this variable is `LP' followed by
-   the number LABELNO, so you would generate the name using `LP%d' in a
-   `fprintf'.
-
-   The details of how the address should be passed to `mcount' are determined
-   by your operating system environment, not by GNU CC.  To figure them out,
-   compile a small program for profiling using the system's installed C
-   compiler and look at the assembler code that results.  */
-#define FUNCTION_PROFILER(FILE, LABELNO)	\
-{						\
-  fprintf (FILE, "\t mov rp, r1\n" );		\
-  fprintf (FILE, "\t ldi:32 mcount, r0\n" );	\
-  fprintf (FILE, "\t call @r0\n" );		\
-  fprintf (FILE, ".word\tLP%d\n", LABELNO);	\
-}
-
-/* Define this macro if the code for function profiling should come before the
-   function prologue.  Normally, the profiling code comes after.  */
-/* #define PROFILE_BEFORE_PROLOGUE */
-
-/* A C statement or compound statement to output to FILE some assembler code to
-   initialize basic-block profiling for the current object module.  The global
-   compile flag `profile_block_flag' distingishes two profile modes.
-
-   profile_block_flag != 2'
-        Output code to call the subroutine `__bb_init_func' once per
-        object module, passing it as its sole argument the address of
-        a block allocated in the object module.
-
-        The name of the block is a local symbol made with this
-        statement:
-
-             ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
-
-        Of course, since you are writing the definition of
-        `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro,
-        you can take a short cut in the definition of this macro and
-        use the name that you know will result.
-
-        The first word of this block is a flag which will be nonzero
-        if the object module has already been initialized.  So test
-        this word first, and do not call `__bb_init_func' if the flag
-        is nonzero.  BLOCK_OR_LABEL contains a unique number which
-        may be used to generate a label as a branch destination when
-        `__bb_init_func' will not be called.
-
-        Described in assembler language, the code to be output looks
-        like:
-
-               cmp (LPBX0),0
-               bne local_label
-               parameter1 <- LPBX0
-               call __bb_init_func
-             local_label:
-
-   profile_block_flag == 2'
-        Output code to call the subroutine `__bb_init_trace_func' and
-        pass two parameters to it.  The first parameter is the same as
-        for `__bb_init_func'.  The second parameter is the number of
-        the first basic block of the function as given by
-        BLOCK_OR_LABEL.  Note that `__bb_init_trace_func' has to be
-        called, even if the object module has been initialized
-        already.
-
-        Described in assembler language, the code to be output looks
-        like:
-             parameter1 <- LPBX0
-             parameter2 <- BLOCK_OR_LABEL
-             call __bb_init_trace_func  */
-/* #define FUNCTION_BLOCK_PROFILER (FILE, LABELNO) */
-
-/* A C statement or compound statement to output to FILE some assembler code to
-   increment the count associated with the basic block number BLOCKNO.  The
-   global compile flag `profile_block_flag' distingishes two profile modes.
-
-   profile_block_flag != 2'
-        Output code to increment the counter directly.  Basic blocks
-        are numbered separately from zero within each compilation.
-        The count associated with block number BLOCKNO is at index
-        BLOCKNO in a vector of words; the name of this array is a
-        local symbol made with this statement:
-
-             ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
-
-        Of course, since you are writing the definition of
-        `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro,
-        you can take a short cut in the definition of this macro and
-        use the name that you know will result.
-
-        Described in assembler language, the code to be output looks
-        like:
-
-             inc (LPBX2+4*BLOCKNO)
-
-   profile_block_flag == 2'
-        Output code to initialize the global structure `__bb' and
-        call the function `__bb_trace_func', which will increment the
-        counter.
-
-        `__bb' consists of two words.  In the first word, the current
-        basic block number, as given by BLOCKNO, has to be stored.  In
-        the second word, the address of a block allocated in the
-        object module has to be stored.  The address is given by the
-        label created with this statement:
-
-             ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
-
-        Described in assembler language, the code to be output looks
-        like:
-             move BLOCKNO -> (__bb)
-             move LPBX0 -> (__bb+4)
-             call __bb_trace_func  */
-/* #define BLOCK_PROFILER(FILE, BLOCKNO) */
-
-/* A C statement or compound statement to output to FILE assembler
-   code to call function `__bb_trace_ret'.  The assembler code should
-   only be output if the global compile flag `profile_block_flag' ==
-   2.  This macro has to be used at every place where code for
-   returning from a function is generated (e.g. `FUNCTION_EPILOGUE').
-   Although you have to write the definition of `FUNCTION_EPILOGUE'
-   as well, you have to define this macro to tell the compiler, that
-   the proper call to `__bb_trace_ret' is produced.  */
-/* #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) */
-
-/* A C statement or compound statement to save all registers, which may be
-   clobbered by a function call, including condition codes.  The `asm'
-   statement will be mostly likely needed to handle this task.  Local labels in
-   the assembler code can be concatenated with the string ID, to obtain a
-   unique lable name.
-
-   Registers or condition codes clobbered by `FUNCTION_PROLOGUE' or
-   `FUNCTION_EPILOGUE' must be saved in the macros `FUNCTION_BLOCK_PROFILER',
-   `FUNCTION_BLOCK_PROFILER_EXIT' and `BLOCK_PROFILER' prior calling
-   `__bb_init_trace_func', `__bb_trace_ret' and `__bb_trace_func' respectively.  */
-/* #define MACHINE_STATE_SAVE(ID) */
-
-/* A C statement or compound statement to restore all registers, including
-   condition codes, saved by `MACHINE_STATE_SAVE'.
-
-   Registers or condition codes clobbered by `FUNCTION_PROLOGUE' or
-   `FUNCTION_EPILOGUE' must be restored in the macros
-   `FUNCTION_BLOCK_PROFILER', `FUNCTION_BLOCK_PROFILER_EXIT' and
-   `BLOCK_PROFILER' after calling `__bb_init_trace_func', `__bb_trace_ret' and
-   `__bb_trace_func' respectively.  */
-/* #define MACHINE_STATE_RESTORE(ID) */
-
-/* A C function or functions which are needed in the library to support block
-   profiling.  */
-/* #define BLOCK_PROFILER_CODE */
-
-/*}}}*/ 
-/*{{{  Implementing the VARARGS Macros.  */ 
-
-/* If defined, is a C expression that produces the machine-specific code for a
-   call to `__builtin_saveregs'.  This code will be moved to the very beginning
-   of the function, before any parameter access are made.  The return value of
-   this function should be an RTX that contains the value to use as the return
-   of `__builtin_saveregs'.
-
-   The argument ARGS is a `tree_list' containing the arguments that were passed
-   to `__builtin_saveregs'.
-
-   If this macro is not defined, the compiler will output an ordinary call to
-   the library function `__builtin_saveregs'.  */
-/* #define EXPAND_BUILTIN_SAVEREGS(ARGS) */
-
-/* This macro offers an alternative to using `__builtin_saveregs' and defining
-   the macro `EXPAND_BUILTIN_SAVEREGS'.  Use it to store the anonymous register
-   arguments into the stack so that all the arguments appear to have been
-   passed consecutively on the stack.  Once this is done, you can use the
-   standard implementation of varargs that works for machines that pass all
-   their arguments on the stack.
-
-   The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
-   the values that obtain after processing of the named arguments.  The
-   arguments MODE and TYPE describe the last named argument--its machine mode
-   and its data type as a tree node.
-
-   The macro implementation should do two things: first, push onto the stack
-   all the argument registers *not* used for the named arguments, and second,
-   store the size of the data thus pushed into the `int'-valued variable whose
-   name is supplied as the argument PRETEND_ARGS_SIZE.  The value that you
-   store here will serve as additional offset for setting up the stack frame.
-
-   Because you must generate code to push the anonymous arguments at compile
-   time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
-   useful on machines that have just a single category of argument register and
-   use it uniformly for all data types.
-
-   If the argument SECOND_TIME is nonzero, it means that the arguments of the
-   function are being analyzed for the second time.  This happens for an inline
-   function, which is not actually compiled until the end of the source file.
-   The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
-   this case.  */
-#define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \
-  if (! SECOND_TIME) \
-    fr30_setup_incoming_varargs (ARGS_SO_FAR, MODE, TYPE, & PRETEND_ARGS_SIZE)
-
-extern void fr30_setup_incoming_varargs
-  PROTO ((CUMULATIVE_ARGS, int, Tree, int *));
-
-/* Define this macro if the location where a function argument is passed
-   depends on whether or not it is a named argument.
-
-   This macro controls how the NAMED argument to `FUNCTION_ARG' is set for
-   varargs and stdarg functions.  With this macro defined, the NAMED argument
-   is always true for named arguments, and false for unnamed arguments.  If
-   this is not defined, but `SETUP_INCOMING_VARARGS' is defined, then all
-   arguments are treated as named.  Otherwise, all named arguments except the
-   last are treated as named.  */
-#define STRICT_ARGUMENT_NAMING 0
-
-/*}}}*/ 
-/*{{{  Trampolines for Nested Functions.  */ 
-
-/* On the FR30, the trampoline is:
-
-   ldi:32 STATIC, r12
-   ldi:32 FUNCTION, r0
-   jmp    @r0
-   
-/* A C statement to output, on the stream FILE, assembler code for a block of
-   data that contains the constant parts of a trampoline.  This code should not
-   include a label--the label is taken care of automatically.  */
-#define TRAMPOLINE_TEMPLATE(FILE)						\
-{										\
-  fprintf (FILE, "\tldi:32\t#0, %s\n", reg_names [STATIC_CHAIN_REGNUM]);	\
-  fprintf (FILE, "\tldi:32\t#0, %s\n", reg_names [COMPILER_SCRATCH_REGISTER]);	\
-  fprintf (FILE, "\tjmp\t@%s\n", reg_names [COMPILER_SCRATCH_REGISTER]);	\
-}
-
-/* The name of a subroutine to switch to the section in which the trampoline
-   template is to be placed.  The default is a value of
-   `readonly_data_section', which places the trampoline in the section
-   containing read-only data.  */
-/* #define TRAMPOLINE_SECTION */
-
-/* A C expression for the size in bytes of the trampoline, as an integer.  */
-#define TRAMPOLINE_SIZE 14
-
-/* Alignment required for trampolines, in bits.
-
-   If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for
-   aligning trampolines.  */
-/* #define TRAMPOLINE_ALIGNMENT */
-
-/* A C statement to initialize the variable parts of a trampoline.  ADDR is an
-   RTX for the address of the trampoline; FNADDR is an RTX for the address of
-   the nested function; STATIC_CHAIN is an RTX for the static chain value that
-   should be passed to the function when it is called.  */
-#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN)			\
-do										\
-{										\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (ADDR, 2)), STATIC_CHAIN);\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (ADDR, 8)), FNADDR);	\
-} while (0);
-
-/* A C expression to allocate run-time space for a trampoline.  The expression
-   value should be an RTX representing a memory reference to the space for the
-   trampoline.
-
-   If this macro is not defined, by default the trampoline is allocated as a
-   stack slot.  This default is right for most machines.  The exceptions are
-   machines where it is impossible to execute instructions in the stack area.
-   On such machines, you may have to implement a separate stack, using this
-   macro in conjunction with `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE'.
-
-   FP points to a data structure, a `struct function', which describes the
-   compilation status of the immediate containing function of the function
-   which the trampoline is for.  Normally (when `ALLOCATE_TRAMPOLINE' is not
-   defined), the stack slot for the trampoline is in the stack frame of this
-   containing function.  Other allocation strategies probably must do something
-   analogous with this information.  */
-/* #define ALLOCATE_TRAMPOLINE(FP) */
-
-/* Implementing trampolines is difficult on many machines because they have
-   separate instruction and data caches.  Writing into a stack location fails
-   to clear the memory in the instruction cache, so when the program jumps to
-   that location, it executes the old contents.
-
-   Here are two possible solutions.  One is to clear the relevant parts of the
-   instruction cache whenever a trampoline is set up.  The other is to make all
-   trampolines identical, by having them jump to a standard subroutine.  The
-   former technique makes trampoline execution faster; the latter makes
-   initialization faster.
-
-   To clear the instruction cache when a trampoline is initialized, define the
-   following macros which describe the shape of the cache.  */
-
-/* The total size in bytes of the cache.  */
-/* #define INSN_CACHE_SIZE */
-
-/* The length in bytes of each cache line.  The cache is divided into cache
-   lines which are disjoint slots, each holding a contiguous chunk of data
-   fetched from memory.  Each time data is brought into the cache, an entire
-   line is read at once.  The data loaded into a cache line is always aligned
-   on a boundary equal to the line size.  */
-/* #define INSN_CACHE_LINE_WIDTH */
-
-/* The number of alternative cache lines that can hold any particular memory
-   location.  */
-/* #define INSN_CACHE_DEPTH */
-
-/* Alternatively, if the machine has system calls or instructions to clear the
-   instruction cache directly, you can define the following macro.  */
-
-/* If defined, expands to a C expression clearing the *instruction cache* in
-   the specified interval.  If it is not defined, and the macro INSN_CACHE_SIZE
-   is defined, some generic code is generated to clear the cache.  The
-   definition of this macro would typically be a series of `asm' statements.
-   Both BEG and END are both pointer expressions.  */
-/* #define CLEAR_INSN_CACHE (BEG, END) */
-
-/* To use a standard subroutine, define the following macro.  In addition, you
-   must make sure that the instructions in a trampoline fill an entire cache
-   line with identical instructions, or else ensure that the beginning of the
-   trampoline code is always aligned at the same point in its cache line.  Look
-   in `m68k.h' as a guide.  */
-
-/* Define this macro if trampolines need a special subroutine to do their work.
-   The macro should expand to a series of `asm' statements which will be
-   compiled with GNU CC.  They go in a library function named
-   `__transfer_from_trampoline'.
-
-   If you need to avoid executing the ordinary prologue code of a compiled C
-   function when you jump to the subroutine, you can do so by placing a special
-   label of your own in the assembler code.  Use one `asm' statement to
-   generate an assembler label, and another to make the label global.  Then
-   trampolines can use that label to jump directly to your special assembler
-   code.  */
-/* #define TRANSFER_FROM_TRAMPOLINE */
-
-/*}}}*/ 
-/*{{{  Implicit Calls to Library Routines */ 
-
-/* A C string constant giving the name of the function to call for
-   multiplication of one signed full-word by another.  If you do not define
-   this macro, the default name is used, which is `__mulsi3', a function
-   defined in `libgcc.a'.  */
-/* #define MULSI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for division of
-   one signed full-word by another.  If you do not define this macro, the
-   default name is used, which is `__divsi3', a function defined in `libgcc.a'.  */
-/* #define DIVSI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for division of
-   one unsigned full-word by another.  If you do not define this macro, the
-   default name is used, which is `__udivsi3', a function defined in
-   `libgcc.a'.  */
-/* #define UDIVSI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for the
-   remainder in division of one signed full-word by another.  If you do not
-   define this macro, the default name is used, which is `__modsi3', a function
-   defined in `libgcc.a'.  */
-/* #define MODSI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for the
-   remainder in division of one unsigned full-word by another.  If you do not
-   define this macro, the default name is used, which is `__umodsi3', a
-   function defined in `libgcc.a'.  */
-/* #define UMODSI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for
-   multiplication of one signed double-word by another.  If you do not define
-   this macro, the default name is used, which is `__muldi3', a function
-   defined in `libgcc.a'.  */
-/* #define MULDI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for division of
-   one signed double-word by another.  If you do not define this macro, the
-   default name is used, which is `__divdi3', a function defined in `libgcc.a'.  */
-/* #define DIVDI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for division of
-   one unsigned full-word by another.  If you do not define this macro, the
-   default name is used, which is `__udivdi3', a function defined in
-   `libgcc.a'.  */
-/* #define UDIVDI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for the
-   remainder in division of one signed double-word by another.  If you do not
-   define this macro, the default name is used, which is `__moddi3', a function
-   defined in `libgcc.a'.  */
-/* #define MODDI3_LIBCALL */
-
-/* A C string constant giving the name of the function to call for the
-   remainder in division of one unsigned full-word by another.  If you do not
-   define this macro, the default name is used, which is `__umoddi3', a
-   function defined in `libgcc.a'.  */
-/* #define UMODDI3_LIBCALL */
-
-/* Define this macro as a C statement that declares additional library routines
-   renames existing ones. `init_optabs' calls this macro after initializing all
-   the normal library routines.  */
-/* #define INIT_TARGET_OPTABS */
-
-/* The value of `EDOM' on the target machine, as a C integer constant
-   expression.  If you don't define this macro, GNU CC does not attempt to
-   deposit the value of `EDOM' into `errno' directly.  Look in
-   `/usr/include/errno.h' to find the value of `EDOM' on your system.
-
-   If you do not define `TARGET_EDOM', then compiled code reports domain errors
-   by calling the library function and letting it report the error.  If
-   mathematical functions on your system use `matherr' when there is an error,
-   then you should leave `TARGET_EDOM' undefined so that `matherr' is used
-   normally.  */
-/* #define TARGET_EDOM */
-
-/* Define this macro as a C expression to create an rtl expression that refers
-   to the global "variable" `errno'.  (On certain systems, `errno' may not
-   actually be a variable.)  If you don't define this macro, a reasonable
-   default is used.  */
-/* #define GEN_ERRNO_RTX */
-
-/* Define this macro if GNU CC should generate calls to the System V (and ANSI
-   C) library functions `memcpy' and `memset' rather than the BSD functions
-   `bcopy' and `bzero'.
-
-   Defined in svr4.h.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Define this macro if only `float' arguments cannot be passed to library
-   routines (so they must be converted to `double').  This macro affects both
-   how library calls are generated and how the library routines in `libgcc1.c'
-   accept their arguments.  It is useful on machines where floating and fixed
-   point arguments are passed differently, such as the i860.  */
-/* #define LIBGCC_NEEDS_DOUBLE */
-
-/* Define this macro to override the type used by the library routines to pick
-   up arguments of type `float'.  (By default, they use a union of `float' and
-   `int'.)
-
-   The obvious choice would be `float'--but that won't work with traditional C
-   compilers that expect all arguments declared as `float' to arrive as
-   `double'.  To avoid this conversion, the library routines ask for the value
-   as some other type and then treat it as a `float'.
-
-   On some systems, no other type will work for this.  For these systems, you
-   must use `LIBGCC_NEEDS_DOUBLE' instead, to force conversion of the values
-   `double' before they are passed.  */
-/* #define FLOAT_ARG_TYPE */
-
-/* Define this macro to override the way library routines redesignate a `float'
-   argument as a `float' instead of the type it was passed as.  The default is
-   an expression which takes the `float' field of the union.  */
-/* #define FLOATIFY(PASSED_VALUE) */
-
-/* Define this macro to override the type used by the library routines to
-   return values that ought to have type `float'.  (By default, they use
-   `int'.)
-
-   The obvious choice would be `float'--but that won't work with traditional C
-   compilers gratuitously convert values declared as `float' into `double'.  */
-/* #define FLOAT_VALUE_TYPE */
-
-/* Define this macro to override the way the value of a `float'-returning
-   library routine should be packaged in order to return it.  These functions
-   are actually declared to return type `FLOAT_VALUE_TYPE' (normally `int').
-
-   These values can't be returned as type `float' because traditional C
-   compilers would gratuitously convert the value to a `double'.
-
-   A local variable named `intify' is always available when the macro `INTIFY'
-   is used.  It is a union of a `float' field named `f' and a field named `i'
-   whose type is `FLOAT_VALUE_TYPE' or `int'.
-
-   If you don't define this macro, the default definition works by copying the
-   value through that union.  */
-/* #define INTIFY(FLOAT_VALUE) */
-
-/* Define this macro as the name of the data type corresponding to `SImode' in
-   the system's own C compiler.
-
-   You need not define this macro if that type is `long int', as it usually is.  */
-/* #define nongcc_SI_type */
-
-/* Define this macro as the name of the data type corresponding to the
-   word_mode in the system's own C compiler.
-
-   You need not define this macro if that type is `long int', as it usually is.  */
-/* #define nongcc_word_type */
-
-/* Define these macros to supply explicit C statements to carry out various
-   arithmetic operations on types `float' and `double' in the library routines
-   in `libgcc1.c'.  See that file for a full list of these macros and their
-   arguments.
-
-   On most machines, you don't need to define any of these macros, because the
-   C compiler that comes with the system takes care of doing them.  */
-/* #define perform_... */
-
-/* Define this macro to generate code for Objective C message sending using the
-   calling convention of the NeXT system.  This calling convention involves
-   passing the object, the selector and the method arguments all at once to the
-   method-lookup library function.
-
-   The default calling convention passes just the object and the selector to
-   the lookup function, which returns a pointer to the method.  */
-/* #define NEXT_OBJC_RUNTIME */
-
-/*}}}*/ 
-/*{{{  Addressing Modes */ 
-
-/* Define this macro if the machine supports post-increment addressing.  */
-/* #define HAVE_POST_INCREMENT 0 */
-
-/* Similar for other kinds of addressing.  */
-/* #define HAVE_PRE_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-/* #define HAVE_PRE_DECREMENT 0 */
-
-/* A C expression that is 1 if the RTX X is a constant which is a valid
-   address.  On most machines, this can be defined as `CONSTANT_P (X)', but a
-   few machines are more restrictive in which constant addresses are supported.
-
-   `CONSTANT_P' accepts integer-values expressions whose values are not
-   explicitly known, such as `symbol_ref', `label_ref', and `high' expressions
-   and `const' arithmetic expressions, in addition to `const_int' and
-   `const_double' expressions.  */
-#define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
-
-/* A number, the maximum number of registers that can appear in a valid memory
-   address.  Note that it is up to you to specify a value equal to the maximum
-   number that `GO_IF_LEGITIMATE_ADDRESS' would ever accept.  */
-#define MAX_REGS_PER_ADDRESS 1
-
-/* A C compound statement with a conditional `goto LABEL;' executed if X (an
-   RTX) is a legitimate memory address on the target machine for a memory
-   operand of mode MODE.
-
-   It usually pays to define several simpler macros to serve as subroutines for
-   this one.  Otherwise it may be too complicated to understand.
-
-   This macro must exist in two variants: a strict variant and a non-strict
-   one.  The strict variant is used in the reload pass.  It must be defined so
-   that any pseudo-register that has not been allocated a hard register is
-   considered a memory reference.  In contexts where some kind of register is
-   required, a pseudo-register with no hard register must be rejected.
-
-   The non-strict variant is used in other passes.  It must be defined to
-   accept all pseudo-registers in every context where some kind of register is
-   required.
-
-   Compiler source files that want to use the strict variant of this macro
-   define the macro `REG_OK_STRICT'.  You should use an `#ifdef REG_OK_STRICT'
-   conditional to define the strict variant in that case and the non-strict
-   variant otherwise.
-
-   Subroutines to check for acceptable registers for various purposes (one for
-   base registers, one for index registers, and so on) are typically among the
-   subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'.  Then only these
-   subroutine macros need have two variants; the higher levels of macros may be
-   the same whether strict or not.
-
-   Normally, constant addresses which are the sum of a `symbol_ref' and an
-   integer are stored inside a `const' RTX to mark them as constant.
-   Therefore, there is no need to recognize such sums specifically as
-   legitimate addresses.  Normally you would simply recognize any `const' as
-   legitimate.
-
-   Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
-   are not marked with `const'.  It assumes that a naked `plus' indicates
-   indexing.  If so, then you *must* reject such naked constant sums as
-   illegitimate addresses, so that none of them will be given to
-   `PRINT_OPERAND_ADDRESS'.
-
-   On some machines, whether a symbolic address is legitimate depends on the
-   section that the address refers to.  On these machines, define the macro
-   `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
-   then check for it here.  When you see a `const', you will have to look
-   inside it to find the `symbol_ref' in order to determine the section.
-
-   The best way to modify the name string is by adding text to the beginning,
-   with suitable punctuation to prevent any ambiguity.  Allocate the new name
-   in `saveable_obstack'.  You will have to modify `ASM_OUTPUT_LABELREF' to
-   remove and decode the added text and output the name accordingly, and define
-   `STRIP_NAME_ENCODING' to access the original name string.
-
-   You can check the information stored here into the `symbol_ref' in the
-   definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
-   `PRINT_OPERAND_ADDRESS'.
-
-   Used in explow.c, recog.c, reload.c.  */
-
-/* On the FR30 we only have one real addressing mode - an address in a
-   register.  There are three special cases however:
-   
-   * indexed addressing using small positive offsets from the stack pointer
-   
-   * indexed addressing using small signed offsets from the frame pointer
-
-   * register plus register addresing using R13 as the base register.
-
-   At the moment we only support the first two of these special cases.  */
-   
-#ifdef REG_OK_STRICT
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL)			\
-  do									\
-    {									\
-      if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
-        goto LABEL;							\
-      if (GET_CODE (X) == PLUS						\
-	  && ((MODE) == SImode || (MODE) == SFmode)			\
-	  && XEXP (X, 0) == stack_pointer_rtx				\
-	  && GET_CODE (XEXP (X, 1)) == CONST_INT			\
-	  && IN_RANGE (INTVAL (XEXP (X, 1)), 0, (1 <<  6) - 4))		\
-	goto LABEL;							\
-      if (GET_CODE (X) == PLUS						\
-	  && ((MODE) == SImode || (MODE) == SFmode)			\
-	  && XEXP (X, 0) == frame_pointer_rtx				\
-	  && GET_CODE (XEXP (X, 1)) == CONST_INT			\
-	  && IN_RANGE (INTVAL (XEXP (X, 1)), -(1 << 9), (1 <<  9) - 4))	\
-        goto LABEL;							\
-    }									\
-  while (0)
-#else
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL)			\
-  do									\
-    {									\
-      if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
-        goto LABEL;							\
-      if (GET_CODE (X) == PLUS						\
-	  && ((MODE) == SImode || (MODE) == SFmode)			\
-	  && XEXP (X, 0) == stack_pointer_rtx				\
-	  && GET_CODE (XEXP (X, 1)) == CONST_INT			\
-	  && IN_RANGE (INTVAL (XEXP (X, 1)), 0, (1 <<  6) - 4))		\
-	goto LABEL;							\
-      if (GET_CODE (X) == PLUS						\
-	  && ((MODE) == SImode || (MODE) == SFmode)			\
-	  && (XEXP (X, 0) == frame_pointer_rtx				\
-	      || XEXP(X,0) == arg_pointer_rtx)				\
-	  && GET_CODE (XEXP (X, 1)) == CONST_INT			\
-	  && IN_RANGE (INTVAL (XEXP (X, 1)), -(1 << 9), (1 <<  9) - 4))	\
-        goto LABEL;							\
-    }									\
-  while (0)
-#endif
-
-/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
-   use as a base register.  For hard registers, it should always accept those
-   which the hardware permits and reject the others.  Whether the macro accepts
-   or rejects pseudo registers must be controlled by `REG_OK_STRICT' as
-   described above.  This usually requires two variant definitions, of which
-   `REG_OK_STRICT' controls the one actually used.  */
-#ifdef REG_OK_STRICT
-#define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) <= STACK_POINTER_REGNUM)
-#else
-#define REG_OK_FOR_BASE_P(X) 1
-#endif
-
-/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
-   use as an index register.
-
-   The difference between an index register and a base register is that the
-   index register may be scaled.  If an address involves the sum of two
-   registers, neither one of them scaled, then either one may be labeled the
-   "base" and the other the "index"; but whichever labeling is used must fit
-   the machine's constraints of which registers may serve in each capacity.
-   The compiler will try both labelings, looking for one that is valid, and
-   will reload one or both registers only if neither labeling works.  */
-#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
-
-/* A C compound statement that attempts to replace X with a valid memory
-   address for an operand of mode MODE.  WIN will be a C statement label
-   elsewhere in the code; the macro definition may use
-
-        GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
-
-   to avoid further processing if the address has become legitimate.
-
-   X will always be the result of a call to `break_out_memory_refs', and OLDX
-   will be the operand that was given to that function to produce X.
-
-   The code generated by this macro should not alter the substructure of X.  If
-   it transforms X into a more legitimate form, it should assign X (which will
-   always be a C variable) a new value.
-
-   It is not necessary for this macro to come up with a legitimate address.
-   The compiler has standard ways of doing so in all cases.  In fact, it is
-   safe for this macro to do nothing.  But often a machine-dependent strategy
-   can generate better code.  */
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
-
-/* A C statement or compound statement with a conditional `goto LABEL;'
-   executed if memory address X (an RTX) can have different meanings depending
-   on the machine mode of the memory reference it is used for or if the address
-   is valid for some modes but not others.
-
-   Autoincrement and autodecrement addresses typically have mode-dependent
-   effects because the amount of the increment or decrement is the size of the
-   operand being addressed.  Some machines have other mode-dependent addresses.
-   Many RISC machines have no mode-dependent addresses.
-
-   You may assume that ADDR is a valid address for the machine.  */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
-
-/* A C expression that is nonzero if X is a legitimate constant for an
-   immediate operand on the target machine.  You can assume that X satisfies
-   `CONSTANT_P', so you need not check this.  In fact, `1' is a suitable
-   definition for this macro on machines where anything `CONSTANT_P' is valid.  */
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/*}}}*/ 
-/*{{{  Condition Code Status */ 
-
-/* C code for a data type which is used for declaring the `mdep' component of
-   `cc_status'.  It defaults to `int'.
-
-   This macro is not used on machines that do not use `cc0'.  */
-/* #define CC_STATUS_MDEP */
-
-/* A C expression to initialize the `mdep' field to "empty".  The default
-   definition does nothing, since most machines don't use the field anyway.  If
-   you want to use the field, you should probably define this macro to
-   initialize it.
-
-   This macro is not used on machines that do not use `cc0'.  */
-/* #define CC_STATUS_MDEP_INIT */
-
-/* A C compound statement to set the components of `cc_status' appropriately
-   for an insn INSN whose body is EXP.  It is this macro's responsibility to
-   recognize insns that set the condition code as a byproduct of other activity
-   as well as those that explicitly set `(cc0)'.
-
-   This macro is not used on machines that do not use `cc0'.
-
-   If there are insns that do not set the condition code but do alter other
-   machine registers, this macro must check to see whether they invalidate the
-   expressions that the condition code is recorded as reflecting.  For example,
-   on the 68000, insns that store in address registers do not set the condition
-   code, which means that usually `NOTICE_UPDATE_CC' can leave `cc_status'
-   unaltered for such insns.  But suppose that the previous insn set the
-   condition code based on location `a4@(102)' and the current insn stores a
-   new value in `a4'.  Although the condition code is not changed by this, it
-   will no longer be true that it reflects the contents of `a4@(102)'.
-   Therefore, `NOTICE_UPDATE_CC' must alter `cc_status' in this case to say
-   that nothing is known about the condition code value.
-
-   The definition of `NOTICE_UPDATE_CC' must be prepared to deal with the
-   results of peephole optimization: insns whose patterns are `parallel' RTXs
-   containing various `reg', `mem' or constants which are just the operands.
-   The RTL structure of these insns is not sufficient to indicate what the
-   insns actually do.  What `NOTICE_UPDATE_CC' should do when it sees one is
-   just to run `CC_STATUS_INIT'.
-
-   A possible definition of `NOTICE_UPDATE_CC' is to call a function that looks
-   at an attribute named, for example, `cc'.  This
-   avoids having detailed information about patterns in two places, the `md'
-   file and in `NOTICE_UPDATE_CC'.  */
-/* #define NOTICE_UPDATE_CC(EXP, INSN) fr30_notice_update_cc (INSN)
-  extern int fr30_notice_update_cc PROTO ((Rtx)); */
-
-/* A list of names to be used for additional modes for condition code values in
-   registers.  These names are added to `enum
-   machine_mode' and all have class `MODE_CC'.  By convention, they should
-   start with `CC' and end with `mode'.
-
-   You should only define this macro if your machine does not use `cc0' and
-   only if additional modes are required.  */
-/* #define EXTRA_CC_MODES */
-
-/* A list of C strings giving the names for the modes listed in
-   `EXTRA_CC_MODES'.  For example, the Sparc defines this macro and
-   `EXTRA_CC_MODES' as
-
-        #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
-        #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
-
-   This macro is not required if `EXTRA_CC_MODES' is not defined.  */
-/* #define EXTRA_CC_NAMES */
-
-/* Returns a mode from class `MODE_CC' to be used when comparison operation
-   code OP is applied to rtx X and Y.  For example, on the Sparc,
-   `SELECT_CC_MODE' is defined as (see *note Jump Patterns::.  for a
-   description of the reason for this definition)
-
-        #define SELECT_CC_MODE(OP,X,Y) \
-          (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT          \
-           ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode)    \
-           : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS    \
-               || GET_CODE (X) == NEG) \
-              ? CC_NOOVmode : CCmode))
-
-   You need not define this macro if `EXTRA_CC_MODES' is not defined.  */
-/* #define SELECT_CC_MODE(OP, X, Y) */
-
-/* One some machines not all possible comparisons are defined, but you can
-   convert an invalid comparison into a valid one.  For example, the Alpha does
-   not have a `GT' comparison, but you can use an `LT' comparison instead and
-   swap the order of the operands.
-
-   On such machines, define this macro to be a C statement to do any required
-   conversions.  CODE is the initial comparison code and OP0 and OP1 are the
-   left and right operands of the comparison, respectively.  You should modify
-   CODE, OP0, and OP1 as required.
-
-   GNU CC will not assume that the comparison resulting from this macro is
-   valid but will see if the resulting insn matches a pattern in the `md' file.
-
-   You need not define this macro if it would never change the comparison code
-   or operands.  */
-/* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
-
-/* A C expression whose value is one if it is always safe to reverse a
-   comparison whose mode is MODE.  If `SELECT_CC_MODE' can ever return MODE for
-   a floating-point inequality comparison, then `REVERSIBLE_CC_MODE (MODE)'
-   must be zero.
-
-   You need not define this macro if it would always returns zero or if the
-   floating-point format is anything other than `IEEE_FLOAT_FORMAT'.  For
-   example, here is the definition used on the Sparc, where floating-point
-   inequality comparisons are always given `CCFPEmode':
-
-        #define REVERSIBLE_CC_MODE(MODE)  ((MODE) != CCFPEmode)  */
-/* #define REVERSIBLE_CC_MODE(MODE) */
-
-/*}}}*/ 
-/*{{{  Describing Relative Costs of Operations */ 
-
-/* A part of a C `switch' statement that describes the relative costs of
-   constant RTL expressions.  It must contain `case' labels for expression
-   codes `const_int', `const', `symbol_ref', `label_ref' and `const_double'.
-   Each case must ultimately reach a `return' statement to return the relative
-   cost of the use of that kind of constant value in an expression.  The cost
-   may depend on the precise value of the constant, which is available for
-   examination in X, and the rtx code of the expression in which it is
-   contained, found in OUTER_CODE.
-
-   CODE is the expression code--redundant, since it can be obtained with
-   `GET_CODE (X)'.  */
-/* #define CONST_COSTS(X, CODE, OUTER_CODE) */
-
-/* Like `CONST_COSTS' but applies to nonconstant RTL expressions.  This can be
-   used, for example, to indicate how costly a multiply instruction is.  In
-   writing this macro, you can use the construct `COSTS_N_INSNS (N)' to specify
-   a cost equal to N fast instructions.  OUTER_CODE is the code of the
-   expression in which X is contained.
-
-   This macro is optional; do not define it if the default cost assumptions are
-   adequate for the target machine.  */
-/* #define RTX_COSTS(X, CODE, OUTER_CODE) */
-
-/* An expression giving the cost of an addressing mode that contains ADDRESS.
-   If not defined, the cost is computed from the ADDRESS expression and the
-   `CONST_COSTS' values.
-
-   For most CISC machines, the default cost is a good approximation of the true
-   cost of the addressing mode.  However, on RISC machines, all instructions
-   normally have the same length and execution time.  Hence all addresses will
-   have equal costs.
-
-   In cases where more than one form of an address is known, the form with the
-   lowest cost will be used.  If multiple forms have the same, lowest, cost,
-   the one that is the most complex will be used.
-
-   For example, suppose an address that is equal to the sum of a register and a
-   constant is used twice in the same basic block.  When this macro is not
-   defined, the address will be computed in a register and memory references
-   will be indirect through that register.  On machines where the cost of the
-   addressing mode containing the sum is no higher than that of a simple
-   indirect reference, this will produce an additional instruction and possibly
-   require an additional register.  Proper specification of this macro
-   eliminates this overhead for such machines.
-
-   Similar use of this macro is made in strength reduction of loops.
-
-   ADDRESS need not be valid as an address.  In such a case, the cost is not
-   relevant and can be any value; invalid addresses need not be assigned a
-   different cost.
-
-   On machines where an address involving more than one register is as cheap as
-   an address computation involving only one register, defining `ADDRESS_COST'
-   to reflect this can cause two registers to be live over a region of code
-   where only one would have been if `ADDRESS_COST' were not defined in that
-   manner.  This effect should be considered in the definition of this macro.
-   Equivalent costs should probably only be given to addresses with different
-   numbers of registers on machines with lots of registers.
-
-   This macro will normally either not be defined or be defined as a constant.  */
-/* #define ADDRESS_COST(ADDRESS) */
-
-/* A C expression for the cost of moving data from a register in class FROM to
-   one in class TO.  The classes are expressed using the enumeration values
-   such as `GENERAL_REGS'.  A value of 4 is the default; other values are
-   interpreted relative to that.
-
-   It is not required that the cost always equal 2 when FROM is the same as TO;
-   on some machines it is expensive to move between registers if they are not
-   general registers.
-
-   If reload sees an insn consisting of a single `set' between two hard
-   registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
-   value of 2, reload does not check to ensure that the constraints of the insn
-   are met.  Setting a cost of other than 2 will allow reload to verify that
-   the constraints are met.  You should do this if the `movM' pattern's
-   constraints do not allow such copying.  */
-/* #define REGISTER_MOVE_COST(FROM, TO) */
-
-/* A C expression for the cost of moving data of mode M between a register and
-   memory.  A value of 2 is the default; this cost is relative to those in
-   `REGISTER_MOVE_COST'.
-
-   If moving between registers and memory is more expensive than between two
-   registers, you should define this macro to express the relative cost.  */
-/* #define MEMORY_MOVE_COST(M,C,I) */
-
-/* A C expression for the cost of a branch instruction.  A value of 1 is the
-   default; other values are interpreted relative to that.
-
-/* Here are additional macros which do not specify precise relative costs, but
-   only that certain actions are more expensive than GNU CC would ordinarily
-   expect.  */
-
-/* #define BRANCH_COST */
-
-/* Define this macro as a C expression which is nonzero if accessing less than
-   a word of memory (i.e. a `char' or a `short') is no faster than accessing a
-   word of memory, i.e., if such access require more than one instruction or if
-   there is no difference in cost between byte and (aligned) word loads.
-
-   When this macro is not defined, the compiler will access a field by finding
-   the smallest containing object; when it is defined, a fullword load will be
-   used if alignment permits.  Unless bytes accesses are faster than word
-   accesses, using word accesses is preferable since it may eliminate
-   subsequent memory access if subsequent accesses occur to other fields in the
-   same word of the structure, but to different bytes.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* Define this macro if zero-extension (of a `char' or `short' to an `int') can
-   be done faster if the destination is a register that is known to be zero.
-
-   If you define this macro, you must have instruction patterns that recognize
-   RTL structures like this:
-
-        (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
-   and likewise for `HImode'.  */
-#define SLOW_ZERO_EXTEND 0
-
-/* Define this macro to be the value 1 if unaligned accesses have a cost many
-   times greater than aligned accesses, for example if they are emulated in a
-   trap handler.
-
-   When this macro is non-zero, the compiler will act as if `STRICT_ALIGNMENT'
-   were non-zero when generating code for block moves.  This can cause
-   significantly more instructions to be produced.  Therefore, do not set this
-   macro non-zero if unaligned accesses only add a cycle or two to the time for
-   a memory access.
-
-   If the value of this macro is always zero, it need not be defined.  */
-/* #define SLOW_UNALIGNED_ACCESS */
-
-/* Define this macro to inhibit strength reduction of memory addresses.  (On
-   some machines, such strength reduction seems to do harm rather than good.)  */
-/* #define DONT_REDUCE_ADDR */
-
-/* The number of scalar move insns which should be generated instead of a
-   string move insn or a library call.  Increasing the value will always make
-   code faster, but eventually incurs high cost in increased code size.
-
-   If you don't define this, a reasonable default is used.  */
-/* #define MOVE_RATIO */
-
-/* Define this macro if it is as good or better to call a constant function
-   address than to call an address kept in a register.  */
-/* #define NO_FUNCTION_CSE */
-
-/* Define this macro if it is as good or better for a function to call itself
-   with an explicit address than to call an address kept in a register.  */
-/* #define NO_RECURSIVE_FUNCTION_CSE */
-
-/* A C statement (sans semicolon) to update the integer variable COST based on
-   the relationship between INSN that is dependent on DEP_INSN through the
-   dependence LINK.  The default is to make no adjustment to COST.  This can be
-   used for example to specify to the scheduler that an output- or
-   anti-dependence does not incur the same cost as a data-dependence.  */
-/* #define ADJUST_COST(INSN, LINK, DEP_INSN, COST) */
-
-/* A C statement (sans semicolon) to update the integer scheduling
-   priority `INSN_PRIORITY(INSN)'.  Reduce the priority to execute
-   the INSN earlier, increase the priority to execute INSN later.
-   Do not define this macro if you do not need to adjust the
-   scheduling priorities of insns.  */
-/* #define ADJUST_PRIORITY (INSN) */
-
-/*}}}*/ 
-/*{{{  Dividing the output into sections.  */ 
-
-/* A C expression whose value is a string containing the assembler operation
-   that should precede instructions and read-only data.  Normally `".text"' is
-   right.  */
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* A C expression whose value is a string containing the assembler operation to
-   identify the following data as writable initialized data.  Normally
-   `".data"' is right.  */
-#define DATA_SECTION_ASM_OP ".data"
-
-/* if defined, a C expression whose value is a string containing the assembler
-   operation to identify the following data as shared data.  If not defined,
-   `DATA_SECTION_ASM_OP' will be used.  */
-/* #define SHARED_SECTION_ASM_OP */
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as
-   uninitialized global data.  If not defined, and neither
-   `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
-   uninitialized global data will be output in the data section if
-   `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
-   used.  */
-#define BSS_SECTION_ASM_OP ".bss"
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as
-   uninitialized global shared data.  If not defined, and
-   `BSS_SECTION_ASM_OP' is, the latter will be used.  */
-/* #define SHARED_BSS_SECTION_ASM_OP */
-
-/* A list of names for sections other than the standard two, which are
-   `in_text' and `in_data'.  You need not define this macro on a system with no
-   other sections (that GCC needs to use).
-
-   Defined in svr4.h.  */
-/* #define EXTRA_SECTIONS */
-
-/* One or more functions to be defined in `varasm.c'.  These functions should
-   do jobs analogous to those of `text_section' and `data_section', for your
-   additional sections.  Do not define this macro if you do not define
-   `EXTRA_SECTIONS'.
-
-   Defined in svr4.h.  */
-/* #define EXTRA_SECTION_FUNCTIONS */
-
-/* On most machines, read-only variables, constants, and jump tables are placed
-   in the text section.  If this is not the case on your machine, this macro
-   should be defined to be the name of a function (either `data_section' or a
-   function defined in `EXTRA_SECTIONS') that switches to the section to be
-   used for read-only items.
-
-   If these items should be placed in the text section, this macro should not
-   be defined.  */
-/* #define READONLY_DATA_SECTION */
-
-/* A C statement or statements to switch to the appropriate section for output
-   of EXP.  You can assume that EXP is either a `VAR_DECL' node or a constant
-   of some sort.  RELOC indicates whether the initial value of EXP requires
-   link-time relocations.  Select the section by calling `text_section' or one
-   of the alternatives for other sections.
-
-   Do not define this macro if you put all read-only variables and constants in
-   the read-only data section (usually the text section).
-
-   Defined in svr4.h.  */
-/* #define SELECT_SECTION(EXP, RELOC) */
-
-/* A C statement or statements to switch to the appropriate section for output
-   of RTX in mode MODE.  You can assume that RTX is some kind of constant in
-   RTL.  The argument MODE is redundant except in the case of a `const_int'
-   rtx.  Select the section by calling `text_section' or one of the
-   alternatives for other sections.
-
-   Do not define this macro if you put all constants in the read-only data
-   section.
-
-   Defined in svr4.h.  */
-/* #define SELECT_RTX_SECTION(MODE, RTX) */
-
-/* Define this macro if jump tables (for `tablejump' insns) should be output in
-   the text section, along with the assembler instructions.  Otherwise, the
-   readonly data section is used.
-
-   This macro is irrelevant if there is no separate readonly data section.  */
-/* #define JUMP_TABLES_IN_TEXT_SECTION */
-
-/* Define this macro if references to a symbol must be treated differently
-   depending on something about the variable or function named by the symbol
-   (such as what section it is in).
-
-   The macro definition, if any, is executed immediately after the rtl for DECL
-   has been created and stored in `DECL_RTL (DECL)'.  The value of the rtl will
-   be a `mem' whose address is a `symbol_ref'.
-
-   The usual thing for this macro to do is to record a flag in the `symbol_ref'
-   (such as `SYMBOL_REF_FLAG') or to store a modified name string in the
-   `symbol_ref' (if one bit is not enough information).  */
-/* #define ENCODE_SECTION_INFO(DECL) */
-
-/* Decode SYM_NAME and store the real name part in VAR, sans the characters
-   that encode section info.  Define this macro if `ENCODE_SECTION_INFO' alters
-   the symbol's name string.  */
-/* #define STRIP_NAME_ENCODING(VAR, SYM_NAME) */
-
-/* A C expression which evaluates to true if DECL should be placed
-   into a unique section for some target-specific reason.  If you do
-   not define this macro, the default is `0'.  Note that the flag
-   `-ffunction-sections' will also cause functions to be placed into
-   unique sections.
-
-   Defined in svr4.h.  */
-/* #define UNIQUE_SECTION_P(DECL) */
-
-/* A C statement to build up a unique section name, expressed as a
-   STRING_CST node, and assign it to `DECL_SECTION_NAME (DECL)'.
-   RELOC indicates whether the initial value of EXP requires
-   link-time relocations.  If you do not define this macro, GNU CC
-   will use the symbol name prefixed by `.' as the section name.
-
-   Defined in svr4.h.  */
-/* #define UNIQUE_SECTION(DECL, RELOC) */
-
-/*}}}*/ 
-/*{{{  Position Independent Code.  */ 
-
-/* The register number of the register used to address a table of static data
-   addresses in memory.  In some cases this register is defined by a
-   processor's "application binary interface" (ABI).  When this macro is
-   defined, RTL is generated for this register once, as with the stack pointer
-   and frame pointer registers.  If this macro is not defined, it is up to the
-   machine-dependent files to allocate such a register (if necessary).  */
-/* #define PIC_OFFSET_TABLE_REGNUM */
-
-/* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
-   clobbered by calls.  Do not define this macro if `PPIC_OFFSET_TABLE_REGNUM'
-   is not defined.  */
-/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
-
-/* By generating position-independent code, when two different programs (A and
-   B) share a common library (libC.a), the text of the library can be shared
-   whether or not the library is linked at the same address for both programs.
-   In some of these environments, position-independent code requires not only
-   the use of different addressing modes, but also special code to enable the
-   use of these addressing modes.
-
-   The `FINALIZE_PIC' macro serves as a hook to emit these special codes once
-   the function is being compiled into assembly code, but not before.  (It is
-   not done before, because in the case of compiling an inline function, it
-   would lead to multiple PIC prologues being included in functions which used
-   inline functions and were compiled to assembly language.)  */
-/* #define FINALIZE_PIC */
-
-/* A C expression that is nonzero if X is a legitimate immediate operand on the
-   target machine when generating position independent code.  You can assume
-   that X satisfies `CONSTANT_P', so you need not check this.  You can also
-   assume FLAG_PIC is true, so you need not check it either.  You need not
-   define this macro if all constants (including `SYMBOL_REF') can be immediate
-   operands when generating position independent code.  */
-/* #define LEGITIMATE_PIC_OPERAND_P(X) */
-
-/*}}}*/ 
-/*{{{  The Overall Framework of an Assembler File.  */
-
-/* A C expression which outputs to the stdio stream STREAM some appropriate
-   text to go at the end of an assembler file.
-
-   If this macro is not defined, the default is to output nothing special at
-   the end of the file.  Most systems don't require any definition.
-
-   On systems that use SDB, it is necessary to output certain commands; see
-   `attasm.h'.
-
-   Defined in svr4.h.  */
-/* #define ASM_FILE_END(STREAM) */
-
-/* A C statement to output assembler commands which will identify the object
-   file as having been compiled with GNU CC (or another GNU compiler).
-
-   If you don't define this macro, the string `gcc_compiled.:' is output.  This
-   string is calculated to define a symbol which, on BSD systems, will never be
-   defined for any other reason.  GDB checks for the presence of this symbol
-   when reading the symbol table of an executable.
-
-   On non-BSD systems, you must arrange communication with GDB in some other
-   fashion.  If GDB is not used on your system, you can define this macro with
-   an empty body.
-
-   Defined in svr4.h.  */
-/* #define ASM_IDENTIFY_GCC(FILE) */
-
-/* Like ASM_IDENTIFY_GCC, but used when dbx debugging is selected to emit
-   a stab the debugger uses to identify gcc as the compiler that is emitted
-   after the stabs for the filename, which makes it easier for GDB to parse.
-
-   Defined in svr4.h.  */
-/* #define ASM_IDENTIFY_GCC_AFTER_SOURCE(FILE) */
-
-/* A C string constant describing how to begin a comment in the target
-   assembler language.  The compiler assumes that the comment will end at the
-   end of the line.  */
-#define ASM_COMMENT_START ";"
-
-/* A C string constant for text to be output before each `asm' statement or
-   group of consecutive ones.  Normally this is `"#APP"', which is a comment
-   that has no effect on most assemblers but tells the GNU assembler that it
-   must check the lines that follow for all valid assembler constructs.  */
-#define ASM_APP_ON "#APP\n"
-
-/* A C string constant for text to be output after each `asm' statement or
-   group of consecutive ones.  Normally this is `"#NO_APP"', which tells the
-   GNU assembler to resume making the time-saving assumptions that are valid
-   for ordinary compiler output.  */
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* A C statement to output COFF information or DWARF debugging information
-   which indicates that filename NAME is the current source file to the stdio
-   stream STREAM.
-
-   This macro need not be defined if the standard form of output for the file
-   format in use is appropriate.  */
-/* #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) */
-
-/* A C statement to output DBX or SDB debugging information before code for
-   line number LINE of the current source file to the stdio stream STREAM.
-
-   This macro need not be defined if the standard form of debugging information
-   for the debugger in use is appropriate.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) */
-
-/* A C statement to output something to the assembler file to handle a `#ident'
-   directive containing the text STRING.  If this macro is not defined, nothing
-   is output for a `#ident' directive.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_IDENT(STREAM, STRING) */
-
-/* A C statement to output something to the assembler file to switch to section
-   NAME for object DECL which is either a `FUNCTION_DECL', a `VAR_DECL' or
-   `NULL_TREE'.  Some target formats do not support arbitrary sections.  Do not
-   define this macro in such cases.
-
-   At present this macro is only used to support section attributes.  When this
-   macro is undefined, section attributes are disabled.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_SECTION_NAME(STREAM, DECL, NAME) */
-
-/* A C statement to output any assembler statements which are required to
-   precede any Objective C object definitions or message sending.  The
-   statement is executed only when compiling an Objective C program.  */
-/* #define OBJC_PROLOGUE */
-
-/*}}}*/ 
-/*{{{  Output of Data.  */
-
-/* A C statement to output to the stdio stream STREAM an assembler instruction
-   to assemble a floating-point constant of `TFmode', `DFmode', `SFmode',
-   `TQFmode', `HFmode', or `QFmode', respectively, whose value is VALUE.  VALUE
-   will be a C expression of type `REAL_VALUE_TYPE'.  Macros such as
-   `REAL_VALUE_TO_TARGET_DOUBLE' are useful for writing these definitions.  */
-/* #define ASM_OUTPUT_LONG_DOUBLE(STREAM, VALUE) */
-/* #define ASM_OUTPUT_THREE_QUARTER_FLOAT(STREAM, VALUE) */
-/* #define ASM_OUTPUT_SHORT_FLOAT(STREAM, VALUE) */
-/* #define ASM_OUTPUT_BYTE_FLOAT(STREAM, VALUE) */
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)					\
-do {									\
-  long t;								\
-  char str[30];								\
-  REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);				\
-  REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);			\
-  fprintf (FILE, "\t.word\t0x%lx %s %s\n",				\
-	   t, ASM_COMMENT_START, str);					\
-} while (0)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)					\
-do {									\
-  long t[2];								\
-  char str[30];								\
-  REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);				\
-  REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);			\
-  fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n",		\
-	   t[0], ASM_COMMENT_START, str, t[1]);				\
-} while (0)
-
-     
-/* A C statement to output to the stdio stream STREAM an assembler instruction
-   to assemble an integer of 16, 8, 4, 2 or 1 bytes, respectively, whose value
-   is VALUE.  The argument EXP will be an RTL expression which represents a
-   constant value.  Use `output_addr_const (STREAM, EXP)' to output this value
-   as an assembler expression.
-
-   For sizes larger than `UNITS_PER_WORD', if the action of a macro would be
-   identical to repeatedly calling the macro corresponding to a size of
-   `UNITS_PER_WORD', once for each word, you need not define the macro.  */
-/* #define ASM_OUTPUT_QUADRUPLE_INT(STREAM, EXP) */
-/* #define ASM_OUTPUT_DOUBLE_INT(STREAM, EXP) */
-
-/* This is how to output an assembler line defining a `char' constant.  */
-#define ASM_OUTPUT_CHAR(FILE, VALUE)					\
-do {									\
-  fprintf (FILE, "\t.byte\t");						\
-  output_addr_const (FILE, (VALUE));					\
-  fprintf (FILE, "\n");							\
-} while (0)
-
-/* This is how to output an assembler line defining a `short' constant.  */
-#define ASM_OUTPUT_SHORT(FILE, VALUE)					\
-do {									\
-  fprintf (FILE, "\t.hword\t");						\
-  output_addr_const (FILE, (VALUE));					\
-  fprintf (FILE, "\n");							\
-} while (0)
-
-/* This is how to output an assembler line defining an `int' constant.
-   We also handle symbol output here.  */
-#define ASM_OUTPUT_INT(FILE, VALUE)					\
-do {									\
-  fprintf (FILE, "\t.word\t");						\
-  output_addr_const (FILE, (VALUE));					\
-  fprintf (FILE, "\n");							\
-} while (0)
-
-/* A C statement to output to the stdio stream STREAM an assembler instruction
-   to assemble a single byte containing the number VALUE.  */
-#define ASM_OUTPUT_BYTE(STREAM, VALUE) \
-  fprintf (STREAM, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
-
-/* A C string constant giving the pseudo-op to use for a sequence of
-   single-byte constants.  If this macro is not defined, the default
-   is `"byte"'.
-
-   Defined in svr4.h.  */
-/* #define ASM_BYTE_OP */
-
-/* A C statement to output to the stdio stream STREAM an assembler instruction
-   to assemble a string constant containing the LEN bytes at PTR.  PTR will be
-   a C expression of type `char *' and LEN a C expression of type `int'.
-
-   If the assembler has a `.ascii' pseudo-op as found in the Berkeley Unix
-   assembler, do not define the macro `ASM_OUTPUT_ASCII'.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) */
-
-/* You may define this macro as a C expression.  You should define the
-   expression to have a non-zero value if GNU CC should output the
-   constant pool for a function before the code for the function, or
-   a zero value if GNU CC should output the constant pool after the
-   function.  If you do not define this macro, the usual case, GNU CC
-   will output the constant pool before the function.  */
-/* #define CONSTANT_POOL_BEFORE_FUNCTION */
-
-/* A C statement to output assembler commands to define the start of the
-   constant pool for a function.  FUNNAME is a string giving the name of the
-   function.  Should the return type of the function be required, it can be
-   obtained via FUNDECL.  SIZE is the size, in bytes, of the constant pool that
-   will be written immediately after this call.
-
-   If no constant-pool prefix is required, the usual case, this macro need not
-   be defined.  */
-/* #define ASM_OUTPUT_POOL_PROLOGUE(FILE FUNNAME FUNDECL SIZE) */
-
-/* A C statement (with or without semicolon) to output a constant in the
-   constant pool, if it needs special treatment.  (This macro need not do
-   anything for RTL expressions that can be output normally.)
-
-   The argument FILE is the standard I/O stream to output the assembler code
-   on.  X is the RTL expression for the constant to output, and MODE is the
-   machine mode (in case X is a `const_int').  ALIGN is the required alignment
-   for the value X; you should output an assembler directive to force this much
-   alignment.
-
-   The argument LABELNO is a number to use in an internal label for the address
-   of this pool entry.  The definition of this macro is responsible for
-   outputting the label definition at the proper place.  Here is how to do
-   this:
-
-        ASM_OUTPUT_INTERNAL_LABEL (FILE, "LC", LABELNO);
-
-   When you output a pool entry specially, you should end with a `goto' to the
-   label JUMPTO.  This will prevent the same pool entry from being output a
-   second time in the usual manner.
-
-   You need not define this macro if it would do nothing.  */
-/* #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) */
-
-/* Define this macro as a C expression which is nonzero if the constant EXP, of
-   type `tree', should be output after the code for a function.  The compiler
-   will normally output all constants before the function; you need not define
-   this macro if this is OK.  */
-/* #define CONSTANT_AFTER_FUNCTION_P(EXP) */
-
-/* A C statement to output assembler commands to at the end of the constant
-   pool for a function.  FUNNAME is a string giving the name of the function.
-   Should the return type of the function be required, you can obtain it via
-   FUNDECL.  SIZE is the size, in bytes, of the constant pool that GNU CC wrote
-   immediately before this call.
-
-   If no constant-pool epilogue is required, the usual case, you need not
-   define this macro.  */
-/* #define ASM_OUTPUT_POOL_EPILOGUE (FILE FUNNAME FUNDECL SIZE) */
-
-/* Define this macro as a C expression which is nonzero if C is used as a
-   logical line separator by the assembler.
-
-   If you do not define this macro, the default is that only the character `;'
-   is treated as a logical line separator.  */
-/* #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) */
-
-/* These macros are defined as C string constant, describing the syntax in the
-   assembler for grouping arithmetic expressions.  The following definitions
-   are correct for most assemblers:
-
-        #define ASM_OPEN_PAREN "("
-        #define ASM_CLOSE_PAREN ")"  */
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* These macros are provided by `real.h' for writing the definitions of
-   `ASM_OUTPUT_DOUBLE' and the like: */
-
-/* These translate X, of type `REAL_VALUE_TYPE', to the target's floating point
-   representation, and store its bit pattern in the array of `long int' whose
-   address is L.  The number of elements in the output array is determined by
-   the size of the desired target floating point data type: 32 bits of it go in
-   each `long int' array element.  Each array element holds 32 bits of the
-   result, even if `long int' is wider than 32 bits on the host machine.
-
-   The array element values are designed so that you can print them out using
-   `fprintf' in the order they should appear in the target machine's memory.  */
-/* #define REAL_VALUE_TO_TARGET_SINGLE(X, L) */
-/* #define REAL_VALUE_TO_TARGET_DOUBLE(X, L) */
-/* #define REAL_VALUE_TO_TARGET_LONG_DOUBLE(X, L) */
-
-/* This macro converts X, of type `REAL_VALUE_TYPE', to a decimal number and
-   stores it as a string into STRING.  You must pass, as STRING, the address of
-   a long enough block of space to hold the result.
-
-   The argument FORMAT is a `printf'-specification that serves as a suggestion
-   for how to format the output string.  */
-/* #define REAL_VALUE_TO_DECIMAL(X, FORMAT, STRING) */
-
-/*}}}*/ 
-/*{{{  Output of Uninitialized Variables.  */ 
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM the
-   assembler definition of a common-label named NAME whose size is SIZE bytes.
-   The variable ROUNDED is the size rounded up to whatever alignment the caller
-   wants.
-
-   Use the expression `assemble_name (STREAM, NAME)' to output the name itself;
-   before and after that, output the additional assembler syntax for defining
-   the name, and a newline.
-
-   This macro controls how the assembler definitions of uninitialized global
-   variables are output.  */
-/* #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) */
-
-/* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a separate,
-   explicit argument.  If you define this macro, it is used in place of
-   `ASM_OUTPUT_COMMON', and gives you more flexibility in handling the required
-   alignment of the variable.  The alignment is specified as the number of
-   bits.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_ALIGNED_COMMON(STREAM, NAME, SIZE, ALIGNMENT) */
-
-/* Like ASM_OUTPUT_ALIGNED_COMMON except that it takes an additional argument -
-   the DECL of the variable to be output, if there is one.  This macro can be
-   called with DECL == NULL_TREE.  If you define this macro, it is used in
-   place of both ASM_OUTPUT_COMMON and ASM_OUTPUT_ALIGNED_COMMON, and gives you
-   more flexibility in handling the destination of the variable.  */
-/* #define ASM_OUTPUT_DECL_COMMON (STREAM, DECL, NAME, SIZE, ALIGNMENT) */
-
-/* If defined, it is similar to `ASM_OUTPUT_COMMON', except that it is used
-   when NAME is shared.  If not defined, `ASM_OUTPUT_COMMON' will be used.  */
-/* #define ASM_OUTPUT_SHARED_COMMON(STREAM, NAME, SIZE, ROUNDED) */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM the
-   assembler definition of uninitialized global DECL named NAME whose size is
-   SIZE bytes.  The variable ROUNDED is the size rounded up to whatever
-   alignment the caller wants.
-
-   Try to use function `asm_output_bss' defined in `varasm.c' when defining
-   this macro.  If unable, use the expression `assemble_name (STREAM, NAME)' to
-   output the name itself; before and after that, output the additional
-   assembler syntax for defining the name, and a newline.
-
-   This macro controls how the assembler definitions of uninitialized global
-   variables are output.  This macro exists to properly support languages like
-   `c++' which do not have `common' data.  However, this macro currently is not
-   defined for all targets.  If this macro and `ASM_OUTPUT_ALIGNED_BSS' are not
-   defined then `ASM_OUTPUT_COMMON' or `ASM_OUTPUT_ALIGNED_COMMON' or
-   `ASM_OUTPUT_DECL_COMMON' is used.  */
-/* #define ASM_OUTPUT_BSS(STREAM, DECL, NAME, SIZE, ROUNDED) */
-
-/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a separate,
-   explicit argument.  If you define this macro, it is used in place of
-   `ASM_OUTPUT_BSS', and gives you more flexibility in handling the required
-   alignment of the variable.  The alignment is specified as the number of
-   bits.
-
-   Try to use function `asm_output_aligned_bss' defined in file `varasm.c' when
-   defining this macro.  */
-/* #define ASM_OUTPUT_ALIGNED_BSS(STREAM, DECL, NAME, SIZE, ALIGNMENT) */
-
-/* If defined, it is similar to `ASM_OUTPUT_BSS', except that it is used when
-   NAME is shared.  If not defined, `ASM_OUTPUT_BSS' will be used.  */
-/* #define ASM_OUTPUT_SHARED_BSS(STREAM, DECL, NAME, SIZE, ROUNDED) */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM the
-   assembler definition of a local-common-label named NAME whose size is SIZE
-   bytes.  The variable ROUNDED is the size rounded up to whatever alignment
-   the caller wants.
-
-   Use the expression `assemble_name (STREAM, NAME)' to output the name itself;
-   before and after that, output the additional assembler syntax for defining
-   the name, and a newline.
-
-   This macro controls how the assembler definitions of uninitialized static
-   variables are output.  */
-/* #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) */
-
-/* Like `ASM_OUTPUT_LOCAL' except takes the required alignment as a separate,
-   explicit argument.  If you define this macro, it is used in place of
-   `ASM_OUTPUT_LOCAL', and gives you more flexibility in handling the required
-   alignment of the variable.  The alignment is specified as the number of
-   bits.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGNMENT) */
-
-/* Like `ASM_OUTPUT_ALIGNED_LOCAL' except that it takes an additional
-   parameter - the DECL of variable to be output, if there is one.
-   This macro can be called with DECL == NULL_TREE.  If you define
-   this macro, it is used in place of `ASM_OUTPUT_LOCAL' and
-   `ASM_OUTPUT_ALIGNED_LOCAL', and gives you more flexibility in
-   handling the destination of the variable.  */
-/* #define ASM_OUTPUT_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) */
-
-/* If defined, it is similar to `ASM_OUTPUT_LOCAL', except that it is used when
-   NAME is shared.  If not defined, `ASM_OUTPUT_LOCAL' will be used.  */
-/* #define ASM_OUTPUT_SHARED_LOCAL (STREAM, NAME, SIZE, ROUNDED) */
-
-/*}}}*/ 
-/*{{{  Output and Generation of Labels.  */ 
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM the
-   assembler definition of a label named NAME.  Use the expression
-   `assemble_name (STREAM, NAME)' to output the name itself; before and after
-   that, output the additional assembler syntax for defining the name, and a
-   newline.  */
-#define ASM_OUTPUT_LABEL(STREAM, NAME)					\
-do {									\
-  assemble_name (STREAM, NAME);						\
-  fputs (":\n", STREAM);						\
-} while (0)
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM any text
-   necessary for declaring the name NAME of a function which is being defined.
-   This macro is responsible for outputting the label definition (perhaps using
-   `ASM_OUTPUT_LABEL').  The argument DECL is the `FUNCTION_DECL' tree node
-   representing the function.
-
-   If this macro is not defined, then the function name is defined in the usual
-   manner as a label (by means of `ASM_OUTPUT_LABEL').
-
-   Defined in svr4.h.  */
-/* #define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM any text
-   necessary for declaring the size of a function which is being defined.  The
-   argument NAME is the name of the function.  The argument DECL is the
-   `FUNCTION_DECL' tree node representing the function.
-
-   If this macro is not defined, then the function size is not defined.
-
-   Defined in svr4.h.  */
-/* #define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM any text
-   necessary for declaring the name NAME of an initialized variable which is
-   being defined.  This macro must output the label definition (perhaps using
-   `ASM_OUTPUT_LABEL').  The argument DECL is the `VAR_DECL' tree node
-   representing the variable.
-
-   If this macro is not defined, then the variable name is defined in the usual
-   manner as a label (by means of `ASM_OUTPUT_LABEL').
-
-   Defined in svr4.h.  */
-/* #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) */
-
-/* A C statement (sans semicolon) to finish up declaring a variable name once
-   the compiler has processed its initializer fully and thus has had a chance
-   to determine the size of an array when controlled by an initializer.  This
-   is used on systems where it's necessary to declare something about the size
-   of the object.
-
-   If you don't define this macro, that is equivalent to defining it to do
-   nothing.
-
-   Defined in svr4.h.  */
-/* #define ASM_FINISH_DECLARE_OBJECT(STREAM, DECL, TOPLEVEL, ATEND) */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM some
-   commands that will make the label NAME global; that is, available for
-   reference from other files.  Use the expression `assemble_name (STREAM,
-   NAME)' to output the name itself; before and after that, output the
-   additional assembler syntax for making that name global, and a newline.  */
-#define ASM_GLOBALIZE_LABEL(STREAM,NAME)				\
-do {									\
-  fputs ("\t.globl ", STREAM);						\
-  assemble_name (STREAM, NAME);						\
-  fputs ("\n", STREAM);							\
-} while (0)
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM some
-   commands that will make the label NAME weak; that is, available for
-   reference from other files but only used if no other definition is
-   available.  Use the expression `assemble_name (STREAM, NAME)' to output the
-   name itself; before and after that, output the additional assembler syntax
-   for making that name weak, and a newline.
-
-   If you don't define this macro, GNU CC will not support weak symbols and you
-   should not define the `SUPPORTS_WEAK' macro.
-
-   Defined in svr4.h.  */
-/* #define ASM_WEAKEN_LABEL */
-
-/* A C expression which evaluates to true if the target supports weak symbols.
-
-   If you don't define this macro, `defaults.h' provides a default definition.
-   If `ASM_WEAKEN_LABEL' is defined, the default definition is `1'; otherwise,
-   it is `0'.  Define this macro if you want to control weak symbol support
-   with a compiler flag such as `-melf'.  */
-/* #define SUPPORTS_WEAK */
-
-/* A C statement (sans semicolon) to mark DECL to be emitted as a
-   public symbol such that extra copies in multiple translation units
-   will be discarded by the linker.  Define this macro if your object
-   file format provides support for this concept, such as the `COMDAT'
-   section flags in the Microsoft Windows PE/COFF format, and this
-   support requires changes to DECL, such as putting it in a separate
-   section.
-
-   Defined in svr4.h.  */
-/* #define MAKE_DECL_ONE_ONLY */
-
-/* A C expression which evaluates to true if the target supports one-only
-   semantics.
-
-   If you don't define this macro, `varasm.c' provides a default definition.
-   If `MAKE_DECL_ONE_ONLY' is defined, the default definition is `1';
-   otherwise, it is `0'.  Define this macro if you want to control one-only
-   symbol support with a compiler flag, or if setting the `DECL_ONE_ONLY' flag
-   is enough to mark a declaration to be emitted as one-only.  */
-/* #define SUPPORTS_ONE_ONLY */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM any text
-   necessary for declaring the name of an external symbol named NAME which is
-   referenced in this compilation but not defined.  The value of DECL is the
-   tree node for the declaration.
-
-   This macro need not be defined if it does not need to output anything.  The
-   GNU assembler and most Unix assemblers don't require anything.  */
-/* #define ASM_OUTPUT_EXTERNAL(STREAM, DECL, NAME) */
-
-/* A C statement (sans semicolon) to output on STREAM an assembler pseudo-op to
-   declare a library function name external.  The name of the library function
-   is given by SYMREF, which has type `rtx' and is a `symbol_ref'.
-
-   This macro need not be defined if it does not need to output anything.  The
-   GNU assembler and most Unix assemblers don't require anything.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_EXTERNAL_LIBCALL(STREAM, SYMREF) */
-
-/* A C statement (sans semicolon) to output to the stdio stream STREAM a
-   reference in assembler syntax to a label named NAME.  This should add `_' to
-   the front of the name, if that is customary on your operating system, as it
-   is in most Berkeley Unix systems.  This macro is used in `assemble_name'.  */
-/* #define ASM_OUTPUT_LABELREF(STREAM, NAME) */
-
-/* A C statement to output to the stdio stream STREAM a label whose name is
-   made from the string PREFIX and the number NUM.
-
-   It is absolutely essential that these labels be distinct from the labels
-   used for user-level functions and variables.  Otherwise, certain programs
-   will have name conflicts with internal labels.
-
-   It is desirable to exclude internal labels from the symbol table of the
-   object file.  Most assemblers have a naming convention for labels that
-   should be excluded; on many systems, the letter `L' at the beginning of a
-   label has this effect.  You should find out what convention your system
-   uses, and follow it.
-
-   The usual definition of this macro is as follows:
-
-        fprintf (STREAM, "L%s%d:\n", PREFIX, NUM)
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) */
-
-/* A C expression to assign to OUTVAR (which is a variable of type `char *') a
-   newly allocated string made from the string NAME and the number NUMBER, with
-   some suitable punctuation added.  Use `alloca' to get space for the string.
-
-   The string will be used as an argument to `ASM_OUTPUT_LABELREF' to produce
-   an assembler label for an internal static variable whose name is NAME.
-   Therefore, the string must be such as to result in valid assembler code.
-   The argument NUMBER is different each time this macro is executed; it
-   prevents conflicts between similarly-named internal static variables in
-   different scopes.
-
-   Ideally this string should not be a valid C identifier, to prevent any
-   conflict with the user's own symbols.  Most assemblers allow periods or
-   percent signs in assembler symbols; putting at least one of these between
-   the name and the number will suffice.  */
-#define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER)			\
-do {									\
-  (OUTVAR) = (char *) alloca (strlen ((NAME)) + 12);			\
-  sprintf ((OUTVAR), "%s.%ld", (NAME), (long)(NUMBER));			\
-} while (0)
-
-/* A C statement to output to the stdio stream STREAM assembler code which
-   defines (equates) the symbol NAME to have the value VALUE.
-
-   If SET_ASM_OP is defined, a default definition is provided which is correct
-   for most systems.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) */
-
-/* A C statement to output to the stdio stream STREAM assembler code which
-   defines (equates) the weak symbol NAME to have the value VALUE.
-
-   Define this macro if the target only supports weak aliases; define
-   ASM_OUTPUT_DEF instead if possible.  */
-/* #define ASM_OUTPUT_WEAK_ALIAS (STREAM, NAME, VALUE) */
-
-/* Define this macro to override the default assembler names used for Objective
-   C methods.
-
-   The default name is a unique method number followed by the name of the class
-   (e.g. `_1_Foo').  For methods in categories, the name of the category is
-   also included in the assembler name (e.g.  `_1_Foo_Bar').
-
-   These names are safe on most systems, but make debugging difficult since the
-   method's selector is not present in the name.  Therefore, particular systems
-   define other ways of computing names.
-
-   BUF is an expression of type `char *' which gives you a buffer in which to
-   store the name; its length is as long as CLASS_NAME, CAT_NAME and SEL_NAME
-   put together, plus 50 characters extra.
-
-   The argument IS_INST specifies whether the method is an instance method or a
-   class method; CLASS_NAME is the name of the class; CAT_NAME is the name of
-   the category (or NULL if the method is not in a category); and SEL_NAME is
-   the name of the selector.
-
-   On systems where the assembler can handle quoted names, you can use this
-   macro to provide more human-readable names.  */
-/* #define OBJC_GEN_METHOD_LABEL(BUF, IS_INST, CLASS_NAME, CAT_NAME, SEL_NAME) */
-
-/*}}}*/ 
-/*{{{  Macros Controlling Initialization Routines.  */ 
-
-/* If defined, a C string constant for the assembler operation to identify the
-   following data as initialization code.  If not defined, GNU CC will assume
-   such a section does not exist.  When you are using special sections for
-   initialization and termination functions, this macro also controls how
-   `crtstuff.c' and `libgcc2.c' arrange to run the initialization functions.
-
-   Defined in svr4.h.  */
-/* #define INIT_SECTION_ASM_OP */
-
-/* If defined, `main' will not call `__main' as described above.  This macro
-   should be defined for systems that control the contents of the init section
-   on a symbol-by-symbol basis, such as OSF/1, and should not be defined
-   explicitly for systems that support `INIT_SECTION_ASM_OP'.  */
-/* #define HAS_INIT_SECTION */
-
-/* If defined, a C string constant for a switch that tells the linker that the
-   following symbol is an initialization routine.  */
-/* #define LD_INIT_SWITCH */
-
-/* If defined, a C string constant for a switch that tells the linker that the
-   following symbol is a finalization routine.  */
-/* #define LD_FINI_SWITCH */
-
-/* If defined, `main' will call `__main' despite the presence of
-   `INIT_SECTION_ASM_OP'.  This macro should be defined for systems where the
-   init section is not actually run automatically, but is still useful for
-   collecting the lists of constructors and destructors.  */
-/* #define INVOKE__main */
-
-/* Define this macro as a C statement to output on the stream STREAM the
-   assembler code to arrange to call the function named NAME at initialization
-   time.
-
-   Assume that NAME is the name of a C function generated automatically by the
-   compiler.  This function takes no arguments.  Use the function
-   `assemble_name' to output the name NAME; this performs any system-specific
-   syntactic transformations such as adding an underscore.
-
-   If you don't define this macro, nothing special is output to arrange to call
-   the function.  This is correct when the function will be called in some
-   other manner--for example, by means of the `collect2' program, which looks
-   through the symbol table to find these functions by their names.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_CONSTRUCTOR(STREAM, NAME) */
-
-/* This is like `ASM_OUTPUT_CONSTRUCTOR' but used for termination functions
-   rather than initialization functions.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_DESTRUCTOR(STREAM, NAME) */
-
-/* If your system uses `collect2' as the means of processing constructors, then
-   that program normally uses `nm' to scan an object file for constructor
-   functions to be called.  On certain kinds of systems, you can define these
-   macros to make `collect2' work faster (and, in some cases, make it work at
-   all): */
-
-/* Define this macro if the system uses COFF (Common Object File Format) object
-   files, so that `collect2' can assume this format and scan object files
-   directly for dynamic constructor/destructor functions.  */
-/* #define OBJECT_FORMAT_COFF */
-
-/* Define this macro if the system uses ROSE format object files, so that
-   `collect2' can assume this format and scan object files directly for dynamic
-   constructor/destructor functions.
-
-   These macros are effective only in a native compiler; `collect2' as
-   part of a cross compiler always uses `nm' for the target machine.  */
-/* #define OBJECT_FORMAT_ROSE */
-
-/* Define this macro if the system uses ELF format object files.
-
-   Defined in svr4.h.  */
-/* #define OBJECT_FORMAT_ELF */
-
-/* Define this macro as a C string constant containing the file name to use to
-   execute `nm'.  The default is to search the path normally for `nm'.
-
-   If your system supports shared libraries and has a program to list the
-   dynamic dependencies of a given library or executable, you can define these
-   macros to enable support for running initialization and termination
-   functions in shared libraries: */
-/* #define REAL_NM_FILE_NAME */
-
-/* Define this macro to a C string constant containing the name of the program
-   which lists dynamic dependencies, like `"ldd"' under SunOS 4.  */
-/* #define LDD_SUFFIX */
-
-/* Define this macro to be C code that extracts filenames from the output of
-   the program denoted by `LDD_SUFFIX'.  PTR is a variable of type `char *'
-   that points to the beginning of a line of output from `LDD_SUFFIX'.  If the
-   line lists a dynamic dependency, the code must advance PTR to the beginning
-   of the filename on that line.  Otherwise, it must set PTR to `NULL'.  */
-/* #define PARSE_LDD_OUTPUT (PTR) */
-
-/*}}}*/ 
-/*{{{  Output of Assembler Instructions.  */ 
-
-/* Define this macro if you are using an unusual assembler that requires
-   different names for the machine instructions.
-
-   The definition is a C statement or statements which output an assembler
-   instruction opcode to the stdio stream STREAM.  The macro-operand PTR is a
-   variable of type `char *' which points to the opcode name in its "internal"
-   form--the form that is written in the machine description.  The definition
-   should output the opcode name to STREAM, performing any translation you
-   desire, and increment the variable PTR to point at the end of the opcode so
-   that it will not be output twice.
-
-   In fact, your macro definition may process less than the entire opcode name,
-   or more than the opcode name; but if you want to process text that includes
-   `%'-sequences to substitute operands, you must take care of the substitution
-   yourself.  Just be sure to increment PTR over whatever text should not be
-   output normally.
-
-   If you need to look at the operand values, they can be found as the elements
-   of `recog_operand'.
-
-   If the macro definition does nothing, the instruction is output in the usual
-   way.  */
-/* #define ASM_OUTPUT_OPCODE(STREAM, PTR) */
-
-/* If defined, a C statement to be executed just prior to the output of
-   assembler code for INSN, to modify the extracted operands so they will be
-   output differently.
-
-   Here the argument OPVEC is the vector containing the operands extracted from
-   INSN, and NOPERANDS is the number of elements of the vector which contain
-   meaningful data for this insn.  The contents of this vector are what will be
-   used to convert the insn template into assembler code, so you can change the
-   assembler output by changing the contents of the vector.
-
-   This macro is useful when various assembler syntaxes share a single file of
-   instruction patterns; by defining this macro differently, you can cause a
-   large class of instructions to be output differently (such as with
-   rearranged operands).  Naturally, variations in assembler syntax affecting
-   individual insn patterns ought to be handled by writing conditional output
-   routines in those patterns.
-
-   If this macro is not defined, it is equivalent to a null statement.  */
-/* #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) */
-
-/* If defined, `FINAL_PRESCAN_INSN' will be called on each
-   `CODE_LABEL'.  In that case, OPVEC will be a null pointer and
-   NOPERANDS will be zero.  */
-/* #define FINAL_PRESCAN_LABEL */
-
-/* A C compound statement to output to stdio stream STREAM the assembler syntax
-   for an instruction operand X.  X is an RTL expression.
-
-   CODE is a value that can be used to specify one of several ways of printing
-   the operand.  It is used when identical operands must be printed differently
-   depending on the context.  CODE comes from the `%' specification that was
-   used to request printing of the operand.  If the specification was just
-   `%DIGIT' then CODE is 0; if the specification was `%LTR DIGIT' then CODE is
-   the ASCII code for LTR.
-
-   If X is a register, this macro should print the register's name.  The names
-   can be found in an array `reg_names' whose type is `char *[]'.  `reg_names'
-   is initialized from `REGISTER_NAMES'.
-
-   When the machine description has a specification `%PUNCT' (a `%' followed by
-   a punctuation character), this macro is called with a null pointer for X and
-   the punctuation character for CODE.  */
-#define PRINT_OPERAND(STREAM, X, CODE)	fr30_print_operand (STREAM, X, CODE)
-
-extern void fr30_print_operand STDIO_PROTO((FILE *, Rtx, int));
-
-/* A C expression which evaluates to true if CODE is a valid punctuation
-   character for use in the `PRINT_OPERAND' macro.  If
-   `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no punctuation
-   characters (except for the standard one, `%') are used in this way.  */
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) (CODE == '#')
-
-/* A C compound statement to output to stdio stream STREAM the assembler syntax
-   for an instruction operand that is a memory reference whose address is X.  X
-   is an RTL expression.
-
-   On some machines, the syntax for a symbolic address depends on the section
-   that the address refers to.  On these machines, define the macro
-   `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
-   then check for it here.  *Note Assembler Format::.  */
-#define PRINT_OPERAND_ADDRESS(STREAM, X) fr30_print_operand_address (STREAM, X)
-extern void fr30_print_operand_address STDIO_PROTO((FILE *, Rtx));
-
-/* A C statement, to be executed after all slot-filler instructions have been
-   output.  If necessary, call `dbr_sequence_length' to determine the number of
-   slots filled in a sequence (zero if not currently outputting a sequence), to
-   decide how many no-ops to output, or whatever.
-
-   Don't define this macro if it has nothing to do, but it is helpful in
-   reading assembly output if the extent of the delay sequence is made explicit
-   (e.g. with white space).
-
-   Note that output routines for instructions with delay slots must be prepared
-   to deal with not being output as part of a sequence (i.e.  when the
-   scheduling pass is not run, or when no slot fillers could be found.)  The
-   variable `final_sequence' is null when not processing a sequence, otherwise
-   it contains the `sequence' rtx being output.  */
-/* #define DBR_OUTPUT_SEQEND(FILE) */
-
-/* If defined, C string expressions to be used for the `%R', `%L', `%U', and
-   `%I' options of `asm_fprintf' (see `final.c').  These are useful when a
-   single `md' file must support multiple assembler formats.  In that case, the
-   various `tm.h' files can define these macros differently.
-
-   USER_LABEL_PREFIX is defined in svr4.h.  */
-#define REGISTER_PREFIX "%"
-#define LOCAL_LABEL_PREFIX "."
-#define USER_LABEL_PREFIX ""
-#define IMMEDIATE_PREFIX ""
-
-/* If your target supports multiple dialects of assembler language (such as
-   different opcodes), define this macro as a C expression that gives the
-   numeric index of the assembler language dialect to use, with zero as the
-   first variant.
-
-   If this macro is defined, you may use `{option0|option1|option2...}'
-   constructs in the output templates of patterns or
-   in the first argument of `asm_fprintf'.  This construct outputs `option0',
-   `option1' or `option2', etc., if the value of `ASSEMBLER_DIALECT' is zero,
-   one or two, etc.  Any special characters within these strings retain their
-   usual meaning.
-
-   If you do not define this macro, the characters `{', `|' and `}' do not have
-   any special meaning when used in templates or operands to `asm_fprintf'.
-
-   Define the macros `REGISTER_PREFIX', `LOCAL_LABEL_PREFIX',
-   `USER_LABEL_PREFIX' and `IMMEDIATE_PREFIX' if you can express the variations
-   in assemble language syntax with that mechanism.  Define `ASSEMBLER_DIALECT'
-   and use the `{option0|option1}' syntax if the syntax variant are larger and
-   involve such things as different opcodes or operand order.  */
-/* #define ASSEMBLER_DIALECT */
-
-/* A C expression to output to STREAM some assembler code which will push hard
-   register number REGNO onto the stack.  The code need not be optimal, since
-   this macro is used only when profiling.  */
-/* #define ASM_OUTPUT_REG_PUSH (STREAM, REGNO) */
-
-/* A C expression to output to STREAM some assembler code which will pop hard
-   register number REGNO off of the stack.  The code need not be optimal, since
-   this macro is used only when profiling.  */
-/* #define ASM_OUTPUT_REG_POP (STREAM, REGNO) */
-
-/*}}}*/ 
-/*{{{  Output of dispatch tables.  */ 
-
-/* This macro should be provided on machines where the addresses in a dispatch
-   table are relative to the table's own address.
-
-   The definition should be a C statement to output to the stdio stream STREAM
-   an assembler pseudo-instruction to generate a difference between two labels.
-   VALUE and REL are the numbers of two internal labels.  The definitions of
-   these labels are output using `ASM_OUTPUT_INTERNAL_LABEL', and they must be
-   printed in the same way here.  For example,
-
-        fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL)  */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
-fprintf (STREAM, "\t.word .L%d-.L%d\n", VALUE, REL)
-
-/* This macro should be provided on machines where the addresses in a dispatch
-   table are absolute.
-
-   The definition should be a C statement to output to the stdio stream STREAM
-   an assembler pseudo-instruction to generate a reference to a label.  VALUE
-   is the number of an internal label whose definition is output using
-   `ASM_OUTPUT_INTERNAL_LABEL'.  For example,
-
-        fprintf (STREAM, "\t.word L%d\n", VALUE)  */
-#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
-fprintf (STREAM, "\t.word .L%d\n", VALUE)
-
-/* Define this if the label before a jump-table needs to be output specially.
-   The first three arguments are the same as for `ASM_OUTPUT_INTERNAL_LABEL';
-   the fourth argument is the jump-table which follows (a `jump_insn'
-   containing an `addr_vec' or `addr_diff_vec').
-
-   This feature is used on system V to output a `swbeg' statement for the
-   table.
-
-   If this macro is not defined, these labels are output with
-   `ASM_OUTPUT_INTERNAL_LABEL'.
-
-   Defined in svr4.h.  */
-/* #define ASM_OUTPUT_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) */
-
-/* Define this if something special must be output at the end of a jump-table.
-   The definition should be a C statement to be executed after the assembler
-   code for the table is written.  It should write the appropriate code to
-   stdio stream STREAM.  The argument TABLE is the jump-table insn, and NUM is
-   the label-number of the preceding label.
-
-   If this macro is not defined, nothing special is output at the end of the
-   jump-table.  */
-/* #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) */
-
-/*}}}*/ 
-/*{{{  Assembler Commands for Exception Regions.  */ 
-
-/* A C expression to output text to mark the start of an exception region.
-
-   This macro need not be defined on most platforms.  */
-/* #define ASM_OUTPUT_EH_REGION_BEG() */
-
-/* A C expression to output text to mark the end of an exception region.
-
-   This macro need not be defined on most platforms.  */
-/* #define ASM_OUTPUT_EH_REGION_END() */
-
-/* A C expression to switch to the section in which the main exception table is
-   to be placed.  The default is a section named
-   `.gcc_except_table' on machines that support named sections via
-   `ASM_OUTPUT_SECTION_NAME', otherwise if `-fpic' or `-fPIC' is in effect, the
-   `data_section', otherwise the `readonly_data_section'.  */
-/* #define EXCEPTION_SECTION() */
-
-/* If defined, a C string constant for the assembler operation to switch to the
-   section for exception handling frame unwind information.  If not defined,
-   GNU CC will provide a default definition if the target supports named
-   sections.  `crtstuff.c' uses this macro to switch to the appropriate
-   section.
-
-   You should define this symbol if your target supports DWARF 2 frame unwind
-   information and the default definition does not work.  */
-/* #define EH_FRAME_SECTION_ASM_OP */
-
-/* A C expression that is nonzero if the normal exception table output should
-   be omitted.
-
-   This macro need not be defined on most platforms.  */
-/* #define OMIT_EH_TABLE() */
-
-/* Alternate runtime support for looking up an exception at runtime and finding
-   the associated handler, if the default method won't work.
-
-   This macro need not be defined on most platforms.  */
-/* #define EH_TABLE_LOOKUP() */
-
-/* A C expression that decides whether or not the current function needs to
-   have a function unwinder generated for it.  See the file `except.c' for
-   details on when to define this, and how.  */
-/* #define DOESNT_NEED_UNWINDER */
-
-/* An rtx used to mask the return address found via RETURN_ADDR_RTX, so that it
-   does not contain any extraneous set bits in it.  */
-/* #define MASK_RETURN_ADDR */
-
-/* Define this macro to 0 if your target supports DWARF 2 frame unwind
-   information, but it does not yet work with exception handling.  Otherwise,
-   if your target supports this information (if it defines
-   `INCOMING_RETURN_ADDR_RTX' and either `UNALIGNED_INT_ASM_OP' or
-   `OBJECT_FORMAT_ELF'), GCC will provide a default definition of 1.
-
-   If this macro is defined to 1, the DWARF 2 unwinder will be the default
-   exception handling mechanism; otherwise, setjmp/longjmp will be used by
-   default.
-
-   If this macro is defined to anything, the DWARF 2 unwinder will be used
-   instead of inline unwinders and __unwind_function in the non-setjmp case.  */
-/* #define DWARF2_UNWIND_INFO */
-
-/*}}}*/ 
-/*{{{  Assembler Commands for Alignment.  */ 
-
-/* The alignment (log base 2) to put in front of LABEL, which follows
-   a BARRIER.
-
-   This macro need not be defined if you don't want any special alignment to be
-   done at such a time.  Most machine descriptions do not currently define the
-   macro.  */
-/* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
-
-/* The desired alignment for the location counter at the beginning
-   of a loop.
-
-   This macro need not be defined if you don't want any special alignment to be
-   done at such a time.  Most machine descriptions do not currently define the
-   macro.  */
-/* #define LOOP_ALIGN(LABEL) */
-
-/* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
-   section because it fails put zeros in the bytes that are skipped.  This is
-   true on many Unix systems, where the pseudo-op to skip bytes produces no-op
-   instructions rather than zeros when used in the text section.  */
-/* #define ASM_NO_SKIP_IN_TEXT */
-
-/* A C statement to output to the stdio stream STREAM an assembler command to
-   advance the location counter to a multiple of 2 to the POWER bytes.  POWER
-   will be a C expression of type `int'.  */
-#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
-  fprintf ((STREAM), "\t.p2align %d\n", (POWER))
-
-/*}}}*/ 
-/*{{{  Macros Affecting all Debug Formats.  */ 
-
-/* A C expression that returns the DBX register number for the compiler
-   register number REGNO.  In simple cases, the value of this expression may be
-   REGNO itself.  But sometimes there are some registers that the compiler
-   knows about and DBX does not, or vice versa.  In such cases, some register
-   may need to have one number in the compiler and another for DBX.
-
-   If two registers have consecutive numbers inside GNU CC, and they can be
-   used as a pair to hold a multiword value, then they *must* have consecutive
-   numbers after renumbering with `DBX_REGISTER_NUMBER'.  Otherwise, debuggers
-   will be unable to access such a pair, because they expect register pairs to
-   be consecutive in their own numbering scheme.
-
-   If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not
-   preserve register pairs, then what you must do instead is redefine the
-   actual register numbering scheme.  */
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* A C expression that returns the integer offset value for an automatic
-   variable having address X (an RTL expression).  The default computation
-   assumes that X is based on the frame-pointer and gives the offset from the
-   frame-pointer.  This is required for targets that produce debugging output
-   for DBX or COFF-style debugging output for SDB and allow the frame-pointer
-   to be eliminated when the `-g' options is used.  */
-/* #define DEBUGGER_AUTO_OFFSET(X) */
-
-/* A C expression that returns the integer offset value for an argument having
-   address X (an RTL expression).  The nominal offset is OFFSET.  */
-/* #define DEBUGGER_ARG_OFFSET(OFFSET, X) */
-     
-/* A C expression that returns the type of debugging output GNU CC produces
-   when the user specifies `-g' or `-ggdb'.  Define this if you have arranged
-   for GNU CC to support more than one format of debugging output.  Currently,
-   the allowable values are `DBX_DEBUG', `SDB_DEBUG', `DWARF_DEBUG',
-   `DWARF2_DEBUG', and `XCOFF_DEBUG'.
-
-   The value of this macro only affects the default debugging output; the user
-   can always get a specific type of output by using `-gstabs', `-gcoff',
-   `-gdwarf-1', `-gdwarf-2', or `-gxcoff'.
-
-   Defined in svr4.h.  */
-#undef  PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-/*}}}*/ 
-/*{{{  Macros for SDB and Dwarf Output.  */ 
-
-/* Define this macro if GNU CC should produce dwarf format debugging output in
-   response to the `-g' option.
-
-   Defined in svr4.h.  */
-#define DWARF_DEBUGGING_INFO
-
-/* Define this macro if GNU CC should produce dwarf version 2 format debugging
-   output in response to the `-g' option.
-
-   To support optional call frame debugging information, you must also define
-   `INCOMING_RETURN_ADDR_RTX' and either set `RTX_FRAME_RELATED_P' on the
-   prologue insns if you use RTL for the prologue, or call `dwarf2out_def_cfa'
-   and `dwarf2out_reg_save' as appropriate from `FUNCTION_PROLOGUE' if you
-   don't.
-
-   Defined in svr4.h.  */
-#define DWARF2_DEBUGGING_INFO
-
-/* Define these macros to override the assembler syntax for the special SDB
-   assembler directives.  See `sdbout.c' for a list of these macros and their
-   arguments.  If the standard syntax is used, you need not define them
-   yourself.  */
-/* #define PUT_SDB_... */
-
-/* Some assemblers do not support a semicolon as a delimiter, even between SDB
-   assembler directives.  In that case, define this macro to be the delimiter
-   to use (usually `\n').  It is not necessary to define a new set of
-   `PUT_SDB_OP' macros if this is the only change required.  */
-/* #define SDB_DELIM */
-
-/* Define this macro to override the usual method of constructing a dummy name
-   for anonymous structure and union types.  See `sdbout.c' for more
-   information.  */
-/* #define SDB_GENERATE_FAKE */
-
-/* Define this macro to allow references to unknown structure, union, or
-   enumeration tags to be emitted.  Standard COFF does not allow handling of
-   unknown references, MIPS ECOFF has support for it.  */
-/* #define SDB_ALLOW_UNKNOWN_REFERENCES */
-
-/* Define this macro to allow references to structure, union, or enumeration
-   tags that have not yet been seen to be handled.  Some assemblers choke if
-   forward tags are used, while some require it.  */
-/* #define SDB_ALLOW_FORWARD_REFERENCES */
-
-#define DWARF_LINE_MIN_INSTR_LENGTH 2
-     
-/*}}}*/ 
-/*{{{  Cross Compilation and Floating Point.  */ 
-
-/* While all modern machines use 2's complement representation for integers,
-   there are a variety of representations for floating point numbers.  This
-   means that in a cross-compiler the representation of floating point numbers
-   in the compiled program may be different from that used in the machine doing
-   the compilation.
-
-   Because different representation systems may offer different amounts of
-   range and precision, the cross compiler cannot safely use the host machine's
-   floating point arithmetic.  Therefore, floating point constants must be
-   represented in the target machine's format.  This means that the cross
-   compiler cannot use `atof' to parse a floating point constant; it must have
-   its own special routine to use instead.  Also, constant folding must emulate
-   the target machine's arithmetic (or must not be done at all).
-
-   The macros in the following table should be defined only if you are cross
-   compiling between different floating point formats.
-
-   Otherwise, don't define them.  Then default definitions will be set up which
-   use `double' as the data type, `==' to test for equality, etc.
-
-   You don't need to worry about how many times you use an operand of any of
-   these macros.  The compiler never uses operands which have side effects.  */
-
-/* A macro for the C data type to be used to hold a floating point value in the
-   target machine's format.  Typically this would be a `struct' containing an
-   array of `int'.  */
-/* #define REAL_VALUE_TYPE */
-
-/* A macro for a C expression which compares for equality the two values, X and
-   Y, both of type `REAL_VALUE_TYPE'.  */
-/* #define REAL_VALUES_EQUAL(X, Y) */
-
-/* A macro for a C expression which tests whether X is less than Y, both values
-   being of type `REAL_VALUE_TYPE' and interpreted as floating point numbers in
-   the target machine's representation.  */
-/* #define REAL_VALUES_LESS(X, Y) */
-
-/* A macro for a C expression which performs the standard library function
-   `ldexp', but using the target machine's floating point representation.  Both
-   X and the value of the expression have type `REAL_VALUE_TYPE'.  The second
-   argument, SCALE, is an integer.  */
-/* #define REAL_VALUE_LDEXP(X, SCALE) */
-
-/* A macro whose definition is a C expression to convert the target-machine
-   floating point value X to a signed integer.  X has type `REAL_VALUE_TYPE'.  */
-/* #define REAL_VALUE_FIX(X) */
-
-/* A macro whose definition is a C expression to convert the target-machine
-   floating point value X to an unsigned integer.  X has type
-   `REAL_VALUE_TYPE'.  */
-/* #define REAL_VALUE_UNSIGNED_FIX(X) */
-
-/* A macro whose definition is a C expression to round the target-machine
-   floating point value X towards zero to an integer value (but still as a
-   floating point number).  X has type `REAL_VALUE_TYPE', and so does the
-   value.  */
-/* #define REAL_VALUE_RNDZINT(X) */
-
-/* A macro whose definition is a C expression to round the target-machine
-   floating point value X towards zero to an unsigned integer value (but still
-   represented as a floating point number).  X has type `REAL_VALUE_TYPE', and
-   so does the value.  */
-/* #define REAL_VALUE_UNSIGNED_RNDZINT(X) */
-
-/* A macro for a C expression which converts STRING, an expression of type
-   `char *', into a floating point number in the target machine's
-   representation for mode MODE.  The value has type `REAL_VALUE_TYPE'.  */
-/* #define REAL_VALUE_ATOF(STRING, MODE) */
-
-/* Define this macro if infinity is a possible floating point value, and
-   therefore division by 0 is legitimate.  */
-/* #define REAL_INFINITY */
-
-/* A macro for a C expression which determines whether X, a floating point
-   value, is infinity.  The value has type `int'.  By default, this is defined
-   to call `isinf'.  */
-/* #define REAL_VALUE_ISINF(X) */
-
-/* A macro for a C expression which determines whether X, a floating point
-   value, is a "nan" (not-a-number).  The value has type `int'.  By default,
-   this is defined to call `isnan'.  */
-/* #define REAL_VALUE_ISNAN(X) */
-
-/* Define the following additional macros if you want to make floating point
-   constant folding work while cross compiling.  If you don't define them,
-   cross compilation is still possible, but constant folding will not happen
-   for floating point values.  */
-
-/* A macro for a C statement which calculates an arithmetic operation of the
-   two floating point values X and Y, both of type `REAL_VALUE_TYPE' in the
-   target machine's representation, to produce a result of the same type and
-   representation which is stored in OUTPUT (which will be a variable).
-
-   The operation to be performed is specified by CODE, a tree code which will
-   always be one of the following: `PLUS_EXPR', `MINUS_EXPR', `MULT_EXPR',
-   `RDIV_EXPR', `MAX_EXPR', `MIN_EXPR'.
-
-   The expansion of this macro is responsible for checking for overflow.  If
-   overflow happens, the macro expansion should execute the statement `return
-   0;', which indicates the inability to perform the arithmetic operation
-   requested.  */
-/* #define REAL_ARITHMETIC(OUTPUT, CODE, X, Y) */
-
-/* A macro for a C expression which returns the negative of the floating point
-   value X.  Both X and the value of the expression have type `REAL_VALUE_TYPE'
-   and are in the target machine's floating point representation.
-
-   There is no way for this macro to report overflow, since overflow can't
-   happen in the negation operation.  */
-/* #define REAL_VALUE_NEGATE(X) */
-
-/* A macro for a C expression which converts the floating point value X to mode
-   MODE.
-
-   Both X and the value of the expression are in the target machine's floating
-   point representation and have type `REAL_VALUE_TYPE'.  However, the value
-   should have an appropriate bit pattern to be output properly as a floating
-   constant whose precision accords with mode MODE.
-
-   There is no way for this macro to report overflow.  */
-/* #define REAL_VALUE_TRUNCATE(MODE, X) */
-
-/* A macro for a C expression which converts a floating point value X into a
-   double-precision integer which is then stored into LOW and HIGH, two
-   variables of type INT.  */
-/* #define REAL_VALUE_TO_INT(LOW, HIGH, X) */
-
-/* A macro for a C expression which converts a double-precision integer found
-   in LOW and HIGH, two variables of type INT, into a floating point value
-   which is then stored into X.  */
-/* #define REAL_VALUE_FROM_INT(X, LOW, HIGH) */
-
-/*}}}*/ 
-/*{{{  Miscellaneous Parameters.  */ 
-
-/* An alias for a machine mode name.  This is the machine mode that elements of
-   a jump-table should have.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define this if control falls through a `case' insn when the index value is
-   out of range.  This means the specified default-label is actually ignored by
-   the `case' insn proper.  */
-/* #define CASE_DROPS_THROUGH */
-
-/* Define this to be the smallest number of different values for which it is
-   best to use a jump-table instead of a tree of conditional branches.  The
-   default is four for machines with a `casesi' instruction and five otherwise.
-   This is best for most machines.  */
-/* #define CASE_VALUES_THRESHOLD */
-
-/* Define this macro if operations between registers with integral mode smaller
-   than a word are always performed on the entire register.  Most RISC machines
-   have this property and most CISC machines do not.  */
-/* #define WORD_REGISTER_OPERATIONS */
-
-/* Define this macro to be a C expression indicating when insns that read
-   memory in MODE, an integral mode narrower than a word, set the bits outside
-   of MODE to be either the sign-extension or the zero-extension of the data
-   read.  Return `SIGN_EXTEND' for values of MODE for which the insn
-   sign-extends, `ZERO_EXTEND' for which it zero-extends, and `NIL' for other
-   modes.
-
-   This macro is not called with MODE non-integral or with a width greater than
-   or equal to `BITS_PER_WORD', so you may return any value in this case.  Do
-   not define this macro if it would always return `NIL'.  On machines where
-   this macro is defined, you will normally define it as the constant
-   `SIGN_EXTEND' or `ZERO_EXTEND'.  */
-/* #define LOAD_EXTEND_OP (MODE) */
-
-/* Define if loading short immediate values into registers sign extends.  */
-/* #define SHORT_IMMEDIATES_SIGN_EXTEND */
-
-/* An alias for a tree code that should be used by default for conversion of
-   floating point values to fixed point.  Normally, `FIX_ROUND_EXPR' is used.  */
-/* #define IMPLICIT_FIX_EXPR */
-
-/* Define this macro if the same instructions that convert a floating point
-   number to a signed fixed point number also convert validly to an unsigned
-   one.  */
-/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
-
-/* An alias for a tree code that is the easiest kind of division to compile
-   code for in the general case.  It may be `TRUNC_DIV_EXPR', `FLOOR_DIV_EXPR',
-   `CEIL_DIV_EXPR' or `ROUND_DIV_EXPR'.  These four division operators differ
-   in how they round the result to an integer.  `EASY_DIV_EXPR' is used when it
-   is permissible to use any of those kinds of division and the choice should
-   be made on the basis of efficiency.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* The maximum number of bytes that a single instruction can move quickly from
-   memory to memory.  */
-#define MOVE_MAX 8
-
-/* The maximum number of bytes that a single instruction can move quickly from
-   memory to memory.  If this is undefined, the default is `MOVE_MAX'.
-   Otherwise, it is the constant value that is the largest value that
-   `MOVE_MAX' can have at run-time.  */
-/* #define MAX_MOVE_MAX */
-
-/* A C expression that is nonzero if on this machine the number of bits
-   actually used for the count of a shift operation is equal to the number of
-   bits needed to represent the size of the object being shifted.  When this
-   macro is non-zero, the compiler will assume that it is safe to omit a
-   sign-extend, zero-extend, and certain bitwise `and' instructions that
-   truncates the count of a shift operation.  On machines that have
-   instructions that act on bitfields at variable positions, which may include
-   `bit test' instructions, a nonzero `SHIFT_COUNT_TRUNCATED' also enables
-   deletion of truncations of the values that serve as arguments to bitfield
-   instructions.
-
-   If both types of instructions truncate the count (for shifts) and position
-   (for bitfield operations), or if no variable-position bitfield instructions
-   exist, you should define this macro.
-
-   However, on some machines, such as the 80386 and the 680x0, truncation only
-   applies to shift operations and not the (real or pretended) bitfield
-   operations.  Define `SHIFT_COUNT_TRUNCATED' to be zero on such machines.
-   Instead, add patterns to the `md' file that include the implied truncation
-   of the shift instructions.
-
-   You need not define this macro if it would always have the value of zero.  */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* A C expression which is nonzero if on this machine it is safe to "convert"
-   an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
-   than INPREC) by merely operating on it as if it had only OUTPREC bits.
-
-   On many machines, this expression can be 1.
-
-   When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for
-   which `MODES_TIEABLE_P' is 0, suboptimal code can result.  If this is the
-   case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve
-   things.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* A C expression describing the value returned by a comparison operator with
-   an integral mode and stored by a store-flag instruction (`sCOND') when the
-   condition is true.  This description must apply to *all* the `sCOND'
-   patterns and all the comparison operators whose results have a `MODE_INT'
-   mode.
-
-   A value of 1 or -1 means that the instruction implementing the comparison
-   operator returns exactly 1 or -1 when the comparison is true and 0 when the
-   comparison is false.  Otherwise, the value indicates which bits of the
-   result are guaranteed to be 1 when the comparison is true.  This value is
-   interpreted in the mode of the comparison operation, which is given by the
-   mode of the first operand in the `sCOND' pattern.  Either the low bit or the
-   sign bit of `STORE_FLAG_VALUE' be on.  Presently, only those bits are used
-   by the compiler.
-
-   If `STORE_FLAG_VALUE' is neither 1 or -1, the compiler will generate code
-   that depends only on the specified bits.  It can also replace comparison
-   operators with equivalent operations if they cause the required bits to be
-   set, even if the remaining bits are undefined.  For example, on a machine
-   whose comparison operators return an `SImode' value and where
-   `STORE_FLAG_VALUE' is defined as `0x80000000', saying that just the sign bit
-   is relevant, the expression
-
-        (ne:SI (and:SI X (const_int POWER-OF-2)) (const_int 0))
-
-   can be converted to
-
-        (ashift:SI X (const_int N))
-
-   where N is the appropriate shift count to move the bit being tested into the
-   sign bit.
-
-   There is no way to describe a machine that always sets the low-order bit for
-   a true value, but does not guarantee the value of any other bits, but we do
-   not know of any machine that has such an instruction.  If you are trying to
-   port GNU CC to such a machine, include an instruction to perform a
-   logical-and of the result with 1 in the pattern for the comparison operators
-   and let us know.
-
-   Often, a machine will have multiple instructions that obtain a value from a
-   comparison (or the condition codes).  Here are rules to guide the choice of
-   value for `STORE_FLAG_VALUE', and hence the instructions to be used:
-
-      * Use the shortest sequence that yields a valid definition for
-        `STORE_FLAG_VALUE'.  It is more efficient for the compiler to
-        "normalize" the value (convert it to, e.g., 1 or 0) than for
-        the comparison operators to do so because there may be
-        opportunities to combine the normalization with other
-        operations.
-
-      * For equal-length sequences, use a value of 1 or -1, with -1
-        being slightly preferred on machines with expensive jumps and
-        1 preferred on other machines.
-
-      * As a second choice, choose a value of `0x80000001' if
-        instructions exist that set both the sign and low-order bits
-        but do not define the others.
-
-      * Otherwise, use a value of `0x80000000'.
-
-   Many machines can produce both the value chosen for `STORE_FLAG_VALUE' and
-   its negation in the same number of instructions.  On those machines, you
-   should also define a pattern for those cases, e.g., one matching
-
-        (set A (neg:M (ne:M B C)))
-
-   Some machines can also perform `and' or `plus' operations on condition code
-   values with less instructions than the corresponding `sCOND' insn followed
-   by `and' or `plus'.  On those machines, define the appropriate patterns.
-   Use the names `incscc' and `decscc', respectively, for the the patterns
-   which perform `plus' or `minus' operations on condition code values.  See
-   `rs6000.md' for some examples.  The GNU Superoptizer can be used to find
-   such instruction sequences on other machines.
-
-   You need not define `STORE_FLAG_VALUE' if the machine has no store-flag
-   instructions.  */
-/* #define STORE_FLAG_VALUE */
-
-/* A C expression that gives a non-zero floating point value that is returned
-   when comparison operators with floating-point results are true.  Define this
-   macro on machine that have comparison operations that return floating-point
-   values.  If there are no such operations, do not define this macro.  */
-/* #define FLOAT_STORE_FLAG_VALUE */
-
-/* An alias for the machine mode for pointers.  On most machines, define this
-   to be the integer mode corresponding to the width of a hardware pointer;
-   `SImode' on 32-bit machine or `DImode' on 64-bit machines.  On some machines
-   you must define this to be one of the partial integer modes, such as
-   `PSImode'.
-
-   The width of `Pmode' must be at least as large as the value of
-   `POINTER_SIZE'.  If it is not equal, you must define the macro
-   `POINTERS_EXTEND_UNSIGNED' to specify how pointers are extended to `Pmode'.  */
-#define Pmode SImode
-
-/* An alias for the machine mode used for memory references to functions being
-   called, in `call' RTL expressions.  On most machines this should be
-   `QImode'.  */
-#define FUNCTION_MODE QImode
-
-/* A C expression for the maximum number of instructions above which the
-   function DECL should not be inlined.  DECL is a `FUNCTION_DECL' node.
-
-   The default definition of this macro is 64 plus 8 times the number of
-   arguments that the function accepts.  Some people think a larger threshold
-   should be used on RISC machines.  */
-/* #define INTEGRATE_THRESHOLD(DECL) */
-
-/* Define this if the preprocessor should ignore `#sccs' directives and print
-   no error message.
-
-   Defined in svr4.h.  */
-/* #define SCCS_DIRECTIVE */
-
-/* Define this macro if the system header files support C++ as well as C.  This
-   macro inhibits the usual method of using system header files in C++, which
-   is to pretend that the file's contents are enclosed in `extern "C" {...}'.  */
-/* #define NO_IMPLICIT_EXTERN_C */
-
-/* Define this macro if you want to implement any pragmas.  If defined, it
-   should be a C expression to be executed when #pragma is seen.  The
-   argument GETC is a function which will return the next character in the
-   input stream, or EOF if no characters are left.  The argument UNGETC is
-   a function which will push a character back into the input stream.  The
-   argument NAME is the word following #pragma in the input stream.  The input
-   stream pointer will be pointing just beyond the end of this word.  The
-   expression should return true if it handled the pragma, false otherwise.
-   The input stream should be left undistrubed if false is returned, otherwise
-   it should be pointing at the next character after the end of the pragma.
-   Any characters left between the end of the pragma and the end of the line will
-   be ignored.
-   
-   It is generally a bad idea to implement new uses of `#pragma'.  The only
-   reason to define this macro is for compatibility with other compilers that
-   do support `#pragma' for the sake of any user programs which already use it.  */
-/* #define HANDLE_PRAGMA(GETC, UNGETC, NAME) handle_pragma (GETC, UNGETC, NAME) */
-
-/* Define this macro to handle System V style pragmas: #pragma pack and
-   #pragma weak.  Note, #pragma weak will only be supported if SUPPORT_WEAK is
-   defined.
-
-   Defined in svr4.h.  */
-#define HANDLE_SYSV_PRAGMA
-
-/* Define this macro to control use of the character `$' in identifier names.
-   The value should be 0, 1, or 2.  0 means `$' is not allowed by default; 1
-   means it is allowed by default if `-traditional' is used; 2 means it is
-   allowed by default provided `-ansi' is not used.  1 is the default; there is
-   no need to define this macro in that case.  */
-/* #define DOLLARS_IN_IDENTIFIERS */
-
-/* Define this macro if the assembler does not accept the character `$' in
-   label names.  By default constructors and destructors in G++ have `$' in the
-   identifiers.  If this macro is defined, `.' is used instead.
-
-   Defined in svr4.h.  */
-/* #define NO_DOLLAR_IN_LABEL */
-
-/* Define this macro if the assembler does not accept the character `.' in
-   label names.  By default constructors and destructors in G++ have names that
-   use `.'.  If this macro is defined, these names are rewritten to avoid `.'.  */
-/* #define NO_DOT_IN_LABEL */
-
-/* Define this macro if the target system expects every program's `main'
-   function to return a standard "success" value by default (if no other value
-   is explicitly returned).
-
-   The definition should be a C statement (sans semicolon) to generate the
-   appropriate rtl instructions.  It is used only when compiling the end of
-   `main'.  */
-/* #define DEFAULT_MAIN_RETURN */
-
-/* Define this if the target system supports the function `atexit' from the
-   ANSI C standard.  If this is not defined, and `INIT_SECTION_ASM_OP' is not
-   defined, a default `exit' function will be provided to support C++.
-
-   Defined by svr4.h */
-/* #define HAVE_ATEXIT */
-
-/* Define this if your `exit' function needs to do something besides calling an
-   external function `_cleanup' before terminating with `_exit'.  The
-   `EXIT_BODY' macro is only needed if netiher `HAVE_ATEXIT' nor
-   `INIT_SECTION_ASM_OP' are defined.  */
-/* #define EXIT_BODY */
-
-/* Define this macro as a C expression that is nonzero if it is safe for the
-   delay slot scheduler to place instructions in the delay slot of INSN, even
-   if they appear to use a resource set or clobbered in INSN.  INSN is always a
-   `jump_insn' or an `insn'; GNU CC knows that every `call_insn' has this
-   behavior.  On machines where some `insn' or `jump_insn' is really a function
-   call and hence has this behavior, you should define this macro.
-
-   You need not define this macro if it would always return zero.  */
-/* #define INSN_SETS_ARE_DELAYED(INSN) */
-
-/* Define this macro as a C expression that is nonzero if it is safe for the
-   delay slot scheduler to place instructions in the delay slot of INSN, even
-   if they appear to set or clobber a resource referenced in INSN.  INSN is
-   always a `jump_insn' or an `insn'.  On machines where some `insn' or
-   `jump_insn' is really a function call and its operands are registers whose
-   use is actually in the subroutine it calls, you should define this macro.
-   Doing so allows the delay slot scheduler to move instructions which copy
-   arguments into the argument registers into the delay slot of INSN.
-
-   You need not define this macro if it would always return zero.  */
-/* #define INSN_REFERENCES_ARE_DELAYED(INSN) */
-
-/* #define MACHINE_DEPENDENT_REORG(INSN) fr30_reorg (INSN) */
-
-/* Define this macro if in some cases global symbols from one translation unit
-   may not be bound to undefined symbols in another translation unit without
-   user intervention.  For instance, under Microsoft Windows symbols must be
-   explicitly imported from shared libraries (DLLs).  */
-/* #define MULTIPLE_SYMBOL_SPACES */
-
-/* A C expression for the maximum number of instructions to execute via
-   conditional execution instructions instead of a branch.  A value of
-   BRANCH_COST+1 is the default if the machine does not use
-   cc0, and 1 if it does use cc0.  */
-/* #define MAX_CONDITIONAL_EXECUTE */
-
-/* Indicate how many instructions can be issued at the same time.  */
-/* #define ISSUE_RATE */
-
-/* If cross-compiling, don't require stdio.h etc to build libgcc.a.  */
-#if defined CROSS_COMPILE && ! defined inhibit_libc
-#define inhibit_libc
-#endif
-
-/*}}}*/ 
-/*{{{  Exported variables */ 
-
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  Note that we can't use "rtx" here
-   since it hasn't been defined!  */
-
-extern struct rtx_def * fr30_compare_op0;
-extern struct rtx_def * fr30_compare_op1;
-
-/*}}}*/ 
-/*{{{  PERDICATE_CODES */ 
-
-#define PREDICATE_CODES					\
-  { "stack_add_operand",	{ CONST_INT }},		\
-  { "high_register_operand",	{ REG }},		\
-  { "low_register_operand",	{ REG }},		\
-  { "call_operand",		{ REG, MEM }},		\
-  { "fp_displacement_operand",	{ CONST_INT }},		\
-  { "sp_displacement_operand",	{ CONST_INT }},		\
-  { "add_immediate_operand",	{ REG, CONST_INT }},
-
-/*}}}*/ 
-/*{{{  Functions defined in fr30.c */
-
-extern void fr30_expand_prologue PROTO ((void));
-extern void fr30_expand_epilogue PROTO ((void));
-extern unsigned int fr30_compute_frame_size PROTO ((int, int));
-extern int stack_add_operand        PROTO ((Rtx, int));
-extern int add_immediate_operand    PROTO ((Rtx, int));
-extern int high_register_operand    PROTO ((Rtx, int));
-extern int low_register_operand     PROTO ((Rtx, int));
-extern int call_operand             PROTO ((Rtx, int));
-extern int fp_displacement_operand  PROTO ((Rtx, int));
-extern int sp_displacement_operand  PROTO ((Rtx, int));
-extern int fr30_check_multiple_regs PROTO ((Rtx *, int, int));
-
-/*}}}*/ 
-
-/* Local Variables: */
-/* folded-file: t   */
-/* End:		    */
-
-/* END CYGNUS LOCAL -- nickc/fr30 */
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md
deleted file mode 100755
index 6970c16..0000000
--- a/gcc/config/fr30/fr30.md
+++ /dev/null
@@ -1,1404 +0,0 @@
-;; CYGNUS LOCAL -- nickc/fr30
-
-;;{{{ Comment 
-
-;; FR30 machine description.
-;; Copyright (C) 1998, 1999 Free Software Foundation, Inc.
-;; Contributed by Cygnus Solutions.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;;}}} 
-;;{{{ Attributes 
-
-(define_attr "length" "" (const_int 2))
-
-;; Used to distinguish between small memory model targets and big mode targets.
-
-(define_attr "size" "small,big"
-  (const (if_then_else (symbol_ref "TARGET_SMALL_MODEL")
-		       (const_string "small")
-		       (const_string "big"))))
-
-
-;; Define an attribute to be used by the delay slot code.
-;; An instruction by default is considered to be 'delyabable'
-;; that is, it can be placed into a delay slot, but it is not
-;; itself an delyaed branch type instruction.  An instruction
-;; whoes type is 'delayed' is one which has a delay slot, and
-;; an instruction whoes delay_type is 'other' is one which does
-;; not have a delay slot, nor can it be placed into a delay slot.
-
-(define_attr "delay_type" "delayable,delayed,other" (const_string "delayable"))
-
-;;}}} 
-;;{{{ Delay Slot Specifications 
-
-(define_delay (eq_attr "delay_type" "delayed")
-  [(and (eq_attr "delay_type" "delayable")
-	(eq_attr "length" "2"))
-   (nil)
-   (nil)]
-)
-
-;;}}}
-;;{{{ Moves 
-
-;;{{{ Comment 
-
-;; Wrap moves in define_expand to prevent memory->memory moves from being
-;; generated at the RTL level, which generates better code for most machines
-;; which can't do mem->mem moves.
-
-;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
-;; than M, the effect of this instruction is to store the specified value in
-;; the part of the register that corresponds to mode M.  The effect on the rest
-;; of the register is undefined.
-
-;; This class of patterns is special in several ways.  First of all, each of
-;; these names *must* be defined, because there is no other way to copy a datum
-;; from one place to another.
-
-;; Second, these patterns are not used solely in the RTL generation pass.  Even
-;; the reload pass can generate move insns to copy values from stack slots into
-;; temporary registers.  When it does so, one of the operands is a hard
-;; register and the other is an operand that can need to be reloaded into a
-;; register.
-
-;; Therefore, when given such a pair of operands, the pattern must
-;; generate RTL which needs no reloading and needs no temporary
-;; registers--no registers other than the operands.  For example, if
-;; you support the pattern with a `define_expand', then in such a
-;; case the `define_expand' mustn't call `force_reg' or any other such
-;; function which might generate new pseudo registers.
-
-;; This requirement exists even for subword modes on a RISC machine
-;; where fetching those modes from memory normally requires several
-;; insns and some temporary registers.  Look in `spur.md' to see how
-;; the requirement can be satisfied.
-
-;; During reload a memory reference with an invalid address may be passed as an
-;; operand.  Such an address will be replaced with a valid address later in the
-;; reload pass.  In this case, nothing may be done with the address except to
-;; use it as it stands.  If it is copied, it will not be replaced with a valid
-;; address.  No attempt should be made to make such an address into a valid
-;; address and no routine (such as `change_address') that will do so may be
-;; called.  Note that `general_operand' will fail when applied to such an
-;; address.
-;;
-;; The global variable `reload_in_progress' (which must be explicitly declared
-;; if required) can be used to determine whether such special handling is
-;; required.
-;;
-;; The variety of operands that have reloads depends on the rest of
-;; the machine description, but typically on a RISC machine these can
-;; only be pseudo registers that did not get hard registers, while on
-;; other machines explicit memory references will get optional
-;; reloads.
-;;
-;; If a scratch register is required to move an object to or from memory, it
-;; can be allocated using `gen_reg_rtx' prior to reload.  But this is
-;; impossible during and after reload.  If there are cases needing scratch
-;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
-;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
-;; patterns `reload_inM' or `reload_outM' to handle them.
-
-;; The constraints on a `moveM' must permit moving any hard register to any
-;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
-;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
-;; value of 2.
-
-;; It is obligatory to support floating point `moveM' instructions
-;; into and out of any registers that can hold fixed point values,
-;; because unions and structures (which have modes `SImode' or
-;; `DImode') can be in those registers and they may have floating
-;; point members.
-
-;; There may also be a need to support fixed point `moveM' instructions in and
-;; out of floating point registers.  Unfortunately, I have forgotten why this
-;; was so, and I don't know whether it is still true.  If `HARD_REGNO_MODE_OK'
-;; rejects fixed point values in floating point registers, then the constraints
-;; of the fixed point `moveM' instructions must be designed to avoid ever
-;; trying to reload into a floating point register.
-
-;;}}}
-;;{{{ Push and Pop  
-
-;; Push a register onto the stack
-(define_insn "movsi_push"
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	(match_operand:SI 0 "register_operand" "a"))]
-  ""
-  "st	%0, @-r15"
-)
-
-;; Pop a register off the stack
-(define_insn "movsi_pop"
-  [(set:SI (match_operand:SI 0 "register_operand" "a")
-	(mem:SI (post_inc:SI (reg:SI 15))))]
-  ""
-  "ld	@r15+, %0"
-)
-
-;;}}}
-;;{{{ 1 Byte Moves 
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (!reload_in_progress
-      && !reload_completed
-      && GET_CODE (operands[0]) == MEM
-      && (GET_CODE (operands[1]) == MEM
-         || immediate_operand (operands[1], QImode)))
-    operands[1] = copy_to_mode_reg (QImode, operands[1]);
-}")
-
-(define_insn "movqi_unsigned_register_load"
-  [(set (match_operand:SI 0 "register_operand"              "=r")
-	(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
-  ""
-  "ldub	%1, %0"
-)
-
-(define_expand "movqi_signed_register_load"
-  [(set (match_operand:SI 0 "register_operand"               "")
-	(sign_extend:SI (match_operand:QI 1 "memory_operand" "")))]
-  ""
-  "
-  emit_insn (gen_movqi_unsigned_register_load (operands[0], operands[1]));
-  emit_insn (gen_extendqisi2 (operands[0], operands[0]));
-  DONE;
-  "
-)
-
-(define_insn "*movqi_internal"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,red,m,r")
-	(match_operand:QI 1 "general_operand"       "i,red,r,rm"))]
-  ""
-  "@
-   ldi:8\\t#%A1, %0
-   mov  \\t%1, %0
-   stb  \\t%1, %0
-   ldub \\t%1, %0"
-)
-
-;;}}}
-;;{{{ 2 Byte Moves 
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (!reload_in_progress
-      && !reload_completed
-      && GET_CODE (operands[0]) == MEM
-      && (GET_CODE (operands[1]) == MEM
-	 || immediate_operand (operands[1], HImode)))
-    operands[1] = copy_to_mode_reg (HImode, operands[1]);
-}")
-
-(define_insn "movhi_unsigned_register_load"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
-  ""
-  "lduh	%1, %0"
-)
-
-(define_expand "movhi_signed_register_load"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI (match_operand:HI 1 "memory_operand" "")))]
-  ""
-  "
-  emit_insn (gen_movhi_unsigned_register_load (operands[0], operands[1]));
-  emit_insn (gen_extendhisi2 (operands[0], operands[0]));
-  DONE;
-  "
-)
-
-(define_insn "*movhi_internal"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,red,m,r")
-	(match_operand:HI 1 "general_operand"       "L,M,n,red,r,rm"))]
-  ""
-  "@
-   ldi:8 \\t#%1, %0
-   ldi:20\\t#%1, %0
-   ldi:32\\t#%1, %0
-   mov   \\t%1, %0
-   sth   \\t%1, %0
-   lduh  \\t%1, %0"
-  [(set_attr "length" "*,4,6,*,*,*")]
-)
-
-;;}}}
-;;{{{ 4 Byte Moves 
-
-;; If the destination is a MEM and the source is a
-;; MEM or an CONST_INT move the source into a register.
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "{
-  if (!reload_in_progress
-      && !reload_completed
-      && GET_CODE(operands[0]) == MEM
-      && (GET_CODE (operands[1]) == MEM
-	  || immediate_operand (operands[1], SImode)))
-     operands[1] = copy_to_mode_reg (SImode, operands[1]);
-  }"
-)
-
-;; We can do some clever tricks when loading certain immediate
-;; values.  We implement these tricks as define_splits, rather
-;; than putting the code into the define_expand "movsi" above,
-;; because if we put them there, they will be evaluated at RTL
-;; generation time and then the combiner pass will come along
-;; and replace the multiple insns that have been generated with
-;; the original, slower, load insns.  (The combiner pass only
-;; cares about reducing the number of instructions, it does not
-;; care about instruction lengths or speeds).  Splits are
-;; evaluated after the combine pass and before the scheduling
-;; passes, so that they are the perfect place to put this
-;; intelligence.
-;;
-;; XXX we probably ought to implement these for QI and HI mode
-;; loads as well.
-
-;; If we are loading a small negative constant we can save space
-;; and time by loading the positive value and then sign extending it.
-(define_split
-  [(set (match_operand:SI 0 "register_operand"  "r")
-	(match_operand:SI 1 "immediate_operand" "i"))]
-   "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128"
-   [(set:SI (match_dup 0) (match_dup 2))
-    (set:SI (match_dup 0) (sign_extend:SI (subreg:QI (match_dup 0) 0)))]
-   "{
-   operands[2] = GEN_INT (INTVAL (operands[1]) & 0xff);
-   }"
-)
-
-;; If we are loading a large negative constant, one which does
-;; not have any of its bottom 24 bit set, then we can save time
-;; and space by loading the byte value and shifting it into place.
-(define_split
-  [(set (match_operand:SI 0 "register_operand"  "r")
-	(match_operand:SI 1 "immediate_operand" "i"))]
-   "(INTVAL (operands[1]) < 0) && (INTVAL (operands[1]) & 0x00ffffff == 0)"
-   [(set:SI (match_dup 0) (match_dup 2))
-    (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (const_int 24)))
-	       (clobber (reg:CC 16))])]
-   "{
-   HOST_WIDE_INT val = INTVAL (operands[1]);
-   operands[2] = GEN_INT (val >> 24);
-   }"
-)
-
-;; If we are loading a large positive constant, one which has bits
-;; in the top byte set, but whoes set bits all lie within an 8 bit
-;; range, then we can save time and space by loading the byte value
-;; and shifting it into place.
-(define_split
-  [(set (match_operand:SI 0 "register_operand"  "r")
-	(match_operand:SI 1 "immediate_operand" "i"))]
-   "(INTVAL (operands[1]) > 0x00ffffff)
-   && ((INTVAL (operands[1]) >> exact_log2 (INTVAL (operands[1]) & (- INTVAL (operands[1])))) < 0x100)"
-   [(set:SI (match_dup 0) (match_dup 2))
-    (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))
-	       (clobber (reg:CC 16))])]
-   "{
-   HOST_WIDE_INT val = INTVAL (operands[1]);
-   int shift = exact_log2 (val & ( - val));
-   operands[2] = GEN_INT (val >> shift);
-   operands[3] = GEN_INT (shift);
-   }"
-)
-
-;; When TARGET_SMALL_MODEL is defined we assume that all symbolic
-;; values are addresses which will fit in 20 bits.
-
-(define_insn "movsi_internal"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,red,m,r")
-	(match_operand:SI 1 "general_operand"       "L,M,n,i,rde,r,rm"))]
-  ""
-  "*
-  {
-    switch (which_alternative)
-    {
-    case 0: return   \"ldi:8 \\t#%1, %0\";
-    case 1: return   \"ldi:20\\t#%1, %0\";
-    case 2: return   \"ldi:32\\t#%1, %0\";
-    case 3: if (TARGET_SMALL_MODEL)
-	      return \"ldi:20\\t%1, %0\";
-            else
-	      return \"ldi:32\\t%1, %0\";
-    case 4: return   \"mov   \\t%1, %0\";
-    case 5: return   \"st    \\t%1, %0\";
-    case 6: return   \"ld    \\t%1, %0\";
-    default: abort ();	       
-    }
-  }"
-  [(set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 4)
-			       (eq_attr "alternative" "2") (const_int 6)
-			       (eq_attr "alternative" "3") 
-			                (if_then_else (eq_attr "size" "small")
-						      (const_int 4)
-						      (const_int 6))]
-			      (const_int 2)))]
-)
-
-;;}}}
-;;{{{ Load & Store Multiple Registers 
-
-;; The load multiple and store multiple patterns are implemented
-;; as peepholes because the only time they are expected to occur
-;; is during function prologues and epilogues.
-
-(define_peephole
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "high_register_operand" "h"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 1 "high_register_operand" "h"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 2 "high_register_operand" "h"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 3 "high_register_operand" "h"))]
-  "fr30_check_multiple_regs (operands, 4, 1)"
-  "stm1	(%0, %1, %2, %3)"
-  [(set_attr "delay_type" "other")]
-)
-
-(define_peephole
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "high_register_operand" "h"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 1 "high_register_operand" "h"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 2 "high_register_operand" "h"))]
-  "fr30_check_multiple_regs (operands, 3, 1)"
-  "stm1	(%0, %1, %2)"
-  [(set_attr "delay_type" "other")]
-)
-
-(define_peephole
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "high_register_operand" "h"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 1 "high_register_operand" "h"))]
-  "fr30_check_multiple_regs (operands, 2, 1)"
-  "stm1	(%0, %1)"
-  [(set_attr "delay_type" "other")]
-)
-
-(define_peephole
-  [(set:SI (match_operand:SI 0 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))
-   (set:SI (match_operand:SI 1 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))
-   (set:SI (match_operand:SI 2 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))
-   (set:SI (match_operand:SI 3 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))]
-  "fr30_check_multiple_regs (operands, 4, 0)"
-  "ldm1	(%0, %1, %2, %3)"
-  [(set_attr "delay_type" "other")]
-)
-
-(define_peephole
-  [(set:SI (match_operand:SI 0 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))
-   (set:SI (match_operand:SI 1 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))
-   (set:SI (match_operand:SI 2 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))]
-  "fr30_check_multiple_regs (operands, 3, 0)"
-  "ldm1	(%0, %1, %2)"
-  [(set_attr "delay_type" "other")]
-)
-
-(define_peephole
-  [(set:SI (match_operand:SI 0 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))
-   (set:SI (match_operand:SI 1 "high_register_operand" "h")
-           (mem:SI (post_inc:SI (reg:SI 15))))]
-  "fr30_check_multiple_regs (operands, 2, 0)"
-  "ldm1	(%0, %1)"
-  [(set_attr "delay_type" "other")]
-)
-
-(define_peephole
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "low_register_operand" "l"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 1 "low_register_operand" "l"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 2 "low_register_operand" "l"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 3 "low_register_operand" "l"))]
-  "fr30_check_multiple_regs (operands, 4, 1)"
-  "stm0	(%0, %1, %2, %3)"
-  [(set_attr "delay_type" "other")]
-)
-
-(define_peephole
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "low_register_operand" "l"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 1 "low_register_operand" "l"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 2 "low_register_operand" "l"))]
-  "fr30_check_multiple_regs (operands, 3, 1)"
-  "stm0	(%0, %1, %2)"
-  [(set_attr "delay_type" "other")]
-)
-
-(define_peephole
-  [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-	   (match_operand:SI 0 "low_register_operand" "l"))
-   (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
-           (match_operand:SI 1 "low_register_operand" "l"))]
-  "fr30_check_multiple_regs (operands, 2, 1)"
-  "stm0	(%0, %1)"
-  [(set_attr "delay_type" "other")]
-)
-
-;;}}}
-;;{{{ Floating Point Moves 
-
-;; Note - Patterns for SF mode moves are compulsory, but
-;; patterns for DF are optional, as GCC can synthesise them.
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "{
-  if (!reload_in_progress && !reload_completed
-      && memory_operand (operands[0], SFmode)
-      && memory_operand (operands[1], SFmode))
-    operands[1] = copy_to_mode_reg (SFmode, operands[1]);
-  }"
-)
-
-(define_insn "*movsf_internal"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,red,m,r")
-	(match_operand:SF 1 "general_operand"      "Fn,i,rde,r,rm"))]
-  ""
-  "*
-  {
-    switch (which_alternative)
-    {
-    case 0: return   \"ldi:32\\t%1, %0\";
-    case 1: if (TARGET_SMALL_MODEL)
-	      return \"ldi:20\\t%1, %0\";
-            else
-	      return \"ldi:32\\t%1, %0\";
-    case 2: return   \"mov   \\t%1, %0\";
-    case 3: return   \"st    \\t%1, %0\";
-    case 4: return   \"ld    \\t%1, %0\";
-    default: abort ();	       
-    }
-  }"
-  [(set (attr "length") (cond [(eq_attr "alternative" "0") (const_int 6)
-			       (eq_attr "alternative" "1") 
-			                (if_then_else (eq_attr "size" "small")
-						      (const_int 4)
-						      (const_int 6))]
-			      (const_int 2)))]
-)
-
-(define_insn "*movsf_constant_store"
-  [(set (match_operand:SF 0 "memory_operand"    "m")
-	(match_operand:SF 1 "immediate_operand" "F"))]
-  ""
-  "*
-  {
-  char *         ldi_instr;
-  char *          tmp_reg;
-  static char     buffer[100];
-  REAL_VALUE_TYPE d;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
-  
-  if (REAL_VALUES_EQUAL (d, dconst0))
-    ldi_instr = \"ldi:8\";
-  else
-    ldi_instr = \"ldi:32\";
-
-  tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
-  
-  sprintf (buffer, \"%s\\t#%%1, %s\\t;\\n\\tst\\t%s, %%0\\t; Created by movsf_constant_store\",
-    ldi_instr, tmp_reg, tmp_reg);
-
-  return buffer;
-  }"
-  [(set_attr "length" "8")]
-)
-
-;;}}}
-
-;;}}} 
-;;{{{ Conversions 
-
-;; Signed conversions from a smaller integer to a larger integer
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand"                "=r")
-	(sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
-  ""
-  "extsb	%0"
-)
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand"                "=r")
-	(sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
-  ""
-  "extsh	%0"
-)
-
-;; Unsigned conversions from a smaller integer to a larger integer
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand"                "=r")
-	(zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
-  ""
-  "extub	%0"
-)
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand"                "=r")
-	(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
-  ""
-  "extuh	%0"
-)
-
-;;}}} 
-;;{{{ Arithmetic 
-
-;;{{{ Addition 
-
-;; This is a special pattern just for adjusting the stack size.
-(define_insn "add_to_stack"
-  [(set (reg:SI 15)
-	(plus:SI (reg:SI 15)
-		 (match_operand:SI 0 "stack_add_operand" "i")))]
-  ""
-  "addsp	%0"
-)
-
-;; We need some trickery to be able to handle the addition of
-;; large (ie outside +/- 16) constants.  We need to be able to
-;; handle this because reload assumes that it can generate add
-;; instructions with arbitary sized constants.
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "register_operand"           "")
-	(plus:SI (match_operand:SI 1 "register_operand"  "")
-		 (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "{
-  if (   GET_CODE (operands[2]) == REG
-      || GET_CODE (operands[2]) == SUBREG)
-    emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2]));
-  else if (GET_CODE (operands[2]) != CONST_INT)
-    emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
-  else if ((INTVAL (operands[2]) >= -16) && (INTVAL (operands[2]) <= 15))
-    emit_insn (gen_addsi_small_int (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
-  DONE;
-  }"
-)
-
-(define_insn "addsi_regs"
-  [(set (match_operand:SI 0 "register_operand"          "=r")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0")
-		 (match_operand:SI 2 "register_operand"  "r")))]
-  ""
-  "addn	%2, %0"
-)
-
-(define_insn "addsi_small_int"
-  [(set (match_operand:SI 0 "register_operand"              "=r,r")
-	(plus:SI (match_operand:SI 1 "register_operand"      "0,0")
-		 (match_operand:SI 2 "add_immediate_operand" "I,J")))]
-  ""
-  "@
-   addn	%2, %0
-   addn2	%2, %0"
-)
-
-(define_expand "addsi_big_int"
-  [(set (match_operand:SI 0 "register_operand"           "")
-	(plus:SI (match_operand:SI 1 "register_operand"  "")
-		 (match_operand:SI 2 "immediate_operand" "")))]
-  ""
-  "{
-  /* Cope with the possibility that ops 0 and 1 are the same register.  */
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    {
-      if (reload_in_progress || reload_completed)
-        {
-	  rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
-	  
-	  emit_insn (gen_movsi (reg, operands[2]));
-	  emit_insn (gen_addsi_regs (operands[0], operands[0], reg));
-	}
-      else
-	{
-	  operands[2] = force_reg (SImode, operands[2]);
-	  emit_insn (gen_addsi_regs (operands[0], operands[0], operands[2]));
-	}
-    }
-  else
-    {
-      emit_insn (gen_movsi (operands[0], operands[2]));
-      emit_insn (gen_addsi_regs (operands[0], operands[0], operands[1]));
-    }
-  DONE;
-  }"
-)
-
-(define_insn "*addsi_for_reload"
-  [(set (match_operand:SI 0 "register_operand"         "=&r,r,r")
-	(plus:SI (match_operand:SI 1 "register_operand"  "r,r,r")
-		 (match_operand:SI 2 "immediate_operand" "L,M,n")))]
-  "reload_in_progress || reload_completed"
-  "@
-  ldi:8\\t#%2, %0  \\n\\taddn\\t%1, %0
-  ldi:20\\t#%2, %0 \\n\\taddn\\t%1, %0
-  ldi:32\\t#%2, %0 \\n\\taddn\\t%1, %0"
-  [(set_attr "length" "4,6,8")]
-)
-
-;;}}}
-;;{{{ Subtraction 
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "register_operand"       "=r")
-	(minus (match_operand:SI 1 "register_operand" "0")
-	       (match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "subn	%2, %0"
-)
-
-;;}}}
-;;{{{ Multiplication 
-
-;; Signed multiplication producing 64 bit results from 32 bit inputs
-(define_insn "mulsidi3"
-  [(set (match_operand:DI 0 "register_operand"                             "=r")
-	   (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
-		    (sign_extend:DI (match_operand:SI 2 "register_operand"  "r"))))
-   (clobber (reg:CC 16))]
-  ""
-  "mul	%2, %1\\n\\tmov\\tmdh, %0\\n\\tmov\\tmdl, %p0"
-  [(set_attr "length" "6")]
-)
-
-;; Unsigned multiplication producing 64 bit results from 32 bit inputs
-(define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "register_operand"                             "=r")
-	   (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
-		    (zero_extend:DI (match_operand:SI 2 "register_operand"  "r"))))
-   (clobber (reg:CC 16))]
-  ""
-  "mulu	%2, %1\\n\\tmov\\tmdh, %0\\n\\tmov\\tmdl, %p0"
-  [(set_attr "length" "6")]
-)
-
-;; Signed multiplication producing 32 bit result from 16 bit inputs
-(define_insn "mulhisi3"
-  [(set (match_operand:SI 0 "register_operand"                             "=r")
-	   (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
-		    (sign_extend:SI (match_operand:HI 2 "register_operand"  "r"))))
-   (clobber (reg:CC 16))]
-  ""
-  "mulh	%2, %1\\n\\tmov\\tmdl, %0"
-  [(set_attr "length" "4")]
-)
-
-;; Unsigned multiplication producing 32 bit result from 16 bit inputs
-(define_insn "umulhisi3"
-  [(set (match_operand:SI 0 "register_operand"                             "=r")
-	   (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r"))
-		    (zero_extend:SI (match_operand:HI 2 "register_operand"  "r"))))
-   (clobber (reg:CC 16))]
-  ""
-  "muluh	%2, %1\\n\\tmov\\tmdl, %0"
-  [(set_attr "length" "4")]
-)
-
-;; Signed multiplication producing 32 bit result from 32 bit inputs
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand"             "=r")
-	   (mult:SI (match_operand:SI 1 "register_operand" "%r")
-		    (match_operand:SI 2 "register_operand"  "r")))
-   (clobber (reg:CC 16))]
-  ""
-  "mul	%2, %1\\n\\tmov\\tmdl, %0"
-  [(set_attr "length" "4")]
-)
-
-;;}}}
-;;{{{ Negation 
-
-(define_expand "negsi2"
-  [(set (match_operand:SI 0 "register_operand"         "")
-	(neg:SI (match_operand:SI 1 "register_operand" "")))]
-  ""
-  "{
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    {
-      if (reload_in_progress || reload_completed)
-        {
-	  rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
-	  
-	  emit_insn (gen_movsi (reg, GEN_INT (0)));
-	  emit_insn (gen_subsi3 (reg, reg, operands[0]));
-	  emit_insn (gen_movsi (operands[0], reg));
-	}
-      else
-	{
-	  rtx reg = gen_reg_rtx (SImode);
-	
-	  emit_insn (gen_movsi (reg, GEN_INT (0)));
-	  emit_insn (gen_subsi3 (reg, reg, operands[0]));
-	  emit_insn (gen_movsi (operands[0], reg));
-	}
-    }
-  else
-    {
-      emit_insn (gen_movsi_internal (operands[0], GEN_INT (0)));
-      emit_insn (gen_subsi3 (operands[0], operands[0], operands[1]));
-    }
-  DONE;
-  }"
-)
-
-;;}}}
-
-;;}}} 
-;;{{{ Shifts 
-
-;; Arithmetic Shift Left
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand"            "=r,r,r")
-	(ashift:SI (match_operand:SI 1 "register_operand"  "0,0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
-   (clobber (reg:CC 16))]
-  ""
-  "@
-  lsl	%2, %0
-  lsl	%2, %0
-  lsl2	%x2, %0"
-)
-
-;; Arithmetic Shift Right
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand"              "=r,r,r")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand"  "0,0,0")
-		     (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
-   (clobber (reg:CC 16))]
-  ""
-  "@
-  asr	%2, %0
-  asr	%2, %0
-  asr2	%x2, %0"
-)
-
-;; Logical Shift Right
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand"              "=r,r,r")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand"  "0,0,0")
-		     (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
-   (clobber (reg:CC 16))]
-  ""
-  "@
-  lsr	%2, %0
-  lsr	%2, %0
-  lsr2	%x2, %0"
-)
-
-;;}}} 
-;;{{{ Logical Operations 
-
-;; Logical AND, 32 bit integers
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand"         "=r")
-	(and:SI (match_operand:SI 1 "register_operand" "%r")
-		(match_operand:SI 2 "register_operand"  "0")))
-   (clobber (reg:CC 16))]
-  ""
-  "and	%1, %0"
-)
-
-;; Inclusive OR, 32 bit integers
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand"         "=r")
-	(ior:SI (match_operand:SI 1 "register_operand" "%r")
-		(match_operand:SI 2 "register_operand"  "0")))
-   (clobber (reg:CC 16))]
-  ""
-  "or	%1, %0"
-)
-
-;; Exclusive OR, 32 bit integers
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand"         "=r")
-	(xor:SI (match_operand:SI 1 "register_operand" "%r")
-		(match_operand:SI 2 "register_operand"  "0")))
-   (clobber (reg:CC 16))]
-  ""
-  "eor	%1, %0"
-)
-
-;; One's complement, 32 bit integers
-(define_expand "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand"         "")
-	(not:SI (match_operand:SI 1 "register_operand" "")))]
-  ""
-  "{
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    {
-      if (reload_in_progress || reload_completed)
-        {
-	  rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
-	  
-	  emit_insn (gen_movsi (reg, GEN_INT (-1)));
-	  emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
-	}
-      else
-	{
-	  rtx reg = gen_reg_rtx (SImode);
-	
-	  emit_insn (gen_movsi (reg, GEN_INT (-1)));
-	  emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
-	}
-    }
-  else
-    {
-      emit_insn (gen_movsi_internal (operands[0], GEN_INT (-1)));
-      emit_insn (gen_xorsi3 (operands[0], operands[1], operands[0]));
-    }
-  DONE;
-  }"
-)
-
-;;}}} 
-;;{{{ Comparisons 
-
-;; Note, we store the operands in the comparison insns, and use them later
-;; when generating the branch or scc operation.
-
-;; First the routines called by the machine independent part of the compiler
-(define_expand "cmpsi"
-  [(set (reg:CC 16)
-        (compare:CC (match_operand:SI 0 "register_operand"  "")
-		    (match_operand:SI 1 "nonmemory_operand" "")))]
-  ""
-  "{
-  fr30_compare_op0 = operands[0];
-  fr30_compare_op1 = operands[1];
-  DONE;
-  }"
-)
-
-;; Now, the actual comparisons, generated by the branch and/or scc operations
-
-(define_insn "*cmpsi_internal"
-  [(set (reg:CC 16)
-	(compare:CC (match_operand:SI 0 "register_operand"  "r,r,r")
-		    (match_operand:SI 1 "nonmemory_operand" "r,I,J")))]
-  ""
-  "@
-  cmp	%1, %0
-  cmp	%1, %0
-  cmp2	%1, %0"
-)
-
-;;}}} 
-;;{{{ Branches 
-
-;; Define_expands called by the machine independent part of the compiler
-;; to allocate a new comparison register
-
-(define_expand "beq"
-  [(set (reg:CC 16)
-	(compare:CC (match_dup 1)
-		    (match_dup 2)))
-   (set (pc)
-	(if_then_else (eq:CC (reg:CC 16)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{
-  operands[1] = fr30_compare_op0;
-  operands[2] = fr30_compare_op1;
-  }"
-)
-
-(define_expand "bne"
-  [(set (reg:CC 16)
-	(compare:CC (match_dup 1)
-		    (match_dup 2)))
-   (set (pc)
-	(if_then_else (ne:CC (reg:CC 16)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{
-  operands[1] = fr30_compare_op0;
-  operands[2] = fr30_compare_op1;
-  }"
-)
-
-(define_expand "blt"
-  [(set (reg:CC 16)
-	(compare:CC (match_dup 1)
-		    (match_dup 2)))
-   (set (pc)
-	(if_then_else (lt:CC (reg:CC 16)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{
-  operands[1] = fr30_compare_op0;
-  operands[2] = fr30_compare_op1;
-  }"
-)
-
-(define_expand "ble"
-  [(set (reg:CC 16)
-	(compare:CC (match_dup 1)
-		    (match_dup 2)))
-   (set (pc)
-	(if_then_else (le:CC (reg:CC 16)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{
-  operands[1] = fr30_compare_op0;
-  operands[2] = fr30_compare_op1;
-  }"
-)
-
-(define_expand "bgt"
-  [(set (reg:CC 16)
-	(compare:CC (match_dup 1)
-		    (match_dup 2)))
-   (set (pc)
-	(if_then_else (gt:CC (reg:CC 16)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{
-  operands[1] = fr30_compare_op0;
-  operands[2] = fr30_compare_op1;
-  }"
-)
-
-(define_expand "bge"
-  [(set (reg:CC 16)
-	(compare:CC (match_dup 1)
-		    (match_dup 2)))
-   (set (pc)
-	(if_then_else (ge:CC (reg:CC 16)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{
-  operands[1] = fr30_compare_op0;
-  operands[2] = fr30_compare_op1;
-  }"
-)
-
-(define_expand "bltu"
-  [(set (reg:CC 16)
-	(compare:CC (match_dup 1)
-		    (match_dup 2)))
-   (set (pc)
-	(if_then_else (ltu:CC (reg:CC 16)
-			      (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{
-  operands[1] = fr30_compare_op0;
-  operands[2] = fr30_compare_op1;
-  }"
-)
-
-(define_expand "bleu"
-  [(set (reg:CC 16)
-	(compare:CC (match_dup 1)
-		    (match_dup 2)))
-   (set (pc)
-	(if_then_else (leu:CC (reg:CC 16)
-			      (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{
-  operands[1] = fr30_compare_op0;
-  operands[2] = fr30_compare_op1;
-  }"
-)
-
-(define_expand "bgtu"
-  [(set (reg:CC 16)
-	(compare:CC (match_dup 1)
-		    (match_dup 2)))
-   (set (pc)
-	(if_then_else (gtu:CC (reg:CC 16)
-			      (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{
-  operands[1] = fr30_compare_op0;
-  operands[2] = fr30_compare_op1;
-  }"
-)
-
-(define_expand "bgeu"
-  [(set (reg:CC 16)
-	(compare:CC (match_dup 1)
-		    (match_dup 2)))
-   (set (pc)
-	(if_then_else (geu:CC (reg:CC 16)
-			      (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "{
-  operands[1] = fr30_compare_op0;
-  operands[2] = fr30_compare_op1;
-  }"
-)
-
-;; Actual branches.  We must allow for the (label_ref) and the (pc) to be
-;; swapped.  If they are swapped, it reverses the sense of the branch.
-
-;; This pattern matches the (branch-if-true) branches generated above.
-;; It generates two different instruction sequences depending upon how
-;; far away the destination is.
-
-;; The calculation for the instruction length is derived as follows:
-;; The branch instruction has a 9 bit signed displacement so we have
-;; this inequality for the displacement:
-;;
-;;               -256 <= pc < 256
-;; or
-;;	   -256 + 256 <= pc + 256 < 256 + 256
-;; ie
-;;		    0 <= pc + 256 < 512 
-;;
-;; if we consider the displacement as an unsigned value, then negative
-;; displacements become very large positive displacements, and the
-;; inequality becomes:
-;;
-;;		pc + 256 < 512
-;;
-;; In order to allow for the fact that the real branch instruction works
-;; from pc + 2, we increase the offset to 258.
-;;
-;; Note - we do not have to worry about whether the branch is delayed or
-;; not, as branch shortening happens after delay slot reorganisation.
-
-(define_insn "*branch_true"
-  [(set (pc)
-	(if_then_else (match_operator:CC 0 "comparison_operator"
-					 [(reg:CC 16)
-					  (const_int 0)])
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))]
-  ""
-  "*
-  {
-    if (get_attr_length (insn) == 2)
-      return \"b%b0%#\\t%l1\";
-    else
-      {
-        static char buffer [100];
-	char *      tmp_reg; 
-	char *      ldi_insn;
-	
-        tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
-	
-	ldi_insn = TARGET_SMALL_MODEL ? \"ldi:20\" : \"ldi:32\";
-
-	/* The code produced here is, for say the EQ case:
-
-	       Bne  1f
-	       LDI  <label>, r0
-	       JMP  r0
-	     1:                                         */
-	     
-	sprintf (buffer,
-	  \"b%%B0\\t1f\\t;\\n\\t%s\\t%%l1, %s\\t;\\n\\tjmp%#\\t@%s\\t;\\n1:\",
-	  ldi_insn, tmp_reg, tmp_reg);
- 
-        return buffer;
-    }
-  }"
-  [(set (attr "length") (if_then_else
-			  (ltu
-			    (plus
-			      (minus
-			        (match_dup 1)
-				(pc))
-			      (const_int 254))
-			    (const_int 506))
-			  (const_int 2)
-			  (if_then_else (eq_attr "size" "small")
-					(const_int 8)
-					(const_int 10))))
-   (set_attr "delay_type" "delayed")]
-)
-
-
-;; This pattern is a duplicate of the previous one, except that the
-;; branch occurs if the test is false, so the %B operator is used.
-(define_insn "*branch_false"
-  [(set (pc)
-	(if_then_else (match_operator:CC 0 "comparison_operator"
-					 [(reg:CC 16)
-					  (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 1 "" ""))))]
-  ""
-  "*
-  {
-    if (get_attr_length (insn) == 2)
-      return \"b%B0%#\\t%l1 \";
-    else
-      {
-        static char buffer [100];
-	char *      tmp_reg; 
-	char *      ldi_insn;
-	
-        tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
-	
-	ldi_insn = TARGET_SMALL_MODEL ? \"ldi:20\" : \"ldi:32\";
-
-	sprintf (buffer,
-	  \"b%%b0\\t1f\\t;\\n\\t%s\\t%%l1, %s\\t;\\n\\tjmp%#\\t@%s\\t;\\n1:\",
-	  ldi_insn, tmp_reg, tmp_reg);
- 
-        return buffer;
-      }
-  }"
-  [(set (attr "length") (if_then_else (ltu (plus (minus (match_dup 1) (pc))
-						 (const_int 254))
-					   (const_int 506))
-				      (const_int 2)
-				      (if_then_else (eq_attr "size" "small")
-						    (const_int 8)
-						    (const_int 10))))
-   (set_attr "delay_type" "delayed")]
-)
-
-;;}}} 
-;;{{{ Calls & Jumps 
-
-;; Subroutine call instruction returning no value.  Operand 0 is the function
-;; to call; operand 1 is the number of bytes of arguments pushed (in mode
-;; `SImode', except it is normally a `const_int'); operand 2 is the number of
-;; registers used as operands.
-
-(define_insn "call"
-  [(call (match_operand 0 "call_operand" "Qrm")
-	 (match_operand 1 ""             "g"))
-   (clobber (reg:SI 17))]
-  ""
-  "call%#\\t%0"
-  [(set_attr "delay_type" "delayed")]
-)
-
-;; Subroutine call instruction returning a value.  Operand 0 is the hard
-;; register in which the value is returned.  There are three more operands, the
-;; same as the three operands of the `call' instruction (but with numbers
-;; increased by one).
-
-;; Subroutines that return `BLKmode' objects use the `call' insn.
-
-(define_insn "call_value"
-  [(set (match_operand 0 "register_operand"  "=r")
-	(call (match_operand 1 "call_operand" "Qrm")
-	      (match_operand 2 ""             "g")))
-   (clobber (reg:SI 17))]
-  ""
-  "call%#\\t%1"
-  [(set_attr "delay_type" "delayed")]
-)
-
-;; Normal unconditional jump.
-;; For a description of the computation of the length 
-;; attribute see the branch patterns above.
-(define_insn "jump"
-  [(set (pc) (label_ref (match_operand 0 "" "")))]
-  ""
-  "*
-  {
-    if (get_attr_length (insn) == 2)
-       return \"bra%#\\t%0\";
-    else
-      {
-        static char buffer [100];
-	char *      tmp_reg; 
-	char *      ldi_insn;
-	
-        tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
-
-	ldi_insn = TARGET_SMALL_MODEL ? \"ldi:20\" : \"ldi:32\";
-
-	sprintf (buffer, \"%s\\t%%0, %s\\t;\\n\\tjmp%#\\t@%s\\t;\",
-	  ldi_insn, tmp_reg, tmp_reg);
- 
-        return buffer;
-      }
-  }"
-  [(set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
-						(const_int 254))
-					  (const_int 506))
-				     (const_int 2)
-				     (if_then_else (eq_attr "size" "small")
-						   (const_int 6)
-						   (const_int 8))))
-   (set_attr "delay_type" "delayed")]
-)
-
-;; Indirect jump through a register
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "r"))]
-  "GET_CODE (operands[0]) != MEM || GET_CODE (XEXP (operands[0], 0)) != PLUS"
-  "jmp%#\\t@%0"
-  [(set_attr "delay_type" "delayed")]
-)
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmp%#\\t@%0"
-  [(set_attr "delay_type" "delayed")]
-)
-
-;;}}} 
-;;{{{ Function Prologues and Epilogues 
-
-;; Called after register allocation to add any instructions needed for the
-;; prologue.  Using a prologue insn is favored compared to putting all of the
-;; instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
-;; to intermix instructions with the saves of the caller saved registers.  In
-;; some cases, it might be necessary to emit a barrier instruction as the last
-;; insn to prevent such scheduling.
-(define_expand "prologue"
-  [(const_int 0)]
-  ""
-  "{
-  fr30_expand_prologue ();
-  DONE;
-  }"
-)
-
-;; Called after register allocation to add any instructions needed for the
-;; epilogue.  Using a epilogue insn is favored compared to putting all of the
-;; instructions in the FUNCTION_EPILOGUE macro, since it allows the scheduler
-;; to intermix instructions with the restores of the caller saved registers.
-;; In some cases, it might be necessary to emit a barrier instruction as the
-;; first insn to prevent such scheduling.
-(define_expand "epilogue"
-  [(return)]
-  ""
-  "{
-  fr30_expand_epilogue ();
-  DONE;
-  }"
-)
-
-(define_insn "return_from_func"
-  [(return)
-   (use (reg:SI 17))]
-  "reload_completed"
-  "ret%#"
-  [(set_attr "delay_type" "delayed")]
-)
-
-(define_insn "leave_func"
-  [(set (reg:SI 15) (reg:SI 14))
-   (set (reg:SI 14) (mem:SI (post_inc:SI (reg:SI 15))))]
-  "reload_completed"
-  "leave"
-)
-
-(define_insn "enter_func"
-  [(set:SI (mem:SI (minus:SI (reg:SI 15)
-			     (const_int 4)))
-	   (reg:SI 14))
-   (set:SI (reg:SI 14)
-	   (minus:SI (reg:SI 15)
-		     (const_int 4)))
-   (set:SI (reg:SI 15)
-	   (minus:SI (reg:SI 15)
-		     (match_operand 0 "immediate_operand" "i")))]
-  "reload_completed"
-  "enter	#%0"
-  [(set_attr "delay_type" "other")]
-)
-
-;;}}} 
-;;{{{ Miscellaneous 
-
-;; No operation, needed in case the user uses -g but not -O.
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-)
-
-;; Pseudo instruction that prevents the scheduler from moving code above this
-;; point.
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  ""
-  [(set_attr "length" "0")]
-)
-  
-;; Local Variables:
-;; mode: md
-;; folded-file: t
-;; End:
-
-;;}}} 
-
-;; END CYGNUS LOCAL -- nickc/fr30
diff --git a/gcc/config/fr30/lib1funcs.asm b/gcc/config/fr30/lib1funcs.asm
deleted file mode 100755
index 1369327..0000000
--- a/gcc/config/fr30/lib1funcs.asm
+++ /dev/null
@@ -1,126 +0,0 @@
-/* libgcc1 routines for the FR30.
-   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with files
-   compiled with GCC to produce an executable, this does not cause
-   the resulting executable to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-	
-
-	.macro FUNC_START name
-	.text
-	.globl __\name
-	.type  __\name, @function
-__\name:
-	.endm
-
-	.macro FUNC_END name
-	.size  __\name, . - __\name
-	.endm
-
-	.macro DIV_BODY reg number
-	.if \number
-	DIV_BODY  \reg, "\number - 1"
-	div1	\reg
-	.endif
-	.endm
-	
-#ifdef L_udivsi3
-FUNC_START udivsi3
-	;; Perform an unsiged division of r4 / r5 and place the result in r4.
-	;; Does not handle overflow yet...
-	mov	r4, mdl
-	div0u	r5
-	DIV_BODY r5 32
-	mov	mdl, r4
-	ret
-FUNC_END udivsi3
-#endif /* L_udivsi3 */
-
-#ifdef L_divsi3
-FUNC_START divsi3
-	;; Perform a siged division of r4 / r5 and place the result in r4.
-	;; Does not handle overflow yet...
-	mov	r4, mdl
-	div0s	r5
-	DIV_BODY r5 32
-	div2    r5
-	div3
-	div4s
-	mov	mdl, r4
-	ret
-FUNC_END divsi3
-#endif /* L_divsi3 */
-
-#ifdef L_umodsi3
-FUNC_START umodsi3
-	;; Perform an unsiged division of r4 / r5 and places the remainder in r4.
-	;; Does not handle overflow yet...
-	mov	r4, mdl
-	div0u	r5
-	DIV_BODY r5 32
-	mov	mdh, r4
-	ret
-FUNC_END umodsi3
-#endif /* L_umodsi3 */
-
-#ifdef L_modsi3
-FUNC_START modsi3
-	;; Perform a siged division of r4 / r5 and place the remainder in r4.
-	;; Does not handle overflow yet...
-	mov	r4, mdl
-	div0s	r5
-	DIV_BODY r5 32
-	div2    r5
-	div3
-	div4s
-	mov	mdh, r4
-	ret
-FUNC_END modsi3
-#endif /* L_modsi3 */
-
-#ifdef L_negsi2
-FUNC_START negsi2
-	ldi:8	#0, r0
-	sub	r4, r0
-	mov	r0, r4
-	ret
-FUNC_END negsi2
-#endif /* L_negsi2 */
-
-#ifdef L_one_cmplsi2
-FUNC_START one_cmplsi2
-	ldi:8	#0xff, r0
-	extsb	r0
-	eor	r0, r4
-	ret
-FUNC_END one_cmplsi2
-#endif /* L_one_cmplsi2 */
-
-
diff --git a/gcc/config/fr30/t-fr30 b/gcc/config/fr30/t-fr30
deleted file mode 100755
index 46387d8..0000000
--- a/gcc/config/fr30/t-fr30
+++ /dev/null
@@ -1,47 +0,0 @@
-
-# Name of assembly file containing libgcc1 functions.
-# This entry must be present, but it can be empty if the target does
-# not need any assembler functions to support its code generation.
-# CROSS_LIBGCC1 =
-#
-# Alternatively if assembler functions *are* needed then define the
-# entries below:
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC    = fr30/lib1funcs.asm
-LIB1ASMFUNCS  = _udivsi3 _divsi3 _umodsi3 _modsi3
-
-# Assemble startup files.
-crti.o: $(srcdir)/config/fr30/crti.asm $(GCC_PASSES)
-	$(GCC_FOR_TARGET) -c -o crti.o -x assembler $(srcdir)/config/fr30/crti.asm
-
-crtn.o: $(srcdir)/config/fr30/crtn.asm $(GCC_PASSES)
-	$(GCC_FOR_TARGET) -c -o crtn.o -x assembler $(srcdir)/config/fr30/crtn.asm
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-# If any special flags are necessary when building libgcc2 put them here.
-#
-# TARGET_LIBGCC2_CFLAGS
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-# Enable the following if multilibs are needed.
-# See gcc/genmultilib, gcc/gcc.texi and gcc/tm.texi for a
-# description of the options and their values.
-#
-# MULTILIB_OPTIONS    = 
-# MULTILIB_DIRNAMES   = 
-# MULTILIB_MATCHES    =
-# MULTILIB_EXCEPTIONS =
-# MULTILIB_EXTRA_OPTS = 
-#
-# LIBGCC = stmp-multilib
-# INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/fr30/xm-fr30.h b/gcc/config/fr30/xm-fr30.h
deleted file mode 100755
index 6b1f650..0000000
--- a/gcc/config/fr30/xm-fr30.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* CYGNUS LOCAL -- nickc/entire file */
-/* Definitions of FR30 target.
-   Copyright (C) 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Solutions.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define	FALSE	0
-#define	TRUE	1
-
-/* A C expression for the status code to be returned when the compiler exits
-   after serious errors.  */
-#define FATAL_EXIT_CODE 33
-
-/* A C expression for the status code to be returned when the compiler exits
-   without serious errors.  */
-#define SUCCESS_EXIT_CODE 0
-
-/* Defined if the host machine stores words of multi-word values in big-endian
-   order.  (GNU CC does not depend on the host byte ordering within a word.)  */
-/* #define HOST_WORDS_BIG_ENDIAN 1 */
-
-/* In addition, configuration files for system V define `bcopy', `bzero' and
-   `bcmp' as aliases.  Some files define `alloca' as a macro when compiled with
-   GNU CC, in order to take advantage of the benefit of GNU CC's built-in
-   `alloca'.  */
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* end of xm-fr30.h */
-/* END CYGNUS LOCAL -- nickc */
diff --git a/gcc/config/fx80/fx80.c b/gcc/config/fx80/fx80.c
deleted file mode 100755
index 4e8f420..0000000
--- a/gcc/config/fx80/fx80.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/* Subroutines for insn-output.c for Alliant FX computers.
-   Copyright (C) 1989, 1991, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Some output-actions in alliant.md need these.  */
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-
-/* Index into this array by (register number >> 3) to find the
-   smallest class which contains that register.  */
-enum reg_class regno_reg_class[]
-  = { DATA_REGS, ADDR_REGS, FP_REGS };
-
-static rtx find_addr_reg ();
-
-char *
-output_btst (operands, countop, dataop, insn, signpos)
-     rtx *operands;
-     rtx countop, dataop;
-     rtx insn;
-     int signpos;
-{
-  operands[0] = countop;
-  operands[1] = dataop;
-
-  if (GET_CODE (countop) == CONST_INT)
-    {
-      register int count = INTVAL (countop);
-      /* If COUNT is bigger than size of storage unit in use,
-	 advance to the containing unit of same size.  */
-      if (count > signpos)
-	{
-	  int offset = (count & ~signpos) / 8;
-	  count = count & signpos;
-	  operands[1] = dataop = adj_offsettable_operand (dataop, offset);
-	}
-      if (count == signpos)
-	cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
-      else
-	cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
-
-      /* These three statements used to use next_insns_test_no...
-	 but it appears that this should do the same job.  */
-      if (count == 31
-	  && next_insn_tests_no_inequality (insn))
-	return "tst%.l %1";
-      if (count == 15
-	  && next_insn_tests_no_inequality (insn))
-	return "tst%.w %1";
-      if (count == 7
-	  && next_insn_tests_no_inequality (insn))
-	return "tst%.b %1";
-
-      cc_status.flags = CC_NOT_NEGATIVE;
-    }
-  return "btst %0,%1";
-}
-
-/* Return the best assembler insn template
-   for moving operands[1] into operands[0] as a fullword.  */
-
-static char *
-singlemove_string (operands)
-     rtx *operands;
-{
-  if (operands[1] != const0_rtx)
-    return "mov%.l %1,%0";
-  if (! ADDRESS_REG_P (operands[0]))
-    return "clr%.l %0";
-  return "sub%.l %0,%0";
-}
-
-/* Output assembler code to perform a doubleword move insn
-   with operands OPERANDS.  */
-
-char *
-output_move_double (operands)
-     rtx *operands;
-{
-  enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
-  rtx latehalf[2];
-  rtx addreg0 = 0, addreg1 = 0;
-
-  /* First classify both operands.  */
-
-  if (REG_P (operands[0]))
-    optype0 = REGOP;
-  else if (offsettable_memref_p (operands[0]))
-    optype0 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    optype0 = POPOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    optype0 = PUSHOP;
-  else if (GET_CODE (operands[0]) == MEM)
-    optype0 = MEMOP;
-  else
-    optype0 = RNDOP;
-
-  if (REG_P (operands[1]))
-    optype1 = REGOP;
-  else if (CONSTANT_P (operands[1]))
-    optype1 = CNSTOP;
-  else if (offsettable_memref_p (operands[1]))
-    optype1 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
-    optype1 = POPOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
-    optype1 = PUSHOP;
-  else if (GET_CODE (operands[1]) == MEM)
-    optype1 = MEMOP;
-  else
-    optype1 = RNDOP;
-
-  /* Check for the cases that the operand constraints are not
-     supposed to allow to happen.  Abort if we get one,
-     because generating code for these cases is painful.  */
-
-  if (optype0 == RNDOP || optype1 == RNDOP)
-    abort ();
-
-  /* If one operand is decrementing and one is incrementing
-     decrement the former register explicitly
-     and change that operand into ordinary indexing.  */
-
-  if (optype0 == PUSHOP && optype1 == POPOP)
-    {
-      operands[0] = XEXP (XEXP (operands[0], 0), 0);
-      output_asm_insn ("subq%.l %#8,%0", operands);
-      operands[0] = gen_rtx (MEM, DImode, operands[0]);
-      optype0 = OFFSOP;
-    }
-  if (optype0 == POPOP && optype1 == PUSHOP)
-    {
-      operands[1] = XEXP (XEXP (operands[1], 0), 0);
-      output_asm_insn ("subq%.l %#8,%1", operands);
-      operands[1] = gen_rtx (MEM, DImode, operands[1]);
-      optype1 = OFFSOP;
-    }
-
-  /* If an operand is an unoffsettable memory ref, find a register
-     we can increment temporarily to make it refer to the second word.  */
-
-  if (optype0 == MEMOP)
-    addreg0 = find_addr_reg (XEXP (operands[0], 0));
-
-  if (optype1 == MEMOP)
-    addreg1 = find_addr_reg (XEXP (operands[1], 0));
-
-  /* Ok, we can do one word at a time.
-     Normally we do the low-numbered word first,
-     but if either operand is autodecrementing then we
-     do the high-numbered word first.
-
-     In either case, set up in LATEHALF the operands to use
-     for the high-numbered word and in some cases alter the
-     operands in OPERANDS to be suitable for the low-numbered word.  */
-
-  if (optype0 == REGOP)
-    latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  else if (optype0 == OFFSOP)
-    latehalf[0] = adj_offsettable_operand (operands[0], 4);
-  else
-    latehalf[0] = operands[0];
-
-  if (optype1 == REGOP)
-    latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-  else if (optype1 == OFFSOP)
-    latehalf[1] = adj_offsettable_operand (operands[1], 4);
-  else if (optype1 == CNSTOP)
-    {
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	split_double (operands[1], &operands[1], &latehalf[1]);
-      else if (CONSTANT_P (operands[1]))
-	{
-	  latehalf[1] = operands[1];
-	  operands[1] = const0_rtx;
-	}
-    }
-  else
-    latehalf[1] = operands[1];
-
-  /* If insn is effectively movd N(sp),-(sp) then we will do the
-     high word first.  We should use the adjusted operand 1 (which is N+4(sp))
-     for the low word as well, to compensate for the first decrement of sp.  */
-  if (optype0 == PUSHOP
-      && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
-      && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
-    operands[1] = latehalf[1];
-
-  /* If one or both operands autodecrementing,
-     do the two words, high-numbered first.  */
-
-  /* Likewise,  the first move would clobber the source of the second one,
-     do them in the other order.  This happens only for registers;
-     such overlap can't happen in memory unless the user explicitly
-     sets it up, and that is an undefined circumstance.  */
-
-  if (optype0 == PUSHOP || optype1 == PUSHOP
-      || (optype0 == REGOP && optype1 == REGOP
-	  && REGNO (operands[0]) == REGNO (latehalf[1])))
-    {
-      /* Make any unoffsettable addresses point at high-numbered word.  */
-      if (addreg0)
-	output_asm_insn ("addql %#4,%0", &addreg0);
-      if (addreg1)
-	output_asm_insn ("addql %#4,%0", &addreg1);
-
-      /* Do that word.  */
-      output_asm_insn (singlemove_string (latehalf), latehalf);
-
-      /* Undo the adds we just did.  */
-      if (addreg0)
-	output_asm_insn ("subql %#4,%0", &addreg0);
-      if (addreg1)
-	output_asm_insn ("subql %#4,%0", &addreg1);
-
-      /* Do low-numbered word.  */
-      return singlemove_string (operands);
-    }
-
-  /* Normal case: do the two words, low-numbered first.  */
-
-  output_asm_insn (singlemove_string (operands), operands);
-
-  /* Make any unoffsettable addresses point at high-numbered word.  */
-  if (addreg0)
-    output_asm_insn ("addql %#4,%0", &addreg0);
-  if (addreg1)
-    output_asm_insn ("addql %#4,%0", &addreg1);
-
-  /* Do that word.  */
-  output_asm_insn (singlemove_string (latehalf), latehalf);
-
-  /* Undo the adds we just did.  */
-  if (addreg0)
-    output_asm_insn ("subql %#4,%0", &addreg0);
-  if (addreg1)
-    output_asm_insn ("subql %#4,%0", &addreg1);
-
-  return "";
-}
-
-/* Return a REG that occurs in ADDR with coefficient 1.
-   ADDR can be effectively incremented by incrementing REG.  */
-
-static rtx
-find_addr_reg (addr)
-     rtx addr;
-{
-  while (GET_CODE (addr) == PLUS)
-    {
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-	addr = XEXP (addr, 0);
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	addr = XEXP (addr, 1);
-      else if (CONSTANT_P (XEXP (addr, 0)))
-	addr = XEXP (addr, 1);
-      else if (CONSTANT_P (XEXP (addr, 1)))
-	addr = XEXP (addr, 0);
-      else
-	abort ();
-    }
-  if (GET_CODE (addr) == REG)
-    return addr;
-  abort ();
-}
-
-int
-standard_SunFPA_constant_p (x)
-     rtx x;
-{
-  return( 0 );
-}
-
diff --git a/gcc/config/fx80/fx80.h b/gcc/config/fx80/fx80.h
deleted file mode 100755
index 651d13d..0000000
--- a/gcc/config/fx80/fx80.h
+++ /dev/null
@@ -1,1446 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Alliant FX version.
-   Copyright (C) 1989, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
-   Adapted from m68k.h by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu)
-   and Joe Weening (weening@gang-of-four.stanford.edu).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* This file is based on m68k.h, simplified by removing support for
-   the Sun FPA and other things not applicable to the Alliant.  Some
-   remnants of these features remain.  */
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dmc68000 -Dalliant -Dunix -Asystem(unix) -Acpu(m68k) -Amachine(m68k)"
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fprintf (stderr, " (Alliant)");
-
-/* Run-time compilation parameters selecting different hardware
-   subsets.  The Alliant IP is an mc68020.  (Older mc68010-based IPs
-   are no longer supported.)  The Alliant CE is 68020-compatible, and
-   also has floating point, vector and concurrency instructions.
-
-   Although the IP doesn't have floating point, it emulates it in the
-   operating system.  Using this generally is faster than running code
-   compiled with -msoft-float, because the soft-float code still uses
-   (simulated) FP registers and ends up emulating several fmove{s,d}
-   instructions per call.  So I don't recommend using soft-float for
-   any Alliant code.  -- JSW
-*/
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Compile for a 68020 (not a 68000 or 68010).  */
-#define TARGET_68020 (target_flags & 1)
-/* Compile CE insns for floating point (not library calls).  */
-#define TARGET_CE (target_flags & 2)
-/* Compile using 68020 bitfield insns.  */
-#define TARGET_BITFIELD (target_flags & 4)
-/* Compile with 16-bit `int'.  */
-#define TARGET_SHORT (target_flags & 040)
-
-/* Default 3 means compile 68020 and CE instructions.  We don't use
-   bitfield instructions because there appears to be a bug in the
-   implementation of bfins on the CE.  */
-
-#define TARGET_DEFAULT 3
-
-/* Define __HAVE_CE__ in preprocessor according to the -m flags.
-   This will control the use of inline FP insns in certain macros.
-   Also inform the program which CPU this is for.  */
-
-#if TARGET_DEFAULT & 02
-
-/* -mce is the default */
-#define CPP_SPEC \
-"%{!msoft-float:-D__HAVE_CE__ }\
-%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
-
-#else
-
-/* -msoft-float is the default */
-#define CPP_SPEC \
-"%{mce:-D__HAVE_CE__ }\
-%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
-
-#endif
-
-/* Link with libg.a when debugging, for dbx's sake.  */
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
-
-/* Make the linker remove temporary labels, since the Alliant assembler
-   doesn't.  */
-
-#define LINK_SPEC "-X"
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  { { "68020", 5},				\
-    { "c68020", 5},				\
-    { "bitfield", 4},				\
-    { "68000", -7},				\
-    { "c68000", -7},				\
-    { "soft-float", -2},			\
-    { "nobitfield", -4},			\
-    { "short", 040},				\
-    { "noshort", -040},				\
-    { "", TARGET_DEFAULT}}
-
-/* target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is true for 68020 insns such as bfins and bfexts.
-   We make it true always by avoiding using the single-bit insns
-   except in special cases with constant bit numbers.  */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is true on the 68000.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.  */
-/* For 68000 we can decide arbitrarily
-   since there are no machine instructions for them.  */
-#define WORDS_BIG_ENDIAN 0
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 16
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 16
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 16
-
-/* Set this non-zero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Define number of bits in most basic integer type.
-   (If undefined, default is BITS_PER_WORD).  */
-
-#define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
-
-/* Define these to avoid dependence on meaning of `int'.
-   Note that WCHAR_TYPE_SIZE is used in cexp.y,
-   where TARGET_SHORT is not available.  */
-
-#define WCHAR_TYPE "long int"
-#define WCHAR_TYPE_SIZE 32
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-   For the Alliant, we give the data registers numbers 0-7,
-   the address registers numbers 010-017,
-   and the floating point registers numbers 020-027.  */
-#define FIRST_PSEUDO_REGISTER 24
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   On the Alliant, these are a0 (argument pointer),
-   a6 (frame pointer) and a7 (stack pointer).  */
-#define FIXED_REGISTERS  \
- {0, 0, 0, 0, 0, 0, 0, 0, \
-  1, 0, 0, 0, 0, 0, 1, 1, \
-  0, 0, 0, 0, 0, 0, 0, 0  }
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.
-   The Alliant calling sequence allows a function to use any register,
-   so we include them all here.  */
-
-#define CALL_USED_REGISTERS \
- {1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1  }
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On the Alliant, ordinary registers hold 32 bits worth;
-   for the FP registers, a single register is always enough for
-   any floating-point value.  */
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE)	\
-   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On the Alliant, the cpu registers can hold any mode but the FP registers
-   can hold only floating point.  */
-#define HARD_REGNO_MODE_OK(REGNO, MODE)		\
-  ((REGNO) < 16 || GET_MODE_CLASS (MODE) == MODE_FLOAT	\
-   || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2)			\
-   (((MODE1) == SFmode || (MODE1) == DFmode		\
-     || (MODE1) == SCmode || (MODE1) == DCmode)		\
-       == ((MODE2) == SFmode || (MODE2) == DFmode	\
-	   || (MODE2) == SCmode || (MODE2) == DCmode))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* m68000 pc isn't overloaded on a register.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 15
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 14
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-/* Set for now on Alliant until we find a way to make this work with
-   their calling sequence.  */
-#define FRAME_POINTER_REQUIRED 1
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM  8 
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 10
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 9
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-/* The Alliant has three kinds of registers, so eight classes would be
-   a complete set.  One of them is not needed.  */
-
-enum reg_class { NO_REGS, FP_REGS, DATA_REGS, DATA_OR_FP_REGS,
-  ADDR_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- { "NO_REGS", "FP_REGS", "DATA_REGS", "DATA_OR_FP_REGS",  \
-   "ADDR_REGS", "GENERAL_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS \
-{					\
- 0,		/* NO_REGS */		\
- 0x00ff0000,	/* FP_REGS */		\
- 0x000000ff,	/* DATA_REGS */		\
- 0x00ff00ff,	/* DATA_OR_FP_REGS */	\
- 0x0000ff00,	/* ADDR_REGS */		\
- 0x0000ffff,	/* GENERAL_REGS */	\
- 0x00ffffff	/* ALL_REGS */		\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-extern enum reg_class regno_reg_class[];
-#define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS ADDR_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'a' ? ADDR_REGS :			\
-   ((C) == 'd' ? DATA_REGS :			\
-    ((C) == 'f' ? FP_REGS :			\
-     NO_REGS)))
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   For the 68000, `I' is used for the range 1 to 8
-   allowed as immediate shift counts and in addq.
-   `J' is used for the range of signed numbers that fit in 16 bits.
-   `K' is for numbers that moveq can't handle.
-   `L' is for range -8 to -1, range of values that can be added with subq.  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 :    \
-   (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF :	\
-   (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 :	\
-   (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0)
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  0
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.
-   On the 68000 series, use a data reg if possible when the
-   value is a constant in the range where moveq could be used
-   and we ensure that QImodes are reloaded into data regs.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)  \
-  ((GET_CODE (X) == CONST_INT			\
-    && (unsigned) (INTVAL (X) + 0x80) < 0x100	\
-    && (CLASS) != ADDR_REGS)			\
-   ? DATA_REGS					\
-   : GET_MODE (X) == QImode			\
-   ? DATA_REGS					\
-   : (CLASS))
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-/* On the 68000, this is the size of MODE in words,
-   except in the FP regs, where a single reg is always enough.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- ((CLASS) == FP_REGS ? 1 \
-  : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Moves between fp regs and other regs are two insns.  */
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)		\
-  ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS)	\
-    || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS))	\
-   ? 4 : 2)
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* The Alliant uses -fcaller-saves by default.  */
-#define DEFAULT_CALLER_SAVES
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET -4
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On the 68000, sp@- in a byte insn really pushes a word.  */
-#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack. 
-
-   On the Alliant we define this as SIZE and make the calling sequence
-   (in alliant.md) pop the args.  This wouldn't be necessary if we
-   could add to the pending stack adjustment the size of the argument
-   descriptors that are pushed after the arguments.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-/* On the Alliant the return value is in FP0 if real, else D0.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  (TREE_CODE (VALTYPE) == REAL_TYPE \
-   ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
-   : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-/* On the Alliant the return value is in FP0 if real, else D0.  The
-   Alliant library functions for floating-point emulation return their
-   values both in FP0 and in D0/D1.  But since not all libgcc functions
-   return the results of these directly, we cannot assume that D0/D1
-   contain the values we expect on return from a libgcc function.  */
-
-#define LIBCALL_VALUE(MODE)  \
-  (((MODE) == DFmode || (MODE) == SFmode) \
-   ? gen_rtx (REG, MODE, 16) \
-   : gen_rtx (REG, MODE, 0))
-
-/* 1 if N is a possible register number for a function value.
-   On the Alliant, D0 and FP0 are the only registers thus used.
-   (No need to mention D1 when used as a pair with D0.)  */
-
-#define FUNCTION_VALUE_REGNO_P(N) (((N) & ~16) == 0)
-
-/* Define this if PCC uses the nonreentrant convention for returning
-   structure and union values.  */
-
-#define PCC_STATIC_STRUCT_RETURN
-
-/* 1 if N is a possible register number for function argument passing.
-   On the Alliant, no registers are used in this way.  */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the Alliant, this is a single integer, which is a number of bytes
-   of arguments scanned so far.  */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the Alliant, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM) += ((MODE) != BLKmode			\
-	    ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
-	    : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On the Alliant all args are pushed.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.
-   The Alliant uses caller-saves, so this macro is very simple.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)     \
-{ int fsize = ((SIZE) - STARTING_FRAME_OFFSET + 3) & -4;	\
-  if (frame_pointer_needed)					\
-    {								\
-      if (fsize < 0x8000)					\
-	fprintf(FILE,"\tlinkw a6,#%d\n", -fsize);		\
-      else if (TARGET_68020)					\
-	fprintf(FILE,"\tlinkl a6,#%d\n", -fsize);		\
-      else							\
-	fprintf(FILE,"\tlinkw a6,#0\n\tsubl #%d,sp\n", fsize);  \
-      fprintf(FILE, "\tmovl a0,a6@(-4)\n" ); }}
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\tjbsr __mcount_\n")
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-{ if (frame_pointer_needed)					\
-    fprintf (FILE, "\tunlk a6\n");				\
-  fprintf (FILE, "\trts\n"); }
-
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved.  */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)			\
-{								\
-  int regno;							\
-  int offset = -4;						\
-  for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++)	\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      offset += 12;						\
-  for (regno = 0; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      offset += 4;						\
-  (DEPTH) = offset - ((get_frame_size () + 3) & -4);		\
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-#define HAVE_POST_INCREMENT 1
-/* #define HAVE_POST_DECREMENT 0 */
-
-#define HAVE_PRE_DECREMENT 1
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-(((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
-#define REGNO_OK_FOR_DATA_P(REGNO) \
-((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
-#define REGNO_OK_FOR_FP_P(REGNO) \
-(((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
-
-/* Now macros that check whether X is a register and also,
-   strictly, whether it is in a specified class.
-
-   These macros are specific to the 68000, and may be used only
-   in code for printing assembler insns and in conditions for
-   define_optimization.  */
-
-/* 1 if X is a data register.  */
-
-#define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
-
-/* 1 if X is an fp register.  */
-
-#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
-
-/* 1 if X is an address register  */
-
-#define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-/* Alliant FP instructions don't take immediate operands, so this
-   forces them into memory.  */
-#define LEGITIMATE_CONSTANT_P(X) (GET_CODE (X) != CONST_DOUBLE)
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS.  */
-
-#define INDIRECTABLE_1_ADDRESS_P(X)  \
-  (CONSTANT_ADDRESS_P (X)						\
-   || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
-   || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC)		\
-       && REG_P (XEXP (X, 0))						\
-       && REG_OK_FOR_BASE_P (XEXP (X, 0)))				\
-   || (GET_CODE (X) == PLUS						\
-       && REG_P (XEXP (X, 0)) && REG_OK_FOR_BASE_P (XEXP (X, 0))	\
-       && GET_CODE (XEXP (X, 1)) == CONST_INT				\
-       && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000))
-
-#define GO_IF_NONINDEXED_ADDRESS(X, ADDR)  \
-{ if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
-
-#define GO_IF_INDEXABLE_BASE(X, ADDR)	\
-{ if (GET_CODE (X) == LABEL_REF) goto ADDR;				\
-  if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; }
-
-#define GO_IF_INDEXING(X, ADDR)	\
-{ if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0)))		\
-    { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); }			\
-  if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1)))		\
-    { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
-
-#define GO_IF_INDEXED_ADDRESS(X, ADDR)	 \
-{ GO_IF_INDEXING (X, ADDR);						\
-  if (GET_CODE (X) == PLUS)						\
-    { if (GET_CODE (XEXP (X, 1)) == CONST_INT				\
-	  && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)		\
-	{ rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); }	\
-      if (GET_CODE (XEXP (X, 0)) == CONST_INT				\
-	  && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)		\
-	{ rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
-
-#define LEGITIMATE_INDEX_REG_P(X)   \
-  ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))	\
-   || (GET_CODE (X) == SIGN_EXTEND			\
-       && GET_CODE (XEXP (X, 0)) == REG			\
-       && GET_MODE (XEXP (X, 0)) == HImode		\
-       && REG_OK_FOR_INDEX_P (XEXP (X, 0))))
-
-#define LEGITIMATE_INDEX_P(X)   \
-   (LEGITIMATE_INDEX_REG_P (X)				\
-    || (TARGET_68020 && GET_CODE (X) == MULT		\
-	&& LEGITIMATE_INDEX_REG_P (XEXP (X, 0))		\
-	&& GET_CODE (XEXP (X, 1)) == CONST_INT		\
-	&& (INTVAL (XEXP (X, 1)) == 2			\
-	    || INTVAL (XEXP (X, 1)) == 4		\
-	    || INTVAL (XEXP (X, 1)) == 8)))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
-{ GO_IF_NONINDEXED_ADDRESS (X, ADDR);			\
-  GO_IF_INDEXED_ADDRESS (X, ADDR); }
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the 68000, we handle X+REG by loading X into a register R and
-   using R+REG.  R will go in an address reg and indexing will be used.
-   However, if REG is a broken-out memory address or multiplication,
-   nothing needs to be done because REG can certainly go in an address reg.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)   \
-{ register int ch = (X) != (OLDX);					\
-  if (GET_CODE (X) == PLUS)						\
-    { if (GET_CODE (XEXP (X, 0)) == MULT)				\
-	ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0);		\
-      if (GET_CODE (XEXP (X, 1)) == MULT)				\
-	ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0);		\
-      if (ch && GET_CODE (XEXP (X, 1)) == REG				\
-	  && GET_CODE (XEXP (X, 0)) == REG)				\
-	goto WIN;							\
-      if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); }		\
-      if (GET_CODE (XEXP (X, 0)) == REG					\
-	       || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND		\
-		   && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG		\
-		   && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode))	\
-	{ register rtx temp = gen_reg_rtx (Pmode);			\
-	  register rtx val = force_operand (XEXP (X, 1), 0);		\
-	  emit_move_insn (temp, val);					\
-	  XEXP (X, 1) = temp;						\
-	  goto WIN; }							\
-      else if (GET_CODE (XEXP (X, 1)) == REG				\
-	       || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND		\
-		   && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG		\
-		   && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode))	\
-	{ register rtx temp = gen_reg_rtx (Pmode);			\
-	  register rtx val = force_operand (XEXP (X, 0), 0);		\
-	  emit_move_insn (temp, val);					\
-	  XEXP (X, 0) = temp;						\
-	  goto WIN; }}}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the 68000, only predecrement and postincrement address depend thus
-   (the amount of decrement or increment being the length of the operand).  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
- if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE HImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE 1
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 4
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-#define SLOW_ZERO_EXTEND
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
-   few bits. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE -1
-
-/* When a prototype says `char' or `short', really pass an `int'.  */
-#define PROMOTE_PROTOTYPES
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    /* Constant zero is super cheap due to clr instruction.  */	\
-    if (RTX == const0_rtx) return 0;				\
-    if ((unsigned) INTVAL (RTX) < 077) return 1;		\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 3;							\
-  case CONST_DOUBLE:						\
-    return 5;
-
-/* Check a `double' value for validity for a particular machine mode.
-   This is defined to avoid crashes outputting certain constants.  */
-
-#define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW)				\
-  if (OVERFLOW)								\
-    (D) = 3.4028234663852890e+38;					\
-  else if ((MODE) == SFmode)						\
-    { 									\
-      if ((d) > 3.4028234663852890e+38)					\
-	(OVERFLOW) = 1, (D) = 3.4028234663852890e+38;			\
-      else if ((D) < -3.4028234663852890e+38)				\
-	(OVERFLOW) = 1, (D) = -3.4028234663852890e+38;			\
-      else if (((D) > 0) && ((D) < 1.1754943508222873e-38))		\
-	(OVERFLOW) = 1, (D) = 0.0;					\
-      else if (((d) < 0) && ((d) > -1.1754943508222873e-38))		\
-	(OVERFLOW) = 1, (D) = 0.0;					\
-    }
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  */
-
-/* On the Alliant, floating-point instructions do not modify the
-   ordinary CC register.  Only fcmp and ftest instructions modify the
-   floating-point CC register.  We should actually keep track of what
-   both kinds of CC registers contain, but for now we only consider
-   the most recent instruction that has set either register.  */
-
-/* Set if the cc value came from a floating point test, so a floating
-   point conditional branch must be output.  */
-#define CC_IN_FP 04000
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-/* On the 68000, all the insns to store in an address register
-   fail to set the cc's.  However, in some cases these instructions
-   can make it possibly invalid to use the saved cc's.  In those
-   cases we clear out some or all of the saved cc's so they won't be used.  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-{								\
-  if (GET_CODE (EXP) == SET)					\
-    { if (ADDRESS_REG_P (SET_DEST (EXP)) || FP_REG_P (SET_DEST (EXP)))	    \
-	{ if (cc_status.value1					\
-	      && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value1)) \
-	    cc_status.value1 = 0;				\
-	  if (cc_status.value2					\
-	      && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value2)) \
-	    cc_status.value2 = 0; }				\
-      else if (GET_CODE (SET_SRC (EXP)) == MOD			\
-	       || GET_CODE (SET_SRC (EXP)) == UMOD		\
-	       || (GET_CODE (SET_SRC (EXP)) == TRUNCATE		\
-		   && (GET_CODE (XEXP (SET_SRC (EXP))) == MOD	\
-		       || GET_CODE (XEXP (SET_SRC (EXP))) == UMOD)))	\
-	/* The swap insn produces cc's that don't correspond to the 	\
-	   result.  */						\
-        CC_STATUS_INIT;						\
-      else if (SET_DEST (EXP) != cc0_rtx				\
-	       && (FP_REG_P (SET_SRC (EXP))			\
-		   || GET_CODE (SET_SRC (EXP)) == FIX		\
-		   || GET_CODE (SET_SRC (EXP)) == FLOAT_TRUNCATE \
-		   || GET_CODE (SET_SRC (EXP)) == FLOAT_EXTEND)) \
-	{ CC_STATUS_INIT; }					\
-      /* A pair of move insns doesn't produce a useful overall cc.  */ \
-      else if (!FP_REG_P (SET_DEST (EXP))			\
-	       && !FP_REG_P (SET_SRC (EXP))			\
-	       && GET_MODE_SIZE (GET_MODE (SET_SRC (EXP))) > 4	\
-	       && (GET_CODE (SET_SRC (EXP)) == REG		\
-		   || GET_CODE (SET_SRC (EXP)) == MEM		\
-		   || GET_CODE (SET_SRC (EXP)) == CONST_DOUBLE))\
-	{ CC_STATUS_INIT; }					\
-      else if (GET_CODE (SET_SRC (EXP)) == CALL)		\
-	{ CC_STATUS_INIT; }					\
-      else if (XEXP (EXP, 0) != pc_rtx)				\
-	{ cc_status.flags = 0;					\
-	  cc_status.value1 = XEXP (EXP, 0);			\
-	  cc_status.value2 = XEXP (EXP, 1); } }			\
-  else if (GET_CODE (EXP) == PARALLEL				\
-	   && GET_CODE (XVECEXP (EXP, 0, 0)) == SET)		\
-    {								\
-      if (ADDRESS_REG_P (XEXP (XVECEXP (EXP, 0, 0), 0)))	\
-	CC_STATUS_INIT;						\
-      else if (XEXP (XVECEXP (EXP, 0, 0), 0) != pc_rtx)		\
-	{ cc_status.flags = 0;					\
-	  cc_status.value1 = XEXP (XVECEXP (EXP, 0, 0), 0);	\
-	  cc_status.value2 = XEXP (XVECEXP (EXP, 0, 0), 1); } }	\
-  else CC_STATUS_INIT;						\
-  if (cc_status.value2 != 0					\
-      && ADDRESS_REG_P (cc_status.value2)			\
-      && GET_MODE (cc_status.value2) == QImode)			\
-    CC_STATUS_INIT;						\
-  if (cc_status.value2 != 0)					\
-    switch (GET_CODE (cc_status.value2))			\
-      { case PLUS: case MINUS: case MULT:			\
-	case DIV: case UDIV: case MOD: case UMOD: case NEG:	\
-	case ASHIFT:  case ASHIFTRT: case LSHIFTRT:		\
-	case ROTATE: case ROTATERT:				\
-	  if (GET_MODE (cc_status.value2) != VOIDmode)		\
-	    cc_status.flags |= CC_NO_OVERFLOW;			\
-	  break;						\
-	case ZERO_EXTEND:					\
-	  /* (SET r1 (ZERO_EXTEND r2)) on this machine
-	     ends with a move insn moving r2 in r2's mode.
-	     Thus, the cc's are set for r2.
-	     This can set N bit spuriously. */			\
-	  cc_status.flags |= CC_NOT_NEGATIVE; }			\
-  if (cc_status.value1 && GET_CODE (cc_status.value1) == REG	\
-      && cc_status.value2					\
-      && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))	\
-    cc_status.value2 = 0;					\
-  if ((cc_status.value1 && FP_REG_P (cc_status.value1))		\
-       || (cc_status.value2 && FP_REG_P (cc_status.value2)))	\
-    cc_status.flags = CC_IN_FP; }
-
-#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV)  \
-{ if (cc_prev_status.flags & CC_IN_FP)			\
-    return FLOAT;						\
-  if (cc_prev_status.flags & CC_NO_OVERFLOW)			\
-    return NO_OV;						\
-  return NORMAL; }
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(FILE)	\
-  fprintf (FILE, "#NO_APP\n");
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",	\
- "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",	\
- "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
-
-/* How to renumber registers for dbx and gdb.
-   On the Sun-3, the floating point registers have numbers
-   18 to 25, not 16 to 23 as they do in the compiler.  */
-/* (On the Alliant, dbx isn't working yet at all.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-do { union { double d; long v[2];} tem;			\
-     tem.d = (VALUE);					\
-     fprintf (FILE, "\t.long 0x%x,0x%x\n", tem.v[0], tem.v[1]);	\
-   } while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-do { union { float f; long l;} tem;			\
-     tem.f = (VALUE);					\
-     fprintf (FILE, "\t.long 0x%x\n", tem.l);	\
-   } while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_ASCII(FILE,PTR,SIZE)               \
-do { int i; unsigned char *pp = (unsigned char *) (PTR);	\
-  fprintf((FILE), "\t.byte %d", (unsigned int)*pp++);		\
-  for (i = 1; i < (SIZE); ++i, ++pp) {				\
-    if ((i % 8) == 0)						\
-      fprintf((FILE), "\n\t.byte %d", (unsigned int) *pp);	\
-    else							\
-      fprintf((FILE), ",%d", (unsigned int) *pp); }		\
-  fprintf ((FILE), "\n");       } while (0)
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tmovl %s,sp@-\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tmovl sp@+,%s\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute.
-   (The 68000 does not use such vectors,
-   but we must define this macro anyway.)  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.long L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) == 1)			\
-    fprintf (FILE, "\t.even\n");	\
-  else if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %dn", (LOG));	
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t. = . + %u\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\t.comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\t.lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.
-
-   On the Alliant, we use several CODE characters:
-   '.' for dot needed in Motorola-style opcode names.
-   '-' for an operand pushing on the stack:
-       sp@-, -(sp) or -(%sp) depending on the style of syntax.
-   '+' for an operand pushing on the stack:
-       sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
-   '@' for a reference to the top word on the stack:
-       sp@, (sp) or (%sp) depending on the style of syntax.
-   '#' for an immediate operand prefix (# in MIT and Motorola syntax
-       but & in SGS syntax).
-   '!' for the cc register (used in an `and to cc' insn).
-
-   'b' for byte insn (no effect, on the Sun; this is for the ISI).
-   'd' to force memory addressing to be absolute, not relative.
-   'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
-   'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
-       or print pair of registers as rx:ry.  */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)				\
-  ((CODE) == '.' || (CODE) == '#' || (CODE) == '-'			\
-   || (CODE) == '+' || (CODE) == '@' || (CODE) == '!')
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ int i;								\
-  if (CODE == '.') ;							\
-  else if (CODE == '#') fprintf (FILE, "#");				\
-  else if (CODE == '-') fprintf (FILE, "sp@-");				\
-  else if (CODE == '+') fprintf (FILE, "sp@+");				\
-  else if (CODE == '@') fprintf (FILE, "sp@");				\
-  else if (CODE == '!') fprintf (FILE, "cc");				\
-  else if ((X)  == 0  ) ;						\
-  else if (GET_CODE (X) == REG)						\
-    { if (REGNO (X) < 16 && (CODE == 'y' || CODE == 'x') && GET_MODE (X) == DFmode)	\
-        fprintf (FILE, "%s,%s", reg_names[REGNO (X)], reg_names[REGNO (X)+1]); \
-      else								\
-        fprintf (FILE, "%s", reg_names[REGNO (X)]);			\
-    }									\
-  else if (GET_CODE (X) == MEM)						\
-    {									\
-      output_address (XEXP (X, 0));					\
-      if (CODE == 'd' && ! TARGET_68020					\
-	  && CONSTANT_ADDRESS_P (XEXP (X, 0))				\
-	  && !(GET_CODE (XEXP (X, 0)) == CONST_INT			\
-	       && INTVAL (XEXP (X, 0)) < 0x8000				\
-	       && INTVAL (XEXP (X, 0)) >= -0x8000))			\
-	fprintf (FILE, ":l");						\
-    }									\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode)	\
-    { union { double d; int i[2]; } u;					\
-      union { float f; int i; } u1;					\
-      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
-      u1.f = u.d;							\
-      if (CODE == 'f')							\
-        fprintf (FILE, "#0r%.9g", u1.f);				\
-      else								\
-        fprintf (FILE, "#0x%x", u1.i); }				\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)	\
-    { union { double d; int i[2]; } u;					\
-      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
-      fprintf (FILE, "#0r%.20g", u.d); }				\
-  else { putc ('#', FILE); output_addr_const (FILE, X); }}
-
-/* Note that this contains a kludge that knows that the only reason
-   we have an address (plus (label_ref...) (reg...))
-   is in the insn before a tablejump, and we know that m68k.md
-   generates a label LInnn: on such an insn.  */
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx reg1, reg2, breg, ireg;					\
-  register rtx addr = ADDR;						\
-  static char *sz = ".BW.L...D";					\
-  rtx offset;								\
-  switch (GET_CODE (addr))						\
-    {									\
-    case REG:								\
-      fprintf (FILE, "%s@", reg_names[REGNO (addr)]);			\
-      break;								\
-    case PRE_DEC:							\
-      fprintf (FILE, "%s@-", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case POST_INC:							\
-      fprintf (FILE, "%s@+", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case PLUS:								\
-      reg1 = 0;	reg2 = 0;						\
-      ireg = 0;	breg = 0;						\
-      offset = 0;							\
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))				\
-	{								\
-	  offset = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))			\
-	{								\
-	  offset = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) != PLUS) ;					\
-      else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT		\
-	  || GET_CODE (addr) == SIGN_EXTEND)				\
-	{ if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; }	\
-/*  for OLD_INDEXING							\
-      else if (GET_CODE (addr) == PLUS)					\
-	{								\
-	  if (GET_CODE (XEXP (addr, 0)) == REG)				\
-	    {								\
-	      reg2 = XEXP (addr, 0);					\
-	      addr = XEXP (addr, 1);					\
-	    }								\
-	  else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	    {								\
-	      reg2 = XEXP (addr, 1);					\
-	      addr = XEXP (addr, 0);					\
-	    }								\
-	}								\
-  */									\
-      if (offset != 0) { if (addr != 0) abort (); addr = offset; }	\
-      if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND			\
-		    || GET_CODE (reg1) == MULT))			\
-	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))		\
-	{ breg = reg2; ireg = reg1; }					\
-      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))		\
-	{ breg = reg1; ireg = reg2; }					\
-      if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { int scale = 1;						\
-	  if (GET_CODE (ireg) == MULT)					\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (GET_CODE (ireg) == SIGN_EXTEND)				\
-	    fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:W",			\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (XEXP (ireg, 0))]); 		\
-	  else								\
-	    fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L",			\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (ireg)]);				\
-	  fprintf (FILE, ":%c", sz[scale]);				\
-	  putc (']', FILE);						\
-	  break; }							\
-      if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]",			\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   reg_names[REGNO (breg)]);				\
-	  break; }							\
-      if (ireg != 0 || breg != 0)					\
-	{ int scale = 1;						\
-	  if (breg == 0)						\
-	    abort ();							\
-	  if (addr && GET_CODE (addr) == LABEL_REF) abort ();		\
-	  fprintf (FILE, "%s@", reg_names[REGNO (breg)]);		\
-	  if (addr != 0) {						\
-            putc( '(', FILE );						\
-	    output_addr_const (FILE, addr);				\
-            if (ireg != 0) {						\
-              if (GET_CODE(addr) == CONST_INT) {			\
-                int size_of = 1, val = INTVAL(addr);			\
-                if (val < -0x8000 || val >= 0x8000)			\
-                   size_of = 4;   					\
-                else if (val < -0x80 || val >= 0x80)			\
-                   size_of = 2;						\
-                fprintf(FILE, ":%c", sz[size_of]);			\
-              }        							\
-              else							\
-                fprintf(FILE, ":L"); } 					\
-            putc( ')', FILE ); }					\
-	  if (ireg != 0) {						\
-	    putc ('[', FILE);						\
-	    if (ireg != 0 && GET_CODE (ireg) == MULT)			\
-	      { scale = INTVAL (XEXP (ireg, 1));			\
-	        ireg = XEXP (ireg, 0); }				\
-	    if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)		\
-	      fprintf (FILE, "%s:W", reg_names[REGNO (XEXP (ireg, 0))]);	\
-	    else if (ireg != 0)						\
-	      fprintf (FILE, "%s:L", reg_names[REGNO (ireg)]);		\
-	    fprintf (FILE, ":%c", sz[scale]);				\
-	    putc (']', FILE);						\
-          }								\
-	  break;							\
-	}								\
-      else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF)		\
-	{ fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]",			\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   reg_names[REGNO (reg1)]);				\
-	  break; }							\
-    default:								\
-      if (GET_CODE (addr) == CONST_INT					\
-	  && INTVAL (addr) < 0x8000					\
-	  && INTVAL (addr) >= -0x8000)					\
-	fprintf (FILE, "%d:W", INTVAL (addr));				\
-      else								\
-        output_addr_const (FILE, addr);					\
-    }}
-
-/*
-Local variables:
-version-control: t
-End:
-*/
-
diff --git a/gcc/config/fx80/fx80.md b/gcc/config/fx80/fx80.md
deleted file mode 100755
index cec863b..0000000
--- a/gcc/config/fx80/fx80.md
+++ /dev/null
@@ -1,2516 +0,0 @@
-;;- Machine description for GNU C compiler for Alliant FX systems
-;;  Copyright (C) 1989, 1994, 1996 Free Software Foundation, Inc.
-;;  Adapted from m68k.md by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu)
-;;  and Joe Weening (weening@gang-of-four.stanford.edu).
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- instruction definitions
-
-;;- @@The original PO technology requires these to be ordered by speed,
-;;- @@    so that assigner will pick the fastest.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;;- When naming insn's (operand 0 of define_insn) be careful about using
-;;- names from other targets machine descriptions.
-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-;;- Operand classes for the register allocator:
-;;- 'a' one of the address registers can be used.
-;;- 'd' one of the data registers can be used.
-;;- 'f' one of the CE floating point registers can be used
-;;- 'r' either a data or an address register can be used.
-
-;;- Immediate integer operand constraints:
-;;- 'I'  1 .. 8
-;;- 'J'  -32768 .. 32767
-;;- 'K'  -128 .. 127
-;;- 'L'  -8 .. -1
-
-;;- Some remnants of constraint codes for the m68k ('x','y','G','H')
-;;- may remain in the insn definitions.
-
-;;- Some of these insn's are composites of several Alliant op codes.
-;;- The assembler (or final @@??) insures that the appropriate one is
-;;- selected.
-
-;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
-;; be folded while optimizing anyway.
-
-(define_insn "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "nonimmediate_operand" "rm"))]
-  ""
-  "*
-{
-  if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
-    return \"tst%.l %0\";
-  /* If you think that the 68020 does not support tstl a0,
-     reread page B-167 of the 68020 manual more carefully.  */
-  /* On an address reg, cmpw may replace cmpl.  */
-  return \"cmp%.w %#0,%0\";
-}")
-
-(define_insn "tsthi"
-  [(set (cc0)
-	(match_operand:HI 0 "nonimmediate_operand" "rm"))]
-  ""
-  "*
-{
-  if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
-    return \"tst%.w %0\";
-  return \"cmp%.w %#0,%0\";
-}")
-
-(define_insn "tstqi"
-  [(set (cc0)
-	(match_operand:QI 0 "nonimmediate_operand" "dm"))]
-  ""
-  "tst%.b %0")
-
-(define_insn "tstsf"
-  [(set (cc0)
-	(match_operand:SF 0 "nonimmediate_operand" "fm"))]
-  "TARGET_CE"
-  "*
-{
-  cc_status.flags = CC_IN_FP;
-  return \"ftest%.s %0\";
-}")
-
-(define_insn "tstdf"
-  [(set (cc0)
-	(match_operand:DF 0 "nonimmediate_operand" "fm"))]
-  "TARGET_CE"
-  "*
-{
-  cc_status.flags = CC_IN_FP;
-  return \"ftest%.d %0\";
-}")
-
-;; compare instructions.
-
-;; A composite of the cmp, cmpa, & cmpi m68000 op codes.
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
-		 (match_operand:SI 1 "general_operand" "mr,Ksr,>")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-    return \"cmpm%.l %1,%0\";
-  if (REG_P (operands[1])
-      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
-    {
-      cc_status.flags |= CC_REVERSED;
-      return \"cmp%.l %d0,%d1\"; 
-    }
-  return \"cmp%.l %d1,%d0\";
-}")
-
-(define_insn "cmphi"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m")
-		 (match_operand:HI 1 "general_operand" "d,rnm,m,n")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-    return \"cmpm%.w %1,%0\";
-  if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
-      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
-    { cc_status.flags |= CC_REVERSED;
-      return \"cmp%.w %d0,%d1\"; 
-    }
-  return \"cmp%.w %d1,%d0\";
-}")
-
-(define_insn "cmpqi"
-  [(set (cc0)
-	(compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
-		 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-    return \"cmpm%.b %1,%0\";
-  if (REG_P (operands[1])
-      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
-    {
-      cc_status.flags |= CC_REVERSED;
-      return \"cmp%.b %d0,%d1\";
-    }
-  return \"cmp%.b %d1,%d0\";
-}")
-
-(define_insn "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "nonimmediate_operand" "f,m")
-		 (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
-  "TARGET_CE"
-  "*
-{
-  cc_status.flags = CC_IN_FP;
-  if (FP_REG_P (operands[0]))
-    return \"fcmp%.d %1,%0\";
-  cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.d %0,%1\";
-}")
-
-(define_insn "cmpsf"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "nonimmediate_operand" "f,m")
-		 (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
-  "TARGET_CE"
-  "*
-{
-  cc_status.flags = CC_IN_FP;
-  if (FP_REG_P (operands[0]))
-    return \"fcmp%.s %1,%0\";
-  cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.s %0,%1\";
-}")
-
-;; Recognizers for btst instructions.
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
-			    (const_int 1)
-			    (minus:SI (const_int 7)
-				      (match_operand:SI 1 "general_operand" "di"))))]
-  ""
-  "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
-			    (const_int 1)
-			    (minus:SI (const_int 31)
-				      (match_operand:SI 1 "general_operand" "di"))))]
-  ""
-  "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
-
-;; The following two patterns are like the previous two
-;; except that they use the fact that bit-number operands
-;; are automatically masked to 3 or 5 bits.
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
-			    (const_int 1)
-			    (minus:SI (const_int 7)
-				      (and:SI
-				       (match_operand:SI 1 "general_operand" "d")
-				       (const_int 7)))))]
-  ""
-  "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
-			    (const_int 1)
-			    (minus:SI (const_int 31)
-				      (and:SI
-				       (match_operand:SI 1 "general_operand" "d")
-				       (const_int 31)))))]
-  ""
-  "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
-
-;; Nonoffsettable mem refs are ok in this one pattern
-;; since we don't try to adjust them.
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
-			    (const_int 1)
-			    (match_operand:SI 1 "general_operand" "i")))]
-  "GET_CODE (operands[1]) == CONST_INT
-   && (unsigned) INTVAL (operands[1]) < 8"
-  "*
-{
-  operands[1] = GEN_INT (7 - INTVAL (operands[1]));
-  return output_btst (operands, operands[1], operands[0], insn, 7);
-}")
-
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
-			    (const_int 1)
-			    (match_operand:SI 1 "general_operand" "i")))]
-  "GET_CODE (operands[1]) == CONST_INT"
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      operands[0] = adj_offsettable_operand (operands[0],
-					     INTVAL (operands[1]) / 8);
-      operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
-      return output_btst (operands, operands[1], operands[0], insn, 7);
-    }
-  operands[1] = GEN_INT (31 - INTVAL (operands[1]));
-  return output_btst (operands, operands[1], operands[0], insn, 31);
-}")
-
-
-;; move instructions
-
-;; A special case in which it is not desirable
-;; to reload the constant into a data register.
-(define_insn ""
-  [(set (match_operand:SI 0 "push_operand" "=m")
-	(match_operand:SI 1 "general_operand" "J"))]
-  "GET_CODE (operands[1]) == CONST_INT
-   && INTVAL (operands[1]) >= -0x8000
-   && INTVAL (operands[1]) < 0x8000"
-  "*
-{
-  if (operands[1] == const0_rtx)
-    return \"clr%.l %0\";
-  return \"pea %a1\";
-}")
-
-;This is never used.
-;(define_insn "swapsi"
-;  [(set (match_operand:SI 0 "general_operand" "r")
-;	(match_operand:SI 1 "general_operand" "r"))
-;   (set (match_dup 1) (match_dup 0))]
-;  ""
-;  "exg %1,%0")
-
-;; Special case of fullword move when source is zero.
-;; The reason this is special is to avoid loading a zero
-;; into a data reg with moveq in order to store it elsewhere.
-   
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=a,g")
-	(const_int 0))]
-  ""
-  "@
-   sub%.l %0,%0
-   clr%.l %0")
-
-;; General case of fullword move.  The register constraints
-;; force integer constants in range for a moveq to be reloaded
-;; if they are headed for memory.
-(define_insn "movsi"
-  ;; Notes: make sure no alternative allows g vs g.
-  ;; We don't allow f-regs since fixed point cannot go in them.
-  ;; We do allow y and x regs since fixed point is allowed in them.
-  [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
-	(match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      if (operands[1] == const0_rtx
-	  && (DATA_REG_P (operands[0])
-	      || GET_CODE (operands[0]) == MEM))
-	return \"clr%.l %0\";
-      else if (DATA_REG_P (operands[0])
-	       && INTVAL (operands[1]) < 128
-	       && INTVAL (operands[1]) >= -128)
-	return \"moveq %1,%0\";
-      else if (ADDRESS_REG_P (operands[0])
-	       && INTVAL (operands[1]) < 0x8000
-	       && INTVAL (operands[1]) >= -0x8000)
-	return \"mov%.w %1,%0\";
-      else if (push_operand (operands[0], SImode)
-	       && INTVAL (operands[1]) < 0x8000
-	       && INTVAL (operands[1]) >= -0x8000)
-        return \"pea %a1\";
-    }
-  else if ((GET_CODE (operands[1]) == SYMBOL_REF
-	    || GET_CODE (operands[1]) == CONST)
-	   && push_operand (operands[0], SImode))
-    return \"pea %a1\";
-  else if ((GET_CODE (operands[1]) == SYMBOL_REF
-	    || GET_CODE (operands[1]) == CONST)
-	   && ADDRESS_REG_P (operands[0]))
-    return \"lea %a1,%0\";
-  return \"mov%.l %1,%0\";
-}")
-
-(define_insn "movhi"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(match_operand:HI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      if (operands[1] == const0_rtx
-	  && (DATA_REG_P (operands[0])
-	      || GET_CODE (operands[0]) == MEM))
-	return \"clr%.w %0\";
-      else if (DATA_REG_P (operands[0])
-	       && INTVAL (operands[1]) < 128
-	       && INTVAL (operands[1]) >= -128)
-        {
-	  return \"moveq %1,%0\";
-	}
-      else if (INTVAL (operands[1]) < 0x8000
-	       && INTVAL (operands[1]) >= -0x8000)
-	return \"mov%.w %1,%0\";
-    }
-  else if (CONSTANT_P (operands[1]))
-    return \"mov%.l %1,%0\";
-  /* Recognize the insn before a tablejump, one that refers
-     to a table of offsets.  Such an insn will need to refer
-     to a label on the insn.  So output one.  Use the label-number
-     of the table of offsets to generate this label.  */
-  if (GET_CODE (operands[1]) == MEM
-      && GET_CODE (XEXP (operands[1], 0)) == PLUS
-      && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
-	  || GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF)
-      && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS
-      && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) != PLUS)
-    {
-      rtx labelref;
-      if (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF)
-	labelref = XEXP (XEXP (operands[1], 0), 0);
-      else
-	labelref = XEXP (XEXP (operands[1], 0), 1);
-      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
-				 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
-    }
-  return \"mov%.w %1,%0\";
-}")
-
-(define_insn "movstricthi"
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
-	(match_operand:HI 1 "general_operand" "rmn"))]
-  ""
-  "*
-{
-  if (operands[1] == const0_rtx)
-    return \"clr%.w %0\";
-  return \"mov%.w %1,%0\";
-}")
-
-(define_insn "movqi"
-  [(set (match_operand:QI 0 "general_operand" "=d,*a,m,m,?*a")
-	(match_operand:QI 1 "general_operand" "dmi*a,d*a,dmi,?*a,m"))]
-  ""
-  "*
-{
-  rtx xoperands[4];
-  if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM)
-    {
-      xoperands[1] = operands[1];
-      xoperands[2]
-        = gen_rtx (MEM, QImode,
-		   gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
-      xoperands[3] = stack_pointer_rtx;
-      /* Just pushing a byte puts it in the high byte of the halfword.  */
-      /* We must put it in the low half, the second byte.  */
-      output_asm_insn (\"subq%.w %#2,%3\;mov%.b %1,%2\", xoperands);
-      return \"mov%.w %+,%0\";
-    }
-  if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM)
-    {
-      xoperands[0] = operands[0];
-      xoperands[1] = operands[1];
-      xoperands[2]
-        = gen_rtx (MEM, QImode,
-		   gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
-      xoperands[3] = stack_pointer_rtx;
-      output_asm_insn (\"mov%.w %1,%-\;mov%.b %2,%0\;addq%.w %#2,%3\", xoperands);
-      return \"\";
-    }
-  if (operands[1] == const0_rtx)
-    return \"clr%.b %0\";
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL (operands[1]) == -1)
-    return \"st %0\";
-  if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
-    return \"mov%.l %1,%0\";
-  if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
-    return \"mov%.w %1,%0\";
-  return \"mov%.b %1,%0\";
-}")
-
-(define_insn "movstrictqi"
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
-	(match_operand:QI 1 "general_operand" "dmn"))]
-  ""
-  "*
-{
-  if (operands[1] == const0_rtx)
-    return \"clr%.b %0\";
-  return \"mov%.b %1,%0\";
-}")
-
-;; Floating-point moves on a CE are faster using an FP register than
-;; with movl instructions.  (Especially for double floats, but also
-;; for single floats, even though it takes an extra instruction.)  But
-;; on an IP, the FP registers are simulated and so should be avoided.
-;; We do this by using define_expand for movsf and movdf, and using
-;; different constraints for each target type.  The constraints for
-;; TARGET_CE allow general registers because they sometimes need to
-;; hold floats, but they are not preferable.
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "nonimmediate_operand" ""))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f,m,!*r,!f*m")
-	(match_operand:SF 1 "nonimmediate_operand" "fm,f,f*r*m,*r"))]
-  "TARGET_CE"
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"fmove%.s %1,%0\";
-      if (REG_P (operands[1]))
-	return \"mov%.l %1,%-\;fmove%.s %+,%0\";
-      return \"fmove%.s %1,%0\";
-    }
-  if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	return \"fmove%.s %1,%-\;mov%.l %+,%0\";
-      return \"fmove%.s %1,%0\";
-    }
-  return \"mov%.l %1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=frm")
-	(match_operand:SF 1 "nonimmediate_operand" "frm"))]
-  "!TARGET_CE"
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"fmove%.s %1,%0\";
-      if (REG_P (operands[1]))
-	return \"mov%.l %1,%-\;fmove%.s %+,%0\";
-      return \"fmove%.s %1,%0\";
-    }
-  if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	return \"fmove%.s %1,%-\;mov%.l %+,%0\";
-      return \"fmove%.s %1,%0\";
-    }
-  return \"mov%.l %1,%0\";
-}")
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "nonimmediate_operand" ""))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f,m,!*r,!f*m")
-	(match_operand:DF 1 "nonimmediate_operand" "fm,f,f*r*m,*r"))]
-  "TARGET_CE"
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"fmove%.d %1,%0\";
-      if (REG_P (operands[1]))
-	{
-	  rtx xoperands[2];
-	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"mov%.l %1,%-\", xoperands);
-	  output_asm_insn (\"mov%.l %1,%-\", operands);
-	  return \"fmove%.d %+,%0\";
-	}
-      return \"fmove%.d %1,%0\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	{
-	  output_asm_insn (\"fmove%.d %1,%-\;mov%.l %+,%0\", operands);
-	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-	  return \"mov%.l %+,%0\";
-	}
-      return \"fmove%.d %1,%0\";
-    }
-  return output_move_double (operands);
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=frm")
-	(match_operand:DF 1 "nonimmediate_operand" "frm"))]
-  "!TARGET_CE"
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"fmove%.d %1,%0\";
-      if (REG_P (operands[1]))
-	{
-	  rtx xoperands[2];
-	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"mov%.l %1,%-\", xoperands);
-	  output_asm_insn (\"mov%.l %1,%-\", operands);
-	  return \"fmove%.d %+,%0\";
-	}
-      return \"fmove%.d %1,%0\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	{
-	  output_asm_insn (\"fmove%.d %1,%-\;mov%.l %+,%0\", operands);
-	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-	  return \"mov%.l %+,%0\";
-	}
-      return \"fmove%.d %1,%0\";
-    }
-  return output_move_double (operands);
-}")
-
-(define_insn "movdi"
-  [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>")
-	(match_operand:DI 1 "general_operand" "r,m,roi<>"))]
-  ""
-  "*
-{
-  return output_move_double (operands);
-}
-")
-
-;; This goes after the move instructions
-;; because the move instructions are better (require no spilling)
-;; when they can apply.  It goes before the add/sub insns
-;; so we will prefer it to them.
-
-(define_insn "pushasi"
-  [(set (match_operand:SI 0 "push_operand" "=m")
-	(match_operand:SI 1 "address_operand" "p"))]
-  ""
-  "pea %a1")
-
-;; truncation instructions
-(define_insn "truncsiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm,d")
-	(truncate:QI
-	 (match_operand:SI 1 "general_operand" "doJ,i")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == REG)
-    return \"mov%.l %1,%0\";
-  if (GET_CODE (operands[1]) == MEM)
-    operands[1] = adj_offsettable_operand (operands[1], 3);
-  return \"mov%.b %1,%0\";
-}")
-
-(define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm,d")
-	(truncate:QI
-	 (match_operand:HI 1 "general_operand" "doJ,i")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == REG
-      && (GET_CODE (operands[1]) == MEM
-	  || GET_CODE (operands[1]) == CONST_INT))
-    return \"mov%.w %1,%0\";
-  if (GET_CODE (operands[0]) == REG)
-    return \"mov%.l %1,%0\";
-  if (GET_CODE (operands[1]) == MEM)
-    operands[1] = adj_offsettable_operand (operands[1], 1);
-  return \"mov%.b %1,%0\";
-}")
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "general_operand" "=dm,d")
-	(truncate:HI
-	 (match_operand:SI 1 "general_operand" "roJ,i")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == REG)
-    return \"mov%.l %1,%0\";
-  if (GET_CODE (operands[1]) == MEM)
-    operands[1] = adj_offsettable_operand (operands[1], 2);
-  return \"mov%.w %1,%0\";
-}")
-
-;; zero extension instructions
-
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(const_int 0))
-   (set (strict_low_part (subreg:HI (match_dup 0) 0))
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "operands[1] = make_safe_from (operands[1], operands[0]);")
-
-(define_expand "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(const_int 0))
-   (set (strict_low_part (subreg:QI (match_dup 0) 0))
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "operands[1] = make_safe_from (operands[1], operands[0]);")
-
-(define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(const_int 0))
-   (set (strict_low_part (subreg:QI (match_dup 0) 0))
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  " operands[1] = make_safe_from (operands[1], operands[0]); ")
-
-;; Patterns to recognize zero-extend insns produced by the combiner.
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=do<>")
-	(zero_extend:SI
-	 (match_operand:HI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "*
-{
-  if (DATA_REG_P (operands[0]))
-    {
-      if (GET_CODE (operands[1]) == REG
-	  && REGNO (operands[0]) == REGNO (operands[1]))
-	return \"and%.l %#0xFFFF,%0\";
-      if (reg_mentioned_p (operands[0], operands[1]))
-        return \"mov%.w %1,%0\;and%.l %#0xFFFF,%0\";
-      return \"clr%.l %0\;mov%.w %1,%0\";
-    }
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    return \"mov%.w %1,%0\;clr%.w %0\";
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    return \"clr%.w %0\;mov%.w %1,%0\";
-  else
-    {
-      output_asm_insn (\"clr%.w %0\", operands);
-      operands[0] = adj_offsettable_operand (operands[0], 2);
-      return \"mov%.w %1,%0\";
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=do<>")
-	(zero_extend:HI
-	 (match_operand:QI 1 "nonimmediate_operand" "dm")))]
-  ""
-  "*
-{
-  if (DATA_REG_P (operands[0]))
-    {
-      if (GET_CODE (operands[1]) == REG
-	  && REGNO (operands[0]) == REGNO (operands[1]))
-	return \"and%.w %#0xFF,%0\";
-      if (reg_mentioned_p (operands[0], operands[1]))
-        return \"mov%.b %1,%0\;and%.w %#0xFF,%0\";
-      return \"clr%.w %0\;mov%.b %1,%0\";
-    }
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    {
-      if (REGNO (XEXP (XEXP (operands[0], 0), 0))
-	  == STACK_POINTER_REGNUM)
-	return \"clr%.w %-\;mov%.b %1,%0\";
-      else
-	return \"mov%.b %1,%0\;clr%.b %0\";
-    }
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    return \"clr%.b %0\;mov%.b %1,%0\";
-  else
-    {
-      output_asm_insn (\"clr%.b %0\", operands);
-      operands[0] = adj_offsettable_operand (operands[0], 1);
-      return \"mov%.b %1,%0\";
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=do<>")
-	(zero_extend:SI
-	 (match_operand:QI 1 "nonimmediate_operand" "dm")))]
-  ""
-  "*
-{
-  if (DATA_REG_P (operands[0]))
-    {
-      if (GET_CODE (operands[1]) == REG
-	  && REGNO (operands[0]) == REGNO (operands[1]))
-	return \"and%.l %#0xFF,%0\";
-      if (reg_mentioned_p (operands[0], operands[1]))
-        return \"mov%.b %1,%0\;and%.l %#0xFF,%0\";
-      return \"clr%.l %0\;mov%.b %1,%0\";
-    }
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    {
-      operands[0] = XEXP (XEXP (operands[0], 0), 0);
-      return \"clr%.l %0@-\;mov%.b %1,%0@(3)\";
-    }
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    {
-      operands[0] = XEXP (XEXP (operands[0], 0), 0);
-      return \"clr%.l %0@+\;mov%.b %1,%0@(-1)\";
-    }
-  else
-    {
-      output_asm_insn (\"clr%.l %0\", operands);
-      operands[0] = adj_offsettable_operand (operands[0], 3);
-      return \"mov%.b %1,%0\";
-    }
-}")
-
-;; sign extension instructions
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=*d,a")
-	(sign_extend:SI
-	 (match_operand:HI 1 "nonimmediate_operand" "0,rmn")))]
-  ""
-  "@
-   ext%.l %0
-   mov%.w %1,%0")
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(sign_extend:HI
-	 (match_operand:QI 1 "nonimmediate_operand" "0")))]
-  ""
-  "ext%.w %0")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(sign_extend:SI
-	 (match_operand:QI 1 "nonimmediate_operand" "0")))]
-  "TARGET_68020"
-  "extb%.l %0")
-
-;; Conversions between float and double.
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "general_operand" "=f,m")
-	(float_extend:DF
-	  (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
-  "TARGET_CE"
-  "fmovesd %1,%0")
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "general_operand" "=f,m")
-	(float_truncate:SF
-	  (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
-  "TARGET_CE"
-  "fmoveds %1,%0")
-
-;; Conversion between fixed point and floating point.
-;; Note that among the fix-to-float insns
-;; the ones that start with SImode come first.
-;; That is so that an operand that is a CONST_INT
-;; (and therefore lacks a specific machine mode).
-;; will be recognized as SImode (which is always valid)
-;; rather than as QImode or HImode.
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float:SF (match_operand:SI 1 "nonimmediate_operand" "dm")))]
-  "TARGET_CE"
-  "fmovels %1,%0")
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float:DF (match_operand:SI 1 "nonimmediate_operand" "dm")))]
-  "TARGET_CE"
-  "fmoveld %1,%0")
-
-(define_insn "floathisf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float:SF (match_operand:HI 1 "nonimmediate_operand" "dm")))]
-  "TARGET_CE"
-  "fmovews %1,%0")
-
-(define_insn "floathidf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float:DF (match_operand:HI 1 "nonimmediate_operand" "dm")))]
-  "TARGET_CE"
-  "fmovewd %1,%0")
-
-(define_insn "floatqisf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float:SF (match_operand:QI 1 "nonimmediate_operand" "dm")))]
-  "TARGET_CE"
-  "fmovebs %1,%0")
-
-(define_insn "floatqidf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float:DF (match_operand:QI 1 "nonimmediate_operand" "dm")))]
-  "TARGET_CE"
-  "fmovebd %1,%0")
-
-;; Float-to-fix conversion insns.
-
-(define_insn "fix_truncsfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(fix:QI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
-  "TARGET_CE"
-  "fmovesb %1,%0")
-
-(define_insn "fix_truncsfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=dm")
-	(fix:HI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
-  "TARGET_CE"
-  "fmovesw %1,%0")
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=dm")
-	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
-  "TARGET_CE"
-  "fmovesl %1,%0")
-
-(define_insn "fix_truncdfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
-  "TARGET_CE"
-  "fmovedb %1,%0")
-
-(define_insn "fix_truncdfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=dm")
-	(fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
-  "TARGET_CE"
-  "fmovedw %1,%0")
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=dm")
-	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
-  "TARGET_CE"
-  "fmovedl %1,%0")
-
-;; add instructions
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "general_operand" "=m,r,!a,!a")
-	(plus:SI (match_operand:SI 1 "general_operand" "%0,0,a,rJK")
-		 (match_operand:SI 2 "general_operand" "dIKLs,mrIKLs,rJK,a")))]
-  ""
-  "*
-{
-  if (! operands_match_p (operands[0], operands[1]))
-    {
-      if (!ADDRESS_REG_P (operands[1]))
-	{
-	  rtx tmp = operands[1];
-
-	  operands[1] = operands[2];
-	  operands[2] = tmp;
-	}
-
-      /* These insns can result from reloads to access
-	 stack slots over 64k from the frame pointer.  */
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
-        return \"mov%.l %2,%0\;add%.l %1,%0\";
-      if (GET_CODE (operands[2]) == REG)
-	return \"lea %1@[%2:L:B],%0\";
-      else
-	return \"lea %1@(%c2),%0\";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) > 0
-	  && INTVAL (operands[2]) <= 8)
-	return (ADDRESS_REG_P (operands[0])
-		? \"addq%.w %2,%0\"
-		: \"addq%.l %2,%0\");
-      if (INTVAL (operands[2]) < 0
-	  && INTVAL (operands[2]) >= -8)
-        {
-	  operands[2] = GEN_INT (- INTVAL (operands[2]));
-	  return (ADDRESS_REG_P (operands[0])
-		  ? \"subq%.w %2,%0\"
-		  : \"subq%.l %2,%0\");
-	}
-      if (ADDRESS_REG_P (operands[0])
-	  && INTVAL (operands[2]) >= -0x8000
-	  && INTVAL (operands[2]) < 0x8000)
-	return \"add%.w %2,%0\";
-    }
-  return \"add%.l %2,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=a")
-	(plus:SI (match_operand:SI 1 "general_operand" "0")
-		 (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmn"))))]
-  ""
-  "add%.w %2,%0")
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "general_operand" "=mr,mr,m,r")
-	(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0")
-		 (match_operand:HI 2 "general_operand" "I,L,dn,rmn")))]
-  ""
-  "@
-   addq%.w %2,%0
-   subq%.w #%n2,%0
-   add%.w %2,%0
-   add%.w %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
-	(plus:HI (match_dup 0)
-		 (match_operand:HI 1 "general_operand" "dn,rmn")))]
-  ""
-  "add%.w %1,%0")
-
-(define_insn "addqi3"
-  [(set (match_operand:QI 0 "general_operand" "=md,mr,m,d")
-	(plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
-		 (match_operand:QI 2 "general_operand" "I,L,dn,dmn")))]
-  ""
-  "@
-   addq%.b %2,%0
-   subq%.b #%n2,%0
-   add%.b %2,%0
-   add%.b %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
-	(plus:QI (match_dup 0)
-		 (match_operand:QI 1 "general_operand" "dn,dmn")))]
-  ""
-  "add%.b %1,%0")
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%f")
-		 (match_operand:DF 2 "nonimmediate_operand" "fm")))]
-  "TARGET_CE"
-  "fadd%.d %2,%1,%0")
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%f")
-		 (match_operand:SF 2 "nonimmediate_operand" "fm")))]
-  "TARGET_CE"
-  "fadd%.s %2,%1,%0")
-
-;; subtract instructions
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "general_operand" "=m,r,!a,?d")
-	(minus:SI (match_operand:SI 1 "general_operand" "0,0,a,mrIKs")
-		  (match_operand:SI 2 "general_operand" "dIKs,mrIKs,J,0")))]
-  ""
-  "*
-{
-  if (! operands_match_p (operands[0], operands[1]))
-    {
-      if (operands_match_p (operands[0], operands[2]))
-	{
-	  if (GET_CODE (operands[1]) == CONST_INT)
-	    {
-	      if (INTVAL (operands[1]) > 0
-		  && INTVAL (operands[1]) <= 8)
-		return \"subq%.l %1,%0\;neg%.l %0\";
-	    }
-	  return \"sub%.l %1,%0\;neg%.l %0\";
-	}
-      /* This case is matched by J, but negating -0x8000
-         in an lea would give an invalid displacement.
-	 So do this specially.  */
-      if (INTVAL (operands[2]) == -0x8000)
-	return \"mov%.l %1,%0\;sub%.l %2,%0\";
-      return \"lea %1@(%n2),%0\";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) > 0
-	  && INTVAL (operands[2]) <= 8)
-	return \"subq%.l %2,%0\";
-      if (ADDRESS_REG_P (operands[0])
-	  && INTVAL (operands[2]) >= -0x8000
-	  && INTVAL (operands[2]) < 0x8000)
-	return \"sub%.w %2,%0\";
-    }
-  return \"sub%.l %2,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=a")
-	(minus:SI (match_operand:SI 1 "general_operand" "0")
-		  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmn"))))]
-  ""
-  "sub%.w %2,%0")
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "general_operand" "=m,r")
-	(minus:HI (match_operand:HI 1 "general_operand" "0,0")
-		  (match_operand:HI 2 "general_operand" "dn,rmn")))]
-  ""
-  "sub%.w %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
-	(minus:HI (match_dup 0)
-		  (match_operand:HI 1 "general_operand" "dn,rmn")))]
-  ""
-  "sub%.w %1,%0")
-
-(define_insn "subqi3"
-  [(set (match_operand:QI 0 "general_operand" "=m,d")
-	(minus:QI (match_operand:QI 1 "general_operand" "0,0")
-		  (match_operand:QI 2 "general_operand" "dn,dmn")))]
-  ""
-  "sub%.b %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
-	(minus:QI (match_dup 0)
-		  (match_operand:QI 1 "general_operand" "dn,dmn")))]
-  ""
-  "sub%.b %1,%0")
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
-	(minus:DF (match_operand:DF 1 "nonimmediate_operand" "f,f,m")
-		  (match_operand:DF 2 "nonimmediate_operand" "f,m,f")))]
-  "TARGET_CE"
-  "@
-   fsub%.d %2,%1,%0
-   fsub%.d %2,%1,%0
-   frsub%.d %1,%2,%0")
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f,f,f")
-	(minus:SF (match_operand:SF 1 "nonimmediate_operand" "f,f,m")
-		  (match_operand:SF 2 "nonimmediate_operand" "f,m,f")))]
-  "TARGET_CE"
-  "@
-   fsub%.s %2,%1,%0
-   fsub%.s %2,%1,%0
-   frsub%.s %1,%2,%0")
-
-;; multiply instructions
-
-(define_insn "mulhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(mult:HI (match_operand:HI 1 "general_operand" "%0")
-		 (match_operand:HI 2 "general_operand" "dmn")))]
-  ""
-  "muls %2,%0")
-
-(define_insn "mulhisi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(mult:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0"))
-		 (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
-  ""
-  "muls %2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(mult:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0"))
-		 (match_operand:SI 2 "const_int_operand" "n")))]
-  ""
-  "muls %2,%0")
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(mult:SI (match_operand:SI 1 "general_operand" "%0")
-		 (match_operand:SI 2 "general_operand" "dmsK")))]
-  "TARGET_68020"
-  "muls%.l %2,%0")
-
-(define_insn "umulhisi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(mult:SI (zero_extend:SI
-		  (match_operand:HI 1 "nonimmediate_operand" "%0"))
-		 (zero_extend:SI
-		  (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
-  ""
-  "mulu %2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(mult:SI (zero_extend:SI
-		  (match_operand:HI 1 "nonimmediate_operand" "%0"))
-		 (match_operand:SI 2 "const_int_operand" "n")))]
-  ""
-  "mulu %2,%0")
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%f")
-		 (match_operand:DF 2 "nonimmediate_operand" "fm")))]
-  "TARGET_CE"
-  "fmul%.d %2,%1,%0")
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%f")
-		 (match_operand:SF 2 "nonimmediate_operand" "fm")))]
-  "TARGET_CE"
-  "fmul%.s %2,%1,%0")
-
-;; divide instructions
-
-(define_insn "divhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(div:HI (match_operand:HI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "dmn")))]
-  ""
-  "extl %0\;divs %2,%0")
-
-(define_insn "divhisi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI
-	 (div:SI
-	  (match_operand:SI 1 "general_operand" "0")
-	  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
-  ""
-  "divs %2,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI (div:SI (match_operand:SI 1 "general_operand" "0")
-			     (match_operand:SI 2 "const_int_operand" "n"))))]
-  ""
-  "divs %2,%0")
-
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(div:SI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:SI 2 "general_operand" "dmsK")))]
-  "TARGET_68020"
-  "divs%.l %2,%0,%0")
-
-(define_insn "udivhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(udiv:HI (match_operand:HI 1 "general_operand" "0")
-		 (match_operand:HI 2 "general_operand" "dmn")))]
-  ""
-  "and%.l %#0xFFFF,%0\;divu %2,%0")
-
-(define_insn "udivhisi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI
-	 (udiv:SI
-	  (match_operand:SI 1 "general_operand" "0")
-	  (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
-  ""
-  "divu %2,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-			      (match_operand:HI 2 "const_int_operand" "n"))))]
-  ""
-  "divu %2,%0")
-
-(define_insn "udivsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(udiv:SI (match_operand:SI 1 "general_operand" "0")
-		 (match_operand:SI 2 "general_operand" "dmsK")))]
-  "TARGET_68020"
-  "divu%.l %2,%0,%0")
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
-	(div:DF (match_operand:DF 1 "nonimmediate_operand" "f,f,m")
-		(match_operand:DF 2 "nonimmediate_operand" "f,m,f")))]
-  "TARGET_CE"
-  "@
-   fdiv%.d %2,%1,%0
-   fdiv%.d %2,%1,%0
-   frdiv%.d %1,%2,%0")
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f,f,f")
-	(div:SF (match_operand:SF 1 "nonimmediate_operand" "f,f,m")
-		(match_operand:SF 2 "nonimmediate_operand" "f,m,f")))]
-  "TARGET_CE"
-  "@
-   fdiv%.s %2,%1,%0
-   fdiv%.s %2,%1,%0
-   frdiv%.s %1,%2,%0")
-
-;; Remainder instructions.
-
-(define_insn "modhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(mod:HI (match_operand:HI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "dmn")))]
-  ""
-  "extl %0\;divs %2,%0\;swap %0")
-
-(define_insn "modhisi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI
-	 (mod:SI
-	  (match_operand:SI 1 "general_operand" "0")
-	  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
-  ""
-  "divs %2,%0\;swap %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI (mod:SI (match_operand:SI 1 "general_operand" "0")
-			     (match_operand:SI 2 "const_int_operand" "n"))))]
-  ""
-  "divs %2,%0\;swap %0")
-
-(define_insn "umodhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(umod:HI (match_operand:HI 1 "general_operand" "0")
-		 (match_operand:HI 2 "general_operand" "dmn")))]
-  ""
-  "and%.l %#0xFFFF,%0\;divu %2,%0\;swap %0")
-
-(define_insn "umodhisi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI
-	 (umod:SI
-	  (match_operand:SI 1 "general_operand" "0")
-	  (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
-  ""
-  "divu %2,%0\;swap %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI (umod:SI (match_operand:SI 1 "general_operand" "0")
-			      (match_operand:SI 2 "const_int_operand" "n"))))]
-  ""
-  "divu %2,%0\;swap %0")
-
-(define_insn "divmodsi4"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(div:SI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:SI 2 "general_operand" "dmsK")))
-   (set (match_operand:SI 3 "general_operand" "=d")
-	(mod:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_68020"
-  "divs%.l %2,%0,%3")
-
-(define_insn "udivmodsi4"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(udiv:SI (match_operand:SI 1 "general_operand" "0")
-		 (match_operand:SI 2 "general_operand" "dmsK")))
-   (set (match_operand:SI 3 "general_operand" "=d")
-	(umod:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_68020"
-  "divu%.l %2,%0,%3")
-
-;; logical-and instructions
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "general_operand" "=m,d")
-	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "dKs,dmKs")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
-      && (DATA_REG_P (operands[0])
-	  || offsettable_memref_p (operands[0])))
-    { 
-      if (GET_CODE (operands[0]) != REG)
-        operands[0] = adj_offsettable_operand (operands[0], 2);
-      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
-      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
-      CC_STATUS_INIT;
-      if (operands[2] == const0_rtx)
-        return \"clr%.w %0\";
-      return \"and%.w %2,%0\";
-    }
-  return \"and%.l %2,%0\";
-}")
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "general_operand" "=m,d")
-	(and:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "dn,dmn")))]
-  ""
-  "and%.w %2,%0")
-
-(define_insn "andqi3"
-  [(set (match_operand:QI 0 "general_operand" "=m,d")
-	(and:QI (match_operand:QI 1 "general_operand" "%0,0")
-		(match_operand:QI 2 "general_operand" "dn,dmn")))]
-  ""
-  "and%.b %2,%0")
-
-
-;; inclusive-or instructions
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=m,d")
-	(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "dKs,dmKs")))]
-  ""
-  "*
-{
-  register int logval;
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) >> 16 == 0
-      && (DATA_REG_P (operands[0])
-	  || offsettable_memref_p (operands[0])))
-    { 
-      if (GET_CODE (operands[0]) != REG)
-        operands[0] = adj_offsettable_operand (operands[0], 2);
-      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
-      CC_STATUS_INIT;
-      return \"or%.w %2,%0\";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
-      && (DATA_REG_P (operands[0])
-	  || offsettable_memref_p (operands[0])))
-    { 
-      if (DATA_REG_P (operands[0]))
-	operands[1] = GEN_INT (logval);
-      else
-        {
-	  operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
-	  operands[1] = GEN_INT (logval % 8);
-	}
-      return \"bset %1,%0\";
-    }
-  return \"or%.l %2,%0\";
-}")
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=m,d")
-	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "dn,dmn")))]
-  ""
-  "or%.w %2,%0")
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=m,d")
-	(ior:QI (match_operand:QI 1 "general_operand" "%0,0")
-		(match_operand:QI 2 "general_operand" "dn,dmn")))]
-  ""
-  "or%.b %2,%0")
-
-;; xor instructions
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=do,m")
-	(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "di,dKs")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) >> 16 == 0
-      && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
-    { 
-      if (! DATA_REG_P (operands[0]))
-	operands[0] = adj_offsettable_operand (operands[0], 2);
-      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
-      CC_STATUS_INIT;
-      return \"eor%.w %2,%0\";
-    }
-  return \"eor%.l %2,%0\";
-}")
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=dm")
-	(xor:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "dn")))]
-  ""
-  "eor%.w %2,%0")
-
-(define_insn "xorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(xor:QI (match_operand:QI 1 "general_operand" "%0")
-		(match_operand:QI 2 "general_operand" "dn")))]
-  ""
-  "eor%.b %2,%0")
-
-;; negation instructions
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "general_operand" "=dm")
-	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
-  ""
-  "neg%.l %0")
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "general_operand" "=dm")
-	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
-  ""
-  "neg%.w %0")
-
-(define_insn "negqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(neg:QI (match_operand:QI 1 "general_operand" "0")))]
-  ""
-  "neg%.b %0")
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (match_operand:SF 1 "nonimmediate_operand" "fm")))]
-  "TARGET_CE"
-  "fneg%.s %1,%0")
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (match_operand:DF 1 "nonimmediate_operand" "fm")))]
-  "TARGET_CE"
-  "fneg%.d %1,%0")
-
-;; Absolute value instructions
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(abs:SF (match_operand:SF 1 "nonimmediate_operand" "fm")))]
-  "TARGET_CE"
-  "fabs%.s %1,%0")
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(abs:DF (match_operand:DF 1 "nonimmediate_operand" "fm")))]
-  "TARGET_CE"
-  "fabs%.d %1,%0")
-
-;; Square root instructions
-
-(define_insn "sqrtsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "fm")))]
-  "TARGET_CE"
-  "fsqrt%.s %1,%0")
-
-(define_insn "sqrtdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "fm")))]
-  "TARGET_CE"
-  "fsqrt%.d %1,%0")
-
-;; one complement instructions
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "general_operand" "=dm")
-	(not:SI (match_operand:SI 1 "general_operand" "0")))]
-  ""
-  "not%.l %0")
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "general_operand" "=dm")
-	(not:HI (match_operand:HI 1 "general_operand" "0")))]
-  ""
-  "not%.w %0")
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(not:QI (match_operand:QI 1 "general_operand" "0")))]
-  ""
-  "not%.b %0")
-
-
-;; arithmetic shift instructions
-;; We don't need the shift memory by 1 bit instruction
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(ashift:SI (match_operand:SI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "dI")))]
-  ""
-  "asl%.l %2,%0")
-
-(define_insn "ashlhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(ashift:HI (match_operand:HI 1 "general_operand" "0")
-		   (match_operand:HI 2 "general_operand" "dI")))]
-  ""
-  "asl%.w %2,%0")
-
-(define_insn "ashlqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(ashift:QI (match_operand:QI 1 "general_operand" "0")
-		   (match_operand:QI 2 "general_operand" "dI")))]
-  ""
-  "asl%.b %2,%0")
-
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "dI")))]
-  ""
-  "asr%.l %2,%0")
-
-(define_insn "ashrhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
-		     (match_operand:HI 2 "general_operand" "dI")))]
-  ""
-  "asr%.w %2,%0")
-
-(define_insn "ashrqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
-		     (match_operand:QI 2 "general_operand" "dI")))]
-  ""
-  "asr%.b %2,%0")
-
-;; logical shift instructions
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "dI")))]
-  ""
-  "lsr%.l %2,%0")
-
-(define_insn "lshrhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
-		     (match_operand:HI 2 "general_operand" "dI")))]
-  ""
-  "lsr%.w %2,%0")
-
-(define_insn "lshrqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
-		     (match_operand:QI 2 "general_operand" "dI")))]
-  ""
-  "lsr%.b %2,%0")
-
-;; rotate instructions
-
-(define_insn "rotlsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(rotate:SI (match_operand:SI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "dI")))]
-  ""
-  "rol%.l %2,%0")
-
-(define_insn "rotlhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(rotate:HI (match_operand:HI 1 "general_operand" "0")
-		   (match_operand:HI 2 "general_operand" "dI")))]
-  ""
-  "rol%.w %2,%0")
-
-(define_insn "rotlqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(rotate:QI (match_operand:QI 1 "general_operand" "0")
-		   (match_operand:QI 2 "general_operand" "dI")))]
-  ""
-  "rol%.b %2,%0")
-
-(define_insn "rotrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(rotatert:SI (match_operand:SI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "dI")))]
-  ""
-  "ror%.l %2,%0")
-
-(define_insn "rotrhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(rotatert:HI (match_operand:HI 1 "general_operand" "0")
-		     (match_operand:HI 2 "general_operand" "dI")))]
-  ""
-  "ror%.w %2,%0")
-
-(define_insn "rotrqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(rotatert:QI (match_operand:QI 1 "general_operand" "0")
-		     (match_operand:QI 2 "general_operand" "dI")))]
-  ""
-  "ror%.b %2,%0")
-
-;; Special cases of bit-field insns which we should
-;; recognize in preference to the general case.
-;; These handle aligned 8-bit and 16-bit fields,
-;; which can usually be done with move instructions.
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
-			 (match_operand:SI 1 "const_int_operand" "i")
-			 (match_operand:SI 2 "const_int_operand" "i"))
-	(match_operand:SI 3 "general_operand" "d"))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
-   && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
-   && (GET_CODE (operands[0]) == REG
-       || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
-  "*
-{
-  if (REG_P (operands[0]))
-    {
-      if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
-        return \"bfins %3,[%c2,%c1]%0\";
-    }
-  else
-    operands[0]
-      = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
-
-  if (GET_CODE (operands[3]) == MEM)
-    operands[3] = adj_offsettable_operand (operands[3],
-					   (32 - INTVAL (operands[1])) / 8);
-  if (INTVAL (operands[1]) == 8)
-    return \"mov%.b %3,%0\";
-  return \"mov%.w %3,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=&d")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "do")
-			 (match_operand:SI 2 "const_int_operand" "i")
-			 (match_operand:SI 3 "const_int_operand" "i")))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
-   && (GET_CODE (operands[1]) == REG
-       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
-  "*
-{
-  if (REG_P (operands[1]))
-    {
-      if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
-	return \"bfextu [%c3,%c2]%1,%0\";
-    }
-  else
-    operands[1]
-      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
-
-  output_asm_insn (\"clrl %0\", operands);
-  if (GET_CODE (operands[0]) == MEM)
-    operands[0] = adj_offsettable_operand (operands[0],
-					   (32 - INTVAL (operands[1])) / 8);
-  if (INTVAL (operands[2]) == 8)
-    return \"mov%.b %1,%0\";
-  return \"mov%.w %1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(sign_extract:SI (match_operand:SI 1 "register_operand" "do")
-			 (match_operand:SI 2 "const_int_operand" "i")
-			 (match_operand:SI 3 "const_int_operand" "i")))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
-   && (GET_CODE (operands[1]) == REG
-       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
-  "*
-{
-  if (REG_P (operands[1]))
-    {
-      if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
-	return \"bfexts [%c3,%c2]%1,%0\";
-    }
-  else
-    operands[1]
-      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
-
-  if (INTVAL (operands[2]) == 8)
-    return \"mov%.b %1,%0\;extb%.l %0\";
-  return \"mov%.w %1,%0\;ext%.l %0\";
-}")
-
-;; Bit field instructions, general cases.
-;; "o,d" constraint causes a nonoffsettable memref to match the "o"
-;; so that its address is reloaded.
-
-(define_expand "extv"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(sign_extract:SI (match_operand:SI 1 "general_operand" "")
-			 (match_operand:SI 2 "general_operand" "")
-			 (match_operand:SI 3 "general_operand" "")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
-			 (match_operand:SI 2 "general_operand" "di")
-			 (match_operand:SI 3 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "bfexts [%c3,%c2]%1,%0")
-
-(define_expand "extzv"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(zero_extract:SI (match_operand:SI 1 "general_operand" "")
-			 (match_operand:SI 2 "general_operand" "")
-			 (match_operand:SI 3 "general_operand" "")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
-			 (match_operand:SI 2 "general_operand" "di")
-			 (match_operand:SI 3 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "bfextu [%c3,%c2]%1,%0")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-        (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
-		(match_operand:SI 3 "const_int_operand" "i,i")))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[3]) == -1
-       || (GET_CODE (operands[1]) == CONST_INT
-           && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bfchg [%c2,%c1]%0\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-	(const_int 0))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bfclr [%c2,%c1]%0\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-	(const_int -1))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bfset [%c2,%c1]%0\";
-}")
-
-(define_expand "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
-			 (match_operand:SI 1 "general_operand" "")
-			 (match_operand:SI 2 "general_operand" ""))
-	(match_operand:SI 3 "general_operand" ""))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-	(match_operand:SI 3 "general_operand" "d"))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "bfins %3,[%c2,%c1]%0")
-
-;; Now recognize bit field insns that operate on registers
-;; (or at least were intended to do so).
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(sign_extract:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "general_operand" "di")
-			 (match_operand:SI 3 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "bfexts [%c3,%c2]%1,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "general_operand" "di")
-			 (match_operand:SI 3 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "bfextu [%c3,%c2]%1,%0")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-	(const_int 0))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bfclr [%c2,%c1]%0\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-	(const_int -1))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bfset [%c2,%c1]%0\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-	(match_operand:SI 3 "general_operand" "d"))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  return \"bfins %3,[%c2,%c1]%0\";
-}")
-
-;; Special patterns for optimizing bit-field instructions.
-
-(define_insn ""
-  [(set (cc0)
-	(zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
-			 (match_operand:SI 1 "const_int_operand" "i")
-			 (match_operand:SI 2 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  if (operands[1] == const1_rtx
-      && GET_CODE (operands[2]) == CONST_INT)
-    {    
-      int width = GET_CODE (operands[0]) == REG ? 31 : 7;
-      return output_btst (operands,
-			  GEN_INT (width - INTVAL (operands[2])),
-			  operands[0],
-			  insn, 1000);
-      /* Pass 1000 as SIGNPOS argument so that btst will
-         not think we are testing the sign bit for an `and'
-	 and assume that nonzero implies a negative result.  */
-    }
-  if (INTVAL (operands[1]) != 32)
-    cc_status.flags = CC_NOT_NEGATIVE;
-  return \"bftst [%c2,%c1]%0\";
-}")
-
-;;; now handle the register cases
-(define_insn ""
-  [(set (cc0)
-	(zero_extract:SI (match_operand:SI 0 "register_operand" "d")
-			 (match_operand:SI 1 "const_int_operand" "i")
-			 (match_operand:SI 2 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  if (operands[1] == const1_rtx
-      && GET_CODE (operands[2]) == CONST_INT)
-    {    
-      int width = GET_CODE (operands[0]) == REG ? 31 : 7;
-      return output_btst (operands,
-			  GEN_INT (width - INTVAL (operands[2])),
-			  operands[0],
-			  insn, 1000);
-      /* Pass 1000 as SIGNPOS argument so that btst will
-         not think we are testing the sign bit for an `and'
-	 and assume that nonzero implies a negative result.  */
-    }
-  if (INTVAL (operands[1]) != 32)
-    cc_status.flags = CC_NOT_NEGATIVE;
-  return \"bftst [%c2,%c1]%0\";
-}")
-
-
-(define_insn "seq"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(eq:QI (cc0) (const_int 0)))]
-  ""
-  "*
-  cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
-")
-
-(define_insn "sne"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(ne:QI (cc0) (const_int 0)))]
-  ""
-  "*
-  cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"sne %0\", \"fsneq %0\", \"sne %0\");
-")
-
-(define_insn "sgt"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(gt:QI (cc0) (const_int 0)))]
-  ""
-  "*
-  cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", \"and%.b %#0xc,%!\;sgt %0\");
-")
-
-(define_insn "sgtu"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(gtu:QI (cc0) (const_int 0)))]
-  ""
-  "* cc_status = cc_prev_status;
-     return \"shi %0\"; ")
-
-(define_insn "slt"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(lt:QI (cc0) (const_int 0)))]
-  ""
-  "* cc_status = cc_prev_status;
-     OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
-
-(define_insn "sltu"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(ltu:QI (cc0) (const_int 0)))]
-  ""
-  "* cc_status = cc_prev_status;
-     return \"scs %0\"; ")
-
-(define_insn "sge"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(ge:QI (cc0) (const_int 0)))]
-  ""
-  "* cc_status = cc_prev_status;
-     OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
-
-(define_insn "sgeu"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(geu:QI (cc0) (const_int 0)))]
-  ""
-  "* cc_status = cc_prev_status;
-     return \"scc %0\"; ")
-
-(define_insn "sle"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(le:QI (cc0) (const_int 0)))]
-  ""
-  "*
-  cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"sle %0\", \"fsle %0\", \"and%.b %#0xc,%!\;sle %0\");
-")
-
-(define_insn "sleu"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(leu:QI (cc0) (const_int 0)))]
-  ""
-  "* cc_status = cc_prev_status;
-     return \"sls %0\"; ")
-
-;; Basic conditional jump instructions.
-
-(define_insn "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  OUTPUT_JUMP (\"jeq %l0\", \"fbeq %l0\", \"jeq %l0\");
-}")
-
-(define_insn "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  OUTPUT_JUMP (\"jne %l0\", \"fbneq %l0\", \"jne %l0\");
-}")
-
-(define_insn "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-  OUTPUT_JUMP (\"jgt %l0\", \"fbgt %l0\", \"and%.b %#0xc,%!\;jgt %l0\");
-")
-
-(define_insn "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-  return \"jhi %l0\";
-")
-
-(define_insn "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-  OUTPUT_JUMP (\"jlt %l0\", \"fblt %l0\", \"jmi %l0\");
-")
-
-(define_insn "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-  return \"jcs %l0\";
-")
-
-(define_insn "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-  OUTPUT_JUMP (\"jge %l0\", \"fbge %l0\", \"jpl %l0\");
-")
-
-(define_insn "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-  return \"jcc %l0\";
-")
-
-(define_insn "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-  OUTPUT_JUMP (\"jle %l0\", \"fble %l0\", \"and%.b %#0xc,%!\;jle %l0\");
-")
-
-(define_insn "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-  return \"jls %l0\";
-")
-
-;; Negated conditional jump instructions.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  OUTPUT_JUMP (\"jne %l0\", \"fbneq %l0\", \"jne %l0\");
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  OUTPUT_JUMP (\"jeq %l0\", \"fbeq %l0\", \"jeq %l0\");
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-  OUTPUT_JUMP (\"jle %l0\", \"fbngt %l0\", \"and%.b %#0xc,%!\;jle %l0\");
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-  return \"jls %l0\";
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-  OUTPUT_JUMP (\"jge %l0\", \"fbnlt %l0\", \"jpl %l0\");
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-  return \"jcc %l0\";
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-  OUTPUT_JUMP (\"jlt %l0\", \"fbnge %l0\", \"jmi %l0\");
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-  return \"jcs %l0\";
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-  OUTPUT_JUMP (\"jgt %l0\", \"fbnle %l0\", \"and%.b %#0xc,%!\;jgt %l0\");
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-  return \"jhi %l0\";
-")
-
-;; Subroutines of "casesi".
-
-(define_expand "casesi_1"
-  [(set (match_operand:SI 3 "general_operand" "")
-	(plus:SI (match_operand:SI 0 "general_operand" "")
-		 ;; Note operand 1 has been negated!
-		 (match_operand:SI 1 "immediate_operand" "")))
-   (set (cc0) (compare (match_operand:SI 2 "nonimmediate_operand" "")
-		       (match_dup 3)))
-   (set (pc) (if_then_else (ltu (cc0) (const_int 0))
-			   (label_ref (match_operand 4 "" "")) (pc)))]
-  ""
-  "")
-
-(define_expand "casesi_2"
-  [(set (match_operand:HI 0 "" "") (mem:HI (match_operand:SI 1 "" "")))
-   ;; The USE here is so that at least one jump-insn will refer to the label,
-   ;; to keep it alive in jump_optimize.
-   (parallel [(set (pc)
-		   (plus:SI (pc) (sign_extend:SI (match_dup 0))))
-	      (use (label_ref (match_operand 2 "" "")))])]
-  ""
-  "")
-
-;; Operand 0 is index (in bytes); operand 1 is minimum, operand 2 the maximum;
-;; operand 3 is CODE_LABEL for the table;
-;; operand 4 is the CODE_LABEL to go to if index out of range.
-(define_expand "casesi"
-  ;; We don't use these for generating the RTL, but we must describe
-  ;; the operands here.
-  [(match_operand:HI 0 "general_operand" "")
-   (match_operand:SI 1 "immediate_operand" "")
-   (match_operand:SI 2 "general_operand" "")
-   (match_operand 3 "" "")
-   (match_operand 4 "" "")]
-  ""
-  "
-{
-  rtx table_elt_addr;
-  rtx index_diff;
-
-  operands[1] = negate_rtx (SImode, operands[1]);
-  index_diff = gen_reg_rtx (SImode);
-  /* Emit the first few insns.  */
-  emit_insn (gen_casesi_1 (operands[0], operands[1], operands[2],
-			   index_diff, operands[4]));
-  /* Construct a memory address.  This may emit some insns.  */
-  table_elt_addr
-    = memory_address_noforce
-        (HImode,
-	 gen_rtx (PLUS, Pmode,
-		  gen_rtx (MULT, Pmode, index_diff,
-			   GEN_INT (2)),
-		  gen_rtx (LABEL_REF, VOIDmode, operands[3])));
-  /* Emit the last few insns.  */
-  emit_insn (gen_casesi_2 (gen_reg_rtx (HImode), table_elt_addr, operands[3]));
-  DONE;
-}")
-
-;; Recognize one of the insns resulting from casesi_2.
-(define_insn ""
-  [(set (pc)
-	(plus:SI (pc)
-		 (sign_extend:SI (match_operand:HI 0 "general_operand" "r"))))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "*
-  return \"jmp pc@(2:B)[%0:W:B]\";
-")
-
-;; Unconditional and other jump instructions
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "*
-  return \"jra %l0\";
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (match_operand:HI 0 "general_operand" "d,m,g")
-	     (const_int 0))
-	 (label_ref (match_operand 1 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:HI (match_dup 0)
-		 (const_int -1)))]
-  ""
-  "@
-   dbra %0,%l1
-   subq%.w %#1,%0\;jcc %l1
-   subq%.w %#1,%0\;cmp%.w %#-1,%0\;jne %l1")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (match_operand:SI 0 "general_operand" "d,m,g")
-	     (const_int 0))
-	 (label_ref (match_operand 1 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  ""
-  "@
-   dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jcc %l1
-   subq%.l %#1,%0\;jcc %l1
-   subq%.l %#1,%0\;cmp%.l %#-1,%0\;jne %l1")
-
-;; dbra patterns that use REG_NOTES info generated by strength_reduce.
-
-(define_expand "decrement_and_branch_until_zero"
-  [(parallel [(set (pc)
-		   (if_then_else
-		    (ge (match_operand:SI 0 "general_operand" "")
-			(const_int 1))
-		    (label_ref (match_operand 1 "" ""))
-		    (pc)))
-	      (set (match_dup 0)
-		   (plus:SI (match_dup 0)
-			    (const_int -1)))])]
-  ""
-  "")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	  (ge (match_operand:SI 0 "general_operand" "d,m,g")
-	      (const_int 1))
-	  (label_ref (match_operand 1 "" ""))
-	  (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  "find_reg_note (insn, REG_NONNEG, 0)"
-  "@
-   dbra %0,%l1\;clrw %0\;subql %#1,%0\;jcc %l1
-   subq%.l %#1,%0\;jcc %l1
-   subq%.l %#1,%0\;cmp%.l %#-1,%0\;jne %l1")
-
-;; Call subroutine with no return value.
-(define_insn "call"
-  [(call (match_operand:QI 0 "memory_operand" "o")
-	 (match_operand:SI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  rtx xoperands[2];
-  int size = XINT(operands[1],0);
-
-  if (size == 0) 
-    output_asm_insn (\"sub%.l a0,a0\;jbsr %0\", operands);
-  else
-  {
-    xoperands[1] = GEN_INT (size/4);
-    output_asm_insn (\"mov%.l sp,a0\;pea %a1\", xoperands);
-    output_asm_insn (\"jbsr %0\", operands);
-    size = size + 4;
-    xoperands[1] = GEN_INT (size);
-    if (size <= 8)
-      output_asm_insn (\"addq%.l %1,sp\", xoperands);
-    else if (size < 0x8000)
-      output_asm_insn (\"add%.w %1,sp\", xoperands);
-    else
-      output_asm_insn (\"add%.l %1,sp\", xoperands);
-  }
-  return \"mov%.l a6@(-4),a0\";
-}")
-
-;; Call subroutine, returning value in operand 0
-;; (which must be a hard register).
-(define_insn "call_value"
-  [(set (match_operand 0 "" "=rf")
-	(call (match_operand:QI 1 "memory_operand" "o")
-	      (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  rtx xoperands[3];
-  int size = XINT(operands[2],0);
-
-  if (size == 0)
-    output_asm_insn(\"sub%.l a0,a0\;jbsr %1\", operands);
-  else
-  {
-    xoperands[2] = GEN_INT (size/4);
-    output_asm_insn (\"mov%.l sp,a0\;pea %a2\", xoperands);
-    output_asm_insn (\"jbsr %1\", operands);
-    size = size + 4;
-    xoperands[2] = GEN_INT (size);
-    if (size <= 8)
-      output_asm_insn (\"addq%.l %2,sp\", xoperands);
-    else if (size < 0x8000)
-      output_asm_insn (\"add%.w %2,sp\", xoperands);
-    else
-      output_asm_insn (\"add%.l %2,sp\", xoperands);
-  }
-  return \"mov%.l a6@(-4),a0\";
-}")
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
-
-;; This should not be used unless the add/sub insns can't be.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=a")
-	(match_operand:QI 1 "address_operand" "p"))]
-  ""
-  "lea %a1,%0")
-
-;; This is the first machine-dependent peephole optimization.
-;; It is useful when a floating value is returned from a function call
-;; and then is moved into an FP register.
-;; But it is mainly intended to test the support for these optimizations.
-
-;Not applicable to Alliant -- floating results are returned in fp0
-;(define_peephole
-;  [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
-;   (set (match_operand:DF 0 "register_operand" "f")
-;	(match_operand:DF 1 "register_operand" "ad"))]
-;  "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
-;  "*
-;{
-;  rtx xoperands[2];
-;  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-;  output_asm_insn (\"mov%.l %1,%@\", xoperands);
-;  output_asm_insn (\"mov%.l %1,%-\", operands);
-;  return \"fmove%.d %+,%0\";
-;}
-;")
diff --git a/gcc/config/fx80/xm-fx80.h b/gcc/config/fx80/xm-fx80.h
deleted file mode 100755
index 178d762..0000000
--- a/gcc/config/fx80/xm-fx80.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Configuration for GNU C-compiler for Alliant FX computers.
-   Copyright (C) 1989, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
diff --git a/gcc/config/gmicro/gmicro.c b/gcc/config/gmicro/gmicro.c
deleted file mode 100755
index 0029ccc..0000000
--- a/gcc/config/gmicro/gmicro.c
+++ /dev/null
@@ -1,982 +0,0 @@
-/* Subroutines for insn-output.c for the Gmicro.
-   Ported by Masanobu Yuhara, Fujitsu Laboratories LTD.
-   (yuhara@flab.fujitsu.co.jp)
-
-   Copyright (C) 1990, 1991, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-Among other things, the copyright
-notice and this notice must be preserved on all copies.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-
-extern char *rtx_name[];
-
-mypr (s, a1, a2, a3, a4, a5)
-     char *s;
-     int a1, a2, a3, a4, a5;
-{
-  fprintf (stderr, s, a1, a2, a3, a4, a5);
-}
-
-myprcode (i)
-     int i;
-{
-  if (i < 0 || i > 90)
-    fprintf (stderr, "code = %d\n", i);
-  else
-    fprintf (stderr, "code = %s\n", rtx_name[i]);
-}
-
-myabort (i)
-     int i;
-{
-  fprintf (stderr, "myabort");
-  myprcode (i);
-}
-
-
-/* This is how to output an ascii string.  */
-/* See ASM_OUTPUT_ASCII in gmicro.h.  */
-output_ascii (file, p, size)
-     FILE *file;
-     char *p;
-     int size;
-{
-  int i;
-  int in_quote = 0;
-  register int c;
-
-  fprintf (file, "\t.sdata ");
-
-  for (i = 0; i < size; i++) 
-    {
-      c = p[i];
-      if (c >= ' ' && c < 0x7f) 
-	{
-	  if (!in_quote) 
-	    {
-	      putc ('"', file);
-	      in_quote = 1;
-	    }
-	  putc (c, file);
-	}
-      else 
-	{
-	  if (in_quote) 
-	    {
-	      putc ('"', file);
-	      in_quote = 0;
-	    }
-	  fprintf (file, "<%d>", c);
-	}
-    }
-  if (in_quote)
-    putc ('"', file);
-  putc ('\n', file);
-}
-
-
-/* call this when GET_CODE (index) is MULT. */
-print_scaled_index (file, index)
-     FILE *file;
-     register rtx index;
-{
-  register rtx ireg;
-  int scale;
-
-  if (GET_CODE (XEXP (index, 0)) == REG) 
-    {
-      ireg = XEXP (index, 0);
-      scale = INTVAL (XEXP (index, 1));
-    }
-  else 
-    {
-      ireg = XEXP (index, 1);
-      scale = INTVAL (XEXP (index, 0));
-    }
-  if (scale == 1)
-    fprintf (file, "%s", reg_names[REGNO (ireg)]);
-  else
-    fprintf (file, "%s*%d", reg_names[REGNO (ireg)], scale);
-}
-    
-
-print_operand_address (file, addr)
-     FILE *file;
-     register rtx addr;
-{
-  register rtx xtmp0, xtmp1, breg, ixreg;
-  int scale;
-  int needcomma = 0;
-  rtx offset;
-
-  fprintf (file, "@");
- retry:
-  switch (GET_CODE (addr)) 
-    {
-    case MEM:
-      fprintf (file, "@");
-      addr = XEXP (addr, 0);
-      goto retry;
-
-    case REG:
-      fprintf (file, "%s", reg_names[REGNO (addr)]);
-      break;
-
-    case MULT:
-      print_scaled_index (file, addr);
-      break;
-
-    case PRE_DEC:
-      fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case POST_INC:
-      fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case PLUS:
-      xtmp0 = XEXP (addr, 0);
-      xtmp1 = XEXP (addr, 1);
-      ixreg = 0;	breg = 0;
-      offset = 0;
-      if (CONSTANT_ADDRESS_P (xtmp0)) 
-	{
-	  offset = xtmp0;
-	  breg = xtmp1;
-	}
-      else if (CONSTANT_ADDRESS_P (xtmp1)) 
-	{
-	  offset = xtmp1;
-	  breg = xtmp0;
-	}
-      else 
-	{
-	  goto NOT_DISP;
-	}
-
-      if (REG_CODE_BASE_P (breg))
-	goto PRINT_MEM;
-
-      if (GET_CODE (breg) == MULT) 
-	{
-	  if (REG_CODE_INDEX_P (XEXP (breg, 0))) 
-	    {
-	      ixreg = XEXP (breg, 0);
-	      scale = INTVAL (XEXP (breg, 1));
-	      breg = 0;
-	    }
-	  else 
-	    {
-	      ixreg = XEXP (breg, 1);
-	      scale = INTVAL (XEXP (breg, 0));
-	      breg = 0;
-	    }
-	  goto PRINT_MEM;
-	}
-
-      /* GET_CODE (breg) must be PLUS here. */
-      xtmp0 = XEXP (breg, 0);
-      xtmp1 = XEXP (breg, 1);
-      if (REG_CODE_BASE_P (xtmp0)) 
-	{
-	  breg = xtmp0;
-	  xtmp0 = xtmp1;
-	}
-      else 
-	{
-	  breg = xtmp1;
-	  /* xtmp0 = xtmp0; */
-	}
-
-      if (GET_CODE (xtmp0) == MULT) 
-	{
-	  if (REG_CODE_INDEX_P (XEXP (xtmp0, 0))) 
-	    {
-	      ixreg = XEXP (xtmp0, 0);
-	      scale = INTVAL (XEXP (xtmp0, 1));
-	    }
-	  else 
-	    {
-	      ixreg = XEXP (xtmp0, 1);
-	      scale = INTVAL (XEXP (xtmp0, 0));
-	    }
-	}
-      else 
-	{
-	  ixreg = xtmp0;
-	  scale = 1;
-	}
-      goto PRINT_MEM;
-
-    NOT_DISP:
-      if (REG_CODE_BASE_P (xtmp0)) 
-	{
-	  breg = xtmp0;
-	  xtmp0 = xtmp1;
-	}
-      else if (REG_CODE_BASE_P (xtmp1)) 
-	{
-	  breg = xtmp1;
-	  /* xtmp0 = xtmp0; */
-	}
-      else
-	goto NOT_BASE;
-    
-      if (REG_CODE_INDEX_P (xtmp0)) 
-	{
-	  ixreg = xtmp0;
-	  scale = 1;
-	  goto PRINT_MEM;
-	}
-      else if (CONSTANT_ADDRESS_P (xtmp0)) 
-	{
-	  offset = xtmp0;
-	  goto PRINT_MEM;
-	}
-      else if (GET_CODE (xtmp0) == MULT) 
-	{
-	  if (REG_CODE_INDEX_P (XEXP (xtmp0, 0))) 
-	    {
-	      ixreg = XEXP (xtmp0, 0);
-	      scale = INTVAL (XEXP (xtmp0, 1));
-	    }
-	  else 
-	    {
-	      ixreg = XEXP (xtmp0, 1);
-	      scale = INTVAL (XEXP (xtmp0, 0));
-	    }
-	  goto PRINT_MEM;
-	}
-
-      /* GET_CODE (xtmp0) must be PLUS. */
-      xtmp1 = XEXP (xtmp0, 1);
-      xtmp0 = XEXP (xtmp0, 0);
-
-      if (CONSTANT_ADDRESS_P (xtmp0)) 
-	{
-	  offset = xtmp0;
-	  xtmp0 = xtmp1;
-	}
-      else 
-	{
-	  offset = xtmp1;
-	  /* xtmp0 = xtmp0; */
-	}
-
-      if (REG_CODE_INDEX_P (xtmp0)) 
-	{
-	  ixreg = xtmp0;
-	}
-      else 
-	{			/* GET_CODE (xtmp0) must be MULT. */
-	  if (REG_CODE_INDEX_P (XEXP (xtmp0, 0))) 
-	    {
-	      ixreg = XEXP (xtmp0, 0);
-	      scale = INTVAL (XEXP (xtmp0, 1));
-	    }
-	  else 
-	    {
-	      ixreg = XEXP (xtmp0, 1);
-	      scale = INTVAL (XEXP (xtmp0, 0));
-	    }
-	}
-      goto PRINT_MEM;
-
-    NOT_BASE:
-      if (GET_CODE (xtmp0) == PLUS) 
-	{
-	  ixreg = xtmp1;
-	  /* xtmp0 = xtmp0; */
-	}
-      else 
-	{
-	  ixreg = xtmp0;
-	  xtmp0 = xtmp1;
-	}
-
-      if (REG_CODE_INDEX_P (ixreg)) 
-	{
-	  scale = 1;
-	}
-      else if (REG_CODE_INDEX_P (XEXP (ixreg, 0))) 
-	{
-	  scale = INTVAL (XEXP (ixreg, 1));
-	  ixreg = XEXP (ixreg, 0);
-	}
-      else 
-	{			/* was else if with no condition. OK ??? */
-	  scale = INTVAL (XEXP (ixreg, 0));
-	  ixreg = XEXP (ixreg, 1);
-	}
-
-      if (REG_CODE_BASE_P (XEXP (xtmp0, 0))) 
-	{
-	  breg = XEXP (xtmp0, 0);
-	  offset = XEXP (xtmp0, 1);
-	}
-      else 
-	{
-	  breg = XEXP (xtmp0, 1);
-	  offset = XEXP (xtmp0, 0);
-	}
-
-    PRINT_MEM:
-      if (breg == 0 && ixreg == 0) 
-	{
-	  output_address (offset);
-	  break;
-	}
-      else if (ixreg == 0 && offset == 0) 
-	{
-	  fprintf (file, "%s", reg_names[REGNO (breg)]);
-	  break;
-	}
-      else 
-	{
-	  fprintf (file, "(");
-	  if (offset != 0) 
-	    {
-	      output_addr_const (file, offset);
-	      needcomma = 1;
-	    }
-	  if (breg != 0) 
-	    {
-	      if (needcomma)
-		fprintf (file, ",");
-	      fprintf (file, "%s", reg_names[REGNO (breg)]);
-	      needcomma = 1;
-	    }
-	  if (ixreg != 0) 
-	    {
-	      if (needcomma)
-		fprintf (file, ",");
-	      fprintf (file, "%s", reg_names[REGNO (ixreg)]);
-	      if (scale != 1)
-		fprintf (file,"*%d", scale);
-	    }
-	  fprintf (file, ")");
-
-	  break;
-	}
-
-    default:
-      output_addr_const (file, addr);
-    }
-}
-
-
-
-/* Return a REG that occurs in ADDR with coefficient 1.
-   ADDR can be effectively incremented by incrementing REG.  */
-
-static rtx
-find_addr_reg (addr)
-     rtx addr;
-{
-  while (GET_CODE (addr) == PLUS)
-    {
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-	addr = XEXP (addr, 0);
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	addr = XEXP (addr, 1);
-      else if (GET_CODE (XEXP (addr, 0)) == PLUS)
-	addr = XEXP (addr, 0);
-      else if (GET_CODE (XEXP (addr, 1)) == PLUS)
-	addr = XEXP (addr, 1);
-    }
-  if (GET_CODE (addr) == REG)
-    return addr;
-  return 0;
-}
-
-
-    /* Return the best assembler insn template
-    for moving operands[1] into operands[0] as a fullword.  */
-
-static char *
-singlemove_string (operands)
-     rtx *operands;
-{
-  if (FPU_REG_P (operands[0]) || FPU_REG_P (operands[1])) 
-    {
-      if (GREG_P (operands[0]) || GREG_P (operands[1])) 
-	{
-	  myabort (101);	/* Not Supported yet !! */
-	}
-      else 
-	{
-	  return "fmov.s %1,%0";
-	}
-    }
-  return "mov.w %1,%0";
-}
-
-
-/* Output assembler code to perform a doubleword move insn
-   with operands OPERANDS.  */
-
-char *
-output_move_double (operands)
-     rtx *operands;
-{
-  enum 
-    { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP }
-  optype0, optype1;
-  rtx latehalf[2];
-  rtx addreg0 = 0, addreg1 = 0;
-
-  /* First classify both operands.  */
-
-  if (REG_P (operands[0]))
-    optype0 = REGOP;
-  else if (offsettable_memref_p (operands[0]))
-    optype0 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    optype0 = POPOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    optype0 = PUSHOP;
-  else if (GET_CODE (operands[0]) == MEM)
-    optype0 = MEMOP;
-  else
-    optype0 = RNDOP;
-
-  if (REG_P (operands[1]))
-    optype1 = REGOP;
-  else if (CONSTANT_P (operands[1]))
-    optype1 = CNSTOP;
-  else if (offsettable_memref_p (operands[1]))
-    optype1 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
-    optype1 = POPOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
-    optype1 = PUSHOP;
-  else if (GET_CODE (operands[1]) == MEM)
-    optype1 = MEMOP;
-  else
-    optype1 = RNDOP;
-
-  /* Check for the cases that the operand constraints are not
-     supposed to allow to happen.  Abort if we get one,
-     because generating code for these cases is painful.  */
-
-  if (optype0 == RNDOP || optype1 == RNDOP)
-    myabort (102);
-
-  /* If one operand is decrementing and one is incrementing
-     decrement the former register explicitly
-     and change that operand into ordinary indexing.  */
-
-  if (optype0 == PUSHOP && optype1 == POPOP)
-    {
-      operands[0] = XEXP (XEXP (operands[0], 0), 0);
-      output_asm_insn ("sub.w %#8,%0", operands);
-      operands[0] = gen_rtx (MEM, DImode, operands[0]);
-      optype0 = OFFSOP;
-    }
-  if (optype0 == POPOP && optype1 == PUSHOP)
-    {
-      operands[1] = XEXP (XEXP (operands[1], 0), 0);
-      output_asm_insn ("sub.w %#8,%1", operands);
-      operands[1] = gen_rtx (MEM, DImode, operands[1]);
-      optype1 = OFFSOP;
-    }
-
-  /* If an operand is an unoffsettable memory ref, find a register
-     we can increment temporarily to make it refer to the second word.  */
-
-  if (optype0 == MEMOP)
-    addreg0 = find_addr_reg (operands[0]);
-
-  if (optype1 == MEMOP)
-    addreg1 = find_addr_reg (operands[1]);
-
-  /* Ok, we can do one word at a time.
-     Normally we do the low-numbered word first,
-     but if either operand is autodecrementing then we
-     do the high-numbered word first.
-     
-     In either case, set up in LATEHALF the operands to use
-     for the high-numbered word and in some cases alter the
-     operands in OPERANDS to be suitable for the low-numbered word.  */
-
-  if (optype0 == REGOP)
-    latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  else if (optype0 == OFFSOP)
-    latehalf[0] = adj_offsettable_operand (operands[0], 4);
-  else
-    latehalf[0] = operands[0];
-
-  if (optype1 == REGOP)
-    latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-  else if (optype1 == OFFSOP)
-    latehalf[1] = adj_offsettable_operand (operands[1], 4);
-  else if (optype1 == CNSTOP)
-    {
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	split_double (operands[1], &operands[1], &latehalf[1]);
-      else if (CONSTANT_P (operands[1]))
-	latehalf[1] = const0_rtx;
-    }
-  else
-    latehalf[1] = operands[1];
-
-  /* If insn is effectively movd N(sp),-(sp) then we will do the
-     high word first.  We should use the adjusted operand 1 (which is N+4(sp))
-     for the low word as well, to compensate for the first decrement of sp.  */
-  if (optype0 == PUSHOP
-      && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
-      && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
-    operands[1] = latehalf[1];
-
-  /* If one or both operands autodecrementing,
-     do the two words, high-numbered first.  */
-
-  /* Likewise,  the first move would clobber the source of the second one,
-     do them in the other order.  This happens only for registers;
-     such overlap can't happen in memory unless the user explicitly
-     sets it up, and that is an undefined circumstance.  */
-
-  if (optype0 == PUSHOP || optype1 == PUSHOP
-      || (optype0 == REGOP && optype1 == REGOP
-	  && REGNO (operands[0]) == REGNO (latehalf[1])))
-    {
-      /* Make any unoffsettable addresses point at high-numbered word.  */
-      if (addreg0)
-	output_asm_insn ("add.w %#4,%0", &addreg0);
-      if (addreg1)
-	output_asm_insn ("add.w %#4,%0", &addreg1);
-
-      /* Do that word.  */
-      output_asm_insn (singlemove_string (latehalf), latehalf);
-
-      /* Undo the adds we just did.  */
-      if (addreg0)
-	output_asm_insn ("sub.w %#4,%0", &addreg0);
-      if (addreg1)
-	output_asm_insn ("sub.w %#4,%0", &addreg1);
-
-      /* Do low-numbered word.  */
-      return singlemove_string (operands);
-    }
-
-  /* Normal case: do the two words, low-numbered first.  */
-
-  output_asm_insn (singlemove_string (operands), operands);
-
-  /* Make any unoffsettable addresses point at high-numbered word.  */
-  if (addreg0)
-    output_asm_insn ("add.w %#4,%0", &addreg0);
-  if (addreg1)
-    output_asm_insn ("add.w %#4,%0", &addreg1);
-
-  /* Do that word.  */
-  output_asm_insn (singlemove_string (latehalf), latehalf);
-
-  /* Undo the adds we just did.  */
-  if (addreg0)
-    output_asm_insn ("sub.w %#4,%0", &addreg0);
-  if (addreg1)
-    output_asm_insn ("sub.w %#4,%0", &addreg1);
-
-  return "";
-}
-
-/* Move const_double to floating point register (DF) */
-char *
-output_move_const_double (operands)
-     rtx *operands;
-{
-  int code = standard_fpu_constant_p (operands[1]);
-
-  if (FPU_REG_P (operands[0])) 
-    {
-      if (code != 0)
-	{
-	  static char buf[40];
-
-	  sprintf (buf, "fmvr from%d,%%0.d", code);
-	  return buf;
-	}
-      else 
-	{
-	  return "fmov %1,%0.d";
-	}
-    }
-  else if (GREG_P (operands[0])) 
-    {
-      rtx xoperands[2];
-      xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-      xoperands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
-      output_asm_insn ("mov.w %1,%0", xoperands);
-      operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-      return "mov.w %1,%0";
-    }
-  else 
-    {
-      return output_move_double (operands); /* ?????? */
-    }
-}
-
-char *
-output_move_const_single (operands)
-     rtx *operands;
-{
-  int code = standard_fpu_constant_p (operands[1]);
-  static char buf[40];
-
-  if (FPU_REG_P (operands[0])) 
-    {
-      if (code != 0)
-	{
-	  sprintf (buf, "fmvr from%d,%%0.s", code);
-	  return buf;
-	}
-      return "fmov.s %f1,%0";
-    }
-  else 
-    return "mov.w %f1,%0";
-}
-
-
-/* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
-   from the "fmvr" instruction of the Gmicro FPU.
-   The value, anded with 0xff, gives the code to use in fmovecr
-   to get the desired constant.  */
-
-  u.i[0] = CONST_DOUBLE_LOW (x);
-  u.i[1] = CONST_DOUBLE_HIGH (x);
-  d = u.d;
-
-  if (d == 0.0)			/* +0.0 */
-    return 0x0;
-  /* Note: there are various other constants available
-     but it is a nuisance to put in their values here.  */
-  if (d == 1.0)			/* +1.0 */
-    return 0x1;
-
-  /*
-   * Stuff that looks different if it's single or double
-   */
-  if (GET_MODE (x) == SFmode)
-    {
-      if (d == S_PI)
-	return 0x2;
-      if (d == (S_PI / 2.0))
-	return 0x3;
-      if (d == S_E)
-	return 0x4;
-      if (d == S_LOGEof2)
-	return 0x5;
-      if (d == S_LOGEof10)
-	return 0x6;
-      if (d == S_LOG10of2)
-	return 0x7;
-      if (d == S_LOG10ofE)
-	return 0x8;
-      if (d == S_LOG2ofE)
-	return 0x9;
-    }
-  else
-    {
-      if (d == D_PI)
-	return 0x2;
-      if (d == (D_PI / 2.0))
-	return 0x3;
-      if (d == D_E)
-	return 0x4;
-      if (d == D_LOGEof2)
-	return 0x5;
-      if (d == D_LOGEof10)
-	return 0x6;
-      if (d == D_LOG10of2)
-	return 0x7;
-      if (d == D_LOG10ofE)
-	return 0x8;
-      if (d == D_LOG2ofE)
-	return 0x9;
-    }
-
-  return 0;
-}
-
-#undef S_PI
-#undef D_PI
-#undef S_E
-#undef D_E
-#undef S_LOGEof2
-#undef D_LOGEof2
-#undef S_LOGEof10
-#undef D_LOGEof10
-#undef S_LOG10of2
-#undef D_LOG10of2
-#undef S_LOG10ofE
-#undef D_LOG10ofE
-#undef S_LOG2ofE
-#undef D_LOG2ofE
-
-/* dest should be operand 0 */
-/* imm should be operand 1 */
-
-extern char *sub_imm_word ();
-
-char *
-add_imm_word (imm, dest, immp)
-     int imm;
-     rtx dest, *immp;
-{
-  int is_reg, short_ok;
-
-
-  if (imm < 0) 
-    {
-      *immp = GEN_INT (-imm);
-      return sub_imm_word (-imm, dest);
-    }
-    
-  if (imm == 0)
-    return "mov:l.w #0,%0";
-    
-  short_ok = short_format_ok (dest);
-
-  if (short_ok && imm <= 8)
-    return "add:q %1,%0.w";
-
-  if (imm < 128)
-    return "add:e %1,%0.w";
-
-  is_reg = (GET_CODE (dest) == REG);
-
-  if (is_reg)
-    return "add:l %1,%0.w";
-    
-  if (short_ok)
-    return "add:i %1,%0.w";
-    
-  return "add %1,%0.w";
-}
-
-char *
-sub_imm_word (imm, dest, immp)
-     int imm;
-     rtx dest, *immp;
-{
-  int is_reg, short_ok;
-
-  if (imm < 0 &&  imm != 0x80000000) 
-    {
-      *immp = GEN_INT (-imm);
-      return add_imm_word (-imm, dest);
-    }
-    
-  if (imm == 0)
-    return "mov:z.w #0,%0";
-    
-  short_ok = short_format_ok (dest);
-
-  if (short_ok && imm <= 8)
-    return "sub:q %1,%0.w";
-
-  if (imm < 128)
-    return "sub:e %1,%0.w";
-
-  is_reg = (GET_CODE (dest) == REG);
-
-  if (is_reg)
-    return "sub:l %1,%0.w";
-    
-  if (short_ok)
-    return "sub:i %1,%0.w";
-    
-  return "sub %1,%0.w";
-}
-
-int
-short_format_ok (x)
-     rtx x;
-{
-  rtx x0, x1;
-
-  if (GET_CODE (x) == REG)
-    return 1;
-
-  if (GET_CODE (x) == MEM 
-      && GET_CODE (XEXP (x, 0)) == PLUS) 
-    {
-      x0 = XEXP (XEXP (x, 0), 0);
-      x1 = XEXP (XEXP (x, 0), 1);
-      return ((GET_CODE (x0) == REG
-	       && CONSTANT_P (x1)
-	       && ((unsigned) (INTVAL (x1) + 0x8000)  < 0x10000))
-	      ||
-	      (GET_CODE (x1) == REG
-	       && CONSTANT_P (x0)
-	       && ((unsigned) (INTVAL (x0) + 0x8000)  < 0x10000)));
-    }
-
-  return 0;
-}
-
-myoutput_sp_adjust (file, op, fsize)
-     FILE *file;
-     char *op;
-     int fsize;
-{
-  if (fsize == 0)
-    ;
-  else if (fsize < 8)
-    fprintf (file, "\t%s:q #%d,sp.w\n", op, fsize);
-  else if (fsize < 128)
-    fprintf (file, "\t%s:e #%d,sp.w\n", op, fsize);
-  else
-    fprintf (file, "\t%s:l #%d,sp.w\n", op, fsize);
-}
-
-
-char *
-mov_imm_word (imm, dest)
-     int imm;
-     rtx dest;
-{
-  int is_reg, short_ok;
-
-  if (imm == 0)
-    return "mov:z.w #0,%0";
-    
-  short_ok = short_format_ok (dest);
-
-  if (short_ok && imm > 0 && imm <= 8)
-    return "mov:q %1,%0.w";
-
-  if (-128 <= imm && imm < 128)
-    return "mov:e %1,%0.w";
-
-  is_reg = (GET_CODE (dest) == REG);
-
-  if (is_reg)
-    return "mov:l %1,%0.w";
-    
-  if (short_ok)
-    return "mov:i %1,%0.w";
-    
-  return "mov %1,%0.w";
-}
-
-char *
-cmp_imm_word (imm, dest)
-     int imm;
-     rtx dest;
-{
-  int is_reg, short_ok;
-
-  if (imm == 0)
-    return "cmp:z.w #0,%0";
-    
-  short_ok = short_format_ok (dest);
-
-  if (short_ok && imm >0 && imm <= 8)
-    return "cmp:q %1,%0.w";
-
-  if (-128 <= imm && imm < 128)
-    return "cmp:e %1,%0.w";
-
-  is_reg = (GET_CODE (dest) == REG);
-
-  if (is_reg)
-    return "cmp:l %1,%0.w";
-    
-  if (short_ok)
-    return "cmp:i %1,%0.w";
-    
-  return "cmp %1,%0.w";
-}
-
-char *
-push_imm_word (imm)
-     int imm;
-{
-  if (imm == 0)
-    return "mov:z.w #0,%-";
-    
-  if (imm > 0 && imm <= 8)
-    return "mov:q %1,%-.w";
-
-  if (-128 <= imm && imm < 128)
-    return "mov:e %1,%-.w";
-
-  return "mov:g %1,%-.w";
-    
-  /* In some cases, g-format may be better than I format.??
-     return "mov %1,%0.w";
-     */
-}
-
-my_signed_comp (insn)
-     rtx insn;
-{
-  rtx my_insn;
-
-  my_insn = NEXT_INSN (insn);
-  if (GET_CODE (my_insn) != JUMP_INSN) 
-    {
-      fprintf (stderr, "my_signed_comp: Not Jump_insn ");
-      myabort (GET_CODE (my_insn));
-    }
-  my_insn = PATTERN (my_insn);
-  if (GET_CODE (my_insn) != SET) 
-    {
-      fprintf (stderr, "my_signed_comp: Not Set ");
-      myabort (GET_CODE (my_insn));
-    }
-  my_insn = SET_SRC (my_insn);
-  if (GET_CODE (my_insn) != IF_THEN_ELSE) 
-    {
-      fprintf (stderr, "my_signed_comp: Not if_then_else ");
-      myabort (GET_CODE (my_insn));
-    }
-  switch (GET_CODE (XEXP (my_insn, 0)))
-    {
-    case NE:
-    case EQ:
-    case GE:
-    case GT:
-    case LE:
-    case LT:
-      return 1;
-    case GEU:
-    case GTU:
-    case LEU:
-    case LTU:
-      return 0;
-    }
-  fprintf (stderr, "my_signed_comp: Not cccc ");
-  myabort (GET_CODE (XEXP (my_insn, 0)));
-}
diff --git a/gcc/config/gmicro/gmicro.h b/gcc/config/gmicro/gmicro.h
deleted file mode 100755
index 789ca84..0000000
--- a/gcc/config/gmicro/gmicro.h
+++ /dev/null
@@ -1,1588 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Gmicro (TRON) version.
-   Copyright (C) 1987, 88, 89, 95, 96, 1997 Free Software Foundation, Inc.
-   Contributed by Masanobu Yuhara, Fujitsu Laboratories LTD.
-   (yuhara@flab.fujitsu.co.jp)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.   */
-
-
-/* Note that some other tm.h files include this one and then override
-   many of the definitions that relate to assembler syntax.  */
-
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dgmicro -Acpu(tron) -Amachine(tron)"
-
-/* #define CPP_SPEC    ** currently not defined **/
-
-/* #define CC1_SPEC    ** currently not defined **/
-
-
-/* Print subsidiary information on the compiler version in use.  */
-/*
-#define TARGET_VERSION fprintf (stderr, " (Gmicro syntax)");
-*/
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Compile for a Gmicro/300.  */
-#define TARGET_G300 (target_flags & 1)
-/* Compile for a Gmicro/200. */
-#define TARGET_G200 (target_flags & 2)
-/* Compile for a Gmicro/100. */
-#define TARGET_G100 (target_flags & 4)
-
-/* Compile FPU insns for floating point (not library calls).  */
-#define TARGET_FPU (target_flags & 8)
-
-/* Pop up arguments by called function. */
-#define TARGET_RTD (target_flags & 0x10)
-
-/* Compile passing first args in regs 0 and 1.
-   This exists only to test compiler features that will be needed for
-   RISC chips. It is not usable and is not intended to be usable on
-   this cpu ;-< */
-#define TARGET_REGPARM (target_flags & 0x20)
-
-#define TARGET_BITFIELD (target_flags & 0x40)
-
-#define TARGET_NEWRETURN (target_flags & 0x80)
-
-/* Do not expand __builtin_smov (strcpy) to multiple movs.
-   Use the smov instruction. */
-#define TARGET_FORCE_SMOV (target_flags & 0x100)
-
-/* default options are -m300, -mFPU,
-   with bitfield instructions added because it won't always work otherwise.
-   If there are versions of the gmicro that don't support bitfield instructions
-   then it will take some thinking to figure out how to make them work.  */
-#define TARGET_DEFAULT 0x49
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  { { "g300", 1},				\
-    { "g200", 2},				\
-    { "g100", 4},				\
-    { "fpu", 8},				\
-    { "soft-float", -8},			\
-    { "rtd", 0x10},				\
-    { "no-rtd", -0x10},				\
-    { "regparm", 0x20},				\
-    { "no-regparm", -0x20},			\
-#if 0 /* Since we don't define PCC_BITFIELD_TYPE_MATTERS or use a large
-	 STRUCTURE_SIZE_BOUNDARY, we must have bitfield instructions.  */
-    { "bitfield", 0x40},			\
-    { "no-bitfield", -0x40},			\
-#endif
-    { "newreturn", 0x80},			\
-    { "no-newreturn", -0x80},			\
-    { "force-smov", 0x100},			\
-    { "no-force-smov", -0x100},			\
-    { "", TARGET_DEFAULT}}
-
-
-/* Blow away G100 flag silently off TARGET_fpu (since we can't clear
-   any bits in TARGET_SWITCHES above) */
-#define OVERRIDE_OPTIONS		\
-{					\
-  if (TARGET_G100) target_flags &= ~8;	\
-}
-
-/* target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is true for Gmicro insns.
-   We make it true always by avoiding using the single-bit insns
-   except in special cases with constant bit numbers.  */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is true on the Gmicro.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.  */
-/* For Gmicro we can decide arbitrarily
-   since there are no machine instructions for them.  ????? */
-#define WORDS_BIG_ENDIAN 0
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register. */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-/* Instructions of the Gmicro should be on half-word boundary */
-/* But word boundary gets better performance */
-#define FUNCTION_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* No data type wants to be aligned rounder than this. */
-/* This is not necessarily 32 on the Gmicro */
-#define BIGGEST_ALIGNMENT 32
-
-/* Set this non-zero if move instructions will actually fail to work
-   when given unaligned data.
-   Unaligned data is allowed on Gmicro, though the access is slow. */
-
-#define STRICT_ALIGNMENT 1
-#define SLOW_UNALIGNED_ACCESS 1
-
-/* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  (TREE_CODE (EXP) == STRING_CST	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Define number of bits in most basic integer type.
-   (If undefined, default is BITS_PER_WORD).  */
-#define INT_TYPE_SIZE 32
-
-/* #define PCC_BITFIELD_TYPE_MATTERS 1 ????? */
-
-/* #define CHECK_FLOAT_VALUE (MODE, VALUE) ????? */
-
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-   For the Gmicro, we give the general registers numbers 0-15,
-   and the FPU floating point registers numbers 16-31.  */
-#define FIRST_PSEUDO_REGISTER 32
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   On the Gmicro, the stack pointer and the frame pointer are
-   such registers.  */
-/* frame pointer is not indicated as fixed, because fp may be used freely
-   when a frame is not built. */
-#define FIXED_REGISTERS  \
- {0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 1, \
-  /* FPU registers.  */   \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, }
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS \
- {1, 1, 1, 1, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 1, \
-  /* FPU registers.  */   \
-  1, 1, 1, 1, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, }
-
-
-/* Make sure everything's fine if we *don't* have a given processor.
-   This assumes that putting a register in fixed_regs will keep the
-   compilers mitt's completely off it.  We don't bother to zero it out
-   of register classes.  If TARGET_FPU is not set,
-   the compiler won't touch since no instructions that use these
-   registers will be valid.  */
-/*  This Macro is not defined now.
-    #define CONDITIONAL_REGISTER_USAGE */
-
-/* The Gmicro has no overlapping register */
-/* #define OVERLAPPING_REGNO_P(REGNO) */
-
-/* #define INSN_CLOBBERS_REGNO_P(INSN,REGNO)  */
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On the Gmicro, ordinary registers hold 32 bits worth;
-   for the Gmicro/FPU registers, a single register is always enough for
-   anything that can be stored in them at all.  */
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((REGNO) >= 16 ? 1				\
-   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On the Gmicro, the cpu registers can hold any mode but the FPU registers
-   can hold only SFmode or DFmode.  And the FPU registers can't hold anything
-   if FPU use is disabled. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-  ((REGNO) < 16								\
-   || ((REGNO) < 32							\
-       ? TARGET_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT ||		\
-			GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)	\
-       : 0 ))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2)			\
-  (! TARGET_FPU						\
-   || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||		\
-	GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)	\
-       == ((MODE2) == SFmode || (MODE2) == DFmode)))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* Gmicro pc isn't overloaded on a register.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 15
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 14
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function.  */
-/* The Gmicro does not have hardware ap. Fp is treated as ap */
-#define ARG_POINTER_REGNUM 14
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 0
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 1
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-/* The Gmicro has two kinds of registers, so four classes would be
-   a complete set.  */
-
-enum reg_class { NO_REGS, FPU_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
-   { "NO_REGS", "FPU_REGS", "GENERAL_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS \
-{						\
-     0,			/* NO_REGS */		\
-     0xffff0000,	/* FPU_REGS */		\
-     0x0000ffff,	/* GENERAL_REGS */	\
-     0xffffffff		/* ALL_REGS */		\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-extern enum reg_class regno_reg_class[];
-#define REGNO_REG_CLASS(REGNO) ( (REGNO < 16) ? GENERAL_REGS : FPU_REGS )
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS  GENERAL_REGS
-  
-/* Get reg_class from a letter such as appears in the machine description.
-   We do a trick here to modify the effective constraints on the
-   machine description; we zorch the constraint letters that aren't
-   appropriate for a specific target.  This allows us to guarantee
-   that a specific kind of register will not be used for a given target
-   without fiddling with the register classes above. */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'r' ? GENERAL_REGS :			\
-   ((C) == 'f' ? (TARGET_FPU ? FPU_REGS : NO_REGS) :	\
-     NO_REGS))
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   For the Gmicro, all immediate value optimizations are done 
-   by assembler, so no machine dependent definition is necessary ??? */
-
-/* #define CONST_OK_FOR_LETTER_P(VALUE, C) ((C) == 'I') */
-#define CONST_OK_FOR_LETTER_P(VALUE, C) 0
-
-/*
- * The letters G defines all of the floating constants tha are *NOT*
- * Gmicro-FPU constant.
- */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)	\
-    ((C) == 'F' ||				\
-     (C) == 'G' && !(TARGET_FPU && standard_fpu_constant_p (VALUE)))
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class. */
-/* On the Gmicro series, there is no restriction on GENERAL_REGS,
-   so CLASS is returned. I do not know whether I should treat FPU_REGS
-   specially or not (at least, m68k does not). */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-/* On the Gmicro, this is the size of MODE in words,
-   except in the FPU regs, where a single reg is always enough.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- ((CLASS) == FPU_REGS ? \
-   1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-/* On the Gmicro, FP points to the old FP and the first local variables are
-   at (FP - 4). */
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by. */
-/* On the Gmicro, sp is decremented by the exact size of the operand */
-#define PUSH_ROUNDING(BYTES) (BYTES)
-
-/* Offset of first parameter from the argument pointer register value.  */
-/* On the Gmicro, the first argument is found at (ap + 8) where ap is fp. */
-#define FIRST_PARM_OFFSET(FNDECL) 8
-
-/* Value is the number of byte of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack. 
-
-   On the Gmicro, the EXITD insn may be used to pop them if the number
-   of args is fixed, but if the number is variable then the caller must pop
-   them all. The adjsp operand of the EXITD insn can't be used for library
-   calls now because the library is compiled with the standard compiler.
-   Use of adjsp operand is a selectable option, since it is incompatible with
-   standard Unix calling sequences.  If the option is not selected,
-   the caller must always pop the args.
-   On the m68k this is an RTD option, so I use the same name
-   for the Gmicro. The option name may be changed in the future. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE)   \
-  ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE)	\
-    && (TYPE_ARG_TYPES (FUNTYPE) == 0				\
-	|| (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE)))	\
-	    == void_type_node)))					\
-   ? (SIZE) : 0)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-/* On the Gmicro the floating return value is in fr0 not r0.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  LIBCALL_VALUE (TYPE_MODE (VALTYPE))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE)	\
-  (gen_rtx (REG, (MODE),		\
-    ((TARGET_FPU && ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0)))
-
-
-/* 1 if N is a possible register number for a function value.
-   On the Gmicro, r0 and fp0 are the possible registers.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 16)
-
-/* Define this if PCC uses the nonreentrant convention for returning
-   structure and union values.  */
-
-#define PCC_STATIC_STRUCT_RETURN
-
-/* 1 if N is a possible register number for function argument passing.
-   On the Gmicro, no registers are used in this way.  */
-/* Really? For the performance improvement, registers should be used !! */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the Gmicro, this is a single integer, which is a number of bytes
-   of arguments scanned so far.  */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the Gmicro, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM) += ((MODE) != BLKmode			\
-	    ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
-	    : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On the Gmicro all args are pushed, except if -mregparm is specified
-   then the first two words of arguments are passed in d0, d1.
-   *NOTE* -mregparm does not work.
-   It exists only to test register calling conventions.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-((TARGET_REGPARM && (CUM) < 8					\
-  && 8 < ((CUM) + ((MODE) == BLKmode				\
-		      ? int_size_in_bytes (TYPE)		\
-		      : GET_MODE_SIZE (MODE))))  		\
- ? 2 - (CUM) / 4 : 0)
-
-/* The following macro is defined to output register list.
-   The LSB of Mask is the lowest number register.
-   Regoff is MY_GREG_OFF or MY_FREG_OFF.
-   Do NOT use <i> in File, Mask, Regoff !!
-   Should be changed from macros to functions.    M.Yuhara */
-
-#define MY_GREG_OFF 0
-#define MY_FREG_OFF 16
-
-#define MY_PRINT_MASK(File, Mask, Regoff)		\
-{							\
-    int i, first = -1;					\
-    if ((Mask) == 0) {					\
-	fprintf(File, "#0");				\
-    } else {						\
-	fprintf(File, "(");				\
-	for (i = 0; i < 16; i++) {			\
-	    if ( (Mask) & (1 << i) ) {			\
-		if (first < 0) {			\
-		    if (first == -2) {			\
-			fprintf(File, ",");		\
-		    }					\
-		    first = i;				\
-		    fprintf(File, "%s", reg_names[Regoff + i]);	\
-		}					\
-	    } else if (first >= 0) {			\
-		if (i > first + 1) {			\
-		    fprintf(File, "-%s", reg_names[Regoff + i - 1]);	\
-		}					\
-		first = -2;				\
-	    }						\
-	}						\
-	if ( (first >= 0) && (first != 15) )		\
-	    fprintf(File, "-%s", reg_names[Regoff + 15]);\
-	fprintf(File, ")");				\
-    }							\
-}
-
-
-#define MY_PRINT_ONEREG_L(FILE,MASK)		\
-{   register int i;				\
-    for (i = 0; i < 16; i++)			\
-	if ( (1 << i) & (MASK)) {		\
-	    fprintf(FILE, "%s", reg_names[i]);	\
-	    (MASK) &= ~(1 << i);		\
-	    break;				\
-	}					\
-}
-
-
-#define MY_PRINT_ONEREG_H(FILE,MASK)		\
-{   register int i;				\
-    for (i = 15; i >= 0; i--)			\
-	if ( (1 << i) & (MASK)) {		\
-	    fprintf(FILE, "%s", reg_names[i]);	\
-	    (MASK) &= ~(1 << i);		\
-	    break;				\
-	}					\
-}
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-/* The next macro needs much optimization !!
-   M.Yuhara */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)     \
-{ register int regno;						\
-  register int mask = 0;					\
-  register int nregs = 0;					\
-  static char *reg_names[] = REGISTER_NAMES;			\
-  extern char call_used_regs[];					\
-  int fsize = ((SIZE) + 3) & -4;				\
-  for (regno = 0; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && !call_used_regs[regno]) {	\
-	mask |= (1 << regno);					\
-	nregs++;						\
-    }								\
-  if (frame_pointer_needed) {					\
-    mask &= ~(1 << FRAME_POINTER_REGNUM);			\
-    if (nregs > 4) {						\
-	fprintf(FILE, "\tenter.w #%d,", fsize);			\
-	MY_PRINT_MASK(FILE, mask, MY_GREG_OFF);			\
-	fprintf(FILE,"\n");					\
-    } else {							\
-	fprintf(FILE, "\tmov.w fp,@-sp\n");			\
-	fprintf(FILE, "\tmov.w sp,fp\n");			\
-	if (fsize > 0)						\
-	    myoutput_sp_adjust(FILE, "sub", fsize);		\
-	while (nregs--) {					\
-	    fprintf(FILE, "\tmov.w ");				\
-	    MY_PRINT_ONEREG_H(FILE, mask);			\
-	    fprintf(FILE, ",@-sp\n");				\
-	}							\
-    }								\
-  } else {							\
-    if (fsize > 0)						\
-	myoutput_sp_adjust(FILE, "sub", fsize);			\
-    if (mask != 0) {						\
-	if (nregs > 4) {					\
-	    fprintf(FILE, "\tstm.w ");				\
-	    MY_PRINT_MASK(FILE, mask, MY_GREG_OFF);		\
-	    fprintf(FILE, ",@-sp\n");				\
-	} else {						\
-	    while (nregs--) {					\
-		fprintf(FILE, "\tmov.w ");			\
-		MY_PRINT_ONEREG_H(FILE, mask);			\
-		fprintf(FILE, ",@-sp\n");			\
-	    }							\
-	}							\
-    }								\
-  }								\
-  mask = 0;							\
-  for (regno = 16; regno < 32; regno++)				\
-        if (regs_ever_live[regno] && !call_used_regs[regno])	\
-            mask |= 1 << (regno - 16);				\
-  if (mask != 0) {						\
-	fprintf(FILE, "\tfstm.w ");				\
-	MY_PRINT_MASK(FILE, mask, MY_FREG_OFF);			\
-	fprintf(FILE, ",@-sp\n", mask);				\
-  }								\
-}
-
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-/* ??? M.Yuhara */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\tmova @LP%d,r0\n\tjsr mcount\n", (LABELNO))
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.  */
-
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\tcmp #0,@LPBX0\n\tbne LPI%d\n\tpusha @LPBX0\n\tjsr ___bb_init_func\n\tadd #4,sp\nLPI%d:\n",  \
-	   LABELNO, LABELNO);
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  */
-
-#define BLOCK_PROFILER(FILE, BLOCKNO)	\
-  fprintf (FILE, "\tadd #1,@(LPBX2+%d)\n", 4 * BLOCKNO)
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer (when
-   frame_pinter_needed)  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-/* The Gmicro FPU seems to be unable to fldm/fstm double or single
-   floating. It only allows extended !! */
-/* Optimization is not enough, especially FREGs load !! M.Yuhara */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-{ register int regno;						\
-  register int mask, fmask;					\
-  register int nregs, nfregs;					\
-  int offset, foffset;						\
-  extern char call_used_regs[];					\
-  static char *reg_names[] = REGISTER_NAMES;			\
-  int fsize = ((SIZE) + 3) & -4;				\
-  FUNCTION_EXTRA_EPILOGUE (FILE, SIZE);				\
-  nfregs = 0;  fmask = 0; 					\
-  for (regno = 16; regno < 31; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      { nfregs++; fmask |= 1 << (regno - 16); }			\
-  foffset = nfregs * 12;					\
-  nregs = 0;  mask = 0;						\
-  if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \
-  for (regno = 0; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      { nregs++; mask |= 1 << regno; }				\
-  if (frame_pointer_needed) {					\
-    offset = nregs * 4 + fsize;					\
-    if (nfregs > 0) {						\
-	fprintf(FILE, "\tfldm.x @(%d,fp),", -(foffset + offset));\
-	MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF);		\
-	fprintf(FILE, "\n");					\
-    }								\
-    if (nregs > 4						\
-	|| current_function_pops_args) {			\
-	fprintf(FILE, "\tmova @(%d,fp),sp\n", -offset);		\
-	fprintf(FILE, "\texitd ");				\
-	MY_PRINT_MASK(FILE, mask, MY_GREG_OFF);			\
-	fprintf(FILE, ",#%d\n", current_function_pops_args);	\
-    } else {							\
-	while (nregs--) {					\
-	    fprintf(FILE, "\tmov:l.w @(%d,fp),", -offset);	\
-	    MY_PRINT_ONEREG_L(FILE, mask);			\
-	    fprintf(FILE, "\n");				\
-	    offset -= 4;					\
-	}							\
-	if (TARGET_NEWRETURN) {					\
-	    fprintf(FILE, "\tmova.w @(4,fp),sp\n");		\
-	    fprintf(FILE, "\tmov:l.w @fp,fp\n");		\
-	} else {						\
-	    fprintf(FILE, "\tmov.w fp,sp\n");			\
-	    fprintf(FILE, "\tmov.w @sp+,fp\n");			\
-	}							\
-	fprintf(FILE, "\trts\n");				\
-    }								\
-  } else {							\
-    if (nfregs > 0) {						\
-	fprintf(FILE, "\tfldm.w @sp+,");			\
-	MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF);		\
-	fprintf(FILE, "\n");					\
-    }								\
-    if (nregs > 4) {						\
-	fprintf(FILE, "\tldm.w @sp+,");				\
-	MY_PRINT_MASK(FILE, mask, MY_GREG_OFF);			\
-	fprintf(FILE, "\n");					\
-    } else {							\
-	while (nregs--) {					\
-	    fprintf(FILE, "\tmov.w @sp+,");			\
-	    MY_PRINT_ONEREG_L(FILE,mask);			\
-	    fprintf(FILE, "\n");				\
-	}							\
-    }								\
-      if (current_function_pops_args) {				\
-	myoutput_sp_adjust(FILE, "add", 			\
-	    (fsize + 4 + current_function_pops_args));		\
-	fprintf(FILE, "\tjmp @(%d,sp)\n", current_function_pops_args);\
-    } else {							\
-	if (fsize > 0)						\
-	    myoutput_sp_adjust(FILE, "add", fsize);		\
-	fprintf(FILE, "\trts\n");				\
-    }								\
-  }								\
-}
-
-/* This is a hook for other tm files to change.  */
-#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)
-
-/* If the memory address ADDR is relative to the frame pointer,
-   correct it to be relative to the stack pointer instead.
-   This is for when we don't use a frame pointer.
-   ADDR should be a variable name.  */
-
-/* You have to change the next macro if you want to use more complex
-   addressing modes (such as double indirection and  more than one
-   chain-addressing stages). */
-
-#define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH)  \
-{ int offset = -1;							\
-  rtx regs = stack_pointer_rtx;						\
-  if (ADDR == frame_pointer_rtx)					\
-    offset = 0;								\
-  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
-	   && GET_CODE (XEXP (ADDR, 1)) == CONST_INT)			\
-    offset = INTVAL (XEXP (ADDR, 1));					\
-  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
-    { rtx other_reg = XEXP (ADDR, 1);					\
-      offset = 0;							\
-      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }	\
-  else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
-    { rtx other_reg = XEXP (ADDR, 0);					\
-      offset = 0;							\
-      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }	\
-  else if (GET_CODE (ADDR) == PLUS					\
-	   && GET_CODE (XEXP (ADDR, 0)) == PLUS				\
-	   && XEXP (XEXP (ADDR, 0), 0) == frame_pointer_rtx		\
-	   && GET_CODE (XEXP (ADDR, 1)) == CONST_INT)			\
-    { rtx other_reg = XEXP (XEXP (ADDR, 0), 1);				\
-      offset = INTVAL (XEXP (ADDR, 1));					\
-      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }	\
-  else if (GET_CODE (ADDR) == PLUS					\
-	   && GET_CODE (XEXP (ADDR, 0)) == PLUS				\
-	   && XEXP (XEXP (ADDR, 0), 1) == frame_pointer_rtx		\
-	   && GET_CODE (XEXP (ADDR, 1)) == CONST_INT)			\
-    { rtx other_reg = XEXP (XEXP (ADDR, 0), 0);				\
-      offset = INTVAL (XEXP (ADDR, 1));					\
-      regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); }	\
-  if (offset >= 0)							\
-    { int regno;							\
-      extern char call_used_regs[];					\
-      for (regno = 16; regno < 32; regno++)				\
-        if (regs_ever_live[regno] && ! call_used_regs[regno])		\
-          offset += 12;							\
-      for (regno = 0; regno < 16; regno++)				\
-	if (regs_ever_live[regno] && ! call_used_regs[regno])		\
-	  offset += 4;							\
-      offset -= 4;							\
-      ADDR = plus_constant (regs, offset + (DEPTH)); } }
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-/* Gmicro */
-#define REGNO_OK_FOR_GREG_P(REGNO) \
-((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
-#define REGNO_OK_FOR_FPU_P(REGNO) \
-(((REGNO) ^ 0x10) < 16 || (unsigned) (reg_renumber[REGNO] ^ 0x10) < 16)
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO)
-#define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO)
-
-/* Now macros that check whether X is a register and also,
-   strictly, whether it is in a specified class.
-
-   These macros are specific to the Gmicro, and may be used only
-   in code for printing assembler insns and in conditions for
-   define_optimization.  */
-
-/* 1 if X is an fpu register.  */
-
-#define FPU_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPU_P (REGNO (X)))
-
-/* I used GREG_P in the gmicro.md file. */
-
-#ifdef REG_OK_STRICT
-#define GREG_P(X) (REG_P (X) && REGNO_OK_FOR_GREG_P (REGNO(X)))
-#else
-#define GREG_P(X) (REG_P (X) && ((REGNO (X) & ~0xf) != 0x10))
-#endif
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-/* The Gmicro allows more registers in the chained addressing mode.
-   But I do not know gcc supports such an architecture. */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) ((REGNO (X) & ~0xf) != 0x10)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~0xf) != 0x10)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* The gcc uses the following effective address of the Gmicro.
-					       (without using PC!!).
-   {@} ( {Rbase} + {Disp} + {Rindex * [1,2,4,8]} )
-	where
-		@:     memory indirection.
-		Rbase: Base Register = General Register.
-		Disp:  Displacement (up to 32bits)
-		Rindex: Index Register = General Register.
-		[1,2,4,8]: Scale of Index. 1 or 2 or 4 or 8.
-		The inside of { } can be omitted.
-    This restricts the chained addressing up to 1 stage.  */
-
-
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
-   except for CONSTANT_ADDRESS_P which is actually machine-independent.  */
-
-#define REG_CODE_BASE_P(X) \
-  (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
-
-#define REG_CODE_INDEX_P(X) \
-  (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
-
-/* GET_CODE(X) must be PLUS. This macro does not check for PLUS! */
-#define BASE_PLUS_DISP_P(X) \
-   ( REG_CODE_BASE_P (XEXP (X, 0)) 		\
-     && CONSTANT_ADDRESS_P (XEXP (X, 1))	\
-    ||						\
-     REG_CODE_BASE_P (XEXP (X, 1)) 		\
-     && CONSTANT_ADDRESS_P (XEXP (X, 0)) )
-
-/* 1 if X is {0,Rbase} + {0,disp}.  */
-#define BASED_ADDRESS_P(X)  \
-  (CONSTANT_ADDRESS_P (X)	\
-   || REG_CODE_BASE_P (X)	\
-   || (GET_CODE (X) == PLUS)	\
-       && BASE_PLUS_DISP_P (X))
-
-/* 1 if X is 1 or 2 or 4 or 8. GET_CODE(X) must be CONST_INT. */
-#define SCALE_OF_INDEX_P(X) \
-  ( INTVAL(X) == 4	\
-    || INTVAL(X) == 2	\
-    || INTVAL(X) == 8	\
-    || INTVAL(X) == 1 )
-
-/* #define INDEX_TERM_P(X,MODE)  */
-#define INDEX_TERM_P(X)  \
-  ( REG_CODE_INDEX_P(X)					\
-    || (GET_CODE (X) == MULT				\
-	&& ( (xfoo0 = XEXP (X, 0)), (xfoo1 = XEXP(X, 1)), \
-	     ( ( (GET_CODE (xfoo0) == CONST_INT)	\
-	       && SCALE_OF_INDEX_P (xfoo0)		\
-	       && REG_CODE_INDEX_P (xfoo1) )		\
-	      ||					\
-	       ( (GET_CODE (xfoo1) == CONST_INT)		\
-	       && SCALE_OF_INDEX_P (xfoo1)		\
-	       && REG_CODE_INDEX_P (xfoo0) ) ))))
-
-/* Assumes there are no cases such that X = (Ireg + Disp) + Disp */
-#define BASE_DISP_INDEX_P(X)  \
-  ( BASED_ADDRESS_P (X)							\
-   || ( (GET_CODE (X) == PLUS)						\
-      && ( ( (xboo0 = XEXP (X, 0)), (xboo1 = XEXP (X, 1)),		\
-	  (REG_CODE_BASE_P (xboo0)					\
-	    && (GET_CODE (xboo1) == PLUS)				\
-	    && ( ( CONSTANT_ADDRESS_P (XEXP (xboo1, 0))			\
-		   && INDEX_TERM_P (XEXP (xboo1, 1)) )			\
-	         || ( CONSTANT_ADDRESS_P (XEXP (xboo1, 1))		\
-		     && INDEX_TERM_P (XEXP (xboo1, 0))) )))		\
-	 ||								\
-	  (CONSTANT_ADDRESS_P (xboo0)					\
-	    && (GET_CODE (xboo1) == PLUS)				\
-	    && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0))			\
-	 	   && INDEX_TERM_P (XEXP (xboo1, 1)) )			\
-	         || ( REG_CODE_BASE_P (XEXP (xboo1, 1))			\
-		      && INDEX_TERM_P (XEXP (xboo1, 0))) ))		\
-	||								\
-	  (INDEX_TERM_P (xboo0)						\
-	    && ( ( (GET_CODE (xboo1) == PLUS)				\
-	          && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0))		\
-		      && CONSTANT_ADDRESS_P (XEXP (xboo1, 1)) )		\
-	               || ( REG_CODE_BASE_P (XEXP (xboo1, 1))   	\
-		      && CONSTANT_ADDRESS_P (XEXP (xboo1, 0))) ))	\
-		||							\
-		 (CONSTANT_ADDRESS_P (xboo1))				\
-		||							\
-		 (REG_CODE_BASE_P (xboo1)) )))))
-
-/*
-	If you want to allow double-indirection,
-	you have to change the <fp-relative> => <sp-relative> conversion
-	routine. M.Yuhara
-
-#ifdef REG_OK_STRICT
-#define DOUBLE_INDIRECTION(X,ADDR) {\
-    if (BASE_DISP_INDEX_P (XEXP (XEXP (X, 0), 0) )) goto ADDR; \
-    }
-#else
-#define DOUBLE_INDIRECTION(X,ADDR) { }
-#endif
-*/
-
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) {\
-  register rtx xboo0, xboo1, xfoo0, xfoo1;		\
-  if (GET_CODE (X) == MEM) { 				\
-    /*							\
-    if (GET_CODE (XEXP (X,0)) == MEM) {			\
-	DOUBLE_INDIRECTION(X,ADDR);			\
-    } else {						\
-	if (BASE_DISP_INDEX_P (XEXP (X, 0))) goto ADDR;	\
-    }							\
-    */							\
-  } else {						\
-	if (BASE_DISP_INDEX_P (X)) goto ADDR;		\
-	if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC)	\
-	    && REG_P (XEXP (X, 0))					\
-	    && (REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM))		\
-		goto ADDR;						\
-  }							\
-}
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the Gmicro, nothing is done now. */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the VAX, the predecrement and postincrement address depend thus
-   (the amount of decrement or increment being the length of the operand)
-   and all indexed address depend thus (because the index scale factor
-   is the length of the operand).
-   The Gmicro mimics the VAX now. Since ADDE is legitimate, it cannot
-   include auto-inc/dec. */
-
-/* Unnecessary ??? */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
- { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC)	\
-     goto LABEL; }
-
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-/* #define CASE_VECTOR_MODE HImode */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE 1
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 4
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-/* #define STORE_FLAG_VALUE -1 */
-
-/* When a prototype says `char' or `short', really pass an `int'.  */
-#define PROMOTE_PROTOTYPES
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    if ((unsigned) INTVAL (RTX) < 8) return 0;			\
-    if ((unsigned) (INTVAL (RTX) + 0x80) < 0x100) return 1;	\
-    if ((unsigned) (INTVAL (RTX) + 0x8000) < 0x10000) return 2;	\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 3;							\
-  case CONST_DOUBLE:						\
-    return 5;
-
-/* Define subroutines to call to handle multiply and divide.
-   The `*' prevents an underscore from being prepended by the compiler.  */
-/* Use libgcc on Gmicro */
-/* #define UDIVSI3_LIBCALL "*udiv" */
-/* #define UMODSI3_LIBCALL "*urem" */
-
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  */
-
-/* Set if the cc value is actually in the FPU, so a floating point
-   conditional branch must be output.  */
-#define CC_IN_FPU 04000
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-/* Since Gmicro's compare instructions depend on the branch condition,
-   all branch should be kept.
-   More work must be done to optimize condition code !! M.Yuhara */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) {CC_STATUS_INIT;}
-
-/* The skeleton of the next macro is taken from "vax.h".
-   FPU-reg manipulation is added.  M.Yuhara */
-/* Now comment out.
-#define NOTICE_UPDATE_CC(EXP, INSN) {	\
-  if (GET_CODE (EXP) == SET) {					\
-      if ( !FPU_REG_P (XEXP (EXP, 0))				\
-	  && (XEXP (EXP, 0) != cc0_rtx)				\
-	  && (FPU_REG_P (XEXP (EXP, 1))				\
-	      || GET_CODE (XEXP (EXP, 1)) == FIX		\
-	      || GET_CODE (XEXP (EXP, 1)) == FLOAT_TRUNCATE	\
-	      || GET_CODE (XEXP (EXP, 1)) == FLOAT_EXTEND)) {	\
-	 CC_STATUS_INIT;					\
-      } else if (GET_CODE (SET_SRC (EXP)) == CALL) {		\
-	 CC_STATUS_INIT;					\
-      } else if (GET_CODE (SET_DEST (EXP)) != PC) {		\
-	  cc_status.flags = 0;					\
-	  cc_status.value1 = SET_DEST (EXP);			\
-	  cc_status.value2 = SET_SRC (EXP);			\
-      }								\
-  } else if (GET_CODE (EXP) == PARALLEL				\
-	   && GET_CODE (XVECEXP (EXP, 0, 0)) == SET		\
-	   && GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) != PC) {\
-      cc_status.flags = 0;					\
-      cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0));	\
-      cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0)); 	\
-  /* PARALLELs whose first element sets the PC are aob, sob VAX insns.	\
-     They do change the cc's.  So drop through and forget the cc's. * / \
-  } else CC_STATUS_INIT;						\
-  if (cc_status.value1 && GET_CODE (cc_status.value1) == REG	\
-      && cc_status.value2					\
-      && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))	\
-    cc_status.value2 = 0;					\
-  if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM	\
-      && cc_status.value2					\
-      && GET_CODE (cc_status.value2) == MEM)			\
-    cc_status.value2 = 0;					\
-  if ( (cc_status.value1 && FPU_REG_P (cc_status.value1))	\
-      || (cc_status.value2 && FPU_REG_P (cc_status.value2)))	\
-    cc_status.flags = CC_IN_FPU;				\
-}
-*/
-
-#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV)  \
-{ if (cc_prev_status.flags & CC_IN_FPU)		\
-    return FLOAT;				\
-  if (cc_prev_status.flags & CC_NO_OVERFLOW)	\
-    return NO_OV;				\
-  return NORMAL; }
-
-/* Control the assembler format that we output.  */
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".section text,code,align=4"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".section data,data,align=4"
-
-/* Output before uninitialized data. */
-
-#define BSS_SECTION_ASM_OP ".section bss,data,align=4"
-
-/* Output at beginning of assembler file.
-   It is not appropriate for this to print a list of the options used,
-   since that's not the convention that we use.  */
-
-#define ASM_FILE_START(FILE)
-
-/* Output at the end of assembler file. */
-
-#define ASM_FILE_END(FILE)  fprintf (FILE, "\t.end\n");
-
-
-/* Don't try to define `gcc_compiled.' since the assembler do not
-   accept symbols with periods and GDB doesn't run on this machine anyway.  */
-#define ASM_IDENTIFY_GCC(FILE)
-
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-/* #define ASM_APP_ON "#APP\n" */
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-/* #define ASM_APP_OFF ";#NO_APP\n" */
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",	\
- "r8", "r9", "r10", "r11", "r12", "r13", "fp", "sp",	\
- "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
- "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15"}
-
-/* How to renumber registers for dbx and gdb. */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Define this if gcc should produce debugging output for dbx in response
-   to the -g flag. This does not work for the Gmicro now */
-
-#define DBX_DEBUGGING_INFO
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME) {	\
-    assemble_name (FILE, NAME);	\
-    fputs (":\n", FILE);	\
-}
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME) {\
-    fputs ("\t.global ", FILE);	\
-    assemble_name (FILE, NAME);	\
-    fputs ("\n", FILE);		\
-}
-
-/* This is how to output a command to make the external label named NAME
-   which are not defined in the file to be referable */
-/* ".import" does not work ??? */
-
-#define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) { \
-    fputs ("\t.global ", FILE);	\
-    assemble_name (FILE, NAME);	\
-    fputs ("\n", FILE);		\
-}
-
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-/* do {...} while(0) is necessary, because these macros are used as
-    if (xxx) MACRO; else ....
-		  ^
-*/
-
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-do { union { double d; long l[2];} tem;					\
-     tem.d = (VALUE);							\
-     fprintf (FILE, "\t.fdata.d h'%x%08x.d\n", tem.l[0], tem.l[1]);	\
-} while(0)
-
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-do { union { float f; long l;} tem;			\
-     tem.f = (VALUE);					\
-     fprintf (FILE, "\t.fdata.s h'%x.s\n", tem.l);	\
-} while(0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.data.w "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.data.h "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.data.b "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.data.b h'%x\n", (VALUE))
-
-#define ASM_OUTPUT_ASCII(FILE,P,SIZE)  \
-  output_ascii ((FILE), (P), (SIZE))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tmov %s,@-sp\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tmov @sp+,%s\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute.
-   (The Gmicro does not use such vectors,
-   but we must define this macro anyway.)  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.data.w L%d\n", VALUE)
-
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.data.w L%d-L%d\n", VALUE, REL)
-
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
-  fprintf (FILE, "\t.align %d\n", (1 << (LOG)));
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.res.b %d\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( bss_section (),				\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)),\
-  fprintf ((FILE), "\t.export "),		\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), "\n") )
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( bss_section (),				\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-/* $__ is unique ????? M.Yuhara */
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12),	\
-  sprintf ((OUTPUT), "$__%s%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Output a float value (represented as a C double) as an immediate operand.
-   This macro is a Gmicro/68k-specific macro.  */
-
-#define ASM_OUTPUT_FLOAT_OPERAND(FILE,VALUE)	\
-do { union { float f; long l;} tem;		\
-  tem.f = (VALUE);				\
-  fprintf (FILE, "#h'%x.s", tem.l);		\
-} while(0)
-
-
-/* Output a double value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)	\
-do { union { double d; long l[2];} tem;		\
-  tem.d = (VALUE);				\
-  fprintf (FILE, "#h'%x%08x.d", tem.l[0], tem.l[1]);	\
-} while(0)
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.
-
-   On the Gmicro, we use several CODE characters:
-   'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
-   'b' for branch target label.
-   '-' for an operand pushing on the stack.
-   '+' for an operand pushing on the stack.
-   '#' for an immediate operand prefix 
-*/
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)	\
-  ( (CODE) == '#' || (CODE) == '-'		\
-     || (CODE) == '+' || (CODE) == '@' || (CODE) == '!')
-
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ int i;								\
-  static char *reg_name[] = REGISTER_NAMES;				\
-/* fprintf (stderr, "PRINT_OPERAND CODE=%c(0x%x), ", CODE, CODE);\
-myprcode(GET_CODE(X)); */	\
-  if (CODE == '#') fprintf (FILE, "#");					\
-  else if (CODE == '-') fprintf (FILE, "@-sp");				\
-  else if (CODE == '+') fprintf (FILE, "@sp+");				\
-  else if (CODE == 's') fprintf (stderr, "err: PRINT_OPERAND <s>\n"); 	\
-  else if (CODE == '!') fprintf (stderr, "err: PRINT_OPERAND <!>\n"); 	\
-  else if (CODE == '.') fprintf (stderr, "err: PRINT_OPERAND <.>\n"); 	\
-  else if (CODE == 'b') {						\
-    if (GET_CODE (X) == MEM)						\
-	output_addr_const (FILE, XEXP (X, 0));  /* for bsr */		\
-    else								\
-	output_addr_const (FILE, X);  /* for bcc */			\
-  }									\
-  else if (CODE == 'p')							\
-    print_operand_address (FILE, X);					\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_name[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode)	\
-    { union { double d; int i[2]; } u;					\
-      union { float f; int i; } u1;					\
-      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
-      u1.f = u.d;							\
-      if (CODE == 'f')							\
-	ASM_OUTPUT_FLOAT_OPERAND (FILE, u1.f);				\
-      else								\
-	fprintf (FILE, "#h'%x", u1.i); }				\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode)	\
-    { union { double d; int i[2]; } u;					\
-      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
-      ASM_OUTPUT_DOUBLE_OPERAND (FILE, u.d); }				\
-  else { putc ('#', FILE);						\
-output_addr_const (FILE, X); }}
-
-/* Note that this contains a kludge that knows that the only reason
-   we have an address (plus (label_ref...) (reg...))
-   is in the insn before a tablejump, and we know that m68k.md
-   generates a label LInnn: on such an insn.  */
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
-    { print_operand_address (FILE, ADDR); }
-
-/*
-Local variables:
-version-control: t
-End:
-*/
diff --git a/gcc/config/gmicro/gmicro.md b/gcc/config/gmicro/gmicro.md
deleted file mode 100755
index 35384ce..0000000
--- a/gcc/config/gmicro/gmicro.md
+++ /dev/null
@@ -1,2738 +0,0 @@
-;;- Machine description for GNU compiler, Fujitsu Gmicro Version
-;;  Copyright (C) 1990, 1994, 1996 Free Software Foundation, Inc.
-;;  Contributed by M.Yuhara, Fujitsu Laboratories LTD.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-;; Among other things, the copyright
-;; notice and this notice must be preserved on all copies.
-
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- instruction definitions
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;;- When naming insn's (operand 0 of define_insn) be careful about using
-;;- names from other targets machine descriptions.
-
-;;- cpp macro #define NOTICE_UPDATE_CC is essentially a no-op for the 
-;;- gmicro; no compares are eliminated.
-
-;;- The original structure of this file is m68k.md.
-
-;; ??? Work to be done:
-;; Add patterns for ACB and SCB instructions.
-;; Add define_insn patterns to recognize the insns that extend a byte
-;; to a word and add it into a word, etc.
-
-;;- Some of these insn's are composites of several Gmicro op codes.
-;;- The assembler (or final @@??) insures that the appropriate one is
-;;- selected.
-
-(define_insn ""
-  [(set (match_operand:DF 0 "push_operand" "=m")
-	(match_operand:DF 1 "general_operand" "rmfF"))]
-  ""
-  "*
-{
-  if (FPU_REG_P (operands[1]))
-    return \"fmov.d %f1,%0\";
-  return output_move_double (operands);
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "push_operand" "=m")
-	(match_operand:DF 1 "general_operand" "rmF"))]
-  ""
-  "*
-{
-  return output_move_double (operands);
-}")
-
-;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
-;; be folded while optimizing anyway.
-
-(define_insn "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "nonimmediate_operand" "rm"))]
-  ""
-  "cmp:z.w #0,%0")
-
-(define_insn "tsthi"
-  [(set (cc0)
-	(match_operand:HI 0 "nonimmediate_operand" "rm"))]
-  ""
-  "cmp:z.h #0,%0")
-
-(define_insn "tstqi"
-  [(set (cc0)
-	(match_operand:QI 0 "nonimmediate_operand" "rm"))]
-  ""
-  "cmp:z.b #0,%0")
-  
-
-(define_insn "tstsf"
-  [(set (cc0)
-	(match_operand:SF 0 "general_operand" "fmF"))]
-  "TARGET_FPU"
-  "*
-{
-  cc_status.flags = CC_IN_FPU;
-  return \"ftst.s %0\";
-}")
-
-
-(define_insn "tstdf"
-  [(set (cc0)
-	(match_operand:DF 0 "general_operand" "fmF"))]
-  "TARGET_FPU"
-  "*
-{
-  cc_status.flags = CC_IN_FPU;
-  return \"ftst.d %0\";
-}")
-
-;; compare instructions.
-
-;; (operand0 - operand1)
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "ri,rm")
-		 (match_operand:SI 1 "general_operand" "rm,rmi")))]
-  ""
-  "*
-{
-  int signed_flag = my_signed_comp (insn);
-
-  if (which_alternative == 0)
-    {
-      cc_status.flags |= CC_REVERSED;
-      if (signed_flag && GET_CODE (operands[0]) == CONST_INT)
-	{
-	  register rtx xfoo;
-	  xfoo = operands[1];
-	  operands[0] = operands[1];
-	  operands[1] = xfoo;
-	  return cmp_imm_word (INTVAL (operands[1]), operands[0]);
-	}
-      if (signed_flag)
-	return \"cmp.w %0,%1\"; 
-      return \"cmpu.w %0,%1\"; 
-    }
-  if (signed_flag)
-    {
-      if (GET_CODE (operands[1]) == CONST_INT)
-	return cmp_imm_word (INTVAL (operands[1]), operands[0]);
-      return \"cmp.w %1,%0\"; 
-    }
-  else
-    return \"cmpu.w %1,%0\"; 
-}")
-
-(define_insn "cmphi"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "nonimmediate_operand" "ri,rm")
-		 (match_operand:HI 1 "general_operand" "rm,rmi")))]
-  ""
-  "*
-{
-  int signed_flag = my_signed_comp (insn);
-
-  if (which_alternative == 0)
-    {
-      cc_status.flags |= CC_REVERSED;
-      if (signed_flag)
-	return \"cmp.h %0,%1\"; 
-      return \"cmpu.h %0,%1\"; 
-    }
-  if (signed_flag)
-    return \"cmp.h %1,%0\"; 
-  return \"cmpu.h %1,%0\"; 
-}")
-
-(define_insn "cmpqi"
-  [(set (cc0)
-	(compare (match_operand:QI 0 "nonimmediate_operand" "ri,rm")
-		 (match_operand:QI 1 "general_operand" "rm,rmi")))]
-  ""
-  "*
-{
-  int signed_flag = my_signed_comp (insn);
-
-  if (which_alternative == 0)
-    {
-      cc_status.flags |= CC_REVERSED;
-      if (signed_flag)
-	return \"cmp.b %0,%1\"; 
-      return \"cmpu.b %0,%1\"; 
-    }
-  if (signed_flag)
-    return \"cmp.b %1,%0\"; 
-  return \"cmpu.b %1,%0\"; 
-}")
-
-
-(define_insn "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "general_operand" "f,mG")
-		 (match_operand:DF 1 "general_operand" "fmG,f")))]
-  "TARGET_FPU"
-  "*
-{
-  cc_status.flags = CC_IN_FPU;
-
-  if (FPU_REG_P (operands[0]))
-    return \"fcmp.d %f1,%f0\";
-  cc_status.flags |= CC_REVERSED;
-  return \"fcmp.d %f0,%f1\";
-}")
-
-
-(define_insn "cmpsf"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "general_operand" "f,mG")
-		 (match_operand:SF 1 "general_operand" "fmG,f")))]
-  "TARGET_FPU"
-  "*
-{
-  cc_status.flags = CC_IN_FPU;
-  if (FPU_REG_P (operands[0]))
-    return \"fcmp.s %f1,%0\";
-  cc_status.flags |= CC_REVERSED;
-  return \"fcmp.s %f0,%1\";
-}")
-
-;; Recognizers for btst instructions.
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
-			    (const_int 1)
-			    (match_operand:SI 1 "general_operand" "rmi")))]
-  ""
-  "btst %1.w,%0.b")
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "rm")
-			    (const_int 1)
-			    (match_operand:SI 1 "general_operand" "rmi")))]
-  ""
-  "btst %1.w,%0.w")
-
-;; The following two patterns are like the previous two
-;; except that they use the fact that bit-number operands (offset)
-;; are automatically masked to 3 or 5 bits when the base is a register.
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
-			    (const_int 1)
-			    (and:SI
-			       (match_operand:SI 1 "general_operand" "rmi")
-			       (const_int 7))))]
-  ""
-  "btst %1.w,%0.b")
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r")
-			    (const_int 1)
-			    (and:SI
-			       (match_operand:SI 1 "general_operand" "rmi")
-			       (const_int 31))))]
-  ""
-  "btst %1.w,%0.w")
-
-; More various size-patterns are allowed for btst, but not
-; included yet.  M.Yuhara
-
-
-(define_insn ""
-  [(set (cc0) (and:SI (sign_extend:SI
-		       (sign_extend:HI
-			(match_operand:QI 0 "nonimmediate_operand" "rm")))
-		      (match_operand:SI 1 "general_operand" "i")))]
-  "(GET_CODE (operands[1]) == CONST_INT
-    && (unsigned) INTVAL (operands[1]) < 0x100
-    && exact_log2 (INTVAL (operands[1])) >= 0)"
-  "*
-{
-  register int log = exact_log2 (INTVAL (operands[1]));
-  operands[1] = GEN_INT (log);
-  return \"btst %1,%0.b\";
-}")
-
-; I can add more patterns like above. But not yet.  M.Yuhara
-
-
-; mtst is supported only by G/300.
-
-(define_insn ""
-  [(set (cc0) 
-	(and:SI (match_operand:SI 0 "general_operand" "%rmi")
-		(match_operand:SI 1 "general_operand" "rm")))]
-  "TARGET_G300"
-  "*
-{
-  if (GET_CODE (operands[0]) == CONST_INT)
-    return \"mtst.w %0,%1\";
-  return \"mtst.w %1,%0\";
-}")
-
-(define_insn ""
-  [(set (cc0) 
-	(and:HI (match_operand:HI 0 "general_operand" "%rmi")
-		(match_operand:HI 1 "general_operand" "rm")))]
-  "TARGET_G300"
-  "*
-{
-  if (GET_CODE (operands[0]) == CONST_INT)
-    return \"mtst.h %0,%1\";
-  return \"mtst.h %1,%0\";
-}")
-
-(define_insn ""
-  [(set (cc0) 
-	(and:QI (match_operand:QI 0 "general_operand" "%rmi")
-		(match_operand:QI 1 "general_operand" "rm")))]
-  "TARGET_G300"
-  "*
-{
-  if (GET_CODE (operands[0]) == CONST_INT)
-    return \"mtst.b %0,%1\";
-  return \"mtst.b %1,%0\";
-}")
-
-
-
-;; move instructions
-
-/* added by M.Yuhara */
-;; 1.35.04 89.08.28 modification start
-;; register_operand -> general_operand
-;; ashift -> mult 
-
-(define_insn ""
-  [(set (mem:SI (plus:SI
-		  (match_operand:SI 0 "general_operand" "r")
-		  (ashift:SI
-		      (match_operand:SI 1 "general_operand" "r")
-		      (const_int 2))))
-	(match_operand:SI 2 "general_operand" "rmi"))]
-  ""
-  "*
-{
-  return \"mov.w %2,@(%0:b,%1*4)\";
-}")
-
-(define_insn ""
-  [(set (mem:SI (plus:SI
-		  (ashift:SI
-		      (match_operand:SI 0 "general_operand" "r")
-		      (const_int 2))
-		  (match_operand:SI 1 "general_operand" "r")))
-	(match_operand:SI 2 "general_operand" "rmi"))]
-  ""
-  "*
-{
-  return \"mov.w %2,@(%1:b,%0*4)\";
-}")
-
-
-(define_insn ""
-  [(set (mem:SI (plus:SI
-		  (match_operand:SI 0 "register_operand" "r")
-		  (mult:SI
-		      (match_operand:SI 1 "register_operand" "r")
-		      (const_int 4))))
-	(match_operand:SI 2 "general_operand" "rmi"))]
-  ""
-  "*
-{
-  return \"mov.w %2,@(%0:b,%1*4)\";
-}")
-
-(define_insn ""
-  [(set (mem:SI (plus:SI
-		  (mult:SI
-		      (match_operand:SI 0 "register_operand" "r")
-		      (const_int 4))
-		  (match_operand:SI 1 "register_operand" "r")))
-	(match_operand:SI 2 "general_operand" "rmi"))]
-  ""
-  "*
-{
-  return \"mov.w %2,@(%1:b,%0*4)\";
-}")
-
-
-(define_insn ""
-  [(set (mem:SI (plus:SI
-		  (match_operand:SI 0 "general_operand" "r")
-		  (plus:SI
-		      (match_operand:SI 1 "register_operand" "r")
-		      (match_operand:SI 2 "register_operand" "i"))))
-	(match_operand:SI 3 "general_operand" "rmi"))]
-  ""
-  "*
-{
-  return \"mov.w %3,@(%c2,%0,%1)\";
-}")
-
-(define_insn ""
-  [(set (mem:SI (plus:SI
-		  (plus:SI
-		      (match_operand:SI 0 "register_operand" "r")
-		      (match_operand:SI 1 "register_operand" "r"))
-		  (match_operand:SI 2 "general_operand" "i")))
-	(match_operand:SI 3 "general_operand" "rmi"))]
-  ""
-  "*
-{
-  return \"mov.w %3,@(%c2,%0,%1)\";
-}")
-
-
-(define_insn ""
-  [(set (mem:SI (plus:SI
-		  (match_operand:SI 0 "general_operand" "i")
-		  (plus:SI
-		      (match_operand:SI 1 "register_operand" "r")
-		      (mult:SI
-			  (match_operand:SI 2 "register_operand" "r")
-			  (const_int 4)))))
-	(match_operand:SI 3 "general_operand" "rmi"))]
-  ""
-  "*
-{
-  return \"mov.w %3,@(%1:b,%0,%2*4)\";
-}")
-
-;; 89.08.28 1.35.04 modification end
-
-;; Should add "!" to op2 ??
-
-;; General move-address-to-operand should handle these.
-;; If that does not work, please figure out why.
-
-;(define_insn ""
-;  [(set (match_operand:SI 0 "push_operand" "=m")
-;	(plus:SI
-;	    (match_operand:SI 1 "immediate_operand" "i")
-;	    (match_operand:SI 2 "general_operand" "r")))]
-;  ""
-;  "mova.w @(%c1,%2),%-")
-
-;(define_insn ""
-;  [(set (match_operand:SI 0 "push_operand" "=m")
-;	(plus:SI
-;	    (match_operand:SI 1 "general_operand" "r")
-;	    (match_operand:SI 2 "immediate_operand" "i")))]
-;  ""
-;  "mova.w @(%c2,%1),%-")
-
-
-(define_insn ""
-  [(set (match_operand:SI 0 "push_operand" "=m")
-	(minus:SI
-	    (match_operand:SI 1 "general_operand" "r")
-	    (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "mova.w @(%n2,%1),%-")
-
-
-
-;; General case of fullword move.
-
-(define_insn "movsi"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(match_operand:SI 1 "general_operand" "rmi"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    return mov_imm_word (INTVAL (operands[1]), operands[0]);
-  /* if (address_operand (operands[1], SImode))
-     return \"mova.w %1,%0\"; */
-  if (push_operand (operands[0], SImode))
-    return \"mov.w %1,%-\";
-  return \"mov.w %1,%0\";
-}")
-
-/* pushsi 89.08.10 for test M.Yuhara */
-/*
-(define_insn ""
-  [(set (match_operand:SI 0 "push_operand" "=m")
-	(match_operand:SI 1 "general_operand" "rmi"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    return mov_imm_word (INTVAL (operands[1]), operands[0]);
-  if (push_operand (operands[0], SImode))
-    return \"mov.w %1,%-\";
-  return \"mov.w %1,%0\";
-}")
-*/
-
-
-(define_insn "movhi"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(match_operand:HI 1 "general_operand" "rmi"))]
-  ""
-  "*
-{
-  if (push_operand (operands[0], SImode))
-    return \"mov.h %1,%-\";
-  return \"mov.h %1,%0\";
-}")
-
-;; Is the operand constraint "+" necessary ????
-;; Should I check push_operand ????
-
-(define_insn "movstricthi"
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
-	(match_operand:HI 1 "general_operand" "rmi"))]
-  ""
-  "mov.h %1,%0");
-
-(define_insn "movqi"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(match_operand:QI 1 "general_operand" "rmi"))]
-  ""
-  "*
-{
-  if (GREG_P (operands[0]))
-    {
-      if (CONSTANT_P (operands[1]))
-	return \"mov:l %1,%0.w\";
-      else
-	return \"mov:l %1.b,%0.w\";
-    }
-  if (GREG_P (operands[1]))
-    return \"mov:s %1.w,%0.b\";
-  return \"mov.b %1,%0\";
-}")
-
-(define_insn "movstrictqi"
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
-	(match_operand:QI 1 "general_operand" "rmi"))]
-  ""
-  "mov.b %1,%0")
-
-
-(define_insn "movsf"
-  [(set (match_operand:SF 0 "general_operand" "=f,mf,rm,fr")
-	(match_operand:SF 1 "general_operand" "mfF,f,rmF,fr"))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	return output_move_const_single (operands);
-      return \"fmov.s %1,%0\";
-    case 1:
-      return \"fmov.s %1,%0\";
-    case 2:
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	return output_move_const_single (operands);
-      return \"mov.w %1,%0\";
-    case 3:
-      if (FPU_REG_P (operands[0]))
-	return \"mov.w %1,%-\\n\\tfmov.s %+,%0\";
-      return \"fmov.s %1,%-\\n\\tmov.w %+,%0\";
-    }
-}")
-
-(define_insn "movdf"
-  [(set (match_operand:DF 0 "general_operand" "=f,mf,rm,fr")
-	(match_operand:DF 1 "general_operand" "mfF,f,rmF,fr"))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	return output_move_const_double (operands);
-      return \"fmov.d %1,%0\";
-    case 1:
-      return \"fmov.d %1,%0\";
-    case 2:
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	return output_move_const_double (operands);
-      return output_move_double (operands);
-    case 3:
-      if (FPU_REG_P (operands[0]))
-	{
-	  rtx xoperands[2];
-	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"mov.w %1,%-\", xoperands);
-	  output_asm_insn (\"mov.w %1,%-\", operands);
-	  return \"fmov.d %+,%0\";
-	}
-      else
-	{
-	  output_asm_insn (\"fmov.d %f1,%-\", operands);
-	  output_asm_insn (\"mov.w %+,%0\", operands);
-	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-	  return \"mov.w %+,%0\";
-	}
-    }
-}")
-
-
-;; movdi can apply to fp regs in some cases
-;; Must check again.  you can use fsti/fldi, etc.
-;; FPU reg should be included ??
-;; 89.12.13 for test
-
-(define_insn "movdi"
-  ;; Let's see if it really still needs to handle fp regs, and, if so, why.
-  [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro")
-	(match_operand:DI 1 "general_operand" "rF,m,roiF"))]
-  ""
-  "*
-{
-  if (FPU_REG_P (operands[0]))
-    {
-      if (FPU_REG_P (operands[1]))
-	return \"fmov.d %1,%0\";
-      if (REG_P (operands[1]))
-	{
-	  rtx xoperands[2];
-	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"mov.w %1,%-\", xoperands);
-	  output_asm_insn (\"mov.w %1,%-\", operands);
-	  return \"fmov.d %+,%0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	return output_move_const_double (operands);
-      return \"fmov.d %f1,%0\";
-    }
-  else if (FPU_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	{
-	  output_asm_insn (\"fmov.d %f1,%-\;mov.w %+,%0\", operands);
-	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-	  return \"mov.w %+,%0\";
-	}
-      else
-        return \"fmov.d %f1,%0\";
-    }
-  return output_move_double (operands);
-}
-")
-
-
-;; The definition of this insn does not really explain what it does,
-;; but it should suffice
-;; that anything generated as this insn will be recognized as one
-;; and that it won't successfully combine with anything.
-
-;; This is dangerous when %0 and %1 overlapped !!!!!
-;; Ugly code...
-
-(define_insn "movstrhi"
-  [(set (match_operand:BLK 0 "general_operand" "=m")
-	(match_operand:BLK 1 "general_operand" "m"))
-   (use (match_operand:HI 2 "general_operand" "rmi"))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 1))
-   (clobber (reg:SI 2))]
-  ""
-  "*
-{
-  int op2const;
-  rtx tmpx;
-
-  if (CONSTANT_P (operands[1]))
-    {
-      fprintf (stderr, \"smov 1 const err \");
-      abort ();
-    }
-  else if (GET_CODE (operands[1]) == REG)
-    {
-      fprintf (stderr, \"smov 1 reg err \");
-      abort ();
-    }
-  else if (GET_CODE (operands[1]) == MEM)
-    {
-      tmpx = XEXP (operands[1], 0);
-      if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx))
-	{
-	  operands[1] = tmpx;
-	  output_asm_insn (\"mov.w %1,r0\", operands);
-	}
-      else
-	{
-	  output_asm_insn (\"mova %1,r0\", operands);
-	}
-    }
-  else
-    {
-      fprintf (stderr, \"smov 1 else err \");
-      abort ();
-      output_asm_insn (\"mova.w %p1,r0\", operands);
-    }
-    
-  if (CONSTANT_P (operands[0]))
-    {
-      fprintf (stderr, \"smov 0 const err \");
-      abort ();
-    }
-  else if (GET_CODE (operands[0]) == REG)
-    {
-      fprintf (stderr, \"smov 0 reg err \");
-      abort ();
-    }
-  else if (GET_CODE (operands[0]) == MEM)
-    {
-      tmpx = XEXP (operands[0], 0);
-      if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx))
-	{
-	  operands[0] = tmpx;
-	  output_asm_insn (\"mov.w %0,r1\", operands);
-	}
-      else
-	{
-	  output_asm_insn (\"mova %0,r1\", operands);
-	}
-    }
-  else
-    {
-      fprintf (stderr, \"smov 0 else err \");
-      abort ();
-    }
-    
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      op2const = INTVAL (operands[2]);
-      if (op2const % 4 != 0)
-	{
-	  output_asm_insn (\"mov.w %2,r2\", operands);
-	  return \"smov/n/f.b\";
-	}
-      op2const = op2const / 4;
-      if (op2const <= 4)
-	{
-	  if (op2const == 0)
-	    abort (0);
-	  if (op2const == 1)
-	    return \"mov.w @r0,@r1\";
-	  output_asm_insn (\"mov.w @r0,@r1\", operands);
-	  if (op2const == 2)
-	    return \"mov.w @(4,r0),@(4,r1)\";
-	  output_asm_insn (\"mov.w @(4,r0),@(4,r1)\", operands);
-	  if (op2const == 3)
-	    return \"mov.w @(8,r0),@(8,r1)\";
-	  output_asm_insn (\"mov.w @(8,r0),@(8,r1)\", operands);
-	  return \"mov.w @(12,r0),@(12,r1)\";
-	}
-	    
-      operands[2] = GEN_INT (op2const);
-      output_asm_insn (\"mov.w %2,r2\", operands);
-      return \"smov/n/f.w\";
-    }
-  else
-    {
-      fprintf (stderr, \"smov 0 else err \");
-      abort ();
-      output_asm_insn (\"mov %2.h,r2.w\", operands);
-      return \"smov/n/f.b\";
-    }
-
-}")
-
-;; M.Yuhara 89.08.24
-;; experiment on the built-in strcpy (__builtin_smov)
-;;
-;; len = 0 means unknown string length.
-;;
-;; mem:SI is dummy. Necessary so as not to be deleted by optimization.
-;; Use of BLKmode would be better...
-;;
-;;
-(define_insn "smovsi"
-  [(set (mem:SI (match_operand:SI 0 "general_operand" "=rm"))
-	(mem:SI (match_operand:SI 1 "general_operand" "rm")))
-   (use (match_operand:SI 2 "general_operand" "i"))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 1))
-   (clobber (reg:SI 2))
-   (clobber (reg:SI 3))]
-  ""
-  "*
-{
-  int len, wlen, blen, offset;
-  char tmpstr[128];
-  rtx xoperands[1];
-
-  len = INTVAL (operands[2]);
-  output_asm_insn (\"mov.w %1,r0\\t; begin built-in strcpy\", operands);
-  output_asm_insn (\"mov.w %0,r1\", operands);
-
-  if (len == 0)
-    {
-      output_asm_insn (\"mov:z.w #0,r2\", operands);
-      output_asm_insn (\"mov:z.w #0,r3\", operands);
-      return \"smov/eq/f.b\\t; end built-in strcpy\";
-    }
-
-  wlen = len / 4;
-  blen = len - wlen * 4;
-
-  if (wlen > 0)
-    {
-      if (len <= 40 && !TARGET_FORCE_SMOV)
-	{
-	  output_asm_insn (\"mov.w @r0,@r1\", operands);
-	  offset = 4;
-	  while ( (blen = len - offset) > 0)
-	    {
-	      if (blen >= 4)
-		{
-		  sprintf (tmpstr, \"mov.w @(%d,r0),@(%d,r1)\",
-			   offset, offset);
-		  output_asm_insn (tmpstr, operands);
-		  offset += 4;
-		}
-	      else if (blen >= 2)
-		{
-		  sprintf (tmpstr, \"mov.h @(%d,r0),@(%d,r1)\",
-			   offset, offset);
-		  output_asm_insn (tmpstr, operands);
-		  offset += 2;
-		}
-	      else
-		{
-		  sprintf (tmpstr, \"mov.b @(%d,r0),@(%d,r1)\",
-			   offset, offset);
-		  output_asm_insn (tmpstr, operands);
-		  offset++;
-		}
-	    }
-	  return \"\\t\\t; end built-in strcpy\";
-	}
-      else
-	{
-	  xoperands[0] = GEN_INT (wlen);
-	  output_asm_insn (\"mov.w %0,r2\", xoperands);
-	  output_asm_insn (\"smov/n/f.w\", operands);
-	}
-    }
-
-  if (blen >= 2)
-    {
-      output_asm_insn (\"mov.h @r0,@r1\", operands);
-      if (blen == 3)
-	output_asm_insn (\"mov.b @(2,r0),@(2,r1)\", operands);
-    }
-  else if (blen == 1)
-    {
-      output_asm_insn (\"mov.b @r0,@r1\", operands);
-    }
-
-  return \"\\t\\t; end built-in strcpy\";
-}")
-
-;; truncation instructions
-(define_insn "truncsiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(truncate:QI
-	 (match_operand:SI 1 "general_operand" "rmi")))]
-  ""
-  "mov %1.w,%0.b")
-;  "*
-;{
-;  if (GET_CODE (operands[0]) == REG)
-;    return \"mov.w %1,%0\";
-;  if (GET_CODE (operands[1]) == MEM)
-;    operands[1] = adj_offsettable_operand (operands[1], 3);
-;  return \"mov.b %1,%0\";
-;}")
-
-(define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(truncate:QI
-	 (match_operand:HI 1 "general_operand" "rmi")))]
-  ""
-  "mov %1.h,%0.b")
-;  "*
-;{
-;  if (GET_CODE (operands[0]) == REG)
-;    return \"mov.h %1,%0\";
-;  if (GET_CODE (operands[1]) == MEM)
-;    operands[1] = adj_offsettable_operand (operands[1], 1);
-;  return \"mov.b %1,%0\";
-;}")
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(truncate:HI
-	 (match_operand:SI 1 "general_operand" "rmi")))]
-  ""
-  "mov %1.w,%0.h")
-;  "*
-;{
-;  if (GET_CODE (operands[0]) == REG)
-;    return \"mov.w %1,%0\";
-;  if (GET_CODE (operands[1]) == MEM)
-;    operands[1] = adj_offsettable_operand (operands[1], 2);
-;  return \"mov.h %1,%0\";
-;}")
-
-;; zero extension instructions
-;; define_expand (68k) -> define_insn (Gmicro)
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-        (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "movu %1.h,%0.w")
-
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-        (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "movu %1.b,%0.h")
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-        (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "movu %1.b,%0.w")
-
-
-;; sign extension instructions
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-        (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "mov %1.h,%0.w")
-
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-        (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "mov %1.b,%0.h")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-        (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "mov %1.b,%0.w")
-
-
-
-;; Conversions between float and double.
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "general_operand" "=*frm,f")
-	(float_extend:DF
-	  (match_operand:SF 1 "general_operand" "f,rmF")))]
-  "TARGET_FPU"
-  "*
-{
-  if (FPU_REG_P (operands[0]))
-    {
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	return output_move_const_double (operands);
-      if (GREG_P (operands[1]))
-	{
-	  output_asm_insn (\"mov.w %1,%-\", operands);
-	  return \"fmov %+.s,%0.d\";
-	}
-      return \"fmov %1.s,%0.d\";
-    }
-  else
-    {
-      if (GREG_P (operands[0]))
-	{
-	  output_asm_insn (\"fmov %1.s,%-.d\", operands);
-	  output_asm_insn (\"mov.w %+,%0\", operands);
-	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-	  return \"mov.w %+,%0\";
-	}
-      return \"fmov %1.s,%0.d\";
-    }
-}")
-
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "general_operand" "=rfm")
-	(float_truncate:SF
-	  (match_operand:DF 1 "general_operand" "f")))]
-  "TARGET_FPU"
-  "*
-{
-  if (GREG_P (operands[0]))
-    {
-      output_asm_insn (\"fmov %1.d,%-.s\", operands);
-      return \"mov.w %+,%0\";
-    }
-  return \"fmov %1.d,%0.s\";
-}")
-
-;; Conversion between fixed point and floating point.
-;; Note that among the fix-to-float insns
-;; the ones that start with SImode come first.
-;; That is so that an operand that is a CONST_INT
-;; (and therefore lacks a specific machine mode).
-;; will be recognized as SImode (which is always valid)
-;; rather than as QImode or HImode.
-
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(float:SF (match_operand:SI 1 "general_operand" "rmi")))]
-  "TARGET_FPU"
-  "fldi %1.w,%0.s")
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(float:DF (match_operand:SI 1 "general_operand" "rmi")))]
-  "TARGET_FPU"
-  "fldi %1.w,%0.d")
-
-(define_insn "floathisf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(float:SF (match_operand:HI 1 "general_operand" "rmi")))]
-  "TARGET_FPU"
-  "fldi %1.h,%0.s")
-
-(define_insn "floathidf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(float:DF (match_operand:HI 1 "general_operand" "rmi")))]
-  "TARGET_FPU"
-  "fldi %1.h,%0.d")
-
-(define_insn "floatqisf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(float:SF (match_operand:QI 1 "general_operand" "rmi")))]
-  "TARGET_FPU"
-  "fldi %1.b,%0.s")
-
-(define_insn "floatqidf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(float:DF (match_operand:QI 1 "general_operand" "rmi")))]
-  "TARGET_FPU"
-  "fldi %1.b,%0.d")
-
-;;; Convert a float to a float whose value is an integer.
-;;; This is the first stage of converting it to an integer type.
-;
-;(define_insn "ftruncdf2"
-;  [(set (match_operand:DF 0 "general_operand" "=f")
-;	(fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
-;  "TARGET_FPU"
-;  "*
-;{
-;  return \"fintrz.d %f1,%0\";
-;}")
-;
-;(define_insn "ftruncsf2"
-;  [(set (match_operand:SF 0 "general_operand" "=f")
-;	(fix:SF (match_operand:SF 1 "general_operand" "fFm")))]
-;  "TARGET_FPU"
-;  "*
-;{
-;  return \"fintrz.s %f1,%0\";
-;}")
-
-;; Convert a float to an integer.
-
-(define_insn "fix_truncsfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(fix:QI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
-  "TARGET_FPU"
-  "fsti %1.s,%0.b")
-
-(define_insn "fix_truncsfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(fix:HI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
-  "TARGET_FPU"
-  "fsti %1.s,%0.h")
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
-  "TARGET_FPU"
-  "fsti %1.s,%0.w")
-
-(define_insn "fix_truncdfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(fix:QI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
-  "TARGET_FPU"
-  "fsti %1.d,%0.b")
-
-(define_insn "fix_truncdfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(fix:HI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
-  "TARGET_FPU"
-  "fsti %1.d,%0.h")
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
-  "TARGET_FPU"
-  "fsti %1.d,%0.w")
-
-
-;;; Special add patterns
-;;; 89.09.28
-
-;; This should be redundant; please find out why regular addsi3
-;; fails to match this case.
-
-;(define_insn ""
-;  [(set (mem:SI (plus:SI
-;		    (plus:SI (match_operand 0 "general_operand" "r")
-;			     (match_operand 1 "general_operand" "r"))
-;		    (match_operand 2 "general_operand" "i")))
-;	(plus:SI
-;	    (mem:SI (plus:SI
-;			(plus:SI (match_dup 0)
-;				 (match_dup 1))
-;			(match_dup 2)))
-;	    (match_operand 3 "general_operand" "rmi")))]
-;  ""
-;  "add.w %3,@(%c2,%0,%1)")
-
-
-;; add instructions
-
-;; Note that the last two alternatives are near-duplicates
-;; in order to handle insns generated by reload.
-;; This is needed since they are not themselves reloaded,
-;; so commutativity won't apply to them.
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm,!r,!r")
-	(plus:SI (match_operand:SI 1 "general_operand" "%0,r,ri")
-		 (match_operand:SI 2 "general_operand" "rmi,ri,r")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    {
-      if (GET_CODE (operands[2]) == CONST_INT)
-	{
-	  operands[1] = operands[2];
-	  return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]);
-	}
-      else
-	return \"add.w %2,%0\";
-    }
-  else
-    {
-      if (GET_CODE (operands[1]) == REG
-	  && REGNO (operands[0]) == REGNO (operands[1]))
-	return \"add.w %2,%0\";
-      if (GET_CODE (operands[2]) == REG
-	  && REGNO (operands[0]) == REGNO (operands[2]))
-	return \"add.w %1,%0\";
-
-      if (GET_CODE (operands[1]) == REG)
-	{
-	  if (GET_CODE (operands[2]) == REG)
-	    return \"mova.w @(%1,%2),%0\";
-	  else
-	    return \"mova.w @(%c2,%1),%0\";
-	}
-      else
-	return \"mova.w @(%c1,%2),%0\";
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(plus:SI (match_operand:SI 1 "general_operand" "0")
-		 (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))]
-  ""
-  "*
-{
-  if (CONSTANT_P (operands[2]))
-    {
-      operands[1] = operands[2];
-      return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]);
-    }
-  else
-    return \"add %2.h,%0.w\";
-}")
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(plus:HI (match_operand:HI 1 "general_operand" "%0")
-		 (match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) < 0)
-    return \"sub.h #%n2,%0\";
-  if (GREG_P (operands[0]))
-    {
-      if (CONSTANT_P (operands[2]))
-	return \"add:l %2,%0.w\";
-      else
-	return \"add:l %2.h,%0.w\";
-    }
-  return \"add.h %2,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
-	(plus:HI (match_dup 0)
-		 (match_operand:HI 1 "general_operand" "rmi")))]
-  ""
-  "add.h %1,%0")
-
-(define_insn "addqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(plus:QI (match_operand:QI 1 "general_operand" "%0")
-		 (match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) < 0)
-    return \"sub.b #%n2,%0\";
-  if (GREG_P (operands[0]))
-    {
-      if (CONSTANT_P (operands[2]))
-	return \"add:l %2,%0.w\";
-      else
-	return \"add:l %2.b,%0.w\";
-    }
-  return \"add.b %2,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
-	(plus:QI (match_dup 0)
-		 (match_operand:QI 1 "general_operand" "rmi")))]
-  ""
-  "add.b %1,%0")
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(plus:DF (match_operand:DF 1 "general_operand" "%0")
-		 (match_operand:DF 2 "general_operand" "fmG")))]
-  "TARGET_FPU"
-  "fadd.d %f2,%0")
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(plus:SF (match_operand:SF 1 "general_operand" "%0")
-		 (match_operand:SF 2 "general_operand" "fmG")))]
-  "TARGET_FPU"
-  "fadd.s %f2,%0")
-
-;; subtract instructions
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm,!r")
-	(minus:SI (match_operand:SI 1 "general_operand" "0,r")
-		  (match_operand:SI 2 "general_operand" "rmi,i")))]
-  ""
-  "*
-{
-  if (which_alternative == 0
-      || (GET_CODE (operands[1]) == REG
-	  && REGNO (operands[0]) == REGNO (operands[1])))
-    {
-      if (GET_CODE (operands[2]) == CONST_INT)
-	{
-	  operands[1] = operands[2];
-	  return sub_imm_word (INTVAL (operands[1]),
-			       operands[0], &operands[1]);
-	}
-      else
-	return \"sub.w %2,%0\";
-    }
-  else
-    return \"mova.w @(%n2,%1),%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(minus:SI (match_operand:SI 1 "general_operand" "0")
-		  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))]
-  ""
-  "sub %2.h,%0.w")
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(minus:HI (match_operand:HI 1 "general_operand" "0")
-		  (match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) < 0
-      && INTVAL (operands[2]) != 0x8000)
-    return \"add.h #%n2,%0\";
-  return \"sub.h %2,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
-	(minus:HI (match_dup 0)
-		  (match_operand:HI 1 "general_operand" "rmi")))]
-  ""
-  "sub.h %1,%0")
-
-(define_insn "subqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(minus:QI (match_operand:QI 1 "general_operand" "0")
-		  (match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) < 0
-      && INTVAL (operands[2]) != 0x80)
-    return \"add.b #%n2,%0\";
-  return \"sub.b %2,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
-	(minus:QI (match_dup 0)
-		  (match_operand:QI 1 "general_operand" "rmi")))]
-  ""
-  "sub.b %1,%0")
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(minus:DF (match_operand:DF 1 "general_operand" "0")
-		  (match_operand:DF 2 "general_operand" "fmG")))]
-  "TARGET_FPU"
-  "fsub.d %f2,%0")
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(minus:SF (match_operand:SF 1 "general_operand" "0")
-		  (match_operand:SF 2 "general_operand" "fmG")))]
-  "TARGET_FPU"
-  "fsub.s %f2,%0")
-
-
-;; multiply instructions
-
-(define_insn "mulqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(mult:QI (match_operand:QI 1 "general_operand" "%0")
-		 (match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  "mul.b %2,%0")
-
-
-(define_insn "mulhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(mult:HI (match_operand:HI 1 "general_operand" "%0")
-		 (match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "mul.h %2,%0")
-
-;; define_insn "mulhisi3"
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(mult:SI (match_operand:SI 1 "general_operand" "%0")
-		 (match_operand:SI 2 "general_operand" "rmi")))]
-  ""
-  "mul.w %2,%0")
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(mult:DF (match_operand:DF 1 "general_operand" "%0")
-		 (match_operand:DF 2 "general_operand" "fmG")))]
-  "TARGET_FPU"
-  "fmul.d %f2,%0")
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(mult:SF (match_operand:SF 1 "general_operand" "%0")
-		 (match_operand:SF 2 "general_operand" "fmG")))]
-  "TARGET_FPU"
-  "fmul.s %f2,%0")
-
-
-;; divide instructions
-
-(define_insn "divqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(div:QI (match_operand:QI 1 "general_operand" "0")
-		(match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  "div.b %2,%0")
-
-(define_insn "divhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(div:HI (match_operand:HI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "div.h %2,%0")
-
-(define_insn "divhisi3"
-  [(set (match_operand:HI 0 "general_operand" "=r")
-	(div:HI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "div %2.h,%0.w")
-
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(div:SI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:SI 2 "general_operand" "rmi")))]
-  ""
-  "div.w %2,%0")
-
-(define_insn "udivqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(udiv:QI (match_operand:QI 1 "general_operand" "0")
-		 (match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  "divu.b %2,%0")
-
-(define_insn "udivhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(udiv:HI (match_operand:HI 1 "general_operand" "0")
-		 (match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "divu.h %2,%0")
-
-(define_insn "udivhisi3"
-  [(set (match_operand:HI 0 "general_operand" "=r")
-	(udiv:HI (match_operand:SI 1 "general_operand" "0")
-		 (match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "divu %2.h,%0.w")
-
-(define_insn "udivsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(udiv:SI (match_operand:SI 1 "general_operand" "0")
-		 (match_operand:SI 2 "general_operand" "rmi")))]
-  ""
-  "divu.w %2,%0")
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(div:DF (match_operand:DF 1 "general_operand" "0")
-		(match_operand:DF 2 "general_operand" "fmG")))]
-  "TARGET_FPU"
-  "fdiv.d %f2,%0")
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(div:SF (match_operand:SF 1 "general_operand" "0")
-		(match_operand:SF 2 "general_operand" "fmG")))]
-  "TARGET_FPU"
-  "fdiv.s %f2,%0")
-
-;; Remainder instructions.
-
-(define_insn "modqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(mod:QI (match_operand:QI 1 "general_operand" "0")
-		(match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  "rem.b %2,%0")
-
-(define_insn "modhisi3"
-  [(set (match_operand:HI 0 "general_operand" "=r")
-	(mod:HI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "rem.h %2,%0")
-
-(define_insn "umodqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(umod:QI (match_operand:QI 1 "general_operand" "0")
-		 (match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  "remu.b %2,%0")
-
-(define_insn "umodhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(umod:HI (match_operand:HI 1 "general_operand" "0")
-		 (match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "remu.h %2,%0")
-
-(define_insn "umodhisi3"
-  [(set (match_operand:HI 0 "general_operand" "=r")
-	(umod:HI (match_operand:SI 1 "general_operand" "0")
-		 (match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "remu %2.h,%0.w")
-
-;; define_insn "divmodsi4"
-
-(define_insn "udivmodsi4"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(udiv:SI (match_operand:SI 1 "general_operand" "0")
-		 (match_operand:SI 2 "general_operand" "rmi")))
-   (set (match_operand:SI 3 "general_operand" "=r")
-	(umod:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "mov.w #0,%3;divx.w %2,%0,%3")
-
-;; logical-and instructions
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(and:SI (match_operand:SI 1 "general_operand" "%0")
-		(match_operand:SI 2 "general_operand" "rmi")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
-      && (GREG_P (operands[0])
-	  || offsettable_memref_p (operands[0])))
-   
-    { 
-      if (GET_CODE (operands[0]) != REG)
-        operands[0] = adj_offsettable_operand (operands[0], 2);
-      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
-      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
-      CC_STATUS_INIT;
-      return \"and.h %2,%0\";
-    }
-  return \"and.w %2,%0\";
-}")
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(and:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "and.h %2,%0")
-
-(define_insn "andqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(and:QI (match_operand:QI 1 "general_operand" "%0")
-		(match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  "and.b %2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(and:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))
-		(match_operand:SI 2 "general_operand" "0")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    return \"and %1,%0.w\";
-  return \"and %1.h,%0.w\";
-}")
-
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(and:SI (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm"))
-		(match_operand:SI 2 "general_operand" "0")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    return \"and %1,%0.w\";
-  return \"and %1.b,%0.w\";
-}")
-
-;; inclusive-or instructions
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(ior:SI (match_operand:SI 1 "general_operand" "%0")
-		(match_operand:SI 2 "general_operand" "rmi")))]
-  ""
-  "*
-{
-  register int logval;
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) >> 16 == 0
-      && (GREG_P (operands[0])
-	  || offsettable_memref_p (operands[0])))
-    { 
-      if (GET_CODE (operands[0]) != REG)
-        operands[0] = adj_offsettable_operand (operands[0], 2);
-      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
-      CC_STATUS_INIT;
-      return \"or.h %2,%0\";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
-      && (GREG_P (operands[0])
-	  || offsettable_memref_p (operands[0])))
-    { 
-      if (GREG_P (operands[0]))
-	{
-	  if (logval < 7)
-	    {
-	      operands[1] = GEN_INT (7 - logval);
-	      return \"bset.b %1,%0\";
-	    }
-	  operands[1] = GEN_INT (31 - logval);
-	  return \"bset.w %1,%0\";
-	}
-      else
-        {
-	  operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
-	  operands[1] = GEN_INT (7 - (logval % 8));
-	}
-      return \"bset.b %1,%0\";
-    }
-  return \"or.w %2,%0\";
-}")
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(ior:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "or.h %2,%0")
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(ior:QI (match_operand:QI 1 "general_operand" "%0")
-		(match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  "or.b %2,%0")
-
-;; xor instructions
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(xor:SI (match_operand:SI 1 "general_operand" "%0")
-		(match_operand:SI 2 "general_operand" "rmi")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) >> 16 == 0
-      && (offsettable_memref_p (operands[0]) || GREG_P (operands[0])))
-    { 
-      if (! GREG_P (operands[0]))
-	operands[0] = adj_offsettable_operand (operands[0], 2);
-      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
-      CC_STATUS_INIT;
-      return \"xor.h %2,%0\";
-    }
-  return \"xor.w %2,%0\";
-}")
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(xor:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "xor.h %2,%0")
-
-(define_insn "xorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(xor:QI (match_operand:QI 1 "general_operand" "%0")
-		(match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  "xor.b %2,%0")
-
-;; negation instructions
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
-  ""
-  "neg.w %0")
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
-  ""
-  "neg.h %0")
-
-(define_insn "negqi2"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(neg:QI (match_operand:QI 1 "general_operand" "0")))]
-  ""
-  "neg.b %0")
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
-  "TARGET_FPU"
-  "fneg.s %f1,%0")
-
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
-  "TARGET_FPU"
-  "fneg.d %f1,%0")
-
-
-;; Absolute value instructions
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
-  "TARGET_FPU"
-  "fabs.s %f1,%0")
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
-  "TARGET_FPU"
-  "fabs.d %f1,%0")
-
-
-;; one complement instructions
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(not:SI (match_operand:SI 1 "general_operand" "0")))]
-  ""
-  "not.w %0")
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(not:HI (match_operand:HI 1 "general_operand" "0")))]
-  ""
-  "not.h %0")
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(not:QI (match_operand:QI 1 "general_operand" "0")))]
-  ""
-  "not.b %0")
-
-;; Optimized special case of shifting.
-;; Must precede the general case.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
-		     (const_int 24)))]
-  "GET_CODE (XEXP (operands[1], 0)) != POST_INC
-   && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
-  "mov:l %1.b,%0.w")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
-		     (const_int 24)))]
-  "GET_CODE (XEXP (operands[1], 0)) != POST_INC
-   && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
-  "movu %1.b,%0.w")
-
-(define_insn ""
-  [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
-		       (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
-				    (const_int 24))))]
-  "(GET_CODE (operands[0]) == CONST_INT
-    && (INTVAL (operands[0]) & ~0xff) == 0)"
-  "*
-{
-  cc_status.flags |= CC_REVERSED;
-  if (my_signed_comp (insn))
-    return \"cmp.b %0,%1\";
-  return \"cmpu.b %0,%1\";
-}")
-
-(define_insn ""
-  [(set (cc0) (compare (lshiftrt:SI (match_operand:SI 0 "memory_operand" "m")
-				    (const_int 24))
-		       (match_operand:QI 1 "general_operand" "i")))]
-  "(GET_CODE (operands[1]) == CONST_INT
-    && (INTVAL (operands[1]) & ~0xff) == 0)"
-  "*
-  if (my_signed_comp (insn))
-	return \"cmp.b %1,%0\";
-  return \"cmpu.b %1,%0\";
-")
-
-(define_insn ""
-  [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
-		       (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
-				    (const_int 24))))]
-  "(GET_CODE (operands[0]) == CONST_INT
-    && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)"
-  "*
-  cc_status.flags |= CC_REVERSED;
-  if (my_signed_comp (insn))
-	return \"cmp.b %0,%1\";
-  return \"cmpu.b %0,%1\";
-")
-
-(define_insn ""
-  [(set (cc0) (compare (ashiftrt:SI (match_operand:SI 0 "memory_operand" "m")
-				    (const_int 24))
-		       (match_operand:QI 1 "general_operand" "i")))]
-  "(GET_CODE (operands[1]) == CONST_INT
-    && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)"
-  "*
-  if (my_signed_comp (insn))
-	return \"cmp.b %1,%0\";
-  return \"cmpu.b %1,%0\";
-")
-
-;; arithmetic shift instructions
-;; We don't need the shift memory by 1 bit instruction
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(ashift:SI (match_operand:SI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "rmi")))]
-  ""
-  "sha.w %2,%0")
-
-(define_insn "ashlhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(ashift:HI (match_operand:HI 1 "general_operand" "0")
-		   (match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "sha.h %2,%0")
-
-(define_insn "ashlqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(ashift:QI (match_operand:QI 1 "general_operand" "0")
-		   (match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  "sha.b %2,%0")
-
-;; Arithmetic right shift on the Gmicro works by negating the shift count
-
-;; ashiftrt -> ashift
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(ashift:SI (match_operand:SI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "rmi")))]
-  ""
-  "{ operands[2] = negate_rtx (SImode, operands[2]); }")
-
-;; ashiftrt -> ashift
-(define_expand "ashrhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(ashift:HI (match_operand:HI 1 "general_operand" "0")
-		     (match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  " { operands[2] = negate_rtx (HImode, operands[2]); }")
-
-;; ashiftrt -> ashift
-(define_expand "ashrqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(ashift:QI (match_operand:QI 1 "general_operand" "0")
-		     (match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  " { operands[2] = negate_rtx (QImode, operands[2]); }")
-
-;; logical shift instructions
-
-;; Logical right shift on the gmicro works by negating the shift count,
-;; then emitting a right shift with the shift count negated.  This means
-;; that all actual shift counts in the RTL will be positive.  This 
-;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
-;; which isn't valid.
-
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
-		     (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "n")))]
-  ""
-  "shl.w %n2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
-		     (neg:SI (match_operand:SI 2 "general_operand" "rm"))))]
-  ""
-  "shl.w %2,%0")
-
-(define_expand "lshrhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
-		     (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, HImode, negate_rtx (HImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
-		     (match_operand:HI 2 "const_int_operand" "n")))]
-  ""
-  "shl.h %n2,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
-		     (neg:HI (match_operand:HI 2 "general_operand" "rm"))))]
-  ""
-  "shl.h %2,%0")
-
-(define_expand "lshrqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
-		     (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
-		     (match_operand:QI 2 "const_int_operand" "n")))]
-  ""
-  "shl.b %n2,%0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
-		     (neg:QI (match_operand:QI 2 "general_operand" "rm"))))]
-  ""
-  "shl.b %2,%0")
-
-;; rotate instructions
-
-(define_insn "rotlsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(rotate:SI (match_operand:SI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "rmi")))]
-  ""
-  "rol.w %2,%0")
-
-(define_insn "rotlhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(rotate:HI (match_operand:HI 1 "general_operand" "0")
-		   (match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  "rol.h %2,%0")
-
-(define_insn "rotlqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(rotate:QI (match_operand:QI 1 "general_operand" "0")
-		   (match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  "rol.b %2,%0")
-
-(define_expand "rotrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(rotatert:SI (match_operand:SI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "rmi")))]
-  ""
-  " { operands[2] = negate_rtx (SImode, operands[2]); }")
-
-(define_expand "rotrhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-	(rotatert:HI (match_operand:HI 1 "general_operand" "0")
-		     (match_operand:HI 2 "general_operand" "rmi")))]
-  ""
-  " { operands[2] = negate_rtx (HImode, operands[2]); }")
-
-(define_expand "rotrqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rm")
-	(rotatert:QI (match_operand:QI 1 "general_operand" "0")
-		     (match_operand:QI 2 "general_operand" "rmi")))]
-  ""
-  " { operands[2] = negate_rtx (QImode, operands[2]); }")
-
-;; Special cases of bit-field insns which we should
-;; recognize in preference to the general case.
-;; These handle aligned 8-bit and 16-bit fields,
-;; which can usually be done with move instructions.
-
-;; Should I add  mode_dependent_address_p ????
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+rm")
-			 (match_operand:SI 1 "immediate_operand" "i")
-			 (match_operand:SI 2 "immediate_operand" "i"))
-	(match_operand:SI 3 "general_operand" "rm"))]
-  "TARGET_BITFIELD
-   && GET_CODE (operands[1]) == CONST_INT
-   && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
-   && GET_CODE (operands[2]) == CONST_INT
-   && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
-   && (GET_CODE (operands[0]) != REG
-       || ( INTVAL (operands[1]) + INTVAL (operands[2]) == 32))"
-  "*
-{
-  if (GET_CODE (operands[3]) == MEM)
-    operands[3] = adj_offsettable_operand (operands[3],
-					   (32 - INTVAL (operands[1])) / 8);
-
-  if (GET_CODE (operands[0]) == REG)
-    {
-      if (INTVAL (operands[1]) == 8)
-	return \"movu %3.b,%0.w\";
-      return \"movu %3.h,%0.w\";
-    }
-  else
-    {
-      operands[0]
-	= adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
-      if (INTVAL (operands[1]) == 8)
-	return \"mov.b %3,%0\";
-      return \"mov.h %3,%0\";
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=&r")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "rm")
-			 (match_operand:SI 2 "immediate_operand" "i")
-			 (match_operand:SI 3 "immediate_operand" "i")))]
-  "TARGET_BITFIELD
-   && GET_CODE (operands[2]) == CONST_INT
-   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && GET_CODE (operands[3]) == CONST_INT
-   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
-  "*
-{
-  if (!REG_P (operands[1]))
-    operands[1]
-      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
-
-  if (REG_P (operands[0]))
-    {
-      if (REG_P (operands[1]))
-	{
-	  if (INTVAL (operands[2]) == 8)
-	    {			/* width == 8 */
-	      switch (INTVAL (operands[3]))
-		{
-		case 0:
-		  return \"mov.w %1,%0;shl.w #-24,%0\";
-		  break;
-		case 8:
-		  return \"mov.w %1,%0;shl.w #8,%0;shl.w #-24,%0\";
-		  break;
-		case 16:
-		  return \"mov.w %1,%0;shl.w #16,%0;shl.w #-24,%0\";
-		  break;
-		case 24:
-		  return \"movu %1.b,%0.w\";
-		  break;
-		default:
-		  myabort (2);
-		}
-	    }
-	  else
-	    {
-	      switch (INTVAL (operands[3]))
-		{
-		case 0:
-		  return \"mov.w %1,%0;shl.w #-16,%0\";
-		  break;
-		case 16:
-		  return \"movu %1.h,%0.w\";
-		  break;
-		default:
-		  myabort (3);
-		}
-	    }
-	}
-      else
-	{
-	  if (INTVAL (operands[2]) == 8)
-	    return \"movu %1.h,%0.w\";
-	  else
-	    return \"movu %1.b,%0.w\";
-	}
-    }
-  else
-    {				/* op[0] == MEM */
-      if (INTVAL (operands[2]) == 8)
-	return \"movu %1.b,%0.w\";
-      return \"movu %1.h,%0.w\";
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
-			 (match_operand:SI 2 "immediate_operand" "i")
-			 (match_operand:SI 3 "immediate_operand" "i")))]
-  "TARGET_BITFIELD
-   && GET_CODE (operands[2]) == CONST_INT
-   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && GET_CODE (operands[3]) == CONST_INT
-   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
-  "*
-{
-  if (!REG_P (operands[1]))
-    operands[1]
-      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
-
-  if (REG_P (operands[0]))
-    {
-      if (REG_P (operands[1]))
-	{
-	  if (INTVAL (operands[2]) == 8)
-	    {			/* width == 8 */
-	      switch (INTVAL (operands[3]))
-		{
-		case 0:
-		  return \"mov.w %1,%0;sha.w #-24,%0\";
-		  break;
-		case 8:
-		  return \"mov.w %1,%0;shl.w #8,%0;sha.w #-24,%0\";
-		  break;
-		case 16:
-		  return \"mov.w %1,%0;shl.w #16,%0;sha.w #-24,%0\";
-		  break;
-		case 24:
-		  return \"mov %1.b,%0.w\";
-		  break;
-		default:
-		  myabort (4);
-		}
-	    }
-	  else
-	    {
-	      switch (INTVAL (operands[3]))
-		{
-		case 0:
-		  return \"mov.w %1,%0;sha.w #-16,%0\";
-		  break;
-		case 16:
-		  return \"mov %1.h,%0.w\";
-		  break;
-		default:
-		  myabort (5);
-		}
-	    }
-	}
-      else
-	{
-	  if (INTVAL (operands[2]) == 8)
-	    return \"mov %1.h,%0.w\";
-	  else
-	    return \"mov %1.b,%0.w\";
-	}
-    }
-  else
-    {				/* op[0] == MEM */
-      if (INTVAL (operands[2]) == 8)
-	return \"mov %1.b,%0.w\";
-      return \"mov %1.h,%0.w\";
-    }
-}")
-
-;; Bit field instructions, general cases.
-;; "o,d" constraint causes a nonoffsettable memref to match the "o"
-;; so that its address is reloaded.
-
-;; extv dest:SI src(:QI/:SI) width:SI pos:SI
-;;        r.w    m            r.w/#    rmi  
-;;        %0     %1           %2       %3
-
-(define_expand "extv"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(sign_extract:SI (match_operand:SI 1 "general_operand" "")
-			 (match_operand:SI 2 "general_operand" "")
-			 (match_operand:SI 3 "general_operand" "")))]
-  "TARGET_BITFIELD"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
-			 (match_operand:SI 2 "general_operand" "ri")
-			 (match_operand:SI 3 "general_operand" "rmi")))]
-  "TARGET_BITFIELD"
-  "bfext %3,%2,%1,%0")
-
-
-(define_expand "extzv"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(zero_extract:SI (match_operand:SI 1 "general_operand" "")
-			 (match_operand:SI 2 "general_operand" "")
-			 (match_operand:SI 3 "general_operand" "")))]
-  "TARGET_BITFIELD"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
-			 (match_operand:SI 2 "general_operand" "ri")
-			 (match_operand:SI 3 "general_operand" "rmi")))]
-  "TARGET_BITFIELD"
-  "bfextu %3,%2,%1,%0")
-
-;; There is no insn on the Gmicro to NOT/SET/CLR bitfield.
-
-
-;; insv dest(BF):QI/SI  width:SI  pos:SI  src:SI
-;;        m                r.w      rmi     r.w/i
-;;        0                1        2       3
-
-
-(define_expand "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
-			 (match_operand:SI 1 "general_operand" "")
-			 (match_operand:SI 2 "general_operand" ""))
-	(match_operand:SI 3 "general_operand" ""))]
-  "TARGET_BITFIELD"
-  "")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m,m")
-			 (match_operand:SI 1 "general_operand" "r,i")
-			 (match_operand:SI 2 "general_operand" "rmi,i"))
-	(match_operand:SI 3 "general_operand" "ri,ri"))]
-  "TARGET_BITFIELD"
-  "bfinsu %3,%2,%1,%0")
-
-;;; bfins/bfinsu ????????
-
-;; == == == == == == == == == == == == == 
-
-;; Now recognize bit field insns that operate on registers
-;; (or at least were intended to do so).
-
-;; On the Gmicro/300,
-;; bitfield instructions are not applicable to registers ;-<
-;; But I write the register cases, because without them the gcc
-;; seems to use "and" instruction with some other instructions
-;; instead of using a shift instruction.
-;; It is because on many processors shift instructions are slower.
-;; On the Gmicro/300 which has a barrel shifter,
-;; it is faster to use a shift instruction.
-;;
-;; Restricts width and offset to be immediates.
-;;
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "immediate_operand" "i")
-			 (match_operand:SI 3 "immediate_operand" "i")))]
-  "TARGET_BITFIELD"
-  "*
-{
-  if (REGNO (operands[0]) != REGNO (operands[1]))
-    output_asm_insn (\"mov.w %1,%0\", operands);
-  if (INTVAL (operands[3]) != 0)
-    output_asm_insn (\"shl.w %3,%0\", operands);
-  operands[2] = GEN_INT (-(32 - INTVAL (operands[2])));
-  return \"sha.w %3,%0\";
-}")
-    
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "immediate_operand" "i")
-			 (match_operand:SI 3 "immediate_operand" "i")))]
-  "TARGET_BITFIELD"
-  "*
-{
-  if (REGNO (operands[0]) != REGNO (operands[1]))
-    output_asm_insn (\"mov.w %1,%0\", operands);
-  if (INTVAL (operands[3]) != 0)
-    output_asm_insn (\"shl.w %3,%0\", operands);
-  operands[2] = GEN_INT (-(32 - INTVAL (operands[2])));
-  return \"shl.w %3,%0\";
-}")
-
-
-;; There are more descriptions for m68k, but not yet for the Gmicro.
-;;
-
-;; Basic conditional jump instructions.
-
-
-(define_insn "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  OUTPUT_JUMP (\"beq %b0\", \"fbeq %b0\", \"beq %b0\");
-}")
-
-(define_insn "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  OUTPUT_JUMP (\"bne %b0\", \"fbne %b0\", \"bne %b0\");
-}")
-
-(define_insn "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-  OUTPUT_JUMP (\"bgt %b0\", \"fbgt %b0\", 0);
-")
-
-(define_insn "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "bgt %b0")
-
-(define_insn "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-  OUTPUT_JUMP (\"blt %b0\", \"fblt %b0\", \"bms %b0\");
-")
-
-;; bms ?????
-;; 
-
-(define_insn "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "blt %b0")
-
-(define_insn "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-  OUTPUT_JUMP (\"bge %b0\", \"fbge %b0\", \"bmc %b0\");
-")
-
-;; bmc ??
-
-(define_insn "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "bge %b0")
-
-(define_insn "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "ble %b0")
-
-(define_insn "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "ble %b0")
-
-;; Negated conditional jump instructions.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  OUTPUT_JUMP (\"bne %b0\", \"fbne %b0\", \"bne %b0\");
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  OUTPUT_JUMP (\"beq %b0\", \"fbeq %b0\", \"beq %b0\");
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-  OUTPUT_JUMP (\"ble %b0\", \"fbngt %b0\", 0);
-")
-;; fbngt ???
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "ble %b0")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-  OUTPUT_JUMP (\"bge %b0\", \"fbnlt %b0\", \"jbmc %b0\");
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "blt %b0")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-  OUTPUT_JUMP (\"blt %b0\", \"fbnge %b0\", \"jbms %b0\");
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "blt %b0")
-;; ????
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-  OUTPUT_JUMP (\"bgt %b0\", \"fbnle %b0\", 0);
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "bgt %b0")
-
-;; Unconditional and other jump instructions
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "bra %b0")
-
-(define_insn "tablejump"
-  [(set (pc)
-	(plus:SI (pc) (match_operand:SI 0 "general_operand" "r")))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmp @(pc:b,4:4,%0)")
-
-;;
-;; Should Add code for "ACB", "SCB". !!! ????
-;; See m68k.h (dbra)
-;;
-
-;; Call subroutine with no return value.
-(define_insn "call"
-  [(call (match_operand:QI 0 "general_operand" "m")
-	 (match_operand:SI 1 "general_operand" "rmi"))]
-  ;; Operand 1 not really used on the Gmicro.
-
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM
-      && GET_CODE (XEXP (operands[0],0)) == SYMBOL_REF)
-    return \"bsr %b0\";
-  return \"jsr %0\";
-}")
-
-;; Call subroutine, returning value in operand 0
-;; (which must be a hard register).
-(define_insn "call_value"
-  [(set (match_operand 0 "" "=rf")
-	(call (match_operand:QI 1 "general_operand" "m")
-	      (match_operand:SI 2 "general_operand" "rmi")))]
-  ;; Operand 2 not really used on the Gmicro.
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == MEM
-      && GET_CODE (XEXP (operands[1],0)) == SYMBOL_REF)
-    return \"bsr %b1\";
-  return \"jsr %1\";
-}")
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-(define_insn "nop"
-  [(const_int 0)]
-    ""
-    "nop")
-
-;; Turned off because the general move-an-address pattern handles it.
-;; 
-;; Thus goes after the move instructions
-;; because the move instructions are better (require no spilling)
-;; when they can apply. 
-;; After add/sub now !!
-
-;(define_insn "pushasi"
-;  [(set (match_operand:SI 0 "push_operand" "=m")
-;	(match_operand:SI 1 "address_operand" "p"))]
-;  ""
-;  "*
-;{
-;  if (GET_CODE (operands[1]) == CONST_INT)
-;    return push_imm_word (INTVAL (operands[1]), operands[0]);
-;  if (CONSTANT_P (operands[1]))
-;    return \"mov.w %1,%-\";
-;  if (GET_CODE (operands[1]) == REG)
-;    return \"mov.w %1,%-\";
-;  else if (GET_CODE (operands[1]) == MEM)
-;    {
-;      return \"mov.w %1,%-\";
-;    }
-;  else
-;    return \"mova.w %p1,%-\";
-;}")
-
-;; This should not be used unless the add/sub insns can't be.
-
-/* mova.[whq] 89.08.11 for test M.Yuhara */
-;(define_insn ""
-;  [(set (match_operand:SI 0 "general_operand" "=rm")
-;	(address (match_operand:SI 1 "address_operand" "p")))]
-;  ""
-;  "*
-;{
-;    if (GET_CODE (operands[1]) == CONST_INT)
-;        return mov_imm_word (INTVAL (operands[1]), operands[0]);
-;    if (CONSTANT_P (operands[1]))
-;        return \"mov.w %1,%0\";
-;    if (GET_CODE (operands[1]) == REG)
-;        return \"mov.w %1,%0\";
-;    else  if (GET_CODE (operands[1]) == MEM) {
-;	operands[1] = XEXP (operands[1],0);
-;        return \"mov.w %1,%0\";
-;    }
-;    else
-;        return \"mova.w %p1,%0\";
-;}")
-
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(address (match_operand:HI 1 "address_operand" "")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    return mov_imm_word (INTVAL (operands[1]), operands[0]);
-  if (CONSTANT_P (operands[1]))
-    return \"mov.w %1,%0\";
-  if (GET_CODE (operands[1]) == REG)
-    return \"mov.w %1,%0\";
-  else  if (GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = XEXP (operands[1],0);
-      return \"mov.w %1,%0\";	/* OK ? */
-    }
-  else
-    return \"mova.w %p1,%0\";
-}")
-
-;(define_insn ""
-;  [(set (match_operand:SI 0 "general_operand" "=rm")
-;	(match_operand:QI 1 "address_operand" "p"))]
-;  ""
-;  "*
-;{
-;  if (push_operand (operands[0], SImode))
-;    return \"mova %1,%-\";
-;  return \"mova %1,%0\";
-;}")
-
-;(define_insn ""
-;  [(set (match_operand:SI 0 "general_operand" "=rm")
-;	(match_operand:QI 1 "address_operand" "p"))]
-;  ""
-;  "*
-;{
-;  if (CONSTANT_P (operands[1]))
-;    return \"mov.w %1,%0\";
-;  else if (GET_CODE (operands[1]) == REG)
-;    return \"mov.w %1,%0\";
-;  else if (GET_CODE (operands[1]) == MEM)
-;    {
-;      operands[1] = XEXP (operands[1],0);
-;      return \"mov.w %1,%0 ; OK?\";
-;    }
-;  else if (GET_CODE (operands[0]) == REG
-;	   && GET_CODE (operands[1]) == PLUS)
-;    {
-;      rtx xreg, xdisp;
-;
-;      if (GET_CODE (XEXP (operands[1], 0)) == REG 
-;	  && REGNO (XEXP (operands[1], 0)) == REGNO (operands[0]))
-;	{
-;	  xreg = XEXP (operands[1], 0);
-;	  xdisp = XEXP (operands[1],1);
-;	}
-;      else
-;	{
-;	  xreg = XEXP (operands[1], 1);
-;	  xdisp = XEXP (operands[1],0);
-;	}
-;
-;      if (GET_CODE (xreg) == REG
-;	  && REGNO (xreg) == REGNO (operands[0])
-;	  && (CONSTANT_P (xdisp) || GET_CODE (xdisp) == REG))
-;	{
-;	  operands[1] = xdisp;
-;	  if (CONSTANT_P (xdisp))
-;	    return add_imm_word (INTVAL (xdisp), xreg, &operands[1]);
-;	  else
-;	    return \"add.w %1,%0\";
-;	}
-;    }
-;  return \"mova.w %p1,%0\";
-;}")
-
-;; This is the first machine-dependent peephole optimization.
-;; It is useful when a floating value is returned from a function call
-;; and then is moved into an FP register.
-;; But it is mainly intended to test the support for these optimizations.
-
-(define_peephole
-  [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
-   (set (match_operand:DF 0 "register_operand" "=f")
-	(match_operand:DF 1 "register_operand" "r"))]
-  "FPU_REG_P (operands[0]) && ! FPU_REG_P (operands[1])"
-  "*
-{
-  rtx xoperands[2];
-  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-  output_asm_insn (\"mov.w %1,@sp\", xoperands);
-  output_asm_insn (\"mov.w %1,%-\", operands);
-  return \"fmov.d %+,%0\";
-}
-")
diff --git a/gcc/config/gnu.h b/gcc/config/gnu.h
deleted file mode 100755
index d169164..0000000
--- a/gcc/config/gnu.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Configuration common to all targets running the GNU system.  */
-
-/* Provide GCC options for standard feature-test macros.  */
-#undef CPP_SPEC
-#define CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{bsd:-D_BSD_SOURCE}"
-
-/* Default C library spec.  Use -lbsd-compat for gcc -bsd.  */
-#undef LIB_SPEC
-#define LIB_SPEC "%{bsd:-lbsd-compat} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
-
-/* Standard include directory.  In GNU, "/usr" is a four-letter word.  */
-#undef STANDARD_INCLUDE_DIR
-#define STANDARD_INCLUDE_DIR "/include"
-
-
-/* We have atexit.  */
-#define HAVE_ATEXIT
-
-/* Implicit library calls should use memcpy, not bcopy, etc.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* The system headers under GNU are C++-aware.  */
-#define NO_IMPLICIT_EXTERN_C
diff --git a/gcc/config/gofast.h b/gcc/config/gofast.h
deleted file mode 100755
index 84bea51..0000000
--- a/gcc/config/gofast.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* US Software GOFAST floating point library support.
-   Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This is used by fp-bit.c.  */
-#define US_SOFTWARE_GOFAST
-
-/* The US Software GOFAST library requires special optabs support.
-   There is no negation libcall, and several others have names different
-   from gcc.  This file consolidates the support in one place.
-
-   The basic plan is to leave gcc proper alone and via some hook fix things
-   after the optabs have been set up.  Our main entry point is
-   INIT_GOFAST_OPTABS.  */
-
-#define INIT_GOFAST_OPTABS \
-  do { \
-    GOFAST_CLEAR_NEG_FLOAT_OPTAB; \
-    GOFAST_RENAME_LIBCALLS; \
-  } while (0)
-
-#define GOFAST_CLEAR_NEG_FLOAT_OPTAB \
-  do { \
-    int mode; \
-    for (mode = SFmode; (int) mode <= (int) TFmode; \
-	 mode = (enum machine_mode) ((int) mode + 1)) \
-      neg_optab->handlers[(int) mode].libfunc = NULL_RTX; \
-  } while (0)
-
-#define GOFAST_RENAME_LIBCALLS \
-  add_optab->handlers[(int) SFmode].libfunc = gen_rtx (SYMBOL_REF, Pmode, "fpadd"); \
-  add_optab->handlers[(int) DFmode].libfunc = gen_rtx (SYMBOL_REF, Pmode, "dpadd"); \
-  sub_optab->handlers[(int) SFmode].libfunc = gen_rtx (SYMBOL_REF, Pmode, "fpsub"); \
-  sub_optab->handlers[(int) DFmode].libfunc = gen_rtx (SYMBOL_REF, Pmode, "dpsub"); \
-  smul_optab->handlers[(int) SFmode].libfunc = gen_rtx (SYMBOL_REF, Pmode, "fpmul"); \
-  smul_optab->handlers[(int) DFmode].libfunc = gen_rtx (SYMBOL_REF, Pmode, "dpmul"); \
-  flodiv_optab->handlers[(int) SFmode].libfunc = gen_rtx (SYMBOL_REF, Pmode, "fpdiv"); \
-  flodiv_optab->handlers[(int) DFmode].libfunc = gen_rtx (SYMBOL_REF, Pmode, "dpdiv"); \
-  cmp_optab->handlers[(int) SFmode].libfunc = gen_rtx (SYMBOL_REF, Pmode, "fpcmp"); \
-  cmp_optab->handlers[(int) DFmode].libfunc = gen_rtx (SYMBOL_REF, Pmode, "dpcmp"); \
-\
-  extendsfdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "fptodp"); \
-  truncdfsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "dptofp"); \
-\
-  eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "fpcmp"); \
-  nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "fpcmp"); \
-  gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "fpcmp"); \
-  gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "fpcmp"); \
-  ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "fpcmp"); \
-  lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "fpcmp"); \
-\
-  eqdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "dpcmp"); \
-  nedf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "dpcmp"); \
-  gtdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "dpcmp"); \
-  gedf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "dpcmp"); \
-  ltdf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "dpcmp"); \
-  ledf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "dpcmp"); \
-\
-  eqxf2_libfunc = NULL_RTX; \
-  nexf2_libfunc = NULL_RTX; \
-  gtxf2_libfunc = NULL_RTX; \
-  gexf2_libfunc = NULL_RTX; \
-  ltxf2_libfunc = NULL_RTX; \
-  lexf2_libfunc = NULL_RTX; \
-\
-  eqtf2_libfunc = NULL_RTX; \
-  netf2_libfunc = NULL_RTX; \
-  gttf2_libfunc = NULL_RTX; \
-  getf2_libfunc = NULL_RTX; \
-  lttf2_libfunc = NULL_RTX; \
-  letf2_libfunc = NULL_RTX; \
-\
-  floatsisf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "sitofp"); \
-  floatsidf_libfunc = gen_rtx (SYMBOL_REF, Pmode, "litodp"); \
-  fixsfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "fptosi"); \
-  fixdfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "dptoli"); \
-  fixunssfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "fptoui"); \
-  fixunsdfsi_libfunc = gen_rtx (SYMBOL_REF, Pmode, "dptoul"); \
-
-/* End of GOFAST_RENAME_LIBCALLS */
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
deleted file mode 100755
index 0870ede..0000000
--- a/gcc/config/h8300/h8300.c
+++ /dev/null
@@ -1,3143 +0,0 @@
-/* Subroutines for insn-output.c for Hitachi H8/300.
-   Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
-   Contributed by Steve Chamberlain (sac@cygnus.com),
-   Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#include "expr.h"
-#include "tree.h"
-#include "obstack.h"
-
-/* Forward declarations.  */
-void print_operand_address ();
-char *index ();
-
-static int h8300_interrupt_function_p PROTO ((tree));
-static int h8300_monitor_function_p PROTO ((tree));
-static int h8300_os_task_function_p PROTO ((tree));
-
-/* CPU_TYPE, says what cpu we're compiling for.  */
-int cpu_type;
-
-/* True if the current function is an interrupt handler
-   (either via #pragma or an attribute specification).  */
-int interrupt_handler;
-
-/* True if the current function is an OS Task
-   (via an attribute specification).  */
-int os_task;
-
-/* True if the current function is a monitor
-   (via an attribute specification).  */
-int monitor;
-
-/* True if a #pragma saveall has been seen for the current function.  */
-int pragma_saveall;
-
-static char *names_big[] =
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7"};
-
-static char *names_extended[] =
-{"er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7"};
-
-static char *names_upper_extended[] =
-{"e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7"};
-
-/* Points to one of the above.  */
-/* ??? The above could be put in an array indexed by CPU_TYPE.  */
-char **h8_reg_names;
-
-/* Various operations needed by the following, indexed by CPU_TYPE.  */
-
-static char *h8_push_ops[2] =
-{"push", "push.l"};
-static char *h8_pop_ops[2] =
-{"pop", "pop.l"};
-static char *h8_mov_ops[2] =
-{"mov.w", "mov.l"};
-
-char *h8_push_op, *h8_pop_op, *h8_mov_op;
-
-/* Initialize various cpu specific globals at start up.  */
-
-void
-h8300_init_once ()
-{
-  if (TARGET_H8300)
-    {
-      cpu_type = (int) CPU_H8300;
-      h8_reg_names = names_big;
-    }
-  else
-    {
-      /* For this we treat the H8/300 and H8/S the same.  */
-      cpu_type = (int) CPU_H8300H;
-      h8_reg_names = names_extended;
-    }
-  h8_push_op = h8_push_ops[cpu_type];
-  h8_pop_op = h8_pop_ops[cpu_type];
-  h8_mov_op = h8_mov_ops[cpu_type];
-}
-
-char *
-byte_reg (x, b)
-     rtx x;
-     int b;
-{
-  static char *names_small[] =
-  {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
-   "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
-
-  return names_small[REGNO (x) * 2 + b];
-}
-
-/* REGNO must be saved/restored across calls if this macro is true.  */
-
-#define WORD_REG_USED(regno)					\
-  (regno < 7 &&							\
-   (interrupt_handler						\
-    || pragma_saveall						\
-    || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno])	\
-    || (regs_ever_live[regno] && !call_used_regs[regno])))
-
-/* Output assembly language to FILE for the operation OP with operand size
-   SIZE to adjust the stack pointer.  */
-
-static void
-dosize (file, op, size)
-     FILE *file;
-     char *op;
-     unsigned int size;
-{
-  /* On the h8300h and h8300s, for sizes <= 8 bytes it is as good or
-     better to use adds/subs insns rather than add.l/sub.l
-     with an immediate value.   */
-  if (size > 4 && size <= 8 && (TARGET_H8300H || TARGET_H8300S))
-    {
-      /* Crank the size down to <= 4 */
-      fprintf (file, "\t%ss\t#%d,sp\n", op, 4);
-      size -= 4;
-    }
-
-  switch (size)
-    {
-    case 4:
-      if (TARGET_H8300H || TARGET_H8300S)
-	{
-	  fprintf (file, "\t%ss\t#%d,sp\n", op, 4);
-	  size = 0;
-	  break;
-	}
-    case 3:
-      fprintf (file, "\t%ss\t#%d,sp\n", op, 2);
-      size -= 2;
-      /* Fall through...  */
-    case 2:
-    case 1:
-      fprintf (file, "\t%ss\t#%d,sp\n", op, size);
-      size = 0;
-      break;
-    case 0:
-      break;
-    default:
-      if (TARGET_H8300)
-	{
-	  if (current_function_needs_context
-	      && strcmp (op, "sub") == 0)
-	    {
-	      /* Egad.  We don't have a temporary to hold the
-		 size of the frame in the prologue!  Just inline
-		 the bastard since this shouldn't happen often.  */
-	      while (size >= 2)
-		{
-		  fprintf (file, "\tsubs\t#2,sp\n");
-		  size -= 2;
-		}
-
-	      if (size)
-		fprintf (file, "\tsubs\t#1,sp\n");
-
-	      size = 0;
-	    }
-	  else
-	    fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op);
-	}
-      else
-	fprintf (file, "\t%s\t#%d,sp\n", op, size);
-      size = 0;
-      break;
-    }
-}
-
-/* Output assembly language code for the function prologue.  */
-static int push_order[FIRST_PSEUDO_REGISTER] =
-{0, 1, 2, 3, 4, 5, 6, -1, -1, -1};
-static int pop_order[FIRST_PSEUDO_REGISTER] =
-{6, 5, 4, 3, 2, 1, 0, -1, -1, -1};
-
-/* This is what the stack looks like after the prolog of 
-   a function with a frame has been set up:
-
-   <args>
-   PC
-   FP			<- fp
-   <locals>
-   <saved registers> 	<- sp
-
-   This is what the stack looks like after the prolog of
-   a function which doesn't have a frame:
-
-   <args>
-   PC
-   <locals>
-   <saved registers>   	<- sp
-*/
-
-void
-function_prologue (file, size)
-     FILE *file;
-     int size;
-{
-  register int mask = 0;
-  int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
-  int idx;
-
-  /* Note a function with the interrupt attribute and set interrupt_handler
-     accordingly.  */
-  if (h8300_interrupt_function_p (current_function_decl))
-    interrupt_handler = 1;
-
-  /* If the current function has the OS_Task attribute set, then
-     we have a naked prologue.  */
-  if (h8300_os_task_function_p (current_function_decl))
-    {
-      fprintf (file, ";OS_Task prologue\n");
-      os_task = 1;
-      return;
-    }
-
-  if (h8300_monitor_function_p (current_function_decl))
-    {
-      /* My understanding of monitor functions is they act just
-	 like interrupt functions, except the prologue must
-	 mask interrupts.  */
-      fprintf (file, ";monitor prologue\n");
-      interrupt_handler = 1;
-      monitor = 1;
-      if (TARGET_H8300)
-	{
-	  fprintf (file, "\tsubs\t#2,sp\n");
-	  fprintf (file, "\tpush\tr0\n");
-	  fprintf (file, "\tstc\tccr,r0l\n");
-	  fprintf (file, "\torc\t#128,ccr\n");
-	  fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
-	}
-      else
-	{
-	  fprintf (file, "\tpush\ter0\n");
-	  fprintf (file, "\tstc\tccr,r0l\n");
-	  fprintf (file, "\torc\t#128,ccr\n");
-	  fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
-	}
-    }
-
-  if (frame_pointer_needed)
-    {
-      /* Push fp */
-      fprintf (file, "\t%s\t%s\n", h8_push_op,
-	       h8_reg_names[FRAME_POINTER_REGNUM]);
-      fprintf (file, "\t%s\t%s,%s\n", h8_mov_op,
-	       h8_reg_names[STACK_POINTER_REGNUM],
-	       h8_reg_names[FRAME_POINTER_REGNUM]);
-    }
-
-  /* leave room for locals */
-  dosize (file, "sub", fsize);
-
-  /* Push the rest of the registers */
-  for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
-    {
-      int regno = push_order[idx];
-
-      if (regno >= 0
-	  && WORD_REG_USED (regno)
-	  && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM))
-	{
-	  if (TARGET_H8300S)
-	    {
-	      /* Try to push multiple registers.  */
-	      if (regno == 0 || regno == 4)
-		{
-		  int second_regno = push_order[idx + 1];
-		  int third_regno = push_order[idx + 2];
-		  int fourth_regno = push_order[idx + 3];
-
-		  if (fourth_regno >= 0
-		      && WORD_REG_USED (fourth_regno)
-		      && (!frame_pointer_needed
-			  || fourth_regno != FRAME_POINTER_REGNUM)
-		      && third_regno >= 0
-		      && WORD_REG_USED (third_regno)
-		      && (!frame_pointer_needed
-			  || third_regno != FRAME_POINTER_REGNUM)
-		      && second_regno >= 0
-		      && WORD_REG_USED (second_regno)
-		      && (!frame_pointer_needed
-			  || second_regno != FRAME_POINTER_REGNUM))
-		    {
-		      fprintf (file, "\tstm.l %s-%s,@-sp\n", 
-			       h8_reg_names[regno],
-			       h8_reg_names[fourth_regno]);
-		      idx += 3;
-		      continue;
-		    }
-		}
-	      if (regno == 0 || regno == 4)
-		{
-		  int second_regno = push_order[idx + 1];
-		  int third_regno = push_order[idx + 2];
-
-		  if (third_regno >= 0
-		      && WORD_REG_USED (third_regno)
-		      && (!frame_pointer_needed
-			  || third_regno != FRAME_POINTER_REGNUM)
-		      && second_regno >= 0
-		      && WORD_REG_USED (second_regno)
-		      && (!frame_pointer_needed
-			  || second_regno != FRAME_POINTER_REGNUM))
-		    {
-		      fprintf (file, "\tstm.l %s-%s,@-sp\n", 
-			       h8_reg_names[regno],
-			       h8_reg_names[third_regno]);
-		      idx += 2;
-		      continue;
-		    }
-		}
-	      if (regno == 0 || regno == 2 || regno == 4 || regno == 6)
-		{
-		  int second_regno = push_order[idx + 1];
-
-		  if (second_regno >= 0
-		      && WORD_REG_USED (second_regno)
-		      && (!frame_pointer_needed
-			  || second_regno != FRAME_POINTER_REGNUM))
-		    {
-		      fprintf (file, "\tstm.l %s-%s,@-sp\n", 
-			       h8_reg_names[regno],
-			       h8_reg_names[second_regno]);
-		      idx += 1;
-		      continue;
-		    }
-		}
-	    }
-	  fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[regno]);
-	}
-    }
-}
-
-/* Output assembly language code for the function epilogue.  */
-
-void
-function_epilogue (file, size)
-     FILE *file;
-     int size;
-{
-  register int regno;
-  register int mask = 0;
-  int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
-  int idx;
-  rtx insn = get_last_insn ();
-
-  if (os_task)
-    {
-      /* OS_Task epilogues are nearly naked -- they just have an
-	 rts instruction.  */
-      fprintf (file, ";OS_task epilogue\n");
-      fprintf (file, "\trts\n");
-      goto out;
-    }
-
-  /* monitor epilogues are the same as interrupt function epilogues.
-     Just make a note that we're in an monitor epilogue.  */
-  if (monitor)
-    fprintf(file, ";monitor epilogue\n");
-
-  /* If the last insn was a BARRIER, we don't have to write any code.  */
-  if (GET_CODE (insn) == NOTE)
-    insn = prev_nonnote_insn (insn);
-  if (insn && GET_CODE (insn) == BARRIER)
-    return;
-
-  /* Pop the saved registers. */
-  for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
-    {
-      int regno = pop_order[idx];
-
-      if (regno >= 0
-	  && WORD_REG_USED (regno)
-	  && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM))
-	{
-	  if (TARGET_H8300S)
-	    {
-	      /* Try to pop multiple registers.  */
-	      if (regno == 7 || regno == 3)
-		{
-		  int second_regno = pop_order[idx + 1];
-		  int third_regno = pop_order[idx + 2];
-		  int fourth_regno = pop_order[idx + 3];
-
-		  if (fourth_regno >= 0
-		      && WORD_REG_USED (fourth_regno)
-		      && (!frame_pointer_needed
-			  || fourth_regno != FRAME_POINTER_REGNUM)
-		      && third_regno >= 0
-		      && WORD_REG_USED (third_regno)
-		      && (!frame_pointer_needed
-			  || third_regno != FRAME_POINTER_REGNUM)
-		      && second_regno >= 0
-		      && WORD_REG_USED (second_regno)
-		      && (!frame_pointer_needed
-			  || second_regno != FRAME_POINTER_REGNUM))
-		    {
-		      fprintf (file, "\tldm.l @sp+,%s-%s\n", 
-			       h8_reg_names[fourth_regno],
-			       h8_reg_names[regno]);
-		      idx += 3;
-		      continue;
-		    }
-		}
-	      if (regno == 6 || regno == 2)
-		{
-		  int second_regno = pop_order[idx + 1];
-		  int third_regno = pop_order[idx + 2];
-
-		  if (third_regno >= 0
-		      && WORD_REG_USED (third_regno)
-		      && (!frame_pointer_needed
-			  || third_regno != FRAME_POINTER_REGNUM)
-		      && second_regno >= 0
-		      && WORD_REG_USED (second_regno)
-		      && (!frame_pointer_needed
-			  || second_regno != FRAME_POINTER_REGNUM))
-		    {
-		      fprintf (file, "\tldm.l @sp+,%s-%s\n", 
-			       h8_reg_names[third_regno],
-			       h8_reg_names[regno]);
-		      idx += 2;
-		      continue;
-		    }
-		}
-	      if (regno == 7 || regno == 5 || regno == 3 || regno == 1)
-		{
-		  int second_regno = pop_order[idx + 1];
-
-		  if (second_regno >= 0
-		      && WORD_REG_USED (second_regno)
-		      && (!frame_pointer_needed
-			  || second_regno != FRAME_POINTER_REGNUM))
-		    {
-		      fprintf (file, "\tldm.l @sp+,%s-%s\n", 
-			       h8_reg_names[second_regno],
-			       h8_reg_names[regno]);
-		      idx += 1;
-		      continue;
-		    }
-		}
-	    }
-	  fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[regno]);
-	}
-    }
-
-  /* deallocate locals */
-  dosize (file, "add", fsize);
-
-  /* pop frame pointer if we had one. */
-  if (frame_pointer_needed)
-    fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[FRAME_POINTER_REGNUM]);
-
-  /* If this is a monitor function, there is one register still left on
-     the stack.  */
-  if (monitor)
-    fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[0]);
-
-  if (interrupt_handler)
-    fprintf (file, "\trte\n");
-  else
-    fprintf (file, "\trts\n");
-
-out:
-  interrupt_handler = 0;
-  os_task = 0;
-  monitor = 0;
-  pragma_saveall = 0;
-}
-
-/* Output assembly code for the start of the file.  */
-
-asm_file_start (file)
-     FILE *file;
-{
-  fprintf (file, ";\tGCC For the Hitachi H8/300\n");
-  fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
-  fprintf (file, ";\trelease F-1\n");
-  if (optimize)
-    fprintf (file, "; -O%d\n", optimize);
-  if (TARGET_H8300H)
-    fprintf (file, "\n\t.h8300h\n");
-  else if (TARGET_H8300S)
-    fprintf (file, "\n\t.h8300s\n");
-  else
-    fprintf (file, "\n\n");
-  output_file_directive (file, main_input_filename);
-}
-
-/* Output assembly language code for the end of file.  */
-
-void
-asm_file_end (file)
-     FILE *file;
-{
-  fprintf (file, "\t.end\n");
-}
-
-/* Return true if VALUE is a valid constant for constraint 'P'.
-   IE: VALUE is a power of two <= 2**15.  */
-
-int
-small_power_of_two (value)
-     int value;
-{
-  switch (value)
-    {
-    case 1:
-    case 2:
-    case 4:
-    case 8:
-    case 16:
-    case 32:
-    case 64:
-    case 128:
-    case 256:
-    case 512:
-    case 1024:
-    case 2048:
-    case 4096:
-    case 8192:
-    case 16384:
-    case 32768:
-      return 1;
-    }
-  return 0;
-}
-
-/* Return true if VALUE is a valid constant for constraint 'O', which
-   means that the constant would be ok to use as a bit for a bclr
-   instruction.  */
-
-int
-ok_for_bclr (value)
-     int value;
-{
-  return small_power_of_two ((~value) & 0xff);
-}
-
-/* Return true is OP is a valid source operand for an integer move
-   instruction.  */
-
-int
-general_operand_src (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
-    return 1;
-  return general_operand (op, mode);
-}
-
-/* Return true if OP is a valid destination operand for an integer move
-   instruction.  */
-
-int
-general_operand_dst (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
-    return 1;
-  return general_operand (op, mode);
-}
-
-/* Return true if OP is a const valid for a bit clear instruction.  */
-
-int
-o_operand (operand, mode)
-     rtx operand;
-     enum machine_mode mode;
-{
-  return (GET_CODE (operand) == CONST_INT
-	  && CONST_OK_FOR_O (INTVAL (operand)));
-}
-
-/* Return true if OP is a const valid for a bit set or bit xor instruction.  */
-
-int
-p_operand (operand, mode)
-     rtx operand;
-     enum machine_mode mode;
-{
-  return (GET_CODE (operand) == CONST_INT
-	  && CONST_OK_FOR_P (INTVAL (operand)));
-}
-
-/* Return true if OP is a valid call operand.  */
-
-int
-call_insn_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == MEM)
-    {
-      rtx inside = XEXP (op, 0);
-      if (register_operand (inside, Pmode))
-	return 1;
-      if (CONSTANT_ADDRESS_P (inside))
-	return 1;
-    }
-  return 0;
-}
-
-int
-adds_subs_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    {
-      if (INTVAL (op) <= 4 && INTVAL (op) >= 0)
-	return 1;
-      if (INTVAL (op) >= -4 && INTVAL (op) <= 0)
-	return 1;
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && INTVAL (op) != 7
-	  && (INTVAL (op) <= 8 && INTVAL (op) >= 0))
-	return 1;
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && INTVAL (op) != -7
-	  && (INTVAL (op) >= -8 && INTVAL (op) <= 0))
-	return 1;
-    }
-  return 0;
-}
-
-/* Return nonzero if op is an adds/subs operand which only requires
-   one insn to implement.  It is assumed that OP is already an adds/subs
-   operand.  */
-int
-one_insn_adds_subs_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int val = INTVAL (op);
-
-  if (val == 1 || val == -1
-      || val == 2 || val == -2
-      || ((TARGET_H8300H || TARGET_H8300S)
-	  && (val == 4 || val == -4)))
-    return 1;
-  return 0;
-}
-
-char *
-output_adds_subs (operands)
-     rtx *operands;
-{
-  int val = INTVAL (operands[2]);
-
-  /* First get the value into the range -4..4 inclusive.
-
-     The only way it can be out of this range is when TARGET_H8300H
-     or TARGET_H8300S is true, thus it is safe to use adds #4 and subs #4.  */
-  if (val > 4)
-    {
-      output_asm_insn ("adds #4,%A0", operands);
-      val -= 4;
-    }
-
-  if (val < -4)
-    {
-      output_asm_insn ("subs #4,%A0", operands);
-      val += 4;
-    }
-
-  /* Handle case were val == 4 or val == -4 and we're compiling
-     for TARGET_H8300H or TARGET_H8300S.  */
-  if ((TARGET_H8300H || TARGET_H8300S)
-      && val == 4)
-    return "adds #4,%A0";
-
-  if ((TARGET_H8300H || TARGET_H8300S)
-      && val == -4)
-    return "subs #4,%A0";
-
-  if (val > 2)
-    {
-      output_asm_insn ("adds #2,%A0", operands);
-      val -= 2;
-    }
-
-  if (val < -2)
-    {
-      output_asm_insn ("subs #2,%A0", operands);
-      val += 2;
-    }
-
-  /* val should be one or two now.  */
-  if (val == 2)
-    return "adds #2,%A0";
-
-  if (val == -2)
-    return "subs #2,%A0";
-
-  /* val should be one now.  */
-  if (val == 1)
-    return "adds #1,%A0";
-
-  if (val == -1)
-    return "subs #1,%A0";
-
-  /* If not optimizing, we might be asked to add 0.  */
-  if (val == 0)
-    return "";
-
-  /* In theory, this can't happen.  */
-  abort ();
-}
-
-/* Return true if OP is a valid call operand, and OP represents
-   an operand for a small call (4 bytes instead of 6 bytes).  */
-
-int
-small_call_insn_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == MEM)
-    {
-      rtx inside = XEXP (op, 0);
-
-      /* Register indirect is a small call.  */
-      if (register_operand (inside, Pmode))
-	return 1;
-
-      /* A call through the function vector is a small
-	 call too.  */
-      if (GET_CODE (inside) == SYMBOL_REF
-	  && SYMBOL_REF_FLAG (inside))
-	return 1;
-    }
-  /* Otherwise it's a large call.  */
-  return 0;
-}
-
-/* Return true if OP is a valid jump operand.  */
-
-int
-jump_address_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == REG)
-    return mode == Pmode;
-
-  if (GET_CODE (op) == MEM)
-    {
-      rtx inside = XEXP (op, 0);
-      if (register_operand (inside, Pmode))
-	return 1;
-      if (CONSTANT_ADDRESS_P (inside))
-	return 1;
-    }
-  return 0;
-}
-
-/* Recognize valid operands for bitfield instructions.  */
-
-extern int rtx_equal_function_value_matters;
-
-int
-bit_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  /* We can except any general operand, expept that MEM operands must
-     be limited to those that use addresses valid for the 'U' constraint.  */
-  if (!general_operand (op, mode))
-    return 0;
-
-  /* Accept any mem during RTL generation.  Otherwise, the code that does
-     insv and extzv will think that we can not handle memory.  However,
-     to avoid reload problems, we only accept 'U' MEM operands after RTL
-     generation.  This means that any named pattern which uses this predicate
-     must force its operands to match 'U' before emitting RTL.  */
-
-  if (GET_CODE (op) == REG)
-    return 1;
-  if (GET_CODE (op) == SUBREG)
-    return 1;
-  if (!rtx_equal_function_value_matters)
-    {
-      /* We're building rtl */
-      return GET_CODE (op) == MEM;
-    }
-  else
-    {
-      return (GET_CODE (op) == MEM
-	      && EXTRA_CONSTRAINT (op, 'U'));
-    }
-}
-
-int
-bit_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == MEM
-	  && EXTRA_CONSTRAINT (op, 'U'));
-}
-
-/* Recognize valid operators for bit test.  */
-
-int
-eq_operator (x, mode)
-     rtx x;
-     enum machine_mode mode;
-{
-  return (GET_CODE (x) == EQ || GET_CODE (x) == NE);
-}
-
-/* Handle machine specific pragmas for compatibility with existing
-   compilers for the H8/300.
-
-   pragma saveall generates prolog/epilog code which saves and
-   restores all the registers on function entry.
-
-   pragma interrupt saves and restores all registers, and exits with
-   an rte instruction rather than an rts.  A pointer to a function
-   with this attribute may be safely used in an interrupt vector.  */
-
-int
-handle_pragma (p_getc, p_ungetc, pname)
-     int (*  p_getc) PROTO ((void));
-     void (* p_ungetc) PROTO ((int));
-     char * pname;
-{
-  int retval = 0;
-
-  if (strcmp (pname, "interrupt") == 0)
-    interrupt_handler = retval = 1;
-  else if (strcmp (pname, "saveall") == 0)
-    pragma_saveall = retval = 1;
-
-  return retval;
-}
-
-/* If the next arg with MODE and TYPE is to be passed in a register, return
-   the rtx to represent where it is passed.  CUM represents the state after
-   the last argument.  NAMED is not used.  */
-
-static char *hand_list[] =
-{
-  "__main",
-  "__cmpsi2",
-  "__divhi3",
-  "__modhi3",
-  "__udivhi3",
-  "__umodhi3",
-  "__divsi3",
-  "__modsi3",
-  "__udivsi3",
-  "__umodsi3",
-  "__mulhi3",
-  "__mulsi3",
-  "__reg_memcpy",
-  "__reg_memset",
-  "__ucmpsi2",
-  0,
-};
-
-/* Return an RTX to represent where a value with mode MODE will be returned
-   from a function.  If the result is 0, the argument is pushed.  */
-
-rtx
-function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  rtx result = 0;
-  char *fname;
-  int regpass = 0;
-
-  /* Never pass unnamed arguments in registers.  */
-  if (!named)
-    return 0;
-
-  /* Pass 3 regs worth of data in regs when user asked on the command line.  */
-  if (TARGET_QUICKCALL)
-    regpass = 3;
-
-  /* If calling hand written assembler, use 4 regs of args.  */
-
-  if (cum->libcall)
-    {
-      char **p;
-
-      fname = XSTR (cum->libcall, 0);
-
-      /* See if this libcall is one of the hand coded ones.  */
-
-      for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
-	;
-
-      if (*p)
-	regpass = 4;
-    }
-
-  if (regpass)
-    {
-      int size;
-
-      if (mode == BLKmode)
-	size = int_size_in_bytes (type);
-      else
-	size = GET_MODE_SIZE (mode);
-
-      if (size + cum->nbytes > regpass * UNITS_PER_WORD)
-	{
-	  result = 0;
-	}
-      else
-	{
-	  switch (cum->nbytes / UNITS_PER_WORD)
-	    {
-	    case 0:
-	      result = gen_rtx (REG, mode, 0);
-	      break;
-	    case 1:
-	      result = gen_rtx (REG, mode, 1);
-	      break;
-	    case 2:
-	      result = gen_rtx (REG, mode, 2);
-	      break;
-	    case 3:
-	      result = gen_rtx (REG, mode, 3);
-	      break;
-	    default:
-	      result = 0;
-	    }
-	}
-    }
-
-  return result;
-}
-
-/* Return the cost of the rtx R with code CODE.  */
-
-int
-const_costs (r, c)
-     rtx r;
-     enum rtx_code c;
-{
-  switch (c)
-    {
-    case CONST_INT:
-      switch (INTVAL (r))
-	{
-	case 0:
-	case 1:
-	case 2:
-	case -1:
-	case -2:
-	  return 0;
-	case 4:
-	case -4:
-	  if (TARGET_H8300H || TARGET_H8300S)
-	    return 0;
-	  else
-	    return 1;
-	default:
-	  return 1;
-	}
-
-    case CONST:
-    case LABEL_REF:
-    case SYMBOL_REF:
-      return 3;
-
-    case CONST_DOUBLE:
-      return 20;
-
-    default:
-      return 4;
-    }
-}
-
-/* Documentation for the machine specific operand escapes:
-
-   'A' print rn in h8/300 mode, erN in H8/300H mode
-   'C' print (operand - 2).
-   'E' like s but negative.
-   'F' like t but negative.
-   'G' constant just the negative
-   'M' turn a 'M' constant into its negative mod 2.
-   'P' if operand is incing/decing sp, print .w, otherwise .b.
-   'R' print operand as a byte:8 address if appropriate, else fall back to
-       'X' handling.
-   'S' print operand as a long word
-   'T' print operand as a word
-   'U' if operand is incing/decing sp, print l, otherwise nothing.
-   'V' find the set bit, and print its number.
-   'W' find the clear bit, and print its number.
-   'X' print operand as a byte
-   'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
-       If this operand isn't a register, fall back to 'R' handling.
-   'Z' print int & 7.
-   'b' print the bit opcode
-   'c' print the ibit opcode
-   'd' bcc if EQ, bcs if NE
-   'e' first word of 32 bit value - if reg, then least reg. if mem
-       then least. if const then most sig word
-   'f' second word of 32 bit value - if reg, then biggest reg. if mem
-       then +2. if const then least sig word
-   'g' bcs if EQ, bcc if NE
-   'j' print operand as condition code.
-   'k' print operand as reverse condition code.
-   's' print as low byte of 16 bit value
-   't' print as high byte of 16 bit value
-   'w' print as low byte of 32 bit value
-   'x' print as 2nd byte of 32 bit value
-   'y' print as 3rd byte of 32 bit value
-   'z' print as msb of 32 bit value
-*/
-
-/* Return assembly language string which identifies a comparison type.  */
-
-static char *
-cond_string (code)
-     enum rtx_code code;
-{
-  switch (code)
-    {
-    case NE:
-      return "ne";
-    case EQ:
-      return "eq";
-    case GE:
-      return "ge";
-    case GT:
-      return "gt";
-    case LE:
-      return "le";
-    case LT:
-      return "lt";
-    case GEU:
-      return "hs";
-    case GTU:
-      return "hi";
-    case LEU:
-      return "ls";
-    case LTU:
-      return "lo";
-    default:
-      abort ();
-    }
-}
-
-/* Print operand X using operand code CODE to assembly language output file
-   FILE.  */
-
-void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
-{
-  /* This is used for communication between the 'P' and 'U' codes.  */
-  static char *last_p;
-
-  /* This is used for communication between codes V,W,Z and Y.  */
-  static int bitint;
-
-  switch (code)
-    {
-    case 'A':
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", h8_reg_names[REGNO (x)]);
-      else
-	goto def;
-      break;
-    case 'C':
-      fprintf (file, "#%d", INTVAL (x) - 2);
-      break;
-    case 'E':
-      switch (GET_CODE (x))
-	{
-	case REG:
-	  fprintf (file, "%sl", names_big[REGNO (x)]);
-	  break;
-	case CONST_INT:
-	  fprintf (file, "#%d", (-INTVAL (x)) & 0xff);
-	  break;
-	default:
-	  abort ();
-	}
-      break;
-    case 'F':
-      switch (GET_CODE (x))
-	{
-	case REG:
-	  fprintf (file, "%sh", names_big[REGNO (x)]);
-	  break;
-	case CONST_INT:
-	  fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8);
-	  break;
-	default:
-	  abort ();
-	}
-      break;
-    case 'G':
-      if (GET_CODE (x) != CONST_INT)
-	abort ();
-      fprintf (file, "#%d", 0xff & (-INTVAL (x)));
-      break;
-    case 'M':
-      /* For 3/-3 and 4/-4, the other 2 is handled separately.  */
-      switch (INTVAL (x))
-	{
-	case 2:
-	case 4:
-	case -2:
-	case -4:
-	  fprintf (file, "#2");
-	  break;
-	case 1:
-	case 3:
-	case -1:
-	case -3:
-	  fprintf (file, "#1");
-	  break;
-	default:
-	  abort ();
-	}
-      break;
-    case 'P':
-      if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM)
-	{
-	  last_p = "";
-	  fprintf (file, ".w");
-	}
-      else
-	{
-	  last_p = "l";
-	  fprintf (file, ".b");
-	}
-      break;
-    case 'S':
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", names_extended[REGNO (x)]);
-      else
-	goto def;
-      break;
-    case 'T':
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", names_big[REGNO (x)]);
-      else
-	goto def;
-      break;
-    case 'U':
-      fprintf (file, "%s%s", names_big[REGNO (x)], last_p);
-      break;
-    case 'V':
-      bitint = exact_log2 (INTVAL (x));
-      if (bitint == -1)
-	abort ();
-      fprintf (file, "#%d", bitint & 7);
-      break;
-    case 'W':
-      bitint = exact_log2 ((~INTVAL (x)) & 0xff);
-      if (bitint == -1)
-	abort ();
-      fprintf (file, "#%d", bitint & 7);
-      break;
-    case 'R':
-    case 'X':
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", byte_reg (x, 0));
-      else
-	goto def;
-      break;
-    case 'Y':
-      if (bitint == -1)
-	abort ();
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
-      else
-	print_operand (file, x, 'R');
-      bitint = -1;
-      break;
-    case 'Z':
-      bitint = INTVAL (x);
-      fprintf (file, "#%d", bitint & 7);
-      break;
-    case 'b':
-      switch (GET_CODE (x))
-	{
-	case IOR:
-	  fprintf (file, "bor");
-	  break;
-	case XOR:
-	  fprintf (file, "bxor");
-	  break;
-	case AND:
-	  fprintf (file, "band");
-	  break;
-	}
-      break;
-    case 'c':
-      switch (GET_CODE (x))
-	{
-	case IOR:
-	  fprintf (file, "bior");
-	  break;
-	case XOR:
-	  fprintf (file, "bixor");
-	  break;
-	case AND:
-	  fprintf (file, "biand");
-	  break;
-	}
-      break;
-    case 'd':
-      switch (GET_CODE (x))
-	{
-	case EQ:
-	  fprintf (file, "bcc");
-	  break;
-	case NE:
-	  fprintf (file, "bcs");
-	  break;
-	default:
-	  abort ();
-	}
-      break;
-    case 'e':
-      switch (GET_CODE (x))
-	{
-	case REG:
-	  if (TARGET_H8300)
-	    fprintf (file, "%s", names_big[REGNO (x)]);
-	  else
-	    fprintf (file, "%s", names_upper_extended[REGNO (x)]);
-	  break;
-	case MEM:
-	  x = adj_offsettable_operand (x, 0);
-	  print_operand (file, x, 0);
-	  break;
-	case CONST_INT:
-	  fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff));
-	  break;
-	case CONST_DOUBLE:
-	  {
-	    long val;
-	    REAL_VALUE_TYPE rv;
-	    REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-	    REAL_VALUE_TO_TARGET_SINGLE (rv, val);
-	    fprintf (file, "#%d", ((val >> 16) & 0xffff));
-	    break;
-	  }
-	default:
-	  abort ();
-	  break;
-	}
-      break;
-    case 'f':
-      switch (GET_CODE (x))
-	{
-	case REG:
-	  if (TARGET_H8300)
-	    fprintf (file, "%s", names_big[REGNO (x) + 1]);
-	  else
-	    fprintf (file, "%s", names_big[REGNO (x)]);
-	  break;
-	case MEM:
-	  x = adj_offsettable_operand (x, 2);
-	  print_operand (file, x, 0);
-	  break;
-	case CONST_INT:
-	  fprintf (file, "#%d", INTVAL (x) & 0xffff);
-	  break;
-	case CONST_DOUBLE:
-	  {
-	    long val;
-	    REAL_VALUE_TYPE rv;
-	    REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-	    REAL_VALUE_TO_TARGET_SINGLE (rv, val);
-	    fprintf (file, "#%d", (val & 0xffff));
-	    break;
-	  }
-	default:
-	  abort ();
-	}
-      break;
-    case 'g':
-      switch (GET_CODE (x))
-	{
-	case NE:
-	  fprintf (file, "bcc");
-	  break;
-	case EQ:
-	  fprintf (file, "bcs");
-	  break;
-	default:
-	  abort ();
-	}
-      break;
-    case 'j':
-      asm_fprintf (file, cond_string (GET_CODE (x)));
-      break;
-    case 'k':
-      asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x))));
-      break;
-    case 's':
-      if (GET_CODE (x) == CONST_INT)
-	fprintf (file, "#%d", (INTVAL (x)) & 0xff);
-      else
-	fprintf (file, "%s", byte_reg (x, 0));
-      break;
-    case 't':
-      if (GET_CODE (x) == CONST_INT)
-	fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
-      else
-	fprintf (file, "%s", byte_reg (x, 1));
-      break;
-    case 'u':
-      if (GET_CODE (x) != CONST_INT)
-	abort ();
-      fprintf (file, "%d", INTVAL (x));
-      break;
-    case 'w':
-      if (GET_CODE (x) == CONST_INT)
-	fprintf (file, "#%d", INTVAL (x) & 0xff);
-      else
-	fprintf (file, "%s",
-		 byte_reg (x, TARGET_H8300 ? 2 : 0));
-      break;
-    case 'x':
-      if (GET_CODE (x) == CONST_INT)
-	fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
-      else
-	fprintf (file, "%s",
-		 byte_reg (x, TARGET_H8300 ? 3 : 1));
-      break;
-    case 'y':
-      if (GET_CODE (x) == CONST_INT)
-	fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff);
-      else
-	fprintf (file, "%s", byte_reg (x, 0));
-      break;
-    case 'z':
-      if (GET_CODE (x) == CONST_INT)
-	fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff);
-      else
-	fprintf (file, "%s", byte_reg (x, 1));
-      break;
-
-    default:
-    def:
-      switch (GET_CODE (x))
-	{
-	case REG:
-	  switch (GET_MODE (x))
-	    {
-	    case QImode:
-#if 0 /* Is it asm ("mov.b %0,r2l", ...) */
-	      fprintf (file, "%s", byte_reg (x, 0));
-#else /* ... or is it asm ("mov.b %0l,r2l", ...) */
-	      fprintf (file, "%s", names_big[REGNO (x)]);
-#endif
-	      break;
-	    case HImode:
-	      fprintf (file, "%s", names_big[REGNO (x)]);
-	      break;
-	    case SImode:
-	    case SFmode:
-	      fprintf (file, "%s", names_extended[REGNO (x)]);
-	      break;
-	    default:
-	      abort ();
-	    }
-	  break;
-
-	case MEM:
-	  fprintf (file, "@");
-	  output_address (XEXP (x, 0));
-
-	  /* If this is an 'R' operand (reference into the 8-bit area),
-	     then specify a symbolic address as "foo:8".  */
- 	  if (code == 'R'
-	      && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
-	      && SYMBOL_REF_FLAG (XEXP (x, 0)))
-	    fprintf (file, ":8");
-	  if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
-	      && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0)))
-	    fprintf (file, ":16");
-	  break;
-
-	case CONST_INT:
-	case SYMBOL_REF:
-	case CONST:
-	case LABEL_REF:
-	  fprintf (file, "#");
-	  print_operand_address (file, x);
-	  break;
-	case CONST_DOUBLE:
-	  {
-	    long val;
-	    REAL_VALUE_TYPE rv;
-	    REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-	    REAL_VALUE_TO_TARGET_SINGLE (rv, val);
-	    fprintf (file, "#%d", val);
-	    break;
-	  }
-	}
-    }
-}
-
-/* Output assembly language output for the address ADDR to FILE.  */
-
-void
-print_operand_address (file, addr)
-     FILE *file;
-     rtx addr;
-{
-  switch (GET_CODE (addr))
-    {
-    case REG:
-      fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
-      break;
-
-    case PRE_DEC:
-      fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case POST_INC:
-      fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case PLUS:
-      fprintf (file, "(");
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-	{
-	  /* reg,foo */
-	  print_operand_address (file, XEXP (addr, 1));
-	  fprintf (file, ",");
-	  print_operand_address (file, XEXP (addr, 0));
-	}
-      else
-	{
-	  /* foo+k */
-	  print_operand_address (file, XEXP (addr, 0));
-	  fprintf (file, "+");
-	  print_operand_address (file, XEXP (addr, 1));
-	}
-      fprintf (file, ")");
-      break;
-
-    case CONST_INT:
-      {
-	/* Since the h8/300 only has 16 bit pointers, negative values are also
-	   those >= 32768.  This happens for example with pointer minus a
-	   constant.  We don't want to turn (char *p - 2) into
-	   (char *p + 65534) because loop unrolling can build upon this
-	   (IE: char *p + 131068).  */
-	int n = INTVAL (addr);
-	if (TARGET_H8300)
-	  n = (int) (short) n;
-	if (n < 0)
-	  /* ??? Why the special case for -ve values? */
-	  fprintf (file, "-%d", -n);
-	else
-	  fprintf (file, "%d", n);
-	break;
-      }
-
-    default:
-      output_addr_const (file, addr);
-      break;
-    }
-}
-
-/* Output all insn addresses and their sizes into the assembly language
-   output file.  This is helpful for debugging whether the length attributes
-   in the md file are correct.  This is not meant to be a user selectable
-   option.  */
-
-void
-final_prescan_insn (insn, operand, num_operands)
-     rtx insn, *operand;
-     int num_operands;
-{
-  /* This holds the last insn address.  */
-  static int last_insn_address = 0;
-
-  int uid = INSN_UID (insn);
-
-  if (TARGET_RTL_DUMP)
-    {
-      fprintf (asm_out_file, "\n****************");
-      print_rtl (asm_out_file, PATTERN (insn));
-      fprintf (asm_out_file, "\n");
-    }
-
-  if (TARGET_ADDRESSES)
-    {
-      fprintf (asm_out_file, "; 0x%x %d\n", insn_addresses[uid],
-	       insn_addresses[uid] - last_insn_address);
-      last_insn_address = insn_addresses[uid];
-    }
-}
-
-/* Prepare for an SI sized move.  */
-
-int
-do_movsi (operands)
-     rtx operands[];
-{
-  rtx src = operands[1];
-  rtx dst = operands[0];
-  if (!reload_in_progress && !reload_completed)
-    {
-      if (!register_operand (dst, GET_MODE (dst)))
-	{
-	  rtx tmp = gen_reg_rtx (GET_MODE (dst));
-	  emit_move_insn (tmp, src);
-	  operands[1] = tmp;
-	}
-    }
-  return 0;
-}
-
-/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
-   Define the offset between two registers, one to be eliminated, and the other
-   its replacement, at the start of a routine.  */
-
-int
-initial_offset (from, to)
-{
-  int offset = 0;
-
-  if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
-    offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
-  else
-    {
-      int regno;
-
-      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-	if (WORD_REG_USED (regno))
-	  offset += UNITS_PER_WORD;
-
-      /* See the comments for get_frame_size.  We need to round it up to
-	 STACK_BOUNDARY.  */
-
-      offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1)
-		 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
-
-      if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
-	offset += UNITS_PER_WORD;	/* Skip saved PC */
-    }
-  return offset;
-}
-
-/* Update the condition code from the insn.  */
-
-int
-notice_update_cc (body, insn)
-     rtx body;
-     rtx insn;
-{
-  switch (get_attr_cc (insn))
-    {
-    case CC_NONE:
-      /* Insn does not affect CC at all.  */
-      break;
-
-    case CC_NONE_0HIT:
-      /* Insn does not change CC, but the 0'th operand has been changed.  */
-      if (cc_status.value1 != 0
-	  && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1))
-	cc_status.value1 = 0;
-      break;
-
-    case CC_SET_ZN:
-      /* Insn sets the Z,N flags of CC to recog_operand[0].
-	 The V flag is unusable.  The C flag may or may not be known but
-	 that's ok because alter_cond will change tests to use EQ/NE.  */
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
-      cc_status.value1 = recog_operand[0];
-      break;
-
-    case CC_SET_ZNV:
-      /* Insn sets the Z,N,V flags of CC to recog_operand[0].
-	 The C flag may or may not be known but that's ok because
-	 alter_cond will change tests to use EQ/NE.  */
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_NO_CARRY;
-      cc_status.value1 = recog_operand[0];
-      break;
-
-    case CC_COMPARE:
-      /* The insn is a compare instruction.  */
-      CC_STATUS_INIT;
-      cc_status.value1 = SET_SRC (body);
-      break;
-
-    case CC_CLOBBER:
-      /* Insn doesn't leave CC in a usable state.  */
-      CC_STATUS_INIT;
-      break;
-    }
-}
-
-/* Recognize valid operators for bit instructions */
-
-int
-bit_operator (x, mode)
-     rtx x;
-     enum machine_mode mode;
-{
-  enum rtx_code code = GET_CODE (x);
-
-  return (code == XOR
-	  || code == AND
-	  || code == IOR);
-}
-
-/* Shifts.
-
-   We devote a fair bit of code to getting efficient shifts since we can only
-   shift one bit at a time on the H8/300 and H8/300H and only one or two
-   bits at a time on the H8/S.
-
-   The basic shift methods:
-
-     * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
-     this is the default.  SHIFT_LOOP
-
-     * inlined shifts -- emit straight line code for the shift; this is
-     used when a straight line shift is about the same size or smaller
-     than a loop.  We allow the inline version to be slightly longer in
-     some cases as it saves a register.  SHIFT_INLINE
-
-     * rotate + and -- rotate the value the opposite direction, then
-     mask off the values we don't need.  This is used when only a few
-     of the bits in the original value will survive in the shifted value.
-     Again, this is used when it's about the same size or smaller than
-     a loop.  We allow this version to be slightly longer as it is usually
-     much faster than a loop.  SHIFT_ROT_AND
-
-     * swap (+ shifts) -- often it's possible to swap bytes/words to
-     simulate a shift by 8/16.  Once swapped a few inline shifts can be
-     added if the shift count is slightly more than 8 or 16.  This is used
-     when it's about the same size or smaller than a loop.  We allow this
-     version to be slightly longer as it is usually much faster than a loop.
-     SHIFT_SPECIAL
-
-     * There other oddballs.  Not worth explaining.  SHIFT_SPECIAL
-
-
-   Here are some thoughts on what the absolutely positively best code is.
-   "Best" here means some rational trade-off between code size and speed,
-   where speed is more preferred but not at the expense of generating 20 insns.
-
-   A trailing '*' after the shift count indicates the "best" mode isn't
-   implemented.
-   
-   H8/300 QImode shifts
-   1-4    - do them inline
-   5-6    - ASHIFT | LSHIFTRT: rotate, mask off other bits
-            ASHIFTRT: loop
-   7      - ASHIFT | LSHIFTRT: rotate, mask off other bits
-            ASHIFTRT: shll, subx (propagate carry bit to all bits)
-
-   H8/300 HImode shifts
-   1-4    - do them inline
-   5-6    - loop
-   7      - shift 2nd half other way into carry.
-	    copy 1st half into 2nd half
-	    rotate 2nd half other way with carry
-	    rotate 1st half other way (no carry)
-	    mask off bits in 1st half (ASHIFT | LSHIFTRT).
-	    sign extend 1st half (ASHIFTRT)
-   8      - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
-   9-12   - do shift by 8, inline remaining shifts
-   13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
-          - ASHIFTRT: loop
-   15     - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
-          - ASHIFTRT: shll, subx, set other byte
-
-   H8/300 SImode shifts
-   1-2    - do them inline
-   3-6    - loop
-   7*     - shift other way once, move bytes into place,
-            move carry into place (possibly with sign extension)
-   8      - move bytes into place, zero or sign extend other
-   9-14   - loop
-   15*    - shift other way once, move word into place, move carry into place
-   16     - move word, zero or sign extend other
-   17-23  - loop
-   24*    - move bytes into place, zero or sign extend other
-   25-27  - loop
-   28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
-                               zero others
-            ASHIFTRT: loop
-   31     - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
-                               zero others
-            ASHIFTRT: shll top byte, subx, copy to other bytes
-
-   H8/300H QImode shifts (same as H8/300 QImode shifts)
-   1-4    - do them inline
-   5-6    - ASHIFT | LSHIFTRT: rotate, mask off other bits
-            ASHIFTRT: loop
-   7      - ASHIFT | LSHIFTRT: rotate, mask off other bits
-            ASHIFTRT: shll, subx (propagate carry bit to all bits)
-
-
-   H8/300H HImode shifts
-   1-4    - do them inline
-   5-6    - loop
-   7      - shift 2nd half other way into carry.
-	    copy 1st half into 2nd half
-	    rotate entire word other way using carry
-	    mask off remaining bits  (ASHIFT | LSHIFTRT)
-	    sign extend remaining bits (ASHIFTRT)
-   8      - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
-   9-12   - do shift by 8, inline remaining shifts
-   13-14  - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
-          - ASHIFTRT: loop
-   15     - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
-          - ASHIFTRT: shll, subx, set other byte
-
-   H8/300H SImode shifts
-   (These are complicated by the fact that we don't have byte level access to
-   the top word.)
-   A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
-   1-4    - do them inline
-   5-14   - loop
-   15*    - shift other way once, move word into place, move carry into place
-            (with sign extension for ASHIFTRT)
-   16     - move word into place, zero or sign extend other
-   17-20  - do 16bit shift, then inline remaining shifts
-   20-23  - loop
-   24*    - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
-                    move word 0 to word 1, zero word 0
-            LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
-                      zero word 1, zero byte 1
-            ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
-                      sign extend byte 0, sign extend word 0
-   25-27* - either loop, or
-            do 24 bit shift, inline rest
-   28-30  - ASHIFT: rotate 4/3/2, mask
-            LSHIFTRT: rotate 4/3/2, mask
-            ASHIFTRT: loop
-   31     - shll, subx byte 0, sign extend byte 0, sign extend word 0
-
-   H8/S QImode shifts
-   1-6    - do them inline
-   7      - ASHIFT | LSHIFTRT: rotate, mask off other bits
-            ASHIFTRT: shll, subx (propagate carry bit to all bits)
-
-   H8/S HImode shifts
-   1-7	  - do them inline
-   8      - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
-   9-12   - do shift by 8, inline remaining shifts
-   13-14  - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
-          - ASHIFTRT: loop
-   15     - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
-          - ASHIFTRT: shll, subx, set other byte
-
-   H8/S SImode shifts
-   (These are complicated by the fact that we don't have byte level access to
-   the top word.)
-   A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
-   1-10   - do them inline
-   11-14  - loop
-   15*    - shift other way once, move word into place, move carry into place
-            (with sign extension for ASHIFTRT)
-   16     - move word into place, zero or sign extend other
-   17-20  - do 16bit shift, then inline remaining shifts
-   20-23  - loop
-   24*    - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
-                    move word 0 to word 1, zero word 0
-            LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
-                      zero word 1, zero byte 1
-            ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
-                      sign extend byte 0, sign extend word 0
-   25-27* - either loop, or
-            do 24 bit shift, inline rest
-   28-30  - ASHIFT: rotate 4/3/2, mask
-            LSHIFTRT: rotate 4/3/2, mask
-            ASHIFTRT: loop
-   31     - shll, subx byte 0, sign extend byte 0, sign extend word 0
-
-   Panic!!!  */
-
-int
-nshift_operator (x, mode)
-     rtx x;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (x))
-    {
-    case ASHIFTRT:
-    case LSHIFTRT:
-    case ASHIFT:
-      return 1;
-
-    default:
-      return 0;
-    }
-}
-
-/* Called from the .md file to emit code to do shifts.
-   Returns a boolean indicating success
-   (currently this is always TRUE).  */
-
-int
-expand_a_shift (mode, code, operands)
-     enum machine_mode mode;
-     int code;
-     rtx operands[];
-{
-  emit_move_insn (operands[0], operands[1]);
-
-  /* need a loop to get all the bits we want  - we generate the
-     code at emit time, but need to allocate a scratch reg now  */
-
-  emit_insn (gen_rtx
-	     (PARALLEL, VOIDmode,
-	      gen_rtvec (2,
-			 gen_rtx (SET, VOIDmode, operands[0],
-				  gen_rtx (code, mode, operands[0], operands[2])),
-			 gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, QImode, 0)))));
-
-  return 1;
-}
-
-/* Shift algorithm determination.
-
-   There are various ways of doing a shift:
-   SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
-                 shifts as we need.
-   SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
-                  necessary bits into position and then set the rest to zero.
-   SHIFT_SPECIAL: Hand crafted assembler.
-   SHIFT_LOOP:    If the above methods fail, just loop.  */
-
-enum shift_alg
-{
-  SHIFT_INLINE,
-  SHIFT_ROT_AND,
-  SHIFT_SPECIAL,
-  SHIFT_LOOP,
-  SHIFT_MAX
-};
-
-/* Symbols of the various shifts which can be used as indices.  */
-
-enum shift_type
-  {
-    SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
-  };
-
-/* Symbols of the various modes which can be used as indices.  */
-
-enum shift_mode
-  {
-    QIshift, HIshift, SIshift
-  };
-
-/* For single bit shift insns, record assembler and what bits of the
-   condition code are valid afterwards (represented as various CC_FOO
-   bits, 0 means CC isn't left in a usable state).  */
-
-struct shift_insn
-{
-  char *assembler;
-  int cc_valid;
-};
-
-/* Assembler instruction shift table.
-
-   These tables are used to look up the basic shifts.
-   They are indexed by cpu, shift_type, and mode.
-*/
-
-static const struct shift_insn shift_one[2][3][3] =
-{
-/* H8/300 */
-  {
-/* SHIFT_ASHIFT */
-    {
-      { "shll\t%X0", CC_NO_CARRY },
-      { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
-      { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
-    },
-/* SHIFT_LSHIFTRT */
-    {
-      { "shlr\t%X0", CC_NO_CARRY },
-      { "shlr\t%t0\n\trotxr\t%s0", 0 },
-      { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
-    },
-/* SHIFT_ASHIFTRT */
-    {
-      { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
-      { "shar\t%t0\n\trotxr\t%s0", 0 },
-      { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
-    }
-  },
-/* H8/300H */
-  {
-/* SHIFT_ASHIFT */
-    {
-      { "shll.b\t%X0", CC_NO_CARRY },
-      { "shll.w\t%T0", CC_NO_CARRY },
-      { "shll.l\t%S0", CC_NO_CARRY }
-    },
-/* SHIFT_LSHIFTRT */
-    {
-      { "shlr.b\t%X0", CC_NO_CARRY },
-      { "shlr.w\t%T0", CC_NO_CARRY },
-      { "shlr.l\t%S0", CC_NO_CARRY }
-    },
-/* SHIFT_ASHIFTRT */
-    {
-      { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
-      { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
-      { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
-    }
-  }
-};
-
-static const struct shift_insn shift_two[3][3] =
-{
-/* SHIFT_ASHIFT */
-    {
-      { "shll.b\t#2,%X0", CC_NO_CARRY },
-      { "shll.w\t#2,%T0", CC_NO_CARRY },
-      { "shll.l\t#2,%S0", CC_NO_CARRY }
-    },
-/* SHIFT_LSHIFTRT */
-    {
-      { "shlr.b\t#2,%X0", CC_NO_CARRY },
-      { "shlr.w\t#2,%T0", CC_NO_CARRY },
-      { "shlr.l\t#2,%S0", CC_NO_CARRY }
-    },
-/* SHIFT_ASHIFTRT */
-    {
-      { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
-      { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
-      { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
-    }
-};
-
-/* Rotates are organized by which shift they'll be used in implementing.
-   There's no need to record whether the cc is valid afterwards because
-   it is the AND insn that will decide this.  */
-
-static const char *const rotate_one[2][3][3] =
-{
-/* H8/300 */
-  {
-/* SHIFT_ASHIFT */
-    {
-      "rotr\t%X0",
-      "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
-      0
-    },
-/* SHIFT_LSHIFTRT */
-    {
-      "rotl\t%X0",
-      "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
-      0
-    },
-/* SHIFT_ASHIFTRT */
-    {
-      "rotl\t%X0",
-      "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
-      0
-    }
-  },
-/* H8/300H */
-  {
-/* SHIFT_ASHIFT */
-    {
-      "rotr.b\t%X0",
-      "rotr.w\t%T0",
-      "rotr.l\t%S0"
-    },
-/* SHIFT_LSHIFTRT */
-    {
-      "rotl.b\t%X0",
-      "rotl.w\t%T0",
-      "rotl.l\t%S0"
-    },
-/* SHIFT_ASHIFTRT */
-    {
-      "rotl.b\t%X0",
-      "rotl.w\t%T0",
-      "rotl.l\t%S0"
-    }
-  }
-};
-
-static const char *const rotate_two[3][3] =
-{
-/* SHIFT_ASHIFT */
-    {
-      "rotr.b\t#2,%X0",
-      "rotr.w\t#2,%T0",
-      "rotr.l\t#2,%S0"
-    },
-/* SHIFT_LSHIFTRT */
-    {
-      "rotl.b\t#2,%X0",
-      "rotl.w\t#2,%T0",
-      "rotl.l\t#2,%S0"
-    },
-/* SHIFT_ASHIFTRT */
-    {
-      "rotl.b\t#2,%X0",
-      "rotl.w\t#2,%T0",
-      "rotl.l\t#2,%S0"
-    }
-};
-
-/* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
-   algorithm for doing the shift.  The assembler code is stored in ASSEMBLER.
-   We don't achieve maximum efficiency in all cases, but the hooks are here
-   to do so.
-
-   For now we just use lots of switch statements.  Since we don't even come
-   close to supporting all the cases, this is simplest.  If this function ever
-   gets too big, perhaps resort to a more table based lookup.  Of course,
-   at this point you may just wish to do it all in rtl.
-
-   WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
-   1,2,3,4 will be inlined (1,2 for SI).  */
-
-static enum shift_alg
-get_shift_alg (cpu, shift_type, mode, count, assembler_p,
-	       assembler2_p, cc_valid_p)
-     enum attr_cpu cpu;
-     enum shift_type shift_type;
-     enum machine_mode mode;
-     int count;
-     const char **assembler_p;
-     const char **assembler2_p;
-     int *cc_valid_p;
-{
-  /* The default is to loop.  */
-  enum shift_alg alg = SHIFT_LOOP;
-  enum shift_mode shift_mode;
-
-  /* We don't handle negative shifts or shifts greater than the word size,
-     they should have been handled already.  */
-
-  if (count < 0 || count > GET_MODE_BITSIZE (mode))
-    abort ();
-
-  switch (mode)
-    {
-    case QImode:
-      shift_mode = QIshift;
-      break;
-    case HImode:
-      shift_mode = HIshift;
-      break;
-    case SImode:
-      shift_mode = SIshift;
-      break;
-    default:
-      abort ();
-    }
-
-  /* Assume either SHIFT_LOOP or SHIFT_INLINE.
-     It is up to the caller to know that looping clobbers cc.  */
-  *assembler_p = shift_one[cpu][shift_type][shift_mode].assembler;
-  if (TARGET_H8300S)
-    *assembler2_p = shift_two[shift_type][shift_mode].assembler;
-  else
-    *assembler2_p = NULL;
-  *cc_valid_p = shift_one[cpu][shift_type][shift_mode].cc_valid;
-
-  /* Now look for cases we want to optimize.  */
-
-  switch (shift_mode)
-    {
-    case QIshift:
-      if (count <= 4)
-	return SHIFT_INLINE;
-      else
-	{
-	  /* Shift by 5/6 are only 3 insns on the H8/S, so it's just as
-	     fast as SHIFT_ROT_AND, plus CC is valid.  */
-	  if (TARGET_H8300S && count <= 6)
-	    return SHIFT_INLINE;
-
-	  /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
-	     through the entire value.  */
-	  if (shift_type == SHIFT_ASHIFTRT && count == 7)
-	    {
-	      *assembler_p = "shll\t%X0\n\tsubx\t%X0,%X0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-
-	  /* Other ASHIFTRTs are too much of a pain.  */
-	  if (shift_type == SHIFT_ASHIFTRT)
-	    return SHIFT_LOOP;
-
-	  /* Other shifts by 5, 6, or 7 bits use SHIFT_ROT_AND.  */
-	  *assembler_p = rotate_one[cpu][shift_type][shift_mode];
-	  if (TARGET_H8300S)
-	    *assembler2_p = rotate_two[shift_type][shift_mode];
-	  *cc_valid_p = 0;
-	  return SHIFT_ROT_AND;
-	}
-
-    case HIshift:
-      if (count <= 4)
-	return SHIFT_INLINE;
-      else if (TARGET_H8300S && count <= 7)
-	return SHIFT_INLINE;
-      else if (count == 7)
-	{
-	  if (shift_type == SHIFT_ASHIFT && TARGET_H8300)
-	    {
-	      *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-
-	  if (shift_type == SHIFT_ASHIFT && TARGET_H8300H)
-	    {
-	      *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-
-	  if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300)
-	    {
-	      *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-
-	  if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300H)
-	    {
-	      *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-
-	  if (shift_type == SHIFT_ASHIFTRT)
-	    {
-	      *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 8)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      if (TARGET_H8300)
-		*assembler_p = "mov.b\t%t0,%s0\n\tshll\t%t0\n\tsubx\t%t0,%t0\t";
-	      else
-		*assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 9)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      if (TARGET_H8300)
-		*assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0";
-	      else
-		*assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 10)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      if (TARGET_H8300S)
-		*assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\t";
-	      else
-		*assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      if (TARGET_H8300S)
-		*assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0";
-	      else
-		*assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      if (TARGET_H8300)
-		*assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0";
-	      else if (TARGET_H8300H)
-		*assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0";
-	      else if (TARGET_H8300S)
-		*assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 11)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      if (TARGET_H8300S)
-		*assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t%t0";
-	      else
-		*assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      if (TARGET_H8300S)
-		*assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t%s0";
-	      else
-		*assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      if (TARGET_H8300)
-		*assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
-	      else if (TARGET_H8300H)
-		*assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
-	      else if (TARGET_H8300S)
-		*assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t%s0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 12)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      if (TARGET_H8300S)
-		*assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t#2,%t0";
-	      else
-		*assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      if (TARGET_H8300S)
-		*assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t#2,%s0";
-	      else
-		*assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      if (TARGET_H8300)
-		*assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
-	      else if (TARGET_H8300H)
-		*assembler_p = "mov.b\t%t0,%s0\n\textw.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
-	      else if (TARGET_H8300S)
-		*assembler_p = "mov.b\t%t0,%s0\n\textw.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t#2,%s0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (!TARGET_H8300 && (count == 13 || count == 14)
-	       || count == 15)
-	{
-	  if (count == 15 && shift_type == SHIFT_ASHIFTRT)
-	    {
-	      *assembler_p = "shll\t%t0,%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	  else if (shift_type != SHIFT_ASHIFTRT)
-	    {
-	      *assembler_p = rotate_one[cpu][shift_type][shift_mode];
-	      if (TARGET_H8300S)
-	        *assembler2_p = rotate_two[shift_type][shift_mode];
-	      else
-		*assembler2_p = NULL;
-	      *cc_valid_p = 0;
-	      return SHIFT_ROT_AND;
-	    }
-	}
-      break;
-
-    case SIshift:
-      if (count <= (TARGET_H8300 ? 2 : 4))
-	return SHIFT_INLINE;
-      else if (TARGET_H8300S && count <= 10)
-	return SHIFT_INLINE;
-      else if (count == 8 && TARGET_H8300)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      *assembler_p = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 8 && !TARGET_H8300)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 16)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      if (TARGET_H8300)
-		*assembler_p = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
-	      else
-		*assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 17 && !TARGET_H8300)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 18 && !TARGET_H8300)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      if (TARGET_H8300S)
-		*assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0";
-	      else
-		*assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      if (TARGET_H8300S)
-		*assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0";
-	      else
-		*assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      if (TARGET_H8300S)
-		*assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0";
-	      else
-		*assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 19 && !TARGET_H8300)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      if (TARGET_H8300S)
-		*assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t%S0";
-	      else
-		*assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0\n\tshll.l\t%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      if (TARGET_H8300S)
-		*assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t%S0";
-	      else
-		*assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      if (TARGET_H8300S)
-		*assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t%S0";
-	      else
-		*assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 20 && TARGET_H8300S)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t#2,%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t#2,%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t#2,%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 24 && !TARGET_H8300)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_LSHIFTRT:
-	      *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    case SHIFT_ASHIFTRT:
-	      *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count >= 28 && count <= 30 && !TARGET_H8300)
-	{
-	  if (shift_type == SHIFT_ASHIFTRT)
-	    {
-	      return SHIFT_LOOP;
-	    }
-	  else
-	    {
-	      *assembler_p = rotate_one[cpu][shift_type][shift_mode];
-	      if (TARGET_H8300S)
-	        *assembler2_p = rotate_two[shift_type][shift_mode];
-	      else
-		*assembler2_p = NULL;
-	      *cc_valid_p = 0;
-	      return SHIFT_ROT_AND;
-	    }
-	}
-      else if (count == 31)
-	{
-	  if (shift_type == SHIFT_ASHIFTRT)
-	    {
-	      if (TARGET_H8300)
-		*assembler_p = "shll\t%z0\n\tsubx %w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
-	      else
-		*assembler_p = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
-	      *cc_valid_p = 0;
-	      return SHIFT_SPECIAL;
-	    }
-	  else
-	    {
-	      if (TARGET_H8300)
-		{
-		  if (shift_type == SHIFT_ASHIFT)
-		    *assembler_p = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
-		  else
-		    *assembler_p = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
-		  *cc_valid_p = 0;
-		  return SHIFT_SPECIAL;
-		}
-	      else
-		{
-		  *assembler_p = rotate_one[cpu][shift_type][shift_mode];
-	      if (TARGET_H8300S)
-	        *assembler2_p = rotate_two[shift_type][shift_mode];
-	      else
-		*assembler2_p = NULL;
-		  *cc_valid_p = 0;
-		  return SHIFT_ROT_AND;
-		}
-	    }
-	}
-      break;
-
-    default:
-      abort ();
-    }
-
-  return alg;
-}
-
-/* Emit the assembler code for doing shifts.  */
-
-char *
-emit_a_shift (insn, operands)
-     rtx insn;
-     rtx *operands;
-{
-  static int loopend_lab;
-  char *assembler;
-  char *assembler2;
-  int cc_valid;
-  rtx inside = PATTERN (insn);
-  rtx shift = operands[3];
-  enum machine_mode mode = GET_MODE (shift);
-  enum rtx_code code = GET_CODE (shift);
-  enum shift_type shift_type;
-  enum shift_mode shift_mode;
-
-  loopend_lab++;
-
-  switch (mode)
-    {
-    case QImode:
-      shift_mode = QIshift;
-      break;
-    case HImode:
-      shift_mode = HIshift;
-      break;
-    case SImode:
-      shift_mode = SIshift;
-      break;
-    default:
-      abort ();
-    }
-
-  switch (code)
-    {
-    case ASHIFTRT:
-      shift_type = SHIFT_ASHIFTRT;
-      break;
-    case LSHIFTRT:
-      shift_type = SHIFT_LSHIFTRT;
-      break;
-    case ASHIFT:
-      shift_type = SHIFT_ASHIFT;
-      break;
-    default:
-      abort ();
-    }
-
-  if (GET_CODE (operands[2]) != CONST_INT)
-    {
-      /* Indexing by reg, so have to loop and test at top */
-      output_asm_insn ("mov.b	%X2,%X4", operands);
-      fprintf (asm_out_file, "\tble	.Lle%d\n", loopend_lab);
-
-      /* Get the assembler code to do one shift.  */
-      get_shift_alg (cpu_type, shift_type, mode, 1, &assembler,
-		     &assembler2, &cc_valid);
-    }
-  else
-    {
-      int n = INTVAL (operands[2]);
-      enum shift_alg alg;
-
-      /* If the count is negative, make it 0.  */
-      if (n < 0)
-	n = 0;
-      /* If the count is too big, truncate it.
-         ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
-	 do the intuitive thing.  */
-      else if (n > GET_MODE_BITSIZE (mode))
-	n = GET_MODE_BITSIZE (mode);
-
-      alg = get_shift_alg (cpu_type, shift_type, mode, n, &assembler,
-			   &assembler2, &cc_valid);
-
-      switch (alg)
-	{
-	case SHIFT_INLINE:
-	  /* Emit two bit shifts first.  */
-	  while (n > 1 && assembler2 != NULL)
-	    {
-	      output_asm_insn (assembler2, operands);
-	      n -= 2;
-	    }
-
-	  /* Now emit one bit shifts for any residual.  */
-	  while (n > 0)
-	    {
-	      output_asm_insn (assembler, operands);
-	      n -= 1;
-	    }
-
-	  /* Keep track of CC.  */
-	  if (cc_valid)
-	    {
-	      cc_status.value1 = operands[0];
-	      cc_status.flags |= cc_valid;
-	    }
-	  return "";
-
-	case SHIFT_ROT_AND:
-	  {
-	    int m = GET_MODE_BITSIZE (mode) - n;
-	    int mask = (shift_type == SHIFT_ASHIFT
-			? ((1 << GET_MODE_BITSIZE (mode) - n) - 1) << n
-			: (1 << GET_MODE_BITSIZE (mode) - n) - 1);
-	    char insn_buf[200];
-	    /* Not all possibilities of rotate are supported.  They shouldn't
-	       be generated, but let's watch for 'em.  */
-	    if (assembler == 0)
-	      abort ();
-
-	    /* Emit two bit rotates first.  */
-	    while (m > 1 && assembler2 != NULL)
-	      {
-		output_asm_insn (assembler2, operands);
-		m -= 2;
-	      }
-
-	    /* Now single bit rotates for any residual.  */
-	    while (m > 0)
-	      {
-		output_asm_insn (assembler, operands);
-		m -= 1;
-	      }
-
-	    /* Now mask off the high bits.  */
-	    if (TARGET_H8300)
-	      {
-		switch (mode)
-		  {
-		  case QImode:
-		    sprintf (insn_buf, "and #%d,%%X0",
-			     mask, n);
-		    cc_status.value1 = operands[0];
-		    cc_status.flags |= CC_NO_CARRY;
-		    break;
-		  case HImode:
-		    sprintf (insn_buf, "and #%d,%%s0\n\tand #%d,%%t0",
-			     mask & 255, mask >> 8, n);
-		    break;
-		  case SImode:
-		    abort ();
-		  }
-	      }
-	    else
-	      {
-		sprintf (insn_buf, "and.%c #%d,%%%c0",
-			 "bwl"[shift_mode], mask,
-			 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
-		cc_status.value1 = operands[0];
-		cc_status.flags |= CC_NO_CARRY;
-	      }
-	    output_asm_insn (insn_buf, operands);
-	    return "";
-	  }
-	case SHIFT_SPECIAL:
-	  output_asm_insn (assembler, operands);
-	  return "";
-	}
-
-      /* A loop to shift by a "large" constant value.
-	 If we have shift-by-2 insns, use them.  */
-      if (assembler2 != NULL)
-	{
-	  fprintf (asm_out_file, "\tmov.b	#%d,%sl\n", n / 2,
-		   names_big[REGNO (operands[4])]);
-	  fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
-	  output_asm_insn (assembler2, operands);
-	  output_asm_insn ("add	#0xff,%X4", operands);
-	  fprintf (asm_out_file, "\tbne	.Llt%d\n", loopend_lab);
-	  if (n % 2)
-	    output_asm_insn (assembler, operands);
-	  return "";
-	}
-      else
-	{
-	  fprintf (asm_out_file, "\tmov.b	#%d,%sl\n", n,
-		   names_big[REGNO (operands[4])]);
-	  fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
-	  output_asm_insn (assembler, operands);
-	  output_asm_insn ("add	#0xff,%X4", operands);
-	  fprintf (asm_out_file, "\tbne	.Llt%d\n", loopend_lab);
-	  return "";
-	}
-    }
-
-  fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
-  output_asm_insn (assembler, operands);
-  output_asm_insn ("add	#0xff,%X4", operands);
-  fprintf (asm_out_file, "\tbne	.Llt%d\n", loopend_lab);
-  fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
-
-  return "";
-}
-
-/* Fix the operands of a gen_xxx so that it could become a bit
-  operating insn.  */
-
-int
-fix_bit_operand (operands, what, type)
-     rtx *operands;
-     char what;
-     enum rtx_code type;
-{
-  /* The bit_operand predicate accepts any memory during RTL generation, but
-     only 'U' memory afterwards, so if this is a MEM operand, we must force
-     it to be valid for 'U' by reloading the address.  */
-
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what))
-	{
-	  /* Ok to have a memory dest.  */
-	  if (GET_CODE (operands[0]) == MEM && !EXTRA_CONSTRAINT (operands[0], 'U'))
-	    {
-	      rtx mem;
-	      mem = gen_rtx (MEM, GET_MODE (operands[0]),
-			   copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
-	      RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[0]);
-	      MEM_COPY_ATTRIBUTES (mem, operands[0]);
-	      operands[0] = mem;
-	    }
-
-	  if (GET_CODE (operands[1]) == MEM && !EXTRA_CONSTRAINT (operands[1], 'U'))
-	    {
-	      rtx mem;
-	      mem = gen_rtx (MEM, GET_MODE (operands[1]),
-			   copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
-	      RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[1]);
-	      MEM_COPY_ATTRIBUTES (mem, operands[0]);
-	      operands[1] = mem;
-	    }
-	  return 0;
-	}
-    }
-
-  /* Dest and src op must be register.  */
-
-  operands[1] = force_reg (QImode, operands[1]);
-  {
-    rtx res = gen_reg_rtx (QImode);
-    emit_insn (gen_rtx (SET, VOIDmode, res, gen_rtx (type, QImode, operands[1], operands[2])));
-    emit_insn (gen_rtx (SET, VOIDmode, operands[0], res));
-  }
-  return 1;
-}
-
-/* Return nonzero if FUNC is an interrupt function as specified
-   by the "interrupt" attribute.  */
-
-static int
-h8300_interrupt_function_p (func)
-     tree func;
-{
-  tree a;
-
-  if (TREE_CODE (func) != FUNCTION_DECL)
-    return 0;
-
-  a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func));
-  return a != NULL_TREE;
-}
-
-/* Return nonzero if FUNC is an OS_Task function as specified
-   by the "OS_Task" attribute.  */
-
-static int
-h8300_os_task_function_p (func)
-     tree func;
-{
-  tree a;
-
-  if (TREE_CODE (func) != FUNCTION_DECL)
-    return 0;
-
-  a = lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func));
-  return a != NULL_TREE;
-}
-
-/* Return nonzero if FUNC is a monitor function as specified
-   by the "monitor" attribute.  */
-
-static int
-h8300_monitor_function_p (func)
-     tree func;
-{
-  tree a;
-
-  if (TREE_CODE (func) != FUNCTION_DECL)
-    return 0;
-
-  a = lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func));
-  return a != NULL_TREE;
-}
-
-/* Return nonzero if FUNC is a function that should be called
-   through the function vector.  */
-
-int
-h8300_funcvec_function_p (func)
-     tree func;
-{
-  tree a;
-
-  if (TREE_CODE (func) != FUNCTION_DECL)
-    return 0;
-
-  a = lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func));
-  return a != NULL_TREE;
-}
-
-/* Return nonzero if DECL is a variable that's in the eight bit
-   data area.  */
-
-int
-h8300_eightbit_data_p (decl)
-     tree decl;
-{
-  tree a;
-
-  if (TREE_CODE (decl) != VAR_DECL)
-    return 0;
-
-  a = lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl));
-  return a != NULL_TREE;
-}
-
-/* Return nonzero if DECL is a variable that's in the tiny
-   data area.  */
-
-int
-h8300_tiny_data_p (decl)
-     tree decl;
-{
-  tree a;
-
-  if (TREE_CODE (decl) != VAR_DECL)
-    return 0;
-
-  a = lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl));
-  return a != NULL_TREE;
-}
-
-/* Return nonzero if ATTR is a valid attribute for DECL.
-   ATTRIBUTES are any existing attributes and ARGS are the arguments
-   supplied with ATTR.
-
-   Supported attributes:
-
-   interrupt_handler: output a prologue and epilogue suitable for an
-   interrupt handler.
-
-   function_vector: This function should be called through the
-   function vector.
-
-   eightbit_data: This variable lives in the 8-bit data area and can
-   be referenced with 8-bit absolute memory addresses.
-
-   tiny_data: This variable lives in the tiny data area and can be
-   referenced with 16-bit absolute memory references.  */
-
-int
-h8300_valid_machine_decl_attribute (decl, attributes, attr, args)
-     tree decl;
-     tree attributes;
-     tree attr;
-     tree args;
-{
-  if (args != NULL_TREE)
-    return 0;
-
-  if (is_attribute_p ("interrupt_handler", attr)
-      || is_attribute_p ("OS_Task", attr)
-      || is_attribute_p ("monitor", attr)
-      || is_attribute_p ("function_vector", attr))
-    return TREE_CODE (decl) == FUNCTION_DECL;
-
-  if (is_attribute_p ("eightbit_data", attr)
-      && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
-    {
-      if (DECL_INITIAL (decl) == NULL_TREE)
-	{
-	  warning ("Only initialized variables can be placed into the 8-bit area.");
-	  return 0;
-	}
-      DECL_SECTION_NAME (decl) = build_string (7, ".eight");
-      return 1;
-    }
-
-  if (is_attribute_p ("tiny_data", attr)
-      && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
-    {
-      if (DECL_INITIAL (decl) == NULL_TREE)
-	{
-	  warning ("Only initialized variables can be placed into the 8-bit area.");
-	  return 0;
-	}
-      DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
-      return 1;
-    }
-      
-  return 0;
-}
-
-extern struct obstack *saveable_obstack;
-
-h8300_encode_label (decl)
-     tree decl;
-{
-  char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
-  int len = strlen (str);
-  char *newstr;
-
-  newstr = obstack_alloc (saveable_obstack, len + 2);
-
-  strcpy (newstr + 1, str);
-  *newstr = '&';
-  XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
-}
-
-char *
-output_simode_bld (bild, log2, operands)
-     int bild;
-     int log2;
-     rtx operands[];
-{
-  /* Clear the destination register.  */
-  if (TARGET_H8300H || TARGET_H8300S)
-    output_asm_insn ("sub.l\t%S0,%S0", operands);
-  else
-    output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
-
-  /* Get the bit number we want to load.  */
-  if (log2)
-    operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
-
-  /* Now output the bit load or bit inverse load, and store it in
-     the destination.  */
-  if (bild)
-    output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
-  else
-    output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
-
-  /* All done.  */
-  return "";
-}
-
-/* Given INSN and its current length LENGTH, return the adjustment
-   (in bytes) to correctly compute INSN's length.
-
-   We use this to get the lengths of various memory references correct.  */
-
-h8300_adjust_insn_length (insn, length)
-     rtx insn;
-     int length;
-{
-  rtx pat = PATTERN (insn);
-
-  /* Adjust length for reg->mem and mem->reg copies.  */
-  if (GET_CODE (pat) == SET
-      && (GET_CODE (SET_SRC (pat)) == MEM
-	  || GET_CODE (SET_DEST (pat)) == MEM))
-    {
-      /* This insn might need a length adjustment.  */
-      rtx addr;
-
-      if (GET_CODE (SET_SRC (pat)) == MEM)
-	addr = XEXP (SET_SRC (pat), 0);
-      else
-	addr = XEXP (SET_DEST (pat), 0);
-
-      /* On the H8/300, only one adjustment is necessary; if the
-	 address mode is register indirect, then this insn is two
-	 bytes shorter than indicated in the machine description.  */
-      if (TARGET_H8300 && GET_CODE (addr) == REG)
-	return -2;
-
-      /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than
-	 indicated in the machine description.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-          && GET_CODE (addr) == REG)
-	return -6;
-
-      /* On the H8/300H and H8/300S, reg + d, for small displacements is 4
-	 bytes shorter than indicated in the machine description.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && GET_CODE (addr) == PLUS
-	  && GET_CODE (XEXP (addr, 0)) == REG
-	  && GET_CODE (XEXP (addr, 1)) == CONST_INT
-	  && INTVAL (XEXP (addr, 1)) > -32768
-	  && INTVAL (XEXP (addr, 1)) < 32767)
-	return -4;
-
-      /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the
-	 more general abs:24.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && GET_CODE (addr) == SYMBOL_REF
-	  && TINY_DATA_NAME_P (XSTR (addr, 0)))
-	return -2;
-    }
-
-  /* Loading some constants needs adjustment.  */
-  if (GET_CODE (pat) == SET
-      && GET_CODE (SET_SRC (pat)) == CONST_INT
-      && GET_MODE (SET_DEST (pat)) == SImode
-      && INTVAL (SET_SRC (pat)) != 0)
-    {
-      if (TARGET_H8300
-	  && ((INTVAL (SET_SRC (pat)) & 0xffff) == 0
-	      || ((INTVAL (SET_SRC (pat)) >> 16) & 0xffff) == 0))
-	return -2;
-
-      if (TARGET_H8300H || TARGET_H8300S)
-	{
-	  int val = INTVAL (SET_SRC (pat));
-
-	  if (val == (val & 0xff)
-	      || val == (val & 0xff00))
-	    return -6;
-
-	  if (val == -4 || val == -2 || val == -1)
-	    return -6;
-	}
-    }
-
-  /* Shifts need various adjustments.  */
-  if (GET_CODE (pat) == PARALLEL
-      && GET_CODE (XVECEXP (pat, 0, 0)) == SET
-      && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT
-          || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT
-          || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT))
-    {
-      rtx src = SET_SRC (XVECEXP (pat, 0, 0));
-      enum machine_mode mode = GET_MODE (src);
-
-      if (GET_CODE (XEXP (src, 1)) != CONST_INT)
-	return 0;
-
-      /* QImode shifts by small constants take one insn
-	 per shift.  So the adjustment is 20 (md length) -
-	 # shifts * 2.  */
-      if (mode == QImode && INTVAL (XEXP (src, 1)) <= 4)
-	return -(20 - INTVAL (XEXP (src, 1)) * 2);
-
-      /* Similarly for HImode and SImode shifts by
-	 small constants on the H8/300H and H8/300S.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && (mode == HImode || mode == SImode)
-	  && INTVAL (XEXP (src, 1)) <= 4)
-	return -(20 - INTVAL (XEXP (src, 1)) * 2);
-
-      /* HImode shifts by small constants for the H8/300.  */
-      if (mode == HImode
-	  && INTVAL (XEXP (src, 1)) <= 4)
-	return -(20 - (INTVAL (XEXP (src, 1))
-		       * (GET_CODE (src) == ASHIFT ? 2 : 4)));
-
-      /* SImode shifts by small constants for the H8/300.  */
-      if (mode == SImode
-	  && INTVAL (XEXP (src, 1)) <= 2)
-	return -(20 - (INTVAL (XEXP (src, 1))
-		       * (GET_CODE (src) == ASHIFT ? 6 : 8)));
-
-      /* XXX ??? Could check for more shift/rotate cases here.  */
-    }
-    
-  return 0;
-}
diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
deleted file mode 100755
index d8b6c36..0000000
--- a/gcc/config/h8300/h8300.h
+++ /dev/null
@@ -1,1413 +0,0 @@
-/* Definitions of target machine for GNU compiler. 
-   Hitachi H8/300 version generating coff 
-   Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Steve Chamberlain (sac@cygnus.com),
-   Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Which cpu to compile for.
-   We use int for CPU_TYPE to avoid lots of casts.  */
-#if 0 /* defined in insn-attr.h, here for documentation */
-enum attr_cpu { CPU_H8300, CPU_H8300H };
-#endif
-extern int cpu_type;
-
-/* Various globals defined in h8300.c.  */
-
-extern char *h8_push_op,*h8_pop_op,*h8_mov_op;
-extern char **h8_reg_names;
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES \
-"-D__LONG_MAX__=2147483647L -D__LONG_LONG_MAX__=2147483647L"
-
-#define CPP_SPEC \
-  "%{!mh:%{!ms:-D__H8300__}} %{mh:-D__H8300H__} %{ms:-D__H8300S__} \
-   %{!mh:%{!ms:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
-   %{mh:-D__SIZE_TYPE__=unsigned\\ long -D__PTRDIFF_TYPE__=long} \
-   %{ms:-D__SIZE_TYPE__=unsigned\\ long -D__PTRDIFF_TYPE__=long} \
-   %{!mh:%{!ms:-Acpu(h8300) -Amachine(h8300)}} \
-   %{mh:-Acpu(h8300h) -Amachine(h8300h)} \
-   %{ms:-Acpu(h8300s) -Amachine(h8300s)} \
-   %{!mint32:-D__INT_MAX__=32767} %{mint32:-D__INT_MAX__=2147483647}"
-
-#define LINK_SPEC "%{mh:-m h8300h} %{ms:-m h8300s}"
-
-#define LIB_SPEC "%{mrelax:-relax} %{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fprintf (stderr, " (Hitachi H8/300)");
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Make int's 32 bits.  */
-#define TARGET_INT32 (target_flags & 8)
-
-/* Dump recorded insn lengths into the output file.  This helps debug the
-   md file.  */
-#define TARGET_ADDRESSES (target_flags & 64)
-
-/* Pass the first few arguments in registers.  */
-#define TARGET_QUICKCALL (target_flags & 128)
-
-/* Pretend byte accesses are slow.  */
-#define TARGET_SLOWBYTE (target_flags & 256)
-
-/* Dump each assembler insn's rtl into the output file.
-   This is for debugging the compiler only.  */
-#define TARGET_RTL_DUMP	(target_flags & 2048)
-
-/* Select between the h8/300 and h8/300h cpus.  */
-#define TARGET_H8300	(! TARGET_H8300H && ! TARGET_H8300S)
-#define TARGET_H8300H	(target_flags & 4096)
-#define TARGET_H8300S	(target_flags & 1)
-
-/* Align all values on the h8/300h the same way as the h8/300.  Specifically,
-   32 bit and larger values are aligned on 16 bit boundaries.
-   This is all the hardware requires, but the default is 32 bits for the 300h.
-   ??? Now watch someone add hardware floating point requiring 32 bit
-   alignment.  */
-#define TARGET_ALIGN_300 (target_flags & 8192)
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  { {"s",1 },			\
-    {"no-s",-1},		\
-    {"int32",8},		\
-    {"addresses",64 },		\
-    {"quickcall",128},  	\
-    {"no-quickcall",-128},	\
-    {"slowbyte",256},		\
-    {"relax",1024},		\
-    {"rtl-dump",2048},		\
-    {"h",4096},			\
-    {"no-h",-4096},		\
-    {"align-300",8192},	\
-    { "", TARGET_DEFAULT}}
-
-/* Do things that must be done once at start up.  */
-
-#define OVERRIDE_OPTIONS \
-do {				\
-  h8300_init_once ();		\
-} while (0)
-
-/* Default target_flags if no switches specified.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (128)	/* quickcall */
-#endif
-
-/* Show we can debug even without a frame pointer.  */
-/* #define CAN_DEBUG_WITHOUT_FP */
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap. 
-
-   Calls through a register are cheaper than calls to named
-   functions; however, the register pressure this causes makes
-   CSEing of function addresses generally a lose.  */
-#define NO_FUNCTION_CSE 
-
-/* Target machine storage layout */
-
-/* Define to use software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion. */
-#define REAL_ARITHMETIC
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is not true on the H8/300.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is true on the H8/300.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered.  
-   This is true on an H8/300 (actually we can make it up, but we choose to
-   be consistent).  */ 
-#define WORDS_BIG_ENDIAN 1
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD		(TARGET_H8300H || TARGET_H8300S ? 32 : 16)
-#define MAX_BITS_PER_WORD	32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD		(TARGET_H8300H || TARGET_H8300S ? 4 : 2)
-#define MIN_UNITS_PER_WORD	2
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE (TARGET_H8300H || TARGET_H8300S ? 32 : 16)
-
-#define SHORT_TYPE_SIZE 	16
-#define INT_TYPE_SIZE 		(TARGET_INT32 ? 32 : 16)
-#define LONG_TYPE_SIZE 		32
-#define LONG_LONG_TYPE_SIZE	32
-#define FLOAT_TYPE_SIZE 	32
-#define DOUBLE_TYPE_SIZE 	32
-#define LONG_DOUBLE_TYPE_SIZE 	DOUBLE_TYPE_SIZE
-
-#define MAX_FIXED_MODE_SIZE 	32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY (TARGET_H8300H || TARGET_H8300S ? 32 : 16)
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 16
-
-/* Alignment of field after `int : 0' in a structure.  */
-/* One can argue this should be 32 for -mint32, but since 32 bit ints only
-   need 16 bit alignment, this is left as is so that -mint32 doesn't change
-   structure layouts.  */
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS  0
-
-/* No data type wants to be aligned rounder than this.
-   32 bit values are aligned as such on the 300h for speed.  */
-#define BIGGEST_ALIGNMENT \
-(((TARGET_H8300H || TARGET_H8300S) && ! TARGET_ALIGN_300) ? 32 : 16)
-
-/* The stack goes in 16/32 bit lumps.  */
-#define STACK_BOUNDARY (TARGET_H8300 ? 16 : 32)
-
-/* Define this if move instructions will actually fail to work
-   when given unaligned data.  */
-/* On the H8/300, longs can be aligned on halfword boundaries, but not
-   byte boundaries.  */
-#define STRICT_ALIGNMENT 1
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  
-
-   Reg 9 does not correspond to any hardware register, but instead
-   appears in the RTL as an argument pointer prior to reload, and is
-   eliminated during reloading in favor of either the stack or frame
-   pointer.  */
-
-#define FIRST_PSEUDO_REGISTER 10
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.  */
-
-#define FIXED_REGISTERS \
-  { 0, 0, 0, 0, 0, 0, 0, 1, 0, 1}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you
-   like.  
-
-   h8 destroys r0,r1,r2,r3.  */
-
-#define CALL_USED_REGISTERS \
-  { 1, 1, 1, 1, 0, 0, 0, 1, 1, 1 }
-
-#define REG_ALLOC_ORDER \
-  { 2, 3, 0, 1, 4, 5, 6, 8, 7, 9}
-
-#define CONDITIONAL_REGISTER_USAGE	\
-{					\
-  if (!TARGET_H8300S)			\
-    fixed_regs[8] = call_used_regs[8] = 1;\
-}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers. 
-
-   We pretend the MAC register is 32bits -- we don't have any data
-   types on the H8 series to handle more than 32bits.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
-   MODE.
-
-   H8/300: If an even reg, then anything goes. Otherwise the mode must be QI
-           or HI.
-   H8/300H: Anything goes.  */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (TARGET_H8300 ? (((REGNO)&1)==0) || (MODE==HImode) || (MODE==QImode) \
-   : REGNO == 8 ? MODE == SImode : 1)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2)  ((MODE1) == (MODE2))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* H8/300 pc is not overloaded on a register.  */
-
-/*#define PC_REGNUM 15*/
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 7
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 6
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 9
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 3
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-enum reg_class {
-  NO_REGS, GENERAL_REGS, MAC_REGS, ALL_REGS, LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
-{ "NO_REGS", "GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS  			\
-{      0,		/* No regs      */	\
-   0x2ff,		/* GENERAL_REGS */    	\
-   0x100,		/* MAC_REGS */    	\
-   0x3ff,		/* ALL_REGS 	*/	\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) (REGNO != 8 ? GENERAL_REGS : MAC_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS NO_REGS
-#define BASE_REG_CLASS  GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description. 
-
-   'a' is the MAC register.  */
-
-#define REG_CLASS_FROM_LETTER(C) ((C) == 'a' ? MAC_REGS : NO_REGS)
-
-/* The letters I, J, K, L, M, N, O, P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.  */
-
-#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
-#define CONST_OK_FOR_J(VALUE) ((unsigned) (VALUE) < 256)
-#define CONST_OK_FOR_K(VALUE) (((VALUE) == 1) || (VALUE) == 2)
-#define CONST_OK_FOR_L(VALUE) (((VALUE) == -1) || (VALUE) == -2)
-#define CONST_OK_FOR_M(VALUE) (((VALUE) == 3) || (VALUE) == 4)
-#define CONST_OK_FOR_N(VALUE) (((VALUE) == -3) || (VALUE) == -4)
-#define CONST_OK_FOR_O(VALUE) (ok_for_bclr (VALUE))
-#define CONST_OK_FOR_P(VALUE) (small_power_of_two (VALUE))
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
-   (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
-   (C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
-   (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
-   (C) == 'M' ? CONST_OK_FOR_M (VALUE) : \
-   (C) == 'N' ? CONST_OK_FOR_N (VALUE) : \
-   (C) == 'O' ? CONST_OK_FOR_O (VALUE) : \
-   (C) == 'P' ? CONST_OK_FOR_P(VALUE) : \
-   0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself. 
-     
-  `G' is a floating-point zero.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'G' ? (VALUE) == CONST0_RTX (DFmode)	\
-   : 0)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)  (CLASS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-
-/* On the H8, this is the size of MODE in words.  */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Any SI register to register move may need to be reloaded, 
-   so define REGISTER_MOVE_COST to be > 2 so that reload never
-   shortcuts.  */
-
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)  \
-  (CLASS1 == MAC_REGS || CLASS2 == MAC_REGS ? 6 : 3)
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-
-   On the H8/300, @-sp really pushes a byte if you ask it to - but that's
-   dangerous, so we claim that it always pushes a word, then we catch
-   the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output.
-
-   On the H8/300h, we simplify TARGET_QUICKCALL by setting this to 4 and doing
-   a similar thing.  */
-
-#define PUSH_ROUNDING(BYTES) \
-  (((BYTES) + PARM_BOUNDARY/8 - 1) & -PARM_BOUNDARY/8)
-
-/* Offset of first parameter from the argument pointer register value.  */
-/* Is equal to the size of the saved fp + pc, even if an fp isn't
-   saved since the value is used before we know.  */
-
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.
-
-   On the H8 the return does not pop anything.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Definitions for register eliminations.
-
-   This is an array of structures.  Each structure initializes one pair
-   of eliminable registers.  The "from" register number is given first,
-   followed by "to".  Eliminations of the same "from" register are listed
-   in order of preference.
-
-   We have two registers that can be eliminated on the h8300.  First, the
-   frame pointer register can often be eliminated in favor of the stack
-   pointer register.  Secondly, the argument pointer register can always be
-   eliminated; it is replaced with either the stack or frame pointer. */
-
-#define ELIMINABLE_REGS				\
-{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},   \
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
-
-/* Given FROM and TO register numbers, say whether this elimination is allowed.
-   Frame pointer elimination is automatically handled.
-
-   For the h8300, if frame pointer elimination is being done, we would like to
-   convert ap into sp, not fp.
-
-   All other eliminations are valid.  */
-
-#define CAN_ELIMINATE(FROM, TO)					\
- ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM	\
-  ? ! frame_pointer_needed					\
-  : 1)
-
-/* Define the offset between two registers, one to be eliminated, and the other
-   its replacement, at the start of a routine.  */
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
-  OFFSET = initial_offset (FROM, TO)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0. 
-   
-   On the H8 the return value is in R0/R1.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-/* On the h8 the return value is in R0/R1 */
-
-#define LIBCALL_VALUE(MODE) \
-  gen_rtx (REG, MODE, 0)
-
-/* 1 if N is a possible register number for a function value.
-   On the H8, R0 is the only register thus used.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-/* Define this if PCC uses the nonreentrant convention for returning
-   structure and union values.  */
-
-/*#define PCC_STATIC_STRUCT_RETURN*/
-
-/* 1 if N is a possible register number for function argument passing.
-   On the H8, no registers are used in this way.  */
-
-#define FUNCTION_ARG_REGNO_P(N) (TARGET_QUICKCALL ? N < 3 : 0)
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-
-#define STRUCT_VALUE 0
-
-/* Return true if X should be returned in memory.  */
-#define RETURN_IN_MEMORY(X) \
-  (TYPE_MODE (X) == BLKmode || GET_MODE_SIZE (TYPE_MODE (X)) > 4)
-
-/* When defined, the compiler allows registers explicitly used in the
-   rtl to be used as spill registers but prevents the compiler from
-   extending the lifetime of these registers. */
-
-#define SMALL_REGISTER_CLASSES 1
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the H8/300, this is a two item struct, the first is the number of bytes
-   scanned so far and the second is the rtx of the called library
-   function if any.  */
-
-#define CUMULATIVE_ARGS struct cum_arg
-struct cum_arg { int nbytes; struct rtx_def * libcall; };
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the H8/300, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM).nbytes = 0, (CUM).libcall = LIBNAME)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM).nbytes += ((MODE) != BLKmode			\
-  ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD	\
-  : (int_size_in_bytes (TYPE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On the H8/300 all normal args are pushed, unless -mquickcall in which
-   case the first 3 arguments are passed in registers.
-   See function `function_arg'.  */
-
-struct rtx_def *function_arg();
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  function_arg (&CUM, MODE, TYPE, NAMED)
-
-/* Generate assembly output for the start of a function.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) \
-  function_prologue (FILE, SIZE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\t%s\t#LP%d,%s\n\tjsr @mcount\n", \
-	   h8_mov_op, (LABELNO), h8_reg_names[0]);
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.  */
-/* ??? @LPBX0 is moved into r0 twice.  */
-
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\t%s\t%s\n\t%s\t@LPBX0,%s\n\tbne LPI%d\n\t%s\t@LPBX0,%s\n\t%s\t%s\n\tjsr\t@__bb_init_func\nLPI%d:\t%s\t%s\n", \
-	   h8_push_op, h8_reg_names[0],		\
-	   h8_mov_op, h8_reg_names[0],		\
-	   (LABELNO),				\
-	   h8_mov_op, h8_reg_names[0],		\
-	   h8_push_op, h8_reg_names[0],		\
-	   (LABELNO),				\
-	   h8_pop_op, h8_reg_names[0]);
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  This is a real pain in the
-   sphincter on a VAX, since we do not want to change any of the bits in the
-   processor status word.  The way it is done here, it is pushed onto the stack
-   before any flags have changed, and then the stack is fixed up to account for
-   the fact that the instruction to restore the flags only reads a word.
-   It may seem a bit clumsy, but at least it works.  */
-/* ??? This one needs work.  */
-
-#define BLOCK_PROFILER(FILE, BLOCKNO)	\
-  fprintf (FILE, "\tmovpsl -(sp)\n\tmovw (sp),2(sp)\n\taddl2 $2,sp\n\taddl2 $1,LPBX2+%d\n\tbicpsw $255\n\tbispsw (sp)+\n", \
-	   4 * BLOCKNO)
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 0
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-  function_epilogue (FILE, SIZE)
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  
-
-   H8/300
-	      vvvv context
-   1 0000 7900xxxx 		mov.w	#0x1234,r3
-   2 0004 5A00xxxx 		jmp	@0x1234
-	      ^^^^ function
-
-   H8/300H
-	      vvvvvvvv context
-   2 0000 7A00xxxxxxxx 		mov.l	#0x12345678,er3
-   3 0006 5Axxxxxx 		jmp	@0x123456
-	    ^^^^^^ function
-*/
-
-#define TRAMPOLINE_TEMPLATE(FILE)			\
-  do {							\
-    if (TARGET_H8300)					\
-      {							\
-	fprintf (FILE, "\tmov.w	#0x1234,r3\n");		\
-	fprintf (FILE, "\tjmp	@0x1234\n");		\
-      }							\
-    else						\
-      {							\
-	fprintf (FILE, "\tmov.l	#0x12345678,er3\n");	\
-	fprintf (FILE, "\tjmp	@0x123456\n");	\
-      }							\
-  } while (0)
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE (TARGET_H8300 ? 8 : 12)
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)				\
-{										\
-  enum machine_mode mode = TARGET_H8300H || TARGET_H8300S? SImode : HImode; \
-  emit_move_insn (gen_rtx (MEM, mode, plus_constant ((TRAMP), 2)), CXT);    \
-  emit_move_insn (gen_rtx (MEM, mode, plus_constant ((TRAMP), 6)), FNADDR); \
-  if (TARGET_H8300H || TARGET_H8300S)					    \
-    emit_move_insn (gen_rtx (MEM, QImode, plus_constant ((TRAMP), 6)), GEN_INT (0x5A)); \
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-#define HAVE_POST_INCREMENT 1
-/*#define HAVE_POST_DECREMENT 0 */
-
-#define HAVE_PRE_DECREMENT 1
-/*#define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
- 
-#define REGNO_OK_FOR_INDEX_P(regno) 0
-
-#define REGNO_OK_FOR_BASE_P(regno) \
-  (((regno) < FIRST_PSEUDO_REGISTER && regno != 8) || reg_renumber[regno] >= 0)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 1
-
-/* 1 if X is an rtx for a constant that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF	\
-   || (GET_CODE (X) == CONST_INT				\
-       /* We handle signed and unsigned offsets here.  */	\
-       && INTVAL (X) > (TARGET_H8300 ? -0x10000 : -0x1000000)	\
-       && INTVAL (X) < (TARGET_H8300 ? 0x10000 : 0x1000000))	\
-   || ((GET_CODE (X) == HIGH || GET_CODE (X) == CONST)		\
-       && TARGET_H8300))
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) (GET_CODE (X) != CONST_DOUBLE)
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) 0
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-/* Don't use REGNO_OK_FOR_BASE_P here because it uses reg_renumber.  */
-#define REG_OK_FOR_BASE_P(X) \
-	(REGNO (X) >= FIRST_PSEUDO_REGISTER || REGNO (X) != 8)
-#define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-#define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-#define STRICT 0
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-#define STRICT 1
-
-#endif
-
-/* Extra constraints - 'U' if for an operand valid for a bset
-   destination; i.e. a register, register indirect, or the
-   eightbit memory region (a SYMBOL_REF with an SYMBOL_REF_FLAG set). 
-
-   On the H8/S 'U' can also be a 16bit or 32bit absolute.  */
-#define OK_FOR_U(OP) \
-  ((GET_CODE (OP) == REG && REG_OK_FOR_BASE_P (OP)) \
-   || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
-       && REG_OK_FOR_BASE_P (XEXP (OP, 0)))  \
-   || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
-       && (TARGET_H8300S || SYMBOL_REF_FLAG (XEXP (OP, 0)))) \
-   || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == CONST \
-       && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \
-       && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == SYMBOL_REF \
-       && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT) \
-       && (TARGET_H8300S || SYMBOL_REF_FLAG (XEXP (XEXP (OP, 0), 0))))
- 
-#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'U' ? OK_FOR_U (OP) : 0)
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
-   except for CONSTANT_ADDRESS_P which is actually
-   machine-independent.  
-
-   On the H8/300, a legitimate address has the form
-   REG, REG+CONSTANT_ADDRESS or CONSTANT_ADDRESS.  */
-
-/* Accept either REG or SUBREG where a register is valid.  */
-  
-#define RTX_OK_FOR_BASE_P(X)					\
-  ((REG_P (X) && REG_OK_FOR_BASE_P (X))				\
-   || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))		\
-       && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)    	\
-  if (RTX_OK_FOR_BASE_P (X)) goto ADDR;			\
-  if (CONSTANT_ADDRESS_P (X)) goto ADDR;    		\
-  if (GET_CODE (X) == PLUS				\
-      && CONSTANT_ADDRESS_P (XEXP (X, 1))		\
-      && RTX_OK_FOR_BASE_P (XEXP (X, 0))) goto ADDR;
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output. 
-
-   For the H8/300, don't do anything.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)  {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-
-   On the H8/300, the predecrement and postincrement address depend thus
-   (the amount of decrement or increment being the length of the operand).  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
-  if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL;
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE Pmode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/*#define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define this if the case instruction drops through after the table
-   when the index is out of range.  Don't define it if the case insn
-   jumps to the default label instead.  */
-#define CASE_DROPS_THROUGH
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.
-
-   On the H8/300, sign extension is expensive, so we'll say that chars
-   are unsigned.  */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.  */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX	(TARGET_H8300H || TARGET_H8300S ? 4 : 2)
-#define MAX_MOVE_MAX	4
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS TARGET_SLOWBYTE
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode (TARGET_H8300H || TARGET_H8300S ? SImode : HImode)
-
-/* ANSI C types.
-   We use longs for the 300h because ints can be 16 or 32.
-   GCC requires SIZE_TYPE to be the same size as pointers.  */
-#define NO_BUILTIN_SIZE_TYPE
-#define NO_BUILTIN_PTRDIFF_TYPE
-#define SIZE_TYPE (TARGET_H8300 ? "unsigned int" : "long unsigned int")
-#define PTRDIFF_TYPE (TARGET_H8300 ? "int" : "long int")
-
-#define WCHAR_TYPE "short unsigned int"
-#define WCHAR_TYPE_SIZE 16
-#define MAX_WCHAR_TYPE_SIZE 16
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
-   is a valid machine specific attribute for DECL.
-   The attributes in ATTRIBUTES have previously been assigned to DECL.  */
-extern int h8300_valid_machine_decl_attribute ();
-#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
-h8300_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
-
-#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
-  LENGTH += h8300_adjust_insn_length (INSN, LENGTH);
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define DEFAULT_RTX_COSTS(RTX,CODE,OUTER_CODE) \
-  return (const_costs (RTX, CODE));
-
-#define BRANCH_COST 0
-
-/* We say that MOD and DIV are so cheap because otherwise we'll
-   generate some really horrible code for division of a power of two.  */
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  */
-/* ??? Shifts need to have a *much* higher cost than this.  */
-
-#define RTX_COSTS(RTX,CODE,OUTER_CODE) \
-  case MOD:		\
-  case DIV:		\
-    return 60;		\
-  case MULT:		\
-    return 20;		\
-  case ASHIFT:		\
-  case ASHIFTRT:	\
-  case LSHIFTRT:	\
-  case ROTATE:		\
-  case ROTATERT:	\
-    if (GET_MODE (RTX) == HImode) return 2; \
-    return 8; 
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  No extra ones are needed for the h8300.  */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
-
-/* The add insns don't set overflow in a usable way.  */
-#define CC_OVERFLOW_UNUSABLE 01000
-/* The mov,and,or,xor insns don't set carry.  That's ok though as the
-   Z bit is all we need when doing unsigned comparisons on the result of
-   these insns (since they're always with 0).  However, conditions.h has
-   CC_NO_OVERFLOW defined for this purpose.  Rename it to something more
-   understandable.  */
-#define CC_NO_CARRY CC_NO_OVERFLOW
-
-/* Control the assembler format that we output.  */
-
-#define ASM_IDENTIFY_GCC /* nothing */
-
-/* Output at beginning/end of assembler file.  */
-
-#define ASM_FILE_START(FILE) asm_file_start(FILE)
-
-#define ASM_FILE_END(FILE) asm_file_end(FILE)
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "; #APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "; #NO_APP\n"
-
-#define FILE_ASM_OP "\t.file\n"
-#define IDENT_ASM_OP "\t.ident\n"
-
-/* The assembler op to get a word, 2 bytes for the H8/300, 4 for H8/300H.  */
-#define ASM_WORD_OP	(TARGET_H8300 ? ".word" : ".long")
-
-/* We define a readonly data section solely to remove readonly data
-   from the instruction stream.  This can improve relaxing in two significant
-   ways.  First it's more likely that references to readonly data
-   can be done with a 16bit absolute address since they'll be in low
-   memory.  Second, it's more likely that jsr instructions can be
-   turned into bsr instructions since read-only data is not in the
-   instruction stream.  */
-#define READONLY_DATA_SECTION readonly_data
-
-#define TEXT_SECTION_ASM_OP "\t.section .text"
-#define DATA_SECTION_ASM_OP "\t.section .data"
-#define BSS_SECTION_ASM_OP "\t.section .bss"
-#define INIT_SECTION_ASM_OP "\t.section .init"
-#define CTORS_SECTION_ASM_OP "\t.section .ctors"
-#define DTORS_SECTION_ASM_OP "\t.section .dtors"
-#define READONLY_DATA_SECTION_ASM_OP "\t.section .rodata"
-
-#define EXTRA_SECTIONS in_ctors, in_dtors, in_readonly_data
-
-#define EXTRA_SECTION_FUNCTIONS					\
-								\
-void								\
-ctors_section() 						\
-{								\
-  if (in_section != in_ctors)					\
-    {								\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);	\
-      in_section = in_ctors;					\
-    }								\
-}								\
-								\
-void								\
-dtors_section() 						\
-{								\
-  if (in_section != in_dtors)					\
-    {								\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);	\
-      in_section = in_dtors;					\
-    }								\
-}								\
-								\
-void								\
-readonly_data() 						\
-{								\
-  if (in_section != in_readonly_data)				\
-    {								\
-      fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP);\
-      in_section = in_readonly_data;				\
-    }								\
-}
-
-
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)	\
-  do { ctors_section();				\
-       fprintf(FILE, "\t%s\t_%s\n", ASM_WORD_OP, NAME); } while (0)
-
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)	\
-  do { dtors_section();				\
-       fprintf(FILE, "\t%s\t_%s\n", ASM_WORD_OP, NAME); } while (0)
-
-#undef DO_GLOBAL_CTORS_BODY                     
-#define DO_GLOBAL_CTORS_BODY			\
-{						\
-  typedef (*pfunc)();				\
-  extern pfunc __ctors[];			\
-  extern pfunc __ctors_end[];			\
-  pfunc *p;					\
-  for (p = __ctors_end; p > __ctors; )		\
-    {						\
-      (*--p)();					\
-    }						\
-}						
-
-#undef DO_GLOBAL_DTORS_BODY			 
-#define DO_GLOBAL_DTORS_BODY                    \
-{						\
-  typedef (*pfunc)();				\
-  extern pfunc __dtors[];			\
-  extern pfunc __dtors_end[];			\
-  pfunc *p;					\
-  for (p = __dtors; p < __dtors_end; p++)	\
-    {						\
-      (*p)();					\
-    }						\
-}						 
-
-#define TINY_DATA_NAME_P(NAME) (*(NAME) == '&')
-
-/* If we are referencing a function that is supposed to be called
-   through the function vector, the SYMBOL_REF_FLAG in the rtl
-   so the call patterns can generate the correct code.  */
-#define ENCODE_SECTION_INFO(DECL)  \
-  if (TREE_CODE (DECL) == FUNCTION_DECL \
-       && h8300_funcvec_function_p (DECL)) \
-    SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
-  else if ((TREE_STATIC (DECL) || DECL_EXTERNAL (DECL)) \
-      && TREE_CODE (DECL) == VAR_DECL \
-      && h8300_eightbit_data_p (DECL)) \
-    SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
-  else if ((TREE_STATIC (DECL) || DECL_EXTERNAL (DECL)) \
-      && TREE_CODE (DECL) == VAR_DECL \
-      && h8300_tiny_data_p (DECL)) \
-    h8300_encode_label (DECL);
-
-/* Store the user-specified part of SYMBOL_NAME in VAR.
-   This is sort of inverse to ENCODE_SECTION_INFO.  */
-#define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME) \
-  (VAR) = (SYMBOL_NAME) + ((SYMBOL_NAME)[0] == '*' || (SYMBOL_NAME)[0] == '@' || (SYMBOL_NAME)[0] == '&') 
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp", "mac", "ap"}
-
-#define ADDITIONAL_REGISTER_NAMES \
-{ {"er0", 0}, {"er1", 1}, {"er2", 2}, {"er3", 3}, {"er4", 4}, \
-  {"er5", 5}, {"er6", 6}, {"er7", 7}, {"r7", 7} }
-
-/* How to renumber registers for dbx and gdb.
-   H8/300 needs no change in the numeration.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-#define SDB_DEBUGGING_INFO
-#define SDB_DELIM	"\n"
-
-/* Support -gstabs.  */
-
-#include "dbxcoff.h"
-
-/* Override definition in dbxcoff.h.  */
-/* Generate a blank trailing N_SO to mark the end of the .o file, since
-   we can't depend upon the linker to mark .o file boundaries with
-   embedded stabs.  */
-
-#undef DBX_OUTPUT_MAIN_SOURCE_FILE_END
-#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME)			\
-  fprintf (FILE,							\
-	   "\t.text\n.stabs \"\",%d,0,0,.Letext\n.Letext:\n", N_SO)
-
-/* A C statement to output something to the assembler file to switch to section
-   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
-   NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
-   define this macro in such cases.  */
-
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
-  fprintf (FILE, "\t.section %s\n", NAME)
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE, NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-#define ASM_OUTPUT_LABELREF(FILE,NAME)  \
-  asm_fprintf ((FILE), "%U%s", (NAME) + (TINY_DATA_NAME_P (NAME) ? 1 : 0))
-
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) 
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE, NAME)	\
-  do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
-   ASM_OUTPUT_LABEL(FILE, NAME)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-
-   N.B.: The h8300.md branch_true and branch_false patterns also know
-   how to generate internal labels.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM)	\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)	\
-  sprintf (LABEL, "*.%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.
-   It is .dfloat or .gfloat, depending.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.double %s\n", dstr);		\
-   } while (0)
-
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.float %s\n", dstr);		\
-   } while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE, VALUE)		\
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE, VALUE)		\
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE, VALUE)		\
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-#define ASM_OUTPUT_BYTE(FILE, VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
-  fprintf (FILE, "\t%s\t%s\n", h8_push_op, h8_reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
-  fprintf (FILE, "\t%s\t%s\n", h8_pop_op, h8_reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-  asm_fprintf (FILE, "\t%s .L%d\n", ASM_WORD_OP, VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t%s .L%d-.L%d\n", ASM_WORD_OP, VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", (LOG))
-
-/* This is how to output an assembler line
-   that says to advance the location counter by SIZE bytes.  */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  fprintf(FILE, "%s\t \"%s\"\n", IDENT_ASM_OP, NAME)
-
-#define ASM_OUTPUT_SKIP(FILE, SIZE) \
-  fprintf (FILE, "\t.space %d\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\t.comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* This says how to output the assembler to define a global
-   uninitialized but not common symbol.
-   Try to use asm_output_bss to implement this macro.  */
-
-#define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ROUNDED) \
-  asm_output_bss ((FILE), (DECL), (NAME), (SIZE), (ROUNDED))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED)	\
-( fputs ("\t.lcomm ", (FILE)),				\
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print an instruction operand X on file FILE.
-   look in h8300.c for details */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
-  ((CODE) == '#')
-
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand(FILE,X,CODE)
-
-/* Print a memory operand whose address is X, on file FILE.
-   This uses a function in h8300.c.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
-
-/* Define this macro if you want to implement any pragmas.  If defined, it
-   should be a C expression to be executed when #pragma is seen.  The
-   argument GETC is a function which will return the next character in the
-   input stream, or EOF if no characters are left.  The argument UNGETC is
-   a function which will push a character back into the input stream.  The
-   argument NAME is the word following #pragma in the input stream.  The input
-   stream pointer will be pointing just beyond the end of this word.  The
-   expression should return true if it handled the pragma, false otherwise.
-   The input stream should be left undistrubed if false is returned, otherwise
-   it should be pointing at the last character after the end of the pragma
-   (newline or end-of-file).  */
-#define HANDLE_PRAGMA(GETC, UNGETC, NAME) handle_pragma (GETC, UNGETC, NAME)
-extern int handle_pragma ();
-
-#define FINAL_PRESCAN_INSN(insn, operand, nop) final_prescan_insn (insn, operand,nop)
-
-/* Define this macro if GNU CC should generate calls to the System V
-   (and ANSI C) library functions `memcpy' and `memset' rather than
-   the BSD functions `bcopy' and `bzero'.  */
-
-#define TARGET_MEM_FUNCTIONS 1
-
-#define MULHI3_LIBCALL	"__mulhi3"
-#define DIVHI3_LIBCALL	"__divhi3"
-#define UDIVHI3_LIBCALL	"__udivhi3"
-#define MODHI3_LIBCALL	"__modhi3"
-#define UMODHI3_LIBCALL	"__umodhi3"
-
-/* Perform target dependent optabs initialization.  */
-
-#define INIT_TARGET_OPTABS \
-  do { \
-    smul_optab->handlers[(int) HImode].libfunc		\
-      = gen_rtx (SYMBOL_REF, Pmode, MULHI3_LIBCALL);	\
-    sdiv_optab->handlers[(int) HImode].libfunc		\
-      = gen_rtx (SYMBOL_REF, Pmode, DIVHI3_LIBCALL);	\
-    udiv_optab->handlers[(int) HImode].libfunc		\
-      = gen_rtx (SYMBOL_REF, Pmode, UDIVHI3_LIBCALL);	\
-    smod_optab->handlers[(int) HImode].libfunc		\
-      = gen_rtx (SYMBOL_REF, Pmode, MODHI3_LIBCALL);	\
-    umod_optab->handlers[(int) HImode].libfunc		\
-      = gen_rtx (SYMBOL_REF, Pmode, UMODHI3_LIBCALL);	\
-  } while (0)
-
-#define MOVE_RATIO 3
-
-/* Declarations for functions used in insn-output.c.  */
-char *emit_a_shift ();
-int h8300_funcvec_function_p ();
-char *output_adds_subs ();
-char * output_simode_bld ();
-
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
deleted file mode 100755
index d892cad..0000000
--- a/gcc/config/h8300/h8300.md
+++ /dev/null
@@ -1,2291 +0,0 @@
-;; GCC machine description for Hitachi H8/300
-;; Copyright (C) 1992, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
-
-;;   Contributed by Steve Chamberlain (sac@cygnus.com),
-;;   Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;; The original PO technology requires these to be ordered by speed,
-;; so that assigner will pick the fastest.
-
-;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-(define_attr "cpu" "h8300,h8300h"
-  (const (symbol_ref "cpu_type")))
-
-;; Many logical operations should have "bit" variants if only one
-;; bit is going to be operated on.
-
-;; (and (logical op) (const_int X))
-;; If const_int only specifies a few bits (like a single byte in a 4 byte
-;; operation, then it's more efficient to only apply the and and logical_op
-;; to the bits we care about.
-
-;; Some of the extend instructions accept a general_operand_src, which
-;; allows all the normal memory addressing modes.  The length computations
-;; don't take this into account.  The lengths in the MD file should be
-;; "worst case" and then be adjusted to their correct values by
-;; h8300_adjust_insn_length.
-
-;; On the h8300h, adds/subs operate on the 32bit "er" registers.  Right
-;; now GCC doesn't expose the "e" half to the compiler, so using add/subs
-;; for addhi and subhi is safe.
-;; Long term, we want to expose the "e" half to the compiler (gives us
-;; 8 more 16bit registers).  At that point addhi and subhi can't use adds/subs.
-
-;; There's currently no way to have a insv/extzv expander for the h8/300h
-;; because word_mode is different for the h8/300 and h8/300h.
-
-;; Shifts/rotates by small constants should be handled by special
-;; patterns so we get the length and cc status correct.
-
-;; Bitfield operations no longer accept memory operands.  We need
-;; to add variants which operate on memory back to the MD.
-
-;; ??? Implement remaining bit ops available on the h8300
-
-(define_attr "type" "branch,arith"
-  (const_string "arith"))
-
-;; The size of instructions in bytes.
-
-(define_attr "length" "" 
-  (cond [(eq_attr "type" "branch")
-	 (if_then_else (and (ge (minus (pc) (match_dup 0))
-				(const_int -120))
-			    (le (minus (pc) (match_dup 0))
-				(const_int 120)))
-		       (const_int 2)
-		       (if_then_else (and (eq_attr "cpu" "h8300h")
-					  (and (ge (minus (pc) (match_dup 0))
-						   (const_int -32000))
-					       (le (minus (pc) (match_dup 0))
-						   (const_int 32000))))
-				     (const_int 4)
-				     (const_int 6)))]
-	(const_int 200)))
-
-;; Condition code settings.
-;; none - insn does not affect cc
-;; none_0hit - insn does not affect cc but it does modify operand 0
-;;	This attribute is used to keep track of when operand 0 changes.
-;; 	See the description of NOTICE_UPDATE_CC for more info.
-;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
-;; set_zn  - insn sets z,n to usable values; v,c are unknown.
-;; compare - compare instruction
-;; clobber - value of cc is unknown
-(define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
-  (const_string "clobber"))
-
-;; ----------------------------------------------------------------------
-;; MOVE INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; movqi
-
-(define_insn "movqi_push"
-  [(set (match_operand:QI 0 "push_operand" "=<")
-	(match_operand:QI 1 "register_operand" "r"))]
-  ""
-  "*
-{
-  if (TARGET_H8300)
-    return \"push.w	%T1\";
-  else
-    return \"push.l	%S1\";
-}"
-  [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
-   (set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand_dst" "=r,r,<,r,r,m")
-	(match_operand:QI 1 "general_operand_src" "I,r>,r,n,m,r"))]
-  "register_operand (operands[0],QImode)
-   || register_operand (operands[1], QImode)"
-  "@
-   sub.b	%X0,%X0
-   mov.b	%R1,%X0
-   mov.b	%X1,%R0
-   mov.b	%R1,%X0
-   mov.b	%R1,%X0
-   mov.b	%X1,%R0"
-  [(set_attr_alternative "length"
-     [(const_int 2) (const_int 2) (const_int 2) (const_int 2)
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
-   (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand_dst" "")
-	(match_operand:QI 1 "general_operand_src" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand(operand0, QImode)
-      && !register_operand(operand1, QImode))
-    {
-      operands[1] = copy_to_mode_reg(QImode, operand1);
-    }
-}")
-
-(define_insn "movstrictqi"
-  [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "=r,r,r,r"))
-			 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
-  ""
-  "@
-   sub.b	%X0,%X0
-   mov.b	%X1,%X0
-   mov.b	%R1,%X0
-   mov.b	%R1,%X0"
-  [(set_attr_alternative "length"
-     [(const_int 2) (const_int 2) (const_int 2)
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
-   (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
-   
-;; movhi
-
-;; ??? We use push.l on the h8300h to push a 16bit value?!?  We have
-;; 16bit push insns!
-(define_insn "movhi_push"
-  [(set (match_operand:HI 0 "push_operand" "=<")
-	(match_operand:HI 1 "register_operand" "r"))]
-  ""
-  "*
-{
-  if (TARGET_H8300)
-    return \"push.w	%T1\";
-  else
-    return \"push.l	%S1\";
-}"
-  [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
-   (set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
-	(match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
-  "register_operand (operands[0],HImode)
-   || register_operand (operands[1], HImode)"
-  "@
-   sub.w	%T0,%T0
-   mov.w	%T1,%T0
-   mov.w	%T1,%T0
-   mov.w	%T1,%T0
-   mov.w	%T1,%T0
-   mov.w	%T1,%T0"
-  [(set_attr_alternative "length"
-     [(const_int 2) (const_int 2) (const_int 2) (const_int 4)
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
-   (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand_dst" "")
-	(match_operand:HI 1 "general_operand_src" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand(operand1, HImode)
-      && !register_operand(operand0, HImode))
-    {
-      operands[1] = copy_to_mode_reg(HImode, operand1);
-    }
-}")
-
-(define_insn "movstricthi"
-  [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "=r,r,r,r"))
-			 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
-  ""
-  "@
-   sub.w	%T0,%T0
-   mov.w	%T1,%T0
-   mov.w	%T1,%T0
-   mov.w	%T1,%T0"
-  [(set_attr_alternative "length"
-     [(const_int 2) (const_int 2) (const_int 4)
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
-   (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
-
-;; movsi
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand_dst" "")
-	(match_operand:SI 1 "general_operand_src" ""))]
-  ""
-  "
-{
-  if (TARGET_H8300)
-    {
-      if (do_movsi (operands))
-	DONE;
-    }
-  else
-    {
-      /* One of the ops has to be in a register.  */
-      if (!register_operand (operand1, SImode)
-	  && !register_operand (operand0, SImode))
-	{
-	  operands[1] = copy_to_mode_reg (SImode, operand1);
-	}
-    }
-}")
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand_dst" "")
-	(match_operand:SF 1 "general_operand_src" ""))]
-  ""
-  "
-{
-  if (TARGET_H8300)
-    {
-      if (do_movsi (operands))
-	DONE;
-    }
-  else
-    {
-      /* One of the ops has to be in a register.  */
-      if (!register_operand (operand1, SFmode)
-	  && !register_operand (operand0, SFmode))
-	{
-	  operands[1] = copy_to_mode_reg (SFmode, operand1);
-	}
-    }
-}")
-
-(define_insn "movsi_h8300"
-  [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
-	(match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
-  "TARGET_H8300
-   && (register_operand (operands[0], SImode)
-       || register_operand (operands[1], SImode))"
-  "*
-{
-  int rn = -1;
-  switch (which_alternative)
-    {
-    case 0:
-      return \"sub.w	%e0,%e0\;sub.w	%f0,%f0\";
-    case 1:
-      if (REGNO(operands[0]) < REGNO(operands[1]))
-	return \"mov.w	%e1,%e0\;mov.w	%f1,%f0\";
-      else 
-	return \"mov.w	%f1,%f0\;mov.w	%e1,%e0\";
-    case 2:
-      /* Make sure we don't trample the register we index with.  */
-    
-      if (GET_CODE(operands[1]) == MEM) 
-	{
-	  rtx inside = XEXP (operands[1],0);
-	  if  (REG_P (inside)) 
-	    {
-	      rn = REGNO(inside);
-	    }
-	  else if (GET_CODE (inside) == PLUS) 
-	    {
-	      rtx lhs = XEXP (inside,0);
-	      rtx rhs = XEXP (inside,1);
-	      if (REG_P (lhs)) rn = REGNO (lhs);
-	      if (REG_P (rhs)) rn = REGNO (rhs);
-	    }
-	}
-      if (rn == REGNO (operands[0])) 	
-	{
-	  /* Move the second word first.  */
-	  return \"mov.w	%f1,%f0\;mov.w	%e1,%e0\";
-	}
-      else 
-	{
-	  /* See if either half is zero.  If so, use sub.w to clear
-	     that half.  */
-	if (GET_CODE (operands[1]) == CONST_INT)
-	  {
-	    if ((INTVAL (operands[1]) & 0xffff) == 0)
-	      return \"mov.w	%e1,%e0\;sub.w	%f0,%f0\";
-	    if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
-	      return \"sub.w	%e0,%e0\;mov.w	%f1,%f0\";
-	  }
-	return \"mov.w	%e1,%e0\;mov.w	%f1,%f0\";
-	}
-    case 3:
-	return \"mov.w	%e1,%e0\;mov.w	%f1,%f0\";
-    case 4:
-      return \"mov.w	%f1,%T0\;mov.w	%e1,%T0\";
-    case 5:
-      return \"mov.w	%T1,%e0\;mov.w	%T1,%f0\";
-    }
-}"
-  [(set_attr "length" "4,4,8,8,4,4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "movsf_h8300"
-  [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
-	(match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
-  "TARGET_H8300
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode))"
-  "*
-{
-  /* Copy of the movsi stuff */
-  int rn = -1;
-  switch (which_alternative)
-    {
-    case 0:
-      return \"sub.w	%e0,%e0\;sub.w	%f0,%f0\";
-    case 1:
-      if (REGNO(operands[0]) < REGNO(operands[1]))
-	return \"mov.w	%e1,%e0\;mov.w	%f1,%f0\";
-      else 
-	return \"mov.w	%f1,%f0\;mov.w	%e1,%e0\";
-    case 2:
-      /* Make sure we don't trample the register we index with.  */
-    
-      if (GET_CODE (operands[1]) == MEM) 
-	{
-	  rtx inside = XEXP (operands[1],0);
-	  if (REG_P (inside))
-	    {
-	      rn = REGNO (inside);
-	    }
-	  else if (GET_CODE (inside) == PLUS) 
-	    {
-	      rtx lhs = XEXP (inside,0);
-	      rtx rhs = XEXP (inside,1);
-	      if (REG_P (lhs)) rn = REGNO (lhs);
-	      if (REG_P (rhs)) rn = REGNO (rhs);
-	    }
-	}
-      if (rn == REGNO (operands[0]))
-	{
-	  /* move the second word first */
-	  return \"mov.w	%f1,%f0\;mov.w	%e1,%e0\";
-	}
-      else 
-	{
-	  return \"mov.w	%e1,%e0\;mov.w	%f1,%f0\";
-	}
-    
-    case 3:
-      return \"mov.w	%e1,%e0\;mov.w	%f1,%f0\";
-    case 4:
-      return \"mov.w	%f1,%T0\;mov.w	%e1,%T0\";
-    case 5:
-      return \"mov.w	%T1,%e0\;mov.w	%T1,%f0\";
-
-    }
-}"
-  [(set_attr "length" "4,4,8,8,4,4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "movsi_h8300hs"
-  [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,m,<,r,*a,*a,r")
-	(match_operand:SI 1 "general_operand_src" "I,r,im,r,r,>,I,r,*a"))]
-  "(TARGET_H8300S || TARGET_H8300H)
-   && (register_operand (operands[0], SImode)
-       || register_operand (operands[1], SImode))"
-  "*
-{
-  if (which_alternative == 0)
-    return \"sub.l	%S0,%S0\";
-  if (which_alternative == 6)
-    return \"clrmac\";
-  if (which_alternative == 7)
-    return \"clrmac\;ldmac %1,macl\";
-  if (which_alternative == 8)
-    return \"stmac macl,%0\";
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      int val = INTVAL (operands[1]);
-
-      /* Look for constants which can be made by adding an 8-bit
-	 number to zero in one of the two low bytes.  */
-      if (val == (val & 0xff))
-	{
-	  operands[1] = GEN_INT ((char)val & 0xff);
-	  return \"sub.l %S0,%S0\;add.b %1,%w0\";
-	}
-     
-      if (val == (val & 0xff00))
-	{
-	  operands[1] = GEN_INT ((char)(val >> 8) & 0xff);
-	  return \"sub.l %S0,%S0\;add.b %1,%x0\";
-	}
-
-      /* Now look for small negative numbers.  We can subtract them
-	 from zero to get the desired constant.  */
-      if (val == -4 || val == -2 || val == -1)
-	{
-	  operands[1] = GEN_INT (-INTVAL (operands[1]));
-	  return \"sub.l %S0,%S0\;subs %1,%S0\";
-	}
-    }
-   return \"mov.l	%S1,%S0\";
-}"
-  [(set_attr "length" "2,2,10,10,4,4,2,6,4")
-   (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
-
-(define_insn "movsf_h8300h"
-  [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
-	(match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
-  "(TARGET_H8300H || TARGET_H8300S)
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode))"
-  "@
-   sub.l	%S0,%S0
-   mov.l	%S1,%S0
-   mov.l	%S1,%S0
-   mov.l	%S1,%S0
-   mov.l	%S1,%S0
-   mov.l	%S1,%S0"
-  [(set_attr "length" "2,2,10,10,4,4")
-   (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
-
-;; ----------------------------------------------------------------------
-;; TEST INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn ""
-  [(set (cc0) (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "rU")
-			       (const_int 1)
-			       (match_operand:QI 1 "const_int_operand" "n")))]
-  ""
-  "btst	%Z1,%R0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-(define_insn ""
-  [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "rU")
-			       (const_int 1)
-			       (match_operand:QI 1 "const_int_operand" "n")))]
-  ""
-  "btst	%Z1,%Y0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-(define_insn ""
-  [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "rU")
-			       (const_int 1)
-			       (match_operand:QI 1 "const_int_operand" "n")))]
-  ""
-  "btst	%Z1,%Y0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-(define_insn ""
-  [(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r")
-			       (const_int 1)
-			       (match_operand:HI 1 "const_int_operand" "n")))]
-  ""
-  "btst	%Z1,%R0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-  
-(define_insn ""
-  [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
-			       (const_int 1)
-			       (match_operand:HI 1 "const_int_operand" "n")))]
-  ""
-  "btst	%Z1,%Y0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-(define_insn ""
-  [(set (cc0) (zero_extract:SI (match_operand:HI 0 "register_operand" "r")
-			       (const_int 1)
-			       (match_operand:HI 1 "const_int_operand" "n")))]
-  ""
-  "btst	%Z1,%Y0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-(define_insn "tstqi"
-  [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
-  ""
-  "mov.b	%X0,%X0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_znv")])
-
-(define_insn "tsthi"
-  [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
-  ""
-  "mov.w	%T0,%T0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_znv")])
-
-(define_insn "tstsi"
-  [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "mov.l	%S0,%S0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_znv")])
-
-(define_insn "cmpqi"
-  [(set (cc0)
-	(compare:QI (match_operand:QI 0 "register_operand" "r")
-		    (match_operand:QI 1 "nonmemory_operand" "rn")))]
-  ""
-  "cmp.b	%X1,%X0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "compare")])
-
-(define_expand "cmphi"
-  [(set (cc0)
-	(compare:HI (match_operand:HI 0 "register_operand" "")
-		    (match_operand:HI 1 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  /* Force operand1 into a register if we're compiling
-     for the h8/300.  */
-  if (GET_CODE (operands[1]) != REG && TARGET_H8300)
-    operands[1] = force_reg (HImode, operands[1]);
-}")
-
-(define_insn ""
-  [(set (cc0)
-	(compare:HI (match_operand:HI 0 "register_operand" "r")
-		    (match_operand:HI 1 "register_operand" "r")))]
-  "TARGET_H8300"
-  "cmp.w	%T1,%T0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "compare")])
-
-(define_insn ""
-  [(set (cc0)
-	(compare:HI (match_operand:HI 0 "register_operand" "r,r")
-		    (match_operand:HI 1 "nonmemory_operand" "r,n")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "cmp.w	%T1,%T0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "compare,compare")])
-
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare:SI (match_operand:SI 0 "register_operand" "r,r")
-		    (match_operand:SI 1 "nonmemory_operand" "r,i")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "cmp.l	%S1,%S0"
-  [(set_attr "length" "2,6")
-   (set_attr "cc" "compare,compare")])
-
-;; ----------------------------------------------------------------------
-;; ADD INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "addqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(plus:QI (match_operand:QI 1 "register_operand" "%0")
-		 (match_operand:QI 2 "nonmemory_operand" "rn")))]
-  ""
-  "add.b	%X2,%X0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-(define_expand "addhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(plus:HI (match_operand:HI 1 "register_operand" "")
-		 (match_operand:HI 2 "nonmemory_operand" "")))]
-  ""
-  "")
-
-;; Specialized version using adds/subs.  This must come before
-;; the more general patterns below.
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(plus:HI (match_operand:HI 1 "register_operand" "%0")
-		 (match_operand:HI 2 "adds_subs_operand" "n")))]
-  ""
-  "* return output_adds_subs (operands);"
-  [(set_attr "cc" "none_0hit")
-   (set (attr "length")
-        (if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
-			  (const_int 0))
-		      (const_int 2)
-		      (const_int 4)))])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r,r,&r")
-	(plus:HI (match_operand:HI 1 "register_operand" "%0,0,g")
-		 (match_operand:HI 2 "nonmemory_operand" "n,r,r")))]
-  "TARGET_H8300"
-  "@
-   add.b	%s2,%s0\;addx	%t2,%t0 
-   add.w	%T2,%T0
-   mov.w        %T1,%T0\;add.w  %T2,%T0"
-  [(set_attr "length" "4,2,6")
-   (set_attr "cc" "clobber,set_zn,set_zn")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(plus:HI (match_operand:HI 1 "register_operand" "%0,0")
-		 (match_operand:HI 2 "nonmemory_operand" "n,r")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "@
-   add.w	%T2,%T0
-   add.w	%T2,%T0"
-  [(set_attr "length" "4,2")
-   (set_attr "cc" "set_zn,set_zn")])
-
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "")
-
-;; Specialized version using adds/subs.  This must come before
-;; the more general patterns below.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0")
-		 (match_operand:SI 2 "adds_subs_operand" "n")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "* return output_adds_subs (operands);"
-  [(set_attr "cc" "none_0hit")
-   (set (attr "length")
-        (if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
-			  (const_int 0))
-		      (const_int 2)
-		      (const_int 4)))])
-
-(define_insn "addsi_h8300"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
-		 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
-  "TARGET_H8300"
-  "@
-   add	%w2,%w0\;addx	%x2,%x0\;addx	%y2,%y0\;addx	%z2,%z0
-   add.w	%f2,%f0\;addx	%y2,%y0\;addx	%z2,%z0
-   mov.w	%f1,%f0\;mov.w	%e1,%e0\;add.w	%f2,%f0\;addx	%y2,%y0\;addx	%z2,%z0"
-  [(set_attr "length" "8,6,10")
-   (set_attr "cc" "clobber")])
-
-(define_insn "addsi_h8300h"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,0")
-		 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "@
-   add.l	%S2,%S0
-   add.l	%S2,%S0"
-  [(set_attr "length" "6,2")
-   (set_attr "cc" "set_zn,set_zn")])
-
-;; ----------------------------------------------------------------------
-;; SUBTRACT INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "subqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r,r")
-	(minus:QI (match_operand:QI 1 "register_operand" "0,0")
-		  (match_operand:QI 2 "nonmemory_operand" "r,n")))]
-  ""
-  "@
-   sub.b	%X2,%X0
-   add.b	%G2,%X0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-(define_expand "subhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(minus:HI (match_operand:HI 1 "general_operand" "")
-		  (match_operand:HI 2 "nonmemory_operand" "")))]
-  ""
-  "")
-
-;; Specialized version using adds/subs.  This must come before
-;; the more general patterns below.  This may not be needed
-;; due to instruction canonicalization.
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(minus:HI (match_operand:HI 1 "register_operand" "r")
-		  (match_operand:HI 2 "adds_subs_operand" "n")))]
-  ""
-  "*
-{
-  operands[2] = GEN_INT (-INTVAL (operands[2]));
-  return output_adds_subs (operands);
-}"
-  [(set_attr "cc" "none_0hit")
-   (set (attr "length")
-        (if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
-			  (const_int 0))
-		      (const_int 2)
-		      (const_int 4)))])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,&r")
-	(minus:HI (match_operand:HI 1 "general_operand" "0,0")
-		  (match_operand:HI 2 "nonmemory_operand" "r,n")))]
-  "TARGET_H8300"
-  "@
-   sub.w	%T2,%T0
-   add.b	%E2,%s0\;addx	%F2,%t0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "set_zn,clobber")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,&r")
-	(minus:HI (match_operand:HI 1 "general_operand" "0,0")
-		  (match_operand:HI 2 "nonmemory_operand" "r,n")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "@
-   sub.w	%T2,%T0
-   sub.w	%T2,%T0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "set_zn,set_zn")])
-
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 1 "register_operand" "")
-		  (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "")
-
-(define_insn "subsi3_h8300"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "0")
-		  (match_operand:SI 2 "register_operand" "r")))]
-  "TARGET_H8300"
-  "sub.w	%f2,%f0\;subx	%y2,%y0\;subx	%z2,%z0"
-  [(set_attr "length" "6")
-   (set_attr "cc" "clobber")])
-
-;; Specialized version using adds/subs.  This must come before
-;; the more general patterns below.  This may not be needed
-;; due to instruction canonicalization.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "general_operand" "0")
-		  (match_operand:SI 2 "adds_subs_operand" "n")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "*
-{
-  operands[2] = GEN_INT (-INTVAL (operands[2]));
-  return output_adds_subs (operands);
-}"
-  [(set_attr "cc" "none_0hit")
-   (set (attr "length")
-        (if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
-			  (const_int 0))
-		      (const_int 2)
-		      (const_int 4)))])
-
-(define_insn "subsi3_h8300h"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(minus:SI (match_operand:SI 1 "general_operand" "0,0")
-		  (match_operand:SI 2 "nonmemory_operand" "r,i")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "@
-   sub.l	%S2,%S0
-   sub.l	%S2,%S0"
-  [(set_attr "length" "2,6")
-   (set_attr "cc" "set_zn,set_zn")])
-
-;; ----------------------------------------------------------------------
-;; MULTIPLY INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; Note that the h8/300 can only handle umulqihi3.
-
-(define_insn "mulqihi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
-		 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "mulxs.b	%X2,%T0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "set_zn")])
-
-(define_insn "mulhisi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
-		 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "mulxs.w	%T2,%S0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "set_zn")])
-
-(define_insn "umulqihi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
-		 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
-  ""
-  "mulxu	%X2,%T0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none_0hit")])
-
-(define_insn "umulhisi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
-		 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "mulxu.w	%T2,%S0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none_0hit")])
-
-;; This is a "bridge" instruction.  Combine can't cram enough insns
-;; together to crate a MAC instruction directly, but it can create
-;; this instruction, which then allows combine to create the real
-;; MAC insn.
-;;
-;; Unfortunately, if combine doesn't create a MAC instruction, this
-;; insn must generate reasonably correct code.  Egad.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(mult:SI
-	  (sign_extend:SI
-	    (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
-	  (sign_extend:SI
-	    (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
-  "TARGET_H8300S"
-  "clrmac\;mac	%2,%1"
-  [(set_attr "length" "6")
-   (set_attr "cc" "none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(plus (mult:SI
-	  (sign_extend:SI (mem:HI
-	    (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
-	  (sign_extend:SI (mem:HI
-	    (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
-	      (match_operand:SI 3 "register_operand" "0")))]
-  "TARGET_H8300S"
-  "mac	%2,%1"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")])
-
-;; ----------------------------------------------------------------------
-;; DIVIDE INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "udivqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(truncate:QI
-	  (udiv:HI
-	    (match_operand:HI 1 "general_operand" "0")
-	    (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
-  ""
-  "divxu	%X2,%T0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "clobber")])
-
-;; ??? Will divxu always work here?
-
-(define_insn "divqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(truncate:QI
-	  (div:HI
-	    (match_operand:HI 1 "general_operand" "0")
-	    (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
-  ""
-  "divxu	%X2,%T0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "clobber")])
-
-(define_insn "udivhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(truncate:HI
-	  (udiv:SI
-	    (match_operand:SI 1 "general_operand" "0")
-	    (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "divxu.w	%T2,%S0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "clobber")])
-
-(define_insn "divhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(truncate:HI
-	  (div:SI
-	    (match_operand:SI 1 "general_operand" "0")
-	    (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "divxs.w	%T2,%S0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-;; ----------------------------------------------------------------------
-;; MOD INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "umodqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(truncate:QI
-	  (umod:HI
-	    (match_operand:HI 1 "general_operand" "0")
-	    (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
-  ""
-  "divxu	%X2,%T0\;mov %t0,%s0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "modqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(truncate:QI
-	  (mod:HI
-	    (match_operand:HI 1 "general_operand" "0")
-	    (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "divxs.b	%X2,%T0\;mov %t0,%s0"
-  [(set_attr "length" "6")
-   (set_attr "cc" "clobber")])
-
-(define_insn "umodhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(truncate:HI
-	  (umod:SI
-	    (match_operand:SI 1 "general_operand" "0")
-	    (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "divxu.w	%T2,%S0\;mov %e0,%f0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "modhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(truncate:HI
-	  (mod:SI
-	    (match_operand:SI 1 "general_operand" "0")
-	    (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "divxs.w	%T2,%S0\;mov %e0,%f0"
-  [(set_attr "length" "6")
-   (set_attr "cc" "clobber")])
-
-;; ----------------------------------------------------------------------
-;; AND INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn ""
-  [(set (match_operand:QI 0 "bit_operand" "=r,U")
-	(and:QI (match_operand:QI 1 "bit_operand" "%0,0")
-		(match_operand:QI 2 "nonmemory_operand" "rn,O")))]
-  "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
-  "@
-   and	%X2,%X0
-   bclr	%W2,%R0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "set_znv,none_0hit")])
-
-(define_expand "andqi3"
-  [(set (match_operand:QI 0 "bit_operand" "")
-	(and:QI (match_operand:QI 1 "bit_operand" "")
-		(match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (fix_bit_operand (operands, 'O', AND))
-    DONE;
-}")
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(and:HI (match_operand:HI 1 "register_operand" "%0")
-		(match_operand:HI 2 "nonmemory_operand" "rn")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-
-      if ((i & 0x00ff) != 0x00ff) 
-	output_asm_insn (\"and	%s2,%s0\", operands);
-      if ((i & 0xff00) != 0xff00) 
-	output_asm_insn (\"and	%t2,%t0\", operands);
-      return \"\";
-    }
-  if (TARGET_H8300H || TARGET_H8300S)
-    return \"and.w %T2,%T0\";
-  return \"and	%s2,%s0\;and	%t2,%t0;\";
-}"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (match_operand:SI 1 "register_operand" "%0")
-		(match_operand:SI 2 "nonmemory_operand" "rn")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-      int upper_cleared, lower_cleared;
-
-      /* The h8300h can't do byte-wise operations on the
-	 upper 16bits of 32bit registers.  However, if
-	 those bits aren't going to change, or they're
-	 going to be zero'd out, then we can work on the
-	 low-order bits.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && ((i & 0xffff0000) != 0xffff0000
-	      || (i & 0xffff0000) == 0x00000000))
-        return \"and.l	%S2,%S0\";
-
-      lower_cleared = 0;
-      if ((i & 0x0000ffff) == 0x00000000)
-	{
-	  output_asm_insn (\"sub.w	%f0,%f0\", operands);
-	  lower_cleared = 1;
-	}
-
-      upper_cleared = 0;
-      if ((i & 0xffff0000) == 0x00000000)
-	{
-	  output_asm_insn (\"sub.w	%e0,%e0\", operands);
-	  upper_cleared = 1;
-	}
-
-      if ((i & 0x000000ff) != 0x000000ff && !lower_cleared)
-	output_asm_insn (\"and	%w2,%w0\", operands);
-      if ((i & 0x0000ff00) != 0x0000ff00 && !lower_cleared)
-	output_asm_insn (\"and	%x2,%x0\", operands);
-      if ((i & 0x00ff0000) != 0x00ff0000 && !upper_cleared) 
-	output_asm_insn (\"and	%y2,%y0\", operands);
-      if ((i & 0xff000000) != 0xff000000 && !upper_cleared) 
-	output_asm_insn (\"and	%z2,%z0\", operands);
-      return \"\";
-    }
-  if (TARGET_H8300H || TARGET_H8300S)
-    return \"and.l	%S2,%S0\";
-  return \"and	%w2,%w0\;and	%x2,%x0\;and	%y2,%y0\;and	%z2,%z0\;\";
-}"
-  [(set_attr "length" "8")
-   (set_attr "cc" "clobber")])
-
-
-;; ----------------------------------------------------------------------
-;; OR INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn ""
-  [(set (match_operand:QI 0 "bit_operand" "=r,U")
-	(ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
-		(match_operand:QI 2 "nonmemory_operand" "rn,P")))]
-  "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
-  "@
-   or	%X2,%X0
-   bset	%V2,%R0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "set_znv,none_0hit")])
-
-(define_expand "iorqi3"
-  [(set (match_operand:QI 0 "bit_operand" "=r,U")
-	(ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
-		(match_operand:QI 2 "nonmemory_operand" "rn,P")))]
-  ""
-  "
-{
-  if (fix_bit_operand (operands, 'P', IOR))
-    DONE;
-}")
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=r,r")
-	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "J,rn")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-
-      if ((i & 0x00ff) != 0) 
-	output_asm_insn (\"or	%s2,%s0\", operands);
-      if ((i & 0xff00) != 0) 
-	output_asm_insn (\"or	%t2,%t0\", operands);
-      return \"\";
-    }
-  if (TARGET_H8300H || TARGET_H8300S)
-    return \"or.w	%T2,%T0\";
-  return \"or	%s2,%s0\;or	%t2,%t0; %2 or2\";
-}"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "clobber,clobber")])
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
-		(match_operand:SI 2 "nonmemory_operand" "J,rn")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-
-      /* The h8300h can't do byte-wise operations on the
-	 upper 16bits of 32bit registers.  However, if
-	 those bits aren't going to change, then we can
-	 work on the low-order bits.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && (i & 0xffff0000) != 0x00000000)
-        return \"or.l	%S2,%S0\";
-	
-      if ((i & 0x000000ff) != 0) 
-	output_asm_insn (\"or	%w2,%w0\", operands);
-      if ((i & 0x0000ff00) != 0) 
-	output_asm_insn (\"or	%x2,%x0\", operands);
-      if ((i & 0x00ff0000) != 0) 
-	output_asm_insn (\"or	%y2,%y0\", operands);
-      if ((i & 0xff000000) != 0) 
-	output_asm_insn (\"or	%z2,%z0\", operands);
-      return \"\";
-    }
-  if (TARGET_H8300H || TARGET_H8300S)
-    return \"or.l	%S2,%S0\";
-  return \"or	%w2,%w0\;or	%x2,%x0\;or	%y2,%y0\;or	%z2,%z0\;\";
-}"
-  [(set_attr "length" "2,8")
-   (set_attr "cc" "clobber,clobber")])
-
-;; ----------------------------------------------------------------------
-;; XOR INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn ""
-  [(set (match_operand:QI 0 "bit_operand" "=r,U")
-	(xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
-		(match_operand:QI 2 "nonmemory_operand" "rn,P")))]
-  "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
-  "@
-   xor	%X2,%X0
-   bnot	%V2,%R0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "set_znv,none_0hit")])
-
-(define_expand "xorqi3"
-  [(set (match_operand:QI 0 "bit_operand" "=r,U")
-	(xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
-		(match_operand:QI 2 "nonmemory_operand" "rn,O")))]
-  ""
-  "
-{
-  if (fix_bit_operand (operands, 'O', XOR))
-    DONE;
-}")
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(xor:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "nonmemory_operand" "J,rn")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-
-      if ((i & 0x00ff) != 0) 
-	output_asm_insn (\"xor	%s2,%s0\", operands);
-      if ((i & 0xff00) != 0) 
-	output_asm_insn (\"xor	%t2,%t0\", operands);
-      return \"\";
-    }
-  if (TARGET_H8300H || TARGET_H8300S)
-    return \"xor.w	%T2,%T0\";
-  return \"xor	%s2,%s0\;xor	%t2,%t0\";
-}"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "clobber,clobber")])
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(xor:SI (match_operand:SI 1 "register_operand" "%0,0")
-		(match_operand:SI 2 "nonmemory_operand" "J,rn")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-
-      /* The h8300h can't do byte-wise operations on the
-	 upper 16bits of 32bit registers.  However, if
-	 those bits aren't going to change, then we can
-	 work on the low-order bits.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && (i & 0xffff0000) != 0x00000000)
-        return \"xor.l	%S2,%S0\";
-
-      if ((i & 0x000000ff) != 0) 
-	output_asm_insn (\"xor	%w2,%w0\", operands);
-      if ((i & 0x0000ff00) != 0) 
-	output_asm_insn (\"xor	%x2,%x0\", operands);
-      if ((i & 0x00ff0000) != 0) 
-	output_asm_insn (\"xor	%y2,%y0\", operands);
-      if ((i & 0xff000000) != 0) 
-	output_asm_insn (\"xor	%z2,%z0\", operands);
-      return \"\";
-    }
-  if (TARGET_H8300H || TARGET_H8300S)
-    return \"xor.l	%S2,%S0\";
-  return \"xor	%w2,%w0\;xor	%x2,%x0\;xor	%y2,%y0\;xor	%z2,%z0\;\";
-}"
-  [(set_attr "length" "2,8")
-   (set_attr "cc" "clobber,clobber")])
-
-;; ----------------------------------------------------------------------
-;; NEGATION INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "negqi2"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(neg:QI (match_operand:QI 1 "general_operand" "0")))]
-  ""
-  "neg	%X0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-(define_expand "neghi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
-  ""
-  "
-{
-  if (TARGET_H8300)
-    {
-      emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
-      DONE;
-    }
-}")
-
-(define_expand "neghi2_h8300"
-  [(set (match_dup 2)
-	(not:HI (match_operand:HI 1 "register_operand" "r")))
-   (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
-   (set (match_operand:HI 0 "register_operand" "=r")
-	(match_dup 2))]
-  ""
-  "{ operands[2] = gen_reg_rtx (HImode); }")
-
-(define_insn "neghi2_h8300h"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "neg	%T0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-(define_expand "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
-  ""
-  "
-{
-  if (TARGET_H8300)
-    {
-      emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
-      DONE;
-    }
-}")
-
-(define_expand "negsi2_h8300"
-  [(set (match_dup 2)
-	(not:SI (match_operand:SI 1 "register_operand" "r")))
-   (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(match_dup 2))]
-  ""
-  "{ operands[2] = gen_reg_rtx(SImode); }")
-
-(define_insn "negsi2_h8300h"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "neg	%S0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-;; ----------------------------------------------------------------------
-;; NOT INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(not:QI (match_operand:QI 1 "general_operand" "0")))]
-  ""
-  "not	%X0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_znv")])
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(not:HI (match_operand:HI 1 "general_operand" "0")))]
-  ""
-  "*
-{
-  if (TARGET_H8300)
-    return \"not	%s0\;not	%t0\";
-  else
-    return \"not	%T0\";
-}"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 4)
-		      (const_int 2)))])
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operand:SI 1 "general_operand" "0")))]
-  ""
-  "*
-{
-  if (TARGET_H8300)
-    return \"not	%w0\;not	%x0\;not	%y0\;not	%z0\";
-  else
-    return \"not	%S0\";
-}"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 8)
-		      (const_int 2)))])
-			
-
-;; ----------------------------------------------------------------------
-;; JUMP INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; Conditional jump instructions
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_insn "branch_true"
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
-      && (GET_CODE (operands[1]) == GT
-          || GET_CODE (operands[1]) == GE
-          || GET_CODE (operands[1]) == LE
-          || GET_CODE (operands[1]) == LT))
-    {
-      cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
-      return 0;
-    }
-
-  if (get_attr_length (insn) == 2) 
-    return \"b%j1	%l0\";
-  else if (get_attr_length (insn) == 4) 
-    return \"b%j1	%l0:16\";
-  else
-    return \"b%k1	.Lh8BR%=\;jmp	@%l0\\n.Lh8BR%=:\";
-}" 
- [(set_attr "type" "branch")
-   (set_attr "cc" "none")])
-
-(define_insn "branch_false"
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
-      && (GET_CODE (operands[1]) == GT
-          || GET_CODE (operands[1]) == GE
-          || GET_CODE (operands[1]) == LE
-          || GET_CODE (operands[1]) == LT))
-    {
-      cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
-      return 0;
-    }
-
-  if (get_attr_length (insn) == 2) 
-    return \"b%k1	%l0\";
-  else if (get_attr_length (insn) == 4) 
-    return \"b%k1	%l0:16\";
-  else
-    return \"b%j1	.Lh8BR%=\;jmp	@%l0\\n.Lh8BR%=:\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "cc" "none")])
-
-;; Unconditional and other jump instructions.
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "*
-{
-  if (get_attr_length (insn) == 2)
-    return \"bra	%l0\";
-  else if (get_attr_length (insn) == 4)
-    return \"bra	%l0:16\";
-  else
-    return \"jmp	@%l0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "cc" "none")])
-
-;; This is a define expand, because pointers may be either 16 or 32 bits.
-
-(define_expand "tablejump"
-  [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
-	      (use (label_ref (match_operand 1 "" "")))])]
-  ""
-  "")
-
-(define_insn "tablejump_h8300"
-  [(set (pc) (match_operand:HI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  "TARGET_H8300"
-  "jmp	@%0"
-  [(set_attr "cc" "none")
-   (set_attr "length" "2")])
-
-(define_insn "tablejump_h8300h"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "jmp	@%0"
-  [(set_attr "cc" "none")
-   (set_attr "length" "2")])
-
-;; This is a define expand, because pointers may be either 16 or 32 bits.
-
-(define_expand "indirect_jump"
-  [(set (pc) (match_operand 0 "jump_address_operand" ""))]
-  ""
-  "")
-
-(define_insn "indirect_jump_h8300"
-  [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
-  "TARGET_H8300"
-  "jmp	@%0"
-  [(set_attr "cc" "none")
-   (set_attr "length" "2")])
-
-(define_insn "indirect_jump_h8300h"
-  [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "jmp @%0"
-  [(set_attr "cc" "none")
-   (set_attr "length" "2")])
-
-;; Call subroutine with no return value.
-
-;; ??? Even though we use HImode here, this works for the 300h.
-
-(define_insn "call"
-  [(call (match_operand:QI 0 "call_insn_operand" "or")
-	 (match_operand:HI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
-      && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
-    return \"jsr\\t\@%0:8\";
-  else
-    return \"jsr\\t%0\";
-}"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-     (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
-		   (const_int 4)
-		   (const_int 8)))])
-
-;; Call subroutine, returning value in operand 0
-;; (which must be a hard register).
-
-;; ??? Even though we use HImode here, this works on the 300h.
-
-(define_insn "call_value"
-  [(set (match_operand 0 "" "=r")
-	(call (match_operand:QI 1 "call_insn_operand" "or")
-	      (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
-      && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
-    return \"jsr\\t\@%1:8\";
-  else
-    return \"jsr\\t%1\";
-}"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-     (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
-		   (const_int 4)
-		   (const_int 8)))])
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-  [(set_attr "cc" "none")
-   (set_attr "length" "2")])
-
-;; ----------------------------------------------------------------------
-;; EXTEND INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
-  ""
-  "@
-  mov.b	#0,%t0
-  mov.b	%R1,%s0\;mov.b	#0,%t0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "clobber,clobber")])
-
-;; The compiler can synthesize a 300H variant of this which is
-;; just as efficient as one that we'd create
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300"
-  "@
-  mov.b	#0,%x0\;sub.w %e0,%e0
-  mov.b	%R1,%w0\;mov.b	#0,%x0\;sub.w %e0,%e0"
-  [(set_attr "length" "4,6")
-   (set_attr "cc" "clobber,clobber")])
-
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:HI 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_H8300
-      && GET_CODE (operands[1]) != CONST_INT
-      && !optimize)
-    {
-      emit_insn (gen_zero_extendhisi2_h8300 (operands[0], operands[1]));
-      DONE;
-    }
-}")
-
-;; This is used when not optimizing.  It avoids severe code explosion
-;; due to poor register allocation.
-(define_expand "zero_extendhisi2_h8300"
-  [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
-   (set (reg:SI 0) (zero_extend:SI (reg:HI 1)))
-   (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
-  "TARGET_H8300"
-  "")
-
-;; %e prints the high part of a CONST_INT, not the low part.  Arggh.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
-  "TARGET_H8300"
-  "@
-  sub.w	%e0,%e0
-  mov.w %f1,%f0\;sub.w %e0,%e0
-  mov.w %e1,%f0\;sub.w %e0,%e0"
-  [(set_attr "length" "2,4,4")
-   (set_attr "cc" "clobber,clobber,clobber")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "@
-  extu.l	%S0
-  mov.w	%T1,%T0\;extu.l	%S0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "set_znv,set_znv")])
-
-(define_expand "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(sign_extend:HI (match_operand:QI 1 "general_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300"
-  "@
-  bld	#7,%s0\;subx	%t0,%t0
-  mov.b	%R1,%s0\;bld	#7,%s0\;subx	%t0,%t0"
-  [(set_attr "length" "4,6")
-   (set_attr "cc" "clobber,clobber")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "@
-  exts.w	%T0
-  mov.b	%R1,%s0\;exts.w	%T0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "set_znv,set_znv")])
-
-;; The compiler can synthesize a 300H variant of this which is
-;; just as efficient as one that we'd create
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300"
-  "@
-  bld	#7,%w0\;subx	%x0,%x0\;subx	%y0,%y0\;subx	%z0,%z0
-  mov.b %R1,%w0\;bld	#7,%w0\;subx	%x0,%x0\;subx	%y0,%y0\;subx	%z0,%z0"
-  [(set_attr "length" "8,10")
-   (set_attr "cc" "clobber,clobber")])
-
-(define_expand "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI (match_operand:HI 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_H8300
-      && GET_CODE (operands[1]) != CONST_INT
-      && !optimize)
-    {
-      emit_insn (gen_extendhisi2_h8300 (operands[0], operands[1]));
-      DONE;
-    }
-}")
-
-;; This is used when not optimizing.  It avoids severe code explosion
-;; due to poor register allocation.
-(define_expand "extendhisi2_h8300"
-  [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
-   (set (reg:SI 0) (sign_extend:SI (reg:HI 1)))
-   (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
-  "TARGET_H8300"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300"
-  "@
-  bld	#7,%x0\;subx	%y0,%y0\;subx	%z0,%z0
-  mov.w	%T1,%f0\;bld	#7,%x0\;subx	%y0,%y0\;subx	%z0,%z0"
-  [(set_attr "length" "6,8")
-   (set_attr "cc" "clobber,clobber")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300H || TARGET_H8300S"
-  "@
-  exts.l	%S0
-  mov.w	%T1,%T0\;exts.l	%S0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "set_znv,set_znv")])
-
-;; ----------------------------------------------------------------------
-;; SHIFTS
-;; ----------------------------------------------------------------------
-;;
-;; We make some attempt to provide real efficient shifting.  One example is
-;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
-;; reg and moving 0 into the former reg.
-;;
-;; We also try to achieve this in a uniform way.  IE: We don't try to achieve
-;; this in both rtl and at insn emit time.  Ideally, we'd use rtl as that would
-;; give the optimizer more cracks at the code.  However, we wish to do things
-;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
-;; There is rtl to handle this (rotate + and), but the h8/300 doesn't handle
-;; 16 bit rotates.  Also, if we emit complicated rtl, combine may not be able
-;; to detect cases it can optimize.
-;;
-;; For these and other fuzzy reasons, I've decided to go the less pretty but
-;; easier "do it at insn emit time" route.
-
-;; QI BIT SHIFTS
-
-(define_expand "ashlqi3"
-  [(set (match_operand:QI 0 "register_operand" "")
-	(ashift:QI (match_operand:QI 1 "register_operand" "")
-		   (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;")
-
-(define_expand "ashrqi3"
-  [(set (match_operand:QI 0 "register_operand" "")
-	(ashiftrt:QI (match_operand:QI 1 "register_operand" "")
-		     (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;")
-
-(define_expand "lshrqi3"
-  [(set (match_operand:QI 0 "register_operand" "")
-	(lshiftrt:QI (match_operand:QI 1 "register_operand" "")
-		     (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r,r")
-	(match_operator:QI 3 "nshift_operator" 
-			[ (match_operand:QI 1 "register_operand" "0,0")
-			  (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
-   (clobber (match_scratch:QI 4 "=X,&r"))]
-  ""
-  "* return emit_a_shift (insn, operands);"
-  [(set_attr "length" "20")
-   (set_attr "cc" "clobber")])
-
-;; HI BIT SHIFTS
-
-(define_expand "ashlhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
-		   (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;")
-
-(define_expand "lshrhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(lshiftrt:HI (match_operand:HI 1 "general_operand" "")
-		     (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;")
-
-(define_expand "ashrhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(ashiftrt:HI (match_operand:HI 1 "register_operand" "")
-		     (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(match_operator:HI 3 "nshift_operator" 
-			[ (match_operand:HI 1 "register_operand" "0,0")
-			  (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
-   (clobber (match_scratch:QI 4 "=X,&r"))]
-  ""
-  "* return emit_a_shift (insn, operands);"
-  [(set_attr "length" "20")
-   (set_attr "cc" "clobber")])
-
-;;  SI BIT SHIFTS
-
-(define_expand "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashift:SI
-	 (match_operand:SI 1 "general_operand" "")
-	 (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;")
-
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lshiftrt:SI
-	 (match_operand:SI 1 "general_operand" "")
-	 (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;")
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:SI
-	 (match_operand:SI 1 "general_operand" "")
-	 (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(match_operator:SI 3 "nshift_operator" 
-			[ (match_operand:SI 1 "register_operand" "0,0")
-			  (match_operand:QI 2 "nonmemory_operand" "K,rn")]))
-   (clobber (match_scratch:QI 4 "=X,&r"))]
-  ""
-  "* return emit_a_shift (insn, operands);"
-  [(set_attr "length" "20")
-   (set_attr "cc" "clobber")])
-
-;; -----------------------------------------------------------------
-;; BIT FIELDS
-;; -----------------------------------------------------------------
-;; The H8/300 has given 1/8th of its opcode space to bitfield
-;; instructions so let's use them as well as we can.
-
-;; You'll never believe all these patterns perform one basic action --
-;; load a bit from the source, optionally invert the bit, then store it
-;; in the destination (which is known to be zero)..  
-;;
-;; Combine obviously need some work to better identify this situation and
-;; canonicalize the form better.
-
-;; 
-;; Normal loads with a 16bit destination.
-;; 
-;; Yes, both cases are needed.
-;;
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-	(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
-			 (const_int 1)
-			 (match_operand:HI 2 "immediate_operand" "n")))]
-  ""
-  "sub.w	%0,%0\;bld	%Z2,%Y1\;bst	#0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "6")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-	(subreg:HI (zero_extract:SI
-		     (match_operand:HI 1 "register_operand" "r")
-		     (const_int 1)
-		     (match_operand:HI 2 "immediate_operand" "n")) 1))]
-  ""
-  "sub.w	%0,%0\;bld	%Z2,%Y1\;bst	#0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "6")])
-
-;; 
-;; Inverted loads with a 16bit destination.
-;; 
-;; Yes, all four cases are needed.
-;;
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-	(zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
-				 (match_operand:HI 3 "p_operand" "P"))
-			 (const_int 1)
-			 (match_operand:HI 2 "const_int_operand" "n")))]
-  "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
-  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-	(and:HI (not:HI 
-		  (lshiftrt:HI
-		    (match_operand:HI 1 "bit_operand" "Ur")
-		    (match_operand:HI 2 "const_int_operand" "n")))
-		(const_int 1)))]
-  ""
-  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-	(and:HI (not:HI 
-		  (subreg:HI 
-		    (lshiftrt:SI
-		      (match_operand:SI 1 "register_operand" "Ur")
-		      (match_operand:SI 2 "const_int_operand" "n")) 1))
-		(const_int 1)))]
-  "INTVAL (operands[2]) < 16"
-  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-	(and:HI (not:HI 
-		  (subreg:HI 
-		    (lshiftrt:SI
-		      (match_operand:SI 1 "bit_operand" "Ur")
-		      (match_operand:SI 2 "const_int_operand" "n")) 0))
-		(const_int 1)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-   && INTVAL (operands[2]) < 16"
-  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
-
-;; 
-;; Normal loads with a 32bit destination.
-;; 
-;; Yes, all three cases are needed.
-;;
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(zero_extract:SI (match_operand:HI 1 "register_operand" "r")
-			 (const_int 1)
-			 (match_operand:HI 2 "const_int_operand" "n")))]
-  ""
-  "* return output_simode_bld (0, 0, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (zero_extend:SI 
-		   (lshiftrt:QI
-		     (match_operand:QI 1 "bit_operand" "Ur")
-		     (match_operand:QI 2 "const_int_operand" "n")))
-		(const_int 1)))]
-  ""
-  "* return output_simode_bld (0, 0, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (zero_extend:SI 
-		   (lshiftrt:HI
-		      (match_operand:HI 1 "bit_operand" "Ur")
-		      (match_operand:HI 2 "const_int_operand" "n")))
-		(const_int 1)))]
-  ""
-  "* return output_simode_bld (0, 0, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-
-;; 
-;; Inverted loads with a 32bit destination.
-;; 
-;; Yes, all seven cases are needed.
-;;
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (not:SI
-		  (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
-		(match_operand:SI 2 "p_operand" "P")))]
-  ""
-  "* return output_simode_bld (1, 1, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (not:SI
-		  (zero_extend:SI
-		    (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
-				 (match_operand:HI 2 "const_int_operand" "n"))))
-		(const_int 1)))]
-  ""
-  "* return output_simode_bld (1, 0, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (not:SI
-		  (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
-		(match_operand:SI 2 "p_operand" "P")))]
-  ""
-  "* return output_simode_bld (1, 1, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (not:SI
-		  (zero_extend:SI
-		    (lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
-				 (match_operand:QI 2 "const_int_operand" "n"))))
-		(const_int 1)))]
-  ""
-  "* return output_simode_bld (1, 0, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (not:SI
-		  (subreg:SI 
-		     (lshiftrt:HI
-			(match_operand:HI 1 "bit_operand" "Ur")
-			(match_operand:HI 2 "const_int_operand" "n")) 0))
-		(const_int 1)))]
-  "1"
-  "* return output_simode_bld (1, 0, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(and:SI (not:SI
-		  (subreg:SI 
-		     (lshiftrt:QI
-			(match_operand:QI 1 "bit_operand" "Ur")
-			(match_operand:QI 2 "const_int_operand" "n")) 0))
-		(const_int 1)))]
-  "1"
-  "* return output_simode_bld (1, 0, operands);"
-  [(set_attr "cc" "clobber")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
-			  (const_int 0))
-		      (const_int 10)
-		      (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
-				 (match_operand:HI 3 "p_operand" "P"))
-			 (const_int 1)
-			 (match_operand:HI 2 "const_int_operand" "n")))]
-  "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
-  "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "8")])
-
-(define_expand "insv"
-  [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
-			 (match_operand:HI 1 "general_operand" "")
-			 (match_operand:HI 2 "general_operand" ""))
-	(match_operand:HI 3 "general_operand" ""))]
-  "TARGET_H8300"
-  "
-{
-  /* We only have single bit bitfield instructions.  */
-  if (INTVAL (operands[1]) != 1)
-    FAIL;
-
-  /* For now, we don't allow memory operands.  */
-  if (GET_CODE (operands[0]) == MEM
-      || GET_CODE (operands[3]) == MEM)
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
-			 (const_int 1)
-			 (match_operand:HI 1 "immediate_operand" "n"))
-	(match_operand:HI 2 "register_operand" "r"))]
-  ""
-  "bld	#0,%R2\;bst	%Z1,%Y0 ; i1"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "4")])
-
-(define_expand "extzv"
-  [(set (match_operand:HI 0 "register_operand" "") 
-	(zero_extract:HI (match_operand:HI 1 "bit_operand" "")
-			 (match_operand:HI 2 "general_operand" "")
-			 (match_operand:HI 3 "general_operand" "")))]
-  "TARGET_H8300"
-  "
-{
-  /* We only have single bit bitfield instructions.  */
-  if (INTVAL (operands[2]) != 1)
-    FAIL;
-
-  /* For now, we don't allow memory operands.  */
-  if (GET_CODE (operands[1]) == MEM)
-    FAIL;
-}")
-
-;; BAND, BOR, and BXOR patterns
-
-(define_insn ""
-  [(set (match_operand:HI 0 "bit_operand" "=Ur")
-	(match_operator:HI 4 "bit_operator"
-	   [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
-			     (const_int 1)
-			     (match_operand:HI 2 "immediate_operand" "n"))
-	    (match_operand:HI 3 "bit_operand" "0")]))]
-  ""
-  "bld	%Z2,%Y1\;%b4	#0,%R0\;bst	#0,%R0; bl1"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "6")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "bit_operand" "=Ur")
-	(match_operator:HI 5 "bit_operator"
-	   [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
-			     (const_int 1)
-			     (match_operand:HI 2 "immediate_operand" "n"))
-	    (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
-			     (const_int 1)
-			     (match_operand:HI 4 "immediate_operand" "n"))]))]
-  ""
-  "bld	%Z2,%Y1\;%b5	%Z4,%Y3\;bst	#0,%R0; bl3"
-  [(set_attr "cc" "clobber")
-   (set_attr "length" "6")])
-
-
-;; ----------------------------------------------
-;; Peepholes go at the end.
-;; ----------------------------------------------
-
-;; Notice a move which could be post incremented.
-
-(define_peephole 
-  [(set (match_operand:QI 0 "register_operand" "")
-	(mem:QI (match_operand:HI 1 "register_operand" "")))
-   (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))]
-  "REGNO(operands[1]) != REGNO(operands[0])"
-  "mov.b	@%T1+,%X0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_znv")])
-
-(define_peephole 
-  [(set (match_operand:HI 0 "register_operand" "")
-	(mem:HI (match_operand:HI 1 "register_operand" "")))
-   (set (match_dup 1) (plus:HI (match_dup 1) (const_int 2)))]
-  "REGNO(operands[1]) != REGNO(operands[0])"
-  "mov.w	@%T1+,%T0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_znv")])
-
-;; Notice a move which could be predecremented.
-
-(define_peephole 
-  [(set (match_operand:HI 1 "register_operand" "")
-	(plus:HI (match_dup 1) (const_int -1)))
-   (set (mem:QI (match_dup 1))
-		(match_operand:QI 0 "register_operand" ""))]
-  "REGNO(operands[1]) != REGNO(operands[0])"
-  "mov.b	%X0,@-%T1"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_znv")])
-
-(define_peephole 
-  [(set (match_operand:HI 1 "register_operand" "")
-	(plus:HI (match_dup 1) (const_int -1)))
-   (set (mem:HI (match_dup 1))
-		(match_operand:HI 0 "register_operand" ""))]
-  "REGNO(operands[1]) != REGNO(operands[0])"
-  "mov.w	%T0,@-%T1"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_znv")])
-
diff --git a/gcc/config/h8300/lib1funcs.asm b/gcc/config/h8300/lib1funcs.asm
deleted file mode 100755
index 8b6066e..0000000
--- a/gcc/config/h8300/lib1funcs.asm
+++ /dev/null
@@ -1,781 +0,0 @@
-;; libgcc1 routines for the Hitachi h8/300 cpu.
-;; Contributed by Steve Chamberlain.
-;; sac@cygnus.com
-
-/* Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with other files,
-   some of which are compiled with GCC, to produce an executable,
-   this library does not by itself cause the resulting executable
-   to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-/* Assembler register definitions.  */
-
-#define A0 r0
-#define A0L r0l
-#define A0H r0h
-
-#define A1 r1
-#define A1L r1l
-#define A1H r1h
-
-#define A2 r2
-#define A2L r2l
-#define A2H r2h
-
-#define A3 r3
-#define A3L r3l
-#define A3H r3h
-
-#define S0 r4
-#define S0L r4l
-#define S0H r4h
-
-#define S1 r5
-#define S1L r5l
-#define S1H r5h
-
-#define S2 r6
-#define S2L r6l
-#define S2H r6h
-
-#ifdef __H8300__
-#define MOVP	mov.w	/* pointers are 16 bits */
-#define ADDP	add.w
-#define CMPP	cmp.w
-#define PUSHP	push
-#define POPP	pop
-
-#define A0P	r0
-#define A1P	r1
-#define A2P	r2
-#define A3P	r3
-#define S0P	r4
-#define S1P	r5
-#define S2P	r6
-#endif
-
-#if defined (__H8300H__) || defined (__H8300S__)
-#define MOVP	mov.l	/* pointers are 32 bits */
-#define ADDP	add.l
-#define CMPP	cmp.l
-#define PUSHP	push.l
-#define POPP	pop.l
-
-#define A0P	er0
-#define A1P	er1
-#define A2P	er2
-#define A3P	er3
-#define S0P	er4
-#define S1P	er5
-#define S2P	er6
-
-#define A0E	e0
-#define A1E	e1
-#define A2E	e2
-#define A3E	e3
-#endif
-
-#ifdef L_cmpsi2
-#ifdef __H8300__
-	.section .text
-	.align 2
-	.global ___cmpsi2
-___cmpsi2:
-	cmp.w	A2,A0
-	bne	.L2
-	cmp.w	A3,A1
-	bne	.L2
-	mov.w	#1,A0
-	rts
-.L2:
-	cmp.w	A0,A2
-	bgt	.L4
-	bne	.L3
-	cmp.w	A1,A3
-	bls	.L3
-.L4:
-	sub.w	A0,A0
-	rts
-.L3:
-	mov.w	#2,A0
-.L5:
-	rts
-	.end
-#endif
-#endif /* L_cmpsi2 */
-
-#ifdef L_ucmpsi2
-#ifdef __H8300__
-	.section .text
-	.align 2
-	.global ___ucmpsi2
-___ucmpsi2:
-	cmp.w	A2,A0
-	bne	.L2
-	cmp.w	A3,A1
-	bne	.L2
-	mov.w	#1,A0
-	rts
-.L2:
-	cmp.w	A0,A2
-	bhi	.L4
-	bne	.L3
-	cmp.w	A1,A3
-	bls	.L3
-.L4:
-	sub.w	A0,A0
-	rts
-.L3:
-	mov.w	#2,A0
-.L5:
-	rts
-	.end
-#endif
-#endif /* L_ucmpsi2 */
-
-#ifdef L_divhi3
-
-;; HImode divides for the H8/300.
-;; We bunch all of this into one object file since there are several
-;; "supporting routines".
-
-; general purpose normalize routine
-; 
-; divisor in A0
-; dividend in A1
-; turns both into +ve numbers, and leaves what the answer sign
-; should be in A2L
-
-#ifdef __H8300__
-	.section .text
-	.align 2
-divnorm:
-	mov.b	#0x0,A2L
-	or	A0H,A0H		; is divisor > 0
-	bge	_lab1			
-	not	A0H		; no - then make it +ve
-	not	A0L
-	adds	#1,A0			
-	xor	#0x1,A2L	; and remember that in A2L
-_lab1:	or	A1H,A1H	; look at dividend
-	bge	_lab2		
-	not	A1H		; it is -ve, make it positive
-	not	A1L
-	adds	#1,A1
-	xor	#0x1,A2L; and toggle sign of result
-_lab2:	rts
-;; Basically the same, except that the sign of the divisor determines
-;; the sign.
-modnorm:
-	mov.b	#0x0,A2L
-	or	A0H,A0H		; is divisor > 0
-	bge	_lab7			
-	not	A0H		; no - then make it +ve
-	not	A0L
-	adds	#1,A0			
-	xor	#0x1,A2L	; and remember that in A2L
-_lab7:	or	A1H,A1H	; look at dividend
-	bge	_lab8		
-	not	A1H		; it is -ve, make it positive
-	not	A1L
-	adds	#1,A1
-_lab8:	rts
-
-; A0=A0/A1 signed
-
-	.global	___divhi3
-___divhi3:
-	bsr	divnorm
-	bsr	___udivhi3
-negans:	or	A2L,A2L	; should answer be negative ?
-	beq	_lab4
-	not	A0H	; yes, so make it so
-	not	A0L
-	adds	#1,A0
-_lab4:	rts	
-
-; A0=A0%A1 signed
-
-	.global	___modhi3
-___modhi3:
-	bsr	modnorm
-	bsr	___udivhi3
-	mov	A3,A0
-	bra	negans
-
-; A0=A0%A1 unsigned
-
-	.global	___umodhi3
-___umodhi3:
-	bsr	___udivhi3
-	mov	A3,A0
-	rts
-
-; A0=A0/A1 unsigned
-; A3=A0%A1 unsigned
-; A2H trashed
-; D high 8 bits of denom
-; d low 8 bits of denom
-; N high 8 bits of num
-; n low 8 bits of num
-; M high 8 bits of mod
-; m low 8 bits of mod
-; Q high 8 bits of quot
-; q low 8 bits of quot
-; P preserve
-
-; The h8 only has a 16/8 bit divide, so we look at the incoming and
-; see how to partition up the expression.
-
-	.global	___udivhi3
-___udivhi3:
-				; A0 A1 A2 A3 
-				; Nn Dd       P
-	sub.w	A3,A3		; Nn Dd xP 00 
-	or	A1H,A1H		 
-	bne	divlongway
-	or	A0H,A0H		
-	beq	_lab6		
-
-; we know that D == 0 and N is != 0
-	mov.b	A0H,A3L		; Nn Dd xP 0N
-	divxu	A1L,A3		;          MQ
-	mov.b	A3L,A0H	 	; Q
-; dealt with N, do n
-_lab6:	mov.b	A0L,A3L		;           n
-	divxu	A1L,A3		;          mq
-	mov.b	A3L,A0L		; Qq
-	mov.b	A3H,A3L         ;           m
-	mov.b	#0x0,A3H	; Qq       0m
-	rts	
-
-; D != 0 - which means the denominator is
-;          loop around to get the result.
-
-divlongway:
-	mov.b	A0H,A3L		; Nn Dd xP 0N
-	mov.b	#0x0,A0H	; high byte of answer has to be zero
-	mov.b	#0x8,A2H	;       8
-div8:	add.b	A0L,A0L		; n*=2
-	rotxl	A3L		; Make remainder bigger
-	rotxl	A3H		
-	sub.w	A1,A3		; Q-=N
-	bhs	setbit		; set a bit ?
-	add.w	A1,A3		;  no : too far , Q+=N
-
-	dec	A2H		
-	bne	div8		; next bit	
-	rts	
-
-setbit:	inc	A0L		; do insert bit
-	dec	A2H		
-	bne	div8		; next bit	
-	rts	
-
-#endif /* __H8300__ */
-#endif /* L_divhi3 */
-
-#ifdef L_divsi3
-
-;; 4 byte integer divides for the H8/300.
-;;
-;; We have one routine which does all the work and lots of 
-;; little ones which prepare the args and massage the sign.
-;; We bunch all of this into one object file since there are several
-;; "supporting routines".
-
-#ifdef __H8300H__
-	.h8300h
-#endif
-
-#ifdef __H8300S__
-	.h8300s
-#endif
-
-	.section .text
-	.align 2
-
-; Put abs SIs into r0/r1 and r2/r3, and leave a 1 in r6l with sign of rest.
-; This function is here to keep branch displacements small.
-
-#ifdef __H8300__
-
-divnorm:
-	mov.b	#0,S2L		; keep the sign in S2
-	mov.b	A0H,A0H		; is the numerator -ve
-	bge	postive
-
-	; negate arg
-	not	A0H
-	not	A1H
-	not	A0L
-	not	A1L
-
-	add	#1,A1L
-	addx	#0,A1H
-	addx	#0,A0L
-	addx	#0,A0H
-
-	mov.b	#1,S2L		; the sign will be -ve
-postive:
-	mov.b	A2H,A2H		; is the denominator -ve
-	bge	postive2
-	not	A2L		
-	not	A2H
-	not	A3L
-	not	A3H
-	add.b	#1,A3L	
-	addx	#0,A3H
-	addx	#0,A2L
-	addx	#0,A2H
-	xor	#1,S2L		; toggle result sign
-postive2:
-	rts
-
-;; Basically the same, except that the sign of the divisor determines
-;; the sign.
-modnorm:
-	mov.b	#0,S2L		; keep the sign in S2
-	mov.b	A0H,A0H		; is the numerator -ve
-	bge	mpostive
-
-	; negate arg
-	not	A0H
-	not	A1H
-	not	A0L
-	not	A1L
-
-	add	#1,A1L
-	addx	#0,A1H
-	addx	#0,A0L
-	addx	#0,A0H
-
-	mov.b	#1,S2L		; the sign will be -ve
-mpostive:
-	mov.b	A2H,A2H		; is the denominator -ve
-	bge	mpostive2
-	not	A2L		
-	not	A2H
-	not	A3L
-	not	A3H
-	add.b	#1,A3L	
-	addx	#0,A3H
-	addx	#0,A2L
-	addx	#0,A2H
-mpostive2:
-	rts
-
-#else /* __H8300H__ */
-
-divnorm:
-	mov.b	#0,S2L		; keep the sign in S2
-	mov.l	A0P,A0P		; is the numerator -ve
-	bge	postive
-
-	neg.l	A0P		; negate arg
-	mov.b	#1,S2L		; the sign will be -ve
-
-postive:
-	mov.l	A1P,A1P		; is the denominator -ve
-	bge	postive2
-
-	neg.l	A1P		; negate arg
-	xor.b	#1,S2L		; toggle result sign
-
-postive2:
-	rts
-
-;; Basically the same, except that the sign of the divisor determines
-;; the sign.
-modnorm:
-	mov.b	#0,S2L		; keep the sign in S2
-	mov.l	A0P,A0P		; is the numerator -ve
-	bge	mpostive
-
-	neg.l	A0P		; negate arg
-	mov.b	#1,S2L		; the sign will be -ve
-
-mpostive:
-	mov.l	A1P,A1P		; is the denominator -ve
-	bge	mpostive2
-
-	neg.l	A1P		; negate arg
-
-mpostive2:
-	rts
-
-#endif
-
-; numerator in A0/A1
-; denominator in A2/A3
-	.global	___modsi3
-___modsi3:
-	PUSHP	S2P		
-	PUSHP	S0P
-	PUSHP	S1P
-
-	bsr	modnorm
-	bsr	divmodsi4
-#ifdef __H8300__
-	mov	S0,A0
-	mov	S1,A1
-#else
-	mov.l	S0P,A0P
-#endif
-	bra	exitdiv
-
-	.global	___udivsi3
-___udivsi3:
-	PUSHP	S2P
-	PUSHP	S0P
-	PUSHP	S1P
-	mov.b	#0,S2L	; keep sign low
-	bsr	divmodsi4
-	bra	exitdiv
-
-	.global	___umodsi3
-___umodsi3:
-	PUSHP	S2P
-	PUSHP	S0P
-	PUSHP	S1P
-	mov.b	#0,S2L	; keep sign low
-	bsr	divmodsi4
-#ifdef __H8300__
-	mov	S0,A0
-	mov	S1,A1
-#else
-	mov.l	S0P,A0P
-#endif
-	bra	exitdiv
-	
-	.global	___divsi3
-___divsi3:
-	PUSHP	S2P
-	PUSHP	S0P
-	PUSHP	S1P
-	jsr	divnorm
-	jsr	divmodsi4
-
-	; examine what the sign should be
-exitdiv:
-	POPP	S1P
-	POPP	S0P
-
-	or	S2L,S2L
-	beq	reti
-	
-	; should be -ve
-#ifdef __H8300__
-	not	A0H
-	not	A1H
-	not	A0L
-	not	A1L
-
-	add	#1,A1L
-	addx	#0,A1H
-	addx	#0,A0L
-	addx	#0,A0H
-#else /* __H8300H__ */
-	neg.l	A0P
-#endif
-
-reti:
-	POPP	S2P
-	rts	
-
-	; takes A0/A1 numerator (A0P for 300h)
-	; A2/A3 denominator (A1P for 300h)
-	; returns A0/A1 quotient (A0P for 300h)
-	; S0/S1 remainder (S0P for 300h)
-	; trashes S2
-
-#ifdef __H8300__
-
-divmodsi4:
-        sub.w	S0,S0		; zero play area
-        mov.w	S0,S1
-        mov.b	A2H,S2H
-        or	A2L,S2H
-        or	A3H,S2H
-        bne	DenHighZero
-        mov.b	A0H,A0H
-        bne	NumByte0Zero
-        mov.b	A0L,A0L
-        bne	NumByte1Zero
-        mov.b	A1H,A1H
-        bne	NumByte2Zero
-        bra	NumByte3Zero
-NumByte0Zero:
-	mov.b	A0H,S1L
-        divxu	A3L,S1
-        mov.b	S1L,A0H
-NumByte1Zero:
-	mov.b	A0L,S1L
-        divxu	A3L,S1
-        mov.b	S1L,A0L
-NumByte2Zero:
-	mov.b	A1H,S1L
-        divxu	A3L,S1
-        mov.b	S1L,A1H
-NumByte3Zero:
-	mov.b	A1L,S1L
-        divxu	A3L,S1
-        mov.b	S1L,A1L
-
-        mov.b	S1H,S1L
-        mov.b	#0x0,S1H
-        rts	
-
-; have to do the divide by shift and test
-DenHighZero:
-	mov.b	A0H,S1L
-        mov.b	A0L,A0H
-        mov.b	A1H,A0L
-        mov.b	A1L,A1H
-
-        mov.b	#0,A1L
-        mov.b	#24,S2H	; only do 24 iterations
-
-nextbit:
-	add.w	A1,A1	; double the answer guess
-        rotxl	A0L
-        rotxl	A0H
-
-        rotxl	S1L	; double remainder
-        rotxl	S1H
-        rotxl	S0L
-        rotxl	S0H
-        sub.w	A3,S1	; does it all fit
-        subx	A2L,S0L
-        subx	A2H,S0H
-        bhs	setone	 
-
-        add.w	A3,S1	; no, restore mistake
-        addx	A2L,S0L
-        addx	A2H,S0H
-
-        dec	S2H
-        bne	nextbit
-        rts	
-	
-setone:
-	inc	A1L
-        dec	S2H
-        bne	nextbit
-        rts	
-
-#else /* __H8300H__ */
-
-divmodsi4:
-	sub.l	S0P,S0P		; zero play area
-	mov.w	A1E,A1E		; denominator top word 0?
-	bne	DenHighZero
-
-	; do it the easy way, see page 107 in manual
-	mov.w	A0E,A2
-	extu.l	A2P
-	divxu.w	A1,A2P
-	mov.w	A2E,A0E
-	divxu.w	A1,A0P
-	mov.w	A0E,S0
-	mov.w	A2,A0E
-	extu.l	S0P
-	rts
-
-DenHighZero:
-	mov.w	A0E,A2
-	mov.b	A2H,S0L
-	mov.b	A2L,A2H
-	mov.b	A0H,A2L
-	mov.w	A2,A0E
-	mov.b	A0L,A0H
-	mov.b	#0,A0L
-	mov.b	#24,S2H		; only do 24 iterations
-
-nextbit:
-	shll.l	A0P		; double the answer guess
-	rotxl.l	S0P		; double remainder
-	sub.l	A1P,S0P		; does it all fit?
-	bhs	setone
-
-	add.l	A1P,S0P		; no, restore mistake
-	dec	S2H
-	bne	nextbit
-	rts
-
-setone:
-	inc	A0L
-	dec	S2H
-	bne	nextbit
-	rts
-
-#endif
-#endif /* L_divsi3 */
-
-#ifdef L_mulhi3
-
-;; HImode multiply.
-; The h8 only has an 8*8->16 multiply.
-; The answer is the same as:
-; 
-; product = (srca.l * srcb.l) + ((srca.h * srcb.l) + (srcb.h * srca.l)) * 256
-; (we can ignore A1.h * A0.h cause that will all off the top)
-; A0 in
-; A1 in 
-; A0 answer
-
-#ifdef __H8300__
-	.section .text
-	.align 2
-	.global	___mulhi3
-___mulhi3:
-	mov.b	A1L,A2L		; A2l gets srcb.l
-	mulxu	A0L,A2		; A2 gets first sub product 
-
-	mov.b	A0H,A3L		; prepare for
-	mulxu	A1L,A3		; second sub product
-
-	add.b	A3L,A2H		; sum first two terms
-
-	mov.b	A1H,A3L		; third sub product
-	mulxu	A0L,A3		
-
-	add.b	A3L,A2H		; almost there
-	mov.w	A2,A0		; that is
-	rts
-
-#endif
-#endif /* L_mulhi3 */
-
-#ifdef L_mulsi3
-
-;; SImode multiply.
-;; 
-;; I think that shift and add may be sufficient for this.  Using the
-;; supplied 8x8->16 would need 10 ops of 14 cycles each + overhead.  This way
-;; the inner loop uses maybe 20 cycles + overhead, but terminates
-;; quickly on small args.
-;;
-;; A0/A1 src_a
-;; A2/A3 src_b
-;;
-;;  while (a) 
-;;    {
-;;      if (a & 1)
-;;        r += b;
-;;      a >>= 1;
-;;      b <<= 1;
-;;    }
-
-	.section .text
-	.align 2
-
-#ifdef __H8300__
-
-	.global	___mulsi3
-___mulsi3:
-	PUSHP	S0P
-	PUSHP	S1P
-	PUSHP	S2P
-	
-	sub.w	S0,S0
-	sub.w	S1,S1
-	
-	; while (a)
-_top:	mov.w	A0,A0
-	bne	_more
-	mov.w	A1,A1
-	beq	_done
-_more:	; if (a & 1)
-	bld	#0,A1L
-	bcc	_nobit
-	; r += b
-	add.w	A3,S1
-	addx	A2L,S0L
-	addx	A2H,S0H
-_nobit:
-	; a >>= 1
-	shlr	A0H
-	rotxr	A0L
-	rotxr	A1H
-	rotxr	A1L
-	
-	; b <<= 1
-	add.w	A3,A3
-	addx	A2L,A2L
-	addx	A2H,A2H
-	bra 	_top
-
-_done:
-	mov.w	S0,A0	
-	mov.w	S1,A1
-	POPP	S2P
-	POPP	S1P
-	POPP	S0P
-	rts
-
-#else /* __H8300H__ */
-
-#ifdef __H8300H__
-	.h8300h
-#endif
-
-#ifdef __H8300S__
-	.h8300s
-#endif
-
-	.global	___mulsi3
-___mulsi3:
-	sub.l	A2P,A2P
-
-	; while (a)
-_top:	mov.l	A0P,A0P
-	beq	_done
-
-	; if (a & 1)
-	bld	#0,A0L
-	bcc	_nobit
-
-	; r += b
-	add.l	A1P,A2P
-
-_nobit:
-	; a >>= 1
-	shlr.l	A0P
-
-	; b <<= 1
-	shll.l	A1P
-	bra	_top
-
-_done:
-	mov.l	A2P,A0P
-	rts
-
-#endif
-#endif /* L_mulsi3 */
diff --git a/gcc/config/h8300/t-h8300 b/gcc/config/h8300/t-h8300
deleted file mode 100755
index e220048..0000000
--- a/gcc/config/h8300/t-h8300
+++ /dev/null
@@ -1,27 +0,0 @@
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = h8300/lib1funcs.asm
-LIB1ASMFUNCS = _cmpsi2 _ucmpsi2 _divhi3 _divsi3 _mulhi3 _mulsi3
-
-# We do not have DF or DI types, so fake out the libgcc2 compilation.
-TARGET_LIBGCC2_CFLAGS = -DDF=SF -DDI=SI
-
-LIB2FUNCS_EXTRA = fp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#define FLOAT_ONLY' >> fp-bit.c
-	echo '#define SMALL_MACHINE' >> fp-bit.c
-	echo '#ifdef __H8300__' >> fp-bit.c
-	echo '#define CMPtype HItype' >> fp-bit.c
-	echo '#else' >> fp-bit.c
-	echo '#define CMPtype SItype' >> fp-bit.c
-	echo '#endif' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-MULTILIB_OPTIONS = mh/ms mint32
-MULTILIB_DIRNAMES = h8300h h8300s int32
-MULTILIB_EXCEPTIONS = mint32
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
diff --git a/gcc/config/h8300/xm-h8300.h b/gcc/config/h8300/xm-h8300.h
deleted file mode 100755
index 7fde9e6..0000000
--- a/gcc/config/h8300/xm-h8300.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Configuration for GNU C-compiler for H8/300.
-   Copyright (C) 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 16
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* If compiled with GNU C, use the built-in alloca */
-#ifdef __GNUC__
-#define alloca __builtin_alloca
-#else
-#define USE_C_ALLOCA
-#endif
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
diff --git a/gcc/config/i370/i370.c b/gcc/config/i370/i370.c
deleted file mode 100755
index 5518982..0000000
--- a/gcc/config/i370/i370.c
+++ /dev/null
@@ -1,584 +0,0 @@
-/* Subroutines for insn-output.c for System/370.
-   Copyright (C) 1989, 1993, 1995, 1997 Free Software Foundation, Inc.
-   Contributed by Jan Stein (jan@cd.chalmers.se).
-   Modified for MVS C/370 by Dave Pitts (dpitts@nyx.cs.du.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include <string.h>
-#include <ctype.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#ifdef sun
-#include <sys/types.h>
-#include <ctype.h>
-#endif
-#include <time.h>
-
-
-/* Label node, this structure is used to keep track of labels on the
-   current page.  */
-typedef struct label_node
-  {
-    struct label_node *label_next;
-    int label_id;
-    int label_page;
-  }
-label_node_t;
-
-/* Is 1 when a label has been generated and the base register must be
-   reloaded.  */
-int mvs_label_emitted = 0;
-
-/* Current function starting base page.  */
-int function_base_page;
-
-/* Length of the current page code.  */
-int mvs_page_code;
-
-/* Length of the current page literals.  */
-int mvs_page_lit;
-
-/* Current function name.  */
-char *mvs_function_name = 0;
-
-/* Current function name length.  */
-int mvs_function_name_length = 0;
-
-/* Page number for multi-page functions.  */
-int mvs_page_num = 0;
-
-/* Label node list anchor.  */
-static label_node_t *label_anchor = 0;
-
-/* Label node free list anchor.  */
-static label_node_t *free_anchor = 0;
-
-/* Assembler source file descriptor.  */
-static FILE *assembler_source = 0;
-
-/* Define the length of the internal MVS function table.  */
-#define MVS_FUNCTION_TABLE_LENGTH 32
-
-/* C/370 internal function table.  These functions use non-standard linkage
-   and must handled in a special manner.  */
-static char *mvs_function_table[MVS_FUNCTION_TABLE_LENGTH] =
-{
-   "ceil",     "edc_acos", "edc_asin", "edc_ata2", "edc_atan", "edc_cos",
-   "edc_cosh", "edc_erf",  "edc_erfc", "edc_exp",  "edc_gamm", "edc_lg10",
-   "edc_log",  "edc_sin",  "edc_sinh", "edc_sqrt", "edc_tan",  "edc_tanh",
-   "fabs",     "floor",    "fmod",     "frexp",    "hypot",    "j0",
-   "j1",       "jn",       "ldexp",    "modf",     "pow",      "y0",
-   "y1",       "yn"
-};
-
-/* ASCII to EBCDIC conversion table.  */
-#if defined(TARGET_EBCDIC) && !defined(HOST_EBCDIC)
-static unsigned char ascebc[256] =
-{
- /*00  NL    SH    SX    EX    ET    NQ    AK    BL */
-     0x00, 0x01, 0x02, 0x03, 0x37, 0x2D, 0x2E, 0x2F,
- /*08  BS    HT    LF    VT    FF    CR    SO    SI */
-     0x16, 0x05, 0x15, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
- /*10  DL    D1    D2    D3    D4    NK    SN    EB */
-     0x10, 0x11, 0x12, 0x13, 0x3C, 0x3D, 0x32, 0x26,
- /*18  CN    EM    SB    EC    FS    GS    RS    US */
-     0x18, 0x19, 0x3F, 0x27, 0x1C, 0x1D, 0x1E, 0x1F,
- /*20  SP     !     "     #     $     %     &     ' */
-     0x40, 0x5A, 0x7F, 0x7B, 0x5B, 0x6C, 0x50, 0x7D,
- /*28   (     )     *     +     ,     -    .      / */
-     0x4D, 0x5D, 0x5C, 0x4E, 0x6B, 0x60, 0x4B, 0x61,
- /*30   0     1     2     3     4     5     6     7 */
-     0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
- /*38   8     9     :     ;     <     =     >     ? */
-     0xF8, 0xF9, 0x7A, 0x5E, 0x4C, 0x7E, 0x6E, 0x6F,
- /*40   @     A     B     C     D     E     F     G */
-     0x7C, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
- /*48   H     I     J     K     L     M     N     O */
-     0xC8, 0xC9, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6,
- /*50   P     Q     R     S     T     U     V     W */
-     0xD7, 0xD8, 0xD9, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6,
- /*58   X     Y     Z     [     \     ]     ^     _ */
-     0xE7, 0xE8, 0xE9, 0xAD, 0xE0, 0xBD, 0x5F, 0x6D,
- /*60   `     a     b     c     d     e     f     g */
-     0x79, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
- /*68   h     i     j     k     l     m     n     o */
-     0x88, 0x89, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96,
- /*70   p     q     r     s     t     u     v     w */
-     0x97, 0x98, 0x99, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6,
- /*78   x     y     z     {     |     }     ~    DL */
-     0xA7, 0xA8, 0xA9, 0xC0, 0x4F, 0xD0, 0xA1, 0x07,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
-     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0xFF
-};
-#endif
-
-/* EBCDIC to ASCII conversion table.  */
-#if defined(HOST_EBCDIC) && !defined(TARGET_EBCDIC)
-unsigned char ebcasc[256] =
-{
- /*00  NU    SH    SX    EX    PF    HT    LC    DL */
-     0x00, 0x01, 0x02, 0x03, 0x00, 0x09, 0x00, 0x7F,
- /*08              SM    VT    FF    CR    SO    SI */
-     0x00, 0x00, 0x00, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
- /*10  DE    D1    D2    TM    RS    NL    BS    IL */
-     0x10, 0x11, 0x12, 0x13, 0x14, 0x0A, 0x08, 0x00,
- /*18  CN    EM    CC    C1    FS    GS    RS    US */
-     0x18, 0x19, 0x00, 0x00, 0x1C, 0x1D, 0x1E, 0x1F,
- /*20  DS    SS    FS          BP    LF    EB    EC */
-     0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x17, 0x1B,
- /*28              SM    C2    EQ    AK    BL       */
-     0x00, 0x00, 0x00, 0x00, 0x05, 0x06, 0x07, 0x00,
- /*30              SY          PN    RS    UC    ET */
-     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
- /*38                    C3    D4    NK          SU */
-     0x00, 0x00, 0x00, 0x00, 0x14, 0x15, 0x00, 0x1A,
- /*40  SP                                           */
-     0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /*48                     .     <     (     +     | */
-     0x00, 0x00, 0x00, 0x2E, 0x3C, 0x28, 0x2B, 0x7C,
- /*50   &                                           */
-     0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /*58               !     $     *     )     ;     ^ */
-     0x00, 0x00, 0x21, 0x24, 0x2A, 0x29, 0x3B, 0x5E,
- /*60   -     /                                     */
-     0x2D, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /*68                     ,     %     _     >     ? */
-     0x00, 0x00, 0x00, 0x2C, 0x25, 0x5F, 0x3E, 0x3F,
- /*70                                               */
-     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /*78         `     :     #     @     '     =     " */
-     0x00, 0x60, 0x3A, 0x23, 0x40, 0x27, 0x3D, 0x22,
- /*80         a     b     c     d     e     f     g */
-     0x00, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
- /*88   h     i           {                         */
-     0x68, 0x69, 0x00, 0x7B, 0x00, 0x00, 0x00, 0x00,
- /*90         j     k     l     m     n     o     p */
-     0x00, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70,
- /*98   q     r           }                         */
-     0x71, 0x72, 0x00, 0x7D, 0x00, 0x00, 0x00, 0x00,
- /*A0         ~     s     t     u     v     w     x */
-     0x00, 0x7E, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
- /*A8   y     z                       [             */
-     0x79, 0x7A, 0x00, 0x00, 0x00, 0x5B, 0x00, 0x00,
- /*B0                                               */
-     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /*B8                                 ]             */
-     0x00, 0x00, 0x00, 0x00, 0x00, 0x5D, 0x00, 0x00,
- /*C0   {     A     B     C     D     E     F     G */
-     0x7B, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
- /*C8   H     I                                     */
-     0x48, 0x49, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /*D0   }     J     K     L     M     N     O     P */
-     0x7D, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50,
- /*D8   Q     R                                     */
-     0x51, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /*E0   \           S     T     U     V     W     X */
-     0x5C, 0x00, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
- /*E8   Y     Z                                     */
-     0x59, 0x5A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- /*F0   0     1     2     3     4     5     6     7 */
-     0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- /*F8   8     9                                     */
-     0x38, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF
-};
-#endif
-
-/* Map characters from one character set to another.
-   C is the character to be translated.  */
-
-char
-mvs_map_char (c)
-     char c;
-{
-#if defined(TARGET_EBCDIC) && !defined(HOST_EBCDIC)
-  return ascebc[c];
-#else
-#if defined(HOST_EBCDIC) && !defined(TARGET_EBCDIC)
-  return ebcasc[c];
-#else
-  return c;
-#endif
-#endif
-}
-
-/* Emit reload of base register if indicated.  This is to eliminate multiple
-   reloads when several labels are generated pointing to the same place
-   in the code.  */
-
-int
-check_label_emit (void)
-{
-  if (mvs_label_emitted)
-    {
-      mvs_label_emitted = 0;
-      mvs_page_code += 4;
-      fprintf (assembler_source, "\tL\t%d,%d(,%d)\n",
-	  BASE_REGISTER, (mvs_page_num - function_base_page) * 4,
-	  PAGE_REGISTER);
-    }
-}
-
-/* Add the label to the current page label list.  If a free element is available
-   it will be used for the new label.  Otherwise, a label element will be
-   allocated from memory.
-   ID is the label number of the label being added to the list.  */
-
-int
-mvs_add_label (id)
-     int id;
-{
-  label_node_t *lp;
-
-  if (free_anchor)
-    {
-      lp = free_anchor;
-      free_anchor = lp->label_next;
-    }
-  else
-    {
-      lp = (label_node_t *) malloc (sizeof (label_node_t));
-      if (lp == 0)
-	{
-	  fatal ("virtual memory exhausted\n");
-	  abort ();
-	}
-    }
-  lp->label_id = id;
-  lp->label_page = mvs_page_num;
-  lp->label_next = label_anchor;
-  label_anchor = lp;
-}
-
-/* Check to see if the label is in the list.  If 1 is returned then a load
-   and branch on register must be generated.
-   ID is the label number of the label being checked.  */
-
-int
-mvs_check_label (id)
-     int id;
-{
-  label_node_t *lp;
-
-  for (lp = label_anchor; lp; lp = lp->label_next)
-    {
-      if (lp->label_id == id)
-	return 1;
-    }
-  return 0;
-}
-
-/* The label list for the current page freed by linking the list onto the free
-   label element chain.  */
-
-int
-mvs_free_label (void)
-{
-  if (label_anchor)
-    {
-      if (free_anchor)
-	label_anchor->label_next = free_anchor;
-      free_anchor = label_anchor;
-    }
-  label_anchor = 0;
-}
-
-/* If the page size limit is reached a new code page is started, and the base
-   register is set to it.  This page break point is counted conservatively,
-   most literals that have the same value are collapsed by the assembler.
-   True is returned when a new page is started.
-   FILE is the assembler output file descriptor.
-   CODE is the length, in bytes, of the instruction to be emitted.
-   LIT is the length of the literal to be emitted.  */
-
-int
-mvs_check_page (file, code, lit)
-     FILE *file;
-     int code, lit;
-{
-  if (file)
-    assembler_source = file;
-
-  if (mvs_page_code + code + mvs_page_lit + lit > MAX_MVS_PAGE_LENGTH)
-    {
-      fprintf (assembler_source, "\tB\tPGE%d\n", mvs_page_num);
-      fprintf (assembler_source, "\tDS\t0F\n");
-      fprintf (assembler_source, "\tLTORG\n");
-      fprintf (assembler_source, "\tDS\t0F\n");
-      fprintf (assembler_source, "PGE%d\tEQU\t*\n", mvs_page_num);
-      fprintf (assembler_source, "\tDROP\t%d\n", BASE_REGISTER);
-      mvs_page_num++;
-      fprintf (assembler_source, "\tBALR\t%d,0\n", BASE_REGISTER);
-      fprintf (assembler_source, "PG%d\tEQU\t*\n", mvs_page_num);
-      fprintf (assembler_source, "\tUSING\t*,%d\n", BASE_REGISTER);
-      mvs_free_label ();
-      mvs_page_code = code;
-      mvs_page_lit = lit;
-      return 1;
-    }
-  mvs_page_code += code;
-  mvs_page_lit += lit;
-  return 0;
-}
-
-/* Check for C/370 runtime function, they don't use standard calling
-   conventions.  True is returned if the function is in the table.
-   NAME is the name of the current function.  */
-
-int
-mvs_function_check (name)
-     char *name;
-{
-  int lower, middle, upper;
-  int i;
-
-  lower = 0;
-  upper = MVS_FUNCTION_TABLE_LENGTH - 1;
-  while (lower <= upper)
-    {
-      middle = (lower + upper) / 2;
-      i = strcmp (name, mvs_function_table[middle]);
-      if (i == 0)
-	return 1;
-      if (i < 0)
-	upper = middle - 1;
-      else
-	lower = middle + 1;
-    }
-  return 0;
-}
-
-
-/* Return 1 if OP is a valid S operand for an RS, SI or SS type instruction.
-   OP is the current operation.
-   MODE is the current operation mode.  */
-
-int
-s_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  extern int volatile_ok;
-  register enum rtx_code code = GET_CODE (op);
-
-  if (CONSTANT_ADDRESS_P (op))
-    return 1;
-  if (mode == VOIDmode || GET_MODE (op) != mode)
-    return 0;
-  if (code == MEM)
-    {
-      register rtx x = XEXP (op, 0);
-
-      if (!volatile_ok && op->volatil)
-	return 0;
-      if (REG_P (x) && REG_OK_FOR_BASE_P (x))
-	return 1;
-      if (GET_CODE (x) == PLUS
-	  && REG_P (XEXP (x, 0)) && REG_OK_FOR_BASE_P (XEXP (x, 0))
-	  && GET_CODE (XEXP (x, 1)) == CONST_INT
-	  && (unsigned) INTVAL (XEXP (x, 1)) < 4096)
-	return 1;
-    }
-  return 0;
-}
-
-
-/* Return 1 if OP is a valid R or S operand for an RS, SI or SS type
-   instruction.
-   OP is the current operation.
-   MODE is the current operation mode.  */
-
-int
-r_or_s_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  extern int volatile_ok;
-  register enum rtx_code code = GET_CODE (op);
-
-  if (CONSTANT_ADDRESS_P (op))
-    return 1;
-  if (mode == VOIDmode || GET_MODE (op) != mode)
-    return 0;
-  if (code == REG)
-    return 1;
-  else if (code == MEM)
-    {
-      register rtx x = XEXP (op, 0);
-
-      if (!volatile_ok && op->volatil)
-	return 0;
-      if (REG_P (x) && REG_OK_FOR_BASE_P (x))
-	return 1;
-      if (GET_CODE (x) == PLUS
-	  && REG_P (XEXP (x, 0)) && REG_OK_FOR_BASE_P (XEXP (x, 0))
-	  && GET_CODE (XEXP (x, 1)) == CONST_INT
-	  && (unsigned) INTVAL (XEXP (x, 1)) < 4096)
-	return 1;
-    }
-  return 0;
-}
-
-
-/* Return 1 if the next instruction is an unsigned jump instruction.
-   INSN is the current instruction.  */
-
-unsigned_jump_follows_p (insn)
-     register rtx insn;
-{
-  insn = NEXT_INSN (insn);
-  if (GET_CODE (insn) != JUMP_INSN)
-    return 0;
-
-  insn = XEXP (insn, 3);
-  if (GET_CODE (insn) != SET)
-    return 0;
-
-  if (GET_CODE (XEXP (insn, 0)) != PC)
-    return 0;
-
-  insn = XEXP (insn, 1);
-  if (GET_CODE (insn) != IF_THEN_ELSE)
-    return 0;
-
-  insn = XEXP (insn, 0);
-  return GET_CODE (insn) != GE && GET_CODE (insn) != GT
-    && GET_CODE (insn) != LE && GET_CODE (insn) != LT;
-}
-
-void
-i370_function_prolog (f, l)
-     FILE *f;
-     int l;
-{
-#if MACROPROLOGUE == 1
-  fprintf (f, "\tEDCPRLG USRDSAL=%d,BASEREG=%d\n",
-	   STACK_POINTER_OFFSET + l - 120 +
-	   current_function_outgoing_args_size, BASE_REGISTER);
-  fprintf (f, "PG%d\tEQU\t*\n", mvs_page_num );
-  fprintf (f, "\tLR\t11,1\n");
-  fprintf (f, "\tL\t%d,=A(PGT%d)\n", PAGE_REGISTER, mvs_page_num);
-  mvs_page_code = 6;
-  mvs_page_lit = 4;
-  mvs_check_page (f, 0, 0);
-  function_base_page = mvs_page_num;
-#else /* MACROPROLOGUE != 1 */
-  static int function_label_index = 1;
-  static int function_first = 0;
-  static int function_year, function_month, function_day;
-  static int function_hour, function_minute, function_second;
-  int i;
-  if (!function_first)
-    {
-      struct tm *function_time;
-      time_t lcltime;
-      time (&lcltime);
-      function_time = localtime (&lcltime);
-      function_year = function_time->tm_year + 1900;
-      function_month = function_time->tm_mon + 1;
-      function_day = function_time->tm_mday;
-      function_hour = function_time->tm_hour;
-      function_minute = function_time->tm_min;
-      function_second = function_time->tm_sec;
-      fprintf (f, "PPA2\tDS\t0F\n");
-      fprintf (f, "\tDC\tX'03',X'00',X'33',X'00'\n");
-      fprintf (f, "\tDC\tV(CEESTART),A(0)\n");
-      fprintf (f, "\tDC\tA(CEETIMES)\n");
-      fprintf (f, "CEETIMES\tDS\t0F\n");
-      fprintf (f, "\tDC\tCL4'%d',CL4'%02d%02d',CL6'%02d%02d00'\n",
-    		 function_year, function_month, function_day,
-    		 function_hour, function_minute, function_second);
-      fprintf (f, "\tDC\tCL2'01',CL4'0100'\n");
-    }
-  fprintf (f, "$DSD%03d\tDSECT\n", function_label_index);
-  fprintf (f, "\tDS\tD\n");
-  fprintf (f, "\tDS\tCL(%d)\n", STACK_POINTER_OFFSET + l
-			+ current_function_outgoing_args_size);
-  fprintf (f, "\tORG\t$DSD%03d\n", function_label_index);
-  fprintf (f, "\tDS\tCL(120+8)\n");
-  fprintf (f, "\tORG\n");
-  fprintf (f, "\tDS\t0D\n");
-  fprintf (f, "$DSL%03d\tEQU\t*-$DSD%03d-8\n", function_label_index,
-	   function_label_index);
-  fprintf (f, "\tDS\t0H\n");
-  assemble_name (f, mvs_function_name);
-  fprintf (f, "\tEQU\t*\n");
-  fprintf (f, "\tUSING\t*,15\n");
-  fprintf (f, "\tB\tFPL%03d\n", function_label_index);
-  fprintf (f, "\tDC\tAL1(FPL%03d+4-*)\n", function_label_index + 1);
-  fprintf (f, "\tDC\tX'CE',X'A0',AL1(16)\n");
-  fprintf (f, "\tDC\tAL4(PPA2)\n");
-  fprintf (f, "\tDC\tAL4(0)\n");
-  fprintf (f, "\tDC\tAL4($DSL%03d)\n", function_label_index);
-  fprintf (f, "FPL%03d\tEQU\t*\n", function_label_index + 1);
-  fprintf (f, "\tDC\tAL2(%d),C'%s'\n", strlen (mvs_function_name),
-	mvs_function_name);
-  fprintf (f, "FPL%03d\tDS\t0H\n", function_label_index);
-  fprintf (f, "\tSTM\t14,12,12(13)\n");
-  fprintf (f, "\tL\t2,76(,13)\n");
-  fprintf (f, "\tL\t0,16(,15)\n");
-  fprintf (f, "\tALR\t0,2\n");
-  fprintf (f, "\tCL\t0,12(,12)\n");
-  fprintf (f, "\tBNH\t*+10\n");
-  fprintf (f, "\tL\t15,116(,12)\n");
-  fprintf (f, "\tBALR\t14,15\n");
-  fprintf (f, "\tL\t15,72(,13)\n");
-  fprintf (f, "\tSTM\t15,0,72(2)\n");
-  fprintf (f, "\tMVI\t0(2),X'10'\n");
-  fprintf (f, "\tST\t2,8(,13)\n ");
-  fprintf (f, "\tST\t13,4(,2)\n ");
-  fprintf (f, "\tLR\t13,2\n");
-  fprintf (f, "\tDROP\t15\n");
-  fprintf (f, "\tBALR\t%d,0\n", BASE_REGISTER);
-  fprintf (f, "PG%d\tEQU\t*\n", mvs_page_num );
-  fprintf (f, "\tUSING\t*,%d\n", BASE_REGISTER);
-  fprintf (f, "\tLR\t11,1\n");
-  fprintf (f, "\tL\t%d,=A(PGT%d)\n", PAGE_REGISTER, mvs_page_num);
-  mvs_page_code = 4;
-  mvs_page_lit = 4;
-  mvs_check_page (f, 0, 0);
-  function_base_page = mvs_page_num;
-  function_first = 1;
-  function_label_index += 2;
-#endif /* MACROPROLOGUE */
-}
diff --git a/gcc/config/i370/i370.h b/gcc/config/i370/i370.h
deleted file mode 100755
index 22675eb..0000000
--- a/gcc/config/i370/i370.h
+++ /dev/null
@@ -1,1440 +0,0 @@
-/* Definitions of target machine for GNU compiler.  System/370 version.
-   Copyright (C) 1989, 1993, 1995, 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Jan Stein (jan@cd.chalmers.se).
-   Modified for C/370 MVS by Dave Pitts (dpitts@nyx.cs.du.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define TARGET_VERSION printf (" (370/MVS)");
-
-/* Options for the preprocessor for this target machine.  */
-
-#define CPP_SPEC "-trigraphs"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-DGCC -Dgcc -DMVS -Dmvs -Asystem(mvs) -Acpu(i370) -Amachine(i370)"
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* The sizes of the code and literals on the current page.  */
-
-extern int mvs_page_code, mvs_page_lit;
-
-/* The current page number and the base page number for the function.  */
-
-extern int mvs_page_num, function_base_page;
-
-/* True if a label has been emitted.  */
-
-extern int mvs_label_emitted;
-
-/* The name of the current function.  */
-
-extern char *mvs_function_name;
-
-/* The length of the function name malloc'd area.  */
-
-extern int mvs_function_name_length;
-
-/* The amount of space used for outgoing arguments.  */
-
-extern int current_function_outgoing_args_size;
-
-/* Compile using char instructions (mvc, nc, oc, xc).  On 4341 use this since
-   these are more than twice as fast as load-op-store.
-   On 3090 don't use this since load-op-store is much faster.  */
-
-#define TARGET_CHAR_INSTRUCTIONS (target_flags & 1)
-
-/* Default target switches */
-
-#define TARGET_DEFAULT 1
-
-/* Macro to define tables used to set the flags.  This is a list in braces
-   of pairs in braces, each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES							\
-{ { "char-instructions", 1},						\
-  { "no-char-instructions", -1},					\
-  { "", TARGET_DEFAULT} }
-
-/* To use IBM supplied macro function prologue and epilogue, define the
-   following to 1.  Should only be needed if IBM changes the definition
-   of their prologue and epilogue.  */
-
-#define MACROPROLOGUE 0
-#define MACROEPILOGUE 0
-
-/* Target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered in instructions
-   that operate on numbered bit-fields.  */
-
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if MS word of a multiword is the lowest numbered.  */
-
-#define WORDS_BIG_ENDIAN 1
-
-/* Number of bits in an addressable storage unit.  */
-
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.  */
-
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.  See also the macro `Pmode' defined below.  */
-
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing pointers in memory.  */
-
-#define POINTER_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-
-#define STACK_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-
-#define FUNCTION_BOUNDARY 32
-
-/* There is no point aligning anything to a rounder boundary than this.  */
-
-#define BIGGEST_ALIGNMENT 64
-
-/* Alignment of field after `int : 0' in a structure.  */
-
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Define this if move instructions will actually fail to work when given
-   unaligned data.  */
-
-#define STRICT_ALIGNMENT 0
-
-/* Define target floating point format.  */
-
-#define TARGET_FLOAT_FORMAT IBM_FLOAT_FORMAT
-
-/* Define character mapping for cross-compiling.  */
-
-#define TARGET_EBCDIC 1
-
-#ifdef HOST_EBCDIC
-#define MAP_CHARACTER(c) ((char)(c))
-#else
-#define MAP_CHARACTER(c) ((char)mvs_map_char (c))
-#endif
-
-/* Define maximum length of page minus page escape overhead.  */
-
-#define MAX_MVS_PAGE_LENGTH 4080
-
-/* Define if special allocation order desired.  */
-
-#define REG_ALLOC_ORDER							\
-{ 0, 1, 2, 3, 14, 15, 12, 10, 9, 8, 7, 6, 5, 4, 16, 17, 18, 19, 11, 13 }
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.  The hardware registers are
-   assigned numbers for the compiler from 0 to just below
-   FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-   For the 370, we give the data registers numbers 0-15,
-   and the floating point registers numbers 16-19.  */
-
-#define FIRST_PSEUDO_REGISTER 20
-
-/* Define base and page registers.  */
-
-#define BASE_REGISTER 3
-#define PAGE_REGISTER 4
-
-/* 1 for registers that have pervasive standard uses and are not available
-   for the register allocator.  On the 370 under C/370, R13 is stack (DSA)
-   pointer, R12 is the TCA pointer, R3 is the base register, R4 is the page
-   origin table pointer and R11 is the arg pointer.  */
-
-#define FIXED_REGISTERS 						\
-{ 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 }
-/*0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19*/
-
-/* 1 for registers not available across function calls.  These must include
-   the FIXED_REGISTERS and also any registers that can be used without being
-   saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   NOTE: all floating registers are undefined across calls.  */
-
-#define CALL_USED_REGISTERS 						\
-{ 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
-/*0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19*/
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE) 					\
-  ((REGNO) > 15 ? 1 : (GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On the 370, the cpu registers can hold QI, HI, SI, SF and DF.  The
-   even registers can hold DI.  The floating point registers can hold
-   either SF or DF.  */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE)					\
-  ((REGNO) < 16 ? ((REGNO) & 1) == 0 || (MODE) != DImode		\
-		: (MODE) == SFmode || (MODE) == DFmode)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers when one has
-   mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-
-#define MODES_TIEABLE_P(MODE1, MODE2)					\
-  (((MODE1) == SFmode || (MODE1) == DFmode)				\
-   == ((MODE2) == SFmode || (MODE2) == DFmode))
-
-/* Mark external references.  */
-
-#define ENCODE_SECTION_INFO(decl)  					\
-  if (DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)) 			\
-    SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* 370 PC isn't overloaded on a register.  */
-
-/* #define PC_REGNUM */
-
-/* Register to use for pushing function arguments.  */
-
-#define STACK_POINTER_REGNUM 13
-
-/* Base register for access to local variables of the function.  */
-
-#define FRAME_POINTER_REGNUM 13
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms may be
-   accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-
-#define FRAME_POINTER_REQUIRED 1
-
-/* Base register for access to arguments of the function.  */
-
-#define ARG_POINTER_REGNUM 11
-
-/* Register in which static-chain is passed to a function.  */
-
-#define STATIC_CHAIN_REGNUM 10
-
-/* Register in which address to store a structure value is passed to
-   a function.  */
-
-#define STRUCT_VALUE_REGNUM 1
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-enum reg_class
-  {
-    NO_REGS, ADDR_REGS, DATA_REGS,
-    FP_REGS, ALL_REGS, LIM_REG_CLASSES
-  };
-
-#define GENERAL_REGS DATA_REGS
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.  */
-
-#define REG_CLASS_NAMES 						\
-{ "NO_REGS", "ADDR_REGS", "DATA_REGS", "FP_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.  This is an initializer for
-   a vector of HARD_REG_SET of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS {0, 0x0fffe, 0x0ffff, 0xf0000, 0xfffff}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) 						\
-  ((REGNO) >= 16 ? FP_REGS : (REGNO) != 0 ? ADDR_REGS : DATA_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS ADDR_REGS
-#define BASE_REG_CLASS ADDR_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C)					\
-  ((C) == 'a' ? ADDR_REGS :						\
-  ((C) == 'd' ? DATA_REGS :						\
-  ((C) == 'f' ? FP_REGS   : NO_REGS)))
-
-/* The letters I, J, K, L and M in a register constraint string can be used
-   to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)					\
-  ((C) == 'I' ? (unsigned) (VALUE) < 256 :				\
-   (C) == 'J' ? (unsigned) (VALUE) < 4096 :				\
-   (C) == 'K' ? (VALUE) >= -32768 && (VALUE) < 32768 : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  1
-
-/* Given an rtx X being reloaded into a reg required to be in class CLASS,
-   return the class of reg to actually use.  In general this is just CLASS;
-   but on some machines in some cases it is preferable to use a more
-   restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X, CLASS)				\
-    (GET_CODE(X) == CONST_DOUBLE ? FP_REGS :				\
-     GET_CODE(X) == CONST_INT ? DATA_REGS :				\
-     GET_CODE(X) == LABEL_REF ||					\
-     GET_CODE(X) == SYMBOL_REF ||					\
-     GET_CODE(X) == CONST ? ADDR_REGS : (CLASS))
-
-/* Return the maximum number of consecutive registers needed to represent
-   mode MODE in a register of class CLASS.  */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)					\
-  ((CLASS) == FP_REGS ? 1 :						\
-   (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack makes the stack pointer a
-   smaller address.  */
-
-/* #define STACK_GROWS_DOWNWARD */
-
-/* Define this if the nominal address of the stack frame is at the
-   high-address end of the local variables; that is, each additional local
-   variable allocated goes at a more negative offset in the frame.  */
-
-/* #define FRAME_GROWS_DOWNWARD */
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-
-#define STARTING_FRAME_OFFSET  						\
-     (STACK_POINTER_OFFSET + current_function_outgoing_args_size)
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = STARTING_FRAME_OFFSET
-
-/* If we generate an insn to push BYTES bytes, this says how many the stack
-   pointer really advances by.  On the 370, we have no push instruction.  */
-
-/* #define PUSH_ROUNDING(BYTES) */
-
-/* Accumulate the outgoing argument count so we can request the right
-   DSA size and determine stack offset.  */
-
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Define offset from stack pointer, to location where a parm can be
-   pushed.  */
-
-#define STACK_POINTER_OFFSET 148
-
-/* Offset of first parameter from the argument pointer register value.  */
-
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* 1 if N is a possible register number for function argument passing.
-   On the 370, no registers are used in this way.  */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-
-/* Define a data type for recording info about an argument list during
-   the scan of that argument list.  This data type should hold all
-   necessary information about the function itself and about the args
-   processed so far, enough to enable macros such as FUNCTION_ARG to
-   determine where the next arg should go.  */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to
-   a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT)  ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument of mode MODE and
-   data type TYPE.  (TYPE is null for libcalls where that information
-   may not be available.) */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
- ((CUM) += ((MODE) == DFmode || (MODE) == SFmode			\
-	    ? 256							\
-	    : (MODE) != BLKmode                 			\
-	    ? (GET_MODE_SIZE (MODE) + 3) / 4 				\
-	    : (int_size_in_bytes (TYPE) + 3) / 4))
-
-/* Define where to put the arguments to a function.  Value is zero to push
-   the argument on the stack, or a hard register in which to store the
-   argument.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
-
-/* For an arg passed partly in registers and partly in memory, this is the
-   number of registers used.  For args passed entirely in registers or
-   entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
-/* Define if returning from a function call automatically pops the
-   arguments described by the number-of-args field in the call.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.  VALTYPE is the
-   data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 15.  */
-
-#define RET_REG(MODE)	((MODE) == DFmode || (MODE) == SFmode ? 16 : 15)
-
-/* On the 370 the return value is in R15 or R16.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  					\
-  gen_rtx(REG, TYPE_MODE (VALTYPE), RET_REG(TYPE_MODE(VALTYPE)))
-
-/* Define how to find the value returned by a library function assuming
-   the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE)  gen_rtx(REG, MODE, RET_REG(MODE))
-
-/* 1 if N is a possible register number for a function value.
-   On the 370 under C/370, R15 and R16 are thus used.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 15 || (N) == 16)
-
-/* This macro definition sets up a default value for `main' to return.  */
-
-#define DEFAULT_MAIN_RETURN  c_expand_return (integer_zero_node)
-
-/* This macro generates the assembly code for function entry.
-   All of the C/370 environment is preserved.  */
-#define FUNCTION_PROLOGUE(FILE, LSIZE) i370_function_prolog ((FILE), (LSIZE));
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-{									\
-  if (strlen (NAME) * 2 > mvs_function_name_length)			\
-    {									\
-      if (mvs_function_name)						\
-	free (mvs_function_name);					\
-      mvs_function_name = 0;						\
-    }									\
-  if (!mvs_function_name)						\
-    {									\
-      mvs_function_name_length = strlen (NAME) * 2;			\
-      mvs_function_name = (char *) malloc (mvs_function_name_length);	\
-      if (mvs_function_name == 0)					\
-	{								\
-	  fatal ("virtual memory exceeded");				\
-	  abort ();							\
-	}								\
-    }									\
-  if (!strcmp (NAME, "main"))						\
-    strcpy (mvs_function_name, "gccmain");				\
-  else									\
-    strcpy (mvs_function_name, NAME);					\
-}
-
-/* This macro generates the assembly code for function exit, on machines
-   that need it.  If FUNCTION_EPILOGUE is not defined then individual
-   return instructions are generated for each return statement.  Args are
-   same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-#if MACROEPILOGUE == 1
-#define FUNCTION_EPILOGUE(FILE, LSIZE)					\
-{									\
-  int i;								\
-  check_label_emit();							\
-  mvs_check_page (FILE,14,0);						\
-  fprintf (FILE, "\tEDCEPIL\n");					\
-  mvs_page_num++;							\
-  fprintf (FILE, "\tDS\t0F\n" );					\
-  fprintf (FILE, "\tLTORG\n");						\
-  fprintf (FILE, "\tDS\t0F\n");						\
-  fprintf (FILE, "PGT%d\tEQU\t*\n", function_base_page);		\
-  mvs_free_label();							\
-  for ( i = function_base_page; i < mvs_page_num; i++ )			\
-    fprintf (FILE, "\tDC\tA(PG%d)\n", i);				\
-}
-#else /* MACROEPILOGUE != 1 */
-#define FUNCTION_EPILOGUE(FILE, LSIZE)					\
-{									\
-  int i;								\
-  check_label_emit();							\
-  mvs_check_page (FILE,14,0);						\
-  fprintf (FILE, "\tL\t13,4(,13)\n");					\
-  fprintf (FILE, "\tL\t14,12(,13)\n");					\
-  fprintf (FILE, "\tLM\t2,12,28(13)\n");				\
-  fprintf (FILE, "\tBALR\t1,14\n");					\
-  fprintf (FILE, "\tDC\tA(");						\
-  mvs_page_num++;							\
-  assemble_name (FILE, mvs_function_name);				\
-  fprintf (FILE, ")\n" );						\
-  fprintf (FILE, "\tDS\t0F\n" );					\
-  fprintf (FILE, "\tLTORG\n");						\
-  fprintf (FILE, "\tDS\t0F\n");						\
-  fprintf (FILE, "PGT%d\tEQU\t*\n", function_base_page);		\
-  mvs_free_label();							\
-  for ( i = function_base_page; i < mvs_page_num; i++ )			\
-    fprintf (FILE, "\tDC\tA(PG%d)\n", i);				\
-}
-#endif /* MACROEPILOGUE */
-
-
-/* Output assembler code for a block containing the constant parts of a
-   trampoline, leaving space for the variable parts.
-
-   On the 370, the trampoline contains these instructions:
-
-        BALR  14,0
-        USING *,14
-        L     STATIC_CHAIN_REGISTER,X
-        L     15,Y
-        BR    15
-   X    DS    0F
-   Y    DS    0F  */
-
-#define TRAMPOLINE_TEMPLATE(FILE)					\
-{									\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x05E0));				\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x5800 | STATIC_CHAIN_REGNUM << 4));	\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0xE00A));				\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x58F0)); 				\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0xE00E));				\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x07FF));				\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 20
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), CXT); \
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), FNADDR); \
-}
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) 				\
-  fprintf (FILE, "Error: No profiling available.\n")
-
-/* Define EXIT_IGNORE_STACK if, when returning from a function, the stack
-   pointer does not matter (provided there is a frame pointer).  */
-
-#define EXIT_IGNORE_STACK	1
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* These assume that REGNO is a hard or pseudo reg number.  They give
-   nonzero only if REGNO is a hard reg of the suitable class or a pseudo
-   reg currently allocated to a suitable hard reg.
-   These definitions are NOT overridden anywhere.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) 					\
-  (((REGNO) > 0 && (REGNO) < 16)					\
-    || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16))
-
-#define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P(REGNO)
-
-#define REGNO_OK_FOR_DATA_P(REGNO) 					\
-  ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
-
-#define REGNO_OK_FOR_FP_P(REGNO) 					\
-  ((unsigned) ((REGNO) - 16) < 4 || (unsigned) (reg_renumber[REGNO] - 16) < 4)
-
-/* Now macros that check whether X is a register and also,
-   strictly, whether it is in a specified class.  */
-
-/* 1 if X is a data register.  */
-
-#define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
-
-/* 1 if X is an fp register.  */
-
-#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
-
-/* 1 if X is an address register.  */
-
-#define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)						\
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-  || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE		\
-  || (GET_CODE (X) == CONST						\
-	  && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF)		\
-  || (GET_CODE (X) == CONST						\
-	  && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF		\
-	  && !SYMBOL_REF_FLAG (XEXP (XEXP (X, 0), 0))))
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check
-   its validity for a certain class.  We have two alternate definitions
-   for each of them.  The usual definition accepts all pseudo regs; the
-   other rejects them all.  The symbol REG_OK_STRICT causes the latter
-   definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that they will
-   get allocated to the class that the insn wants them to be in.
-   Some source files that are used after register allocation
-   need to be strict.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index or if it is
-  a pseudo reg.  */
-
-#define REG_OK_FOR_INDEX_P(X)						\
-  ((REGNO(X) > 0 && REGNO(X) < 16) || REGNO(X) >= 20)
-
-/* Nonzero if X is a hard reg that can be used as a base reg or if it is
-   a pseudo reg.  */
-
-#define REG_OK_FOR_BASE_P(X)	REG_OK_FOR_INDEX_P(X)
-
-#else /* REG_OK_STRICT */
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P(REGNO(X))
-
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P(REGNO(X))
-
-#endif /* REG_OK_STRICT */
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
-   valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
-   except for CONSTANT_ADDRESS_P which is actually machine-independent.  */
-
-#define COUNT_REGS(X, REGS, FAIL)					\
- if (REG_P (X) && REG_OK_FOR_BASE_P (X))				\
-   REGS += 1;								\
- else if (GET_CODE (X) != CONST_INT || (unsigned) INTVAL (X) >= 4096)	\
-   goto FAIL;
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-{									\
-  if (REG_P (X) && REG_OK_FOR_BASE_P (X))				\
-    goto ADDR;								\
-  if (GET_CODE (X) == PLUS)						\
-    {									\
-      int regs = 0;							\
-      rtx x0 = XEXP (X, 0);						\
-      rtx x1 = XEXP (X, 1);						\
-      if (GET_CODE (x0) == PLUS)					\
-	{								\
-	  COUNT_REGS (XEXP (x0, 0), regs, FAIL);			\
-	  COUNT_REGS (XEXP (x0, 1), regs, FAIL);			\
-	  COUNT_REGS (x1, regs, FAIL);					\
-	  if (regs == 2)						\
-	    goto ADDR;							\
-	}								\
-      else if (GET_CODE (x1) == PLUS)					\
-	{								\
-	  COUNT_REGS (x0, regs, FAIL);					\
-	  COUNT_REGS (XEXP (x1, 0), regs, FAIL);			\
-	  COUNT_REGS (XEXP (x1, 1), regs, FAIL);			\
-	  if (regs == 2)						\
-	    goto ADDR;							\
-	}								\
-      else								\
-	{								\
-	  COUNT_REGS (x0, regs, FAIL);					\
-	  COUNT_REGS (x1, regs, FAIL);					\
-	  if (regs != 0)						\
-	    goto ADDR;							\
-	}								\
-    }									\
-  FAIL: ;								\
-}
-
-/* The 370 has no mode dependent addresses.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.  */
-
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)				\
-{									\
-  if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1)))		\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 0),				\
-		   copy_to_mode_reg (SImode, XEXP (X, 1)));		\
-  if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0)))		\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 1),				\
-		   copy_to_mode_reg (SImode, XEXP (X, 0)));		\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT)		\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 1),				\
-		   force_operand (XEXP (X, 0), 0));			\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT)		\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 0),				\
-		   force_operand (XEXP (X, 1), 0));			\
-  if (memory_address_p (MODE, X))					\
-    goto WIN;								\
-}
-
-/* Specify the machine mode that this machine uses for the index in the
-   tablejump instruction.  */
-
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* Define this if fixuns_trunc is the same as fix_trunc.  */
-
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* We use "unsigned char" as default.  */
-
-#define DEFAULT_SIGNED_CHAR 0
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Max number of bytes we can move from memory to memory in one reasonably
-   fast instruction.  */
-
-#define MOVE_MAX 256
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-
-#define SLOW_ZERO_EXTEND
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-
-#define SLOW_BYTE_ACCESS 1
-
-/* Define if shifts truncate the shift count which implies one can omit
-   a sign-extension or zero-extension of a shift count.  */
-
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)	(OUTPREC != 16)
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-/* #define STORE_FLAG_VALUE -1 */
-
-/* When a prototype says `char' or `short', really pass an `int'.  */
-
-#define PROMOTE_PROTOTYPES
-
-/* Don't perform CSE on function addresses.  */
-
-#define NO_FUNCTION_CSE
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-
-#define Pmode SImode
-
-/* A function address in a call instruction is a byte address (for
-   indexing purposes) so give the MEM rtx a byte's mode.  */
-
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX whose
-   rtx-code is CODE.  The body of this macro is a portion of a switch
-   statement.  If the code is computed here, return it with a return
-   statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX, CODE, OUTERCODE)				\
-  case CONST_INT:							\
-    if ((unsigned) INTVAL (RTX) < 0xfff) return 1;			\
-  case CONST:								\
-  case LABEL_REF:							\
-  case SYMBOL_REF:							\
-    return 2;								\
-  case CONST_DOUBLE:							\
-    return 4;
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  */
-
-/* Store in cc_status the expressions that the condition codes will
-   describe after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.
-
-   On the 370, load insns do not alter the cc's.  However, in some
-   cases these instructions can make it possibly invalid to use the
-   saved cc's.  In those cases we clear out some or all of the saved
-   cc's so they won't be used.  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN)					\
-{									\
-  rtx exp = (EXP);							\
-  if (GET_CODE (exp) == PARALLEL) /* Check this */			\
-    exp = XVECEXP (exp, 0, 0);						\
-  if (GET_CODE (exp) != SET)						\
-    CC_STATUS_INIT;							\
-  else									\
-    {									\
-      if (XEXP (exp, 0) == cc0_rtx)					\
-	{								\
-	  cc_status.value1 = XEXP (exp, 0);				\
-	  cc_status.value2 = XEXP (exp, 1);				\
-	  cc_status.flags = 0;						\
-	}								\
-      else								\
-	{								\
-	  if (cc_status.value1						\
-	      && reg_mentioned_p (XEXP (exp, 0), cc_status.value1))	\
-	    cc_status.value1 = 0;					\
-	  if (cc_status.value2						\
-	      && reg_mentioned_p (XEXP (exp, 0), cc_status.value2))	\
-	    cc_status.value2 = 0;					\
-	  switch (GET_CODE (XEXP (exp, 1)))				\
-	    {								\
-	      case PLUS:     case MINUS: case MULT:   /* case UMULT: */	\
-	      case DIV:      case UDIV:  case NEG:    case ASHIFT:	\
-	      case ASHIFTRT: case AND:   case IOR:    case XOR:		\
-	      case ABS:      case NOT:					\
-		CC_STATUS_SET (XEXP (exp, 0), XEXP (exp, 1));		\
-	    }								\
-	}								\
-    }									\
-}
-
-
-#define CC_STATUS_SET(V1, V2)						\
-{									\
-  cc_status.flags = 0;							\
-  cc_status.value1 = (V1);						\
-  cc_status.value2 = (V2);						\
-  if (cc_status.value1							\
-      && reg_mentioned_p (cc_status.value1, cc_status.value2))		\
-    cc_status.value2 = 0;						\
-}
-
-#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) 				\
-{ if (cc_status.flags & CC_NO_OVERFLOW)	return NO_OV; return NORMAL; }
-
-/* Control the assembler format that we output.  */
-
-#define TEXT_SECTION_ASM_OP "* Program text area"
-#define DATA_SECTION_ASM_OP "* Program data area"
-#define INIT_SECTION_ASM_OP "* Program initialization area"
-#define CTOR_LIST_BEGIN		/* NO OP */
-#define CTOR_LIST_END		/* NO OP */
-
-/* How to refer to registers in assembler output.  This sequence is
-   indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES							\
-{ "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",			\
-  "8",  "9", "10", "11", "12", "13", "14", "15",			\
-  "0",  "2",  "4",  "6"							\
-}
-
-/* How to renumber registers for dbx and gdb.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-#define ASM_FILE_START(FILE) fputs ("\tCSECT\n", FILE);
-#define ASM_FILE_END(FILE) fputs ("\tEND\n", FILE);
-#define ASM_IDENTIFY_GCC(FILE)
-#define ASM_COMMENT_START "*"
-#define ASM_APP_OFF ""
-#define ASM_APP_ON ""
-
-#define ASM_OUTPUT_LABEL(FILE, NAME) 					\
-{ assemble_name (FILE, NAME); fputs ("\tEQU\t*\n", FILE); }
-
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)	/* NO OP */
-
-#define ASM_GLOBALIZE_LABEL(FILE, NAME)					\
-{ fputs ("\tENTRY\t", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE); }
-
-/* MVS externals are limited to 8 characters, upper case only.
-   The '_' is mapped to '@', except for MVS functions, then '#'.  */
-
-#define MAX_MVS_LABEL_SIZE 8
-
-#define ASM_OUTPUT_LABELREF(FILE, NAME)					\
-{									\
-  char *bp, ch, temp[MAX_MVS_LABEL_SIZE + 1];				\
-  if (strlen (NAME) > MAX_MVS_LABEL_SIZE)				\
-    {									\
-      strncpy (temp, NAME, MAX_MVS_LABEL_SIZE);				\
-      temp[MAX_MVS_LABEL_SIZE] = '\0';					\
-    }									\
-  else									\
-    strcpy (temp,NAME);							\
-  if (!strcmp (temp,"main"))						\
-    strcpy (temp,"gccmain");						\
-  if (mvs_function_check (temp))					\
-    ch = '#';								\
-  else									\
-    ch = '@';								\
-  for (bp = temp; *bp; bp++)						\
-    {									\
-      if (islower (*bp)) *bp = toupper (*bp);				\
-      if (*bp == '_') *bp = ch;						\
-    }									\
-  fprintf (FILE, "%s", temp);						\
-}
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)			\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* Generate internal label.  Since we can branch here from off page, we
-   must reload the base register.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) 			\
-{									\
-  if (!strcmp (PREFIX,"L"))						\
-    {									\
-      mvs_add_label(NUM);						\
-      mvs_label_emitted = 1;						\
-    }									\
-  fprintf (FILE, "%s%d\tEQU\t*\n", PREFIX, NUM);			\
-}
-
-/* Generate case label.  */
-
-#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, TABLE)			\
-   fprintf (FILE, "%s%d\tEQU\t*\n", PREFIX, NUM)
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  				\
-  mvs_check_page (FILE, 4, 0);						\
-  fprintf (FILE, "\tDC\tA(L%d)\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) 		\
-  mvs_check_page (FILE, 4, 0);						\
-  fprintf (FILE, "\tDC\tA(L%d-L%d)\n", VALUE, REL)
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE, REGNO)				\
-  mvs_check_page (FILE, 8, 4);						\
-  fprintf (FILE, "\tS\t13,=F'4'\n\tST\t%s,%d(13)\n",			\
-     reg_names[REGNO], STACK_POINTER_OFFSET)
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE, REGNO)					\
-  mvs_check_page (FILE, 8, 0);						\
-  fprintf (FILE, "\tL\t%s,%d(13)\n\tLA\t13,4(13)\n",			\
-     reg_names[REGNO], STACK_POINTER_OFFSET)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)					\
-  fprintf (FILE, "\tDC\tD'%.18G'\n", (VALUE))
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)					\
-  fprintf (FILE, "\tDC\tE'%.9G'\n", (VALUE))
-
-/* This outputs an integer, if not a CONST_INT must be address constant.  */
-
-#define ASM_OUTPUT_INT(FILE, EXP)					\
-{ 									\
-  if (GET_CODE (EXP) == CONST_INT)					\
-    {									\
-      fprintf (FILE, "\tDC\tF'");					\
-      output_addr_const (FILE, EXP);					\
-      fprintf (FILE, "'\n");						\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\tDC\tA(");					\
-      output_addr_const (FILE, EXP);					\
-      fprintf (FILE, ")\n");						\
-    }									\
-}
-
-/* This outputs a short integer.  */
-
-#define ASM_OUTPUT_SHORT(FILE, EXP)					\
-{									\
-  fprintf (FILE, "\tDC\tX'%04X'\n", INTVAL(EXP) & 0xFFFF);		\
-}
-
-/* This outputs a byte sized integer.  */
-
-#define ASM_OUTPUT_CHAR(FILE, EXP)					\
-  fprintf (FILE, "\tDC\tX'%02X'\n", INTVAL (EXP) )
-
-#define ASM_OUTPUT_BYTE(FILE, VALUE)					\
-  fprintf (FILE, "\tDC\tX'%02X'\n", VALUE)
-
-/* This outputs a text string.  The string are chopped up to fit into
-   an 80 byte record.  Also, control and special characters, interpreted
-   by the IBM assembler, are output numerically.  */
-
-#define MVS_ASCII_TEXT_LENGTH 48
-
-#define ASM_OUTPUT_ASCII(FILE, PTR, LEN)				\
-{									\
-  int i, j;								\
-  int c;								\
-  for (j = 0, i = 0; i < LEN; j++, i++)					\
-    {									\
-      c = PTR[i];							\
-      if (iscntrl (c) || c == '&')					\
-	{								\
-	  if (j % MVS_ASCII_TEXT_LENGTH != 0 )				\
-	    fprintf (FILE, "'\n");					\
-	  j = -1;							\
-	  if (c == '&') c = MAP_CHARACTER (c);				\
-	  fprintf (FILE, "\tDC\tX'%X'\n", c );				\
-	}								\
-      else								\
-	{								\
-	  if (j % MVS_ASCII_TEXT_LENGTH == 0)				\
-            fprintf (FILE, "\tDC\tC'");					\
-          if ( c == '\'' )                                       	\
-	    fprintf (FILE, "%c%c", c, c);                        	\
-	  else                                                   	\
-	    fprintf (FILE, "%c", c);                             	\
-	  if (j % MVS_ASCII_TEXT_LENGTH == MVS_ASCII_TEXT_LENGTH - 1)	\
-	    fprintf (FILE, "'\n" );					\
-	}								\
-    }									\
-  if (j % MVS_ASCII_TEXT_LENGTH != 0)					\
-    fprintf (FILE, "'\n");						\
-}
-
-/* This is how to output an assembler line that says to advance the
-   location counter to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE, LOG)					\
-  if (LOG)								\
-    {									\
-      if ((LOG) == 1)							\
-        fprintf (FILE, "\tDS\t0H\n" );					\
-      else 								\
-        fprintf (FILE, "\tDS\t0F\n" );					\
-    }									\
-
-/* The maximum length of memory that the IBM assembler will allow in one
-   DS operation.  */
-
-#define MAX_CHUNK 32767
-
-/* A C statement to output to the stdio stream FILE an assembler
-   instruction to advance the location counter by SIZE bytes. Those
-   bytes should be zero when loaded.  */
-
-#define ASM_OUTPUT_SKIP(FILE, SIZE)  					\
-{									\
-  int s, k;								\
-  for (s = (SIZE); s > 0; s -= MAX_CHUNK)				\
-    {									\
-      if (s > MAX_CHUNK)						\
-	k = MAX_CHUNK;							\
-      else								\
-	k = s;								\
-      fprintf (FILE, "\tDS\tXL%d\n", k);				\
-    }									\
-}
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of a common-label named NAME whose
-   size is SIZE bytes.  The variable ROUNDED is the size rounded up
-   to whatever alignment the caller wants.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) 			\
-{									\
-  fputs ("\tENTRY\t", FILE);						\
-  assemble_name (FILE, NAME);						\
-  fputs ("\n", FILE);							\
-  fprintf (FILE, "\tDS\t0F\n");						\
-  ASM_OUTPUT_LABEL (FILE,NAME);						\
-  ASM_OUTPUT_SKIP (FILE,SIZE);						\
-}
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of a local-common-label named NAME
-   whose size is SIZE bytes.  The variable ROUNDED is the size
-   rounded up to whatever alignment the caller wants.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) 			\
-{									\
-  fprintf (FILE, "\tDS\t0F\n");						\
-  ASM_OUTPUT_LABEL (FILE,NAME);						\
-  ASM_OUTPUT_SKIP (FILE,SIZE);						\
-}
-
-/* Store in OUTPUT a string (made with alloca) containing an
-   assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)  		\
-{									\
-  (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10);			\
-  sprintf ((OUTPUT), "%s%d", (NAME), (LABELNO));			\
-}
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-
-#define TARGET_BELL	47
-#define TARGET_BS	22
-#define TARGET_TAB	5
-#define TARGET_NEWLINE	21
-#define TARGET_VT	11
-#define TARGET_FF	12
-#define TARGET_CR	13
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-#define PRINT_OPERAND(FILE, X, CODE)					\
-{									\
-  switch (GET_CODE (X))							\
-    {									\
-      static char curreg[4];						\
-      case REG:								\
-	if (CODE == 'N')						\
-	    strcpy (curreg, reg_names[REGNO (X) + 1]);			\
-	else								\
-	    strcpy (curreg, reg_names[REGNO (X)]);			\
-	fprintf (FILE, "%s", curreg);					\
-	break;								\
-      case MEM:								\
-	{								\
-	  rtx addr = XEXP (X, 0);					\
-	  if (CODE == 'O')						\
-	    {								\
-	      if (GET_CODE (addr) == PLUS)				\
-		fprintf (FILE, "%d", INTVAL (XEXP (addr, 1)));		\
-	      else							\
-		fprintf (FILE, "0");					\
-	    }								\
-	  else if (CODE == 'R')						\
-	    {								\
-	      if (GET_CODE (addr) == PLUS)				\
-		fprintf (FILE, "%s", reg_names[REGNO (XEXP (addr, 0))]);\
-	      else							\
-		fprintf (FILE, "%s", reg_names[REGNO (addr)]);		\
-	    }								\
-	  else								\
-	    output_address (XEXP (X, 0));				\
-	}								\
-	break;								\
-      case SYMBOL_REF:							\
-      case LABEL_REF:							\
-	mvs_page_lit += 4;						\
-	if (SYMBOL_REF_FLAG (X)) fprintf (FILE, "=V(");			\
-	else                     fprintf (FILE, "=A(");			\
-	output_addr_const (FILE, X);					\
-	fprintf (FILE, ")");						\
-	break;								\
-      case CONST_INT:					        	\
-	if (CODE == 'B')						\
-	  fprintf (FILE, "%d", INTVAL (X) & 0xff);			\
-	else if (CODE == 'X')						\
-	  fprintf (FILE, "%02X", INTVAL (X) & 0xff);			\
-	else if (CODE == 'h')						\
-	  fprintf (FILE, "%d", (INTVAL (X) << 16) >> 16);		\
-	else if (CODE == 'H')						\
-	  {								\
-	    mvs_page_lit += 2;						\
-	    fprintf (FILE, "=H'%d'", (INTVAL (X) << 16) >> 16);		\
-	  }								\
-	else								\
-	  {								\
-	    mvs_page_lit += 4;						\
-	    fprintf (FILE, "=F'%d'", INTVAL (X));			\
-	  }								\
-	break;								\
-      case CONST_DOUBLE:						\
-	if (GET_MODE (X) == DImode)					\
-	  {								\
-	    if (CODE == 'M')						\
-	      {								\
-		mvs_page_lit += 4;					\
-		fprintf (FILE, "=XL4'%08X'", CONST_DOUBLE_LOW (X));	\
-	      }								\
-	    else if (CODE == 'L')					\
-	      {								\
-		mvs_page_lit += 4;					\
-		fprintf (FILE, "=XL4'%08X'", CONST_DOUBLE_HIGH (X));	\
-	      }								\
-	    else							\
-	      {								\
-		mvs_page_lit += 8;					\
-		fprintf (FILE, "=XL8'%08X%08X'", CONST_DOUBLE_LOW (X),	\
-			CONST_DOUBLE_HIGH (X));				\
-	      }								\
-	  }								\
-	else								\
-	  { 								\
-	    union { double d; int i[2]; } u;				\
-	    u.i[0] = CONST_DOUBLE_LOW (X);				\
-	    u.i[1] = CONST_DOUBLE_HIGH (X);				\
-	    if (GET_MODE (X) == SFmode)					\
-	      {								\
-		mvs_page_lit += 4;					\
-		fprintf (FILE, "=E'%.9G'", u.d);			\
-	      }								\
-	    else							\
-	      {								\
-		mvs_page_lit += 8;					\
-		fprintf (FILE, "=D'%.18G'", u.d);			\
-	      }								\
-	  }								\
-	break;								\
-      case CONST:							\
-	if (GET_CODE (XEXP (X, 0)) == PLUS				\
-	   && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF)		\
-	  {								\
-	    mvs_page_lit += 4;						\
-	    if (SYMBOL_REF_FLAG (XEXP (XEXP (X, 0), 0)))		\
-	      {								\
-		fprintf (FILE, "=V(");					\
-		ASM_OUTPUT_LABELREF (FILE,				\
-				  XSTR (XEXP (XEXP (X, 0), 0), 0));	\
-		fprintf (FILE, ")\n\tA\t%s,=F'%d'", curreg,		\
-				  INTVAL (XEXP (XEXP (X, 0), 1)));	\
-	      }								\
-	    else							\
-	      {								\
-		fprintf (FILE, "=A(");					\
-		output_addr_const (FILE, X);				\
-		fprintf (FILE, ")");					\
-	      }								\
-	  }								\
-	else								\
-	  {								\
-	    mvs_page_lit += 4;						\
-	    fprintf (FILE, "=F'");					\
-	    output_addr_const (FILE, X);				\
-	    fprintf (FILE, "'");					\
-	  }								\
-	break;								\
-      default:								\
-	abort();							\
-    }									\
-}
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)				\
-{									\
-  rtx breg, xreg, offset, plus;						\
-  									\
-  switch (GET_CODE (ADDR))						\
-    {									\
-      case REG:								\
-	fprintf (FILE, "0(%s)", reg_names[REGNO (ADDR)]);		\
-	break;								\
-      case PLUS:							\
-	breg = 0;							\
-	xreg = 0;							\
-	offset = 0;							\
-	if (GET_CODE (XEXP (ADDR, 0)) == PLUS)				\
-	  {								\
-	    if (GET_CODE (XEXP (ADDR, 1)) == REG)			\
-	      breg = XEXP (ADDR, 1);					\
-	    else							\
-	      offset = XEXP (ADDR, 1);					\
-	    plus = XEXP (ADDR, 0);					\
-	  }								\
-	else								\
-	  {								\
-	    if (GET_CODE (XEXP (ADDR, 0)) == REG)			\
-	      breg = XEXP (ADDR, 0);					\
-	    else							\
-	      offset = XEXP (ADDR, 0);					\
-	    plus = XEXP (ADDR, 1);					\
-	  }								\
-	if (GET_CODE (plus) == PLUS)					\
-	  {								\
-	    if (GET_CODE (XEXP (plus, 0)) == REG)			\
-	      {								\
-		if (breg)						\
-		  xreg = XEXP (plus, 0);				\
-		else							\
-		  breg = XEXP (plus, 0);				\
-	      }								\
-	    else							\
-	      {								\
-		offset = XEXP (plus, 0);				\
-	      }								\
-	    if (GET_CODE (XEXP (plus, 1)) == REG)			\
-	      {								\
-		if (breg)						\
-		  xreg = XEXP (plus, 1);				\
-		else							\
-		  breg = XEXP (plus, 1);				\
-	      }								\
-	    else							\
-	      {								\
-		offset = XEXP (plus, 1);				\
-	      }								\
-	  }								\
-	else if (GET_CODE (plus) == REG)				\
-	  {								\
-	    if (breg)							\
-	      xreg = plus;						\
-	    else							\
-	      breg = plus;						\
-	  }								\
-	else								\
-	  {								\
-	    offset = plus;						\
-	  }								\
-	if (offset)							\
-	  {								\
-	    if (GET_CODE (offset) == LABEL_REF)				\
-	      fprintf (FILE, "L%d",					\
-			CODE_LABEL_NUMBER (XEXP (offset, 0)));		\
-	    else							\
-	      output_addr_const (FILE, offset);				\
-	  }								\
-	else								\
-	  fprintf (FILE, "0");						\
-	if (xreg)							\
-	    fprintf (FILE, "(%s,%s)",					\
-		    reg_names[REGNO (xreg)], reg_names[REGNO (breg)]); 	\
-	else								\
-	  fprintf (FILE, "(%s)", reg_names[REGNO (breg)]);		\
-	break;								\
-      default:								\
-	mvs_page_lit += 4;						\
-	if (SYMBOL_REF_FLAG (ADDR)) fprintf (FILE, "=V(");		\
-	else                        fprintf (FILE, "=A(");		\
-	output_addr_const (FILE, ADDR);					\
-	fprintf (FILE, ")");						\
-	break;								\
-    }									\
-}
diff --git a/gcc/config/i370/i370.md b/gcc/config/i370/i370.md
deleted file mode 100755
index 6d893d6..0000000
--- a/gcc/config/i370/i370.md
+++ /dev/null
@@ -1,4210 +0,0 @@
-;;- Machine description for GNU compiler -- System/370 version.
-;;  Copyright (C) 1989, 93, 94, 95, 1997 Free Software Foundation, Inc.
-;;  Contributed by Jan Stein (jan@cd.chalmers.se).
-;;  Modified for MVS C/370 by Dave Pitts (dpitts@nyx.cs.du.edu)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-;;
-;; Special constraints for 370 machine description:
-;;
-;;    a -- Any address register from 1 to 15.
-;;    d -- Any register from 0 to 15.
-;;    I -- An 8-bit constant (0..255).
-;;    J -- A 12-bit constant (0..4095).
-;;    K -- A 16-bit constant (-32768..32767).
-;;
-;; Special formats used for outputting 370 instructions.
-;;
-;;   %B -- Print a constant byte integer.
-;;   %H -- Print a signed 16-bit constant.
-;;   %L -- Print least significant word of a CONST_DOUBLE.
-;;   %M -- Print most significant word of a CONST_DOUBLE.
-;;   %N -- Print next register (second word of a DImode reg).
-;;   %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
-;;   %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
-;;   %X -- Print a constant byte integer in hex.
-;;
-;; We have a special constraint for pattern matching.
-;;
-;;   s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
-;;
-;;   r_or_s_operand -- Matches a register or a valid S operand in a RS, SI
-;;		       or SS type instruction or a register
-;;
-;; For MVS C/370 we use the following stack locations for:
-;;
-;;   136 - internal function result buffer
-;;   140 - numeric conversion buffer
-;;   144 - pointer to internal function result buffer
-;;   148 - start of automatic variables and function arguments
-;;
-;; To support programs larger than a page, 4096 bytes, PAGE_REGISTER points
-;; to a page origin table, all internal labels are generated to reload the
-;; BASE_REGISTER knowing what page it is on and all branch instructions go
-;; directly to the target if it is known that the target is on the current
-;; page (essentially backward references).  All forward references and off
-;; page references are handled by loading the address of target into a
-;; register and branching indirectly.
-;;
-;; Some *di patterns have been commented out per advice from RMS, as gcc
-;; will generate the right things to do.
-;;
-
-;;
-;;- Test instructions.
-;;
-
-;
-; tstdi instruction pattern(s).
-;
-
-(define_insn "tstdi"
-  [(set (cc0)
-	(match_operand:DI 0 "register_operand" "d"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 4, 0);
-  return \"SRDA	%0,0\";
-}")
-
-;
-; tstsi instruction pattern(s).
-;
-
-(define_insn "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "register_operand" "d"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 2, 0);
-  return \"LTR	%0,%0\";
-}")
-
-;
-; tsthi instruction pattern(s).
-;
-
-(define_insn "tsthi"
-  [(set (cc0)
-	(match_operand:HI 0 "register_operand" "d"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 4, 2);
-  return \"CH	%0,=H'0'\";
-}")
-
-;
-; tstqi instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (cc0)
-	(match_operand:QI 0 "r_or_s_operand" "dm"))]
-  "unsigned_jump_follows_p (insn)"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 4);
-      return \"N	%0,=X'000000FF'\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"CLI	%0,0\";
-}")
-
-(define_insn "tstqi"
-  [(set (cc0)
-     (match_operand:QI 0 "register_operand" "d"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (unsigned_jump_follows_p (insn))
-    {
-      mvs_check_page (0, 4, 4);
-      return \"N	%0,=X'000000FF'\";
-    }
-  mvs_check_page (0, 8, 0);
-  return \"SLL	%0,24\;SRA	%0,24\";
-}")
-
-;
-; tstdf instruction pattern(s).
-;
-
-(define_insn "tstdf"
-  [(set (cc0)
-	(match_operand:DF 0 "general_operand" "f"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 2, 0);
-  return \"LTDR	%0,%0\";
-}")
-
-;
-; tstsf instruction pattern(s).
-;
-
-(define_insn "tstsf"
-  [(set (cc0)
-	(match_operand:SF 0 "general_operand" "f"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 2, 0);
-  return \"LTER	%0,%0\";
-}")
-
-;;
-;;- Compare instructions.
-;;
-
-;
-; cmpdi instruction pattern(s).
-;
-
-;(define_insn "cmpdi"
-;  [(set (cc0)
-;	(compare (match_operand:DI 0 "register_operand" "d")
-;		 (match_operand:DI 1 "general_operand" "")))]
-;  ""
-;  "*
-;{
-;  check_label_emit ();
-;  if (REG_P (operands[1]))
-;    {
-;      mvs_check_page (0, 8, 0);
-;      if (unsigned_jump_follows_p (insn))
-;        return \"CLR	%0,%1\;BNE	*+6\;CLR	%N0,%N1\";
-;      return \"CR	%0,%1\;BNE	*+6\;CLR	%N0,%N1\";
-;    }
-;  mvs_check_page (0, 12, 0);
-;  if (unsigned_jump_follows_p (insn))
-;    return \"CL	%0,%M1\;BNE	*+8\;CL	%N0,%L1\";
-;  return \"C	%0,%M1\;BNE	*+8\;CL	%N0,%L1\";
-;}")
-
-;
-; cmpsi instruction pattern(s).
-;
-
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "register_operand" "d")
-		 (match_operand:SI 1 "general_operand" "md")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 2, 0);
-      if (unsigned_jump_follows_p (insn))
-	return \"CLR	%0,%1\";
-      return \"CR	%0,%1\";
-    }
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 4);
-      if (unsigned_jump_follows_p (insn))
-	 return \"CL	%0,=F'%c1'\";
-      return \"C	%0,=F'%c1'\";
-    }
-  mvs_check_page (0, 4, 0);
-  if (unsigned_jump_follows_p (insn))
-    return \"CL	%0,%1\";
-  return \"C	%0,%1\";
-}")
-
-;
-; cmphi instruction pattern(s).
-;
-
-(define_insn "cmphi"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "register_operand" "d")
-		 (match_operand:HI 1 "general_operand" "")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 8, 0);
-      if (unsigned_jump_follows_p (insn))
-	return \"STH	%1,140(,13)\;CLM	%0,3,140(13)\";
-      return \"STH	%1,140(,13)\;CH	%0,140(,13)\";
-    }
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"CH	%0,%H1\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"CH	%0,%1\";
-}")
-
-;
-; cmpqi instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:QI 0 "r_or_s_operand" "g")
-		 (match_operand:QI 1 "r_or_s_operand" "g")))]
-  "unsigned_jump_follows_p (insn)"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 8, 0);
-          return \"STC	%1,140(,13)\;CLM	%0,1,140(13)\";
-        }
-      if (GET_CODE (operands[1]) == CONST_INT)
-	{
-	  mvs_check_page (0, 4, 1);
-          return \"CLM	%0,1,=FL1'%B1'\";
-        }
-      mvs_check_page (0, 4, 0);
-      return \"CLM	%0,1,%1\";
-    }
-  else if (GET_CODE (operands[0]) == CONST_INT)
-    {
-      cc_status.flags |= CC_REVERSED;
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 4, 1);
-          return \"CLM	%1,1,=FL1'%B0'\";
-        }
-      mvs_check_page (0, 4, 0);
-      return \"CLI	%1,%B0\";
-    }
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"CLI	%0,%B1\";
-    }
-  if (GET_CODE (operands[1]) == MEM)
-    {
-      mvs_check_page (0, 6, 0);
-      return \"CLC	%O0(1,%R0),%1\";
-    }
-  cc_status.flags |= CC_REVERSED;
-  mvs_check_page (0, 4, 0);
-  return \"CLM	%1,1,%0\";
-}")
-
-(define_insn "cmpqi"
-  [(set (cc0)
-	(compare (match_operand:QI 0 "register_operand" "d")
-		 (match_operand:QI 1 "general_operand" "di")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (unsigned_jump_follows_p (insn))
-    {
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 4, 0);
-          return \"CLM	%0,1,%1\";
-        }
-      if (GET_CODE (operands[1]) == CONST_INT)
-	{
-	  mvs_check_page (0, 4, 1);
-          return \"CLM	%0,1,=FL1'%B1'\";
-        }
-      mvs_check_page (0, 8, 0);
-      return \"STC	%1,140(,13)\;CLM	%0,1,140(13)\";
-    }
-  if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 18, 0);
-      return \"SLL	%0,24\;SRA	%0,24\;SLL	%1,24\;SRA	%1,24\;CR	%0,%1\";
-    }
-  mvs_check_page (0, 12, 0);
-  return \"SLL	%0,24\;SRA	%0,24\;C	%0,%1\";
-}")
-
-;
-; cmpdf instruction pattern(s).
-;
-
-(define_insn "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "general_operand" "f,mF")
-		 (match_operand:DF 1 "general_operand" "fmF,f")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 2, 0);
-	  return \"CDR	%0,%1\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"CD	%0,%1\";
-    }
-  cc_status.flags |= CC_REVERSED;
-  mvs_check_page (0, 4, 0);
-  return \"CD	%1,%0\";
-}")
-
-;
-; cmpsf instruction pattern(s).
-;
-
-(define_insn "cmpsf"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "general_operand" "f,mF")
-		 (match_operand:SF 1 "general_operand" "fmF,f")))]
-  ""
-  "*
-{
-check_label_emit ();
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 2, 0);
-	  return \"CER	%0,%1\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"CE	%0,%1\";
-    }
-  cc_status.flags |= CC_REVERSED;
-  mvs_check_page (0, 4, 0);
-  return \"CE	%1,%0\";
-}")
-
-;
-; cmpstrsi instruction pattern(s).
-;
-
-(define_expand "cmpstrsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	  (compare (match_operand:BLK 1 "general_operand" "")
-		   (match_operand:BLK 2 "general_operand" "")))
-     (use (match_operand:SI 3 "general_operand" ""))
-     (use (match_operand:SI 4 "" ""))]
-   ""
-   "
-{
-  rtx op1, op2;
-
-  op1 = XEXP (operands[1], 0);
-  if (GET_CODE (op1) == REG
-      || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG
-	  && GET_CODE (XEXP (op1, 1)) == CONST_INT
-	  && (unsigned) INTVAL (XEXP (op1, 1)) < 4096))
-    {
-      op1 = operands[1];
-    }
-  else
-    {
-      op1 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op1));
-    }
-
-  op2 = XEXP (operands[2], 0);
-  if (GET_CODE (op2) == REG
-      || (GET_CODE (op2) == PLUS && GET_CODE (XEXP (op2, 0)) == REG
-	  && GET_CODE (XEXP (op2, 1)) == CONST_INT
-	  && (unsigned) INTVAL (XEXP (op2, 1)) < 4096))
-    {
-      op2 = operands[2];
-    }
-  else
-    {
-      op2 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op2));
-    }
-      
-  if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
-    {
-      emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
-		gen_rtx (SET, VOIDmode, operands[0], 
-			gen_rtx (COMPARE, VOIDmode, op1, op2)),
-		gen_rtx (USE, VOIDmode, operands[3]))));
-    }
-  else
-    {
-      rtx reg1 = gen_reg_rtx (DImode);
-      rtx reg2 = gen_reg_rtx (DImode);
-      rtx subreg = gen_rtx (SUBREG, SImode, reg1, 1);
-
-      emit_insn (gen_rtx (SET, VOIDmode, subreg, operands[3]));
-      emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, reg2, 1),
-					    subreg));
-      emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5,
-		gen_rtx (SET, VOIDmode, operands[0],
-			gen_rtx (COMPARE, VOIDmode, op1, op2)),
-		gen_rtx (USE, VOIDmode, reg1),
-		gen_rtx (USE, VOIDmode, reg2),
-		gen_rtx (CLOBBER, VOIDmode, reg1),
-		gen_rtx (CLOBBER, VOIDmode, reg2))));
-    }
-  DONE;
-}")
-
-; Compare a block that is less than 256 bytes in length.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "d")
-	(compare (match_operand:BLK 1 "s_operand" "m")
-		 (match_operand:BLK 2 "s_operand" "m")))
-   (use (match_operand:QI 3 "immediate_operand" "I"))]
-  "((unsigned) INTVAL (operands[3]) < 256)"
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 22, 0);
-  return \"LA	%0,1\;CLC	%O1(%c3,%R1),%2\;BH	*+12\;BL	*+6\;SLR	%0,%0\;LNR	%0,%0\";
-}")
-
-; Compare a block that is larger than 255 bytes in length.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "d")
- 	(compare (match_operand:BLK 1 "general_operand" "m")
-		 (match_operand:BLK 2 "general_operand" "m")))
-   (use (match_operand:DI 3 "register_operand" "d"))
-   (use (match_operand:DI 4 "register_operand" "d"))
-   (clobber (match_dup 3))
-   (clobber (match_dup 4))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 26, 0);
-  return \"LA	%3,%1\;LA	%4,%2\;LA	%0,1\;CLCL	%3,%4\;BH	*+12\;BL	*+6\;SLR	%0,%0\;LNR	%0,%0\";
-}")
-
-;;
-;;- Move instructions.
-;;
-
-;
-; movdi instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:DI 0 "r_or_s_operand" "=dm")
-        (match_operand:DI 1 "r_or_s_operand" "dim*fF"))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 8, 0);
-	  return \"STD	%1,140(,13)\;LM	%0,%N0,140(13)\";
-	}
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 4, 0);
-	  return \"LR	%0,%1\;LR	%N0,%N1\";
-	}
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 4, 0);
-	  return \"SLR	%0,%0\;SLR	%N0,%N0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT
-  	  && (unsigned) INTVAL (operands[1]) < 4096)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 6, 0);
-	  return \"SLR	%0,%0\;LA	%N0,%c1\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT)
-	{
-	  CC_STATUS_SET (operands[0], operands[1]);
-	  mvs_check_page (0, 8, 0);
-	  return \"L	%0,%1\;SRDA	%0,32\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"LM	%0,%N0,%1\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"STD	%1,%0\";
-    }
-  else if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"STM	%1,%N1,%0\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"MVC	%O0(8,%R0),%1\";
-}")
-
-(define_insn "movdi"
-  [(set (match_operand:DI 0 "general_operand" "=dm")
-	(match_operand:DI 1 "general_operand" "dim*fF"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 8, 0);
-	  return \"STD	%1,140(,13)\;LM	%0,%N0,140(13)\";
-	}
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 4, 0);
-	  return \"LR	%0,%1\;LR	%N0,%N1\";
-	}
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 4, 0);
-	  return \"SLR	%0,%0\;SLR	%N0,%N0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT
-  	  && (unsigned) INTVAL (operands[1]) < 4096)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 6, 0);
-	  return \"SLR	%0,%0\;LA	%N0,%c1\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT)
-	{
-	  CC_STATUS_SET (operands[0], operands[1]);
-	  mvs_check_page (0, 8, 0);
-	  return \"L	%0,%1\;SRDA	%0,32\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"LM	%0,%N0,%1\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"STD	%1,%0\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"STM	%1,%N1,%0\";
-}")
-
-;
-; movsi instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:SI 0 "r_or_s_operand" "=dm,dm")
-        (match_operand:SI 1 "r_or_s_operand" "dim,*fF"))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 8, 0);
-	  return \"STE	%1,140(,13)\;L	%0,140(,13)\";
-	}
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 2, 0);
-	  return \"LR	%0,%1\";
-	}
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 2, 0);
-	  return \"SLR	%0,%0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT
- 	  && (unsigned) INTVAL (operands[1]) < 4096)
-	{
-	  mvs_check_page (0, 4, 0);
-	  return \"LA	%0,%c1\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"L	%0,%1\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"STE	%1,%0\";
-    }
-  else if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"ST	%1,%0\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"MVC	%O0(4,%R0),%1\";
-}")
-
-(define_insn "movsi"
-  [(set (match_operand:SI 0 "general_operand" "=d,dm")
-	(match_operand:SI 1 "general_operand" "dimF,*fd"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 8, 0);
-	  return \"STE	%1,140(,13)\;L	%0,140(,13)\";
-	}
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 2, 0);
-	  return \"LR	%0,%1\";
-	}
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 2, 0);
-	  return \"SLR	%0,%0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT
-	  && (unsigned) INTVAL (operands[1]) < 4096)
-	{
-	  mvs_check_page (0, 4, 0);
-	  return \"LA	%0,%c1\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"L	%0,%1\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"STE	%1,%0\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"ST	%1,%0\";
-}")
-
-;(define_expand "movsi"
-;  [(set (match_operand:SI 0 "general_operand" "=d,dm")
-;	(match_operand:SI 1 "general_operand" "dimF,*fd"))]
-;  ""
-;  "
-;{
-;  rtx op0, op1;
-;
-;  op0 = operands[0];
-;  if (GET_CODE (op0) == CONST
-;      && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SYMBOL_REF
-;      && SYMBOL_REF_FLAG (XEXP (XEXP (op0, 0), 0)))
-;    {
-;      op0 = gen_rtx (MEM, SImode, copy_to_mode_reg (SImode, XEXP (op0, 0)));
-;    }
-;
-;  op1 = operands[1];
-;  if (GET_CODE (op1) == CONST
-;      && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF
-;      && SYMBOL_REF_FLAG (XEXP (XEXP (op1, 0), 0)))
-;    {
-;      op1 = gen_rtx (MEM, SImode, copy_to_mode_reg (SImode, XEXP (op1, 0)));
-;    }
-;
-;  emit_insn (gen_rtx (SET, VOIDmode, op0, op1));
-;  DONE;
-;}")
-
-;
-; movhi instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_or_s_operand" "=g")
-        (match_operand:HI 1 "r_or_s_operand" "g"))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 2, 0);
-	  return \"LR	%0,%1\";
-	}
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 2, 0);
-	  return \"SLR	%0,%0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT
-	  && (unsigned) INTVAL (operands[1]) < 4096)
-	{
-	  mvs_check_page (0, 4, 0);
-	  return \"LA	%0,%c1\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT)
-	{
-	  mvs_check_page (0, 4, 0);
-	  return \"LH	%0,%H1\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"LH	%0,%1\";
-    }
-  else if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"STH	%1,%0\";
-    }
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      mvs_check_page (0, 6, 0);
-      return \"MVC	%O0(2,%R0),%H1\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"MVC	%O0(2,%R0),%1\";
-}")
-
-(define_insn "movhi"
-  [(set (match_operand:HI 0 "general_operand" "=d,m")
-	(match_operand:HI 1 "general_operand" "g,d"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 2, 0);
-	  return \"LR	%0,%1\";
-	}
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 2, 0);
-	  return \"SLR	%0,%0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT
-	  && (unsigned) INTVAL (operands[1]) < 4096)
-	{
-	  mvs_check_page (0, 4, 0);
-	  return \"LA	%0,%c1\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT)
-	{
-	  mvs_check_page (0, 4, 0);
-	  return \"LH	%0,%H1\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"LH	%0,%1\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"STH	%1,%0\";
-}")
-
-;
-; movqi instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:QI 0 "r_or_s_operand" "=g")
-	(match_operand:QI 1 "r_or_s_operand" "g"))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 2, 0);
-	  return \"LR	%0,%1\";
-	}
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 2, 0);
-	  return \"SLR	%0,%0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT)
-	{
-	  if (INTVAL (operands[1]) >= 0)
-	    {
-	      mvs_check_page (0, 4, 0);
-	      return \"LA	%0,%c1\";
-	    }
-	  mvs_check_page (0, 4, 0);
-	  return \"L	%0,=F'%c1'\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"IC	%0,%1\";
-    }
-  else if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"STC	%1,%0\";
-    }
-  else if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"MVI	%0,%B1\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"MVC	%O0(1,%R0),%1\";
-}")
-
-(define_insn "movqi"
-  [(set (match_operand:QI 0 "general_operand" "=d,m")
-	(match_operand:QI 1 "general_operand" "g,d"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 2, 0);
-	  return \"LR	%0,%1\";
-	}
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 2, 0);
-	  return \"SLR	%0,%0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT)
-	{
-	  if (INTVAL (operands[1]) >= 0)
-	    {
-	      mvs_check_page (0, 4, 0);
-	      return \"LA	%0,%c1\";
-	    }
-	  mvs_check_page (0, 4, 0);
-	  return \"L	%0,=F'%c1'\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"IC	%0,%1\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"STC	%1,%0\";
-}")
-
-;
-; movestrictqi instruction pattern(s).
-;
-
-(define_insn "movestrictqi"
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "=d"))
-	(match_operand:QI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 8, 0);
-      return \"STC	%1,140(,13)\;IC	%0,140(,13)\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"IC	%0,%1\";
-}")
-
-;
-; movstricthi instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "register_operand" "=d"))
-	(match_operand:HI 1 "r_or_s_operand" "g"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 8, 0);
-      return \"STH	%1,140(,13)\;ICM	%0,3,140(13)\";
-    }
-  else if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"ICM	%0,3,%H1\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"ICM	%0,3,%1\";
-}")
-
-(define_insn "movestricthi"
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "=dm"))
-	(match_operand:HI 1 "general_operand" "d"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 8, 0);
-      return \"STH	%1,140(,13)\;ICM	%0,3,140(13)\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"STH	%1,%0\";
-}")
-
-;
-; movdf instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:DF 0 "r_or_s_operand" "=fm,fm,*dm")
-        (match_operand:DF 1 "r_or_s_operand" "fmF,*dm,fmF"))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 2, 0);
-	  return \"LDR	%0,%1\";
-	}
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 8, 0);
-	  return \"STM	%1,%N1,140(13)\;LD	%0,140(,13)\";
-	}
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_SET (operands[0], operands[1]);
-	  mvs_check_page (0, 2, 0);
-	  return \"SDR	%0,%0\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"LD	%0,%1\";
-    }
-  if (REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 12, 0);
-	  return \"STD	%1,140(,13)\;LM	%0,%N0,140(13)\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"LM	%0,%N0,%1\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"STD	%1,%0\";
-    }
-  else if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"STM	%1,%N1,%0\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"MVC	%O0(8,%R0),%1\";
-}")
-
-(define_insn "movdf"
-  [(set (match_operand:DF 0 "general_operand" "=f,fm,m,*d")
-	(match_operand:DF 1 "general_operand" "fmF,*d,f,fmF"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 2, 0);
-	  return \"LDR	%0,%1\";
-	}
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 8, 0);
-	  return \"STM	%1,%N1,140(13)\;LD	%0,140(,13)\";
-	}
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_SET (operands[0], operands[1]);
-	  mvs_check_page (0, 2, 0);
-	  return \"SDR	%0,%0\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"LD	%0,%1\";
-    }
-  else if (REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 12, 0);
-	  return \"STD	%1,140(,13)\;LM	%0,%N0,140(13)\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"LM	%0,%N0,%1\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"STD	%1,%0\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"STM	%1,%N1,%0\";
-}")
-
-;
-; movsf instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:SF 0 "r_or_s_operand" "=fm,fm,*dm")
-        (match_operand:SF 1 "r_or_s_operand" "fmF,*dm,fmF"))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 2, 0);
-	  return \"LER	%0,%1\";
-	}
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 8, 0);
-	  return \"ST	%1,140(,13)\;LE	%0,140(,13)\";
-	}
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_SET (operands[0], operands[1]);
-	  mvs_check_page (0, 2, 0);
-	  return \"SER	%0,%0\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"LE	%0,%1\";
-    }
-  else if (REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 8, 0);
-	  return \"STE	%1,140(,13)\;L	%0,140(,13)\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"L	%0,%1\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"STE	%1,%0\";
-    }
-  else if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"ST	%1,%0\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"MVC	%O0(4,%R0),%1\";
-}")
-
-(define_insn "movsf"
-  [(set (match_operand:SF 0 "general_operand" "=f,fm,m,*d")
-	(match_operand:SF 1 "general_operand" "fmF,*d,f,fmF"))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 2, 0);
-	  return \"LER	%0,%1\";
-	}
-      if (REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 8, 0);
-	  return \"ST	%1,140(,13)\;LE	%0,140(,13)\";
-	}
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_SET (operands[0], operands[1]);
-	  mvs_check_page (0, 2, 0);
-	  return \"SER	%0,%0\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"LE	%0,%1\";
-    }
-  else if (REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	{
-	  mvs_check_page (0, 8, 0);
-	  return \"STE	%1,140(,13)\;L	%0,140(,13)\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"L	%0,%1\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"STE	%1,%0\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"ST	%1,%0\";
-}")
-
-;
-; movstrsi instruction pattern(s).
-;
-
-(define_expand "movstrsi"
-  [(set (match_operand:BLK 0 "general_operand" "")
-        (match_operand:BLK 1 "general_operand" ""))
-   (use (match_operand:SI 2 "general_operand" ""))
-   (match_operand 3 "" "")]
-   ""
-   "
-{
-  rtx op0, op1;
-
-  op0 = XEXP (operands[0], 0);
-  if (GET_CODE (op0) == REG
-      || (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == REG
-	  && GET_CODE (XEXP (op0, 1)) == CONST_INT
-	  && (unsigned) INTVAL (XEXP (op0, 1)) < 4096))
-    op0 = operands[0];
-  else
-    op0 = change_address (operands[0], VOIDmode,
-			  copy_to_mode_reg (SImode, op0));
-
-  op1 = XEXP (operands[1], 0);
-  if (GET_CODE (op1) == REG
-      || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG
-	  && GET_CODE (XEXP (op1, 1)) == CONST_INT
-	  && (unsigned) INTVAL (XEXP (op1, 1)) < 4096))
-    op1 = operands[1];
-  else
-    op1 = change_address (operands[1], VOIDmode,
-			  copy_to_mode_reg (SImode, op1));
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 256)
-    emit_insn (gen_rtx (PARALLEL, VOIDmode,
-			gen_rtvec (2,
-				   gen_rtx (SET, VOIDmode, op0, op1),
-				   gen_rtx (USE, VOIDmode, operands[2]))));
-
-  else
-    {
-      rtx reg1 = gen_reg_rtx (DImode);
-      rtx reg2 = gen_reg_rtx (DImode);
-      rtx subreg = gen_rtx (SUBREG, SImode, reg1, 1);
-
-      emit_insn (gen_rtx (SET, VOIDmode, subreg, operands[2]));
-      emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, reg2, 1),
-			  subreg));
-      emit_insn (gen_rtx (PARALLEL, VOIDmode,
-			  gen_rtvec (5,
-				     gen_rtx (SET, VOIDmode, op0, op1),
-				     gen_rtx (USE, VOIDmode, reg1),
-				     gen_rtx (USE, VOIDmode, reg2),
-				     gen_rtx (CLOBBER, VOIDmode, reg1),
-				     gen_rtx (CLOBBER, VOIDmode, reg2))));
-    }
-  DONE;
-}")
-
-; Move a block that is less than 256 bytes in length.
-
-(define_insn ""
-  [(set (match_operand:BLK 0 "s_operand" "=m")
-	(match_operand:BLK 1 "s_operand" "m"))
-   (use (match_operand 2 "immediate_operand" "I"))]
-  "((unsigned) INTVAL (operands[2]) < 256)"
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 6, 0);
-  return \"MVC	%O0(%c2,%R0),%1\";
-}")
-
-; Move a block that is larger than 255 bytes in length.
-
-(define_insn ""
-  [(set (match_operand:BLK 0 "general_operand" "=m")
-        (match_operand:BLK 1 "general_operand" "m"))
-   (use (match_operand:DI 2 "register_operand" "d"))
-   (use (match_operand:DI 3 "register_operand" "d"))
-   (clobber (match_dup 2))
-   (clobber (match_dup 3))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 10, 0);
-  return \"LA	%2,%0\;LA	%3,%1\;MVCL	%2,%3\";
-}")
-
-;;
-;;- Conversion instructions.
-;;
-
-;
-; extendsidi2 instruction pattern(s).
-;
-
-(define_expand "extendsidi2"
-  [(set (match_operand:DI 0 "general_operand" "")
-        (sign_extend:DI (match_operand:SI 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) != CONST_INT)
-    {
-      emit_insn (gen_rtx (SET, VOIDmode,
-		  operand_subword (operands[0], 0, 1, DImode), operands[1]));
-      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-			gen_rtx (ASHIFTRT, DImode, operands[0],
-				GEN_INT (32))));
-    }
-  else
-    {
-      if (INTVAL (operands[1]) < 0)
-	{
-	  emit_insn (gen_rtx (SET, VOIDmode,
-				  operand_subword (operands[0], 0, 1, DImode),
-			       GEN_INT (-1)));
-        }
-      else
-	{
-	  emit_insn (gen_rtx (SET, VOIDmode,
-				operand_subword (operands[0], 0, 1, DImode),
-			       GEN_INT (0)));
-        }
-      emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (SImode, operands[0]),
-			   operands[1]));
-    }
-  DONE;
-}")
-
-;
-; extendhisi2 instruction pattern(s).
-;
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=d,m")
-	(sign_extend:SI (match_operand:HI 1 "general_operand" "g,d")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      if (REG_P (operands[1]))
-        if (REGNO (operands[0]) != REGNO (operands[1]))
-	  {
-	    mvs_check_page (0, 2, 0);
-            return \"LR	%0,%1\;SLL	%0,16\;SRA	%0,16\";
-	  }
-        else
-          return \"\"; /* Should be empty.  16-bits regs are always 32-bits.  */
-      if (operands[1] == const0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 2, 0);
-	  return \"SLR	%0,%0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT
- 	  && (unsigned) INTVAL (operands[1]) < 4096)
-	{
-	  mvs_check_page (0, 4, 0);
-	  return \"LA	%0,%c1\";
-	}
-      if (GET_CODE (operands[1]) == CONST_INT)
-	{
-	  mvs_check_page (0, 4, 0);
-	  return \"LH	%0,%H1\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"LH	%0,%1\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"SLL	%1,16\;SRA	%1,16\;ST	%1,%0\";
-}")
-
-;
-; extendqisi2 instruction pattern(s).
-;
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(sign_extend:SI (match_operand:QI 1 "general_operand" "0mi")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_SET (operands[0], operands[1]);
-  if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 8, 0);
-      return \"SLL	%0,24\;SRA	%0,24\";
-    }
-  if (s_operand (operands[1]))
-    {
-      mvs_check_page (0, 8, 0);
-      return \"ICM	%0,8,%1\;SRA	%0,24\";
-    }
-  mvs_check_page (0, 12, 0);
-  return \"IC	%0,%1\;SLL	%0,24\;SRA	%0,24\";
-}")
-
-;
-; extendqihi2 instruction pattern(s).
-;
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(sign_extend:HI (match_operand:QI 1 "general_operand" "0m")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_SET (operands[0], operands[1]);
-  if (REG_P (operands[1]))
-    {
-      mvs_check_page (0, 8, 0);
-      return \"SLL	%0,24\;SRA	%0,24\";
-    }
-  if (s_operand (operands[1]))
-    {
-      mvs_check_page (0, 8, 0);
-      return \"ICM	%0,8,%1\;SRA	%0,24\";
-    }
-  mvs_check_page (0, 12, 0);
-  return \"IC	%0,%1\;SLL	%0,24\;SRA	%0,24\";
-}")
-
-;
-; zero_extendsidi2 instruction pattern(s).
-;
-
-(define_expand "zero_extendsidi2"
-  [(set (match_operand:DI 0 "general_operand" "")
-        (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
-  ""
-  "
-{
-      emit_insn (gen_rtx (SET, VOIDmode,
-		  operand_subword (operands[0], 0, 1, DImode), operands[1]));
-      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-			gen_rtx (LSHIFTRT, DImode, operands[0],
-				GEN_INT (32))));
-  DONE;
-}")
-
-;
-; zero_extendhisi2 instruction pattern(s).
-;
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(zero_extend:SI (match_operand:HI 1 "general_operand" "0")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_SET (operands[0], operands[1]);
-  mvs_check_page (0, 4, 4);
-  return \"N	%1,=X'0000FFFF'\";
-}")
-
-;
-; zero_extendqisi2 instruction pattern(s).
-;
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=d,&d")
-	(zero_extend:SI (match_operand:QI 1 "general_operand" "0i,m")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[1]))
-    {
-      CC_STATUS_SET (operands[0], operands[1]);
-      mvs_check_page (0, 4, 4);
-      return \"N	%0,=X'000000FF'\";
-    }
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"LA	%0,%c1\";
-    }
-  CC_STATUS_INIT;
-  mvs_check_page (0, 8, 0);
-  return \"SLR	%0,%0\;IC	%0,%1\";
-}")
-
-;
-; zero_extendqihi2 instruction pattern(s).
-;
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=d,&d")
-	(zero_extend:HI (match_operand:QI 1 "general_operand" "0i,m")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[1]))
-    {
-      CC_STATUS_SET (operands[0], operands[1]);
-      mvs_check_page (0, 4, 4);
-      return \"N	%0,=X'000000FF'\";
-    }
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"LA	%0,%c1\";
-    }
-  CC_STATUS_INIT;
-  mvs_check_page (0, 8, 0);
-  return \"SLR	%0,%0\;IC	%0,%1\";
-}")
-
-;
-; truncsihi2 instruction pattern(s).
-;
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "general_operand" "=d,m")
-	(truncate:HI (match_operand:SI 1 "general_operand" "0,d")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      CC_STATUS_SET (operands[0], operands[1]);
-      mvs_check_page (0, 8, 0);
-      return \"SLL	%0,16\;SRA	%0,16\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"STH	%1,%0\";
-}")
-
-;
-; fix_truncdfsi2 instruction pattern(s).
-;
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-        (fix:SI (truncate:DF (match_operand:DF 1 "general_operand" "f"))))
-	(clobber (reg:DF 16))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  if (REGNO (operands[1]) == 16)
-    {
-      mvs_check_page (0, 12, 8);
-      return \"AD	0,=XL8'4F08000000000000'\;STD	0,140(,13)\;L	%0,144(,13)\";
-    }
-  mvs_check_page (0, 14, 8);
-  return \"LDR	0,%1\;AD	0,=XL8'4F08000000000000'\;STD	0,140(,13)\;L	%0,144(,13)\";
-}")
-
-;
-; floatsidf2 instruction pattern(s).
-;
-; Uses the float field of the TCA.
-;
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-        (float:DF (match_operand:SI 1 "general_operand" "d")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  mvs_check_page (0, 16, 8);
-  return \"ST	%1,508(,12)\;XI	508(12),128\;LD	%0,504(,12)\;SD	%0,=XL8'4E00000080000000'\";
-}")
-
-;
-; truncdfsf2 instruction pattern(s).
-;
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-        (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 2, 0);
-  return \"LRER	%0,%1\";
-}")
-
-;
-; extendsfdf2 instruction pattern(s).
-;
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-        (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_SET (0, const0_rtx);
-  if (FP_REG_P (operands[1]))
-    {
-      if (REGNO (operands[0]) == REGNO (operands[1]))
-	{
-	  mvs_check_page (0, 10, 0);
-	  return \"STE	%1,140(,13)\;SDR	%0,%0\;LE	%0,140(,13)\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"SDR	%0,%0\;LER	%0,%1\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"SDR	%0,%0\;LE	%0,%1\";
-}")
-
-;;
-;;- Add instructions.
-;;
-
-;
-; adddi3 instruction pattern(s).
-;
-
-(define_expand "adddi3"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(plus:DI (match_operand:DI 1 "general_operand" "")
-		 (match_operand:DI 2 "general_operand" "")))]
-  ""
-  "
-{
-  rtx label = gen_label_rtx ();
-  rtx op0_high = operand_subword (operands[0], 0, 1, DImode);
-  rtx op0_low = gen_lowpart (SImode, operands[0]);
-	
-  emit_insn (gen_rtx (SET, VOIDmode, op0_high,
-		    gen_rtx (PLUS, SImode,
-			    operand_subword (operands[1], 0, 1, DImode),
-			    operand_subword (operands[2], 0, 1, DImode))));
-  emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
-	      gen_rtx (SET, VOIDmode, op0_low,
-		      gen_rtx (PLUS, SImode, gen_lowpart (SImode, operands[1]),
-			      gen_lowpart (SImode, operands[2]))),
-	      gen_rtx (USE, VOIDmode, gen_rtx (LABEL_REF, VOIDmode, label)))));
-  emit_insn (gen_rtx (SET, VOIDmode, op0_high,
-		    gen_rtx (PLUS, SImode, op0_high,
-			    GEN_INT (1))));
-  emit_label (label);
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(plus:SI (match_operand:SI 1 "general_operand" "%0")
-		 (match_operand:SI 2 "general_operand" "g")))
-   (use (label_ref (match_operand 3 "" "")))]
-  ""
-  "*
-{
-  int onpage;
-
-  check_label_emit ();
-  onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3]));
-  if (REG_P (operands[2]))
-    {
-      if (!onpage)
-	{
-	  mvs_check_page (0, 8, 4);
-	  return \"ALR	%0,%2\;L	14,=A(%l3)\;BCR	12,14\";
-	}
-      if (mvs_check_page (0, 6, 0))
-	{
-	  mvs_check_page (0, 2, 4);
-	  return \"ALR	%0,%2\;L	14,=A(%l3)\;BCR	12,14\";
-	}
-      return \"ALR	%0,%2\;BC	12,%l3\";
-    }
-  if (!onpage)
-    {
-      mvs_check_page (0, 10, 4);
-      return \"AL	%0,%2\;L	14,=A(%l3)\;BCR	12,14\";
-    }
-  if (mvs_check_page (0, 8 ,0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"AL	%0,%2\;L	14,=A(%l3)\;BCR	12,14\";
-    }
-  return \"AL	%0,%2\;BC	12,%l3\";
-}")
-
-;
-; addsi3 instruction pattern(s).
-;
-; The following insn is used when it is known that operand one is an address,
-; frame, stack or argument pointer, and operand two is a constant that is
-; small enough to fit in the displacement field.
-; Notice that we can't allow the frame pointer to used as a normal register
-; because of this insn.
-;
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(plus:SI (match_operand:SI 1 "general_operand" "%a")
-		 (match_operand:SI 2 "immediate_operand" "J")))]
-  "((REGNO (operands[1]) == FRAME_POINTER_REGNUM || REGNO (operands[1]) == ARG_POINTER_REGNUM || REGNO (operands[1]) == STACK_POINTER_REGNUM) && (unsigned) INTVAL (operands[2]) < 4096)"
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  mvs_check_page (0, 4, 0);
-  return \"LA	%0,%c2(,%1)\";
-}")
-
-; This insn handles additions that are relative to the frame pointer.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-         (plus:SI (match_operand:SI 1 "register_operand" "%a")
-                  (match_operand:SI 2 "immediate_operand" "i")))]
-  "REGNO (operands[1]) == FRAME_POINTER_REGNUM"
-  "*
-{
-  check_label_emit ();
-  if ((unsigned) INTVAL (operands[2]) < 4096)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"LA	%0,%c2(,%1)\";
-    }
-  if (REGNO (operands[1]) == REGNO (operands[0]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"A	%0,%2\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"L	%0,%2\;AR	%0,%1\";
-}")
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(plus:SI (match_operand:SI 1 "general_operand" "%0")
-		 (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"AR	%0,%2\";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) == -1)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 2, 0);
-	  return \"BCTR	%0,0\";
-	}
-    }
-  mvs_check_page (0, 4, 0);
-  return \"A	%0,%2\";
-}")
-
-;
-; addhi3 instruction pattern(s).
-;
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(plus:HI (match_operand:HI 1 "general_operand" "%0")
-		 (match_operand:HI 2 "general_operand" "dmi")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 8, 0);
-      return \"STH	%2,140(,13)\;AH	%0,140(,13)\";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) == -1)
-	{
-	  CC_STATUS_INIT;
-	  mvs_check_page (0, 2, 0);
-	  return \"BCTR	%0,0\";
-	}
-      mvs_check_page (0, 4, 0);
-      return \"AH	%0,%H2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"AH	%0,%2\";
-}")
-
-;
-; addqi3 instruction pattern(s).
-;
-
-(define_insn "addqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(plus:QI (match_operand:QI 1 "general_operand" "%a")
-		 (match_operand:QI 2 "general_operand" "ai")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  mvs_check_page (0, 4, 0);
-  if (REG_P (operands[2]))
-    return \"LA	%0,0(%1,%2)\";
-  return \"LA	%0,%B2(,%1)\";
-}")
-
-;
-; adddf3 instruction pattern(s).
-;
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(plus:DF (match_operand:DF 1 "general_operand" "%0")
-		 (match_operand:DF 2 "general_operand" "fmF")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"ADR	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"AD	%0,%2\";
-}")
-
-;
-; addsf3 instruction pattern(s).
-;
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(plus:SF (match_operand:SF 1 "general_operand" "%0")
-		 (match_operand:SF 2 "general_operand" "fmF")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"AER	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"AE	%0,%2\";
-}")
-
-;;
-;;- Subtract instructions.
-;;
-
-;
-; subdi3 instruction pattern(s).
-;
-
-(define_expand "subdi3"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(minus:DI (match_operand:DI 1 "general_operand" "")
-		  (match_operand:DI 2 "general_operand" "")))]
-  ""
-  "
-{
-  rtx label = gen_label_rtx ();
-  rtx op0_high = operand_subword (operands[0], 0, 1, DImode);
-  rtx op0_low = gen_lowpart (SImode, operands[0]);
-	
-  emit_insn (gen_rtx (SET, VOIDmode, op0_high,
-		    gen_rtx (MINUS, SImode,
-			      operand_subword (operands[1], 0, 1, DImode),
-			      operand_subword (operands[2], 0, 1, DImode))));
-  emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
-		    gen_rtx (SET, VOIDmode, op0_low,
-			      gen_rtx (MINUS, SImode,
-				      gen_lowpart (SImode, operands[1]),
-				      gen_lowpart (SImode, operands[2]))),
-		    gen_rtx (USE, VOIDmode,
-			      gen_rtx (LABEL_REF, VOIDmode, label)))));
-  emit_insn (gen_rtx (SET, VOIDmode, op0_high,
-		      gen_rtx (MINUS, SImode, op0_high,
-			      GEN_INT (1))));
-  emit_label (label);
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(minus:SI (match_operand:SI 1 "general_operand" "0")
-		  (match_operand:SI 2 "general_operand" "g")))
-   (use (label_ref (match_operand 3 "" "")))]
-  ""
-  "*
-{
-  int onpage;
-
-  check_label_emit ();
-  CC_STATUS_INIT;
-  onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3]));
-  if (REG_P (operands[2]))
-    {
-      if (!onpage)
-	{
-	  mvs_check_page (0, 8, 4);
-	  return \"SLR	%0,%2\;L	14,=A(%l3)\;BCR	12,14\";
-	}
-      if (mvs_check_page (0, 6, 0))
-	{
-	  mvs_check_page (0, 2, 4);
-	  return \"SLR	%0,%2\;L	14,=A(%l3)\;BCR	12,14\";
-	}
-      return \"SLR	%0,%2\;BC	12,%l3\";
-    }
-  if (!onpage)
-    {
-      mvs_check_page (0, 10, 4);
-      return \"SL	%0,%2\;L	14,=A(%l3)\;BCR	12,14\";
-    }
-  if (mvs_check_page (0, 8, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"SL	%0,%2\;L	14,=A(%l3)\;BCR	12,14\";
-    }
-  return \"SL	%0,%2\;BC	12,%l3\";
-}")
-
-;
-; subsi3 instruction pattern(s).
-;
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(minus:SI (match_operand:SI 1 "general_operand" "0")
-		  (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"SR	%0,%2\";
-    }
-  if (operands[2] == const1_rtx)
-    {
-      CC_STATUS_INIT;
-      mvs_check_page (0, 2, 0);
-      return \"BCTR	%0,0\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"S	%0,%2\";
-}")
-
-;
-; subhi3 instruction pattern(s).
-;
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(minus:HI (match_operand:HI 1 "general_operand" "0")
-		  (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 8, 0);
-      return \"STH	%2,140(,13)\;SH	%0,140(,13)\";
-    }
-  if (operands[2] == const1_rtx)
-    {
-      CC_STATUS_INIT;
-      mvs_check_page (0, 2, 0);
-      return \"BCTR	%0,0\";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"SH	%0,%H2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"SH	%0,%2\";
-}")
-
-;
-; subqi3 instruction pattern(s).
-;
-
-(define_expand "subqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(minus:QI (match_operand:QI 1 "general_operand" "0")
-		  (match_operand:QI 2 "general_operand" "di")))]
-  ""
-  "
-{
-  if (REG_P (operands[2]))
-    {
-      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-			gen_rtx (MINUS, QImode, operands[1], operands[2])));
-    }
-  else
-    {
-      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-			gen_rtx (PLUS, QImode, operands[1],
-				 negate_rtx (QImode, operands[2]))));
-    }
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=d")
-	(minus:QI (match_operand:QI 1 "register_operand" "0")
-		 (match_operand:QI 2 "register_operand" "d")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  mvs_check_page (0, 2, 0);
-  return \"SR	%0,%2\";
-}")
-
-;
-; subdf3 instruction pattern(s).
-;
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(minus:DF (match_operand:DF 1 "general_operand" "0")
-		  (match_operand:DF 2 "general_operand" "fmF")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"SDR	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"SD	%0,%2\";
-}")
-
-;
-; subsf3 instruction pattern(s).
-;
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(minus:SF (match_operand:SF 1 "general_operand" "0")
-		  (match_operand:SF 2 "general_operand" "fmF")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"SER	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"SE	%0,%2\";
-}")
-
-;;
-;;- Multiply instructions.
-;;
-
-;
-; mulsi3 instruction pattern(s).
-;
-
-(define_expand "mulsi3"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(mult:SI (match_operand:SI 1 "general_operand" "")
-		 (match_operand:SI 2 "general_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == CONST_INT
-      && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
-    {
-      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-			  gen_rtx (MULT, SImode, operands[2], operands[1])));
-    }
-  else if (GET_CODE (operands[2]) == CONST_INT
-	   && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))
-    {
-      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-			  gen_rtx (MULT, SImode, operands[1], operands[2])));
-    }
-  else
-    {
-      rtx r = gen_reg_rtx (DImode);
-
-      emit_insn (gen_rtx (SET, VOIDmode,
-			  gen_rtx (SUBREG, SImode, r, 1), operands[1]));
-      emit_insn (gen_rtx (SET, VOIDmode, r,
-			  gen_rtx (MULT, SImode, r, operands[2])));
-      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-			  gen_rtx (SUBREG, SImode, r, 1)));
-    }
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(mult:SI (match_operand:SI 1 "general_operand" "%0")
-		 (match_operand:SI 2 "immediate_operand" "K")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 4, 0);
-  return \"MH	%0,%H2\";
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(mult:SI (match_operand:DI 1 "general_operand" "%0")
-		 (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"MR	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"M	%0,%2\";
-}")
-
-;
-; muldf3 instruction pattern(s).
-;
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(mult:DF (match_operand:DF 1 "general_operand" "%0")
-		 (match_operand:DF 2 "general_operand" "fmF")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"MDR	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"MD	%0,%2\";
-}")
-
-;
-; mulsf3 instruction pattern(s).
-;
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(mult:SF (match_operand:SF 1 "general_operand" "%0")
-		 (match_operand:SF 2 "general_operand" "fmF")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"MER	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"ME	%0,%2\";
-}")
-
-;;
-;;- Divide instructions.
-;;
-
-;
-; divsi3 instruction pattern(s).
-;
-
-(define_expand "divsi3"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(div:SI (match_operand:SI 1 "general_operand" "")
-		(match_operand:SI 2 "general_operand" "")))]
-  ""
-  "
-{
-  rtx r = gen_reg_rtx (DImode);
-
-  emit_insn (gen_extendsidi2 (r, operands[1]));
-  emit_insn (gen_rtx (SET, VOIDmode, r,
-			gen_rtx (DIV, SImode, r, operands[2])));
-  emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-			gen_rtx (SUBREG, SImode, r, 1)));
-  DONE;
-}")
-
-
-;
-; udivsi3 instruction pattern(s).
-;
-
-(define_expand "udivsi3"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(udiv:SI (match_operand:SI 1 "general_operand" "")
-		 (match_operand:SI 2 "general_operand" "")))]
-  ""
-  "
-{
-  rtx dr = gen_reg_rtx (DImode);
-  rtx dr_0 = gen_rtx (SUBREG, SImode, dr, 0);
-  rtx dr_1 = gen_rtx (SUBREG, SImode, dr, 1);
-
-
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) > 0)
-	{
-	  emit_insn (gen_zero_extendsidi2 (dr, operands[1]));
-	  emit_insn (gen_rtx (SET, VOIDmode, dr,
-			gen_rtx (DIV, SImode, dr, operands[2])));
-	}
-      else
-	{
-	  rtx label1 = gen_label_rtx ();
-
-	  emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1]));
-	  emit_insn (gen_rtx (SET, VOIDmode, dr_1, const0_rtx));
-	  emit_insn (gen_cmpsi (dr_0, operands[2]));
-	  emit_jump_insn (gen_bltu (label1));
-	  emit_insn (gen_rtx (SET, VOIDmode, dr_1, const1_rtx));
-	  emit_label (label1);
-	}
-    }
-  else
-    {
-      rtx label1 = gen_label_rtx ();
-      rtx label2 = gen_label_rtx ();
-      rtx label3 = gen_label_rtx ();
-      rtx sr = gen_reg_rtx (SImode);
-
-      emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1]));
-      emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2]));
-      emit_insn (gen_rtx (SET, VOIDmode, dr_1, const0_rtx));
-      emit_insn (gen_cmpsi (sr, dr_0));
-      emit_jump_insn (gen_bgtu (label3));
-      emit_insn (gen_cmpsi (sr, const1_rtx));
-      emit_jump_insn (gen_blt (label2));
-      emit_jump_insn (gen_beq (label1));
-      emit_insn (gen_rtx (SET, VOIDmode, dr,
-			  gen_rtx (LSHIFTRT, DImode, dr,
-				    GEN_INT (32))));
-      emit_insn (gen_rtx (SET, VOIDmode, dr,
-		    gen_rtx (DIV, SImode, dr, sr)));
-      emit_jump_insn (gen_jump (label3));
-      emit_label (label1);
-      emit_insn (gen_rtx (SET, VOIDmode, dr_1, dr_0));
-      emit_jump_insn (gen_jump (label3));
-      emit_label (label2);
-      emit_insn (gen_rtx (SET, VOIDmode, dr_1, const1_rtx));
-      emit_label (label3);
-    }
-  emit_insn (gen_rtx (SET, VOIDmode, operands[0], dr_1));
-
-  DONE;
-}")
-
-; This is used by divsi3 & udivsi3.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(div:SI (match_operand:DI 1 "register_operand" "0")
-		(match_operand:SI 2 "general_operand" "")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"DR	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"D	%0,%2\";
-}")
-
-;
-; divdf3 instruction pattern(s).
-;
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-        (div:DF (match_operand:DF 1 "general_operand" "0")
-                (match_operand:DF 2 "general_operand" "fmF")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"DDR	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"DD	%0,%2\";
-}")
-
-;
-; divsf3 instruction pattern(s).
-;
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-        (div:SF (match_operand:SF 1 "general_operand" "0")
-                (match_operand:SF 2 "general_operand" "fmF")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (FP_REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"DER	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"DE	%0,%2\";
-}")
-
-;;
-;;- Modulo instructions.
-;;
-
-;
-; modsi3 instruction pattern(s).
-;
-
-(define_expand "modsi3"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(mod:SI (match_operand:SI 1 "general_operand" "")
-		(match_operand:SI 2 "general_operand" "")))]
-  ""
-  "
-{
-  rtx r = gen_reg_rtx (DImode);
-
-  emit_insn (gen_extendsidi2 (r, operands[1]));
-  emit_insn (gen_rtx (SET, VOIDmode, r,
-			gen_rtx (MOD, SImode, r, operands[2])));
-  emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-			gen_rtx (SUBREG, SImode, r, 0)));
-  DONE;
-}")
-
-;
-; umodsi3 instruction pattern(s).
-;
-
-(define_expand "umodsi3"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(umod:SI (match_operand:SI 1 "general_operand" "")
-		 (match_operand:SI 2 "general_operand" "")))]
-  ""
-  "
-{
-  rtx dr = gen_reg_rtx (DImode);
-  rtx dr_0 = gen_rtx (SUBREG, SImode, dr, 0);
-  rtx dr_1 = gen_rtx (SUBREG, SImode, dr, 1);
-
-  emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1]));
-
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) > 0)
-	{
-	  emit_insn (gen_rtx (SET, VOIDmode, dr,
-			      gen_rtx (LSHIFTRT, DImode, dr,
-					GEN_INT (32))));
-	  emit_insn (gen_rtx (SET, VOIDmode, dr,
-			gen_rtx (MOD, SImode, dr, operands[2])));
-	}
-      else
-	{
-	  rtx label1 = gen_label_rtx ();
-	  rtx sr = gen_reg_rtx (SImode);
-
-	  emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2]));
-	  emit_insn (gen_cmpsi (dr_0, sr));
-	  emit_jump_insn (gen_bltu (label1));
-	  emit_insn (gen_rtx (SET, VOIDmode, sr, gen_rtx (ABS, SImode, sr)));
-	  emit_insn (gen_rtx (SET, VOIDmode, dr_0,
-			      gen_rtx (PLUS, SImode, dr_0, sr)));
-	  emit_label (label1);
-	}
-    }
-  else
-    {
-      rtx label1 = gen_label_rtx ();
-      rtx label2 = gen_label_rtx ();
-      rtx label3 = gen_label_rtx ();
-      rtx sr = gen_reg_rtx (SImode);
-
-      emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1]));
-      emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2]));
-      emit_insn (gen_cmpsi (sr, dr_0));
-      emit_jump_insn (gen_bgtu (label3));
-      emit_insn (gen_cmpsi (sr, const1_rtx));
-      emit_jump_insn (gen_blt (label2));
-      emit_jump_insn (gen_beq (label1));
-      emit_insn (gen_rtx (SET, VOIDmode, dr,
-			  gen_rtx (LSHIFTRT, DImode, dr,
-				    GEN_INT (32))));
-      emit_insn (gen_rtx (SET, VOIDmode, dr, gen_rtx (MOD, SImode, dr, sr)));
-      emit_jump_insn (gen_jump (label3));
-      emit_label (label1);
-      emit_insn (gen_rtx (SET, VOIDmode, dr_0, const0_rtx));
-      emit_jump_insn (gen_jump (label3));
-      emit_label (label2);
-      emit_insn (gen_rtx (SET, VOIDmode, dr_0,
-			  gen_rtx (MINUS, SImode, dr_0, sr)));
-      emit_label (label3);
-
-    }
-  emit_insn (gen_rtx (SET, VOIDmode, operands[0], dr_0));
-
-  DONE;
-}")
-
-; This is used by modsi3 & umodsi3.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(mod:SI (match_operand:DI 1 "register_operand" "0")
-		(match_operand:SI 2 "general_operand" "")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"DR	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"D	%0,%2\";
-}")
-
-;;
-;;- And instructions.
-;;
-
-;
-; anddi3 instruction pattern(s).
-;
-
-;(define_expand "anddi3"
-;  [(set (match_operand:DI 0 "general_operand" "")
-;	(and:DI (match_operand:DI 1 "general_operand" "")
-;		(match_operand:DI 2 "general_operand" "")))]
-;  ""
-;  "
-;{
-;  rtx gen_andsi3();
-;
-;  emit_insn (gen_andsi3 (operand_subword (operands[0], 0, 1, DImode),
-;			 operand_subword (operands[1], 0, 1, DImode),
-;			 operand_subword (operands[2], 0, 1, DImode)));
-;  emit_insn (gen_andsi3 (gen_lowpart (SImode, operands[0]),
-;			 gen_lowpart (SImode, operands[1]),
-;			 gen_lowpart (SImode, operands[2])));
-;  DONE;
-;}")
-
-;
-; andsi3 instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:SI 0 "r_or_s_operand" "=d,m")
-	(and:SI (match_operand:SI 1 "r_or_s_operand" "%0,0")
-		(match_operand:SI 2 "r_or_s_operand" "g,mi")))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"NR	%0,%2\";
-    }
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"N	%0,%2\";
-    }
-  CC_STATUS_INIT;
-  mvs_check_page (0, 6, 0);
-  return \"NC	%O0(4,%R0),%2\";
-}")
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(and:SI (match_operand:SI 1 "general_operand" "%0")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"NR	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"N	%0,%2\";
-}")
-
-;
-; andhi3 instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_or_s_operand" "=d,m")
-	(and:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
-		(match_operand:HI 2 "r_or_s_operand" "di,mi")))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"NR	%0,%2\";
-    }
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"N	%0,%2\";
-    }
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 6, 0);
-      return \"NC	%O0(2,%R0),%H2\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"NC	%O0(2,%R0),%2\";
-}")
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(and:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "di")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"N	%0,%2\";
-    }
-  mvs_check_page (0, 2, 0);
-  return \"NR	%0,%2\";
-}")
-
-;
-; andqi3 instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:QI 0 "r_or_s_operand" "=d,m")
-	(and:QI (match_operand:QI 1 "r_or_s_operand" "%0,0")
-		(match_operand:QI 2 "r_or_s_operand" "di,mi")))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT; 
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"NR	%0,%2\";
-    }
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"N	%0,%2\";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"NI	%0,%B2\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"NC	%O0(1,%R0),%2\";
-}")
-
-(define_insn "andqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(and:QI (match_operand:QI 1 "general_operand" "%0")
-		(match_operand:QI 2 "general_operand" "di")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"N	%0,%2\";
-    }
-  mvs_check_page (0, 2, 0);
-  return \"NR	%0,%2\";
-}")
-
-;;
-;;- Bit set (inclusive or) instructions.
-;;
-
-;
-; iordi3 instruction pattern(s).
-;
-
-;(define_expand "iordi3"
-;  [(set (match_operand:DI 0 "general_operand" "")
-;	(ior:DI (match_operand:DI 1 "general_operand" "")
-;		(match_operand:DI 2 "general_operand" "")))]
-;  ""
-;  "
-;{
-;  rtx gen_iorsi3();
-;
-;  emit_insn (gen_iorsi3 (operand_subword (operands[0], 0, 1, DImode),
-;			 operand_subword (operands[1], 0, 1, DImode),
-;			 operand_subword (operands[2], 0, 1, DImode)));
-;  emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]),
-;			 gen_lowpart (SImode, operands[1]),
-;			 gen_lowpart (SImode, operands[2])));
-;  DONE;
-;}")
-
-;
-; iorsi3 instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:SI 0 "r_or_s_operand" "=d,m")
-	(ior:SI (match_operand:SI 1 "r_or_s_operand" "%0,0")
-		(match_operand:SI 2 "r_or_s_operand" "g,mi")))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"OR	%0,%2\";
-    }
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"O	%0,%2\";
-    }
-  CC_STATUS_INIT;
-  mvs_check_page (0, 6, 0);
-  return \"OC	%O0(4,%R0),%2\";
-}")
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(ior:SI (match_operand:SI 1 "general_operand" "%0")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"OR	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"O	%0,%2\";
-}")
-
-;
-; iorhi3 instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_or_s_operand" "=d,m")
-	(ior:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
-		(match_operand:HI 2 "r_or_s_operand" "di,mi")))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"OR	%0,%2\";
-    }
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"O	%0,%2\";
-    }
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 6, 0);
-      return \"OC	%O0(2,%R0),%H2\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"OC	%O0(2,%R0),%2\";
-}")
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(ior:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "di")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"O	%0,%2\";
-    }
-  mvs_check_page (0, 2, 0);
-  return \"OR	%0,%2\";
-}")
-
-;
-; iorqi3 instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:QI 0 "r_or_s_operand" "=d,m")
-	(ior:QI (match_operand:QI 1 "r_or_s_operand" "%0,0")
-		(match_operand:QI 2 "r_or_s_operand" "di,mi")))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"OR	%0,%2\";
-    }
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"O	%0,%2\";
-    }
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"OI	%0,%B2\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"OC	%O0(1,%R0),%2\";
-}")
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(ior:QI (match_operand:QI 1 "general_operand" "%0")
-		(match_operand:QI 2 "general_operand" "di")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"O	%0,%2\";
-    }
-  mvs_check_page (0, 2, 0);
-  return \"OR	%0,%2\";
-}")
-
-;;
-;;- Xor instructions.
-;;
-
-;
-; xordi3 instruction pattern(s).
-;
-
-;(define_expand "xordi3"
-;  [(set (match_operand:DI 0 "general_operand" "")
-;	(xor:DI (match_operand:DI 1 "general_operand" "")
-;		(match_operand:DI 2 "general_operand" "")))]
-;  ""
-;  "
-;{
-;  rtx gen_xorsi3();
-;
-;  emit_insn (gen_xorsi3 (operand_subword (operands[0], 0, 1, DImode),
-;			 operand_subword (operands[1], 0, 1, DImode),
-;			 operand_subword (operands[2], 0, 1, DImode)));
-;  emit_insn (gen_xorsi3 (gen_lowpart (SImode, operands[0]),
-;			 gen_lowpart (SImode, operands[1]),
-;			 gen_lowpart (SImode, operands[2])));
-;  DONE;
-;}")
-
-;
-; xorsi3 instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:SI 0 "r_or_s_operand" "=d,m")
-	(xor:SI (match_operand:SI 1 "r_or_s_operand" "%0,0")
-		(match_operand:SI 2 "r_or_s_operand" "g,mi")))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"XR	%0,%2\";
-    }
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"X	%0,%2\";
-    }
-  CC_STATUS_INIT;
-  mvs_check_page (0, 6, 0);
-  return \"XC	%O0(4,%R0),%2\";
-}")
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(xor:SI (match_operand:SI 1 "general_operand" "%0")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"XR	%0,%2\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"X	%0,%2\";
-}")
-
-;
-; xorhi3 instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_or_s_operand" "=d,m")
-	(xor:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
-		(match_operand:HI 2 "r_or_s_operand" "di,mi")))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"XR	%0,%2\";
-    }
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"X	%0,%2\";
-    }
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 6, 0);
-      return \"XC	%O0(2,%R0),%H2\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"XC	%O0(2,%R0),%2\";
-}")
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(xor:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "di")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"X	%0,%2\";
-    }
-  mvs_check_page (0, 2, 0);
-  return \"XR	%0,%2\";
-}")
-
-;
-; xorqi3 instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:QI 0 "r_or_s_operand" "=d,m")
-	(xor:QI (match_operand:QI 1 "r_or_s_operand" "%0,0")
-		(match_operand:QI 2 "r_or_s_operand" "di,mi")))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 2, 0);
-      return \"XR	%0,%2\";
-    }
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 0);
-      return \"X	%0,%2\";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"XI	%0,%B2\";
-    }
-  mvs_check_page (0, 6, 0);
-  return \"XC	%O0(1,%R0),%2\";
-}")
-
-(define_insn "xorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(xor:QI (match_operand:QI 1 "general_operand" "%0")
-		(match_operand:QI 2 "general_operand" "di")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      mvs_check_page (0, 4, 0);
-      return \"X	%0,%2\";
-    }
-  mvs_check_page (0, 2, 0);
-  return \"XR	%0,%2\";
-}")
-
-;;
-;;- Negate instructions.
-;;
-
-;
-; negsi2 instruction pattern(s).
-;
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(neg:SI (match_operand:SI 1 "general_operand" "d")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 2, 0);
-  return \"LCR	%0,%1\";
-}")
-
-;
-; neghi2 instruction pattern(s).
-;
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(neg:HI (match_operand:HI 1 "general_operand" "d")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 10, 0);
-  return \"SLL	%1,16\;SRA	%1,16\;LCR	%0,%1\";
-}")
-
-;
-; negdf2 instruction pattern(s).
-;
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(neg:DF (match_operand:DF 1 "general_operand" "f")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 2, 0);
-  return \"LCDR	%0,%1\";
-}")
-
-;
-; negsf2 instruction pattern(s).
-;
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(neg:SF (match_operand:SF 1 "general_operand" "f")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 2, 0);
-  return \"LCER	%0,%1\";
-}")
-
-;;
-;;- Absolute value instructions.
-;;
-
-;
-; abssi2 instruction pattern(s).
-;
-
-(define_insn "abssi2"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(abs:SI (match_operand:SI 1 "general_operand" "d")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 2, 0);
-  return \"LPR	%0,%1\";
-}")
-
-;
-; abshi2 instruction pattern(s).
-;
-
-(define_insn "abshi2"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(abs:HI (match_operand:HI 1 "general_operand" "d")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 10, 0);
-  return \"SLL	%1,16\;SRA	%1,16\;LPR	%0,%1\";
-}")
-
-;
-; absdf2 instruction pattern(s).
-;
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(abs:DF (match_operand:DF 1 "general_operand" "f")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 2, 0);
-  return \"LPDR	%0,%1\";
-}")
-
-;
-; abssf2 instruction pattern(s).
-;
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(abs:SF (match_operand:SF 1 "general_operand" "f")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 2, 0);
-  return \"LPER	%0,%1\";
-}")
-
-;;
-;;- One complement instructions.
-;;
-
-;
-; one_cmpldi2 instruction pattern(s).
-;
-
-;(define_expand "one_cmpldi2"
-;  [(set (match_operand:DI 0 "general_operand" "")
-;	(not:DI (match_operand:DI 1 "general_operand" "")))]
-;  ""
-;  "
-;{
-;  rtx gen_one_cmplsi2();
-;
-;  emit_insn (gen_one_cmplsi2 (operand_subword (operands[0], 0, 1, DImode),
-;			      operand_subword (operands[1], 0, 1, DImode)));
-;  emit_insn (gen_one_cmplsi2 (gen_lowpart (SImode, operands[0]),
-;			      gen_lowpart (SImode, operands[1])));
-;  DONE;
-;}")
-
-;
-; one_cmplsi2 instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:SI 0 "r_or_s_operand" "=dm")
-	(not:SI (match_operand:SI 1 "r_or_s_operand" "0")))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 4);
-      return \"X	%0,=F'-1'\";
-    }
-  CC_STATUS_INIT;
-  mvs_check_page (0, 6, 4);
-  return \"XC	%O0(4,%R0),=F'-1'\";
-}")
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(not:SI (match_operand:SI 1 "general_operand" "0")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 4, 4);
-  return \"X	%0,=F'-1'\";
-}")
-
-;
-; one_cmplhi2 instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_or_s_operand" "=dm")
-	(not:HI (match_operand:HI 1 "r_or_s_operand" "0")))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 4);
-      return \"X	%0,=F'-1'\";
-    }
-  CC_STATUS_INIT;
-  mvs_check_page (0, 6, 4);
-  return \"XC	%O0(2,%R0),=X'FFFF'\";
-}")
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(not:HI (match_operand:HI 1 "general_operand" "0")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 4, 4);
-  return \"X	%0,=F'-1'\";
-}")
-
-;
-; one_cmplqi2 instruction pattern(s).
-;
-
-(define_insn ""
-  [(set (match_operand:QI 0 "r_or_s_operand" "=dm")
-	(not:QI (match_operand:QI 1 "r_or_s_operand" "0")))]
-  "TARGET_CHAR_INSTRUCTIONS"
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 4, 4);
-      return \"X	%0,=F'-1'\";
-    }
-  mvs_check_page (0, 4, 0);
-  return \"XI	%0,255\";
-}")
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(not:QI (match_operand:QI 1 "general_operand" "0")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  mvs_check_page (0, 4, 4);
-  return \"X	%0,=F'-1'\";
-}")
-
-;;
-;;- Arithmetic shift instructions.
-;;
-
-;
-; ashldi3 instruction pattern(s).
-;
-
-(define_insn "ashldi3"
-  [(set (match_operand:DI 0 "general_operand" "=d")
-	(ashift:DI (match_operand:DI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "Ja")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  mvs_check_page (0, 4, 0);
-  if (REG_P (operands[2]))
-    return \"SLDA	%0,0(%2)\";
-  return \"SLDA	%0,%c2\";
-}")
-
-;
-; ashrdi3 instruction pattern(s).
-;
-
-(define_insn "ashrdi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "Ja")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 4, 0);
-  if (REG_P (operands[2])) 
-    return \"SRDA	%0,0(%2)\";
-  return \"SRDA	%0,%c2\";
-}")
-
-;
-; ashlsi3 instruction pattern(s).
-;
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(ashift:SI (match_operand:SI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "Ja")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  mvs_check_page (0, 4, 0);
-  if (REG_P (operands[2])) 
-    return \"SLL	%0,0(%2)\";
-  return \"SLL	%0,%c2\";
-}")
-
-;
-; ashrsi3 instruction pattern(s).
-;
-
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "Ja")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 4, 0);
-  if (REG_P (operands[2])) 
-    return \"SRA	%0,0(%2)\";
-  return \"SRA	%0,%c2\";
-}")
-
-;
-; ashlhi3 instruction pattern(s).
-;
-
-(define_insn "ashlhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(ashift:HI (match_operand:HI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "Ja")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 8, 0);
-  if (REG_P (operands[2])) 
-    return \"SLL	%0,16(%2)\;SRA	%0,16\";
-  return \"SLL	%0,16+%c2\;SRA	%0,16\";
-}")
-
-;
-; ashrhi3 instruction pattern(s).
-;
-
-(define_insn "ashrhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "Ja")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 4, 0);
-  if (REG_P (operands[2])) 
-    return \"SLL	%0,16\;SRA	%0,16(%2)\";
-  return \"SLL	%0,16\;SRA	%0,16+%c2\";
-}")
-
-;
-; ashlqi3 instruction pattern(s).
-;
-
-(define_insn "ashlqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(ashift:QI (match_operand:QI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "Ja")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  mvs_check_page (0, 4, 0);
-  if (REG_P (operands[2])) 
-    return \"SLL	%0,0(%2)\";
-  return \"SLL	%0,%c2\";
-}")
-
-;
-; ashrqi3 instruction pattern(s).
-;
-
-(define_insn "ashrqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "Ja")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 8, 0);
-  if (REG_P (operands[2])) 
-    return \"SLL	%0,24\;SRA	%0,24(%2)\";
-  return \"SLL	%0,24\;SRA	%0,24+%c2\";
-}")
-
-;;
-;;- Logical shift instructions.
-;;
-
-;
-; lshrdi3 instruction pattern(s).
-;
-
-(define_insn "lshrdi3"
-  [(set (match_operand:DI 0 "general_operand" "=d")
-	(lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "Ja")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 4, 0);
-  if (REG_P (operands[2])) 
-    return \"SRDL	%0,0(%2)\";
-  return \"SRDL	%0,%c2\";
-}")
-
-
-;
-; lshrsi3 instruction pattern(s).
-;
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "Ja")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 4, 0);
-  if (REG_P (operands[2])) 
-    return \"SRL	%0,0(%2)\";
-  return \"SRL	%0,%c2\";
-}")
-
-;
-; lshrhi3 instruction pattern(s).
-;
-
-(define_insn "lshrhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "Ja")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  if (REG_P (operands[2]))
-    {
-      mvs_check_page (0, 8, 4);
-      return \"N	%0,=X'0000FFFF'\;SRL	%0,0(%2)\";
-    }
-  mvs_check_page (0, 8, 4);
-  return \"N	%0,=X'0000FFFF'\;SRL	%0,%c2\";
-}")
-
-;
-; lshrqi3 instruction pattern(s).
-;
-
-(define_insn "lshrqi3"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
-		     (match_operand:SI 2 "general_operand" "Ja")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  CC_STATUS_INIT;
-  mvs_check_page (0, 8, 4);
-  if (REG_P (operands[2])) 
-    return \"N	%0,=X'000000FF'\;SRL	%0,0(%2)\";
-  return \"N	%0,=X'000000FF'\;SRL	%0,%c2\";
-}")
-
-;;
-;;- Conditional jump instructions.
-;;
-
-;
-; beq instruction pattern(s).
-;
-
-(define_insn "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BER	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BER	14\";
-    }
-  return \"BE	%l0\";
-}")
-
-;
-; bne instruction pattern(s).
-;
-
-(define_insn "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BNER	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BNER	14\";
-    }
-  return \"BNE	%l0\";
-}")
-
-;
-; bgt instruction pattern(s).
-;
-
-(define_insn "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BHR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BHR	14\";
-    }
-  return \"BH	%l0\";
-}")
-
-;
-; bgtu instruction pattern(s).
-;
-
-(define_insn "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BHR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BHR	14\";
-    }
-  return \"BH	%l0\";
-}")
-
-;
-; blt instruction pattern(s).
-;
-
-(define_insn "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BLR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BLR	14\";
-    }
-  return \"BL	%l0\";
-}")
-
-;
-; bltu instruction pattern(s).
-;
-
-(define_insn "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BLR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BLR	14\";
-    }
-  return \"BL	%l0\";
-}")
-
-;
-; bge instruction pattern(s).
-;
-
-(define_insn "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BNLR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BNLR	14\";
-    }
-  return \"BNL	%l0\";
-}")
-
-;
-; bgeu instruction pattern(s).
-;
-
-(define_insn "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BNLR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BNLR	14\";
-    }
-  return \"BNL	%l0\";
-}")
-
-;
-; ble instruction pattern(s).
-;
-
-(define_insn "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BNHR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BNHR	14\";
-    }
-  return \"BNH	%l0\";
-}")
-
-;
-; bleu instruction pattern(s).
-;
-
-(define_insn "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BNHR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BNHR	14\";
-    }
-  return \"BNH	%l0\";
-}")
-
-;;
-;;- Negated conditional jump instructions.
-;;
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BNER	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BNER	14\";
-    }
-  return \"BNE	%l0\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BER	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BER	14\";
-    }
-  return \"BE	%l0\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BNHR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BNHR	14\";
-    }
-  return \"BNH	%l0\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BNHR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BNHR	14\";
-    }
-  return \"BNH	%l0\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BNLR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BNLR	14\";
-    }
-  return \"BNL	%l0\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BNLR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BNLR	14\";
-    }
-  return \"BNL	%l0\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BLR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BLR	14\";
-    }
-  return \"BL	%l0\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BLR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BLR	14\";
-    }
-  return \"BL	%l0\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BHR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BHR	14\";
-    }
-  return \"BH	%l0\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BHR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BHR	14\";
-    }
-  return \"BH	%l0\";
-}")
-
-;;
-;;- Subtract one and jump if not zero.
-;;
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (plus:SI (match_operand:SI 0 "register_operand" "+d")
-		      (const_int -1))
-	     (const_int 0))
-	 (label_ref (match_operand 1 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[1])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l1)\;BCTR	%0,14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l1)\;BCTR	%0,14\";
-    }
-  return \"BCT	%0,%l1\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (plus:SI (match_operand:SI 0 "register_operand" "+d")
-		      (const_int -1))
-	     (const_int 0))
-	 (pc)
-	 (label_ref (match_operand 1 "" ""))))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[1])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l1)\;BCTR	%0,14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l1)\;BCTR	%0,14\";
-    }
-  return \"BCT	%0,%l1\";
-}")
-
-;;
-;;- Unconditional jump instructions.
-;;
-
-;
-; jump instruction pattern(s).
-;
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
-    {
-      mvs_check_page (0, 6, 4);
-      return \"L	14,=A(%l0)\;BR	14\";
-    }
-  if (mvs_check_page (0, 4, 0))
-    {
-      mvs_check_page (0, 2, 4);
-      return \"L	14,=A(%l0)\;BR	14\";
-    }
-  return \"B	%l0\";
-}")
-
-;
-; indirect-jump instruction pattern(s).
-;
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "general_operand" "r"))]
-  "(GET_CODE (operands[0]) != MEM )"
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 2, 0);
-  return \"BR	%0\";
-}")
-
-;
-; tablejump instruction pattern(s).
-;
-
-(define_insn "tablejump"
-  [(set (pc)
-	(match_operand:SI 0 "general_operand" "am"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "*
-{
-  check_label_emit ();
-  if (REG_P (operands[0]))
-    {
-      mvs_check_page (0, 6, 0);
-      return \"BR	%0\;DS	0F\";
-    }
-  mvs_check_page (0, 10, 0);
-  return \"L	14,%0\;BR	14\;DS	0F\";
-}")
-
-;;
-;;- Jump to subroutine.
-;;
-;; For the C/370 environment the internal functions, ie. sqrt, are called with
-;; a non-standard form.  So, we must fix it here.  There's no BM like IBM.
-;;
-
-;
-; call instruction pattern(s).
-;
-
-(define_insn "call"
-  [(call (match_operand:QI 0 "memory_operand" "m")
-	 (match_operand:SI 1 "immediate_operand" "i"))]
-  ""
-  "*
-{
-  static char temp[128];
-  int i = STACK_POINTER_OFFSET;
-
-  check_label_emit ();
-  if (mvs_function_check (XSTR (operands[0], 0)))
-    {
-      mvs_check_page (0, 22, 4);
-      sprintf ( temp, \"LA	1,136(,13)\;ST	1,%d(,13)\;LA	1,%d(,13)\;L	15,%%0\;BALR	14,15\;LD	0,136(,13)\",
-	     i - 4, i - 4 );
-    }
-  else
-    {
-      mvs_check_page (0, 10, 4);
-      sprintf ( temp, \"LA	1,%d(,13)\;L	15,%%0\;BALR	14,15\", i );
-    }
-  return temp;
-}")
-
-;
-; call_value instruction pattern(s).
-;
-
-(define_insn "call_value"
-  [(set (match_operand 0 "" "rf")
- 	(call (match_operand:QI 1 "memory_operand" "m")
- 	      (match_operand:SI 2 "general_operand" "i")))]
-  ""
-  "*
-{
-  static char temp[128];
-  int i = STACK_POINTER_OFFSET;
-
-  check_label_emit ();
-  if (mvs_function_check (XSTR (operands[1], 0)))
-    {
-      mvs_check_page (0, 22, 4);
-      sprintf ( temp, \"LA	1,136(,13)\;ST	1,%d(,13)\;LA	1,%d(,13)\;L	15,%%1\;BALR	14,15\;LD	0,136(,13)\",
-	   i - 4, i - 4 );
-    }
-  else
-    {
-      mvs_check_page (0, 10, 4);
-      sprintf ( temp, \"LA	1,%d(,13)\;L	15,%%1\;BALR	14,15\", i );
-    }
-  return temp;
-}")
-
-(define_insn ""
-  [(call (mem:QI (match_operand:SI 0 "" "i"))
-	 (match_operand:SI 1 "general_operand" "g"))]
-  "GET_CODE (operands[0]) == SYMBOL_REF"
-  "*
-{
-  static char temp[128];
-  int i = STACK_POINTER_OFFSET;
-
-  check_label_emit ();
-  if (mvs_function_check (XSTR (operands[0], 0)))
-    {
-      mvs_check_page (0, 22, 4);
-      sprintf ( temp, \"LA	1,136(,13)\;ST	1,%d(,13)\;LA	1,%d(,13)\;L	15,%%0\;BALR	14,15\;LD	0,136(,13)\",
-	   i - 4, i - 4 );
-    }
-  else
-    {
-      mvs_check_page (0, 10, 4);
-      sprintf ( temp, \"LA	1,%d(,13)\;L	15,%%0\;BALR	14,15\", i );
-    }
-  return temp;
-}")
-
-(define_insn ""
-  [(set (match_operand 0 "" "rf")
-	(call (mem:QI (match_operand:SI 1 "" "i"))
-	      (match_operand:SI 2 "general_operand" "g")))]
-  "GET_CODE (operands[1]) == SYMBOL_REF"
-  "*
-{
-  static char temp[128];
-  int i = STACK_POINTER_OFFSET;
-
-  check_label_emit ();
-  if (mvs_function_check (XSTR (operands[1], 0)))
-    {
-      mvs_check_page (0, 22, 4);
-      sprintf ( temp, \"LA	1,136(,13)\;ST	1,%d(,13)\;LA	1,%d(,13)\;L	15,%%1\;BALR	14,15\;LD	0,136(,13)\",
-	   i - 4, i - 4 );
-    }
-  else
-    {
-      mvs_check_page (0, 10, 4);
-      sprintf ( temp, \"LA	1,%d(,13)\;L	15,%%1\;BALR	14,15\", i );
-    }
-  return temp;
-}")
-
-
-;;
-;;- Miscellaneous instructions.
-;;
-
-;
-; nop instruction pattern(s).
-;
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "*
-{
-  check_label_emit ();
-  mvs_check_page (0, 2, 0);
-  return \"LR	0,0\";
-}")
-
diff --git a/gcc/config/i370/t-i370 b/gcc/config/i370/t-i370
deleted file mode 100755
index d20ab38..0000000
--- a/gcc/config/i370/t-i370
+++ /dev/null
@@ -1,4 +0,0 @@
-# There is no libgcc for mvs
-LIBGCC =
-INSTALL_LIBGCC =
-LIBGCC1_TEST =
diff --git a/gcc/config/i370/xm-i370.h b/gcc/config/i370/xm-i370.h
deleted file mode 100755
index ac75363..0000000
--- a/gcc/config/i370/xm-i370.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Configuration for GNU C-compiler for System/370.
-   Copyright (C) 1989, 1993, 1997 Free Software Foundation, Inc.
-   Contributed by Jan Stein (jan@cd.chalmers.se).
-   Modified for MVS C/370 by Dave Pitts (dpitts@nyx.cs.du.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-
-#define HOST_BITS_PER_CHAR	8
-#define HOST_BITS_PER_SHORT	16
-#define HOST_BITS_PER_INT	32
-#define HOST_BITS_PER_LONG	32
-#define HOST_FLOAT_FORMAT	IBM_FLOAT_FORMAT
-#define HOST_EBCDIC		1
-
-#define USG
-#ifndef MVS
-#define MVS
-#endif
-
-/* Target machine dependencies.  tm.h is a symbolic link to the actual
-   target specific file.  */
-
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-
-#define SUCCESS_EXIT_CODE	0
-#define FATAL_EXIT_CODE		12
-
-#define NO_DBX_FORMAT
-
diff --git a/gcc/config/i386/386bsd.h b/gcc/config/i386/386bsd.h
deleted file mode 100755
index 7962321..0000000
--- a/gcc/config/i386/386bsd.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Configuration for an i386 running 386BSD as the target machine.  */
-
-/* This is tested by i386gas.h.  */
-#define YES_UNDERSCORES
-
-#include "i386/gstabs.h"
-
-/* Get perform_* macros to build libgcc.a.  */
-#include "i386/perform.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Di386 -D____386BSD____ -D__386BSD__ -DBSD_NET2 -Asystem(unix) -Asystem(bsd) -Acpu(i386) -Amachine(i386)"
-
-/* Like the default, except no -lg.  */
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-
-#define WCHAR_UNSIGNED 1
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
-
-/* 386BSD does have atexit.  */
-
-#define HAVE_ATEXIT
-
-/* Redefine this to use %eax instead of %edx.  */
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-{									\
-  if (flag_pic)								\
-    {									\
-      fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%eax\n",		\
-	       LPREFIX, (LABELNO));					\
-      fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n");			\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\tmovl $%sP%d,%%eax\n", LPREFIX, (LABELNO));	\
-      fprintf (FILE, "\tcall mcount\n");				\
-    }									\
-}
-
-#undef ASM_APP_ON
-#define ASM_APP_ON "#APP\n"
-
-#undef ASM_APP_OFF
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* The following macros are stolen from i386v4.h */
-/* These have to be defined to get PIC code correct */
-
-/* This is how to output an element of a case-vector that is relative.
-   This is only used for PIC code.  See comments by the `casesi' insn in
-   i386.md for an explanation of the expression this outputs. */
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE)
-
-/* Indicate that jump tables go in the text section.  This is
-   necessary when compiling PIC code.  */
-
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
diff --git a/gcc/config/i386/aix386.h b/gcc/config/i386/aix386.h
deleted file mode 100755
index e0498e7..0000000
--- a/gcc/config/i386/aix386.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Definitions for IBM PS2 running AIX/386 with gas.
-   From: Minh Tran-Le <TRANLE@intellicorp.com>
-   Copyright (C) 1988 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* 
- * This configuration file is for gcc with gas-2.x and gnu ld 2.x
- * with aix ps/2 1.3.x.
- */
-
-/* Define USE_GAS if you have the new version of gas that can handle
- * multiple segments and .section pseudo op.  This will allow gcc to
- * use the .init section for g++ ctor/dtor.
- *
- * If you don't have gas then undefined USE_GAS.  You will also have
- * to use collect if you want to use g++
- */
-#define USE_GAS
-
-#include "i386/aix386ng.h"
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.
-   And add crtbegin.o and crtend.o for ctors and dtors */
-
-#undef  STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} crtbegin.o%s"
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC \
-  "crtend.o%s crtn.o%s"
-
-/* Removed the -K flags because the gnu ld does not handle it */
-#undef LINK_SPEC
-#define LINK_SPEC "%{T*} %{z:-lm}"
-
-/* Define a few machine-specific details of the implementation of
-   constructors.  */
-
-#undef INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP     ".section .init,\"x\""
-
-#define CTOR_LIST_BEGIN				\
-  asm (INIT_SECTION_ASM_OP);			\
-  asm ("pushl $0")
-#define CTOR_LIST_END CTOR_LIST_BEGIN
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)	\
-  do {						\
-    init_section ();				\
-    fprintf (FILE, "\tpushl $");		\
-    assemble_name (FILE, NAME);			\
-    fprintf (FILE, "\n");			\
-  } while (0)
diff --git a/gcc/config/i386/aix386ng.h b/gcc/config/i386/aix386ng.h
deleted file mode 100755
index 3b3d65a..0000000
--- a/gcc/config/i386/aix386ng.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Definitions for IBM PS2 running AIX/386.
-   Copyright (C) 1988, 1996 Free Software Foundation, Inc.
-   Contributed by Minh Tran-Le <TRANLE@intellicorp.com>.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "i386/i386.h"
-
-/* Get the generic definitions for system V.3.  */
-
-#include "svr3.h"
-
-/* Use the ATT assembler syntax.
-   This overrides at least one macro (USER_LABEL_PREFIX) from svr3.h.  */
-
-#include "i386/att.h"
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
-#define ENDFILE_SPEC   "crtn.o%s"
-
-#define LIB_SPEC "%{shlib:-lc_s} -lc"
-
-/* Special flags for the linker.  I don't know what they do.  */
-
-#define LINK_SPEC "%{K} %{!K:-K} %{T*} %{z:-lm}"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#define CPP_PREDEFINES "-Dps2 -Dunix -Asystem(aix)"
-
-#define CPP_SPEC "%(cpp_cpu) \
-  %{posix:-D_POSIX_SOURCE}%{!posix:-DAIX} -D_I386 -D_AIX -D_MBCS"
-
-/* special flags for the aix assembler to generate the short form for all
-   qualifying forward reference */
-/* The buggy /bin/as of aix ps/2 1.2.x cannot always handle it.	*/
-#if 0
-#define ASM_SPEC "-s2"
-#endif /* 0 */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) 					\
-  do { output_file_directive (FILE, main_input_filename);	\
-       if (optimize)						\
-          ASM_FILE_START_1 (FILE); 				\
-       else							\
-          fprintf (FILE, "\t.noopt\n");				\
-     } while (0)
-
-/* This was suggested, but it shouldn't be right for DBX output. -- RMS
-   #define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) */
-
-/* Writing `int' for a bitfield forces int alignment for the structure.  */
-
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-#ifndef USE_GAS
-/* Don't write a `.optim' pseudo; this assembler
-   is said to have a bug when .optim is used.  */
-
-#undef ASM_FILE_START_1
-#define ASM_FILE_START_1(FILE) fprintf (FILE, "\t.noopt\n")
-#endif
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   fprintf (FILE, "\tleal %sP%d,%%eax\n\tcall mcount\n", LPREFIX, (LABELNO));
-
-/* Note that using bss_section here caused errors
-   in building shared libraries on system V.3.
-   but AIX 1.2 does not have yet shareable libraries on PS2 */
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-  (bss_section (),					\
-   ASM_OUTPUT_LABEL ((FILE), (NAME)),			\
-   fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED)))
-
-
-/* Undef all the .init and .fini section stuff if we are not using gas and
- * gnu ld so that we can use collect because the standard /bin/as and /bin/ld
- * cannot handle those.
- */
-#ifndef USE_GAS
-# undef INIT_SECTION_ASM_OP
-# undef FINI_SECTION_ASM_OP
-# undef CTORS_SECTION_ASM_OP
-# undef DTORS_SECTION_ASM_OP
-# undef ASM_OUTPUT_CONSTRUCTOR
-# undef ASM_OUTPUT_DESTRUCTOR
-# undef DO_GLOBAL_CTORS_BODY
-
-# undef CTOR_LIST_BEGIN
-# define CTOR_LIST_BEGIN
-# undef CTOR_LIST_END
-# define CTOR_LIST_END
-# undef DTOR_LIST_BEGIN
-# define DTOR_LIST_BEGIN
-# undef DTOR_LIST_END
-# define DTOR_LIST_END
-
-# undef CONST_SECTION_FUNCTION
-# define CONST_SECTION_FUNCTION						\
-void									\
-const_section ()							\
-{									\
-  extern void text_section();						\
-  text_section();							\
-}
-
-# undef EXTRA_SECTION_FUNCTIONS
-# define EXTRA_SECTION_FUNCTIONS				\
-  CONST_SECTION_FUNCTION
-
-/* for collect2 */
-# define OBJECT_FORMAT_COFF
-# define MY_ISCOFF(magic) \
-  ((magic) == I386MAGIC || (magic) == I386SVMAGIC)
-
-#endif /* !USE_GAS */
diff --git a/gcc/config/i386/att.h b/gcc/config/i386/att.h
deleted file mode 100755
index e5c2d9c..0000000
--- a/gcc/config/i386/att.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Definitions for AT&T assembler syntax for the Intel 80386.
-   Copyright (C) 1988, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Include common aspects of all 386 Unix assemblers.  */
-#include "i386/unix.h"
-
-#define TARGET_VERSION fprintf (stderr, " (80386, ATT syntax)");
-
-/* Define the syntax of instructions and addresses.  */
-
-/* Prefix for internally generated assembler labels.  */
-#define LPREFIX ".L"
-
-/* Assembler pseudos to introduce constants of various size.  */
-
-/* #define ASM_BYTE_OP "\t.byte"  Now in svr3.h or svr4.h.  */
-#define ASM_SHORT "\t.value"
-#define ASM_LONG "\t.long"
-#define ASM_DOUBLE "\t.double"
-
-/* How to output an ASCII string constant.  */
-
-#define ASM_OUTPUT_ASCII(FILE, p, size) \
-do								\
-{ int i = 0; 							\
-  while (i < (size))						\
-    { if (i%10 == 0) { if (i!=0) fprintf ((FILE), "\n");	\
-		       fprintf ((FILE), "%s ", ASM_BYTE_OP); }	\
-      else fprintf ((FILE), ",");				\
-	fprintf ((FILE), "0x%x", ((p)[i++] & 0377)) ;}		\
-      fprintf ((FILE), "\n");					\
-} while (0)
-
-/* Do use .optim by default on this machine.  */
-#undef ASM_FILE_START_1
-#define ASM_FILE_START_1(FILE) fprintf (FILE, "\t.optim\n")
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-    if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG))
-
-/* This is how to output an assembler line
-   that says to advance the location counter by SIZE bytes.  */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf ((FILE), "\t.set .,.+%u\n", (SIZE))
-
-/* Can't use ASM_OUTPUT_SKIP in text section; it doesn't leave 0s.  */
-
-#define ASM_NO_SKIP_IN_TEXT 1
-
-/* Define the syntax of labels and symbol definitions/declarations.  */
-
-/* This is how to store into the string BUF
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER)	\
-  sprintf ((BUF), ".%s%d", (PREFIX), (NUMBER))
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
diff --git a/gcc/config/i386/bsd.h b/gcc/config/i386/bsd.h
deleted file mode 100755
index 34db79a..0000000
--- a/gcc/config/i386/bsd.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Definitions for BSD assembler syntax for Intel 386
-   (actually AT&T syntax for insns and operands,
-   adapted to BSD conventions for symbol names and debugging.)
-   Copyright (C) 1988, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Include common aspects of all 386 Unix assemblers.  */
-#include "i386/unix.h"
-
-/* Use the Sequent Symmetry assembler syntax.  */
-
-#define TARGET_VERSION fprintf (stderr, " (80386, BSD syntax)");
-
-/* Define the syntax of pseudo-ops, labels and comments.  */
-
-/* Prefix for internally generated assembler labels.  If we aren't using
-   underscores, we are using prefix `.'s to identify labels that should
-   be ignored, as in `i386/gas.h' --karl@cs.umb.edu  */
-#ifdef NO_UNDERSCORES
-#define LPREFIX ".L"
-#else
-#define LPREFIX "L"
-#endif /* not NO_UNDERSCORES */
-
-/* Assembler pseudos to introduce constants of various size.  */
-
-#define ASM_BYTE_OP "\t.byte"
-#define ASM_SHORT "\t.word"
-#define ASM_LONG "\t.long"
-#define ASM_DOUBLE "\t.double"
-
-/* Output at beginning of assembler file.
-   ??? I am skeptical of this -- RMS.  */
-
-#define ASM_FILE_START(FILE) \
-  do {	output_file_directive (FILE, main_input_filename);	\
-  } while (0)
-
-/* This was suggested, but it shouldn't be right for DBX output. -- RMS
-   #define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) */
-
-
-/* Define the syntax of labels and symbol definitions/declarations.  */
-
-/* This is how to output an assembler line
-   that says to advance the location counter by SIZE bytes.  */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %u\n", (SIZE))
-
-/* Define the syntax of labels and symbol definitions/declarations.  */
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", (LOG))
-
-/* This is how to store into the string BUF
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#ifdef NO_UNDERSCORES
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER)	\
-    sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER))
-#else
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER)	\
-    sprintf ((BUF), "*%s%d", (PREFIX), (NUMBER))
-#endif
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#ifdef NO_UNDERSCORES
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-#else
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-#endif
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#ifdef NO_UNDERSCORES
-#define USER_LABEL_PREFIX ""
-#else
-#define USER_LABEL_PREFIX "_"
-#endif /* not NO_UNDERSCORES */
-
-/* Sequent has some changes in the format of DBX symbols.  */
-#define DBX_NO_XREFS 1
-
-/* Don't split DBX symbols into continuations.  */
-#define DBX_CONTIN_LENGTH 0
diff --git a/gcc/config/i386/bsd386.h b/gcc/config/i386/bsd386.h
deleted file mode 100755
index c0dcf87..0000000
--- a/gcc/config/i386/bsd386.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Configuration for an i386 running BSDI's BSD/OS (formerly known as BSD/386)
-   as the target machine.  */
-
-#include "i386/386bsd.h"
-
-/* We exist mostly to add -Dbsdi and such to the predefines. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Di386 -Dbsdi -D__i386__ -D__bsdi__ -D____386BSD____ -D__386BSD__ -DBSD_NET2 -Asystem(unix) -Asystem(bsd) -Acpu(i386) -Amachine(i386)"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "int"
-
-#undef WCHAR_UNSIGNED
-#define WCHAR_UNSIGNED 0
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 32
-
-/* This is suitable for BSD/OS 3.0; we don't know about earlier releases.  */
-#undef ASM_COMMENT_START
-#define ASM_COMMENT_START " #"
-
-/* Until they use ELF or something that handles dwarf2 unwinds
-   and initialization stuff better.  */
-#define DWARF2_UNWIND_INFO 0
-
-/* BSD/OS still uses old binutils that don't insert nops by default
-   when the .align directive demands to insert extra space in the text
-   segment.  */
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
-  if ((LOG)!=0) fprintf ((FILE), "\t.align %d,0x90\n", (LOG))
diff --git a/gcc/config/i386/config-nt.sed b/gcc/config/i386/config-nt.sed
deleted file mode 100755
index 6c86b27..0000000
--- a/gcc/config/i386/config-nt.sed
+++ /dev/null
@@ -1,38 +0,0 @@
-/^Makefile/,/^	rm -f config.run/d
-s/rm -f/del/
-s/|| cp/|| copy/
-/^config.status/,/	fi/d
-s/config.status//g
-s/\/dev\/null/NUL/g
-s/$(srcdir)\/c-parse/c-parse/g
-s/$(srcdir)\/c-gperf/c-gperf/g
-/^multilib.h/ s/multilib/not-multilib/
-/^target=/ c\
-target=winnt3.5
-/^xmake_file=/ d
-/^tmake_file=/ d
-/^out_file/ c\
-out_file=config/i386/i386.c
-/^out_object_file/ c\
-out_object_file=i386.obj
-/^md_file/ c\
-md_file=config/i386/i386.md
-/^tm_file/ c\
-tm_file=config/i386/win-nt.h
-/^build_xm_file/ c\
-build_xm_file=config/i386/xm-winnt.h
-/^host_xm_file/ c\
-host_xm_file=config/i386/xm-winnt.h
-/^####target/ i\
-CC = cl \
-CLIB = libc.lib kernel32.lib \
-CFLAGS = -Di386 -DWIN32 -D_WIN32 -D_M_IX86=300 -D_X86_=1 \\\
- -DALMOST_STDC -D_MSC_VER=800 \
-LDFLAGS = -align:0x1000 -subsystem:console -entry:mainCRTStartup \\\
- -stack:1000000,1000 \
-\
-EXTRA_OBJS=winnt.obj \
-winnt.obj: $(srcdir)/config/i386/winnt.c \
-\	$(CC) $(CFLAGS) \\\
-\ 	-I. -I$(srcdir) -I$(srcdir)/config -c $(srcdir)/config/i386/winnt.c \
-
diff --git a/gcc/config/i386/crtdll.h b/gcc/config/i386/crtdll.h
deleted file mode 100755
index f7eaf2b..0000000
--- a/gcc/config/i386/crtdll.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Operating system specific defines to be used when targeting GCC for
-   hosting on Windows32, using GNU tools and the Windows32 API Library,
-   as distinct from winnt.h, which is used to build GCC for use with a
-   windows style library and tool set and uses the Microsoft tools.
-   This variant uses CRTDLL.DLL insted of MSVCRTDLL.DLL.
-   Copyright (C) 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di386 -D_WIN32 -DWIN32 -D__WIN32__ \
-  -D__MINGW32__ -DWINNT  -D_X86_=1 -D__STDC__=1\
-  -D__stdcall=__attribute__((__stdcall__)) \
-  -D_stdcall=__attribute__((__stdcall__)) \
-  -D__cdecl=__attribute__((__cdecl__)) \
-  -D__declspec(x)=__attribute__((x)) \
-  -Asystem(winnt) -Acpu(i386) -Amachine(i386)"
-
-#undef LIBGCC_SPEC
-#define LIBGCC_SPEC "-lmingw32 -lgcc -lmoldname -lcrtdll"
-
-/* Specify a different entry point when linking a DLL */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{mdll:dllcrt1%O%s} %{!mdll:crt1%O%s}"
-
-#undef MATH_LIBRARY
-#define MATH_LIBRARY "-lcrtdll"
diff --git a/gcc/config/i386/cygwin.asm b/gcc/config/i386/cygwin.asm
deleted file mode 100755
index 4ac4c91..0000000
--- a/gcc/config/i386/cygwin.asm
+++ /dev/null
@@ -1,32 +0,0 @@
-/* stuff needed for libgcc1 on win32. */
-
-#ifdef L_chkstk
-
-	.global ___chkstk
-	.global	__alloca
-___chkstk:
-__alloca:
-	pushl  %ecx		/* save temp */
-	movl   %esp,%ecx	/* get sp */
-	addl   $0x8,%ecx	/* and point to return addr */
-
-probe: 	cmpl   $0x1000,%eax	/* > 4k ?*/
-	jb    done		
-
-	subl   $0x1000,%ecx  		/* yes, move pointer down 4k*/
-	orl    $0x0,(%ecx)   		/* probe there */
-	subl   $0x1000,%eax  	 	/* decrement count */
-	jmp    probe           	 	/* and do it again */
-
-done: 	subl   %eax,%ecx	   
-	orl    $0x0,(%ecx)	/* less that 4k, just peek here */
-
-	movl   %esp,%eax
-	movl   %ecx,%esp	/* decrement stack */
-
-	movl   (%eax),%ecx	/* recover saved temp */
-	movl   4(%eax),%eax	/* get return address */
-	jmp    *%eax	
-
-
-#endif
diff --git a/gcc/config/i386/cygwin.h b/gcc/config/i386/cygwin.h
deleted file mode 100755
index af0b25e..0000000
--- a/gcc/config/i386/cygwin.h
+++ /dev/null
@@ -1,504 +0,0 @@
-/* Operating system specific defines to be used when targeting GCC for
-   hosting on Windows NT 3.x, using a Unix style C library and tools,
-   as distinct from winnt.h, which is used to build GCC for use with a
-   windows style library and tool set and uses the Microsoft tools.
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define YES_UNDERSCORES
-
-#define DBX_DEBUGGING_INFO 
-#define SDB_DEBUGGING_INFO 
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#include "i386/gas.h"
-#include "dbxcoff.h"
-
-/* Augment TARGET_SWITCHES with the cygwin/no-cygwin options. */
-#define MASK_WIN32 0x40000000 /* Use -lming32 interface */
-#define MASK_CYGWIN  0x20000000 /* Use -lcygwin interface */
-#define MASK_WINDOWS 0x10000000 /* Use windows interface */
-#define MASK_DLL     0x08000000 /* Use dll interface    */
-#define MASK_NOP_FUN_DLLIMPORT 0x20000 /* Ignore dllimport for functions */
-
-#define TARGET_WIN32             (target_flags & MASK_WIN32)
-#define TARGET_CYGWIN            (target_flags & MASK_CYGWIN)
-#define TARGET_WINDOWS           (target_flags & MASK_WINDOWS)
-#define TARGET_DLL               (target_flags & MASK_DLL)
-#define TARGET_NOP_FUN_DLLIMPORT (target_flags & MASK_NOP_FUN_DLLIMPORT)
-
-#undef  SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{ "no-cygwin",                       MASK_WIN32 }, \
-{ "cygwin",                          MASK_CYGWIN },  \
-{ "windows",                         MASK_WINDOWS }, \
-{ "dll",                             MASK_DLL },     \
-{ "nop-fun-dllimport",               MASK_NOP_FUN_DLLIMPORT }, \
-{ "no-nop-fun-dllimport",            MASK_NOP_FUN_DLLIMPORT },
-
-
-/* Support the __declspec keyword by turning them into attributes.
-   We currently only support: dllimport and dllexport.
-   Note that the current way we do this may result in a collision with
-   predefined attributes later on.  This can be solved by using one attribute,
-   say __declspec__, and passing args to it.  The problem with that approach
-   is that args are not accumulated: each new appearance would clobber any
-   existing args.  */
-
-#ifdef CPP_PREDEFINES
-#undef CPP_PREDEFINES
-#endif
-
-#define CPP_PREDEFINES "-Di386 -D_WIN32 \
-  -DWINNT  -D_X86_=1 -D__STDC__=1\
-  -D__stdcall=__attribute__((__stdcall__)) \
-  -D__cdecl=__attribute__((__cdecl__)) \
-  -D__declspec(x)=__attribute__((x)) \
-  -Asystem(winnt) -Acpu(i386) -Amachine(i386)"
-
-/* Normally, -lgcc is not needed since everything in it is in the DLL, but we
-   want to allow things to be added to it when installing new versions of
-   GCC without making a new CYGWIN.DLL, so we leave it.  Profiling is handled
-   by calling the init function from the prologue. */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{mdll: %{!mno-cygwin:dllcrt0%O%s} \
-                                %{mno-cygwin:dllcrt1%O%s}} \
-                        %{!mdll: %{!mno-cygwin:crt0%O%s} \
-                                 %{mno-cygwin:crt1%O%s} %{pg:gcrt0%O%s}}"
-
-#undef CPP_SPEC
-#define CPP_SPEC "-remap %(cpp_cpu) %{posix:-D_POSIX_SOURCE} \
-  %{!mno-cygwin:-D__CYGWIN32__ -D__CYGWIN__} \
-  %{mno-cygwin:-iwithprefixbefore include/mingw32 -D__MINGW32__=0.2}"
-
-/* We have to dynamic link to get to the system DLLs.  All of libc, libm and
-   the Unix stuff is in cygwin.dll.  The import library is called
-   'libcygwin.a'.  For Windows applications, include more libraries, but
-   always include kernel32.  We'd like to specific subsystem windows to
-   ld, but that doesn't work just yet.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{pg:-lgmon} \
-                  %{!mno-cygwin:-lcygwin} \
-                  %{mno-cygwin:-lmingw32 -lmoldname -lcrtdll} \
-                  %{mwindows:-luser32 -lgdi32 -lcomdlg32} \
-		  -lkernel32 -ladvapi32 -lshell32"
-
-#define LINK_SPEC "%{mwindows:--subsystem windows} \
-                   %{mdll:--dll -e _DllMainCRTStartup@12}"
-
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-#define WCHAR_UNSIGNED 1
-#define WCHAR_TYPE_SIZE 16
-#define WCHAR_TYPE "short unsigned int"
-
-#define HAVE_ATEXIT 1
-
-
-/* Enable parsing of #pragma pack(push,<n>) and #pragma pack(pop).  */
-#define HANDLE_PRAGMA_PACK_PUSH_POP 1
-
-/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
-   is a valid machine specific attribute for DECL.
-   The attributes in ATTRIBUTES have previously been assigned to DECL.  */
-extern int i386_pe_valid_decl_attribute_p ();
-
-#undef VALID_MACHINE_DECL_ATTRIBUTE
-#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
-  i386_pe_valid_decl_attribute_p (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
-
-/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
-   is a valid machine specific attribute for TYPE.
-   The attributes in ATTRIBUTES have previously been assigned to TYPE.  */
-
-#undef VALID_MACHINE_TYPE_ATTRIBUTE
-#define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, IDENTIFIER, ARGS) \
-  i386_pe_valid_type_attribute_p (TYPE, ATTRIBUTES, IDENTIFIER, ARGS)
-extern int i386_pe_valid_type_attribute_p ();
-
-extern union tree_node *i386_pe_merge_decl_attributes ();
-#define MERGE_MACHINE_DECL_ATTRIBUTES(OLD, NEW) \
-  i386_pe_merge_decl_attributes ((OLD), (NEW))
-
-/* Used to implement dllexport overriding dllimport semantics.  It's also used
-   to handle vtables - the first pass won't do anything because
-   DECL_CONTEXT (DECL) will be 0 so i386_pe_dll{ex,im}port_p will return 0.
-   It's also used to handle dllimport override semantics.  */
-#if 0
-#define REDO_SECTION_INFO_P(DECL) \
-  ((DECL_MACHINE_ATTRIBUTES (DECL) != NULL_TREE) \
-   || (TREE_CODE (DECL) == VAR_DECL && DECL_VIRTUAL_P (DECL)))
-#else
-#define REDO_SECTION_INFO_P(DECL) 1
-#endif
-
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_ctor, in_dtor, in_drectve
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS					\
-  CTOR_SECTION_FUNCTION						\
-  DTOR_SECTION_FUNCTION						\
-  DRECTVE_SECTION_FUNCTION					\
-  SWITCH_TO_SECTION_FUNCTION
-
-#define CTOR_SECTION_FUNCTION					\
-void								\
-ctor_section ()							\
-{								\
-  if (in_section != in_ctor)					\
-    {								\
-      fprintf (asm_out_file, "\t.section .ctor\n");		\
-      in_section = in_ctor;					\
-    }								\
-}
-
-#define DTOR_SECTION_FUNCTION					\
-void								\
-dtor_section ()							\
-{								\
-  if (in_section != in_dtor)					\
-    {								\
-      fprintf (asm_out_file, "\t.section .dtor\n");		\
-      in_section = in_dtor;					\
-    }								\
-}
-
-#define DRECTVE_SECTION_FUNCTION \
-void									\
-drectve_section ()							\
-{									\
-  if (in_section != in_drectve)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", "\t.section .drectve\n");		\
-      in_section = in_drectve;						\
-    }									\
-}
-
-/* Switch to SECTION (an `enum in_section').
-
-   ??? This facility should be provided by GCC proper.
-   The problem is that we want to temporarily switch sections in
-   ASM_DECLARE_OBJECT_NAME and then switch back to the original section
-   afterwards.  */
-#define SWITCH_TO_SECTION_FUNCTION 				\
-void 								\
-switch_to_section (section, decl) 				\
-     enum in_section section; 					\
-     tree decl; 						\
-{ 								\
-  switch (section) 						\
-    { 								\
-      case in_text: text_section (); break; 			\
-      case in_data: data_section (); break; 			\
-      case in_named: named_section (decl, NULL, 0); break; 	\
-      case in_ctor: ctor_section (); break; 			\
-      case in_dtor: dtor_section (); break; 			\
-      case in_drectve: drectve_section (); break; 		\
-      default: abort (); break; 				\
-    } 								\
-}
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)	\
-  do {						\
-    ctor_section ();				\
-    fprintf (FILE, "%s\t", ASM_LONG);		\
-    assemble_name (FILE, NAME);			\
-    fprintf (FILE, "\n");			\
-  } while (0)
-
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       	\
-  do {						\
-    dtor_section ();                   		\
-    fprintf (FILE, "%s\t", ASM_LONG);		\
-    assemble_name (FILE, NAME);			\
-    fprintf (FILE, "\n");			\
-  } while (0)
-
-/* Define this macro if references to a symbol must be treated
-   differently depending on something about the variable or
-   function named by the symbol (such as what section it is in).
-
-   On i386 running Windows NT, modify the assembler name with a suffix 
-   consisting of an atsign (@) followed by string of digits that represents
-   the number of bytes of arguments passed to the function, if it has the 
-   attribute STDCALL.
-
-   In addition, we must mark dll symbols specially. Definitions of 
-   dllexport'd objects install some info in the .drectve section.  
-   References to dllimport'd objects are fetched indirectly via
-   _imp__.  If both are declared, dllexport overrides.  This is also 
-   needed to implement one-only vtables: they go into their own
-   section and we need to set DECL_SECTION_NAME so we do that here.
-   Note that we can be called twice on the same decl.  */
-
-extern void i386_pe_encode_section_info ();
-
-#ifdef ENCODE_SECTION_INFO
-#undef ENCODE_SECTION_INFO
-#endif
-#define ENCODE_SECTION_INFO(DECL) i386_pe_encode_section_info (DECL)
-
-/* Utility used only in this file.  */
-#define I386_PE_STRIP_ENCODING(SYM_NAME) \
-  ((SYM_NAME) + ((SYM_NAME)[0] == '@' ? 3 : 0))
-
-/* This macro gets just the user-specified name
-   out of the string in a SYMBOL_REF.  Discard
-   trailing @[NUM] encoded by ENCODE_SECTION_INFO.  */
-#undef  STRIP_NAME_ENCODING
-#define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME)				\
-do {									\
-  char *_p;								\
-  char *_name = I386_PE_STRIP_ENCODING (SYMBOL_NAME);			\
-  for (_p = _name; *_p && *_p != '@'; ++_p)				\
-    ;									\
-  if (*_p == '@')							\
-    {									\
-      int _len = _p - _name;						\
-      (VAR) = (char *) alloca (_len + 1);				\
-      strncpy ((VAR), _name, _len);					\
-      (VAR)[_len] = '\0';						\
-    }									\
-  else									\
-    (VAR) = _name;							\
-} while (0)
-      
-
-/* Output a reference to a label.  */
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(STREAM, NAME)  		\
-  fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, 		\
-           I386_PE_STRIP_ENCODING (NAME))		\
-
-/* Output a common block.  */
-#undef ASM_OUTPUT_COMMON
-#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED)	\
-do {							\
-  if (i386_pe_dllexport_name_p (NAME))			\
-    {							\
-      drectve_section ();				\
-      fprintf ((STREAM), "\t.ascii \" -export:%s\"\n",	\
-               I386_PE_STRIP_ENCODING (NAME));		\
-    }							\
-  if (! i386_pe_dllimport_name_p (NAME))		\
-    {							\
-      fprintf ((STREAM), "\t.comm\t"); 			\
-      assemble_name ((STREAM), (NAME));			\
-      fprintf ((STREAM), ", %d\t%s %d\n",		\
-	       (ROUNDED), ASM_COMMENT_START, (SIZE));	\
-    }							\
-} while (0)
-
-/* Output the label for an initialized variable.  */
-#undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) 	\
-do {							\
-  if (i386_pe_dllexport_name_p (NAME))			\
-    {							\
-      enum in_section save_section = in_section;	\
-      drectve_section ();				\
-      fprintf ((STREAM), "\t.ascii \" -export:%s\"\n",	\
-               I386_PE_STRIP_ENCODING (NAME));		\
-      switch_to_section (save_section, (DECL));		\
-    }							\
-  ASM_OUTPUT_LABEL ((STREAM), (NAME));			\
-} while (0)
-
-
-/* Emit code to check the stack when allocating more that 4000
-   bytes in one go. */
-
-#define CHECK_STACK_LIMIT 4000
-
-/* By default, target has a 80387, uses IEEE compatible arithmetic,
-   and returns float values in the 387 and needs stack probes */
-#undef TARGET_DEFAULT
-
-#define TARGET_DEFAULT \
-   (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS | MASK_STACK_PROBE) 
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-    if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG))
-
-/* Define this macro if in some cases global symbols from one translation
-   unit may not be bound to undefined symbols in another translation unit
-   without user intervention.  For instance, under Microsoft Windows
-   symbols must be explicitly imported from shared libraries (DLLs).  */
-#define MULTIPLE_SYMBOL_SPACES
-
-#define UNIQUE_SECTION_P(DECL) DECL_ONE_ONLY (DECL)
-extern void i386_pe_unique_section ();
-#define UNIQUE_SECTION(DECL,RELOC) i386_pe_unique_section (DECL, RELOC)
-
-#define SUPPORTS_ONE_ONLY 1
-
-/* A C statement to output something to the assembler file to switch to section
-   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
-   NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
-   define this macro in such cases.  */
-#undef ASM_OUTPUT_SECTION_NAME
-#define ASM_OUTPUT_SECTION_NAME(STREAM, DECL, NAME, RELOC)		\
-do {									\
-  static struct section_info						\
-    {									\
-      struct section_info *next;					\
-      char *name;							\
-      enum sect_enum {SECT_RW, SECT_RO, SECT_EXEC} type;		\
-    } *sections;							\
-  struct section_info *s;						\
-  char *mode;								\
-  enum sect_enum type;							\
-									\
-  for (s = sections; s; s = s->next)					\
-    if (!strcmp (NAME, s->name))					\
-      break;								\
-									\
-  if (DECL && TREE_CODE (DECL) == FUNCTION_DECL)			\
-    type = SECT_EXEC, mode = "x";					\
-  else if (DECL && DECL_READONLY_SECTION (DECL, RELOC))			\
-    type = SECT_RO, mode = "";						\
-  else									\
-    type = SECT_RW, mode = "w";						\
-									\
-  if (s == 0)								\
-    {									\
-      s = (struct section_info *) xmalloc (sizeof (struct section_info)); \
-      s->name = xmalloc ((strlen (NAME) + 1) * sizeof (*NAME));		\
-      strcpy (s->name, NAME);						\
-      s->type = type;							\
-      s->next = sections;						\
-      sections = s;							\
-      fprintf (STREAM, ".section\t%s,\"%s\"\n", NAME, mode);		\
-      /* Functions may have been compiled at various levels of		\
-         optimization so we can't use `same_size' here.  Instead,	\
-         have the linker pick one.  */					\
-      if ((DECL) && DECL_ONE_ONLY (DECL))				\
-        fprintf (STREAM, "\t.linkonce %s\n",				\
-	         TREE_CODE (DECL) == FUNCTION_DECL			\
-	         ? "discard" : "same_size");				\
-    }									\
-  else									\
-    {									\
-      fprintf (STREAM, ".section\t%s,\"%s\"\n", NAME, mode);		\
-    }									\
-} while (0)
-
-/* Write the extra assembler code needed to declare a function
-   properly.  If we are generating SDB debugging information, this
-   will happen automatically, so we only need to handle other cases.  */
-#undef ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-  do									\
-    {									\
-      if (i386_pe_dllexport_name_p (NAME))				\
-	{								\
-	  drectve_section ();						\
-	  fprintf ((FILE), "\t.ascii \" -export:%s\"\n", 		\
-		   I386_PE_STRIP_ENCODING (NAME));			\
-	  function_section (DECL);					\
-	}								\
-      if (write_symbols != SDB_DEBUG)					\
-	i386_pe_declare_function_type (FILE, NAME, TREE_PUBLIC (DECL));	\
-      ASM_OUTPUT_LABEL (FILE, NAME);					\
-    }									\
-  while (0)
-
-/* Add an external function to the list of functions to be declared at
-   the end of the file.  */
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)				\
-  do									\
-    {									\
-      if (TREE_CODE (DECL) == FUNCTION_DECL)				\
-	i386_pe_record_external_function (NAME);			\
-    }									\
-  while (0)
-
-/* Declare the type properly for any external libcall.  */
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
-  i386_pe_declare_function_type (FILE, XSTR (FUN, 0), 1)
-
-/* Output function declarations at the end of the file.  */
-#define ASM_FILE_END(FILE) \
-  i386_pe_asm_file_end (FILE)
-
-#undef ASM_COMMENT_START
-#define ASM_COMMENT_START " #"
-
-/* DWARF2 Unwinding doesn't work with exception handling yet. */
-#define DWARF2_UNWIND_INFO 0
-
-/* Don't assume anything about the header files. */
-#define NO_IMPLICIT_EXTERN_C
-
-#define SUBTARGET_PROLOGUE						\
-  if (profile_flag 							\
-      && strcmp (IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),\
-		 "main") == 0)						\
-     {									\
-      rtx xops[1];							\
-      xops[0] = gen_rtx_MEM (FUNCTION_MODE,				\
-			 gen_rtx (SYMBOL_REF, Pmode, "_monstartup"));	\
-      if (do_rtl)							\
-	emit_call_insn (gen_rtx (CALL, VOIDmode, xops[0], const0_rtx));	\
-      else								\
-	output_asm_insn (AS1 (call,%P1), xops);			\
-     }
-
-/* External function declarations.  */
-
-#ifndef PROTO
-#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__)
-#define PROTO(ARGS) ARGS
-#else
-#define PROTO(ARGS) ()
-#endif
-#endif
-
-#ifdef BUFSIZ		/* stdio.h has been included, ok to use FILE * */
-#define STDIO_PROTO(ARGS) PROTO(ARGS)
-#else
-#define STDIO_PROTO(ARGS) ()
-#endif
-
-extern void i386_pe_record_external_function PROTO((char *));
-extern void i386_pe_declare_function_type STDIO_PROTO((FILE *, char *, int));
-extern void i386_pe_asm_file_end STDIO_PROTO((FILE *));
-
-/* For Win32 ABI compatibility */
-#undef DEFAULT_PCC_STRUCT_RETURN
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* No data type wants to be aligned rounder than this.  */
-#undef	BIGGEST_ALIGNMENT
-#define BIGGEST_ALIGNMENT 128
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#undef PCC_BITFIELDS_TYPE_MATTERS
-#define PCC_BITFIELDS_TYPE_MATTERS 0
-
diff --git a/gcc/config/i386/dgux.c b/gcc/config/i386/dgux.c
deleted file mode 100755
index 638d1e0..0000000
--- a/gcc/config/i386/dgux.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Subroutines for GNU compiler for Intel 80x86 running DG/ux
-   Copyright (C) 1993, 1995, 1997 Free Software Foundation, Inc.
-   Currently maintained by (gcc@dg-rtp.dg.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <time.h>
-#include "i386/i386.c"
-
-
-extern char *version_string;
-
-struct option
-{
-  char *string;
-  int *variable;
-  int on_value;
-  char *description;
-};
-
-static int
-output_option (file, sep, type, name, indent, pos, max)
-     FILE *file;
-     char *sep;
-     char *type;
-     char *name;
-     char *indent;
-     int pos;
-     int max;
-{
-  if (strlen (sep) + strlen (type) + strlen (name) + pos > max)
-    {
-      fprintf (file, indent);
-      return fprintf (file, "%s%s", type, name);
-    }
-  return pos + fprintf (file, "%s%s%s", sep, type, name);
-}
-
-static struct { char *name; int value; } m_options[] = TARGET_SWITCHES;
-
-static void
-output_options (file, f_options, f_len, W_options, W_len,
-		pos, max, sep, indent, term)
-     FILE *file;
-     struct option *f_options;
-     struct option *W_options;
-     int f_len, W_len;
-     int pos;
-     int max;
-     char *indent;
-     char *term;
-{
-  register int j;
-
-  if (optimize)
-    pos = output_option (file, sep, "-O", "", indent, pos, max);
-  if (write_symbols != NO_DEBUG)
-    pos = output_option (file, sep, "-g", "", indent, pos, max);
-/*  if (flag_traditional)
-    pos = output_option (file, sep, "-traditional", "", indent, pos, max);*/
-  if (profile_flag)
-    pos = output_option (file, sep, "-p", "", indent, pos, max);
-  if (profile_block_flag)
-    pos = output_option (file, sep, "-a", "", indent, pos, max);
-
-  for (j = 0; j < f_len; j++)
-    if (*f_options[j].variable == f_options[j].on_value)
-      pos = output_option (file, sep, "-f", f_options[j].string,
-			   indent, pos, max);
-
-  for (j = 0; j < W_len; j++)
-    if (*W_options[j].variable == W_options[j].on_value)
-      pos = output_option (file, sep, "-W", W_options[j].string,
-			   indent, pos, max);
-
-  for (j = 0; j < sizeof m_options / sizeof m_options[0]; j++)
-    if (m_options[j].name[0] != '\0'
-	&& m_options[j].value > 0
-	&& ((m_options[j].value & target_flags)
-	    == m_options[j].value))
-      pos = output_option (file, sep, "-m", m_options[j].name,
-			   indent, pos, max);
-
-  pos = output_option (file, sep, "-mcpu=", ix86_cpu_string, indent, pos, max);
-  pos = output_option (file, sep, "-march=", ix86_arch_string, indent, pos, max);
-  fprintf (file, term);
-}
-
-/* Output to FILE the start of the assembler file.  */
-
-void
-output_file_start (file, f_options, f_len, W_options, W_len)
-     FILE *file;
-     struct option *f_options;
-     struct option *W_options;
-     int f_len, W_len;
-{
-  register int pos;
-
-  output_file_directive (file, main_input_filename);
-  fprintf (file, "\t.version\t\"01.01\"\n");			\
-  /* Switch to the data section so that the coffsem symbol and the
-     gcc2_compiled. symbol aren't in the text section.  */
-  data_section ();
-
-  pos = fprintf (file, "\n// cc1 (%s) arguments:", VERSION_STRING);
-  output_options (file, f_options, f_len, W_options, W_len,
-		  pos, 75, " ", "\n// ", "\n\n");
-
-#ifdef TARGET_IDENTIFY_REVISION
-  if (TARGET_IDENTIFY_REVISION)
-    {
-      char indent[256];
-
-      time_t now = time ((time_t *)0);
-      sprintf (indent, "]\"\n\t%s\t \"@(#)%s [", IDENT_ASM_OP, main_input_filename);
-      fprintf (file, indent+3);
-      pos = fprintf (file, "gcc %s, %.24s,", VERSION_STRING, ctime (&now));
-      output_options (file, f_options, f_len, W_options, W_len,
-		      pos, 150 - strlen (indent), " ", indent, "]\"\n\n");
-    }
-#endif /* TARGET_IDENTIFY_REVISION */
-}
-
-#ifndef CROSS_COMPILE
-#if defined (_abort_aux) 
-/* Debugging aid to be registered via `atexit'.  See the definition
-   of abort in dgux.h.  */
-void
-abort_aux ()
-{
-  extern int insn_;
-  extern char * file_;
-  extern int line_;
-  static int done;
-  rtx line_note;
-
-  if (done++)
-    return;
-  if (file_ || line_)
-    {
-      if (write_symbols != NO_DEBUG)
-	{
-	  for (line_note = (rtx) insn_ ; line_note != 0 ; line_note = PREV_INSN (line_note))
-	    if (GET_CODE (line_note) == NOTE && NOTE_LINE_NUMBER (line_note) > 0)
-	      break;
-	  if (line_note != 0)
-	    {
-	      error_with_file_and_line (NOTE_SOURCE_FILE (line_note),
-					NOTE_LINE_NUMBER (line_note),
-					"Internal gcc abort from %s:%d",
-					file_ ? file_ : "<nofile>", line_);
-	      if (insn_ && file_ && strcmp (file_, "toplev.c"))
-		{
-		  error_with_file_and_line (NOTE_SOURCE_FILE (line_note),
-					    NOTE_LINE_NUMBER (line_note),
-					    "The local variable `insn' has the value:", 0);
-		  debug_rtx ((rtx) insn_);
-		}
-	    }
-	}
-      if (write_symbols == NO_DEBUG || line_note == 0)
-	{
-	  error ("Internal gcc abort from %s:%d",
-		 file_ ? file_ : "<nofile>", line_);
-	  if (insn_ && file_ && strcmp (file_, "toplev.c"))
-	    {
-	      error ("The local variable `insn' has the value:", 0);
-	      debug_rtx ((rtx) insn_);
-	    }
-	}
-    }
-}
-#endif
-#endif
-
-
diff --git a/gcc/config/i386/dgux.h b/gcc/config/i386/dgux.h
deleted file mode 100755
index 75eacb4..0000000
--- a/gcc/config/i386/dgux.h
+++ /dev/null
@@ -1,266 +0,0 @@
-/* Target definitions for GNU compiler for Intel 80x86 running DG/ux
-   Copyright (C) 1993, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Currently maintained by gcc@dg-rtp.dg.com.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* for now, we are just like the sysv4 version with a
-   few hacks
-*/
-
-#include "i386/sysv4.h"
-
-#ifndef VERSION_INFO2
-#define VERSION_INFO2   "$Revision: 1.4 $"
-#endif
-
-#ifndef VERSION_STRING
-#define VERSION_STRING  version_string
-#endif
-
-/* Identify the compiler.  */
-/* TARGET_VERSION used by toplev.c VERSION_STRING used by -midentify-revision */
-
-#undef	TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (%s%s, %s)", \
-				VERSION_INFO1, VERSION_INFO2, __DATE__)
-#undef  VERSION_INFO1
-#define VERSION_INFO1 "ix86 DG/ux, "
-
-/* Augment TARGET_SWITCHES with the MXDB options.  */
-#define MASK_STANDARD		0x40000000 /* Retain standard information */
-#define MASK_NOLEGEND		0x20000000 /* Discard legend information */
-#define MASK_EXTERNAL_LEGEND	0x10000000 /* Make external legends */
-#define MASK_IDENTIFY_REVISION  0x08000000 /* Emit 'ident' to .s */
-#define MASK_WARN_PASS_STRUCT   0x04000000 /* Emit 'ident' to .s */
-
-#define TARGET_STANDARD		  (target_flags & MASK_STANDARD)
-#define TARGET_NOLEGEND		  (target_flags & MASK_NOLEGEND)
-#define TARGET_EXTERNAL_LEGEND	  (target_flags & MASK_EXTERNAL_LEGEND)
-#define TARGET_IDENTIFY_REVISION  (target_flags & MASK_IDENTIFY_REVISION)
-#define TARGET_WARN_PASS_STRUCT   (target_flags & MASK_WARN_PASS_STRUCT)
-
-#undef  SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-    { "standard",			 MASK_STANDARD },          \
-    { "legend",				-MASK_NOLEGEND },          \
-    { "no-legend",			 MASK_NOLEGEND },          \
-    { "external-legend",		 MASK_EXTERNAL_LEGEND },   \
-    { "identify-revision", 		 MASK_IDENTIFY_REVISION }, \
-    { "warn-passed-structs", 		 MASK_WARN_PASS_STRUCT },
-
-#undef  DWARF_DEBUGGING_INFO
-#define DWARF_DEBUGGING_INFO
-
-/*
-  allow -gstabs so that those who have gnu-as installed
-  can debug c++ programs.
-*/
-#undef  DBX_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-
-#define PREFERRED_DEBUGGING_TYPE DWARF_DEBUG
-
-/* Override svr[34].h.  */
-#undef	ASM_FILE_START
-#define ASM_FILE_START(FILE) \
-  output_file_start (FILE, f_options, sizeof f_options / sizeof f_options[0], \
-		     W_options, sizeof W_options / sizeof W_options[0])
-
-/* ix86 abi specified type for wchar_t */
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-
-/* Some machines may desire to change what optimizations are performed for
-   various optimization levels.   This macro, if defined, is executed once
-   just after the optimization level is determined and before the remainder
-   of the command options have been parsed.  Values set in this macro are
-   used as the default values for the other command line options.
-
-   LEVEL is the optimization level specified; 2 if -O2 is specified,
-   1 if -O is specified, and 0 if neither is specified.  */
-
-/* This macro used to store 0 in flag_signed_bitfields.
-   Not only is that misuse of this macro; the whole idea is wrong.
-
-   The GNU C dialect makes bitfields signed by default,
-   regardless of machine type.  Making any machine inconsistent in this
-   regard is bad for portability.
-
-   I chose to make bitfields signed by default because this is consistent
-   with the way ordinary variables are handled: `int' equals `signed int'.
-   If there is a good reason to prefer making bitfields unsigned by default,
-   it cannot have anything to do with the choice of machine.
-   If the reason is good enough, we should change the convention for all machines.
-
-   -- rms, 20 July 1991.  */
-
-/*
-  this really should go into dgux-local.h 
-*/
-
-#undef	OPTIMIZATION_OPTIONS
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)		\
-  do {							\
-    extern int flag_signed_bitfields;			\
-    flag_signed_bitfields = 0;				\
-    abort_helper ();					\
-    optimization_options (LEVEL,SIZE);			\
-  } while (0)
-
-
-/* The normal location of the `ld' and `as' programs */
-
-#undef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "/usr/bin/"
-
-/* The normal location of the various *crt*.o files is the */
-
-#undef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/lib/"
-
-/* Macros to be automatically defined.  
-   __CLASSIFY_TYPE__ is used in the <varargs.h> and <stdarg.h> header
-   files with DG/UX revision 5.40 and later.  This allows GNU CC to
-   operate without installing the header files.  */
-
-#undef	CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di386 -D__ix86 -Dunix -DDGUX -D__CLASSIFY_TYPE__=2\
-   -Asystem(unix) -Asystem(svr4) -Acpu(i386) -Amachine(i386)"
-
-   /*
-     If not -ansi, -traditional, or restricting include files to one
-     specific source target, specify full DG/UX features.
-   */
-#undef	CPP_SPEC
-#define	CPP_SPEC "%{!ansi:%{!traditional:-D__OPEN_NAMESPACE__}}"
-
-/* Assembler support (legends for mxdb).  */
-#undef	ASM_SPEC
-#define ASM_SPEC "\
-%{mno-legend:%{mstandard:-Wc,off}}\
-%{g:%{!mno-legend:-Wc,-fix-bb,-s\"%i\"\
-%{traditional:,-lc}%{!traditional:,-lansi-c}\
-%{mstandard:,-keep-std}\
-%{mexternal-legend:,-external}}}"
-
-/* Override svr4.h.  */
-
-/* hassey 3/12/94 keep svr4 ASM_FINAL_SPEC allows -pipe to work */
-
-/* Linker and library spec's.
-   -static, -shared, -symbolic, -h* and -z* access AT&T V.4 link options.
-   -svr4 instructs gcc to place /usr/lib/values-X[cat].o on link the line.
-   The absence of -msvr4 indicates linking done in a COFF environment and
-   adds the link script to the link line.  In all environments, the first
-   and last objects are crtbegin.o and crtend.o.
-   When the -G link option is used (-shared and -symbolic) a final link is
-   not being done.  */
-
-#undef	LIB_SPEC
-#define LIB_SPEC \
-"%{!shared:%{!symbolic:-lc}}"
-
-#undef	LINK_SPEC
-#define LINK_SPEC "%{z*} %{h*} %{v:-V} \
-		   %{static:-dn -Bstatic} \
-		   %{shared:-G -dy} \
-		   %{symbolic:-Bsymbolic -G -dy} \
-		   %{pg:-L/usr/lib/libp}%{p:-L/usr/lib/libp}"
-
-#ifdef CROSS_COMPILE
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared:%{!symbolic:%{pg:gcrt1.o%s} 		\
-			                      %{!pg:%{p:mcrt1.o%s} 	\
-					      %{!p:crt1.o%s}}}} 	\
-			 %{pg:gcrti.o%s}%{!pg:crti.o%s} 		\
-			 crtbegin.o%s 					\
-			 %{ansi:values-Xc.o%s} 				\
-			 %{!ansi:%{traditional:values-Xt.o%s} 		\
-			         %{!traditional:values-Xa.o%s}}"
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s %{pg:gcrtn.o}%{!pg:crtn.o%s}"
-
-#else
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared:%{!symbolic:%{pg:gcrt1.o%s} 		\
-			                      %{!pg:%{p:/lib/mcrt1.o%s}	\
-					      %{!p:/lib/crt1.o%s}}} 	\
-			%{pg:gcrti.o%s}%{!pg:/lib/crti.o%s}} 		\
-			crtbegin.o%s 					\
-			%{ansi:/lib/values-Xc.o%s} 			\
-			%{!ansi:%{traditional:/lib/values-Xt.o%s} 	\
-			        %{!traditional:/lib/values-Xa.o%s}}"
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s %{pg:gcrtn.o}%{!pg:/lib/crtn.o}"
-
-#endif /* CROSS_COMPILE */
-
-#if !defined (no_abort) || defined (CRT_BEGIN) || defined (CRT_END)
-#undef abort
-
-char insn; int insn_; char * file_; int line_;
-#define abort()			\
-  (insn_ = (int) insn,		\
-   file_ = __FILE__,		\
-   line_ = __LINE__,		\
-   fancy_abort ())
-#define abort_helper()		\
-  do {				\
-    extern void abort_aux ();	\
-    atexit (abort_aux);		\
-  } while (0)
-#define _abort_aux
-#endif /* no abort */
-
-/* The maximum alignment which the object file format can support.
-   page alignment would seem to be enough */
-#undef MAX_OFILE_ALIGNMENT
-#define MAX_OFILE_ALIGNMENT 0x1000
-
-/* Must use data section for relocatable constants when pic.  */
-#undef SELECT_RTX_SECTION
-#define SELECT_RTX_SECTION(MODE,RTX)            \
-{                                               \
-  if (flag_pic && symbolic_operand (RTX))       \
-    data_section ();                            \
-  else                                          \
-    const_section ();                           \
-}
-
-/* This supplements FUNCTION_ARG's definition in i386.h to check
-   TARGET_WARN_PASS_STRUCT */
-
-#undef  FUNCTION_ARG
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-((((MODE) == BLKmode && TARGET_WARN_PASS_STRUCT) ? \
-    warning ("argument is a structure"),0 : 0), \
-    (function_arg (&CUM, MODE, TYPE, NAMED)))
-
-/* Add .align 1 to avoid .backalign bug in assembler */
-#undef CONST_SECTION_ASM_OP
-#define CONST_SECTION_ASM_OP    ".section\t.rodata\n\t.align 1"
diff --git a/gcc/config/i386/freebsd-elf.h b/gcc/config/i386/freebsd-elf.h
deleted file mode 100755
index 3c1934b..0000000
--- a/gcc/config/i386/freebsd-elf.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/* Definitions for Intel 386 running FreeBSD with ELF format
-   Copyright (C) 1996 Free Software Foundation, Inc.
-   Contributed by Eric Youngdale.
-   Modified for stabs-in-ELF by H.J. Lu.
-   Adapted from GNU/Linux version by John Polstra.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i386 FreeBSD/ELF)");
-
-/* The svr4 ABI for the i386 says that records and unions are returned
-   in memory.  */
-#undef DEFAULT_PCC_STRUCT_RETURN
-#define DEFAULT_PCC_STRUCT_RETURN 1
-
-/* This is how to output an element of a case-vector that is relative.
-   This is only used for PIC code.  See comments by the `casesi' insn in
-   i386.md for an explanation of the expression this outputs. */
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE)
-
-/* Indicate that jump tables go in the text section.  This is
-   necessary when compiling PIC code.  */
-#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
-
-/* Copy this from the svr4 specifications... */
-/* Define the register numbers to be used in Dwarf debugging information.
-   The SVR4 reference port C compiler uses the following register numbers
-   in its Dwarf output code:
-	0 for %eax (gnu regno = 0)
-	1 for %ecx (gnu regno = 2)
-	2 for %edx (gnu regno = 1)
-	3 for %ebx (gnu regno = 3)
-	4 for %esp (gnu regno = 7)
-	5 for %ebp (gnu regno = 6)
-	6 for %esi (gnu regno = 4)
-	7 for %edi (gnu regno = 5)
-   The following three DWARF register numbers are never generated by
-   the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
-   believes these numbers have these meanings.
-	8  for %eip    (no gnu equivalent)
-	9  for %eflags (no gnu equivalent)
-	10 for %trapno (no gnu equivalent)
-   It is not at all clear how we should number the FP stack registers
-   for the x86 architecture.  If the version of SDB on x86/svr4 were
-   a bit less brain dead with respect to floating-point then we would
-   have a precedent to follow with respect to DWARF register numbers
-   for x86 FP registers, but the SDB on x86/svr4 is so completely
-   broken with respect to FP registers that it is hardly worth thinking
-   of it as something to strive for compatibility with.
-   The version of x86/svr4 SDB I have at the moment does (partially)
-   seem to believe that DWARF register number 11 is associated with
-   the x86 register %st(0), but that's about all.  Higher DWARF
-   register numbers don't seem to be associated with anything in
-   particular, and even for DWARF regno 11, SDB only seems to under-
-   stand that it should say that a variable lives in %st(0) (when
-   asked via an `=' command) if we said it was in DWARF regno 11,
-   but SDB still prints garbage when asked for the value of the
-   variable in question (via a `/' command).
-   (Also note that the labels SDB prints for various FP stack regs
-   when doing an `x' command are all wrong.)
-   Note that these problems generally don't affect the native SVR4
-   C compiler because it doesn't allow the use of -O with -g and
-   because when it is *not* optimizing, it allocates a memory
-   location for each floating-point variable, and the memory
-   location is what gets described in the DWARF AT_location
-   attribute for the variable in question.
-   Regardless of the severe mental illness of the x86/svr4 SDB, we
-   do something sensible here and we use the following DWARF
-   register numbers.  Note that these are all stack-top-relative
-   numbers.
-	11 for %st(0) (gnu regno = 8)
-	12 for %st(1) (gnu regno = 9)
-	13 for %st(2) (gnu regno = 10)
-	14 for %st(3) (gnu regno = 11)
-	15 for %st(4) (gnu regno = 12)
-	16 for %st(5) (gnu regno = 13)
-	17 for %st(6) (gnu regno = 14)
-	18 for %st(7) (gnu regno = 15)
-*/
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n) \
-((n) == 0 ? 0 \
- : (n) == 1 ? 2 \
- : (n) == 2 ? 1 \
- : (n) == 3 ? 3 \
- : (n) == 4 ? 6 \
- : (n) == 5 ? 7 \
- : (n) == 6 ? 5 \
- : (n) == 7 ? 4 \
- : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \
- : (-1))
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-{									\
-  if (flag_pic)								\
-    {									\
-      fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n",		\
-	       LPREFIX, (LABELNO));					\
-      fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n");			\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO));	\
-      fprintf (FILE, "\tcall mcount\n");				\
-    }									\
-}
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
- 
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-  
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "int"
-   
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-    
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di386 -Dunix -D__ELF__ -D__FreeBSD__ -Asystem(unix) -Asystem(FreeBSD) -Acpu(i386) -Amachine(i386)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) %{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}"
-
-#undef	LIB_SPEC
-#if 1
-/* We no longer link with libc_p.a or libg.a by default. If you
- * want to profile or debug the C library, please add
- * -lc_p or -ggdb to LDFLAGS at the link time, respectively.
- */
-#define LIB_SPEC \
-  "%{!shared: %{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} \
-     %{!ggdb:-lc} %{ggdb:-lg}}"
-#else
-#define LIB_SPEC \
-  "%{!shared: \
-     %{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \
-       %{!p:%{!pg:%{!g*:-lc} %{g*:-lg}}}}"
-#endif
-
-/* Provide a LINK_SPEC appropriate for FreeBSD.  Here we provide support
-   for the special GCC options -static and -shared, which allow us to
-   link things in one of these three modes by applying the appropriate
-   combinations of options at link-time. We like to support here for
-   as many of the other GNU linker options as possible. But I don't
-   have the time to search for those flags. I am sure how to add
-   support for -soname shared_object_name. H.J.
-
-   I took out %{v:%{!V:-V}}. It is too much :-(. They can use
-   -Wl,-V.
-
-   When the -shared link option is used a final link is not being
-   done.  */
-
-#undef	LINK_SPEC
-#define LINK_SPEC "-m elf_i386 %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-	%{rdynamic:-export-dynamic} \
-	%{!dynamic-linker:-dynamic-linker /usr/libexec/ld-elf.so.1}} \
-	%{static:-static}}}"
-
-/* Get perform_* macros to build libgcc.a.  */
-
-/* A C statement to output to the stdio stream FILE an assembler
-   command to advance the location counter to a multiple of 1<<LOG
-   bytes if it is within MAX_SKIP bytes.
-
-   This is used to align code labels according to Intel recommendations.  */
-
-#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
-#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
-  if ((LOG)!=0) \
-    if ((MAX_SKIP)==0) fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
-    else fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP))
-#endif
diff --git a/gcc/config/i386/freebsd.h b/gcc/config/i386/freebsd.h
deleted file mode 100755
index df653ae..0000000
--- a/gcc/config/i386/freebsd.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/* Definitions of target machine for GNU compiler for Intel 80386
-   running FreeBSD.
-   Copyright (C) 1988, 1992, 1994, 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Poul-Henning Kamp <phk@login.dkuug.dk>
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This goes away when the math-emulator is fixed */
-#define TARGET_CPU_DEFAULT 0400		/* TARGET_NO_FANCY_MATH_387 */
-
-/* This is tested by i386gas.h.  */
-#define YES_UNDERSCORES
-
-/* Don't assume anything about the header files. */
-#define NO_IMPLICIT_EXTERN_C
-
-#include "i386/gstabs.h"
-
-/* Get perform_* macros to build libgcc.a.  */
-#include "i386/perform.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Di386 -D__FreeBSD__ -Asystem(unix) -Asystem(FreeBSD) -Acpu(i386) -Amachine(i386)"
-
-/* Like the default, except no -lg.  */
-#define LIB_SPEC "%{!shared:%{!pg:-lc}%{pg:-lc_p}}"
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "int"
-
-#define WCHAR_UNSIGNED 0
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-#define HAVE_ATEXIT
-
-/* Override the default comment-starter of "/".  */
-
-#undef ASM_COMMENT_START
-#define ASM_COMMENT_START "#"
-
-#undef ASM_APP_ON
-#define ASM_APP_ON "#APP\n"
-
-#undef ASM_APP_OFF
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* FreeBSD using a.out does not support DWARF2 unwinding mechanisms.  */
-#define DWARF2_UNWIND_INFO 0
-
-/* The following macros are stolen from i386v4.h */
-/* These have to be defined to get PIC code correct */
-
-/* This is how to output an element of a case-vector that is relative.
-   This is only used for PIC code.  See comments by the `casesi' insn in
-   i386.md for an explanation of the expression this outputs. */
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE)
-
-/* Indicate that jump tables go in the text section.  This is
-   necessary when compiling PIC code.  */
-
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* i386 freebsd still uses old binutils that don't insert nops by default
-   when the .align directive demands to insert extra space in the text
-   segment.  */
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
-  if ((LOG)!=0) fprintf ((FILE), "\t.align %d,0x90\n", (LOG))
-
-/* Profiling routines, partially copied from i386/osfrose.h.  */
-
-/* Redefine this to use %eax instead of %edx.  */
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-{									\
-  if (flag_pic)								\
-    {									\
-      fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%eax\n",		\
-	       LPREFIX, (LABELNO));					\
-      fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n");			\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\tmovl $%sP%d,%%eax\n", LPREFIX, (LABELNO));	\
-      fprintf (FILE, "\tcall mcount\n");				\
-    }									\
-}
-
-/*
- * Some imports from svr4.h in support of shared libraries.
- * Currently, we need the DECLARE_OBJECT_SIZE stuff.
- */
-
-/* Define the strings used for the special svr4 .type and .size directives.
-   These strings generally do not vary from one system running svr4 to
-   another, but if a given system (e.g. m88k running svr) needs to use
-   different pseudo-op names for these, they may be overridden in the
-   file which includes this one.  */
-
-#define TYPE_ASM_OP	".type"
-#define SIZE_ASM_OP	".size"
-
-/* The following macro defines the format used to output the second
-   operand of the .type assembler directive.  Different svr4 assemblers
-   expect various different forms for this operand.  The one given here
-   is just a default.  You may need to override it in your machine-
-   specific tm.h file (depending upon the particulars of your assembler).  */
-
-#define TYPE_OPERAND_FMT	"@%s"
-
-/* Write the extra assembler code needed to declare a function's result.
-   Most svr4 assemblers don't require any special declaration of the
-   result value, but there are exceptions.  */
-
-#ifndef ASM_DECLARE_RESULT
-#define ASM_DECLARE_RESULT(FILE, RESULT)
-#endif
-
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare a function properly.
-   Some svr4 assemblers need to also have something extra said about the
-   function's return value.  We allow for that here.  */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "function");			\
-    putc ('\n', FILE);							\
-    ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));			\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Write the extra assembler code needed to declare an object properly.  */
-
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
-    putc ('\n', FILE);							\
-    size_directive_output = 0;						\
-    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-      {									\
-        size_directive_output = 1;					\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-	fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));	\
-      }									\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)        \
-do {                                                                    \
-     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);                  \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)	        \
-         && ! AT_END && TOP_LEVEL                                       \
-         && DECL_INITIAL (DECL) == error_mark_node                      \
-         && !size_directive_output)                                     \
-       {                                                                \
-         fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);                        \
-	 assemble_name (FILE, name);                                    \
-	 fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));\
-	}								\
-   } while (0)
-
-
-/* This is how to declare the size of a function.  */
-
-#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)			\
-  do {									\
-    if (!flag_inhibit_size_directive)					\
-      {									\
-        char label[256];						\
-	static int labelno;						\
-	labelno++;							\
-	ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno);		\
-	ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno);		\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, (FNAME));					\
-        fprintf (FILE, ",");						\
-	assemble_name (FILE, label);					\
-        fprintf (FILE, "-");						\
-	assemble_name (FILE, (FNAME));					\
-	putc ('\n', FILE);						\
-      }									\
-  } while (0)
-
-#define ASM_SPEC   " %| %{fpic:-k} %{fPIC:-k}"
-#define LINK_SPEC \
-  "%{p:%e`-p' not supported; use `-pg' and gprof(1)} \
-   %{shared:-Bshareable} \
-   %{!shared:%{!nostdlib:%{!r:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} \
-   %{pg:-Bstatic} %{Z}} \
-   %{assert*} %{R*}"
-
-#define STARTFILE_SPEC  \
-  "%{shared:c++rt0.o%s} \
-   %{!shared:%{pg:gcrt0.o%s}%{!pg:%{static:scrt0.o%s}%{!static:crt0.o%s}}}"
-
-/* This is defined when gcc is compiled in the BSD-directory-tree, and must
- * make up for the gap to all the stuff done in the GNU-makefiles.
- */
-
-#ifdef FREEBSD_NATIVE
-
-#define INCLUDE_DEFAULTS { \
-	{ "/usr/include", 0, 0, 0 }, \
-	{ "/usr/include/g++", "G++", 1, 1 }, \
-	{ 0, 0, 0, 0} \
-	}
-
-#undef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "/usr/libexec/"
-
-#undef STANDARD_STARTFILE_PREFIX
-#define STANDARD_STARTFILE_PREFIX "/usr/lib"
-
-#if 0 /* This is very wrong!!! */
-#define DEFAULT_TARGET_MACHINE "i386-unknown-freebsd_1.0"
-#define GPLUSPLUS_INCLUDE_DIR "/usr/local/lib/gcc-lib/i386-unknown-freebsd_1.0/2.5.8/include"
-#define TOOL_INCLUDE_DIR "/usr/local/i386-unknown-freebsd_1.0/include"
-#define GCC_INCLUDE_DIR "/usr/local/lib/gcc-lib/i386-unknown-freebsd_1.0/2.5.8/include"
-#endif
-
-#endif /* FREEBSD_NATIVE */
diff --git a/gcc/config/i386/gas.h b/gcc/config/i386/gas.h
deleted file mode 100755
index 173bf19..0000000
--- a/gcc/config/i386/gas.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* Definitions for Intel 386 using GAS.
-   Copyright (C) 1988, 1993, 1994, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Note that i386/seq-gas.h is a GAS configuration that does not use this
-   file. */
-
-#include "i386/i386.h"
-
-#ifndef YES_UNDERSCORES
-/* Define this now, because i386/bsd.h tests it.  */
-#define NO_UNDERSCORES
-#endif
-
-/* Use the bsd assembler syntax.  */
-/* we need to do this because gas is really a bsd style assembler,
- * and so doesn't work well this these att-isms:
- *
- *  ASM_OUTPUT_SKIP is .set .,.+N, which isn't implemented in gas
- *  ASM_OUTPUT_LOCAL is done with .set .,.+N, but that can't be
- *   used to define bss static space
- *
- * Next is the question of whether to uses underscores.  RMS didn't
- * like this idea at first, but since it is now obvious that we
- * need this separate tm file for use with gas, at least to get
- * dbx debugging info, I think we should also switch to underscores.
- * We can keep i386v for real att style output, and the few
- * people who want both form will have to compile twice.
- */
-
-#include "i386/bsd.h"
-
-/* these come from i386/bsd.h, but are specific to sequent */
-#undef DBX_NO_XREFS
-#undef DBX_CONTIN_LENGTH
-
-/* Ask for COFF symbols.  */
-
-#define SDB_DEBUGGING_INFO
-
-/* Specify predefined symbols in preprocessor.  */
-
-#define CPP_PREDEFINES "-Dunix"
-#define CPP_SPEC "%(cpp_cpu) %{posix:-D_POSIX_SOURCE}"
-
-/* Allow #sccs in preprocessor.  */
-
-#define SCCS_DIRECTIVE
-
-/* Output #ident as a .ident.  */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-
-/* Implicit library calls should use memcpy, not bcopy, etc.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* In the past there was confusion as to what the argument to .align was
-   in GAS.  For the last several years the rule has been this: for a.out
-   file formats that argument is LOG, and for all other file formats the
-   argument is 1<<LOG.
-
-   However, GAS now has .p2align and .balign pseudo-ops so to remove any
-   doubt or guess work, and since this file is used for both a.out and other
-   file formats, we use one of them.  */
-
-#ifdef HAVE_GAS_BALIGN_AND_P2ALIGN 
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
-  if ((LOG)!=0) fprintf ((FILE), "\t.balign %d\n", 1<<(LOG))
-#endif
-
-/* A C statement to output to the stdio stream FILE an assembler
-   command to advance the location counter to a multiple of 1<<LOG
-   bytes if it is within MAX_SKIP bytes.
-
-   This is used to align code labels according to Intel recommendations.  */
-
-#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
-#  define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
-     if ((LOG)!=0) \
-       if ((MAX_SKIP)==0) fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
-       else fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP))
-#endif
-
-/* A C statement or statements which output an assembler instruction
-   opcode to the stdio stream STREAM.  The macro-operand PTR is a
-   variable of type `char *' which points to the opcode name in its
-   "internal" form--the form that is written in the machine description.
-
-   GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic.
-   So use `repe' instead.  */
-
-#define ASM_OUTPUT_OPCODE(STREAM, PTR)	\
-{									\
-  if ((PTR)[0] == 'r'							\
-      && (PTR)[1] == 'e'						\
-      && (PTR)[2] == 'p')						\
-    {									\
-      if ((PTR)[3] == 'z')						\
-	{								\
-	  fprintf (STREAM, "repe");					\
-	  (PTR) += 4;							\
-	}								\
-      else if ((PTR)[3] == 'n' && (PTR)[4] == 'z')			\
-	{								\
-	  fprintf (STREAM, "repne");					\
-	  (PTR) += 5;							\
-	}								\
-    }									\
-}
-
-/* Define macro used to output shift-double opcodes when the shift
-   count is in %cl.  Some assemblers require %cl as an argument;
-   some don't.
-
-   GAS requires the %cl argument, so override i386/unix.h. */
-
-#undef SHIFT_DOUBLE_OMITS_COUNT
-#define SHIFT_DOUBLE_OMITS_COUNT 0
-
-/* Print opcodes the way that GAS expects them. */
-#define GAS_MNEMONICS 1
-
-#ifdef NO_UNDERSCORES /* If user-symbols don't have underscores,
-			 then it must take more than `L' to identify
-			 a label that should be ignored.  */
-
-/* This is how to store into the string BUF
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER)	\
-    sprintf ((BUF), ".%s%d", (PREFIX), (NUMBER))
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-#endif /* NO_UNDERSCORES */
diff --git a/gcc/config/i386/gmon-sol2.c b/gcc/config/i386/gmon-sol2.c
deleted file mode 100755
index 35ac1c9..0000000
--- a/gcc/config/i386/gmon-sol2.c
+++ /dev/null
@@ -1,409 +0,0 @@
-/*-
- * Copyright (c) 1991 The Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * This is a modified gmon.c by J.W.Hawtin <oolon@ankh.org>,
- * 14/8/96 based on the original gmon.c in GCC and the hacked version
- * solaris 2 sparc version (config/sparc/gmon-sol.c) by Mark Eichin. To do
- * process profiling on solaris 2.X X86
- *
- * It must be used in conjunction with sol2-gc1.asm, which is used to start
- * and stop process monitoring.
- *
- * Differences.
- *
- * On Solaris 2 _mcount is called by library functions not mcount, so support
- * has been added for both.
- *
- * Also the prototype for profil() is different
- *
- * Solaris 2 does not seem to have char *minbrk whcih allows the setting of
- * the minimum SBRK region so this code has been removed and lets pray malloc
- * does not mess it up.
- *
- * Notes
- *
- * This code could easily be integrated with the original gmon.c and perhaps
- * should be.
- */
-
-#ifndef lint
-static char sccsid[] = "@(#)gmon.c	5.3 (Berkeley) 5/22/91";
-#endif /* not lint */
-
-#if 0
-#include <unistd.h>
-
-#endif
-#ifdef DEBUG
-#include <stdio.h>
-#endif
-
-#if 0
-#include "i386/gmon.h"
-#else
-
-struct phdr {
-                char    *lpc;
-                char    *hpc;
-                int     ncnt;
-};
-
-
-#define HISTFRACTION 2
-#define HISTCOUNTER unsigned short
-#define HASHFRACTION 1
-#define ARCDENSITY 2
-#define MINARCS 50
-#define BASEADDRESS 0x8000000 /* On Solaris 2 X86 all executables start here
-				 and not at 0 */ 
-
-struct tostruct {
-  char *selfpc;
-  long count;
-  unsigned short link;
-};
-struct rawarc {
-    unsigned long       raw_frompc;
-    unsigned long       raw_selfpc;
-    long                raw_count;
-};
-#define ROUNDDOWN(x,y)  (((x)/(y))*(y))
-#define ROUNDUP(x,y)    ((((x)+(y)-1)/(y))*(y))
-#endif
-
-/* char *minbrk; */
-
-#ifdef __alpha
-extern char *sbrk ();
-#endif
-
-    /*
-     *	froms is actually a bunch of unsigned shorts indexing tos
-     */
-static int		profiling = 3;
-static unsigned short	*froms;
-static struct tostruct	*tos = 0;
-static long		tolimit = 0;
-static char		*s_lowpc = 0;
-static char		*s_highpc = 0;
-static unsigned long	s_textsize = 0;
-
-static int	ssiz;
-static char	*sbuf;
-static int	s_scale;
-    /* see profil(2) where this is describe (incorrectly) */
-#define		SCALE_1_TO_1	0x10000L
-
-#define	MSG "No space for profiling buffer(s)\n"
-
-extern int errno;
-
-monstartup(lowpc, highpc)
-    char	*lowpc;
-    char	*highpc;
-{
-    int			monsize;
-    char		*buffer;
-    register int	o;
-
-	/*
-	 *	round lowpc and highpc to multiples of the density we're using
-	 *	so the rest of the scaling (here and in gprof) stays in ints.
-	 */
-    lowpc = (char *)
-	    ROUNDDOWN((unsigned)lowpc, HISTFRACTION*sizeof(HISTCOUNTER));
-    s_lowpc = lowpc;
-    highpc = (char *)
-	    ROUNDUP((unsigned)highpc, HISTFRACTION*sizeof(HISTCOUNTER));
-    s_highpc = highpc;
-    s_textsize = highpc - lowpc;
-    monsize = (s_textsize / HISTFRACTION) + sizeof(struct phdr);
-    buffer = (char *) sbrk( monsize );
-    if ( buffer == (char *) -1 ) {
-	write( 2 , MSG , sizeof(MSG) );
-	return;
-    }
-    froms = (unsigned short *) sbrk( s_textsize / HASHFRACTION );
-    if ( froms == (unsigned short *) -1 ) {
-	write( 2 , MSG , sizeof(MSG) );
-	froms = 0;
-	return;
-    }
-    tolimit = s_textsize * ARCDENSITY / 100;
-    if ( tolimit < MINARCS ) {
-	tolimit = MINARCS;
-    } else if ( tolimit > 65534 ) {
-	tolimit = 65534;
-    }
-    tos = (struct tostruct *) sbrk( tolimit * sizeof( struct tostruct ) );
-    if ( tos == (struct tostruct *) -1 ) {
-	write( 2 , MSG , sizeof(MSG) );
-	froms = 0;
-	tos = 0;
-	return;
-    }
-/*    minbrk = (char *) sbrk(0);*/
-    tos[0].link = 0;
-    sbuf = buffer;
-    ssiz = monsize;
-    ( (struct phdr *) buffer ) -> lpc = lowpc;
-    ( (struct phdr *) buffer ) -> hpc = highpc;
-    ( (struct phdr *) buffer ) -> ncnt = ssiz;
-    monsize -= sizeof(struct phdr);
-    if ( monsize <= 0 )
-	return;
-    o = highpc - lowpc;
-    if( monsize < o )
-#ifndef hp300
-	s_scale = ( (float) monsize / o ) * SCALE_1_TO_1;
-#else /* avoid floating point */
-    {
-	int quot = o / monsize;
-
-	if (quot >= 0x10000)
-		s_scale = 1;
-	else if (quot >= 0x100)
-		s_scale = 0x10000 / quot;
-	else if (o >= 0x800000)
-		s_scale = 0x1000000 / (o / (monsize >> 8));
-	else
-		s_scale = 0x1000000 / ((o << 8) / monsize);
-    }
-#endif
-    else
-	s_scale = SCALE_1_TO_1;
-    moncontrol(1);
-}
-
-_mcleanup()
-{
-    int			fd;
-    int			fromindex;
-    int			endfrom;
-    char		*frompc;
-    int			toindex;
-    struct rawarc	rawarc;
-
-    moncontrol(0);
-    fd = creat( "gmon.out" , 0666 );
-    if ( fd < 0 ) {
-	perror( "mcount: gmon.out" );
-	return;
-    }
-#   ifdef DEBUG
-	fprintf( stderr , "[mcleanup] sbuf 0x%x ssiz %d\n" , sbuf , ssiz );
-#   endif DEBUG
-
-    write( fd , sbuf , ssiz );
-    endfrom = s_textsize / (HASHFRACTION * sizeof(*froms));
-    for ( fromindex = 0 ; fromindex < endfrom ; fromindex++ ) {
-	if ( froms[fromindex] == 0 ) {
-	    continue;
-	}
-	frompc = s_lowpc + (fromindex * HASHFRACTION * sizeof(*froms));
-	for (toindex=froms[fromindex]; toindex!=0; toindex=tos[toindex].link) {
-#	    ifdef DEBUG
-		fprintf( stderr ,
-			"[mcleanup] frompc 0x%x selfpc 0x%x count %d\n" ,
-			frompc , tos[toindex].selfpc , tos[toindex].count );
-#	    endif DEBUG
-	    rawarc.raw_frompc = (unsigned long) frompc;
-	    rawarc.raw_selfpc = (unsigned long) tos[toindex].selfpc;
-	    rawarc.raw_count = tos[toindex].count;
-	    write( fd , &rawarc , sizeof rawarc );
-	}
-    }
-    close( fd );
-}
-
-/* Solaris 2 libraries use _mcount.  */
-asm(".globl _mcount; _mcount: jmp internal_mcount");
-/* This is for compatibility with old versions of gcc which used mcount.  */
-asm(".globl mcount; mcount: jmp internal_mcount");
-
-internal_mcount()
-{
-	register char			*selfpc;
-	register unsigned short		*frompcindex;
-	register struct tostruct	*top;
-	register struct tostruct	*prevtop;
-	register long			toindex;
-	static char already_setup;
-
-	/*
-	 *	find the return address for mcount,
-	 *	and the return address for mcount's caller.
-	 */
-
-	/* selfpc = pc pushed by mcount call.
-	   This identifies the function that was just entered.  */
-	selfpc = (void *) __builtin_return_address (0);
-	/* frompcindex = pc in preceding frame.
-	   This identifies the caller of the function just entered.  */
-	frompcindex = (void *) __builtin_return_address (1);
-
-	if(!already_setup) {
-          extern etext();
-	  already_setup = 1;
-/*	  monstartup(0, etext); */
-	  monstartup(0x08040000, etext);
-#ifdef USE_ONEXIT
-	  on_exit(_mcleanup, 0);
-#else
-	  atexit(_mcleanup);
-#endif
-	}
-	/*
-	 *	check that we are profiling
-	 *	and that we aren't recursively invoked.
-	 */
-	if (profiling) {
-		goto out;
-	}
-	profiling++;
-	/*
-	 *	check that frompcindex is a reasonable pc value.
-	 *	for example:	signal catchers get called from the stack,
-	 *			not from text space.  too bad.
-	 */
-	frompcindex = (unsigned short *)((long)frompcindex - (long)s_lowpc);
-	if ((unsigned long)frompcindex > s_textsize) {
-		goto done;
-	}
-	frompcindex =
-	    &froms[((long)frompcindex) / (HASHFRACTION * sizeof(*froms))];
-	toindex = *frompcindex;
-	if (toindex == 0) {
-		/*
-		 *	first time traversing this arc
-		 */
-		toindex = ++tos[0].link;
-		if (toindex >= tolimit) {
-			goto overflow;
-		}
-		*frompcindex = toindex;
-		top = &tos[toindex];
-		top->selfpc = selfpc;
-		top->count = 1;
-		top->link = 0;
-		goto done;
-	}
-	top = &tos[toindex];
-	if (top->selfpc == selfpc) {
-		/*
-		 *	arc at front of chain; usual case.
-		 */
-		top->count++;
-		goto done;
-	}
-	/*
-	 *	have to go looking down chain for it.
-	 *	top points to what we are looking at,
-	 *	prevtop points to previous top.
-	 *	we know it is not at the head of the chain.
-	 */
-	for (; /* goto done */; ) {
-		if (top->link == 0) {
-			/*
-			 *	top is end of the chain and none of the chain
-			 *	had top->selfpc == selfpc.
-			 *	so we allocate a new tostruct
-			 *	and link it to the head of the chain.
-			 */
-			toindex = ++tos[0].link;
-			if (toindex >= tolimit) {
-				goto overflow;
-			}
-			top = &tos[toindex];
-			top->selfpc = selfpc;
-			top->count = 1;
-			top->link = *frompcindex;
-			*frompcindex = toindex;
-			goto done;
-		}
-		/*
-		 *	otherwise, check the next arc on the chain.
-		 */
-		prevtop = top;
-		top = &tos[top->link];
-		if (top->selfpc == selfpc) {
-			/*
-			 *	there it is.
-			 *	increment its count
-			 *	move it to the head of the chain.
-			 */
-			top->count++;
-			toindex = prevtop->link;
-			prevtop->link = top->link;
-			top->link = *frompcindex;
-			*frompcindex = toindex;
-			goto done;
-		}
-
-	}
-done:
-	profiling--;
-	/* and fall through */
-out:
-	return;		/* normal return restores saved registers */
-
-overflow:
-	profiling++; /* halt further profiling */
-#   define	TOLIMIT	"mcount: tos overflow\n"
-	write(2, TOLIMIT, sizeof(TOLIMIT));
-	goto out;
-}
-
-/*
- * Control profiling
- *	profiling is what mcount checks to see if
- *	all the data structures are ready.
- */
-moncontrol(mode)
-    int mode;
-{
-    if (mode)
-    {
-      /* start */
-      profil((unsigned short *)(sbuf + sizeof(struct phdr)),
-	     ssiz - sizeof(struct phdr),
-	     (int)s_lowpc, s_scale);
-      
-      profiling = 0;
-    } else {
-      /* stop */
-      profil((unsigned short *)0, 0, 0, 0);
-      profiling = 3;
-    }
-}
diff --git a/gcc/config/i386/gnu.h b/gcc/config/i386/gnu.h
deleted file mode 100755
index 971a5f8..0000000
--- a/gcc/config/i386/gnu.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Configuration for an i386 running GNU with ELF as the target machine.  */
-
-/* This does it mostly for us.  */
-#include <i386/linux.h>
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di386 -Acpu(i386) -Amachine(i386) \
--Dunix -Asystem(unix)  -DMACH -Asystem(mach) -D__GNU__ -Asystem(gnu)"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i386 GNU)");
-
-#undef	LINK_SPEC
-#define LINK_SPEC "-m elf_i386 %{shared:-shared} \
-  %{!shared: \
-    %{!static: \
-      %{rdynamic:-export-dynamic} \
-      %{!dynamic-linker:-dynamic-linker /lib/ld.so}} \
-    %{static:-static}}"
-
-
-/* Get machine-independent configuration parameters for the GNU system.  */
-#include <gnu.h>
diff --git a/gcc/config/i386/go32-rtems.h b/gcc/config/i386/go32-rtems.h
deleted file mode 100755
index 9ae1998..0000000
--- a/gcc/config/i386/go32-rtems.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Configuration for an i386 running RTEMS on top of MS-DOS with
-   djgpp/go32 v1.x.
-
-   Copyright (C) 1996 Free Software Foundation, Inc.
-   Contributed by Joel Sherrill (joel@OARcorp.com).
- 
-This file is part of GNU CC.
- 
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
- 
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
- 
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/go32.h"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#ifdef CPP_PREDEFINES
-#undef CPP_PREDEFINES
-#endif
-#define CPP_PREDEFINES "-Dunix -Di386 -DGO32 -DMSDOS -Drtems -D__rtems__ \
-  -Asystem(unix) -Asystem(msdos) -Acpu(i386) -Amachine(i386) -Asystem(rtems)"
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#ifndef TARGET_MEM_FUNCTIONS
-#define TARGET_MEM_FUNCTIONS
-#endif
-
-/* end of i386/go32-rtems.h */
-
diff --git a/gcc/config/i386/go32.h b/gcc/config/i386/go32.h
deleted file mode 100755
index cad716e..0000000
--- a/gcc/config/i386/go32.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* Configuration for an i386 running MS-DOS with djgpp/go32.  */
-   Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "dbxcoff.h"
-
-/* Don't assume anything about the header files. */
-#define NO_IMPLICIT_EXTERN_C
-
-#define HANDLE_SYSV_PRAGMA
-
-/* Enable parsing of #pragma pack(push,<n>) and #pragma pack(pop).  */
-#define HANDLE_PRAGMA_PACK_PUSH_POP 1
-
-#define YES_UNDERSCORES
-
-#include "i386/gas.h"
-
-/* Search for as.exe and ld.exe in DJGPP's binary directory. */ 
-#define MD_EXEC_PREFIX "$DJDIR/bin/"
-
-/* Correctly handle absolute filename detection in cp/xref.c */
-#define FILE_NAME_ABSOLUTE_P(NAME) \
-        (((NAME)[0] == '/') || ((NAME)[0] == '\\') || \
-        (((NAME)[0] >= 'A') && ((NAME)[0] <= 'z') && ((NAME)[1] == ':')))
-
-#ifdef CPP_PREDEFINES
-#undef CPP_PREDEFINES
-#endif
-#define CPP_PREDEFINES "-Dunix -Di386 -DGO32 -DMSDOS \
-  -Asystem(unix) -Asystem(msdos) -Acpu(i386) -Amachine(i386)"
-
-/* We need to override link_command_spec in gcc.c so support -Tdjgpp.djl.
-   This cannot be done in LINK_SPECS as that LINK_SPECS is processed
-   before library search directories are known by the linker.
-   This avoids problems when specs file is not available. An alternate way,
-   suggested by Robert Hoehne, is to use SUBTARGET_EXTRA_SPECS instead.
-*/ 
-
-#undef LINK_COMMAND_SPEC
-#define LINK_COMMAND_SPEC \
-"%{!fsyntax-only: \
-%{!c:%{!M:%{!MM:%{!E:%{!S:%(linker) %l %X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} \
-\t%{r} %{s} %{t} %{u*} %{x} %{z} %{Z}\
-\t%{!A:%{!nostdlib:%{!nostartfiles:%S}}}\
-\t%{static:} %{L*} %D %o\
-\t%{!nostdlib:%{!nodefaultlibs:%G %L %G}}\
-\t%{!A:%{!nostdlib:%{!nostartfiles:%E}}}\
-\t-Tdjgpp.djl %{T*}}}}}}}\n\
-%{!c:%{!M:%{!MM:%{!E:%{!S:stubify %{v} %{o*:%*} %{!o*:a.out} }}}}}"
- 
-/* Make sure that gcc will not look for .h files in /usr/local/include 
-   unless user explicitly requests it.  */
-#undef LOCAL_INCLUDE_DIR
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_ctor, in_dtor
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS					\
-  CTOR_SECTION_FUNCTION						\
-  DTOR_SECTION_FUNCTION
-
-#define CTOR_SECTION_FUNCTION					\
-void								\
-ctor_section ()							\
-{								\
-  if (in_section != in_ctor)					\
-    {								\
-      fprintf (asm_out_file, "\t.section .ctor\n");		\
-      in_section = in_ctor;					\
-    }								\
-}
-
-#define DTOR_SECTION_FUNCTION					\
-void								\
-dtor_section ()							\
-{								\
-  if (in_section != in_dtor)					\
-    {								\
-      fprintf (asm_out_file, "\t.section .dtor\n");		\
-      in_section = in_dtor;					\
-    }								\
-}
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)	\
-  do {						\
-    ctor_section ();				\
-    fprintf (FILE, "%s\t", ASM_LONG);		\
-    assemble_name (FILE, NAME);			\
-    fprintf (FILE, "\n");			\
-  } while (0)
-
-/* Allow (eg) __attribute__((section "locked")) to work */
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC)\
-  do {						\
-    fprintf (FILE, "\t.section %s\n", NAME);	\
-  } while (0)
-
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)	\
-  do {						\
-    dtor_section ();                   		\
-    fprintf (FILE, "%s\t", ASM_LONG);		\
-    assemble_name (FILE, NAME);              	\
-    fprintf (FILE, "\n");			\
-  } while (0)
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)						\
-  do {									\
-	output_file_directive (FILE, main_input_filename);		\
-  } while (0)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
-  if ((LOG) != 0) fprintf ((FILE), "\t.p2align %d\n", LOG)
-
-/* djgpp has atexit ().  */
-#undef HAVE_ATEXIT
-#define HAVE_ATEXIT
-
-/* djgpp automatically calls its own version of __main, so don't define one
-   in libgcc, nor call one in main().  */
-#define HAS_INIT_SECTION
diff --git a/gcc/config/i386/gstabs.h b/gcc/config/i386/gstabs.h
deleted file mode 100755
index 5f0ae34..0000000
--- a/gcc/config/i386/gstabs.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#include "i386/gas.h"
-
-/* We do not want to output SDB debugging information.  */
-
-#undef SDB_DEBUGGING_INFO
-
-/* We want to output DBX debugging information.  */
-
-#define DBX_DEBUGGING_INFO
diff --git a/gcc/config/i386/i386-aout.h b/gcc/config/i386/i386-aout.h
deleted file mode 100755
index e4be8d5..0000000
--- a/gcc/config/i386/i386-aout.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Definitions for "naked" Intel 386 using a.out (or coff encap'd
-   a.out) object format and stabs debugging info.
-
-   Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* This is tested by gas.h.  */
-#define YES_UNDERSCORES
-
-#include "i386/gstabs.h"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di386"
-
-/* end of i386-aout.h */
diff --git a/gcc/config/i386/i386-coff.h b/gcc/config/i386/i386-coff.h
deleted file mode 100755
index 2e00b7a..0000000
--- a/gcc/config/i386/i386-coff.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Definitions for "naked" Intel 386 using coff object format files
-   and coff debugging info.
-
-   Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "i386/gas.h"
-#include "dbxcoff.h"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di386"
-
-/* We want to be able to get DBX debugging information via -gstabs.  */
-
-#undef DBX_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
-
-/* Support the ctors and dtors sections for g++.  */
-
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"x\""
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"x\""
-
-/* A list of other sections which the compiler might be "in" at any
-   given time.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_ctors, in_dtors
-
-/* A list of extra section function definitions.  */
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-#define INT_ASM_OP ".long"
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-
-/* end of i386-coff.h */
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
deleted file mode 100755
index 3ab7368..0000000
--- a/gcc/config/i386/i386.c
+++ /dev/null
@@ -1,5591 +0,0 @@
-/* Subroutines for insn-output.c for Intel X86.
-   Copyright (C) 1988, 92, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#include <setjmp.h>
-#include "config.h"
-#include "system.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "tree.h"
-#include "flags.h"
-#include "except.h"
-#include "function.h"
-#include "recog.h"
-#include "expr.h"
-#include "toplev.h"
-
-#ifdef EXTRA_CONSTRAINT
-/* If EXTRA_CONSTRAINT is defined, then the 'S'
-   constraint in REG_CLASS_FROM_LETTER will no longer work, and various
-   asm statements that need 'S' for class SIREG will break.  */
- error EXTRA_CONSTRAINT conflicts with S constraint letter
-/* The previous line used to be #error, but some compilers barf
-   even if the conditional was untrue.  */
-#endif
-
-#ifndef CHECK_STACK_LIMIT
-#define CHECK_STACK_LIMIT -1
-#endif
-
-/* Type of an operand for ix86_{binary,unary}_operator_ok */
-enum reg_mem
-{
-  reg_p,
-  mem_p,
-  imm_p
-};
-
-/* Processor costs (relative to an add) */
-struct processor_costs i386_cost = {	/* 386 specific costs */
-  1,					/* cost of an add instruction */
-  1,					/* cost of a lea instruction */
-  3,					/* variable shift costs */
-  2,					/* constant shift costs */
-  6,					/* cost of starting a multiply */
-  1,					/* cost of multiply per each bit set */
-  23					/* cost of a divide/mod */
-};
-
-struct processor_costs i486_cost = {	/* 486 specific costs */
-  1,					/* cost of an add instruction */
-  1,					/* cost of a lea instruction */
-  3,					/* variable shift costs */
-  2,					/* constant shift costs */
-  12,					/* cost of starting a multiply */
-  1,					/* cost of multiply per each bit set */
-  40					/* cost of a divide/mod */
-};
-
-struct processor_costs pentium_cost = {
-  1,					/* cost of an add instruction */
-  1,					/* cost of a lea instruction */
-  4,					/* variable shift costs */
-  1,					/* constant shift costs */
-  11,					/* cost of starting a multiply */
-  0,					/* cost of multiply per each bit set */
-  25					/* cost of a divide/mod */
-};
-
-struct processor_costs pentiumpro_cost = {
-  1,					/* cost of an add instruction */
-  1,					/* cost of a lea instruction */
-  3,					/* variable shift costs */
-  1,					/* constant shift costs */
-  4,					/* cost of starting a multiply */
-  0,					/* cost of multiply per each bit set */
-  17					/* cost of a divide/mod */
-};
-
-struct processor_costs k6_cost = {
-  1,					/* cost of an add instruction */
-  1,					/* cost of a lea instruction */
-  1,					/* variable shift costs */
-  1,					/* constant shift costs */
-  2,					/* cost of starting a multiply */
-  0,					/* cost of multiply per each bit set */
-  18					/* cost of a divide/mod */
-};
-
-struct processor_costs *ix86_cost = &pentium_cost;
-
-/* Processor feature/optimization bitmasks.  */
-#define m_386 (1<<PROCESSOR_I386)
-#define m_486 (1<<PROCESSOR_I486)
-#define m_PENT (1<<PROCESSOR_PENTIUM)
-#define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
-#define m_K6  (1<<PROCESSOR_K6)
-
-const int x86_use_leave = m_386 | m_K6;
-const int x86_push_memory = m_386 | m_K6;
-const int x86_zero_extend_with_and = m_486 | m_PENT;
-const int x86_movx = m_386 | m_PPRO | m_K6;
-const int x86_double_with_add = ~m_386;
-const int x86_use_bit_test = m_386;
-const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO;
-const int x86_use_q_reg = m_PENT | m_PPRO | m_K6;
-const int x86_use_any_reg = m_486;
-const int x86_cmove = m_PPRO;
-const int x86_deep_branch = m_PPRO| m_K6;
-
-#define AT_BP(mode) (gen_rtx_MEM ((mode), frame_pointer_rtx))
-
-extern FILE *asm_out_file;
-extern char *strcat ();
-
-static void ix86_epilogue PROTO((int));
-static void ix86_prologue PROTO((int));
-
-char *singlemove_string ();
-char *output_move_const_single ();
-char *output_fp_cc0_set ();
-
-char *hi_reg_name[] = HI_REGISTER_NAMES;
-char *qi_reg_name[] = QI_REGISTER_NAMES;
-char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
-
-/* Array of the smallest class containing reg number REGNO, indexed by
-   REGNO.  Used by REGNO_REG_CLASS in i386.h. */
-
-enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
-{
-  /* ax, dx, cx, bx */
-  AREG, DREG, CREG, BREG,
-  /* si, di, bp, sp */
-  SIREG, DIREG, INDEX_REGS, GENERAL_REGS,
-  /* FP registers */
-  FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
-  FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
-  /* arg pointer */
-  INDEX_REGS
-};
-
-/* Test and compare insns in i386.md store the information needed to
-   generate branch and scc insns here.  */
-
-struct rtx_def *i386_compare_op0 = NULL_RTX;
-struct rtx_def *i386_compare_op1 = NULL_RTX;
-struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
-
-/* which cpu are we scheduling for */
-enum processor_type ix86_cpu;
-
-/* which instruction set architecture to use.  */
-int ix86_arch;
-
-/* Strings to hold which cpu and instruction set architecture  to use.  */
-char *ix86_cpu_string;		/* for -mcpu=<xxx> */
-char *ix86_arch_string;		/* for -march=<xxx> */
-
-/* Register allocation order */
-char *i386_reg_alloc_order;
-static char regs_allocated[FIRST_PSEUDO_REGISTER];
-
-/* # of registers to use to pass arguments. */
-char *i386_regparm_string;
-
-/* i386_regparm_string as a number */
-int i386_regparm;
-
-/* Alignment to use for loops and jumps:  */
-
-/* Power of two alignment for loops. */
-char *i386_align_loops_string;
-
-/* Power of two alignment for non-loop jumps. */
-char *i386_align_jumps_string;
-
-/* Values 1-5: see jump.c */
-int i386_branch_cost;
-char *i386_branch_cost_string;
-
-/* Power of two alignment for functions. */
-int i386_align_funcs;
-char *i386_align_funcs_string;
-
-/* Power of two alignment for loops. */
-int i386_align_loops;
-
-/* Power of two alignment for non-loop jumps. */
-int i386_align_jumps;
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-
-void
-override_options ()
-{
-  int ch, i, j;
-  int def_align;
-
-  static struct ptt
-    {
-      char *name;		/* Canonical processor name.  */
-      enum processor_type processor; /* Processor type enum value.  */
-      struct processor_costs *cost; /* Processor costs */
-      int target_enable;	/* Target flags to enable.  */
-      int target_disable;	/* Target flags to disable.  */
-    } processor_target_table[]
-      = {{PROCESSOR_I386_STRING, PROCESSOR_I386, &i386_cost, 0, 0},
-	   {PROCESSOR_I486_STRING, PROCESSOR_I486, &i486_cost, 0, 0},
-	   {PROCESSOR_I586_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
-	   {PROCESSOR_PENTIUM_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
-	   {PROCESSOR_I686_STRING, PROCESSOR_PENTIUMPRO, &pentiumpro_cost,
-	      0, 0},
-	   {PROCESSOR_PENTIUMPRO_STRING, PROCESSOR_PENTIUMPRO,
-	      &pentiumpro_cost, 0, 0},
-      	   {PROCESSOR_K6_STRING, PROCESSOR_K6, &k6_cost, 0, 0}};
-
-  int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
-
-#ifdef SUBTARGET_OVERRIDE_OPTIONS
-  SUBTARGET_OVERRIDE_OPTIONS;
-#endif
-
-  /* Validate registers in register allocation order.  */
-  if (i386_reg_alloc_order)
-    {
-      for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
-	{
-	  int regno = 0;
-
-	  switch (ch)
-	    {
-	    case 'a':	regno = 0;	break;
-	    case 'd':	regno = 1;	break;
-	    case 'c':	regno = 2;	break;
-	    case 'b':	regno = 3;	break;
-	    case 'S':	regno = 4;	break;
-	    case 'D':	regno = 5;	break;
-	    case 'B':	regno = 6;	break;
-
-	    default:	fatal ("Register '%c' is unknown", ch);
-	    }
-
-	  if (regs_allocated[regno])
-	    fatal ("Register '%c' already specified in allocation order", ch);
-
-	  regs_allocated[regno] = 1;
-	}
-    }
-
-  if (ix86_arch_string == 0)
-    {
-      ix86_arch_string = PROCESSOR_PENTIUM_STRING;
-      if (ix86_cpu_string == 0)
-	ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
-    }
-
-  for (i = 0; i < ptt_size; i++)
-    if (! strcmp (ix86_arch_string, processor_target_table[i].name))
-      {
-	ix86_arch = processor_target_table[i].processor;
-	if (ix86_cpu_string == 0)
-	  ix86_cpu_string = processor_target_table[i].name;
-	break;
-      }
-
-  if (i == ptt_size)
-    {
-      error ("bad value (%s) for -march= switch", ix86_arch_string);
-      ix86_arch_string = PROCESSOR_PENTIUM_STRING;
-      ix86_arch = PROCESSOR_DEFAULT;
-    }
-
-  if (ix86_cpu_string == 0)
-    ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
-
-  for (j = 0; j < ptt_size; j++)
-    if (! strcmp (ix86_cpu_string, processor_target_table[j].name))
-      {
-	ix86_cpu = processor_target_table[j].processor;
-	ix86_cost = processor_target_table[j].cost;
-	if (i > j && (int) ix86_arch >= (int) PROCESSOR_K6)
-	  error ("-mcpu=%s does not support -march=%s",
-		 ix86_cpu_string, ix86_arch_string);
-
-	target_flags |= processor_target_table[j].target_enable;
-	target_flags &= ~processor_target_table[j].target_disable;
-	break;
-      }
-
-  if (j == ptt_size)
-    {
-      error ("bad value (%s) for -mcpu= switch", ix86_cpu_string);
-      ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
-      ix86_cpu = PROCESSOR_DEFAULT;
-    }
-
-  /* Validate -mregparm= value. */
-  if (i386_regparm_string)
-    {
-      i386_regparm = atoi (i386_regparm_string);
-      if (i386_regparm < 0 || i386_regparm > REGPARM_MAX)
-	fatal ("-mregparm=%d is not between 0 and %d",
-	       i386_regparm, REGPARM_MAX);
-    }
-
-  /* The 486 suffers more from non-aligned cache line fills, and the
-     larger code size results in a larger cache foot-print and more misses.
-     The 486 has a 16 byte cache line, pentium and pentiumpro have a 32 byte
-     cache line.  */
-  def_align = (TARGET_486) ? 4 : 2;
-
-  /* Validate -malign-loops= value, or provide default.  */
-  if (i386_align_loops_string)
-    {
-      i386_align_loops = atoi (i386_align_loops_string);
-      if (i386_align_loops < 0 || i386_align_loops > MAX_CODE_ALIGN)
-	fatal ("-malign-loops=%d is not between 0 and %d",
-	       i386_align_loops, MAX_CODE_ALIGN);
-    }
-  else
-#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
-    i386_align_loops = 4;
-#else
-    i386_align_loops = 2;
-#endif
-
-  /* Validate -malign-jumps= value, or provide default.  */
-  if (i386_align_jumps_string)
-    {
-      i386_align_jumps = atoi (i386_align_jumps_string);
-      if (i386_align_jumps < 0 || i386_align_jumps > MAX_CODE_ALIGN)
-	fatal ("-malign-jumps=%d is not between 0 and %d",
-	       i386_align_jumps, MAX_CODE_ALIGN);
-    }
-  else
-#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
-    i386_align_jumps = 4;
-#else
-    i386_align_jumps = def_align;
-#endif
-
-  /* Validate -malign-functions= value, or provide default. */
-  if (i386_align_funcs_string)
-    {
-      i386_align_funcs = atoi (i386_align_funcs_string);
-      if (i386_align_funcs < 0 || i386_align_funcs > MAX_CODE_ALIGN)
-	fatal ("-malign-functions=%d is not between 0 and %d",
-	       i386_align_funcs, MAX_CODE_ALIGN);
-    }
-  else
-    i386_align_funcs = def_align;
-
-  /* Validate -mbranch-cost= value, or provide default. */
-  if (i386_branch_cost_string)
-    {
-      i386_branch_cost = atoi (i386_branch_cost_string);
-      if (i386_branch_cost < 0 || i386_branch_cost > 5)
-	fatal ("-mbranch-cost=%d is not between 0 and 5",
-	       i386_branch_cost);
-    }
-  else
-    i386_branch_cost = 1;
-
-  /* Keep nonleaf frame pointers.  */
-  if (TARGET_OMIT_LEAF_FRAME_POINTER)
-    flag_omit_frame_pointer = 1;
-}
-
-/* A C statement (sans semicolon) to choose the order in which to
-   allocate hard registers for pseudo-registers local to a basic
-   block.
-
-   Store the desired register order in the array `reg_alloc_order'.
-   Element 0 should be the register to allocate first; element 1, the
-   next register; and so on.
-
-   The macro body should not assume anything about the contents of
-   `reg_alloc_order' before execution of the macro.
-
-   On most machines, it is not necessary to define this macro.  */
-
-void
-order_regs_for_local_alloc ()
-{
-  int i, ch, order;
-
-  /* User specified the register allocation order.  */
-
-  if (i386_reg_alloc_order)
-    {
-      for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
-	{
-	  int regno = 0;
-
-	  switch (ch)
-	    {
-	    case 'a':	regno = 0;	break;
-	    case 'd':	regno = 1;	break;
-	    case 'c':	regno = 2;	break;
-	    case 'b':	regno = 3;	break;
-	    case 'S':	regno = 4;	break;
-	    case 'D':	regno = 5;	break;
-	    case 'B':	regno = 6;	break;
-	    }
-
-	  reg_alloc_order[order++] = regno;
-	}
-
-      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	{
-	  if (! regs_allocated[i])
-	    reg_alloc_order[order++] = i;
-	}
-    }
-
-  /* If user did not specify a register allocation order, use natural order. */
-  else
-    {
-      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	reg_alloc_order[i] = i;
-    }
-}
-
-void
-optimization_options (level, size)
-     int level;
-     int size ATTRIBUTE_UNUSED;
-{
-  /* For -O2 and beyond, turn off -fschedule-insns by default.  It tends to
-     make the problem with not enough registers even worse.  */
-#ifdef INSN_SCHEDULING
-  if (level > 1)
-    flag_schedule_insns = 0;
-#endif
-}
-
-/* Sign-extend a 16-bit constant */
-
-struct rtx_def *
-i386_sext16_if_const (op)
-     struct rtx_def *op;
-{
-  if (GET_CODE (op) == CONST_INT)
-    {
-      HOST_WIDE_INT val = INTVAL (op);
-      HOST_WIDE_INT sext_val;
-      if (val & 0x8000)
-	sext_val = val | ~0xffff;
-      else
-	sext_val = val & 0xffff;
-      if (sext_val != val)
-	op = GEN_INT (sext_val);
-    }
-  return op;
-}
-
-/* Return nonzero if the rtx is aligned */
-
-static int
-i386_aligned_reg_p (regno)
-     int regno;
-{
-  return (regno == STACK_POINTER_REGNUM
-	  || (! flag_omit_frame_pointer && regno == FRAME_POINTER_REGNUM));
-}
-
-int
-i386_aligned_p (op)
-     rtx op;
-{
-  /* Registers and immediate operands are always "aligned". */
-  if (GET_CODE (op) != MEM)
-    return 1;
-
-  /* Don't even try to do any aligned optimizations with volatiles. */
-  if (MEM_VOLATILE_P (op))
-    return 0;
-
-  /* Get address of memory operand. */
-  op = XEXP (op, 0);
-
-  switch (GET_CODE (op))
-    {
-    case CONST_INT:
-      if (INTVAL (op) & 3)
-	break;
-      return 1;
-
-      /* Match "reg + offset" */
-    case PLUS:
-      if (GET_CODE (XEXP (op, 1)) != CONST_INT)
-	break;
-      if (INTVAL (XEXP (op, 1)) & 3)
-	break;
-
-      op = XEXP (op, 0);
-      if (GET_CODE (op) != REG)
-	break;
-
-      /* ... fall through ... */
-
-    case REG:
-      return i386_aligned_reg_p (REGNO (op));
-
-    default:
-      break;
-    }
-
-  return 0;
-}
-
-/* Return nonzero if INSN looks like it won't compute useful cc bits
-   as a side effect.  This information is only a hint. */
-
-int
-i386_cc_probably_useless_p (insn)
-     rtx insn;
-{
-  return ! next_cc0_user (insn);
-}
-
-/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
-   attribute for DECL.  The attributes in ATTRIBUTES have previously been
-   assigned to DECL.  */
-
-int
-i386_valid_decl_attribute_p (decl, attributes, identifier, args)
-     tree decl ATTRIBUTE_UNUSED;
-     tree attributes ATTRIBUTE_UNUSED;
-     tree identifier ATTRIBUTE_UNUSED;
-     tree args ATTRIBUTE_UNUSED;
-{
-  return 0;
-}
-
-/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
-   attribute for TYPE.  The attributes in ATTRIBUTES have previously been
-   assigned to TYPE.  */
-
-int
-i386_valid_type_attribute_p (type, attributes, identifier, args)
-     tree type;
-     tree attributes ATTRIBUTE_UNUSED;
-     tree identifier;
-     tree args;
-{
-  if (TREE_CODE (type) != FUNCTION_TYPE
-      && TREE_CODE (type) != METHOD_TYPE
-      && TREE_CODE (type) != FIELD_DECL
-      && TREE_CODE (type) != TYPE_DECL)
-    return 0;
-
-  /* Stdcall attribute says callee is responsible for popping arguments
-     if they are not variable.  */
-  if (is_attribute_p ("stdcall", identifier))
-    return (args == NULL_TREE);
-
-  /* Cdecl attribute says the callee is a normal C declaration. */
-  if (is_attribute_p ("cdecl", identifier))
-    return (args == NULL_TREE);
-
-  /* Regparm attribute specifies how many integer arguments are to be
-     passed in registers. */
-  if (is_attribute_p ("regparm", identifier))
-    {
-      tree cst;
-
-      if (! args || TREE_CODE (args) != TREE_LIST
-	  || TREE_CHAIN (args) != NULL_TREE
-	  || TREE_VALUE (args) == NULL_TREE)
-	return 0;
-
-      cst = TREE_VALUE (args);
-      if (TREE_CODE (cst) != INTEGER_CST)
-	return 0;
-
-      if (TREE_INT_CST_HIGH (cst) != 0
-	  || TREE_INT_CST_LOW (cst) < 0
-	  || TREE_INT_CST_LOW (cst) > REGPARM_MAX)
-	return 0;
-
-      return 1;
-    }
-
-  return 0;
-}
-
-/* Return 0 if the attributes for two types are incompatible, 1 if they
-   are compatible, and 2 if they are nearly compatible (which causes a
-   warning to be generated).  */
-
-int
-i386_comp_type_attributes (type1, type2)
-     tree type1;
-     tree type2;
-{
-  /* Check for mismatch of non-default calling convention. */
-  char *rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
-
-  if (TREE_CODE (type1) != FUNCTION_TYPE)
-    return 1;
-
-  /* Check for mismatched return types (cdecl vs stdcall).  */
-  if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
-      != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
-    return 0;
-  return 1;
-}
-
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.
-
-   On the 80386, the RTD insn may be used to pop them if the number
-     of args is fixed, but if the number is variable then the caller
-     must pop them all.  RTD can't be used for library calls now
-     because the library is compiled with the Unix compiler.
-   Use of RTD is a selectable option, since it is incompatible with
-   standard Unix calling sequences.  If the option is not selected,
-   the caller must always pop the args.
-
-   The attribute stdcall is equivalent to RTD on a per module basis.  */
-
-int
-i386_return_pops_args (fundecl, funtype, size)
-     tree fundecl;
-     tree funtype;
-     int size;
-{
-  int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
-
-    /* Cdecl functions override -mrtd, and never pop the stack. */
-  if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
-
-    /* Stdcall functions will pop the stack if not variable args. */
-    if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype)))
-      rtd = 1;
-
-    if (rtd
-        && (TYPE_ARG_TYPES (funtype) == NULL_TREE
-	    || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
-		== void_type_node)))
-      return size;
-  }
-
-  /* Lose any fake structure return argument.  */
-  if (aggregate_value_p (TREE_TYPE (funtype)))
-    return GET_MODE_SIZE (Pmode);
-
-    return 0;
-}
-
-
-/* Argument support functions.  */
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-
-void
-init_cumulative_args (cum, fntype, libname)
-     CUMULATIVE_ARGS *cum;	/* Argument info to initialize */
-     tree fntype;		/* tree ptr for function decl */
-     rtx libname;		/* SYMBOL_REF of library name or 0 */
-{
-  static CUMULATIVE_ARGS zero_cum;
-  tree param, next_param;
-
-  if (TARGET_DEBUG_ARG)
-    {
-      fprintf (stderr, "\ninit_cumulative_args (");
-      if (fntype)
-	fprintf (stderr, "fntype code = %s, ret code = %s",
-		 tree_code_name[(int) TREE_CODE (fntype)],
-		 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
-      else
-	fprintf (stderr, "no fntype");
-
-      if (libname)
-	fprintf (stderr, ", libname = %s", XSTR (libname, 0));
-    }
-
-  *cum = zero_cum;
-
-  /* Set up the number of registers to use for passing arguments.  */
-  cum->nregs = i386_regparm;
-  if (fntype)
-    {
-      tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype));
-
-      if (attr)
-	cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
-    }
-
-  /* Determine if this function has variable arguments.  This is
-     indicated by the last argument being 'void_type_mode' if there
-     are no variable arguments.  If there are variable arguments, then
-     we won't pass anything in registers */
-
-  if (cum->nregs)
-    {
-      for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
-	   param != 0; param = next_param)
-	{
-	  next_param = TREE_CHAIN (param);
-	  if (next_param == 0 && TREE_VALUE (param) != void_type_node)
-	    cum->nregs = 0;
-	}
-    }
-
-  if (TARGET_DEBUG_ARG)
-    fprintf (stderr, ", nregs=%d )\n", cum->nregs);
-
-  return;
-}
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-void
-function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;	/* current arg information */
-     enum machine_mode mode;	/* current arg mode */
-     tree type;			/* type of the argument or 0 if lib support */
-     int named;			/* whether or not the argument was named */
-{
-  int bytes
-    = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
-  int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-
-  if (TARGET_DEBUG_ARG)
-    fprintf (stderr,
-	     "function_adv (sz=%d, wds=%2d, nregs=%d, mode=%s, named=%d)\n\n",
-	     words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
-
-  cum->words += words;
-  cum->nregs -= words;
-  cum->regno += words;
-
-  if (cum->nregs <= 0)
-    {
-      cum->nregs = 0;
-      cum->regno = 0;
-    }
-
-  return;
-}
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-struct rtx_def *
-function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;	/* current arg information */
-     enum machine_mode mode;	/* current arg mode */
-     tree type;			/* type of the argument or 0 if lib support */
-     int named;			/* != 0 for normal args, == 0 for ... args */
-{
-  rtx ret   = NULL_RTX;
-  int bytes
-    = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
-  int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-
-  switch (mode)
-    {
-      /* For now, pass fp/complex values on the stack. */
-    default:
-      break;
-
-    case BLKmode:
-    case DImode:
-    case SImode:
-    case HImode:
-    case QImode:
-      if (words <= cum->nregs)
-	ret = gen_rtx_REG (mode, cum->regno);
-      break;
-    }
-
-  if (TARGET_DEBUG_ARG)
-    {
-      fprintf (stderr,
-	       "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d",
-	       words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
-
-      if (ret)
-	fprintf (stderr, ", reg=%%e%s", reg_names[ REGNO(ret) ]);
-      else
-	fprintf (stderr, ", stack");
-
-      fprintf (stderr, " )\n");
-    }
-
-  return ret;
-}
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-int
-function_arg_partial_nregs (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;	/* current arg information */
-     enum machine_mode mode ATTRIBUTE_UNUSED;	/* current arg mode */
-     tree type ATTRIBUTE_UNUSED;		/* type of the argument or 0 if lib support */
-     int named ATTRIBUTE_UNUSED;		/* != 0 for normal args, == 0 for ... args */
-{
-  return 0;
-}
-
-/* Output an insn whose source is a 386 integer register.  SRC is the
-   rtx for the register, and TEMPLATE is the op-code template.  SRC may
-   be either SImode or DImode.
-
-   The template will be output with operands[0] as SRC, and operands[1]
-   as a pointer to the top of the 386 stack.  So a call from floatsidf2
-   would look like this:
-
-      output_op_from_reg (operands[1], AS1 (fild%z0,%1));
-
-   where %z0 corresponds to the caller's operands[1], and is used to
-   emit the proper size suffix.
-
-   ??? Extend this to handle HImode - a 387 can load and store HImode
-   values directly. */
-
-void
-output_op_from_reg (src, template)
-     rtx src;
-     char *template;
-{
-  rtx xops[4];
-  int size = GET_MODE_SIZE (GET_MODE (src));
-
-  xops[0] = src;
-  xops[1] = AT_SP (Pmode);
-  xops[2] = GEN_INT (size);
-  xops[3] = stack_pointer_rtx;
-
-  if (size > UNITS_PER_WORD)
-    {
-      rtx high;
-
-      if (size > 2 * UNITS_PER_WORD)
-	{
-	  high = gen_rtx_REG (SImode, REGNO (src) + 2);
-	  output_asm_insn (AS1 (push%L0,%0), &high);
-	}
-
-      high = gen_rtx_REG (SImode, REGNO (src) + 1);
-      output_asm_insn (AS1 (push%L0,%0), &high);
-    }
-
-  output_asm_insn (AS1 (push%L0,%0), &src);
-  output_asm_insn (template, xops);
-  output_asm_insn (AS2 (add%L3,%2,%3), xops);
-}
-
-/* Output an insn to pop an value from the 387 top-of-stack to 386
-   register DEST. The 387 register stack is popped if DIES is true.  If
-   the mode of DEST is an integer mode, a `fist' integer store is done,
-   otherwise a `fst' float store is done. */
-
-void
-output_to_reg (dest, dies, scratch_mem)
-     rtx dest;
-     int dies;
-     rtx scratch_mem;
-{
-  rtx xops[4];
-  int size = GET_MODE_SIZE (GET_MODE (dest));
-
-  if (! scratch_mem)
-    xops[0] = AT_SP (Pmode);
-  else
-    xops[0] = scratch_mem;
-
-  xops[1] = stack_pointer_rtx;
-  xops[2] = GEN_INT (size);
-  xops[3] = dest;
-
-  if (! scratch_mem)
-    output_asm_insn (AS2 (sub%L1,%2,%1), xops);
-
-  if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT)
-    {
-      if (dies)
-	output_asm_insn (AS1 (fistp%z3,%y0), xops);
-      else if (GET_MODE (xops[3]) == DImode && ! dies)
-	{
-	  /* There is no DImode version of this without a stack pop, so
-	     we must emulate it.  It doesn't matter much what the second
-	     instruction is, because the value being pushed on the FP stack
-	     is not used except for the following stack popping store.
-	     This case can only happen without optimization, so it doesn't
-	     matter that it is inefficient.  */
-	  output_asm_insn (AS1 (fistp%z3,%0), xops);
-	  output_asm_insn (AS1 (fild%z3,%0), xops);
-	}
-      else
-	output_asm_insn (AS1 (fist%z3,%y0), xops);
-    }
-
-  else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT)
-    {
-      if (dies)
-	output_asm_insn (AS1 (fstp%z3,%y0), xops);
-      else
-	{
-	  if (GET_MODE (dest) == XFmode)
-	    {
-	      output_asm_insn (AS1 (fstp%z3,%y0), xops);
-	      output_asm_insn (AS1 (fld%z3,%y0), xops);
-	    }
-	  else
-	    output_asm_insn (AS1 (fst%z3,%y0), xops);
-	}
-    }
-
-  else
-    abort ();
-
-  if (! scratch_mem)
-    output_asm_insn (AS1 (pop%L0,%0), &dest);
-  else
-    output_asm_insn (AS2 (mov%L0,%0,%3), xops);
-
-
-  if (size > UNITS_PER_WORD)
-    {
-      dest = gen_rtx_REG (SImode, REGNO (dest) + 1);
-      if (! scratch_mem)
-	output_asm_insn (AS1 (pop%L0,%0), &dest);
-      else
-	{
-	  xops[0] = adj_offsettable_operand (xops[0], 4);
-	  xops[3] = dest;
-	  output_asm_insn (AS2 (mov%L0,%0,%3), xops);
-	}
-
-      if (size > 2 * UNITS_PER_WORD)
-	{
-	  dest = gen_rtx_REG (SImode, REGNO (dest) + 1);
-	  if (! scratch_mem)
-	    output_asm_insn (AS1 (pop%L0,%0), &dest);
-	  else
-	    {
-	      xops[0] = adj_offsettable_operand (xops[0], 4);
-	      output_asm_insn (AS2 (mov%L0,%0,%3), xops);
-	    }
-	}
-    }
-}
-
-char *
-singlemove_string (operands)
-     rtx *operands;
-{
-  rtx x;
-  if (GET_CODE (operands[0]) == MEM
-      && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC)
-    {
-      if (XEXP (x, 0) != stack_pointer_rtx)
-	abort ();
-      return "push%L1 %1";
-    }
-  else if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    return output_move_const_single (operands);
-  else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)
-    return AS2 (mov%L0,%1,%0);
-  else if (CONSTANT_P (operands[1]))
-    return AS2 (mov%L0,%1,%0);
-  else
-    {
-      output_asm_insn ("push%L1 %1", operands);
-      return "pop%L0 %0";
-    }
-}
-
-/* Return a REG that occurs in ADDR with coefficient 1.
-   ADDR can be effectively incremented by incrementing REG.  */
-
-static rtx
-find_addr_reg (addr)
-     rtx addr;
-{
-  while (GET_CODE (addr) == PLUS)
-    {
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-	addr = XEXP (addr, 0);
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	addr = XEXP (addr, 1);
-      else if (CONSTANT_P (XEXP (addr, 0)))
-	addr = XEXP (addr, 1);
-      else if (CONSTANT_P (XEXP (addr, 1)))
-	addr = XEXP (addr, 0);
-      else
-	abort ();
-    }
-
-  if (GET_CODE (addr) == REG)
-    return addr;
-  abort ();
-}
-
-/* Output an insn to add the constant N to the register X.  */
-
-static void
-asm_add (n, x)
-     int n;
-     rtx x;
-{
-  rtx xops[2];
-  xops[0] = x;
-
-  if (n == -1)
-    output_asm_insn (AS1 (dec%L0,%0), xops);
-  else if (n == 1)
-    output_asm_insn (AS1 (inc%L0,%0), xops);
-  else if (n < 0 || n == 128)
-    {
-      xops[1] = GEN_INT (-n);
-      output_asm_insn (AS2 (sub%L0,%1,%0), xops);
-    }
-  else if (n > 0)
-    {
-      xops[1] = GEN_INT (n);
-      output_asm_insn (AS2 (add%L0,%1,%0), xops);
-    }
-}
-
-/* Output assembler code to perform a doubleword move insn
-   with operands OPERANDS.  */
-
-char *
-output_move_double (operands)
-     rtx *operands;
-{
-  enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
-  rtx latehalf[2];
-  rtx middlehalf[2];
-  rtx xops[2];
-  rtx addreg0 = 0, addreg1 = 0;
-  int dest_overlapped_low = 0;
-  int size = GET_MODE_SIZE (GET_MODE (operands[0]));
-
-  middlehalf[0] = 0;
-  middlehalf[1] = 0;
-
-  /* First classify both operands.  */
-
-  if (REG_P (operands[0]))
-    optype0 = REGOP;
-  else if (offsettable_memref_p (operands[0]))
-    optype0 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    optype0 = POPOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    optype0 = PUSHOP;
-  else if (GET_CODE (operands[0]) == MEM)
-    optype0 = MEMOP;
-  else
-    optype0 = RNDOP;
-
-  if (REG_P (operands[1]))
-    optype1 = REGOP;
-  else if (CONSTANT_P (operands[1]))
-    optype1 = CNSTOP;
-  else if (offsettable_memref_p (operands[1]))
-    optype1 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
-    optype1 = POPOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
-    optype1 = PUSHOP;
-  else if (GET_CODE (operands[1]) == MEM)
-    optype1 = MEMOP;
-  else
-    optype1 = RNDOP;
-
-  /* Check for the cases that the operand constraints are not
-     supposed to allow to happen.  Abort if we get one,
-     because generating code for these cases is painful.  */
-
-  if (optype0 == RNDOP || optype1 == RNDOP)
-    abort ();
-
-  /* If one operand is decrementing and one is incrementing
-     decrement the former register explicitly
-     and change that operand into ordinary indexing.  */
-
-  if (optype0 == PUSHOP && optype1 == POPOP)
-    {
-      /* ??? Can this ever happen on i386? */
-      operands[0] = XEXP (XEXP (operands[0], 0), 0);
-      asm_add (-size, operands[0]);
-      if (GET_MODE (operands[1]) == XFmode)
-        operands[0] = gen_rtx_MEM (XFmode, operands[0]);
-      else if (GET_MODE (operands[0]) == DFmode)
-        operands[0] = gen_rtx_MEM (DFmode, operands[0]);
-      else
-        operands[0] = gen_rtx_MEM (DImode, operands[0]);
-      optype0 = OFFSOP;
-    }
-
-  if (optype0 == POPOP && optype1 == PUSHOP)
-    {
-      /* ??? Can this ever happen on i386? */
-      operands[1] = XEXP (XEXP (operands[1], 0), 0);
-      asm_add (-size, operands[1]);
-      if (GET_MODE (operands[1]) == XFmode)
-        operands[1] = gen_rtx_MEM (XFmode, operands[1]);
-      else if (GET_MODE (operands[1]) == DFmode)
-        operands[1] = gen_rtx_MEM (DFmode, operands[1]);
-      else
-        operands[1] = gen_rtx_MEM (DImode, operands[1]);
-      optype1 = OFFSOP;
-    }
-
-  /* If an operand is an unoffsettable memory ref, find a register
-     we can increment temporarily to make it refer to the second word.  */
-
-  if (optype0 == MEMOP)
-    addreg0 = find_addr_reg (XEXP (operands[0], 0));
-
-  if (optype1 == MEMOP)
-    addreg1 = find_addr_reg (XEXP (operands[1], 0));
-
-  /* Ok, we can do one word at a time.
-     Normally we do the low-numbered word first,
-     but if either operand is autodecrementing then we
-     do the high-numbered word first.
-
-     In either case, set up in LATEHALF the operands to use
-     for the high-numbered word and in some cases alter the
-     operands in OPERANDS to be suitable for the low-numbered word.  */
-
-  if (size == 12)
-    {
-      if (optype0 == REGOP)
-	{
-	  middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-	  latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
-	}
-      else if (optype0 == OFFSOP)
-	{
-	  middlehalf[0] = adj_offsettable_operand (operands[0], 4);
-	  latehalf[0] = adj_offsettable_operand (operands[0], 8);
-	}
-      else
-	{
-         middlehalf[0] = operands[0];
-         latehalf[0] = operands[0];
-	}
-
-      if (optype1 == REGOP)
-	{
-          middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-          latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
-	}
-      else if (optype1 == OFFSOP)
-	{
-          middlehalf[1] = adj_offsettable_operand (operands[1], 4);
-          latehalf[1] = adj_offsettable_operand (operands[1], 8);
-	}
-      else if (optype1 == CNSTOP)
-	{
-	  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	    {
-	      REAL_VALUE_TYPE r; long l[3];
-
-	      REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
-	      REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
-	      operands[1] = GEN_INT (l[0]);
-	      middlehalf[1] = GEN_INT (l[1]);
-	      latehalf[1] = GEN_INT (l[2]);
-	    }
-	  else if (CONSTANT_P (operands[1]))
-	    /* No non-CONST_DOUBLE constant should ever appear here.  */
-	    abort ();
-        }
-      else
-	{
-	  middlehalf[1] = operands[1];
-	  latehalf[1] = operands[1];
-	}
-    }
-
-  else
-    {
-      /* Size is not 12. */
-
-      if (optype0 == REGOP)
-	latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-      else if (optype0 == OFFSOP)
-	latehalf[0] = adj_offsettable_operand (operands[0], 4);
-      else
-	latehalf[0] = operands[0];
-
-      if (optype1 == REGOP)
-	latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-      else if (optype1 == OFFSOP)
-	latehalf[1] = adj_offsettable_operand (operands[1], 4);
-      else if (optype1 == CNSTOP)
-	split_double (operands[1], &operands[1], &latehalf[1]);
-      else
-	latehalf[1] = operands[1];
-    }
-
-  /* If insn is effectively movd N (sp),-(sp) then we will do the
-     high word first.  We should use the adjusted operand 1
-     (which is N+4 (sp) or N+8 (sp))
-     for the low word and middle word as well,
-     to compensate for the first decrement of sp.  */
-  if (optype0 == PUSHOP
-      && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
-      && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
-    middlehalf[1] = operands[1] = latehalf[1];
-
-  /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
-     if the upper part of reg N does not appear in the MEM, arrange to
-     emit the move late-half first.  Otherwise, compute the MEM address
-     into the upper part of N and use that as a pointer to the memory
-     operand.  */
-  if (optype0 == REGOP
-      && (optype1 == OFFSOP || optype1 == MEMOP))
-    {
-      if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
-	  && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
-	{
-	  /* If both halves of dest are used in the src memory address,
-	     compute the address into latehalf of dest.  */
-	compadr:
-	  xops[0] = latehalf[0];
-	  xops[1] = XEXP (operands[1], 0);
-	  output_asm_insn (AS2 (lea%L0,%a1,%0), xops);
-	  if (GET_MODE (operands[1]) == XFmode)
-	    {
-	      operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
-	      middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
-	      latehalf[1] = adj_offsettable_operand (operands[1], size-4);
-	    }
-	  else
-	    {
-	      operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
-	      latehalf[1] = adj_offsettable_operand (operands[1], size-4);
-	    }
-	}
-
-      else if (size == 12
-		 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0)))
-	{
-	  /* Check for two regs used by both source and dest. */
-	  if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
-		|| reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
-	    goto compadr;
-
-	  /* JRV says this can't happen: */
-	  if (addreg0 || addreg1)
-	      abort ();
-
-	  /* Only the middle reg conflicts; simply put it last. */
-	  output_asm_insn (singlemove_string (operands), operands);
-	  output_asm_insn (singlemove_string (latehalf), latehalf);
-	  output_asm_insn (singlemove_string (middlehalf), middlehalf);
-	  return "";
-	}
-
-      else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
-	/* If the low half of dest is mentioned in the source memory
-	   address, the arrange to emit the move late half first.  */
-	dest_overlapped_low = 1;
-    }
-
-  /* If one or both operands autodecrementing,
-     do the two words, high-numbered first.  */
-
-  /* Likewise,  the first move would clobber the source of the second one,
-     do them in the other order.  This happens only for registers;
-     such overlap can't happen in memory unless the user explicitly
-     sets it up, and that is an undefined circumstance.  */
-
-#if 0
-  if (optype0 == PUSHOP || optype1 == PUSHOP
-      || (optype0 == REGOP && optype1 == REGOP
-	  && REGNO (operands[0]) == REGNO (latehalf[1]))
-      || dest_overlapped_low)
-#endif
-
-  if (optype0 == PUSHOP || optype1 == PUSHOP
-      || (optype0 == REGOP && optype1 == REGOP
-	  && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
-	      || REGNO (operands[0]) == REGNO (latehalf[1])))
-      || dest_overlapped_low)
-    {
-      /* Make any unoffsettable addresses point at high-numbered word.  */
-      if (addreg0)
-	asm_add (size-4, addreg0);
-      if (addreg1)
-	asm_add (size-4, addreg1);
-
-      /* Do that word.  */
-      output_asm_insn (singlemove_string (latehalf), latehalf);
-
-      /* Undo the adds we just did.  */
-      if (addreg0)
-	asm_add (-4, addreg0);
-      if (addreg1)
-	asm_add (-4, addreg1);
-
-      if (size == 12)
-        {
-	  output_asm_insn (singlemove_string (middlehalf), middlehalf);
-	  if (addreg0)
-	    asm_add (-4, addreg0);
-	  if (addreg1)
-	    asm_add (-4, addreg1);
-	}
-
-      /* Do low-numbered word.  */
-      return singlemove_string (operands);
-    }
-
-  /* Normal case: do the two words, low-numbered first.  */
-
-  output_asm_insn (singlemove_string (operands), operands);
-
-  /* Do the middle one of the three words for long double */
-  if (size == 12)
-    {
-      if (addreg0)
-        asm_add (4, addreg0);
-      if (addreg1)
-        asm_add (4, addreg1);
-
-      output_asm_insn (singlemove_string (middlehalf), middlehalf);
-    }
-
-  /* Make any unoffsettable addresses point at high-numbered word.  */
-  if (addreg0)
-    asm_add (4, addreg0);
-  if (addreg1)
-    asm_add (4, addreg1);
-
-  /* Do that word.  */
-  output_asm_insn (singlemove_string (latehalf), latehalf);
-
-  /* Undo the adds we just did.  */
-  if (addreg0)
-    asm_add (4-size, addreg0);
-  if (addreg1)
-    asm_add (4-size, addreg1);
-
-  return "";
-}
-
-#define MAX_TMPS 2		/* max temporary registers used */
-
-/* Output the appropriate code to move push memory on the stack */
-
-char *
-output_move_pushmem (operands, insn, length, tmp_start, n_operands)
-     rtx operands[];
-     rtx insn;
-     int length;
-     int tmp_start;
-     int n_operands;
-{
-  struct
-    {
-      char *load;
-      char *push;
-      rtx   xops[2];
-    } tmp_info[MAX_TMPS];
-
-  rtx src = operands[1];
-  int max_tmps = 0;
-  int offset = 0;
-  int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src);
-  int stack_offset = 0;
-  int i, num_tmps;
-  rtx xops[1];
-
-  if (! offsettable_memref_p (src))
-    fatal_insn ("Source is not offsettable", insn);
-
-  if ((length & 3) != 0)
-    fatal_insn ("Pushing non-word aligned size", insn);
-
-  /* Figure out which temporary registers we have available */
-  for (i = tmp_start; i < n_operands; i++)
-    {
-      if (GET_CODE (operands[i]) == REG)
-	{
-	  if (reg_overlap_mentioned_p (operands[i], src))
-	    continue;
-
-	  tmp_info[ max_tmps++ ].xops[1] = operands[i];
-	  if (max_tmps == MAX_TMPS)
-	    break;
-	}
-    }
-
-  if (max_tmps == 0)
-    for (offset = length - 4; offset >= 0; offset -= 4)
-      {
-	xops[0] = adj_offsettable_operand (src, offset + stack_offset);
-	output_asm_insn (AS1(push%L0,%0), xops);
-	if (stack_p)
-	  stack_offset += 4;
-      }
-
-  else
-    for (offset = length - 4; offset >= 0; )
-      {
-	for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++)
-	  {
-	    tmp_info[num_tmps].load    = AS2(mov%L0,%0,%1);
-	    tmp_info[num_tmps].push    = AS1(push%L0,%1);
-	    tmp_info[num_tmps].xops[0]
-	      = adj_offsettable_operand (src, offset + stack_offset);
-	    offset -= 4;
-	  }
-
-	for (i = 0; i < num_tmps; i++)
-	  output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
-
-	for (i = 0; i < num_tmps; i++)
-	  output_asm_insn (tmp_info[i].push, tmp_info[i].xops);
-
-	if (stack_p)
-	  stack_offset += 4*num_tmps;
-      }
-
-  return "";
-}
-
-/* Output the appropriate code to move data between two memory locations */
-
-char *
-output_move_memory (operands, insn, length, tmp_start, n_operands)
-     rtx operands[];
-     rtx insn;
-     int length;
-     int tmp_start;
-     int n_operands;
-{
-  struct
-    {
-      char *load;
-      char *store;
-      rtx   xops[3];
-    } tmp_info[MAX_TMPS];
-
-  rtx dest = operands[0];
-  rtx src  = operands[1];
-  rtx qi_tmp = NULL_RTX;
-  int max_tmps = 0;
-  int offset = 0;
-  int i, num_tmps;
-  rtx xops[3];
-
-  if (GET_CODE (dest) == MEM
-      && GET_CODE (XEXP (dest, 0)) == PRE_INC
-      && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx)
-    return output_move_pushmem (operands, insn, length, tmp_start, n_operands);
-
-  if (! offsettable_memref_p (src))
-    fatal_insn ("Source is not offsettable", insn);
-
-  if (! offsettable_memref_p (dest))
-    fatal_insn ("Destination is not offsettable", insn);
-
-  /* Figure out which temporary registers we have available */
-  for (i = tmp_start; i < n_operands; i++)
-    {
-      if (GET_CODE (operands[i]) == REG)
-	{
-	  if ((length & 1) != 0 && qi_tmp == 0 && QI_REG_P (operands[i]))
-	    qi_tmp = operands[i];
-
-	  if (reg_overlap_mentioned_p (operands[i], dest))
-	    fatal_insn ("Temporary register overlaps the destination", insn);
-
-	  if (reg_overlap_mentioned_p (operands[i], src))
-	    fatal_insn ("Temporary register overlaps the source", insn);
-
-	  tmp_info[max_tmps++].xops[2] = operands[i];
-	  if (max_tmps == MAX_TMPS)
-	    break;
-	}
-    }
-
-  if (max_tmps == 0)
-    fatal_insn ("No scratch registers were found to do memory->memory moves",
-		insn);
-
-  if ((length & 1) != 0)
-    {
-      if (qi_tmp == 0)
-	fatal_insn ("No byte register found when moving odd # of bytes.",
-		    insn);
-    }
-
-  while (length > 1)
-    {
-      for (num_tmps = 0; num_tmps < max_tmps; num_tmps++)
-	{
-	  if (length >= 4)
-	    {
-	      tmp_info[num_tmps].load    = AS2(mov%L0,%1,%2);
-	      tmp_info[num_tmps].store   = AS2(mov%L0,%2,%0);
-	      tmp_info[num_tmps].xops[0]
-		= adj_offsettable_operand (dest, offset);
-	      tmp_info[num_tmps].xops[1]
-		= adj_offsettable_operand (src, offset);
-
-	      offset += 4;
-	      length -= 4;
-	    }
-
-	  else if (length >= 2)
-	    {
-	      tmp_info[num_tmps].load    = AS2(mov%W0,%1,%2);
-	      tmp_info[num_tmps].store   = AS2(mov%W0,%2,%0);
-	      tmp_info[num_tmps].xops[0]
-		= adj_offsettable_operand (dest, offset);
-	      tmp_info[num_tmps].xops[1]
-		= adj_offsettable_operand (src, offset);
-
-	      offset += 2;
-	      length -= 2;
-	    }
-	  else
-	    break;
-	}
-
-      for (i = 0; i < num_tmps; i++)
-	output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
-
-      for (i = 0; i < num_tmps; i++)
-	output_asm_insn (tmp_info[i].store, tmp_info[i].xops);
-    }
-
-  if (length == 1)
-    {
-      xops[0] = adj_offsettable_operand (dest, offset);
-      xops[1] = adj_offsettable_operand (src, offset);
-      xops[2] = qi_tmp;
-      output_asm_insn (AS2(mov%B0,%1,%2), xops);
-      output_asm_insn (AS2(mov%B0,%2,%0), xops);
-    }
-
-  return "";
-}
-
-int
-standard_80387_constant_p (x)
-     rtx x;
-{
-#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
-  REAL_VALUE_TYPE d;
-  jmp_buf handler;
-  int is0, is1;
-
-  if (setjmp (handler))
-    return 0;
-
-  set_float_handler (handler);
-  REAL_VALUE_FROM_CONST_DOUBLE (d, x);
-  is0 = REAL_VALUES_EQUAL (d, dconst0) && !REAL_VALUE_MINUS_ZERO (d);
-  is1 = REAL_VALUES_EQUAL (d, dconst1);
-  set_float_handler (NULL_PTR);
-
-  if (is0)
-    return 1;
-
-  if (is1)
-    return 2;
-
-  /* Note that on the 80387, other constants, such as pi,
-     are much slower to load as standard constants
-     than to load from doubles in memory!  */
-  /* ??? Not true on K6: all constants are equal cost.  */
-#endif
-
-  return 0;
-}
-
-char *
-output_move_const_single (operands)
-     rtx *operands;
-{
-  if (FP_REG_P (operands[0]))
-    {
-      int conval = standard_80387_constant_p (operands[1]);
-
-      if (conval == 1)
-	return "fldz";
-
-      if (conval == 2)
-	return "fld1";
-    }
-
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    {
-      REAL_VALUE_TYPE r; long l;
-
-      if (GET_MODE (operands[1]) == XFmode)
-	abort ();
-
-      REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
-      REAL_VALUE_TO_TARGET_SINGLE (r, l);
-      operands[1] = GEN_INT (l);
-    }
-
-  return singlemove_string (operands);
-}
-
-/* Returns 1 if OP is either a symbol reference or a sum of a symbol
-   reference and a constant.  */
-
-int
-symbolic_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return 1;
-
-    case CONST:
-      op = XEXP (op, 0);
-      return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
-	       || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-	      && GET_CODE (XEXP (op, 1)) == CONST_INT);
-
-    default:
-      return 0;
-    }
-}
-
-/* Test for a valid operand for a call instruction.
-   Don't allow the arg pointer register or virtual regs
-   since they may change into reg + const, which the patterns
-   can't handle yet.  */
-
-int
-call_insn_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) == MEM
-      && ((CONSTANT_ADDRESS_P (XEXP (op, 0))
-	   /* This makes a difference for PIC.  */
-	   && general_operand (XEXP (op, 0), Pmode))
-	  || (GET_CODE (XEXP (op, 0)) == REG
-	      && XEXP (op, 0) != arg_pointer_rtx
-	      && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
-		    && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
-    return 1;
-
-  return 0;
-}
-
-/* Like call_insn_operand but allow (mem (symbol_ref ...))
-   even if pic.  */
-
-int
-expander_call_insn_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) == MEM
-      && (CONSTANT_ADDRESS_P (XEXP (op, 0))
-	  || (GET_CODE (XEXP (op, 0)) == REG
-	      && XEXP (op, 0) != arg_pointer_rtx
-	      && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
-		    && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
-    return 1;
-
-  return 0;
-}
-
-/* Return 1 if OP is a comparison operator that can use the condition code
-   generated by an arithmetic operation. */
-
-int
-arithmetic_comparison_operator (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  enum rtx_code code;
-
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-
-  code = GET_CODE (op);
-  if (GET_RTX_CLASS (code) != '<')
-    return 0;
-
-  return (code != GT && code != LE);
-}
-
-int
-ix86_logical_operator (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return GET_CODE (op) == AND || GET_CODE (op) == IOR || GET_CODE (op) == XOR;
-}
-
-
-/* Returns 1 if OP contains a symbol reference */
-
-int
-symbolic_reference_mentioned_p (op)
-     rtx op;
-{
-  register char *fmt;
-  register int i;
-
-  if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
-    return 1;
-
-  fmt = GET_RTX_FORMAT (GET_CODE (op));
-  for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
-    {
-      if (fmt[i] == 'E')
-	{
-	  register int j;
-
-	  for (j = XVECLEN (op, i) - 1; j >= 0; j--)
-	    if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
-	      return 1;
-	}
-
-      else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
-	return 1;
-    }
-
-  return 0;
-}
-
-/* Attempt to expand a binary operator.  Make the expansion closer to the
-   actual machine, then just general_operand, which will allow 3 separate
-   memory references (one output, two input) in a single insn.  Return
-   whether the insn fails, or succeeds.  */
-
-int
-ix86_expand_binary_operator (code, mode, operands)
-     enum rtx_code code;
-     enum machine_mode mode;
-     rtx operands[];
-{
-  int modified;
-
-  /* Recognize <var1> = <value> <op> <var1> for commutative operators */
-  if (GET_RTX_CLASS (code) == 'c'
-      && (rtx_equal_p (operands[0], operands[2])
-	  || immediate_operand (operands[1], mode)))
-    {
-      rtx temp = operands[1];
-      operands[1] = operands[2];
-      operands[2] = temp;
-    }
-
-  /* If optimizing, copy to regs to improve CSE */
-  if (TARGET_PSEUDO && optimize
-      && ((reload_in_progress | reload_completed) == 0))
-    {
-      if (GET_CODE (operands[1]) == MEM
-	  && ! rtx_equal_p (operands[0], operands[1]))
-	operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
-
-      if (GET_CODE (operands[2]) == MEM)
-	operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
-
-      if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
-	{
-	  rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
-
-	  emit_move_insn (temp, operands[1]);
-	  operands[1] = temp;
-	  return TRUE;
-	}
-    }
-
-  if (!ix86_binary_operator_ok (code, mode, operands))
-    {
-      /* If not optimizing, try to make a valid insn (optimize code
-	 previously did this above to improve chances of CSE) */
-
-      if ((! TARGET_PSEUDO || !optimize)
-	  && ((reload_in_progress | reload_completed) == 0)
-	  && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM))
-	{
-	  modified = FALSE;
-	  if (GET_CODE (operands[1]) == MEM
-	      && ! rtx_equal_p (operands[0], operands[1]))
-	    {
-	      operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
-	      modified = TRUE;
-	    }
-
-	  if (GET_CODE (operands[2]) == MEM)
-	    {
-	      operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
-	      modified = TRUE;
-	    }
-
-	  if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
-	    {
-	      rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
-
-	      emit_move_insn (temp, operands[1]);
-	      operands[1] = temp;
-	      return TRUE;
-	    }
-
-	  if (modified && ! ix86_binary_operator_ok (code, mode, operands))
-	    return FALSE;
-	}
-      else
-	return FALSE;
-    }
-
-  return TRUE;
-}
-
-/* Return TRUE or FALSE depending on whether the binary operator meets the
-   appropriate constraints.  */
-
-int
-ix86_binary_operator_ok (code, mode, operands)
-     enum rtx_code code;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     rtx operands[3];
-{
-  return (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
-    && (GET_CODE (operands[1]) != CONST_INT || GET_RTX_CLASS (code) == 'c');
-}
-
-/* Attempt to expand a unary operator.  Make the expansion closer to the
-   actual machine, then just general_operand, which will allow 2 separate
-   memory references (one output, one input) in a single insn.  Return
-   whether the insn fails, or succeeds.  */
-
-int
-ix86_expand_unary_operator (code, mode, operands)
-     enum rtx_code code;
-     enum machine_mode mode;
-     rtx operands[];
-{
-  /* If optimizing, copy to regs to improve CSE */
-  if (TARGET_PSEUDO
-      && optimize
-      && ((reload_in_progress | reload_completed) == 0)
-      && GET_CODE (operands[1]) == MEM)
-    operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
-
-  if (! ix86_unary_operator_ok (code, mode, operands))
-    {
-      if ((! TARGET_PSEUDO || optimize == 0)
-	  && ((reload_in_progress | reload_completed) == 0)
-	  && GET_CODE (operands[1]) == MEM)
-	{
-	  operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
-	  if (! ix86_unary_operator_ok (code, mode, operands))
-	    return FALSE;
-	}
-      else
-	return FALSE;
-    }
-
-  return TRUE;
-}
-
-/* Return TRUE or FALSE depending on whether the unary operator meets the
-   appropriate constraints.  */
-
-int
-ix86_unary_operator_ok (code, mode, operands)
-     enum rtx_code code ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     rtx operands[2] ATTRIBUTE_UNUSED;
-{
-  return TRUE;
-}
-
-static rtx pic_label_rtx;
-static char pic_label_name [256];
-static int pic_label_no = 0;
-
-/* This function generates code for -fpic that loads %ebx with
-   the return address of the caller and then returns.  */
-
-void
-asm_output_function_prefix (file, name)
-     FILE *file;
-     char *name ATTRIBUTE_UNUSED;
-{
-  rtx xops[2];
-  int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
-				  || current_function_uses_const_pool);
-  xops[0] = pic_offset_table_rtx;
-  xops[1] = stack_pointer_rtx;
-
-  /* Deep branch prediction favors having a return for every call. */
-  if (pic_reg_used && TARGET_DEEP_BRANCH_PREDICTION)
-    {
-      tree prologue_node;
-
-      if (pic_label_rtx == 0)
-	{
-	  pic_label_rtx = gen_label_rtx ();
-	  ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++);
-	  LABEL_NAME (pic_label_rtx) = pic_label_name;
-	}
-
-      prologue_node = make_node (FUNCTION_DECL);
-      DECL_RESULT (prologue_node) = 0;
-
-      /* This used to call ASM_DECLARE_FUNCTION_NAME() but since it's an
-	 internal (non-global) label that's being emitted, it didn't make
-	 sense to have .type information for local labels.   This caused
-	 the SCO OpenServer 5.0.4 ELF assembler grief (why are you giving
-  	 me debug info for a label that you're declaring non-global?) this
-	 was changed to call ASM_OUTPUT_LABEL() instead. */
-
-
-      ASM_OUTPUT_LABEL (file, pic_label_name); 
-      output_asm_insn ("movl (%1),%0", xops);
-      output_asm_insn ("ret", xops);
-    }
-}
-
-/* Generate the assembly code for function entry.
-   FILE is an stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate. */
-
-void
-function_prologue (file, size)
-     FILE *file ATTRIBUTE_UNUSED;
-     int size ATTRIBUTE_UNUSED;
-{
-  if (TARGET_SCHEDULE_PROLOGUE)
-    {
-      pic_label_rtx = 0;
-      return;
-    }
-
-  ix86_prologue (0);
-}
-
-/* Expand the prologue into a bunch of separate insns. */
-
-void
-ix86_expand_prologue ()
-{
-  if (! TARGET_SCHEDULE_PROLOGUE)
-      return;
-
-  ix86_prologue (1);
-}
-
-void
-load_pic_register (do_rtl)
-     int do_rtl;
-{
-  rtx xops[4];
-
-  if (TARGET_DEEP_BRANCH_PREDICTION)
-    {
-      xops[0] = pic_offset_table_rtx;
-      if (pic_label_rtx == 0)
-	{
-	  pic_label_rtx = gen_label_rtx ();
-	  ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++);
-	  LABEL_NAME (pic_label_rtx) = pic_label_name;
-	}
-
-      xops[1] = gen_rtx_MEM (QImode,
-			 gen_rtx (SYMBOL_REF, Pmode,
-				  LABEL_NAME (pic_label_rtx)));
-
-      if (do_rtl)
-	{
-	  emit_insn (gen_prologue_get_pc (xops[0], xops[1]));
-	  emit_insn (gen_prologue_set_got (xops[0],
-					   gen_rtx (SYMBOL_REF, Pmode,
-						    "$_GLOBAL_OFFSET_TABLE_"),
-					   xops[1]));
-	}
-      else
-	{
-	  output_asm_insn (AS1 (call,%X1), xops);
-	  output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_,%0", xops);
-	  pic_label_rtx = 0;
-	}
-    }
-
-  else
-    {
-      xops[0] = pic_offset_table_rtx;
-      xops[1] = gen_label_rtx ();
-
-      if (do_rtl)
-	{
-	  /* We can't put a raw CODE_LABEL into the RTL, and we can't emit
-	     a new CODE_LABEL after reload, so we need a single pattern to
-	     emit the 3 necessary instructions.  */
-	  emit_insn (gen_prologue_get_pc_and_set_got (xops[0]));
-	}
-      else
-	{
-	  output_asm_insn (AS1 (call,%P1), xops);
-	  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				     CODE_LABEL_NUMBER (xops[1]));
-	  output_asm_insn (AS1 (pop%L0,%0), xops);
-	  output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops);
-	}
-    }
-
-  /* When -fpic, we must emit a scheduling barrier, so that the instruction
-     that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get
-     moved before any instruction which implicitly uses the got.   */
-
-  if (do_rtl)
-    emit_insn (gen_blockage ());
-}
-
-static void
-ix86_prologue (do_rtl)
-     int do_rtl;
-{
-  register int regno;
-  int limit;
-  rtx xops[4];
-  int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
-				  || current_function_uses_const_pool);
-  long tsize = get_frame_size ();
-  rtx insn;
-  int cfa_offset = INCOMING_FRAME_SP_OFFSET, cfa_store_offset = cfa_offset;
-
-  xops[0] = stack_pointer_rtx;
-  xops[1] = frame_pointer_rtx;
-  xops[2] = GEN_INT (tsize);
-
-  if (frame_pointer_needed)
-    {
-      if (do_rtl)
-	{
-	  insn = emit_insn (gen_rtx (SET, VOIDmode,
-				     gen_rtx_MEM (SImode,
-					      gen_rtx (PRE_DEC, SImode,
-						       stack_pointer_rtx)),
-				     frame_pointer_rtx));
-
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	  insn = emit_move_insn (xops[1], xops[0]);
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	}
-
-      else
-	{
-	  output_asm_insn ("push%L1 %1", xops);
-#ifdef INCOMING_RETURN_ADDR_RTX
- 	  if (dwarf2out_do_frame ())
- 	    {
- 	      char *l = dwarf2out_cfi_label ();
-
- 	      cfa_store_offset += 4;
- 	      cfa_offset = cfa_store_offset;
- 	      dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
- 	      dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, - cfa_store_offset);
- 	    }
-#endif
-
-	  output_asm_insn (AS2 (mov%L0,%0,%1), xops);
-#ifdef INCOMING_RETURN_ADDR_RTX
- 	  if (dwarf2out_do_frame ())
- 	    dwarf2out_def_cfa ("", FRAME_POINTER_REGNUM, cfa_offset);
-#endif
-	}
-    }
-
-  if (tsize == 0)
-    ;
-  else if (! TARGET_STACK_PROBE || tsize < CHECK_STACK_LIMIT)
-    {
-      if (do_rtl)
-	{
-	  insn = emit_insn (gen_prologue_set_stack_ptr (xops[2]));
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	}
-      else
-	{
-	  output_asm_insn (AS2 (sub%L0,%2,%0), xops);
-#ifdef INCOMING_RETURN_ADDR_RTX
- 	  if (dwarf2out_do_frame ())
- 	    {
- 	      cfa_store_offset += tsize;
- 	      if (! frame_pointer_needed)
- 		{
- 		  cfa_offset = cfa_store_offset;
- 		  dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset);
- 		}
- 	    }
-#endif
-	}
-    }
-  else
-    {
-      xops[3] = gen_rtx_REG (SImode, 0);
-      if (do_rtl)
-      emit_move_insn (xops[3], xops[2]);
-      else
-	output_asm_insn (AS2 (mov%L0,%2,%3), xops);
-
-      xops[3] = gen_rtx_MEM (FUNCTION_MODE,
-			 gen_rtx (SYMBOL_REF, Pmode, "_alloca"));
-
-      if (do_rtl)
-	emit_call_insn (gen_rtx (CALL, VOIDmode, xops[3], const0_rtx));
-      else
-	output_asm_insn (AS1 (call,%P3), xops);
-    }
-
-  /* Note If use enter it is NOT reversed args.
-     This one is not reversed from intel!!
-     I think enter is slower.  Also sdb doesn't like it.
-     But if you want it the code is:
-     {
-     xops[3] = const0_rtx;
-     output_asm_insn ("enter %2,%3", xops);
-     }
-     */
-
-  limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
-  for (regno = limit - 1; regno >= 0; regno--)
-    if ((regs_ever_live[regno] && ! call_used_regs[regno])
-	|| (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
-      {
-	xops[0] = gen_rtx_REG (SImode, regno);
-	if (do_rtl)
-	  {
-	    insn = emit_insn (gen_rtx (SET, VOIDmode,
-				       gen_rtx_MEM (SImode,
-						gen_rtx (PRE_DEC, SImode,
-							 stack_pointer_rtx)),
-				       xops[0]));
-
-	    RTX_FRAME_RELATED_P (insn) = 1;
-	  }
-	else
-	  {
-	    output_asm_insn ("push%L0 %0", xops);
-#ifdef INCOMING_RETURN_ADDR_RTX
- 	    if (dwarf2out_do_frame ())
- 	      {
- 		char *l = dwarf2out_cfi_label ();
-
- 		cfa_store_offset += 4;
- 		if (! frame_pointer_needed)
- 		  {
- 		    cfa_offset = cfa_store_offset;
- 		    dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
- 		  }
-
- 		dwarf2out_reg_save (l, regno, - cfa_store_offset);
- 	      }
-#endif
- 	  }
-      }
-
-#ifdef SUBTARGET_PROLOGUE
-  SUBTARGET_PROLOGUE;
-#endif  
-
-  if (pic_reg_used)
-    load_pic_register (do_rtl);
-
-  /* If we are profiling, make sure no instructions are scheduled before
-     the call to mcount.  However, if -fpic, the above call will have
-     done that.  */
-  if ((profile_flag || profile_block_flag)
-      && ! pic_reg_used && do_rtl)
-    emit_insn (gen_blockage ());
-}
-
-/* Return 1 if it is appropriate to emit `ret' instructions in the
-   body of a function.  Do this only if the epilogue is simple, needing a
-   couple of insns.  Prior to reloading, we can't tell how many registers
-   must be saved, so return 0 then.  Return 0 if there is no frame
-   marker to de-allocate.
-
-   If NON_SAVING_SETJMP is defined and true, then it is not possible
-   for the epilogue to be simple, so return 0.  This is a special case
-   since NON_SAVING_SETJMP will not cause regs_ever_live to change
-   until final, but jump_optimize may need to know sooner if a
-   `return' is OK.  */
-
-int
-ix86_can_use_return_insn_p ()
-{
-  int regno;
-  int nregs = 0;
-  int reglimit = (frame_pointer_needed
-		  ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
-  int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
-				  || current_function_uses_const_pool);
-
-#ifdef NON_SAVING_SETJMP
-  if (NON_SAVING_SETJMP && current_function_calls_setjmp)
-    return 0;
-#endif
-
-  if (! reload_completed)
-    return 0;
-
-  for (regno = reglimit - 1; regno >= 0; regno--)
-    if ((regs_ever_live[regno] && ! call_used_regs[regno])
-	|| (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
-      nregs++;
-
-  return nregs == 0 || ! frame_pointer_needed;
-}
-
-/* This function generates the assembly code for function exit.
-   FILE is an stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to deallocate. */
-
-void
-function_epilogue (file, size)
-     FILE *file ATTRIBUTE_UNUSED;
-     int size ATTRIBUTE_UNUSED;
-{
-    return;
-}
-
-/* Restore function stack, frame, and registers. */
-
-void
-ix86_expand_epilogue ()
-{
-  ix86_epilogue (1);
-}
-
-static void
-ix86_epilogue (do_rtl)
-     int do_rtl;
-{
-  register int regno;
-  register int nregs, limit;
-  int offset;
-  rtx xops[3];
-  int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
-				  || current_function_uses_const_pool);
-  int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
-  long tsize = get_frame_size ();
-
-  /* Compute the number of registers to pop */
-
-  limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
-
-  nregs = 0;
-
-  for (regno = limit - 1; regno >= 0; regno--)
-    if ((regs_ever_live[regno] && ! call_used_regs[regno])
-	|| (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
-      nregs++;
-
-  /* sp is often unreliable so we may have to go off the frame pointer. */
-
-  offset = - tsize - (nregs * UNITS_PER_WORD);
-
-  xops[2] = stack_pointer_rtx;
-
-  /* When -fpic, we must emit a scheduling barrier, so that the instruction
-     that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get
-     moved before any instruction which implicitly uses the got.  This
-     includes any instruction which uses a SYMBOL_REF or a LABEL_REF.
-
-     Alternatively, this could be fixed by making the dependence on the
-     PIC_OFFSET_TABLE_REGNUM explicit in the RTL.  */
-
-  if (flag_pic || profile_flag || profile_block_flag)
-    emit_insn (gen_blockage ());
-
-  /* If we're only restoring one register and sp is not valid then
-     using a move instruction to restore the register since it's
-     less work than reloading sp and popping the register.  Otherwise,
-     restore sp (if necessary) and pop the registers. */
-
-  if (nregs > 1 || sp_valid)
-    {
-      if ( !sp_valid )
-	{
-	  xops[0] = adj_offsettable_operand (AT_BP (QImode), offset);
-	  if (do_rtl)
-	    emit_insn (gen_movsi_lea (xops[2], XEXP (xops[0], 0)));
-	  else
-	    output_asm_insn (AS2 (lea%L2,%0,%2), xops);
-	}
-
-      for (regno = 0; regno < limit; regno++)
-	if ((regs_ever_live[regno] && ! call_used_regs[regno])
-	    || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
-	  {
-	    xops[0] = gen_rtx_REG (SImode, regno);
-
-	    if (do_rtl)
-	      emit_insn (gen_pop (xops[0]));
-	    else
-	      output_asm_insn ("pop%L0 %0", xops);
-	  }
-    }
-
-  else
-    for (regno = 0; regno < limit; regno++)
-      if ((regs_ever_live[regno] && ! call_used_regs[regno])
-	  || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
-	{
-	  xops[0] = gen_rtx_REG (SImode, regno);
-	  xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset);
-
-	  if (do_rtl)
-	    emit_move_insn (xops[0], xops[1]);
-	  else
-	    output_asm_insn (AS2 (mov%L0,%1,%0), xops);
-
-	  offset += 4;
-	}
-
-  if (frame_pointer_needed)
-    {
-      /* If not an i386, mov & pop is faster than "leave". */
-
-      if (TARGET_USE_LEAVE)
-	{
-	  if (do_rtl)
-	    emit_insn (gen_leave());
-	  else
-	    output_asm_insn ("leave", xops);
-	}
-      else
-	{
-	  xops[0] = frame_pointer_rtx;
-	  xops[1] = stack_pointer_rtx;
-
-	  if (do_rtl)
-	    {
-	      emit_insn (gen_epilogue_set_stack_ptr());
-	      emit_insn (gen_pop (xops[0]));
-	    }
-	  else
-	    {
-	      output_asm_insn (AS2 (mov%L2,%0,%2), xops);
-	      output_asm_insn ("pop%L0 %0", xops);
-	    }
-	}
-    }
-
-  else if (tsize)
-    {
-      /* Intel's docs say that for 4 or 8 bytes of stack frame one should
-	 use `pop' and not `add'.  */
-      int use_pop = tsize == 4;
-
-      /* Use two pops only for the Pentium processors.  */
-      if (tsize == 8 && !TARGET_386 && !TARGET_486)
-	{
-	  rtx retval = current_function_return_rtx;
-
-	  xops[1] = gen_rtx_REG (SImode, 1);	/* %edx */
-
-	  /* This case is a bit more complex.  Since we cannot pop into
-	     %ecx twice we need a second register.  But this is only
-	     available if the return value is not of DImode in which
-	     case the %edx register is not available.  */
-	  use_pop = (retval == NULL
-		     || ! reg_overlap_mentioned_p (xops[1], retval));
-	}
-
-      if (use_pop)
-	{
-	  xops[0] = gen_rtx_REG (SImode, 2);	/* %ecx */
-
-	  if (do_rtl)
-	    {
-	      /* We have to prevent the two pops here from being scheduled.
-		 GCC otherwise would try in some situation to put other
-		 instructions in between them which has a bad effect.  */
-	      emit_insn (gen_blockage ());
-	      emit_insn (gen_pop (xops[0]));
-	      if (tsize == 8)
-		emit_insn (gen_pop (xops[1]));
-	    }
-	  else
-	    {
-	      output_asm_insn ("pop%L0 %0", xops);
-	      if (tsize == 8)
-		output_asm_insn ("pop%L1 %1", xops);
-	    }
-	}
-      else
-	{
-	  /* If there is no frame pointer, we must still release the frame. */
-	  xops[0] = GEN_INT (tsize);
-
-	  if (do_rtl)
-	    emit_insn (gen_rtx (SET, VOIDmode, xops[2],
-				gen_rtx (PLUS, SImode, xops[2], xops[0])));
-	  else
-	    output_asm_insn (AS2 (add%L2,%0,%2), xops);
-	}
-    }
-
-#ifdef FUNCTION_BLOCK_PROFILER_EXIT
-  if (profile_block_flag == 2)
-    {
-      FUNCTION_BLOCK_PROFILER_EXIT(file);
-    }
-#endif
-
-  if (current_function_pops_args && current_function_args_size)
-    {
-      xops[1] = GEN_INT (current_function_pops_args);
-
-      /* i386 can only pop 32K bytes (maybe 64K?  Is it signed?).  If
-	 asked to pop more, pop return address, do explicit add, and jump
-	 indirectly to the caller. */
-
-      if (current_function_pops_args >= 32768)
-	{
-	  /* ??? Which register to use here? */
-	  xops[0] = gen_rtx_REG (SImode, 2);
-
-	  if (do_rtl)
-	    {
-	      emit_insn (gen_pop (xops[0]));
-	      emit_insn (gen_rtx (SET, VOIDmode, xops[2],
-				  gen_rtx (PLUS, SImode, xops[1], xops[2])));
-	      emit_jump_insn (xops[0]);
-	    }
-	  else
-	    {
-	      output_asm_insn ("pop%L0 %0", xops);
-	      output_asm_insn (AS2 (add%L2,%1,%2), xops);
-	      output_asm_insn ("jmp %*%0", xops);
-	    }
-	}
-      else
-	{
-	  if (do_rtl)
-	    emit_jump_insn (gen_return_pop_internal (xops[1]));
-	  else
-	    output_asm_insn ("ret %1", xops);
-	}
-    }
-  else
-    {
-      if (do_rtl)
-	emit_jump_insn (gen_return_internal ());
-      else
-	output_asm_insn ("ret", xops);
-    }
-}
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   On x86, legitimate addresses are:
-	base				movl (base),reg
-	displacement			movl disp,reg
-	base + displacement		movl disp(base),reg
-	index + base			movl (base,index),reg
-	(index + base) + displacement	movl disp(base,index),reg
-	index*scale			movl (,index,scale),reg
-	index*scale + disp		movl disp(,index,scale),reg
-	index*scale + base 		movl (base,index,scale),reg
-	(index*scale + base) + disp	movl disp(base,index,scale),reg
-
-	In each case, scale can be 1, 2, 4, 8.  */
-
-/* This is exactly the same as print_operand_addr, except that
-   it recognizes addresses instead of printing them.
-
-   It only recognizes address in canonical form.  LEGITIMIZE_ADDRESS should
-   convert common non-canonical forms to canonical form so that they will
-   be recognized.  */
-
-#define ADDR_INVALID(msg,insn)						\
-do {									\
-  if (TARGET_DEBUG_ADDR)						\
-    {									\
-      fprintf (stderr, msg);						\
-      debug_rtx (insn);							\
-    }									\
-} while (0)
-
-static int
-legitimate_pic_address_disp_p (disp)
-     register rtx disp;
-{
-  if (GET_CODE (disp) != CONST)
-    return 0;
-  disp = XEXP (disp, 0);
-
-  if (GET_CODE (disp) == PLUS)
-    {
-      if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
-	return 0;
-      disp = XEXP (disp, 0);
-    }
-
-  if (GET_CODE (disp) != UNSPEC
-      || XVECLEN (disp, 0) != 1)
-    return 0;
-
-  /* Must be @GOT or @GOTOFF.  */
-  if (XINT (disp, 1) != 6
-      && XINT (disp, 1) != 7)
-    return 0;
-
-  if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
-      && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
-    return 0;
-
-  return 1;
-}
-
-int
-legitimate_address_p (mode, addr, strict)
-     enum machine_mode mode;
-     register rtx addr;
-     int strict;
-{
-  rtx base  = NULL_RTX;
-  rtx indx  = NULL_RTX;
-  rtx scale = NULL_RTX;
-  rtx disp  = NULL_RTX;
-
-  if (TARGET_DEBUG_ADDR)
-    {
-      fprintf (stderr,
-	       "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
-	       GET_MODE_NAME (mode), strict);
-
-      debug_rtx (addr);
-    }
-
-  if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
-      base = addr;
-
-  else if (GET_CODE (addr) == PLUS)
-    {
-      rtx op0 = XEXP (addr, 0);
-      rtx op1 = XEXP (addr, 1);
-      enum rtx_code code0 = GET_CODE (op0);
-      enum rtx_code code1 = GET_CODE (op1);
-
-      if (code0 == REG || code0 == SUBREG)
-	{
-	  if (code1 == REG || code1 == SUBREG)
-	    {
-	      indx = op0;	/* index + base */
-	      base = op1;
-	    }
-
-	  else
-	    {
-	      base = op0;	/* base + displacement */
-	      disp = op1;
-	    }
-	}
-
-      else if (code0 == MULT)
-	{
-	  indx  = XEXP (op0, 0);
-	  scale = XEXP (op0, 1);
-
-	  if (code1 == REG || code1 == SUBREG)
-	    base = op1;		/* index*scale + base */
-
-	  else
-	    disp = op1;		/* index*scale + disp */
-	}
-
-      else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
-	{
-	  indx  = XEXP (XEXP (op0, 0), 0);	/* index*scale + base + disp */
-	  scale = XEXP (XEXP (op0, 0), 1);
-	  base  = XEXP (op0, 1);
-	  disp  = op1;
-	}
-
-      else if (code0 == PLUS)
-	{
-	  indx = XEXP (op0, 0);	/* index + base + disp */
-	  base = XEXP (op0, 1);
-	  disp = op1;
-	}
-
-      else
-	{
-	  ADDR_INVALID ("PLUS subcode is not valid.\n", op0);
-	  return FALSE;
-	}
-    }
-
-  else if (GET_CODE (addr) == MULT)
-    {
-      indx  = XEXP (addr, 0);	/* index*scale */
-      scale = XEXP (addr, 1);
-    }
-
-  else
-    disp = addr;		/* displacement */
-
-  /* Allow arg pointer and stack pointer as index if there is not scaling */
-  if (base && indx && !scale
-      && (indx == arg_pointer_rtx || indx == stack_pointer_rtx))
-    {
-      rtx tmp = base;
-      base = indx;
-      indx = tmp;
-    }
-
-  /* Validate base register:
-
-     Don't allow SUBREG's here, it can lead to spill failures when the base
-     is one word out of a two word structure, which is represented internally
-     as a DImode int.  */
-
-  if (base)
-    {
-      if (GET_CODE (base) != REG)
-	{
-	  ADDR_INVALID ("Base is not a register.\n", base);
-	  return FALSE;
-	}
-
-      if ((strict && ! REG_OK_FOR_BASE_STRICT_P (base))
-	  || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (base)))
-	{
-	  ADDR_INVALID ("Base is not valid.\n", base);
-	  return FALSE;
-	}
-    }
-
-  /* Validate index register:
-
-     Don't allow SUBREG's here, it can lead to spill failures when the index
-     is one word out of a two word structure, which is represented internally
-     as a DImode int.  */
-  if (indx)
-    {
-      if (GET_CODE (indx) != REG)
-	{
-	  ADDR_INVALID ("Index is not a register.\n", indx);
-	  return FALSE;
-	}
-
-      if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (indx))
-	  || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (indx)))
-	{
-	  ADDR_INVALID ("Index is not valid.\n", indx);
-	  return FALSE;
-	}
-    }
-  else if (scale)
-    abort ();			/* scale w/o index invalid */
-
-  /* Validate scale factor: */
-  if (scale)
-    {
-      HOST_WIDE_INT value;
-
-      if (GET_CODE (scale) != CONST_INT)
-	{
-	  ADDR_INVALID ("Scale is not valid.\n", scale);
-	  return FALSE;
-	}
-
-      value = INTVAL (scale);
-      if (value != 1 && value != 2 && value != 4 && value != 8)
-	{
-	  ADDR_INVALID ("Scale is not a good multiplier.\n", scale);
-	  return FALSE;
-	}
-    }
-
-  /* Validate displacement.  */
-  if (disp)
-    {
-      if (!CONSTANT_ADDRESS_P (disp))
-	{
-	  ADDR_INVALID ("Displacement is not valid.\n", disp);
-	  return FALSE;
-	}
-
-      else if (GET_CODE (disp) == CONST_DOUBLE)
-	{
-	  ADDR_INVALID ("Displacement is a const_double.\n", disp);
-	  return FALSE;
-	}
-
-      if (flag_pic && SYMBOLIC_CONST (disp))
-	{
-	  if (! legitimate_pic_address_disp_p (disp))
-	    {
-	      ADDR_INVALID ("Displacement is an invalid PIC construct.\n",
-			    disp);
-	      return FALSE;
-	    }
-
-	  if (base != pic_offset_table_rtx
-	      && (indx != pic_offset_table_rtx || scale != NULL_RTX))
-	    {
-	      ADDR_INVALID ("PIC displacement against invalid base.\n", disp);
-	      return FALSE;
-	    }
-	}
-
-      else if (HALF_PIC_P ())
-	{
-	  if (! HALF_PIC_ADDRESS_P (disp)
-	      || (base != NULL_RTX || indx != NULL_RTX))
-	    {
-	      ADDR_INVALID ("Displacement is an invalid half-pic reference.\n",
-			    disp);
-	      return FALSE;
-	    }
-	}
-    }
-
-  if (TARGET_DEBUG_ADDR)
-    fprintf (stderr, "Address is valid.\n");
-
-  /* Everything looks valid, return true */
-  return TRUE;
-}
-
-/* Return a legitimate reference for ORIG (an address) using the
-   register REG.  If REG is 0, a new pseudo is generated.
-
-   There are two types of references that must be handled:
-
-   1. Global data references must load the address from the GOT, via
-      the PIC reg.  An insn is emitted to do this load, and the reg is
-      returned.
-
-   2. Static data references, constant pool addresses, and code labels
-      compute the address as an offset from the GOT, whose base is in
-      the PIC reg.  Static data objects have SYMBOL_REF_FLAG set to
-      differentiate them from global data objects.  The returned
-      address is the PIC reg + an unspec constant.
-
-   GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
-   reg also appears in the address.  */
-
-rtx
-legitimize_pic_address (orig, reg)
-     rtx orig;
-     rtx reg;
-{
-  rtx addr = orig;
-  rtx new = orig;
-  rtx base;
-
-  if (GET_CODE (addr) == LABEL_REF
-      || (GET_CODE (addr) == SYMBOL_REF
-	  && (CONSTANT_POOL_ADDRESS_P (addr)
-	      || SYMBOL_REF_FLAG (addr))))
-    {
-      /* This symbol may be referenced via a displacement from the PIC
-	 base address (@GOTOFF).  */
-
-      current_function_uses_pic_offset_table = 1;
-      new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 7);
-      new = gen_rtx_CONST (VOIDmode, new);
-      new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
-
-      if (reg != 0)
-	{
-	  emit_move_insn (reg, new);
-	  new = reg;
-	}
-    }
-  else if (GET_CODE (addr) == SYMBOL_REF)
-    {
-      /* This symbol must be referenced via a load from the
-	 Global Offset Table (@GOT). */
-
-      current_function_uses_pic_offset_table = 1;
-      new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 6);
-      new = gen_rtx_CONST (VOIDmode, new);
-      new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
-      new = gen_rtx_MEM (Pmode, new);
-      RTX_UNCHANGING_P (new) = 1;
-
-      if (reg == 0)
-	reg = gen_reg_rtx (Pmode);
-      emit_move_insn (reg, new);
-      new = reg;
-    }      
-  else
-    {
-      if (GET_CODE (addr) == CONST)
-	{
-	  addr = XEXP (addr, 0);
-	  if (GET_CODE (addr) == UNSPEC)
-	    {
-	      /* Check that the unspec is one of the ones we generate?  */
-	    }
-	  else if (GET_CODE (addr) != PLUS)
-	    abort();
-	}
-      if (GET_CODE (addr) == PLUS)
-	{
-	  rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
-
-	  /* Check first to see if this is a constant offset from a @GOTOFF
-	     symbol reference.  */
-	  if ((GET_CODE (op0) == LABEL_REF
-	       || (GET_CODE (op0) == SYMBOL_REF
-		   && (CONSTANT_POOL_ADDRESS_P (op0)
-		       || SYMBOL_REF_FLAG (op0))))
-	      && GET_CODE (op1) == CONST_INT)
-	    {
-	      current_function_uses_pic_offset_table = 1;
-	      new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, op0), 7);
-	      new = gen_rtx_PLUS (VOIDmode, new, op1);
-	      new = gen_rtx_CONST (VOIDmode, new);
-	      new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
-
-	      if (reg != 0)
-		{
-		  emit_move_insn (reg, new);
-		  new = reg;
-		}
-	    }
-	  else
-	    {
-	      base = legitimize_pic_address (XEXP (addr, 0), reg);
-	      new  = legitimize_pic_address (XEXP (addr, 1),
-					     base == reg ? NULL_RTX : reg);
-
-	      if (GET_CODE (new) == CONST_INT)
-		new = plus_constant (base, INTVAL (new));
-	      else
-		{
-		  if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
-		    {
-		      base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
-		      new = XEXP (new, 1);
-		    }
-		  new = gen_rtx_PLUS (Pmode, base, new);
-		}
-	    }
-	}
-    }
-  return new;
-}
-
-/* Emit insns to move operands[1] into operands[0].  */
-
-void
-emit_pic_move (operands, mode)
-     rtx *operands;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
-
-  if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
-    operands[1] = force_reg (Pmode, operands[1]);
-  else
-    operands[1] = legitimize_pic_address (operands[1], temp);
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the 80386, we handle X+REG by loading X into a register R and
-   using R+REG.  R will go in a general reg and indexing will be used.
-   However, if REG is a broken-out memory address or multiplication,
-   nothing needs to be done because REG can certainly go in a general reg.
-
-   When -fpic is used, special handling is needed for symbolic references.
-   See comments by legitimize_pic_address in i386.c for details.  */
-
-rtx
-legitimize_address (x, oldx, mode)
-     register rtx x;
-     register rtx oldx ATTRIBUTE_UNUSED;
-     enum machine_mode mode;
-{
-  int changed = 0;
-  unsigned log;
-
-  if (TARGET_DEBUG_ADDR)
-    {
-      fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
-	       GET_MODE_NAME (mode));
-      debug_rtx (x);
-    }
-
-  if (flag_pic && SYMBOLIC_CONST (x))
-    return legitimize_pic_address (x, 0);
-
-  /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
-  if (GET_CODE (x) == ASHIFT
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
-      && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4)
-    {
-      changed = 1;
-      x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
-			GEN_INT (1 << log));
-    }
-
-  if (GET_CODE (x) == PLUS)
-    {
-      /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
-
-      if (GET_CODE (XEXP (x, 0)) == ASHIFT
-	  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
-	  && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4)
-	{
-	  changed = 1;
-	  XEXP (x, 0) = gen_rtx (MULT, Pmode,
-				 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
-				 GEN_INT (1 << log));
-	}
-
-      if (GET_CODE (XEXP (x, 1)) == ASHIFT
-	  && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
-	  && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4)
-	{
-	  changed = 1;
-	  XEXP (x, 1) = gen_rtx (MULT, Pmode,
-				 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
-				 GEN_INT (1 << log));
-	}
-
-      /* Put multiply first if it isn't already. */
-      if (GET_CODE (XEXP (x, 1)) == MULT)
-	{
-	  rtx tmp = XEXP (x, 0);
-	  XEXP (x, 0) = XEXP (x, 1);
-	  XEXP (x, 1) = tmp;
-	  changed = 1;
-	}
-
-      /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
-	 into (plus (plus (mult (reg) (const)) (reg)) (const)).  This can be
-	 created by virtual register instantiation, register elimination, and
-	 similar optimizations.  */
-      if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
-	{
-	  changed = 1;
-	  x = gen_rtx (PLUS, Pmode,
-		       gen_rtx (PLUS, Pmode, XEXP (x, 0),
-				XEXP (XEXP (x, 1), 0)),
-		       XEXP (XEXP (x, 1), 1));
-	}
-
-      /* Canonicalize
-	 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
-	 into (plus (plus (mult (reg) (const)) (reg)) (const)).  */
-      else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
-	       && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
-	       && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
-	       && CONSTANT_P (XEXP (x, 1)))
-	{
-	  rtx constant;
-	  rtx other = NULL_RTX;
-
-	  if (GET_CODE (XEXP (x, 1)) == CONST_INT)
-	    {
-	      constant = XEXP (x, 1);
-	      other = XEXP (XEXP (XEXP (x, 0), 1), 1);
-	    }
-	  else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
-	    {
-	      constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
-	      other = XEXP (x, 1);
-	    }
-	  else
-	    constant = 0;
-
-	  if (constant)
-	    {
-	      changed = 1;
-	      x = gen_rtx (PLUS, Pmode,
-			   gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
-				    XEXP (XEXP (XEXP (x, 0), 1), 0)),
-			   plus_constant (other, INTVAL (constant)));
-	    }
-	}
-
-      if (changed && legitimate_address_p (mode, x, FALSE))
-	return x;
-
-      if (GET_CODE (XEXP (x, 0)) == MULT)
-	{
-	  changed = 1;
-	  XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
-	}
-
-      if (GET_CODE (XEXP (x, 1)) == MULT)
-	{
-	  changed = 1;
-	  XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
-	}
-
-      if (changed
-	  && GET_CODE (XEXP (x, 1)) == REG
-	  && GET_CODE (XEXP (x, 0)) == REG)
-	return x;
-
-      if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
-	{
-	  changed = 1;
-	  x = legitimize_pic_address (x, 0);
-	}
-
-      if (changed && legitimate_address_p (mode, x, FALSE))
-	return x;
-
-      if (GET_CODE (XEXP (x, 0)) == REG)
-	{
-	  register rtx temp = gen_reg_rtx (Pmode);
-	  register rtx val  = force_operand (XEXP (x, 1), temp);
-	  if (val != temp)
-	    emit_move_insn (temp, val);
-
-	  XEXP (x, 1) = temp;
-	  return x;
-	}
-
-      else if (GET_CODE (XEXP (x, 1)) == REG)
-	{
-	  register rtx temp = gen_reg_rtx (Pmode);
-	  register rtx val  = force_operand (XEXP (x, 0), temp);
-	  if (val != temp)
-	    emit_move_insn (temp, val);
-
-	  XEXP (x, 0) = temp;
-	  return x;
-	}
-    }
-
-  return x;
-}
-
-/* Print an integer constant expression in assembler syntax.  Addition
-   and subtraction are the only arithmetic that may appear in these
-   expressions.  FILE is the stdio stream to write to, X is the rtx, and
-   CODE is the operand print code from the output string.  */
-
-static void
-output_pic_addr_const (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
-{
-  char buf[256];
-
-  switch (GET_CODE (x))
-    {
-    case PC:
-      if (flag_pic)
-	putc ('.', file);
-      else
-	abort ();
-      break;
-
-    case SYMBOL_REF:
-      assemble_name (file, XSTR (x, 0));
-      if (code == 'P' && ! SYMBOL_REF_FLAG (x))
-	fputs ("@PLT", file);
-      break;
-
-    case LABEL_REF:
-      x = XEXP (x, 0);
-      /* FALLTHRU */
-    case CODE_LABEL:
-      ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
-      assemble_name (asm_out_file, buf);
-      break;
-
-    case CONST_INT:
-      fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
-      break;
-
-    case CONST:
-      /* This used to output parentheses around the expression,
-	 but that does not work on the 386 (either ATT or BSD assembler).  */
-      output_pic_addr_const (file, XEXP (x, 0), code);
-      break;
-
-    case CONST_DOUBLE:
-      if (GET_MODE (x) == VOIDmode)
-	{
-	  /* We can use %d if the number is <32 bits and positive.  */
-	  if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
-	    fprintf (file, "0x%lx%08lx",
-		     (unsigned long) CONST_DOUBLE_HIGH (x),
-		     (unsigned long) CONST_DOUBLE_LOW (x));
-	  else
-	    fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
-	}
-      else
-	/* We can't handle floating point constants;
-	   PRINT_OPERAND must handle them.  */
-	output_operand_lossage ("floating constant misused");
-      break;
-
-    case PLUS:
-      /* Some assemblers need integer constants to appear first.  */
-      if (GET_CODE (XEXP (x, 0)) == CONST_INT)
-	{
-	  output_pic_addr_const (file, XEXP (x, 0), code);
-	  fprintf (file, "+");
-	  output_pic_addr_const (file, XEXP (x, 1), code);
-	}
-      else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
-	{
-	  output_pic_addr_const (file, XEXP (x, 1), code);
-	  fprintf (file, "+");
-	  output_pic_addr_const (file, XEXP (x, 0), code);
-	}
-      else
-	abort ();
-      break;
-
-    case MINUS:
-      output_pic_addr_const (file, XEXP (x, 0), code);
-      fprintf (file, "-");
-      output_pic_addr_const (file, XEXP (x, 1), code);
-      break;
-
-     case UNSPEC:
-       if (XVECLEN (x, 0) != 1)
- 	abort ();
-       output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
-       switch (XINT (x, 1))
- 	{
- 	case 6:
- 	  fputs ("@GOT", file);
- 	  break;
- 	case 7:
- 	  fputs ("@GOTOFF", file);
- 	  break;
- 	case 8:
- 	  fputs ("@PLT", file);
- 	  break;
- 	default:
- 	  output_operand_lossage ("invalid UNSPEC as operand");
- 	  break;
- 	}
-       break;
-
-    default:
-      output_operand_lossage ("invalid expression as operand");
-    }
-}
-
-static void
-put_jump_code (code, reverse, file)
-     enum rtx_code code;
-     int reverse;
-     FILE *file;
-{
-  int flags = cc_prev_status.flags;
-  int ieee = (TARGET_IEEE_FP && (flags & CC_IN_80387));
-  const char *suffix;
-
-  if (flags & CC_Z_IN_NOT_C)
-    switch (code)
-      {
-      case EQ:
-	fputs (reverse ? "c" : "nc", file);
-	return;
-
-      case NE:
-	fputs (reverse ? "nc" : "c", file);
-	return;
-
-      default:
-	abort ();
-      }
-  if (ieee)
-    {
-      switch (code)
-	{
-	case LE:
-	  suffix = reverse ? "ae" : "b";
-	  break;
-	case GT:
-	case LT:
-	case GE:
-	  suffix = reverse ? "ne" : "e";
-	  break;
-	case EQ:
-	  suffix = reverse ? "ne" : "e";
-	  break;
-	case NE:
-	  suffix = reverse ? "e" : "ne";
-	  break;
-	default:
-	  abort ();
-	}
-      fputs (suffix, file);
-      return;
-    }
-  if (flags & CC_TEST_AX)
-    abort();
-  if ((flags & CC_NO_OVERFLOW) && (code == LE || code == GT))
-    abort ();
-  if (reverse)
-    code = reverse_condition (code);
-  switch (code)
-    {
-    case EQ:
-      suffix = "e";
-      break;
-
-    case NE:
-      suffix = "ne";
-      break;
-
-    case GT:
-      suffix = flags & CC_IN_80387 ? "a" : "g";
-      break;
-
-    case GTU:
-      suffix = "a";
-      break;
-
-    case LT:
-      if (flags & CC_NO_OVERFLOW)
-	suffix = "s";
-      else
-	suffix = flags & CC_IN_80387 ? "b" : "l";
-      break;
-
-    case LTU:
-      suffix = "b";
-      break;
-
-    case GE:
-      if (flags & CC_NO_OVERFLOW)
-	suffix = "ns";
-      else
-	suffix = flags & CC_IN_80387 ? "ae" : "ge";
-      break;
-
-    case GEU:
-      suffix = "ae";
-      break;
-
-    case LE:
-      suffix = flags & CC_IN_80387 ? "be" : "le";
-      break;
-
-    case LEU:
-      suffix = "be";
-      break;
-
-    default:
-      abort ();
-    }
-  fputs (suffix, file);
-}
-
-/* Append the correct conditional move suffix which corresponds to CODE.  */
-
-static void
-put_condition_code (code, reverse_cc, mode, file)
-     enum rtx_code code;
-     int  reverse_cc;
-     enum mode_class mode;
-     FILE * file;
-{
-  int ieee = (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
-	      && ! (cc_prev_status.flags & CC_FCOMI));
-  if (reverse_cc && ! ieee)
-    code = reverse_condition (code);
-
-  if (mode == MODE_INT)
-    switch (code)
-      {
-      case NE:
-	if (cc_prev_status.flags & CC_Z_IN_NOT_C)
-	  fputs ("b", file);
-	else
-	  fputs ("ne", file);
-	return;
-
-      case EQ:
-	if (cc_prev_status.flags & CC_Z_IN_NOT_C)
-	  fputs ("ae", file);
-	else
-	  fputs ("e", file);
-	return;
-
-      case GE:
-	if (cc_prev_status.flags & CC_NO_OVERFLOW)
-	  fputs ("ns", file);
-	else
-	  fputs ("ge", file);
-	return;
-
-      case GT:
-	fputs ("g", file);
-	return;
-
-      case LE:
-	fputs ("le", file);
-	return;
-
-      case LT:
-	if (cc_prev_status.flags & CC_NO_OVERFLOW)
-	  fputs ("s", file);
-	else
-	  fputs ("l", file);
-	return;
-
-      case GEU:
-	fputs ("ae", file);
-	return;
-
-      case GTU:
-	fputs ("a", file);
-	return;
-
-      case LEU:
-	fputs ("be", file);
-	return;
-
-      case LTU:
-	fputs ("b", file);
-	return;
-
-      default:
-	output_operand_lossage ("Invalid %%C operand");
-      }
-
-  else if (mode == MODE_FLOAT)
-    switch (code)
-      {
-      case NE:
-	fputs (ieee ? (reverse_cc ? "ne" : "e") : "ne", file);
-	return;
-      case EQ:
-	fputs (ieee ? (reverse_cc ? "ne" : "e") : "e", file);
-	return;
-      case GE:
-	fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file);
-	return;
-      case GT:
-	fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file);
-	return;
-      case LE:
-	fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file);
-	return;
-      case LT:
-	fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file);
-	return;
-      case GEU:
-	fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file);
-	return;
-      case GTU:
-	fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file);
-	return;
-      case LEU:
-	fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file);
-	return;
-      case LTU:
-	fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file);
-	return;
-      default:
-	output_operand_lossage ("Invalid %%C operand");
-    }
-}
-
-/* Meaning of CODE:
-   L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
-   C -- print opcode suffix for set/cmov insn.
-   c -- like C, but print reversed condition
-   F -- print opcode suffix for fcmov insn.
-   f -- like F, but print reversed condition
-   D -- print the opcode suffix for a jump
-   d -- like D, but print reversed condition
-   R -- print the prefix for register names.
-   z -- print the opcode suffix for the size of the current operand.
-   * -- print a star (in certain assembler syntax)
-   w -- print the operand as if it's a "word" (HImode) even if it isn't.
-   J -- print the appropriate jump operand.
-   s -- print a shift double count, followed by the assemblers argument
-	delimiter.
-   b -- print the QImode name of the register for the indicated operand.
-	%b0 would print %al if operands[0] is reg 0.
-   w --  likewise, print the HImode name of the register.
-   k --  likewise, print the SImode name of the register.
-   h --  print the QImode name for a "high" register, either ah, bh, ch or dh.
-   y --  print "st(0)" instead of "st" as a register.
-   P --  print as a PIC constant */
-
-void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
-{
-  if (code)
-    {
-      switch (code)
-	{
-	case '*':
-	  if (USE_STAR)
-	    putc ('*', file);
-	  return;
-
-	case 'L':
-	  PUT_OP_SIZE (code, 'l', file);
-	  return;
-
-	case 'W':
-	  PUT_OP_SIZE (code, 'w', file);
-	  return;
-
-	case 'B':
-	  PUT_OP_SIZE (code, 'b', file);
-	  return;
-
-	case 'Q':
-	  PUT_OP_SIZE (code, 'l', file);
-	  return;
-
-	case 'S':
-	  PUT_OP_SIZE (code, 's', file);
-	  return;
-
-	case 'T':
-	  PUT_OP_SIZE (code, 't', file);
-	  return;
-
-	case 'z':
-	  /* 387 opcodes don't get size suffixes if the operands are
-	     registers. */
-
-	  if (STACK_REG_P (x))
-	    return;
-
-	  /* this is the size of op from size of operand */
-	  switch (GET_MODE_SIZE (GET_MODE (x)))
-	    {
-	    case 1:
-	      PUT_OP_SIZE ('B', 'b', file);
-	      return;
-
-	    case 2:
-	      PUT_OP_SIZE ('W', 'w', file);
-	      return;
-
-	    case 4:
-	      if (GET_MODE (x) == SFmode)
-		{
-		  PUT_OP_SIZE ('S', 's', file);
-		  return;
-		}
-	      else
-		PUT_OP_SIZE ('L', 'l', file);
-	      return;
-
-	    case 12:
-		  PUT_OP_SIZE ('T', 't', file);
-		  return;
-
-	    case 8:
-	      if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
-		{
-#ifdef GAS_MNEMONICS
-		  PUT_OP_SIZE ('Q', 'q', file);
-		  return;
-#else
-		  PUT_OP_SIZE ('Q', 'l', file);	/* Fall through */
-#endif
-		}
-
-	      PUT_OP_SIZE ('Q', 'l', file);
-	      return;
-	    }
-
-	case 'b':
-	case 'w':
-	case 'k':
-	case 'h':
-	case 'y':
-	case 'P':
-	case 'X':
-	  break;
-
-	case 'J':
-	  switch (GET_CODE (x))
-	    {
-	      /* These conditions are appropriate for testing the result
-		 of an arithmetic operation, not for a compare operation.
-	         Cases GE, LT assume CC_NO_OVERFLOW true. All cases assume
-		 CC_Z_IN_NOT_C false and not floating point.  */
-	    case NE:  fputs ("jne", file); return;
-	    case EQ:  fputs ("je",  file); return;
-	    case GE:  fputs ("jns", file); return;
-	    case LT:  fputs ("js",  file); return;
-	    case GEU: fputs ("jmp", file); return;
-	    case GTU: fputs ("jne",  file); return;
-	    case LEU: fputs ("je", file); return;
-	    case LTU: fputs ("#branch never",  file); return;
-
-	    /* no matching branches for GT nor LE */
-
-	    default:
-	      abort ();
-	    }
-
-	case 's':
-	  if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
-	    {
-	      PRINT_OPERAND (file, x, 0);
-	      fputs (AS2C (,) + 1, file);
-	    }
-
-	  return;
-
-	case 'D':
-	  put_jump_code (GET_CODE (x), 0, file);
-	  return;
-
-	case 'd':
-	  put_jump_code (GET_CODE (x), 1, file);
-	  return;
-
-	  /* This is used by the conditional move instructions.  */
-	case 'C':
-	  put_condition_code (GET_CODE (x), 0, MODE_INT, file);
-	  return;
-
-	  /* Like above, but reverse condition */
-	case 'c':
-	  put_condition_code (GET_CODE (x), 1, MODE_INT, file); return;
-
-	case 'F':
-	  put_condition_code (GET_CODE (x), 0, MODE_FLOAT, file);
-	  return;
-
-	  /* Like above, but reverse condition */
-	case 'f':
-	  put_condition_code (GET_CODE (x), 1, MODE_FLOAT, file);
-	  return;
-
-	default:
-	  {
-	    char str[50];
-
-	    sprintf (str, "invalid operand code `%c'", code);
-	    output_operand_lossage (str);
-	  }
-	}
-    }
-
-  if (GET_CODE (x) == REG)
-    {
-      PRINT_REG (x, code, file);
-    }
-
-  else if (GET_CODE (x) == MEM)
-    {
-      PRINT_PTR (x, file);
-      if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
-	{
-	  if (flag_pic)
-	    output_pic_addr_const (file, XEXP (x, 0), code);
-	  else
-	    output_addr_const (file, XEXP (x, 0));
-	}
-      else
-	output_address (XEXP (x, 0));
-    }
-
-  else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
-    {
-      REAL_VALUE_TYPE r;
-      long l;
-
-      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
-      REAL_VALUE_TO_TARGET_SINGLE (r, l);
-      PRINT_IMMED_PREFIX (file);
-      fprintf (file, "0x%lx", l);
-    }
-
- /* These float cases don't actually occur as immediate operands. */
- else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
-    {
-      REAL_VALUE_TYPE r;
-      char dstr[30];
-
-      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
-      REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
-      fprintf (file, "%s", dstr);
-    }
-
-  else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
-    {
-      REAL_VALUE_TYPE r;
-      char dstr[30];
-
-      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
-      REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
-      fprintf (file, "%s", dstr);
-    }
-  else
-    {
-      if (code != 'P')
-	{
-	  if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
-	    PRINT_IMMED_PREFIX (file);
-	  else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
-		   || GET_CODE (x) == LABEL_REF)
-	    PRINT_OFFSET_PREFIX (file);
-	}
-      if (flag_pic)
-	output_pic_addr_const (file, x, code);
-      else
-	output_addr_const (file, x);
-    }
-}
-
-/* Print a memory operand whose address is ADDR.  */
-
-void
-print_operand_address (file, addr)
-     FILE *file;
-     register rtx addr;
-{
-  register rtx reg1, reg2, breg, ireg;
-  rtx offset;
-
-  switch (GET_CODE (addr))
-    {
-    case REG:
-      ADDR_BEG (file);
-      fprintf (file, "%se", RP);
-      fputs (hi_reg_name[REGNO (addr)], file);
-      ADDR_END (file);
-      break;
-
-    case PLUS:
-      reg1 = 0;
-      reg2 = 0;
-      ireg = 0;
-      breg = 0;
-      offset = 0;
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
-	{
-	  offset = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
-	}
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
-	{
-	  offset = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-
-      if (GET_CODE (addr) != PLUS)
-	;
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)
-	reg1 = XEXP (addr, 0), addr = XEXP (addr, 1);
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)
-	reg1 = XEXP (addr, 1), addr = XEXP (addr, 0);
-      else if (GET_CODE (XEXP (addr, 0)) == REG)
-	reg1 = XEXP (addr, 0), addr = XEXP (addr, 1);
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	reg1 = XEXP (addr, 1), addr = XEXP (addr, 0);
-
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
-	{
-	  if (reg1 == 0)
-	    reg1 = addr;
-	  else
-	    reg2 = addr;
-
-	  addr = 0;
-	}
-
-      if (offset != 0)
-	{
-	  if (addr != 0)
-	    abort ();
-	  addr = offset;
-	}
-
-      if ((reg1 && GET_CODE (reg1) == MULT)
-	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
-	{
-	  breg = reg2;
-	  ireg = reg1;
-	}
-      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
-	{
-	  breg = reg1;
-	  ireg = reg2;
-	}
-
-      if (ireg != 0 || breg != 0)
-	{
-	  int scale = 1;
-
-	  if (addr != 0)
-	    {
-	      if (flag_pic)
-		output_pic_addr_const (file, addr, 0);
-	      else if (GET_CODE (addr) == LABEL_REF)
-		output_asm_label (addr);
-	      else
-		output_addr_const (file, addr);
-	    }
-
-  	  if (ireg != 0 && GET_CODE (ireg) == MULT)
-	    {
-	      scale = INTVAL (XEXP (ireg, 1));
-	      ireg = XEXP (ireg, 0);
-	    }
-
-	  /* The stack pointer can only appear as a base register,
-	     never an index register, so exchange the regs if it is wrong. */
-
-	  if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
-	    {
-	      rtx tmp;
-
-	      tmp = breg;
-	      breg = ireg;
-	      ireg = tmp;
-	    }
-
-	  /* output breg+ireg*scale */
-	  PRINT_B_I_S (breg, ireg, scale, file);
-	  break;
-	}
-
-    case MULT:
-      {
-	int scale;
-
-	if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
-	  {
-	    scale = INTVAL (XEXP (addr, 0));
-	    ireg = XEXP (addr, 1);
-	  }
-	else
-	  {
-	    scale = INTVAL (XEXP (addr, 1));
-	    ireg = XEXP (addr, 0);
-	  }
-
-	output_addr_const (file, const0_rtx);
-	PRINT_B_I_S (NULL_RTX, ireg, scale, file);
-      }
-      break;
-
-    default:
-      if (GET_CODE (addr) == CONST_INT
-	  && INTVAL (addr) < 0x8000
-	  && INTVAL (addr) >= -0x8000)
-	fprintf (file, "%d", (int) INTVAL (addr));
-      else
-	{
-	  if (flag_pic)
-	    output_pic_addr_const (file, addr, 0);
-	  else
-	    output_addr_const (file, addr);
-	}
-    }
-}
-
-/* Set the cc_status for the results of an insn whose pattern is EXP.
-   On the 80386, we assume that only test and compare insns, as well
-   as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, BSF, ASHIFT,
-   ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
-   Also, we assume that jumps, moves and sCOND don't affect the condition
-   codes.  All else clobbers the condition codes, by assumption.
-
-   We assume that ALL integer add, minus, etc. instructions effect the
-   condition codes.  This MUST be consistent with i386.md.
-
-   We don't record any float test or compare - the redundant test &
-   compare check in final.c does not handle stack-like regs correctly. */
-
-void
-notice_update_cc (exp)
-     rtx exp;
-{
-  if (GET_CODE (exp) == SET)
-    {
-      /* Jumps do not alter the cc's.  */
-      if (SET_DEST (exp) == pc_rtx)
-	return;
-
-      /* Moving register or memory into a register:
-	 it doesn't alter the cc's, but it might invalidate
-	 the RTX's which we remember the cc's came from.
-	 (Note that moving a constant 0 or 1 MAY set the cc's).  */
-      if (REG_P (SET_DEST (exp))
-	  && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
-	      || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'
-	      || (GET_CODE (SET_SRC (exp)) == IF_THEN_ELSE
-		  && GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_INT)))
-	{
-	  if (cc_status.value1
-	      && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
-	    cc_status.value1 = 0;
-
-	  if (cc_status.value2
-	      && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
-	    cc_status.value2 = 0;
-
-	  return;
-	}
-
-      /* Moving register into memory doesn't alter the cc's.
-	 It may invalidate the RTX's which we remember the cc's came from.  */
-      if (GET_CODE (SET_DEST (exp)) == MEM
-	  && (REG_P (SET_SRC (exp))
-	      || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
-	{
-	  if (cc_status.value1
-	      && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
-	    cc_status.value1 = 0;
-	  if (cc_status.value2
-	      && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
-	    cc_status.value2 = 0;
-
-	  return;
-	}
-
-      /* Function calls clobber the cc's.  */
-      else if (GET_CODE (SET_SRC (exp)) == CALL)
-	{
-	  CC_STATUS_INIT;
-	  return;
-	}
-
-      /* Tests and compares set the cc's in predictable ways.  */
-      else if (SET_DEST (exp) == cc0_rtx)
-	{
-	  CC_STATUS_INIT;
-	  cc_status.value1 = SET_SRC (exp);
-	  return;
-	}
-
-      /* Certain instructions effect the condition codes. */
-      else if (GET_MODE (SET_SRC (exp)) == SImode
-	       || GET_MODE (SET_SRC (exp)) == HImode
-	       || GET_MODE (SET_SRC (exp)) == QImode)
-	switch (GET_CODE (SET_SRC (exp)))
-	  {
-	  case ASHIFTRT: case LSHIFTRT: case ASHIFT:
-	    /* Shifts on the 386 don't set the condition codes if the
-	       shift count is zero. */
-	    if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
-	      {
-		CC_STATUS_INIT;
-		break;
-	      }
-
-	    /* We assume that the CONST_INT is non-zero (this rtx would
-	       have been deleted if it were zero. */
-
-	  case PLUS: case MINUS: case NEG:
-	  case AND: case IOR: case XOR:
-	    cc_status.flags = CC_NO_OVERFLOW;
-	    cc_status.value1 = SET_SRC (exp);
-	    cc_status.value2 = SET_DEST (exp);
-	    break;
-
-	    /* This is the bsf pattern used by ffs.  */
-	  case UNSPEC:
-	    if (XINT (SET_SRC (exp), 1) == 5)
-	      {
-		/* Only the Z flag is defined after bsf.  */
-		cc_status.flags
-		  = CC_NOT_POSITIVE | CC_NOT_NEGATIVE | CC_NO_OVERFLOW;
-		cc_status.value1 = XVECEXP (SET_SRC (exp), 0, 0);
-		cc_status.value2 = 0;
-		break;
-	      }
-	    /* FALLTHRU */
-
-	  default:
-	    CC_STATUS_INIT;
-	  }
-      else
-	{
-	  CC_STATUS_INIT;
-	}
-    }
-  else if (GET_CODE (exp) == PARALLEL
-	   && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
-    {
-      if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
-	return;
-      if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
-
-	{
-	  CC_STATUS_INIT;
-          if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
-	    {
-              cc_status.flags |= CC_IN_80387;
-	      if (0 && TARGET_CMOVE && stack_regs_mentioned_p
-		  (XEXP (SET_SRC (XVECEXP (exp, 0, 0)), 1)))
-		cc_status.flags |= CC_FCOMI;
-	    }
-	  else
-	    cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
-	  return;
-	}
-
-      CC_STATUS_INIT;
-    }
-  else
-    {
-      CC_STATUS_INIT;
-    }
-}
-
-/* Split one or more DImode RTL references into pairs of SImode
-   references.  The RTL can be REG, offsettable MEM, integer constant, or
-   CONST_DOUBLE.  "operands" is a pointer to an array of DImode RTL to
-   split and "num" is its length.  lo_half and hi_half are output arrays
-   that parallel "operands". */
-
-void
-split_di (operands, num, lo_half, hi_half)
-     rtx operands[];
-     int num;
-     rtx lo_half[], hi_half[];
-{
-  while (num--)
-    {
-      rtx op = operands[num];
-      if (! reload_completed)
-	{
-	  lo_half[num] = gen_lowpart (SImode, op);
-	  hi_half[num] = gen_highpart (SImode, op);
-	}
-      else if (GET_CODE (op) == REG)
-	{
-	  lo_half[num] = gen_rtx_REG (SImode, REGNO (op));
-	  hi_half[num] = gen_rtx_REG (SImode, REGNO (op) + 1);
-	}
-      else if (CONSTANT_P (op))
-	split_double (op, &lo_half[num], &hi_half[num]);
-      else if (offsettable_memref_p (op))
-	{
-	  rtx lo_addr = XEXP (op, 0);
-	  rtx hi_addr = XEXP (adj_offsettable_operand (op, 4), 0);
-	  lo_half[num] = change_address (op, SImode, lo_addr);
-	  hi_half[num] = change_address (op, SImode, hi_addr);
-	}
-      else
-	abort();
-    }
-}
-
-/* Return 1 if this is a valid binary operation on a 387.
-   OP is the expression matched, and MODE is its mode. */
-
-int
-binary_387_op (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-
-  switch (GET_CODE (op))
-    {
-    case PLUS:
-    case MINUS:
-    case MULT:
-    case DIV:
-      return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
-
-    default:
-      return 0;
-    }
-}
-
-/* Return 1 if this is a valid shift or rotate operation on a 386.
-   OP is the expression matched, and MODE is its mode. */
-
-int
-shift_op (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  rtx operand = XEXP (op, 0);
-
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-
-  if (GET_MODE (operand) != GET_MODE (op)
-      || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
-    return 0;
-
-  return (GET_CODE (op) == ASHIFT
-	  || GET_CODE (op) == ASHIFTRT
-	  || GET_CODE (op) == LSHIFTRT
-	  || GET_CODE (op) == ROTATE
-	  || GET_CODE (op) == ROTATERT);
-}
-
-/* Return 1 if OP is COMPARE rtx with mode VOIDmode.
-   MODE is not used.  */
-
-int
-VOIDmode_compare_op (op, mode)
-    register rtx op;
-    enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
-}
-
-/* Output code to perform a 387 binary operation in INSN, one of PLUS,
-   MINUS, MULT or DIV.  OPERANDS are the insn operands, where operands[3]
-   is the expression of the binary operation.  The output may either be
-   emitted here, or returned to the caller, like all output_* functions.
-
-   There is no guarantee that the operands are the same mode, as they
-   might be within FLOAT or FLOAT_EXTEND expressions. */
-
-char *
-output_387_binary_op (insn, operands)
-     rtx insn;
-     rtx *operands;
-{
-  rtx temp;
-  char *base_op;
-  static char buf[100];
-
-  switch (GET_CODE (operands[3]))
-    {
-    case PLUS:
-      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
-	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
-	base_op = "fiadd";
-      else
-	base_op = "fadd";
-      break;
-
-    case MINUS:
-      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
-	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
-	base_op = "fisub";
-      else
-	base_op = "fsub";
-      break;
-
-    case MULT:
-      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
-	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
-	base_op = "fimul";
-      else
-	base_op = "fmul";
-      break;
-
-    case DIV:
-      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
-	  || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
-	base_op = "fidiv";
-      else
-	base_op = "fdiv";
-      break;
-
-    default:
-      abort ();
-    }
-
-  strcpy (buf, base_op);
-
-  switch (GET_CODE (operands[3]))
-    {
-    case MULT:
-    case PLUS:
-      if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
-	{
-	  temp = operands[2];
-	  operands[2] = operands[1];
-	  operands[1] = temp;
-	}
-
-      if (GET_CODE (operands[2]) == MEM)
-	return strcat (buf, AS1 (%z2,%2));
-
-      if (NON_STACK_REG_P (operands[1]))
-	{
-	  output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
-	  return "";
-	}
-
-      else if (NON_STACK_REG_P (operands[2]))
-	{
-	  output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
-	  return "";
-	}
-
-      if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
-	{
-	  if (STACK_TOP_P (operands[0]))
-	    return strcat (buf, AS2 (p,%0,%2));
-	  else
-	    return strcat (buf, AS2 (p,%2,%0));
-	}
-
-      if (STACK_TOP_P (operands[0]))
-	return strcat (buf, AS2C (%y2,%0));
-      else
-	return strcat (buf, AS2C (%2,%0));
-
-    case MINUS:
-    case DIV:
-      if (GET_CODE (operands[1]) == MEM)
-	return strcat (buf, AS1 (r%z1,%1));
-
-      if (GET_CODE (operands[2]) == MEM)
-	return strcat (buf, AS1 (%z2,%2));
-
-      if (NON_STACK_REG_P (operands[1]))
-	{
-	  output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1)));
-	  return "";
-	}
-
-      else if (NON_STACK_REG_P (operands[2]))
-	{
-	  output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1)));
-	  return "";
-	}
-
-      if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
-	abort ();
-
-      if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
-	{
-	  if (STACK_TOP_P (operands[0]))
-	    return strcat (buf, AS2 (p,%0,%2));
-	  else
-	    return strcat (buf, AS2 (rp,%2,%0));
-	}
-
-      if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-	{
-	  if (STACK_TOP_P (operands[0]))
-	    return strcat (buf, AS2 (rp,%0,%1));
-	  else
-	    return strcat (buf, AS2 (p,%1,%0));
-	}
-
-      if (STACK_TOP_P (operands[0]))
-	{
-	  if (STACK_TOP_P (operands[1]))
-	    return strcat (buf, AS2C (%y2,%0));
-	  else
-	    return strcat (buf, AS2 (r,%y1,%0));
-	}
-      else if (STACK_TOP_P (operands[1]))
-	return strcat (buf, AS2C (%1,%0));
-      else
-	return strcat (buf, AS2 (r,%2,%0));
-
-    default:
-      abort ();
-    }
-}
-
-/* Output code for INSN to convert a float to a signed int.  OPERANDS
-   are the insn operands.  The output may be SFmode or DFmode and the
-   input operand may be SImode or DImode.  As a special case, make sure
-   that the 387 stack top dies if the output mode is DImode, because the
-   hardware requires this.  */
-
-char *
-output_fix_trunc (insn, operands)
-     rtx insn;
-     rtx *operands;
-{
-  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-  rtx xops[2];
-
-  if (! STACK_TOP_P (operands[1]))
-    abort ();
-
-  xops[0] = GEN_INT (12);
-  xops[1] = operands[4];
-
-  output_asm_insn (AS1 (fnstc%W2,%2), operands);
-  output_asm_insn (AS2 (mov%L2,%2,%4), operands);
-  output_asm_insn (AS2 (mov%B1,%0,%h1), xops);
-  output_asm_insn (AS2 (mov%L4,%4,%3), operands);
-  output_asm_insn (AS1 (fldc%W3,%3), operands);
-
-  if (NON_STACK_REG_P (operands[0]))
-    output_to_reg (operands[0], stack_top_dies, operands[3]);
-
-  else if (GET_CODE (operands[0]) == MEM)
-    {
-      if (stack_top_dies)
-	output_asm_insn (AS1 (fistp%z0,%0), operands);
-      else if (GET_MODE (operands[0]) == DImode && ! stack_top_dies)
-	{
-	  /* There is no DImode version of this without a stack pop, so
-	     we must emulate it.  It doesn't matter much what the second
-	     instruction is, because the value being pushed on the FP stack
-	     is not used except for the following stack popping store.
-	     This case can only happen without optimization, so it doesn't
-	     matter that it is inefficient.  */
-	  output_asm_insn (AS1 (fistp%z0,%0), operands);
-	  output_asm_insn (AS1 (fild%z0,%0), operands);
-	}
-      else
-	output_asm_insn (AS1 (fist%z0,%0), operands);
-    }
-  else
-    abort ();
-
-  return AS1 (fldc%W2,%2);
-}
-
-/* Output code for INSN to compare OPERANDS.  The two operands might
-   not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
-   expression.  If the compare is in mode CCFPEQmode, use an opcode that
-   will not fault if a qNaN is present. */
-
-char *
-output_float_compare (insn, operands)
-     rtx insn;
-     rtx *operands;
-{
-  int stack_top_dies;
-  rtx body = XVECEXP (PATTERN (insn), 0, 0);
-  int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
-  rtx tmp;
-
-  if (0 && TARGET_CMOVE && STACK_REG_P (operands[1]))
-    {
-      cc_status.flags |= CC_FCOMI;
-      cc_prev_status.flags &= ~CC_TEST_AX;
-    }
-
-  if (! STACK_TOP_P (operands[0]))
-    {
-      tmp = operands[0];
-      operands[0] = operands[1];
-      operands[1] = tmp;
-      cc_status.flags |= CC_REVERSED;
-    }
-
-  if (! STACK_TOP_P (operands[0]))
-    abort ();
-
-  stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-
-  if (STACK_REG_P (operands[1])
-      && stack_top_dies
-      && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
-      && REGNO (operands[1]) != FIRST_STACK_REG)
-    {
-      /* If both the top of the 387 stack dies, and the other operand
-	 is also a stack register that dies, then this must be a
-	 `fcompp' float compare */
-
-      if (unordered_compare)
-	{
-	  if (cc_status.flags & CC_FCOMI)
-	    {
-	      output_asm_insn (AS2 (fucomip,%y1,%0), operands);
-	      output_asm_insn (AS1 (fstp, %y0), operands);
-	      return "";
-	    }
-	  else
-	    output_asm_insn ("fucompp", operands);
-	}
-      else
-	{
-	  if (cc_status.flags & CC_FCOMI)
-	    {
-	      output_asm_insn (AS2 (fcomip, %y1,%0), operands);
-	      output_asm_insn (AS1 (fstp, %y0), operands);
-	      return "";
-	    }
-	  else
-	    output_asm_insn ("fcompp", operands);
-	}
-    }
-  else
-    {
-      static char buf[100];
-
-      /* Decide if this is the integer or float compare opcode, or the
-	 unordered float compare. */
-
-      if (unordered_compare)
-	strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fucomi" : "fucom");
-      else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT)
-	strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fcomi" : "fcom");
-      else
-	strcpy (buf, "ficom");
-
-      /* Modify the opcode if the 387 stack is to be popped. */
-
-      if (stack_top_dies)
-	strcat (buf, "p");
-
-      if (NON_STACK_REG_P (operands[1]))
-	output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1)));
-      else if (cc_status.flags & CC_FCOMI)
-	{
-	  output_asm_insn (strcat (buf, AS2 (%z1,%y1,%0)), operands);
-	  return "";
-	}
-      else
-        output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
-    }
-
-  /* Now retrieve the condition code. */
-
-  return output_fp_cc0_set (insn);
-}
-
-/* Output opcodes to transfer the results of FP compare or test INSN
-   from the FPU to the CPU flags.  If TARGET_IEEE_FP, ensure that if the
-   result of the compare or test is unordered, no comparison operator
-   succeeds except NE.  Return an output template, if any.  */
-
-char *
-output_fp_cc0_set (insn)
-     rtx insn;
-{
-  rtx xops[3];
-  rtx next;
-  enum rtx_code code;
-
-  xops[0] = gen_rtx_REG (HImode, 0);
-  output_asm_insn (AS1 (fnsts%W0,%0), xops);
-
-  if (! TARGET_IEEE_FP)
-    {
-      if (!(cc_status.flags & CC_REVERSED))
-        {
-          next = next_cc0_user (insn);
-
-          if (GET_CODE (next) == JUMP_INSN
-              && GET_CODE (PATTERN (next)) == SET
-              && SET_DEST (PATTERN (next)) == pc_rtx
-              && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
-	    code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
-          else if (GET_CODE (PATTERN (next)) == SET)
-	    code = GET_CODE (SET_SRC (PATTERN (next)));
-          else
-	    return "sahf";
-
-	  if (code == GT || code == LT || code == EQ || code == NE
-	      || code == LE || code == GE)
-	    {
-	      /* We will test eax directly. */
-              cc_status.flags |= CC_TEST_AX;
-	      return "";
-            }
-        }
-
-      return "sahf";
-    }
-
-  next = next_cc0_user (insn);
-  if (next == NULL_RTX)
-    abort ();
-
-  if (GET_CODE (next) == JUMP_INSN
-      && GET_CODE (PATTERN (next)) == SET
-      && SET_DEST (PATTERN (next)) == pc_rtx
-      && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
-    code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
-  else if (GET_CODE (PATTERN (next)) == SET)
-    {
-      if (GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
-	code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
-      else
-	code = GET_CODE (SET_SRC (PATTERN (next)));
-    }
-
-  else if (GET_CODE (PATTERN (next)) == PARALLEL
-	   && GET_CODE (XVECEXP (PATTERN (next), 0, 0)) == SET)
-    {
-      if (GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0))) == IF_THEN_ELSE)
-	code = GET_CODE (XEXP (SET_SRC (XVECEXP (PATTERN (next), 0, 0)), 0));
-      else
-	code = GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0)));
-    }
-  else
-    abort ();
-
-  xops[0] = gen_rtx_REG (QImode, 0);
-
-  switch (code)
-    {
-    case GT:
-      xops[1] = GEN_INT (0x45);
-      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
-      /* je label */
-      break;
-
-    case LT:
-      xops[1] = GEN_INT (0x45);
-      xops[2] = GEN_INT (0x01);
-      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
-      output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
-      /* je label */
-      break;
-
-    case GE:
-      xops[1] = GEN_INT (0x05);
-      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
-      /* je label */
-      break;
-
-    case LE:
-      xops[1] = GEN_INT (0x45);
-      xops[2] = GEN_INT (0x40);
-      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
-      output_asm_insn (AS1 (dec%B0,%h0), xops);
-      output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
-      /* jb label */
-      break;
-
-    case EQ:
-      xops[1] = GEN_INT (0x45);
-      xops[2] = GEN_INT (0x40);
-      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
-      output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
-      /* je label */
-      break;
-
-    case NE:
-      xops[1] = GEN_INT (0x44);
-      xops[2] = GEN_INT (0x40);
-      output_asm_insn (AS2 (and%B0,%1,%h0), xops);
-      output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
-      /* jne label */
-      break;
-
-    case GTU:
-    case LTU:
-    case GEU:
-    case LEU:
-    default:
-      abort ();
-    }
-
-  return "";
-}
-
-#define MAX_386_STACK_LOCALS 2
-
-static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
-
-/* Define the structure for the machine field in struct function.  */
-struct machine_function
-{
-  rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
-  rtx pic_label_rtx;
-  char pic_label_name[256];
-};
-
-/* Functions to save and restore i386_stack_locals.
-   These will be called, via pointer variables,
-   from push_function_context and pop_function_context.  */
-
-void
-save_386_machine_status (p)
-     struct function *p;
-{
-  p->machine
-    = (struct machine_function *) xmalloc (sizeof (struct machine_function));
-  bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals,
-	 sizeof i386_stack_locals);
-  p->machine->pic_label_rtx = pic_label_rtx;
-  bcopy (pic_label_name, p->machine->pic_label_name, 256);
-}
-
-void
-restore_386_machine_status (p)
-     struct function *p;
-{
-  bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals,
-	 sizeof i386_stack_locals);
-  pic_label_rtx = p->machine->pic_label_rtx;
-  bcopy (p->machine->pic_label_name, pic_label_name, 256);
-  free (p->machine);
-  p->machine = NULL;
-}
-
-/* Clear stack slot assignments remembered from previous functions.
-   This is called from INIT_EXPANDERS once before RTL is emitted for each
-   function.  */
-
-void
-clear_386_stack_locals ()
-{
-  enum machine_mode mode;
-  int n;
-
-  for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
-       mode = (enum machine_mode) ((int) mode + 1))
-    for (n = 0; n < MAX_386_STACK_LOCALS; n++)
-      i386_stack_locals[(int) mode][n] = NULL_RTX;
-
-  pic_label_rtx = NULL_RTX;
-  bzero (pic_label_name, 256);
-  /* Arrange to save and restore i386_stack_locals around nested functions.  */
-  save_machine_status = save_386_machine_status;
-  restore_machine_status = restore_386_machine_status;
-}
-
-/* Return a MEM corresponding to a stack slot with mode MODE.
-   Allocate a new slot if necessary.
-
-   The RTL for a function can have several slots available: N is
-   which slot to use.  */
-
-rtx
-assign_386_stack_local (mode, n)
-     enum machine_mode mode;
-     int n;
-{
-  if (n < 0 || n >= MAX_386_STACK_LOCALS)
-    abort ();
-
-  if (i386_stack_locals[(int) mode][n] == NULL_RTX)
-    i386_stack_locals[(int) mode][n]
-      = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
-
-  return i386_stack_locals[(int) mode][n];
-}
-
-int is_mul(op,mode)
-    register rtx op;
-    enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == MULT);
-}
-
-int is_div(op,mode)
-    register rtx op;
-    enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == DIV);
-}
-
-#ifdef NOTYET
-/* Create a new copy of an rtx.
-   Recursively copies the operands of the rtx,
-   except for those few rtx codes that are sharable.
-   Doesn't share CONST  */
-
-rtx
-copy_all_rtx (orig)
-     register rtx orig;
-{
-  register rtx copy;
-  register int i, j;
-  register RTX_CODE code;
-  register char *format_ptr;
-
-  code = GET_CODE (orig);
-
-  switch (code)
-    {
-    case REG:
-    case QUEUED:
-    case CONST_INT:
-    case CONST_DOUBLE:
-    case SYMBOL_REF:
-    case CODE_LABEL:
-    case PC:
-    case CC0:
-    case SCRATCH:
-      /* SCRATCH must be shared because they represent distinct values. */
-      return orig;
-
-#if 0
-    case CONST:
-      /* CONST can be shared if it contains a SYMBOL_REF.  If it contains
-	 a LABEL_REF, it isn't sharable.  */
-      if (GET_CODE (XEXP (orig, 0)) == PLUS
-	  && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
-	  && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT)
-	return orig;
-      break;
-#endif
-      /* A MEM with a constant address is not sharable.  The problem is that
-	 the constant address may need to be reloaded.  If the mem is shared,
-	 then reloading one copy of this mem will cause all copies to appear
-	 to have been reloaded.  */
-    }
-
-  copy = rtx_alloc (code);
-  PUT_MODE (copy, GET_MODE (orig));
-  copy->in_struct = orig->in_struct;
-  copy->volatil = orig->volatil;
-  copy->unchanging = orig->unchanging;
-  copy->integrated = orig->integrated;
-  /* intel1 */
-  copy->is_spill_rtx = orig->is_spill_rtx;
-
-  format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
-
-  for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
-    {
-      switch (*format_ptr++)
-	{
-	case 'e':
-	  XEXP (copy, i) = XEXP (orig, i);
-	  if (XEXP (orig, i) != NULL)
-	    XEXP (copy, i) = copy_rtx (XEXP (orig, i));
-	  break;
-
-	case '0':
-	case 'u':
-	  XEXP (copy, i) = XEXP (orig, i);
-	  break;
-
-	case 'E':
-	case 'V':
-	  XVEC (copy, i) = XVEC (orig, i);
-	  if (XVEC (orig, i) != NULL)
-	    {
-	      XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
-	      for (j = 0; j < XVECLEN (copy, i); j++)
-		XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j));
-	    }
-	  break;
-
-	case 'w':
-	  XWINT (copy, i) = XWINT (orig, i);
-	  break;
-
-	case 'i':
-	  XINT (copy, i) = XINT (orig, i);
-	  break;
-
-	case 's':
-	case 'S':
-	  XSTR (copy, i) = XSTR (orig, i);
-	  break;
-
-	default:
-	  abort ();
-	}
-    }
-  return copy;
-}
-
-
-/* Try to rewrite a memory address to make it valid */
-
-void
-rewrite_address (mem_rtx)
-     rtx mem_rtx;
-{
-  rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx;
-  int scale = 1;
-  int offset_adjust = 0;
-  int was_only_offset = 0;
-  rtx mem_addr = XEXP (mem_rtx, 0);
-  char *storage = oballoc (0);
-  int in_struct = 0;
-  int is_spill_rtx = 0;
-
-  in_struct = MEM_IN_STRUCT_P (mem_rtx);
-  is_spill_rtx = RTX_IS_SPILL_P (mem_rtx);
-
-  if (GET_CODE (mem_addr) == PLUS
-      && GET_CODE (XEXP (mem_addr, 1)) == PLUS
-      && GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG)
-    {
-      /* This part is utilized by the combiner. */
-      ret_rtx
-	= gen_rtx (PLUS, GET_MODE (mem_addr),
-		   gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)),
-			    XEXP (mem_addr, 0), XEXP (XEXP (mem_addr, 1), 0)),
-		   XEXP (XEXP (mem_addr, 1), 1));
-
-      if (memory_address_p (GET_MODE (mem_rtx), ret_rtx))
-	{
-	  XEXP (mem_rtx, 0) = ret_rtx;
-	  RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx;
-	  return;
-	}
-
-      obfree (storage);
-    }
-
-  /* This part is utilized by loop.c.
-     If the address contains PLUS (reg,const) and this pattern is invalid
-     in this case - try to rewrite the address to make it valid. */
-  storage = oballoc (0);
-  index_rtx = base_rtx = offset_rtx = NULL;
-
-  /* Find the base index and offset elements of the memory address. */
-  if (GET_CODE (mem_addr) == PLUS)
-    {
-      if (GET_CODE (XEXP (mem_addr, 0)) == REG)
-	{
-	  if (GET_CODE (XEXP (mem_addr, 1)) == REG)
-	    base_rtx = XEXP (mem_addr, 1), index_rtx = XEXP (mem_addr, 0);
-	  else
-	    base_rtx = XEXP (mem_addr, 0), offset_rtx = XEXP (mem_addr, 1);
-	}
-
-      else if (GET_CODE (XEXP (mem_addr, 0)) == MULT)
-	{
-	  index_rtx = XEXP (mem_addr, 0);
-	  if (GET_CODE (XEXP (mem_addr, 1)) == REG)
-	    base_rtx = XEXP (mem_addr, 1);
-	  else
-	    offset_rtx = XEXP (mem_addr, 1);
-	}
-
-      else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS)
-	{
-	  if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS
-	      && GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT
-	      && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0))
-		  == REG)
-	      && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1))
-		  == CONST_INT)
-	      && (GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1))
-		  == CONST_INT)
-	      && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG
-	      && GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF)
-	    {
-	      index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0);
-	      offset_rtx = XEXP (mem_addr, 1);
-	      base_rtx = XEXP (XEXP (mem_addr, 0), 1);
-	      offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1));
-	    }
-	  else
-	    {
-	      offset_rtx = XEXP (mem_addr, 1);
-	      index_rtx = XEXP (XEXP (mem_addr, 0), 0);
-	      base_rtx = XEXP (XEXP (mem_addr, 0), 1);
-	    }
-	}
-
-      else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT)
-	{
-	  was_only_offset = 1;
-	  index_rtx = NULL;
-	  base_rtx = NULL;
-	  offset_rtx = XEXP (mem_addr, 1);
-	  offset_adjust = INTVAL (XEXP (mem_addr, 0));
-	  if (offset_adjust == 0)
-	    {
-	      XEXP (mem_rtx, 0) = offset_rtx;
-	      RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
-	      return;
-	    }
-	}
-      else
-	{
-	  obfree (storage);
-	  return;
-	}
-    }
-  else if (GET_CODE (mem_addr) == MULT)
-    index_rtx = mem_addr;
-  else
-    {
-      obfree (storage);
-      return;
-    }
-
-  if (index_rtx != 0 && GET_CODE (index_rtx) == MULT)
-    {
-      if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT)
-	{
-	  obfree (storage);
-	  return;
-	}
-
-      scale_rtx = XEXP (index_rtx, 1);
-      scale = INTVAL (scale_rtx);
-      index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
-    }
-
-  /* Now find which of the elements are invalid and try to fix them. */
-  if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL)
-    {
-      offset_adjust = INTVAL (index_rtx) * scale;
-
-      if (offset_rtx != 0 && CONSTANT_P (offset_rtx))
-	offset_rtx = plus_constant (offset_rtx, offset_adjust);
-      else if (offset_rtx == 0)
-	offset_rtx = const0_rtx;
-
-      RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
-      XEXP (mem_rtx, 0) = offset_rtx;
-      return;
-    }
-
-  if (base_rtx && GET_CODE (base_rtx) == PLUS
-      && GET_CODE (XEXP (base_rtx, 0)) == REG
-      && GET_CODE (XEXP (base_rtx, 1)) == CONST_INT)
-    {
-      offset_adjust += INTVAL (XEXP (base_rtx, 1));
-      base_rtx = copy_all_rtx (XEXP (base_rtx, 0));
-    }
-
-  else if (base_rtx && GET_CODE (base_rtx) == CONST_INT)
-    {
-      offset_adjust += INTVAL (base_rtx);
-      base_rtx = NULL;
-    }
-
-  if (index_rtx && GET_CODE (index_rtx) == PLUS
-      && GET_CODE (XEXP (index_rtx, 0)) == REG
-      && GET_CODE (XEXP (index_rtx, 1)) == CONST_INT)
-    {
-      offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale;
-      index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
-    }
-
-  if (index_rtx)
-    {
-      if (! LEGITIMATE_INDEX_P (index_rtx)
-	  && ! (index_rtx == stack_pointer_rtx && scale == 1
-		&& base_rtx == NULL))
-	{
-	  obfree (storage);
-	  return;
-	}
-    }
-
-  if (base_rtx)
-    {
-      if (! LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG)
-	{
-	  obfree (storage);
-	  return;
-	}
-    }
-
-  if (offset_adjust != 0)
-    {
-      if (offset_rtx != 0 && CONSTANT_P (offset_rtx))
-	offset_rtx = plus_constant (offset_rtx, offset_adjust);
-      else
-	offset_rtx = const0_rtx;
-
-      if (index_rtx)
-	{
-	  if (base_rtx)
-	    {
-	      if (scale != 1)
-		{
-		  ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx),
-				     gen_rtx (MULT, GET_MODE (index_rtx),
-					      index_rtx, scale_rtx),
-				     base_rtx);
-
-		  if (GET_CODE (offset_rtx) != CONST_INT
-		      || INTVAL (offset_rtx) != 0)
-		    ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
-				       ret_rtx, offset_rtx);
-		}
-	      else
-		{
-		  ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx),
-				     index_rtx, base_rtx);
-
-		  if (GET_CODE (offset_rtx) != CONST_INT
-		      || INTVAL (offset_rtx) != 0)
-		    ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
-				       ret_rtx, offset_rtx);
-		}
-	    }
-	  else
-	    {
-	      if (scale != 1)
-		{
-		  ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx),
-				     index_rtx, scale_rtx);
-
-		  if (GET_CODE (offset_rtx) != CONST_INT
-		      || INTVAL (offset_rtx) != 0)
-		    ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
-				       ret_rtx, offset_rtx);
-		}
-	      else
-		{
-		  if (GET_CODE (offset_rtx) == CONST_INT
-		      && INTVAL (offset_rtx) == 0)
-		    ret_rtx = index_rtx;
-		  else
-		    ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx),
-				       index_rtx, offset_rtx);
-		}
-	    }
-	}
-      else
-	{
-	  if (base_rtx)
-	    {
-	      if (GET_CODE (offset_rtx) == CONST_INT
-		  && INTVAL (offset_rtx) == 0)
-		ret_rtx = base_rtx;
-	      else
-		ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx,
-				   offset_rtx);
-	    }
-	  else if (was_only_offset)
-	    ret_rtx = offset_rtx;
-	  else
-	    {
-	      obfree (storage);
-	      return;
-	    }
-	}
-
-      XEXP (mem_rtx, 0) = ret_rtx;
-      RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
-      return;
-    }
-  else
-    {
-      obfree (storage);
-      return;
-    }
-}
-#endif /* NOTYET */
-
-/* Return 1 if the first insn to set cc before INSN also sets the register
-   REG_RTX; otherwise return 0. */
-int
-last_to_set_cc (reg_rtx, insn)
-     rtx reg_rtx, insn;
-{
-  rtx prev_insn = PREV_INSN (insn);
-
-  while (prev_insn)
-    {
-      if (GET_CODE (prev_insn) == NOTE)
-	;
-
-      else if (GET_CODE (prev_insn) == INSN)
-	{
-	  if (GET_CODE (PATTERN (prev_insn)) != SET)
-	    return (0);
-
-	  if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx))
-	    {
-	      if (sets_condition_code (SET_SRC (PATTERN (prev_insn))))
-		return (1);
-
-	      return (0);
-	    }
-
-	  else if (! doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn))))
-	    return (0);
-	}
-
-      else
-	return (0);
-
-      prev_insn = PREV_INSN (prev_insn);
-    }
-
-  return (0);
-}
-
-int
-doesnt_set_condition_code (pat)
-     rtx pat;
-{
-  switch (GET_CODE (pat))
-    {
-    case MEM:
-    case REG:
-      return 1;
-
-    default:
-      return 0;
-
-    }
-}
-
-int
-sets_condition_code (pat)
-     rtx pat;
-{
-  switch (GET_CODE (pat))
-    {
-    case PLUS:
-    case MINUS:
-    case AND:
-    case IOR:
-    case XOR:
-    case NOT:
-    case NEG:
-    case MULT:
-    case DIV:
-    case MOD:
-    case UDIV:
-    case UMOD:
-      return 1;
-
-    default:
-      return (0);
-    }
-}
-
-int
-str_immediate_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0)
-    return 1;
-
-  return 0;
-}
-
-int
-is_fp_insn (insn)
-     rtx insn;
-{
-  if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
-      && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
-	  || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
-	  || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode))
-    return 1;
-
-  return 0;
-}
-
-/* Return 1 if the mode of the SET_DEST of insn is floating point
-   and it is not an fld or a move from memory to memory.
-   Otherwise return 0 */
-
-int
-is_fp_dest (insn)
-     rtx insn;
-{
-  if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
-      && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
-	  || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
-	  || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
-      && GET_CODE (SET_DEST (PATTERN (insn))) == REG
-      && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG
-      && GET_CODE (SET_SRC (PATTERN (insn))) != MEM)
-    return 1;
-
-  return 0;
-}
-
-/* Return 1 if the mode of the SET_DEST of INSN is floating point and is
-   memory and the source is a register.  */
-
-int
-is_fp_store (insn)
-     rtx insn;
-{
-  if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
-      && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
-	  || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
-	  || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
-      && GET_CODE (SET_DEST (PATTERN (insn))) == MEM
-      && GET_CODE (SET_SRC (PATTERN (insn))) == REG)
-    return 1;
-
-  return 0;
-}
-
-/* Return 1 if DEP_INSN sets a register which INSN uses as a base
-   or index to reference memory.
-   otherwise return 0 */
-
-int
-agi_dependent (insn, dep_insn)
-     rtx insn, dep_insn;
-{
-  if (GET_CODE (dep_insn) == INSN
-      && GET_CODE (PATTERN (dep_insn)) == SET
-      && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG)
-    return reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn);
-
-  if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET
-      && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM
-      && push_operand (SET_DEST (PATTERN (dep_insn)),
-                       GET_MODE (SET_DEST (PATTERN (dep_insn)))))
-    return reg_mentioned_in_mem (stack_pointer_rtx, insn);
-
-  return 0;
-}
-
-/* Return 1 if reg is used in rtl as a base or index for a memory ref
-   otherwise return 0. */
-
-int
-reg_mentioned_in_mem (reg, rtl)
-     rtx reg, rtl;
-{
-  register char *fmt;
-  register int i, j;
-  register enum rtx_code code;
-
-  if (rtl == NULL)
-    return 0;
-
-  code = GET_CODE (rtl);
-
-  switch (code)
-    {
-    case HIGH:
-    case CONST_INT:
-    case CONST:
-    case CONST_DOUBLE:
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case PC:
-    case CC0:
-    case SUBREG:
-      return 0;
-    default:
-      break;
-    }
-
-  if (code == MEM && reg_mentioned_p (reg, rtl))
-    return 1;
-
-  fmt = GET_RTX_FORMAT (code);
-  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
-    {
-      if (fmt[i] == 'E')
-	{
-	  for (j = XVECLEN (rtl, i) - 1; j >= 0; j--)
-	    if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j)))
-	      return 1;
-	}
-
-      else if (fmt[i] == 'e' && reg_mentioned_in_mem (reg, XEXP (rtl, i)))
-	return 1;
-    }
-
-  return 0;
-}
-
-/* Output the appropriate insns for doing strlen if not just doing repnz; scasb
-
-   operands[0] = result, initialized with the startaddress
-   operands[1] = alignment of the address.
-   operands[2] = scratch register, initialized with the startaddress when
-   		 not aligned, otherwise undefined
-
-   This is just the body. It needs the initialisations mentioned above and
-   some address computing at the end.  These things are done in i386.md.  */
-
-char *
-output_strlen_unroll (operands)
-     rtx operands[];
-{
-  rtx xops[18];
-
-  xops[0] = operands[0];		/* Result */
-  /*        operands[1];                 * Alignment */
-  xops[1] = operands[2];		/* Scratch */
-  xops[2] = GEN_INT (0);
-  xops[3] = GEN_INT (2);
-  xops[4] = GEN_INT (3);
-  xops[5] = GEN_INT (4);
-  /* xops[6] = gen_label_rtx ();	 * label when aligned to 3-byte */
-  /* xops[7] = gen_label_rtx ();	 * label when aligned to 2-byte */
-  xops[8] = gen_label_rtx ();		/* label of main loop */
-
-  if (TARGET_USE_Q_REG && QI_REG_P (xops[1]))
-    xops[9] = gen_label_rtx ();		/* pentium optimisation */
-
-  xops[10] = gen_label_rtx ();		/* end label 2 */
-  xops[11] = gen_label_rtx ();		/* end label 1 */
-  xops[12] = gen_label_rtx ();		/* end label */
-  /* xops[13]				 * Temporary used */
-  xops[14] = GEN_INT (0xff);
-  xops[15] = GEN_INT (0xff00);
-  xops[16] = GEN_INT (0xff0000);
-  xops[17] = GEN_INT (0xff000000);
-
-  /* Loop to check 1..3 bytes for null to get an aligned pointer.  */
-
-  /* Is there a known alignment and is it less than 4?  */
-  if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) < 4)
-    {
-      /* Is there a known alignment and is it not 2? */
-      if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
-	{
-	  xops[6] = gen_label_rtx (); /* Label when aligned to 3-byte */
-	  xops[7] = gen_label_rtx (); /* Label when aligned to 2-byte */
-
-	  /* Leave just the 3 lower bits.
-	     If this is a q-register, then the high part is used later
-	     therefore use andl rather than andb. */
-	  output_asm_insn (AS2 (and%L1,%4,%1), xops);
-
-	  /* Is aligned to 4-byte address when zero */
-	  output_asm_insn (AS1 (je,%l8), xops);
-
-	  /* Side-effect even Parity when %eax == 3 */
-	  output_asm_insn (AS1 (jp,%6), xops);
-
-	  /* Is it aligned to 2 bytes ? */
-	  if (QI_REG_P (xops[1]))
-	    output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
-	  else
-	    output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
-
-	  output_asm_insn (AS1 (je,%7), xops);
-	}
-      else
-        {
-	  /* Since the alignment is 2, we have to check 2 or 0 bytes;
-	     check if is aligned to 4 - byte.  */
-	  output_asm_insn (AS2 (and%L1,%3,%1), xops);
-
-	  /* Is aligned to 4-byte address when zero */
-	  output_asm_insn (AS1 (je,%l8), xops);
-        }
-
-      xops[13] = gen_rtx_MEM (QImode, xops[0]);
-
-      /* Now compare the bytes; compare with the high part of a q-reg
-	 gives shorter code. */
-      if (QI_REG_P (xops[1]))
-        {
-	  /* Compare the first n unaligned byte on a byte per byte basis. */
-          output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
-
-	  /* When zero we reached the end. */
-          output_asm_insn (AS1 (je,%l12), xops);
-
-	  /* Increment the address. */
-          output_asm_insn (AS1 (inc%L0,%0), xops);
-
-	  /* Not needed with an alignment of 2 */
-	  if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
-	    {
-	      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-					 CODE_LABEL_NUMBER (xops[7]));
-	      output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
-	      output_asm_insn (AS1 (je,%l12), xops);
-	      output_asm_insn (AS1 (inc%L0,%0), xops);
-
-	      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-					 CODE_LABEL_NUMBER (xops[6]));
-	    }
-
-          output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
-        }
-      else
-        {
-          output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
-          output_asm_insn (AS1 (je,%l12), xops);
-          output_asm_insn (AS1 (inc%L0,%0), xops);
-
-	  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				     CODE_LABEL_NUMBER (xops[7]));
-          output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
-          output_asm_insn (AS1 (je,%l12), xops);
-          output_asm_insn (AS1 (inc%L0,%0), xops);
-
-	  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				     CODE_LABEL_NUMBER (xops[6]));
-          output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
-        }
-
-      output_asm_insn (AS1 (je,%l12), xops);
-      output_asm_insn (AS1 (inc%L0,%0), xops);
-    }
-
-    /* Generate loop to check 4 bytes at a time.  It is not a good idea to
-       align this loop.  It gives only huge programs, but does not help to
-       speed up.  */
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[8]));
-
-  xops[13] = gen_rtx_MEM (SImode, xops[0]);
-  output_asm_insn (AS2 (mov%L1,%13,%1), xops);
-
-  if (QI_REG_P (xops[1]))
-    {
-      /* On i586 it is faster to combine the hi- and lo- part as
-	 a kind of lookahead.  If anding both yields zero, then one
-	 of both *could* be zero, otherwise none of both is zero;
-	 this saves one instruction, on i486 this is slower
-	 tested with P-90, i486DX2-66, AMD486DX2-66  */
-      if (TARGET_PENTIUM)
-        {
-	  output_asm_insn (AS2 (test%B1,%h1,%b1), xops);
-	  output_asm_insn (AS1 (jne,%l9), xops);
-        }
-
-      /* Check first byte. */
-      output_asm_insn (AS2 (test%B1,%b1,%b1), xops);
-      output_asm_insn (AS1 (je,%l12), xops);
-
-      /* Check second byte. */
-      output_asm_insn (AS2 (test%B1,%h1,%h1), xops);
-      output_asm_insn (AS1 (je,%l11), xops);
-
-      if (TARGET_PENTIUM)
-	ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				   CODE_LABEL_NUMBER (xops[9]));
-    }
-
-  else
-    {
-      /* Check first byte. */
-      output_asm_insn (AS2 (test%L1,%14,%1), xops);
-      output_asm_insn (AS1 (je,%l12), xops);
-
-      /* Check second byte. */
-      output_asm_insn (AS2 (test%L1,%15,%1), xops);
-      output_asm_insn (AS1 (je,%l11), xops);
-    }
-
-  /* Check third byte. */
-  output_asm_insn (AS2 (test%L1,%16,%1), xops);
-  output_asm_insn (AS1 (je,%l10), xops);
-
-  /* Check fourth byte and increment address. */
-  output_asm_insn (AS2 (add%L0,%5,%0), xops);
-  output_asm_insn (AS2 (test%L1,%17,%1), xops);
-  output_asm_insn (AS1 (jne,%l8), xops);
-
-  /* Now generate fixups when the compare stops within a 4-byte word. */
-  output_asm_insn (AS2 (sub%L0,%4,%0), xops);
-
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[10]));
-  output_asm_insn (AS1 (inc%L0,%0), xops);
-
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[11]));
-  output_asm_insn (AS1 (inc%L0,%0), xops);
-
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[12]));
-
-  return "";
-}
-
-char *
-output_fp_conditional_move (which_alternative, operands)
-     int which_alternative;
-     rtx operands[];
-{
-  switch (which_alternative)
-    {
-    case 0:
-      /* r <- cond ? arg : r */
-      output_asm_insn (AS2 (fcmov%F1,%2,%0), operands);
-      break;
-
-    case 1:
-      /* r <- cond ? r : arg */
-      output_asm_insn (AS2 (fcmov%f1,%3,%0), operands);
-      break;
-
-    case 2:
-      /* r <- cond ? r : arg */
-      output_asm_insn (AS2 (fcmov%F1,%2,%0), operands);
-      output_asm_insn (AS2 (fcmov%f1,%3,%0), operands);
-      break;
-
-    default:
-      abort ();
-    }
-
-  return "";
-}
-
-char *
-output_int_conditional_move (which_alternative, operands)
-     int which_alternative;
-     rtx operands[];
-{
-  int code = GET_CODE (operands[1]);
-  enum machine_mode mode;
-  rtx xops[4];
-
-  /* This is very tricky. We have to do it right. For a code segement
-     like:
-
-	int foo, bar;
-	....
-	foo = foo - x;
-	if (foo >= 0)
-	  bar = y;
-
-     final_scan_insn () may delete the insn which sets CC. We have to
-     tell final_scan_insn () if it should be reinserted. When CODE is
-     GT or LE, we have to check the CC_NO_OVERFLOW bit and return
-     NULL_PTR to tell final to reinsert the test insn because the
-     conditional move cannot be handled properly without it. */
-  if ((code == GT || code == LE)
-      && (cc_prev_status.flags & CC_NO_OVERFLOW))
-    return NULL_PTR;
-
-  mode = GET_MODE (operands [0]);
-  if (mode == DImode)
-    {
-      xops [0] = gen_rtx_SUBREG (SImode, operands [0], 1);
-      xops [1] = operands [1];
-      xops [2] = gen_rtx_SUBREG (SImode, operands [2], 1);
-      xops [3] = gen_rtx_SUBREG (SImode, operands [3], 1);
-    }
-
-  switch (which_alternative)
-    {
-    case 0:
-      /* r <- cond ? arg : r */
-      output_asm_insn (AS2 (cmov%C1,%2,%0), operands);
-      if (mode == DImode)
-	output_asm_insn (AS2 (cmov%C1,%2,%0), xops);
-      break;
-
-    case 1:
-      /* r <- cond ? r : arg */
-      output_asm_insn (AS2 (cmov%c1,%3,%0), operands);
-      if (mode == DImode)
-	output_asm_insn (AS2 (cmov%c1,%3,%0), xops);
-      break;
-
-    case 2:
-      /* rm <- cond ? arg1 : arg2 */
-      output_asm_insn (AS2 (cmov%C1,%2,%0), operands);
-      output_asm_insn (AS2 (cmov%c1,%3,%0), operands);
-      if (mode == DImode)
-	{
-	  output_asm_insn (AS2 (cmov%C1,%2,%0), xops);
-	  output_asm_insn (AS2 (cmov%c1,%3,%0), xops);
-	}
-      break;
-
-    default:
-      abort ();
-    }
-
-  return "";
-}
-
-int
-x86_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn, link, dep_insn;
-     int cost;
-{
-  rtx next_inst;
-
-  if (GET_CODE (dep_insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
-    return 0;
-
-  if (GET_CODE (dep_insn) == INSN
-      && GET_CODE (PATTERN (dep_insn)) == SET
-      && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG
-      && GET_CODE (insn) == INSN
-      && GET_CODE (PATTERN (insn)) == SET
-      && !reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
-				   SET_SRC (PATTERN (insn))))
-    return 0;	/* ??? */
-
-
-  switch (ix86_cpu)
-    {
-    case PROCESSOR_PENTIUM:
-      if (cost != 0 && is_fp_insn (insn) && is_fp_insn (dep_insn)
-	  && !is_fp_dest (dep_insn))
-	return 0;
-
-      if (agi_dependent (insn, dep_insn))
-	return 3;
-
-      if (GET_CODE (insn) == INSN
-	  && GET_CODE (PATTERN (insn)) == SET
-	  && SET_DEST (PATTERN (insn)) == cc0_rtx
-	  && (next_inst = next_nonnote_insn (insn))
-	  && GET_CODE (next_inst) == JUMP_INSN)
-	/* compare probably paired with jump */
-	return 0;
-      break;
-
-    case PROCESSOR_K6:
-    default:
-      if (!is_fp_dest (dep_insn))
-	{
-	  if(!agi_dependent (insn, dep_insn))
-	    return 0;
-	  if (TARGET_486)
-	    return 2;
-	}
-      else
-	if (is_fp_store (insn) && is_fp_insn (dep_insn)
-	    && NEXT_INSN (insn) && NEXT_INSN (NEXT_INSN (insn))
-	    && NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))
-	    && (GET_CODE (NEXT_INSN (insn)) == INSN)
-	    && (GET_CODE (NEXT_INSN (NEXT_INSN (insn))) == JUMP_INSN)
-	    && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) == NOTE)
-	    && (NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn))))
-		== NOTE_INSN_LOOP_END))
-	  return 3;
-      break;
-    }
-
-  return cost;
-}
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
deleted file mode 100755
index 9e1150b..0000000
--- a/gcc/config/i386/i386.h
+++ /dev/null
@@ -1,2760 +0,0 @@
-/* Definitions of target machine for GNU compiler for Intel X86
-   (386, 486, Pentium).
-   Copyright (C) 1988, 92, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* The purpose of this file is to define the characteristics of the i386,
-   independent of assembler syntax or operating system.
-
-   Three other files build on this one to describe a specific assembler syntax:
-   bsd386.h, att386.h, and sun386.h.
-
-   The actual tm.h file for a particular system should include
-   this file, and then the file for the appropriate assembler syntax.
-
-   Many macros that specify assembler syntax are omitted entirely from
-   this file because they really belong in the files for particular
-   assemblers.  These include AS1, AS2, AS3, RP, IP, LPREFIX, L_SIZE,
-   PUT_OP_SIZE, USE_STAR, ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE,
-   PRINT_B_I_S, and many that start with ASM_ or end in ASM_OP.  */
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define I386 1
-
-/* Stubs for half-pic support if not OSF/1 reference platform.  */
-
-#ifndef HALF_PIC_P
-#define HALF_PIC_P() 0
-#define HALF_PIC_NUMBER_PTRS 0
-#define HALF_PIC_NUMBER_REFS 0
-#define HALF_PIC_ENCODE(DECL)
-#define HALF_PIC_DECLARE(NAME)
-#define HALF_PIC_INIT()	error ("half-pic init called on systems that don't support it.")
-#define HALF_PIC_ADDRESS_P(X) 0
-#define HALF_PIC_PTR(X) X
-#define HALF_PIC_FINISH(STREAM)
-#endif
-
-/* Define the specific costs for a given cpu */
-
-struct processor_costs {
-  int add;			/* cost of an add instruction */
-  int lea;			/* cost of a lea instruction */
-  int shift_var;		/* variable shift costs */
-  int shift_const;		/* constant shift costs */
-  int mult_init;		/* cost of starting a multiply */
-  int mult_bit;			/* cost of multiply per each bit set */
-  int divide;			/* cost of a divide/mod */
-};
-
-extern struct processor_costs *ix86_cost;
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* configure can arrange to make this 2, to force a 486.  */
-#ifndef TARGET_CPU_DEFAULT
-#define TARGET_CPU_DEFAULT 0
-#endif
-
-/* Masks for the -m switches */
-#define MASK_80387		000000000001	/* Hardware floating point */
-#define MASK_NOTUSED1		000000000002	/* bit not currently used */
-#define MASK_NOTUSED2		000000000004	/* bit not currently used */
-#define MASK_RTD		000000000010	/* Use ret that pops args */
-#define MASK_ALIGN_DOUBLE	000000000020	/* align doubles to 2 word boundary */
-#define MASK_SVR3_SHLIB		000000000040	/* Uninit locals into bss */
-#define MASK_IEEE_FP		000000000100	/* IEEE fp comparisons */
-#define MASK_FLOAT_RETURNS	000000000200	/* Return float in st(0) */
-#define MASK_NO_FANCY_MATH_387	000000000400	/* Disable sin, cos, sqrt */
-#define MASK_OMIT_LEAF_FRAME_POINTER 0x00000800 /* omit leaf frame pointers */
-						/* Temporary codegen switches */
-#define MASK_DEBUG_ADDR		000001000000	/* Debug GO_IF_LEGITIMATE_ADDRESS */
-#define MASK_NO_WIDE_MULTIPLY	000002000000	/* Disable 32x32->64 multiplies */
-#define MASK_NO_MOVE		000004000000	/* Don't generate mem->mem */
-#define MASK_NO_PSEUDO		000010000000	/* Move op's args -> pseudos */
-#define MASK_DEBUG_ARG		000020000000	/* Debug function_arg */   
-#define MASK_SCHEDULE_PROLOGUE  000040000000    /* Emit prologue as rtl */
-#define MASK_STACK_PROBE	000100000000	/* Enable stack probing */
-
-/* Use the floating point instructions */
-#define TARGET_80387 (target_flags & MASK_80387)
-
-/* Compile using ret insn that pops args.
-   This will not work unless you use prototypes at least
-   for all functions that can take varying numbers of args.  */  
-#define TARGET_RTD (target_flags & MASK_RTD)
-
-/* Align doubles to a two word boundary.  This breaks compatibility with
-   the published ABI's for structures containing doubles, but produces
-   faster code on the pentium.  */
-#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
-
-/* Put uninitialized locals into bss, not data.
-   Meaningful only on svr3.  */
-#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
-
-/* Use IEEE floating point comparisons.  These handle correctly the cases
-   where the result of a comparison is unordered.  Normally SIGFPE is
-   generated in such cases, in which case this isn't needed.  */
-#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
-
-/* Functions that return a floating point value may return that value
-   in the 387 FPU or in 386 integer registers.  If set, this flag causes
-   the 387 to be used, which is compatible with most calling conventions. */
-#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
-
-/* Disable generation of FP sin, cos and sqrt operations for 387.
-   This is because FreeBSD lacks these in the math-emulator-code */
-#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
-
-/* Don't create frame pointers for leaf functions */
-#define TARGET_OMIT_LEAF_FRAME_POINTER (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
-
-/* Temporary switches for tuning code generation */
-
-/* Disable 32x32->64 bit multiplies that are used for long long multiplies
-   and division by constants, but sometimes cause reload problems.  */
-#define TARGET_NO_WIDE_MULTIPLY (target_flags & MASK_NO_WIDE_MULTIPLY)
-#define TARGET_WIDE_MULTIPLY (!TARGET_NO_WIDE_MULTIPLY)
-
-/* Emit/Don't emit prologue as rtl */
-#define TARGET_SCHEDULE_PROLOGUE (target_flags & MASK_SCHEDULE_PROLOGUE)
-
-/* Debug GO_IF_LEGITIMATE_ADDRESS */
-#define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR)
-
-/* Debug FUNCTION_ARG macros */
-#define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
-
-/* Hack macros for tuning code generation */
-#define TARGET_MOVE	((target_flags & MASK_NO_MOVE) == 0)	/* Don't generate memory->memory */
-#define TARGET_PSEUDO	((target_flags & MASK_NO_PSEUDO) == 0)	/* Move op's args into pseudos */
-
-#define TARGET_386 (ix86_cpu == PROCESSOR_I386)
-#define TARGET_486 (ix86_cpu == PROCESSOR_I486)
-#define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
-#define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
-#define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
-
-#define CPUMASK (1 << ix86_cpu)
-extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
-extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
-extern const int x86_unroll_strlen, x86_use_q_reg, x86_use_any_reg;
-extern const int x86_double_with_add;
-
-#define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
-#define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
-#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
-#define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
-#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
-#define TARGET_USE_Q_REG (x86_use_q_reg & CPUMASK)
-#define TARGET_USE_ANY_REG (x86_use_any_reg & CPUMASK)
-#define TARGET_CMOVE (x86_cmove & (1 << ix86_arch))
-#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
-#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
-
-#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
-
-#define TARGET_SWITCHES							\
-{ { "80387",			 MASK_80387, "Use hardware fp" },	\
-  { "no-80387",			-MASK_80387, "Do not use hardware fp" },\
-  { "hard-float",		 MASK_80387, "Use hardware fp" },	\
-  { "soft-float",		-MASK_80387, "Do not use hardware fp" },\
-  { "no-soft-float",		 MASK_80387, "Use hardware fp" },	\
-  { "386",			 0, "Optimize for i80386" },		\
-  { "no-386",			 0, "" },				\
-  { "486",			 0, "Optimize for i80486" },		\
-  { "no-486",			 0, "" },				\
-  { "pentium",			 0, "Optimize for Pentium" },		\
-  { "pentiumpro",		 0, "Optimize for Pentium Pro, Pentium II" },\
-  { "rtd",			 MASK_RTD, "Alternate calling convention" },\
-  { "no-rtd",			-MASK_RTD, "Use normal calling convention" },\
-  { "align-double",		 MASK_ALIGN_DOUBLE, "Align some doubles on dword boundary" },\
-  { "no-align-double",		-MASK_ALIGN_DOUBLE, "Align doubles on word boundary" },		\
-  { "svr3-shlib",		 MASK_SVR3_SHLIB, "Uninitialized locals in .bss"  },			\
-  { "no-svr3-shlib",		-MASK_SVR3_SHLIB, "Uninitialized locals in .data" },			\
-  { "ieee-fp",			 MASK_IEEE_FP, "Use IEEE math for fp comparisons" },	\
-  { "no-ieee-fp",		-MASK_IEEE_FP, "Do not use IEEE math for fp comparisons" },			\
-  { "fp-ret-in-387",		 MASK_FLOAT_RETURNS, "Return values of functions in FPU registers" },			\
-  { "no-fp-ret-in-387",		-MASK_FLOAT_RETURNS , "Do not return values of functions in FPU registers"},			\
-  { "no-fancy-math-387",	 MASK_NO_FANCY_MATH_387, "Do not generate sin, cos, sqrt for 387" },		\
-  { "fancy-math-387",		-MASK_NO_FANCY_MATH_387, "Generate sin, cos, sqrt for FPU"},		\
-  { "omit-leaf-frame-pointer",	 MASK_OMIT_LEAF_FRAME_POINTER }, 	\
-  { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER },       \
-  { "no-wide-multiply",		 MASK_NO_WIDE_MULTIPLY, "multiplies of 32 bits constrained to 32 bits" },		\
-  { "wide-multiply",		-MASK_NO_WIDE_MULTIPLY, "multiplies of 32 bits are 64 bits" },		\
-  { "schedule-prologue",	 MASK_SCHEDULE_PROLOGUE },		\
-  { "no-schedule-prologue",	-MASK_SCHEDULE_PROLOGUE },		\
-  { "debug-addr",		 MASK_DEBUG_ADDR },			\
-  { "no-debug-addr",		-MASK_DEBUG_ADDR },			\
-  { "move",			-MASK_NO_MOVE },			\
-  { "no-move",			 MASK_NO_MOVE },			\
-  { "debug-arg",		 MASK_DEBUG_ARG },			\
-  { "no-debug-arg",		-MASK_DEBUG_ARG },			\
-  { "stack-arg-probe",		 MASK_STACK_PROBE },			\
-  { "no-stack-arg-probe",	-MASK_STACK_PROBE },			\
-  { "windows",			0 },					\
-  { "dll",			0 },					\
-  SUBTARGET_SWITCHES							\
-  { "", MASK_SCHEDULE_PROLOGUE | TARGET_DEFAULT}}
-
-/* Which processor to schedule for. The cpu attribute defines a list that
-   mirrors this list, so changes to i386.md must be made at the same time.  */
-
-enum processor_type
- {PROCESSOR_I386,			/* 80386 */
-  PROCESSOR_I486,			/* 80486DX, 80486SX, 80486DX[24] */
-  PROCESSOR_PENTIUM,
-  PROCESSOR_PENTIUMPRO,
-  PROCESSOR_K6};
-
-#define PROCESSOR_I386_STRING "i386"
-#define PROCESSOR_I486_STRING "i486"
-#define PROCESSOR_I586_STRING "i586"
-#define PROCESSOR_PENTIUM_STRING "pentium"
-#define PROCESSOR_I686_STRING "i686"
-#define PROCESSOR_PENTIUMPRO_STRING "pentiumpro"
-#define PROCESSOR_K6_STRING "k6"
-
-extern enum processor_type ix86_cpu;
-
-extern int ix86_arch;
-
-/* Define the default processor.  This is overridden by other tm.h files.  */
-#define PROCESSOR_DEFAULT (enum processor_type) TARGET_CPU_DEFAULT
-#define PROCESSOR_DEFAULT_STRING \
-  (PROCESSOR_DEFAULT == PROCESSOR_I486 ? PROCESSOR_I486_STRING  \
-  : PROCESSOR_DEFAULT == PROCESSOR_PENTIUM ? PROCESSOR_PENTIUM_STRING  \
-  : PROCESSOR_DEFAULT == PROCESSOR_PENTIUMPRO ? PROCESSOR_PENTIUMPRO_STRING  \
-  : PROCESSOR_DEFAULT == PROCESSOR_K6 ? PROCESSOR_K6_STRING  \
-  : PROCESSOR_I386_STRING)
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an
-   initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   fixed part of the option name, and the address of a variable.  The
-   variable, type `char *', is set to the variable part of the given
-   option if the fixed part matches.  The actual option name is made
-   by appending `-m' to the specified name.  */
-#define TARGET_OPTIONS							\
-{ { "cpu=",		&ix86_cpu_string, "Schedule code for given CPU"}, \
-  { "arch=",		&ix86_arch_string, "Generate code for given CPU"}, \
-  { "reg-alloc=",	&i386_reg_alloc_order, "Control allocation order of integer registers" }, \
-  { "regparm=",		&i386_regparm_string, "Number of registers used to pass integer arguments" }, \
-  { "align-loops=",	&i386_align_loops_string, "Loop code aligned to this power of 2" }, \
-  { "align-jumps=",	&i386_align_jumps_string, "Jump targets are aligned to this power of 2" }, \
-  { "align-functions=",	&i386_align_funcs_string, "Function starts are aligned to this power of 2" }, \
-  { "branch-cost=",	&i386_branch_cost_string },			\
-  SUBTARGET_OPTIONS							\
-}
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-
-#define OVERRIDE_OPTIONS override_options ()
-
-/* These are meant to be redefined in the host dependent files */
-#define SUBTARGET_SWITCHES
-#define SUBTARGET_OPTIONS
-
-/* Define this to change the optimizations performed by default.  */
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
-
-/* Specs for the compiler proper */
-
-#ifndef CC1_CPU_SPEC
-#define CC1_CPU_SPEC "\
-%{!mcpu*: \
-%{m386:-mcpu=i386 -march=i386} \
-%{mno-486:-mcpu=i386 -march=i386} \
-%{m486:-mcpu=i486 -march=i486} \
-%{mno-386:-mcpu=i486 -march=i486} \
-%{mno-pentium:-mcpu=i486 -march=i486} \
-%{mpentium:-mcpu=pentium} \
-%{mno-pentiumpro:-mcpu=pentium} \
-%{mpentiumpro:-mcpu=pentiumpro}}"
-#endif
-
-#define CPP_486_SPEC "%{!ansi:-Di486} -D__i486 -D__i486__"
-#define CPP_586_SPEC "%{!ansi:-Di586 -Dpentium} \
-	-D__i586 -D__i586__ -D__pentium -D__pentium__"
-#define CPP_686_SPEC "%{!ansi:-Di686 -Dpentiumpro} \
-	-D__i686 -D__i686__ -D__pentiumpro -D__pentiumpro__"
-
-#ifndef CPP_CPU_DEFAULT_SPEC
-#if TARGET_CPU_DEFAULT == 1
-#define CPP_CPU_DEFAULT_SPEC "%(cpp_486)"
-#else
-#if TARGET_CPU_DEFAULT == 2
-#define CPP_CPU_DEFAULT_SPEC "%(cpp_586)"
-#else
-#if TARGET_CPU_DEFAULT == 3
-#define CPP_CPU_DEFAULT_SPEC "%(cpp_686)"
-#else
-#define CPP_CPU_DEFAULT_SPEC ""
-#endif
-#endif
-#endif
-#endif /* CPP_CPU_DEFAULT_SPEC */
-
-#ifndef CPP_CPU_SPEC
-#define CPP_CPU_SPEC "\
--Acpu(i386) -Amachine(i386) \
-%{!ansi:-Di386} -D__i386 -D__i386__ \
-%{mcpu=i486:%(cpp_486)} %{m486:%(cpp_486)} \
-%{mpentium:%(cpp_586)} %{mcpu=pentium:%(cpp_586)} \
-%{mpentiumpro:%(cpp_686)} %{mcpu=pentiumpro:%(cpp_686)} \
-%{!mcpu*:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}"
-#endif
-
-#ifndef CC1_SPEC
-#define CC1_SPEC "%(cc1_spec) "
-#endif
-
-/* This macro defines names of additional specifications to put in the
-   specs that can be used in various specifications like CC1_SPEC.  Its
-   definition is an initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   specification name, and a string constant that used by the GNU CC driver
-   program.
-
-   Do not define this macro if it does not need to do anything.  */
-
-#ifndef SUBTARGET_EXTRA_SPECS
-#define SUBTARGET_EXTRA_SPECS
-#endif
-
-#define EXTRA_SPECS							\
-  { "cpp_486", CPP_486_SPEC},						\
-  { "cpp_586", CPP_586_SPEC},						\
-  { "cpp_686", CPP_686_SPEC},						\
-  { "cpp_cpu_default",	CPP_CPU_DEFAULT_SPEC },				\
-  { "cpp_cpu",	CPP_CPU_SPEC },						\
-  { "cc1_cpu",  CC1_CPU_SPEC },						\
-  SUBTARGET_EXTRA_SPECS
-
-/* target machine storage layout */
-
-/* Define for XFmode extended real floating point support.
-   This will automatically cause REAL_ARITHMETIC to be defined.  */
-#define LONG_DOUBLE_TYPE_SIZE 96
-
-/* Define if you don't want extended real, but do want to use the
-   software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion. */
-/* #define REAL_ARITHMETIC */
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is true on the 80386.  */
-
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is not true on the 80386.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.  */
-/* Not true for 80386 */
-#define WORDS_BIG_ENDIAN 0
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 80386, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for the code of a function.
-   For i486, we get better performance by aligning to a cache
-   line (i.e. 16 byte) boundary.  */
-#define FUNCTION_BOUNDARY (1 << (i386_align_funcs + 3))
-
-/* Alignment of field after `int : 0' in a structure. */
-
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Minimum size in bits of the largest boundary to which any
-   and all fundamental data types supported by the hardware
-   might need to be aligned. No data type wants to be aligned
-   rounder than this.  The i386 supports 64-bit floating point
-   quantities, but these can be aligned on any 32-bit boundary.
-   The published ABIs say that doubles should be aligned on word
-   boundaries, but the Pentium gets better performance with them
-   aligned on 64 bit boundaries. */
-#define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
-
-/* If defined, a C expression to compute the alignment given to a
-   constant that is being placed in memory.  CONSTANT is the constant
-   and ALIGN is the alignment that the object would ordinarily have.
-   The value of this macro is used instead of that alignment to align
-   the object.
-
-   If this macro is not defined, then ALIGN is used.
-
-   The typical use of this macro is to increase alignment for string
-   constants to be word aligned so that `strcpy' calls that copy
-   constants can be done inline.  */
-
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)					\
-  (TREE_CODE (EXP) == REAL_CST						\
-    ? ((TYPE_MODE (TREE_TYPE (EXP)) == DFmode && (ALIGN) < 64)		\
-	? 64								\
-   	: (TYPE_MODE (TREE_TYPE (EXP)) == XFmode && (ALIGN) < 128)	\
-	? 128								\
-	: (ALIGN))							\
-    : TREE_CODE (EXP) == STRING_CST					\
-    ? ((TREE_STRING_LENGTH (EXP) >= 31 && (ALIGN) < 256)		\
-	? 256								\
-	: (ALIGN))							\
-    : (ALIGN))
-
-/* If defined, a C expression to compute the alignment for a static
-   variable.  TYPE is the data type, and ALIGN is the alignment that
-   the object would ordinarily have.  The value of this macro is used
-   instead of that alignment to align the object.
-
-   If this macro is not defined, then ALIGN is used.
-
-   One use of this macro is to increase alignment of medium-size
-   data to make it all fit in fewer cache lines.  Another is to
-   cause character arrays to be word-aligned so that `strcpy' calls
-   that copy constants to character arrays can be done inline.  */
-
-#define DATA_ALIGNMENT(TYPE, ALIGN)					\
-  ((AGGREGATE_TYPE_P (TYPE)						\
-    && TYPE_SIZE (TYPE)							\
-    && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST			\
-    && (TREE_INT_CST_LOW (TYPE_SIZE (TYPE)) >= 256			\
-	|| TREE_INT_CST_HIGH (TYPE_SIZE (TYPE))) && (ALIGN) < 256)	\
-    ? 256								\
-    : TREE_CODE (TYPE) == ARRAY_TYPE					\
-    ? ((TYPE_MODE (TREE_TYPE (TYPE)) == DFmode && (ALIGN) < 64)	\
-	? 64								\
-   	: (TYPE_MODE (TREE_TYPE (TYPE)) == XFmode && (ALIGN) < 128)	\
-	? 128								\
-	: (ALIGN))							\
-    : TREE_CODE (TYPE) == COMPLEX_TYPE					\
-    ? ((TYPE_MODE (TYPE) == DCmode && (ALIGN) < 64)			\
-	? 64								\
-   	: (TYPE_MODE (TYPE) == XCmode && (ALIGN) < 128)			\
-	? 128								\
-	: (ALIGN))							\
-    : ((TREE_CODE (TYPE) == RECORD_TYPE					\
-	|| TREE_CODE (TYPE) == UNION_TYPE				\
-	|| TREE_CODE (TYPE) == QUAL_UNION_TYPE)				\
-	&& TYPE_FIELDS (TYPE))						\
-    ? ((DECL_MODE (TYPE_FIELDS (TYPE)) == DFmode && (ALIGN) < 64)	\
-	? 64								\
-	: (DECL_MODE (TYPE_FIELDS (TYPE)) == XFmode && (ALIGN) < 128)	\
-	? 128								\
-	: (ALIGN))							\
-    : TREE_CODE (TYPE) == REAL_TYPE					\
-    ? ((TYPE_MODE (TYPE) == DFmode && (ALIGN) < 64)			\
-	? 64								\
-   	: (TYPE_MODE (TYPE) == XFmode && (ALIGN) < 128)			\
-	? 128								\
-	: (ALIGN))							\
-    : (ALIGN))
-
-/* Set this non-zero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 0
-
-/* If bit field type is int, don't let it cross an int,
-   and give entire struct the alignment of an int.  */
-/* Required on the 386 since it doesn't have bitfield insns.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Maximum power of 2 that code can be aligned to.  */
-#define MAX_CODE_ALIGN	6			/* 64 byte alignment */
-
-/* Align loop starts for optimal branching.  */
-#define LOOP_ALIGN(LABEL) (i386_align_loops)
-#define LOOP_ALIGN_MAX_SKIP (i386_align_loops_string ? 0 : 7)
-
-/* This is how to align an instruction for optimal branching.
-   On i486 we'll get better performance by aligning on a
-   cache line (i.e. 16 byte) boundary.  */
-#define LABEL_ALIGN_AFTER_BARRIER(LABEL) (i386_align_jumps)
-#define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP (i386_align_jumps_string ? 0 : 7)
-
-
-/* Standard register usage.  */
-
-/* This processor has special stack-like registers.  See reg-stack.c
-   for details. */
-
-#define STACK_REGS
-#define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode || mode==XFmode)
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   In the 80386 we give the 8 general purpose registers the numbers 0-7.
-   We number the floating point registers 8-15.
-   Note that registers 0-7 can be accessed as a  short or int,
-   while only 0-3 may be used with byte `mov' instructions.
-
-   Reg 16 does not correspond to any hardware register, but instead
-   appears in the RTL as an argument pointer prior to reload, and is
-   eliminated during reloading in favor of either the stack or frame
-   pointer. */
-
-#define FIRST_PSEUDO_REGISTER 17
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   On the 80386, the stack pointer is such, as is the arg pointer. */
-#define FIXED_REGISTERS \
-/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/       \
-{  0, 0, 0, 0, 0, 0, 0, 1, 0,  0,  0,  0,  0,  0,  0,  0,  1 }
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-
-#define CALL_USED_REGISTERS \
-/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
-{  1, 1, 1, 0, 0, 0, 0, 1, 1,  1,  1,  1,  1,  1,  1,  1,  1 }
-
-/* Order in which to allocate registers.  Each register must be
-   listed once, even those in FIXED_REGISTERS.  List frame pointer
-   late and fixed registers last.  Note that, in general, we prefer
-   registers listed in CALL_USED_REGISTERS, keeping the others
-   available for storage of persistent values.
-
-   Three different versions of REG_ALLOC_ORDER have been tried:
-
-   If the order is edx, ecx, eax, ... it produces a slightly faster compiler,
-   but slower code on simple functions returning values in eax.
-
-   If the order is eax, ecx, edx, ... it causes reload to abort when compiling
-   perl 4.036 due to not being able to create a DImode register (to hold a 2
-   word union).
-
-   If the order is eax, edx, ecx, ... it produces better code for simple
-   functions, and a slightly slower compiler.  Users complained about the code
-   generated by allocating edx first, so restore the 'natural' order of things. */
-
-#define REG_ALLOC_ORDER \
-/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
-{  0, 1, 2, 3, 4, 5, 6, 7, 8,  9, 10, 11, 12, 13, 14, 15, 16 }
-
-/* A C statement (sans semicolon) to choose the order in which to
-   allocate hard registers for pseudo-registers local to a basic
-   block.
-
-   Store the desired register order in the array `reg_alloc_order'.
-   Element 0 should be the register to allocate first; element 1, the
-   next register; and so on.
-
-   The macro body should not assume anything about the contents of
-   `reg_alloc_order' before execution of the macro.
-
-   On most machines, it is not necessary to define this macro.  */
-
-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
-
-/* Macro to conditionally modify fixed_regs/call_used_regs.  */
-#define CONDITIONAL_REGISTER_USAGE			\
-  {							\
-    if (flag_pic)					\
-      {							\
-	fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;	\
-	call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;	\
-      }							\
-    if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
-      { 						\
-	int i; 						\
-	HARD_REG_SET x;					\
-        COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
-        for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ )	\
-         if (TEST_HARD_REG_BIT (x, i)) 			\
-	  fixed_regs[i] = call_used_regs[i] = 1; 	\
-      }							\
-  }
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   Actually there are no two word move instructions for consecutive 
-   registers.  And only registers 0-3 may have mov byte instructions
-   applied to them.
-   */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  (FP_REGNO_P (REGNO) ? 1 \
-   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On the 80386, the first 4 cpu registers can hold any mode
-   while the floating point registers may hold only floating point.
-   Make it clear that the fp regs could not hold a 16-byte float.  */
-
-/* The casts to int placate a compiler on a microvax,
-   for cross-compiler testing.  */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-  ((REGNO) < 4 ? 1						\
-   : FP_REGNO_P (REGNO)						\
-   ? (((int) GET_MODE_CLASS (MODE) == (int) MODE_FLOAT		\
-       || (int) GET_MODE_CLASS (MODE) == (int) MODE_COMPLEX_FLOAT)	\
-      && GET_MODE_UNIT_SIZE (MODE) <= (LONG_DOUBLE_TYPE_SIZE == 96 ? 12 : 8))\
-   : (int) (MODE) != (int) QImode ? 1				\
-   : (reload_in_progress | reload_completed) == 1)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-
-#define MODES_TIEABLE_P(MODE1, MODE2)				\
-  ((MODE1) == (MODE2)						\
-   || ((MODE1) == SImode && (MODE2) == HImode)			\
-   || ((MODE1) == HImode && (MODE2) == SImode))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* on the 386 the pc register is %eip, and is not usable as a general
-   register.  The ordinary mov instructions won't work */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 7
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 6
-
-/* First floating point reg */
-#define FIRST_FLOAT_REG 8
-
-/* First & last stack-like regs */
-#define FIRST_STACK_REG FIRST_FLOAT_REG
-#define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED (TARGET_OMIT_LEAF_FRAME_POINTER && !leaf_function_p ()) 	
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 16
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 2
-
-/* Register to hold the addressing base for position independent
-   code access to data items.  */
-#define PIC_OFFSET_TABLE_REGNUM 3
-
-/* Register in which address to store a structure value
-   arrives in the function.  On the 386, the prologue
-   copies this from the stack to register %eax.  */
-#define STRUCT_VALUE_INCOMING 0
-
-/* Place in which caller passes the structure value address.
-   0 means push the value on the stack like an argument.  */
-#define STRUCT_VALUE 0
-
-/* A C expression which can inhibit the returning of certain function
-   values in registers, based on the type of value.  A nonzero value
-   says to return the function value in memory, just as large
-   structures are always returned.  Here TYPE will be a C expression
-   of type `tree', representing the data type of the value.
-
-   Note that values of mode `BLKmode' must be explicitly handled by
-   this macro.  Also, the option `-fpcc-struct-return' takes effect
-   regardless of this macro.  On most systems, it is possible to
-   leave the macro undefined; this causes a default definition to be
-   used, whose value is the constant 1 for `BLKmode' values, and 0
-   otherwise.
-
-   Do not use this macro to indicate that structures and unions
-   should always be returned in memory.  You should instead use
-   `DEFAULT_PCC_STRUCT_RETURN' to indicate this.  */
-
-#define RETURN_IN_MEMORY(TYPE) \
-  ((TYPE_MODE (TYPE) == BLKmode) || int_size_in_bytes (TYPE) > 12)
-
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.
-
-   It might seem that class BREG is unnecessary, since no useful 386
-   opcode needs reg %ebx.  But some systems pass args to the OS in ebx,
-   and the "b" register constraint is useful in asms for syscalls.  */
-
-enum reg_class
-{
-  NO_REGS,
-  AREG, DREG, CREG, BREG,
-  AD_REGS,			/* %eax/%edx for DImode */
-  Q_REGS,			/* %eax %ebx %ecx %edx */
-  SIREG, DIREG,
-  INDEX_REGS,			/* %eax %ebx %ecx %edx %esi %edi %ebp */
-  GENERAL_REGS,			/* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
-  FP_TOP_REG, FP_SECOND_REG,	/* %st(0) %st(1) */
-  FLOAT_REGS,
-  ALL_REGS, LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-#define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
-{  "NO_REGS",				\
-   "AREG", "DREG", "CREG", "BREG",	\
-   "AD_REGS",				\
-   "Q_REGS",				\
-   "SIREG", "DIREG",			\
-   "INDEX_REGS",			\
-   "GENERAL_REGS",			\
-   "FP_TOP_REG", "FP_SECOND_REG",	\
-   "FLOAT_REGS",			\
-   "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS \
-{      {0},							\
-     {0x1},    {0x2},  {0x4},	 {0x8},	/* AREG, DREG, CREG, BREG */	\
-     {0x3},			/* AD_REGS */			\
-     {0xf},			/* Q_REGS */			\
-    {0x10},   {0x20},		/* SIREG, DIREG */		\
- {0x7f},				/* INDEX_REGS */		\
- {0x100ff},			/* GENERAL_REGS */		\
-  {0x0100}, {0x0200},		/* FP_TOP_REG, FP_SECOND_REG */	\
-  {0xff00},			/* FLOAT_REGS */		\
- {0x1ffff}}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
-
-/* When defined, the compiler allows registers explicitly used in the
-   rtl to be used as spill registers but prevents the compiler from
-   extending the lifetime of these registers. */
-
-#define SMALL_REGISTER_CLASSES 1
-
-#define QI_REG_P(X) \
-  (REG_P (X) && REGNO (X) < 4)
-#define NON_QI_REG_P(X) \
-  (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
-
-#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
-#define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
-  
-#define STACK_REG_P(xop) (REG_P (xop) &&		       	\
-			  REGNO (xop) >= FIRST_STACK_REG &&	\
-			  REGNO (xop) <= LAST_STACK_REG)
-
-#define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop))
-
-#define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG)
-
-/* 1 if register REGNO can magically overlap other regs.
-   Note that nonzero values work only in very special circumstances. */
-
-/* #define OVERLAPPING_REGNO_P(REGNO) FP_REGNO_P (REGNO) */
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS INDEX_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C)	\
-  ((C) == 'r' ? GENERAL_REGS :					\
-   (C) == 'q' ? Q_REGS :					\
-   (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387	\
-		 ? FLOAT_REGS					\
-		 : NO_REGS) :					\
-   (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387	\
-		 ? FP_TOP_REG					\
-		 : NO_REGS) :					\
-   (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387	\
-		 ? FP_SECOND_REG				\
-		 : NO_REGS) :					\
-   (C) == 'a' ? AREG :						\
-   (C) == 'b' ? BREG :						\
-   (C) == 'c' ? CREG :						\
-   (C) == 'd' ? DREG :						\
-   (C) == 'A' ? AD_REGS :					\
-   (C) == 'D' ? DIREG :						\
-   (C) == 'S' ? SIREG : NO_REGS)
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   I is for non-DImode shifts.
-   J is for DImode shifts.
-   K and L are for an `andsi' optimization.
-   M is for shifts that can be executed by the "lea" opcode.
-   */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 :	\
-   (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 :	\
-   (C) == 'K' ? (VALUE) == 0xff :		\
-   (C) == 'L' ? (VALUE) == 0xffff :		\
-   (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 :	\
-   (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 :\
-   (C) == 'O' ? (VALUE) >= 0 && (VALUE) <= 32 :	\
-   0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  We allow constants even if
-   TARGET_387 isn't set, because the stack register converter may need to
-   load 0.0 into the function value register.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'G' ? standard_80387_constant_p (VALUE) : 0)
-
-/* Place additional restrictions on the register class to use when it
-   is necessary to be able to hold a value of mode MODE in a reload
-   register for which class CLASS would ordinarily be used. */
-
-#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
-  ((MODE) == QImode && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
-   ? Q_REGS : (CLASS))
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.
-   On the 80386 series, we prevent floating constants from being
-   reloaded into floating registers (since no move-insn can do that)
-   and we ensure that QImodes aren't reloaded into the esi or edi reg.  */
-
-/* Put float CONST_DOUBLE in the constant pool instead of fp regs.
-   QImode must go into class Q_REGS.
-   Narrow ALL_REGS to GENERAL_REGS.  This supports allowing movsf and
-   movdf to do mem-to-mem moves through integer regs. */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)					\
-  (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode		\
-   ? (standard_80387_constant_p (X)					\
-      ? reg_class_subset_p (CLASS, FLOAT_REGS) ? CLASS : FLOAT_REGS	\
-      : NO_REGS)							\
-   : GET_MODE (X) == QImode && ! reg_class_subset_p (CLASS, Q_REGS) ? Q_REGS \
-   : ((CLASS) == ALL_REGS						\
-      && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) ? GENERAL_REGS	\
-   : (CLASS))
-
-/* If we are copying between general and FP registers, we need a memory
-   location.  */
-
-#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
-  ((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2))	\
-   || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2)))
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-/* On the 80386, this is the size of MODE in words,
-   except in the FP regs, where a single reg is always enough.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- (FLOAT_CLASS_P (CLASS) ? 1 :		\
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* A C expression whose value is nonzero if pseudos that have been
-   assigned to registers of class CLASS would likely be spilled
-   because registers of CLASS are needed for spill registers.
-
-   The default value of this macro returns 1 if CLASS has exactly one
-   register and zero otherwise.  On most machines, this default
-   should be used.  Only define this macro to some other expression
-   if pseudo allocated by `local-alloc.c' end up in memory because
-   their hard registers were needed for spill registers.  If this
-   macro returns nonzero for those classes, those pseudos will only
-   be allocated by `global.c', which knows how to reallocate the
-   pseudo to another register.  If there would not be another
-   register available for reallocation, you should not change the
-   definition of this macro since the only effect of such a
-   definition would be to slow down register allocation.  */
-
-#define CLASS_LIKELY_SPILLED_P(CLASS)					\
-  (((CLASS) == AREG)							\
-   || ((CLASS) == DREG)							\
-   || ((CLASS) == CREG)							\
-   || ((CLASS) == BREG)							\
-   || ((CLASS) == AD_REGS)						\
-   || ((CLASS) == SIREG)						\
-   || ((CLASS) == DIREG))
-
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On 386 pushw decrements by exactly 2 no matter what the position was.
-   On the 386 there is no pushb; we use pushw instead, and this
-   has the effect of rounding up to 2.  */
-
-#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2))
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.
-
-   On the 80386, the RTD insn may be used to pop them if the number
-     of args is fixed, but if the number is variable then the caller
-     must pop them all.  RTD can't be used for library calls now
-     because the library is compiled with the Unix compiler.
-   Use of RTD is a selectable option, since it is incompatible with
-   standard Unix calling sequences.  If the option is not selected,
-   the caller must always pop the args.
-
-   The attribute stdcall is equivalent to RTD on a per module basis.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
-  (i386_return_pops_args (FUNDECL, FUNTYPE, SIZE))
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-   gen_rtx_REG (TYPE_MODE (VALTYPE), \
-	    VALUE_REGNO (TYPE_MODE (VALTYPE)))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE) \
-  gen_rtx_REG (MODE, VALUE_REGNO (MODE))
-
-/* Define the size of the result block used for communication between
-   untyped_call and untyped_return.  The block contains a DImode value
-   followed by the block used by fnsave and frstor.  */
-
-#define APPLY_RESULT_SIZE (8+108)
-
-/* 1 if N is a possible register number for function argument passing.  */
-#define FUNCTION_ARG_REGNO_P(N) ((N) >= 0 && (N) < REGPARM_MAX)
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.  */
-
-typedef struct i386_args {
-  int words;			/* # words passed so far */
-  int nregs;			/* # registers available for passing */
-  int regno;			/* next available register number */
-} CUMULATIVE_ARGS;
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
-  (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
-  (function_arg_advance (&CUM, MODE, TYPE, NAMED))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  (function_arg (&CUM, MODE, TYPE, NAMED))
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-  (function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED))
-
-/* This macro is invoked just before the start of a function.
-   It is used here to output code for -fpic that will load the
-   return address into %ebx.  */
-
-#undef ASM_OUTPUT_FUNCTION_PREFIX
-#define ASM_OUTPUT_FUNCTION_PREFIX(FILE, FNNAME) \
-  asm_output_function_prefix (FILE, FNNAME)
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)     \
-  function_prologue (FILE, SIZE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-{									\
-  if (flag_pic)								\
-    {									\
-      fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n",		\
-	       LPREFIX, (LABELNO));					\
-      fprintf (FILE, "\tcall *_mcount@GOT(%%ebx)\n");			\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO));	\
-      fprintf (FILE, "\tcall _mcount\n");				\
-    }									\
-}
-
-
-/* There are three profiling modes for basic blocks available.
-   The modes are selected at compile time by using the options
-   -a or -ax of the gnu compiler.
-   The variable `profile_block_flag' will be set according to the
-   selected option.
-
-   profile_block_flag == 0, no option used:
-
-      No profiling done.
-
-   profile_block_flag == 1, -a option used.
-
-      Count frequency of execution of every basic block.
-
-   profile_block_flag == 2, -ax option used.
-
-      Generate code to allow several different profiling modes at run time. 
-      Available modes are:
-             Produce a trace of all basic blocks.
-             Count frequency of jump instructions executed.
-      In every mode it is possible to start profiling upon entering
-      certain functions and to disable profiling of some other functions.
-
-    The result of basic-block profiling will be written to a file `bb.out'.
-    If the -ax option is used parameters for the profiling will be read
-    from file `bb.in'.
-
-*/
-
-/* The following macro shall output assembler code to FILE
-   to initialize basic-block profiling.
-
-   If profile_block_flag == 2
-
-	Output code to call the subroutine `__bb_init_trace_func'
-	and pass two parameters to it. The first parameter is
-	the address of a block allocated in the object module.
-	The second parameter is the number of the first basic block
-	of the function.
-
-	The name of the block is a local symbol made with this statement:
-	
-	    ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
-
-	Of course, since you are writing the definition of
-	`ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
-	can take a short cut in the definition of this macro and use the
-	name that you know will result.
-
-	The number of the first basic block of the function is
-	passed to the macro in BLOCK_OR_LABEL.
-
-	If described in a virtual assembler language the code to be
-	output looks like:
-
-		parameter1 <- LPBX0
-		parameter2 <- BLOCK_OR_LABEL
-		call __bb_init_trace_func
-
-    else if profile_block_flag != 0
-
-	Output code to call the subroutine `__bb_init_func'
-	and pass one single parameter to it, which is the same
-	as the first parameter to `__bb_init_trace_func'.
-
-	The first word of this parameter is a flag which will be nonzero if
-	the object module has already been initialized.  So test this word
-	first, and do not call `__bb_init_func' if the flag is nonzero.
-	Note: When profile_block_flag == 2 the test need not be done
-	but `__bb_init_trace_func' *must* be called.
-
-	BLOCK_OR_LABEL may be used to generate a label number as a
-	branch destination in case `__bb_init_func' will not be called.
-
-	If described in a virtual assembler language the code to be
-	output looks like:
-
-		cmp (LPBX0),0
-		jne local_label
-		parameter1 <- LPBX0
-		call __bb_init_func
-local_label:
-
-*/
-
-#undef	FUNCTION_BLOCK_PROFILER
-#define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL)			\
-do									\
-  {									\
-    static int num_func = 0;						\
-    rtx xops[8];							\
-    char block_table[80], false_label[80];				\
-									\
-    ASM_GENERATE_INTERNAL_LABEL (block_table, "LPBX", 0);		\
-									\
-    xops[1] = gen_rtx_SYMBOL_REF (VOIDmode, block_table);		\
-    xops[5] = stack_pointer_rtx;					\
-    xops[7] = gen_rtx_REG (Pmode, 0);	/* eax */			\
-									\
-    CONSTANT_POOL_ADDRESS_P (xops[1]) = TRUE;				\
-									\
-    switch (profile_block_flag) 					\
-      {									\
-									\
-      case 2:								\
-									\
-        xops[2] = GEN_INT ((BLOCK_OR_LABEL));				\
-        xops[3] = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, "__bb_init_trace_func")); \
-        xops[6] = GEN_INT (8);						\
-    									\
-        output_asm_insn (AS1(push%L2,%2), xops);			\
-        if (!flag_pic)							\
-          output_asm_insn (AS1(push%L1,%1), xops);			\
-        else								\
-          {								\
-            output_asm_insn (AS2 (lea%L7,%a1,%7), xops);		\
-            output_asm_insn (AS1 (push%L7,%7), xops);			\
-          }								\
-    									\
-        output_asm_insn (AS1(call,%P3), xops);				\
-        output_asm_insn (AS2(add%L0,%6,%5), xops);			\
-									\
-        break;								\
-									\
-      default:								\
-									\
-        ASM_GENERATE_INTERNAL_LABEL (false_label, "LPBZ", num_func);	\
-    									\
-        xops[0] = const0_rtx;						\
-        xops[2] = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, false_label)); \
-        xops[3] = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, "__bb_init_func")); \
-        xops[4] = gen_rtx_MEM (Pmode, xops[1]);			\
-        xops[6] = GEN_INT (4);						\
-    									\
-        CONSTANT_POOL_ADDRESS_P (xops[2]) = TRUE;			\
-    									\
-        output_asm_insn (AS2(cmp%L4,%0,%4), xops);			\
-        output_asm_insn (AS1(jne,%2), xops);				\
-    									\
-        if (!flag_pic)							\
-          output_asm_insn (AS1(push%L1,%1), xops);			\
-        else								\
-          {								\
-            output_asm_insn (AS2 (lea%L7,%a1,%7), xops);		\
-            output_asm_insn (AS1 (push%L7,%7), xops);			\
-          }								\
-    									\
-        output_asm_insn (AS1(call,%P3), xops);				\
-        output_asm_insn (AS2(add%L0,%6,%5), xops);			\
-        ASM_OUTPUT_INTERNAL_LABEL (FILE, "LPBZ", num_func);		\
-        num_func++;							\
-									\
-        break;								\
-									\
-    }									\
-  }									\
-while (0)
-
-/* The following macro shall output assembler code to FILE
-   to increment a counter associated with basic block number BLOCKNO.
-
-   If profile_block_flag == 2
-
-	Output code to initialize the global structure `__bb' and
-	call the function `__bb_trace_func' which will increment the
-	counter.
-
-	`__bb' consists of two words. In the first word the number
-	of the basic block has to be stored. In the second word
-	the address of a block allocated in the object module 
-	has to be stored.
-
-	The basic block number is given by BLOCKNO.
-
-	The address of the block is given by the label created with 
-
-	    ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
-
-	by FUNCTION_BLOCK_PROFILER.
-
-	Of course, since you are writing the definition of
-	`ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
-	can take a short cut in the definition of this macro and use the
-	name that you know will result.
-
-	If described in a virtual assembler language the code to be
-	output looks like:
-
-		move BLOCKNO -> (__bb)
-		move LPBX0 -> (__bb+4)
-		call __bb_trace_func
-
-	Note that function `__bb_trace_func' must not change the
-	machine state, especially the flag register. To grant
-	this, you must output code to save and restore registers
-	either in this macro or in the macros MACHINE_STATE_SAVE
-	and MACHINE_STATE_RESTORE. The last two macros will be
-	used in the function `__bb_trace_func', so you must make
-	sure that the function prologue does not change any 
-	register prior to saving it with MACHINE_STATE_SAVE.
-
-   else if profile_block_flag != 0
-
-	Output code to increment the counter directly.
-	Basic blocks are numbered separately from zero within each
-	compiled object module. The count associated with block number
-	BLOCKNO is at index BLOCKNO in an array of words; the name of 
-	this array is a local symbol made with this statement:
-
-	    ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
-
-	Of course, since you are writing the definition of
-	`ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
-	can take a short cut in the definition of this macro and use the
-	name that you know will result. 
-
-	If described in a virtual assembler language the code to be
-	output looks like:
-
-		inc (LPBX2+4*BLOCKNO)
-
-*/
-
-#define BLOCK_PROFILER(FILE, BLOCKNO)					\
-do									\
-  {									\
-    rtx xops[8], cnt_rtx;						\
-    char counts[80];							\
-    char *block_table = counts;						\
-									\
-    switch (profile_block_flag) 					\
-      {									\
-									\
-      case 2:								\
-									\
-        ASM_GENERATE_INTERNAL_LABEL (block_table, "LPBX", 0);		\
-									\
-	xops[1] = gen_rtx_SYMBOL_REF (VOIDmode, block_table);		\
-        xops[2] = GEN_INT ((BLOCKNO));					\
-        xops[3] = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, "__bb_trace_func")); \
-        xops[4] = gen_rtx_SYMBOL_REF (VOIDmode, "__bb");		\
-	xops[5] = plus_constant (xops[4], 4);				\
-	xops[0] = gen_rtx_MEM (SImode, xops[4]);			\
-	xops[6] = gen_rtx_MEM (SImode, xops[5]);			\
-									\
-	CONSTANT_POOL_ADDRESS_P (xops[1]) = TRUE;			\
-									\
-	fprintf(FILE, "\tpushf\n");					\
-        output_asm_insn (AS2(mov%L0,%2,%0), xops);			\
-	if (flag_pic)							\
-	  {								\
-            xops[7] = gen_rtx_REG (Pmode, 0);	/* eax */		\
-            output_asm_insn (AS1(push%L7,%7), xops);			\
-            output_asm_insn (AS2(lea%L7,%a1,%7), xops);			\
-            output_asm_insn (AS2(mov%L6,%7,%6), xops);			\
-            output_asm_insn (AS1(pop%L7,%7), xops);			\
-	  }								\
-        else								\
-          output_asm_insn (AS2(mov%L6,%1,%6), xops);			\
-        output_asm_insn (AS1(call,%P3), xops);				\
-	fprintf(FILE, "\tpopf\n");					\
-									\
-        break;								\
-									\
-      default:								\
-									\
-        ASM_GENERATE_INTERNAL_LABEL (counts, "LPBX", 2);		\
-        cnt_rtx = gen_rtx_SYMBOL_REF (VOIDmode, counts);		\
-        SYMBOL_REF_FLAG (cnt_rtx) = TRUE;				\
-									\
-        if (BLOCKNO)							\
-          cnt_rtx = plus_constant (cnt_rtx, (BLOCKNO)*4);		\
-									\
-        if (flag_pic)							\
-          cnt_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, cnt_rtx);	\
-									\
-        xops[0] = gen_rtx_MEM (SImode, cnt_rtx);			\
-        output_asm_insn (AS1(inc%L0,%0), xops);				\
-									\
-        break;								\
-									\
-    }									\
-  }									\
-while (0)
-
-/* The following macro shall output assembler code to FILE
-   to indicate a return from function during basic-block profiling.
-
-   If profiling_block_flag == 2:
-
-	Output assembler code to call function `__bb_trace_ret'.
-
-	Note that function `__bb_trace_ret' must not change the
-	machine state, especially the flag register. To grant
-	this, you must output code to save and restore registers
-	either in this macro or in the macros MACHINE_STATE_SAVE_RET
-	and MACHINE_STATE_RESTORE_RET. The last two macros will be
-	used in the function `__bb_trace_ret', so you must make
-	sure that the function prologue does not change any 
-	register prior to saving it with MACHINE_STATE_SAVE_RET.
-
-   else if profiling_block_flag != 0:
-
-	The macro will not be used, so it need not distinguish
-	these cases.
-*/
-
-#define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
-do									\
-  {									\
-    rtx xops[1];							\
-									\
-    xops[0] = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, "__bb_trace_ret")); \
-									\
-    output_asm_insn (AS1(call,%P0), xops);				\
-									\
-  }									\
-while (0)
-
-/* The function `__bb_trace_func' is called in every basic block
-   and is not allowed to change the machine state. Saving (restoring)
-   the state can either be done in the BLOCK_PROFILER macro,
-   before calling function (rsp. after returning from function)
-   `__bb_trace_func', or it can be done inside the function by
-   defining the macros:
-
-	MACHINE_STATE_SAVE(ID)
-	MACHINE_STATE_RESTORE(ID)
-
-   In the latter case care must be taken, that the prologue code
-   of function `__bb_trace_func' does not already change the
-   state prior to saving it with MACHINE_STATE_SAVE.
-
-   The parameter `ID' is a string identifying a unique macro use.
-
-   On the i386 the initialization code at the begin of
-   function `__bb_trace_func' contains a `sub' instruction
-   therefore we handle save and restore of the flag register 
-   in the BLOCK_PROFILER macro. */
-
-#define MACHINE_STATE_SAVE(ID) \
-  asm ("	pushl %eax"); \
-  asm ("	pushl %ecx"); \
-  asm ("	pushl %edx"); \
-  asm ("	pushl %esi");
-
-#define MACHINE_STATE_RESTORE(ID) \
-  asm ("	popl %esi"); \
-  asm ("	popl %edx"); \
-  asm ("	popl %ecx"); \
-  asm ("	popl %eax");
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-/* Note on the 386 it might be more efficient not to define this since 
-   we have to restore it ourselves from the frame pointer, in order to
-   use pop */
-
-#define EXIT_IGNORE_STACK 1
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.
-
-   If the last non-note insn in the function is a BARRIER, then there
-   is no need to emit a function prologue, because control does not fall
-   off the end.  This happens if the function ends in an "exit" call, or
-   if a `return' insn is emitted directly into the function. */
-
-#if 0
-#define FUNCTION_BEGIN_EPILOGUE(FILE)		\
-do {						\
-  rtx last = get_last_insn ();			\
-  if (last && GET_CODE (last) == NOTE)		\
-    last = prev_nonnote_insn (last);		\
-/*  if (! last || GET_CODE (last) != BARRIER)	\
-    function_epilogue (FILE, SIZE);*/		\
-} while (0)
-#endif
-
-#define FUNCTION_EPILOGUE(FILE, SIZE)     \
-  function_epilogue (FILE, SIZE)
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  */
-
-/* On the 386, the trampoline contains two instructions:
-     mov #STATIC,ecx
-     jmp FUNCTION
-   The trampoline is generated entirely at runtime.  The operand of JMP
-   is the address of FUNCTION relative to the instruction following the
-   JMP (which is 5 bytes long).  */
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 10
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  /* Compute offset from the end of the jmp to the target function.  */	\
-  rtx disp = expand_binop (SImode, sub_optab, FNADDR,			\
-			   plus_constant (TRAMP, 10),			\
-			   NULL_RTX, 1, OPTAB_DIRECT);			\
-  emit_move_insn (gen_rtx_MEM (QImode, TRAMP), GEN_INT (0xb9));		\
-  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 1)), CXT); \
-  emit_move_insn (gen_rtx_MEM (QImode, plus_constant (TRAMP, 5)), GEN_INT (0xe9));\
-  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 6)), disp); \
-}
-
-/* Definitions for register eliminations.
-
-   This is an array of structures.  Each structure initializes one pair
-   of eliminable registers.  The "from" register number is given first,
-   followed by "to".  Eliminations of the same "from" register are listed
-   in order of preference.
-
-   We have two registers that can be eliminated on the i386.  First, the
-   frame pointer register can often be eliminated in favor of the stack
-   pointer register.  Secondly, the argument pointer register can always be
-   eliminated; it is replaced with either the stack or frame pointer. */
-
-#define ELIMINABLE_REGS				\
-{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},   \
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
-
-/* Given FROM and TO register numbers, say whether this elimination is allowed.
-   Frame pointer elimination is automatically handled.
-
-   For the i386, if frame pointer elimination is being done, we would like to
-   convert ap into sp, not fp.
-
-   All other eliminations are valid.  */
-
-#define CAN_ELIMINATE(FROM, TO)					\
- ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM	\
-  ? ! frame_pointer_needed					\
-  : 1)
-
-/* Define the offset between two registers, one to be eliminated, and the other
-   its replacement, at the start of a routine.  */
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
-{									\
-  if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)	\
-    (OFFSET) = 8;	/* Skip saved PC and previous frame pointer */	\
-  else									\
-    {									\
-      int regno;							\
-      int offset = 0;							\
-									\
-      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)		\
-	if ((regs_ever_live[regno] && ! call_used_regs[regno])		\
-	    || ((current_function_uses_pic_offset_table			\
-		 || current_function_uses_const_pool)			\
-		&& flag_pic && regno == PIC_OFFSET_TABLE_REGNUM))	\
-	  offset += 4;							\
-									\
-      (OFFSET) = offset + get_frame_size ();				\
-									\
-      if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	\
-	(OFFSET) += 4;	/* Skip saved PC */				\
-    }									\
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-  ((REGNO) < STACK_POINTER_REGNUM \
-   || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM)
-
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-  ((REGNO) <= STACK_POINTER_REGNUM \
-   || (REGNO) == ARG_POINTER_REGNUM \
-   || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
-
-#define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
-#define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5)
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-
-/* Non strict versions, pseudos are ok */
-#define REG_OK_FOR_INDEX_NONSTRICT_P(X)					\
-  (REGNO (X) < STACK_POINTER_REGNUM					\
-   || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-
-#define REG_OK_FOR_BASE_NONSTRICT_P(X)					\
-  (REGNO (X) <= STACK_POINTER_REGNUM					\
-   || REGNO (X) == ARG_POINTER_REGNUM					\
-   || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-
-#define REG_OK_FOR_STRREG_NONSTRICT_P(X)				\
-  (REGNO (X) == 4 || REGNO (X) == 5 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-
-/* Strict versions, hard registers only */
-#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-#define REG_OK_FOR_BASE_STRICT_P(X)  REGNO_OK_FOR_BASE_P (REGNO (X))
-#define REG_OK_FOR_STRREG_STRICT_P(X)					\
-  (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X)))
-
-#ifndef REG_OK_STRICT
-#define REG_OK_FOR_INDEX_P(X)  REG_OK_FOR_INDEX_NONSTRICT_P(X)
-#define REG_OK_FOR_BASE_P(X)   REG_OK_FOR_BASE_NONSTRICT_P(X)
-#define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_NONSTRICT_P(X)
-
-#else
-#define REG_OK_FOR_INDEX_P(X)  REG_OK_FOR_INDEX_STRICT_P(X)
-#define REG_OK_FOR_BASE_P(X)   REG_OK_FOR_BASE_STRICT_P(X)
-#define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_STRICT_P(X)
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
-   except for CONSTANT_ADDRESS_P which is usually machine-independent.
-
-   See legitimize_pic_address in i386.c for details as to what
-   constitutes a legitimate address when -fpic is used.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-#define CONSTANT_ADDRESS_P(X)					\
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF	\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) \
-  (GET_CODE (X) == CONST_DOUBLE ? standard_80387_constant_p (X) : 1)
-
-#ifdef REG_OK_STRICT
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-{									\
-  if (legitimate_address_p (MODE, X, 1))				\
-    goto ADDR;								\
-}
-
-#else
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-{									\
-  if (legitimate_address_p (MODE, X, 0))				\
-    goto ADDR;								\
-}
-
-#endif
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the 80386, we handle X+REG by loading X into a register R and
-   using R+REG.  R will go in a general reg and indexing will be used.
-   However, if REG is a broken-out memory address or multiplication,
-   nothing needs to be done because REG can certainly go in a general reg.
-
-   When -fpic is used, special handling is needed for symbolic references.
-   See comments by legitimize_pic_address in i386.c for details.  */
-
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)				\
-{									\
-  (X) = legitimize_address (X, OLDX, MODE);				\
-  if (memory_address_p (MODE, X))					\
-    goto WIN;								\
-}
-
-#define REWRITE_ADDRESS(x) rewrite_address(x)
-
-/* Nonzero if the constant value X is a legitimate general operand
-   when generating PIC code.  It is given that flag_pic is on and 
-   that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_PIC_OPERAND_P(X) \
-  (! SYMBOLIC_CONST (X)							\
-   || (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)))
-
-#define SYMBOLIC_CONST(X)	\
-(GET_CODE (X) == SYMBOL_REF						\
- || GET_CODE (X) == LABEL_REF						\
- || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the 80386, only postdecrement and postincrement address depend thus
-   (the amount of decrement or increment being the length of the operand).  */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
- if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
-
-/* Define this macro if references to a symbol must be treated
-   differently depending on something about the variable or
-   function named by the symbol (such as what section it is in).
-
-   On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
-   so that we may access it directly in the GOT.  */
-
-#define ENCODE_SECTION_INFO(DECL) \
-do									\
-  {									\
-    if (flag_pic)							\
-      {									\
-	rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd'		\
-		   ? TREE_CST_RTL (DECL) : DECL_RTL (DECL));		\
-									\
-	if (TARGET_DEBUG_ADDR						\
-	    && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd')		\
-	  {								\
-	    fprintf (stderr, "Encode %s, public = %d\n",		\
-		     IDENTIFIER_POINTER (DECL_NAME (DECL)),		\
-		     TREE_PUBLIC (DECL));				\
-	  }								\
-									\
-	SYMBOL_REF_FLAG (XEXP (rtl, 0))					\
-	  = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd'			\
-	     || ! TREE_PUBLIC (DECL));					\
-      }									\
-  }									\
-while (0)
-
-/* Initialize data used by insn expanders.  This is called from
-   init_emit, once for each function, before code is generated.
-   For 386, clear stack slot assignments remembered from previous
-   functions. */
-
-#define INIT_EXPANDERS clear_386_stack_locals ()
-
-/* The `FINALIZE_PIC' macro serves as a hook to emit these special
-   codes once the function is being compiled into assembly code, but
-   not before.  (It is not done before, because in the case of
-   compiling an inline function, it would lead to multiple PIC
-   prologues being included in functions which used inline functions
-   and were compiled to assembly language.)  */
-
-#define FINALIZE_PIC							\
-do									\
-  {									\
-    extern int current_function_uses_pic_offset_table;			\
-									\
-    current_function_uses_pic_offset_table |= profile_flag | profile_block_flag; \
-  }									\
-while (0)
-
-
-/* If defined, a C expression whose value is nonzero if IDENTIFIER
-   with arguments ARGS is a valid machine specific attribute for DECL.
-   The attributes in ATTRIBUTES have previously been assigned to DECL.  */
-
-#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, NAME, ARGS) \
-  (i386_valid_decl_attribute_p (DECL, ATTRIBUTES, NAME, ARGS))
-
-/* If defined, a C expression whose value is nonzero if IDENTIFIER
-   with arguments ARGS is a valid machine specific attribute for TYPE.
-   The attributes in ATTRIBUTES have previously been assigned to TYPE.  */
-
-#define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
-  (i386_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
-
-/* If defined, a C expression whose value is zero if the attributes on
-   TYPE1 and TYPE2 are incompatible, one if they are compatible, and
-   two if they are nearly compatible (which causes a warning to be
-   generated).  */
-
-#define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
-  (i386_comp_type_attributes (TYPE1, TYPE2))
-
-/* If defined, a C statement that assigns default attributes to newly
-   defined TYPE.  */
-
-/* #define SET_DEFAULT_TYPE_ATTRIBUTES (TYPE) */
-
-/* Max number of args passed in registers.  If this is more than 3, we will
-   have problems with ebx (register #4), since it is a caller save register and
-   is also used as the pic register in ELF.  So for now, don't allow more than
-   3 registers to be passed in registers.  */
-
-#define REGPARM_MAX 3
-
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE Pmode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.
-   This should be changed to take advantage of fist --wfs ??
- */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 4
-
-/* If a memory-to-memory move would take MOVE_RATIO or more simple
-   move-instruction pairs, we will do a movstr or libcall instead.
-   Increasing the value will always make code faster, but eventually
-   incurs high cost in increased code size.
-
-   If you don't define this, a reasonable default is used.
-
-   Make this large on i386, since the block move is very inefficient with small
-   blocks, and the hard register needs of the block move require much reload
-   work. */
-
-#define MOVE_RATIO 5
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-/* On i386, shifts do truncate the count.  But bit opcodes don't. */
-
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
-/* When a prototype says `char' or `short', really pass an `int'.
-   (The 386 can't easily push less than an int.)  */
-
-#define PROMOTE_PROTOTYPES
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* A part of a C `switch' statement that describes the relative costs
-   of constant RTL expressions.  It must contain `case' labels for
-   expression codes `const_int', `const', `symbol_ref', `label_ref'
-   and `const_double'.  Each case must ultimately reach a `return'
-   statement to return the relative cost of the use of that kind of
-   constant value in an expression.  The cost may depend on the
-   precise value of the constant, which is available for examination
-   in X, and the rtx code of the expression in which it is contained,
-   found in OUTER_CODE.
-  
-   CODE is the expression code--redundant, since it can be obtained
-   with `GET_CODE (X)'.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    return (unsigned) INTVAL (RTX) < 256 ? 0 : 1;		\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return flag_pic && SYMBOLIC_CONST (RTX) ? 2 : 1;		\
-								\
-  case CONST_DOUBLE:						\
-    {								\
-      int code;							\
-      if (GET_MODE (RTX) == VOIDmode)				\
-	return 2;						\
-								\
-      code = standard_80387_constant_p (RTX);			\
-      return code == 1 ? 0 :					\
-	     code == 2 ? 1 :					\
-			 2;					\
-    }
-
-/* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
-#define TOPLEVEL_COSTS_N_INSNS(N) {total = COSTS_N_INSNS (N); break;}
-
-/* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
-   This can be used, for example, to indicate how costly a multiply
-   instruction is.  In writing this macro, you can use the construct
-   `COSTS_N_INSNS (N)' to specify a cost equal to N fast
-   instructions.  OUTER_CODE is the code of the expression in which X
-   is contained.
-
-   This macro is optional; do not define it if the default cost
-   assumptions are adequate for the target machine.  */
-
-#define RTX_COSTS(X,CODE,OUTER_CODE)					\
-  case ASHIFT:								\
-    if (GET_CODE (XEXP (X, 1)) == CONST_INT				\
-	&& GET_MODE (XEXP (X, 0)) == SImode)				\
-      {									\
-	HOST_WIDE_INT value = INTVAL (XEXP (X, 1));			\
-									\
-	if (value == 1)							\
-	  return COSTS_N_INSNS (ix86_cost->add) 			\
-				+ rtx_cost(XEXP (X, 0), OUTER_CODE);	\
-									\
-	if (value == 2 || value == 3)					\
-	  return COSTS_N_INSNS (ix86_cost->lea)				\
-				 + rtx_cost(XEXP (X, 0), OUTER_CODE);	\
-      }									\
-    /* fall through */							\
-		  							\
-  case ROTATE:								\
-  case ASHIFTRT:							\
-  case LSHIFTRT:							\
-  case ROTATERT:							\
-    if (GET_MODE (XEXP (X, 0)) == DImode)				\
-      {									\
-	if (GET_CODE (XEXP (X, 1)) == CONST_INT)			\
-	  {								\
-	    if (INTVAL (XEXP (X, 1)) > 32)				\
-	      return COSTS_N_INSNS(ix86_cost->shift_const + 2);		\
-	    return COSTS_N_INSNS(ix86_cost->shift_const * 2);		\
-	  }								\
-	return ((GET_CODE (XEXP (X, 1)) == AND				\
-		 ? COSTS_N_INSNS(ix86_cost->shift_var * 2)		\
-		 : COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2))		\
-		+ rtx_cost(XEXP (X, 0), OUTER_CODE));			\
-      }									\
-    return COSTS_N_INSNS (GET_CODE (XEXP (X, 1)) == CONST_INT		\
-			  ? ix86_cost->shift_const			\
-			  : ix86_cost->shift_var)			\
-      + rtx_cost(XEXP (X, 0), OUTER_CODE);				\
-									\
-  case MULT:								\
-    if (GET_CODE (XEXP (X, 1)) == CONST_INT)				\
-      {									\
-	unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1));		\
-	int nbits = 0;							\
-									\
-	if (value == 2)							\
-	  return COSTS_N_INSNS (ix86_cost->add)				\
-				 + rtx_cost(XEXP (X, 0), OUTER_CODE);	\
-	if (value == 4 || value == 8)					\
-	  return COSTS_N_INSNS (ix86_cost->lea)				\
-				 + rtx_cost(XEXP (X, 0), OUTER_CODE);	\
-									\
-	while (value != 0)						\
-	  {								\
-	    nbits++;							\
-	    value >>= 1;						\
-	  } 								\
-									\
-	if (nbits == 1)							\
-	  return COSTS_N_INSNS (ix86_cost->shift_const)			\
-	    + rtx_cost(XEXP (X, 0), OUTER_CODE);			\
-									\
-	return COSTS_N_INSNS (ix86_cost->mult_init			\
-			      + nbits * ix86_cost->mult_bit)		\
-	  + rtx_cost(XEXP (X, 0), OUTER_CODE);				\
-      }									\
-									\
-    else			/* This is arbitrary */			\
-      TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init			\
-			      + 7 * ix86_cost->mult_bit);		\
-									\
-  case DIV:								\
-  case UDIV:								\
-  case MOD:								\
-  case UMOD:								\
-    TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide);				\
-									\
-  case PLUS:								\
-    if (GET_CODE (XEXP (X, 0)) == REG					\
-	&& GET_MODE (XEXP (X, 0)) == SImode				\
-	&& GET_CODE (XEXP (X, 1)) == PLUS)				\
-      return COSTS_N_INSNS (ix86_cost->lea);				\
-									\
-    /* fall through */							\
-  case AND:								\
-  case IOR:								\
-  case XOR:								\
-  case MINUS:								\
-    if (GET_MODE (X) == DImode)						\
-      return COSTS_N_INSNS (ix86_cost->add) * 2				\
-	+ (rtx_cost (XEXP (X, 0), OUTER_CODE)				\
-	   << (GET_MODE (XEXP (X, 0)) != DImode))			\
-	+ (rtx_cost (XEXP (X, 1), OUTER_CODE)				\
- 	   << (GET_MODE (XEXP (X, 1)) != DImode));			\
-  case NEG:								\
-  case NOT:								\
-    if (GET_MODE (X) == DImode)						\
-      TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2)			\
-    TOPLEVEL_COSTS_N_INSNS (ix86_cost->add)
-
-
-/* An expression giving the cost of an addressing mode that contains
-   ADDRESS.  If not defined, the cost is computed from the ADDRESS
-   expression and the `CONST_COSTS' values.
-
-   For most CISC machines, the default cost is a good approximation
-   of the true cost of the addressing mode.  However, on RISC
-   machines, all instructions normally have the same length and
-   execution time.  Hence all addresses will have equal costs.
-
-   In cases where more than one form of an address is known, the form
-   with the lowest cost will be used.  If multiple forms have the
-   same, lowest, cost, the one that is the most complex will be used.
-
-   For example, suppose an address that is equal to the sum of a
-   register and a constant is used twice in the same basic block.
-   When this macro is not defined, the address will be computed in a
-   register and memory references will be indirect through that
-   register.  On machines where the cost of the addressing mode
-   containing the sum is no higher than that of a simple indirect
-   reference, this will produce an additional instruction and
-   possibly require an additional register.  Proper specification of
-   this macro eliminates this overhead for such machines.
-
-   Similar use of this macro is made in strength reduction of loops.
-
-   ADDRESS need not be valid as an address.  In such a case, the cost
-   is not relevant and can be any value; invalid addresses need not be
-   assigned a different cost.
-
-   On machines where an address involving more than one register is as
-   cheap as an address computation involving only one register,
-   defining `ADDRESS_COST' to reflect this can cause two registers to
-   be live over a region of code where only one would have been if
-   `ADDRESS_COST' were not defined in that manner.  This effect should
-   be considered in the definition of this macro.  Equivalent costs
-   should probably only be given to addresses with different numbers
-   of registers on machines with lots of registers.
-
-   This macro will normally either not be defined or be defined as a
-   constant.
-
-   For i386, it is better to use a complex address than let gcc copy
-   the address into a reg and make a new pseudo.  But not if the address
-   requires to two regs - that would mean more pseudos with longer
-   lifetimes.  */
-
-#define ADDRESS_COST(RTX) \
-  ((CONSTANT_P (RTX)						\
-    || (GET_CODE (RTX) == PLUS && CONSTANT_P (XEXP (RTX, 1))	\
-	&& REG_P (XEXP (RTX, 0)))) ? 0				\
-   : REG_P (RTX) ? 1						\
-   : 2)
-
-/* A C expression for the cost of moving data of mode M between a
-   register and memory.  A value of 2 is the default; this cost is
-   relative to those in `REGISTER_MOVE_COST'.
-
-   If moving between registers and memory is more expensive than
-   between two registers, you should define this macro to express the
-   relative cost.
-
-   On the i386, copying between floating-point and fixed-point
-   registers is expensive.  */
-
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)				\
-  (((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2))		\
-    || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2))) ? 10	\
-   : 2)
-
-
-/* A C expression for the cost of moving data of mode M between a
-   register and memory.  A value of 2 is the default; this cost is
-   relative to those in `REGISTER_MOVE_COST'.
-
-   If moving between registers and memory is more expensive than
-   between two registers, you should define this macro to express the
-   relative cost.  */
-
-/* #define MEMORY_MOVE_COST(M,C,I) 2  */
-
-/* A C expression for the cost of a branch instruction.  A value of 1
-   is the default; other values are interpreted relative to that.  */
-
-#define BRANCH_COST i386_branch_cost
-
-/* Define this macro as a C expression which is nonzero if accessing
-   less than a word of memory (i.e. a `char' or a `short') is no
-   faster than accessing a word of memory, i.e., if such access
-   require more than one instruction or if there is no difference in
-   cost between byte and (aligned) word loads.
-
-   When this macro is not defined, the compiler will access a field by
-   finding the smallest containing object; when it is defined, a
-   fullword load will be used if alignment permits.  Unless bytes
-   accesses are faster than word accesses, using word accesses is
-   preferable since it may eliminate subsequent memory access if
-   subsequent accesses occur to other fields in the same word of the
-   structure, but to different bytes.  */
-
-#define SLOW_BYTE_ACCESS 0
-
-/* Nonzero if access to memory by shorts is slow and undesirable.  */
-#define SLOW_SHORT_ACCESS 0
-
-/* Define this macro if zero-extension (of a `char' or `short' to an
-   `int') can be done faster if the destination is a register that is
-   known to be zero.
-
-   If you define this macro, you must have instruction patterns that
-   recognize RTL structures like this:
-
-          (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
-   and likewise for `HImode'.  */
-
-/* #define SLOW_ZERO_EXTEND */
-
-/* Define this macro to be the value 1 if unaligned accesses have a
-   cost many times greater than aligned accesses, for example if they
-   are emulated in a trap handler.
-
-   When this macro is non-zero, the compiler will act as if
-   `STRICT_ALIGNMENT' were non-zero when generating code for block
-   moves.  This can cause significantly more instructions to be
-   produced.  Therefore, do not set this macro non-zero if unaligned
-   accesses only add a cycle or two to the time for a memory access.
-
-   If the value of this macro is always zero, it need not be defined.  */
-
-/* #define SLOW_UNALIGNED_ACCESS 0 */
-
-/* Define this macro to inhibit strength reduction of memory
-   addresses.  (On some machines, such strength reduction seems to do
-   harm rather than good.)  */
-
-/* #define DONT_REDUCE_ADDR */
-
-/* Define this macro if it is as good or better to call a constant
-   function address than to call an address kept in a register.
-
-   Desirable on the 386 because a CALL with a constant address is
-   faster than one with a register address.  */
-
-#define NO_FUNCTION_CSE
-
-/* Define this macro if it is as good or better for a function to call
-   itself with an explicit address than to call an address kept in a
-   register.  */
-
-#define NO_RECURSIVE_FUNCTION_CSE
-
-/* A C statement (sans semicolon) to update the integer variable COST
-   based on the relationship between INSN that is dependent on
-   DEP_INSN through the dependence LINK.  The default is to make no
-   adjustment to COST.  This can be used for example to specify to
-   the scheduler that an output- or anti-dependence does not incur
-   the same cost as a data-dependence.  */
-
-#define ADJUST_COST(insn,link,dep_insn,cost)				\
-     (cost) = x86_adjust_cost(insn, link, dep_insn, cost)
-
-#define ADJUST_BLOCKAGE(last_insn,insn,blockage)			\
-{									\
-  if (is_fp_store (last_insn) && is_fp_insn (insn)			\
-      && NEXT_INSN (last_insn) && NEXT_INSN (NEXT_INSN (last_insn))	\
-      && NEXT_INSN (NEXT_INSN (NEXT_INSN (last_insn)))			\
-      && (GET_CODE (NEXT_INSN (last_insn)) == INSN)			\
-      && (GET_CODE (NEXT_INSN (NEXT_INSN (last_insn))) == JUMP_INSN)	\
-      && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (last_insn)))) == NOTE) \
-      && (NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (last_insn)))) \
-	  == NOTE_INSN_LOOP_END))					\
-    {									\
-      (blockage) = 3;							\
-    }									\
-}
-
-#define ISSUE_RATE ((int)ix86_cpu > (int)PROCESSOR_I486 ? 2 : 1)
-
-
-/* Add any extra modes needed to represent the condition code.
-
-   For the i386, we need separate modes when floating-point equality
-   comparisons are being done.  */
-
-#define EXTRA_CC_MODES CCFPEQmode
-
-/* Define the names for the modes specified above.  */
-#define EXTRA_CC_NAMES "CCFPEQ"
-
-/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
-   return the mode to be used for the comparison.
-
-   For floating-point equality comparisons, CCFPEQmode should be used.
-   VOIDmode should be used in all other cases.  */
-
-#define SELECT_CC_MODE(OP,X,Y) \
-  (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT			\
-   && ((OP) == EQ || (OP) == NE) ? CCFPEQmode : VOIDmode)
-
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  Note that we can't use "rtx" here
-   since it hasn't been defined!  */
-
-extern struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  */
-
-/* Set if the cc value was actually from the 80387 and
-   we are testing eax directly (i.e. no sahf) */
-#define CC_TEST_AX 020000
-
-/* Set if the cc value is actually in the 80387, so a floating point
-   conditional branch must be output.  */
-#define CC_IN_80387 04000
-
-/* Set if the CC value was stored in a nonstandard way, so that
-   the state of equality is indicated by zero in the carry bit.  */
-#define CC_Z_IN_NOT_C 010000
-
-/* Set if the CC value was actually from the 80387 and loaded directly
-   into the eflags instead of via eax/sahf.  */
-#define CC_FCOMI 040000
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-  notice_update_cc((EXP))
-
-/* Output a signed jump insn.  Use template NORMAL ordinarily, or
-   FLOAT following a floating point comparison.
-   Use NO_OV following an arithmetic insn that set the cc's
-   before a test insn that was deleted.
-   NO_OV may be zero, meaning final should reinsert the test insn
-   because the jump cannot be handled properly without it.  */
-
-#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV)			\
-{								\
-  if (cc_prev_status.flags & CC_IN_80387)			\
-    return FLOAT;						\
-  if (cc_prev_status.flags & CC_NO_OVERFLOW)			\
-    return NO_OV;						\
-  return NORMAL;						\
-}
-
-/* Control the assembler format that we output, to the extent
-   this does not vary between assemblers.  */
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above). */
-
-/* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
-   For non floating point regs, the following are the HImode names.
-
-   For float regs, the stack top is sometimes referred to as "%st(0)"
-   instead of just "%st".  PRINT_REG handles this with the "y" code.  */
-
-#define HI_REGISTER_NAMES \
-{"ax","dx","cx","bx","si","di","bp","sp",          \
- "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","" }
-
-#define REGISTER_NAMES HI_REGISTER_NAMES
-
-/* Table of additional register names to use in user input.  */
-
-#define ADDITIONAL_REGISTER_NAMES \
-{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 },	\
-  { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 },	\
-  { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 },		\
-  { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
-
-/* Note we are omitting these since currently I don't know how
-to get gcc to use these, since they want the same but different
-number as al, and ax.
-*/
-
-/* note the last four are not really qi_registers, but
-   the md will have to never output movb into one of them
-   only a movw .  There is no movb into the last four regs */
-
-#define QI_REGISTER_NAMES \
-{"al", "dl", "cl", "bl", "si", "di", "bp", "sp",}
-
-/* These parallel the array above, and can be used to access bits 8:15
-   of regs 0 through 3. */
-
-#define QI_HIGH_REGISTER_NAMES \
-{"ah", "dh", "ch", "bh", }
-
-/* How to renumber registers for dbx and gdb.  */
-
-/* {0,2,1,3,6,7,4,5,12,13,14,15,16,17}  */
-#define DBX_REGISTER_NUMBER(n) \
-((n) == 0 ? 0 : \
- (n) == 1 ? 2 : \
- (n) == 2 ? 1 : \
- (n) == 3 ? 3 : \
- (n) == 4 ? 6 : \
- (n) == 5 ? 7 : \
- (n) == 6 ? 4 : \
- (n) == 7 ? 5 : \
- (n) + 4)
-
-/* Before the prologue, RA is at 0(%esp).  */
-#define INCOMING_RETURN_ADDR_RTX \
-  gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
-
-/* After the prologue, RA is at -4(AP) in the current frame.  */
-#define RETURN_ADDR_RTX(COUNT, FRAME)					\
-  ((COUNT) == 0								\
-   ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, arg_pointer_rtx, GEN_INT(-4)))\
-   : gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, (FRAME), GEN_INT(4))))
-
-/* PC is dbx register 8; let's use that column for RA. */
-#define DWARF_FRAME_RETURN_COLUMN 	8
-
-/* Before the prologue, the top of the frame is at 4(%esp).  */
-#define INCOMING_FRAME_SP_OFFSET 4
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  (assemble_name (FILE, NAME), fputs (":\n", FILE))
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
-do { long l[2];								\
-     REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l);				\
-     fprintf (FILE, "%s 0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]);		\
-   } while (0)
-
-/* This is how to output a `long double' extended real constant. */
-
-#undef ASM_OUTPUT_LONG_DOUBLE
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE)  		\
-do { long l[3];						\
-     REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l);	\
-     fprintf (FILE, "%s 0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \
-   } while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)			\
-do { long l;						\
-     REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-     fprintf ((FILE), "%s 0x%lx\n", ASM_LONG, l);	\
-   } while (0)
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "%s ", ASM_LONG),		\
-  output_addr_const (FILE,(VALUE)),		\
-  putc('\n',FILE))
-
-/* Likewise for `char' and `short' constants.  */
-/* is this supposed to do align too?? */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "%s ", ASM_SHORT),		\
-  output_addr_const (FILE,(VALUE)),		\
-  putc('\n',FILE))
-
-/*
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "%s ", ASM_BYTE_OP),		\
-  output_addr_const (FILE,(VALUE)),		\
-  fputs (",", FILE),		      		\
-  output_addr_const (FILE,(VALUE)),		\
-  fputs (" >> 8\n",FILE))
-*/
-
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "%s ", ASM_BYTE_OP),		\
-  output_addr_const (FILE, (VALUE)),		\
-  putc ('\n', FILE))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf ((FILE), "%s 0x%x\n", ASM_BYTE_OP, (VALUE))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tpushl %%e%s\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tpopl %%e%s\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute.
-     */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "%s %s%d\n", ASM_LONG, LPREFIX, VALUE)
-
-/* This is how to output an element of a case-vector that is relative.
-   We don't use these on the 386 yet, because the ATT assembler can't do
-   forward reference the differences.  
- */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t.word %s%d-%s%d\n",LPREFIX, VALUE,LPREFIX, REL)
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN ""
-#define ASM_CLOSE_PAREN ""
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   The CODE z takes the size of operand from the following digit, and
-   outputs b,w,or l respectively.
-
-   On the 80386, we use several such letters:
-   f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
-   L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
-   R -- print the prefix for register names.
-   z -- print the opcode suffix for the size of the current operand.
-   * -- print a star (in certain assembler syntax)
-   P -- if PIC, print an @PLT suffix.
-   X -- don't print any sort of PIC '@' suffix for a symbol.
-   J -- print jump insn for arithmetic_comparison_operator.
-   s -- ??? something to do with double shifts.  not actually used, afaik.
-   C -- print a conditional move suffix corresponding to the op code.
-   c -- likewise, but reverse the condition.
-   F,f -- likewise, but for floating-point.  */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)				\
-  ((CODE) == '*')
-
-/* Print the name of a register based on its machine mode and number.
-   If CODE is 'w', pretend the mode is HImode.
-   If CODE is 'b', pretend the mode is QImode.
-   If CODE is 'k', pretend the mode is SImode.
-   If CODE is 'h', pretend the reg is the `high' byte register.
-   If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
-
-extern char *hi_reg_name[];
-extern char *qi_reg_name[];
-extern char *qi_high_reg_name[];
-
-#define PRINT_REG(X, CODE, FILE) \
-  do { if (REGNO (X) == ARG_POINTER_REGNUM)		\
-	 abort ();					\
-       fprintf (FILE, "%s", RP);			\
-       switch ((CODE == 'w' ? 2 			\
-		: CODE == 'b' ? 1			\
-		: CODE == 'k' ? 4			\
-		: CODE == 'y' ? 3			\
-		: CODE == 'h' ? 0			\
-		: GET_MODE_SIZE (GET_MODE (X))))	\
-	 {						\
-	 case 3:					\
-	   if (STACK_TOP_P (X))				\
-	     {						\
-	       fputs ("st(0)", FILE);			\
-	       break;					\
-	     }						\
-	 case 4:					\
-	 case 8:					\
-	 case 12:					\
-	   if (! FP_REG_P (X)) fputs ("e", FILE);	\
-	 case 2:					\
-	   fputs (hi_reg_name[REGNO (X)], FILE);	\
-	   break;					\
-	 case 1:					\
-	   fputs (qi_reg_name[REGNO (X)], FILE);	\
-	   break;					\
-	 case 0:					\
-	   fputs (qi_high_reg_name[REGNO (X)], FILE);	\
-	   break;					\
-	 }						\
-     } while (0)
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-  print_operand (FILE, X, CODE)
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-  print_operand_address (FILE, ADDR)
-
-/* Print the name of a register for based on its machine mode and number.
-   This macro is used to print debugging output.
-   This macro is different from PRINT_REG in that it may be used in
-   programs that are not linked with aux-output.o.  */
-
-#define DEBUG_PRINT_REG(X, CODE, FILE) \
-  do { static char *hi_name[] = HI_REGISTER_NAMES;	\
-       static char *qi_name[] = QI_REGISTER_NAMES;	\
-       fprintf (FILE, "%d %s", REGNO (X), RP);	\
-       if (REGNO (X) == ARG_POINTER_REGNUM)		\
-	 { fputs ("argp", FILE); break; }		\
-       if (STACK_TOP_P (X))				\
-	 { fputs ("st(0)", FILE); break; }		\
-       if (FP_REG_P (X))				\
-	 { fputs (hi_name[REGNO(X)], FILE); break; }	\
-       switch (GET_MODE_SIZE (GET_MODE (X)))		\
-	 {						\
-	 default:					\
-	   fputs ("e", FILE);				\
-	 case 2:					\
-	   fputs (hi_name[REGNO (X)], FILE);		\
-	   break;					\
-	 case 1:					\
-	   fputs (qi_name[REGNO (X)], FILE);		\
-	   break;					\
-	 }						\
-     } while (0)
-
-/* Output the prefix for an immediate operand, or for an offset operand.  */
-#define PRINT_IMMED_PREFIX(FILE)  fputs (IP, (FILE))
-#define PRINT_OFFSET_PREFIX(FILE)  fputs (IP, (FILE))
-
-/* Routines in libgcc that return floats must return them in an fp reg,
-   just as other functions do which return such values.
-   These macros make that happen.  */
-
-#define FLOAT_VALUE_TYPE float
-#define INTIFY(FLOATVAL) FLOATVAL
-
-/* Nonzero if INSN magically clobbers register REGNO.  */
-
-/* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO)	\
-    (FP_REGNO_P (REGNO)				\
-     && (GET_CODE (INSN) == JUMP_INSN || GET_CODE (INSN) == BARRIER))
-*/
-
-/* a letter which is not needed by the normal asm syntax, which
-   we can use for operand syntax in the extended asm */
-
-#define ASM_OPERAND_LETTER '#'
-#define RET return ""
-#define AT_SP(mode) (gen_rtx_MEM ((mode), stack_pointer_rtx))
-
-/* Helper macros to expand a binary/unary operator if needed */
-#define IX86_EXPAND_BINARY_OPERATOR(OP, MODE, OPERANDS)			\
-do {									\
-  if (!ix86_expand_binary_operator (OP, MODE, OPERANDS))		\
-    FAIL;								\
-} while (0)
-
-#define IX86_EXPAND_UNARY_OPERATOR(OP, MODE, OPERANDS)			\
-do {									\
-  if (!ix86_expand_unary_operator (OP, MODE, OPERANDS,))		\
-    FAIL;								\
-} while (0)
-
-
-/* Functions in i386.c */
-extern void override_options ();
-extern void order_regs_for_local_alloc ();
-extern char *output_strlen_unroll ();
-extern struct rtx_def *i386_sext16_if_const ();
-extern int i386_aligned_p ();
-extern int i386_cc_probably_useless_p ();
-extern int i386_valid_decl_attribute_p ();
-extern int i386_valid_type_attribute_p ();
-extern int i386_return_pops_args ();
-extern int i386_comp_type_attributes ();
-extern void init_cumulative_args ();
-extern void function_arg_advance ();
-extern struct rtx_def *function_arg ();
-extern int function_arg_partial_nregs ();
-extern char *output_strlen_unroll ();
-extern void output_op_from_reg ();
-extern void output_to_reg ();
-extern char *singlemove_string ();
-extern char *output_move_double ();
-extern char *output_move_memory ();
-extern char *output_move_pushmem ();
-extern int standard_80387_constant_p ();
-extern char *output_move_const_single ();
-extern int symbolic_operand ();
-extern int call_insn_operand ();
-extern int expander_call_insn_operand ();
-extern int symbolic_reference_mentioned_p ();
-extern int ix86_expand_binary_operator ();
-extern int ix86_binary_operator_ok ();
-extern int ix86_expand_unary_operator ();
-extern int ix86_unary_operator_ok ();
-extern void emit_pic_move ();
-extern void function_prologue ();
-extern int simple_386_epilogue ();
-extern void function_epilogue ();
-extern int legitimate_address_p ();
-extern struct rtx_def *legitimize_pic_address ();
-extern struct rtx_def *legitimize_address ();
-extern void print_operand ();
-extern void print_operand_address ();
-extern void notice_update_cc ();
-extern void split_di ();
-extern int binary_387_op ();
-extern int shift_op ();
-extern int VOIDmode_compare_op ();
-extern char *output_387_binary_op ();
-extern char *output_fix_trunc ();
-extern char *output_float_compare ();
-extern char *output_fp_cc0_set ();
-extern void save_386_machine_status ();
-extern void restore_386_machine_status ();
-extern void clear_386_stack_locals ();
-extern struct rtx_def *assign_386_stack_local ();
-extern int is_mul ();
-extern int is_div ();
-extern int last_to_set_cc ();
-extern int doesnt_set_condition_code ();
-extern int sets_condition_code ();
-extern int str_immediate_operand ();
-extern int is_fp_insn ();
-extern int is_fp_dest ();
-extern int is_fp_store ();
-extern int agi_dependent ();
-extern int reg_mentioned_in_mem ();
-extern char *output_int_conditional_move ();
-extern char *output_fp_conditional_move ();
-extern int ix86_can_use_return_insn_p ();
-
-#ifdef NOTYET
-extern struct rtx_def *copy_all_rtx ();
-extern void rewrite_address ();
-#endif
-
-/* Variables in i386.c */
-extern char *ix86_cpu_string;			/* for -mcpu=<xxx> */
-extern char *ix86_arch_string;			/* for -march=<xxx> */
-extern char *i386_reg_alloc_order;		/* register allocation order */
-extern char *i386_regparm_string;		/* # registers to use to pass args */
-extern char *i386_align_loops_string;		/* power of two alignment for loops */
-extern char *i386_align_jumps_string;		/* power of two alignment for non-loop jumps */
-extern char *i386_align_funcs_string;		/* power of two alignment for functions */
-extern char *i386_branch_cost_string;		/* values 1-5: see jump.c */
-extern int i386_regparm;			/* i386_regparm_string as a number */
-extern int i386_align_loops;			/* power of two alignment for loops */
-extern int i386_align_jumps;			/* power of two alignment for non-loop jumps */
-extern int i386_align_funcs;			/* power of two alignment for functions */
-extern int i386_branch_cost;			/* values 1-5: see jump.c */
-extern char *hi_reg_name[];			/* names for 16 bit regs */
-extern char *qi_reg_name[];			/* names for 8 bit regs (low) */
-extern char *qi_high_reg_name[];		/* names for 8 bit regs (high) */
-extern enum reg_class regclass_map[];		/* smalled class containing REGNO */
-extern struct rtx_def *i386_compare_op0;	/* operand 0 for comparisons */
-extern struct rtx_def *i386_compare_op1;	/* operand 1 for comparisons */
-
-/* External variables used */
-extern int optimize;				/* optimization level */
-extern int obey_regdecls;			/* TRUE if stupid register allocation */
-
-/* External functions used */
-extern struct rtx_def *force_operand ();
-
-
-/*
-Local variables:
-version-control: t
-End:
-*/
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
deleted file mode 100755
index b036b5d..0000000
--- a/gcc/config/i386/i386.md
+++ /dev/null
@@ -1,7732 +0,0 @@
-; GCC machine description for Intel X86.
-;; Copyright (C) 1988, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
-;; Mostly by William Schelter.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA. */
-
-;; The original PO technology requires these to be ordered by speed,
-;; so that assigner will pick the fastest.
-
-;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
-;; updates for most instructions.
-
-;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
-;; constraint letters.
-
-;; the special asm out single letter directives following a '%' are:
-;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
-;;     operands[1].
-;; 'L' Print the opcode suffix for a 32-bit integer opcode.
-;; 'W' Print the opcode suffix for a 16-bit integer opcode.
-;; 'B' Print the opcode suffix for an 8-bit integer opcode.
-;; 'Q' Print the opcode suffix for a 64-bit float opcode.
-;; 'S' Print the opcode suffix for a 32-bit float opcode.
-;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
-;; 'J' Print the appropriate jump operand.
-
-;; 'b' Print the QImode name of the register for the indicated operand.
-;;     %b0 would print %al if operands[0] is reg 0.
-;; 'w' Likewise, print the HImode name of the register.
-;; 'k' Likewise, print the SImode name of the register.
-;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
-;; 'y' Print "st(0)" instead of "st" as a register.
-
-;; UNSPEC usage:
-;; 0  This is a `scas' operation.  The mode of the UNSPEC is always SImode.
-;;    operand 0 is the memory address to scan.
-;;    operand 1 is a register containing the value to scan for.  The mode
-;;       of the scas opcode will be the same as the mode of this operand.
-;;    operand 2 is the known alignment of operand 0.
-;; 1  This is a `sin' operation.  The mode of the UNSPEC is MODE_FLOAT.
-;;    operand 0 is the argument for `sin'.
-;; 2  This is a `cos' operation.  The mode of the UNSPEC is MODE_FLOAT.
-;;    operand 0 is the argument for `cos'.
-;; 3  This is part of a `stack probe' operation.  The mode of the UNSPEC is 
-;;    always SImode.  operand 0 is the size of the stack allocation.
-;; 4  This is the source of a fake SET of the frame pointer which is used to
-;;    prevent insns referencing it being scheduled across the initial
-;;    decrement of the stack pointer.
-;; 5  This is a `bsf' operation.
-;; 6  This is the @GOT offset of a PIC address.
-;; 7  This is the @GOTOFF offset of a PIC address.
-;; 8  This is a reference to a symbol's @PLT address.
-
-;; This shadows the processor_type enumeration, so changes must be made
-;; to i386.h at the same time.
-
-(define_attr "type"
-  "integer,binary,memory,test,compare,fcompare,idiv,imul,lea,fld,fpop,fpdiv,fpmul"
-  (const_string "integer"))
-
-(define_attr "memory" "none,load,store"
-  (cond [(eq_attr "type" "idiv,lea")
-	 (const_string "none")
-
-	 (eq_attr "type" "fld")
-	 (const_string "load")
-
-	 (eq_attr "type" "test")
-	 (if_then_else (match_operand 0 "memory_operand" "")
-		       (const_string "load")
-		       (const_string "none"))
-
-	 (eq_attr "type" "compare,fcompare")
-	 (if_then_else (ior (match_operand 0 "memory_operand" "")
-			    (match_operand 1 "memory_operand" ""))
-		       (const_string "load")
-		       (const_string "none"))
-
-	 (and (eq_attr "type" "integer,memory,fpop")
-	      (match_operand 0 "memory_operand" ""))
-	 (const_string "store")
-
-	 (and (eq_attr "type" "integer,memory,fpop")
-	      (match_operand 1 "memory_operand" ""))
-	 (const_string "load")
-
-	 (and (eq_attr "type" "binary,imul,fpmul,fpdiv")
-	      (ior (match_operand 1 "memory_operand" "")
-		   (match_operand 2 "memory_operand" "")))
-	 (const_string "load")]
-
-	(const_string "none")))
-
-;; Functional units
-
-; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
-;                       TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
-
-; pentiumpro has a reservation station with 5 ports
-; port  0 has integer, float add, integer divide, float divide, float 
-;        multiply, and shifter units.
-; port  1 has integer, and jump units.
-; port  2 has the load address generation unit
-; ports 3 and 4 have the store address generation units
-
-; pentium has two integer pipelines, the main u pipe and the secondary v pipe.
-; and a float pipeline
-
-;; Floating point
-
-(define_function_unit "fp" 1 0
- (and (eq_attr "type" "fpop,fcompare") (eq_attr "cpu" "i386,i486"))
- 5 5)
-
-(define_function_unit "fp" 1 0
- (and (eq_attr "type" "fpop,fcompare") (eq_attr "cpu" "pentium,pentiumpro")) 
- 3 0)
-
-(define_function_unit "fp" 1 0
- (and (eq_attr "type" "fpmul") (eq_attr "cpu" "pentium")) 
- 7 0)
-
-(define_function_unit "fp" 1 0
- (and (eq_attr "type" "fpmul") (eq_attr "cpu" "pentiumpro")) 
- 5 0)
-
-(define_function_unit "fp" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "pentiumpro")) 
- 10 10)
-
-(define_function_unit "fp" 1 0
- (and (eq_attr "type" "imul") (eq_attr "cpu" "pentiumpro")) 
- 6 0)
-
-(define_function_unit "fp" 1 0
- (eq_attr "type" "fpdiv") 
- 10 10)
-
-(define_function_unit "fp" 1 0
-  (and (eq_attr "type" "fld") (eq_attr "cpu" "!pentiumpro,k6"))
- 1 0)
-
-;; K6 FPU is not pipelined.
-(define_function_unit "fp" 1 0
-  (and (eq_attr "type" "fpop,fpmul,fcompare") (eq_attr "cpu" "k6"))
- 2 2)
-
-;; i386 and i486 have one integer unit, which need not be modeled
-
-(define_function_unit "integer" 2 0
-  (and (eq_attr "type" "integer,binary,test,compare,lea") (eq_attr "cpu" "pentium,pentiumpro"))
- 1 0)
-
-(define_function_unit "integer" 2 0
-  (and (eq_attr "cpu" "k6")
-       (and (eq_attr "type" "integer,binary,test,compare")
-	    (eq_attr "memory" "!load")))
-  1 0)
-
-;; Internally, K6 converts REG OP MEM instructions into a load (2 cycles)
-;; and a register operation (1 cycle).
-(define_function_unit "integer" 2 0
-  (and (eq_attr "cpu" "k6")
-       (and (eq_attr "type" "integer,binary,test,compare")
-	    (eq_attr "memory" "load")))
-  3 0)
-
-;; Multiplies use one of the integer units
-(define_function_unit "integer" 2 0
-  (and (eq_attr "cpu" "pentium") (eq_attr "type" "imul"))
-  11 11)
-
-(define_function_unit "integer" 2 0
-  (and (eq_attr "cpu" "k6") (eq_attr "type" "imul"))
-  2 2)
-
-(define_function_unit "integer" 2 0
-  (and (eq_attr "cpu" "pentium") (eq_attr "type" "idiv"))
-  25 25)
-
-(define_function_unit "integer" 2 0
-  (and (eq_attr "cpu" "k6") (eq_attr "type" "idiv"))
-  17 17)
-
-;; Pentium Pro and K6 have a separate load unit.
-(define_function_unit "load" 1 0
-  (and (eq_attr "cpu" "pentiumpro") (eq_attr "memory" "load"))
-  3 0)
-
-(define_function_unit "load" 1 0
-  (and (eq_attr "cpu" "k6") (eq_attr "memory" "load"))
-  2 0)
-
-;; Pentium Pro and K6 have a separate store unit.
-(define_function_unit "store" 1 0
-  (and (eq_attr "cpu" "pentiumpro,k6") (eq_attr "memory" "store"))
-  1 0)
-
-;; lea executes in the K6 store unit with 1 cycle latency
-(define_function_unit "store" 1 0
-  (and (eq_attr "cpu" "k6") (eq_attr "type" "lea"))
-  1 0)
-
-
-;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM".
-;; But restricting MEM here would mean that gcc could not remove a redundant
-;; test in cases like "incl MEM / je TARGET".
-;;
-;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
-;; be folded while optimizing anyway.
-
-;; All test insns have expanders that save the operands away without
-;; actually generating RTL.  The bCOND or sCOND (emitted immediately
-;; after the tstM or cmp) will actually emit the tstM or cmpM.
-
-;; Processor type -- this attribute must exactly match the processor_type
-;; enumeration in i386.h.
-
-(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6"
-  (const (symbol_ref "ix86_cpu")))
-
-(define_insn "tstsi_1"
-  [(set (cc0)
-	(match_operand:SI 0 "nonimmediate_operand" "rm"))]
-  ""
-  "*
-{
-  if (REG_P (operands[0]))
-    return AS2 (test%L0,%0,%0);
-
-  operands[1] = const0_rtx;
-  return AS2 (cmp%L0,%1,%0);
-}"
-  [(set_attr "type" "test")])
-
-(define_expand "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "nonimmediate_operand" ""))]
-  ""
-  "
-{
-  i386_compare_gen = gen_tstsi_1;
-  i386_compare_op0 = operands[0];
-  i386_compare_op1 = const0_rtx;
-  DONE;
-}")
-
-(define_insn "tsthi_1"
-  [(set (cc0)
-	(match_operand:HI 0 "nonimmediate_operand" "rm"))]
-  ""
-  "*
-{
-  if (REG_P (operands[0]))
-    return AS2 (test%W0,%0,%0);
-
-  operands[1] = const0_rtx;
-  return AS2 (cmp%W0,%1,%0);
-}"
-  [(set_attr "type" "test")])
-
-(define_expand "tsthi"
-  [(set (cc0)
-	(match_operand:HI 0 "nonimmediate_operand" ""))]
-  ""
-  "
-{
-  i386_compare_gen = gen_tsthi_1;
-  i386_compare_op0 = operands[0];
-  i386_compare_op1 = const0_rtx;
-  DONE;
-}")
-
-(define_insn "tstqi_1"
-  [(set (cc0)
-	(match_operand:QI 0 "nonimmediate_operand" "qm"))]
-  ""
-  "*
-{
-  if (REG_P (operands[0]))
-    return AS2 (test%B0,%0,%0);
-
-  operands[1] = const0_rtx;
-  return AS2 (cmp%B0,%1,%0);
-}"
-  [(set_attr "type" "test")])
-
-(define_expand "tstqi"
-  [(set (cc0)
-	(match_operand:QI 0 "nonimmediate_operand" ""))]
-  ""
-  "
-{
-  i386_compare_gen = gen_tstqi_1;
-  i386_compare_op0 = operands[0];
-  i386_compare_op1 = const0_rtx;
-  DONE;
-}")
-
-(define_insn "tstsf_cc"
-  [(set (cc0)
-	(match_operand:SF 0 "register_operand" "f"))
-   (clobber (match_scratch:HI 1 "=a"))]
-  "TARGET_80387 && ! TARGET_IEEE_FP"
-  "*
-{
-  if (! STACK_TOP_P (operands[0]))
-    abort ();
-
-  output_asm_insn (\"ftst\", operands);
-
-  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
-    output_asm_insn (AS1 (fstp,%y0), operands);
-
-  return output_fp_cc0_set (insn);
-}"
-  [(set_attr "type" "test")])
-
-;; Don't generate tstsf if generating IEEE code, since the `ftst' opcode
-;; isn't IEEE compliant.
-
-(define_expand "tstsf"
-  [(parallel [(set (cc0)
-		   (match_operand:SF 0 "register_operand" ""))
-	      (clobber (match_scratch:HI 1 ""))])]
-  "TARGET_80387 && ! TARGET_IEEE_FP"
-  "
-{
-  i386_compare_gen = gen_tstsf_cc;
-  i386_compare_op0 = operands[0];
-  i386_compare_op1 = const0_rtx;
-  DONE;
-}")
-
-(define_insn "tstdf_cc"
-  [(set (cc0)
-	(match_operand:DF 0 "register_operand" "f"))
-   (clobber (match_scratch:HI 1 "=a"))]
-  "TARGET_80387 && ! TARGET_IEEE_FP"
-  "*
-{
-  if (! STACK_TOP_P (operands[0]))
-    abort ();
-
-  output_asm_insn (\"ftst\", operands);
-
-  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
-    output_asm_insn (AS1 (fstp,%y0), operands);
-
-  return output_fp_cc0_set (insn);
-}"
-  [(set_attr "type" "test")])
-
-;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode
-;; isn't IEEE compliant.
-
-(define_expand "tstdf"
-  [(parallel [(set (cc0)
-		   (match_operand:DF 0 "register_operand" ""))
-	      (clobber (match_scratch:HI 1 ""))])]
-  "TARGET_80387 && ! TARGET_IEEE_FP"
-  "
-{
-  i386_compare_gen = gen_tstdf_cc;
-  i386_compare_op0 = operands[0];
-  i386_compare_op1 = const0_rtx;
-  DONE;
-}")
-
-(define_insn "tstxf_cc"
-  [(set (cc0)
-	(match_operand:XF 0 "register_operand" "f"))
-   (clobber (match_scratch:HI 1 "=a"))]
-  "TARGET_80387 && ! TARGET_IEEE_FP"
-  "*
-{
-  if (! STACK_TOP_P (operands[0]))
-    abort ();
-
-  output_asm_insn (\"ftst\", operands);
-
-  if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
-    output_asm_insn (AS1 (fstp,%y0), operands);
-
-  return output_fp_cc0_set (insn);
-}"
-  [(set_attr "type" "test")])
-
-;; Don't generate tstxf if generating IEEE code, since the `ftst' opcode
-;; isn't IEEE compliant.
-
-(define_expand "tstxf"
-  [(parallel [(set (cc0)
-		   (match_operand:XF 0 "register_operand" ""))
-	      (clobber (match_scratch:HI 1 ""))])]
-  "TARGET_80387 && ! TARGET_IEEE_FP"
-  "
-{
-  i386_compare_gen = gen_tstxf_cc;
-  i386_compare_op0 = operands[0];
-  i386_compare_op1 = const0_rtx;
-  DONE;
-}")
-
-;;- compare instructions.  See comments above tstM patterns about
-;;  expansion of these insns.
-
-(define_insn "cmpsi_1"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "mr,r")
-		 (match_operand:SI 1 "general_operand" "ri,mr")))]
-  "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
-  "* return AS2 (cmp%L0,%1,%0);"
-  [(set_attr "type" "compare")])
-
-(define_expand "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "")
-		 (match_operand:SI 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-    operands[0] = force_reg (SImode, operands[0]);
-
-  i386_compare_gen = gen_cmpsi_1;
-  i386_compare_op0 = operands[0];
-  i386_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_insn "cmphi_1"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "nonimmediate_operand" "mr,r")
-		 (match_operand:HI 1 "general_operand" "ri,mr")))]
-  "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
-  "* return AS2 (cmp%W0,%1,%0);"
-  [(set_attr "type" "compare")])
-
-(define_expand "cmphi"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "nonimmediate_operand" "")
-		 (match_operand:HI 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-    operands[0] = force_reg (HImode, operands[0]);
-
-  i386_compare_gen = gen_cmphi_1;
-  i386_compare_op0 = operands[0];
-  i386_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_insn "cmpqi_1"
-  [(set (cc0)
-	(compare (match_operand:QI 0 "nonimmediate_operand" "q,mq")
-		 (match_operand:QI 1 "general_operand" "qm,nq")))]
-  "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
-  "* return AS2 (cmp%B0,%1,%0);"
-  [(set_attr "type" "compare")])
-
-(define_expand "cmpqi"
-  [(set (cc0)
-	(compare (match_operand:QI 0 "nonimmediate_operand" "")
-		 (match_operand:QI 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-    operands[0] = force_reg (QImode, operands[0]);
-
-  i386_compare_gen = gen_cmpqi_1;
-  i386_compare_op0 = operands[0];
-  i386_compare_op1 = operands[1];
-  DONE;
-}")
-
-;; These implement float point compares.  For each of DFmode and
-;; SFmode, there is the normal insn, and an insn where the second operand
-;; is converted to the desired mode.
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(match_operand:XF 0 "register_operand" "f")
-			 (match_operand:XF 1 "register_operand" "f")]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(match_operand:XF 0 "register_operand" "f")
-			 (float:XF
-			  (match_operand:SI 1 "nonimmediate_operand" "rm"))]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(float:XF
-			  (match_operand:SI 0 "nonimmediate_operand" "rm"))
-			 (match_operand:XF 1 "register_operand" "f")]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(match_operand:XF 0 "register_operand" "f")
-			 (float_extend:XF
-			  (match_operand:DF 1 "nonimmediate_operand" "fm"))]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(float_extend:XF
-			  (match_operand:DF 0 "nonimmediate_operand" "fm"))
-			 (match_operand:XF 1 "register_operand" "f")]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(match_operand:XF 0 "register_operand" "f")
-			 (float_extend:XF
-			  (match_operand:SF 1 "nonimmediate_operand" "fm"))]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(float_extend:XF
-			  (match_operand:SF 0 "nonimmediate_operand" "fm"))
-			 (match_operand:XF 1 "register_operand" "f")]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(compare:CCFPEQ (match_operand:XF 0 "register_operand" "f")
-			(match_operand:XF 1 "register_operand" "f")))
-   (clobber (match_scratch:HI 2 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(match_operand:DF 0 "nonimmediate_operand" "f,fm")
-			 (match_operand:DF 1 "nonimmediate_operand" "fm,f")]))
-   (clobber (match_scratch:HI 3 "=a,a"))]
-  "TARGET_80387
-   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(match_operand:DF 0 "register_operand" "f")
-			 (float:DF
-			  (match_operand:SI 1 "nonimmediate_operand" "rm"))]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(float:DF
-			  (match_operand:SI 0 "nonimmediate_operand" "rm"))
-			 (match_operand:DF 1 "register_operand" "f")]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(match_operand:DF 0 "register_operand" "f")
-			 (float_extend:DF
-			  (match_operand:SF 1 "nonimmediate_operand" "fm"))]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(float_extend:DF
-			  (match_operand:SF 0 "nonimmediate_operand" "fm"))
-			 (match_operand:DF 1 "register_operand" "f")]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(float_extend:DF
-			  (match_operand:SF 0 "register_operand" "f"))
-			 (match_operand:DF 1 "nonimmediate_operand" "fm")]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(compare:CCFPEQ (match_operand:DF 0 "register_operand" "f")
-			(match_operand:DF 1 "register_operand" "f")))
-   (clobber (match_scratch:HI 2 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-;; These two insns will never be generated by combine due to the mode of
-;; the COMPARE.
-;(define_insn ""
-;  [(set (cc0)
-;	(compare:CCFPEQ (match_operand:DF 0 "register_operand" "f")
-;			(float_extend:DF
-;			 (match_operand:SF 1 "register_operand" "f"))))
-;   (clobber (match_scratch:HI 2 "=a"))]
-;  "TARGET_80387"
-;  "* return output_float_compare (insn, operands);")
-;
-;(define_insn ""
-;  [(set (cc0)
-;	(compare:CCFPEQ (float_extend:DF
-;			 (match_operand:SF 0 "register_operand" "f"))
-;			(match_operand:DF 1 "register_operand" "f")))
-;   (clobber (match_scratch:HI 2 "=a"))]
-;  "TARGET_80387"
-;  "* return output_float_compare (insn, operands);")
-
-(define_insn "*cmpsf_cc_1"
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(match_operand:SF 0 "nonimmediate_operand" "f,fm")
-			 (match_operand:SF 1 "nonimmediate_operand" "fm,f")]))
-   (clobber (match_scratch:HI 3 "=a,a"))]
-  "TARGET_80387
-   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(match_operand:SF 0 "register_operand" "f")
-			 (float:SF
-			  (match_operand:SI 1 "nonimmediate_operand" "rm"))]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(match_operator 2 "VOIDmode_compare_op"
-			[(float:SF
-			  (match_operand:SI 0 "nonimmediate_operand" "rm"))
-			 (match_operand:SF 1 "register_operand" "f")]))
-   (clobber (match_scratch:HI 3 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_insn ""
-  [(set (cc0)
-	(compare:CCFPEQ (match_operand:SF 0 "register_operand" "f")
-			(match_operand:SF 1 "register_operand" "f")))
-   (clobber (match_scratch:HI 2 "=a"))]
-  "TARGET_80387"
-  "* return output_float_compare (insn, operands);"
-  [(set_attr "type" "fcompare")])
-
-(define_expand "cmpxf"
-  [(set (cc0)
-	(compare (match_operand:XF 0 "register_operand" "")
-		 (match_operand:XF 1 "register_operand" "")))]
-  "TARGET_80387"
-  "
-{
-  i386_compare_gen = gen_cmpxf_cc;
-  i386_compare_gen_eq = gen_cmpxf_ccfpeq;
-  i386_compare_op0 = operands[0];
-  i386_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "register_operand" "")
-		 (match_operand:DF 1 "general_operand" "")))]
-  "TARGET_80387"
-  "
-{
-  i386_compare_gen = gen_cmpdf_cc;
-  i386_compare_gen_eq = gen_cmpdf_ccfpeq;
-  i386_compare_op0 = operands[0];
-  i386_compare_op1 = (immediate_operand (operands[1], DFmode))
-			? copy_to_mode_reg (DFmode, operands[1]) : operands[1];
-  DONE;
-}")
-
-(define_expand "cmpsf"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "register_operand" "")
-		 (match_operand:SF 1 "general_operand" "")))]
-  "TARGET_80387"
-  "
-{
-  i386_compare_gen = gen_cmpsf_cc;
-  i386_compare_gen_eq = gen_cmpsf_ccfpeq;
-  i386_compare_op0 = operands[0];
-  i386_compare_op1 = (immediate_operand (operands[1], SFmode))
-			? copy_to_mode_reg (SFmode, operands[1]) : operands[1];
-  DONE;
-}")
-
-(define_expand "cmpxf_cc"
-  [(parallel [(set (cc0)
-		   (compare (match_operand:XF 0 "register_operand" "")
-			    (match_operand:XF 1 "register_operand" "")))
-	      (clobber (match_scratch:HI 2 ""))])]
-  "TARGET_80387"
-  "")
-
-(define_expand "cmpxf_ccfpeq"
-  [(parallel [(set (cc0)
-		   (compare:CCFPEQ (match_operand:XF 0 "register_operand" "")
-				   (match_operand:XF 1 "register_operand" "")))
-	      (clobber (match_scratch:HI 2 ""))])]
-  "TARGET_80387"
-  "")
-
-(define_expand "cmpdf_cc"
-  [(parallel [(set (cc0)
-		   (compare (match_operand:DF 0 "register_operand" "")
-			    (match_operand:DF 1 "register_operand" "")))
-	      (clobber (match_scratch:HI 2 ""))])]
-  "TARGET_80387"
-  "")
-
-(define_expand "cmpdf_ccfpeq"
-  [(parallel [(set (cc0)
-		   (compare:CCFPEQ (match_operand:DF 0 "register_operand" "")
-				   (match_operand:DF 1 "register_operand" "")))
-	      (clobber (match_scratch:HI 2 ""))])]
-  "TARGET_80387"
-  "
-{
-  if (! register_operand (operands[1], DFmode))
-    operands[1] = copy_to_mode_reg (DFmode, operands[1]);
-}")
-
-(define_expand "cmpsf_cc"
-  [(parallel [(set (cc0)
-		   (compare (match_operand:SF 0 "register_operand" "")
-			    (match_operand:SF 1 "register_operand" "")))
-	      (clobber (match_scratch:HI 2 ""))])]
-  "TARGET_80387"
-  "")
-
-(define_expand "cmpsf_ccfpeq"
-  [(parallel [(set (cc0)
-		   (compare:CCFPEQ (match_operand:SF 0 "register_operand" "")
-				   (match_operand:SF 1 "register_operand" "")))
-	      (clobber (match_scratch:HI 2 ""))])]
-  "TARGET_80387"
-  "
-{
-  if (! register_operand (operands[1], SFmode))
-    operands[1] = copy_to_mode_reg (SFmode, operands[1]);
-}")
-
-;; logical compare
-
-(define_insn ""
-  [(set (cc0)
-	(and:SI (match_operand:SI 0 "general_operand" "%ro")
-		(match_operand:SI 1 "nonmemory_operand" "ri")))]
-  ""
-  "*
-{
-  /* For small integers, we may actually use testb. */
-  if (GET_CODE (operands[1]) == CONST_INT
-      && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
-      && (! REG_P (operands[0]) || QI_REG_P (operands[0])))
-    {
-      /* We may set the sign bit spuriously.  */
-
-      if ((INTVAL (operands[1]) & ~0xff) == 0)
-        {
-	  cc_status.flags |= CC_NOT_NEGATIVE;
-	  return AS2 (test%B0,%1,%b0);
-	}
-
-      if ((INTVAL (operands[1]) & ~0xff00) == 0)
-        {
-	  cc_status.flags |= CC_NOT_NEGATIVE;
-	  operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
-
-	  if (QI_REG_P (operands[0]))
-	    return AS2 (test%B0,%1,%h0);
-	  else
-	    {
-	      operands[0] = adj_offsettable_operand (operands[0], 1);
-	      return AS2 (test%B0,%1,%b0);
-	    }
-	}
-
-      if (GET_CODE (operands[0]) == MEM
-	  && (INTVAL (operands[1]) & ~0xff0000) == 0)
-        {
-	  cc_status.flags |= CC_NOT_NEGATIVE;
-	  operands[1] = GEN_INT (INTVAL (operands[1]) >> 16);
-	  operands[0] = adj_offsettable_operand (operands[0], 2);
-	  return AS2 (test%B0,%1,%b0);
-	}
-
-      if (GET_CODE (operands[0]) == MEM
-	  && (INTVAL (operands[1]) & ~0xff000000) == 0)
-        {
-	  operands[1] = GEN_INT ((INTVAL (operands[1]) >> 24) & 0xff);
-	  operands[0] = adj_offsettable_operand (operands[0], 3);
-	  return AS2 (test%B0,%1,%b0);
-	}
-    }
-
-  if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
-    return AS2 (test%L0,%1,%0);
-
-  return AS2 (test%L1,%0,%1);
-}"
-  [(set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (cc0)
-	(and:HI (match_operand:HI 0 "general_operand" "%ro")
-		(match_operand:HI 1 "nonmemory_operand" "ri")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT
-      && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
-      && (! REG_P (operands[0]) || QI_REG_P (operands[0])))
-    {
-      if ((INTVAL (operands[1]) & 0xff00) == 0)
-	{
-	  /* ??? This might not be necessary. */
-	  if (INTVAL (operands[1]) & 0xffff0000)
-	    operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
-
-	  /* We may set the sign bit spuriously.  */
-	  cc_status.flags |= CC_NOT_NEGATIVE;
-	  return AS2 (test%B0,%1,%b0);
-	}
-
-      if ((INTVAL (operands[1]) & 0xff) == 0)
-        {
-	  operands[1] = GEN_INT ((INTVAL (operands[1]) >> 8) & 0xff);
-
-	  if (QI_REG_P (operands[0]))
-	    return AS2 (test%B0,%1,%h0);
-	  else
-	    {
-	      operands[0] = adj_offsettable_operand (operands[0], 1);
-	      return AS2 (test%B0,%1,%b0);
-	    }
-	}
-    }
-
-  /* use 32-bit test instruction if there are no sign issues */
-  if (GET_CODE (operands[1]) == CONST_INT
-      && !(INTVAL (operands[1]) & ~0x7fff)
-      && i386_aligned_p (operands[0]))
-    return AS2 (test%L0,%1,%k0);
-
-  if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
-    return AS2 (test%W0,%1,%0);
-
-  return AS2 (test%W1,%0,%1);
-}"
-  [(set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (cc0)
-	(and:QI (match_operand:QI 0 "nonimmediate_operand" "%qm")
-		(match_operand:QI 1 "nonmemory_operand" "qi")))]
-  ""
-  "*
-{
-  if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
-    return AS2 (test%B0,%1,%0);
-
-  return AS2 (test%B1,%0,%1);
-}"
-  [(set_attr "type" "compare")])
-
-;; move instructions.
-;; There is one for each machine mode,
-;; and each is preceded by a corresponding push-insn pattern
-;; (since pushes are not general_operands on the 386).
-
-(define_insn ""
-  [(set (match_operand:SI 0 "push_operand" "=<")
-	(match_operand:SI 1 "nonmemory_operand" "rn"))]
-  "flag_pic"
-  "* return AS1 (push%L0,%1);"
-  [(set_attr "memory" "store")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "push_operand" "=<")
-	(match_operand:SI 1 "nonmemory_operand" "ri"))]
-  "!flag_pic"
-  "* return AS1 (push%L0,%1);"
-  [(set_attr "memory" "store")])
-
-;; On a 386, it is faster to push MEM directly.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "push_operand" "=<")
-	(match_operand:SI 1 "memory_operand" "m"))]
-  "TARGET_PUSH_MEMORY"
-  "* return AS1 (push%L0,%1);"
-  [(set_attr "type" "memory")
-   (set_attr "memory" "load")])
-
-;; General case of fullword move.
-
-;; If generating PIC code and operands[1] is a symbolic CONST, emit a
-;; move to get the address of the symbolic object from the GOT.
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  extern int flag_pic;
-
-  if (flag_pic && SYMBOLIC_CONST (operands[1]))
-    emit_pic_move (operands, SImode);
-
-  /* Don't generate memory->memory moves, go through a register */
-  else if (TARGET_MOVE
-	   && (reload_in_progress | reload_completed) == 0
-	   && GET_CODE (operands[0]) == MEM
-	   && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (SImode, operands[1]);
-    }
-}")
-
-;; On i486, incl reg is faster than movl $1,reg.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g,r,r")
-	(match_operand:SI 1 "general_operand" "rn,i,m"))]
-  "((!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
-    || (GET_CODE (operands[1]) != MEM))
-   && flag_pic"
-  "*
-{
-  rtx link;
-
-  /* K6: mov reg,0 is slightly faster than xor reg,reg but is 3 bytes
-     longer.  */
-  if ((ix86_cpu != PROCESSOR_K6 || optimize_size)
-      && operands[1] == const0_rtx && REG_P (operands[0]))
-    return AS2 (xor%L0,%0,%0);
-
-  if (operands[1] == const1_rtx
-      /* PPRO and K6 prefer mov to inc to reduce dependencies.  */
-      && (optimize_size || (int)ix86_cpu < (int)PROCESSOR_PENTIUMPRO)
-      && (link = find_reg_note (insn, REG_WAS_0, 0))
-      /* Make sure the insn that stored the 0 is still present.  */
-      && ! INSN_DELETED_P (XEXP (link, 0))
-      && GET_CODE (XEXP (link, 0)) != NOTE
-      /* Make sure cross jumping didn't happen here.  */
-      && no_labels_between_p (XEXP (link, 0), insn)
-      /* Make sure the reg hasn't been clobbered.  */
-      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
-    /* Fastest way to change a 0 to a 1.  */
-    return AS1 (inc%L0,%0);
-
-  if (SYMBOLIC_CONST (operands[1]))
-    return AS2 (lea%L0,%a1,%0);
-
-  return AS2 (mov%L0,%1,%0);
-}"
-  [(set_attr "type" "integer,integer,memory")
-   (set_attr "memory" "*,*,load")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g,r")
-	(match_operand:SI 1 "general_operand" "ri,m"))]
-  "((!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
-    || (GET_CODE (operands[1]) != MEM))
-   && !flag_pic"
-  "*
-{
-  rtx link;
-  if ((ix86_cpu != PROCESSOR_K6 || optimize_size)
-      && operands[1] == const0_rtx && REG_P (operands[0]))
-    return AS2 (xor%L0,%0,%0);
-
-  if (operands[1] == const1_rtx
-      /* PPRO and K6 prefer mov to inc to reduce dependencies.  */
-      && (optimize_size || (int)ix86_cpu < (int)PROCESSOR_PENTIUMPRO)
-      && (link = find_reg_note (insn, REG_WAS_0, 0))
-      /* Make sure the insn that stored the 0 is still present.  */
-      && ! INSN_DELETED_P (XEXP (link, 0))
-      && GET_CODE (XEXP (link, 0)) != NOTE
-      /* Make sure cross jumping didn't happen here.  */
-      && no_labels_between_p (XEXP (link, 0), insn)
-      /* Make sure the reg hasn't been clobbered.  */
-      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
-    /* Fastest way to change a 0 to a 1.  */
-    return AS1 (inc%L0,%0);
-
-  return AS2 (mov%L0,%1,%0);
-}"
-  [(set_attr "type" "integer,memory")
-   (set_attr "memory" "*,load")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "push_operand" "=<")
-	(match_operand:HI 1 "nonmemory_operand" "ri"))]
-  ""
-  "* return AS1 (push%W0,%1);"
-  [(set_attr "type" "memory")
-   (set_attr "memory" "store")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "push_operand" "=<")
-	(match_operand:HI 1 "memory_operand" "m"))]
-  "TARGET_PUSH_MEMORY"
-  "* return AS1 (push%W0,%1);"
-  [(set_attr "type" "memory")
-   (set_attr "memory" "load")])
-
-;; On i486, an incl and movl are both faster than incw and movw.
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (HImode, operands[1]);
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g,r")
-	(match_operand:HI 1 "general_operand" "ri,m"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
-  "*
-{
-  rtx link;
-  if (REG_P (operands[0]) && operands[1] == const0_rtx)
-    return AS2 (xor%L0,%k0,%k0);
-
-  if (REG_P (operands[0]) && operands[1] == const1_rtx 
-      /* PPRO and K6 prefer mov to inc to reduce dependencies.  */
-      && (optimize_size || (int)ix86_cpu < (int)PROCESSOR_PENTIUMPRO)
-      && (link = find_reg_note (insn, REG_WAS_0, 0))
-      /* Make sure the insn that stored the 0 is still present.  */
-      && ! INSN_DELETED_P (XEXP (link, 0))
-      && GET_CODE (XEXP (link, 0)) != NOTE
-      /* Make sure cross jumping didn't happen here.  */
-      && no_labels_between_p (XEXP (link, 0), insn)
-      /* Make sure the reg hasn't been clobbered.  */
-      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
-    /* Fastest way to change a 0 to a 1.  */
-    return AS1 (inc%L0,%k0);
-
-  if (REG_P (operands[0]))
-    {
-      if (i386_aligned_p (operands[1]))
-	{
-	  operands[1] = i386_sext16_if_const (operands[1]);
-	  return AS2 (mov%L0,%k1,%k0);
-	}
-      if (! TARGET_ZERO_EXTEND_WITH_AND)
-	{
-	  /* movzwl is faster than movw on the Pentium Pro,
-	   * although not as fast as an aligned movl. */
-#ifdef INTEL_SYNTAX
-	  return AS2 (movzx,%1,%k0);
-#else
-	  return AS2 (movz%W0%L0,%1,%k0);
-#endif
-	}
-    }
-
-  return AS2 (mov%W0,%1,%0);
-}"
-  [(set_attr "type" "integer,memory")
-   (set_attr "memory" "*,load")])
-
-(define_expand "movstricthi"
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (HImode, operands[1]);
-    }
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+g,r"))
-	(match_operand:HI 1 "general_operand" "ri,m"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
-  "*
-{
-  rtx link;
-  if ((ix86_cpu != PROCESSOR_K6 || optimize_size)
-      && operands[1] == const0_rtx && REG_P (operands[0]))
-    return AS2 (xor%W0,%0,%0);
-
-  if (operands[1] == const1_rtx
-      /* PPRO and K6 prefer mov to inc to reduce dependencies.  */
-      && (optimize_size || (int)ix86_cpu < (int)PROCESSOR_PENTIUMPRO)
-      && (link = find_reg_note (insn, REG_WAS_0, 0))
-      /* Make sure the insn that stored the 0 is still present.  */
-      && ! INSN_DELETED_P (XEXP (link, 0))
-      && GET_CODE (XEXP (link, 0)) != NOTE
-      /* Make sure cross jumping didn't happen here.  */
-      && no_labels_between_p (XEXP (link, 0), insn)
-      /* Make sure the reg hasn't been clobbered.  */
-      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
-    /* Fastest way to change a 0 to a 1.  */
-    return AS1 (inc%W0,%0);
-
-  return AS2 (mov%W0,%1,%0);
-}"
-  [(set_attr "type" "integer,memory")])
-
-;; emit_push_insn when it calls move_by_pieces
-;; requires an insn to "push a byte".
-;; But actually we use pushw, which has the effect of rounding
-;; the amount pushed up to a halfword.
-(define_insn ""
-  [(set (match_operand:QI 0 "push_operand" "=<")
-	(match_operand:QI 1 "const_int_operand" "n"))]
-  ""
-  "* return AS1(push%W0,%1);")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "push_operand" "=<")
-	(match_operand:QI 1 "register_operand" "q"))]
-  ""
-  "*
-{
-  operands[1] = gen_rtx_REG (HImode, REGNO (operands[1]));
-  return AS1 (push%W0,%1);
-}")
-
-;; On i486, incb reg is faster than movb $1,reg.
-
-;; ??? Do a recognizer for zero_extract that looks just like this, but reads
-;; or writes %ah, %bh, %ch, %dh.
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (QImode, operands[1]);
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=q,*r,qm")
-	(match_operand:QI 1 "general_operand" "*g,*rn,qn"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
-  "*
-{
-  rtx link;
-
-  /* movb $0,reg8 is 2 bytes, the same as xorl reg8,reg8.
-     It is at least as fast as xor on any processor except a Pentium. */
-
-  if (operands[1] == const1_rtx
-      && TARGET_PENTIUM
-      && (link = find_reg_note (insn, REG_WAS_0, 0))
-      /* Make sure the insn that stored the 0 is still present.  */
-      && ! INSN_DELETED_P (XEXP (link, 0))
-      && GET_CODE (XEXP (link, 0)) != NOTE
-      /* Make sure cross jumping didn't happen here.  */
-      && no_labels_between_p (XEXP (link, 0), insn)
-      /* Make sure the reg hasn't been clobbered.  */
-      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
-    {
-      /* Fastest way to change a 0 to a 1.
-	 If inc%B0 isn't allowed, use inc%L0.  */
-      if (NON_QI_REG_P (operands[0]))
-	return AS1 (inc%L0,%k0);
-      else
-	return AS1 (inc%B0,%0);
-    }
-
-  /* If mov%B0 isn't allowed for one of these regs, use mov%L0.  */
-  if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1]))
-    return (AS2 (mov%L0,%k1,%k0));
-
-  return (AS2 (mov%B0,%1,%0));
-}")
-
-;; If it becomes necessary to support movstrictqi into %esi or %edi,
-;; use the insn sequence:
-;;
-;;	shrdl $8,srcreg,dstreg
-;;	rorl $24,dstreg
-;;
-;; If operands[1] is a constant, then an andl/orl sequence would be
-;; faster.
-
-(define_expand "movstrictqi"
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (QImode, operands[1]);
-    }
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
-	(match_operand:QI 1 "general_operand" "*qn,m"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
-  "*
-{
-  rtx link;
-
-  /* movb $0,reg8 is 2 bytes, the same as xorl reg8,reg8.  */
-
-  if (operands[1] == const1_rtx
-      && TARGET_PENTIUM
-      && ! NON_QI_REG_P (operands[0])
-      && (link = find_reg_note (insn, REG_WAS_0, 0))
-      /* Make sure the insn that stored the 0 is still present.  */
-      && ! INSN_DELETED_P (XEXP (link, 0))
-      && GET_CODE (XEXP (link, 0)) != NOTE
-      /* Make sure cross jumping didn't happen here.  */
-      && no_labels_between_p (XEXP (link, 0), insn)
-      /* Make sure the reg hasn't been clobbered.  */
-      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
-    /* Fastest way to change a 0 to a 1.  */
-    return AS1 (inc%B0,%0);
-
-  /* If mov%B0 isn't allowed for one of these regs, use mov%L0.  */
-  if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1]))
-    {
-      abort ();
-      return (AS2 (mov%L0,%k1,%k0));
-    }
-
-  return AS2 (mov%B0,%1,%0);
-}")
-
-(define_insn "movsf_push"
-  [(set (match_operand:SF 0 "push_operand" "=<,<")
-	(match_operand:SF 1 "general_operand" "*rfF,m"))]
-  "GET_CODE (operands[1]) != MEM || reload_in_progress || reload_completed"
-  "*
-{
-  if (STACK_REG_P (operands[1]))
-    {
-      rtx xops[3];
-
-      if (! STACK_TOP_P (operands[1]))
-        abort ();
-
-      xops[0] = AT_SP (SFmode);
-      xops[1] = GEN_INT (4);
-      xops[2] = stack_pointer_rtx;
-
-      output_asm_insn (AS2 (sub%L2,%1,%2), xops);
-
-      if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
-        output_asm_insn (AS1 (fstp%S0,%0), xops);
-      else
-        output_asm_insn (AS1 (fst%S0,%0), xops);
-
-      RET;
-    }
-
-  return AS1 (push%L0,%1);
-}")
-
-(define_insn "movsf_push_memory"
-  [(set (match_operand:SF 0 "push_operand" "=<")
-	(match_operand:SF 1 "memory_operand" "m"))]
-  "TARGET_PUSH_MEMORY"
-  "* return AS1 (push%L0,%1);")
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (SFmode, operands[1]);
-    }
-
-  /* If we are loading a floating point constant that isn't 0 or 1
-     into a register, force the value to memory now, since we'll 
-     get better code out the back end.  */
-  else if ((reload_in_progress | reload_completed) == 0
-	   && GET_CODE (operands[0]) != MEM
-	   && GET_CODE (operands[1]) == CONST_DOUBLE
-	   && !standard_80387_constant_p (operands[1]))
-    {
-      operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
-    }
-}")
-
-;; For the purposes of regclass, prefer FLOAT_REGS.
-(define_insn ""
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=*rfm,*rf,f,!*rm")
-	(match_operand:SF 1 "general_operand" "*rf,*rfm,fG,fF"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
-  "*
-{
-  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-
-  /* First handle a `pop' insn or a `fld %st(0)' */
-
-  if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]))
-    {
-      if (stack_top_dies)
-	return AS1 (fstp,%y0);
-      else
-        return AS1 (fld,%y0);
-    }
-
-  /* Handle a transfer between the 387 and a 386 register */
-
-  if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1]))
-    {
-      output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
-      RET;
-    }
-
-  if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0]))
-    {
-      output_to_reg (operands[0], stack_top_dies, 0);
-      RET;
-    }
-
-  /* Handle other kinds of writes from the 387 */
-
-  if (STACK_TOP_P (operands[1]))
-    {
-      if (stack_top_dies)
-	return AS1 (fstp%z0,%y0);
-      else
-        return AS1 (fst%z0,%y0);
-    }
-
-  /* Handle other kinds of reads to the 387 */
-
-  if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE)
-    return output_move_const_single (operands);
-
-  if (STACK_TOP_P (operands[0]))
-    return AS1 (fld%z1,%y1);
-
-  /* Handle all SFmode moves not involving the 387 */
-
-  return singlemove_string (operands);
-}"
-  [(set_attr "type" "fld")])
-
-
-(define_insn "swapsf"
-  [(set (match_operand:SF 0 "register_operand" "f")
-	(match_operand:SF 1 "register_operand" "f"))
-   (set (match_dup 1)
-	(match_dup 0))]
-  ""
-  "*
-{
-  if (STACK_TOP_P (operands[0]))
-    return AS1 (fxch,%1);
-  else
-    return AS1 (fxch,%0);
-}")
-
-
-(define_insn "movdf_push"
-  [(set (match_operand:DF 0 "push_operand" "=<,<")
-	(match_operand:DF 1 "general_operand" "*rfF,o"))]
-  "GET_CODE (operands[1]) != MEM || reload_in_progress || reload_completed"
-  "*
-{
-  if (STACK_REG_P (operands[1]))
-    {
-      rtx xops[3];
-
-      xops[0] = AT_SP (DFmode);
-      xops[1] = GEN_INT (8);
-      xops[2] = stack_pointer_rtx;
-
-      output_asm_insn (AS2 (sub%L2,%1,%2), xops);
-
-      if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
-        output_asm_insn (AS1 (fstp%Q0,%0), xops);
-      else
-        output_asm_insn (AS1 (fst%Q0,%0), xops);
-
-      RET;
-    }
-
-  if (which_alternative == 1)
-    return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode), 0, 0);
-
-  return output_move_double (operands);
-}")
-
-(define_insn "movdf_push_memory"
-  [(set (match_operand:DF 0 "push_operand" "=<")
-	(match_operand:DF 1 "memory_operand" "o"))]
-  "TARGET_PUSH_MEMORY"
-  "* return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode),0,0);")
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (DFmode, operands[1]);
-    }
-
-  /* If we are loading a floating point constant that isn't 0 or 1 into a
-     register, indicate we need the pic register loaded.  This could be
-     optimized into stores of constants if the target eventually moves to
-     memory, but better safe than sorry.  */
-  else if ((reload_in_progress | reload_completed) == 0
-	   && GET_CODE (operands[0]) != MEM
-	   && GET_CODE (operands[1]) == CONST_DOUBLE
-	   && !standard_80387_constant_p (operands[1]))
-    {
-      operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
-    }
-}")
-
-;; For the purposes of regclass, prefer FLOAT_REGS.
-(define_insn ""
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,fm,!*rf,!*rm")
-	(match_operand:DF 1 "general_operand" "fmG,f,*rfm,*rfF"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
-   || (GET_CODE (operands[1]) != MEM)"
-  "*
-{
-  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-
-  /* First handle a `pop' insn or a `fld %st(0)' */
-
-  if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]))
-    {
-      if (stack_top_dies)
-	return AS1 (fstp,%y0);
-      else
-        return AS1 (fld,%y0);
-    }
-
-  /* Handle a transfer between the 387 and a 386 register */
-
-  if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1]))
-    {
-      output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
-      RET;
-    }
-
-  if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0]))
-    {
-      output_to_reg (operands[0], stack_top_dies, 0);
-      RET;
-    }
-
-  /* Handle other kinds of writes from the 387 */
-
-  if (STACK_TOP_P (operands[1]))
-    {
-      if (stack_top_dies)
-	return AS1 (fstp%z0,%y0);
-      else
-        return AS1 (fst%z0,%y0);
-    }
-
-  /* Handle other kinds of reads to the 387 */
-
-  if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE)
-    return output_move_const_single (operands);
-
-  if (STACK_TOP_P (operands[0]))
-    return AS1 (fld%z1,%y1);
-
-  /* Handle all DFmode moves not involving the 387 */
-
-  return output_move_double (operands);
-}"
-  [(set_attr "type" "fld")])
-
-
-
-(define_insn "swapdf"
-  [(set (match_operand:DF 0 "register_operand" "f")
-	(match_operand:DF 1 "register_operand" "f"))
-   (set (match_dup 1)
-	(match_dup 0))]
-  ""
-  "*
-{
-  if (STACK_TOP_P (operands[0]))
-    return AS1 (fxch,%1);
-  else
-    return AS1 (fxch,%0);
-}")
-
-(define_insn "movxf_push"
-  [(set (match_operand:XF 0 "push_operand" "=<,<")
- 	(match_operand:XF 1 "general_operand" "*rfF,o"))]
-  "GET_CODE (operands[1]) != MEM || reload_in_progress || reload_completed"
-  "*
-{
-  if (STACK_REG_P (operands[1]))
-    {
-      rtx xops[3];
-
-      xops[0] = AT_SP (XFmode);
-      xops[1] = GEN_INT (12);
-      xops[2] = stack_pointer_rtx;
-
-      output_asm_insn (AS2 (sub%L2,%1,%2), xops);
-
-      output_asm_insn (AS1 (fstp%T0,%0), xops);
-      if (! find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
-	output_asm_insn (AS1 (fld%T0,%0), xops);
-
-      RET;
-    }
-
-  if (which_alternative == 1)
-    return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode), 0, 0);
-
-  return output_move_double (operands);
- }")
-
-(define_insn "movxf_push_memory"
-  [(set (match_operand:XF 0 "push_operand" "=<")
- 	(match_operand:XF 1 "memory_operand" "o"))]
-  "TARGET_PUSH_MEMORY"
-  "* return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode),0,0);")
-
-(define_expand "movxf"
-  [(set (match_operand:XF 0 "general_operand" "")
-	(match_operand:XF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (XFmode, operands[1]);
-    }
-
-  /* If we are loading a floating point constant that isn't 0 or 1
-     into a register, indicate we need the pic register loaded.  This could
-     be optimized into stores of constants if the target eventually moves
-     to memory, but better safe than sorry.  */
-  else if ((reload_in_progress | reload_completed) == 0
-	   && GET_CODE (operands[0]) != MEM
-	   && GET_CODE (operands[1]) == CONST_DOUBLE
-	   && !standard_80387_constant_p (operands[1]))
-    {
-      operands[1] = validize_mem (force_const_mem (XFmode, operands[1]));
-    }
-}")
-
-
-(define_insn ""
-  [(set (match_operand:XF 0 "nonimmediate_operand" "=f,fm,!*rf,!*rm")
-	(match_operand:XF 1 "general_operand" "fmG,f,*rfm,*rfF"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
-   || (GET_CODE (operands[1]) != MEM)"
-  "*
-{
-  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-
-  /* First handle a `pop' insn or a `fld %st(0)' */
-
-  if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]))
-    {
-      if (stack_top_dies)
-	return AS1 (fstp,%y0);
-      else
-        return AS1 (fld,%y0);
-    }
-
-  /* Handle a transfer between the 387 and a 386 register */
-
-  if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1]))
-    {
-      output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
-      RET;
-    }
-
-  if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0]))
-    {
-      output_to_reg (operands[0], stack_top_dies, 0);
-      RET;
-    }
-
-  /* Handle other kinds of writes from the 387 */
-
-  if (STACK_TOP_P (operands[1]))
-    {
-      output_asm_insn (AS1 (fstp%z0,%y0), operands);
-      if (! stack_top_dies)
-	return AS1 (fld%z0,%y0);
-
-      RET;
-    }
-
-  /* Handle other kinds of reads to the 387 */
-
-  if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE)
-    return output_move_const_single (operands);
-
-  if (STACK_TOP_P (operands[0]))
-       return AS1 (fld%z1,%y1);
-
-  /* Handle all XFmode moves not involving the 387 */
-
-  return output_move_double (operands);
-}")
-
-(define_insn "swapxf" 
-  [(set (match_operand:XF 0 "register_operand" "f")
-	(match_operand:XF 1 "register_operand" "f"))
-   (set (match_dup 1)
-	(match_dup 0))]
-  ""
-  "*
-{
-  if (STACK_TOP_P (operands[0]))
-    return AS1 (fxch,%1);
-  else
-    return AS1 (fxch,%0);
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "push_operand" "=<")
-	(match_operand:DI 1 "general_operand" "riF"))]
-  ""
-  "* return output_move_double (operands);")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "push_operand" "=<")
-	(match_operand:DI 1 "memory_operand" "o"))]
-  "TARGET_PUSH_MEMORY"
-  "* return output_move_pushmem (operands, insn, GET_MODE_SIZE (DImode),0,0);")
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      operands[1] = force_reg (DImode, operands[1]);
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=g,r")
-	(match_operand:DI 1 "general_operand" "riF,m"))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
-   || (GET_CODE (operands[1]) != MEM)"
-  "* return output_move_double (operands);"
-  [(set_attr "type" "integer,memory")
-   (set_attr "memory" "*,load")])
-
-
-;;- conversion instructions
-;;- NONE
-
-;;- zero extension instructions
-;; See comments by `andsi' for when andl is faster than movzx.
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,&r,?r")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,rm,rm")))]
-  ""
-  "*
-  {
-  rtx xops[2];
-
-  if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0) 
-      && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]))
-    {
-      xops[0] = operands[0];
-      xops[1] = GEN_INT (0xffff);
-      output_asm_insn (AS2 (and%L0,%1,%k0), xops);
-      RET;
-    }
-  if (TARGET_ZERO_EXTEND_WITH_AND && !reg_overlap_mentioned_p (operands[0], operands[1]))
-    {
-      output_asm_insn (AS2 (xor%L0,%0,%0),operands);
-      output_asm_insn (AS2 (mov%W0,%1,%w0),operands);
-      RET;
-    }
-
-  if (TARGET_ZERO_EXTEND_WITH_AND)
-    {
-      xops[0] = operands[0];
-      xops[1] = GEN_INT (0xffff);
-      if (i386_aligned_p (operands[1]))
-	output_asm_insn (AS2 (mov%L0,%k1,%k0),operands);
-      else
-	output_asm_insn (AS2 (mov%W0,%1,%w0),operands);
-      output_asm_insn (AS2 (and%L0,%1,%k0), xops);
-      RET;
-    }
-
-#ifdef INTEL_SYNTAX
-  return AS2 (movzx,%1,%0);
-#else
-  return AS2 (movz%W0%L0,%1,%0);
-#endif
-}")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
- "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !reg_overlap_mentioned_p (operands[0], operands[1])"
- [(set (match_dup 0)
-       (const_int 0))
-  (set (strict_low_part (match_dup 2))
-       (match_dup 1))]
- "operands[2] = gen_rtx_REG (HImode, true_regnum (operands[0]));")
-
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:HI 1 "memory_operand" "")))]
- "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && reg_overlap_mentioned_p (operands[0], operands[1])"
- [(set (strict_low_part (match_dup 2))
-       (match_dup 1))
-  (set (match_dup 0)
-       (and:SI (match_dup 0)
-	       (const_int 65535)))]
-  "operands[2] = gen_rtx_REG (HImode, true_regnum (operands[0]));")
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=q,&q,?r")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm,qm")))]
-  ""
-  "*
-  {
-  rtx xops[2];
-
-  if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0)
-      && REG_P (operands[1]) 
-      && REGNO (operands[0]) == REGNO (operands[1]))
-    {
-      xops[0] = operands[0];
-      xops[1] = GEN_INT (0xff);
-      output_asm_insn (AS2 (and%L0,%1,%k0), xops);
-      RET;
-    }
-  if (TARGET_ZERO_EXTEND_WITH_AND && QI_REG_P (operands[0]))
-    {
-      if(!reg_overlap_mentioned_p(operands[0],operands[1]))
-	{
-	  output_asm_insn (AS2 (xor%L0,%k0,%k0), operands);
-	  output_asm_insn (AS2 (mov%B0,%1,%b0), operands);
-	}
-      else
-	{
-	  xops[0] = operands[0];
-	  xops[1] = GEN_INT (0xff);
-	  output_asm_insn (AS2 (mov%B0,%1,%b0),operands);
-	  output_asm_insn (AS2 (and%L0,%1,%k0), xops);
-	}
-      RET;
-    }
-  
-#ifdef INTEL_SYNTAX
-  return AS2 (movzx,%1,%0);
-#else
-  return AS2 (movz%B0%W0,%1,%0);
-#endif
-}")
-
-(define_split
-  [(set (match_operand:HI 0 "register_operand" "")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
- "reload_completed && QI_REG_P (operands[0]) && TARGET_ZERO_EXTEND_WITH_AND
-  && !reg_overlap_mentioned_p (operands[0], operands[1])"
- [(set (match_dup 0)
-       (const_int 0))
-  (set (strict_low_part (match_dup 2))
-       (match_dup 1))]
- "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
-
-
-(define_split
-  [(set (match_operand:HI 0 "register_operand" "")
-	(zero_extend:HI (match_operand:QI 1 "memory_operand" "")))]
- "reload_completed && QI_REG_P (operands[0]) && TARGET_ZERO_EXTEND_WITH_AND
-  && reg_overlap_mentioned_p (operands[0], operands[1])"
- [(set (strict_low_part (match_dup 2))
-       (match_dup 1))
-  (set (match_dup 0)
-       (and:HI (match_dup 0)
-	       (const_int 255)))]
- "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
-
-(define_split
-  [(set (match_operand:HI 0 "register_operand" "")
-	(zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
- "reload_completed && TARGET_ZERO_EXTEND_WITH_AND"
- [(set (match_dup 0)
-       (match_dup 2))
-  (set (match_dup 0)
-       (and:HI (match_dup 0)
-	       (const_int 255)))]
- "if (GET_CODE (operands[1]) == SUBREG && SUBREG_WORD (operands[1]) == 0)
-    operands[1] = SUBREG_REG (operands[1]);
-  if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG
-      || REGNO (operands[0]) == REGNO (operands[1]))
-    FAIL;
-  operands[2] = gen_rtx_REG (HImode, REGNO (operands[1]));")
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=q,&q,?r")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm,qm")))]
-  ""
-  "*
-  {
-  rtx xops[2];
-
-  if ((TARGET_ZERO_EXTEND_WITH_AND || REGNO (operands[0]) == 0)
-      && REG_P (operands[1]) 
-      && REGNO (operands[0]) == REGNO (operands[1]))
-    {
-      xops[0] = operands[0];
-      xops[1] = GEN_INT (0xff);
-      output_asm_insn (AS2 (and%L0,%1,%k0), xops);
-      RET;
-    }
-  if (TARGET_ZERO_EXTEND_WITH_AND && QI_REG_P (operands[0]))
-    {
-      if(!reg_overlap_mentioned_p (operands[0], operands[1]))
-	{
-	  output_asm_insn (AS2 (xor%L0,%0,%0),operands);
-	  output_asm_insn (AS2 (mov%B0,%1,%b0),operands);
-	}
-      else
-	{
-	  xops[0] = operands[0];
-	  xops[1] = GEN_INT (0xff);
-	  output_asm_insn (AS2 (mov%B0,%1,%b0), operands);
-	  output_asm_insn (AS2 (and%L0,%1,%k0), xops);
-	}
-      RET;
-    }
-
-  if (TARGET_ZERO_EXTEND_WITH_AND && GET_CODE (operands[1]) == REG)
-    {
-      xops[0] = operands[0];
-      xops[1] = GEN_INT (0xff);
-      operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]));
-      output_asm_insn (AS2 (mov%L0,%1,%0), operands);
-      output_asm_insn (AS2 (and%L0,%1,%k0), xops);
-      RET;
-    }
-
-#ifdef INTEL_SYNTAX
-  return AS2 (movzx,%1,%0);
-#else
-  return AS2 (movz%B0%L0,%1,%0);
-#endif
-}")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
- "reload_completed && QI_REG_P (operands[0]) && TARGET_ZERO_EXTEND_WITH_AND
-  && !reg_overlap_mentioned_p (operands[0], operands[1])"
- [(set (match_dup 0)
-       (const_int 0))
-  (set (strict_low_part (match_dup 2))
-       (match_dup 1))]
- "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
-
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:QI 1 "memory_operand" "")))]
- "reload_completed && QI_REG_P (operands[0]) && TARGET_ZERO_EXTEND_WITH_AND
-  && reg_overlap_mentioned_p (operands[0], operands[1])"
- [(set (strict_low_part (match_dup 2))
-       (match_dup 1))
-  (set (match_dup 0)
-       (and:SI (match_dup 0)
-	       (const_int 255)))]
- "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
- "reload_completed && TARGET_ZERO_EXTEND_WITH_AND
-  && ! reg_overlap_mentioned_p (operands[0], operands[1])"
- [(set (match_dup 0)
-       (match_dup 2))
-  (set (match_dup 0)
-       (and:SI (match_dup 0)
-	       (const_int 255)))]
- "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
-
-(define_insn "zero_extendsidi2"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
-	(zero_extend:DI (match_operand:SI 1 "general_operand" "0,rm,r")))]
-  ""
-  "#")
-
-(define_split 
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
-  "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])"
-  [(set (match_dup 4) (const_int 0))]
-  "split_di (&operands[0], 1, &operands[3], &operands[4]);")
-
-(define_split 
-  [(set (match_operand:DI 0 "nonimmediate_operand" "")
-	(zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 3) (match_dup 1))
-   (set (match_dup 4) (const_int 0))]
-  "split_di (&operands[0], 1, &operands[3], &operands[4]);")
-
-;;- sign extension instructions
-
-(define_insn "extendsidi2"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=A,?r,?Ar,*o")
-	(sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,*r")))
-   (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
-  ""
-  "#")
-
-;; Extend to memory case when source register does die.
-(define_split 
-  [(set (match_operand:DI 0 "memory_operand" "")
-	(sign_extend:DI (match_operand:SI 1 "register_operand" "")))
-   (clobber (match_operand:SI 2 "register_operand" ""))]
-  "(flow2_completed
-    && dead_or_set_p (insn, operands[1])
-    && !reg_mentioned_p (operands[1], operands[0]))"
-  [(set (match_dup 3) (match_dup 1))
-   (set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
-   (set (match_dup 4) (match_dup 1))]
-  "split_di (&operands[0], 1, &operands[3], &operands[4]);")
-
-;; Extend to memory case when source register does not die.
-(define_split 
-  [(set (match_operand:DI 0 "memory_operand" "")
-	(sign_extend:DI (match_operand:SI 1 "register_operand" "")))
-   (clobber (match_operand:SI 2 "register_operand" ""))]
-  "flow2_completed"
-  [(const_int 0)]
-  "
-{
-  split_di (&operands[0], 1, &operands[3], &operands[4]);
-
-  emit_move_insn (operands[3], operands[1]);
-
-  /* Generate a cltd if possible and doing so it profitable.  */
-  if (true_regnum (operands[1]) == 0
-      && true_regnum (operands[2]) == 1
-      && (optimize_size || !TARGET_PENTIUM))
-    {
-      emit_insn (gen_ashrsi3_31 (operands[2], operands[1]));
-    }
-  else
-    {
-      emit_move_insn (operands[2], operands[1]);
-      emit_insn (gen_ashrsi3_31 (operands[2], operands[2]));
-    }
-  emit_move_insn (operands[4], operands[2]);
-  DONE;
-}")
-
-;; Extend to register case.  Optimize case where source and destination
-;; registers match and cases where we can use cltd.
-(define_split 
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI (match_operand:SI 1 "register_operand" "")))
-   (clobber (match_scratch:SI 2 ""))]
-  "reload_completed"
-  [(const_int 0)]
-  "
-{
-  split_di (&operands[0], 1, &operands[3], &operands[4]);
-
-  if (true_regnum (operands[3]) != true_regnum (operands[1]))
-    emit_move_insn (operands[3], operands[1]);
-
-  /* Generate a cltd if possible and doing so it profitable.  */
-  if (true_regnum (operands[3]) == 0
-      && (optimize_size || !TARGET_PENTIUM))
-    {
-      emit_insn (gen_ashrsi3_31 (operands[4], operands[3]));
-      DONE;
-    }
-
-  if (true_regnum (operands[4]) != true_regnum (operands[1]))
-    emit_move_insn (operands[4], operands[1]);
-
-  emit_insn (gen_ashrsi3_31 (operands[4], operands[4]));
-  DONE;
-}")
-
-;; Note that the i386 programmers' manual says that the opcodes
-;; are named movsx..., but the assembler on Unix does not accept that.
-;; We use what the Unix assembler expects.
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "*
-{
-  if (REGNO (operands[0]) == 0
-      && REG_P (operands[1]) && REGNO (operands[1]) == 0)
-#ifdef INTEL_SYNTAX
-    return \"cwde\";
-#else
-    return \"cwtl\";
-#endif
-
-#ifdef INTEL_SYNTAX
-  return AS2 (movsx,%1,%0);
-#else
-  return AS2 (movs%W0%L0,%1,%0);
-#endif
-}")
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
-  ""
-  "*
-{
-  if (REGNO (operands[0]) == 0
-      && REG_P (operands[1]) && REGNO (operands[1]) == 0)
-    return \"cbtw\";
-
-#ifdef INTEL_SYNTAX
-  return AS2 (movsx,%1,%0);
-#else
-  return AS2 (movs%B0%W0,%1,%0);
-#endif
-}")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
-  ""
-  "*
-{
-#ifdef INTEL_SYNTAX
-  return AS2 (movsx,%1,%0);
-#else
-  return AS2 (movs%B0%L0,%1,%0);
-#endif
-}")
-
-
-;; Truncation of long long -> 32 bit
-
-(define_expand "truncdisi2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m")
-	(truncate:SI (match_operand:DI 1 "nonimmediate_operand" "ro,r")))]
-  ""
-  "
-{
-  /* Don't generate memory->memory moves, go through a register */
-  if (TARGET_MOVE
-      && (reload_in_progress | reload_completed) == 0
-      && GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
-    {
-      rtx target = gen_reg_rtx (SImode);
-      emit_insn (gen_truncdisi2 (target, operands[1]));
-      emit_move_insn (operands[0], target);
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m")
-	(truncate:SI (match_operand:DI 1 "nonimmediate_operand" "ro,r")))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
-  "*
-{
-  rtx low[2], high[2], xops[2];
-
-  split_di (&operands[1], 1, low, high);
-  xops[0] = operands[0];
-  xops[1] = low[0];
-  if (!rtx_equal_p (xops[0], xops[1]))
-    output_asm_insn (AS2 (mov%L0,%1,%0), xops);
-
-  RET;
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m")
-	(truncate:SI (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "ro,r")
-				  (const_int 32))))]
-  "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)"
-  "*
-{
-  rtx low[2], high[2], xops[2];
-
-  split_di (&operands[1], 1, low, high);
-  xops[0] = operands[0];
-  xops[1] = high[0];
-  if (!rtx_equal_p (xops[0], xops[1]))
-    output_asm_insn (AS2 (mov%L0,%1,%0), xops);
-
-  RET;
-}")
-
-
-
-;; Conversions between float and double.
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=fm,f")
-	(float_extend:DF
-	 (match_operand:SF 1 "nonimmediate_operand" "f,fm")))]
-  "TARGET_80387"
-  "*
-{
-  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-
-  if (NON_STACK_REG_P (operands[1]))
-    {
-      output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
-      RET;
-    }
-
-  if (NON_STACK_REG_P (operands[0]))
-    {
-      output_to_reg (operands[0], stack_top_dies, 0);
-      RET;
-    }
-
-  if (STACK_TOP_P (operands[0]))
-    return AS1 (fld%z1,%y1);
-
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (stack_top_dies)
-	return AS1 (fstp%z0,%y0);
-      else
-        return AS1 (fst%z0,%y0);
-    }
-
-  abort ();
-}")
-
-(define_insn "extenddfxf2"
-  [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f,f,!*r")
-	(float_extend:XF
-	 (match_operand:DF 1 "nonimmediate_operand" "f,fm,!*r,f")))]
-  "TARGET_80387"
-  "*
-{
-  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-
-  if (NON_STACK_REG_P (operands[1]))
-    {
-      output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
-      RET;
-    }
-
-  if (NON_STACK_REG_P (operands[0]))
-    {
-      output_to_reg (operands[0], stack_top_dies, 0);
-      RET;
-    }
-
-  if (STACK_TOP_P (operands[0]))
-    return AS1 (fld%z1,%y1);
-
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      output_asm_insn (AS1 (fstp%z0,%y0), operands);
-      if (! stack_top_dies)
-	return AS1 (fld%z0,%y0);
-      RET;
-    }
-
-  abort ();
-}")
-
-(define_insn "extendsfxf2"
-  [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f,f,!*r")
-	(float_extend:XF
-	 (match_operand:SF 1 "nonimmediate_operand" "f,fm,!*r,f")))]
-  "TARGET_80387"
-  "*
-{
-  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-
-  if (NON_STACK_REG_P (operands[1]))
-    {
-      output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
-      RET;
-    }
-
-  if (NON_STACK_REG_P (operands[0]))
-    {
-      output_to_reg (operands[0], stack_top_dies, 0);
-      RET;
-    }
-
-  if (STACK_TOP_P (operands[0]))
-    return AS1 (fld%z1,%y1);
-
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      output_asm_insn (AS1 (fstp%z0,%y0), operands);
-      if (! stack_top_dies)
-	return AS1 (fld%z0,%y0);
-      RET;
-    }
-
-  abort ();
-}")
-
-(define_expand "truncdfsf2"
-  [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
-		   (float_truncate:SF
-		    (match_operand:DF 1 "register_operand" "")))
-	      (clobber (match_dup 2))])]
-  "TARGET_80387"
-  "
-{
-  operands[2] = (rtx) assign_386_stack_local (SFmode, 0);
-}")
-
-;; This cannot output into an f-reg because there is no way to be sure
-;; of truncating in that case.  Otherwise this is just like a simple move
-;; insn.  So we pretend we can output to a reg in order to get better
-;; register preferencing, but we really use a stack slot.
-
-(define_insn ""
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,m")
-	(float_truncate:SF
-	 (match_operand:DF 1 "register_operand" "0,f")))
-   (clobber (match_operand:SF 2 "memory_operand" "m,m"))]
-  "TARGET_80387"
-  "*
-{
-  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (stack_top_dies)
-	return AS1 (fstp%z0,%0);
-      else
-        return AS1 (fst%z0,%0);
-    }
-  else if (STACK_TOP_P (operands[0]))
-    {
-      output_asm_insn (AS1 (fstp%z2,%y2), operands);
-      return AS1 (fld%z2,%y2);
-    }
-  else
-    abort ();
-}")
-
-(define_insn "truncxfsf2"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=m,!*r")
-	(float_truncate:SF
-	 (match_operand:XF 1 "register_operand" "f,f")))]
-  "TARGET_80387"
-  "*
-{
-  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-
-  if (NON_STACK_REG_P (operands[0]))
-    {
-      if (stack_top_dies == 0)
-	{
-	  output_asm_insn (AS1 (fld,%y1), operands);
-	  stack_top_dies = 1;
-	}
-      output_to_reg (operands[0], stack_top_dies, 0);
-      RET;
-    }
-  else if (GET_CODE (operands[0]) == MEM)
-    {
-      if (stack_top_dies)
-	return AS1 (fstp%z0,%0);
-      else
-	{
-	  output_asm_insn (AS1 (fld,%y1), operands);
-	  return AS1 (fstp%z0,%0);
-	}
-    }
-  else
-    abort ();
-}")
-
-(define_insn "truncxfdf2"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!*r")
-	(float_truncate:DF
-	 (match_operand:XF 1 "register_operand" "f,f")))]
-  "TARGET_80387"
-  "*
-{
-  int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
-
-  if (NON_STACK_REG_P (operands[0]))
-    {
-      if (stack_top_dies == 0)
-	{
-	  output_asm_insn (AS1 (fld,%y1), operands);
-	  stack_top_dies = 1;
-	}
-      output_to_reg (operands[0], stack_top_dies, 0);
-      RET;
-    }
-  else if (GET_CODE (operands[0]) == MEM)
-    {
-      if (stack_top_dies)
-	return AS1 (fstp%z0,%0);
-      else
-	{
-	  output_asm_insn (AS1 (fld,%y1), operands);
-	  return AS1 (fstp%z0,%0);
-	}
-    }
-  else
-    abort ();
-}")
-
-
-;; The 387 requires that the stack top dies after converting to DImode.
-
-;; Represent an unsigned conversion from SImode to MODE_FLOAT by first
-;; doing a signed conversion to DImode, and then taking just the low
-;; part.
-
-(define_expand "fixuns_truncxfsi2"
-  [(set (match_dup 4)
-	(match_operand:XF 1 "register_operand" ""))
-   (parallel [(set (match_dup 2)
-		   (fix:DI (fix:XF (match_dup 4))))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))
-	      (clobber (match_scratch:SI 7 ""))])
-   (set (match_operand:SI 0 "general_operand" "")
-	(match_dup 3))]
-  "TARGET_80387"
-  "
-{
-  operands[2] = gen_reg_rtx (DImode);
-  operands[3] = gen_lowpart (SImode, operands[2]);
-  operands[4] = gen_reg_rtx (XFmode);
-  operands[5] = (rtx) assign_386_stack_local (SImode, 0);
-  operands[6] = (rtx) assign_386_stack_local (DImode, 1);
-}")
-
-(define_expand "fixuns_truncdfsi2"
-  [(set (match_dup 4)
-	(match_operand:DF 1 "register_operand" ""))
-   (parallel [(set (match_dup 2)
-		   (fix:DI (fix:DF (match_dup 4))))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))
-	      (clobber (match_scratch:SI 7 ""))])
-   (set (match_operand:SI 0 "general_operand" "")
-	(match_dup 3))]
-  "TARGET_80387"
-  "
-{
-  operands[2] = gen_reg_rtx (DImode);
-  operands[3] = gen_lowpart (SImode, operands[2]);
-  operands[4] = gen_reg_rtx (DFmode);
-  operands[5] = (rtx) assign_386_stack_local (SImode, 0);
-  operands[6] = (rtx) assign_386_stack_local (DImode, 1);
-}")
-
-(define_expand "fixuns_truncsfsi2"
-  [(set (match_dup 4)
-	(match_operand:SF 1 "register_operand" ""))
-   (parallel [(set (match_dup 2)
-		   (fix:DI (fix:SF (match_dup 4))))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))
-	      (clobber (match_scratch:SI 7 ""))])
-   (set (match_operand:SI 0 "general_operand" "")
-	(match_dup 3))]
-  "TARGET_80387"
-  "
-{
-  operands[2] = gen_reg_rtx (DImode);
-  operands[3] = gen_lowpart (SImode, operands[2]);
-  operands[4] = gen_reg_rtx (SFmode);
-  operands[5] = (rtx) assign_386_stack_local (SImode, 0);
-  operands[6] = (rtx) assign_386_stack_local (DImode, 1);
-}")
-
-;; Signed conversion to DImode.
-
-(define_expand "fix_truncxfdi2"
-  [(set (match_dup 2)
-	(match_operand:XF 1 "register_operand" ""))
-   (parallel [(set (match_operand:DI 0 "general_operand" "")
-		   (fix:DI (fix:XF (match_dup 2))))
-	      (clobber (match_dup 2))
-	      (clobber (match_dup 3))
-	      (clobber (match_dup 4))
-	      (clobber (match_scratch:SI 5 ""))])]
-  "TARGET_80387"
-  "
-{
-  operands[1] = copy_to_mode_reg (XFmode, operands[1]);
-  operands[2] = gen_reg_rtx (XFmode);
-  operands[3] = (rtx) assign_386_stack_local (SImode, 0);
-  operands[4] = (rtx) assign_386_stack_local (DImode, 1);
-}")
-
-(define_expand "fix_truncdfdi2"
-  [(set (match_dup 2)
-	(match_operand:DF 1 "register_operand" ""))
-   (parallel [(set (match_operand:DI 0 "general_operand" "")
-		   (fix:DI (fix:DF (match_dup 2))))
-	      (clobber (match_dup 2))
-	      (clobber (match_dup 3))
-	      (clobber (match_dup 4))
-	      (clobber (match_scratch:SI 5 ""))])]
-  "TARGET_80387"
-  "
-{
-  operands[1] = copy_to_mode_reg (DFmode, operands[1]);
-  operands[2] = gen_reg_rtx (DFmode);
-  operands[3] = (rtx) assign_386_stack_local (SImode, 0);
-  operands[4] = (rtx) assign_386_stack_local (DImode, 1);
-}")
-
-(define_expand "fix_truncsfdi2"
-  [(set (match_dup 2)
-	(match_operand:SF 1 "register_operand" ""))
-   (parallel [(set (match_operand:DI 0 "general_operand" "")
-		   (fix:DI (fix:SF (match_dup 2))))
-	      (clobber (match_dup 2))
-	      (clobber (match_dup 3))
-	      (clobber (match_dup 4))
-	      (clobber (match_scratch:SI 5 ""))])]
-  "TARGET_80387"
-  "
-{
-  operands[1] = copy_to_mode_reg (SFmode, operands[1]);
-  operands[2] = gen_reg_rtx (SFmode);
-  operands[3] = (rtx) assign_386_stack_local (SImode, 0);
-  operands[4] = (rtx) assign_386_stack_local (DImode, 1);
-}")
-
-;; These match a signed conversion of either DFmode or SFmode to DImode.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
-	(fix:DI (fix:XF (match_operand:XF 1 "register_operand" "+f"))))
-   (clobber (match_dup 1))
-   (clobber (match_operand:SI 2 "memory_operand" "m"))
-   (clobber (match_operand:DI 3 "memory_operand" "m"))
-   (clobber (match_scratch:SI 4 "=&q"))]
-  "TARGET_80387"
-  "* return output_fix_trunc (insn, operands);")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
-	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "+f"))))
-   (clobber (match_dup 1))
-   (clobber (match_operand:SI 2 "memory_operand" "m"))
-   (clobber (match_operand:DI 3 "memory_operand" "m"))
-   (clobber (match_scratch:SI 4 "=&q"))]
-  "TARGET_80387"
-  "* return output_fix_trunc (insn, operands);")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
-	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "+f"))))
-   (clobber (match_dup 1))
-   (clobber (match_operand:SI 2 "memory_operand" "m"))
-   (clobber (match_operand:DI 3 "memory_operand" "m"))
-   (clobber (match_scratch:SI 4 "=&q"))]
-  "TARGET_80387"
-  "* return output_fix_trunc (insn, operands);")
-
-;; Signed MODE_FLOAT conversion to SImode.
-
-(define_expand "fix_truncxfsi2"
-  [(parallel [(set (match_operand:SI 0 "general_operand" "")
-		   (fix:SI
-		    (fix:XF (match_operand:XF 1 "register_operand" ""))))
-	      (clobber (match_dup 2))
-	      (clobber (match_dup 3))
-	      (clobber (match_scratch:SI 4 ""))])]
-  "TARGET_80387"
-  "
-{
-  operands[2] = (rtx) assign_386_stack_local (SImode, 0);
-  operands[3] = (rtx) assign_386_stack_local (DImode, 1);
-}")
-
-(define_expand "fix_truncdfsi2"
-  [(parallel [(set (match_operand:SI 0 "general_operand" "")
-		   (fix:SI
-		    (fix:DF (match_operand:DF 1 "register_operand" ""))))
-	      (clobber (match_dup 2))
-	      (clobber (match_dup 3))
-	      (clobber (match_scratch:SI 4 ""))])]
-  "TARGET_80387"
-  "
-{
-  operands[2] = (rtx) assign_386_stack_local (SImode, 0);
-  operands[3] = (rtx) assign_386_stack_local (DImode, 1);
-}")
-
-(define_expand "fix_truncsfsi2"
-  [(parallel [(set (match_operand:SI 0 "general_operand" "")
-		   (fix:SI
-		    (fix:SF (match_operand:SF 1 "register_operand" ""))))
-	      (clobber (match_dup 2))
-	      (clobber (match_dup 3))
-	      (clobber (match_scratch:SI 4 ""))])]
-  "TARGET_80387"
-  "
-{
-  operands[2] = (rtx) assign_386_stack_local (SImode, 0);
-  operands[3] = (rtx) assign_386_stack_local (DImode, 1);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-	(fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))
-   (clobber (match_operand:SI 2 "memory_operand" "m"))
-   (clobber (match_operand:DI 3 "memory_operand" "m"))
-   (clobber (match_scratch:SI 4 "=&q"))]
-  "TARGET_80387"
-  "* return output_fix_trunc (insn, operands);")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
-   (clobber (match_operand:SI 2 "memory_operand" "m"))
-   (clobber (match_operand:DI 3 "memory_operand" "m"))
-   (clobber (match_scratch:SI 4 "=&q"))]
-  "TARGET_80387"
-  "* return output_fix_trunc (insn, operands);")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))
-   (clobber (match_operand:SI 2 "memory_operand" "m"))
-   (clobber (match_operand:DI 3 "memory_operand" "m"))
-   (clobber (match_scratch:SI 4 "=&q"))]
-  "TARGET_80387"
-  "* return output_fix_trunc (insn, operands);")
-
-;; Conversion between fixed point and floating point.
-;; The actual pattern that matches these is at the end of this file.
-
-;; ??? Possibly represent floatunssidf2 here in gcc2.
-
-(define_expand "floatsisf2"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "")
-
-(define_expand "floatdisf2"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "")
-
-(define_expand "floatsidf2"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "")
-
-(define_expand "floatdidf2"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "")
-
-(define_expand "floatsixf2"
-  [(set (match_operand:XF 0 "register_operand" "")
-	(float:XF (match_operand:SI 1 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "")
-
-(define_expand "floatdixf2"
-  [(set (match_operand:XF 0 "register_operand" "")
-	(float:XF (match_operand:DI 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 && LONG_DOUBLE_TYPE_SIZE == 96"
-  "")
-
-;; This will convert from SImode or DImode to MODE_FLOAT.
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(float:XF (match_operand:DI 1 "nonimmediate_operand" "rm")))]
-  "TARGET_80387"
-  "*
-{
-  if (NON_STACK_REG_P (operands[1]))
-    {
-      output_op_from_reg (operands[1], AS1 (fild%z0,%1));
-      RET;
-    }
-  else if (GET_CODE (operands[1]) == MEM)
-    return AS1 (fild%z1,%1);
-  else
-    abort ();
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float:DF (match_operand:DI 1 "nonimmediate_operand" "rm")))]
-  "TARGET_80387"
-  "*
-{
-  if (NON_STACK_REG_P (operands[1]))
-    {
-      output_op_from_reg (operands[1], AS1 (fild%z0,%1));
-      RET;
-    }
-  else if (GET_CODE (operands[1]) == MEM)
-    return AS1 (fild%z1,%1);
-  else
-    abort ();
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float:SF (match_operand:DI 1 "nonimmediate_operand" "rm")))]
-  "TARGET_80387"
-  "*
-{
-  if (NON_STACK_REG_P (operands[1]))
-    {
-      output_op_from_reg (operands[1], AS1 (fild%z0,%1));
-      RET;
-    }
-  else if (GET_CODE (operands[1]) == MEM)
-    return AS1 (fild%z1,%1);
-  else
-    abort ();
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float:DF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
-  "TARGET_80387"
-  "*
-{
-  if (NON_STACK_REG_P (operands[1]))
-    {
-      output_op_from_reg (operands[1], AS1 (fild%z0,%1));
-      RET;
-    }
-  else if (GET_CODE (operands[1]) == MEM)
-    return AS1 (fild%z1,%1);
-  else
-    abort ();
-}")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f,f")
-	(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,!*r")))]
-  "TARGET_80387"
-  "*
-{
-  if (NON_STACK_REG_P (operands[1]))
-    {
-      output_op_from_reg (operands[1], AS1 (fild%z0,%1));
-      RET;
-    }
-  else if (GET_CODE (operands[1]) == MEM)
-    return AS1 (fild%z1,%1);
-  else
-    abort ();
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float:SF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
-  "TARGET_80387"
-  "*
-{
-  if (NON_STACK_REG_P (operands[1]))
-    {
-      output_op_from_reg (operands[1], AS1 (fild%z0,%1));
-      RET;
-    }
-  else if (GET_CODE (operands[1]) == MEM)
-    return AS1 (fild%z1,%1);
-  else
-    abort ();
-}")
-
-;;- add instructions
-
-(define_insn "*addsidi3_1"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,!&r,!r,o,!o")
-	(plus:DI (match_operand:DI 1 "general_operand" "0,0,0,o,riF,riF,o")
-		 (zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,roi,roi,ri,ri"))))
-   (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,&r"))]
-  ""
-  "*
-{
-  rtx low[3], high[3], xops[7];
-
-  CC_STATUS_INIT;
-
-  split_di (operands, 2, low, high);
-  high[2] = const0_rtx;
-  low[2]  = operands[2];
-
-  if (!rtx_equal_p (operands[0], operands[1]))
-    {
-      xops[0] = high[0];
-      xops[1] = low[0];
-      xops[2] = high[1];
-      xops[3] = low[1];
-
-      if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-	{
-	  output_asm_insn (AS2 (mov%L1,%3,%1), xops);
-	  output_asm_insn (AS2 (mov%L0,%2,%0), xops);
-	}
-      else
-	{
-	  xops[4] = high[2];
-	  xops[5] = low[2];
-	  xops[6] = operands[3];
-	  output_asm_insn (AS2 (mov%L6,%3,%6), xops);
-	  output_asm_insn (AS2 (add%L6,%5,%6), xops);
-	  output_asm_insn (AS2 (mov%L1,%6,%1), xops);
-	  output_asm_insn (AS2 (mov%L6,%2,%6), xops);
-	  output_asm_insn (AS2 (adc%L6,%4,%6), xops);
-	  output_asm_insn (AS2 (mov%L0,%6,%0), xops);
-	  RET;
-	}
-    }
-
-  output_asm_insn (AS2 (add%L0,%2,%0), low);
-  output_asm_insn (AS2 (adc%L0,%2,%0), high);
-  cc_status.value1 = high[0];
-  cc_status.flags = CC_NO_OVERFLOW;
-  RET;
-}"
-  [(set_attr "type" "binary")])
-
-(define_insn "addsidi3_2"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,&r,!&r,&r,o,o,!o")
-	(plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,o,o,ri,ri,i,r"))
-		 (match_operand:DI 1 "general_operand" "0,0,0,iF,ro,roiF,riF,o,o")))
-   (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,X,&r,&r"))]
-  ""
-  "*
-{
-  rtx low[3], high[3], xops[7];
-
-  CC_STATUS_INIT;
-
-  split_di (operands, 2, low, high);
-  high[2] = const0_rtx;
-  low[2]  = operands[2];
-
-  if (!rtx_equal_p (operands[0], operands[1]))
-    {
-      xops[0] = high[0];
-      xops[1] = low[0];
-      xops[2] = high[1];
-      xops[3] = low[1];
-
-      if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-	{
-	  if (rtx_equal_p (low[0], operands[2]))
-	    {
-	      output_asm_insn (AS2 (mov%L0,%2,%0), high);
-	      output_asm_insn (AS2 (add%L0,%1,%0), low);
-	      output_asm_insn (AS2 (adc%L0,%1,%0), high);
-	      RET;
-	    }
-	  if (rtx_equal_p (high[0], operands[2]))
-	    {
-	      if (GET_CODE (operands[0]) != MEM)
-		{
-		  output_asm_insn (AS2 (mov%L0,%2,%0), low);
-		  output_asm_insn (AS2 (mov%L0,%2,%0), high);
-		  output_asm_insn (AS2 (add%L0,%1,%0), low);
-		  output_asm_insn (AS2 (adc%L0,%1,%0), high);
-		}
-	      else
-		{
-		  /* It's too late to ask for a scratch now - but this
-		     will probably not happen too often.  */
-		  output_asm_insn (AS2 (add%L1,%2,%1), low);
-		  output_asm_insn (AS2 (mov%L0,%1,%0), low);
-		  output_asm_insn (AS2 (mov%L1,%2,%1), low);
-		  output_asm_insn (AS2 (mov%L0,%2,%0), high);
-		  output_asm_insn (AS2 (adc%L0,%1,%0), high);
-		  output_asm_insn (AS2 (sub%L1,%0,%1), low);
-		  output_asm_insn (AS1 (neg%L1,%1), low);
-		}
-	      RET;
-	    }
-	  output_asm_insn (AS2 (mov%L1,%3,%1), xops);
-	  output_asm_insn (AS2 (mov%L0,%2,%0), xops);
-	}
-      else
-	{
-	  xops[4] = high[2];
-	  xops[5] = low[2];
-	  xops[6] = operands[3];
-	  output_asm_insn (AS2 (mov%L6,%3,%6), xops);
-	  output_asm_insn (AS2 (add%L6,%5,%6), xops);
-	  output_asm_insn (AS2 (mov%L1,%6,%1), xops);
-	  output_asm_insn (AS2 (mov%L6,%2,%6), xops);
-	  output_asm_insn (AS2 (adc%L6,%4,%6), xops);
-	  output_asm_insn (AS2 (mov%L0,%6,%0), xops);
-	  RET;
-	}
-    }
-
-  output_asm_insn (AS2 (add%L0,%2,%0), low);
-  output_asm_insn (AS2 (adc%L0,%2,%0), high);
-  cc_status.value1 = high[0];
-  cc_status.flags = CC_NO_OVERFLOW;
-  RET;
-}"
-  [(set_attr "type" "binary")])
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "general_operand" "=&r,&ro,!r,o,!&r,!o,!o")
-	(plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0iF,or,riF,o")
-		 (match_operand:DI 2 "general_operand" "o,riF,0,or,or,oriF,o")))
-   (clobber (match_scratch:SI 3 "=X,X,X,&r,X,&r,&r"))]
-  ""
-  "*
-{
-  rtx low[3], high[3], xops[7], temp;
-
-  CC_STATUS_INIT;
-
-  if (rtx_equal_p (operands[0], operands[2]))
-    {
-      temp = operands[1];
-      operands[1] = operands[2];
-      operands[2] = temp;
-    }
-
-  split_di (operands, 3, low, high);
-  if (!rtx_equal_p (operands[0], operands[1]))
-    {
-      xops[0] = high[0];
-      xops[1] = low[0];
-      xops[2] = high[1];
-      xops[3] = low[1];
-
-      if (GET_CODE (operands[0]) != MEM)
-	{
-	  output_asm_insn (AS2 (mov%L1,%3,%1), xops);
-	  output_asm_insn (AS2 (mov%L0,%2,%0), xops);
-	}
-      else
-	{
-	  xops[4] = high[2];
-	  xops[5] = low[2];
-	  xops[6] = operands[3];
-	  output_asm_insn (AS2 (mov%L6,%3,%6), xops);
-	  output_asm_insn (AS2 (add%L6,%5,%6), xops);
-	  output_asm_insn (AS2 (mov%L1,%6,%1), xops);
-	  output_asm_insn (AS2 (mov%L6,%2,%6), xops);
-	  output_asm_insn (AS2 (adc%L6,%4,%6), xops);
-	  output_asm_insn (AS2 (mov%L0,%6,%0), xops);
-	  RET;
-	}
-    }
-
-  cc_status.value1 = high[0];
-  cc_status.flags = CC_NO_OVERFLOW;
-
-  if (GET_CODE (operands[3]) == REG && GET_CODE (operands[2]) != REG)
-    {
-      xops[0] = high[0];
-      xops[1] = low[0];
-      xops[2] = high[2];
-      xops[3] = low[2];
-      xops[4] = operands[3];
-
-      output_asm_insn (AS2 (mov%L4,%3,%4), xops);
-      output_asm_insn (AS2 (add%L1,%4,%1), xops);
-      output_asm_insn (AS2 (mov%L4,%2,%4), xops);
-      output_asm_insn (AS2 (adc%L0,%4,%0), xops);
-    }
-
-  else if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0)
-    {
-      output_asm_insn (AS2 (add%L0,%2,%0), low);
-      output_asm_insn (AS2 (adc%L0,%2,%0), high);
-    }
-
-  else
-    output_asm_insn (AS2 (add%L0,%2,%0), high);
-
-  RET;
-}"
-  [(set_attr "type" "binary")])
-
-;; On a 486, it is faster to do movl/addl than to do a single leal if
-;; operands[1] and operands[2] are both registers.
-
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "")
-	(plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
-		 (match_operand:SI 2 "general_operand" "")))]
-  ""
-  "IX86_EXPAND_BINARY_OPERATOR (PLUS, SImode, operands);")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
-	(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
-		 (match_operand:SI 2 "general_operand" "rmi,ri,ri")))]
-  "ix86_binary_operator_ok (PLUS, SImode, operands)"
-  "*
-{
-  if (REG_P (operands[0]) && REG_P (operands[1])
-      && (REG_P (operands[2]) || GET_CODE (operands[2]) == CONST_INT)
-      && REGNO (operands[0]) != REGNO (operands[1]))
-    {
-      if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
-	return AS2 (add%L0,%1,%0);
-
-      if (operands[2] == stack_pointer_rtx)
-	{
-	  rtx temp;
-
-	  temp = operands[1];
-	  operands[1] = operands[2];
-	  operands[2] = temp;
-	}
-
-      if (operands[2] != stack_pointer_rtx)
-	{
-	  CC_STATUS_INIT;
-	  operands[1] = SET_SRC (PATTERN (insn));
-	  return AS2 (lea%L0,%a1,%0);
-	}
-    }
-
-  if (!rtx_equal_p (operands[0], operands[1]))
-    output_asm_insn (AS2 (mov%L0,%1,%0), operands);
-
-  if (operands[2] == const1_rtx)
-    return AS1 (inc%L0,%0);
-
-  if (operands[2] == constm1_rtx)
-    return AS1 (dec%L0,%0);
-
-  /* subl $-128,%ebx is smaller than addl $128,%ebx. */
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) == 128)
-    {
-      /* This doesn't compute the carry bit in the same way
-       * as add%L0, but we use inc and dec above and they
-       * don't set the carry bit at all.  If inc/dec don't need
-       * a CC_STATUS_INIT, this doesn't either... */
-      operands[2] = GEN_INT (-128);
-      return AS2 (sub%L0,%2,%0);
-    }
-
-  return AS2 (add%L0,%2,%0);
-}"
-  [(set_attr "type" "binary")])
-
-;; addsi3 is faster, so put this after.
-
-(define_insn "movsi_lea"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (match_operand:QI 1 "address_operand" "p"))]
-  ""
-  "*
-{
-  /* Adding a constant to a register is faster with an add.  */
-  /* ??? can this ever happen? */
-  if (GET_CODE (operands[1]) == PLUS
-      && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
-      && rtx_equal_p (operands[0], XEXP (operands[1], 0)))
-    {
-      operands[1] = XEXP (operands[1], 1);
-
-      if (operands[1] == const1_rtx)
-        return AS1 (inc%L0,%0);
-
-      if (operands[1] == constm1_rtx)
-        return AS1 (dec%L0,%0);
-
-      return AS2 (add%L0,%1,%0);
-    }
-
-  CC_STATUS_INIT;
-  return AS2 (lea%L0,%a1,%0);
-}"
-  [(set_attr "type" "lea")])
-
-;; ??? `lea' here, for three operand add?  If leaw is used, only %bx,
-;; %si and %di can appear in SET_SRC, and output_asm_insn might not be
-;; able to handle the operand.  But leal always works?
-
-(define_expand "addhi3"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
-		 (match_operand:HI 2 "general_operand" "")))]
-  ""
-  "IX86_EXPAND_BINARY_OPERATOR (PLUS, HImode, operands);")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
-	(plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-		 (match_operand:HI 2 "general_operand" "ri,rm")))]
-  "ix86_binary_operator_ok (PLUS, HImode, operands)"
-  "*
-{
-  /* ??? what about offsettable memory references? */
-  if (!TARGET_PENTIUMPRO /* partial stalls are just too painful to risk. */
-      && QI_REG_P (operands[0])
-      && GET_CODE (operands[2]) == CONST_INT
-      && (INTVAL (operands[2]) & 0xff) == 0
-      && i386_cc_probably_useless_p (insn))
-    {
-      int byteval = (INTVAL (operands[2]) >> 8) & 0xff;
-      CC_STATUS_INIT;
-
-      if (byteval == 1)
-	return AS1 (inc%B0,%h0);
-      else if (byteval == 255)
-	return AS1 (dec%B0,%h0);
-
-      operands[2] = GEN_INT (byteval);
-      return AS2 (add%B0,%2,%h0);
-    }
-
-  /* Use a 32-bit operation when possible, to avoid the prefix penalty. */
-  if (REG_P (operands[0])
-      && i386_aligned_p (operands[2])
-      && i386_cc_probably_useless_p (insn))
-    {
-      CC_STATUS_INIT;
-
-      if (GET_CODE (operands[2]) == CONST_INT)
-	{
-	  HOST_WIDE_INT intval = 0xffff & INTVAL (operands[2]);
-
-	  if (intval == 1)
-	    return AS1 (inc%L0,%k0);
-
-	  if (intval == 0xffff)
-	    return AS1 (dec%L0,%k0);
-
-	  operands[2] = i386_sext16_if_const (operands[2]);
-	}
-      return AS2 (add%L0,%k2,%k0);
-    }
-
-  if (operands[2] == const1_rtx)
-    return AS1 (inc%W0,%0);
-
-  if (operands[2] == constm1_rtx
-      || (GET_CODE (operands[2]) == CONST_INT
-	  && INTVAL (operands[2]) == 65535))
-    return AS1 (dec%W0,%0);
-
-  return AS2 (add%W0,%2,%0);
-}"
-  [(set_attr "type" "binary")])
-
-(define_expand "addqi3"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(plus:QI (match_operand:QI 1 "general_operand" "")
-		 (match_operand:QI 2 "general_operand" "")))]
-  ""
-  "IX86_EXPAND_BINARY_OPERATOR (PLUS, QImode, operands);")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
-	(plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
-		 (match_operand:QI 2 "general_operand" "qn,qmn")))]
-  "ix86_binary_operator_ok (PLUS, QImode, operands)"
-  "*
-{
-  if (operands[2] == const1_rtx)
-    return AS1 (inc%B0,%0);
-
-  if (operands[2] == constm1_rtx
-      || (GET_CODE (operands[2]) == CONST_INT
-	  && INTVAL (operands[2]) == 255))
-    return AS1 (dec%B0,%0);
-
-  return AS2 (add%B0,%2,%0);
-}"
-  [(set_attr "type" "binary")])
-
-;Lennart Augustsson <augustss@cs.chalmers.se>
-;says this pattern just makes slower code:
-;	pushl	%ebp
-;	addl	$-80,(%esp)
-;instead of
-;	leal	-80(%ebp),%eax
-;	pushl	%eax
-;
-;(define_insn ""
-;  [(set (match_operand:SI 0 "push_operand" "=<")
-;	(plus:SI (match_operand:SI 1 "register_operand" "%r")
-;		 (match_operand:SI 2 "nonmemory_operand" "ri")))]
-;  ""
-;  "*
-;{
-;  rtx xops[4];
-;  xops[0] = operands[0];
-;  xops[1] = operands[1];
-;  xops[2] = operands[2];
-;  xops[3] = gen_rtx_MEM (SImode, stack_pointer_rtx);
-;  output_asm_insn (\"push%z1 %1\", xops);
-;  output_asm_insn (AS2 (add%z3,%2,%3), xops);
-;  RET;
-;}")
-
-;; The patterns that match these are at the end of this file.
-
-(define_expand "addxf3"
-  [(set (match_operand:XF 0 "register_operand" "")
-	(plus:XF (match_operand:XF 1 "register_operand" "")
-		 (match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387"
-  "")
-
-(define_expand "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(plus:DF (match_operand:DF 1 "nonimmediate_operand" "")
-		 (match_operand:DF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "")
-
-(define_expand "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(plus:SF (match_operand:SF 1 "nonimmediate_operand" "")
-		 (match_operand:SF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "")
-
-;;- subtract instructions
-
-(define_insn "subsidi3"
-  [(set (match_operand:DI 0 "general_operand" "=&r,&ro,&r,!&r,o,o,!o")
-	(minus:DI (match_operand:DI 1 "general_operand" "0iF,0,roiF,roiF,riF,o,o")
-		  (zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,o,ri,i,r"))))
-   (clobber (match_scratch:SI 3 "=X,X,X,X,X,&r,&r"))]
-  ""
-  "*
-{
-  rtx low[3], high[3], xops[7];
-
-  CC_STATUS_INIT;
-
-  split_di (operands, 2, low, high);
-  high[2] = const0_rtx;
-  low[2]  = operands[2];
-
-  if (!rtx_equal_p (operands[0], operands[1]))
-    {
-      xops[0] = high[0];
-      xops[1] = low[0];
-      xops[2] = high[1];
-      xops[3] = low[1];
-
-      if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-	{
-	  output_asm_insn (AS2 (mov%L1,%3,%1), xops);
-	  output_asm_insn (AS2 (mov%L0,%2,%0), xops);
-	}
-      else
-	{
-	  xops[4] = high[2];
-	  xops[5] = low[2];
-	  xops[6] = operands[3];
-	  output_asm_insn (AS2 (mov%L6,%3,%6), xops);
-	  output_asm_insn (AS2 (sub%L6,%5,%6), xops);
-	  output_asm_insn (AS2 (mov%L1,%6,%1), xops);
-	  output_asm_insn (AS2 (mov%L6,%2,%6), xops);
-	  output_asm_insn (AS2 (sbb%L6,%4,%6), xops);
-	  output_asm_insn (AS2 (mov%L0,%6,%0), xops);
-	  RET;
-	}
-    }
-
-  output_asm_insn (AS2 (sub%L0,%2,%0), low);
-  output_asm_insn (AS2 (sbb%L0,%2,%0), high);
-  cc_status.value1 = high[0];
-  cc_status.flags = CC_NO_OVERFLOW;
-
-  RET;
-}"
-  [(set_attr "type" "binary")])
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "general_operand" "=&r,&ro,o,o,!&r,!o")
-	(minus:DI (match_operand:DI 1 "general_operand" "0,0,0iF,or,roiF,roiF")
-		  (match_operand:DI 2 "general_operand" "or,riF,or,iF,roiF,roiF")))
-   (clobber (match_scratch:SI 3 "=X,X,&r,&r,X,&r"))]
-  ""
-  "*
-{
-  rtx low[3], high[3], xops[7];
-
-  CC_STATUS_INIT;
-
-  split_di (operands, 3, low, high);
-
-  if (!rtx_equal_p (operands[0], operands[1]))
-    {
-      xops[0] = high[0];
-      xops[1] = low[0];
-      xops[2] = high[1];
-      xops[3] = low[1];
-
-      if (GET_CODE (operands[0]) != MEM)
-	{
-	  output_asm_insn (AS2 (mov%L1,%3,%1), xops);
-	  output_asm_insn (AS2 (mov%L0,%2,%0), xops);
-	}
-      else
-	{
-	  xops[4] = high[2];
-	  xops[5] = low[2];
-	  xops[6] = operands[3];
-	  output_asm_insn (AS2 (mov%L6,%3,%6), xops);
-	  output_asm_insn (AS2 (sub%L6,%5,%6), xops);
-	  output_asm_insn (AS2 (mov%L1,%6,%1), xops);
-	  output_asm_insn (AS2 (mov%L6,%2,%6), xops);
-	  output_asm_insn (AS2 (sbb%L6,%4,%6), xops);
-	  output_asm_insn (AS2 (mov%L0,%6,%0), xops);
-	  RET;
-	}
-    }
-
-  cc_status.value1 = high[0];
-  cc_status.flags = CC_NO_OVERFLOW;
-
-  if (GET_CODE (operands[3]) == REG)
-    {
-      xops[0] = high[0];
-      xops[1] = low[0];
-      xops[2] = high[2];
-      xops[3] = low[2];
-      xops[4] = operands[3];
-
-      output_asm_insn (AS2 (mov%L4,%3,%4), xops);
-      output_asm_insn (AS2 (sub%L1,%4,%1), xops);
-      output_asm_insn (AS2 (mov%L4,%2,%4), xops);
-      output_asm_insn (AS2 (sbb%L0,%4,%0), xops);
-    }
-
-  else if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0)
-    {
-      output_asm_insn (AS2 (sub%L0,%2,%0), low);
-      output_asm_insn (AS2 (sbb%L0,%2,%0), high);
-    }
-
-  else
-      output_asm_insn (AS2 (sub%L0,%2,%0), high);
-
-
-  RET;
-}"
-  [(set_attr "type" "binary")])
-
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "")
-	(minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
-		  (match_operand:SI 2 "general_operand" "")))]
-  ""
-  "IX86_EXPAND_BINARY_OPERATOR (MINUS, SImode, operands);")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
-	(minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
-		  (match_operand:SI 2 "general_operand" "ri,rm")))]
-  "ix86_binary_operator_ok (MINUS, SImode, operands)"
-  "* return AS2 (sub%L0,%2,%0);"
-  [(set_attr "type" "binary")])
-
-(define_expand "subhi3"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
-		  (match_operand:HI 2 "general_operand" "")))]
-  ""
-  "IX86_EXPAND_BINARY_OPERATOR (MINUS, HImode, operands);")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
-	(minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
-		  (match_operand:HI 2 "general_operand" "ri,rm")))]
-  "ix86_binary_operator_ok (MINUS, HImode, operands)"
-  "*
-{
-  if (REG_P (operands[0])
-      && i386_aligned_p (operands[2])
-      && i386_cc_probably_useless_p (insn))
-    {
-      CC_STATUS_INIT;
-      operands[2] = i386_sext16_if_const (operands[2]);
-      return AS2 (sub%L0,%k2,%k0);
-    }
- return AS2 (sub%W0,%2,%0);
-}"
-  [(set_attr "type" "binary")])
-
-(define_expand "subqi3"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(minus:QI (match_operand:QI 1 "general_operand" "")
-		  (match_operand:QI 2 "general_operand" "")))]
-  ""
-  "IX86_EXPAND_BINARY_OPERATOR (MINUS, QImode, operands);")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
-	(minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
-		  (match_operand:QI 2 "general_operand" "qn,qmn")))]
-  "ix86_binary_operator_ok (MINUS, QImode, operands)"
-  "* return AS2 (sub%B0,%2,%0);"
-  [(set_attr "type" "binary")])
-
-;; The patterns that match these are at the end of this file.
-
-(define_expand "subxf3"
-  [(set (match_operand:XF 0 "register_operand" "")
-	(minus:XF (match_operand:XF 1 "register_operand" "")
-		  (match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387"
-  "")
-
-(define_expand "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(minus:DF (match_operand:DF 1 "nonimmediate_operand" "")
-		  (match_operand:DF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "")
-
-(define_expand "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(minus:SF (match_operand:SF 1 "nonimmediate_operand" "")
-		  (match_operand:SF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "")
-
-;;- multiply instructions
-
-;(define_insn "mulqi3"
-;  [(set (match_operand:QI 0 "register_operand" "=a")
-;	(mult:QI (match_operand:QI 1 "register_operand" "%0")
-;		 (match_operand:QI 2 "nonimmediate_operand" "qm")))]
-;  ""
-;  "imul%B0 %2,%0")
-
-(define_insn "mulhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(mult:HI (match_operand:HI 1 "nonimmediate_operand" "%0,rm")
-		 (match_operand:HI 2 "general_operand" "g,i")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == REG
-      && REGNO (operands[1]) == REGNO (operands[0])
-      && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG))
-    /* Assembler has weird restrictions.  */
-    return AS2 (imul%W0,%2,%0);
-  return AS3 (imul%W0,%2,%1,%0);
-}"
-  [(set_attr "type" "imul")])
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,rm")
-		 (match_operand:SI 2 "general_operand" "g,i")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == REG
-      && REGNO (operands[1]) == REGNO (operands[0])
-      && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG))
-    /* Assembler has weird restrictions.  */
-    return AS2 (imul%L0,%2,%0);
-  return AS3 (imul%L0,%2,%1,%0);
-}"
-  [(set_attr "type" "imul")])
-
-(define_insn "umulqihi3"
-  [(set (match_operand:HI 0 "register_operand" "=a")
-	(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
-		 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))]
-  ""
-  "mul%B0 %2"
-  [(set_attr "type" "imul")])
-
-(define_insn "mulqihi3"
-  [(set (match_operand:HI 0 "register_operand" "=a")
-	(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
-		 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))]
-  ""
-  "imul%B0 %2"
-  [(set_attr "type" "imul")])
-
-(define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=A")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
-		 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))]
-  "TARGET_WIDE_MULTIPLY"
-  "mul%L0 %2"
-  [(set_attr "type" "imul")])
-
-(define_insn "mulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=A")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
-		 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))]
-  "TARGET_WIDE_MULTIPLY"
-  "imul%L0 %2"
-  [(set_attr "type" "imul")])
-
-(define_insn "umulsi3_highpart"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%a"))
-					   (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))
-				  (const_int 32))))
-   (clobber (match_scratch:SI 3 "=a"))]
-  "TARGET_WIDE_MULTIPLY"
-  "mul%L0 %2"
-  [(set_attr "type" "imul")])
-
-(define_insn "smulsi3_highpart"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%a"))
-					   (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))
-				  (const_int 32))))
-   (clobber (match_scratch:SI 3 "=a"))]
-  "TARGET_WIDE_MULTIPLY"
-  "imul%L0 %2"
-  [(set_attr "type" "imul")])
-
-;; The patterns that match these are at the end of this file.
-
-(define_expand "mulxf3"
-  [(set (match_operand:XF 0 "register_operand" "")
-	(mult:XF (match_operand:XF 1 "register_operand" "")
-		 (match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387"
-  "")
-
-(define_expand "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(mult:DF (match_operand:DF 1 "register_operand" "")
-		 (match_operand:DF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "")
-
-(define_expand "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(mult:SF (match_operand:SF 1 "register_operand" "")
-		 (match_operand:SF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "")
-
-;;- divide instructions
-
-(define_insn "divqi3"
-  [(set (match_operand:QI 0 "register_operand" "=a")
-	(div:QI (match_operand:HI 1 "register_operand" "0")
-		(match_operand:QI 2 "nonimmediate_operand" "qm")))]
-  ""
-  "idiv%B0 %2")
-
-(define_insn "udivqi3"
-  [(set (match_operand:QI 0 "register_operand" "=a")
-	(udiv:QI (match_operand:HI 1 "register_operand" "0")
-		 (match_operand:QI 2 "nonimmediate_operand" "qm")))]
-  ""
-  "div%B0 %2"
-  [(set_attr "type" "idiv")])
-
-;; The patterns that match these are at the end of this file.
-
-(define_expand "divxf3"
-  [(set (match_operand:XF 0 "register_operand" "")
-	(div:XF (match_operand:XF 1 "register_operand" "")
-		(match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387"
-  "")
-
-(define_expand "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "")
- 	(div:DF (match_operand:DF 1 "register_operand" "")
- 		(match_operand:DF 2 "nonimmediate_operand" "")))]
-   "TARGET_80387"
-   "")
- 
-(define_expand "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(div:SF (match_operand:SF 1 "register_operand" "")
-		(match_operand:SF 2 "nonimmediate_operand" "")))]
-  "TARGET_80387"
-  "")
-
-;; Remainder instructions.
-
-(define_insn "divmodsi4"
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(div:SI (match_operand:SI 1 "register_operand" "0")
-		(match_operand:SI 2 "nonimmediate_operand" "rm")))
-   (set (match_operand:SI 3 "register_operand" "=&d")
-	(mod:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "*
-{
-#ifdef INTEL_SYNTAX
-  output_asm_insn (\"cdq\", operands);
-#else
-  output_asm_insn (\"cltd\", operands);
-#endif
-  return AS1 (idiv%L0,%2);
-}"
-  [(set_attr "type" "idiv")])
-
-(define_insn "divmodhi4"
-  [(set (match_operand:HI 0 "register_operand" "=a")
-	(div:HI (match_operand:HI 1 "register_operand" "0")
-		(match_operand:HI 2 "nonimmediate_operand" "rm")))
-   (set (match_operand:HI 3 "register_operand" "=&d")
-	(mod:HI (match_dup 1) (match_dup 2)))]
-  ""
-  "cwtd\;idiv%W0 %2"
-  [(set_attr "type" "idiv")])
-
-;; ??? Can we make gcc zero extend operand[0]?
-(define_insn "udivmodsi4"
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(udiv:SI (match_operand:SI 1 "register_operand" "0")
-		 (match_operand:SI 2 "nonimmediate_operand" "rm")))
-   (set (match_operand:SI 3 "register_operand" "=&d")
-	(umod:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "*
-{
-  output_asm_insn (AS2 (xor%L3,%3,%3), operands);
-  return AS1 (div%L0,%2);
-}"
-  [(set_attr "type" "idiv")])
-
-;; ??? Can we make gcc zero extend operand[0]?
-(define_insn "udivmodhi4"
-  [(set (match_operand:HI 0 "register_operand" "=a")
-	(udiv:HI (match_operand:HI 1 "register_operand" "0")
-		 (match_operand:HI 2 "nonimmediate_operand" "rm")))
-   (set (match_operand:HI 3 "register_operand" "=&d")
-	(umod:HI (match_dup 1) (match_dup 2)))]
-  ""
-  "*
-{
-  output_asm_insn (AS2 (xor%W0,%3,%3), operands);
-  return AS1 (div%W0,%2);
-}"
-  [(set_attr "type" "idiv")])
-
-/*
-;;this should be a valid double division which we may want to add
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(udiv:DI (match_operand:DI 1 "register_operand" "a")
-		 (match_operand:SI 2 "nonimmediate_operand" "rm")))
-   (set (match_operand:SI 3 "register_operand" "=d")
-	(umod:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "div%L0 %2,%0"
-  [(set_attr "type" "idiv")])
-*/
-
-;;- and instructions
-
-;; On i386,
-;;			movzbl %bl,%ebx
-;; is faster than
-;;			andl $255,%ebx
-;;
-;; but if the reg is %eax, then the "andl" is faster.
-;;
-;; On i486, the "andl" is always faster than the "movzbl".
-;;
-;; On both i386 and i486, a three operand AND is as fast with movzbl or
-;; movzwl as with andl, if operands[0] != operands[1].
-
-;; The `r' in `rm' for operand 3 looks redundant, but it causes
-;; optional reloads to be generated if op 3 is a pseudo in a stack slot.
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
-	(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "ri,rm")))]
-  ""
-  "*
-{
-  HOST_WIDE_INT intval;
-  if (!rtx_equal_p (operands[0], operands[1])
-      && rtx_equal_p (operands[0], operands[2]))
-    {
-      rtx tmp;
-      tmp = operands[1];
-      operands[1] = operands[2];
-      operands[2] = tmp;
-    }
-  switch (GET_CODE (operands[2]))
-    {
-    case CONST_INT:
-      if (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
-	break;
-      intval = INTVAL (operands[2]);
-      /* zero-extend 16->32? */
-      if (intval == 0xffff && REG_P (operands[0])
-	  && (! REG_P (operands[1])
-	      || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0)
-	  && (!TARGET_ZERO_EXTEND_WITH_AND || ! rtx_equal_p (operands[0], operands[1])))
-	{
-	  /* ??? tege: Should forget CC_STATUS only if we clobber a
-	     remembered operand.  Fix that later.  */
-	  CC_STATUS_INIT;
-#ifdef INTEL_SYNTAX
-	  return AS2 (movzx,%w1,%0);
-#else
-	  return AS2 (movz%W0%L0,%w1,%0);
-#endif
-	}
-
-      /* zero extend 8->32? */
-      if (intval == 0xff && REG_P (operands[0])
-	  && !(REG_P (operands[1]) && NON_QI_REG_P (operands[1]))
-	  && (! REG_P (operands[1])
-	      || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0)
-	  && (!TARGET_ZERO_EXTEND_WITH_AND || ! rtx_equal_p (operands[0], operands[1])))
-	{
-	  /* ??? tege: Should forget CC_STATUS only if we clobber a
-	     remembered operand.  Fix that later.  */
-	  CC_STATUS_INIT;
-#ifdef INTEL_SYNTAX
-	  return AS2 (movzx,%b1,%0);
-#else
-	  return AS2 (movz%B0%L0,%b1,%0);
-#endif
-	}
-
-      /* Check partial bytes.. non-QI-regs are not available */
-      if (REG_P (operands[0]) && ! QI_REG_P (operands[0]))
-	break;
-
-      /* only low byte has zero bits? */
-      if (~(intval | 0xff) == 0)
-	{
-	  intval &= 0xff;
-	  if (REG_P (operands[0]))
-	    {
-	      if (intval == 0)
-		{
-		  CC_STATUS_INIT;
-		  return AS2 (xor%B0,%b0,%b0);
-		}
-
-	      /* we're better off with the 32-bit version if reg != EAX */
-	      /* the value is sign-extended in 8 bits */
-	      if (REGNO (operands[0]) != 0 && (intval & 0x80))
-		break;
-	    }
-
-	  CC_STATUS_INIT;
-
-	  operands[2] = GEN_INT (intval);
-
-	  if (intval == 0)
-	    return AS2 (mov%B0,%2,%b0);
-
-	  return AS2 (and%B0,%2,%b0);
-	}
-
-      /* only second byte has zero? */
-      if (~(intval | 0xff00) == 0)
-	{
-	  CC_STATUS_INIT;
-
-	  intval = (intval >> 8) & 0xff;
-	  operands[2] = GEN_INT (intval);
-	  if (intval == 0)
-	    {
-	      if (REG_P (operands[0]))
-		return AS2 (xor%B0,%h0,%h0);
-	      operands[0] = adj_offsettable_operand (operands[0], 1);
-	      return AS2 (mov%B0,%2,%b0);
-	    }
-
-	  if (REG_P (operands[0]))
-	    return AS2 (and%B0,%2,%h0);
-
-	  operands[0] = adj_offsettable_operand (operands[0], 1);
-	  return AS2 (and%B0,%2,%b0);
-	}
-
-      if (REG_P (operands[0]))
-	break;
-
-      /* third byte has zero bits? */
-      if (~(intval | 0xff0000) == 0)
-	{
-	  intval = (intval >> 16) & 0xff;
-	  operands[0] = adj_offsettable_operand (operands[0], 2);
-byte_and_operation:
-	  CC_STATUS_INIT;
-	  operands[2] = GEN_INT (intval);
-	  if (intval == 0)
-	    return AS2 (mov%B0,%2,%b0);
-	  return AS2 (and%B0,%2,%b0);
-	}
-
-      /* fourth byte has zero bits? */
-      if (~(intval | 0xff000000) == 0)
-	{
-	  intval = (intval >> 24) & 0xff;
-	  operands[0] = adj_offsettable_operand (operands[0], 3);
-	  goto byte_and_operation;
-	}
-
-      /* Low word is zero? */
-      if (intval == 0xffff0000)
-        {
-word_zero_and_operation:
-	  CC_STATUS_INIT;
-	  operands[2] = const0_rtx;
-	  return AS2 (mov%W0,%2,%w0);
-	}
-
-      /* High word is zero? */
-      if (intval == 0x0000ffff)
-        {
-	  operands[0] = adj_offsettable_operand (operands[0], 2);
-	  goto word_zero_and_operation;
-	}
-
-    default:
-      break;
-    }
-
-  return AS2 (and%L0,%2,%0);
-}"
-  [(set_attr "type" "binary")])
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
-	(and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "ri,rm")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
-    {
-      /* Can we ignore the upper byte? */
-      if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
-	  && (INTVAL (operands[2]) & 0xff00) == 0xff00)
-	{
-	  CC_STATUS_INIT;
-
-	  if ((INTVAL (operands[2]) & 0xff) == 0)
-	    {
-	      operands[2] = const0_rtx;
-	      return AS2 (mov%B0,%2,%b0);
-	    }
-
-	  operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
-	  return AS2 (and%B0,%2,%b0);
-	}
-
-      /* Can we ignore the lower byte? */
-      /* ??? what about offsettable memory references? */
-      if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & 0xff) == 0xff)
-	{
-	  CC_STATUS_INIT;
-
-	  if ((INTVAL (operands[2]) & 0xff00) == 0)
-	    {
-	      operands[2] = const0_rtx;
-	      return AS2 (mov%B0,%2,%h0);
-	    }
-
-	  operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
-	  return AS2 (and%B0,%2,%h0);
-	}
-
-      /* use 32-bit ops on registers when there are no sign issues.. */
-      if (REG_P (operands[0]))
-	{
-	  if (!(INTVAL (operands[2]) & ~0x7fff))
-	    return AS2 (and%L0,%2,%k0);
-	}
-    }
-
-  if (REG_P (operands[0])
-      && i386_aligned_p (operands[2]))
-    {
-      CC_STATUS_INIT;
-      /* If op[2] is constant, we should zero-extend it and */
-      /* make a note that op[0] has been zero-extended, so  */
-      /* that we could use 32-bit ops on it forthwith, but  */
-      /* there is no such reg-note available. Instead we do */
-      /* a sign extension as that can result in shorter asm */
-      operands[2] = i386_sext16_if_const (operands[2]);
-      return AS2 (and%L0,%k2,%k0);
-    }
-
-  /* Use a 32-bit word with the upper bits set, invalidate CC */
-  if (GET_CODE (operands[2]) == CONST_INT
-      && i386_aligned_p (operands[0]))
-    {
-      HOST_WIDE_INT val = INTVAL (operands[2]);
-      CC_STATUS_INIT;
-      val |= ~0xffff;
-      if (val != INTVAL (operands[2]))
-	operands[2] = GEN_INT (val);
-      return AS2 (and%L0,%k2,%k0);
-    }
-
-  return AS2 (and%W0,%2,%0);
-}"
-  [(set_attr "type" "binary")])
-
-(define_insn "andqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
-	(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:QI 2 "general_operand" "qn,qmn")))]
-  ""
-  "* return AS2 (and%B0,%2,%0);"
-  [(set_attr "type" "binary")])
-
-/* I am nervous about these two.. add them later..
-;I presume this means that we have something in say op0= eax which is small
-;and we want to and it with memory so we can do this by just an
-;andb m,%al  and have success.
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(and:SI (zero_extend:SI
-		 (match_operand:HI 1 "nonimmediate_operand" "rm"))
-		(match_operand:SI 2 "general_operand" "0")))]
-  "GET_CODE (operands[2]) == CONST_INT
-   && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))"
-  "and%W0 %1,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=q")
-	(and:SI
-	 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))
-		(match_operand:SI 2 "register_operand" "0")))]
-  "GET_CODE (operands[2]) == CONST_INT
-   && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))"
-  "and%L0 %1,%0")
-
-*/
-
-;;- Bit set (inclusive or) instructions
-
-;; This optimizes known byte-wide operations to memory, and in some cases
-;; to QI registers.. Note that we don't want to use the QI registers too
-;; aggressively, because often the 32-bit register instruction is the same
-;; size, and likely to be faster on PentiumPro.
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
-	(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "ri,rm")))]
-  ""
-  "*
-{
-  HOST_WIDE_INT intval;
-  switch (GET_CODE (operands[2]))
-    {
-    case CONST_INT:
-
-      if (REG_P (operands[0]) && ! QI_REG_P (operands[0]))
-	break;
-
-      /* don't try to optimize volatile accesses */
-      if (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
-	break;
-
-      intval = INTVAL (operands[2]);
-      if ((intval & ~0xff) == 0)
-        {
-	  if (REG_P (operands[0]))
-	    {
-	      /* Do low byte access only for %eax or when high bit is set */
-	      if (REGNO (operands[0]) != 0 && !(intval & 0x80))
-	        break;
-	    }
-
-byte_or_operation:
-	    CC_STATUS_INIT;
-
-	    if (intval != INTVAL (operands[2]))
-	      operands[2] = GEN_INT (intval);
-
-	    if (intval == 0xff)
-	      return AS2 (mov%B0,%2,%b0);
-
-	    return AS2 (or%B0,%2,%b0);
-	}
-
-      /* second byte? */
-      if ((intval & ~0xff00) == 0)
-	{
-	  intval >>= 8;
-
-	  if (REG_P (operands[0]))
-	    {
-	      CC_STATUS_INIT;
-	      operands[2] = GEN_INT (intval);
-	      if (intval == 0xff)
-		return AS2 (mov%B0,%2,%h0);
-
-	      return AS2 (or%B0,%2,%h0);
-	    }
-
-	  operands[0] = adj_offsettable_operand (operands[0], 1);
-	  goto byte_or_operation;
-	}
-
-      if (REG_P (operands[0]))
-	break;
-
-      /* third byte? */
-      if ((intval & ~0xff0000) == 0)
-	{
-	  intval >>= 16;
-	  operands[0] = adj_offsettable_operand (operands[0], 2);
-	  goto byte_or_operation;
-	}
-
-      /* fourth byte? */
-      if ((intval & ~0xff000000) == 0)
-	{
-	  intval = (intval >> 24) & 0xff;
-	  operands[0] = adj_offsettable_operand (operands[0], 3);
-	  goto byte_or_operation;
-	}
-
-    default:
-      break;
-    }
-
-  return AS2 (or%L0,%2,%0);
-}"
-  [(set_attr "type" "binary")])
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
-	(ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "ri,rm")))]
-  ""
-  "*
-{
-  HOST_WIDE_INT intval;
-  switch (GET_CODE (operands[2]))
-    {
-    case CONST_INT:
-
-      if (REG_P (operands[0]) && ! QI_REG_P (operands[0]))
-	break;
-
-      /* don't try to optimize volatile accesses */
-      if (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
-	break;
-
-      intval = 0xffff & INTVAL (operands[2]);
-
-      if ((intval & 0xff00) == 0)
-        {
-	  if (REG_P (operands[0]))
-	    {
-	      /* Do low byte access only for %eax or when high bit is set */
-	      if (REGNO (operands[0]) != 0 && !(intval & 0x80))
-	        break;
-	    }
-
-byte_or_operation:
-	    CC_STATUS_INIT;
-
-	    if (intval == 0xff)
-	      return AS2 (mov%B0,%2,%b0);
-
-	    return AS2 (or%B0,%2,%b0);
-	}
-
-      /* high byte? */
-      if ((intval & 0xff) == 0)
-	{
-	  intval >>= 8;
-	  operands[2] = GEN_INT (intval);
-
-	  if (REG_P (operands[0]))
-	    {
-	      CC_STATUS_INIT;
-	      if (intval == 0xff)
-		return AS2 (mov%B0,%2,%h0);
-
-	      return AS2 (or%B0,%2,%h0);
-	    }
-
-	  operands[0] = adj_offsettable_operand (operands[0], 1);
-
-	  goto byte_or_operation;
-	}
-
-    default:
-      break;
-    }
-
-  if (REG_P (operands[0])
-      && i386_aligned_p (operands[2]))
-    {
-      CC_STATUS_INIT;
-      operands[2] = i386_sext16_if_const (operands[2]);
-      return AS2 (or%L0,%k2,%k0);
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT
-      && i386_aligned_p (operands[0]))
-    {
-      CC_STATUS_INIT;
-      intval = 0xffff & INTVAL (operands[2]);
-      if (intval != INTVAL (operands[2]))
-	operands[2] = GEN_INT (intval);
-      return AS2 (or%L0,%2,%k0);
-    }
-
-  return AS2 (or%W0,%2,%0);
-}"
-  [(set_attr "type" "binary")])
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
-	(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:QI 2 "general_operand" "qn,qmn")))]
-  ""
-  "* return AS2 (or%B0,%2,%0);"
-  [(set_attr "type" "binary")])
-
-;;- xor instructions
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
-	(xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "ri,rm")))]
-  ""
-  "*
-{
-  HOST_WIDE_INT intval;
-  switch (GET_CODE (operands[2]))
-    {
-    case CONST_INT:
-
-      if (REG_P (operands[0]) && ! QI_REG_P (operands[0]))
-	break;
-
-      /* don't try to optimize volatile accesses */
-      if (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
-	break;
-
-      intval = INTVAL (operands[2]);
-      if ((intval & ~0xff) == 0)
-        {
-	  if (REG_P (operands[0]))
-	    {
-	      /* Do low byte access only for %eax or when high bit is set */
-	      if (REGNO (operands[0]) != 0 && !(intval & 0x80))
-	        break;
-	    }
-
-byte_xor_operation:
-	    CC_STATUS_INIT;
-	      
-	    if (intval == 0xff)
-	      return AS1 (not%B0,%b0);
-
-	    if (intval != INTVAL (operands[2]))
-	      operands[2] = GEN_INT (intval);
-	    return AS2 (xor%B0,%2,%b0);
-	}
-
-      /* second byte? */
-      if ((intval & ~0xff00) == 0)
-	{
-	  intval >>= 8;
-
-	  if (REG_P (operands[0]))
-	    {
-	      CC_STATUS_INIT;
-	      if (intval == 0xff)
-		return AS1 (not%B0,%h0);
-
-	      operands[2] = GEN_INT (intval);
-	      return AS2 (xor%B0,%2,%h0);
-	    }
-
-	  operands[0] = adj_offsettable_operand (operands[0], 1);
-
-	  goto byte_xor_operation;
-	}
-
-      if (REG_P (operands[0]))
-	break;
-
-      /* third byte? */
-      if ((intval & ~0xff0000) == 0)
-	{
-	  intval >>= 16;
-	  operands[0] = adj_offsettable_operand (operands[0], 2);
-	  goto byte_xor_operation;
-	}
-
-      /* fourth byte? */
-      if ((intval & ~0xff000000) == 0)
-	{
-	  intval = (intval >> 24) & 0xff;
-	  operands[0] = adj_offsettable_operand (operands[0], 3);
-	  goto byte_xor_operation;
-	}
-
-    default:
-      break;
-    }
-
-  return AS2 (xor%L0,%2,%0);
-}"
-  [(set_attr "type" "binary")])
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
-	(xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "ri,rm")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
-    {
-      /* Can we ignore the upper byte? */
-      if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
-	  && (INTVAL (operands[2]) & 0xff00) == 0)
-	{
-	  CC_STATUS_INIT;
-	  if (INTVAL (operands[2]) & 0xffff0000)
-	    operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
-
-	  if (INTVAL (operands[2]) == 0xff)
-	    return AS1 (not%B0,%b0);
-
-	  return AS2 (xor%B0,%2,%b0);
-	}
-
-      /* Can we ignore the lower byte? */
-      /* ??? what about offsettable memory references? */
-      if (QI_REG_P (operands[0])
-	  && (INTVAL (operands[2]) & 0xff) == 0)
-	{
-	  CC_STATUS_INIT;
-	  operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
-
-	  if (INTVAL (operands[2]) == 0xff)
-	    return AS1 (not%B0,%h0);
-
-	  return AS2 (xor%B0,%2,%h0);
-	}
-    }
-
-  if (REG_P (operands[0])
-      && i386_aligned_p (operands[2]))
-    {
-      CC_STATUS_INIT;
-      operands[2] = i386_sext16_if_const (operands[2]);
-      return AS2 (xor%L0,%k2,%k0);
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT
-      && i386_aligned_p (operands[0]))
-    {
-      HOST_WIDE_INT intval;
-      CC_STATUS_INIT;
-      intval = 0xffff & INTVAL (operands[2]);
-      if (intval != INTVAL (operands[2]))
-	operands[2] = GEN_INT (intval);
-      return AS2 (xor%L0,%2,%k0);
-    }
-
-  return AS2 (xor%W0,%2,%0);
-}"
-  [(set_attr "type" "binary")])
-
-(define_insn "xorqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
-	(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:QI 2 "general_operand" "qn,qm")))]
-  ""
-  "* return AS2 (xor%B0,%2,%0);"
-  [(set_attr "type" "binary")])
-
-;; logical operations for DImode
-
-(define_insn "anddi3"
-  [(set (match_operand:DI 0 "general_operand" "=&r,&ro")
-	(and:DI (match_operand:DI 1 "general_operand" "0,0")
-		(match_operand:DI 2 "general_operand" "oriF,riF")))]
-  ""
-  "#"
-  [(set_attr "type" "binary")])
-
-
-(define_insn "iordi3"
-  [(set (match_operand:DI 0 "general_operand" "=&r,&ro")
-	(ior:DI (match_operand:DI 1 "general_operand" "0,0")
-		(match_operand:DI 2 "general_operand" "oriF,riF")))]
-  ""
-  "#"
-  [(set_attr "type" "binary")])
-
-(define_insn "xordi3"
-  [(set (match_operand:DI 0 "general_operand" "=&r,&ro")
-	(xor:DI (match_operand:DI 1 "general_operand" "0,0")
-		(match_operand:DI 2 "general_operand" "oriF,riF")))]
-  ""
-  "#"
-  [(set_attr "type" "binary")])
-
-(define_split
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operator:DI 3 "ix86_logical_operator"
-	  [(match_operand:DI 1 "general_operand" "")
-	   (match_operand:DI 2 "general_operand" "")]))]
-  ""
-  [(set (match_dup 4) (match_op_dup:SI 3 [(match_dup 6) (match_dup 8)]))
-   (set (match_dup 5) (match_op_dup:SI 3 [(match_dup 7) (match_dup 9)]))]
-  "split_di (&operands[0], 1, &operands[4], &operands[5]);
-   split_di (&operands[1], 1, &operands[6], &operands[7]);
-   split_di (&operands[2], 1, &operands[8], &operands[9]);")
-
-;;- negation instructions
-
-(define_insn "negdi2"
-  [(set (match_operand:DI 0 "general_operand" "=&ro")
-	(neg:DI (match_operand:DI 1 "general_operand" "0")))]
-  ""
-  "*
-{
-  rtx xops[2], low[1], high[1];
-
-  CC_STATUS_INIT;
-
-  split_di (operands, 1, low, high);
-  xops[0] = const0_rtx;
-  xops[1] = high[0];
-
-  output_asm_insn (AS1 (neg%L0,%0), low);
-  output_asm_insn (AS2 (adc%L1,%0,%1), xops);
-  output_asm_insn (AS1 (neg%L0,%0), high);
-  RET;
-}")
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-	(neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
-  ""
-  "neg%L0 %0")
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
-	(neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
-  ""
-  "neg%W0 %0")
-
-(define_insn "negqi2"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
-	(neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
-  ""
-  "neg%B0 %0")
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (match_operand:SF 1 "register_operand" "0")))]
-  "TARGET_80387"
-  "fchs")
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (match_operand:DF 1 "register_operand" "0")))]
-  "TARGET_80387"
-  "fchs")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (float_extend:DF (match_operand:SF 1 "register_operand" "0"))))]
-  "TARGET_80387"
-  "fchs")
-
-(define_insn "negxf2"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(neg:XF (match_operand:XF 1 "register_operand" "0")))]
-  "TARGET_80387"
-  "fchs")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(neg:XF (float_extend:XF (match_operand:DF 1 "register_operand" "0"))))]
-  "TARGET_80387"
-  "fchs")
-
-;; Absolute value instructions
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(abs:SF (match_operand:SF 1 "register_operand" "0")))]
-  "TARGET_80387"
-  "fabs"
-  [(set_attr "type" "fpop")])
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(abs:DF (match_operand:DF 1 "register_operand" "0")))]
-  "TARGET_80387"
-  "fabs"
-  [(set_attr "type" "fpop")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(abs:DF (float_extend:DF (match_operand:SF 1 "register_operand" "0"))))]
-  "TARGET_80387"
-  "fabs"
-  [(set_attr "type" "fpop")])
-
-(define_insn "absxf2"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(abs:XF (match_operand:XF 1 "register_operand" "0")))]
-  "TARGET_80387"
-  "fabs"
-  [(set_attr "type" "fpop")])
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(abs:XF (float_extend:XF (match_operand:DF 1 "register_operand" "0"))))]
-  "TARGET_80387"
-  "fabs"
-  [(set_attr "type" "fpop")])
-
-(define_insn "sqrtsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
-  "fsqrt")
-
-(define_insn "sqrtdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fsqrt")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(sqrt:DF (float_extend:DF
-		  (match_operand:SF 1 "register_operand" "0"))))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
-  "fsqrt")
-
-(define_insn "sqrtxf2"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
-   && (TARGET_IEEE_FP || flag_fast_math) "
-  "fsqrt")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(sqrt:XF (float_extend:XF
-		  (match_operand:DF 1 "register_operand" "0"))))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
-  "fsqrt")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(sqrt:XF (float_extend:XF
-		  (match_operand:SF 1 "register_operand" "0"))))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
-  "fsqrt")
-
-(define_insn "sindf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
-  "fsin")
-
-(define_insn "sinsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
-  "fsin")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(unspec:DF [(float_extend:DF
-		     (match_operand:SF 1 "register_operand" "0"))] 1))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
-  "fsin")
-
-(define_insn "sinxf2"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
-  "fsin")
-
-(define_insn "cosdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
-  "fcos")
-
-(define_insn "cossf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
-  "fcos")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(unspec:DF [(float_extend:DF
-		     (match_operand:SF 1 "register_operand" "0"))] 2))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
-  "fcos")
-
-(define_insn "cosxf2"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
-  "fcos")
-
-;;- one complement instructions
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-	(not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
-  ""
-  "not%L0 %0")
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
-	(not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
-  ""
-  "not%W0 %0")
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
-	(not:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
-  ""
-  "not%B0 %0")
-
-;;- arithmetic shift instructions
-
-;; DImode shifts are implemented using the i386 "shift double" opcode,
-;; which is written as "sh[lr]d[lw] imm,reg,reg/mem".  If the shift count
-;; is variable, then the count is in %cl and the "imm" operand is dropped
-;; from the assembler input.
-
-;; This instruction shifts the target reg/mem as usual, but instead of
-;; shifting in zeros, bits are shifted in from reg operand.  If the insn
-;; is a left shift double, bits are taken from the high order bits of
-;; reg, else if the insn is a shift right double, bits are taken from the
-;; low order bits of reg.  So if %eax is "1234" and %edx is "5678",
-;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
-
-;; Since sh[lr]d does not change the `reg' operand, that is done
-;; separately, making all shifts emit pairs of shift double and normal
-;; shift.  Since sh[lr]d does not shift more than 31 bits, and we wish to
-;; support a 63 bit shift, each shift where the count is in a reg expands
-;; to a pair of shifts, a branch, a shift by 32 and a label.
-
-;; If the shift count is a constant, we need never emit more than one
-;; shift pair, instead using moves and sign extension for counts greater
-;; than 31.
-
-(define_expand "ashldi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashift:DI (match_operand:DI 1 "register_operand" "")
-		   (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT
-      || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
-    {
-      operands[2] = copy_to_mode_reg (QImode, operands[2]);
-      emit_insn (gen_ashldi3_non_const_int (operands[0], operands[1],
-					    operands[2]));
-    }
-  else
-    emit_insn (gen_ashldi3_const_int (operands[0], operands[1], operands[2]));
-
-  DONE;
-}")
-
-(define_insn "ashldi3_const_int"
-  [(set (match_operand:DI 0 "register_operand" "=&r")
-	(ashift:DI (match_operand:DI 1 "register_operand" "0")
-		   (match_operand:QI 2 "const_int_operand" "J")))]
-  "CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')"
-  "*
-{
-  rtx xops[4], low[1], high[1];
-
-  CC_STATUS_INIT;
-
-  split_di (operands, 1, low, high);
-  xops[0] = operands[2];
-  xops[1] = const1_rtx;
-  xops[2] = low[0];
-  xops[3] = high[0];
-
-  if (INTVAL (xops[0]) > 31)
-    {
-      output_asm_insn (AS2 (mov%L3,%2,%3), xops);	/* Fast shift by 32 */
-      output_asm_insn (AS2 (xor%L2,%2,%2), xops);
-
-      if (INTVAL (xops[0]) > 32)
-        {
-	  xops[0] = GEN_INT (INTVAL (xops[0]) - 32);
-	  output_asm_insn (AS2 (sal%L3,%0,%3), xops); /* Remaining shift */
-	}
-    }
-  else
-    {
-      output_asm_insn (AS3 (shld%L3,%0,%2,%3), xops);
-      output_asm_insn (AS2 (sal%L2,%0,%2), xops);
-    }
-  RET;
-}")
-
-(define_insn "ashldi3_non_const_int"
-  [(set (match_operand:DI 0 "register_operand" "=&r")
-	(ashift:DI (match_operand:DI 1 "register_operand" "0")
-		   (match_operand:QI 2 "register_operand" "c")))]
-  ""
-  "*
-{
-  rtx xops[5], low[1], high[1];
-
-  CC_STATUS_INIT;
-
-  split_di (operands, 1, low, high);
-  xops[0] = operands[2];
-  xops[1] = GEN_INT (32);
-  xops[2] = low[0];
-  xops[3] = high[0];
-  xops[4] = gen_label_rtx ();
-
-  output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops);
-  output_asm_insn (AS2 (sal%L2,%0,%2), xops);
-  output_asm_insn (AS2 (test%B0,%1,%b0), xops);
-  output_asm_insn (AS1 (je,%X4), xops);
-  output_asm_insn (AS2 (mov%L3,%2,%3), xops);	/* Fast shift by 32 */
-  output_asm_insn (AS2 (xor%L2,%2,%2), xops);
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
-                             CODE_LABEL_NUMBER (xops[4]));
-  RET;
-}")
-
-;; On i386 and i486, "addl reg,reg" is faster than "sall $1,reg"
-;; On i486, movl/sall appears slightly faster than leal, but the leal
-;; is smaller - use leal for now unless the shift count is 1.
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
-	(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "r,0")
-		   (match_operand:SI 2 "nonmemory_operand" "M,cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
-    {
-      if (TARGET_DOUBLE_WITH_ADD && INTVAL (operands[2]) == 1)
-	{
-	  output_asm_insn (AS2 (mov%L0,%1,%0), operands);
-	  return AS2 (add%L0,%1,%0);
-	}
-      else
-        {
-          CC_STATUS_INIT;
-
-	  if (operands[1] == stack_pointer_rtx)
-	    {
-	      output_asm_insn (AS2 (mov%L0,%1,%0), operands);
-	      operands[1] = operands[0];
-	    }
-          operands[1] = gen_rtx_MULT (SImode, operands[1],
-				      GEN_INT (1 << INTVAL (operands[2])));
-	  return AS2 (lea%L0,%a1,%0);
-	}
-    }
-
-  if (REG_P (operands[2]))
-    return AS2 (sal%L0,%b2,%0);
-
-  if (REG_P (operands[0]) && operands[2] == const1_rtx)
-    return AS2 (add%L0,%0,%0);
-
-  return AS2 (sal%L0,%2,%0);
-}")
-
-(define_insn "ashlhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
-	(ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-		   (match_operand:HI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (sal%W0,%b2,%0);
-
-  if (REG_P (operands[0]) && operands[2] == const1_rtx)
-    return AS2 (add%W0,%0,%0);
-
-  return AS2 (sal%W0,%2,%0);
-}")
-
-(define_insn "ashlqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
-	(ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-		   (match_operand:QI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (sal%B0,%b2,%0);
-
-  if (REG_P (operands[0]) && operands[2] == const1_rtx)
-    return AS2 (add%B0,%0,%0);
-
-  return AS2 (sal%B0,%2,%0);
-}")
-
-;; See comment above `ashldi3' about how this works.
-
-(define_expand "ashrdi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT
-      || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
-    {
-      operands[2] = copy_to_mode_reg (QImode, operands[2]);
-      emit_insn (gen_ashrdi3_non_const_int (operands[0], operands[1],
-					    operands[2]));
-    }
-  else
-    emit_insn (gen_ashrdi3_const_int (operands[0], operands[1], operands[2]));
-
-  DONE;
-}")
-
-(define_insn "ashldi3_32"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
-	(ashift:DI (match_operand:DI 1 "nonimmediate_operand" "ro,r")
-		   (const_int 32)))]
-  ""
-  "*
-{
-  rtx low[2], high[2], xops[4];
-
-  split_di (operands, 2, low, high);
-  xops[0] = high[0];
-  xops[1] = low[1];
-  xops[2] = low[0];
-  xops[3] = const0_rtx;
-  if (!rtx_equal_p (xops[0], xops[1]))
-    output_asm_insn (AS2 (mov%L0,%1,%0), xops);
-
-  if (GET_CODE (low[0]) == MEM)
-    output_asm_insn (AS2 (mov%L2,%3,%2), xops);
-  else
-    output_asm_insn (AS2 (xor%L2,%2,%2), xops);
-
-  RET;
-}")
-
-(define_insn "ashrdi3_const_int"
-  [(set (match_operand:DI 0 "register_operand" "=&r")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
-		     (match_operand:QI 2 "const_int_operand" "J")))]
-  "CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')"
-  "*
-{
-  rtx xops[4], low[1], high[1];
-
-  CC_STATUS_INIT;
-
-  split_di (operands, 1, low, high);
-  xops[0] = operands[2];
-  xops[1] = const1_rtx;
-  xops[2] = low[0];
-  xops[3] = high[0];
-
-  if (INTVAL (xops[0]) > 31)
-    {
-      xops[1] = GEN_INT (31);
-      output_asm_insn (AS2 (mov%L2,%3,%2), xops);
-      output_asm_insn (AS2 (sar%L3,%1,%3), xops);	/* shift by 32 */
-
-      if (INTVAL (xops[0]) > 32)
-        {
-	  xops[0] = GEN_INT (INTVAL (xops[0]) - 32);
-	  output_asm_insn (AS2 (sar%L2,%0,%2), xops); /* Remaining shift */
-	}
-    }
-  else
-    {
-      output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops);
-      output_asm_insn (AS2 (sar%L3,%0,%3), xops);
-    }
-
-  RET;
-}")
-
-(define_insn "ashrdi3_non_const_int"
-  [(set (match_operand:DI 0 "register_operand" "=&r")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
-		     (match_operand:QI 2 "register_operand" "c")))]
-  ""
-  "*
-{
-  rtx xops[5], low[1], high[1];
-
-  CC_STATUS_INIT;
-
-  split_di (operands, 1, low, high);
-  xops[0] = operands[2];
-  xops[1] = GEN_INT (32);
-  xops[2] = low[0];
-  xops[3] = high[0];
-  xops[4] = gen_label_rtx ();
-
-  output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops);
-  output_asm_insn (AS2 (sar%L3,%0,%3), xops);
-  output_asm_insn (AS2 (test%B0,%1,%b0), xops);
-  output_asm_insn (AS1 (je,%X4), xops);
-  xops[1] = GEN_INT (31);
-  output_asm_insn (AS2 (mov%L2,%3,%2), xops);
-  output_asm_insn (AS2 (sar%L3,%1,%3), xops);	/* shift by 32 */
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
-                             CODE_LABEL_NUMBER (xops[4]));
-  RET;
-}")
-
-(define_insn "ashrsi3_31"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,d")
-	(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,a")
-		     (const_int 31)))]
-  "!TARGET_PENTIUM || optimize_size"
-  "@
-    sar%L0 $31,%0
-    cltd")
-
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-	(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-		     (match_operand:SI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (sar%L0,%b2,%0);
-  else
-    return AS2 (sar%L0,%2,%0);
-}")
-
-(define_insn "ashrhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
-	(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-		     (match_operand:HI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (sar%W0,%b2,%0);
-  else
-    return AS2 (sar%W0,%2,%0);
-}")
-
-(define_insn "ashrqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
-	(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-		     (match_operand:QI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (sar%B0,%b2,%0);
-  else
-    return AS2 (sar%B0,%2,%0);
-}")
-
-;;- logical shift instructions
-
-;; See comment above `ashldi3' about how this works.
-
-(define_expand "lshrdi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT
-      || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
-    {
-      operands[2] = copy_to_mode_reg (QImode, operands[2]);
-      emit_insn (gen_lshrdi3_non_const_int (operands[0], operands[1],
-					    operands[2]));
-    }
-  else
-    emit_insn (gen_lshrdi3_const_int (operands[0], operands[1], operands[2]));
-
-  DONE;
-}")
-
-(define_insn "lshrdi3_32"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
-	(lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "ro,r")
-		     (const_int 32)))]
-  ""
-  "*
-{
-  rtx low[2], high[2], xops[4];
-
-  split_di (operands, 2, low, high);
-  xops[0] = low[0];
-  xops[1] = high[1];
-  xops[2] = high[0];
-  xops[3] = const0_rtx;
-  if (!rtx_equal_p (xops[0], xops[1]))
-    output_asm_insn (AS2 (mov%L0,%1,%0), xops);
-
-  if (GET_CODE (low[0]) == MEM)
-    output_asm_insn (AS2 (mov%L2,%3,%2), xops);
-  else
-    output_asm_insn (AS2 (xor%L2,%2,%2), xops);
-
-  RET;
-}")
-
-(define_insn "lshrdi3_const_int"
-  [(set (match_operand:DI 0 "register_operand" "=&r")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
-		     (match_operand:QI 2 "const_int_operand" "J")))]
-  "CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')"
-  "*
-{
-  rtx xops[4], low[1], high[1];
-
-  CC_STATUS_INIT;
-
-  split_di (operands, 1, low, high);
-  xops[0] = operands[2];
-  xops[1] = const1_rtx;
-  xops[2] = low[0];
-  xops[3] = high[0];
-
-  if (INTVAL (xops[0]) > 31)
-    {
-      output_asm_insn (AS2 (mov%L2,%3,%2), xops);	/* Fast shift by 32 */
-      output_asm_insn (AS2 (xor%L3,%3,%3), xops);
-
-      if (INTVAL (xops[0]) > 32)
-        {
-	  xops[0] = GEN_INT (INTVAL (xops[0]) - 32);
-	  output_asm_insn (AS2 (shr%L2,%0,%2), xops); /* Remaining shift */
-	}
-    }
-  else
-    {
-      output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops);
-      output_asm_insn (AS2 (shr%L3,%0,%3), xops);
-    }
-
-  RET;
-}")
-
-(define_insn "lshrdi3_non_const_int"
-  [(set (match_operand:DI 0 "register_operand" "=&r")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
-		     (match_operand:QI 2 "register_operand" "c")))]
-  ""
-  "*
-{
-  rtx xops[5], low[1], high[1];
-
-  CC_STATUS_INIT;
-
-  split_di (operands, 1, low, high);
-  xops[0] = operands[2];
-  xops[1] = GEN_INT (32);
-  xops[2] = low[0];
-  xops[3] = high[0];
-  xops[4] = gen_label_rtx ();
-
-  output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops);
-  output_asm_insn (AS2 (shr%L3,%0,%3), xops);
-  output_asm_insn (AS2 (test%B0,%1,%b0), xops);
-  output_asm_insn (AS1 (je,%X4), xops);
-  output_asm_insn (AS2 (mov%L2,%3,%2), xops);	/* Fast shift by 32 */
-  output_asm_insn (AS2 (xor%L3,%3,%3), xops);
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
-                             CODE_LABEL_NUMBER (xops[4]));
-  RET;
-}")
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-	(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-		     (match_operand:SI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (shr%L0,%b2,%0);
-  else
-    return AS2 (shr%L0,%2,%1);
-}")
-
-(define_insn "lshrhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
-	(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-		     (match_operand:HI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (shr%W0,%b2,%0);
-  else
-    return AS2 (shr%W0,%2,%0);
-}")
-
-(define_insn "lshrqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
-	(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-		     (match_operand:QI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (shr%B0,%b2,%0);
-  else
-    return AS2 (shr%B0,%2,%0);
-}")
-
-;;- rotate instructions
-
-(define_insn "rotlsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-	(rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-		   (match_operand:SI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (rol%L0,%b2,%0);
-  else
-    return AS2 (rol%L0,%2,%0);
-}")
-
-(define_insn "rotlhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
-	(rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-		   (match_operand:HI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (rol%W0,%b2,%0);
-  else
-    return AS2 (rol%W0,%2,%0);
-}")
-
-(define_insn "rotlqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
-	(rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-		   (match_operand:QI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (rol%B0,%b2,%0);
-  else
-    return AS2 (rol%B0,%2,%0);
-}")
-
-(define_insn "rotrsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-	(rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-		     (match_operand:SI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (ror%L0,%b2,%0);
-  else
-    return AS2 (ror%L0,%2,%0);
-}")
-
-(define_insn "rotrhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
-	(rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-		     (match_operand:HI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (ror%W0,%b2,%0);
-  else
-    return AS2 (ror%W0,%2,%0);
-}")
-
-(define_insn "rotrqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
-	(rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-		     (match_operand:QI 2 "nonmemory_operand" "cI")))]
-  ""
-  "*
-{
-  if (REG_P (operands[2]))
-    return AS2 (ror%B0,%b2,%0);
-  else
-    return AS2 (ror%B0,%2,%0);
-}")
-
-/*
-;; This usually looses.  But try a define_expand to recognize a few case
-;; we can do efficiently, such as accessing the "high" QImode registers,
-;; %ah, %bh, %ch, %dh.
-;; ??? Note this has a botch on the mode of operand 0, which needs to be
-;; fixed if this is ever enabled.
-(define_insn "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+&r")
-			 (match_operand:SI 1 "immediate_operand" "i")
-			 (match_operand:SI 2 "immediate_operand" "i"))
-	(match_operand:SI 3 "nonmemory_operand" "ri"))]
-  ""
-  "*
-{
-  if (INTVAL (operands[1]) + INTVAL (operands[2]) > GET_MODE_BITSIZE (SImode))
-    abort ();
-  if (GET_CODE (operands[3]) == CONST_INT)
-    {
-      unsigned int mask = (1 << INTVAL (operands[1])) - 1; 
-      operands[1] = GEN_INT (~(mask << INTVAL (operands[2])));
-      output_asm_insn (AS2 (and%L0,%1,%0), operands);
-      operands[3] = GEN_INT (INTVAL (operands[3]) << INTVAL (operands[2]));
-      output_asm_insn (AS2 (or%L0,%3,%0), operands);
-    }
-  else
-    {
-      operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
-      if (INTVAL (operands[2]))
-	output_asm_insn (AS2 (ror%L0,%2,%0), operands);
-      output_asm_insn (AS3 (shrd%L0,%1,%3,%0), operands);
-      operands[2] = GEN_INT (BITS_PER_WORD
-			     - INTVAL (operands[1]) - INTVAL (operands[2]));
-      if (INTVAL (operands[2]))
-	output_asm_insn (AS2 (ror%L0,%2,%0), operands);
-    }
-  RET;
-}")
-*/
-/*
-;; ??? There are problems with the mode of operand[3].  The point of this
-;; is to represent an HImode move to a "high byte" register.
-
-(define_expand "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
-			 (match_operand:SI 1 "immediate_operand" "")
-			 (match_operand:SI 2 "immediate_operand" ""))
-	(match_operand:QI 3 "nonmemory_operand" "ri"))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) != CONST_INT
-      || GET_CODE (operands[2]) != CONST_INT)
-    FAIL;
-
-  if (! (INTVAL (operands[1]) == 8
-	 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 0))
-      && ! INTVAL (operands[1]) == 1)
-    FAIL;
-}")
-*/
-
-;; On i386, the register count for a bit operation is *not* truncated,
-;; so SHIFT_COUNT_TRUNCATED must not be defined.
-
-;; On i486, the shift & or/and code is faster than bts or btr.  If
-;; operands[0] is a MEM, the bt[sr] is half as fast as the normal code.
-
-;; On i386, bts is a little faster if operands[0] is a reg, and a
-;; little slower if operands[0] is a MEM, than the shift & or/and code.
-;; Use bts & btr, since they reload better.
-
-;; General bit set and clear.
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+rm")
-			 (const_int 1)
-			 (match_operand:SI 2 "register_operand" "r"))
-	(match_operand:SI 3 "const_int_operand" "n"))]
-  "TARGET_USE_BIT_TEST && GET_CODE (operands[2]) != CONST_INT"
-  "*
-{
-  CC_STATUS_INIT;
-
-  if (INTVAL (operands[3]) == 1)
-    return AS2 (bts%L0,%2,%0);
-  else
-    return AS2 (btr%L0,%2,%0);
-}")
-
-;; Bit complement.  See comments on previous pattern.
-;; ??? Is this really worthwhile?
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-	(xor:SI (ashift:SI (const_int 1)
-			   (match_operand:SI 1 "register_operand" "r"))
-		(match_operand:SI 2 "nonimmediate_operand" "0")))]
-  "TARGET_USE_BIT_TEST && GET_CODE (operands[1]) != CONST_INT"
-  "*
-{
-  CC_STATUS_INIT;
-
-  return AS2 (btc%L0,%1,%0);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-	(xor:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-		(ashift:SI (const_int 1)
-			   (match_operand:SI 2 "register_operand" "r"))))]
-  "TARGET_USE_BIT_TEST && GET_CODE (operands[2]) != CONST_INT"
-  "*
-{
-  CC_STATUS_INIT;
-
-  return AS2 (btc%L0,%2,%0);
-}")
-
-;; Recognizers for bit-test instructions.
-
-;; The bt opcode allows a MEM in operands[0].  But on both i386 and
-;; i486, it is faster to copy a MEM to REG and then use bt, than to use
-;; bt on the MEM directly.
-
-;; ??? The first argument of a zero_extract must not be reloaded, so
-;; don't allow a MEM in the operand predicate without allowing it in the
-;; constraint.
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r")
-			    (const_int 1)
-			    (match_operand:SI 1 "register_operand" "r")))]
-  "GET_CODE (operands[1]) != CONST_INT"
-  "*
-{
-  cc_status.flags |= CC_Z_IN_NOT_C;
-  return AS2 (bt%L0,%1,%0);
-}")
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r")
-			    (match_operand:SI 1 "const_int_operand" "n")
-			    (match_operand:SI 2 "const_int_operand" "n")))]
-  ""
-  "*
-{
-  unsigned int mask;
-
-  mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]);
-  operands[1] = GEN_INT (mask);
-
-  if (QI_REG_P (operands[0]))
-    {
-      if ((mask & ~0xff) == 0)
-        {
-	  cc_status.flags |= CC_NOT_NEGATIVE;
-	  return AS2 (test%B0,%1,%b0);
-	}
-
-      if ((mask & ~0xff00) == 0)
-        {
-	  cc_status.flags |= CC_NOT_NEGATIVE;
-	  operands[1] = GEN_INT (mask >> 8);
-	  return AS2 (test%B0,%1,%h0);
-	}
-    }
-
-  return AS2 (test%L0,%1,%0);
-}")
-
-;; ??? All bets are off if operand 0 is a volatile MEM reference.
-;; The CPU may access unspecified bytes around the actual target byte.
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
-			    (match_operand:SI 1 "const_int_operand" "n")
-			    (match_operand:SI 2 "const_int_operand" "n")))]
-  "GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])"
-  "*
-{
-  unsigned int mask;
-
-  mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]);
-  operands[1] = GEN_INT (mask);
-
-  if (! REG_P (operands[0]) || QI_REG_P (operands[0]))
-    {
-      if ((mask & ~0xff) == 0)
-        {
-	  cc_status.flags |= CC_NOT_NEGATIVE;
-	  return AS2 (test%B0,%1,%b0);
-	}
-
-      if ((mask & ~0xff00) == 0)
-        {
-	  cc_status.flags |= CC_NOT_NEGATIVE;
-	  operands[1] = GEN_INT (mask >> 8);
-
-	  if (QI_REG_P (operands[0]))
-	    return AS2 (test%B0,%1,%h0);
-	  else
-	    {
-	      operands[0] = adj_offsettable_operand (operands[0], 1);
-	      return AS2 (test%B0,%1,%b0);
-	    }
-	}
-
-      if (GET_CODE (operands[0]) == MEM && (mask & ~0xff0000) == 0)
-        {
-	  cc_status.flags |= CC_NOT_NEGATIVE;
-	  operands[1] = GEN_INT (mask >> 16);
-	  operands[0] = adj_offsettable_operand (operands[0], 2);
-	  return AS2 (test%B0,%1,%b0);
-	}
-
-      if (GET_CODE (operands[0]) == MEM && (mask & ~0xff000000) == 0)
-        {
-	  cc_status.flags |= CC_NOT_NEGATIVE;
-	  operands[1] = GEN_INT (mask >> 24);
-	  operands[0] = adj_offsettable_operand (operands[0], 3);
-	  return AS2 (test%B0,%1,%b0);
-	}
-    }
-
-  if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
-    return AS2 (test%L0,%1,%0);
-
-  return AS2 (test%L1,%0,%1);
-}")
-
-;; Store-flag instructions.
-
-;; For all sCOND expanders, also expand the compare or test insn that
-;; generates cc0.  Generate an equality comparison if `seq' or `sne'.
-
-(define_expand "seq"
-  [(match_dup 1)
-   (set (match_operand:QI 0 "register_operand" "")
-	(eq:QI (cc0) (const_int 0)))]
-  ""
-  "
-{
-  if (TARGET_IEEE_FP
-      && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
-    operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
-  else
-    operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
-}")
-
-(define_expand "sne"
-  [(match_dup 1)
-   (set (match_operand:QI 0 "register_operand" "")
-	(ne:QI (cc0) (const_int 0)))]
-  ""
-  "
-{
-  if (TARGET_IEEE_FP
-      && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
-    operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
-  else
-    operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
-}")
-
-(define_expand "sgt"
-  [(match_dup 1)
-   (set (match_operand:QI 0 "register_operand" "")
-	(gt:QI (cc0) (const_int 0)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "sgtu"
-  [(match_dup 1)
-   (set (match_operand:QI 0 "register_operand" "")
-	(gtu:QI (cc0) (const_int 0)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "slt"
-  [(match_dup 1)
-   (set (match_operand:QI 0 "register_operand" "")
-	(lt:QI (cc0) (const_int 0)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "sltu"
-  [(match_dup 1)
-   (set (match_operand:QI 0 "register_operand" "")
-	(ltu:QI (cc0) (const_int 0)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "sge"
-  [(match_dup 1)
-   (set (match_operand:QI 0 "register_operand" "")
-	(ge:QI (cc0) (const_int 0)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "sgeu"
-  [(match_dup 1)
-   (set (match_operand:QI 0 "register_operand" "")
-	(geu:QI (cc0) (const_int 0)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "sle"
-  [(match_dup 1)
-   (set (match_operand:QI 0 "register_operand" "")
-	(le:QI (cc0) (const_int 0)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "sleu"
-  [(match_dup 1)
-   (set (match_operand:QI 0 "register_operand" "")
-	(leu:QI (cc0) (const_int 0)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-;; The 386 sCOND opcodes can write to memory.  But a gcc sCOND insn may
-;; not have any input reloads.  A MEM write might need an input reload
-;; for the address of the MEM.  So don't allow MEM as the SET_DEST.
-
-(define_insn "*setcc"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
-	(match_operator:QI 1 "comparison_operator" [(cc0) (const_int 0)]))]
-  "reload_completed || register_operand (operands[0], QImode)"
-  "*
-{
-  enum rtx_code code = GET_CODE (operands[1]);
-  if (cc_prev_status.flags & CC_TEST_AX)
-    {
-      int eq;
-      HOST_WIDE_INT c;
-      operands[2] = gen_rtx_REG (SImode, 0);
-      switch (code)
-	{
-	case EQ:
-	  c = 0x4000;
-	  eq = 0;
-	  break;
-	case NE:
-	  c = 0x4000;
-	  eq = 1;
-	  break;
-	case GT:
-	  c = 0x4100;
-	  eq = 1;
-	  break;
-	case LT:
-	  c = 0x100;
-	  eq = 0;
-	  break;
-	case GE:
-	  c = 0x100;
-	  eq = 1;
-	  break;
-	case LE:
-	  c = 0x4100;
-	  eq = 0;
-	  break;
-	default:
-	  abort ();
-	}
-      operands[3] = GEN_INT (c);
-      output_asm_insn (AS2 (testl,%3,%2), operands);
-      return eq ? AS1 (sete,%0) : AS1 (setne, %0);
-    }
-
-  if ((cc_status.flags & CC_NO_OVERFLOW) && (code == LE || code == GT))
-    return (char *)0;
-  return AS1(set%D1,%0);
-}")
-
-
-;; Basic conditional jump instructions.
-;; We ignore the overflow flag for signed branch instructions.
-
-;; For all bCOND expanders, also expand the compare or test insn that
-;; generates cc0.  Generate an equality comparison if `beq' or `bne'.
-
-(define_expand "beq"
-  [(match_dup 1)
-   (set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (TARGET_IEEE_FP
-      && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
-    operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
-  else
-    operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
-}")
-
-(define_expand "bne"
-  [(match_dup 1)
-   (set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (TARGET_IEEE_FP
-      && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
-    operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
-  else
-    operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
-}")
-
-
-(define_expand "bgt"
-  [(match_dup 1)
-   (set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "bgtu"
-  [(match_dup 1)
-   (set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "blt"
-  [(match_dup 1)
-   (set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-
-(define_expand "bltu"
-  [(match_dup 1)
-   (set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "bge"
-  [(match_dup 1)
-   (set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "bgeu"
-  [(match_dup 1)
-   (set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "ble"
-  [(match_dup 1)
-   (set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_expand "bleu"
-  [(match_dup 1)
-   (set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  enum rtx_code code = GET_CODE (operands[0]);
-  if (cc_prev_status.flags & CC_TEST_AX)
-    {
-      int eq;
-      HOST_WIDE_INT c;
-      operands[2] = gen_rtx_REG (SImode, 0);
-      switch (code)
-	{
-	case EQ:
-	  c = 0x4000;
-	  eq = 0;
-	  break;
-	case NE:
-	  c = 0x4000;
-	  eq = 1;
-	  break;
-	case GT:
-	  c = 0x4100;
-	  eq = 1;
-	  break;
-	case LT:
-	  c = 0x100;
-	  eq = 0;
-	  break;
-	case GE:
-	  c = 0x100;
-	  eq = 1;
-	  break;
-	case LE:
-	  c = 0x4100;
-	  eq = 0;
-	  break;
-	default:
-	  abort ();
-	}
-      operands[3] = GEN_INT (c);
-      output_asm_insn (AS2 (testl,%3,%2), operands);
-      return eq ? AS1 (je,%l1) : AS1 (jne, %l1);
-    }
-  if ((cc_status.flags & CC_NO_OVERFLOW) && (code == LE || code == GT))
-    return (char *)0;
-
-  return AS1(j%D0,%l1);
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 1 "" ""))))]
-  ""
-  "*
-{
-  enum rtx_code code = GET_CODE (operands[0]);
-  if (cc_prev_status.flags & CC_TEST_AX)
-    {
-      int eq;
-      HOST_WIDE_INT c;
-      operands[2] = gen_rtx_REG (SImode, 0);
-      switch (code)
-	{
-	case EQ:
-	  c = 0x4000;
-	  eq = 1;
-	  break;
-	case NE:
-	  c = 0x4000;
-	  eq = 0;
-	  break;
-	case GT:
-	  c = 0x4100;
-	  eq = 0;
-	  break;
-	case LT:
-	  c = 0x100;
-	  eq = 1;
-	  break;
-	case GE:
-	  c = 0x100;
-	  eq = 0;
-	  break;
-	case LE:
-	  c = 0x4100;
-	  eq = 1;
-	  break;
-	default:
-	  abort ();
-	}
-      operands[3] = GEN_INT (c);
-      output_asm_insn (AS2 (testl,%3,%2), operands);
-      return eq ? AS1 (je,%l1) : AS1 (jne, %l1);
-    }
-  if ((cc_status.flags & CC_NO_OVERFLOW) && (code == LE || code == GT))
-    return (char *)0;
-
-  return AS1(j%d0,%l1);
-}")
-
-;; Unconditional and other jump instructions
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "jmp %l0"
-  [(set_attr "memory" "none")])
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-
-  return AS1 (jmp,%*%0);
-}"
-  [(set_attr "memory" "none")])
-
-;; ??? could transform while(--i > 0) S; to if (--i > 0) do S; while(--i);
-;;     if S does not change i
-
-(define_expand "decrement_and_branch_until_zero"
-  [(parallel [(set (pc)
-		   (if_then_else (ge (plus:SI (match_operand:SI 0 "general_operand" "")
-					      (const_int -1))
-				     (const_int 0))
-				 (label_ref (match_operand 1 "" ""))
-				 (pc)))
-	      (set (match_dup 0)
-		   (plus:SI (match_dup 0)
-			    (const_int -1)))])]
-  ""
-  "")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "arithmetic_comparison_operator"
-				      [(plus:SI (match_operand:SI 1 "nonimmediate_operand" "+c*r,m")
-						(match_operand:SI 2 "general_operand" "rmi,ri"))
-				       (const_int 0)])
-		      (label_ref (match_operand 3 "" ""))
-		      (pc)))
-   (set (match_dup 1)
-	(plus:SI (match_dup 1)
-		 (match_dup 2)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-
-  if (GET_CODE (operands[1]) == REG && REGNO (operands[2]) == 2 &&
-      operands[2] == constm1_rtx && ix86_cpu == PROCESSOR_K6)
-    return \"loop %l3\";
-
-  if (operands[2] == constm1_rtx)
-    output_asm_insn (AS1 (dec%L1,%1), operands);
-
-  else if (operands[2] == const1_rtx)
-    output_asm_insn (AS1 (inc%L1,%1), operands);
-
-  else
-    output_asm_insn (AS2 (add%L1,%2,%1), operands);
-
-  return AS1 (%J0,%l3);
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "arithmetic_comparison_operator"
-				      [(minus:SI (match_operand:SI 1 "nonimmediate_operand" "+r,m")
-						 (match_operand:SI 2 "general_operand" "rmi,ri"))
-				       (const_int 0)])
-		      (label_ref (match_operand 3 "" ""))
-		      (pc)))
-   (set (match_dup 1)
-	(minus:SI (match_dup 1)
-		  (match_dup 2)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (operands[2] == const1_rtx)
-    output_asm_insn (AS1 (dec%L1,%1), operands);
-
-  else if (operands[1] == constm1_rtx)
-    output_asm_insn (AS1 (inc%L1,%1), operands);
-
-  else
-    output_asm_insn (AS2 (sub%L1,%2,%1), operands);
-
-  return AS1 (%J0,%l3);
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (match_operand:SI 0 "general_operand" "+g")
-			  (const_int 0))
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  operands[2] = const1_rtx;
-  output_asm_insn (AS2 (sub%L0,%2,%0), operands);
-  return \"jnc %l1\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (match_operand:SI 0 "general_operand" "+g")
-			  (const_int 0))
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  operands[2] = const1_rtx;
-  output_asm_insn (AS2 (sub%L0,%2,%0), operands);
-  return \"jc %l1\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (match_operand:SI 0 "general_operand" "+g")
-			  (const_int 1))
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  output_asm_insn (AS1 (dec%L0,%0), operands);
-  return \"jnz %l1\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (match_operand:SI 0 "general_operand" "+g")
-			  (const_int 1))
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  output_asm_insn (AS1 (dec%L0,%0), operands);
-  return \"jz %l1\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (match_operand:SI 0 "general_operand" "+g")
-			  (const_int -1))
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int 1)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  output_asm_insn (AS1 (inc%L0,%0), operands);
-  return \"jnz %l1\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (match_operand:SI 0 "general_operand" "+g")
-			  (const_int -1))
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int 1)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  output_asm_insn (AS1 (inc%L0,%0), operands);
-  return \"jz %l1\";
-}")
-
-;; Implement switch statements when generating PIC code.  Switches are
-;; implemented by `tablejump' when not using -fpic.
-
-;; Emit code here to do the range checking and make the index zero based.
-
-(define_expand "casesi"
-  [(set (match_dup 5)
-	(match_operand:SI 0 "general_operand" ""))
-   (set (match_dup 6)
-	(minus:SI (match_dup 5)
-		  (match_operand:SI 1 "general_operand" "")))
-   (set (cc0)
-	(compare:CC (match_dup 6)
-		    (match_operand:SI 2 "general_operand" "")))
-   (set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 4 "" ""))
-		      (pc)))
-   (parallel
-    [(set (pc)
-	  (minus:SI (reg:SI 3)
-		    (mem:SI (plus:SI (mult:SI (match_dup 6)
-					      (const_int 4))
-				     (label_ref (match_operand 3 "" ""))))))
-     (clobber (match_scratch:SI 7 ""))])]
-  "flag_pic"
-  "
-{
-  operands[5] = gen_reg_rtx (SImode);
-  operands[6] = gen_reg_rtx (SImode);
-  current_function_uses_pic_offset_table = 1;
-}")
-
-;; Implement a casesi insn.
-
-;; Each entry in the "addr_diff_vec" looks like this as the result of the
-;; two rules below:
-;; 
-;; 	.long _GLOBAL_OFFSET_TABLE_+[.-.L2]
-;; 
-;; 1. An expression involving an external reference may only use the
-;;    addition operator, and only with an assembly-time constant.
-;;    The example above satisfies this because ".-.L2" is a constant.
-;; 
-;; 2. The symbol _GLOBAL_OFFSET_TABLE_ is magic, and at link time is
-;;    given the value of "GOT - .", where GOT is the actual address of
-;;    the Global Offset Table.  Therefore, the .long above actually
-;;    stores the value "( GOT - . ) + [ . - .L2 ]", or "GOT - .L2".  The
-;;    expression "GOT - .L2" by itself would generate an error from as(1).
-;; 
-;; The pattern below emits code that looks like this:
-;; 
-;; 	movl %ebx,reg
-;; 	subl TABLE@GOTOFF(%ebx,index,4),reg
-;; 	jmp reg
-;; 
-;; The addr_diff_vec contents may be directly referenced with @GOTOFF, since
-;; the addr_diff_vec is known to be part of this module.
-;; 
-;; The subl above calculates "GOT - (( GOT - . ) + [ . - .L2 ])", which
-;; evaluates to just ".L2".
-
-(define_insn ""
-  [(set (pc)
-	(minus:SI (reg:SI 3)
-		  (mem:SI (plus:SI
-			   (mult:SI (match_operand:SI 0 "register_operand" "r")
-				    (const_int 4))
-			   (label_ref (match_operand 1 "" ""))))))
-   (clobber (match_scratch:SI 2 "=&r"))]
-  ""
-  "*
-{
-  rtx xops[4];
-
-  xops[0] = operands[0];
-  xops[1] = operands[1];
-  xops[2] = operands[2];
-  xops[3] = pic_offset_table_rtx;
-
-  output_asm_insn (AS2 (mov%L2,%3,%2), xops);
-  output_asm_insn (\"sub%L2 %l1@GOTOFF(%3,%0,4),%2\", xops);
-  output_asm_insn (AS1 (jmp,%*%2), xops);
-  ASM_OUTPUT_ALIGN (asm_out_file, i386_align_jumps);
-  RET;
-}")
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-
-  return AS1 (jmp,%*%0);
-}")
-
-;; Call insns.
-
-;; If generating PIC code, the predicate indirect_operand will fail
-;; for operands[0] containing symbolic references on all of the named
-;; call* patterns.  Each named pattern is followed by an unnamed pattern
-;; that matches any call to a symbolic CONST (ie, a symbol_ref).  The
-;; unnamed patterns are only used while generating PIC code, because
-;; otherwise the named patterns match.
-
-;; Call subroutine returning no value.
-
-(define_expand "call_pop"
-  [(parallel [(call (match_operand:QI 0 "indirect_operand" "")
-		    (match_operand:SI 1 "general_operand" ""))
-	      (set (reg:SI 7)
-		   (plus:SI (reg:SI 7)
-			    (match_operand:SI 3 "immediate_operand" "")))])]
-  ""
-  "
-{
-  rtx addr;
-
-  if (operands[3] == const0_rtx)
-    {
-      emit_insn (gen_call (operands[0], operands[1]));
-      DONE;
-    }
-
-  if (flag_pic)
-    current_function_uses_pic_offset_table = 1;
-
-  /* With half-pic, force the address into a register.  */
-  addr = XEXP (operands[0], 0);
-  if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
-    XEXP (operands[0], 0) = force_reg (Pmode, addr);
-
-  if (! expander_call_insn_operand (operands[0], QImode))
-    operands[0]
-      = change_address (operands[0], VOIDmode,
-			copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
-}")
-
-(define_insn ""
-  [(call (match_operand:QI 0 "call_insn_operand" "m")
-	 (match_operand:SI 1 "general_operand" "g"))
-   (set (reg:SI 7) (plus:SI (reg:SI 7)
-			    (match_operand:SI 3 "immediate_operand" "i")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM
-      && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-    {
-      operands[0] = XEXP (operands[0], 0);
-      return AS1 (call,%*%0);
-    }
-  else
-    return AS1 (call,%P0);
-}")
-
-(define_insn ""
-  [(call (mem:QI (match_operand:SI 0 "symbolic_operand" ""))
-	 (match_operand:SI 1 "general_operand" "g"))
-   (set (reg:SI 7) (plus:SI (reg:SI 7)
-			    (match_operand:SI 3 "immediate_operand" "i")))]
-  "!HALF_PIC_P ()"
-  "call %P0")
-
-(define_expand "call"
-  [(call (match_operand:QI 0 "indirect_operand" "")
-	 (match_operand:SI 1 "general_operand" ""))]
-  ;; Operand 1 not used on the i386.
-  ""
-  "
-{
-  rtx addr;
-
-  if (flag_pic)
-    current_function_uses_pic_offset_table = 1;
-
-  /* With half-pic, force the address into a register.  */
-  addr = XEXP (operands[0], 0);
-  if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
-    XEXP (operands[0], 0) = force_reg (Pmode, addr);
-
-  if (! expander_call_insn_operand (operands[0], QImode))
-    operands[0]
-      = change_address (operands[0], VOIDmode,
-			copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
-}")
-
-(define_insn ""
-  [(call (match_operand:QI 0 "call_insn_operand" "m")
-	 (match_operand:SI 1 "general_operand" "g"))]
-  ;; Operand 1 not used on the i386.
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM
-      && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-    {
-      operands[0] = XEXP (operands[0], 0);
-      return AS1 (call,%*%0);
-    }
-  else
-    return AS1 (call,%P0);
-}")
-
-(define_insn ""
-  [(call (mem:QI (match_operand:SI 0 "symbolic_operand" ""))
-	 (match_operand:SI 1 "general_operand" "g"))]
-  ;; Operand 1 not used on the i386.
-  "!HALF_PIC_P ()"
-  "call %P0")
-
-;; Call subroutine, returning value in operand 0
-;; (which must be a hard register).
-
-(define_expand "call_value_pop"
-  [(parallel [(set (match_operand 0 "" "")
-		   (call (match_operand:QI 1 "indirect_operand" "")
-			 (match_operand:SI 2 "general_operand" "")))
-	      (set (reg:SI 7)
-		   (plus:SI (reg:SI 7)
-			    (match_operand:SI 4 "immediate_operand" "")))])]
-  ""
-  "
-{
-  rtx addr;
-
-  if (operands[4] == const0_rtx)
-    {
-      emit_insn (gen_call_value (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-
-  if (flag_pic)
-    current_function_uses_pic_offset_table = 1;
-
-  /* With half-pic, force the address into a register.  */
-  addr = XEXP (operands[1], 0);
-  if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
-    XEXP (operands[1], 0) = force_reg (Pmode, addr);
-
-  if (! expander_call_insn_operand (operands[1], QImode))
-    operands[1]
-      = change_address (operands[1], VOIDmode,
-			copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
-}")
-
-(define_insn ""
-  [(set (match_operand 0 "" "=rf")
-	(call (match_operand:QI 1 "call_insn_operand" "m")
-	      (match_operand:SI 2 "general_operand" "g")))
-   (set (reg:SI 7) (plus:SI (reg:SI 7)
-			    (match_operand:SI 4 "immediate_operand" "i")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == MEM
-      && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-    {
-      operands[1] = XEXP (operands[1], 0);
-      output_asm_insn (AS1 (call,%*%1), operands);
-    }
-  else
-    output_asm_insn (AS1 (call,%P1), operands);
-
-  RET;
-}")
-
-(define_insn ""
-  [(set (match_operand 0 "" "=rf")
-	(call (mem:QI (match_operand:SI 1 "symbolic_operand" ""))
-	      (match_operand:SI 2 "general_operand" "g")))
-   (set (reg:SI 7) (plus:SI (reg:SI 7)
-			    (match_operand:SI 4 "immediate_operand" "i")))]
-  "!HALF_PIC_P ()"
-  "call %P1")
-
-(define_expand "call_value"
-  [(set (match_operand 0 "" "")
-	(call (match_operand:QI 1 "indirect_operand" "")
-	      (match_operand:SI 2 "general_operand" "")))]
-  ;; Operand 2 not used on the i386.
-  ""
-  "
-{
-  rtx addr;
-
-  if (flag_pic)
-    current_function_uses_pic_offset_table = 1;
-
-  /* With half-pic, force the address into a register.  */
-  addr = XEXP (operands[1], 0);
-  if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
-    XEXP (operands[1], 0) = force_reg (Pmode, addr);
-
-  if (! expander_call_insn_operand (operands[1], QImode))
-    operands[1]
-      = change_address (operands[1], VOIDmode,
-			copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
-}")
-
-(define_insn ""
-  [(set (match_operand 0 "" "=rf")
-	(call (match_operand:QI 1 "call_insn_operand" "m")
-	      (match_operand:SI 2 "general_operand" "g")))]
-  ;; Operand 2 not used on the i386.
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == MEM
-      && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-    {
-      operands[1] = XEXP (operands[1], 0);
-      output_asm_insn (AS1 (call,%*%1), operands);
-    }
-  else
-    output_asm_insn (AS1 (call,%P1), operands);
-
-  RET;
-}")
-
-(define_insn ""
-  [(set (match_operand 0 "" "=rf")
-	(call (mem:QI (match_operand:SI 1 "symbolic_operand" ""))
-	      (match_operand:SI 2 "general_operand" "g")))]
-  ;; Operand 2 not used on the i386.
-  "!HALF_PIC_P ()"
-  "call %P1")
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  /* In order to give reg-stack an easier job in validating two
-     coprocessor registers as containing a possible return value,
-     simply pretend the untyped call returns a complex long double
-     value.  */
-
-  emit_call_insn (TARGET_80387
-                  ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
-				    operands[0], const0_rtx)
-                  : gen_call (operands[0], const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  ""
-  [(set_attr "memory" "none")])
-
-;; Insn emitted into the body of a function to return from a function.
-;; This is only done if the function's epilogue is known to be simple.
-;; See comments for simple_386_epilogue in i386.c.
-
-(define_expand "return"
-  [(return)]
-  "ix86_can_use_return_insn_p ()"
-  "")
-
-(define_insn "return_internal"
-  [(return)]
-  "reload_completed"
-  "ret"
-  [(set_attr "memory" "none")])
-
-(define_insn "return_pop_internal"
-  [(return)
-   (use (match_operand:SI 0 "const_int_operand" ""))]
-  "reload_completed"
-  "ret %0"
-  [(set_attr "memory" "none")])
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-  [(set_attr "memory" "none")])
-
-(define_expand "prologue"
-  [(const_int 1)]
-  ""
-  "
-{
-  ix86_expand_prologue ();
-  DONE;
-}")
-
-;; The use of UNSPEC here is currently not necessary - a simple SET of ebp
-;; to itself would be enough. But this way we are safe even if some optimizer
-;; becomes too clever in the future.
-(define_insn "prologue_set_stack_ptr"
-  [(set (reg:SI 7)
-	(minus:SI (reg:SI 7) (match_operand:SI 0 "immediate_operand" "i")))
-   (set (reg:SI 6) (unspec:SI [(reg:SI 6)] 4))]
-  ""
-  "*
-{
-  rtx xops [2];
-
-  xops[0] = operands[0];
-  xops[1] = stack_pointer_rtx;
-  output_asm_insn (AS2 (sub%L1,%0,%1), xops);
-  RET;
-}"
-  [(set_attr "memory" "none")])
-
-(define_insn "prologue_set_got"
-  [(set (match_operand:SI 0 "" "")
-	(unspec_volatile
-	 [(plus:SI (match_dup 0)
-		   (plus:SI (match_operand:SI 1 "symbolic_operand" "")
-			    (minus:SI (pc) (match_operand 2 "" ""))))] 1))]
-  ""
-  "*
-{
-  char buffer[64];
-
-  if (TARGET_DEEP_BRANCH_PREDICTION) 
-    {
-      sprintf (buffer, \"addl %s,%%0\", XSTR (operands[1], 0));
-      output_asm_insn (buffer, operands);
-    }
-  else  
-    {
-      sprintf (buffer, \"addl %s+[.-%%X2],%%0\", XSTR (operands[1], 0));
-      output_asm_insn (buffer, operands);
-    }    
-  RET;
-}")
-
-(define_insn "prologue_get_pc"
-  [(set (match_operand:SI 0 "" "")
-    (unspec_volatile [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
-  ""
-  "*
-{
-  output_asm_insn (AS1 (call,%X1), operands);
-  if (! TARGET_DEEP_BRANCH_PREDICTION) 
-    {
-      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (operands[1]));
-    }    
-  RET;
-}"
-  [(set_attr "memory" "none")])
-
-(define_insn "prologue_get_pc_and_set_got"
-  [(unspec_volatile [(match_operand:SI 0 "" "")] 3)]
-  ""
-  "*
-{
-  operands[1] = gen_label_rtx ();
-  output_asm_insn (AS1 (call,%X1), operands);
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
-			     CODE_LABEL_NUMBER (operands[1]));
-  output_asm_insn (AS1 (pop%L0,%0), operands);
-  output_asm_insn (\"addl $_GLOBAL_OFFSET_TABLE_+[.-%X1],%0\", operands);
-  RET;
-}"
-  [(set_attr "memory" "none")])
-
-(define_expand "epilogue"
-  [(const_int 1)]
-  ""
-  "
-{
-  ix86_expand_epilogue ();
-  DONE;
-}")
-
-(define_insn "epilogue_set_stack_ptr"
-  [(set (reg:SI 7) (reg:SI 6))
-	(clobber (reg:SI 6))]
-  ""
-  "*
-{
-  rtx xops [2];
-
-    xops[0] = frame_pointer_rtx;
-    xops[1] = stack_pointer_rtx;
-    output_asm_insn (AS2 (mov%L0,%0,%1), xops);
-    RET;
-}"
-  [(set_attr "memory" "none")])
-
-(define_insn "leave"
-  [(const_int 2)
-      (clobber (reg:SI 6))
-      (clobber (reg:SI 7))]
-  ""
-  "leave"
-  [(set_attr "memory" "none")])
-
-(define_insn "pop"
-  [(set (match_operand:SI 0 "register_operand" "r")
-	(mem:SI (reg:SI 7)))
-   (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))]
-  ""
-  "*
-{
-    output_asm_insn (AS1 (pop%L0,%P0), operands);
-    RET;
-}"
-  [(set_attr "memory" "load")])
-
-(define_expand "movstrsi"
-  [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
-		   (match_operand:BLK 1 "memory_operand" ""))
-	      (use (match_operand:SI 2 "const_int_operand" ""))
-	      (use (match_operand:SI 3 "const_int_operand" ""))
-	      (clobber (match_scratch:SI 4 ""))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))])]
-  ""
-  "
-{
-  rtx addr0, addr1;
-
-  if (GET_CODE (operands[2]) != CONST_INT)
-    FAIL;
-
-  addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
-  addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
-
-  operands[5] = addr0;
-  operands[6] = addr1;
-
-  operands[0] = change_address (operands[0], VOIDmode, addr0);
-  operands[1] = change_address (operands[1], VOIDmode, addr1);
-}")
-
-;; It might seem that operands 0 & 1 could use predicate register_operand.
-;; But strength reduction might offset the MEM expression.  So we let
-;; reload put the address into %edi & %esi.
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "address_operand" "D"))
-	(mem:BLK (match_operand:SI 1 "address_operand" "S")))
-   (use (match_operand:SI 2 "const_int_operand" "n"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_scratch:SI 4 "=&c"))
-   (clobber (match_dup 0))
-   (clobber (match_dup 1))]
-  ""
-  "*
-{
-  rtx xops[2];
-
-  output_asm_insn (\"cld\", operands);
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) & ~0x03)
-	{
-	  xops[0] = GEN_INT ((INTVAL (operands[2]) >> 2) & 0x3fffffff);
-	  xops[1] = operands[4];
-
-	  output_asm_insn (AS2 (mov%L1,%0,%1), xops);
-#ifdef INTEL_SYNTAX
-	  output_asm_insn (\"rep movsd\", xops);
-#else
-	  output_asm_insn (\"rep\;movsl\", xops);
-#endif
-	}
-      if (INTVAL (operands[2]) & 0x02)
-	output_asm_insn (\"movsw\", operands);
-      if (INTVAL (operands[2]) & 0x01)
-	output_asm_insn (\"movsb\", operands);
-    }
-  else
-    abort ();
-  RET;
-}")
-
-(define_expand "clrstrsi"
-  [(set (match_dup 3) (const_int 0))
-   (parallel [(set (match_operand:BLK 0 "memory_operand" "")
-		   (const_int 0))
-	      (use (match_operand:SI 1 "const_int_operand" ""))
-	      (use (match_operand:SI 2 "const_int_operand" ""))
-	      (use (match_dup 3))
-	      (clobber (match_scratch:SI 4 ""))
-	      (clobber (match_dup 5))])]
-  ""
-  "
-{
-  rtx addr0;
-
-  if (GET_CODE (operands[1]) != CONST_INT)
-    FAIL;
-
-  addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
-
-  operands[3] = gen_reg_rtx (SImode);
-  operands[5] = addr0;
-
-  operands[0] = gen_rtx_MEM (BLKmode, addr0);
-}")
-
-;; It might seem that operand 0 could use predicate register_operand.
-;; But strength reduction might offset the MEM expression.  So we let
-;; reload put the address into %edi.
-
-(define_insn "*bzero"
-  [(set (mem:BLK (match_operand:SI 0 "address_operand" "D"))
-	(const_int 0))
-   (use (match_operand:SI 1 "const_int_operand" "n"))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "register_operand" "a"))
-   (clobber (match_scratch:SI 4 "=&c"))
-   (clobber (match_dup 0))]
-  ""
-  "*
-{
-  rtx xops[2];
-
-  output_asm_insn (\"cld\", operands);
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      unsigned int count = INTVAL (operands[1]) & 0xffffffff;
-      if (count & ~0x03)
-	{
-	  xops[0] = GEN_INT (count / 4);
-	  xops[1] = operands[4];
-
-	  /* K6: stos takes 1 cycle, rep stos takes 8 + %ecx cycles.
-	     80386: 4/5+5n (+2 for set of ecx)
-	     80486: 5/7+5n (+1 for set of ecx)
-	     */
-	  if (count / 4 < ((int) ix86_cpu < (int)PROCESSOR_PENTIUM ? 4 : 6))
-	    {
-	      do
-#ifdef INTEL_SYNTAX
-		output_asm_insn (\"stosd\", xops);
-#else
-		output_asm_insn (\"stosl\", xops);
-#endif
-	      while ((count -= 4) > 3);
-	    }
-	  else
-	    {
-	      output_asm_insn (AS2 (mov%L1,%0,%1), xops);
-#ifdef INTEL_SYNTAX
-	      output_asm_insn (\"rep stosd\", xops);
-#else
-	      output_asm_insn (\"rep\;stosl\", xops);
-#endif
-	    }
-	}
-      if (INTVAL (operands[1]) & 0x02)
-	output_asm_insn (\"stosw\", operands);
-      if (INTVAL (operands[1]) & 0x01)
-	output_asm_insn (\"stosb\", operands);
-    }
-  else
-    abort ();
-  RET;
-}")
-
-(define_expand "cmpstrsi"
-  [(parallel [(set (match_operand:SI 0 "general_operand" "")
-		   (compare:SI (match_operand:BLK 1 "general_operand" "")
-			       (match_operand:BLK 2 "general_operand" "")))
-	      (use (match_operand:SI 3 "general_operand" ""))
-	      (use (match_operand:SI 4 "immediate_operand" ""))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))
-	      (clobber (match_dup 3))])]
-  ""
-  "
-{
-  rtx addr1, addr2;
-
-  addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
-  addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
-  operands[3] = copy_to_mode_reg (SImode, operands[3]);
-
-  operands[5] = addr1;
-  operands[6] = addr2;
-
-  operands[1] = gen_rtx_MEM (BLKmode, addr1);
-  operands[2] = gen_rtx_MEM (BLKmode, addr2);
-
-}")
-
-;; memcmp recognizers.  The `cmpsb' opcode does nothing if the count is
-;; zero.  Emit extra code to make sure that a zero-length compare is EQ.
-
-;; It might seem that operands 0 & 1 could use predicate register_operand.
-;; But strength reduction might offset the MEM expression.  So we let
-;; reload put the address into %edi & %esi.
-
-;; ??? Most comparisons have a constant length, and it's therefore
-;; possible to know that the length is non-zero, and to avoid the extra
-;; code to handle zero-length compares.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(compare:SI (mem:BLK (match_operand:SI 1 "address_operand" "S"))
-		    (mem:BLK (match_operand:SI 2 "address_operand" "D"))))
-   (use (match_operand:SI 3 "register_operand" "c"))
-   (use (match_operand:SI 4 "immediate_operand" "i"))
-   (clobber (match_dup 1))
-   (clobber (match_dup 2))
-   (clobber (match_dup 3))]
-  ""
-  "*
-{
-  rtx xops[2], label;
-
-  label = gen_label_rtx ();
-
-  output_asm_insn (\"cld\", operands);
-  output_asm_insn (AS2 (xor%L0,%0,%0), operands);
-  output_asm_insn (\"repz\;cmps%B2\", operands);
-  output_asm_insn (\"je %l0\", &label);
-
-  xops[0] = operands[0];
-  xops[1] = const1_rtx;
-  output_asm_insn (AS2 (sbb%L0,%0,%0), xops);
-  if (QI_REG_P (xops[0]))
-     output_asm_insn (AS2 (or%B0,%1,%b0), xops);
-  else
-     output_asm_insn (AS2 (or%L0,%1,%0), xops);
-	
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (label));
-  RET;
-}")
-
-(define_insn ""
-  [(set (cc0)
-	(compare:SI (mem:BLK (match_operand:SI 0 "address_operand" "S"))
-		    (mem:BLK (match_operand:SI 1 "address_operand" "D"))))
-   (use (match_operand:SI 2 "register_operand" "c"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_dup 0))
-   (clobber (match_dup 1))
-   (clobber (match_dup 2))]
-  ""
-  "*
-{
-  rtx xops[2];
-
-  cc_status.flags |= CC_NOT_SIGNED;
-
-  xops[0] = gen_rtx_REG (QImode, 0);
-  xops[1] = CONST0_RTX (QImode);
-
-  output_asm_insn (\"cld\", operands);
-  output_asm_insn (AS2 (test%B0,%1,%0), xops);
-  return \"repz\;cmps%B2\";
-}")
-
-
-;; Note, you cannot optimize away the branch following the bsfl by assuming
-;; that the destination is not modified if the input is 0, since not all
-;; x86 implementations do this.
-
-(define_expand "ffssi2"
-  [(set (match_operand:SI 0 "general_operand" "") 
-	(ffs:SI (match_operand:SI 1 "general_operand" "")))]
-  ""
-  "
-{
-  rtx label = gen_label_rtx (), temp = gen_reg_rtx (SImode);
-
-  emit_insn (gen_ffssi_1 (temp, operands[1]));
-  emit_cmp_insn (operands[1], const0_rtx, NE, NULL_RTX, SImode, 0, 0);
-  emit_jump_insn (gen_bne (label));
-  emit_move_insn (temp, constm1_rtx);
-  emit_label (label);
-  temp = expand_binop (SImode, add_optab, temp, const1_rtx,
-		       operands[0], 0, OPTAB_WIDEN);
-
-  if (temp != operands[0])
-    emit_move_insn (operands[0], temp);
-  DONE;  
-}")
-
-(define_insn "ffssi_1"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(unspec:SI [(match_operand:SI 1 "nonimmediate_operand" "rm")] 5))]
-  ""
-  "* return AS2 (bsf%L0,%1,%0);")
-
-(define_expand "ffshi2"
-  [(set (match_operand:SI 0 "general_operand" "") 
-	(ffs:HI (match_operand:HI 1 "general_operand" "")))]
-  ""
-  "
-{
-  rtx label = gen_label_rtx (), temp = gen_reg_rtx (HImode);
-
-  emit_insn (gen_ffshi_1 (temp, operands[1]));
-  emit_cmp_insn (operands[1], const0_rtx, NE, NULL_RTX, HImode, 0, 0);
-  emit_jump_insn (gen_bne (label));
-  emit_move_insn (temp, constm1_rtx);
-  emit_label (label);
-  temp = expand_binop (HImode, add_optab, temp, const1_rtx,
-		       operands[0], 0, OPTAB_WIDEN);
-
-  if (temp != operands[0])
-    emit_move_insn (operands[0], temp);
-  DONE;  
-}")
-
-(define_insn "ffshi_1"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(unspec:HI [(match_operand:SI 1 "nonimmediate_operand" "rm")] 5))]
-  ""
-  "* return AS2 (bsf%W0,%1,%0);")
-
-;; These patterns match the binary 387 instructions for addM3, subM3,
-;; mulM3 and divM3.  There are three patterns for each of DFmode and
-;; SFmode.  The first is the normal insn, the second the same insn but
-;; with one operand a conversion, and the third the same insn but with
-;; the other operand a conversion.  The conversion may be SFmode or
-;; SImode if the target mode DFmode, but only SImode if the target mode
-;; is SFmode.
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(match_operator:DF 3 "binary_387_op"
-			[(match_operand:DF 1 "nonimmediate_operand" "0,fm")
-			 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(match_operator:DF 3 "binary_387_op"
-	   [(float:DF (match_operand:SI 1 "nonimmediate_operand" "rm"))
-	    (match_operand:DF 2 "register_operand" "0")]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f,f")
-	(match_operator:XF 3 "binary_387_op"
-			[(match_operand:XF 1 "register_operand" "0,f")
-			 (match_operand:XF 2 "register_operand" "f,0")]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(match_operator:XF 3 "binary_387_op"
-	   [(float:XF (match_operand:SI 1 "nonimmediate_operand" "rm"))
-	    (match_operand:XF 2 "register_operand" "0")]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f,f")
-	(match_operator:XF 3 "binary_387_op"
-	   [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
-	    (match_operand:XF 2 "register_operand" "0,f")]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(match_operator:XF 3 "binary_387_op"
-	  [(match_operand:XF 1 "register_operand" "0")
-	   (float:XF (match_operand:SI 2 "nonimmediate_operand" "rm"))]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f,f")
-	(match_operator:XF 3 "binary_387_op"
-	  [(match_operand:XF 1 "register_operand" "0,f")
-	   (float_extend:XF
-	    (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(match_operator:DF 3 "binary_387_op"
-	   [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
-	    (match_operand:DF 2 "register_operand" "0,f")]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(match_operator:DF 3 "binary_387_op"
-	  [(match_operand:DF 1 "register_operand" "0")
-	   (float:DF (match_operand:SI 2 "nonimmediate_operand" "rm"))]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(match_operator:DF 3 "binary_387_op"
-	  [(match_operand:DF 1 "register_operand" "0,f")
-	   (float_extend:DF
-	    (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-	(match_operator:SF 3 "binary_387_op"
-			[(match_operand:SF 1 "nonimmediate_operand" "0,fm")
-			 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(match_operator:SF 3 "binary_387_op"
-	  [(float:SF (match_operand:SI 1 "nonimmediate_operand" "rm"))
-	   (match_operand:SF 2 "register_operand" "0")]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(match_operator:SF 3 "binary_387_op"
-	  [(match_operand:SF 1 "register_operand" "0")
-	   (float:SF (match_operand:SI 2 "nonimmediate_operand" "rm"))]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "is_mul" "") 
-                 (const_string "fpmul")
-               (match_operand:DF 3 "is_div" "") 
-                 (const_string "fpdiv")
-              ]
-               (const_string "fpop")
-        )
-  )])
-
-(define_expand "strlensi"
-  [(parallel [(set (match_dup 4)
-		   (unspec:SI [(mem:BLK (match_operand:BLK 1 "general_operand" ""))
-			       (match_operand:QI 2 "immediate_operand" "")
-			       (match_operand:SI 3 "immediate_operand" "")] 0))
-	      (clobber (match_dup 1))])
-   (set (match_dup 5)
-	(not:SI (match_dup 4)))
-   (set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_dup 5)
-	         (const_int -1)))]
-  ""
-  "
-{
-  if (TARGET_UNROLL_STRLEN && operands[2] == const0_rtx && optimize > 1)
-    {
-      rtx address;
-      rtx scratch;
-
-	/* well it seems that some optimizer does not combine a call like
-	     foo(strlen(bar), strlen(bar));
-	   when the move and the subtraction is done here.  It does calculate
-	   the length just once when these instructions are done inside of
-	   output_strlen_unroll().  But I think since &bar[strlen(bar)] is
-	   often used and I use one fewer register for the lifetime of
-	   output_strlen_unroll() this is better.  */
-      scratch = gen_reg_rtx (SImode);
-      address = force_reg (SImode, XEXP (operands[1], 0));
-
-	/* move address to scratch-register
-	   this is done here because the i586 can do the following and
-	   in the same cycle with the following move.  */
-      if (GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) < 4)
-	  emit_insn (gen_movsi (scratch, address));
-
-      emit_insn (gen_movsi (operands[0], address));
-
-      if(TARGET_USE_Q_REG)
-	emit_insn (gen_strlensi_unroll5 (operands[0],
-					operands[3],
-					scratch,
-					operands[0]));
-      else
-	emit_insn (gen_strlensi_unroll4 (operands[0],
-					operands[3],
-					scratch,
-					operands[0]));
-
-        /* gen_strlensi_unroll[45] returns the address of the zero
-           at the end of the string, like memchr(), so compute the
-           length by subtracting the startaddress.  */
-      emit_insn (gen_subsi3 (operands[0], operands[0], address));
-      DONE;
-    }
-
-  operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
-  operands[4] = gen_reg_rtx (SImode);
-  operands[5] = gen_reg_rtx (SImode);
-}")
-
-;; It might seem that operands 0 & 1 could use predicate register_operand.
-;; But strength reduction might offset the MEM expression.  So we let
-;; reload put the address into %edi.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&c")
-	(unspec:SI [(mem:BLK (match_operand:SI 1 "address_operand" "D"))
-		    (match_operand:QI 2 "immediate_operand" "a")
-		    (match_operand:SI 3 "immediate_operand" "i")] 0))
-   (clobber (match_dup 1))]
-  ""
-  "*
-{
-  rtx xops[2];
-
-  xops[0] = operands[0];
-  xops[1] = constm1_rtx;
-  output_asm_insn (\"cld\", operands);
-  output_asm_insn (AS2 (mov%L0,%1,%0), xops);
-  return \"repnz\;scas%B2\";
-}")
-
-/* Conditional move define_insns.  */
-
-(define_expand "movsicc"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(if_then_else:SI (match_operand 1 "comparison_operator" "")
-			 (match_operand:SI 2 "nonimmediate_operand" "")
-			 (match_operand:SI 3 "nonimmediate_operand" "")))]
-  "TARGET_CMOVE"
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (i386_compare_op0)) != MODE_INT)
-    FAIL;
-
-  operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
-			GET_MODE (i386_compare_op0),
-			i386_compare_op0, i386_compare_op1);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,&r,&r")
-	(if_then_else:SI (match_operator 1 "comparison_operator" 
-	      [(match_operand:QI 2 "nonimmediate_operand" "q,m,q,m,q,m")
-		(match_operand:QI 3 "general_operand" "qmn,qn,qmn,qn,qmn,qn")])
-	      (match_operand:SI 4 "nonimmediate_operand" "rm,rm,0,0,rm,rm")
-	      (match_operand:SI 5 "nonimmediate_operand" "0,0,rm,rm,rm,rm")))]
-  "TARGET_CMOVE"
-  "#")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,&r,&r")
-	(if_then_else:SI (match_operator 1 "comparison_operator" 
-	      [(match_operand 2 "nonimmediate_operand" "r,m,r,m,r,m")
-		(match_operand 3 "general_operand" "rmi,ri,rmi,ri,rmi,ri")])
-	      (match_operand:SI 4 "nonimmediate_operand" "rm,rm,0,0,rm,rm")
-	      (match_operand:SI 5 "nonimmediate_operand" "0,0,rm,rm,rm,rm")))]
-  "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT"
-  "#")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
-	(if_then_else:SI (match_operator 1 "comparison_operator" 
-				[(match_operand 2 "nonimmediate_operand" "")
-				 (const_int 0)])
-		      (match_operand:SI 3 "nonimmediate_operand" "rm,0,rm")
-		      (match_operand:SI 4 "nonimmediate_operand" "0,rm,rm")))]
-  "TARGET_CMOVE && reload_completed"
-  [(set (cc0)
-	(match_dup 2))
-   (set (match_dup 0)
-	(if_then_else:SI (match_op_dup 1 [(cc0) (const_int 0)])
-		      (match_dup 3) (match_dup 4)))]
-  "")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
-	(if_then_else:SI (match_operator 1 "comparison_operator" 
-				[(match_operand 2 "nonimmediate_operand" "")
-				 (match_operand 3 "general_operand" "")])
-		      (match_operand:SI 4 "nonimmediate_operand" "rm,0,rm")
-		      (match_operand:SI 5 "nonimmediate_operand" "0,rm,rm")))]
-  "TARGET_CMOVE && reload_completed"
-  [(set (cc0) (compare (match_dup 2) (match_dup 3)))
-   (set (match_dup 0)
-	(if_then_else:SI (match_op_dup 1 [(cc0) (const_int 0)])
-		      (match_dup 4) (match_dup 5)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
-	(if_then_else:SI (match_operator 1 "comparison_operator" 
-				[(cc0) (const_int 0)])
-		      (match_operand:SI 2 "nonimmediate_operand" "rm,0,rm")
-		      (match_operand:SI 3 "nonimmediate_operand" "0,rm,rm")))]
-  "TARGET_CMOVE && reload_completed"
-  "* return output_int_conditional_move (which_alternative, operands);")
-
-(define_expand "movhicc"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(if_then_else:HI (match_operand 1 "comparison_operator" "")
-			 (match_operand:HI 2 "nonimmediate_operand" "")
-			 (match_operand:HI 3 "nonimmediate_operand" "")))]
-  "TARGET_CMOVE"
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (i386_compare_op0)) != MODE_INT)
-    FAIL;
-
-  operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
-			GET_MODE (i386_compare_op0),
-			i386_compare_op0, i386_compare_op1);
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,&r,&r")
-	(if_then_else:HI (match_operator 1 "comparison_operator" 
-	      [(match_operand:QI 2 "nonimmediate_operand" "q,m,q,m,q,m")
-		(match_operand:QI 3 "general_operand" "qmn,qn,qmn,qn,qmn,qn")])
-	      (match_operand:HI 4 "nonimmediate_operand" "rm,rm,0,0,rm,rm")
-	      (match_operand:HI 5 "nonimmediate_operand" "0,0,rm,rm,rm,rm")))]
-  "TARGET_CMOVE"
-  "#")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,&r,&r")
-	(if_then_else:HI (match_operator 1 "comparison_operator" 
-	      [(match_operand 2 "nonimmediate_operand" "r,m,r,m,r,m")
-		(match_operand 3 "general_operand" "rmi,ri,rmi,ri,rmi,ri")])
-	      (match_operand:HI 4 "nonimmediate_operand" "rm,rm,0,0,rm,rm")
-	      (match_operand:HI 5 "nonimmediate_operand" "0,0,rm,rm,rm,rm")))]
-  "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT"
-  "#")
-
-(define_split
-  [(set (match_operand:HI 0 "register_operand" "=r,r,&r")
-	(if_then_else:HI (match_operator 1 "comparison_operator" 
-				[(match_operand 2 "nonimmediate_operand" "")
-				 (const_int 0)])
-		      (match_operand:HI 3 "nonimmediate_operand" "rm,0,rm")
-		      (match_operand:HI 4 "nonimmediate_operand" "0,rm,rm")))]
-  "TARGET_CMOVE && reload_completed"
-  [(set (cc0)
-	(match_dup 2))
-   (set (match_dup 0)
-	(if_then_else:HI (match_op_dup 1 [(cc0) (const_int 0)])
-		      (match_dup 3) (match_dup 4)))]
-  "")
-
-(define_split
-  [(set (match_operand:HI 0 "register_operand" "=r,r,&r")
-	(if_then_else:HI (match_operator 1 "comparison_operator" 
-				[(match_operand 2 "nonimmediate_operand" "")
-				 (match_operand 3 "general_operand" "")])
-		      (match_operand:HI 4 "nonimmediate_operand" "rm,0,rm")
-		      (match_operand:HI 5 "nonimmediate_operand" "0,rm,rm")))]
-  "TARGET_CMOVE && reload_completed"
-  [(set (cc0)
-	(compare (match_dup 2) (match_dup 3)))
-   (set (match_dup 0)
-	(if_then_else:HI (match_op_dup 1 [(cc0) (const_int 0)])
-		      (match_dup 4) (match_dup 5)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r,&r")
-	(if_then_else:HI (match_operator 1 "comparison_operator" 
-				[(cc0) (const_int 0)])
-		      (match_operand:HI 2 "nonimmediate_operand" "rm,0,rm")
-		      (match_operand:HI 3 "nonimmediate_operand" "0,rm,rm")))]
-  "TARGET_CMOVE && reload_completed"
-  "* return output_int_conditional_move (which_alternative, operands);")
-
-(define_expand "movsfcc"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(if_then_else:SF (match_operand 1 "comparison_operator" "")
-			 (match_operand:SF 2 "register_operand" "")
-			 (match_operand:SF 3 "register_operand" "")))]
-  "TARGET_CMOVE"
-  "
-{
-  rtx temp;
-
-  if (GET_MODE_CLASS (GET_MODE (i386_compare_op0)) != MODE_INT)
-    FAIL;
-
-  /* The floating point conditional move instructions don't directly
-     support conditions resulting from a signed integer comparison. */
-
-  switch (GET_CODE (operands[1]))
-    {
-    case LT:
-    case LE:
-    case GE:
-    case GT:
-      temp = emit_store_flag (gen_reg_rtx (QImode),
-		GET_CODE (operands[1]), i386_compare_op0, i386_compare_op1,
-		VOIDmode, 0, 0);
-
-      if (!temp)
-        FAIL;
-
-      operands[1] = gen_rtx_fmt_ee (NE, QImode, temp, const0_rtx);
-      break;
-
-    default:
-      operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
-			GET_MODE (i386_compare_op0),
-			i386_compare_op0, i386_compare_op1);
-      break;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f,f,f,f,f,f")
-	(if_then_else:SF (match_operator 1 "comparison_operator" 
-	      [(match_operand:QI 2 "nonimmediate_operand" "q,m,q,m,q,m")
-		(match_operand:QI 3 "general_operand" "qmn,qn,qmn,qn,qmn,qn")])
-	      (match_operand:SF 4 "register_operand" "f,f,0,0,f,f")
-	      (match_operand:SF 5 "register_operand" "0,0,f,f,f,f")))]
-  "TARGET_CMOVE
-    && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE
-    && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT"
-  "#")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f,f,f,f,f,f")
-	(if_then_else:SF (match_operator 1 "comparison_operator" 
-		[(match_operand 2 "nonimmediate_operand" "r,m,r,m,r,m")
-		 (match_operand 3 "general_operand" "rmi,ri,rmi,ri,rmi,ri")])
-	      (match_operand:SF 4 "register_operand" "f,f,0,0,f,f")
-	      (match_operand:SF 5 "register_operand" "0,0,f,f,f,f")))]
-  "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT
-    && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE
-    && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT"
-  "#")
-
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "=f,f,f")
-	(if_then_else:SF (match_operator 1 "comparison_operator" 
-				[(match_operand 2 "nonimmediate_operand" "")
-				 (const_int 0)])
-		      (match_operand:SF 3 "register_operand" "f,0,f")
-		      (match_operand:SF 4 "register_operand" "0,f,f")))]
-  "TARGET_CMOVE && reload_completed"
-  [(set (cc0)
-	(match_dup 2))
-   (set (match_dup 0)
-	(if_then_else:SF (match_op_dup 1 [(cc0) (const_int 0)])
-		      (match_dup 3) (match_dup 4)))]
-  "")
-
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "=f,f,f")
-	(if_then_else:SF (match_operator 1 "comparison_operator" 
-				[(match_operand 2 "nonimmediate_operand" "")
-				 (match_operand 3 "general_operand" "")])
-		      (match_operand:SF 4 "register_operand" "f,0,f")
-		      (match_operand:SF 5 "register_operand" "0,f,f")))]
-  "TARGET_CMOVE && reload_completed"
-  [(set (cc0) (compare (match_dup 2) (match_dup 3)))
-   (set (match_dup 0)
-	(if_then_else:SF (match_op_dup 1 [(cc0) (const_int 0)])
-		      (match_dup 4) (match_dup 5)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f,f,f")
-	(if_then_else:SF (match_operator 1 "comparison_operator" 
-				[(cc0) (const_int 0)])
-		      (match_operand:SF 2 "register_operand" "f,0,f")
-		      (match_operand:SF 3 "register_operand" "0,f,f")))]
-  "TARGET_CMOVE && reload_completed"
-  "* return output_fp_conditional_move (which_alternative, operands);")
-
-(define_expand "movdfcc"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(if_then_else:DF (match_operand 1 "comparison_operator" "")
-			 (match_operand:DF 2 "register_operand" "")
-			 (match_operand:DF 3 "register_operand" "")))]
-  "TARGET_CMOVE"
-  "
-{
-  rtx temp;
-
-  if (GET_MODE_CLASS (GET_MODE (i386_compare_op0)) != MODE_INT)
-    FAIL;
-
-  /* The floating point conditional move instructions don't directly
-     support conditions resulting from a signed integer comparison. */
-
-  switch (GET_CODE (operands[1]))
-    {
-    case LT:
-    case LE:
-    case GE:
-    case GT:
-      temp = emit_store_flag (gen_reg_rtx (QImode),
-		GET_CODE (operands[1]), i386_compare_op0, i386_compare_op1,
-		VOIDmode, 0, 0);
-
-      if (!temp)
-        FAIL;
-
-      operands[1] = gen_rtx_fmt_ee (NE, QImode, temp, const0_rtx);
-      break;
-
-    default:
-      operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
-			GET_MODE (i386_compare_op0),
-			i386_compare_op0, i386_compare_op1);
-      break;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f,f,f,f,f")
-	(if_then_else:DF (match_operator 1 "comparison_operator" 
-	      [(match_operand:QI 2 "nonimmediate_operand" "q,m,q,m,q,m")
-		(match_operand:QI 3 "general_operand" "qmn,qn,qmn,qn,qmn,qn")])
-	      (match_operand:DF 4 "register_operand" "f,f,0,0,f,f")
-	      (match_operand:DF 5 "register_operand" "0,0,f,f,f,f")))]
-  "TARGET_CMOVE
-    && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE
-    && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT"
-  "#")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f,f,f,f,f")
-	(if_then_else:DF (match_operator 1 "comparison_operator" 
-	      [(match_operand 2 "nonimmediate_operand" "r,m,r,m,r,m")
-		(match_operand 3 "general_operand" "rmi,ri,rmi,ri,rmi,ri")])
-	      (match_operand:DF 4 "register_operand" "f,f,0,0,f,f")
-	      (match_operand:DF 5 "register_operand" "0,0,f,f,f,f")))]
-  "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT
-    && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE
-    && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT"
-  "#")
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
-	(if_then_else:DF (match_operator 1 "comparison_operator" 
-				[(match_operand 2 "nonimmediate_operand" "")
-				 (const_int 0)])
-		      (match_operand:DF 3 "register_operand" "f,0,f")
-		      (match_operand:DF 4 "register_operand" "0,f,f")))]
-  "TARGET_CMOVE && reload_completed"
-  [(set (cc0)
-	(match_dup 2))
-   (set (match_dup 0)
-	(if_then_else:DF (match_op_dup 1 [(cc0) (const_int 0)])
-		      (match_dup 3) (match_dup 4)))]
-  "")
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
-	(if_then_else:DF (match_operator 1 "comparison_operator" 
-				[(match_operand 2 "nonimmediate_operand" "")
-				 (match_operand 3 "general_operand" "")])
-		      (match_operand:DF 4 "register_operand" "f,0,f")
-		      (match_operand:DF 5 "register_operand" "0,f,f")))]
-  "TARGET_CMOVE && reload_completed"
-  [(set (cc0) (compare (match_dup 2) (match_dup 3)))
-   (set (match_dup 0)
-	(if_then_else:DF (match_op_dup 1 [(cc0) (const_int 0)])
-		      (match_dup 4) (match_dup 5)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
-	(if_then_else:DF (match_operator 1 "comparison_operator" 
-				[(cc0) (const_int 0)])
-		      (match_operand:DF 2 "register_operand" "f,0,f")
-		      (match_operand:DF 3 "register_operand" "0,f,f")))]
-  "TARGET_CMOVE && reload_completed"
-  "* return output_fp_conditional_move (which_alternative, operands);")
-
-(define_expand "movxfcc"
-  [(set (match_operand:XF 0 "register_operand" "")
-	(if_then_else:XF (match_operand 1 "comparison_operator" "")
-			 (match_operand:XF 2 "register_operand" "")
-			 (match_operand:XF 3 "register_operand" "")))]
-  "TARGET_CMOVE"
-  "
-{
-  rtx temp;
-
-  if (GET_MODE_CLASS (GET_MODE (i386_compare_op0)) != MODE_INT)
-    FAIL;
-
-  /* The floating point conditional move instructions don't directly
-     support conditions resulting from a signed integer comparison. */
-
-  switch (GET_CODE (operands[1]))
-    {
-    case LT:
-    case LE:
-    case GE:
-    case GT:
-      temp = emit_store_flag (gen_reg_rtx (QImode),
-		GET_CODE (operands[1]), i386_compare_op0, i386_compare_op1,
-		VOIDmode, 0, 0);
-
-      if (!temp)
-        FAIL;
-
-      operands[1] = gen_rtx_fmt_ee (NE, QImode, temp, const0_rtx);
-      break;
-
-    default:
-      operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
-			GET_MODE (i386_compare_op0),
-			i386_compare_op0, i386_compare_op1);
-      break;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f,f,f,f,f,f")
-	(if_then_else:XF (match_operator 1 "comparison_operator" 
-	      [(match_operand:QI 2 "nonimmediate_operand" "q,m,q,m,q,m")
-		(match_operand:QI 3 "general_operand" "qmn,qn,qmn,qn,qmn,qn")])
-	      (match_operand:XF 4 "register_operand" "f,f,0,0,f,f")
-	      (match_operand:XF 5 "register_operand" "0,0,f,f,f,f")))]
-  "TARGET_CMOVE
-    && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE
-    && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT"
-  "#")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f,f,f,f,f,f")
-	(if_then_else:XF (match_operator 1 "comparison_operator" 
-	      [(match_operand 2 "nonimmediate_operand" "r,m,r,m,r,m")
-		(match_operand 3 "general_operand" "rmi,ri,rmi,ri,rmi,ri")])
-	      (match_operand:XF 4 "register_operand" "f,f,0,0,f,f")
-	      (match_operand:XF 5 "register_operand" "0,0,f,f,f,f")))]
-  "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT
-    && GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != LE
-    && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != GT"
-  "#")
-
-(define_split
-  [(set (match_operand:XF 0 "register_operand" "=f,f,f")
-	(if_then_else:XF (match_operator 1 "comparison_operator" 
-				[(match_operand 2 "nonimmediate_operand" "")
-				 (const_int 0)])
-		      (match_operand:XF 3 "register_operand" "f,0,f")
-		      (match_operand:XF 4 "register_operand" "0,f,f")))]
-  "TARGET_CMOVE && reload_completed"
-  [(set (cc0)
-	(match_dup 2))
-   (set (match_dup 0)
-	(if_then_else:XF (match_op_dup 1 [(cc0) (const_int 0)])
-		      (match_dup 3) (match_dup 4)))]
-  "")
-
-(define_split
-  [(set (match_operand:XF 0 "register_operand" "=f,f,f")
-	(if_then_else:XF (match_operator 1 "comparison_operator" 
-				[(match_operand 2 "nonimmediate_operand" "")
-				 (match_operand 3 "general_operand" "")])
-		      (match_operand:XF 4 "register_operand" "f,0,f")
-		      (match_operand:XF 5 "register_operand" "0,f,f")))]
-  "TARGET_CMOVE && reload_completed"
-  [(set (cc0) (compare (match_dup 2) (match_dup 3)))
-   (set (match_dup 0)
-	(if_then_else:XF (match_op_dup 1 [(cc0) (const_int 0)])
-		      (match_dup 4) (match_dup 5)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "register_operand" "=f,f,f")
-	(if_then_else:XF (match_operator 1 "comparison_operator" 
-				[(cc0) (const_int 0)])
-		      (match_operand:XF 2 "register_operand" "f,0,f")
-		      (match_operand:XF 3 "register_operand" "0,f,f")))]
-  "TARGET_CMOVE && reload_completed"
-  "* return output_fp_conditional_move (which_alternative, operands);")
-
-(define_expand "movdicc"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI (match_operand 1 "comparison_operator" "")
-			 (match_operand:DI 2 "nonimmediate_operand" "")
-			 (match_operand:DI 3 "nonimmediate_operand" "")))]
-  "TARGET_CMOVE"
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (i386_compare_op0)) != MODE_INT)
-    FAIL;
-
-  operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
-			GET_MODE (i386_compare_op0),
-			i386_compare_op0, i386_compare_op1);
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=&r,&r,&r,&r,&r,&r")
-	(if_then_else:DI (match_operator 1 "comparison_operator" 
-	      [(match_operand:QI 2 "nonimmediate_operand" "q,m,q,m,q,m")
-		(match_operand:QI 3 "general_operand" "qmn,qn,qmn,qn,qmn,qn")])
-	      (match_operand:DI 4 "nonimmediate_operand" "ro,ro,0,0,ro,ro")
-	      (match_operand:DI 5 "nonimmediate_operand" "0,0,ro,ro,ro,ro")))]
-  "TARGET_CMOVE"
-  "#")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=&r,&r,&r,&r,&r,&r")
-	(if_then_else:DI (match_operator 1 "comparison_operator" 
-	      [(match_operand 2 "nonimmediate_operand" "r,m,r,m,r,m")
-		(match_operand 3 "general_operand" "rmi,ri,rmi,ri,rmi,ri")])
-	      (match_operand:DI 4 "nonimmediate_operand" "ro,ro,0,0,ro,ro")
-	      (match_operand:DI 5 "nonimmediate_operand" "0,0,ro,ro,ro,ro")))]
-  "TARGET_CMOVE && GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT"
-  "#")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "=&r,&r,&r")
-	(if_then_else:DI (match_operator 1 "comparison_operator" 
-				[(match_operand 2 "nonimmediate_operand" "")
-				 (const_int 0)])
-		      (match_operand:DI 3 "nonimmediate_operand" "ro,0,ro")
-		      (match_operand:DI 4 "nonimmediate_operand" "0,ro,ro")))]
-  "TARGET_CMOVE && reload_completed"
-  [(set (cc0)
-	(match_dup 2))
-   (set (match_dup 0)
-	(if_then_else:DI (match_op_dup 1 [(cc0) (const_int 0)])
-		      (match_dup 3) (match_dup 4)))]
-  "")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "=&r,&r,&r")
-	(if_then_else:DI (match_operator 1 "comparison_operator" 
-				[(match_operand 2 "nonimmediate_operand" "")
-				 (match_operand 3 "general_operand" "")])
-		      (match_operand:DI 4 "nonimmediate_operand" "ro,0,ro")
-		      (match_operand:DI 5 "nonimmediate_operand" "0,ro,ro")))]
-  "TARGET_CMOVE && reload_completed"
-  [(set (cc0) (compare (match_dup 2) (match_dup 3)))
-   (set (match_dup 0)
-	(if_then_else:DI (match_op_dup 1 [(cc0) (const_int 0)])
-		      (match_dup 4) (match_dup 5)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=&r,&r,&r")
-	(if_then_else:DI (match_operator 1 "comparison_operator" 
-				[(cc0) (const_int 0)])
-		      (match_operand:DI 2 "nonimmediate_operand" "ro,0,ro")
-		      (match_operand:DI 3 "nonimmediate_operand" "0,ro,ro")))]
-  "TARGET_CMOVE && reload_completed"
-  "* return output_int_conditional_move (which_alternative, operands);")
-
-(define_insn "strlensi_unroll"
-  [(set (match_operand:SI 0 "register_operand" "=&r,&r")
-	(unspec:SI [(mem:BLK (match_operand:SI 1 "address_operand" "r,r"))
-		    (match_operand:SI 2 "immediate_operand" "i,i")] 0))
-   (clobber (match_scratch:SI 3 "=&q,&r"))]
-  "optimize > 1"
-  "* return output_strlen_unroll (operands);")
-
-;; the only difference between the following patterns is the register preference
-;; on a pentium using a q-register saves one clock cycle per 4 characters
-
-(define_insn "strlensi_unroll4"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-		   (unspec:SI [(mem:BLK (match_operand:SI 3 "register_operand" "0,0"))
-			       (match_operand:SI 1 "immediate_operand" "i,i")
-			       (match_operand:SI 2 "register_operand" "+q,!r")] 0))
-   (clobber (match_dup 2))]
-  "(TARGET_USE_ANY_REG && optimize > 1)"
-  "* return output_strlen_unroll (operands);")
-
-(define_insn "strlensi_unroll5"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-		   (unspec:SI [(mem:BLK (match_operand:SI 3 "register_operand" "0"))
-			       (match_operand:SI 1 "immediate_operand" "i")
-			       (match_operand:SI 2 "register_operand" "+q")] 0))
-   (clobber (match_dup 2))]
-  "(TARGET_USE_Q_REG && optimize > 1)"
-  "* return output_strlen_unroll (operands);"
-)
-
-(define_insn "allocate_stack_worker"
-  [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
-   (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
-   (clobber (match_dup 0))]
-  "TARGET_STACK_PROBE"
-  "* return AS1(call,__alloca);"
-  [(set_attr "memory" "none")])
-
-(define_expand "allocate_stack"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-  	(minus:SI (reg:SI 7) (match_operand:SI 1 "general_operand" "")))
-   (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 1)))]
-   "TARGET_STACK_PROBE"
-  "
-{
-#ifdef CHECK_STACK_LIMIT
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
-    emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
-			   operands[1]));
-  else 
-#endif
-    emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
-							    operands[1])));
-
-  emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
-  DONE;
-}")
-
-(define_expand "exception_receiver"
-  [(const_int 0)]
-  "flag_pic"
-  "
-{
-  load_pic_register (1);
-  DONE;
-}")
diff --git a/gcc/config/i386/i386elf.h b/gcc/config/i386/i386elf.h
deleted file mode 100755
index 8cedb2a..0000000
--- a/gcc/config/i386/i386elf.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/* CYGNUS LOCAL (entire file) i386-elf */
-/* Target definitions for GNU compiler for Intel 80386 using ELF
-   Copyright (C) 1988, 1991, 1995 Free Software Foundation, Inc.
-
-   Derived from sysv4.h written by Ron Guilmette (rfg@netcom.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-/* Use stabs instead of DWARF debug format.  */
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#include "i386/i386.h"
-#include "i386/att.h"
-#include "elfos.h"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i386 bare ELF target)");
-
-/* By default, target has a 80387, uses IEEE compatible arithmetic,
-   and returns float values in the 387, ie,
-   (TARGET_80387 | TARGET_IEEE_FP | TARGET_FLOAT_RETURNS_IN_80387) */
-
-#define TARGET_DEFAULT 0301
-
-/* The svr4 ABI for the i386 says that records and unions are returned
-   in memory.  */
-
-#undef RETURN_IN_MEMORY
-#define RETURN_IN_MEMORY(TYPE) \
-  (TYPE_MODE (TYPE) == BLKmode)
-
-/* Define which macros to predefine.  __svr4__ is our extension.  */
-/* This used to define X86, but james@bigtex.cactus.org says that
-   is supposed to be defined optionally by user programs--not by default.  */
-#define CPP_PREDEFINES \
-  "-Di386 -Acpu(i386) -Amachine(i386)"
-
-/* This is how to output assembly code to define a `float' constant.
-   We always have to use a .long pseudo-op to do this because the native
-   SVR4 ELF assembler is buggy and it generates incorrect values when we
-   try to use the .float pseudo-op instead.  */
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
-do { long value;							\
-     REAL_VALUE_TO_TARGET_SINGLE ((VALUE), value);			\
-     if (sizeof (int) == sizeof (long))					\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value);		\
-     else								\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value);		\
-   } while (0)
-
-/* This is how to output assembly code to define a `double' constant.
-   We always have to use a pair of .long pseudo-ops to do this because
-   the native SVR4 ELF assembler is buggy and it generates incorrect
-   values when we try to use the the .double pseudo-op instead.  */
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
-do { long value[2];							\
-     REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), value);			\
-     if (sizeof (int) == sizeof (long))					\
-       {								\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[0]);		\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[1]);		\
-       }								\
-     else								\
-       {								\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[0]);		\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[1]);		\
-       }								\
-   } while (0)
-
-
-#undef ASM_OUTPUT_LONG_DOUBLE
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE)				\
-do { long value[3];							\
-     REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), value);			\
-     if (sizeof (int) == sizeof (long))					\
-       {								\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[0]);		\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[1]);		\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[2]);		\
-       }								\
-     else								\
-       {								\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[0]);		\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[1]);		\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[2]);		\
-       }								\
-   } while (0)
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)						\
-  do {									\
-	output_file_directive (FILE, main_input_filename);		\
-	fprintf (FILE, "\t.version\t\"01.01\"\n");			\
-  } while (0)
-
-/* Define the register numbers to be used in Dwarf debugging information.
-   The SVR4 reference port C compiler uses the following register numbers
-   in its Dwarf output code:
-
-	0 for %eax (gnu regno = 0)
-	1 for %ecx (gnu regno = 2)
-	2 for %edx (gnu regno = 1)
-	3 for %ebx (gnu regno = 3)
-	4 for %esp (gnu regno = 7)
-	5 for %ebp (gnu regno = 6)
-	6 for %esi (gnu regno = 4)
-	7 for %edi (gnu regno = 5)
-
-   The following three DWARF register numbers are never generated by
-   the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
-   believes these numbers have these meanings.
-
-	8  for %eip    (no gnu equivalent)
-	9  for %eflags (no gnu equivalent)
-	10 for %trapno (no gnu equivalent)
-
-   It is not at all clear how we should number the FP stack registers
-   for the x86 architecture.  If the version of SDB on x86/svr4 were
-   a bit less brain dead with respect to floating-point then we would
-   have a precedent to follow with respect to DWARF register numbers
-   for x86 FP registers, but the SDB on x86/svr4 is so completely
-   broken with respect to FP registers that it is hardly worth thinking
-   of it as something to strive for compatibility with.
-
-   The verison of x86/svr4 SDB I have at the moment does (partially)
-   seem to believe that DWARF register number 11 is associated with
-   the x86 register %st(0), but that's about all.  Higher DWARF
-   register numbers don't seem to be associated with anything in
-   particular, and even for DWARF regno 11, SDB only seems to under-
-   stand that it should say that a variable lives in %st(0) (when
-   asked via an `=' command) if we said it was in DWARF regno 11,
-   but SDB still prints garbage when asked for the value of the
-   variable in question (via a `/' command).
-
-   (Also note that the labels SDB prints for various FP stack regs
-   when doing an `x' command are all wrong.)
-
-   Note that these problems generally don't affect the native SVR4
-   C compiler because it doesn't allow the use of -O with -g and
-   because when it is *not* optimizing, it allocates a memory
-   location for each floating-point variable, and the memory
-   location is what gets described in the DWARF AT_location
-   attribute for the variable in question.
-
-   Regardless of the severe mental illness of the x86/svr4 SDB, we
-   do something sensible here and we use the following DWARF
-   register numbers.  Note that these are all stack-top-relative
-   numbers.
-
-	11 for %st(0) (gnu regno = 8)
-	12 for %st(1) (gnu regno = 9)
-	13 for %st(2) (gnu regno = 10)
-	14 for %st(3) (gnu regno = 11)
-	15 for %st(4) (gnu regno = 12)
-	16 for %st(5) (gnu regno = 13)
-	17 for %st(6) (gnu regno = 14)
-	18 for %st(7) (gnu regno = 15)
-*/
-
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n) \
-((n) == 0 ? 0 \
- : (n) == 1 ? 2 \
- : (n) == 2 ? 1 \
- : (n) == 3 ? 3 \
- : (n) == 4 ? 6 \
- : (n) == 5 ? 7 \
- : (n) == 6 ? 5 \
- : (n) == 7 ? 4 \
- : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \
- : (-1))
-
-/* The routine used to output sequences of byte values.  We use a special
-   version of this for most svr4 targets because doing so makes the
-   generated assembly code more compact (and thus faster to assemble)
-   as well as more readable.  Note that if we find subparts of the
-   character sequence which end with NUL (and which are shorter than
-   STRING_LIMIT) we output those using ASM_OUTPUT_LIMITED_STRING.  */
-
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH)				\
-  do									\
-    {									\
-      register unsigned char *_ascii_bytes = (unsigned char *) (STR);	\
-      register unsigned char *limit = _ascii_bytes + (LENGTH);		\
-      register unsigned bytes_in_chunk = 0;				\
-      for (; _ascii_bytes < limit; _ascii_bytes++)			\
-        {								\
-	  register unsigned char *p;					\
-	  if (bytes_in_chunk >= 64)					\
-	    {								\
-	      fputc ('\n', (FILE));					\
-	      bytes_in_chunk = 0;					\
-	    }								\
-	  for (p = _ascii_bytes; p < limit && *p != '\0'; p++)		\
-	    continue;							\
-	  if (p < limit && (p - _ascii_bytes) <= STRING_LIMIT)		\
-	    {								\
-	      if (bytes_in_chunk > 0)					\
-		{							\
-		  fputc ('\n', (FILE));					\
-		  bytes_in_chunk = 0;					\
-		}							\
-	      ASM_OUTPUT_LIMITED_STRING ((FILE), _ascii_bytes);		\
-	      _ascii_bytes = p;						\
-	    }								\
-	  else								\
-	    {								\
-	      if (bytes_in_chunk == 0)					\
-		fprintf ((FILE), "\t.byte\t");				\
-	      else							\
-		fputc (',', (FILE));					\
-	      fprintf ((FILE), "0x%02x", *_ascii_bytes);		\
-	      bytes_in_chunk += 5;					\
-	    }								\
-	}								\
-      if (bytes_in_chunk > 0)						\
-        fprintf ((FILE), "\n");						\
-    }									\
-  while (0)
-
-/* This is how to output an element of a case-vector that is relative.
-   This is only used for PIC code.  See comments by the `casesi' insn in
-   i386.md for an explanation of the expression this outputs. */
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE)
-
-/* Indicate that jump tables go in the text section.  This is
-   necessary when compiling PIC code.  */
-
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-#define LOCAL_LABEL_PREFIX	"."
-
-/* A C statement to output something to the assembler file to switch to section
-   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
-   NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
-   define this macro in such cases.  */
-
-#undef  ASM_OUTPUT_SECTION_NAME
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
-do {									\
-  if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL)			\
-    fprintf (FILE, ".section\t%s,\"ax\"\n", (NAME));			\
-  else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC))		\
-    fprintf (FILE, ".section\t%s,\"a\"\n", (NAME));			\
-  else									\
-    fprintf (FILE, ".section\t%s,\"aw\"\n", (NAME));			\
-} while (0)
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as
-   uninitialized global data.  If not defined, and neither
-   `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
-   uninitialized global data will be output in the data section if
-   `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
-   used.  */
-#undef BSS_SECTION_ASM_OP
-#define BSS_SECTION_ASM_OP ".section\t.bss"
-
-/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
-   separate, explicit argument.  If you define this macro, it is used
-   in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
-   handling the required alignment of the variable.  The alignment is
-   specified as the number of bits.
-
-   Try to use function `asm_output_aligned_bss' defined in file
-   `varasm.c' when defining this macro. */
-#undef ASM_OUTPUT_ALIGNED_BSS
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
diff --git a/gcc/config/i386/isc.h b/gcc/config/i386/isc.h
deleted file mode 100755
index 6c1c4c7..0000000
--- a/gcc/config/i386/isc.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Assembler-independent definitions for an Intel 386 running
-   Interactive Unix System V. Specifically, this is for recent versions
-   that support POSIX.  */
-
-/* Use crt1.o, not crt0.o, as a startup file, and crtn.o as a closing file. */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{!shlib:%{posix:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\
-   %{Xp:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\
-   %{!posix:%{!Xp:%{pg:mcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}\
-   %{p:-L/lib/libp} %{pg:-L/lib/libp}}}}\
-   %{shlib:%{Xp:crtp1.o%s}%{posix:crtp1.o%s}%{!posix:%{!Xp:crt1.o%s}}}\
-   crtbegin.o%s"
-  
-#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
-
-/* Library spec */
-#undef LIB_SPEC
-#define LIB_SPEC "%{shlib:-lc_s} %{posix:-lcposix} %{Xp:-lcposix} -lc -lg"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) %{posix:-D_POSIX_SOURCE} %{Xp:-D_POSIX_SOURCE}"
-
-/* ISC 2.2 uses `char' for `wchar_t'.  */
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "char"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_UNIT
-
-#if 0
-/* This is apparently not true: ISC versions up to 3.0, at least, use
-   the standard calling sequence in which the called function pops the
-   extra arg.  */
-/* caller has to pop the extra argument passed to functions that return
-   structures. */
-
-#undef RETURN_POPS_ARGS
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE)   \
-  ((FUNDECL) && TREE_CODE (FUNDECL) == IDENTIFIER_NODE ? 0	\
-   : (TARGET_RTD						\
-      && (TYPE_ARG_TYPES (FUNTYPE) == 0				\
-	  || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE)))	\
-	      == void_type_node))) ? (SIZE)			\
-   : 0)
-/* On other 386 systems, the last line looks like this:
-   : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0)  */
-#endif
-
-/* Handle #pragma pack and #pragma weak.  */
-#define HANDLE_SYSV_PRAGMA
-
-/* By default, target has a 80387, uses IEEE compatible arithmetic,
-   and returns float values in the 387, ie,
-   (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387)
-
-   ISC's software emulation of a 387 fails to handle the `fucomp'
-   opcode.  fucomp is only used when generating IEEE compliant code.
-   So don't make TARGET_IEEE_FP default for ISC. */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_80387 | MASK_FLOAT_RETURNS)
-
-/* The ISC 2.0.2 software FPU emulator apparently can't handle
-   80-bit XFmode insns, so don't generate them.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* The ISC assembler does not like a .file directive with a name
-   longer than 14 characters.  Truncating it will not permit
-   debugging to work properly, but at least we won't get an error
-   message.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)				\
-  do {							\
-    int len = strlen (main_input_filename);		\
-    char *na = main_input_filename + len;		\
-    char shorter[15];					\
-    /* NA gets MAIN_INPUT_FILENAME sans directory names.  */\
-    while (na > main_input_filename)			\
-      {							\
-	if (na[-1] == '/')				\
-	  break;					\
-	na--;						\
-      }							\
-    strncpy (shorter, na, 14);				\
-    shorter[14] = 0;					\
-    fprintf (FILE, "\t.file\t");			\
-    output_quoted_string (FILE, shorter);		\
-    fprintf (FILE, "\n");				\
-  } while (0)
-
-/* Work around assembler forward label references generated in exception
-   handling code. */
-#define DWARF2_UNWIND_INFO 0
diff --git a/gcc/config/i386/isccoff.h b/gcc/config/i386/isccoff.h
deleted file mode 100755
index 595c7d9..0000000
--- a/gcc/config/i386/isccoff.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Definitions for Intel 386 running Interactive Unix System V.
-   Specifically, this is for recent versions that support POSIX;
-   for version 2.0.2, use configuration option i386-sysv instead.
-   (But set TARGET_DEFAULT to (MASK_80307 | MASK_FLOAT_RETURNS)
-   if you do that, if you don't have a real 80387.)  */
-
-/* Mostly it's like AT&T Unix System V. */
-
-#include "i386/sysv3.h"
-
-/* But with a few changes.  */
-#include "i386/isc.h"
diff --git a/gcc/config/i386/iscdbx.h b/gcc/config/i386/iscdbx.h
deleted file mode 100755
index 6c2d42e..0000000
--- a/gcc/config/i386/iscdbx.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Definitions for Intel 386 running Interactive Unix System V,
-   using dbx-in-coff encapsulation.
-   Specifically, this is for recent versions that support POSIX.
-   Copyright (C) 1992, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Mostly it's like AT&T Unix System V with dbx-in-coff. */
-
-#include "i386/svr3dbx.h"
-
-/* But with a few changes.  */
-#undef ENDFILE_SPEC
-#include "i386/isc.h"
-
-/* Overridden defines for ifile usage. */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{!r:%{!z:svr3.ifile%s}%{z:svr3z.ifile%s}}\
-   %{!shlib:%{posix:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\
-   %{Xp:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\
-   %{!posix:%{!Xp:%{pg:mcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}\
-   %{p:-L/usr/lib/libp} %{pg:-L/usr/lib/libp}}\
-   %{shlib:%{posix:crtp1.o%s}%{Xp:crtp1.o%s}%{!posix:%{!Xp:crt1.o%s}}}"
-  
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtn.o%s"
diff --git a/gcc/config/i386/linux-aout.h b/gcc/config/i386/linux-aout.h
deleted file mode 100755
index de81d87..0000000
--- a/gcc/config/i386/linux-aout.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Definitions for Intel 386 running Linux-based GNU systems using a.out.
-   Copyright (C) 1992, 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by H.J. Lu (hjl@nynexst.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This is tested by i386/gas.h.  */
-#define YES_UNDERSCORES
-
-#include <i386/gstabs.h>
-#include <linux-aout.h>	/* some common stuff */
-
-#undef ASM_COMMENT_START
-#define ASM_COMMENT_START "#"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dlinux -Asystem(posix)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) %{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}"
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler,
-   and we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-#undef LIB_SPEC
-
-#if 1
-/* We no longer link with libc_p.a or libg.a by default. If you
-   want to profile or debug the GNU/Linux C library, please add
-   -lc_p or -ggdb to LDFLAGS at the link time, respectively.  */
-#define LIB_SPEC \
-"%{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}"
-#else    
-#define LIB_SPEC \
-"%{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \
- %{!p:%{!pg:%{!g*:-lc} %{g*:-lg -static}}}" 
-#endif
-
-
-#undef LINK_SPEC
-#define LINK_SPEC	"-m i386linux"
-
-/* Get perform_* macros to build libgcc.a.  */
-#include "i386/perform.h"
diff --git a/gcc/config/i386/linux-oldld.h b/gcc/config/i386/linux-oldld.h
deleted file mode 100755
index 4e3085b..0000000
--- a/gcc/config/i386/linux-oldld.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* Definitions for Intel 386 running Linux-based GNU systems with pre-BFD
-   a.out linkers.
-   Copyright (C) 1995, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Michael Meissner (meissner@cygnus.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This is tested by i386/gas.h.  */
-#define YES_UNDERSCORES
-
-#include <i386/gstabs.h>
-#include <linux-aout.h>	/* some common stuff */
-
-#undef ASM_COMMENT_START
-#define ASM_COMMENT_START "#"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dlinux -Asystem(posix)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) %{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}"
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler,
-   and we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-#undef LIB_SPEC
-
-#if 1
-/* We no longer link with libc_p.a or libg.a by default. If you
-   want to profile or debug the GNU/Linux C library, please add
-   lc_p or -ggdb to LDFLAGS at the link time, respectively.  */
-#define LIB_SPEC \
-"%{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}"
-#else    
-#define LIB_SPEC \
-"%{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \
- %{!p:%{!pg:%{!g*:-lc} %{g*:-lg -static}}}" 
-#endif
-
-
-#undef LINK_SPEC
-#define LINK_SPEC ""
-
-/* Get perform_* macros to build libgcc.a.  */
-#include <i386/perform.h>
diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h
deleted file mode 100755
index bd2aeb0..0000000
--- a/gcc/config/i386/linux.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/* Definitions for Intel 386 running Linux-based GNU systems with ELF format.
-   Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Eric Youngdale.
-   Modified for stabs-in-ELF by H.J. Lu.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define LINUX_DEFAULT_ELF
-
-/* A lie, I guess, but the general idea behind linux/ELF is that we are
-   supposed to be outputting something that will assemble under SVr4.
-   This gets us pretty close.  */
-#include <i386/i386.h>	/* Base i386 target machine definitions */
-#include <i386/att.h>	/* Use the i386 AT&T assembler syntax */
-#include <linux.h>	/* some common stuff */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i386 Linux/ELF)");
-
-/* The svr4 ABI for the i386 says that records and unions are returned
-   in memory.  */
-#undef DEFAULT_PCC_STRUCT_RETURN
-#define DEFAULT_PCC_STRUCT_RETURN 1
-
-#undef ASM_COMMENT_START
-#define ASM_COMMENT_START "#"
-
-/* This is how to output an element of a case-vector that is relative.
-   This is only used for PIC code.  See comments by the `casesi' insn in
-   i386.md for an explanation of the expression this outputs. */
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE)
-
-/* Indicate that jump tables go in the text section.  This is
-   necessary when compiling PIC code.  */
-#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
-
-/* Copy this from the svr4 specifications... */
-/* Define the register numbers to be used in Dwarf debugging information.
-   The SVR4 reference port C compiler uses the following register numbers
-   in its Dwarf output code:
-	0 for %eax (gnu regno = 0)
-	1 for %ecx (gnu regno = 2)
-	2 for %edx (gnu regno = 1)
-	3 for %ebx (gnu regno = 3)
-	4 for %esp (gnu regno = 7)
-	5 for %ebp (gnu regno = 6)
-	6 for %esi (gnu regno = 4)
-	7 for %edi (gnu regno = 5)
-   The following three DWARF register numbers are never generated by
-   the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
-   believes these numbers have these meanings.
-	8  for %eip    (no gnu equivalent)
-	9  for %eflags (no gnu equivalent)
-	10 for %trapno (no gnu equivalent)
-   It is not at all clear how we should number the FP stack registers
-   for the x86 architecture.  If the version of SDB on x86/svr4 were
-   a bit less brain dead with respect to floating-point then we would
-   have a precedent to follow with respect to DWARF register numbers
-   for x86 FP registers, but the SDB on x86/svr4 is so completely
-   broken with respect to FP registers that it is hardly worth thinking
-   of it as something to strive for compatibility with.
-   The version of x86/svr4 SDB I have at the moment does (partially)
-   seem to believe that DWARF register number 11 is associated with
-   the x86 register %st(0), but that's about all.  Higher DWARF
-   register numbers don't seem to be associated with anything in
-   particular, and even for DWARF regno 11, SDB only seems to under-
-   stand that it should say that a variable lives in %st(0) (when
-   asked via an `=' command) if we said it was in DWARF regno 11,
-   but SDB still prints garbage when asked for the value of the
-   variable in question (via a `/' command).
-   (Also note that the labels SDB prints for various FP stack regs
-   when doing an `x' command are all wrong.)
-   Note that these problems generally don't affect the native SVR4
-   C compiler because it doesn't allow the use of -O with -g and
-   because when it is *not* optimizing, it allocates a memory
-   location for each floating-point variable, and the memory
-   location is what gets described in the DWARF AT_location
-   attribute for the variable in question.
-   Regardless of the severe mental illness of the x86/svr4 SDB, we
-   do something sensible here and we use the following DWARF
-   register numbers.  Note that these are all stack-top-relative
-   numbers.
-	11 for %st(0) (gnu regno = 8)
-	12 for %st(1) (gnu regno = 9)
-	13 for %st(2) (gnu regno = 10)
-	14 for %st(3) (gnu regno = 11)
-	15 for %st(4) (gnu regno = 12)
-	16 for %st(5) (gnu regno = 13)
-	17 for %st(6) (gnu regno = 14)
-	18 for %st(7) (gnu regno = 15)
-*/
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n) \
-((n) == 0 ? 0 \
- : (n) == 1 ? 2 \
- : (n) == 2 ? 1 \
- : (n) == 3 ? 3 \
- : (n) == 4 ? 6 \
- : (n) == 5 ? 7 \
- : (n) == 6 ? 5 \
- : (n) == 7 ? 4 \
- : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \
- : (-1))
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-{									\
-  if (flag_pic)								\
-    {									\
-      fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n",		\
-	       LPREFIX, (LABELNO));					\
-      fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n");			\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO));	\
-      fprintf (FILE, "\tcall mcount\n");				\
-    }									\
-}
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
- 
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-  
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-   
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-    
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D__ELF__ -Dunix -D__i386__ -Dlinux -Asystem(posix)"
-
-#undef CPP_SPEC
-#ifdef USE_GNULIBC_1
-#define CPP_SPEC "%(cpp_cpu) %{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}"
-#else
-#define CPP_SPEC "%(cpp_cpu) %{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
-#endif
-
-#undef CC1_SPEC
-#define CC1_SPEC "%(cc1_cpu) %{profile:-p}"
-
-/* Provide a LINK_SPEC appropriate for Linux.  Here we provide support
-   for the special GCC options -static and -shared, which allow us to
-   link things in one of these three modes by applying the appropriate
-   combinations of options at link-time. We like to support here for
-   as many of the other GNU linker options as possible. But I don't
-   have the time to search for those flags. I am sure how to add
-   support for -soname shared_object_name. H.J.
-
-   I took out %{v:%{!V:-V}}. It is too much :-(. They can use
-   -Wl,-V.
-
-   When the -shared link option is used a final link is not being
-   done.  */
-
-/* If ELF is the default format, we should not use /lib/elf. */
-
-#undef	LINK_SPEC
-#ifdef USE_GNULIBC_1
-#ifndef LINUX_DEFAULT_ELF
-#define LINK_SPEC "-m elf_i386 %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-	%{rdynamic:-export-dynamic} \
-	%{!dynamic-linker:-dynamic-linker /lib/elf/ld-linux.so.1} \
-	%{!rpath:-rpath /lib/elf/}} %{static:-static}}}"
-#else
-#define LINK_SPEC "-m elf_i386 %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-	%{rdynamic:-export-dynamic} \
-	%{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.1}} \
-	%{static:-static}}}"
-#endif
-#else
-#define LINK_SPEC "-m elf_i386 %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-	%{rdynamic:-export-dynamic} \
-	%{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.2}} \
-	%{static:-static}}}"
-#endif
-
-/* Get perform_* macros to build libgcc.a.  */
-#include "i386/perform.h"
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of uninitialized global DECL named
-   NAME whose size is SIZE bytes and alignment is ALIGN bytes.
-   Try to use asm_output_aligned_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
-
-/* A C statement to output to the stdio stream FILE an assembler
-   command to advance the location counter to a multiple of 1<<LOG
-   bytes if it is within MAX_SKIP bytes.
-
-   This is used to align code labels according to Intel recommendations.  */
-
-#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
-#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP)			\
-  do {									\
-    if ((LOG)!=0)							\
-      if ((MAX_SKIP)==0) fprintf ((FILE), "\t.p2align %d\n", (LOG));	\
-      else fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP));	\
-  } while (0)
-#endif
diff --git a/gcc/config/i386/lynx-ng.h b/gcc/config/i386/lynx-ng.h
deleted file mode 100755
index ec4e296..0000000
--- a/gcc/config/i386/lynx-ng.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Definitions for Intel 386 running LynxOS, using Lynx's old as and ld.
-   Copyright (C) 1993, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <i386/gstabs.h>
-#include <lynx-ng.h>
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Di386 -DI386 -DLynx -DIBITS32 -Asystem(unix) -Asystem(lynx) -Acpu(i386) -Amachine(i386)"
-
-/* Provide required defaults for linker switches.  */
-
-#undef LINK_SPEC
-#define LINK_SPEC "-P1000 %{msystem-v:-V} %{mcoff:-k}"
-
-/* Apparently LynxOS clobbers ebx when you call into the OS.  */
-
-#undef CALL_USED_REGISTERS
-#define CALL_USED_REGISTERS \
-/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
-{  1, 1, 1, 1, 0, 0, 0, 1, 1,  1,  1,  1,  1,  1,  1,  1,  1 }
diff --git a/gcc/config/i386/lynx.h b/gcc/config/i386/lynx.h
deleted file mode 100755
index 73111f9..0000000
--- a/gcc/config/i386/lynx.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Definitions for Intel 386 running LynxOS.
-   Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <i386/gstabs.h>
-#include <lynx.h>
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Di386 -DI386 -DLynx -DIBITS32 -Asystem(unix) -Asystem(lynx) -Acpu(i386) -Amachine(i386)"
-
-/* The prefix to add to user-visible assembler symbols. */
-
-/* Override the svr3 convention of adding a leading underscore. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-
-/* Apparently LynxOS clobbers ebx when you call into the OS.  */
-
-#undef CALL_USED_REGISTERS
-#define CALL_USED_REGISTERS \
-/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
-{  1, 1, 1, 1, 0, 0, 0, 1, 1,  1,  1,  1,  1,  1,  1,  1,  1 }
diff --git a/gcc/config/i386/mach.h b/gcc/config/i386/mach.h
deleted file mode 100755
index 4b7cf37..0000000
--- a/gcc/config/i386/mach.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Configuration for an i386 running Mach as the target machine.  */
-
-/* We do want to add an underscore to the front of each user symbol.
-   i386/gas.h checks this.  */
-#define YES_UNDERSCORES
-
-#include "i386/gstabs.h"
-
-/* Get perform_* macros to build libgcc.a.  */
-#include "i386/perform.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Di386 -DMACH -Asystem(unix) -Asystem(mach) -Acpu(i386) -Amachine(i386)"
-
-/* Specify extra dir to search for include files.  */
-#define SYSTEM_INCLUDE_DIR "/usr/mach/include"
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
diff --git a/gcc/config/i386/mingw32.h b/gcc/config/i386/mingw32.h
deleted file mode 100755
index 3ef5c5b..0000000
--- a/gcc/config/i386/mingw32.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Operating system specific defines to be used when targeting GCC for
-   hosting on Windows32, using GNU tools and the Windows32 API Library,
-   as distinct from winnt.h, which is used to build GCC for use with a
-   windows style library and tool set and uses the Microsoft tools.
-   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* Most of this is the same as for cygwin, except for changing some
-   specs.  */
-
-#include "i386/cygwin.h"
-
-/* Please keep changes to CPP_PREDEFINES in sync with i386/crtdll. The
-   only difference between the two should be __MSVCRT__ needed to 
-   distinguish MSVC from CRTDLL runtime in mingw headers. */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di386 -D_WIN32 -DWIN32 -D__WIN32__ \
-  -D__MINGW32__ -D__MSVCRT__ -DWINNT  -D_X86_=1 -D__STDC__=1\
-  -D__stdcall=__attribute__((__stdcall__)) \
-  -D_stdcall=__attribute__((__stdcall__)) \
-  -D__cdecl=__attribute__((__cdecl__)) \
-  -D__declspec(x)=__attribute__((x)) \
-  -Asystem(winnt) -Acpu(i386) -Amachine(i386)"
-
-/* Specific a different directory for the standard include files.  */
-#undef STANDARD_INCLUDE_DIR
-#define STANDARD_INCLUDE_DIR "/usr/local/i386-mingw32/include"
-
-#define STANDARD_INCLUDE_COMPONENT "MINGW32"
-
-/* For Windows applications, include more libraries, but always include
-   kernel32.  */
-#undef LIB_SPEC
-#define LIB_SPEC \
-"%{mwindows:-luser32 -lgdi32 -lcomdlg32} -lkernel32 -ladvapi32 -lshell32"
-
-/* Include in the mingw32 libraries with libgcc */
-#undef LIBGCC_SPEC
-#define LIBGCC_SPEC "-lmingw32 -lgcc -lmoldname -lmsvcrt"
-
-/* Specify a different entry point when linking a DLL */
-#undef LINK_SPEC
-#define LINK_SPEC \
-"%{mwindows:--subsystem windows} %{mdll:--dll -e _DllMainCRTStartup@12}"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{mdll:dllcrt2%O%s} %{!mdll:crt2%O%s}"
-
-#define MATH_LIBRARY "-lmsvcrt"
-
-/* Output STRING, a string representing a filename, to FILE.  We canonicalize
-   it to be in MS-DOS format.  */
-#define OUTPUT_QUOTED_STRING(FILE, STRING) \
-do {						\
-  char c;					\
-						\
-  putc ('\"', asm_file);			\
-  if (STRING[1] == ':'				\
-      && (STRING[2] == '/' || STRING[2] == '\\')) \
-    {						\
-      putc ('/', asm_file);			\
-      putc ('/', asm_file);			\
-      putc (*string, asm_file);			\
-      string += 2;				\
-    }						\
-						\
-  while ((c = *string++) != 0)			\
-    {						\
-      if (c == '\\')				\
-	c = '/';				\
-						\
-      if (c == '\"')				\
-	putc ('\\', asm_file);			\
-      putc (c, asm_file);			\
-    }						\
-						\
-  putc ('\"', asm_file);			\
-} while (0)
-
diff --git a/gcc/config/i386/moss.h b/gcc/config/i386/moss.h
deleted file mode 100755
index d2548e3..0000000
--- a/gcc/config/i386/moss.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Definitions for Intel 386 running MOSS
-   Copyright (C) 1996 Free Software Foundation, Inc.
-   Contributed by Bryan Ford <baford@cs.utah.edu>
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* I believe in reuse... */
-#include "i386/linux.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D__ELF__ -Di386 -Dmoss -Asystem(posix) -Acpu(i386) -Amachine(i386)"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC  "crt0.o%s"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC  "crtn.o%s"
-
-#undef	LINK_SPEC
-
diff --git a/gcc/config/i386/netbsd.h b/gcc/config/i386/netbsd.h
deleted file mode 100755
index 5978aec..0000000
--- a/gcc/config/i386/netbsd.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* This goes away when the math-emulator is fixed */
-#define TARGET_CPU_DEFAULT 0400		/* TARGET_NO_FANCY_MATH_387 */
-
-/* This is tested by i386gas.h.  */
-#define YES_UNDERSCORES
-
-#include <i386/gstabs.h>
-
-/* Get perform_* macros to build libgcc.a.  */
-#include <i386/perform.h>
-
-/* Get generic NetBSD definitions.  */
-#include <netbsd.h>
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Di386 -D__NetBSD__ -Asystem(unix) -Asystem(NetBSD) -Acpu(i386) -Amachine(i386)"
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "int"
-
-#undef WCHAR_UNSIGNED
-#define WCHAR_UNSIGNED 0
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 32
-
-#undef ASM_APP_ON
-#define ASM_APP_ON "#APP\n"
-
-#undef ASM_APP_OFF
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* The following macros are stolen from i386v4.h */
-/* These have to be defined to get PIC code correct */
-
-/* This is how to output an element of a case-vector that is relative.
-   This is only used for PIC code.  See comments by the `casesi' insn in
-   i386.md for an explanation of the expression this outputs. */
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE)
-
-/* Indicate that jump tables go in the text section.  This is
-   necessary when compiling PIC code.  */
-
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* i386 netbsd still uses old binutils that don't insert nops by default
-   when the .align directive demands to insert extra space in the text
-   segment.  */
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
-  if ((LOG)!=0) fprintf ((FILE), "\t.align %d,0x90\n", (LOG))
-
-/* Profiling routines, partially copied from i386/osfrose.h.  */
-
-/* Redefine this to use %eax instead of %edx.  */
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-{									\
-  if (flag_pic)								\
-    {									\
-      fprintf (FILE, "\tcall mcount@PLT\n");				\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\tcall mcount\n");				\
-    }									\
-}
-
-/* Until they use ELF or something that handles dwarf2 unwinds
-   and initialization stuff better.  */
-#define DWARF2_UNWIND_INFO 0
-
diff --git a/gcc/config/i386/netware.h b/gcc/config/i386/netware.h
deleted file mode 100755
index 6a0ca1f..0000000
--- a/gcc/config/i386/netware.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* This file is CYGNUS LOCAL.  */
-
-/* Core target definitions for GNU compiler for Intel 80386 running Netware 4.
-   and using stabs-in-elf for the debugging format.
-   Copyright (C) 1993, 1994 Free Software Foundation, Inc.
-
-   Written by David V. Henkel-Wallace (gumby@cygnus.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#include "i386/sysv4gdb.h"	/* Build on the base i386 SVR4 configuration */
-#include "netware.h"		/* Then add netware-specific goo. */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i386 Netware 4)");
-
-/* These surely require augmentation */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-  "-DAPX386 -D__i386__ -D__netware__ -Asystem(netware) -Acpu(i386) -Amachine(i386)"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
diff --git a/gcc/config/i386/next.h b/gcc/config/i386/next.h
deleted file mode 100755
index bbc0e6b..0000000
--- a/gcc/config/i386/next.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/* Target definitions for GNU compiler for Intel x86 CPU running NeXTSTEP
-   Copyright (C) 1993, 1995, 1996, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/gas.h"
-#include "nextstep.h"
-
-/* By default, target has a 80387, with IEEE FP.  */
-
-#undef	TARGET_DEFAULT
-#define TARGET_DEFAULT  (MASK_80387 | MASK_IEEE_FP)
-
-/* Implicit library calls should use memcpy, not bcopy, etc.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Machines that use the AT&T assembler syntax
-   also return floating point values in an FP register.
-   Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-#undef	VALUE_REGNO
-#define VALUE_REGNO(MODE) \
-  ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode	\
-   ? FIRST_FLOAT_REG : 0)
-
-/* 1 if N is a possible register number for a function value. */
-
-#undef	FUNCTION_VALUE_REGNO_P
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N)== FIRST_FLOAT_REG)
-
-#ifdef REAL_VALUE_TO_TARGET_LONG_DOUBLE
-#undef	ASM_OUTPUT_LONG_DOUBLE
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE)				\
-  do {									\
-    long hex[3];							\
-    REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, hex);			\
-    if (sizeof (int) == sizeof (long))					\
-      fprintf (FILE, "\t.long 0x%x\n\t.long 0x%x\n\t.long 0x%x\n",	\
-		hex[0], hex[1], hex[2]);				\
-    else								\
-      fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n\t.long 0x%lx\n",	\
-		hex[0], hex[1], hex[2]);				\
-  } while (0)
-#endif
-
-#ifdef REAL_VALUE_TO_TARGET_DOUBLE
-#undef	ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
-  do {									\
-    long hex[2];							\
-    REAL_VALUE_TO_TARGET_DOUBLE (VALUE, hex);				\
-    if (sizeof (int) == sizeof (long))					\
-      fprintf (FILE, "\t.long 0x%x\n\t.long 0x%x\n", hex[0], hex[1]);	\
-    else								\
-      fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", hex[0], hex[1]);	\
-  } while (0)
-#endif
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#ifdef REAL_VALUE_TO_TARGET_SINGLE
-#undef	ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
-  do {									\
-    long hex;								\
-    REAL_VALUE_TO_TARGET_SINGLE (VALUE, hex);				\
-    if (sizeof (int) == sizeof (long))					\
-      fprintf (FILE, "\t.long 0x%x\n", hex);				\
-    else								\
-      fprintf (FILE, "\t.long 0x%lx\n", hex);				\
-  } while (0)
-#endif
-
-/* A C statement or statements which output an assembler instruction
-   opcode to the stdio stream STREAM.  The macro-operand PTR is a
-   variable of type `char *' which points to the opcode name in its
-   "internal" form--the form that is written in the machine description.
-
-   GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic.
-   So use `repe' instead.  */
-
-#undef	ASM_OUTPUT_OPCODE
-#define ASM_OUTPUT_OPCODE(STREAM, PTR)	\
-{							\
-  if ((PTR)[0] == 'r'					\
-      && (PTR)[1] == 'e'				\
-      && (PTR)[2] == 'p')				\
-    {							\
-      if ((PTR)[3] == 'z')				\
-	{						\
-	  fprintf (STREAM, "repe");			\
-	  (PTR) += 4;					\
-	}						\
-      else if ((PTR)[3] == 'n' && (PTR)[4] == 'z')	\
-	{						\
-	  fprintf (STREAM, "repne");			\
-	  (PTR) += 5;					\
-	}						\
-    }							\
-}
-
-/* Define macro used to output shift-double opcodes when the shift
-   count is in %cl.  Some assemblers require %cl as an argument;
-   some don't.
-
-   GAS requires the %cl argument, so override unx386.h. */
-
-#undef	SHIFT_DOUBLE_OMITS_COUNT
-#define SHIFT_DOUBLE_OMITS_COUNT 0
-
-/* Print opcodes the way that GAS expects them. */
-#define GAS_MNEMONICS 1
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#undef	CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di386 -DNeXT -Dunix -D__MACH__ -D__LITTLE_ENDIAN__ -D__ARCHITECTURE__=\"i386\" -Asystem(unix) -Asystem(mach) -Acpu(i386) -Amachine(i386)"
-
-/* This accounts for the return pc and saved fp on the i386. */
-
-#define OBJC_FORWARDING_STACK_OFFSET 8
-#define OBJC_FORWARDING_MIN_OFFSET 8
-
-/* We do not want a dot in internal labels.  */
-
-#undef LPREFIX
-#define LPREFIX "L"
-
-#undef	ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER)	\
-    sprintf ((BUF), "*%s%d", (PREFIX), (NUMBER))
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#undef	ASM_APP_ON
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#undef	ASM_APP_OFF
-#define ASM_APP_OFF "#NO_APP\n"
-
-#undef	ASM_OUTPUT_REG_PUSH
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tpushl %se%s\n", "%", reg_names[REGNO])
-
-#undef	ASM_OUTPUT_REG_POP
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tpopl %se%s\n", "%", reg_names[REGNO])
-
-/* This is being overridden because the default i386 configuration
-   generates calls to "_mcount".  NeXT system libraries all use
-   "mcount".  */
-
-#undef	FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)				\
-{									\
-  if (flag_pic)								\
-    {									\
-      fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n",		\
-               LPREFIX, (LABELNO));					\
-      fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n");			\
-    }									\
-  else									\
-    {								  	\
-      fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO));	\
-      fprintf (FILE, "\tcall mcount\n");				\
-    }									\
-}
-
-/* BEGIN Calling Convention CHANGES */
-
-/* These changes violate the Intel/Unix ABI.  Specifically, they
-   change the way that space for a block return value is passed to a
-   function.  The ABI says that the pointer is passed on the stack.
-   We change to pass the pointer in %ebx.  This makes the NeXT
-   Objective-C forwarding mechanism possible to implement on an i386.  */
-
-/* Do NOT pass address of structure values on the stack.  */
-
-#undef	STRUCT_VALUE_INCOMING
-#undef	STRUCT_VALUE
-
-/* Pass them in %ebx.  */
-
-#undef	STRUCT_VALUE_REGNUM
-#define STRUCT_VALUE_REGNUM 3
-
-/* Because we are passing the pointer in a register, we don't need to
-   rely on the callee to pop it.  */
-
-#undef	RETURN_POPS_ARGS
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 				\
-  ((FUNDECL) && TREE_CODE (FUNDECL) == IDENTIFIER_NODE		\
-   ? 0								\
-   : (TARGET_RTD						\
-      && (TYPE_ARG_TYPES (FUNTYPE) == 0				\
-          || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE)))	\
-              == void_type_node))) ? (SIZE) : 0)
-
-/* END Calling Convention CHANGES */
-
-/* NeXT still uses old binutils that don't insert nops by default
-   when the .align directive demands to insert extra space in the text
-   segment.  */
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
-  if ((LOG)!=0) fprintf ((FILE), "\t.align %d,0x90\n", (LOG))
diff --git a/gcc/config/i386/os2.h b/gcc/config/i386/os2.h
deleted file mode 100755
index 8bbab36..0000000
--- a/gcc/config/i386/os2.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Definitions of target machine for GNU compiler
-   for an Intel i386 or later processor running OS/2 2.x.
-   Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc.
-   Contributed by Samuel Figueroa (figueroa@cs.nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#ifndef DEFAULT_TARGET_MACHINE
-#define DEFAULT_TARGET_MACHINE "i386-os2"
-#endif
-#ifndef LINK_SPEC
-#define LINK_SPEC "/st:1048576/pm:vio/noi/a:16/e/bas:65536/nol"
-#endif
-#ifndef LIB_SPEC
-#define LIB_SPEC "libgcc libc"
-#endif
-#ifndef STARTFILE_SPEC
-#define STARTFILE_SPEC "libcrt.lib"
-#endif
-#ifndef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "\\gcc\\bin\\"
-#endif
-#ifndef STANDARD_STARTFILE_PREFIX
-#define STANDARD_STARTFILE_PREFIX "\\gcc\\lib\\"
-#endif
-#ifndef LOCAL_INCLUDE_DIR
-#define LOCAL_INCLUDE_DIR "\\gcc\\include"
-#endif
-
-#define YES_UNDERSCORES
-#include "i386/gstabs.h"
-
-#define USE_COLLECT
-
-#define BIGGEST_FIELD_ALIGNMENT \
-  (maximum_field_alignment ? maximum_field_alignment : 32)
-
-extern int maximum_field_alignment;
-
-#undef PCC_BITFIELD_TYPE_MATTERS
-#define PCC_BITFIELD_TYPE_MATTERS (maximum_field_alignment == 0)
-
-/* Define this macro if it is advisable to hold scalars in registers
-   in a wider mode than that declared by the program.  In such cases,
-   the value is constrained to be within the bounds of the declared
-   type, but kept valid in the wider mode.  The signedness of the
-   extension may differ from that of the type.  */
-
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)  \
-  if (GET_MODE_CLASS (MODE) == MODE_INT         \
-      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
-      (MODE) = SImode;
-
-/* Define this if function arguments should also be promoted using the above
-   procedure.  */
-
-#define PROMOTE_FUNCTION_ARGS
-
-/* Likewise, if the function return value is promoted.  */
-
-#define PROMOTE_FUNCTION_RETURN
diff --git a/gcc/config/i386/osf1-ci.asm b/gcc/config/i386/osf1-ci.asm
deleted file mode 100755
index a0f0773..0000000
--- a/gcc/config/i386/osf1-ci.asm
+++ /dev/null
@@ -1,65 +0,0 @@
-! crti.s for OSF/1, x86; derived from sol2-ci.asm.
-
-!   Copyright (C) 1993, 1998 Free Software Foundation, Inc.
-!   Written By Fred Fish, Nov 1992
-! 
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-! 
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file with other programs, and to distribute
-! those programs without any restriction coming from the use of this
-! file.  (The General Public License restrictions do apply in other
-! respects; for example, they cover modification of the file, and
-! distribution when not linked into another program.)
-! 
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-! General Public License for more details.
-! 
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING.  If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-! 
-!    As a special exception, if you link this library with files
-!    compiled with GCC to produce an executable, this does not cause
-!    the resulting executable to be covered by the GNU General Public License.
-!    This exception does not however invalidate any other reasons why
-!    the executable file might be covered by the GNU General Public License.
-! 
-
-! This file just supplies labeled starting points for the .init and .fini
-! sections.  It is linked in before the values-Xx.o files and also before
-! crtbegin.o.
- 
-	.file	"crti.s"
-	.ident	"GNU C crti.s"
-
-	.section .init
-	.globl	_init
-	.type	_init,@function
-_init:
-
-	.section .fini
-	.globl	_fini
-	.type	_fini,@function
-_fini:
-
-.globl _init_init_routine
-.data
-        .align 4
-        .type    _init_init_routine,@object
-        .size    _init_init_routine,4
-_init_init_routine:
-        .long _init
-.globl _init_fini_routine
-        .align 4
-        .type    _init_fini_routine,@object
-        .size    _init_fini_routine,4
-_init_fini_routine:
-        .long _fini
diff --git a/gcc/config/i386/osf1-cn.asm b/gcc/config/i386/osf1-cn.asm
deleted file mode 100755
index a10298f..0000000
--- a/gcc/config/i386/osf1-cn.asm
+++ /dev/null
@@ -1,46 +0,0 @@
-! crtn.s for OSF/1, x86; derived from sol2-cn.asm.
-
-!   Copyright (C) 1993, 1998 Free Software Foundation, Inc.
-!   Written By Fred Fish, Nov 1992
-! 
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-! 
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file with other programs, and to distribute
-! those programs without any restriction coming from the use of this
-! file.  (The General Public License restrictions do apply in other
-! respects; for example, they cover modification of the file, and
-! distribution when not linked into another program.)
-! 
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-! General Public License for more details.
-! 
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING.  If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-! 
-!    As a special exception, if you link this library with files
-!    compiled with GCC to produce an executable, this does not cause
-!    the resulting executable to be covered by the GNU General Public License.
-!    This exception does not however invalidate any other reasons why
-!    the executable file might be covered by the GNU General Public License.
-! 
-
-! This file just supplies returns for the .init and .fini sections.  It is
-! linked in after all other files.
-
-	.file	"crtn.o"
-	.ident	"GNU C crtn.o"
-
-	.section .init
-	ret    $0x0
-
-	.section .fini
-	ret    $0x0
diff --git a/gcc/config/i386/osf1elf.h b/gcc/config/i386/osf1elf.h
deleted file mode 100755
index da61e8b..0000000
--- a/gcc/config/i386/osf1elf.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/* OSF/1 1.3 now is compitable with SVR4, so include sysv4.h, and
-   put difference here.  */
-
-#include <stdio.h>
-#include "i386/sysv4.h"	/* Base i386 target machine definitions */
-#define _sys_siglist sys_siglist
-extern char *sys_siglist[];
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i386 OSF/1)");
-
-/* WORD_SWITCH_TAKES_ARG defined in svr4 is not correct. We also
- need an extra -soname */
-#undef WORD_SWITCH_TAKES_ARG
-#define WORD_SWITCH_TAKES_ARG(STR)                    \
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR)                 \
-  || !strcmp (STR, "Tdata") || !strcmp (STR, "Ttext") \
-  || !strcmp (STR, "Tbss") || !strcmp (STR, "soname"))
-
-/* Note, -fpic and -fPIC are equivalent */
-#undef  CPP_SPEC
-#define CPP_SPEC "\
-%{fpic: -D__SHARED__} %{fPIC: %{!fpic: -D__SHARED__}} \
-%{.S:	%{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}} \
-%{.S:	-D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
-%{.cc:	-D__LANGUAGE_C_PLUS_PLUS} \
-%{.cxx:	-D__LANGUAGE_C_PLUS_PLUS} \
-%{.C:	-D__LANGUAGE_C_PLUS_PLUS} \
-%{.m:	-D__LANGUAGE_OBJECTIVE_C} \
-%{!.S:	-D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}"
-
-/* -mmcount or -mno-mcount should be used with -pg or -p */
-#undef  CC1_SPEC
-#define CC1_SPEC "%{p: %{!mmcount: %{!mno-mcount: -mno-mcount }}} \
-%{!p: %{pg: %{!mmcount: %{!mno-mcount: -mno-mcount }}}}"
-
-/* Note, -D__NO_UNDERSCORES__ -D__ELF__ are provided in the older version of
-   OSF/1 gcc. We keep them here, so that old /usr/include/i386/asm.h works.
-   */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-  "-D__NO_UNDERSCORES__ -D__ELF__ -DOSF -DOSF1 -Di386 -Dunix -Asystem(xpg4) -Asystem(osf1) -Acpu(i386) -Amachine(i386)"
-
-/* current OSF/1 doesn't provide separate crti.o and gcrti.o (and also, crtn.o
-   and gcrtn.o) for profile.  */
-
-#undef  STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared: \
-                         %{!symbolic: \
-                          %{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}}\
-			crti.o%s \
-			crtbegin.o%s"
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
-
-#undef	ASM_SPEC
-#define ASM_SPEC       "%{v*: -v}"
-
-#undef  LINK_SPEC
-#define LINK_SPEC      "%{v*: -v} \
-		%{h*} %{z*} \
-		%{dy:-call_shared} %{dn:-static} \
-		%{static:-static} \
-		%{shared:-shared} \
-		%{call_shared:-call_shared} \
-		%{symbolic:-Bsymbolic -shared -call_shared} \
-		%{!dy: %{!dn: %{!static: %{!shared: %{!symbolic: \
-			%{noshrlib: -static } \
-			%{!noshrlib: -call_shared}}}}}}"
-
-#undef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX	"/usr/ccs/gcc/"
-
-#undef  MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX	"/usr/ccs/lib/"
-
-/* Define this macro meaning that gcc should find the library 'libgcc.a'
-   by hand, rather than passing the argument '-lgcc' to tell the linker
-   to do the search */
-#define LINK_LIBGCC_SPECIAL
-
-/* This goes with LINK_LIBGCC_SPECIAL, we need tell libgcc.a differently */
-#undef  LIBGCC_SPEC
-#define LIBGCC_SPEC "%{!shared:%{!symbolic:libgcc.a%s}}"
-
-/* A C statement to output assembler commands which will identify the object
-  file as having been compile with GNU CC. We don't need or want this for
-  OSF1. */
-#undef ASM_IDENTIFY_GCC
-#define ASM_IDENTIFY_GCC(FILE)
-
-/* Identify the front-end which produced this file.  To keep symbol
-   space down, and not confuse kdb, only do this if the language is
-   not C.  */
-#define ASM_IDENTIFY_LANGUAGE(STREAM)                                   \
-{                                                                       \
-  if (strcmp (lang_identify (), "c") != 0)                              \
-    output_lang_identify (STREAM);                                      \
-}
-
-/* Specify size_t, ptrdiff_t, and wchar_t types.  */
-#undef  SIZE_TYPE
-#undef  PTRDIFF_TYPE
-#undef  WCHAR_TYPE
-#undef  WCHAR_TYPE_SIZE
-
-#define SIZE_TYPE       "long unsigned int"
-#define PTRDIFF_TYPE    "int"
-#define WCHAR_TYPE      "unsigned int"
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-/* Turn off long double being 96 bits.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Work with OSF/1 profile */
-#define MASK_NO_MCOUNT		000200000000	/* profiling uses mcount_ptr */
-
-#define TARGET_MCOUNT		((target_flags & MASK_NO_MCOUNT) == 0)
-
-#undef	SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES						\
-     { "mcount",		-MASK_NO_MCOUNT},			\
-     { "no-mcount",		 MASK_NO_MCOUNT},
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.
-
-   We override it here to allow for the new profiling code to go before
-   the prologue and the old mcount code to go after the prologue (and
-   after %ebx has been set up for ELF shared library support).  */
-#if 0
-#define OSF_PROFILE_BEFORE_PROLOGUE					\
-  (!TARGET_MCOUNT							\
-   && !current_function_needs_context					\
-   && (!flag_pic							\
-       || !frame_pointer_needed						\
-       || (!current_function_uses_pic_offset_table			\
-	   && !current_function_uses_const_pool)))
-#else
-#define OSF_PROFILE_BEFORE_PROLOGUE 0
-#endif
-#undef	FUNCTION_PROLOGUE
-#define FUNCTION_PROLOGUE(FILE, SIZE)					\
-do									\
-  {									\
-    char *prefix = "";			\
-    char *lprefix = LPREFIX;						\
-    int labelno = profile_label_no;					\
-									\
-    if (profile_flag && OSF_PROFILE_BEFORE_PROLOGUE)			\
-      {									\
-	if (!flag_pic)				\
-	  {								\
-	    fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno);	\
-	    fprintf (FILE, "\tcall *%s_mcount_ptr\n", prefix);		\
-	  }								\
-									\
-	else								\
-	  {								\
-	    static int call_no = 0;					\
-									\
-	    fprintf (FILE, "\tcall %sPc%d\n", lprefix, call_no);	\
-	    fprintf (FILE, "%sPc%d:\tpopl %%eax\n", lprefix, call_no);	\
-	    fprintf (FILE, "\taddl $_GLOBAL_OFFSET_TABLE_+[.-%sPc%d],%%eax\n", \
-		     lprefix, call_no++);				\
-	    fprintf (FILE, "\tleal %sP%d@GOTOFF(%%eax),%%edx\n",	\
-		     lprefix, labelno);					\
-	    fprintf (FILE, "\tmovl %s_mcount_ptr@GOT(%%eax),%%eax\n",	\
-		     prefix);						\
-	    fprintf (FILE, "\tcall *(%%eax)\n");			\
-	  }								\
-      }									\
-									\
-    function_prologue (FILE, SIZE);					\
-  }									\
-while (0)
-
-/* A C statement or compound statement to output to FILE some assembler code to
-   call the profiling subroutine `mcount'.  Before calling, the assembler code
-   must load the address of a counter variable into a register where `mcount'
-   expects to find the address.  The name of this variable is `LP' followed by
-   the number LABELNO, so you would generate the name using `LP%d' in a
-   `fprintf'.
-
-   The details of how the address should be passed to `mcount' are determined
-   by your operating system environment, not by GNU CC.  To figure them out,
-   compile a small program for profiling using the system's installed C
-   compiler and look at the assembler code that results. */
-
-#undef  FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)				\
-do									\
-  {									\
-    if (!OSF_PROFILE_BEFORE_PROLOGUE)					\
-      {									\
-	char *prefix = "";			\
-	char *lprefix = LPREFIX;					\
-	int labelno = LABELNO;					\
-									\
-	/* Note that OSF/rose blew it in terms of calling mcount,	\
-	   since OSF/rose prepends a leading underscore, but mcount's	\
-	   doesn't.  At present, we keep this kludge for ELF as well	\
-	   to allow old kernels to build profiling.  */			\
-									\
-	if (flag_pic							\
-	    && !current_function_uses_pic_offset_table			\
-	    && !current_function_uses_const_pool)			\
-	  abort ();							\
-									\
-	if (TARGET_MCOUNT && flag_pic)					\
-	  {								\
-	    fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n",	\
-		     lprefix, labelno);					\
-	    fprintf (FILE, "\tcall *%smcount@GOT(%%ebx)\n", prefix);	\
-	  }								\
-									\
-	else if (TARGET_MCOUNT)						\
-	  {								\
-	    fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno);	\
-	    fprintf (FILE, "\tcall %smcount\n", prefix);		\
-	  }								\
-									\
-	else if (flag_pic && frame_pointer_needed)			\
-	  {								\
-	    fprintf (FILE, "\tmovl 4(%%ebp),%%ecx\n");			\
-	    fprintf (FILE, "\tpushl %%ecx\n");				\
-	    fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n",	\
-		     lprefix, labelno);					\
-	    fprintf (FILE, "\tmovl _mcount_ptr@GOT(%%ebx),%%eax\n");	\
-	    fprintf (FILE, "\tcall *(%%eax)\n");			\
-	    fprintf (FILE, "\tpopl %%eax\n");				\
-	  }								\
-									\
-	else if (frame_pointer_needed)					\
-	  {								\
-	    fprintf (FILE, "\tmovl 4(%%ebp),%%ecx\n");			\
-	    fprintf (FILE, "\tpushl %%ecx\n");				\
-	    fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno);	\
-	    fprintf (FILE, "\tcall *_mcount_ptr\n");			\
-	    fprintf (FILE, "\tpopl %%eax\n");				\
-	  }								\
-									\
-	else								\
-	  abort ();							\
-      }									\
-  }									\
-while (0)
-
-#if defined (CROSS_COMPILE) && defined (HOST_BITS_PER_INT) && defined (HOST_BITS_PER_LONG) && defined (HOST_BITS_PER_LONGLONG)
-#if (HOST_BITS_PER_INT==32) && (HOST_BITS_PER_LONG==64) && (HOST_BITS_PER_LONGLONG==64)
-#define REAL_ARITHMETIC
-#endif
-#endif
diff --git a/gcc/config/i386/osf1elfgdb.h b/gcc/config/i386/osf1elfgdb.h
deleted file mode 100755
index af6efa2..0000000
--- a/gcc/config/i386/osf1elfgdb.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Target definitions for GNU compiler for Intel 80386 running OSF/1 1.3+
-   with gas and gdb.  */
-
-/* Use stabs instead of DWARF debug format.  */
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#include "i386/osf1elf.h"
diff --git a/gcc/config/i386/osfelf.h b/gcc/config/i386/osfelf.h
deleted file mode 100755
index 381ffc2..0000000
--- a/gcc/config/i386/osfelf.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Intel 386 (OSF/1 with ELF) version.
-   Copyright (C) 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config/i386/osfrose.h"
-
-#undef	CPP_PREDEFINES
-#define CPP_PREDEFINES "-DOSF -DOSF1 -Dunix -Asystem(xpg4)"
-
-#undef  CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) \
-%{mrose: -D__ROSE__ %{!pic-none: -D__SHARED__}} \
-%{!mrose: -D__ELF__ %{fpic: -D__SHARED__}} \
-%{mno-underscores: -D__NO_UNDERSCORES__} \
-%{!mrose: %{!munderscores: -D__NO_UNDERSCORES__}} \
-%{.S:	%{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}} \
-%{.S:	-D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
-%{.cc:	-D__LANGUAGE_C_PLUS_PLUS} \
-%{.cxx:	-D__LANGUAGE_C_PLUS_PLUS} \
-%{.C:	-D__LANGUAGE_C_PLUS_PLUS} \
-%{.m:	-D__LANGUAGE_OBJECTIVE_C} \
-%{!.S:	-D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}"
-
-/* Turn on -pic-extern by default for OSF/rose, -fpic for ELF.  */
-#undef  CC1_SPEC
-#define CC1_SPEC "\
-%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
-%{!melf: %{!mrose: -melf }} \
-%{!mrose: %{!munderscores: %{!mno-underscores: -mno-underscores }} \
-	  %{!mmcount: %{!mno-mcount: %{!mmcount-ptr: -mmcount-ptr }}}} \
-%{mrose: %{!mmcount: %{!mno-mcount: %{!mmcount-ptr: -mmcount }}} \
-	 %{pic-extern: -mhalf-pic } %{pic-lib: -mhalf-pic } \
-	 %{!pic-extern: %{!pic-lib: %{pic-none: -mno-half-pic} %{!pic-none: -mhalf-pic}}} \
-	 %{pic-calls: } %{pic-names*: }}"
-
-#undef	ASM_SPEC
-#define ASM_SPEC       "%{v*: -v}"
-
-#undef  LINK_SPEC
-#define LINK_SPEC      "%{v*: -v} \
-%{mrose:	%{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \
-		%{nostdlib} %{noshrlib} %{glue}} \
-%{!mrose:	%{dy} %{dn} %{glue: } \
-		%{h*} %{z*} \
-		%{static:-dn -Bstatic} \
-		%{shared:-G -dy} \
-		%{symbolic:-Bsymbolic -G -dy} \
-		%{G:-G} \
-		%{!dy: %{!dn: %{!static: %{!shared: %{!symbolic: \
-			%{noshrlib: -dn } %{pic-none: -dn } \
-			%{!noshrlib: %{!pic-none: -dy}}}}}}}}"
-
-#undef TARGET_VERSION_INTERNAL
-#undef TARGET_VERSION
-
-#undef	I386_VERSION
-#define I386_VERSION " 80386, ELF objects"
-
-#define TARGET_VERSION_INTERNAL(STREAM) fputs (I386_VERSION, STREAM)
-#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
-
-#undef OBJECT_FORMAT_ROSE
diff --git a/gcc/config/i386/osfrose.h b/gcc/config/i386/osfrose.h
deleted file mode 100755
index 9cfe187..0000000
--- a/gcc/config/i386/osfrose.h
+++ /dev/null
@@ -1,918 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Intel 386 (OSF/1 with OSF/rose) version.
-   Copyright (C) 1991, 1992, 1993, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "halfpic.h"
-#include "i386/gstabs.h"
-
-/* Get perform_* macros to build libgcc.a.  */
-#include "i386/perform.h"
-
-#define OSF_OS
-
-#undef  WORD_SWITCH_TAKES_ARG
-#define WORD_SWITCH_TAKES_ARG(STR)					\
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) || !strcmp (STR, "pic-names"))
-
-/* This defines which switch letters take arguments.  On svr4, most of
-   the normal cases (defined in gcc.c) apply, and we also have -h* and
-   -z* options (for the linker).  */
-
-#define SWITCH_TAKES_ARG(CHAR) \
-  (DEFAULT_SWITCH_TAKES_ARG(CHAR) \
-   || (CHAR) == 'h' \
-   || (CHAR) == 'z')
-
-#define MASK_HALF_PIC     	010000000000	/* Mask for half-pic code */
-#define MASK_HALF_PIC_DEBUG     004000000000	/* Debug flag */
-#define MASK_ELF		002000000000	/* ELF not rose */
-#define MASK_NO_IDENT		001000000000	/* suppress .ident */
-#define MASK_NO_UNDERSCORES	000400000000	/* suppress leading _ */
-#define MASK_LARGE_ALIGN	000200000000	/* align to >word boundaries */
-#define MASK_NO_MCOUNT		000100000000	/* profiling uses mcount_ptr */
-
-#define TARGET_HALF_PIC		(target_flags & MASK_HALF_PIC)
-#define TARGET_DEBUG		(target_flags & MASK_HALF_PIC_DEBUG)
-#define HALF_PIC_DEBUG		TARGET_DEBUG
-#define TARGET_ELF		(target_flags & MASK_ELF)
-#define TARGET_ROSE		((target_flags & MASK_ELF) == 0)
-#define TARGET_IDENT		((target_flags & MASK_NO_IDENT) == 0)
-#define TARGET_UNDERSCORES	((target_flags & MASK_NO_UNDERSCORES) == 0)
-#define TARGET_LARGE_ALIGN	(target_flags & MASK_LARGE_ALIGN)
-#define TARGET_MCOUNT		((target_flags & MASK_NO_MCOUNT) == 0)
-
-#undef	SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES						\
-     { "half-pic",		 MASK_HALF_PIC},			\
-     { "no-half-pic",		-MASK_HALF_PIC},			\
-     { "debug-half-pic",	 MASK_HALF_PIC_DEBUG},			\
-     { "debugb",		 MASK_HALF_PIC_DEBUG},			\
-     { "elf",			 MASK_ELF},				\
-     { "rose",			-MASK_ELF},				\
-     { "ident",			-MASK_NO_IDENT},			\
-     { "no-ident",		 MASK_NO_IDENT},			\
-     { "underscores",		-MASK_NO_UNDERSCORES},			\
-     { "no-underscores",	 MASK_NO_UNDERSCORES},			\
-     { "large-align",		 MASK_LARGE_ALIGN},			\
-     { "no-large-align",	-MASK_LARGE_ALIGN},			\
-     { "mcount",		-MASK_NO_MCOUNT},			\
-     { "mcount-ptr",		 MASK_NO_MCOUNT},			\
-     { "no-mcount",		 MASK_NO_MCOUNT},
-
-/* OSF/rose uses stabs, not dwarf.  */
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#ifndef DWARF_DEBUGGING_INFO
-#define DWARF_DEBUGGING_INFO	/* enable dwarf debugging for testing */
-#endif
-
-/* Handle #pragma weak and #pragma pack.  */
-
-#define HANDLE_SYSV_PRAGMA
-#define SUPPORTS_WEAK	TARGET_ELF
-
-/* Change default predefines.  */
-#undef	CPP_PREDEFINES
-#define CPP_PREDEFINES "-DOSF -DOSF1 -Dunix -Asystem(xpg4)"
-
-#undef  CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) \
-%{!melf: -D__ROSE__ %{!pic-none: -D__SHARED__}} \
-%{melf: -D__ELF__ %{fpic: -D__SHARED__}} \
-%{mno-underscores: -D__NO_UNDERSCORES__} \
-%{melf: %{!munderscores: -D__NO_UNDERSCORES__}} \
-%{.S:	%{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}} \
-%{.S:	-D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
-%{.cc:	-D__LANGUAGE_C_PLUS_PLUS} \
-%{.cxx:	-D__LANGUAGE_C_PLUS_PLUS} \
-%{.C:	-D__LANGUAGE_C_PLUS_PLUS} \
-%{.m:	-D__LANGUAGE_OBJECTIVE_C} \
-%{!.S:	-D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}"
-
-/* Turn on -pic-extern by default for OSF/rose, -fpic for ELF.  */
-#undef  CC1_SPEC
-#define CC1_SPEC "\
-%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
-%{!melf: %{!mrose: -mrose }} \
-%{melf: %{!munderscores: %{!mno-underscores: -mno-underscores }} \
-	%{!mmcount: %{!mno-mcount: %{!mmcount-ptr: -mmcount-ptr }}}} \
-%{!melf: %{!munderscores: %{!mno-underscores: -munderscores }} \
-	 %{!mmcount: %{!mno-mcount: %{!mmcount-ptr: -mmcount }}} \
-	 %{pic-extern: -mhalf-pic } %{pic-lib: -mhalf-pic } \
-	 %{!pic-extern: %{!pic-lib: %{pic-none: -mno-half-pic} %{!pic-none: -mhalf-pic}}} \
-	 %{pic-calls: } %{pic-names*: }}"
-
-#undef	ASM_SPEC
-#define ASM_SPEC       "%{v*: -v}"
-
-#undef  LINK_SPEC
-#define LINK_SPEC      "%{v*: -v} \
-%{!melf:	%{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \
-		%{nostdlib} %{noshrlib} %{glue}} \
-%{melf:		%{dy} %{dn} %{glue: } \
-		%{h*} %{z*} \
-		%{static:-dn -Bstatic} \
-		%{shared:-G -dy} \
-		%{symbolic:-Bsymbolic -G -dy} \
-		%{G:-G} \
-		%{!dy: %{!dn: %{!static: %{!shared: %{!symbolic: \
-			%{noshrlib: -dn } %{pic-none: -dn } \
-			%{!noshrlib: %{!pic-none: -dy}}}}}}}}"
-
-#undef  LIB_SPEC
-#define LIB_SPEC "-lc"
-
-#undef  LIBG_SPEC
-#define LIBG_SPEC ""
-
-#undef  STARTFILE_SPEC
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-
-#undef TARGET_VERSION_INTERNAL
-#undef TARGET_VERSION
-
-#define I386_VERSION " 80386, OSF/rose objects"
-
-#define TARGET_VERSION_INTERNAL(STREAM) fputs (I386_VERSION, STREAM)
-#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
-
-#undef  MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX		"/usr/ccs/gcc/"
-
-#undef  MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX	"/usr/ccs/lib/"
-
-/* Specify size_t, ptrdiff_t, and wchar_t types.  */
-#undef	SIZE_TYPE
-#undef	PTRDIFF_TYPE
-#undef	WCHAR_TYPE
-#undef	WCHAR_TYPE_SIZE
-
-#define SIZE_TYPE	"long unsigned int"
-#define PTRDIFF_TYPE	"int"
-#define WCHAR_TYPE	"unsigned int"
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-/* Define this macro if the system header files support C++ as well
-   as C.  This macro inhibits the usual method of using system header
-   files in C++, which is to pretend that the file's contents are
-   enclosed in `extern "C" {...}'. */
-#define NO_IMPLICIT_EXTERN_C
-
-/* Turn off long double being 96 bits.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.
-
-   We override it here to allow for the new profiling code to go before
-   the prologue and the old mcount code to go after the prologue (and
-   after %ebx has been set up for ELF shared library support).  */
-
-#define OSF_PROFILE_BEFORE_PROLOGUE					\
-  (!TARGET_MCOUNT							\
-   && !current_function_needs_context					\
-   && (!flag_pic							\
-       || !frame_pointer_needed						\
-       || (!current_function_uses_pic_offset_table			\
-	   && !current_function_uses_const_pool)))
-
-#undef	FUNCTION_PROLOGUE
-#define FUNCTION_PROLOGUE(FILE, SIZE)					\
-do									\
-  {									\
-    char *prefix = (TARGET_UNDERSCORES) ? "_" : "";			\
-    char *lprefix = LPREFIX;						\
-    int labelno = profile_label_no;					\
-									\
-    if (profile_flag && OSF_PROFILE_BEFORE_PROLOGUE)			\
-      {									\
-	if (!flag_pic && !HALF_PIC_P ())				\
-	  {								\
-	    fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno);	\
-	    fprintf (FILE, "\tcall *%s_mcount_ptr\n", prefix);		\
-	  }								\
-									\
-	else if (HALF_PIC_P ())						\
-	  {								\
-	    rtx symref;							\
-									\
-	    HALF_PIC_EXTERNAL ("_mcount_ptr");				\
-	    symref = HALF_PIC_PTR (gen_rtx (SYMBOL_REF, Pmode,		\
-					    "_mcount_ptr"));		\
-									\
-	    fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno);	\
-	    fprintf (FILE, "\tmovl %s%s,%%eax\n", prefix,		\
-		     XSTR (symref, 0));					\
-	    fprintf (FILE, "\tcall *(%%eax)\n");			\
-	  }								\
-									\
-	else								\
-	  {								\
-	    static int call_no = 0;					\
-									\
-	    fprintf (FILE, "\tcall %sPc%d\n", lprefix, call_no);	\
-	    fprintf (FILE, "%sPc%d:\tpopl %%eax\n", lprefix, call_no);	\
-	    fprintf (FILE, "\taddl $_GLOBAL_OFFSET_TABLE_+[.-%sPc%d],%%eax\n", \
-		     lprefix, call_no++);				\
-	    fprintf (FILE, "\tleal %sP%d@GOTOFF(%%eax),%%edx\n",	\
-		     lprefix, labelno);					\
-	    fprintf (FILE, "\tmovl %s_mcount_ptr@GOT(%%eax),%%eax\n",	\
-		     prefix);						\
-	    fprintf (FILE, "\tcall *(%%eax)\n");			\
-	  }								\
-      }									\
-									\
-    function_prologue (FILE, SIZE);					\
-  }									\
-while (0)
-
-/* A C statement or compound statement to output to FILE some assembler code to
-   call the profiling subroutine `mcount'.  Before calling, the assembler code
-   must load the address of a counter variable into a register where `mcount'
-   expects to find the address.  The name of this variable is `LP' followed by
-   the number LABELNO, so you would generate the name using `LP%d' in a
-   `fprintf'.
-
-   The details of how the address should be passed to `mcount' are determined
-   by your operating system environment, not by GNU CC.  To figure them out,
-   compile a small program for profiling using the system's installed C
-   compiler and look at the assembler code that results. */
-
-#undef  FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)				\
-do									\
-  {									\
-    if (!OSF_PROFILE_BEFORE_PROLOGUE)					\
-      {									\
-	char *prefix = (TARGET_UNDERSCORES) ? "_" : "";			\
-	char *lprefix = LPREFIX;					\
-	int labelno = LABELNO;						\
-									\
-	/* Note that OSF/rose blew it in terms of calling mcount,	\
-	   since OSF/rose prepends a leading underscore, but mcount's	\
-	   doesn't.  At present, we keep this kludge for ELF as well	\
-	   to allow old kernels to build profiling.  */			\
-									\
-	if (flag_pic							\
-	    && !current_function_uses_pic_offset_table			\
-	    && !current_function_uses_const_pool)			\
-	  abort ();							\
-									\
-	if (TARGET_MCOUNT && flag_pic)					\
-	  {								\
-	    fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n",	\
-		     lprefix, labelno);					\
-	    fprintf (FILE, "\tcall *%smcount@GOT(%%ebx)\n", prefix);	\
-	  }								\
-									\
-	else if (TARGET_MCOUNT && HALF_PIC_P ())			\
-	  {								\
-	    rtx symdef;							\
-									\
-	    HALF_PIC_EXTERNAL ("mcount");				\
-	    symdef = HALF_PIC_PTR (gen_rtx (SYMBOL_REF, Pmode, "mcount")); \
-	    fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno);	\
-	    fprintf (FILE, "\tcall *%s%s\n", prefix, XSTR (symdef, 0));	\
-	  }								\
-									\
-	else if (TARGET_MCOUNT)						\
-	  {								\
-	    fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno);	\
-	    fprintf (FILE, "\tcall %smcount\n", prefix);		\
-	  }								\
-									\
-	else if (flag_pic && frame_pointer_needed)			\
-	  {								\
-	    fprintf (FILE, "\tmovl 4(%%ebp),%%ecx\n");			\
-	    fprintf (FILE, "\tpushl %%ecx\n");				\
-	    fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n",	\
-		     lprefix, labelno);					\
-	    fprintf (FILE, "\tmovl _mcount_ptr@GOT(%%ebx),%%eax\n");	\
-	    fprintf (FILE, "\tcall *(%%eax)\n");			\
-	    fprintf (FILE, "\tpopl %%eax\n");				\
-	  }								\
-									\
-	else if (frame_pointer_needed)					\
-	  {								\
-	    fprintf (FILE, "\tmovl 4(%%ebp),%%ecx\n");			\
-	    fprintf (FILE, "\tpushl %%ecx\n");				\
-	    fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno);	\
-	    fprintf (FILE, "\tcall *_mcount_ptr\n");			\
-	    fprintf (FILE, "\tpopl %%eax\n");				\
-	  }								\
-									\
-	else								\
-	  abort ();							\
-      }									\
-  }									\
-while (0)
-
-/* A C function or functions which are needed in the library to
-   support block profiling.  When support goes into libc, undo
-   the #if 0.  */
-
-#if 0
-#undef	BLOCK_PROFILING_CODE
-#define	BLOCK_PROFILING_CODE
-#endif
-
-/* Prefix for internally generated assembler labels.  If we aren't using
-   underscores, we are using prefix `.'s to identify labels that should
-   be ignored, as in `i386/gas.h' --karl@cs.umb.edu  */
-#undef	LPREFIX
-#define	LPREFIX ((TARGET_UNDERSCORES) ? "L" : ".L")
-
-/* This is how to store into the string BUF
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#undef	ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER)			\
-    sprintf ((BUF), "*%s%s%d", (TARGET_UNDERSCORES) ? "" : ".",		\
-	     (PREFIX), (NUMBER))
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef	ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)			\
-  fprintf (FILE, "%s%s%d:\n", (TARGET_UNDERSCORES) ? "" : ".",		\
-	   PREFIX, NUM)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-/* target_flags is not accessible by the preprocessor */
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output a reference to a user-level label named NAME.  */
-
-#undef	ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE,NAME)					\
-  fprintf (FILE, "%s%s", (TARGET_UNDERSCORES) ? "_" : "", NAME)
-
-/* This is how to output an element of a case-vector that is relative.
-   This is only used for PIC code.  See comments by the `casesi' insn in
-   i386.md for an explanation of the expression this outputs. */
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE)
-
-/* Output a definition */
-#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)				\
-do									\
-{									\
-    fprintf ((FILE), "\t%s\t", SET_ASM_OP);				\
-    assemble_name (FILE, LABEL1);					\
-    fprintf (FILE, ",");						\
-    assemble_name (FILE, LABEL2);					\
-    fprintf (FILE, "\n");						\
-    }									\
-while (0)
-
-/* A C expression to output text to align the location counter in the
-   way that is desirable at a point in the code that is reached only
-   by jumping.
-
-   This macro need not be defined if you don't want any special
-   alignment to be done at such a time.  Most machine descriptions do
-   not currently define the macro.  */
-
-#undef	LABEL_ALIGN_AFTER_BARRIER
-#define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
-  ((!TARGET_LARGE_ALIGN && i386_align_jumps > 2) ? 2 : i386_align_jumps)
-
-/* A C expression to output text to align the location counter in the
-   way that is desirable at the beginning of a loop.
-
-   This macro need not be defined if you don't want any special
-   alignment to be done at such a time.  Most machine descriptions do
-   not currently define the macro.  */
-
-#undef	LOOP_ALIGN
-#define LOOP_ALIGN(LABEL) (i386_align_loops)
-
-/* A C statement to output to the stdio stream STREAM an assembler
-   command to advance the location counter to a multiple of 2 to the
-   POWER bytes.  POWER will be a C expression of type `int'.  */
-
-#undef	ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(STREAM, POWER)					\
-  fprintf (STREAM, "\t.align\t%d\n",					\
-	   (!TARGET_LARGE_ALIGN && (POWER) > 2) ? 2 : (POWER))
-
-/* A C expression that is 1 if the RTX X is a constant which is a
-   valid address.  On most machines, this can be defined as
-   `CONSTANT_P (X)', but a few machines are more restrictive in
-   which constant addresses are supported.
-
-   `CONSTANT_P' accepts integer-values expressions whose values are
-   not explicitly known, such as `symbol_ref', `label_ref', and
-   `high' expressions and `const' arithmetic expressions, in
-   addition to `const_int' and `const_double' expressions.  */
-
-#define CONSTANT_ADDRESS_P_ORIG(X)					\
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-#undef	CONSTANT_ADDRESS_P
-#define CONSTANT_ADDRESS_P(X)                                           \
-  ((CONSTANT_ADDRESS_P_ORIG (X)) && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#undef	LEGITIMATE_CONSTANT_P
-#define LEGITIMATE_CONSTANT_P(X)					\
-  (!HALF_PIC_P ()							\
-   || GET_CODE (X) == CONST_DOUBLE					\
-   || GET_CODE (X) == CONST_INT						\
-   || !HALF_PIC_ADDRESS_P (X))
-
-/* Sometimes certain combinations of command options do not make sense
-   on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.  */
-
-#undef  SUBTARGET_OVERRIDE_OPTIONS
-#define SUBTARGET_OVERRIDE_OPTIONS					\
-{									\
-  /*									\
-  if (TARGET_ELF && TARGET_HALF_PIC)					\
-    {									\
-      target_flags &= ~MASK_HALF_PIC;					\
-      flag_pic = 1;							\
-    }									\
-  */									\
-									\
-  if (TARGET_ROSE && flag_pic)						\
-    {									\
-      target_flags |= MASK_HALF_PIC;					\
-      flag_pic = 0;							\
-    }									\
-									\
-  if (TARGET_HALF_PIC)							\
-    half_pic_init ();							\
-}
-
-/* Define this macro if references to a symbol must be treated
-   differently depending on something about the variable or
-   function named by the symbol (such as what section it is in).
-
-   The macro definition, if any, is executed immediately after the
-   rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
-   The value of the rtl will be a `mem' whose address is a
-   `symbol_ref'.
-
-   The usual thing for this macro to do is to a flag in the
-   `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
-   name string in the `symbol_ref' (if one bit is not enough
-   information).
-
-   The best way to modify the name string is by adding text to the
-   beginning, with suitable punctuation to prevent any ambiguity.
-   Allocate the new name in `saveable_obstack'.  You will have to
-   modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
-   and output the name accordingly.
-
-   You can also check the information stored in the `symbol_ref' in
-   the definition of `GO_IF_LEGITIMATE_ADDRESS' or
-   `PRINT_OPERAND_ADDRESS'. */
-
-#undef	ENCODE_SECTION_INFO
-#define ENCODE_SECTION_INFO(DECL)					\
-do									\
-  {									\
-   if (HALF_PIC_P ())							\
-      HALF_PIC_ENCODE (DECL);						\
-									\
-   else if (flag_pic)							\
-     {									\
-       rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd'		\
-		  ? TREE_CST_RTL (DECL) : DECL_RTL (DECL));		\
-       SYMBOL_REF_FLAG (XEXP (rtl, 0))					\
-	 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd'			\
-	    || ! TREE_PUBLIC (DECL));					\
-      }									\
-  }									\
-while (0)
-
-
-/* On most machines, read-only variables, constants, and jump tables
-   are placed in the text section.  If this is not the case on your
-   machine, this macro should be defined to be the name of a function
-   (either `data_section' or a function defined in `EXTRA_SECTIONS')
-   that switches to the section to be used for read-only items.
-
-   If these items should be placed in the text section, this macro
-   should not be defined.  */
-
-#if 0
-#undef	READONLY_DATA_SECTION
-#define READONLY_DATA_SECTION()						\
-do									\
-  {									\
-    if (TARGET_ELF)							\
-      {									\
-	if (in_section != in_rodata)					\
-	  {								\
-	    fprintf (asm_out_file, "\t.section \"rodata\"\n");		\
-	    in_section = in_rodata;					\
-	  }								\
-      }									\
-    else								\
-      text_section ();							\
-  }									\
-while (0)
-#endif
-
-/* A list of names for sections other than the standard two, which are
-   `in_text' and `in_data'.  You need not define this macro on a
-   system with no other sections (that GCC needs to use).  */
-
-#undef	EXTRA_SECTIONS
-#define	EXTRA_SECTIONS in_rodata, in_data1
-
-/* Given a decl node or constant node, choose the section to output it in
-   and select that section.  */
-
-#undef	SELECT_RTX_SECTION
-#define SELECT_RTX_SECTION(MODE, RTX)					\
-do									\
-  {									\
-    if (MODE == Pmode && HALF_PIC_P () && HALF_PIC_ADDRESS_P (RTX))	\
-      data_section ();							\
-    else								\
-      readonly_data_section ();						\
-  }									\
-while (0)
-
-#undef	SELECT_SECTION
-#define SELECT_SECTION(DECL, RELOC)					\
-{									\
-  if (RELOC && HALF_PIC_P ())						\
-    data_section ();							\
-									\
-  else if (TREE_CODE (DECL) == STRING_CST)				\
-    {									\
-      if (flag_writable_strings)					\
-	data_section ();						\
-      else								\
-	readonly_data_section ();					\
-    }									\
-									\
-  else if (TREE_CODE (DECL) != VAR_DECL)				\
-    readonly_data_section ();						\
-									\
-  else if (!TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)		\
-	   || !DECL_INITIAL (DECL)					\
-	   || (DECL_INITIAL (DECL) != error_mark_node			\
-	       && !TREE_CONSTANT (DECL_INITIAL (DECL))))		\
-    data_section ();							\
-									\
-  else									\
-    readonly_data_section ();						\
-}
-
-
-/* Define the strings used for the special svr4 .type and .size directives.
-   These strings generally do not vary from one system running svr4 to
-   another, but if a given system (e.g. m88k running svr) needs to use
-   different pseudo-op names for these, they may be overridden in the
-   file which includes this one.  */
-
-#define TYPE_ASM_OP	".type"
-#define SIZE_ASM_OP	".size"
-#define SET_ASM_OP	".set"
-
-/* This is how we tell the assembler that a symbol is weak.  */
-
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
-  do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \
-       fputc ('\n', FILE); } while (0)
-
-/* The following macro defines the format used to output the second
-   operand of the .type assembler directive.  Different svr4 assemblers
-   expect various different forms for this operand.  The one given here
-   is just a default.  You may need to override it in your machine-
-   specific tm.h file (depending upon the particulars of your assembler).  */
-
-#define TYPE_OPERAND_FMT	"@%s"
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   STREAM any text necessary for declaring the name NAME of an
-   initialized variable which is being defined.  This macro must
-   output the label definition (perhaps using `ASM_OUTPUT_LABEL').
-   The argument DECL is the `VAR_DECL' tree node representing the
-   variable.
-
-   If this macro is not defined, then the variable name is defined
-   in the usual manner as a label (by means of `ASM_OUTPUT_LABEL').  */
-
-#undef	ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL)			     \
-do									     \
- {									     \
-   ASM_OUTPUT_LABEL(STREAM,NAME);					     \
-   HALF_PIC_DECLARE (NAME);						     \
-   if (TARGET_ELF)							     \
-     {									     \
-       fprintf (STREAM, "\t%s\t ", TYPE_ASM_OP);			     \
-       assemble_name (STREAM, NAME);					     \
-       putc (',', STREAM);						     \
-       fprintf (STREAM, TYPE_OPERAND_FMT, "object");			     \
-       putc ('\n', STREAM);						     \
-       size_directive_output = 0;					     \
-       if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		     \
-	 {								     \
-           size_directive_output = 1;					     \
-	   fprintf (STREAM, "\t%s\t ", SIZE_ASM_OP);			     \
-	   assemble_name (STREAM, NAME);				     \
-	   fprintf (STREAM, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL))); \
-	 }								     \
-     }									     \
- }									     \
-while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
-     if (TARGET_ELF							 \
-	 && !flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
-	 assemble_name (FILE, name);					 \
-	 fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL))); \
-       }								 \
-   } while (0)
-
-/* This is how to declare a function name. */
-
-#undef	ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)			\
-do									\
- {									\
-   ASM_OUTPUT_LABEL(STREAM,NAME);					\
-   HALF_PIC_DECLARE (NAME);						\
-   if (TARGET_ELF)							\
-     {									\
-       fprintf (STREAM, "\t%s\t ", TYPE_ASM_OP);			\
-       assemble_name (STREAM, NAME);					\
-       putc (',', STREAM);						\
-       fprintf (STREAM, TYPE_OPERAND_FMT, "function");			\
-       putc ('\n', STREAM);						\
-       ASM_DECLARE_RESULT (STREAM, DECL_RESULT (DECL));			\
-     }									\
- }									\
-while (0)
-
-/* Write the extra assembler code needed to declare a function's result.
-   Most svr4 assemblers don't require any special declaration of the
-   result value, but there are exceptions.  */
-
-#ifndef ASM_DECLARE_RESULT
-#define ASM_DECLARE_RESULT(FILE, RESULT)
-#endif
-
-/* This is how to declare the size of a function.  */
-
-#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)			\
-do									\
-  {									\
-    if (TARGET_ELF && !flag_inhibit_size_directive)			\
-      {									\
-        char label[256];						\
-	static int labelno;						\
-	labelno++;							\
-	ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno);		\
-	ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno);		\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, (FNAME));					\
-        fprintf (FILE, ",");						\
-	assemble_name (FILE, label);					\
-        fprintf (FILE, "-");						\
-	assemble_name (FILE, (FNAME));					\
-	putc ('\n', FILE);						\
-      }									\
-  }									\
-while (0)
-
-/* Attach a special .ident directive to the end of the file to identify
-   the version of GCC which compiled this code.  The format of the
-   .ident string is patterned after the ones produced by native svr4
-   C compilers.  */
-
-#define IDENT_ASM_OP ".ident"
-
-/* Allow #sccs in preprocessor.  */
-
-#define SCCS_DIRECTIVE
-
-/* This says what to print at the end of the assembly file */
-#define ASM_FILE_END(STREAM)						\
-do									\
-  {									\
-    if (HALF_PIC_P ())							\
-      HALF_PIC_FINISH (STREAM);						\
-									\
-    if (TARGET_IDENT)							\
-      {									\
-	char *fstart = main_input_filename;				\
-	char *fname;							\
-									\
-	if (!fstart)							\
-	  fstart = "<no file>";						\
-									\
-	fname = fstart + strlen (fstart) - 1;				\
-	while (fname > fstart && *fname != '/')				\
-	  fname--;							\
-									\
-	if (*fname == '/')						\
-	  fname++;							\
-									\
-	fprintf ((STREAM), "\t%s\t\"GCC: (GNU) %s %s -O%d",		\
-		 IDENT_ASM_OP, version_string, fname, optimize);	\
-									\
-	if (write_symbols == PREFERRED_DEBUGGING_TYPE)			\
-	  fprintf ((STREAM), " -g%d", (int)debug_info_level);		\
-									\
-	else if (write_symbols == DBX_DEBUG)				\
-	  fprintf ((STREAM), " -gstabs%d", (int)debug_info_level);	\
-									\
-	else if (write_symbols == DWARF_DEBUG)				\
-	  fprintf ((STREAM), " -gdwarf%d", (int)debug_info_level);	\
-									\
-	else if (write_symbols != NO_DEBUG)				\
-	  fprintf ((STREAM), " -g??%d", (int)debug_info_level);		\
-									\
-	if (flag_omit_frame_pointer)					\
-	  fprintf ((STREAM), " -fomit-frame-pointer");			\
-									\
-	if (flag_strength_reduce)					\
-	  fprintf ((STREAM), " -fstrength-reduce");			\
-									\
-	if (flag_unroll_loops)						\
-	  fprintf ((STREAM), " -funroll-loops");			\
-									\
-	if (flag_schedule_insns)					\
-	  fprintf ((STREAM), " -fschedule-insns");			\
-									\
-	if (flag_schedule_insns_after_reload)				\
-	  fprintf ((STREAM), " -fschedule-insns2");			\
-									\
-	if (flag_force_mem)						\
-	  fprintf ((STREAM), " -fforce-mem");				\
-									\
-	if (flag_force_addr)						\
-	  fprintf ((STREAM), " -fforce-addr");				\
-									\
-	if (flag_inline_functions)					\
-	  fprintf ((STREAM), " -finline-functions");			\
-									\
-	if (flag_caller_saves)						\
-	  fprintf ((STREAM), " -fcaller-saves");			\
-									\
-	if (flag_pic)							\
-	  fprintf ((STREAM), (flag_pic > 1) ? " -fPIC" : " -fpic");	\
-									\
-	if (flag_inhibit_size_directive)				\
-	  fprintf ((STREAM), " -finhibit-size-directive");		\
-									\
-	if (flag_gnu_linker)						\
-	  fprintf ((STREAM), " -fgnu-linker");				\
-									\
-	if (profile_flag)						\
-	  fprintf ((STREAM), " -p");					\
-									\
-	if (profile_block_flag)						\
-	  fprintf ((STREAM), " -a");					\
-									\
-	if (TARGET_IEEE_FP)						\
-	  fprintf ((STREAM), " -mieee-fp");				\
-									\
-	if (TARGET_HALF_PIC)						\
-	  fprintf ((STREAM), " -mhalf-pic");				\
-									\
-	if (!TARGET_MOVE)						\
-	  fprintf ((STREAM), " -mno-move");				\
-									\
-	if (TARGET_386)							\
-	  fprintf ((STREAM), " -m386");					\
-									\
-	else if (TARGET_486)						\
-	  fprintf ((STREAM), " -m486");					\
-									\
-	else								\
-	  fprintf ((STREAM), " -munknown-machine");			\
-									\
-	fprintf ((STREAM), (TARGET_ELF) ? " -melf\"\n" : " -mrose\"\n"); \
-      }									\
-  }									\
-while (0)
-
-/* Tell collect that the object format is OSF/rose.  */
-#define OBJECT_FORMAT_ROSE
-
-/* Tell collect where the appropriate binaries are.  */
-#define REAL_NM_FILE_NAME	"/usr/ccs/gcc/bfd-nm"
-#define REAL_STRIP_FILE_NAME	"/usr/ccs/bin/strip"
-
-/* Use atexit for static constructors/destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
-/* Define this macro meaning that gcc should find the library 'libgcc.a'
-   by hand, rather than passing the argument '-lgcc' to tell the linker
-   to do the search */
-#define LINK_LIBGCC_SPECIAL
-
-/* A C statement to output assembler commands which will identify the object
-  file as having been compile with GNU CC. We don't need or want this for
-  OSF1. GDB doesn't need it and kdb doesn't like it */
-#define ASM_IDENTIFY_GCC(FILE)
-
-/* Identify the front-end which produced this file.  To keep symbol
-   space down, and not confuse kdb, only do this if the language is
-   not C.  */
-
-#define ASM_IDENTIFY_LANGUAGE(STREAM)					\
-{									\
-  if (strcmp (lang_identify (), "c") != 0)				\
-    output_lang_identify (STREAM);					\
-}
-
-/* Generate calls to memcpy, etc., not bcopy, etc. */
-#define TARGET_MEM_FUNCTIONS
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Map i386 registers to the numbers dwarf expects.  Of course this is different
-   from what stabs expects.  */
-
-#define DWARF_DBX_REGISTER_NUMBER(n) \
-((n) == 0 ? 0 \
- : (n) == 1 ? 2 \
- : (n) == 2 ? 1 \
- : (n) == 3 ? 3 \
- : (n) == 4 ? 6 \
- : (n) == 5 ? 7 \
- : (n) == 6 ? 5 \
- : (n) == 7 ? 4 \
- : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \
- : (-1))
-
-/* Now what stabs expects in the register.  */
-#define STABS_DBX_REGISTER_NUMBER(n) \
-((n) == 0 ? 0 : \
- (n) == 1 ? 2 : \
- (n) == 2 ? 1 : \
- (n) == 3 ? 3 : \
- (n) == 4 ? 6 : \
- (n) == 5 ? 7 : \
- (n) == 6 ? 4 : \
- (n) == 7 ? 5 : \
- (n) + 4)
-
-#undef	DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n) ((write_symbols == DWARF_DEBUG)		\
-				? DWARF_DBX_REGISTER_NUMBER(n)		\
-				: STABS_DBX_REGISTER_NUMBER(n))
diff --git a/gcc/config/i386/perform.h b/gcc/config/i386/perform.h
deleted file mode 100755
index 8d6d0b7..0000000
--- a/gcc/config/i386/perform.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Definitions for AT&T assembler syntax for the Intel 80386.
-   Copyright (C) 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Defines to be able to build libgcc.a with GCC.  */
-
-/* It might seem that these are not important, since gcc 2 will never
-   call libgcc for these functions.  But programs might be linked with
-   code compiled by gcc 1, and then these will be used.  */
-
-/* The arg names used to be a and b, but `a' appears inside strings
-   and that confuses non-ANSI cpp.  */
-
-#define perform_udivsi3(arg0,arg1)					\
-{									\
-  register int dx asm("dx");						\
-  register int ax asm("ax");						\
-									\
-  dx = 0;								\
-  ax = arg0;								\
-  asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1), "d" (dx)); \
-  return ax;								\
-}
-
-#define perform_divsi3(arg0,arg1)					\
-{									\
-  register int dx asm("dx");						\
-  register int ax asm("ax");						\
-  register int cx asm("cx");						\
-									\
-  ax = arg0;								\
-  cx = arg1;								\
-  asm ("cltd\n\tidivl %3" : "=a" (ax), "=&d" (dx) : "a" (ax), "c" (cx)); \
-  return ax;								\
-}
-
-#define perform_umodsi3(arg0,arg1)					\
-{									\
-  register int dx asm("dx");						\
-  register int ax asm("ax");						\
-									\
-  dx = 0;								\
-  ax = arg0;								\
-  asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1), "d" (dx)); \
-  return dx;								\
-}
-
-#define perform_modsi3(arg0,arg1)					\
-{									\
-  register int dx asm("dx");						\
-  register int ax asm("ax");						\
-  register int cx asm("cx");						\
-									\
-  ax = arg0;								\
-  cx = arg1;								\
-  asm ("cltd\n\tidivl %3" : "=a" (ax), "=&d" (dx) : "a" (ax), "c" (cx)); \
-  return dx;								\
-}
-
-#define perform_fixdfsi(arg0)						\
-{									\
-  auto unsigned short ostatus;						\
-  auto unsigned short nstatus;						\
-  auto int ret;								\
-  auto double tmp;							\
-									\
-  &ostatus;			/* guarantee these land in memory */	\
-  &nstatus;								\
-  &ret;									\
-  &tmp;									\
-									\
-  asm volatile ("fnstcw %0" : "=m" (ostatus));				\
-  nstatus = ostatus | 0x0c00;						\
-  asm volatile ("fldcw %0" : /* no outputs */ : "m" (nstatus));		\
-  tmp = arg0;								\
-  asm volatile ("fldl %0" : /* no outputs */ : "m" (tmp));		\
-  asm volatile ("fistpl %0" : "=m" (ret));				\
-  asm volatile ("fldcw %0" : /* no outputs */ : "m" (ostatus));		\
-									\
-  return ret;								\
-}
-
diff --git a/gcc/config/i386/ptx4-i.h b/gcc/config/i386/ptx4-i.h
deleted file mode 100755
index 1537b4a..0000000
--- a/gcc/config/i386/ptx4-i.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/* Target definitions for GNU compiler for Intel 80386 running Dynix/ptx v4
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-   Modified from sysv4.h
-   Originally written by Ron Guilmette (rfg@netcom.com).
-   Modified by Tim Wright (timw@sequent.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/i386.h"	/* Base i386 target machine definitions */
-#include "i386/att.h"	/* Use the i386 AT&T assembler syntax */
-#include "ptx4.h"	/* Rest of definitions (non architecture dependent) */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i386 Sequent Dynix/ptx Version 4)");
-
-/* The svr4 ABI for the i386 says that records and unions are returned
-   in memory.  */
-
-#undef RETURN_IN_MEMORY
-#define RETURN_IN_MEMORY(TYPE) \
-  (TYPE_MODE (TYPE) == BLKmode)
-
-/* Define which macros to predefine.  _SEQUENT_ is our extension.  */
-/* This used to define X86, but james@bigtex.cactus.org says that
-   is supposed to be defined optionally by user programs--not by default.  */
-#define CPP_PREDEFINES \
-  "-Di386 -Dunix -D_SEQUENT_ -Asystem(unix) -Asystem(ptx4) -Acpu(i386) -Amachine(i386)"
-
-/* This is how to output assembly code to define a `float' constant.
-   We always have to use a .long pseudo-op to do this because the native
-   SVR4 ELF assembler is buggy and it generates incorrect values when we
-   try to use the .float pseudo-op instead.  */
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
-do { long value;							\
-     REAL_VALUE_TO_TARGET_SINGLE ((VALUE), value);			\
-     if (sizeof (int) == sizeof (long))					\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value);		\
-     else								\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value);		\
-   } while (0)
-
-/* This is how to output assembly code to define a `double' constant.
-   We always have to use a pair of .long pseudo-ops to do this because
-   the native SVR4 ELF assembler is buggy and it generates incorrect
-   values when we try to use the .double pseudo-op instead.  */
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
-do { long value[2];							\
-     REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), value);			\
-     if (sizeof (int) == sizeof (long))					\
-       {								\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[0]);		\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[1]);		\
-       }								\
-     else								\
-       {								\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[0]);		\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[1]);		\
-       }								\
-   } while (0)
-
-
-#undef ASM_OUTPUT_LONG_DOUBLE
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE)				\
-do { long value[3];							\
-     REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), value);			\
-     if (sizeof (int) == sizeof (long))					\
-       {								\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[0]);		\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[1]);		\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[2]);		\
-       }								\
-     else								\
-       {								\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[0]);		\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[1]);		\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[2]);		\
-       }								\
-   } while (0)
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)						\
-  do {									\
-	output_file_directive (FILE, main_input_filename);		\
-	fprintf (FILE, "\t.version\t\"01.01\"\n");			\
-  } while (0)
-
-/* Define the register numbers to be used in Dwarf debugging information.
-   The SVR4 reference port C compiler uses the following register numbers
-   in its Dwarf output code:
-
-	0 for %eax (gnu regno = 0)
-	1 for %ecx (gnu regno = 2)
-	2 for %edx (gnu regno = 1)
-	3 for %ebx (gnu regno = 3)
-	4 for %esp (gnu regno = 7)
-	5 for %ebp (gnu regno = 6)
-	6 for %esi (gnu regno = 4)
-	7 for %edi (gnu regno = 5)
-
-   The following three DWARF register numbers are never generated by
-   the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
-   believes these numbers have these meanings.
-
-	8  for %eip    (no gnu equivalent)
-	9  for %eflags (no gnu equivalent)
-	10 for %trapno (no gnu equivalent)
-
-   It is not at all clear how we should number the FP stack registers
-   for the x86 architecture.  If the version of SDB on x86/svr4 were
-   a bit less brain dead with respect to floating-point then we would
-   have a precedent to follow with respect to DWARF register numbers
-   for x86 FP registers, but the SDB on x86/svr4 is so completely
-   broken with respect to FP registers that it is hardly worth thinking
-   of it as something to strive for compatibility with.
-
-   The version of x86/svr4 SDB I have at the moment does (partially)
-   seem to believe that DWARF register number 11 is associated with
-   the x86 register %st(0), but that's about all.  Higher DWARF
-   register numbers don't seem to be associated with anything in
-   particular, and even for DWARF regno 11, SDB only seems to under-
-   stand that it should say that a variable lives in %st(0) (when
-   asked via an `=' command) if we said it was in DWARF regno 11,
-   but SDB still prints garbage when asked for the value of the
-   variable in question (via a `/' command).
-
-   (Also note that the labels SDB prints for various FP stack regs
-   when doing an `x' command are all wrong.)
-
-   Note that these problems generally don't affect the native SVR4
-   C compiler because it doesn't allow the use of -O with -g and
-   because when it is *not* optimizing, it allocates a memory
-   location for each floating-point variable, and the memory
-   location is what gets described in the DWARF AT_location
-   attribute for the variable in question.
-
-   Regardless of the severe mental illness of the x86/svr4 SDB, we
-   do something sensible here and we use the following DWARF
-   register numbers.  Note that these are all stack-top-relative
-   numbers.
-
-	11 for %st(0) (gnu regno = 8)
-	12 for %st(1) (gnu regno = 9)
-	13 for %st(2) (gnu regno = 10)
-	14 for %st(3) (gnu regno = 11)
-	15 for %st(4) (gnu regno = 12)
-	16 for %st(5) (gnu regno = 13)
-	17 for %st(6) (gnu regno = 14)
-	18 for %st(7) (gnu regno = 15)
-*/
-
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n) \
-((n) == 0 ? 0 \
- : (n) == 1 ? 2 \
- : (n) == 2 ? 1 \
- : (n) == 3 ? 3 \
- : (n) == 4 ? 6 \
- : (n) == 5 ? 7 \
- : (n) == 6 ? 5 \
- : (n) == 7 ? 4 \
- : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \
- : (-1))
-
-/* The routine used to output sequences of byte values.  We use a special
-   version of this for most svr4 targets because doing so makes the
-   generated assembly code more compact (and thus faster to assemble)
-   as well as more readable.  Note that if we find subparts of the
-   character sequence which end with NUL (and which are shorter than
-   STRING_LIMIT) we output those using ASM_OUTPUT_LIMITED_STRING.  */
-
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH)				\
-  do									\
-    {									\
-      register unsigned char *_ascii_bytes = (unsigned char *) (STR);	\
-      register unsigned char *limit = _ascii_bytes + (LENGTH);		\
-      register unsigned bytes_in_chunk = 0;				\
-      for (; _ascii_bytes < limit; _ascii_bytes++)			\
-        {								\
-	  register unsigned char *p;					\
-	  if (bytes_in_chunk >= 64)					\
-	    {								\
-	      fputc ('\n', (FILE));					\
-	      bytes_in_chunk = 0;					\
-	    }								\
-	  for (p = _ascii_bytes; p < limit && *p != '\0'; p++)		\
-	    continue;							\
-	  if (p < limit && (p - _ascii_bytes) <= STRING_LIMIT)		\
-	    {								\
-	      if (bytes_in_chunk > 0)					\
-		{							\
-		  fputc ('\n', (FILE));					\
-		  bytes_in_chunk = 0;					\
-		}							\
-	      ASM_OUTPUT_LIMITED_STRING ((FILE), _ascii_bytes);		\
-	      _ascii_bytes = p;						\
-	    }								\
-	  else								\
-	    {								\
-	      if (bytes_in_chunk == 0)					\
-		fprintf ((FILE), "\t.byte\t");				\
-	      else							\
-		fputc (',', (FILE));					\
-	      fprintf ((FILE), "0x%02x", *_ascii_bytes);		\
-	      bytes_in_chunk += 5;					\
-	    }								\
-	}								\
-      if (bytes_in_chunk > 0)						\
-        fprintf ((FILE), "\n");						\
-    }									\
-  while (0)
-
-/* This is how to output an element of a case-vector that is relative.
-   This is only used for PIC code.  See comments by the `casesi' insn in
-   i386.md for an explanation of the expression this outputs. */
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE)
-
-/* Indicate that jump tables go in the text section.  This is
-   necessary when compiling PIC code.  */
-
-#define JUMP_TABLES_IN_TEXT_SECTION 1
diff --git a/gcc/config/i386/rtems.h b/gcc/config/i386/rtems.h
deleted file mode 100755
index 60e6dc7..0000000
--- a/gcc/config/i386/rtems.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Definitions for rtems targeting an Intel i386 using coff.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/i386-coff.h"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di386 -Drtems -D__rtems__ \
-   -Asystem(rtems) -Acpu(i386) -Amachine(i386)"
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#ifndef TARGET_MEM_FUNCTIONS
-#define TARGET_MEM_FUNCTIONS
-#endif
-
diff --git a/gcc/config/i386/rtemself.h b/gcc/config/i386/rtemself.h
deleted file mode 100755
index d9d9733..0000000
--- a/gcc/config/i386/rtemself.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Definitions for Intel 386 running Linux-based GNU systems with ELF format.
-   Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Eric Youngdale.
-   Modified for stabs-in-ELF by H.J. Lu.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define LINUX_DEFAULT_ELF
-
-/* A lie, I guess, but the general idea behind linux/ELF is that we are
-   supposed to be outputting something that will assemble under SVr4.
-   This gets us pretty close.  */
-#include <i386/i386.h>	/* Base i386 target machine definitions */
-#include <i386/att.h>	/* Use the i386 AT&T assembler syntax */
-#include <linux.h>	/* some common stuff */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i386 RTEMS with ELF)");
-
-/* The svr4 ABI for the i386 says that records and unions are returned
-   in memory.  */
-#undef DEFAULT_PCC_STRUCT_RETURN
-#define DEFAULT_PCC_STRUCT_RETURN 1
-
-/* This is how to output an element of a case-vector that is relative.
-   This is only used for PIC code.  See comments by the `casesi' insn in
-   i386.md for an explanation of the expression this outputs. */
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE)
-
-/* Indicate that jump tables go in the text section.  This is
-   necessary when compiling PIC code.  */
-#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
-
-/* Copy this from the svr4 specifications... */
-/* Define the register numbers to be used in Dwarf debugging information.
-   The SVR4 reference port C compiler uses the following register numbers
-   in its Dwarf output code:
-	0 for %eax (gnu regno = 0)
-	1 for %ecx (gnu regno = 2)
-	2 for %edx (gnu regno = 1)
-	3 for %ebx (gnu regno = 3)
-	4 for %esp (gnu regno = 7)
-	5 for %ebp (gnu regno = 6)
-	6 for %esi (gnu regno = 4)
-	7 for %edi (gnu regno = 5)
-   The following three DWARF register numbers are never generated by
-   the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
-   believes these numbers have these meanings.
-	8  for %eip    (no gnu equivalent)
-	9  for %eflags (no gnu equivalent)
-	10 for %trapno (no gnu equivalent)
-   It is not at all clear how we should number the FP stack registers
-   for the x86 architecture.  If the version of SDB on x86/svr4 were
-   a bit less brain dead with respect to floating-point then we would
-   have a precedent to follow with respect to DWARF register numbers
-   for x86 FP registers, but the SDB on x86/svr4 is so completely
-   broken with respect to FP registers that it is hardly worth thinking
-   of it as something to strive for compatibility with.
-   The version of x86/svr4 SDB I have at the moment does (partially)
-   seem to believe that DWARF register number 11 is associated with
-   the x86 register %st(0), but that's about all.  Higher DWARF
-   register numbers don't seem to be associated with anything in
-   particular, and even for DWARF regno 11, SDB only seems to under-
-   stand that it should say that a variable lives in %st(0) (when
-   asked via an `=' command) if we said it was in DWARF regno 11,
-   but SDB still prints garbage when asked for the value of the
-   variable in question (via a `/' command).
-   (Also note that the labels SDB prints for various FP stack regs
-   when doing an `x' command are all wrong.)
-   Note that these problems generally don't affect the native SVR4
-   C compiler because it doesn't allow the use of -O with -g and
-   because when it is *not* optimizing, it allocates a memory
-   location for each floating-point variable, and the memory
-   location is what gets described in the DWARF AT_location
-   attribute for the variable in question.
-   Regardless of the severe mental illness of the x86/svr4 SDB, we
-   do something sensible here and we use the following DWARF
-   register numbers.  Note that these are all stack-top-relative
-   numbers.
-	11 for %st(0) (gnu regno = 8)
-	12 for %st(1) (gnu regno = 9)
-	13 for %st(2) (gnu regno = 10)
-	14 for %st(3) (gnu regno = 11)
-	15 for %st(4) (gnu regno = 12)
-	16 for %st(5) (gnu regno = 13)
-	17 for %st(6) (gnu regno = 14)
-	18 for %st(7) (gnu regno = 15)
-*/
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n) \
-((n) == 0 ? 0 \
- : (n) == 1 ? 2 \
- : (n) == 2 ? 1 \
- : (n) == 3 ? 3 \
- : (n) == 4 ? 6 \
- : (n) == 5 ? 7 \
- : (n) == 6 ? 5 \
- : (n) == 7 ? 4 \
- : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \
- : (-1))
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-{									\
-  if (flag_pic)								\
-    {									\
-      fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n",		\
-	       LPREFIX, (LABELNO));					\
-      fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n");			\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO));	\
-      fprintf (FILE, "\tcall mcount\n");				\
-    }									\
-}
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
- 
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-  
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-   
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-    
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES  "-Di386 -Drtems -D__rtems__ \
-   -Asystem(rtems) -Acpu(i386) -Amachine(i386)"
-
-/* Get perform_* macros to build libgcc.a.  */
-#include "i386/perform.h"
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of uninitialized global DECL named
-   NAME whose size is SIZE bytes and alignment is ALIGN bytes.
-   Try to use asm_output_aligned_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC  "crt0.o%s"
-
-#undef ENDFILE_SPEC
-     
diff --git a/gcc/config/i386/sco.h b/gcc/config/i386/sco.h
deleted file mode 100755
index 55af641..0000000
--- a/gcc/config/i386/sco.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Definitions for Intel 386 running SCO Unix System V.
-   Copyright (C) 1988, 92, 94, 95, 96, 1999  Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Mostly it's like AT&T Unix System V. */
-
-#include "i386/sysv3.h"
-
-/* By default, target has a 80387, uses IEEE compatible arithmetic,
-   and returns float values in the 387, ie,
-   (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387)
-
-   SCO's software emulation of a 387 fails to handle the `fucomp'
-   opcode.  fucomp is only used when generating IEEE compliant code.
-   So don't make TARGET_IEEE_FP default for SCO. */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_80387 | MASK_FLOAT_RETURNS)
-
-/* Let's guess that the SCO software FPU emulator can't handle
-   80-bit XFmode insns, so don't generate them.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} crtbegin.o%s"
-
-#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
-
-/* Library spec, including SCO international language support. */
-
-#undef LIB_SPEC
-#define LIB_SPEC \
- "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} %{scointl:libintl.a%s} -lc"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -DM_UNIX -DM_I386 -DM_COFF -DM_WORDSWAP -Asystem(svr3)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) %{scointl:-DM_INTERNAT}"
-
-/* This spec is used for telling cpp whether char is signed or not.  */
-
-#undef SIGNED_CHAR_SPEC
-#if DEFAULT_SIGNED_CHAR
-#define SIGNED_CHAR_SPEC \
- "%{funsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}"
-#else
-#define SIGNED_CHAR_SPEC \
- "%{!fsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}"
-#endif
-
-/* Use atexit for static destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
-/* Specify the size_t type.  */
-#define SIZE_TYPE "unsigned int"
-
-#if 0 /* Not yet certain whether this is needed.  */
-/* If no 387, use the general regs to return floating values,
-   since this system does not emulate the 80387.  */
-
-#undef VALUE_REGNO
-#define VALUE_REGNO(MODE) \
-  ((TARGET_80387
-     && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)
-   ? FIRST_FLOAT_REG : 0)
-
-#undef HARD_REGNO_MODE_OK
-#define HARD_REGNO_MODE_OK(REGNO, MODE)					  \
-  ((REGNO) < 2 ? 1							  \
-   : (REGNO) < 4 ? 1							  \
-   : FP_REGNO_P (REGNO) ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT		  \
-                          || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
-                         && TARGET_80387				  \
-                         && GET_MODE_UNIT_SIZE (MODE) <= 8)		  \
-   : (MODE) != QImode)
-#endif
-
-/* caller has to pop the extra argument passed to functions that return
-   structures. */
-
-#undef RETURN_POPS_ARGS
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE)   \
-  ((FUNDECL) && TREE_CODE (FUNDECL) == IDENTIFIER_NODE ? 0	\
-   : (TARGET_RTD						\
-      && (TYPE_ARG_TYPES (FUNTYPE) == 0				\
-	  || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE)))	\
-	      == void_type_node))) ? (SIZE)			\
-   : 0)
-/* On other 386 systems, the last line looks like this:
-   : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0)  */
-
-/* Handle #pragma pack. */
-#define HANDLE_SYSV_PRAGMA
diff --git a/gcc/config/i386/sco4.h b/gcc/config/i386/sco4.h
deleted file mode 100755
index 5d1ea47..0000000
--- a/gcc/config/i386/sco4.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* Definitions for Intel 386 running SCO Unix System V 3.2 Version 4.
-   Written by Chip Salzenberg.
-   Copyright (C) 1992, 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Mostly it's like earlier SCO UNIX.  */
-
-#include "i386/sco.h"
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{scoxpg3:%{p:mcrt1X.o%s}%{!p:crt1X.o%s}} \
-  %{!scoxpg3:\
-   %{posix:%{p:mcrt1P.o%s}%{!p:crt1P.o%s}} \
-   %{!posix:\
-    %{ansi:%{p:mcrt1A.o%s}%{!p:crt1A.o%s}} \
-    %{!ansi:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}} \
-  crtbegin.o%s"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC \
- "crtend.o%s \
-  %{scoxpg3:crtnX.o%s} \
-  %{!scoxpg3:\
-   %{posix:crtnP.o%s} \
-   %{!posix:\
-    %{ansi:crtnA.o%s} \
-    %{!ansi:crtn.o%s}}}"
-
-/* Library spec.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC \
- "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} \
- %{scoxpg3:-lcX -lcP -lcA} \
- %{!scoxpg3:\
-  %{posix:-lcP -lcA} \
-  %{!posix:\
-   %{ansi:-lcA} \
-   %{!ansi:%{scointl:-lintl} -lc}}}"
-
-/* Macros, macros everywhere:
-   Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-Asystem(svr3)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) \
-  -D_i386 -D_M_I386 -D_M_I86 -D_M_I86SM -D_M_SDATA -D_M_STEXT \
-  -D_unix -D_M_UNIX -D_M_XENIX \
-  -D_M_SYS5 -D_M_SYSV -D_M_SYS3 -D_M_SYSIII \
-  -D_M_COFF -D_M_BITFIELDS -D_M_WORDSWAP \
-  %{scoxpg3:-D_XOPEN_SOURCE -D_STRICT_NAMES} \
-  %{!scoxpg3:%{posix:-D_POSIX_SOURCE -D_STRICT_NAMES}} \
-  %{!scoxpg3:%{!posix:\
-    %{ansi:-D_STRICT_NAMES}%{!ansi:\
-    -Di386 -DM_I386 -DM_I86 -DM_I86SM -DM_SDATA -DM_STEXT \
-    -Dunix -DM_UNIX -DM_XENIX \
-    -DM_SYS5 -DM_SYSV -DM_SYS3 -DM_SYSIII \
-    -DM_COFF -DM_BITFIELDS -DM_WORDSWAP \
-    %{scointl:-D_M_INTERNAT -DM_INTERNAT} \
-    %{traditional:-D_KR -D_SVID -D_NO_PROTOTYPE}}}}"
-
-/* The system headers are C++-aware.  */
-#define NO_IMPLICIT_EXTERN_C
diff --git a/gcc/config/i386/sco4dbx.h b/gcc/config/i386/sco4dbx.h
deleted file mode 100755
index 3d075b6..0000000
--- a/gcc/config/i386/sco4dbx.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Definitions for Intel 386 running SCO Unix System V 3.2 Version 4.s,
-   using dbx-in-coff encapsulation.
-   Copyright (C) 1992 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Mostly it's like earlier SCO UNIX.  */
-
-#include "i386/scodbx.h"
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{!r:%{!z:gcc.ifile%s}%{z:gccz.ifile%s}}\
-  %{scoxpg3:%{p:mcrt1X.o%s}%{!p:crt1X.o%s}} \
-  %{!scoxpg3:\
-   %{posix:%{p:mcrt1P.o%s}%{!p:crt1P.o%s}} \
-   %{!posix:\
-    %{ansi:%{p:mcrt1A.o%s}%{!p:crt1A.o%s}} \
-    %{!ansi:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}}"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC \
- "%{scoxpg3:crtnX.o%s} \
-  %{!scoxpg3:\
-   %{posix:crtnP.o%s} \
-   %{!posix:\
-    %{ansi:crtnA.o%s} \
-    %{!ansi:crtn.o%s}}}"
-
-/* Library spec.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC \
- "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} \
- %{scoxpg3:-lcX -lcP -lcA} \
- %{!scoxpg3:\
-  %{posix:-lcP -lcA} \
-  %{!posix:\
-   %{ansi:-lcA} \
-   %{!ansi:%{scointl:-lintl} -lc}}}"
-
-/* Macros, macros everywhere:
-   Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Asystem(svr3)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) \
-  -D_M_I386 -D_M_I86 -D_M_I86SM -D_M_SDATA -D_M_STEXT \
-  -D_M_UNIX -D_M_XENIX \
-  -D_M_SYS5 -D_M_SYSV -D_M_SYS3 -D_M_SYSIII \
-  -D_M_COFF -D_M_BITFIELDS -D_M_WORDSWAP \
-  %{scoxpg3:-D_XOPEN_SOURCE -D_STRICT_NAMES} \
-  %{!scoxpg3:%{posix:-D_POSIX_SOURCE -D_STRICT_NAMES}} \
-  %{!scoxpg3:%{!posix:\
-    %{ansi:-D_STRICT_NAMES}%{!ansi:\
-    -DM_I386 -DM_I86 -DM_I86SM -DM_SDATA -DM_STEXT \
-    -DM_UNIX -DM_XENIX \
-    -DM_SYS5 -DM_SYSV -DM_SYS3 -DM_SYSIII \
-    -DM_COFF -DM_BITFIELDS -DM_WORDSWAP \
-    %{scointl:-D_M_INTERNAT -DM_INTERNAT} \
-    %{traditional:-D_KR -D_SVID -D_NO_PROTOTYPE}}}}"
diff --git a/gcc/config/i386/sco5.h b/gcc/config/i386/sco5.h
deleted file mode 100755
index 16ee957..0000000
--- a/gcc/config/i386/sco5.h
+++ /dev/null
@@ -1,974 +0,0 @@
-/* Definitions for Intel 386 running SCO Unix System V 3.2 Version 5.
-   Copyright (C) 1992, 95-98, 1999 Free Software Foundation, Inc.
-   Contributed by Kean Johnston (hug@netcom.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/i386.h"	/* Base i386 target definitions */
-#include "i386/att.h"	/* Use AT&T i386 assembler syntax */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i386, SCO OpenServer 5 Syntax)");
-
-#undef LPREFIX
-#define LPREFIX				".L"
-
-#undef ALIGN_ASM_OP
-#define ALIGN_ASM_OP			"\t.align"
-
-#undef ASCII_DATA_ASM_OP
-#define ASCII_DATA_ASM_OP		"\t.ascii"
-
-#undef ASM_BYTE_OP
-#define ASM_BYTE_OP			"\t.byte"
-
-#undef IDENT_ASM_OP
-#define IDENT_ASM_OP			"\t.ident"
-
-#undef COMMON_ASM_OP
-#define COMMON_ASM_OP			"\t.comm"
-
-#undef SET_ASM_OP
-#define SET_ASM_OP			"\t.set"
-
-#undef LOCAL_ASM_OP
-#define LOCAL_ASM_OP			"\t.local"
-
-#undef INT_ASM_OP
-#define INT_ASM_OP			"\t.long"
-
-#undef ASM_SHORT
-#define ASM_SHORT			"\t.value"
-
-#undef ASM_LONG
-#define ASM_LONG			"\t.long"
-
-#undef ASM_DOUBLE
-#define ASM_DOUBLE			"\t.double"
-
-#undef TYPE_ASM_OP
-#define TYPE_ASM_OP			"\t.type"
-
-#undef SIZE_ASM_OP
-#define SIZE_ASM_OP			"\t.size"
-
-#undef STRING_ASM_OP
-#define STRING_ASM_OP			"\t.string"
-
-#undef SKIP_ASM_OP
-#define SKIP_ASM_OP			"\t.zero"
-
-#undef GLOBAL_ASM_OP
-#define GLOBAL_ASM_OP			"\t.globl"
-
-#undef EH_FRAME_SECTION_ASM_OP
-#define EH_FRAME_SECTION_ASM_OP_COFF	"\t.section\t.ehfram, \"x\""
-#define EH_FRAME_SECTION_ASM_OP_ELF	"\t.section\t.eh_frame, \"aw\""
-#define EH_FRAME_SECTION_ASM_OP	\
-  ((TARGET_ELF) ? EH_FRAME_SECTION_ASM_OP_ELF : EH_FRAME_SECTION_ASM_OP_COFF)
-
-/* Avoid problems (long sectino names, forward assembler refs) with DWARF
-   exception unwinding when we're generating COFF */
-#define DWARF2_UNWIND_INFO	\
-  ((TARGET_ELF) ? 1 : 0 )  
-
-#undef CONST_SECTION_ASM_OP
-#define CONST_SECTION_ASM_OP_COFF	"\t.section\t.rodata, \"x\""
-#define CONST_SECTION_ASM_OP_ELF	"\t.section\t.rodata"
-#define CONST_SECTION_ASM_OP	\
-  ((TARGET_ELF) ? CONST_SECTION_ASM_OP_ELF : CONST_SECTION_ASM_OP_COFF)
-
-#undef USE_CONST_SECTION
-#define USE_CONST_SECTION_ELF		1
-#define USE_CONST_SECTION_COFF		0
-#define USE_CONST_SECTION	\
- ((TARGET_ELF) ? USE_CONST_SECTION_ELF : USE_CONST_SECTION_COFF)
-
-#undef INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP_ELF		"\t.section\t.init"
-#define INIT_SECTION_ASM_OP_COFF	"\t.section\t.init ,\"x\""
-#define INIT_SECTION_ASM_OP	\
-  ((TARGET_ELF) ? INIT_SECTION_ASM_OP_ELF : INIT_SECTION_ASM_OP_COFF)
-
-#undef CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP_ELF	"\t.section\t.ctors,\"aw\""
-#define CTORS_SECTION_ASM_OP_COFF	INIT_SECTION_ASM_OP_COFF
-#define CTORS_SECTION_ASM_OP	\
- ((TARGET_ELF) ? CTORS_SECTION_ASM_OP_ELF : CTORS_SECTION_ASM_OP_COFF)
-
-#undef DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP_ELF	"\t.section\t.dtors, \"aw\""
-#define DTORS_SECTION_ASM_OP_COFF	FINI_SECTION_ASM_OP_COFF
-#define DTORS_SECTION_ASM_OP	\
- ((TARGET_ELF) ? DTORS_SECTION_ASM_OP_ELF : DTORS_SECTION_ASM_OP_COFF)
-
-#undef FINI_SECTION_ASM_OP
-#define FINI_SECTION_ASM_OP_ELF		"\t.section\t.fini"
-#define FINI_SECTION_ASM_OP_COFF	"\t.section\t.fini, \"x\""
-#define FINI_SECTION_ASM_OP	\
- ((TARGET_ELF) ? FINI_SECTION_ASM_OP_ELF : FINI_SECTION_ASM_OP_COFF)
-
-#undef BSS_SECTION_ASM_OP
-#define BSS_SECTION_ASM_OP		"\t.data"
-
-#undef TEXT_SECTION_ASM_OP
-#define TEXT_SECTION_ASM_OP		"\t.text"
-
-#undef DATA_SECTION_ASM_OP
-#define DATA_SECTION_ASM_OP		"\t.data"
-
-#undef TYPE_OPERAND_FMT
-#define TYPE_OPERAND_FMT		"@%s"
-
-#undef APPLY_RESULT_SIZE
-#define APPLY_RESULT_SIZE						\
-(TARGET_ELF) ? size : 116
-
-#ifndef ASM_DECLARE_RESULT
-#define ASM_DECLARE_RESULT(FILE, RESULT)
-#endif
-
-#define SCO_DEFAULT_ASM_COFF(FILE,NAME)					\
-do {									\
-      ASM_OUTPUT_LABEL (FILE, NAME);					\
-  } while (0)
-
-#undef ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-  do {									\
-    if (TARGET_ELF) {							\
-      fprintf (FILE, "%s\t ", TYPE_ASM_OP);				\
-      assemble_name (FILE, NAME);					\
-      putc (',', FILE);							\
-      fprintf (FILE, TYPE_OPERAND_FMT, "function");			\
-      putc ('\n', FILE);						\
-      ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));			\
-      ASM_OUTPUT_LABEL(FILE, NAME);					\
-    } else								\
-      SCO_DEFAULT_ASM_COFF(FILE, NAME);					\
-} while (0)
-
-#undef ASM_DECLARE_FUNCTION_SIZE
-#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)			\
-  do {									\
-    if (TARGET_ELF) { if (!flag_inhibit_size_directive)			\
-      {									\
-	fprintf (FILE, "%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, (FNAME));					\
-        fprintf (FILE, ",.-");						\
-	assemble_name (FILE, (FNAME));					\
-	putc ('\n', FILE);						\
-      }	}								\
-  } while (0)
-
-#undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    if (TARGET_ELF) {							\
-      fprintf (FILE, "%s\t ", TYPE_ASM_OP);				\
-      assemble_name (FILE, NAME);					\
-      putc (',', FILE);							\
-      fprintf (FILE, TYPE_OPERAND_FMT, "object");			\
-      putc ('\n', FILE);						\
-      size_directive_output = 0;					\
-      if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-        {								\
-  	size_directive_output = 1;					\
-	fprintf (FILE, "%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-	fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));	\
-        }								\
-      ASM_OUTPUT_LABEL(FILE, NAME);					\
-    } else								\
-      SCO_DEFAULT_ASM_COFF(FILE, NAME);					\
-  } while (0)
-
-#undef ASM_FILE_START_1
-#define ASM_FILE_START_1(FILE)
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)						\
-do {									\
-  output_file_directive((FILE),main_input_filename);			\
-  fprintf ((FILE), "\t.version\t\"01.01\"\n");				\
-} while (0)
-
-#undef ASM_FILE_END
-#define ASM_FILE_END(FILE)						\
-do {									\
-  fprintf ((FILE), "%s\t\"GCC: (GNU) %s\"\n",				\
-    IDENT_ASM_OP, version_string);					\
-} while (0)
-
-#undef ASM_FINISH_DECLARE_OBJECT
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-  if (TARGET_ELF) {							\
-     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 fprintf (FILE, "%s\t ", SIZE_ASM_OP);			 	 \
-	 assemble_name (FILE, name);					 \
-	 fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL))); \
-       }								 \
-    }									 \
-} while (0)
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)			\
-do {									\
-  if (TARGET_ELF)							\
-    sprintf (LABEL, "*.%s%d", (PREFIX), (NUM));				\
-  else									\
-    sprintf (LABEL, ".%s%d", (PREFIX), (NUM));				\
-} while (0)
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-do {									\
-  if (TARGET_ELF)							\
-    fprintf (FILE, "%s _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", ASM_LONG, LPREFIX, VALUE); \
-  else									\
-    fprintf (FILE, "\t.word %s%d-%s%d\n", LPREFIX,VALUE,LPREFIX,REL);	\
-} while (0)
-
-#undef ASM_OUTPUT_ALIGNED_COMMON
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fprintf ((FILE), "%s\t", COMMON_ASM_OP);				\
-  assemble_name ((FILE), (NAME));					\
-  if (TARGET_ELF)							\
-    fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
-  else									\
-    fprintf ((FILE), ",%u\n", (SIZE));					\
-} while (0)
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  if (TARGET_ELF) {							\
-    fprintf ((FILE), "%s\t", LOCAL_ASM_OP);				\
-    assemble_name ((FILE), (NAME));					\
-    fprintf ((FILE), "\n");						\
-    ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);		\
-  } else {								\
-    int align = exact_log2 (ALIGN);					\
-    if (align > 2) align = 2;						\
-    if (TARGET_SVR3_SHLIB)						\
-      data_section ();							\
-    else								\
-      bss_section ();							\
-    ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align);			\
-    fprintf ((FILE), "%s\t", "\t.lcomm");				\
-    assemble_name ((FILE), (NAME));					\
-    fprintf ((FILE), ",%u\n", (SIZE));					\
-   }									\
-} while (0)
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of uninitialized global DECL named
-   NAME whose size is SIZE bytes and alignment is ALIGN bytes.
-   Try to use asm_output_aligned_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
-
-#undef ESCAPES
-#define ESCAPES \
-"\1\1\1\1\1\1\1\1btn\1fr\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\0\0\"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
-\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\\\0\0\0\
-\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1"
-
-#undef STRING_LIMIT
-#define STRING_LIMIT	((unsigned) 256)
-
-#undef ASM_OUTPUT_LIMITED_STRING
-#define ASM_OUTPUT_LIMITED_STRING(FILE, STR)				\
-  do									\
-    {									\
-      register unsigned char *_limited_str = (unsigned char *) (STR);	\
-      register unsigned ch;						\
-      fprintf ((FILE), "%s\t\"", STRING_ASM_OP);			\
-      for (; (ch = *_limited_str); _limited_str++)			\
-        {								\
-	  register int escape;						\
-	  switch (escape = ESCAPES[ch])					\
-	    {								\
-	    case 0:							\
-	      putc (ch, (FILE));					\
-	      break;							\
-	    case 1:							\
-	      fprintf ((FILE), "\\%03o", ch);				\
-	      break;							\
-	    default:							\
-	      putc ('\\', (FILE));					\
-	      putc (escape, (FILE));					\
-	      break;							\
-	    }								\
-        }								\
-      fprintf ((FILE), "\"\n");						\
-    }									\
-  while (0)
-
-
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH)				\
-do {									\
-      register unsigned char *_ascii_bytes = (unsigned char *) (STR);	\
-      register unsigned char *limit = _ascii_bytes + (LENGTH);		\
-      register unsigned bytes_in_chunk = 0;				\
-      for (; _ascii_bytes < limit; _ascii_bytes++)			\
-        {								\
-	  register unsigned char *p;					\
-	  if (bytes_in_chunk >= 64)					\
-	    {								\
-	      fputc ('\n', (FILE));					\
-	      bytes_in_chunk = 0;					\
-	    }								\
-	  for (p = _ascii_bytes; p < limit && *p != '\0'; p++)		\
-	    continue;							\
-	  if (p < limit && (p - _ascii_bytes) <= STRING_LIMIT)		\
-	    {								\
-	      if (bytes_in_chunk > 0)					\
-		{							\
-		  fputc ('\n', (FILE));					\
-		  bytes_in_chunk = 0;					\
-		}							\
-	      ASM_OUTPUT_LIMITED_STRING ((FILE), _ascii_bytes);		\
-	      _ascii_bytes = p;						\
-	    }								\
-	  else								\
-	    {								\
-	      if (bytes_in_chunk == 0)					\
-		fprintf ((FILE), "%s\t", ASM_BYTE_OP);			\
-	      else							\
-		fputc (',', (FILE));					\
-	      fprintf ((FILE), "0x%02x", *_ascii_bytes);		\
-	      bytes_in_chunk += 5;					\
-	    }								\
-	}								\
-      if (bytes_in_chunk > 0)						\
-        fprintf ((FILE), "\n");						\
-} while (0) 
-
-/* Must use data section for relocatable constants when pic.  */
-#undef SELECT_RTX_SECTION
-#define SELECT_RTX_SECTION(MODE,RTX)					\
-{									\
-  if (TARGET_ELF) {							\
-    if (flag_pic && symbolic_operand (RTX))				\
-      data_section ();							\
-    else								\
-      const_section ();							\
-  } else								\
-    readonly_data_section();						\
-}
-
-#undef ASM_OUTPUT_CASE_LABEL
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,JUMPTABLE)		\
-do {									\
-  if (TARGET_ELF)							\
-    ASM_OUTPUT_ALIGN ((FILE), 2);					\
-  ASM_OUTPUT_INTERNAL_LABEL((FILE),(PREFIX),(NUM));			\
-} while (0)
-
-
-#undef ASM_OUTPUT_CONSTRUCTOR
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-do {									\
-  if (TARGET_ELF) {							\
-     ctors_section ();							\
-     fprintf (FILE, "%s\t ", INT_ASM_OP);				\
-     assemble_name (FILE, NAME);					\
-     fprintf (FILE, "\n");						\
-  } else {								\
-    init_section ();							\
-    fprintf (FILE, "\tpushl $");					\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n"); }						\
-  } while (0)
-
-#undef ASM_OUTPUT_DESTRUCTOR
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)				\
-do {									\
-  if (TARGET_ELF) {							\
-    dtors_section ();                   				\
-    fprintf (FILE, "%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } else {								\
-    fini_section ();                   					\
-    fprintf (FILE, "%s\t ", ASM_LONG);					\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n"); }						\
-  } while (0)
-
-
-#undef ASM_OUTPUT_IDENT
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  fprintf (FILE, "%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
-
-#undef ASM_GLOBALIZE_LABEL
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  (fprintf ((FILE), "%s ", GLOBAL_ASM_OP), assemble_name (FILE, NAME), fputs ("\n", FILE))
-
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN)				\
-  if (TARGET_ELF) ASM_GLOBALIZE_LABEL (FILE, XSTR (FUN, 0))
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)			\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-
-/* 
- * Compensate for the difference between ELF and COFF assembler syntax.
- * Otherwise, this is cribbed from ../svr4.h.
- * We rename 'gcc_except_table' to the shorter name in preparation
- * for the day when we're ready to do DWARF2 eh unwinding under COFF 
- */
-#undef ASM_OUTPUT_SECTION_NAME
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
-do {									\
-  static struct section_info                                            \
-    {                                                                   \
-      struct section_info *next;                                        \
-      char *name;                                                       \
-      enum sect_enum {SECT_RW, SECT_RO, SECT_EXEC} type;                \
-    } *sections;                                                        \
-  struct section_info *s;                                               \
-  char *mode;                                                           \
-  enum sect_enum type;                                                  \
-  char *sname = NAME ;							\
-  if (strcmp(NAME, ".gcc_except_table") == 0) sname = ".gccexc" ;	\
-                                                                        \
-  for (s = sections; s; s = s->next)                                    \
-    if (!strcmp (NAME, s->name))                                        \
-      break;                                                            \
-                                                                        \
-  if (DECL && TREE_CODE (DECL) == FUNCTION_DECL)                        \
-    type = SECT_EXEC, mode = (TARGET_ELF) ? "ax" : "x" ;                \
-  else if (DECL && DECL_READONLY_SECTION (DECL, RELOC))                 \
-    type = SECT_RO, mode = "a";                                         \
-  else                                                                  \
-    type = SECT_RW, mode = (TARGET_ELF) ? "aw" : "w" ;                  \
-                                                                        \
-  if (s == 0)                                                           \
-    {                                                                   \
-      s = (struct section_info *) xmalloc (sizeof (struct section_info));  \
-      s->name = xmalloc ((strlen (NAME) + 1) * sizeof (*NAME));         \
-      strcpy (s->name, NAME);                                           \
-      s->type = type;                                                   \
-      s->next = sections;                                               \
-      sections = s;                                                     \
-      fprintf (FILE, ".section\t%s,\"%s\"%s\n", sname, mode,		\
-		(TARGET_ELF) ? ",@progbits" : "" );    			\
-    }                                                                   \
-  else                                                                  \
-    {                                                                   \
-      if (DECL && s->type != type)                                      \
-        error_with_decl (DECL, "%s causes a section type conflict");    \
-                                                                        \
-      fprintf (FILE, ".section\t%s\n", sname);                          \
-    }                                                                   \
-} while (0)
-
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
-do {									\
-  if (TARGET_ELF)							\
-    fprintf (FILE, "%s\t%u\n", SKIP_ASM_OP, (SIZE));			\
-  else									\
-    fprintf ((FILE), "%s\t.,.+%u\n", SET_ASM_OP, (SIZE));		\
-} while (0)
-
-
-#undef CTOR_LIST_BEGIN
-#define CTOR_LIST_BEGIN							\
-do {									\
-  asm (CTORS_SECTION_ASM_OP);						\
-  if (TARGET_ELF)							\
-    STATIC func_ptr __CTOR_LIST__[1] = { (func_ptr) (-1) };		\
-  else									\
-    asm ("pushl $0");							\
-} while (0)
-
-#undef CTOR_LIST_END
-#define CTOR_LIST_END							\
-do {									\
-  if (TARGET_ELF) {							\
-    asm (CTORS_SECTION_ASM_OP);						\
-    STATIC func_ptr __CTOR_LIST__[1] = { (func_ptr) (0) };		\
-  } else {								\
-    CTOR_LIST_BEGIN;							\
-  }									\
-} while (0)
-
-#undef DBX_BLOCKS_FUNCTION_RELATIVE
-#define DBX_BLOCKS_FUNCTION_RELATIVE 1
-
-#undef DBX_FUNCTION_FIRST
-#define DBX_FUNCTION_FIRST 1
-
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n)						\
-((TARGET_ELF) ?								\
- ((n) == 0 ? 0 								\
-  : (n) == 1 ? 2 							\
-  : (n) == 2 ? 1 							\
-  : (n) == 3 ? 3 							\
-  : (n) == 4 ? 6 							\
-  : (n) == 5 ? 7 							\
-  : (n) == 6 ? 5 							\
-  : (n) == 7 ? 4 							\
-  : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 		\
-  : (-1))								\
- :									\
- ((n) == 0 ? 0 : 							\
-  (n) == 1 ? 2 : 							\
-  (n) == 2 ? 1 : 							\
-  (n) == 3 ? 3 : 							\
-  (n) == 4 ? 6 : 							\
-  (n) == 5 ? 7 : 							\
-  (n) == 6 ? 4 : 							\
-  (n) == 7 ? 5 : 							\
-  (n) + 4))
-
-#undef DWARF_DEBUGGING_INFO
-#undef SDB_DEBUGGING_INFO
-#undef DBX_DEBUGGING_INFO
-#undef PREFERRED_DEBUGGING_TYPE
-
-#define DWARF_DEBUGGING_INFO 1
-#define SDB_DEBUGGING_INFO   1
-#define DBX_DEBUGGING_INFO   1
-#define PREFERRED_DEBUGGING_TYPE					\
-  ((TARGET_ELF) ? DWARF_DEBUG: SDB_DEBUG)
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_init, in_fini, in_ctors, in_dtors
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CONST_SECTION_FUNCTION						\
-  INIT_SECTION_FUNCTION							\
-  FINI_SECTION_FUNCTION							\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-#undef CONST_SECTION_FUNCTION
-#define CONST_SECTION_FUNCTION						\
-void									\
-const_section ()							\
-{									\
-  extern void text_section();						\
-  if (!USE_CONST_SECTION)						\
-    text_section();							\
-  else if (in_section != in_const)					\
-    {									\
-      fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP);		\
-      in_section = in_const;						\
-    }									\
-}
-
-#undef FINI_SECTION_FUNCTION
-#define FINI_SECTION_FUNCTION						\
-void									\
-fini_section ()								\
-{									\
-  if ((!TARGET_ELF) && in_section != in_fini)				\
-    {									\
-      fprintf (asm_out_file, "%s\n", FINI_SECTION_ASM_OP);		\
-      in_section = in_fini;						\
-    }									\
-}
-
-#undef INIT_SECTION_FUNCTION
-#define INIT_SECTION_FUNCTION						\
-void									\
-init_section ()								\
-{									\
-  if ((!TARGET_ELF) && in_section != in_init)				\
-    {									\
-      fprintf (asm_out_file, "%s\n", INIT_SECTION_ASM_OP);		\
-      in_section = in_init;						\
-    }									\
-}
-
-#undef CTORS_SECTION_FUNCTION
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#undef DTORS_SECTION_FUNCTION
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-#undef FRAME_POINTER_REQUIRED
-#define FRAME_POINTER_REQUIRED						\
-  ((TARGET_ELF) ? 0 : 							\
-   (current_function_calls_setjmp || current_function_calls_longjmp))
-
-#undef JUMP_TABLES_IN_TEXT_SECTION
-#define JUMP_TABLES_IN_TEXT_SECTION (TARGET_ELF && flag_pic)
-
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX						\
- ((TARGET_ELF) ? "" : ".")
-
-#undef MD_EXEC_PREFIX
-#undef MD_STARTFILE_PREFIX
-#define MD_EXEC_PREFIX "/usr/ccs/bin/"
-#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
-
-#undef NON_SAVING_SETJMP
-#define NON_SAVING_SETJMP						\
-  ((TARGET_ELF) ? 0 : 							\
-   (current_function_calls_setjmp && current_function_calls_longjmp))
-
-#undef NO_IMPLICIT_EXTERN_C
-#define NO_IMPLICIT_EXTERN_C 1
-
-/* JKJ FIXME - examine the ramifications of RETURN_IN_MEMORY and
-   RETURN_POPS_ARGS */
-
-#undef RETURN_POPS_ARGS
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 				\
- ((TARGET_ELF) ?							\
-  (i386_return_pops_args (FUNDECL, FUNTYPE, SIZE)) : 			\
-  (((FUNDECL) && (TREE_CODE (FUNDECL) == IDENTIFIER_NODE)) ? 0		\
-   : (TARGET_RTD							\
-      && (TYPE_ARG_TYPES (FUNTYPE) == 0					\
-	  || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE)))		\
-	      == void_type_node))) ? (SIZE)				\
-   : 0))
-
-#undef SELECT_SECTION
-#define SELECT_SECTION(DECL,RELOC)					\
-{									\
-  if (TARGET_ELF && flag_pic && RELOC)					\
-     data_section ();							\
-  else if (TREE_CODE (DECL) == STRING_CST)				\
-    {									\
-      if (! flag_writable_strings)					\
-	const_section ();						\
-      else								\
-	data_section ();						\
-    }									\
-  else if (TREE_CODE (DECL) == VAR_DECL)				\
-    {									\
-      if (! DECL_READONLY_SECTION (DECL, RELOC)) 			\
-	data_section ();						\
-      else								\
-	const_section ();						\
-    }									\
-  else									\
-    const_section ();							\
-}
-
-#undef SWITCH_TAKES_ARG
-#define SWITCH_TAKES_ARG(CHAR) 						\
-  (DEFAULT_SWITCH_TAKES_ARG(CHAR)					\
-   || (CHAR) == 'h' 							\
-   || (CHAR) == 'R' 							\
-   || (CHAR) == 'Y' 							\
-   || (CHAR) == 'z')
-
-#undef WORD_SWITCH_TAKES_ARG
-#define WORD_SWITCH_TAKES_ARG(STR)					\
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR)					\
-  && strcmp (STR, "Tdata") && strcmp (STR, "Ttext")			\
-  && strcmp (STR, "Tbss"))
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS)
-
-#undef HANDLE_SYSV_PRAGMA
-#define HANDLE_SYSV_PRAGMA 1
-
-/* Though OpenServer support .weak in COFF, g++ doesn't play nice with it
- * so we'll punt on it for now
- */
-#define SUPPORTS_WEAK (TARGET_ELF)
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
-  do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME);		\
-	fputc ('\n', FILE); } while (0)
-
-#undef SCCS_DIRECTIVE
-#define SCCS_DIRECTIVE 1
-
-/*
- * Define sizes and types
- */
-#undef SIZE_TYPE
-#undef PTRDIFF_TYPE
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 	96
-#define SIZE_TYPE		"unsigned int"
-#define PTRDIFF_TYPE		"int"
-#define WCHAR_TYPE		"long int"
-#define WCHAR_TYPE_SIZE		BITS_PER_WORD
-
-/*
- * New for multilib support. Set the default switches for multilib,
- * which is -melf.
- */
-#define MULTILIB_DEFAULTS { "melf" }
-
-
-/* Please note that these specs may look messy but they are required in
-   order to emulate the SCO Development system as closely as possible.
-   With SCO Open Server 5.0, you now get the linker and assembler free,
-   so that is what these specs are targeted for. These utilities are
-   very argument sensitive: a space in the wrong place breaks everything.
-   So RMS, please forgive this mess. It works.
-
-   Parameters which can be passed to gcc, and their SCO equivalents:
-   GCC Parameter                SCO Equivalent
-   -ansi                        -a ansi
-   -posix                       -a posix
-   -Xpg4                        -a xpg4
-   -Xpg4plus                    -a xpg4plus
-   -Xods30                      -a ods30
-
-   As with SCO, the default is XPG4 plus mode. SCO also allows you to
-   specify a C dialect with -Xt, -Xa, -Xc, -Xk and -Xm. These are passed
-   on to the assembler and linker in the same way that the SCO compiler
-   does.
-
-   SCO also allows you to compile, link and generate either ELF or COFF
-   binaries. With gcc, unlike the SCO compiler, the default is ELF.
-   Specify -mcoff to gcc to produce COFF binaries. -fpic will get the
-   assembler and linker to produce PIC code.
-*/
-
-/* Set up assembler flags for PIC and ELF compilations */
-#undef ASM_SPEC
-
-#if USE_GAS
-  /* Leave ASM_SPEC undefined so we pick up the master copy from gcc.c 
-   * Undef MD_EXEC_PREFIX becuase we don't know where GAS is, but it's not
-   * likely in /usr/ccs/bin/ 
-   */
-#undef MD_EXEC_PREFIX 
-#else
-
-#define ASM_SPEC \
-   "-b %{!mcoff:elf}%{mcoff:coff \
-     %{static:%e-static not valid with -mcoff} \
-     %{shared:%e-shared not valid with -mcoff} \
-     %{symbolic:%e-symbolic not valid with -mcoff}} \
-    %{Ym,*} %{Yd,*} %{Wa,*:%*} \
-    %{!mcoff:-E%{Xa:a}%{!Xa:%{Xc:c}%{!Xc:%{Xk:k}%{!Xk:%{Xt:t}%{!Xt:a}}}},%{ansi:ansi}%{!ansi:%{posix:posix}%{!posix:%{Xpg4:xpg4}%{!Xpg4:%{Xpg4plus:XPG4PLUS}%{!Xpg4plus:%{Xods30:ods30}%{!Xods30:XPG4PLUS}}}}},ELF %{Qn:} %{!Qy:-Qn}}"
-#endif
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
- "%{!shared:\
-   %{!symbolic: \
-    %{pg:gcrt.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}} \
-  %{ansi:values-Xc.o%s} \
-  %{!ansi: \
-   %{traditional:values-Xt.o%s} \
-    %{!traditional: \
-     %{Xa:values-Xa.o%s} \
-      %{!Xa:%{Xc:values-Xc.o%s} \
-       %{!Xc:%{Xk:values-Xk.o%s} \
-        %{!Xk:%{Xt:values-Xt.o%s} \
-         %{!Xt:values-Xa.o%s}}}}}} \
-  %{mcoff:crtbeginS.o%s} %{!mcoff:crtbegin.o%s}"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC \
- "%{!mcoff:crtend.o%s} \
-  %{mcoff:crtendS.o%s} \
-  %{pg:gcrtn.o%s}%{!pg:crtn.o%s}"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-Asystem(svr3)"
-
-/* You are in a maze of GCC specs ... all alike */
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) \
-  %{fpic:%{mcoff:%e-fpic is not valid with -mcoff}} \
-  %{fPIC:%{mcoff:%e-fPIC is not valid with -mcoff}} \
-  -D__i386 -D__unix -D_SCO_DS=1 -D_M_I386 -D_M_XENIX -D_M_UNIX \
-  %{!Xods30:-D_STRICT_NAMES} \
-  %{!ansi:%{!posix:%{!Xods30:-D_SCO_XPG_VERS=4}}} \
-  %{ansi:-isystem include/ansi%s -isystem /usr/include/ansi -D_STRICT_ANSI} \
-  %{!ansi: \
-   %{posix:-isystem include/posix%s -isystem /usr/include/posix \
-           -D_POSIX_C_SOURCE=2 -D_POSIX_SOURCE=1} \
-    %{!posix:%{Xpg4:-isystem include/xpg4%s -isystem /usr/include/xpg4 \
-                    -D_XOPEN_SOURCE=1} \
-     %{!Xpg4:-D_M_I86 -D_M_I86SM -D_M_INTERNAT -D_M_SDATA -D_M_STEXT \
-             -D_M_BITFIELDS -D_M_SYS5 -D_M_SYSV -D_M_SYSIII \
-             -D_M_WORDSWAP -Dunix -DM_I386 -DM_UNIX -DM_XENIX \
-             %{Xods30:-isystem include/ods_30_compat%s \
-                      -isystem /usr/include/ods_30_compat \
-                      -D_SCO_ODS_30 -DM_I86 -DM_I86SM -DM_SDATA -DM_STEXT \
-                      -DM_BITFIELDS -DM_SYS5 -DM_SYSV -DM_INTERNAT -DM_SYSIII \
-                      -DM_WORDSWAP}}}} \
-  %{scointl:-DM_INTERNAT -D_M_INTERNAT} \
-  %{traditional:-D_KR -D_SVID -D_NO_PROTOTYPE} \
-  %{!mcoff:-D_SCO_ELF} \
-  %{mcoff:-D_M_COFF -D_SCO_COFF} \
-  %{!mcoff:%{fpic:-D__PIC__ -D__pic__} \
-         %{fPIC:%{!fpic:-D__PIC__ -D__pic__}}} \
-  %{Xa:-D_SCO_C_DIALECT=1} \
-  %{!Xa:%{Xc:-D_SCO_C_DIALECT=3} \
-   %{!Xc:%{Xk:-D_SCO_C_DIALECT=4} \
-    %{!Xk:%{Xt:-D_SCO_C_DIALECT=2} \
-     %{!Xt:-D_SCO_C_DIALECT=1}}}} \
-  %{traditional:-traditional -D_KR -D_NO_PROTOTYPE}"
-
-#undef LINK_SPEC
-#define LINK_SPEC \
- "-b %{!mcoff:elf}%{mcoff:coff \
-   %{static:%e-static not valid with -mcoff} \
-   %{shared:%e-shared not valid with -mcoff} \
-   %{symbolic:%e-symbolic not valid with -mcoff} \
-   %{fpic:%e-fpic not valid with -mcoff} \
-   %{fPIC:%e-fPIC not valid with -mcoff}} \
-  -R%{Xa:a}%{!Xa:%{Xc:c}%{!Xc:%{Xk:k}%{!Xk:%{Xt:t}%{!Xt:a}}}},%{ansi:ansi}%{!ansi:%{posix:posix}%{!posix:%{Xpg4:xpg4}%{!Xpg4:%{Xpg4plus:XPG4PLUS}%{!Xpg4plus:%{Xods30:ods30}%{!Xods30:XPG4PLUS}}}}},%{mcoff:COFF}%{!mcoff:ELF} \
-  %{Wl,*%*} %{YP,*} %{YL,*} %{YU,*} \
-  %{!YP,*:%{p:-YP,/usr/ccs/libp:/lib/libp:/usr/lib/libp:/usr/ccs/lib:/lib:/usr/lib} \
-   %{!p:-YP,/usr/ccs/lib:/lib:/usr/lib}} \
-  %{h*} %{static:-dn -Bstatic} %{shared:-G -dy %{!z*:-z text}} \
-  %{symbolic:-Bsymbolic -G -dy %{!z*:-z text}} %{z*} %{R*} %{Y*} \
-  %{G:-G} %{!mcoff:%{Qn:} %{!Qy:-Qn}}"
-
-/* The SCO COFF linker gets confused on the difference between "-ofoo"
-   and "-o foo".   So we just always force a single space. */
-
-#define SWITCHES_NEED_SPACES "o"
-
-/* Library spec. If we are not building a shared library, provide the
-   standard libraries, as per the SCO compiler.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC \
- "%{shared:pic/libgcc.a%s}%{!shared:%{!symbolic:-lcrypt -lgen -lc}}"
-
-#undef LIBGCC_SPEC
-#define LIBGCC_SPEC \
- "%{!shared:-lgcc}"
-
-#define MASK_COFF     		010000000000	/* Mask for elf generation */
-#define TARGET_COFF             (target_flags & MASK_COFF)
-#define TARGET_ELF              (!(target_flags & MASK_COFF))
-
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES 		\
-	{ "coff", MASK_COFF, "Generate COFF output" }, 		\
-	{ "elf", -MASK_COFF, "Generate ELF output"  },
-
-#define NO_DOLLAR_IN_LABEL
-
-/* Implicit library calls should use memcpy, not bcopy, etc.  They are 
-   faster on OpenServer libraries. */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Biggest alignment supported by the object file format of this
-   machine.  Use this macro to limit the alignment which can be
-   specified using the `__attribute__ ((aligned (N)))' construct.  If
-   not defined, the default value is `BIGGEST_ALIGNMENT'.  */
-
-#define MAX_OFILE_ALIGNMENT (32768*8)
-
-/*
-Here comes some major hackery to get the crt stuff to compile properly.
-Since we can (and do) compile for both COFF and ELF environments, we
-set things up accordingly, based on the pre-processor defines for ELF
-and COFF. This is insane, but then I guess having one compiler with a
-single back-end supporting two vastly different file format types is
-a little insane too. But it is not impossible and we get a useful
-compiler at the end of the day. Onward we go ...
-*/
-
-#if defined(CRT_BEGIN) || defined(CRT_END) || defined(IN_LIBGCC2)
-# undef OBJECT_FORMAT_ELF
-# undef HAVE_ATEXIT
-# undef INIT_SECTION_ASM_OP
-# undef FINI_SECTION_ASM_OP
-# undef CTORS_SECTION_ASM_OP
-# undef DTORS_SECTION_ASM_OP
-# undef EH_FRAME_SECTION_ASM_OP
-# undef CTOR_LIST_BEGIN
-# undef CTOR_LIST_END
-# undef DO_GLOBAL_CTORS_BODY
-
-# if defined (_SCO_ELF)
-#  define OBJECT_FORMAT_ELF
-#  define HAVE_ATEXIT 1
-#  define INIT_SECTION_ASM_OP INIT_SECTION_ASM_OP_ELF
-#  define FINI_SECTION_ASM_OP FINI_SECTION_ASM_OP_ELF
-#  define DTORS_SECTION_ASM_OP DTORS_SECTION_ASM_OP_ELF
-#  define CTORS_SECTION_ASM_OP CTORS_SECTION_ASM_OP_ELF
-#  define EH_FRAME_SECTION_ASM_OP EH_FRAME_SECTION_ASM_OP_ELF
-# else /* ! _SCO_ELF */
-#  define INIT_SECTION_ASM_OP INIT_SECTION_ASM_OP_COFF
-#  define FINI_SECTION_ASM_OP FINI_SECTION_ASM_OP_COFF
-#  define DTORS_SECTION_ASM_OP DTORS_SECTION_ASM_OP_COFF
-#  define CTORS_SECTION_ASM_OP CTORS_SECTION_ASM_OP_COFF
-#  define EH_FRAME_SECTION_ASM_OP ""
-#  define CTOR_LIST_BEGIN asm (INIT_SECTION_ASM_OP); asm ("pushl $0")
-#  define CTOR_LIST_END CTOR_LIST_BEGIN
-#  define DO_GLOBAL_CTORS_BODY						\
-do {									\
-     func_ptr *p, *beg = alloca(0);					\
-     for (p = beg; *p;)							\
-      (*p++) ();							\
-} while (0)
-# endif /* ! _SCO_ELF */
-#endif /* CRT_BEGIN !! CRT_END */
diff --git a/gcc/config/i386/sco5gas.h b/gcc/config/i386/sco5gas.h
deleted file mode 100755
index de3e5d5..0000000
--- a/gcc/config/i386/sco5gas.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Definitions for Intel x86 running SCO OpenServer, running GNU assembler
-   Copyright (C) 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Just set a single flag we can test for inside of sco5.h and include it. */
-
-#define USE_GAS 1
diff --git a/gcc/config/i386/scodbx.h b/gcc/config/i386/scodbx.h
deleted file mode 100755
index d7d03f8..0000000
--- a/gcc/config/i386/scodbx.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Definitions for Intel 386 running SCO Unix System V,
-   using dbx-in-coff encapsulation.
-   Copyright (C) 1992, 1995, 1996, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/svr3dbx.h"
-
-/* Overridden defines for SCO systems from sco.h. */
-
-/* By default, target has a 80387, uses IEEE compatible arithmetic,
-   and returns float values in the 387, ie,
-   (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387)
-
-   SCO's software emulation of a 387 fails to handle the `fucomp'
-   opcode.  fucomp is only used when generating IEEE compliant code.
-   So don't make TARGET_IEEE_FP default for SCO. */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_80387 | MASK_FLOAT_RETURNS)
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{!r:%{!z:svr3.ifile%s}%{z:svr3z.ifile%s}}\
-   %{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
-
-/* Library spec, including SCO international language support. */
-
-#undef LIB_SPEC
-#define LIB_SPEC \
- "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} %{scointl:libintl.a%s} -lc"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -DM_UNIX -DM_I386 -DM_COFF -DM_WORDSWAP -Asystem(svr3)"
-
-#undef CPP_SPEC
-#define CPP_SPEC " -Acpu(i386) -Amachine(i386) %{scointl:-DM_INTERNAT}"
-
-/* This spec is used for telling cpp whether char is signed or not.  */
-
-#undef SIGNED_CHAR_SPEC
-#if DEFAULT_SIGNED_CHAR
-#define SIGNED_CHAR_SPEC \
- "%{funsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}"
-#else
-#define SIGNED_CHAR_SPEC \
- "%{!fsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}"
-#endif
-
-/* Use atexit for static destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
-/* caller has to pop the extra argument passed to functions that return
-   structures. */
-
-#undef RETURN_POPS_ARGS
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE)   \
-  ((FUNDECL) && TREE_CODE (FUNDECL) == IDENTIFIER_NODE ? 0	\
-   : (TARGET_RTD						\
-      && (TYPE_ARG_TYPES (FUNTYPE) == 0				\
-	  || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE)))	\
-	      == void_type_node))) ? (SIZE)			\
-   : 0)
-/* On other 386 systems, the last line looks like this:
-   : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0)  */
-
-/* Use periods rather than dollar signs in special g++ assembler names.  */
-
-#define NO_DOLLAR_IN_LABEL
-
-/* Handle #pragma pack. */
-#define HANDLE_SYSV_PRAGMA
diff --git a/gcc/config/i386/seq-gas.h b/gcc/config/i386/seq-gas.h
deleted file mode 100755
index 796eaa2..0000000
--- a/gcc/config/i386/seq-gas.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Definitions for Sequent Intel 386 using GAS.
-   Copyright (C) 1992 Free Software Foundation, Inc.
-
-/* Mostly it's like a Sequent 386 without GAS. */
-
-#include "i386/sequent.h"
-
-/* A C statement or statements which output an assembler instruction
-   opcode to the stdio stream STREAM.  The macro-operand PTR is a
-   variable of type `char *' which points to the opcode name in its
-   "internal" form--the form that is written in the machine description.
-
-   GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic.
-   So use `repe' instead.  */
-
-#undef ASM_OUTPUT_OPCODE
-#define ASM_OUTPUT_OPCODE(STREAM, PTR)	\
-{									\
-  if ((PTR)[0] == 'r'							\
-      && (PTR)[1] == 'e'						\
-      && (PTR)[2] == 'p')						\
-    {									\
-      if ((PTR)[3] == 'z')						\
-	{								\
-	  fprintf (STREAM, "repe");					\
-	  (PTR) += 4;							\
-	}								\
-      else if ((PTR)[3] == 'n' && (PTR)[4] == 'z')			\
-	{								\
-	  fprintf (STREAM, "repne");					\
-	  (PTR) += 5;							\
-	}								\
-    }									\
-}
-
-/* Define macro used to output shift-double opcodes when the shift
-   count is in %cl.  Some assemblers require %cl as an argument;
-   some don't.
-
-   GAS requires the %cl argument, so override i386/unix.h. */
-
-#undef SHIFT_DOUBLE_OMITS_COUNT
-#define SHIFT_DOUBLE_OMITS_COUNT 0
-
-/* Print opcodes the way that GAS expects them. */
-#define GAS_MNEMONICS 1
diff --git a/gcc/config/i386/seq-sysv3.h b/gcc/config/i386/seq-sysv3.h
deleted file mode 100755
index 9e8388d..0000000
--- a/gcc/config/i386/seq-sysv3.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Sequent DYNIX/ptx 1.x (SVr3) */
-
-#include "i386/sysv3.h"
-
-/* Sequent Symmetry SVr3 doesn't have crtn.o; crt1.o doesn't work
-   but crt0.o does.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC  \
-"%{pg:gcrt0.o%s}\
- %{!pg:%{posix:%{p:mcrtp0.o%s}%{!p:crtp0.o%s}}\
-       %{!posix:%{p:mcrt0.o%s}%{!p:crt0.o%s}}} crtbegin.o%s\
- %{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp}"
-
-#undef LIB_SPEC
-#define LIB_SPEC \
-"%{posix:-lcposix}\
- %{shlib:-lc_s}\
- %{fshared-data:-lpps -lseq} -lc crtend.o%s"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{posix:-D_POSIX_SOURCE} -D_SEQUENT_=1"
-
-/* Although the .init section is used, it is not automatically invoked.
-   This because the _start() function in /lib/crt0.o never calls anything
-   from the .init section */
-#define INVOKE__main
-
-/* Assembler pseudo-op for initialized shared variables (.shdata). */
-#undef  SHARED_SECTION_ASM_OP
-#define SHARED_SECTION_ASM_OP ".section .shdata, \"ws\""
-
-/* Assembler pseudo-op for uninitialized shared global variables (.shbss). */
-#undef  ASM_OUTPUT_SHARED_COMMON
-#define ASM_OUTPUT_SHARED_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs(".comm ", (FILE)),			\
-  assemble_name((FILE), (NAME)),		\
-   fprintf((FILE), ",%u,-3\n", (SIZE)))
-
-/* Assembler pseudo-op for uninitialized shared local variables (.shbss). */
-#undef  SHARED_BSS_SECTION_ASM_OP
-#define SHARED_BSS_SECTION_ASM_OP ".section .shbss, \"bs\""
diff --git a/gcc/config/i386/seq2-sysv3.h b/gcc/config/i386/seq2-sysv3.h
deleted file mode 100755
index 763c5f0..0000000
--- a/gcc/config/i386/seq2-sysv3.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Sequent DYNIX/ptx 2.x (SVr3) */
-
-#include "i386/seq-sysv3.h"
-
-/* Use atexit for static destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
diff --git a/gcc/config/i386/sequent.h b/gcc/config/i386/sequent.h
deleted file mode 100755
index 8613ad7..0000000
--- a/gcc/config/i386/sequent.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/* Definitions for Sequent Intel 386.
-   Copyright (C) 1988, 1994, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/i386.h"
-
-/* Use the BSD assembler syntax.  */
-
-#include "i386/bsd.h"
-
-/* By default, don't use IEEE compatible arithmetic comparisons
-   because the assembler can't handle the fucom insn.
-   Return float values in the 387.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_80387 | MASK_FLOAT_RETURNS)
-
-/* Specify predefined symbols in preprocessor.  */
-
-#define CPP_PREDEFINES "-Dunix -Di386 -Dsequent -Asystem(unix) -Acpu(i386) -Amachine(i386)"
-
-/* Pass -Z and -ZO options to the linker.  */
-
-#define LINK_SPEC "%{Z*}"
-
-#if 0 /* Dynix 3.1 is said to accept -L.  */
-/* Dynix V3.0.12 doesn't accept -L at all.  */
-
-#define LINK_LIBGCC_SPECIAL
-#endif
-
-/* Link with libg.a when debugging, for dbx's sake.  */
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
-
-/* We don't want to output SDB debugging information.  */
-
-#undef SDB_DEBUGGING_INFO
-
-/* We want to output DBX debugging information.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Sequent Symmetry has size_t defined as int in /usr/include/sys/types.h */
-#define SIZE_TYPE "int"
-
-/* gcc order is ax, dx, cx, bx, si, di, bp, sp, st, st.
- * dbx order is ax, dx, cx, st(0), st(1), bx, si, di, st(2), st(3),
- * 		st(4), st(5), st(6), st(7), sp, bp  */
-
-/* ??? The right thing would be to change the ordering of the
-   registers to correspond to the conventions of this system,
-   and get rid of DBX_REGISTER_NUMBER.  */
-
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n)		\
-((n) < 3 ? (n) : (n) < 6 ? (n) + 2	\
- : (n) == 6 ? 15 : (n) == 7 ? 14 : 3)
-
-/* malcolmp@hydra.maths.unsw.EDU.AU says these two definitions
-   fix trouble in dbx.  */
-#undef DBX_OUTPUT_LBRAC
-#define DBX_OUTPUT_LBRAC(file,name)	\
-	      fprintf (asmfile, "%s %d,0,%d,", ASM_STABN_OP, N_LBRAC, depth); \
-	      assemble_name (asmfile, buf); \
-	      fprintf (asmfile, "\n");
-
-#undef DBX_OUTPUT_RBRAC
-#define DBX_OUTPUT_RBRAC(file,name)	\
-	      fprintf (asmfile, "%s %d,0,%d,", ASM_STABN_OP, N_RBRAC, depth); \
-	      assemble_name (asmfile, buf); \
-	      fprintf (asmfile, "\n");
-
-/* Prevent anything from being allocated in the register pair cx/bx,
-   since that would confuse GDB.  */
-
-#undef HARD_REGNO_MODE_OK
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-  (((REGNO) < 2 ? 1							\
-    : (REGNO) < 4 ? 1							\
-    : FP_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_FLOAT         \
-			    || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
-    : (MODE) != QImode)							\
-   && ! (REGNO == 2 && GET_MODE_UNIT_SIZE (MODE) > 4))
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry. */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   fprintf (FILE, "\tmovl $.LP%d,%%eax\n\tcall mcount\n", (LABELNO));
-
-/* Assembler pseudo-op for shared data segment. */
-#define SHARED_SECTION_ASM_OP ".shdata"
-
-/* A C statement or statements which output an assembler instruction
-   opcode to the stdio stream STREAM.  The macro-operand PTR is a
-   variable of type `char *' which points to the opcode name in its
-   "internal" form--the form that is written in the machine description.
-
-   The Sequent assembler (identified as "Balance 8000 Assembler
-   07/17/85 3.90" by "as -v") does not understand the `movs[bwl]' string
-   move mnemonics - it uses `smov[bwl]' instead.  Change "movs" into
-   "smov", carefully avoiding the sign-extend opcodes.  */
-
-#define ASM_OUTPUT_OPCODE(STREAM, PTR)	\
-{									\
-  if ((PTR)[0] == 'm'							\
-      && (PTR)[1] == 'o'						\
-      && (PTR)[2] == 'v'						\
-      && (PTR)[3] == 's'						\
-      && ((PTR)[4] == 'b' || (PTR)[4] == 'w' || (PTR)[4] == 'l')	\
-      && ((PTR)[5] == ' ' || (PTR)[5] == '\t'|| (PTR)[5] == '\0'))	\
-    {									\
-      fprintf (STREAM, "smov");						\
-      (PTR) += 4;							\
-    }									\
-}
-
-/* 10-Aug-92 pes  Local labels are prefixed with ".L" */
-#undef LPREFIX
-#define LPREFIX ".L"
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER)\
-  sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER))
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-/* The native compiler passes the address of the returned structure in eax. */
-#undef STRUCT_VALUE
-#undef STRUCT_VALUE_INCOMING
-#define STRUCT_VALUE_REGNUM	0
diff --git a/gcc/config/i386/sol2-c1.asm b/gcc/config/i386/sol2-c1.asm
deleted file mode 100755
index d08bcbd..0000000
--- a/gcc/config/i386/sol2-c1.asm
+++ /dev/null
@@ -1,156 +0,0 @@
-! crt1.s for Solaris 2, x86
-
-!   Copyright (C) 1993, 1998 Free Software Foundation, Inc.
-!   Written By Fred Fish, Nov 1992
-! 
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-! 
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file with other programs, and to distribute
-! those programs without any restriction coming from the use of this
-! file.  (The General Public License restrictions do apply in other
-! respects; for example, they cover modification of the file, and
-! distribution when not linked into another program.)
-! 
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-! General Public License for more details.
-! 
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING.  If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-! 
-!    As a special exception, if you link this library with files
-!    compiled with GCC to produce an executable, this does not cause
-!    the resulting executable to be covered by the GNU General Public License.
-!    This exception does not however invalidate any other reasons why
-!    the executable file might be covered by the GNU General Public License.
-! 
-
-! This file takes control of the process from the kernel, as specified
-! in section 3 of the System V Application Binary Interface, Intel386
-! Processor Supplement.  It has been constructed from information obtained
-! from the ABI, information obtained from single stepping existing
-! Solaris executables through their startup code with gdb, and from
-! information obtained by single stepping executables on other i386 SVR4
-! implementations.  This file is the first thing linked into any executable.
-
-	.file	"crt1.s"
-	.ident	"GNU C crt1.s"
-	.weak	_cleanup
-	.weak	_DYNAMIC
-	.text
-
-! Start creating the initial frame by pushing a NULL value for the return
-! address of the initial frame, and mark the end of the stack frame chain
-! (the innermost stack frame) with a NULL value, per page 3-32 of the ABI.
-! Initialize the first stack frame pointer in %ebp (the contents of which
-! are unspecified at process initialization).
-
-	.globl	_start
-_start:
-	pushl	$0x0
-	pushl	$0x0
-	movl	%esp,%ebp
-
-! As specified per page 3-32 of the ABI, %edx contains a function 
-! pointer that should be registered with atexit(), for proper
-! shared object termination.  Just push it onto the stack for now
-! to preserve it.  We want to register _cleanup() first.
-
-	pushl	%edx
-
-! Check to see if there is an _cleanup() function linked in, and if
-! so, register it with atexit() as the last thing to be run by
-! atexit().
-
-	movl	$_cleanup,%eax
-	testl	%eax,%eax
-	je	.L1
-	pushl	$_cleanup
-	call	atexit
-	addl	$0x4,%esp
-.L1:
-
-! Now check to see if we have an _DYNAMIC table, and if so then
-! we need to register the function pointer previously in %edx, but
-! now conveniently saved on the stack as the argument to pass to
-! atexit().
-
-	movl	$_DYNAMIC,%eax
-	testl	%eax,%eax
-	je	.L2
-	call	atexit
-.L2:
-
-! Register _fini() with atexit().  We will take care of calling _init()
-! directly.
-
-	pushl	$_fini
-	call	atexit
-
-! Compute the address of the environment vector on the stack and load
-! it into the global variable _environ.  Currently argc is at 8 off
-! the frame pointer.  Fetch the argument count into %eax, scale by the
-! size of each arg (4 bytes) and compute the address of the environment
-! vector which is 16 bytes (the two zero words we pushed, plus argc,
-! plus the null word terminating the arg vector) further up the stack,
-! off the frame pointer (whew!).
-
-	movl	8(%ebp),%eax
-	leal	16(%ebp,%eax,4),%edx
-	movl	%edx,_environ
-
-! Push the environment vector pointer, the argument vector pointer,
-! and the argument count on to the stack to set up the arguments
-! for _init(), _fpstart(), and main().  Note that the environment
-! vector pointer and the arg count were previously loaded into
-! %edx and %eax respectively.  The only new value we need to compute
-! is the argument vector pointer, which is at a fixed address off
-! the initial frame pointer.
-
-	pushl	%edx
-	leal	12(%ebp),%edx
-	pushl	%edx
-	pushl	%eax
-
-! Call _init(argc, argv, environ), _fpstart(argc, argv, environ), and
-! main(argc, argv, environ).
-
-	call	_init
-	call	__fpstart
-	call	main
-
-! Pop the argc, argv, and environ arguments off the stack, push the
-! value returned from main(), and call exit().
-
-	addl	$12,%esp
-	pushl	%eax
-	call	exit
-
-! An inline equivalent of _exit, as specified in Figure 3-26 of the ABI.
-
-	pushl	$0x0
-	movl	$0x1,%eax
-	lcall	$7,$0
-
-! If all else fails, just try a halt!
-
-	hlt
-	.type	_start,@function
-	.size	_start,.-_start
-
-! A dummy profiling support routine for non-profiling executables,
-! in case we link in some objects that have been compiled for profiling.
-
-	.weak	_mcount
-_mcount:
-	ret
-	.type	_mcount,@function
-	.size	_mcount,.-_mcount
diff --git a/gcc/config/i386/sol2-ci.asm b/gcc/config/i386/sol2-ci.asm
deleted file mode 100755
index 439c709..0000000
--- a/gcc/config/i386/sol2-ci.asm
+++ /dev/null
@@ -1,51 +0,0 @@
-! crti.s for Solaris 2, x86.
-
-!   Copyright (C) 1993 Free Software Foundation, Inc.
-!   Written By Fred Fish, Nov 1992
-! 
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-! 
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file with other programs, and to distribute
-! those programs without any restriction coming from the use of this
-! file.  (The General Public License restrictions do apply in other
-! respects; for example, they cover modification of the file, and
-! distribution when not linked into another program.)
-! 
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-! General Public License for more details.
-! 
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING.  If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-! 
-!    As a special exception, if you link this library with files
-!    compiled with GCC to produce an executable, this does not cause
-!    the resulting executable to be covered by the GNU General Public License.
-!    This exception does not however invalidate any other reasons why
-!    the executable file might be covered by the GNU General Public License.
-! 
-
-! This file just supplies labeled starting points for the .init and .fini
-! sections.  It is linked in before the values-Xx.o files and also before
-! crtbegin.o.
- 
-	.file	"crti.s"
-	.ident	"GNU C crti.s"
-
-	.section .init
-	.globl	_init
-	.type	_init,@function
-_init:
-
-	.section .fini
-	.globl	_fini
-	.type	_fini,@function
-_fini:
diff --git a/gcc/config/i386/sol2-cn.asm b/gcc/config/i386/sol2-cn.asm
deleted file mode 100755
index 3f3bad9..0000000
--- a/gcc/config/i386/sol2-cn.asm
+++ /dev/null
@@ -1,46 +0,0 @@
-! crtn.s for Solaris 2, x86.
-
-!   Copyright (C) 1993 Free Software Foundation, Inc.
-!   Written By Fred Fish, Nov 1992
-! 
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-! 
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file with other programs, and to distribute
-! those programs without any restriction coming from the use of this
-! file.  (The General Public License restrictions do apply in other
-! respects; for example, they cover modification of the file, and
-! distribution when not linked into another program.)
-! 
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-! General Public License for more details.
-! 
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING.  If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-! 
-!    As a special exception, if you link this library with files
-!    compiled with GCC to produce an executable, this does not cause
-!    the resulting executable to be covered by the GNU General Public License.
-!    This exception does not however invalidate any other reasons why
-!    the executable file might be covered by the GNU General Public License.
-! 
-
-! This file just supplies returns for the .init and .fini sections.  It is
-! linked in after all other files.
-
-	.file	"crtn.o"
-	.ident	"GNU C crtn.o"
-
-	.section .init
-	ret    $0x0
-
-	.section .fini
-	ret    $0x0
diff --git a/gcc/config/i386/sol2-gc1.asm b/gcc/config/i386/sol2-gc1.asm
deleted file mode 100755
index 24a1965..0000000
--- a/gcc/config/i386/sol2-gc1.asm
+++ /dev/null
@@ -1,160 +0,0 @@
-! gcrt1.s for Solaris 2, x86
-
-!   Copyright (C) 1993 Free Software Foundation, Inc.
-!   Written By Fred Fish, Nov 1992
-! 
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-! 
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file with other programs, and to distribute
-! those programs without any restriction coming from the use of this
-! file.  (The General Public License restrictions do apply in other
-! respects; for example, they cover modification of the file, and
-! distribution when not linked into another program.)
-! 
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-! General Public License for more details.
-! 
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING.  If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-! 
-!    As a special exception, if you link this library with files
-!    compiled with GCC to produce an executable, this does not cause
-!    the resulting executable to be covered by the GNU General Public License.
-!    This exception does not however invalidate any other reasons why
-!    the executable file might be covered by the GNU General Public License.
-! 
-
-! This file takes control of the process from the kernel, as specified
-! in section 3 of the System V Application Binary Interface, Intel386
-! Processor Supplement.  It has been constructed from information obtained
-! from the ABI, information obtained from single stepping existing
-! Solaris executables through their startup code with gdb, and from
-! information obtained by single stepping executables on other i386 SVR4
-! implementations.  This file is the first thing linked into any executable.
-
-! This is a modified crt1.s by J.W.Hawtin <oolon@ankh.org> 15/8/96, 
-! to allow program profiling, by calling monstartup on entry and _mcleanup 
-! on exit
-
-	.file	"gcrt1.s"
-	.ident	"GNU C gcrt1.s"
-	.weak	_DYNAMIC
-	.text
-
-! Start creating the initial frame by pushing a NULL value for the return
-! address of the initial frame, and mark the end of the stack frame chain
-! (the innermost stack frame) with a NULL value, per page 3-32 of the ABI.
-! Initialize the first stack frame pointer in %ebp (the contents of which
-! are unspecified at process initialization).
-
-	.globl	_start
-_start:
-	pushl	$0x0
-	pushl	$0x0
-	movl	%esp,%ebp
-
-! As specified per page 3-32 of the ABI, %edx contains a function 
-! pointer that should be registered with atexit(), for proper
-! shared object termination.  Just push it onto the stack for now
-! to preserve it.  We want to register _cleanup() first.
-
-	pushl	%edx
-
-! Check to see if there is an _cleanup() function linked in, and if
-! so, register it with atexit() as the last thing to be run by
-! atexit().
-
-	movl	$_mcleanup,%eax
-	testl	%eax,%eax
-	je	.L1
-	pushl	$_mcleanup
-	call	atexit
-	addl	$0x4,%esp
-.L1:
-
-! Now check to see if we have an _DYNAMIC table, and if so then
-! we need to register the function pointer previously in %edx, but
-! now conveniently saved on the stack as the argument to pass to
-! atexit().
-
-	movl	$_DYNAMIC,%eax
-	testl	%eax,%eax
-	je	.L2
-	call	atexit
-.L2:
-
-! Register _fini() with atexit().  We will take care of calling _init()
-! directly.
-
-	pushl	$_fini
-	call	atexit
-
-! Start profiling
-
-        pushl %ebp
-        movl %esp,%ebp
-        pushl $_etext
-        pushl $_start
-        call monstartup
-        addl $8,%esp
-	popl %ebp
-
-! Compute the address of the environment vector on the stack and load
-! it into the global variable _environ.  Currently argc is at 8 off
-! the frame pointer.  Fetch the argument count into %eax, scale by the
-! size of each arg (4 bytes) and compute the address of the environment
-! vector which is 16 bytes (the two zero words we pushed, plus argc,
-! plus the null word terminating the arg vector) further up the stack,
-! off the frame pointer (whew!).
-
-	movl	8(%ebp),%eax
-	leal	16(%ebp,%eax,4),%edx
-	movl	%edx,_environ
-
-! Push the environment vector pointer, the argument vector pointer,
-! and the argument count on to the stack to set up the arguments
-! for _init(), _fpstart(), and main().  Note that the environment
-! vector pointer and the arg count were previously loaded into
-! %edx and %eax respectively.  The only new value we need to compute
-! is the argument vector pointer, which is at a fixed address off
-! the initial frame pointer.
-
-	pushl	%edx
-	leal	12(%ebp),%edx
-	pushl	%edx
-	pushl	%eax
-
-! Call _init(argc, argv, environ), _fpstart(argc, argv, environ), and
-! main(argc, argv, environ).
-
-	call	_init
-	call	__fpstart
-	call	main
-
-! Pop the argc, argv, and environ arguments off the stack, push the
-! value returned from main(), and call exit().
-
-	addl	$12,%esp
-	pushl	%eax
-	call	exit
-
-! An inline equivalent of _exit, as specified in Figure 3-26 of the ABI.
-
-	pushl	$0x0
-	movl	$0x1,%eax
-	lcall	$7,$0
-
-! If all else fails, just try a halt!
-
-	hlt
-	.type	_start,@function
-	.size	_start,.-_start
diff --git a/gcc/config/i386/sol2.h b/gcc/config/i386/sol2.h
deleted file mode 100755
index cc5a089..0000000
--- a/gcc/config/i386/sol2.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Target definitions for GNU compiler for Intel 80386 running Solaris 2
-   Copyright (C) 1993, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Fred Fish (fnf@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/sysv4.h"
-
-/* The Solaris 2.0 x86 linker botches alignment of code sections.
-   It tries to align to a 16 byte boundary by padding with 0x00000090
-   ints, rather than 0x90 bytes (nop).  This generates trash in the
-   ".init" section since the contribution from crtbegin.o is only 7
-   bytes.  The linker pads it to 16 bytes with a single 0x90 byte, and
-   two 0x00000090 ints, which generates a segmentation violation when
-   executed.  This macro forces the assembler to do the padding, since
-   it knows what it is doing. */
-
-#define FORCE_INIT_SECTION_ALIGN asm (ALIGN_ASM_OP ## " 16")
-#define FORCE_FINI_SECTION_ALIGN FORCE_INIT_SECTION_ALIGN
-
-/* Add "sun" to the list of symbols defined for SVR4.  */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-  "-Dunix -D__svr4__ -D__SVR4 -Dsun -Asystem(svr4)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) \
-   %{compat-bsd:-iwithprefixbefore ucbinclude -I/usr/ucbinclude}"
-
-#undef LIB_SPEC
-#define LIB_SPEC \
-  "%{compat-bsd:-lucb -lsocket -lnsl -lelf -laio} %{!shared:%{!symbolic:-lc}}"
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s %{pg:crtn.o%s}%{!pg:crtn.o%s}"
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared: \
-			 %{!symbolic: \
-			  %{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}\
-			%{pg:gmon.o%s} crti.o%s \
-			%{ansi:values-Xc.o%s} \
-			%{!ansi: \
-			 %{traditional:values-Xt.o%s} \
-			 %{!traditional:values-Xa.o%s}} \
- 			crtbegin.o%s"
-  
-/* This should be the same as in svr4.h, except with -R added.  */
-#undef LINK_SPEC
-#define LINK_SPEC \
-  "%{h*} %{v:-V} \
-   %{b} %{Wl,*:%*} \
-   %{static:-dn -Bstatic} \
-   %{shared:-G -dy -z text} \
-   %{symbolic:-Bsymbolic -G -dy -z text} \
-   %{G:-G} \
-   %{YP,*} \
-   %{R*} \
-   %{compat-bsd: \
-     %{!YP,*:%{pg:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-     %{!pg:%{p:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-       %{!p:-Y P,/usr/ucblib:/usr/ccs/lib:/usr/lib}}} \
-     -R /usr/ucblib} \
-   %{!compat-bsd: \
-     %{!YP,*:%{pg:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-     %{!pg:%{p:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-       %{!p:-Y P,/usr/ccs/lib:/usr/lib}}}} \
-   %{Qy:} %{!Qn:-Qy}"
-
-/* This defines which switch letters take arguments.
-   It is as in svr4.h but with -R added.  */
-
-#undef SWITCH_TAKES_ARG
-#define SWITCH_TAKES_ARG(CHAR) \
-  (DEFAULT_SWITCH_TAKES_ARG(CHAR) \
-   || (CHAR) == 'R' \
-   || (CHAR) == 'h' \
-   || (CHAR) == 'z')
-
-#define STDC_0_IN_SYSTEM_HEADERS
-
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX "."
diff --git a/gcc/config/i386/sol2dbg.h b/gcc/config/i386/sol2dbg.h
deleted file mode 100755
index 9f95333..0000000
--- a/gcc/config/i386/sol2dbg.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Target definitions for GNU compiler for Intel 80386 running Solaris
-   with gas and gdb.
-   This file is added into the directory .../gcc-2.../config/i386
-   Workability without "#undef DWARF_DEBUGGING_INFO" is not tested. */
-
-/* Use stabs instead of DWARF debug format.  */
-#ifdef PREFERRED_DEBUGGING_TYPE
-#undef PREFERRED_DEBUGGING_TYPE
-#endif
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#include "i386/sol2.h"
-
-#ifdef DWARF_DEBUGGING_INFO
-#undef DWARF_DEBUGGING_INFO
-#endif
-
-/*
-  Changed from config/svr4.h in the following ways:
-
-  - Added "%{V}".
-  - Modified "{%v:-V}" to take into account "%{V}".
-  - Added "-s" so that stabs are saved in the final executable.  */
-
-#undef ASM_SPEC
-#define ASM_SPEC \
-  "%{V} %{v:%{!V:-V}} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} -s"
diff --git a/gcc/config/i386/sun.h b/gcc/config/i386/sun.h
deleted file mode 100755
index ecc0e82..0000000
--- a/gcc/config/i386/sun.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Definitions for Intel 386 running SunOS 4.0.
-   Copyright (C) 1988, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "i386/i386.h"
-
-/* Use the Sun assembler syntax.  */
-
-#include "i386/sun386.h"
-
-/* Use crt0.o as a startup file.  */
-
-#define STARTFILE_SPEC  \
-  "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \
-%{g:-lg} %{sun386:}"
-/* That last item is just to prevent a spurious error.  */
-
-#undef LINK_SPEC
-#define LINK_SPEC \
-  "%{!nostdlib:%{!r*:%{!e*:-e _start}}} -dc -dp %{static:-Bstatic}"
-
-/* Extra switches to give the assembler.  */
-
-#define ASM_SPEC "%{R} -i386 %{keep-local-as-symbols:-L}"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#define CPP_PREDEFINES "-Dunix -Di386 -Dsun386 -Dsun -Asystem(unix) -Asystem(bsd) -Acpu(i386) -Amachine(i386)"
-
-/* Allow #sccs in preprocessor.  */
-
-#define SCCS_DIRECTIVE
-
-/* Output #ident as a .ident.  */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-
-/* We don't want to output SDB debugging information.  */
-
-#undef SDB_DEBUGGING_INFO
-
-/* We want to output DBX debugging information.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Implicit library calls should use memcpy, not bcopy, etc.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Force structure alignment to the type used for a bitfield.  */
-
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* This is partly guess.  */
-
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n) \
-  ((n) == 0 ? 11 : (n)  == 1 ? 9 : (n) == 2 ? 10 : (n) == 3 ? 8	\
-   : (n) == 4 ? 5 : (n) == 5 ? 4 : (n) == 6 ? 6 : (n))
-
-/* Every debugger symbol must be in the text section.
-   Otherwise the assembler or the linker screws up.  */
-
-#define DEBUG_SYMS_TEXT
diff --git a/gcc/config/i386/sun386.h b/gcc/config/i386/sun386.h
deleted file mode 100755
index 4302ec4..0000000
--- a/gcc/config/i386/sun386.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/* Definitions for Sun assembler syntax for the Intel 80386.
-   Copyright (C) 1988, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Include common aspects of all 386 Unix assemblers.  */
-#include "i386/unix.h"
-
-#define TARGET_VERSION fprintf (stderr, " (80386, Sun syntax)");
-
-/* Define the syntax of instructions and addresses.  */
-
-/* Prefix for internally generated assembler labels.  */
-#define LPREFIX ".L"
-
-/* Define the syntax of pseudo-ops, labels and comments.  */
-
-/* Assembler pseudos to introduce constants of various size.  */
-
-#define ASM_BYTE_OP "\t.byte"
-#define ASM_SHORT "\t.value"
-#define ASM_LONG "\t.long"
-#define ASM_DOUBLE "\t.double"
-
-/* How to output an ASCII string constant.  */
-
-#define ASM_OUTPUT_ASCII(FILE, p, size) \
-do								\
-{ int i = 0; 							\
-  while (i < (size))						\
-    { if (i%10 == 0) { if (i!=0) fprintf ((FILE), "\n");	\
-		       fprintf ((FILE), "%s ", ASM_BYTE_OP); }	\
-      else fprintf ((FILE), ",");				\
-      fprintf ((FILE), "0x%x", ((p)[i++] & 0377)) ;}		\
-      fprintf ((FILE), "\n");					\
-} while (0)
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
-  do {							\
-    extern char *version_string, *language_string;	\
-    {							\
-      int len = strlen (main_input_filename);		\
-      char *na = main_input_filename + len;		\
-      char shorter[15];					\
-      /* NA gets MAIN_INPUT_FILENAME sans directory names.  */\
-      while (na > main_input_filename)			\
-	{						\
-	  if (na[-1] == '/')				\
-	    break;					\
-	  na--;						\
-	}						\
-      strncpy (shorter, na, 14);			\
-      shorter[14] = 0;					\
-      fprintf (FILE, "\t.file\t");			\
-      output_quoted_string (FILE, shorter);		\
-      fprintf (FILE, "\n");				\
-    }							\
-    fprintf (FILE, "\t.version\t\"%s %s\"\n",		\
-	     language_string, version_string);		\
-    if (optimize) ASM_FILE_START_1 (FILE);		\
-  } while (0)
-
-#define ASM_FILE_START_1(FILE) fprintf (FILE, "\t.optim\n")
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-    if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG))
-
-/* This is how to output an assembler line
-   that says to advance the location counter by SIZE bytes.  */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf ((FILE), "\t.set\t.,.+%u\n", (SIZE))
-
-/* Output before read-only data.  */
-
-#undef TEXT_SECTION_ASM_OP
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#undef DATA_SECTION_ASM_OP
-#define DATA_SECTION_ASM_OP ".data"
-
-/* Define the syntax of labels and symbol definitions/declarations.  */
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This is how to store into the string BUF
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER)	\
-  sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER))
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX ""
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
diff --git a/gcc/config/i386/svr3.ifile b/gcc/config/i386/svr3.ifile
deleted file mode 100755
index 32b3ddc..0000000
--- a/gcc/config/i386/svr3.ifile
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *      svr3.ifile - for collectless G++ on i386 System V.
- *	Leaves memory configured at address 0.
- *	
- *      Install this file as $prefix/gcc-lib/TARGET/VERSION/gcc.ifile
- *
- *	BLOCK to an offset that leaves room for many headers ( the value
- *	here allows for a file header, an outheader, and up to 11 section 
- *	headers on most systems.
- *	BIND to an address that includes page 0 in mapped memory. The value
- *	used for BLOCK should be or'd into this value. Here I'm setting BLOCK
- *	to 0x200 and BIND to ( value_used_for(BLOCK) )
- *	If you are using shared libraries, watch that you don't overlap the
- *	address ranges assigned for shared libs.
- *
- *	GROUP BIND to a location in the next segment.  Here, the only value
- *	that you should change (I think) is that within NEXT, which I've set
- *	to my hardware segment size. You can always use a larger size, but not
- *	a smaller one.
- */
-SECTIONS
-{
-	.text BIND(0x000200) BLOCK (0x200) :
-	{
-		 /* plenty for room for headers */
-		*(.init)
-		*(.text)
-		vfork = fork; /* I got tired of editing peoples sloppy code */
-		*(.fini)
-	}
-	.stab BIND(ADDR(.text) + SIZEOF(.text)): { }
-	.stabstr BIND(ADDR(.stab) + SIZEOF(.stab)): { }
-	GROUP BIND( NEXT(0x400000) +
-		(ADDR(.stabstr) + (SIZEOF(.stabstr)) % 0x1000)):
-	{
-			.data : {
-				__CTOR_LIST__ = . ; 
-				. += 4 ;	/* leading NULL */
-				*(.ctor) 
-				. += 4 ;	/* trailing NULL */
-				__DTOR_LIST__ = . ;
-				. += 4 ;	/* leading NULL */
-				*(.dtor) 
-				. += 4 ; 	/* trailing NULL */
-			 }
-			.bss : { }
-	}
-}
diff --git a/gcc/config/i386/svr3dbx.h b/gcc/config/i386/svr3dbx.h
deleted file mode 100755
index 36c01cc..0000000
--- a/gcc/config/i386/svr3dbx.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Definitions for Intel 386 running system V, using dbx-in-coff encapsulation.
-   Copyright (C) 1992, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/svr3gas.h"
-
-/* We do not want to output SDB debugging information.  */
-
-#undef SDB_DEBUGGING_INFO
-
-/* We want to output DBX debugging information.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Compensate for botch in dbxout_init/dbxout_source_file which
-   unconditionally drops the first character from ltext_label_name */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER)	\
-    sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER))
-
-/* With the current gas, .align N aligns to an N-byte boundary.
-   This is done to be compatible with the system assembler.
-   You must specify -DOTHER_ALIGN when building gas-1.38.1.  */
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-     if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG))
-
-/* Align labels, etc. at 4-byte boundaries.
-   For the 486, align to 16-byte boundary for sake of cache.  */
-
-#undef LABEL_ALIGN_AFTER_BARRIER
-#define LABEL_ALIGN_AFTER_BARRIER(LABEL) (i386_align_jumps)
-
-/* Align start of loop at 4-byte boundary.  */
-
-#undef LOOP_ALIGN
-#define LOOP_ALIGN(LABEL) (i386_align_loops)
-
-
-/* Additional overrides needed for dbx-in-coff gas, mostly taken from pbb.h */
-
-/* Although the gas we use can create .ctor and .dtor sections from N_SETT
-   stabs, it does not support section directives, so we need to have the loader
-   define the lists.
- */
-#define CTOR_LISTS_DEFINED_EXTERNALLY
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-/*
- * The loader directive file svr3.ifile defines how to merge the constructor 
- * sections into the data section.  Also, since gas only puts out those 
- * sections in response to N_SETT stabs, and does not (yet) have a 
- * ".sections" directive, svr3.ifile also defines the list symbols 
- * __DTOR_LIST__ and __CTOR_LIST__.
- */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{!r:%{!z:svr3.ifile%s}%{z:svr3z.ifile%s}}\
-   %{pg:gcrt1.o%s}%{!pg:%{posix:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}%{!posix:%{p:mcrt1.o%s}%{!p:crt1.o%s}}} \
-   %{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp}"
-  
-#define ENDFILE_SPEC "crtn.o%s"
-  
-#undef LIB_SPEC
-#define LIB_SPEC "%{posix:-lcposix} %{shlib:-lc_s} -lc -lg"
diff --git a/gcc/config/i386/svr3gas.h b/gcc/config/i386/svr3gas.h
deleted file mode 100755
index a288b84..0000000
--- a/gcc/config/i386/svr3gas.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/* Definitions for Intel 386 running system V, using gas.
-   Copyright (C) 1992, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/gas.h"
-
-/* Add stuff that normally comes from i386/sysv3.h */
-
-/* longjmp may fail to restore the registers if called from the same
-   function that called setjmp.  To compensate, the compiler avoids
-   putting variables in registers in functions that use both setjmp
-   and longjmp.  */
-
-#define NON_SAVING_SETJMP \
-  (current_function_calls_setjmp && current_function_calls_longjmp)
-
-/* longjmp may fail to restore the stack pointer if the saved frame
-   pointer is the same as the caller's frame pointer.  Requiring a frame
-   pointer in any function that calls setjmp or longjmp avoids this
-   problem, unless setjmp and longjmp are called from the same function.
-   Since a frame pointer will be required in such a function, it is OK
-   that the stack pointer is not restored.  */
-
-#undef FRAME_POINTER_REQUIRED
-#define FRAME_POINTER_REQUIRED \
-  (current_function_calls_setjmp || current_function_calls_longjmp)
-
-/* Modify ASM_OUTPUT_LOCAL slightly to test -msvr3-shlib, adapted to gas  */
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
-  do {							\
-    int align = exact_log2 (ROUNDED);			\
-    if (align > 2) align = 2;				\
-    if (TARGET_SVR3_SHLIB)				\
-      {							\
-	data_section ();				\
-	ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align); \
-	ASM_OUTPUT_LABEL ((FILE), (NAME));		\
-	fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED));	\
-      }							\
-    else						\
-      {							\
-	fputs (".lcomm ", (FILE));			\
-	assemble_name ((FILE), (NAME));			\
-	fprintf ((FILE), ",%u\n", (ROUNDED));		\
-      }							\
-  } while (0)
-
-/* Add stuff that normally comes from i386/sysv3.h via svr3.h */
-
-/* Define the actual types of some ANSI-mandated types.  These
-   definitions should work for most SVR3 systems.  */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-/* ??? This stuff is copied from config/svr3.h.  In the future,
-   this file should be rewritten to include config/svr3.h
-   and override what isn't right.  */
-
-/* Support const sections and the ctors and dtors sections for g++.
-   Note that there appears to be two different ways to support const
-   sections at the moment.  You can either #define the symbol
-   READONLY_DATA_SECTION (giving it some code which switches to the
-   readonly data section) or else you can #define the symbols
-   EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
-   SELECT_RTX_SECTION.  We do both here just to be on the safe side.
-   However, use of the const section is turned off by default
-   unless the specific tm.h file turns it on by defining
-   USE_CONST_SECTION as 1.  */
-
-/* Define a few machine-specific details of the implementation of
-   constructors.
-
-   The __CTORS_LIST__ goes in the .init section.  Define CTOR_LIST_BEGIN
-   and CTOR_LIST_END to contribute to the .init section an instruction to
-   push a word containing 0 (or some equivalent of that).
-
-   Define ASM_OUTPUT_CONSTRUCTOR to push the address of the constructor.  */
-
-#define USE_CONST_SECTION	0
-
-#define INIT_SECTION_ASM_OP     ".section\t.init"
-#define FINI_SECTION_ASM_OP     ".section .fini,\"x\""
-#define CONST_SECTION_ASM_OP	".section\t.rodata, \"x\""
-#define CTORS_SECTION_ASM_OP	INIT_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP    FINI_SECTION_ASM_OP
-
-/* CTOR_LIST_BEGIN and CTOR_LIST_END are machine-dependent
-   because they push on the stack.  */
-
-#ifdef STACK_GROWS_DOWNWARD
-
-/* Constructor list on stack is in reverse order.  Go to the end of the
-   list and go backwards to call constructors in the right order.  */
-#define DO_GLOBAL_CTORS_BODY					\
-do {								\
-  func_ptr *p, *beg = alloca (0);				\
-  for (p = beg; *p; p++)					\
-    ;								\
-  while (p != beg)						\
-    (*--p) ();							\
-} while (0)
-
-#else
-
-/* Constructor list on stack is in correct order.  Just call them.  */
-#define DO_GLOBAL_CTORS_BODY					\
-do {								\
-  func_ptr *p, *beg = alloca (0);				\
-  for (p = beg; *p; )						\
-    (*p++) ();							\
-} while (0)
-
-#endif /* STACK_GROWS_DOWNWARD */
-
-/* Add extra sections .rodata, .init and .fini.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_init, in_fini
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS					\
-  CONST_SECTION_FUNCTION					\
-  INIT_SECTION_FUNCTION						\
-  FINI_SECTION_FUNCTION
-
-#define INIT_SECTION_FUNCTION					\
-void								\
-init_section ()							\
-{								\
-  if (in_section != in_init)					\
-    {								\
-      fprintf (asm_out_file, "\t%s\n", INIT_SECTION_ASM_OP);	\
-      in_section = in_init;					\
-    }								\
-}
-
-#define FINI_SECTION_FUNCTION					\
-void								\
-fini_section ()							\
-{								\
-  if (in_section != in_fini)					\
-    {								\
-      fprintf (asm_out_file, "\t%s\n", FINI_SECTION_ASM_OP);	\
-      in_section = in_fini;					\
-    }								\
-}
-
-#define READONLY_DATA_SECTION() const_section ()
-
-#define CONST_SECTION_FUNCTION						\
-void									\
-const_section ()							\
-{									\
-  extern void text_section();						\
-  if (!USE_CONST_SECTION)						\
-    text_section();							\
-  else if (in_section != in_const)					\
-    {									\
-      fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP);		\
-      in_section = in_const;						\
-    }									\
-}
-
-/* The ctors and dtors sections are not normally put into use 
-   by EXTRA_SECTIONS and EXTRA_SECTION_FUNCTIONS as defined in svr3.h,
-   but it can't hurt to define these macros for whatever systems use them.  */
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-/* This is machine-dependent
-   because it needs to push something on the stack.  */
-#undef ASM_OUTPUT_CONSTRUCTOR
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    fini_section ();                   				\
-    fprintf (FILE, "%s\t ", ASM_LONG);					\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement or statements to switch to the appropriate
-   section for output of DECL.  DECL is either a `VAR_DECL' node
-   or a constant of some sort.  RELOC indicates whether forming
-   the initial value of DECL requires link-time relocations.  */
-
-#define SELECT_SECTION(DECL,RELOC)					\
-{									\
-  if (TREE_CODE (DECL) == STRING_CST)					\
-    {									\
-      if (! flag_writable_strings)					\
-	const_section ();						\
-      else								\
-	data_section ();						\
-    }									\
-  else if (TREE_CODE (DECL) == VAR_DECL)				\
-    {									\
-      if ((0 && RELOC)	/* should be (flag_pic && RELOC) */		\
-	  || !TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)		\
-	  || !DECL_INITIAL (DECL)					\
-	  || (DECL_INITIAL (DECL) != error_mark_node 			\
-	      && !TREE_CONSTANT (DECL_INITIAL (DECL))))			\
-	data_section ();						\
-      else								\
-	const_section ();						\
-    }									\
-  else									\
-    const_section ();							\
-}
-
-/* A C statement or statements to switch to the appropriate
-   section for output of RTX in mode MODE.  RTX is some kind
-   of constant in RTL.  The argument MODE is redundant except
-   in the case of a `const_int' rtx.  Currently, these always
-   go into the const section.  */
-
-#define SELECT_RTX_SECTION(MODE,RTX) const_section()
-
-/* This is copied from i386/sysv3.h.  */
-
-/* Define a few machine-specific details of the implementation of
-   constructors.
-
-   The __CTORS_LIST__ goes in the .init section.  Define CTOR_LIST_BEGIN
-   and CTOR_LIST_END to contribute to the .init section an instruction to
-   push a word containing 0 (or some equivalent of that).
-
-   ASM_OUTPUT_CONSTRUCTOR should be defined to push the address of the
-   constructor.  */
-
-#undef INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP     ".section .init,\"x\""
-
-#define CTOR_LIST_BEGIN				\
-  asm (INIT_SECTION_ASM_OP);			\
-  asm ("pushl $0")
-#define CTOR_LIST_END CTOR_LIST_BEGIN
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)	\
-  do {						\
-    init_section ();				\
-    fprintf (FILE, "\tpushl $");		\
-    assemble_name (FILE, NAME);			\
-    fprintf (FILE, "\n");			\
-  } while (0)
diff --git a/gcc/config/i386/svr3z.ifile b/gcc/config/i386/svr3z.ifile
deleted file mode 100755
index 4946051..0000000
--- a/gcc/config/i386/svr3z.ifile
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *      svr3z.ifile - for collectless G++ on i386 System V.
- *	Leaves memory unconfigured at address 0.
- *	
- *      Install this file as $prefix/gcc-lib/TARGET/VERSION/gccz.ifile
- *
- *	BLOCK to an offset that leaves room for many headers ( the value
- *	here allows for a file header, an outheader, and up to 11 section 
- *	headers on most systems.
- *	BIND to an address that excludes page 0 from being mapped. The value
- *	used for BLOCK should be or'd into this value. Here I'm setting BLOCK
- *	to 0x200 and BIND to ( 0x400000 | value_used_for(BLOCK) )
- *	If you are using shared libraries, watch that you don't overlap the
- *	address ranges assigned for shared libs.
- *
- *	GROUP BIND to a location in the next segment.  Here, the only value
- *	that you should change (I think) is that within NEXT, which I've set
- *	to my hardware segment size. You can always use a larger size, but not
- *	a smaller one.
- */
-SECTIONS
-{
-	.text BIND(0x400200) BLOCK (0x200) :
-	{
-		 /* plenty for room for headers */
-		*(.init)
-		*(.text)
-		vfork = fork; /* I got tired of editing peoples sloppy code */
-		*(.fini)
-	}
-	.stab BIND(ADDR(.text) + SIZEOF(.text)): { }
-	.stabstr BIND(ADDR(.stab) + SIZEOF(.stab)): { }
-	GROUP BIND( NEXT(0x400000) +
-		(ADDR(.stabstr) + (SIZEOF(.stabstr)) % 0x1000)):
-	{
-			.data : {
-				__CTOR_LIST__ = . ; 
-				. += 4 ;	/* leading NULL */
-				*(.ctor) 
-				. += 4 ;	/* trailing NULL */
-				__DTOR_LIST__ = . ;
-				. += 4 ;	/* leading NULL */
-				*(.dtor) 
-				. += 4 ; 	/* trailing NULL */
-			 }
-			.bss : { }
-	}
-}
diff --git a/gcc/config/i386/sysv3.h b/gcc/config/i386/sysv3.h
deleted file mode 100755
index ce89889..0000000
--- a/gcc/config/i386/sysv3.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/* Definitions for Intel 386 running system V.
-   Copyright (C) 1988, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "i386/i386.h"
-
-/* Use default settings for system V.3.  */
-
-#include "svr3.h"
-
-/* Use the ATT assembler syntax.
-   This overrides at least one macro (USER_LABEL_PREFIX) from svr3.h.  */
-
-#include "i386/att.h"
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-
-#define STARTFILE_SPEC  \
-  "%{pg:gcrt1.o%s}%{!pg:%{posix:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}%{!posix:%{p:mcrt1.o%s}%{!p:crt1.o%s}}} crtbegin.o%s\
-   %{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp}"
-
-/* ??? There is a suggestion that -lg is needed here.
-   Does anyone know whether this is right?  */
-#define LIB_SPEC "%{posix:-lcposix} %{shlib:-lc_s} -lc crtend.o%s crtn.o%s"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#define CPP_PREDEFINES "-Dunix -Asystem(svr3)"
-
-#define CPP_SPEC "%(cpp_cpu) %{posix:-D_POSIX_SOURCE}"
-
-/* Writing `int' for a bitfield forces int alignment for the structure.  */
-
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Don't write a `.optim' pseudo; this assembler doesn't handle them.  */
-
-#undef ASM_FILE_START_1
-#define ASM_FILE_START_1(FILE)
-
-/* We want to be able to get DBX debugging information via -gstabs.  */
-
-#undef DBX_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
-
-/* longjmp may fail to restore the registers if called from the same
-   function that called setjmp.  To compensate, the compiler avoids
-   putting variables in registers in functions that use both setjmp
-   and longjmp.  */
-
-#define NON_SAVING_SETJMP \
-  (current_function_calls_setjmp && current_function_calls_longjmp)
-
-/* longjmp may fail to restore the stack pointer if the saved frame
-   pointer is the same as the caller's frame pointer.  Requiring a frame
-   pointer in any function that calls setjmp or longjmp avoids this
-   problem, unless setjmp and longjmp are called from the same function.
-   Since a frame pointer will be required in such a function, it is OK
-   that the stack pointer is not restored.  */
-
-#undef FRAME_POINTER_REQUIRED
-#define FRAME_POINTER_REQUIRED \
-  (current_function_calls_setjmp || current_function_calls_longjmp)
-
-/* Modify ASM_OUTPUT_LOCAL slightly to test -msvr3-shlib.  */
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
-  do {							\
-    int align = exact_log2 (ROUNDED);			\
-    if (align > 2) align = 2;				\
-    if (TARGET_SVR3_SHLIB)				\
-      data_section ();					\
-    else						\
-      bss_section ();					\
-    ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align);	\
-    ASM_OUTPUT_LABEL ((FILE), (NAME));			\
-    fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED));	\
-  } while (0)
-
-/* Define a few machine-specific details of the implementation of
-   constructors.
-
-   The __CTORS_LIST__ goes in the .init section.  Define CTOR_LIST_BEGIN
-   and CTOR_LIST_END to contribute to the .init section an instruction to
-   push a word containing 0 (or some equivalent of that).
-
-   ASM_OUTPUT_CONSTRUCTOR should be defined to push the address of the
-   constructor.  */
-
-#undef INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP     ".section .init,\"x\""
-
-#define CTOR_LIST_BEGIN				\
-  asm (INIT_SECTION_ASM_OP);			\
-  asm ("pushl $0")
-#define CTOR_LIST_END CTOR_LIST_BEGIN
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)	\
-  do {						\
-    init_section ();				\
-    fprintf (FILE, "\tpushl $");		\
-    assemble_name (FILE, NAME);			\
-    fprintf (FILE, "\n");			\
-  } while (0)
diff --git a/gcc/config/i386/sysv4.h b/gcc/config/i386/sysv4.h
deleted file mode 100755
index e688f7b..0000000
--- a/gcc/config/i386/sysv4.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/* Target definitions for GNU compiler for Intel 80386 running System V.4
-   Copyright (C) 1991 Free Software Foundation, Inc.
-
-   Written by Ron Guilmette (rfg@netcom.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/i386.h"	/* Base i386 target machine definitions */
-#include "i386/att.h"	/* Use the i386 AT&T assembler syntax */
-#include "svr4.h"	/* Definitions common to all SVR4 targets */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i386 System V Release 4)");
-
-/* The svr4 ABI for the i386 says that records and unions are returned
-   in memory.  */
-
-#undef RETURN_IN_MEMORY
-#define RETURN_IN_MEMORY(TYPE) \
-  (TYPE_MODE (TYPE) == BLKmode)
-
-/* Define which macros to predefine.  __svr4__ is our extension.  */
-/* This used to define X86, but james@bigtex.cactus.org says that
-   is supposed to be defined optionally by user programs--not by default.  */
-#define CPP_PREDEFINES \
-  "-Di386 -Dunix -D__svr4__ -Asystem(unix) -Asystem(svr4) -Acpu(i386) -Amachine(i386)"
-
-/* This is how to output assembly code to define a `float' constant.
-   We always have to use a .long pseudo-op to do this because the native
-   SVR4 ELF assembler is buggy and it generates incorrect values when we
-   try to use the .float pseudo-op instead.  */
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
-do { long value;							\
-     REAL_VALUE_TO_TARGET_SINGLE ((VALUE), value);			\
-     if (sizeof (int) == sizeof (long))					\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value);		\
-     else								\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value);		\
-   } while (0)
-
-/* This is how to output assembly code to define a `double' constant.
-   We always have to use a pair of .long pseudo-ops to do this because
-   the native SVR4 ELF assembler is buggy and it generates incorrect
-   values when we try to use the .double pseudo-op instead.  */
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
-do { long value[2];							\
-     REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), value);			\
-     if (sizeof (int) == sizeof (long))					\
-       {								\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[0]);		\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[1]);		\
-       }								\
-     else								\
-       {								\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[0]);		\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[1]);		\
-       }								\
-   } while (0)
-
-
-#undef ASM_OUTPUT_LONG_DOUBLE
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE)				\
-do { long value[3];							\
-     REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), value);			\
-     if (sizeof (int) == sizeof (long))					\
-       {								\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[0]);		\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[1]);		\
-         fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[2]);		\
-       }								\
-     else								\
-       {								\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[0]);		\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[1]);		\
-         fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[2]);		\
-       }								\
-   } while (0)
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)						\
-  do {									\
-	output_file_directive (FILE, main_input_filename);		\
-	fprintf (FILE, "\t.version\t\"01.01\"\n");			\
-  } while (0)
-
-/* Define the register numbers to be used in Dwarf debugging information.
-   The SVR4 reference port C compiler uses the following register numbers
-   in its Dwarf output code:
-
-	0 for %eax (gnu regno = 0)
-	1 for %ecx (gnu regno = 2)
-	2 for %edx (gnu regno = 1)
-	3 for %ebx (gnu regno = 3)
-	4 for %esp (gnu regno = 7)
-	5 for %ebp (gnu regno = 6)
-	6 for %esi (gnu regno = 4)
-	7 for %edi (gnu regno = 5)
-
-   The following three DWARF register numbers are never generated by
-   the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
-   believes these numbers have these meanings.
-
-	8  for %eip    (no gnu equivalent)
-	9  for %eflags (no gnu equivalent)
-	10 for %trapno (no gnu equivalent)
-
-   It is not at all clear how we should number the FP stack registers
-   for the x86 architecture.  If the version of SDB on x86/svr4 were
-   a bit less brain dead with respect to floating-point then we would
-   have a precedent to follow with respect to DWARF register numbers
-   for x86 FP registers, but the SDB on x86/svr4 is so completely
-   broken with respect to FP registers that it is hardly worth thinking
-   of it as something to strive for compatibility with.
-
-   The version of x86/svr4 SDB I have at the moment does (partially)
-   seem to believe that DWARF register number 11 is associated with
-   the x86 register %st(0), but that's about all.  Higher DWARF
-   register numbers don't seem to be associated with anything in
-   particular, and even for DWARF regno 11, SDB only seems to under-
-   stand that it should say that a variable lives in %st(0) (when
-   asked via an `=' command) if we said it was in DWARF regno 11,
-   but SDB still prints garbage when asked for the value of the
-   variable in question (via a `/' command).
-
-   (Also note that the labels SDB prints for various FP stack regs
-   when doing an `x' command are all wrong.)
-
-   Note that these problems generally don't affect the native SVR4
-   C compiler because it doesn't allow the use of -O with -g and
-   because when it is *not* optimizing, it allocates a memory
-   location for each floating-point variable, and the memory
-   location is what gets described in the DWARF AT_location
-   attribute for the variable in question.
-
-   Regardless of the severe mental illness of the x86/svr4 SDB, we
-   do something sensible here and we use the following DWARF
-   register numbers.  Note that these are all stack-top-relative
-   numbers.
-
-	11 for %st(0) (gnu regno = 8)
-	12 for %st(1) (gnu regno = 9)
-	13 for %st(2) (gnu regno = 10)
-	14 for %st(3) (gnu regno = 11)
-	15 for %st(4) (gnu regno = 12)
-	16 for %st(5) (gnu regno = 13)
-	17 for %st(6) (gnu regno = 14)
-	18 for %st(7) (gnu regno = 15)
-*/
-
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(n) \
-((n) == 0 ? 0 \
- : (n) == 1 ? 2 \
- : (n) == 2 ? 1 \
- : (n) == 3 ? 3 \
- : (n) == 4 ? 6 \
- : (n) == 5 ? 7 \
- : (n) == 6 ? 5 \
- : (n) == 7 ? 4 \
- : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \
- : (-1))
-
-/* The routine used to output sequences of byte values.  We use a special
-   version of this for most svr4 targets because doing so makes the
-   generated assembly code more compact (and thus faster to assemble)
-   as well as more readable.  Note that if we find subparts of the
-   character sequence which end with NUL (and which are shorter than
-   STRING_LIMIT) we output those using ASM_OUTPUT_LIMITED_STRING.  */
-
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH)				\
-  do									\
-    {									\
-      register unsigned char *_ascii_bytes = (unsigned char *) (STR);	\
-      register unsigned char *limit = _ascii_bytes + (LENGTH);		\
-      register unsigned bytes_in_chunk = 0;				\
-      for (; _ascii_bytes < limit; _ascii_bytes++)			\
-        {								\
-	  register unsigned char *p;					\
-	  if (bytes_in_chunk >= 64)					\
-	    {								\
-	      fputc ('\n', (FILE));					\
-	      bytes_in_chunk = 0;					\
-	    }								\
-	  for (p = _ascii_bytes; p < limit && *p != '\0'; p++)		\
-	    continue;							\
-	  if (p < limit && (p - _ascii_bytes) <= STRING_LIMIT)		\
-	    {								\
-	      if (bytes_in_chunk > 0)					\
-		{							\
-		  fputc ('\n', (FILE));					\
-		  bytes_in_chunk = 0;					\
-		}							\
-	      ASM_OUTPUT_LIMITED_STRING ((FILE), _ascii_bytes);		\
-	      _ascii_bytes = p;						\
-	    }								\
-	  else								\
-	    {								\
-	      if (bytes_in_chunk == 0)					\
-		fprintf ((FILE), "\t.byte\t");				\
-	      else							\
-		fputc (',', (FILE));					\
-	      fprintf ((FILE), "0x%02x", *_ascii_bytes);		\
-	      bytes_in_chunk += 5;					\
-	    }								\
-	}								\
-      if (bytes_in_chunk > 0)						\
-        fprintf ((FILE), "\n");						\
-    }									\
-  while (0)
-
-/* This is how to output an element of a case-vector that is relative.
-   This is only used for PIC code.  See comments by the `casesi' insn in
-   i386.md for an explanation of the expression this outputs. */
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE)
-
-/* Indicate that jump tables go in the text section.  This is
-   necessary when compiling PIC code.  */
-
-#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of uninitialized global DECL named
-   NAME whose size is SIZE bytes and alignment is ALIGN bytes.
-   Try to use asm_output_aligned_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
diff --git a/gcc/config/i386/t-crtpic b/gcc/config/i386/t-crtpic
deleted file mode 100755
index 891a5de..0000000
--- a/gcc/config/i386/t-crtpic
+++ /dev/null
@@ -1,16 +0,0 @@
-# The pushl in CTOR initialization interferes with frame pointer elimination.
-
-# We need to use -fPIC when we are using gcc to compile the routines in
-# crtstuff.c.  This is only really needed when we are going to use gcc/g++
-# to produce a shared library, but since we don't know ahead of time when
-# we will be doing that, we just always use -fPIC when compiling the
-# routines in crtstuff.c.
-
-CRTSTUFF_T_CFLAGS = -fPIC -fno-omit-frame-pointer
-TARGET_LIBGCC2_CFLAGS = -fPIC
-
-# CYGNUS LOCAL i386/t-crtpic
-# Don't build libgcc1.a, so that we can build cross compilers to unixware.
-LIBGCC1 =
-CROSS_LIBGCC1 =
-# END CYGNUS LOCAL
diff --git a/gcc/config/i386/t-crtstuff b/gcc/config/i386/t-crtstuff
deleted file mode 100755
index a202df6..0000000
--- a/gcc/config/i386/t-crtstuff
+++ /dev/null
@@ -1,2 +0,0 @@
-# The pushl in CTOR initialization interferes with frame pointer elimination.
-CRTSTUFF_T_CFLAGS = -fno-omit-frame-pointer
diff --git a/gcc/config/i386/t-cygwin b/gcc/config/i386/t-cygwin
deleted file mode 100755
index 175f66b..0000000
--- a/gcc/config/i386/t-cygwin
+++ /dev/null
@@ -1,16 +0,0 @@
-LIBGCC1 = libgcc1-asm.a
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = i386/cygwin.asm
-LIB1ASMFUNCS = _chkstk
-
-# cygwin always has a limits.h, but, depending upon how we are doing
-# the build, it may not be installed yet.
-LIMITS_H_TEST = true
-
-# If we are building next to winsup, this will let us find the real
-# limits.h when building libgcc2.  Otherwise, winsup must be installed
-# first.
-LIBGCC2_INCLUDES = -I$(srcdir)/../winsup/include
-
-winnt.o: $(srcdir)/config/i386/winnt.c
-	$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/i386/winnt.c
diff --git a/gcc/config/i386/t-dgux b/gcc/config/i386/t-dgux
deleted file mode 100755
index 292331f..0000000
--- a/gcc/config/i386/t-dgux
+++ /dev/null
@@ -1,4 +0,0 @@
-#
-# target makefile for dgux
-#
-EXTRA_PARTS=crtbegin.o crtend.o
diff --git a/gcc/config/i386/t-freebsd b/gcc/config/i386/t-freebsd
deleted file mode 100755
index 5164669..0000000
--- a/gcc/config/i386/t-freebsd
+++ /dev/null
@@ -1,5 +0,0 @@
-# Don't run fixproto
-STMP_FIXPROTO =
-# Use only native include files
-USER_H = $(EXTRA_HEADERS) $(LANG_EXTRA_HEADERS)
-
diff --git a/gcc/config/i386/t-go32 b/gcc/config/i386/t-go32
deleted file mode 100755
index 6160b7e..0000000
--- a/gcc/config/i386/t-go32
+++ /dev/null
@@ -1,2 +0,0 @@
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
diff --git a/gcc/config/i386/t-i386bare b/gcc/config/i386/t-i386bare
deleted file mode 100755
index 2970fa7..0000000
--- a/gcc/config/i386/t-i386bare
+++ /dev/null
@@ -1,3 +0,0 @@
-# The i386 md has all of these taken care of, according to sef.
-LIBGCC1 =
-CROSS_LIBGCC1 =
diff --git a/gcc/config/i386/t-i386elf b/gcc/config/i386/t-i386elf
deleted file mode 100755
index 017f08a..0000000
--- a/gcc/config/i386/t-i386elf
+++ /dev/null
@@ -1,8 +0,0 @@
-# CYGNUS LOCAL (entire file) i386-elf
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
-
-# For svr4 we build crtbegin.o and crtend.o which serve to add begin and
-# end labels to the .ctors and .dtors section when we link using gcc.
-
-EXTRA_PARTS=crtbegin.o crtend.o
diff --git a/gcc/config/i386/t-mingw32 b/gcc/config/i386/t-mingw32
deleted file mode 100755
index fe948c6..0000000
--- a/gcc/config/i386/t-mingw32
+++ /dev/null
@@ -1,4 +0,0 @@
-#
-# collect2 doesn't work for i386-mingw32* yet.
-#
-USE_COLLECT2=
diff --git a/gcc/config/i386/t-netware b/gcc/config/i386/t-netware
deleted file mode 100755
index f898857..0000000
--- a/gcc/config/i386/t-netware
+++ /dev/null
@@ -1,6 +0,0 @@
-# This file is CYGNUS LOCAL in order to not build libgcc1.a.
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
-
-# Our header files are supposed to be correct, nein?
-STMP_FIXPROTO =
diff --git a/gcc/config/i386/t-next b/gcc/config/i386/t-next
deleted file mode 100755
index effa695..0000000
--- a/gcc/config/i386/t-next
+++ /dev/null
@@ -1,12 +0,0 @@
-# libgcc1.c is not needed, since the standard library has these functions.
-LIBGCC1=libgcc1.null
-CROSS_LIBGCC1=libgcc1.null
-
-# Specify other dirs of system header files to be fixed.
-OTHER_FIXINCLUDES_DIRS= /LocalDeveloper/Headers
-
-# <limits.h> is sometimes in /usr/include/ansi/limits.h.
-LIMITS_H_TEST = [ -f $(SYSTEM_HEADER_DIR)/limits.h -o -f $(SYSTEM_HEADER_DIR)/ansi/limits.h ]
-
-nextstep.o: $(srcdir)/config/nextstep.c $(CONFIG_H) flags.h tree.h
-	$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/nextstep.c
diff --git a/gcc/config/i386/t-osf b/gcc/config/i386/t-osf
deleted file mode 100755
index c996e0c..0000000
--- a/gcc/config/i386/t-osf
+++ /dev/null
@@ -1,2 +0,0 @@
-# If compiling with the osf gcc, avoid sharing code.
-TCFLAGS = -pic-none
diff --git a/gcc/config/i386/t-osf1elf b/gcc/config/i386/t-osf1elf
deleted file mode 100755
index 77c7df1..0000000
--- a/gcc/config/i386/t-osf1elf
+++ /dev/null
@@ -1,18 +0,0 @@
-# Assemble startup files.
-crti.o: $(srcdir)/config/i386/osf1-ci.asm $(GCC_PASSES)
-	sed -e '/^!/d' <$(srcdir)/config/i386/osf1-ci.asm >crti.s
-	$(GCC_FOR_TARGET) -c -o crti.o crti.s
-crtn.o: $(srcdir)/config/i386/osf1-cn.asm $(GCC_PASSES)
-	sed -e '/^!/d' <$(srcdir)/config/i386/osf1-cn.asm >crtn.s
-	$(GCC_FOR_TARGET) -c -o crtn.o crtn.s
-
-# The pushl in CTOR initialization interferes with frame pointer elimination.
-
-# We need to use -fPIC when we are using gcc to compile the routines in
-# crtstuff.c.  This is only really needed when we are going to use gcc/g++
-# to produce a shared library, but since we don't know ahead of time when
-# we will be doing that, we just always use -fPIC when compiling the
-# routines in crtstuff.c.
-
-CRTSTUFF_T_CFLAGS = -fPIC -fno-omit-frame-pointer
-TARGET_LIBGCC2_CFLAGS = -fPIC
diff --git a/gcc/config/i386/t-sco5 b/gcc/config/i386/t-sco5
deleted file mode 100755
index fd3d6c6..0000000
--- a/gcc/config/i386/t-sco5
+++ /dev/null
@@ -1,16 +0,0 @@
-# The pushl in CTOR initialization interferes with frame pointer elimination.
-CRTSTUFF_T_CFLAGS   = -fPIC -fno-omit-frame-pointer
-CRTSTUFF_T_CFLAGS_S = -mcoff -fno-omit-frame-pointer
-
-#
-# I am still a little unsure of the multilib architecture. The following
-# 4 lines are based on advice from meissner@cygnus.com.
-#
-MULTILIB_OPTIONS    = mcoff/fPIC
-MULTILIB_DIRNAMES   = coff pic
-MULTILIB_EXCEPTIONS = *mcoff*/*fPIC*
-MULTILIB_MATCHES    = fPIC=fpic
-MULTILIB_EXTRA_OPTS =
-
-LIBGCC=stmp-multilib
-INSTALL_LIBGCC=install-multilib
diff --git a/gcc/config/i386/t-sco5gas b/gcc/config/i386/t-sco5gas
deleted file mode 100755
index 6aa15d2..0000000
--- a/gcc/config/i386/t-sco5gas
+++ /dev/null
@@ -1,16 +0,0 @@
-# The pushl in CTOR initialization interferes with frame pointer elimination.
-CRTSTUFF_T_CFLAGS   = -fPIC -fno-omit-frame-pointer
-CRTSTUFF_T_CFLAGS_S = -mcoff -fno-omit-frame-pointer
-
-#
-# I am still a little unsure of the multilib architecture. The following
-# 4 lines are based on advice from meissner@cygnus.com.
-#
-MULTILIB_OPTIONS    = fPIC
-MULTILIB_DIRNAMES   = pic
-MULTILIB_EXCEPTIONS = *fPIC*
-MULTILIB_MATCHES    = fPIC=fpic
-MULTILIB_EXTRA_OPTS =
-
-LIBGCC=stmp-multilib
-INSTALL_LIBGCC=install-multilib
diff --git a/gcc/config/i386/t-sol2 b/gcc/config/i386/t-sol2
deleted file mode 100755
index 5dc59cc..0000000
--- a/gcc/config/i386/t-sol2
+++ /dev/null
@@ -1,40 +0,0 @@
-# we need to supply our own assembly versions of libgcc1.c files,
-# since the user may not have native 'cc' available
-
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
-
-# gmon build rule:
-gmon.o:	$(srcdir)/config/i386/gmon-sol2.c $(GCC_PASSES) $(CONFIG_H)
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) \
-		-c $(srcdir)/config/i386/gmon-sol2.c -o gmon.o
-
-# Assemble startup files.
-# Apparently Sun believes that assembler files don't need comments, because no
-# single ASCII character is valid (tried them all).  So we manually strip out
-# the comments with sed.  This bug may only be in the Early Access releases.
-gcrt1.o: $(srcdir)/config/i386/sol2-gc1.asm
-	sed -e '/^!/d' <$(srcdir)/config/i386/sol2-gc1.asm >gcrt1.s
-	$(AS) -o gcrt1.o gcrt1.s
-crt1.o: $(srcdir)/config/i386/sol2-c1.asm $(GCC_PASSES)
-	sed -e '/^!/d' <$(srcdir)/config/i386/sol2-c1.asm >crt1.s
-	$(GCC_FOR_TARGET) -c -o crt1.o crt1.s
-crti.o: $(srcdir)/config/i386/sol2-ci.asm $(GCC_PASSES)
-	sed -e '/^!/d' <$(srcdir)/config/i386/sol2-ci.asm >crti.s
-	$(GCC_FOR_TARGET) -c -o crti.o crti.s
-crtn.o: $(srcdir)/config/i386/sol2-cn.asm $(GCC_PASSES)
-	sed -e '/^!/d' <$(srcdir)/config/i386/sol2-cn.asm >crtn.s
-	$(GCC_FOR_TARGET) -c -o crtn.o crtn.s
-
-# We need to use -fPIC when we are using gcc to compile the routines in
-# crtstuff.c.  This is only really needed when we are going to use gcc/g++
-# to produce a shared library, but since we don't know ahead of time when
-# we will be doing that, we just always use -fPIC when compiling the
-# routines in crtstuff.c.
-#
-# We must also enable optimization to avoid having any code appear after
-# the call & alignment statement, but before we switch back to the
-# .text section.
-
-CRTSTUFF_T_CFLAGS = -fPIC -O2
-TARGET_LIBGCC2_CFLAGS = -fPIC
diff --git a/gcc/config/i386/t-svr3dbx b/gcc/config/i386/t-svr3dbx
deleted file mode 100755
index 5171137..0000000
--- a/gcc/config/i386/t-svr3dbx
+++ /dev/null
@@ -1,7 +0,0 @@
-# gas 1.38.1 supporting dbx-in-coff requires a link script.
-
-svr3.ifile: $(srcdir)/config/i386/svr3.ifile
-	rm -f svr3.ifile; cp $(srcdir)/config/i386/svr3.ifile .
-
-svr3z.ifile: $(srcdir)/config/i386/svr3z.ifile
-	rm -f svr3z.ifile; cp $(srcdir)/config/i386/svr3z.ifile .
diff --git a/gcc/config/i386/t-svr4 b/gcc/config/i386/t-svr4
deleted file mode 100755
index 10b9b4f..0000000
--- a/gcc/config/i386/t-svr4
+++ /dev/null
@@ -1,17 +0,0 @@
-# CYGNUS LOCAL: entire file
-# Don't build libgcc1.a.
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
-
-# For svr4 we build crtbegin.o and crtend.o which serve to add begin and
-# end labels to the .ctors and .dtors section when we link using gcc.
-
-EXTRA_PARTS=crtbegin.o crtend.o
-
-# We need to use -fPIC when we are using gcc to compile the routines in
-# crtstuff.c.  This is only really needed when we are going to use gcc/g++
-# to produce a shared library, but since we don't know ahead of time when
-# we will be doing that, we just always use -fPIC when compiling the
-# routines in crtstuff.c.
-
-CRTSTUFF_T_CFLAGS = -fPIC
diff --git a/gcc/config/i386/t-udk b/gcc/config/i386/t-udk
deleted file mode 100755
index 96e1864..0000000
--- a/gcc/config/i386/t-udk
+++ /dev/null
@@ -1,2 +0,0 @@
-# Tell fixincludes to work on this set of headers
-SYSTEM_HEADER_DIR = /udk/usr/include
diff --git a/gcc/config/i386/t-vsta b/gcc/config/i386/t-vsta
deleted file mode 100755
index 6160b7e..0000000
--- a/gcc/config/i386/t-vsta
+++ /dev/null
@@ -1,2 +0,0 @@
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
diff --git a/gcc/config/i386/t-winnt b/gcc/config/i386/t-winnt
deleted file mode 100755
index 1e3557c..0000000
--- a/gcc/config/i386/t-winnt
+++ /dev/null
@@ -1,6 +0,0 @@
-winnt.o: $(srcdir)/config/i386/winnt.c
-	$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/i386/winnt.c
-oldnames.o: $(srcdir)/config/winnt/oldnames.c
-	$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/winnt/oldnames.c
-spawnv.o: $(srcdir)/config/winnt/spawnv.c
-	$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/winnt/spawnv.c
diff --git a/gcc/config/i386/udk.h b/gcc/config/i386/udk.h
deleted file mode 100755
index 3b93ebc..0000000
--- a/gcc/config/i386/udk.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Configuration for i386 interfacing with SCO's Universal Development Kit
-   probably running on OpenServer 5, Unixware 2, or Unixware 5
- */
-
-
-/* We're very much the SVR4 target with "/udk" prepended to everything that's
-   interesting */
-
-#include "i386/sysv4.h"
-
-#undef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX 		"/udk/usr/ccs/bin/" 
-
-#undef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX 	"/udk/usr/ccs/lib/" 
-
-#if 0 /* Later. */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 
-#endif
-
-#define STANDARD_INCLUDE_DIR	"/udk/usr/include"
-
-#undef LINK_SPEC
-#define LINK_SPEC "%{h*} %{v:-V} \
-	%{b} %{Wl,*:%*} \
-	%{static:-dn -Bstatic} \
-	%{shared:-G -dy -z text} \
-	%{symbolic:-Bsymbolic -G -dy -z text} \
-	%{G:-G} \
-	%{YP,*} \
-	%{!YP,*:%{p:-Y P,/udk/usr/ccs/lib/libp:/udk/usr/lib/libp:/udk/usr/ccs/lib:/udk/usr/lib} \
-	%{!p:-Y P,/udk/usr/ccs/lib:/usr/lib}} \
-	%{Qy:} %{!Qn:-Qy}"
-
diff --git a/gcc/config/i386/unix.h b/gcc/config/i386/unix.h
deleted file mode 100755
index 3ff2075..0000000
--- a/gcc/config/i386/unix.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/* Definitions for Unix assembler syntax for the Intel 80386.
-   Copyright (C) 1988, 1994, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file defines the aspects of assembler syntax
-   that are the same for all the i386 Unix systems
-   (though they may differ in non-Unix systems).  */
-
-/* Define some concatenation macros to concatenate an opcode
-   and one, two or three operands.  In other assembler syntaxes
-   they may alter the order of ther operands.  */
-
-/* Note that the other files fail to use these
-   in some of the places where they should.  */
-
-#if defined(__STDC__) || defined(ALMOST_STDC)
-#define AS2(a,b,c) #a " " #b "," #c
-#define AS2C(b,c) " " #b "," #c
-#define AS3(a,b,c,d) #a " " #b "," #c "," #d
-#define AS1(a,b) #a " " #b
-#else
-#define AS1(a,b) "a b"
-#define AS2(a,b,c) "a b,c"
-#define AS2C(b,c) " b,c"
-#define AS3(a,b,c,d) "a b,c,d"
-#endif  
-
-/* Define macro used to output shift-double opcodes when the shift
-   count is in %cl.  Some assemblers require %cl as an argument;
-   some don't.  This macro controls what to do: by default, don't
-   print %cl.  */
-#define SHIFT_DOUBLE_OMITS_COUNT 1
-#define AS3_SHIFT_DOUBLE(a,b,c,d) \
-	(SHIFT_DOUBLE_OMITS_COUNT ? AS2 (a,c,d) : AS3 (a,b,c,d))
-
-/* Output the size-letter for an opcode.
-   CODE is the letter used in an operand spec (L, B, W, S or Q).
-   CH is the corresponding lower case letter
-     (except if CODE is `Q' then CH is `l', unless GAS_MNEMONICS).  */
-#define PUT_OP_SIZE(CODE,CH,FILE) putc (CH,(FILE))
-
-/* Opcode suffix for fullword insn.  */
-#define L_SIZE "l"
-
-/* Prefix for register names in this syntax.  */
-#define RP "%"
-
-/* Prefix for immediate operands in this syntax.  */
-#define IP "$"
-
-/* Indirect call instructions should use `*'.  */
-#define USE_STAR 1
-
-/* Prefix for a memory-operand X.  */
-#define PRINT_PTR(X, FILE)
-
-/* Delimiters that surround base reg and index reg.  */
-#define ADDR_BEG(FILE) putc('(', (FILE))
-#define ADDR_END(FILE) putc(')', (FILE))
-
-/* Print an index register (whose rtx is IREG).  */
-#define PRINT_IREG(FILE,IREG) \
-  do								\
-  { fputs (",", (FILE)); PRINT_REG ((IREG), 0, (FILE)); }	\
-  while (0)
-  
-/* Print an index scale factor SCALE.  */
-#define PRINT_SCALE(FILE,SCALE) \
-  if ((SCALE) != 1) fprintf ((FILE), ",%d", (SCALE))
-
-/* Print a base/index combination.
-   BREG is the base reg rtx, IREG is the index reg rtx,
-   and SCALE is the index scale factor (an integer).  */
-
-#define PRINT_B_I_S(BREG,IREG,SCALE,FILE) \
-  { ADDR_BEG (FILE); 				\
-    if (BREG) PRINT_REG ((BREG), 0, (FILE));	\
-    if ((IREG) != 0)				\
-      { PRINT_IREG ((FILE), (IREG));		\
-        PRINT_SCALE ((FILE), (SCALE)); }	\
-    ADDR_END (FILE); }
-
-/* Define the syntax of pseudo-ops, labels and comments.  */
-
-/* String containing the assembler's comment-starter.  */
-
-#define ASM_COMMENT_START "/"
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "/APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "/NO_APP\n"
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable (initialized) data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* Output before writable (uninitialized) data.  */
-
-#define BSS_SECTION_ASM_OP ".bss"
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  (fputs (".globl ", FILE), assemble_name (FILE, NAME), fputs ("\n", FILE))
-
-/* By default, target has a 80387, uses IEEE compatible arithmetic,
-   and returns float values in the 387.  */
-
-#define TARGET_DEFAULT (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS)
-
-/* Floating-point return values come in the FP register.  */
-
-#define VALUE_REGNO(MODE) \
-  (GET_MODE_CLASS (MODE) == MODE_FLOAT				\
-   && TARGET_FLOAT_RETURNS_IN_80387 ? FIRST_FLOAT_REG : 0)
-
-/* 1 if N is a possible register number for a function value. */
-
-#define FUNCTION_VALUE_REGNO_P(N) \
-  ((N) == 0 || ((N)== FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387))
-
-/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
-   Used for C++ multiple inheritance.  */
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION)	      \
-do {									      \
-  tree parm;								      \
-									      \
-  if (i386_regparm > 0)							      \
-    parm = TYPE_ARG_TYPES (TREE_TYPE (function));			      \
-  else									      \
-    parm = NULL_TREE;							      \
-  for (; parm; parm = TREE_CHAIN (parm))				      \
-    if (TREE_VALUE (parm) == void_type_node)				      \
-      break;								      \
-  fprintf (FILE, "\taddl $%d,%s\n", DELTA,				      \
-	   parm ? "%eax"						      \
-	   : aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? "8(%esp)" \
-	   : "4(%esp)");						      \
-									      \
-  if (flag_pic)								      \
-    {									      \
-      rtx xops[2];							      \
-      xops[0] = pic_offset_table_rtx;					      \
-      xops[1] = (rtx) gen_label_rtx ();					      \
-									      \
-      if (i386_regparm > 2)						      \
-	abort ();							      \
-      output_asm_insn ("push%L0 %0", xops);				      \
-      output_asm_insn (AS1 (call,%P1), xops);				      \
-      ASM_OUTPUT_INTERNAL_LABEL (FILE, "L", CODE_LABEL_NUMBER (xops[1]));     \
-      output_asm_insn (AS1 (pop%L0,%0), xops);				      \
-      output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops);	      \
-      fprintf (FILE, "\tmovl ");					      \
-      assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0));	      \
-      fprintf (FILE, "@GOT(%%ebx),%%ecx\n\tpopl %%ebx\n\tjmp *%%ecx\n");      \
-    }									      \
-  else									      \
-    {									      \
-      fprintf (FILE, "\tjmp ");						      \
-      assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0));	      \
-      fprintf (FILE, "\n");						      \
-    }									      \
-} while (0)
diff --git a/gcc/config/i386/v3gas.h b/gcc/config/i386/v3gas.h
deleted file mode 100755
index fe558d2..0000000
--- a/gcc/config/i386/v3gas.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* Definitions for Intel 386 running system V, using gas.
-   Copyright (C) 1992, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <i386/gas.h>
-
-/* Add stuff that normally comes from i386v.h */
-
-/* longjmp may fail to restore the registers if called from the same
-   function that called setjmp.  To compensate, the compiler avoids
-   putting variables in registers in functions that use both setjmp
-   and longjmp.  */
-
-#define NON_SAVING_SETJMP \
-  (current_function_calls_setjmp && current_function_calls_longjmp)
-
-/* longjmp may fail to restore the stack pointer if the saved frame
-   pointer is the same as the caller's frame pointer.  Requiring a frame
-   pointer in any function that calls setjmp or longjmp avoids this
-   problem, unless setjmp and longjmp are called from the same function.
-   Since a frame pointer will be required in such a function, it is OK
-   that the stack pointer is not restored.  */
-
-#undef FRAME_POINTER_REQUIRED
-#define FRAME_POINTER_REQUIRED \
-  (current_function_calls_setjmp || current_function_calls_longjmp)
-
-/* Modify ASM_OUTPUT_LOCAL slightly to test -msvr3-shlib, adapted to gas  */
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
-  do {							\
-    int align = exact_log2 (ROUNDED);			\
-    if (align > 2) align = 2;				\
-    if (TARGET_SVR3_SHLIB)				\
-      {							\
-	data_section ();				\
-	ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align); \
-	ASM_OUTPUT_LABEL ((FILE), (NAME));		\
-	fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED));	\
-      }							\
-    else						\
-      {							\
-	fputs (".lcomm ", (FILE));			\
-	assemble_name ((FILE), (NAME));			\
-	fprintf ((FILE), ",%u\n", (ROUNDED));		\
-      }							\
-  } while (0)
-
-/* Add stuff that normally comes from i386v.h via svr3.h */
-
-/* Define the actual types of some ANSI-mandated types.  These
-   definitions should work for most SVR3 systems.  */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
diff --git a/gcc/config/i386/vsta.h b/gcc/config/i386/vsta.h
deleted file mode 100755
index ee7fab9..0000000
--- a/gcc/config/i386/vsta.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Configuration for an i386 running VSTa micro-kernel.
-   Copyright (C) 1994 Free Software Foundation, Inc.
-   Contributed by Rob Savoye (rob@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define YES_UNDERSCORES
-
-#include "i386/gas.h"
-
-#ifdef CPP_PREDEFINES
-#undef CPP_PREDEFINES
-#endif
-#define CPP_PREDEFINES "-Dunix -Di386 -DVSTA \
-  -Asystem(unix) -Asystem(vsta) -Acpu(i386) -Amachine(i386)"
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_ctor, in_dtor
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS					\
-  CTOR_SECTION_FUNCTION						\
-  DTOR_SECTION_FUNCTION
-
-#define CTOR_SECTION_FUNCTION					\
-void								\
-ctor_section ()							\
-{								\
-  if (in_section != in_ctor)					\
-    {								\
-      fprintf (asm_out_file, "\t.section .ctor\n");		\
-      in_section = in_ctor;					\
-    }								\
-}
-
-#define DTOR_SECTION_FUNCTION					\
-void								\
-dtor_section ()							\
-{								\
-  if (in_section != in_dtor)					\
-    {								\
-      fprintf (asm_out_file, "\t.section .dtor\n");		\
-      in_section = in_dtor;					\
-    }								\
-}
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)	\
-  do {						\
-    ctor_section ();				\
-    fprintf (FILE, "%s\t", ASM_LONG);		\
-    assemble_name (FILE, NAME);			\
-    fprintf (FILE, "\n");			\
-  } while (0)
-
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       	\
-  do {						\
-    dtor_section ();                   		\
-    fprintf (FILE, "%s\t", ASM_LONG);		\
-    assemble_name (FILE, NAME);              	\
-    fprintf (FILE, "\n");			\
-  } while (0)
-
-
diff --git a/gcc/config/i386/vxi386.h b/gcc/config/i386/vxi386.h
deleted file mode 100755
index 1044286..0000000
--- a/gcc/config/i386/vxi386.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Definitions of target machine for GNU compiler.  VxWorks i386 version.
-   Copyright (C) 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/i386-aout.h"
-
-#define HANDLE_SYSV_PRAGMA
diff --git a/gcc/config/i386/win-nt.h b/gcc/config/i386/win-nt.h
deleted file mode 100755
index 97f10c3..0000000
--- a/gcc/config/i386/win-nt.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/* Operating system specific defines to be used when targeting GCC for
-   Windows NT 3.x on an i386.
-   Copyright (C) 1994, 1995 Free Software Foundation, Inc.
-   Contributed by Douglas B. Rupp (drupp@cs.washington.edu).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define YES_UNDERSCORES
-
-#include "i386/gas.h"
-
-#ifdef CPP_PREDEFINES
-#undef CPP_PREDEFINES
-#endif
-#define CPP_PREDEFINES "-Dunix -Di386 -DWIN32 -D_WIN32 \
-  -DWINNT -D_M_IX86=300 -D_X86_=1 -D__STDC__=0 -DALMOST_STDC -D_MSC_VER=800 \
-  -D__stdcall=__attribute__((__stdcall__)) \
-  -D__cdecl=__attribute__((__cdecl__)) \
-  -D_cdecl=__attribute__((__cdecl__)) \
-  -Asystem(unix) -Asystem(winnt) -Acpu(i386) -Amachine(i386)"
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-#define WCHAR_UNSIGNED 1
-#define WCHAR_TYPE_SIZE 16
-#define WCHAR_TYPE "short unsigned int"
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-#define HAVE_ATEXIT 1
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_ctor, in_dtor
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS					\
-  CTOR_SECTION_FUNCTION						\
-  DTOR_SECTION_FUNCTION
-
-#define CTOR_SECTION_FUNCTION					\
-void								\
-ctor_section ()							\
-{								\
-  if (in_section != in_ctor)					\
-    {								\
-      fprintf (asm_out_file, "\t.section .ctor\n");		\
-      in_section = in_ctor;					\
-    }								\
-}
-
-#define DTOR_SECTION_FUNCTION					\
-void								\
-dtor_section ()							\
-{								\
-  if (in_section != in_dtor)					\
-    {								\
-      fprintf (asm_out_file, "\t.section .dtor\n");		\
-      in_section = in_dtor;					\
-    }								\
-}
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)	\
-  do {						\
-    ctor_section ();				\
-    fprintf (FILE, "%s\t", ASM_LONG);		\
-    assemble_name (FILE, NAME);			\
-    fprintf (FILE, "\n");			\
-  } while (0)
-
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       	\
-  do {						\
-    dtor_section ();                   		\
-    fprintf (FILE, "%s\t", ASM_LONG);		\
-    assemble_name (FILE, NAME);              	\
-    fprintf (FILE, "\n");			\
-  } while (0)
-
-/* Define this macro if references to a symbol must be treated
-   differently depending on something about the variable or
-   function named by the symbol (such as what section it is in).
-
-   On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
-   so that we may access it directly in the GOT.
-
-   On i386 running Windows NT, modify the assembler name with a suffix 
-   consisting of an atsign (@) followed by string of digits that represents
-   the number of bytes of arguments passed to the function, if it has the 
-   attribute STDCALL. */
-
-#ifdef ENCODE_SECTION_INFO
-#undef ENCODE_SECTION_INFO
-#define ENCODE_SECTION_INFO(DECL) 					\
-do									\
-  {									\
-    if (flag_pic)							\
-      {									\
-	rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd'		\
-		   ? TREE_CST_RTL (DECL) : DECL_RTL (DECL));		\
-	SYMBOL_REF_FLAG (XEXP (rtl, 0))					\
-	  = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd'			\
-	     || ! TREE_PUBLIC (DECL));					\
-      }									\
-    if (TREE_CODE (DECL) == FUNCTION_DECL) 				\
-      if (lookup_attribute ("stdcall",					\
-			    TYPE_ATTRIBUTES (TREE_TYPE (DECL))))	\
-        XEXP (DECL_RTL (DECL), 0) = 					\
-          gen_rtx (SYMBOL_REF, Pmode, gen_stdcall_suffix (DECL)); 	\
-  }									\
-while (0)
-#endif
-
-/* The global __fltused is necessary to cause the printf/scanf routines
-   for outputting/inputting floating point numbers to be loaded.  Since this
-   is kind of hard to detect, we just do it all the time. */
-
-#ifdef ASM_FILE_START
-#undef ASM_FILE_START
-#endif
-#define ASM_FILE_START(FILE) \
-  do {	output_file_directive (FILE, main_input_filename);	\
-        fprintf (FILE, ".global\t__fltused\n");			\
-  } while (0)
-
-/* if the switch "-mwindows" is passed to ld, then specify to the Microsoft
-   linker the proper switches and libraries to build a graphical program */
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{mwindows:-subsystem windows -e _WinMainCRTStartup \
-  USER32.LIB%s GDI32.LIB%s COMDLG32.LIB%s WINSPOOL.LIB%s} \
- %{!mwindows:-subsystem console -e _mainCRTStartup} \
- %{mcrtmt:LIBCMT.LIB%s KERNEL32.LIB%s ADVAPI32.LIB%s} \
- %{!mcrtmt:LIBC.LIB%s KERNEL32.LIB%s ADVAPI32.LIB%s} \
- %{v}"
-
-#include "winnt/win-nt.h"
-
diff --git a/gcc/config/i386/win32.h b/gcc/config/i386/win32.h
deleted file mode 100755
index f6cc451..0000000
--- a/gcc/config/i386/win32.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/* Operating system specific defines to be used when targeting GCC for
-   hosting on Windows NT 3.x, using a Unix style C library and tools,
-   as distinct from winnt.h, which is used to build GCC for use with a
-   windows style library and tool set and uses the Microsoft tools.
-   Copyright (C) 1995-1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define YES_UNDERSCORES
-
-/* Enable parsing of #pragma pack(push,<n>) and #pragma pack(pop).  */
-#define HANDLE_PRAGMA_PACK_PUSH_POP 1
-
-#define DBX_DEBUGGING_INFO 
-#define SDB_DEBUGGING_INFO 
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#include "i386/gas.h"
-#include "dbxcoff.h"
-
-/* Augment TARGET_SWITCHES with the cygwin/win32 options. */
-#define MASK_WIN32 0x40000000 /* Use -lming32 interface */
-#define MASK_CYGWIN  0x20000000 /* Use -lcygwin interface */
-#define MASK_WINDOWS 0x10000000 /* Use windows interface */
-#define MASK_DLL     0x08000000 /* Use dll interface    */
-#define MASK_NOP_FUN_DLLIMPORT 0x20000 /* Ignore dllimport for functions */
-
-#define TARGET_WIN32             (target_flags & MASK_WIN32)
-#define TARGET_CYGWIN            (target_flags & MASK_CYGWIN)
-#define TARGET_WINDOWS           (target_flags & MASK_WINDOWS)
-#define TARGET_DLL               (target_flags & MASK_DLL)
-#define TARGET_NOP_FUN_DLLIMPORT (target_flags & MASK_NOP_FUN_DLLIMPORT)
-
-#undef  SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-    { "win32",                           MASK_WIN32 }, \
-    { "cygwin",                          MASK_CYGWIN },  \
-    { "windows",                         MASK_WINDOWS }, \
-    { "dll",                             MASK_DLL },     \
-    { "nop-fun-dllimport",		 MASK_NOP_FUN_DLLIMPORT }, \
-    { "no-nop-fun-dllimport",		 MASK_NOP_FUN_DLLIMPORT },
-
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D_WIN32 \
-  -DWINNT  -D_X86_=1 -D__STDC__=1\
-  -D__stdcall=__attribute__((__stdcall__)) \
-  -D__cdecl=__attribute__((__cdecl__)) \
-  -Asystem(winnt)"
-
-#undef STARTFILE_SPEC
-
-#define STARTFILE_SPEC "%{mdll:dllcrt0%O%s} %{!mdll: %{!mcygwin:mcrt0%O%s} \
-                        %{mcygwin:crt0%O%s} %{pg:gcrt0%O%s}}"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) %{posix:-D_POSIX_SOURCE} \
-  %{!mcygwin:-iwithprefixbefore include/mingw32 -D__MINGW32__}    \
-  %{mcygwin:-D__CYGWIN32__ -D__CYGWIN__}"
-
-/* We have to dynamic link to get to the system DLLs.  All of libc, libm and
-   the Unix stuff is in cygwin.dll.  The import library is called
-   'libcygwin.a'.  For Windows applications, include more libraries, but
-   always include kernel32.  We'd like to specific subsystem windows to
-   ld, but that doesn't work just yet.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{pg:-lgmon}						\
-		  %{!mcygwin:-lmingw32 -lmoldname -lmsvcrt -lcrtdll}	\
-                  %{mcygwin:-lcygwin} %{mwindows:-luser32 -lgdi32 -lcomdlg32} \
-                  -lkernel32 -ladvapi32 -lshell32"
-
-#define LINK_SPEC "%{mwindows:--subsystem windows} \
-  %{mdll:--dll -e _DllMainCRTStartup@12}"
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-#define WCHAR_UNSIGNED 1
-#define WCHAR_TYPE_SIZE 16
-#define WCHAR_TYPE "short unsigned int"
-/* Currently we do not have the atexit() function,
-   so take that from libgcc2.c */
-
-#define NEED_ATEXIT 1
-#define HAVE_ATEXIT 1     
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_ctor, in_dtor
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS					\
-  CTOR_SECTION_FUNCTION						\
-  DTOR_SECTION_FUNCTION
-
-#define CTOR_SECTION_FUNCTION					\
-void								\
-ctor_section ()							\
-{								\
-  if (in_section != in_ctor)					\
-    {								\
-      fprintf (asm_out_file, "\t.section .ctor\n");		\
-      in_section = in_ctor;					\
-    }								\
-}
-
-#define DTOR_SECTION_FUNCTION					\
-void								\
-dtor_section ()							\
-{								\
-  if (in_section != in_dtor)					\
-    {								\
-      fprintf (asm_out_file, "\t.section .dtor\n");		\
-      in_section = in_dtor;					\
-    }								\
-}
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)	\
-  do {						\
-    ctor_section ();				\
-    fprintf (FILE, "%s\t", ASM_LONG);		\
-    assemble_name (FILE, NAME);			\
-    fprintf (FILE, "\n");			\
-  } while (0)
-
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       	\
-  do {						\
-    dtor_section ();                   		\
-    fprintf (FILE, "%s\t", ASM_LONG);		\
-    assemble_name (FILE, NAME);              	\
-    fprintf (FILE, "\n");			\
-  } while (0)
-
-/* Define this macro if references to a symbol must be treated
-   differently depending on something about the variable or
-   function named by the symbol (such as what section it is in).
-
-   On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
-   so that we may access it directly in the GOT.
-
-   On i386 running Windows NT, modify the assembler name with a suffix 
-   consisting of an atsign (@) followed by string of digits that represents
-   the number of bytes of arguments passed to the function, if it has the 
-   attribute STDCALL. */
-
-#ifdef ENCODE_SECTION_INFO
-#undef ENCODE_SECTION_INFO
-#define ENCODE_SECTION_INFO(DECL) 					\
-do									\
-  {									\
-    if (flag_pic)							\
-      {									\
-	rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd'		\
-		   ? TREE_CST_RTL (DECL) : DECL_RTL (DECL));		\
-	SYMBOL_REF_FLAG (XEXP (rtl, 0))					\
-	  = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd'			\
-	     || ! TREE_PUBLIC (DECL));					\
-      }									\
-    if (TREE_CODE (DECL) == FUNCTION_DECL) 				\
-      if (lookup_attribute ("stdcall",					\
-			    TYPE_ATTRIBUTES (TREE_TYPE (DECL))))	\
-        XEXP (DECL_RTL (DECL), 0) = 					\
-          gen_rtx (SYMBOL_REF, Pmode, gen_stdcall_suffix (DECL)); 	\
-  }									\
-while (0)
-#endif
-
-/* This macro gets just the user-specified name
-   out of the string in a SYMBOL_REF.  Discard
-   trailing @[NUM] encoded by ENCODE_SECTION_INFO. 
-   Do we need the stripping of leading '*'?  */
-#undef  STRIP_NAME_ENCODING
-#define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME)				\
-do {									\
-  char *_p;								\
-  char *_name = ((SYMBOL_NAME) + ((SYMBOL_NAME)[0] == '*'));		\
-  for (_p = _name; *_p && *_p != '@'; ++_p)				\
-    ;									\
-  if (*_p == '@')							\
-    {									\
-      int _len = _p - _name;						\
-      (VAR) = (char *) alloca (_len + 1);				\
-      strncpy ((VAR), _name, _len);					\
-      (VAR)[_len] = '\0';						\
-    }									\
-  else									\
-    (VAR) = _name;							\
-} while (0)
-      
-
-/* Emit code to check the stack when allocating more that 4000
-   bytes in one go. */
-
-#define CHECK_STACK_LIMIT 4000
-
-/* By default, target has a 80387, uses IEEE compatible arithmetic,
-   and returns float values in the 387 and needs stack probes */
-#undef TARGET_DEFAULT
-
-#define TARGET_DEFAULT \
-   (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS | MASK_STACK_PROBE) 
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-    if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG))
-
-/* Define this macro if in some cases global symbols from one translation
-   unit may not be bound to undefined symbols in another translation unit
-   without user intervention.  For instance, under Microsoft Windows
-   symbols must be explicitly imported from shared libraries (DLLs).  */
-#define MULTIPLE_SYMBOL_SPACES
-
-#define UNIQUE_SECTION_P(DECL) DECL_ONE_ONLY (DECL)
-extern void i386_pe_unique_section ();
-#define UNIQUE_SECTION(DECL,RELOC) i386_pe_unique_section (DECL, RELOC)
-
-#define SUPPORTS_ONE_ONLY 1
-
-/* A C statement to output something to the assembler file to switch to section
-   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
-   NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
-   define this macro in such cases.  */
-#undef ASM_OUTPUT_SECTION_NAME
-#define ASM_OUTPUT_SECTION_NAME(STREAM, DECL, NAME, RELOC)	\
-do {								\
-  if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL)		\
-    fprintf (STREAM, "\t.section %s,\"x\"\n", (NAME));		\
-  else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC))	\
-    fprintf (STREAM, "\t.section %s,\"\"\n", (NAME));		\
-  else								\
-    fprintf (STREAM, "\t.section %s,\"w\"\n", (NAME));		\
-  /* Functions may have been compiled at various levels of	\
-     optimization so we can't use `same_size' here.  Instead,	\
-     have the linker pick one.  */				\
-  if ((DECL) && DECL_ONE_ONLY (DECL))				\
-    fprintf (STREAM, "\t.linkonce %s\n",			\
-	     TREE_CODE (DECL) == FUNCTION_DECL			\
-	     ? "discard" : "same_size");			\
-} while (0)
-
-#undef ASM_COMMENT_START
-#define ASM_COMMENT_START " #"
-
-/* DWARF2 Unwinding doesn't work with exception handling yet. */
-#define DWARF2_UNWIND_INFO 0
-
-/* Don't assume anything about the header files. */
-#define NO_IMPLICIT_EXTERN_C
-
-#define SUBTARGET_PROLOGUE						\
-  if (profile_flag 							\
-      && strcmp (IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),\
-		 "main") == 0)						\
-     {									\
-      rtx xops[1];							\
-      xops[0] = gen_rtx_MEM (FUNCTION_MODE,				\
-			 gen_rtx (SYMBOL_REF, Pmode, "_monstartup"));	\
-      if (do_rtl)							\
-	emit_call_insn (gen_rtx (CALL, VOIDmode, xops[0], const0_rtx));	\
-      else								\
-	output_asm_insn (AS1 (call,%P1), xops);			\
-     }
diff --git a/gcc/config/i386/winnt.c b/gcc/config/i386/winnt.c
deleted file mode 100755
index f1a2d4b..0000000
--- a/gcc/config/i386/winnt.c
+++ /dev/null
@@ -1,570 +0,0 @@
-/* Subroutines for insn-output.c for Windows NT.
-   Contributed by Douglas Rupp (drupp@cs.washington.edu)
-   Copyright (C) 1995, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include "system.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "output.h"
-#include "tree.h"
-#include "flags.h"
-
-/* i386/PE specific attribute support.
-
-   i386/PE has two new attributes:
-   dllexport - for exporting a function/variable that will live in a dll
-   dllimport - for importing a function/variable from a dll
-
-   Microsoft allows multiple declspecs in one __declspec, separating
-   them with spaces.  We do NOT support this.  Instead, use __declspec
-   multiple times.
-*/
-
-/* Return nonzero if ATTR is a valid attribute for DECL.
-   ATTRIBUTES are any existing attributes and ARGS are the arguments
-   supplied with ATTR.  */
-
-int
-i386_pe_valid_decl_attribute_p (decl, attributes, attr, args)
-     tree decl;
-     tree attributes;
-     tree attr;
-     tree args;
-{
-  if (args == NULL_TREE)
-    {
-      if (is_attribute_p ("dllexport", attr))
-	return 1;
-      if (is_attribute_p ("dllimport", attr))
-	return 1;
-    }
-
-  return i386_valid_decl_attribute_p (decl, attributes, attr, args);
-}
-
-/* Return nonzero if ATTR is a valid attribute for TYPE.
-   ATTRIBUTES are any existing attributes and ARGS are the arguments
-   supplied with ATTR.  */
-
-int
-i386_pe_valid_type_attribute_p (type, attributes, attr, args)
-     tree type;
-     tree attributes;
-     tree attr;
-     tree args;
-{
-  if (args == NULL_TREE
-      && (TREE_CODE (type) == RECORD_TYPE || TREE_CODE (type) == UNION_TYPE))
-    {
-      if (is_attribute_p ("dllexport", attr))
-	return 1;
-      if (is_attribute_p ("dllimport", attr))
-	return 1;
-    }
-
-  return i386_valid_type_attribute_p (type, attributes, attr, args);
-}
-
-/* Merge attributes in decls OLD and NEW.
-
-   This handles the following situation:
-
-   __declspec (dllimport) int foo;
-   int foo;
-
-   The second instance of `foo' nullifies the dllimport.  */
-
-tree
-i386_pe_merge_decl_attributes (old, new)
-     tree old, new;
-{
-  tree a;
-  int delete_dllimport_p;
-
-  old = DECL_MACHINE_ATTRIBUTES (old);
-  new = DECL_MACHINE_ATTRIBUTES (new);
-
-  /* What we need to do here is remove from `old' dllimport if it doesn't
-     appear in `new'.  dllimport behaves like extern: if a declaration is
-     marked dllimport and a definition appears later, then the object
-     is not dllimport'd.  */
-
-  if (lookup_attribute ("dllimport", old) != NULL_TREE
-      && lookup_attribute ("dllimport", new) == NULL_TREE)
-    delete_dllimport_p = 1;
-  else
-    delete_dllimport_p = 0;
-
-  a = merge_attributes (old, new);
-
-  if (delete_dllimport_p)
-    {
-      tree prev,t;
-
-      /* Scan the list for dllimport and delete it.  */
-      for (prev = NULL_TREE, t = a; t; prev = t, t = TREE_CHAIN (t))
-	{
-	  if (is_attribute_p ("dllimport", TREE_PURPOSE (t)))
-	    {
-	      if (prev == NULL_TREE)
-		a = TREE_CHAIN (a);
-	      else
-		TREE_CHAIN (prev) = TREE_CHAIN (t);
-	      break;
-	    }
-	}
-    }
-
-  return a;
-}
-
-/* Return the type that we should use to determine if DECL is
-   imported or exported.  */
-
-static tree
-associated_type (decl)
-     tree decl;
-{
-  tree t = NULL_TREE;
-
-  /* In the C++ frontend, DECL_CONTEXT for a method doesn't actually refer
-     to the containing class.  So we look at the 'this' arg.  */
-  if (TREE_CODE (TREE_TYPE (decl)) == METHOD_TYPE)
-    {
-      /* Artificial methods are not affected by the import/export status of
-	 their class unless they are virtual.  */
-      if (! DECL_ARTIFICIAL (decl) || DECL_VINDEX (decl))
-	t = TREE_TYPE (TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (decl))));
-    }
-  else if (DECL_CONTEXT (decl)
-	   && TREE_CODE_CLASS (TREE_CODE (DECL_CONTEXT (decl))) == 't')
-    t = DECL_CONTEXT (decl);
-
-  return t;
-}
-
-/* Return non-zero if DECL is a dllexport'd object.  */
-
-int
-i386_pe_dllexport_p (decl)
-     tree decl;
-{
-  tree exp;
-
-  if (TREE_CODE (decl) != VAR_DECL
-      && TREE_CODE (decl) != FUNCTION_DECL)
-    return 0;
-  exp = lookup_attribute ("dllexport", DECL_MACHINE_ATTRIBUTES (decl));
-  if (exp)
-    return 1;
-
-  /* Class members get the dllexport status of their class.  */
-  if (associated_type (decl))
-    {
-      exp = lookup_attribute ("dllexport",
-			      TYPE_ATTRIBUTES (associated_type (decl)));
-      if (exp)
-	return 1;
-    }
-
-  return 0;
-}
-
-/* Return non-zero if DECL is a dllimport'd object.  */
-
-int
-i386_pe_dllimport_p (decl)
-     tree decl;
-{
-  tree imp;
-
-  if (TREE_CODE (decl) == FUNCTION_DECL
-      && TARGET_NOP_FUN_DLLIMPORT)
-    return 0;
-
-  if (TREE_CODE (decl) != VAR_DECL
-      && TREE_CODE (decl) != FUNCTION_DECL)
-    return 0;
-  imp = lookup_attribute ("dllimport", DECL_MACHINE_ATTRIBUTES (decl));
-  if (imp)
-    return 1;
-
-  /* Class members get the dllimport status of their class.  */
-  if (associated_type (decl))
-    {
-      imp = lookup_attribute ("dllimport",
-			      TYPE_ATTRIBUTES (associated_type (decl)));
-      if (imp)
-	return 1;
-    }
-
-  return 0;
-}
-
-/* Return non-zero if SYMBOL is marked as being dllexport'd.  */
-
-int
-i386_pe_dllexport_name_p (symbol)
-     char *symbol;
-{
-  return symbol[0] == '@' && symbol[1] == 'e' && symbol[2] == '.';
-}
-
-/* Return non-zero if SYMBOL is marked as being dllimport'd.  */
-
-int
-i386_pe_dllimport_name_p (symbol)
-     char *symbol;
-{
-  return symbol[0] == '@' && symbol[1] == 'i' && symbol[2] == '.';
-}
-
-/* Mark a DECL as being dllexport'd.
-   Note that we override the previous setting (eg: dllimport).  */
-
-void
-i386_pe_mark_dllexport (decl)
-     tree decl;
-{
-  char *oldname, *newname;
-  rtx rtlname;
-  tree idp;
-
-  rtlname = XEXP (DECL_RTL (decl), 0);
-  if (GET_CODE (rtlname) == SYMBOL_REF)
-    oldname = XSTR (rtlname, 0);
-  else if (GET_CODE (rtlname) == MEM
-	   && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
-    oldname = XSTR (XEXP (rtlname, 0), 0);
-  else
-    abort ();
-  if (i386_pe_dllimport_name_p (oldname))
-    oldname += 9;
-  else if (i386_pe_dllexport_name_p (oldname))
-    return; /* already done */
-
-  newname = alloca (strlen (oldname) + 4);
-  sprintf (newname, "@e.%s", oldname);
-
-  /* We pass newname through get_identifier to ensure it has a unique
-     address.  RTL processing can sometimes peek inside the symbol ref
-     and compare the string's addresses to see if two symbols are
-     identical.  */
-  idp = get_identifier (newname);
-
-  XEXP (DECL_RTL (decl), 0) =
-    gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (idp));
-}
-
-/* Mark a DECL as being dllimport'd.  */
-
-void
-i386_pe_mark_dllimport (decl)
-     tree decl;
-{
-  char *oldname, *newname;
-  tree idp;
-  rtx rtlname, newrtl;
-
-  rtlname = XEXP (DECL_RTL (decl), 0);
-  if (GET_CODE (rtlname) == SYMBOL_REF)
-    oldname = XSTR (rtlname, 0);
-  else if (GET_CODE (rtlname) == MEM
-	   && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
-    oldname = XSTR (XEXP (rtlname, 0), 0);
-  else
-    abort ();
-  if (i386_pe_dllexport_name_p (oldname))
-    {
-      error ("`%s' declared as both exported to and imported from a DLL.",
-             IDENTIFIER_POINTER (DECL_NAME (decl)));
-      return;
-    }
-  else if (i386_pe_dllimport_name_p (oldname))
-    {
-      /* Already done, but force correct linkage since the redeclaration 
-         might have omitted explicit extern.  Sigh.  */
-      if (TREE_CODE (decl) == VAR_DECL
-	  /* ??? Is this test for vtables needed?  */
-	  && !DECL_VIRTUAL_P (decl))
-	{
-	  DECL_EXTERNAL (decl) = 1;
-	  TREE_PUBLIC (decl) = 1;
-	}
-      return;
-    }
-
-  /* ??? One can well ask why we're making these checks here,
-     and that would be a good question.  */
-
-  /* Imported variables can't be initialized. Note that C++ classes
-     are marked initial, so we need to check.  */
-  if (TREE_CODE (decl) == VAR_DECL
-      && !DECL_VIRTUAL_P (decl)
-      && (DECL_INITIAL (decl)
-          && ! TYPE_NEEDS_CONSTRUCTING (TREE_TYPE (decl))))
-    {
-      error_with_decl (decl, "initialized variable `%s' is marked dllimport");
-      return;
-    }
-  /* Nor can they be static.  */
-  if (TREE_CODE (decl) == VAR_DECL
-      /* ??? Is this test for vtables needed?  */
-      && !DECL_VIRTUAL_P (decl)
-      && 0 /*???*/)
-    {
-      error_with_decl (decl, "static variable `%s' is marked dllimport");
-      return;
-    }
-
-  /* `extern' needn't be specified with dllimport.
-     Specify `extern' now and hope for the best.  Sigh.  */
-  if (TREE_CODE (decl) == VAR_DECL
-      /* ??? Is this test for vtables needed?  */
-      && !DECL_VIRTUAL_P (decl))
-    {
-      DECL_EXTERNAL (decl) = 1;
-      TREE_PUBLIC (decl) = 1;
-    }
-
-  newname = alloca (strlen (oldname) + 11);
-  sprintf (newname, "@i._imp__%s", oldname);
-
-  /* We pass newname through get_identifier to ensure it has a unique
-     address.  RTL processing can sometimes peek inside the symbol ref
-     and compare the string's addresses to see if two symbols are
-     identical.  */
-  idp = get_identifier (newname);
-
-  newrtl = gen_rtx (MEM, Pmode,
-		    gen_rtx (SYMBOL_REF, Pmode,
-			     IDENTIFIER_POINTER (idp)));
-  XEXP (DECL_RTL (decl), 0) = newrtl;
-
-  /* Can't treat a pointer to this as a constant address */
-  DECL_NON_ADDR_CONST_P (decl) = 1;
-}
-
-/* Return string which is the former assembler name modified with a 
-   suffix consisting of an atsign (@) followed by the number of bytes of 
-   arguments */
-
-char *
-gen_stdcall_suffix (decl)
-  tree decl;
-{
-  int total = 0;
-  /* ??? This probably should use XSTR (XEXP (DECL_RTL (decl), 0), 0) instead
-     of DECL_ASSEMBLER_NAME.  */
-  char *asmname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
-  char *newsym;
-
-  if (TYPE_ARG_TYPES (TREE_TYPE (decl)))
-    if (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (decl)))) 
-        == void_type_node)
-      {
-	tree formal_type = TYPE_ARG_TYPES (TREE_TYPE (decl));
-
-	while (TREE_VALUE (formal_type) != void_type_node)
-	  {
-	    int parm_size
-	      = TREE_INT_CST_LOW (TYPE_SIZE (TREE_VALUE (formal_type)));
-	    /* Must round up to include padding.  This is done the same
-	       way as in store_one_arg.  */
-	    parm_size = ((parm_size + PARM_BOUNDARY - 1)
-			 / PARM_BOUNDARY * PARM_BOUNDARY);
-	    total += parm_size;
-	    formal_type = TREE_CHAIN (formal_type);
-	  }
-      }
-
-  newsym = xmalloc (strlen (asmname) + 10);
-  sprintf (newsym, "%s@%d", asmname, total/BITS_PER_UNIT);
-  return IDENTIFIER_POINTER (get_identifier (newsym));
-}
-
-/* Cover function to implement ENCODE_SECTION_INFO.  */
-
-void
-i386_pe_encode_section_info (decl)
-     tree decl;
-{
-  /* This bit is copied from i386.h.  */
-  if (optimize > 0 && TREE_CONSTANT (decl)
-      && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST))
-    {
-      rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
-                 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
-      SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
-    }
-
-  if (TREE_CODE (decl) == FUNCTION_DECL)
-    if (lookup_attribute ("stdcall",
-			  TYPE_ATTRIBUTES (TREE_TYPE (decl))))
-      XEXP (DECL_RTL (decl), 0) = 
-	gen_rtx (SYMBOL_REF, Pmode, gen_stdcall_suffix (decl));
-
-  /* Mark the decl so we can tell from the rtl whether the object is
-     dllexport'd or dllimport'd.  */
-
-  if (i386_pe_dllexport_p (decl))
-    i386_pe_mark_dllexport (decl);
-  else if (i386_pe_dllimport_p (decl))
-    i386_pe_mark_dllimport (decl);
-  /* It might be that DECL has already been marked as dllimport, but a
-     subsequent definition nullified that.  The attribute is gone but
-     DECL_RTL still has @i._imp__foo.  We need to remove that. Ditto
-     for the DECL_NON_ADDR_CONST_P flag.  */
-  else if ((TREE_CODE (decl) == FUNCTION_DECL
-	    || TREE_CODE (decl) == VAR_DECL)
-	   && DECL_RTL (decl) != NULL_RTX
-	   && GET_CODE (DECL_RTL (decl)) == MEM
-	   && GET_CODE (XEXP (DECL_RTL (decl), 0)) == MEM
-	   && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF
-	   && i386_pe_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0)))
-    {
-      char *oldname = XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0);
-      tree idp = get_identifier (oldname + 9);
-      rtx newrtl = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (idp));
-
-      XEXP (DECL_RTL (decl), 0) = newrtl;
-
-      DECL_NON_ADDR_CONST_P (decl) = 0;
-
-      /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
-	 We leave these alone for now.  */
-    }
-}
-
-/* Cover function for UNIQUE_SECTION.  */
-
-void
-i386_pe_unique_section (decl, reloc)
-     tree decl;
-     int reloc;
-{
-  int len;
-  char *name,*string,*prefix;
-
-  name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
-  /* Strip off any encoding in fnname.  */
-  STRIP_NAME_ENCODING (name, name);
-
-  /* The object is put in, for example, section .text$foo.
-     The linker will then ultimately place them in .text
-     (everything from the $ on is stripped). Don't put
-     read-only data in .rdata section to avoid a PE linker 
-     bug when .rdata$* grouped sections are used in code
-     without a .rdata section.  */
-  if (TREE_CODE (decl) == FUNCTION_DECL)
-    prefix = ".text$";
-  else if (DECL_READONLY_SECTION (decl, reloc))
-#ifdef READONLY_DATA_SECTION
-    prefix = ".rdata$";
-#else
-    prefix = ".text$";
-#endif
-  else
-    prefix = ".data$";
-  len = strlen (name) + strlen (prefix);
-  string = alloca (len + 1);
-  sprintf (string, "%s%s", prefix, name);
-
-  DECL_SECTION_NAME (decl) = build_string (len, string);
-}
-
-/* The Microsoft linker requires that every function be marked as
-   DT_FCN.  When using gas on cygwin, we must emit appropriate .type
-   directives.  */
-
-#include "gsyms.h"
-
-/* Mark a function appropriately.  This should only be called for
-   functions for which we are not emitting COFF debugging information.
-   FILE is the assembler output file, NAME is the name of the
-   function, and PUBLIC is non-zero if the function is globally
-   visible.  */
-
-void
-i386_pe_declare_function_type (file, name, public)
-     FILE *file;
-     char *name;
-     int public;
-{
-  fprintf (file, "\t.def\t");
-  assemble_name (file, name);
-  fprintf (file, ";\t.scl\t%d;\t.type\t%d;\t.endef\n",
-	   public ? (int) C_EXT : (int) C_STAT,
-	   (int) DT_FCN << N_BTSHFT);
-}
-
-/* Keep a list of external functions.  */
-
-struct extern_list
-{
-  struct extern_list *next;
-  char *name;
-};
-
-static struct extern_list *extern_head;
-
-/* Assemble an external function reference.  We need to keep a list of
-   these, so that we can output the function types at the end of the
-   assembly.  We can't output the types now, because we might see a
-   definition of the function later on and emit debugging information
-   for it then.  */
-
-void
-i386_pe_record_external_function (name)
-     char *name;
-{
-  struct extern_list *p;
-
-  p = (struct extern_list *) permalloc (sizeof *p);
-  p->next = extern_head;
-  p->name = name;
-  extern_head = p;
-}
-
-/* This is called at the end of assembly.  For each external function
-   which has not been defined, we output a declaration now.  */
-
-void
-i386_pe_asm_file_end (file)
-     FILE *file;
-{
-  struct extern_list *p;
-
-  for (p = extern_head; p != NULL; p = p->next)
-    {
-      tree decl;
-
-      decl = get_identifier (p->name);
-
-      /* Positively ensure only one declaration for any given symbol.  */
-      if (! TREE_ASM_WRITTEN (decl) && TREE_SYMBOL_REFERENCED (decl))
-	{
-	  TREE_ASM_WRITTEN (decl) = 1;
-	  i386_pe_declare_function_type (file, p->name, TREE_PUBLIC (decl));
-	}
-    }
-}
diff --git a/gcc/config/i386/x-aix b/gcc/config/i386/x-aix
deleted file mode 100755
index b191e48..0000000
--- a/gcc/config/i386/x-aix
+++ /dev/null
@@ -1,12 +0,0 @@
-# There is an alloca in -lbsd, but it is limited to 32K
-ALLOCA = alloca.o
-
-# If you are running out of memory while compiling gcc, with the standard
-# /bin/cc uncomment MALLOCLIB line. That version of malloc is slower but
-# has less overhead than the one in libc.
-#MALLOCLIB = -lmalloc
-
-# Uncomment out the next line if you want to link with the shareable libc_s.
-#CLIB_S = -lc_s
-
-CLIB = -lld $(MALLOCLIB) $(CLIB_S)
diff --git a/gcc/config/i386/x-cygwin b/gcc/config/i386/x-cygwin
deleted file mode 100755
index f251835..0000000
--- a/gcc/config/i386/x-cygwin
+++ /dev/null
@@ -1,4 +0,0 @@
-# Don't run fixproto
-STMP_FIXPROTO =
-# prefix.c wants to poke around the Registry
-CLIB = -ladvapi32
diff --git a/gcc/config/i386/x-dgux b/gcc/config/i386/x-dgux
deleted file mode 100755
index 322bfe3..0000000
--- a/gcc/config/i386/x-dgux
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# host is ix86 running dgux
-#
-CC = /bin/gcc
-X_CFLAGS = -O -mstandard -mlegend
-BOOT_CFLAGS = -O2 -g -mstandard -mlegend $(CFLAGS)
-CLIB = -lw32
-RANLIB = true
-USER_H = $(EXTRA_HEADERS) $(LANG_EXTRA_HEADERS)
-STMP_FIXPROTO = 
-
diff --git a/gcc/config/i386/x-go32 b/gcc/config/i386/x-go32
deleted file mode 100755
index ee7fc6d..0000000
--- a/gcc/config/i386/x-go32
+++ /dev/null
@@ -1,47 +0,0 @@
-# CYGNUS LOCAL WTF/law
-# This is ugly but x-go32 is only ever used in a Canadian cross
-# and passing down all these things as environment variables is
-# amazingly tedious and error prone.
-HOST_CC=gcc
-HOST_CFLAGS=
-CFLAGS=-O2 -fno-omit-frame-pointer
-HOST_PREFIX=foo
-HOST_PREFIX_1=foo
-RANLIB=i386-go32-ranlib
-AR=i386-go32-ar
-GCC_FOR_TARGET=${target}-gcc
-AR_FOR_TARGET=${target}-ar
-RANLIB_FOR_TARGET=${target}-ranlib
-CLIB=-lm
-CC=i386-go32-gcc
-# FIXME: This should be done in a better way, but how?  The problem is
-# that we can't build protoize.
-LANGUAGES=c c++
-
-# FIXME: Until collect supports DOS, don't use it.
-USE_COLLECT2 =
-# END CYGNUS LOCAL
-
-# translate the version string, so it can be used on DJGPP, where only
-# one dot in filename is allowed
-
-# to avoid recursion when redefining $(version)
-_version:=$(version)
-__version=$(subst ., ,$(_version))
-version=$(word 1,$(__version))$(word 2,$(__version)).$(word 3,$(__version))
-
-SYSTEM_HEADER_DIR=$(DJDIR)/include
-X_CPPFLAGS=-DSTANDARD_INCLUDE_DIR=\"\$$DJDIR/include\" \
-	   -DSTANDARD_INCLUDE_COMPONENT=\"\"
-
-# when building a native compiler for DJGPP, make the target_alias
-# a shorter name, since otherwise it will produce some problems, when
-# using the same gcc once with long filenames and once with short (8+3)
-# filenames
-ifeq ($(findstring -pc-msdosdjgpp,$(target_alias)),-pc-msdosdjgpp)
-target_alias=djgpp
-endif
-
-# on DJGPP the 'ln -s' does not work correctly
-LN = cp -p
-LN_S = cp -p
diff --git a/gcc/config/i386/x-isc b/gcc/config/i386/x-isc
deleted file mode 100755
index ea65ec8..0000000
--- a/gcc/config/i386/x-isc
+++ /dev/null
@@ -1,3 +0,0 @@
-CLIB = -lPW -lcposix
-X_CFLAGS = -D_POSIX_SOURCE
-ENQUIRE_LDFLAGS = -posix $(LDFLAGS)
diff --git a/gcc/config/i386/x-isc3 b/gcc/config/i386/x-isc3
deleted file mode 100755
index 527cca8..0000000
--- a/gcc/config/i386/x-isc3
+++ /dev/null
@@ -1,4 +0,0 @@
-CLIB = -lPW
-# One person said it needs -DPOSIX_JC, but daa@CERF.NET says no.
-X_CFLAGS = -D_SYSV3 -Xp
-ENQUIRE_LDFLAGS = $(LDFLAGS)
diff --git a/gcc/config/i386/x-ncr3000 b/gcc/config/i386/x-ncr3000
deleted file mode 100755
index 4ae168b..0000000
--- a/gcc/config/i386/x-ncr3000
+++ /dev/null
@@ -1,34 +0,0 @@
-# Makefile additions for the NCR3000 as host system.
-
-# Using -O with the AT&T compiler fails, with a message about a missing
-# /usr/ccs/lib/optim pass.  So override the default in Makefile.in
-
-CCLIBFLAGS=
-
-## Supposedly not needed now that xm-sysv4.h includes alloc.h for Metaware.
-### NCR3000 ships with a MetaWare compiler installed as CC, which chokes and
-### dies all over the place on GCC source.  However, the AT&T compiler,
-### crusty as it is, can be used to bootstrap GCC.  It can be found in
-### /usr/ccs/ATT/cc.  It is also used to compile the things that should
-### not be compiled with GCC.
-##
-##CC = /usr/ccs/ATT/cc
-##OLDCC = /usr/ccs/ATT/cc
-
-# The rest is just x-i386v4.
-
-# Some versions of SVR4 have an alloca in /usr/ucblib/libucb.a, and if we are
-# careful to link that in after libc we can use it, but since newer versions of
-# SVR4 are dropping libucb, it is better to just use the portable C version for
-# bootstrapping.  Do this by defining ALLOCA.
-
-ALLOCA = alloca.o
-
-# We used to build all stages *without* shared libraries because that may make
-# debugging the compiler easier (until there is a GDB which supports
-# both Dwarf *and* svr4 shared libraries).
-
-# But james@bigtex.cactus.org says that redefining GCC_CFLAGS causes trouble,
-# and that it is easy enough to debug using shared libraries.
-# CCLIBFLAGS=-Bstatic -dn -g
-# GCC_CFLAGS=-static -g -O2 -B./
diff --git a/gcc/config/i386/x-next b/gcc/config/i386/x-next
deleted file mode 100755
index a16b918..0000000
--- a/gcc/config/i386/x-next
+++ /dev/null
@@ -1,3 +0,0 @@
-# Make assignments for compiling on NeXT with their compiler version.
-CC=cc -traditional-cpp
-OLDCC=cc -traditional-cpp
diff --git a/gcc/config/i386/x-osf1elf b/gcc/config/i386/x-osf1elf
deleted file mode 100755
index 1467381..0000000
--- a/gcc/config/i386/x-osf1elf
+++ /dev/null
@@ -1,8 +0,0 @@
-# Defaults for OSF/1 1.3+
-CC		= $(OLDCC)
-CLIB		= -lld
-INSTALL		= installbsd -c
-OLDCC		= /usr/ccs/gcc/gcc
-X_CFLAGS	= -static
-
-# FIXPROTO_DEFINES = -D_XOPEN_SOURCE
diff --git a/gcc/config/i386/x-osfrose b/gcc/config/i386/x-osfrose
deleted file mode 100755
index 2c5e3ba..0000000
--- a/gcc/config/i386/x-osfrose
+++ /dev/null
@@ -1,27 +0,0 @@
-# Define CC and OLDCC as the same, so that the tests:
-#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
-#
-# will succeed (if OLDCC != CC, it is assumed that GCC is
-# being used in secondary stage builds).
-
-BUILD		=
-CC		= $(OLDCC)
-CLIB		= -lld
-X_CFLAGS	= $(DEB_OPT) $(MSTATS) $(X_DEFINES)
-X_CFLAGS_NODEBUG = $(NO_DEBUG) $(MSTATS) $(OPT) $(PROFILE) $(X_DEFINES) $(XCFLAGS)
-XCFLAGS		= $(SHLIB)
-CPP_ABORT	= # -Dabort=fancy_abort
-CPPFLAGS	= $(CPP_ABORT) $(SYSTEM_INCLUDES)
-DEB_OPT		= $(OPT) $(DEBUG) $(PROFILE)
-DEBUG		= 
-DEBUG_COLLECT	= # -DDEBUG
-CCLIBFLAGS	= -O -DNO_HALF_PIC
-GCC_CFLAGS	= $(INTERNAL_CFLAGS) $(X_CFLAGS) $(T_CFLAGS) $(CFLAGS) -B./ -DPOSIX -DNO_HALF_PIC
-LDFLAGS		=
-MSTATS		= # -mstats
-OLDCC		= /usr/ccs/gcc/gcc
-OPT		= -O
-PROFILE		=
-SHLIB		= -pic-none
-SYSTEM_INCLUDES	= # -I${BUILD}/usr/include
-X_DEFINES	= -Dvfork=fork
diff --git a/gcc/config/i386/x-sco b/gcc/config/i386/x-sco
deleted file mode 100755
index f7f14e9..0000000
--- a/gcc/config/i386/x-sco
+++ /dev/null
@@ -1,7 +0,0 @@
-RANLIB = :
-RANLIB_TEST = false
-CC = rcc $(RCCFLAGS)
-OLDCC = rcc $(RCCFLAGS)
-RCCFLAGS = -Dunix -Di386 -DM_UNIX -DM_I386 -DNULL=0
-CCLIBFLAGS =
-CLIB = -lmalloc -lPW
diff --git a/gcc/config/i386/x-sco4 b/gcc/config/i386/x-sco4
deleted file mode 100755
index be6080f..0000000
--- a/gcc/config/i386/x-sco4
+++ /dev/null
@@ -1,10 +0,0 @@
-RANLIB = :
-RANLIB_TEST = false
-CC = rcc $(RCCFLAGS)
-OLDCC = rcc $(RCCFLAGS)
-RCCFLAGS = -Dunix -Di386 -DM_UNIX -DM_I386 -DNULL=0
-CCLIBFLAGS =
-CLIB = -lmalloc -lPW
-
-# See all the declarations.
-FIXPROTO_DEFINES = -D_XOPEN_SOURCE
diff --git a/gcc/config/i386/x-sco5 b/gcc/config/i386/x-sco5
deleted file mode 100755
index e13ed74..0000000
--- a/gcc/config/i386/x-sco5
+++ /dev/null
@@ -1,10 +0,0 @@
-RANLIB = :
-RANLIB_TEST = false
-CC = cc
-OLDCC = cc
-CCLIBFLAGS =
-# We avoid the ALLOCA in -lPW becuase it gives us an evil index()
-ALLOCA = alloca.o
-
-# See all the declarations.
-FIXPROTO_DEFINES = -D_XOPEN_SOURCE -D_POSIX_C_SOURCE=2
diff --git a/gcc/config/i386/x-sysv3 b/gcc/config/i386/x-sysv3
deleted file mode 100755
index a1391df..0000000
--- a/gcc/config/i386/x-sysv3
+++ /dev/null
@@ -1 +0,0 @@
-CLIB=-lPW
diff --git a/gcc/config/i386/x-vsta b/gcc/config/i386/x-vsta
deleted file mode 100755
index e2279a4..0000000
--- a/gcc/config/i386/x-vsta
+++ /dev/null
@@ -1 +0,0 @@
-CLIB=-lm
diff --git a/gcc/config/i386/xm-aix.h b/gcc/config/i386/xm-aix.h
deleted file mode 100755
index 4cbd36e..0000000
--- a/gcc/config/i386/xm-aix.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#undef TRUE
-#undef FALSE
diff --git a/gcc/config/i386/xm-bsd386.h b/gcc/config/i386/xm-bsd386.h
deleted file mode 100755
index 6b8eee7..0000000
--- a/gcc/config/i386/xm-bsd386.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/* Configuration for GCC for Intel i386 running BSDI's BSD/386 as host.  */
-
-#include "i386/xm-i386.h"
diff --git a/gcc/config/i386/xm-cygwin.h b/gcc/config/i386/xm-cygwin.h
deleted file mode 100755
index 4b166eb..0000000
--- a/gcc/config/i386/xm-cygwin.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Configuration for GNU C-compiler for hosting on Windows NT.
-   using a unix style C library.
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define EXECUTABLE_SUFFIX ".exe"
-#define NO_SYS_SIGLIST 1
-#define HAVE_BCOPY 1
-#define HAVE_BZERO 1
-#define HAVE_BCMP 1
-#define HAVE_RINDEX 1
-#define HAVE_INDEX 1
-
-/* We support both "/" and "\" since everybody tests both but we
-   default to "/".  This is important because if gcc produces Win32
-   paths containing backslashes, make and configure may treat the
-   backslashes as escape characters.  Many Win32 programs use forward
-   slashes so using a forward slash shouldn't be problematic from the
-   perspective of wanting gcc to produce native Win32 paths. */
-#define DIR_SEPARATOR '/'
-
-/* If we allow both '/' and '\' as dir separators, then
-   allow both unix and win32 PATH syntax. */
-#undef GET_ENV_PATH_LIST
-#define GET_ENV_PATH_LIST(VAR,NAME)					\
-do {									\
-  char *_epath;								\
-  char *_win32epath;							\
-  _epath = _win32epath = getenv (NAME);					\
-  /* if we have a posix path list, convert to win32 path list */	\
-  if (_epath != NULL && *_epath != 0					\
-      && cygwin32_posix_path_list_p (_epath))				\
-    {									\
-      _win32epath = (char *) xmalloc					\
-	(cygwin32_posix_to_win32_path_list_buf_size (_epath));		\
-      cygwin32_posix_to_win32_path_list (_epath, _win32epath);		\
-    }									\
-  (VAR) = _win32epath;							\
-} while (0)
-
-#define PATH_SEPARATOR ';'
-
-/* This is needed so that protoize will compile.  */
-#ifndef POSIX
-#define POSIX
-#endif
diff --git a/gcc/config/i386/xm-dgux.h b/gcc/config/i386/xm-dgux.h
deleted file mode 100755
index 5bdb9be..0000000
--- a/gcc/config/i386/xm-dgux.h
+++ /dev/null
@@ -1,12 +0,0 @@
-
-/* Configuration for GCC for Intel i386 running DG/ux */
-
-/* looks just like sysv4 for now */
-
-#include "i386/xm-i386.h"
-#include "xm-svr4.h"
-
-/* If not compiled with GNU C, use the portable alloca.  */
-#ifndef __GNUC__
-#define USE_C_ALLOCA
-#endif
diff --git a/gcc/config/i386/xm-dos.h b/gcc/config/i386/xm-dos.h
deleted file mode 100755
index a734a81..0000000
--- a/gcc/config/i386/xm-dos.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#include "i386/xm-i386.h"
-
-/* Use semicolons to separate elements of a path.  */
-#define PATH_SEPARATOR ';'
-
-/* Use backslashs to separate levels of directory.  */
-#define DIR_SEPARATOR '\\'
-
-/* Suffix for executable file names.  */
-#define EXECUTABLE_SUFFIX ".exe"
-
-#define MKTEMP_EACH_FILE 1
-
-#define NO_PRECOMPILES 1
diff --git a/gcc/config/i386/xm-freebsd.h b/gcc/config/i386/xm-freebsd.h
deleted file mode 100755
index 007a609..0000000
--- a/gcc/config/i386/xm-freebsd.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/* Configuration for GCC for Intel i386 running FreeBSD as host.  */
-
-#include <i386/xm-i386.h>
-#include <xm-freebsd.h>
diff --git a/gcc/config/i386/xm-gnu.h b/gcc/config/i386/xm-gnu.h
deleted file mode 100755
index 0b5985f..0000000
--- a/gcc/config/i386/xm-gnu.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* Configuration for GCC for Intel i386 running GNU as host.  */
-
-#include <i386/xm-i386.h>
-#include <xm-gnu.h>
-
diff --git a/gcc/config/i386/xm-go32.h b/gcc/config/i386/xm-go32.h
deleted file mode 100755
index a66889c..0000000
--- a/gcc/config/i386/xm-go32.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Configuration for GNU C-compiler for Intel 80386 running GO32.
-   Copyright (C) 1988, 1996, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define __MSDOS__ 1
-
-#include "i386/xm-i386.h"
-
-/* Use semicolons to separate elements of a path.  */
-#define PATH_SEPARATOR ';'
-
-#define EXECUTABLE_SUFFIX ".exe"
-
-/* Even though we support "/", allow "\" since everybody tests both.  */
-#define DIR_SEPARATOR '\\'
-
-#define NO_SYS_SIGLIST 1
-
-#define LIBSTDCXX "-lstdcxx"
-
diff --git a/gcc/config/i386/xm-isc.h b/gcc/config/i386/xm-isc.h
deleted file mode 100755
index e686c5e..0000000
--- a/gcc/config/i386/xm-isc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef REAL_ARITHMETIC
-#define REAL_VALUE_ATOF(x, mode) strtod ((x), (char **)0)
-extern double strtod ();
-#endif
diff --git a/gcc/config/i386/xm-linux.h b/gcc/config/i386/xm-linux.h
deleted file mode 100755
index 713bf3b..0000000
--- a/gcc/config/i386/xm-linux.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Configuration for GCC for Intel i386 running Linux-based GNU systems.
-   Copyright (C) 1993, 1994, 1995, 1997 Free Software Foundation, Inc.
-   Contributed by H.J. Lu (hjl@nynexst.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <i386/xm-i386.h>
-#include <xm-linux.h>
-
diff --git a/gcc/config/i386/xm-lynx.h b/gcc/config/i386/xm-lynx.h
deleted file mode 100755
index 359e41b..0000000
--- a/gcc/config/i386/xm-lynx.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Configuration for GNU C-compiler for i386 platforms running LynxOS.
-   Copyright (C) 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <xm-lynx.h>
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-
-#include "tm.h"
diff --git a/gcc/config/i386/xm-mingw32.h b/gcc/config/i386/xm-mingw32.h
deleted file mode 100755
index d818142..0000000
--- a/gcc/config/i386/xm-mingw32.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Configuration for GNU C-compiler for hosting on Windows32.
-   using GNU tools and the Windows32 API Library.
-   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#ifndef USG
-#define USG 1
-#endif
-
-#ifndef ONLY_INT_FIELD
-#define ONLY_INT_FIELDS 1
-#endif
-
-#ifndef USE_PROTOTYPES
-#define USE_PROTOTYPES 1
-#endif
-
-#define NO_SYS_SIGLIST 1
-#define environ _environ
-
-/* Even though we support "/", allow "\" since everybody tests both.  */
-#define DIR_SEPARATOR '\\'
-#define EXECUTABLE_SUFFIX ".exe"
-
-#undef PATH_SEPARATOR
-#define PATH_SEPARATOR ';'
diff --git a/gcc/config/i386/xm-netbsd.h b/gcc/config/i386/xm-netbsd.h
deleted file mode 100755
index 3a9f324..0000000
--- a/gcc/config/i386/xm-netbsd.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/* Configuration for GCC for Intel i386 running NetBSD as host.  */
-
-#include <i386/xm-i386.h>
-#include <xm-netbsd.h>
diff --git a/gcc/config/i386/xm-next.h b/gcc/config/i386/xm-next.h
deleted file mode 100755
index bf90328..0000000
--- a/gcc/config/i386/xm-next.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "i386/xm-i386.h"
-
-/* malloc does better with chunks the size of a page.  */ 
-
-#define OBSTACK_CHUNK_SIZE (getpagesize ())
diff --git a/gcc/config/i386/xm-os2.h b/gcc/config/i386/xm-os2.h
deleted file mode 100755
index aed925e..0000000
--- a/gcc/config/i386/xm-os2.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Configuration for GNU compiler
-   for an Intel i386 or later processor running OS/2 2.x.
-   Copyright (C) 1993, 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Samuel Figueroa (figueroa@apple.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#ifndef OS2
-#define OS2
-#endif
-
-#ifdef __IBMC__
-#include <stdlib.h> /* this defines alloca */
-#define USG
-#define ONLY_INT_FIELDS
-#define USE_PROTOTYPES 1
-#define strcasecmp stricmp
-#define kill(a,b) raise(b)
-#define mktemp tmpnam
-#else
-#ifdef __EMX__
-#define EMX
-#define USG
-#define BSTRING
-#define HAVE_PUTENV
-#define HAVE_VPRINTF
-#define HAVE_STRERROR
-#define strcasecmp stricmp
-#else
-#define ____386BSD____
-int spawnv (int modeflag, char *path, char *argv[]);
-int spawnvp (int modeflag, char *path, char *argv[]);
-#endif /* __EMX__ */
-#endif /* __IBMC__ */
-
-#ifndef PATH_SEPARATOR
-#define PATH_SEPARATOR ';'
-#endif
-#ifndef DIR_SEPARATOR
-#define DIR_SEPARATOR '\\'
-#endif
-
-#define EXECUTABLE_SUFFIX ".exe"
-
-/* The EMX compiler uses regular .o files */
-#ifndef __EMX__
-#define OBJECT_SUFFIX ".obj"
-#endif
-
-/* This is required to make temporary file names unique on file
-   systems which severely restrict the length of file names. */
-#define MKTEMP_EACH_FILE
-
-#include "i386/xm-i386.h"
diff --git a/gcc/config/i386/xm-osf.h b/gcc/config/i386/xm-osf.h
deleted file mode 100755
index 4cbd36e..0000000
--- a/gcc/config/i386/xm-osf.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#undef TRUE
-#undef FALSE
diff --git a/gcc/config/i386/xm-osf1elf.h b/gcc/config/i386/xm-osf1elf.h
deleted file mode 100755
index 69ca9c1..0000000
--- a/gcc/config/i386/xm-osf1elf.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Configuration for GCC for Intel i386 running OSF/1 1.3.  */
-
-#ifndef HZ
-#include <machine/machtime.h>
-#define HZ DEFAULT_CLK_TCK
-#endif
diff --git a/gcc/config/i386/xm-sco.h b/gcc/config/i386/xm-sco.h
deleted file mode 100755
index ad63449..0000000
--- a/gcc/config/i386/xm-sco.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Configuration for GCC for Intel i386 running SCO.  */
-
-/* Big buffers improve performance.  */
-
-#define IO_BUFFER_SIZE (0x8000 - 1024)
-
-#ifndef __GNUC__
-/* The SCO compiler gets it wrong, and treats enumerated bitfields
-   as signed quantities, making it impossible to use an 8-bit enum
-   for compiling GNU C++.  */
-#define ONLY_INT_FIELDS 1
-#define CODE_FIELD_BUG 1
-#endif
diff --git a/gcc/config/i386/xm-sco5.h b/gcc/config/i386/xm-sco5.h
deleted file mode 100755
index 6b22b1d..0000000
--- a/gcc/config/i386/xm-sco5.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Configuration for GCC for Intel i386 running SCO.  */
-
-/* Big buffers improve performance.  */
-
-#define IO_BUFFER_SIZE (0x8000 - 1024)
-
-
diff --git a/gcc/config/i386/xm-sun.h b/gcc/config/i386/xm-sun.h
deleted file mode 100755
index de7c201..0000000
--- a/gcc/config/i386/xm-sun.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Configuration for GNU C-compiler for Intel 80386 running SunOS 4.0.
-   Copyright (C) 1988, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define USG
-
-#include "i386/xm-i386.h"
diff --git a/gcc/config/i386/xm-sysv3.h b/gcc/config/i386/xm-sysv3.h
deleted file mode 100755
index 72078bb..0000000
--- a/gcc/config/i386/xm-sysv3.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/* Configuration for GCC for Intel i386 running System V Release 3.  */
-
-#include "i386/xm-i386.h"
-#include "xm-svr3.h"
diff --git a/gcc/config/i386/xm-sysv4.h b/gcc/config/i386/xm-sysv4.h
deleted file mode 100755
index 1365064..0000000
--- a/gcc/config/i386/xm-sysv4.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* Configuration for GCC for Intel i386 running System V Release 4.  */
-
-#ifdef __HIGHC__
-#include <alloca.h>		/* for MetaWare High-C on NCR System 3000 */
-#endif
diff --git a/gcc/config/i386/xm-vsta.h b/gcc/config/i386/xm-vsta.h
deleted file mode 100755
index 735d1d5..0000000
--- a/gcc/config/i386/xm-vsta.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* Use semicolons to separate elements of a path.  */
-#define PATH_SEPARATOR ';'
diff --git a/gcc/config/i386/xm-winnt.h b/gcc/config/i386/xm-winnt.h
deleted file mode 100755
index d36d2cd..0000000
--- a/gcc/config/i386/xm-winnt.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Configuration for GNU compiler
-   for an Intel i386 or later processor running Windows NT 3.x.
-   Copyright (C) 1994 Free Software Foundation, Inc.
-   Contributed by Douglas B. Rupp (drupp@cs.washington.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "winnt/xm-winnt.h"
-#include "i386/xm-i386.h"
diff --git a/gcc/config/i860/bsd-gas.h b/gcc/config/i860/bsd-gas.h
deleted file mode 100755
index f76fec7..0000000
--- a/gcc/config/i860/bsd-gas.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#undef ASCII_DATA_ASM_OP
-#define ASCII_DATA_ASM_OP ".ascii"
diff --git a/gcc/config/i860/bsd.h b/gcc/config/i860/bsd.h
deleted file mode 100755
index 17b0533..0000000
--- a/gcc/config/i860/bsd.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i860, BSD)")
-
-/* BSD UN*X systems use BSD STABS debugging info.  */
-
-#define DBX_DEBUGGING_INFO
-
-#define ASCII_DATA_ASM_OP ".byte"
-#define	ASM_OUTPUT_ASCII(f, p, size)	\
-do { register unsigned i;		\
-  int inside;				\
-  inside = FALSE;			\
-  for (i = 0; i < (size); i++) {	\
-    if (i % 64 == 0) {			\
-      if (i != 0) {			\
-	if (inside)			\
-	  putc('"', (f));		\
-	putc('\n', (f));		\
-	inside = FALSE;			\
-      }					\
-      fprintf((f), "\t%s ", ASCII_DATA_ASM_OP);	\
-    }					\
-    if ((p)[i] < 32 || (p)[i] == '\\' || (p)[i] == '"' || (p)[i] >= 127) {	\
-      if (inside) {			\
-	putc('"', (f));			\
-	inside = FALSE;			\
-      }					\
-      if (i % 64 != 0)			\
-	putc(',', (f));			\
-      fprintf((f), "%d", (p)[i]);	\
-    } else {				\
-      if (!inside) {			\
-	if (i % 64 != 0)		\
-	  putc(',', (f));		\
-	putc('"', (f));			\
-	inside = TRUE;			\
-      }					\
-      putc((p)[i], (f));		\
-    }					\
-  }					\
-  if (inside)				\
-    putc('"', (f));			\
-  putc('\n', (f));			\
-} while (0)
diff --git a/gcc/config/i860/fx2800.h b/gcc/config/i860/fx2800.h
deleted file mode 100755
index 26c7c25..0000000
--- a/gcc/config/i860/fx2800.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/* Target definitions for GNU compiler for Alliant FX/2800
-   running Concentrix 2.2
-   Copyright (C) 1991, 1996, 1998 Free Software Foundation, Inc.
-   Contributed by Howard Chu (hyc@hanauma.jpl.nasa.gov).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* The Alliant fx2800 running Concentrix 2.x is weird.  This is basically
-   a BSD 4.3 based operating system, but it uses svr4 ELF format object
-   files and it somehow puts BSD stabs records into the ELF files for
-   symbolic debug information.  The assembler is "mostly an SVR4 assembler
-   with some Alliant additions. We based it on the `Intel 80860 Assembly
-   Language Specification' from AT&T." */
-
-/* This file consists of three sections. The first section establishes
-   definitions unique to the Alliant FX/2800. The next section reconciles
-   differences between Alliant and i860v4.h, and the last overrides the
-   remaining differences with svr4.h */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i860 Alliant)");
-
-/* atexit is not present prior to Concentrix 2.2. Uncomment the following
-   if you're on 2.1 or older. */
- 
-/* #undef HAVE_ATEXIT */
-
-#define I860_STRICT_ABI_PROLOGUES
-
-/* There is no avoiding this; -L does not exist at all (in Concentrix 2.2).  */
-#define LINK_LIBGCC_SPECIAL 1
-
-/* Most of the Alliant-specific definitions here are to get stab info that
-   Alliant's dbx can understand. */
-
-#define DBX_DEBUGGING_INFO
-#define DEFAULT_GDB_EXTENSIONS 0
-#define DBX_NO_XREFS
-#define DBX_NO_EXTRA_TAGS
-
-/* Alliant dbx also needs to see the function stab before anything
-   else in the function. */
-
-#define DBX_FUNCTION_FIRST
-#define DBX_LBRAC_FIRST
-
-/* Alliant dbx also needs to see the end of a function somewhere. */
-
-#define DBX_OUTPUT_FUNCTION_END(file,decl)	\
-	fprintf (file, ".stab \"\",.,0x%x,0,0\n", N_EFUN)
-
-/* Alliant dbx has predefined types, so they must be emitted with the
-   proper type numbers. The defined types are:
-
-     Type #	C, Fortran, Pascal Types
-	--	------------------------
-	 1	char, integer*1
-	 2	short, 	integer*2
-	 3	int, long, integer*4, integer
-	 4	logical*1, byte
-	 5	logical*2
-	 6	logical*4, logical
-	 7	float, real*4, 	real
-	 8	double, real*8,	double
-	 9	single complex, complex*8, complex
-	10	double complex, doublecomplex
-	11	character
-	12	void
-	13	nil
-	14	boolean
-	15	unsigned char, ubyte
-	16	unsigned short, uword
-	17	unsigned, unsigned int, unsigned long, ulong
-	18	quad, logical*8
-	19	long long, integer*8
-	20	unsigned long long, uquad*8
-    21-100	reserved for future predefined types
-	100	long redefine same as 3
-	101	unsigned long same as 17
-	--	--------------------
-	102	First user program type
-
-   Since long and unsigned long are int references, they must be handled
-   as special cases. The Alliant compiler doesn't use types 18-20, so it
-   sets long & unsigned long in 18 & 19, not in 100 & 101 as shown above. */
-
-#define DBX_OUTPUT_STANDARD_TYPES(syms)	\
-{ char *dtyps[]={"", "char", "short int", "int", "logical*1",		\
-	"logical*2", "logical*4", "float", "double", "complex",		\
-	"doublecomplex", "character", "void", "nil", "boolean",		\
-	"unsigned char", "short unsigned int", "unsigned int",		\
-	"logical*8", "long long int", "long long unsigned int",""};	\
-									\
-  tree decl;								\
-  int i;								\
-									\
-  for (i=1;*dtyps[i];i++)						\
-    for (decl = syms; decl; decl = TREE_CHAIN(decl))			\
-	if ((TREE_CODE (decl) == TYPE_DECL) && DECL_NAME(decl) &&	\
-	    !strcmp(IDENTIFIER_POINTER(DECL_NAME(decl)), dtyps[i])) {	\
-		TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = i;		\
-		typevec[i] = TYPE_DEFINED;				\
-		dbxout_symbol (decl, 0);				\
-		break;							\
-	}								\
-									\
-  for (decl = syms; decl; decl = TREE_CHAIN(decl))			\
-    if ((TREE_CODE (decl) == TYPE_DECL) && DECL_NAME(decl) &&		\
-	!strcmp(IDENTIFIER_POINTER(DECL_NAME(decl)),"long int")) {	\
-      TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = i;			\
-      typevec[i] = TYPE_DEFINED;					\
-      fprintf(asmfile,".stab \"long int:t%d=3\",0,0x%x,0,0\n",		\
-		i++,N_LSYM);						\
-      TREE_ASM_WRITTEN (decl) = 1;					\
-      break;								\
-    }									\
-									\
-  for (decl = syms; decl; decl = TREE_CHAIN(decl))			\
-    if ((TREE_CODE (decl) == TYPE_DECL) && DECL_NAME(decl) && !strcmp(	\
-	IDENTIFIER_POINTER(DECL_NAME(decl)),"long unsigned int")) {	\
-      TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = i;			\
-      typevec[i] = TYPE_DEFINED;					\
-      fprintf(asmfile,".stab \"long unsigned int:t%d=17\",0,0x%x,0,0\n",\
-		i++,N_LSYM);						\
-      TREE_ASM_WRITTEN (decl) = 1;					\
-      break;								\
-    }									\
-  next_type_number = i; };
-
-/* Alliant dbx doesn't understand split names... */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* The syntax for stabs records is also different; there is only a single
-   ".stab" directive instead of the 3 directives in BSD, and the order of
-   arguments is slightly changed. */
-
-#define ASM_STABS_OP	".stab"
-#define ASM_STABN_OP	".stab"
-#define ASM_STABD_OP	".stab"
-
-#define DBX_MEMPARM_STABS_LETTER 'k'
-#define DBX_REGPARM_STABS_LETTER 'r'
-
-#define ASM_OUTPUT_SOURCE_LINE(file,num)		\
-	fprintf (file, "\t.stab \"\",.,0x%x,0,%d\n",	\
-		N_SLINE,num)
-
-#if 0	/* Alliant dbx only reads first N_SO, so it
-	   ignores the filename if dir is present. */
-#define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(file,name)		\
-	fprintf (file, ".stab \"%s/\",.Ltext0,0x%x,0,0\n",	\
-		name, N_SO)
-#else
-#define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(file,name)
-#endif
-
-#define DBX_OUTPUT_MAIN_SOURCE_FILENAME(file,name)		\
-	fprintf (file, ".stab ");				\
-	output_quoted_string (file, name);			\
-	fprintf (file, ",.Ltext0,0x%x,0,0\n", N_SO);		\
-	text_section ();					\
-	ASM_OUTPUT_INTERNAL_LABEL (file, "Ltext", 0)
-
-#define DBX_OUTPUT_SOURCE_FILENAME(file,name)			\
-  do {	fprintf (file, ".stab ");				\
-	output_quoted_string (file, name);			\
-	fprintf (file, ",.Ltext0,0x%x,0,0\n", N_SOL);		\
-  } while (0)
-
-#define DBX_OUTPUT_CONSTANT_SYMBOL(file,name,ival)		\
-	fprintf (file, ".stab \"%s:c=i%d\",0,0x%x,0,0\n",	\
-		name, ival, N_LSYM)
-
-#define DBX_FINISH_SYMBOL(decl)	\
-	int line = 0;						\
-	fprintf (asmfile, "\",");				\
-	if (current_sym_addr)					\
-	  output_addr_const (asmfile, current_sym_addr);	\
-	else							\
-	  fprintf (asmfile, "%d", current_sym_value);		\
-	if (decl != 0 && TREE_CODE(decl) == FUNCTION_DECL)	\
-	  line=DECL_SOURCE_LINE (decl);				\
-	fprintf (asmfile, ",0x%x,%d,%d\n", current_sym_code,	\
-	  line!=0?64:0,line)
-
-#define DBX_OUTPUT_CATCH(file,decl,name)		\
-  fprintf (file, ".stab \"%s:C1\",",			\
-	   IDENTIFIER_POINTER (DECL_NAME (decl)));	\
-  assemble_name (file, name);				\
-  fprintf (file, ",0x%x,0,0\n", N_CATCH)
-
-#define DBX_OUTPUT_LBRAC(file,name)	\
-  if (depth > 1) {			\
-    fprintf (file, ".stab \"\",");	\
-    assemble_name (file, name);		\
-    fprintf (file, ",0x%x,0,%d\n", N_LBRAC, depth); }
-
-#define DBX_OUTPUT_RBRAC(file,name)	\
-  if (depth > 1) {			\
-    fprintf (file, ".stab \"\",");	\
-    assemble_name (file, name);		\
-    fprintf (file, ",0x%x,0,%d\n", N_RBRAC, depth); }
-
-#define DBX_OUTPUT_ENUM(file,type)				\
-  fprintf (file, "e3");						\
-  CHARS(2);							\
-  for (tem = TYPE_VALUES (type); tem; tem = TREE_CHAIN (tem))	\
-    {								\
-      fprintf (asmfile, "%s:%d,",				\
-	       IDENTIFIER_POINTER (TREE_PURPOSE (tem)),		\
-	       TREE_INT_CST_LOW (TREE_VALUE (tem)));		\
-      CHARS (11 + IDENTIFIER_LENGTH (TREE_PURPOSE (tem)));	\
-      if (TREE_CHAIN (tem) != 0)				\
-	CONTIN;							\
-    }								\
-  putc (';', asmfile);						\
-  CHARS (1);
-
-/* Undefine some things defined in i860.h because the native C compiler
-   on the FX/2800 emits code to do these operations inline.  For GCC,
-   we will use the default implementation of these things... i.e.
-   generating calls to libgcc1 routines.  */
-
-#undef DIVSI3_LIBCALL
-#undef UDIVSI3_LIBCALL
-#undef REMSI3_LIBCALL
-#undef UREMSI3_LIBCALL
-
-/* The Alliant compiler's mod function gives the wrong result after a
-   shift operation. This bug typically hits in hash functions. */
-
-#define perform_umodsi3(a, b)	a %= b; if (a == b) a=0; return a
-#define perform_modsi3(a, b)	a %= b; if (a == b) a=0; return a
-
-/* Global pointer needs to be 8 byte aligned? Link error if not... */
-
-#define DATA_ALIGNMENT(dummy,align)	\
-	((TREE_PUBLIC (decl) &&	\
-	 (POINTER_TYPE_P (TREE_TYPE (decl)))) ? 64: align)
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)	\
-	fprintf (FILE, "\tcall __mcount_\n\tnop\n")
-
-/* Overrides for i860v4.h begin here */
-
-/* Provide a set of pre-definitions and pre-assertions appropriate for
-   the i860 running Concentrix 2.x.  */
-
-#undef CPP_PREDEFINES 
-#define CPP_PREDEFINES "-Di860 -Dunix -DBSD4_3 -Dalliant -Asystem(unix) -Asystem(bsd) -Acpu(i860) -Amachine(i860)"
-
-#undef I860_REG_PREFIX
-#undef ASM_COMMENT_START
-#define ASM_COMMENT_START "//"
-
-/* Use definitions of ASM_OUTPUT_{DOUBLE,FLOAT} as given in i860.h */
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
-  fprintf(FILE, "\t.double %.20e\n", (VALUE))
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
-  fprintf(FILE, "\t.float %.12e\n", (VALUE))
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)
-#undef ASM_OUTPUT_FUNCTION_PREFIX
-#define ASM_OUTPUT_FUNCTION_PREFIX(FILE,NAME) \
-  fputs("\tnop\n", (FILE));			\
-  current_function_original_name = (NAME)
-#undef ASM_OUTPUT_PROLOGUE_SUFFIX
-
-/* Overrides for svr4.h begin here */
-
-#undef SVR4
-
-#undef SWITCH_TAKES_ARG
-#undef WORD_SWITCH_TAKES_ARG
-
-#undef ASM_SPEC
-#undef ASM_FINAL_SPEC
-#undef MD_STARTFILE_PREFIX
-#undef MD_EXEC_PREFIX
-
-/* Generate an error message if -p option is selected. Concentrix 2.x
-   does not support prof format profiling, only gprof is supported. */
-
-#define CPP_SPEC	"%{p:%e-p option not supported: use -pg instead}"
-
-/* Provide an appropriate LIB_SPEC. The crtend.o file provides part of the
-   support for getting C++ file-scope static objects constructed before
-   entering `main'. */
-
-#undef LIB_SPEC
-#define LIB_SPEC \
-	"%{g*:-lg} %{!pg:-lc}%{pg:-lc_p} crtend.o%s"
-
-/* Tell linker to strip local symbols, since assembler may not. */
-
-#undef LINK_SPEC
-#define LINK_SPEC	"-X"
-
-/* Get the correct startup file for regular or profiled code. Also
-   use the crtbegin.o file for C++ ... */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-	"%{!pg:crt0.o%s}%{pg:gcrt0.o%s} crtbegin.o%s"
-
-#undef SCCS_DIRECTIVE
-#undef NO_DOLLAR_IN_LABEL
-#undef TARGET_MEM_FUNCTIONS
-
-#undef DWARF_DEBUGGING_INFO
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX "_"
-
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-
-/* ??? Is this used anywhere?  */
-#undef BSS_ASM_OP
-#define BSS_ASM_OP	"\t.lcomm"
-
-#undef ASM_FILE_END
-#define ASM_FILE_END(FILE)					\
-do {				 				\
-     if (current_function_original_name != NULL) {		\
-       tdesc_section();						\
-       fprintf ((FILE), "%s __ETEXT\n", ASM_LONG);		\
-       fprintf ((FILE), "%s 0\n", ASM_LONG);			\
-       text_section();						\
-       fputs("__ETEXT:\n", (FILE));				\
-     }								\
-     fprintf ((FILE), "\t.ident\t\"GCC: (GNU) %s\"\n",		\
-	      version_string);					\
-   } while (0)
diff --git a/gcc/config/i860/i860.c b/gcc/config/i860/i860.c
deleted file mode 100755
index 7eed361..0000000
--- a/gcc/config/i860/i860.c
+++ /dev/null
@@ -1,2097 +0,0 @@
-/* Subroutines for insn-output.c for Intel 860
-   Copyright (C) 1989, 1991, 1997, 1998 Free Software Foundation, Inc.
-   Derived from sparc.c.
-
-   Written by Richard Stallman (rms@ai.mit.edu).
-
-   Hacked substantially by Ron Guilmette (rfg@netcom.com) to cater
-   to the whims of the System V Release 4 assembler.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "config.h"
-#include <stdio.h>
-#include "flags.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "recog.h"
-#include "insn-attr.h"
-
-static rtx find_addr_reg ();
-
-#ifndef I860_REG_PREFIX
-#define I860_REG_PREFIX ""
-#endif
-
-char *i860_reg_prefix = I860_REG_PREFIX;
-
-/* Save information from a "cmpxx" operation until the branch is emitted.  */
-
-rtx i860_compare_op0, i860_compare_op1;
-
-/* Return non-zero if this pattern, can be evaluated safely, even if it
-   was not asked for.  */
-int
-safe_insn_src_p (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  /* Just experimenting.  */
-
-  /* No floating point src is safe if it contains an arithmetic
-     operation, since that operation may trap.  */
-  switch (GET_CODE (op))
-    {
-    case CONST_INT:
-    case LABEL_REF:
-    case SYMBOL_REF:
-    case CONST:
-      return 1;
-
-    case REG:
-      return 1;
-
-    case MEM:
-      return CONSTANT_ADDRESS_P (XEXP (op, 0));
-
-      /* We never need to negate or complement constants.  */
-    case NEG:
-      return (mode != SFmode && mode != DFmode);
-    case NOT:
-    case ZERO_EXTEND:
-      return 1;
-
-    case EQ:
-    case NE:
-    case LT:
-    case GT:
-    case LE:
-    case GE:
-    case LTU:
-    case GTU:
-    case LEU:
-    case GEU:
-    case MINUS:
-    case PLUS:
-      return (mode != SFmode && mode != DFmode);
-    case AND:
-    case IOR:
-    case XOR:
-    case ASHIFT:
-    case ASHIFTRT:
-    case LSHIFTRT:
-      if ((GET_CODE (XEXP (op, 0)) == CONST_INT && ! SMALL_INT (XEXP (op, 0)))
-	  || (GET_CODE (XEXP (op, 1)) == CONST_INT && ! SMALL_INT (XEXP (op, 1))))
-	return 0;
-      return 1;
-
-    default:
-      return 0;
-    }
-}
-
-/* Return 1 if REG is clobbered in IN.
-   Return 2 if REG is used in IN. 
-   Return 3 if REG is both used and clobbered in IN.
-   Return 0 if neither.  */
-
-static int
-reg_clobbered_p (reg, in)
-     rtx reg;
-     rtx in;
-{
-  register enum rtx_code code;
-
-  if (in == 0)
-    return 0;
-
-  code = GET_CODE (in);
-
-  if (code == SET || code == CLOBBER)
-    {
-      rtx dest = SET_DEST (in);
-      int set = 0;
-      int used = 0;
-
-      while (GET_CODE (dest) == STRICT_LOW_PART
-	     || GET_CODE (dest) == SUBREG
-	     || GET_CODE (dest) == SIGN_EXTRACT
-	     || GET_CODE (dest) == ZERO_EXTRACT)
-	dest = XEXP (dest, 0);
-
-      if (dest == reg)
-	set = 1;
-      else if (GET_CODE (dest) == REG
-	       && refers_to_regno_p (REGNO (reg),
-				     REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
-				     SET_DEST (in), 0))
-	{
-	  set = 1;
-	  /* Anything that sets just part of the register
-	     is considered using as well as setting it.
-	     But note that a straight SUBREG of a single-word value
-	     clobbers the entire value.   */
-	  if (dest != SET_DEST (in)
-	      && ! (GET_CODE (SET_DEST (in)) == SUBREG
-		    || UNITS_PER_WORD >= GET_MODE_SIZE (GET_MODE (dest))))
-	    used = 1;
-	}
-
-      if (code == SET)
-	{
-	  if (set)
-	    used = refers_to_regno_p (REGNO (reg),
-				      REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
-				      SET_SRC (in), 0);
-	  else
-	    used = refers_to_regno_p (REGNO (reg),
-				      REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
-				      in, 0);
-	}
-
-      return set + used * 2;
-    }
-
-  if (refers_to_regno_p (REGNO (reg),
-			 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
-			 in, 0))
-    return 2;
-  return 0;
-}
-
-/* Return non-zero if OP can be written to without screwing up
-   GCC's model of what's going on.  It is assumed that this operand
-   appears in the dest position of a SET insn in a conditional
-   branch's delay slot.  AFTER is the label to start looking from.  */
-int
-operand_clobbered_before_used_after (op, after)
-     rtx op;
-     rtx after;
-{
-  /* Just experimenting.  */
-  if (GET_CODE (op) == CC0)
-    return 1;
-  if (GET_CODE (op) == REG)
-    {
-      rtx insn;
-
-      if (op == stack_pointer_rtx)
-	return 0;
-
-      /* Scan forward from the label, to see if the value of OP
-	 is clobbered before the first use.  */
-
-      for (insn = NEXT_INSN (after); insn; insn = NEXT_INSN (insn))
-	{
-	  if (GET_CODE (insn) == NOTE)
-	    continue;
-	  if (GET_CODE (insn) == INSN
-	      || GET_CODE (insn) == JUMP_INSN
-	      || GET_CODE (insn) == CALL_INSN)
-	    {
-	      switch (reg_clobbered_p (op, PATTERN (insn)))
-		{
-		default:
-		  return 0;
-		case 1:
-		  return 1;
-		case 0:
-		  break;
-		}
-	    }
-	  /* If we reach another label without clobbering OP,
-	     then we cannot safely write it here.  */
-	  else if (GET_CODE (insn) == CODE_LABEL)
-	    return 0;
-	  if (GET_CODE (insn) == JUMP_INSN)
-	    {
-	      if (condjump_p (insn))
-		return 0;
-	      /* This is a jump insn which has already
-		 been mangled.  We can't tell what it does.  */
-	      if (GET_CODE (PATTERN (insn)) == PARALLEL)
-		return 0;
-	      if (! JUMP_LABEL (insn))
-		return 0;
-	      /* Keep following jumps.  */
-	      insn = JUMP_LABEL (insn);
-	    }
-	}
-      return 1;
-    }
-
-  /* In both of these cases, the first insn executed
-     for this op will be a orh whatever%h,%?r0,%?r31,
-     which is tolerable.  */
-  if (GET_CODE (op) == MEM)
-    return (CONSTANT_ADDRESS_P (XEXP (op, 0)));
-
-  return 0;
-}
-
-/* Return non-zero if this pattern, as a source to a "SET",
-   is known to yield an instruction of unit size.  */
-int
-single_insn_src_p (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case CONST_INT:
-      /* This is not always a single insn src, technically,
-	 but output_delayed_branch knows how to deal with it.  */
-      return 1;
-
-    case SYMBOL_REF:
-    case CONST:
-      /* This is not a single insn src, technically,
-	 but output_delayed_branch knows how to deal with it.  */
-      return 1;
-
-    case REG:
-      return 1;
-
-    case MEM:
-      return 1;
-
-      /* We never need to negate or complement constants.  */
-    case NEG:
-      return (mode != DFmode);
-    case NOT:
-    case ZERO_EXTEND:
-      return 1;
-
-    case PLUS:
-    case MINUS:
-      /* Detect cases that require multiple instructions.  */
-      if (CONSTANT_P (XEXP (op, 1))
-	  && !(GET_CODE (XEXP (op, 1)) == CONST_INT
-	       && SMALL_INT (XEXP (op, 1))))
-	return 0;
-    case EQ:
-    case NE:
-    case LT:
-    case GT:
-    case LE:
-    case GE:
-    case LTU:
-    case GTU:
-    case LEU:
-    case GEU:
-      /* Not doing floating point, since they probably
-	 take longer than the branch slot they might fill.  */
-      return (mode != SFmode && mode != DFmode);
-
-    case AND:
-      if (GET_CODE (XEXP (op, 1)) == NOT)
-	{
-	  rtx arg = XEXP (XEXP (op, 1), 0);
-	  if (CONSTANT_P (arg)
-	      && !(GET_CODE (arg) == CONST_INT
-		   && (SMALL_INT (arg)
-		       || (INTVAL (arg) & 0xffff) == 0)))
-	    return 0;
-	}
-    case IOR:
-    case XOR:
-      /* Both small and round numbers take one instruction;
-	 others take two.  */
-      if (CONSTANT_P (XEXP (op, 1))
-	  && !(GET_CODE (XEXP (op, 1)) == CONST_INT
-	       && (SMALL_INT (XEXP (op, 1))
-		   || (INTVAL (XEXP (op, 1)) & 0xffff) == 0)))
-	return 0;
-
-    case ASHIFT:
-    case ASHIFTRT:
-    case LSHIFTRT:
-      return 1;
-
-    case SUBREG:
-      if (SUBREG_WORD (op) != 0)
-	return 0;
-      return single_insn_src_p (SUBREG_REG (op), mode);
-
-      /* Not doing floating point, since they probably
-	 take longer than the branch slot they might fill.  */
-    case FLOAT_EXTEND:
-    case FLOAT_TRUNCATE:
-    case FLOAT:
-    case FIX:
-    case UNSIGNED_FLOAT:
-    case UNSIGNED_FIX:
-      return 0;
-
-    default:
-      return 0;
-    }
-}
-
-/* Return non-zero only if OP is a register of mode MODE,
-   or const0_rtx.  */
-int
-reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (op == const0_rtx || register_operand (op, mode)
-	  || op == CONST0_RTX (mode));
-}
-
-/* Return truth value of whether OP can be used as an operands in a three
-   address add/subtract insn (such as add %o1,7,%l2) of mode MODE.  */
-
-int
-arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && SMALL_INT (op)));
-}
-
-/* Return 1 if OP is a valid first operand for a logical insn of mode MODE.  */
-
-int
-logic_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && LOGIC_INT (op)));
-}
-
-/* Return 1 if OP is a valid first operand for a shift insn of mode MODE.  */
-
-int
-shift_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-          || (GET_CODE (op) == CONST_INT));
-}
-
-/* Return 1 if OP is a valid first operand for either a logical insn
-   or an add insn of mode MODE.  */
-
-int
-compare_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && SMALL_INT (op) && LOGIC_INT (op)));
-}
-
-/* Return truth value of whether OP can be used as the 5-bit immediate
-   operand of a bte or btne insn.  */
-
-int
-bte_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT
-	      && (unsigned) INTVAL (op) < 0x20));
-}
-
-/* Return 1 if OP is an indexed memory reference of mode MODE.  */
-
-int
-indexed_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == MEM && GET_MODE (op) == mode
-	  && GET_CODE (XEXP (op, 0)) == PLUS
-	  && GET_MODE (XEXP (op, 0)) == SImode
-	  && register_operand (XEXP (XEXP (op, 0), 0), SImode)
-	  && register_operand (XEXP (XEXP (op, 0), 1), SImode));
-}
-
-/* Return 1 if OP is a suitable source operand for a load insn
-   with mode MODE.  */
-
-int
-load_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (memory_operand (op, mode) || indexed_operand (op, mode));
-}
-
-/* Return truth value of whether OP is a integer which fits the
-   range constraining immediate operands in add/subtract insns.  */
-
-int
-small_int (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
-}
-
-/* Return truth value of whether OP is a integer which fits the
-   range constraining immediate operands in logic insns.  */
-
-int
-logic_int (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == CONST_INT && LOGIC_INT (op));
-}
-
-/* Test for a valid operand for a call instruction.
-   Don't allow the arg pointer register or virtual regs
-   since they may change into reg + const, which the patterns
-   can't handle yet.  */
-
-int
-call_insn_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == MEM
-      && (CONSTANT_ADDRESS_P (XEXP (op, 0))
-	  || (GET_CODE (XEXP (op, 0)) == REG
-	      && XEXP (op, 0) != arg_pointer_rtx
-	      && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
-		   && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
-    return 1;
-  return 0;
-}
-
-/* Return the best assembler insn template
-   for moving operands[1] into operands[0] as a fullword.  */
-
-static char *
-singlemove_string (operands)
-     rtx *operands;
-{
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (GET_CODE (operands[1]) != MEM)
-	if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-	  {
-	    if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-		   && (cc_prev_status.flags & CC_HI_R31_ADJ)
-		   && cc_prev_status.mdep == XEXP (operands[0], 0)))
-	      {
-		CC_STATUS_INIT;
-	        output_asm_insn ("orh %h0,%?r0,%?r31", operands);
-	      }
-	    cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-	    cc_status.mdep = XEXP (operands[0], 0);
-	    return "st.l %r1,%L0(%?r31)";
-	  }
-	else
-	  return "st.l %r1,%0";
-      else
-	abort ();
-#if 0
-	{
-	  rtx xoperands[2];
-
-	  cc_status.flags &= ~CC_F0_IS_0;
-	  xoperands[0] = gen_rtx (REG, SFmode, 32);
-	  xoperands[1] = operands[1];
-	  output_asm_insn (singlemove_string (xoperands), xoperands);
-	  xoperands[1] = xoperands[0];
-	  xoperands[0] = operands[0];
-	  output_asm_insn (singlemove_string (xoperands), xoperands);
-	  return "";
-	}
-#endif
-    }
-  if (GET_CODE (operands[1]) == MEM)
-    {
-      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-	{
-	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-		 && (cc_prev_status.flags & CC_HI_R31_ADJ)
-		 && cc_prev_status.mdep == XEXP (operands[1], 0)))
-	    {
-	      CC_STATUS_INIT;
-	      output_asm_insn ("orh %h1,%?r0,%?r31", operands);
-	    }
-	  cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-	  cc_status.mdep = XEXP (operands[1], 0);
-	  return "ld.l %L1(%?r31),%0";
-	}
-      return "ld.l %m1,%0";
-    }
- if (GET_CODE (operands[1]) == CONST_INT)
-   {
-     if (operands[1] == const0_rtx)
-      return "mov %?r0,%0";
-     if((INTVAL (operands[1]) & 0xffff0000) == 0)
-      return "or %L1,%?r0,%0";
-     if((INTVAL (operands[1]) & 0xffff8000) == 0xffff8000)
-      return "adds %1,%?r0,%0";
-     if((INTVAL (operands[1]) & 0x0000ffff) == 0)
-      return "orh %H1,%?r0,%0";
-   }
-  return "mov %1,%0";
-}
-
-/* Output assembler code to perform a doubleword move insn
-   with operands OPERANDS.  */
-
-char *
-output_move_double (operands)
-     rtx *operands;
-{
-  enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
-  rtx latehalf[2];
-  rtx addreg0 = 0, addreg1 = 0;
-  int highest_first = 0;
-  int no_addreg1_decrement = 0;
-
-  /* First classify both operands.  */
-
-  if (REG_P (operands[0]))
-    optype0 = REGOP;
-  else if (offsettable_memref_p (operands[0]))
-    optype0 = OFFSOP;
-  else if (GET_CODE (operands[0]) == MEM)
-    optype0 = MEMOP;
-  else
-    optype0 = RNDOP;
-
-  if (REG_P (operands[1]))
-    optype1 = REGOP;
-  else if (CONSTANT_P (operands[1]))
-    optype1 = CNSTOP;
-  else if (offsettable_memref_p (operands[1]))
-    optype1 = OFFSOP;
-  else if (GET_CODE (operands[1]) == MEM)
-    optype1 = MEMOP;
-  else
-    optype1 = RNDOP;
-
-  /* Check for the cases that the operand constraints are not
-     supposed to allow to happen.  Abort if we get one,
-     because generating code for these cases is painful.  */
-
-  if (optype0 == RNDOP || optype1 == RNDOP)
-    abort ();
-
-  /* If an operand is an unoffsettable memory ref, find a register
-     we can increment temporarily to make it refer to the second word.  */
-
-  if (optype0 == MEMOP)
-    addreg0 = find_addr_reg (XEXP (operands[0], 0));
-
-  if (optype1 == MEMOP)
-    addreg1 = find_addr_reg (XEXP (operands[1], 0));
-
-/* ??? Perhaps in some cases move double words
-   if there is a spare pair of floating regs.  */
-
-  /* Ok, we can do one word at a time.
-     Normally we do the low-numbered word first,
-     but if either operand is autodecrementing then we
-     do the high-numbered word first.
-
-     In either case, set up in LATEHALF the operands to use
-     for the high-numbered word and in some cases alter the
-     operands in OPERANDS to be suitable for the low-numbered word.  */
-
-  if (optype0 == REGOP)
-    latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  else if (optype0 == OFFSOP)
-    latehalf[0] = adj_offsettable_operand (operands[0], 4);
-  else
-    latehalf[0] = operands[0];
-
-  if (optype1 == REGOP)
-    latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-  else if (optype1 == OFFSOP)
-    latehalf[1] = adj_offsettable_operand (operands[1], 4);
-  else if (optype1 == CNSTOP)
-    {
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	split_double (operands[1], &operands[1], &latehalf[1]);
-      else if (CONSTANT_P (operands[1]))
-	latehalf[1] = const0_rtx;
-    }
-  else
-    latehalf[1] = operands[1];
-
-  /* If the first move would clobber the source of the second one,
-     do them in the other order.
-
-     RMS says "This happens only for registers;
-     such overlap can't happen in memory unless the user explicitly
-     sets it up, and that is an undefined circumstance."
-
-     but it happens on the sparc when loading parameter registers,
-     so I am going to define that circumstance, and make it work
-     as expected.  */
-
-  if (optype0 == REGOP && optype1 == REGOP
-      && REGNO (operands[0]) == REGNO (latehalf[1]))
-    {
-      CC_STATUS_PARTIAL_INIT;
-      /* Make any unoffsettable addresses point at high-numbered word.  */
-      if (addreg0)
-	output_asm_insn ("adds 0x4,%0,%0", &addreg0);
-      if (addreg1)
-	output_asm_insn ("adds 0x4,%0,%0", &addreg1);
-
-      /* Do that word.  */
-      output_asm_insn (singlemove_string (latehalf), latehalf);
-
-      /* Undo the adds we just did.  */
-      if (addreg0)
-	output_asm_insn ("adds -0x4,%0,%0", &addreg0);
-      if (addreg1)
-	output_asm_insn ("adds -0x4,%0,%0", &addreg1);
-
-      /* Do low-numbered word.  */
-      return singlemove_string (operands);
-    }
-  else if (optype0 == REGOP && optype1 != REGOP
-	   && reg_overlap_mentioned_p (operands[0], operands[1]))
-    {
-      /* If both halves of dest are used in the src memory address,
-	 add the two regs and put them in the low reg (operands[0]).
-	 Then it works to load latehalf first.  */
-      if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
-	  && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
-	{
-	  rtx xops[2];
-	  xops[0] = latehalf[0];
-	  xops[1] = operands[0];
-	  output_asm_insn ("adds %1,%0,%1", xops);
-	  operands[1] = gen_rtx (MEM, DImode, operands[0]);
-	  latehalf[1] = adj_offsettable_operand (operands[1], 4);
-	  addreg1 = 0;
-	  highest_first = 1;
-	}
-      /* Only one register in the dest is used in the src memory address,
-	 and this is the first register of the dest, so we want to do
-	 the late half first here also.  */
-      else if (! reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
-	highest_first = 1;
-      /* Only one register in the dest is used in the src memory address,
-	 and this is the second register of the dest, so we want to do
-	 the late half last.  If addreg1 is set, and addreg1 is the same
-	 register as latehalf, then we must suppress the trailing decrement,
-	 because it would clobber the value just loaded.  */
-      else if (addreg1 && reg_mentioned_p (addreg1, latehalf[0]))
-	no_addreg1_decrement = 1;
-    }
-
-  /* Normal case: do the two words, low-numbered first.
-     Overlap case (highest_first set): do high-numbered word first.  */
-
-  if (! highest_first)
-    output_asm_insn (singlemove_string (operands), operands);
-
-  CC_STATUS_PARTIAL_INIT;
-  /* Make any unoffsettable addresses point at high-numbered word.  */
-  if (addreg0)
-    output_asm_insn ("adds 0x4,%0,%0", &addreg0);
-  if (addreg1)
-    output_asm_insn ("adds 0x4,%0,%0", &addreg1);
-
-  /* Do that word.  */
-  output_asm_insn (singlemove_string (latehalf), latehalf);
-
-  /* Undo the adds we just did.  */
-  if (addreg0)
-    output_asm_insn ("adds -0x4,%0,%0", &addreg0);
-  if (addreg1 && !no_addreg1_decrement)
-    output_asm_insn ("adds -0x4,%0,%0", &addreg1);
-
-  if (highest_first)
-    output_asm_insn (singlemove_string (operands), operands);
-
-  return "";
-}
-
-char *
-output_fp_move_double (operands)
-     rtx *operands;
-{
-  /* If the source operand is any sort of zero, use f0 instead.  */
-
-  if (operands[1] == CONST0_RTX (GET_MODE (operands[1])))
-    operands[1] = gen_rtx (REG, DFmode, F0_REGNUM);
-
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return "fmov.dd %1,%0";
-      if (GET_CODE (operands[1]) == REG)
-	{
-	  output_asm_insn ("ixfr %1,%0", operands);
-	  operands[0] = gen_rtx (REG, VOIDmode, REGNO (operands[0]) + 1);
-	  operands[1] = gen_rtx (REG, VOIDmode, REGNO (operands[1]) + 1);
-	  return "ixfr %1,%0";
-	}
-      if (operands[1] == CONST0_RTX (DFmode))
-	return "fmov.dd f0,%0";
-      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-	{
-	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-		 && (cc_prev_status.flags & CC_HI_R31_ADJ)
-		 && cc_prev_status.mdep == XEXP (operands[1], 0)))
-	    {
-	      CC_STATUS_INIT;
-	      output_asm_insn ("orh %h1,%?r0,%?r31", operands);
-	    }
-	  cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-	  cc_status.mdep = XEXP (operands[1], 0);
-	  return "fld.d %L1(%?r31),%0";
-	}
-      return "fld.d %1,%0";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      if (GET_CODE (operands[0]) == REG)
-	{
-	  output_asm_insn ("fxfr %1,%0", operands);
-	  operands[0] = gen_rtx (REG, VOIDmode, REGNO (operands[0]) + 1);
-	  operands[1] = gen_rtx (REG, VOIDmode, REGNO (operands[1]) + 1);
-	  return "fxfr %1,%0";
-	}
-      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-	{
-	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-		 && (cc_prev_status.flags & CC_HI_R31_ADJ)
-		 && cc_prev_status.mdep == XEXP (operands[0], 0)))
-	    {
-	      CC_STATUS_INIT;
-	      output_asm_insn ("orh %h0,%?r0,%?r31", operands);
-	    }
-	  cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-	  cc_status.mdep = XEXP (operands[0], 0);
-	  return "fst.d %1,%L0(%?r31)";
-	}
-      return "fst.d %1,%0";
-    }
-  else
-    abort ();
-  /* NOTREACHED */
-  return NULL;
-}
-
-/* Return a REG that occurs in ADDR with coefficient 1.
-   ADDR can be effectively incremented by incrementing REG.  */
-
-static rtx
-find_addr_reg (addr)
-     rtx addr;
-{
-  while (GET_CODE (addr) == PLUS)
-    {
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-	addr = XEXP (addr, 0);
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	addr = XEXP (addr, 1);
-      else if (CONSTANT_P (XEXP (addr, 0)))
-	addr = XEXP (addr, 1);
-      else if (CONSTANT_P (XEXP (addr, 1)))
-	addr = XEXP (addr, 0);
-      else
-	abort ();
-    }
-  if (GET_CODE (addr) == REG)
-    return addr;
-  abort ();
-  /* NOTREACHED */
-  return NULL;
-}
-
-/* Return a template for a load instruction with mode MODE and
-   arguments from the string ARGS.
-
-   This string is in static storage.   */
-
-static char *
-load_opcode (mode, args, reg)
-     enum machine_mode mode;
-     char *args;
-     rtx reg;
-{
-  static char buf[30];
-  char *opcode;
-
-  switch (mode)
-    {
-    case QImode:
-      opcode = "ld.b";
-      break;
-
-    case HImode:
-      opcode = "ld.s";
-      break;
-
-    case SImode:
-    case SFmode:
-      if (FP_REG_P (reg))
-	opcode = "fld.l";
-      else
-	opcode = "ld.l";
-      break;
-
-    case DImode:
-      if (!FP_REG_P (reg))
-	abort ();
-    case DFmode:
-      opcode = "fld.d";
-      break;
-
-    default:
-      abort ();
-    }
-
-  sprintf (buf, "%s %s", opcode, args);
-  return buf;
-}
-
-/* Return a template for a store instruction with mode MODE and
-   arguments from the string ARGS.
-
-   This string is in static storage.   */
-
-static char *
-store_opcode (mode, args, reg)
-     enum machine_mode mode;
-     char *args;
-     rtx reg;
-{
-  static char buf[30];
-  char *opcode;
-
-  switch (mode)
-    {
-    case QImode:
-      opcode = "st.b";
-      break;
-
-    case HImode:
-      opcode = "st.s";
-      break;
-
-    case SImode:
-    case SFmode:
-      if (FP_REG_P (reg))
-	opcode = "fst.l";
-      else
-	opcode = "st.l";
-      break;
-
-    case DImode:
-      if (!FP_REG_P (reg))
-	abort ();
-    case DFmode:
-      opcode = "fst.d";
-      break;
-
-    default:
-      abort ();
-    }
-
-  sprintf (buf, "%s %s", opcode, args);
-  return buf;
-}
-
-/* Output a store-in-memory whose operands are OPERANDS[0,1].
-   OPERANDS[0] is a MEM, and OPERANDS[1] is a reg or zero.
-
-   This function returns a template for an insn.
-   This is in static storage.
-
-   It may also output some insns directly.
-   It may alter the values of operands[0] and operands[1].  */
-
-char *
-output_store (operands)
-     rtx *operands;
-{
-  enum machine_mode mode = GET_MODE (operands[0]);
-  rtx address = XEXP (operands[0], 0);
-  char *string;
-
-  cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-  cc_status.mdep = address;
-
-  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-	 && (cc_prev_status.flags & CC_HI_R31_ADJ)
-	 && address == cc_prev_status.mdep))
-    {
-      CC_STATUS_INIT;
-      output_asm_insn ("orh %h0,%?r0,%?r31", operands);
-      cc_prev_status.mdep = address;
-    }
-
-  /* Store zero in two parts when appropriate.  */
-  if (mode == DFmode && operands[1] == CONST0_RTX (DFmode))
-    return store_opcode (DFmode, "%r1,%L0(%?r31)", operands[1]);
-
-  /* Code below isn't smart enough to move a doubleword in two parts,
-     so use output_move_double to do that in the cases that require it.  */
-  if ((mode == DImode || mode == DFmode)
-      && ! FP_REG_P (operands[1]))
-    return output_move_double (operands);
-
-  return store_opcode (mode, "%r1,%L0(%?r31)", operands[1]);
-}
-
-/* Output a load-from-memory whose operands are OPERANDS[0,1].
-   OPERANDS[0] is a reg, and OPERANDS[1] is a mem.
-
-   This function returns a template for an insn.
-   This is in static storage.
-
-   It may also output some insns directly.
-   It may alter the values of operands[0] and operands[1].  */
-
-char *
-output_load (operands)
-     rtx *operands;
-{
-  enum machine_mode mode = GET_MODE (operands[0]);
-  rtx address = XEXP (operands[1], 0);
-
-  /* We don't bother trying to see if we know %hi(address).
-     This is because we are doing a load, and if we know the
-     %hi value, we probably also know that value in memory.  */
-  cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-  cc_status.mdep = address;
-
-  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-	 && (cc_prev_status.flags & CC_HI_R31_ADJ)
-	 && address == cc_prev_status.mdep
-	 && cc_prev_status.mdep == cc_status.mdep))
-    {
-      CC_STATUS_INIT;
-      output_asm_insn ("orh %h1,%?r0,%?r31", operands);
-      cc_prev_status.mdep = address;
-    }
-
-  /* Code below isn't smart enough to move a doubleword in two parts,
-     so use output_move_double to do that in the cases that require it.  */
-  if ((mode == DImode || mode == DFmode)
-      && ! FP_REG_P (operands[0]))
-    return output_move_double (operands);
-
-  return load_opcode (mode, "%L1(%?r31),%0", operands[0]);
-}
-
-#if 0
-/* Load the address specified by OPERANDS[3] into the register
-   specified by OPERANDS[0].
-
-   OPERANDS[3] may be the result of a sum, hence it could either be:
-
-   (1) CONST
-   (2) REG
-   (2) REG + CONST_INT
-   (3) REG + REG + CONST_INT
-   (4) REG + REG  (special case of 3).
-
-   Note that (3) is not a legitimate address.
-   All cases are handled here.  */
-
-void
-output_load_address (operands)
-     rtx *operands;
-{
-  rtx base, offset;
-
-  if (CONSTANT_P (operands[3]))
-    {
-      output_asm_insn ("mov %3,%0", operands);
-      return;
-    }
-
-  if (REG_P (operands[3]))
-    {
-      if (REGNO (operands[0]) != REGNO (operands[3]))
-	output_asm_insn ("shl %?r0,%3,%0", operands);
-      return;
-    }
-
-  if (GET_CODE (operands[3]) != PLUS)
-    abort ();
-
-  base = XEXP (operands[3], 0);
-  offset = XEXP (operands[3], 1);
-
-  if (GET_CODE (base) == CONST_INT)
-    {
-      rtx tmp = base;
-      base = offset;
-      offset = tmp;
-    }
-
-  if (GET_CODE (offset) != CONST_INT)
-    {
-      /* Operand is (PLUS (REG) (REG)).  */
-      base = operands[3];
-      offset = const0_rtx;
-    }
-
-  if (REG_P (base))
-    {
-      operands[6] = base;
-      operands[7] = offset;
-      CC_STATUS_PARTIAL_INIT;
-      if (SMALL_INT (offset))
-	output_asm_insn ("adds %7,%6,%0", operands);
-      else
-	output_asm_insn ("mov %7,%0\n\tadds %0,%6,%0", operands);
-    }
-  else if (GET_CODE (base) == PLUS)
-    {
-      operands[6] = XEXP (base, 0);
-      operands[7] = XEXP (base, 1);
-      operands[8] = offset;
-
-      CC_STATUS_PARTIAL_INIT;
-      if (SMALL_INT (offset))
-	output_asm_insn ("adds %6,%7,%0\n\tadds %8,%0,%0", operands);
-      else
-	output_asm_insn ("mov %8,%0\n\tadds %0,%6,%0\n\tadds %0,%7,%0", operands);
-    }
-  else
-    abort ();
-}
-#endif
-
-/* Output code to place a size count SIZE in register REG.
-   Because block moves are pipelined, we don't include the
-   first element in the transfer of SIZE to REG.
-   For this, we subtract ALIGN.  (Actually, I think it is not
-   right to subtract on this machine, so right now we don't.)  */
-
-static void
-output_size_for_block_move (size, reg, align)
-     rtx size, reg, align;
-{
-  rtx xoperands[3];
-
-  xoperands[0] = reg;
-  xoperands[1] = size;
-  xoperands[2] = align;
-
-#if 1
-  cc_status.flags &= ~ CC_KNOW_HI_R31;
-  output_asm_insn (singlemove_string (xoperands), xoperands);
-#else
-  if (GET_CODE (size) == REG)
-    output_asm_insn ("sub %2,%1,%0", xoperands);
-  else
-    {
-      xoperands[1]
-	= GEN_INT (INTVAL (size) - INTVAL (align));
-      cc_status.flags &= ~ CC_KNOW_HI_R31;
-      output_asm_insn ("mov %1,%0", xoperands);
-    }
-#endif
-}
-
-/* Emit code to perform a block move.
-
-   OPERANDS[0] is the destination.
-   OPERANDS[1] is the source.
-   OPERANDS[2] is the size.
-   OPERANDS[3] is the known safe alignment.
-   OPERANDS[4..6] are pseudos we can safely clobber as temps.  */
-
-char *
-output_block_move (operands)
-     rtx *operands;
-{
-  /* A vector for our computed operands.  Note that load_output_address
-     makes use of (and can clobber) up to the 8th element of this vector.  */
-  rtx xoperands[10];
-  rtx zoperands[10];
-  static int movstrsi_label = 0;
-  int i, j;
-  rtx temp1 = operands[4];
-  rtx alignrtx = operands[3];
-  int align = INTVAL (alignrtx);
-  int chunk_size;
-
-  xoperands[0] = operands[0];
-  xoperands[1] = operands[1];
-  xoperands[2] = temp1;
-
-  /* We can't move more than four bytes at a time
-     because we have only one register to move them through.  */
-  if (align > 4)
-    {
-      align = 4;
-      alignrtx = GEN_INT (4);
-    }
-
-  /* Recognize special cases of block moves.  These occur
-     when GNU C++ is forced to treat something as BLKmode
-     to keep it in memory, when its mode could be represented
-     with something smaller.
-
-     We cannot do this for global variables, since we don't know
-     what pages they don't cross.  Sigh.  */
-  if (GET_CODE (operands[2]) == CONST_INT
-      && ! CONSTANT_ADDRESS_P (operands[0])
-      && ! CONSTANT_ADDRESS_P (operands[1]))
-    {
-      int size = INTVAL (operands[2]);
-      rtx op0 = xoperands[0];
-      rtx op1 = xoperands[1];
-
-      if ((align & 3) == 0 && (size & 3) == 0 && (size >> 2) <= 16)
-	{
-	  if (memory_address_p (SImode, plus_constant (op0, size))
-	      && memory_address_p (SImode, plus_constant (op1, size)))
-	    {
-	      cc_status.flags &= ~CC_KNOW_HI_R31;
-	      for (i = (size>>2)-1; i >= 0; i--)
-		{
-		  xoperands[0] = plus_constant (op0, i * 4);
-		  xoperands[1] = plus_constant (op1, i * 4);
-		  output_asm_insn ("ld.l %a1,%?r31\n\tst.l %?r31,%a0",
-				   xoperands);
-		}
-	      return "";
-	    }
-	}
-      else if ((align & 1) == 0 && (size & 1) == 0 && (size >> 1) <= 16)
-	{
-	  if (memory_address_p (HImode, plus_constant (op0, size))
-	      && memory_address_p (HImode, plus_constant (op1, size)))
-	    {
-	      cc_status.flags &= ~CC_KNOW_HI_R31;
-	      for (i = (size>>1)-1; i >= 0; i--)
-		{
-		  xoperands[0] = plus_constant (op0, i * 2);
-		  xoperands[1] = plus_constant (op1, i * 2);
-		  output_asm_insn ("ld.s %a1,%?r31\n\tst.s %?r31,%a0",
-				   xoperands);
-		}
-	      return "";
-	    }
-	}
-      else if (size <= 16)
-	{
-	  if (memory_address_p (QImode, plus_constant (op0, size))
-	      && memory_address_p (QImode, plus_constant (op1, size)))
-	    {
-	      cc_status.flags &= ~CC_KNOW_HI_R31;
-	      for (i = size-1; i >= 0; i--)
-		{
-		  xoperands[0] = plus_constant (op0, i);
-		  xoperands[1] = plus_constant (op1, i);
-		  output_asm_insn ("ld.b %a1,%?r31\n\tst.b %?r31,%a0",
-				   xoperands);
-		}
-	      return "";
-	    }
-	}
-    }
-
-  /* Since we clobber untold things, nix the condition codes.  */
-  CC_STATUS_INIT;
-
-  /* This is the size of the transfer.
-     Either use the register which already contains the size,
-     or use a free register (used by no operands).  */
-  output_size_for_block_move (operands[2], operands[4], alignrtx);
-
-#if 0
-  /* Also emit code to decrement the size value by ALIGN.  */
-  zoperands[0] = operands[0];
-  zoperands[3] = plus_constant (operands[0], align);
-  output_load_address (zoperands);
-#endif
-
-  /* Generate number for unique label.  */
-
-  xoperands[3] = GEN_INT (movstrsi_label++);
-
-  /* Calculate the size of the chunks we will be trying to move first.  */
-
-#if 0
-  if ((align & 3) == 0)
-    chunk_size = 4;
-  else if ((align & 1) == 0)
-    chunk_size = 2;
-  else
-#endif
-    chunk_size = 1;
-
-  /* Copy the increment (negative) to a register for bla insn.  */
-
-  xoperands[4] = GEN_INT (- chunk_size);
-  xoperands[5] = operands[5];
-  output_asm_insn ("adds %4,%?r0,%5", xoperands);
-
-  /* Predecrement the loop counter.  This happens again also in the `bla'
-     instruction which precedes the loop, but we need to have it done
-     two times before we enter the loop because of the bizarre semantics
-     of the bla instruction.  */
-
-  output_asm_insn ("adds %5,%2,%2", xoperands);
-
-  /* Check for the case where the original count was less than or equal to
-     zero.  Avoid going through the loop at all if the original count was
-     indeed less than or equal to zero.  Note that we treat the count as
-     if it were a signed 32-bit quantity here, rather than an unsigned one,
-     even though we really shouldn't.  We have to do this because of the
-     semantics of the `ble' instruction, which assume that the count is
-     a signed 32-bit value.  Anyway, in practice it won't matter because
-     nobody is going to try to do a memcpy() of more than half of the
-     entire address space (i.e. 2 gigabytes) anyway.  */
-
-  output_asm_insn ("bc .Le%3", xoperands);
-
-  /* Make available a register which is a temporary.  */
-
-  xoperands[6] = operands[6];
-
-  /* Now the actual loop.
-     In xoperands, elements 1 and 0 are the input and output vectors.
-     Element 2 is the loop index.  Element 5 is the increment.  */
-
-  output_asm_insn ("subs %1,%5,%1", xoperands);
-  output_asm_insn ("bla %5,%2,.Lm%3", xoperands);
-  output_asm_insn ("adds %0,%2,%6", xoperands);
-  output_asm_insn ("\n.Lm%3:", xoperands);	    /* Label for bla above.  */
-  output_asm_insn ("\n.Ls%3:",  xoperands);	    /* Loop start label. */
-  output_asm_insn ("adds %5,%6,%6", xoperands);
-
-  /* NOTE:  The code here which is supposed to handle the cases where the
-     sources and destinations are known to start on a 4 or 2 byte boundary
-     are currently broken.  They fail to do anything about the overflow
-     bytes which might still need to be copied even after we have copied
-     some number of words or halfwords.  Thus, for now we use the lowest
-     common denominator, i.e. the code which just copies some number of
-     totally unaligned individual bytes.  (See the calculation of
-     chunk_size above.  */
-
-  if (chunk_size == 4)
-    {
-      output_asm_insn ("ld.l %2(%1),%?r31", xoperands);
-      output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
-      output_asm_insn ("st.l %?r31,8(%6)", xoperands);
-    }
-  else if (chunk_size == 2)
-    {
-      output_asm_insn ("ld.s %2(%1),%?r31", xoperands);
-      output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
-      output_asm_insn ("st.s %?r31,4(%6)", xoperands);
-    }
-  else /* chunk_size == 1 */
-    {
-      output_asm_insn ("ld.b %2(%1),%?r31", xoperands);
-      output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
-      output_asm_insn ("st.b %?r31,2(%6)", xoperands);
-    }
-  output_asm_insn ("\n.Le%3:", xoperands);	    /* Here if count <= 0.  */
-
-  return "";
-}
-
-/* Output a delayed branch insn with the delay insn in its
-   branch slot.  The delayed branch insn template is in TEMPLATE,
-   with operands OPERANDS.  The insn in its delay slot is INSN.
-
-   As a special case, since we know that all memory transfers are via
-   ld/st insns, if we see a (MEM (SYMBOL_REF ...)) we divide the memory
-   reference around the branch as
-
-	orh ha%x,%?r0,%?r31
-	b ...
-	ld/st l%x(%?r31),...
-
-   As another special case, we handle loading (SYMBOL_REF ...) and
-   other large constants around branches as well:
-
-	orh h%x,%?r0,%0
-	b ...
-	or l%x,%0,%1
-
-   */
-
-char *
-output_delayed_branch (template, operands, insn)
-     char *template;
-     rtx *operands;
-     rtx insn;
-{
-  rtx src = XVECEXP (PATTERN (insn), 0, 1);
-  rtx dest = XVECEXP (PATTERN (insn), 0, 0);
-
-  /* See if we are doing some branch together with setting some register
-     to some 32-bit value which does (or may) have some of the high-order
-     16 bits set.  If so, we need to set the register in two stages.  One
-     stage must be done before the branch, and the other one can be done
-     in the delay slot.  */
-
-  if ( (GET_CODE (src) == CONST_INT
-	&& ((unsigned) INTVAL (src) & (unsigned) 0xffff0000) != (unsigned) 0)
-      || (GET_CODE (src) == SYMBOL_REF)
-      || (GET_CODE (src) == LABEL_REF)
-      || (GET_CODE (src) == CONST))
-    {
-      rtx xoperands[2];
-      xoperands[0] = dest;
-      xoperands[1] = src;
-
-      CC_STATUS_PARTIAL_INIT;
-      /* Output the `orh' insn.  */
-      output_asm_insn ("orh %H1,%?r0,%0", xoperands);
-
-      /* Output the branch instruction next.  */
-      output_asm_insn (template, operands);
-
-      /* Now output the `or' insn.  */
-      output_asm_insn ("or %L1,%0,%0", xoperands);
-    }
-  else if ((GET_CODE (src) == MEM
-	    && CONSTANT_ADDRESS_P (XEXP (src, 0)))
-	   || (GET_CODE (dest) == MEM
-	       && CONSTANT_ADDRESS_P (XEXP (dest, 0))))
-    {
-      rtx xoperands[2];
-      char *split_template;
-      xoperands[0] = dest;
-      xoperands[1] = src;
-
-      /* Output the `orh' insn.  */
-      if (GET_CODE (src) == MEM)
-	{
-	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-		 && (cc_prev_status.flags & CC_HI_R31_ADJ)
-		 && cc_prev_status.mdep == XEXP (operands[1], 0)))
-	    {
-	      CC_STATUS_INIT;
-	      output_asm_insn ("orh %h1,%?r0,%?r31", xoperands);
-	    }
-	  split_template = load_opcode (GET_MODE (dest),
-					"%L1(%?r31),%0", dest);
-	}
-      else
-	{
-	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-		 && (cc_prev_status.flags & CC_HI_R31_ADJ)
-		 && cc_prev_status.mdep == XEXP (operands[0], 0)))
-	    {
-	      CC_STATUS_INIT;
-	      output_asm_insn ("orh %h0,%?r0,%?r31", xoperands);
-	    }
-	  split_template = store_opcode (GET_MODE (dest),
-					 "%r1,%L0(%?r31)", src);
-	}
-
-      /* Output the branch instruction next.  */
-      output_asm_insn (template, operands);
-
-      /* Now output the load or store.
-	 No need to do a CC_STATUS_INIT, because we are branching anyway.  */
-      output_asm_insn (split_template, xoperands);
-    }
-  else
-    {
-      int insn_code_number;
-      rtx pat = gen_rtx (SET, VOIDmode, dest, src);
-      rtx delay_insn = gen_rtx (INSN, VOIDmode, 0, 0, 0, pat, -1, 0, 0);
-      int i;
-
-      /* Output the branch instruction first.  */
-      output_asm_insn (template, operands);
-
-      /* Now recognize the insn which we put in its delay slot.
-	 We must do this after outputting the branch insn,
-	 since operands may just be a pointer to `recog_operand'.  */
-      INSN_CODE (delay_insn) = insn_code_number
-	= recog (pat, delay_insn, NULL_PTR);
-      if (insn_code_number == -1)
-	abort ();
-
-      for (i = 0; i < insn_n_operands[insn_code_number]; i++)
-	{
-	  if (GET_CODE (recog_operand[i]) == SUBREG)
-	    recog_operand[i] = alter_subreg (recog_operand[i]);
-	}
-
-      insn_extract (delay_insn);
-      if (! constrain_operands (insn_code_number, 1))
-	fatal_insn_not_found (delay_insn);
-
-      template = insn_template[insn_code_number];
-      if (template == 0)
-	template = (*insn_outfun[insn_code_number]) (recog_operand, delay_insn);
-      output_asm_insn (template, recog_operand);
-    }
-  CC_STATUS_INIT;
-  return "";
-}
-
-/* Output a newly constructed insn DELAY_INSN.  */
-char *
-output_delay_insn (delay_insn)
-     rtx delay_insn;
-{
-  char *template;
-  int insn_code_number;
-  int i;
-
-  /* Now recognize the insn which we put in its delay slot.
-     We must do this after outputting the branch insn,
-     since operands may just be a pointer to `recog_operand'.  */
-  insn_code_number = recog_memoized (delay_insn);
-  if (insn_code_number == -1)
-    abort ();
-
-  /* Extract the operands of this delay insn.  */
-  INSN_CODE (delay_insn) = insn_code_number;
-  insn_extract (delay_insn);
-
-  /* It is possible that this insn has not been properly scanned by final
-     yet.  If this insn's operands don't appear in the peephole's
-     actual operands, then they won't be fixed up by final, so we
-     make sure they get fixed up here.  -- This is a kludge.  */
-  for (i = 0; i < insn_n_operands[insn_code_number]; i++)
-    {
-      if (GET_CODE (recog_operand[i]) == SUBREG)
-	recog_operand[i] = alter_subreg (recog_operand[i]);
-    }
-
-#ifdef REGISTER_CONSTRAINTS
-  if (! constrain_operands (insn_code_number, 1))
-    abort ();
-#endif
-
-  cc_prev_status = cc_status;
-
-  /* Update `cc_status' for this instruction.
-     The instruction's output routine may change it further.
-     If the output routine for a jump insn needs to depend
-     on the cc status, it should look at cc_prev_status.  */
-
-  NOTICE_UPDATE_CC (PATTERN (delay_insn), delay_insn);
-
-  /* Now get the template for what this insn would
-     have been, without the branch.  */
-
-  template = insn_template[insn_code_number];
-  if (template == 0)
-    template = (*insn_outfun[insn_code_number]) (recog_operand, delay_insn);
-  output_asm_insn (template, recog_operand);
-  return "";
-}
-
-/* Special routine to convert an SFmode value represented as a
-   CONST_DOUBLE into its equivalent unsigned long bit pattern.
-   We convert the value from a double precision floating-point
-   value to single precision first, and thence to a bit-wise
-   equivalent unsigned long value.  This routine is used when
-   generating an immediate move of an SFmode value directly
-   into a general register because the svr4 assembler doesn't
-   grok floating literals in instruction operand contexts.  */
-
-unsigned long
-sfmode_constant_to_ulong (x)
-     rtx x;
-{
-  REAL_VALUE_TYPE d;
-  union { float f; unsigned long i; } u2;
-
-  if (GET_CODE (x) != CONST_DOUBLE || GET_MODE (x) != SFmode)
-    abort ();
-
-#if TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT
- error IEEE emulation needed
-#endif
-  REAL_VALUE_FROM_CONST_DOUBLE (d, x);
-  u2.f = d;
-  return u2.i;
-}
-
-/* This function generates the assembly code for function entry.
-   The macro FUNCTION_PROLOGUE in i860.h is defined to call this function.
-
-   ASM_FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.
-
-   NOTE: `frame_lower_bytes' is the count of bytes which will lie
-   between the new `fp' value and the new `sp' value after the
-   prologue is done.  `frame_upper_bytes' is the count of bytes
-   that will lie between the new `fp' and the *old* `sp' value
-   after the new `fp' is setup (in the prologue).  The upper
-   part of each frame always includes at least 2 words (8 bytes)
-   to hold the saved frame pointer and the saved return address.
-
-   The svr4 ABI for the i860 now requires that the values of the
-   stack pointer and frame pointer registers be kept aligned to
-   16-byte boundaries at all times.  We obey that restriction here.
-
-   The svr4 ABI for the i860 is entirely vague when it comes to specifying
-   exactly where the "preserved" registers should be saved.  The native
-   svr4 C compiler I now have doesn't help to clarify the requirements
-   very much because it is plainly out-of-date and non-ABI-compliant
-   (in at least one important way, i.e. how it generates function
-   epilogues).
-
-   The native svr4 C compiler saves the "preserved" registers (i.e.
-   r4-r15 and f2-f7) in the lower part of a frame (i.e. at negative
-   offsets from the frame pointer).
-
-   Previous versions of GCC also saved the "preserved" registers in the
-   "negative" part of the frame, but they saved them using positive
-   offsets from the (adjusted) stack pointer (after it had been adjusted
-   to allocate space for the new frame).  That's just plain wrong
-   because if the current function calls alloca(), the stack pointer
-   will get moved, and it will be impossible to restore the registers
-   properly again after that.
-
-   Both compilers handled parameter registers (i.e. r16-r27 and f8-f15)
-   by copying their values either into various "preserved" registers or
-   into stack slots in the lower part of the current frame (as seemed
-   appropriate, depending upon subsequent usage of these values).
-
-   Here we want to save the preserved registers at some offset from the
-   frame pointer register so as to avoid any possible problems arising
-   from calls to alloca().  We can either save them at small positive
-   offsets from the frame pointer, or at small negative offsets from
-   the frame pointer.  If we save them at small negative offsets from
-   the frame pointer (i.e. in the lower part of the frame) then we
-   must tell the rest of GCC (via STARTING_FRAME_OFFSET) exactly how
-   many bytes of space we plan to use in the lower part of the frame
-   for this purpose.  Since other parts of the compiler reference the
-   value of STARTING_FRAME_OFFSET long before final() calls this function,
-   we would have to go ahead and assume the worst-case storage requirements
-   for saving all of the "preserved" registers (and use that number, i.e.
-   `80', to define STARTING_FRAME_OFFSET) if we wanted to save them in
-   the lower part of the frame.  That could potentially be very wasteful,
-   and that wastefulness could really hamper people compiling for embedded
-   i860 targets with very tight limits on stack space.  Thus, we choose
-   here to save the preserved registers in the upper part of the
-   frame, so that we can decide at the very last minute how much (or how
-   little) space we must allocate for this purpose.
-
-   To satisfy the needs of the svr4 ABI "tdesc" scheme, preserved
-   registers must always be saved so that the saved values of registers
-   with higher numbers are at higher addresses.  We obey that restriction
-   here.
-
-   There are two somewhat different ways that you can generate prologues
-   here... i.e. pedantically ABI-compliant, and the "other" way.  The
-   "other" way is more consistent with what is currently generated by the
-   "native" svr4 C compiler for the i860.  That's important if you want
-   to use the current (as of 8/91) incarnation of svr4 SDB for the i860.
-   The SVR4 SDB for the i860 insists on having function prologues be
-   non-ABI-compliant!
-
-   To get fully ABI-compliant prologues, define I860_STRICT_ABI_PROLOGUES
-   in the i860svr4.h file.  (By default this is *not* defined).
-
-   The differences between the ABI-compliant and non-ABI-compliant prologues
-   are that (a) the ABI version seems to require the use of *signed*
-   (rather than unsigned) adds and subtracts, and (b) the ordering of
-   the various steps (e.g. saving preserved registers, saving the
-   return address, setting up the new frame pointer value) is different.
-
-   For strict ABI compliance, it seems to be the case that the very last
-   thing that is supposed to happen in the prologue is getting the frame
-   pointer set to its new value (but only after everything else has
-   already been properly setup).  We do that here, but only if the symbol
-   I860_STRICT_ABI_PROLOGUES is defined.
-*/
-
-#ifndef STACK_ALIGNMENT
-#define STACK_ALIGNMENT	16
-#endif
-
-extern char call_used_regs[];
-extern int leaf_function_p ();
-
-char *current_function_original_name;
-
-static int must_preserve_r1;
-static unsigned must_preserve_bytes;
-
-void
-function_prologue (asm_file, local_bytes)
-     register FILE *asm_file;
-     register unsigned local_bytes;
-{
-  register unsigned frame_lower_bytes;
-  register unsigned frame_upper_bytes;
-  register unsigned total_fsize;
-  register unsigned preserved_reg_bytes = 0;
-  register unsigned i;
-  register unsigned preserved_so_far = 0;
-
-  must_preserve_r1 = (optimize < 2 || ! leaf_function_p ());
-  must_preserve_bytes = 4 + (must_preserve_r1 ? 4 : 0);
-
-  /* Count registers that need preserving.  Ignore r0.  It never needs
-     preserving.  */
-
-  for (i = 1; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      if (regs_ever_live[i] && ! call_used_regs[i])
-        preserved_reg_bytes += 4;
-    }
-
-  /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
-
-  frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
-
-  /* The upper part of each frame will contain the saved fp,
-     the saved r1, and stack slots for all of the other "preserved"
-     registers that we find we will need to save & restore. */
-
-  frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes;
-
-  /* Round-up the frame_upper_bytes so that it's a multiple of 16. */
-
-  frame_upper_bytes
-    = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
-
-  total_fsize = frame_upper_bytes + frame_lower_bytes;
-
-#ifndef I860_STRICT_ABI_PROLOGUES
-
-  /* There are two kinds of function prologues.
-     You use the "small" version if the total frame size is
-     small enough so that it can fit into an immediate 16-bit
-     value in one instruction.  Otherwise, you use the "large"
-     version of the function prologue.  */
-
-  if (total_fsize > 0x7fff)
-    {
-      /* Adjust the stack pointer.  The ABI sez to do this using `adds',
-	 but the native C compiler on svr4 uses `addu'.  */
-
-      fprintf (asm_file, "\taddu -%d,%ssp,%ssp\n",
-	frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
-
-      /* Save the old frame pointer.  */
-
-      fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n",
-	i860_reg_prefix, i860_reg_prefix);
-
-      /* Setup the new frame pointer.  The ABI sez to do this after
-	 preserving registers (using adds), but that's not what the
-	 native C compiler on svr4 does.  */
-
-      fprintf (asm_file, "\taddu 0,%ssp,%sfp\n",
-	i860_reg_prefix, i860_reg_prefix);
-
-      /* Get the value of frame_lower_bytes into r31.  */
-
-      fprintf (asm_file, "\torh %d,%sr0,%sr31\n",
-	frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix);
-      fprintf (asm_file, "\tor %d,%sr31,%sr31\n",
-	frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix);
-
-      /* Now re-adjust the stack pointer using the value in r31.
-	 The ABI sez to do this with `subs' but SDB may prefer `subu'.  */
-
-      fprintf (asm_file, "\tsubu %ssp,%sr31,%ssp\n",
-	i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
-
-      /* Preserve registers.  The ABI sez to do this before setting
-	 up the new frame pointer, but that's not what the native
-	 C compiler on svr4 does.  */
-
-      for (i = 1; i < 32; i++)
-        if (regs_ever_live[i] && ! call_used_regs[i])
-          fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n",
-	    i860_reg_prefix, reg_names[i],
-	    must_preserve_bytes  + (4 * preserved_so_far++),
-	    i860_reg_prefix);
-
-      for (i = 32; i < 64; i++)
-        if (regs_ever_live[i] && ! call_used_regs[i])
-          fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n",
-	    i860_reg_prefix, reg_names[i],
-	    must_preserve_bytes + (4 * preserved_so_far++),
-	    i860_reg_prefix);
-
-      /* Save the return address.  */
-
-      if (must_preserve_r1)
-        fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n",
-	  i860_reg_prefix, i860_reg_prefix);
-    }
-  else
-    {
-      /* Adjust the stack pointer.  The ABI sez to do this using `adds',
-	 but the native C compiler on svr4 uses `addu'.  */
-
-      fprintf (asm_file, "\taddu -%d,%ssp,%ssp\n",
-	total_fsize, i860_reg_prefix, i860_reg_prefix);
-
-      /* Save the old frame pointer.  */
-
-      fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n",
-	i860_reg_prefix, frame_lower_bytes, i860_reg_prefix);
-
-      /* Setup the new frame pointer.  The ABI sez to do this after
-	 preserving registers and after saving the return address,
-	(and its saz to do this using adds), but that's not what the
-	 native C compiler on svr4 does.  */
-
-      fprintf (asm_file, "\taddu %d,%ssp,%sfp\n",
-	frame_lower_bytes, i860_reg_prefix, i860_reg_prefix);
-
-      /* Preserve registers.  The ABI sez to do this before setting
-	 up the new frame pointer, but that's not what the native
-	 compiler on svr4 does.  */
-
-      for (i = 1; i < 32; i++)
-        if (regs_ever_live[i] && ! call_used_regs[i])
-          fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n",
-	    i860_reg_prefix, reg_names[i],
-	    must_preserve_bytes + (4 * preserved_so_far++),
-	    i860_reg_prefix);
-
-      for (i = 32; i < 64; i++)
-        if (regs_ever_live[i] && ! call_used_regs[i])
-          fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n",
-	    i860_reg_prefix, reg_names[i],
-	    must_preserve_bytes + (4 * preserved_so_far++),
-	    i860_reg_prefix);
-
-      /* Save the return address.  The ABI sez to do this earlier,
-	 and also via an offset from %sp, but the native C compiler
-	 on svr4 does it later (i.e. now) and uses an offset from
-	 %fp.  */
-
-      if (must_preserve_r1)
-        fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n",
-	  i860_reg_prefix, i860_reg_prefix);
-    }
-
-#else /* defined(I860_STRICT_ABI_PROLOGUES) */
-
-  /* There are two kinds of function prologues.
-     You use the "small" version if the total frame size is
-     small enough so that it can fit into an immediate 16-bit
-     value in one instruction.  Otherwise, you use the "large"
-     version of the function prologue.  */
-
-  if (total_fsize > 0x7fff)
-    {
-      /* Adjust the stack pointer (thereby allocating a new frame).  */
-
-      fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n",
-	frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
-
-      /* Save the caller's frame pointer.  */
-
-      fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n",
-	i860_reg_prefix, i860_reg_prefix);
-
-      /* Save return address.  */
-
-      if (must_preserve_r1)
-        fprintf (asm_file, "\tst.l %sr1,4(%ssp)\n",
-	  i860_reg_prefix, i860_reg_prefix);
-
-      /* Get the value of frame_lower_bytes into r31 for later use.  */
-
-      fprintf (asm_file, "\torh %d,%sr0,%sr31\n",
-	frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix);
-      fprintf (asm_file, "\tor %d,%sr31,%sr31\n",
-	frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix);
-
-      /* Now re-adjust the stack pointer using the value in r31.  */
-
-      fprintf (asm_file, "\tsubs %ssp,%sr31,%ssp\n",
-	i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
-
-      /* Pre-compute value to be used as the new frame pointer.  */
-
-      fprintf (asm_file, "\tadds %ssp,%sr31,%sr31\n",
-	i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
-
-      /* Preserve registers.  */
-
-      for (i = 1; i < 32; i++)
-        if (regs_ever_live[i] && ! call_used_regs[i])
-          fprintf (asm_file, "\tst.l %s%s,%d(%sr31)\n",
-	    i860_reg_prefix, reg_names[i],
-	    must_preserve_bytes + (4 * preserved_so_far++),
-	    i860_reg_prefix);
-
-      for (i = 32; i < 64; i++)
-        if (regs_ever_live[i] && ! call_used_regs[i])
-          fprintf (asm_file, "\tfst.l %s%s,%d(%sr31)\n",
-	    i860_reg_prefix, reg_names[i],
-	    must_preserve_bytes + (4 * preserved_so_far++),
-	    i860_reg_prefix);
-
-      /* Actually set the new value of the frame pointer.  */
-
-      fprintf (asm_file, "\tmov %sr31,%sfp\n",
-	i860_reg_prefix, i860_reg_prefix);
-    }
-  else
-    {
-      /* Adjust the stack pointer.  */
-
-      fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n",
-	total_fsize, i860_reg_prefix, i860_reg_prefix);
-
-      /* Save the caller's frame pointer.  */
-
-      fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n",
-	i860_reg_prefix, frame_lower_bytes, i860_reg_prefix);
-
-      /* Save the return address.  */
-
-      if (must_preserve_r1)
-        fprintf (asm_file, "\tst.l %sr1,%d(%ssp)\n",
-	  i860_reg_prefix, frame_lower_bytes + 4, i860_reg_prefix);
-
-      /* Preserve registers.  */
-
-      for (i = 1; i < 32; i++)
-        if (regs_ever_live[i] && ! call_used_regs[i])
-          fprintf (asm_file, "\tst.l %s%s,%d(%ssp)\n",
-	    i860_reg_prefix, reg_names[i],
-	    frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++),
-	    i860_reg_prefix);
-
-      for (i = 32; i < 64; i++)
-        if (regs_ever_live[i] && ! call_used_regs[i])
-          fprintf (asm_file, "\tfst.l %s%s,%d(%ssp)\n",
-	    i860_reg_prefix, reg_names[i],
-	    frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++),
-	    i860_reg_prefix);
-
-      /* Setup the new frame pointer.  */
-
-      fprintf (asm_file, "\tadds %d,%ssp,%sfp\n",
-	frame_lower_bytes, i860_reg_prefix, i860_reg_prefix);
-    }
-#endif /* defined(I860_STRICT_ABI_PROLOGUES) */
-
-#ifdef ASM_OUTPUT_PROLOGUE_SUFFIX
-  ASM_OUTPUT_PROLOGUE_SUFFIX (asm_file);
-#endif /* defined(ASM_OUTPUT_PROLOGUE_SUFFIX) */
-}
-
-/* This function generates the assembly code for function exit.
-   The macro FUNCTION_EPILOGUE in i860.h is defined to call this function.
-
-   ASM_FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.
-
-   Note that when we go to restore the preserved register values we must
-   not try to address their slots by using offsets from the stack pointer.
-   That's because the stack pointer may have been moved during the function
-   execution due to a call to alloca().  Rather, we must restore all
-   preserved registers via offsets from the frame pointer value.
-
-   Note also that when the current frame is being "popped" (by adjusting
-   the value of the stack pointer) on function exit, we must (for the
-   sake of alloca) set the new value of the stack pointer based upon
-   the current value of the frame pointer.  We can't just add what we
-   believe to be the (static) frame size to the stack pointer because
-   if we did that, and alloca() had been called during this function,
-   we would end up returning *without* having fully deallocated all of
-   the space grabbed by alloca.  If that happened, and a function
-   containing one or more alloca() calls was called over and over again,
-   then the stack would grow without limit!
-
-   Finally note that the epilogues generated here are completely ABI
-   compliant.  They go out of their way to insure that the value in
-   the frame pointer register is never less than the value in the stack
-   pointer register.  It's not clear why this relationship needs to be
-   maintained at all times, but maintaining it only costs one extra
-   instruction, so what the hell.
-*/
-
-/* This corresponds to a version 4 TDESC structure. Lower numbered
-   versions successively omit the last word of the structure. We
-   don't try to handle version 5 here. */
-
-typedef struct TDESC_flags {
-	int version:4;
-	int reg_packing:1;
-	int callable_block:1;
-	int reserved:4;
-	int fregs:6;	/* fp regs 2-7 */
-	int iregs:16;	/* regs 0-15 */
-} TDESC_flags;
-
-typedef struct TDESC {
-	TDESC_flags flags;
-	int integer_reg_offset;		/* same as must_preserve_bytes */
-	int floating_point_reg_offset;
-	unsigned int positive_frame_size;	/* same as frame_upper_bytes */
-	unsigned int negative_frame_size;	/* same as frame_lower_bytes */
-} TDESC;
-
-void
-function_epilogue (asm_file, local_bytes)
-     register FILE *asm_file;
-     register unsigned local_bytes;
-{
-  register unsigned frame_upper_bytes;
-  register unsigned frame_lower_bytes;
-  register unsigned preserved_reg_bytes = 0;
-  register unsigned i;
-  register unsigned restored_so_far = 0;
-  register unsigned int_restored;
-  register unsigned mask;
-  unsigned intflags=0;
-  register TDESC_flags *flags = (TDESC_flags *) &intflags;
-
-  flags->version = 4;
-  flags->reg_packing = 1;
-  flags->iregs = 8;	/* old fp always gets saved */
-
-  /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
-
-  frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
-
-  /* Count the number of registers that were preserved in the prologue.
-     Ignore r0.  It is never preserved.  */
-
-  for (i = 1; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      if (regs_ever_live[i] && ! call_used_regs[i])
-        preserved_reg_bytes += 4;
-    }
-
-  /* The upper part of each frame will contain only saved fp,
-     the saved r1, and stack slots for all of the other "preserved"
-     registers that we find we will need to save & restore. */
-
-  frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes;
-
-  /* Round-up frame_upper_bytes so that t is a multiple of 16. */
-
-  frame_upper_bytes
-    = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
-
-  /* Restore all of the "preserved" registers that need restoring.  */
-
-  mask = 2;
-
-  for (i = 1; i < 32; i++, mask<<=1)
-    if (regs_ever_live[i] && ! call_used_regs[i]) {
-      fprintf (asm_file, "\tld.l %d(%sfp),%s%s\n",
-	must_preserve_bytes + (4 * restored_so_far++),
-	i860_reg_prefix, i860_reg_prefix, reg_names[i]);
-      if (i > 3 && i < 16)
-	flags->iregs |= mask;
-    }
-
-  int_restored = restored_so_far;
-  mask = 1;
-
-  for (i = 32; i < 64; i++) {
-    if (regs_ever_live[i] && ! call_used_regs[i]) {
-      fprintf (asm_file, "\tfld.l %d(%sfp),%s%s\n",
-	must_preserve_bytes + (4 * restored_so_far++),
-	i860_reg_prefix, i860_reg_prefix, reg_names[i]);
-      if (i > 33 & i < 40)
-	flags->fregs |= mask;
-    }
-    if (i > 33 && i < 40)
-      mask<<=1;
-  }
-
-  /* Get the value we plan to use to restore the stack pointer into r31.  */
-
-  fprintf (asm_file, "\tadds %d,%sfp,%sr31\n",
-    frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
-
-  /* Restore the return address and the old frame pointer.  */
-
-  if (must_preserve_r1) {
-    fprintf (asm_file, "\tld.l 4(%sfp),%sr1\n",
-      i860_reg_prefix, i860_reg_prefix);
-    flags->iregs |= 2;
-  }
-
-  fprintf (asm_file, "\tld.l 0(%sfp),%sfp\n",
-    i860_reg_prefix, i860_reg_prefix);
-
-  /* Return and restore the old stack pointer value.  */
-
-  fprintf (asm_file, "\tbri %sr1\n\tmov %sr31,%ssp\n",
-    i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
-
-#ifdef	OUTPUT_TDESC	/* Output an ABI-compliant TDESC entry */
-  if (! frame_lower_bytes) {
-    flags->version--;
-    if (! frame_upper_bytes) {
-      flags->version--;
-      if (restored_so_far == int_restored)	/* No FP saves */
-	flags->version--;
-    }
-  }
-  assemble_name(asm_file,current_function_original_name);
-  fputs(".TDESC:\n", asm_file);
-  fprintf(asm_file, "%s 0x%0x\n", ASM_LONG, intflags);
-  fprintf(asm_file, "%s %d\n", ASM_LONG,
-	int_restored ? must_preserve_bytes : 0);
-  if (flags->version > 1) {
-    fprintf(asm_file, "%s %d\n", ASM_LONG,
-	(restored_so_far == int_restored) ? 0 : must_preserve_bytes +
-	  (4 * int_restored));
-    if (flags->version > 2) {
-      fprintf(asm_file, "%s %d\n", ASM_LONG, frame_upper_bytes);
-      if (flags->version > 3)
-	fprintf(asm_file, "%s %d\n", ASM_LONG, frame_lower_bytes);
-    }
-  }
-  tdesc_section();
-  fprintf(asm_file, "%s ", ASM_LONG);
-  assemble_name(asm_file, current_function_original_name);
-  fprintf(asm_file, "\n%s ", ASM_LONG);
-  assemble_name(asm_file, current_function_original_name);
-  fputs(".TDESC\n", asm_file);
-  text_section();
-#endif
-}
diff --git a/gcc/config/i860/i860.h b/gcc/config/i860/i860.h
deleted file mode 100755
index d6b2911..0000000
--- a/gcc/config/i860/i860.h
+++ /dev/null
@@ -1,1432 +0,0 @@
-/* Definitions of target machine for GNU compiler, for Intel 860.
-   Copyright (C) 1989, 91, 93, 95, 96, 1997 Free Software Foundation, Inc.
-   Hacked substantially by Ron Guilmette (rfg@monkeys.com) to cater to
-   the whims of the System V Release 4 assembler.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Note that some other tm.h files include this one and then override
-   many of the definitions that relate to assembler syntax.  */
-
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Di860 -Dunix -Asystem(unix) -Asystem(svr4) -Acpu(i860) -Amachine(i860)"
-
-/* Print subsidiary information on the compiler version in use.  */
-#define TARGET_VERSION fprintf (stderr, " (i860)");
-
-/* Run-time compilation parameters selecting different hardware subsets
-   or supersets.
-
-   On the i860, we have one: TARGET_XP.  This option allows gcc to generate
-   additional instructions available only on the newer i860 XP (but not on
-   the older i860 XR).
-*/
-
-extern int target_flags;
-
-/* Nonzero if we should generate code to use the fpu.  */
-#define TARGET_XP (target_flags & 1)
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  { {"xp", 1},			\
-    {"noxp", -1},		\
-    {"xr", -1},			\
-    { "", TARGET_DEFAULT}}
-
-#define TARGET_DEFAULT 0
-
-/* target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is a moot question on the i860 due to the lack of bit-field insns.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is not true on i860 in the mode we will use.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.  */
-/* For the i860 this goes with BYTES_BIG_ENDIAN.  */
-/* NOTE: GCC probably cannot support a big-endian i860
-   because GCC fundamentally assumes that the order of words
-   in memory as the same as the order in registers.
-   That's not true for the big-endian i860.
-   The big-endian i860 isn't important enough to
-   justify the trouble of changing this assumption.  */
-#define WORDS_BIG_ENDIAN 0
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 128
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 64
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* Minimum size in bits of the largest boundary to which any
-   and all fundamental data types supported by the hardware
-   might need to be aligned. No data type wants to be aligned
-   rounder than this.  The i860 supports 128-bit (long double)
-   floating point quantities, and the System V Release 4 i860
-   ABI requires these to be aligned to 16-byte (128-bit)
-   boundaries.  */
-#define BIGGEST_ALIGNMENT 128
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* If bit field type is int, dont let it cross an int,
-   and give entire struct the alignment of an int.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   i860 has 32 fullword registers and 32 floating point registers.  */
-
-#define FIRST_PSEUDO_REGISTER 64
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   On the i860, this includes the always-0 registers
-   and fp, sp, arg pointer, and the return address.
-   Also r31, used for special purposes for constant addresses.  */
-#define FIXED_REGISTERS  \
- {1, 1, 1, 1, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 1,	\
-  1, 1, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   On the i860, these are r0-r3, r16-r31, f0, f1, and f16-f31.  */
-#define CALL_USED_REGISTERS  \
- {1, 1, 1, 1, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 0, 0, 0, 0, 0, 0,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1}
-
-/* Try to get a non-preserved register before trying to get one we will
-   have to preserve.  Try to get an FP register only *after* trying to
-   get a general register, because it is relatively expensive to move
-   into or out of an FP register.  */
-
-#define REG_ALLOC_ORDER			\
- {31, 30, 29, 28, 27, 26, 25, 24,	\
-  23, 22, 21, 20, 19, 18, 17, 16,	\
-  15, 14, 13, 12, 11, 10,  9,  8,	\
-   7,  6,  5,  4,  3,  2,  1,  0,	\
-  63, 62, 61, 60, 59, 58, 57, 56,	\
-  55, 54, 53, 52, 51, 50, 49, 48,	\
-  47, 46, 45, 44, 43, 42, 41, 40,	\
-  39, 38, 37, 36, 35, 34, 33, 32}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On the i860, all registers hold 32 bits worth.  */
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-#define REGNO_MODE_ALIGNED(REGNO, MODE) \
-  (((REGNO) % ((GET_MODE_UNIT_SIZE (MODE) + 3) / 4)) == 0)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-
-   On the i860, we allow anything to go into any registers, but we require
-   any sort of value going into the FP registers to be properly aligned
-   (based on its size) within the FP register set.
-*/
-#define HARD_REGNO_MODE_OK(REGNO, MODE)					\
-  (((REGNO) < 32) 							\
-   || (MODE) == VOIDmode || (MODE) == BLKmode				\
-   || REGNO_MODE_ALIGNED (REGNO, MODE))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-/* I think that is not always true; alignment restrictions for doubles
-   should not prevent tying them with singles.  So try allowing that.
-   On the other hand, don't let fixed and floating be tied;
-   this restriction is not necessary, but may make better code.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  ((GET_MODE_CLASS (MODE1) == MODE_FLOAT		\
-    || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)	\
-   == (GET_MODE_CLASS (MODE2) == MODE_FLOAT		\
-       || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* i860 pc isn't overloaded on a register that the compiler knows about.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 2
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 3
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 1
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 28
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 29
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 16
-
-/* Register to use when a source of a floating-point zero is needed.  */
-#define F0_REGNUM	32
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-/* The i860 has two kinds of registers, hence four classes.  */
-
-enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS	\
- {{0, 0}, {0xffffffff, 0},	\
-  {0, 0xffffffff}, {0xffffffff, 0xffffffff}}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) \
- ((REGNO) >= 32 ? FP_REGS : GENERAL_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'f' ? FP_REGS : NO_REGS)
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   For the i860, `I' is used for the range of constants 
-   an add/subtract insn can actually contain.
-   But not including -0x8000, since we need
-   to negate the constant sometimes.
-   `J' is used for the range which is just zero (since that is R0).
-   `K' is used for the range allowed in bte.
-   `L' is used for the range allowed in logical insns.  */
-
-#define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x7fff) < 0xffff)
-
-#define LOGIC_INT(X) ((unsigned) INTVAL (X) < 0x10000)
-
-#define SMALL_INTVAL(X) ((unsigned) ((X) + 0x7fff) < 0xffff)
-
-#define LOGIC_INTVAL(X) ((unsigned) (X) < 0x10000)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'I' ? ((unsigned) (VALUE) + 0x7fff) < 0xffff	\
-   : (C) == 'J' ? (VALUE) == 0				\
-   : (C) == 'K' ? (unsigned) (VALUE) < 0x20	\
-   : (C) == 'L' ? (unsigned) (VALUE) < 0x10000	\
-   : 0)
-
-/* Return non-zero if the given VALUE is acceptable for the
-   constraint letter C.  For the i860, constraint letter 'G'
-   permits only a floating-point zero value.  */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  	\
-  ((C) == 'G' && CONST_DOUBLE_LOW ((VALUE)) == 0	\
-   && CONST_DOUBLE_HIGH ((VALUE)) == 0)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.
-
-   If we are trying to put an integer constant into some register, prefer an
-   integer register to an FP register.  If we are trying to put a 
-   non-zero floating-point constant into some register, use an integer
-   register if the constant is SFmode and GENERAL_REGS is one of our options.
-   Otherwise, put the constant into memory.
-
-   When reloading something smaller than a word, use a general reg
-   rather than an FP reg.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)  \
-  ((CLASS) == ALL_REGS && GET_CODE (X) == CONST_INT ? GENERAL_REGS	\
-   : ((GET_MODE (X) == HImode || GET_MODE (X) == QImode)		\
-      && (CLASS) == ALL_REGS)						\
-   ? GENERAL_REGS							\
-   : (GET_CODE (X) == CONST_DOUBLE					\
-      && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT			\
-      && ! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G'))			\
-   ? ((CLASS) == ALL_REGS && GET_MODE (X) == SFmode ? GENERAL_REGS	\
-      : (CLASS) == GENERAL_REGS && GET_MODE (X) == SFmode ? (CLASS)	\
-      : NO_REGS)							\
-   : (CLASS))
-
-/* Return the register class of a scratch register needed to copy IN into
-   a register in CLASS in MODE.  If it can be done directly, NO_REGS is
-   returned.  */
-
-#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
-  ((CLASS) == FP_REGS && CONSTANT_P (IN) ? GENERAL_REGS : NO_REGS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-/* On the i860, this is the size of MODE in words.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On the i860, don't define this because there are no push insns.  */
-/*  #define PUSH_ROUNDING(BYTES) */
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-/* On the i860, the value register depends on the mode.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE),				\
-	   (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT	\
-	    ? 40 : 16))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE)				\
-  gen_rtx (REG, MODE,					\
-	   (GET_MODE_CLASS ((MODE)) == MODE_FLOAT	\
-	    ? 40 : 16))
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 40 || (N) == 16)
-
-/* 1 if N is a possible register number for function argument passing.
-   On the i860, these are r16-r27 and f8-f15.  */
-
-#define FUNCTION_ARG_REGNO_P(N)		\
-  (((N) < 28 && (N) > 15) || ((N) < 48 && (N) >= 40))
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the i860, we must count separately the number of general registers used
-   and the number of float registers used.  */
-
-struct cumulative_args { int ints, floats; };
-#define CUMULATIVE_ARGS struct cumulative_args
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the i860, the general-reg offset normally starts at 0,
-   but starts at 4 bytes
-   when the function gets a structure-value-address as an
-   invisible first argument.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM).ints = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE ((FNTYPE))) \
-		? 4 : 0),			\
-  (CUM).floats = 0)
-
-/* Machine-specific subroutines of the following macros.  */
-#define CEILING(X,Y)  (((X) + (Y) - 1) / (Y))
-#define ROUNDUP(X,Y)  (CEILING ((X), (Y)) * (Y))
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)
-   Floats, and doubleword ints, are returned in f regs;
-   other ints, in r regs.
-   Aggregates, even short ones, are passed in memory.  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)		\
- ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE		\
-		  || TREE_CODE ((TYPE)) == UNION_TYPE)		\
-  ? 0								\
-  : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode	\
-  ? ((CUM).floats = (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE)))	\
-		     + ROUNDUP (GET_MODE_SIZE (MODE), 4)))	\
-  : GET_MODE_CLASS ((MODE)) == MODE_INT				\
-  ? ((CUM).ints = (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) \
-		   + ROUNDUP (GET_MODE_SIZE (MODE), 4)))	\
-  : 0)
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On the i860, the first 12 words of integer arguments go in r16-r27,
-   and the first 8 words of floating arguments go in f8-f15.
-   DImode values are treated as floats.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)		\
- ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE	\
-		  || TREE_CODE ((TYPE)) == UNION_TYPE)	\
-  ? 0							\
-  : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode	\
-  ? (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) < 32	\
-     ? gen_rtx (REG, (MODE),				\
-		40+(ROUNDUP ((CUM).floats,		\
-			     GET_MODE_SIZE ((MODE)))	\
-		    / 4))				\
-     : 0)						\
-  : GET_MODE_CLASS ((MODE)) == MODE_INT			\
-  ? (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) < 48	\
-     ? gen_rtx (REG, (MODE),				\
-		16+(ROUNDUP ((CUM).ints,		\
-			     GET_MODE_SIZE ((MODE)))	\
-		    / 4))				\
-     : 0)						\
-  : 0)
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
-/* If defined, a C expression that gives the alignment boundary, in
-   bits, of an argument with the specified mode and type.  If it is
-   not defined,  `PARM_BOUNDARY' is used for all arguments.  */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE)			\
-  (((TYPE) != 0)						\
-   ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY)			\
-      ? PARM_BOUNDARY						\
-      : TYPE_ALIGN(TYPE))					\
-   : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY)		\
-      ? PARM_BOUNDARY						\
-      : GET_MODE_ALIGNMENT(MODE)))
-
-/* This macro generates the assembly code for function entry.
-
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-*/
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue ((FILE), (SIZE))
-
-/* Output a no-op just before the beginning of the function,
-   to ensure that there does not appear to be a delayed branch there.
-   Such a thing would confuse interrupt recovery.  */
-#define ASM_OUTPUT_FUNCTION_PREFIX(FILE,NAME) \
-  fprintf (FILE, "\tnop\n")
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   abort ();
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* This macro generates the assembly code for function exit.
-
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.
-*/
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue ((FILE), (SIZE))
-
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved.
-
-   On the i860, FRAME_POINTER_REQUIRED is always 1, so the definition of this
-   macro doesn't matter.  But it must be defined.  */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
-  do { (DEPTH) = 0; } while (0)
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  */
-
-/* On the i860, the trampoline contains five instructions:
-     orh #TOP_OF_FUNCTION,r0,r31
-     or #BOTTOM_OF_FUNCTION,r31,r31
-     orh #TOP_OF_STATIC,r0,r29
-     bri r31
-     or #BOTTOM_OF_STATIC,r29,r29  */
-#define TRAMPOLINE_TEMPLATE(FILE)					\
-{									\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0xec1f0000));	\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0xe7ff0000));	\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0xec1d0000));	\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0x4000f800));	\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0xe7bd0000));	\
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 20
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.
-
-   Store hi function at +0, low function at +4,
-   hi static at +8, low static at +16  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  rtx cxt = force_reg (Pmode, CXT);					\
-  rtx fn = force_reg (Pmode, FNADDR);					\
-  rtx hi_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt,			\
-			     size_int (16), 0, 0);			\
-  rtx hi_fn = expand_shift (RSHIFT_EXPR, SImode, fn,			\
-			    size_int (16), 0, 0);			\
-  emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 16)),	\
-		  gen_lowpart (HImode, cxt));				\
-  emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 4)),	\
-		  gen_lowpart (HImode, fn));				\
-  emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 8)),	\
-		  gen_lowpart (HImode, hi_cxt));			\
-  emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 0)),	\
-		  gen_lowpart (HImode, hi_fn));				\
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
-#define REGNO_OK_FOR_FP_P(REGNO) \
-(((REGNO) ^ 0x20) < 32 || (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32)
-
-/* Now macros that check whether X is a register and also,
-   strictly, whether it is in a specified class.
-
-   These macros are specific to the i860, and may be used only
-   in code for printing assembler insns and in conditions for
-   define_optimization.  */
-
-/* 1 if X is an fp register.  */
-
-#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
-
-   On the Sparc, this is anything but a CONST_DOUBLE.
-   Let's try permitting CONST_DOUBLEs and see what happens.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   On the i860, the actual addresses must be REG+REG or REG+SMALLINT.
-   But we can treat a SYMBOL_REF as legitimate if it is part of this
-   function's constant-pool, because such addresses can actually
-   be output as REG+SMALLINT.
-
-   The displacement in an address must be a multiple of the alignment.
-
-   Try making SYMBOL_REF (and other things which are CONSTANT_ADDRESS_P)
-   a legitimate address, regardless.  Because the only insns which can use
-   memory are load or store insns, the added hair in the machine description
-   is not that bad.  It should also speed up the compiler by halving the number
-   of insns it must manage for each (MEM (SYMBOL_REF ...)) involved.  */
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)		\
-{ if (GET_CODE (X) == REG)				\
-    { if (REG_OK_FOR_BASE_P (X)) goto ADDR; }		\
-  else if (GET_CODE (X) == PLUS)			\
-    {							\
-      if (GET_CODE (XEXP (X, 0)) == REG			\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 0)))		\
-	{						\
-	  if (GET_CODE (XEXP (X, 1)) == CONST_INT	\
-	      && INTVAL (XEXP (X, 1)) >= -0x8000	\
-	      && INTVAL (XEXP (X, 1)) < 0x8000		\
-	      && (INTVAL (XEXP (X, 1)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \
-	    goto ADDR;					\
-	}						\
-      else if (GET_CODE (XEXP (X, 1)) == REG		\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 1)))		\
-	{						\
-	  if (GET_CODE (XEXP (X, 0)) == CONST_INT	\
-	      && INTVAL (XEXP (X, 0)) >= -0x8000	\
-	      && INTVAL (XEXP (X, 0)) < 0x8000		\
-	      && (INTVAL (XEXP (X, 0)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \
-	    goto ADDR;					\
-	}						\
-    }							\
-  else if (CONSTANT_ADDRESS_P (X))			\
-    goto ADDR;						\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.  */
-
-/* On the i860, change COMPLICATED + CONSTANT to REG+CONSTANT.
-   Also change a symbolic constant to a REG,
-   though that may not be necessary.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)	\
-{ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT)	\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 1),			\
-		   force_operand (XEXP (X, 0), 0));		\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT)	\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 0),			\
-		   force_operand (XEXP (X, 1), 0));		\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS)	\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 1),			\
-		   force_operand (XEXP (X, 0), 0));		\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS)	\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 0),			\
-		   force_operand (XEXP (X, 1), 0));		\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) != REG	\
-      && GET_CODE (XEXP (X, 0)) != CONST_INT)			\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 1),			\
-		   copy_to_mode_reg (SImode, XEXP (X, 0)));	\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) != REG	\
-      && GET_CODE (XEXP (X, 1)) != CONST_INT)			\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 0),			\
-		   copy_to_mode_reg (SImode, XEXP (X, 1)));	\
-  if (GET_CODE (x) == SYMBOL_REF)				\
-    (X) = copy_to_reg (X);					\
-  if (GET_CODE (x) == CONST)					\
-    (X) = copy_to_reg (X);					\
-  if (memory_address_p (MODE, X))				\
-    goto WIN; }
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the i860 this is never true.
-   There are some addresses that are invalid in wide modes
-   but valid for narrower modes, but they shouldn't affect
-   the places that use this macro.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Must pass floats to libgcc functions as doubles.  */
-#define LIBGCC_NEEDS_DOUBLE 1
-
-#define DIVSI3_LIBCALL "*.div"
-#define UDIVSI3_LIBCALL "*.udiv"
-#define REMSI3_LIBCALL "*.rem"
-#define UREMSI3_LIBCALL "*.urem"
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 16
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 0
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Value is 1 if it generates better code to perform an unsigned comparison
-   on the given literal integer value in the given mode when we are only
-   looking for an equal/non-equal result.  */
-/* For the i860, if the immediate value has its high-order 27 bits zero,
-   then we want to engineer an unsigned comparison for EQ/NE because
-   such values can fit in the 5-bit immediate field of a bte or btne
-   instruction (which gets zero extended before comparing).  For all
-   other immediate values on the i860, we will use signed compares
-   because that avoids the need for doing explicit xor's to zero_extend
-   the non-constant operand in cases where it was (mem:QI ...) or a
-   (mem:HI ...) which always gets automatically sign-extended by the
-   hardware upon loading.  */
-
-#define LITERAL_COMPARE_BETTER_UNSIGNED(intval, mode)                   \
-  (((unsigned) (intval) & 0x1f) == (unsigned) (intval))
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE SImode
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.  */
-#define NO_FUNCTION_CSE
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE, OUTER_CODE)			\
-  case CONST_INT:						\
-    if (INTVAL (RTX) == 0)					\
-      return 0;							\
-    if (INTVAL (RTX) < 0x2000 && INTVAL (RTX) >= -0x2000) return 1; \
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 4;							\
-  case CONST_DOUBLE:						\
-    return 6;
-
-/* Specify the cost of a branch insn; roughly the number of extra insns that
-   should be added to avoid a branch.
-
-   Set this to 3 on the i860 since branches may often take three cycles.  */
-
-#define BRANCH_COST 3
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  */
-
-/* This holds the value sourcing h%r31.  We keep this info
-   around so that mem/mem ops, such as increment and decrement,
-   etc, can be performed reasonably.  */
-#define CC_STATUS_MDEP rtx
-
-#define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
-
-#define CC_NEGATED	01000
-
-/* We use this macro in those places in the i860.md file where we would
-   normally just do a CC_STATUS_INIT (for other machines).  This macro
-   differs from CC_STATUS_INIT in that it doesn't mess with the special
-   bits or fields which describe what is currently in the special r31
-   scratch register, but it does clear out everything that actually
-   relates to the condition code bit of the i860.  */
-
-#define CC_STATUS_PARTIAL_INIT						\
- (cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ),			\
-  cc_status.value1 = 0,							\
-  cc_status.value2 = 0)
-
-/* Nonzero if we know the value of h%r31.  */
-#define CC_KNOW_HI_R31 0100000
-
-/* Nonzero if h%r31 is actually ha%something, rather than h%something.  */
-#define CC_HI_R31_ADJ 0200000
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-/* On the i860, only compare insns set a useful condition code.  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-{ cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ);	\
-  cc_status.value1 = 0; cc_status.value2 = 0; }
-
-/* Control the assembler format that we output.  */
-
-/* Assembler pseudos to introduce constants of various size.  */
-
-#define ASM_BYTE_OP "\t.byte"
-#define ASM_SHORT "\t.short"
-#define ASM_LONG "\t.long"
-#define ASM_DOUBLE "\t.double"
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-
-#define ASM_FILE_START(FILE)
-#if 0
-#define ASM_FILE_START(FILE)					\
-  do { output_file_directive ((FILE), main_input_filename);	\
-       if (optimize) ASM_FILE_START_1 (FILE);			\
-     } while (0)
-#endif
-
-#define ASM_FILE_START_1(FILE)
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", "r8", "r9",		\
- "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",	\
- "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",	\
- "r30", "r31",								\
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",		\
- "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",	\
- "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",	\
- "f30", "f31" }
-
-/* How to renumber registers for dbx and gdb.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)					\
-  do { fputs (".globl ", FILE);					\
-	assemble_name (FILE, NAME);					\
-	fputs ("\n", FILE);						\
-  } while (0)
-
-/* The prefix to add to user-visible assembler symbols.
-
-   This definition is overridden in i860v4.h because under System V
-   Release 4, user-level symbols are *not* prefixed with underscores in
-   the generated assembly code.  */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-/* This is how to output an internal numbered label which
-   labels a jump table.  */
-
-#undef ASM_OUTPUT_CASE_LABEL
-#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE)		\
-do { ASM_OUTPUT_ALIGN ((FILE), 2);					\
-     ASM_OUTPUT_INTERNAL_LABEL ((FILE), PREFIX, NUM);			\
-   } while (0)
-
-/* Output at the end of a jump table.  */
-
-#define ASM_OUTPUT_CASE_END(FILE,NUM,INSN)	\
-  fprintf (FILE, ".text\n")
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*.%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-  fprintf (FILE, "\t.double %.20e\n", (VALUE))
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-  fprintf (FILE, "\t.float %.12e\n", (VALUE))
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.short "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* This is how to output code to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)					\
-  fprintf (FILE, "\taddu -16,%ssp,%ssp\n\t%sst.l %s%s,0(%ssp)\n",	\
-	i860_reg_prefix, i860_reg_prefix,				\
-	((REGNO) < 32 ? "" : "f"),					\
-	i860_reg_prefix, reg_names[REGNO],				\
-	i860_reg_prefix)
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)					\
-  fprintf (FILE, "\t%sld.l 0(%ssp),%s%s\n\taddu 16,%ssp,%ssp\n",	\
-	((REGNO) < 32 ? "" : "f"),					\
-	i860_reg_prefix,						\
-	i860_reg_prefix, reg_names[REGNO],				\
-	i860_reg_prefix, i860_reg_prefix)
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.long .L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.
-   (The i860 does not use such vectors,
-   but we must define this macro anyway.)  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", 1 << (LOG))
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.blkb %u\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.
-
-   In the following comments, the term "constant address" is used frequently.
-   For an exact definition of what constitutes a "constant address" see the
-   output_addr_const routine in final.c
-
-   On the i860, the following target-specific special codes are recognized:
-
-	`r'	The operand can be anything, but if it is an immediate zero
-		value (either integer or floating point) then it will be
-		represented as `r0' or as `f0' (respectively).
-
-	`m'	The operand is a memory ref (to a constant address) but print
-		its address as a constant.
-
-	`L'	The operand is a numeric constant, a constant address, or
-		a memory ref to a constant address.  Print the correct
-		notation to yield the low part of the given value or
-		address or the low part of the address of the referred
-		to memory object.
-
-	`H'	The operand is a numeric constant, a constant address, or
-		a memory ref to a constant address.  Print the correct
-		notation to yield the high part of the given value or
-		address or the high part of the address of the referred
-		to memory object.
-
-	`h'	The operand is a numeric constant, a constant address, or
-		a memory ref to a constant address.  Either print the
-		correct notation to yield the plain high part of the
-		given value or address (or the plain high part of the
-		address of the memory object) or else print the correct
-		notation to yield the "adjusted" high part of the given
-		address (or of the address of the referred to memory object).
-
-		The choice of what to print depends upon whether the address
-		in question is relocatable or not.  If it is relocatable,
-		print the notation to get the adjusted high part.  Otherwise
-		just print the notation to get the plain high part.  Note
-		that "adjusted" high parts are generally used *only* when
-		the next following instruction uses the low part of the
-		address as an offset, as in `offset(reg)'.
-
-	`R'	The operand is a floating-pointer register.  Print the
-		name of the next following (32-bit) floating-point register.
-		(This is used when moving a value into just the most
-		significant part of a floating-point register pair.)
-
-	`?'	(takes no operand) Substitute the value of i860_reg_prefix
-		at this point.  The value of i860_reg_prefix is typically
-		a null string for most i860 targets, but for System V
-		Release 4 the i860 assembler syntax requires that all
-		names of registers be prefixed with a percent-sign, so
-		for SVR4, the value of i860_reg_prefix is initialized to
-		"%" in i860.c.
-*/
-
-extern char *i860_reg_prefix;
-extern unsigned long sfmode_constant_to_ulong ();
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '?')
-
-/* The following macro definition is overridden in i860v4.h
-   because the svr4 i860 assembler required a different syntax
-   for getting parts of constant/relocatable values.  */
-
-#define PRINT_OPERAND_PART(FILE, X, PART_CODE)				\
-  do { fprintf (FILE, "%s%%", PART_CODE);				\
-	output_address (X);						\
-  } while (0)
-
-#define OPERAND_LOW_PART	"l"
-#define OPERAND_HIGH_PART	"h"
-/* NOTE: All documentation available for the i860 sez that you must
-   use "ha" to get the relocated high part of a relocatable, but
-   reality sez different.  */
-#define OPERAND_HIGH_ADJ_PART	"ha"
-
-#define PRINT_OPERAND(FILE, X, CODE)					\
-{ if ((CODE) == '?')							\
-    fprintf (FILE, "%s", i860_reg_prefix);				\
-  else if (CODE == 'R')							\
-    fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X) + 1]);	\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X)]);	\
-  else if ((CODE) == 'm')						\
-    output_address (XEXP (X, 0));					\
-  else if ((CODE) == 'L')						\
-    {									\
-      if (GET_CODE (X) == MEM)						\
-	PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_LOW_PART);	\
-      else								\
-	PRINT_OPERAND_PART (FILE, X, OPERAND_LOW_PART);			\
-    }									\
-  else if ((CODE) == 'H')						\
-    {									\
-      if (GET_CODE (X) == MEM)						\
-	PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_PART);	\
-      else								\
-	PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_PART);		\
-    }									\
-  else if ((CODE) == 'h')						\
-    {									\
-      if (GET_CODE (X) == MEM)						\
-	PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_ADJ_PART);	\
-      else								\
-	PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_ADJ_PART);		\
-    }									\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else if ((CODE) == 'r' && (X) == const0_rtx)				\
-    fprintf (FILE, "%sr0", i860_reg_prefix);				\
-  else if ((CODE) == 'r' && (X) == CONST0_RTX (GET_MODE (X)))		\
-    fprintf (FILE, "%sf0", i860_reg_prefix);				\
-  else if (GET_CODE (X) == CONST_DOUBLE)				\
-    fprintf (FILE, "0x%x", sfmode_constant_to_ulong (X));		\
-  else									\
-    output_addr_const (FILE, X); }
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx base, index = 0;					\
-  int offset = 0;						\
-  register rtx addr = ADDR;					\
-  if (GET_CODE (addr) == REG)					\
-    {								\
-      fprintf (FILE, "0(%s%s)",					\
-	i860_reg_prefix, reg_names[REGNO (addr)]);		\
-    }								\
-  else if (GET_CODE (addr) == CONST_DOUBLE			\
-            && GET_MODE (addr) == SFmode)			\
-    fprintf (FILE, "0x%x", sfmode_constant_to_ulong (addr));	\
-  else if (GET_CODE (addr) == PLUS)				\
-    {								\
-      if ((GET_CODE (XEXP (addr, 0)) == CONST_INT)		\
-	  && (GET_CODE (XEXP (addr, 1)) == REG))		\
-	fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 0)),	\
-	    i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\
-      else if ((GET_CODE (XEXP (addr, 1)) == CONST_INT)		\
-	  && (GET_CODE (XEXP (addr, 0)) == REG))		\
-	fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 1)),	\
-	    i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))]);\
-      else if ((GET_CODE (XEXP (addr, 0)) == REG)		\
-	  && (GET_CODE (XEXP (addr, 1)) == REG))		\
-	fprintf (FILE, "%s%s(%s%s)",				\
-	    i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))],	\
-	    i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\
-      else							\
-	output_addr_const (FILE, addr);				\
-    }								\
-  else								\
-    {								\
-      output_addr_const (FILE, addr);				\
-    }								\
-}
-
-/* The following #defines are used when compiling the routines in
-   libgcc1.c.  Since the i860 calling conventions require single
-   precision floats to be passed in the floating-point registers
-   (rather than in the general registers) we have to build the
-   libgcc1.c routines in such a way that they know the actual types
-   of their formal arguments and the actual types of their return
-   values.  Otherwise, gcc will generate calls to the libgcc1.c
-   routines, passing arguments in the floating-point registers,
-   but the libgcc1.c routines will expect their arguments on the
-   stack (where the i860 calling conventions require structs &
-   unions to be passed).  */
-
-#define FLOAT_VALUE_TYPE	float
-#define INTIFY(FLOATVAL)	(FLOATVAL)
-#define FLOATIFY(INTVAL)	(INTVAL)
-#define FLOAT_ARG_TYPE		float
-
-
-/* Optionally define this if you have added predicates to
-   `MACHINE.c'.  This macro is called within an initializer of an
-   array of structures.  The first field in the structure is the
-   name of a predicate and the second field is an array of rtl
-   codes.  For each predicate, list all rtl codes that can be in
-   expressions matched by the predicate.  The list should have a
-   trailing comma.  Here is an example of two entries in the list
-   for a typical RISC machine:
-
-   #define PREDICATE_CODES \
-     {"gen_reg_rtx_operand", {SUBREG, REG}},  \
-     {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
-
-   Defining this macro does not affect the generated code (however,
-   incorrect definitions that omit an rtl code that may be matched
-   by the predicate can cause the compiler to malfunction). 
-   Instead, it allows the table built by `genrecog' to be more
-   compact and efficient, thus speeding up the compiler.  The most
-   important predicates to include in the list specified by this
-   macro are thoses used in the most insn patterns.  */
-
-#define PREDICATE_CODES							\
-   {"reg_or_0_operand",		{REG, SUBREG, CONST_INT}},		\
-   {"arith_operand",		{REG, SUBREG, CONST_INT}},		\
-   {"logic_operand",		{REG, SUBREG, CONST_INT}},		\
-   {"shift_operand",		{REG, SUBREG, CONST_INT}},		\
-   {"compare_operand",		{REG, SUBREG, CONST_INT}},		\
-   {"arith_const_operand",	{CONST_INT}},				\
-   {"logic_const_operand",	{CONST_INT}},				\
-   {"bte_operand",		{REG, SUBREG, CONST_INT}},		\
-   {"indexed_operand",		{MEM}},					\
-   {"load_operand",		{MEM}},					\
-   {"small_int",		{CONST_INT}},				\
-   {"logic_int",		{CONST_INT}},				\
-   {"call_insn_operand",	{MEM}},
-
-/* Define the information needed to generate branch insns.  This is stored
-   from the compare operation.  Note that we can't use "rtx" here since it
-   hasn't been defined!  */
-
-extern struct rtx_def *i860_compare_op0, *i860_compare_op1;
-
-/* Declare things which are defined in i860.c but called from
-   insn-output.c.  */
-
-extern unsigned long sfmode_constant_to_ulong ();
-extern char *output_load ();
-extern char *output_store ();
-extern char *output_move_double ();
-extern char *output_fp_move_double ();
-extern char *output_block_move ();
-extern char *output_delay_insn ();
-extern char *output_delayed_branch ();
-extern void output_load_address ();
diff --git a/gcc/config/i860/i860.md b/gcc/config/i860/i860.md
deleted file mode 100755
index 48e0c35..0000000
--- a/gcc/config/i860/i860.md
+++ /dev/null
@@ -1,2310 +0,0 @@
-;;- Machine description for Intel 860 chip for GNU C compiler
-;;   Copyright (C) 1989, 1990, 1997 Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-;;- Operand classes for the register allocator:
-
-/* Bit-test instructions.  */
-
-(define_insn ""
-  [(set (cc0) (eq (and:SI (match_operand:SI 0 "register_operand" "r")
-			  (match_operand:SI 1 "logic_operand" "rL"))
-		  (const_int 0)))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"and %1,%0,%?r0\";
-}")
-
-(define_insn ""
-  [(set (cc0) (ne (and:SI (match_operand:SI 0 "register_operand" "r")
-			  (match_operand:SI 1 "logic_operand" "rL"))
-		  (const_int 0)))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  cc_status.flags |= CC_NEGATED;
-  return \"and %1,%0,%?r0\";
-}")
-
-(define_insn ""
-  [(set (cc0) (eq (and:SI (match_operand:SI 0 "register_operand" "r")
-			  (match_operand:SI 1 "immediate_operand" "i"))
-		  (const_int 0)))]
-  "GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) & 0xffff) == 0"
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"andh %H1,%0,%?r0\";
-}")
-
-(define_insn ""
-  [(set (cc0) (ne (and:SI (match_operand:SI 0 "register_operand" "r")
-			  (match_operand:SI 1 "immediate_operand" "i"))
-		  (const_int 0)))]
-  "GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) & 0xffff) == 0"
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  cc_status.flags |= CC_NEGATED;
-  return \"andh %H1,%0,%?r0\";
-}")
-
-(define_insn ""
-  [(set (cc0) (eq (ashiftrt:SI
-		   (sign_extend:SI
-		    (ashift:QI (match_operand:QI 0 "register_operand" "r")
-			       (match_operand:QI 1 "logic_int" "n")))
-		   (match_operand:SI 2 "logic_int" "n"))
-		  (const_int 0)))]
-  ""
-  "*
-{
-  int width = 8 - INTVAL (operands[2]);
-  int pos = 8 - width - INTVAL (operands[1]);
-
-  CC_STATUS_PARTIAL_INIT;
-  operands[2] = GEN_INT (~((-1) << width) << pos);
-  return \"and %2,%0,%?r0\";
-}")
-
-;; -------------------------------------------------------------------------
-;; SImode signed integer comparisons
-;; -------------------------------------------------------------------------
-
-(define_insn "cmpeqsi"
-  [(set (cc0) (eq (match_operand:SI 0 "logic_operand" "r,rL")
-		  (match_operand:SI 1 "logic_operand" "L,r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  if (REG_P (operands[0]))
-    return \"xor %1,%0,%?r0\";
-  else
-    return \"xor %0,%1,%?r0\";
-}")
-
-(define_insn "cmpnesi"
-  [(set (cc0) (ne (match_operand:SI 0 "logic_operand" "r,rL")
-		  (match_operand:SI 1 "logic_operand" "L,r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  cc_status.flags |= CC_NEGATED;
-  if (REG_P (operands[0]))
-    return \"xor %1,%0,%?r0\";
-  else
-    return \"xor %0,%1,%?r0\";
-}")
-
-(define_insn "cmpltsi"
-  [(set (cc0) (lt (match_operand:SI 0 "arith_operand" "r,rI")
-		  (match_operand:SI 1 "arith_operand" "I,r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  if (REG_P (operands[1]))
-    return \"subs %0,%1,%?r0\";
-  else
-    {
-      cc_status.flags |= CC_REVERSED;
-      operands[1] = GEN_INT (- INTVAL (operands[1]));
-      return \"adds %1,%0,%?r0\";
-    }
-}")
-
-(define_insn "cmpgtsi"
-  [(set (cc0) (gt (match_operand:SI 0 "arith_operand" "r,rI")
-		  (match_operand:SI 1 "arith_operand" "I,r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  if (REG_P (operands[0]))
-    return \"subs %1,%0,%?r0\";
-  else
-    {
-      cc_status.flags |= CC_REVERSED;
-      operands[0] = GEN_INT (- INTVAL (operands[0]));
-      return \"adds %0,%1,%?r0\";
-    }
-}")
-
-(define_insn "cmplesi"
-  [(set (cc0) (le (match_operand:SI 0 "arith_operand" "r,rI")
-		  (match_operand:SI 1 "arith_operand" "I,r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  cc_status.flags |= CC_NEGATED;
-  if (REG_P (operands[0]))
-    return \"subs %1,%0,%?r0\";
-  else
-    {
-      cc_status.flags |= CC_REVERSED;
-      operands[0] = GEN_INT (- INTVAL (operands[0]));
-      return \"adds %0,%1,%?r0\";
-    }
-}")
-
-(define_insn "cmpgesi"
-  [(set (cc0) (ge (match_operand:SI 0 "arith_operand" "r,rI")
-		  (match_operand:SI 1 "arith_operand" "I,r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  cc_status.flags |= CC_NEGATED;
-  if (REG_P (operands[1]))
-    return \"subs %0,%1,%?r0\";
-  else
-    {
-      cc_status.flags |= CC_REVERSED;
-      operands[1] = GEN_INT (- INTVAL (operands[1]));
-      return \"adds %1,%0,%?r0\";
-    }
-}")
-
-;; -------------------------------------------------------------------------
-;; SImode unsigned integer comparisons
-;; -------------------------------------------------------------------------
-
-;; WARNING!  There is a small i860 hardware limitation (bug?) which we
-;; may run up against (if we are not careful) when we are trying to do
-;; unsigned comparisons like (x >= 0), (x < 0), (0 <= x), and (0 > x).
-;; Specifically, we must avoid using an `addu' instruction to perform
-;; such comparisons because the result (in the CC bit register) will
-;; come out wrong.  (This fact is documented in a footnote on page 7-10
-;; of the 1991 version of the i860 Microprocessor Family Programmer's
-;; Reference Manual).  Note that unsigned comparisons of this sort are
-;; always redundant anyway, because an unsigned quantity can never be
-;; less than zero.  When we see cases like this, we generate an
-;; `or K,%r0,%r0' instruction instead (where K is a constant 0 or -1)
-;; so as to get the CC bit register set properly for any subsequent
-;; conditional jump instruction.
-
-(define_insn "cmpgeusi"
-  [(set (cc0) (geu (match_operand:SI 0 "arith_operand" "r,rI")
-		   (match_operand:SI 1 "arith_operand" "I,r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  if (REG_P (operands[1]))
-    return \"subu %0,%1,%?r0\";
-  else
-    {
-      if (INTVAL (operands[1]) == 0)
-	return \"or 0,%?r0,%?r0\";
-      else
-	{
-	  cc_status.flags |= CC_REVERSED;
-	  operands[1] = GEN_INT (- INTVAL (operands[1]));
-	  return \"addu %1,%0,%?r0\";
-	}
-    }
-}")
-
-(define_insn "cmpleusi"
-  [(set (cc0) (leu (match_operand:SI 0 "arith_operand" "r,rI")
-		   (match_operand:SI 1 "arith_operand" "I,r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  if (REG_P (operands[0]))
-    return \"subu %1,%0,%?r0\";
-  else
-    {
-      if (INTVAL (operands[0]) == 0)
-	return \"or 0,%?r0,%?r0\";
-      else
-	{
-	  cc_status.flags |= CC_REVERSED;
-	  operands[0] = GEN_INT (- INTVAL (operands[0]));
-	  return \"addu %0,%1,%?r0\";
-	}
-    }
-}")
-
-;; -------------------------------------------------------------------------
-;; SFmode floating-point comparisons
-;; -------------------------------------------------------------------------
-
-(define_insn "cmpeqsf"
-  [(set (cc0) (eq (match_operand:SF 0 "reg_or_0_operand" "fG")
-		  (match_operand:SF 1 "reg_or_0_operand" "fG")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"pfeq.ss %r0,%r1,%?f0\";
-}")
-
-(define_insn "cmpnesf"
-  [(set (cc0) (ne (match_operand:SF 0 "reg_or_0_operand" "fG")
-		  (match_operand:SF 1 "reg_or_0_operand" "fG")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  cc_status.flags |= CC_NEGATED;
-  return \"pfeq.ss %r1,%r0,%?f0\";
-}")
-
-;; NOTE:  The i860 Programmer's Reference Manual says that when we are
-;; doing (A < B) or (A > B) comparisons, we have to use pfgt for these
-;; in order to be IEEE compliant (in case a trap occurs during these
-;; operations).  Conversely, for (A <= B) or (A >= B) comparisons, we
-;; must use pfle to be IEEE compliant.
-
-(define_insn "cmpltsf"
-  [(set (cc0) (lt (match_operand:SF 0 "reg_or_0_operand" "fG")
-		  (match_operand:SF 1 "reg_or_0_operand" "fG")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"pfgt.ss %r1,%r0,%?f0\";
-}")
-
-(define_insn "cmpgtsf"
-  [(set (cc0) (gt (match_operand:SF 0 "reg_or_0_operand" "fG")
-		  (match_operand:SF 1 "reg_or_0_operand" "fG")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"pfgt.ss %r0,%r1,%?f0\";
-}")
-
-;; NOTE:  The pfle opcode doesn't do what you think it does.  It is
-;; bass-ackwards.  It *clears* the CC flag if the first operand is
-;; less than or equal to the second.  Thus, we have to set CC_NEGATED
-;; for the following two patterns.
-
-(define_insn "cmplesf"
-  [(set (cc0) (le (match_operand:SF 0 "reg_or_0_operand" "fG")
-		  (match_operand:SF 1 "reg_or_0_operand" "fG")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  cc_status.flags |= CC_NEGATED;
-  return \"pfle.ss %r0,%r1,%?f0\";
-}")
-
-(define_insn "cmpgesf"
-  [(set (cc0) (ge (match_operand:SF 0 "reg_or_0_operand" "fG")
-		  (match_operand:SF 1 "reg_or_0_operand" "fG")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  cc_status.flags |= CC_NEGATED;
-  return \"pfle.ss %r1,%r0,%?f0\";
-}")
-
-;; -------------------------------------------------------------------------
-;; DFmode floating-point comparisons
-;; -------------------------------------------------------------------------
-
-(define_insn "cmpeqdf"
-  [(set (cc0) (eq (match_operand:DF 0 "reg_or_0_operand" "fG")
-		  (match_operand:DF 1 "reg_or_0_operand" "fG")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"pfeq.dd %r0,%r1,%?f0\";
-}")
-
-(define_insn "cmpnedf"
-  [(set (cc0) (ne (match_operand:DF 0 "reg_or_0_operand" "fG")
-		  (match_operand:DF 1 "reg_or_0_operand" "fG")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  cc_status.flags |= CC_NEGATED;
-  return \"pfeq.dd %r1,%r0,%?f0\";
-}")
-
-;; NOTE:  The i860 Programmer's Reference Manual says that when we are
-;; doing (A < B) or (A > B) comparisons, we have to use pfgt for these
-;; in order to be IEEE compliant (in case a trap occurs during these
-;; operations).  Conversely, for (A <= B) or (A >= B) comparisons, we
-;; must use pfle to be IEEE compliant.
-
-(define_insn "cmpltdf"
-  [(set (cc0) (lt (match_operand:DF 0 "reg_or_0_operand" "fG")
-		  (match_operand:DF 1 "reg_or_0_operand" "fG")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"pfgt.dd %r1,%r0,%?f0\";
-}")
-
-(define_insn "cmpgtdf"
-  [(set (cc0) (gt (match_operand:DF 0 "reg_or_0_operand" "fG")
-		  (match_operand:DF 1 "reg_or_0_operand" "fG")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"pfgt.dd %r0,%r1,%?f0\";
-}")
-
-;; NOTE:  The pfle opcode doesn't do what you think it does.  It is
-;; bass-ackwards.  It *clears* the CC flag if the first operand is
-;; less than or equal to the second.  Thus, we have to set CC_NEGATED
-;; for the following two patterns.
-
-(define_insn "cmpledf"
-  [(set (cc0) (le (match_operand:DF 0 "reg_or_0_operand" "fG")
-		  (match_operand:DF 1 "reg_or_0_operand" "fG")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  cc_status.flags |= CC_NEGATED;
-  return \"pfle.dd %r0,%r1,%?f0\";
-}")
-
-(define_insn "cmpgedf"
-  [(set (cc0) (ge (match_operand:DF 0 "reg_or_0_operand" "fG")
-		  (match_operand:DF 1 "reg_or_0_operand" "fG")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  cc_status.flags |= CC_NEGATED;
-  return \"pfle.dd %r1,%r0,%?f0\";
-}")
-
-;; ------------------------------------------------------------------------
-;; Integer EQ/NE comparisons against constant values which will fit in the
-;; 16-bit immediate field of an instruction.  These are made by combining.
-;; ------------------------------------------------------------------------
-
-(define_insn ""
-  [(set (cc0) (eq (zero_extend:SI (match_operand:HI 0 "load_operand" "m"))
-	          (match_operand:SI 1 "small_int" "I")))]
-  "INTVAL (operands[1]) >= 0"
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"ld.s %0,%?r31\;xor %1,%?r31,%?r0\";
-}")
-
-(define_insn ""
-  [(set (cc0) (eq (match_operand:SI 0 "small_int" "I")
-	          (zero_extend:SI (match_operand:HI 1 "load_operand" "m"))))]
-  "INTVAL (operands[0]) >= 0"
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"ld.s %1,%?r31\;xor %0,%?r31,%?r0\";
-}")
-
-;; ------------------------------------------------------------------------
-;; Define the real conditional branch instructions.
-;; ------------------------------------------------------------------------
-
-(define_insn "cbranch"
-  [(set (pc) (if_then_else (eq (cc0) (const_int 0))
-			   (label_ref (match_operand 0 "" ""))
-			   (pc)))]
-  ""
-  "*
-{
-  if ((cc_prev_status.flags & CC_NEGATED) == 0)
-    return \"bnc %l0\";
-  else
-    return \"bc %l0\";
-}")
-
-(define_insn "flipped_cbranch"
-  [(set (pc) (if_then_else (ne (cc0)
-			       (const_int 0))
-			   (pc)
-			   (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  if ((cc_prev_status.flags & CC_NEGATED) == 0)
-    return \"bnc %l0\";
-  else
-    return \"bc %l0\";
-}")
-
-(define_insn "inverse_cbranch"
-  [(set (pc) (if_then_else (eq (cc0)
-			       (const_int 0))
-			   (pc)
-			   (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  if ((cc_prev_status.flags & CC_NEGATED) == 0)
-    return \"bc %l0\";
-  else
-    return \"bnc %l0\";
-}")
-
-
-(define_insn "flipped_inverse_cbranch"
-  [(set (pc) (if_then_else (ne (cc0)
-			       (const_int 0))
-			   (label_ref (match_operand 0 "" ""))
-			   (pc)))]
-  ""
-  "*
-{
-  if ((cc_prev_status.flags & CC_NEGATED) == 0)
-    return \"bc %l0\";
-  else
-    return \"bnc %l0\";
-}")
-
-;; Simple BTE/BTNE compare-and-branch insns made by combining.
-;; Note that it is wrong to add similar patterns for QI or HImode
-;; because bte/btne always compare the whole register.
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (eq (match_operand:SI 0 "register_operand" "r")
-			  (match_operand:SI 1 "bte_operand" "rK"))
-		      (label_ref (match_operand 2 "" ""))
-		      (pc)))]
-  ""
-  "bte %1,%0,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ne (match_operand:SI 0 "register_operand" "r")
-			  (match_operand:SI 1 "bte_operand" "rK"))
-		      (label_ref (match_operand 2 "" ""))
-		      (pc)))]
-  ""
-  "btne %1,%0,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (eq (match_operand:SI 0 "register_operand" "r")
-			  (match_operand:SI 1 "bte_operand" "rK"))
-		      (pc)
-		      (label_ref (match_operand 2 "" ""))))]
-  ""
-  "btne %1,%0,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ne (match_operand:SI 0 "register_operand" "r")
-			  (match_operand:SI 1 "bte_operand" "rK"))
-		      (pc)
-		      (label_ref (match_operand 2 "" ""))))]
-  ""
-  "bte %1,%0,%2")
-
-;; Load byte/halfword, zero-extend, & compare-and-branch insns.
-;; These are made by combining.
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (eq (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
-                          (match_operand:SI 1 "bte_operand" "K"))
-                      (label_ref (match_operand 2 "" ""))
-                      (pc)))
-   (match_scratch:SI 3 "=r")]
-  ""
-  "ld.b %0,%3;bte %1,%3,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ne (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
-                          (match_operand:SI 1 "bte_operand" "K"))
-                      (label_ref (match_operand 2 "" ""))
-                      (pc)))
-   (match_scratch:SI 3 "=r")]
-  ""
-  "ld.b %0,%3;btne %1,%3,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (eq (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
-                          (match_operand:SI 1 "bte_operand" "K"))
-                      (pc)
-                      (label_ref (match_operand 2 "" ""))))
-   (match_scratch:SI 3 "=r")]
-  ""
-  "ld.b %0,%3;btne %1,%3,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ne (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
-                          (match_operand:SI 1 "bte_operand" "K"))
-                      (pc)
-                      (label_ref (match_operand 2 "" ""))))
-   (match_scratch:SI 3 "=r")]
-  ""
-  "ld.b %0,%3;bte %1,%3,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (eq (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
-                          (match_operand:SI 1 "bte_operand" "K"))
-                      (label_ref (match_operand 2 "" ""))
-                      (pc)))
-   (match_scratch:SI 3 "=r")]
-  ""
-  "ld.s %0,%3;bte %1,%3,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ne (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
-                          (match_operand:SI 1 "bte_operand" "K"))
-                      (label_ref (match_operand 2 "" ""))
-                      (pc)))
-   (match_scratch:SI 3 "=r")]
-  ""
-  "ld.s %0,%3;btne %1,%3,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (eq (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
-                          (match_operand:SI 1 "bte_operand" "K"))
-                      (pc)
-                      (label_ref (match_operand 2 "" ""))))
-   (match_scratch:SI 3 "=r")]
-  ""
-  "ld.s %0,%3;btne %1,%3,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ne (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
-                          (match_operand:SI 1 "bte_operand" "K"))
-                      (pc)
-                      (label_ref (match_operand 2 "" ""))))
-   (match_scratch:SI 3 "=r")]
-  ""
-  "ld.s %0,%3;bte %1,%3,%2")
-
-
-;; Generation of conditionals.
-
-;; We save the compare operands in the cmpxx patterns and use then when
-;; we generate the branch.
-
-(define_expand "cmpsi"
-  [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
-		       (match_operand:SI 1 "compare_operand" "")))]
-  ""
-  "
-{ i860_compare_op0 = operands[0];
-  i860_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "cmpsf"
-  [(set (cc0) (compare (match_operand:SF 0 "register_operand" "")
-		       (match_operand:SF 1 "register_operand" "")))]
-  ""
-  "
-{ i860_compare_op0 = operands[0];
-  i860_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "cmpdf"
-  [(set (cc0) (compare (match_operand:DF 0 "register_operand" "")
-		       (match_operand:DF 1 "register_operand" "")))]
-  ""
-  "
-{ i860_compare_op0 = operands[0];
-  i860_compare_op1 = operands[1];
-  DONE;
-}")
-
-;; These are the standard-named conditional branch patterns.
-;; Detailed comments are found in the first one only.
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  /* Emit a single-condition compare insn according to
-     the type of operands and the condition to be tested.  */
-
-  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
-    emit_insn (gen_cmpeqsi (i860_compare_op0, i860_compare_op1));
-  else if (GET_MODE (i860_compare_op0) == SFmode)
-    emit_insn (gen_cmpeqsf (i860_compare_op0, i860_compare_op1));
-  else if (GET_MODE (i860_compare_op0) == DFmode)
-    emit_insn (gen_cmpeqdf (i860_compare_op0, i860_compare_op1));
-  else
-    abort ();
-
-  /* Emit branch-if-true.  */
-
-  emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
-  DONE;
-}")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
-    emit_insn (gen_cmpeqsi (i860_compare_op0, i860_compare_op1));
-  else if (GET_MODE (i860_compare_op0) == SFmode)
-    emit_insn (gen_cmpeqsf (i860_compare_op0, i860_compare_op1));
-  else if (GET_MODE (i860_compare_op0) == DFmode)
-    emit_insn (gen_cmpeqdf (i860_compare_op0, i860_compare_op1));
-  else
-    abort ();
-
-  emit_jump_insn (gen_flipped_cbranch (operands[0]));
-
-  DONE;
-}")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
-    emit_insn (gen_cmpgtsi (i860_compare_op0, i860_compare_op1));
-  else if (GET_MODE (i860_compare_op0) == SFmode)
-    emit_insn (gen_cmpgtsf (i860_compare_op0, i860_compare_op1));
-  else if (GET_MODE (i860_compare_op0) == DFmode)
-    emit_insn (gen_cmpgtdf (i860_compare_op0, i860_compare_op1));
-  else
-    abort ();
-
-  emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
-  DONE;
-}")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
-    emit_insn (gen_cmpltsi (i860_compare_op0, i860_compare_op1));
-  else if (GET_MODE (i860_compare_op0) == SFmode)
-    emit_insn (gen_cmpltsf (i860_compare_op0, i860_compare_op1));
-  else if (GET_MODE (i860_compare_op0) == DFmode)
-    emit_insn (gen_cmpltdf (i860_compare_op0, i860_compare_op1));
-  else
-    abort ();
-
-  emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
-  DONE;
-}")
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
-    {
-      emit_insn (gen_cmpgtsi (i860_compare_op0, i860_compare_op1));
-      emit_jump_insn (gen_flipped_cbranch (operands[0]));
-    }
-  else
-    {
-      if (GET_MODE (i860_compare_op0) == SFmode)
-	emit_insn (gen_cmplesf (i860_compare_op0, i860_compare_op1));
-      else if (GET_MODE (i860_compare_op0) == DFmode)
-	emit_insn (gen_cmpledf (i860_compare_op0, i860_compare_op1));
-      else
-	abort ();
-      emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
-    }
-  DONE;
-}")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
-    {
-      emit_insn (gen_cmpltsi (i860_compare_op0, i860_compare_op1));
-      emit_jump_insn (gen_flipped_cbranch (operands[0]));
-    }
-  else
-    {
-      if (GET_MODE (i860_compare_op0) == SFmode)
-	emit_insn (gen_cmpgesf (i860_compare_op0, i860_compare_op1));
-      else if (GET_MODE (i860_compare_op0) == DFmode)
-	emit_insn (gen_cmpgedf (i860_compare_op0, i860_compare_op1));
-      else
-	abort ();
-      emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
-    }
-  DONE;
-}")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT)
-    abort ();
-
-  emit_insn (gen_cmpleusi (i860_compare_op0, i860_compare_op1));
-  emit_jump_insn (gen_flipped_cbranch (operands[0]));
-  DONE;
-}")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT)
-    abort ();
-
-  emit_insn (gen_cmpgeusi (i860_compare_op0, i860_compare_op1));
-  emit_jump_insn (gen_flipped_cbranch (operands[0]));
-  DONE;
-}")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT)
-    abort ();
-
-  emit_insn (gen_cmpgeusi (i860_compare_op0, i860_compare_op1));
-  emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
-  DONE;
-}")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT)
-    abort ();
-
-  emit_insn (gen_cmpleusi (i860_compare_op0, i860_compare_op1));
-  emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
-  DONE;
-}")
-
-;; Move instructions
-
-;; Note that source operands for `mov' pseudo-instructions are no longer
-;; allowed (by the svr4 assembler) to be "big" things, i.e. constants that
-;; won't fit in 16-bits.  (This includes any sort of a relocatable address
-;; also.)  Thus, we must use an explicit orh/or pair of instructions if
-;; the source operand is something "big".
-
-(define_insn "movsi"
-  [(set (match_operand:SI 0 "general_operand" "=r,m,f")
-	(match_operand:SI 1 "general_operand" "rmif,rfJ,rmfJ"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-	return output_store (operands);
-      if (FP_REG_P (operands[1]))
-	return \"fst.l %1,%0\";
-      return \"st.l %r1,%0\";
-    }
-  if (GET_CODE (operands[1]) == MEM)
-    {
-      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-	return output_load (operands);
-      if (FP_REG_P (operands[0]))
-	return \"fld.l %1,%0\";
-      return \"ld.l %1,%0\";
-    }
-  if (FP_REG_P (operands[1]) && FP_REG_P (operands[0]))
-    return \"fmov.ss %1,%0\";
-  if (FP_REG_P (operands[1]))
-    return \"fxfr %1,%0\";
-  if (FP_REG_P (operands[0]) && operands[1] == const0_rtx)
-    return \"fmov.ss %?f0,%0\";
-  if (FP_REG_P (operands[0]))
-    return \"ixfr %1,%0\";
-
-  if (GET_CODE (operands[1]) == REG)
-    return \"shl %?r0,%1,%0\";
-
-  CC_STATUS_PARTIAL_INIT;
-
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      if((INTVAL (operands[1]) & 0xffff0000) == 0)
-        return \"or %L1,%?r0,%0\";
-      if((INTVAL (operands[1]) & 0x0000ffff) == 0)
-        return \"orh %H1,%?r0,%0\";
-    }
-  return \"orh %H1,%?r0,%0\;or %L1,%0,%0\";
-}")
- 
-(define_insn "movhi"
-  [(set (match_operand:HI 0 "general_operand" "=r,m,!*f,!r")
-	(match_operand:HI 1 "general_operand" "rmi,rJ,rJ*f,*f"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-	return output_store (operands);
-      return \"st.s %r1,%0\";
-    }
-  if (GET_CODE (operands[1]) == MEM)
-    {
-      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-	return output_load (operands);
-      return \"ld.s %1,%0\";
-    }
-  if (FP_REG_P (operands[1]) && FP_REG_P (operands[0]))
-    return \"fmov.ss %1,%0\";
-  if (FP_REG_P (operands[1]))
-    return \"fxfr %1,%0\";
-  if (FP_REG_P (operands[0]) && operands[1] == const0_rtx)
-    return \"fmov.ss %?f0,%0\";
-  if (FP_REG_P (operands[0]))
-    return \"ixfr %1,%0\";
-
-  if (GET_CODE (operands[1]) == REG)
-    return \"shl %?r0,%1,%0\";
-
-  CC_STATUS_PARTIAL_INIT;
-
-  return \"or %L1,%?r0,%0\";
-}")
-
-(define_insn "movqi"
-  [(set (match_operand:QI 0 "general_operand" "=r,m,!*f,!r")
-	(match_operand:QI 1 "general_operand" "rmi,rJ,rJ*f,*f"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-	return output_store (operands);
-      return \"st.b %r1,%0\";
-    }
-  if (GET_CODE (operands[1]) == MEM)
-    {
-      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-	return output_load (operands);
-      return \"ld.b %1,%0\";
-    }
-  if (FP_REG_P (operands[1]) && FP_REG_P (operands[0]))
-    return \"fmov.ss %1,%0\";
-  if (FP_REG_P (operands[1]))
-    return \"fxfr %1,%0\";
-  if (FP_REG_P (operands[0]) && operands[1] == const0_rtx)
-    return \"fmov.ss %?f0,%0\";
-  if (FP_REG_P (operands[0]))
-    return \"ixfr %1,%0\";
-
-  if (GET_CODE (operands[1]) == REG)
-    return \"shl %?r0,%1,%0\";
-
-  CC_STATUS_PARTIAL_INIT;
-
-  return \"or %L1,%?r0,%0\";
-}")
-
-;; The definition of this insn does not really explain what it does,
-;; but it should suffice
-;; that anything generated as this insn will be recognized as one
-;; and that it won't successfully combine with anything.
-(define_expand "movstrsi"
-  [(parallel [(set (match_operand:BLK 0 "general_operand" "")
-		   (match_operand:BLK 1 "general_operand" ""))
-	      (use (match_operand:SI 2 "nonmemory_operand" ""))
-	      (use (match_operand:SI 3 "immediate_operand" ""))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))
-	      (clobber (match_dup 7))
-	      (clobber (match_dup 8))])]
-  ""
-  "
-{
-  operands[4] = gen_reg_rtx (SImode);
-  operands[5] = gen_reg_rtx (SImode);
-  operands[6] = gen_reg_rtx (SImode);
-  operands[7] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
-  operands[8] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
-
-  operands[0] = change_address (operands[0], VOIDmode, operands[7]);
-  operands[1] = change_address (operands[1], VOIDmode, operands[8]);
-}")
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "r")))
-   (use (match_operand:SI 2 "general_operand" "rn"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "register_operand" "=r"))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))
-   (clobber (match_operand:SI 6 "register_operand" "=r"))
-   (clobber (match_dup 0))
-   (clobber (match_dup 1))]
-  ""
-  "* return output_block_move (operands);")
-
-;; Floating point move insns
-
-;; This pattern forces (set (reg:DF ...) (const_double ...))
-;; to be reloaded by putting the constant into memory.
-;; It must come before the more general movdf pattern.
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=r,f,o")
-	(match_operand:DF 1 "" "mG,m,G"))]
-  "GET_CODE (operands[1]) == CONST_DOUBLE"
-  "*
-{
-  if (FP_REG_P (operands[0]) || operands[1] == CONST0_RTX (DFmode))
-    return output_fp_move_double (operands);
-  return output_move_double (operands);
-}")
-
-(define_insn "movdf"
-  [(set (match_operand:DF 0 "general_operand" "=*rm,*r,?f,?*rm")
-	(match_operand:DF 1 "general_operand" "*r,m,*rfmG,f"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM
-      && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-    return output_store (operands);
-  if (GET_CODE (operands[1]) == MEM
-      && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-    return output_load (operands);
-
-  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
-    return output_fp_move_double (operands);
-  return output_move_double (operands);
-}")
-
-(define_insn "movdi"
-  [(set (match_operand:DI 0 "general_operand" "=rm,r,?f,?rm")
-	(match_operand:DI 1 "general_operand" "r,miF,rfmG,f"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM
-      && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-    return output_store (operands);
-  if (GET_CODE (operands[1]) == MEM
-      && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-    return output_load (operands);
-
-  /* ??? How can we have a DFmode arg here with DImode above? */
-  if (FP_REG_P (operands[0]) && operands[1] == CONST0_RTX (DFmode))
-    return \"fmov.dd %?f0,%0\";
-
-  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
-    return output_fp_move_double (operands);
-  return output_move_double (operands);
-}")
-
-;; The alternative m/r is separate from m/f
-;; The first alternative is separate from the second for the same reason.
-(define_insn "movsf"
-  [(set (match_operand:SF 0 "general_operand" "=*rf,*rf,*r,m,m")
-	(match_operand:SF 1 "general_operand" "*r,fmG,F,*r,f"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM
-      && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-    return output_store (operands);
-  if (GET_CODE (operands[1]) == MEM
-      && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-    return output_load (operands);
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"fmov.ss %1,%0\";
-      if (GET_CODE (operands[1]) == REG)
-	return \"ixfr %1,%0\";
-      if (operands[1] == CONST0_RTX (SFmode))
-        return \"fmov.ss %?f0,%0\";
-      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-	{
-	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-		 && (cc_prev_status.flags & CC_HI_R31_ADJ)
-		 && cc_prev_status.mdep == XEXP(operands[1],0)))
-	    {
-	      CC_STATUS_INIT;
-	      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-	      cc_status.mdep = XEXP (operands[1], 0);
-	      return \"orh %h1,%?r0,%?r31\;fld.l %L1(%?r31),%0\";
-	    }
-	  return \"fld.l %L1(%?r31),%0\";
-	}
-      return \"fld.l %1,%0\";
-    }
-  if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
-    {
-      if (GET_CODE (operands[0]) == REG && FP_REG_P (operands[1]))
-	return \"fxfr %1,%0\";
-      if (GET_CODE (operands[0]) == REG)
-	{
-	  CC_STATUS_PARTIAL_INIT;
-	  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	    {
-	      register unsigned long ul;
-
-              ul = sfmode_constant_to_ulong (operands[1]);
-	      if ((ul & 0x0000ffff) == 0)
-		return \"orh %H1,%?r0,%0\";
-	      if ((ul & 0xffff0000) == 0)
-		return \"or %L1,%?r0,%0\";
-	    }
-          return \"orh %H1,%?r0,%0\;or %L1,%0,%0\";
-	}
-      /* Now operand 0 must be memory.
-         If operand 1 is CONST_DOUBLE, its value must be 0.  */
-      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-	{
-	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-		 && (cc_prev_status.flags & CC_HI_R31_ADJ)
-		 && XEXP (operands[0], 0) == cc_prev_status.mdep))
-	    {
-	      CC_STATUS_INIT;
-	      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-	      cc_status.mdep = XEXP (operands[0], 0);
-	      output_asm_insn (\"orh %h0,%?r0,%?r31\", operands);
-	    }
-	  return \"fst.l %r1,%L0(%?r31)\";
-	}
-      return \"fst.l %r1,%0\";
-    }
-  if (GET_CODE (operands[0]) == MEM)
-    return \"st.l %r1,%0\";
-  if (GET_CODE (operands[1]) == MEM)
-    return \"ld.l %1,%0\";
-  if (operands[1] == CONST0_RTX (SFmode))
-    return \"shl %?r0,%?r0,%0\";
-  return \"mov %1,%0\";
-}")
-
-;; Special load insns for REG+REG addresses.
-;; Such addresses are not "legitimate" because st rejects them.
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=rf")
-	(match_operand:DF 1 "indexed_operand" "m"))]
-  ""
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    return output_fp_move_double (operands);
-  return output_move_double (operands);
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=rf")
-	(match_operand:SF 1 "indexed_operand" "m"))]
-  ""
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    return \"fld.l %1,%0\";
-  return \"ld.l %1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=rf")
-	(match_operand:SI 1 "indexed_operand" "m"))]
-  ""
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    return \"fld.l %1,%0\";
-  return \"ld.l %1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(match_operand:HI 1 "indexed_operand" "m"))]
-  ""
-  "ld.s %1,%0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(match_operand:QI 1 "indexed_operand" "m"))]
-  ""
-  "ld.b %1,%0")
-
-;; Likewise for floating-point store insns.
-
-(define_insn ""
-  [(set (match_operand:DF 0 "indexed_operand" "=m")
-	(match_operand:DF 1 "register_operand" "f"))]
-  ""
-  "fst.d %1,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "indexed_operand" "=m")
-	(match_operand:SF 1 "register_operand" "f"))]
-  ""
-  "fst.l %1,%0")
-
-;;- truncation instructions
-(define_insn "truncsiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(truncate:QI
-	 (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM)
-    if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-      {
-	if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-	       && (cc_prev_status.flags & CC_HI_R31_ADJ)
-	       && XEXP (operands[0], 0) == cc_prev_status.mdep))
-	  {
-	    CC_STATUS_INIT;
-	    cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-	    cc_status.mdep = XEXP (operands[0], 0);
-	    output_asm_insn (\"orh %h0,%?r0,%?r31\", operands);
-	  }
-	return \"st.b %1,%L0(%?r31)\";
-      }
-    else
-      return \"st.b %1,%0\";
-  return \"shl %?r0,%1,%0\";
-}")
-
-(define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(truncate:QI
-	 (match_operand:HI 1 "register_operand" "r")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM)
-    if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-      {
-	if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-	       && (cc_prev_status.flags & CC_HI_R31_ADJ)
-	       && XEXP (operands[0], 0) == cc_prev_status.mdep))
-	  {
-	    CC_STATUS_INIT;
-	    cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-	    cc_status.mdep = XEXP (operands[0], 0);
-	    output_asm_insn (\"orh %h0,%?r0,%?r31\", operands);
-	  }
-	return \"st.b %1,%L0(%?r31)\";
-      }
-    else
-      return \"st.b %1,%0\";
-  return \"shl %?r0,%1,%0\";
-}")
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(truncate:HI
-	 (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM)
-    if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
-      {
-	if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
-	       && (cc_prev_status.flags & CC_HI_R31_ADJ)
-	       && XEXP (operands[0], 0) == cc_prev_status.mdep))
-	  {
-	    CC_STATUS_INIT;
-	    cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-	    cc_status.mdep = XEXP (operands[0], 0);
-	    output_asm_insn (\"orh %h0,%?r0,%?r31\", operands);
-	  }
-	return \"st.s %1,%L0(%?r31)\";
-      }
-    else
-      return \"st.s %1,%0\";
-  return \"shl %?r0,%1,%0\";
-}")
-
-;;- zero extension instructions
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI
-	 (match_operand:HI 1 "register_operand" "r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"and 0xffff,%1,%0\";
-}")
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(zero_extend:HI
-	 (match_operand:QI 1 "register_operand" "r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"and 0xff,%1,%0\";
-}")
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI
-	 (match_operand:QI 1 "register_operand" "r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"and 0xff,%1,%0\";
-}")
-
-;; Sign extension instructions.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI
-	 (match_operand:HI 1 "indexed_operand" "m")))]
-  ""
-  "ld.s %1,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(sign_extend:HI
-	 (match_operand:QI 1 "indexed_operand" "m")))]
-  ""
-  "ld.b %1,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI
-	 (match_operand:QI 1 "indexed_operand" "m")))]
-  ""
-  "ld.b %1,%0")
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI
-	 (match_operand:HI 1 "nonimmediate_operand" "mr")))]
-  ""
-  "*
-{
-  if (REG_P (operands[1]))
-    return \"shl 16,%1,%0\;shra 16,%0,%0\";
-  if (GET_CODE (operands[1]) == CONST_INT)
-    abort ();
-  if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-    {
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-      cc_status.mdep = XEXP (operands[1], 0);
-      return \"orh %h1,%?r0,%?r31\;ld.s %L1(%?r31),%0\";
-    }
-  else
-    return \"ld.s %1,%0\";
-}")
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(sign_extend:HI
-	 (match_operand:QI 1 "nonimmediate_operand" "mr")))]
-  ""
-  "*
-{
-  if (REG_P (operands[1]))
-    return \"shl 24,%1,%0\;shra 24,%0,%0\";
-  if (GET_CODE (operands[1]) == CONST_INT)
-    abort ();
-  if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-    {
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-      cc_status.mdep = XEXP (operands[1], 0);
-      return \"orh %h1,%?r0,%?r31\;ld.b %L1(%?r31),%0\";
-    }
-  else
-    return \"ld.b %1,%0\";
-}")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI
-	 (match_operand:QI 1 "nonimmediate_operand" "mr")))]
-  ""
-  "*
-{
-  if (REG_P (operands[1]))
-    return \"shl 24,%1,%0\;shra 24,%0,%0\";
-  if (GET_CODE (operands[1]) == CONST_INT)
-    abort ();
-  if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-    {
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-      cc_status.mdep = XEXP (operands[1], 0);
-      return \"orh %h1,%?r0,%?r31\;ld.b %L1(%?r31),%0\";
-    }
-  else
-    return \"ld.b %1,%0\";
-}")
-
-;; Signed bitfield extractions come out looking like
-;;	(shiftrt (sign_extend (shift <Y> <C1>)) <C2>)
-;; which we expand poorly as four shift insns.
-;; These patterns yield two shifts:
-;;	(shiftrt (shift <Y> <C3>) <C4>)
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashiftrt:SI
-	 (sign_extend:SI
-	  (match_operand:QI 1 "register_operand" "r"))
-	 (match_operand:SI 2 "logic_int" "n")))]
-  "INTVAL (operands[2]) < 8"
-  "*
-{
-  return \"shl 24,%1,%0\;shra 24+%2,%0,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashiftrt:SI
-	 (sign_extend:SI
-	  (subreg:QI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-				(match_operand:SI 2 "logic_int" "n")) 0))
-	 (match_operand:SI 3 "logic_int" "n")))]
-  "INTVAL (operands[3]) < 8"
-  "*
-{
-  return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashiftrt:SI
-	 (sign_extend:SI
-	  (ashift:QI (match_operand:QI 1 "register_operand" "r")
-		     (match_operand:QI 2 "logic_int" "n")))
-	 (match_operand:SI 3 "logic_int" "n")))]
-  "INTVAL (operands[3]) < 8"
-  "*
-{
-  return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\";
-}")
-
-;; Special patterns for optimizing bit-field instructions.
-
-;; First two patterns are for bitfields that came from memory
-;; testing only the high bit.  They work with old combiner.
-
-(define_insn ""
-  [(set (cc0)
-	(eq (zero_extend:SI (subreg:QI (lshiftrt:SI (match_operand:SI 0 "register_operand" "r")
-						    (const_int 7)) 0))
-	    (const_int 0)))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"and 128,%0,%?r0\";
-}")
-
-(define_insn ""
-  [(set (cc0)
-	(eq (sign_extend:SI (subreg:QI (ashiftrt:SI (match_operand:SI 0 "register_operand" "r")
-						    (const_int 7)) 0))
-	    (const_int 0)))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"and 128,%0,%?r0\";
-}")
-
-;; next two patterns are good for bitfields coming from memory
-;; (via pseudo-register) or from a register, though this optimization
-;; is only good for values contained wholly within the bottom 13 bits
-(define_insn ""
-  [(set (cc0)
-	(eq 
-	 (and:SI (lshiftrt:SI (match_operand:SI 0 "register_operand" "r")
-			      (match_operand:SI 1 "logic_int" "n"))
-		 (match_operand:SI 2 "logic_int" "n"))
-	 (const_int 0)))]
-  "LOGIC_INTVAL (INTVAL (operands[2]) << INTVAL (operands[1]))"
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  operands[2] = GEN_INT ((INTVAL (operands[2]) << INTVAL (operands[1])));
-  return \"and %2,%0,%?r0\";
-}")
-
-(define_insn ""
-  [(set (cc0)
-	(eq 
-	 (and:SI (ashiftrt:SI (match_operand:SI 0 "register_operand" "r")
-			      (match_operand:SI 1 "logic_int" "n"))
-		 (match_operand:SI 2 "logic_int" "n"))
-	 (const_int 0)))]
-  "LOGIC_INTVAL (INTVAL (operands[2]) << INTVAL (operands[1]))"
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  operands[2] = GEN_INT ((INTVAL (operands[2]) << INTVAL (operands[1])));
-  return \"and %2,%0,%?r0\";
-}")
-
-;; Conversions between float and double.
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float_extend:DF
-	 (match_operand:SF 1 "register_operand" "f")))]
-  ""
-  "fmov.sd %1,%0")
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float_truncate:SF
-	 (match_operand:DF 1 "register_operand" "f")))]
-  ""
-  "fmov.ds %1,%0")
-
-;; Conversion between fixed point and floating point.
-;; Note that among the fix-to-float insns
-;; the ones that start with SImode come first.
-;; That is so that an operand that is a CONST_INT
-;; (and therefore lacks a specific machine mode).
-;; will be recognized as SImode (which is always valid)
-;; rather than as QImode or HImode.
-
-;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
-;; to be reloaded by putting the constant into memory.
-;; It must come before the more general floatsisf2 pattern.
-(define_expand "floatsidf2"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (xor:SI (match_operand:SI 1 "register_operand" "")
-			      (const_int -2147483648)))
-   (set (match_dup 5) (match_dup 3))
-   (set (subreg:SI (match_dup 5) 0) (match_dup 4))
-   (set (match_operand:DF 0 "register_operand" "")
-	(minus:DF (match_dup 5) (match_dup 2)))]
-  ""
-  "
-{
-  REAL_VALUE_TYPE d;
-  /* 4503601774854144 is  (1 << 30) * ((1 << 22) + (1 << 1)).  */
-  d = REAL_VALUE_ATOF (\"4503601774854144\", DFmode);
-  operands[2] = gen_reg_rtx (DFmode);
-  operands[3] = CONST_DOUBLE_FROM_REAL_VALUE (d, DFmode);
-  operands[4] = gen_reg_rtx (SImode);
-  operands[5] = gen_reg_rtx (DFmode);
-}")
-
-;; Floating to fixed conversion.
-
-(define_expand "fix_truncdfsi2"
-  ;; This first insn produces a double-word value
-  ;; in which only the low word is valid.
-  [(set (match_dup 2)
-	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
-   (set (match_operand:SI 0 "register_operand" "=f")
-	(subreg:SI (match_dup 2) 0))]
-  ""
-  "
-{
-  operands[2] = gen_reg_rtx (DImode);
-}")
-
-;; Recognize the first insn generated above.
-;; This RTL looks like a fix_truncdfdi2 insn,
-;; but we dont call it that, because only 32 bits
-;; of the result are valid.
-;; This pattern will work for the intended purposes 
-;; as long as we do not have any fixdfdi2 or fix_truncdfdi2.
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
-  ""
-  "ftrunc.dd %1,%0")
-
-(define_expand "fix_truncsfsi2"
-  ;; This first insn produces a double-word value
-  ;; in which only the low word is valid.
-  [(set (match_dup 2)
-	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))
-   (set (match_operand:SI 0 "register_operand" "=f")
-	(subreg:SI (match_dup 2) 0))]
-  ""
-  "
-{
-  operands[2] = gen_reg_rtx (DImode);
-}")
-
-;; Recognize the first insn generated above.
-;; This RTL looks like a fix_truncsfdi2 insn,
-;; but we dont call it that, because only 32 bits
-;; of the result are valid.
-;; This pattern will work for the intended purposes 
-;; as long as we do not have any fixsfdi2 or fix_truncsfdi2.
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=f")
-	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
-  ""
-  "ftrunc.sd %1,%0")
-
-;;- arithmetic instructions
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,*f")
-	(plus:SI (match_operand:SI 1 "nonmemory_operand" "%r,*f")
-		 (match_operand:SI 2 "arith_operand" "rI,*f")))]
-  ""
-  "*
-{
-  if (which_alternative == 1)
-    return \"fiadd.ss %2,%1,%0\";
-  CC_STATUS_PARTIAL_INIT;
-  return \"addu %2,%1,%0\";
-}")
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=f")
-	(plus:DI (match_operand:DI 1 "register_operand" "%f")
-		 (match_operand:DI 2 "register_operand" "f")))]
-  ""
-  "fiadd.dd %1,%2,%0")
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,*f")
-	(minus:SI (match_operand:SI 1 "register_operand" "r,I,*f")
-		  (match_operand:SI 2 "arith_operand" "rI,r,*f")))]
-  ""
-  "*
-{
-  if (which_alternative == 2)
-    return \"fisub.ss %1,%2,%0\";
-  CC_STATUS_PARTIAL_INIT;
-  if (REG_P (operands[2]))
-    return \"subu %1,%2,%0\";
-  operands[2] = GEN_INT (- INTVAL (operands[2]));
-  return \"addu %2,%1,%0\";
-}")
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=f")
-	(minus:DI (match_operand:DI 1 "register_operand" "f")
-		  (match_operand:DI 2 "register_operand" "f")))]
-  ""
-  "fisub.dd %1,%2,%0")
-
-(define_expand "mulsi3"
-  [(set (subreg:SI (match_dup 4) 0) (match_operand:SI 1 "general_operand" ""))
-   (set (subreg:SI (match_dup 5) 0) (match_operand:SI 2 "general_operand" ""))
-   (clobber (match_dup 3))
-   (set (subreg:SI (match_dup 3) 0)
-	(mult:SI (subreg:SI (match_dup 4) 0) (subreg:SI (match_dup 5) 0)))
-   (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))]
-  ""
-  "
-{
-  if (WORDS_BIG_ENDIAN)
-    emit_insn (gen_mulsi3_big (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_mulsi3_little (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_expand "mulsi3_little"
-  [(set (subreg:SI (match_dup 4) 0) (match_operand:SI 1 "general_operand" ""))
-   (set (subreg:SI (match_dup 5) 0) (match_operand:SI 2 "general_operand" ""))
-   (clobber (match_dup 3))
-   (set (subreg:SI (match_dup 3) 0)
-	(mult:SI (subreg:SI (match_dup 4) 0) (subreg:SI (match_dup 5) 0)))
-   (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))]
-  "! WORDS_BIG_ENDIAN"
-  "
-{
-  operands[3] = gen_reg_rtx (DImode);
-  operands[4] = gen_reg_rtx (DImode);
-  operands[5] = gen_reg_rtx (DImode);
-}")
-
-(define_expand "mulsi3_big"
-  [(set (subreg:SI (match_dup 4) 1) (match_operand:SI 1 "general_operand" ""))
-   (set (subreg:SI (match_dup 5) 1) (match_operand:SI 2 "general_operand" ""))
-   (clobber (match_dup 3))
-   (set (subreg:SI (match_dup 3) 1)
-	(mult:SI (subreg:SI (match_dup 4) 1) (subreg:SI (match_dup 5) 1)))
-   (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 1))]
-  "WORDS_BIG_ENDIAN"
-  "
-{
-  operands[3] = gen_reg_rtx (DImode);
-  operands[4] = gen_reg_rtx (DImode);
-  operands[5] = gen_reg_rtx (DImode);
-}")
-
-(define_insn ""
-  [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 0)
-	(mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 0)
-		 (subreg:SI (match_operand:DI 2 "register_operand" "f") 0)))]
-  "! WORDS_BIG_ENDIAN"
-  "fmlow.dd %2,%1,%0")
-
-(define_insn ""
-  [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 1)
-	(mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 1)
-		 (subreg:SI (match_operand:DI 2 "register_operand" "f") 1)))]
-  "WORDS_BIG_ENDIAN"
-  "fmlow.dd %2,%1,%0")
-
-;;- and instructions (with compliment also)			   
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (match_operand:SI 1 "nonmemory_operand" "%r")
-		(match_operand:SI 2 "nonmemory_operand" "rL")))]
-  ""
-  "*
-{
-  rtx xop[3];
-
-  CC_STATUS_PARTIAL_INIT;
-  if (REG_P (operands[2]) || LOGIC_INT (operands[2]))
-    return \"and %2,%1,%0\";
-  if ((INTVAL (operands[2]) & 0xffff) == 0)
-    {
-      operands[2] = GEN_INT ((unsigned) INTVAL (operands[2]) >> 16);
-      return \"andh %2,%1,%0\";
-    }
-  xop[0] = operands[0];
-  xop[1] = operands[1];
-  xop[2] = GEN_INT (~INTVAL (operands[2]) & 0xffff);
-  output_asm_insn (\"andnot %2,%1,%0\", xop);
-  operands[2] = GEN_INT (~(unsigned) INTVAL (operands[2]) >> 16);
-  return \"andnoth %2,%0,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "register_operand" "rn"))
-		(match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "*
-{
-  rtx xop[3];
-
-  CC_STATUS_PARTIAL_INIT;
-  if (REG_P (operands[1]) || LOGIC_INT (operands[1]))
-    return \"andnot %1,%2,%0\";
-  if ((INTVAL (operands[1]) & 0xffff) == 0)
-    {
-      operands[1] = GEN_INT ((unsigned) INTVAL (operands[1]) >> 16);
-      return \"andnoth %1,%2,%0\";
-    }
-  xop[0] = operands[0];
-  xop[1] = GEN_INT ((INTVAL (operands[1]) & 0xffff));
-  xop[2] = operands[2];
-  output_asm_insn (\"andnot %1,%2,%0\", xop);
-  operands[1] = GEN_INT ((unsigned) INTVAL (operands[1]) >> 16);
-  return \"andnoth %1,%0,%0\";
-}")
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (match_operand:SI 1 "nonmemory_operand" "%r")
-		(match_operand:SI 2 "nonmemory_operand" "rL")))]
-  ""
-  "*
-{
-  rtx xop[3];
-
-  CC_STATUS_PARTIAL_INIT;
-  if (REG_P (operands[2]) || LOGIC_INT (operands[2]))
-    return \"or %2,%1,%0\";
-  if ((INTVAL (operands[2]) & 0xffff) == 0)
-    {
-      operands[2] = GEN_INT ((unsigned) INTVAL (operands[2]) >> 16);
-      return \"orh %2,%1,%0\";
-    }
-  xop[0] = operands[0];
-  xop[1] = operands[1];
-  xop[2] = GEN_INT ((INTVAL (operands[2]) & 0xffff));
-  output_asm_insn (\"or %2,%1,%0\", xop);
-  operands[2] = GEN_INT ((unsigned) INTVAL (operands[2]) >> 16);
-  return \"orh %2,%0,%0\";
-}")
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(xor:SI (match_operand:SI 1 "nonmemory_operand" "%r")
-		(match_operand:SI 2 "nonmemory_operand" "rL")))]
-  ""
-  "*
-{
-  rtx xop[3];
-
-  CC_STATUS_PARTIAL_INIT;
-  if (REG_P (operands[2]) || LOGIC_INT (operands[2]))
-    return \"xor %2,%1,%0\";
-  if ((INTVAL (operands[2]) & 0xffff) == 0)
-    {
-      operands[2] = GEN_INT ((unsigned) INTVAL (operands[2]) >> 16);
-      return \"xorh %2,%1,%0\";
-    }
-  xop[0] = operands[0];
-  xop[1] = operands[1];
-  xop[2] = GEN_INT ((INTVAL (operands[2]) & 0xffff));
-  output_asm_insn (\"xor %2,%1,%0\", xop);
-  operands[2] = GEN_INT ((unsigned) INTVAL (operands[2]) >> 16);
-  return \"xorh %2,%0,%0\";
-}")
-
-;(The i860 instruction set doesn't allow an immediate second operand in
-; a subtraction.)
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(neg:SI (match_operand:SI 1 "arith_operand" "r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"subu %?r0,%1,%0\";
-}")
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(not:SI (match_operand:SI 1 "arith_operand" "r")))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  return \"subu -1,%1,%0\";
-}")
-
-;; Floating point arithmetic instructions.
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (match_operand:DF 1 "register_operand" "f")
-		 (match_operand:DF 2 "register_operand" "f")))]
-  ""
-  "fadd.dd %1,%2,%0")
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))]
-  ""
-  "fadd.ss %1,%2,%0")
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 1 "register_operand" "f")
-		  (match_operand:DF 2 "register_operand" "f")))]
-  ""
-  "fsub.dd %1,%2,%0")
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (match_operand:SF 1 "register_operand" "f")
-		  (match_operand:SF 2 "register_operand" "f")))]
-  ""
-  "fsub.ss %1,%2,%0")
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mult:DF (match_operand:DF 1 "register_operand" "f")
-		 (match_operand:DF 2 "register_operand" "f")))]
-  ""
-  "fmul.dd %1,%2,%0")
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(mult:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))]
-  ""
-  "fmul.ss %1,%2,%0")
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (match_operand:DF 1 "register_operand" "f")))]
-  ""
-  "fsub.dd %?f0,%1,%0")
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (match_operand:SF 1 "register_operand" "f")))]
-  ""
-  "fsub.ss %?f0,%1,%0")
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=&f")
-	(div:DF (match_operand:DF 1 "register_operand" "f")
-		 (match_operand:DF 2 "register_operand" "f")))
-   (clobber (match_scratch:DF 3 "=&f"))
-   (clobber (match_scratch:DF 4 "=&f"))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  if (((cc_prev_status.flags & CC_KNOW_HI_R31) == 0)
-      || (cc_prev_status.flags & CC_HI_R31_ADJ)
-      || (cc_prev_status.mdep != CONST2_RTX (SFmode)))
-    {
-      cc_status.flags |= CC_KNOW_HI_R31;
-      cc_status.flags &= ~CC_HI_R31_ADJ;
-      cc_status.mdep = CONST2_RTX (SFmode); 
-      return \"frcp.dd %2,%3\;fmul.dd %2,%3,%0\;fmov.dd %?f0,%4\;\\\
-orh 0x4000,%?r0,%?r31\;ixfr %?r31,%R4\;fsub.dd %4,%0,%0\;\\\
-fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\\
-fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\\
-fmul.dd %3,%1,%3\;fmul.dd %0,%3,%0\";
-    }
-  else
-    return \"frcp.dd %2,%3\;fmul.dd %2,%3,%0\;fmov.dd %?f0,%4\;\\\
-ixfr %?r31,%R4\;fsub.dd %4,%0,%0\;\\\
-fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\\
-fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\\
-fmul.dd %3,%1,%3\;fmul.dd %0,%3,%0\";
-}")
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=&f")
-	(div:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))
-   (clobber (match_scratch:SF 3 "=&f"))
-   (clobber (match_scratch:SF 4 "=&f"))]
-  ""
-  "*
-{
-  CC_STATUS_PARTIAL_INIT;
-  if (((cc_prev_status.flags & CC_KNOW_HI_R31) == 0)
-      || (cc_prev_status.flags & CC_HI_R31_ADJ)
-      || (cc_prev_status.mdep != CONST2_RTX (SFmode)))
-    {
-      cc_status.flags |= CC_KNOW_HI_R31;
-      cc_status.flags &= ~CC_HI_R31_ADJ;
-      cc_status.mdep = CONST2_RTX (SFmode);
-      output_asm_insn (\"orh 0x4000,%?r0,%?r31\", operands);
-    }
-  return \"ixfr %?r31,%4\;frcp.ss %2,%0\;\\\
-fmul.ss %2,%0,%3\;fsub.ss %4,%3,%3\;fmul.ss %0,%3,%0\;\\\
-fmul.ss %2,%0,%3\;fsub.ss %4,%3,%3\;\\\
-fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\";
-}")
-
-;; Shift instructions
-
-;; Optimized special case of shifting.
-;; Must precede the general case.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
-		     (const_int 24)))]
-  ""
-  "*
-{
-  if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
-    {
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
-      cc_status.mdep = XEXP (operands[1], 0);
-      return \"orh %h1,%?r0,%?r31\;ld.b %L1(%?r31),%0\";
-    }
-  return \"ld.b %1,%0\";
-}")
-
-
-;;- arithmetic shift instructions
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "r")
-		   (match_operand:SI 2 "shift_operand" "rn")))]
-  ""
-  "*
-{
-  return \"shl %2,%1,%0\";
-}")
-
-(define_insn "ashlhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(ashift:HI (match_operand:HI 1 "register_operand" "r")
-		   (match_operand:HI 2 "shift_operand" "rn")))]
-  ""
-  "*
-{
-  return \"shl %2,%1,%0\";
-}")
-
-(define_insn "ashlqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(ashift:QI (match_operand:QI 1 "register_operand" "r")
-		   (match_operand:QI 2 "shift_operand" "rn")))]
-  ""
-  "*
-{
-  return \"shl %2,%1,%0\";
-}")
-
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
-		     (match_operand:SI 2 "shift_operand" "rn")))]
-  ""
-  "*
-{
-  return \"shra %2,%1,%0\";
-}")
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
-		     (match_operand:SI 2 "shift_operand" "rn")))]
-  ""
-  "*
-{
-  return \"shr %2,%1,%0\";
-}")
-
-;; Unconditional and other jump instructions
-
-(define_insn "jump"
-  [(set (pc) (label_ref (match_operand 0 "" "")))]
-  ""
-  "*
-{
-  return \"br %l0\;nop\";
-}")
-
-;; Here are two simple peepholes which fill the delay slot of
-;; an unconditional branch.
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=rf")
-	(match_operand:SI 1 "single_insn_src_p" "gfG"))
-   (set (pc) (label_ref (match_operand 2 "" "")))]
-  ""
-  "* return output_delayed_branch (\"br %l2\", operands, insn);")
-
-(define_peephole
-  [(set (match_operand:SI 0 "memory_operand" "=m")
-	(match_operand:SI 1 "reg_or_0_operand" "rfJ"))
-   (set (pc) (label_ref (match_operand 2 "" "")))]
-  ""
-  "* return output_delayed_branch (\"br %l2\", operands, insn);")
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "bri %0\;nop")
-
-(define_peephole
-  [(set (match_operand:SI 0 "memory_operand" "=m")
-	(match_operand:SI 1 "reg_or_0_operand" "rfJ"))
-   (set (pc) (match_operand:SI 2 "register_operand" "r"))
-   (use (label_ref (match_operand 3 "" "")))]
-  ""
-  "* return output_delayed_branch (\"bri %2\", operands, insn);")
-
-;;- jump to subroutine
-(define_expand "call"
-  [(call (match_operand:SI 0 "memory_operand" "m")
-	 (match_operand 1 "" "i"))]
-  ;; operand[2] is next_arg_register
-  ""
-  "
-{
-  /* Make sure the address is just one reg and will stay that way.  */
-  if (! call_insn_operand (operands[0], QImode))
-    operands[0]
-      = change_address (operands[0], VOIDmode,
-			copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
-  if (INTVAL (operands[1]) > 0)
-    {
-      emit_move_insn (arg_pointer_rtx, stack_pointer_rtx);
-      emit_insn (gen_rtx (USE, VOIDmode, arg_pointer_rtx));
-    }
-}")
-
-;;- jump to subroutine
-(define_insn ""
-  [(call (match_operand:SI 0 "call_insn_operand" "m")
-	 (match_operand 1 "" "i"))]
-  ;; operand[2] is next_arg_register
-  ""
-  "*
-{
-  /* strip the MEM.  */
-  operands[0] = XEXP (operands[0], 0);
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[0]) == REG)
-    return \"calli %0\;nop\";
-  return \"call %0\;nop\";
-}")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=rf")
-	(match_operand:SI 1 "single_insn_src_p" "gfG"))
-   (call (match_operand:SI 2 "memory_operand" "m")
-	 (match_operand 3 "" "i"))]
-  ;;- Don't use operand 1 for most machines.
-  "! reg_mentioned_p (operands[0], operands[2])"
-  "*
-{
-  /* strip the MEM.  */
-  operands[2] = XEXP (operands[2], 0);
-  if (GET_CODE (operands[2]) == REG)
-    return output_delayed_branch (\"calli %2\", operands, insn);
-  return output_delayed_branch (\"call %2\", operands, insn);
-}")
-
-(define_peephole
-  [(set (match_operand:SI 0 "memory_operand" "=m")
-	(match_operand:SI 1 "reg_or_0_operand" "rfJ"))
-   (call (match_operand:SI 2 "call_insn_operand" "m")
-	 (match_operand 3 "" "i"))]
-  ;;- Don't use operand 1 for most machines.
-  ""
-  "*
-{
-  /* strip the MEM.  */
-  operands[2] = XEXP (operands[2], 0);
-  if (GET_CODE (operands[2]) == REG)
-    return output_delayed_branch (\"calli %2\", operands, insn);
-  return output_delayed_branch (\"call %2\", operands, insn);
-}")
-
-(define_expand "call_value"
-  [(set (match_operand 0 "register_operand" "=rf")
-	(call (match_operand:SI 1 "memory_operand" "m")
-	      (match_operand 2 "" "i")))]
-  ;; operand 3 is next_arg_register
-  ""
-  "
-{
-  /* Make sure the address is just one reg and will stay that way.  */
-  if (! call_insn_operand (operands[1], QImode))
-    operands[1]
-      = change_address (operands[1], VOIDmode,
-			copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
-  if (INTVAL (operands[2]) > 0)
-    {
-      emit_move_insn (arg_pointer_rtx, stack_pointer_rtx);
-      emit_insn (gen_rtx (USE, VOIDmode, arg_pointer_rtx));
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand 0 "register_operand" "=rf")
-	(call (match_operand:SI 1 "call_insn_operand" "m")
-	      (match_operand 2 "" "i")))]
-  ;; operand 3 is next_arg_register
-  ""
-  "*
-{
-  /* strip the MEM.  */
-  operands[1] = XEXP (operands[1], 0);
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[1]) == REG)
-    return \"calli %1\;nop\";
-  return \"call %1\;nop\";
-}")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=rf")
-	(match_operand:SI 1 "single_insn_src_p" "gfG"))
-   (set (match_operand 2 "" "=rf")
-	(call (match_operand:SI 3 "call_insn_operand" "m")
-	      (match_operand 4 "" "i")))]
-  ;;- Don't use operand 4 for most machines.
-  "! reg_mentioned_p (operands[0], operands[3])"
-  "*
-{
-  /* strip the MEM.  */
-  operands[3] = XEXP (operands[3], 0);
-  if (GET_CODE (operands[3]) == REG)
-    return output_delayed_branch (\"calli %3\", operands, insn);
-  return output_delayed_branch (\"call %3\", operands, insn);
-}")
-
-(define_peephole
-  [(set (match_operand:SI 0 "memory_operand" "=m")
-	(match_operand:SI 1 "reg_or_0_operand" "rJf"))
-   (set (match_operand 2 "" "=rf")
-	(call (match_operand:SI 3 "call_insn_operand" "m")
-	      (match_operand 4 "" "i")))]
-  ;;- Don't use operand 4 for most machines.
-  ""
-  "*
-{
-  /* strip the MEM.  */
-  operands[3] = XEXP (operands[3], 0);
-  if (GET_CODE (operands[3]) == REG)
-    return output_delayed_branch (\"calli %3\", operands, insn);
-  return output_delayed_branch (\"call %3\", operands, insn);
-}")
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
-  ""
-  "bri %0")
-
-;;
-;; A special insn that does the work to get setup just
-;; before a table jump.
-;;
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
-			 (label_ref (match_operand 2 "" "")))))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"orh %H2,%?r0,%?r31\;or %L2,%?r31,%?r31\;ld.l %?r31(%1),%0\";
-}")
-  
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=rf")
-	(match_operand:SI 1 "single_insn_src_p" "gfG"))
-   (set (pc) (match_operand:SI 2 "register_operand" "r"))
-   (use (label_ref (match_operand 3 "" "")))]
-  "REGNO (operands[0]) != REGNO (operands[2])"
-  "* return output_delayed_branch (\"bri %2\", operands, insn);")
diff --git a/gcc/config/i860/mach.h b/gcc/config/i860/mach.h
deleted file mode 100755
index a59cc58..0000000
--- a/gcc/config/i860/mach.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Configuration for an i860 running Mach as the target machine.  */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i860 Mach3.x)");
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Di860 -DMACH -Asystem(unix) -Asystem(mach) -Acpu(i860) -Amachine(i860)"
-
-/* Specify extra dir to search for include files.  */
-#define SYSTEM_INCLUDE_DIR "/usr/mach/include"
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
diff --git a/gcc/config/i860/paragon.h b/gcc/config/i860/paragon.h
deleted file mode 100755
index c6bfbba..0000000
--- a/gcc/config/i860/paragon.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/* Target definitions for GNU compiler for Intel 80860 running OSF/1AD
-   Copyright (C) 1991, 1996 Free Software Foundation, Inc.
-   Based upon original work of Ron Guilmette (rfg@monkeys.com).
-   Contributed by Andy Pfiffer (andyp@ssd.intel.com).
-   Partially inspired by
-	Pete Beckman of Indiana University (beckman@cs.indiana.edu)
-	Harry Dolan of Intel Corporation (dolan@ssd.intel.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* For the sake of libgcc2.c, indicate target supports atexit.  */
-#define HAVE_ATEXIT
-
-#undef TARGET_SWITCHES
-#define TARGET_SWITCHES  \
-  { {"xp", 1},                  \
-    {"noxp", -1},               \
-    {"xr", -1},                 \
-    {"noieee", -1},		\
-    {"nx", 2},                  \
-    { "", TARGET_DEFAULT}}
- 
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT 1
-
-/* The Intel as860 assembler does not understand .stabs, must use COFF */
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i860 OSF/1AD)");
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES	"-Di860 -D__i860 -D__i860__ -D__PARAGON__ -D__OSF1__ -D_COFF -Dunix -DMACH -DCMU"
-
-#define CPP_SPEC "%{mnx:-D__NODE}"
-
-/* autoinit.o autolaunches NX applications */
-#define STARTFILE_SPEC "crt0.o%s %{mnx:-yoptions/autoinit.o%s}"
-
-/* libic.a is the PGI intrinsic library */
-/* libpm.o and guard.o are for the performance monitoring modules (ignored) */
-/* /usr/lib/noieee contains non-IEEE compliant (but faster) math routines */
-#if	HAVE_DASH_G
-#define LIB_SPEC \
-"%{mnoieee:-L/usr/lib/noieee} %{mnx:-lnx} %{g*:-lg} -lc -lmach -lc -lic"
-#else	/* HAVE_DASH_G */
-/* can't use -g for -lg; libg.a doesn't have a symbol table and ld complains */
-#define LIB_SPEC "%{mnoieee:-L/usr/lib/noieee} %{mnx:-lnx} -lc -lmach -lc -lic"
-#endif	/* HAVE_DASH_G */
-
-/* Get rid of definition from svr3.h.  */
-#undef SIZE_TYPE
-
-#undef	I860_REG_PREFIX
-
-#undef	ASM_COMMENT_START
-#define ASM_COMMENT_START "//"
-
-#undef TYPE_OPERAND_FMT
-#define TYPE_OPERAND_FMT      "\"%s\""
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-#undef ASCII_DATA_ASM_OP
-#define ASCII_DATA_ASM_OP	".byte"
-
-/*
- *	the assembler we're using doesn't grok .ident...
- */
-#undef	ASM_OUTPUT_IDENT
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  fprintf (FILE, "//\t.ident \"%s\"\n", NAME);
-
-/*
- *	the assembler doesn't grok .double INF and the like
- *	but does understand .long with hex numbers, so special
- *	case the "symbolic" IEEE numbers.
- */
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)				\
-  {								\
-    if (REAL_VALUE_ISINF (VALUE)				\
-        || REAL_VALUE_ISNAN (VALUE)				\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))			\
-      {								\
-	long t[2];						\
-	REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);		\
-	fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", t[0], t[1]); \
-      }								\
-    else							\
-      fprintf (FILE, "\t.double %.20e\n", VALUE);		\
-  }
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)				\
-  {								\
-    if (REAL_VALUE_ISINF (VALUE)				\
-        || REAL_VALUE_ISNAN (VALUE)				\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))			\
-      {								\
-	long t;							\
-	REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);		\
-	fprintf (FILE, "\t.long 0x%lx\n", t);			\
-      }								\
-    else							\
-      fprintf (FILE, "\t.float %.12e\n", VALUE);		\
-  }
-
-#undef	ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH)			\
-  do								\
-    {								\
-      register unsigned char *str = (unsigned char *) (STR);	\
-      register unsigned char *limit = str + (LENGTH);		\
-      register unsigned bytes_in_chunk = 0;			\
-      for (; str < limit; str++)				\
-        {							\
-          register unsigned ch = *str;				\
-          if (ch < 32 || ch == '\\' || ch == '"' || ch >= 127)	\
-	    {							\
-	      if (bytes_in_chunk > 0)				\
-	        {						\
-	          fprintf ((FILE), "\"\n");			\
-	          bytes_in_chunk = 0;				\
-	        }						\
-	      fprintf ((FILE), "\t%s\t%d\n", ASM_BYTE_OP, ch);	\
-	    }							\
-          else							\
-	    {							\
-	      if (bytes_in_chunk >= 60)				\
-	        {						\
-	          fprintf ((FILE), "\"\n");			\
-	          bytes_in_chunk = 0;				\
-	        }						\
-	      if (bytes_in_chunk == 0)				\
-	        fprintf ((FILE), "\t%s\t\"", ASCII_DATA_ASM_OP);\
-	      putc (ch, (FILE));				\
-	      bytes_in_chunk++;					\
-	    }							\
-        }							\
-      if (bytes_in_chunk > 0)					\
-        fprintf ((FILE), "\"\n");				\
-    }								\
-  while (0)
-
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/*
- *	not defining ASM_STABS_OP yields .stabs in the .s file
- *	when using g++ -- so, I'll define it.
- */
-#define	ASM_STABS_OP	"//.stabs"
-
-/* Define this macro if an argument declared as `char' or `short' in a
-   prototype should actually be passed as an `int'.  In addition to
-   avoiding errors in certain cases of mismatch, it also makes for
-   better code on certain machines. */
-/*#define PROMOTE_PROTOTYPES*/
-
-/* Define this macro if an instruction to load a value narrower
-   than a word from memory into a register also zero-extends the
-   value to the whole  register.  */
-/*#define BYTE_LOADS_ZERO_EXTEND*/
-
-/* Define this macro as a C expression which is nonzero if
-   accessing less than a word of memory (i.e. a `char' or a
-   `short') is no faster than accessing a word of memory, i.e., if
-   such access require more than one instruction or if there is no
-   difference in cost between byte and (aligned) word loads.
-
-   On RISC machines, it tends to generate better code to define
-   this as 1, since it avoids making a QI or HI mode register.  */
-/*
-#undef SLOW_BYTE_ACCESS
-#define SLOW_BYTE_ACCESS 1
-*/
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-
-#define FASTEST_ALIGNMENT 32
-
-/* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  (TREE_CODE (EXP) == STRING_CST	\
-   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
-
-/*
- *	disable a few things picked up from svr3.h
- */
-#undef INIT_SECTION_ASM_OP
-#undef FINI_SECTION_ASM_OP
-#undef CONST_SECTION_ASM_OP
-#undef CTORS_SECTION_ASM_OP
-#undef DTORS_SECTION_ASM_OP
-#undef DO_GLOBAL_CTORS_BODY
-#undef ASM_OUTPUT_DESTRUCTOR
-#undef SELECT_SECTION
-#undef SELECT_RTX_SECTION
-#undef READONLY_DATA_SECTION
-
-#define	BSS_SECTION_ASM_OP	".bss"		/* XXX */
-#undef EXTRA_SECTIONS
-#undef EXTRA_SECTION_FUNCTIONS
diff --git a/gcc/config/i860/sysv3.h b/gcc/config/i860/sysv3.h
deleted file mode 100755
index 56f8e49..0000000
--- a/gcc/config/i860/sysv3.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/* Target definitions for GNU compiler for Intel 80860 running System V.3
-   Copyright (C) 1991, 1996 Free Software Foundation, Inc.
-   Contributed by Ron Guilmette (rfg@monkeys.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i860, System V Release 3)")
-
-/* Provide a set of pre-definitions and pre-assertions appropriate for
-   the i860 running svr3.  */
-#define CPP_PREDEFINES "-Di860 -Dunix -D__svr3__ -Asystem(unix) -Asystem(svr3) -Acpu(i860) -Amachine(i860)"
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-
-#define STARTFILE_SPEC  \
-  "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
-
-#define LIB_SPEC "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} -lc crtn.o%s"
-
-/* Special flags for the linker.  I don't know what they do.  */
-
-#define LINK_SPEC "%{T*} %{z:-lm}"
-
-/* The prefix to be used in assembler output for all names of registers.
-   None is needed in V.3.  */
-
-#define I860_REG_PREFIX	""
-
-/* Delimiter that starts comments in the assembler code.  */
-
-#define ASM_COMMENT_START "//"
-
-/* Don't renumber the regusters for debugger output.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Output the special word the System V SDB wants to see just before
-   the first word of each function's prologue code.  */
-
-extern char *current_function_original_name;
-
-/* This special macro is used to output a magic word just before the
-   first word of each function.  On some versions of UNIX running on
-   the i860, this word can be any word that looks like a NOP, however
-   under svr4, this neds to be an `shr r0,r0,r0' instruction in which
-   the normally unused low-order bits contain the length of the function
-   prologue code (in bytes).  This is needed to make the System V SDB
-   debugger happy.  */
-
-#undef ASM_OUTPUT_FUNCTION_PREFIX
-#define ASM_OUTPUT_FUNCTION_PREFIX(FILE, FNNAME)			\
-  do {	ASM_OUTPUT_ALIGN (FILE, 2);					\
-  	fprintf ((FILE), "\t.long\t.ep.");				\
-	assemble_name (FILE, FNNAME);					\
-	fprintf (FILE, "-");						\
-	assemble_name (FILE, FNNAME);					\
-	fprintf (FILE, "+0xc8000000\n");				\
-	current_function_original_name = (FNNAME);			\
-  } while (0)
-
-/* Output the special label that must go just after each function's
-   prologue code to support svr4 SDB.  */
-
-#define ASM_OUTPUT_PROLOGUE_SUFFIX(FILE)				\
-  do {	fprintf (FILE, ".ep.");						\
-	assemble_name (FILE, current_function_original_name);		\
-	fprintf (FILE, ":\n");						\
-  } while (0)
-
-/* This says how to output an assembler line
-   to define a local common symbol.
-   The difference from svr3.h is we don't limit align to 2.  */
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
-  do {							\
-    int align = exact_log2 (ROUNDED);			\
-    data_section ();					\
-    ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align);	\
-    ASM_OUTPUT_LABEL ((FILE), (NAME));			\
-    fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED));	\
-  } while (0)
-
-/* The routine used to output string literals.
-
-#define ASCII_DATA_ASM_OP	".byte"
-
-#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH)				\
-  do									\
-    {									\
-      register unsigned char *str = (unsigned char *) (STR);		\
-      register unsigned char *limit = str + (LENGTH);			\
-      register unsigned bytes_in_chunk = 0;				\
-      for (; str < limit; str++)					\
-        {								\
-          register unsigned ch = *str;					\
-          if (ch < 32 || ch == '\\' || ch == '"' || ch >= 127)		\
-	    {								\
-	      if (bytes_in_chunk > 0)					\
-	        {							\
-	          fprintf ((FILE), "\"\n");				\
-	          bytes_in_chunk = 0;					\
-	        }							\
-	      fprintf ((FILE), "\t%s\t%d\n", ASM_BYTE_OP, ch);		\
-	    }								\
-          else								\
-	    {								\
-	      if (bytes_in_chunk >= 60)					\
-	        {							\
-	          fprintf ((FILE), "\"\n");				\
-	          bytes_in_chunk = 0;					\
-	        }							\
-	      if (bytes_in_chunk == 0)					\
-	        fprintf ((FILE), "\t%s\t\"", ASCII_DATA_ASM_OP);	\
-	      putc (ch, (FILE));					\
-	      bytes_in_chunk++;						\
-	    }								\
-        }								\
-      if (bytes_in_chunk > 0)						\
-        fprintf ((FILE), "\"\n");					\
-    }									\
-  while (0)
-
-
-#undef CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"x\""
-#undef DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"x\""
-
-/* Add definitions to support the .tdesc section as specified in the svr4
-   ABI for the i860.  */
-
-#define TDESC_SECTION_ASM_OP    ".section\t.tdesc"
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_ctors, in_dtors, in_tdesc
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CONST_SECTION_FUNCTION						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION						\
-  TDESC_SECTION_FUNCTION
-
-#define TDESC_SECTION_FUNCTION						\
-void									\
-tdesc_section ()							\
-{									\
-  if (in_section != in_tdesc)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", TDESC_SECTION_ASM_OP);		\
-      in_section = in_tdesc;						\
-    }									\
-}
-
-/* Enable the `const' section that svr3.h defines how to use.  */
-#undef USE_CONST_SECTION
-#define USE_CONST_SECTION	1
diff --git a/gcc/config/i860/sysv4.h b/gcc/config/i860/sysv4.h
deleted file mode 100755
index eca6b79..0000000
--- a/gcc/config/i860/sysv4.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/* Target definitions for GNU compiler for Intel 80860 running System V.4
-   Copyright (C) 1991, 1996 Free Software Foundation, Inc.
-   Contributed by Ron Guilmette (rfg@monkeys.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (i860 System V Release 4)");
-
-/* Provide a set of pre-definitions and pre-assertions appropriate for
-   the i860 running svr4.  Note that the symbol `__svr4__' MUST BE
-   DEFINED!  It is needed so that the va_list struct in va-i860.h
-   will get correctly defined for the svr4 (ABI compliant) case rather
-   than for the previous (svr3, svr2, ...) case.  It also needs to be
-   defined so that the correct (svr4) version of __builtin_saveregs
-   will be selected when we are building gnulib2.c.
-   __svr4__ is our extension.  */
-
-#define CPP_PREDEFINES \
-  "-Di860 -Dunix -DSVR4 -D__svr4__ -Asystem(unix) -Asystem(svr4) -Acpu(i860) -Amachine(i860)"
-
-/* The prefix to be used in assembler output for all names of registers.
-   This string gets prepended to all i860 register names (svr4 only).  */
-
-#define I860_REG_PREFIX	"%"
-
-#define ASM_COMMENT_START "#"
-
-#undef TYPE_OPERAND_FMT
-#define TYPE_OPERAND_FMT      "\"%s\""
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* The following macro definition overrides the one in i860.h
-   because the svr4 i860 assembler requires a different syntax
-   for getting parts of constant/relocatable values.  */
-
-#undef PRINT_OPERAND_PART
-#define PRINT_OPERAND_PART(FILE, X, PART_CODE)				\
-  do { fprintf (FILE, "[");						\
-	output_address (X);						\
-	fprintf (FILE, "]@%s", PART_CODE);				\
-  } while (0)
-
-/* If the host and target formats match, output the floats as hex.  */
-#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
-#if defined (HOST_WORDS_BIG_ENDIAN) == WORDS_BIG_ENDIAN
-
-/* This is how to output an assembler line defining a `double' constant.
-   Note that the native i860/svr4 ELF assembler can't properly handle
-   infinity.  It generates an incorrect (non-infinity) value when given
-   `.double 99e9999' and it doesn't grok `inf' at all.  It also mishandles
-   NaNs and -0.0.  */
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t[2];							\
-	REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);			\
-	fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", t[0], t[1]);	\
-      }									\
-    else								\
-      fprintf (FILE, "\t.double %.20e\n", VALUE);			\
-  }
-
-/* This is how to output an assembler line defining a `float' constant.
-   Note that the native i860/svr4 ELF assembler can't properly handle
-   infinity.  It actually generates an assembly time error when given
-   `.float 99e9999' and it doesn't grok `inf' at all.  It also mishandles
-   NaNs and -0.0.  */
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t;								\
-	REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
-	fprintf (FILE, "\t.word 0x%lx\n", t);				\
-      }									\
-    else								\
-      fprintf (FILE, "\t.float %.12e\n", VALUE);			\
-  }
-
-#endif /* word order matches */
-#endif /* HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)						\
-  do {	output_file_directive (FILE, main_input_filename);		\
-	fprintf (FILE, "\t.version\t\"01.01\"\n");			\
-  } while (0)
-
-/* Output the special word the svr4 SDB wants to see just before
-   the first word of each function's prologue code.  */
-
-extern char *current_function_original_name;
-
-/* This special macro is used to output a magic word just before the
-   first word of each function.  On some versions of UNIX running on
-   the i860, this word can be any word that looks like a NOP, however
-   under svr4, this neds to be an `shr r0,r0,r0' instruction in which
-   the normally unused low-order bits contain the length of the function
-   prologue code (in bytes).  This is needed to make the svr4 SDB debugger
-   happy.  */
-
-#undef ASM_OUTPUT_FUNCTION_PREFIX
-#define ASM_OUTPUT_FUNCTION_PREFIX(FILE, FNNAME)			\
-  do {	ASM_OUTPUT_ALIGN (FILE, 2);					\
-  	fprintf ((FILE), "\t.long\t.ep.");				\
-	assemble_name (FILE, FNNAME);					\
-	fprintf (FILE, "-");						\
-	assemble_name (FILE, FNNAME);					\
-	fprintf (FILE, "+0xc8000000\n");				\
-	current_function_original_name = (FNNAME);			\
-  } while (0)
-
-/* Output the special label that must go just after each function's
-   prologue code to support svr4 SDB.  */
-
-#define ASM_OUTPUT_PROLOGUE_SUFFIX(FILE)				\
-  do {	fprintf (FILE, ".ep.");						\
-	assemble_name (FILE, current_function_original_name);		\
-	fprintf (FILE, ":\n");						\
-  } while (0)
-
-/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
- 
-   Note that we want to give these sections the SHF_WRITE attribute
-   because these sections will actually contain data (i.e. tables of
-   addresses of functions in the current root executable or shared library
-   file) and, in the case of a shared library, the relocatable addresses
-   will have to be properly resolved/relocated (and then written into) by
-   the dynamic linker when it actually attaches the given shared library
-   to the executing process.  (Note that on SVR4, you may wish to use the
-   `-z text' option to the ELF linker, when building a shared library, as
-   an additional check that you are doing everything right.  But if you do
-   use the `-z text' option when building a shared library, you will get
-   errors unless the .ctors and .dtors sections are marked as writable
-   via the SHF_WRITE attribute.)  */
- 
-#undef CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"aw\""
-#undef DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"aw\""
-
-/* Add definitions to support the .tdesc section as specified in the svr4
-   ABI for the i860.  */
-
-#define TDESC_SECTION_ASM_OP    ".section\t.tdesc"
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_ctors, in_dtors, in_tdesc
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CONST_SECTION_FUNCTION						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION						\
-  TDESC_SECTION_FUNCTION
-
-#define TDESC_SECTION_FUNCTION						\
-void									\
-tdesc_section ()							\
-{									\
-  if (in_section != in_tdesc)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", TDESC_SECTION_ASM_OP);		\
-      in_section = in_tdesc;						\
-    }									\
-}
-
diff --git a/gcc/config/i860/t-fx2800 b/gcc/config/i860/t-fx2800
deleted file mode 100755
index 5f08173..0000000
--- a/gcc/config/i860/t-fx2800
+++ /dev/null
@@ -1,3 +0,0 @@
-# Use ieee rounding rules for divide and square root operations.
-# /bin/cc is assumed to point to fxc version 1.3 or newer.
-CCLIBFLAGS=-O -ieee -uniproc
diff --git a/gcc/config/i860/x-fx2800 b/gcc/config/i860/x-fx2800
deleted file mode 100755
index cf05f8f..0000000
--- a/gcc/config/i860/x-fx2800
+++ /dev/null
@@ -1,7 +0,0 @@
-
-# The Alliant FX2800 is supposed to conform to the SysV R4 i860 ABI,
-# but apparently the native compiler generates non ABI-compliant
-# function prologues and epilogues, so we need the alloca from emacs.
-#  -- hyc@hanauma.jpl.nasa.gov
-
-ALLOCA=alloca.o
diff --git a/gcc/config/i860/x-sysv3 b/gcc/config/i860/x-sysv3
deleted file mode 100755
index 3375d42..0000000
--- a/gcc/config/i860/x-sysv3
+++ /dev/null
@@ -1 +0,0 @@
-ALLOCA=alloca.o
diff --git a/gcc/config/i860/x-sysv4 b/gcc/config/i860/x-sysv4
deleted file mode 100755
index c01fb88..0000000
--- a/gcc/config/i860/x-sysv4
+++ /dev/null
@@ -1,44 +0,0 @@
-# The svr4 reference port for the i860 contains an alloca.o routine
-# in /usr/ucblib/libucb.a, but we can't just try to get that by
-# setting CLIB to /usr/ucblib/libucb.a because (unfortunately)
-# there are a lot of other routines in libucb.a which are supposed
-# to be the Berkeley versions of library routines normally found in
-# libc.a and many of these Berkeley versions are badly broken.  Thus,
-# if we try to link programs with libucb.a before libc.a, those
-# programs tend to crash.
-
-# Also, the alloca() routine supplied in early version of svr4 for
-# the i860 is non-ABI compliant.  It doesn't keep the stack aligned
-# to a 16-byte boundary as the ABI requires.
-
-# More importantly however, even a fully ABI compliant alloca() routine
-# would fail to work correctly with some versions of the native svr4 C
-# compiler currently being distributed for the i860 (as of 1/29/92).
-# The problem is that the native C compiler generates non-ABI-compliant
-# function epilogues which cut back the stack (upon function exit) in
-# an incorrect manner.  Specifically, they cut back the stack by adding
-# the nominal *static* frame size (determined statically at compile-time)
-# to the stack pointer rather than setting the stack pointer based upon
-# the current value of the frame pointer (as called for in the i860 ABI).
-# This can cause serious trouble in cases where you repeatedly call a
-# routine which itself calls alloca().  In such cases, the stack will
-# grow continuously until you finally run out of swap space or exceed
-# the system's process size limit.  To avoid this problem (which can
-# arise when a stage1 gcc is being used to build a stage2 gcc) you
-# *must* link in the C language version of alloca() which is supplied
-# with gcc to your stage1 version of gcc.  The following definition
-# forces that to happen.
-
-ALLOCA=alloca.o
-
-# We build all stages *without* shared libraries because that may make
-# debugging the compiler easier (until there is a GDB which supports
-# both Dwarf *and* svr4 shared libraries).
-
-# Note that the native C compiler for the svr4 reference port on the
-# i860 recognizes a special -gg option.  Using that option causes *full*
-# Dwarf debugging information to be generated, whereas using only -g
-# causes only limited Dwarf debugging information to be generated.
-# (This is an undocumented feature of the native svr4 C compiler.)
-
-CCLIBFLAGS=-Bstatic -dn -gg
diff --git a/gcc/config/i860/xm-fx2800.h b/gcc/config/i860/xm-fx2800.h
deleted file mode 100755
index f1ab6d8..0000000
--- a/gcc/config/i860/xm-fx2800.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Alliant FX/2800 running Concentrix 2.x. */
-
-/* vfprintf is not present prior to Concentrix 2.2. Unfortunately, there
-   does not seem to be a cpp symbol that identifies OS revision. Undefine
-   the following if running 2.1 or older.  */
-
-#define HAVE_VPRINTF
diff --git a/gcc/config/i860/xm-i860.h b/gcc/config/i860/xm-i860.h
deleted file mode 100755
index 4e8488f..0000000
--- a/gcc/config/i860/xm-i860.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Configuration for GNU C-compiler for Intel i860.
-   Copyright (C) 1988, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#ifndef i860
-#define i860
-#endif
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-
-#include "tm.h"
diff --git a/gcc/config/i960/i960-coff.h b/gcc/config/i960/i960-coff.h
deleted file mode 100755
index 139e8d1..0000000
--- a/gcc/config/i960/i960-coff.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Definitions of target machine for GNU compiler, for "naked" Intel
-   80960 using coff object format and coff debugging symbols.
-   Copyright (C) 1988, 1989, 1991, 1996 Free Software Foundation.
-   Contributed by Steven McGeady (mcg@omepd.intel.com)
-   Additional work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
-   Converted to GCC 2.0 by Michael Tiemann, Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Support -gstabs using stabs in COFF sections.  */
-
-/* Generate SDB_DEBUGGING_INFO by default.  */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
-
-/* This is intended to be used with Cygnus's newlib library, so we want to
-   use the standard definition of LIB_SPEC.  */
-#undef LIB_SPEC
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
-  output_file_directive ((FILE), main_input_filename)
-
-/* Support the ctors and dtors sections for g++.  */
-
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"x\""
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"x\""
-
-/* A list of other sections which the compiler might be "in" at any
-   given time.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_ctors, in_dtors
-
-/* A list of extra section function definitions.  */
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-#define INT_ASM_OP ".word"
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* end of i960-coff.h */
diff --git a/gcc/config/i960/i960.c b/gcc/config/i960/i960.c
deleted file mode 100755
index 970cef0..0000000
--- a/gcc/config/i960/i960.c
+++ /dev/null
@@ -1,3000 +0,0 @@
-/* Subroutines used for code generation on intel 80960.
-   Copyright (C) 1992, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Steven McGeady, Intel Corp.
-   Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
-   Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "tree.h"
-#include "insn-codes.h"
-#include "expr.h"
-#include "except.h"
-#include "function.h"
-#include "recog.h"
-#include <math.h>
-
-/* Save the operands last given to a compare for use when we
-   generate a scc or bcc insn.  */
-
-rtx i960_compare_op0, i960_compare_op1;
-
-/* Used to implement #pragma align/noalign.  Initialized by OVERRIDE_OPTIONS
-   macro in i960.h.  */
-
-static int i960_maxbitalignment;
-static int i960_last_maxbitalignment;
-
-/* Used to implement switching between MEM and ALU insn types, for better
-   C series performance.  */
-
-enum insn_types i960_last_insn_type;
-
-/* The leaf-procedure return register.  Set only if this is a leaf routine.  */
-
-static int i960_leaf_ret_reg;
-
-/* True if replacing tail calls with jumps is OK.  */
-
-static int tail_call_ok;
-
-/* A string containing a list of insns to emit in the epilogue so as to
-   restore all registers saved by the prologue.  Created by the prologue
-   code as it saves registers away.  */
-
-char epilogue_string[1000];
-
-/* A unique number (per function) for return labels.  */
-
-static int ret_label = 0;
-
-/* This is true if FNDECL is either a varargs or a stdarg function.
-   This is used to help identify functions that use an argument block.  */
-
-#define VARARGS_STDARG_FUNCTION(FNDECL)	\
-((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0						      \
-  && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node))    \
- || current_function_varargs)
-
-/* Handle pragmas for compatibility with Intel's compilers.  */
-
-/* ??? This is incomplete, since it does not handle all pragmas that the
-   intel compilers understand.  */
-
-int
-process_pragma (p_getc, p_ungetc, pname)
-     int (*  p_getc) PROTO ((void));
-     void (* p_ungetc) PROTO ((int));
-     char * pname;
-{
-  int i;
-  register int c;
-  char buf[20];
-  char *s = buf;
-  int align;
-
-  /* Should be pragma 'far' or equivalent for callx/balx here.  */
-  if (strcmp (pname, "align") != 0)
-    return 0;
-  
-  do
-    {
-      c = p_getc ();
-    }
-  while (c == ' ' || c == '\t');
-
-  if (c == '(')
-    c = p_getc ();
-  
-  while (c >= '0' && c <= '9')
-    {
-      if (s < buf + sizeof buf - 1)
-	*s++ = c;
-      c = p_getc ();
-    }
-  
-  *s = '\0';
-
-  /* We had to read a non-numerical character to get out of the
-     while loop---often a newline.  So, we have to put it back to
-     make sure we continue to parse everything properly.  */
-  
-  p_ungetc (c);
-
-  align = atoi (buf);
-
-  switch (align)
-    {
-    case 0:
-      /* Return to last alignment.  */
-      align = i960_last_maxbitalignment / 8;
-      /* Fall through.  */
-    case 16:
-    case 8:
-    case 4:
-    case 2:
-    case 1:
-      i960_last_maxbitalignment = i960_maxbitalignment;
-      i960_maxbitalignment = align * 8;
-      break;
-      
-    default:
-      /* Silently ignore bad values.  */
-      break;
-    }
-  
-  /* NOTE: ic960 R3.0 pragma align definition:
-     
-     #pragma align [(size)] | (identifier=size[,...])
-     #pragma noalign [(identifier)[,...]]
-     
-     (all parens are optional)
-     
-     - size is [1,2,4,8,16]
-     - noalign means size==1
-     - applies only to component elements of a struct (and union?)
-     - identifier applies to structure tag (only)
-     - missing identifier means next struct
-     
-     - alignment rules for bitfields need more investigation  */
-  
-  return 1;
-}
-
-/* Initialize variables before compiling any files.  */
-
-void
-i960_initialize ()
-{
-  if (TARGET_IC_COMPAT2_0)
-    {
-      i960_maxbitalignment = 8;
-      i960_last_maxbitalignment = 128;
-    }
-  else
-    {
-      i960_maxbitalignment = 128;
-      i960_last_maxbitalignment = 8;
-    }
-}
-
-/* Return true if OP can be used as the source of an fp move insn.  */
-
-int
-fpmove_src_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode));
-}
-
-#if 0
-/* Return true if OP is a register or zero.  */
-
-int
-reg_or_zero_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return register_operand (op, mode) || op == const0_rtx;
-}
-#endif
-
-/* Return truth value of whether OP can be used as an operands in a three
-   address arithmetic insn (such as add %o1,7,%l2) of mode MODE.  */
-
-int
-arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode) || literal (op, mode));
-}
-
-/* Return truth value of whether OP can be used as an operands in a three
-   address logic insn, possibly complementing OP, of mode MODE.  */
-
-int
-logic_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT
-	      && INTVAL(op) >= -32 && INTVAL(op) < 32));
-}
-
-/* Return true if OP is a register or a valid floating point literal.  */
-
-int
-fp_arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode) || fp_literal (op, mode));
-}
-
-/* Return true is OP is a register or a valid signed integer literal.  */
-
-int
-signed_arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode) || signed_literal (op, mode));
-}
-
-/* Return truth value of whether OP is a integer which fits the
-   range constraining immediate operands in three-address insns.  */
-
-int
-literal (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32);
-}
-
-/* Return true if OP is a float constant of 1.  */
-
-int
-fp_literal_one (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST1_RTX (mode));
-}
-
-/* Return true if OP is a float constant of 0.  */
-
-int
-fp_literal_zero (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST0_RTX (mode));
-}
-
-/* Return true if OP is a valid floating point literal.  */
-
-int
-fp_literal(op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return fp_literal_zero (op, mode) || fp_literal_one (op, mode);
-}
-
-/* Return true if OP is a valid signed immediate constant.  */
-
-int
-signed_literal(op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32);
-}
-
-/* Return truth value of statement that OP is a symbolic memory
-   operand of mode MODE.  */
-
-int
-symbolic_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  if (GET_CODE (op) != MEM)
-    return 0;
-  op = XEXP (op, 0);
-  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
-	  || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
-}
-
-/* Return truth value of whether OP is EQ or NE.  */
-
-int
-eq_or_neq (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
-}
-
-/* OP is an integer register or a constant.  */
-
-int
-arith32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (register_operand (op, mode))
-    return 1;
-  return (CONSTANT_P (op));
-}
-
-/* Return true if OP is an integer constant which is a power of 2.  */
-
-int
-power2_operand (op,mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-
-  return exact_log2 (INTVAL (op)) >= 0;
-}
-
-/* Return true if OP is an integer constant which is the complement of a
-   power of 2.  */
-
-int
-cmplpower2_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-
-  return exact_log2 (~ INTVAL (op)) >= 0;
-}
-
-/* If VAL has only one bit set, return the index of that bit.  Otherwise
-   return -1.  */
-
-int
-bitpos (val)
-     unsigned int val;
-{
-  register int i;
-
-  for (i = 0; val != 0; i++, val >>= 1)
-    {
-      if (val & 1)
-	{
-	  if (val != 1)
-	    return -1;
-	  return i;
-	}
-    }
-  return -1;
-}
-
-/* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
-   The return value indicates how many consecutive non-zero bits exist
-   if this is a mask.  This is the same as the next function, except that
-   it does not indicate what the start and stop bit positions are.  */
-
-int
-is_mask (val)
-     unsigned int val;
-{
-  register int start, end, i;
-
-  start = -1;
-  for (i = 0; val != 0; val >>= 1, i++)
-    {
-      if (val & 1)
-	{
-	  if (start < 0)
-	    start = i;
-
-	  end = i;
-	  continue;
-	}
-      /* Still looking for the first bit.  */
-      if (start < 0)
-	continue;
-
-      /* We've seen the start of a bit sequence, and now a zero.  There
-	 must be more one bits, otherwise we would have exited the loop.
-	 Therefore, it is not a mask.  */
-      if (val)
-	return 0;
-    }
-
-  /* The bit string has ones from START to END bit positions only.  */
-  return end - start + 1;
-}
-
-/* If VAL is a mask, then return nonzero, with S set to the starting bit
-   position and E set to the ending bit position of the mask.  The return
-   value indicates how many consecutive bits exist in the mask.  This is
-   the same as the previous function, except that it also indicates the
-   start and end bit positions of the mask.  */
-
-int
-bitstr (val, s, e)
-     unsigned int val;
-     int *s, *e;
-{
-  register int start, end, i;
-
-  start = -1;
-  end = -1;
-  for (i = 0; val != 0; val >>= 1, i++)
-    {
-      if (val & 1)
-	{
-	  if (start < 0)
-	    start = i;
-
-	  end = i;
-	  continue;
-	}
-
-      /* Still looking for the first bit.  */
-      if (start < 0)
-	continue;
-
-      /* We've seen the start of a bit sequence, and now a zero.  There
-	 must be more one bits, otherwise we would have exited the loop.
-	 Therefor, it is not a mask.  */
-      if (val)
-	{
-	  start = -1;
-	  end = -1;
-	  break;
-	}
-    }
-
-  /* The bit string has ones from START to END bit positions only.  */
-  *s = start;
-  *e = end;
-  return ((start < 0) ? 0 : end - start + 1);
-}
-
-/* Return the machine mode to use for a comparison.  */
-
-enum machine_mode
-select_cc_mode (op, x)
-     RTX_CODE op;
-     rtx x;
-{
-  if (op == GTU || op == LTU || op == GEU || op == LEU)
-    return CC_UNSmode;
-  return CCmode;
-}
-
-/* X and Y are two things to compare using CODE.  Emit the compare insn and
-   return the rtx for register 36 in the proper mode.  */
-
-rtx
-gen_compare_reg (code, x, y)
-     enum rtx_code code;
-     rtx x, y;
-{
-  rtx cc_reg;
-  enum machine_mode ccmode = SELECT_CC_MODE (code, x, y);
-  enum machine_mode mode
-    = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x);
-
-  if (mode == SImode)
-    {
-      if (! arith_operand (x, mode))
-	x = force_reg (SImode, x);
-      if (! arith_operand (y, mode))
-	y = force_reg (SImode, y);
-    }
-
-  cc_reg = gen_rtx (REG, ccmode, 36);
-  emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
-		      gen_rtx (COMPARE, ccmode, x, y)));
-
-  return cc_reg;
-}
-
-/* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
-   REG+nonimmed CONST is cost 4.  REG+SYMBOL_REF, SYMBOL_REF, and similar
-   are 4.  Indexed addresses are cost 6.  */
-
-/* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST.  */
-
-int
-i960_address_cost (x)
-     rtx x;
-{
-#if 0
-  /* Handled before calling here.  */
-  if (GET_CODE (x) == REG)
-    return 1;
-#endif
-  /* This is a MEMA operand -- it's free.  */
-  if (GET_CODE (x) == CONST_INT
-      && INTVAL (x) >= 0
-      && INTVAL (x) < 4096)
-    return 0;
-
-  if (GET_CODE (x) == PLUS)
-    {
-      rtx base = XEXP (x, 0);
-      rtx offset = XEXP (x, 1);
-
-      if (GET_CODE (base) == SUBREG)
-	base = SUBREG_REG (base);
-      if (GET_CODE (offset) == SUBREG)
-	offset = SUBREG_REG (offset);
-
-      if (GET_CODE (base) == REG)
-	{
-	  if (GET_CODE (offset) == REG)
-	    return 2;
-	  if (GET_CODE (offset) == CONST_INT)
-	    {
-	      if ((unsigned)INTVAL (offset) < 2047)
-		return 2;
-	      return 4;
-	    }
-	  if (CONSTANT_P (offset))
-	    return 4;
-	}
-      if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT)
-	return 6;
-
-      /* This is an invalid address.  The return value doesn't matter, but
-	 for convenience we make this more expensive than anything else.  */
-      return 12;
-    }
-  if (GET_CODE (x) == MULT)
-    return 6;
-
-  /* Symbol_refs and other unrecognized addresses are cost 4.  */
-  return 4;
-}
-
-/* CYGNUS LOCAL -- move coalescence */
-/* Global variables that are reset for each function.  */
-
-static rtx i960_const0_r12r13;		/* for DImode const0_rtx */
-static rtx i960_const0_r12r15;		/* for TImode const0_rtx */
-
-/* Define the structure for the machine field in struct function.  */
-struct machine_function
-{
-  rtx const0_r12r13;
-  rtx const0_r12r15;
-};
-
-/* Functions to save and restore i960_fpmem_size.
-   These will be called, via pointer variables,
-   from push_function_context and pop_function_context.  */
-
-void
-i960_save_machine_status (p)
-     struct function *p;
-{
-  struct machine_function *machine =
-    (struct machine_function *) xmalloc (sizeof (struct machine_function));
-
-  p->machine = machine;
-  machine->const0_r12r13 = i960_const0_r12r13;
-  machine->const0_r12r15 = i960_const0_r12r15;
-}
-
-void
-i960_restore_machine_status (p)
-     struct function *p;
-{
-  struct machine_function *machine = p->machine;
-
-  i960_const0_r12r13 = machine->const0_r12r13;
-  i960_const0_r12r15 = machine->const0_r12r15;
-
-  free (machine);
-  p->machine = (struct machine_function *)0;
-}
-
-/* Do anything needed before RTL is emitted for each function.  */
-
-void
-i960_init_expanders ()
-{
-  i960_const0_r12r13 = (rtx) 0;
-  i960_const0_r12r15 = (rtx) 0;
-
-  /* Arrange to save and restore machine status around nested functions.  */
-  save_machine_status = i960_save_machine_status;
-  restore_machine_status = i960_restore_machine_status;
-}
-
-
-/* END CYGNUS LOCAL -- move coalescence */
-
-/* Emit insns to move operands[1] into operands[0].
-
-   Return 1 if we have written out everything that needs to be done to
-   do the move.  Otherwise, return 0 and the caller will emit the move
-   normally. */
-
-int
-emit_move_sequence (operands, mode)
-     rtx *operands;
-     enum machine_mode mode;
-{
-  /* We can only store registers to memory.  */
-  
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG
-      && (operands[1] != const0_rtx || current_function_args_size
-	  || current_function_varargs || current_function_stdarg
-	  || rtx_equal_function_value_matters))
-    /* Here we use the same test as movsi+1 pattern -- see i960.md. */
-    operands[1] = force_reg (mode, operands[1]);
-
-  /* Storing multi-word values in unaligned hard registers to memory may
-     require a scratch since we have to store them a register at a time and
-     adding 4 to the memory address may not yield a valid insn.  */
-  /* ??? We don't always need the scratch, but that would complicate things.
-     Maybe later.  */
-  /* ??? We must also handle stores to pseudos here, because the pseudo may be
-     replaced with a MEM later.  This would be cleaner if we didn't have
-     a separate pattern for unaligned DImode/TImode stores.  */
-  if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
-      && (GET_CODE (operands[0]) == MEM
-	  || (GET_CODE (operands[0]) == REG
-	      && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
-      && GET_CODE (operands[1]) == REG
-      && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-      && ! HARD_REGNO_MODE_OK (REGNO (operands[1]), mode))
-    {
-      emit_insn (gen_rtx (PARALLEL, VOIDmode,
-			  gen_rtvec (2,
-				     gen_rtx (SET, VOIDmode,
-					      operands[0], operands[1]),
-				     gen_rtx (CLOBBER, VOIDmode,
-					      gen_rtx (SCRATCH, Pmode)))));
-      return 1;
-    }
-
-/* CYGNUS LOCAL -- move coalescence */
-  /* See if we can coalesce this move with a previous move.
-     ??? Actually coalesing is machine-independent optimization.  If
-     the optimization is implemented in machine independent part of
-     the compiler we will need remove the code. */
-  if (! TARGET_STRICT_ALIGN
-      && (operands[1] == const0_rtx || operands[1] == i960_const0_r12r13)
-      && GET_CODE (operands[0]) == MEM)
-    {
-      /* ??? This is bogus because we can get insn from a previous
-	 sequence.  But we need it, otherwise the optimization will
-	 never work because move pattern themselves always start an
-	 new sequence. */
-      rtx last_insn = (TARGET_MOVE_COALESCENCE
-		       ? get_last_insn_anywhere () : (rtx) 0);
-      rtx last_dest;
-
-      if (last_insn && GET_CODE (last_insn) == NOTE)
-	last_insn = prev_nonnote_insn (last_insn);
-
-      if (last_insn && GET_CODE (last_insn) == INSN
-	  && GET_CODE (PATTERN (last_insn)) == SET
-	  && (SET_SRC (PATTERN (last_insn)) == const0_rtx
-	      || SET_SRC (PATTERN (last_insn)) == i960_const0_r12r13)
-	  && GET_CODE (last_dest = SET_DEST (PATTERN (last_insn))) == MEM)
-	{
-	  rtx last_addr = XEXP (last_dest, 0);
-	  rtx this_addr = XEXP (operands[0], 0);
-	  enum machine_mode last_mode = GET_MODE (last_dest);
-
-	  if (last_mode == GET_MODE (operands[0])
-	      && GET_MODE_SIZE (last_mode) <= 8)
-	    {
-	      rtx last_base = last_addr, this_base = this_addr;
-	      rtx last_offset = const0_rtx, this_offset = const0_rtx;
-
-	      if (GET_CODE (last_addr) == PLUS)
-		{
-		  last_offset = XEXP (last_addr, 1);
-		  last_base = XEXP (last_addr, 0);
-		}
-	      if (GET_CODE (this_addr) == PLUS)
-		{
-		  this_offset = XEXP (this_addr, 1);
-		  this_base = XEXP (this_addr, 0);
-		}
-
-	      /* Now comes the time for the payoff: we check whether
-		 the two store instructions are to adjacent memory
-		 locations, and if so, we merge them.  We recurse
-		 here to pick up merges across 4, 8 or even 16 insns.  */
-
-	      if (rtx_equal_p (this_base, last_base))
-		{
-		  if (rtx_equal_p (last_offset,
-				   plus_constant (this_offset,
-						  GET_MODE_SIZE (last_mode))))
-		    XEXP (last_dest, 0) = this_addr;
-		  else if (!rtx_equal_p (this_offset,
-					 plus_constant
-					 (last_offset,
-					  GET_MODE_SIZE (last_mode))))
-		    last_dest = 0;
-		}
-	      else
-		last_dest = 0;
-
-	      /* If it worked, we've got some housekeeping to do... */
-	      if (last_dest)
-		{
-		  /* Change the size of our dest operand.  */
-		  PUT_MODE (last_dest, GET_MODE_WIDER_MODE (last_mode));
-		  operands[0] = last_dest;
-		  
-		  /* Remove our last insn so that recursion will work.  */
-		  PUT_CODE (last_insn, NOTE);
-		  NOTE_LINE_NUMBER (last_insn) = NOTE_INSN_DELETED;
-		  
-		  /* Make sure we have a large enough register
-		     to act as the source for const0_rtx.  */
-		  
-		  if (GET_MODE_SIZE (GET_MODE (last_dest)) > 4)
-		    {
-		      rtx reg_needs_init = 0;
-		      rtx const0_equiv;
-		      
-		      if (GET_MODE (last_dest) == DImode)
-			{
-			  if (i960_const0_r12r13 == 0)
-			    {
-			      i960_const0_r12r13 = gen_rtx (REG, DImode, 28);
-			      reg_needs_init = i960_const0_r12r13;
-			    }
-			  const0_equiv = i960_const0_r12r13;
-			}
-		      else
-			{
-			  if (i960_const0_r12r15 == 0)
-			    {
-			      i960_const0_r12r15 = gen_rtx (REG, TImode, 28);
-			      reg_needs_init = i960_const0_r12r15;
-			    }
-			  const0_equiv = i960_const0_r12r15;
-			}
-		      if (reg_needs_init)
-			{
-			  push_topmost_sequence ();
-			  emit_insn_before (gen_rtx (SET, VOIDmode,
-						     reg_needs_init,
-						     const0_rtx),
-					    next_real_insn (get_insns ()));
-			  pop_topmost_sequence ();
-			}
-		      operands[1] = const0_equiv;
-		    }
-		  return emit_move_sequence (operands, GET_MODE (last_dest));
-		}
-	    }
-	}
-    }
-/* END CYGNUS LOCAL -- move coalescence */
-  return 0;
-}
-
-/* Output assembler to move a double word value.  */
-
-char *
-i960_output_move_double (dst, src)
-     rtx dst, src;
-{
-  rtx operands[5];
-
-  if (GET_CODE (dst) == REG
-      && GET_CODE (src) == REG)
-    {
-      if ((REGNO (src) & 1)
-	  || (REGNO (dst) & 1))
-	{
-	  /* We normally copy the low-numbered register first.  However, if
-	     the second source register is the same as the first destination
-	     register, we must copy in the opposite order.  */
-	  if (REGNO (src) + 1 == REGNO (dst))
-	    return "mov	%D1,%D0\n\tmov	%1,%0";
-	  else
-	    return "mov	%1,%0\n\tmov	%D1,%D0";
-	}
-      else
-	return "movl	%1,%0";
-    }
-  else if (GET_CODE (dst) == REG
-	   && GET_CODE (src) == CONST_INT
-	   && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
-    {
-      if (REGNO (dst) & 1)
-	return "mov	%1,%0\n\tmov	0,%D0";
-      else
-	return "movl	%1,%0";
-    }
-  else if (GET_CODE (dst) == REG
-	   && GET_CODE (src) == MEM)
-    {
-      if (REGNO (dst) & 1)
-	{
-	  /* One can optimize a few cases here, but you have to be
-	     careful of clobbering registers used in the address and
-	     edge conditions.  */
-	  operands[0] = dst;
-	  operands[1] = src;
-	  operands[2] = gen_rtx (REG, Pmode, REGNO (dst) + 1);
-	  operands[3] = gen_rtx (MEM, word_mode, operands[2]);
-	  operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
-	  output_asm_insn ("lda	%1,%2\n\tld	%3,%0\n\tld	%4,%D0", operands);
-	  return "";
-	}
-      else
-	return "ldl	%1,%0";
-    }
-  else if (GET_CODE (dst) == MEM
-	   && GET_CODE (src) == REG)
-    {
-      if (REGNO (src) & 1)
-	{
-	  operands[0] = dst;
-	  operands[1] = adj_offsettable_operand (dst, UNITS_PER_WORD);
-	  if (! memory_address_p (word_mode, XEXP (operands[1], 0)))
-	    abort ();
-	  operands[2] = src;
-	  output_asm_insn ("st	%2,%0\n\tst	%D2,%1", operands);
-	  return "";
-	}
-      return "stl	%1,%0";
-    }
-  else
-    abort ();
-}
-
-/* Output assembler to move a double word zero.  */
-
-char *
-i960_output_move_double_zero (dst)
-     rtx dst;
-{
-  rtx operands[2];
-
-  operands[0] = dst;
-/* CYGNUS LOCAL -- move coalescence */
-  if (i960_const0_r12r13)
-    output_asm_insn ("stl	r12,%0", operands);
-  else
-/* END CYGNUS LOCAL -- move coalescence */
-    {
-      operands[1] = adj_offsettable_operand (dst, 4);
-      output_asm_insn ("st	g14,%0\n\tst	g14,%1", operands);
-    }
-  return "";
-}
-
-/* Output assembler to move a quad word value.  */
-
-char *
-i960_output_move_quad (dst, src)
-     rtx dst, src;
-{
-  rtx operands[7];
-
-  if (GET_CODE (dst) == REG
-      && GET_CODE (src) == REG)
-    {
-      if ((REGNO (src) & 3)
-	  || (REGNO (dst) & 3))
-	{
-	  /* We normally copy starting with the low numbered register.
-	     However, if there is an overlap such that the first dest reg
-	     is <= the last source reg but not < the first source reg, we
-	     must copy in the opposite order.  */
-	  if (REGNO (dst) <= REGNO (src) + 3
-	      && REGNO (dst) >= REGNO (src))
-	    return "mov	%F1,%F0\n\tmov	%E1,%E0\n\tmov	%D1,%D0\n\tmov	%1,%0";
-	  else
-	    return "mov	%1,%0\n\tmov	%D1,%D0\n\tmov	%E1,%E0\n\tmov	%F1,%F0";
-	}
-      else
-	return "movq	%1,%0";
-    }
-  else if (GET_CODE (dst) == REG
-	   && GET_CODE (src) == CONST_INT
-	   && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
-    {
-      if (REGNO (dst) & 3)
-	return "mov	%1,%0\n\tmov	0,%D0\n\tmov	0,%E0\n\tmov	0,%F0";
-      else
-	return "movq	%1,%0";
-    }
-  else if (GET_CODE (dst) == REG
-	   && GET_CODE (src) == MEM)
-    {
-      if (REGNO (dst) & 3)
-	{
-	  /* One can optimize a few cases here, but you have to be
-	     careful of clobbering registers used in the address and
-	     edge conditions.  */
-	  operands[0] = dst;
-	  operands[1] = src;
-	  operands[2] = gen_rtx (REG, Pmode, REGNO (dst) + 3);
-	  operands[3] = gen_rtx (MEM, word_mode, operands[2]);
-	  operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
-	  operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD);
-	  operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD);
-	  output_asm_insn ("lda	%1,%2\n\tld	%3,%0\n\tld	%4,%D0\n\tld	%5,%E0\n\tld	%6,%F0", operands);
-	  return "";
-	}
-      else
-	return "ldq	%1,%0";
-    }
-  else if (GET_CODE (dst) == MEM
-	   && GET_CODE (src) == REG)
-    {
-      if (REGNO (src) & 3)
-	{
-	  operands[0] = dst;
-	  operands[1] = adj_offsettable_operand (dst, UNITS_PER_WORD);
-	  operands[2] = adj_offsettable_operand (dst, 2*UNITS_PER_WORD);
-	  operands[3] = adj_offsettable_operand (dst, 3*UNITS_PER_WORD);
-	  if (! memory_address_p (word_mode, XEXP (operands[3], 0)))
-	    abort ();
-	  operands[4] = src;
-	  output_asm_insn ("st	%4,%0\n\tst	%D4,%1\n\tst	%E4,%2\n\tst	%F4,%3", operands);
-	  return "";
-	}
-      return "stq	%1,%0";
-    }
-  else
-    abort ();
-}
-
-/* Output assembler to move a quad word zero.  */
-
-char *
-i960_output_move_quad_zero (dst)
-     rtx dst;
-{
-  rtx operands[4];
-
-  operands[0] = dst;
-/* CYGNUS LOCAL -- move coalescence */
-  if (i960_const0_r12r15)
-    output_asm_insn ("stq	r12,%0", operands);
-  else
-/* END CYGNUS LOCAL -- move coalescence */
-    {
-      operands[1] = adj_offsettable_operand (dst, 4);
-      operands[2] = adj_offsettable_operand (dst, 8);
-      operands[3] = adj_offsettable_operand (dst, 12);
-      output_asm_insn ("st	g14,%0\n\tst	g14,%1\n\tst	g14,%2\n\tst	g14,%3", operands);
-    }
-  return "";
-}
-
-
-/* Emit insns to load a constant to non-floating point registers.
-   Uses several strategies to try to use as few insns as possible.  */
-
-char *
-i960_output_ldconst (dst, src)
-     register rtx dst, src;
-{
-  register int rsrc1;
-  register unsigned rsrc2;
-  enum machine_mode mode = GET_MODE (dst);
-  rtx operands[4];
-
-  operands[0] = operands[2] = dst;
-  operands[1] = operands[3] = src;
-
-  /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
-     must be a ldconst insn.  */
-
-  if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE)
-    {
-      output_asm_insn ("ldconst	%1,%0", operands);
-      return "";
-    }
-  else if (mode == XFmode)
-    {
-      REAL_VALUE_TYPE d;
-      long value_long[3];
-      int i;
-
-      if (fp_literal_zero (src, XFmode))
-	return "movt	0,%0";
-
-      REAL_VALUE_FROM_CONST_DOUBLE (d, src);
-      REAL_VALUE_TO_TARGET_LONG_DOUBLE (d, value_long);
-
-      output_asm_insn ("# ldconst	%1,%0",operands);
-
-      for (i = 0; i < 3; i++)
-	{
-	  operands[0] = gen_rtx (REG, SImode, REGNO (dst) + i);
-	  operands[1] = GEN_INT (value_long[i]);
-	  output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
-			   operands);
-	}
-
-      return ""; 
-   }
-  else if (mode == DFmode)
-    {
-      rtx first, second;
-
-      if (fp_literal_zero (src, DFmode))
-	return "movl	0,%0";
-
-      split_double (src, &first, &second);
-
-      output_asm_insn ("# ldconst	%1,%0",operands);
-
-      operands[0] = gen_rtx (REG, SImode, REGNO (dst));
-      operands[1] = first;
-      output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
-		      operands);
-      operands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1);
-      operands[1] = second;
-      output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
-		      operands);
-      return "";
-    }
-  else if (mode == SFmode)
-    {
-      REAL_VALUE_TYPE d;
-      long value;
-
-      REAL_VALUE_FROM_CONST_DOUBLE (d, src);
-      REAL_VALUE_TO_TARGET_SINGLE (d, value);
-
-      output_asm_insn ("# ldconst	%1,%0",operands);
-      operands[0] = gen_rtx (REG, SImode, REGNO (dst));
-      operands[1] = GEN_INT (value);
-      output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
-		      operands);
-      return "";
-    }
-  else if (mode == TImode)
-    {
-      /* ??? This is currently not handled at all.  */
-      abort ();
-
-      /* Note: lowest order word goes in lowest numbered reg.  */
-      rsrc1 = INTVAL (src);
-      if (rsrc1 >= 0 && rsrc1 < 32)
-	return "movq	%1,%0";
-      else
-	output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands);
-      /* Go pick up the low-order word.  */
-    }
-  else if (mode == DImode)
-    {
-      rtx upperhalf, lowerhalf, xoperands[2];
-
-      if (GET_CODE (src) == CONST_DOUBLE || GET_CODE (src) == CONST_INT)
- 	split_double (src, &lowerhalf, &upperhalf);
-
-      else
-	abort ();
-
-      /* Note: lowest order word goes in lowest numbered reg.  */
-      /* Numbers from 0 to 31 can be handled with a single insn.  */
-      rsrc1 = INTVAL (lowerhalf);
-      if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32)
-	return "movl	%1,%0";
-
-      /* Output the upper half with a recursive call.  */
-      xoperands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1);
-      xoperands[1] = upperhalf;
-      output_asm_insn (i960_output_ldconst (xoperands[0], xoperands[1]),
-		       xoperands);
-      /* The lower word is emitted as normally.  */
-    }
-  else
-    {
-      rsrc1 = INTVAL (src);
-      if (mode == QImode)
-	{
-	  if (rsrc1 > 0xff)
-	    rsrc1 &= 0xff;
-	}
-      else if (mode == HImode)
-	{
-	  if (rsrc1 > 0xffff)
-	    rsrc1 &= 0xffff;
-	}
-    }
-
-  if (rsrc1 >= 0)
-    {
-      /* ldconst	0..31,X		-> 	mov	0..31,X  */
-      if (rsrc1 < 32)
-	{
-	  if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
-	    return "lda	%1,%0";
-	  return "mov	%1,%0";
-	}
-
-      /* ldconst	32..63,X	->	add	31,nn,X  */
-      if (rsrc1 < 63)
-	{
-	  if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
-	    return "lda	%1,%0";
-	  operands[1] = GEN_INT (rsrc1 - 31);
-	  output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands);
-	  return "";
-	}
-    }
-  else if (rsrc1 < 0)
-    {
-      /* ldconst	-1..-31		->	sub	0,0..31,X  */
-      if (rsrc1 >= -31)
-	{
-	  /* return 'sub -(%1),0,%0' */
-	  operands[1] = GEN_INT (- rsrc1);
-	  output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands);
-	  return "";
-	}
-      
-      /* ldconst	-32		->	not	31,X  */
-      if (rsrc1 == -32)
-	{
-	  operands[1] = GEN_INT (~rsrc1);
-	  output_asm_insn ("not\t%1,%0	# ldconst %3,%0", operands);
-	  return "";
-	}
-    }
-
-  /* If const is a single bit.  */
-  if (bitpos (rsrc1) >= 0)
-    {
-      operands[1] = GEN_INT (bitpos (rsrc1));
-      output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands);
-      return "";
-    }
-
-  /* If const is a bit string of less than 6 bits (1..31 shifted).  */
-  if (is_mask (rsrc1))
-    {
-      int s, e;
-
-      if (bitstr (rsrc1, &s, &e) < 6)
-	{
-	  rsrc2 = ((unsigned int) rsrc1) >> s;
-	  operands[1] = GEN_INT (rsrc2);
-	  operands[2] = GEN_INT (s);
-	  output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands);
-	  return "";
-	}
-    }
-
-  /* Unimplemented cases:
-     const is in range 0..31 but rotated around end of word:
-     ror	31,3,g0	-> ldconst 0xe0000003,g0
-   
-     and any 2 instruction cases that might be worthwhile  */
-  
-  output_asm_insn ("ldconst	%1,%0", operands);
-  return "";
-}
-
-/* Determine if there is an opportunity for a bypass optimization.
-   Bypass succeeds on the 960K* if the destination of the previous
-   instruction is the second operand of the current instruction.
-   Bypass always succeeds on the C*.
- 
-   Return 1 if the pattern should interchange the operands.
-
-   CMPBR_FLAG is true if this is for a compare-and-branch insn.
-   OP1 and OP2 are the two source operands of a 3 operand insn.  */
-
-int
-i960_bypass (insn, op1, op2, cmpbr_flag)
-     register rtx insn, op1, op2;
-     int cmpbr_flag;
-{
-  register rtx prev_insn, prev_dest;
-
-  if (TARGET_C_SERIES)
-    return 0;
-
-  /* Can't do this if op1 isn't a register.  */
-  if (! REG_P (op1))
-    return 0;
-
-  /* Can't do this for a compare-and-branch if both ops aren't regs.  */
-  if (cmpbr_flag && ! REG_P (op2))
-    return 0;
-
-  prev_insn = prev_real_insn (insn);
-
-  if (prev_insn && GET_CODE (prev_insn) == INSN
-      && GET_CODE (PATTERN (prev_insn)) == SET)
-    {
-      prev_dest = SET_DEST (PATTERN (prev_insn));
-      if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1))
-	  || (GET_CODE (prev_dest) == SUBREG
-	      && GET_CODE (SUBREG_REG (prev_dest)) == REG
-	      && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1)))
-	return 1;
-    }
-  return 0;
-}
-
-/* Output the code which declares the function name.  This also handles
-   leaf routines, which have special requirements, and initializes some
-   global variables.  */
-
-void
-i960_function_name_declare (file, name, fndecl)
-     FILE *file;
-     char *name;
-     tree fndecl;
-{
-  register int i, j;
-  int leaf_proc_ok;
-  rtx insn;
-
-  /* Increment global return label.  */
-
-  ret_label++;
-
-  /* Compute whether tail calls and leaf routine optimizations can be performed
-     for this function.  */
-
-  if (TARGET_TAILCALL)
-    tail_call_ok = 1;
-  else
-    tail_call_ok = 0;
-
-  if (TARGET_LEAFPROC)
-    leaf_proc_ok = 1;
-  else
-    leaf_proc_ok = 0;
-
-  /* Even if nobody uses extra parms, can't have leafproc or tail calls if
-     argblock, because argblock uses g14 implicitly.  */
-
-  if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
-    {
-      tail_call_ok = 0;
-      leaf_proc_ok = 0;
-    }
-      
-  /* See if caller passes in an address to return value. */
-
-  if (aggregate_value_p (DECL_RESULT (fndecl)))
-    {
-      tail_call_ok = 0;
-      leaf_proc_ok = 0;
-    }
-
-  /* Can not use tail calls or make this a leaf routine if there is a non
-     zero frame size.  */
-
-  if (get_frame_size () != 0)
-    leaf_proc_ok = 0;
-
-  /* I don't understand this condition, and do not think that it is correct.
-     Apparently this is just checking whether the frame pointer is used, and
-     we can't trust regs_ever_live[fp] since it is (almost?) always set.  */
-
-  if (tail_call_ok)
-    for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-      if (GET_CODE (insn) == INSN
-	  && reg_mentioned_p (frame_pointer_rtx, insn))
-	{
-	  tail_call_ok = 0;
-	  break;
-	}
-
-  /* Check for CALL insns.  Can not be a leaf routine if there are any.  */
-
-  if (leaf_proc_ok)
-    for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-      if (GET_CODE (insn) == CALL_INSN)
-	{
-	  leaf_proc_ok = 0;
-	  break;
-	}
-
-  /* Can not be a leaf routine if any non-call clobbered registers are
-     used in this function.  */
-
-  if (leaf_proc_ok)
-    for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
-      if (regs_ever_live[i]
-	  && ((! call_used_regs[i]) || (i > 7 && i < 12)))
-	{
-	  /* Global registers.  */
-	  if (i < 16 && i > 7 && i != 13)
-	    leaf_proc_ok = 0;
-	  /* Local registers.  */
-	  else if (i < 32)
-	    leaf_proc_ok = 0;
-	}
-
-  /* Now choose a leaf return register, if we can find one, and if it is
-     OK for this to be a leaf routine.  */
-
-  i960_leaf_ret_reg = -1;
-
-  if (optimize && leaf_proc_ok)
-    {
-      for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++)
-	if (regs_ever_live[i] == 0)
-	  {
-	    i960_leaf_ret_reg = i;
-	    regs_ever_live[i] = 1;
-	    break;
-	  }
-    }
-
-  /* Do this after choosing the leaf return register, so it will be listed
-     if one was chosen.  */
-
-  fprintf (file, "\t#  Function '%s'\n", (name[0] == '*' ? &name[1] : name));
-  fprintf (file, "\t#  Registers used: ");
-
-  for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      if (regs_ever_live[i])
-	{
-	  fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*");
-
-	  if (i > 15 && j == 0)
-	    {
-	      fprintf (file,"\n\t#\t\t   ");
-	      j++;
-            }
-        }
-    }
-
-  fprintf (file, "\n");
-
-  if (i960_leaf_ret_reg >= 0)
-    {
-      /* Make it a leaf procedure.  */
-
-      if (TREE_PUBLIC (fndecl))
-	fprintf (file,"\t.globl\t%s.lf\n", (name[0] == '*' ? &name[1] : name));
-
-      fprintf (file, "\t.leafproc\t");
-      assemble_name (file, name);
-      fprintf (file, ",%s.lf\n", (name[0] == '*' ? &name[1] : name));
-      ASM_OUTPUT_LABEL (file, name);
-      fprintf (file, "\tlda    LR%d,g14\n", ret_label);
-      fprintf (file, "%s.lf:\n", (name[0] == '*' ? &name[1] : name));
-      fprintf (file, "\tmov    g14,g%d\n", i960_leaf_ret_reg);
-
-      if (TARGET_C_SERIES)
-	{
-	  fprintf (file, "\tlda    0,g14\n");
-	  i960_last_insn_type = I_TYPE_MEM;
-	}
-      else
-	{
-	  fprintf (file, "\tmov    0,g14\n");
-	  i960_last_insn_type = I_TYPE_REG;
-	}
-    }
-  else
-    {
-      ASM_OUTPUT_LABEL (file, name);
-      i960_last_insn_type = I_TYPE_CTRL; 
-    }
-}
-
-/* Compute and return the frame size.  */
-
-int
-compute_frame_size (size)
-     int size;
-{
-  int actual_fsize;
-  int outgoing_args_size = current_function_outgoing_args_size;
-
-  /* The STARTING_FRAME_OFFSET is totally hidden to us as far
-     as size is concerned.  */
-  actual_fsize = (size + 15) & -16;
-  actual_fsize += (outgoing_args_size + 15) & -16;
-
-  return actual_fsize;
-}
-
-/* Here register group is range of registers which can be moved by
-   one i960 instruction. */
-
-struct reg_group
-{
-  char start_reg;
-  char length;
-};
-
-/* The following functions forms the biggest as possible register
-   groups with registers in STATE.  REGS contain states of the
-   registers in range [start, finish_reg).  The function returns the
-   number of groups formed. */
-static int
-i960_form_reg_groups (start_reg, finish_reg, regs, state, reg_groups)
-     int start_reg;
-     int finish_reg;
-     int *regs;
-     int state;
-     struct reg_group *reg_groups;
-{
-  int i;
-  int nw = 0;
-
-  for (i = start_reg; i < finish_reg; )
-    {
-      if (regs [i] != state)
-	{
-	  i++;
-	  continue;
-	}
-      else if (i % 2 != 0 || regs [i + 1] != state)
-	reg_groups [nw].length = 1;
-      else if (i % 4 != 0 || regs [i + 2] != state)
-	reg_groups [nw].length = 2;
-      else if (regs [i + 3] != state)
-	reg_groups [nw].length = 3;
-      else
-	reg_groups [nw].length = 4;
-      reg_groups [nw].start_reg = i;
-      i += reg_groups [nw].length;
-      nw++;
-    }
-  return nw;
-}
-
-/* We sort register winodws in descending order by length. */
-static int
-i960_reg_group_compare (group1, group2)
-     void *group1;
-     void *group2;
-{
-  struct reg_group *w1 = group1;
-  struct reg_group *w2 = group2;
-
-  if (w1->length > w2->length)
-    return -1;
-  else if (w1->length < w2->length)
-    return 1;
-  else
-    return 0;
-}
-
-/* Split the first register group in REG_GROUPS on subgroups one of
-   which will contain SUBGROUP_LENGTH registers.  The function
-   returns new number of winodws. */
-static int
-i960_split_reg_group (reg_groups, nw, subgroup_length)
-     struct reg_group *reg_groups;
-     int nw;
-     int subgroup_length;
-{
-  if (subgroup_length < reg_groups->length - subgroup_length)
-    /* This guarantees correct alignments of the two subgroups for
-       i960 (see spliting for the group length 2, 3, 4).  More
-       generalized algorithm would require splitting the group more
-       two subgroups. */
-    subgroup_length = reg_groups->length - subgroup_length;
-  /* More generalized algorithm would require to try merging
-     subgroups here.  But in case i960 it always results in failure
-     because of register group alignment. */
-  reg_groups[nw].length = reg_groups->length - subgroup_length;
-  reg_groups[nw].start_reg = reg_groups->start_reg + subgroup_length;
-  nw++;
-  reg_groups->length = subgroup_length;
-  qsort (reg_groups, nw, sizeof (struct reg_group), i960_reg_group_compare);
-  return nw;
-}
-
-/* Output code for the function prologue.  */
-
-void
-i960_function_prologue (file, size)
-     FILE *file;
-     unsigned int size;
-{
-  register int i, j, nr;
-  int n_iregs = 0;
-  int rsize = 0;
-  int actual_fsize, offset;
-  int gnw, lnw;
-  struct reg_group *g, *l;
-  char tmpstr[1000];
-  /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
-     somewhere.  */
-  int regs[FIRST_PSEUDO_REGISTER];
-  /* All global registers (which must be saved) divided by groups. */
-  struct reg_group global_reg_groups [16];
-  /* All local registers (which are available) divided by groups. */
-  struct reg_group local_reg_groups [16];
-
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    if (regs_ever_live[i]
-	&& ((! call_used_regs[i]) || (i > 7 && i < 12)))
-      {
-	regs[i] = -1;
-        /* Count global registers that need saving.  */
-	if (i < 16)
-	  n_iregs++;
-      }
-    else
-      regs[i] = 0;
-
-  epilogue_string[0] = '\0';
-
-  if (profile_flag || profile_block_flag)
-    {
-      /* When profiling, we may use registers 20 to 27 to save arguments, so
-	 they can't be used here for saving globals.  J is the number of
-	 argument registers the mcount call will save.  */
-      for (j = 7; j >= 0 && ! regs_ever_live[j]; j--)
-	;
-
-      for (i = 20; i <= j + 20; i++)
-	regs[i] = -1;
-    }
-
-  gnw = i960_form_reg_groups (0, 16, regs, -1, global_reg_groups);
-  lnw = i960_form_reg_groups (19, 32, regs, 0, local_reg_groups);
-  qsort (global_reg_groups, gnw, sizeof (struct reg_group),
-	 i960_reg_group_compare);
-  qsort (local_reg_groups, lnw, sizeof (struct reg_group),
-	 i960_reg_group_compare);
-  for (g = global_reg_groups, l = local_reg_groups; lnw != 0 && gnw != 0;)
-    {
-      if (g->length == l->length)
-	{
-	  fprintf (file, "\tmov%s	%s,%s\n",
-		   ((g->length == 4) ? "q" :
-		    (g->length == 3) ? "t" :
-		    (g->length == 2) ? "l" : ""),
-		   reg_names[g->start_reg], reg_names[l->start_reg]);
-	  sprintf (tmpstr, "\tmov%s	%s,%s\n",
-		   ((g->length == 4) ? "q" :
-		    (g->length == 3) ? "t" :
-		    (g->length == 2) ? "l" : ""),
-		   reg_names[l->start_reg], reg_names[g->start_reg]);
-	  strcat (epilogue_string, tmpstr);
-	  n_iregs -= g->length;
-	  for (i = 0; i < g->length; i++)
-	    {
-	      regs [i + g->start_reg] = 1;
-	      regs [i + l->start_reg] = -1;
-	      regs_ever_live [i + l->start_reg] = 1;
-	    }
-	  g++;
-	  l++;
-	  gnw--;
-	  lnw--;
-	}
-      else if (g->length > l->length)
-	gnw = i960_split_reg_group (g, gnw, l->length);
-      else
-	lnw = i960_split_reg_group (l, lnw, g->length);
-    }
-
-  /* N_iregs is now the number of global registers that haven't been saved
-     yet.  */
-
-  rsize = (n_iregs * 4);
-  actual_fsize = compute_frame_size (size) + rsize;
-#if 0
-  /* ??? The 1.2.1 compiler does this also.  This is meant to round the frame
-     size up to the nearest multiple of 16.  I don't know whether this is
-     necessary, or even desirable.
-
-     The frame pointer must be aligned, but the call instruction takes care of
-     that.  If we leave the stack pointer unaligned, we may save a little on
-     dynamic stack allocation.  And we don't lose, at least according to the
-     i960CA manual.  */
-  actual_fsize = (actual_fsize + 15) & ~0xF;
-#endif
-
-  /* Allocate space for register save and locals.  */
-  if (actual_fsize > 0)
-    {
-      if (actual_fsize < 32)
-	fprintf (file, "\taddo	%d,sp,sp\n", actual_fsize);
-      else
-	fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize);
-    }
-
-  /* Take hardware register save area created by the call instruction
-     into account, but store them before the argument block area.  */
-  offset = 64 + actual_fsize - compute_frame_size (0) - rsize;
-  /* Save registers on stack if needed.  */
-  /* ??? Is it worth to use the same algorithm as one for saving
-     global registers in local registers? */
-  for (i = 0, j = n_iregs; j > 0 && i < 16; i++)
-    {
-      if (regs[i] != -1)
-	continue;
-
-      nr = 1;
-
-      if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0)
-	nr = 2;
-
-      if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1
-	  && offset % 4 == 0)
-	nr = 3;
-
-      if (nr == 3 && regs[i+3] == -1)
-	nr = 4;
-
-      fprintf (file,"\tst%s	%s,%d(fp)\n",
-	       ((nr == 4) ? "q" :
-		(nr == 3) ? "t" :
-		(nr == 2) ? "l" : ""),
-	       reg_names[i], offset);
-      sprintf (tmpstr,"\tld%s	%d(fp),%s\n",
-	       ((nr == 4) ? "q" :
-		(nr == 3) ? "t" :
-		(nr == 2) ? "l" : ""),
-	       offset, reg_names[i]);
-      strcat (epilogue_string, tmpstr);
-      i += nr-1;
-      j -= nr;
-      offset += nr * 4;
-    }
-
-  if (actual_fsize == 0 && size == 0 && rsize == 0)
-    return;
-
-  fprintf (file, "\t#Prologue stats:\n");
-  fprintf (file, "\t#  Total Frame Size: %d bytes\n", actual_fsize);
-
-  if (size)
-    fprintf (file, "\t#  Local Variable Size: %d bytes\n", size);
-  if (rsize)
-    fprintf (file, "\t#  Register Save Size: %d regs, %d bytes\n",
-	     n_iregs, rsize);
-  fprintf (file, "\t#End Prologue#\n");
-}
-
-/* Output code for the function profiler.  */
-
-void
-output_function_profiler (file, labelno)
-     FILE *file;
-     int labelno;
-{
-  /* The last used parameter register.  */
-  int last_parm_reg;
-  int i, j, increment;
-  int varargs_stdarg_function
-    = VARARGS_STDARG_FUNCTION (current_function_decl);
-
-  /* Figure out the last used parameter register.  The proper thing to do
-     is to walk incoming args of the function.  A function might have live
-     parameter registers even if it has no incoming args.  Note that we
-     don't have to save parameter registers g8 to g11 because they are
-     call preserved.  */
-
-  /* See also output_function_prologue, which tries to use local registers
-     for preserved call-saved global registers.  */
-
-  for (last_parm_reg = 7;
-       last_parm_reg >= 0 && ! regs_ever_live[last_parm_reg];
-       last_parm_reg--)
-    ;
-
-  /* Save parameter registers in regs r4 (20) to r11 (27).  */
-
-  for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
-    {
-      if (i % 4 == 0 && (last_parm_reg - i) >= 3)
-	increment = 4;
-      else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
-	increment = 3;
-      else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
-	increment = 2;
-      else
-	increment = 1;
-
-      fprintf (file, "\tmov%s	g%d,r%d\n",
-	       (increment == 4 ? "q" : increment == 3 ? "t"
-		: increment == 2 ? "l": ""), i, j);
-      }
-
-  /* If this function uses the arg pointer, then save it in r3 and then
-     set it to zero.  */
-
-  if (current_function_args_size != 0 || varargs_stdarg_function)
-    fprintf (file, "\tmov	g14,r3\n\tmov	0,g14\n");
-
-  /* Load location address into g0 and call mcount.  */
-
-  fprintf (file, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno);
-
-  /* If this function uses the arg pointer, restore it.  */
-
-  if (current_function_args_size != 0 || varargs_stdarg_function)
-    fprintf (file, "\tmov	r3,g14\n");
-
-  /* Restore parameter registers.  */
-
-  for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
-    {
-      if (i % 4 == 0 && (last_parm_reg - i) >= 3)
-	increment = 4;
-      else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
-	increment = 3;
-      else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
-	increment = 2;
-      else
-	increment = 1;
-
-      fprintf (file, "\tmov%s	r%d,g%d\n",
-	       (increment == 4 ? "q" : increment == 3 ? "t"
-		: increment == 2 ? "l": ""), j, i);
-    }
-}
-
-/* Output code for the function epilogue.  */
-
-void
-i960_function_epilogue (file, size)
-     FILE *file;
-     unsigned int size;
-{
-  if (i960_leaf_ret_reg >= 0)
-    {
-      fprintf (file, "LR%d:	ret\n", ret_label);
-      return;
-    }
-
-  if (*epilogue_string == 0)
-    {
-      register rtx tmp;
-	
-      /* Emit a return insn, but only if control can fall through to here.  */
-
-      tmp = get_last_insn ();
-      while (tmp)
-	{
-	  if (GET_CODE (tmp) == BARRIER)
-	    return;
-	  if (GET_CODE (tmp) == CODE_LABEL)
-	    break;
-	  if (GET_CODE (tmp) == JUMP_INSN)
-	    {
-	      if (GET_CODE (PATTERN (tmp)) == RETURN)
-		return;
-	      break;
-	    }
-	  if (GET_CODE (tmp) == NOTE)
-	    {
-	      tmp = PREV_INSN (tmp);
-	      continue;
-	    }
-	  break;
-	}
-      fprintf (file, "LR%d:	ret\n", ret_label);
-      return;
-    }
-
-  fprintf (file, "LR%d:\n", ret_label);
-
-  fprintf (file, "\t#EPILOGUE#\n");
-
-  /* Output the string created by the prologue which will restore all
-     registers saved by the prologue.  */
-
-  if (epilogue_string[0] != '\0')
-    fprintf (file, "%s", epilogue_string);
-
-  /* Must clear g14 on return if this function set it.
-     Only varargs/stdarg functions modify g14.  */
-
-  if (VARARGS_STDARG_FUNCTION (current_function_decl))
-    fprintf (file, "\tmov	0,g14\n");
-
-  fprintf (file, "\tret\n");
-  fprintf (file, "\t#End Epilogue#\n");
-}
-
-/* Output code for a call insn.  */
-
-char *
-i960_output_call_insn (target, argsize_rtx, arg_pointer, insn)
-     register rtx target, argsize_rtx, arg_pointer, insn;
-{
-  int argsize = INTVAL (argsize_rtx);
-  rtx nexti = next_real_insn (insn);
-  rtx operands[2];
-  int varargs_stdarg_function
-    = VARARGS_STDARG_FUNCTION (current_function_decl);
-
-  operands[0] = target;
-  operands[1] = arg_pointer;
-
-  if (current_function_args_size != 0 || varargs_stdarg_function)
-    output_asm_insn ("mov	g14,r3", operands);
-
-  if (argsize > 48)
-    output_asm_insn ("lda	%a1,g14", operands);
-  else if (current_function_args_size != 0 || varargs_stdarg_function)
-    output_asm_insn ("mov	0,g14", operands);
-
-  /* The code used to assume that calls to SYMBOL_REFs could not be more
-     than 24 bits away (b vs bx, callj vs callx).  This is not true.  This
-     feature is now implemented by relaxing in the GNU linker.  It can convert
-     bx to b if in range, and callx to calls/call/balx/bal as appropriate.  */
-
-  /* Nexti could be zero if the called routine is volatile.  */
-  if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok 
-      && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN))
-    {
-      /* Delete following return insn.  */
-      if (nexti && no_labels_between_p (insn, nexti))
-	delete_insn (nexti);
-      output_asm_insn ("bx	%0", operands);
-      return "# notreached";
-    }
-
-  output_asm_insn ("callx	%0", operands);
-
-  /* If the caller sets g14 to the address of the argblock, then the caller
-     must clear it after the return.  */
-
-  if (current_function_args_size != 0 || varargs_stdarg_function)
-    output_asm_insn ("mov	r3,g14", operands);
-  else if (argsize > 48)
-    output_asm_insn ("mov	0,g14", operands);
-
-  return "";
-}
-
-/* Output code for a return insn.  */
-
-char *
-i960_output_ret_insn (insn)
-     register rtx insn;
-{
-  static char lbuf[20];
-  
-  if (*epilogue_string != 0)
-    {
-      if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0)
-	return "";
-
-      sprintf (lbuf, "b	LR%d", ret_label);
-      return lbuf;
-    }
-
-  /* Must clear g14 on return if this function set it.
-     Only varargs/stdarg functions modify g14.  */
-
-  if (VARARGS_STDARG_FUNCTION (current_function_decl))
-    output_asm_insn ("mov	0,g14", 0);
-
-  if (i960_leaf_ret_reg >= 0)
-    {
-      sprintf (lbuf, "bx	(%s)", reg_names[i960_leaf_ret_reg]);
-      return lbuf;
-    }
-  return "ret";
-}
-
-#if 0
-/* Return a character string representing the branch prediction
-   opcode to be tacked on an instruction.  This must at least
-   return a null string.  */
-
-char *
-i960_br_predict_opcode (lab_ref, insn)
-     rtx lab_ref, insn;
-{
-  if (TARGET_BRANCH_PREDICT)
-    {
-      unsigned long label_uid;
-      
-      if (GET_CODE (lab_ref) == CODE_LABEL)
-	label_uid = INSN_UID (lab_ref);
-      else if (GET_CODE (lab_ref) == LABEL_REF)
-	label_uid = INSN_UID (XEXP (lab_ref, 0));
-      else
-	return ".f";
-
-      /* If not optimizing, then the insn_addresses array will not be
-	 valid.  In this case, always return ".t" since most branches
-	 are taken.  If optimizing, return .t for backward branches
-	 and .f for forward branches.  */
-      if (! optimize
-	  || insn_addresses[label_uid] < insn_addresses[INSN_UID (insn)])
-	return ".t";
-      return ".f";
-    }
-    
-  return "";
-}
-#endif
-
-/* Print the operand represented by rtx X formatted by code CODE.  */
-
-void
-i960_print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     char code;
-{
-  enum rtx_code rtxcode = GET_CODE (x);
-
-  if (rtxcode == REG)
-    {
-      switch (code)
-	{
-	case 'D':
-	  /* Second reg of a double or quad.  */
-	  fprintf (file, "%s", reg_names[REGNO (x)+1]);
-	  break;
-
-	case 'E':
-	  /* Third reg of a quad.  */
-	  fprintf (file, "%s", reg_names[REGNO (x)+2]);
-	  break;
-
-	case 'F':
-	  /* Fourth reg of a quad.  */
-	  fprintf (file, "%s", reg_names[REGNO (x)+3]);
-	  break;
-
-	case 0:
-	  fprintf (file, "%s", reg_names[REGNO (x)]);
-	  break;
-
-	default:
-	  abort ();
-	}
-      return;
-    }
-  else if (rtxcode == MEM)
-    {
-      output_address (XEXP (x, 0));
-      return;
-    }
-  else if (rtxcode == CONST_INT)
-    {
-      HOST_WIDE_INT val = INTVAL (x);
-      if (code == 'C')
-	val = ~val;
-      if (val > 9999 || val < -999)
-	fprintf (file, "0x%x", val);
-      else
-	fprintf (file, "%d", val);
-      return;
-    }
-  else if (rtxcode == CONST_DOUBLE)
-    {
-      REAL_VALUE_TYPE d;
-      char dstr[30];
-
-      if (x == CONST0_RTX (GET_MODE (x)))
-	{
-	  fprintf (file, "0f0.0");
-	  return;
-	}
-      else if (x == CONST1_RTX (GET_MODE (x)))
-	{
-	  fprintf (file, "0f1.0");
-	  return;
-	}
-
-      REAL_VALUE_FROM_CONST_DOUBLE (d, x);
-      REAL_VALUE_TO_DECIMAL (d, "%#g", dstr);
-      fprintf (file, "0f%s", dstr);
-      return;
-    }
-
-  switch(code)
-    {
-    case 'B':
-      /* Branch or jump, depending on assembler.  */
-      if (TARGET_ASM_COMPAT)
-	fputs ("j", file);
-      else
-	fputs ("b", file);
-      break;
-
-    case 'S':
-      /* Sign of condition.  */
-      if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU)
-	  || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU))
-	fputs ("o", file);
-      else if ((rtxcode == GT) || (rtxcode == LT)
-	  || (rtxcode == GE) || (rtxcode == LE))
-	fputs ("i", file);
-      else
-	abort();
-      break;
-
-    case 'I':
-      /* Inverted condition.  */
-      rtxcode = reverse_condition (rtxcode);
-      goto normal;
-
-    case 'X':
-      /* Inverted condition w/ reversed operands.  */
-      rtxcode = reverse_condition (rtxcode);
-      /* Fallthrough.  */
-
-    case 'R':
-      /* Reversed operand condition.  */
-      rtxcode = swap_condition (rtxcode);
-      /* Fallthrough.  */
-
-    case 'C':
-      /* Normal condition.  */
-    normal:
-      if (rtxcode == EQ)  { fputs ("e", file); return; }
-      else if (rtxcode == NE)  { fputs ("ne", file); return; }
-      else if (rtxcode == GT)  { fputs ("g", file); return; }
-      else if (rtxcode == GTU) { fputs ("g", file); return; }
-      else if (rtxcode == LT)  { fputs ("l", file); return; }
-      else if (rtxcode == LTU) { fputs ("l", file); return; }
-      else if (rtxcode == GE)  { fputs ("ge", file); return; }
-      else if (rtxcode == GEU) { fputs ("ge", file); return; }
-      else if (rtxcode == LE)  { fputs ("le", file); return; }
-      else if (rtxcode == LEU) { fputs ("le", file); return; }
-      else abort ();
-      break;
-
-    case 0:
-      output_addr_const (file, x);
-      break;
-
-    default:
-      abort ();
-    }
-
-  return;
-}
-
-/* Print a memory address as an operand to reference that memory location.
-
-   This is exactly the same as legitimate_address_p, except that it the prints
-   addresses instead of recognizing them.  */
-
-void
-i960_print_operand_addr (file, addr)
-     FILE *file;
-     register rtx addr;
-{
-  rtx breg, ireg;
-  rtx scale, offset;
-
-  ireg = 0;
-  breg = 0;
-  offset = 0;
-  scale = const1_rtx;
-
-  if (GET_CODE (addr) == REG)
-    breg = addr;
-  else if (CONSTANT_P (addr))
-    offset = addr;
-  else if (GET_CODE (addr) == PLUS)
-    {
-      rtx op0, op1;
-
-      op0 = XEXP (addr, 0);
-      op1 = XEXP (addr, 1);
-
-      if (GET_CODE (op0) == REG)
-	{
-	  breg = op0;
-	  if (GET_CODE (op1) == REG)
-	    ireg = op1;
-	  else if (CONSTANT_P (op1))
-	    offset = op1;
-	  else
-	    abort ();
-	}
-      else if (GET_CODE (op0) == PLUS)
-	{
-	  if (GET_CODE (XEXP (op0, 0)) == MULT)
-	    {
-	      ireg = XEXP (XEXP (op0, 0), 0);
-	      scale = XEXP (XEXP (op0, 0), 1);
-	      if (GET_CODE (XEXP (op0, 1)) == REG)
-		{
-		  breg = XEXP (op0, 1);
-		  offset = op1;
-		}
-	      else
-		abort ();
-	    }
-	  else if (GET_CODE (XEXP (op0, 0)) == REG)
-	    {
-	      breg = XEXP (op0, 0);
-	      if (GET_CODE (XEXP (op0, 1)) == REG)
-		{
-		  ireg = XEXP (op0, 1);
-		  offset = op1;
-		}
-	      else
-		abort ();
-	    }
-	  else
-	    abort ();
-	}
-      else if (GET_CODE (op0) == MULT)
-	{
-	  ireg = XEXP (op0, 0);
-	  scale = XEXP (op0, 1);
-	  if (GET_CODE (op1) == REG)
-	    breg = op1;
-	  else if (CONSTANT_P (op1))
-	    offset = op1;
-	  else
-	    abort ();
-	}
-      else
-	abort ();
-    }
-  else if (GET_CODE (addr) == MULT)
-    {
-      ireg = XEXP (addr, 0);
-      scale = XEXP (addr, 1);
-    }
-  else
-    abort ();
-
-  if (offset)
-    output_addr_const (file, offset);
-  if (breg)
-    fprintf (file, "(%s)", reg_names[REGNO (breg)]);
-  if (ireg)
-    fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale));
-}
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-	On 80960, legitimate addresses are:
-		base				ld	(g0),r0
-		disp	(12 or 32 bit)		ld	foo,r0
-		base + index			ld	(g0)[g1*1],r0
-		base + displ			ld	0xf00(g0),r0
-		base + index*scale + displ	ld	0xf00(g0)[g1*4],r0
-		index*scale + base		ld	(g0)[g1*4],r0
-		index*scale + displ		ld	0xf00[g1*4],r0
-		index*scale			ld	[g1*4],r0
-		index + base + displ		ld	0xf00(g0)[g1*1],r0
-
-	In each case, scale can be 1, 2, 4, 8, or 16.  */
-
-/* This is exactly the same as i960_print_operand_addr, except that
-   it recognizes addresses instead of printing them.
-
-   It only recognizes address in canonical form.  LEGITIMIZE_ADDRESS should
-   convert common non-canonical forms to canonical form so that they will
-   be recognized.  */
-
-/* These two macros allow us to accept either a REG or a SUBREG anyplace
-   where a register is valid.  */
-
-#define RTX_OK_FOR_BASE_P(X, STRICT)					\
-  ((GET_CODE (X) == REG							\
-    && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X)))	\
-   || (GET_CODE (X) == SUBREG						\
-       && GET_CODE (SUBREG_REG (X)) == REG				\
-       && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X))		\
-	   : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
-
-#define RTX_OK_FOR_INDEX_P(X, STRICT)					\
-  ((GET_CODE (X) == REG							\
-    && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
-   || (GET_CODE (X) == SUBREG						\
-       && GET_CODE (SUBREG_REG (X)) == REG				\
-       && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X))		\
-	   : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
-
-int
-legitimate_address_p (mode, addr, strict)
-     enum machine_mode mode;
-     register rtx addr;
-     int strict;
-{
-  if (RTX_OK_FOR_BASE_P (addr, strict))
-    return 1;
-  else if (CONSTANT_P (addr))
-    return 1;
-  else if (GET_CODE (addr) == PLUS)
-    {
-      rtx op0, op1;
-
-      if (! TARGET_COMPLEX_ADDR && ! reload_completed)
-	return 0;
-
-      op0 = XEXP (addr, 0);
-      op1 = XEXP (addr, 1);
-
-      if (RTX_OK_FOR_BASE_P (op0, strict))
-	{
-	  if (RTX_OK_FOR_INDEX_P (op1, strict))
-	    return 1;
-	  else if (CONSTANT_P (op1))
-	    return 1;
-	  else
-	    return 0;
-	}
-      else if (GET_CODE (op0) == PLUS)
-	{
-	  if (GET_CODE (XEXP (op0, 0)) == MULT)
-	    {
-	      if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0), strict)
-		     && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1))))
-		return 0;
-
-	      if (RTX_OK_FOR_BASE_P (XEXP (op0, 1), strict)
-		  && CONSTANT_P (op1))
-		return 1;
-	      else
-		return 0;
-	    }
-	  else if (RTX_OK_FOR_BASE_P (XEXP (op0, 0), strict))
-	    {
-	      if (RTX_OK_FOR_INDEX_P (XEXP (op0, 1), strict)
-		  && CONSTANT_P (op1))
-		return 1;
-	      else
-		return 0;
-	    }
-	  else
-	    return 0;
-	}
-      else if (GET_CODE (op0) == MULT)
-	{
-	  if (! (RTX_OK_FOR_INDEX_P (XEXP (op0, 0), strict)
-		 && SCALE_TERM_P (XEXP (op0, 1))))
-	    return 0;
-
-	  if (RTX_OK_FOR_BASE_P (op1, strict))
-	    return 1;
-	  else if (CONSTANT_P (op1))
-	    return 1;
-	  else
-	    return 0;
-	}
-      else
-	return 0;
-    }
-  else if (GET_CODE (addr) == MULT)
-    {
-      if (! TARGET_COMPLEX_ADDR && ! reload_completed)
-	return 0;
-
-      return (RTX_OK_FOR_INDEX_P (XEXP (addr, 0), strict)
-	      && SCALE_TERM_P (XEXP (addr, 1)));
-    }
-  else
-    return 0;
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   This converts some non-canonical addresses to canonical form so they
-   can be recognized.  */
-
-rtx
-legitimize_address (x, oldx, mode)
-     register rtx x;
-     register rtx oldx;
-     enum machine_mode mode;
-{ 
-  if (GET_CODE (x) == SYMBOL_REF)
-    {
-      abort ();
-      x = copy_to_reg (x);
-    }
-
-  if (! TARGET_COMPLEX_ADDR && ! reload_completed)
-    return x;
-
-  /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
-     into (plus (plus (mult (reg) (const)) (reg)) (const)).  This can be
-     created by virtual register instantiation, register elimination, and
-     similar optimizations.  */
-  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
-      && GET_CODE (XEXP (x, 1)) == PLUS)
-    x = gen_rtx (PLUS, Pmode,
-		 gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
-		 XEXP (XEXP (x, 1), 1));
-
-  /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
-     into (plus (plus (mult (reg) (const)) (reg)) (const)).  */
-  else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
-	   && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
-	   && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
-	   && CONSTANT_P (XEXP (x, 1)))
-    {
-      rtx constant, other;
-
-      if (GET_CODE (XEXP (x, 1)) == CONST_INT)
-	{
-	  constant = XEXP (x, 1);
-	  other = XEXP (XEXP (XEXP (x, 0), 1), 1);
-	}
-      else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
-	{
-	  constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
-	  other = XEXP (x, 1);
-	}
-      else
-	constant = 0;
-
-      if (constant)
-	x = gen_rtx (PLUS, Pmode,
-		     gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
-			      XEXP (XEXP (XEXP (x, 0), 1), 0)),
-		     plus_constant (other, INTVAL (constant)));
-    }
-
-  return x;
-}
-
-#if 0
-/* Return the most stringent alignment that we are willing to consider
-   objects of size SIZE and known alignment ALIGN as having. */
-   
-int
-i960_alignment (size, align)
-     int size;
-     int align;
-{
-  int i;
-
-  if (! TARGET_STRICT_ALIGN)
-    if (TARGET_IC_COMPAT2_0 || align >= 4)
-      {
-	i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
-	if (i > align)
-	  align = i;
-      }
-
-  return align;
-}
-#endif
-
-
-int
-hard_regno_mode_ok (regno, mode)
-     int regno;
-     enum machine_mode mode;
-{
-  if (regno < 32)
-    {
-      switch (mode)
-	{
-	case CCmode: case CC_UNSmode: case CC_CHKmode:
-	  return 0;
-
-	case DImode: case DFmode:
-	  return (regno & 1) == 0;
-
-	case TImode: case XFmode:
-	  return (regno & 3) == 0;
-
-	default:
-	  return 1;
-	}
-    }
-  else if (regno >= 32 && regno < 36)
-    {
-      switch (mode)
-	{
-	case SFmode: case DFmode: case XFmode:
-	case SCmode: case DCmode:
-	  return 1;
-
-	default:
-	  return 0;
-	}
-    }
-  else if (regno == 36)
-    {
-      switch (mode)
-	{
-	case CCmode: case CC_UNSmode: case CC_CHKmode:
-	  return 1;
-
-	default:
-	  return 0;
-	}
-    }
-  else if (regno == 37)
-    return 0;
-
-  abort ();
-}
-
-
-/* Return the minimum alignment of an expression rtx X in bytes.  This takes
-   advantage of machine specific facts, such as knowing that the frame pointer
-   is always 16 byte aligned.  */
-
-int
-i960_expr_alignment (x, size)
-     rtx x;
-     int size;
-{
-  int align = 1;
-
-  if (x == 0)
-    return 1;
-
-  switch (GET_CODE(x))
-    {
-    case CONST_INT:
-      align = INTVAL(x);
-
-      if ((align & 0xf) == 0)
-	align = 16;
-      else if ((align & 0x7) == 0)
-	align = 8;
-      else if ((align & 0x3) == 0)
-	align = 4;
-      else if ((align & 0x1) == 0)
-	align = 2;
-      else
-	align = 1;
-      break;
-
-    case PLUS:
-      align = MIN (i960_expr_alignment (XEXP (x, 0), size),
-		   i960_expr_alignment (XEXP (x, 1), size));
-      break;
-
-    case SYMBOL_REF:
-      /* If this is a valid program, objects are guaranteed to be
-	 correctly aligned for whatever size the reference actually is. */
-      align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
-      break;
-
-    case REG:
-      if (REGNO (x) == FRAME_POINTER_REGNUM)
-	align = 16;
-      break;
-
-    case ASHIFT:
-      align = i960_expr_alignment (XEXP (x, 0));
-
-      if (GET_CODE (XEXP (x, 1)) == CONST_INT)
-	{
-	  align = align << INTVAL (XEXP (x, 1));
-	  align = MIN (align, 16);
-	}
-      break;
-
-    case MULT:
-      align = (i960_expr_alignment (XEXP (x, 0), size) *
-	       i960_expr_alignment (XEXP (x, 1), size));
-
-      align = MIN (align, 16);
-      break;
-    }
-
-  return align;
-}
-
-/* Return true if it is possible to reference both BASE and OFFSET, which
-   have alignment at least as great as 4 byte, as if they had alignment valid
-   for an object of size SIZE.  */
-
-int
-i960_improve_align (base, offset, size)
-     rtx base;
-     rtx offset;
-     int size;
-{
-  int i, j;
-
-  /* We have at least a word reference to the object, so we know it has to
-     be aligned at least to 4 bytes.  */
-
-  i = MIN (i960_expr_alignment (base, 4),
-	   i960_expr_alignment (offset, 4));
-
-  i = MAX (i, 4);
-
-  /* We know the size of the request.  If strict align is not enabled, we
-     can guess that the alignment is OK for the requested size.  */
-
-  if (! TARGET_STRICT_ALIGN)
-    if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i)
-      i = j;
-
-  return (i >= size);
-}
-
-/* Return true if it is possible to access BASE and OFFSET, which have 4 byte
-   (SImode) alignment as if they had 16 byte (TImode) alignment.  */
-
-int
-i960_si_ti (base, offset)
-     rtx base;
-     rtx offset;
-{
-  return i960_improve_align (base, offset, 16);
-}
-
-/* Return true if it is possible to access BASE and OFFSET, which have 4 byte
-   (SImode) alignment as if they had 8 byte (DImode) alignment.  */
-
-int
-i960_si_di (base, offset)
-     rtx base;
-     rtx offset;
-{
-  return i960_improve_align (base, offset, 8);
-}
-
-/* Return raw values of size and alignment (in words) for the data
-   type being accessed.  These values will be rounded by the caller.  */
-
-static void 
-i960_arg_size_and_align (mode, type, size_out, align_out)
-     enum machine_mode mode;
-     tree type;
-     int *size_out;
-     int *align_out;
-{
-  int size, align;
-
-  /* Use formal alignment requirements of type being passed, except make
-     it at least a word.  If we don't have a type, this is a library call,
-     and the parm has to be of scalar type.  In this case, consider its
-     formal alignment requirement to be its size in words.  */
-
-  if (mode == BLKmode)
-    size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-  else if (mode == VOIDmode)
-    {
-      /* End of parm list.  */
-      if (type == 0 || TYPE_MODE (type) != VOIDmode)
-	abort ();
-      size = 1;
-    }
-  else
-    size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-
-  if (type == 0)
-    {
-      /* ??? This is a hack to properly correct the alignment of XFmode
-	 values without affecting anything else.  */
-      if (size == 3)
-	align = 4;
-      else
-	align = size;
-    }
-  else if (TYPE_ALIGN (type) >= BITS_PER_WORD)
-    align = TYPE_ALIGN (type) / BITS_PER_WORD;
-  else
-    align = 1;
-
-  *size_out  = size;
-  *align_out = align;
-}
-
-/* On the 80960 the first 12 args are in registers and the rest are pushed.
-   Any arg that is bigger than 4 words is placed on the stack and all
-   subsequent arguments are placed on the stack.
-
-   Additionally, parameters with an alignment requirement stronger than
-   a word must be aligned appropriately.  Note that this means that a
-   64 bit object with a 32 bit alignment is not 64 bit aligned and may be
-   passed in an odd/even register pair.  */
-
-/* Update CUM to advance past an argument described by MODE and TYPE.  */
-
-void
-i960_function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int size, align;
-
-  i960_arg_size_and_align (mode, type, &size, &align);
-
-  if (size > 4 || cum->ca_nstackparms != 0
-      || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
-      || MUST_PASS_IN_STACK (mode, type))
-    {
-      /* Indicate that all the registers are in use, even if all are not,
-	 so va_start will compute the right value.  */
-      cum->ca_nregparms = NPARM_REGS;
-      cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align) + size;
-    }
-  else
-    cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align) + size;
-}
-
-/* Return the register that the argument described by MODE and TYPE is
-   passed in, or else return 0 if it is passed on the stack.  */
-
-rtx
-i960_function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  rtx ret;
-  int size, align;
-
-  i960_arg_size_and_align (mode, type, &size, &align);
-
-  if (size > 4 || cum->ca_nstackparms != 0
-      || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
-      || MUST_PASS_IN_STACK (mode, type))
-    {
-      cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align);
-      ret = 0;
-    }
-  else
-    {
-      cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align);
-      ret = gen_rtx (REG, mode, cum->ca_nregparms);
-    }
-
-  return ret;
-}
-
-/* Floating-point support.  */
-
-void
-i960_output_long_double (file, value)
-     FILE *file;
-     REAL_VALUE_TYPE value;
-{
-  long value_long[3];
-  char dstr[30];
-
-  REAL_VALUE_TO_TARGET_LONG_DOUBLE (value, value_long);
-  REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr);
-
-  fprintf (file,
-	   "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
-	   value_long[0], dstr, value_long[1], value_long[2]);
-  fprintf (file, "\t.word\t0x0\n");
-}
-
-void
-i960_output_double (file, value)
-     FILE *file;
-     REAL_VALUE_TYPE value;
-{
-  long value_long[2];
-  char dstr[30];
-
-  REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
-  REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr);
-
-  fprintf (file, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
-	   value_long[0], dstr, value_long[1]);
-}
-  
-void
-i960_output_float (file, value)
-     FILE *file;
-     REAL_VALUE_TYPE value;
-{
-  long value_long;
-  char dstr[30];
-
-  REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
-  REAL_VALUE_TO_DECIMAL (value, "%.12g", dstr);
-
-  fprintf (file, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long, dstr);
-}
-
-/* Return the number of bits that an object of size N bytes is aligned to.  */
-
-int
-i960_object_bytes_bitalign (n)
-     int n;
-{
-  if (n > 8)      n = 128;
-  else if (n > 4) n = 64;
-  else if (n > 2) n = 32;
-  else if (n > 1) n = 16;
-  else            n = 8;
-
-  return n;
-}
-
-/* Compute the alignment for an aggregate type TSIZE.
-   Alignment is MAX (greatest member alignment,
-                     MIN (pragma align, structure size alignment)).  */
-
-int
-i960_round_align (align, tsize)
-     int align;
-     tree tsize;
-{
-  int new_align;
-
-  if (TREE_CODE (tsize) != INTEGER_CST)
-    return align;
-
-  new_align = i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize)
-					  / BITS_PER_UNIT);
-  /* Handle #pragma align.  */
-  if (new_align > i960_maxbitalignment)
-    new_align = i960_maxbitalignment;
-
-  if (align < new_align)
-    align = new_align;
-
-  return align;
-}
-
-/* Do any needed setup for a varargs function.  For the i960, we must
-   create a register parameter block if one doesn't exist, and then copy
-   all register parameters to memory.  */
-
-void
-i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int *pretend_size;
-     int no_rtl;
-{
-  /* Note: for a varargs fn with only a va_alist argument, this is 0.  */
-  int first_reg = cum->ca_nregparms;
-
-  /* Copy only unnamed register arguments to memory.  If there are
-     any stack parms, there are no unnamed arguments in registers, and
-     an argument block was already allocated by the caller.
-     Remember that any arg bigger than 4 words is passed on the stack as
-     are all subsequent args.
-
-     If there are no stack arguments but there are exactly NPARM_REGS
-     registers, either there were no extra arguments or the caller
-     allocated an argument block. */
-
-  if (cum->ca_nstackparms == 0 && first_reg < NPARM_REGS && !no_rtl)
-    {
-      rtx label = gen_label_rtx ();
-      rtx regblock;
-
-      /* If arg_pointer_rtx == 0, no arguments were passed on the stack
-	 and we need to allocate a chunk to save the registers (if any
-	 arguments were passed on the stack the caller would allocate the
-	 48 bytes as well).  We must allocate all 48 bytes (12*4) because
-	 va_start assumes it.  */
-      emit_insn (gen_cmpsi (arg_pointer_rtx, const0_rtx));
-      emit_jump_insn (gen_bne (label));
-      emit_insn (gen_rtx (SET, VOIDmode, arg_pointer_rtx,
-			  stack_pointer_rtx));
-      emit_insn (gen_rtx (SET, VOIDmode, stack_pointer_rtx,
-			  memory_address (SImode,
-					  plus_constant (stack_pointer_rtx,
-							 48))));
-      emit_label (label);
-
-      /* ??? Note that we unnecessarily store one extra register for stdarg
-	 fns.  We could optimize this, but it's kept as for now.  */
-      regblock = gen_rtx (MEM, BLKmode,
-			  plus_constant (arg_pointer_rtx,
-					 first_reg * 4));
-      move_block_from_reg (first_reg, regblock,
-			   NPARM_REGS - first_reg,
-			   (NPARM_REGS - first_reg) * UNITS_PER_WORD);
-    }
-}
-
-/* Calculate the final size of the reg parm stack space for the current
-   function, based on how many bytes would be allocated on the stack.  */
-
-int
-i960_final_reg_parm_stack_space (const_size, var_size)
-     int const_size;
-     tree var_size;
-{
-  if (var_size || const_size > 48)
-    return 48;
-  else
-    return 0;
-}
-
-/* Calculate the size of the reg parm stack space.  This is a bit complicated
-   on the i960.  */
-
-int
-i960_reg_parm_stack_space (fndecl)
-     tree fndecl;
-{
-  /* In this case, we are called from emit_library_call, and we don't need
-     to pretend we have more space for parameters than what's apparent.  */
-  if (fndecl == 0)
-    return 0;
-
-  /* In this case, we are called from locate_and_pad_parms when we're
-     not IN_REGS, so we have an arg block.  */
-  if (fndecl != current_function_decl)
-    return 48;
-
-  /* Otherwise, we have an arg block if the current function has more than
-     48 bytes of parameters.  */
-  if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
-    return 48;
-  else
-    return 0;
-}
-
-/* Return the register class of a scratch register needed to copy IN into
-   or out of a register in CLASS in MODE.  If it can be done directly,
-   NO_REGS is returned.  */
-
-enum reg_class
-secondary_reload_class (class, mode, in)
-     enum reg_class class;
-     enum machine_mode mode;
-     rtx in;
-{
-  int regno = -1;
-
-  if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
-    regno = true_regnum (in);
-
-  /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
-     LOCAL_OR_GLOBAL_REGS into anything.  */
-  if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS
-      || class == GLOBAL_REGS || (regno >= 0 && regno < 32))
-    return NO_REGS;
-
-  /* We can place any hard register, 0.0, and 1.0 into FP_REGS.  */
-  if (class == FP_REGS
-      && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
-	  || in == CONST0_RTX (mode) || in == CONST1_RTX (mode)))
-    return NO_REGS;
-
-  return LOCAL_OR_GLOBAL_REGS;
-}
-
-/* Look at the opcode P, and set i96_last_insn_type to indicate which
-   function unit it executed on.  */
-
-/* ??? This would make more sense as an attribute.  */
-
-void
-i960_scan_opcode (p)
-     char *p;
-{
-  switch (*p)
-    {
-    case 'a':
-    case 'd':
-    case 'e':
-    case 'm':
-    case 'n':
-    case 'o':
-    case 'r':
-      /* Ret is not actually of type REG, but it won't matter, because no
-	 insn will ever follow it.  */
-    case 'u':
-    case 'x':
-      i960_last_insn_type = I_TYPE_REG;
-      break;
-
-    case 'b':
-      if (p[1] == 'x' || p[3] == 'x')
-        i960_last_insn_type = I_TYPE_MEM;
-      i960_last_insn_type = I_TYPE_CTRL;
-      break;
-
-    case 'f':
-    case 't':
-      i960_last_insn_type = I_TYPE_CTRL;
-      break;
-
-    case 'c':
-      if (p[1] == 'a')
-	{
-	  if (p[4] == 'x')
-	    i960_last_insn_type = I_TYPE_MEM;
-	  else
-	    i960_last_insn_type = I_TYPE_CTRL;
-	}
-      else if (p[1] == 'm')
-	{
-	  if (p[3] == 'd')
-	    i960_last_insn_type = I_TYPE_REG;
-	  else if (p[4] == 'b' || p[4] == 'j')
-	    i960_last_insn_type = I_TYPE_CTRL;
-	  else
-	    i960_last_insn_type = I_TYPE_REG;
-	}
-      else
-        i960_last_insn_type = I_TYPE_REG;
-      break;
-
-    case 'l':
-      i960_last_insn_type = I_TYPE_MEM;
-      break;
-
-    case 's':
-      if (p[1] == 't')
-        i960_last_insn_type = I_TYPE_MEM;
-      else
-        i960_last_insn_type = I_TYPE_REG;
-      break;
-    }
-}
-
-
-/* CYGNUS LOCAL -- branch prediction */
-int
-i960_branch_predict_p (reverse, comparison, expected, value)
-     int reverse;
-     rtx comparison;
-     rtx expected;
-     rtx value;
-{
-  HOST_WIDE_INT s_exp;
-  HOST_WIDE_INT s_val;
-  unsigned HOST_WIDE_INT u_exp;
-  unsigned HOST_WIDE_INT u_val;
-  int ret = 0;
-
-  if (GET_CODE (expected) != CONST_INT || GET_CODE (value) != CONST_INT)
-    abort ();
-
-  u_exp = s_exp = INTVAL (expected);
-  u_val = s_val = INTVAL (value);
-  switch (GET_CODE (comparison)) {
-  default:
-    abort ();
-
-  case EQ:  ret = (s_exp == s_val);	break;
-  case NE:  ret = (s_exp != s_val);	break;
-  case LT:  ret = (s_exp <  s_val);	break;
-  case LE:  ret = (s_exp <= s_val);	break;
-  case GT:  ret = (s_exp >  s_val);	break;
-  case GE:  ret = (s_exp >= s_val);	break;
-  case LTU: ret = (u_exp <  u_val);	break;
-  case LEU: ret = (u_exp <= u_val);	break;
-  case GTU: ret = (u_exp >  u_val);	break;
-  case GEU: ret = (u_exp >= u_val);	break;
-  }
-
-  return ret;
-}
-/* END CYGNUS LOCAL -- branch prediction */
diff --git a/gcc/config/i960/i960.h b/gcc/config/i960/i960.h
deleted file mode 100755
index dd21ef4..0000000
--- a/gcc/config/i960/i960.h
+++ /dev/null
@@ -1,1628 +0,0 @@
-/* Definitions of target machine for GNU compiler, for Intel 80960
-   Copyright (C) 1992, 1993, 1995, 1996, 1998 Free Software Foundation, Inc.
-   Contributed by Steven McGeady, Intel Corp.
-   Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
-   Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Note that some other tm.h files may include this one and then override
-   many of the definitions that relate to assembler syntax.  */
-
-#define MULTILIB_DEFAULTS { "mnumerics" }
-
-/* Names to predefine in the preprocessor for this target machine.  */
-#define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu(i960) -Amachine(i960)"
-
-/* Name to predefine in the preprocessor for processor variations.  */
-#define	CPP_SPEC "%{mic*:-D__i960\
-			%{mka:-D__i960KA}%{mkb:-D__i960KB}\
-			%{mja:-D__i960JA}%{mjd:-D__i960JD}%{mjf:-D__i960JF}\
-			%{mrp:-D__i960RP}\
-			%{msa:-D__i960SA}%{msb:-D__i960SB}\
-			%{mmc:-D__i960MC}\
-			%{mca:-D__i960CA}%{mcc:-D__i960CC}\
-			%{mcf:-D__i960CF}}\
-	%{mka:-D__i960KA__ -D__i960_KA__}\
-	%{mkb:-D__i960KB__ -D__i960_KB__}\
-	%{msa:-D__i960SA__ -D__i960_SA__}\
-	%{msb:-D__i960SB__ -D__i960_SB__}\
-	%{mmc:-D__i960MC__ -D__i960_MC__}\
-	%{mca:-D__i960CA__ -D__i960_CA__}\
-	%{mcc:-D__i960CC__ -D__i960_CC__}\
-	%{mcf:-D__i960CF__ -D__i960_CF__}\
-	%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
-		%{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}\
-	%{mlong-double-64:-D__LONG_DOUBLE_64__}"
-
-/* -mic* options make characters signed by default.  */
-/* Use #if rather than ?: because MIPS C compiler rejects ?: in
-   initializers.  */
-#if DEFAULT_SIGNED_CHAR
-#define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
-#else
-#define SIGNED_CHAR_SPEC "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}"
-#endif
-
-/* Specs for the compiler, to handle processor variations. 
-   If the user gives an explicit -gstabs or -gcoff option, then do not
-   try to add an implicit one, as this will fail.  */
-#define CC1_SPEC \
-	"%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-mka}}}}}}}}}}}}\
-	 %{!gs*:%{!gc*:%{mbout:%{g*:-gstabs}}\
-		       %{mcoff:%{g*:-gcoff}}\
-		       %{!mbout:%{!mcoff:%{g*:-gstabs}}}}}"
-
-/* Specs for the assembler, to handle processor variations.
-   For compatibility with Intel's gnu960 tool chain, pass -A options to
-   the assembler.  */
-#define ASM_SPEC \
-	"%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
-	%{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
-        %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\
-	%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-AKB}}}}}}}}}}}}\
-	%{mlink-relax:-linkrelax}"
-
-/* Specs for the linker, to handle processor variations.
-   For compatibility with Intel's gnu960 tool chain, pass -F and -A options
-   to the linker.  */
-#define LINK_SPEC \
-	"%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
-	%{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
-        %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\
-	%{mbout:-Fbout}%{mcoff:-Fcoff}\
-	%{mlink-relax:-relax}"
-
-/* Specs for the libraries to link with, to handle processor variations.
-   Compatible with Intel's gnu960 tool chain.  */
-#define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
-	  %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"
-
-/* Show we can debug even without a frame pointer.  */
-#define CAN_DEBUG_WITHOUT_FP
-
-/* Do leaf procedure and tail call optimizations for -O2 and higher.  */
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)	\
-{						\
-  if ((LEVEL) >= 2)				\
-    {						\
-      target_flags |= TARGET_FLAG_LEAFPROC;	\
-      target_flags |= TARGET_FLAG_TAILCALL;	\
-    }						\
-}
-
-/* Print subsidiary information on the compiler version in use.  */
-#define TARGET_VERSION fprintf (stderr," (intel 80960)");
-
-/* Generate DBX debugging information.  */
-#define DBX_DEBUGGING_INFO
-
-/* Generate SDB style debugging information.  */
-#define SDB_DEBUGGING_INFO
-#define EXTENDED_SDB_BASIC_TYPES
-
-/* Generate DBX_DEBUGGING_INFO by default.  */
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* Redefine this to print in hex.  No value adjustment is necessary
-   anymore.  */
-#define PUT_SDB_TYPE(A) \
-  fprintf (asm_out_file, "\t.type\t0x%x;", A)
-
-/* Handle pragmas for compatibility with Intel's compilers.  */
-#define HANDLE_PRAGMA(GET, UNGET, NAME) process_pragma (GET, UNGET, NAME)
-extern int process_pragma ();
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-/* 960 architecture with floating-point.  */
-#define TARGET_FLAG_NUMERICS	0x01
-#define TARGET_NUMERICS		(target_flags & TARGET_FLAG_NUMERICS)
-
-/* 960 architecture with memory management.  */
-/* ??? Not used currently.  */
-#define	TARGET_FLAG_PROTECTED	0x02
-#define	TARGET_PROTECTED	(target_flags & TARGET_FLAG_PROTECTED)
-
-/* The following three are mainly used to provide a little sanity checking
-   against the -mARCH flags given. The Jx series, for the purposes of
-   gcc, is a Kx with a data cache. */
-
-/* Nonzero if we should generate code for the KA and similar processors.
-   No FPU, no microcode instructions.  */
-#define TARGET_FLAG_K_SERIES	0x04
-#define TARGET_K_SERIES		(target_flags & TARGET_FLAG_K_SERIES)
-
-/* Nonzero if we should generate code for the MC processor.
-   Not really different from KB for our purposes.  */
-#define	TARGET_FLAG_MC		0x08
-#define TARGET_MC 		(target_flags & TARGET_FLAG_MC)
-
-/* Nonzero if we should generate code for the CA processor.
-   Enables different optimization strategies.  */
-#define	TARGET_FLAG_C_SERIES	0x10
-#define	TARGET_C_SERIES 	(target_flags & TARGET_FLAG_C_SERIES)
-
-/* Nonzero if we should generate leaf-procedures when we find them.
-   You may not want to do this because leaf-proc entries are
-   slower when not entered via BAL - this would be true when
-   a linker not supporting the optimization is used.  */
-#define	TARGET_FLAG_LEAFPROC	0x20
-#define	TARGET_LEAFPROC		(target_flags & TARGET_FLAG_LEAFPROC)
-
-/* Nonzero if we should perform tail-call optimizations when we find them.
-   You may not want to do this because the detection of cases where
-   this is not valid is not totally complete.  */
-#define	TARGET_FLAG_TAILCALL	0x40
-#define	TARGET_TAILCALL		(target_flags & TARGET_FLAG_TAILCALL)
-
-/* Nonzero if use of a complex addressing mode is a win on this implementation.
-   Complex addressing modes are probably not worthwhile on the K-series,
-   but they definitely are on the C-series.  */
-#define	TARGET_FLAG_COMPLEX_ADDR 0x80
-#define	TARGET_COMPLEX_ADDR	(target_flags & TARGET_FLAG_COMPLEX_ADDR)
-
-/* Align code to 8 byte boundaries for faster fetching.  */
-#define	TARGET_FLAG_CODE_ALIGN	0x100
-#define	TARGET_CODE_ALIGN	(target_flags  & TARGET_FLAG_CODE_ALIGN)
-
-/* Append branch prediction suffixes to branch opcodes.  */
-/* ??? Not used currently.  */
-#define	TARGET_FLAG_BRANCH_PREDICT 0x200
-#define	TARGET_BRANCH_PREDICT	(target_flags  & TARGET_FLAG_BRANCH_PREDICT)
-
-/* Forces prototype and return promotions.  */
-/* ??? This does not work.  */
-#define	TARGET_FLAG_CLEAN_LINKAGE 0x400
-#define	TARGET_CLEAN_LINKAGE	(target_flags & TARGET_FLAG_CLEAN_LINKAGE)
-
-/* For compatibility with iC960 v3.0.  */
-#define	TARGET_FLAG_IC_COMPAT3_0 0x800 
-#define	TARGET_IC_COMPAT3_0	(target_flags & TARGET_FLAG_IC_COMPAT3_0)
-
-/* For compatibility with iC960 v2.0.  */
-#define	TARGET_FLAG_IC_COMPAT2_0 0x1000
-#define	TARGET_IC_COMPAT2_0	(target_flags & TARGET_FLAG_IC_COMPAT2_0)
-
-/* If no unaligned accesses are to be permitted.  */
-#define	TARGET_FLAG_STRICT_ALIGN 0x2000
-#define	TARGET_STRICT_ALIGN	(target_flags & TARGET_FLAG_STRICT_ALIGN)
-
-/* For compatibility with iC960 assembler.  */
-#define	TARGET_FLAG_ASM_COMPAT	0x4000
-#define	TARGET_ASM_COMPAT	(target_flags & TARGET_FLAG_ASM_COMPAT)
-
-/* For compatibility with the gcc960 v1.2 compiler.  Use the old structure
-   alignment rules.  Also, turns on STRICT_ALIGNMENT.  */
-#define TARGET_FLAG_OLD_ALIGN	0x8000
-#define TARGET_OLD_ALIGN	(target_flags & TARGET_FLAG_OLD_ALIGN)
-
-/* Nonzero if long doubles are to be 64 bits.  Useful for soft-float targets
-   if 80 bit long double support is missing.  */
-#define TARGET_FLAG_LONG_DOUBLE_64	0x10000
-#define TARGET_LONG_DOUBLE_64	(target_flags & TARGET_FLAG_LONG_DOUBLE_64)
-
-/* CYGNUS LOCAL -- move coalescence */
-/* Switching on move coalescence.  */
-#define TARGET_FLAG_MOVE_COALESCENCE	0x10000
-#define TARGET_MOVE_COALESCENCE	(target_flags & TARGET_FLAG_OLD_ALIGN)
-/* CYGNUS LOCAL -- move coalescence */
-
-extern int target_flags;
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-/* ??? Not all ten of these architecture variations actually exist, but I
-   am not sure which are real and which aren't.  */
-
-#define TARGET_SWITCHES  \
-  { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
-    {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
-			TARGET_FLAG_COMPLEX_ADDR)},\
-/*  {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
-			TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
-    {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
-    {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
-			TARGET_FLAG_COMPLEX_ADDR)},\
-/*  {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
-			TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
-    {"ja", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
-    {"jd", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
-    {"jf", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
-			TARGET_FLAG_COMPLEX_ADDR)},\
-    {"rp", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
-    {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
-			TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\
-    {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
-			TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
-/*  {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\
-			TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\
-    {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
-			TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
-			TARGET_FLAG_CODE_ALIGN)}, */	\
-    {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
-			TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
-    {"numerics", (TARGET_FLAG_NUMERICS)},		\
-    {"soft-float", -(TARGET_FLAG_NUMERICS)},		\
-    {"leaf-procedures", TARGET_FLAG_LEAFPROC},		\
-    {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)},	\
-    {"tail-call",TARGET_FLAG_TAILCALL},			\
-    {"no-tail-call",-(TARGET_FLAG_TAILCALL)},		\
-    {"complex-addr",TARGET_FLAG_COMPLEX_ADDR},		\
-    {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)},	\
-    {"code-align",TARGET_FLAG_CODE_ALIGN},		\
-    {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)},	\
-    {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)},	\
-    {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)},	\
-    {"ic-compat", TARGET_FLAG_IC_COMPAT2_0},		\
-    {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0},		\
-    {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0},		\
-    {"asm-compat",TARGET_FLAG_ASM_COMPAT},		\
-    {"intel-asm",TARGET_FLAG_ASM_COMPAT},		\
-    {"strict-align", TARGET_FLAG_STRICT_ALIGN},		\
-    {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)},	\
-    {"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)},	 \
-    {"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)}, \
-    {"long-double-64", TARGET_FLAG_LONG_DOUBLE_64},	\
-/* CYGNUS LOCAL -- move coalescence */\
-    {"move-coalescence", TARGET_FLAG_MOVE_COALESCENCE},	 \
-    {"no-move-coalescence", -(TARGET_FLAG_MOVE_COALESCENCE)}, \
-/* END CYGNUS LOCAL -- move coalescence */\
-    {"link-relax", 0},					\
-    {"no-link-relax", 0},				\
-    SUBTARGET_SWITCHES                                                  \
-    { "", TARGET_DEFAULT}}
-
-/* This are meant to be redefined in the host dependent files */
-#define SUBTARGET_SWITCHES
-
-/* Override conflicting target switch options.
-   Doesn't actually detect if more than one -mARCH option is given, but
-   does handle the case of two blatantly conflicting -mARCH options.  */
-#define OVERRIDE_OPTIONS					\
-{								\
-  if (TARGET_K_SERIES && TARGET_C_SERIES)			\
-    {								\
-      warning ("conflicting architectures defined - using C series", 0); \
-      target_flags &= ~TARGET_FLAG_K_SERIES;			\
-    }								\
-  if (TARGET_K_SERIES && TARGET_MC)				\
-    {								\
-      warning ("conflicting architectures defined - using K series", 0); \
-      target_flags &= ~TARGET_FLAG_MC;				\
-    }								\
-  if (TARGET_C_SERIES && TARGET_MC)				\
-    {								\
-      warning ("conflicting architectures defined - using C series", 0);\
-      target_flags &= ~TARGET_FLAG_MC;				\
-    }								\
-  if (TARGET_IC_COMPAT3_0)					\
-    {								\
-      flag_short_enums = 1;					\
-      flag_signed_char = 1;					\
-      target_flags |= TARGET_FLAG_CLEAN_LINKAGE;		\
-      if (TARGET_IC_COMPAT2_0)					\
-	{							\
-	  warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \
-	  target_flags &= ~TARGET_FLAG_IC_COMPAT2_0;		\
-	}							\
-    }								\
-  if (TARGET_IC_COMPAT2_0)					\
-    {								\
-      flag_signed_char = 1;					\
-      target_flags |= TARGET_FLAG_CLEAN_LINKAGE;		\
-    }								\
-  i960_initialize ();						\
-}
-
-/* Don't enable anything by default.  The user is expected to supply a -mARCH
-   option.  If none is given, then -mka is added by CC1_SPEC.  */
-#define TARGET_DEFAULT 0
-
-/* Target machine storage layout.  */
-
-/* Define for cross-compilation from a host with a different float format
-   or endianness, as well as to support 80 bit long doubles on the i960.  */
-#define REAL_ARITHMETIC
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.
-   The i960 case be either big endian or little endian.  We only support
-   little endian, which is the most common.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered.  */
-#define WORDS_BIG_ENDIAN 0
-
-/* Number of bits in an addressable storage unit.  */
-#define BITS_PER_UNIT 8
-
-/* Bitfields cannot cross word boundaries.  */
-#define BITFIELD_NBYTES_LIMITED 1
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.  See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Width in bits of a long double.  Define to 96, and let ROUND_TYPE_ALIGN
-   adjust the alignment for speed.  */
-#define	LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 96)
-
-/* Define this to set long double type size to use in libgcc2.c, which can
-   not depend on target_flags.  */
-#if defined(__LONG_DOUBLE_64__)
-#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
-#else
-#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
-#endif
-
-/* Allocation boundary (in *bits*) for storing pointers in memory.  */
-#define POINTER_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 128
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 128
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* This makes zero-length anonymous fields lay the next field
-   at a word boundary.  It also makes the whole struct have
-   at least word alignment if there are any bitfields at all.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* No data type wants to be aligned rounder than this.
-   Extended precision floats gets 4-word alignment.  */
-#define BIGGEST_ALIGNMENT 128
-
-/* Define this if move instructions will actually fail to work
-   when given unaligned data.
-   80960 will work even with unaligned data, but it is slow.  */
-#define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
-
-/* Specify alignment for string literals (which might be higher than the
-   base type's minimal alignment requirement.  This allows strings to be
-   aligned on word boundaries, and optimizes calls to the str* and mem*
-   library functions.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
-  (TREE_CODE (EXP) == STRING_CST	\
-   && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \
-   ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP)))	    \
-   : (ALIGN))
-
-/* Make XFmode floating point quantities be 128 bit aligned.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)					\
-  (TREE_CODE (TYPE) == ARRAY_TYPE					\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == XFmode				\
-   && (ALIGN) < 128 ? 128 : (ALIGN))
-
-/* Macros to determine size of aggregates (structures and unions
-   in C).  Normally, these may be defined to simply return the maximum
-   alignment and simple rounded-up size, but on some machines (like
-   the i960), the total size of a structure is based on a non-trivial
-   rounding method.  */
-
-#define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED)		\
-  ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode)	   \
-   ? 128  /* Put 80 bit floating point elements on 128 bit boundaries.  */ \
-   : ((!TARGET_OLD_ALIGN && !TYPE_PACKED (TYPE)				   \
-       && TREE_CODE (TYPE) == RECORD_TYPE)				   \
-      ? i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE_SIZE (TYPE)) \
-      : MAX ((COMPUTED), (SPECIFIED))))
-
-#define ROUND_TYPE_SIZE(TYPE, COMPUTED, SPECIFIED)		\
-  ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode)	\
-   ? build_int_2 (128, 0) : round_up (COMPUTED, SPECIFIED))
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   Registers 0-15 are the global registers (g0-g15).
-   Registers 16-31 are the local registers (r0-r15).
-   Register 32-35 are the fp registers (fp0-fp3).
-   Register 36 is the condition code register.
-   Register 37 is unused.  */
-
-#define FIRST_PSEUDO_REGISTER 38
-
-/* 1 for registers that have pervasive standard uses and are not available
-   for the register allocator.  On 80960, this includes the frame pointer
-   (g15), the previous FP (r0), the stack pointer (r1), the return
-   instruction pointer (r2), and the argument pointer (g14).  */
-#define FIXED_REGISTERS  \
- {0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 1, 1,	\
-  1, 1, 1, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 1, 1}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-
-/* On the 80960, note that:
-	g0..g3 are used for return values,
-	g0..g7 may always be used for parameters,
-	g8..g11 may be used for parameters, but are preserved if they aren't,
-	g12 is always preserved, but otherwise unused,
-	g13 is the struct return ptr if used, or temp, but may be trashed,
-	g14 is the leaf return ptr or the arg block ptr otherwise zero,
-		must be reset to zero before returning if it was used,
-	g15 is the frame pointer,
-	r0 is the previous FP,
-	r1 is the stack pointer,
-	r2 is the return instruction pointer,
-	r3-r15 are always available,
-	r3 is clobbered by calls in functions that use the arg pointer
-	r4-r11 may be clobbered by the mcount call when profiling
-	r4-r15 if otherwise unused may be used for preserving global registers
-	fp0..fp3 are never available.  */
-#define CALL_USED_REGISTERS  \
- {1, 1, 1, 1, 1, 1, 1, 1,	\
-  0, 0, 0, 0, 0, 1, 1, 1,	\
-  1, 1, 1, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  1, 1, 1, 1, 1, 1}
-
-/* If no fp unit, make all of the fp registers fixed so that they can't
-   be used.  */
-#define	CONDITIONAL_REGISTER_USAGE	\
-  if (! TARGET_NUMERICS) {						\
-     fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\
-  }									\
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On 80960, ordinary registers hold 32 bits worth, but can be ganged
-   together to hold double or extended precision floating point numbers,
-   and the floating point registers hold any size floating point number */
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((REGNO) < 32							\
-   ? (((MODE) == VOIDmode)					\
-      ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
-   : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On 80960, the cpu registers can hold any mode but the float registers
-   can only hold SFmode, DFmode, or XFmode.  */
-extern int hard_regno_mode_ok ();
-#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok ((REGNO), (MODE))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* 80960 pc isn't overloaded on a register that the compiler knows about.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 17
-
-/* Actual top-of-stack address is same as
-   the contents of the stack pointer register.  */
-#define STACK_POINTER_OFFSET (-current_function_outgoing_args_size)
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 15
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-/* ??? It isn't clear to me why this is here.  Perhaps because of a bug (since
-   fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have
-   caused this to fail.  */
-#define FRAME_POINTER_REQUIRED (! leaf_function_p ())
-
-/* C statement to store the difference between the frame pointer
-   and the stack pointer values immediately after the function prologue.
-
-   Since the stack grows upward on the i960, this must be a negative number.
-   This includes the 64 byte hardware register save area and the size of
-   the frame.  */
-
-#define INITIAL_FRAME_POINTER_OFFSET(VAR) \
-  do { (VAR) = - (64 + compute_frame_size (get_frame_size ())); } while (0)
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 14
-
-/* Register in which static-chain is passed to a function.
-   On i960, we use r3.  */
-#define STATIC_CHAIN_REGNUM 19
- 
-/* Functions which return large structures get the address
-   to place the wanted value at in g13.  */
-
-#define STRUCT_VALUE_REGNUM 13 
-
-/* The order in which to allocate registers.  */
-
-#define	REG_ALLOC_ORDER	\
-{  4, 5, 6, 7, 0, 1, 2, 3, 13,	 /* g4, g5, g6, g7, g0, g1, g2, g3, g13  */ \
-  20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11  */    \
-  28, 29, 30, 31, 19, 8, 9, 10,	 /* r12, r13, r14, r15, r3, g8, g9, g10  */ \
-  11, 12,			 /* g11, g12  */			    \
-  32, 33, 34, 35,		 /* fp0, fp1, fp2, fp3  */		    \
-  /* We can't actually allocate these.  */				    \
-  16, 17, 18, 14, 15, 36, 37}	 /* r0, r1, r2, g14, g15, cc  */
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-/* The 80960 has four kinds of registers, global, local, floating point,
-   and condition code.  The cc register is never allocated, so no class
-   needs to be defined for it.  */
-
-enum reg_class { NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS,
-  FP_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-/* 'r' includes floating point registers if TARGET_NUMERICS.  'd' never
-   does.  */
-#define	GENERAL_REGS	((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS)
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.  */
-
-#define REG_CLASS_NAMES							\
-{ "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS",	\
-  "FP_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS	\
-{ {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO)	\
-  ((REGNO) < 16 ? GLOBAL_REGS	\
-   : (REGNO) < 32 ? LOCAL_REGS	\
-   : (REGNO) < 36 ? FP_REGS	\
-   : NO_REGS)
-
-/* The class value for index registers, and the one for base regs.
-   There is currently no difference between base and index registers on the
-   i960, but this distinction may one day be useful.  */
-#define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS
-#define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.
-   'f' is a floating point register (fp0..fp3)
-   'l' is a local register (r0-r15)
-   'b' is a global register (g0-g15)
-   'd' is any local or global register
-   'r' or 'g' are pre-defined to the class GENERAL_REGS.  */
-/* 'l' and 'b' are probably never used.  Note that 'd' and 'r' are *not*
-   the same thing, since 'r' may include the fp registers.  */
-#define REG_CLASS_FROM_LETTER(C) \
-  (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \
-    (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS)))
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   For 80960:
-	'I' is used for literal values 0..31
-   	'J' means literal 0
-	'K' means 0..-31.  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  				\
-  ((C) == 'I' ? (((unsigned) (VALUE)) <= 31)				\
-   : (C) == 'J' ? ((VALUE) == 0)					\
-   : (C) == 'K' ? ((VALUE) >= -31 && (VALUE) <= 0)			\
-   : (C) == 'M' ? ((VALUE) >= -32 && (VALUE) <= 0)			\
-   : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.
-   For the 80960, G is 0.0 and H is 1.0.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)				\
-  ((TARGET_NUMERICS) &&							\
-   (((C) == 'G' && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))		\
-    || ((C) == 'H' && ((VALUE) == CONST1_RTX (GET_MODE (VALUE))))))
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-/* On 960, can't load constant into floating-point reg except
-   0.0 or 1.0.
-
-   Any hard reg is ok as a src operand of a reload insn.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)			\
-  (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER	\
-   ? (CLASS)							\
-   : ((CLASS) == FP_REGS && CONSTANT_P (X)			\
-      && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\
-      && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\
-      ? NO_REGS							\
-      : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS)))
-
-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
-  secondary_reload_class (CLASS, MODE, IN)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-/* On 80960, this is the size of MODE in words,
-   except in the FP regs, where a single reg is always enough.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)					\
-  ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE)))
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* CYGNUS LOCAL -- move coalescence */
-/* Initialize data used by insn expanders.  This is called from
-   init_emit, once for each function, before code is generated. */
-#define INIT_EXPANDERS i960_init_expanders ()
-
-extern void i960_init_expanders ();
-/* END CYGNUS LOCAL -- move coalescence */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-/* #define STACK_GROWS_DOWNWARD */
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-/* #define FRAME_GROWS_DOWNWARD */
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.
-
-   The i960 has a 64 byte register save area, plus possibly some extra
-   bytes allocated for varargs functions.  */
-#define STARTING_FRAME_OFFSET 64
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On 80960, don't define this because there are no push insns.  */
-/* #define PUSH_ROUNDING(BYTES) BYTES */
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* When a parameter is passed in a register, no stack space is
-   allocated for it.  However, when args are passed in the
-   stack, space is allocated for every register parameter.  */
-#define MAYBE_REG_PARM_STACK_SPACE 48
-#define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE)	\
-  i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE);
-#define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL)
-#define OUTGOING_REG_PARM_STACK_SPACE
-
-/* Keep the stack pointer constant throughout the function.  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Value is 1 if returning from a function call automatically
-   pops the arguments described by the number-of-args field in the call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0)
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.
-   On 80960, returns are in g0..g3 */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-/* 1 if N is a possible register number for function argument passing.
-   On 80960, parameters are passed in g0..g11 */
-
-#define FUNCTION_ARG_REGNO_P(N) ((N) < 12)
-
-/* Perform any needed actions needed for a function that is receiving a
-   variable number of arguments. 
-
-   CUM is as above.
-
-   MODE and TYPE are the mode and type of the current parameter.
-
-   PRETEND_SIZE is a variable that should be set to the amount of stack
-   that must be pushed by the prolog to pretend that our caller pushed
-   it.
-
-   Normally, this macro will push all remaining incoming registers on the
-   stack and set PRETEND_SIZE to the length of the registers pushed.  */
-
-#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
-  i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL)
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On 80960, this is two integers, which count the number of register
-   parameters and the number of stack parameters seen so far.  */
-
-struct cum_args { int ca_nregparms; int ca_nstackparms; };
-
-#define CUMULATIVE_ARGS struct cum_args
-
-/* Define the number of registers that can hold parameters.
-   This macro is used only in macro definitions below and/or i960.c.  */
-#define NPARM_REGS 12
-
-/* Define how to round to the next parameter boundary.
-   This macro is used only in macro definitions below and/or i960.c.  */
-#define ROUND_PARM(X, MULTIPLE_OF)	\
-  ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF)
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On 80960, the offset always starts at 0; the first parm reg is g0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
-  ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   CUM should be advanced to align with the data type accessed and
-   also the size of that data type in # of regs.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
-  i960_function_arg_advance(&CUM, MODE, TYPE, NAMED)
-
-/* Indicate the alignment boundary for an argument of the specified mode and
-   type.  */
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE)				\
-  (((TYPE) != 0)							\
-   ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY)				\
-      ? PARM_BOUNDARY							\
-      : TYPE_ALIGN (TYPE))						\
-   : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY)			\
-      ? PARM_BOUNDARY							\
-      : GET_MODE_ALIGNMENT (MODE)))
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-extern struct rtx_def *i960_function_arg ();
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)	\
-  i960_function_arg(&CUM, MODE, TYPE, NAMED)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-#define FUNCTION_VALUE(TYPE, FUNC) \
-  gen_rtx (REG, TYPE_MODE (TYPE), 0)
-
-/* Force aggregates and objects larger than 16 bytes to be returned in memory,
-   since we only have 4 registers available for return values.  */
-
-#define RETURN_IN_MEMORY(TYPE) \
-  (TYPE_MODE (TYPE) == BLKmode || int_size_in_bytes (TYPE) > 16)
-
-/* Don't default to pcc-struct-return, because we have already specified
-   exactly how to return structures in the RETURN_IN_MEMORY macro.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   This never happens on 80960.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
-/* Output the label for a function definition.
-  This handles leaf functions and a few other things for the i960.  */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)	\
-  i960_function_name_declare (FILE, NAME, DECL)
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE))
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)	\
-  output_function_profiler ((FILE), (LABELNO));
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define	EXIT_IGNORE_STACK 1
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE)
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-  ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-  ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
-#define REGNO_OK_FOR_FP_P(REGNO) \
-  ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36)
-
-/* Now macros that check whether X is a register and also,
-   strictly, whether it is in a specified class.
-
-   These macros are specific to the 960, and may be used only
-   in code for printing assembler insns and in conditions for
-   define_optimization.  */
-
-/* 1 if X is an fp register.  */
-
-#define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-#define	MAX_REGS_PER_ADDRESS 2
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* LEGITIMATE_CONSTANT_P is nonzero if the constant value X
-   is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P.
-
-   Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0.
-
-   ??? This probably should be defined to 1.  */
-
-#define LEGITIMATE_CONSTANT_P(X) \
-  ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), GET_MODE (X)))
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) \
-  (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-  (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-
-#define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-#define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-	On 80960, legitimate addresses are:
-		base				ld	(g0),r0
-		disp	(12 or 32 bit)		ld	foo,r0
-		base + index			ld	(g0)[g1*1],r0
-		base + displ			ld	0xf00(g0),r0
-		base + index*scale + displ	ld	0xf00(g0)[g1*4],r0
-		index*scale + base		ld	(g0)[g1*4],r0
-		index*scale + displ		ld	0xf00[g1*4],r0
-		index*scale			ld	[g1*4],r0
-		index + base + displ		ld	0xf00(g0)[g1*1],r0
-
-	In each case, scale can be 1, 2, 4, 8, or 16.  */
-
-/* Returns 1 if the scale factor of an index term is valid. */
-#define SCALE_TERM_P(X)							\
-  (GET_CODE (X) == CONST_INT						\
-   && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 		\
-       || INTVAL(X) == 8 || INTVAL (X) == 16))
-
-
-#ifdef REG_OK_STRICT
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-  { if (legitimate_address_p (MODE, X, 1)) goto ADDR; }
-#else
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-  { if (legitimate_address_p (MODE, X, 0)) goto ADDR; }
-#endif
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.  */
-
-/* On 80960, convert non-canonical addresses to canonical form.  */
-
-extern struct rtx_def *legitimize_address ();
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)	\
-{ rtx orig_x = (X);				\
-  (X) = legitimize_address (X, OLDX, MODE);	\
-  if ((X) != orig_x && memory_address_p (MODE, X)) \
-    goto WIN; }
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the 960 this is never true.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* Allow and ignore #sccs directives.  */
-#define	SCCS_DIRECTIVE
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 16
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.  */
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* Nonzero if access to memory by bytes is no faster than for words.
-   Value changed to 1 after reports of poor bitfield code with g++.
-   Indications are that code is usually as good, sometimes better. */   
-
-#define SLOW_BYTE_ACCESS 1
-
-/* Force sizeof(bool) == 1 to maintain binary compatibility; otherwise, the
-   change in SLOW_BYTE_ACCESS would have changed it to 4.  */
-
-#define BOOL_TYPE_SIZE CHAR_TYPE_SIZE
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
-   few bits. */
-#define SHIFT_COUNT_TRUNCATED 0
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* Specify the widest mode that BLKmode objects can be promoted to */
-#define	MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
-
-/* These global variables are used to pass information between
-   cc setter and cc user at insn emit time.  */
-
-extern struct rtx_def *i960_compare_op0, *i960_compare_op1;
-
-/* Define the function that build the compare insn for scc and bcc.  */
-
-extern struct rtx_def *gen_compare_reg ();
-
-/* Add any extra modes needed to represent the condition code.
-
-   Also, signed and unsigned comparisons are distinguished, as
-   are operations which are compatible with chkbit insns.  */
-#define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode
-
-/* Define the names for the modes specified above.  */
-#define EXTRA_CC_NAMES "CC_UNS", "CC_CHK"
-
-/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
-   return the mode to be used for the comparison.  For floating-point, CCFPmode
-   should be used.  CC_NOOVmode should be used when the first operand is a
-   PLUS, MINUS, or NEG.  CCmode should be used when no special processing is
-   needed.  */
-#define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X)
-
-/* A function address in a call instruction is a byte address
-   (for indexing purposes) so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE SImode
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.  */
-#define NO_FUNCTION_CSE
-
-/* Use memcpy, etc. instead of bcopy.  */
-
-#ifndef WIND_RIVER
-#define	TARGET_MEM_FUNCTIONS	1
-#endif
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-/* Constants that can be (non-ldconst) insn operands are cost 0.  Constants
-   that can be non-ldconst operands in rare cases are cost 1.  Other constants
-   have higher costs.  */
-
-/* Must check for OUTER_CODE of SET for power2_operand, because
-   reload_cse_move2add calls us with OUTER_CODE of PLUS to decide when
-   to replace set with add.  */
-
-#define CONST_COSTS(RTX, CODE, OUTER_CODE)				\
-  case CONST_INT:							\
-    if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32)			\
-	|| (OUTER_CODE == SET && power2_operand (RTX, VOIDmode)))	\
-      return 0; 							\
-    else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0)			\
-      return 1;								\
-  case CONST:								\
-  case LABEL_REF:							\
-  case SYMBOL_REF:							\
-    return (TARGET_C_SERIES ? 6 : 8);					\
-  case CONST_DOUBLE:							\
-    if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode)	\
-	|| (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\
-      return 1;								\
-    return 12;
-
-/* The i960 offers addressing modes which are "as cheap as a register".
-   See i960.c (or gcc.texinfo) for details.  */
-
-#define ADDRESS_COST(RTX) \
-  (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX))
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(file)
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES {						\
-	"g0", "g1", "g2",  "g3",  "g4",  "g5",  "g6",  "g7",		\
-	"g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp",		\
-	"pfp","sp", "rip", "r3",  "r4",  "r5",  "r6",  "r7",		\
-	"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",		\
-	"fp0","fp1","fp2", "fp3", "cc", "fake" }
-
-/* How to renumber registers for dbx and gdb.
-   In the 960 encoding, g0..g15 are registers 16..31.  */
-
-#define DBX_REGISTER_NUMBER(REGNO)					\
-  (((REGNO) < 16) ? (REGNO) + 16					\
-   : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16))
-
-/* Don't emit dbx records longer than this.  This is an arbitrary value.  */
-#define DBX_CONTIN_LENGTH 1500
-
-/* This is how to output a note to DBX telling it the line number
-   to which the following sequence of instructions corresponds. */
-
-#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE)			\
-{ if (write_symbols == SDB_DEBUG) {				\
-    fprintf ((FILE), "\t.ln	%d\n",				\
-	     (sdb_begin_function_line				\
-	      ? (LINE) - sdb_begin_function_line : 1));		\
-  } else if (write_symbols == DBX_DEBUG) {			\
-	fprintf((FILE),"\t.stabd	68,0,%d\n",(LINE));	\
-  } }
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)		\
-{ fputs ("\t.globl ", FILE);			\
-  assemble_name (FILE, NAME);			\
-  fputs ("\n", FILE); }
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `long double'
-   constant.  */
-
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) i960_output_long_double(FILE, VALUE)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  i960_output_double(FILE, VALUE)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  i960_output_float(FILE, VALUE)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.short "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)	\
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.word L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line that says to advance the
-   location counter to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  fprintf (FILE, "\t.align %d\n", (LOG))
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %d\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-/* For common objects, output unpadded size... gld960 & lnk960 both
-   have code to align each common object at link time.  Also, if size
-   is 0, treat this as a declaration, not a definition - i.e.,
-   do nothing at all.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)	\
-{ if ((SIZE) != 0)					\
-    {							\
-      fputs (".globl ", (FILE)),			\
-      assemble_name ((FILE), (NAME)),			\
-      fputs ("\n.comm ", (FILE)),			\
-      assemble_name ((FILE), (NAME)),			\
-      fprintf ((FILE), ",%d\n", (SIZE));		\
-    }							\
-}
-
-/* This says how to output an assembler line to define a local common symbol.
-   Output unpadded size, with request to linker to align as requested.
-   0 size should not be possible here.  */
-
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)  \
-( fputs (".bss\t", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%d,%d\n", (SIZE),		\
-	   (floor_log2 ((ALIGN) / BITS_PER_UNIT))))
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of uninitialized global DECL named
-   NAME whose size is SIZE bytes and alignment is ALIGN bytes.
-   Try to use asm_output_aligned_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN)	\
-  do {								\
-    fputs (".globl ", (FILE));					\
-    assemble_name ((FILE), (NAME));				\
-    fputs ("\n", (FILE));					\
-    ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN);		\
-  } while (0)
-
-/* Output text for an #ident directive.  */
-#define	ASM_OUTPUT_IDENT(FILE, STR)  fprintf(FILE, "\t# %s\n", STR);
-
-/* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true.  */
-
-#define	LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_CODE_ALIGN ? 3 : 0)
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-	( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-	  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL	007
-#define TARGET_BS	010
-#define TARGET_TAB	011
-#define TARGET_NEWLINE	012
-#define TARGET_VT	013
-#define TARGET_FF	014
-#define TARGET_CR	015
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.  */
-
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
-{ fprintf (FILE, "\tld	LPBX0,g12\n");			\
-  fprintf (FILE, "\tcmpobne	0,g12,LPY%d\n",LABELNO);\
-  fprintf (FILE, "\tlda	LPBX0,g12\n");			\
-  fprintf (FILE, "\tcall	___bb_init_func\n");	\
-  fprintf (FILE, "LPY%d:\n",LABELNO); }
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  */
-
-#define BLOCK_PROFILER(FILE, BLOCKNO) \
-{ int blockn = (BLOCKNO);				\
-  fprintf (FILE, "\tld	LPBX2+%d,g12\n", 4 * blockn);	\
-  fprintf (FILE, "\taddo	g12,1,g12\n");		\
-  fprintf (FILE, "\tst	g12,LPBX2+%d\n", 4 * blockn); }
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-  i960_print_operand (FILE, X, CODE);
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)	\
-  i960_print_operand_addr (FILE, ADDR)
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  */
-
-/* On the i960, the trampoline contains three instructions:
-     ldconst _function, r4
-     ldconst static addr, r3
-     jump (r4)  */
-
-#define TRAMPOLINE_TEMPLATE(FILE)					\
-{									\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0x8C203000));	\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0x00000000));	\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0x8C183000));	\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0x00000000));	\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0x84212000));	\
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 20
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)),	\
-		  FNADDR);						\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)),	\
-		  CXT);							\
-}
-
-/* Generate RTL to flush the register windows so as to make arbitrary frames
-   available.  */
-#define SETUP_FRAME_ADDRESSES()		\
-  emit_insn (gen_flush_register_windows ())
-
-#define BUILTIN_SETJMP_FRAME_VALUE hard_frame_pointer_rtx
-
-#if 0
-/* Promote char and short arguments to ints, when want compatibility with
-   the iC960 compilers.  */
-
-/* ??? In order for this to work, all users would need to be changed
-   to test the value of the macro at run time.  */
-#define PROMOTE_PROTOTYPES	TARGET_CLEAN_LINKAGE
-/* ??? This does not exist.  */
-#define PROMOTE_RETURN		TARGET_CLEAN_LINKAGE
-#endif
-
-/* Instruction type definitions.  Used to alternate instructions types for
-   better performance on the C series chips.  */
-
-enum insn_types { I_TYPE_REG, I_TYPE_MEM, I_TYPE_CTRL };
-
-/* Holds the insn type of the last insn output to the assembly file.  */
-
-extern enum insn_types i960_last_insn_type;
-
-/* Parse opcodes, and set the insn last insn type based on them.  */
-
-#define ASM_OUTPUT_OPCODE(FILE, INSN)	i960_scan_opcode (INSN)
-
-/* Table listing what rtl codes each predicate in i960.c will accept.  */
-
-#define PREDICATE_CODES \
-  {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF,	\
-			  LABEL_REF, SUBREG, REG, MEM}},		\
-  {"arith_operand", {SUBREG, REG, CONST_INT}},				\
-  {"logic_operand", {SUBREG, REG, CONST_INT}},				\
-  {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}},			\
-  {"signed_arith_operand", {SUBREG, REG, CONST_INT}},			\
-  {"literal", {CONST_INT}},						\
-  {"fp_literal_one", {CONST_DOUBLE}},					\
-  {"fp_literal_double", {CONST_DOUBLE}},				\
-  {"fp_literal", {CONST_DOUBLE}},					\
-  {"signed_literal", {CONST_INT}},					\
-  {"symbolic_memory_operand", {SUBREG, MEM}},				\
-  {"eq_or_neq", {EQ, NE}},						\
-  {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT,	\
-		       CONST_DOUBLE, CONST}},				\
-  {"power2_operand", {CONST_INT}},					\
-  {"cmplpower2_operand", {CONST_INT}},
-
-/* Define functions in i960.c and used in insn-output.c.  */
-
-extern char *i960_output_ldconst ();
-extern char *i960_output_call_insn ();
-extern char *i960_output_ret_insn ();
-extern char *i960_output_move_double ();
-extern char *i960_output_move_double_zero ();
-extern char *i960_output_move_quad ();
-extern char *i960_output_move_quad_zero ();
-
-/* Defined in reload.c, and used in insn-recog.c.  */
-
-extern int rtx_equal_function_value_matters;
-
-/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
-   Used for C++ multiple inheritance.  */
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION)	\
-do {									\
-  int d = (DELTA);							\
-  if (d < 0 && d > -32)							\
-    fprintf (FILE, "\tsubo %d,g0,g0\n", -d);				\
-  else if (d > 0 && d < 32)						\
-    fprintf (FILE, "\taddo %d,g0,g0\n", d);				\
-  else									\
-    {									\
-      fprintf (FILE, "\tldconst %d,r5\n", d);				\
-      fprintf (FILE, "\taddo r5,g0,g0\n");				\
-    }									\
-  fprintf (FILE, "\tbx ");						\
-  assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0));	\
-  fprintf (FILE, "\n");							\
-} while (0);
diff --git a/gcc/config/i960/i960.md b/gcc/config/i960/i960.md
deleted file mode 100755
index 3c34622..0000000
--- a/gcc/config/i960/i960.md
+++ /dev/null
@@ -1,2933 +0,0 @@
-;;- Machine description for Intel 80960 chip for GNU C compiler
-;;   Copyright (C) 1992, 1995, 1998 Free Software Foundation, Inc.
-;;   Contributed by Steven McGeady, Intel Corp.
-;;   Additional work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
-;;   Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; There are very few (4) 'f' registers, they can't be loaded/stored from/to
-;; memory, and some instructions explicitly require them, so we get better
-;; code by discouraging pseudo-registers from being allocated to them.
-;; However, we do want to allow all patterns which can store to them to
-;; include them in their constraints, so we always use '*f' in a destination
-;; constraint except when 'f' is the only alternative.
-
-;; Insn attributes which describe the i960.
-
-;; Modscan is not used, since the compiler never emits any of these insns.
-(define_attr "type"
-  "move,arith,alu2,mult,div,modscan,load,store,branch,call,address,compare,fpload,fpstore,fpmove,fpcvt,fpcc,fpadd,fpmul,fpdiv,multi,misc"
-  (const_string "arith"))
-
-;; Length (in # of insns).
-(define_attr "length" ""
-  (cond [(eq_attr "type" "load,fpload")
-	      (if_then_else (match_operand 1 "symbolic_memory_operand" "")
-			    (const_int 2)
-			    (const_int 1))
-	 (eq_attr "type" "store,fpstore")
-	      (if_then_else (match_operand 0 "symbolic_memory_operand" "")
-			    (const_int 2)
-			    (const_int 1))
-	 (eq_attr "type" "address")
-	      (const_int 2)]
-	(const_int 1)))
-
-(define_asm_attributes
-  [(set_attr "length" "1")
-   (set_attr "type" "multi")])
-
-;; (define_function_unit {name} {num-units} {n-users} {test}
-;;                       {ready-delay} {issue-delay} [{conflict-list}])
-
-;; The integer ALU
-(define_function_unit "alu" 2 0 (eq_attr "type" "arith,compare,move,address") 1 0)
-(define_function_unit "alu" 2 0 (eq_attr "type" "alu2") 2 0)
-(define_function_unit "alu" 2 0 (eq_attr "type" "mult") 5 0)
-(define_function_unit "alu" 2 0 (eq_attr "type" "div") 35 0)
-(define_function_unit "alu" 2 0 (eq_attr "type" "modscan") 3 0)
-
-;; Memory with load-delay of 1 (i.e., 2 cycle load).
-(define_function_unit "memory" 1 0 (eq_attr "type" "load,fpload") 2 0)
-
-;; Floating point operations.
-(define_function_unit "fp" 1 2 (eq_attr "type" "fpmove") 5 0)
-(define_function_unit "fp" 1 2 (eq_attr "type" "fpcvt") 35 0)
-(define_function_unit "fp" 1 2 (eq_attr "type" "fpcc") 10 0)
-(define_function_unit "fp" 1 2 (eq_attr "type" "fpadd") 10 0)
-(define_function_unit "fp" 1 2 (eq_attr "type" "fpmul") 20 0)
-(define_function_unit "fp" 1 2 (eq_attr "type" "fpdiv") 35 0)
-
-;; Compare instructions.
-;; This controls RTL generation and register allocation.
-
-;; We generate RTL for comparisons and branches by having the cmpxx 
-;; patterns store away the operands.  Then, the scc and bcc patterns
-;; emit RTL for both the compare and the branch.
-;;
-;; We start with the DEFINE_EXPANDs, then DEFINE_INSNs to match
-;; the patterns.  Finally, we have the DEFINE_SPLITs for some of the scc
-;; insns that actually require more than one machine instruction.
-
-;; Put cmpsi first because it is expected to be the most common.
-
-(define_expand "cmpsi"
-  [(set (reg:CC 36)
-	(compare:CC (match_operand:SI 0 "nonimmediate_operand" "")
-		    (match_operand:SI 1 "general_operand" "")))]
-  ""
-  "
-{
-  i960_compare_op0 = operands[0];
-  i960_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "cmpdf"
-  [(set (reg:CC 36)
-	(compare:CC (match_operand:DF 0 "register_operand" "r")
-		    (match_operand:DF 1 "nonmemory_operand" "rGH")))]
-  "TARGET_NUMERICS"
-  "
-{
-  i960_compare_op0 = operands[0];
-  i960_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "cmpsf"
-  [(set (reg:CC 36)
-	(compare:CC (match_operand:SF 0 "register_operand" "r")
-		    (match_operand:SF 1 "nonmemory_operand" "rGH")))]
-  "TARGET_NUMERICS"
-  "
-{
-  i960_compare_op0 = operands[0];
-  i960_compare_op1 = operands[1];
-  DONE;
-}")
-
-;; Now the DEFINE_INSNs for the compare and scc cases.  First the compares.
-
-(define_insn ""
-  [(set (reg:CC 36)
-	(compare:CC (match_operand:SI 0 "register_operand" "d")
-		    (match_operand:SI 1 "arith_operand" "dI")))]
-  ""
-  "cmpi	%0,%1"
-  [(set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (reg:CC_UNS 36)
-	(compare:CC_UNS (match_operand:SI 0 "register_operand" "d")
-			(match_operand:SI 1 "arith_operand" "dI")))]
-  ""
-  "cmpo	%0,%1"
-  [(set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (reg:CC 36)
-	(compare:CC (match_operand:DF 0 "register_operand" "r")
-		    (match_operand:DF 1 "nonmemory_operand" "rGH")))]
-  "TARGET_NUMERICS"
-  "cmprl %0,%1"
-  [(set_attr "type" "fpcc")])
-
-(define_insn ""
-  [(set (reg:CC 36)
-	(compare:CC (match_operand:SF 0 "register_operand" "r")
-		    (match_operand:SF 1 "nonmemory_operand" "rGH")))]
-  "TARGET_NUMERICS"
-  "cmpr %0,%1"
-  [(set_attr "type" "fpcc")])
-
-;; Instruction definitions for branch-on-bit-set and clear insns.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
-			      (const_int 1)
-			      (match_operand:SI 2 "arith_operand" "dI"))
-	     (const_int 0))
-	 (label_ref (match_operand 3 "" ""))
-	 (pc)))]
-  ""
-  "bbs	%2,%1,%l3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
-			      (const_int 1)
-			      (match_operand:SI 2 "arith_operand" "dI"))
-	     (const_int 0))
-	 (label_ref (match_operand 3 "" ""))
-	 (pc)))]
-  ""
-  "bbc	%2,%1,%l3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
-			      (const_int 1)
-			      (match_operand:SI 2 "arith_operand" "dI"))
-	     (const_int 0))
-	 (label_ref (match_operand 3 "" ""))
-	 (pc)))]
-  ""
-  "bbs	%2,%1,%l3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
-			      (const_int 1)
-			      (match_operand:SI 2 "arith_operand" "dI"))
-	     (const_int 0))
-	 (label_ref (match_operand 3 "" ""))
-	 (pc)))]
-  ""
-  "bbc	%2,%1,%l3"
-  [(set_attr "type" "branch")])
-
-;; ??? These will never match.  The LOG_LINKs necessary to make these match
-;; are not created by flow.  These remain as a reminder to make this work
-;; some day.
-
-(define_insn ""
-  [(set (reg:CC 36)
-	(compare (match_operand:SI 0 "arith_operand" "d")
-		 (match_operand:SI 1 "arith_operand" "d")))
-   (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))]
-  "0"
-  "cmpinci	%0,%1"
-  [(set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (reg:CC_UNS 36)
-	(compare (match_operand:SI 0 "arith_operand" "d")
-		 (match_operand:SI 1 "arith_operand" "d")))
-   (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))]
-  "0"
-  "cmpinco	%0,%1"
-  [(set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (reg:CC 36)
-	(compare (match_operand:SI 0 "arith_operand" "d")
-		 (match_operand:SI 1 "arith_operand" "d")))
-   (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))]
-  "0"
-  "cmpdeci	%0,%1"
-  [(set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (reg:CC_UNS 36)
-	(compare (match_operand:SI 0 "arith_operand" "d")
-		 (match_operand:SI 1 "arith_operand" "d")))
-   (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))]
-  "0"
-  "cmpdeco	%0,%1"
-  [(set_attr "type" "compare")])
-
-;; Templates to store result of condition.
-;; '1' is stored if condition is true.
-;; '0' is stored if condition is false.
-;; These should use predicate "general_operand", since
-;; gcc seems to be creating mem references which use these
-;; templates.
-
-(define_expand "seq"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(eq:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1);
-}")
-
-(define_expand "sne"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(ne:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1);
-}")
-
-(define_expand "sgt"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(gt:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1);
-}")
-
-(define_expand "sgtu"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(gtu:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1);
-}")
-
-(define_expand "slt"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(lt:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1);
-}")
-
-(define_expand "sltu"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(ltu:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1);
-}")
-
-(define_expand "sge"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(ge:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1);
-}")
-
-(define_expand "sgeu"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(geu:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1);
-}")
-
-(define_expand "sle"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(le:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1);
-}")
-
-(define_expand "sleu"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(leu:SI (match_dup 1) (const_int 0)))]
-  ""
-  "
-{
-  operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(eq:SI (match_operand:SI 1 "register_operand" "d") (const_int 0)))]
-  ""
-  "shro	%1,1,%0"
-  [(set_attr "type" "alu2")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(match_operator:SI 1 "comparison_operator" [(reg:CC 36) (const_int 0)]))]
-  ""
-  "test%C1	%0"
-  [(set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(match_operator:SI 1 "comparison_operator" [(reg:CC_UNS 36) (const_int 0)]))]
-  ""
-  "test%C1	%0"
-  [(set_attr "type" "compare")])
-
-;; These control RTL generation for conditional jump insns
-;; and match them for register allocation.
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (match_dup 1)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1); }")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (match_dup 1)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1); }")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (match_dup 1)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1); }")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (match_dup 1)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1); }")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (match_dup 1)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1); }")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (match_dup 1)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1); }")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (match_dup 1)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1); }")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (match_dup 1)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1); }")
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (match_dup 1)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1); }")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (match_dup 1)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); }")
-
-;; Now the normal branch insns (forward and reverse).
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
-				      [(reg:CC 36) (const_int 0)])
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))]
-  ""
-  "b%C0 %l1"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
-				      [(reg:CC 36) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 1 "" ""))))]
-  ""
-  "b%I0 %l1"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
-				      [(reg:CC_UNS 36) (const_int 0)])
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))]
-  ""
-  "b%C0 %l1"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
-				      [(reg:CC_UNS 36) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 1 "" ""))))]
-  ""
-  "b%I0 %l1"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "comparison_operator"
-			 [(match_operand:SI 1 "arith_operand" "d")
-			  (match_operand:SI 2 "arith_operand" "dI")])
-	 (label_ref (match_operand 3 "" ""))
-	 (pc)))]
-  ""
-  "cmp%S0%B0%R0	%2,%1,%l3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "comparison_operator"
-			 [(match_operand:SI 1 "arith_operand" "d")
-			  (match_operand:SI 2 "arith_operand" "dI")])
-	 (pc)
-	 (label_ref (match_operand 3 "" ""))))]
-  ""
-  "cmp%S0%B0%X0	%2,%1,%l3"
-  [(set_attr "type" "branch")])
-
-;; CYGNUS LOCAL -- branch prediction
-;; Branch prediction insns
-(define_expand "expectsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(expect:SI (match_operand:SI 1 "nonmemory_operand" "")
-		   (match_operand:SI 2 "immediate_operand" "")))]
-  ""
-  "
-{
-  if (CONSTANT_P (operands[1]))
-    {
-      emit_move_insn (operands[0], operands[1]);
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,?d,d,d")
-	(expect:SI (match_operand:SI 1 "nonmemory_operand" "0,d,I,i")
-		   (match_operand:SI 2 "immediate_operand" "n,n,n,n")))]
-  ""
-  "*
-{
-  output_asm_insn (\"# expect %1 to be %2\", operands);
-
-  return (which_alternative) ? \"#\" : \"\";
-}"
-  [(set_attr "type" "move,move,move,address")
-   (set_attr "length" "0,*,*,3")])
-
-;; Recreate simple move from expect
-(define_split
-  [(set (match_operand:SI 0 "general_operand" "=")
-	(expect:SI (match_operand:SI 1 "general_operand" "")
-		   (match_operand:SI 2 "immediate_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 0) (match_dup 1))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "comparison_operator"
-			 [(expect:SI (match_operand:SI 1 "arith_operand" "d")
-				     (match_operand:SI 2 "immediate_operand" "n"))
-			  (match_operand:SI 3 "arith_operand" "dI")])
-	 (label_ref (match_operand 4 "" ""))
-	 (pc)))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[3]) != CONST_INT)
-    return \"cmp%S0%B0%R0\\t%3,%1,%l4\\t# expect %2\";
-
-  return (i960_branch_predict_p (FALSE, operands[0], operands[2], operands[3]))
-   ? \"cmp%S0%B0%R0.t %3,%1,%l4\\t# expect %2\"
-   : \"cmp%S0%B0%R0.f %3,%1,%l4\\t# expect %2\";
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "comparison_operator"
-			 [(expect:SI (match_operand:SI 1 "arith_operand" "d")
-				     (match_operand:SI 2 "immediate_operand" "n"))
-			  (match_operand:SI 3 "arith_operand" "dI")])
-	 (pc)
-	 (label_ref (match_operand 4 "" ""))))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[3]) != CONST_INT)
-    return \"cmp%S0%B0%X0\\t%3,%1,%l4\\t# expect %2\";
-
-  return (i960_branch_predict_p (TRUE, operands[0], operands[2], operands[3]))
-    ? \"cmp%S0%B0%X0.t %3,%1,%l4\\t# expect %2\"
-    : \"cmp%S0%B0%X0.f %3,%1,%l4\\t# expect %2\";
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (expect:SI (match_operator 0 "comparison_operator"
-					[(match_operand:SI 1 "arith_operand" "d")
-					 (match_operand:SI 2 "arith_operand" "dI")])
-			(match_operand:SI 3 "immediate_operand" "n"))
-	     (const_int 0))
-	 (label_ref (match_operand 4 "" ""))
-	 (pc)))]
-  ""
-  "*
-{
-  return (INTVAL (operands[3]) != 0)
-   ? \"cmp%S0%B0%R0.t %2,%1,%l4\\t# expect %3\"
-   : \"cmp%S0%B0%R0.f %2,%1,%l4\\t# expect %3\";
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (expect:SI (match_operator 0 "comparison_operator"
-					[(match_operand:SI 1 "arith_operand" "d")
-					 (match_operand:SI 2 "arith_operand" "dI")])
-			(match_operand:SI 3 "immediate_operand" "n"))
-	     (const_int 0))
-	 (pc)
-	 (label_ref (match_operand 4 "" ""))))]
-  ""
-  "*
-{
-  return (INTVAL (operands[3]) != 0)
-   ? \"cmp%S0%B0%X0.f %2,%1,%l4\\t# expect %3\"
-   : \"cmp%S0%B0%X0.t %2,%1,%l4\\t# expect %3\";
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (expect:SI (match_operator 0 "comparison_operator"
-					[(match_operand:SI 1 "arith_operand" "d")
-					 (match_operand:SI 2 "arith_operand" "dI")])
-			(match_operand:SI 3 "immediate_operand" "n"))
-	     (const_int 0))
-	 (label_ref (match_operand 4 "" ""))
-	 (pc)))]
-  ""
-  "*
-{
-  return (INTVAL (operands[3]) != 0)
-   ? \"cmp%S0%B0%X0.t %2,%1,%l4\\t# expect %3\"
-   : \"cmp%S0%B0%X0.f %2,%1,%l4\\t# expect %3\";
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (expect:SI (match_operator 0 "comparison_operator"
-					[(match_operand:SI 1 "arith_operand" "d")
-					 (match_operand:SI 2 "arith_operand" "dI")])
-			(match_operand:SI 3 "immediate_operand" "n"))
-	     (const_int 0))
-	 (pc)
-	 (label_ref (match_operand 4 "" ""))))]
-  ""
-  "*
-{
-  return (INTVAL (operands[3]) != 0)
-   ? \"cmp%S0%B0%R0.f %2,%1,%l4\\t# expect %3\"
-   : \"cmp%S0%B0%R0.t %2,%1,%l4\\t# expect %3\";
-}"
-  [(set_attr "type" "branch")])
-
-;; END CYGNUS LOCAL -- branch prediction
-
-;; Normal move instructions.
-;; This code is based on the sparc machine description.
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, SImode))
-    DONE;
-}")
-
-;; The store case can not be separate, because reload may convert a register
-;; to register move insn to a store (or load) insn without rerecognizing
-;; the insn.
-
-;; The i960 does not have any store constant to memory instruction.  However,
-;; the calling convention is defined so that the arg pointer when it is not
-;; overwise being used is zero.  Thus, we can handle store zero to memory
-;; by storing an unused arg pointer.  The arg pointer will be unused if
-;; current_function_args_size is zero and this is not a stdarg/varargs
-;; function.  This value of the former variable is not valid until after
-;; all rtl generation is complete, including function inlining (because a
-;; function that doesn't need an arg pointer may be inlined into a function
-;; that does need an arg pointer), so we must also check that
-;; rtx_equal_function_value_matters is zero.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d,d,d,m")
-	(match_operand:SI 1 "general_operand" "dI,i,m,dJ"))]
-  "(current_function_args_size == 0
-    && current_function_varargs == 0
-    && current_function_stdarg == 0
-    && rtx_equal_function_value_matters == 0)
-   && (register_operand (operands[0], SImode)
-       || register_operand (operands[1], SImode)
-       || operands[1] == const0_rtx)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
-	{
-	  if (GET_CODE (operands[1]) == REG)
-	    return \"lda	(%1),%0\";
-	  else
-	    return \"lda	%1,%0\";
-	}
-      return \"mov	%1,%0\";
-    case 1:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 2:
-      return \"ld	%1,%0\";
-    case 3:
-      if (operands[1] == const0_rtx)
-	return \"st	g14,%0\";
-      return \"st	%1,%0\";      
-    }
-}"
-  [(set_attr "type" "move,address,load,store")
-   (set_attr "length" "*,3,*,*")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d,d,d,m")
-	(match_operand:SI 1 "general_operand" "dI,i,m,d"))]
-  "(current_function_args_size != 0
-    || current_function_varargs != 0
-    || current_function_stdarg != 0
-    || rtx_equal_function_value_matters != 0)
-   && (register_operand (operands[0], SImode)
-       || register_operand (operands[1], SImode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
-	{
-	  if (GET_CODE (operands[1]) == REG)
-	    return \"lda	(%1),%0\";
-	  else
-	    return \"lda	%1,%0\";
-	}
-      return \"mov	%1,%0\";
-    case 1:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 2:
-      return \"ld	%1,%0\";
-    case 3:
-      return \"st	%1,%0\";      
-    }
-}"
-  [(set_attr "type" "move,address,load,store")
-   (set_attr "length" "*,3,*,*")])
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, HImode))
-    DONE;
-}")
-
-;; Special pattern for zero stores to memory for functions which don't use
-;; the arg pointer.
-
-;; The store case can not be separate.  See above.
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d,d,d,m")
-	(match_operand:HI 1 "general_operand" "dI,i,m,dJ"))]
-  "(current_function_args_size == 0
-    && current_function_varargs == 0
-    && current_function_stdarg == 0
-    && rtx_equal_function_value_matters == 0)
-   && (register_operand (operands[0], HImode)
-       || register_operand (operands[1], HImode)
-       || operands[1] == const0_rtx)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
-	{
-	  if (GET_CODE (operands[1]) == REG)
-	    return \"lda	(%1),%0\";
-	  else
-	    return \"lda	%1,%0\";
-	}
-      return \"mov	%1,%0\";
-    case 1:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 2:
-      return \"ldos	%1,%0\";
-    case 3:
-      if (operands[1] == const0_rtx)
-	return \"stos	g14,%0\";
-      return \"stos	%1,%0\";
-    }
-}"
-  [(set_attr "type" "move,misc,load,store")
-   (set_attr "length" "*,3,*,*")])
-
-;; The store case can not be separate.  See above.
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d,d,d,m")
-	(match_operand:HI 1 "general_operand" "dI,i,m,d"))]
-  "(current_function_args_size != 0
-    || current_function_varargs != 0
-    || current_function_stdarg != 0
-    || rtx_equal_function_value_matters != 0)
-   && (register_operand (operands[0], HImode)
-       || register_operand (operands[1], HImode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
-	{
-	  if (GET_CODE (operands[1]) == REG)
-	    return \"lda	(%1),%0\";
-	  else
-	    return \"lda	%1,%0\";
-	}
-      return \"mov	%1,%0\";
-    case 1:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 2:
-      return \"ldos	%1,%0\";
-    case 3:
-      return \"stos	%1,%0\";
-    }
-}"
-  [(set_attr "type" "move,misc,load,store")
-   (set_attr "length" "*,3,*,*")])
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, QImode))
-    DONE;
-}")
-
-;; The store case can not be separate.  See comment above.
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d,d,d,m")
-	(match_operand:QI 1 "general_operand" "dI,i,m,dJ"))]
-  "(current_function_args_size == 0
-    && current_function_varargs == 0
-    && current_function_stdarg == 0
-    && rtx_equal_function_value_matters == 0)
-   && (register_operand (operands[0], QImode)
-       || register_operand (operands[1], QImode)
-       || operands[1] == const0_rtx)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
-	{
-	  if (GET_CODE (operands[1]) == REG)
-	    return \"lda	(%1),%0\";
-	  else
-	    return \"lda	%1,%0\";
-	}
-      return \"mov	%1,%0\";
-    case 1:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 2:
-      return \"ldob	%1,%0\";
-    case 3:
-      if (operands[1] == const0_rtx)
-	return \"stob	g14,%0\";
-      return \"stob	%1,%0\";
-    }
-}"
-  [(set_attr "type" "move,misc,load,store")
-   (set_attr "length" "*,3,*,*")])
-
-;; The store case can not be separate.  See comment above.
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d,d,d,m")
-	(match_operand:QI 1 "general_operand" "dI,i,m,d"))]
-  "(current_function_args_size != 0
-    || current_function_varargs != 0
-    || current_function_stdarg != 0
-    || rtx_equal_function_value_matters != 0)
-   && (register_operand (operands[0], QImode)
-       || register_operand (operands[1], QImode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
-	{
-	  if (GET_CODE (operands[1]) == REG)
-	    return \"lda	(%1),%0\";
-	  else
-	    return \"lda	%1,%0\";
-	}
-      return \"mov	%1,%0\";
-    case 1:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 2:
-      return \"ldob	%1,%0\";
-    case 3:
-      return \"stob	%1,%0\";
-    }
-}"
-  [(set_attr "type" "move,misc,load,store")
-   (set_attr "length" "*,3,*,*")])
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, DImode))
-    DONE;
-}")
-
-;; The store case can not be separate.  See comment above.
-(define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,m,o")
-	(match_operand:DI 1 "general_operand" "d,I,i,m,d,J"))]
-  "(current_function_args_size == 0
-    && current_function_varargs == 0
-    && current_function_stdarg == 0
-    && rtx_equal_function_value_matters == 0)
-   && (register_operand (operands[0], DImode)
-       || register_operand (operands[1], DImode)
-       || operands[1] == const0_rtx)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-    case 3:
-    case 4:
-      return i960_output_move_double (operands[0], operands[1]);
-    case 2:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 5:
-      return i960_output_move_double_zero (operands[0]);
-    }
-}"
-  [(set_attr "type" "move,move,load,load,store,store")])
-
-;; The store case can not be separate.  See comment above.
-(define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,m")
-	(match_operand:DI 1 "general_operand" "d,I,i,m,d"))]
-  "(current_function_args_size != 0
-    || current_function_varargs != 0
-    || current_function_stdarg != 0
-    || rtx_equal_function_value_matters != 0)
-   && (register_operand (operands[0], DImode)
-       || register_operand (operands[1], DImode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-    case 3:
-    case 4:
-      return i960_output_move_double (operands[0], operands[1]);
-    case 2:
-      return i960_output_ldconst (operands[0], operands[1]);
-    }
-}"
-  [(set_attr "type" "move,move,load,load,store")])
-
-(define_insn "*store_unaligned_di_reg"
-  [(set (match_operand:DI 0 "general_operand" "=d,m")
-	(match_operand:DI 1 "register_operand" "d,d"))
-   (clobber (match_scratch:SI 2 "=X,&d"))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return i960_output_move_double (operands[0], operands[1]);
-    
-  operands[3] = gen_rtx (MEM, word_mode, operands[2]);
-  operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
-  return \"lda	%0,%2\;st	%1,%3\;st	%D1,%4\";
-}"
-  [(set_attr "type" "move,store")])
-
-(define_expand "movti"
-  [(set (match_operand:TI 0 "general_operand" "")
-	(match_operand:TI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, TImode))
-    DONE;
-}")
-
-;; The store case can not be separate.  See comment above.
-(define_insn ""
-  [(set (match_operand:TI 0 "general_operand" "=d,d,d,d,m,o")
-	(match_operand:TI 1 "general_operand" "d,I,i,m,d,J"))]
-  "(current_function_args_size == 0
-    && current_function_varargs == 0
-    && current_function_stdarg == 0
-    && rtx_equal_function_value_matters == 0)
-   && (register_operand (operands[0], TImode)
-       || register_operand (operands[1], TImode)
-       || operands[1] == const0_rtx)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-    case 3:
-    case 4:
-      return i960_output_move_quad (operands[0], operands[1]);
-    case 2:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 5:
-      return i960_output_move_quad_zero (operands[0]);
-    }
-}"
-  [(set_attr "type" "move,move,load,load,store,store")])
-
-;; The store case can not be separate.  See comment above.
-(define_insn ""
-  [(set (match_operand:TI 0 "general_operand" "=d,d,d,d,m")
-	(match_operand:TI 1 "general_operand" "d,I,i,m,d"))]
-  "(current_function_args_size != 0
-    || current_function_varargs != 0
-    || current_function_stdarg != 0
-    || rtx_equal_function_value_matters != 0)
-   && (register_operand (operands[0], TImode)
-       || register_operand (operands[1], TImode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-    case 3:
-    case 4:
-      return i960_output_move_quad (operands[0], operands[1]);
-    case 2:
-      return i960_output_ldconst (operands[0], operands[1]);
-    }
-}"
-  [(set_attr "type" "move,move,load,load,store")])
-
-(define_insn "*store_unaligned_ti_reg"
-  [(set (match_operand:TI 0 "general_operand" "=d,m")
-	(match_operand:TI 1 "register_operand" "d,d"))
-   (clobber (match_scratch:SI 2 "=X,&d"))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return i960_output_move_quad (operands[0], operands[1]);
-
-  operands[3] = gen_rtx (MEM, word_mode, operands[2]);
-  operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
-  operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD);
-  operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD);
-  return \"lda	%0,%2\;st	%1,%3\;st	%D1,%4\;st	%E1,%5\;st	%F1,%6\";
-}"
-  [(set_attr "type" "move,store")])
-
-(define_expand "store_multiple"
-  [(set (match_operand:SI 0 "" "")	;;- dest
-	(match_operand:SI 1 "" ""))	;;- src
-   (use (match_operand:SI 2 "" ""))]	;;- nregs
-  ""
-  "
-{
-  int regno;
-  int count;
-  rtx from;
-  int i;
-
-  if (GET_CODE (operands[0]) != MEM
-      || GET_CODE (operands[1]) != REG
-      || GET_CODE (operands[2]) != CONST_INT)
-    FAIL;
-
-  count = INTVAL (operands[2]);
-  if (count > 12)
-    FAIL;
-
-  regno = REGNO (operands[1]);
-  from = memory_address (SImode, XEXP (operands[0], 0));
-  while (count >= 4 && ((regno & 3) == 0))
-    {
-      emit_insn (gen_rtx (SET, VOIDmode,
-			  gen_rtx (MEM, TImode, from),
-			  gen_rtx (REG, TImode, regno)));
-      count -= 4;
-      regno += 4;
-      from = memory_address (TImode, plus_constant (from, 16));
-    }
-  while (count >= 2 && ((regno & 1) == 0))
-    {
-      emit_insn (gen_rtx (SET, VOIDmode,
-			  gen_rtx (MEM, DImode, from),
-			  gen_rtx (REG, DImode, regno)));
-      count -= 2;
-      regno += 2;
-      from = memory_address (DImode, plus_constant (from, 8));
-    }
-  while (count > 0)
-    {
-      emit_insn (gen_rtx (SET, VOIDmode,
-			  gen_rtx (MEM, SImode, from),
-			  gen_rtx (REG, SImode, regno)));
-      count -= 1;
-      regno += 1;
-      from = memory_address (SImode, plus_constant (from, 4));
-    }
-  DONE;
-}")
-
-;; Floating point move insns
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "fpmove_src_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, DFmode))
-    DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m,o")
-	(match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))]
-  "(current_function_args_size == 0
-    && current_function_varargs == 0
-    && current_function_stdarg == 0
-    && rtx_equal_function_value_matters == 0)
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode)
-       || operands[1] == CONST0_RTX (DFmode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
-	return \"movrl	%1,%0\";
-      else
-	return \"movl	%1,%0\";
-    case 1:
-      return \"movrl	%1,%0\";
-    case 2:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 3:
-      return \"ldl	%1,%0\";
-    case 4:
-      return \"stl	%1,%0\";
-    case 5:
-      operands[1] = adj_offsettable_operand (operands[0], 4);
-      return \"st	g14,%0\;st	g14,%1\";
-    }
-}"
-  [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m")
-	(match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
-  "(current_function_args_size != 0
-    || current_function_varargs != 0
-    || current_function_stdarg != 0
-    || rtx_equal_function_value_matters != 0)
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
-	return \"movrl	%1,%0\";
-      else
-	return \"movl	%1,%0\";
-    case 1:
-      return \"movrl	%1,%0\";
-    case 2:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 3:
-      return \"ldl	%1,%0\";
-    case 4:
-      return \"stl	%1,%0\";
-    }
-}"
-  [(set_attr "type" "move,move,load,fpload,fpstore")])
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "fpmove_src_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, SFmode))
-    DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m")
-	(match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,dG"))]
-  "(current_function_args_size == 0
-    && current_function_varargs == 0
-    && current_function_stdarg == 0
-    && rtx_equal_function_value_matters == 0)
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode)
-       || operands[1] == CONST0_RTX (SFmode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
-	return \"movr	%1,%0\";
-      else
-	return \"mov	%1,%0\";
-    case 1:
-      return \"movr	%1,%0\";
-    case 2:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 3:
-      return \"ld	%1,%0\";
-    case 4:
-      if (operands[1] == CONST0_RTX (SFmode))
-	return \"st	g14,%0\";
-      return \"st	%1,%0\";
-    }
-}"
-  [(set_attr "type" "move,move,load,fpload,fpstore")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m")
-	(match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
-  "(current_function_args_size != 0
-    || current_function_varargs != 0
-    || current_function_stdarg != 0
-    || rtx_equal_function_value_matters != 0)
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
-	return \"movr	%1,%0\";
-      else
-	return \"mov	%1,%0\";
-    case 1:
-      return \"movr	%1,%0\";
-    case 2:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 3:
-      return \"ld	%1,%0\";
-    case 4:
-      return \"st	%1,%0\";
-    }
-}"
-  [(set_attr "type" "move,move,load,fpload,fpstore")])
-
-;; Mixed-mode moves with sign and zero-extension.
-
-;; Note that the one starting from HImode comes before those for QImode
-;; so that a constant operand will match HImode, not QImode.
-
-(define_expand "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI
-	 (match_operand:HI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
-  if (GET_CODE (operand1) == REG
-      || (GET_CODE (operand1) == SUBREG
-	  && GET_CODE (XEXP (operand1, 0)) == REG))
-    {
-      rtx temp = gen_reg_rtx (SImode);
-      rtx shift_16 = GEN_INT (16);
-      int op1_subreg_word = 0;
-
-      if (GET_CODE (operand1) == SUBREG)
-	{
-	  op1_subreg_word = SUBREG_WORD (operand1);
-	  operand1 = SUBREG_REG (operand1);
-	}
-      if (GET_MODE (operand1) != SImode)
-	operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
-
-      emit_insn (gen_ashlsi3 (temp, operand1, shift_16));
-      emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
-  ""
-  "ldis	%1,%0"
-  [(set_attr "type" "load")])
-
-(define_expand "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operand1) == REG
-      || (GET_CODE (operand1) == SUBREG
-	  && GET_CODE (XEXP (operand1, 0)) == REG))
-    {
-      rtx temp = gen_reg_rtx (SImode);
-      rtx shift_24 = GEN_INT (24);
-      int op1_subreg_word = 0;
-
-      if (GET_CODE (operand1) == SUBREG)
-	{
-	  op1_subreg_word = SUBREG_WORD (operand1);
-	  operand1 = SUBREG_REG (operand1);
-	}
-      if (GET_MODE (operand1) != SImode)
-	operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
-
-      emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
-      emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
-  ""
-  "ldib	%1,%0"
-  [(set_attr "type" "load")])
-
-(define_expand "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(sign_extend:HI
-	 (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operand1) == REG
-      || (GET_CODE (operand1) == SUBREG
-	  && GET_CODE (XEXP (operand1, 0)) == REG))
-    {
-      rtx temp = gen_reg_rtx (SImode);
-      rtx shift_24 = GEN_INT (24);
-      int op0_subreg_word = 0;
-      int op1_subreg_word = 0;
-
-      if (GET_CODE (operand1) == SUBREG)
-	{
-	  op1_subreg_word = SUBREG_WORD (operand1);
-	  operand1 = SUBREG_REG (operand1);
-	}
-      if (GET_MODE (operand1) != SImode)
-	operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
-
-      if (GET_CODE (operand0) == SUBREG)
-	{
-	  op0_subreg_word = SUBREG_WORD (operand0);
-	  operand0 = SUBREG_REG (operand0);
-	}
-      if (GET_MODE (operand0) != SImode)
-	operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word);
-
-      emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
-      emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=d")
-	(sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
-  ""
-  "ldib	%1,%0"
-  [(set_attr "type" "load")])
-
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI
-	 (match_operand:HI 1 "nonimmediate_operand" "")))]
- ""
- "
-{
-  if (GET_CODE (operand1) == REG
-      || (GET_CODE (operand1) == SUBREG
-	  && GET_CODE (XEXP (operand1, 0)) == REG))
-    {
-      rtx temp = gen_reg_rtx (SImode);
-      rtx shift_16 = GEN_INT (16);
-      int op1_subreg_word = 0;
-
-      if (GET_CODE (operand1) == SUBREG)
-	{
-	  op1_subreg_word = SUBREG_WORD (operand1);
-	  operand1 = SUBREG_REG (operand1);
-	}
-      if (GET_MODE (operand1) != SImode)
-	operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
-
-      emit_insn (gen_ashlsi3 (temp, operand1, shift_16));
-      emit_insn (gen_lshrsi3 (operand0, temp, shift_16));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
-  ""
-  "ldos	%1,%0"
-  [(set_attr "type" "load")])
-
-;; Using shifts here generates much better code than doing an `and 255'.
-;; This is mainly because the `and' requires loading the constant separately,
-;; the constant is likely to get optimized, and then the compiler can't
-;; optimize the `and' because it doesn't know that one operand is a constant.
-
-(define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operand1) == REG
-      || (GET_CODE (operand1) == SUBREG
-	  && GET_CODE (XEXP (operand1, 0)) == REG))
-    {
-      rtx temp = gen_reg_rtx (SImode);
-      rtx shift_24 = GEN_INT (24);
-      int op1_subreg_word = 0;
-
-      if (GET_CODE (operand1) == SUBREG)
-	{
-	  op1_subreg_word = SUBREG_WORD (operand1);
-	  operand1 = SUBREG_REG (operand1);
-	}
-      if (GET_MODE (operand1) != SImode)
-	operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
-
-      emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
-      emit_insn (gen_lshrsi3 (operand0, temp, shift_24));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
-  ""
-  "ldob	%1,%0"
-  [(set_attr "type" "load")])
-
-(define_expand "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(zero_extend:HI
-	 (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operand1) == REG
-      || (GET_CODE (operand1) == SUBREG
-	  && GET_CODE (XEXP (operand1, 0)) == REG))
-    {
-      rtx temp = gen_reg_rtx (SImode);
-      rtx shift_24 = GEN_INT (24);
-      int op0_subreg_word = 0;
-      int op1_subreg_word = 0;
-
-      if (GET_CODE (operand1) == SUBREG)
-	{
-	  op1_subreg_word = SUBREG_WORD (operand1);
-	  operand1 = SUBREG_REG (operand1);
-	}
-      if (GET_MODE (operand1) != SImode)
-	operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
-
-      if (GET_CODE (operand0) == SUBREG)
-	{
-	  op0_subreg_word = SUBREG_WORD (operand0);
-	  operand0 = SUBREG_REG (operand0);
-	}
-      if (GET_MODE (operand0) != SImode)
-	operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word);
-
-      emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
-      emit_insn (gen_lshrsi3 (operand0, temp, shift_24));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=d")
-	(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
-  ""
-  "ldob	%1,%0"
-  [(set_attr "type" "load")])
-
-;; Conversions between float and double.
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=*f,d")
-	(float_extend:DF (match_operand:SF 1 "fp_arith_operand" "dGH,fGH")))]
-  "TARGET_NUMERICS"
-  "@
-  movr	%1,%0
-  movrl	%1,%0"
-  [(set_attr "type" "fpmove")])
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(float_truncate:SF
-	 (match_operand:DF 1 "fp_arith_operand" "fGH")))]
-  "TARGET_NUMERICS"
-  "movr	%1,%0"
-  [(set_attr "type" "fpmove")])
-
-;; Conversion between fixed point and floating point.
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float:DF (match_operand:SI 1 "register_operand" "d")))]
-  "TARGET_NUMERICS"
-  "cvtir	%1,%0"
-  [(set_attr "type" "fpcvt")])
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "register_operand" "=d*f")
-	(float:SF (match_operand:SI 1 "register_operand" "d")))]
-  "TARGET_NUMERICS"
-  "cvtir	%1,%0"
-  [(set_attr "type" "fpcvt")])
-
-;; Convert a float to an actual integer.
-;; Truncation is performed as part of the conversion.
-;; The i960 requires conversion from DFmode to DImode to make
-;; unsigned conversions work properly.
-
-(define_insn "fixuns_truncdfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(unsigned_fix:DI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))]
-  "TARGET_NUMERICS"
-  "cvtzril	%1,%0"
-  [(set_attr "type" "fpcvt")])
-
-(define_insn "fixuns_truncsfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(unsigned_fix:DI (fix:SF (match_operand:SF 1 "fp_arith_operand" "fGH"))))]
-  "TARGET_NUMERICS"
-  "cvtzril	%1,%0"
-  [(set_attr "type" "fpcvt")])
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))]
-  "TARGET_NUMERICS"
-  "cvtzri	%1,%0"
-  [(set_attr "type" "fpcvt")])
-
-(define_expand "fixuns_truncdfsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(unsigned_fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" ""))))]
-  "TARGET_NUMERICS"
-  "
-{
-  rtx temp = gen_reg_rtx (DImode);
-  emit_insn (gen_rtx (SET, VOIDmode, temp,
-		      gen_rtx (UNSIGNED_FIX, DImode,
-			       gen_rtx (FIX, DFmode, operands[1]))));
-  emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-		      gen_rtx (SUBREG, SImode, temp, 0)));
-  DONE;
-}")
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" "dfGH"))))]
-  "TARGET_NUMERICS"
-  "cvtzri	%1,%0"
-  [(set_attr "type" "fpcvt")])
-
-(define_expand "fixuns_truncsfsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(unsigned_fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" ""))))]
-  "TARGET_NUMERICS"
-  "
-{
-  rtx temp = gen_reg_rtx (DImode);
-  emit_insn (gen_rtx (SET, VOIDmode, temp,
-		      gen_rtx (UNSIGNED_FIX, DImode,
-			       gen_rtx (FIX, SFmode, operands[1]))));
-  emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-		      gen_rtx (SUBREG, SImode, temp, 0)));
-  DONE;
-}")
-
-;; Arithmetic instructions.
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(minus:SI (match_operand:SI 1 "arith_operand" "dI")
-		  (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "subo	%2,%1,%0")
-
-;; Try to generate an lda instruction when it would be faster than an
-;; add instruction.
-;; Some assemblers apparently won't accept two addresses added together.
-
-;; ??? The condition should be improved to reject the case of two
-;; symbolic constants.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
-	(plus:SI (match_operand:SI 1 "arith32_operand" "%dn,i,dn")
-		 (match_operand:SI 2 "arith32_operand" "dn,dn,i")))]
-  "(TARGET_C_SERIES) && (CONSTANT_P (operands[1]) || CONSTANT_P (operands[2]))"
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      rtx tmp = operands[1];
-      operands[1] = operands[2];
-      operands[2] = tmp;
-    }
-  if (GET_CODE (operands[2]) == CONST_INT
-      && GET_CODE (operands[1]) == REG
-      && i960_last_insn_type != I_TYPE_REG)
-    {
-      if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32)
-	return \"subo	%n2,%1,%0\";
-      else if (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)
-	return \"addo	%1,%2,%0\";
-    }
-  /* Non-canonical results (op1 == const, op2 != const) have been seen
-     in reload output when both operands were symbols before reload, so
-     we deal with it here.  This may be a fault of the constraints above.  */
-  if (CONSTANT_P (operands[1]))
-    {
-      if (CONSTANT_P (operands[2]))
-	return \"lda	%1+%2,%0\";
-      else
-	return \"lda	%1(%2),%0\";
-    }
-  return \"lda	%2(%1),%0\";
-}")
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(plus:SI (match_operand:SI 1 "signed_arith_operand" "%dI")
-		 (match_operand:SI 2 "signed_arith_operand" "dIK")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    return \"subo	%n2,%1,%0\";
-  if (i960_bypass (insn, operands[1], operands[2], 0))
-    return \"addo	%2,%1,%0\";
-  return \"addo	%1,%2,%0\";
-}")
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(mult:SI (match_operand:SI 1 "arith_operand" "%dI")
-		 (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "*
-{
-  if (i960_bypass (insn, operands[1], operands[2], 0))
-    return \"mulo	%2,%1,%0\";
-  return \"mulo	%1,%2,%0\";
-}"
-  [(set_attr "type" "mult")])
-
-(define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
-		 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
-  ""
-  "*
-{
-  if (i960_bypass (insn, operands[1], operands[2], 0))
-    return \"emul	%2,%1,%0\";
-  return \"emul	%1,%2,%0\";
-}"
-  [(set_attr "type" "mult")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%d"))
-		 (match_operand:SI 2 "literal" "I")))]
-  ""
-  "*
-{
-  if (i960_bypass (insn, operands[1], operands[2], 0))
-    return \"emul	%2,%1,%0\";
-  return \"emul	%1,%2,%0\";
-}"
-  [(set_attr "type" "mult")])
-
-;; This goes after the move/add/sub/mul instructions  
-;; because those instructions are better when they apply.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(match_operand:SI 1 "address_operand" "p"))]
-  ""
-  "lda	%a1,%0"
-  [(set_attr "type" "load")])
-
-;; This will never be selected because of an "optimization" that GCC does.
-;; It always converts divides by a power of 2 into a sequence of instructions
-;; that does a right shift, and then corrects the result if it was negative.
-
-;; (define_insn ""
-;;   [(set (match_operand:SI 0 "register_operand" "=d")
-;;         (div:SI (match_operand:SI 1 "arith_operand" "dI")
-;;                 (match_operand:SI 2 "power2_operand" "nI")))]
-;;   ""
-;;   "*{
-;; 	operands[2] = GEN_INT (bitpos (INTVAL (operands[2])));
-;; 	return \"shrdi	%2,%1,%0\";
-;;   }"
-
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-        (div:SI (match_operand:SI 1 "arith_operand" "dI")
-                (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "divi	%2,%1,%0"
-  [(set_attr "type" "div")])
-
-(define_insn "udivsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-        (udiv:SI (match_operand:SI 1 "arith_operand" "dI")
-		 (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "divo	%2,%1,%0"
-  [(set_attr "type" "div")])
-
-;; We must use `remi' not `modi' here, to ensure that `%' has the effects
-;; specified by the ANSI C standard.
-
-(define_insn "modsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-        (mod:SI (match_operand:SI 1 "arith_operand" "dI")
-                (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "remi	%2,%1,%0"
-  [(set_attr "type" "div")])
-
-(define_insn "umodsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-        (umod:SI (match_operand:SI 1 "arith_operand" "dI")
-		 (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "remo	%2,%1,%0"
-  [(set_attr "type" "div")])
-
-;; And instructions (with complement also).
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(and:SI (match_operand:SI 1 "register_operand" "%d")
-		(match_operand:SI 2 "logic_operand" "dIM")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    return \"andnot	%C2,%1,%0\";
-  if (i960_bypass (insn, operands[1], operands[2], 0))
-    return \"and	%2,%1,%0\";
-  return \"and	%1,%2,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(and:SI (match_operand:SI 1 "arith_operand" "dI")
-		(match_operand:SI 2 "cmplpower2_operand" "n")))]
-  ""
-  "*
-{
-  operands[2] = GEN_INT (bitpos (~INTVAL (operands[2])));
-  return \"clrbit	%2,%1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
-		(match_operand:SI 2 "logic_operand" "dIM")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    return \"nor	%C2,%1,%0\";
-  if (i960_bypass (insn, operands[1], operands[2], 0))
-    return \"notand	%2,%1,%0\";
-  return \"andnot	%1,%2,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ior:SI (not:SI (match_operand:SI 1 "register_operand" "%d"))
-		(not:SI (match_operand:SI 2 "register_operand" "d"))))]
-  ""
-  "*
-{
-  if (i960_bypass (insn, operands[1], operands[2], 0))
-    return \"nand	%2,%1,%0\";
-  return \"nand	%1,%2,%0\";
-}")
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ior:SI (match_operand:SI 1 "register_operand" "%d")
-		(match_operand:SI 2 "logic_operand" "dIM")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    return \"ornot	%C2,%1,%0\";
-  if (i960_bypass (insn, operands[1], operands[2], 0))
-    return \"or	%2,%1,%0\";
-  return \"or	%1,%2,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ior:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "power2_operand" "n")))]
-  ""
-  "*
-{
-  operands[2] = GEN_INT (bitpos (INTVAL (operands[2])));
-  return \"setbit	%2,%1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ior:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
-		(match_operand:SI 2 "logic_operand" "dIM")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    return \"nand	%C2,%1,%0\";
-  if (i960_bypass (insn, operands[1], operands[2], 0))
-    return \"notor	%2,%1,%0\";
-  return \"ornot	%1,%2,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(and:SI (not:SI (match_operand:SI 1 "register_operand" "%d"))
-		(not:SI (match_operand:SI 2 "register_operand" "d"))))]
-  ""
-  "*
-{
-  if (i960_bypass (insn, operands[1], operands[2], 0))
-    return \"nor	%2,%1,%0\";
-  return \"nor	%1,%2,%0\";
-}")
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(xor:SI (match_operand:SI 1 "register_operand" "%d")
-		(match_operand:SI 2 "logic_operand" "dIM")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    return \"xnor	%C2,%1,%0\";
-  if (i960_bypass (insn, operands[1], operands[2], 0))
-    return \"xor	%2,%1,%0\";
-  return \"xor	%1,%2,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(xor:SI (match_operand:SI 1 "arith_operand" "dI")
-		(match_operand:SI 2 "power2_operand" "n")))]
-  ""
-  "*
-{
-  operands[2] = GEN_INT (bitpos (INTVAL (operands[2])));
-  return \"notbit	%2,%1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(not:SI (xor:SI (match_operand:SI 1 "register_operand" "%d")
-			(match_operand:SI 2 "register_operand" "d"))))]
-  ""
-  "*
-{
-  if (i960_bypass (insn, operands[1], operands[2], 0))
-    return \"xnor	%2,%1,%0\";
-  return \"xnor	%2,%1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ior:SI (ashift:SI (const_int 1)
-			   (match_operand:SI 1 "register_operand" "d"))
-		(match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "setbit	%1,%2,%0")
-
-;; (not (ashift 1 reg)) canonicalizes to (rotate -2 reg)
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(and:SI (rotate:SI (const_int -2)
-			   (match_operand:SI 1 "register_operand" "d"))
-		(match_operand:SI 2 "register_operand" "d")))]
-  ""
-  "clrbit	%1,%2,%0")
-
-;; The above pattern canonicalizes to this when both the input and output
-;; are the same pseudo-register.
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "=d")
-			 (const_int 1)
-			 (match_operand:SI 1 "register_operand" "d"))
-	(const_int 0))]
-  ""
-  "clrbit	%1,%0,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(xor:SI (ashift:SI (const_int 1)
-			   (match_operand:SI 1 "register_operand" "d"))
-		(match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "notbit	%1,%2,%0")
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(neg:SI (match_operand:SI 1 "arith_operand" "dI")))]
-  ""
-  "subo	%1,0,%0"
-  [(set_attr "length" "1")])
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(not:SI (match_operand:SI 1 "arith_operand" "dI")))]
-  ""
-  "not	%1,%0"
-  [(set_attr "length" "1")])
-
-;; Floating point arithmetic instructions.
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=d*f")
-	(plus:DF (match_operand:DF 1 "fp_arith_operand" "%rGH")
-		 (match_operand:DF 2 "fp_arith_operand" "rGH")))]
-  "TARGET_NUMERICS"
-  "addrl	%1,%2,%0"
-  [(set_attr "type" "fpadd")])
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=d*f")
-	(plus:SF (match_operand:SF 1 "fp_arith_operand" "%rGH")
-		 (match_operand:SF 2 "fp_arith_operand" "rGH")))]
-  "TARGET_NUMERICS"
-  "addr	%1,%2,%0"
-  [(set_attr "type" "fpadd")])
-
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=d*f")
-	(minus:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
-		  (match_operand:DF 2 "fp_arith_operand" "rGH")))]
-  "TARGET_NUMERICS"
-  "subrl	%2,%1,%0"
-  [(set_attr "type" "fpadd")])
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=d*f")
-	(minus:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
-		  (match_operand:SF 2 "fp_arith_operand" "rGH")))]
-  "TARGET_NUMERICS"
-  "subr	%2,%1,%0"
-  [(set_attr "type" "fpadd")])
-
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=d*f")
-	(mult:DF (match_operand:DF 1 "fp_arith_operand" "%rGH")
-		 (match_operand:DF 2 "fp_arith_operand" "rGH")))]
-  "TARGET_NUMERICS"
-  "mulrl	%1,%2,%0"
-  [(set_attr "type" "fpmul")])
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=d*f")
-	(mult:SF (match_operand:SF 1 "fp_arith_operand" "%rGH")
-		 (match_operand:SF 2 "fp_arith_operand" "rGH")))]
-  "TARGET_NUMERICS"
-  "mulr	%1,%2,%0"
-  [(set_attr "type" "fpmul")])
-
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=d*f")
-	(div:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
-		(match_operand:DF 2 "fp_arith_operand" "rGH")))]
-  "TARGET_NUMERICS"
-  "divrl	%2,%1,%0"
-  [(set_attr "type" "fpdiv")])
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=d*f")
-	(div:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
-		(match_operand:SF 2 "fp_arith_operand" "rGH")))]
-  "TARGET_NUMERICS"
-  "divr	%2,%1,%0"
-  [(set_attr "type" "fpdiv")])
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=d,d*f")
-	(neg:DF (match_operand:DF 1 "register_operand" "d,r")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    {
-      if (REGNO (operands[0]) == REGNO (operands[1]))
-	return \"notbit	31,%D1,%D0\";
-      return \"mov	%1,%0\;notbit	31,%D1,%D0\";
-    }
-  return \"subrl	%1,0f0.0,%0\";
-}"
-  [(set_attr "type" "fpadd")])
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=d,d*f")
-	(neg:SF (match_operand:SF 1 "register_operand" "d,r")))]
-  ""
-  "@
-  notbit	31,%1,%0
-  subr	%1,0f0.0,%0"
-  [(set_attr "type" "fpadd")])
-
-;;; The abs patterns also work even if the target machine doesn't have
-;;; floating point, because in that case dstreg and srcreg will always be
-;;; less than 32.
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "=d*f")
-	(abs:DF (match_operand:DF 1 "register_operand" "df")))]
-  ""
-  "*
-{
-  int dstreg = REGNO (operands[0]);
-  int srcreg = REGNO (operands[1]);
-
-  if (dstreg < 32)
-    {
-      if (srcreg < 32)
-	{
-	  if (dstreg != srcreg)
-	    output_asm_insn (\"mov	%1,%0\", operands);
-	  return \"clrbit	31,%D1,%D0\";
-	}
-      /* Src is an fp reg.  */
-      return \"movrl	%1,%0\;clrbit	31,%D1,%D0\";
-    }
-  if (srcreg >= 32)
-    return \"cpysre	%1,0f0.0,%0\";
-  return \"movrl	%1,%0\;cpysre	%0,0f0.0,%0\";
-}"
-  [(set_attr "type" "multi")])
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=d*f")
-	(abs:SF (match_operand:SF 1 "register_operand" "df")))]
-  ""
-  "*
-{
-  int dstreg = REGNO (operands[0]);
-  int srcreg = REGNO (operands[1]);
-
-  if (dstreg < 32 && srcreg < 32)
-    return \"clrbit	31,%1,%0\";
-
-  if (dstreg >= 32 && srcreg >= 32)
-    return \"cpysre	%1,0f0.0,%0\";
-
-  if (dstreg < 32)
-    return \"movr	%1,%0\;clrbit	31,%0,%0\";
-
-  return \"movr	%1,%0\;cpysre	%0,0f0.0,%0\";
-}"
-  [(set_attr "type" "multi")])
-
-;; Tetra (16 byte) float support.
-
-(define_expand "cmpxf"
-  [(set (reg:CC 36)
-	(compare:CC (match_operand:XF 0 "register_operand" "")
-		    (match_operand:XF 1 "nonmemory_operand" "")))]
-  "TARGET_NUMERICS"
-  "
-{
-  i960_compare_op0 = operands[0];
-  i960_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_insn ""
-  [(set (reg:CC 36)
-	(compare:CC (match_operand:XF 0 "register_operand" "f")
-		    (match_operand:XF 1 "nonmemory_operand" "fGH")))]
-  "TARGET_NUMERICS"
-  "cmpr %0,%1"
-  [(set_attr "type" "fpcc")])
-
-(define_expand "movxf"
-  [(set (match_operand:XF 0 "general_operand" "")
-	(match_operand:XF 1 "fpmove_src_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, XFmode))
-    DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=r,f,d,d,m")
-	(match_operand:XF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
-  "register_operand (operands[0], XFmode)
-   || register_operand (operands[1], XFmode)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
-	return \"movre	%1,%0\";
-      else
-	return \"movq	%1,%0\";
-    case 1:
-      return \"movre	%1,%0\";
-    case 2:
-      return i960_output_ldconst (operands[0], operands[1]);
-    case 3:
-      return \"ldt	%1,%0\";
-    case 4:
-      return \"stt	%1,%0\";
-    }
-}"
-  [(set_attr "type" "move,move,load,fpload,fpstore")])
-
-(define_insn "extendsfxf2"
-  [(set (match_operand:XF 0 "register_operand" "=f,d")
-	(float_extend:XF
-	 (match_operand:SF 1 "register_operand" "d,f")))]
-  "TARGET_NUMERICS"
-  "@
-  movr	%1,%0
-  movre	%1,%0"
-  [(set_attr "type" "fpmove")])
-
-(define_insn "extenddfxf2"
-  [(set (match_operand:XF 0 "register_operand" "=f,d")
-	(float_extend:XF
-	 (match_operand:DF 1 "register_operand" "d,f")))]
-  "TARGET_NUMERICS"
-  "@
-  movrl	%1,%0
-  movre	%1,%0"
-  [(set_attr "type" "fpmove")])
-
-(define_insn "truncxfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(float_truncate:DF
-	 (match_operand:XF 1 "register_operand" "f")))]
-  "TARGET_NUMERICS"
-  "movrl	%1,%0"
-  [(set_attr "type" "fpmove")])
-
-(define_insn "truncxfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=d")
-	(float_truncate:SF
-	 (match_operand:XF 1 "register_operand" "f")))]
-  "TARGET_NUMERICS"
-  "movr	%1,%0"
-  [(set_attr "type" "fpmove")])
-
-(define_insn "floatsixf2"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(float:XF (match_operand:SI 1 "register_operand" "d")))]
-  "TARGET_NUMERICS"
-  "cvtir	%1,%0"
-  [(set_attr "type" "fpcvt")])
-
-(define_insn "fix_truncxfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))]
-  "TARGET_NUMERICS"
-  "cvtzri	%1,%0"
-  [(set_attr "type" "fpcvt")])
-
-(define_insn "fixuns_truncxfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(unsigned_fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))]
-  "TARGET_NUMERICS"
-  "cvtzri	%1,%0"
-  [(set_attr "type" "fpcvt")])
-
-(define_insn "addxf3"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(plus:XF (match_operand:XF 1 "nonmemory_operand" "%fGH")
-		 (match_operand:XF 2 "nonmemory_operand" "fGH")))]
-  "TARGET_NUMERICS"
-  "addr	%1,%2,%0"
-  [(set_attr "type" "fpadd")])
-
-(define_insn "subxf3"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(minus:XF (match_operand:XF 1 "nonmemory_operand" "fGH")
-		  (match_operand:XF 2 "nonmemory_operand" "fGH")))]
-  "TARGET_NUMERICS"
-  "subr	%2,%1,%0"
-  [(set_attr "type" "fpadd")])
-
-(define_insn "mulxf3"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(mult:XF (match_operand:XF 1 "nonmemory_operand" "%fGH")
-		 (match_operand:XF 2 "nonmemory_operand" "fGH")))]
-  "TARGET_NUMERICS"
-  "mulr	%1,%2,%0"
-  [(set_attr "type" "fpmul")])
-
-(define_insn "divxf3"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(div:XF (match_operand:XF 1 "nonmemory_operand" "fGH")
-		(match_operand:XF 2 "nonmemory_operand" "fGH")))]
-  "TARGET_NUMERICS"
-  "divr	%2,%1,%0"
-  [(set_attr "type" "fpdiv")])
-
-(define_insn "negxf2"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(neg:XF (match_operand:XF 1 "register_operand" "f")))]
-  "TARGET_NUMERICS"
-  "subr	%1,0f0.0,%0"
-  [(set_attr "type" "fpadd")])
-
-(define_insn "absxf2"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(abs:XF (match_operand:XF 1 "register_operand" "f")))]
-  "(TARGET_NUMERICS)"
-  "cpysre	%1,0f0.0,%0"
-  [(set_attr "type" "fpmove")])
-
-;; Arithmetic shift instructions.
-
-;; The shli instruction generates an overflow fault if the sign changes.
-;; In the case of overflow, it does not give the natural result, it instead
-;; gives the last shift value before the overflow.  We can not use this
-;; instruction because gcc thinks that arithmetic left shift and logical
-;; left shift are identical, and sometimes canonicalizes the logical left
-;; shift to an arithmetic left shift.  Therefore we must always use the
-;; logical left shift instruction.
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashift:SI (match_operand:SI 1 "arith_operand" "dI")
-		   (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "shlo	%2,%1,%0"
-  [(set_attr "type" "alu2")])
-
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashiftrt:SI (match_operand:SI 1 "arith_operand" "dI")
-		     (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "shri	%2,%1,%0"
-  [(set_attr "type" "alu2")])
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(lshiftrt:SI (match_operand:SI 1 "arith_operand" "dI")
-		   (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "shro	%2,%1,%0"
-  [(set_attr "type" "alu2")])
-
-;; Unconditional and other jump instructions.
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "b	%l0"
-  [(set_attr "type" "branch")])
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
-  ""
-  "bx	%a0"
-  [(set_attr "type" "branch")])
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "d"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "*
-{
-  if (flag_pic)
-    return \"bx	%l1(%0)\";
-  else
-    return \"bx	(%0)\";
-}"
-  [(set_attr "type" "branch")])
-
-;;- jump to subroutine
-
-(define_expand "call"
-  [(call (match_operand:SI 0 "memory_operand" "m")
-	 (match_operand:SI 1 "immediate_operand" "i"))]
-  ""
-  "
-{
-  emit_insn (gen_call_internal (operands[0], operands[1],
-				virtual_outgoing_args_rtx));
-  DONE;
-}")
-
-;; We need a call saved register allocated for the match_scratch, so we use
-;; 'l' because all local registers are call saved.
-
-;; ??? I would prefer to use a match_scratch here, but match_scratch allocated
-;; registers can't be used for spills.  In a function with lots of calls,
-;; local-alloc may allocate all local registers to a match_scratch, leaving
-;; no local registers available for spills.
-
-(define_insn "call_internal"
-  [(call (match_operand:SI 0 "memory_operand" "m")
-	 (match_operand:SI 1 "immediate_operand" "i"))
-   (use (match_operand:SI 2 "address_operand" "p"))
-   (clobber (reg:SI 19))]
-  ""
-  "* return i960_output_call_insn (operands[0], operands[1], operands[2],
-				   insn);"
-  [(set_attr "type" "call")])
-
-(define_expand "call_value"
-  [(set (match_operand 0 "register_operand" "=d")
-	(call (match_operand:SI 1 "memory_operand" "m")
-	      (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "
-{
-  emit_insn (gen_call_value_internal (operands[0], operands[1], operands[2],
-				      virtual_outgoing_args_rtx));
-  DONE;
-}")
-
-;; We need a call saved register allocated for the match_scratch, so we use
-;; 'l' because all local registers are call saved.
-
-(define_insn "call_value_internal"
-  [(set (match_operand 0 "register_operand" "=d")
-	(call (match_operand:SI 1 "memory_operand" "m")
-	      (match_operand:SI 2 "immediate_operand" "i")))
-   (use (match_operand:SI 3 "address_operand" "p"))
-   (clobber (reg:SI 19))]
-  ""
-  "* return i960_output_call_insn (operands[1], operands[2], operands[3],
-				   insn);"
-  [(set_attr "type" "call")])
-
-(define_insn "return"
-  [(return)]
-  ""
-  "* return i960_output_ret_insn (insn);"
-  [(set_attr "type" "branch")])
-
-;; A return instruction.  Used only by nonlocal_goto to change the
-;; stack pointer, frame pointer, previous frame pointer and the return
-;; instruction pointer.
-(define_insn "ret"
-  [(use (reg:SI 16))
-   (unspec_volatile [(const_int 0)] 3)]
-  ""
-  "ret"
-  [(set_attr "type" "branch")
-   (set_attr "length" "1")])
-
-(define_expand "nonlocal_goto"
-  [(match_operand:SI 0 "" "")
-   (match_operand:SI 1 "general_operand" "")
-   (match_operand:SI 2 "general_operand" "")
-   (match_operand:SI 3 "general_operand" "")]
-  ""
-  "
-{
-  rtx fp = operands[1];
-  rtx new_pc = operands[3];
-  rtx stack = operands[2];
-  rtx val = operands[0];
-
-  /* This code isn't sufficient to make nonlocal_gotos for nested
-     functions to work fully.  Here we assume that the passed frame
-     pointer is a real hard frame pointer, not a
-     virtual_stack_vars_rtx type of frame.  */
-
-  /* We must restore the stack pointer, frame pointer, previous frame
-     pointer and the return instruction pointer.  Since the ret
-     instruction does all this for us with one instruction, we arrange
-     everything so that ret will do everything we need done.  */
-
-  if (GET_CODE (fp) != REG)
-    fp = force_reg (Pmode, fp);
-  if (GET_CODE (val) != REG)
-    val = force_reg (Pmode, val);
-  if (GET_CODE (new_pc) != REG)
-    new_pc = force_reg (Pmode, new_pc);
-
-
-  /* First, we must flush the register windows, so that we can modify
-     the saved local registers on the stack directly and because we
-     are going to change the previous frame pointer.  */
-
-  emit_insn (gen_flush_register_windows ());
-
-  /* Next, we put the address that we want to transfer to, into the
-     saved $rip value on the stack.  Once we ret below, that value
-     will be loaded into the pc (IP).  */
-
-  emit_move_insn (gen_rtx (MEM, SImode,
-			   plus_constant (fp, 8)),
-		  new_pc);
-
-#if 0
-  /* Next, we put the value into the static chain register's save
-     area on the stack.  After the ret below, this will be loaded into
-     r3 (the static chain).  */
-     
-  emit_move_insn (gen_rtx (MEM, SImode,
-			   plus_constant (fp, 12)),
-		  val);
-#endif
-
-  /* We now load pfp (the previous frame pointer) with the value that
-     we want fp to be.  */
-
-  emit_move_insn (gen_rtx (REG, SImode, 16), fp);
-
-  /* And finally, we can now just ret to get all the values saved
-     above into all the right registers, and also, all the local
-     register that were in use in the function, are restored from
-     their saved values (from the call instruction) on the stack
-     because we are very careful to ret from the exact save area in
-     use during the original call.  */
-
-  emit_insn (gen_ret ());
-  emit_barrier ();
-  DONE;
-}")
-
-;; Special insn to flush register windows.
-(define_insn "flush_register_windows"
-  [(unspec_volatile [(const_int 0)] 1)]
-  ""
-  "flushreg"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "")
-
-;; Various peephole optimizations for multiple-word moves, loads, and stores.
-;; Multiple register moves.
-
-;; Matched 5/28/91
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "register_operand" "r"))
-   (set (match_operand:SI 2 "register_operand" "=r")
-	(match_operand:SI 3 "register_operand" "r"))
-   (set (match_operand:SI 4 "register_operand" "=r")
-	(match_operand:SI 5 "register_operand" "r"))
-   (set (match_operand:SI 6 "register_operand" "=r")
-	(match_operand:SI 7 "register_operand" "r"))]
-  "((REGNO (operands[0]) & 3) == 0)
-   && ((REGNO (operands[1]) & 3) == 0)
-   && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
-   && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
-   && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
-   && (REGNO (operands[1]) + 2 == REGNO (operands[5]))
-   && (REGNO (operands[0]) + 3 == REGNO (operands[6]))
-   && (REGNO (operands[1]) + 3 == REGNO (operands[7]))"
-  "movq	%1,%0")
-
-;; Matched 4/17/92
-(define_peephole
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(match_operand:DI 1 "register_operand" "r"))
-   (set (match_operand:DI 2 "register_operand" "=r")
-	(match_operand:DI 3 "register_operand" "r"))]
-  "((REGNO (operands[0]) & 3) == 0)
-   && ((REGNO (operands[1]) & 3) == 0)
-   && (REGNO (operands[0]) + 2 == REGNO (operands[2]))
-   && (REGNO (operands[1]) + 2 == REGNO (operands[3]))"
-  "movq	%1,%0")
-
-;; Matched 4/17/92
-(define_peephole
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(match_operand:DI 1 "register_operand" "r"))
-   (set (match_operand:SI 2 "register_operand" "=r")
-	(match_operand:SI 3 "register_operand" "r"))
-   (set (match_operand:SI 4 "register_operand" "=r")
-	(match_operand:SI 5 "register_operand" "r"))]
-  "((REGNO (operands[0]) & 3) == 0)
-   && ((REGNO (operands[1]) & 3) == 0)
-   && (REGNO (operands[0]) + 2 == REGNO (operands[2]))
-   && (REGNO (operands[1]) + 2 == REGNO (operands[3]))
-   && (REGNO (operands[0]) + 3 == REGNO (operands[4]))
-   && (REGNO (operands[1]) + 3 == REGNO (operands[5]))"
-  "movq	%1,%0")
-
-;; Matched 4/17/92
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "register_operand" "r"))
-   (set (match_operand:SI 2 "register_operand" "=r")
-	(match_operand:SI 3 "register_operand" "r"))
-   (set (match_operand:DI 4 "register_operand" "=r")
-	(match_operand:DI 5 "register_operand" "r"))]
-  "((REGNO (operands[0]) & 3) == 0)
-   && ((REGNO (operands[1]) & 3) == 0)
-   && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
-   && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
-   && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
-   && (REGNO (operands[1]) + 2 == REGNO (operands[5]))"
-  "movq	%1,%0")
-
-;; Matched 4/17/92
-(define_peephole
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(match_operand:DI 1 "register_operand" "r"))
-   (set (match_operand:SI 2 "register_operand" "=r")
-	(match_operand:SI 3 "register_operand" "r"))]
-  "((REGNO (operands[0]) & 3) == 0)
-   && ((REGNO (operands[1]) & 3) == 0)
-   && (REGNO (operands[0]) + 2 == REGNO (operands[2]))
-   && (REGNO (operands[1]) + 2 == REGNO (operands[3]))"
-  "movt	%1,%0")
-
-;; Matched 5/28/91
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "register_operand" "r"))
-   (set (match_operand:SI 2 "register_operand" "=r")
-	(match_operand:SI 3 "register_operand" "r"))
-   (set (match_operand:SI 4 "register_operand" "=r")
-	(match_operand:SI 5 "register_operand" "r"))]
-  "((REGNO (operands[0]) & 3) == 0)
-   && ((REGNO (operands[1]) & 3) == 0)
-   && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
-   && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
-   && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
-   && (REGNO (operands[1]) + 2 == REGNO (operands[5]))"
-  "movt	%1,%0")
-
-;; Matched 5/28/91
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "register_operand" "r"))
-   (set (match_operand:SI 2 "register_operand" "=r")
-	(match_operand:SI 3 "register_operand" "r"))]
-  "((REGNO (operands[0]) & 1) == 0)
-   && ((REGNO (operands[1]) & 1) == 0)
-   && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
-   && (REGNO (operands[1]) + 1 == REGNO (operands[3]))"
-  "movl	%1,%0")
-
-; Multiple register loads.
-
-;; Matched 6/15/91
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "immediate_operand" "n"))))
-   (set (match_operand:SI 3 "register_operand" "=r")
-	(mem:SI (plus:SI (match_dup 1)
-			 (match_operand:SI 4 "immediate_operand" "n"))))
-   (set (match_operand:SI 5 "register_operand" "=r")
-	(mem:SI (plus:SI (match_dup 1)
-			 (match_operand:SI 6 "immediate_operand" "n"))))
-   (set (match_operand:SI 7 "register_operand" "=r")
-	(mem:SI (plus:SI (match_dup 1)
-			 (match_operand:SI 8 "immediate_operand" "n"))))]
-  "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
-   && (REGNO (operands[1]) != REGNO (operands[0]))
-   && (REGNO (operands[0]) + 1 == REGNO (operands[3]))
-   && (REGNO (operands[1]) != REGNO (operands[3]))
-   && (REGNO (operands[0]) + 2 == REGNO (operands[5]))
-   && (REGNO (operands[1]) != REGNO (operands[5]))
-   && (REGNO (operands[0]) + 3 == REGNO (operands[7]))
-   && (INTVAL (operands[2]) + 4 == INTVAL (operands[4]))
-   && (INTVAL (operands[2]) + 8 == INTVAL (operands[6]))
-   && (INTVAL (operands[2]) + 12 == INTVAL (operands[8])))"
-  "ldq	%2(%1),%0")
-
-;; Matched 5/28/91
-(define_peephole
-  [(set (match_operand:DF 0 "register_operand" "=d")
-	(mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "immediate_operand" "n"))))
-   (set (match_operand:DF 3 "register_operand" "=d")
-	(mem:DF (plus:SI (match_dup 1)
-			 (match_operand:SI 4 "immediate_operand" "n"))))]
-  "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
-   && (REGNO (operands[1]) != REGNO (operands[0]))
-   && (REGNO (operands[0]) + 2 == REGNO (operands[3]))
-   && (REGNO (operands[1]) != REGNO (operands[3]))
-   && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))"
-  "ldq	%2(%1),%0")
-
-;; Matched 1/24/92
-(define_peephole
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(mem:DI (plus:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "immediate_operand" "n"))))
-   (set (match_operand:DI 3 "register_operand" "=d")
-	(mem:DI (plus:SI (match_dup 1)
-			 (match_operand:SI 4 "immediate_operand" "n"))))]
-  "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
-   && (REGNO (operands[1]) != REGNO (operands[0]))
-   && (REGNO (operands[0]) + 2 == REGNO (operands[3]))
-   && (REGNO (operands[1]) != REGNO (operands[3]))
-   && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))"
-  "ldq	%2(%1),%0")
-
-;; Matched 4/17/92
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(mem:SI (match_operand:SI 1 "register_operand" "d")))
-   (set (match_operand:SI 2 "register_operand" "=d")
-	(mem:SI (plus:SI (match_dup 1)
-			 (match_operand:SI 3 "immediate_operand" "n"))))
-   (set (match_operand:SI 4 "register_operand" "=d")
-	(mem:SI (plus:SI (match_dup 1)
-			 (match_operand:SI 5 "immediate_operand" "n"))))
-   (set (match_operand:SI 6 "register_operand" "=d")
-	(mem:SI (plus:SI (match_dup 1)
-			 (match_operand:SI 7 "immediate_operand" "n"))))]
-  "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0)
-   && (REGNO (operands[1]) != REGNO (operands[0]))
-   && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
-   && (REGNO (operands[1]) != REGNO (operands[2]))
-   && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
-   && (REGNO (operands[1]) != REGNO (operands[4]))
-   && (REGNO (operands[0]) + 3 == REGNO (operands[6]))
-   && (INTVAL (operands[3]) == 4)
-   && (INTVAL (operands[5]) == 8)
-   && (INTVAL (operands[7]) == 12))"
-  "ldq	(%1),%0")
-
-;; Matched 5/28/91
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "immediate_operand" "n"))))
-   (set (match_operand:SI 3 "register_operand" "=d")
-	(mem:SI (plus:SI (match_dup 1)
-			 (match_operand:SI 4 "immediate_operand" "n"))))
-   (set (match_operand:SI 5 "register_operand" "=d")
-	(mem:SI (plus:SI (match_dup 1)
-			 (match_operand:SI 6 "immediate_operand" "n"))))]
-  "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
-   && (REGNO (operands[1]) != REGNO (operands[0]))
-   && (REGNO (operands[0]) + 1 == REGNO (operands[3]))
-   && (REGNO (operands[1]) != REGNO (operands[3]))
-   && (REGNO (operands[0]) + 2 == REGNO (operands[5]))
-   && (INTVAL (operands[2]) + 4 == INTVAL (operands[4]))
-   && (INTVAL (operands[2]) + 8 == INTVAL (operands[6])))"
-  "ldt	%2(%1),%0")
-
-;; Matched 6/15/91
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(mem:SI (match_operand:SI 1 "register_operand" "d")))
-   (set (match_operand:SI 2 "register_operand" "=d")
-	(mem:SI (plus:SI (match_dup 1)
-			 (match_operand:SI 3 "immediate_operand" "n"))))
-   (set (match_operand:SI 4 "register_operand" "=d")
-	(mem:SI (plus:SI (match_dup 1)
-			 (match_operand:SI 5 "immediate_operand" "n"))))]
-  "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0)
-   && (REGNO (operands[1]) != REGNO (operands[0]))
-   && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
-   && (REGNO (operands[1]) != REGNO (operands[2]))
-   && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
-   && (INTVAL (operands[3]) == 4)
-   && (INTVAL (operands[5]) == 8))"
-  "ldt	(%1),%0")
-
-;; Matched 5/28/91
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "immediate_operand" "n"))))
-   (set (match_operand:SI 3 "register_operand" "=d")
-	(mem:SI (plus:SI (match_dup 1)
-			 (match_operand:SI 4 "immediate_operand" "n"))))]
-  "(i960_si_di (operands[1], operands[2]) && ((REGNO (operands[0]) & 1) == 0)
-   && (REGNO (operands[1]) != REGNO (operands[0]))
-   && (REGNO (operands[0]) + 1 == REGNO (operands[3]))
-   && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])))"
-  "ldl	%2(%1),%0")
-
-;; Matched 5/28/91
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(mem:SI (match_operand:SI 1 "register_operand" "d")))
-   (set (match_operand:SI 2 "register_operand" "=d")
-	(mem:SI (plus:SI (match_dup 1)
-			 (match_operand:SI 3 "immediate_operand" "n"))))]
-  "(i960_si_di (operands[1], 0) && ((REGNO (operands[0]) & 1) == 0)
-   && (REGNO (operands[1]) != REGNO (operands[0]))
-   && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
-   && (INTVAL (operands[3]) == 4))"
-  "ldl	(%1),%0")
-
-; Multiple register stores.
-
-;; Matched 5/28/91
-(define_peephole
-  [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d")
-			 (match_operand:SI 1 "immediate_operand" "n")))
-	(match_operand:SI 2 "register_operand" "d"))
-   (set (mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 3 "immediate_operand" "n")))
-	(match_operand:SI 4 "register_operand" "d"))
-   (set (mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 5 "immediate_operand" "n")))
-	(match_operand:SI 6 "register_operand" "d"))
-   (set (mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 7 "immediate_operand" "n")))
-	(match_operand:SI 8 "register_operand" "d"))]
-  "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
-   && (REGNO (operands[2]) + 1 == REGNO (operands[4]))
-   && (REGNO (operands[2]) + 2 == REGNO (operands[6]))
-   && (REGNO (operands[2]) + 3 == REGNO (operands[8]))
-   && (INTVAL (operands[1]) + 4 == INTVAL (operands[3]))
-   && (INTVAL (operands[1]) + 8 == INTVAL (operands[5]))
-   && (INTVAL (operands[1]) + 12 == INTVAL (operands[7])))"
-  "stq	%2,%1(%0)")
-
-;; Matched 6/16/91
-(define_peephole
-  [(set (mem:DF (plus:SI (match_operand:SI 0 "register_operand" "d")
-			 (match_operand:SI 1 "immediate_operand" "n")))
-	(match_operand:DF 2 "register_operand" "d"))
-   (set (mem:DF (plus:SI (match_dup 0)
-			 (match_operand:SI 3 "immediate_operand" "n")))
-	(match_operand:DF 4 "register_operand" "d"))]
-  "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
-   && (REGNO (operands[2]) + 2 == REGNO (operands[4]))
-   && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))"
-  "stq	%2,%1(%0)")
-
-;; Matched 4/17/92
-(define_peephole
-  [(set (mem:DI (plus:SI (match_operand:SI 0 "register_operand" "d")
-			 (match_operand:SI 1 "immediate_operand" "n")))
-	(match_operand:DI 2 "register_operand" "d"))
-   (set (mem:DI (plus:SI (match_dup 0)
-			 (match_operand:SI 3 "immediate_operand" "n")))
-	(match_operand:DI 4 "register_operand" "d"))]
-  "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
-   && (REGNO (operands[2]) + 2 == REGNO (operands[4]))
-   && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))"
-  "stq	%2,%1(%0)")
-
-;; Matched 1/23/92
-(define_peephole
-  [(set (mem:SI (match_operand:SI 0 "register_operand" "d"))
-	(match_operand:SI 1 "register_operand" "d"))
-   (set (mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 2 "immediate_operand" "n")))
-	(match_operand:SI 3 "register_operand" "d"))
-   (set (mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 4 "immediate_operand" "n")))
-	(match_operand:SI 5 "register_operand" "d"))
-   (set (mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 6 "immediate_operand" "n")))
-	(match_operand:SI 7 "register_operand" "d"))]
-  "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0)
-   && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
-   && (REGNO (operands[1]) + 2 == REGNO (operands[5]))
-   && (REGNO (operands[1]) + 3 == REGNO (operands[7]))
-   && (INTVAL (operands[2]) == 4)
-   && (INTVAL (operands[4]) == 8)
-   && (INTVAL (operands[6]) == 12))"
-  "stq	%1,(%0)")
-
-;; Matched 5/29/91
-(define_peephole
-  [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d")
-			 (match_operand:SI 1 "immediate_operand" "n")))
-	(match_operand:SI 2 "register_operand" "d"))
-   (set (mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 3 "immediate_operand" "n")))
-	(match_operand:SI 4 "register_operand" "d"))
-   (set (mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 5 "immediate_operand" "n")))
-	(match_operand:SI 6 "register_operand" "d"))]
-  "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
-   && (REGNO (operands[2]) + 1 == REGNO (operands[4]))
-   && (REGNO (operands[2]) + 2 == REGNO (operands[6]))
-   && (INTVAL (operands[1]) + 4 == INTVAL (operands[3]))
-   && (INTVAL (operands[1]) + 8 == INTVAL (operands[5])))"
-  "stt	%2,%1(%0)")
-
-;; Matched 5/29/91
-(define_peephole
-  [(set (mem:SI (match_operand:SI 0 "register_operand" "d"))
-	(match_operand:SI 1 "register_operand" "d"))
-   (set (mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 2 "immediate_operand" "n")))
-	(match_operand:SI 3 "register_operand" "d"))
-   (set (mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 4 "immediate_operand" "n")))
-	(match_operand:SI 5 "register_operand" "d"))]
-  "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0)
-   && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
-   && (REGNO (operands[1]) + 2 == REGNO (operands[5]))
-   && (INTVAL (operands[2]) == 4)
-   && (INTVAL (operands[4]) == 8))"
-  "stt	%1,(%0)")
-
-;; Matched 5/28/91
-(define_peephole
-  [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d")
-			 (match_operand:SI 1 "immediate_operand" "n")))
-	(match_operand:SI 2 "register_operand" "d"))
-   (set (mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 3 "immediate_operand" "n")))
-	(match_operand:SI 4 "register_operand" "d"))]
-  "(i960_si_di (operands[0], operands[1]) && ((REGNO (operands[2]) & 1) == 0)
-   && (REGNO (operands[2]) + 1 == REGNO (operands[4]))
-   && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])))"
-  "stl	%2,%1(%0)")
-
-;; Matched 5/28/91
-(define_peephole
-  [(set (mem:SI (match_operand:SI 0 "register_operand" "d"))
-	(match_operand:SI 1 "register_operand" "d"))
-   (set (mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 2 "immediate_operand" "n")))
-	(match_operand:SI 3 "register_operand" "d"))]
-  "(i960_si_di (operands[0], 0) && ((REGNO (operands[1]) & 1) == 0)
-   && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
-   && (INTVAL (operands[2]) == 4))"
-  "stl	%1,(%0)")
diff --git a/gcc/config/i960/rtems.h b/gcc/config/i960/rtems.h
deleted file mode 100755
index 909fc73..0000000
--- a/gcc/config/i960/rtems.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Definitions for rtems targeting an Intel i960.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i960/i960-coff.h"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Drtems -D__rtems__ \
-   -Asystem(rtems) -Acpu(i960) -Amachine(i960)"
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#ifndef TARGET_MEM_FUNCTIONS
-#define TARGET_MEM_FUNCTIONS
-#endif
diff --git a/gcc/config/i960/t-960bare b/gcc/config/i960/t-960bare
deleted file mode 100755
index 37929bb..0000000
--- a/gcc/config/i960/t-960bare
+++ /dev/null
@@ -1,24 +0,0 @@
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c xp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' > dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-xp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define EXTENDED_FLOAT_STUBS' > xp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> xp-bit.c
-
-MULTILIB_OPTIONS=mnumerics/msoft-float mlong-double-64
-MULTILIB_DIRNAMES=float soft-float ld64
-MULTILIB_MATCHES=mnumerics=msb mnumerics=msc mnumerics=mkb mnumerics=mkc mnumerics=mmc mnumerics=mcb mnumerics=mcc mnumerics=mjf msoft-float=msa msoft-float=mka msoft-float=mca msoft-float=mcf
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/i960/t-vxworks960 b/gcc/config/i960/t-vxworks960
deleted file mode 100755
index 851e7bd..0000000
--- a/gcc/config/i960/t-vxworks960
+++ /dev/null
@@ -1,27 +0,0 @@
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# We don't want to put exit in libgcc.a for VxWorks, because VxWorks
-# does not have _exit.
-TARGET_LIBGCC2_CFLAGS = -Dexit=unused_exit
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c xp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' > dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-xp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define EXTENDED_FLOAT_STUBS' > xp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> xp-bit.c
-
-MULTILIB_OPTIONS=mnumerics/msoft-float mlong-double-64
-MULTILIB_DIRNAMES=float soft-float ld64
-MULTILIB_MATCHES=mnumerics=msb mnumerics=msc mnumerics=mkb mnumerics=mkc mnumerics=mmc mnumerics=mcb mnumerics=mcc msoft-float=msa msoft-float=mka msoft-float=mca msoft-float=mcf
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/i960/vx960-coff.h b/gcc/config/i960/vx960-coff.h
deleted file mode 100755
index 91879dd..0000000
--- a/gcc/config/i960/vx960-coff.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Vxworks i960 version.
-   Copyright (C) 1994, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file just exists to give specs for the 960 running on VxWorks.
-   VxWorks does all the library stuff itself.  */
-
-#define MULTILIB_DEFAULTS { "msoft-float" }
-
-#undef LIB_SPEC
-#define LIB_SPEC ""
-
-/* VxWorks provides the functionality of crt0.o and friends itself.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-
-/* Predefine vxworks.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Dvxworks -Acpu(i960) -Amachine(i960)"
-
-/* The VxWorks header files expect the compiler to define CPU to a
-   magic number.  Note that we define CPU here even if the user
-   has specified -ansi.  This violates user namespace, but the VxWorks
-   headers, and potentially user code, all explicitly rely upon the
-   definition of CPU in order to get the proper processor information.  */
-
-#undef CPP_SPEC
-#define	CPP_SPEC "%{mic*:-D__i960\
-			%{mka:-D__i960KA}%{mkb:-D__i960KB}\
-			%{msa:-D__i960SA}%{msb:-D__i960SB}\
-			%{mmc:-D__i960MC}\
-			%{mca:-D__i960CA}%{mcc:-D__i960CC}\
-			%{mcf:-D__i960CF}}\
-	%{mka:-D__i960KA__ -D__i960_KA__ -DCPU=I960KA}\
-	%{mkb:-D__i960KB__ -D__i960_KB__ -DCPU=I960KB}\
-	%{msa:-D__i960SA__ -D__i960_SA__}\
-	%{msb:-D__i960SB__ -D__i960_SB__}\
-	%{mmc:-D__i960MC__ -D__i960_MC__}\
-	%{mca:-D__i960CA__ -D__i960_CA__ -DCPU=I960CA}\
-	%{mcc:-D__i960CC__ -D__i960_CC__}\
-	%{mcf:-D__i960CF__ -D__i960_CF__}\
-	%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
-		%{!mcc:%{!mcf:-D__i960_CA -D__i960CA__ -DCPU=I960CA\
-			      %{mic*:-D__i960CA}}}}}}}}}\
-	%{mlong-double-64:-D__LONG_DOUBLE_64__}"
-
-/* Default to -mca.  */
-
-#undef CC1_SPEC
-#define CC1_SPEC \
-	"%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-mca}}}}}}}}\
-	 %{!gs*:%{!gc*:%{mbout:%{g*:-gstabs}}\
-		       %{mcoff:%{g*:-gcoff}}\
-		       %{!mbout:%{!mcoff:%{g*:-gcoff}}}}}"
diff --git a/gcc/config/i960/vx960.h b/gcc/config/i960/vx960.h
deleted file mode 100755
index ebf70dc..0000000
--- a/gcc/config/i960/vx960.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Vxworks i960 version.
-   Copyright (C) 1994, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file just exists to give specs for the 960 running on VxWorks. 
-   VxWorks does all the library stuff itself.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC ""
-
-/* VxWorks provides the functionality of crt0.o and friends itself.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
diff --git a/gcc/config/i960/xm-i960.h b/gcc/config/i960/xm-i960.h
deleted file mode 100755
index 09dcadf..0000000
--- a/gcc/config/i960/xm-i960.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Configuration for GNU C-compiler for Intel 960 family
-   Copyright (C) 1987, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* If not compiled with GNU C, use the C alloca */
-#ifndef __GNUC__
-#define USE_C_ALLOCA
-#endif
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
diff --git a/gcc/config/libgloss.h b/gcc/config/libgloss.h
deleted file mode 100755
index 2f2ba56..0000000
--- a/gcc/config/libgloss.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* libgloss.h -- operating system specific defines to be used when
-   targeting GCC for Libgloss supported targets.
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* The libgloss standard for crt0.s has the name based on the command line
-   option. */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared:%{pg:pgcrt0%O%s}%{!pg:%{p:pcrt0%O%s}%{!p:crt0%O%s}}}"
-
-/* This file used to force LINK_SPEC to be the null string, but that is not
-   correct.  LINK_SPEC is used to pass machine specific arguments to the
-   linker and hence can not be redefined here.  LINK_SPEC is never used to
-   specify startup files or libraries, so it should never conflict with
-   libgloss.  */
-
-/* Don't set the target flags, this is done by the linker script */
-#undef LIB_SPEC
-#define LIB_SPEC ""
diff --git a/gcc/config/linux-aout.h b/gcc/config/linux-aout.h
deleted file mode 100755
index ca8a39d..0000000
--- a/gcc/config/linux-aout.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Definitions for Linux-based GNU systems.
-   Copyright (C) 1995, 1997 Free Software Foundation, Inc.
-   Contributed by H.J. Lu (hjl@nynexst.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Don't assume anything about the header files. */
-#define NO_IMPLICIT_EXTERN_C
-
-#undef HAVE_ATEXIT
-#define HAVE_ATEXIT
-
-/* GNU/Linux uses ctype from glibc.a. I am not sure how complete it is.
-   For now, we play safe. It may change later. */
-
-#if 0
-#undef MULTIBYTE_CHARS
-#define MULTIBYTE_CHARS	1
-#endif
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC  "%{pg:gcrt0.o%s} %{!pg:%{p:gcrt0.o%s} %{!p:crt0.o%s}} %{static:-static}"
-
-#undef ASM_APP_ON
-#define ASM_APP_ON "#APP\n"
-
-#undef ASM_APP_OFF
-#define ASM_APP_OFF "#NO_APP\n"
-
-#define SET_ASM_OP	".set"
-
-/* We need that too. */
-#define HANDLE_SYSV_PRAGMA
diff --git a/gcc/config/linux.h b/gcc/config/linux.h
deleted file mode 100755
index b619d01..0000000
--- a/gcc/config/linux.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Definitions for Linux-based GNU systems with ELF format
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Eric Youngdale.
-   Modified for stabs-in-ELF by H.J. Lu (hjl@lucon.org).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Don't assume anything about the header files. */
-#define NO_IMPLICIT_EXTERN_C
-
-#undef HAVE_ATEXIT
-#define HAVE_ATEXIT
-
-/* GNU/Linux uses ctype from glibc.a. I am not sure how complete it is.
-   For now, we play safe. It may change later. */
-
-#if 0
-#undef MULTIBYTE_CHARS
-#define MULTIBYTE_CHARS 1
-#endif
-
-#undef ASM_APP_ON
-#define ASM_APP_ON "#APP\n"
-
-#undef ASM_APP_OFF
-#define ASM_APP_OFF "#NO_APP\n"
-
-#define SET_ASM_OP	".set"
-
-/* Use stabs instead of DWARF debug format.  */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-#include "svr4.h"
-
-#undef MD_EXEC_PREFIX
-#undef MD_STARTFILE_PREFIX
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)						\
-  do {									\
-	output_file_directive (FILE, main_input_filename);		\
-	fprintf (FILE, "\t.version\t\"01.01\"\n");			\
-  } while (0)
-
-/* Provide a STARTFILE_SPEC appropriate for GNU/Linux.  Here we add
-   the GNU/Linux magical crtbegin.o file (see crtstuff.c) which
-   provides part of the support for getting C++ file-scope static
-   object constructed before entering `main'. */
-   
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{!shared: \
-     %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} \
-		       %{!p:%{profile:gcrt1.o%s} \
-			 %{!profile:crt1.o%s}}}} \
-   crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}"
-
-/* Provide a ENDFILE_SPEC appropriate for GNU/Linux.  Here we tack on
-   the GNU/Linux magical crtend.o file (see crtstuff.c) which
-   provides part of the support for getting C++ file-scope static
-   object constructed before entering `main', followed by a normal
-   GNU/Linux "finalizer" file, `crtn.o'.  */
-
-#undef	ENDFILE_SPEC
-#define ENDFILE_SPEC \
-  "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s"
-
-/* This is for -profile to use -lc_p instead of -lc. */
-#ifndef CC1_SPEC
-#define CC1_SPEC "%{profile:-p}"
-#endif
-
-#ifndef USE_GNULIBC_1
-#undef DEFAULT_VTABLE_THUNKS
-#define DEFAULT_VTABLE_THUNKS 1
-#endif
-
-#undef	LIB_SPEC
-/* We no longer link with libc_p.a or libg.a by default. If you
-   want to profile or debug the GNU/Linux C library, please add
-   -profile or -ggdb to LDFLAGS at the link time, respectively. */
-#if 1
-#ifdef USE_GNULIBC_1
-#define LIB_SPEC \
-  "%{!shared: %{p:-lgmon} %{pg:-lgmon} %{profile:-lgmon -lc_p} \
-     %{!profile:%{!ggdb:-lc} %{ggdb:-lg}}}"
-#else
-#define LIB_SPEC \
-  "%{shared: -lc} \
-   %{!shared: %{mieee-fp:-lieee} %{pthread:-lpthread} \
-	%{profile:-lc_p} %{!profile: -lc}}"
-#endif
-#else
-#define LIB_SPEC \
-  "%{!shared: \
-     %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \
-       %{!p:%{!pg:%{!g*:-lc} %{g*:-lg}}}}"
-#endif
diff --git a/gcc/config/lynx-ng.h b/gcc/config/lynx-ng.h
deleted file mode 100755
index a3a9c37..0000000
--- a/gcc/config/lynx-ng.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* Target independent definitions for LynxOS, using Lynx's old as and ld.
-   Copyright (C) 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This is for backwards compatibility with older Lynx tools, which use
-   a version of a.out format. */
-
-#undef ASM_SPEC
-#define ASM_SPEC "%{mcoff:-C}"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{mthreads:-D_MULTITHREADED}  \
-  %{mposix:-D_POSIX_SOURCE}  \
-  %{msystem-v:-I/usr/include_v}"
-
-/* Provide required defaults for linker switches.  */
-
-#undef LINK_SPEC
-#define LINK_SPEC "%{msystem-v:-V} %{mcoff:-k}"
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{mthreads:-L/lib/thread/}%{msystem-v:-lc_v}%{!msystem-v:%{mposix:-lc_p} -lc}"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{p:%{mcoff:pinit1.o%s}%{!mcoff:pinit.o%s}}%{!p:%{msystem-v:%{mcoff:vinit1.o%s}%{!mcoff:vinit.o%s}}%{!msystem-v:%{mcoff:init1.o%s}%{!mcoff:init.o%s}}}"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "%{mcoff:initn.o%s} %{p:_etext.o%s}"
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "long int"
-
-/* We want to output DBX debugging information.  */
-
-#define DBX_DEBUGGING_INFO
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* We optionally want to be able to produce SDB debugging output so that
-   we can create debuggable SDB/coff files.  This won't be needed when
-   stabs-in-coff works.  */
-
-#define SDB_DEBUGGING_INFO
-
-/* Generate calls to memcpy, memcmp and memset.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Handle #pragma pack and sometimes #pragma weak.  */
-
-#define HANDLE_SYSV_PRAGMA
-
-#define TARGET_THREADS	(target_flags & MASK_THREADS)
-#define MASK_THREADS	0x40000000
-
-#define TARGET_POSIX	(target_flags & MASK_POSIX)
-#define MASK_POSIX	0x20000000
-
-#define TARGET_SYSTEM_V	(target_flags & MASK_SYSTEM_V)
-#define MASK_SYSTEM_V	0x10000000
-
-#define TARGET_COFF	(target_flags & MASK_COFF)
-#define MASK_COFF	0x08000000
-
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-    {"threads",		MASK_THREADS},		\
-    {"posix",		MASK_POSIX},		\
-    {"system-v",	MASK_SYSTEM_V},		\
-    {"coff",		MASK_COFF},
-
-#undef SUBTARGET_OVERRIDE_OPTIONS
-#define SUBTARGET_OVERRIDE_OPTIONS \
-{ if (TARGET_SYSTEM_V && profile_flag)			\
-    warning ("-msystem-v and -p are incompatible");		\
-  if (TARGET_SYSTEM_V && TARGET_THREADS)			\
-    warning ("-msystem-v and -mthreads are incompatible"); }
-
-/* Define this so that C++ destructors will use atexit.  */
-
-#define HAVE_ATEXIT
-
-/* This is defined only so that we can find the assembler.  Everything else
-   is in /bin.  */
-
-#define MD_EXEC_PREFIX "/usr/local/lib/gcc-"
-
-/* This is needed because /bin/ld does not handle -L options correctly. */
-
-#define LINK_LIBGCC_SPECIAL_1
-
-/* The Lynx linker considers __main to be a possible entry point, so we
-   must use a different name.  */
-
-#define NAME__MAIN "____main"
-#define SYMBOL__MAIN ____main
diff --git a/gcc/config/lynx.h b/gcc/config/lynx.h
deleted file mode 100755
index 62c790b..0000000
--- a/gcc/config/lynx.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Target independent definitions for LynxOS.
-   Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* LynxOS is a multi-platform Unix, similar to SVR3, but not identical.
-   We can get quite a bit from generic svr3, but have to do some overrides. */
-
-#include "svr3.h"
-
-/* Define various macros, depending on the combination of flags. */
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{mthreads:-D_MULTITHREADED}  \
-  %{mposix:-D_POSIX_SOURCE}  \
-  %{msystem-v:-I/usr/include_v}"
-
-/* No asm spec needed, since using GNU assembler always. */
-
-/* No linker spec needed, since using GNU linker always. */
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{mthreads:-L/lib/thread/}  \
-  %{msystem-v:-lc_v}  \
-  %{!msystem-v:%{mposix:-lc_p} -lc -lm}"
-
-/* Set the appropriate names for the Lynx startfiles. */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{p:%{mthreads:thread/pinit1.o%s}%{!mthreads:pinit1.o%s}}%{!p:%{msystem-v:vinit1.o%s -e_start}%{!msystem-v:%{mthreads:thread/init1.o%s}%{!mthreads:init1.o%s}}}"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "%{p:_etext.o%s}%{!p:initn.o%s}"
-
-/* Override the svr3 versions. */
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "long int"
-
-/* We want to output DBX (stabs) debugging information normally.  */
-
-#define DBX_DEBUGGING_INFO
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* It is convenient to be able to generate standard coff debugging
-   if requested via -gcoff. */
-
-#define SDB_DEBUGGING_INFO
-
-/* Be function-relative for block and source line stab directives. */
-
-#define DBX_BLOCKS_FUNCTION_RELATIVE 1
-
-/* but, to make this work, functions must appear prior to line info */
-
-#define DBX_FUNCTION_FIRST
-
-/* Generate a blank trailing N_SO to mark the end of the .o file, since
-   we can't depend upon the linker to mark .o file boundaries with
-   embedded stabs.  */
-
-#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME)			\
-  fprintf (FILE,							\
-	   "\t.text\n\t.stabs \"\",%d,0,0,Letext\nLetext:\n", N_SO)
-
-#undef  ASM_OUTPUT_SOURCE_LINE
-#define ASM_OUTPUT_SOURCE_LINE(file, line)		\
-  { static int sym_lineno = 1;				\
-    fprintf (file, ".stabn 68,0,%d,.LM%d-",		\
-	     line, sym_lineno);				\
-    assemble_name (file,				\
-		   XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
-    fprintf (file, "\n.LM%d:\n", sym_lineno);		\
-    sym_lineno += 1; }
-
-/* Handle #pragma pack and sometimes #pragma weak.  */
-
-#define HANDLE_SYSV_PRAGMA
-
-/* Some additional command-line options. */
-
-#define TARGET_THREADS	(target_flags & MASK_THREADS)
-#define MASK_THREADS	0x40000000
-
-#define TARGET_POSIX	(target_flags & MASK_POSIX)
-#define MASK_POSIX	0x20000000
-
-#define TARGET_SYSTEM_V	(target_flags & MASK_SYSTEM_V)
-#define MASK_SYSTEM_V	0x10000000
-
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-    {"threads",		MASK_THREADS},		\
-    {"posix",		MASK_POSIX},		\
-    {"system-v",	MASK_SYSTEM_V},
-
-#undef SUBTARGET_OVERRIDE_OPTIONS
-#define SUBTARGET_OVERRIDE_OPTIONS \
-do {								\
-  if (TARGET_SYSTEM_V && profile_flag)				\
-    warning ("-msystem-v and -p are incompatible");		\
-  if (TARGET_SYSTEM_V && TARGET_THREADS)			\
-    warning ("-msystem-v and -mthreads are incompatible");	\
-} while (0)
-
-/* Define this so that C++ destructors will use atexit, since LynxOS
-   calls exit after main returns.  */
-
-#define HAVE_ATEXIT
-
-/* Since init.o et al put all sorts of stuff into the init section,
-   we can't use the standard init section support in crtbegin.o. */
-
-#undef INIT_SECTION_ASM_OP
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_ctors, in_dtors, in_fini
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS					\
-  CONST_SECTION_FUNCTION					\
-  CTORS_SECTION_FUNCTION					\
-  DTORS_SECTION_FUNCTION					\
-  FINI_SECTION_FUNCTION
-
-#undef CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP	".section\t.ctors"
-#undef DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP	".section\t.dtors"
-
-#define INT_ASM_OP		".long"
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#undef ASM_OUTPUT_CONSTRUCTOR
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#undef ASM_OUTPUT_DESTRUCTOR
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-#undef DO_GLOBAL_CTORS_BODY
-#undef DO_GLOBAL_DTORS_BODY
-
-/* LynxOS doesn't have mcount. */
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(file, profile_label_no)
diff --git a/gcc/config/m32r/initfini.c b/gcc/config/m32r/initfini.c
deleted file mode 100755
index 34ef5da..0000000
--- a/gcc/config/m32r/initfini.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* .init/.fini section handling + C++ global constructor/destructor handling.
-   This file is based on crtstuff.c, sol2-crti.asm, sol2-crtn.asm.
-
-Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this file with files
-   compiled with GCC to produce an executable, this does not cause
-   the resulting executable to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-/*  Declare a pointer to void function type.  */
-typedef void (*func_ptr) (void);
-
-#ifdef CRT_INIT
-
-/* NOTE:  In order to be able to support SVR4 shared libraries, we arrange
-   to have one set of symbols { __CTOR_LIST__, __DTOR_LIST__, __CTOR_END__,
-   __DTOR_END__ } per root executable and also one set of these symbols
-   per shared library.  So in any given whole process image, we may have
-   multiple definitions of each of these symbols.  In order to prevent
-   these definitions from conflicting with one another, and in order to
-   ensure that the proper lists are used for the initialization/finalization
-   of each individual shared library (respectively), we give these symbols
-   only internal (i.e. `static') linkage, and we also make it a point to
-   refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__
-   symbol in crtinit.o, where they are defined.  */
-
-static func_ptr __CTOR_LIST__[1]
-  __attribute__ ((section (".ctors")))
-     = { (func_ptr) (-1) };
-
-static func_ptr __DTOR_LIST__[1]
-  __attribute__ ((section (".dtors")))
-     = { (func_ptr) (-1) };
-
-/* Run all the global destructors on exit from the program.  */
- 
-/* Some systems place the number of pointers in the first word of the
-   table.  On SVR4 however, that word is -1.  In all cases, the table is
-   null-terminated.  On SVR4, we start from the beginning of the list and
-   invoke each per-compilation-unit destructor routine in order
-   until we find that null.
-
-   Note that this function MUST be static.  There will be one of these
-   functions in each root executable and one in each shared library, but
-   although they all have the same code, each one is unique in that it
-   refers to one particular associated `__DTOR_LIST__' which belongs to the
-   same particular root executable or shared library file.  */
-
-static void __do_global_dtors ()
-asm ("__do_global_dtors") __attribute__ ((section (".text")));
-
-static void
-__do_global_dtors ()
-{
-  func_ptr *p;
-
-  for (p = __DTOR_LIST__ + 1; *p; p++)
-    (*p) ();
-}
-
-/* .init section start.
-   This must appear at the start of the .init section.  */
-
-asm ("
-	.section .init,\"ax\",@progbits
-	.balign 4
-	.global __init
-__init:
-	push fp
-	push lr
-	mv fp,sp
-	ld24 r0,#__fini
-	bl atexit
-	.fillinsn
-");
-
-/* .fini section start.
-   This must appear at the start of the .init section.  */
-
-asm ("
-	.section .fini,\"ax\",@progbits
-	.balign 4
-	.global __fini
-__fini:
-	push fp
-	push lr
-	mv fp,sp
-	bl __do_global_dtors
-	.fillinsn
-");
-
-#endif /* CRT_INIT */
-
-#ifdef CRT_FINI
-
-/* Put a word containing zero at the end of each of our two lists of function
-   addresses.  Note that the words defined here go into the .ctors and .dtors
-   sections of the crtend.o file, and since that file is always linked in
-   last, these words naturally end up at the very ends of the two lists
-   contained in these two sections.  */
-
-static func_ptr __CTOR_END__[1]
-  __attribute__ ((section (".ctors")))
-     = { (func_ptr) 0 };
-
-static func_ptr __DTOR_END__[1]
-  __attribute__ ((section (".dtors")))
-     = { (func_ptr) 0 };
-
-/* Run all global constructors for the program.
-   Note that they are run in reverse order.  */
-
-static void __do_global_ctors ()
-asm ("__do_global_ctors") __attribute__ ((section (".text")));
-
-static void
-__do_global_ctors ()
-{
-  func_ptr *p;
-
-  for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--)
-    (*p) ();
-}
-
-/* .init section end.
-   This must live at the end of the .init section.  */
-
-asm ("
-	.section .init,\"ax\",@progbits
-	bl __do_global_ctors
-	mv sp,fp
-	pop lr
-	pop fp
-	jmp lr
-	.fillinsn
-");
-
-/* .fini section end.
-   This must live at the end of the .fini section.  */
-
-asm ("
-	.section .fini,\"ax\",@progbits
-	mv sp,fp
-	pop lr
-	pop fp
-	jmp lr
-	.fillinsn
-");
-
-#endif /* CRT_FINI */
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
deleted file mode 100755
index c7717b1..0000000
--- a/gcc/config/m32r/m32r.c
+++ /dev/null
@@ -1,3323 +0,0 @@
-/* CYGNUS LOCAL -- meissner/m32r work */
-/* Subroutines used for code generation on the Mitsubishi M32R cpu.
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include "system.h"
-#include "tree.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "expr.h"
-#include "recog.h"
-
-/* Save the operands last given to a compare for use when we
-   generate a scc or bcc insn.  */
-rtx m32r_compare_op0, m32r_compare_op1;
-
-/* Array of valid operand punctuation characters.  */
-char m32r_punct_chars[256];
-
-/* Selected code model.  */
-char *m32r_model_string = M32R_MODEL_DEFAULT;
-enum m32r_model m32r_model;
-
-/* Selected SDA support.  */
-char *m32r_sdata_string = M32R_SDATA_DEFAULT;
-enum m32r_sdata m32r_sdata;
-
-/* Scheduler support */
-int m32r_sched_odd_word_p;
-
-/* Values of the -mcond-exec=n string.  */
-int    m32rx_cond_exec = 4;
-char * m32rx_cond_exec_string = NULL;
-
-/* Forward declaration.  */
-static void init_reg_tables	PROTO((void));
-static void emit_S_clause	PROTO((rtx, rtx, char *));
-static int generate_comparison	PROTO((rtx, char *));
-
-static int internal_reg_or_eq_int16_operand	PROTO ((rtx, enum machine_mode));
-static int internal_reg_or_cmp_int16_operand	PROTO ((rtx, enum machine_mode));
-static int internal_reg_or_uint16_operand	PROTO ((rtx, enum machine_mode));
-static int internal_reg_or_zero_operand		PROTO ((rtx, enum machine_mode));
-
-/* Called by OVERRIDE_OPTIONS to initialize various things.  */
-
-void
-m32r_init ()
-{
-  init_reg_tables ();
-
-  /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P.  */
-  memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
-  m32r_punct_chars['#'] = 1;
-  m32r_punct_chars['@'] = 1; /* ??? no longer used */
-
-  /* Provide default value if not specified.  */
-  if (!g_switch_set)
-    g_switch_value = SDATA_DEFAULT_SIZE;
-
-  if (strcmp (m32r_model_string, "small") == 0)
-    m32r_model = M32R_MODEL_SMALL;
-  else if (strcmp (m32r_model_string, "medium") == 0)
-    m32r_model = M32R_MODEL_MEDIUM;
-  else if (strcmp (m32r_model_string, "large") == 0)
-    m32r_model = M32R_MODEL_LARGE;
-  else
-    error ("bad value (%s) for -mmodel switch", m32r_model_string);
-
-  if (strcmp (m32r_sdata_string, "none") == 0)
-    m32r_sdata = M32R_SDATA_NONE;
-  else if (strcmp (m32r_sdata_string, "sdata") == 0)
-    m32r_sdata = M32R_SDATA_SDATA;
-  else if (strcmp (m32r_sdata_string, "use") == 0)
-    m32r_sdata = M32R_SDATA_USE;
-  else
-    error ("bad value (%s) for -msdata switch", m32r_sdata_string);
-
-  /* Set up max # instructions to use with conditional execution */
-  if (m32rx_cond_exec_string)
-    m32rx_cond_exec = atoi (m32rx_cond_exec_string);
-}
-
-/* Vectors to keep interesting information about registers where it can easily
-   be got.  We use to use the actual mode value as the bit number, but there
-   is (or may be) more than 32 modes now.  Instead we use two tables: one
-   indexed by hard register number, and one indexed by mode.  */
-
-/* The purpose of m32r_mode_class is to shrink the range of modes so that
-   they all fit (as bit numbers) in a 32 bit word (again).  Each real mode is
-   mapped into one m32r_mode_class mode.  */
-
-enum m32r_mode_class
-{
-  C_MODE,
-  S_MODE, D_MODE, T_MODE, O_MODE,
-  SF_MODE, DF_MODE, TF_MODE, OF_MODE
-  , A_MODE
-};
-
-/* Modes for condition codes.  */
-#define C_MODES (1 << (int) C_MODE)
-
-/* Modes for single-word and smaller quantities.  */
-#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
-
-/* Modes for double-word and smaller quantities.  */
-#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
-
-/* Modes for quad-word and smaller quantities.  */
-#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
-
-/* Modes for accumulators.  */
-#define A_MODES (1 << (int) A_MODE)
-
-/* Value is 1 if register/mode pair is acceptable on arc.  */
-
-unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
-{
-  T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
-  T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
-  S_MODES, C_MODES
-  , A_MODES, A_MODES
-};
-
-unsigned int m32r_mode_class [NUM_MACHINE_MODES];
-
-enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
-
-static void
-init_reg_tables ()
-{
-  int i;
-
-  for (i = 0; i < NUM_MACHINE_MODES; i++)
-    {
-      switch (GET_MODE_CLASS (i))
-	{
-	case MODE_INT:
-	case MODE_PARTIAL_INT:
-	case MODE_COMPLEX_INT:
-	  if (GET_MODE_SIZE (i) <= 4)
-	    m32r_mode_class[i] = 1 << (int) S_MODE;
-	  else if (GET_MODE_SIZE (i) == 8)
-	    m32r_mode_class[i] = 1 << (int) D_MODE;
-	  else if (GET_MODE_SIZE (i) == 16)
-	    m32r_mode_class[i] = 1 << (int) T_MODE;
-	  else if (GET_MODE_SIZE (i) == 32)
-	    m32r_mode_class[i] = 1 << (int) O_MODE;
-	  else 
-	    m32r_mode_class[i] = 0;
-	  break;
-	case MODE_FLOAT:
-	case MODE_COMPLEX_FLOAT:
-	  if (GET_MODE_SIZE (i) <= 4)
-	    m32r_mode_class[i] = 1 << (int) SF_MODE;
-	  else if (GET_MODE_SIZE (i) == 8)
-	    m32r_mode_class[i] = 1 << (int) DF_MODE;
-	  else if (GET_MODE_SIZE (i) == 16)
-	    m32r_mode_class[i] = 1 << (int) TF_MODE;
-	  else if (GET_MODE_SIZE (i) == 32)
-	    m32r_mode_class[i] = 1 << (int) OF_MODE;
-	  else 
-	    m32r_mode_class[i] = 0;
-	  break;
-	case MODE_CC:
-	default:
-	  /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
-	     we must explicitly check for them here.  */
-	  if (i == (int) CCmode)
-	    m32r_mode_class[i] = 1 << (int) C_MODE;
-	  else
-	    m32r_mode_class[i] = 0;
-	  break;
-	}
-    }
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      if (GPR_P (i))
-	m32r_regno_reg_class[i] = GENERAL_REGS;
-      else if (i == ARG_POINTER_REGNUM)
-	m32r_regno_reg_class[i] = GENERAL_REGS;
-      else
-	m32r_regno_reg_class[i] = NO_REGS;
-    }
-}
-
-static tree interrupt_ident;
-static tree model_ident;
-static tree small_ident;
-static tree medium_ident;
-static tree large_ident;
-
-static void
-init_idents ()
-{
-  if (interrupt_ident == 0)
-    {
-      interrupt_ident = get_identifier ("interrupt");
-      model_ident = get_identifier ("model");
-      small_ident = get_identifier ("small");
-      medium_ident = get_identifier ("medium");
-      large_ident = get_identifier ("large");
-    }
-}
-
-/* M32R specific attribute support.
-
-   interrupt - for interrupt functions
-
-   model - select code model used to access object
-
-	small: addresses use 24 bits, use bl to make calls
-	medium: addresses use 32 bits, use bl to make calls
-	large: addresses use 32 bits, use seth/add3/jl to make calls
-
-	Grep for MODEL in m32r.h for more info.
-*/
-
-/* Return nonzero if IDENTIFIER is a valid decl attribute.  */
-
-int
-m32r_valid_machine_decl_attribute (type, attributes, identifier, args)
-     tree type;
-     tree attributes;
-     tree identifier;
-     tree args;
-    {
-  init_idents ();
-
-  if (identifier == interrupt_ident
-      && list_length (args) == 0)
-    return 1;
-
-  if (identifier == model_ident
-      && list_length (args) == 1
-      && (TREE_VALUE (args) == small_ident
-	  || TREE_VALUE (args) == medium_ident
-	  || TREE_VALUE (args) == large_ident))
-    return 1;
-
-  return 0;
-}
-
-/* Return zero if TYPE1 and TYPE are incompatible, one if they are compatible,
-   and two if they are nearly compatible (which causes a warning to be
-   generated).  */
-
-int
-m32r_comp_type_attributes (type1, type2)
-     tree type1, type2;
-{
-  return 1;
-}
-
-/* Set the default attributes for TYPE.  */
-
-void
-m32r_set_default_type_attributes (type)
-     tree type;
-{
-}
-
-/* A C statement or statements to switch to the appropriate
-   section for output of DECL.  DECL is either a `VAR_DECL' node
-   or a constant of some sort.  RELOC indicates whether forming
-   the initial value of DECL requires link-time relocations.  */
-
-void
-m32r_select_section (decl, reloc)
-     tree decl;
-     int reloc;
-{
-  if (TREE_CODE (decl) == STRING_CST)
-    {
-      if (! flag_writable_strings)
-	const_section ();
-      else
-	data_section ();
-    }
-  else if (TREE_CODE (decl) == VAR_DECL)
-    {
-      if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl), 0), 0)))
-	sdata_section ();
-      else if ((flag_pic && reloc)
-	       || !TREE_READONLY (decl)
-	       || TREE_SIDE_EFFECTS (decl)
-	       || !DECL_INITIAL (decl)
-	       || (DECL_INITIAL (decl) != error_mark_node
-		   && !TREE_CONSTANT (DECL_INITIAL (decl))))
-	data_section ();
-      else
-	const_section ();
-    }
-  else
-    const_section ();
-}
-
-/* Encode section information of DECL, which is either a VAR_DECL,
-   FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
-
-   For the M32R we want to record:
-
-   - whether the object lives in .sdata/.sbss.
-     objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
-
-   - what code model should be used to access the object
-     small: recorded with no flag - for space efficiency since they'll
-            be the most common
-     medium: prefixed with MEDIUM_FLAG_CHAR
-     large: prefixed with LARGE_FLAG_CHAR
-*/
-
-void
-m32r_encode_section_info (decl)
-     tree decl;
-{
-  char prefix = 0;
-  tree model = 0;
-
-  switch (TREE_CODE (decl))
-    {
-    case VAR_DECL :
-    case FUNCTION_DECL :
-      model = lookup_attribute ("model", DECL_MACHINE_ATTRIBUTES (decl));
-      break;
-    case STRING_CST :
-    case CONSTRUCTOR :
-      /* ??? document all others that can appear here */
-    default :
-      return;
-    }
-
-  /* Only mark the object as being small data area addressable if
-     it hasn't been explicitly marked with a code model.
-
-     The user can explicitly put an object in the small data area with the
-     section attribute.  If the object is in sdata/sbss and marked with a
-     code model do both [put the object in .sdata and mark it as being
-     addressed with a specific code model - don't mark it as being addressed
-     with an SDA reloc though].  This is ok and might be useful at times.  If
-     the object doesn't fit the linker will give an error.  */
-
-  if (! model)
-    {
-      if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd'
-	  && DECL_SECTION_NAME (decl) != NULL_TREE)
-	{
-	  char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
-	  if (! strcmp (name, ".sdata") || ! strcmp (name, ".sbss"))
-	    {
-#if 0 /* ??? There's no reason to disallow this, is there?  */
-	      if (TREE_READONLY (decl))
-		error_with_decl (decl, "const objects cannot go in .sdata/.sbss");
-#endif
-	      prefix = SDATA_FLAG_CHAR;
-	    }
-	}
-      else
-	{
-	  if (TREE_CODE (decl) == VAR_DECL
-	      && ! TREE_READONLY (decl)
-	      && ! TARGET_SDATA_NONE)
-	    {
-	      int size = int_size_in_bytes (TREE_TYPE (decl));
-
-	      if (size > 0 && size <= g_switch_value)
-		prefix = SDATA_FLAG_CHAR;
-	    }
-	}
-    }
-
-  /* If data area not decided yet, check for a code model.  */
-  if (prefix == 0)
-    {
-      if (model)
-	{
-	  init_idents ();
-	  
-	  if (TREE_VALUE (TREE_VALUE (model)) == small_ident)
-	    ; /* don't mark the symbol specially */
-	  else if (TREE_VALUE (TREE_VALUE (model)) == medium_ident)
-	    prefix = MEDIUM_FLAG_CHAR;
-	  else if (TREE_VALUE (TREE_VALUE (model)) == large_ident)
-	    prefix = LARGE_FLAG_CHAR;
-	  else
-	    abort (); /* shouldn't happen */
-	}
-      else
-	{
-	  if (TARGET_MODEL_SMALL)
-	    ; /* don't mark the symbol specially */
-	  else if (TARGET_MODEL_MEDIUM)
-	    prefix = MEDIUM_FLAG_CHAR;
-	  else if (TARGET_MODEL_LARGE)
-	    prefix = LARGE_FLAG_CHAR;
-	  else
-	    abort (); /* shouldn't happen */
-	}
-    }
-
-  if (prefix != 0)
-    {
-      rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
-                 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
-      char *str = XSTR (XEXP (rtl, 0), 0);
-      int len = strlen (str);
-      char *newstr = savealloc (len + 2);
-      strcpy (newstr + 1, str);
-      *newstr = prefix;
-      XSTR (XEXP (rtl, 0), 0) = newstr;
-    }
-}
-
-/* Do anything needed before RTL is emitted for each function.  */
-
-void
-m32r_init_expanders ()
-{
-  /* ??? At one point there was code here.  The function is left in
-     to make it easy to experiment.  */
-}
-
-/* Acceptable arguments to the call insn.  */
-
-int
-call_address_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  return symbolic_operand (op, int_mode);
-
-/* The following xxx_operand functions all take an integer for the machine_mode
-   argument.  This is to allow them to be prototyped in m32r.h which is
-   included before rtl.h is included.  Not every function includes rtl.h, so we
-   can't assume it will be included.  */
-
-/* Constants and values in registers are not OK, because
-   the m32r BL instruction can only support PC relative branching.  */ 
-}
-
-int
-call_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-
-  if (GET_CODE (op) != MEM)
-    return 0;
-  op = XEXP (op, 0);
-  return call_address_operand (op, mode);
-}
-
-/* Returns 1 if OP is a symbol reference.  */
-
-int
-symbolic_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case CONST :
-      return 1;
-
-    default:
-      return 0;
-    }
-}
-
-/* Return 1 if OP is a reference to an object in .sdata/.sbss.  */
-
-int
-small_data_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  if (! TARGET_SDATA_USE)
-    return 0;
-
-  if (GET_CODE (op) == SYMBOL_REF)
-    return SDATA_NAME_P (XSTR (op, 0));
-
-  if (GET_CODE (op) == CONST
-      && GET_CODE (XEXP (op, 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
-      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
-      && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
-    return SDATA_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0));
-
-  return 0;
-}
-
-/* Return 1 if OP is a symbol that can use 24 bit addressing.  */
-
-int
-addr24_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  if (GET_CODE (op) == LABEL_REF)
-    return TARGET_ADDR24;
-
-  if (GET_CODE (op) == SYMBOL_REF)
-    return (SMALL_NAME_P (XSTR (op, 0))
-	    || (TARGET_ADDR24
-		&& (CONSTANT_POOL_ADDRESS_P (op)
-		    || LIT_NAME_P (XSTR (op, 0)))));
-
-  if (GET_CODE (op) == CONST
-      && GET_CODE (XEXP (op, 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
-      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
-      && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
-    {
-      rtx sym = XEXP (XEXP (op, 0), 0);
-      return (SMALL_NAME_P (XSTR (sym, 0))
-	      || (TARGET_ADDR24
-		  && (CONSTANT_POOL_ADDRESS_P (op)
-		      || LIT_NAME_P (XSTR (op, 0)))));
-    }
-
-  return 0;
-}
-
-/* Return 1 if OP is a symbol that needs 32 bit addressing.  */
-
-int
-addr32_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  if (GET_CODE (op) == LABEL_REF)
-    return TARGET_ADDR32;
-
-  if (GET_CODE (op) == SYMBOL_REF)
-    return (! addr24_operand (op, int_mode)
-	    && ! small_data_operand (op, int_mode));
-
-  if (GET_CODE (op) == CONST
-      && GET_CODE (XEXP (op, 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
-      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
-    {
-      return (! addr24_operand (op, int_mode)
-	      && ! small_data_operand (op, int_mode));
-    }
-
-  return 0;
-}
-
-/* Return 1 if OP is a function that can be called with the `bl' insn.  */
-
-int
-call26_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  if (GET_CODE (op) == SYMBOL_REF)
-    return ! LARGE_NAME_P (XSTR (op, 0));
-
-  return TARGET_CALL26;
-}
-
-/* Returns 1 if OP is an acceptable operand for seth/add3.  */
-
-int
-seth_add3_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  if (GET_CODE (op) == SYMBOL_REF
-      || GET_CODE (op) == LABEL_REF)
-    return 1;
-
-  if (GET_CODE (op) == CONST
-      && GET_CODE (XEXP (op, 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
-      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
-      && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
-    return 1;
-
-  return 0;
-}
-
-/* Return true if OP is a signed 8 bit immediate value.  */
-
-int
-int8_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  return INT8_P (INTVAL (op));
-}
-
-/* Return true if OP is a signed 16 bit immediate value
-   useful in comparisons.  */
-
-int
-cmp_int16_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  return CMP_INT16_P (INTVAL (op));
-}
-
-/* Return true if OP is an unsigned 16 bit immediate value.  */
-int
-uint16_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  return UINT16_P (INTVAL (op));
-}
-
-/* Return true if OP is a register or signed 16 bit value.  */
-int
-reg_or_int16_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-
-  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
-    return register_operand (op, mode);
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  return INT16_P (INTVAL (op));
-}
-
-/* Return true if OP is a register or an unsigned 16 bit value.  */
-int
-reg_or_uint16_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-
-  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
-    return register_operand (op, mode);
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  return UINT16_P (INTVAL (op));
-}
-
-/* Return true if OP is a register or an integer value that can be
-   used is SEQ/SNE.  We can use either XOR of the value or ADD of
-   the negative of the value for the constant.  Don't allow 0,
-   because that is special cased.  */
-int
-reg_or_eq_int16_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  HOST_WIDE_INT value;
-  enum machine_mode mode = (enum machine_mode)int_mode;
-
-  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
-    return register_operand (op, mode);
-
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-
-  value = INTVAL (op);
-  return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
-}
-
-/* Same as eqne_int16_operand, except the mode argument is an enum.  */
-int
-internal_reg_or_eq_int16_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  HOST_WIDE_INT value;
-
-  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
-    return register_operand (op, mode);
-
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-
-  value = INTVAL (op);
-  return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
-}
-
-/* Same as reg_or_int16_operand, except the mode argument is an enum.  */
-static int
-internal_reg_or_uint16_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
-    return register_operand (op, mode);
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  return UINT16_P (INTVAL (op));
-}
-
-/* Return true if OP is a register or signed 16 bit value for compares.  */
-int
-reg_or_cmp_int16_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-
-  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
-    return register_operand (op, mode);
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  return CMP_INT16_P (INTVAL (op));
-}
-
-/* Same as reg_or_cmp_int16_operand, but uses machine_mode as an
-   operand.  */
-static int
-internal_reg_or_cmp_int16_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
-    return register_operand (op, mode);
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  return CMP_INT16_P (INTVAL (op));
-}
-
-/* Return true if OP is a register or the constant 0.  */
-int
-reg_or_zero_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-
-  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
-    return register_operand (op, mode);
-  
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  
-  return INTVAL (op) == 0;
-}
-
-/* Like reg_or_zero_operand, except mode argument is an enum.  */
-static int
-internal_reg_or_zero_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
-    return register_operand (op, mode);
-  
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  
-  return INTVAL (op) == 0;
-}
-
-/* Return true if OP is a const_int requiring two instructions to load.  */
-
-int
-two_insn_const_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  if (INT16_P (INTVAL (op))
-      || UINT24_P (INTVAL (op))
-      || UPPER16_P (INTVAL (op)))
-    return 0;
-  return 1;
-}
-
-/* Return true if OP is an acceptable argument for a single word
-   move source.  */
-
-int
-move_src_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF :
-    case CONST :
-      return addr24_operand (op, int_mode);
-    case CONST_INT :
-      /* ??? We allow more cse opportunities if we only allow constants
-	 loadable with one insn, and split the rest into two.  The instances
-	 where this would help should be rare and the current way is
-	 simpler.  */
-      return INT32_P (INTVAL (op));
-    case LABEL_REF :
-      return TARGET_ADDR24;
-    case CONST_DOUBLE :
-      if (mode == SFmode)
-	return 1;
-      else if (mode == SImode)
-	{
-	  /* Large unsigned constants are represented as const_double's.  */
-	  unsigned HOST_WIDE_INT low, high;
-
-	  low = CONST_DOUBLE_LOW (op);
-	  high = CONST_DOUBLE_HIGH (op);
-	  return high == 0 && low <= 0xffffffff;
-	}
-      else
-	return 0;
-    case REG :
-      return register_operand (op, mode);
-    case SUBREG :
-      /* (subreg (mem ...) ...) can occur here if the inner part was once a
-	 pseudo-reg and is now a stack slot.  */
-      if (GET_CODE (SUBREG_REG (op)) == MEM)
-	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
-      else
-	return register_operand (op, mode);
-    case MEM :
-      if (GET_CODE (XEXP (op, 0)) == PRE_INC
-	  || GET_CODE (XEXP (op, 0)) == PRE_DEC)
-	return 0;		/* loads can't do pre-{inc,dec} */
-      return address_operand (XEXP (op, 0), mode);
-    default :
-      return 0;
-    }
-}
-
-/* Return true if OP is an acceptable argument for a double word
-   move source.  */
-
-int
-move_double_src_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-  switch (GET_CODE (op))
-    {
-    case CONST_INT :
-    case CONST_DOUBLE :
-      return 1;
-    case REG :
-      return register_operand (op, mode);
-    case SUBREG :
-      /* (subreg (mem ...) ...) can occur here if the inner part was once a
-	 pseudo-reg and is now a stack slot.  */
-      if (GET_CODE (SUBREG_REG (op)) == MEM)
-	return move_double_src_operand (SUBREG_REG (op), int_mode);
-      else
-	return register_operand (op, mode);
-    case MEM :
-      /* Disallow auto inc/dec for now.  */
-      if (GET_CODE (XEXP (op, 0)) == PRE_DEC
-	  || GET_CODE (XEXP (op, 0)) == PRE_INC)
-	return 0;
-      return address_operand (XEXP (op, 0), mode);
-    default :
-      return 0;
-    }
-}
-
-/* Return true if OP is an acceptable argument for a move destination.  */
-
-int
-move_dest_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-  switch (GET_CODE (op))
-    {
-    case REG :
-      return register_operand (op, mode);
-    case SUBREG :
-      /* (subreg (mem ...) ...) can occur here if the inner part was once a
-	 pseudo-reg and is now a stack slot.  */
-      if (GET_CODE (SUBREG_REG (op)) == MEM)
-	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
-      else
-	return register_operand (op, mode);
-    case MEM :
-      if (GET_CODE (XEXP (op, 0)) == POST_INC)
-	return 0;		/* stores can't do post inc */
-      return address_operand (XEXP (op, 0), mode);
-    default :
-      return 0;
-    }
-}
-
-/* Return 1 if OP is a DImode const we want to handle inline.
-   This must match the code in the movdi pattern.
-   It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER.  */
-
-int
-easy_di_const (op)
-     rtx op;
-{
-  rtx high_rtx, low_rtx;
-  HOST_WIDE_INT high, low;
-
-  split_double (op, &high_rtx, &low_rtx);
-  high = INTVAL (high_rtx);
-  low = INTVAL (low_rtx);
-  /* Pick constants loadable with 2 16 bit `ldi' insns.  */
-  if (high >= -128 && high <= 127
-      && low >= -128 && low <= 127)
-    return 1;
-  return 0;
-}
-
-/* Return 1 if OP is a DFmode const we want to handle inline.
-   This must match the code in the movdf pattern.
-   It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER.  */
-
-int
-easy_df_const (op)
-     rtx op;
-{
-  REAL_VALUE_TYPE r;
-  long l[2];
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-  REAL_VALUE_TO_TARGET_DOUBLE (r, l);
-  if (l[0] == 0 && l[1] == 0)
-    return 1;
-  if ((l[0] & 0xffff) == 0 && l[1] == 0)
-    return 1;
-  return 0;
-}
-
-/* Return 1 if OP is an EQ or NE comparison operator.  */
-
-int
-eqne_comparison_operator (op, int_mode)
-    rtx op;
-    int int_mode;
-{
-  enum rtx_code code = GET_CODE (op);
-
-  if (GET_RTX_CLASS (code) != '<')
-    return 0;
-  return (code == EQ || code == NE);
-}
-
-/* Return 1 if OP is a signed comparison operator.  */
-
-int
-signed_comparison_operator (op, int_mode)
-    rtx op;
-    int int_mode;
-{
-  enum rtx_code code = GET_CODE (op);
-
-  if (GET_RTX_CLASS (code) != '<')
-    return 0;
-  return (code == EQ || code == NE
-	  || code == LT || code == LE || code == GT || code == GE);
-}
-
-/* Return 1 if OP is (mem (reg ...)).
-   This is used in insn length calcs.  */
-
-int
-memreg_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
-}
-
-/* Return true if OP is an acceptable input argument for a zero/sign extend
-   operation.  */
-
-int
-extend_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-  rtx addr;
-
-  switch (GET_CODE (op))
-    {
-    case REG :
-    case SUBREG :
-      return register_operand (op, mode);
-
-    case MEM :
-      addr = XEXP (op, 0);
-      if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
-	return 0;		/* loads can't do pre inc/pre dec */
-
-      return address_operand (addr, mode);
-
-    default :
-      return 0;
-    }
-}
-
-/* Return non-zero if the operand is an insn that is a small insn.
-   Allow const_int 0 as well, which is a placeholder for NOP slots.  */
-
-int
-small_insn_p (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
-    return 1;
-
-  if (GET_RTX_CLASS (GET_CODE (op)) != 'i')
-    return 0;
-
-  return get_attr_length (op) == 2;
-}
-
-/* Return non-zero if the operand is an insn that is a large insn.  */
-
-int
-large_insn_p (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  if (GET_RTX_CLASS (GET_CODE (op)) != 'i')
-    return 0;
-
-  return get_attr_length (op) != 2;
-}
-
-
-/* Comparisons.  */
-
-/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
-   return the mode to be used for the comparison.  */
-
-int
-m32r_select_cc_mode (op, x, y)
-     int op;
-     rtx x, y;
-{
-  return (int)CCmode;
-}
-
-/* X and Y are two things to compare using CODE.  Emit the compare insn and
-   return the rtx for compare [arg0 of the if_then_else].
-   If need_compare is true then the comparison insn must be generated, rather
-   than being susummed into the following branch instruction. */
-
-rtx
-gen_compare (int_code, label, x, y)
-     int int_code;
-     rtx label;
-     rtx x;
-     rtx y;
-{
-  enum rtx_code     code = (enum rtx_code)int_code;
-  enum rtx_code     branch_code;
-  enum machine_mode mode      = SELECT_CC_MODE (code, x, y);
-  rtx               cc_reg    = gen_rtx (REG, mode, CARRY_REGNUM);
-  int               must_swap = FALSE;
-  int		    int_p     = (GET_CODE (y) == CONST_INT);
-  HOST_WIDE_INT	    value     = (int_p) ? INTVAL (y) : 0;
-  int		    signed_p  = 0;
-  rtx		    arg1;
-  rtx		    arg2;
-  rtx		    ret;
-  rtx		    (*gen_func) PROTO ((rtx, rtx))
-			      = (rtx (*) PROTO ((rtx, rtx))) abort;
-  int		    (*constrain_func) PROTO ((rtx, enum machine_mode))
-			      = (int (*) PROTO ((rtx, enum machine_mode))) abort;
-
-  start_sequence ();
-  if (GET_CODE (x) != REG && GET_CODE (x) != SUBREG)
-    x = force_reg (GET_MODE (x), x);
-
-  if (GET_CODE (y) != REG && GET_CODE (y) != SUBREG && !int_p)
-    y = force_reg (GET_MODE (x), y);
-
-  /* If we have a LE, GT, etc. of a constant, see if we can tranform it to the
-     appropriate LT, GE, etc. to use the cmpi or cmpui instruction.  */
-  if (int_p)
-    {
-      if ((code == LE || code == GT) && (value >= -32768 && value < 32767))
-	{
-	  ++value;
-	  y = GEN_INT (value);
-	  code = (code == LE) ? LT : GE;
-	}
-
-      else if ((code == LEU || code == GTU) && (value >= 0 && value < 32767))
-	{
-	  ++value;
-	  y = GEN_INT (value);
-	  code = (code == LEU) ? LTU : GEU;
-	}
-    }
-
-  switch (code)
-    {
-    default:
-      abort ();
-
-    case EQ:
-      gen_func = gen_cmp_eqsi_insn;
-      constrain_func = internal_reg_or_uint16_operand;
-      branch_code = NE;
-      signed_p = TRUE;
-      if (TARGET_M32RX)
-	{
-	  gen_func = gen_cmp_eqsi_zero_insn;
-	  constrain_func = internal_reg_or_zero_operand;
-	}
-      break;
-
-    case NE:
-      gen_func = gen_cmp_eqsi_insn;
-      constrain_func = internal_reg_or_uint16_operand;
-      branch_code = EQ;
-      signed_p = TRUE;
-      if (TARGET_M32RX)
-	{
-	  gen_func = gen_cmp_eqsi_zero_insn;
-	  constrain_func = internal_reg_or_zero_operand;
-	}
-      break;
-
-    case LT:
-      gen_func = gen_cmp_ltsi_insn;
-      constrain_func = internal_reg_or_cmp_int16_operand;
-      branch_code = NE;
-      signed_p = TRUE;
-      break;
-
-    case LE:
-      gen_func = gen_cmp_ltsi_insn;
-      constrain_func = internal_reg_or_cmp_int16_operand;
-      branch_code = EQ;
-      signed_p = TRUE;
-      must_swap = TRUE;
-      break;
-
-    case GT:
-      gen_func = gen_cmp_ltsi_insn;
-      constrain_func = internal_reg_or_cmp_int16_operand;
-      branch_code = NE;
-      signed_p = TRUE;
-      must_swap = TRUE;
-      break;
-
-    case GE:
-      gen_func = gen_cmp_ltsi_insn;
-      constrain_func = internal_reg_or_cmp_int16_operand;
-      branch_code = EQ;
-      signed_p = TRUE;
-      break;
-
-    case LTU:
-      gen_func = gen_cmp_ltusi_insn;
-      constrain_func = internal_reg_or_cmp_int16_operand;
-      branch_code = NE;
-      signed_p = FALSE;
-      break;
-
-    case LEU:
-      gen_func = gen_cmp_ltusi_insn;
-      constrain_func = internal_reg_or_cmp_int16_operand;
-      branch_code = EQ;
-      signed_p = FALSE;
-      must_swap = TRUE;
-      break;
-
-    case GTU:
-      gen_func = gen_cmp_ltusi_insn;
-      constrain_func = internal_reg_or_cmp_int16_operand;
-      branch_code = NE;
-      signed_p = FALSE;
-      must_swap = TRUE;
-      break;
-
-    case GEU:
-      gen_func = gen_cmp_ltusi_insn;
-      constrain_func = internal_reg_or_cmp_int16_operand;
-      branch_code = EQ;
-      signed_p = FALSE;
-      break;
-    }
-
-  /* Is this a branch comparison against 0? */
-  if (int_p && value == 0 && signed_p)
-    {
-      emit_jump_insn (gen_rtx_SET (VOIDmode,
-				   pc_rtx,
-				   gen_rtx_IF_THEN_ELSE (VOIDmode,
-							 gen_rtx (code,
-								  VOIDmode,
-								  x,
-								  CONST0_RTX (mode)),
-							 gen_rtx_LABEL_REF (VOIDmode,
-									    label),
-							 pc_rtx)));
-    }
-
-  /* Is this a branch comparison comparing two registers for == or !=? */
-  else if (code == EQ || code == NE)
-    {
-      if (int_p)
-	y = force_reg (GET_MODE (x), y);
-
-      emit_jump_insn (gen_rtx_SET (VOIDmode,
-				   pc_rtx,
-				   gen_rtx_IF_THEN_ELSE (VOIDmode,
-							 gen_rtx (code,
-								  VOIDmode,
-								  x, y),
-							 gen_rtx_LABEL_REF (VOIDmode,
-									    label),
-							 pc_rtx)));
-    }
-
-  /* If not, set c bit and then do jump */
-  else
-    {
-      if (int_p && (must_swap || ! (*constrain_func) (y, GET_MODE (y))))
-	y = force_reg (GET_MODE (x), y);
-
-      if (must_swap)
-	{
-	  arg1 = y;
-	  arg2 = x;
-	}
-      else
-	{
-	  arg1 = x;
-	  arg2 = y;
-	}
-
-      emit_insn ((*gen_func) (arg1, arg2));
-      emit_jump_insn (gen_rtx_SET (VOIDmode,
-				   pc_rtx,
-				   gen_rtx_IF_THEN_ELSE (VOIDmode,
-							 gen_rtx (branch_code,
-								  VOIDmode,
-								  cc_reg,
-								  CONST0_RTX (mode)),
-							 gen_rtx_LABEL_REF (VOIDmode,
-									    label),
-							 pc_rtx)));
-    }
-
-  ret = gen_sequence ();
-  end_sequence ();
-  return ret;
-}
-
-/* Split a 2 word move (DI or DF) into component parts.  */
-
-rtx
-gen_split_move_double (operands)
-     rtx operands[];
-{
-  enum machine_mode mode = GET_MODE (operands[0]);
-  rtx dest = operands[0];
-  rtx src  = operands[1];
-  rtx val;
-
-  /* We might have (SUBREG (MEM)) here, so just get rid of the
-     subregs to make this code simpler.  It is safe to call
-     alter_subreg any time after reload.  */
-  if (GET_CODE (dest) == SUBREG)
-    dest = alter_subreg (dest);
-  if (GET_CODE (src) == SUBREG)
-    src = alter_subreg (src);
-
-  start_sequence ();
-  if (GET_CODE (dest) == REG)
-    {
-      int dregno = REGNO (dest);
-
-      /* reg = reg */
-      if (GET_CODE (src) == REG)
-	{
-	  int sregno = REGNO (src);
-
-	  int reverse = (dregno == sregno + 1);
-
-	  /* We normally copy the low-numbered register first.  However, if
-	     the first register operand 0 is the same as the second register of
-	     operand 1, we must copy in the opposite order.  */
-	  emit_insn (gen_rtx_SET (VOIDmode,
-				  operand_subword (dest, reverse, TRUE, mode),
-				  operand_subword (src,  reverse, TRUE, mode)));
-
-	  emit_insn (gen_rtx_SET (VOIDmode,
-				  operand_subword (dest, !reverse, TRUE, mode),
-				  operand_subword (src,  !reverse, TRUE, mode)));
-	}
-
-      /* reg = constant */
-      else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
-	{
-	  rtx words[2];
-	  split_double (src, &words[0], &words[1]);
-	  emit_insn (gen_rtx_SET (VOIDmode,
-				  operand_subword (dest, 0, TRUE, mode),
-				  words[0]));
-
-	  emit_insn (gen_rtx_SET (VOIDmode,
-				  operand_subword (dest, 1, TRUE, mode),
-				  words[1]));
-	}
-
-      /* reg = mem */
-      else if (GET_CODE (src) == MEM)
-	{
-	  /* If the high-address word is used in the address, we must load it
-	     last.  Otherwise, load it first.  */
-	  rtx addr = XEXP (src, 0);
-	  int reverse = (refers_to_regno_p (dregno, dregno+1, addr, 0) != 0);
-
-	  /* We used to optimize loads from single registers as
-
-		ld r1,r3+; ld r2,r3
-
-	     if r3 were not used subsequently.  However, the REG_NOTES aren't
-	     propigated correctly by the reload phase, and it can cause bad
-	     code to be generated.  We could still try:
-
-		ld r1,r3+; ld r2,r3; addi r3,-4
-
-	     which saves 2 bytes and doesn't force longword alignment.  */
-	  emit_insn (gen_rtx_SET (VOIDmode,
-				  operand_subword (dest, reverse, TRUE, mode),
-				  change_address (src, SImode,
-						  plus_constant (addr,
-								 reverse * UNITS_PER_WORD))));
-
-	  emit_insn (gen_rtx_SET (VOIDmode,
-				  operand_subword (dest, !reverse, TRUE, mode),
-				  change_address (src, SImode,
-						  plus_constant (addr,
-								 (!reverse) * UNITS_PER_WORD))));
-	}
-
-      else
-	abort ();
-    }
-
-  /* mem = reg */
-  /* We used to optimize loads from single registers as
-
-	st r1,r3; st r2,+r3
-
-     if r3 were not used subsequently.  However, the REG_NOTES aren't
-     propigated correctly by the reload phase, and it can cause bad
-     code to be generated.  We could still try:
-
-	st r1,r3; st r2,+r3; addi r3,-4
-
-     which saves 2 bytes and doesn't force longword alignment.  */
-  else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
-    {
-      rtx addr = XEXP (dest, 0);
-
-      emit_insn (gen_rtx_SET (VOIDmode,
-			      change_address (dest, SImode, addr),
-			      operand_subword (src, 0, TRUE, mode)));
-
-      emit_insn (gen_rtx_SET (VOIDmode,
-			      change_address (dest, SImode,
-					      plus_constant (addr, UNITS_PER_WORD)),
-			      operand_subword (src, 1, TRUE, mode)));
-    }
-
-  else
-    abort ();
-
-  val = gen_sequence ();
-  end_sequence ();
-  return val;
-}
-
-
-/* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.  */
-
-int
-function_arg_partial_nregs (cum, int_mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     int int_mode;
-     tree type;
-     int named;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-  int ret;
-  int size = (((mode == BLKmode && type)
-	       ? int_size_in_bytes (type)
-	       : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-
-  if (*cum >= M32R_MAX_PARM_REGS)
-    ret = 0;
-  else if (*cum + size > M32R_MAX_PARM_REGS)
-    ret = (*cum + size) - M32R_MAX_PARM_REGS;
-  else
-    ret = 0;
-
-  return ret;
-}
-
-/* Do any needed setup for a variadic function.  For the M32R, we must
-   create a register parameter block, and then copy any anonymous arguments
-   in registers to memory.
-
-   CUM has not been updated for the last named argument which has type TYPE
-   and mode MODE, and we rely on this fact.  */
-
-void
-m32r_setup_incoming_varargs (cum, int_mode, type, pretend_size, no_rtl)
-     CUMULATIVE_ARGS *cum;
-     int int_mode;
-     tree type;
-     int *pretend_size;
-     int no_rtl;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-  int first_anon_arg;
-
-  if (no_rtl)
-    return;
-
-  /* All BLKmode values are passed by reference.  */
-  if (mode == BLKmode)
-    abort ();
-
-  /* We must treat `__builtin_va_alist' as an anonymous arg.  */
-  if (current_function_varargs)
-    first_anon_arg = *cum;
-  else
-    first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
-		      + ROUND_ADVANCE_ARG (mode, type));
-
-  if (first_anon_arg < M32R_MAX_PARM_REGS)
-    {
-      /* Note that first_reg_offset < M32R_MAX_PARM_REGS.  */
-      int first_reg_offset = first_anon_arg;
-      /* Size in words to "pretend" allocate.  */
-      int size = M32R_MAX_PARM_REGS - first_reg_offset;
-      rtx regblock;
-
-      regblock = gen_rtx (MEM, BLKmode,
-			  plus_constant (arg_pointer_rtx,
-					 FIRST_PARM_OFFSET (0)));
-      move_block_from_reg (first_reg_offset, regblock,
-			   size, size * UNITS_PER_WORD);
-
-      *pretend_size = (size * UNITS_PER_WORD);
-    }
-}
-
-/* Cost functions.  */
-
-/* Provide the costs of an addressing mode that contains ADDR.
-   If ADDR is not a valid address, its cost is irrelevant.
-
-   This function is trivial at the moment.  This code doesn't live
-   in m32r.h so it's easy to experiment.  */
-
-int
-m32r_address_cost (addr)
-     rtx addr;
-{
-  return 1;
-}
-
-
-/* A C statement (sans semicolon) to update the integer variable COST based on
-   the relationship between INSN that is dependent on DEP_INSN through the
-   dependence LINK.  The default is to make no adjustment to COST.  This can be
-   used for example to specify to the scheduler that an output- or
-   anti-dependence does not incur the same cost as a data-dependence.  */
-
-int
-m32r_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
-{
-  return cost;
-}
-
-
-/* A C statement (sans semicolon) to update the integer scheduling
-   priority `INSN_PRIORITY(INSN)'.  Reduce the priority to execute
-   the INSN earlier, increase the priority to execute INSN later.
-   Do not define this macro if you do not need to adjust the
-   scheduling priorities of insns.
-
-   On the m32r, increase the priority of long instructions so that
-   the short instructions are scheduled ahead of the long ones.  */
-
-int
-m32r_adjust_priority (insn, priority)
-     rtx insn;
-     int priority;
-{
-  if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
-    {
-      enum rtx_code code = GET_CODE (PATTERN (insn));
-      if (code != USE && code != CLOBBER && code != ADDR_VEC
-	  && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
-	priority <<= 3;
-    }
-
-  return priority;
-}
-
-
-/* Initialize for scheduling a group of instructions.  */
-
-void
-m32r_sched_init (stream, verbose)
-     FILE *stream;
-     int verbose;
-{
-  m32r_sched_odd_word_p = FALSE;
-}
-
-
-/* Reorder the schedulers priority list if needed */
-
-void
-m32r_sched_reorder (stream, verbose, ready, n_ready)
-     FILE *stream;
-     int verbose;
-     rtx *ready;
-     int n_ready;
-{
-  if (TARGET_DEBUG)
-    return;
-
-  if (verbose <= 7)
-    stream = (FILE *)0;
-
-  if (stream)
-    fprintf (stream,
-	     ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
-	     n_ready,
-	     (m32r_sched_odd_word_p) ? "odd" : "even");
-
-  if (n_ready > 1)
-    {
-      rtx *long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
-      rtx *long_tail = long_head;
-      rtx *short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
-      rtx *short_tail = short_head;
-      rtx *new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
-      rtx *new_tail = new_head + (n_ready - 1);
-      int i;
-
-      /* Loop through the instructions, classifing them as short/long.  Try
-	 to keep 2 short together and/or 1 long.  Note, the ready list is
-	 actually ordered backwards, so keep it in that manner.  */
-      for (i = n_ready-1; i >= 0; i--)
-	{
-	  rtx insn = ready[i];
-	  enum rtx_code code;
-
-	  if (GET_RTX_CLASS (GET_CODE (insn)) != 'i'
-	      || (code = GET_CODE (PATTERN (insn))) == USE
-	      || code == CLOBBER || code == ADDR_VEC)
-	    {
-	      /* Dump all current short/long insns just in case */
-	      while (long_head != long_tail)
-		*new_tail-- = *long_head++;
-
-	      while (short_head != short_tail)
-		*new_tail-- = *short_head++;
-
-	      *new_tail-- = insn;
-	      if (stream)
-		fprintf (stream,
-			 ";;\t\t::: Skipping non instruction %d\n",
-			 INSN_UID (insn));
-
-	    }
-
-	  else
-	    {
-	      if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
-		*long_tail++ = insn;
-
-	      else
-		*short_tail++ = insn;
-	    }
-	}
-
-      /* If we are on an odd word, emit a single short instruction if
-	 we can */
-      if (m32r_sched_odd_word_p && short_head != short_tail)
-	*new_tail-- = *short_head++;
-
-      /* Now dump out all of the long instructions */
-      while (long_head != long_tail)
-	*new_tail-- = *long_head++;
-
-      /* Now dump out all of the short instructions */
-      while (short_head != short_tail)
-	*new_tail-- = *short_head++;
-
-      if (new_tail+1 != new_head)
-	abort ();
-
-      bcopy ((char *) new_head, (char *) ready, sizeof (rtx) * n_ready);
-      if (stream)
-	{
-#ifdef HAIFA
-	  fprintf (stream, ";;\t\t::: New ready list:               ");
-	  debug_ready_list (ready, n_ready);
-#else
-	  int i;
-	  for (i = 0; i < n_ready; i++)
-	    {
-	      rtx insn = ready[i];
-	      enum rtx_code code;
-
-	      fprintf (stream, " %d", INSN_UID (ready[i]));
-	      if (GET_RTX_CLASS (GET_CODE (insn)) != 'i'
-		  || (code = GET_CODE (PATTERN (insn))) == USE
-		  || code == CLOBBER || code == ADDR_VEC)
-		fputs ("(?)", stream);
-
-	      else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
-		fputs ("(l)", stream);
-
-	      else
-		fputs ("(s)", stream);
-	    }
-
-	  fprintf (stream, "\n");
-#endif
-	}
-    }
-}
-
-
-/* if we have a machine that can issue a variable # of instructions
-   per cycle, indicate how many more instructions can be issued
-   after the current one.  */
-int
-m32r_sched_variable_issue (stream, verbose, insn, how_many)
-     FILE *stream;
-     int verbose;
-     rtx insn;
-     int how_many;
-{
-  int orig_odd_word_p = m32r_sched_odd_word_p;
-  int short_p = FALSE;
-
-  how_many--;
-  if (how_many > 0 && !TARGET_DEBUG)
-    {
-      if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
-	how_many++;
-
-      else if (GET_CODE (PATTERN (insn)) == USE
-	       || GET_CODE (PATTERN (insn)) == CLOBBER
-	       || GET_CODE (PATTERN (insn)) == ADDR_VEC)
-	how_many++;
-
-      else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
-	{
-	  how_many = 0;
-	  m32r_sched_odd_word_p = 0;
-	}
-
-      else
-	{
-	  m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
-	  short_p = TRUE;
-	}
-    }
-
-  if (verbose > 7 && stream)
-    fprintf (stream,
-	     ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
-	     short_p ? "short" : "long",
-	     INSN_UID (insn),
-	     orig_odd_word_p ? "odd" : "even",
-	     how_many);
-
-  return how_many;
-}
-
-
-/* Type of function DECL.
-
-   The result is cached.  To reset the cache at the end of a function,
-   call with DECL = NULL_TREE.  */
-
-enum m32r_function_type
-m32r_compute_function_type (decl)
-     tree decl;
-{
-  /* Cached value.  */
-  static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
-  /* Last function we were called for.  */
-  static tree last_fn = NULL_TREE;
-
-  /* Resetting the cached value?  */
-  if (decl == NULL_TREE)
-    {
-      fn_type = M32R_FUNCTION_UNKNOWN;
-      last_fn = NULL_TREE;
-      return fn_type;
-    }
-
-  if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
-    return fn_type;
-
-  /* Compute function type.  */
-  fn_type = (lookup_attribute ("interrupt", DECL_MACHINE_ATTRIBUTES (current_function_decl)) != NULL_TREE
-	     ? M32R_FUNCTION_INTERRUPT
-	     : M32R_FUNCTION_NORMAL);
-
-  last_fn = decl;
-  return fn_type;
-}
-/* Function prologue/epilogue handlers.  */
-
-/* M32R stack frames look like:
-
-             Before call                       After call
-        +-----------------------+       +-----------------------+
-        |                       |       |                       |
-   high |  local variables,     |       |  local variables,     |
-   mem  |  reg save area, etc.  |       |  reg save area, etc.  |
-        |                       |       |                       |
-        +-----------------------+       +-----------------------+
-        |                       |       |                       |
-        |  arguments on stack.  |       |  arguments on stack.  |
-        |                       |       |                       |
-  SP+0->+-----------------------+       +-----------------------+
-                                        |  reg parm save area,  |
-                                        |  only created for     |    
-                                        |  variable argument    |    
-                                        |  functions            |    
-					+-----------------------+
-                                        |   previous frame ptr  |
-                                        +-----------------------+    
-                                        |                       |    
-                                        |  register save area   |    
-                                        |                       |    
-					+-----------------------+
-                                        |    return address     |    
-                                        +-----------------------+    
-                                        |                       |    
-                                        |  local variables      |    
-                                        |                       |    
-                                        +-----------------------+    
-                                        |                       |    
-                                        |  alloca allocations   |    
-                                        |                       |    
-                                        +-----------------------+    
-                                        |                       |    
-   low                                  |  arguments on stack   |    
-   memory                               |                       |    
-                                  SP+0->+-----------------------+    
-
-Notes:
-1) The "reg parm save area" does not exist for non variable argument fns.
-2) The "reg parm save area" can be eliminated completely if we saved regs
-   containing anonymous args separately but that complicates things too
-   much (so it's not done).
-3) The return address is saved after the register save area so as to have as
-   many insns as possible between the restoration of `lr' and the `jmp lr'.
-*/
-
-/* Structure to be filled in by m32r_compute_frame_size with register
-   save masks, and offsets for the current function.  */
-struct m32r_frame_info
-{
-  unsigned int total_size;	/* # bytes that the entire frame takes up */
-  unsigned int extra_size;	/* # bytes of extra stuff */
-  unsigned int pretend_size;	/* # bytes we push and pretend caller did */
-  unsigned int args_size;	/* # bytes that outgoing arguments take up */
-  unsigned int reg_size;	/* # bytes needed to store regs */
-  unsigned int var_size;	/* # bytes that variables take up */
-  unsigned int gmask;		/* mask of saved gp registers */
-  unsigned int save_fp;		/* nonzero if fp must be saved */
-  unsigned int save_lr;		/* nonzero if lr (return addr) must be saved */
-  int          initialized;	/* nonzero if frame size already calculated */
-};
-
-/* Current frame information calculated by m32r_compute_frame_size.  */
-static struct m32r_frame_info current_frame_info;
-
-/* Zero structure to initialize current_frame_info.  */
-static struct m32r_frame_info zero_frame_info;
-
-#define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
-#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
-
-/* Tell prologue and epilogue if register REGNO should be saved / restored.
-   The return address and frame pointer are treated separately.
-   Don't consider them here.  */
-#define MUST_SAVE_REGISTER(regno, interrupt_p) \
-((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
- && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
-
-#define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
-#define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || profile_flag)
-
-#define SHORT_INSN_SIZE 2	/* size of small instructions */
-#define LONG_INSN_SIZE 4	/* size of long instructions */
-
-/* Return the bytes needed to compute the frame pointer from the current
-   stack pointer.
-
-   SIZE is the size needed for local variables.  */
-
-unsigned int
-m32r_compute_frame_size (size)
-     int size;			/* # of var. bytes allocated.  */
-{
-  int regno;
-  unsigned int total_size, var_size, args_size, pretend_size, extra_size;
-  unsigned int reg_size, frame_size;
-  unsigned int gmask;
-  enum m32r_function_type fn_type;
-  int interrupt_p;
-
-  var_size	= M32R_STACK_ALIGN (size);
-  args_size	= M32R_STACK_ALIGN (current_function_outgoing_args_size);
-  pretend_size	= current_function_pretend_args_size;
-  extra_size	= FIRST_PARM_OFFSET (0);
-  total_size	= extra_size + pretend_size + args_size + var_size;
-  reg_size	= 0;
-  gmask		= 0;
-
-  /* See if this is an interrupt handler.  Call used registers must be saved
-     for them too.  */
-  fn_type = m32r_compute_function_type (current_function_decl);
-  interrupt_p = M32R_INTERRUPT_P (fn_type);
-
-  /* Calculate space needed for registers.  */
-
-  for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
-    {
-      if (MUST_SAVE_REGISTER (regno, interrupt_p))
-	{
-	  reg_size += UNITS_PER_WORD;
-	  gmask |= 1 << regno;
-	}
-    }
-
-  current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
-  current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
-
-  reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
-	       * UNITS_PER_WORD);
-  total_size += reg_size;
-
-  /* ??? Not sure this is necessary, and I don't think the epilogue
-     handler will do the right thing if this changes total_size.  */
-  total_size = M32R_STACK_ALIGN (total_size);
-
-  frame_size = total_size - (pretend_size + reg_size);
-
-  /* Save computed information.  */
-  current_frame_info.total_size   = total_size;
-  current_frame_info.extra_size   = extra_size;
-  current_frame_info.pretend_size = pretend_size;
-  current_frame_info.var_size     = var_size;
-  current_frame_info.args_size    = args_size;
-  current_frame_info.reg_size	  = reg_size;
-  current_frame_info.gmask	  = gmask;
-  current_frame_info.initialized  = reload_completed;
-
-  /* Ok, we're done.  */
-  return total_size;
-}
-
-/* When the `length' insn attribute is used, this macro specifies the
-   value to be assigned to the address of the first insn in a
-   function.  If not specified, 0 is used.  */
-
-int
-m32r_first_insn_address ()
-{
-  if (! current_frame_info.initialized)
-    m32r_compute_frame_size (get_frame_size ());
-
-  return 0;
-}
-
-/* Expand the m32r prologue as a series of insns.  */
-
-void
-m32r_expand_prologue ()
-{
-  int regno;
-  int frame_size;
-  unsigned int gmask;
-
-  if (! current_frame_info.initialized)
-    m32r_compute_frame_size (get_frame_size ());
-
-  gmask = current_frame_info.gmask;
-
-  /* These cases shouldn't happen.  Catch them now.  */
-  if (current_frame_info.total_size == 0 && gmask)
-    abort ();
-
-  /* Allocate space for register arguments if this is a variadic function.  */
-  if (current_frame_info.pretend_size != 0)
-    {
-      /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
-	 the wrong result on a 64-bit host.  */
-      HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
-      emit_insn (gen_addsi3 (stack_pointer_rtx,
-			     stack_pointer_rtx,
-			     GEN_INT (-pretend_size)));
-    }
-
-  /* Save any registers we need to and set up fp.  */
-
-  if (current_frame_info.save_fp)
-    emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
-
-  gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
-
-  /* Save any needed call-saved regs (and call-used if this is an
-     interrupt handler).  */
-  for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
-    {
-      if ((gmask & (1 << regno)) != 0)
-	emit_insn (gen_movsi_push (stack_pointer_rtx,
-				   gen_rtx_REG (Pmode, regno)));
-    }
-
-  if (current_frame_info.save_lr)
-    emit_insn (gen_movsi_push (stack_pointer_rtx,
-			       gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
-
-  /* Allocate the stack frame.  */
-  frame_size = (current_frame_info.total_size
-		- (current_frame_info.pretend_size
-		   + current_frame_info.reg_size));
-
-  if (frame_size == 0)
-    ; /* nothing to do */
-  else if (frame_size <= 32768)
-    emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
-			   GEN_INT (-frame_size)));
-  else
-    {
-      rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
-      emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
-      emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
-    }
-
-  if (frame_pointer_needed)
-    emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
-
-  if (profile_flag || profile_block_flag)
-    emit_insn (gen_blockage ());
-}
-
-
-/* Set up the stack and frame pointer (if desired) for the function.
-   Note, if this is changed, you need to mirror the changes in
-   m32r_compute_frame_size which calculates the prolog size.  */
-
-void
-m32r_output_function_prologue (file, size)
-     FILE * file;
-     int    size;
-{
-  enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
-
-  /* If this is an interrupt handler, mark it as such.  */
-  if (M32R_INTERRUPT_P (fn_type))
-    {
-      fprintf (file, "\t%s interrupt handler\n",
-	       ASM_COMMENT_START);
-    }
-
-  if (! current_frame_info.initialized)
-    m32r_compute_frame_size (size);
-
-  /* This is only for the human reader.  */
-  fprintf (file,
-	   "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
-	   ASM_COMMENT_START,
-	   current_frame_info.var_size,
-	   current_frame_info.reg_size / 4,
-	   current_frame_info.args_size,
-	   current_frame_info.extra_size);
-}
-
-/* Do any necessary cleanup after a function to restore stack, frame,
-   and regs. */
-
-void
-m32r_output_function_epilogue (file, size)
-     FILE * file;
-     int    size;
-{
-  int regno;
-  int noepilogue = FALSE;
-  int total_size;
-  enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
-
-  /* This is only for the human reader.  */
-  fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
-
-  if (!current_frame_info.initialized)
-    abort ();
-  total_size = current_frame_info.total_size;
-
-  if (total_size == 0)
-    {
-      rtx insn = get_last_insn ();
-
-      /* If the last insn was a BARRIER, we don't have to write any code
-	 because a jump (aka return) was put there.  */
-      if (GET_CODE (insn) == NOTE)
-	insn = prev_nonnote_insn (insn);
-      if (insn && GET_CODE (insn) == BARRIER)
-	noepilogue = TRUE;
-    }
-
-  if (!noepilogue)
-    {
-      unsigned int pretend_size = current_frame_info.pretend_size;
-      unsigned int frame_size = total_size - pretend_size;
-      unsigned int var_size = current_frame_info.var_size;
-      unsigned int args_size = current_frame_info.args_size;
-      unsigned int gmask = current_frame_info.gmask;
-      int can_trust_sp_p = !current_function_calls_alloca;
-      char * sp_str = reg_names[STACK_POINTER_REGNUM];
-      char * fp_str = reg_names[FRAME_POINTER_REGNUM];
-
-      /* The first thing to do is point the sp at the bottom of the register
-	 save area.  */
-      if (can_trust_sp_p)
-	{
-	  unsigned int reg_offset = var_size + args_size;
-	  if (reg_offset == 0)
-	    ; /* nothing to do */
-	  else if (reg_offset < 128)
-	    fprintf (file, "\taddi %s,%s%d\n",
-		     sp_str, IMMEDIATE_PREFIX, reg_offset);
-	  else if (reg_offset < 32768)
-	    fprintf (file, "\tadd3 %s,%s,%s%d\n",
-		     sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
-	  else
-	    fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
-		     reg_names[PROLOGUE_TMP_REGNUM],
-		     IMMEDIATE_PREFIX, reg_offset,
-		     sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
-	}
-      else if (frame_pointer_needed)
-	{
-	  unsigned int reg_offset = var_size + args_size;
-	  if (reg_offset == 0)
-	    fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
-	  else if (reg_offset < 32768)
-	    fprintf (file, "\tadd3 %s,%s,%s%d\n",
-		     sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
-	  else
-	    fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
-		     reg_names[PROLOGUE_TMP_REGNUM],
-		     IMMEDIATE_PREFIX, reg_offset,
-		     sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
-	}
-      else
-	abort ();
-
-      if (current_frame_info.save_lr)
-	fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
-
-      /* Restore any saved registers, in reverse order of course.  */
-      gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
-      for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
-	{
-	  if ((gmask & (1L << regno)) != 0)
-	    fprintf (file, "\tpop %s\n", reg_names[regno]);
-	}
-
-      if (current_frame_info.save_fp)
-	fprintf (file, "\tpop %s\n", fp_str);
-
-      /* Remove varargs area if present.  */
-      if (current_frame_info.pretend_size != 0)
-	fprintf (file, "\taddi %s,%s%d\n",
-		 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
-	
-      /* Emit the return instruction.  */
-      if (M32R_INTERRUPT_P (fn_type))
-	fprintf (file, "\trte\n");
-      else
-	fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
-    }
-
-#if 0 /* no longer needed */
-  /* Ensure the function cleanly ends on a 32 bit boundary.  */
-  fprintf (file, "\t.fillinsn\n");
-#endif
-
-  /* Reset state info for each function.  */
-  current_frame_info = zero_frame_info;
-  m32r_compute_function_type (NULL_TREE);
-}
-
-/* Return non-zero if this function is known to have a null or 1 instruction
-   epilogue.  */
-
-int
-direct_return ()
-{
-  if (!reload_completed)
-    return FALSE;
-
-  if (! current_frame_info.initialized)
-    m32r_compute_frame_size (get_frame_size ());
-
-  return current_frame_info.total_size == 0;
-}
-
-
-/* PIC */
-
-/* Emit special PIC prologues and epilogues.  */
-
-void
-m32r_finalize_pic ()
-{
-  /* nothing to do */
-}
-
-/* Nested function support.  */
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-void
-m32r_initialize_trampoline (tramp, fnaddr, cxt)
-     rtx tramp, fnaddr, cxt;
-{
-}
-
-/* Set the cpu type and print out other fancy things,
-   at the top of the file.  */
-
-void
-m32r_asm_file_start (file)
-     FILE * file;
-{
-  if (flag_verbose_asm)
-    fprintf (file, "%s M32R/D special options: -G %d\n",
-	     ASM_COMMENT_START, g_switch_value);
-}
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-void
-m32r_print_operand (file, x, code)
-     FILE * file;
-     rtx    x;
-     int    code;
-{
-  rtx addr;
-
-  switch (code)
-    {
-      /* The 's' and 'p' codes are used by output_block_move() to
-	 indicate post-increment 's'tores and 'p're-increment loads.  */
-    case 's':
-      if (GET_CODE (x) == REG)
-	fprintf (file, "@+%s", reg_names [REGNO (x)]);
-      else
-	output_operand_lossage ("invalid operand to %s code");
-      return;
-      
-    case 'p':
-      if (GET_CODE (x) == REG)
-	fprintf (file, "@%s+", reg_names [REGNO (x)]);
-      else
-	output_operand_lossage ("invalid operand to %p code");
-      return;
-
-    case 'R' :
-      /* Write second word of DImode or DFmode reference,
-	 register or memory.  */
-      if (GET_CODE (x) == REG)
-	fputs (reg_names[REGNO (x)+1], file);
-      else if (GET_CODE (x) == MEM)
-	{
-	  fprintf (file, "@(");
-	  /* Handle possible auto-increment.  Since it is pre-increment and
-	     we have already done it, we can just use an offset of four.  */
-	  /* ??? This is taken from rs6000.c I think.  I don't think it is
-	     currently necessary, but keep it around.  */
-	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
-	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
-	    output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
-	  else
-	    output_address (plus_constant (XEXP (x, 0), 4));
-	  fputc (')', file);
-	}
-      else
-	output_operand_lossage ("invalid operand to %R code");
-      return;
-
-    case 'H' : /* High word */
-    case 'L' : /* Low word */
-      if (GET_CODE (x) == REG)
-	{
-	  /* L = least significant word, H = most significant word */
-	  if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
-	    fputs (reg_names[REGNO (x)], file);
-	  else
-	    fputs (reg_names[REGNO (x)+1], file);
-	}
-      else if (GET_CODE (x) == CONST_INT
-	       || GET_CODE (x) == CONST_DOUBLE)
-	{
-	  rtx first, second;
-
-	  split_double (x, &first, &second);
-	  fprintf (file, "0x%08lx",
-		   code == 'L' ? INTVAL (first) : INTVAL (second));
-	}
-      else
-	output_operand_lossage ("invalid operand to %H/%L code");
-      return;
-
-    case 'A' :
-      {
-	REAL_VALUE_TYPE d;
-	char str[30];
-
-	if (GET_CODE (x) != CONST_DOUBLE
-	    || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
-	  fatal_insn ("Bad insn for 'A'", x);
-	REAL_VALUE_FROM_CONST_DOUBLE (d, x);
-	REAL_VALUE_TO_DECIMAL (d, "%.20e", str);
-	fprintf (file, "%s", str);
-	return;
-      }
-
-    case 'B' : /* Bottom half */
-    case 'T' : /* Top half */
-      /* Output the argument to a `seth' insn (sets the Top half-word).
-	 For constants output arguments to a seth/or3 pair to set Top and
-	 Bottom halves.  For symbols output arguments to a seth/add3 pair to
-	 set Top and Bottom halves.  The difference exists because for
-	 constants seth/or3 is more readable but for symbols we need to use
-	 the same scheme as `ld' and `st' insns (16 bit addend is signed).  */
-      switch (GET_CODE (x))
-	{
-	case CONST_INT :
-	case CONST_DOUBLE :
-	  {
-	    rtx first, second;
-
-	    split_double (x, &first, &second);
-	    x = WORDS_BIG_ENDIAN ? second : first;
-	    fprintf (file,
-#if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
-		     "0x%x",
-#else
-		     "0x%lx",
-#endif
-		     (code == 'B'
-		      ? INTVAL (x) & 0xffff
-		      : (INTVAL (x) >> 16) & 0xffff));
-	  }
-	  return;
-	case CONST :
-	case SYMBOL_REF :
-	  if (code == 'B'
-	      && small_data_operand (x, VOIDmode))
-	    {
-	      fputs ("sda(", file);
-	      output_addr_const (file, x);
-	      fputc (')', file);
-	      return;
-	    }
-	  /* fall through */
-	case LABEL_REF :
-	  fputs (code == 'T' ? "shigh(" : "low(", file);
-	  output_addr_const (file, x);
-	  fputc (')', file);
-	  return;
-	default :
-	  output_operand_lossage ("invalid operand to %T/%B code");
-	  return;
-	}
-      break;
-
-    case 'U' :
-      /* ??? wip */
-      /* Output a load/store with update indicator if appropriate.  */
-      if (GET_CODE (x) == MEM)
-	{
-	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
-	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
-	    fputs (".a", file);
-	}
-      else
-	output_operand_lossage ("invalid operand to %U code");
-      return;
-
-    case 'N' :
-      /* Print a constant value negated.  */
-      if (GET_CODE (x) == CONST_INT)
-	output_addr_const (file, GEN_INT (- INTVAL (x)));
-      else
-	output_operand_lossage ("invalid operand to %N code");
-      return;
-
-    case 'X' :
-      /* Print a const_int in hex.  Used in comments.  */
-      if (GET_CODE (x) == CONST_INT)
-	fprintf (file,
-#if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
-		 "0x%x",
-#else
-		 "0x%lx",
-#endif
-		 INTVAL (x));
-      return;
-
-    case '#' :
-      fputs (IMMEDIATE_PREFIX, file);
-      return;
-
-#if 0 /* ??? no longer used */
-    case '@' :
-      fputs (reg_names[SDA_REGNUM], file);
-      return;
-#endif
-
-    case 0 :
-      /* Do nothing special.  */
-      break;
-
-    default :
-      /* Unknown flag.  */
-      output_operand_lossage ("invalid operand output code");
-    }
-
-  switch (GET_CODE (x))
-    {
-    case REG :
-      fputs (reg_names[REGNO (x)], file);
-      break;
-
-    case MEM :
-      addr = XEXP (x, 0);
-      if (GET_CODE (addr) == PRE_INC)
-	{
-	  if (GET_CODE (XEXP (addr, 0)) != REG)
-	    fatal_insn ("Pre-increment address is not a register", x);
-
-	  fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
-	}
-      else if (GET_CODE (addr) == PRE_DEC)
-	{
-	  if (GET_CODE (XEXP (addr, 0)) != REG)
-	    fatal_insn ("Pre-decrement address is not a register", x);
-
-	  fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
-	}
-      else if (GET_CODE (addr) == POST_INC)
-	{
-	  if (GET_CODE (XEXP (addr, 0)) != REG)
-	    fatal_insn ("Post-increment address is not a register", x);
-
-	  fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
-	}
-      else
-	{
-	  fputs ("@(", file);
-	  output_address (XEXP (x, 0));
-	  fputc (')', file);
-	}
-      break;
-
-    case CONST_DOUBLE :
-      /* We handle SFmode constants here as output_addr_const doesn't.  */
-      if (GET_MODE (x) == SFmode)
-	{
-	  REAL_VALUE_TYPE d;
-	  long l;
-
-	  REAL_VALUE_FROM_CONST_DOUBLE (d, x);
-	  REAL_VALUE_TO_TARGET_SINGLE (d, l);
-	  fprintf (file, "0x%08lx", l);
-	  break;
-	}
-
-      /* Fall through.  Let output_addr_const deal with it.  */
-
-    default :
-      output_addr_const (file, x);
-      break;
-    }
-}
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-void
-m32r_print_operand_address (file, addr)
-     FILE * file;
-     rtx    addr;
-{
-  register rtx base;
-  register rtx index = 0;
-  int          offset = 0;
-
-  switch (GET_CODE (addr))
-    {
-    case REG :
-      fputs (reg_names[REGNO (addr)], file);
-      break;
-
-    case PLUS :
-      if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
-	offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
-      else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
-	offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
-      else
-	base = XEXP (addr, 0), index = XEXP (addr, 1);
-      if (GET_CODE (base) == REG)
-	{
-	  /* Print the offset first (if present) to conform to the manual.  */
-	  if (index == 0)
-	    {
-	      if (offset != 0)
-		fprintf (file, "%d,", offset);
-	      fputs (reg_names[REGNO (base)], file);
-	    }
-	  /* The chip doesn't support this, but left in for generality.  */
-	  else if (GET_CODE (index) == REG)
-	    fprintf (file, "%s,%s",
-		     reg_names[REGNO (base)], reg_names[REGNO (index)]);
-	  /* Not sure this can happen, but leave in for now.  */
-	  else if (GET_CODE (index) == SYMBOL_REF)
-	    {
-	      output_addr_const (file, index);
-	      fputc (',', file);
-	      fputs (reg_names[REGNO (base)], file);
-	    }
-	  else
-	    fatal_insn ("Bad address", addr);
-	}
-      else if (GET_CODE (base) == LO_SUM)
-	{
-	  if (index != 0
-	      || GET_CODE (XEXP (base, 0)) != REG)
-	    abort ();
-	  if (small_data_operand (XEXP (base, 1), VOIDmode))
-	    fputs ("sda(", file);
-	  else
-	    fputs ("low(", file);
-	  output_addr_const (file, plus_constant (XEXP (base, 1), offset));
-	  fputs ("),", file);
-	  fputs (reg_names[REGNO (XEXP (base, 0))], file);
-	}
-      else
-	fatal_insn ("Bad address", addr);
-      break;
-
-    case LO_SUM :
-      if (GET_CODE (XEXP (addr, 0)) != REG)
-	fatal_insn ("Lo_sum not of register", addr);
-      if (small_data_operand (XEXP (addr, 1), VOIDmode))
-	fputs ("sda(", file);
-      else
-	fputs ("low(", file);
-      output_addr_const (file, XEXP (addr, 1));
-      fputs ("),", file);
-      fputs (reg_names[REGNO (XEXP (addr, 0))], file);
-      break;
-
-    case PRE_INC :	/* Assume SImode */
-      fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case PRE_DEC :	/* Assume SImode */
-      fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case POST_INC :	/* Assume SImode */
-      fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    default :
-      output_addr_const (file, addr);
-      break;
-    }
-}
-
-/* Return true if the operands are the constants 0 and 1.  */
-int
-zero_and_one (operand1, operand2)
-     rtx operand1;
-     rtx operand2;
-{
-  return
-       GET_CODE (operand1) == CONST_INT
-    && GET_CODE (operand2) == CONST_INT
-    && (  ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
-	||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
-}
-
-/* Return non-zero if the operand is suitable for use in a conditional move sequence.  */
-int
-conditional_move_operand (operand, int_mode)
-     rtx operand;
-     int int_mode;
-{
-  enum machine_mode mode = (enum machine_mode)int_mode;
-
-  /* Only defined for simple integers so far... */
-  if (mode != SImode && mode != HImode && mode != QImode)
-    return FALSE;
-
-  /* At the moment we can hanndle moving registers and loading constants.  */
-  /* To be added: Addition/subtraction/bitops/multiplication of registers.  */
-
-  switch (GET_CODE (operand))
-    {
-    case REG:
-      return 1;
-
-    case CONST_INT:
-      return INT8_P (INTVAL (operand));
-
-    default:
-#if 0
-      fprintf (stderr, "Test for cond move op of type: %s\n",
-	       GET_RTX_NAME (GET_CODE (operand)));
-#endif
-      return 0;
-    }
-}
-
-/* Return true if the code is a test of the carry bit */
-int
-carry_compare_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  rtx x;
-
-  if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
-    return FALSE;
-
-  if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
-    return FALSE;
-
-  x = XEXP (op, 0);
-  if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
-    return FALSE;
-
-  x = XEXP (op, 1);
-  if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
-    return FALSE;
-
-  return TRUE;
-}
-
-/* Place into the buffer an assembler instruction which can be executed in the S pipe.  */
-static void
-emit_S_clause (dest, source, buffer)
-     rtx    dest;
-     rtx    source;
-     char * buffer;
-{
-  char * dest_reg;
-
-  
-  dest_reg = reg_names [REGNO (dest)];
-  
-  switch (GET_CODE (source))
-    {
-    case REG:
-      sprintf (buffer, "mv %s, %s", dest_reg, reg_names [REGNO (source)]);
-      break;
-      
-    case CONST_INT:
-      sprintf (buffer, "ldi %s, #%d", dest_reg, INTVAL (source));
-      break;
-
-      /* Todo: other S pipe instructions.  */
-    default:
-      abort();
-    }
-
-  return;
-}
-
-
-/* Generate the correct assembler code to handle the conditional loading of a
-   value into a register.  It is known that the operands satisfy the
-   conditional_move_operand() function above.  The destination is operand[0].
-   The condition is operand [1].  The 'true' value is operand [2] and the
-   'false' value is operand [3].  */
-char *
-emit_cond_move (operands, insn)
-     rtx * operands;
-     rtx   insn;
-{
-  static char buffer [100];
-
-  buffer [0] = 0;
-  
-  /* Destination must be a register.  */
-  if (GET_CODE (operands [0]) != REG)
-    abort();
-  if (! conditional_move_operand (operands [2], SImode))
-    abort();
-  if (! conditional_move_operand (operands [3], SImode))
-    abort();
-      
-
-  /* Check to see if the test is reversed.  */
-  if (GET_CODE (operands [1]) == NE)
-    {
-      rtx tmp = operands [2];
-      operands [2] = operands [3];
-      operands [3] = tmp;
-    }
-
-  /* Catch a special case where 0 or 1 is being loaded into the destination.
-     Since we already have these values in the C bit we can use a special
-     instruction.  */
-  if (zero_and_one (operands [2], operands [3]))
-    {
-      char * dest = reg_names [REGNO (operands [0])];
-      
-      sprintf (buffer, "mvfc %s, cbr", dest);
-
-      /* If the true value was '0' then we need to invert the results of the move.  */
-      if (INTVAL (operands [2]) == 0)
-	sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
-		 dest, dest);
-      
-      return buffer;
-    }
-
-  
-  /* Test to see if the then clause is redundant.  */
-  if (GET_CODE (operands [2]) == REG
-      && REGNO (operands [2]) == REGNO (operands [0]))
-    /* Do not do anything for the then clause.  */
-    ;
-  else
-    {
-      /* Generate the then clause.  */
-      sprintf (buffer, "snc || ");
-      emit_S_clause (operands [0], operands [2], buffer + strlen (buffer));
-    }
-  
-  /* Test to see if the else clause is redundant.  */
-  if (GET_CODE (operands [3]) == REG
-      && REGNO (operands [3]) == REGNO (operands [0]))
-    /* Do not do anything for the else clause.  */
-    ;
-  else
-    {
-      /* Generate the else clause.  */
-
-      if (* buffer != 0)
-	strcat (buffer, "\n\t");
-      
-      strcat (buffer, "sc || ");
-      emit_S_clause (operands [0], operands [3], buffer + strlen (buffer));
-    }
-  
-
-  return buffer;
-}
-
-
-/* Return true if the code is a test of the carry bit that can be used
-   to start a conditional execution sequence.  This function is very
-   similar to carry_compare_operand() except that it allows a test
-   for 'register == register' and 'register == 0' as well as the
-   normal 'carry flag set'.  */
-int
-conditional_compare_operand (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  rtx x;
-
-  if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
-    return FALSE;
-
-  if (   GET_CODE (op) != NE
-      && GET_CODE (op) != EQ
-      && GET_CODE (op) != LE
-      && GET_CODE (op) != GE
-      && GET_CODE (op) != LT
-      && GET_CODE (op) != GT)
-    return FALSE;
-
-  x = XEXP (op, 0);
-  if (GET_CODE (x) != REG)
-    return FALSE;
-
-  /* Allow a test of 'reg eq/ne reg' or 'Carry flag set/not set'.  */
-  x = XEXP (op, 1);
-  if (GET_CODE (x) == CONST_INT)
-    {
-      if (INTVAL (x) != 0)
-	return FALSE;
-
-      return TRUE;
-    }
-  else if (GET_CODE (x) != REG)
-    return FALSE;
-  
-  return TRUE;
-}
-
-/* Return true if the binary operator can go inside of a s{n}c || operation. */
-int
-binary_parallel_operator (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  rtx op0, op1;
-
-  /* Can only handle integer operations.  */
-  if (   GET_MODE (op) != SImode
-      && GET_MODE (op) != HImode
-      && GET_MODE (op) != QImode)
-    return FALSE;
-
-  /* Can only handle simple binary operations.  */
-  if (   GET_CODE (op) != PLUS
-      && GET_CODE (op) != MINUS
-      && GET_CODE (op) != MULT
-      && GET_CODE (op) != AND
-      && GET_CODE (op) != IOR
-      && GET_CODE (op) != XOR)
-    return FALSE;
-
-  op0 = XEXP (op, 0);
-  op1 = XEXP (op, 1);
-
-  while (GET_CODE (op0) == SUBREG)
-    op0 = SUBREG_REG (op0);
-
-  while (GET_CODE (op1) == SUBREG)
-    op1 = SUBREG_REG (op1);
-
-  if (GET_CODE (op0) != REG)
-    return FALSE;
-
-  /* Allowable opreations are entirely register based
-     or the addition of a small constant to a register.  */
-  if (GET_CODE (op1) == REG)
-    {
-      return TRUE;
-    }
-  else if (GET_CODE (op1) == CONST_INT)
-    {
-      if (GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
-	return INT8_P (INTVAL (op1));
-    }
-
-  return FALSE;
-}
-
-/* Generate the assembler statement for the given comparison RTL.
-   Returns true if the sense of the comparison is reversed.  */
-static int
-generate_comparison (operand, buffer)
-     rtx    operand;
-     char * buffer;
-{
-  rtx op1 = XEXP (operand, 0);
-  rtx op2 = XEXP (operand, 1);
-  int reverse_sense = FALSE;
-
-  
-  if (GET_CODE (op1) != REG)
-    abort();
-
-  /* If we are testing the carry bit the comparison has already been generated.
-     Since there is only one bit, the only viable tests are NE and EQ.  If the
-     test is NE, then we must reverse the sense of the comparision.  */
-  if (REGNO (op1) == CARRY_REGNUM)
-    return GET_CODE (operand) == NE;
-    
-  /* Handle tests of a value in a register.  */
-  switch (GET_CODE (operand))
-    {
-    case NE:
-      reverse_sense = TRUE;
-      /* Fall through.  */
-    case EQ:
-      if (GET_CODE (op2) == REG)
-	sprintf (buffer, "cmpeq %s %s\n\t",
-		 reg_names [REGNO (op1)], reg_names [REGNO (op2)]);
-      else if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0)
-	sprintf (buffer, "cmpz %s\n\t", reg_names [REGNO (op1)]);
-      else
-	abort();
-      break;
-      
-    case GE:
-      reverse_sense = TRUE;
-      /* Fall through.  */
-    case LT:
-      if (GET_CODE (op2) != CONST_INT || ! INT16_P (INTVAL (op2)))
-	abort();
-      
-      sprintf (buffer, "cmpi %s, #%d\n\t", reg_names [REGNO (op1)], INTVAL (op2));
-      break;
-      
-    case GT:
-      reverse_sense = TRUE;
-      /* Fall through.  */
-    case LE:
-      if (GET_CODE (op2) != CONST_INT || ! INT16_P (INTVAL (op2) + 1))
-	abort();
-      
-      sprintf (buffer, "cmpi %s, #%d\n\t", reg_names [REGNO (op1)], INTVAL (op2) + 1);
-      break;
-      
-    default:
-      abort();
-    }
-
-  /* These generated comparisons are inverted.  */
-  return ! reverse_sense;
-}
-      
-     
-
-/* Generate the correct assembler code to handle the conditional execution of a
-   simple binary operation.  It is known that the operation satisfies
-   binary_parallel_operand() and that the condition satifies
-   conditional_compare_operand().  The operation is in operands [4] and its two
-   arguments are in operands [1] and [2].  The destination of the operation is
-   operands [0], which is the same as operands [1].  The condition is in
-   operands [3], and if 'condition_true' is non-zero then the operation should
-   be performed if the condition is true, otherwise it should be performed if
-   the condition is false.  */
-char *
-emit_binary_cond_exec (operands, condition_true)
-     rtx * operands;
-     int   condition_true;
-{
-  static char buffer [100];
-
-  buffer [0] = 0;
-
-  /* Destination and first operand must be registers.  */
-  if (   GET_CODE (operands [0]) != REG
-      || GET_CODE (operands [1]) != REG)
-    abort();
-  
-  /* Destination must be the same as the first opreand.  */
-  if (REGNO (operands [0]) != REGNO (operands [1]))
-    abort();
-
-  /* Generate the comparison and if necessary reverse the sense of the test.  */
-  if (generate_comparison (operands [3], buffer))
-    condition_true = ! condition_true;
-  
-  /* Generate the appropriate abort of the following binary operation.  */
-  if (condition_true)
-    strcat (buffer, "snc || ");
-  else
-    strcat (buffer, "sc || ");
-
-  /* Generate the binary operation.  */
-  switch (GET_CODE (operands [4]))
-    {
-    case PLUS:  strcat (buffer, "add "); break;
-    case MINUS:	strcat (buffer, "sub "); break;
-    case MULT:	strcat (buffer, "mul "); break;
-    case AND:	strcat (buffer, "and "); break;
-    case IOR:	strcat (buffer, "or  "); break;
-    case XOR:	strcat (buffer, "xor "); break;
-    default:    abort();
-    }
-
-  /* Generate the arguments for the binary operation.  */
-  if (GET_CODE (operands [2]) == REG)
-    sprintf (buffer + strlen (buffer), "%s, %s",
-	     reg_names [REGNO (operands [0])],
-	     reg_names [REGNO (operands [2])]);
-  else if (GET_CODE (operands [2]) == CONST_INT)
-    sprintf (buffer + strlen (buffer), "%s, %d",
-	     reg_names [REGNO (operands [0])],
-	     INTVAL (operands [2]));
-  else
-    abort();
-
-  return buffer;
-}
-
-/* Return true if the unary operator can go inside of a s{n}c || operation.  */
-int
-unary_parallel_operator (op, int_mode)
-     rtx op;
-     int int_mode;
-{
-  /* Can only handle integer operations.  */
-  if (   GET_MODE (op) != SImode
-      && GET_MODE (op) != HImode
-      && GET_MODE (op) != QImode)
-    return FALSE;
-
-  /* Can only handle simple unary operations.  */
-  if (   GET_CODE (op) != NEG
-      && GET_CODE (op) != NOT)
-    return FALSE;
-
-  /* Can only handle register based operations.  */
-  op = XEXP (op, 0);
-  while (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) == REG)
-    return TRUE;
-    
-  return FALSE;
-}
-
-/* Generate the correct assembler code to handle the conditional execution
-   of a simple unary operation.  It is known that the operation satisfies
-   unary_parallel_operand() and that the condition satifies
-   conditional_compare_operand().  The operation is in operands [3] and
-   its argument is in operands [1].  The destination of the operation is
-   operands [0].  The condition is in operands [2], and if 'condition_true' is
-   non-zero then the operation should be performed if the condition is true,
-   otherwise it should be performed if the condition is false.  */
-char *
-emit_unary_cond_exec (operands, condition_true)
-     rtx * operands;
-     int   condition_true;
-{
-  static char buffer [100];
-
-  buffer [0] = 0;
-
-  /* Destination and operand must be registers.  */
-  if (   GET_CODE (operands [0]) != REG
-      || GET_CODE (operands [1]) != REG)
-    abort();
-
-  /* Generate the comparison, and if necessary reverse the sense of the test.  */
-  if (generate_comparison (operands [2], buffer))
-    condition_true = ! condition_true;
-  
-  /* Generate the appropriate abort of the following binary operation.  */
-  if (condition_true)
-    strcat (buffer, "snc || ");
-  else
-    strcat (buffer, "sc || ");
-
-  /* Generate the unary operation.  */
-  switch (GET_CODE (operands [3]))
-    {
-    case NOT: strcat (buffer, "not "); break;
-    case NEG: strcat (buffer, "neg "); break;
-    default:  abort();
-    }
-
-  /* Generate the arguments for the unary operation.  */
-  sprintf (buffer + strlen (buffer), "%s, %s",
-	   reg_names [REGNO (operands [0])],
-	   reg_names [REGNO (operands [1])]);
-  
-  return buffer;
-}
-
-/* END CYGNUS LOCAL -- meissner/m32r work */
-
-/* Returns true if the registers contained in the two
-   rtl expressions are different. */
-int
-m32r_not_same_reg (a, b)
-     rtx a;
-     rtx b;
-{
-  int reg_a = -1;
-  int reg_b = -2;
-  
-  while (GET_CODE (a) == SUBREG)
-    a = SUBREG_REG (a);
-  
-  if (GET_CODE (a) == REG)
-    reg_a = REGNO (a);
-  
-  while (GET_CODE (b) == SUBREG)
-    b = SUBREG_REG (b);
-  
-  if (GET_CODE (b) == REG)
-    reg_b = REGNO (b);
-  
-  return reg_a != reg_b;
-}
-
-
-/* Use a library function to move some bytes.  */
-static void
-block_move_call (dest_reg, src_reg, bytes_rtx)
-     rtx dest_reg;
-     rtx src_reg;
-     rtx bytes_rtx;
-{
-  /* We want to pass the size as Pmode, which will normally be SImode
-     but will be DImode if we are using 64 bit longs and pointers.  */
-  if (GET_MODE (bytes_rtx) != VOIDmode
-      && GET_MODE (bytes_rtx) != Pmode)
-    bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
-
-#ifdef TARGET_MEM_FUNCTIONS
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
-		     VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
-		     convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
-				      TREE_UNSIGNED (sizetype)),
-		     TYPE_MODE (sizetype));
-#else
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
-		     VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
-		     convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
-				      TREE_UNSIGNED (integer_type_node)),
-		     TYPE_MODE (integer_type_node));
-#endif
-}
-
-/* The maximum number of bytes to copy using pairs of load/store instructions.
-   If a block is larger than this then a loop will be generated to copy
-   MAX_MOVE_BYTES chunks at a time.  The value of 32 is a semi-arbitary choice.
-   A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
-   string copy in it.  */
-#define MAX_MOVE_BYTES 32
-
-/* Expand string/block move operations.
-
-   operands[0] is the pointer to the destination.
-   operands[1] is the pointer to the source.
-   operands[2] is the number of bytes to move.
-   operands[3] is the alignment.  */
-
-void
-m32r_expand_block_move (operands)
-     rtx operands[];
-{
-  rtx           orig_dst  = operands[0];
-  rtx           orig_src  = operands[1];
-  rtx           bytes_rtx = operands[2];
-  rtx           align_rtx = operands[3];
-  int           constp    = GET_CODE (bytes_rtx) == CONST_INT;
-  HOST_WIDE_INT bytes     = constp ? INTVAL (bytes_rtx) : 0;
-  int           align     = INTVAL (align_rtx);
-  int           leftover;
-  rtx           src_reg;
-  rtx           dst_reg;
-
-  if (constp && bytes <= 0)
-    return;
-
-  /* Move the address into scratch registers.  */
-  dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
-  src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
-
-  if (align > UNITS_PER_WORD)
-    align = UNITS_PER_WORD;
-
-  /* If we prefer size over speed, always use a function call.
-     If we do not know the size, use a function call.
-     If the blocks are not word aligned, use a function call.  */
-  if (optimize_size || ! constp || align != UNITS_PER_WORD)
-    {
-      block_move_call (dst_reg, src_reg, bytes_rtx);
-      return;
-    }
-
-  leftover = bytes % MAX_MOVE_BYTES;
-  bytes   -= leftover;
-  
-  /* If necessary, generate a loop to handle the bulk of the copy.  */
-  if (bytes)
-    {
-      rtx label;
-      rtx final_src;
-      rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
-      rtx rounded_total = GEN_INT (bytes);
-
-      /* If we are going to have to perform this loop more than
-	 once, then generate a label and compute the address the
-	 source register will contain upon completion of the final
-	 itteration.  */
-      if (bytes > MAX_MOVE_BYTES)
-	{
-	  final_src = gen_reg_rtx (Pmode);
-
-	  if (INT16_P(bytes))
-	    emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
-	  else
-	    {
-	      emit_insn (gen_movsi (final_src, rounded_total));
-	      emit_insn (gen_addsi3 (final_src, final_src, src_reg));
-	    }
-
-	  label = gen_label_rtx ();
-	  emit_label (label);
-	}
-
-      /* It is known that output_block_move() will update src_reg to point
-	 to the word after the end of the source block, and dst_reg to point
-	 to the last word of the destination block, provided that the block
-	 is MAX_MOVE_BYTES long.  */
-      emit_insn (gen_movstrsi_internal (dst_reg, src_reg, at_a_time));
-      emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
-      
-      if (bytes > MAX_MOVE_BYTES)
-	{
-	  emit_insn (gen_cmpsi (src_reg, final_src));
-	  emit_jump_insn (gen_bne (label));
-	}
-    }
-
-  if (leftover)
-    emit_insn (gen_movstrsi_internal (dst_reg, src_reg, GEN_INT (leftover)));
-}
-
-
-/* Emit load/stores for a small constant word aligned block_move. 
-
-   operands[0] is the memory address of the destination.
-   operands[1] is the memory address of the source.
-   operands[2] is the number of bytes to move.
-   operands[3] is a temp register.
-   operands[4] is a temp register.  */
-
-char *
-m32r_output_block_move (insn, operands)
-     rtx insn;
-     rtx operands[];
-{
-  HOST_WIDE_INT bytes = INTVAL (operands[2]);
-  int		first_time;
-  int		got_extra = 0;
-  
-  if (bytes < 1 || bytes > MAX_MOVE_BYTES)
-    abort ();
-  
-  /* We do not have a post-increment store available, so the first set of
-     stores are done without any increment, then the remaining ones can use
-     the pre-increment addressing mode.
-     
-     Note: expand_block_move() also relies upon this behaviour when building
-     loops to copy large blocks.  */
-  first_time = 1;
-  
-  while (bytes > 0)
-    {
-      if (bytes >= 8)
-	{
-	  if (first_time)
-	    {
-	      output_asm_insn ("ld\t%3, %p1", operands);
-	      output_asm_insn ("ld\t%4, %p1", operands);
-	      output_asm_insn ("st\t%3, @%0", operands);
-	      output_asm_insn ("st\t%4, %s0", operands);
-	    }
-	  else
-	    {
-	      output_asm_insn ("ld\t%3, %p1", operands);
-	      output_asm_insn ("ld\t%4, %p1", operands);
-	      output_asm_insn ("st\t%3, %s0", operands);
-	      output_asm_insn ("st\t%4, %s0", operands);
-	    }
-
-	  bytes -= 8;
-	}
-      else if (bytes >= 4)
-	{
-	  if (bytes > 4)
-	    got_extra = 1;
-	  
-	  output_asm_insn ("ld\t%3, %p1", operands);
-	  
-	  if (got_extra)
-	    output_asm_insn ("ld\t%4, %p1", operands);
-		
-	  if (first_time)
-	    output_asm_insn ("st\t%3, @%0", operands);
-	  else
-	    output_asm_insn ("st\t%3, %s0", operands);
-
-	  bytes -= 4;
-	}
-      else 
-	{
-	  /* Get the entire next word, even though we do not want all of it.
-	     The saves us from doing several smaller loads, and we assume that
-	     we cannot cause a page fault when at least part of the word is in
-	     valid memory [since we don't get called if things aren't properly
-	     aligned].  */
-	  int dst_offset = first_time ? 0 : 4;
-	  int last_shift;
-	  rtx my_operands[3];
-
-	  /* If got_extra is true then we have already loaded
-	     the next word as part of loading and storing the previous word.  */
-	  if (! got_extra)
-	    output_asm_insn ("ld\t%4, @%1", operands);
-
-	  if (bytes >= 2)
-	    {
-	      bytes -= 2;
-
-	      output_asm_insn ("sra3\t%3, %4, #16", operands);
-	      my_operands[0] = operands[3];
-	      my_operands[1] = GEN_INT (dst_offset);
-	      my_operands[2] = operands[0];
-	      output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
-	      
-	      /* If there is a byte left to store then increment the
-		 destination address and shift the contents of the source
-		 register down by 8 bits.  We could not do the address
-		 increment in the store half word instruction, because it does
-		 not have an auto increment mode.  */
-	      if (bytes > 0)  /* assert (bytes == 1) */
-		{
-		  dst_offset += 2;
-		  last_shift = 8;
-		}
-	    }
-	  else
-	    last_shift = 24;
-
-	  if (bytes > 0)
-	    {
-	      my_operands[0] = operands[4];
-	      my_operands[1] = GEN_INT (last_shift);
-	      output_asm_insn ("srai\t%0, #%1", my_operands);
-	      my_operands[0] = operands[4];
-	      my_operands[1] = GEN_INT (dst_offset);
-	      my_operands[2] = operands[0];
-	      output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
-	    }
-	  
-	  bytes = 0;
-	}
-
-      first_time = 0;
-    }
-
-  return "";
-}
-
-/* Return true if op is an integer constant, less than or equal to
-   MAX_MOVE_BYTES.  */
-int
-m32r_block_immediate_operand (op, mode)
-     rtx op;
-     int mode;
-{
-  if (GET_CODE (op) != CONST_INT
-      || INTVAL (op) > MAX_MOVE_BYTES
-      || INTVAL (op) <= 0)
-    return 0;
-
-  return 1;
-}
-
diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h
deleted file mode 100755
index d6e5f4c..0000000
--- a/gcc/config/m32r/m32r.h
+++ /dev/null
@@ -1,2408 +0,0 @@
-/* CYGNUS LOCAL -- meissner/m32r work */
-/* Definitions of target machine for GNU compiler, Mitsubishi M32R cpu.
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* ??? Create elf.h and have svr4.h include it.  */
-#include "svr4.h"
-
-#undef SWITCH_TAKES_ARG
-#undef WORD_SWITCH_TAKES_ARG
-#undef HANDLE_SYSV_PRAGMA
-#undef SIZE_TYPE
-#undef PTRDIFF_TYPE
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-#undef ASM_FILE_START
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-#undef TARGET_VERSION
-#undef CPP_SPEC
-#undef ASM_SPEC
-#undef LINK_SPEC
-#undef STARTFILE_SPEC
-#undef ENDFILE_SPEC
-#undef SUBTARGET_SWITCHES
-
-/* M32R/X overrides */
-/* Print subsidiary information on the compiler version in use.  */
-#define TARGET_VERSION fprintf (stderr, " (m32r/x)");
-
-/* Additional flags for the preprocessor.  */
-#define CPP_CPU_SPEC "%{m32rx:-D__M32RX__} %{m32r:-U__M32RX__}"
-
-/* Assembler switches */
-#define ASM_CPU_SPEC \
-"%{m32r} %{m32rx} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
-
-/* Use m32rx specific crt0/crtinit/crtfini files */
-#define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
-#define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
-
-/* Extra machine dependent switches */
-#define SUBTARGET_SWITCHES						\
-    { "32rx",			TARGET_M32RX_MASK, "Compile for the m32rx" },  \
-    { "32r",			-TARGET_M32RX_MASK, "" },
-
-/* A C expression for the maximum number of instructions to execute via
-   conditional execution instructions instead of a branch.  A value of
-   BRANCH_COST+1 is the default if the machine does not use cc0, and 1 if it
-   does use cc0. */
-#define MAX_CONDITIONAL_EXECUTE m32rx_cond_exec
-
-extern char * m32rx_cond_exec_string;
-extern int    m32rx_cond_exec;
-
-/* m32rx specific switches that take values */
-#define SUBTARGET_OPTIONS ,{ "cond-exec=", & m32rx_cond_exec_string, \
-  "Maximum number of conditionally executed instructions" }
-
-/* Define this macro as a C expression for the initializer of an array of
-   strings to tell the driver program which options are defaults for this
-   target and thus do not need to be handled specially when using
-   `MULTILIB_OPTIONS'.  */
-#define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
-
-/* Number of additional registers the subtarget defines.  */
-#define SUBTARGET_NUM_REGISTERS 1
-
-/* 1 for registers that cannot be allocated.  */
-#define SUBTARGET_FIXED_REGISTERS , 1
-
-/* 1 for registers that are not available across function calls */
-#define SUBTARGET_CALL_USED_REGISTERS , 1
-
-/* Order to allocate model specific registers */
-#define SUBTARGET_REG_ALLOC_ORDER , 19
-
-/* Registers which are accumulators */
-#define SUBTARGET_REG_CLASS_ACCUM 0x80000
-
-/* All registers added */
-#define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
-
-/* Additional accumulator registers */
-#define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
-
-/* Define additional register names */
-#define SUBTARGET_REGISTER_NAMES , "a1"
-/* end M32R/X overrides */
-
-
-/* Print subsidiary information on the compiler version in use.  */
-#ifndef	TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (m32r)")
-#endif
-
-/* Switch  Recognition by gcc.c.  Add -G xx support */
-
-#define SWITCH_TAKES_ARG(CHAR) \
-(DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
-
-/* Names to predefine in the preprocessor for this target machine.  */
-/* __M32R__ is defined by the existing compiler so we use that.  */
-#define CPP_PREDEFINES "-Acpu(m32r) -Amachine(m32r) -D__M32R__"
-
-/* This macro defines names of additional specifications to put in the specs
-   that can be used in various specifications like CC1_SPEC.  Its definition
-   is an initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   specification name, and a string constant that used by the GNU CC driver
-   program.
-
-   Do not define this macro if it does not need to do anything.  */
-
-#ifndef SUBTARGET_EXTRA_SPECS
-#define SUBTARGET_EXTRA_SPECS
-#endif
-
-#ifndef	ASM_CPU_SPEC
-#define	ASM_CPU_SPEC ""
-#endif
-
-#ifndef	CPP_CPU_SPEC
-#define	CPP_CPU_SPEC ""
-#endif
-
-#ifndef	CC1_CPU_SPEC
-#define	CC1_CPU_SPEC ""
-#endif
-
-#ifndef	LINK_CPU_SPEC
-#define	LINK_CPU_SPEC ""
-#endif
-
-#ifndef STARTFILE_CPU_SPEC
-#define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
-#endif
-
-#ifndef ENDFILE_CPU_SPEC
-#define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
-#endif
-
-#ifndef RELAX_SPEC
-#if 0 /* not supported yet */
-#define RELAX_SPEC "%{mrelax:-relax}"
-#else
-#define RELAX_SPEC ""
-#endif
-#endif
-
-#define EXTRA_SPECS							\
-  { "asm_cpu",			ASM_CPU_SPEC },				\
-  { "cpp_cpu",			CPP_CPU_SPEC },				\
-  { "cc1_cpu",			CC1_CPU_SPEC },				\
-  { "link_cpu",			LINK_CPU_SPEC },			\
-  { "startfile_cpu",		STARTFILE_CPU_SPEC },			\
-  { "endfile_cpu",		ENDFILE_CPU_SPEC },			\
-  { "relax",			RELAX_SPEC },				\
-  SUBTARGET_EXTRA_SPECS
-
-#define CC1_SPEC "%{G*} %(cc1_cpu)"
-
-/* Options to pass on to the assembler.  */
-#define ASM_SPEC "%{v} %(asm_cpu) %(relax)"
-#undef	ASM_FINAL_SPEC
-
-#define LINK_SPEC "%{v} %(link_cpu) %(relax)"
-
-#define STARTFILE_SPEC "%(startfile_cpu)"
-#define ENDFILE_SPEC "%(endfile_cpu)"
-     
-#undef LIB_SPEC
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* If non-zero, tell the linker to do relaxing.
-   We don't do anything with the option, other than recognize it.
-   LINK_SPEC handles passing -relax to the linker.
-   This can cause incorrect debugging information as line numbers may
-   turn out wrong.  This shouldn't be specified unless accompanied with -O2
-   [where the user expects debugging information to be less accurate].  */
-#define TARGET_RELAX_MASK 1
-
-/* For miscellaneous debugging purposes.  */
-#define TARGET_DEBUG_MASK (1 << 1)
-#define TARGET_DEBUG (target_flags & TARGET_DEBUG_MASK)
-
-/* Align loops to 32 byte boundaries (cache line size).  */
-/* ??? This option is experimental and is not documented.  */
-#define TARGET_ALIGN_LOOPS_MASK (1 << 2)
-#define TARGET_ALIGN_LOOPS (target_flags & TARGET_ALIGN_LOOPS_MASK)
-
-/* Change issue rate */
-#define TARGET_ISSUE_RATE_MASK	(1 << 3)
-#define TARGET_ISSUE_RATE	(target_flags & TARGET_ISSUE_RATE_MASK)
-
-/* Target machine to compile for.  */
-#define TARGET_M32R 1
-
-/* Support extended instruction set.  */
-#define TARGET_M32RX_MASK	(1 << 4)
-#define TARGET_M32RX		(target_flags & TARGET_M32RX_MASK)
-#undef	TARGET_M32R
-#define TARGET_M32R		(! TARGET_M32RX)
-
-/* Change branch cost */
-#define TARGET_BRANCH_COST_MASK	(1 << 5)
-#define TARGET_BRANCH_COST	(target_flags & TARGET_BRANCH_COST_MASK)
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#ifndef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES
-#endif
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 0
-#endif
-
-#define TARGET_SWITCHES							\
-{									\
-/*  { "relax",			TARGET_RELAX_MASK },			\
-    { "no-relax",		-TARGET_RELAX_MASK },*/			\
-    { "debug",			TARGET_DEBUG_MASK, 			\
-	"Display compile time statistics" },				\
-    { "align-loops",		TARGET_ALIGN_LOOPS_MASK, 		\
-	"Align all loops to 32 byte boundary" },			\
-    { "no-align-loops",		-TARGET_ALIGN_LOOPS_MASK, "" },		\
-    { "issue-rate=1",		TARGET_ISSUE_RATE_MASK, 		\
-	"Only issue one instruction per cycle" },			\
-    { "issue-rate=2",		-TARGET_ISSUE_RATE_MASK, "" },		\
-    { "branch-cost=1",		TARGET_BRANCH_COST_MASK, 		\
-	"Prefer branches over conditional execution" },			\
-    { "branch-cost=2",		-TARGET_BRANCH_COST_MASK, "" },		\
-    SUBTARGET_SWITCHES							\
-    { "", TARGET_DEFAULT }						\
-}
-
-extern char * m32r_model_string;
-extern char * m32r_sdata_string;
-
-#define TARGET_OPTIONS							\
-{									\
-  { "model=", & m32r_model_string, "Code size: small, medium or large" },\
-  { "sdata=", & m32r_sdata_string, "Small data area: none, sdata, use" } \
-  SUBTARGET_OPTIONS							\
-}
-
-/* Code Models
-
-   Code models are used to select between two choices of two separate
-   possibilities (address space size, call insn to use):
-
-   small: addresses use 24 bits, use bl to make calls
-   medium: addresses use 32 bits, use bl to make calls (*1)
-   large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
-
-   The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
-   using this one doesn't make much sense.
-
-   (*1) The linker may eventually be able to relax seth/add3 -> ld24.
-   (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
-
-   Internally these are recorded as TARGET_ADDR{24,32} and
-   TARGET_CALL{26,32}.
-
-   The __model__ attribute can be used to select the code model to use when
-   accessing particular objects.  */
-
-enum m32r_model
-{
-  M32R_MODEL_SMALL,
-  M32R_MODEL_MEDIUM,
-  M32R_MODEL_LARGE
-};
-
-extern enum m32r_model m32r_model;
-#define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
-#define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
-#define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
-#define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
-#define TARGET_ADDR32 (! TARGET_ADDR24)
-#define TARGET_CALL26 (! TARGET_CALL32)
-#define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
-
-/* The default is the small model.  */
-#ifndef M32R_MODEL_DEFAULT
-#define M32R_MODEL_DEFAULT "small"
-#endif
-
-/* Small Data Area
-
-   The SDA consists of sections .sdata, .sbss, and .scommon.
-   .scommon isn't a real section, symbols in it have their section index
-   set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
-
-   Two switches control the SDA:
-
-   -G NNN        - specifies the maximum size of variable to go in the SDA
-
-   -msdata=foo   - specifies how such variables are handled
-
-        -msdata=none  - small data area is disabled
-
-        -msdata=sdata - small data goes in the SDA, special code isn't
-                        generated to use it, and special relocs aren't
-                        generated
-
-        -msdata=use   - small data goes in the SDA, special code is generated
-                        to use the SDA and special relocs are generated
-
-   The SDA is not multilib'd, it isn't necessary.
-   MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
-   libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
-   -msdata=use will successfully link with them (references in header files
-   will cause the compiler to emit code that refers to library objects in
-   .data).  ??? There can be a problem if the user passes a -G value greater
-   than the default and a library object in a header file is that size.
-   The default is 8 so this should be rare - if it occurs the user
-   is required to rebuild the libraries or use a smaller value for -G.
-*/
-
-/* Maximum size of variables that go in .sdata/.sbss.
-   The -msdata=foo switch also controls how small variables are handled.  */
-#ifndef SDATA_DEFAULT_SIZE
-#define SDATA_DEFAULT_SIZE 8
-#endif
-
-extern int g_switch_value;		/* value of the -G xx switch */
-extern int g_switch_set;		/* whether -G xx was passed.  */
-
-enum m32r_sdata
-{
-  M32R_SDATA_NONE,
-  M32R_SDATA_SDATA,
-  M32R_SDATA_USE
-};
-
-extern enum m32r_sdata m32r_sdata;
-#define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
-#define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
-#define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
-
-/* Default is to disable the SDA
-   [for upward compatibility with previous toolchains].  */
-#ifndef M32R_SDATA_DEFAULT
-#define M32R_SDATA_DEFAULT "none"
-#endif
-
-/* Define this macro as a C expression for the initializer of an array of
-   strings to tell the driver program which options are defaults for this
-   target and thus do not need to be handled specially when using
-   `MULTILIB_OPTIONS'.  */
-#ifndef SUBTARGET_MULTILIB_DEFAULTS
-#define SUBTARGET_MULTILIB_DEFAULTS
-#endif
-
-#ifndef MULTILIB_DEFAULTS
-#define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
-#endif
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-
-#ifndef SUBTARGET_OVERRIDE_OPTIONS
-#define SUBTARGET_OVERRIDE_OPTIONS
-#endif
-
-#define OVERRIDE_OPTIONS						\
-do {									\
-  /* These need to be done at start up.					\
-     It's convenient to do them here.  */				\
-  m32r_init ();								\
-  SUBTARGET_OVERRIDE_OPTIONS						\
-} while (0)
-
-/* Some machines may desire to change what optimizations are
-   performed for various optimization levels.   This macro, if
-   defined, is executed once just after the optimization level is
-   determined and before the remainder of the command options have
-   been parsed.  Values set in this macro are used as the default
-   values for the other command line options.
-
-   LEVEL is the optimization level specified; 2 if `-O2' is
-   specified, 1 if `-O' is specified, and 0 if neither is specified.
-
-   SIZE is non-zero if `-Os' is specified and zero otherwise.
-
-   You should not use this macro to change options that are not
-   machine-specific.  These should uniformly selected by the same
-   optimization level on all supported machines.  Use this macro to
-   enable machbine-specific optimizations.
-
-   *Do not examine `write_symbols' in this macro!* The debugging
-   options are not supposed to alter the generated code.  */
-#ifndef SUBTARGET_OPTIMIZATION_OPTIONS
-#define SUBTARGET_OPTIMIZATION_OPTIONS
-#endif
-
-#define OPTIMIZATION_OPTIONS(LEVEL, SIZE)				\
-do {									\
-  if (LEVEL == 1)							\
-    flag_regmove = TRUE;						\
-									\
-  if (SIZE)								\
-    {									\
-      flag_omit_frame_pointer = TRUE;					\
-      flag_strength_reduce = FALSE;					\
-    }									\
-									\
-  SUBTARGET_OPTIMIZATION_OPTIONS					\
-} while (0)
-
-/* Define this macro if debugging can be performed even without a frame
-   pointer.  If this macro is defined, GNU CC will turn on the
-   `-fomit-frame-pointer' option whenever `-O' is specified.  This is disabled
-   because the debugger cannot find the start of a function when optimization
-   is specified.  */
-/* #define CAN_DEBUG_WITHOUT_FP */
-
-
-/* Target machine storage layout.  */
-
-/* Define to use software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion.  */
-#define REAL_ARITHMETIC
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.  */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* Define this macro if WORDS_BIG_ENDIAN is not constant.  This must
-   be a constant value with the same meaning as WORDS_BIG_ENDIAN,
-   which will be used only when compiling libgcc2.c.  Typically the
-   value will be set based on preprocessor defines.  */
-/*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
-
-/* Number of bits in an addressable storage unit.  */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Define this macro if it is advisable to hold scalars in registers
-   in a wider mode than that declared by the program.  In such cases, 
-   the value is constrained to be within the bounds of the declared
-   type, but kept valid in the wider mode.  The signedness of the
-   extension may differ from that of the type.  */
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)				\
-if (GET_MODE_CLASS (MODE) == MODE_INT					\
-    && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)				\
-{									\
-  (MODE) = SImode;							\
-}
-
-/* Define this macro if the promotion described by `PROMOTE_MODE'
-   should also be done for outgoing function arguments.  */
-/*#define PROMOTE_FUNCTION_ARGS*/
-
-/* Likewise, if the function return value is promoted.
-   If defined, FUNCTION_VALUE must perform the same promotions done by
-   PROMOTE_MODE.  */
-/*#define PROMOTE_FUNCTION_RETURN*/
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 32
-
-/* ALIGN FRAMES on word boundaries */
-#define M32R_STACK_ALIGN(LOC) (((LOC)+3) & ~3)
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 32
-
-/* The best alignment to use in cases where we have a choice.  */
-#define FASTEST_ALIGNMENT 32
-
-/* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)					\
-  ((TREE_CODE (EXP) == STRING_CST					\
-    && (ALIGN) < FASTEST_ALIGNMENT)					\
-   ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)					\
-  (TREE_CODE (TYPE) == ARRAY_TYPE					\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode				\
-   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Layout of source language data types.  */
-
-#define SHORT_TYPE_SIZE		16
-#define INT_TYPE_SIZE		32
-#define LONG_TYPE_SIZE		32
-#define LONG_LONG_TYPE_SIZE	64
-#define FLOAT_TYPE_SIZE		32
-#define DOUBLE_TYPE_SIZE	64
-#define LONG_DOUBLE_TYPE_SIZE	64
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-#define SIZE_TYPE "long unsigned int"
-#define PTRDIFF_TYPE "long int"
-#define WCHAR_TYPE "short unsigned int"
-#define WCHAR_TYPE_SIZE 16
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  */
-
-#define M32R_NUM_REGISTERS 19
-
-#ifndef SUBTARGET_NUM_REGISTERS
-#define SUBTARGET_NUM_REGISTERS 0
-#endif
-
-#define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
-	
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   0-3   - arguments/results
-   4-5   - call used [4 is used as a tmp during prologue/epilogue generation]
-   6     - call used, gptmp
-   7     - call used, static chain pointer
-   8-11  - call saved
-   12    - call saved [reserved for global pointer]
-   13    - frame pointer
-   14    - subroutine link register
-   15    - stack pointer
-   16    - arg pointer
-   17    - carry flag
-   18	 - accumulator
-   19    - accumulator 1 in the m32r/x
-   
-   By default, the extension registers are not available.  */
-
-#ifndef SUBTARGET_FIXED_REGISTERS
-#define SUBTARGET_FIXED_REGISTERS
-#endif
-
-#define FIXED_REGISTERS							\
-{									\
-  0, 0, 0, 0, 0, 0, 0, 0,						\
-  0, 0, 0, 0, 0, 0, 0, 1,						\
-  1, 1, 1								\
-  SUBTARGET_FIXED_REGISTERS						\
-}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-
-#ifndef SUBTARGET_CALL_USED_REGISTERS
-#define SUBTARGET_CALL_USED_REGISTERS
-#endif
-
-#define CALL_USED_REGISTERS						\
-{									\
-  1, 1, 1, 1, 1, 1, 1, 1,						\
-  0, 0, 0, 0, 0, 0, 1, 1,						\
-  1, 1, 1								\
-  SUBTARGET_CALL_USED_REGISTERS						\
-}
-
-/* Zero or more C statements that may conditionally modify two variables
-   `fixed_regs' and `call_used_regs' (both of type `char []') after they
-   have been initialized from the two preceding macros.
-
-   This is necessary in case the fixed or call-clobbered registers depend
-   on target flags.
-
-   You need not define this macro if it has no work to do.  */
-
-#ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
-#define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
-#endif
-
-/* If defined, an initializer for a vector of integers, containing the
-   numbers of hard registers in the order in which GNU CC should
-   prefer to use them (from most preferred to least).  */
-
-#ifndef SUBTARGET_REG_ALLOC_ORDER
-#define SUBTARGET_REG_ALLOC_ORDER
-#endif
-
-#if 1 /* better for int code */
-#define REG_ALLOC_ORDER							\
-{									\
-  4,  5,  6,  7,  2,  3,  8,  9, 10,					\
-  11, 12, 13, 14,  0,  1, 15, 16, 17, 18				\
-  SUBTARGET_REG_ALLOC_ORDER						\
-}
-
-#else /* better for fp code at expense of int code */
-#define REG_ALLOC_ORDER							\
-{									\
-   0,  1,  2,  3,  4,  5,  6,  7,  8,					\
-   9, 10, 11, 12, 13, 14, 15, 16, 17, 18				\
-  SUBTARGET_REG_ALLOC_ORDER						\
-}
-#endif
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.  */
-#define HARD_REGNO_NREGS(REGNO, MODE) \
-((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.  */
-extern unsigned int m32r_hard_regno_mode_ok[];
-extern unsigned int m32r_mode_class[];
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
-
-/* A C expression that is nonzero if it is desirable to choose
-   register allocation so as to avoid move instructions between a
-   value of mode MODE1 and a value of mode MODE2.
-
-   If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
-   MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
-   MODE2)' must be zero.  */
-
-/* Tie QI/HI/SI modes together.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-(GET_MODE_CLASS (MODE1) == MODE_INT		\
- && GET_MODE_CLASS (MODE2) == MODE_INT		\
- && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD	\
- && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
-
-/* Register classes and constants.  */
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.
-
-   It is important that any condition codes have class NO_REGS.
-   See `register_operand'.  */
-
-enum reg_class
-{
-  NO_REGS,
-  CARRY_REG,
-  ACCUM_REGS,
-  GENERAL_REGS,
-  ALL_REGS,
-  LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
-
-/* Give names of register classes as strings for dump file.   */
-#define REG_CLASS_NAMES							\
-{									\
-  "NO_REGS",								\
-  "CARRY_REG",								\
-  "ACCUM_REGS",								\
-  "GENERAL_REGS",							\
-  "ALL_REGS"								\
-}
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#ifndef SUBTARGET_REG_CLASS_CARRY
-#define SUBTARGET_REG_CLASS_CARRY 0
-#endif
-
-#ifndef SUBTARGET_REG_CLASS_ACCUM
-#define SUBTARGET_REG_CLASS_ACCUM 0
-#endif
-
-#ifndef SUBTARGET_REG_CLASS_GENERAL
-#define SUBTARGET_REG_CLASS_GENERAL 0
-#endif
-
-#ifndef SUBTARGET_REG_CLASS_ALL
-#define SUBTARGET_REG_CLASS_ALL 0
-#endif
-
-#define REG_CLASS_CONTENTS						\
-{									\
-  { 0x00000 },								\
-  { 0x20000 | SUBTARGET_REG_CLASS_CARRY },				\
-  { 0x40000 | SUBTARGET_REG_CLASS_ACCUM },				\
-  { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL },				\
-  { 0x7ffff | SUBTARGET_REG_CLASS_ALL },				\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
-#define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* A C expression which defines the machine-dependent operand constraint
-   letters for register classes.  If CHAR is such a letter, the value should be
-   the register class corresponding to it.  Otherwise, the value should be
-   `NO_REGS'.  The register letter `r', corresponding to class `GENERAL_REGS',
-   will not be passed to this macro; you do not need to handle it.
-
-   The following letters are unavailable, due to being used as
-   constraints:
-	'0'..'9'
-	'<', '>'
-	'E', 'F', 'G', 'H'
-	'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
-	'Q', 'R', 'S', 'T', 'U'
-	'V', 'X'
-	'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
-
-#define REG_CLASS_FROM_LETTER(C)					\
-((C) == 'c'	? CARRY_REG						\
- : (C) == 'a'	? ACCUM_REGS						\
- :		  NO_REGS)
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-((REGNO) < FIRST_PSEUDO_REGISTER			\
- ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM	\
- : GPR_P (reg_renumber[REGNO]))
-#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
-(CLASS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-#define CLASS_MAX_NREGS(CLASS, MODE) \
-((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* The letters I, J, K, L, M, N, O, P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.  */
-/* 'I' is used for 8 bit signed immediates.
-   'J' is used for 16 bit signed immediates.
-   'K' is used for 16 bit unsigned immediates.
-   'L' is used for 16 bit immediates left shifted by 16 (sign ???).
-   'M' is used for 24 bit unsigned immediates.
-   'N' is used for any 32 bit non-symbolic value.
-   'O' is used for 5 bit unsigned immediates (shift count).
-   'P' is used for 16 bit signed immediates for compares
-       (values in the range -32767 to +32768).  */
-
-/* Return true if a value is inside a range */
-#define IN_RANGE_P(VALUE, LOW, HIGH)					\
-  (((unsigned HOST_WIDE_INT)((VALUE) - (LOW)))				\
-   <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
-
-#define INT8_P(X) IN_RANGE_P (X, -128, 127)
-#define INT16_P(X) IN_RANGE_P (X, -32768, 32767)
-#define CMP_INT16_P(X) IN_RANGE_P (X, -32769, 32766)
-#define UINT16_P(X) IN_RANGE_P (X, 0, 65535)
-#define UPPER16_P(X) (((X) & ~0xffff0000) == 0)
-#define UINT24_P(X) IN_RANGE_P (X, 0, 0xffffff)
-#if HOST_BITS_PER_LONG > 32
-#define INT32_P(X) IN_RANGE_P (X, (-2147483647L-1), 2147483647L)
-#else
-#define INT32_P(X) 1
-#endif
-#define UINT5_P(X) IN_RANGE_P (X, 0, 31)
-#define INVERTED_SIGNED_8BIT(X) IN_RANGE_P (X, -127, 128)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)					\
-((C) == 'I' ? INT8_P (VALUE)						\
- : (C) == 'J' ? INT16_P (VALUE)						\
- : (C) == 'K' ? UINT16_P (VALUE)					\
- : (C) == 'L' ? UPPER16_P (VALUE)					\
- : (C) == 'M' ? UINT24_P (VALUE)					\
- : (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE)				\
- : (C) == 'O' ? UINT5_P (VALUE)						\
- : (C) == 'P' ? CMP_INT16_P (VALUE)					\
- : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.
-   For the m32r, handle a few constants inline.
-   ??? We needn't treat DI and DF modes differently, but for now we do.  */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
-((C) == 'G' ? easy_di_const (VALUE)					\
- : (C) == 'H' ? easy_df_const (VALUE)					\
- : 0)
-
-/* A C expression that defines the optional machine-dependent constraint
-   letters that can be used to segregate specific types of operands,
-   usually memory references, for the target machine.  It should return 1 if
-   VALUE corresponds to the operand type represented by the constraint letter
-   C.  If C is not defined as an extra constraint, the value returned should
-   be 0 regardless of VALUE.  */
-/* Q is for symbolic addresses loadable with ld24.
-   R is for symbolic addresses when ld24 can't be used.
-   S is for stores with pre {inc,dec}rement
-   T is for indirect of a pointer.
-   U is for loads with post increment.  */
-
-#define EXTRA_CONSTRAINT(VALUE, C)					\
-((C) == 'Q'   ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF)	\
-		 || addr24_operand (VALUE, VOIDmode))			\
- : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF)	\
-		 || addr32_operand (VALUE, VOIDmode))			\
- : (C) == 'S' ? (GET_CODE (VALUE) == MEM				\
-		 && STORE_PREINC_PREDEC_P (GET_MODE (VALUE),		\
-					   XEXP (VALUE, 0)))		\
- : (C) == 'T' ? (GET_CODE (VALUE) == MEM				\
-		 && memreg_operand (VALUE, GET_MODE (VALUE)))		\
- : (C) == 'U' ? (GET_CODE (VALUE) == MEM				\
-		 && LOAD_POSTINC_P (GET_MODE (VALUE),			\
-				    XEXP (VALUE, 0)))			\
- : 0)
-
-
-/* Stack layout and stack pointer usage.  */
-
-/* Define this macro if pushing a word onto the stack moves the stack
-   pointer to a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset from the frame pointer.  */
-/*#define FRAME_GROWS_DOWNWARD*/
-
-/* Offset from frame pointer to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-/* The frame pointer points at the same place as the stack pointer, except if
-   alloca has been called.  */
-#define STARTING_FRAME_OFFSET \
-M32R_STACK_ALIGN (current_function_outgoing_args_size)
-
-/* Offset from the stack pointer register to the first location at which
-   outgoing arguments are placed.  */
-#define STACK_POINTER_OFFSET 0
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* A C expression whose value is RTL representing the address in a
-   stack frame where the pointer to the caller's frame is stored.
-   Assume that FRAMEADDR is an RTL expression for the address of the
-   stack frame itself.
-
-   If you don't define this macro, the default is to return the value
-   of FRAMEADDR--that is, the stack frame address is also the address
-   of the stack word that points to the previous frame.  */
-/*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
-
-/* A C expression whose value is RTL representing the value of the
-   return address for the frame COUNT steps up from the current frame.
-   FRAMEADDR is the frame pointer of the COUNT frame, or the frame
-   pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
-   is defined.  */
-/* The current return address is in r14.  */
-#if 0 /* The default value should work.  */
-#define RETURN_ADDR_RTX(COUNT, FRAME) \
-(((COUNT) == -1)				\
- ? gen_rtx (REG, Pmode, 14)			\
- : copy_to_reg (gen_rtx (MEM, Pmode,		\
-			 memory_address (Pmode, plus_constant ((FRAME), UNITS_PER_WORD)))))
-#endif
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 15
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 13
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 16
-
-/* The register number of the return address pointer register, which
-   is used to access the current function's return address from the
-   stack.  On some machines, the return address is not at a fixed
-   offset from the frame pointer or stack pointer or argument
-   pointer.  This register can be defined to point to the return
-   address on the stack, and then be converted by `ELIMINABLE_REGS'
-   into either the frame pointer or stack pointer.
-
-   Do not define this macro unless there is no other way to get the
-   return address from the stack.  */
-/* ??? revisit */
-/* #define RETURN_ADDRESS_POINTER_REGNUM */
-
-/* Register in which static-chain is passed to a function.  This must
-   not be a register used by the prologue.  */
-#define STATIC_CHAIN_REGNUM 7
-
-/* These aren't official macros.  */
-#define PROLOGUE_TMP_REGNUM 4
-#define RETURN_ADDR_REGNUM 14
-/* #define GP_REGNUM 12 */
-#define CARRY_REGNUM 17
-#define ACCUM_REGNUM 18
-#define M32R_MAX_INT_REGS 16
-
-#ifndef SUBTARGET_GPR_P
-#define SUBTARGET_GPR_P(REGNO) 0
-#endif
-
-#ifndef SUBTARGET_ACCUM_P
-#define SUBTARGET_ACCUM_P(REGNO) 0
-#endif
-
-#ifndef SUBTARGET_CARRY_P
-#define SUBTARGET_CARRY_P(REGNO) 0
-#endif
-
-#define GPR_P(REGNO) IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO)
-#define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
-#define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
-
-
-/* Eliminating the frame and arg pointers.  */
-
-/* A C expression which is nonzero if a function must have and use a
-   frame pointer.  This expression is evaluated in the reload pass.
-   If its value is nonzero the function will have a frame pointer.  */
-#define FRAME_POINTER_REQUIRED \
-(current_function_calls_alloca)
-
-#if 0
-/* C statement to store the difference between the frame pointer
-   and the stack pointer values immediately after the function prologue.
-   If `ELIMINABLE_REGS' is defined, this macro will be not be used and
-   need not be defined.  */
-#define INITIAL_FRAME_POINTER_OFFSET(VAR) \
-((VAR) = m32r_compute_frame_size (get_frame_size ()))
-#endif
-
-/* If defined, this macro specifies a table of register pairs used to
-   eliminate unneeded registers that point into the stack frame.  If
-   it is not defined, the only elimination attempted by the compiler
-   is to replace references to the frame pointer with references to
-   the stack pointer.
-
-   Note that the elimination of the argument pointer with the stack
-   pointer is specified first since that is the preferred elimination.  */
-
-#define ELIMINABLE_REGS							\
-{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },			\
- { ARG_POINTER_REGNUM,	 STACK_POINTER_REGNUM },			\
- { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM }}			\
-
-/* A C expression that returns non-zero if the compiler is allowed to
-   try to replace register number FROM-REG with register number
-   TO-REG.  This macro need only be defined if `ELIMINABLE_REGS' is
-   defined, and will usually be the constant 1, since most of the
-   cases preventing register elimination are things that the compiler
-   already knows about.  */
-
-#define CAN_ELIMINATE(FROM, TO)						\
-((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM		\
- ? ! frame_pointer_needed						\
- : 1)
-
-/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'.  It
-   specifies the initial difference between the specified pair of
-   registers.  This macro must be defined if `ELIMINABLE_REGS' is
-   defined.  */
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
-{									\
-  int size = m32r_compute_frame_size (get_frame_size ());		\
-									\
- if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	\
-   (OFFSET) = 0;							\
- else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)	\
-   (OFFSET) = size - current_function_pretend_args_size;		\
- else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	\
-   (OFFSET) = size - current_function_pretend_args_size;		\
-  else									\
-    abort ();								\
-}
-
-/* Function argument passing.  */
-
-/* When a prototype says `char' or `short', really pass an `int'.  */
-#define PROMOTE_PROTOTYPES
-
-/* If defined, the maximum amount of space required for outgoing
-   arguments will be computed and placed into the variable
-   `current_function_outgoing_args_size'.  No space will be pushed
-   onto the stack for each call; instead, the function prologue should
-   increase the stack frame size by this amount.  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Define this macro if functions should assume that stack space has
-   been allocated for arguments even when their values are passed in
-   registers.
-
-   The value of this macro is the size, in bytes, of the area
-   reserved for arguments passed in registers for the function
-   represented by FNDECL.
-
-   This space can be allocated by the caller, or be a part of the
-   machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
-   which.  */
-#if 0
-#define REG_PARM_STACK_SPACE(FNDECL) \
-(M32R_MAX_PARM_REGS * UNITS_PER_WORD)
-#endif
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-#define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
-
-/* Nonzero if we do not know how to pass TYPE solely in registers. */
-#define MUST_PASS_IN_STACK(MODE,TYPE)			\
-  ((TYPE) != 0						\
-   && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST	\
-       || TREE_ADDRESSABLE (TYPE)))
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.  */
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
-((CUM) = 0)
-
-/* The number of registers used for parameter passing.  Local to this file.  */
-#define M32R_MAX_PARM_REGS 4
-
-/* 1 if N is a possible register number for function argument passing.  */
-#define FUNCTION_ARG_REGNO_P(N) \
-((unsigned) (N) < M32R_MAX_PARM_REGS)
-
-/* The ROUND_ADVANCE* macros are local to this file.  */
-/* Round SIZE up to a word boundary.  */
-#define ROUND_ADVANCE(SIZE) \
-(((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Round arg MODE/TYPE up to the next word boundary.  */
-#define ROUND_ADVANCE_ARG(MODE, TYPE) \
-((MODE) == BLKmode				\
- ? ROUND_ADVANCE (int_size_in_bytes (TYPE))	\
- : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
-
-/* Round CUM up to the necessary point for argument MODE/TYPE.  */
-#if 0
-#define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \
-((((MODE) == BLKmode ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) \
-  > BITS_PER_WORD)	\
- ? ((CUM) + 1 & ~1)	\
- : (CUM))
-#else
-#define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
-#endif
-
-/* Return boolean indicating arg of type TYPE and mode MODE will be passed in
-   a reg.  This includes arguments that have to be passed by reference as the
-   pointer to them is passed in a reg if one is available (and that is what
-   we're given).
-   This macro is only used in this file.  */
-#define PASS_IN_REG_P(CUM, MODE, TYPE, NAMED) \
-(ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-/* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
-   and the rest are pushed.  */
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-(PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED))				\
- ? gen_rtx (REG, (MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)))	\
- : 0)
-
-/* ??? Quick hack to try to get varargs working the normal way.  */
-#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
-(((! current_function_varargs || (NAMED))				\
-  && PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED)))			\
- ? gen_rtx (REG, (MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)))	\
- : 0)
-
-/* A C expression for the number of words, at the beginning of an
-   argument, must be put in registers.  The value must be zero for
-   arguments that are passed entirely in registers or that are entirely
-   pushed on the stack.
-
-   On some machines, certain arguments must be passed partially in
-   registers and partially in memory.  On these machines, typically the
-   first @var{n} words of arguments are passed in registers, and the rest
-   on the stack.  If a multi-word argument (a @code{double} or a
-   structure) crosses that boundary, its first few words must be passed
-   in registers and the rest must be pushed.  This macro tells the
-   compiler when this occurs, and how many of the words should go in
-   registers.  */
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-  function_arg_partial_nregs (&CUM, (int)MODE, TYPE, NAMED)
-
-/* A C expression that indicates when an argument must be passed by
-   reference.  If nonzero for an argument, a copy of that argument is
-   made in memory and a pointer to the argument is passed instead of
-   the argument itself.  The pointer is passed in whatever way is
-   appropriate for passing a pointer to that type.  */
-/* All arguments greater than 8 bytes are passed this way.  */
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
-((TYPE) && int_size_in_bytes (TYPE) > 8)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
-((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
-	  + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
-
-/* If defined, a C expression that gives the alignment boundary, in bits,
-   of an argument with the specified mode and type.  If it is not defined, 
-   PARM_BOUNDARY is used for all arguments.  */
-#if 0
-/* We assume PARM_BOUNDARY == UNITS_PER_WORD here.  */
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
-(((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
- ? PARM_BOUNDARY \
- : 2 * PARM_BOUNDARY)
-#endif
-
-#if 0
-/* If defined, is a C expression that produces the machine-specific
-   code for a call to `__builtin_saveregs'.  This code will be moved
-   to the very beginning of the function, before any parameter access
-   are made.  The return value of this function should be an RTX that
-   contains the value to use as the return of `__builtin_saveregs'.
-
-   The argument ARGS is a `tree_list' containing the arguments that
-   were passed to `__builtin_saveregs'.
-
-   If this macro is not defined, the compiler will output an ordinary
-   call to the library function `__builtin_saveregs'.  */
-extern struct rtx *m32r_expand_builtin_savergs ();
-#define EXPAND_BUILTIN_SAVEREGS(ARGS) m32r_expand_builtin_saveregs (ARGS)
-#endif
-
-/* This macro offers an alternative
-   to using `__builtin_saveregs' and defining the macro
-   `EXPAND_BUILTIN_SAVEREGS'.  Use it to store the anonymous register
-   arguments into the stack so that all the arguments appear to have
-   been passed consecutively on the stack.  Once this is done, you
-   can use the standard implementation of varargs that works for
-   machines that pass all their arguments on the stack.
-
-   The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure,
-   containing the values that obtain after processing of the named
-   arguments.  The arguments MODE and TYPE describe the last named
-   argument--its machine mode and its data type as a tree node.
-
-   The macro implementation should do two things: first, push onto the
-   stack all the argument registers *not* used for the named
-   arguments, and second, store the size of the data thus pushed into
-   the `int'-valued variable whose name is supplied as the argument
-   PRETEND_SIZE.  The value that you store here will serve as
-   additional offset for setting up the stack frame.
-
-   If the argument NO_RTL is nonzero, it means that the
-   arguments of the function are being analyzed for the second time.
-   This happens for an inline function, which is not actually
-   compiled until the end of the source file.  The macro
-   `SETUP_INCOMING_VARARGS' should not generate any instructions in
-   this case.  */
-
-#define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
-m32r_setup_incoming_varargs (&ARGS_SO_FAR, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
-
-/* Function results.  */
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-#define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.  */
-/* ??? What about r1 in DI/DF values.  */
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-/* A C expression which can inhibit the returning of certain function
-   values in registers, based on the type of value.  A nonzero value says
-   to return the function value in memory, just as large structures are
-   always returned.  Here TYPE will be a C expression of type `tree',
-   representing the data type of the value.  */
-#define RETURN_IN_MEMORY(TYPE) \
-(int_size_in_bytes (TYPE) > 8)
-
-/* Tell GCC to use RETURN_IN_MEMORY.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Register in which address to store a structure value
-   is passed to a function, or 0 to use `invisible' first argument.  */
-#define STRUCT_VALUE 0
-
-/* Function entry and exit.  */
-
-/* Initialize data used by insn expanders.  This is called from
-   init_emit, once for each function, before code is generated.  */
-#define INIT_EXPANDERS m32r_init_expanders ()
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-#define FUNCTION_PROLOGUE(FILE, SIZE) \
-m32r_output_function_prologue (FILE, SIZE)
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-#define EXIT_IGNORE_STACK 1
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-m32r_output_function_epilogue (FILE, SIZE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-#define FUNCTION_PROFILER(FILE, LABELNO) abort ()
-
-/* Trampolines.  */
-
-/* On the M32R, the trampoline is
-
-	ld24 r7,STATIC
-	ld24 r6,FUNCTION
-	jmp r6
-	nop
-
-   ??? Need addr32 support.
-*/
-
-/* Length in bytes of the trampoline for entering a nested function.  */
-#define TRAMPOLINE_SIZE 12
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-do {									\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)),	\
-		  plus_constant ((CXT), 0xe7000000));			\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)),	\
-		  plus_constant ((FNADDR), 0xe6000000));		\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)),	\
-		  GEN_INT (0x1fc67000));				\
-  emit_insn (gen_flush_icache (validize_mem (gen_rtx (MEM, SImode,	\
-						      TRAMP))));	\
-} while (0)
-
-/* Library calls.  */
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-#define MAX_REGS_PER_ADDRESS 1
-
-/* We have post-inc load and pre-dec,pre-inc store,
-   but only for 4 byte vals.  */
-#define HAVE_PRE_DECREMENT 1
-#define HAVE_PRE_INCREMENT 1
-#define HAVE_POST_INCREMENT 1
-
-/* Recognize any constant value that is a valid address.  */
-#define CONSTANT_ADDRESS_P(X) \
-(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF	\
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   We don't allow (plus symbol large-constant) as the relocations can't
-   describe it.  INTVAL > 32767 handles both 16 bit and 24 bit relocations.
-   We allow all CONST_DOUBLE's as the md file patterns will force the
-   constant to memory if they can't handle them.  */
-
-#define LEGITIMATE_CONSTANT_P(X)					\
-(! (GET_CODE (X) == CONST						\
-    && GET_CODE (XEXP (X, 0)) == PLUS					\
-    && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF			\
-    && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT			\
-    && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifdef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X)						\
-(GPR_P (REGNO (X))							\
- || (REGNO (X)) == ARG_POINTER_REGNUM					\
- || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.  */
-
-/* local to this file */
-#define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
-
-/* local to this file */
-#define RTX_OK_FOR_OFFSET_P(X) \
-(GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
-
-/* local to this file */
-#define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X)				\
-(GET_CODE (X) == PLUS							\
- && RTX_OK_FOR_BASE_P (XEXP (X, 0))					\
- && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
-
-/* local to this file */
-/* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
-   since more than one instruction will be required.  */
-#define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X)				\
-(GET_CODE (X) == LO_SUM							\
- && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)		\
- && RTX_OK_FOR_BASE_P (XEXP (X, 0))					\
- && CONSTANT_P (XEXP (X, 1)))
-
-/* local to this file */
-/* Is this a load and increment operation.  */
-#define LOAD_POSTINC_P(MODE, X)						\
-(((MODE) == SImode || (MODE) == SFmode)					\
- && GET_CODE (X) == POST_INC						\
- && GET_CODE (XEXP (X, 0)) == REG					\
- && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
-
-/* local to this file */
-/* Is this a increment/decrement and store operation.  */
-#define STORE_PREINC_PREDEC_P(MODE, X)					\
-(((MODE) == SImode || (MODE) == SFmode)					\
- && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC)		\
- && GET_CODE (XEXP (X, 0)) == REG					\
- && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-{ if (RTX_OK_FOR_BASE_P (X))						\
-    goto ADDR;								\
-  if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X)))			\
-    goto ADDR;								\
-  if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X)))			\
-    goto ADDR;								\
-  if (LOAD_POSTINC_P ((MODE), (X)))					\
-    goto ADDR;								\
-  if (STORE_PREINC_PREDEC_P ((MODE), (X)))				\
-    goto ADDR;								\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   ??? Is there anything useful we can do here for the M32R?  */
-
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.  */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)			\
-do {									\
-  if (GET_CODE (ADDR) == PRE_DEC					\
-      || GET_CODE (ADDR) == PRE_INC					\
-      || GET_CODE (ADDR) == POST_INC					\
-      || GET_CODE (ADDR) == LO_SUM)					\
-    goto LABEL;								\
-} while (0)
-
-/* Condition code usage.  */
-
-/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
-   return the mode to be used for the comparison.  */
-#define SELECT_CC_MODE(OP, X, Y) \
-((enum machine_mode)m32r_select_cc_mode ((int)OP, X, Y))
-
-/* Return non-zero if SELECT_CC_MODE will never return MODE for a
-   floating point inequality comparison.  */
-#define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
-
-/* Costs.  */
-
-/* ??? I'm quite sure I don't understand enough of the subtleties involved
-   in choosing the right numbers to use here, but there doesn't seem to be
-   enough documentation on this.  What I've done is define an insn to cost
-   4 "units" and work from there.  COSTS_N_INSNS (N) is defined as (N) * 4 - 2
-   so that seems reasonable.  Some values are supposed to be defined relative
-   to each other and thus aren't necessarily related to COSTS_N_INSNS.  */
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-/* Small integers are as cheap as registers.  4 byte values can be fetched
-   as immediate constants - let's give that the cost of an extra insn.  */
-#define CONST_COSTS(X, CODE, OUTER_CODE)				\
-  case CONST_INT :							\
-    if (INT16_P (INTVAL (X)))						\
-      return 0;								\
-    /* fall through */							\
-  case CONST :								\
-  case LABEL_REF :							\
-  case SYMBOL_REF :							\
-    return 4;								\
-  case CONST_DOUBLE :							\
-    {									\
-      rtx high, low;							\
-      split_double (X, &high, &low);					\
-      return 4 * (!INT16_P (INTVAL (high))				\
-		  + !INT16_P (INTVAL (low)));				\
-    }
-
-/* Compute the cost of an address.  */
-#define ADDRESS_COST(ADDR) m32r_address_cost (ADDR)
-
-/* Compute extra cost of moving data between one register class
-   and another.  */
-#define REGISTER_MOVE_COST(CLASS1, CLASS2) 2
-
-/* Compute the cost of moving data between registers and memory.  */
-/* Memory is 3 times as expensive as registers.
-   ??? Is that the right way to look at it?  */
-#define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \
-(GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
-
-/* The cost of a branch insn.  */
-/* A value of 2 here causes GCC to avoid using branches in comparisons like
-   while (a < N && a).  Branches aren't that expensive on the M32R so
-   we define this as 1.  Defining it as 2 had a heavy hit in fp-bit.c.  */
-#define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  The purpose for the cost of MULT is to encourage
-   `synth_mult' to find a synthetic multiply when reasonable.
-
-   If we need more than 12 insns to do a multiply, then go out-of-line,
-   since the call overhead will be < 10% of the cost of the multiply.  */
-#define RTX_COSTS(X, CODE, OUTER_CODE)					\
-  case MULT :								\
-    return COSTS_N_INSNS (3);						\
-  case DIV :								\
-  case UDIV :								\
-  case MOD :								\
-  case UMOD :								\
-    return COSTS_N_INSNS (10);
-
-/* Nonzero if access to memory by bytes is slow and undesirable.
-   For RISC chips, it means that access to memory by bytes is no
-   better than access by words when possible, so grab a whole word
-   and maybe make use of that.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* Define this macro if it is as good or better to call a constant
-   function address than to call an address kept in a register.  */
-#define NO_FUNCTION_CSE
-
-/* Define this macro if it is as good or better for a function to call
-   itself with an explicit address than to call an address kept in a
-   register.  */
-#define NO_RECURSIVE_FUNCTION_CSE
-
-/* A C statement (sans semicolon) to update the integer variable COST based on
-   the relationship between INSN that is dependent on DEP_INSN through the
-   dependence LINK.  The default is to make no adjustment to COST.  This can be
-   used for example to specify to the scheduler that an output- or
-   anti-dependence does not incur the same cost as a data-dependence.  */
-
-#define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
-  (COST) = m32r_adjust_cost (INSN, LINK, DEP_INSN, COST)
-
-/* A C statement (sans semicolon) to update the integer scheduling
-   priority `INSN_PRIORITY(INSN)'.  Reduce the priority to execute
-   the INSN earlier, increase the priority to execute INSN later.
-   Do not define this macro if you do not need to adjust the
-   scheduling priorities of insns.  */
-#define ADJUST_PRIORITY(INSN) \
-  INSN_PRIORITY (INSN) = m32r_adjust_priority (INSN, INSN_PRIORITY (INSN))
-
-/* Macro to determine whether the Haifa scheduler is used.  */
-#ifdef HAIFA
-#define HAIFA_P 1
-#else
-#define HAIFA_P 0
-#endif
-
-/* Indicate how many instructions can be issued at the same time.
-   This is sort of a lie.  The m32r can issue only 1 long insn at
-   once, but it can issue 2 short insns.  The default therefore is
-   set at 2, but this can be overridden by the command line option
-   -missue-rate=1 */
-#define ISSUE_RATE ((TARGET_ISSUE_RATE) ? 1 : 2)
-
-/* If we have a machine that can issue a variable # of instructions
-   per cycle, indicate how many more instructions can be issued
-   after the current one.  */
-#define MD_SCHED_VARIABLE_ISSUE(STREAM, VERBOSE, INSN, HOW_MANY)	\
-(HOW_MANY) = m32r_sched_variable_issue (STREAM, VERBOSE, INSN, HOW_MANY)
-
-/* Whether we are on an odd word boundary while scheduling.  */
-extern int m32r_sched_odd_word_p;
-
-/* Hook to run before scheduling a block of insns.  */
-#define MD_SCHED_INIT(STREAM, VERBOSE) m32r_sched_init (STREAM, VERBOSE)
-
-/* Hook to reorder the list of ready instructions.  */
-#define MD_SCHED_REORDER(STREAM, VERBOSE, READY, N_READY) \
-m32r_sched_reorder (STREAM, VERBOSE, READY, N_READY)
-
-/* When the `length' insn attribute is used, this macro specifies the
-   value to be assigned to the address of the first insn in a
-   function.  If not specified, 0 is used.  */
-#define FIRST_INSN_ADDRESS m32r_first_insn_address ()
-
-
-/* Section selection.  */
-
-#define TEXT_SECTION_ASM_OP	"\t.section .text"
-#define DATA_SECTION_ASM_OP	"\t.section .data"
-#define RODATA_SECTION_ASM_OP	"\t.section .rodata"
-#define BSS_SECTION_ASM_OP	"\t.section .bss"
-#define SDATA_SECTION_ASM_OP	"\t.section .sdata"
-#define SBSS_SECTION_ASM_OP	"\t.section .sbss"
-/* This one is for svr4.h.  */
-#undef CONST_SECTION_ASM_OP
-#define CONST_SECTION_ASM_OP	"\t.section .rodata"
-
-/* A list of names for sections other than the standard two, which are
-   `in_text' and `in_data'.  You need not define this macro
-   on a system with no other sections (that GCC needs to use).  */
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_sdata, in_sbss, in_const, in_ctors, in_dtors
-
-/* One or more functions to be defined in "varasm.c".  These
-   functions should do jobs analogous to those of `text_section' and
-   `data_section', for your additional sections.  Do not define this
-   macro if you do not define `EXTRA_SECTIONS'.  */
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-CONST_SECTION_FUNCTION							\
-CTORS_SECTION_FUNCTION							\
-DTORS_SECTION_FUNCTION							\
-SDATA_SECTION_FUNCTION							\
-SBSS_SECTION_FUNCTION
-
-#define SDATA_SECTION_FUNCTION						\
-void									\
-sdata_section ()							\
-{									\
-  if (in_section != in_sdata)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP);		\
-      in_section = in_sdata;						\
-    }									\
-}									\
-
-#define SBSS_SECTION_FUNCTION						\
-void									\
-sbss_section ()								\
-{									\
-  if (in_section != in_sbss)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", SBSS_SECTION_ASM_OP);		\
-      in_section = in_sbss;						\
-    }									\
-}									\
-
-/* A C statement or statements to switch to the appropriate section for
-   output of EXP.  You can assume that EXP is either a `VAR_DECL' node
-   or a constant of some sort.  RELOC indicates whether the initial value
-   of EXP requires link-time relocations.  */
-extern void m32r_select_section ();
-#undef SELECT_SECTION
-#define SELECT_SECTION(EXP, RELOC) m32r_select_section ((EXP), (RELOC))
-
-/* A C statement or statements to switch to the appropriate section for
-   output of RTX in mode MODE.  You can assume that RTX
-   is some kind of constant in RTL.  The argument MODE is redundant
-   except in the case of a `const_int' rtx.  Select the section by
-   calling `text_section' or one of the alternatives for other
-   sections.
-
-   Do not define this macro if you put all constants in the read-only
-   data section.  */
-
-#undef SELECT_RTX_SECTION
-
-/* Define this macro if jump tables (for tablejump insns) should be
-   output in the text section, along with the assembler instructions.
-   Otherwise, the readonly data section is used.
-   This macro is irrelevant if there is no separate readonly data section.  */
-/*#define JUMP_TABLES_IN_TEXT_SECTION*/
-
-/* Define this macro if references to a symbol must be treated
-   differently depending on something about the variable or
-   function named by the symbol (such as what section it is in).
-
-   The macro definition, if any, is executed immediately after the
-   rtl for DECL or other node is created.
-   The value of the rtl will be a `mem' whose address is a
-   `symbol_ref'.
-
-   The usual thing for this macro to do is to store a flag in the
-   `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
-   name string in the `symbol_ref' (if one bit is not enough
-   information).  */
-
-#define SDATA_FLAG_CHAR '@'
-/* Small objects are recorded with no prefix for space efficiency since
-   they'll be the most common.  This isn't the case if the user passes
-   -mmodel={medium|large} and one could choose to not mark symbols that
-   are the default, but that complicates things.  */
-/*#define SMALL_FLAG_CHAR '#'*/
-#define MEDIUM_FLAG_CHAR '%'
-#define LARGE_FLAG_CHAR '&'
-
-#define SDATA_NAME_P(NAME) (*(NAME) == SDATA_FLAG_CHAR)
-/*#define SMALL_NAME_P(NAME) (*(NAME) == SMALL_FLAG_CHAR)*/
-#define SMALL_NAME_P(NAME) (! ENCODED_NAME_P (NAME) && ! LIT_NAME_P (NAME))
-#define MEDIUM_NAME_P(NAME) (*(NAME) == MEDIUM_FLAG_CHAR)
-#define LARGE_NAME_P(NAME) (*(NAME) == LARGE_FLAG_CHAR)
-/* For string literals, etc.  */
-#define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
-
-#define ENCODED_NAME_P(SYMBOL_NAME) \
-(SDATA_NAME_P (SYMBOL_NAME) \
- /*|| SMALL_NAME_P (SYMBOL_NAME)*/ \
- || MEDIUM_NAME_P (SYMBOL_NAME) \
- || LARGE_NAME_P (SYMBOL_NAME))
-
-#define ENCODE_SECTION_INFO(DECL) m32r_encode_section_info (DECL)
-
-/* Decode SYM_NAME and store the real name part in VAR, sans
-   the characters that encode section info.  Define this macro if
-   ENCODE_SECTION_INFO alters the symbol's name string.  */
-/* Note that we have to handle symbols like "%*start".  */
-#define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
-do {							\
-  (VAR) = (SYMBOL_NAME) + ENCODED_NAME_P (SYMBOL_NAME);	\
-  (VAR) += *(VAR) == '*';				\
-} while (0)
-
-/* PIC */
-
-/* The register number of the register used to address a table of static
-   data addresses in memory.  In some cases this register is defined by a
-   processor's ``application binary interface'' (ABI).  When this macro
-   is defined, RTL is generated for this register once, as with the stack
-   pointer and frame pointer registers.  If this macro is not defined, it
-   is up to the machine-dependent files to allocate such a register (if
-   necessary).  */
-/*#define PIC_OFFSET_TABLE_REGNUM 12*/
-
-/* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
-   clobbered by calls.  Do not define this macro if PIC_OFFSET_TABLE_REGNUM
-   is not defined.  */
-/* This register is call-saved on the M32R.  */
-/*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
-
-/* By generating position-independent code, when two different programs (A
-   and B) share a common library (libC.a), the text of the library can be
-   shared whether or not the library is linked at the same address for both
-   programs.  In some of these environments, position-independent code
-   requires not only the use of different addressing modes, but also
-   special code to enable the use of these addressing modes.
-
-   The FINALIZE_PIC macro serves as a hook to emit these special
-   codes once the function is being compiled into assembly code, but not
-   before.  (It is not done before, because in the case of compiling an
-   inline function, it would lead to multiple PIC prologues being
-   included in functions which used inline functions and were compiled to
-   assembly language.)  */
-
-/*#define FINALIZE_PIC m32r_finalize_pic ()*/
-
-/* A C expression that is nonzero if X is a legitimate immediate
-   operand on the target machine when generating position independent code.
-   You can assume that X satisfies CONSTANT_P, so you need not
-   check this.  You can also assume `flag_pic' is true, so you need not
-   check it either.  You need not define this macro if all constants
-   (including SYMBOL_REF) can be immediate operands when generating
-   position independent code.  */
-/*#define LEGITIMATE_PIC_OPERAND_P(X)*/
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-#define ASM_FILE_START(FILE) m32r_asm_file_start (FILE)
-
-/* A C string constant describing how to begin a comment in the target
-   assembler language.  The compiler assumes that the comment will
-   end at the end of the line.  */
-#define ASM_COMMENT_START ";"
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-#define ASM_APP_OFF ""
-
-/* This is how to output an assembler line defining a `char' constant.  */
-#define ASM_OUTPUT_CHAR(FILE, VALUE)					\
-do {									\
-  fprintf (FILE, "\t.byte\t");						\
-  output_addr_const (FILE, (VALUE));					\
-  fprintf (FILE, "\n");							\
-} while (0)
-
-/* This is how to output an assembler line defining a `short' constant.  */
-#define ASM_OUTPUT_SHORT(FILE, VALUE)					\
-do {									\
-  fprintf (FILE, "\t.hword\t");						\
-  output_addr_const (FILE, (VALUE));					\
-  fprintf (FILE, "\n");							\
-} while (0)
-
-/* This is how to output an assembler line defining an `int' constant.
-   We also handle symbol output here.  */
-#define ASM_OUTPUT_INT(FILE, VALUE)					\
-do {									\
-  fprintf (FILE, "\t.word\t");						\
-  output_addr_const (FILE, (VALUE));					\
-  fprintf (FILE, "\n");							\
-} while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)					\
-do {									\
-  long t;								\
-  char str[30];								\
-  REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);				\
-  REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);			\
-  fprintf (FILE, "\t.word\t0x%lx %s %s\n",				\
-	   t, ASM_COMMENT_START, str);					\
-} while (0)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)					\
-do {									\
-  long t[2];								\
-  char str[30];								\
-  REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);				\
-  REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);			\
-  fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n",		\
-	   t[0], ASM_COMMENT_START, str, t[1]);				\
-} while (0)
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-#define ASM_OUTPUT_BYTE(FILE, VALUE)					\
-  fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
-
-/* The assembler's parentheses characters.  */
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-/* On the M32R we need to ensure the next instruction starts on a 32 bit
-   boundary [the previous insn must either be 2 16 bit insns or 1 32 bit].  */
-#define ASM_OUTPUT_LABEL(FILE, NAME)					\
-do {									\
-  assemble_name (FILE, NAME);						\
-  fputs (":\n", FILE);							\
-} while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-#define ASM_GLOBALIZE_LABEL(FILE, NAME)					\
-do {									\
-  fputs ("\t.global\t", FILE);						\
-  assemble_name (FILE, NAME);						\
-  fputs ("\n", FILE);							\
-} while (0)
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE, NAME) \
-do {							\
-  char * real_name;					\
-  STRIP_NAME_ENCODING (real_name, (NAME));		\
-  asm_fprintf (FILE, "%U%s", real_name);		\
-} while (0)           
-
-/* If -Os, don't force line number labels to begin at the beginning of
-   the word; we still want the assembler to try to put things in parallel,
-   should that be possible.
-   For m32r/d, instructions are never in parallel (other than with a nop)
-   and the simulator and stub both handle a breakpoint in the middle of
-   a word so don't ever force line number labels to begin at the beginning
-   of a word.  */
-
-#undef	ASM_OUTPUT_SOURCE_LINE
-#define ASM_OUTPUT_SOURCE_LINE(file, line)				\
-do									\
-  {									\
-    static int sym_lineno = 1;						\
-    fprintf (file, ".stabn 68,0,%d,.LM%d-",				\
-	     line, sym_lineno);						\
-    assemble_name (file,						\
-		   XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));\
-    fprintf (file,							\
-	     (optimize_size || TARGET_M32R)				\
-	     ? "\n\t.debugsym .LM%d\n"					\
-	     : "\n.LM%d:\n",						\
-	     sym_lineno);						\
-    sym_lineno += 1;							\
-  }									\
-while (0)
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)			\
-do {									\
-  (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10);			\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO));			\
-} while (0)
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-#ifndef SUBTARGET_REGISTER_NAMES
-#define SUBTARGET_REGISTER_NAMES
-#endif
-
-#define REGISTER_NAMES							\
-{									\
-  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",			\
-  "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",			\
-  "ap", "cbit", "a0"							\
-  SUBTARGET_REGISTER_NAMES						\
-}
-
-/* If defined, a C initializer for an array of structures containing
-   a name and a register number.  This macro defines additional names
-   for hard registers, thus allowing the `asm' option in declarations
-   to refer to registers using alternate names.  */
-#ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
-#define SUBTARGET_ADDITIONAL_REGISTER_NAMES
-#endif
-
-#define ADDITIONAL_REGISTER_NAMES					\
-{									\
-  /*{ "gp", GP_REGNUM },*/						\
-  { "r13", FRAME_POINTER_REGNUM },					\
-  { "r14", RETURN_ADDR_REGNUM },					\
-  { "r15", STACK_POINTER_REGNUM },					\
-  SUBTARGET_ADDITIONAL_REGISTER_NAMES					\
-}
-
-/* A C expression which evaluates to true if CODE is a valid
-   punctuation character for use in the `PRINT_OPERAND' macro.  */
-extern char m32r_punct_chars[];
-#define PRINT_OPERAND_PUNCT_VALID_P(CHAR)				\
-m32r_punct_chars[(unsigned char) (CHAR)]
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-#define PRINT_OPERAND(FILE, X, CODE)					\
-m32r_print_operand (FILE, X, CODE)
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand that is a memory
-   reference whose address is ADDR.  ADDR is an RTL expression.
-
-   On some machines, the syntax for a symbolic address depends on
-   the section that the address refers to.  On these machines,
-   define the macro `ENCODE_SECTION_INFO' to store the information
-   into the `symbol_ref', and then check for it here.  */
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)				\
-m32r_print_operand_address (FILE, ADDR)
-
-/* If defined, C string expressions to be used for the `%R', `%L',
-   `%U', and `%I' options of `asm_fprintf' (see `final.c').  These
-   are useful when a single `md' file must support multiple assembler
-   formats.  In that case, the various `tm.h' files can define these
-   macros differently.  */
-#define REGISTER_PREFIX ""
-#define LOCAL_LABEL_PREFIX ".L"
-#define USER_LABEL_PREFIX ""
-#define IMMEDIATE_PREFIX "#"
-
-/* This is how to output an element of a case-vector that is absolute.  */
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)				\
-do {									\
-  char label[30];							\
-  ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);			\
-  fprintf (FILE, "\t.word\t");						\
-  assemble_name (FILE, label);						\
-  fprintf (FILE, "\n");							\
-} while (0)
-
-/* This is how to output an element of a case-vector that is relative.  */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)		\
-do {									\
-  char label[30];							\
-  ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);			\
-  fprintf (FILE, "\t.word\t");						\
-  assemble_name (FILE, label);						\
-  fprintf (FILE, "-");							\
-  ASM_GENERATE_INTERNAL_LABEL (label, "L", REL);			\
-  assemble_name (FILE, label);						\
-  fprintf (FILE, ")\n");						\
-} while (0)
-
-/* The desired alignment for the location counter at the beginning
-   of a loop.  */
-/* On the M32R, align loops to 32 byte boundaries (cache line size)
-   if -malign-loops.  */
-#define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
-
-/* Define this to be the maximum number of insns to move around when moving
-   a loop test from the top of a loop to the bottom
-   and seeing whether to duplicate it.  The default is thirty.
-
-   Loop unrolling currently doesn't like this optimization, so
-   disable doing if we are unrolling loops and saving space.  */
-#define LOOP_TEST_THRESHOLD (optimize_size				\
-			     && !flag_unroll_loops			\
-			     && !flag_unroll_all_loops ? 2 : 30)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-/* .balign is used to avoid confusion.  */
-#define ASM_OUTPUT_ALIGN(FILE,LOG)					\
-do {									\
-  if ((LOG) != 0)							\
-    fprintf (FILE, "\t.balign %d\n", 1 << (LOG));			\
-} while (0)
-
-/* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
-   separate, explicit argument.  If you define this macro, it is used in
-   place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
-   handling the required alignment of the variable.  The alignment is
-   specified as the number of bits.  */
-
-#define SCOMMON_ASM_OP ".scomm"
-
-#undef ASM_OUTPUT_ALIGNED_COMMON
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  if (! TARGET_SDATA_NONE						\
-      && (SIZE) > 0 && (SIZE) <= g_switch_value)			\
-    fprintf ((FILE), "\t%s\t", SCOMMON_ASM_OP);				\
-  else									\
-    fprintf ((FILE), "\t%s\t", COMMON_ASM_OP);				\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
-} while (0)
-
-/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
-   separate, explicit argument.  If you define this macro, it is used in
-   place of `ASM_OUTPUT_BSS', and gives you more flexibility in
-   handling the required alignment of the variable.  The alignment is
-   specified as the number of bits.
-
-   For the M32R we need sbss support.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN)		\
-do {									\
-  ASM_GLOBALIZE_LABEL (FILE, NAME);					\
-  ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);			\
-} while (0)
-
-/* Debugging information.  */
-
-/* Generate DBX and DWARF debugging information.  */
-#undef	DBX_DEBUGGING_INFO
-#undef	DWARF_DEBUGGING_INFO
-#undef	DWARF2_DEBUGGING_INFO
-
-#define DBX_DEBUGGING_INFO
-#define DWARF_DEBUGGING_INFO
-#define DWARF2_DEBUGGING_INFO
-
-/* Prefer STABS (for now).  */
-#undef	PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* How to renumber registers for dbx and gdb.  */
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Turn off splitting of long stabs.  */
-#define DBX_CONTIN_LENGTH 0
-
-/* Miscellaneous.  */
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE Pmode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* It's not clear what PIC will look like or whether we want to use -fpic
-   for the embedded form currently being talked about.  For now require -fpic
-   to get pc relative switch tables.  */
-/*#define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.  */
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 4
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
-   few bits.  */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-#define STORE_FLAG_VALUE 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-/* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
-   it's own problems (you have to add extendpsisi2 and truncsipsi2).
-   Try to avoid it.  */
-#define Pmode SImode
-
-/* A function address in a call instruction.  */
-#define FUNCTION_MODE SImode
-
-/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
-   is a valid machine specific attribute for DECL.
-   The attributes in ATTRIBUTES have previously been assigned to TYPE.  */
-#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
-m32r_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
-
-/* A C expression that returns zero if the attributes on TYPE1 and TYPE2 are
-   incompatible, one if they are compatible, and two if they are
-   nearly compatible (which causes a warning to be generated).  */
-#define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
-m32r_comp_type_attributes (TYPE1, TYPE2)
-
-/* Give newly defined TYPE some default attributes.  */
-#define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
-m32r_set_default_type_attributes (TYPE)
-
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  Note that we can't use "rtx" here
-   since it hasn't been defined!  */
-extern struct rtx_def * m32r_compare_op0;
-extern struct rtx_def * m32r_compare_op1;
-
-/* M32R function types.   */
-enum m32r_function_type
-{
-  M32R_FUNCTION_UNKNOWN,
-  M32R_FUNCTION_NORMAL,
-  M32R_FUNCTION_INTERRUPT
-};
-
-#define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
-
-/* Define this if you have defined special-purpose predicates in the
-   file `MACHINE.c'.  This macro is called within an initializer of an
-   array of structures.  The first field in the structure is the name
-   of a predicate and the second field is an array of rtl codes.  For
-   each predicate, list all rtl codes that can be in expressions
-   matched by the predicate.  The list should have a trailing comma.  */
-
-#define PREDICATE_CODES							\
-{ "conditional_compare_operand",{ EQ, NE }},				\
-{ "binary_parallel_operator",	{ PLUS, MINUS, MULT, AND, IOR, XOR }},	\
-{ "unary_parallel_operator",	{ NOT, NEG }},				\
-{ "reg_or_zero_operand",	{ REG, SUBREG, CONST_INT }},		\
-{ "carry_compare_operand",	{ EQ, NE }},				\
-{ "eqne_comparison_operator",	{ EQ, NE }},				\
-{ "signed_comparison_operator", { EQ, NE, LT, LE, GT, GE }},		\
-{ "move_dest_operand",		{ REG, SUBREG, MEM }},			\
-{ "move_src_operand",		{ REG, SUBREG, MEM, CONST_INT,		\
-				  CONST_DOUBLE, LABEL_REF, CONST,	\
-				  SYMBOL_REF }},			\
-{ "move_double_src_operand",	{ REG, SUBREG, MEM, CONST_INT,		\
-				  CONST_DOUBLE }},			\
-{ "two_insn_const_operand",	{ CONST_INT }},				\
-{ "symbolic_operand",		{ SYMBOL_REF, LABEL_REF, CONST }},	\
-{ "seth_add3_operand",		{ SYMBOL_REF, LABEL_REF, CONST }},	\
-{ "int8_operand",		{ CONST_INT }},				\
-{ "uint16_operand",		{ CONST_INT }},				\
-{ "reg_or_int16_operand",	{ REG, SUBREG, CONST_INT }},		\
-{ "reg_or_uint16_operand",	{ REG, SUBREG, CONST_INT }},		\
-{ "reg_or_cmp_int16_operand",	{ REG, SUBREG, CONST_INT }},		\
-{ "reg_or_eq_int16_operand",	{ REG, SUBREG, CONST_INT }},		\
-{ "cmp_int16_operand",		{ CONST_INT }},				\
-{ "call_address_operand",	{ SYMBOL_REF, LABEL_REF, CONST }},	\
-{ "extend_operand",		{ REG, SUBREG, MEM }},			\
-{ "small_insn_p",		{ INSN, CALL_INSN, JUMP_INSN }},	\
-{ "m32r_not_same_reg",		{ REG, SUBREG }},			\
-{ "m32r_block_immediate_operand",{ CONST_INT }},			\
-{ "large_insn_p",		{ INSN, CALL_INSN, JUMP_INSN }},
-
-/* Functions declared in m32r.c */
-#ifndef PROTO
-#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__)
-#define PROTO(ARGS) ARGS
-#else
-#define PROTO(ARGS) ()
-#endif
-#endif
-
-#ifdef BUFSIZ		/* stdio.h has been included, ok to use FILE * */
-#define STDIO_PROTO(ARGS) PROTO(ARGS)
-#else
-#define STDIO_PROTO(ARGS) ()
-#endif
-
-#ifndef TREE_CODE
-union tree_node;
-#define Tree union tree_node *
-#else
-#define Tree tree
-#endif
-
-#ifndef RTX_CODE
-struct rtx_def;
-#define Rtx struct rtx_def *
-#else
-#define Rtx rtx
-#endif
-
-extern void sbss_section			PROTO((void));
-extern void sdata_section			PROTO((void));
-extern void m32r_init				PROTO((void));
-extern int  m32r_valid_machine_decl_attribute	PROTO((Tree, Tree, Tree, Tree));
-extern int  m32r_comp_type_attributes		PROTO((Tree, Tree));
-extern void m32r_select_section			PROTO((Tree, int));
-extern void m32r_encode_section_info		PROTO((Tree));
-extern void m32r_init_expanders			PROTO((void));
-extern int  call_address_operand		PROTO((Rtx, int));
-extern int  call_operand			PROTO((Rtx, int));
-extern int  symbolic_operand			PROTO((Rtx, int));
-extern int  small_data_operand			PROTO((Rtx, int));
-extern int  addr24_operand			PROTO((Rtx, int));
-extern int  addr32_operand			PROTO((Rtx, int));
-extern int  call26_operand			PROTO((Rtx, int));
-extern int  seth_add3_operand			PROTO((Rtx, int));
-extern int  int8_operand			PROTO((Rtx, int));
-extern int  cmp_int16_operand			PROTO((Rtx, int));
-extern int  uint16_operand			PROTO((Rtx, int));
-extern int  reg_or_int16_operand		PROTO((Rtx, int));
-extern int  reg_or_uint16_operand		PROTO((Rtx, int));
-extern int  reg_or_cmp_nt16_operand		PROTO((Rtx, int));
-extern int  reg_or_eqne_nt16_operand		PROTO((Rtx, int));
-extern int  two_insn_const_operand		PROTO((Rtx, int));
-extern int  move_src_operand			PROTO((Rtx, int));
-extern int  move_double_src_operand		PROTO((Rtx, int));
-extern int  move_dest_operand			PROTO((Rtx, int));
-extern int  easy_di_const			PROTO((Rtx));
-extern int  easy_df_const			PROTO((Rtx));
-extern int  eqne_comparison_operator		PROTO((Rtx, int));
-extern int  signed_comparison_operator		PROTO((Rtx, int));
-extern int  memreg_operand			PROTO((Rtx, int));
-extern int  extend_operand			PROTO((Rtx, int));
-extern int  reg_or_zero_operand			PROTO((Rtx, int));
-extern int  small_insn_p			PROTO((Rtx, int));
-extern int  large_insn_p			PROTO((Rtx, int));
-extern int  direct_return			PROTO((void));
-extern int  m32r_select_cc_mode			PROTO((int, Rtx, Rtx));
-extern Rtx  gen_compare				PROTO((int, Rtx, Rtx, Rtx));
-extern Rtx  gen_split_move_double		PROTO((Rtx *));
-extern int  function_arg_partial_nregs		PROTO((CUMULATIVE_ARGS *,
-						       int, Tree, int));
-extern void m32r_setup_incoming_varargs		PROTO((CUMULATIVE_ARGS *,
-						       int, Tree, int *,
-						       int));
-extern int  m32r_address_cost			PROTO((Rtx));
-extern int  m32r_adjust_cost			PROTO((Rtx, Rtx, Rtx, int));
-extern int  m32r_adjust_priority		PROTO((Rtx, int));
-extern void m32r_sched_init			STDIO_PROTO((FILE *, int));
-extern void m32r_sched_reorder			STDIO_PROTO((FILE *, int, Rtx *, int));
-extern int  m32r_sched_variable_issue		STDIO_PROTO((FILE *, int, Rtx, int));
-extern enum m32r_function_type m32r_compute_function_type
-						PROTO((Tree));
-extern unsigned m32r_compute_frame_size		PROTO((int));
-extern int  m32r_first_insn_address		PROTO((void));
-extern void m32r_expand_prologue		PROTO((void));
-extern void m32r_output_function_prologue	STDIO_PROTO((FILE *, int));
-extern void m32r_output_function_epilogue	STDIO_PROTO((FILE *, int));
-extern void m32r_finalize_pic			PROTO((void));
-extern void m32r_initialize_trampoline		PROTO((Rtx, Rtx, Rtx));
-extern void m32r_asm_file_start			STDIO_PROTO((FILE *));
-extern void m32r_print_operand			STDIO_PROTO((FILE *, Rtx, int));
-extern void m32r_print_operand_address		STDIO_PROTO((FILE *, Rtx));
-extern int  zero_and_one			PROTO((Rtx, Rtx));
-extern int  conditional_move_operand		PROTO((Rtx, int));
-extern int  carry_compare_operand		PROTO((Rtx, int));
-extern char *emit_cond_move			PROTO((Rtx *, Rtx));
-extern int  conditional_compare_operand		PROTO((Rtx, int));
-extern int  binary_parallel_operand		PROTO((Rtx, int));
-extern int  unary_parallel_operand		PROTO((Rtx, int));
-extern char *emit_binary_cond_exec		PROTO((Rtx *, int));
-extern char *emit_unary_cond_exec		PROTO((Rtx *, int));
-
-/* Externals that are referenced, but may not have the proper include file
-   dragged in.  */
-extern int optimize;
-extern int optimize_size;
-
-/* END CYGNUS LOCAL -- meissner/m32r work */
-
-extern int    m32r_not_same_reg PROTO((Rtx, Rtx));
-extern char * m32r_output_block_move PROTO((Rtx, Rtx *));
-extern int    m32r_block_immediate_operand PROTO((Rtx, int));
-extern void   m32r_expand_block_move PROTO((Rtx *));
diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md
deleted file mode 100755
index 859ed1b..0000000
--- a/gcc/config/m32r/m32r.md
+++ /dev/null
@@ -1,2649 +0,0 @@
-;; CYGNUS LOCAL -- meissner/m32r work
-;; Machine description of the Mitsubishi M32R cpu for GNU C compiler
-;; Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; unspec usage
-;; 0 - blockage
-;; 1 - flush_icache
-;; 2 - load_sda_base
-;; 3 - setting carry in addx/subx instructions.
-
-;; Insn type.  Used to default other attribute values.
-(define_attr "type"
-  "int2,int4,load2,load4,load8,store2,store4,store8,shift2,shift4,mul2,div4,uncond_branch,branch,call,multi,misc"
-  (const_string "misc"))
-
-;; Length in bytes.
-(define_attr "length" ""
-  (cond [(eq_attr "type" "int2,load2,store2,shift2,mul2")
-	 (const_int 2)
-
-	 (eq_attr "type" "int4,load4,store4,shift4,div4")
-	 (const_int 4)
-
-	 (eq_attr "type" "multi")
-	 (const_int 8)
-
-	 (eq_attr "type" "uncond_branch,branch,call")
-	 (const_int 4)]
-
-	 (const_int 4)))
-
-;; The length here is the length of a single asm.  Unfortunately it might be
-;; 2 or 4 so we must allow for 4.  That's ok though.
-(define_asm_attributes
-  [(set_attr "length" "4")
-   (set_attr "type" "multi")])
-
-
-;; Whether an instruction is 16-bit or 32-bit
-(define_attr "insn_size" "short,long"
-  (if_then_else (eq_attr "type" "int2,load2,store2,shift2,mul2")
-		(const_string "short")
-		(const_string "long")))
-
-(define_attr "debug" "no,yes"
-  (const (symbol_ref "(TARGET_DEBUG != 0)")))
-
-(define_attr "opt_size" "no,yes"
-  (const (symbol_ref "(optimize_size != 0)")))
-
-(define_attr "m32r" "no,yes"
-  (const (symbol_ref "(TARGET_M32R != 0)")))
-
-(define_attr "m32rx" "no,yes"
-  (const (symbol_ref "(TARGET_M32RX != 0)")))
-
-(define_attr "m32rx_pipeline" "either,s,o,long,m32r"
-  (cond [(eq_attr "m32rx" "no")
-	 (const_string "m32r")
-
-	 (eq_attr "insn_size" "!short")
-	 (const_string "long")]
-
-	(cond [(eq_attr "type" "int2")
-	       (const_string "either")
-
-	       (eq_attr "type" "load2,store2,shift2,uncond_branch,branch,call")
-	       (const_string "o")
-
-	       (eq_attr "type" "mul2")
-	       (const_string "s")]
-
-	      (const_string "long"))))
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Function Units
-;; ::
-;; ::::::::::::::::::::
-
-;; On most RISC machines, there are instructions whose results are not
-;; available for a specific number of cycles.  Common cases are instructions
-;; that load data from memory.  On many machines, a pipeline stall will result
-;; if the data is referenced too soon after the load instruction.
-
-;; In addition, many newer microprocessors have multiple function units,
-;; usually one for integer and one for floating point, and often will incur
-;; pipeline stalls when a result that is needed is not yet ready.
-
-;; The descriptions in this section allow the specification of how much time
-;; must elapse between the execution of an instruction and the time when its
-;; result is used.  It also allows specification of when the execution of an
-;; instruction will delay execution of similar instructions due to function
-;; unit conflicts.
-
-;; For the purposes of the specifications in this section, a machine is divided
-;; into "function units", each of which execute a specific class of
-;; instructions in first-in-first-out order.  Function units that accept one
-;; instruction each cycle and allow a result to be used in the succeeding
-;; instruction (usually via forwarding) need not be specified.  Classic RISC
-;; microprocessors will normally have a single function unit, which we can call
-;; `memory'.  The newer "superscalar" processors will often have function units
-;; for floating point operations, usually at least a floating point adder and
-;; multiplier.
-
-;; Each usage of a function units by a class of insns is specified with a
-;; `define_function_unit' expression, which looks like this:
-
-;; (define_function_unit NAME MULTIPLICITY SIMULTANEITY TEST READY-DELAY
-;;   ISSUE-DELAY [CONFLICT-LIST])
-
-;; NAME is a string giving the name of the function unit.
-
-;; MULTIPLICITY is an integer specifying the number of identical units in the
-;; processor.  If more than one unit is specified, they will be scheduled
-;; independently.  Only truly independent units should be counted; a pipelined
-;; unit should be specified as a single unit.  (The only common example of a
-;; machine that has multiple function units for a single instruction class that
-;; are truly independent and not pipelined are the two multiply and two
-;; increment units of the CDC 6600.)
-
-;; SIMULTANEITY specifies the maximum number of insns that can be executing in
-;; each instance of the function unit simultaneously or zero if the unit is
-;; pipelined and has no limit.
-
-;; All `define_function_unit' definitions referring to function unit NAME must
-;; have the same name and values for MULTIPLICITY and SIMULTANEITY.
-
-;; TEST is an attribute test that selects the insns we are describing in this
-;; definition.  Note that an insn may use more than one function unit and a
-;; function unit may be specified in more than one `define_function_unit'.
-
-;; READY-DELAY is an integer that specifies the number of cycles after which
-;; the result of the instruction can be used without introducing any stalls.
-
-;; ISSUE-DELAY is an integer that specifies the number of cycles after the
-;; instruction matching the TEST expression begins using this unit until a
-;; subsequent instruction can begin.  A cost of N indicates an N-1 cycle delay.
-;; A subsequent instruction may also be delayed if an earlier instruction has a
-;; longer READY-DELAY value.  This blocking effect is computed using the
-;; SIMULTANEITY, READY-DELAY, ISSUE-DELAY, and CONFLICT-LIST terms.  For a
-;; normal non-pipelined function unit, SIMULTANEITY is one, the unit is taken
-;; to block for the READY-DELAY cycles of the executing insn, and smaller
-;; values of ISSUE-DELAY are ignored.
-
-;; CONFLICT-LIST is an optional list giving detailed conflict costs for this
-;; unit.  If specified, it is a list of condition test expressions to be
-;; applied to insns chosen to execute in NAME following the particular insn
-;; matching TEST that is already executing in NAME.  For each insn in the list,
-;; ISSUE-DELAY specifies the conflict cost; for insns not in the list, the cost
-;; is zero.  If not specified, CONFLICT-LIST defaults to all instructions that
-;; use the function unit.
-
-;; Typical uses of this vector are where a floating point function unit can
-;; pipeline either single- or double-precision operations, but not both, or
-;; where a memory unit can pipeline loads, but not stores, etc.
-
-;; As an example, consider a classic RISC machine where the result of a load
-;; instruction is not available for two cycles (a single "delay" instruction is
-;; required) and where only one load instruction can be executed
-;; simultaneously.  This would be specified as:
-
-;; (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
-
-;; For the case of a floating point function unit that can pipeline
-;; either single or double precision, but not both, the following could be
-;; specified:
-;;
-;; (define_function_unit "fp" 1 0
-;;   (eq_attr "type" "sp_fp") 4 4
-;;   [(eq_attr "type" "dp_fp")])
-;;
-;; (define_function_unit "fp" 1 0
-;;   (eq_attr "type" "dp_fp") 4 4
-;;   [(eq_attr "type" "sp_fp")])
-
-;; Note: The scheduler attempts to avoid function unit conflicts and uses all
-;; the specifications in the `define_function_unit' expression.  It has
-;; recently come to our attention that these specifications may not allow
-;; modeling of some of the newer "superscalar" processors that have insns using
-;; multiple pipelined units.  These insns will cause a potential conflict for
-;; the second unit used during their execution and there is no way of
-;; representing that conflict.  We welcome any examples of how function unit
-;; conflicts work in such processors and suggestions for their representation.
-
-;; Function units of the M32R
-;; Units that take one cycle do not need to be specified.
-
-;; (define_function_unit {name} {multiplicity} {simulataneity} {test}
-;;                       {ready-delay} {issue-delay} [{conflict-list}])
-
-;; Hack to get GCC to better pack the instructions.
-;; We pretend there is a separate long function unit that conflicts with
-;; both the left and right 16 bit insn slots.
-
-(define_function_unit "short" 2 2
-  (and (eq_attr "m32r" "yes")
-       (and (eq_attr "insn_size" "short")
-	    (eq_attr "type" "!load2")))
-  1 0
-  [(eq_attr "insn_size" "long")])
-
-(define_function_unit "short" 2 2	;; load delay of 1 clock for mem execution + 1 clock for WB
-  (and (eq_attr "m32r" "yes")
-       (eq_attr "type" "load2"))
-  3 0
-  [(eq_attr "insn_size" "long")])
-
-(define_function_unit "long" 1 1
-  (and (eq_attr "m32r" "yes")
-       (and (eq_attr "insn_size" "long")
-	    (eq_attr "type" "!load4,load8")))
-  1 0
-  [(eq_attr "insn_size" "short")])
-
-(define_function_unit "long" 1 1	;; load delay of 1 clock for mem execution + 1 clock for WB
-  (and (eq_attr "m32r" "yes")
-       (and (eq_attr "insn_size" "long")
-	    (eq_attr "type" "load4,load8")))
-  3 0
-  [(eq_attr "insn_size" "short")])
-
-(define_function_unit "left" 1 1
-  (and (eq_attr "m32rx_pipeline" "o,either")
-       (eq_attr "type" "!load2"))
-  1 0
-  [(eq_attr "insn_size" "long")])
-
-(define_function_unit "left" 1 1	;; load delay of 1 clock for mem execution + 1 clock for WB
-  (and (eq_attr "m32rx_pipeline" "o,either")
-       (eq_attr "type" "load2"))
-  3 0
-  [(eq_attr "insn_size" "long")])
-
-(define_function_unit "right" 1 1
-  (eq_attr "m32rx_pipeline" "s,either")
-  1 0
-  [(eq_attr "insn_size" "long")])
-
-(define_function_unit "long" 1 1
-  (and (eq_attr "m32rx" "yes")
-       (and (eq_attr "insn_size" "long")
-	    (eq_attr "type" "!load4,load8")))
-  2 0
-  [(eq_attr "insn_size" "short")])
-
-(define_function_unit "long" 1 1	;; load delay of 1 clock for mem execution + 1 clock for WB
-  (and (eq_attr "m32rx" "yes")
-       (and (eq_attr "insn_size" "long")
-	    (eq_attr "type" "load4,load8")))
-  3 0
-  [(eq_attr "insn_size" "short")])
-
-
-;; Instruction grouping
-
-(define_insn "*small_sequence"
-  [(group_sequence [(match_insn2 0 "small_insn_p")
-		    (match_insn2 1 "small_insn_p")])]
-  ""
-  "*
-{
-  abort ();
-}"
-  [(set_attr "length" "4")
-   (set_attr "type" "multi")])
-
-(define_insn "*small_parallel"
-  [(group_parallel [(match_insn2 0 "small_insn_p")
-		    (match_insn2 1 "small_insn_p")])]
-  "TARGET_M32RX"
-  "*
-{
-  abort ();
-}"
-  [(set_attr "length" "4")
-   (set_attr "type" "multi")])
-
-(define_insn "*long_group"
-  [(group_sequence [(match_insn2 0 "large_insn_p")])]
-  ""
-  "*
-{
-  abort ();
-}"
-  [(set_attr "length" "4")
-   (set_attr "type" "multi")])
-
-
-;; Expand prologue as RTL
-(define_expand "prologue"
-  [(const_int 1)]
-  ""
-  "
-{
-  m32r_expand_prologue ();
-  DONE;
-}")
-
-
-;; Move instructions.
-;;
-;; For QI and HI moves, the register must contain the full properly
-;; sign-extended value.  nonzero_bits assumes this [otherwise
-;; SHORT_IMMEDIATES_SIGN_EXTEND must be used, but the comment for it
-;; says it's a kludge and the .md files should be fixed instead].
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Everything except mem = const or mem = mem can be done easily.
-     Objects in the small data area are handled too.  */
-
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (QImode, operands[1]);
-}")
-
-(define_insn "*movqi_insn"
-  [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,r,T,m")
-	(match_operand:QI 1 "move_src_operand" "r,I,JQR,T,m,r,r"))]
-  "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)"
-  "@
-   mv %0,%1
-   ldi %0,%#%1
-   ldi %0,%#%1
-   ldub %0,%1
-   ldub %0,%1
-   stb %1,%0
-   stb %1,%0"
-  [(set_attr "type" "int2,int2,int4,load2,load4,store2,store4")
-   (set_attr "length" "2,2,4,2,4,2,4")])
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Everything except mem = const or mem = mem can be done easily.  */
-
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (HImode, operands[1]);
-}")
-
-(define_insn "*movhi_insn"
-  [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,r,T,m")
-	(match_operand:HI 1 "move_src_operand" "r,I,JQR,K,T,m,r,r"))]
-  "register_operand (operands[0], HImode) || register_operand (operands[1], HImode)"
-  "@
-   mv %0,%1
-   ldi %0,%#%1
-   ldi %0,%#%1
-   ld24 %0,%#%1
-   lduh %0,%1
-   lduh %0,%1
-   sth %1,%0
-   sth %1,%0"
-  [(set_attr "type" "int2,int2,int4,int4,load2,load4,store2,store4")
-   (set_attr "length" "2,2,4,4,2,4,2,4")])
-
-(define_expand "movsi_push"
-  [(set (mem:SI (pre_dec:SI (match_operand:SI 0 "register_operand" "")))
-	(match_operand:SI 1 "register_operand" ""))]
-  ""
-  "")
-
-(define_expand "movsi_pop"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(mem:SI (post_inc:SI (match_operand:SI 1 "register_operand" ""))))]
-  ""
-  "")
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Everything except mem = const or mem = mem can be done easily.  */
-
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (SImode, operands[1]);
-
-  /* Small Data Area reference?  */
-  if (small_data_operand (operands[1], SImode))
-    {
-      emit_insn (gen_movsi_sda (operands[0], operands[1]));
-      DONE;
-    }
-
-  /* If medium or large code model, symbols have to be loaded with
-     seth/add3.  */
-  if (addr32_operand (operands[1], SImode))
-    {
-      emit_insn (gen_movsi_addr32 (operands[0], operands[1]));
-      DONE;
-    }
-}")
-
-;; ??? Do we need a const_double constraint here for large unsigned values?
-(define_insn "*movsi_insn"
-  [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,r,r,T,S,m")
-	(match_operand:SI 1 "move_src_operand" "r,I,J,MQ,L,n,T,U,m,r,r,r"))]
-  "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
-  "*
-{
-  if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == SUBREG)
-    {
-      switch (GET_CODE (operands[1]))
-	{
-	  HOST_WIDE_INT value;
-
-	  default:
-	    break;
-
-	  case REG:
-	  case SUBREG:
-	    return \"mv %0,%1\";
-
-	  case MEM:
-	    if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
-		&& XEXP (XEXP (operands[1], 0), 0) == stack_pointer_rtx)
-	      return \"pop %0\";
-
-	    return \"ld %0,%1\";
-
-	  case CONST_INT:
-	    value = INTVAL (operands[1]);
-	    if (INT16_P (value))
-	      return \"ldi %0,%#%1\\t; %X1\";
-
-	    if (UINT24_P (value))
-	      return \"ld24 %0,%#%1\\t; %X1\";
-
-	    if (UPPER16_P (value))
-	      return \"seth %0,%#%T1\\t; %X1\";
-
-	    return \"#\";
-
-	  case CONST:
-	  case SYMBOL_REF:
-	  case LABEL_REF:
-	    if (TARGET_ADDR24)
-	      return \"ld24 %0,%#%1\";
-
-	    return \"#\";
-	}
-    }
-
-  else if (GET_CODE (operands[0]) == MEM
-	   && (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG))
-    {
-      if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
-	  && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
-	return \"push %1\";
-
-      return \"st %1,%0\";
-    }
-
-  fatal_insn (\"bad movsi insn\", insn);
-}"
-  [(set_attr "type" "int2,int2,int4,int4,int4,multi,load2,load2,load4,store2,store2,store4")
-   (set_attr "length" "2,2,4,4,4,8,2,2,4,2,2,4")])
-
-; Try to use a four byte / two byte pair for constants not loadable with
-; ldi, ld24, seth.
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
-       (match_operand:SI 1 "two_insn_const_operand" ""))]
-  ""
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 3)))]
-  "
-{
-  unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
-  unsigned HOST_WIDE_INT tmp;
-  int shift;
-
-  /* In all cases we will emit two instructions.  However we try to
-     use 2 byte instructions wherever possible.  We can assume the
-     constant isn't loadable with any of ldi, ld24, or seth.  */
-
-  /* See if we can load a 24 bit unsigned value and invert it.  */
-  if (UINT24_P (~ val))
-    {
-      emit_insn (gen_movsi (operands[0], GEN_INT (~ val)));
-      emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
-      DONE;
-    }
-
-  /* See if we can load a 24 bit unsigned value and shift it into place.
-     0x01fffffe is just beyond ld24's range.  */
-  for (shift = 1, tmp = 0x01fffffe;
-       shift < 8;
-       ++shift, tmp <<= 1)
-    {
-      if ((val & ~tmp) == 0)
-	{
-	  emit_insn (gen_movsi (operands[0], GEN_INT (val >> shift)));
-	  emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (shift)));
-	  DONE;
-	}
-    }
-
-  /* Can't use any two byte insn, fall back to seth/or3.  Use ~0xffff instead
-     of 0xffff0000, since the later fails on a 64-bit host.  */
-  operands[2] = GEN_INT ((val) & ~0xffff);
-  operands[3] = GEN_INT ((val) & 0xffff);
-}")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operand:SI 1 "seth_add3_operand" "i"))]
-  "TARGET_ADDR32"
-  [(set (match_dup 0)
-	(high:SI (match_dup 1)))
-   (set (match_dup 0)
-	(lo_sum:SI (match_dup 0)
-		   (match_dup 1)))]
-  "")
-
-;; Small data area support.
-;; The address of _SDA_BASE_ is loaded into a register and all objects in
-;; the small data area are indexed off that.  This is done for each reference
-;; but cse will clean things up for us.  We let the compiler choose the
-;; register to use so we needn't allocate (and maybe even fix) a special
-;; register to use.  Since the load and store insns have a 16 bit offset the
-;; total size of the data area can be 64K.  However, if the data area lives
-;; above 16M (24 bits), _SDA_BASE_ will have to be loaded with seth/add3 which
-;; would then yield 3 instructions to reference an object [though there would
-;; be no net loss if two or more objects were referenced].  The 3 insns can be
-;; reduced back to 2 if the size of the small data area were reduced to 32K
-;; [then seth + ld/st would work for any object in the area].  Doing this
-;; would require special handling of _SDA_BASE_ (its value would be
-;; (.sdata + 32K) & 0xffff0000) and reloc computations would be different
-;; [I think].  What to do about this is deferred until later and for now we
-;; require .sdata to be in the first 16M.
-
-(define_expand "movsi_sda"
-  [(set (match_dup 2)
-	(unspec [(const_int 0)] 2))
-   (set (match_operand:SI 0 "register_operand" "")
-	(lo_sum:SI (match_dup 2)
-		   (match_operand:SI 1 "small_data_operand" "")))]
-  ""
-  "
-{
-  if (reload_in_progress || reload_completed)
-    operands[2] = operands[0];
-  else
-    operands[2] = gen_reg_rtx (SImode);
-}")
-
-(define_insn "*load_sda_base"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(unspec [(const_int 0)] 2))]
-  ""
-  "ld24 %0,#_SDA_BASE_"
-  [(set_attr "type" "int4")
-   (set_attr "length" "4")])
-
-;; 32 bit address support.
-
-(define_expand "movsi_addr32"
-  [(set (match_dup 2)
-	; addr32_operand isn't used because it's too restrictive,
-	; seth_add3_operand is more general and thus safer.
-	(high:SI (match_operand:SI 1 "seth_add3_operand" "")))
-   (set (match_operand:SI 0 "register_operand" "")
-	(lo_sum:SI (match_dup 2) (match_dup 1)))]
-  ""
-  "
-{
-  if (reload_in_progress || reload_completed)
-    operands[2] = operands[0];
-  else
-    operands[2] = gen_reg_rtx (SImode);
-}")
-
-(define_insn "set_hi_si"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(high:SI (match_operand 1 "symbolic_operand" "")))]
-  ""
-  "seth %0,%#shigh(%1)"
-  [(set_attr "type" "int4")
-   (set_attr "length" "4")])
-
-(define_insn "lo_sum_si"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-		   (match_operand:SI 2 "immediate_operand" "in")))]
-  ""
-  "add3 %0,%1,%#%B2"
-  [(set_attr "type" "int4")
-   (set_attr "length" "4")])
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Everything except mem = const or mem = mem can be done easily.  */
-
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (DImode, operands[1]);
-}")
-
-(define_insn "*movdi_insn"
-  [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,r,m")
-	(match_operand:DI 1 "move_double_src_operand" "r,nG,F,m,r"))]
-  "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
-  "#"
-  [(set_attr "type" "multi,multi,multi,load8,store8")
-   (set_attr "length" "4,4,16,6,6")])
-
-(define_split
-  [(set (match_operand:DI 0 "move_dest_operand" "")
-	(match_operand:DI 1 "move_double_src_operand" ""))]
-  "reload_completed"
-  [(match_dup 2)]
-  "operands[2] = gen_split_move_double (operands);")
-
-;; Floating point move insns.
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Everything except mem = const or mem = mem can be done easily.  */
-
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (SFmode, operands[1]);
-}")
-
-(define_insn "*movsf_insn"
-  [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,r,r,T,S,m")
-	(match_operand:SF 1 "move_src_operand" "r,F,U,S,m,r,r,r"))]
-  "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)"
-  "@
-   mv %0,%1
-   #
-   ld %0,%1
-   ld %0,%1
-   ld %0,%1
-   st %1,%0
-   st %1,%0
-   st %1,%0"
-  ;; ??? Length of alternative 1 is either 2, 4 or 8.
-  [(set_attr "type" "int2,multi,load2,load2,load4,store2,store2,store4")
-   (set_attr "length" "2,8,2,2,4,2,2,4")])
-
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "")
-	(match_operand:SF 1 "const_double_operand" ""))]
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 3))]
-  "
-{
-  long l;
-  REAL_VALUE_TYPE rv;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-  REAL_VALUE_TO_TARGET_SINGLE (rv, l);
-
-  operands[2] = operand_subword (operands[0], 0, 0, SFmode);
-  operands[3] = GEN_INT (l);
-}")
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Everything except mem = const or mem = mem can be done easily.  */
-
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (DFmode, operands[1]);
-}")
-
-(define_insn "*movdf_insn"
-  [(set (match_operand:DF 0 "move_dest_operand" "=r,r,r,m")
-	(match_operand:DF 1 "move_double_src_operand" "r,F,m,r"))]
-  "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)"
-  "#"
-  [(set_attr "type" "multi,multi,load8,store8")
-   (set_attr "length" "4,16,6,6")])
-
-(define_split
-  [(set (match_operand:DF 0 "move_dest_operand" "")
-	(match_operand:DF 1 "move_double_src_operand" ""))]
-  "reload_completed"
-  [(match_dup 2)]
-  "operands[2] = gen_split_move_double (operands);")
-
-;; Zero extension instructions.
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
-	(zero_extend:HI (match_operand:QI 1 "extend_operand" "r,T,m")))]
-  ""
-  "@
-   and3 %0,%1,%#255
-   ldub %0,%1
-   ldub %0,%1"
-  [(set_attr "type" "int4,load2,load4")
-   (set_attr "length" "4,2,4")])
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(zero_extend:SI (match_operand:QI 1 "extend_operand" "r,T,m")))]
-  ""
-  "@
-   and3 %0,%1,%#255
-   ldub %0,%1
-   ldub %0,%1"
-  [(set_attr "type" "int4,load2,load4")
-   (set_attr "length" "4,2,4")])
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(zero_extend:SI (match_operand:HI 1 "extend_operand" "r,T,m")))]
-  ""
-  "@
-   and3 %0,%1,%#65535
-   lduh %0,%1
-   lduh %0,%1"
-  [(set_attr "type" "int4,load2,load4")
-   (set_attr "length" "4,2,4")])
-
-;; Signed conversions from a smaller integer to a larger integer
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
-	(sign_extend:HI (match_operand:QI 1 "extend_operand" "0,T,m")))]
-  ""
-  "@
-    #
-    ldb %0,%1
-    ldb %0,%1"
-  [(set_attr "type" "multi,load2,load4")
-   (set_attr "length" "2,2,4")])
-
-(define_split
-  [(set (match_operand:HI 0 "register_operand" "")
-	(sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
-  "reload_completed"
-  [(match_dup 2)
-   (match_dup 3)]
-  "
-{
-  rtx op0   = gen_lowpart (SImode, operands[0]);
-  rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
-
-  operands[2] = gen_ashlsi3 (op0, op0, shift);
-  operands[3] = gen_ashrsi3 (op0, op0, shift);
-}")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(sign_extend:SI (match_operand:QI 1 "extend_operand" "0,T,m")))]
-  ""
-  "@
-    #
-    ldb %0,%1
-    ldb %0,%1"
-  [(set_attr "type" "multi,load2,load4")
-   (set_attr "length" "4,2,4")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
-  "reload_completed"
-  [(match_dup 2)
-   (match_dup 3)]
-  "
-{
-  rtx op0   = gen_lowpart (SImode, operands[0]);
-  rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
-
-  operands[2] = gen_ashlsi3 (op0, op0, shift);
-  operands[3] = gen_ashrsi3 (op0, op0, shift);
-}")
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(sign_extend:SI (match_operand:HI 1 "extend_operand" "0,T,m")))]
-  ""
-  "@
-    #
-    ldh %0,%1
-    ldh %0,%1"
-  [(set_attr "type" "multi,load2,load4")
-   (set_attr "length" "4,2,4")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
-  "reload_completed"
-  [(match_dup 2)
-   (match_dup 3)]
-  "
-{
-  rtx op0   = gen_lowpart (SImode, operands[0]);
-  rtx shift = gen_rtx (CONST_INT, VOIDmode, 16);
-
-  operands[2] = gen_ashlsi3 (op0, op0, shift);
-  operands[3] = gen_ashrsi3 (op0, op0, shift);
-}")
-
-;; Arithmetic instructions.
-
-; ??? Adding an alternative to split add3 of small constants into two
-; insns yields better instruction packing but slower code.  Adds of small
-; values is done a lot.
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
-		 (match_operand:SI 2 "nonmemory_operand" "r,I,J")))]
-  ""
-  "@
-   add %0,%2
-   addi %0,%#%2
-   add3 %0,%1,%#%2"
-  [(set_attr "type" "int2,int2,int4")
-   (set_attr "length" "2,2,4")])
-
-;(define_split
-;  [(set (match_operand:SI 0 "register_operand" "")
-;	(plus:SI (match_operand:SI 1 "register_operand" "")
-;		 (match_operand:SI 2 "int8_operand" "")))]
-;  "reload_completed
-;   && REGNO (operands[0]) != REGNO (operands[1])
-;   && INT8_P (INTVAL (operands[2]))
-;   && INTVAL (operands[2]) != 0"
-;  [(set (match_dup 0) (match_dup 1))
-;   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
-;  "")
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_operand:DI 1 "register_operand" "%0")
-		 (match_operand:DI 2 "register_operand" "r")))
-   (clobber (reg:SI 17))]
-  ""
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "6")])
-
-;; ??? The cmp clears the condition bit.  Can we speed up somehow?
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(plus:DI (match_operand:DI 1 "register_operand" "")
-		 (match_operand:DI 2 "register_operand" "")))
-   (clobber (match_operand 3 "" ""))]
-  "reload_completed"
-  [(parallel [(set (match_dup 3)
-		   (const_int 0))
-	      (use (match_dup 4))])
-   (parallel [(set (match_dup 4)
-		   (plus:SI (match_dup 4)
-			    (plus:SI (match_dup 5)
-				     (match_dup 3))))
-	      (set (match_dup 3)
-		   (unspec [(const_int 0)] 3))])
-   (parallel [(set (match_dup 6)
-		   (plus:SI (match_dup 6)
-			    (plus:SI (match_dup 7)
-				     (match_dup 3))))
-	      (set (match_dup 3)
-		   (unspec [(const_int 0)] 3))])]
-  "
-{
-  operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
-  operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);
-  operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);
-  operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);
-}")
-
-(define_insn "*clear_c"
-  [(set (reg:SI 17)
-	(const_int 0))
-   (use (match_operand:SI 0 "register_operand" "r"))]
-  ""
-  "cmp %0,%0"
-  [(set_attr "type" "int2")
-   (set_attr "length" "2")])
-
-(define_insn "*add_carry"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0")
-		 (plus:SI (match_operand:SI 2 "register_operand" "r")
-			  (reg:SI 17))))
-   (set (reg:SI 17)
-	(unspec [(const_int 0)] 3))]
-  ""
-  "addx %0,%2"
-  [(set_attr "type" "int2")
-   (set_attr "length" "2")])
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "0")
-		  (match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "sub %0,%2"
-  [(set_attr "type" "int2")
-   (set_attr "length" "2")])
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "register_operand" "0")
-		  (match_operand:DI 2 "register_operand" "r")))
-   (clobber (reg:SI 17))]
-  ""
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "6")])
-
-;; ??? The cmp clears the condition bit.  Can we speed up somehow?
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(minus:DI (match_operand:DI 1 "register_operand" "")
-		  (match_operand:DI 2 "register_operand" "")))
-   (clobber (match_operand 3 "" ""))]
-  "reload_completed"
-  [(parallel [(set (match_dup 3)
-		   (const_int 0))
-	      (use (match_dup 4))])
-   (parallel [(set (match_dup 4)
-		   (minus:SI (match_dup 4)
-			     (minus:SI (match_dup 5)
-				       (match_dup 3))))
-	      (set (match_dup 3)
-		   (unspec [(const_int 0)] 3))])
-   (parallel [(set (match_dup 6)
-		   (minus:SI (match_dup 6)
-			     (minus:SI (match_dup 7)
-				       (match_dup 3))))
-	      (set (match_dup 3)
-		   (unspec [(const_int 0)] 3))])]
-  "
-{
-  operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
-  operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);
-  operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);
-  operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);
-}")
-
-(define_insn "*sub_carry"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "%0")
-		  (minus:SI (match_operand:SI 2 "register_operand" "r")
-			    (reg:SI 17))))
-   (set (reg:SI 17)
-	(unspec [(const_int 0)] 3))]
-  ""
-  "subx %0,%2"
-  [(set_attr "type" "int2")
-   (set_attr "length" "2")])
-
-; Multiply/Divide instructions.
-
-(define_insn "mulhisi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "r"))
-		 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
-  ""
-  "mullo %1,%2\;mvfacmi %0"
-  [(set_attr "type" "multi")
-   (set_attr "length" "4")])
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (match_operand:SI 1 "register_operand" "%0")
-		 (match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "mul %0,%2"
-  [(set_attr "type" "mul2")
-   (set_attr "length" "2")])
-
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(div:SI (match_operand:SI 1 "register_operand" "0")
-		(match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "div %0,%2"
-  [(set_attr "type" "div4")
-   (set_attr "length" "4")])
-
-(define_insn "udivsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(udiv:SI (match_operand:SI 1 "register_operand" "0")
-		 (match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "divu %0,%2"
-  [(set_attr "type" "div4")
-   (set_attr "length" "4")])
-
-(define_insn "modsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mod:SI (match_operand:SI 1 "register_operand" "0")
-		(match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "rem %0,%2"
-  [(set_attr "type" "div4")
-   (set_attr "length" "4")])
-
-(define_insn "umodsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(umod:SI (match_operand:SI 1 "register_operand" "0")
-		 (match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "remu %0,%2"
-  [(set_attr "type" "div4")
-   (set_attr "length" "4")])
-
-;; Boolean instructions.
-;;
-;; We don't define the DImode versions as expand_binop does a good enough job.
-;; And if it doesn't it should be fixed.
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(and:SI (match_operand:SI 1 "register_operand" "%0,r")
-		(match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
-  ""
-  "*
-{
-  /* If we are worried about space, see if we can break this up into two
-     short instructions, which might eliminate a NOP being inserted.  */
-  if (optimize_size
-      && m32r_not_same_reg (operands[0], operands[1])
-      && GET_CODE (operands[2]) == CONST_INT
-      && INT8_P (INTVAL (operands[2])))
-    return \"#\";
-
-  else if (GET_CODE (operands[2]) == CONST_INT)
-    return \"and3 %0,%1,%#%X2\";
-
-  return \"and %0,%2\";
-}"
-  [(set_attr "type" "int2,int4")
-   (set_attr "length" "2,4")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(and:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "int8_operand" "")))]
-  "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (and:SI (match_dup 1) (match_dup 0)))]
-  "")
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ior:SI (match_operand:SI 1 "register_operand" "%0,r")
-		(match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
-  ""
-  "*
-{
-  /* If we are worried about space, see if we can break this up into two
-     short instructions, which might eliminate a NOP being inserted.  */
-  if (optimize_size
-      && m32r_not_same_reg (operands[0], operands[1])
-      && GET_CODE (operands[2]) == CONST_INT
-      && INT8_P (INTVAL (operands[2])))
-    return \"#\";
-
-  else if (GET_CODE (operands[2]) == CONST_INT)
-    return \"or3 %0,%1,%#%X2\";
-
-  return \"or %0,%2\";
-}"
-  [(set_attr "type" "int2,int4")
-   (set_attr "length" "2,4")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ior:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "int8_operand" "")))]
-  "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 0)))]
-  "")
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(xor:SI (match_operand:SI 1 "register_operand" "%0,r")
-		(match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
-  ""
-  "*
-{
-  /* If we are worried about space, see if we can break this up into two
-     short instructions, which might eliminate a NOP being inserted.  */
-  if (optimize_size
-      && m32r_not_same_reg (operands[0], operands[1])
-      && GET_CODE (operands[2]) == CONST_INT
-      && INT8_P (INTVAL (operands[2])))
-    return \"#\";
-
-  else if (GET_CODE (operands[2]) == CONST_INT)
-    return \"xor3 %0,%1,%#%X2\";
-
-  return \"xor %0,%2\";
-}"
-  [(set_attr "type" "int2,int4")
-   (set_attr "length" "2,4")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(xor:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "int8_operand" "")))]
-  "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (xor:SI (match_dup 1) (match_dup 0)))]
-  "")
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "neg %0,%1"
-  [(set_attr "type" "int2")
-   (set_attr "length" "2")])
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "not %0,%1"
-  [(set_attr "type" "int2")
-   (set_attr "length" "2")])
-
-;; Shift instructions.
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
-		   (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
-  ""
-  "@
-   sll %0,%2
-   slli %0,%#%2
-   sll3 %0,%1,%#%2"
-  [(set_attr "type" "shift2,shift2,shift4")
-   (set_attr "length" "2,2,4")])
-
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
-		     (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
-  ""
-  "@
-   sra %0,%2
-   srai %0,%#%2
-   sra3 %0,%1,%#%2"
-  [(set_attr "type" "shift2,shift2,shift4")
-   (set_attr "length" "2,2,4")])
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
-		     (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
-  ""
-  "@
-   srl %0,%2
-   srli %0,%#%2
-   srl3 %0,%1,%#%2"
-  [(set_attr "type" "shift2,shift2,shift4")
-   (set_attr "length" "2,2,4")])
-
-;; Compare instructions.
-;; This controls RTL generation and register allocation.
-
-;; We generate RTL for comparisons and branches by having the cmpxx 
-;; patterns store away the operands.  Then the bcc patterns
-;; emit RTL for both the compare and the branch.
-;;
-;; On the m32r it is more efficient to use the bxxz instructions and
-;; thus merge the compare and branch into one instruction, so they are
-;; preferred.
-
-(define_expand "cmpsi"
-  [(set (reg:SI 17)
-	(compare:CC (match_operand:SI 0 "register_operand" "")
-		    (match_operand:SI 1 "reg_or_cmp_int16_operand" "")))]
-  ""
-  "
-{
-  m32r_compare_op0 = operands[0];
-  m32r_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_insn "cmp_eqsi_zero_insn"
-  [(set (reg:SI 17)
-	(eq:SI (match_operand:SI 0 "register_operand" "r,r")
-	       (match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
-  "TARGET_M32RX"
-  "@
-   cmpeq %0, %1
-   cmpz  %0"
-  [(set_attr "type" "int4")
-   (set_attr "length" "4")])
-
-;; The cmp_xxx_insn patterns set the condition bit to the result of the
-;; comparison.  There isn't a "compare equal" instruction so cmp_eqsi_insn
-;; is quite inefficient.  However, it is rarely used.
-
-(define_expand "cmp_eqsi_insn"
-  [(parallel [(set (reg:SI 17)
-		   (eq:SI (match_operand:SI 0 "register_operand" "")
-			  (match_operand:SI 1 "reg_or_uint16_operand" "")))
-	      (clobber (match_dup 2))])]
-  ""
-  "operands[2] = gen_reg_rtx (SImode);")
-
-(define_insn "*cmp_eqsi_insn_internal"
-  [(set (reg:SI 17)
-	(eq:SI (match_operand:SI 0 "register_operand" "r,r")
-	       (match_operand:SI 1 "reg_or_uint16_operand" "r,K")))
-   (clobber (match_operand:SI 2 "register_operand" "=0,r"))]
-  "reload_completed"
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "6,8")])
-
-(define_split
-  [(set (reg:SI 17)
-	(eq:SI (match_operand:SI 0 "register_operand" "")
-	       (match_operand:SI 1 "reg_or_uint16_operand" "")))
-   (clobber (match_operand:SI 2 "register_operand" ""))]
-  ""
-  [(set (match_dup 2)
-	(xor:SI (match_dup 0)
-		(match_dup 1)))
-   (set (reg:SI 17)
-	(ltu:SI (match_dup 2)
-		(const_int 1)))]
-  "")
-
-(define_insn "cmp_ltsi_insn"
-  [(set (reg:SI 17)
-	(lt:SI (match_operand:SI 0 "register_operand" "r,r")
-	       (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
-  ""
-  "@
-   cmp %0,%1
-   cmpi %0,%#%1"
-  [(set_attr "type" "int2,int4")
-   (set_attr "length" "2,4")])
-
-(define_insn "cmp_ltusi_insn"
-  [(set (reg:SI 17)
-	(ltu:SI (match_operand:SI 0 "register_operand" "r,r")
-	        (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
-  ""
-  "@
-   cmpu %0,%1
-   cmpui %0,%#%1"
-  [(set_attr "type" "int2,int4")
-   (set_attr "length" "2,4")])
-
-
-;; These control RTL generation for conditional jump insns.
-
-(define_expand "beq"
-  [(match_operand 0 "" "")]
-  ""
-  "
-{
-  emit_insn (gen_compare ((int)EQ, operands[0], m32r_compare_op0,
-			  m32r_compare_op1));
-  DONE;
-}")
-
-(define_expand "bne"
-  [(match_operand 0 "" "")]
-  ""
-  "
-{
-  emit_insn (gen_compare ((int)NE, operands[0], m32r_compare_op0,
-			  m32r_compare_op1));
-  DONE;
-}")
-
-(define_expand "blt"
-  [(match_operand 0 "" "")]
-  ""
-  "
-{
-  emit_insn (gen_compare ((int)LT, operands[0], m32r_compare_op0,
-			  m32r_compare_op1));
-  DONE;
-}")
-
-(define_expand "ble"
-  [(match_operand 0 "" "")]
-  ""
-  "
-{
-  emit_insn (gen_compare ((int)LE, operands[0], m32r_compare_op0,
-			  m32r_compare_op1));
-  DONE;
-}")
-
-(define_expand "bgt"
-  [(match_operand 0 "" "")]
-  ""
-  "
-{
-  emit_insn (gen_compare ((int)GT, operands[0], m32r_compare_op0,
-			  m32r_compare_op1));
-  DONE;
-}")
-
-(define_expand "bge"
-  [(match_operand 0 "" "")]
-  ""
-  "
-{
-  emit_insn (gen_compare ((int)GE, operands[0], m32r_compare_op0,
-			  m32r_compare_op1));
-  DONE;
-}")
-
-(define_expand "bltu"
-  [(match_operand 0 "" "")]
-  ""
-  "
-{
-  emit_insn (gen_compare ((int)LTU, operands[0], m32r_compare_op0,
-			  m32r_compare_op1));
-  DONE;
-}")
-
-(define_expand "bleu"
-  [(match_operand 0 "" "")]
-  ""
-  "
-{
-  emit_insn (gen_compare ((int)LEU, operands[0], m32r_compare_op0,
-			  m32r_compare_op1));
-  DONE;
-}")
-
-(define_expand "bgtu"
-  [(match_operand 0 "" "")]
-  ""
-  "
-{
-  emit_insn (gen_compare ((int)GTU, operands[0], m32r_compare_op0,
-			  m32r_compare_op1));
-  DONE;
-}")
-
-(define_expand "bgeu"
-  [(match_operand 0 "" "")]
-  ""
-  "
-{
-  emit_insn (gen_compare ((int)GEU, operands[0], m32r_compare_op0,
-			  m32r_compare_op1));
-  DONE;
-}")
-
-;; Now match both normal and inverted jump.
-
-(define_insn "*branch_insn"
-  [(set (pc)
-	(if_then_else (match_operator 1 "eqne_comparison_operator"
-				      [(reg 17) (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  static char instruction[40];
-  sprintf (instruction, \"%s%s %%l0\",
-	   (GET_CODE (operands[1]) == NE) ? \"bc\" : \"bnc\",
-	   (get_attr_length (insn) == 2) ? \".s\" : \"\");
-  return instruction;
-}"
-  [(set_attr "type" "branch")
-   ; We use 400/800 instead of 512,1024 to account for inaccurate insn
-   ; lengths and insn alignments that are complex to track.
-   ; It's not important that we be hyper-precise here.  It may be more
-   ; important blah blah blah when the chip supports parallel execution
-   ; blah blah blah but until then blah blah blah this is simple and
-   ; suffices.
-   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
-						 (const_int 400))
-					   (const_int 800))
-				      (const_int 2)
-				      (const_int 4)))])
-
-(define_insn "*rev_branch_insn"
-  [(set (pc)
-	(if_then_else (match_operator 1 "eqne_comparison_operator"
-				      [(reg 17) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ;"REVERSIBLE_CC_MODE (GET_MODE (XEXP (operands[1], 0)))"
-  ""
-  "*
-{
-  static char instruction[40];
-  sprintf (instruction, \"%s%s %%l0\",
-	   (GET_CODE (operands[1]) == EQ) ? \"bc\" : \"bnc\",
-	   (get_attr_length (insn) == 2) ? \".s\" : \"\");
-  return instruction;
-}"
-  [(set_attr "type" "branch")
-   ; We use 400/800 instead of 512,1024 to account for inaccurate insn
-   ; lengths and insn alignments that are complex to track.
-   ; It's not important that we be hyper-precise here.  It may be more
-   ; important blah blah blah when the chip supports parallel execution
-   ; blah blah blah but until then blah blah blah this is simple and
-   ; suffices.
-   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
-						 (const_int 400))
-					   (const_int 800))
-				      (const_int 2)
-				      (const_int 4)))])
-
-; reg/reg compare and branch insns
-
-(define_insn "*reg_branch_insn"
-  [(set (pc)
-	(if_then_else (match_operator 1 "eqne_comparison_operator"
-				      [(match_operand:SI 2 "register_operand" "r")
-				       (match_operand:SI 3 "register_operand" "r")])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  /* Is branch target reachable with beq/bne?  */
-  if (get_attr_length (insn) == 4)
-    {
-      if (GET_CODE (operands[1]) == EQ)
-	return \"beq %2,%3,%l0\";
-      else
-	return \"bne %2,%3,%l0\";
-    }
-  else
-    {
-      if (GET_CODE (operands[1]) == EQ)
-	return \"bne %2,%3,1f\;bra %l0\;1:\";
-      else
-	return \"beq %2,%3,1f\;bra %l0\;1:\";
-    }
-}"
-  [(set_attr "type" "branch")
-  ; We use 25000/50000 instead of 32768/65536 to account for slot filling
-  ; which is complex to track and inaccurate length specs.
-   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
-						 (const_int 25000))
-					   (const_int 50000))
-				      (const_int 4)
-				      (const_int 8)))])
-
-(define_insn "*rev_reg_branch_insn"
-  [(set (pc)
-	(if_then_else (match_operator 1 "eqne_comparison_operator"
-				      [(match_operand:SI 2 "register_operand" "r")
-				       (match_operand:SI 3 "register_operand" "r")])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  /* Is branch target reachable with beq/bne?  */
-  if (get_attr_length (insn) == 4)
-    {
-      if (GET_CODE (operands[1]) == NE)
-	return \"beq %2,%3,%l0\";
-      else
-	return \"bne %2,%3,%l0\";
-    }
-  else
-    {
-      if (GET_CODE (operands[1]) == NE)
-	return \"bne %2,%3,1f\;bra %l0\;1:\";
-      else
-	return \"beq %2,%3,1f\;bra %l0\;1:\";
-    }
-}"
-  [(set_attr "type" "branch")
-  ; We use 25000/50000 instead of 32768/65536 to account for slot filling
-  ; which is complex to track and inaccurate length specs.
-   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
-						 (const_int 25000))
-					   (const_int 50000))
-				      (const_int 4)
-				      (const_int 8)))])
-
-; reg/zero compare and branch insns
-
-(define_insn "*zero_branch_insn"
-  [(set (pc)
-	(if_then_else (match_operator 1 "signed_comparison_operator"
-				      [(match_operand:SI 2 "register_operand" "r")
-				       (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  char *br,*invbr;
-  char asmtext[40];
-
-  switch (GET_CODE (operands[1]))
-    {
-      case EQ : br = \"eq\"; invbr = \"ne\"; break;
-      case NE : br = \"ne\"; invbr = \"eq\"; break;
-      case LE : br = \"le\"; invbr = \"gt\"; break;
-      case GT : br = \"gt\"; invbr = \"le\"; break;
-      case LT : br = \"lt\"; invbr = \"ge\"; break;
-      case GE : br = \"ge\"; invbr = \"lt\"; break;
-    }
-
-  /* Is branch target reachable with bxxz?  */
-  if (get_attr_length (insn) == 4)
-    {
-      sprintf (asmtext, \"b%sz %%2,%%l0\", br);
-      output_asm_insn (asmtext, operands);
-    }
-  else
-    {
-      sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", invbr);
-      output_asm_insn (asmtext, operands);
-    }
-  return \"\";
-}"
-  [(set_attr "type" "branch")
-  ; We use 25000/50000 instead of 32768/65536 to account for slot filling
-  ; which is complex to track and inaccurate length specs.
-   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
-						 (const_int 25000))
-					   (const_int 50000))
-				      (const_int 4)
-				      (const_int 8)))])
-
-(define_insn "*rev_zero_branch_insn"
-  [(set (pc)
-	(if_then_else (match_operator 1 "eqne_comparison_operator"
-				      [(match_operand:SI 2 "register_operand" "r")
-				       (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  char *br,*invbr;
-  char asmtext[40];
-
-  switch (GET_CODE (operands[1]))
-    {
-      case EQ : br = \"eq\"; invbr = \"ne\"; break;
-      case NE : br = \"ne\"; invbr = \"eq\"; break;
-      case LE : br = \"le\"; invbr = \"gt\"; break;
-      case GT : br = \"gt\"; invbr = \"le\"; break;
-      case LT : br = \"lt\"; invbr = \"ge\"; break;
-      case GE : br = \"ge\"; invbr = \"lt\"; break;
-    }
-
-  /* Is branch target reachable with bxxz?  */
-  if (get_attr_length (insn) == 4)
-    {
-      sprintf (asmtext, \"b%sz %%2,%%l0\", invbr);
-      output_asm_insn (asmtext, operands);
-    }
-  else
-    {
-      sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", br);
-      output_asm_insn (asmtext, operands);
-    }
-  return \"\";
-}"
-  [(set_attr "type" "branch")
-  ; We use 25000/50000 instead of 32768/65536 to account for slot filling
-  ; which is complex to track and inaccurate length specs.
-   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
-						 (const_int 25000))
-					   (const_int 50000))
-				      (const_int 4)
-				      (const_int 8)))])
-
-;; S<cc> operations to set a register to 1/0 based on a comparison
-
-(define_expand "seq"
-  [(match_operand:SI 0 "register_operand" "")]
-  ""
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = m32r_compare_op0;
-  rtx op2 = m32r_compare_op1;
-  enum machine_mode mode = GET_MODE (op0);
-
-  if (mode != SImode)
-    FAIL;
-
-  if (! register_operand (op1, mode))
-    op1 = force_reg (mode, op1);
-
-  if (TARGET_M32RX)
-    {
-      if (! reg_or_zero_operand (op2, mode))
-	op2 = force_reg (mode, op2);
-
-      emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
-      DONE;
-    }
-
-  if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0)
-    {
-      emit_insn (gen_seq_zero_insn (op0, op1));
-      DONE;
-    }
-
-  if (! reg_or_eq_int16_operand (op2, mode))
-    op2 = force_reg (mode, op2);
-
-  emit_insn (gen_seq_insn (op0, op1, op2));
-  DONE;
-}")
-
-(define_insn "seq_insn_m32rx"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (match_operand:SI 1 "register_operand" "%r")
-	       (match_operand:SI 2 "reg_or_zero_operand" "rP")))
-   (clobber (reg:SI 17))]
-  "TARGET_M32RX"
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "6")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(eq:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "reg_or_zero_operand" "")))
-   (clobber (reg:SI 17))]
-  "TARGET_M32RX"
-  [(set (reg:SI 17)
-	(eq:SI (match_dup 1)
-	       (match_dup 2)))
-   (set (match_dup 0)
-	(reg:SI 17))]
-  "")
-
-(define_insn "seq_zero_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (match_operand:SI 1 "register_operand" "r")
-	       (const_int 0)))
-   (clobber (reg:SI 17))]
-  "TARGET_M32R"
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "6")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(eq:SI (match_operand:SI 1 "register_operand" "")
-	       (const_int 0)))
-   (clobber (reg:SI 17))]
-  "TARGET_M32R"
-  [(match_dup 3)]
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-
-  start_sequence ();
-  emit_insn (gen_cmp_ltusi_insn (op1, GEN_INT (1)));
-  emit_insn (gen_movcc_insn (op0));
-  operands[3] = gen_sequence ();
-  end_sequence ();
-}")
-
-(define_insn "seq_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
-	(eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
-	       (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
-   (clobber (reg:SI 17))
-   (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
-  "TARGET_M32R"
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8,8,10,10")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(eq:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
-   (clobber (reg:SI 17))
-   (clobber (match_scratch:SI 3 ""))]
-  "TARGET_M32R && reload_completed"
-  [(match_dup 4)]
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-  rtx op2 = operands[2];
-  rtx op3 = operands[3];
-  HOST_WIDE_INT value;
-
-  if (GET_CODE (op2) == REG && GET_CODE (op3) == REG
-      && REGNO (op2) == REGNO (op3))
-    {
-      op1 = operands[2];
-      op2 = operands[1];
-    }
-
-  start_sequence ();
-  if (GET_CODE (op1) == REG && GET_CODE (op3) == REG
-      && REGNO (op1) != REGNO (op3))
-    {
-      emit_move_insn (op3, op1);
-      op1 = op3;
-    }
-
-  if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
-      && CMP_INT16_P (value))
-    emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
-  else
-    emit_insn (gen_xorsi3 (op3, op1, op2));
-
-  emit_insn (gen_cmp_ltusi_insn (op3, GEN_INT (1)));
-  emit_insn (gen_movcc_insn (op0));
-  operands[4] = gen_sequence ();
-  end_sequence ();
-}")
-
-(define_expand "sne"
-  [(match_operand:SI 0 "register_operand" "")]
-  ""
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = m32r_compare_op0;
-  rtx op2 = m32r_compare_op1;
-  enum machine_mode mode = GET_MODE (op0);
-
-  if (mode != SImode)
-    FAIL;
-
-  if (GET_CODE (op2) != CONST_INT
-      || (INTVAL (op2) != 0 && UINT16_P (INTVAL (op2))))
-    {
-      rtx reg;
-
-      if (reload_completed || reload_in_progress)
-	FAIL;
-
-      reg = gen_reg_rtx (SImode);
-      emit_insn (gen_xorsi3 (reg, op1, op2));
-      op1 = reg;
-
-      if (! register_operand (op1, mode))
-        op1 = force_reg (mode, op1);
-
-      emit_insn (gen_sne_zero_insn (op0, op1));
-      DONE;
-    }
-  else
-    FAIL;
-}")
-
-(define_insn "sne_zero_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ne:SI (match_operand:SI 1 "register_operand" "r")
-	       (const_int 0)))
-   (clobber (reg:SI 17))
-   (clobber (match_scratch:SI 2 "=&r"))]
-  ""
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "6")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ne:SI (match_operand:SI 1 "register_operand" "")
-	       (const_int 0)))
-   (clobber (reg:SI 17))
-   (clobber (match_scratch:SI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 2)
-	(const_int 0))
-   (set (reg:SI 17)
-	(ltu:SI (match_dup 2)
-		(match_dup 1)))
-   (set (match_dup 0)
-	(reg:SI 17))]
-  "")
-	
-(define_expand "slt"
-  [(match_operand:SI 0 "register_operand" "")]
-  ""
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = m32r_compare_op0;
-  rtx op2 = m32r_compare_op1;
-  enum machine_mode mode = GET_MODE (op0);
-
-  if (mode != SImode)
-    FAIL;
-
-  if (! register_operand (op1, mode))
-    op1 = force_reg (mode, op1);
-
-  if (! reg_or_int16_operand (op2, mode))
-    op2 = force_reg (mode, op2);
-
-  emit_insn (gen_slt_insn (op0, op1, op2));
-  DONE;
-}")
-
-(define_insn "slt_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(lt:SI (match_operand:SI 1 "register_operand" "r,r")
-	       (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
-   (clobber (reg:SI 17))]
-  ""
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "4,6")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lt:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "reg_or_int16_operand" "")))
-   (clobber (reg:SI 17))]
-  ""
-  [(set (reg:SI 17)
-	(lt:SI (match_dup 1)
-	       (match_dup 2)))
-   (set (match_dup 0)
-	(reg:SI 17))]
-  "")
-
-(define_expand "sle"
-  [(match_operand:SI 0 "register_operand" "")]
-  ""
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = m32r_compare_op0;
-  rtx op2 = m32r_compare_op1;
-  enum machine_mode mode = GET_MODE (op0);
-
-  if (mode != SImode)
-    FAIL;
-
-  if (! register_operand (op1, mode))
-    op1 = force_reg (mode, op1);
-
-  if (GET_CODE (op2) == CONST_INT)
-    {
-      HOST_WIDE_INT value = INTVAL (op2);
-      if (value >= 2147483647)
-	{
-	  emit_move_insn (op0, GEN_INT (1));
-	  DONE;
-	}
-
-      op2 = GEN_INT (value+1);
-      if (value < -32768 || value >= 32767)
-	op2 = force_reg (mode, op2);
-
-      emit_insn (gen_slt_insn (op0, op1, op2));
-      DONE;
-    }
-
-  if (! register_operand (op2, mode))
-    op2 = force_reg (mode, op2);
-
-  emit_insn (gen_sle_insn (op0, op1, op2));
-  DONE;
-}")
-
-(define_insn "sle_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(le:SI (match_operand:SI 1 "register_operand" "r")
-	       (match_operand:SI 2 "register_operand" "r")))
-   (clobber (reg:SI 17))]
-  ""
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(le:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "register_operand" "")))
-   (clobber (reg:SI 17))]
-  "!optimize_size"
-  [(set (reg:SI 17)
-	(lt:SI (match_dup 2)
-	       (match_dup 1)))
-   (set (match_dup 0)
-	(reg:SI 17))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
-;; xor reg,reg,1 which might eliminate a NOP being inserted.
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(le:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "register_operand" "")))
-   (clobber (reg:SI 17))]
-  "optimize_size"
-  [(set (reg:SI 17)
-	(lt:SI (match_dup 2)
-	       (match_dup 1)))
-   (set (match_dup 0)
-	(reg:SI 17))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))
-   (set (match_dup 0)
-	(neg:SI (match_dup 0)))]
-  "")
-
-(define_expand "sgt"
-  [(match_operand:SI 0 "register_operand" "")]
-  ""
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = m32r_compare_op0;
-  rtx op2 = m32r_compare_op1;
-  enum machine_mode mode = GET_MODE (op0);
-
-  if (mode != SImode)
-    FAIL;
-
-  if (! register_operand (op1, mode))
-    op1 = force_reg (mode, op1);
-
-  if (! register_operand (op2, mode))
-    op2 = force_reg (mode, op2);
-
-  emit_insn (gen_slt_insn (op0, op2, op1));
-  DONE;
-}")
-
-(define_expand "sge"
-  [(match_operand:SI 0 "register_operand" "")]
-  ""
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = m32r_compare_op0;
-  rtx op2 = m32r_compare_op1;
-  enum machine_mode mode = GET_MODE (op0);
-
-  if (mode != SImode)
-    FAIL;
-
-  if (! register_operand (op1, mode))
-    op1 = force_reg (mode, op1);
-
-  if (! reg_or_int16_operand (op2, mode))
-    op2 = force_reg (mode, op2);
-
-  emit_insn (gen_sge_insn (op0, op1, op2));
-  DONE;
-}")
-
-(define_insn "sge_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ge:SI (match_operand:SI 1 "register_operand" "r,r")
-	       (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
-   (clobber (reg:SI 17))]
-  ""
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8,10")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ge:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "reg_or_int16_operand" "")))
-   (clobber (reg:SI 17))]
-  "!optimize_size"
-  [(set (reg:SI 17)
-	(lt:SI (match_dup 1)
-	       (match_dup 2)))
-   (set (match_dup 0)
-	(reg:SI 17))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
-;; xor reg,reg,1 which might eliminate a NOP being inserted.
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ge:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "reg_or_int16_operand" "")))
-   (clobber (reg:SI 17))]
-  "optimize_size"
-  [(set (reg:SI 17)
-	(lt:SI (match_dup 1)
-	       (match_dup 2)))
-   (set (match_dup 0)
-	(reg:SI 17))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))
-   (set (match_dup 0)
-	(neg:SI (match_dup 0)))]
-  "")
-
-(define_expand "sltu"
-  [(match_operand:SI 0 "register_operand" "")]
-  ""
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = m32r_compare_op0;
-  rtx op2 = m32r_compare_op1;
-  enum machine_mode mode = GET_MODE (op0);
-
-  if (mode != SImode)
-    FAIL;
-
-  if (! register_operand (op1, mode))
-    op1 = force_reg (mode, op1);
-
-  if (! reg_or_int16_operand (op2, mode))
-    op2 = force_reg (mode, op2);
-
-  emit_insn (gen_sltu_insn (op0, op1, op2));
-  DONE;
-}")
-
-(define_insn "sltu_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ltu:SI (match_operand:SI 1 "register_operand" "r,r")
-		(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
-   (clobber (reg:SI 17))]
-  ""
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "6,8")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ltu:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "reg_or_int16_operand" "")))
-   (clobber (reg:SI 17))]
-  ""
-  [(set (reg:SI 17)
-	(ltu:SI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(reg:SI 17))]
-  "")
-
-(define_expand "sleu"
-  [(match_operand:SI 0 "register_operand" "")]
-  ""
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = m32r_compare_op0;
-  rtx op2 = m32r_compare_op1;
-  enum machine_mode mode = GET_MODE (op0);
-
-  if (mode != SImode)
-    FAIL;
-
-  if (GET_CODE (op2) == CONST_INT)
-    {
-      HOST_WIDE_INT value = INTVAL (op2);
-      if (value >= 2147483647)
-	{
-	  emit_move_insn (op0, GEN_INT (1));
-	  DONE;
-	}
-
-      op2 = GEN_INT (value+1);
-      if (value < 0 || value >= 32767)
-	op2 = force_reg (mode, op2);
-
-      emit_insn (gen_sltu_insn (op0, op1, op2));
-      DONE;
-    }
-
-  if (! register_operand (op2, mode))
-    op2 = force_reg (mode, op2);
-
-  emit_insn (gen_sleu_insn (op0, op1, op2));
-  DONE;
-}")
-
-(define_insn "sleu_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(leu:SI (match_operand:SI 1 "register_operand" "r")
-		(match_operand:SI 2 "register_operand" "r")))
-   (clobber (reg:SI 17))]
-  ""
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(leu:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "register_operand" "")))
-   (clobber (reg:SI 17))]
-  "!optimize_size"
-  [(set (reg:SI 17)
-	(ltu:SI (match_dup 2)
-		(match_dup 1)))
-   (set (match_dup 0)
-	(reg:SI 17))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
-;; xor reg,reg,1 which might eliminate a NOP being inserted.
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(leu:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "register_operand" "")))
-   (clobber (reg:SI 17))]
-  "optimize_size"
-  [(set (reg:SI 17)
-	(ltu:SI (match_dup 2)
-		(match_dup 1)))
-   (set (match_dup 0)
-	(reg:SI 17))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))
-   (set (match_dup 0)
-	(neg:SI (match_dup 0)))]
-  "")
-
-(define_expand "sgtu"
-  [(match_operand:SI 0 "register_operand" "")]
-  ""
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = m32r_compare_op0;
-  rtx op2 = m32r_compare_op1;
-  enum machine_mode mode = GET_MODE (op0);
-
-  if (mode != SImode)
-    FAIL;
-
-  if (! register_operand (op1, mode))
-    op1 = force_reg (mode, op1);
-
-  if (! register_operand (op2, mode))
-    op2 = force_reg (mode, op2);
-
-  emit_insn (gen_sltu_insn (op0, op2, op1));
-  DONE;
-}")
-
-(define_expand "sgeu"
-  [(match_operand:SI 0 "register_operand" "")]
-  ""
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = m32r_compare_op0;
-  rtx op2 = m32r_compare_op1;
-  enum machine_mode mode = GET_MODE (op0);
-
-  if (mode != SImode)
-    FAIL;
-
-  if (! register_operand (op1, mode))
-    op1 = force_reg (mode, op1);
-
-  if (! reg_or_int16_operand (op2, mode))
-    op2 = force_reg (mode, op2);
-
-  emit_insn (gen_sgeu_insn (op0, op1, op2));
-  DONE;
-}")
-
-(define_insn "sgeu_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(geu:SI (match_operand:SI 1 "register_operand" "r,r")
-		(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
-   (clobber (reg:SI 17))]
-  ""
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8,10")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(geu:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "reg_or_int16_operand" "")))
-   (clobber (reg:SI 17))]
-  "!optimize_size"
-  [(set (reg:SI 17)
-	(ltu:SI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(reg:SI 17))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
-;; xor reg,reg,1 which might eliminate a NOP being inserted.
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(geu:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "reg_or_int16_operand" "")))
-   (clobber (reg:SI 17))]
-  "optimize_size"
-  [(set (reg:SI 17)
-	(ltu:SI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(reg:SI 17))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))
-   (set (match_dup 0)
-	(neg:SI (match_dup 0)))]
-  "")
-
-(define_insn "movcc_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(reg:SI 17))]
-  ""
-  "mvfc %0, cbr"
-  [(set_attr "type" "misc")
-   (set_attr "length" "2")])
-
-
-;; Unconditional and other jump instructions.
-
-(define_insn "jump"
-  [(set (pc) (label_ref (match_operand 0 "" "")))]
-  ""
-  "bra %l0"
-  [(set_attr "type" "uncond_branch")
-   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
-						 (const_int 400))
-					   (const_int 800))
-				      (const_int 2)
-				      (const_int 4)))])
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
-  ""
-  "jmp %a0"
-  [(set_attr "type" "uncond_branch")
-   (set_attr "length" "2")])
-
-(define_insn "return"
-  [(return)]
-  "direct_return ()"
-  "jmp lr"
-  [(set_attr "type" "uncond_branch")
-   (set_attr "length" "2")])
- 
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "address_operand" "p"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmp %a0"
-  [(set_attr "type" "uncond_branch")
-   (set_attr "length" "2")])
-
-(define_expand "call"
-  ;; operands[1] is stack_size_rtx
-  ;; operands[2] is next_arg_register
-  [(parallel [(call (match_operand:SI 0 "call_operand" "")
-		    (match_operand 1 "" ""))
-	     (clobber (reg:SI 14))])]
-  ""
-  "")
-
-(define_insn "*call_via_reg"
-  [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
-	 (match_operand 1 "" ""))
-   (clobber (reg:SI 14))]
-  ""
-  "jl %0"
-  [(set_attr "type" "call")
-   (set_attr "length" "2")])
-
-(define_insn "*call_via_label"
-  [(call (mem:SI (match_operand:SI 0 "call_address_operand" ""))
-	 (match_operand 1 "" ""))
-   (clobber (reg:SI 14))]
-  ""
-  "*
-{
-  int call26_p = call26_operand (operands[0], FUNCTION_MODE);
-
-  if (! call26_p)
-    {
-      /* We may not be able to reach with a `bl' insn so punt and leave it to
-	 the linker.
-	 We do this here, rather than doing a force_reg in the define_expand
-	 so these insns won't be separated, say by scheduling, thus simplifying
-	 the linker.  */
-      return \"seth r14,%T0\;add3 r14,r14,%B0\;jl r14\";
-    }
-  else
-    return \"bl %0\";
-}"
-  [(set_attr "type" "call")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "call26_operand (operands[0], FUNCTION_MODE)")
-			  (const_int 0))
-		      (const_int 12) ; 10 + 2 for nop filler
-		      ; The return address must be on a 4 byte boundary so
-		      ; there's no point in using a value of 2 here.  A 2 byte
-		      ; insn may go in the left slot but we currently can't
-		      ; use such knowledge.
-		      (const_int 4)))])
-
-(define_expand "call_value"
-  ;; operand 2 is stack_size_rtx
-  ;; operand 3 is next_arg_register
-  [(parallel [(set (match_operand 0 "register_operand" "=r")
-		   (call (match_operand:SI 1 "call_operand" "")
-			 (match_operand 2 "" "")))
-	     (clobber (reg:SI 14))])]
-  ""
-  "")
-
-(define_insn "*call_value_via_reg"
-  [(set (match_operand 0 "register_operand" "=r")
-	(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
-	      (match_operand 2 "" "")))
-   (clobber (reg:SI 14))]
-  ""
-  "jl %1"
-  [(set_attr "type" "call")
-   (set_attr "length" "2")])
-
-(define_insn "*call_value_via_label"
-  [(set (match_operand 0 "register_operand" "=r")
-	(call (mem:SI (match_operand:SI 1 "call_address_operand" ""))
-	      (match_operand 2 "" "")))
-   (clobber (reg:SI 14))]
-  ""
-  "*
-{
-  int call26_p = call26_operand (operands[1], FUNCTION_MODE);
-
-  if (! call26_p)
-    {
-      /* We may not be able to reach with a `bl' insn so punt and leave it to
-	 the linker.
-	 We do this here, rather than doing a force_reg in the define_expand
-	 so these insns won't be separated, say by scheduling, thus simplifying
-	 the linker.  */
-      return \"seth r14,%T1\;add3 r14,r14,%B1\;jl r14\";
-    }
-  else
-    return \"bl %1\";
-}"
-  [(set_attr "type" "call")
-   (set (attr "length")
-	(if_then_else (eq (symbol_ref "call26_operand (operands[1], FUNCTION_MODE)")
-			  (const_int 0))
-		      (const_int 12) ; 10 + 2 for nop filler
-		      ; The return address must be on a 4 byte boundary so
-		      ; there's no point in using a value of 2 here.  A 2 byte
-		      ; insn may go in the left slot but we currently can't
-		      ; use such knowledge.
-		      (const_int 4)))])
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-  [(set_attr "type" "int2")
-   (set_attr "length" "2")])
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-;; Special pattern to flush the icache.
-
-(define_insn "flush_icache"
-  [(unspec_volatile [(match_operand 0 "memory_operand" "m")] 0)]
-  ""
-  "* return \"nop ; flush-icache\";"
-  [(set_attr "type" "int2")
-   (set_attr "length" "2")])
-
-;; Speed up fabs and provide correct sign handling for -0
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(abs:DF (match_operand:DF 1 "register_operand" "0")))]
-  ""
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "4")])
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-	(abs:DF (match_operand:DF 1 "register_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 2)
-	(ashift:SI (match_dup 2)
-		   (const_int 1)))
-   (set (match_dup 2)
-	(lshiftrt:SI (match_dup 2)
-		     (const_int 1)))]
-  "operands[2] = gen_highpart (SImode, operands[0]);")
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(abs:SF (match_operand:SF 1 "register_operand" "0")))]
-  ""
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "4")])
-
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "")
-	(abs:SF (match_operand:SF 1 "register_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 2)
-	(ashift:SI (match_dup 2)
-		   (const_int 1)))
-   (set (match_dup 2)
-	(lshiftrt:SI (match_dup 2)
-		     (const_int 1)))]
-  "operands[2] = gen_highpart (SImode, operands[0]);")
-
-
-;; These patterns are currently commented out as the customer does
-;; not wish the compiler to generate code using instructions which
-;; are not yet open to the public.
-
-;; ;; Move of SImode integer.  Currently we can handle register to register moves
-;; ;; and constant into register moves.
-;; 
-;; (define_expand "movsicc"
-;;   [
-;;    (set (match_operand:SI 0 "register_operand" "r,r,r,r")
-;; 	(if_then_else:SI (match_operand 1 "" "")
-;; 			 (match_operand:SI 2 "conditional_move_operand" "r,r,P,P")
-;; 			 (match_operand:SI 3 "conditional_move_operand" "r,P,r,P")
-;;         )
-;;    )
-;;   ]
-;;   ""
-;;   "
-;; {
-;;   if (! TARGET_M32RX && ! zero_and_one (operands [2], operands [3]))
-;;     FAIL;
-;; 
-;;   /* Generate the comparision that will set the carry flag.  */
-;;   operands[1] = gen_compare ((int)GET_CODE (operands[1]), m32r_compare_op0, m32r_compare_op1);
-;; 
-;;   /* If the conditional move is putting either the constant 0 or
-;;      the constant 1 into the destination register the RTL to do
-;;      this will be optimised away by the combine pass (because
-;;      cmp_ne_small_const_insn claims that it can do everything in
-;;      one pattern, when this is not really true).  Catch this case
-;;      here and generate a block to prevent the combiner from
-;;      optimising us away..  */
-;;   if (zero_and_one (operands [2], operands [3]))
-;;     emit_insn (gen_blockage());
-;; }")
-;; 
-;; ;; Generate the conditional instructions based on how the carry flag is examined.
-;; (define_insn "*movsicc_internal"
-;;   [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-;; 	(if_then_else:SI (match_operand 1 "carry_compare_operand" "")
-;; 			 (match_operand:SI 2 "conditional_move_operand" "r,r,P,P")
-;; 			 (match_operand:SI 3 "conditional_move_operand" "r,P,r,P")
-;;         )
-;;    )]
-;;   "TARGET_M32RX || zero_and_one (operands [2], operands[3])"
-;;   "* return emit_cond_move (operands, insn);"
-;;   [(set_attr "type" "multi")
-;;    (set_attr "length" "8")]
-;; )
-
-;; The movhicc and movqicc patterns are not here because
-;; PROMOTE_MODE() will porbably turn any such references into
-;; SImode operations.  If they are ever needed then they are
-;; easy to add since they are just duplications of the above
-;; two patterns with SImode replaced by HImode or QImode.
-;; 
-;; ;; Conditional Execution
-;; ;; This code is based on the code used for the d10v
-;; 
-;; (define_insn "*cond_exec_si_binary_true"
-;;   [(if_then_else
-;;       (match_operand 3 "conditional_compare_operand" "")
-;; 	 (set (match_operand:SI 0 "register_operand" "=r,r")
-;; 	      (match_operator:SI 4 "binary_parallel_operator"
-;; 		 [(match_operand:SI 1 "register_operand" "0,0")
-;; 		  (match_operand:SI 2 "nonmemory_operand" "r,I")
-;; 		 ]
-;; 	       )
-;; 	  )
-;; 	 (const_int 0)
-;;   )]
-;;   "TARGET_M32RX"
-;;   "* return emit_binary_cond_exec (operands, TRUE);"
-;;   [(set_attr "type" "multi")
-;;    (set_attr "length" "8")]
-;; )
-;; 
-;; (define_insn "*cond_exec_si_binary_false"
-;;   [(if_then_else
-;;       (match_operand 3 "conditional_compare_operand" "")
-;;       (const_int 0)
-;;       (set (match_operand:SI 0 "register_operand" "=r,r")
-;; 	   (match_operator:SI 4 "binary_parallel_operator"
-;; 	      [(match_operand:SI 1 "register_operand" "0,0")
-;; 	       (match_operand:SI 2 "nonmemory_operand" "r,I")
-;; 	      ]
-;; 	   )
-;;       )
-;;   )]
-;;   "TARGET_M32RX"
-;;   "* return emit_binary_cond_exec (operands, FALSE);"
-;;   [(set_attr "type" "multi")
-;;    (set_attr "length" "8")]
-;; )
-;; 
-;; (define_insn "*cond_exec_si_unary_true"
-;;   [(if_then_else
-;;       (match_operand 2 "conditional_compare_operand" "")
-;; 	 (set (match_operand:SI 0 "register_operand" "=r")
-;; 	      (match_operator:SI 3 "unary_parallel_operator"
-;; 		 [(match_operand:SI 1 "register_operand" "r")]
-;; 	       )
-;; 	  )
-;; 	 (const_int 0)
-;;   )]
-;;   "TARGET_M32RX"
-;;   "* return emit_unary_cond_exec (operands, TRUE);"
-;;   [(set_attr "type" "multi")
-;;    (set_attr "length" "8")]
-;; )
-;; 
-;; (define_insn "*cond_exec_si_unary_false"
-;;   [(if_then_else
-;;       (match_operand 2 "conditional_compare_operand" "")
-;;       (const_int 0)
-;;       (set (match_operand:SI 0 "register_operand" "=r")
-;; 	   (match_operator:SI 3 "unary_parallel_operator"
-;; 	      [(match_operand:SI 1 "register_operand" "r")]
-;; 	   )
-;;       )
-;;   )]
-;;   "TARGET_M32RX"
-;;   "* return emit_unary_cond_exec (operands, FALSE);"
-;;   [(set_attr "type" "multi")
-;;    (set_attr "length" "8")]
-;; )
-;;
-
-;; END CYGNUS LOCAL -- meissner/m32r work
-
-;; Block moves, see m32r.c for more details.
-;; Argument 0 is the destination
-;; Argument 1 is the source
-;; Argument 2 is the length
-;; Argument 3 is the alignment
-
-(define_expand "movstrsi"
-  [(parallel [(set (match_operand:BLK 0 "general_operand" "")
-		   (match_operand:BLK 1 "general_operand" ""))
-	      (use (match_operand:SI  2 "immediate_operand" ""))
-	      (use (match_operand:SI  3 "immediate_operand" ""))])]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code messages */
-    {
-      m32r_expand_block_move (operands);
-      DONE;
-    }
-}")
-
-;; Insn generated by block moves
-
-(define_insn "movstrsi_internal"
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))	;; destination
-	(mem:BLK (match_operand:SI 1 "register_operand" "r")))	;; source
-   (use (match_operand:SI 2 "m32r_block_immediate_operand" "J"));; # bytes to move
-   (set (match_dup 0) (plus:SI (match_dup 0) (minus:SI (match_dup 2) (const_int 4))))
-   (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 3 "=&r"))				;; temp 1
-   (clobber (match_scratch:SI 4 "=&r"))]			;; temp 2
-  ""
-  "* return m32r_output_block_move (insn, operands);"
-  [(set_attr "type"	"store8")
-   (set_attr "length"	"72")]) ;; Maximum
diff --git a/gcc/config/m32r/t-m32r b/gcc/config/m32r/t-m32r
deleted file mode 100755
index 1f6e3d7..0000000
--- a/gcc/config/m32r/t-m32r
+++ /dev/null
@@ -1,70 +0,0 @@
-# lib1funcs.asm is currently empty.
-CROSS_LIBGCC1 =
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-# Turn off the SDA while compiling libgcc2.  There are no headers for it
-# and we want maximal upward compatibility here.
-
-TARGET_LIBGCC2_CFLAGS = -G 0
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-# We need to use -fpic when we are using gcc to compile the routines in
-# initfini.c.  This is only really needed when we are going to use gcc/g++
-# to produce a shared library, but since we don't know ahead of time when
-# we will be doing that, we just always use -fpic when compiling the
-# routines in initfini.c.
-# -fpic currently isn't supported for the m32r.
-
-CRTSTUFF_T_CFLAGS =
-
-# .init/.fini section routines
-
-crtinit.o: $(srcdir)/config/m32r/initfini.c $(GCC_PASSES) $(CONFIG_H)
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(CRTSTUFF_T_CFLAGS) \
-	  -DCRT_INIT -finhibit-size-directive -fno-inline-functions \
-	  -g0 -c $(srcdir)/config/m32r/initfini.c -o crtinit.o
-
-crtfini.o: $(srcdir)/config/m32r/initfini.c $(GCC_PASSES) $(CONFIG_H)
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(CRTSTUFF_T_CFLAGS) \
-	  -DCRT_FINI -finhibit-size-directive -fno-inline-functions \
-	  -g0 -c $(srcdir)/config/m32r/initfini.c -o crtfini.o
-
-m32rx/crtinit.o: $(srcdir)/config/m32r/initfini.c $(GCC_PASSES) $(CONFIG_H)
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(CRTSTUFF_T_CFLAGS) \
-	  -DCRT_INIT -finhibit-size-directive -fno-inline-functions \
-	  -g0 -c $(srcdir)/config/m32r/initfini.c -m32rx -o m32rx/crtinit.o
-
-m32rx/crtfini.o: $(srcdir)/config/m32r/initfini.c $(GCC_PASSES) $(CONFIG_H)
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(CRTSTUFF_T_CFLAGS) \
-	  -DCRT_FINI -finhibit-size-directive -fno-inline-functions \
-	  -g0 -c $(srcdir)/config/m32r/initfini.c -m32rx -o m32rx/crtfini.o
-
-# -mmodel={small,medium} requires separate libraries.
-# We don't build libraries for the large model, instead we use the medium
-# libraries.  The only difference is that the large model can handle jumps
-# more than 26 signed bits away.
-
-MULTILIB_OPTIONS = mmodel=small/mmodel=medium
-MULTILIB_DIRNAMES = small medium
-MULTILIB_MATCHES = mmodel?medium=mmodel?large
-
-MULTILIB_OPTIONS = mmodel=small/mmodel=medium m32r/m32rx
-MULTILIB_DIRNAMES = small medium m32r m32rx
-
-# Set MULTILIB_EXTRA_OPTS so shipped libraries have small data in .sdata and
-# SHN_M32R_SCOMMON.
-# This is important for objects referenced in system header files.
-MULTILIB_EXTRA_OPTS = msdata=sdata
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/m32r/xm-m32r.h b/gcc/config/m32r/xm-m32r.h
deleted file mode 100755
index 57100c8..0000000
--- a/gcc/config/m32r/xm-m32r.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Configuration for GNU C-compiler for the M32R processor.
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Doubles are stored in memory with the high order word first.  This
-   matters when cross-compiling.  */
-#define HOST_WORDS_BIG_ENDIAN 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* If compiled with Sun CC, the use of alloca requires this #include.  */
-#ifndef __GNUC__
-#include "alloca.h"
-#endif
diff --git a/gcc/config/m68k/3b1.h b/gcc/config/m68k/3b1.h
deleted file mode 100755
index 2b6611a..0000000
--- a/gcc/config/m68k/3b1.h
+++ /dev/null
@@ -1,513 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   AT&T UNIX PC version (pc7300, 3b1)
-   Copyright (C) 1987, 1993, 1996 Free Software Foundation, Inc.
-   Contributed by Alex Crain (alex@umbc3.umd.edu).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define SGS_SWITCH_TABLES	/* Different switch table handling */
-
-#include "m68k/hp320.h"
-
-/* See m68k.h.  0 means 680[01]0 with no 68881.  */
-
-#undef TARGET_DEFAULT
-#define	TARGET_DEFAULT 0
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* -m68020 requires special flags to the assembler.  */
-
-#undef ASM_SPEC
-#define ASM_SPEC "%{m68020:-68020}%{!m68020:-68010} %{m68881:-68881}"
-
-/* we use /lib/libp/lib*  when profiling */
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{!shlib:%{p:-L/lib/libp} %{pg:-L/lib/libp} -lc}"
-
-/* shared libraries need to use crt0s.o  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{!shlib:%{pg:mcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}\
-   %{shlib:crt0s.o%s shlib.ifile%s} "
-
-/* cpp has to support a #sccs directive for the /usr/include files */
-
-#define SCCS_DIRECTIVE
-
-/* Make output for SDB.  */
-
-#define SDB_DEBUGGING_INFO
-
-/* The .file command should always begin the output.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
-output_file_directive ((FILE), main_input_filename)
-
-/* Don't try to define `gcc_compiled.' since the assembler might not
-   accept symbols with periods and GDB doesn't run on this machine anyway.  */
-#define ASM_IDENTIFY_GCC(FILE)
-
-/* Define __HAVE_68881__ in preprocessor if -m68881 is specified.
-   This will control the use of inline 68881 insns in certain macros.  */
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{m68881:-D__HAVE_68881__}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-/* ihnp4!lmayk!lgm@eddie.mit.edu says mc68000 and m68k should not be here.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmc68k -Dunix -Dunixpc -D__motorola__ -Asystem(unix)  -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)"
-
-#undef REGISTER_NAMES
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",	\
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",	\
- "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7"}
-
-/* Specify how to pad function arguments.
-   Value should be `upward', `downward' or `none'.
-   Same as the default, except no padding for large or variable-size args.  */
-
-#define FUNCTION_ARG_PADDING(MODE, TYPE)				\
-  (((MODE) == BLKmode							\
-    ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST		\
-       && int_size_in_bytes (TYPE) < PARM_BOUNDARY / BITS_PER_UNIT)	\
-    : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY)				\
-   ? downward : none)
-
-/* The 3b1 does not have `atexit'.  */
-
-#undef HAVE_ATEXIT
-
-/* Override parts of m68k.h to fit the SGS-3b1 assembler.  */
-
-#undef TARGET_VERSION
-#undef ASM_FORMAT_PRIVATE_NAME
-#undef ASM_OUTPUT_DOUBLE
-#undef ASM_OUTPUT_FLOAT
-#undef ASM_OUTPUT_ALIGN
-#undef ASM_OUTPUT_SOURCE_FILENAME
-#undef ASM_OUTPUT_SOURCE_LINE
-#undef PRINT_OPERAND_ADDRESS
-#undef ASM_GENERATE_INTERNAL_LABEL
-#undef FUNCTION_PROFILER
-#undef ASM_OUTPUT_ADDR_VEC_ELT
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#undef ASM_OUTPUT_OPCODE
-#undef ASM_OUTPUT_LOCAL
-#undef USER_LABEL_PREFIX
-#undef ASM_OUTPUT_ASCII
-
-#define TARGET_VERSION fprintf (stderr, " (68k, SGS/AT&T unixpc syntax)");
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12),	\
-  sprintf ((OUTPUT), "%s_%%%d", (NAME), (LABELNO)))
-
-/* The unixpc doesn't know about double's and float's */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-do { long l[2];						\
-     REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l);		\
-     fprintf (FILE, "\tlong 0x%x,0x%x\n", l[0], l[1]); \
-   } while (0)
-
-#undef ASM_OUTPUT_LONG_DOUBLE
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE)  				\
-do { long l[3];								\
-     REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l);			\
-     fprintf (FILE, "\tlong 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]);	\
-   } while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-do { long l;					\
-     REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);	\
-     fprintf ((FILE), "\tlong 0x%x\n", l);	\
-   } while (0)
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) == 1)			\
-    fprintf (FILE, "\teven\n");	\
-  else if ((LOG) != 0)			\
-    abort ();
-
-/* This is how to output an assembler line
-   that says to advance the location counter by SIZE bytes.  */
-
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\tspace %d\n", (SIZE))
-
-/* Can't use ASM_OUTPUT_SKIP in text section; it doesn't leave 0s.  */
-
-#define ASM_NO_SKIP_IN_TEXT 1
-
-/* The beginnings of sdb support... */
-
-#define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) \
-  do {	fprintf (FILE, "\tfile\t");		\
-	output_quoted_string (FILE, FILENAME);	\
-	fprintf (FILE, "\n");			\
-  } while (0)
-
-#define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO)	\
-  fprintf (FILE, "\tln\t%d\n",			\
-	   (sdb_begin_function_line		\
-	    ? last_linenum - sdb_begin_function_line : 1))
-
-/* Yet another null terminated string format. */
-
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \
-  do { register int sp = 0, lp = 0; \
-    fprintf ((FILE), "\tbyte\t"); \
-  loop: \
-    if ((PTR)[sp] > ' ' && ! ((PTR)[sp] & 0x80) && (PTR)[sp] != '\\') \
-      { lp += 3; \
-	fprintf ((FILE), "'%c", (PTR)[sp]); } \
-    else \
-      { lp += 5; \
-	fprintf ((FILE), "0x%x", (PTR)[sp]); } \
-    if (++sp < (LEN)) \
-      {	if (lp > 60) \
-	  { lp = 0; \
-	    fprintf ((FILE), "\n\t%s ", ASCII_DATA_ASM_OP); }	\
-	else \
-	  putc (',', (FILE)); \
-	goto loop; } \
-    putc ('\n', (FILE)); } while (0)
-
-/* Note that in the case of the movhi which fetches an element of
-   an ADDR_DIFF_VEC the offset output is too large by 2.
-   This is because the 3b1 assembler refuses to subtract 2.
-   ASM_OUTPUT_CASE_LABEL, below, compensates for this.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx reg1, reg2, breg, ireg;					\
-  register rtx addr = ADDR;						\
-  rtx offset;								\
-  switch (GET_CODE (addr))						\
-    {									\
-    case REG:								\
-      fprintf (FILE, "(%s)", reg_names[REGNO (addr)]);			\
-      break;								\
-    case PRE_DEC:							\
-      fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case POST_INC:							\
-      fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case PLUS:								\
-      reg1 = 0;	reg2 = 0;						\
-      ireg = 0;	breg = 0;						\
-      offset = 0;							\
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))				\
-	{								\
-	  offset = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))			\
-	{								\
-	  offset = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) != PLUS) ;					\
-      else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT		\
-	  || GET_CODE (addr) == SIGN_EXTEND)				\
-	{ if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; }	\
-/*  for OLD_INDEXING							\
-      else if (GET_CODE (addr) == PLUS)					\
-	{								\
-	  if (GET_CODE (XEXP (addr, 0)) == REG)				\
-	    {								\
-	      reg2 = XEXP (addr, 0);					\
-	      addr = XEXP (addr, 1);					\
-	    }								\
-	  else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	    {								\
-	      reg2 = XEXP (addr, 1);					\
-	      addr = XEXP (addr, 0);					\
-	    }								\
-	}								\
-  */									\
-      if (offset != 0) { if (addr != 0) abort (); addr = offset; }	\
-      if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND			\
-		    || GET_CODE (reg1) == MULT))			\
-	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))		\
-	{ breg = reg2; ireg = reg1; }					\
-      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))		\
-	{ breg = reg1; ireg = reg2; }					\
-      if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { int scale = 1;						\
-	  if (GET_CODE (ireg) == MULT)					\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (GET_CODE (ireg) == SIGN_EXTEND)				\
-	    fprintf (FILE, "LD%%%d(%%pc,%s.w",				\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (XEXP (ireg, 0))]); 		\
-	  else								\
-	    fprintf (FILE, "LD%%%d(%%pc,%s.l",				\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (ireg)]);				\
-	  if (scale != 1) fprintf (FILE, "*%d", scale);			\
-	  fprintf (FILE, ")");						\
-	  break; }							\
-      if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { fprintf (FILE, "LD%%%d(%%pc,%s.l",				\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   reg_names[REGNO (breg)]);				\
-	  putc (')', FILE);						\
-	  break; }							\
-      if (ireg != 0 || breg != 0)					\
-	{ int scale = 1;						\
-	  if (breg == 0)						\
-	    abort ();							\
-	  if (addr != 0)						\
-	    output_addr_const (FILE, addr);				\
-	  fprintf (FILE, "(%s", reg_names[REGNO (breg)]);		\
-	  if (ireg != 0)					        \
-	    putc (',', FILE);						\
-	  if (ireg != 0 && GET_CODE (ireg) == MULT)			\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)		\
-	    fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);	\
-	  else if (ireg != 0)						\
-	    fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]);		\
-	  if (scale != 1) fprintf (FILE, "*%d", scale);			\
-	  putc (')', FILE);						\
-	  break;							\
-	}								\
-      else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF)		\
-	{ fprintf (FILE, "LD%%%d(%%pc,%s.w)",				\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   reg_names[REGNO (reg1)]);				\
-	  break; }							\
-    default:								\
-      if (GET_CODE (addr) == CONST_INT					\
-	  && INTVAL (addr) < 0x8000					\
-	  && INTVAL (addr) >= -0x8000)					\
-	fprintf (FILE, "%d", INTVAL (addr));				\
-      else								\
-        output_addr_const (FILE, addr);					\
-    }}
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)	\
-  sprintf ((LABEL), "%s%%%d", (PREFIX), (NUM))
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-    fprintf (FILE, "%s%%%d:\n", PREFIX, NUM)
-
-/* Must put address in  %a0 , not  %d0 . -- LGM, 7/15/88 */
-#define FUNCTION_PROFILER(FILE, LABEL_NO)	\
-    fprintf (FILE, "\tmov.l &LP%%%d,%%a0\n\tjsr mcount\n", (LABEL_NO))
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)	\
-    fprintf (FILE, "\tlong L%%%d\n", (VALUE))
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)	\
-    fprintf (FILE, "\tshort L%%%d-L%%%d\n", (VALUE), (REL))
-
-/* ihnp4!lmayk!lgm says that `short 0' triggers assembler bug;
-   `short L%nn-L%nn' supposedly works.  */
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE)			\
-  if (! RTX_INTEGRATED_P (TABLE))					\
-    fprintf (FILE, "\tswbeg &%d\n%s%%%d:\n",				\
-	     XVECLEN (PATTERN (TABLE), 1), (PREFIX), (NUM));		\
-  else									\
-    fprintf (FILE, "\tswbeg &%d\n%s%%%d:\n\tshort %s%%%d-%s%%%d\n",	\
-	     XVECLEN (PATTERN (TABLE), 1) + 1, (PREFIX), (NUM),		\
-	     (PREFIX), (NUM), (PREFIX), (NUM))
-
-/* At end of a switch table, define LDnnn iff the symbol LInnn was defined.
-   Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
-   fails to assemble.  Luckily "LDnnn(pc,d0.l*2)" produces the results
-   we want.  This difference can be accommodated by making the assembler
-   define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
-   string, as necessary.  This is accomplished via the ASM_OUTPUT_CASE_END
-   macro. */
-
-#define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE)				\
-{ if (switch_table_difference_label_flag)				\
-    fprintf (FILE, "\tset LD%%%d,L%%%d-LI%%%d\n", (NUM), (NUM), (NUM));	\
-  switch_table_difference_label_flag = 0; }
-
-int switch_table_difference_label_flag;
-
-#define ASM_OUTPUT_OPCODE(FILE, PTR)			\
-{ if ((PTR)[0] == 'j' && (PTR)[1] == 'b')		\
-    { ++(PTR);						\
-      while (*(PTR) != ' ')				\
-	{ putc (*(PTR), (FILE)); ++(PTR); }		\
-      fprintf ((FILE), ".w"); }				\
-  else if ((PTR)[0] == 's')				\
-    {							\
-      if (!strncmp ((PTR), "swap", 4))			\
-	{ fprintf ((FILE), "swap.w"); (PTR) += 4; }	\
-    }							\
-  else if ((PTR)[0] == 'f')				\
-    {							\
-      if (!strncmp ((PTR), "fmove", 5))			\
-	{ fprintf ((FILE), "fmov"); (PTR) += 5; }	\
-      else if (!strncmp ((PTR), "fbne", 4))		\
-	{ fprintf ((FILE), "fbneq"); (PTR) += 4; }	\
-    }							\
-/* MOVE, MOVEA, MOVEQ, MOVEC ==> MOV	*/		\
-  else if ((PTR)[0] == 'm' && (PTR)[1] == 'o'		\
-	   && (PTR)[2] == 'v' && (PTR)[3] == 'e')	\
-    { fprintf ((FILE), "mov"); (PTR) += 4;		\
-       if ((PTR)[0] == 'q' || (PTR)[0] == 'a'		\
-	   || (PTR)[0] == 'c') (PTR)++; }		\
-/* SUB, SUBQ, SUBA, SUBI ==> SUB */			\
-  else if ((PTR)[0] == 's' && (PTR)[1] == 'u' 		\
-	   && (PTR)[2] == 'b')				\
-    { fprintf ((FILE), "sub"); (PTR) += 3;		\
-       if ((PTR)[0] == 'q' || (PTR)[0] == 'i'	 	\
-	   || (PTR)[0] == 'a') (PTR)++; }		\
-/* CMP, CMPA, CMPI, CMPM ==> CMP	*/		\
-  else if ((PTR)[0] == 'c' && (PTR)[1] == 'm'		\
-	   && (PTR)[2] == 'p')				\
-    { fprintf ((FILE), "cmp"); (PTR) += 3;		\
-       if ((PTR)[0] == 'a' || (PTR)[0] == 'i'	 	\
-	   || (PTR)[0] == 'm') (PTR)++; }		\
-}
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\tlcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-#define USER_LABEL_PREFIX ""
-
-/* Override usual definitions of SDB output macros.
-   These definitions differ only in the absence of the period
-   at the beginning of the name of the directive
-   and in the use of `~' as the symbol for the current location.  */
-
-#define PUT_SDB_SCL(a) fprintf(asm_out_file, "\tscl\t%d;", (a))
-#define PUT_SDB_INT_VAL(a) fprintf (asm_out_file, "\tval\t%d;", (a))
-#define PUT_SDB_VAL(a)				\
-( fputs ("\tval\t", asm_out_file),		\
-  output_addr_const (asm_out_file, (a)),	\
-  fputc (';', asm_out_file))
-
-#define PUT_SDB_DEF(a)				\
-do { fprintf (asm_out_file, "\tdef\t");	\
-     ASM_OUTPUT_LABELREF (asm_out_file, a); 	\
-     fprintf (asm_out_file, ";"); } while (0)
-
-#define PUT_SDB_PLAIN_DEF(a) fprintf(asm_out_file,"\tdef\t~%s;",a)
-#define PUT_SDB_ENDEF fputs("\tendef\n", asm_out_file)
-#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\ttype\t0%o;", a)
-#define PUT_SDB_SIZE(a) fprintf(asm_out_file, "\tsize\t%d;", a)
-#define PUT_SDB_START_DIM fprintf(asm_out_file, "\tdim\t")
-
-#define PUT_SDB_TAG(a)				\
-do { fprintf (asm_out_file, "\ttag\t");	\
-     ASM_OUTPUT_LABELREF (asm_out_file, a);	\
-     fprintf (asm_out_file, ";"); } while (0)
-
-#define PUT_SDB_BLOCK_START(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~bb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n",	\
-	   (LINE))
-
-#define PUT_SDB_BLOCK_END(LINE)			\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~eb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n",	\
-	   (LINE))
-
-#define PUT_SDB_FUNCTION_START(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~bf;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n",	\
-	   (LINE))
-
-#define PUT_SDB_FUNCTION_END(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~ef;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n",	\
-	   (LINE))
-
-#define PUT_SDB_EPILOGUE_END(NAME)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t%s;\tval\t~;\tscl\t-1;\tendef\n",	\
-	   (NAME))
-
-#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
-  sprintf ((BUFFER), "~%dfake", (NUMBER));
-
-/* Define subroutines to call to handle multiply, divide, and remainder.
-   Use the subroutines that the 3b1's library provides.
-   The `*' prevents an underscore from being prepended by the compiler.  */
-
-#define DIVSI3_LIBCALL "*ldiv"
-#define UDIVSI3_LIBCALL "*uldiv"
-#define MODSI3_LIBCALL "*lrem"
-#define UMODSI3_LIBCALL "*ulrem"
-#define MULSI3_LIBCALL "*lmul"
-#define UMULSI3_LIBCALL "*ulmul"
-
-/* Definitions for collect2.  */
-
-#define OBJECT_FORMAT_COFF
-#define NO_SYS_SIGLIST
-#define MY_ISCOFF(magic) \
- ((magic) == MC68KWRMAGIC || (magic) == MC68KROMAGIC || (magic) == MC68KPGMAGIC)
diff --git a/gcc/config/m68k/3b1g.h b/gcc/config/m68k/3b1g.h
deleted file mode 100755
index 2b1d23c..0000000
--- a/gcc/config/m68k/3b1g.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Definitions of target machine for GNU compiler, for a 3b1 using GAS.
-   Copyright (C) 1987, 1988 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m68k/m68k.h"
-
-/* See m68k.h.  0 means 68000 with no 68881.  */
-#define TARGET_DEFAULT 0
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Define __HAVE_68881 in preprocessor only if -m68881 is specified.
-   This will control the use of inline 68881 insns in certain macros.
-   Also inform the program which CPU this is for.  */
-#define CPP_SPEC "%{m68881:-D__HAVE_68881__} \
-%{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}"
-
-/* -m68020 requires special flags to the assembler.  */
-#define ASM_SPEC \
- "%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!m68020:-mc68010}}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-#define CPP_PREDEFINES "-Dmc68000 -Dmc68k -Dunix -Dunixpc -Asystem(unix)  -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)"
-
-/* This is (not really) BSD, so (but) it wants DBX format.  */
-#define DBX_DEBUGGING_INFO
-
-/* Brain damage. */
-#define SCCS_DIRECTIVE
-
-/* Specify how to pad function arguments.
-   Value should be `upward', `downward' or `none'.
-   Same as the default, except no padding for large or variable-size args.  */
-#define FUNCTION_ARG_PADDING(MODE, TYPE)				\
-  (((MODE) == BLKmode							\
-    ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE))	== INTEGER_CST		\
-       && int_size_in_bytes (TYPE) < PARM_BOUNDARY / BITS_PER_UNIT)	\
-    : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY)				\
-   ? downward : none)
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#define TARGET_MEM_FUNCTIONS
-
diff --git a/gcc/config/m68k/a-ux.h b/gcc/config/m68k/a-ux.h
deleted file mode 100755
index 69ecb53..0000000
--- a/gcc/config/m68k/a-ux.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/* Definitions for Motorola 680x0 running A/UX
-   Copyright (C) 1996, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file was renamed from aux.h because of MSDOS: aux.anything
-   isn't usable.  Sigh.  */
-
-/* Execution environment */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)	/* 68020, 68881 */
-
-#define CPP_PREDEFINES "-Dunix -Dm68k -DAUX -DmacII \
--Asystem(unix) -Asystem(AUX) -Acpu(m68k) -Amachine(m68k) -Amachine(macII)"
-
-#define CPP_SPEC \
-"%{!msoft-float:%{!ansi:-Dmc68881 }-D__HAVE_68881__ }\
--Acpu(mc68000) -D__mc68000__ %{!ansi:-Dmc68000 }\
-%{!mc68000:%{!m68000:-Acpu(mc68020) -D__mc68020__ %{!ansi:-Dmc68020 }}}\
-%{m68030:-Acpu(mc68030) -D__mc68030__ %{!ansi:-Dmc68030 }}\
-%{m68040:-Acpu(mc68040) -D__mc68040__ %{!ansi:-Dmc68040 }}\
-%{!ansi:%{!traditional:-D__STDC__=2 }}\
-%{sbsd:-D_BSD_SOURCE -DBSD }%{ZB:-D_BSD_SOURCE -DBSD }\
-%{ssysv:-D_SYSV_SOURCE -DSYSV -DUSG }%{ZS:-D_SYSV_SOURCE -DSYSV -DUSG }\
-%{sposix:-D_POSIX_SOURCE -DPOSIX }%{ZP:-D_POSIX_SOURCE -DPOSIX }\
-%{sposix+:-D_POSIX_SOURCE -DPOSIX }\
-%{saux:-D_AUX_SOURCE }%{ZA:-D_AUX_SOURCE }\
-%{!sbsd:%{!ZB:%{!ssysv:%{!ZS:%{!sposix:%{!ZP:%{!snone:\
--D_BSD_SOURCE -D_SYSV_SOURCE -D_AUX_SOURCE }}}}}}}"
-
-#define LIB_SPEC \
-"%{sbsd:-lbsd }%{ZB:-lbsd }\
-%{ssysv:-lsvid }%{ZS:-lsvid }\
-%{sposix:-lposix }%{ZP:-lposix }%{sposix+:-lposix }\
-%{!static:%{smac:-lmac_s -lat -lld -lmr }-lc_s }\
-%{static:%{smac:-lmac -lat -lld -lmr }-lc }"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-"%{pg:mcrt0.o%s }%{!pg:%{p:mcrt1.o%s }\
-%{!p:%{smac:maccrt1.o%s low.o%s }%{!smac:crt1.o%s }}}\
-crt2.o%s "
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtn.o%s "
-
-
-/*===================================================================*/
-/* Compilation environment -- mostly */
-
-#define NO_SYS_SIGLIST
-
-/* We provide atexit(), A/UX does not have it */
-#define HAVE_ATEXIT
-
-/* Generate calls to memcpy, memcmp and memset, as opposed to bcopy, bcmp,
-   and bzero */
-#define TARGET_MEM_FUNCTIONS
-
-/* Resize standard types */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "unsigned int"
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Bits needed by collect */
-
-#define OBJECT_FORMAT_COFF
-#define MY_ISCOFF(m)	((m) == M68TVMAGIC || \
-			 (m) == M68MAGIC || \
-			 (m) == MC68TVMAGIC || \
-			 (m) == MC68MAGIC || \
-			 (m) == M68NSMAGIC)
-
-
-#ifndef USE_COLLECT2
-/* For .ctor/.dtor sections for collecting constructors */
-/* We have special start/end files for defining [cd]tor lists */
-#define CTOR_LISTS_DEFINED_EXTERNALLY
-#endif
-
-
-/*======================================================================*/
-/* Calling convention and library support changes */
-
-/* Define how to generate (in the callee) the output value of a function
-   and how to find (in the caller) the value returned by a function.  VALTYPE
-   is the data type of the value (as a tree).  If the precise function being
-   called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
-   For A/UX generate the result in d0, a0, or fp0 as appropriate. */
-
-#undef FUNCTION_VALUE
-#define FUNCTION_VALUE(VALTYPE, FUNC)                                  \
-  (TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_68881                    \
-   ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16)                            \
-   : (POINTER_TYPE_P (VALTYPE)		                               \
-      ? gen_rtx (REG, TYPE_MODE (VALTYPE), 8)                           \
-      : gen_rtx (REG, TYPE_MODE (VALTYPE), 0)))
-                    
-#undef LIBCALL_VALUE
-#define LIBCALL_VALUE(MODE)						\
-  gen_rtx (REG, (MODE), ((TARGET_68881 &&				\
-			 ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0))
-
-/* 1 if N is a possible register number for a function value.
-   For A/UX allow d0, a0, or fp0 as return registers, for integral,
-   pointer, or floating types, respectively. Reject fp0 if not using a
-   68881 coprocessor. */
-
-#undef FUNCTION_VALUE_REGNO_P
-#define FUNCTION_VALUE_REGNO_P(N) \
-  ((N) == 0 || (N) == 8 || (TARGET_68881 && (N) == 16))
-
-/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
-   more than one register.  */
-
-#undef NEEDS_UNTYPED_CALL
-#define NEEDS_UNTYPED_CALL 1
-
-/* For compatibility with the large body of existing code which does not
-   always properly declare external functions returning pointer types, the
-   A/UX convention is to copy the value returned for pointer functions
-   from a0 to d0 in the function epilogue, so that callers that have
-   neglected to properly declare the callee can still find the correct return
-   value. */
-
-#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)				\
-{									\
-  extern int current_function_returns_pointer;				\
-  if ((current_function_returns_pointer) &&				\
-      ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode))	\
-    asm_fprintf (FILE, "\t%s %Ra0,%Rd0\n", ASM_MOV_INSN);		\
-}
-
-/* How to call the function profiler */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)				\
-  asm_fprintf (FILE, "\t%Olea %LLP%d,%Ra0\n\t%Ojbsr %s\n",		\
-	       (LABELNO), FUNCTION_PROFILER_SYMBOL)
-
-/* Finalize the trampoline by flushing the insn cache */
-
-#undef FINALIZE_TRAMPOLINE
-#define FINALIZE_TRAMPOLINE(TRAMP)					\
-  emit_library_call(gen_rtx(SYMBOL_REF, Pmode, "__clear_cache"),	\
-		    0, VOIDmode, 2, TRAMP, Pmode,			\
-		    plus_constant(TRAMP, TRAMPOLINE_SIZE), Pmode);
-
-/* Clear the instruction cache from `beg' to `end'.  This makes an 
-   inline system call to SYS_sysm68k.  The arguments are as follows:
-
-	sysm68k(105, addr, scope, cache, len)
-
-   105	  - the subfunction code to clear the cache
-   addr	  - the start address for the flush
-   scope  - the scope of the flush (see the cpush insn)
-   cache  - which cache to flush (see the cpush insn)
-   len    - a factor relating to the number of flushes to perform :
-   	    len/16 lines, or len/4096 pages.
-
-   While all this is only really relevant to 040's, the system call
-   will just return an error (which we ignore) on other systems.  */
-
-#define CLEAR_INSN_CACHE(beg, end)					\
-{									\
-    unsigned _beg = (unsigned)(beg), _end = (unsigned)(end);		\
-    unsigned _len = ((_end / 16) - (_beg / 16) + 1) * 16;		\
-    __asm __volatile(							\
-	    ASM_MOV_INSN " %1, %-\n\t"     /* nr lines */		\
-	    ASM_MOV_INSN " %#3, %-\n\t"	   /* insn+data caches */	\
-	    ASM_MOV_INSN " %#1, %-\n\t"	   /* clear lines */		\
-	    ASM_MOV_INSN " %0, %-\n\t"	   /* beginning of buffer */	\
-	    ASM_MOV_INSN " %#105, %-\n\t"  /* cache sub-function nr */	\
-	    ASM_MOV_INSN " %#0, %-\n\t"	   /* dummy return address */	\
-	    ASM_MOV_INSN " %#38, %/d0\n\t" /* system call nr */		\
-	    "trap %#0\n\t"						\
-	    "add%.l %#24, %/sp"						\
-	    : /* no outputs */						\
-	    : "g"(_beg), "g"(_len)					\
-	    : "%d0");							\
-}
diff --git a/gcc/config/m68k/altos3068.h b/gcc/config/m68k/altos3068.h
deleted file mode 100755
index 5903a12..0000000
--- a/gcc/config/m68k/altos3068.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Altos 3068 68020 version.
-   Copyright (C) 1988, 1989, 1993, 1996 Free Software Foundation, Inc.
-   Contributed by Jyrki Kuoppala <jkp@cs.hut.fi>
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "m68k/m68k.h"
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-/* 5 is without 68881.  Change to 7 if you have 68881 */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68020)
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-#endif
-
-/* Define __HAVE_68881__ in preprocessor,
-   according to the -m flags.
-   This will control the use of inline 68881 insns in certain macros.
-   Also inform the program which CPU this is for.  */
-
-#if TARGET_DEFAULT & MASK_68881
-
-/* -m68881 is the default */
-#define CPP_SPEC \
-"%{!msoft-float:-D__HAVE_68881__ }\
-%{!ansi:%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}}"
-
-#else
-
-/* -msoft-float is the default */
-#define CPP_SPEC \
-"%{m68881:-D__HAVE_68881__ }\
-%{!ansi:%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}}"
-
-#endif
-
-/* -m68000 requires special flags to the assembler.  */
-
-#define ASM_SPEC \
- "%{m68000:-mc68010}%{mc68000:-mc68010}%{!mc68000:%{!m68000:-mc68020}}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dmc68000 -DPORTAR -Dmc68k32 -Uvax -Dm68k -Dunix -Asystem(unix)  -Acpu(m68k) -Amachine(m68k)"
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* We use gnu assembler, linker and gdb, so we want DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Tell some conditionals we will use GAS.  Is this really used?  */
-
-#define USE_GAS
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)			\
-  do { char dstr[30];					\
-       REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", dstr);	\
-       fprintf (FILE, "\t.double 0r%s\n", dstr);	\
-     } while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)                    \
-  do { char dstr[30];					\
-       REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", dstr);	\
-       fprintf (FILE, "\t.single 0r%s\n", dstr);	\
-     } while (0)
-
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)		\
- do {								\
-      if (CODE == 'f')						\
-        {							\
-          char dstr[30];					\
-          REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr);		\
-	  fprintf (FILE, "#0r%s", dstr);			\
-        }							\
-      else							\
-        {							\
-          long l;						\
-          REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-          if (sizeof (int) == sizeof (long))			\
-            asm_fprintf ((FILE), "%I0x%x", l);			\
-          else							\
-            asm_fprintf ((FILE), "%I0x%lx", l);			\
-        }							\
-     } while (0)
-
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)		\
-  do { char dstr[30];					\
-       REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr);	\
-       fprintf (FILE, "#0r%s", dstr);			\
-     } while (0)
-
-/* Return pointer values in both d0 and a0.  */
-
-#undef FUNCTION_EXTRA_EPILOGUE
-#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)			\
-{								\
-  extern int current_function_returns_pointer;			\
-  if ((current_function_returns_pointer) && 			\
-      ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode))\
-    fprintf (FILE, "\tmovel d0,a0\n");				\
-}
diff --git a/gcc/config/m68k/amix.h b/gcc/config/m68k/amix.h
deleted file mode 100755
index 9b40a29..0000000
--- a/gcc/config/m68k/amix.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Commodore Amiga A3000UX version.
-
-   Copyright (C) 1991, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m68k/m68kv4.h"
-
-/* rhealey@aggregate.com says dots are no good either.  */
-#define NO_DOT_IN_LABEL
-
-/* Alter assembler syntax for fsgldiv and fsglmul.
-   It is highly likely that this is a generic SGS m68k assembler dependency.
-   If so, it should eventually be handled in the m68k/sgs.h ASM_OUTPUT_OPCODE
-   macro, like the other SGS assembler quirks.  -fnf */
-
-#define FSGLDIV_USE_S		/* Use fsgldiv.s, not fsgldiv.x */
-#define FSGLMUL_USE_S		/* Use fsglmul.s, not fsglmul.x */
-
-/* Names to predefine in the preprocessor for this target machine.  For the
-   Amiga, these definitions match those of the native AT&T compiler.  Note
-   that we override the definition in m68kv4.h, where SVR4 is defined and
-   AMIX isn't. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-  "-Dm68k -Dunix -DAMIX -D__svr4__ -D__motorola__ \
- -Amachine(m68k) -Acpu(m68k) -Asystem(unix) -Alint(off)"
-
-/* At end of a switch table, define LDnnn iff the symbol LInnn was defined.
-   Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
-   fails to assemble.  Luckily "Lnnn(pc,d0.l*2)" produces the results
-   we want.  This difference can be accommodated by making the assembler
-   define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
-   string, as necessary.  This is accomplished via the ASM_OUTPUT_CASE_END
-   macro. (the Amiga assembler has this bug) */
-
-#undef ASM_OUTPUT_CASE_END
-#define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE)				\
-do {									\
-  if (switch_table_difference_label_flag)				\
-    asm_fprintf ((FILE), "\t%s %LLD%d,%LL%d\n", SET_ASM_OP, (NUM), (NUM));\
-  switch_table_difference_label_flag = 0;				\
-} while (0)
-
-int switch_table_difference_label_flag;
-
-/* This says how to output assembler code to declare an
-   uninitialized external linkage data object.  Under SVR4,
-   the linker seems to want the alignment of data objects
-   to depend on their types.  We do exactly that here.
-   [This macro overrides the one in svr4.h because the amix assembler
-    has a minimum default alignment of 4, and will not accept any
-    explicit alignment smaller than this.  -fnf] */
-
-#undef ASM_OUTPUT_ALIGNED_COMMON
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fputs ("\t.comm\t", (FILE));						\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), ",%u,%u\n", (SIZE), MAX ((ALIGN) / BITS_PER_UNIT, 4)); \
-} while (0)
-
-/* This says how to output assembler code to declare an
-   uninitialized internal linkage data object.  Under SVR4,
-   the linker seems to want the alignment of data objects
-   to depend on their types.  We do exactly that here.
-   [This macro overrides the one in svr4.h because the amix assembler
-    has a minimum default alignment of 4, and will not accept any
-    explicit alignment smaller than this.  -fnf] */
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fprintf ((FILE), "\t%s\t%s,%u,%u\n",					\
-	   BSS_ASM_OP, (NAME), (SIZE), MAX ((ALIGN) / BITS_PER_UNIT, 4)); \
-} while (0)
-
-/* This definition of ASM_OUTPUT_ASCII is the same as the one in m68k/sgs.h,
-   which has been overridden by the one in svr4.h.  However, we can't use
-   the one in svr4.h because the amix assembler croaks on some of the
-   strings that it emits (such as .string "\"%s\"\n"). */
-
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)				\
-do {								\
-  register int sp = 0, lp = 0, ch;				\
-  fprintf ((FILE), "\t%s ", BYTE_ASM_OP);			\
-  do {								\
-    ch = (PTR)[sp];						\
-    if (ch > ' ' && ! (ch & 0x80) && ch != '\\')		\
-      {								\
-	fprintf ((FILE), "'%c", ch);				\
-      }								\
-    else							\
-      {								\
-	fprintf ((FILE), "0x%x", ch);				\
-      }								\
-    if (++sp < (LEN))						\
-      {								\
-	if ((sp % 10) == 0)					\
-	  {							\
-	    fprintf ((FILE), "\n\t%s ", BYTE_ASM_OP);		\
-	  }							\
-	else							\
-	  {							\
-	    putc (',', (FILE));					\
-	  }							\
-      }								\
-  } while (sp < (LEN));						\
-  putc ('\n', (FILE));						\
-} while (0)
-
-/* The following should be unnecessary as a result of PIC_CASE_VECTOR_ADDRESS.
-   But rhealey@aggregate.com says they are still needed.  */
-
-/* Override these for the sake of an assembler bug: the Amix
-   assembler can't handle .LC0@GOT syntax.  This pollutes the final
-   table for shared librarys but what's a poor soul to do; sigh... RFH */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  if (flag_pic && !strcmp(PREFIX,"LC"))			\
-    sprintf (LABEL, "*%s%%%d", PREFIX, NUM);		\
-  else							\
-    sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  if (flag_pic && !strcmp(PREFIX,"LC"))			\
-    asm_fprintf (FILE, "%s%%%d:\n", PREFIX, NUM);	\
-  else							\
-    asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM)
diff --git a/gcc/config/m68k/apollo68.h b/gcc/config/m68k/apollo68.h
deleted file mode 100755
index 8eed141..0000000
--- a/gcc/config/m68k/apollo68.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Apollo 680X0 version.
-   Copyright (C) 1989, 1992, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m68k/m68k.h"
-
-/* This symbol may be tested in other files for special Apollo handling */
-
-#define TM_APOLLO
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-/* Target switches for the Apollo is the same as in m68k.h, except
-   there is no Sun FPA. */
-
-#undef TARGET_SWITCHES
-#define TARGET_SWITCHES  \
-  { { "68020", 5},				\
-    { "c68020", 5},				\
-    { "68881", 2},				\
-    { "bitfield", 4},				\
-    { "68000", -5},				\
-    { "c68000", -5},				\
-    { "soft-float", -0102},			\
-    { "nobitfield", -4},			\
-    { "rtd", 8},				\
-    { "nortd", -8},				\
-    { "short", 040},				\
-    { "noshort", -040},				\
-    { "", TARGET_DEFAULT}}
-
-/* Define __HAVE_68881__ in preprocessor,
-   according to the -m flags.
-   This will control the use of inline 68881 insns in certain macros.
-   Also inform the program which CPU this is for.  */
-
-#if TARGET_DEFAULT & MASK_68881
-
-/* -m68881 is the default */
-#define CPP_SPEC \
-"%{!msoft-float:%{mfpa:-D__HAVE_FPA__ }%{!mfpa:-D__HAVE_68881__ }}\
-%{!ansi:%{m68000:-Dmc68010 }%{mc68000:-Dmc68010 }%{!mc68000:%{!m68000:-Dmc68020 }}\
-%{!ansi:-D_APOLLO_SOURCE}}"
-
-#else
-
-/* -msoft-float is the default */
-#define CPP_SPEC \
-"%{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }\
-%{!ansi:%{m68000:-Dmc68010 }%{mc68000:-Dmc68010 }%{!mc68000:%{!m68000:-Dmc68020 }}\
-%{!ansi:-D_APOLLO_SOURCE}}"
-
-#endif
-
-/* Names to predefine in the preprocessor for this target machine.  */
-/* These are the ones defined by Apollo, plus mc68000 for uniformity with
-   GCC on other 68000 systems.  */
-
-#define CPP_PREDEFINES "-Dapollo -Daegis -Dunix -Asystem(unix)  -Acpu(m68k) -Amachine(m68k)"
-
-/* cpp has to support a #sccs directive for the /usr/include files */
-
-#define SCCS_DIRECTIVE
-
-/* Allow #ident but output nothing for it.  */
-
-#define IDENT_DIRECTIVE
-#define ASM_OUTPUT_IDENT(FILE, NAME)
-
-/* -m68000 requires special flags to the assembler.  */
-
-#define ASM_SPEC \
- "%{m68000:-mc68010}%{mc68000:-mc68010}%{!mc68000:%{!m68000:-mc68020}}"
-
-/* STARTFILE_SPEC
-   Note that includes knowledge of the default specs for gcc, ie. no
-   args translates to the same effect as -m68881 */
-
-#if TARGET_DEFAULT & MASK_68881
-/* -m68881 is the default */
-#define STARTFILE_SPEC					\
-  "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-#else
-/* -msoft-float is the default */
-#define STARTFILE_SPEC					\
-  "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-#endif
-
-/* Specify library to handle `-a' basic block profiling.  */
-
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \
-%{a:/usr/lib/bb_link.o} "
-
-/* Debugging is not supported yet */
-
-#undef DBX_DEBUGGING_INFO
-#undef SDB_DEBUGGING_INFO
-
-/* We have atexit(2).  So C++ can use it for global destructors.  */
-
-#if 0 /* troy@cbme.unsw.edu.au says people are still using sr10.2
-	 and it does not support atexit.  */
-#define HAVE_ATEXIT
-#endif
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#undef STACK_BOUNDARY
-#define STACK_BOUNDARY 32
-
-/* Functions which return large structures get the address
-   to place the wanted value from a hidden parameter.  */
-
-#undef  PCC_STATIC_STRUCT_RETURN
-#undef  STRUCT_VALUE_REGNUM
-#define STRUCT_VALUE 0
-#define STRUCT_VALUE_INCOMING 0
-
-/* Specify how to pad function arguments.
-   Arguments are not padded at all; the stack is kept aligned on long
-   boundaries. */
-
-#define FUNCTION_ARG_PADDING(mode, size) none
-
-/* The definition of this macro imposes a limit on the size of
-   an aggregate object which can be treated as if it were a scalar
-   object.  */
-
-#define MAX_FIXED_MODE_SIZE    BITS_PER_WORD
-
-/* The definition of this macro implies that there are cases where
-   a scalar value cannot be returned in registers.
-   For Apollo, anything larger than one integer register is returned
-   using the structure-value mechanism, i.e. objects of DFmode are
-   returned that way. */
-
-#define RETURN_IN_MEMORY(type) \
-  (TYPE_MODE (type) == BLKmode \
-   || GET_MODE_SIZE (TYPE_MODE (type)) > UNITS_PER_WORD)
-
-/* In order to link with Apollo libraries, we can't prefix external
-   symbols with an underscore.  */
-
-#undef  USER_LABEL_PREFIX
-
-/* Use a prefix for local labels, just to be on the save side.  */
-
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX "."
-
-/* Use a register prefix to avoid clashes with external symbols (classic
-   example: `extern char PC;' in termcap).  */
-
-#undef REGISTER_PREFIX
-#define REGISTER_PREFIX "%"
-
-/* config/m68k.md has an explicit reference to the program counter,
-   prefix this by the register prefix.  */
-
-#define ASM_RETURN_CASE_JUMP    		\
-  do {						\
-    if (TARGET_5200)				\
-      return "ext%.l %0\n\tjmp %%pc@(2,%0:l)";	\
-    else					\
-      return "jmp %%pc@(2,%0:w)"		\
-  } while (0)
-
-/* Here are the new register names.  */
-
-#undef REGISTER_NAMES
-#ifndef SUPPORT_SUN_FPA
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",	\
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp",	\
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7" }
-#else /* SUPPORTED_SUN_FPA */
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",	\
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp",	\
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7", \
- "%fpa0", "%fpa1", "%fpa2", "%fpa3", "%fpa4", "%fpa5", "%fpa6", "%fpa7", \
- "%fpa8", "%fpa9", "%fpa10", "%fpa11", "%fpa12", "%fpa13", "%fpa14", "%fpa15", \
- "%fpa16", "%fpa17", "%fpa18", "%fpa19", "%fpa20", "%fpa21", "%fpa22", "%fpa23", \
- "%fpa24", "%fpa25", "%fpa26", "%fpa27", "%fpa28", "%fpa29", "%fpa30", "%fpa31" }
-#endif /* defined SUPPORT_SUN_FPA */
diff --git a/gcc/config/m68k/atari.h b/gcc/config/m68k/atari.h
deleted file mode 100755
index da0a803..0000000
--- a/gcc/config/m68k/atari.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Atari TT ASV version.
-   Copyright (C) 1994, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m68k/m68kv4.h"
-
-/* Dollars and dots in labels are not allowed. */
-
-#define NO_DOLLAR_IN_LABEL
-#define NO_DOT_IN_LABEL
-
-/* Alter assembler syntax for fsgldiv and fsglmul.
-   It is highly likely that this is a generic SGS m68k assembler dependency.
-   If so, it should eventually be handled in the m68k/sgs.h ASM_OUTPUT_OPCODE
-   macro, like the other SGS assembler quirks.  -fnf */
-
-#define FSGLDIV_USE_S		/* Use fsgldiv.s, not fsgldiv.x */
-#define FSGLMUL_USE_S		/* Use fsglmul.s, not fsglmul.x */
-
-/* At end of a switch table, define LDnnn iff the symbol LInnn was defined.
-   Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
-   fails to assemble.  Luckily "Lnnn(pc,d0.l*2)" produces the results
-   we want.  This difference can be accommodated by making the assembler
-   define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
-   string, as necessary.  This is accomplished via the ASM_OUTPUT_CASE_END
-   macro. (the Amiga assembler has this bug) */
-
-#undef ASM_OUTPUT_CASE_END
-#define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE)				\
-do {									\
-  if (switch_table_difference_label_flag)				\
-    asm_fprintf ((FILE), "\t%s %LLD%d,%LL%d\n", SET_ASM_OP, (NUM), (NUM));\
-  switch_table_difference_label_flag = 0;				\
-} while (0)
-
-int switch_table_difference_label_flag;
-
-/* This definition of ASM_OUTPUT_ASCII is the same as the one in m68k/sgs.h,
-   which has been overridden by the one in svr4.h.  However, we can't use
-   the one in svr4.h because the ASV assembler croaks on some of the
-   strings that it emits (such as .string "\"%s\"\n"). */
-
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)				\
-{								\
-  register int sp = 0, lp = 0, ch;				\
-  fprintf ((FILE), "\t%s ", BYTE_ASM_OP);				\
-  do {								\
-    ch = (PTR)[sp];						\
-    if (ch > ' ' && ! (ch & 0x80) && ch != '\\')		\
-      {								\
-	fprintf ((FILE), "'%c", ch);				\
-      }								\
-    else							\
-      {								\
-	fprintf ((FILE), "0x%x", ch);				\
-      }								\
-    if (++sp < (LEN))						\
-      {								\
-	if ((sp % 10) == 0)					\
-	  {							\
-	    fprintf ((FILE), "\n\t%s ", BYTE_ASM_OP);		\
-	  }							\
-	else							\
-	  {							\
-	    putc (',', (FILE));					\
-	  }							\
-      }								\
-  } while (sp < (LEN));						\
-  putc ('\n', (FILE));						\
-}
-
-/* Override these for the sake of an assembler bug: the ASV
-   assembler can't handle .LC0@GOT syntax.  This pollutes the final
-   table for shared librarys but what's a poor soul to do; sigh... RFH */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  if (flag_pic && !strcmp(PREFIX,"LC"))			\
-    sprintf (LABEL, "*%s%%%d", PREFIX, NUM);		\
-  else							\
-    sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  if (flag_pic && !strcmp(PREFIX,"LC"))			\
-    asm_fprintf (FILE, "%s%%%d:\n", PREFIX, NUM);	\
-  else							\
-    asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM)
diff --git a/gcc/config/m68k/aux-crt1.c b/gcc/config/m68k/aux-crt1.c
deleted file mode 100755
index 9ee529b..0000000
--- a/gcc/config/m68k/aux-crt1.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Startup code for A/UX
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with files
-   compiled with GCC to produce an executable, this does not cause
-   the resulting executable to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-/* This file is compiled three times to produce crt1.o, mcrt1.o, and
-   maccrt1.o.  The final two are created by defining MCRT1 and MACCRT1
-   respectively.  */
-
-#include <stdlib.h>
-#ifdef MCRT1
-#include <unistd.h>
-#include <mon.h>
-#endif
-
-/* Extern function declarations */
-
-extern void initfpu(void);
-extern void __istart(void);
-extern void __compatmode(void);
-extern void _cleanup(void);
-extern int main(int, char **, char **);
-extern void exit(int) __attribute__((noreturn));
-extern void _exit(int) __attribute__((noreturn));
-
-#ifdef MACCRT1
-extern void InitMac(void);
-#endif
-#ifdef MCRT1
-static void monitor_start(void);
-#endif
-
-/* Global variables */
-
-char **environ;
-char *__splimit;			/* address of top of stack */
-
-
-/* Initialize system and run */
-
-void _start() __attribute__((noreturn));
-void _start()
-{
-  register int *fp __asm__("%a6");
-  register char *d0 __asm__("%d0");
-  char **argv;
-  int argc;
-
-  __splimit = d0;
-  argc = fp[1];
-  argv = (char **)&fp[2];
-  environ = &argv[argc+1];
-
-  initfpu();
-  __istart();
-  __compatmode();
-
-  atexit(_cleanup);
-#ifdef MCRT1
-  monitor_start();
-#endif
-#ifdef MACCRT1
-  InitMac();
-#endif
-
-  exit(main(argc, argv, environ));
-}
-
-
-#ifdef MCRT1
-/* Start/Stop program monitor */
-
-extern void monitor(void *, void *, WORD *, int, int);
-
-static WORD *monitor_buffer;
-
-static void monitor_cleanup(void)
-{
-  monitor(NULL, NULL, NULL, 0, 0);
-  free(monitor_buffer);
-}
-
-static void monitor_start(void)
-{
-  extern int etext;
-  extern int stext __asm__(".text");
-
-  /* Choice of buffer size should be "no more than a few times
-     smaller than the program size" -- I don't believe that there
-     are any (useful) functions smaller than two insns (4 bytes)
-     so that is the scale factor used here */
-  int len = (&etext - &stext + 1) / 4;
-
-  monitor_buffer = (WORD *)calloc(len, sizeof(WORD));
-  if (monitor_buffer == NULL)
-    {
-      static const char msg[] = "mcrt1: could not allocate monitor buffer\n";
-      write(2, msg, sizeof(msg)-1);
-      _exit(-1);
-    }
-
-  /* I'm not sure why the count cap at 600 -- but that is what A/UX does */
-  monitor(&stext, &etext, monitor_buffer, len, 600);
-
-  atexit(monitor_cleanup);
-}
-#endif /* MCRT1 */
diff --git a/gcc/config/m68k/aux-crt2.asm b/gcc/config/m68k/aux-crt2.asm
deleted file mode 100755
index 062c16a..0000000
--- a/gcc/config/m68k/aux-crt2.asm
+++ /dev/null
@@ -1,42 +0,0 @@
-/* More startup code for A/UX */
-
-#include "tm.h"
-
-#ifdef USE_BIN_AS
-	file "crt2.s"
-
-/* The init section is used to support shared libraries */
-	init
-	global	__istart
-
-__istart:
-	link %fp,&-4
-#else
-	.file "crt2.s"
-
-/* The init section is used to support shared libraries */
-.section .init, "x"
-.even
-.globl __istart
-
-__istart:
-	link %fp,#-4
-
-#ifndef USE_COLLECT2
-/* The ctors and dtors sections are used to support COFF collection of 
-   c++ constructors and destructors */
-.section .ctors, "d"
-.even
-.globl __CTOR_LIST__
-
-__CTOR_LIST__:
-	.long -1
-
-.section .dtors, "d"
-.even
-.globl __DTOR_LIST__
-
-__DTOR_LIST__:
-	.long -1
-#endif /* USE_COLLECT2 */
-#endif /* USE_BIN_AS */
diff --git a/gcc/config/m68k/aux-crtn.asm b/gcc/config/m68k/aux-crtn.asm
deleted file mode 100755
index ce63d7f..0000000
--- a/gcc/config/m68k/aux-crtn.asm
+++ /dev/null
@@ -1,26 +0,0 @@
-/* More startup code for A/UX */
-
-#include "tm.h"
-
-#ifdef USE_BIN_AS
-	file	"crtn.s"
-
-	init
-
-	unlk %fp
-	rts
-#else
-	.file "crtn.s"
-
-.section .init, "x"
-	unlk %fp
-	rts
-
-#ifndef USE_COLLECT2
-.section .ctors, "d"
-	.long 0
-
-.section .dtors, "d"
-	.long 0
-#endif /* USE_COLLECT2 */
-#endif /* USE_BIN_AS */
diff --git a/gcc/config/m68k/aux-exit.c b/gcc/config/m68k/aux-exit.c
deleted file mode 100755
index fe06c77..0000000
--- a/gcc/config/m68k/aux-exit.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Generic atexit()
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with files
-   compiled with GCC to produce an executable, this does not cause
-   the resulting executable to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-/* Rather than come up with some ugly hack to make mcrt1 work, it is
-   better to just go ahead and provide atexit().  */
-
-
-#include <stdlib.h>
-
-
-void exit(int) __attribute__((noreturn));
-void _exit(int) __attribute__((noreturn));
-void _cleanup(void);
-
-
-#define FNS_PER_BLOCK	32
-
-struct atexit_fn_block
-{
-  struct atexit_fn_block *next;
-  void (*fns[FNS_PER_BLOCK])(void);
-  short used;
-};
-
-
-/* staticly allocate the first block */
-static struct atexit_fn_block atexit_fns;
-static struct atexit_fn_block *current_block = &atexit_fns;
-
-
-int atexit(void (*fn)(void))
-{
-  if (current_block->used >= FNS_PER_BLOCK)
-    {
-      struct atexit_fn_block *new_block = 
-	(struct atexit_fn_block *)malloc(sizeof(struct atexit_fn_block));
-      if (new_block == NULL)
-	return -1;
-
-      new_block->used = 0;
-      new_block->next = current_block;
-      current_block = new_block;
-    }
-
-  current_block->fns[current_block->used++] = fn;
-
-  return 0;
-}
-
-
-void exit(int status)
-{
-  struct atexit_fn_block *block = current_block, *old_block;
-  short i;
-
-  while (1)
-    {
-      for (i = block->used; --i >= 0 ;)
-	(*block->fns[i])();
-      if (block == &atexit_fns)
-	break;
-      /* I know what you are thinking -- we are about to exit, why free?
-	 Because it is friendly to memory leak detectors, that's why. */
-      old_block = block;
-      block = block->next;
-      free(old_block);
-    }
-
-  _exit(status);
-}
diff --git a/gcc/config/m68k/aux-low.gld b/gcc/config/m68k/aux-low.gld
deleted file mode 100755
index d1bb2a9..0000000
--- a/gcc/config/m68k/aux-low.gld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* GLD link script for building mac-compatible executables */
-
-OUTPUT_FORMAT("coff-m68k")
-
-SEARCH_DIR(@tooldir@/lib);
-SEARCH_DIR(@libdir@);
-SEARCH_DIR(/lib);
-SEARCH_DIR(/usr/lib);
-SEARCH_DIR(@local_prefix@/lib);
-
-ENTRY(_start)
-
-SECTIONS 
-{
-	.lowmem 0 (DSECT) : { 
-		/usr/lib/low.o (.data)
-	}
-	.text 0x10000000 : {
-		*(.text)
-		*(.init)
-		*(.fini)
-		etext = .;
-		_etext = .;
-	}
-	.data ALIGN(0x40000) : {
-		*(.data)
-		*(.ctors)
-		*(.dtors)
-		edata = .;
-		_edata = .;
-	}
-	.bss : {
-		*(.bss)
-		*(COMMON)
-		end = .;
-		_end = .;
-	}
-}
diff --git a/gcc/config/m68k/aux-mcount.c b/gcc/config/m68k/aux-mcount.c
deleted file mode 100755
index 1001c84..0000000
--- a/gcc/config/m68k/aux-mcount.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Profiling support code for A/UX 
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with files
-   compiled with GCC to produce an executable, this does not cause
-   the resulting executable to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-/* This routine is called at the beginning of functions compiled with -p
-   or -pg.  The A/UX libraries call mcount%, but gas cannot generate 
-   symbols with embedded percent signs.  Previous ports of GCC to A/UX 
-   have done things like (1) assemble a stub routine with the native
-   assembler, or (2) assemble a stub routine with gas and edit the object
-   file.  This solution has the advantage that it can interoperate with
-   the A/UX version and can be used in an eventual port of glibc to A/UX.  */
-
-#ifndef __GNUC__
-#error This file uses GNU C extensions
-#endif
-
-#include <mon.h>
-
-#ifdef IN_GCC
-#include "tm.h"
-#endif
-
-struct cnt *_countbase;
-
-#ifdef FUNCTION_PROFILER_SYMBOL
-void __mcount() __asm__(FUNCTION_PROFILER_SYMBOL);
-#endif
-
-void __mcount()
-{
-  register long **pfncnt __asm__("%a0");
-  register long *fncnt = *pfncnt;
-
-  if (!fncnt)
-    {
-      struct cnt *newcnt = _countbase++;
-      newcnt->fnpc = (char *)__builtin_return_address(0);
-      *pfncnt = fncnt = &newcnt->mcnt;
-    }
-  *fncnt += 1;
-}
diff --git a/gcc/config/m68k/auxas.h b/gcc/config/m68k/auxas.h
deleted file mode 100755
index 794df51..0000000
--- a/gcc/config/m68k/auxas.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/* Definitions for Motorola 680x0 running A/UX using /bin/as
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define USE_BIN_AS
-
-#ifndef USE_COLLECT2
-#define USE_COLLECT2
-#endif
-
-#ifndef __ASSEMBLY__
-
-#include "m68k/sgs.h"
-
-#define ASM_SPEC "%{m68030:-68030 }%{m68040:-68040 }"
-
-/* Modify AT&T SGS assembler syntax */
-/* A/UX's as doesn't do dots in pseudo-ops */
-
-#define SDB_DEBUGGING_INFO
-
-#define NO_DOLLAR_IN_LABEL
-#define NO_DOT_IN_LABEL
-
-#undef TEXT_SECTION_ASM_OP
-#define TEXT_SECTION_ASM_OP	"\ttext"
-
-#undef DATA_SECTION_ASM_OP
-#define DATA_SECTION_ASM_OP	"\tdata\t1"
-
-#undef BYTE_ASM_OP
-#define	BYTE_ASM_OP		"byte"
-
-#undef WORD_ASM_OP
-#define WORD_ASM_OP		"short"
-
-#undef LONG_ASM_OP
-#define LONG_ASM_OP		"long"
-
-#undef SPACE_ASM_OP
-#define SPACE_ASM_OP		"space"
-
-#undef ALIGN_ASM_OP
-#define ALIGN_ASM_OP		"align"
-
-#undef GLOBAL_ASM_OP
-#define GLOBAL_ASM_OP		"\tglobal"
-
-#undef SWBEG_ASM_OP
-#define SWBEG_ASM_OP		"swbeg"
-
-#undef SET_ASM_OP
-#define SET_ASM_OP		"set"
-
-#undef ASM_PN_FORMAT
-#define ASM_PN_FORMAT		"%s%%%d"
-
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX	"L%"
-
-#define ADDITIONAL_REGISTER_NAMES { "%a6", 14, "%a7", 15 }
-
-#undef ASM_OUTPUT_INT
-#define ASM_OUTPUT_INT(FILE,VALUE)                      \
-( fprintf ((FILE), "\t%s ", LONG_ASM_OP),               \
-  output_addr_const ((FILE), (VALUE)),                  \
-  fprintf ((FILE), "\n"))
-
-#undef ASM_OUTPUT_COMMON
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)	\
-( fputs ("\tcomm\t", (FILE)),				\
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
-( fputs ("\tlcomm\t", (FILE)),				\
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)				\
-  output_file_directive ((FILE), main_input_filename)
-
-#undef ASM_OUTPUT_SOURCE_FILENAME
-#define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME)		\
-( fputs ("\tfile\t", (FILE)),				\
-  output_quoted_string ((FILE), (NAME)),		\
-  fputc ('\n', (FILE)) )
-
-#undef ASM_OUTPUT_CASE_FETCH
-#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)	\
-    asm_fprintf (file, "10(%Rpc,%s.", regname)
-
-#define SGS_NO_LI
-
-/* Random macros describing parts of SDB data.  */
-
-#define PUT_SDB_SCL(a) \
-  fprintf(asm_out_file, "\tscl\t%d%s", (a), SDB_DELIM)
-
-#define PUT_SDB_INT_VAL(a) \
-  fprintf (asm_out_file, "\tval\t%d%s", (a), SDB_DELIM)
-
-#define PUT_SDB_VAL(a)				\
-( fputs ("\tval\t", asm_out_file),		\
-  output_addr_const (asm_out_file, (a)),	\
-  fprintf (asm_out_file, SDB_DELIM))
-
-#define PUT_SDB_DEF(a)				\
-do { fprintf (asm_out_file, "\tdef\t");		\
-     ASM_OUTPUT_LABELREF (asm_out_file, a); 	\
-     fprintf (asm_out_file, SDB_DELIM); } while (0)
-
-#define PUT_SDB_PLAIN_DEF(a) fprintf(asm_out_file,"\tdef\t~%s%s", a, SDB_DELIM)
-
-#define PUT_SDB_ENDEF fputs("\tendef\n", asm_out_file)
-
-#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\ttype\t0%o%s", a, SDB_DELIM)
-
-#define PUT_SDB_SIZE(a) fprintf(asm_out_file, "\tsize\t%d%s", a, SDB_DELIM)
-
-#define PUT_SDB_START_DIM fprintf(asm_out_file, "\tdim\t")
-
-#define PUT_SDB_NEXT_DIM(a) fprintf(asm_out_file, "%d,", a)
-
-#define PUT_SDB_LAST_DIM(a) fprintf(asm_out_file, "%d%s", a, SDB_DELIM)
-
-#define PUT_SDB_TAG(a)				\
-do { fprintf (asm_out_file, "\ttag\t");		\
-     ASM_OUTPUT_LABELREF (asm_out_file, a);	\
-     fprintf (asm_out_file, SDB_DELIM); } while (0)
-
-#define PUT_SDB_BLOCK_START(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~bb%s\tval\t~%s\tscl\t100%s\tline\t%d%s\tendef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_BLOCK_END(LINE)			\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~eb%s\tval\t~%s\tscl\t100%s\tline\t%d%s\tendef\n",  \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_FUNCTION_START(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~bf%s\tval\t~%s\tscl\t101%s\tline\t%d%s\tendef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_FUNCTION_END(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~ef%s\tval\t~%s\tscl\t101%s\tline\t%d%s\tendef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_EPILOGUE_END(NAME)			\
-do { fprintf (asm_out_file, "\tdef\t");			\
-     ASM_OUTPUT_LABELREF (asm_out_file, NAME);		\
-     fprintf (asm_out_file,				\
-	      "%s\tval\t~%s\tscl\t-1%s\tendef\n",	\
-	      SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
-
-#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
-  sprintf ((BUFFER), "~%dfake", (NUMBER));
-
-#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE)		\
-    fprintf((FILE), "\tln\t%d\n", 			\
-	    (sdb_begin_function_line > 1 ?		\
-	     last_linenum - sdb_begin_function_line : 1))
-
-#define ASM_MOV_INSN	"mov.l"
-
-#define FUNCTION_PROFILER_SYMBOL "mcount%"
-
-#endif /* !__ASSEMBLY__ */
diff --git a/gcc/config/m68k/auxgas.h b/gcc/config/m68k/auxgas.h
deleted file mode 100755
index c2e0d56..0000000
--- a/gcc/config/m68k/auxgas.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Definitions for Motorola 680x0 running A/UX using GAS
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define USE_GAS
-
-#ifndef __ASSEMBLY__
-
-#include "m68k/m68k.h"
-#include "m68k/coff.h"
-
-#define ASM_SPEC "%{m68000:-Am68000 }%{m68030:-Am68030 }%{m68040:-Am68040 }"
-
-/* Output #ident as a .ident.  */
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-
-#ifdef IDENTIFY_WITH_IDENT
-/* Put the GCC identification somewhere nicer, I think.
-   Does the COFF GDB use the "gcc2_complied." symbol anyway? */
-#define ASM_IDENTIFY_GCC(FILE) /* nothing */
-#define ASM_IDENTIFY_LANGUAGE(FILE) \
-  fprintf (FILE, "\t.ident \"GCC (%s) %s\"\n", lang_identify(), version_string)
-#endif
-
-#ifdef USE_COLLECT2
-#undef ASM_OUTPUT_CONSTRUCTOR
-#undef ASM_OUTPUT_DESTRUCTOR
-/* for the sake of link-level compatibility with /bin/as version */
-#define NO_DOLLAR_IN_LABEL
-#define NO_DOT_IN_LABEL
-#endif
-
-#define ADDITIONAL_REGISTER_NAMES  { "%fp", 14, "%a7", 15 }
-
-#define ASM_MOV_INSN	"movel"
-
-#define FUNCTION_PROFILER_SYMBOL "__mcount"
-
-#endif /* !__ASSEMBLY__ */
diff --git a/gcc/config/m68k/auxgld.h b/gcc/config/m68k/auxgld.h
deleted file mode 100755
index 12c97af..0000000
--- a/gcc/config/m68k/auxgld.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Definitions for Motorola 680x0 running A/UX using GLD
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define USE_GNU_LD
-
-#ifndef __ASSEMBLY__
-
-#define LINK_SPEC \
-"%{p:-L/lib/libp -L/usr/lib/libp }%{pg:-L/lib/libp -L/usr/lib/libp }\
-%{smac:-T low.gld%s }"
-
-#endif /* !__ASSEMBLY__ */
diff --git a/gcc/config/m68k/auxld.h b/gcc/config/m68k/auxld.h
deleted file mode 100755
index 932dd6a..0000000
--- a/gcc/config/m68k/auxld.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Definitions for Motorola 680x0 running A/UX using /bin/ld
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define USE_BIN_LD
-
-#ifndef USE_COLLECT2
-#define USE_COLLECT2
-#endif
-
-#ifndef __ASSEMBLY__
-
-#define LINK_SPEC \
-"%{p:-L/lib/libp -L/usr/lib/libp }%{pg:-L/lib/libp -L/usr/lib/libp }\
-%{smac:low.ld%s }%{!smac:shlib.ld%s }"
-
-#define SWITCHES_NEED_SPACES "o"
-
-#endif /* !__ASSEMBLY__ */
diff --git a/gcc/config/m68k/ccur-GAS.h b/gcc/config/m68k/ccur-GAS.h
deleted file mode 100755
index 685eb97..0000000
--- a/gcc/config/m68k/ccur-GAS.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Concurrent 68k version.
-   Copyright (C) 1987, 1988, 1995, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#ifndef MASSCOMP
-#define MASSCOMP
-#endif
-
-#ifndef CONCURRENT
-#define CONCURRENT
-#endif
-
-#ifndef __mc68000__
-#define __mc68000__
-#endif
-
-#ifndef __mc68020__
-#define __mc68020__
-#endif
-
-#define USE_GAS
-#define MOVE_RATIO 100
-
-#define SPACE_AFTER_L_OPTION
-#define SWITCHES_NEED_SPACES "oL"
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-#define TARGET_DEFAULT (MASK_68040|MASK_BITFIELD|MASK_68881|MASK_68020)
-
-#include "m68k/m68k.h"
-
-#define SIZE_TYPE "int"
-
-/* for 68k machines this only needs to be TRUE for the 68000 */
-
-#undef STRICT_ALIGNMENT     
-#define STRICT_ALIGNMENT 0
-
-/* Names to predefine in the preprocessor for this target machine.  */
-#define CPP_PREDEFINES \
-    "-Dmc68000 -Dmasscomp -DMASSCOMP -Dunix -DLANGUAGE_C -Dconcurrent -DCONCURRENT"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (68k, GNU GAS syntax)");
-
-/* Discard internal local symbols beginning with 'L'. */
-#define LINK_SPEC "-X"
-
-/* Every structure or union's size must be a multiple of 4 bytes. */
-#define STRUCTURE_SIZE_BOUNDARY 16 
-
-/* No data type wants to be aligned rounder than this.  */
-#undef BIGGEST_ALIGNMENT
-#define BIGGEST_ALIGNMENT 32
-
-/* Allocation boundary (in *bits*) for storing pointers in memory.  */
-#undef POINTER_BOUNDARY
-#define POINTER_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#undef EMPTY_FIELD_BOUNDARY
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Allocation boundary in bits for the code of a function */
-#undef  FUNCTION_BOUNDARY
-#define FUNCTION_BOUNDARY 32
-
-/* Make strings long-word aligned so dhrystones will run faster. */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
-   (TREE_CODE (EXP) == STRING_CST \
-    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* This is BSD, so it wants DBX format.  */
-#define DBX_DEBUGGING_INFO
-
-/* Override parts of m68k.h */
-
-#undef CALL_USED_REGISTERS
-#define CALL_USED_REGISTERS \
- {1, 1, 0, 0, 0, 0, 0, 0, \
-  1, 1, 0, 0, 0, 0, 0, 1, \
-  1, 1, 0, 0, 0, 0, 1, 1 }
-
-#undef REG_ALLOC_ORDER
-#define REG_ALLOC_ORDER \
-{  0,  1,  2,  3,  4,  5,  6,  7,\
-   8,  9, 10, 11, 12, 13, 14, 15, \
-  16, 17, 22, 23, 18, 19, 20, 21 }
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)	\
-  fprintf (FILE, "#NO_APP\n.globl fltused\n");
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-{ int _LOG = LOG;                       \
-  if (_LOG == 1)			\
-    fprintf (FILE, "\t.even\n");	\
-  else if (_LOG == 2)                   \
-    fprintf (FILE, "\t.align 4\n");     \
-  else if (_LOG != 0)			\
-    fprintf (FILE, "\t.align %d\n", _LOG);\
-}
-
-/* crt0.c should use the vax-bsd style of entry, with a dummy arg.  */
-
-#define CRT0_DUMMIES bogus_fp,
diff --git a/gcc/config/m68k/coff.h b/gcc/config/m68k/coff.h
deleted file mode 100755
index acd45e7..0000000
--- a/gcc/config/m68k/coff.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   m68k series COFF object files and debugging, version.
-   Copyright (C) 1994, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file is included after m68k.h by CPU COFF specific files.  It
-   is not a complete target itself.  */
-
-/* Generate sdb debugging information.  */
-
-#define SDB_DEBUGGING_INFO
-
-/* Output DBX (stabs) debugging information if using -gstabs.  */
-
-#include "dbxcoff.h"
-
-/* COFF symbols don't start with an underscore.  */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-
-/* Use a prefix for local labels, just to be on the save side.  */
-
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX "."
-
-/* Use a register prefix to avoid clashes with external symbols (classic
-   example: `extern char PC;' in termcap).  */
-
-#undef REGISTER_PREFIX
-#define REGISTER_PREFIX "%"
-
-/* In the machine description we can't use %R, because it will not be seen
-   by ASM_FPRINTF.  (Isn't that a design bug?).  */
-
-#undef REGISTER_PREFIX_MD
-#define REGISTER_PREFIX_MD "%%"
-
-/* config/m68k.md has an explicit reference to the program counter,
-   prefix this by the register prefix.  */
-
-#define ASM_RETURN_CASE_JUMP 			\
-  do {						\
-    if (TARGET_5200)				\
-      return "ext%.l %0\n\tjmp %%pc@(2,%0:l)";	\
-    else					\
-      return "jmp %%pc@(2,%0:w)";		\
-  } while (0)
-
-/* Here are the new register names.  */
-
-#undef REGISTER_NAMES
-#ifndef SUPPORT_SUN_FPA
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",	\
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp",	\
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7" }
-#else /* SUPPORTED_SUN_FPA */
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",	\
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp",	\
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7", \
- "%fpa0", "%fpa1", "%fpa2", "%fpa3", "%fpa4", "%fpa5", "%fpa6", "%fpa7", \
- "%fpa8", "%fpa9", "%fpa10", "%fpa11", "%fpa12", "%fpa13", "%fpa14", "%fpa15", \
- "%fpa16", "%fpa17", "%fpa18", "%fpa19", "%fpa20", "%fpa21", "%fpa22", "%fpa23", \
- "%fpa24", "%fpa25", "%fpa26", "%fpa27", "%fpa28", "%fpa29", "%fpa30", "%fpa31" }
-#endif /* defined SUPPORT_SUN_FPA */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
-  output_file_directive ((FILE), main_input_filename)
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as uninitialized global
-   data.  */
-
-#define BSS_SECTION_ASM_OP	".section\t.bss"
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of uninitialized global DECL named
-   NAME whose size is SIZE bytes and alignment is ALIGN bytes.
-   Try to use asm_output_aligned_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
-
-/* Support generic sections */
-
-#undef ASM_OUTPUT_SECTION_NAME
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
-  fprintf((FILE), ".section\t%s,\"%c\"\n", (NAME), \
-	  (DECL) && (TREE_CODE (DECL) == FUNCTION_DECL || \
-		     DECL_READONLY_SECTION (DECL, RELOC)) ? 'x' : 'd')
-
-/* Support the ctors and dtors sections for g++.  */
-
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"x\""
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"x\""
-
-/* A list of other sections which the compiler might be "in" at any
-   given time.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_ctors, in_dtors
-
-/* A list of extra section function definitions.  */
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-#define INT_ASM_OP ".long"
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* Don't assume anything about startfiles.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
diff --git a/gcc/config/m68k/crds.h b/gcc/config/m68k/crds.h
deleted file mode 100755
index 441b285..0000000
--- a/gcc/config/m68k/crds.h
+++ /dev/null
@@ -1,621 +0,0 @@
-/* Definitions of target machine for GNU compiler;
-   Charles River Data Systems UNiverse/32.
-   Copyright (C) 1987, 1993, 1994, 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Gary E. Miller (Gary_Edmunds_Miller@cup.portal.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MOTOROLA		/* Use Motorola syntax rather than "MIT" */
-#define SGS			/* Uses SGS assembler */
-#define SGS_SWITCH_TABLES	/* Different switch table handling */
-#define SGS_NO_LI		/* Suppress jump table label usage */
-#define CRDS			/* Charles River Data Systems assembler */
-
-#include "m68k/m68k.h"
-
-/* Without STRUCTURE_SIZE_BOUNDARY, we can't ensure that structures are
-   aligned such that we can correctly extract bitfields from them.
-   Someone should check whether the usual compiler on the crds machine
-   provides the equivalent behavior of STRUCTURE_SIZE_BOUNDARY.  */
-/* Set to 16 because all other m68k targets have it so */
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* See m68k.h.  0 means 680[01]0 with no 68881.  */
-
-#undef TARGET_DEFAULT
-#define	TARGET_DEFAULT 0
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* special flags to the unos assembler.  */
-
-#undef ASM_SPEC
-#define ASM_SPEC "-g"
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{!p:%{!pg:-lunos}}%{p:-lc_p}%{pg:-lc_p}"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC  \
-  "%{pg:gcrt0.o%s}%{!pg:%{p:mc68rt0.o%s}%{!p:c68rt0.o%s}}"
-
-/* CC1 spec */
-#if 0
-/* c.sac only used in _s_call_r() in libunos.a and malloc() in libmalloc.a */
-/* so we do not need to bother ! */
-#define CC1_SPEC "-fpcc-struct-return"
-#endif
-
-/* -O2 for MAX optimization */
-#undef CC1_SPEC
-#define CC1_SPEC "%{O2:-fstrength-reduce}"
-
-/* cpp has to support a #sccs directive for the /usr/include files */
-
-#define SCCS_DIRECTIVE
-
-/* Make output for SDB.  */
-
-/* #define SDB_DEBUGGING_INFO UNOS casm has no debugging :-( */
-
-/* UNOS need stack probe :-( */
-
-#if 0
-#define HAVE_probe 1
-#define gen_probe()  gen_rtx(ASM_INPUT, VOIDmode, "tstb -2048(sp)\t;probe\n")
-#else
-#undef NEED_PROBE
-#define NEED_PROBE (-2048)
-#endif
-
-/* use memcpy, memset instead of bcopy, etc. */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Don't try to define `gcc_compiled.' since the assembler might not
-   accept symbols with periods and GDB doesn't run on this machine anyway.  */
-#define ASM_IDENTIFY_GCC(FILE)
-
-/* Define __HAVE_68881__ in preprocessor if -m68881 is specified.
-   This will control the use of inline 68881 insns in certain macros.  */
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{m68881:-D__HAVE_68881__}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmc68k -DM68000 -Dmc68000 -Dunos -Dunix -D__motorola__ -Asystem(unix)  -Acpu(m68k) -Amachine(m68k)"
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-/* unos uses ".comm c.sac" returns &c.sac in d0 */
-/* make pointer to c.sac ?
-#undef STRUCT_VALUE_REGNUM
-#define STRUCT_VALUE gen_rtx(MEM, Pmode, gen_rtx( , , ) )
-*/
-
-#define BSS_SECTION_ASM_OP ".bss"
-
-/* Specify how to pad function arguments.
-   Value should be `upward', `downward' or `none'.
-   Same as the default, except no padding for large or variable-size args.  */
-
-#define FUNCTION_ARG_PADDING(MODE, TYPE)				\
-  (((MODE) == BLKmode							\
-    ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE))	== INTEGER_CST		\
-       && int_size_in_bytes (TYPE) < PARM_BOUNDARY / BITS_PER_UNIT)	\
-    : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY)				\
-   ? downward : none)
-
-/* Override parts of m68k.h to fit the CRuDS assembler.  */
-
-#undef TARGET_VERSION 
-#define TARGET_VERSION fprintf (stderr, " (68k, CRDS/UNOS)");
-
-/* Specify extra dir to search for include files.  */
-#define SYSTEM_INCLUDE_DIR "/include"
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)	\
-  fprintf (FILE, ";#NO_APP\n");
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#undef ASM_APP_ON
-#define ASM_APP_ON ";#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#undef ASM_APP_OFF 
-#define ASM_APP_OFF ";#NO_APP\n"
-
-/* The prefix for immediate operands.  */
-
-#undef IMMEDIATE_PREFIX
-#define IMMEDIATE_PREFIX "$"
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-do { long l[2];						\
-     REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l);		\
-     fprintf (FILE, "\t.long 0x%x, 0x%x\n", l[0], l[1]);	\
-   } while (0)
-
-/*unos has no .skip :-( */
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE)	 	\
-    fprintf (FILE, "\t. = . + %u\n", (SIZE));	
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-/* should use bss_section instead of data_section but this makes casm die ? */
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-{ data_section ();				\
-  if ((SIZE) > 1) fprintf (FILE, "\t.even\n");	\
-  assemble_name ((FILE), (NAME));		\
-  fprintf ((FILE), ":\t. = . + %u\n", (ROUNDED));}
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#undef ASM_OUTPUT_REG_PUSH
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tmovel %s,-(sp)\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#undef ASM_OUTPUT_REG_POP
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tmovel (sp)+,%s\n", reg_names[REGNO])
-
-#undef  ASM_OUTPUT_ASCII
-#define  ASM_OUTPUT_ASCII(FILE, P , SIZE)				\
-do {  int i;								\
-	  fprintf ((FILE), "\t.ascii \"");				\
-	  for (i = 0; i < (SIZE); i++)					\
-	    {								\
-	      register int c = (P)[i];					\
-	      if (i != 0 && (i / 200) * 200 == i)			\
-		fprintf ((FILE), "\"\n\t.ascii \"");			\
-	      if (c >= ' ' && c < 0177) {				\
-	        if (c != '\"' && c != '\\') {				\
-		  putc (c, (FILE));					\
-		  continue;						\
-	        }							\
-	       }							\
-	       /* brain dead asm doesn't understand char escapes */	\
-	       fprintf ((FILE), "\"\n\t.byte\t%d\n\t.ascii \"", c);	\
-	    }								\
-	  fprintf ((FILE), "\"\n");					\
- } while (0)
-
-
-/* Change all JBxx to Bxx.  Also change all DBRA to DBF.
-   Also change divs.l, etc., to divs, etc.  But don't change divsl.l.  */
-
-#define ASM_OUTPUT_OPCODE(FILE, PTR)			\
-{ if ((PTR)[0] == 'j' && (PTR)[1] == 'b')		\
-    { ++(PTR); }					\
-  else if ((PTR)[0] == 'd')				\
-    {							\
-      if (!strncmp ((PTR), "dbra", 4))			\
-	{ fprintf ((FILE), "dbf"); (PTR) += 4; }	\
-      else if (!strncmp ((PTR), "div", 3) && (PTR)[5] == ' ')  \
-	{ fprintf ((FILE), "div%c", (PTR)[3]); (PTR) += 6; }   \
-    }							\
-}
-
-
-#if 0
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.
-
-   On the 68000, we use several CODE characters:
-   '.' for dot needed in Motorola-style opcode names.
-   '-' for an operand pushing on the stack:
-       sp@-, -(sp) or -(%sp) depending on the style of syntax.
-   '+' for an operand pushing on the stack:
-       sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
-   '@' for a reference to the top word on the stack:
-       sp@, (sp) or (%sp) depending on the style of syntax.
-   '#' for an immediate operand prefix (# in MIT and Motorola syntax
-       but & in SGS syntax, $ in unos syntax).
-   '!' for the fpcr register (used in some float-to-fixed conversions).
-
-   'b' for byte insn (no effect, on the Sun; this is for the ISI).
-   'd' to force memory addressing to be absolute, not relative.
-   'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
-   'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
-       than directly).  Second part of 'y' below.
-   'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
-       or print pair of registers as rx:ry.
-   'y' for a FPA insn (print pair of registers as rx:ry).  This also outputs
-       CONST_DOUBLE's as SunFPA constant RAM registers if
-       possible, so it should not be used except for the SunFPA. */
-
-#undef PRINT_OPERAND_PUNCT_VALID_P
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)				\
-  ((CODE) == '.' || (CODE) == '#' || (CODE) == '-'			\
-   || (CODE) == '+' || (CODE) == '@' || (CODE) == '!')
-
-#undef PRINT_OPERAND
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ int i;								\
-  if (CODE == '.') ;							\
-  else if (CODE == '#') fprintf (FILE, "$");				\
-  else if (CODE == '-') fprintf (FILE, "-(sp)");			\
-  else if (CODE == '+') fprintf (FILE, "(sp)+");			\
-  else if (CODE == '@') fprintf (FILE, "(sp)");				\
-  else if (CODE == '!') fprintf (FILE, "fpcr");				\
-  else if (CODE == '/')							\
-    ;									\
-  else if (GET_CODE (X) == REG)						\
-    { if (REGNO (X) < 16 && (CODE == 'y' || CODE == 'x') && GET_MODE (X) == DFmode)	\
-        fprintf (FILE, "%s:%s", reg_names[REGNO (X)], reg_names[REGNO (X)+1]); \
-      else								\
-        fprintf (FILE, "%s", reg_names[REGNO (X)]);			\
-    }									\
-  else if (GET_CODE (X) == MEM)						\
-    {									\
-      output_address (XEXP (X, 0));					\
-      if (CODE == 'd' && ! TARGET_68020					\
-	  && CONSTANT_ADDRESS_P (XEXP (X, 0)))				\
-	/* fprintf (FILE, ".l") */;					\
-    }									\
-  else if ((CODE == 'y' || CODE == 'w')					\
-	   && GET_CODE(X) == CONST_DOUBLE				\
-	   && (i = standard_sun_fpa_constant_p (X)))			\
-    fprintf (FILE, "%%%d", i & 0x1ff);					\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode)	\
-    { REAL_VALUE_TYPE r; long l;					\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      if (CODE == 'f')							\
-	ASM_OUTPUT_FLOAT_OPERAND (CODE, FILE, r);			\
-      else								\
-        { REAL_VALUE_TO_TARGET_SINGLE (r, l);				\
-          fprintf (FILE, "$0x%x", l); } }				\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode)	\
-    { REAL_VALUE_TYPE r;						\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      ASM_OUTPUT_DOUBLE_OPERAND (FILE, r); }				\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == XFmode)	\
-    { REAL_VALUE_TYPE r;						\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      ASM_OUTPUT_LONG_DOUBLE_OPERAND (FILE, r); }			\
-  else { putc ('$', FILE); output_addr_const (FILE, X); }}
-#endif
-
-/* Note that this contains a kludge that knows that the only reason
-   we have an address (plus (label_ref...) (reg...))
-   is in the insn before a tablejump, and we know that m68k.md
-   generates a label LInnn: on such an insn.  */
-#undef PRINT_OPERAND_ADDRESS
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx reg1, reg2, breg, ireg;					\
-  register rtx addr = ADDR;						\
-  rtx offset;								\
-  switch (GET_CODE (addr))						\
-    {									\
-    case REG:								\
-      fprintf (FILE, "(%s)", reg_names[REGNO (addr)]);			\
-      break;								\
-    case PRE_DEC:							\
-      fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case POST_INC:							\
-      fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case PLUS:								\
-      reg1 = 0;	reg2 = 0;						\
-      ireg = 0;	breg = 0;						\
-      offset = 0;							\
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))				\
-	{								\
-	  offset = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))			\
-	{								\
-	  offset = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) != PLUS) ;					\
-      else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT		\
-	  || GET_CODE (addr) == SIGN_EXTEND)				\
-	{ if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; }	\
-      if (offset != 0) { if (addr != 0) abort (); addr = offset; }	\
-      if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND			\
-		    || GET_CODE (reg1) == MULT))			\
-	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))		\
-	{ breg = reg2; ireg = reg1; }					\
-      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))		\
-	{ breg = reg1; ireg = reg2; }					\
-      if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { int scale = 1;						\
-	  if (GET_CODE (ireg) == MULT)					\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (GET_CODE (ireg) == SIGN_EXTEND)				\
-	    fprintf (FILE, "L%d-LI%d-2(pc,%s.w",			\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (XEXP (ireg, 0))]); 		\
-	  else								\
-	    fprintf (FILE, "L%d-LI%d-2(pc,%s.l",			\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (ireg)]);				\
-	  if (scale != 1) fprintf (FILE, ":%d", scale);			\
-	  putc (')', FILE);						\
-	  break; }							\
-      if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { fprintf (FILE, "L%d-LI%d-2(pc,%s.l",				\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   reg_names[REGNO (breg)]);				\
-	  putc (')', FILE);						\
-	  break; }							\
-      if (ireg != 0 || breg != 0)					\
-	{ int scale = 1;						\
-	  if (breg == 0)						\
-	    abort ();							\
-	  if (addr && GET_CODE (addr) == LABEL_REF) abort ();		\
-	  if (addr != 0)						\
-	    output_addr_const (FILE, addr);				\
-	  fprintf (FILE, "(%s", reg_names[REGNO (breg)]);		\
-	  if (breg != 0 && ireg != 0)					\
-	    putc (',', FILE);						\
-	  if (ireg != 0 && GET_CODE (ireg) == MULT)			\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)		\
-	    fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);	\
-	  else if (ireg != 0)						\
-	    fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]);		\
-	  if (scale != 1) fprintf (FILE, ":%d", scale);			\
-	  putc (')', FILE);						\
-	  break;							\
-	}								\
-      else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF)		\
-	{ fprintf (FILE, "L%d-LI%d-2(pc,%s.l)",				\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   reg_names[REGNO (reg1)]);				\
-	  break; }							\
-    default:								\
-      if (GET_CODE (addr) == CONST_INT					\
-	  && INTVAL (addr) < 0x8000					\
-	  && INTVAL (addr) >= -0x8000)					\
-	fprintf (FILE, "%d", INTVAL (addr));				\
-      else								\
-        output_addr_const (FILE, addr);					\
-    }}
-
-#define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) \
-  do {	fprintf (FILE, "\t; file\t");			\
-	output_quoted_string (FILE, FILENAME);		\
-	fprintf (FILE, "\n");				\
-  } while (0)
-
-#define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO)	\
-  fprintf (FILE, "\t; ln\t%d\n",			\
-	   (sdb_begin_function_line		\
-	    ? last_linenum - sdb_begin_function_line : 1))
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-/* Note that the order of the bit mask for fmovem is the opposite
-   of the order for movem!  */
-
-#undef FUNCTION_PROLOGUE
-#define FUNCTION_PROLOGUE(FILE, SIZE)     \
-{ register int regno;						\
-  register int mask = 0;					\
-  extern char call_used_regs[];					\
-  int fsize = ((SIZE) + 3) & -4;				\
-  /* unos stack probe */					\
-  if ( fsize > 30000 ) {					\
-    fprintf (FILE, "\tmovel sp,a0\n");				\
-    fprintf (FILE, "\taddl $-%d,a0\n", 2048 + fsize);		\
-    fprintf (FILE, "\ttstb (a0)\n");				\
-  } else {							\
-    fprintf (FILE, "\ttstb -%d(sp)\n", 2048 + fsize);		\
-  }								\
-  if (frame_pointer_needed)					\
-    { if (TARGET_68020 || fsize < 0x8000)			\
-        fprintf (FILE, "\tlink a6,$%d\n", -fsize);		\
-      else							\
-	fprintf (FILE, "\tlink a6,$0\n\tsubl $%d,sp\n", fsize); }  \
-  else if (fsize)						      \
-    {								      \
-      /* Adding negative number is faster on the 68040.  */	      \
-      if (fsize + 4 < 0x8000)					      \
-	{							      \
-	  fprintf (FILE, "\tadd.w #%d,sp\n", - (fsize + 4));	      \
-	}							      \
-      else							      \
-	{							      \
-	  fprintf (FILE, "\tadd.l #%d,sp\n", - (fsize + 4));          \
-	}							      \
-    }								      \
-  for (regno = 16; regno < 24; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-       mask |= 1 << (regno - 16);				\
-  if ((mask & 0xff) != 0)					\
-    fprintf (FILE, "\tfmovem $0x%x,-(sp)\n", mask & 0xff);       \
-  mask = 0;							\
-  for (regno = 0; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-       mask |= 1 << (15 - regno);				\
-  if (frame_pointer_needed)					\
-    mask &= ~ (1 << (15-FRAME_POINTER_REGNUM));			\
-  if (exact_log2 (mask) >= 0)					\
-    fprintf (FILE, "\tmovel %s,-(sp)\n", reg_names[15 - exact_log2 (mask)]);  \
-  else if (mask) fprintf (FILE, "\tmovem $0x%x,-(sp)\n", mask); }
-
-/* Must put address in  %a0 , not  %d0 . -- LGM, 7/15/88 */
-/* UNOS ?? */
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABEL_NO)	\
-    fprintf (FILE, "\tmovl &LP%%%d,%%a0\n\tjsr mcount\n", (LABEL_NO))
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-#undef FUNCTION_EPILOGUE
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-{ register int regno;						\
-  register int mask, fmask;					\
-  register int nregs;						\
-  int offset, foffset, fpoffset;				\
-  extern char call_used_regs[];					\
-  int fsize = ((SIZE) + 3) & -4;				\
-  int big = 0;							\
-  nregs = 0;  fmask = 0; fpoffset = 0;				\
-  for (regno = 16; regno < 24; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      { nregs++; fmask |= 1 << (23 - regno); }			\
-  foffset = fpoffset + nregs * 12;				\
-  nregs = 0;  mask = 0;						\
-  if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \
-  for (regno = 0; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      { nregs++; mask |= 1 << regno; }				\
-  offset = foffset + nregs * 4;					\
-  if (offset + fsize >= 0x8000 					\
-      && frame_pointer_needed 					\
-      && (mask || fmask || fpoffset)) 				\
-    { fprintf (FILE, "\tmovel $%d,a0\n", -fsize);		\
-      fsize = 0, big = 1; }					\
-  if (exact_log2 (mask) >= 0) {					\
-    if (big)							\
-      fprintf (FILE, "\tmovel -%d(a6,a0.l),%s\n",		\
-	       offset + fsize, reg_names[exact_log2 (mask)]);	\
-    else if (! frame_pointer_needed)				\
-      fprintf (FILE, "\tmovel (sp)+,%s\n",			\
-	       reg_names[exact_log2 (mask)]);			\
-    else							\
-      fprintf (FILE, "\tmovel -%d(a6),%s\n",			\
-	       offset + fsize, reg_names[exact_log2 (mask)]); }	\
-  else if (mask) {						\
-    if (big)							\
-      fprintf (FILE, "\tmovem -%d(a6,a0.l),$0x%x\n",		\
-	       offset + fsize, mask);				\
-    else if (! frame_pointer_needed)				\
-      fprintf (FILE, "\tmovem (sp)+,$0x%x\n", mask);		\
-    else							\
-      fprintf (FILE, "\tmovem -%d(a6),$0x%x\n",		\
-	       offset + fsize, mask); }				\
-  if (fmask) {							\
-    if (big)							\
-      fprintf (FILE, "\tfmovem -%d(a6,a0.l),$0x%x\n",		\
-	       foffset + fsize, fmask);				\
-    else if (! frame_pointer_needed)				\
-      fprintf (FILE, "\tfmovem (sp)+,$0x%x\n", fmask);		\
-    else							\
-      fprintf (FILE, "\tfmovem -%d(a6),$0x%x\n",		\
-	       foffset + fsize, fmask); }			\
-  if (fpoffset != 0)						\
-    for (regno = 55; regno >= 24; regno--)			\
-      if (regs_ever_live[regno] && ! call_used_regs[regno]) {	\
-	if (big)						\
-	  fprintf(FILE, "\tfpmoved -%d(a6,a0.l), %s\n",	\
-		  fpoffset + fsize, reg_names[regno]);		\
-	else if (! frame_pointer_needed)			\
-	  fprintf(FILE, "\tfpmoved (sp)+, %s\n",			\
-		  reg_names[regno]);				\
-	else							\
-	  fprintf(FILE, "\tfpmoved -%d(a6), %s\n",		\
-		  fpoffset + fsize, reg_names[regno]);		\
-	fpoffset -= 8;						\
-      }								\
-  if (frame_pointer_needed)					\
-    fprintf (FILE, "\tunlk a6\n");				\
-  else if (fsize)                                                     \
-    {                                                                 \
-      if (fsize + 4 < 0x8000)                                         \
-	{                                                             \
-	  fprintf (FILE, "\tadd.w #%d,sp\n", fsize + 4);              \
-	}                                                             \
-      else                                                            \
-	{                                                             \
-	  fprintf (FILE, "\tadd.l #%d,sp\n", fsize + 4);              \
-	}                                                             \
-    }                                                                 \
-  if (current_function_pops_args)				\
-    fprintf (FILE, "\trtd $%d\n", current_function_pops_args);	\
-  else fprintf (FILE, "\trts\n"); }
-
diff --git a/gcc/config/m68k/ctix.h b/gcc/config/m68k/ctix.h
deleted file mode 100755
index 9c213fc..0000000
--- a/gcc/config/m68k/ctix.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Convergent Technologies MiniFrame version,
-   using GAS and binutils with COFF encapsulation.
-
-   Written by Ronald Cole
-
-   Because the MiniFrame's C compiler is so completely lobotomized,
-   bootstrapping this is damn near impossible!
-   Write to me for information on obtaining the binaries...
-
-   bug reports to csusac!unify!rjc@ucdavis.edu
-
-   Copyright (C) 1990 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m68k/3b1g.h"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmc68000 -Dmc68k -Dunix -Dctix -Asystem(unix)  -Acpu(m68k) -Amachine(m68k)"
-
-/* Where to look for robotussinized startfiles.  */
-#undef STANDARD_STARTFILE_PREFIX
-#define STANDARD_STARTFILE_PREFIX "/usr/local/lib/gnu/"
-
-/* Generate calls to the MiniFrame's library (for speed).  */
-#define DIVSI3_LIBCALL "ldiv"
-#define UDIVSI3_LIBCALL "uldiv"
-#define MODSI3_LIBCALL "lrem"
-#define UMODSI3_LIBCALL "ulrem"
-#define MULSI3_LIBCALL "lmul"
-#define UMULSI3_LIBCALL "ulmul"
diff --git a/gcc/config/m68k/dpx2.h b/gcc/config/m68k/dpx2.h
deleted file mode 100755
index b377974..0000000
--- a/gcc/config/m68k/dpx2.h
+++ /dev/null
@@ -1,822 +0,0 @@
-/* Definitions of target machine for GNU compiler.  
-   Bull DPX/2 200 and 300 systems (m68k, SysVr3).
-   Copyright (C) 1987, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Frederic Pierresteguy (F.Pierresteguy@frcl.bull.fr).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#ifndef USE_GAS
-#define MOTOROLA	   /* Use Motorola syntax rather than "MIT" */
-#define SGS_NO_LI	   /* Suppress jump table label usage */
-#define VERSADOS           /* This is the name of the assembler we have */
-#endif
-
-#include "m68k/m68k.h"
-#undef SELECT_RTX_SECTION
-#include "svr3.h"
-
-/* See m68k.h.  7 means 68020 with 68881.
- * We really have 68030 and 68882,
- * but this will get us going.  
- */
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-#define OBJECT_FORMAT_COFF
-#define NO_SYS_SIGLIST
-
-#ifdef CPP_PREDEFINES
-#undef CPP_PREDEFINES
-#endif
-/*
- * define all the things the compiler should
- */
-#ifdef ncl_mr
-# define CPP_PREDEFINES "-Dunix -Dbull -DDPX2 -DSVR3 -Dmc68000 -Dmc68020 -Dncl_mr=1 -D_BULL_SOURCE -D_POSIX_SOURCE -D_XOPEN_SOURCE -Asystem(unix) -Asystem(svr3)  -Acpu(m68k) -Amachine(m68k)"
-#else
-# ifdef ncl_el
-# define CPP_PREDEFINES "-Dunix -Dbull -DDPX2 -DSVR3 -Dmc68000 -Dmc68020 -Dncl_el -D_BULL_SOURCE -D_POSIX_SOURCE -D_XOPEN_SOURCE -Asystem(unix) -Asystem(svr3)  -Acpu(m68k) -Amachine(m68k)"
-# else
-#   define CPP_PREDEFINES "-Dunix -Dbull -DDPX2 -DSVR3 -Dmc68000 -Dmc68020 -D_BULL_SOURCE -D_POSIX_SOURCE -D_XOPEN_SOURCE -Asystem(unix) -Asystem(svr3)  -Acpu(m68k) -Amachine(m68k)"
-# endif
-#endif
-
-#undef	CPP_SPEC
-/*
- * you can't get a DPX/2 without a 68882 but allow it
- * to be ignored...
- */
-# define __HAVE_68881__ 1
-# define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__ }"
-
-#define HAVE_ATEXIT
-#undef DO_GLOBAL_CTORS_BODY		/* don't use svr3.h version */
-#undef DO_GLOBAL_DTORS_BODY
-
-#ifndef USE_GAS
-/*
- * handle the native MOTOROLA VERSAdos assembler.
- */
-
-/* See m68k.h.  3 means 68020 with 68881 and no bitfield
- * bitfield instructions do not seem to work a clean way.
- */
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_68881|MASK_68020)
-
-/* The native assembler doesn't support fmovecr.  */
-#define NO_ASM_FMOVECR
-
-#undef EXTRA_SECTIONS
-#undef EXTRA_SECTION_FUNCTIONS
-#undef READONLY_DATA_SECTION
-#define READONLY_DATA_SECTION data_section
-#undef SELECT_SECTION
-#undef SELECT_RTX_SECTION
-#define fini_section() while (0)
-
-#undef CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP "\tsection 15"
-#undef DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP "\tsection 15"
-#undef INIT_SECTION_ASM_OP
-#define BSS_SECTION_ASM_OP     "\tsection 14"
-#undef TEXT_SECTION_ASM_OP
-#define TEXT_SECTION_ASM_OP    "\tsection 10"
-#undef DATA_SECTION_ASM_OP
-#define DATA_SECTION_ASM_OP  "\tsection 15"
-
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Define if you don't want extended real, but do want to use the
-   software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion. */
-#define REAL_ARITHMETIC 
-
-#undef ASM_OUTPUT_SOURCE_FILENAME
-#define ASM_OUTPUT_SOURCE_FILENAME(FILE, NA)	\
-  do { fprintf ((FILE), "\t.file\t'%s'\n", (NA)); } while (0)
-
-/* Assembler pseudos to introduce constants of various size.  */
-
-#undef ASM_BYTE_OP
-#define ASM_BYTE_OP "\tdc.b"
-#undef ASM_LONG
-#define ASM_LONG "\tdc.l"
-
-/* 
- * we don't seem to support any of:
- * .globl
- * .even
- * .align
- * .ascii
- */
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\tdcb.b %u,0\n", (SIZE))
-
-#undef GLOBAL_ASM_OP 
-#define GLOBAL_ASM_OP "\txdef"
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) >= 1)			\
-    fprintf (FILE, "\tds.w 0\n");
-
-
-#define STRING_LIMIT	(0)
-#undef ASM_APP_ON
-#define ASM_APP_ON ""
-#undef ASM_APP_OFF
-#define ASM_APP_OFF ""
-/*
- * dc.b 'hello, world!'
- * dc.b 10,0
- * is how we have to output "hello, world!\n"
- */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(asm_out_file, p, thissize)		\
-  do { register int i, c, f=0, len=0;				\
-  for (i = 0; i < thissize; i++) { 				\
-    c = p[i];							\
-    if (c == '\'' || c < ' ' || c > 127) {			\
-      switch(f) {						\
-      case 0: /* need to output dc.b etc */			\
-	fprintf(asm_out_file, "\tdc.b %d", c);			\
-	f=1;							\
-	break;							\
-      case 1:							\
-	fprintf(asm_out_file, ",%d", c);			\
-	break;							\
-      default:							\
-	/* close a string */					\
-	fprintf(asm_out_file, "'\n\tdc.b %d", c);		\
-	f=1;							\
-	break;							\
-      }								\
-    } else {							\
-      switch(f) {						\
-      case 0:							\
-	fprintf(asm_out_file, "\tdc.b '%c", c);			\
-	f=2;							\
-	break;							\
-      case 2:							\
-        if (len >= 79) {					\
-          fprintf(asm_out_file, "'\n\tdc.b '%c", c); 	        \
-          len = 0; }						\
-        else							\
-	  fprintf(asm_out_file, "%c", c);			\
-	break;							\
-      default:							\
-	len = 0;						\
-	fprintf(asm_out_file, "\n\tdc.b '%c", c);		\
-	f=2;							\
-	break;							\
-      }								\
-    }								\
-    len++;                                   			\
-  }								\
-  if (f==2)							\
-    putc('\'', asm_out_file);					\
-  putc('\n', asm_out_file); } while (0)
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#undef ASM_OUTPUT_REG_PUSH
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tmove.l %s,-(sp)\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#undef ASM_OUTPUT_REG_POP
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tmove.l (sp)+,%s\n", reg_names[REGNO])
-
-
-#define PUT_SDB_FUNCTION_START(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\t.def\t.bf%s\t.val\t*%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_FUNCTION_END(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\t.def\t.ef%s\t.val\t*%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_BLOCK_START(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\t.def\t.bb%s\t.val\t*%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_BLOCK_END(LINE)			\
-  fprintf (asm_out_file,			\
-	   "\t.def\t.eb%s\t.val\t*%s\t.scl\t100%s\t.line\t%d%s\t.endef\n",  \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_EPILOGUE_END(NAME)	
-
-/* Output type in decimal not in octal as done in sdbout.c */	
-#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0%d%s", a, SDB_DELIM)
-		
-#undef FUNCTION_PROLOGUE
-#define FUNCTION_PROLOGUE(FILE, SIZE)                                 \
-{                                                                     \
-  register int regno;                                                 \
-  register int mask = 0;                                              \
-  int num_saved_regs = 0, first = 1;                                  \
-  extern char call_used_regs[];                                       \
-  int fsize = ((SIZE) + 3) & -4;                                      \
-                                                                      \
-                                                                      \
-  if (frame_pointer_needed)                                           \
-    {                                                                 \
-      /* Adding negative number is faster on the 68040.  */           \
-      if (fsize < 0x8000 && !TARGET_68040)                            \
-	{                                                             \
-	  fprintf (FILE, "\tlink %s,#%d\n", 	                      \
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);      \
-	}                                                             \
-      else if (TARGET_68020)                                          \
-	{                                                             \
-	  fprintf (FILE, "\tlink %s,#%d\n",	                      \
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);      \
-	}                                                             \
-      else                                                            \
-	{                                                             \
-	  fprintf (FILE, "\tlink %s,#0\n\tadd.l #%d,sp\n",	      \
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);      \
-	}							      \
-    }								      \
-  else if (fsize)						      \
-    {								      \
-      /* Adding negative number is faster on the 68040.  */	      \
-      if (fsize + 4 < 0x8000)					      \
-	{							      \
-	  fprintf (FILE, "\tadd.w #%d,sp\n", - (fsize + 4));	      \
-	}							      \
-      else							      \
-	{							      \
-	  fprintf (FILE, "\tadd.l #%d,sp\n", - (fsize + 4));          \
-	}							      \
-    }								      \
-  for (regno = 23; regno >= 16; regno--)                              \
-    if (regs_ever_live[regno] && ! call_used_regs[regno])             \
-      if (first) {						      \
-        fprintf (FILE, "\tfmovem.x %s", reg_names[regno]);            \
-	first = 0;						      \
-       }							      \
-      else fprintf (FILE, "/%s", reg_names[regno]);            	      \
-  if (!first) fprintf (FILE, ",-(sp)\n");			      \
-								      \
-  mask = 0;							      \
-  for (regno = 0; regno < 16; regno++)				      \
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	      \
-      {								      \
-        mask |= 1 << (15 - regno);				      \
-        num_saved_regs++;                   			      \
-      }                                                               \
-  if (frame_pointer_needed)                                           \
-    {                                                                 \
-      mask &= ~ (1 << (15 - FRAME_POINTER_REGNUM));                   \
-      num_saved_regs--;                                               \
-    }                                                                 \
-                                                                      \
-                                                                      \
-  if (num_saved_regs <= 2)                                            \
-    {                                                                 \
-      /* Store each separately in the same order moveml uses.         \
-         Using two movel instructions instead of a single moveml      \
-         is about 15% faster for the 68020 and 68030 at no expense    \
-         in code size */                                              \
-                                                                      \
-      int i;                                                          \
-                                                                      \
-      /* Undo the work from above. */                                 \
-      for (i = 0; i< 16; i++)                                         \
-        if (mask & (1 << i))                                          \
-          fprintf (FILE, "\tmove.l %s,-(sp)\n", reg_names[15 - i]);   \
-    }                                                                 \
-  else if (mask)                                                      \
-    {                                                                 \
-      first = 1;                                                      \
-      for (regno = 0; regno < 16; regno++)                            \
-        if (mask & (1 << regno))                                      \
-          if (first) {                                                \
-            fprintf (FILE, "\tmovem.l %s", reg_names[15 - regno]);    \
-            first = 0;                                                \
-           }                                                          \
-          else fprintf (FILE, "/%s", reg_names[15 - regno]);	      \
-      fprintf (FILE, ",-(sp)\n");	           		      \
-    }                                                                 \
-  if (flag_pic && current_function_uses_pic_offset_table)             \
-    {                                                                 \
-      fprintf (FILE, "\tmove.l #__GLOBAL_OFFSET_TABLE_, %s\n",        \
-		   reg_names[PIC_OFFSET_TABLE_REGNUM]);               \
-      fprintf (FILE, "\tlea.l (pc,%s.l),%s\n",                        \
-		   reg_names[PIC_OFFSET_TABLE_REGNUM],                \
-		   reg_names[PIC_OFFSET_TABLE_REGNUM]);               \
-    }                                                                 \
-}
-
-
-#undef FUNCTION_EPILOGUE
-#define FUNCTION_EPILOGUE(FILE, SIZE)                                 \
-{                                                                     \
-  register int regno;                                                 \
-  register int mask, fmask;                                           \
-  register int nregs;                                                 \
-  int offset, foffset, fpoffset, first = 1;		              \
-  extern char call_used_regs[];                                       \
-  int fsize = ((SIZE) + 3) & -4;                                      \
-  int big = 0;                                                        \
-  rtx insn = get_last_insn ();                                        \
-                                                                      \
-  /* If the last insn was a BARRIER, we don't have to write any code.  */ \
-  if (GET_CODE (insn) == NOTE)                                        \
-    insn = prev_nonnote_insn (insn);                                  \
-  if (insn && GET_CODE (insn) == BARRIER)                             \
-    {                                                                 \
-      /* Output just a no-op so that debuggers don't get confused     \
-	 about which function the pc is in at this address.  */       \
-      fprintf (FILE, "\tnop\n");                                      \
-      return;                                                         \
-    }                                                                 \
-                                                                      \
-  nregs = 0;  fmask = 0; fpoffset = 0;                                \
-  for (regno = 16; regno < 24; regno++)                               \
-    if (regs_ever_live[regno] && ! call_used_regs[regno])             \
-      {                                                               \
-        nregs++;                                                      \
-	fmask |= 1 << (23 - regno);                                   \
-      }                                                               \
-  foffset = fpoffset + nregs * 12;                                    \
-  nregs = 0;  mask = 0;                                               \
-  if (frame_pointer_needed)                                           \
-    regs_ever_live[FRAME_POINTER_REGNUM] = 0;                         \
-  for (regno = 0; regno < 16; regno++)                                \
-    if (regs_ever_live[regno] && ! call_used_regs[regno])             \
-      {                                                               \
-        nregs++;                                                      \
-	mask |= 1 << regno;                                           \
-      }                                                               \
-  offset = foffset + nregs * 4;                                       \
-  if (offset + fsize >= 0x8000                                        \
-      && frame_pointer_needed                                         \
-      && (mask || fmask || fpoffset))                                 \
-    {                                                                 \
-      fprintf (FILE, "\tmove.l #%d,a0\n", -fsize);                    \
-      fsize = 0, big = 1;                                             \
-    }                                                                 \
-  if (nregs <= 2)                                                     \
-    {                                                                 \
-      /* Restore each separately in the same order moveml does.       \
-         Using two movel instructions instead of a single moveml      \
-         is about 15% faster for the 68020 and 68030 at no expense    \
-         in code size. */                                             \
-                                                                      \
-      int i;                                                          \
-                                                                      \
-      /* Undo the work from above. */                                 \
-      for (i = 0; i< 16; i++)                                         \
-        if (mask & (1 << i))                                          \
-          {                                                           \
-            if (big)                                                  \
-	      {                                                       \
-		fprintf (FILE, "\tmove.l -%d(%s,a0.l),%s\n",          \
-			     offset + fsize,                          \
-			     reg_names[FRAME_POINTER_REGNUM],         \
-			     reg_names[i]);                           \
-	      }                                                       \
-            else if (! frame_pointer_needed)                          \
-	      {                                                       \
-		fprintf (FILE, "\tmove.l (sp)+,%s\n",                 \
-			     reg_names[i]);                           \
-	      }                                                       \
-            else                                                      \
-	      {                                                       \
-		fprintf (FILE, "\tmove.l -%d(%s),%s\n",               \
-			     offset + fsize,                          \
-			     reg_names[FRAME_POINTER_REGNUM],         \
-			     reg_names[i]);                           \
-	      }                                                       \
-            offset = offset - 4;                                      \
-          }                                                           \
-    }                                                                 \
-  else if (mask)                                                      \
-    {                                                                 \
-      first = 1;						      \
-      for (regno = 0; regno < 16; regno++)                            \
-        if (mask & (1 << regno))                                      \
-          if (first && big) {                                         \
-            fprintf (FILE, "\tmovem.l -%d(%s,a0.l),%s",               \
-		     offset + fsize,                                  \
-		     reg_names[FRAME_POINTER_REGNUM],                 \
-		     reg_names[regno]);                               \
-            first = 0;                                                \
-           }                                                          \
-          else if (first && ! frame_pointer_needed) {                 \
-            fprintf (FILE, "\tmovem.l (sp)+,%s",                      \
-		     offset + fsize,                                  \
-		     reg_names[FRAME_POINTER_REGNUM],                 \
-		     reg_names[regno]);                               \
-            first = 0;                                                \
-           }                                                          \
-          else if (first) {   				              \
-            fprintf (FILE, "\tmovem.l -%d(%s),%s",                    \
-		     offset + fsize,                                  \
-		     reg_names[FRAME_POINTER_REGNUM],                 \
-		     reg_names[regno]);                               \
-            first = 0;                                                \
-           }                                                          \
-          else  						      \
-	    fprintf (FILE, "/%s", reg_names[regno]);	              \
-      fprintf (FILE, "\n");	                 		      \
-    }                                                                 \
-  if (fmask)                                                          \
-    {                                                                 \
-      first = 1;						      \
-      for (regno = 16; regno < 24; regno++)                           \
-        if (fmask & (1 << (23 - regno)))                               \
-          if (first && big) {	                                      \
-            fprintf (FILE, "\tfmovem.x -%d(%s,a0.l),%s",              \
-		     foffset + fsize,                                 \
-		     reg_names[FRAME_POINTER_REGNUM],                 \
-		     reg_names[regno]);                               \
-	    first = 0;						      \
-           }                                                          \
-          else if (first && ! frame_pointer_needed) {                 \
-            fprintf (FILE, "\tfmovem.x (sp)+,%s",                     \
-		     foffset + fsize,                                 \
-		     reg_names[FRAME_POINTER_REGNUM],                 \
-		     reg_names[regno]);                               \
-	    first = 0;						      \
-           }                                                          \
-          else if (first) {    				              \
-            fprintf (FILE, "\tfmovem.x -%d(%s),%s",                   \
-		     foffset + fsize,                                 \
-		     reg_names[FRAME_POINTER_REGNUM],                 \
-		     reg_names[regno]);                               \
-	    first = 0;						      \
-           }                                                          \
-	  else fprintf (FILE, "/%s", reg_names[regno]); 	      \
-      fprintf (FILE, "\n");					      \
-    }                                                                 \
-  if (frame_pointer_needed)                                           \
-    fprintf (FILE, "\tunlk %s\n",                                     \
-	     reg_names[FRAME_POINTER_REGNUM]);                        \
-  else if (fsize)                                                     \
-    {                                                                 \
-      if (fsize + 4 < 0x8000)                                         \
-	{                                                             \
-	  fprintf (FILE, "\tadd.w #%d,sp\n", fsize + 4);              \
-	}                                                             \
-      else                                                            \
-	{                                                             \
-	  fprintf (FILE, "\tadd.l #%d,sp\n", fsize + 4);              \
-	}                                                             \
-    }                                                                 \
-  if (current_function_pops_args)                                     \
-    fprintf (FILE, "\trtd #%d\n", current_function_pops_args);        \
-  else                                                                \
-    fprintf (FILE, "\trts\n");                                        \
-}
-
-/* Translate Motorola opcodes such as `jbeq'
-   into VERSAdos opcodes such as `beq'.
-   Change `fbeq' to `fbseq', `fbne' to `fbsneq'.
-*/
-
-#undef ASM_OUTPUT_OPCODE
-#define ASM_OUTPUT_OPCODE(FILE, PTR)			\
-{ if ((PTR)[0] == 'j' && (PTR)[1] == 'b')		\
-    { ++(PTR);						\
-      while (*(PTR) != ' ')				\
-	{ putc (*(PTR), (FILE)); ++(PTR); }		\
-    }			                          	\
-  else if ((PTR)[0] == 'f')                             \
-    {                                                   \
-      if (!strncmp ((PTR), "fbeq", 4))                  \
-        { fprintf ((FILE), "fbseq"); (PTR) += 4; }      \
-      else if (!strncmp ((PTR), "fbne", 4))             \
-        { fprintf ((FILE), "fbsneq"); (PTR) += 4; }     \
-    }                                                   \
-  else if ((PTR)[0] == 'b' && (PTR)[1] == 'f')          \
-    {                                                   \
-      char *s;                                          \
-      if ((s = (char*)strchr ((PTR), '{')))             \
-	while (*s != '}') {                             \
-	  if (*s == 'b')                                \
-	    /* hack, I replace it with R ie nothing */  \
-	    *s = '0';                                   \
-	  s++; }					\
-    }                                                   \
-}
-
-/* This is how to output a `long double' extended real constant. */
-#undef ASM_OUTPUT_LONG_DOUBLE 
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE)  				\
-do { long l[3];								\
-     REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l);			\
-     if (sizeof (int) == sizeof (long))					\
-       fprintf (FILE, "\tdc.l $%x,$%x,$%x\n", l[0], l[1], l[2]);	\
-     else								\
-       fprintf (FILE, "\tdc.l $%lx,$%lx,$%lx\n", l[0], l[1], l[2]);	\
-   } while (0)
-
-#undef ASM_OUTPUT_DOUBLE
-#if 0
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-  do { char dstr[30];						\
-       REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr);		\
-       fprintf (FILE, "\tdc.d %s\n", dstr);	        	\
-     } while (0)
-#endif
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-do { long l[2];								\
-     REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l);			        \
-     fprintf (FILE, "\tdc.l $%x,$%x\n", l[0], l[1]);            	\
-   } while (0)
-
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-do { long l;						\
-     REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-     if (sizeof (int) == sizeof (long))			\
-       fprintf (FILE, "\tdc.l $%x\n", l);		\
-     else						\
-       fprintf (FILE, "\tdc.l $%lx\n", l);		\
-   } while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-#undef ASM_OUTPUT_INT 
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\tdc.l "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-#undef ASM_OUTPUT_SHORT
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\tdc.w "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#undef ASM_OUTPUT_CHAR
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\tdc.b "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-#undef ASM_OUTPUT_BYTE
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\tdc.b $%x\n", (VALUE))
-
-/* This is how to output an element of a case-vector that is absolute.
-   (The 68000 does not use such vectors,
-   but we must define this macro anyway.)  */
-#undef ASM_OUTPUT_ADDR_VEC_ELT
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  asm_fprintf (FILE, "\tdc.l %LL%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  asm_fprintf (FILE, "\tdc.w %LL%d-%LL%d\n", VALUE, REL)
-
-/* Currently, JUMP_TABLES_IN_TEXT_SECTION must be defined in order to
-   keep switch tables in the text section. */
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* Output a float value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)		\
- do {								\
-      if (CODE == 'f')						\
-        {							\
-          char dstr[30];					\
-          REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr);		\
-          asm_fprintf ((FILE), "%I%s", dstr);			\
-        }							\
-      else							\
-        {							\
-          long l;						\
-          REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-          if (sizeof (int) == sizeof (long))			\
-            asm_fprintf ((FILE), "%I$%x", l);			\
-          else							\
-            asm_fprintf ((FILE), "%I$%lx", l);			\
-        }							\
-     } while (0)
-
-/* Output a double value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-#undef ASM_OUTPUT_DOUBLE_OPERAND 
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)				\
- do { char dstr[30];							\
-      REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr);			\
-      asm_fprintf (FILE, "%I%s", dstr);					\
-    } while (0)
-
-/* Note, long double immediate operands are not actually
-   generated by m68k.md.  */
-#undef ASM_OUTPUT_LONG_DOUBLE_OPERAND
-#define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE)			\
- do { char dstr[30];							\
-      REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr);			\
-      asm_fprintf (FILE, "%I%s", dstr);					\
-    } while (0)
-
-#undef ASM_OUTPUT_COMMON
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\t.comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
-  do {							\
-    int align = exact_log2 (ROUNDED);			\
-    /*fprintf ((FILE), "\tsection 14\n");  */               \
-    data_section ();					\
-    ASM_OUTPUT_ALIGN ((FILE), align)                    \
-    ASM_OUTPUT_LABEL ((FILE), (NAME));			\
-    fprintf ((FILE), "\tdcb.b %u,0\n", (ROUNDED));	\
-    /* fprintf ((FILE), "\tsection 10\n"); */             \
-  } while (0)
-
-#undef PRINT_OPERAND_ADDRESS
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx reg1, reg2, breg, ireg;					\
-  register rtx addr = ADDR;						\
-  rtx offset;								\
-  switch (GET_CODE (addr))						\
-    {									\
-    case REG:								\
-      fprintf (FILE, "(%s)", reg_names[REGNO (addr)]);			\
-      break;								\
-    case PRE_DEC:							\
-      fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case POST_INC:							\
-      fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case PLUS:								\
-      reg1 = 0;	reg2 = 0;						\
-      ireg = 0;	breg = 0;						\
-      offset = 0;							\
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))				\
-	{								\
-	  offset = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))			\
-	{								\
-	  offset = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) != PLUS) ;					\
-      else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT		\
-	  || GET_CODE (addr) == SIGN_EXTEND)				\
-	{ if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; }	\
-/*  for OLD_INDEXING							\
-      else if (GET_CODE (addr) == PLUS)					\
-	{								\
-	  if (GET_CODE (XEXP (addr, 0)) == REG)				\
-	    {								\
-	      reg2 = XEXP (addr, 0);					\
-	      addr = XEXP (addr, 1);					\
-	    }								\
-	  else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	    {								\
-	      reg2 = XEXP (addr, 1);					\
-	      addr = XEXP (addr, 0);					\
-	    }								\
-	}								\
-  */									\
-      if (offset != 0) { if (addr != 0) abort (); addr = offset; }	\
-      if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND			\
-		    || GET_CODE (reg1) == MULT))			\
-	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))		\
-	{ breg = reg2; ireg = reg1; }					\
-      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))		\
-	{ breg = reg1; ireg = reg2; }					\
-      if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { int scale = 1;						\
-	  if (GET_CODE (ireg) == MULT)					\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (GET_CODE (ireg) == SIGN_EXTEND)				\
-	    fprintf (FILE, "(.L%d,pc,%s.w",				\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (XEXP (ireg, 0))]); 		\
-	  else								\
-	    fprintf (FILE, "(.L%d,pc,%s.l",				\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (ireg)]);				\
-	  if (scale != 1) fprintf (FILE, "*%d", scale);			\
-	  putc (')', FILE);						\
-	  break; }							\
-	if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF      \
-	    && ! (flag_pic && breg == pic_offset_table_rtx))            \
-	  {                                                             \
-	    fprintf (FILE, "(.L%d,pc,%s.l", 	                        \
-			 CODE_LABEL_NUMBER (XEXP (addr, 0)),            \
-			 reg_names[REGNO (breg)]);                      \
-	    putc (')', FILE);                                           \
-	    break; }                                                    \
-      if (ireg != 0 || breg != 0)					\
-	{ int scale = 1;						\
-	  if (breg == 0)						\
-	    abort ();							\
-          putc ('(', FILE); 	     				        \
-	  if (addr != 0)						\
-	    {                                                           \
-	      output_addr_const (FILE, addr);				\
-	      putc (',', FILE); 					\
-	    }    							\
-	  fprintf (FILE, "%s", reg_names[REGNO (breg)]);		\
-	  if (ireg != 0)						\
-	    putc (',', FILE);						\
-	  if (ireg != 0 && GET_CODE (ireg) == MULT)			\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)		\
-	    fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);	\
-	  else if (ireg != 0)						\
-	    fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]);		\
-	  if (scale != 1) fprintf (FILE, "*%d", scale);			\
-	  putc (')', FILE);						\
-	  break;							\
-	}								\
-      else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF)		\
-	{ fprintf (FILE, "(.L%d,pc,%s.w)",				\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   reg_names[REGNO (reg1)]);				\
-	  break; }							\
-    default:								\
-      if (GET_CODE (addr) == CONST_INT					\
-	  && INTVAL (addr) < 0x8000					\
-	  && INTVAL (addr) >= -0x8000)					\
-	fprintf (FILE, "%d.w", INTVAL (addr));				\
-      else								\
-        output_addr_const (FILE, addr);					\
-    }}
-
-
-#endif /* ! use gas */			
diff --git a/gcc/config/m68k/dpx2.ifile b/gcc/config/m68k/dpx2.ifile
deleted file mode 100755
index 2c8acd8..0000000
--- a/gcc/config/m68k/dpx2.ifile
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- *      dpx2.ifile - for collectless G++ on Bull DPX/2
- *	
- *      Peter Schauer <Peter.Schauer@regent.e-technik.tu-muenchen.dbp.de>
- *
- *      Install this file as $prefix/gcc-lib/dpx2/VERSION/gcc.ifile
- *	and comment out the lines referring to COLLECT at the top
- *      of Makefile before building GCC.
- *	
- *      This file has been tested with gcc-2.2.2 on a DPX/2 340
- *      running BOS 2.00.45, if it doesn't work for you, stick
- *      with collect.
- *	--sjg
- */
-/*
- *	Ifile to link with memory configured at 0.
- *	BLOCK to an offset that leaves room for many headers ( the value
- *	here allows for a file header, an outheader, and up to 11 section 
- *	headers on most systems.
- *	BIND to an address that excludes page 0 from being mapped. The value
- *	used for BLOCK should be or'd into this value. Here I'm setting BLOCK
- *	to 0x200 and BIND to ( 0x100000 | value_used_for(BLOCK) )
- *	If you are using shared libraries, watch that you don't overlap the
- *	address ranges assigned for shared libs.
- *
- *	GROUP BIND to a location in the next segment.  Here, the only value
- *	that you should change (I think) is that within NEXT, which I've set
- *	to my hardware segment size. You can always use a larger size, but not
- *	a smaller one.
- */
-SECTIONS
-{
-	.text BIND(0x100200) BLOCK (0x200) :
-	{
-		 /* plenty of room for headers */
-		*(.init)
-		*(.text)
-		_vfork = _fork; /* I got tired of editing peoples sloppy code */
-		*(.fini)
-	}
-	GROUP BIND( NEXT(0x100000) + (ADDR(.text) + (SIZEOF(.text)) % 0x1000)):
-	{
-			.data : {
-				___CTOR_LIST__ = . ; 
-				. += 4 ;	/* leading NULL */
-				*(.ctor) 
-				. += 4 ;	/* trailing NULL */
-				___DTOR_LIST__ = . ;
-				. += 4 ;	/* leading NULL */
-				*(.dtor) 
-				. += 4 ; 	/* trailing NULL */
-			 }
-			.bss : { }
-	}
-}
diff --git a/gcc/config/m68k/dpx2cdbx.h b/gcc/config/m68k/dpx2cdbx.h
deleted file mode 100755
index 88a180e..0000000
--- a/gcc/config/m68k/dpx2cdbx.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Definitions for Bull dpx/2 200 and 300 with gas
-   using dbx-in-coff encapsulation.
-   Copyright (C) 1992, 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "m68k/dpx2g.h"
-
-/* Use STABS debugging information inside COFF.  */
-#ifndef DBX_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-#endif
-
-/* Let sbd debugging be the default.  */
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
diff --git a/gcc/config/m68k/dpx2g.h b/gcc/config/m68k/dpx2g.h
deleted file mode 100755
index ea5cd13..0000000
--- a/gcc/config/m68k/dpx2g.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * dpx2g.h - Bull DPX/2 200 and 300 systems (m68k, SysVr3) with gas
- */
-
-#define USE_GAS
-#include "m68k/dpx2.h"
-
-#if 0 /* #ifndef USE_COLLECT2 */
-
-/* We use set vectors for the constructors/destructors. */ 
-
-#undef ASM_OUTPUT_CONSTRUCTOR
-#undef ASM_OUTPUT_DESTRUCTOR
-
-/* Although the gas we use can create .ctor and .dtor sections from N_SETT
-   stabs, it does not support section directives, so we need to have the loader
-   define the lists.
- */
-#define CTOR_LISTS_DEFINED_EXTERNALLY
-
-/* similar to default, but allows for the table defined by ld with gcc.ifile. 
-   nptrs is always 0.  So we need to instead check that __DTOR_LIST__[1] != 0.
-   The old check is left in so that the same macro can be used if and when  
-   a future version of gas does support section directives. */
-
-#define DO_GLOBAL_DTORS_BODY {int nptrs = *(int *)__DTOR_LIST__; int i; \
-  if (nptrs == -1 || (__DTOR_LIST__[0] == 0 && __DTOR_LIST__[1] != 0))  \
-    for (nptrs = 0; __DTOR_LIST__[nptrs + 1] != 0; nptrs++); 		\
-  for (i = nptrs; i >= 1; i--)						\
-    __DTOR_LIST__[i] (); }
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{!r:gcc.ifile%s}\
-   %{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}\
-  huge.o%s"
-
-#endif /* !USE_COLLECT2 */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}\
-  huge.o%s"
-
-
-/*
- * we are using GAS
- */
-#undef EXTRA_SECTION_FUNCTIONS
-#undef EXTRA_SECTIONS
-/* Gas understands dollars in labels. */
-#undef NO_DOLLAR_IN_LABEL
-/* GAS does not understand .ident so don't output anything for #ident.  */
-#undef ASM_OUTPUT_IDENT
-
-#undef ASM_LONG
-#define ASM_LONG "\t.long"
-
-/*
- * put const's in the text section
- */
-#define const_section()  text_section()
-#define fini_section() while (0)
-			       
-#undef CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP "\t.data"
-#undef DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP "\t.data"
-#undef INIT_SECTION_ASM_OP
-
-/* end of dpx2g.h */
diff --git a/gcc/config/m68k/fpgnulib.c b/gcc/config/m68k/fpgnulib.c
deleted file mode 100755
index 0559b62..0000000
--- a/gcc/config/m68k/fpgnulib.c
+++ /dev/null
@@ -1,442 +0,0 @@
-/* This is a stripped down version of floatlib.c.  It supplies only those
-   functions which exist in libgcc, but for which there is not assembly
-   language versions in m68k/lb1sf68.asm.
-
-   It also includes simplistic support for extended floats (by working in
-   double precision).  You must compile this file again with -DEXTFLOAT
-   to get this support.  */
-
-/*
-** gnulib support for software floating point.
-** Copyright (C) 1991 by Pipeline Associates, Inc.  All rights reserved.
-** Permission is granted to do *anything* you want with this file,
-** commercial or otherwise, provided this message remains intact.  So there!
-** I would appreciate receiving any updates/patches/changes that anyone
-** makes, and am willing to be the repository for said changes (am I
-** making a big mistake?).
-**
-** Pat Wood
-** Pipeline Associates, Inc.
-** pipeline!phw@motown.com or
-** sun!pipeline!phw or
-** uunet!motown!pipeline!phw
-**
-** 05/01/91 -- V1.0 -- first release to gcc mailing lists
-** 05/04/91 -- V1.1 -- added float and double prototypes and return values
-**                  -- fixed problems with adding and subtracting zero
-**                  -- fixed rounding in truncdfsf2
-**                  -- fixed SWAP define and tested on 386
-*/
-
-/*
-** The following are routines that replace the gnulib soft floating point
-** routines that are called automatically when -msoft-float is selected.
-** The support single and double precision IEEE format, with provisions
-** for byte-swapped machines (tested on 386).  Some of the double-precision
-** routines work at full precision, but most of the hard ones simply punt
-** and call the single precision routines, producing a loss of accuracy.
-** long long support is not assumed or included.
-** Overall accuracy is close to IEEE (actually 68882) for single-precision
-** arithmetic.  I think there may still be a 1 in 1000 chance of a bit
-** being rounded the wrong way during a multiply.  I'm not fussy enough to
-** bother with it, but if anyone is, knock yourself out.
-**
-** Efficiency has only been addressed where it was obvious that something
-** would make a big difference.  Anyone who wants to do this right for
-** best speed should go in and rewrite in assembler.
-**
-** I have tested this only on a 68030 workstation and 386/ix integrated
-** in with -msoft-float.
-*/
-
-/* the following deal with IEEE single-precision numbers */
-#define EXCESS		126L
-#define SIGNBIT		0x80000000L
-#define HIDDEN		(1L << 23L)
-#define SIGN(fp)	((fp) & SIGNBIT)
-#define EXP(fp)		(((fp) >> 23L) & 0xFF)
-#define MANT(fp)	(((fp) & 0x7FFFFFL) | HIDDEN)
-#define PACK(s,e,m)	((s) | ((e) << 23L) | (m))
-
-/* the following deal with IEEE double-precision numbers */
-#define EXCESSD		1022
-#define HIDDEND		(1L << 20L)
-#define EXPDBITS	11
-#define EXPDMASK	0x7FF
-#define EXPD(fp)	(((fp.l.upper) >> 20L) & 0x7FFL)
-#define SIGND(fp)	((fp.l.upper) & SIGNBIT)
-#define MANTD(fp)	(((((fp.l.upper) & 0xFFFFF) | HIDDEND) << 10) | \
-				(fp.l.lower >> 22))
-#define MANTDMASK	0xFFFFF /* mask of upper part */
-
-/* the following deal with IEEE extended-precision numbers */
-#define EXCESSX		16382
-#define HIDDENX		(1L << 31L)
-#define EXPXBITS	15
-#define EXPXMASK	0x7FFF
-#define EXPX(fp)	(((fp.l.upper) >> 16) & EXPXMASK)
-#define SIGNX(fp)	((fp.l.upper) & SIGNBIT)
-#define MANTXMASK	0x7FFFFFFF /* mask of upper part */
-
-union double_long 
-{
-  double d;
-  struct {
-      long upper;
-      unsigned long lower;
-    } l;
-};
-
-union float_long {
-  float f;
-  long l;
-};
-
-union long_double_long
-{
-  long double ld;
-  struct
-    {
-      long upper;
-      unsigned long middle;
-      unsigned long lower;
-    } l;
-};
-
-#ifndef EXTFLOAT
-
-/* convert int to double */
-double
-__floatsidf (int a1)
-{
-  long sign = 0, exp = 31 + EXCESSD;
-  union double_long dl;
-
-  if (!a1)
-    {
-      dl.l.upper = dl.l.lower = 0;
-      return dl.d;
-    }
-
-  if (a1 < 0)
-    {
-      sign = SIGNBIT;
-      a1 = -a1;
-      if (a1 < 0)
-	{
-	  dl.l.upper = SIGNBIT | ((32 + EXCESSD) << 20L);
-	  dl.l.lower = 0;
-	  return dl.d;
-        }
-    }
-
-  while (a1 < 0x1000000)
-    {
-      a1 <<= 4;
-      exp -= 4;
-    }
-
-  while (a1 < 0x40000000)
-    {
-      a1 <<= 1;
-      exp--;
-    }
-
-  /* pack up and go home */
-  dl.l.upper = sign;
-  dl.l.upper |= exp << 20L;
-  dl.l.upper |= (a1 >> 10L) & ~HIDDEND;
-  dl.l.lower = a1 << 22L;
-
-  return dl.d;
-}
-
-/* convert int to float */
-float
-__floatsisf (int l)
-{
-  double foo = __floatsidf (l);
-  return foo;
-}
-
-/* convert float to double */
-double
-__extendsfdf2 (float a1)
-{
-  register union float_long fl1;
-  register union double_long dl;
-  register long exp;
-
-  fl1.f = a1;
-
-  if (!fl1.l)
-    {
-      dl.l.upper = dl.l.lower = 0;
-      return dl.d;
-    }
-
-  dl.l.upper = SIGN (fl1.l);
-  exp = EXP (fl1.l) - EXCESS + EXCESSD;
-  dl.l.upper |= exp << 20;
-  dl.l.upper |= (MANT (fl1.l) & ~HIDDEN) >> 3;
-  dl.l.lower = MANT (fl1.l) << 29;
-	
-  return dl.d;
-}
-
-/* convert double to float */
-float
-__truncdfsf2 (double a1)
-{
-  register long exp;
-  register long mant;
-  register union float_long fl;
-  register union double_long dl1;
-
-  dl1.d = a1;
-
-  if (!dl1.l.upper && !dl1.l.lower)
-    return 0;
-
-  exp = EXPD (dl1) - EXCESSD + EXCESS;
-
-  /* shift double mantissa 6 bits so we can round */
-  mant = MANTD (dl1) >> 6;
-
-  /* now round and shift down */
-  mant += 1;
-  mant >>= 1;
-
-  /* did the round overflow? */
-  if (mant & 0xFF000000)
-    {
-      mant >>= 1;
-      exp++;
-    }
-
-  mant &= ~HIDDEN;
-
-  /* pack up and go home */
-  fl.l = PACK (SIGND (dl1), exp, mant);
-  return (fl.f);
-}
-
-/* convert double to int */
-int
-__fixdfsi (double a1)
-{
-  register union double_long dl1;
-  register long exp;
-  register long l;
-
-  dl1.d = a1;
-
-  if (!dl1.l.upper && !dl1.l.lower) 
-    return 0;
-
-  exp = EXPD (dl1) - EXCESSD - 31;
-  l = MANTD (dl1);
-
-  if (exp > 0) 
-    {
-      /* Return largest integer.  */
-      return SIGND (dl1) ? 0x80000000 : 0x7fffffff;
-    }
-
-  if (exp <= -32)
-    return 0;
-
-  /* shift down until exp = 0 */
-  if (exp < 0)
-    l >>= -exp;
-
-  return (SIGND (dl1) ? -l : l);
-}
-
-/* convert float to int */
-int
-__fixsfsi (float a1)
-{
-  double foo = a1;
-  return __fixdfsi (foo);
-}
-
-#else /* EXTFLOAT */
-
-/* Primitive extended precision floating point support.
-
-   We assume all numbers are normalized, don't do any rounding, etc.  */
-
-/* Prototypes for the above in case we use them.  */
-double __floatsidf (int);
-float __floatsisf (int);
-double __extendsfdf2 (float);
-float __truncdfsf2 (double);
-int __fixdfsi (double);
-int __fixsfsi (float);
-
-/* convert double to long double */
-long double
-__extenddfxf2 (double d)
-{
-  register union double_long dl;
-  register union long_double_long ldl;
-  register long exp;
-
-  dl.d = d;
-  /*printf ("dfxf in: %g\n", d);*/
-
-  if (!dl.l.upper && !dl.l.lower)
-    return 0;
-
-  ldl.l.upper = SIGND (dl);
-  exp = EXPD (dl) - EXCESSD + EXCESSX;
-  ldl.l.upper |= exp << 16;
-  ldl.l.middle = HIDDENX;
-  /* 31-20: # mantissa bits in ldl.l.middle - # mantissa bits in dl.l.upper */
-  ldl.l.middle |= (dl.l.upper & MANTDMASK) << (31 - 20);
-  /* 1+20: explicit-integer-bit + # mantissa bits in dl.l.upper */
-  ldl.l.middle |= dl.l.lower >> (1 + 20);
-  /* 32 - 21: # bits of dl.l.lower in ldl.l.middle */
-  ldl.l.lower = dl.l.lower << (32 - 21);
-
-  /*printf ("dfxf out: %s\n", dumpxf (ldl.ld));*/
-  return ldl.ld;
-}
-
-/* convert long double to double */
-double
-__truncxfdf2 (long double ld)
-{
-  register long exp;
-  register union double_long dl;
-  register union long_double_long ldl;
-
-  ldl.ld = ld;
-  /*printf ("xfdf in: %s\n", dumpxf (ld));*/
-
-  if (!ldl.l.upper && !ldl.l.middle && !ldl.l.lower)
-    return 0;
-
-  exp = EXPX (ldl) - EXCESSX + EXCESSD;
-  /* ??? quick and dirty: keep `exp' sane */
-  if (exp >= EXPDMASK)
-    exp = EXPDMASK - 1;
-  dl.l.upper = SIGNX (ldl);
-  dl.l.upper |= exp << (32 - (EXPDBITS + 1));
-  /* +1-1: add one for sign bit, but take one off for explicit-integer-bit */
-  dl.l.upper |= (ldl.l.middle & MANTXMASK) >> (EXPDBITS + 1 - 1);
-  dl.l.lower = (ldl.l.middle & MANTXMASK) << (32 - (EXPDBITS + 1 - 1));
-  dl.l.lower |= ldl.l.lower >> (EXPDBITS + 1 - 1);
-
-  /*printf ("xfdf out: %g\n", dl.d);*/
-  return dl.d;
-}
-
-/* convert a float to a long double */
-long double
-__extendsfxf2 (float f)
-{
-  long double foo = __extenddfxf2 (__extendsfdf2 (f));
-  return foo;
-}
-
-/* convert a long double to a float */
-float
-__truncxfsf2 (long double ld)
-{
-  float foo = __truncdfsf2 (__truncxfdf2 (ld));
-  return foo;
-}
-
-/* convert an int to a long double */
-long double
-__floatsixf (int l)
-{
-  double foo = __floatsidf (l);
-  return foo;
-}
-
-/* convert a long double to an int */
-int
-__fixxfsi (long double ld)
-{
-  int foo = __fixdfsi ((double) ld);
-  return foo;
-}
-
-/* The remaining provide crude math support by working in double precision.  */
-
-long double
-__addxf3 (long double x1, long double x2)
-{
-  return (double) x1 + (double) x2;
-}
-
-long double
-__subxf3 (long double x1, long double x2)
-{
-  return (double) x1 - (double) x2;
-}
-
-long double
-__mulxf3 (long double x1, long double x2)
-{
-  return (double) x1 * (double) x2;
-}
-
-long double
-__divxf3 (long double x1, long double x2)
-{
-  return (double) x1 / (double) x2;
-}
-
-long double
-__negxf2 (long double x1)
-{
-  return - (double) x1;
-}
-
-long
-__cmpxf2 (long double x1, long double x2)
-{
-  return __cmpdf2 ((double) x1, (double) x2);
-}
-
-long
-__eqxf2 (long double x1, long double x2)
-{
-  return __cmpdf2 ((double) x1, (double) x2);
-}
-
-long
-__nexf2 (long double x1, long double x2)
-{
-  return __cmpdf2 ((double) x1, (double) x2);
-}
-
-long
-__ltxf2 (long double x1, long double x2)
-{
-  return __cmpdf2 ((double) x1, (double) x2);
-}
-
-long
-__lexf2 (long double x1, long double x2)
-{
-  return __cmpdf2 ((double) x1, (double) x2);
-}
-
-long
-__gtxf2 (long double x1, long double x2)
-{
-  return __cmpdf2 ((double) x1, (double) x2);
-}
-
-long
-__gexf2 (long double x1, long double x2)
-{
-  return __cmpdf2 ((double) x1, (double) x2);
-}
-
-#endif /* EXTFLOAT */
diff --git a/gcc/config/m68k/hp2bsd.h b/gcc/config/m68k/hp2bsd.h
deleted file mode 100755
index 9090923..0000000
--- a/gcc/config/m68k/hp2bsd.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Definitions of target machine for GNU compiler.  HP 9000/200 68000 version.
-   Copyright (C) 1987, 1991 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m68k/m68k.h"
-
-/* See m68k.h.  0 means 68000 with no 68881.  */
-
-#define TARGET_DEFAULT 0
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Define __HAVE_68881 in preprocessor only if -m68881 is specified.
-   This will control the use of inline 68881 insns in certain macros.
-   Also inform the program which CPU this is for.  */
-
-#define CPP_SPEC "%{m68881:-D__HAVE_68881__} \
-%{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}"
-
-/* -m68020 requires special flags to the assembler.  */
-
-#define ASM_SPEC \
- "%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!m68020:-mc68010}}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dmc68000 -Dmc68010 -Dhp200 -Dunix -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-
-/* Link with libg.a when debugging, for dbx's sake.  */
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
-
-/* Alignment of field after `int : 0' in a structure.  */
-
-#undef EMPTY_FIELD_BOUNDARY
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Define subroutines to call to handle multiply, divide, and remainder.
-   These routines are built into the c-library on the hp200.
-   XXX What other routines from the c-library could we use?
-   The `*' prevents an underscore from being prepended by the compiler.  */
-
-#define DIVSI3_LIBCALL "*ldiv"
-#define UDIVSI3_LIBCALL "*uldiv"
-#define MODSI3_LIBCALL "*lrem"
-#define UMODSI3_LIBCALL "*ulrem"
-#define MULSI3_LIBCALL "*lmul"
-#define UMULSI3_LIBCALL "*ulmul"
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
diff --git a/gcc/config/m68k/hp310.h b/gcc/config/m68k/hp310.h
deleted file mode 100755
index a9d24f4..0000000
--- a/gcc/config/m68k/hp310.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Definitions of target machine for GNU compiler.  HP-UX 68010 version.  */
-
-/* See m68k.h.  0 means 68000 without 68881 and no bitfields.   */
-#define	TARGET_DEFAULT 0
-
-#include "m68k/hp320.h"
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-#undef CPP_SPEC
-#undef ASM_SPEC
-
-/* HP does not support a 68020 without a 68881 or a 68010 with a 68881.
-   However, -m68020 does not imply -m68881.  You must specify both
-   if you want both.  */
-
-#ifdef HPUX_ASM
-
-#define CPP_SPEC "-D__HPUX_ASM__ %{m68881: -D__HAVE_68881__}\
-%{m68020: -Dmc68020}%{mc68020: -Dmc68020}\
-%{!traditional:-D_INCLUDE__STDC__}"
-
-#define ASM_SPEC "%{!m68020:%{!mc68020:+X}}"
-
-#else	/* not HPUX_ASM */
-
-#define CPP_SPEC "%{m68881: -D__HAVE_68881__}\
-%{m68020: -Dmc68020}%{mc68020: -Dmc68020}\
-%{!traditional:-D_INCLUDE__STDC__}"
-
-#define ASM_SPEC \
- "%{m68000:-mc68000}%{mc68000:-mc68000}%{!mc68000:%{!m68000:-mc68020}}"
-
-#endif	/* not HPUX_ASM */
diff --git a/gcc/config/m68k/hp310g.h b/gcc/config/m68k/hp310g.h
deleted file mode 100755
index c07a73b..0000000
--- a/gcc/config/m68k/hp310g.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Definitions of target machine for GNU compiler.  HP-UX 68010 version.
-   Use this file if GCC is supposed to work with the GNU assembler,
-   GNU linker and GNU debugger using DBX debugging information.
-   (In other words, much of HPUX has been cast aside.)  */
-
-/* This wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-#define USE_GAS
-
-#include "m68k/hp310.h"
diff --git a/gcc/config/m68k/hp320.h b/gcc/config/m68k/hp320.h
deleted file mode 100755
index 9816502..0000000
--- a/gcc/config/m68k/hp320.h
+++ /dev/null
@@ -1,642 +0,0 @@
-/* Definitions of target machine for GNU compiler.  HP-UX 68000/68020 version.
-   Copyright (C) 1987, 88, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Define USE_GAS if GCC is supposed to work with the GNU assembler,
-   GNU linker and GNU debugger using DBX debugging information.
-   (In other words, much of HPUX has been cast aside.)
-   Undefine USE_GAS if you want GCC to feed the HP assembler.  */
-
-/* #define USE_GAS */  /* Use hp320g.h if you want this.  */
-
-/* Control assembler-syntax conditionals in m68k.md.  */
-
-#ifndef USE_GAS
-#define MOTOROLA		/* Use Motorola syntax rather than "MIT" */
-#define SGS			/* Uses SGS assembler */
-#define SGS_CMP_ORDER		/* Takes cmp operands in reverse order */
-#define HPUX_ASM
-
-#if !defined (CROSS_COMPILE) && !defined (NO_BUGS)
-/* The assembler on HP 9k3xx machines running HPUX 8.0 doesn't translate
-   floating point constants behind some operands.  The workaround is to
-   use hex constants.  Reported by Thomas Nau (nau@medizin.uni-ulm.de).  */
-#define AS_BUG_FLOATING_CONSTANT
-/* The assembler on HP 9k3xx machines running HPUX 8.0 doesn't accept
-   labels followed by a text, data, or other section directive.  Reported
-   by Thomas Nau (nau@medizin.uni-ulm.de).  */
-#define AS_BUG_TRAILING_LABEL
-#endif
-
-#endif /* not USE_GAS */
-
-/* gcc.c should find libgcc.a itself rather than expecting linker to.  */
-#define LINK_LIBGCC_SPECIAL
-/* The arguments of -L must be a separate argv element.  */
-#define SPACE_AFTER_L_OPTION
-/* HP/UX doesn't have libg.a.  */
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
-
-/* Be compatible with system stddef.h.  */
-#define SIZE_TYPE "unsigned int"
-
-/* Use atexit for static constructors/destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
-#include "m68k/m68k.h"
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-
-#ifndef TARGET_DEFAULT
-#define	TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-/* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified.
-   This will control the use of inline 68881 insns in certain macros.  */
-
-#ifdef HPUX_ASM
-
-#define ASM_SPEC "%{m68000:+X}%{mc68000:+X}"
-
-#define NO_DOT_IN_LABEL
-
-#if TARGET_DEFAULT & MASK_68881  /* -m68881 is the default */
-
-/* These definitions differ from those used for GAS by defining __HPUX_ASM__.
-   This is needed because some programs, particularly GDB, need to
-   know which assembler is being used so that the correct `asm'
-   instructions can be used. */
-
-#define CPP_SPEC \
-"%{!msoft-float:-D__HAVE_68881__ }\
-%{!ansi:%{!mc68000:%{!m68000:-Dmc68020}} -D_HPUX_SOURCE} -D__HPUX_ASM__"
-
-#else /* default is -msoft-float */
-
-#define CPP_SPEC \
-"%{m68881:-D__HAVE_68881__ }\
-%{!ansi:%{!mc68000:%{!m68000:-Dmc68020}} -D_HPUX_SOURCE} -D__HPUX_ASM__"
-
-#endif /* default is -msoft-float */
-
-#else /* not HPUX_ASM */
-
-#if TARGET_DEFAULT & MASK_68881  /* -m68881 is the default */
-
-#define CPP_SPEC \
-"%{!msoft-float:-D__HAVE_68881__ }\
-%{!ansi:%{!mc68000:%{!m68000:-Dmc68020}} -D_HPUX_SOURCE}"
-
-#else /* default is -msoft-float */
-
-#define CPP_SPEC \
-"%{m68881:-D__HAVE_68881__ }\
-%{!ansi:%{!mc68000:%{!m68000:-Dmc68020}} -D_HPUX_SOURCE}"
-
-#endif /* default is -msoft-float */
-
-
-/* -m68000 requires special flags to the assembler.  */
-#define ASM_SPEC \
- "%{m68000:-mc68000}%{mc68000:-mc68000}%{!mc68000:%{!m68000:-mc68020}}"
-
-/* Tell GCC to put a space after -L when generating such options.  */
-#define SPACE_AFTER_L_OPTION
-
-#endif /* Not HPUX_ASM */
-
-/* Translate -static for HPUX linker.  */
-#define LINK_SPEC "%{static:-a archive}"
-
-/* Names to predefine in the preprocessor for this target machine
-   (for non-strict-ANSI programs only).  */
-/* These are the ones defined by HPUX cc, plus mc68000 for uniformity with
-   GCC on other 68000 systems.  */
-
-#define CPP_PREDEFINES "-Dhp9000s200 -Dhp9000s300 -DPWB -Dhpux -Dunix -D__hp9000s300 -D__hp9000s200 -D__PWB -D__hpux -D__unix -D__motorola__ -Asystem(unix) -Asystem(hpux) -Acpu(m68k) -Amachine(m68k)"
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* hpux doesn't use static area for struct returns. */
-#undef PCC_STATIC_STRUCT_RETURN
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#define TARGET_MEM_FUNCTIONS
-
-#if 0  /* No longer correct in HPUX version 6.5.  */
-/* Function calls don't save any fp registers on hpux.  */
-#undef CALL_USED_REGISTERS
-#define CALL_USED_REGISTERS						\
- {1, 1, 0, 0, 0, 0, 0, 0,						\
-  1, 1, 0, 0, 0, 0, 0, 1,						\
-  1, 1, 1, 1, 1, 1, 1, 1}
-#endif /* 0 */
-
-#ifdef HPUX_ASM
-
-/* Override parts of m68k.h to fit the HPUX assembler.  */
-
-#undef TARGET_VERSION
-#undef REGISTER_NAMES
-#undef ASM_OUTPUT_REG_PUSH
-#undef ASM_OUTPUT_REG_POP
-#undef ASM_FILE_START
-#undef ASM_APP_ON
-#undef ASM_APP_OFF
-#undef TEXT_SECTION_ASM_OP
-#undef DATA_SECTION_ASM_OP
-#undef READONLY_DATA_SECTION
-#undef ASM_OUTPUT_DOUBLE
-#undef ASM_OUTPUT_FLOAT
-#undef ASM_OUTPUT_INT
-#undef ASM_OUTPUT_SHORT
-#undef ASM_OUTPUT_CHAR
-#undef ASM_OUTPUT_BYTE
-#undef ASM_OUTPUT_ADDR_VEC_ELT
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#undef ASM_OUTPUT_ALIGN
-#undef ASM_OUTPUT_SKIP
-#undef ASM_OUTPUT_COMMON
-#undef ASM_OUTPUT_LOCAL
-#undef ASM_FORMAT_PRIVATE_NAME
-#undef FUNCTION_PROFILER
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#undef GLOBAL_ASM_OP
-#undef IMMEDIATE_PREFIX
-#undef REGISTER_PREFIX
-
-#define TARGET_VERSION fprintf (stderr, " (68k, SGS/hpux syntax)");
-
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",	\
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",	\
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7"}
-
-#define IMMEDIATE_PREFIX        "&"
-#define REGISTER_PREFIX         "%"
-
-#define FUNCTION_PROFILER(FILE, LABEL_NO) \
-   fprintf (FILE, "\tmov.l &LP%d,%%a0\n\tjsr mcount\n", (LABEL_NO));
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tmov.l %s,-(%%sp)\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tmov.l (%%sp)+,%s\n", reg_names[REGNO])
-
-/* For HPUX versions before 6.5, define this macro as empty.  */
-#define ASM_FILE_START(FILE)						\
-  if (TARGET_68020)							\
-    {									\
-      if (TARGET_68881)							\
-	 fprintf (FILE, "\tversion 3\n"); /* 68020 fp regs saved */	\
-      else								\
-	 fprintf (FILE, "\tversion 2\n"); /* 68020 no fp regs saved */	\
-    }									\
-  else									\
-    fprintf (FILE, "\tversion 1\n");	/* 68010 */
-
-#define ASM_APP_ON ""
-
-#define ASM_APP_OFF ""
-
-#ifdef AS_BUG_TRAILING_LABEL
-#define TEXT_SECTION_ASM_OP "\tlalign\t1\ntext"
-#define DATA_SECTION_ASM_OP "\tlalign\t1\ndata"
-#else
-#define TEXT_SECTION_ASM_OP "text"
-#define DATA_SECTION_ASM_OP "data"
-#endif
-#define	ASCII_DATA_ASM_OP "byte"
- 
-/* This is the command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define GLOBAL_ASM_OP "global"
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\tcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\tlcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u,2\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12),	\
-  sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-do{  if (PREFIX[0] == 'L' && PREFIX[1] == 'I')		\
-    fprintf(FILE, "\tset %s%d,.+2\n", PREFIX, NUM);	\
-  else							\
-    fprintf (FILE, "%s%d:\n", PREFIX, NUM);		\
-} while(0)
-
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)			\
-  do { char dstr[30];					\
-       REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr);	\
-       fprintf (FILE, "\tdouble 0f%s\n", dstr);		\
-     } while (0)
-
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)			\
-  do { char dstr[30];					\
-       REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr);	\
-       fprintf (FILE, "\tfloat 0f%s\n", dstr);		\
-     } while (0)
-
-#undef ASM_OUTPUT_LONG_DOUBLE
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE)  				\
-do { long l[3];								\
-     REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l);			\
-     fprintf (FILE, "\tlong 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]);	\
-   } while (0)
-  
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\tlong "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\tshort "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\tbyte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\tbyte 0x%x\n", (VALUE))
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\tlong L%d\n", VALUE)
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\tshort L%d-L%d\n", VALUE, REL)
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) == 1)			\
-    fprintf (FILE, "\tlalign 2\n");	\
-  else if ((LOG) != 0)			\
-    abort ();
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\tspace %u\n", (SIZE))
-
-#define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME)
-#define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO)
-
-/* Output a float value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#ifdef AS_BUG_FLOATING_CONSTANT
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)		\
- do { long l;							\
-      REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);			\
-      fprintf ((FILE), "&0x%lx", l);				\
-     } while (0)
-#else
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)		\
- do {								\
-      if (CODE == 'f')						\
-        {							\
-          char dstr[30];					\
-          REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr);		\
-          fprintf ((FILE), "&0f%s", dstr);			\
-        }							\
-      else							\
-        {							\
-          long l;						\
-          REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-          fprintf ((FILE), "&0x%lx", l);			\
-        }							\
-     } while (0)
-#endif /* AS_BUG_FLOATING_CONSTANT */
-
-/* Output a double value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)				\
- do { char dstr[30];							\
-      REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr);			\
-      fprintf (FILE, "&0f%s", dstr);					\
-    } while (0)
-
-/* Note, long double immediate operands are not actually
-   generated by m68k.md.  */
-#undef ASM_OUTPUT_LONG_DOUBLE_OPERAND
-#define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE)			\
- do { char dstr[30];							\
-      REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr);			\
-      fprintf (FILE, "&0f%s", dstr);					\
-    } while (0)
-
-#if 0
-#undef PRINT_OPERAND
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ if (CODE == '.') fprintf (FILE, ".");					\
-  else if (CODE == '#') fprintf (FILE, "&");				\
-  else if (CODE == '-') fprintf (FILE, "-(%%sp)");			\
-  else if (CODE == '+') fprintf (FILE, "(%%sp)+");			\
-  else if (CODE == '@') fprintf (FILE, "(%%sp)");			\
-  else if (CODE == '!') fprintf (FILE, "%%fpcr");			\
-  else if (CODE == '$') { if (TARGET_68040_ONLY) fprintf (FILE, "s"); } \
-  else if (CODE == '&') { if (TARGET_68040_ONLY) fprintf (FILE, "d"); } \
-  else if (CODE == '/')							\
-    fprintf (FILE, "%%");						\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode)	\
-    { REAL_VALUE_TYPE r;  long l;					\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      PRINT_OPERAND_FLOAT (CODE, FILE, r, l); }				\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode)	\
-    { REAL_VALUE_TYPE r;  char dstr[30];				\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      REAL_VALUE_TO_DECIMAL (r, "%.20g", dstr);				\
-      fprintf (FILE, "&0f%s", dstr); }					\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == XFmode)	\
-    { REAL_VALUE_TYPE r;  char dstr[30];				\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      REAL_VALUE_TO_DECIMAL (r, "%.20g", dstr);				\
-      fprintf (FILE, "&0f%s", dstr); }					\
-  else { putc ('&', FILE); output_addr_const (FILE, X); }}
-#endif
-
-#undef PRINT_OPERAND_ADDRESS
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx reg1, reg2, breg, ireg;					\
-  register rtx addr = ADDR;						\
-  rtx offset;								\
-  switch (GET_CODE (addr))						\
-    {									\
-    case REG:								\
-      fprintf (FILE, "(%s)", reg_names[REGNO (addr)]);			\
-      break;								\
-    case PRE_DEC:							\
-      fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case POST_INC:							\
-      fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case PLUS:								\
-      reg1 = 0;	reg2 = 0;						\
-      ireg = 0;	breg = 0;						\
-      offset = 0;							\
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))				\
-	{								\
-	  offset = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))			\
-	{								\
-	  offset = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) != PLUS) ;					\
-      else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT		\
-	  || GET_CODE (addr) == SIGN_EXTEND)				\
-	{ if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; }	\
-/*  for OLD_INDEXING							\
-      else if (GET_CODE (addr) == PLUS)					\
-	{								\
-	  if (GET_CODE (XEXP (addr, 0)) == REG)				\
-	    {								\
-	      reg2 = XEXP (addr, 0);					\
-	      addr = XEXP (addr, 1);					\
-	    }								\
-	  else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	    {								\
-	      reg2 = XEXP (addr, 1);					\
-	      addr = XEXP (addr, 0);					\
-	    }								\
-	}								\
-  */									\
-      if (offset != 0) { if (addr != 0) abort (); addr = offset; }	\
-      if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND			\
-		    || GET_CODE (reg1) == MULT))			\
-	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))		\
-	{ breg = reg2; ireg = reg1; }					\
-      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))		\
-	{ breg = reg1; ireg = reg2; }					\
-      if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { int scale = 1;						\
-	  if (GET_CODE (ireg) == MULT)					\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (GET_CODE (ireg) == SIGN_EXTEND)				\
-	    fprintf (FILE, "L%d-LI%d(%%pc,%s.w",			\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (XEXP (ireg, 0))]); 		\
-	  else								\
-	    fprintf (FILE, "L%d-LI%d(%%pc,%s.l",			\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (ireg)]);				\
-	  if (scale != 1) fprintf (FILE, "*%d", scale);			\
-	  putc (')', FILE);						\
-	  break; }							\
-      if (ireg != 0 || breg != 0)					\
-	{ int scale = 1;						\
-	  if (breg == 0)						\
-	    abort ();							\
-	  if (addr != 0)						\
-	    output_addr_const (FILE, addr);				\
-	  fprintf (FILE, "(%s", reg_names[REGNO (breg)]);		\
-	  if (ireg != 0)						\
-	    putc (',', FILE);						\
-	  if (ireg != 0 && GET_CODE (ireg) == MULT)			\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)		\
-	    fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);	\
-	  else if (ireg != 0)						\
-	    fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]);		\
-	  if (scale != 1) fprintf (FILE, "*%d", scale);			\
-	  putc (')', FILE);						\
-	  break;							\
-	}								\
-      else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF)		\
-	{ fprintf (FILE, "L%d-LI%d(%%pc,%s.w)",				\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   reg_names[REGNO (reg1)]);				\
-	  break; }							\
-    default:								\
-      if (GET_CODE (addr) == CONST_INT					\
-	  && INTVAL (addr) < 0x8000					\
-	  && INTVAL (addr) >= -0x8000)					\
-	fprintf (FILE, "%d.w", INTVAL (addr));				\
-      else								\
-        output_addr_const (FILE, addr);					\
-    }}
-
-#define	ASM_OUTPUT_ASCII(f, p, size)	\
-do { register int i;			\
-  int inside;				\
-  inside = FALSE;			\
-  for (i = 0; i < (size); i++) {	\
-    if (i % 8 == 0) {			\
-      if (i != 0) {			\
-	if (inside)			\
-	  putc('"', (f));		\
-	putc('\n', (f));		\
-	inside = FALSE;			\
-      }					\
-      fprintf((f), "\t%s ", ASCII_DATA_ASM_OP);	\
-    }					\
-    if ((p)[i] < 32 || (p)[i] == '\\' || (p)[i] == '"' || (p)[i] == 127) {	\
-      if (inside) {			\
-	putc('"', (f));			\
-	inside = FALSE;			\
-      }					\
-      if (i % 8 != 0)			\
-	putc(',', (f));			\
-      fprintf((f), "%d", (p)[i]);	\
-    } else {				\
-      if (!inside) {			\
-	if (i % 8 != 0)			\
-	  putc(',', (f));		\
-	putc('"', (f));			\
-	inside = TRUE;			\
-      }					\
-      putc((p)[i], (f));		\
-    }					\
-  }					\
-  if (inside)				\
-    putc('"', (f));			\
-  putc('\n', (f));			\
-} while (0)
-
-/* Translate Motorola opcodes such as `jbeq'
-   into SGS opcodes such as `beq.w'.
-   Delete the `e' in `move...' and `fmove'.
-   Change `ftst' to `ftest'.  */
-
-#define ASM_OUTPUT_OPCODE(FILE, PTR)			\
-{ if ((PTR)[0] == 'j' && (PTR)[1] == 'b')		\
-    { ++(PTR);						\
-      while (*(PTR) != ' ')				\
-	{ putc (*(PTR), (FILE)); ++(PTR); }		\
-      fprintf ((FILE), ".w"); }				\
-  else if ((PTR)[0] == 'f')				\
-    {							\
-      if (!strncmp ((PTR), "fmove", 5))			\
-	{ fprintf ((FILE), "fmov"); (PTR) += 5; }	\
-      else if (!strncmp ((PTR), "ftst", 4))		\
-	{ fprintf ((FILE), "ftest"); (PTR) += 4; }	\
-    }							\
-  else if ((PTR)[0] == 'm' && (PTR)[1] == 'o'		\
-	   && (PTR)[2] == 'v' && (PTR)[3] == 'e')	\
-    { fprintf ((FILE), "mov"); (PTR) += 4; }		\
-}
-
-/* Prevent output of `gcc_compiled.:'.  */
-
-#define ASM_IDENTIFY_GCC(FILE)
-
-#else /* not HPUX_ASM */
-
-#undef FUNCTION_PROFILER
-
-/* HP-UX needs the call to mcount before the link instruction.
-   Copy the return address onto the stack before the call to fake it out.  */
-#define FUNCTION_PROFILER(FILE, LABEL_NO) \
-  fprintf (FILE, \
-	   "\tmovel a6@(4),sp@-\n\tmovl #LP%d,a0\n\tjsr mcount\n\taddqw #4,sp\n", \
-	   (LABEL_NO));
-
-#endif /* not HPUX_ASM */
-
-/* In m68k svr4, a symbol_ref rtx can be a valid PIC operand if it is an
-   operand of a function call. */
-#undef LEGITIMATE_PIC_OPERAND_P
-#define LEGITIMATE_PIC_OPERAND_P(X) \
-  ((! symbolic_operand (X, VOIDmode) \
-    && ! (GET_CODE (X) == CONST_DOUBLE && CONST_DOUBLE_MEM (X)	\
-	  && GET_CODE (CONST_DOUBLE_MEM (X)) == MEM		\
-	  && symbolic_operand (XEXP (CONST_DOUBLE_MEM (X), 0), VOIDmode))) \
-   || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)))
-
-/* hpux8 and later have C++ compatible include files, so do not
-   pretend they are `extern "C"'.  */
-#define NO_IMPLICIT_EXTERN_C
diff --git a/gcc/config/m68k/hp320g.h b/gcc/config/m68k/hp320g.h
deleted file mode 100755
index 1e93185..0000000
--- a/gcc/config/m68k/hp320g.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Definitions of target machine for GNU compiler.  HP-UX 68000/68020 version.
-   Use this file if GCC is supposed to work with the GNU assembler,
-   GNU linker and GNU debugger using DBX debugging information.
-   (In other words, much of HPUX has been cast aside.)  */
-
-/* This wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-#define USE_GAS
-
-#include "m68k/hp320.h"
diff --git a/gcc/config/m68k/hp3bsd.h b/gcc/config/m68k/hp3bsd.h
deleted file mode 100755
index 34405f8..0000000
--- a/gcc/config/m68k/hp3bsd.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#include "m68k/m68k.h"
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-
-/* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified.
-   This will control the use of inline 68881 insns in certain macros.  */
-
-#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__ -D__HAVE_FPU__}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dmc68000 -Dmc68020 -Dhp300 -Dhp9000 -Dunix -Asystem(unix)  -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-
-/* Link with libg.a when debugging, for dbx's sake.  */
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Do not break .stabs pseudos into continuations.  */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* This is the char to use for continuation (in case we need to turn
-   continuation back on).  */
-
-#define DBX_CONTIN_CHAR '?'
-
-/* Don't use the `xsfoo;' construct in DBX output; this system
-   doesn't support it.  */
-
-#define DBX_NO_XREFS
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
diff --git a/gcc/config/m68k/hp3bsd44.h b/gcc/config/m68k/hp3bsd44.h
deleted file mode 100755
index a3b652f..0000000
--- a/gcc/config/m68k/hp3bsd44.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#include "m68k/m68k.h"
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-
-/* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified.
-   This will control the use of inline 68881 insns in certain macros.  */
-
-#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__ -D__HAVE_FPU__}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dmc68000 -Dmc68020 -Dhp300 -Dhp9000 -Dunix -D__BSD_4_4__ -Asystem(unix)  -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-
-/* No more libg.a */
-
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
-
-/* Make gcc agree with <machine/ansi.h> */
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Do not break .stabs pseudos into continuations.  */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* This is the char to use for continuation (in case we need to turn
-   continuation back on).  */
-
-#define DBX_CONTIN_CHAR '?'
-
-/* Don't use the `xsfoo;' construct in DBX output; this system
-   doesn't support it.  */
-
-#define DBX_NO_XREFS
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
diff --git a/gcc/config/m68k/hpux7.h b/gcc/config/m68k/hpux7.h
deleted file mode 100755
index ae584bd..0000000
--- a/gcc/config/m68k/hpux7.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* tm.h for m68k running HPUX version 7.  */
-
-/* fletcher@cs.utexas.edu says this is needed.  */
-#define NO_DOT_IN_LABEL
-#define NO_BUGS
-
-#include "m68k/hp320.h"
diff --git a/gcc/config/m68k/isi-nfp.h b/gcc/config/m68k/isi-nfp.h
deleted file mode 100755
index fbded9e..0000000
--- a/gcc/config/m68k/isi-nfp.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Define target machine as an ISI 68000/68020 with no 68881.  */
-
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68020)
-
-#include "m68k/isi.h"
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
diff --git a/gcc/config/m68k/isi.h b/gcc/config/m68k/isi.h
deleted file mode 100755
index a458cf9..0000000
--- a/gcc/config/m68k/isi.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* Definitions of target machine for GNU compiler.  ISI 68000/68020 version.
-   Intended only for use with GAS, and not ISI's assembler, which is buggy
-   Copyright (C) 1988, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m68k/m68k.h"
-
-/* See m68k.h.  7 means 68020 with 68881. */
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-#if TARGET_DEFAULT & MASK_68881
-/* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified.
-   This will control the use of inline 68881 insns in certain macros.  */
-
-#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__}"
-
-/* If the 68881 is used, link must load libmc.a before libc.a.  */
-
-#define LIB_SPEC "%{!msoft-float:%{!p:%{!pg:-lmc}}%{p:-lmc_p}%{pg:-lmc_p}} \
-%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
-
-#else
-/* Define __HAVE_68881__ in preprocessor if -m68881 is specified.
-   This will control the use of inline 68881 insns in certain macros.  */
-
-#define CPP_SPEC "%{m68881:-D__HAVE_68881__}"
-
-/* If the 68881 is used, link must load libmc.a instead of libc.a */
-
-#define LIB_SPEC "%{m68881:%{!p:%{!pg:-lmc}}%{p:-lmc_p}%{pg:-lmc_p}} \
-%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
-#endif
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dunix -Dmc68000 -Dis68k -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Override parts of m68k.h to fit the ISI 68k machine.  */
-
-#undef FUNCTION_VALUE
-#undef LIBCALL_VALUE
-#undef FUNCTION_VALUE_REGNO_P
-#undef NEEDS_UNTYPED_CALL
-#undef ASM_FILE_START
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* If TARGET_68881, return SF and DF values in f0 instead of d0.  */
-
-#define FUNCTION_VALUE(VALTYPE,FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
-
-#define LIBCALL_VALUE(MODE) \
- gen_rtx (REG, (MODE), ((TARGET_68881 && ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0))
-
-/* 1 if N is a possible register number for a function value.
-   D0 may be used, and F0 as well if -m68881 is specified.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) \
- ((N) == 0 || (TARGET_68881 && (N) == 16))
-
-/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
-   more than one register.  */
-
-#define NEEDS_UNTYPED_CALL 1
-
-/* Also output something to cause the correct _doprnt to be loaded.  */
-#define ASM_FILE_START(FILE) fprintf (FILE, "#NO_APP\n%s\n", TARGET_68881 ? ".globl fltused" : "")
diff --git a/gcc/config/m68k/lb1sf68.asm b/gcc/config/m68k/lb1sf68.asm
deleted file mode 100755
index ef40a34..0000000
--- a/gcc/config/m68k/lb1sf68.asm
+++ /dev/null
@@ -1,3904 +0,0 @@
-/* libgcc1 routines for 68000 w/o floating-point hardware.
-   Copyright (C) 1994, 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with files
-   compiled with GCC to produce an executable, this does not cause
-   the resulting executable to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-/* Use this one for any 680x0; assumes no floating point hardware.
-   The trailing " '" appearing on some lines is for ANSI preprocessors.  Yuk.
-   Some of this code comes from MINIX, via the folks at ericsson.
-   D. V. Henkel-Wallace (gumby@cygnus.com) Fete Bastille, 1992
-*/
-
-/* These are predefined by new versions of GNU cpp.  */
-
-#ifndef __USER_LABEL_PREFIX__
-#define __USER_LABEL_PREFIX__ _
-#endif
-
-#ifndef __REGISTER_PREFIX__
-#define __REGISTER_PREFIX__
-#endif
-
-#ifndef __IMMEDIATE_PREFIX__
-#define __IMMEDIATE_PREFIX__ #
-#endif
-
-/* ANSI concatenation macros.  */
-
-#define CONCAT1(a, b) CONCAT2(a, b)
-#define CONCAT2(a, b) a ## b
-
-/* Use the right prefix for global labels.  */
-
-#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
-
-/* Use the right prefix for registers.  */
-
-#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
-
-/* Use the right prefix for immediate values.  */
-
-#define IMM(x) CONCAT1 (__IMMEDIATE_PREFIX__, x)
-
-#define d0 REG (d0)
-#define d1 REG (d1)
-#define d2 REG (d2)
-#define d3 REG (d3)
-#define d4 REG (d4)
-#define d5 REG (d5)
-#define d6 REG (d6)
-#define d7 REG (d7)
-#define a0 REG (a0)
-#define a1 REG (a1)
-#define a2 REG (a2)
-#define a3 REG (a3)
-#define a4 REG (a4)
-#define a5 REG (a5)
-#define a6 REG (a6)
-#define fp REG (fp)
-#define sp REG (sp)
-
-#ifdef L_floatex
-
-| This is an attempt at a decent floating point (single, double and 
-| extended double) code for the GNU C compiler. It should be easy to
-| adapt to other compilers (but beware of the local labels!).
-
-| Starting date: 21 October, 1990
-
-| It is convenient to introduce the notation (s,e,f) for a floating point
-| number, where s=sign, e=exponent, f=fraction. We will call a floating
-| point number fpn to abbreviate, independently of the precision.
-| Let MAX_EXP be in each case the maximum exponent (255 for floats, 1023 
-| for doubles and 16383 for long doubles). We then have the following 
-| different cases:
-|  1. Normalized fpns have 0 < e < MAX_EXP. They correspond to 
-|     (-1)^s x 1.f x 2^(e-bias-1).
-|  2. Denormalized fpns have e=0. They correspond to numbers of the form
-|     (-1)^s x 0.f x 2^(-bias).
-|  3. +/-INFINITY have e=MAX_EXP, f=0.
-|  4. Quiet NaN (Not a Number) have all bits set.
-|  5. Signaling NaN (Not a Number) have s=0, e=MAX_EXP, f=1.
-
-|=============================================================================
-|                                  exceptions
-|=============================================================================
-
-| This is the floating point condition code register (_fpCCR):
-|
-| struct {
-|   short _exception_bits;	
-|   short _trap_enable_bits;	
-|   short _sticky_bits;
-|   short _rounding_mode;
-|   short _format;
-|   short _last_operation;
-|   union {
-|     float sf;
-|     double df;
-|   } _operand1;
-|   union {
-|     float sf;
-|     double df;
-|   } _operand2;
-| } _fpCCR;
-
-	.data
-	.even
-
-	.globl	SYM (_fpCCR)
-	
-SYM (_fpCCR):
-__exception_bits:
-	.word	0
-__trap_enable_bits:
-	.word	0
-__sticky_bits:
-	.word	0
-__rounding_mode:
-	.word	ROUND_TO_NEAREST
-__format:
-	.word	NIL
-__last_operation:
-	.word	NOOP
-__operand1:
-	.long	0
-	.long	0
-__operand2:
-	.long 	0
-	.long	0
-
-| Offsets:
-EBITS  = __exception_bits - SYM (_fpCCR)
-TRAPE  = __trap_enable_bits - SYM (_fpCCR)
-STICK  = __sticky_bits - SYM (_fpCCR)
-ROUND  = __rounding_mode - SYM (_fpCCR)
-FORMT  = __format - SYM (_fpCCR)
-LASTO  = __last_operation - SYM (_fpCCR)
-OPER1  = __operand1 - SYM (_fpCCR)
-OPER2  = __operand2 - SYM (_fpCCR)
-
-| The following exception types are supported:
-INEXACT_RESULT 		= 0x0001
-UNDERFLOW 		= 0x0002
-OVERFLOW 		= 0x0004
-DIVIDE_BY_ZERO 		= 0x0008
-INVALID_OPERATION 	= 0x0010
-
-| The allowed rounding modes are:
-UNKNOWN           = -1
-ROUND_TO_NEAREST  = 0 | round result to nearest representable value
-ROUND_TO_ZERO     = 1 | round result towards zero
-ROUND_TO_PLUS     = 2 | round result towards plus infinity
-ROUND_TO_MINUS    = 3 | round result towards minus infinity
-
-| The allowed values of format are:
-NIL          = 0
-SINGLE_FLOAT = 1
-DOUBLE_FLOAT = 2
-LONG_FLOAT   = 3
-
-| The allowed values for the last operation are:
-NOOP         = 0
-ADD          = 1
-MULTIPLY     = 2
-DIVIDE       = 3
-NEGATE       = 4
-COMPARE      = 5
-EXTENDSFDF   = 6
-TRUNCDFSF    = 7
-
-|=============================================================================
-|                           __clear_sticky_bits
-|=============================================================================
-
-| The sticky bits are normally not cleared (thus the name), whereas the 
-| exception type and exception value reflect the last computation. 
-| This routine is provided to clear them (you can also write to _fpCCR,
-| since it is globally visible).
-
-	.globl  SYM (__clear_sticky_bit)
-
-	.text
-	.even
-
-| void __clear_sticky_bits(void);
-SYM (__clear_sticky_bit):		
-	lea	SYM (_fpCCR),a0
-#ifndef __mcf5200__
-	movew	IMM (0),a0@(STICK)
-#else
-	clr.w	a0@(STICK)
-#endif
-	rts
-
-|=============================================================================
-|                           $_exception_handler
-|=============================================================================
-
-	.globl  $_exception_handler
-
-	.text
-	.even
-
-| This is the common exit point if an exception occurs.
-| NOTE: it is NOT callable from C!
-| It expects the exception type in d7, the format (SINGLE_FLOAT,
-| DOUBLE_FLOAT or LONG_FLOAT) in d6, and the last operation code in d5.
-| It sets the corresponding exception and sticky bits, and the format. 
-| Depending on the format if fills the corresponding slots for the 
-| operands which produced the exception (all this information is provided
-| so if you write your own exception handlers you have enough information
-| to deal with the problem).
-| Then checks to see if the corresponding exception is trap-enabled, 
-| in which case it pushes the address of _fpCCR and traps through 
-| trap FPTRAP (15 for the moment).
-
-FPTRAP = 15
-
-$_exception_handler:
-	lea	SYM (_fpCCR),a0
-	movew	d7,a0@(EBITS)	| set __exception_bits
-#ifndef __mcf5200__
-	orw	d7,a0@(STICK)	| and __sticky_bits
-#else
-	movew	a0@(STICK),d4
-	orl	d7,d4
-	movew	d4,a0@(STICK)
-#endif
-	movew	d6,a0@(FORMT)	| and __format
-	movew	d5,a0@(LASTO)	| and __last_operation
-
-| Now put the operands in place:
-#ifndef __mcf5200__
-	cmpw	IMM (SINGLE_FLOAT),d6
-#else
-	cmpl	IMM (SINGLE_FLOAT),d6
-#endif
-	beq	1f
-	movel	a6@(8),a0@(OPER1)
-	movel	a6@(12),a0@(OPER1+4)
-	movel	a6@(16),a0@(OPER2)
-	movel	a6@(20),a0@(OPER2+4)
-	bra	2f
-1:	movel	a6@(8),a0@(OPER1)
-	movel	a6@(12),a0@(OPER2)
-2:
-| And check whether the exception is trap-enabled:
-#ifndef __mcf5200__
-	andw	a0@(TRAPE),d7	| is exception trap-enabled?
-#else
-	clrl	d6
-	movew	a0@(TRAPE),d6
-	andl	d6,d7
-#endif
-	beq	1f		| no, exit
-	pea	SYM (_fpCCR)	| yes, push address of _fpCCR
-	trap	IMM (FPTRAP)	| and trap
-#ifndef __mcf5200__
-1:	moveml	sp@+,d2-d7	| restore data registers
-#else
-1:	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6		| and return
-	rts
-#endif /* L_floatex */
-
-#ifdef  L_mulsi3
-	.text
-	.proc
-	.globl	SYM (__mulsi3)
-SYM (__mulsi3):
-	movew	sp@(4), d0	/* x0 -> d0 */
-	muluw	sp@(10), d0	/* x0*y1 */
-	movew	sp@(6), d1	/* x1 -> d1 */
-	muluw	sp@(8), d1	/* x1*y0 */
-#ifndef __mcf5200__
-	addw	d1, d0
-#else
-	addl	d1, d0
-#endif
-	swap	d0
-	clrw	d0
-	movew	sp@(6), d1	/* x1 -> d1 */
-	muluw	sp@(10), d1	/* x1*y1 */
-	addl	d1, d0
-
-	rts
-#endif /* L_mulsi3 */
-
-#ifdef  L_udivsi3
-	.text
-	.proc
-	.globl	SYM (__udivsi3)
-SYM (__udivsi3):
-#ifndef __mcf5200__
-	movel	d2, sp@-
-	movel	sp@(12), d1	/* d1 = divisor */
-	movel	sp@(8), d0	/* d0 = dividend */
-
-	cmpl	IMM (0x10000), d1 /* divisor >= 2 ^ 16 ?   */
-	jcc	L3		/* then try next algorithm */
-	movel	d0, d2
-	clrw	d2
-	swap	d2
-	divu	d1, d2          /* high quotient in lower word */
-	movew	d2, d0		/* save high quotient */
-	swap	d0
-	movew	sp@(10), d2	/* get low dividend + high rest */
-	divu	d1, d2		/* low quotient */
-	movew	d2, d0
-	jra	L6
-
-L3:	movel	d1, d2		/* use d2 as divisor backup */
-L4:	lsrl	IMM (1), d1	/* shift divisor */
-	lsrl	IMM (1), d0	/* shift dividend */
-	cmpl	IMM (0x10000), d1 /* still divisor >= 2 ^ 16 ?  */
-	jcc	L4
-	divu	d1, d0		/* now we have 16 bit divisor */
-	andl	IMM (0xffff), d0 /* mask out divisor, ignore remainder */
-
-/* Multiply the 16 bit tentative quotient with the 32 bit divisor.  Because of
-   the operand ranges, this might give a 33 bit product.  If this product is
-   greater than the dividend, the tentative quotient was too large. */
-	movel	d2, d1
-	mulu	d0, d1		/* low part, 32 bits */
-	swap	d2
-	mulu	d0, d2		/* high part, at most 17 bits */
-	swap	d2		/* align high part with low part */
-	tstw	d2		/* high part 17 bits? */
-	jne	L5		/* if 17 bits, quotient was too large */
-	addl	d2, d1		/* add parts */
-	jcs	L5		/* if sum is 33 bits, quotient was too large */
-	cmpl	sp@(8), d1	/* compare the sum with the dividend */
-	jls	L6		/* if sum > dividend, quotient was too large */
-L5:	subql	IMM (1), d0	/* adjust quotient */
-
-L6:	movel	sp@+, d2
-	rts
-
-#else /* __mcf5200__ */
-
-/* Coldfire implementation of non-restoring division algorithm from
-   Hennessy & Patterson, Appendix A. */
-	link	a6,IMM (-12)
-	moveml	d2-d4,sp@
-	movel	a6@(8),d0
-	movel	a6@(12),d1
-	clrl	d2		| clear p
-	moveq	IMM (31),d4
-L1:	addl	d0,d0		| shift reg pair (p,a) one bit left
-	addxl	d2,d2
-	movl	d2,d3		| subtract b from p, store in tmp.
-	subl	d1,d3
-	jcs	L2		| if no carry,
-	bset	IMM (0),d0	| set the low order bit of a to 1,
-	movl	d3,d2		| and store tmp in p.
-L2:	subql	IMM (1),d4
-	jcc	L1
-	moveml	sp@,d2-d4	| restore data registers
-	unlk	a6		| and return
-	rts
-#endif /* __mcf5200__ */
-
-#endif /* L_udivsi3 */
-
-#ifdef  L_divsi3
-	.text
-	.proc
-	.globl	SYM (__divsi3)
-SYM (__divsi3):
-	movel	d2, sp@-
-
-	moveq	IMM (1), d2	/* sign of result stored in d2 (=1 or =-1) */
-	movel	sp@(12), d1	/* d1 = divisor */
-	jpl	L1
-	negl	d1
-#ifndef __mcf5200__
-	negb	d2		/* change sign because divisor <0  */
-#else
-	negl	d2		/* change sign because divisor <0  */
-#endif
-L1:	movel	sp@(8), d0	/* d0 = dividend */
-	jpl	L2
-	negl	d0
-#ifndef __mcf5200__
-	negb	d2
-#else
-	negl	d2
-#endif
-
-L2:	movel	d1, sp@-
-	movel	d0, sp@-
-	jbsr	SYM (__udivsi3)	/* divide abs(dividend) by abs(divisor) */
-	addql	IMM (8), sp
-
-	tstb	d2
-	jpl	L3
-	negl	d0
-
-L3:	movel	sp@+, d2
-	rts
-#endif /* L_divsi3 */
-
-#ifdef  L_umodsi3
-	.text
-	.proc
-	.globl	SYM (__umodsi3)
-SYM (__umodsi3):
-	movel	sp@(8), d1	/* d1 = divisor */
-	movel	sp@(4), d0	/* d0 = dividend */
-	movel	d1, sp@-
-	movel	d0, sp@-
-	jbsr	SYM (__udivsi3)
-	addql	IMM (8), sp
-	movel	sp@(8), d1	/* d1 = divisor */
-#ifndef __mcf5200__
-	movel	d1, sp@-
-	movel	d0, sp@-
-	jbsr	SYM (__mulsi3)	/* d0 = (a/b)*b */
-	addql	IMM (8), sp
-#else
-	mulsl	d1,d0
-#endif
-	movel	sp@(4), d1	/* d1 = dividend */
-	subl	d0, d1		/* d1 = a - (a/b)*b */
-	movel	d1, d0
-	rts
-#endif /* L_umodsi3 */
-
-#ifdef  L_modsi3
-	.text
-	.proc
-	.globl	SYM (__modsi3)
-SYM (__modsi3):
-	movel	sp@(8), d1	/* d1 = divisor */
-	movel	sp@(4), d0	/* d0 = dividend */
-	movel	d1, sp@-
-	movel	d0, sp@-
-	jbsr	SYM (__divsi3)
-	addql	IMM (8), sp
-	movel	sp@(8), d1	/* d1 = divisor */
-#ifndef __mcf5200__
-	movel	d1, sp@-
-	movel	d0, sp@-
-	jbsr	SYM (__mulsi3)	/* d0 = (a/b)*b */
-	addql	IMM (8), sp
-#else
-	mulsl	d1,d0
-#endif
-	movel	sp@(4), d1	/* d1 = dividend */
-	subl	d0, d1		/* d1 = a - (a/b)*b */
-	movel	d1, d0
-	rts
-#endif /* L_modsi3 */
-
-
-#ifdef  L_double
-
-	.globl	SYM (_fpCCR)
-	.globl  $_exception_handler
-
-QUIET_NaN      = 0xffffffff
-
-D_MAX_EXP      = 0x07ff
-D_BIAS         = 1022
-DBL_MAX_EXP    = D_MAX_EXP - D_BIAS
-DBL_MIN_EXP    = 1 - D_BIAS
-DBL_MANT_DIG   = 53
-
-INEXACT_RESULT 		= 0x0001
-UNDERFLOW 		= 0x0002
-OVERFLOW 		= 0x0004
-DIVIDE_BY_ZERO 		= 0x0008
-INVALID_OPERATION 	= 0x0010
-
-DOUBLE_FLOAT = 2
-
-NOOP         = 0
-ADD          = 1
-MULTIPLY     = 2
-DIVIDE       = 3
-NEGATE       = 4
-COMPARE      = 5
-EXTENDSFDF   = 6
-TRUNCDFSF    = 7
-
-UNKNOWN           = -1
-ROUND_TO_NEAREST  = 0 | round result to nearest representable value
-ROUND_TO_ZERO     = 1 | round result towards zero
-ROUND_TO_PLUS     = 2 | round result towards plus infinity
-ROUND_TO_MINUS    = 3 | round result towards minus infinity
-
-| Entry points:
-
-	.globl SYM (__adddf3)
-	.globl SYM (__subdf3)
-	.globl SYM (__muldf3)
-	.globl SYM (__divdf3)
-	.globl SYM (__negdf2)
-	.globl SYM (__cmpdf2)
-
-	.text
-	.even
-
-| These are common routines to return and signal exceptions.	
-
-Ld$den:
-| Return and signal a denormalized number
-	orl	d7,d0
-	movew	IMM (INEXACT_RESULT+UNDERFLOW),d7
-	moveq	IMM (DOUBLE_FLOAT),d6
-	jmp	$_exception_handler
-
-Ld$infty:
-Ld$overflow:
-| Return a properly signed INFINITY and set the exception flags 
-	movel	IMM (0x7ff00000),d0
-	movel	IMM (0),d1
-	orl	d7,d0
-	movew	IMM (INEXACT_RESULT+OVERFLOW),d7
-	moveq	IMM (DOUBLE_FLOAT),d6
-	jmp	$_exception_handler
-
-Ld$underflow:
-| Return 0 and set the exception flags 
-	movel	IMM (0),d0
-	movel	d0,d1
-	movew	IMM (INEXACT_RESULT+UNDERFLOW),d7
-	moveq	IMM (DOUBLE_FLOAT),d6
-	jmp	$_exception_handler
-
-Ld$inop:
-| Return a quiet NaN and set the exception flags
-	movel	IMM (QUIET_NaN),d0
-	movel	d0,d1
-	movew	IMM (INEXACT_RESULT+INVALID_OPERATION),d7
-	moveq	IMM (DOUBLE_FLOAT),d6
-	jmp	$_exception_handler
-
-Ld$div$0:
-| Return a properly signed INFINITY and set the exception flags
-	movel	IMM (0x7ff00000),d0
-	movel	IMM (0),d1
-	orl	d7,d0
-	movew	IMM (INEXACT_RESULT+DIVIDE_BY_ZERO),d7
-	moveq	IMM (DOUBLE_FLOAT),d6
-	jmp	$_exception_handler
-
-|=============================================================================
-|=============================================================================
-|                         double precision routines
-|=============================================================================
-|=============================================================================
-
-| A double precision floating point number (double) has the format:
-|
-| struct _double {
-|  unsigned int sign      : 1;  /* sign bit */ 
-|  unsigned int exponent  : 11; /* exponent, shifted by 126 */
-|  unsigned int fraction  : 52; /* fraction */
-| } double;
-| 
-| Thus sizeof(double) = 8 (64 bits). 
-|
-| All the routines are callable from C programs, and return the result 
-| in the register pair d0-d1. They also preserve all registers except 
-| d0-d1 and a0-a1.
-
-|=============================================================================
-|                              __subdf3
-|=============================================================================
-
-| double __subdf3(double, double);
-SYM (__subdf3):
-	bchg	IMM (31),sp@(12) | change sign of second operand
-				| and fall through, so we always add
-|=============================================================================
-|                              __adddf3
-|=============================================================================
-
-| double __adddf3(double, double);
-SYM (__adddf3):
-#ifndef __mcf5200__
-	link	a6,IMM (0)	| everything will be done in registers
-	moveml	d2-d7,sp@-	| save all data registers and a2 (but d0-d1)
-#else
-	link	a6,IMM (-24)
-	moveml	d2-d7,sp@
-#endif
-	movel	a6@(8),d0	| get first operand
-	movel	a6@(12),d1	| 
-	movel	a6@(16),d2	| get second operand
-	movel	a6@(20),d3	| 
-
-	movel	d0,d7		| get d0's sign bit in d7 '
-	addl	d1,d1		| check and clear sign bit of a, and gain one
-	addxl	d0,d0		| bit of extra precision
-	beq	Ladddf$b	| if zero return second operand
-
-	movel	d2,d6		| save sign in d6 
-	addl	d3,d3		| get rid of sign bit and gain one bit of
-	addxl	d2,d2		| extra precision
-	beq	Ladddf$a	| if zero return first operand
-
-	andl	IMM (0x80000000),d7 | isolate a's sign bit '
-        swap	d6		| and also b's sign bit '
-#ifndef __mcf5200__
-	andw	IMM (0x8000),d6	|
-	orw	d6,d7		| and combine them into d7, so that a's sign '
-				| bit is in the high word and b's is in the '
-				| low word, so d6 is free to be used
-#else
-	andl	IMM (0x8000),d6
-	orl	d6,d7
-#endif
-	movel	d7,a0		| now save d7 into a0, so d7 is free to
-                		| be used also
-
-| Get the exponents and check for denormalized and/or infinity.
-
-	movel	IMM (0x001fffff),d6 | mask for the fraction
-	movel	IMM (0x00200000),d7 | mask to put hidden bit back
-
-	movel	d0,d4		| 
-	andl	d6,d0		| get fraction in d0
-	notl	d6		| make d6 into mask for the exponent
-	andl	d6,d4		| get exponent in d4
-	beq	Ladddf$a$den	| branch if a is denormalized
-	cmpl	d6,d4		| check for INFINITY or NaN
-	beq	Ladddf$nf       | 
-	orl	d7,d0		| and put hidden bit back
-Ladddf$1:
-	swap	d4		| shift right exponent so that it starts
-#ifndef __mcf5200__
-	lsrw	IMM (5),d4	| in bit 0 and not bit 20
-#else
-	lsrl	IMM (5),d4	| in bit 0 and not bit 20
-#endif
-| Now we have a's exponent in d4 and fraction in d0-d1 '
-	movel	d2,d5		| save b to get exponent
-	andl	d6,d5		| get exponent in d5
-	beq	Ladddf$b$den	| branch if b is denormalized
-	cmpl	d6,d5		| check for INFINITY or NaN
-	beq	Ladddf$nf
-	notl	d6		| make d6 into mask for the fraction again
-	andl	d6,d2		| and get fraction in d2
-	orl	d7,d2		| and put hidden bit back
-Ladddf$2:
-	swap	d5		| shift right exponent so that it starts
-#ifndef __mcf5200__
-	lsrw	IMM (5),d5	| in bit 0 and not bit 20
-#else
-	lsrl	IMM (5),d5	| in bit 0 and not bit 20
-#endif
-
-| Now we have b's exponent in d5 and fraction in d2-d3. '
-
-| The situation now is as follows: the signs are combined in a0, the 
-| numbers are in d0-d1 (a) and d2-d3 (b), and the exponents in d4 (a)
-| and d5 (b). To do the rounding correctly we need to keep all the
-| bits until the end, so we need to use d0-d1-d2-d3 for the first number
-| and d4-d5-d6-d7 for the second. To do this we store (temporarily) the
-| exponents in a2-a3.
-
-#ifndef __mcf5200__
-	moveml	a2-a3,sp@-	| save the address registers
-#else
-	movel	a2,sp@-	
-	movel	a3,sp@-	
-	movel	a4,sp@-	
-#endif
-
-	movel	d4,a2		| save the exponents
-	movel	d5,a3		| 
-
-	movel	IMM (0),d7	| and move the numbers around
-	movel	d7,d6		|
-	movel	d3,d5		|
-	movel	d2,d4		|
-	movel	d7,d3		|
-	movel	d7,d2		|
-
-| Here we shift the numbers until the exponents are the same, and put 
-| the largest exponent in a2.
-#ifndef __mcf5200__
-	exg	d4,a2		| get exponents back
-	exg	d5,a3		|
-	cmpw	d4,d5		| compare the exponents
-#else
-	movel	d4,a4		| get exponents back
-	movel	a2,d4
-	movel	a4,a2
-	movel	d5,a4
-	movel	a3,d5
-	movel	a4,a3
-	cmpl	d4,d5		| compare the exponents
-#endif
-	beq	Ladddf$3	| if equal don't shift '
-	bhi	9f		| branch if second exponent is higher
-
-| Here we have a's exponent larger than b's, so we have to shift b. We do 
-| this by using as counter d2:
-1:	movew	d4,d2		| move largest exponent to d2
-#ifndef __mcf5200__
-	subw	d5,d2		| and subtract second exponent
-	exg	d4,a2		| get back the longs we saved
-	exg	d5,a3		|
-#else
-	subl	d5,d2		| and subtract second exponent
-	movel	d4,a4		| get back the longs we saved
-	movel	a2,d4
-	movel	a4,a2
-	movel	d5,a4
-	movel	a3,d5
-	movel	a4,a3
-#endif
-| if difference is too large we don't shift (actually, we can just exit) '
-#ifndef __mcf5200__
-	cmpw	IMM (DBL_MANT_DIG+2),d2
-#else
-	cmpl	IMM (DBL_MANT_DIG+2),d2
-#endif
-	bge	Ladddf$b$small
-#ifndef __mcf5200__
-	cmpw	IMM (32),d2	| if difference >= 32, shift by longs
-#else
-	cmpl	IMM (32),d2	| if difference >= 32, shift by longs
-#endif
-	bge	5f
-2:
-#ifndef __mcf5200__
-	cmpw	IMM (16),d2	| if difference >= 16, shift by words	
-#else
-	cmpl	IMM (16),d2	| if difference >= 16, shift by words	
-#endif
-	bge	6f
-	bra	3f		| enter dbra loop
-
-4:
-#ifndef __mcf5200__
-	lsrl	IMM (1),d4
-	roxrl	IMM (1),d5
-	roxrl	IMM (1),d6
-	roxrl	IMM (1),d7
-#else
-	lsrl	IMM (1),d7
-	btst	IMM (0),d6
-	beq	10f
-	bset	IMM (31),d7
-10:	lsrl	IMM (1),d6
-	btst	IMM (0),d5
-	beq	11f
-	bset	IMM (31),d6
-11:	lsrl	IMM (1),d5
-	btst	IMM (0),d4
-	beq	12f
-	bset	IMM (31),d5
-12:	lsrl	IMM (1),d4
-#endif
-3:
-#ifndef __mcf5200__
-	dbra	d2,4b
-#else
-	subql	IMM (1),d2
-	bpl	4b	
-#endif
-	movel	IMM (0),d2
-	movel	d2,d3	
-	bra	Ladddf$4
-5:
-	movel	d6,d7
-	movel	d5,d6
-	movel	d4,d5
-	movel	IMM (0),d4
-#ifndef __mcf5200__
-	subw	IMM (32),d2
-#else
-	subl	IMM (32),d2
-#endif
-	bra	2b
-6:
-	movew	d6,d7
-	swap	d7
-	movew	d5,d6
-	swap	d6
-	movew	d4,d5
-	swap	d5
-	movew	IMM (0),d4
-	swap	d4
-#ifndef __mcf5200__
-	subw	IMM (16),d2
-#else
-	subl	IMM (16),d2
-#endif
-	bra	3b
-	
-9:
-#ifndef __mcf5200__
-	exg	d4,d5
-	movew	d4,d6
-	subw	d5,d6		| keep d5 (largest exponent) in d4
-	exg	d4,a2
-	exg	d5,a3
-#else
-	movel	d5,d6
-	movel	d4,d5
-	movel	d6,d4
-	subl	d5,d6
-	movel	d4,a4
-	movel	a2,d4
-	movel	a4,a2
-	movel	d5,a4
-	movel	a3,d5
-	movel	a4,a3
-#endif
-| if difference is too large we don't shift (actually, we can just exit) '
-#ifndef __mcf5200__
-	cmpw	IMM (DBL_MANT_DIG+2),d6
-#else
-	cmpl	IMM (DBL_MANT_DIG+2),d6
-#endif
-	bge	Ladddf$a$small
-#ifndef __mcf5200__
-	cmpw	IMM (32),d6	| if difference >= 32, shift by longs
-#else
-	cmpl	IMM (32),d6	| if difference >= 32, shift by longs
-#endif
-	bge	5f
-2:
-#ifndef __mcf5200__
-	cmpw	IMM (16),d6	| if difference >= 16, shift by words	
-#else
-	cmpl	IMM (16),d6	| if difference >= 16, shift by words	
-#endif
-	bge	6f
-	bra	3f		| enter dbra loop
-
-4:
-#ifndef __mcf5200__
-	lsrl	IMM (1),d0
-	roxrl	IMM (1),d1
-	roxrl	IMM (1),d2
-	roxrl	IMM (1),d3
-#else
-	lsrl	IMM (1),d3
-	btst	IMM (0),d2
-	beq	10f
-	bset	IMM (31),d3
-10:	lsrl	IMM (1),d2
-	btst	IMM (0),d1
-	beq	11f
-	bset	IMM (31),d2
-11:	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	12f
-	bset	IMM (31),d1
-12:	lsrl	IMM (1),d0
-#endif
-3:
-#ifndef __mcf5200__
-	dbra	d6,4b
-#else
-	subql	IMM (1),d6
-	bpl	4b
-#endif
-	movel	IMM (0),d7
-	movel	d7,d6
-	bra	Ladddf$4
-5:
-	movel	d2,d3
-	movel	d1,d2
-	movel	d0,d1
-	movel	IMM (0),d0
-#ifndef __mcf5200__
-	subw	IMM (32),d6
-#else
-	subl	IMM (32),d6
-#endif
-	bra	2b
-6:
-	movew	d2,d3
-	swap	d3
-	movew	d1,d2
-	swap	d2
-	movew	d0,d1
-	swap	d1
-	movew	IMM (0),d0
-	swap	d0
-#ifndef __mcf5200__
-	subw	IMM (16),d6
-#else
-	subl	IMM (16),d6
-#endif
-	bra	3b
-Ladddf$3:
-#ifndef __mcf5200__
-	exg	d4,a2	
-	exg	d5,a3
-#else
-	movel	d4,a4
-	movel	a2,d4
-	movel	a4,a2
-	movel	d5,a4
-	movel	a3,d5
-	movel	a4,a3
-#endif
-Ladddf$4:	
-| Now we have the numbers in d0--d3 and d4--d7, the exponent in a2, and
-| the signs in a4.
-
-| Here we have to decide whether to add or subtract the numbers:
-#ifndef __mcf5200__
-	exg	d7,a0		| get the signs 
-	exg	d6,a3		| a3 is free to be used
-#else
-	movel	d7,a4
-	movel	a0,d7
-	movel	a4,a0
-	movel	d6,a4
-	movel	a3,d6
-	movel	a4,a3
-#endif
-	movel	d7,d6		|
-	movew	IMM (0),d7	| get a's sign in d7 '
-	swap	d6              |
-	movew	IMM (0),d6	| and b's sign in d6 '
-	eorl	d7,d6		| compare the signs
-	bmi	Lsubdf$0	| if the signs are different we have 
-				| to subtract
-#ifndef __mcf5200__
-	exg	d7,a0		| else we add the numbers
-	exg	d6,a3		|
-#else
-	movel	d7,a4
-	movel	a0,d7
-	movel	a4,a0
-	movel	d6,a4
-	movel	a3,d6
-	movel	a4,a3
-#endif
-	addl	d7,d3		|
-	addxl	d6,d2		|
-	addxl	d5,d1		| 
-	addxl	d4,d0           |
-
-	movel	a2,d4		| return exponent to d4
-	movel	a0,d7		| 
-	andl	IMM (0x80000000),d7 | d7 now has the sign
-
-#ifndef __mcf5200__
-	moveml	sp@+,a2-a3	
-#else
-	movel	sp@+,a4	
-	movel	sp@+,a3	
-	movel	sp@+,a2	
-#endif
-
-| Before rounding normalize so bit #DBL_MANT_DIG is set (we will consider
-| the case of denormalized numbers in the rounding routine itself).
-| As in the addition (not in the subtraction!) we could have set 
-| one more bit we check this:
-	btst	IMM (DBL_MANT_DIG+1),d0	
-	beq	1f
-#ifndef __mcf5200__
-	lsrl	IMM (1),d0
-	roxrl	IMM (1),d1
-	roxrl	IMM (1),d2
-	roxrl	IMM (1),d3
-	addw	IMM (1),d4
-#else
-	lsrl	IMM (1),d3
-	btst	IMM (0),d2
-	beq	10f
-	bset	IMM (31),d3
-10:	lsrl	IMM (1),d2
-	btst	IMM (0),d1
-	beq	11f
-	bset	IMM (31),d2
-11:	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	12f
-	bset	IMM (31),d1
-12:	lsrl	IMM (1),d0
-	addl	IMM (1),d4
-#endif
-1:
-	lea	Ladddf$5,a0	| to return from rounding routine
-	lea	SYM (_fpCCR),a1	| check the rounding mode
-#ifdef __mcf5200__
-	clrl	d6
-#endif
-	movew	a1@(6),d6	| rounding mode in d6
-	beq	Lround$to$nearest
-#ifndef __mcf5200__
-	cmpw	IMM (ROUND_TO_PLUS),d6
-#else
-	cmpl	IMM (ROUND_TO_PLUS),d6
-#endif
-	bhi	Lround$to$minus
-	blt	Lround$to$zero
-	bra	Lround$to$plus
-Ladddf$5:
-| Put back the exponent and check for overflow
-#ifndef __mcf5200__
-	cmpw	IMM (0x7ff),d4	| is the exponent big?
-#else
-	cmpl	IMM (0x7ff),d4	| is the exponent big?
-#endif
-	bge	1f
-	bclr	IMM (DBL_MANT_DIG-1),d0
-#ifndef __mcf5200__
-	lslw	IMM (4),d4	| put exponent back into position
-#else
-	lsll	IMM (4),d4	| put exponent back into position
-#endif
-	swap	d0		| 
-#ifndef __mcf5200__
-	orw	d4,d0		|
-#else
-	orl	d4,d0		|
-#endif
-	swap	d0		|
-	bra	Ladddf$ret
-1:
-	movew	IMM (ADD),d5
-	bra	Ld$overflow
-
-Lsubdf$0:
-| Here we do the subtraction.
-#ifndef __mcf5200__
-	exg	d7,a0		| put sign back in a0
-	exg	d6,a3		|
-#else
-	movel	d7,a4
-	movel	a0,d7
-	movel	a4,a0
-	movel	d6,a4
-	movel	a3,d6
-	movel	a4,a3
-#endif
-	subl	d7,d3		|
-	subxl	d6,d2		|
-	subxl	d5,d1		|
-	subxl	d4,d0		|
-	beq	Ladddf$ret$1	| if zero just exit
-	bpl	1f		| if positive skip the following
-	movel	a0,d7		|
-	bchg	IMM (31),d7	| change sign bit in d7
-	movel	d7,a0		|
-	negl	d3		|
-	negxl	d2		|
-	negxl	d1              | and negate result
-	negxl	d0              |
-1:	
-	movel	a2,d4		| return exponent to d4
-	movel	a0,d7
-	andl	IMM (0x80000000),d7 | isolate sign bit
-#ifndef __mcf5200__
-	moveml	sp@+,a2-a3	|
-#else
-	movel	sp@+,a4
-	movel	sp@+,a3
-	movel	sp@+,a2
-#endif
-
-| Before rounding normalize so bit #DBL_MANT_DIG is set (we will consider
-| the case of denormalized numbers in the rounding routine itself).
-| As in the addition (not in the subtraction!) we could have set 
-| one more bit we check this:
-	btst	IMM (DBL_MANT_DIG+1),d0	
-	beq	1f
-#ifndef __mcf5200__
-	lsrl	IMM (1),d0
-	roxrl	IMM (1),d1
-	roxrl	IMM (1),d2
-	roxrl	IMM (1),d3
-	addw	IMM (1),d4
-#else
-	lsrl	IMM (1),d3
-	btst	IMM (0),d2
-	beq	10f
-	bset	IMM (31),d3
-10:	lsrl	IMM (1),d2
-	btst	IMM (0),d1
-	beq	11f
-	bset	IMM (31),d2
-11:	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	12f
-	bset	IMM (31),d1
-12:	lsrl	IMM (1),d0
-	addl	IMM (1),d4
-#endif
-1:
-	lea	Lsubdf$1,a0	| to return from rounding routine
-	lea	SYM (_fpCCR),a1	| check the rounding mode
-#ifdef __mcf5200__
-	clrl	d6
-#endif
-	movew	a1@(6),d6	| rounding mode in d6
-	beq	Lround$to$nearest
-#ifndef __mcf5200__
-	cmpw	IMM (ROUND_TO_PLUS),d6
-#else
-	cmpl	IMM (ROUND_TO_PLUS),d6
-#endif
-	bhi	Lround$to$minus
-	blt	Lround$to$zero
-	bra	Lround$to$plus
-Lsubdf$1:
-| Put back the exponent and sign (we don't have overflow). '
-	bclr	IMM (DBL_MANT_DIG-1),d0	
-#ifndef __mcf5200__
-	lslw	IMM (4),d4	| put exponent back into position
-#else
-	lsll	IMM (4),d4	| put exponent back into position
-#endif
-	swap	d0		| 
-#ifndef __mcf5200__
-	orw	d4,d0		|
-#else
-	orl	d4,d0		|
-#endif
-	swap	d0		|
-	bra	Ladddf$ret
-
-| If one of the numbers was too small (difference of exponents >= 
-| DBL_MANT_DIG+1) we return the other (and now we don't have to '
-| check for finiteness or zero).
-Ladddf$a$small:
-#ifndef __mcf5200__
-	moveml	sp@+,a2-a3	
-#else
-	movel	sp@+,a4
-	movel	sp@+,a3
-	movel	sp@+,a2
-#endif
-	movel	a6@(16),d0
-	movel	a6@(20),d1
-	lea	SYM (_fpCCR),a0
-	movew	IMM (0),a0@
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7	| restore data registers
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6		| and return
-	rts
-
-Ladddf$b$small:
-#ifndef __mcf5200__
-	moveml	sp@+,a2-a3	
-#else
-	movel	sp@+,a4	
-	movel	sp@+,a3	
-	movel	sp@+,a2	
-#endif
-	movel	a6@(8),d0
-	movel	a6@(12),d1
-	lea	SYM (_fpCCR),a0
-	movew	IMM (0),a0@
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7	| restore data registers
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6		| and return
-	rts
-
-Ladddf$a$den:
-	movel	d7,d4		| d7 contains 0x00200000
-	bra	Ladddf$1
-
-Ladddf$b$den:
-	movel	d7,d5           | d7 contains 0x00200000
-	notl	d6
-	bra	Ladddf$2
-
-Ladddf$b:
-| Return b (if a is zero)
-	movel	d2,d0
-	movel	d3,d1
-	bra	1f
-Ladddf$a:
-	movel	a6@(8),d0
-	movel	a6@(12),d1
-1:
-	movew	IMM (ADD),d5
-| Check for NaN and +/-INFINITY.
-	movel	d0,d7         		|
-	andl	IMM (0x80000000),d7	|
-	bclr	IMM (31),d0		|
-	cmpl	IMM (0x7ff00000),d0	|
-	bge	2f			|
-	movel	d0,d0           	| check for zero, since we don't  '
-	bne	Ladddf$ret		| want to return -0 by mistake
-	bclr	IMM (31),d7		|
-	bra	Ladddf$ret		|
-2:
-	andl	IMM (0x000fffff),d0	| check for NaN (nonzero fraction)
-	orl	d1,d0			|
-	bne	Ld$inop         	|
-	bra	Ld$infty		|
-	
-Ladddf$ret$1:
-#ifndef __mcf5200__
-	moveml	sp@+,a2-a3	| restore regs and exit
-#else
-	movel	sp@+,a4
-	movel	sp@+,a3
-	movel	sp@+,a2
-#endif
-
-Ladddf$ret:
-| Normal exit.
-	lea	SYM (_fpCCR),a0
-	movew	IMM (0),a0@
-	orl	d7,d0		| put sign bit back
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6
-	rts
-
-Ladddf$ret$den:
-| Return a denormalized number.
-#ifndef __mcf5200__
-	lsrl	IMM (1),d0	| shift right once more
-	roxrl	IMM (1),d1	|
-#else
-	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	10f
-	bset	IMM (31),d1
-10:	lsrl	IMM (1),d0
-#endif
-	bra	Ladddf$ret
-
-Ladddf$nf:
-	movew	IMM (ADD),d5
-| This could be faster but it is not worth the effort, since it is not
-| executed very often. We sacrifice speed for clarity here.
-	movel	a6@(8),d0	| get the numbers back (remember that we
-	movel	a6@(12),d1	| did some processing already)
-	movel	a6@(16),d2	| 
-	movel	a6@(20),d3	| 
-	movel	IMM (0x7ff00000),d4 | useful constant (INFINITY)
-	movel	d0,d7		| save sign bits
-	movel	d2,d6		| 
-	bclr	IMM (31),d0	| clear sign bits
-	bclr	IMM (31),d2	| 
-| We know that one of them is either NaN of +/-INFINITY
-| Check for NaN (if either one is NaN return NaN)
-	cmpl	d4,d0		| check first a (d0)
-	bhi	Ld$inop		| if d0 > 0x7ff00000 or equal and
-	bne	2f
-	tstl	d1		| d1 > 0, a is NaN
-	bne	Ld$inop		| 
-2:	cmpl	d4,d2		| check now b (d1)
-	bhi	Ld$inop		| 
-	bne	3f
-	tstl	d3		| 
-	bne	Ld$inop		| 
-3:
-| Now comes the check for +/-INFINITY. We know that both are (maybe not
-| finite) numbers, but we have to check if both are infinite whether we
-| are adding or subtracting them.
-	eorl	d7,d6		| to check sign bits
-	bmi	1f
-	andl	IMM (0x80000000),d7 | get (common) sign bit
-	bra	Ld$infty
-1:
-| We know one (or both) are infinite, so we test for equality between the
-| two numbers (if they are equal they have to be infinite both, so we
-| return NaN).
-	cmpl	d2,d0		| are both infinite?
-	bne	1f		| if d0 <> d2 they are not equal
-	cmpl	d3,d1		| if d0 == d2 test d3 and d1
-	beq	Ld$inop		| if equal return NaN
-1:	
-	andl	IMM (0x80000000),d7 | get a's sign bit '
-	cmpl	d4,d0		| test now for infinity
-	beq	Ld$infty	| if a is INFINITY return with this sign
-	bchg	IMM (31),d7	| else we know b is INFINITY and has
-	bra	Ld$infty	| the opposite sign
-
-|=============================================================================
-|                              __muldf3
-|=============================================================================
-
-| double __muldf3(double, double);
-SYM (__muldf3):
-#ifndef __mcf5200__
-	link	a6,IMM (0)
-	moveml	d2-d7,sp@-
-#else
-	link	a6,IMM (-24)
-	moveml	d2-d7,sp@
-#endif
-	movel	a6@(8),d0		| get a into d0-d1
-	movel	a6@(12),d1		| 
-	movel	a6@(16),d2		| and b into d2-d3
-	movel	a6@(20),d3		|
-	movel	d0,d7			| d7 will hold the sign of the product
-	eorl	d2,d7			|
-	andl	IMM (0x80000000),d7	|
-	movel	d7,a0			| save sign bit into a0 
-	movel	IMM (0x7ff00000),d7	| useful constant (+INFINITY)
-	movel	d7,d6			| another (mask for fraction)
-	notl	d6			|
-	bclr	IMM (31),d0		| get rid of a's sign bit '
-	movel	d0,d4			| 
-	orl	d1,d4			| 
-	beq	Lmuldf$a$0		| branch if a is zero
-	movel	d0,d4			|
-	bclr	IMM (31),d2		| get rid of b's sign bit '
-	movel	d2,d5			|
-	orl	d3,d5			| 
-	beq	Lmuldf$b$0		| branch if b is zero
-	movel	d2,d5			| 
-	cmpl	d7,d0			| is a big?
-	bhi	Lmuldf$inop		| if a is NaN return NaN
-	beq	Lmuldf$a$nf		| we still have to check d1 and b ...
-	cmpl	d7,d2			| now compare b with INFINITY
-	bhi	Lmuldf$inop		| is b NaN?
-	beq	Lmuldf$b$nf 		| we still have to check d3 ...
-| Here we have both numbers finite and nonzero (and with no sign bit).
-| Now we get the exponents into d4 and d5.
-	andl	d7,d4			| isolate exponent in d4
-	beq	Lmuldf$a$den		| if exponent zero, have denormalized
-	andl	d6,d0			| isolate fraction
-	orl	IMM (0x00100000),d0	| and put hidden bit back
-	swap	d4			| I like exponents in the first byte
-#ifndef __mcf5200__
-	lsrw	IMM (4),d4		| 
-#else
-	lsrl	IMM (4),d4		| 
-#endif
-Lmuldf$1:			
-	andl	d7,d5			|
-	beq	Lmuldf$b$den		|
-	andl	d6,d2			|
-	orl	IMM (0x00100000),d2	| and put hidden bit back
-	swap	d5			|
-#ifndef __mcf5200__
-	lsrw	IMM (4),d5		|
-#else
-	lsrl	IMM (4),d5		|
-#endif
-Lmuldf$2:				|
-#ifndef __mcf5200__
-	addw	d5,d4			| add exponents
-	subw	IMM (D_BIAS+1),d4	| and subtract bias (plus one)
-#else
-	addl	d5,d4			| add exponents
-	subl	IMM (D_BIAS+1),d4	| and subtract bias (plus one)
-#endif
-
-| We are now ready to do the multiplication. The situation is as follows:
-| both a and b have bit 52 ( bit 20 of d0 and d2) set (even if they were 
-| denormalized to start with!), which means that in the product bit 104 
-| (which will correspond to bit 8 of the fourth long) is set.
-
-| Here we have to do the product.
-| To do it we have to juggle the registers back and forth, as there are not
-| enough to keep everything in them. So we use the address registers to keep
-| some intermediate data.
-
-#ifndef __mcf5200__
-	moveml	a2-a3,sp@-	| save a2 and a3 for temporary use
-#else
-	movel	a2,sp@-
-	movel	a3,sp@-
-	movel	a4,sp@-
-#endif
-	movel	IMM (0),a2	| a2 is a null register
-	movel	d4,a3		| and a3 will preserve the exponent
-
-| First, shift d2-d3 so bit 20 becomes bit 31:
-#ifndef __mcf5200__
-	rorl	IMM (5),d2	| rotate d2 5 places right
-	swap	d2		| and swap it
-	rorl	IMM (5),d3	| do the same thing with d3
-	swap	d3		|
-	movew	d3,d6		| get the rightmost 11 bits of d3
-	andw	IMM (0x07ff),d6	|
-	orw	d6,d2		| and put them into d2
-	andw	IMM (0xf800),d3	| clear those bits in d3
-#else
-	moveq	IMM (11),d7	| left shift d2 11 bits
-	lsll	d7,d2
-	movel	d3,d6		| get a copy of d3
-	lsll	d7,d3		| left shift d3 11 bits
-	andl	IMM (0xffe00000),d6 | get the top 11 bits of d3
-	moveq	IMM (21),d7	| right shift them 21 bits
-	lsrl	d7,d6
-	orl	d6,d2		| stick them at the end of d2
-#endif
-
-	movel	d2,d6		| move b into d6-d7
-	movel	d3,d7           | move a into d4-d5
-	movel	d0,d4           | and clear d0-d1-d2-d3 (to put result)
-	movel	d1,d5           |
-	movel	IMM (0),d3	|
-	movel	d3,d2           |
-	movel	d3,d1           |
-	movel	d3,d0	        |
-
-| We use a1 as counter:	
-	movel	IMM (DBL_MANT_DIG-1),a1		
-#ifndef __mcf5200__
-	exg	d7,a1
-#else
-	movel	d7,a4
-	movel	a1,d7
-	movel	a4,a1
-#endif
-
-1:
-#ifndef __mcf5200__
-	exg	d7,a1		| put counter back in a1
-#else
-	movel	d7,a4
-	movel	a1,d7
-	movel	a4,a1
-#endif
-	addl	d3,d3		| shift sum once left
-	addxl	d2,d2           |
-	addxl	d1,d1           |
-	addxl	d0,d0           |
-	addl	d7,d7		|
-	addxl	d6,d6		|
-	bcc	2f		| if bit clear skip the following
-#ifndef __mcf5200__
-	exg	d7,a2		|
-#else
-	movel	d7,a4
-	movel	a2,d7
-	movel	a4,a2
-#endif
-	addl	d5,d3		| else add a to the sum
-	addxl	d4,d2		|
-	addxl	d7,d1		|
-	addxl	d7,d0		|
-#ifndef __mcf5200__
-	exg	d7,a2		| 
-#else
-	movel	d7,a4
-	movel	a2,d7
-	movel	a4,a2
-#endif
-2:
-#ifndef __mcf5200__
-	exg	d7,a1		| put counter in d7
-	dbf	d7,1b		| decrement and branch
-#else
-	movel	d7,a4
-	movel	a1,d7
-	movel	a4,a1
-	subql	IMM (1),d7
-	bpl	1b
-#endif
-
-	movel	a3,d4		| restore exponent
-#ifndef __mcf5200__
-	moveml	sp@+,a2-a3
-#else
-	movel	sp@+,a4
-	movel	sp@+,a3
-	movel	sp@+,a2
-#endif
-
-| Now we have the product in d0-d1-d2-d3, with bit 8 of d0 set. The 
-| first thing to do now is to normalize it so bit 8 becomes bit 
-| DBL_MANT_DIG-32 (to do the rounding); later we will shift right.
-	swap	d0
-	swap	d1
-	movew	d1,d0
-	swap	d2
-	movew	d2,d1
-	swap	d3
-	movew	d3,d2
-	movew	IMM (0),d3
-#ifndef __mcf5200__
-	lsrl	IMM (1),d0
-	roxrl	IMM (1),d1
-	roxrl	IMM (1),d2
-	roxrl	IMM (1),d3
-	lsrl	IMM (1),d0
-	roxrl	IMM (1),d1
-	roxrl	IMM (1),d2
-	roxrl	IMM (1),d3
-	lsrl	IMM (1),d0
-	roxrl	IMM (1),d1
-	roxrl	IMM (1),d2
-	roxrl	IMM (1),d3
-#else
-	moveq	IMM (29),d6
-	lsrl	IMM (3),d3
-	movel	d2,d7
-	lsll	d6,d7
-	orl	d7,d3
-	lsrl	IMM (3),d2
-	movel	d1,d7
-	lsll	d6,d7
-	orl	d7,d2
-	lsrl	IMM (3),d1
-	movel	d0,d7
-	lsll	d6,d7
-	orl	d7,d1
-	lsrl	IMM (3),d0
-#endif
-	
-| Now round, check for over- and underflow, and exit.
-	movel	a0,d7		| get sign bit back into d7
-	movew	IMM (MULTIPLY),d5
-
-	btst	IMM (DBL_MANT_DIG+1-32),d0
-	beq	Lround$exit
-#ifndef __mcf5200__
-	lsrl	IMM (1),d0
-	roxrl	IMM (1),d1
-	addw	IMM (1),d4
-#else
-	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	10f
-	bset	IMM (31),d1
-10:	lsrl	IMM (1),d0
-	addl	IMM (1),d4
-#endif
-	bra	Lround$exit
-
-Lmuldf$inop:
-	movew	IMM (MULTIPLY),d5
-	bra	Ld$inop
-
-Lmuldf$b$nf:
-	movew	IMM (MULTIPLY),d5
-	movel	a0,d7		| get sign bit back into d7
-	tstl	d3		| we know d2 == 0x7ff00000, so check d3
-	bne	Ld$inop		| if d3 <> 0 b is NaN
-	bra	Ld$overflow	| else we have overflow (since a is finite)
-
-Lmuldf$a$nf:
-	movew	IMM (MULTIPLY),d5
-	movel	a0,d7		| get sign bit back into d7
-	tstl	d1		| we know d0 == 0x7ff00000, so check d1
-	bne	Ld$inop		| if d1 <> 0 a is NaN
-	bra	Ld$overflow	| else signal overflow
-
-| If either number is zero return zero, unless the other is +/-INFINITY or
-| NaN, in which case we return NaN.
-Lmuldf$b$0:
-	movew	IMM (MULTIPLY),d5
-#ifndef __mcf5200__
-	exg	d2,d0		| put b (==0) into d0-d1
-	exg	d3,d1		| and a (with sign bit cleared) into d2-d3
-#else
-	movel	d2,d7
-	movel	d0,d2
-	movel	d7,d0
-	movel	d3,d7
-	movel	d1,d3
-	movel	d7,d1
-#endif
-	bra	1f
-Lmuldf$a$0:
-	movel	a6@(16),d2	| put b into d2-d3 again
-	movel	a6@(20),d3	|
-	bclr	IMM (31),d2	| clear sign bit
-1:	cmpl	IMM (0x7ff00000),d2 | check for non-finiteness
-	bge	Ld$inop		| in case NaN or +/-INFINITY return NaN
-	lea	SYM (_fpCCR),a0
-	movew	IMM (0),a0@
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6
-	rts
-
-| If a number is denormalized we put an exponent of 1 but do not put the 
-| hidden bit back into the fraction; instead we shift left until bit 21
-| (the hidden bit) is set, adjusting the exponent accordingly. We do this
-| to ensure that the product of the fractions is close to 1.
-Lmuldf$a$den:
-	movel	IMM (1),d4
-	andl	d6,d0
-1:	addl	d1,d1           | shift a left until bit 20 is set
-	addxl	d0,d0		|
-#ifndef __mcf5200__
-	subw	IMM (1),d4	| and adjust exponent
-#else
-	subl	IMM (1),d4	| and adjust exponent
-#endif
-	btst	IMM (20),d0	|
-	bne	Lmuldf$1        |
-	bra	1b
-
-Lmuldf$b$den:
-	movel	IMM (1),d5
-	andl	d6,d2
-1:	addl	d3,d3		| shift b left until bit 20 is set
-	addxl	d2,d2		|
-#ifndef __mcf5200__
-	subw	IMM (1),d5	| and adjust exponent
-#else
-	subql	IMM (1),d5	| and adjust exponent
-#endif
-	btst	IMM (20),d2	|
-	bne	Lmuldf$2	|
-	bra	1b
-
-
-|=============================================================================
-|                              __divdf3
-|=============================================================================
-
-| double __divdf3(double, double);
-SYM (__divdf3):
-#ifndef __mcf5200__
-	link	a6,IMM (0)
-	moveml	d2-d7,sp@-
-#else
-	link	a6,IMM (-24)
-	moveml	d2-d7,sp@
-#endif
-	movel	a6@(8),d0	| get a into d0-d1
-	movel	a6@(12),d1	| 
-	movel	a6@(16),d2	| and b into d2-d3
-	movel	a6@(20),d3	|
-	movel	d0,d7		| d7 will hold the sign of the result
-	eorl	d2,d7		|
-	andl	IMM (0x80000000),d7
-	movel	d7,a0		| save sign into a0
-	movel	IMM (0x7ff00000),d7 | useful constant (+INFINITY)
-	movel	d7,d6		| another (mask for fraction)
-	notl	d6		|
-	bclr	IMM (31),d0	| get rid of a's sign bit '
-	movel	d0,d4		|
-	orl	d1,d4		|
-	beq	Ldivdf$a$0	| branch if a is zero
-	movel	d0,d4		|
-	bclr	IMM (31),d2	| get rid of b's sign bit '
-	movel	d2,d5		|
-	orl	d3,d5		|
-	beq	Ldivdf$b$0	| branch if b is zero
-	movel	d2,d5
-	cmpl	d7,d0		| is a big?
-	bhi	Ldivdf$inop	| if a is NaN return NaN
-	beq	Ldivdf$a$nf	| if d0 == 0x7ff00000 we check d1
-	cmpl	d7,d2		| now compare b with INFINITY 
-	bhi	Ldivdf$inop	| if b is NaN return NaN
-	beq	Ldivdf$b$nf	| if d2 == 0x7ff00000 we check d3
-| Here we have both numbers finite and nonzero (and with no sign bit).
-| Now we get the exponents into d4 and d5 and normalize the numbers to
-| ensure that the ratio of the fractions is around 1. We do this by
-| making sure that both numbers have bit #DBL_MANT_DIG-32-1 (hidden bit)
-| set, even if they were denormalized to start with.
-| Thus, the result will satisfy: 2 > result > 1/2.
-	andl	d7,d4		| and isolate exponent in d4
-	beq	Ldivdf$a$den	| if exponent is zero we have a denormalized
-	andl	d6,d0		| and isolate fraction
-	orl	IMM (0x00100000),d0 | and put hidden bit back
-	swap	d4		| I like exponents in the first byte
-#ifndef __mcf5200__
-	lsrw	IMM (4),d4	| 
-#else
-	lsrl	IMM (4),d4	| 
-#endif
-Ldivdf$1:			| 
-	andl	d7,d5		|
-	beq	Ldivdf$b$den	|
-	andl	d6,d2		|
-	orl	IMM (0x00100000),d2
-	swap	d5		|
-#ifndef __mcf5200__
-	lsrw	IMM (4),d5	|
-#else
-	lsrl	IMM (4),d5	|
-#endif
-Ldivdf$2:			|
-#ifndef __mcf5200__
-	subw	d5,d4		| subtract exponents
-	addw	IMM (D_BIAS),d4	| and add bias
-#else
-	subl	d5,d4		| subtract exponents
-	addl	IMM (D_BIAS),d4	| and add bias
-#endif
-
-| We are now ready to do the division. We have prepared things in such a way
-| that the ratio of the fractions will be less than 2 but greater than 1/2.
-| At this point the registers in use are:
-| d0-d1	hold a (first operand, bit DBL_MANT_DIG-32=0, bit 
-| DBL_MANT_DIG-1-32=1)
-| d2-d3	hold b (second operand, bit DBL_MANT_DIG-32=1)
-| d4	holds the difference of the exponents, corrected by the bias
-| a0	holds the sign of the ratio
-
-| To do the rounding correctly we need to keep information about the
-| nonsignificant bits. One way to do this would be to do the division
-| using four registers; another is to use two registers (as originally
-| I did), but use a sticky bit to preserve information about the 
-| fractional part. Note that we can keep that info in a1, which is not
-| used.
-	movel	IMM (0),d6	| d6-d7 will hold the result
-	movel	d6,d7		| 
-	movel	IMM (0),a1	| and a1 will hold the sticky bit
-
-	movel	IMM (DBL_MANT_DIG-32+1),d5	
-	
-1:	cmpl	d0,d2		| is a < b?
-	bhi	3f		| if b > a skip the following
-	beq	4f		| if d0==d2 check d1 and d3
-2:	subl	d3,d1		| 
-	subxl	d2,d0		| a <-- a - b
-	bset	d5,d6		| set the corresponding bit in d6
-3:	addl	d1,d1		| shift a by 1
-	addxl	d0,d0		|
-#ifndef __mcf5200__
-	dbra	d5,1b		| and branch back
-#else
-	subql	IMM (1), d5
-	bpl	1b
-#endif
-	bra	5f			
-4:	cmpl	d1,d3		| here d0==d2, so check d1 and d3
-	bhi	3b		| if d1 > d2 skip the subtraction
-	bra	2b		| else go do it
-5:
-| Here we have to start setting the bits in the second long.
-	movel	IMM (31),d5	| again d5 is counter
-
-1:	cmpl	d0,d2		| is a < b?
-	bhi	3f		| if b > a skip the following
-	beq	4f		| if d0==d2 check d1 and d3
-2:	subl	d3,d1		| 
-	subxl	d2,d0		| a <-- a - b
-	bset	d5,d7		| set the corresponding bit in d7
-3:	addl	d1,d1		| shift a by 1
-	addxl	d0,d0		|
-#ifndef __mcf5200__
-	dbra	d5,1b		| and branch back
-#else
-	subql	IMM (1), d5
-	bpl	1b
-#endif
-	bra	5f			
-4:	cmpl	d1,d3		| here d0==d2, so check d1 and d3
-	bhi	3b		| if d1 > d2 skip the subtraction
-	bra	2b		| else go do it
-5:
-| Now go ahead checking until we hit a one, which we store in d2.
-	movel	IMM (DBL_MANT_DIG),d5
-1:	cmpl	d2,d0		| is a < b?
-	bhi	4f		| if b < a, exit
-	beq	3f		| if d0==d2 check d1 and d3
-2:	addl	d1,d1		| shift a by 1
-	addxl	d0,d0		|
-#ifndef __mcf5200__
-	dbra	d5,1b		| and branch back
-#else
-	subql	IMM (1), d5
-	bpl	1b
-#endif
-	movel	IMM (0),d2	| here no sticky bit was found
-	movel	d2,d3
-	bra	5f			
-3:	cmpl	d1,d3		| here d0==d2, so check d1 and d3
-	bhi	2b		| if d1 > d2 go back
-4:
-| Here put the sticky bit in d2-d3 (in the position which actually corresponds
-| to it; if you don't do this the algorithm loses in some cases). '
-	movel	IMM (0),d2
-	movel	d2,d3
-#ifndef __mcf5200__
-	subw	IMM (DBL_MANT_DIG),d5
-	addw	IMM (63),d5
-	cmpw	IMM (31),d5
-#else
-	subl	IMM (DBL_MANT_DIG),d5
-	addl	IMM (63),d5
-	cmpl	IMM (31),d5
-#endif
-	bhi	2f
-1:	bset	d5,d3
-	bra	5f
-#ifndef __mcf5200__
-	subw	IMM (32),d5
-#else
-	subl	IMM (32),d5
-#endif
-2:	bset	d5,d2
-5:
-| Finally we are finished! Move the longs in the address registers to
-| their final destination:
-	movel	d6,d0
-	movel	d7,d1
-	movel	IMM (0),d3
-
-| Here we have finished the division, with the result in d0-d1-d2-d3, with
-| 2^21 <= d6 < 2^23. Thus bit 23 is not set, but bit 22 could be set.
-| If it is not, then definitely bit 21 is set. Normalize so bit 22 is
-| not set:
-	btst	IMM (DBL_MANT_DIG-32+1),d0
-	beq	1f
-#ifndef __mcf5200__
-	lsrl	IMM (1),d0
-	roxrl	IMM (1),d1
-	roxrl	IMM (1),d2
-	roxrl	IMM (1),d3
-	addw	IMM (1),d4
-#else
-	lsrl	IMM (1),d3
-	btst	IMM (0),d2
-	beq	10f
-	bset	IMM (31),d3
-10:	lsrl	IMM (1),d2
-	btst	IMM (0),d1
-	beq	11f
-	bset	IMM (31),d2
-11:	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	12f
-	bset	IMM (31),d1
-12:	lsrl	IMM (1),d0
-	addl	IMM (1),d4
-#endif
-1:
-| Now round, check for over- and underflow, and exit.
-	movel	a0,d7		| restore sign bit to d7
-	movew	IMM (DIVIDE),d5
-	bra	Lround$exit
-
-Ldivdf$inop:
-	movew	IMM (DIVIDE),d5
-	bra	Ld$inop
-
-Ldivdf$a$0:
-| If a is zero check to see whether b is zero also. In that case return
-| NaN; then check if b is NaN, and return NaN also in that case. Else
-| return zero.
-	movew	IMM (DIVIDE),d5
-	bclr	IMM (31),d2	|
-	movel	d2,d4		| 
-	orl	d3,d4		| 
-	beq	Ld$inop		| if b is also zero return NaN
-	cmpl	IMM (0x7ff00000),d2 | check for NaN
-	bhi	Ld$inop		| 
-	blt	1f		|
-	tstl	d3		|
-	bne	Ld$inop		|
-1:	movel	IMM (0),d0	| else return zero
-	movel	d0,d1		| 
-	lea	SYM (_fpCCR),a0	| clear exception flags
-	movew	IMM (0),a0@	|
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7	| 
-#else
-	moveml	sp@,d2-d7	| 
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6		| 
-	rts			| 	
-
-Ldivdf$b$0:
-	movew	IMM (DIVIDE),d5
-| If we got here a is not zero. Check if a is NaN; in that case return NaN,
-| else return +/-INFINITY. Remember that a is in d0 with the sign bit 
-| cleared already.
-	movel	a0,d7		| put a's sign bit back in d7 '
-	cmpl	IMM (0x7ff00000),d0 | compare d0 with INFINITY
-	bhi	Ld$inop		| if larger it is NaN
-	tstl	d1		| 
-	bne	Ld$inop		| 
-	bra	Ld$div$0	| else signal DIVIDE_BY_ZERO
-
-Ldivdf$b$nf:
-	movew	IMM (DIVIDE),d5
-| If d2 == 0x7ff00000 we have to check d3.
-	tstl	d3		|
-	bne	Ld$inop		| if d3 <> 0, b is NaN
-	bra	Ld$underflow	| else b is +/-INFINITY, so signal underflow
-
-Ldivdf$a$nf:
-	movew	IMM (DIVIDE),d5
-| If d0 == 0x7ff00000 we have to check d1.
-	tstl	d1		|
-	bne	Ld$inop		| if d1 <> 0, a is NaN
-| If a is INFINITY we have to check b
-	cmpl	d7,d2		| compare b with INFINITY 
-	bge	Ld$inop		| if b is NaN or INFINITY return NaN
-	tstl	d3		|
-	bne	Ld$inop		| 
-	bra	Ld$overflow	| else return overflow
-
-| If a number is denormalized we put an exponent of 1 but do not put the 
-| bit back into the fraction.
-Ldivdf$a$den:
-	movel	IMM (1),d4
-	andl	d6,d0
-1:	addl	d1,d1		| shift a left until bit 20 is set
-	addxl	d0,d0
-#ifndef __mcf5200__
-	subw	IMM (1),d4	| and adjust exponent
-#else
-	subl	IMM (1),d4	| and adjust exponent
-#endif
-	btst	IMM (DBL_MANT_DIG-32-1),d0
-	bne	Ldivdf$1
-	bra	1b
-
-Ldivdf$b$den:
-	movel	IMM (1),d5
-	andl	d6,d2
-1:	addl	d3,d3		| shift b left until bit 20 is set
-	addxl	d2,d2
-#ifndef __mcf5200__
-	subw	IMM (1),d5	| and adjust exponent
-#else
-	subql	IMM (1),d5	| and adjust exponent
-#endif
-	btst	IMM (DBL_MANT_DIG-32-1),d2
-	bne	Ldivdf$2
-	bra	1b
-
-Lround$exit:
-| This is a common exit point for __muldf3 and __divdf3. When they enter
-| this point the sign of the result is in d7, the result in d0-d1, normalized
-| so that 2^21 <= d0 < 2^22, and the exponent is in the lower byte of d4.
-
-| First check for underlow in the exponent:
-#ifndef __mcf5200__
-	cmpw	IMM (-DBL_MANT_DIG-1),d4		
-#else
-	cmpl	IMM (-DBL_MANT_DIG-1),d4		
-#endif
-	blt	Ld$underflow	
-| It could happen that the exponent is less than 1, in which case the 
-| number is denormalized. In this case we shift right and adjust the 
-| exponent until it becomes 1 or the fraction is zero (in the latter case 
-| we signal underflow and return zero).
-	movel	d7,a0		|
-	movel	IMM (0),d6	| use d6-d7 to collect bits flushed right
-	movel	d6,d7		| use d6-d7 to collect bits flushed right
-#ifndef __mcf5200__
-	cmpw	IMM (1),d4	| if the exponent is less than 1 we 
-#else
-	cmpl	IMM (1),d4	| if the exponent is less than 1 we 
-#endif
-	bge	2f		| have to shift right (denormalize)
-1:
-#ifndef __mcf5200__
-	addw	IMM (1),d4	| adjust the exponent
-	lsrl	IMM (1),d0	| shift right once 
-	roxrl	IMM (1),d1	|
-	roxrl	IMM (1),d2	|
-	roxrl	IMM (1),d3	|
-	roxrl	IMM (1),d6	| 
-	roxrl	IMM (1),d7	|
-	cmpw	IMM (1),d4	| is the exponent 1 already?
-#else
-	addl	IMM (1),d4	| adjust the exponent
-	lsrl	IMM (1),d7
-	btst	IMM (0),d6
-	beq	13f
-	bset	IMM (31),d7
-13:	lsrl	IMM (1),d6
-	btst	IMM (0),d3
-	beq	14f
-	bset	IMM (31),d6
-14:	lsrl	IMM (1),d3
-	btst	IMM (0),d2
-	beq	10f
-	bset	IMM (31),d3
-10:	lsrl	IMM (1),d2
-	btst	IMM (0),d1
-	beq	11f
-	bset	IMM (31),d2
-11:	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	12f
-	bset	IMM (31),d1
-12:	lsrl	IMM (1),d0
-	cmpl	IMM (1),d4	| is the exponent 1 already?
-#endif
-	beq	2f		| if not loop back
-	bra	1b              |
-	bra	Ld$underflow	| safety check, shouldn't execute '
-2:	orl	d6,d2		| this is a trick so we don't lose  '
-	orl	d7,d3		| the bits which were flushed right
-	movel	a0,d7		| get back sign bit into d7
-| Now call the rounding routine (which takes care of denormalized numbers):
-	lea	Lround$0,a0	| to return from rounding routine
-	lea	SYM (_fpCCR),a1	| check the rounding mode
-#ifdef __mcf5200__
-	clrl	d6
-#endif
-	movew	a1@(6),d6	| rounding mode in d6
-	beq	Lround$to$nearest
-#ifndef __mcf5200__
-	cmpw	IMM (ROUND_TO_PLUS),d6
-#else
-	cmpl	IMM (ROUND_TO_PLUS),d6
-#endif
-	bhi	Lround$to$minus
-	blt	Lround$to$zero
-	bra	Lround$to$plus
-Lround$0:
-| Here we have a correctly rounded result (either normalized or denormalized).
-
-| Here we should have either a normalized number or a denormalized one, and
-| the exponent is necessarily larger or equal to 1 (so we don't have to  '
-| check again for underflow!). We have to check for overflow or for a 
-| denormalized number (which also signals underflow).
-| Check for overflow (i.e., exponent >= 0x7ff).
-#ifndef __mcf5200__
-	cmpw	IMM (0x07ff),d4
-#else
-	cmpl	IMM (0x07ff),d4
-#endif
-	bge	Ld$overflow
-| Now check for a denormalized number (exponent==0):
-	movew	d4,d4
-	beq	Ld$den
-1:
-| Put back the exponents and sign and return.
-#ifndef __mcf5200__
-	lslw	IMM (4),d4	| exponent back to fourth byte
-#else
-	lsll	IMM (4),d4	| exponent back to fourth byte
-#endif
-	bclr	IMM (DBL_MANT_DIG-32-1),d0
-	swap	d0		| and put back exponent
-#ifndef __mcf5200__
-	orw	d4,d0		| 
-#else
-	orl	d4,d0		| 
-#endif
-	swap	d0		|
-	orl	d7,d0		| and sign also
-
-	lea	SYM (_fpCCR),a0
-	movew	IMM (0),a0@
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6
-	rts
-
-|=============================================================================
-|                              __negdf2
-|=============================================================================
-
-| double __negdf2(double, double);
-SYM (__negdf2):
-#ifndef __mcf5200__
-	link	a6,IMM (0)
-	moveml	d2-d7,sp@-
-#else
-	link	a6,IMM (-24)
-	moveml	d2-d7,sp@
-#endif
-	movew	IMM (NEGATE),d5
-	movel	a6@(8),d0	| get number to negate in d0-d1
-	movel	a6@(12),d1	|
-	bchg	IMM (31),d0	| negate
-	movel	d0,d2		| make a positive copy (for the tests)
-	bclr	IMM (31),d2	|
-	movel	d2,d4		| check for zero
-	orl	d1,d4		|
-	beq	2f		| if zero (either sign) return +zero
-	cmpl	IMM (0x7ff00000),d2 | compare to +INFINITY
-	blt	1f		| if finite, return
-	bhi	Ld$inop		| if larger (fraction not zero) is NaN
-	tstl	d1		| if d2 == 0x7ff00000 check d1
-	bne	Ld$inop		|
-	movel	d0,d7		| else get sign and return INFINITY
-	andl	IMM (0x80000000),d7
-	bra	Ld$infty		
-1:	lea	SYM (_fpCCR),a0
-	movew	IMM (0),a0@
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6
-	rts
-2:	bclr	IMM (31),d0
-	bra	1b
-
-|=============================================================================
-|                              __cmpdf2
-|=============================================================================
-
-GREATER =  1
-LESS    = -1
-EQUAL   =  0
-
-| int __cmpdf2(double, double);
-SYM (__cmpdf2):
-#ifndef __mcf5200__
-	link	a6,IMM (0)
-	moveml	d2-d7,sp@- 	| save registers
-#else
-	link	a6,IMM (-24)
-	moveml	d2-d7,sp@
-#endif
-	movew	IMM (COMPARE),d5
-	movel	a6@(8),d0	| get first operand
-	movel	a6@(12),d1	|
-	movel	a6@(16),d2	| get second operand
-	movel	a6@(20),d3	|
-| First check if a and/or b are (+/-) zero and in that case clear
-| the sign bit.
-	movel	d0,d6		| copy signs into d6 (a) and d7(b)
-	bclr	IMM (31),d0	| and clear signs in d0 and d2
-	movel	d2,d7		|
-	bclr	IMM (31),d2	|
-	cmpl	IMM (0x7fff0000),d0 | check for a == NaN
-	bhi	Ld$inop		| if d0 > 0x7ff00000, a is NaN
-	beq	Lcmpdf$a$nf	| if equal can be INFINITY, so check d1
-	movel	d0,d4		| copy into d4 to test for zero
-	orl	d1,d4		|
-	beq	Lcmpdf$a$0	|
-Lcmpdf$0:
-	cmpl	IMM (0x7fff0000),d2 | check for b == NaN
-	bhi	Ld$inop		| if d2 > 0x7ff00000, b is NaN
-	beq	Lcmpdf$b$nf	| if equal can be INFINITY, so check d3
-	movel	d2,d4		|
-	orl	d3,d4		|
-	beq	Lcmpdf$b$0	|
-Lcmpdf$1:
-| Check the signs
-	eorl	d6,d7
-	bpl	1f
-| If the signs are not equal check if a >= 0
-	tstl	d6
-	bpl	Lcmpdf$a$gt$b	| if (a >= 0 && b < 0) => a > b
-	bmi	Lcmpdf$b$gt$a	| if (a < 0 && b >= 0) => a < b
-1:
-| If the signs are equal check for < 0
-	tstl	d6
-	bpl	1f
-| If both are negative exchange them
-#ifndef __mcf5200__
-	exg	d0,d2
-	exg	d1,d3
-#else
-	movel	d0,d7
-	movel	d2,d0
-	movel	d7,d2
-	movel	d1,d7
-	movel	d3,d1
-	movel	d7,d3
-#endif
-1:
-| Now that they are positive we just compare them as longs (does this also
-| work for denormalized numbers?).
-	cmpl	d0,d2
-	bhi	Lcmpdf$b$gt$a	| |b| > |a|
-	bne	Lcmpdf$a$gt$b	| |b| < |a|
-| If we got here d0 == d2, so we compare d1 and d3.
-	cmpl	d1,d3
-	bhi	Lcmpdf$b$gt$a	| |b| > |a|
-	bne	Lcmpdf$a$gt$b	| |b| < |a|
-| If we got here a == b.
-	movel	IMM (EQUAL),d0
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7 	| put back the registers
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6
-	rts
-Lcmpdf$a$gt$b:
-	movel	IMM (GREATER),d0
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7 	| put back the registers
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6
-	rts
-Lcmpdf$b$gt$a:
-	movel	IMM (LESS),d0
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7 	| put back the registers
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6
-	rts
-
-Lcmpdf$a$0:	
-	bclr	IMM (31),d6
-	bra	Lcmpdf$0
-Lcmpdf$b$0:
-	bclr	IMM (31),d7
-	bra	Lcmpdf$1
-
-Lcmpdf$a$nf:
-	tstl	d1
-	bne	Ld$inop
-	bra	Lcmpdf$0
-
-Lcmpdf$b$nf:
-	tstl	d3
-	bne	Ld$inop
-	bra	Lcmpdf$1
-
-|=============================================================================
-|                           rounding routines
-|=============================================================================
-
-| The rounding routines expect the number to be normalized in registers
-| d0-d1-d2-d3, with the exponent in register d4. They assume that the 
-| exponent is larger or equal to 1. They return a properly normalized number
-| if possible, and a denormalized number otherwise. The exponent is returned
-| in d4.
-
-Lround$to$nearest:
-| We now normalize as suggested by D. Knuth ("Seminumerical Algorithms"):
-| Here we assume that the exponent is not too small (this should be checked
-| before entering the rounding routine), but the number could be denormalized.
-
-| Check for denormalized numbers:
-1:	btst	IMM (DBL_MANT_DIG-32),d0
-	bne	2f		| if set the number is normalized
-| Normalize shifting left until bit #DBL_MANT_DIG-32 is set or the exponent 
-| is one (remember that a denormalized number corresponds to an 
-| exponent of -D_BIAS+1).
-#ifndef __mcf5200__
-	cmpw	IMM (1),d4	| remember that the exponent is at least one
-#else
-	cmpl	IMM (1),d4	| remember that the exponent is at least one
-#endif
- 	beq	2f		| an exponent of one means denormalized
-	addl	d3,d3		| else shift and adjust the exponent
-	addxl	d2,d2		|
-	addxl	d1,d1		|
-	addxl	d0,d0		|
-#ifndef __mcf5200__
-	dbra	d4,1b		|
-#else
-	subql	IMM (1), d4
-	bpl	1b
-#endif
-2:
-| Now round: we do it as follows: after the shifting we can write the
-| fraction part as f + delta, where 1 < f < 2^25, and 0 <= delta <= 2.
-| If delta < 1, do nothing. If delta > 1, add 1 to f. 
-| If delta == 1, we make sure the rounded number will be even (odd?) 
-| (after shifting).
-	btst	IMM (0),d1	| is delta < 1?
-	beq	2f		| if so, do not do anything
-	orl	d2,d3		| is delta == 1?
-	bne	1f		| if so round to even
-	movel	d1,d3		| 
-	andl	IMM (2),d3	| bit 1 is the last significant bit
-	movel	IMM (0),d2	|
-	addl	d3,d1		|
-	addxl	d2,d0		|
-	bra	2f		| 
-1:	movel	IMM (1),d3	| else add 1 
-	movel	IMM (0),d2	|
-	addl	d3,d1		|
-	addxl	d2,d0
-| Shift right once (because we used bit #DBL_MANT_DIG-32!).
-2:
-#ifndef __mcf5200__
-	lsrl	IMM (1),d0
-	roxrl	IMM (1),d1		
-#else
-	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	10f
-	bset	IMM (31),d1
-10:	lsrl	IMM (1),d0
-#endif
-
-| Now check again bit #DBL_MANT_DIG-32 (rounding could have produced a
-| 'fraction overflow' ...).
-	btst	IMM (DBL_MANT_DIG-32),d0	
-	beq	1f
-#ifndef __mcf5200__
-	lsrl	IMM (1),d0
-	roxrl	IMM (1),d1
-	addw	IMM (1),d4
-#else
-	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	10f
-	bset	IMM (31),d1
-10:	lsrl	IMM (1),d0
-	addl	IMM (1),d4
-#endif
-1:
-| If bit #DBL_MANT_DIG-32-1 is clear we have a denormalized number, so we 
-| have to put the exponent to zero and return a denormalized number.
-	btst	IMM (DBL_MANT_DIG-32-1),d0
-	beq	1f
-	jmp	a0@
-1:	movel	IMM (0),d4
-	jmp	a0@
-
-Lround$to$zero:
-Lround$to$plus:
-Lround$to$minus:
-	jmp	a0@
-#endif /* L_double */
-
-#ifdef  L_float
-
-	.globl	SYM (_fpCCR)
-	.globl  $_exception_handler
-
-QUIET_NaN    = 0xffffffff
-SIGNL_NaN    = 0x7f800001
-INFINITY     = 0x7f800000
-
-F_MAX_EXP      = 0xff
-F_BIAS         = 126
-FLT_MAX_EXP    = F_MAX_EXP - F_BIAS
-FLT_MIN_EXP    = 1 - F_BIAS
-FLT_MANT_DIG   = 24
-
-INEXACT_RESULT 		= 0x0001
-UNDERFLOW 		= 0x0002
-OVERFLOW 		= 0x0004
-DIVIDE_BY_ZERO 		= 0x0008
-INVALID_OPERATION 	= 0x0010
-
-SINGLE_FLOAT = 1
-
-NOOP         = 0
-ADD          = 1
-MULTIPLY     = 2
-DIVIDE       = 3
-NEGATE       = 4
-COMPARE      = 5
-EXTENDSFDF   = 6
-TRUNCDFSF    = 7
-
-UNKNOWN           = -1
-ROUND_TO_NEAREST  = 0 | round result to nearest representable value
-ROUND_TO_ZERO     = 1 | round result towards zero
-ROUND_TO_PLUS     = 2 | round result towards plus infinity
-ROUND_TO_MINUS    = 3 | round result towards minus infinity
-
-| Entry points:
-
-	.globl SYM (__addsf3)
-	.globl SYM (__subsf3)
-	.globl SYM (__mulsf3)
-	.globl SYM (__divsf3)
-	.globl SYM (__negsf2)
-	.globl SYM (__cmpsf2)
-
-| These are common routines to return and signal exceptions.	
-
-	.text
-	.even
-
-Lf$den:
-| Return and signal a denormalized number
-	orl	d7,d0
-	movew	IMM (INEXACT_RESULT+UNDERFLOW),d7
-	moveq	IMM (SINGLE_FLOAT),d6
-	jmp	$_exception_handler
-
-Lf$infty:
-Lf$overflow:
-| Return a properly signed INFINITY and set the exception flags 
-	movel	IMM (INFINITY),d0
-	orl	d7,d0
-	movew	IMM (INEXACT_RESULT+OVERFLOW),d7
-	moveq	IMM (SINGLE_FLOAT),d6
-	jmp	$_exception_handler
-
-Lf$underflow:
-| Return 0 and set the exception flags 
-	movel	IMM (0),d0
-	movew	IMM (INEXACT_RESULT+UNDERFLOW),d7
-	moveq	IMM (SINGLE_FLOAT),d6
-	jmp	$_exception_handler
-
-Lf$inop:
-| Return a quiet NaN and set the exception flags
-	movel	IMM (QUIET_NaN),d0
-	movew	IMM (INEXACT_RESULT+INVALID_OPERATION),d7
-	moveq	IMM (SINGLE_FLOAT),d6
-	jmp	$_exception_handler
-
-Lf$div$0:
-| Return a properly signed INFINITY and set the exception flags
-	movel	IMM (INFINITY),d0
-	orl	d7,d0
-	movew	IMM (INEXACT_RESULT+DIVIDE_BY_ZERO),d7
-	moveq	IMM (SINGLE_FLOAT),d6
-	jmp	$_exception_handler
-
-|=============================================================================
-|=============================================================================
-|                         single precision routines
-|=============================================================================
-|=============================================================================
-
-| A single precision floating point number (float) has the format:
-|
-| struct _float {
-|  unsigned int sign      : 1;  /* sign bit */ 
-|  unsigned int exponent  : 8;  /* exponent, shifted by 126 */
-|  unsigned int fraction  : 23; /* fraction */
-| } float;
-| 
-| Thus sizeof(float) = 4 (32 bits). 
-|
-| All the routines are callable from C programs, and return the result 
-| in the single register d0. They also preserve all registers except 
-| d0-d1 and a0-a1.
-
-|=============================================================================
-|                              __subsf3
-|=============================================================================
-
-| float __subsf3(float, float);
-SYM (__subsf3):
-	bchg	IMM (31),sp@(8)	| change sign of second operand
-				| and fall through
-|=============================================================================
-|                              __addsf3
-|=============================================================================
-
-| float __addsf3(float, float);
-SYM (__addsf3):
-#ifndef __mcf5200__
-	link	a6,IMM (0)	| everything will be done in registers
-	moveml	d2-d7,sp@-	| save all data registers but d0-d1
-#else
-	link	a6,IMM (-24)
-	moveml	d2-d7,sp@
-#endif
-	movel	a6@(8),d0	| get first operand
-	movel	a6@(12),d1	| get second operand
-	movel	d0,d6		| get d0's sign bit '
-	addl	d0,d0		| check and clear sign bit of a
-	beq	Laddsf$b	| if zero return second operand
-	movel	d1,d7		| save b's sign bit '
-	addl	d1,d1		| get rid of sign bit
-	beq	Laddsf$a	| if zero return first operand
-
-	movel	d6,a0		| save signs in address registers
-	movel	d7,a1		| so we can use d6 and d7
-
-| Get the exponents and check for denormalized and/or infinity.
-
-	movel	IMM (0x00ffffff),d4	| mask to get fraction
-	movel	IMM (0x01000000),d5	| mask to put hidden bit back
-
-	movel	d0,d6		| save a to get exponent
-	andl	d4,d0		| get fraction in d0
-	notl 	d4		| make d4 into a mask for the exponent
-	andl	d4,d6		| get exponent in d6
-	beq	Laddsf$a$den	| branch if a is denormalized
-	cmpl	d4,d6		| check for INFINITY or NaN
-	beq	Laddsf$nf
-	swap	d6		| put exponent into first word
-	orl	d5,d0		| and put hidden bit back
-Laddsf$1:
-| Now we have a's exponent in d6 (second byte) and the mantissa in d0. '
-	movel	d1,d7		| get exponent in d7
-	andl	d4,d7		| 
-	beq	Laddsf$b$den	| branch if b is denormalized
-	cmpl	d4,d7		| check for INFINITY or NaN
-	beq	Laddsf$nf
-	swap	d7		| put exponent into first word
-	notl 	d4		| make d4 into a mask for the fraction
-	andl	d4,d1		| get fraction in d1
-	orl	d5,d1		| and put hidden bit back
-Laddsf$2:
-| Now we have b's exponent in d7 (second byte) and the mantissa in d1. '
-
-| Note that the hidden bit corresponds to bit #FLT_MANT_DIG-1, and we 
-| shifted right once, so bit #FLT_MANT_DIG is set (so we have one extra
-| bit).
-
-	movel	d1,d2		| move b to d2, since we want to use
-				| two registers to do the sum
-	movel	IMM (0),d1	| and clear the new ones
-	movel	d1,d3		|
-
-| Here we shift the numbers in registers d0 and d1 so the exponents are the
-| same, and put the largest exponent in d6. Note that we are using two
-| registers for each number (see the discussion by D. Knuth in "Seminumerical 
-| Algorithms").
-#ifndef __mcf5200__
-	cmpw	d6,d7		| compare exponents
-#else
-	cmpl	d6,d7		| compare exponents
-#endif
-	beq	Laddsf$3	| if equal don't shift '
-	bhi	5f		| branch if second exponent largest
-1:
-	subl	d6,d7		| keep the largest exponent
-	negl	d7
-#ifndef __mcf5200__
-	lsrw	IMM (8),d7	| put difference in lower byte
-#else
-	lsrl	IMM (8),d7	| put difference in lower byte
-#endif
-| if difference is too large we don't shift (actually, we can just exit) '
-#ifndef __mcf5200__
-	cmpw	IMM (FLT_MANT_DIG+2),d7		
-#else
-	cmpl	IMM (FLT_MANT_DIG+2),d7		
-#endif
-	bge	Laddsf$b$small
-#ifndef __mcf5200__
-	cmpw	IMM (16),d7	| if difference >= 16 swap
-#else
-	cmpl	IMM (16),d7	| if difference >= 16 swap
-#endif
-	bge	4f
-2:
-#ifndef __mcf5200__
-	subw	IMM (1),d7
-#else
-	subql	IMM (1), d7
-#endif
-3:
-#ifndef __mcf5200__
-	lsrl	IMM (1),d2	| shift right second operand
-	roxrl	IMM (1),d3
-	dbra	d7,3b
-#else
-	lsrl	IMM (1),d3
-	btst	IMM (0),d2
-	beq	10f
-	bset	IMM (31),d3
-10:	lsrl	IMM (1),d2
-	subql	IMM (1), d7
-	bpl	3b
-#endif
-	bra	Laddsf$3
-4:
-	movew	d2,d3
-	swap	d3
-	movew	d3,d2
-	swap	d2
-#ifndef __mcf5200__
-	subw	IMM (16),d7
-#else
-	subl	IMM (16),d7
-#endif
-	bne	2b		| if still more bits, go back to normal case
-	bra	Laddsf$3
-5:
-#ifndef __mcf5200__
-	exg	d6,d7		| exchange the exponents
-#else
-	eorl	d6,d7
-	eorl	d7,d6
-	eorl	d6,d7
-#endif
-	subl	d6,d7		| keep the largest exponent
-	negl	d7		|
-#ifndef __mcf5200__
-	lsrw	IMM (8),d7	| put difference in lower byte
-#else
-	lsrl	IMM (8),d7	| put difference in lower byte
-#endif
-| if difference is too large we don't shift (and exit!) '
-#ifndef __mcf5200__
-	cmpw	IMM (FLT_MANT_DIG+2),d7		
-#else
-	cmpl	IMM (FLT_MANT_DIG+2),d7		
-#endif
-	bge	Laddsf$a$small
-#ifndef __mcf5200__
-	cmpw	IMM (16),d7	| if difference >= 16 swap
-#else
-	cmpl	IMM (16),d7	| if difference >= 16 swap
-#endif
-	bge	8f
-6:
-#ifndef __mcf5200__
-	subw	IMM (1),d7
-#else
-	subl	IMM (1),d7
-#endif
-7:
-#ifndef __mcf5200__
-	lsrl	IMM (1),d0	| shift right first operand
-	roxrl	IMM (1),d1
-	dbra	d7,7b
-#else
-	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	10f
-	bset	IMM (31),d1
-10:	lsrl	IMM (1),d0
-	subql	IMM (1),d7
-	bpl	7b
-#endif
-	bra	Laddsf$3
-8:
-	movew	d0,d1
-	swap	d1
-	movew	d1,d0
-	swap	d0
-#ifndef __mcf5200__
-	subw	IMM (16),d7
-#else
-	subl	IMM (16),d7
-#endif
-	bne	6b		| if still more bits, go back to normal case
-				| otherwise we fall through
-
-| Now we have a in d0-d1, b in d2-d3, and the largest exponent in d6 (the
-| signs are stored in a0 and a1).
-
-Laddsf$3:
-| Here we have to decide whether to add or subtract the numbers
-#ifndef __mcf5200__
-	exg	d6,a0		| get signs back
-	exg	d7,a1		| and save the exponents
-#else
-	movel	d6,d4
-	movel	a0,d6
-	movel	d4,a0
-	movel	d7,d4
-	movel	a1,d7
-	movel	d4,a1
-#endif
-	eorl	d6,d7		| combine sign bits
-	bmi	Lsubsf$0	| if negative a and b have opposite 
-				| sign so we actually subtract the
-				| numbers
-
-| Here we have both positive or both negative
-#ifndef __mcf5200__
-	exg	d6,a0		| now we have the exponent in d6
-#else
-	movel	d6,d4
-	movel	a0,d6
-	movel	d4,a0
-#endif
-	movel	a0,d7		| and sign in d7
-	andl	IMM (0x80000000),d7
-| Here we do the addition.
-	addl	d3,d1
-	addxl	d2,d0
-| Note: now we have d2, d3, d4 and d5 to play with! 
-
-| Put the exponent, in the first byte, in d2, to use the "standard" rounding
-| routines:
-	movel	d6,d2
-#ifndef __mcf5200__
-	lsrw	IMM (8),d2
-#else
-	lsrl	IMM (8),d2
-#endif
-
-| Before rounding normalize so bit #FLT_MANT_DIG is set (we will consider
-| the case of denormalized numbers in the rounding routine itself).
-| As in the addition (not in the subtraction!) we could have set 
-| one more bit we check this:
-	btst	IMM (FLT_MANT_DIG+1),d0	
-	beq	1f
-#ifndef __mcf5200__
-	lsrl	IMM (1),d0
-	roxrl	IMM (1),d1
-#else
-	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	10f
-	bset	IMM (31),d1
-10:	lsrl	IMM (1),d0
-#endif
-	addl	IMM (1),d2
-1:
-	lea	Laddsf$4,a0	| to return from rounding routine
-	lea	SYM (_fpCCR),a1	| check the rounding mode
-#ifdef __mcf5200__
-	clrl	d6
-#endif
-	movew	a1@(6),d6	| rounding mode in d6
-	beq	Lround$to$nearest
-#ifndef __mcf5200__
-	cmpw	IMM (ROUND_TO_PLUS),d6
-#else
-	cmpl	IMM (ROUND_TO_PLUS),d6
-#endif
-	bhi	Lround$to$minus
-	blt	Lround$to$zero
-	bra	Lround$to$plus
-Laddsf$4:
-| Put back the exponent, but check for overflow.
-#ifndef __mcf5200__
-	cmpw	IMM (0xff),d2
-#else
-	cmpl	IMM (0xff),d2
-#endif
-	bhi	1f
-	bclr	IMM (FLT_MANT_DIG-1),d0
-#ifndef __mcf5200__
-	lslw	IMM (7),d2
-#else
-	lsll	IMM (7),d2
-#endif
-	swap	d2
-	orl	d2,d0
-	bra	Laddsf$ret
-1:
-	movew	IMM (ADD),d5
-	bra	Lf$overflow
-
-Lsubsf$0:
-| We are here if a > 0 and b < 0 (sign bits cleared).
-| Here we do the subtraction.
-	movel	d6,d7		| put sign in d7
-	andl	IMM (0x80000000),d7
-
-	subl	d3,d1		| result in d0-d1
-	subxl	d2,d0		|
-	beq	Laddsf$ret	| if zero just exit
-	bpl	1f		| if positive skip the following
-	bchg	IMM (31),d7	| change sign bit in d7
-	negl	d1
-	negxl	d0
-1:
-#ifndef __mcf5200__
-	exg	d2,a0		| now we have the exponent in d2
-	lsrw	IMM (8),d2	| put it in the first byte
-#else
-	movel	d2,d4
-	movel	a0,d2
-	movel	d4,a0
-	lsrl	IMM (8),d2	| put it in the first byte
-#endif
-
-| Now d0-d1 is positive and the sign bit is in d7.
-
-| Note that we do not have to normalize, since in the subtraction bit
-| #FLT_MANT_DIG+1 is never set, and denormalized numbers are handled by
-| the rounding routines themselves.
-	lea	Lsubsf$1,a0	| to return from rounding routine
-	lea	SYM (_fpCCR),a1	| check the rounding mode
-#ifdef __mcf5200__
-	clrl	d6
-#endif
-	movew	a1@(6),d6	| rounding mode in d6
-	beq	Lround$to$nearest
-#ifndef __mcf5200__
-	cmpw	IMM (ROUND_TO_PLUS),d6
-#else
-	cmpl	IMM (ROUND_TO_PLUS),d6
-#endif
-	bhi	Lround$to$minus
-	blt	Lround$to$zero
-	bra	Lround$to$plus
-Lsubsf$1:
-| Put back the exponent (we can't have overflow!). '
-	bclr	IMM (FLT_MANT_DIG-1),d0
-#ifndef __mcf5200__
-	lslw	IMM (7),d2
-#else
-	lsll	IMM (7),d2
-#endif
-	swap	d2
-	orl	d2,d0
-	bra	Laddsf$ret
-
-| If one of the numbers was too small (difference of exponents >= 
-| FLT_MANT_DIG+2) we return the other (and now we don't have to '
-| check for finiteness or zero).
-Laddsf$a$small:
-	movel	a6@(12),d0
-	lea	SYM (_fpCCR),a0
-	movew	IMM (0),a0@
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7	| restore data registers
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6		| and return
-	rts
-
-Laddsf$b$small:
-	movel	a6@(8),d0
-	lea	SYM (_fpCCR),a0
-	movew	IMM (0),a0@
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7	| restore data registers
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6		| and return
-	rts
-
-| If the numbers are denormalized remember to put exponent equal to 1.
-
-Laddsf$a$den:
-	movel	d5,d6		| d5 contains 0x01000000
-	swap	d6
-	bra	Laddsf$1
-
-Laddsf$b$den:
-	movel	d5,d7
-	swap	d7
-	notl 	d4		| make d4 into a mask for the fraction
-				| (this was not executed after the jump)
-	bra	Laddsf$2
-
-| The rest is mainly code for the different results which can be 
-| returned (checking always for +/-INFINITY and NaN).
-
-Laddsf$b:
-| Return b (if a is zero).
-	movel	a6@(12),d0
-	bra	1f
-Laddsf$a:
-| Return a (if b is zero).
-	movel	a6@(8),d0
-1:
-	movew	IMM (ADD),d5
-| We have to check for NaN and +/-infty.
-	movel	d0,d7
-	andl	IMM (0x80000000),d7	| put sign in d7
-	bclr	IMM (31),d0		| clear sign
-	cmpl	IMM (INFINITY),d0	| check for infty or NaN
-	bge	2f
-	movel	d0,d0		| check for zero (we do this because we don't '
-	bne	Laddsf$ret	| want to return -0 by mistake
-	bclr	IMM (31),d7	| if zero be sure to clear sign
-	bra	Laddsf$ret	| if everything OK just return
-2:
-| The value to be returned is either +/-infty or NaN
-	andl	IMM (0x007fffff),d0	| check for NaN
-	bne	Lf$inop			| if mantissa not zero is NaN
-	bra	Lf$infty
-
-Laddsf$ret:
-| Normal exit (a and b nonzero, result is not NaN nor +/-infty).
-| We have to clear the exception flags (just the exception type).
-	lea	SYM (_fpCCR),a0
-	movew	IMM (0),a0@
-	orl	d7,d0		| put sign bit
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7	| restore data registers
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6		| and return
-	rts
-
-Laddsf$ret$den:
-| Return a denormalized number (for addition we don't signal underflow) '
-	lsrl	IMM (1),d0	| remember to shift right back once
-	bra	Laddsf$ret	| and return
-
-| Note: when adding two floats of the same sign if either one is 
-| NaN we return NaN without regard to whether the other is finite or 
-| not. When subtracting them (i.e., when adding two numbers of 
-| opposite signs) things are more complicated: if both are INFINITY 
-| we return NaN, if only one is INFINITY and the other is NaN we return
-| NaN, but if it is finite we return INFINITY with the corresponding sign.
-
-Laddsf$nf:
-	movew	IMM (ADD),d5
-| This could be faster but it is not worth the effort, since it is not
-| executed very often. We sacrifice speed for clarity here.
-	movel	a6@(8),d0	| get the numbers back (remember that we
-	movel	a6@(12),d1	| did some processing already)
-	movel	IMM (INFINITY),d4 | useful constant (INFINITY)
-	movel	d0,d2		| save sign bits
-	movel	d1,d3
-	bclr	IMM (31),d0	| clear sign bits
-	bclr	IMM (31),d1
-| We know that one of them is either NaN of +/-INFINITY
-| Check for NaN (if either one is NaN return NaN)
-	cmpl	d4,d0		| check first a (d0)
-	bhi	Lf$inop		
-	cmpl	d4,d1		| check now b (d1)
-	bhi	Lf$inop		
-| Now comes the check for +/-INFINITY. We know that both are (maybe not
-| finite) numbers, but we have to check if both are infinite whether we
-| are adding or subtracting them.
-	eorl	d3,d2		| to check sign bits
-	bmi	1f
-	movel	d0,d7
-	andl	IMM (0x80000000),d7	| get (common) sign bit
-	bra	Lf$infty
-1:
-| We know one (or both) are infinite, so we test for equality between the
-| two numbers (if they are equal they have to be infinite both, so we
-| return NaN).
-	cmpl	d1,d0		| are both infinite?
-	beq	Lf$inop		| if so return NaN
-
-	movel	d0,d7
-	andl	IMM (0x80000000),d7 | get a's sign bit '
-	cmpl	d4,d0		| test now for infinity
-	beq	Lf$infty	| if a is INFINITY return with this sign
-	bchg	IMM (31),d7	| else we know b is INFINITY and has
-	bra	Lf$infty	| the opposite sign
-
-|=============================================================================
-|                             __mulsf3
-|=============================================================================
-
-| float __mulsf3(float, float);
-SYM (__mulsf3):
-#ifndef __mcf5200__
-	link	a6,IMM (0)
-	moveml	d2-d7,sp@-
-#else
-	link	a6,IMM (-24)
-	moveml	d2-d7,sp@
-#endif
-	movel	a6@(8),d0	| get a into d0
-	movel	a6@(12),d1	| and b into d1
-	movel	d0,d7		| d7 will hold the sign of the product
-	eorl	d1,d7		|
-	andl	IMM (0x80000000),d7
-	movel	IMM (INFINITY),d6	| useful constant (+INFINITY)
-	movel	d6,d5			| another (mask for fraction)
-	notl	d5			|
-	movel	IMM (0x00800000),d4	| this is to put hidden bit back
-	bclr	IMM (31),d0		| get rid of a's sign bit '
-	movel	d0,d2			|
-	beq	Lmulsf$a$0		| branch if a is zero
-	bclr	IMM (31),d1		| get rid of b's sign bit '
-	movel	d1,d3		|
-	beq	Lmulsf$b$0	| branch if b is zero
-	cmpl	d6,d0		| is a big?
-	bhi	Lmulsf$inop	| if a is NaN return NaN
-	beq	Lmulsf$inf	| if a is INFINITY we have to check b
-	cmpl	d6,d1		| now compare b with INFINITY
-	bhi	Lmulsf$inop	| is b NaN?
-	beq	Lmulsf$overflow | is b INFINITY?
-| Here we have both numbers finite and nonzero (and with no sign bit).
-| Now we get the exponents into d2 and d3.
-	andl	d6,d2		| and isolate exponent in d2
-	beq	Lmulsf$a$den	| if exponent is zero we have a denormalized
-	andl	d5,d0		| and isolate fraction
-	orl	d4,d0		| and put hidden bit back
-	swap	d2		| I like exponents in the first byte
-#ifndef __mcf5200__
-	lsrw	IMM (7),d2	| 
-#else
-	lsrl	IMM (7),d2	| 
-#endif
-Lmulsf$1:			| number
-	andl	d6,d3		|
-	beq	Lmulsf$b$den	|
-	andl	d5,d1		|
-	orl	d4,d1		|
-	swap	d3		|
-#ifndef __mcf5200__
-	lsrw	IMM (7),d3	|
-#else
-	lsrl	IMM (7),d3	|
-#endif
-Lmulsf$2:			|
-#ifndef __mcf5200__
-	addw	d3,d2		| add exponents
-	subw	IMM (F_BIAS+1),d2 | and subtract bias (plus one)
-#else
-	addl	d3,d2		| add exponents
-	subl	IMM (F_BIAS+1),d2 | and subtract bias (plus one)
-#endif
-
-| We are now ready to do the multiplication. The situation is as follows:
-| both a and b have bit FLT_MANT_DIG-1 set (even if they were 
-| denormalized to start with!), which means that in the product 
-| bit 2*(FLT_MANT_DIG-1) (that is, bit 2*FLT_MANT_DIG-2-32 of the 
-| high long) is set. 
-
-| To do the multiplication let us move the number a little bit around ...
-	movel	d1,d6		| second operand in d6
-	movel	d0,d5		| first operand in d4-d5
-	movel	IMM (0),d4
-	movel	d4,d1		| the sums will go in d0-d1
-	movel	d4,d0
-
-| now bit FLT_MANT_DIG-1 becomes bit 31:
-	lsll	IMM (31-FLT_MANT_DIG+1),d6		
-
-| Start the loop (we loop #FLT_MANT_DIG times):
-	movew	IMM (FLT_MANT_DIG-1),d3	
-1:	addl	d1,d1		| shift sum 
-	addxl	d0,d0
-	lsll	IMM (1),d6	| get bit bn
-	bcc	2f		| if not set skip sum
-	addl	d5,d1		| add a
-	addxl	d4,d0
-2:
-#ifndef __mcf5200__
-	dbf	d3,1b		| loop back
-#else
-	subql	IMM (1),d3
-	bpl	1b
-#endif
-
-| Now we have the product in d0-d1, with bit (FLT_MANT_DIG - 1) + FLT_MANT_DIG
-| (mod 32) of d0 set. The first thing to do now is to normalize it so bit 
-| FLT_MANT_DIG is set (to do the rounding).
-#ifndef __mcf5200__
-	rorl	IMM (6),d1
-	swap	d1
-	movew	d1,d3
-	andw	IMM (0x03ff),d3
-	andw	IMM (0xfd00),d1
-#else
-	movel	d1,d3
-	lsll	IMM (8),d1
-	addl	d1,d1
-	addl	d1,d1
-	moveq	IMM (22),d5
-	lsrl	d5,d3
-	orl	d3,d1
-	andl	IMM (0xfffffd00),d1
-#endif
-	lsll	IMM (8),d0
-	addl	d0,d0
-	addl	d0,d0
-#ifndef __mcf5200__
-	orw	d3,d0
-#else
-	orl	d3,d0
-#endif
-
-	movew	IMM (MULTIPLY),d5
-	
-	btst	IMM (FLT_MANT_DIG+1),d0
-	beq	Lround$exit
-#ifndef __mcf5200__
-	lsrl	IMM (1),d0
-	roxrl	IMM (1),d1
-	addw	IMM (1),d2
-#else
-	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	10f
-	bset	IMM (31),d1
-10:	lsrl	IMM (1),d0
-	addql	IMM (1),d2
-#endif
-	bra	Lround$exit
-
-Lmulsf$inop:
-	movew	IMM (MULTIPLY),d5
-	bra	Lf$inop
-
-Lmulsf$overflow:
-	movew	IMM (MULTIPLY),d5
-	bra	Lf$overflow
-
-Lmulsf$inf:
-	movew	IMM (MULTIPLY),d5
-| If either is NaN return NaN; else both are (maybe infinite) numbers, so
-| return INFINITY with the correct sign (which is in d7).
-	cmpl	d6,d1		| is b NaN?
-	bhi	Lf$inop		| if so return NaN
-	bra	Lf$overflow	| else return +/-INFINITY
-
-| If either number is zero return zero, unless the other is +/-INFINITY, 
-| or NaN, in which case we return NaN.
-Lmulsf$b$0:
-| Here d1 (==b) is zero.
-	movel	d1,d0		| put b into d0 (just a zero)
-	movel	a6@(8),d1	| get a again to check for non-finiteness
-	bra	1f
-Lmulsf$a$0:
-	movel	a6@(12),d1	| get b again to check for non-finiteness
-1:	bclr	IMM (31),d1	| clear sign bit 
-	cmpl	IMM (INFINITY),d1 | and check for a large exponent
-	bge	Lf$inop		| if b is +/-INFINITY or NaN return NaN
-	lea	SYM (_fpCCR),a0	| else return zero
-	movew	IMM (0),a0@	| 
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7	| 
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6		| 
-	rts			| 
-
-| If a number is denormalized we put an exponent of 1 but do not put the 
-| hidden bit back into the fraction; instead we shift left until bit 23
-| (the hidden bit) is set, adjusting the exponent accordingly. We do this
-| to ensure that the product of the fractions is close to 1.
-Lmulsf$a$den:
-	movel	IMM (1),d2
-	andl	d5,d0
-1:	addl	d0,d0		| shift a left (until bit 23 is set)
-#ifndef __mcf5200__
-	subw	IMM (1),d2	| and adjust exponent
-#else
-	subql	IMM (1),d2	| and adjust exponent
-#endif
-	btst	IMM (FLT_MANT_DIG-1),d0
-	bne	Lmulsf$1	|
-	bra	1b		| else loop back
-
-Lmulsf$b$den:
-	movel	IMM (1),d3
-	andl	d5,d1
-1:	addl	d1,d1		| shift b left until bit 23 is set
-#ifndef __mcf5200__
-	subw	IMM (1),d3	| and adjust exponent
-#else
-	subl	IMM (1),d3	| and adjust exponent
-#endif
-	btst	IMM (FLT_MANT_DIG-1),d1
-	bne	Lmulsf$2	|
-	bra	1b		| else loop back
-
-|=============================================================================
-|                             __divsf3
-|=============================================================================
-
-| float __divsf3(float, float);
-SYM (__divsf3):
-#ifndef __mcf5200__
-	link	a6,IMM (0)
-	moveml	d2-d7,sp@-
-#else
-	link	a6,IMM (-24)
-	moveml	d2-d7,sp@
-#endif
-	movel	a6@(8),d0		| get a into d0
-	movel	a6@(12),d1		| and b into d1
-	movel	d0,d7			| d7 will hold the sign of the result
-	eorl	d1,d7			|
-	andl	IMM (0x80000000),d7	| 
-	movel	IMM (INFINITY),d6	| useful constant (+INFINITY)
-	movel	d6,d5			| another (mask for fraction)
-	notl	d5			|
-	movel	IMM (0x00800000),d4	| this is to put hidden bit back
-	bclr	IMM (31),d0		| get rid of a's sign bit '
-	movel	d0,d2			|
-	beq	Ldivsf$a$0		| branch if a is zero
-	bclr	IMM (31),d1		| get rid of b's sign bit '
-	movel	d1,d3			|
-	beq	Ldivsf$b$0		| branch if b is zero
-	cmpl	d6,d0			| is a big?
-	bhi	Ldivsf$inop		| if a is NaN return NaN
-	beq	Ldivsf$inf		| if a is INFINITY we have to check b
-	cmpl	d6,d1			| now compare b with INFINITY 
-	bhi	Ldivsf$inop		| if b is NaN return NaN
-	beq	Ldivsf$underflow
-| Here we have both numbers finite and nonzero (and with no sign bit).
-| Now we get the exponents into d2 and d3 and normalize the numbers to
-| ensure that the ratio of the fractions is close to 1. We do this by
-| making sure that bit #FLT_MANT_DIG-1 (hidden bit) is set.
-	andl	d6,d2		| and isolate exponent in d2
-	beq	Ldivsf$a$den	| if exponent is zero we have a denormalized
-	andl	d5,d0		| and isolate fraction
-	orl	d4,d0		| and put hidden bit back
-	swap	d2		| I like exponents in the first byte
-#ifndef __mcf5200__
-	lsrw	IMM (7),d2	| 
-#else
-	lsrl	IMM (7),d2	| 
-#endif
-Ldivsf$1:			| 
-	andl	d6,d3		|
-	beq	Ldivsf$b$den	|
-	andl	d5,d1		|
-	orl	d4,d1		|
-	swap	d3		|
-#ifndef __mcf5200__
-	lsrw	IMM (7),d3	|
-#else
-	lsrl	IMM (7),d3	|
-#endif
-Ldivsf$2:			|
-#ifndef __mcf5200__
-	subw	d3,d2		| subtract exponents
- 	addw	IMM (F_BIAS),d2	| and add bias
-#else
-	subl	d3,d2		| subtract exponents
- 	addl	IMM (F_BIAS),d2	| and add bias
-#endif
- 
-| We are now ready to do the division. We have prepared things in such a way
-| that the ratio of the fractions will be less than 2 but greater than 1/2.
-| At this point the registers in use are:
-| d0	holds a (first operand, bit FLT_MANT_DIG=0, bit FLT_MANT_DIG-1=1)
-| d1	holds b (second operand, bit FLT_MANT_DIG=1)
-| d2	holds the difference of the exponents, corrected by the bias
-| d7	holds the sign of the ratio
-| d4, d5, d6 hold some constants
-	movel	d7,a0		| d6-d7 will hold the ratio of the fractions
-	movel	IMM (0),d6	| 
-	movel	d6,d7
-
-	movew	IMM (FLT_MANT_DIG+1),d3
-1:	cmpl	d0,d1		| is a < b?
-	bhi	2f		|
-	bset	d3,d6		| set a bit in d6
-	subl	d1,d0		| if a >= b  a <-- a-b
-	beq	3f		| if a is zero, exit
-2:	addl	d0,d0		| multiply a by 2
-#ifndef __mcf5200__
-	dbra	d3,1b
-#else
-	subql	IMM (1),d3
-	bpl	1b
-#endif
-
-| Now we keep going to set the sticky bit ...
-	movew	IMM (FLT_MANT_DIG),d3
-1:	cmpl	d0,d1
-	ble	2f
-	addl	d0,d0
-#ifndef __mcf5200__
-	dbra	d3,1b
-#else
-	subql	IMM(1),d3
-	bpl	1b
-#endif
-	movel	IMM (0),d1
-	bra	3f
-2:	movel	IMM (0),d1
-#ifndef __mcf5200__
-	subw	IMM (FLT_MANT_DIG),d3
-	addw	IMM (31),d3
-#else
-	subl	IMM (FLT_MANT_DIG),d3
-	addl	IMM (31),d3
-#endif
-	bset	d3,d1
-3:
-	movel	d6,d0		| put the ratio in d0-d1
-	movel	a0,d7		| get sign back
-
-| Because of the normalization we did before we are guaranteed that 
-| d0 is smaller than 2^26 but larger than 2^24. Thus bit 26 is not set,
-| bit 25 could be set, and if it is not set then bit 24 is necessarily set.
-	btst	IMM (FLT_MANT_DIG+1),d0		
-	beq	1f              | if it is not set, then bit 24 is set
-	lsrl	IMM (1),d0	|
-#ifndef __mcf5200__
-	addw	IMM (1),d2	|
-#else
-	addl	IMM (1),d2	|
-#endif
-1:
-| Now round, check for over- and underflow, and exit.
-	movew	IMM (DIVIDE),d5
-	bra	Lround$exit
-
-Ldivsf$inop:
-	movew	IMM (DIVIDE),d5
-	bra	Lf$inop
-
-Ldivsf$overflow:
-	movew	IMM (DIVIDE),d5
-	bra	Lf$overflow
-
-Ldivsf$underflow:
-	movew	IMM (DIVIDE),d5
-	bra	Lf$underflow
-
-Ldivsf$a$0:
-	movew	IMM (DIVIDE),d5
-| If a is zero check to see whether b is zero also. In that case return
-| NaN; then check if b is NaN, and return NaN also in that case. Else
-| return zero.
-	andl	IMM (0x7fffffff),d1	| clear sign bit and test b
-	beq	Lf$inop			| if b is also zero return NaN
-	cmpl	IMM (INFINITY),d1	| check for NaN
-	bhi	Lf$inop			| 
-	movel	IMM (0),d0		| else return zero
-	lea	SYM (_fpCCR),a0		|
-	movew	IMM (0),a0@		|
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7		| 
-#else
-	moveml	sp@,d2-d7		| 
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6			| 
-	rts				| 
-	
-Ldivsf$b$0:
-	movew	IMM (DIVIDE),d5
-| If we got here a is not zero. Check if a is NaN; in that case return NaN,
-| else return +/-INFINITY. Remember that a is in d0 with the sign bit 
-| cleared already.
-	cmpl	IMM (INFINITY),d0	| compare d0 with INFINITY
-	bhi	Lf$inop			| if larger it is NaN
-	bra	Lf$div$0		| else signal DIVIDE_BY_ZERO
-
-Ldivsf$inf:
-	movew	IMM (DIVIDE),d5
-| If a is INFINITY we have to check b
-	cmpl	IMM (INFINITY),d1	| compare b with INFINITY 
-	bge	Lf$inop			| if b is NaN or INFINITY return NaN
-	bra	Lf$overflow		| else return overflow
-
-| If a number is denormalized we put an exponent of 1 but do not put the 
-| bit back into the fraction.
-Ldivsf$a$den:
-	movel	IMM (1),d2
-	andl	d5,d0
-1:	addl	d0,d0		| shift a left until bit FLT_MANT_DIG-1 is set
-#ifndef __mcf5200__
-	subw	IMM (1),d2	| and adjust exponent
-#else
-	subl	IMM (1),d2	| and adjust exponent
-#endif
-	btst	IMM (FLT_MANT_DIG-1),d0
-	bne	Ldivsf$1
-	bra	1b
-
-Ldivsf$b$den:
-	movel	IMM (1),d3
-	andl	d5,d1
-1:	addl	d1,d1		| shift b left until bit FLT_MANT_DIG is set
-#ifndef __mcf5200__
-	subw	IMM (1),d3	| and adjust exponent
-#else
-	subl	IMM (1),d3	| and adjust exponent
-#endif
-	btst	IMM (FLT_MANT_DIG-1),d1
-	bne	Ldivsf$2
-	bra	1b
-
-Lround$exit:
-| This is a common exit point for __mulsf3 and __divsf3. 
-
-| First check for underlow in the exponent:
-#ifndef __mcf5200__
-	cmpw	IMM (-FLT_MANT_DIG-1),d2		
-#else
-	cmpl	IMM (-FLT_MANT_DIG-1),d2		
-#endif
-	blt	Lf$underflow	
-| It could happen that the exponent is less than 1, in which case the 
-| number is denormalized. In this case we shift right and adjust the 
-| exponent until it becomes 1 or the fraction is zero (in the latter case 
-| we signal underflow and return zero).
-	movel	IMM (0),d6	| d6 is used temporarily
-#ifndef __mcf5200__
-	cmpw	IMM (1),d2	| if the exponent is less than 1 we 
-#else
-	cmpl	IMM (1),d2	| if the exponent is less than 1 we 
-#endif
-	bge	2f		| have to shift right (denormalize)
-1:
-#ifndef __mcf5200__
-	addw	IMM (1),d2	| adjust the exponent
-	lsrl	IMM (1),d0	| shift right once 
-	roxrl	IMM (1),d1	|
-	roxrl	IMM (1),d6	| d6 collect bits we would lose otherwise
-	cmpw	IMM (1),d2	| is the exponent 1 already?
-#else
-	addql	IMM (1),d2	| adjust the exponent
-	lsrl	IMM (1),d6
-	btst	IMM (0),d1
-	beq	11f
-	bset	IMM (31),d6
-11:	lsrl	IMM (1),d1
-	btst	IMM (0),d0
-	beq	10f
-	bset	IMM (31),d1
-10:	lsrl	IMM (1),d0
-	cmpl	IMM (1),d2	| is the exponent 1 already?
-#endif
-	beq	2f		| if not loop back
-	bra	1b              |
-	bra	Lf$underflow	| safety check, shouldn't execute '
-2:	orl	d6,d1		| this is a trick so we don't lose  '
-				| the extra bits which were flushed right
-| Now call the rounding routine (which takes care of denormalized numbers):
-	lea	Lround$0,a0	| to return from rounding routine
-	lea	SYM (_fpCCR),a1	| check the rounding mode
-#ifdef __mcf5200__
-	clrl	d6
-#endif
-	movew	a1@(6),d6	| rounding mode in d6
-	beq	Lround$to$nearest
-#ifndef __mcf5200__
-	cmpw	IMM (ROUND_TO_PLUS),d6
-#else
-	cmpl	IMM (ROUND_TO_PLUS),d6
-#endif
-	bhi	Lround$to$minus
-	blt	Lround$to$zero
-	bra	Lround$to$plus
-Lround$0:
-| Here we have a correctly rounded result (either normalized or denormalized).
-
-| Here we should have either a normalized number or a denormalized one, and
-| the exponent is necessarily larger or equal to 1 (so we don't have to  '
-| check again for underflow!). We have to check for overflow or for a 
-| denormalized number (which also signals underflow).
-| Check for overflow (i.e., exponent >= 255).
-#ifndef __mcf5200__
-	cmpw	IMM (0x00ff),d2
-#else
-	cmpl	IMM (0x00ff),d2
-#endif
-	bge	Lf$overflow
-| Now check for a denormalized number (exponent==0).
-	movew	d2,d2
-	beq	Lf$den
-1:
-| Put back the exponents and sign and return.
-#ifndef __mcf5200__
-	lslw	IMM (7),d2	| exponent back to fourth byte
-#else
-	lsll	IMM (7),d2	| exponent back to fourth byte
-#endif
-	bclr	IMM (FLT_MANT_DIG-1),d0
-	swap	d0		| and put back exponent
-#ifndef __mcf5200__
-	orw	d2,d0		| 
-#else
-	orl	d2,d0
-#endif
-	swap	d0		|
-	orl	d7,d0		| and sign also
-
-	lea	SYM (_fpCCR),a0
-	movew	IMM (0),a0@
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6
-	rts
-
-|=============================================================================
-|                             __negsf2
-|=============================================================================
-
-| This is trivial and could be shorter if we didn't bother checking for NaN '
-| and +/-INFINITY.
-
-| float __negsf2(float);
-SYM (__negsf2):
-#ifndef __mcf5200__
-	link	a6,IMM (0)
-	moveml	d2-d7,sp@-
-#else
-	link	a6,IMM (-24)
-	moveml	d2-d7,sp@
-#endif
-	movew	IMM (NEGATE),d5
-	movel	a6@(8),d0	| get number to negate in d0
-	bchg	IMM (31),d0	| negate
-	movel	d0,d1		| make a positive copy
-	bclr	IMM (31),d1	|
-	tstl	d1		| check for zero
-	beq	2f		| if zero (either sign) return +zero
-	cmpl	IMM (INFINITY),d1 | compare to +INFINITY
-	blt	1f		|
-	bhi	Lf$inop		| if larger (fraction not zero) is NaN
-	movel	d0,d7		| else get sign and return INFINITY
-	andl	IMM (0x80000000),d7
-	bra	Lf$infty		
-1:	lea	SYM (_fpCCR),a0
-	movew	IMM (0),a0@
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6
-	rts
-2:	bclr	IMM (31),d0
-	bra	1b
-
-|=============================================================================
-|                             __cmpsf2
-|=============================================================================
-
-GREATER =  1
-LESS    = -1
-EQUAL   =  0
-
-| int __cmpsf2(float, float);
-SYM (__cmpsf2):
-#ifndef __mcf5200__
-	link	a6,IMM (0)
-	moveml	d2-d7,sp@- 	| save registers
-#else
-	link	a6,IMM (-24)
-	moveml	d2-d7,sp@
-#endif
-	movew	IMM (COMPARE),d5
-	movel	a6@(8),d0	| get first operand
-	movel	a6@(12),d1	| get second operand
-| Check if either is NaN, and in that case return garbage and signal
-| INVALID_OPERATION. Check also if either is zero, and clear the signs
-| if necessary.
-	movel	d0,d6
-	andl	IMM (0x7fffffff),d0
-	beq	Lcmpsf$a$0
-	cmpl	IMM (0x7f800000),d0
-	bhi	Lf$inop
-Lcmpsf$1:
-	movel	d1,d7
-	andl	IMM (0x7fffffff),d1
-	beq	Lcmpsf$b$0
-	cmpl	IMM (0x7f800000),d1
-	bhi	Lf$inop
-Lcmpsf$2:
-| Check the signs
-	eorl	d6,d7
-	bpl	1f
-| If the signs are not equal check if a >= 0
-	tstl	d6
-	bpl	Lcmpsf$a$gt$b	| if (a >= 0 && b < 0) => a > b
-	bmi	Lcmpsf$b$gt$a	| if (a < 0 && b >= 0) => a < b
-1:
-| If the signs are equal check for < 0
-	tstl	d6
-	bpl	1f
-| If both are negative exchange them
-#ifndef __mcf5200__
-	exg	d0,d1
-#else
-	movel	d0,d7
-	movel	d1,d0
-	movel	d7,d1
-#endif
-1:
-| Now that they are positive we just compare them as longs (does this also
-| work for denormalized numbers?).
-	cmpl	d0,d1
-	bhi	Lcmpsf$b$gt$a	| |b| > |a|
-	bne	Lcmpsf$a$gt$b	| |b| < |a|
-| If we got here a == b.
-	movel	IMM (EQUAL),d0
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7 	| put back the registers
-#else
-	moveml	sp@,d2-d7
-#endif
-	unlk	a6
-	rts
-Lcmpsf$a$gt$b:
-	movel	IMM (GREATER),d0
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7 	| put back the registers
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6
-	rts
-Lcmpsf$b$gt$a:
-	movel	IMM (LESS),d0
-#ifndef __mcf5200__
-	moveml	sp@+,d2-d7 	| put back the registers
-#else
-	moveml	sp@,d2-d7
-	| XXX if frame pointer is ever removed, stack pointer must
-	| be adjusted here.
-#endif
-	unlk	a6
-	rts
-
-Lcmpsf$a$0:	
-	bclr	IMM (31),d6
-	bra	Lcmpsf$1
-Lcmpsf$b$0:
-	bclr	IMM (31),d7
-	bra	Lcmpsf$2
-
-|=============================================================================
-|                           rounding routines
-|=============================================================================
-
-| The rounding routines expect the number to be normalized in registers
-| d0-d1, with the exponent in register d2. They assume that the 
-| exponent is larger or equal to 1. They return a properly normalized number
-| if possible, and a denormalized number otherwise. The exponent is returned
-| in d2.
-
-Lround$to$nearest:
-| We now normalize as suggested by D. Knuth ("Seminumerical Algorithms"):
-| Here we assume that the exponent is not too small (this should be checked
-| before entering the rounding routine), but the number could be denormalized.
-
-| Check for denormalized numbers:
-1:	btst	IMM (FLT_MANT_DIG),d0
-	bne	2f		| if set the number is normalized
-| Normalize shifting left until bit #FLT_MANT_DIG is set or the exponent 
-| is one (remember that a denormalized number corresponds to an 
-| exponent of -F_BIAS+1).
-#ifndef __mcf5200__
-	cmpw	IMM (1),d2	| remember that the exponent is at least one
-#else
-	cmpl	IMM (1),d2	| remember that the exponent is at least one
-#endif
- 	beq	2f		| an exponent of one means denormalized
-	addl	d1,d1		| else shift and adjust the exponent
-	addxl	d0,d0		|
-#ifndef __mcf5200__
-	dbra	d2,1b		|
-#else
-	subql	IMM (1),d2
-	bpl	1b
-#endif
-2:
-| Now round: we do it as follows: after the shifting we can write the
-| fraction part as f + delta, where 1 < f < 2^25, and 0 <= delta <= 2.
-| If delta < 1, do nothing. If delta > 1, add 1 to f. 
-| If delta == 1, we make sure the rounded number will be even (odd?) 
-| (after shifting).
-	btst	IMM (0),d0	| is delta < 1?
-	beq	2f		| if so, do not do anything
-	tstl	d1		| is delta == 1?
-	bne	1f		| if so round to even
-	movel	d0,d1		| 
-	andl	IMM (2),d1	| bit 1 is the last significant bit
-	addl	d1,d0		| 
-	bra	2f		| 
-1:	movel	IMM (1),d1	| else add 1 
-	addl	d1,d0		|
-| Shift right once (because we used bit #FLT_MANT_DIG!).
-2:	lsrl	IMM (1),d0		
-| Now check again bit #FLT_MANT_DIG (rounding could have produced a
-| 'fraction overflow' ...).
-	btst	IMM (FLT_MANT_DIG),d0	
-	beq	1f
-	lsrl	IMM (1),d0
-#ifndef __mcf5200__
-	addw	IMM (1),d2
-#else
-	addql	IMM (1),d2
-#endif
-1:
-| If bit #FLT_MANT_DIG-1 is clear we have a denormalized number, so we 
-| have to put the exponent to zero and return a denormalized number.
-	btst	IMM (FLT_MANT_DIG-1),d0
-	beq	1f
-	jmp	a0@
-1:	movel	IMM (0),d2
-	jmp	a0@
-
-Lround$to$zero:
-Lround$to$plus:
-Lround$to$minus:
-	jmp	a0@
-#endif /* L_float */
-
-| gcc expects the routines __eqdf2, __nedf2, __gtdf2, __gedf2,
-| __ledf2, __ltdf2 to all return the same value as a direct call to
-| __cmpdf2 would.  In this implementation, each of these routines
-| simply calls __cmpdf2.  It would be more efficient to give the
-| __cmpdf2 routine several names, but separating them out will make it
-| easier to write efficient versions of these routines someday.
-
-#ifdef  L_eqdf2
-	.text
-	.proc
-	.globl	SYM (__eqdf2)
-SYM (__eqdf2):
-	link	a6,IMM (0)
-	movl	a6@(20),sp@-
-	movl	a6@(16),sp@-
-	movl	a6@(12),sp@-
-	movl	a6@(8),sp@-
-	jbsr	SYM (__cmpdf2)
-	unlk	a6
-	rts
-#endif /* L_eqdf2 */
-
-#ifdef  L_nedf2
-	.text
-	.proc
-	.globl	SYM (__nedf2)
-SYM (__nedf2):
-	link	a6,IMM (0)
-	movl	a6@(20),sp@-
-	movl	a6@(16),sp@-
-	movl	a6@(12),sp@-
-	movl	a6@(8),sp@-
-	jbsr	SYM (__cmpdf2)
-	unlk	a6
-	rts
-#endif /* L_nedf2 */
-
-#ifdef  L_gtdf2
-	.text
-	.proc
-	.globl	SYM (__gtdf2)
-SYM (__gtdf2):
-	link	a6,IMM (0)
-	movl	a6@(20),sp@-
-	movl	a6@(16),sp@-
-	movl	a6@(12),sp@-
-	movl	a6@(8),sp@-
-	jbsr	SYM (__cmpdf2)
-	unlk	a6
-	rts
-#endif /* L_gtdf2 */
-
-#ifdef  L_gedf2
-	.text
-	.proc
-	.globl	SYM (__gedf2)
-SYM (__gedf2):
-	link	a6,IMM (0)
-	movl	a6@(20),sp@-
-	movl	a6@(16),sp@-
-	movl	a6@(12),sp@-
-	movl	a6@(8),sp@-
-	jbsr	SYM (__cmpdf2)
-	unlk	a6
-	rts
-#endif /* L_gedf2 */
-
-#ifdef  L_ltdf2
-	.text
-	.proc
-	.globl	SYM (__ltdf2)
-SYM (__ltdf2):
-	link	a6,IMM (0)
-	movl	a6@(20),sp@-
-	movl	a6@(16),sp@-
-	movl	a6@(12),sp@-
-	movl	a6@(8),sp@-
-	jbsr	SYM (__cmpdf2)
-	unlk	a6
-	rts
-#endif /* L_ltdf2 */
-
-#ifdef  L_ledf2
-	.text
-	.proc
-	.globl	SYM (__ledf2)
-SYM (__ledf2):
-	link	a6,IMM (0)
-	movl	a6@(20),sp@-
-	movl	a6@(16),sp@-
-	movl	a6@(12),sp@-
-	movl	a6@(8),sp@-
-	jbsr	SYM (__cmpdf2)
-	unlk	a6
-	rts
-#endif /* L_ledf2 */
-
-| The comments above about __eqdf2, et. al., also apply to __eqsf2,
-| et. al., except that the latter call __cmpsf2 rather than __cmpdf2.
-
-#ifdef  L_eqsf2
-	.text
-	.proc
-	.globl	SYM (__eqsf2)
-SYM (__eqsf2):
-	link	a6,IMM (0)
-	movl	a6@(12),sp@-
-	movl	a6@(8),sp@-
-	jbsr	SYM (__cmpsf2)
-	unlk	a6
-	rts
-#endif /* L_eqsf2 */
-
-#ifdef  L_nesf2
-	.text
-	.proc
-	.globl	SYM (__nesf2)
-SYM (__nesf2):
-	link	a6,IMM (0)
-	movl	a6@(12),sp@-
-	movl	a6@(8),sp@-
-	jbsr	SYM (__cmpsf2)
-	unlk	a6
-	rts
-#endif /* L_nesf2 */
-
-#ifdef  L_gtsf2
-	.text
-	.proc
-	.globl	SYM (__gtsf2)
-SYM (__gtsf2):
-	link	a6,IMM (0)
-	movl	a6@(12),sp@-
-	movl	a6@(8),sp@-
-	jbsr	SYM (__cmpsf2)
-	unlk	a6
-	rts
-#endif /* L_gtsf2 */
-
-#ifdef  L_gesf2
-	.text
-	.proc
-	.globl	SYM (__gesf2)
-SYM (__gesf2):
-	link	a6,IMM (0)
-	movl	a6@(12),sp@-
-	movl	a6@(8),sp@-
-	jbsr	SYM (__cmpsf2)
-	unlk	a6
-	rts
-#endif /* L_gesf2 */
-
-#ifdef  L_ltsf2
-	.text
-	.proc
-	.globl	SYM (__ltsf2)
-SYM (__ltsf2):
-	link	a6,IMM (0)
-	movl	a6@(12),sp@-
-	movl	a6@(8),sp@-
-	jbsr	SYM (__cmpsf2)
-	unlk	a6
-	rts
-#endif /* L_ltsf2 */
-
-#ifdef  L_lesf2
-	.text
-	.proc
-	.globl	SYM (__lesf2)
-SYM (__lesf2):
-	link	a6,IMM (0)
-	movl	a6@(12),sp@-
-	movl	a6@(8),sp@-
-	jbsr	SYM (__cmpsf2)
-	unlk	a6
-	rts
-#endif /* L_lesf2 */
diff --git a/gcc/config/m68k/lb1sun3.asm b/gcc/config/m68k/lb1sun3.asm
deleted file mode 100755
index 7b1854c..0000000
--- a/gcc/config/m68k/lb1sun3.asm
+++ /dev/null
@@ -1,1036 +0,0 @@
-/* libgcc1 routines for 68000 w/o floating-point hardware,
-   calling the Sun3 floating point support routines.  */
-/* Copyright (C) 1992 Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-/* As a special exception, if you link this library with files
-   compiled with GCC to produce an executable, this does not cause
-   the resulting executable to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-#ifdef  L_mulsi3
-	.text
-	.proc
-	.globl	SYM (__mulsi3)
-SYM (__mulsi3):
-	movew	sp@(4), d0	/* x0 -> d0 */
-	muluw	sp@(10), d0	/* x0*y1 */
-	movew	sp@(6), d1	/* x1 -> d1 */
-	muluw	sp@(8), d1	/* x1*y0 */
-	addw	d1, d0
-	swap	d0
-	clrw	d0
-	movew	sp@(6), d1	/* x1 -> d1 */
-	muluw	sp@(10), d1	/* x1*y1 */
-	addl	d1, d0
-
-	rts
-#endif /* L_mulsi3 */
-
-#ifdef  L_udivsi3
-	.text
-	.proc
-	.globl	SYM (__udivsi3)
-SYM (__udivsi3):
-	movel	d2, sp@-
-	movel	sp@(12), d1	/* d1 = divisor */
-	movel	sp@(8), d0	/* d0 = dividend */
-
-	cmpl	#0x10000, d1	/* divisor >= 2 ^ 16 ?   */
-	jcc	L3		/* then try next algorithm */
-	movel	d0, d2
-	clrw	d2
-	swap	d2
-	divu	d1, d2          /* high quotient in lower word */
-	movew	d2, d0		/* save high quotient */
-	swap	d0
-	movew	sp@(10), d2	/* get low dividend + high rest */
-	divu	d1, d2		/* low quotient */
-	movew	d2, d0
-	jra	L6
-
-L3:	movel	d1, d2		/* use d2 as divisor backup */
-L4:	lsrl	#1, d1		/* shift divisor */
-	lsrl	#1, d0		/* shift dividend */
-	cmpl	#0x10000, d1	/* still divisor >= 2 ^ 16 ?  */
-	jcc	L4
-	divu	d1, d0		/* now we have 16 bit divisor */
-	andl	#0xffff, d0	/* mask out divisor, ignore remainder */
-
-/* Muliply the 16 bit tentative quotient with the 32 bit divisor.  Because of
-   the operand ranges, this might give a 33 bit product.  If this product is
-   greater than the dividend, the tentative quotient was too large. */
-	movel	d2, d1
-	mulu	d0, d1		/* low part, 32 bits */
-	swap	d2
-	mulu	d0, d2		/* high part, at most 17 bits */
-	swap	d2		/* align high part with low part */
-	btst	#0, d2		/* high part 17 bits? */
-	jne	L5		/* if 17 bits, quotient was too large */
-	addl	d2, d1		/* add parts */
-	jcs	L5		/* if sum is 33 bits, quotient was too large */
-	cmpl	sp@(8), d1	/* compare the sum with the dividend */
-	jls	L6		/* if sum > dividend, quotient was too large */
-L5:	subql	#1, d0		/* adjust quotient */
-
-L6:	movel	sp@+, d2
-	rts
-#endif /* L_udivsi3 */
-
-#ifdef  L_divsi3
-	.text
-	.proc
-	.globl	SYM (__divsi3)
-SYM (__divsi3):
-	movel	d2, sp@-
-
-	moveb	#1, d2		/* sign of result stored in d2 (=1 or =-1) */
-	movel	sp@(12), d1	/* d1 = divisor */
-	jpl	L1
-	negl	d1
-	negb	d2		/* change sign because divisor <0  */
-L1:	movel	sp@(8), d0	/* d0 = dividend */
-	jpl	L2
-	negl	d0
-	negb	d2
-
-L2:	movel	d1, sp@-
-	movel	d0, sp@-
-	jbsr	SYM (__udivsi3)	/* divide abs(dividend) by abs(divisor) */
-	addql	#8, sp
-
-	tstb	d2
-	jpl	L3
-	negl	d0
-
-L3:	movel	sp@+, d2
-	rts
-#endif /* L_divsi3 */
-
-#ifdef  L_umodsi3
-	.text
-	.proc
-	.globl	SYM (__umodsi3)
-SYM (__umodsi3):
-	movel	sp@(8), d1	/* d1 = divisor */
-	movel	sp@(4), d0	/* d0 = dividend */
-	movel	d1, sp@-
-	movel	d0, sp@-
-	jbsr	SYM (__udivsi3)
-	addql	#8, sp
-	movel	sp@(8), d1	/* d1 = divisor */
-	movel	d1, sp@-
-	movel	d0, sp@-
-	jbsr	SYM (__mulsi3)	/* d0 = (a/b)*b */
-	addql	#8, sp
-	movel	sp@(4), d1	/* d1 = dividend */
-	subl	d0, d1		/* d1 = a - (a/b)*b */
-	movel	d1, d0
-	rts
-#endif /* L_umodsi3 */
-
-#ifdef  L_modsi3
-	.text
-	.proc
-	.globl	SYM (__modsi3)
-SYM (__modsi3):
-	movel	sp@(8), d1	/* d1 = divisor */
-	movel	sp@(4), d0	/* d0 = dividend */
-	movel	d1, sp@-
-	movel	d0, sp@-
-	jbsr	SYM (__divsi3)
-	addql	#8, sp
-	movel	sp@(8), d1	/* d1 = divisor */
-	movel	d1, sp@-
-	movel	d0, sp@-
-	jbsr	SYM (__mulsi3)	/* d0 = (a/b)*b */
-	addql	#8, sp
-	movel	sp@(4), d1	/* d1 = dividend */
-	subl	d0, d1		/* d1 = a - (a/b)*b */
-	movel	d1, d0
-	rts
-#endif /* L_modsi3 */
-
-
-#ifdef  L_divdf3
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 07
-	LF17	=	8
-	LS17	=	0
-	LFF17	=	8
-	LSS17	=	0
-	LV17	=	8
-	.text
-	.globl	___divdf3
-___divdf3:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	lea	a6@(16),a0
-	jbsr	Fdivd
-	movl	d0,a6@(-8)
-	movl	d1,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_divdf3 */
-
-#ifdef  L_muldf3
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 07
-	LF17	=	8
-	LS17	=	0
-	LFF17	=	8
-	LSS17	=	0
-	LV17	=	8
-	.text
-	.globl	___muldf3
-___muldf3:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	lea	a6@(16),a0
-	jbsr	Fmuld
-	movl	d0,a6@(-8)
-	movl	d1,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_muldf3 */
-
-#ifdef  L_negdf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 07
-	LF17	=	8
-	LS17	=	0
-	LFF17	=	8
-	LSS17	=	0
-	LV17	=	8
-	.text
-	.globl	___negdf2
-___negdf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),a6@(-4)
-	bchg	#31,d0
-	movl	d0,a6@(-8)
-	movl	a6@(-4),d1
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_negdf2 */
-
-#ifdef  L_adddf3
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 07
-	LF17	=	8
-	LS17	=	0
-	LFF17	=	8
-	LSS17	=	0
-	LV17	=	8
-	.text
-	.globl	___adddf3
-___adddf3:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	lea	a6@(16),a0
-	jbsr	Faddd
-	movl	d0,a6@(-8)
-	movl	d1,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_adddf3 */
-
-#ifdef  L_subdf3
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 07
-	LF17	=	8
-	LS17	=	0
-	LFF17	=	8
-	LSS17	=	0
-	LV17	=	8
-	.text
-	.globl	___subdf3
-___subdf3:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	lea	a6@(16),a0
-	jbsr	Fsubd
-	movl	d0,a6@(-8)
-	movl	d1,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_subdf3 */
-
-#ifdef  L_fixdfsi
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	4
-	LS17	=	128
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___fixdfsi
-___fixdfsi:
-|#PROLOGUE# 0
-	link	a6,#-4
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	jbsr	Fintd
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_fixdfsi */
-
-#ifdef  L_fixsfsi
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	4
-	LS17	=	128
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___fixsfsi
-___fixsfsi:
-|#PROLOGUE# 0
-	link	a6,#-4
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	jbsr	Fints
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_fixsfsi */
-
-#ifdef  L_floatsidf
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 07
-	LF17	=	8
-	LS17	=	0
-	LFF17	=	8
-	LSS17	=	0
-	LV17	=	8
-	.text
-	.globl	___floatsidf
-___floatsidf:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	jbsr	Ffltd
-	movl	d0,a6@(-8)
-	movl	d1,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_floatsidf */
-
-#ifdef  L_floatsisf
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	128
-	LFF17	=	4
-	LSS17	=	0
-	LV17	=	4
-	.text
-	.globl	___floatsisf
-___floatsisf:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	jbsr	Fflts
-	movl	d0,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_floatsisf */
-
-#ifdef  L_truncdfsf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	128
-	LFF17	=	4
-	LSS17	=	0
-	LV17	=	4
-	.text
-	.globl	___truncdfsf2
-___truncdfsf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	jbsr	Fdtos
-	movl	d0,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_truncdfsf2 */
-
-#ifdef  L_extendsfdf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 07
-	LF17	=	8
-	LS17	=	0
-	LFF17	=	8
-	LSS17	=	0
-	LV17	=	8
-	.text
-	.globl	___extendsfdf2
-___extendsfdf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	jbsr	Fstod
-	movl	d0,a6@(-8)
-	movl	d1,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_extendsfdf2 */
-
-#ifdef  L_addsf3
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	128
-	LFF17	=	4
-	LSS17	=	0
-	LV17	=	4
-	.text
-	.globl	___addsf3
-___addsf3:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	jbsr	Fadds
-	movl	d0,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_addsf3 */
-
-#ifdef  L_negsf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	128
-	LFF17	=	4
-	LSS17	=	0
-	LV17	=	4
-	.text
-	.globl	___negsf2
-___negsf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	bchg	#31,d0
-	movl	d0,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_negsf2 */
-
-#ifdef  L_subsf3
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	128
-	LFF17	=	4
-	LSS17	=	0
-	LV17	=	4
-	.text
-	.globl	___subsf3
-___subsf3:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	jbsr	Fsubs
-	movl	d0,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_subsf3 */
-
-#ifdef  L_mulsf3
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	128
-	LFF17	=	4
-	LSS17	=	0
-	LV17	=	4
-	.text
-	.globl	___mulsf3
-___mulsf3:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	jbsr	Fmuls
-	movl	d0,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_mulsf3 */
-
-#ifdef  L_divsf3
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	128
-	LFF17	=	4
-	LSS17	=	0
-	LV17	=	4
-	.text
-	.globl	___divsf3
-___divsf3:
-|#PROLOGUE# 0
-	link	a6,#-8
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	jbsr	Fdivs
-	movl	d0,a6@(-4)
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_divsf3 */
-
-#ifdef  L_eqdf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	4
-	LS17	=	128
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___eqdf2
-___eqdf2:
-|#PROLOGUE# 0
-	link	a6,#-4
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	lea	a6@(16),a0
-	jbsr	Fcmpd
-	jfeq	L77003
-	moveq	#1,d0
-	jra	L77005
-L77003:
-	moveq	#0,d0
-L77005:
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_eqdf2 */
-
-#ifdef  L_nedf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	132
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___nedf2
-___nedf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-	movl	d7,sp@
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	moveq	#0,d7
-	lea	a6@(16),a0
-	jbsr	Fcmpd
-	sfneq	d7
-	negb	d7
-	movl	d7,d0
-|#PROLOGUE# 2
-	movl	a6@(-8),d7
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_nedf2 */
-
-#ifdef  L_gtdf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	132
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___gtdf2
-___gtdf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-	movl	d7,sp@
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	moveq	#0,d7
-	lea	a6@(16),a0
-	jbsr	Fcmpd
-	sfgt	d7
-	negb	d7
-	movl	d7,d0
-|#PROLOGUE# 2
-	movl	a6@(-8),d7
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_gtdf2 */
-
-#ifdef  L_gedf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	132
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___gedf2
-___gedf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-	movl	d7,sp@
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	moveq	#0,d7
-	lea	a6@(16),a0
-	jbsr	Fcmpd
-	sfge	d7
-	negb	d7
-	subql	#1,d7
-	movl	d7,d0
-|#PROLOGUE# 2
-	movl	a6@(-8),d7
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_gedf2 */
-
-#ifdef  L_ltdf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	132
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___ltdf2
-___ltdf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-	movl	d7,sp@
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	moveq	#0,d7
-	lea	a6@(16),a0
-	jbsr	Fcmpd
-	sflt	d7
-	negb	d7
-	negl	d7
-	movl	d7,d0
-|#PROLOGUE# 2
-	movl	a6@(-8),d7
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_ltdf2 */
-
-#ifdef  L_ledf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	132
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___ledf2
-___ledf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-	movl	d2,sp@
-|#PROLOGUE# 1
-	movl	a6@(8),d0
-	movl	a6@(12),d1
-	moveq	#0,d2
-	lea	a6@(16),a0
-	jbsr	Fcmpd
-	sfle	d2
-	negb	d2
-	moveq	#1,d0
-	subl	d2,d0
-|#PROLOGUE# 2
-	movl	a6@(-8),d2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_ledf2 */
-
-#ifdef  L_eqsf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	4
-	LS17	=	128
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___eqsf2
-___eqsf2:
-|#PROLOGUE# 0
-	link	a6,#-4
-|#PROLOGUE# 1
-	movl	a6@(12),d1
-	movl	a6@(8),d0
-	jbsr	Fcmps
-	jfeq	L77003
-	moveq	#1,d0
-	jra	L77005
-L77003:
-	moveq	#0,d0
-L77005:
-|#PROLOGUE# 2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_eqsf2 */
-
-#ifdef  L_nesf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	132
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___nesf2
-___nesf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-	movl	d7,sp@
-|#PROLOGUE# 1
-	movl	a6@(12),d1
-	movl	a6@(8),d0
-	moveq	#0,d7
-	jbsr	Fcmps
-	sfneq	d7
-	negb	d7
-	movl	d7,d0
-|#PROLOGUE# 2
-	movl	a6@(-8),d7
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_nesf2 */
-
-#ifdef  L_gtsf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	132
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___gtsf2
-___gtsf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-	movl	d7,sp@
-|#PROLOGUE# 1
-	movl	a6@(12),d1
-	movl	a6@(8),d0
-	moveq	#0,d7
-	jbsr	Fcmps
-	sfgt	d7
-	negb	d7
-	movl	d7,d0
-|#PROLOGUE# 2
-	movl	a6@(-8),d7
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_gtsf2 */
-
-#ifdef  L_gesf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	132
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___gesf2
-___gesf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-	movl	d7,sp@
-|#PROLOGUE# 1
-	movl	a6@(12),d1
-	movl	a6@(8),d0
-	moveq	#0,d7
-	jbsr	Fcmps
-	sfge	d7
-	negb	d7
-	subql	#1,d7
-	movl	d7,d0
-|#PROLOGUE# 2
-	movl	a6@(-8),d7
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_gesf2 */
-
-#ifdef  L_ltsf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	132
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___ltsf2
-___ltsf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-	movl	d7,sp@
-|#PROLOGUE# 1
-	movl	a6@(12),d1
-	movl	a6@(8),d0
-	moveq	#0,d7
-	jbsr	Fcmps
-	sflt	d7
-	negb	d7
-	negl	d7
-	movl	d7,d0
-|#PROLOGUE# 2
-	movl	a6@(-8),d7
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_ltsf2 */
-
-#ifdef  L_lesf2
-LL0:
-	.data
-	.data
-	.text
-	.proc
-|#PROC# 04
-	LF17	=	8
-	LS17	=	132
-	LFF17	=	0
-	LSS17	=	0
-	LV17	=	0
-	.text
-	.globl	___lesf2
-___lesf2:
-|#PROLOGUE# 0
-	link	a6,#-8
-	movl	d2,sp@
-|#PROLOGUE# 1
-	movl	a6@(12),d1
-	movl	a6@(8),d0
-	moveq	#0,d2
-	jbsr	Fcmps
-	sfle	d2
-	negb	d2
-	moveq	#1,d0
-	subl	d2,d0
-|#PROLOGUE# 2
-	movl	a6@(-8),d2
-	unlk	a6
-|#PROLOGUE# 3
-	rts
-#endif /* L_lesf2 */
-
diff --git a/gcc/config/m68k/linux-aout.h b/gcc/config/m68k/linux-aout.h
deleted file mode 100755
index 692725e..0000000
--- a/gcc/config/m68k/linux-aout.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Definitions for Motorola m68k running Linux-based GNU systems.
-   Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <m68k/m68k.h>
-#include <linux-aout.h>
-
-/* 68020 with 68881 */
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-
-#define DBX_DEBUGGING_INFO
-
-#define ASM_COMMENT_START "|"
-
-#define CPP_PREDEFINES \
-  "-Dunix -Dmc68000 -Dmc68020 -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(m68k) -Amachine(m68k)"
-
-#undef CPP_SPEC
-#if TARGET_DEFAULT & MASK_68881
-#define CPP_SPEC \
-  "%{!msoft-float:-D__HAVE_68881__} %{posix:-D_POSIX_SOURCE}"
-#else
-#define CPP_SPEC \
-  "%{m68881:-D__HAVE_68881__} %{posix:-D_POSIX_SOURCE}"
-#endif
-
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES	{"ieee-fp", 0},
-
-#undef ASM_SPEC
-#define ASM_SPEC \
-  "%{m68030} %{m68040} %{fpic:-k} %{fPIC:-k}"
-
-#undef LIB_SPEC
-#if 1
-/* We no longer link with libc_p.a or libg.a by default.  If you want
-   to profile or debug the GNU/Linux C library, please add -lc_p or -ggdb
-   to LDFLAGS at the link time, respectively.  */
-#define LIB_SPEC \
-  "%{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}"
-#else
-#define LIB_SPEC \
-  "%{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} %{!p:%{!pg:%{!g*:-lc} %{g*:-lg}}}"
-#endif
-
-/* We want to pass -v to linker */
-#undef LINK_SPEC
-#define LINK_SPEC	"-m m68klinux %{v:-dll-verbose}"
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler.  */
-#undef PCC_STATIC_STRUCT_RETURN
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Allow folding division by zero.  */
-#define REAL_INFINITY
diff --git a/gcc/config/m68k/linux.h b/gcc/config/m68k/linux.h
deleted file mode 100755
index 0df0bd8..0000000
--- a/gcc/config/m68k/linux.h
+++ /dev/null
@@ -1,387 +0,0 @@
-/* Definitions for Motorola 68k running Linux-based GNU systems with
-   ELF format.
-   Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define LINUX_DEFAULT_ELF
-#define MOTOROLA		/* Use Motorola syntax */
-#define USE_GAS			/* But GAS wants jbsr instead of jsr */
-
-#include <m68k/m68k.h>
-
-/* Make sure CC1 is undefined. */
-#undef CC1_SPEC
-
-#include <linux.h>		/* some common stuff */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (68k GNU/Linux with ELF)");
-
-/* 68020 with 68881 */
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-
-/* for 68k machines this only needs to be TRUE for the 68000 */
-
-#undef STRICT_ALIGNMENT     
-#define STRICT_ALIGNMENT 0
-
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES	{"ieee-fp", 0},
-
-/* Here are four prefixes that are used by asm_fprintf to
-   facilitate customization for alternate assembler syntaxes.
-   Machines with no likelihood of an alternate syntax need not
-   define these and need not use asm_fprintf.  */
-
-/* The prefix for register names.  Note that REGISTER_NAMES
-   is supposed to include this prefix. Also note that this is NOT an
-   fprintf format string, it is a literal string */
-
-#undef REGISTER_PREFIX
-#define REGISTER_PREFIX "%"
-
-/* The prefix for local (compiler generated) labels.
-   These labels will not appear in the symbol table. */
-
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX "."
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-
-#define ASM_COMMENT_START "|"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number.
-   Motorola format uses different register names than defined in m68k.h. */
-
-#undef REGISTER_NAMES
-
-#ifndef SUPPORT_SUN_FPA
-
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7" }
-
-#else /* SUPPORTED_SUN_FPA */
-
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7", \
- "%fpa0", "%fpa1", "%fpa2", "%fpa3", "%fpa4", "%fpa5", "%fpa6", "%fpa7", \
- "%fpa8", "%fpa9", "%fpa10","%fpa11","%fpa12","%fpa13","%fpa14","%fpa15", \
- "%fpa16","%fpa17","%fpa18","%fpa19","%fpa20","%fpa21","%fpa22","%fpa23", \
- "%fpa24","%fpa25","%fpa26","%fpa27","%fpa28","%fpa29","%fpa30","%fpa31" }
-
-#endif /* defined SUPPORT_SUN_FPA */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
- 
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-  
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-   
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-#define CPP_PREDEFINES \
-  "-D__ELF__ -Dunix -Dmc68000 -Dmc68020 -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(m68k) -Amachine(m68k)"
-
-#undef CPP_SPEC
-#ifdef USE_GNULIBC_1
-#if TARGET_DEFAULT & MASK_68881
-#define CPP_SPEC \
-  "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{!msoft-float:-D__HAVE_68881__} %{posix:-D_POSIX_SOURCE}"
-#else
-#define CPP_SPEC \
-  "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{m68881:-D__HAVE_68881__} %{posix:-D_POSIX_SOURCE}"
-#endif
-#else
-#if TARGET_DEFAULT & MASK_68881
-#define CPP_SPEC \
-  "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{!msoft-float:-D__HAVE_68881__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
-#else
-#define CPP_SPEC \
-  "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{m68881:-D__HAVE_68881__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
-#endif
-#endif
-
-/* We override the ASM_SPEC from svr4.h because we must pass -m68040 down
-   to the assembler.  */
-#undef ASM_SPEC
-#define ASM_SPEC \
-  "%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
-%{m68040} %{m68060:-m68040}"
-
-/* Provide a LINK_SPEC appropriate for GNU/Linux.  Here we provide support
-   for the special GCC options -static and -shared, which allow us to
-   link things in one of these three modes by applying the appropriate
-   combinations of options at link-time.  We like to support here for
-   as many of the other GNU linker options as possible.  But I don't
-   have the time to search for those flags.  I am sure how to add
-   support for -soname shared_object_name. H.J.
-
-   I took out %{v:%{!V:-V}}.  It is too much :-(.  They can use
-   -Wl,-V.
-
-   When the -shared link option is used a final link is not being
-   done.  */
-
-/* If ELF is the default format, we should not use /lib/elf. */
-
-#undef	LINK_SPEC
-#ifdef USE_GNULIBC_1
-#ifndef LINUX_DEFAULT_ELF
-#define LINK_SPEC "-m m68kelf %{shared} %{symbolic:-shared -Bsymbolic} \
-  %{!shared:%{!symbolic: \
-    %{!static: \
-      %{rdynamic:-export-dynamic} \
-      %{!dynamic-linker*:-dynamic-linker /lib/elf/ld-linux.so.1} \
-      %{!rpath*:-rpath /lib/elf/}} %{static}}}"
-#else
-#define LINK_SPEC "-m m68kelf %{shared} %{symbolic:-shared -Bsymbolic} \
-  %{!shared:%{!symbolic: \
-    %{!static: \
-      %{rdynamic:-export-dynamic} \
-      %{!dynamic-linker*:-dynamic-linker /lib/ld-linux.so.1}} \
-    %{static}}}"
-#endif
-#else
-#define LINK_SPEC "-m m68kelf %{shared} \
-  %{!shared: \
-    %{!static: \
-      %{rdynamic:-export-dynamic} \
-      %{!dynamic-linker*:-dynamic-linker /lib/ld.so.1}} \
-    %{static}}"
-#endif
-
-/* For compatibility with linux/a.out */
-
-#undef PCC_BITFIELD_TYPE_MATTERS
-
-/* Currently, JUMP_TABLES_IN_TEXT_SECTION must be defined in order to
-   keep switch tables in the text section.  */
-   
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* Use the default action for outputting the case label.  */
-#undef ASM_OUTPUT_CASE_LABEL
-#define ASM_RETURN_CASE_JUMP			\
-  do {						\
-    if (TARGET_5200)				\
-      return "ext%.l %0\n\tjmp %%pc@(2,%0:l)";	\
-    else					\
-      return "jmp %%pc@(2,%0:w)";		\
-  } while (0)
-
-/* This is how to output an assembler line that says to advance the
-   location counter to a multiple of 2**LOG bytes.  */
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)				\
-  if ((LOG) > 0)						\
-    fprintf ((FILE), "\t%s \t%u\n", ALIGN_ASM_OP, 1 << (LOG));
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as uninitialized global
-   data.  */
-
-#define BSS_SECTION_ASM_OP ".section\t.bss"
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of uninitialized global DECL named
-   NAME whose size is SIZE bytes and alignment is ALIGN bytes.
-   Try to use asm_output_aligned_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
-{									\
-  asm_fprintf (FILE, "\tlea (%LLP%d,%Rpc),%Ra1\n", (LABELNO));		\
-  if (flag_pic)								\
-    fprintf (FILE, "\tbsr.l _mcount@PLTPC\n");				\
-  else									\
-    fprintf (FILE, "\tjbsr _mcount\n");					\
-}
-
-/* How to renumber registers for dbx and gdb.
-   On the Sun-3, the floating point registers have numbers
-   18 to 25, not 16 to 23 as they do in the compiler.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
-
-/* Do not break .stabs pseudos into continuations.  */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* Allow folding division by zero.  */
-#define REAL_INFINITY
-
-/* 1 if N is a possible register number for a function value.  For
-   m68k/SVR4 allow d0, a0, or fp0 as return registers, for integral,
-   pointer, or floating types, respectively.  Reject fp0 if not using
-   a 68881 coprocessor.  */
-
-#undef FUNCTION_VALUE_REGNO_P
-#define FUNCTION_VALUE_REGNO_P(N) \
-  ((N) == 0 || (N) == 8 || (TARGET_68881 && (N) == 16))
-
-/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
-   more than one register.  */
-
-#undef NEEDS_UNTYPED_CALL
-#define NEEDS_UNTYPED_CALL 1
-
-/* Define how to generate (in the callee) the output value of a
-   function and how to find (in the caller) the value returned by a
-   function.  VALTYPE is the data type of the value (as a tree).  If
-   the precise function being called is known, FUNC is its
-   FUNCTION_DECL; otherwise, FUNC is 0.  For m68k/SVR4 generate the
-   result in d0, a0, or fp0 as appropriate. */
-   
-#undef FUNCTION_VALUE
-#define FUNCTION_VALUE(VALTYPE, FUNC)					\
-  (TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_68881			\
-   ? gen_rtx_REG (TYPE_MODE (VALTYPE), 16)				\
-   : (POINTER_TYPE_P (VALTYPE)						\
-      ? gen_rtx_REG (TYPE_MODE (VALTYPE), 8)				\
-      : gen_rtx_REG (TYPE_MODE (VALTYPE), 0)))
-
-/* For compatibility with the large body of existing code which does
-   not always properly declare external functions returning pointer
-   types, the m68k/SVR4 convention is to copy the value returned for
-   pointer functions from a0 to d0 in the function epilogue, so that
-   callers that have neglected to properly declare the callee can
-   still find the correct return value.  */
-
-extern int current_function_returns_pointer;
-#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)				\
-do {									\
-  if ((current_function_returns_pointer) && 				\
-      ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode))	\
-    asm_fprintf (FILE, "\tmove.l %Ra0,%Rd0\n");				\
-} while (0);
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.
-   For m68k/SVR4 look for integer values in d0, pointer values in d0
-   (returned in both d0 and a0), and floating values in fp0.  */
-
-#undef LIBCALL_VALUE
-#define LIBCALL_VALUE(MODE)						\
-  ((((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)		\
-    && TARGET_68881)							\
-   ? gen_rtx_REG (MODE, 16)						\
-   : gen_rtx_REG (MODE, 0))
-
-/* In m68k svr4, a symbol_ref rtx can be a valid PIC operand if it is
-   an operand of a function call. */
-#undef LEGITIMATE_PIC_OPERAND_P
-#define LEGITIMATE_PIC_OPERAND_P(X) \
-  ((! symbolic_operand (X, VOIDmode) \
-    && ! (GET_CODE (X) == CONST_DOUBLE && CONST_DOUBLE_MEM (X)	\
-	  && GET_CODE (CONST_DOUBLE_MEM (X)) == MEM		\
-	  && symbolic_operand (XEXP (CONST_DOUBLE_MEM (X), 0), VOIDmode))) \
-   || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)))
-
-/* Turn off function cse if we are doing PIC. We always want function
-   call to be done as `bsr foo@PLTPC', so it will force the assembler
-   to create the PLT entry for `foo'.  Doing function cse will cause
-   the address of `foo' to be loaded into a register, which is exactly
-   what we want to avoid when we are doing PIC on svr4 m68k.  */
-#undef SUBTARGET_OVERRIDE_OPTIONS
-#define SUBTARGET_OVERRIDE_OPTIONS \
-  if (flag_pic) flag_no_function_cse = 1;
-
-/* For m68k SVR4, structures are returned using the reentrant
-   technique. */
-#undef PCC_STATIC_STRUCT_RETURN
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Finalize the trampoline by flushing the insn cache.  */
-
-#undef FINALIZE_TRAMPOLINE
-#define FINALIZE_TRAMPOLINE(TRAMP)					\
-  emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"),	\
-		     0, VOIDmode, 2, TRAMP, Pmode,			\
-		     plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode);
-
-/* Clear the instruction cache from `beg' to `end'.  This makes an
-   inline system call to SYS_cacheflush.  The arguments are as
-   follows:
-
-	cacheflush (addr, scope, cache, len)
-
-   addr	  - the start address for the flush
-   scope  - the scope of the flush (see the cpush insn)
-   cache  - which cache to flush (see the cpush insn)
-   len    - a factor relating to the number of flushes to perform:
-   	    len/16 lines, or len/4096 pages.  */
-
-#define CLEAR_INSN_CACHE(BEG, END)					\
-{									\
-  register unsigned long _beg __asm ("%d1") = (unsigned long) (BEG);	\
-  unsigned long _end = (unsigned long) (END);				\
-  register unsigned long _len __asm ("%d4") = (_end - _beg + 32);	\
-  __asm __volatile							\
-    ("move%.l %#123, %/d0\n\t"	/* system call nr */			\
-     "move%.l %#1, %/d2\n\t"	/* clear lines */			\
-     "move%.l %#3, %/d3\n\t"	/* insn+data caches */			\
-     "trap %#0"								\
-     : /* no outputs */							\
-     : "d" (_beg), "d" (_len)						\
-     : "%d0", "%d2", "%d3");						\
-}
-
-/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
-   Used for C++ multiple inheritance.  */
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION)	\
-do {									\
-  if (DELTA > 0 && DELTA <= 8)						\
-    asm_fprintf (FILE, "\taddq.l %I%d,4(%Rsp)\n", DELTA);		\
-  else if (DELTA < 0 && DELTA >= -8)					\
-    asm_fprintf (FILE, "\tsubq.l %I%d,4(%Rsp)\n", -DELTA);		\
-  else									\
-    asm_fprintf (FILE, "\tadd.l %I%d,4(%Rsp)\n", DELTA);		\
-									\
-  if (flag_pic)								\
-    {									\
-      fprintf (FILE, "\tbra.l ");					\
-      assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0));	\
-      fprintf (FILE, "@PLTPC\n");					\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\tjmp ");						\
-      assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0));	\
-      fprintf (FILE, "\n");						\
-    }									\
-} while (0)
diff --git a/gcc/config/m68k/lynx-ng.h b/gcc/config/m68k/lynx-ng.h
deleted file mode 100755
index ac3afac..0000000
--- a/gcc/config/m68k/lynx-ng.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Definitions for Motorola 680x0 running LynxOS, using Lynx's old as and ld.
-   Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <m68k/m68k.h>
-#include <m68k/coff.h>
-#include <lynx-ng.h>
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dmc68000 -DM68K -DLynx -DIBITS32 -Asystem(unix) -Asystem(lynx) -Acpu(m68k) -Amachine(m68k)"
-
-/* Provide required defaults for linker switches.  */
-
-#undef LINK_SPEC
-#define LINK_SPEC "-P1000 %{msystem-v:-V} %{mcoff:-k}"
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
diff --git a/gcc/config/m68k/lynx.h b/gcc/config/m68k/lynx.h
deleted file mode 100755
index 8c54b8b..0000000
--- a/gcc/config/m68k/lynx.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Definitions for Motorola 680x0 running LynxOS.
-   Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <m68k/m68k.h>
-#include <m68k/coff.h>
-
-#undef CTORS_SECTION_ASM_OP
-#undef DTORS_SECTION_ASM_OP
-#undef ASM_OUTPUT_DESTRUCTOR
-#undef SELECT_RTX_SECTION
-
-#define BSS_SECTION_ASM_OP ".bss"
-
-#define ASM_LONG ".long"
-
-#include <lynx.h>
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dmc68000 -DM68K -DLynx -DIBITS32 -Asystem(unix) -Asystem(lynx) -Acpu(m68k) -Amachine(m68k)"
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Lynx uses d2 and d3 as scratch registers. */
-#undef CALL_USED_REGISTERS
-#define CALL_USED_REGISTERS \
- {1, 1, 1, 1, 0, 0, 0, 0,   \
-  1, 1, 0, 0, 0, 0, 0, 1,   \
-  1, 1, 0, 0, 0, 0, 0, 0 }
-
-/* Return floating point values in a fp register.  This make fp code a
-   little bit faster.  It also makes -msoft-float code incompatible with
-   -m68881 code, so people have to be careful not to mix the two.  */
-#undef FUNCTION_VALUE
-#define FUNCTION_VALUE(VALTYPE,FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
-
-#undef LIBCALL_VALUE
-#define LIBCALL_VALUE(MODE)                                                \
- gen_rtx (REG, (MODE),                                                     \
-          ((TARGET_68881                                                   \
-            && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) \
-           ? 16 : 0))
-
-#undef FUNCTION_VALUE_REGNO_P
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (TARGET_68881 && (N) == 16))
-
-#undef NEEDS_UNTYPED_CALL
-#define NEEDS_UNTYPED_CALL 1
diff --git a/gcc/config/m68k/m68020-elf.h b/gcc/config/m68k/m68020-elf.h
deleted file mode 100755
index 94b5d44..0000000
--- a/gcc/config/m68k/m68020-elf.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Definitions of target machine for GNU compiler.  "naked" 68020,
-   elf object files and debugging, version.
-   Copyright (C) 1987, 1988, 1992, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This comment is here to see if it will keep Sun's cpp from dying.  */
-
-#include "m68k/m68k-none.h"
-#include "m68k/m68kelf.h"
-#include "elfos.h"
-/* m68k/m68kemb.h sets some macros in ways that override the svr4 abi.  */
-#include "m68k/m68kemb.h" 
-
-/* We need to override the default specs from elfos.h.  This suppresses the
-   loading of crt0.o by gcc's default linker spec.  For embedded targets crt0
-   now comes from the linker script.  */
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC "crtbegin.o%s"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s"
-
-#define LIB_SPEC "-lc"
-
-/* ??? Quick hack to get constructors working.  Make this look more like a
-   COFF target, so the existing dejagnu/libgloss support works.  A better
-   solution would be to make the necessary dejagnu and libgloss changes so
-   that we can use normal the ELF constructor mechanism.  */
-#undef INIT_SECTION_ASM_OP
-#undef FINI_SECTION_ASM_OP
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC ""
-
-/* end of m68020-elf.h */
diff --git a/gcc/config/m68k/m68360-coff.h b/gcc/config/m68k/m68360-coff.h
deleted file mode 100755
index 9f0c718..0000000
--- a/gcc/config/m68k/m68360-coff.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Definitions of target machine for GNU compiler.  "naked" 68360,
-   COFF object files and debugging, version.
-   Copyright (C) 1987, 1988, 1991, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#define MOTOROLA	/* Use Motorola syntax rather than MIT.  */
-
-#include "m68k/m68360-none.h"
-#include "m68k/m68kemb.h"
-#include "m68k/coff.h"
-
-/* end of m68360-coff.h */
diff --git a/gcc/config/m68k/m68360-none.h b/gcc/config/m68k/m68360-none.h
deleted file mode 100755
index 27b1d60..0000000
--- a/gcc/config/m68k/m68360-none.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* Definitions of target machine for GNU compiler.  "naked" 68360.
-   Copyright (C) 1987, 1988, 1992, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#include "m68k/m68k.h"
-
-/* See m68k.h.  1 means 68020 without bitfield insns or 68881.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 1
-#endif
-
-/* Names to predefine in the preprocessor for this target machine.
-   Always define mc68000.  Other definitions depend on switches given
-   to the compiler:
-
-   -m68000: define nothing else
-   -m68020, -mc68020: define mc68020
-   -m68030: define mc68030
-   -m68040: define mc68040
-   -m68020-40: define mc68020 mc68030 mc68040
-   -m68302: define mc68302
-   -m68332: define mc68332
-   default, -m68360: define mc68360
-   */
-
-#ifndef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmc68000"
-#endif
-
-#ifndef CPP_SPEC
-
-#if TARGET_DEFAULT & 02
-
-/* -m68881 is the default */
-#define CPP_SPEC \
-"%{!mc68000:%{!m68000:%{!m68332:%{!msoft-float:%{mfpa:-D__HAVE_FPA__ }%{!mfpa:-D__HAVE_68881__ }}}}}\
-%{!ansi:%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68302:-Dmc68302 }%{m68332:-Dmc68332 }%{!mc68000:%{!m68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-Dmc68360 }}}}}}}}}}}\
-%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68302:-D__mc68302__ -D__mc68302 }%{m68332:-D__mc68332__ -D__mc68332 }%{!mc68000:%{!m68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-D__mc68360__ -D__mc68360 }}}}}}}}}}"
-
-#else
-#if TARGET_DEFAULT & 0100
-
-/* -mfpa is the default */
-#define CPP_SPEC \
-"%{!msoft-float:%{m68881:-D__HAVE_68881__ }%{!m68881:-D__HAVE_FPA__ }}\
-%{!ansi:%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68302:-Dmc68302 }%{m68332:-Dmc68332 }%{!mc68000:%{!m68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-Dmc68360 }}}}}}}}}}}\
-%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68302:-D__mc68302__ -D__mc68302 }%{m68332:-D__mc68332__ -D__mc68332 }%{!mc68000:%{!m68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-D__mc68360__ -D__mc68360 }}}}}}}}}}"
-
-#else
-
-/* -msoft-float is the default */
-#define CPP_SPEC \
-"%{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }\
-%{!ansi:%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68302:-Dmc68302 }%{m68332:-Dmc68332 }%{!mc68000:%{!m68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-Dmc68360 }}}}}}}}}}}\
-%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68302:-D__mc68302__ -D__mc68302 }%{m68332:-D__mc68332__ -D__mc68332 }%{!mc68000:%{!m68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-D__mc68360__ -D__mc68360 }}}}}}}}}}"
-
-#endif
-#endif
-
-#endif
-
-/* Pass flags to gas indicating which type of processor we have.  */
-
-#ifndef ASM_SPEC
-
-#define ASM_SPEC \
-"%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881 }\
-%{m68000}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040}%{m68302}%{m68332}%{!m68000:%{!mc68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-m68360}}}}}}}}}}"
-
-#endif
-
-#ifndef CC1_SPEC
-
-#define CC1_SPEC \
- "%{m68000:%{!m68881:-msoft-float }}%{m68302:-m68000}%{m68332:-m68020 -mnobitfield %{!m68881:-msoft-float}}%{!m68000:%{!mc68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-m68000}}}}}}}}}}"
-
-#endif
-
-#define HANDLE_SYSV_PRAGMA
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.
-   The m68k/SVR4 convention is to keep the stack pointer longword aligned. */
-
-#undef STACK_BOUNDARY
-#define STACK_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure.
-   For m68k/SVR4, this is the next longword boundary. */
-
-#undef EMPTY_FIELD_BOUNDARY
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-   ((ALIGN) <  BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)           \
-   ((ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* No data type wants to be aligned rounder than this.  */
-#undef BIGGEST_ALIGNMENT
-#define BIGGEST_ALIGNMENT 32
-
-/* Other 68k targets don't have a way to align to more than a two-byte
-   boundary, so we override here.  */
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) == 1)			\
-    fprintf (FILE, "\t.even\n");	\
-  else					\
-    fprintf (FILE, "\t.align %d\n", (LOG))
-/* end of m68360-none.h */
diff --git a/gcc/config/m68k/m68k-aout.h b/gcc/config/m68k/m68k-aout.h
deleted file mode 100755
index b65f9fe..0000000
--- a/gcc/config/m68k/m68k-aout.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Definitions of target machine for GNU compiler.  "naked" 68020,
-   a.out object files and debugging, version.
-   Copyright (C) 1994, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This comment is here to see if it will keep Sun's cpp from dying.  */
-
-#include "m68k/m68k-none.h"
-#include "m68k/m68kemb.h"
-#include "aoutos.h"
-
-#define DBX_DEBUGGING_INFO
-#undef SDB_DEBUGGING_INFO
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as uninitialized global
-   data.  */
-#define BSS_SECTION_ASM_OP "\t.bss"
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of uninitialized global DECL named
-   NAME whose size is SIZE bytes.  The variable ROUNDED
-   is the size rounded up to whatever alignment the caller wants.
-   Try to use asm_output_bss to implement this macro.  */
-/* a.out files typically can't handle arbitrary variable alignments so
-   define ASM_OUTPUT_BSS instead of ASM_OUTPUT_ALIGNED_BSS.  */
-#define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ROUNDED) \
-  asm_output_bss ((FILE), (DECL), (NAME), (SIZE), (ROUNDED))
diff --git a/gcc/config/m68k/m68k-coff.h b/gcc/config/m68k/m68k-coff.h
deleted file mode 100755
index 085dd95..0000000
--- a/gcc/config/m68k/m68k-coff.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Definitions of target machine for GNU compiler.  "naked" 68020,
-   COFF object files and debugging, version.
-   Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MOTOROLA	/* Use Motorola syntax rather than MIT.  */
-
-#include "m68k/m68k-none.h"
-#include "m68k/m68kemb.h"
-#include "m68k/coff.h"
-
-/* end of m68k-coff.h */
diff --git a/gcc/config/m68k/m68k-none.h b/gcc/config/m68k/m68k-none.h
deleted file mode 100755
index c48ac3d..0000000
--- a/gcc/config/m68k/m68k-none.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* Definitions of target machine for GNU compiler.  "naked" 68020.
-   Copyright (C) 1994, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m68k/m68k.h"
-
-/* Default to m68k (m68020).  */
-#ifndef TARGET_CPU_DEFAULT
-#define TARGET_CPU_DEFAULT M68K_CPU_m68k
-#endif
-
-/* These are values set by the configure script in TARGET_CPU_DEFAULT.
-   They are ((desired value for TARGET_DEFAULT) << 4) + sequential integer.
-   See m68k.h for the values (it should really define MASK_FOO so we can
-   use them).  */
-#define M68K_CPU_m68k	((7 << 4) + 0)
-#define M68K_CPU_m68000 ((0 << 4) + 1)
-#define M68K_CPU_m68010 ((0 << 4) + 1) /* make same as m68000 */
-#define M68K_CPU_m68020 ((7 << 4) + 2)
-#define M68K_CPU_m68030 ((7 << 4) + 3)
-#define M68K_CPU_m68040 ((01007 << 4) + 4)
-#define M68K_CPU_m68302 ((0 << 4) + 5)
-#define M68K_CPU_m68332 ((1 << 4) + 6)
-
-/* This is tested for below, so if target wants to override this, it
-   just set this first in cover file.  */
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (TARGET_CPU_DEFAULT >> 4)
-#endif
-
-/* Defaults for the various specs below.
-   These are collected here so we only test TARGET_CPU_DEFAULT once.  */
-/* ??? CC1_CPU_DEFAULT_SPEC was copied over from the earlier version of
-   this file.  However, it's not used anywhere here because it doesn't
-   seem to be necessary.  */
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68k || TARGET_CPU_DEFAULT == M68K_CPU_m68020
-#define CPP_CPU_DEFAULT_SPEC "%{!ansi:-Dmc68020 } -D__mc68020 -D__mc68020__"
-#define ASM_CPU_DEFAULT_SPEC "-mc68020"
-#define CC1_CPU_DEFAULT_SPEC "-m68020"
-#else
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68000
-#define CPP_CPU_DEFAULT_SPEC "%{!ansi:-Dmc68000 } -D__mc68000 -D__mc68000__"
-#define ASM_CPU_DEFAULT_SPEC "-mc68000"
-#define CC1_CPU_DEFAULT_SPEC "-m68000"
-#else
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68030
-#define CPP_CPU_DEFAULT_SPEC "%{!ansi:-Dmc68030 } -D__mc68030 -D__mc68030__"
-#define ASM_CPU_DEFAULT_SPEC "-mc68030"
-#define CC1_CPU_DEFAULT_SPEC "-m68030"
-#else
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68040
-#define CPP_CPU_DEFAULT_SPEC "%{!ansi:-Dmc68040 } -D__mc68040 -D__mc68040__"
-#define ASM_CPU_DEFAULT_SPEC "-mc68040"
-#define CC1_CPU_DEFAULT_SPEC "-m68040"
-#else
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68302
-#define CPP_CPU_DEFAULT_SPEC "%{!ansi:-Dmc68302 } -D__mc68302 -D__mc68302__"
-#define ASM_CPU_DEFAULT_SPEC "-mc68302"
-#define CC1_CPU_DEFAULT_SPEC "-m68302"
-#else
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68332
-#define CPP_CPU_DEFAULT_SPEC "%{!ansi:-Dmc68332 -Dmcpu32 } -D__mc68332 -D__mc68332__ -D__mcpu32 -D__mcpu32__"
-#define ASM_CPU_DEFAULT_SPEC "-mc68332"
-#define CC1_CPU_DEFAULT_SPEC "-m68332"
-#else
-Unrecognized value in TARGET_CPU_DEFAULT.
-#endif
-#endif
-#endif
-#endif
-#endif
-#endif
-
-/* Always define mc68000.
-   Remember that GCC will automatically add __mc68000 and __mc68000__.  */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmc68000"
-
-/* Define one of __HAVE_68881__, __HAVE_FPA__, __HAVE_SKY__, or nothing 
-   (soft float), appropriately.  */
-#undef CPP_FPU_SPEC
-#if TARGET_DEFAULT & MASK_68881
-#define CPP_FPU_SPEC "\
-%{!mc68000:%{!m68000:%{!m68302:%{!mcpu32:%{!m68332:%{!m5200:%{!msoft-float:%{!mno-68881:%{!mfpa:%{!msky:-D__HAVE_68881__ }}}}}}}}}} \
-%{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }%{msky:-D__HAVE_SKY__ }"
-#else
-/* This can't currently happen, but we code it anyway to show how it's done.  */
-#if TARGET_DEFAULT & MASK_FPA
-#define CPP_FPU_SPEC \
-"%{!msoft-float:%{m68881:-D__HAVE_68881__ }%{!m68881:-D__HAVE_FPA__ }}"
-#else
-#define CPP_FPU_SPEC "\
-%{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }%{msky:-D__HAVE_SKY__ }"
-#endif
-#endif
-
-/* Names to predefine in the preprocessor for this target machine.
-   Other definitions depend on what the default cpu is and switches
-   given to the compiler:
-
-   -m68000, -mc68000: define nothing else
-   -m68010: define mc68010
-   -m68020, -mc68020: define mc68020
-   -m68030: define mc68030
-   -m68040: define mc68040
-   -m68060: define mc68060
-   -m68020-40: define mc68020 mc68030 mc68040
-   -m68020-60: define mc68020 mc68030 mc68040 mc68060
-   -m68302: define mc68302 
-   -m68332: define mc68332 mcpu32
-   -mcpu32: define mcpu32
-   -m5200: define mcf5200
-   default: define as above appropriately
-
-   GCC won't automatically add __'d versions, we have to mention them
-   explicitly.  */
-
-#undef CPP_SPEC
-#define CPP_SPEC "\
-%(cpp_fpu)%{!ansi:%{m68302:-Dmc68302 }%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68020-60:-Dmc68020 -Dmc68030 -Dmc68040 -Dmc68060 }%{m68060:-Dmc68060 }%{mcpu32:-Dmcpu32 } %{m68332:-Dmc68332 -Dmcpu32 }%{m5200:-Dmcf5200 }} \
-%{m68302:-D__mc68302__ -D__mc68302 }%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68020-60:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 -D__mc68060__ -D__mc68060 }%{m68060:-D__mc68060__ -D__mc68060 }%{mcpu32:-D__mcpu32__ -D__mcpu32 }%{m68332:-D__mc68332__ -D__mc68332 -D__mcpu32__ -D__mcpu32 }%{m5200:-D__mcf5200__ -D__mcf5200 } \
-%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32: %{!m68332:%{!m5200:%(cpp_cpu_default)}}}}}}}}}}}}}} \
-%(cpp_subtarget) \
-"
-
-/* Pass flags to gas indicating which type of processor we have.  */
-
-#undef ASM_SPEC
-#define ASM_SPEC "\
-%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881 }%{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040 }%{m68020-60:-mc68040 }%{m68060}%{mcpu32}%{m68332}%{m5200}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%(asm_cpu_default) }}}}}}}}}}}}}} \
-"
-
-/* cc1/cc1plus always receives all the -m flags. If the specs strings above 
-   are consistent with the TARGET_OPTIONS flags in m68k.h, there should be no
-   need for any further cc1/cc1plus specs.  */
-
-#undef CC1_SPEC
-#define CC1_SPEC ""
-
-/* This macro defines names of additional specifications to put in the specs
-   that can be used in various specifications like CC1_SPEC.  Its definition
-   is an initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   specification name, and a string constant that used by the GNU CC driver
-   program.
-
-   Do not define this macro if it does not need to do anything.  */
-
-#define EXTRA_SPECS					\
-  { "cpp_cpu_default",	CPP_CPU_DEFAULT_SPEC },		\
-  { "cpp_fpu",		CPP_FPU_SPEC },			\
-  { "cpp_subtarget",	CPP_SUBTARGET_SPEC },		\
-  { "asm_cpu_default",	ASM_CPU_DEFAULT_SPEC },		\
-/*{ "cc1_cpu_default",	CC1_CPU_DEFAULT__SPEC },*/	\
-  SUBTARGET_EXTRA_SPECS
-
-#define CPP_SUBTARGET_SPEC ""
-#define SUBTARGET_EXTRA_SPECS
-
-/* Avoid building multilib libraries for the defaults.
-   t-m68kbare doesn't support -mfpa in the multilib'd libraries, so we don't
-   either.
-   For targets not handled here, just build the full set of multilibs.
-   The default is m68k 99.9% of the time anyway.  */
-
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68k || TARGET_CPU_DEFAULT == M68K_CPU_m68020
-#if TARGET_DEFAULT & MASK_68881
-#define MULTILIB_DEFAULTS { "m68020", "m68881" }
-#else
-#define MULTILIB_DEFAULTS { "m68020", "msoft-float" }
-#endif
-#endif
-
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68000 || TARGET_CPU_DEFAULT == M68K_CPU_m68302
-#if TARGET_DEFAULT & MASK_68881
-#define MULTILIB_DEFAULTS { "m68000", "m68881" }
-#else
-#define MULTILIB_DEFAULTS { "m68000", "msoft-float" }
-#endif
-#endif
diff --git a/gcc/config/m68k/m68k-psos.h b/gcc/config/m68k/m68k-psos.h
deleted file mode 100755
index 8e5b843..0000000
--- a/gcc/config/m68k/m68k-psos.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Definitions of a target machine for the GNU compiler:
-   68040 running pSOS, ELF object files, DBX debugging.
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Use MOTOROLA assembler syntax, as gas is configured that way and
-   glibc also seems to use it. Must come BEFORE m68k.h! */
-
-#define MOTOROLA
-
-/* Get generic m68k definitions. */
-
-#include "m68k/m68k.h"
-#include "m68k/m68kemb.h"
-
-/* Default processor type is a (pure) 68040 with 68881 emulation using
-   the floating-point support package. */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_68040_ONLY|MASK_BITFIELD|MASK_68881|MASK_68020)
-
-/* Options passed to CPP, GAS, CC1 and CC1PLUS. We override
-   m68k-none.h for consistency with TARGET_DEFAULT. */
-
-#undef CPP_SPEC
-#define CPP_SPEC \
-"%{!mc68000:%{!m68000:%{!m68332:%{!msoft-float:-D__HAVE_68881__ }}}}\
-%{!ansi:-Dmc68000 %{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68302:-Dmc68302 }%{m68332:-Dmc68332 }%{!mc68000:%{!m68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-Dmc68040 }}}}}}}}}}}\
--D__mc68000__ -D__mc68000 %{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68302:-D__mc68302__ -D__mc68302 }%{m68332:-D__mc68332__ -D__mc68332 }%{!mc68000:%{!m68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-D__mc68040__ -D__mc68040 }}}}}}}}}}"
-
-#undef ASM_SPEC
-#define ASM_SPEC \
-"%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881 }\
-%{m68000}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040}%{m68302}%{m68332}%{!m68000:%{!mc68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-mc68040}}}}}}}}}}"
-
-#undef CC1_SPEC
-#define CC1_SPEC \
- "%{m68000:%{!m68881:-msoft-float }}%{m68302:-m68000}%{m68332:-m68020 -mnobitfield %{!m68881:-msoft-float}}%{!m68000:%{!mc68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-m68040}}}}}}}}}}"
-
-#undef CC1PLUS_SPEC
-#define CC1PLUS_SPEC \
- "%{m68000:%{!m68881:-msoft-float }}%{m68302:-m68000}%{m68332:-m68020 -mnobitfield %{!m68881:-msoft-float}}%{!m68000:%{!mc68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:-m68040}}}}}}}}}}"
-
-
-/* Get processor-independent pSOS definitions. */
-
-#include "psos.h"
-
-
-/* end of m68k-psos.h */
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
deleted file mode 100755
index 244fa7f..0000000
--- a/gcc/config/m68k/m68k.c
+++ /dev/null
@@ -1,3393 +0,0 @@
-/* Subroutines for insn-output.c for Motorola 68000 family.
-   Copyright (C) 1987, 93-98, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Some output-actions in m68k.md need these.  */
-#include "config.h"
-#include "system.h"
-#include "tree.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "recog.h"
-#include "toplev.h"
-
-/* Needed for use_return_insn.  */
-#include "flags.h"
-
-#ifdef SUPPORT_SUN_FPA
-
-/* Index into this array by (register number >> 3) to find the
-   smallest class which contains that register.  */
-enum reg_class regno_reg_class[]
-  = { DATA_REGS, ADDR_REGS, FP_REGS,
-      LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS };
-
-#endif /* defined SUPPORT_SUN_FPA */
-
-/* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
-   if SGS_SWITCH_TABLE.  */
-int switch_table_difference_label_flag;
-
-static rtx find_addr_reg ();
-rtx legitimize_pic_address ();
-
-
-/* Alignment to use for loops and jumps */
-/* Specify power of two alignment used for loops. */
-char *m68k_align_loops_string;
-/* Specify power of two alignment used for non-loop jumps. */
-char *m68k_align_jumps_string;
-/* Specify power of two alignment used for functions. */
-char *m68k_align_funcs_string;
-
-/* Specify power of two alignment used for loops. */
-int m68k_align_loops;
-/* Specify power of two alignment used for non-loop jumps. */
-int m68k_align_jumps;
-/* Specify power of two alignment used for functions. */
-int m68k_align_funcs;
-
-/* Nonzero if the last compare/test insn had FP operands.  The
-   sCC expanders peek at this to determine what to do for the
-   68060, which has no fsCC instructions.  */
-int m68k_last_compare_had_fp_operands;
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-
-void
-override_options ()
-{
-  int def_align;
-
-  def_align = 1;
-
-  /* Validate -malign-loops= value, or provide default */
-  if (m68k_align_loops_string)
-    {
-      m68k_align_loops = atoi (m68k_align_loops_string);
-      if (m68k_align_loops < 1 || m68k_align_loops > MAX_CODE_ALIGN)
-	fatal ("-malign-loops=%d is not between 1 and %d",
-	       m68k_align_loops, MAX_CODE_ALIGN);
-    }
-  else
-    m68k_align_loops = def_align;
-
-  /* Validate -malign-jumps= value, or provide default */
-  if (m68k_align_jumps_string)
-    {
-      m68k_align_jumps = atoi (m68k_align_jumps_string);
-      if (m68k_align_jumps < 1 || m68k_align_jumps > MAX_CODE_ALIGN)
-	fatal ("-malign-jumps=%d is not between 1 and %d",
-	       m68k_align_jumps, MAX_CODE_ALIGN);
-    }
-  else
-    m68k_align_jumps = def_align;
-
-  /* Validate -malign-functions= value, or provide default */
-  if (m68k_align_funcs_string)
-    {
-      m68k_align_funcs = atoi (m68k_align_funcs_string);
-      if (m68k_align_funcs < 1 || m68k_align_funcs > MAX_CODE_ALIGN)
-	fatal ("-malign-functions=%d is not between 1 and %d",
-	       m68k_align_funcs, MAX_CODE_ALIGN);
-    }
-  else
-    m68k_align_funcs = def_align;
-}
-
-/* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the 
-   function at any time during the compilation process.  In the future 
-   we should try and eliminate the USE if we can easily determine that 
-   all PIC references were deleted from the current function.  That would 
-   save an address register */
-   
-void
-finalize_pic ()
-{
-  if (flag_pic && current_function_uses_pic_offset_table)
-    {
-      rtx insn = gen_rtx_USE (VOIDmode, pic_offset_table_rtx);
-      emit_insn_after (insn, get_insns ());
-      emit_insn (insn);
-    }
-}
-
-
-/* This function generates the assembly code for function entry.
-   STREAM is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This function is responsible for
-   knowing which registers should not be saved even if used.  */
-
-
-/* Note that the order of the bit mask for fmovem is the opposite
-   of the order for movem!  */
-
-
-void
-output_function_prologue (stream, size)
-     FILE *stream;
-     int size;
-{
-  register int regno;
-  register int mask = 0;
-  int num_saved_regs = 0;
-  extern char call_used_regs[];
-  int fsize = (size + 3) & -4;
-  int cfa_offset = INCOMING_FRAME_SP_OFFSET, cfa_store_offset = cfa_offset;
-  
-
-  if (frame_pointer_needed)
-    {
-      if (fsize == 0 && TARGET_68040)
-	{
-	/* on the 68040, pea + move is faster than link.w 0 */
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tpea (%s)\n\tmove.l %s,%s\n",
-	       reg_names[FRAME_POINTER_REGNUM], reg_names[STACK_POINTER_REGNUM],
-	       reg_names[FRAME_POINTER_REGNUM]);
-#else
-	  asm_fprintf (stream, "\tpea %s@\n\tmovel %s,%s\n",
-	       reg_names[FRAME_POINTER_REGNUM], reg_names[STACK_POINTER_REGNUM],
-	       reg_names[FRAME_POINTER_REGNUM]);
-#endif
-	}
-      else if (fsize < 0x8000)
-	{
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tlink.w %s,%0I%d\n",
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);
-#else
-	  asm_fprintf (stream, "\tlink %s,%0I%d\n",
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);
-#endif
-	}
-      else if (TARGET_68020)
-	{
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tlink.l %s,%0I%d\n",
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);
-#else
-	  asm_fprintf (stream, "\tlink %s,%0I%d\n",
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);
-#endif
-	}
-      else
-	{
-      /* Adding negative number is faster on the 68040.  */
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);
-#else
-	  asm_fprintf (stream, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);
-#endif
-	}
-      if (dwarf2out_do_frame ())
-	{
-	  char *l;
-          l = (char *) dwarf2out_cfi_label ();   
-	  cfa_store_offset += 4;
-	  cfa_offset = cfa_store_offset;
-	  dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, cfa_offset);
-	  dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, -cfa_store_offset);
-	  cfa_store_offset += fsize;
-	}
-    }
-  else if (fsize)
-    {
-      if (fsize + 4 < 0x8000)
-	{
-#ifndef NO_ADDSUB_Q
-	  if (fsize + 4 <= 8)
-	    {
-	      if (!TARGET_5200)
-		{
-		  /* asm_fprintf() cannot handle %. */
-#ifdef MOTOROLA
-		  asm_fprintf (stream, "\tsubq.w %0I%d,%Rsp\n", fsize + 4);
-#else
-		  asm_fprintf (stream, "\tsubqw %0I%d,%Rsp\n", fsize + 4);
-#endif
-		}
-	      else
-		{
-		  /* asm_fprintf() cannot handle %. */
-#ifdef MOTOROLA
-		  asm_fprintf (stream, "\tsubq.l %0I%d,%Rsp\n", fsize + 4);
-#else
-		  asm_fprintf (stream, "\tsubql %0I%d,%Rsp\n", fsize + 4);
-#endif
-		}
-	    }
-	  else if (fsize + 4 <= 16 && TARGET_CPU32)
-	    {
-	      /* On the CPU32 it is faster to use two subqw instructions to
-		 subtract a small integer (8 < N <= 16) to a register. */
-	      /* asm_fprintf() cannot handle %. */
-#ifdef MOTOROLA
-	      asm_fprintf (stream, "\tsubq.w %0I8,%Rsp\n\tsubq.w %0I%d,%Rsp\n",
-			   fsize + 4);
-#else
-	      asm_fprintf (stream, "\tsubqw %0I8,%Rsp\n\tsubqw %0I%d,%Rsp\n",
-			   fsize + 4);
-#endif
-	    }
-	  else 
-#endif /* not NO_ADDSUB_Q */
-	  if (TARGET_68040)
-	    {
-	      /* Adding negative number is faster on the 68040.  */
-	      /* asm_fprintf() cannot handle %. */
-#ifdef MOTOROLA
-	      asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", - (fsize + 4));
-#else
-	      asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", - (fsize + 4));
-#endif
-	    }
-	  else
-	    {
-#ifdef MOTOROLA
-	      asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", - (fsize + 4));
-#else
-	      asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", - (fsize + 4));
-#endif
-	    }
-	}
-      else
-	{
-	/* asm_fprintf() cannot handle %. */
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", - (fsize + 4));
-#else
-	  asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", - (fsize + 4));
-#endif
-	}
-      if (dwarf2out_do_frame ())
-	{
-	  cfa_store_offset += fsize;
-	  cfa_offset = cfa_store_offset;
-	  dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset);
-	}
-    }
-#ifdef SUPPORT_SUN_FPA
-  for (regno = 24; regno < 56; regno++)
-    if (regs_ever_live[regno] && ! call_used_regs[regno])
-      {
-#ifdef MOTOROLA
-	asm_fprintf (stream, "\tfpmovd %s,-(%Rsp)\n",
-		     reg_names[regno]);
-#else
-	asm_fprintf (stream, "\tfpmoved %s,%Rsp@-\n",
-		     reg_names[regno]);
-#endif
-	if (dwarf2out_do_frame ())
-	  {
-	    char *l = dwarf2out_cfi_label ();
-
-	    cfa_store_offset += 8;
-	    if (! frame_pointer_needed)
-	      {
-		cfa_offset = cfa_store_offset;
-		dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
-	      }
-	    dwarf2out_reg_save (l, regno, -cfa_store_offset);
-	  }
-      }
-#endif
-  if (TARGET_68881)
-    {
-      for (regno = 16; regno < 24; regno++)
-	if (regs_ever_live[regno] && ! call_used_regs[regno])
-	  {
-	    mask |= 1 << (regno - 16);
-	    num_saved_regs++;
-	  }
-      if ((mask & 0xff) != 0)
-	{
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tfmovm %0I0x%x,-(%Rsp)\n", mask & 0xff);
-#else
-	  asm_fprintf (stream, "\tfmovem %0I0x%x,%Rsp@-\n", mask & 0xff);
-#endif
-	  if (dwarf2out_do_frame ())
-	    {
-	      char *l = (char *) dwarf2out_cfi_label ();
-	      int n_regs;
-
-	      cfa_store_offset += num_saved_regs * 12;
-	      if (! frame_pointer_needed)
-		{
-		  cfa_offset = cfa_store_offset;
-		  dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
-		}
-	      for (regno = 16, n_regs = 0; regno < 24; regno++)
-		if (mask & (1 << (regno - 16)))
-		  dwarf2out_reg_save (l, regno,
-				      -cfa_store_offset + n_regs++ * 12);
-	    }
-	}
-      mask = 0;
-      num_saved_regs = 0;
-    }
-  for (regno = 0; regno < 16; regno++)
-    if (regs_ever_live[regno] && ! call_used_regs[regno])
-      {
-        mask |= 1 << (15 - regno);
-        num_saved_regs++;
-      }
-  if (frame_pointer_needed)
-    {
-      mask &= ~ (1 << (15 - FRAME_POINTER_REGNUM));
-      num_saved_regs--;
-    }
-
-#if NEED_PROBE
-#ifdef MOTOROLA
-#ifdef CRDS
-  asm_fprintf (stream, "\ttstl %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
-#else
-  asm_fprintf (stream, "\ttst.l %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
-#endif
-#else
-  asm_fprintf (stream, "\ttstl %Rsp@(%d)\n", NEED_PROBE - num_saved_regs * 4);
-#endif
-#endif
-
-  if (num_saved_regs <= 2)
-    {
-      /* Store each separately in the same order moveml uses.
-         Using two movel instructions instead of a single moveml
-         is about 15% faster for the 68020 and 68030 at no expense
-         in code size */
-
-      int i;
-
-      /* Undo the work from above. */
-      for (i = 0; i< 16; i++)
-        if (mask & (1 << i))
-	  {
-	    asm_fprintf (stream,
-#ifdef MOTOROLA
-			 "\t%Omove.l %s,-(%Rsp)\n",
-#else
-			 "\tmovel %s,%Rsp@-\n",
-#endif
-			 reg_names[15 - i]);
-	    if (dwarf2out_do_frame ())
-	      {
-		char *l = (char *) dwarf2out_cfi_label ();
-
-		cfa_store_offset += 4;
- 		if (! frame_pointer_needed)
- 		  {
- 		    cfa_offset = cfa_store_offset;
- 		    dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
- 		  }
- 		dwarf2out_reg_save (l, 15 - i, -cfa_store_offset);
-	      }
-	  }
-    }
-  else if (mask)
-    {
-      if (TARGET_5200)
-	{
-	  /* The coldfire does not support the predecrement form of the 
-	     movml instruction, so we must adjust the stack pointer and
-	     then use the plain address register indirect mode.  We also
-	     have to invert the register save mask to use the new mode.
-
-	     FIXME: if num_saved_regs was calculated earlier, we could
-	     combine the stack pointer adjustment with any adjustment
-	     done when the initial stack frame is created.  This would
-	     save an instruction */
-	     
-	  int newmask = 0;
-	  int i;
-
-	  for (i = 0; i < 16; i++)
-	    if (mask & (1 << i))
-		newmask |= (1 << (15-i));
-
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs*4);
-	  asm_fprintf (stream, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask);
-#else
-	  asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs*4);
-	  asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@\n", newmask);
-#endif
-	}
-      else
-	{
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask);
-#else
-	  asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@-\n", mask);
-#endif
-	}
-      if (dwarf2out_do_frame ())
-	{
-	  char *l = (char *) dwarf2out_cfi_label ();
-	  int n_regs;
-
-	  cfa_store_offset += num_saved_regs * 4;
-	  if (! frame_pointer_needed)
-	    {
-	      cfa_offset = cfa_store_offset;
-	      dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
-	    }
-	  for (regno = 0, n_regs = 0; regno < 16; regno++)
-	    if (mask & (1 << (15 - regno)))
-	      dwarf2out_reg_save (l, regno,
-				  -cfa_store_offset + n_regs++ * 4);
-	}
-    }
-  if (flag_pic && current_function_uses_pic_offset_table)
-    {
-#ifdef MOTOROLA
-      asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
-		   reg_names[PIC_OFFSET_TABLE_REGNUM]);
-#else
-      asm_fprintf (stream, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
-		   reg_names[PIC_OFFSET_TABLE_REGNUM]);
-      asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n",
-		   reg_names[PIC_OFFSET_TABLE_REGNUM],
-		   reg_names[PIC_OFFSET_TABLE_REGNUM]);
-#endif
-    }
-}
-
-/* Return true if this function's epilogue can be output as RTL.  */
-
-int
-use_return_insn ()
-{
-  int regno;
-
-  if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
-    return 0;
-  
-  /* Copied from output_function_epilogue ().  We should probably create a
-     separate layout routine to perform the common work.  */
-  
-  for (regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno++)
-    if (regs_ever_live[regno] && ! call_used_regs[regno])
-      return 0;
-  
-  return 1;
-}
-
-/* This function generates the assembly code for function exit,
-   on machines that need it.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only, if there is a frame pointer.
-   This is mandatory because of alloca; we also take advantage of it to
-   omit stack adjustments before returning.  */
-
-void
-output_function_epilogue (stream, size)
-     FILE *stream;
-     int size;
-{
-  register int regno;
-  register int mask, fmask;
-  register int nregs;
-  int offset, foffset, fpoffset;
-  extern char call_used_regs[];
-  int fsize = (size + 3) & -4;
-  int big = 0;
-  rtx insn = get_last_insn ();
-  int restore_from_sp = 0;
-  
-  /* If the last insn was a BARRIER, we don't have to write any code.  */
-  if (GET_CODE (insn) == NOTE)
-    insn = prev_nonnote_insn (insn);
-  if (insn && GET_CODE (insn) == BARRIER)
-    {
-      /* Output just a no-op so that debuggers don't get confused
-	 about which function the pc is in at this address.  */
-      asm_fprintf (stream, "\tnop\n");
-      return;
-    }
-
-#ifdef FUNCTION_BLOCK_PROFILER_EXIT
-  if (profile_block_flag == 2)
-    {
-      FUNCTION_BLOCK_PROFILER_EXIT (stream);
-    }
-#endif
-
-#ifdef FUNCTION_EXTRA_EPILOGUE
-  FUNCTION_EXTRA_EPILOGUE (stream, size);
-#endif
-  nregs = 0;  fmask = 0; fpoffset = 0;
-#ifdef SUPPORT_SUN_FPA
-  for (regno = 24 ; regno < 56 ; regno++)
-    if (regs_ever_live[regno] && ! call_used_regs[regno])
-      nregs++;
-  fpoffset = nregs * 8;
-#endif
-  nregs = 0;
-  if (TARGET_68881)
-    {
-      for (regno = 16; regno < 24; regno++)
-	if (regs_ever_live[regno] && ! call_used_regs[regno])
-	  {
-	    nregs++;
-	    fmask |= 1 << (23 - regno);
-	  }
-    }
-  foffset = fpoffset + nregs * 12;
-  nregs = 0;  mask = 0;
-  if (frame_pointer_needed)
-    regs_ever_live[FRAME_POINTER_REGNUM] = 0;
-  for (regno = 0; regno < 16; regno++)
-    if (regs_ever_live[regno] && ! call_used_regs[regno])
-      {
-        nregs++;
-	mask |= 1 << regno;
-      }
-  offset = foffset + nregs * 4;
-  /* FIXME : leaf_function_p below is too strong.
-     What we really need to know there is if there could be pending
-     stack adjustment needed at that point. */
-  restore_from_sp = ! frame_pointer_needed
-	     || (! current_function_calls_alloca && leaf_function_p ());
-  if (offset + fsize >= 0x8000
-      && ! restore_from_sp
-      && (mask || fmask || fpoffset))
-    {
-#ifdef MOTOROLA
-      asm_fprintf (stream, "\t%Omove.l %0I%d,%Ra1\n", -fsize);
-#else
-      asm_fprintf (stream, "\tmovel %0I%d,%Ra1\n", -fsize);
-#endif
-      fsize = 0, big = 1;
-    }
-  if (TARGET_5200 || nregs <= 2)
-    {
-      /* Restore each separately in the same order moveml does.
-         Using two movel instructions instead of a single moveml
-         is about 15% faster for the 68020 and 68030 at no expense
-         in code size. */
-
-      int i;
-
-      /* Undo the work from above. */
-      for (i = 0; i< 16; i++)
-        if (mask & (1 << i))
-          {
-            if (big)
-	      {
-#ifdef MOTOROLA
-		asm_fprintf (stream, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
-			     offset + fsize,
-			     reg_names[FRAME_POINTER_REGNUM],
-			     reg_names[i]);
-#else
-		asm_fprintf (stream, "\tmovel %s@(-%d,%Ra1:l),%s\n",
-			     reg_names[FRAME_POINTER_REGNUM],
-			     offset + fsize, reg_names[i]);
-#endif
-	      }
-            else if (restore_from_sp)
-	      {
-#ifdef MOTOROLA
-		asm_fprintf (stream, "\t%Omove.l (%Rsp)+,%s\n",
-			     reg_names[i]);
-#else
-		asm_fprintf (stream, "\tmovel %Rsp@+,%s\n",
-			     reg_names[i]);
-#endif
-	      }
-            else
-	      {
-#ifdef MOTOROLA
-		asm_fprintf (stream, "\t%Omove.l -%d(%s),%s\n",
-			     offset + fsize,
-			     reg_names[FRAME_POINTER_REGNUM],
-			     reg_names[i]);
-#else
-		asm_fprintf (stream, "\tmovel %s@(-%d),%s\n",
-			     reg_names[FRAME_POINTER_REGNUM],
-			     offset + fsize, reg_names[i]);
-#endif
-	      }
-            offset = offset - 4;
-          }
-    }
-  else if (mask)
-    {
-      if (big)
-	{
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
-		       offset + fsize,
-		       reg_names[FRAME_POINTER_REGNUM],
-		       mask);
-#else
-	  asm_fprintf (stream, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
-		       reg_names[FRAME_POINTER_REGNUM],
-		       offset + fsize, mask);
-#endif
-	}
-      else if (restore_from_sp)
-	{
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask);
-#else
-	  asm_fprintf (stream, "\tmoveml %Rsp@+,%0I0x%x\n", mask);
-#endif
-	}
-      else
-	{
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tmovm.l -%d(%s),%0I0x%x\n",
-		       offset + fsize,
-		       reg_names[FRAME_POINTER_REGNUM],
-		       mask);
-#else
-	  asm_fprintf (stream, "\tmoveml %s@(-%d),%0I0x%x\n",
-		       reg_names[FRAME_POINTER_REGNUM],
-		       offset + fsize, mask);
-#endif
-	}
-    }
-  if (fmask)
-    {
-      if (big)
-	{
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
-		       foffset + fsize,
-		       reg_names[FRAME_POINTER_REGNUM],
-		       fmask);
-#else
-	  asm_fprintf (stream, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
-		       reg_names[FRAME_POINTER_REGNUM],
-		       foffset + fsize, fmask);
-#endif
-	}
-      else if (restore_from_sp)
-	{
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask);
-#else
-	  asm_fprintf (stream, "\tfmovem %Rsp@+,%0I0x%x\n", fmask);
-#endif
-	}
-      else
-	{
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tfmovm -%d(%s),%0I0x%x\n",
-		       foffset + fsize,
-		       reg_names[FRAME_POINTER_REGNUM],
-		       fmask);
-#else
-	  asm_fprintf (stream, "\tfmovem %s@(-%d),%0I0x%x\n",
-		       reg_names[FRAME_POINTER_REGNUM],
-		       foffset + fsize, fmask);
-#endif
-	}
-    }
-  if (fpoffset != 0)
-    for (regno = 55; regno >= 24; regno--)
-      if (regs_ever_live[regno] && ! call_used_regs[regno])
-        {
-	  if (big)
-	    {
-#ifdef MOTOROLA
-	      asm_fprintf (stream, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
-			   fpoffset + fsize,
-			   reg_names[FRAME_POINTER_REGNUM],
-			   reg_names[regno]);
-#else
-	      asm_fprintf (stream, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
-			   reg_names[FRAME_POINTER_REGNUM],
-			   fpoffset + fsize, reg_names[regno]);
-#endif
-	    }
-	  else if (restore_from_sp)
-	    {
-#ifdef MOTOROLA
-	      asm_fprintf (stream, "\tfpmovd (%Rsp)+,%s\n",
-			   reg_names[regno]);
-#else
-	      asm_fprintf (stream, "\tfpmoved %Rsp@+, %s\n",
-			   reg_names[regno]);
-#endif
-	    }
-	  else
-	    {
-#ifdef MOTOROLA
-	      asm_fprintf (stream, "\tfpmovd -%d(%s), %s\n",
-			   fpoffset + fsize,
-			   reg_names[FRAME_POINTER_REGNUM],
-			   reg_names[regno]);
-#else
-	      asm_fprintf (stream, "\tfpmoved %s@(-%d), %s\n",
-			   reg_names[FRAME_POINTER_REGNUM],
-			   fpoffset + fsize, reg_names[regno]);
-#endif
-	    }
-	  fpoffset -= 8;
-	}
-  if (frame_pointer_needed)
-    fprintf (stream, "\tunlk %s\n",
-	     reg_names[FRAME_POINTER_REGNUM]);
-  else if (fsize)
-    {
-#ifndef NO_ADDSUB_Q
-      if (fsize + 4 <= 8) 
-	{
-	  if (!TARGET_5200)
-	    {
-#ifdef MOTOROLA
-	      asm_fprintf (stream, "\taddq.w %0I%d,%Rsp\n", fsize + 4);
-#else
-	      asm_fprintf (stream, "\taddqw %0I%d,%Rsp\n", fsize + 4);
-#endif
-	    }
-	  else
-	    {
-#ifdef MOTOROLA
-	      asm_fprintf (stream, "\taddq.l %0I%d,%Rsp\n", fsize + 4);
-#else
-	      asm_fprintf (stream, "\taddql %0I%d,%Rsp\n", fsize + 4);
-#endif
-	    }
-	}
-      else if (fsize + 4 <= 16 && TARGET_CPU32)
-	{
-	  /* On the CPU32 it is faster to use two addqw instructions to
-	     add a small integer (8 < N <= 16) to a register. */
-	  /* asm_fprintf() cannot handle %. */
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\taddq.w %0I8,%Rsp\n\taddq.w %0I%d,%Rsp\n",
-		       fsize + 4);
-#else
-	  asm_fprintf (stream, "\taddqw %0I8,%Rsp\n\taddqw %0I%d,%Rsp\n",
-		       fsize + 4);
-#endif
-	}
-      else
-#endif /* not NO_ADDSUB_Q */
-      if (fsize + 4 < 0x8000)
-	{
-	  if (TARGET_68040)
-	    { 
-	      /* asm_fprintf() cannot handle %. */
-#ifdef MOTOROLA
-	      asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", fsize + 4);
-#else
-	      asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", fsize + 4);
-#endif
-	    }
-	  else
-	    {
-#ifdef MOTOROLA
-	      asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", fsize + 4);
-#else
-	      asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", fsize + 4);
-#endif
-	    }
-	}
-      else
-	{
-	/* asm_fprintf() cannot handle %. */
-#ifdef MOTOROLA
-	  asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", fsize + 4);
-#else
-	  asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", fsize + 4);
-#endif
-	}
-    }
-  if (current_function_pops_args)
-    asm_fprintf (stream, "\trtd %0I%d\n", current_function_pops_args);
-  else
-    fprintf (stream, "\trts\n");
-}
-
-/* Similar to general_operand, but exclude stack_pointer_rtx.  */
-
-int
-not_sp_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return op != stack_pointer_rtx && general_operand (op, mode);
-}
-
-/* Return TRUE if X is a valid comparison operator for the dbcc 
-   instruction.  
-
-   Note it rejects floating point comparison operators.
-   (In the future we could use Fdbcc).
-
-   It also rejects some comparisons when CC_NO_OVERFLOW is set.  */
-   
-int
-valid_dbcc_comparison_p (x, mode)
-     rtx x;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  switch (GET_CODE (x))
-    {
-      case EQ: case NE: case GTU: case LTU:
-      case GEU: case LEU:
-        return 1;
-
-      /* Reject some when CC_NO_OVERFLOW is set.  This may be over
-         conservative */
-      case GT: case LT: case GE: case LE:
-        return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
-      default:
-        return 0;
-    }
-}
-
-/* Return non-zero if flags are currently in the 68881 flag register.  */
-int
-flags_in_68881 ()
-{
-  /* We could add support for these in the future */
-  return cc_status.flags & CC_IN_68881;
-}
-
-/* Output a dbCC; jCC sequence.  Note we do not handle the 
-   floating point version of this sequence (Fdbcc).  We also
-   do not handle alternative conditions when CC_NO_OVERFLOW is
-   set.  It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
-   kick those out before we get here.  */
-
-void
-output_dbcc_and_branch (operands)
-     rtx *operands;
-{
-  switch (GET_CODE (operands[3]))
-    {
-      case EQ:
-#ifdef MOTOROLA
-        output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands);
-#else
-        output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
-#endif
-        break;
-
-      case NE:
-#ifdef MOTOROLA
-        output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands);
-#else
-        output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
-#endif
-        break;
-
-      case GT:
-#ifdef MOTOROLA
-        output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands);
-#else
-        output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
-#endif
-        break;
-
-      case GTU:
-#ifdef MOTOROLA
-        output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands);
-#else
-        output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
-#endif
-        break;
-
-      case LT:
-#ifdef MOTOROLA
-        output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands);
-#else
-        output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
-#endif
-        break;
-
-      case LTU:
-#ifdef MOTOROLA
-        output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands);
-#else
-        output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
-#endif
-        break;
-
-      case GE:
-#ifdef MOTOROLA
-        output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands);
-#else
-        output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
-#endif
-        break;
-
-      case GEU:
-#ifdef MOTOROLA
-        output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands);
-#else
-        output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
-#endif
-        break;
-
-      case LE:
-#ifdef MOTOROLA
-        output_asm_insn ("dble %0,%l1\n\tjble %l2", operands);
-#else
-        output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
-#endif
-        break;
-
-      case LEU:
-#ifdef MOTOROLA
-        output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands);
-#else
-        output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
-#endif
-        break;
-
-      default:
-	abort ();
-    }
-
-  /* If the decrement is to be done in SImode, then we have
-     to compensate for the fact that dbcc decrements in HImode. */
-  switch (GET_MODE (operands[0]))
-    {
-      case SImode:
-#ifdef MOTOROLA
-        output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands);
-#else
-        output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands);
-#endif
-        break;
-
-      case HImode:
-        break;
-
-      default:
-        abort ();
-    }
-}
-
-char *
-output_scc_di(op, operand1, operand2, dest)
-     rtx op;
-     rtx operand1;
-     rtx operand2;
-     rtx dest;
-{
-  rtx loperands[7];
-  enum rtx_code op_code = GET_CODE (op);
-
-  /* This does not produce a usefull cc.  */
-  CC_STATUS_INIT;
-
-  /* The m68k cmp.l instruction requires operand1 to be a reg as used
-     below.  Swap the operands and change the op if these requirements
-     are not fulfilled.  */
-  if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
-    {
-      rtx tmp = operand1;
-
-      operand1 = operand2;
-      operand2 = tmp;
-      op_code = swap_condition (op_code);
-    }
-  loperands[0] = operand1;
-  if (GET_CODE (operand1) == REG)
-    loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
-  else
-    loperands[1] = adj_offsettable_operand (operand1, 4);
-  if (operand2 != const0_rtx)
-    {
-      loperands[2] = operand2;
-      if (GET_CODE (operand2) == REG)
-	loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
-      else
-	loperands[3] = adj_offsettable_operand (operand2, 4);
-    }
-  loperands[4] = gen_label_rtx();
-  if (operand2 != const0_rtx)
-    {
-#ifdef MOTOROLA
-#ifdef SGS_CMP_ORDER
-      output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands);
-#else
-      output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands);
-#endif
-#else
-#ifdef SGS_CMP_ORDER
-      output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands);
-#else
-      output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
-#endif
-#endif
-    }
-  else
-    {
-      if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[0]))
-	output_asm_insn ("tst%.l %0", loperands);
-      else
-	{
-#ifdef SGS_CMP_ORDER
-	  output_asm_insn ("cmp%.w %0,%#0", loperands);
-#else
-	  output_asm_insn ("cmp%.w %#0,%0", loperands);
-#endif
-	}
-
-#ifdef MOTOROLA
-      output_asm_insn ("jbne %l4", loperands);
-#else
-      output_asm_insn ("jne %l4", loperands);
-#endif
-
-      if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[1]))
-	output_asm_insn ("tst%.l %1", loperands);
-      else
-	{
-#ifdef SGS_CMP_ORDER
-	  output_asm_insn ("cmp%.w %1,%#0", loperands);
-#else
-	  output_asm_insn ("cmp%.w %#0,%1", loperands);
-#endif
-	}
-    }
-
-  loperands[5] = dest;
-  
-  switch (op_code)
-    {
-      case EQ:
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[4]));
-        output_asm_insn ("seq %5", loperands);
-        break;
-
-      case NE:
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[4]));
-        output_asm_insn ("sne %5", loperands);
-        break;
-
-      case GT:
-        loperands[6] = gen_label_rtx();
-#ifdef MOTOROLA
-        output_asm_insn ("shi %5\n\tjbra %l6", loperands);
-#else
-        output_asm_insn ("shi %5\n\tjra %l6", loperands);
-#endif
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[4]));
-        output_asm_insn ("sgt %5", loperands);
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[6]));
-        break;
-
-      case GTU:
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[4]));
-        output_asm_insn ("shi %5", loperands);
-        break;
-
-      case LT:
-        loperands[6] = gen_label_rtx();
-#ifdef MOTOROLA
-        output_asm_insn ("scs %5\n\tjbra %l6", loperands);
-#else
-        output_asm_insn ("scs %5\n\tjra %l6", loperands);
-#endif
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[4]));
-        output_asm_insn ("slt %5", loperands);
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[6]));
-        break;
-
-      case LTU:
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[4]));
-        output_asm_insn ("scs %5", loperands);
-        break;
-
-      case GE:
-        loperands[6] = gen_label_rtx();
-#ifdef MOTOROLA
-        output_asm_insn ("scc %5\n\tjbra %l6", loperands);
-#else
-        output_asm_insn ("scc %5\n\tjra %l6", loperands);
-#endif
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[4]));
-        output_asm_insn ("sge %5", loperands);
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[6]));
-        break;
-
-      case GEU:
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[4]));
-        output_asm_insn ("scc %5", loperands);
-        break;
-
-      case LE:
-        loperands[6] = gen_label_rtx();
-#ifdef MOTOROLA
-        output_asm_insn ("sls %5\n\tjbra %l6", loperands);
-#else
-        output_asm_insn ("sls %5\n\tjra %l6", loperands);
-#endif
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[4]));
-        output_asm_insn ("sle %5", loperands);
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[6]));
-        break;
-
-      case LEU:
-        ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				    CODE_LABEL_NUMBER (loperands[4]));
-        output_asm_insn ("sls %5", loperands);
-        break;
-
-      default:
-	abort ();
-    }
-  return "";
-}
-
-char *
-output_btst (operands, countop, dataop, insn, signpos)
-     rtx *operands;
-     rtx countop, dataop;
-     rtx insn;
-     int signpos;
-{
-  operands[0] = countop;
-  operands[1] = dataop;
-
-  if (GET_CODE (countop) == CONST_INT)
-    {
-      register int count = INTVAL (countop);
-      /* If COUNT is bigger than size of storage unit in use,
-	 advance to the containing unit of same size.  */
-      if (count > signpos)
-	{
-	  int offset = (count & ~signpos) / 8;
-	  count = count & signpos;
-	  operands[1] = dataop = adj_offsettable_operand (dataop, offset);
-	}
-      if (count == signpos)
-	cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
-      else
-	cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
-
-      /* These three statements used to use next_insns_test_no...
-	 but it appears that this should do the same job.  */
-      if (count == 31
-	  && next_insn_tests_no_inequality (insn))
-	return "tst%.l %1";
-      if (count == 15
-	  && next_insn_tests_no_inequality (insn))
-	return "tst%.w %1";
-      if (count == 7
-	  && next_insn_tests_no_inequality (insn))
-	return "tst%.b %1";
-
-      cc_status.flags = CC_NOT_NEGATIVE;
-    }
-  return "btst %0,%1";
-}
-
-/* Returns 1 if OP is either a symbol reference or a sum of a symbol
-   reference and a constant.  */
-
-int
-symbolic_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return 1;
-
-    case CONST:
-      op = XEXP (op, 0);
-      return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
-	       || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-	      && GET_CODE (XEXP (op, 1)) == CONST_INT);
-
-#if 0 /* Deleted, with corresponding change in m68k.h,
-	 so as to fit the specs.  No CONST_DOUBLE is ever symbolic.  */
-    case CONST_DOUBLE:
-      return GET_MODE (op) == mode;
-#endif
-
-    default:
-      return 0;
-    }
-}
-
-/* Check for sign_extend or zero_extend.  Used for bit-count operands. */
-
-int
-extend_operator(x, mode)
-     rtx x;
-     enum machine_mode mode;
-{
-    if (mode != VOIDmode && GET_MODE(x) != mode)
-	return 0;
-    switch (GET_CODE(x))
-	{
-	case SIGN_EXTEND :
-	case ZERO_EXTEND :
-	    return 1;
-	default :
-	    return 0;
-	}
-}
-
-
-/* Legitimize PIC addresses.  If the address is already
-   position-independent, we return ORIG.  Newly generated
-   position-independent addresses go to REG.  If we need more
-   than one register, we lose.  
-
-   An address is legitimized by making an indirect reference
-   through the Global Offset Table with the name of the symbol
-   used as an offset.  
-
-   The assembler and linker are responsible for placing the 
-   address of the symbol in the GOT.  The function prologue
-   is responsible for initializing a5 to the starting address
-   of the GOT.
-
-   The assembler is also responsible for translating a symbol name
-   into a constant displacement from the start of the GOT.  
-
-   A quick example may make things a little clearer:
-
-   When not generating PIC code to store the value 12345 into _foo
-   we would generate the following code:
-
-	movel #12345, _foo
-
-   When generating PIC two transformations are made.  First, the compiler
-   loads the address of foo into a register.  So the first transformation makes:
-
-	lea	_foo, a0
-	movel   #12345, a0@
-
-   The code in movsi will intercept the lea instruction and call this
-   routine which will transform the instructions into:
-
-	movel   a5@(_foo:w), a0
-	movel   #12345, a0@
-   
-
-   That (in a nutshell) is how *all* symbol and label references are 
-   handled.  */
-
-rtx
-legitimize_pic_address (orig, mode, reg)
-     rtx orig, reg;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  rtx pic_ref = orig;
-
-  /* First handle a simple SYMBOL_REF or LABEL_REF */
-  if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
-    {
-      if (reg == 0)
-	abort ();
-
-      pic_ref = gen_rtx_MEM (Pmode,
-			     gen_rtx_PLUS (Pmode,
-					   pic_offset_table_rtx, orig));
-      current_function_uses_pic_offset_table = 1;
-      if (reload_in_progress)
-	regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
-      RTX_UNCHANGING_P (pic_ref) = 1;
-      emit_move_insn (reg, pic_ref);
-      return reg;
-    }
-  else if (GET_CODE (orig) == CONST)
-    {
-      rtx base;
-
-      /* Make sure this is CONST has not already been legitimized */
-      if (GET_CODE (XEXP (orig, 0)) == PLUS
-	  && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
-	return orig;
-
-      if (reg == 0)
-	abort ();
-
-      /* legitimize both operands of the PLUS */
-      if (GET_CODE (XEXP (orig, 0)) == PLUS)
-	{
-	  base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
-	  orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
-					 base == reg ? 0 : reg);
-	}
-      else abort ();
-
-      if (GET_CODE (orig) == CONST_INT)
-	return plus_constant_for_output (base, INTVAL (orig));
-      pic_ref = gen_rtx_PLUS (Pmode, base, orig);
-      /* Likewise, should we set special REG_NOTEs here?  */
-    }
-  return pic_ref;
-}
-
-
-typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ } CONST_METHOD;
-
-#define USE_MOVQ(i)	((unsigned)((i) + 128) <= 255)
-
-CONST_METHOD
-const_method (constant)
-     rtx constant;
-{
-  int i;
-  unsigned u;
-
-  i = INTVAL (constant);
-  if (USE_MOVQ (i))
-    return MOVQ;
-
-  /* The Coldfire doesn't have byte or word operations. */
-  /* FIXME: This may not be useful for the m68060 either */
-  if (!TARGET_5200) 
-    {
-      /* if -256 < N < 256 but N is not in range for a moveq
-	 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
-      if (USE_MOVQ (i ^ 0xff))
-	return NOTB;
-      /* Likewise, try with not.w */
-      if (USE_MOVQ (i ^ 0xffff))
-	return NOTW;
-      /* This is the only value where neg.w is useful */
-      if (i == -65408)
-	return NEGW;
-      /* Try also with swap */
-      u = i;
-      if (USE_MOVQ ((u >> 16) | (u << 16)))
-	return SWAP;
-    }
-  /* Otherwise, use move.l */
-  return MOVL;
-}
-
-int
-const_int_cost (constant)
-     rtx constant;
-{
-  switch (const_method (constant))
-    {
-      case MOVQ :
-      /* Constants between -128 and 127 are cheap due to moveq */
-	return 0;
-      case NOTB :
-      case NOTW :
-      case NEGW :
-      case SWAP :
-      /* Constants easily generated by moveq + not.b/not.w/neg.w/swap  */
-        return 1;
-      case MOVL :
-	return 2;
-      default :
-        abort ();
-    }
-}
-
-char *
-output_move_const_into_data_reg (operands)
-     rtx *operands;
-{
-  int i;
-
-  i = INTVAL (operands[1]);
-  switch (const_method (operands[1]))
-    {
-    case MOVQ :
-#if defined (MOTOROLA) && !defined (CRDS)
-      return "moveq%.l %1,%0";
-#else
-      return "moveq %1,%0";
-#endif
-    case NOTB :
-      operands[1] = GEN_INT (i ^ 0xff);
-#if defined (MOTOROLA) && !defined (CRDS)
-      return "moveq%.l %1,%0\n\tnot%.b %0";
-#else
-      return "moveq %1,%0\n\tnot%.b %0";
-#endif	 
-    case NOTW :
-      operands[1] = GEN_INT (i ^ 0xffff);
-#if defined (MOTOROLA) && !defined (CRDS)
-      return "moveq%.l %1,%0\n\tnot%.w %0";
-#else
-      return "moveq %1,%0\n\tnot%.w %0";
-#endif	 
-    case NEGW :
-#if defined (MOTOROLA) && !defined (CRDS)
-      return "moveq%.l %#-128,%0\n\tneg%.w %0";
-#else
-      return "moveq %#-128,%0\n\tneg%.w %0";
-#endif	 
-    case SWAP :
-      {
-	unsigned u = i;
-
-	operands[1] = GEN_INT ((u << 16) | (u >> 16));
-#if defined (MOTOROLA) && !defined (CRDS)
-	return "moveq%.l %1,%0\n\tswap %0";
-#else
-	return "moveq %1,%0\n\tswap %0";
-#endif	 
-      }
-    case MOVL :
-	return "move%.l %1,%0";
-    default :
-	abort ();
-    }
-}
-
-char *
-output_move_simode_const (operands)
-     rtx *operands;
-{
-  if (operands[1] == const0_rtx
-      && (DATA_REG_P (operands[0])
-	  || GET_CODE (operands[0]) == MEM)
-      /* clr insns on 68000 read before writing.
-	 This isn't so on the 68010, but we have no TARGET_68010.  */
-      && ((TARGET_68020 || TARGET_5200)
-	  || !(GET_CODE (operands[0]) == MEM
-	       && MEM_VOLATILE_P (operands[0]))))
-    return "clr%.l %0";
-  else if (operands[1] == const0_rtx
-	   && ADDRESS_REG_P (operands[0]))
-    return "sub%.l %0,%0";
-  else if (DATA_REG_P (operands[0]))
-    return output_move_const_into_data_reg (operands);
-  else if (ADDRESS_REG_P (operands[0])
-	   && INTVAL (operands[1]) < 0x8000
-	   && INTVAL (operands[1]) >= -0x8000)
-    return "move%.w %1,%0";
-  else if (GET_CODE (operands[0]) == MEM
-      && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
-      && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
-	   && INTVAL (operands[1]) < 0x8000
-	   && INTVAL (operands[1]) >= -0x8000)
-    return "pea %a1";
-  return "move%.l %1,%0";
-}
-
-char *
-output_move_simode (operands)
-     rtx *operands;
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    return output_move_simode_const (operands);
-  else if ((GET_CODE (operands[1]) == SYMBOL_REF
-	    || GET_CODE (operands[1]) == CONST)
-	   && push_operand (operands[0], SImode))
-    return "pea %a1";
-  else if ((GET_CODE (operands[1]) == SYMBOL_REF
-	    || GET_CODE (operands[1]) == CONST)
-	   && ADDRESS_REG_P (operands[0]))
-    return "lea %a1,%0";
-  return "move%.l %1,%0";
-}
-
-char *
-output_move_himode (operands)
-     rtx *operands;
-{
- if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      if (operands[1] == const0_rtx
-	  && (DATA_REG_P (operands[0])
-	      || GET_CODE (operands[0]) == MEM)
-	  /* clr insns on 68000 read before writing.
-	     This isn't so on the 68010, but we have no TARGET_68010.  */
-	  && ((TARGET_68020 || TARGET_5200)
-	      || !(GET_CODE (operands[0]) == MEM
-		   && MEM_VOLATILE_P (operands[0]))))
-	return "clr%.w %0";
-      else if (operands[1] == const0_rtx
-	       && ADDRESS_REG_P (operands[0]))
-	return "sub%.l %0,%0";
-      else if (DATA_REG_P (operands[0])
-	       && INTVAL (operands[1]) < 128
-	       && INTVAL (operands[1]) >= -128)
-	{
-#if defined(MOTOROLA) && !defined(CRDS)
-	  return "moveq%.l %1,%0";
-#else
-	  return "moveq %1,%0";
-#endif
-	}
-      else if (INTVAL (operands[1]) < 0x8000
-	       && INTVAL (operands[1]) >= -0x8000)
-	return "move%.w %1,%0";
-    }
-  else if (CONSTANT_P (operands[1]))
-    return "move%.l %1,%0";
-#ifndef SGS_NO_LI
-  /* Recognize the insn before a tablejump, one that refers
-     to a table of offsets.  Such an insn will need to refer
-     to a label on the insn.  So output one.  Use the label-number
-     of the table of offsets to generate this label.  This code,
-     and similar code below, assumes that there will be at most one
-     reference to each table.  */
-  if (GET_CODE (operands[1]) == MEM
-      && GET_CODE (XEXP (operands[1], 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
-      && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
-    {
-      rtx labelref = XEXP (XEXP (operands[1], 0), 1);
-#if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
-#ifdef SGS
-      asm_fprintf (asm_out_file, "\tset %LLI%d,.+2\n",
-		   CODE_LABEL_NUMBER (XEXP (labelref, 0)));
-#else /* not SGS */
-      asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n",
-		   CODE_LABEL_NUMBER (XEXP (labelref, 0)));
-#endif /* not SGS */
-#else /* SGS_SWITCH_TABLES or not MOTOROLA */
-      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LI",
-				 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
-#ifdef SGS_SWITCH_TABLES
-      /* Set flag saying we need to define the symbol
-	 LD%n (with value L%n-LI%n) at the end of the switch table.  */
-      switch_table_difference_label_flag = 1;
-#endif /* SGS_SWITCH_TABLES */
-#endif /* SGS_SWITCH_TABLES or not MOTOROLA */
-    }
-#endif /* SGS_NO_LI */
-  return "move%.w %1,%0";
-}
-
-char *
-output_move_qimode (operands)
-     rtx *operands;
-{
-  rtx xoperands[4];
-
-  /* This is probably useless, since it loses for pushing a struct
-     of several bytes a byte at a time.	 */
-  /* 68k family always modifies the stack pointer by at least 2, even for
-     byte pushes.  The 5200 (coldfire) does not do this.  */
-  if (GET_CODE (operands[0]) == MEM
-      && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
-      && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
-      && ! ADDRESS_REG_P (operands[1])
-      && ! TARGET_5200)
-    {
-      xoperands[1] = operands[1];
-      xoperands[2]
-	= gen_rtx_MEM (QImode,
-		       gen_rtx_PLUS (VOIDmode, stack_pointer_rtx, const1_rtx));
-      /* Just pushing a byte puts it in the high byte of the halfword.	*/
-      /* We must put it in the low-order, high-numbered byte.  */
-      if (!reg_mentioned_p (stack_pointer_rtx, operands[1]))
-	{
-	  xoperands[3] = stack_pointer_rtx;
-#ifndef NO_ADDSUB_Q
-	  output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
-#else
-	  output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
-#endif
-	}
-      else
-	output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands);
-      return "";
-    }
-
-  /* clr and st insns on 68000 read before writing.
-     This isn't so on the 68010, but we have no TARGET_68010.  */
-  if (!ADDRESS_REG_P (operands[0])
-      && ((TARGET_68020 || TARGET_5200)
-	  || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
-    {
-      if (operands[1] == const0_rtx)
-	return "clr%.b %0";
-      if ((!TARGET_5200 || DATA_REG_P (operands[0]))
-	  && GET_CODE (operands[1]) == CONST_INT
-	  && (INTVAL (operands[1]) & 255) == 255)
-	{
-	  CC_STATUS_INIT;
-	  return "st %0";
-	}
-    }
-  if (GET_CODE (operands[1]) == CONST_INT
-      && DATA_REG_P (operands[0])
-      && INTVAL (operands[1]) < 128
-      && INTVAL (operands[1]) >= -128)
-    {
-#if defined(MOTOROLA) && !defined(CRDS)
-      return "moveq%.l %1,%0";
-#else
-      return "moveq %1,%0";
-#endif
-    }
-  if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
-    return "sub%.l %0,%0";
-  if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
-    return "move%.l %1,%0";
-  /* 68k family (including the 5200 coldfire) does not support byte moves to
-     from address registers.  */
-  if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
-    return "move%.w %1,%0";
-  return "move%.b %1,%0";
-}
-
-char *
-output_move_stricthi (operands)
-     rtx *operands;
-{
-  if (operands[1] == const0_rtx
-      /* clr insns on 68000 read before writing.
-	 This isn't so on the 68010, but we have no TARGET_68010.  */
-      && ((TARGET_68020 || TARGET_5200)
-	  || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
-    return "clr%.w %0";
-  return "move%.w %1,%0";
-}
-
-char *
-output_move_strictqi (operands)
-     rtx *operands;
-{
-  if (operands[1] == const0_rtx
-      /* clr insns on 68000 read before writing.
-         This isn't so on the 68010, but we have no TARGET_68010.  */
-      && ((TARGET_68020 || TARGET_5200)
-          || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
-    return "clr%.b %0";
-  return "move%.b %1,%0";
-}
-
-/* Return the best assembler insn template
-   for moving operands[1] into operands[0] as a fullword.  */
-
-static char *
-singlemove_string (operands)
-     rtx *operands;
-{
-#ifdef SUPPORT_SUN_FPA
-  if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
-    return "fpmoves %1,%0";
-#endif
-  if (GET_CODE (operands[1]) == CONST_INT)
-    return output_move_simode_const (operands);
-  return "move%.l %1,%0";
-}
-
-
-/* Output assembler code to perform a doubleword move insn
-   with operands OPERANDS.  */
-
-char *
-output_move_double (operands)
-     rtx *operands;
-{
-  enum
-    {
-      REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
-    } optype0, optype1;
-  rtx latehalf[2];
-  rtx middlehalf[2];
-  rtx xops[2];
-  rtx addreg0 = 0, addreg1 = 0;
-  int dest_overlapped_low = 0;
-  int size = GET_MODE_SIZE (GET_MODE (operands[0]));
-
-  middlehalf[0] = 0;
-  middlehalf[1] = 0;
-
-  /* First classify both operands.  */
-
-  if (REG_P (operands[0]))
-    optype0 = REGOP;
-  else if (offsettable_memref_p (operands[0]))
-    optype0 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    optype0 = POPOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    optype0 = PUSHOP;
-  else if (GET_CODE (operands[0]) == MEM)
-    optype0 = MEMOP;
-  else
-    optype0 = RNDOP;
-
-  if (REG_P (operands[1]))
-    optype1 = REGOP;
-  else if (CONSTANT_P (operands[1]))
-    optype1 = CNSTOP;
-  else if (offsettable_memref_p (operands[1]))
-    optype1 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
-    optype1 = POPOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
-    optype1 = PUSHOP;
-  else if (GET_CODE (operands[1]) == MEM)
-    optype1 = MEMOP;
-  else
-    optype1 = RNDOP;
-
-  /* Check for the cases that the operand constraints are not
-     supposed to allow to happen.  Abort if we get one,
-     because generating code for these cases is painful.  */
-
-  if (optype0 == RNDOP || optype1 == RNDOP)
-    abort ();
-
-  /* If one operand is decrementing and one is incrementing
-     decrement the former register explicitly
-     and change that operand into ordinary indexing.  */
-
-  if (optype0 == PUSHOP && optype1 == POPOP)
-    {
-      operands[0] = XEXP (XEXP (operands[0], 0), 0);
-      if (size == 12)
-        output_asm_insn ("sub%.l %#12,%0", operands);
-      else
-        output_asm_insn ("subq%.l %#8,%0", operands);
-      if (GET_MODE (operands[1]) == XFmode)
-	operands[0] = gen_rtx_MEM (XFmode, operands[0]);
-      else if (GET_MODE (operands[0]) == DFmode)
-	operands[0] = gen_rtx_MEM (DFmode, operands[0]);
-      else
-	operands[0] = gen_rtx_MEM (DImode, operands[0]);
-      optype0 = OFFSOP;
-    }
-  if (optype0 == POPOP && optype1 == PUSHOP)
-    {
-      operands[1] = XEXP (XEXP (operands[1], 0), 0);
-      if (size == 12)
-        output_asm_insn ("sub%.l %#12,%1", operands);
-      else
-        output_asm_insn ("subq%.l %#8,%1", operands);
-      if (GET_MODE (operands[1]) == XFmode)
-	operands[1] = gen_rtx_MEM (XFmode, operands[1]);
-      else if (GET_MODE (operands[1]) == DFmode)
-	operands[1] = gen_rtx_MEM (DFmode, operands[1]);
-      else
-	operands[1] = gen_rtx_MEM (DImode, operands[1]);
-      optype1 = OFFSOP;
-    }
-
-  /* If an operand is an unoffsettable memory ref, find a register
-     we can increment temporarily to make it refer to the second word.  */
-
-  if (optype0 == MEMOP)
-    addreg0 = find_addr_reg (XEXP (operands[0], 0));
-
-  if (optype1 == MEMOP)
-    addreg1 = find_addr_reg (XEXP (operands[1], 0));
-
-  /* Ok, we can do one word at a time.
-     Normally we do the low-numbered word first,
-     but if either operand is autodecrementing then we
-     do the high-numbered word first.
-
-     In either case, set up in LATEHALF the operands to use
-     for the high-numbered word and in some cases alter the
-     operands in OPERANDS to be suitable for the low-numbered word.  */
-
-  if (size == 12)
-    {
-      if (optype0 == REGOP)
-	{
-	  latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
-	  middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-	}
-      else if (optype0 == OFFSOP)
-	{
-	  middlehalf[0] = adj_offsettable_operand (operands[0], 4);
-	  latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
-	}
-      else
-	{
-	  middlehalf[0] = operands[0];
-	  latehalf[0] = operands[0];
-	}
-
-      if (optype1 == REGOP)
-	{
-	  latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
-	  middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-	}
-      else if (optype1 == OFFSOP)
-	{
-	  middlehalf[1] = adj_offsettable_operand (operands[1], 4);
-	  latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
-	}
-      else if (optype1 == CNSTOP)
-	{
-	  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	    {
-	      REAL_VALUE_TYPE r;
-	      long l[3];
-
-	      REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
-	      REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
-	      operands[1] = GEN_INT (l[0]);
-	      middlehalf[1] = GEN_INT (l[1]);
-	      latehalf[1] = GEN_INT (l[2]);
-	    }
-	  else if (CONSTANT_P (operands[1]))
-	    {
-	      /* actually, no non-CONST_DOUBLE constant should ever
-		 appear here.  */
-	      abort ();
-	      if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
-		latehalf[1] = constm1_rtx;
-	      else
-		latehalf[1] = const0_rtx;
-	    }
-	}
-      else
-	{
-	  middlehalf[1] = operands[1];
-	  latehalf[1] = operands[1];
-	}
-    }
-  else
-    /* size is not 12: */
-    {
-      if (optype0 == REGOP)
-	latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-      else if (optype0 == OFFSOP)
-	latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
-      else
-	latehalf[0] = operands[0];
-
-      if (optype1 == REGOP)
-	latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-      else if (optype1 == OFFSOP)
-	latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
-      else if (optype1 == CNSTOP)
-	split_double (operands[1], &operands[1], &latehalf[1]);
-      else
-	latehalf[1] = operands[1];
-    }
-
-  /* If insn is effectively movd N(sp),-(sp) then we will do the
-     high word first.  We should use the adjusted operand 1 (which is N+4(sp))
-     for the low word as well, to compensate for the first decrement of sp.  */
-  if (optype0 == PUSHOP
-      && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
-      && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
-    operands[1] = middlehalf[1] = latehalf[1];
-
-  /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
-     if the upper part of reg N does not appear in the MEM, arrange to
-     emit the move late-half first.  Otherwise, compute the MEM address
-     into the upper part of N and use that as a pointer to the memory
-     operand.  */
-  if (optype0 == REGOP
-      && (optype1 == OFFSOP || optype1 == MEMOP))
-    {
-      rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
-
-      if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
-	  && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
-	{
-	  /* If both halves of dest are used in the src memory address,
-	     compute the address into latehalf of dest.
-	     Note that this can't happen if the dest is two data regs.  */
-compadr:
-	  xops[0] = latehalf[0];
-	  xops[1] = XEXP (operands[1], 0);
-	  output_asm_insn ("lea %a1,%0", xops);
-	  if( GET_MODE (operands[1]) == XFmode )
-	    {
-	      operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
-	      middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
-	      latehalf[1] = adj_offsettable_operand (operands[1], size-4);
-	    }
-	  else
-	    {
-	      operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
-	      latehalf[1] = adj_offsettable_operand (operands[1], size-4);
-	    }
-	}
-      else if (size == 12
-	       && reg_overlap_mentioned_p (middlehalf[0],
-					   XEXP (operands[1], 0)))
-	{
-	  /* Check for two regs used by both source and dest.
-	     Note that this can't happen if the dest is all data regs.
-	     It can happen if the dest is d6, d7, a0.
-	     But in that case, latehalf is an addr reg, so
-	     the code at compadr does ok.  */
-
-	  if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
-	      || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
-	    goto compadr;
-
-	  /* JRV says this can't happen: */
-	  if (addreg0 || addreg1)
-	    abort ();
-
-	  /* Only the middle reg conflicts; simply put it last. */
-	  output_asm_insn (singlemove_string (operands), operands);
-	  output_asm_insn (singlemove_string (latehalf), latehalf);
-	  output_asm_insn (singlemove_string (middlehalf), middlehalf);
-	  return "";
-	}
-      else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
-	/* If the low half of dest is mentioned in the source memory
-	   address, the arrange to emit the move late half first.  */
-	dest_overlapped_low = 1;
-    }
-
-  /* If one or both operands autodecrementing,
-     do the two words, high-numbered first.  */
-
-  /* Likewise,  the first move would clobber the source of the second one,
-     do them in the other order.  This happens only for registers;
-     such overlap can't happen in memory unless the user explicitly
-     sets it up, and that is an undefined circumstance.  */
-
-  if (optype0 == PUSHOP || optype1 == PUSHOP
-      || (optype0 == REGOP && optype1 == REGOP
-	  && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
-	      || REGNO (operands[0]) == REGNO (latehalf[1])))
-      || dest_overlapped_low)
-    {
-      /* Make any unoffsettable addresses point at high-numbered word.  */
-      if (addreg0)
-	{
-	  if (size == 12)
-	    output_asm_insn ("addq%.l %#8,%0", &addreg0);
-	  else
-	    output_asm_insn ("addq%.l %#4,%0", &addreg0);
-	}
-      if (addreg1)
-	{
-	  if (size == 12)
-	    output_asm_insn ("addq%.l %#8,%0", &addreg1);
-	  else
-	    output_asm_insn ("addq%.l %#4,%0", &addreg1);
-	}
-
-      /* Do that word.  */
-      output_asm_insn (singlemove_string (latehalf), latehalf);
-
-      /* Undo the adds we just did.  */
-      if (addreg0)
-	output_asm_insn ("subq%.l %#4,%0", &addreg0);
-      if (addreg1)
-	output_asm_insn ("subq%.l %#4,%0", &addreg1);
-
-      if (size == 12)
-	{
-	  output_asm_insn (singlemove_string (middlehalf), middlehalf);
-	  if (addreg0)
-	    output_asm_insn ("subq%.l %#4,%0", &addreg0);
-	  if (addreg1)
-	    output_asm_insn ("subq%.l %#4,%0", &addreg1);
-	}
-
-      /* Do low-numbered word.  */
-      return singlemove_string (operands);
-    }
-
-  /* Normal case: do the two words, low-numbered first.  */
-
-  output_asm_insn (singlemove_string (operands), operands);
-
-  /* Do the middle one of the three words for long double */
-  if (size == 12)
-    {
-      if (addreg0)
-	output_asm_insn ("addq%.l %#4,%0", &addreg0);
-      if (addreg1)
-	output_asm_insn ("addq%.l %#4,%0", &addreg1);
-
-      output_asm_insn (singlemove_string (middlehalf), middlehalf);
-    }
-
-  /* Make any unoffsettable addresses point at high-numbered word.  */
-  if (addreg0)
-    output_asm_insn ("addq%.l %#4,%0", &addreg0);
-  if (addreg1)
-    output_asm_insn ("addq%.l %#4,%0", &addreg1);
-
-  /* Do that word.  */
-  output_asm_insn (singlemove_string (latehalf), latehalf);
-
-  /* Undo the adds we just did.  */
-  if (addreg0)
-    {
-      if (size == 12)
-        output_asm_insn ("subq%.l %#8,%0", &addreg0);
-      else
-        output_asm_insn ("subq%.l %#4,%0", &addreg0);
-    }
-  if (addreg1)
-    {
-      if (size == 12)
-        output_asm_insn ("subq%.l %#8,%0", &addreg1);
-      else
-        output_asm_insn ("subq%.l %#4,%0", &addreg1);
-    }
-
-  return "";
-}
-
-/* Return a REG that occurs in ADDR with coefficient 1.
-   ADDR can be effectively incremented by incrementing REG.  */
-
-static rtx
-find_addr_reg (addr)
-     rtx addr;
-{
-  while (GET_CODE (addr) == PLUS)
-    {
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-	addr = XEXP (addr, 0);
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	addr = XEXP (addr, 1);
-      else if (CONSTANT_P (XEXP (addr, 0)))
-	addr = XEXP (addr, 1);
-      else if (CONSTANT_P (XEXP (addr, 1)))
-	addr = XEXP (addr, 0);
-      else
-	abort ();
-    }
-  if (GET_CODE (addr) == REG)
-    return addr;
-  abort ();
-}
-
-/* Output assembler code to perform a 32 bit 3 operand add.  */
-
-char *
-output_addsi3 (operands)
-     rtx *operands;
-{
-  if (! operands_match_p (operands[0], operands[1]))
-    {
-      if (!ADDRESS_REG_P (operands[1]))
-	{
-	  rtx tmp = operands[1];
-
-	  operands[1] = operands[2];
-	  operands[2] = tmp;
-	}
-
-      /* These insns can result from reloads to access
-	 stack slots over 64k from the frame pointer.  */
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
-        return "move%.l %2,%0\n\tadd%.l %1,%0";
-#ifdef SGS
-      if (GET_CODE (operands[2]) == REG)
-	return "lea 0(%1,%2.l),%0";
-      else
-	return "lea %c2(%1),%0";
-#else /* not SGS */
-#ifdef MOTOROLA
-      if (GET_CODE (operands[2]) == REG)
-	return "lea (%1,%2.l),%0";
-      else
-	return "lea (%c2,%1),%0";
-#else /* not MOTOROLA (MIT syntax) */
-      if (GET_CODE (operands[2]) == REG)
-	return "lea %1@(0,%2:l),%0";
-      else
-	return "lea %1@(%c2),%0";
-#endif /* not MOTOROLA */
-#endif /* not SGS */
-    }
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-#ifndef NO_ADDSUB_Q
-      if (INTVAL (operands[2]) > 0
-	  && INTVAL (operands[2]) <= 8)
-	return "addq%.l %2,%0";
-      if (INTVAL (operands[2]) < 0
-	  && INTVAL (operands[2]) >= -8)
-        {
-	  operands[2] = GEN_INT (-INTVAL (operands[2]));
-	  return "subq%.l %2,%0";
-	}
-      /* On the CPU32 it is faster to use two addql instructions to
-	 add a small integer (8 < N <= 16) to a register.
-	 Likewise for subql. */
-      if (TARGET_CPU32 && REG_P (operands[0]))
-	{
-	  if (INTVAL (operands[2]) > 8
-	      && INTVAL (operands[2]) <= 16)
-	    {
-	      operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-	      return "addq%.l %#8,%0\n\taddq%.l %2,%0";
-	    }
-	  if (INTVAL (operands[2]) < -8
-	      && INTVAL (operands[2]) >= -16)
-	    {
-	      operands[2] = GEN_INT (-INTVAL (operands[2]) - 8);
-	      return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
-	    }
-	}
-#endif
-      if (ADDRESS_REG_P (operands[0])
-	  && INTVAL (operands[2]) >= -0x8000
-	  && INTVAL (operands[2]) < 0x8000)
-	{
-	  if (TARGET_68040)
-	    return "add%.w %2,%0";
-	  else
-#ifdef MOTOROLA  
-	    return "lea (%c2,%0),%0";
-#else
-	    return "lea %0@(%c2),%0";
-#endif
-	}
-    }
-  return "add%.l %2,%0";
-}
-
-/* Store in cc_status the expressions that the condition codes will
-   describe after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-/* On the 68000, all the insns to store in an address register fail to
-   set the cc's.  However, in some cases these instructions can make it
-   possibly invalid to use the saved cc's.  In those cases we clear out
-   some or all of the saved cc's so they won't be used.  */
-
-void
-notice_update_cc (exp, insn)
-     rtx exp;
-     rtx insn;
-{
-  /* If the cc is being set from the fpa and the expression is not an
-     explicit floating point test instruction (which has code to deal with
-     this), reinit the CC.  */
-  if (((cc_status.value1 && FPA_REG_P (cc_status.value1))
-       || (cc_status.value2 && FPA_REG_P (cc_status.value2)))
-      && !(GET_CODE (exp) == PARALLEL
-	   && GET_CODE (XVECEXP (exp, 0, 0)) == SET
-	   && XEXP (XVECEXP (exp, 0, 0), 0) == cc0_rtx))
-    {
-      CC_STATUS_INIT; 
-    }
-  else if (GET_CODE (exp) == SET)
-    {
-      if (GET_CODE (SET_SRC (exp)) == CALL)
-	{
-	  CC_STATUS_INIT; 
-	}
-      else if (ADDRESS_REG_P (SET_DEST (exp)))
-	{
-	  if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
-	    cc_status.value1 = 0;
-	  if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
-	    cc_status.value2 = 0; 
-	}
-      else if (!FP_REG_P (SET_DEST (exp))
-	       && SET_DEST (exp) != cc0_rtx
-	       && (FP_REG_P (SET_SRC (exp))
-		   || GET_CODE (SET_SRC (exp)) == FIX
-		   || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE
-		   || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND))
-	{
-	  CC_STATUS_INIT; 
-	}
-      /* A pair of move insns doesn't produce a useful overall cc.  */
-      else if (!FP_REG_P (SET_DEST (exp))
-	       && !FP_REG_P (SET_SRC (exp))
-	       && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
-	       && (GET_CODE (SET_SRC (exp)) == REG
-		   || GET_CODE (SET_SRC (exp)) == MEM
-		   || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
-	{
-	  CC_STATUS_INIT; 
-	}
-      else if (GET_CODE (SET_SRC (exp)) == CALL)
-	{
-	  CC_STATUS_INIT; 
-	}
-      else if (XEXP (exp, 0) != pc_rtx)
-	{
-	  cc_status.flags = 0;
-	  cc_status.value1 = XEXP (exp, 0);
-	  cc_status.value2 = XEXP (exp, 1);
-	}
-    }
-  else if (GET_CODE (exp) == PARALLEL
-	   && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
-    {
-      if (ADDRESS_REG_P (XEXP (XVECEXP (exp, 0, 0), 0)))
-	CC_STATUS_INIT;
-      else if (XEXP (XVECEXP (exp, 0, 0), 0) != pc_rtx)
-	{
-	  cc_status.flags = 0;
-	  cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
-	  cc_status.value2 = XEXP (XVECEXP (exp, 0, 0), 1);
-	}
-    }
-  else
-    CC_STATUS_INIT;
-  if (cc_status.value2 != 0
-      && ADDRESS_REG_P (cc_status.value2)
-      && GET_MODE (cc_status.value2) == QImode)
-    CC_STATUS_INIT;
-  if (cc_status.value2 != 0
-      && !(cc_status.value1 && FPA_REG_P (cc_status.value1)))
-    switch (GET_CODE (cc_status.value2))
-      {
-      case PLUS: case MINUS: case MULT:
-      case DIV: case UDIV: case MOD: case UMOD: case NEG:
-#if 0 /* These instructions always clear the overflow bit */
-      case ASHIFT: case ASHIFTRT: case LSHIFTRT:
-      case ROTATE: case ROTATERT:
-#endif
-	if (GET_MODE (cc_status.value2) != VOIDmode)
-	  cc_status.flags |= CC_NO_OVERFLOW;
-	break;
-      case ZERO_EXTEND:
-	/* (SET r1 (ZERO_EXTEND r2)) on this machine
-	   ends with a move insn moving r2 in r2's mode.
-	   Thus, the cc's are set for r2.
-	   This can set N bit spuriously. */
-	cc_status.flags |= CC_NOT_NEGATIVE; 
-
-      default:
-	break;
-      }
-  if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
-      && cc_status.value2
-      && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
-    cc_status.value2 = 0;
-  if (((cc_status.value1 && FP_REG_P (cc_status.value1))
-       || (cc_status.value2 && FP_REG_P (cc_status.value2)))
-      && !((cc_status.value1 && FPA_REG_P (cc_status.value1))
-	   || (cc_status.value2 && FPA_REG_P (cc_status.value2))))
-    cc_status.flags = CC_IN_68881;
-}
-
-char *
-output_move_const_double (operands)
-     rtx *operands;
-{
-#ifdef SUPPORT_SUN_FPA
-  if (TARGET_FPA && FPA_REG_P (operands[0]))
-    {
-      int code = standard_sun_fpa_constant_p (operands[1]);
-
-      if (code != 0)
-	{
-	  static char buf[40];
-
-	  sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff);
-	  return buf;
-	}
-      return "fpmove%.d %1,%0";
-    }
-  else
-#endif
-    {
-      int code = standard_68881_constant_p (operands[1]);
-
-      if (code != 0)
-	{
-	  static char buf[40];
-
-	  sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
-	  return buf;
-	}
-      return "fmove%.d %1,%0";
-    }
-}
-
-char *
-output_move_const_single (operands)
-     rtx *operands;
-{
-#ifdef SUPPORT_SUN_FPA
-  if (TARGET_FPA)
-    {
-      int code = standard_sun_fpa_constant_p (operands[1]);
-
-      if (code != 0)
-	{
-	  static char buf[40];
-
-	  sprintf (buf, "fpmove%%.s %%%%%d,%%0", code & 0x1ff);
-	  return buf;
-	}
-      return "fpmove%.s %1,%0";
-    }
-  else
-#endif /* defined SUPPORT_SUN_FPA */
-    {
-      int code = standard_68881_constant_p (operands[1]);
-
-      if (code != 0)
-	{
-	  static char buf[40];
-
-	  sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
-	  return buf;
-	}
-      return "fmove%.s %f1,%0";
-    }
-}
-
-/* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
-   from the "fmovecr" instruction.
-   The value, anded with 0xff, gives the code to use in fmovecr
-   to get the desired constant.  */
-
-/* This code has been fixed for cross-compilation. */
-  
-static int inited_68881_table = 0;
-
-char *strings_68881[7] = {
-  "0.0",
-  "1.0",
-  "10.0",
-  "100.0",
-  "10000.0",
-  "1e8",
-  "1e16"
-  };
-
-int codes_68881[7] = {
-  0x0f,
-  0x32,
-  0x33,
-  0x34,
-  0x35,
-  0x36,
-  0x37
-  };
-
-REAL_VALUE_TYPE values_68881[7];
-
-/* Set up values_68881 array by converting the decimal values
-   strings_68881 to binary.   */
-
-void
-init_68881_table ()
-{
-  int i;
-  REAL_VALUE_TYPE r;
-  enum machine_mode mode;
-
-  mode = SFmode;
-  for (i = 0; i < 7; i++)
-    {
-      if (i == 6)
-        mode = DFmode;
-      r = REAL_VALUE_ATOF (strings_68881[i], mode);
-      values_68881[i] = r;
-    }
-  inited_68881_table = 1;
-}
-
-int
-standard_68881_constant_p (x)
-     rtx x;
-{
-  REAL_VALUE_TYPE r;
-  int i;
-
-#ifdef NO_ASM_FMOVECR
-  return 0;
-#endif
-
-  /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
-     used at all on those chips. */
-  if (TARGET_68040 || TARGET_68060)
-    return 0;
-
-#ifndef REAL_ARITHMETIC
-#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
-  if (! flag_pretend_float)
-    return 0;
-#endif
-#endif
-
-  if (! inited_68881_table)
-    init_68881_table ();
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, x);
-
-  for (i = 0; i < 6; i++)
-    {
-      if (REAL_VALUES_EQUAL (r, values_68881[i]))
-        return (codes_68881[i]);
-    }
-  
-  if (GET_MODE (x) == SFmode)
-    return 0;
-
-  if (REAL_VALUES_EQUAL (r, values_68881[6]))
-    return (codes_68881[6]);
-
-  /* larger powers of ten in the constants ram are not used
-     because they are not equal to a `double' C constant.  */
-  return 0;
-}
-
-/* If X is a floating-point constant, return the logarithm of X base 2,
-   or 0 if X is not a power of 2.  */
-
-int
-floating_exact_log2 (x)
-     rtx x;
-{
-  REAL_VALUE_TYPE r, r1;
-  int i;
-
-#ifndef REAL_ARITHMETIC
-#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
-  if (! flag_pretend_float)
-    return 0;
-#endif
-#endif
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, x);
-
-  if (REAL_VALUES_LESS (r, dconst0))
-    return 0;
-
-  r1 = dconst1;
-  i = 0;
-  while (REAL_VALUES_LESS (r1, r))
-    {
-      r1 = REAL_VALUE_LDEXP (dconst1, i);
-      if (REAL_VALUES_EQUAL (r1, r))
-        return i;
-      i = i + 1;
-    }
-  return 0;
-}
-
-#ifdef SUPPORT_SUN_FPA
-/* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
-   from the Sun FPA's constant RAM.
-   The value returned, anded with 0x1ff, gives the code to use in fpmove
-   to get the desired constant. */
-
-static int inited_FPA_table = 0;
-
-char *strings_FPA[38] = {
-/* small rationals */
-  "0.0",
-  "1.0",
-  "0.5",
-  "-1.0",
-  "2.0",
-  "3.0",
-  "4.0",
-  "8.0",
-  "0.25",
-  "0.125",
-  "10.0",
-  "-0.5",
-/* Decimal equivalents of double precision values */
-  "2.718281828459045091", /* D_E */
-  "6.283185307179586477", /* 2 pi */
-  "3.141592653589793116", /* D_PI */
-  "1.570796326794896619", /* pi/2 */
-  "1.414213562373095145", /* D_SQRT2 */
-  "0.7071067811865475244", /* 1/sqrt(2) */
-  "-1.570796326794896619", /* -pi/2 */
-  "1.442695040888963387", /* D_LOG2ofE */
-  "3.321928024887362182", /* D_LOG2of10 */
-  "0.6931471805599452862", /* D_LOGEof2 */
-  "2.302585092994045901", /* D_LOGEof10 */
-  "0.3010299956639811980", /* D_LOG10of2 */
-  "0.4342944819032518167", /* D_LOG10ofE */
-/* Decimal equivalents of single precision values */
-  "2.718281745910644531", /* S_E */
-  "6.283185307179586477", /* 2 pi */
-  "3.141592741012573242", /* S_PI */
-  "1.570796326794896619", /* pi/2 */
-  "1.414213538169860840", /* S_SQRT2 */
-  "0.7071067811865475244", /* 1/sqrt(2) */
-  "-1.570796326794896619", /* -pi/2 */
-  "1.442695021629333496", /* S_LOG2ofE */
-  "3.321928024291992188", /* S_LOG2of10 */
-  "0.6931471824645996094", /* S_LOGEof2 */
-  "2.302585124969482442", /* S_LOGEof10 */
-  "0.3010300099849700928", /* S_LOG10of2 */
-  "0.4342944920063018799", /* S_LOG10ofE */
-};
-
-
-int codes_FPA[38] = {
-/* small rationals */
-  0x200,
-  0xe,
-  0xf,
-  0x10,
-  0x11,
-  0xb1,
-  0x12,
-  0x13,
-  0x15,
-  0x16,
-  0x17,
-  0x2e,
-/* double precision */
-  0x8,
-  0x9,
-  0xa,
-  0xb,
-  0xc,
-  0xd,
-  0x27,
-  0x28,
-  0x29,
-  0x2a,
-  0x2b,
-  0x2c,
-  0x2d,
-/* single precision */
-  0x8,
-  0x9,
-  0xa,
-  0xb,
-  0xc,
-  0xd,
-  0x27,
-  0x28,
-  0x29,
-  0x2a,
-  0x2b,
-  0x2c,
-  0x2d
-  };
-
-REAL_VALUE_TYPE values_FPA[38];
-
-/* This code has been fixed for cross-compilation. */
-
-void
-init_FPA_table ()
-{
-  enum machine_mode mode;
-  int i;
-  REAL_VALUE_TYPE r;
-
-  mode = DFmode;
-  for (i = 0; i < 38; i++)
-    {
-      if (i == 25)
-        mode = SFmode;
-      r = REAL_VALUE_ATOF (strings_FPA[i], mode);
-      values_FPA[i] = r;
-    }
-  inited_FPA_table = 1;
-}
-
-
-int
-standard_sun_fpa_constant_p (x)
-     rtx x;
-{
-  REAL_VALUE_TYPE r;
-  int i;
-
-#ifndef REAL_ARITHMETIC
-#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
-  if (! flag_pretend_float)
-    return 0;
-#endif
-#endif
-
-  if (! inited_FPA_table)
-    init_FPA_table ();
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, x);
-
-  for (i=0; i<12; i++)
-    {
-      if (REAL_VALUES_EQUAL (r, values_FPA[i]))
-        return (codes_FPA[i]);
-    }
-
-  if (GET_MODE (x) == SFmode)
-    {
-      for (i=25; i<38; i++)
-        {
-          if (REAL_VALUES_EQUAL (r, values_FPA[i]))
-            return (codes_FPA[i]);
-        }
-    }
-  else
-    {
-      for (i=12; i<25; i++)
-        {
-          if (REAL_VALUES_EQUAL (r, values_FPA[i]))
-            return (codes_FPA[i]);
-        }
-    }
-  return 0x0;
-}
-#endif /* define SUPPORT_SUN_FPA */
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand X.  X is an RTL
-   expression.
-
-   CODE is a value that can be used to specify one of several ways
-   of printing the operand.  It is used when identical operands
-   must be printed differently depending on the context.  CODE
-   comes from the `%' specification that was used to request
-   printing of the operand.  If the specification was just `%DIGIT'
-   then CODE is 0; if the specification was `%LTR DIGIT' then CODE
-   is the ASCII code for LTR.
-
-   If X is a register, this macro should print the register's name.
-   The names can be found in an array `reg_names' whose type is
-   `char *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
-
-   When the machine description has a specification `%PUNCT' (a `%'
-   followed by a punctuation character), this macro is called with
-   a null pointer for X and the punctuation character for CODE.
-
-   The m68k specific codes are:
-
-   '.' for dot needed in Motorola-style opcode names.
-   '-' for an operand pushing on the stack:
-       sp@-, -(sp) or -(%sp) depending on the style of syntax.
-   '+' for an operand pushing on the stack:
-       sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
-   '@' for a reference to the top word on the stack:
-       sp@, (sp) or (%sp) depending on the style of syntax.
-   '#' for an immediate operand prefix (# in MIT and Motorola syntax
-       but & in SGS syntax, $ in CRDS/UNOS syntax).
-   '!' for the cc register (used in an `and to cc' insn).
-   '$' for the letter `s' in an op code, but only on the 68040.
-   '&' for the letter `d' in an op code, but only on the 68040.
-   '/' for register prefix needed by longlong.h.
-
-   'b' for byte insn (no effect, on the Sun; this is for the ISI).
-   'd' to force memory addressing to be absolute, not relative.
-   'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
-   'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
-       than directly).  Second part of 'y' below.
-   'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
-       or print pair of registers as rx:ry.
-   'y' for a FPA insn (print pair of registers as rx:ry).  This also outputs
-       CONST_DOUBLE's as SunFPA constant RAM registers if
-       possible, so it should not be used except for the SunFPA.
-
-   */
-
-void
-print_operand (file, op, letter)
-     FILE *file;		/* file to write to */
-     rtx op;			/* operand to print */
-     int letter;		/* %<letter> or 0 */
-{
-#ifdef SUPPORT_SUN_FPA
-  int i;
-#endif
-
-  if (letter == '.')
-    {
-#if defined (MOTOROLA) && !defined (CRDS)
-      asm_fprintf (file, ".");
-#endif
-    }
-  else if (letter == '#')
-    {
-      asm_fprintf (file, "%0I");
-    }
-  else if (letter == '-')
-    {
-#ifdef MOTOROLA
-      asm_fprintf (file, "-(%Rsp)");
-#else
-      asm_fprintf (file, "%Rsp@-");
-#endif
-    }
-  else if (letter == '+')
-    {
-#ifdef MOTOROLA
-      asm_fprintf (file, "(%Rsp)+");
-#else
-      asm_fprintf (file, "%Rsp@+");
-#endif
-    }
-  else if (letter == '@')
-    {
-#ifdef MOTOROLA
-      asm_fprintf (file, "(%Rsp)");
-#else
-      asm_fprintf (file, "%Rsp@");
-#endif
-    }
-  else if (letter == '!')
-    {
-      asm_fprintf (file, "%Rfpcr");
-    }
-  else if (letter == '$')
-    {
-      if (TARGET_68040_ONLY)
-	{
-	  fprintf (file, "s");
-	}
-    }
-  else if (letter == '&')
-    {
-      if (TARGET_68040_ONLY)
-	{
-	  fprintf (file, "d");
-	}
-    }
-  else if (letter == '/')
-    {
-      asm_fprintf (file, "%R");
-    }
-  else if (GET_CODE (op) == REG)
-    {
-#ifdef SUPPORT_SUN_FPA
-      if (REGNO (op) < 16
-	  && (letter == 'y' || letter == 'x')
-	  && GET_MODE (op) == DFmode)
-	{
-	  fprintf (file, "%s:%s", reg_names[REGNO (op)],
-		   reg_names[REGNO (op)+1]);
-	}
-      else
-#endif
-	{
-	  if (letter == 'R')
-	    /* Print out the second register name of a register pair.
-	       I.e., R (6) => 7.  */
-	    fputs (reg_names[REGNO (op) + 1], file);
-	  else
-	    fputs (reg_names[REGNO (op)], file);
-	}
-    }
-  else if (GET_CODE (op) == MEM)
-    {
-      output_address (XEXP (op, 0));
-      if (letter == 'd' && ! TARGET_68020
-	  && CONSTANT_ADDRESS_P (XEXP (op, 0))
-	  && !(GET_CODE (XEXP (op, 0)) == CONST_INT
-	       && INTVAL (XEXP (op, 0)) < 0x8000
-	       && INTVAL (XEXP (op, 0)) >= -0x8000))
-	{
-#ifdef MOTOROLA
-	  fprintf (file, ".l");
-#else
-	  fprintf (file, ":l");
-#endif
-	}
-    }
-#ifdef SUPPORT_SUN_FPA
-  else if ((letter == 'y' || letter == 'w')
-	   && GET_CODE (op) == CONST_DOUBLE
-	   && (i = standard_sun_fpa_constant_p (op)))
-    {
-      fprintf (file, "%%%d", i & 0x1ff);
-    }
-#endif
-  else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
-    {
-      REAL_VALUE_TYPE r;
-      REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-      ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
-    }
-  else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
-    {
-      REAL_VALUE_TYPE r;
-      REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-      ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
-    }
-  else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
-    {
-      REAL_VALUE_TYPE r;
-      REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-      ASM_OUTPUT_DOUBLE_OPERAND (file, r);
-    }
-  else
-    {
-      asm_fprintf (file, "%0I"); output_addr_const (file, op);
-    }
-}
-
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand that is a memory
-   reference whose address is ADDR.  ADDR is an RTL expression.
-
-   Note that this contains a kludge that knows that the only reason
-   we have an address (plus (label_ref...) (reg...)) when not generating
-   PIC code is in the insn before a tablejump, and we know that m68k.md
-   generates a label LInnn: on such an insn.
-
-   It is possible for PIC to generate a (plus (label_ref...) (reg...))
-   and we handle that just like we would a (plus (symbol_ref...) (reg...)).
-
-   Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
-   fails to assemble.  Luckily "Lnnn(pc,d0.l*2)" produces the results
-   we want.  This difference can be accommodated by using an assembler
-   define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
-   string, as necessary.  This is accomplished via the ASM_OUTPUT_CASE_END
-   macro.  See m68k/sgs.h for an example; for versions without the bug.
-   Some assemblers refuse all the above solutions.  The workaround is to
-   emit "K(pc,d0.l*2)" with K being a small constant known to give the
-   right behaviour.
-
-   They also do not like things like "pea 1.w", so we simple leave off
-   the .w on small constants. 
-
-   This routine is responsible for distinguishing between -fpic and -fPIC 
-   style relocations in an address.  When generating -fpic code the
-   offset is output in word mode (eg movel a5@(_foo:w), a0).  When generating
-   -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
-
-#ifndef ASM_OUTPUT_CASE_FETCH
-#ifdef MOTOROLA
-#ifdef SGS
-#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
-	asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
-#else
-#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
-	asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
-#endif
-#else
-#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
-	asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
-#endif
-#endif /* ASM_OUTPUT_CASE_FETCH */
-
-void
-print_operand_address (file, addr)
-     FILE *file;
-     rtx addr;
-{
-  register rtx reg1, reg2, breg, ireg;
-  rtx offset;
-
-  switch (GET_CODE (addr))
-    {
-      case REG:
-#ifdef MOTOROLA
-	fprintf (file, "(%s)", reg_names[REGNO (addr)]);
-#else
-	fprintf (file, "%s@", reg_names[REGNO (addr)]);
-#endif
-	break;
-      case PRE_DEC:
-#ifdef MOTOROLA
-	fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
-#else
-	fprintf (file, "%s@-", reg_names[REGNO (XEXP (addr, 0))]);
-#endif
-	break;
-      case POST_INC:
-#ifdef MOTOROLA
-	fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
-#else
-	fprintf (file, "%s@+", reg_names[REGNO (XEXP (addr, 0))]);
-#endif
-	break;
-      case PLUS:
-	reg1 = reg2 = ireg = breg = offset = 0;
-	if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
-	  {
-	    offset = XEXP (addr, 0);
-	    addr = XEXP (addr, 1);
-	  }
-	else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
-	  {
-	    offset = XEXP (addr, 1);
-	    addr = XEXP (addr, 0);
-	  }
-	if (GET_CODE (addr) != PLUS)
-	  {
-	    ;
-	  }
-	else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)
-	  {
-	    reg1 = XEXP (addr, 0);
-	    addr = XEXP (addr, 1);
-	  }
-	else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)
-	  {
-	    reg1 = XEXP (addr, 1);
-	    addr = XEXP (addr, 0);
-	  }
-	else if (GET_CODE (XEXP (addr, 0)) == MULT)
-	  {
-	    reg1 = XEXP (addr, 0);
-	    addr = XEXP (addr, 1);
-	  }
-	else if (GET_CODE (XEXP (addr, 1)) == MULT)
-	  {
-	    reg1 = XEXP (addr, 1);
-	    addr = XEXP (addr, 0);
-	  }
-	else if (GET_CODE (XEXP (addr, 0)) == REG)
-	  {
-	    reg1 = XEXP (addr, 0);
-	    addr = XEXP (addr, 1);
-	  }
-	else if (GET_CODE (XEXP (addr, 1)) == REG)
-	  {
-	    reg1 = XEXP (addr, 1);
-	    addr = XEXP (addr, 0);
-	  }
-	if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT
-	    || GET_CODE (addr) == SIGN_EXTEND)
-	  {
-	    if (reg1 == 0)
-	      {
-		reg1 = addr;
-	      }
-	    else
-	      {
-		reg2 = addr;
-	      }
-	    addr = 0;
-	  }
-#if 0	/* for OLD_INDEXING */
-	else if (GET_CODE (addr) == PLUS)
-	  {
-	    if (GET_CODE (XEXP (addr, 0)) == REG)
-	      {
-		reg2 = XEXP (addr, 0);
-		addr = XEXP (addr, 1);
-	      }
-	    else if (GET_CODE (XEXP (addr, 1)) == REG)
-	      {
-		reg2 = XEXP (addr, 1);
-		addr = XEXP (addr, 0);
-	      }
-	  }
-#endif
-	if (offset != 0)
-	  {
-	    if (addr != 0)
-	      {
-		abort ();
-	      }
-	    addr = offset;
-	  }
-	if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND
-		      || GET_CODE (reg1) == MULT))
-	    || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
-	  {
-	    breg = reg2;
-	    ireg = reg1;
-	  }
-	else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
-	  {
-	    breg = reg1;
-	    ireg = reg2;
-	  }
-	if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF
-	    && ! (flag_pic && ireg == pic_offset_table_rtx))
-	  {
-	    int scale = 1;
-	    if (GET_CODE (ireg) == MULT)
-	      {
-		scale = INTVAL (XEXP (ireg, 1));
-		ireg = XEXP (ireg, 0);
-	      }
-	    if (GET_CODE (ireg) == SIGN_EXTEND)
-	      {
-		ASM_OUTPUT_CASE_FETCH (file,
-			     CODE_LABEL_NUMBER (XEXP (addr, 0)),
-			     reg_names[REGNO (XEXP (ireg, 0))]);
-		fprintf (file, "w");
-	      }
-	    else
-	      {
-		ASM_OUTPUT_CASE_FETCH (file,
-			     CODE_LABEL_NUMBER (XEXP (addr, 0)),
-			     reg_names[REGNO (ireg)]);
-		fprintf (file, "l");
-	      }
-	    if (scale != 1)
-	      {
-#ifdef MOTOROLA
-		fprintf (file, "*%d", scale);
-#else
-		fprintf (file, ":%d", scale);
-#endif
-	      }
-	    putc (')', file);
-	    break;
-	  }
-	if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF
-	    && ! (flag_pic && breg == pic_offset_table_rtx))
-	  {
-	    ASM_OUTPUT_CASE_FETCH (file,
-			 CODE_LABEL_NUMBER (XEXP (addr, 0)),
-			 reg_names[REGNO (breg)]);
-	    fprintf (file, "l)");
-	    break;
-	  }
-	if (ireg != 0 || breg != 0)
-	  {
-	    int scale = 1;
-	    if (breg == 0)
-	      {
-		abort ();
-	      }
-	    if (! flag_pic && addr && GET_CODE (addr) == LABEL_REF)
-	      {
-		abort ();
-	      }
-#ifdef MOTOROLA
-	    if (addr != 0)
-	      {
-		output_addr_const (file, addr);
-	        if (flag_pic && (breg == pic_offset_table_rtx))
-		  {
-		    fprintf (file, "@GOT");
-		    if (flag_pic == 1)
-		      fprintf (file, ".w");
-		  }
-	      }
-	    fprintf (file, "(%s", reg_names[REGNO (breg)]);
-	    if (ireg != 0)
-	      {
-		putc (',', file);
-	      }
-#else
-	    fprintf (file, "%s@(", reg_names[REGNO (breg)]);
-	    if (addr != 0)
-	      {
-		output_addr_const (file, addr);
-	        if ((flag_pic == 1) && (breg == pic_offset_table_rtx))
-	          fprintf (file, ":w");
-	        if ((flag_pic == 2) && (breg == pic_offset_table_rtx))
-	          fprintf (file, ":l");
-	      }
-	    if (addr != 0 && ireg != 0)
-	      {
-		putc (',', file);
-	      }
-#endif
-	    if (ireg != 0 && GET_CODE (ireg) == MULT)
-	      {
-		scale = INTVAL (XEXP (ireg, 1));
-		ireg = XEXP (ireg, 0);
-	      }
-	    if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)
-	      {
-#ifdef MOTOROLA
-		fprintf (file, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);
-#else
-		fprintf (file, "%s:w", reg_names[REGNO (XEXP (ireg, 0))]);
-#endif
-	      }
-	    else if (ireg != 0)
-	      {
-#ifdef MOTOROLA
-		fprintf (file, "%s.l", reg_names[REGNO (ireg)]);
-#else
-		fprintf (file, "%s:l", reg_names[REGNO (ireg)]);
-#endif
-	      }
-	    if (scale != 1)
-	      {
-#ifdef MOTOROLA
-		fprintf (file, "*%d", scale);
-#else
-		fprintf (file, ":%d", scale);
-#endif
-	      }
-	    putc (')', file);
-	    break;
-	  }
-	else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF
-		 && ! (flag_pic && reg1 == pic_offset_table_rtx))	
-	  {
-	    ASM_OUTPUT_CASE_FETCH (file,
-			 CODE_LABEL_NUMBER (XEXP (addr, 0)),
-			 reg_names[REGNO (reg1)]);
-	    fprintf (file, "l)");
-	    break;
-	  }
-	/* FALL-THROUGH (is this really what we want? */
-      default:
-        if (GET_CODE (addr) == CONST_INT
-	    && INTVAL (addr) < 0x8000
-	    && INTVAL (addr) >= -0x8000)
-	  {
-#ifdef MOTOROLA
-#ifdef SGS
-	    /* Many SGS assemblers croak on size specifiers for constants. */
-	    fprintf (file, "%d", INTVAL (addr));
-#else
-	    fprintf (file, "%d.w", INTVAL (addr));
-#endif
-#else
-	    fprintf (file, "%d:w", INTVAL (addr));
-#endif
-	  }
-	else
-	  {
-	    output_addr_const (file, addr);
-	  }
-	break;
-    }
-}
-
-/* Check for cases where a clr insns can be omitted from code using
-   strict_low_part sets.  For example, the second clrl here is not needed:
-   clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
-
-   MODE is the mode of this STRICT_LOW_PART set.  FIRST_INSN is the clear
-   insn we are checking for redundancy.  TARGET is the register set by the
-   clear insn.  */
-
-int
-strict_low_part_peephole_ok (mode, first_insn, target)
-     enum machine_mode mode;
-     rtx first_insn;
-     rtx target;
-{
-  rtx p;
-
-  p = prev_nonnote_insn (first_insn);
-
-  while (p)
-    {
-      /* If it isn't an insn, then give up.  */
-      if (GET_CODE (p) != INSN)
-	return 0;
-
-      if (reg_set_p (target, p))
-	{
-	  rtx set = single_set (p);
-	  rtx dest;
-
-	  /* If it isn't an easy to recognize insn, then give up.  */
-	  if (! set)
-	    return 0;
-
-	  dest = SET_DEST (set);
-
-	  /* If this sets the entire target register to zero, then our
-	     first_insn is redundant.  */
-	  if (rtx_equal_p (dest, target)
-	      && SET_SRC (set) == const0_rtx)
-	    return 1;
-	  else if (GET_CODE (dest) == STRICT_LOW_PART
-		   && GET_CODE (XEXP (dest, 0)) == REG
-		   && REGNO (XEXP (dest, 0)) == REGNO (target)
-		   && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
-		       <= GET_MODE_SIZE (mode)))
-	    /* This is a strict low part set which modifies less than
-	       we are using, so it is safe.  */
-	    ;
-	  else
-	    return 0;
-	}
-
-      p = prev_nonnote_insn (p);
-
-    }
-
-  return 0;
-}
-
-/* Accept integer operands in the range 0..0xffffffff.  We have to check the
-   range carefully since this predicate is used in DImode contexts.  Also, we
-   need some extra crud to make it work when hosted on 64-bit machines.  */
-
-int
-const_uint32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-#if HOST_BITS_PER_WIDE_INT > 32
-  /* All allowed constants will fit a CONST_INT.  */
-  return (GET_CODE (op) == CONST_INT
-	  && (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
-#else
-  return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0)
-	  || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
-#endif
-}
-
-/* Accept integer operands in the range -0x80000000..0x7fffffff.  We have
-   to check the range carefully since this predicate is used in DImode
-   contexts.  */
-
-int
-const_sint32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  /* All allowed constants will fit a CONST_INT.  */
-  return (GET_CODE (op) == CONST_INT
-	  && (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
-}
-
-char *
-output_andsi3 (operands)
-     rtx *operands;
-{
-  int logval;
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
-      && (DATA_REG_P (operands[0])
-	  || offsettable_memref_p (operands[0]))
-      && !TARGET_5200)
-    {
-      if (GET_CODE (operands[0]) != REG)
-        operands[0] = adj_offsettable_operand (operands[0], 2);
-      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
-      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
-      CC_STATUS_INIT;
-      if (operands[2] == const0_rtx)
-        return "clr%.w %0";
-      return "and%.w %2,%0";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
-      && (DATA_REG_P (operands[0])
-          || offsettable_memref_p (operands[0])))
-    {
-      if (DATA_REG_P (operands[0]))
-        {
-          operands[1] = GEN_INT (logval);
-        }
-      else
-        {
-	  operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
-	  operands[1] = GEN_INT (logval % 8);
-        }
-      /* This does not set condition codes in a standard way.  */
-      CC_STATUS_INIT;
-      return "bclr %1,%0";
-    }
-  return "and%.l %2,%0";
-}
-
-char *
-output_iorsi3 (operands)
-     rtx *operands;
-{
-  register int logval;
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) >> 16 == 0
-      && (DATA_REG_P (operands[0])
-	  || offsettable_memref_p (operands[0]))
-      && !TARGET_5200)
-    {
-      if (GET_CODE (operands[0]) != REG)
-        operands[0] = adj_offsettable_operand (operands[0], 2);
-      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
-      CC_STATUS_INIT;
-      if (INTVAL (operands[2]) == 0xffff)
-	return "mov%.w %2,%0";
-      return "or%.w %2,%0";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
-      && (DATA_REG_P (operands[0])
-	  || offsettable_memref_p (operands[0])))
-    {
-      if (DATA_REG_P (operands[0]))
-	{
-	  operands[1] = GEN_INT (logval);
-	}
-      else
-        {
-	  operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
-	  operands[1] = GEN_INT (logval % 8);
-	}
-      CC_STATUS_INIT;
-      return "bset %1,%0";
-    }
-  return "or%.l %2,%0";
-}
-
-char *
-output_xorsi3 (operands)
-     rtx *operands;
-{
-  register int logval;
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) >> 16 == 0
-      && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
-      && !TARGET_5200)
-    {
-      if (! DATA_REG_P (operands[0]))
-	operands[0] = adj_offsettable_operand (operands[0], 2);
-      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
-      CC_STATUS_INIT;
-      if (INTVAL (operands[2]) == 0xffff)
-	return "not%.w %0";
-      return "eor%.w %2,%0";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
-      && (DATA_REG_P (operands[0])
-	  || offsettable_memref_p (operands[0])))
-    {
-      if (DATA_REG_P (operands[0]))
-	{
-	  operands[1] = GEN_INT (logval);
-	}
-      else
-        {
-	  operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
-	  operands[1] = GEN_INT (logval % 8);
-	}
-      CC_STATUS_INIT;
-      return "bchg %1,%0";
-    }
-  return "eor%.l %2,%0";
-}
diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h
deleted file mode 100755
index 4531908..0000000
--- a/gcc/config/m68k/m68k.h
+++ /dev/null
@@ -1,2139 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Sun 68000/68020 version.
-   Copyright (C) 1987, 88, 93-98, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Note that some other tm.h files include this one and then override
-   many of the definitions that relate to assembler syntax.  */
-
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-/* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES.  */
-
-/* Print subsidiary information on the compiler version in use.  */
-#ifdef MOTOROLA
-#define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
-#else
-#define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
-#endif
-
-/* Define SUPPORT_SUN_FPA to include support for generating code for
-   the Sun Floating Point Accelerator, an optional product for Sun 3
-   machines.  By default, it is not defined.  Avoid defining it unless
-   you need to output code for the Sun3+FPA architecture, as it has the
-   effect of slowing down the register set operations in hard-reg-set.h
-   (total number of registers will exceed number of bits in a long,
-   if defined, causing the set operations to expand to loops).
-   SUPPORT_SUN_FPA is typically defined in sun3.h.  */
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Compile for a 68020 (not a 68000 or 68010).  */
-#define MASK_68020	1
-#define TARGET_68020 (target_flags & MASK_68020)
-
-/* Compile 68881 insns for floating point (not library calls).  */
-#define MASK_68881	2
-#define TARGET_68881 (target_flags & MASK_68881)
-
-/* Compile using 68020 bitfield insns.  */
-#define MASK_BITFIELD	4
-#define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
-
-/* Compile using rtd insn calling sequence.
-   This will not work unless you use prototypes at least
-   for all functions that can take varying numbers of args.  */
-#define MASK_RTD	8
-#define TARGET_RTD (target_flags & MASK_RTD)
-
-/* Compile passing first two args in regs 0 and 1.
-   This exists only to test compiler features that will
-   be needed for RISC chips.  It is not usable
-   and is not intended to be usable on this cpu.  */
-#define MASK_REGPARM	16
-#define TARGET_REGPARM (target_flags & MASK_REGPARM)
-
-/* Compile with 16-bit `int'.  */
-#define MASK_SHORT	32
-#define TARGET_SHORT (target_flags & MASK_SHORT)
-
-/* Compile with special insns for Sun FPA.  */
-#define MASK_FPA	64
-#define TARGET_FPA (target_flags & MASK_FPA)
-
-/* Compile (actually, link) for Sun SKY board.  */
-#define MASK_SKY	128
-#define TARGET_SKY (target_flags & MASK_SKY)
-
-/* Optimize for 68040, but still allow execution on 68020
-   (-m68020-40 or -m68040).
-   The 68040 will execute all 68030 and 68881/2 instructions, but some
-   of them must be emulated in software by the OS.  When TARGET_68040 is
-   turned on, these instructions won't be used.  This code will still
-   run on a 68030 and 68881/2. */
-#define MASK_68040	256
-#define TARGET_68040 (target_flags & MASK_68040)
-
-/* Use the 68040-only fp instructions (-m68040 or -m68060).  */
-#define MASK_68040_ONLY	512
-#define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
-
-/* Optimize for 68060, but still allow execution on 68020
-   (-m68020-60 or -m68060).
-   The 68060 will execute all 68030 and 68881/2 instructions, but some
-   of them must be emulated in software by the OS.  When TARGET_68060 is
-   turned on, these instructions won't be used.  This code will still
-   run on a 68030 and 68881/2. */
-#define MASK_68060	1024
-#define TARGET_68060 (target_flags & MASK_68060)
-
-/* Compile for mcf5200 */
-#define MASK_5200	2048
-#define TARGET_5200 (target_flags & MASK_5200)
-
-/* Align ints to a word boundary.  This breaks compatibility with the 
-   published ABI's for structures containing ints, but produces faster
-   code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
-   It's required for coldfire cpus without a misalignment module.  */
-#define MASK_ALIGN_INT	4096
-#define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
-
-/* Compile for a CPU32 */
-	/* A 68020 without bitfields is a good heuristic for a CPU32 */
-#define TARGET_CPU32	(TARGET_68020 && !TARGET_BITFIELD)
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)},	\
-    { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)},	\
-    { "68020", (MASK_68020|MASK_BITFIELD)},				\
-    { "c68020", (MASK_68020|MASK_BITFIELD)},				\
-    { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY	\
-		|MASK_68020|MASK_BITFIELD|MASK_68881)},			\
-    { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY	\
-		|MASK_68020|MASK_BITFIELD|MASK_68881)},			\
-    { "bitfield", MASK_BITFIELD},					\
-    { "nobitfield", - MASK_BITFIELD},					\
-    { "rtd", MASK_RTD},							\
-    { "nortd", - MASK_RTD},						\
-    { "short", MASK_SHORT},						\
-    { "noshort", - MASK_SHORT},						\
-    { "fpa", -(MASK_SKY|MASK_68040_ONLY|MASK_68881)},			\
-    { "fpa", MASK_FPA},							\
-    { "nofpa", - MASK_FPA},						\
-    { "sky", -(MASK_FPA|MASK_68040_ONLY|MASK_68881)},			\
-    { "sky", MASK_SKY},							\
-    { "nosky", - MASK_SKY},						\
-    { "68881", - (MASK_FPA|MASK_SKY)},					\
-    { "68881", MASK_68881},						\
-    { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881)},	\
-    { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY)},		\
-    { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040)},	\
-    { "68020-60", -(MASK_5200|MASK_68040_ONLY)},			\
-    { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040	\
-		   |MASK_68060)},					\
-    { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)},	\
-    { "68030", (MASK_68020|MASK_BITFIELD)},				\
-    { "68040", - (MASK_5200|MASK_68060)},				\
-    { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD			\
-		|MASK_68040_ONLY|MASK_68040)},				\
-    { "68060", - (MASK_5200|MASK_68040)},				\
-    { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD			\
-		|MASK_68040_ONLY|MASK_68060)},				\
-    { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020	\
-		|MASK_BITFIELD|MASK_68881)},				\
-    { "5200", (MASK_5200)},						\
-    { "68851", 0},							\
-    { "no-68851", 0},							\
-    { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY	\
-		  |MASK_68020|MASK_BITFIELD|MASK_68881)},		\
-    { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY	\
-		  |MASK_BITFIELD|MASK_68881)},				\
-    { "68332", MASK_68020},						\
-    { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY	\
-		  |MASK_BITFIELD|MASK_68881)},				\
-    { "cpu32", MASK_68020},						\
-    { "align-int", MASK_ALIGN_INT },					\
-    { "no-align-int", -MASK_ALIGN_INT },				\
-    SUBTARGET_SWITCHES							\
-    { "", TARGET_DEFAULT}}
-/* TARGET_DEFAULT is defined in sun*.h and isi.h, etc.  */
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an
-   initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   fixed part of the option name, and the address of a variable.  The
-   variable, type `char *', is set to the variable part of the given
-   option if the fixed part matches.  The actual option name is made
-   by appending `-m' to the specified name.  */
-#define TARGET_OPTIONS							\
-{ { "align-loops=",	&m68k_align_loops_string },			\
-  { "align-jumps=",	&m68k_align_jumps_string },			\
-  { "align-functions=",	&m68k_align_funcs_string },			\
-  SUBTARGET_OPTIONS							\
-}
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-
-#define OVERRIDE_OPTIONS		\
-{					\
-  override_options();			\
-  if (! TARGET_68020 && flag_pic == 2)	\
-    error("-fPIC is not currently supported on the 68000 or 68010\n");	\
-  SUBTARGET_OVERRIDE_OPTIONS;		\
-}
-
-/* These are meant to be redefined in the host dependent files */
-#define SUBTARGET_SWITCHES
-#define SUBTARGET_OPTIONS
-#define SUBTARGET_OVERRIDE_OPTIONS
-
-/* target machine storage layout */
-
-/* Define for XFmode extended real floating point support.
-   This will automatically cause REAL_ARITHMETIC to be defined.  */
-#define LONG_DOUBLE_TYPE_SIZE 96
-
-/* Define if you don't want extended real, but do want to use the
-   software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion. */
-/* #define REAL_ARITHMETIC */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is true for 68020 insns such as bfins and bfexts.
-   We make it true always by avoiding using the single-bit insns
-   except in special cases with constant bit numbers.  */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is true on the 68000.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.  */
-/* For 68000 we can decide arbitrarily
-   since there are no machine instructions for them.
-   So let's be consistent.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 16
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* No data type wants to be aligned rounder than this. 
-   Most published ABIs say that ints should be aligned on 16 bit
-   boundaries, but cpus with 32 bit busses get better performance
-   aligned on 32 bit boundaries.  Coldfires without a misalignment
-   module require 32 bit alignment. */
-#define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Maximum power of 2 that code can be aligned to.  */
-#define MAX_CODE_ALIGN	2			/* 4 byte alignment */
-
-/* Align loop starts for optimal branching.  */
-#define LOOP_ALIGN(LABEL) (m68k_align_loops)
-
-/* This is how to align an instruction for optimal branching. */
-#define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
-
-#define SELECT_RTX_SECTION(MODE, X)					\
-{									\
-  if (!flag_pic)							\
-    readonly_data_section();						\
-  else if (LEGITIMATE_PIC_OPERAND_P (X))				\
-    readonly_data_section();						\
-  else									\
-    data_section();							\
-}
-
-/* Define number of bits in most basic integer type.
-   (If undefined, default is BITS_PER_WORD).  */
-
-#define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
-
-/* Define these to avoid dependence on meaning of `int'.
-   Note that WCHAR_TYPE_SIZE is used in cexp.y,
-   where TARGET_SHORT is not available.  */
-
-#define WCHAR_TYPE "long int"
-#define WCHAR_TYPE_SIZE 32
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-   For the 68000, we give the data registers numbers 0-7,
-   the address registers numbers 010-017,
-   and the 68881 floating point registers numbers 020-027.  */
-#ifndef SUPPORT_SUN_FPA
-#define FIRST_PSEUDO_REGISTER 24
-#else
-#define FIRST_PSEUDO_REGISTER 56
-#endif
-
-/* This defines the register which is used to hold the offset table for PIC. */
-#define PIC_OFFSET_TABLE_REGNUM 13
-
-/* Used to output a (use pic_offset_table_rtx) so that we 
-   always save/restore a5 in functions that use PIC relocation
-   at *any* time during the compilation process. */
-#define FINALIZE_PIC finalize_pic()
-
-#ifndef SUPPORT_SUN_FPA
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   On the 68000, only the stack pointer is such.  */
-
-#define FIXED_REGISTERS        \
- {/* Data registers.  */       \
-  0, 0, 0, 0, 0, 0, 0, 0,      \
-                               \
-  /* Address registers.  */    \
-  0, 0, 0, 0, 0, 0, 0, 1,      \
-                               \
-  /* Floating point registers  \
-     (if available).  */       \
-  0, 0, 0, 0, 0, 0, 0, 0 }
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS \
- {1, 1, 0, 0, 0, 0, 0, 0,   \
-  1, 1, 0, 0, 0, 0, 0, 1,   \
-  1, 1, 0, 0, 0, 0, 0, 0 }
-
-#else /* SUPPORT_SUN_FPA */
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   On the 68000, only the stack pointer is such.  */
-
-/* fpa0 is also reserved so that it can be used to move data back and
-   forth between high fpa regs and everything else. */
-
-#define FIXED_REGISTERS        \
- {/* Data registers.  */       \
-  0, 0, 0, 0, 0, 0, 0, 0,      \
-                               \
-  /* Address registers.  */    \
-  0, 0, 0, 0, 0, 0, 0, 1,      \
-                               \
-  /* Floating point registers  \
-     (if available).  */       \
-  0, 0, 0, 0, 0, 0, 0, 0,      \
-                               \
-  /* Sun3 FPA registers.  */   \
-  1, 0, 0, 0, 0, 0, 0, 0,      \
-  0, 0, 0, 0, 0, 0, 0, 0,      \
-  0, 0, 0, 0, 0, 0, 0, 0,      \
-  0, 0, 0, 0, 0, 0, 0, 0 }
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS \
- {1, 1, 0, 0, 0, 0, 0, 0, \
-  1, 1, 0, 0, 0, 0, 0, 1, \
-  1, 1, 0, 0, 0, 0, 0, 0, \
-  /* FPA registers.  */   \
-  1, 1, 1, 1, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0  }
-
-#endif /* defined SUPPORT_SUN_FPA */
-
-
-/* Make sure everything's fine if we *don't* have a given processor.
-   This assumes that putting a register in fixed_regs will keep the
-   compiler's mitts completely off it.  We don't bother to zero it out
-   of register classes.  If neither TARGET_FPA or TARGET_68881 is set,
-   the compiler won't touch since no instructions that use these
-   registers will be valid.  */
-
-#ifdef SUPPORT_SUN_FPA
-
-#define CONDITIONAL_REGISTER_USAGE \
-{ 						\
-  int i; 					\
-  HARD_REG_SET x; 				\
-  if (!TARGET_FPA)				\
-    { 						\
-      COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \
-      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
-       if (TEST_HARD_REG_BIT (x, i)) 		\
-	fixed_regs[i] = call_used_regs[i] = 1; 	\
-    } 						\
-  if (TARGET_FPA)				\
-    { 						\
-      COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
-      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
-       if (TEST_HARD_REG_BIT (x, i)) 		\
-	fixed_regs[i] = call_used_regs[i] = 1; 	\
-    } 						\
-}
-
-#endif /* defined SUPPORT_SUN_FPA */
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On the 68000, ordinary registers hold 32 bits worth;
-   for the 68881 registers, a single register is always enough for
-   anything that can be stored in them at all.  */
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE)	\
-   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-#ifndef SUPPORT_SUN_FPA
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On the 68000, the cpu registers can hold any mode but the 68881 registers
-   can hold only SFmode or DFmode.  The 68881 registers can't hold anything
-   if 68881 use is disabled.  */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-  (((REGNO) < 16					\
-    && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8))	\
-   || ((REGNO) >= 16 && (REGNO) < 24				        \
-       && TARGET_68881                                  \
-       && (GET_MODE_CLASS (MODE) == MODE_FLOAT		\
-	   || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)		\
-       && GET_MODE_UNIT_SIZE (MODE) <= 12))
-
-#else /* defined SUPPORT_SUN_FPA */
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On the 68000, the cpu registers can hold any mode but the 68881 registers
-   can hold only SFmode or DFmode.  And the 68881 registers can't hold anything
-   if 68881 use is disabled.  However, the Sun FPA register can
-   (apparently) hold whatever you feel like putting in them.
-   If using the fpa, don't put a double in d7/a0.  */
-
-/* ??? This is confused.  The check to prohibit d7/a0 overlaps should always
-   be enabled regardless of whether TARGET_FPA is specified.  It isn't clear
-   what the other d/a register checks are for.  Every check using REGNO
-   actually needs to use a range, e.g. 24>=X<56 not <56.  There is probably
-   no one using this code anymore.  */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-(((REGNO) < 16								\
-  && !(TARGET_FPA							\
-       && GET_MODE_CLASS ((MODE)) != MODE_INT				\
-       && GET_MODE_UNIT_SIZE ((MODE)) > 4				\
-       && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8	\
-       && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0))		\
- || ((REGNO) < 24							\
-     ? (TARGET_68881							\
-	&& (GET_MODE_CLASS (MODE) == MODE_FLOAT				\
-	    || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)		\
-	&& GET_MODE_UNIT_SIZE (MODE) <= 12)				\
-     : ((REGNO) < 56 ? TARGET_FPA && GET_MODE_UNIT_SIZE (MODE) <= 8 : 0)))
-
-#endif /* defined SUPPORT_SUN_FPA */
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2)			\
-  (! TARGET_68881					\
-   || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT		\
-	|| GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)	\
-       == (GET_MODE_CLASS (MODE2) == MODE_FLOAT		\
-	   || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* m68000 pc isn't overloaded on a register.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 15
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 14
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 14
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 8
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 9
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-/* The 68000 has three kinds of registers, so eight classes would be
-   a complete set.  One of them is not needed.  */
-
-#ifndef SUPPORT_SUN_FPA
-
-enum reg_class {
-  NO_REGS, DATA_REGS,
-  ADDR_REGS, FP_REGS,
-  GENERAL_REGS, DATA_OR_FP_REGS,
-  ADDR_OR_FP_REGS, ALL_REGS,
-  LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- { "NO_REGS", "DATA_REGS",              \
-   "ADDR_REGS", "FP_REGS",              \
-   "GENERAL_REGS", "DATA_OR_FP_REGS",   \
-   "ADDR_OR_FP_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS \
-{					\
-  {0x00000000},  /* NO_REGS */		\
-  {0x000000ff},  /* DATA_REGS */	\
-  {0x0000ff00},  /* ADDR_REGS */	\
-  {0x00ff0000},  /* FP_REGS */		\
-  {0x0000ffff},  /* GENERAL_REGS */	\
-  {0x00ff00ff},  /* DATA_OR_FP_REGS */	\
-  {0x00ffff00},  /* ADDR_OR_FP_REGS */	\
-  {0x00ffffff},  /* ALL_REGS */		\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
-
-#else /* defined SUPPORT_SUN_FPA */
-
-/*
- * Notes on final choices:
- *
- *   1) Didn't feel any need to union-ize LOW_FPA_REGS with anything
- * else.
- *   2) Removed all unions that involve address registers with
- * floating point registers (left in unions of address and data with
- * floating point).
- *   3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS.
- *   4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS.
- *   4) Left in everything else.
- */
-enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS,
-  FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS,
-  DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS,
-  GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS,
-  LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS",  \
-   "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS",  \
-   "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS",  \
-   "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS \
-{							\
- {0, 0},			/* NO_REGS */		\
- {0xff000000, 0x000000ff},	/* LO_FPA_REGS */	\
- {0xff000000, 0x00ffffff},	/* FPA_REGS */		\
- {0x00ff0000, 0x00000000},	/* FP_REGS */		\
- {0xffff0000, 0x00ffffff},	/* FP_OR_FPA_REGS */	\
- {0x000000ff, 0x00000000},	/* DATA_REGS */		\
- {0xff0000ff, 0x00ffffff},	/* DATA_OR_FPA_REGS */	\
- {0x00ff00ff, 0x00000000},	/* DATA_OR_FP_REGS */	\
- {0xffff00ff, 0x00ffffff},	/* DATA_OR_FP_OR_FPA_REGS */\
- {0x0000ff00, 0x00000000},	/* ADDR_REGS */		\
- {0x0000ffff, 0x00000000},	/* GENERAL_REGS */	\
- {0xff00ffff, 0x00ffffff},	/* GENERAL_OR_FPA_REGS */\
- {0x00ffffff, 0x00000000},	/* GENERAL_OR_FP_REGS */\
- {0xffffffff, 0x00ffffff},	/* ALL_REGS */		\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-extern enum reg_class regno_reg_class[];
-#define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
-
-#endif /* SUPPORT_SUN_FPA */
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS ADDR_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.
-   We do a trick here to modify the effective constraints on the
-   machine description; we zorch the constraint letters that aren't
-   appropriate for a specific target.  This allows us to guarantee
-   that a specific kind of register will not be used for a given target
-   without fiddling with the register classes above. */
-
-#ifndef SUPPORT_SUN_FPA
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'a' ? ADDR_REGS :			\
-   ((C) == 'd' ? DATA_REGS :			\
-    ((C) == 'f' ? (TARGET_68881 ? FP_REGS :	\
-		   NO_REGS) :			\
-     NO_REGS)))
-
-#else /* defined SUPPORT_SUN_FPA */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'a' ? ADDR_REGS :			\
-   ((C) == 'd' ? DATA_REGS :			\
-    ((C) == 'f' ? (TARGET_68881 ? FP_REGS :	\
-		   NO_REGS) :			\
-     ((C) == 'x' ? (TARGET_FPA ? FPA_REGS :	\
-		    NO_REGS) :			\
-      ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS :	\
-		     NO_REGS) :			\
-       NO_REGS)))))
-
-#endif /* defined SUPPORT_SUN_FPA */
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   For the 68000, `I' is used for the range 1 to 8
-   allowed as immediate shift counts and in addq.
-   `J' is used for the range of signed numbers that fit in 16 bits.
-   `K' is for numbers that moveq can't handle.
-   `L' is for range -8 to -1, range of values that can be added with subq.
-   `M' is for numbers that moveq+notb can't handle.
-   'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
-   'O' is for 16 (for rotate using swap).
-   'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate.  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
-   (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
-   (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
-   (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
-   (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
-   (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
-   (C) == 'O' ? (VALUE) == 16 : \
-   (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
-
-/*
- * A small bit of explanation:
- * "G" defines all of the floating constants that are *NOT* 68881
- * constants.  this is so 68881 constants get reloaded and the
- * fpmovecr is used.  "H" defines *only* the class of constants that
- * the fpa can use, because these can be gotten at in any fpa
- * instruction and there is no need to force reloads.
- */
-#ifndef SUPPORT_SUN_FPA
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
-#else /* defined SUPPORT_SUN_FPA */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \
-   (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0)
-#endif /* defined SUPPORT_SUN_FPA */
-
-/* A C expression that defines the optional machine-dependent constraint
-   letters that can be used to segregate specific types of operands,  
-   usually memory references, for the target machine.  It should return 1 if
-   VALUE corresponds to the operand type represented by the constraint letter
-   C.  If C is not defined as an extra constraint, the value returned should 
-   be 0 regardless of VALUE.  */
-
-/* For the m68k, `Q' means address register indirect addressing mode. */
-
-#define EXTRA_CONSTRAINT(OP, C)	\
-  ((C) == 'Q' ? (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) : \
-   0 )
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.
-   On the 68000 series, use a data reg if possible when the
-   value is a constant in the range where moveq could be used
-   and we ensure that QImodes are reloaded into data regs.
-   Also, if a floating constant needs reloading, put it in memory.
-   Don't do this for !G constants, since all patterns in the md file
-   expect them to be loaded into a register via fpmovecr.  See above.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)  \
-  ((GET_CODE (X) == CONST_INT			\
-    && (unsigned) (INTVAL (X) + 0x80) < 0x100	\
-    && (CLASS) != ADDR_REGS)			\
-   ? DATA_REGS					\
-   : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
-   ? DATA_REGS					\
-   : (GET_CODE (X) == CONST_DOUBLE		\
-      && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
-   ? (! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G')	\
-      && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
-      ? FP_REGS : NO_REGS)			\
-   : (CLASS))
-
-/* Force QImode output reloads from subregs to be allocated to data regs,
-   since QImode stores from address regs are not supported.  We make the
-   assumption that if the class is not ADDR_REGS, then it must be a superset
-   of DATA_REGS.  */
-
-#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
-  (((MODE) == QImode && (CLASS) != ADDR_REGS)	\
-   ? DATA_REGS					\
-   : (CLASS))
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-/* On the 68000, this is the size of MODE in words,
-   except in the FP regs, where a single reg is always enough.  */
-#ifndef SUPPORT_SUN_FPA
-
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- ((CLASS) == FP_REGS ? 1 \
-  : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Moves between fp regs and other regs are two insns.  */
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)		\
-  (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS)	        \
-    || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS)	\
-    ? 4 : 2)
-
-#else /* defined SUPPORT_SUN_FPA */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \
-  : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Moves between fp regs and other regs are two insns.  */
-/* Likewise for high fpa regs and other regs.  */
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)		\
-  ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS)	\
-    || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS)	\
-    || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS)	\
-    || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS))	\
-   ? 4 : 2)
-
-#endif /* define SUPPORT_SUN_FPA */
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Nonzero if we need to generate stack-probe insns.
-   On most systems they are not needed.
-   When they are needed, define this as the stack offset to probe at.  */
-#define NEED_PROBE 0
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On the 68000, sp@- in a byte insn really pushes a word.
-   On the 5200 (coldfire), sp@- in a byte insn pushes just a byte.  */
-#define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 8
-
-/* Offset of the CFA from the argument pointer register value.  */
-#define ARG_POINTER_CFA_OFFSET 8
-
-/* Value is the number of byte of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.
-
-   On the 68000, the RTS insn cannot pop anything.
-   On the 68010, the RTD insn may be used to pop them if the number
-     of args is fixed, but if the number is variable then the caller
-     must pop them all.  RTD can't be used for library calls now
-     because the library is compiled with the Unix compiler.
-   Use of RTD is a selectable option, since it is incompatible with
-   standard Unix calling sequences.  If the option is not selected,
-   the caller must always pop the args.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE)   \
-  ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE)	\
-    && (TYPE_ARG_TYPES (FUNTYPE) == 0				\
-	|| (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE)))	\
-	    == void_type_node)))				\
-   ? (SIZE) : 0)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-/* On the 68000 the return value is in D0 regardless.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-/* On the 68000 the return value is in D0 regardless.  */
-
-#define LIBCALL_VALUE(MODE)  gen_rtx_REG (MODE, 0)
-
-/* 1 if N is a possible register number for a function value.
-   On the 68000, d0 is the only register thus used.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
-   more than one register.  */
-
-#define NEEDS_UNTYPED_CALL 0
-
-/* Define this if PCC uses the nonreentrant convention for returning
-   structure and union values.  */
-
-#define PCC_STATIC_STRUCT_RETURN
-
-/* 1 if N is a possible register number for function argument passing.
-   On the 68000, no registers are used in this way.  */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the m68k, this is a single integer, which is a number of bytes
-   of arguments scanned so far.  */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the m68k, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM) += ((MODE) != BLKmode			\
-	    ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
-	    : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On the 68000 all args are pushed, except if -mregparm is specified
-   then the first two words of arguments are passed in d0, d1.
-   *NOTE* -mregparm does not work.
-   It exists only to test register calling conventions.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-((TARGET_REGPARM && (CUM) < 8					\
-  && 8 < ((CUM) + ((MODE) == BLKmode				\
-		      ? int_size_in_bytes (TYPE)		\
-		      : GET_MODE_SIZE (MODE))))  		\
- ? 2 - (CUM) / 4 : 0)
-
-/* Generate the assembly code for function entry. */
-#define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue(FILE, SIZE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-  asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.  */
-
-#define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL)	\
-do							\
-  {							\
-    switch (profile_block_flag)				\
-      {							\
-      case 2:						\
-        asm_fprintf (FILE, "\tpea %d\n\tpea %LLPBX0\n\tjsr %U__bb_init_trace_func\n\taddql %I8,%Rsp\n", \
-                           (BLOCK_OR_LABEL)); \
-        break;						\
-							\
-      default:						\
-        asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \
-                           (BLOCK_OR_LABEL), (BLOCK_OR_LABEL)); \
-        break;						\
-      }							\
-  }							\
-while(0)
-
-/* Output assembler code to FILE to increment the counter for
-   the BLOCKNO'th basic block in this source file.  */
-
-#define BLOCK_PROFILER(FILE, BLOCKNO)	\
-do							\
-  {							\
-    switch (profile_block_flag)				\
-      {							\
-      case 2:						\
-        asm_fprintf (FILE, "\tmovel %Ra1,%Rsp@-\n\tlea ___bb,%Ra1\n\tmovel %I%d,%Ra1@(0)\n\tmovel %I%LLPBX0,%Ra1@(4)\n\tmovel %Rsp@+,%Ra1\n\tjsr %U__bb_trace_func\n", \
-                           BLOCKNO);			\
-        break;						\
-							\
-      default:						\
-        asm_fprintf (FILE, "\taddql %I1,%LLPBX2+%d\n", 4 * BLOCKNO); \
-        break;						\
-      }							\
-  }							\
-while(0)
-
-/* Output assembler code to FILE to indicate return from 
-   a function during basic block profiling. */
-
-#define FUNCTION_BLOCK_PROFILER_EXIT(FILE)		\
-  asm_fprintf (FILE, "\tjsr %U__bb_trace_ret\n");
-
-/* Save all registers which may be clobbered by a function call.
-   MACHINE_STATE_SAVE and MACHINE_STATE_RESTORE are target-code macros,
-   used in libgcc2.c.  They may not refer to TARGET_* macros !!! */
-#if defined (__mc68010__) || defined(mc68010) \
-	|| defined(__mc68020__) || defined(mc68020) \
-	|| defined(__mc68030__) || defined(mc68030) \
-	|| defined(__mc68040__) || defined(mc68040) \
-	|| defined(__mcpu32__) || defined(mcpu32)
-#define MACHINE_STATE_m68010_up
-#endif
-
-#ifdef MOTOROLA
-#if defined(__mcf5200__)
-#define MACHINE_STATE_SAVE(id)		\
-    {					\
-      asm ("sub.l 20,%sp");		\
-      asm ("movm.l &0x0303,4(%sp)");	\
-      asm ("move.w %ccr,%d0");		\
-      asm ("movm.l &0x0001,(%sp)");	\
-    }
-#else /* !__mcf5200__ */
-#if defined(MACHINE_STATE_m68010_up)
-#ifdef __HPUX_ASM__
-/* HPUX assembler does not accept %ccr.  */
-#define MACHINE_STATE_SAVE(id)		\
-    {					\
-      asm ("move.w %cc,-(%sp)");	\
-      asm ("movm.l &0xc0c0,-(%sp)");	\
-    }
-#else /* ! __HPUX_ASM__ */
-#define MACHINE_STATE_SAVE(id)		\
-    {					\
-      asm ("move.w %ccr,-(%sp)");	\
-      asm ("movm.l &0xc0c0,-(%sp)");	\
-    }
-#endif /* __HPUX_ASM__ */
-#else /* !MACHINE_STATE_m68010_up */
-#define MACHINE_STATE_SAVE(id)		\
-    {					\
-      asm ("move.w %sr,-(%sp)");	\
-      asm ("movm.l &0xc0c0,-(%sp)");	\
-    }
-#endif /* MACHINE_STATE_m68010_up */
-#endif /* __mcf5200__ */
-#else /* !MOTOROLA */
-#if defined(__mcf5200__)
-#define MACHINE_STATE_SAVE(id)		\
-    {					\
-      asm ("subl %#20,%/sp" : );	\
-      asm ("movml %/d0/%/d1/%/a0/%/a1,%/sp@(4)" : ); \
-      asm ("movew %/cc,%/d0" : );	\
-      asm ("movml %/d0,%/sp@" : );	\
-    }
-#else /* !__mcf5200__ */
-#if defined(MACHINE_STATE_m68010_up)
-#define MACHINE_STATE_SAVE(id)		\
-    {					\
-      asm ("movew %/cc,%/sp@-" : );	\
-      asm ("moveml %/d0/%/d1/%/a0/%/a1,%/sp@-" : ); \
-    }
-#else /* !MACHINE_STATE_m68010_up */
-#define MACHINE_STATE_SAVE(id)		\
-    {					\
-      asm ("movew %/sr,%/sp@-" : );	\
-      asm ("moveml %/d0/%/d1/%/a0/%/a1,%/sp@-" : ); \
-    }
-#endif /* MACHINE_STATE_m68010_up */
-#endif /* __mcf5200__ */
-#endif /* MOTOROLA */
-
-/* Restore all registers saved by MACHINE_STATE_SAVE. */
-
-#ifdef MOTOROLA
-#if defined(__mcf5200__)
-#define MACHINE_STATE_RESTORE(id)	\
-    {					\
-      asm ("movm.l (%sp),&0x0001");	\
-      asm ("move.w %d0,%ccr");		\
-      asm ("movm.l 4(%sp),&0x0303");	\
-      asm ("add.l 20,%sp");		\
-    }
-#else /* !__mcf5200__ */
-#ifdef __HPUX_ASM__
-/* HPUX assembler does not accept %ccr.  */
-#define MACHINE_STATE_RESTORE(id)	\
-    {					\
-      asm ("movm.l (%sp)+,&0x0303");	\
-      asm ("move.w (%sp)+,%cc");	\
-    }
-#else /* ! __HPUX_ASM__ */
-#define MACHINE_STATE_RESTORE(id)	\
-    {					\
-      asm ("movm.l (%sp)+,&0x0303");	\
-      asm ("move.w (%sp)+,%ccr");	\
-    }
-#endif /* __HPUX_ASM__ */
-#endif /* __mcf5200__ */
-#else /* !MOTOROLA */
-#if defined(__mcf5200__)
-#define MACHINE_STATE_RESTORE(id)	\
-    {					\
-      asm ("movml %/sp@,%/d0" : );	\
-      asm ("movew %/d0,%/cc" : );	\
-      asm ("movml %/sp@(4),%/d0/%/d1/%/a0/%/a1" : ); \
-      asm ("addl %#20,%/sp" : );	\
-    }
-#else /* !__mcf5200__ */
-#define MACHINE_STATE_RESTORE(id)	\
-    {					\
-      asm ("moveml %/sp@+,%/d0/%/d1/%/a0/%/a1" : ); \
-      asm ("movew %/sp@+,%/cc" : );	\
-    }
-#endif /* __mcf5200__ */
-#endif /* MOTOROLA */
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Generate the assembly code for function exit. */
-#define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue (FILE, SIZE)
-  
-/* This is a hook for other tm files to change.  */
-/* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
-
-/* Determine if the epilogue should be output as RTL.
-   You should override this if you define FUNCTION_EXTRA_EPILOGUE.  */
-#define USE_RETURN_INSN use_return_insn ()
-
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved.
-
-   On the 68k, if we have a frame, we must add one word to its length
-   to allow for the place that a6 is stored when we do have a frame pointer.
-   Otherwise, we would need to compute the offset from the frame pointer
-   of a local variable as a function of frame_pointer_needed, which
-   is hard.  */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)			\
-{ int regno;							\
-  int offset = -4;						\
-  for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++)	\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      offset += 12;						\
-  for (regno = 0; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      offset += 4;						\
-  (DEPTH) = (offset + ((get_frame_size () + 3) & -4)		\
-	     + (get_frame_size () == 0 ? 0 : 4));		\
-}
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  */
-
-/* On the 68k, the trampoline looks like this:
-     movl #STATIC,a0
-     jmp  FUNCTION
-
-   WARNING: Targets that may run on 68040+ cpus must arrange for
-   the instruction cache to be flushed.  Previous incarnations of
-   the m68k trampoline code attempted to get around this by either
-   using an out-of-line transfer function or pc-relative data, but
-   the fact remains that the code to jump to the transfer function
-   or the code to load the pc-relative data needs to be flushed
-   just as much as the "variable" portion of the trampoline.  
-   Recognizing that a cache flush is going to be required anyway,
-   dispense with such notions and build a smaller trampoline.  */
-
-/* Since more instructions are required to move a template into
-   place than to create it on the spot, don't use a template.  */
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 12
-
-/* Alignment required for a trampoline in bits.  */
-
-#define TRAMPOLINE_ALIGNMENT 16
-
-/* Targets redefine this to invoke code to either flush the cache,
-   or enable stack execution (or both).  */
-
-#ifndef FINALIZE_TRAMPOLINE
-#define FINALIZE_TRAMPOLINE(TRAMP)
-#endif
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.
-
-   We generate a two-instructions program at address TRAMP :
-	movea.l &CXT,%a0
-	jmp FNADDR					*/
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C));	\
-  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
-  emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)),	\
-		  GEN_INT(0x4EF9));					\
-  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
-  FINALIZE_TRAMPOLINE(TRAMP);						\
-}
-
-/* This is the library routine that is used
-   to transfer control from the trampoline
-   to the actual nested function.
-   It is defined for backward compatibility,
-   for linking with object code that used the old
-   trampoline definition.  */
-
-/* A colon is used with no explicit operands
-   to cause the template string to be scanned for %-constructs.  */
-/* The function name __transfer_from_trampoline is not actually used.
-   The function definition just permits use of "asm with operands"
-   (though the operand list is empty).  */
-#define TRANSFER_FROM_TRAMPOLINE				\
-void								\
-__transfer_from_trampoline ()					\
-{								\
-  register char *a0 asm ("%a0");				\
-  asm (GLOBAL_ASM_OP " ___trampoline");				\
-  asm ("___trampoline:");					\
-  asm volatile ("move%.l %0,%@" : : "m" (a0[22]));		\
-  asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18]));	\
-  asm ("rts":);							\
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-#define HAVE_POST_INCREMENT 1
-/* #define HAVE_POST_DECREMENT 0 */
-
-#define HAVE_PRE_DECREMENT 1
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-(((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
-#define REGNO_OK_FOR_DATA_P(REGNO) \
-((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
-#define REGNO_OK_FOR_FP_P(REGNO) \
-(((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
-#ifdef SUPPORT_SUN_FPA
-#define REGNO_OK_FOR_FPA_P(REGNO) \
-(((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56))
-#endif
-
-/* Now macros that check whether X is a register and also,
-   strictly, whether it is in a specified class.
-
-   These macros are specific to the 68000, and may be used only
-   in code for printing assembler insns and in conditions for
-   define_optimization.  */
-
-/* 1 if X is a data register.  */
-
-#define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
-
-/* 1 if X is an fp register.  */
-
-#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
-
-/* 1 if X is an address register  */
-
-#define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
-
-#ifdef SUPPORT_SUN_FPA
-/* 1 if X is a register in the Sun FPA.  */
-#define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X)))
-#else
-/* Answer must be no if we don't have an FPA.  */
-#define FPA_REG_P(X) 0
-#endif
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* Nonzero if the constant value X is a legitimate general operand
-   when generating PIC code.  It is given that flag_pic is on and 
-   that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_PIC_OPERAND_P(X)	\
-  ((! symbolic_operand (X, VOIDmode)				\
-    && ! (GET_CODE (X) == CONST_DOUBLE && CONST_DOUBLE_MEM (X)	\
-	  && GET_CODE (CONST_DOUBLE_MEM (X)) == MEM		\
-	  && symbolic_operand (XEXP (CONST_DOUBLE_MEM (X), 0),	\
-			       VOIDmode)))			\
-   || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)))
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   When generating PIC, an address involving a SYMBOL_REF is legitimate
-   if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
-   We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
-   and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
-
-   Likewise for a LABEL_REF when generating PIC.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS.  */
-
-/* Allow SUBREG everywhere we allow REG.  This results in better code.  It
-   also makes function inlining work when inline functions are called with
-   arguments that are SUBREGs.  */
-
-#define LEGITIMATE_BASE_REG_P(X)   \
-  ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))	\
-   || (GET_CODE (X) == SUBREG				\
-       && GET_CODE (SUBREG_REG (X)) == REG		\
-       && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
-
-#define INDIRECTABLE_1_ADDRESS_P(X)  \
-  ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
-   || LEGITIMATE_BASE_REG_P (X)						\
-   || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC)		\
-       && LEGITIMATE_BASE_REG_P (XEXP (X, 0)))				\
-   || (GET_CODE (X) == PLUS						\
-       && LEGITIMATE_BASE_REG_P (XEXP (X, 0))				\
-       && GET_CODE (XEXP (X, 1)) == CONST_INT				\
-       && (TARGET_68020							\
-	   || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000))	\
-   || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx 	\
-       && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF)		\
-   || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx 	\
-       && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))		\
-
-#define GO_IF_NONINDEXED_ADDRESS(X, ADDR)  \
-{ if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
-
-/* Only labels on dispatch tables are valid for indexing from.  */
-#define GO_IF_INDEXABLE_BASE(X, ADDR)				\
-{ rtx temp;							\
-  if (GET_CODE (X) == LABEL_REF					\
-      && (temp = next_nonnote_insn (XEXP (X, 0))) != 0		\
-      && GET_CODE (temp) == JUMP_INSN				\
-      && (GET_CODE (PATTERN (temp)) == ADDR_VEC			\
-	  || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC))	\
-    goto ADDR;							\
-  if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
-
-#define GO_IF_INDEXING(X, ADDR)	\
-{ if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0)))		\
-    { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); }			\
-  if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1)))		\
-    { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
-
-#define GO_IF_INDEXED_ADDRESS(X, ADDR)	 \
-{ GO_IF_INDEXING (X, ADDR);						\
-  if (GET_CODE (X) == PLUS)						\
-    { if (GET_CODE (XEXP (X, 1)) == CONST_INT				\
-	  && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100))		\
-	{ rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); }	\
-      if (GET_CODE (XEXP (X, 0)) == CONST_INT				\
-	  && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100))		\
-	{ rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
-
-/* coldfire/5200 does not allow HImode index registers.  */
-#define LEGITIMATE_INDEX_REG_P(X)   \
-  ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))	\
-   || (! TARGET_5200					\
-       && GET_CODE (X) == SIGN_EXTEND			\
-       && GET_CODE (XEXP (X, 0)) == REG			\
-       && GET_MODE (XEXP (X, 0)) == HImode		\
-       && REG_OK_FOR_INDEX_P (XEXP (X, 0)))		\
-   || (GET_CODE (X) == SUBREG				\
-       && GET_CODE (SUBREG_REG (X)) == REG		\
-       && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
-
-#define LEGITIMATE_INDEX_P(X)   \
-   (LEGITIMATE_INDEX_REG_P (X)				\
-    || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
-	&& LEGITIMATE_INDEX_REG_P (XEXP (X, 0))		\
-	&& GET_CODE (XEXP (X, 1)) == CONST_INT		\
-	&& (INTVAL (XEXP (X, 1)) == 2			\
-	    || INTVAL (XEXP (X, 1)) == 4		\
-	    || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
-
-/* If pic, we accept INDEX+LABEL, which is what do_tablejump makes.  */
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-{ GO_IF_NONINDEXED_ADDRESS (X, ADDR);					\
-  GO_IF_INDEXED_ADDRESS (X, ADDR);					\
-  if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS	\
-      && LEGITIMATE_INDEX_P (XEXP (X, 0))				\
-      && GET_CODE (XEXP (X, 1)) == LABEL_REF)				\
-    goto ADDR; }
-
-/* Don't call memory_address_noforce for the address to fetch
-   the switch offset.  This address is ok as it stands (see above),
-   but memory_address_noforce would alter it.  */
-#define PIC_CASE_VECTOR_ADDRESS(index) index
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the 68000, we handle X+REG by loading X into a register R and
-   using R+REG.  R will go in an address reg and indexing will be used.
-   However, if REG is a broken-out memory address or multiplication,
-   nothing needs to be done because REG can certainly go in an address reg.  */
-
-#define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)   \
-{ register int ch = (X) != (OLDX);					\
-  if (GET_CODE (X) == PLUS)						\
-    { int copied = 0;							\
-      if (GET_CODE (XEXP (X, 0)) == MULT)				\
-	{ COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);}	\
-      if (GET_CODE (XEXP (X, 1)) == MULT)				\
-	{ COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);}	\
-      if (ch && GET_CODE (XEXP (X, 1)) == REG				\
-	  && GET_CODE (XEXP (X, 0)) == REG)				\
-	goto WIN;							\
-      if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); }		\
-      if (GET_CODE (XEXP (X, 0)) == REG					\
-	       || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND		\
-		   && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG		\
-		   && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode))	\
-	{ register rtx temp = gen_reg_rtx (Pmode);			\
-	  register rtx val = force_operand (XEXP (X, 1), 0);		\
-	  emit_move_insn (temp, val);					\
-	  COPY_ONCE (X);						\
-	  XEXP (X, 1) = temp;						\
-	  goto WIN; }							\
-      else if (GET_CODE (XEXP (X, 1)) == REG				\
-	       || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND		\
-		   && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG		\
-		   && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode))	\
-	{ register rtx temp = gen_reg_rtx (Pmode);			\
-	  register rtx val = force_operand (XEXP (X, 0), 0);		\
-	  emit_move_insn (temp, val);					\
-	  COPY_ONCE (X);						\
-	  XEXP (X, 0) = temp;						\
-	  goto WIN; }}}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the 68000, only predecrement and postincrement address depend thus
-   (the amount of decrement or increment being the length of the operand).  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
- if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE HImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE 1
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Don't cse the address of the function being compiled.  */
-#define NO_RECURSIVE_FUNCTION_CSE
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 4
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-#define SLOW_ZERO_EXTEND
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 0
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE -1
-
-/* When a prototype says `char' or `short', really pass an `int'.  */
-#define PROMOTE_PROTOTYPES
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    /* Constant zero is super cheap due to clr instruction.  */	\
-    if (RTX == const0_rtx) return 0;				\
-    /* if ((OUTER_CODE) == SET) */				\
-      return const_int_cost(RTX);				\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 3;							\
-  case CONST_DOUBLE:						\
-    return 5;
-
-/* Compute the cost of various arithmetic operations.
-   These are vaguely right for a 68020.  */
-/* The costs for long multiply have been adjusted to
-   work properly in synth_mult on the 68020,
-   relative to an average of the time for add and the time for shift,
-   taking away a little more because sometimes move insns are needed.  */
-/* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms.  */
-#define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13)
-#define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5)
-#define DIVW_COST (TARGET_68020 ? 27 : 12)
-
-#define RTX_COSTS(X,CODE,OUTER_CODE)				\
-  case PLUS:							\
-    /* An lea costs about three times as much as a simple add.  */  \
-    if (GET_MODE (X) == SImode					\
-	&& GET_CODE (XEXP (X, 1)) == REG			\
-	&& GET_CODE (XEXP (X, 0)) == MULT			\
-	&& GET_CODE (XEXP (XEXP (X, 0), 0)) == REG		\
-	&& GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT	\
-	&& (INTVAL (XEXP (XEXP (X, 0), 1)) == 2			\
-	    || INTVAL (XEXP (XEXP (X, 0), 1)) == 4		\
-	    || INTVAL (XEXP (XEXP (X, 0), 1)) == 8))		\
-      return COSTS_N_INSNS (3);	 /* lea an@(dx:l:i),am */	\
-    break;							\
-  case ASHIFT:							\
-  case ASHIFTRT:						\
-  case LSHIFTRT:						\
-    if (TARGET_68060)						\
-      return COSTS_N_INSNS(1);					\
-    if (! TARGET_68020)							\
-      {									\
-	if (GET_CODE (XEXP (X, 1)) == CONST_INT)			\
-	  {								\
-	    if (INTVAL (XEXP (X, 1)) < 16)				\
-	      return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2;	\
-	    else							\
-	      /* We're using clrw + swap for these cases.  */		\
-	      return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \
-	  }								\
-	return COSTS_N_INSNS (10); /* worst case */			\
-      }									\
-    /* A shift by a big integer takes an extra instruction.  */ \
-    if (GET_CODE (XEXP (X, 1)) == CONST_INT			\
-	&& (INTVAL (XEXP (X, 1)) == 16))			\
-      return COSTS_N_INSNS (2);	 /* clrw;swap */		\
-    if (GET_CODE (XEXP (X, 1)) == CONST_INT			\
-	&& !(INTVAL (XEXP (X, 1)) > 0				\
-	     && INTVAL (XEXP (X, 1)) <= 8))			\
-      return COSTS_N_INSNS (3);	 /* lsr #i,dn */		\
-    break;							\
-  case MULT:							\
-    if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND			\
-	 || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND)		\
-	&& GET_MODE (X) == SImode)				\
-      return COSTS_N_INSNS (MULW_COST);				\
-    if (GET_MODE (X) == QImode || GET_MODE (X) == HImode)	\
-      return COSTS_N_INSNS (MULW_COST);				\
-    else							\
-      return COSTS_N_INSNS (MULL_COST);				\
-  case DIV:							\
-  case UDIV:							\
-  case MOD:							\
-  case UMOD:							\
-    if (GET_MODE (X) == QImode || GET_MODE (X) == HImode)	\
-      return COSTS_N_INSNS (DIVW_COST); /* div.w */		\
-    return COSTS_N_INSNS (43);	 /* div.l */
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  */
-
-/* Set if the cc value is actually in the 68881, so a floating point
-   conditional branch must be output.  */
-#define CC_IN_68881 04000
-
-/* Store in cc_status the expressions that the condition codes will
-   describe after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-/* On the 68000, all the insns to store in an address register fail to
-   set the cc's.  However, in some cases these instructions can make it
-   possibly invalid to use the saved cc's.  In those cases we clear out
-   some or all of the saved cc's so they won't be used.  */
-
-#define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
-
-#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV)  \
-{ if (cc_prev_status.flags & CC_IN_68881)			\
-    return FLOAT;						\
-  if (cc_prev_status.flags & CC_NO_OVERFLOW)			\
-    return NO_OV;						\
-  return NORMAL; }
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(FILE)	\
-  fprintf (FILE, "#NO_APP\n");
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* Here are four prefixes that are used by asm_fprintf to
-   facilitate customization for alternate assembler syntaxes.
-   Machines with no likelihood of an alternate syntax need not
-   define these and need not use asm_fprintf.  */
-
-/* The prefix for register names.  Note that REGISTER_NAMES
-   is supposed to include this prefix.  */
-
-#define REGISTER_PREFIX ""
-
-/* The prefix for local labels.  You should be able to define this as
-   an empty string, or any arbitrary string (such as ".", ".L%", etc)
-   without having to make any other changes to account for the specific
-   definition.  Note it is a string literal, not interpreted by printf
-   and friends. */
-
-#define LOCAL_LABEL_PREFIX ""
-
-/* The prefix to add to user-visible assembler symbols.  */
-
-#define USER_LABEL_PREFIX "_"
-
-/* The prefix for immediate operands.  */
-
-#define IMMEDIATE_PREFIX "#"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#ifndef SUPPORT_SUN_FPA
-
-#define REGISTER_NAMES \
-{"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",	\
- "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",	\
- "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
-
-#else /* SUPPORTED_SUN_FPA */
-
-#define REGISTER_NAMES \
-{"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",	\
- "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",	\
- "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \
- "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \
- "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \
- "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \
- "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" }
-
-#endif /* defined SUPPORT_SUN_FPA */
-
-/* How to renumber registers for dbx and gdb.
-   On the Sun-3, the floating point registers have numbers
-   18 to 25, not 16 to 23 as they do in the compiler.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
-
-/* Before the prologue, RA is at 0(%sp).  */
-#define INCOMING_RETURN_ADDR_RTX \
-  gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
-
-/* We must not use the DBX register numbers for the DWARF 2 CFA column
-   numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
-   Instead use the identity mapping.  */
-#define DWARF_FRAME_REGNUM(REG) REG
-
-/* Before the prologue, the top of the frame is at 4(%sp).  */
-#define INCOMING_FRAME_SP_OFFSET 4
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define GLOBAL_ASM_OP ".globl"
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fprintf (FILE, "%s ", GLOBAL_ASM_OP);		\
-       assemble_name (FILE, NAME);			\
-       fputs ("\n", FILE);} while (0)
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-
-#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
-  asm_fprintf (FILE, "%0U%s", NAME)
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
-
-/* This is how to output a `long double' extended real constant. */
-  
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE)  				\
-do { long l[3];								\
-     REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l);			\
-     fprintf (FILE, "\t.long 0x%lx,0x%lx,0x%lx\n", l[0], l[1], l[2]);	\
-   } while (0)
-  
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)				\
-  do { char dstr[30];						\
-       REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr);		\
-       fprintf (FILE, "\t.double 0r%s\n", dstr);		\
-     } while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)			\
-do { long l;						\
-     REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-     fprintf (FILE, "\t.long 0x%lx\n", l);		\
-   } while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute.
-   (The 68000 does not use such vectors,
-   but we must define this macro anyway.)  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-/* We don't have a way to align to more than a two-byte boundary, so do the
-   best we can and don't complain.  */
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) >= 1)			\
-    fprintf (FILE, "\t.even\n");
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.skip %u\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Output a float value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)		\
- do {								\
-      if (CODE == 'f')						\
-        {							\
-          char dstr[30];					\
-          REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr);		\
-          asm_fprintf ((FILE), "%I0r%s", dstr);			\
-        }							\
-      else							\
-        {							\
-          long l;						\
-          REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-          asm_fprintf ((FILE), "%I0x%lx", l);			\
-        }							\
-     } while (0)
-
-/* Output a double value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)				\
- do { char dstr[30];							\
-      REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr);			\
-      asm_fprintf (FILE, "%I0r%s", dstr);				\
-    } while (0)
-
-/* Note, long double immediate operands are not actually
-   generated by m68k.md.  */
-#define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE)			\
- do { char dstr[30];							\
-      REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr);			\
-      asm_fprintf (FILE, "%I0r%s", dstr);				\
-    } while (0)
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.
-
-   On the 68000, we use several CODE characters:
-   '.' for dot needed in Motorola-style opcode names.
-   '-' for an operand pushing on the stack:
-       sp@-, -(sp) or -(%sp) depending on the style of syntax.
-   '+' for an operand pushing on the stack:
-       sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
-   '@' for a reference to the top word on the stack:
-       sp@, (sp) or (%sp) depending on the style of syntax.
-   '#' for an immediate operand prefix (# in MIT and Motorola syntax
-       but & in SGS syntax).
-   '!' for the fpcr register (used in some float-to-fixed conversions).
-   '$' for the letter `s' in an op code, but only on the 68040.
-   '&' for the letter `d' in an op code, but only on the 68040.
-   '/' for register prefix needed by longlong.h.
-
-   'b' for byte insn (no effect, on the Sun; this is for the ISI).
-   'd' to force memory addressing to be absolute, not relative.
-   'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
-   'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
-       than directly).  Second part of 'y' below.
-   'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
-       or print pair of registers as rx:ry.
-   'y' for a FPA insn (print pair of registers as rx:ry).  This also outputs
-       CONST_DOUBLE's as SunFPA constant RAM registers if
-       possible, so it should not be used except for the SunFPA. */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)				\
-  ((CODE) == '.' || (CODE) == '#' || (CODE) == '-'			\
-   || (CODE) == '+' || (CODE) == '@' || (CODE) == '!'			\
-   || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand X.  X is an RTL
-   expression.
-
-   CODE is a value that can be used to specify one of several ways
-   of printing the operand.  It is used when identical operands
-   must be printed differently depending on the context.  CODE
-   comes from the `%' specification that was used to request
-   printing of the operand.  If the specification was just `%DIGIT'
-   then CODE is 0; if the specification was `%LTR DIGIT' then CODE
-   is the ASCII code for LTR.
-
-   If X is a register, this macro should print the register's name.
-   The names can be found in an array `reg_names' whose type is
-   `char *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
-
-   When the machine description has a specification `%PUNCT' (a `%'
-   followed by a punctuation character), this macro is called with
-   a null pointer for X and the punctuation character for CODE.
-
-   See m68k.c for the m68k specific codes.  */
-
-#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand that is a memory
-   reference whose address is ADDR.  ADDR is an RTL expression.
-
-   On some machines, the syntax for a symbolic address depends on
-   the section that the address refers to.  On these machines,
-   define the macro `ENCODE_SECTION_INFO' to store the information
-   into the `symbol_ref', and then check for it here.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
-
-/* Define functions defined in aux-output.c and used in templates.  */
-
-extern char *output_move_const_into_data_reg ();
-extern char *output_move_simode_const ();
-extern char *output_move_simode ();
-extern char *output_move_himode ();
-extern char *output_move_qimode ();
-extern char *output_move_stricthi ();
-extern char *output_move_strictqi ();
-extern char *output_move_double ();
-extern char *output_move_const_single ();
-extern char *output_move_const_double ();
-extern char *output_btst ();
-extern char *output_scc_di ();
-extern char *output_addsi3 ();
-extern char *output_andsi3 ();
-extern char *output_iorsi3 ();
-extern char *output_xorsi3 ();
-extern void output_dbcc_and_branch ();
-extern int const_uint32_operand ();
-extern int const_sint32_operand ();
-extern int floating_exact_log2 ();
-extern int not_sp_operand ();
-extern int valid_dbcc_comparison_p ();
-extern int extend_operator ();
-extern int flags_in_68881 ();
-extern int strict_low_part_peephole_ok ();
-
-/* Variables in m68k.c */
-extern char *m68k_align_loops_string;
-extern char *m68k_align_jumps_string;
-extern char *m68k_align_funcs_string;
-extern int m68k_align_loops;
-extern int m68k_align_jumps;
-extern int m68k_align_funcs;
-extern int m68k_last_compare_had_fp_operands;
-
-/* Functions from m68k.c used in macros.  */
-extern int symbolic_operand ();
-extern int const_int_cost ();
-extern int standard_68881_constant_p ();
-extern int standard_sun_fpa_constant_p ();
-extern void output_function_prologue ();
-extern void output_function_epilogue ();
-extern int use_return_insn ();
-extern void print_operand_address ();
-extern void print_operand ();
-extern void notice_update_cc ();
-extern void finalize_pic ();
-extern void override_options ();
-
-
-/*
-Local variables:
-version-control: t
-End:
-*/
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
deleted file mode 100755
index 87e76ef..0000000
--- a/gcc/config/m68k/m68k.md
+++ /dev/null
@@ -1,7913 +0,0 @@
-;;- Machine description for GNU compiler, Motorola 68000 Version
-;;  Copyright (C) 1987, 88, 93-97, 1998 Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;;- Information about MCF5200 port.
-
-;;- The MCF5200 "ColdFire" architecture is a reduced version of the
-;;- 68k ISA.  Differences include reduced support for byte and word
-;;- operands and the removal of BCD, bitfield, rotate, and integer
-;;- divide instructions.  The TARGET_5200 flag turns the use of the
-;;- removed opcodes and addressing modes off.
-;;- 
-
-
-;;- instruction definitions
-
-;;- @@The original PO technology requires these to be ordered by speed,
-;;- @@    so that assigner will pick the fastest.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;;- When naming insn's (operand 0 of define_insn) be careful about using
-;;- names from other targets machine descriptions.
-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-;;- Operand classes for the register allocator:
-;;- 'a' one of the address registers can be used.
-;;- 'd' one of the data registers can be used.
-;;- 'f' one of the m68881 registers can be used
-;;- 'r' either a data or an address register can be used.
-;;- 'x' if one of the Sun FPA registers
-;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
-
-;;- Immediate Floating point operator constraints
-;;- 'G' a floating point constant that is *NOT* one of the standard
-;;   68881 constant values (to force calling output_move_const_double
-;;   to get it from rom if it is a 68881 constant).
-;;- 'H' one of the standard FPA constant values
-;;
-;;   See the functions standard_XXX_constant_p in output-m68k.c for more
-;; info.
-
-;;- Immediate integer operand constraints:
-;;- 'I'  1 .. 8
-;;- 'J'  -32768 .. 32767
-;;- 'K'  all integers EXCEPT -128 .. 127
-;;- 'L'  -8 .. -1
-;;- 'M'  all integers EXCEPT -256 .. 255
-;;- 'N'  24 .. 31
-;;- 'O'  16
-;;- 'P'  8 .. 15
-
-;;- Assembler specs:
-;;- "%."    size separator ("." or "")			move%.l d0,d1
-;;- "%#"    immediate separator ("#" or "")		move%.l %#0,d0
-;;- "%-"    push operand "sp@-"				move%.l d0,%-
-;;- "%+"    pop operand "sp@+"				move%.l d0,%+
-;;- "%@"    top of stack "sp@"				move%.l d0,%@
-;;- "%!"    fpcr register
-;;- "%$"    single-precision fp specifier ("s" or "")	f%$add.x fp0,fp1
-;;- "%&"    double-precision fp specifier ("d" or "")	f%&add.x fp0,fp1
-
-;; UNSPEC usage:
-;; 1  This is a `sin' operation.  The mode of the UNSPEC is MODE_FLOAT.
-;;    operand 1 is the argument for `sin'.
-;; 2  This is a `cos' operation.  The mode of the UNSPEC is MODE_FLOAT.
-;;    operand 1 is the argument for `cos'.
-
-;;- Information about 68040 port.
-
-;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
-;;- be emulated in software by the OS.  It is faster to avoid these
-;;- instructions and issue a library call rather than trapping into
-;;- the kernel.  The affected instructions are fintrz and fscale.  The
-;;- TARGET_68040 flag turns the use of the opcodes off.
-
-;;- The '040 also implements a set of new floating-point instructions
-;;- which specify the rounding precision in the opcode.  This finally
-;;- permit the 68k series to be truly IEEE compliant, and solves all
-;;- issues of excess precision accumulating in the extended registers.
-;;- By default, GCC does not use these instructions, since such code will
-;;- not run on an '030.  To use these instructions, use the -m68040-only
-;;- switch.  By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
-;;- you can make these instructions the default.
-
-;;- These new instructions aren't directly in the md.  They are brought
-;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
-;;- than "".
-
-;;- Information about 68060 port.
-
-;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
-;;- be emulated in software by the OS.  It is faster to avoid these
-;;- instructions and issue a library call rather than trapping into
-;;- the kernel.  The affected instructions are: divs.l <ea>,Dr:Dq;
-;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
-;;- fscale.  The TARGET_68060 flag turns the use of the opcodes off.
-
-;;- 		FPA port explanation:
-
-;;-		Usage of the Sun FPA and the 68881 together
-
-;;- The current port of gcc to the sun fpa disallows use of the m68881
-;;- instructions completely if code is targeted for the fpa.  This is
-;;- for the following reasons:
-
-;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
-;;- can, the 68881 otherwise, and data registers only if you are
-;;- forced to it) is a bitch with the current constraint scheme,
-;;- especially since it would have to work for any combination of
-;;- -mfpa, -m68881.
-
-;;- 2) There are no instructions to move between the two types of
-;;- registers; the stack must be used as an intermediary.
-
-;;- It could indeed be done; I think the best way would be to have
-;;- separate patterns for TARGET_FPA (which implies a 68881),
-;;- TARGET_68881, and no floating point co-processor.  Use
-;;- define_expands for all of the named instruction patterns, and
-;;- include code in the FPA instruction to deal with the 68881 with
-;;- preferences specifically set to favor the fpa.  Some of this has
-;;- already been done:
-;;-
-;;- 	1) Separation of most of the patterns out into a TARGET_FPA
-;;- case and a TARGET_68881 case (the exceptions are the patterns
-;;- which would need one define_expand and three define_insn's under
-;;- it (with a lot of duplicate code between them) to replace the
-;;- current single define_insn.  These are mov{[ds]f,[ds]i} and the
-;;- first two patterns in the md.
-;;-
-;;- Some would still have to be done:
-;;-
-;;-	1) Add code to the fpa patterns which correspond to 68881
-;;- patterns to deal with the 68881 case (including preferences!).
-;;- What you might actually do here is combine the fpa and 68881 code
-;;- back together into one pattern for those instructions where it's
-;;- absolutely necessary and save yourself some duplicate code.  I'm
-;;- not completely sure as to whether you could get away with doing
-;;- this only for the mov* insns, or if you'd have to do it for all
-;;- named insns.
-;;- 	2) Add code to the mov{[ds]f,[ds]i} instructions to handle
-;;- moving between fpa regs and 68881 regs.
-
-;;- Since the fpa is more powerful than the 68881 and also has more
-;;- registers, and since I think the resultant md would be medium ugly
-;;- (lot's of duplicate code, ugly constraint strings), I elected not
-;;- to do this change.
-
-;;- Another reason why someone *might* want to do the change is to
-;;- control which register classes are accessed in a slightly cleaner
-;;- way than I have.  See the blurb on CONDITIONAL_REGISTER_USAGE in
-;;- the internals manual.
-
-;;- Yet another reason why someone might want to do this change is to
-;;- allow use of some of the 68881 insns which have no equivalent on
-;;- the fpa.  The sqrt instruction comes fairly quickly to mind.
-
-;;- If this is ever done, don't forget to change sun3.h so that
-;;- it *will* define __HAVE_68881__ when the FPA is in use.
-
-;;-		Condition code hack
-
-;;- When a floating point compare is done in the fpa, the resulting
-;;- condition codes are left in the fpastatus register.  The values in
-;;- this register must be moved into the 68000 cc register before any
-;;- jump is executed.  Once this has been done, regular jump
-;;- instructions are fine (ie. floating point jumps are not necessary.
-;;- They are only done if the cc is in the 68881).
-
-;;- The instructions that move the fpastatus register to the 68000
-;;- register clobber a data register (the move cannot be done direct).
-;;- These instructions might be bundled either with the compare
-;;- instruction, or the branch instruction.  If we were using both the
-;;- fpa and the 68881 together, we would wish to only mark the
-;;- register clobbered if we were doing the compare in the fpa, but I
-;;- think that that decision (whether to clobber the register or not)
-;;- must be done before register allocation (makes sense) and hence we
-;;- can't know if the floating point compare will be done in the fpa
-;;- or the fp.  So whenever we are asked for code that uses the fpa,
-;;- we will mark a data register as clobbered.  This is reasonable, as
-;;- almost all floating point compare operations done with fpa code
-;;- enabled will be done in the fpa.  It's even more reasonable since
-;;- we decided to make the 68881 and the fpa mutually exclusive.
-
-;;- We place to code to move the fpastatus register inside of a
-;;- define_expand so that we can do it conditionally based on whether
-;;- we are targeting an fpa or not.
-
-;;- This still leaves us with the question of where we wish to put the
-;;- code to move the fpastatus reg.  If we put it in the compare
-;;- instruction, we can restrict the clobbering of the register to
-;;- floating point compares, but we can't take advantage of floating
-;;- point subtracts & etc. that alter the fpastatus register.  If we
-;;- put it in the branch instruction, all branches compiled with fpa
-;;- code enabled will clobber a data register, but we will be able to
-;;- take advantage of fpa subtracts.  This balance favors putting the
-;;- code in with the compare instruction.
-
-;;- Note that if some enterprising hacker should decide to switch
-;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
-
-;;-		Usage of the top 16 fpa registers
-
-;;- The only locations which we may transfer fpa registers 16-31 from
-;;- or to are the fpa registers 0-15.  (68000 registers and memory
-;;- locations are impossible).  This causes problems in gcc, which
-;;- assumes that mov?? instructions require no additional registers
-;;- (see section 11.7) and since floating point moves *must* be
-;;- supported into general registers (see section 12.3 under
-;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
-
-;;- My solution was to reserve fpa0 for moves into or out of these top
-;;- 16 registers and to disparage the choice to reload into or out of
-;;- these registers as much as I could.  That alternative is always
-;;- last in the list, so it will not be used unless all else fails.  I
-;;- will note that according to my current information, sun's compiler
-;;- doesn't use these top 16 registers at all.
-
-;;- There is another possible way to do it.  I *believe* that if you
-;;- make absolutely sure that the code will not be executed in the
-;;- reload pass, you can support the mov?? names with define_expands
-;;- which require new registers.  This may be possible by the
-;;- appropriate juggling of constraints.  I may come back to this later.
-
-;;- 		Usage of constant RAM
-
-;;- This has been handled correctly (I believe) but the way I've done
-;;- it could use a little explanation.  The constant RAM can only be
-;;- accessed when the instruction is in "command register" mode.
-;;- "command register" mode means that no accessing of memory or the
-;;- 68000 registers is being done.  This can be expressed easily in
-;;- constraints, so generally the mode of the instruction is
-;;- determined by a branch off of which_alternative.  In outputting
-;;- instructions, a 'w' means to output an access to the constant ram
-;;- (if the arg is CONST_DOUBLE and is one of the available
-;;- constants), and 'x' means to output a register pair (if the arg is
-;;- a 68000 register) and a 'y' is the combination of the above two
-;;- processes.  You use a 'y' in two operand DF instructions where you
-;;- *know* the other operand is an fpa register, you use an 'x' in DF
-;;- instructions where the arg might be a 68000 register and the
-;;- instruction is *not* in "command register" mode, and you use a 'w'
-;;- in two situations: 1) The instruction *is* in command register
-;;- mode (and hence won't be accessing 68000 registers), or 2) The
-;;- instruction is a two operand SF instruction where you know the
-;;- other operand is an fpa register.
-
-;;-		Optimization issues
-
-;;- I actually think that I've included all of the fpa instructions
-;;- that should be included.  Note that if someone is interested in
-;;- doing serious floating point work on the sun fpa, I would advise
-;;- the use of the "asm" instruction in gcc to allow you to use the
-;;- sin, cos, and exponential functions on the fpa board.
-
-;;- END FPA Explanation Section.
-
-
-;;- Some of these insn's are composites of several m68000 op codes.
-;;- The assembler (or final @@??) insures that the appropriate one is
-;;- selected.
-
-(define_insn ""
-  [(set (match_operand:DF 0 "push_operand" "=m")
-	(match_operand:DF 1 "general_operand" "ro<>fyE"))]
-  ""
-  "*
-{
-  if (FP_REG_P (operands[1]))
-    return \"fmove%.d %f1,%0\";
-  if (FPA_REG_P (operands[1]))
-    return \"fpmove%.d %1, %x0\";
-  return output_move_double (operands);
-}")
-
-(define_insn "pushdi"
-  [(set (match_operand:DI 0 "push_operand" "=m")
-	(match_operand:DI 1 "general_operand" "ro<>Fyi"))]
-  ""
-  "*
-{
-  return output_move_double (operands);
-}")
-
-;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
-;; be folded while optimizing anyway.
-
-(define_expand "tstdi"
-  [(parallel [(set (cc0)
-		   (match_operand:DI 0 "nonimmediate_operand" ""))
-	      (clobber (match_scratch:SI 1 ""))
-	      (clobber (match_scratch:DI 2 ""))])]
-  ""
-  "m68k_last_compare_had_fp_operands = 0;")
-
-(define_insn ""
-  [(set (cc0)
-	(match_operand:DI 0 "nonimmediate_operand" "am,d"))
-   (clobber (match_scratch:SI 1 "=X,d"))
-   (clobber (match_scratch:DI 2 "=d,X"))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    {
-      rtx xoperands[2];
-
-      xoperands[0] = operands[2];
-      xoperands[1] = operands[0];
-      output_move_double (xoperands);
-      cc_status.flags |= CC_REVERSED;
-      return \"neg%.l %R2\;negx%.l %2\";
-    }
-  if (find_reg_note (insn, REG_DEAD, operands[0]))
-    {
-      cc_status.flags |= CC_REVERSED;
-      return \"neg%.l %R0\;negx%.l %0\";
-    }
-  else
-    /*
-    ** 'sub' clears %1, and also clears the X cc bit
-    ** 'tst' sets the Z cc bit according to the low part of the DImode operand
-    ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
-    */
-    return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
-}")
-
-(define_expand "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "nonimmediate_operand" ""))]
-  ""
-  "m68k_last_compare_had_fp_operands = 0;")
-
-(define_insn ""
-  [(set (cc0)
-	(match_operand:SI 0 "nonimmediate_operand" "rm"))]
-  ""
-  "*
-{
-#ifdef ISI_OV
-  /* ISI's assembler fails to handle tstl a0.  */
-  if (! ADDRESS_REG_P (operands[0]))
-#else
-  if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
-#endif
-    return \"tst%.l %0\";
-  /* If you think that the 68020 does not support tstl a0,
-     reread page B-167 of the 68020 manual more carefully.  */
-  /* On an address reg, cmpw may replace cmpl.  */
-#ifdef SGS_CMP_ORDER
-  return \"cmp%.w %0,%#0\";
-#else
-  return \"cmp%.w %#0,%0\";
-#endif
-}")
-
-;; This can't use an address register, because comparisons
-;; with address registers as second operand always test the whole word.
-(define_expand "tsthi"
-  [(set (cc0)
-	(match_operand:HI 0 "nonimmediate_operand" ""))]
-  ""
-  "m68k_last_compare_had_fp_operands = 0;")
-
-(define_insn ""
-  [(set (cc0)
-	(match_operand:HI 0 "nonimmediate_operand" "dm"))]
-  ""
-  "tst%.w %0")
-
-(define_expand "tstqi"
-  [(set (cc0)
-	(match_operand:QI 0 "nonimmediate_operand" ""))]
-  ""
-  "m68k_last_compare_had_fp_operands = 0;")
-
-(define_insn ""
-  [(set (cc0)
-	(match_operand:QI 0 "nonimmediate_operand" "dm"))]
-  ""
-  "tst%.b %0")
-
-(define_expand "tstsf"
-  [(set (cc0)
-	(match_operand:SF 0 "general_operand" ""))]
-  "TARGET_68881 || TARGET_FPA"
-  "
-{
-  m68k_last_compare_had_fp_operands = 1;
-  if (TARGET_FPA)
-    {
-      emit_insn (gen_tstsf_fpa (operands[0]));
-      DONE;
-    }
-}")
-
-(define_insn "tstsf_fpa"
-  [(set (cc0)
-	(match_operand:SF 0 "general_operand" "xmdF"))
-   (clobber (match_scratch:SI 1 "=d"))]
-  "TARGET_FPA"
-  "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
-
-(define_insn ""
-  [(set (cc0)
-	(match_operand:SF 0 "general_operand" "fdm"))]
-  "TARGET_68881"
-  "*
-{
-  cc_status.flags = CC_IN_68881;
-  if (FP_REG_P (operands[0]))
-    return \"ftst%.x %0\";
-  return \"ftst%.s %0\";
-}")
-
-(define_expand "tstdf"
-  [(set (cc0)
-	(match_operand:DF 0 "general_operand" ""))]
-  "TARGET_68881 || TARGET_FPA"
-  "
-{
-  m68k_last_compare_had_fp_operands = 1;
-  if (TARGET_FPA)
-    {
-      emit_insn (gen_tstsf_fpa (operands[0]));
-      DONE;
-    }
-}")
-
-(define_insn "tstdf_fpa"
-  [(set (cc0)
-	(match_operand:DF 0 "general_operand" "xrmF"))
-   (clobber (match_scratch:SI 1 "=d"))]
-  "TARGET_FPA"
-  "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
-
-(define_insn ""
-  [(set (cc0)
-	(match_operand:DF 0 "general_operand" "fm"))]
-  "TARGET_68881"
-  "*
-{
-  cc_status.flags = CC_IN_68881;
-  if (FP_REG_P (operands[0]))
-    return \"ftst%.x %0\";
-  return \"ftst%.d %0\";
-}")
-
-;; compare instructions.
-
-(define_expand "cmpdi"
-  [(parallel
-    [(set (cc0)
-	  (compare (match_operand:DI 0 "nonimmediate_operand" "")
-		   (match_operand:DI 1 "general_operand" "")))
-     (clobber (match_dup 2))])]
-  ""
-  "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
-		 (match_operand:DI 2 "general_operand" "d,0")))
-   (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
-  else
-    {
-      cc_status.flags |= CC_REVERSED;
-      return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
-    }
-}")
-
-;; This is the second "hook" for PIC code (in addition to movsi). See
-;; comment of movsi for a description of PIC handling.
-(define_expand "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "")
-		 (match_operand:SI 1 "general_operand" "")))]
-  ""
-  "
-{
-  m68k_last_compare_had_fp_operands = 0;
-  if (flag_pic && symbolic_operand (operands[1], SImode))
-    {
-      /* The source is an address which requires PIC relocation.
-         Call legitimize_pic_address with the source, mode, and a relocation
-         register (a new pseudo, or the final destination if reload_in_progress
-         is set).   Then fall through normally */
-      extern rtx legitimize_pic_address();
-      rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
-      operands[1] = legitimize_pic_address (operands[1], SImode, temp);
-    }
-}")
-
-;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
-		 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
-  "!TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-#ifdef SGS_CMP_ORDER
-    return \"cmpm%.l %0,%1\";
-#else
-    return \"cmpm%.l %1,%0\";
-#endif
-  if (REG_P (operands[1])
-      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
-    { cc_status.flags |= CC_REVERSED;
-#ifdef SGS_CMP_ORDER
-      return \"cmp%.l %d1,%d0\";
-#else
-      return \"cmp%.l %d0,%d1\";
-#endif
-    }
-#ifdef SGS_CMP_ORDER
-  return \"cmp%.l %d0,%d1\";
-#else
-  return \"cmp%.l %d1,%d0\";
-#endif
-}")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
-		 (match_operand:SI 1 "general_operand" "r,mrKs")))]
-  "TARGET_5200"
-  "*
-{
-  if (REG_P (operands[1])
-      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
-    { cc_status.flags |= CC_REVERSED;
-#ifdef SGS_CMP_ORDER
-      return \"cmp%.l %d1,%d0\";
-#else
-      return \"cmp%.l %d0,%d1\";
-#endif
-    }
-#ifdef SGS_CMP_ORDER
-  return \"cmp%.l %d0,%d1\";
-#else
-  return \"cmp%.l %d1,%d0\";
-#endif
-}")
-
-(define_expand "cmphi"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "nonimmediate_operand" "")
-		 (match_operand:HI 1 "general_operand" "")))]
-  "!TARGET_5200"
-  "m68k_last_compare_had_fp_operands = 0;")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
-		 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
-  "!TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-#ifdef SGS_CMP_ORDER
-    return \"cmpm%.w %0,%1\";
-#else
-    return \"cmpm%.w %1,%0\";
-#endif
-  if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
-      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
-    { cc_status.flags |= CC_REVERSED;
-#ifdef SGS_CMP_ORDER
-      return \"cmp%.w %d1,%d0\";
-#else
-      return \"cmp%.w %d0,%d1\";
-#endif
-    }
-#ifdef SGS_CMP_ORDER
-  return \"cmp%.w %d0,%d1\";
-#else
-  return \"cmp%.w %d1,%d0\";
-#endif
-}")
-
-(define_expand "cmpqi"
-  [(set (cc0)
-	(compare (match_operand:QI 0 "nonimmediate_operand" "")
-		 (match_operand:QI 1 "general_operand" "")))]
-  "!TARGET_5200"
-  "m68k_last_compare_had_fp_operands = 0;")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
-		 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
-  "!TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-#ifdef SGS_CMP_ORDER
-    return \"cmpm%.b %0,%1\";
-#else
-    return \"cmpm%.b %1,%0\";
-#endif
-  if (REG_P (operands[1])
-      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
-    { cc_status.flags |= CC_REVERSED;
-#ifdef SGS_CMP_ORDER
-      return \"cmp%.b %d1,%d0\";
-#else
-      return \"cmp%.b %d0,%d1\";
-#endif
-    }
-#ifdef SGS_CMP_ORDER
-  return \"cmp%.b %d0,%d1\";
-#else
-  return \"cmp%.b %d1,%d0\";
-#endif
-}")
-
-(define_expand "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "general_operand" "")
-		 (match_operand:DF 1 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "
-{
-  m68k_last_compare_had_fp_operands = 1;
-  if (TARGET_FPA)
-    {
-      emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
-      DONE;
-    }
-}")
-
-(define_insn "cmpdf_fpa"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "general_operand" "x,y")
-		 (match_operand:DF 1 "general_operand" "xH,rmF")))
-   (clobber (match_scratch:SI 2 "=d,d"))]
-  "TARGET_FPA"
-  "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:DF 0 "general_operand" "f,mG")
-		 (match_operand:DF 1 "general_operand" "fmG,f")))]
-  "TARGET_68881"
-  "*
-{
-  cc_status.flags = CC_IN_68881;
-#ifdef SGS_CMP_ORDER
-  if (REG_P (operands[0]))
-    {
-      if (REG_P (operands[1]))
-	return \"fcmp%.x %0,%1\";
-      else
-        return \"fcmp%.d %0,%f1\";
-    }
-  cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.d %1,%f0\";
-#else
-  if (REG_P (operands[0]))
-    {
-      if (REG_P (operands[1]))
-	return \"fcmp%.x %1,%0\";
-      else
-        return \"fcmp%.d %f1,%0\";
-    }
-  cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.d %f0,%1\";
-#endif
-}")
-
-(define_expand "cmpsf"
- [(set (cc0)
-       (compare (match_operand:SF 0 "general_operand" "")
-		(match_operand:SF 1 "general_operand" "")))]
- "TARGET_68881 || TARGET_FPA"
- "
-{
-  m68k_last_compare_had_fp_operands = 1;
-  if (TARGET_FPA)
-    {
-      emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
-      DONE;
-    }
-}")
-
-(define_insn "cmpsf_fpa"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "general_operand" "x,y")
-		 (match_operand:SF 1 "general_operand" "xH,rmF")))
-   (clobber (match_scratch:SI 2 "=d,d"))]
-  "TARGET_FPA"
-  "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:SF 0 "general_operand" "f,mdG")
-		 (match_operand:SF 1 "general_operand" "fmdG,f")))]
-  "TARGET_68881"
-  "*
-{
-  cc_status.flags = CC_IN_68881;
-#ifdef SGS_CMP_ORDER
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"fcmp%.x %0,%1\";
-      else
-        return \"fcmp%.s %0,%f1\";
-    }
-  cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.s %1,%f0\";
-#else
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"fcmp%.x %1,%0\";
-      else
-        return \"fcmp%.s %f1,%0\";
-    }
-  cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.s %f0,%1\";
-#endif
-}")
-
-;; Recognizers for btst instructions.
-
-;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
-;; specified as a constant, so we must disable all patterns that may extract
-;; from a MEM at a constant bit position if we can't use this as a constraint.
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
-			    (const_int 1)
-			    (minus:SI (const_int 7)
-				      (match_operand:SI 1 "general_operand" "di"))))]
-  "!TARGET_5200"
-  "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
-
-;; This is the same as the above pattern except for the constraints.  The 'i'
-;; has been deleted.
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
-			    (const_int 1)
-			    (minus:SI (const_int 7)
-				      (match_operand:SI 1 "general_operand" "d"))))]
-  "TARGET_5200"
-  "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
-			    (const_int 1)
-			    (minus:SI (const_int 31)
-				      (match_operand:SI 1 "general_operand" "di"))))]
-  ""
-  "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
-
-;; The following two patterns are like the previous two
-;; except that they use the fact that bit-number operands
-;; are automatically masked to 3 or 5 bits.
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
-			    (const_int 1)
-			    (minus:SI (const_int 7)
-				      (and:SI
-				       (match_operand:SI 1 "register_operand" "d")
-				       (const_int 7)))))]
-  ""
-  "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
-			    (const_int 1)
-			    (minus:SI (const_int 31)
-				      (and:SI
-				       (match_operand:SI 1 "register_operand" "d")
-				       (const_int 31)))))]
-  ""
-  "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
-
-;; Nonoffsettable mem refs are ok in this one pattern
-;; since we don't try to adjust them.
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
-			    (const_int 1)
-			    (match_operand:SI 1 "const_int_operand" "n")))]
-  "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
-  "*
-{
-  operands[1] = GEN_INT (7 - INTVAL (operands[1]));
-  return output_btst (operands, operands[1], operands[0], insn, 7);
-}")
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
-			    (const_int 1)
-			    (match_operand:SI 1 "const_int_operand" "n")))]
-  "!TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      operands[0] = adj_offsettable_operand (operands[0],
-					     INTVAL (operands[1]) / 8);
-      operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
-      return output_btst (operands, operands[1], operands[0], insn, 7);
-    }
-  operands[1] = GEN_INT (31 - INTVAL (operands[1]));
-  return output_btst (operands, operands[1], operands[0], insn, 31);
-}")
-
-;; This is the same as the above pattern except for the constraints.
-;; The 'o' has been replaced with 'Q'.
-
-(define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
-			    (const_int 1)
-			    (match_operand:SI 1 "const_int_operand" "n")))]
-  "TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      operands[0] = adj_offsettable_operand (operands[0],
-					     INTVAL (operands[1]) / 8);
-      operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
-      return output_btst (operands, operands[1], operands[0], insn, 7);
-    }
-  operands[1] = GEN_INT (31 - INTVAL (operands[1]));
-  return output_btst (operands, operands[1], operands[0], insn, 31);
-}")
-
-
-;; move instructions
-
-;; A special case in which it is not desirable
-;; to reload the constant into a data register.
-(define_insn "pushexthisi_const"
-  [(set (match_operand:SI 0 "push_operand" "=m")
-	(match_operand:SI 1 "const_int_operand" "J"))]
-  "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
-  "*
-{
-  if (operands[1] == const0_rtx)
-    return \"clr%.l %0\";
-  return \"pea %a1\";
-}")
-
-;This is never used.
-;(define_insn "swapsi"
-;  [(set (match_operand:SI 0 "general_operand" "+r")
-;	(match_operand:SI 1 "general_operand" "+r"))
-;   (set (match_dup 1) (match_dup 0))]
-;  ""
-;  "exg %1,%0")
-
-;; Special case of fullword move when source is zero.
-;; The reason this is special is to avoid loading a zero
-;; into a data reg with moveq in order to store it elsewhere.
-
-(define_insn "movsi_const0"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(const_int 0))]
-  ;; clr insns on 68000 read before writing.
-  ;; This isn't so on the 68010, but we have no TARGET_68010.
-  "((TARGET_68020 || TARGET_5200)
-    || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
-  "*
-{
-  if (ADDRESS_REG_P (operands[0]))
-    {
-      /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
-      if (!TARGET_68040 && !TARGET_68060)
-	return \"sub%.l %0,%0\";
-      else
-	{
-#ifdef MOTOROLA
-#ifdef SGS
-	  /* Many SGS assemblers croak on size specifiers for constants. */
-	  return \"lea 0,%0\";
-#else
-	  return \"lea 0.w,%0\";
-#endif
-#else
-	  return \"lea 0:w,%0\";
-#endif
-	}
-    }
-  /* moveq is faster on the 68000.  */
-  if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
-#if defined(MOTOROLA) && !defined(CRDS)
-    return \"moveq%.l %#0,%0\";
-#else
-    return \"moveq %#0,%0\";
-#endif
-  return \"clr%.l %0\";
-}")
-
-;; General case of fullword move.
-;;
-;; This is the main "hook" for PIC code.  When generating
-;; PIC, movsi is responsible for determining when the source address
-;; needs PIC relocation and appropriately calling legitimize_pic_address
-;; to perform the actual relocation.
-;;
-;; In both the PIC and non-PIC cases the patterns generated will
-;; matched by the next define_insn.
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (flag_pic && symbolic_operand (operands[1], SImode))
-    {
-      /* The source is an address which requires PIC relocation.
-         Call legitimize_pic_address with the source, mode, and a relocation
-         register (a new pseudo, or the final destination if reload_in_progress
-         is set).   Then fall through normally */
-      extern rtx legitimize_pic_address();
-      rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
-      operands[1] = legitimize_pic_address (operands[1], SImode, temp);
-    }
-}")
-
-;; General case of fullword move.  The register constraints
-;; force integer constants in range for a moveq to be reloaded
-;; if they are headed for memory.
-(define_insn ""
-  ;; Notes: make sure no alternative allows g vs g.
-  ;; We don't allow f-regs since fixed point cannot go in them.
-  ;; We do allow y and x regs since fixed point is allowed in them.
-  [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
-	(match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
-  "!TARGET_5200"
-  "*
-{
-  if (which_alternative == 3)
-    return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
-  if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
-    return \"fpmove%.l %x1,%x0\";
-  return output_move_simode (operands);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
-	(match_operand:SI 1 "general_operand" "g,r<Q>"))]
-  "TARGET_5200"
-  "* return output_move_simode (operands);")
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(match_operand:HI 1 "general_operand" "g"))]
-  "!TARGET_5200"
-  "* return output_move_himode (operands);")
-
- (define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
-	(match_operand:HI 1 "general_operand" "g,r<Q>"))]
-  "TARGET_5200"
-  "* return output_move_himode (operands);")
-
-(define_expand "movstricthi"
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
-	(match_operand:HI 1 "general_operand" "rmn"))]
-  "!TARGET_5200"
-  "* return output_move_stricthi (operands);")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
-	(match_operand:HI 1 "general_operand" "rmn,r"))]
-  "TARGET_5200"
-  "* return output_move_stricthi (operands);")
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
-	(match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
-  "!TARGET_5200"
-  "* return output_move_qimode (operands);")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d<Q>,dm,d*a")
-	(match_operand:QI 1 "general_operand" "dmi,d<Q>,di*a"))]
-  "TARGET_5200"
-  "* return output_move_qimode (operands);")
-
-(define_expand "movstrictqi"
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
-	(match_operand:QI 1 "general_operand" "dmn"))]
-  "!TARGET_5200"
-  "* return output_move_strictqi (operands);")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
-	(match_operand:QI 1 "general_operand" "dmn,d"))]
-  "TARGET_5200"
-  "* return output_move_strictqi (operands);")
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
-	(match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
-;  [(set (match_operand:SF 0 "general_operand" "=rmf")
-;	(match_operand:SF 1 "general_operand" "rmfF"))]
-  "!TARGET_5200"
-  "*
-{
-  if (which_alternative >= 4)
-    return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
-  if (FPA_REG_P (operands[0]))
-    {
-      if (FPA_REG_P (operands[1]))
-	return \"fpmove%.s %x1,%x0\";
-      else if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	return output_move_const_single (operands);
-      else if (FP_REG_P (operands[1]))
-        return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
-      return \"fpmove%.s %x1,%x0\";
-    }
-  if (FPA_REG_P (operands[1]))
-    {
-      if (FP_REG_P (operands[0]))
-	return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
-      else
-	return \"fpmove%.s %x1,%x0\";
-    }
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"f%$move%.x %1,%0\";
-      else if (ADDRESS_REG_P (operands[1]))
-	return \"move%.l %1,%-\;f%$move%.s %+,%0\";
-      else if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	return output_move_const_single (operands);
-      return \"f%$move%.s %f1,%0\";
-    }
-  if (FP_REG_P (operands[1]))
-    {
-      if (ADDRESS_REG_P (operands[0]))
-	return \"fmove%.s %1,%-\;move%.l %+,%0\";
-      return \"fmove%.s %f1,%0\";
-    }
-  if (operands[1] == CONST0_RTX (SFmode)
-      /* clr insns on 68000 read before writing.
-	 This isn't so on the 68010, but we have no TARGET_68010.  */
-      && ((TARGET_68020 || TARGET_5200)
-	  || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
-    {
-      if (ADDRESS_REG_P (operands[0]))
-	{
-	  /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
-	  if (!TARGET_68040 && !TARGET_68060)
-	    return \"sub%.l %0,%0\";
-	  else
-	    {
-#ifdef MOTOROLA
-#ifdef SGS
-	      /* Many SGS assemblers croak on size specifiers for constants. */
-	      return \"lea 0,%0\";
-#else
-	      return \"lea 0.w,%0\";
-#endif
-#else
-	      return \"lea 0:w,%0\";
-#endif
-	    }
-	}
-      /* moveq is faster on the 68000.  */
-      if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
-	{
-#if defined(MOTOROLA) && !defined(CRDS)
-	  return \"moveq%.l %#0,%0\";
-#else
-	  return \"moveq %#0,%0\";
-#endif
-	}
-      return \"clr%.l %0\";
-    }
-  return \"move%.l %1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=r,g")
-	(match_operand:SF 1 "general_operand" "g,r"))]
-  "TARGET_5200"
-  "* return \"move%.l %1,%0\";")
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
-	(match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
-;  [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
-;	(match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
-  "!TARGET_5200"
-  "*
-{
-  if (which_alternative == 7)
-    return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
-  if (FPA_REG_P (operands[0]))
-    {
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	return output_move_const_double (operands);
-      if (FP_REG_P (operands[1]))
-        return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
-      return \"fpmove%.d %x1,%x0\";
-    }
-  else if (FPA_REG_P (operands[1]))
-    {
-      if (FP_REG_P(operands[0]))
-        return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
-      else
-        return \"fpmove%.d %x1,%x0\";
-    }
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"f%&move%.x %1,%0\";
-      if (REG_P (operands[1]))
-	{
-	  rtx xoperands[2];
-	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
-	  output_asm_insn (\"move%.l %1,%-\", operands);
-	  return \"f%&move%.d %+,%0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	return output_move_const_double (operands);
-      return \"f%&move%.d %f1,%0\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	{
-	  output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
-	  operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-	  return \"move%.l %+,%0\";
-	}
-      else
-        return \"fmove%.d %f1,%0\";
-    }
-  return output_move_double (operands);
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=r,g")
-	(match_operand:DF 1 "general_operand" "g,r"))]
-  "TARGET_5200"
-  "* return output_move_double (operands);")
-
-(define_expand "movxf"
-  [(set (match_operand:XF 0 "nonimmediate_operand" "")
-	(match_operand:XF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (CONSTANT_P (operands[1]))
-    {
-      operands[1] = force_const_mem (XFmode, operands[1]);
-      if (! memory_address_p (XFmode, XEXP (operands[1], 0))
-	  && ! reload_in_progress)
-	operands[1] = change_address (operands[1], XFmode,
-				      XEXP (operands[1], 0));
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
-	(match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
-  "TARGET_68881"
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"fmove%.x %1,%0\";
-      if (REG_P (operands[1]))
-	{
-	  rtx xoperands[2];
-	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
-	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
-	  output_asm_insn (\"move%.l %1,%-\", operands);
-	  return \"fmove%.x %+,%0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-        return \"fmove%.x %1,%0\";
-      return \"fmove%.x %f1,%0\";
-    }
-  if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	{
-	  output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
-	  operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-	  output_asm_insn (\"move%.l %+,%0\", operands);
-	  operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-	  return \"move%.l %+,%0\";
-	}
-      /* Must be memory destination.  */
-      return \"fmove%.x %f1,%0\";
-    }
-  return output_move_double (operands);
-}
-")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
-	(match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
-  "! TARGET_68881 && ! TARGET_5200"
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"fmove%.x %1,%0\";
-      if (REG_P (operands[1]))
-	{
-	  rtx xoperands[2];
-	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
-	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
-	  output_asm_insn (\"move%.l %1,%-\", operands);
-	  return \"fmove%.x %+,%0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-        return \"fmove%.x %1,%0\";
-      return \"fmove%.x %f1,%0\";
-    }
-  if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-        {
-          output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
-          operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-          output_asm_insn (\"move%.l %+,%0\", operands);
-          operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-          return \"move%.l %+,%0\";
-        }
-      else
-        return \"fmove%.x %f1,%0\";
-    }
-  return output_move_double (operands);
-}
-")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
-	(match_operand:XF 1 "nonimmediate_operand" "g,r"))]
-  "! TARGET_68881 && TARGET_5200"
-  "* return output_move_double (operands);")
-
-(define_expand "movdi"
-  ;; Let's see if it really still needs to handle fp regs, and, if so, why.
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "")
-
-;; movdi can apply to fp regs in some cases
-(define_insn ""
-  ;; Let's see if it really still needs to handle fp regs, and, if so, why.
-  [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
-	(match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
-;  [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
-;	(match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
-;  [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
-;	(match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
-  "!TARGET_5200"
-  "*
-{
-  if (which_alternative == 8)
-    return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
-  if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
-    return \"fpmove%.d %x1,%x0\";
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"fmove%.x %1,%0\";
-      if (REG_P (operands[1]))
-	{
-	  rtx xoperands[2];
-	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"move%.l %1,%-\", xoperands);
-	  output_asm_insn (\"move%.l %1,%-\", operands);
-	  return \"fmove%.d %+,%0\";
-	}
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	return output_move_const_double (operands);
-      return \"fmove%.d %f1,%0\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	{
-	  output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
-	  operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-	  return \"move%.l %+,%0\";
-	}
-      else
-        return \"fmove%.d %f1,%0\";
-    }
-  return output_move_double (operands);
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=r,g")
-	(match_operand:DI 1 "general_operand" "g,r"))]
-  "TARGET_5200"
-  "* return output_move_double (operands);")
-
-;; Thus goes after the move instructions
-;; because the move instructions are better (require no spilling)
-;; when they can apply.  It goes before the add/sub insns
-;; so we will prefer it to them.
-
-(define_insn "pushasi"
-  [(set (match_operand:SI 0 "push_operand" "=m")
-	(match_operand:SI 1 "address_operand" "p"))]
-  ""
-  "pea %a1")
-
-;; truncation instructions
-(define_insn "truncsiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm,d")
-	(truncate:QI
-	 (match_operand:SI 1 "general_operand" "doJ,i")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == REG)
-    {
-      /* Must clear condition codes, since the move.l bases them on
-	 the entire 32 bits, not just the desired 8 bits.  */
-      CC_STATUS_INIT;
-      return \"move%.l %1,%0\";
-    }
-  if (GET_CODE (operands[1]) == MEM)
-    operands[1] = adj_offsettable_operand (operands[1], 3);
-  return \"move%.b %1,%0\";
-}")
-
-(define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm,d")
-	(truncate:QI
-	 (match_operand:HI 1 "general_operand" "doJ,i")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == REG
-      && (GET_CODE (operands[1]) == MEM
-	  || GET_CODE (operands[1]) == CONST_INT))
-    {
-      /* Must clear condition codes, since the move.w bases them on
-	 the entire 16 bits, not just the desired 8 bits.  */
-      CC_STATUS_INIT;
-      return \"move%.w %1,%0\";
-    }
-  if (GET_CODE (operands[0]) == REG)
-    {
-      /* Must clear condition codes, since the move.l bases them on
-	 the entire 32 bits, not just the desired 8 bits.  */
-      CC_STATUS_INIT;
-      return \"move%.l %1,%0\";
-    }
-  if (GET_CODE (operands[1]) == MEM)
-    operands[1] = adj_offsettable_operand (operands[1], 1);
-  return \"move%.b %1,%0\";
-}")
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "general_operand" "=dm,d")
-	(truncate:HI
-	 (match_operand:SI 1 "general_operand" "roJ,i")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == REG)
-    {
-      /* Must clear condition codes, since the move.l bases them on
-	 the entire 32 bits, not just the desired 8 bits.  */
-      CC_STATUS_INIT;
-      return \"move%.l %1,%0\";
-    }
-  if (GET_CODE (operands[1]) == MEM)
-    operands[1] = adj_offsettable_operand (operands[1], 2);
-  return \"move%.w %1,%0\";
-}")
-
-;; zero extension instructions
-
-(define_insn "zero_extendqidi2"
-  [(set (match_operand:DI 0 "general_operand" "=&d")
-	(zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
-}")
-
-(define_insn "zero_extendhidi2"
-  [(set (match_operand:DI 0 "general_operand" "=&d")
-	(zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
-}")
-
-;; this is the canonical form for (lshiftrt:DI x 32)
-(define_insn "zero_extendsidi2"
-  [(set (match_operand:DI 0 "general_operand" "rm")
-    (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[0]) == REG)
-    operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    return \"move%.l %1,%0\;clr%.l %0\";
-  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    return \"clr%.l %0\;move%.l %1,%0\";
-  else
-    operands[2] = adj_offsettable_operand (operands[0], 4);
-  if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
-      || REGNO (operands[1]) != REGNO (operands[2]))
-    output_asm_insn (\"move%.l %1,%2\", operands);
-  if (ADDRESS_REG_P (operands[0]))
-    return \"sub%.l %0,%0\";
-  else
-    return \"clr%.l %0\";
-}")
-
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(const_int 0))
-   (set (strict_low_part (match_dup 2))
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  operands[1] = make_safe_from (operands[1], operands[0]);
-  if (GET_CODE (operands[0]) == SUBREG)
-    operands[2] = gen_rtx_SUBREG (HImode, SUBREG_REG (operands[0]),
-				  SUBREG_WORD (operands[0]));
-  else
-    operands[2] = gen_rtx_SUBREG (HImode, operands[0], 0);
-}")
-
-(define_expand "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(const_int 0))
-   (set (strict_low_part (match_dup 2))
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  operands[1] = make_safe_from (operands[1], operands[0]);
-  if (GET_CODE (operands[0]) == SUBREG)
-    operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
-				  SUBREG_WORD (operands[0]));
-  else
-    operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
-}")
-
-(define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(const_int 0))
-   (set (strict_low_part (match_dup 2))
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  operands[1] = make_safe_from (operands[1], operands[0]);
-  if (GET_CODE (operands[0]) == SUBREG)
-    operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
-				  SUBREG_WORD (operands[0]));
-  else
-    operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
-}")
-
-;; Patterns to recognize zero-extend insns produced by the combiner.
-;; We don't allow both operands in memory, because of aliasing problems.
-;; Explicitly disallow two memory operands via the condition since reloading
-;; of this case will result in worse code than the uncombined patterns.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
-  "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
-  "*
-{
-  if (DATA_REG_P (operands[0]))
-    {
-      if (GET_CODE (operands[1]) == REG
-	  && REGNO (operands[0]) == REGNO (operands[1]))
-	return \"and%.l %#0xFFFF,%0\";
-      if (reg_mentioned_p (operands[0], operands[1]))
-        return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
-      return \"clr%.l %0\;move%.w %1,%0\";
-    }
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    return \"move%.w %1,%0\;clr%.w %0\";
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    return \"clr%.w %0\;move%.w %1,%0\";
-  else
-    {
-      output_asm_insn (\"clr%.w %0\", operands);
-      operands[0] = adj_offsettable_operand (operands[0], 2);
-      return \"move%.w %1,%0\";
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=do<>,d")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
-  "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
-  "*
-{
-  if (DATA_REG_P (operands[0]))
-    {
-      if (GET_CODE (operands[1]) == REG
-	  && REGNO (operands[0]) == REGNO (operands[1]))
-	return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
-      if (reg_mentioned_p (operands[0], operands[1]))
-	return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\" 
-			     : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
-      return \"clr%.w %0\;move%.b %1,%0\";
-    }
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    {
-      if (REGNO (XEXP (XEXP (operands[0], 0), 0))
-	  == STACK_POINTER_REGNUM)
-	{
-	  output_asm_insn (\"clr%.w %-\", operands);
-	  operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
-				     plus_constant (stack_pointer_rtx, 1));
-	  return \"move%.b %1,%0\";
-	}
-      else
-	return \"move%.b %1,%0\;clr%.b %0\";
-    }
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    return \"clr%.b %0\;move%.b %1,%0\";
-  else
-    {
-      output_asm_insn (\"clr%.b %0\", operands);
-      operands[0] = adj_offsettable_operand (operands[0], 1);
-      return \"move%.b %1,%0\";
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=do<>,d")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
-  "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
-  "*
-{
-  if (DATA_REG_P (operands[0]))
-    {
-      if (GET_CODE (operands[1]) == REG
-	  && REGNO (operands[0]) == REGNO (operands[1]))
-	return \"and%.l %#0xFF,%0\";
-      if (reg_mentioned_p (operands[0], operands[1]))
-        return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
-      return \"clr%.l %0\;move%.b %1,%0\";
-    }
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    {
-      operands[0] = XEXP (XEXP (operands[0], 0), 0);
-#ifdef MOTOROLA
-#ifdef SGS
-      return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
-#else
-      return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
-#endif
-#else
-      return \"clrl %0@-\;moveb %1,%0@(3)\";
-#endif
-    }
-  else if (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    {
-      operands[0] = XEXP (XEXP (operands[0], 0), 0);
-#ifdef MOTOROLA
-#ifdef SGS
-      return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
-#else
-      return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
-#endif
-#else
-      return \"clrl %0@+\;moveb %1,%0@(-1)\";
-#endif
-    }
-  else
-    {
-      output_asm_insn (\"clr%.l %0\", operands);
-      operands[0] = adj_offsettable_operand (operands[0], 3);
-      return \"move%.b %1,%0\";
-    }
-}")
-
-;; sign extension instructions
-
-(define_insn "extendqidi2"
-  [(set (match_operand:DI 0 "general_operand" "=d")
-	(sign_extend:DI
-	 (match_operand:QI 1 "general_operand" "rm")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (TARGET_68020 || TARGET_5200)
-    return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
-  else
-    return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
-}")
-
-(define_insn "extendhidi2"
-  [(set (match_operand:DI 0 "general_operand" "=d")
-	(sign_extend:DI
-	 (match_operand:HI 1 "general_operand" "rm")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (TARGET_68020 || TARGET_5200)
-    return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
-  else
-    return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
-}")
-
-(define_insn "extendsidi2"
-  [(set (match_operand:DI 0 "general_operand" "=d")
-	(sign_extend:DI
-	 (match_operand:SI 1 "general_operand" "rm")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (TARGET_68020 || TARGET_5200)
-    return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
-  else
-    return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
-}")
-
-;; Special case when one can avoid register clobbering, copy and test
-;; Maybe there is a way to make that the general case, by forcing the
-;; result of the SI tree to be in the lower register of the DI target
-
-(define_insn "extendplussidi"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-    (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
-            (match_operand:SI 2 "general_operand" "rmn"))))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (GET_CODE (operands[1]) == CONST_INT
-  && (unsigned) INTVAL (operands[1]) > 8)
-    {
-      rtx tmp = operands[1];
-
-      operands[1] = operands[2];
-      operands[2] = tmp;
-    }
-  if (GET_CODE (operands[1]) == REG
-      && REGNO (operands[1]) == REGNO (operands[3]))
-    output_asm_insn (\"add%.l %2,%3\", operands);
-  else
-    output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
-  if (TARGET_68020 || TARGET_5200)
-    return \"smi %0\;extb%.l %0\";
-  else
-    return \"smi %0\;ext%.w %0\;ext%.l %0\";
-}")
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=*d,a")
-	(sign_extend:SI
-	 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
-  ""
-  "*
-{
-  if (ADDRESS_REG_P (operands[0]))
-    return \"move%.w %1,%0\";
-  return \"ext%.l %0\";
-}")
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
-  ""
-  "ext%.w %0")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
-  "TARGET_68020 || TARGET_5200"
-  "extb%.l %0")
-
-;; Conversions between float and double.
-
-(define_expand "extendsfdf2"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(float_extend:DF
-	 (match_operand:SF 1 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=x,y")
-	(float_extend:DF
-	 (match_operand:SF 1 "general_operand" "xH,rmF")))]
-  "TARGET_FPA"
-  "fpstod %w1,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
-	(float_extend:DF
-	  (match_operand:SF 1 "general_operand" "f,dmF")))]
-  "TARGET_68881"
-  "*
-{
-  if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
-    {
-      if (REGNO (operands[0]) == REGNO (operands[1]))
-	{
-	  /* Extending float to double in an fp-reg is a no-op.
-	     NOTICE_UPDATE_CC has already assumed that the
-	     cc will be set.  So cancel what it did.  */
-	  cc_status = cc_prev_status;
-	  return \"\";
-	}
-      return \"f%&move%.x %1,%0\";
-    }
-  if (FP_REG_P (operands[0]))
-    return \"f%&move%.s %f1,%0\";
-  if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
-    {
-      output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
-      operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-      return \"move%.l %+,%0\";
-    }
-  return \"fmove%.d %f1,%0\";
-}")
-
-;; This cannot output into an f-reg because there is no way to be
-;; sure of truncating in that case.
-;; But on the Sun FPA, we can be sure.
-(define_expand "truncdfsf2"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(float_truncate:SF
-	  (match_operand:DF 1 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=x,y")
-	(float_truncate:SF
-	  (match_operand:DF 1 "general_operand" "xH,rmF")))]
-  "TARGET_FPA"
-  "fpdtos %y1,%0")
-
-;; On the '040 we can truncate in a register accurately and easily.
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(float_truncate:SF
-	  (match_operand:DF 1 "general_operand" "fmG")))]
-  "TARGET_68040_ONLY"
-  "*
-{
-  if (FP_REG_P (operands[1]))
-    return \"f%$move%.x %1,%0\";
-  return \"f%$move%.d %f1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=dm")
-	(float_truncate:SF
-	  (match_operand:DF 1 "general_operand" "f")))]
-  "TARGET_68881"
-  "fmove%.s %f1,%0")
-
-;; Conversion between fixed point and floating point.
-;; Note that among the fix-to-float insns
-;; the ones that start with SImode come first.
-;; That is so that an operand that is a CONST_INT
-;; (and therefore lacks a specific machine mode).
-;; will be recognized as SImode (which is always valid)
-;; rather than as QImode or HImode.
-
-(define_expand "floatsisf2"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(float:SF (match_operand:SI 1 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=y,x")
-	(float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
-  "TARGET_FPA"
-  "fpltos %1,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(float:SF (match_operand:SI 1 "general_operand" "dmi")))]
-  "TARGET_68881"
-  "f%$move%.l %1,%0")
-
-(define_expand "floatsidf2"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(float:DF (match_operand:SI 1 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=y,x")
-	(float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
-  "TARGET_FPA"
-  "fpltod %1,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(float:DF (match_operand:SI 1 "general_operand" "dmi")))]
-  "TARGET_68881"
-  "f%&move%.l %1,%0")
-
-(define_insn "floathisf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(float:SF (match_operand:HI 1 "general_operand" "dmn")))]
-  "TARGET_68881"
-  "f%$move%.w %1,%0")
-
-(define_insn "floathidf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(float:DF (match_operand:HI 1 "general_operand" "dmn")))]
-  "TARGET_68881"
-  "fmove%.w %1,%0")
-
-(define_insn "floatqisf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(float:SF (match_operand:QI 1 "general_operand" "dmn")))]
-  "TARGET_68881"
-  "fmove%.b %1,%0")
-
-(define_insn "floatqidf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(float:DF (match_operand:QI 1 "general_operand" "dmn")))]
-  "TARGET_68881"
-  "f%&move%.b %1,%0")
-
-;; New routines to convert floating-point values to integers
-;; to be used on the '040.  These should be faster than trapping
-;; into the kernel to emulate fintrz.  They should also be faster
-;; than calling the subroutines fixsfsi or fixdfsi.
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=dm")
-	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
-   (clobber (match_scratch:SI 2 "=d"))
-   (clobber (match_scratch:SI 3 "=d"))]
-  "TARGET_68881 && TARGET_68040"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
-}")
-
-(define_insn "fix_truncdfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=dm")
-	(fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
-   (clobber (match_scratch:SI 2 "=d"))
-   (clobber (match_scratch:SI 3 "=d"))]
-  "TARGET_68881 && TARGET_68040"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
-}")
-
-(define_insn "fix_truncdfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
-   (clobber (match_scratch:SI 2 "=d"))
-   (clobber (match_scratch:SI 3 "=d"))]
-  "TARGET_68881 && TARGET_68040"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
-}")
-
-;; Convert a float to a float whose value is an integer.
-;; This is the first stage of converting it to an integer type.
-
-(define_insn "ftruncdf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
-  "TARGET_68881 && !TARGET_68040"
-  "*
-{
-  if (FP_REG_P (operands[1]))
-    return \"fintrz%.x %f1,%0\";
-  return \"fintrz%.d %f1,%0\";
-}")
-
-(define_insn "ftruncsf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
-  "TARGET_68881 && !TARGET_68040"
-  "*
-{
-  if (FP_REG_P (operands[1]))
-    return \"fintrz%.x %f1,%0\";
-  return \"fintrz%.s %f1,%0\";
-}")
-
-;; Convert a float whose value is an integer
-;; to an actual integer.  Second stage of converting float to integer type.
-(define_insn "fixsfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(fix:QI (match_operand:SF 1 "general_operand" "f")))]
-  "TARGET_68881"
-  "fmove%.b %1,%0")
-
-(define_insn "fixsfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=dm")
-	(fix:HI (match_operand:SF 1 "general_operand" "f")))]
-  "TARGET_68881"
-  "fmove%.w %1,%0")
-
-(define_insn "fixsfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=dm")
-	(fix:SI (match_operand:SF 1 "general_operand" "f")))]
-  "TARGET_68881"
-  "fmove%.l %1,%0")
-
-(define_insn "fixdfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(fix:QI (match_operand:DF 1 "general_operand" "f")))]
-  "TARGET_68881"
-  "fmove%.b %1,%0")
-
-(define_insn "fixdfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=dm")
-	(fix:HI (match_operand:DF 1 "general_operand" "f")))]
-  "TARGET_68881"
-  "fmove%.w %1,%0")
-
-(define_insn "fixdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=dm")
-	(fix:SI (match_operand:DF 1 "general_operand" "f")))]
-  "TARGET_68881"
-  "fmove%.l %1,%0")
-
-;; Convert a float to an integer.
-;; On the Sun FPA, this is done in one step.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=x,y")
-	(fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
-  "TARGET_FPA"
-  "fpstol %w1,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=x,y")
-	(fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
-  "TARGET_FPA"
-  "fpdtol %y1,%0")
-
-;; add instructions
-
-(define_insn "adddi_lshrdi_63"
-  [(set (match_operand:DI 0 "general_operand" "=d")
-    (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
-            (const_int 63))
-        (match_dup 1)))
-   (clobber (match_scratch:SI 2 "=d"))]
-  ""
-  "*
-{
-  operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
-    return
-    \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
-  if (GET_CODE (operands[1]) == REG)
-    operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-  else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
-        || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
-    operands[4] = operands[1];
-  else
-    operands[4] = adj_offsettable_operand (operands[1], 4);
-  if (GET_CODE (operands[1]) == MEM
-   && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
-    output_asm_insn (\"move%.l %4,%3\", operands);
-  output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
-  if (TARGET_68020 || TARGET_5200)
-    output_asm_insn (\"extb%.l %2\", operands);
-  else
-    output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
-  if (GET_CODE (operands[1]) != MEM
-   || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
-    output_asm_insn (\"move%.l %4,%3\", operands);
-  return \"sub%.l %2,%3\;subx%.l %2,%0\";
-}")
-
-(define_insn "adddi_sexthishl32"
-  [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
-    (plus:DI (ashift:DI (sign_extend:DI
-          (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
-            (const_int 32))
-        (match_operand:DI 2 "general_operand" "0,0,0,0")))
-   (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
-  "!TARGET_5200"
-  "*
-{
-  CC_STATUS_INIT;
-  if (ADDRESS_REG_P (operands[0]))
-    return \"add%.w %1,%0\";
-  else if (ADDRESS_REG_P (operands[3]))
-    return \"move%.w %1,%3\;add%.l %3,%0\";
-  else
-    return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
-} ")
-
-(define_insn "adddi_dilshr32"
-  [(set (match_operand:DI 0 "general_operand" "=d,o")
-;;    (plus:DI (match_operand:DI 2 "general_operand" "%0")
-;;	(lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
-;;            (const_int 32))))]
-    (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,r")
-            (const_int 32))
-        (match_operand:DI 2 "general_operand" "0,0")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[0]) == REG)
-    operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  else
-    operands[2] = adj_offsettable_operand (operands[0], 4);
-  return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
-} ")
-
-(define_insn "adddi_dishl32"
-  [(set (match_operand:DI 0 "general_operand" "=r,o")
-;;    (plus:DI (match_operand:DI 2 "general_operand" "%0")
-;;	(ashift:DI (match_operand:DI 1 "general_operand" "ro")
-;;            (const_int 32))))]
-    (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,r")
-            (const_int 32))
-        (match_operand:DI 2 "general_operand" "0,0")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[1]) == REG)
-    operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-  else
-    operands[1] = adj_offsettable_operand (operands[1], 4);
-  return \"add%.l %1,%0\";
-} ")
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
-	(plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
-		 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
-   (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
-  ""
-  "*
-{
-  if (DATA_REG_P (operands[0]))
-    {
-      if (DATA_REG_P (operands[2]))
-	return \"add%.l %R2,%R0\;addx%.l %2,%0\";
-      else if (GET_CODE (operands[2]) == MEM
-	  && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
-	{
-	  return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
-	}
-      else
-	{
-	  rtx xoperands[2];
-	  if (GET_CODE (operands[2]) == REG)
-	    operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
-	  else if (GET_CODE (operands[2]) == CONST_DOUBLE)
-	    {
-	      operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
-	      operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
-	    }
-	  else if (GET_CODE (operands[2]) == CONST_INT)
-	    {
-	      operands[1] = operands[2];
-	      operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
-	    }
-	  else
-	    operands[1] = adj_offsettable_operand (operands[2], 4);
-	  xoperands[0] = operands[3];
-	  if (GET_CODE (operands[1]) == CONST_INT
-	      && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
-	    xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
-	  else
-	    xoperands[1] = operands[2];
-	  output_asm_insn (output_move_simode (xoperands), xoperands);
-	  if (GET_CODE (operands[1]) == CONST_INT)
-	    {
-	      if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
-		{
-#ifdef NO_ADDSUB_Q
-		  return \"add%.l %1,%R0\;addx%.l %3,%0\";
-#else
-		  return \"addq%.l %1,%R0\;addx%.l %3,%0\";
-#endif
-		}
-	      else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
-		{
-		  operands[1] = GEN_INT (-INTVAL (operands[1]));
-#ifdef NO_ADDSUB_Q
-		  return \"sub%.l %1,%R0\;subx%.l %3,%0\";
-#else
-		  return \"subq%.l %1,%R0\;subx%.l %3,%0\";
-#endif
-		}
-	    }
-	  return \"add%.l %1,%R0\;addx%.l %3,%0\";
-	}
-    }
-  else if (GET_CODE (operands[0]) == MEM)
-    {
-      if (GET_CODE (operands[2]) == MEM
-	  && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
-	return \"add%.l %2,%0\;addx%.l %2,%0\";
-      CC_STATUS_INIT;
-      if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-	{
-	  operands[1]
-	    = gen_rtx_MEM (SImode,
-			   gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
-					 GEN_INT (-8)));
-	  return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
-	}
-      else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-	{
-	  operands[1] = XEXP(operands[0], 0);
-	  return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
-	}
-      else
-	{
-	  operands[1] = adj_offsettable_operand (operands[0], 4);
-	  return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
-	}
-    }
-  else
-    abort ();
-} ")
-
-(define_insn "addsi_lshrsi_31"
-  [(set (match_operand:SI 0 "general_operand" "=dm")
-    (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
-            (const_int 31))
-        (match_dup 1)))]
-  ""
-  "*
-{
-  operands[2] = operands[0];
-  operands[3] = gen_label_rtx();
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-        operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
-      else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-        operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
-    }
-  output_asm_insn (\"move%.l %1,%0\", operands);
-#ifdef MOTOROLA
-  output_asm_insn (\"jbpl %l3\", operands);
-#else
-  output_asm_insn (\"jpl %l3\", operands);
-#endif
-#ifndef NO_ADDSUB_Q
-  output_asm_insn (\"addq%.l %#1,%2\", operands);
-#else
-  output_asm_insn (\"add%.l %#1,%2\", operands);
-#endif
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
-				CODE_LABEL_NUMBER (operands[3]));
-  return \"\";
-}")
-
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(plus:SI (match_operand:SI 1 "general_operand" "")
-		 (match_operand:SI 2 "general_operand" "")))]
-  ""
-  "")
-
-;; Note that the middle two alternatives are near-duplicates
-;; in order to handle insns generated by reload.
-;; This is needed since they are not themselves reloaded,
-;; so commutativity won't apply to them.
-(define_insn "*addsi3_internal"
-  [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
-	(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
-		 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
-  "! TARGET_5200"
-  "* return output_addsi3 (operands);")
-
-(define_insn "*addsi3_5200"
-  [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
-	(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
-		 (match_operand:SI 2 "general_operand" "d,rJK,a,mrIKLs")))]
-  "TARGET_5200"
-  "* return output_addsi3 (operands);")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=a")
-	(plus:SI (match_operand:SI 1 "general_operand" "0")
-		 (sign_extend:SI
-		  (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
-  "!TARGET_5200"
-  "add%.w %2,%0")
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "general_operand" "=m,r")
-	(plus:HI (match_operand:HI 1 "general_operand" "%0,0")
-		 (match_operand:HI 2 "general_operand" "dn,rmn")))]
-  "!TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-#ifndef NO_ADDSUB_Q
-      /* If the constant would be a negative number when interpreted as
-	 HImode, make it negative.  This is usually, but not always, done
-	 elsewhere in the compiler.  First check for constants out of range,
-	 which could confuse us.  */
-
-      if (INTVAL (operands[2]) >= 32768)
-	operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
-
-      if (INTVAL (operands[2]) > 0
-	  && INTVAL (operands[2]) <= 8)
-	return \"addq%.w %2,%0\";
-      if (INTVAL (operands[2]) < 0
-	  && INTVAL (operands[2]) >= -8)
-	{
-	  operands[2] = GEN_INT (-INTVAL (operands[2]));
-	  return \"subq%.w %2,%0\";
-	}
-      /* On the CPU32 it is faster to use two addqw instructions to
-	 add a small integer (8 < N <= 16) to a register.  
-	 Likewise for subqw. */
-      if (TARGET_CPU32 && REG_P (operands[0]))
-	{
-	  if (INTVAL (operands[2]) > 8
-	      && INTVAL (operands[2]) <= 16)
-	    {
-	      operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-	      return \"addq%.w %#8,%0\;addq%.w %2,%0\";
-	    }
-	  if (INTVAL (operands[2]) < -8
-	      && INTVAL (operands[2]) >= -16)
-	    {
-	      operands[2] = GEN_INT (-INTVAL (operands[2]) - 8);
-	      return \"subq%.w %#8,%0\;subq%.w %2,%0\";
-	    }
-	}
-#endif
-      if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
-#ifdef MOTOROLA  
-	    return \"lea (%c2,%0),%0\";
-#else
-	    return \"lea %0@(%c2),%0\";
-#endif
-    }
-  return \"add%.w %2,%0\";
-}")
-
-;; These insns must use MATCH_DUP instead of the more expected
-;; use of a matching constraint because the "output" here is also
-;; an input, so you can't use the matching constraint.  That also means
-;; that you can't use the "%", so you need patterns with the matched
-;; operand in both positions.
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
-	(plus:HI (match_dup 0)
-		 (match_operand:HI 1 "general_operand" "dn,rmn")))]
-  "!TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-#ifndef NO_ADDSUB_Q
-      /* If the constant would be a negative number when interpreted as
-	 HImode, make it negative.  This is usually, but not always, done
-	 elsewhere in the compiler.  First check for constants out of range,
-	 which could confuse us.  */
-
-      if (INTVAL (operands[1]) >= 32768)
-	operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
-
-      if (INTVAL (operands[1]) > 0
-	  && INTVAL (operands[1]) <= 8)
-	return \"addq%.w %1,%0\";
-      if (INTVAL (operands[1]) < 0
-	  && INTVAL (operands[1]) >= -8)
-	{
-	  operands[1] = GEN_INT (-INTVAL (operands[1]));
-	  return \"subq%.w %1,%0\";
-	}
-      /* On the CPU32 it is faster to use two addqw instructions to
-	 add a small integer (8 < N <= 16) to a register. 
-	 Likewise for subqw. */
-      if (TARGET_CPU32 && REG_P (operands[0]))
-	{
-	  if (INTVAL (operands[1]) > 8
-	      && INTVAL (operands[1]) <= 16)
-	    {
-	      operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
-	      return \"addq%.w %#8,%0\;addq%.w %1,%0\";
-	    }
-	  if (INTVAL (operands[1]) < -8
-	      && INTVAL (operands[1]) >= -16)
-	    {
-	      operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
-	      return \"subq%.w %#8,%0\;subq%.w %1,%0\";
-	    }
-	}
-#endif
-      if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
-#ifdef MOTOROLA  
-	    return \"lea (%c1,%0),%0\";
-#else
-	    return \"lea %0@(%c1),%0\";
-#endif
-    }
-  return \"add%.w %1,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
-	(plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
-		 (match_dup 0)))]
-  "!TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-#ifndef NO_ADDSUB_Q
-      /* If the constant would be a negative number when interpreted as
-	 HImode, make it negative.  This is usually, but not always, done
-	 elsewhere in the compiler.  First check for constants out of range,
-	 which could confuse us.  */
-
-      if (INTVAL (operands[1]) >= 32768)
-	operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
-
-      if (INTVAL (operands[1]) > 0
-	  && INTVAL (operands[1]) <= 8)
-	return \"addq%.w %1,%0\";
-      if (INTVAL (operands[1]) < 0
-	  && INTVAL (operands[1]) >= -8)
-	{
-	  operands[1] = GEN_INT (-INTVAL (operands[1]));
-	  return \"subq%.w %1,%0\";
-	}
-      /* On the CPU32 it is faster to use two addqw instructions to
-	 add a small integer (8 < N <= 16) to a register.
-	 Likewise for subqw. */
-      if (TARGET_CPU32 && REG_P (operands[0])) 
-	{
-	  if (INTVAL (operands[1]) > 8
-	      && INTVAL (operands[1]) <= 16)
-	    {
-	      operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
-	      return \"addq%.w %#8,%0\;addq%.w %1,%0\";
-	    }
-	  if (INTVAL (operands[1]) < -8
-	      && INTVAL (operands[1]) >= -16)
-	    {
-	      operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
-	      return \"subq%.w %#8,%0\;subq%.w %1,%0\";
-	    }
-	}
-#endif
-      if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
-#ifdef MOTOROLA  
-	    return \"lea (%c1,%0),%0\";
-#else
-	    return \"lea %0@(%c1),%0\";
-#endif
-    }
-  return \"add%.w %1,%0\";
-}")
-
-(define_insn "addqi3"
-  [(set (match_operand:QI 0 "general_operand" "=m,d")
-	(plus:QI (match_operand:QI 1 "general_operand" "%0,0")
-		 (match_operand:QI 2 "general_operand" "dn,dmn")))]
-  "!TARGET_5200"
-  "*
-{
-#ifndef NO_ADDSUB_Q
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) >= 128)
-	operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
-
-      if (INTVAL (operands[2]) > 0
-	  && INTVAL (operands[2]) <= 8)
-	return \"addq%.b %2,%0\";
-      if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
-       {
-	 operands[2] = GEN_INT (-INTVAL (operands[2]));
-	 return \"subq%.b %2,%0\";
-       }
-    }
-#endif
-  return \"add%.b %2,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
-	(plus:QI (match_dup 0)
-		 (match_operand:QI 1 "general_operand" "dn,dmn")))]
-  "!TARGET_5200"
-  "*
-{
-#ifndef NO_ADDSUB_Q
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      if (INTVAL (operands[1]) >= 128)
-	operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
-
-      if (INTVAL (operands[1]) > 0
-	  && INTVAL (operands[1]) <= 8)
-	return \"addq%.b %1,%0\";
-      if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
-       {
-	 operands[1] = GEN_INT (-INTVAL (operands[1]));
-	 return \"subq%.b %1,%0\";
-       }
-    }
-#endif
-  return \"add%.b %1,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
-	(plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
-		 (match_dup 0)))]
-  "!TARGET_5200"
-  "*
-{
-#ifndef NO_ADDSUB_Q
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      if (INTVAL (operands[1]) >= 128)
-	operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
-
-      if (INTVAL (operands[1]) > 0
-	  && INTVAL (operands[1]) <= 8)
-	return \"addq%.b %1,%0\";
-      if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
-       {
-	 operands[1] = GEN_INT (-INTVAL (operands[1]));
-	 return \"subq%.b %1,%0\";
-       }
-    }
-#endif
-  return \"add%.b %1,%0\";
-}")
-
-(define_expand "adddf3"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(plus:DF (match_operand:DF 1 "general_operand" "")
-		 (match_operand:DF 2 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=x,y")
-	(plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
-		 (match_operand:DF 2 "general_operand" "xH,dmF")))]
-  "TARGET_FPA"
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"fpadd%.d %y2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"fpadd%.d %y1,%0\";
-  if (which_alternative == 0)
-    return \"fpadd3%.d %w2,%w1,%0\";
-  return \"fpadd3%.d %x2,%x1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
-		 (match_operand:DF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "f%&add%.l %2,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
-		 (match_operand:DF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "f%&add%.w %2,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
-		 (match_operand:DF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "f%&add%.b %2,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(plus:DF (match_operand:DF 1 "general_operand" "%0")
-		 (match_operand:DF 2 "general_operand" "fmG")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[2]))
-    return \"f%&add%.x %2,%0\";
-  return \"f%&add%.d %f2,%0\";
-}")
-
-(define_expand "addsf3"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(plus:SF (match_operand:SF 1 "general_operand" "")
-		 (match_operand:SF 2 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=x,y")
-	(plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
-		 (match_operand:SF 2 "general_operand" "xH,rmF")))]
-  "TARGET_FPA"
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"fpadd%.s %w2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"fpadd%.s %w1,%0\";
-  if (which_alternative == 0)
-    return \"fpadd3%.s %w2,%w1,%0\";
-  return \"fpadd3%.s %2,%1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
-		 (match_operand:SF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "f%$add%.l %2,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
-		 (match_operand:SF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "f%$add%.w %2,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
-		 (match_operand:SF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "f%$add%.b %2,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(plus:SF (match_operand:SF 1 "general_operand" "%0")
-		 (match_operand:SF 2 "general_operand" "fdmF")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
-    return \"f%$add%.x %2,%0\";
-  return \"f%$add%.s %f2,%0\";
-}")
-
-;; subtract instructions
-
-(define_insn "subdi_sexthishl32"
-  [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
-    (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
-        (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
-            (const_int 32))))
-   (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
-  "!TARGET_5200"
-  "*
-{
-  CC_STATUS_INIT;
-  if (ADDRESS_REG_P (operands[0]))
-    return \"sub%.w %2,%0\";
-  else if (ADDRESS_REG_P (operands[3]))
-    return \"move%.w %2,%3\;sub%.l %3,%0\";
-  else
-    return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
-} ")
-
-(define_insn "subdi_dishl32"
-  [(set (match_operand:DI 0 "general_operand" "+ro")
-    (minus:DI (match_dup 0)
-        (ashift:DI (match_operand:DI 1 "general_operand" "ro")
-            (const_int 32))))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[1]) == REG)
-    operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-  else
-    operands[1] = adj_offsettable_operand (operands[1], 4);
-  return \"sub%.l %1,%0\";
-} ")
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
-	(minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
-		 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
-   (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
-  ""
-  "*
-{
-  if (DATA_REG_P (operands[0]))
-    {
-      if (DATA_REG_P (operands[2]))
-	return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
-      else if (GET_CODE (operands[2]) == MEM
-	  && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
-	{
-	  return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
-	}
-      else
-	{
-	  rtx xoperands[2];
-	  if (GET_CODE (operands[2]) == REG)
-	    operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
-	  else if (GET_CODE (operands[2]) == CONST_DOUBLE)
-	    {
-	      operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
-	      operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
-	    }
-	  else if (GET_CODE (operands[2]) == CONST_INT)
-	    {
-	      operands[1] = operands[2];
-	      operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
-	    }
-	  else
-	    operands[1] = adj_offsettable_operand (operands[2], 4);
-	  xoperands[0] = operands[3];
-	  if (GET_CODE (operands[1]) == CONST_INT
-	      && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
-	    xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
-	  else
-	    xoperands[1] = operands[2];
-	  output_asm_insn (output_move_simode (xoperands), xoperands);
-	  if (GET_CODE (operands[1]) == CONST_INT)
-	    {
-	      if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
-		{
-#ifdef NO_ADDSUB_Q
-		  return \"sub%.l %1,%R0\;subx%.l %3,%0\";
-#else
-		  return \"subq%.l %1,%R0\;subx%.l %3,%0\";
-#endif
-		}
-	      else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
-		{
-		  operands[1] = GEN_INT (-INTVAL (operands[1]));
-#ifdef NO_ADDSUB_Q
-		  return \"add%.l %1,%R0\;addx%.l %3,%0\";
-#else
-		  return \"addq%.l %1,%R0\;addx%.l %3,%0\";
-#endif
-		}
-	    }
-	  return \"sub%.l %1,%R0\;subx%.l %3,%0\";
-	}
-    }
-  else if (GET_CODE (operands[0]) == MEM)
-    {
-      if (GET_CODE (operands[2]) == MEM
-	  && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
-	return \"sub%.l %2,%0\;subx%.l %2,%0\";
-      CC_STATUS_INIT;
-      if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-	{
-	  operands[1]
-	    = gen_rtx_MEM (SImode,
-			   gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
-					 GEN_INT (-8)));
-	  return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
-	}
-      else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-	{
-	  operands[1] = XEXP(operands[0], 0);
-	  return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
-	}
-      else
-	{
-	  operands[1] = adj_offsettable_operand (operands[0], 4);
-	  return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
-	}
-    }
-  else
-    abort ();
-} ")
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "general_operand" "=m,r")
-	(minus:SI (match_operand:SI 1 "general_operand" "0,0")
-		  (match_operand:SI 2 "general_operand" "ds,mrs")))]
-  ""
-  "sub%.l %2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=a")
-	(minus:SI (match_operand:SI 1 "general_operand" "0")
-		  (sign_extend:SI
-		   (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
-  "!TARGET_5200"
-  "sub%.w %2,%0")
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "general_operand" "=m,r")
-	(minus:HI (match_operand:HI 1 "general_operand" "0,0")
-		  (match_operand:HI 2 "general_operand" "dn,rmn")))]
-  "!TARGET_5200"
-  "sub%.w %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
-	(minus:HI (match_dup 0)
-		  (match_operand:HI 1 "general_operand" "dn,rmn")))]
-  "!TARGET_5200"
-  "sub%.w %1,%0")
-
-(define_insn "subqi3"
-  [(set (match_operand:QI 0 "general_operand" "=m,d")
-	(minus:QI (match_operand:QI 1 "general_operand" "0,0")
-		  (match_operand:QI 2 "general_operand" "dn,dmn")))]
-  "!TARGET_5200"
-  "sub%.b %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
-	(minus:QI (match_dup 0)
-		  (match_operand:QI 1 "general_operand" "dn,dmn")))]
-  "!TARGET_5200"
-  "sub%.b %1,%0")
-
-(define_expand "subdf3"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(minus:DF (match_operand:DF 1 "general_operand" "")
-		  (match_operand:DF 2 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=x,y,y")
-	(minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
-		  (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
-  "TARGET_FPA"
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"fprsub%.d %y1,%0\";
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"fpsub%.d %y2,%0\";
-  if (which_alternative == 0)
-    return \"fpsub3%.d %w2,%w1,%0\";
-  return \"fpsub3%.d %x2,%x1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(minus:DF (match_operand:DF 1 "general_operand" "0")
-		  (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
-  "TARGET_68881"
-  "f%&sub%.l %2,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(minus:DF (match_operand:DF 1 "general_operand" "0")
-		  (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
-  "TARGET_68881"
-  "f%&sub%.w %2,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(minus:DF (match_operand:DF 1 "general_operand" "0")
-		  (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
-  "TARGET_68881"
-  "f%&sub%.b %2,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(minus:DF (match_operand:DF 1 "general_operand" "0")
-		  (match_operand:DF 2 "general_operand" "fmG")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[2]))
-    return \"f%&sub%.x %2,%0\";
-  return \"f%&sub%.d %f2,%0\";
-}")
-
-(define_expand "subsf3"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(minus:SF (match_operand:SF 1 "general_operand" "")
-		  (match_operand:SF 2 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=x,y,y")
-	(minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
-		  (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
-  "TARGET_FPA"
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"fprsub%.s %w1,%0\";
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"fpsub%.s %w2,%0\";
-  if (which_alternative == 0)
-    return \"fpsub3%.s %w2,%w1,%0\";
-  return \"fpsub3%.s %2,%1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(minus:SF (match_operand:SF 1 "general_operand" "0")
-		  (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
-  "TARGET_68881"
-  "f%$sub%.l %2,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(minus:SF (match_operand:SF 1 "general_operand" "0")
-		  (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
-  "TARGET_68881"
-  "f%$sub%.w %2,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(minus:SF (match_operand:SF 1 "general_operand" "0")
-		  (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
-  "TARGET_68881"
-  "f%$sub%.b %2,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(minus:SF (match_operand:SF 1 "general_operand" "0")
-		  (match_operand:SF 2 "general_operand" "fdmF")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
-    return \"f%$sub%.x %2,%0\";
-  return \"f%$sub%.s %f2,%0\";
-}")
-
-;; multiply instructions
-
-(define_insn "mulhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(mult:HI (match_operand:HI 1 "general_operand" "%0")
-		 (match_operand:HI 2 "general_operand" "dmn")))]
-  ""
-  "*
-{
-#if defined(MOTOROLA) && !defined(CRDS)
-  return \"muls%.w %2,%0\";
-#else
-  return \"muls %2,%0\";
-#endif
-}")
-
-(define_insn "mulhisi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(mult:SI (sign_extend:SI
-		  (match_operand:HI 1 "nonimmediate_operand" "%0"))
-		 (sign_extend:SI
-		  (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
-  ""
-  "*
-{
-#if defined(MOTOROLA) && !defined(CRDS)
-  return \"muls%.w %2,%0\";
-#else
-  return \"muls %2,%0\";
-#endif
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(mult:SI (sign_extend:SI
-		  (match_operand:HI 1 "nonimmediate_operand" "%0"))
-		 (match_operand:SI 2 "const_int_operand" "n")))]
-  "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
-  "*
-{
-#if defined(MOTOROLA) && !defined(CRDS)
-  return \"muls%.w %2,%0\";
-#else
-  return \"muls %2,%0\";
-#endif
-}")
-
-(define_expand "mulsi3"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(mult:SI (match_operand:SI 1 "general_operand" "")
-		 (match_operand:SI 2 "general_operand" "")))]
-  "TARGET_68020 || TARGET_5200"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(mult:SI (match_operand:SI 1 "general_operand" "%0")
-		 (match_operand:SI 2 "general_operand" "dmsK")))]
-  "TARGET_68020"
-  "muls%.l %2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(mult:SI (match_operand:SI 1 "general_operand" "%0")
-		 (match_operand:SI 2 "general_operand" "d<Q>")))]
-  "TARGET_5200"
-  "muls%.l %2,%0")
-
-(define_insn "umulhisi3"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(mult:SI (zero_extend:SI
-		  (match_operand:HI 1 "nonimmediate_operand" "%0"))
-		 (zero_extend:SI
-		  (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
-  ""
-  "*
-{
-#if defined(MOTOROLA) && !defined(CRDS)
-  return \"mulu%.w %2,%0\";
-#else
-  return \"mulu %2,%0\";
-#endif
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(mult:SI (zero_extend:SI
-		  (match_operand:HI 1 "nonimmediate_operand" "%0"))
-		 (match_operand:SI 2 "const_int_operand" "n")))]
-  "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
-  "*
-{
-#if defined(MOTOROLA) && !defined(CRDS)
-  return \"mulu%.w %2,%0\";
-#else
-  return \"mulu %2,%0\";
-#endif
-}")
-
-;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
-;; proper matching constraint.  This is because the matching is between
-;; the high-numbered word of the DImode operand[0] and operand[1].
-(define_expand "umulsidi3"
-  [(parallel
-    [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
-	  (mult:SI (match_operand:SI 1 "register_operand" "")
-		   (match_operand:SI 2 "nonimmediate_operand" "")))
-     (set (subreg:SI (match_dup 0) 0)
-	  (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
-					     (zero_extend:DI (match_dup 2)))
-				    (const_int 32))))])]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(mult:SI (match_operand:SI 1 "register_operand" "%0")
-		  (match_operand:SI 2 "nonimmediate_operand" "dm")))
-   (set (match_operand:SI 3 "register_operand" "=d")
-	(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
-					   (zero_extend:DI (match_dup 2)))
-				  (const_int 32))))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
-  "mulu%.l %2,%3:%0")
-
-; Match immediate case.  For 2.4 only match things < 2^31.
-; It's tricky with larger values in these patterns since we need to match
-; values between the two parallel multiplies, between a CONST_DOUBLE and
-; a CONST_INT.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(mult:SI (match_operand:SI 1 "register_operand" "%0")
-		 (match_operand:SI 2 "const_int_operand" "n")))
-   (set (match_operand:SI 3 "register_operand" "=d")
-	(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
-					   (match_dup 2))
-				  (const_int 32))))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200
-   && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
-  "mulu%.l %2,%3:%0")
-
-(define_expand "mulsidi3"
-  [(parallel
-    [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
-	  (mult:SI (match_operand:SI 1 "register_operand" "")
-		   (match_operand:SI 2 "nonimmediate_operand" "")))
-     (set (subreg:SI (match_dup 0) 0)
-	  (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
-					     (sign_extend:DI (match_dup 2)))
-				    (const_int 32))))])]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(mult:SI (match_operand:SI 1 "register_operand" "%0")
-		 (match_operand:SI 2 "nonimmediate_operand" "dm")))
-   (set (match_operand:SI 3 "register_operand" "=d")
-	(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
-					   (sign_extend:DI (match_dup 2)))
-				  (const_int 32))))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
-  "muls%.l %2,%3:%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(mult:SI (match_operand:SI 1 "register_operand" "%0")
-		 (match_operand:SI 2 "const_sint32_operand" "")))
-   (set (match_operand:SI 3 "register_operand" "=d")
-	(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
-					   (match_dup 2))
-				  (const_int 32))))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
-  "muls%.l %2,%3:%0")
-
-(define_expand "umulsi3_highpart"
-  [(parallel
-    [(set (match_operand:SI 0 "register_operand" "")
-	  (truncate:SI
-	   (lshiftrt:DI
-	    (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
-		     (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
-	    (const_int 32))))
-     (clobber (match_dup 3))])]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
-  "
-{
-  operands[3] = gen_reg_rtx (SImode);
-  if (GET_CODE (operands[2]) == CONST_INT
-      || GET_CODE (operands[2]) == CONST_DOUBLE)
-    {
-      if (! const_uint32_operand (operands[2], VOIDmode))
-	abort ();
-      /* We have to adjust the operand order for the matching constraints.  */
-      emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
-					     operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI
-	 (lshiftrt:DI
-	  (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
-		   (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
-	  (const_int 32))))
-   (clobber (match_operand:SI 1 "register_operand" "=d"))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
-  "mulu%.l %3,%0:%1")
-
-(define_insn "const_umulsi3_highpart"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI
-	 (lshiftrt:DI
-	  (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
-		   (match_operand 3 "const_uint32_operand" ""))
-	  (const_int 32))))
-   (clobber (match_operand:SI 1 "register_operand" "=d"))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
-  "mulu%.l %3,%0:%1")
-
-(define_expand "smulsi3_highpart"
-  [(parallel
-    [(set (match_operand:SI 0 "register_operand" "")
-	  (truncate:SI
-	   (lshiftrt:DI
-	    (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
-		     (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
-	    (const_int 32))))
-     (clobber (match_dup 3))])]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
-  "
-{
-  operands[3] = gen_reg_rtx (SImode);
-  if (GET_CODE (operands[2]) == CONST_INT
-      || GET_CODE (operands[2]) == CONST_DOUBLE)
-    {
-      if (! const_sint32_operand (operands[2], VOIDmode))
-	abort ();
-      /* We have to adjust the operand order for the matching constraints.  */
-      emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
-					     operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI
-	 (lshiftrt:DI
-	  (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
-		   (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
-	  (const_int 32))))
-   (clobber (match_operand:SI 1 "register_operand" "=d"))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
-  "muls%.l %3,%0:%1")
-
-(define_insn "const_smulsi3_highpart"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI
-	 (lshiftrt:DI
-	  (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
-		   (match_operand 3 "const_sint32_operand" ""))
-	  (const_int 32))))
-   (clobber (match_operand:SI 1 "register_operand" "=d"))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
-  "muls%.l %3,%0:%1")
-
-(define_expand "muldf3"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(mult:DF (match_operand:DF 1 "general_operand" "")
-		 (match_operand:DF 2 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=x,y")
-	(mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
-		 (match_operand:DF 2 "general_operand" "xH,rmF")))]
-  "TARGET_FPA"
-  "*
-{
-  if (rtx_equal_p (operands[1], operands[2]))
-    return \"fpsqr%.d %y1,%0\";
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"fpmul%.d %y2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"fpmul%.d %y1,%0\";
-  if (which_alternative == 0)
-    return \"fpmul3%.d %w2,%w1,%0\";
-  return \"fpmul3%.d %x2,%x1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
-		 (match_operand:DF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "f%&mul%.l %2,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
-		 (match_operand:DF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "f%&mul%.w %2,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
-		 (match_operand:DF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "f%&mul%.b %2,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(mult:DF (match_operand:DF 1 "general_operand" "%0")
-		 (match_operand:DF 2 "general_operand" "fmG")))]
-  "TARGET_68881"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_DOUBLE
-      && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
-    {
-      int i = floating_exact_log2 (operands[2]);
-      operands[2] = GEN_INT (i);
-      return \"fscale%.l %2,%0\";
-    }
-  if (REG_P (operands[2]))
-    return \"f%&mul%.x %2,%0\";
-  return \"f%&mul%.d %f2,%0\";
-}")
-
-(define_expand "mulsf3"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(mult:SF (match_operand:SF 1 "general_operand" "")
-		 (match_operand:SF 2 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=x,y")
-	(mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
-		 (match_operand:SF 2 "general_operand" "xH,rmF")))]
-  "TARGET_FPA"
-  "*
-{
-  if (rtx_equal_p (operands[1], operands[2]))
-    return \"fpsqr%.s %w1,%0\";
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"fpmul%.s %w2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"fpmul%.s %w1,%0\";
-  if (which_alternative == 0)
-    return \"fpmul3%.s %w2,%w1,%0\";
-  return \"fpmul3%.s %2,%1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
-		 (match_operand:SF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "*
-{
-  return (TARGET_68040_ONLY
-          ? \"fsmul%.l %2,%0\"
-          : \"fsglmul%.l %2,%0\");
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
-		 (match_operand:SF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "*
-{
-  return (TARGET_68040_ONLY
-          ? \"fsmul%.w %2,%0\"
-          : \"fsglmul%.w %2,%0\");
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
-		 (match_operand:SF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "*
-{
-  return (TARGET_68040_ONLY
-          ? \"fsmul%.b %2,%0\"
-          : \"fsglmul%.b %2,%0\");
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(mult:SF (match_operand:SF 1 "general_operand" "%0")
-		 (match_operand:SF 2 "general_operand" "fdmF")))]
-  "TARGET_68881"
-  "*
-{
-#ifdef FSGLMUL_USE_S
-  if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
-    return (TARGET_68040_ONLY
-	    ? \"fsmul%.s %2,%0\"
-	    : \"fsglmul%.s %2,%0\");
-#else
-  if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
-    return (TARGET_68040_ONLY
-	    ? \"fsmul%.x %2,%0\"
-	    : \"fsglmul%.x %2,%0\");
-#endif
-  return (TARGET_68040_ONLY
-	  ? \"fsmul%.s %f2,%0\"
-	  : \"fsglmul%.s %f2,%0\");
-}")
-
-;; divide instructions
-
-(define_expand "divdf3"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(div:DF (match_operand:DF 1 "general_operand" "")
-		(match_operand:DF 2 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=x,y,y")
-	(div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
-		(match_operand:DF 2 "general_operand" "xH,rmF,0")))]
-  "TARGET_FPA"
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"fprdiv%.d %y1,%0\";
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"fpdiv%.d %y2,%0\";
-  if (which_alternative == 0)
-    return \"fpdiv3%.d %w2,%w1,%0\";
-  return \"fpdiv3%.d %x2,%x1,%x0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(div:DF (match_operand:DF 1 "general_operand" "0")
-		(float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
-  "TARGET_68881"
-  "f%&div%.l %2,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(div:DF (match_operand:DF 1 "general_operand" "0")
-		(float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
-  "TARGET_68881"
-  "f%&div%.w %2,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(div:DF (match_operand:DF 1 "general_operand" "0")
-		(float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
-  "TARGET_68881"
-  "f%&div%.b %2,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(div:DF (match_operand:DF 1 "general_operand" "0")
-		(match_operand:DF 2 "general_operand" "fmG")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[2]))
-    return \"f%&div%.x %2,%0\";
-  return \"f%&div%.d %f2,%0\";
-}")
-
-(define_expand "divsf3"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(div:SF (match_operand:SF 1 "general_operand" "")
-		(match_operand:SF 2 "general_operand" "")))]
-  "TARGET_68881 || TARGET_FPA"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=x,y,y")
-	(div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
-		(match_operand:SF 2 "general_operand" "xH,rmF,0")))]
-  "TARGET_FPA"
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"fpdiv%.s %w2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"fprdiv%.s %w1,%0\";
-  if (which_alternative == 0)
-    return \"fpdiv3%.s %w2,%w1,%0\";
-  return \"fpdiv3%.s %2,%1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(div:SF (match_operand:SF 1 "general_operand" "0")
-		(float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
-  "TARGET_68881"
-  "*
-{
-  return (TARGET_68040_ONLY
-          ? \"fsdiv%.l %2,%0\"
-          : \"fsgldiv%.l %2,%0\");
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(div:SF (match_operand:SF 1 "general_operand" "0")
-		(float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
-  "TARGET_68881"
-  "*
-{
-  return (TARGET_68040_ONLY
-          ? \"fsdiv%.w %2,%0\"
-          : \"fsgldiv%.w %2,%0\");
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(div:SF (match_operand:SF 1 "general_operand" "0")
-		(float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
-  "TARGET_68881"
-  "*
-{
-  return (TARGET_68040_ONLY
-          ? \"fsdiv%.b %2,%0\"
-          : \"fsgldiv%.b %2,%0\");
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(div:SF (match_operand:SF 1 "general_operand" "0")
-		(match_operand:SF 2 "general_operand" "fdmF")))]
-  "TARGET_68881"
-  "*
-{
-#ifdef FSGLDIV_USE_S
-  if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
-    return (TARGET_68040_ONLY
-	    ? \"fsdiv%.s %2,%0\"
-	    : \"fsgldiv%.s %2,%0\");
-#else
-  if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
-    return (TARGET_68040_ONLY
-	    ? \"fsdiv%.x %2,%0\"
-	    : \"fsgldiv%.x %2,%0\");
-#endif
-  return (TARGET_68040_ONLY
-	  ? \"fsdiv%.s %f2,%0\"
-	  : \"fsgldiv%.s %f2,%0\");
-}")
-
-;; Remainder instructions.
-
-(define_insn "divmodsi4"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(div:SI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:SI 2 "general_operand" "dmsK")))
-   (set (match_operand:SI 3 "general_operand" "=d")
-	(mod:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_68020 && !TARGET_5200"
-  "*
-{
-  if (find_reg_note (insn, REG_UNUSED, operands[3]))
-    return \"divs%.l %2,%0\";
-  else
-    return \"divsl%.l %2,%3:%0\";
-}")
-
-(define_insn "udivmodsi4"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(udiv:SI (match_operand:SI 1 "general_operand" "0")
-		 (match_operand:SI 2 "general_operand" "dmsK")))
-   (set (match_operand:SI 3 "general_operand" "=d")
-	(umod:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_68020 && !TARGET_5200"
-  "*
-{
-  if (find_reg_note (insn, REG_UNUSED, operands[3]))
-    return \"divu%.l %2,%0\";
-  else
-    return \"divul%.l %2,%3:%0\";
-}")
-
-(define_insn "divmodhi4"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(div:HI (match_operand:HI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "dmsK")))
-   (set (match_operand:HI 3 "general_operand" "=d")
-	(mod:HI (match_dup 1) (match_dup 2)))]
-  "!TARGET_5200"
-  "*
-{
-#ifdef MOTOROLA
-  output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
-#else
-  output_asm_insn (\"extl %0\;divs %2,%0\", operands);
-#endif
-  if (!find_reg_note(insn, REG_UNUSED, operands[3]))
-    {
-      CC_STATUS_INIT;
-      return \"move%.l %0,%3\;swap %3\";
-    }
-  else
-    return \"\";
-}")
-
-(define_insn "udivmodhi4"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(udiv:HI (match_operand:HI 1 "general_operand" "0")
-		 (match_operand:HI 2 "general_operand" "dmsK")))
-   (set (match_operand:HI 3 "general_operand" "=d")
-	(umod:HI (match_dup 1) (match_dup 2)))]
-  "!TARGET_5200"
-  "*
-{
-#ifdef MOTOROLA
-  output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
-#else
-  output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
-#endif
-  if (!find_reg_note(insn, REG_UNUSED, operands[3]))
-    {
-      CC_STATUS_INIT;
-      return \"move%.l %0,%3\;swap %3\";
-    }
-  else
-    return \"\";
-}")
-
-;; logical-and instructions
-
-;; "anddi3" is mainly here to help combine().
-(define_insn "anddi3"
-  [(set (match_operand:DI 0 "general_operand" "=o,d")
-	(and:DI (match_operand:DI 1 "general_operand" "%0,0")
-		(match_operand:DI 2 "general_operand" "dn,don")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  /* We can get CONST_DOUBLE, but also const1_rtx etc. */
-  if (GET_CODE (operands[2]) == CONST_DOUBLE
-     || GET_CODE (operands[2]) == CONST_INT)
-    {
-      rtx hi, lo;
-
-      if (GET_CODE (operands[2]) == CONST_DOUBLE)
-	{
-	  hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
-	  lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
-	}
-      else
-	{
-	  lo = operands[2];
-	  hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
-	}
-      switch (INTVAL (hi))
-	{
-	  case 0 :
-	    output_asm_insn (\"clr%.l %0\", operands);
-	    break;
-	  case -1 :
-	    break;
-	  default :
-	    {
-	    rtx xoperands[3];
-
-	    xoperands[0] = operands[0];
-	    xoperands[2] = hi;
-	    output_asm_insn (output_andsi3 (xoperands), xoperands);
-	    }
-	}
-      if (GET_CODE (operands[0]) == REG)
-	operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-      else
-	operands[0] = adj_offsettable_operand (operands[0], 4);
-      switch (INTVAL (lo))
-	{
-	  case 0 :
-	    output_asm_insn (\"clr%.l %0\", operands);
-	    break;
-	  case -1 :
-	    break;
-	  default :
-	    {
-	    rtx xoperands[3];
-
-	    xoperands[0] = operands[0];
-	    xoperands[2] = lo;
-	    output_asm_insn (output_andsi3 (xoperands), xoperands);
-	    }
-	}
-      return \"\";
-    }
-  if (GET_CODE (operands[0]) != REG)
-    {
-      operands[1] = adj_offsettable_operand (operands[0], 4);
-      return \"and%.l %2,%0\;and%.l %R2,%1\";
-    }
-  if (GET_CODE (operands[2]) != REG)
-    {
-      operands[1] = adj_offsettable_operand (operands[2], 4);
-      return \"and%.l %2,%0\;and%.l %1,%R0\";
-    }
-  return \"and%.l %2,%0\;and%.l %R2,%R0\";
-}")
-
-;; Prevent AND from being made with sp.  This doesn't exist in the machine
-;; and reload will cause inefficient code.  Since sp is a FIXED_REG, we
-;; can't allocate pseudos into it.
-
-(define_expand "andsi3"
-  [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
-	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "dKs,dmMs")))]
-  ""
-  "")
-
-(define_insn "andsi3_internal"
-  [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
-	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "dKs,dmMs")))]
-  "!TARGET_5200"
-  "*
-{
-  return output_andsi3 (operands);
-}")
-
-(define_insn "andsi3_5200"
-  [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
-	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "d,dmsK")))]
-  "TARGET_5200"
-  "and%.l %2,%0")
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "general_operand" "=m,d")
-	(and:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "dn,dmn")))]
-  "!TARGET_5200"
-  "and%.w %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
-	(and:HI (match_dup 0)
-		(match_operand:HI 1 "general_operand" "dn,dmn")))]
-  "!TARGET_5200"
-  "and%.w %1,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
-	(and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
-		(match_dup 0)))]
-  "!TARGET_5200"
-  "and%.w %1,%0")
-
-(define_insn "andqi3"
-  [(set (match_operand:QI 0 "general_operand" "=m,d")
-	(and:QI (match_operand:QI 1 "general_operand" "%0,0")
-		(match_operand:QI 2 "general_operand" "dn,dmn")))]
-  "!TARGET_5200"
-  "and%.b %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
-	(and:QI (match_dup 0)
-		(match_operand:QI 1 "general_operand" "dn,dmn")))]
-  "!TARGET_5200"
-  "and%.b %1,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
-	(and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
-		(match_dup 0)))]
-  "!TARGET_5200"
-  "and%.b %1,%0")
-
-;; inclusive-or instructions
-
-(define_insn "iordi_zext"
-  [(set (match_operand:DI 0 "general_operand" "=o,d")
-    (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
-        (match_operand:DI 2 "general_operand" "0,0")))]
-  "!TARGET_5200"
-  "*
-{
-  int byte_mode;
-
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[0]) == REG)
-    operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  else
-    operands[0] = adj_offsettable_operand (operands[0], 4);
-  if (GET_MODE (operands[1]) == SImode)
-    return \"or%.l %1,%0\";
-  byte_mode = (GET_MODE (operands[1]) == QImode);
-  if (GET_CODE (operands[0]) == MEM)
-    operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
-  if (byte_mode)
-    return \"or%.b %1,%0\";
-  else
-    return \"or%.w %1,%0\";
-}")
-
-;; "iordi3" is mainly here to help combine().
-(define_insn "iordi3"
-  [(set (match_operand:DI 0 "general_operand" "=o,d")
-	(ior:DI (match_operand:DI 1 "general_operand" "%0,0")
-		(match_operand:DI 2 "general_operand" "dn,don")))]
-  "!TARGET_5200"
-  "*
-{
-  CC_STATUS_INIT;
-  /* We can get CONST_DOUBLE, but also const1_rtx etc. */
-  if (GET_CODE (operands[2]) == CONST_DOUBLE
-     || GET_CODE (operands[2]) == CONST_INT)
-    {
-      rtx hi, lo;
-
-      if (GET_CODE (operands[2]) == CONST_DOUBLE)
-	{
-	  hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
-	  lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
-	}
-      else
-	{
-	  lo = operands[2];
-	  hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
-	}
-      switch (INTVAL (hi))
-	{
-	  case 0 :
-	    break;
-	  case -1 :
-	    /* FIXME : a scratch register would be welcome here if operand[0]
-	       is not a register */
-	    output_asm_insn (\"move%.l %#-1,%0\", operands);
-	    break;
-	  default :
-	    {
-	    rtx xoperands[3];
-
-	    xoperands[0] = operands[0];
-	    xoperands[2] = hi;
-	    output_asm_insn (output_iorsi3 (xoperands), xoperands);
-	    }
-	}
-      if (GET_CODE (operands[0]) == REG)
-	operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-      else
-	operands[0] = adj_offsettable_operand (operands[0], 4);
-      switch (INTVAL (lo))
-	{
-	  case 0 :
-	    break;
-	  case -1 :
-	    /* FIXME : a scratch register would be welcome here if operand[0]
-	       is not a register */
-	    output_asm_insn (\"move%.l %#-1,%R0\", operands);
-	    break;
-	  default :
-	    {
-	    rtx xoperands[3];
-
-	    xoperands[0] = operands[0];
-	    xoperands[2] = lo;
-	    output_asm_insn (output_iorsi3 (xoperands), xoperands);
-	    }
-	}
-      return \"\";
-    }
-  if (GET_CODE (operands[0]) != REG)
-    {
-      operands[1] = adj_offsettable_operand (operands[0], 4);
-      return \"or%.l %2,%0\;or%.l %R2,%1\";
-    }
-  if (GET_CODE (operands[2]) != REG)
-    {
-      operands[1] = adj_offsettable_operand (operands[2], 4);
-      return \"or%.l %2,%0\;or%.l %1,%R0\";
-    }
-  return \"or%.l %2,%0\;or%.l %R2,%R0\";
-}")
-
-(define_expand "iorsi3"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(ior:SI (match_operand:SI 1 "general_operand" "")
-		(match_operand:SI 2 "general_operand" "")))]
-  ""
-  "")
-
-(define_insn "iorsi3_internal"
-  [(set (match_operand:SI 0 "general_operand" "=m,d")
-	(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "dKs,dmMs")))]
-  "! TARGET_5200"
-  "*
-{
-  return output_iorsi3 (operands);
-}")
-
-(define_insn "iorsi3_5200"
-  [(set (match_operand:SI 0 "general_operand" "=m,d")
-	(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "d,dmsK")))]
-  "TARGET_5200"
-  "or%.l %2,%0")
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=m,d")
-	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "dn,dmn")))]
-  "!TARGET_5200"
-  "or%.w %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
-	(ior:HI (match_dup 0)
-		(match_operand:HI 1 "general_operand" "dn,dmn")))]
-  "!TARGET_5200"
-  "or%.w %1,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
-	(ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
-		(match_dup 0)))]
-  "!TARGET_5200"
-  "or%.w %1,%0")
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=m,d")
-	(ior:QI (match_operand:QI 1 "general_operand" "%0,0")
-		(match_operand:QI 2 "general_operand" "dn,dmn")))]
-  "!TARGET_5200"
-  "or%.b %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
-	(ior:QI (match_dup 0)
-		(match_operand:QI 1 "general_operand" "dn,dmn")))]
-  "!TARGET_5200"
-  "or%.b %1,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
-	(ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
-		(match_dup 0)))]
-  "!TARGET_5200"
-  "or%.b %1,%0")
-
-;; On all 68k models, this makes faster code in a special case.
-;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
-
-(define_insn "iorsi_zexthi_ashl16"
-  [(set (match_operand:SI 0 "general_operand" "=&d")
-    (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
-        (ashift:SI (match_operand:SI 2 "general_operand" "or")
-            (const_int 16))))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[2]) != REG)
-      operands[2] = adj_offsettable_operand (operands[2], 2);
-  if (GET_CODE (operands[2]) != REG
-  || REGNO (operands[2]) != REGNO (operands[0]))
-    output_asm_insn (\"move%.w %2,%0\", operands);
-  return \"swap %0\;mov%.w %1,%0\";
-}")
-
-(define_insn "iorsi_zext"
-  [(set (match_operand:SI 0 "general_operand" "=o,d")
-    (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
-        (match_operand:SI 2 "general_operand" "0,0")))]
-  "!TARGET_5200"
-  "*
-{
-  int byte_mode;
-
-  CC_STATUS_INIT;
-  byte_mode = (GET_MODE (operands[1]) == QImode);
-  if (GET_CODE (operands[0]) == MEM)
-    operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
-  if (byte_mode)
-    return \"or%.b %1,%0\";
-  else
-    return \"or%.w %1,%0\";
-}")
-
-;; xor instructions
-
-;; "xordi3" is mainly here to help combine().
-(define_insn "xordi3"
-  [(set (match_operand:DI 0 "general_operand" "=od")
-	(xor:DI (match_operand:DI 1 "general_operand" "%0")
-		(match_operand:DI 2 "general_operand" "dn")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  /* We can get CONST_DOUBLE, but also const1_rtx etc. */
-  if (GET_CODE (operands[2]) == CONST_DOUBLE
-     || GET_CODE (operands[2]) == CONST_INT)
-    {
-      rtx hi, lo;
-
-      if (GET_CODE (operands[2]) == CONST_DOUBLE)
-	{
-	  hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
-	  lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
-	}
-      else
-	{
-	  lo = operands[2];
-	  hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
-	}
-      switch (INTVAL (hi))
-	{
-	  case 0 :
-	    break;
-	  case -1 :
-	    output_asm_insn (\"not%.l %0\", operands);
-	    break;
-	  default :
-	    /* FIXME : a scratch register would be welcome here if
-	       -128 <= INTVAL (hi) < -1 */
-	    {
-	    rtx xoperands[3];
-
-	    xoperands[0] = operands[0];
-	    xoperands[2] = hi;
-	    output_asm_insn (output_xorsi3 (xoperands), xoperands);
-	    }
-	}
-      if (GET_CODE (operands[0]) == REG)
-	operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-      else
-	operands[0] = adj_offsettable_operand (operands[0], 4);
-      switch (INTVAL (lo))
-	{
-	  case 0 :
-	    break;
-	  case -1 :
-	    output_asm_insn (\"not%.l %0\", operands);
-	    break;
-	  default :
-	    /* FIXME : a scratch register would be welcome here if
-	       -128 <= INTVAL (lo) < -1 */
-	    operands[2] = lo;
-	    /* FIXME : this should be merged with xorsi3 */
-	    {
-	    rtx xoperands[3];
-
-	    xoperands[0] = operands[0];
-	    xoperands[2] = lo;
-	    output_asm_insn (output_xorsi3 (xoperands), xoperands);
-	    }
-	}
-      return \"\";
-    }
-  if (GET_CODE (operands[0]) != REG)
-    {
-      operands[1] = adj_offsettable_operand (operands[0], 4);
-      return \"eor%.l %2,%0\;eor%.l %R2,%1\";
-    }
-  if (GET_CODE (operands[2]) != REG)
-    {
-      operands[1] = adj_offsettable_operand (operands[2], 4);
-      return \"eor%.l %2,%0\;eor%.l %1,%R0\";
-    }
-  return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
-}")
-
-(define_expand "xorsi3"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(xor:SI (match_operand:SI 1 "general_operand" "")
-		(match_operand:SI 2 "general_operand" "")))]
-  ""
-  "")
-
-(define_insn "xorsi3_internal"
-  [(set (match_operand:SI 0 "general_operand" "=do,m")
-	(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "di,dKs")))]
-  "!TARGET_5200"
-  "*
-{
-  return output_xorsi3 (operands);
-}")
-
-(define_insn "xorsi3_5200"
-  [(set (match_operand:SI 0 "general_operand" "=dm,d")
-	(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
-		(match_operand:SI 2 "general_operand" "d,Ks")))]
-  "TARGET_5200"
-  "eor%.l %2,%0")
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=dm")
-	(xor:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "dn")))]
-  "!TARGET_5200"
-  "eor%.w %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
-	(xor:HI (match_dup 0)
-		(match_operand:HI 1 "general_operand" "dn")))]
-  "!TARGET_5200"
-  "eor%.w %1,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
-	(xor:HI (match_operand:HI 1 "general_operand" "dn")
-		(match_dup 0)))]
-  "!TARGET_5200"
-  "eor%.w %1,%0")
-
-(define_insn "xorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(xor:QI (match_operand:QI 1 "general_operand" "%0")
-		(match_operand:QI 2 "general_operand" "dn")))]
-  "!TARGET_5200"
-  "eor%.b %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
-	(xor:QI (match_dup 0)
-		(match_operand:QI 1 "general_operand" "dn")))]
-  "!TARGET_5200"
-  "eor%.b %1,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
-	(xor:QI (match_operand:QI 1 "general_operand" "dn")
-		(match_dup 0)))]
-  "!TARGET_5200"
-  "eor%.b %1,%0")
-
-;; negation instructions
-
-(define_expand "negdi2"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(neg:DI (match_operand:DI 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_5200)
-    emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
-  else
-    emit_insn (gen_negdi2_internal (operands[0], operands[1]));
-  DONE;
-}")
-
-(define_insn "negdi2_internal"
-  [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
-	(neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
-  "!TARGET_5200"
-  "*
-{
-  if (which_alternative == 0)
-    return \"neg%.l %0\;negx%.l %0\";
-  if (GET_CODE (operands[0]) == REG)
-    operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  else
-    operands[1] = adj_offsettable_operand (operands[0], 4);
-  if (ADDRESS_REG_P (operands[0]))
-    return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
-  else
-    return \"neg%.l %1\;negx%.l %0\";
-} ")
-
-(define_insn "negdi2_5200"
-  [(set (match_operand:DI 0 "general_operand" "=d")
-	(neg:DI (match_operand:DI 1 "general_operand" "0")))]
-  "TARGET_5200"
-  "*
-{
-  operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  return \"neg%.l %1\;negx%.l %0\";
-} ")
-
-(define_expand "negsi2"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(neg:SI (match_operand:SI 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_5200)
-    emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
-  else
-    emit_insn (gen_negsi2_internal (operands[0], operands[1]));
-  DONE;
-}")
-
-(define_insn "negsi2_internal"
-  [(set (match_operand:SI 0 "general_operand" "=dm")
-	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
-  "!TARGET_5200"
-  "neg%.l %0")
-
-(define_insn "negsi2_5200"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
-  "TARGET_5200"
-  "neg%.l %0")
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "general_operand" "=dm")
-	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
-  "!TARGET_5200"
-  "neg%.w %0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
-	(neg:HI (match_dup 0)))]
-  "!TARGET_5200"
-  "neg%.w %0")
-
-(define_insn "negqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(neg:QI (match_operand:QI 1 "general_operand" "0")))]
-  "!TARGET_5200"
-  "neg%.b %0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
-	(neg:QI (match_dup 0)))]
-  "!TARGET_5200"
-  "neg%.b %0")
-
-;; If using software floating point, just flip the sign bit.
-
-(define_expand "negsf2"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(neg:SF (match_operand:SF 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (!TARGET_FPA && !TARGET_68881)
-    {
-      rtx result;
-      rtx target;
-
-      target = operand_subword_force (operands[0], 0, SFmode);
-      result = expand_binop (SImode, xor_optab,
-			     operand_subword_force (operands[1], 0, SFmode),
-			     GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
-      if (result == 0)
-	abort ();
-
-      if (result != target)
-	emit_move_insn (result, target);
-
-      /* Make a place for REG_EQUAL.  */
-      emit_move_insn (operands[0], operands[0]);
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=x,y")
-	(neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
-  "TARGET_FPA"
-  "fpneg%.s %w1,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f,d")
-	(neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
-  "TARGET_68881"
-  "*
-{
-  if (DATA_REG_P (operands[0]))
-    {
-      operands[1] = GEN_INT (31);
-      return \"bchg %1,%0\";
-    }
-  if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return \"f%$neg%.x %1,%0\";
-  return \"f%$neg%.s %f1,%0\";
-}")
-
-(define_expand "negdf2"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(neg:DF (match_operand:DF 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (!TARGET_FPA && !TARGET_68881)
-    {
-      rtx result;
-      rtx target;
-      rtx insns;
-
-      start_sequence ();
-      target = operand_subword (operands[0], 0, 1, DFmode);
-      result = expand_binop (SImode, xor_optab,
-			     operand_subword_force (operands[1], 0, DFmode),
-			     GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
-      if (result == 0)
-	abort ();
-
-      if (result != target)
-	emit_move_insn (result, target);
-
-      emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
-		      operand_subword_force (operands[1], 1, DFmode));
-
-      insns = get_insns ();
-      end_sequence ();
-
-      emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=x,y")
-	(neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
-  "TARGET_FPA"
-  "fpneg%.d %y1, %0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f,d")
-	(neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
-  "TARGET_68881"
-  "*
-{
-  if (DATA_REG_P (operands[0]))
-    {
-      operands[1] = GEN_INT (31);
-      return \"bchg %1,%0\";
-    }
-  if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return \"f%&neg%.x %1,%0\";
-  return \"f%&neg%.d %f1,%0\";
-}")
-
-;; Sqrt instruction for the 68881
-
-(define_insn "sqrtsf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
-  "TARGET_68881"
-  "*
-{
-  if (FP_REG_P (operands[1]))
-    return \"f%$sqrt%.x %1,%0\";
-  else
-    return \"f%$sqrt%.s %1,%0\";
-}")
-
-(define_insn "sqrtdf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
-  "TARGET_68881"
-  "*
-{
-  if (FP_REG_P (operands[1]))
-    return \"f%&sqrt%.x %1,%0\";
-  else
-    return \"f%&sqrt%.d %1,%0\";
-}")
-
-;; Absolute value instructions
-;; If using software floating point, just zero the sign bit.
-
-(define_expand "abssf2"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(abs:SF (match_operand:SF 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (!TARGET_FPA && !TARGET_68881)
-    {
-      rtx result;
-      rtx target;
-
-      target = operand_subword_force (operands[0], 0, SFmode);
-      result = expand_binop (SImode, and_optab,
-			     operand_subword_force (operands[1], 0, SFmode),
-			     GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
-      if (result == 0)
-	abort ();
-
-      if (result != target)
-	emit_move_insn (result, target);
-
-      /* Make a place for REG_EQUAL.  */
-      emit_move_insn (operands[0], operands[0]);
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=x,y")
-	(abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
-  "TARGET_FPA"
-  "fpabs%.s %y1,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return \"f%$abs%.x %1,%0\";
-  return \"f%$abs%.s %f1,%0\";
-}")
-
-(define_expand "absdf2"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(abs:DF (match_operand:DF 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (!TARGET_FPA && !TARGET_68881)
-    {
-      rtx result;
-      rtx target;
-      rtx insns;
-
-      start_sequence ();
-      target = operand_subword (operands[0], 0, 1, DFmode);
-      result = expand_binop (SImode, and_optab,
-			     operand_subword_force (operands[1], 0, DFmode),
-			     GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
-      if (result == 0)
-	abort ();
-
-      if (result != target)
-	emit_move_insn (result, target);
-
-      emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
-		      operand_subword_force (operands[1], 1, DFmode));
-
-      insns = get_insns ();
-      end_sequence ();
-
-      emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=x,y")
-	(abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
-  "TARGET_FPA"
-  "fpabs%.d %y1,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return \"f%&abs%.x %1,%0\";
-  return \"f%&abs%.d %f1,%0\";
-}")
-
-;; one complement instructions
-
-;; "one_cmpldi2" is mainly here to help combine().
-(define_insn "one_cmpldi2"
-  [(set (match_operand:DI 0 "general_operand" "=dm")
-	(not:DI (match_operand:DI 1 "general_operand" "0")))]
-  "!TARGET_5200"
-  "*
-{
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[0]) == REG)
-    operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
-        || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    operands[1] = operands[0];
-  else
-    operands[1] = adj_offsettable_operand (operands[0], 4);
-  return \"not%.l %1\;not%.l %0\";
-}")
-
-(define_expand "one_cmplsi2"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(not:SI (match_operand:SI 1 "general_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_5200)
-    emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
-  else
-    emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
-  DONE;
-}")
-
-(define_insn "one_cmplsi2_internal"
-  [(set (match_operand:SI 0 "general_operand" "=dm")
-	(not:SI (match_operand:SI 1 "general_operand" "0")))]
-  "!TARGET_5200"
-  "not%.l %0")
-
-(define_insn "one_cmplsi2_5200"
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(not:SI (match_operand:SI 1 "general_operand" "0")))]
-  "TARGET_5200"
-  "not%.l %0")
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "general_operand" "=dm")
-	(not:HI (match_operand:HI 1 "general_operand" "0")))]
-  "!TARGET_5200"
-  "not%.w %0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
-	(not:HI (match_dup 0)))]
-  "!TARGET_5200"
-  "not%.w %0")
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(not:QI (match_operand:QI 1 "general_operand" "0")))]
-  "!TARGET_5200"
-  "not%.b %0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
-	(not:QI (match_dup 0)))]
-  "!TARGET_5200"
-  "not%.b %0")
-
-;; arithmetic shift instructions
-;; We don't need the shift memory by 1 bit instruction
-
-(define_insn "ashldi_extsi"
-  [(set (match_operand:DI 0 "general_operand" "=ro")
-    (ashift:DI
-      (match_operator:DI 2 "extend_operator"
-        [(match_operand:SI 1 "general_operand" "rm")])
-      (const_int 32)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[0]) == REG)
-    operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  else
-    operands[2] = adj_offsettable_operand (operands[0], 4);
-  if (ADDRESS_REG_P (operands[0]))
-    return \"move%.l %1,%0\;sub%.l %2,%2\";
-  else
-    return \"move%.l %1,%0\;clr%.l %2\";
-} ")
-
-(define_insn "ashldi_sexthi"
-  [(set (match_operand:DI 0 "general_operand" "=m,a*d")
-    (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
-        (const_int 32)))
-    (clobber (match_scratch:SI 2 "=a,X"))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[0]) == MEM)
-    {
-    if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-      return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
-    else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-      return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
-    else
-      {
-	operands[3] = adj_offsettable_operand (operands[0], 4);
-	return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
-      }
-    }
-  else if (DATA_REG_P (operands[0]))
-    return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
-  else
-    return \"move%.w %1,%0\;sub%.l %R0,%R0\";
-} ")
-
-(define_insn "ashldi_const32"
-  [(set (match_operand:DI 0 "general_operand" "=rm")
-	(ashift:DI (match_operand:DI 1 "general_operand" "ro")
-		     (const_int 32)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[1]) == REG)
-    operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-  else
-    operands[3] = adj_offsettable_operand (operands[1], 4);
-  if (GET_CODE (operands[0]) == REG)
-    operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    return \"clr%.l %0\;move%.l %3,%0\";
-  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    return \"move%.l %3,%0\;clr%.l %0\";
-  else
-    operands[2] = adj_offsettable_operand (operands[0], 4);
-  if (ADDRESS_REG_P (operands[2]))
-    return \"move%.l %3,%0\;sub%.l %2,%2\";
-  else
-    return \"move%.l %3,%0\;clr%.l %2\";
-} ")
-
-;; The predicate below must be general_operand, because ashldi3 allows that
-(define_insn "ashldi_const"
-  [(set (match_operand:DI 0 "general_operand" "=d")
-	(ashift:DI (match_operand:DI 1 "general_operand" "0")
-		     (match_operand 2 "const_int_operand" "n")))]
-  "(!TARGET_5200
-    && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
-	|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
-	|| (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
-  "*
-{
-  operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (INTVAL (operands[2]) == 1)
-    return \"add%.l %1,%1\;addx%.l %0,%0\";
-  else if (INTVAL (operands[2]) == 8)
-    return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
-  else if (INTVAL (operands[2]) == 16)
-    return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
-  else if (INTVAL (operands[2]) == 48)
-    return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
-  else if (INTVAL (operands[2]) == 2)
-    return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
-  else if (INTVAL (operands[2]) == 3)
-    return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
-  else /* 32 < INTVAL (operands[2]) <= 63 */
-    {
-      operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
-      output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
-			\"moveq %2,%0\;asl%.l %0,%1\", operands);
-      return \"mov%.l %1,%0\;moveq %#0,%1\";
-    }
-} ")
-
-(define_expand "ashldi3"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(ashift:DI (match_operand:DI 1 "general_operand" "")
-		     (match_operand 2 "const_int_operand" "")))]
-  "!TARGET_5200"
-  "
-{
-  /* ???  This is a named pattern like this is not allowed to FAIL based
-     on its operands.  */
-  if (GET_CODE (operands[2]) != CONST_INT
-      || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
-	  && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
-	  && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
-    FAIL;
-} ")
-
-;; On most 68k models, this makes faster code in a special case.
-
-(define_insn "ashlsi_16"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0")
-		   (const_int 16)))]
-  "!TARGET_68060"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"swap %0\;clr%.w %0\";
-}")
-
-;; ashift patterns : use lsl instead of asl, because lsl always clears the
-;; overflow bit, so we must not set CC_NO_OVERFLOW.
-
-;; On the 68000, this makes faster code in a special case.
-
-(define_insn "ashlsi_17_24"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:SI 2 "const_int_operand" "n")))]
-  "(! TARGET_68020 && !TARGET_5200
-    && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
-  "*
-{
-  CC_STATUS_INIT;
-
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
-  return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
-}")
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:SI 2 "general_operand" "dI")))]
-  ""
-  "*
-{
-  if (operands[2] == const1_rtx)
-    {
-      cc_status.flags = CC_NO_OVERFLOW;
-      return \"add%.l %0,%0\";
-    }
-  return \"lsl%.l %2,%0\";
-}")
-
-(define_insn "ashlhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d")
-	(ashift:HI (match_operand:HI 1 "register_operand" "0")
-		   (match_operand:HI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "lsl%.w %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
-	(ashift:HI (match_dup 0)
-		   (match_operand:HI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "lsl%.w %1,%0")
-
-(define_insn "ashlqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d")
-	(ashift:QI (match_operand:QI 1 "register_operand" "0")
-		   (match_operand:QI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "lsl%.b %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
-	(ashift:QI (match_dup 0)
-		   (match_operand:QI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "lsl%.b %1,%0")
-
-;; On most 68k models, this makes faster code in a special case.
-
-(define_insn "ashrsi_16"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (const_int 16)))]
-  "!TARGET_68060"
-  "swap %0\;ext%.l %0")
-
-;; On the 68000, this makes faster code in a special case.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "n")))]
-  "(! TARGET_68020 && !TARGET_5200
-    && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
-  return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
-}")
-
-(define_insn "subreghi1ashrdi_const32"
-  [(set (match_operand:HI 0 "general_operand" "=rm")
-    (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
-            (const_int 32)) 1))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) != REG)
-    operands[1] = adj_offsettable_operand (operands[1], 2);
-  return \"move%.w %1,%0\";
-} ")
-
-(define_insn "subregsi1ashrdi_const32"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-    (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
-            (const_int 32)) 1))]
-  ""
-  "*
-{
-  return \"move%.l %1,%0\";
-} ")
-
-(define_insn "ashrdi_const32"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
-		     (const_int 32)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (TARGET_68020)
-    return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
-  else
-    return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
-} ")
-
-(define_insn "ashrdi_const32_mem"
-  [(set (match_operand:DI 0 "general_operand" "=o,<")
-	(ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
-		     (const_int 32)))
-   (clobber (match_scratch:SI 2 "=d,d"))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (which_alternative == 1)
-    operands[3] = operands[0];
-  else
-    operands[3] = adj_offsettable_operand (operands[0], 4);
-  if (TARGET_68020)
-    return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
-  else
-    return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
-} ")
-
-;; The predicate below must be general_operand, because ashrdi3 allows that
-(define_insn "ashrdi_const"
-  [(set (match_operand:DI 0 "general_operand" "=d")
-	(ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
-		     (match_operand 2 "const_int_operand" "n")))]
-  "!TARGET_5200 
-    && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
-    || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
-    || INTVAL (operands[2]) == 31
-    || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
-  "*
-{
-  operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (INTVAL (operands[2]) == 63)
-    return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
-  CC_STATUS_INIT;
-  if (INTVAL (operands[2]) == 1)
-    return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
-  else if (INTVAL (operands[2]) == 8)
-    return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
-  else if (INTVAL (operands[2]) == 16)
-    return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
-  else if (INTVAL (operands[2]) == 48)
-    return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
-  else if (INTVAL (operands[2]) == 31)
-    return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
-  else if (INTVAL (operands[2]) == 2)
-    return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
-  else if (INTVAL (operands[2]) == 3)
-    return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
-  else /* 32 < INTVAL (operands[2]) <= 63 */
-    {
-      operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
-      output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
-			\"moveq %2,%1\;asr%.l %1,%0\", operands);
-      output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
-      return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
-	     TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
-    }
-} ")
-
-(define_expand "ashrdi3"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(ashiftrt:DI (match_operand:DI 1 "general_operand" "")
-		     (match_operand 2 "const_int_operand" "")))]
-  "!TARGET_5200"
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT
-  || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
-     && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
-     && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
-    FAIL;
-} ")
-
-;; On all 68k models, this makes faster code in a special case.
-
-(define_insn "ashrsi_31"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (const_int 31)))]
-  ""
-  "*
-{
-  return \"add%.l %0,%0\;subx%.l %0,%0\";
-}")
-
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:SI 2 "general_operand" "dI")))]
-  ""
-  "asr%.l %2,%0")
-
-(define_insn "ashrhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d")
-	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
-		     (match_operand:HI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "asr%.w %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
-	(ashiftrt:HI (match_dup 0)
-		     (match_operand:HI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "asr%.w %1,%0")
-
-(define_insn "ashrqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d")
-	(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
-		     (match_operand:QI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "asr%.b %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
-	(ashiftrt:QI (match_dup 0)
-		     (match_operand:QI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "asr%.b %1,%0")
-
-;; logical shift instructions
-
-;; commented out because of reload problems in 950612-1.c
-;;(define_insn ""
-;;        [(set (cc0)
-;;            (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
-;;                    (const_int 32)) 1))
-;;        (set (match_operand:SI 1 "general_operand" "=dm")
-;;            (subreg:SI (lshiftrt:DI (match_dup 0)
-;;                    (const_int 32)) 1))]
-;;  ""
-;;  "*
-;;{
-;;  return \"move%.l %0,%1\";
-;;} ")
-;;
-;;(define_insn ""
-;;        [(set (cc0)
-;;            (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
-;;                    (const_int 32)) 0))
-;;        (set (match_operand:DI 1 "general_operand" "=do")
-;;            (lshiftrt:DI (match_dup 0)
-;;                (const_int 32)))]
-;;  ""
-;;  "*
-;;{
-;;  if (GET_CODE (operands[1]) == REG)
-;;    operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-;;  else
-;;    operands[2] = adj_offsettable_operand (operands[1], 4);
-;;  return \"move%.l %0,%2\;clr%.l %1\";
-;;} ")
-
-(define_insn "subreg1lshrdi_const32"
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-    (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
-            (const_int 32)) 1))]
-  ""
-  "*
-{
-  return \"move%.l %1,%0\";
-} ")
-
-(define_insn "lshrdi_const32"
-  [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
-	(lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
-		     (const_int 32)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (which_alternative == 1)
-    return \"move%.l %1,%0\;clr%.l %0\";
-  if (which_alternative == 2)
-    return \"clr%.l %0\;move%.l %1,%0\";
-  if (GET_CODE (operands[0]) == REG)
-    operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  else
-    operands[2] = adj_offsettable_operand (operands[0], 4);
-  if (GET_CODE (operands[1]) == REG)
-    operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-  else
-    operands[3] = adj_offsettable_operand (operands[1], 4);
-  if (ADDRESS_REG_P (operands[0]))
-    return \"move%.l %1,%2\;sub%.l %0,%0\";
-  else
-    return \"move%.l %1,%2\;clr%.l %0\";
-} ")
-
-;; The predicate below must be general_operand, because lshrdi3 allows that
-(define_insn "lshrdi_const"
-  [(set (match_operand:DI 0 "general_operand" "=d")
-	(lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
-		     (match_operand 2 "const_int_operand" "n")))]
-  "!TARGET_5200
-    && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
-    || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
-    || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
-  "*
-{
-  operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (INTVAL (operands[2]) == 63)
-    return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
-  CC_STATUS_INIT;
-  if (INTVAL (operands[2]) == 1)
-    return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
-  else if (INTVAL (operands[2]) == 8)
-    return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
-  else if (INTVAL (operands[2]) == 16)
-    return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
-  else if (INTVAL (operands[2]) == 48)
-    return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
-  else if (INTVAL (operands[2]) == 2)
-    return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
-  else if (INTVAL (operands[2]) == 3)
-    return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
-  else /* 32 < INTVAL (operands[2]) <= 63 */
-    {
-      operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
-      output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
-			\"moveq %2,%1\;lsr%.l %1,%0\", operands);
-      return \"mov%.l %0,%1\;moveq %#0,%0\";
-    }
-} ")
-
-(define_expand "lshrdi3"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "general_operand" "")
-		     (match_operand 2 "const_int_operand" "")))]
-  "!TARGET_5200"
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT
-  || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
-     && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
-     && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
-    FAIL;
-} ")
-
-;; On all 68k models, this makes faster code in a special case.
-
-(define_insn "lshrsi_31"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (const_int 31)))]
-  ""
-  "*
-{
-  return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
-}")
-
-;; On most 68k models, this makes faster code in a special case.
-
-(define_insn "lshrsi_16"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (const_int 16)))]
-  "!TARGET_68060"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"clr%.w %0\;swap %0\";
-}")
-
-;; On the 68000, this makes faster code in a special case.
-
-(define_insn "lshrsi_17_24"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "n")))]
-  "(! TARGET_68020 && !TARGET_5200
-    && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
-  "*
-{
-  /* I think lsr%.w sets the CC properly.  */
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
-  return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
-}")
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:SI 2 "general_operand" "dI")))]
-  ""
-  "lsr%.l %2,%0")
-
-(define_insn "lshrhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d")
-	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
-		     (match_operand:HI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "lsr%.w %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
-	(lshiftrt:HI (match_dup 0)
-		     (match_operand:HI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "lsr%.w %1,%0")
-
-(define_insn "lshrqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d")
-	(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
-		     (match_operand:QI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "lsr%.b %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
-	(lshiftrt:QI (match_dup 0)
-		     (match_operand:QI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "lsr%.b %1,%0")
-
-;; rotate instructions
-
-(define_insn "rotlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(rotate:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:SI 2 "general_operand" "dINO")))]
-  "!TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
-    return \"swap %0\";
-  else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
-    {
-      operands[2] = GEN_INT (32 - INTVAL (operands[2]));
-      return \"ror%.l %2,%0\";
-    }
-  else
-    return \"rol%.l %2,%0\";
-}")
-
-(define_insn "rotlhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d")
-	(rotate:HI (match_operand:HI 1 "register_operand" "0")
-		   (match_operand:HI 2 "general_operand" "dIP")))]
-  "!TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
-    {
-      operands[2] = GEN_INT (16 - INTVAL (operands[2]));
-      return \"ror%.w %2,%0\";
-    }
-  else
-    return \"rol%.w %2,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
-	(rotate:HI (match_dup 0)
-		   (match_operand:HI 1 "general_operand" "dIP")))]
-  "!TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
-    {
-      operands[2] = GEN_INT (16 - INTVAL (operands[2]));
-      return \"ror%.w %2,%0\";
-    }
-  else
-    return \"rol%.w %2,%0\";
-}")
-
-(define_insn "rotlqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d")
-	(rotate:QI (match_operand:QI 1 "register_operand" "0")
-		   (match_operand:QI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
-    {
-      operands[2] = GEN_INT (8 - INTVAL (operands[2]));
-      return \"ror%.b %2,%0\";
-    }
-  else
-    return \"rol%.b %2,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
-	(rotate:QI (match_dup 0)
-		   (match_operand:QI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
-    {
-      operands[2] = GEN_INT (8 - INTVAL (operands[2]));
-      return \"ror%.b %2,%0\";
-    }
-  else
-    return \"rol%.b %2,%0\";
-}")
-
-(define_insn "rotrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(rotatert:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:SI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "ror%.l %2,%0")
-
-(define_insn "rotrhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d")
-	(rotatert:HI (match_operand:HI 1 "register_operand" "0")
-		     (match_operand:HI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "ror%.w %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
-	(rotatert:HI (match_dup 0)
-		     (match_operand:HI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "ror%.w %1,%0")
-
-(define_insn "rotrqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d")
-	(rotatert:QI (match_operand:QI 1 "register_operand" "0")
-		     (match_operand:QI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "ror%.b %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
-	(rotatert:QI (match_dup 0)
-		     (match_operand:QI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
-  "ror%.b %1,%0")
-
-
-;; Bit set/clear in memory byte.
-
-;; set bit, bit number is int
-(define_insn "bsetmemqi"
-  [(set (match_operand:QI 0 "memory_operand" "+m")
-	(ior:QI (subreg:QI (ashift:SI (const_int 1)
-		(match_operand:SI 1 "general_operand" "d")) 0)
-	(match_dup 0)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bset %1,%0\";
-}")
-
-;; set bit, bit number is (sign/zero)_extended from HImode/QImode
-(define_insn ""
-  [(set (match_operand:QI 0 "memory_operand" "+m")
-	(ior:QI (subreg:QI (ashift:SI (const_int 1)
-	    (match_operator:SI 2 "extend_operator"
-		[(match_operand 1 "general_operand" "d")])) 0)
-	(match_dup 0)))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bset %1,%0\";
-}")
-
-;; clear bit, bit number is int
-(define_insn "bclrmemqi"
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
-	(const_int 1)
-	(minus:SI (const_int 7)
-	    (match_operand:SI 1 "general_operand" "d")))
-    (const_int 0))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bclr %1,%0\";
-}")
-
-;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
-	(const_int 1)
-	(minus:SI (const_int 7)
-	    (match_operator:SI 2 "extend_operator"
-		[(match_operand 1 "general_operand" "d")])))
-    (const_int 0))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bclr %1,%0\";
-}")
-
-;; Special cases of bit-field insns which we should
-;; recognize in preference to the general case.
-;; These handle aligned 8-bit and 16-bit fields,
-;; which can usually be done with move instructions.
-
-;
-; Special case for 32-bit field in memory.  This only occurs when 32-bit
-; alignment of structure members is specified.
-;
-; The move is allowed to be odd byte aligned, because that's still faster
-; than an odd byte aligned bit field instruction.
-;
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
-			 (const_int 32)
-			 (match_operand:SI 2 "const_int_operand" "n"))
-	(match_operand:SI 3 "general_operand" "rmi"))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[2]) % 8) == 0
-   && ! mode_dependent_address_p (XEXP (operands[0], 0))"
-  "*
-{
-  operands[0]
-    = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
-
-  return \"move%.l %3,%0\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
-			 (match_operand:SI 1 "const_int_operand" "n")
-			 (match_operand:SI 2 "const_int_operand" "n"))
-	(match_operand:SI 3 "register_operand" "d"))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
-   && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
-   && (GET_CODE (operands[0]) == REG
-       || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
-  "*
-{
-  if (REG_P (operands[0]))
-    {
-      if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
-        return \"bfins %3,%0{%b2:%b1}\";
-    }
-  else
-    operands[0]
-      = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
-
-  if (GET_CODE (operands[3]) == MEM)
-    operands[3] = adj_offsettable_operand (operands[3],
-					   (32 - INTVAL (operands[1])) / 8);
-  if (INTVAL (operands[1]) == 8)
-    return \"move%.b %3,%0\";
-  return \"move%.w %3,%0\";
-}")
-
-
-;
-; Special case for 32-bit field in memory.  This only occurs when 32-bit
-; alignment of structure members is specified.
-;
-; The move is allowed to be odd byte aligned, because that's still faster
-; than an odd byte aligned bit field instruction.
-;
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
-			 (const_int 32)
-			 (match_operand:SI 3 "const_int_operand" "n")))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[3]) % 8) == 0
-   && ! mode_dependent_address_p (XEXP (operands[1], 0))"
-  "*
-{
-  operands[1]
-    = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
-
-  return \"move%.l %1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=&d")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "do")
-			 (match_operand:SI 2 "const_int_operand" "n")
-			 (match_operand:SI 3 "const_int_operand" "n")))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
-   && (GET_CODE (operands[1]) == REG
-       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
-  "*
-{
-  cc_status.flags |= CC_NOT_NEGATIVE;
-  if (REG_P (operands[1]))
-    {
-      if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
-	return \"bfextu %1{%b3:%b2},%0\";
-    }
-  else
-    operands[1]
-      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
-
-  output_asm_insn (\"clr%.l %0\", operands);
-  if (GET_CODE (operands[0]) == MEM)
-    operands[0] = adj_offsettable_operand (operands[0],
-					   (32 - INTVAL (operands[1])) / 8);
-  if (INTVAL (operands[2]) == 8)
-    return \"move%.b %1,%0\";
-  return \"move%.w %1,%0\";
-}")
-
-;
-; Special case for 32-bit field in memory.  This only occurs when 32-bit
-; alignment of structure members is specified.
-;
-; The move is allowed to be odd byte aligned, because that's still faster
-; than an odd byte aligned bit field instruction.
-;
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=rm")
-	(sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
-			 (const_int 32)
-			 (match_operand:SI 3 "const_int_operand" "n")))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[3]) % 8) == 0
-   && ! mode_dependent_address_p (XEXP (operands[1], 0))"
-  "*
-{
-  operands[1]
-    = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
-
-  return \"move%.l %1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(sign_extract:SI (match_operand:SI 1 "register_operand" "do")
-			 (match_operand:SI 2 "const_int_operand" "n")
-			 (match_operand:SI 3 "const_int_operand" "n")))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
-   && (GET_CODE (operands[1]) == REG
-       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
-  "*
-{
-  if (REG_P (operands[1]))
-    {
-      if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
-	return \"bfexts %1{%b3:%b2},%0\";
-    }
-  else
-    operands[1]
-      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
-
-  if (INTVAL (operands[2]) == 8)
-    return \"move%.b %1,%0\;extb%.l %0\";
-  return \"move%.w %1,%0\;ext%.l %0\";
-}")
-
-;; Bit field instructions, general cases.
-;; "o,d" constraint causes a nonoffsettable memref to match the "o"
-;; so that its address is reloaded.
-
-(define_expand "extv"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(sign_extract:SI (match_operand:SI 1 "general_operand" "")
-			 (match_operand:SI 2 "general_operand" "")
-			 (match_operand:SI 3 "general_operand" "")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
-			 (match_operand:SI 2 "general_operand" "di")
-			 (match_operand:SI 3 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "bfexts %1{%b3:%b2},%0")
-
-(define_expand "extzv"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(zero_extract:SI (match_operand:SI 1 "general_operand" "")
-			 (match_operand:SI 2 "general_operand" "")
-			 (match_operand:SI 3 "general_operand" "")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d,d")
-	(zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
-			 (match_operand:SI 2 "general_operand" "di,di")
-			 (match_operand:SI 3 "general_operand" "di,di")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) != 32)
-	cc_status.flags |= CC_NOT_NEGATIVE;
-    }
-  else
-    {
-      CC_STATUS_INIT;
-    }
-  return \"bfextu %1{%b3:%b2},%0\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-        (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
-		(match_operand 3 "const_int_operand" "n")))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && (INTVAL (operands[3]) == -1
-       || (GET_CODE (operands[1]) == CONST_INT
-           && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bfchg %0{%b2:%b1}\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-	(const_int 0))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bfclr %0{%b2:%b1}\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-	(const_int -1))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bfset %0{%b2:%b1}\";
-}")
-
-(define_expand "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
-			 (match_operand:SI 1 "general_operand" "")
-			 (match_operand:SI 2 "general_operand" ""))
-	(match_operand:SI 3 "register_operand" ""))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-	(match_operand:SI 3 "register_operand" "d"))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "bfins %3,%0{%b2:%b1}")
-
-;; Now recognize bit field insns that operate on registers
-;; (or at least were intended to do so).
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(sign_extract:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "general_operand" "di")
-			 (match_operand:SI 3 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "bfexts %1{%b3:%b2},%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "general_operand" "di")
-			 (match_operand:SI 3 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) != 32)
-	cc_status.flags |= CC_NOT_NEGATIVE;
-    }
-  else
-    {
-      CC_STATUS_INIT;
-    }
-  return \"bfextu %1{%b3:%b2},%0\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-	(const_int 0))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bfclr %0{%b2:%b1}\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-	(const_int -1))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"bfset %0{%b2:%b1}\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
-			 (match_operand:SI 1 "general_operand" "di")
-			 (match_operand:SI 2 "general_operand" "di"))
-	(match_operand:SI 3 "register_operand" "d"))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-#if 0
-  /* These special cases are now recognized by a specific pattern.  */
-  if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
-    return \"move%.w %3,%0\";
-  if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
-    return \"move%.b %3,%0\";
-#endif
-  return \"bfins %3,%0{%b2:%b1}\";
-}")
-
-;; Special patterns for optimizing bit-field instructions.
-
-(define_insn ""
-  [(set (cc0)
-	(zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
-			 (match_operand:SI 1 "const_int_operand" "n")
-			 (match_operand:SI 2 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  if (operands[1] == const1_rtx
-      && GET_CODE (operands[2]) == CONST_INT)
-    {
-      int width = GET_CODE (operands[0]) == REG ? 31 : 7;
-      return output_btst (operands,
-			  GEN_INT (width - INTVAL (operands[2])),
-			  operands[0],
-			  insn, 1000);
-      /* Pass 1000 as SIGNPOS argument so that btst will
-         not think we are testing the sign bit for an `and'
-	 and assume that nonzero implies a negative result.  */
-    }
-  if (INTVAL (operands[1]) != 32)
-    cc_status.flags = CC_NOT_NEGATIVE;
-  return \"bftst %0{%b2:%b1}\";
-}")
-
-
-;;; now handle the register cases
-(define_insn ""
-  [(set (cc0)
-	(zero_extract:SI (match_operand:SI 0 "register_operand" "d")
-			 (match_operand:SI 1 "const_int_operand" "n")
-			 (match_operand:SI 2 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD"
-  "*
-{
-  if (operands[1] == const1_rtx
-      && GET_CODE (operands[2]) == CONST_INT)
-    {
-      int width = GET_CODE (operands[0]) == REG ? 31 : 7;
-      return output_btst (operands,
-			  GEN_INT (width - INTVAL (operands[2])),
-			  operands[0],
-			  insn, 1000);
-      /* Pass 1000 as SIGNPOS argument so that btst will
-         not think we are testing the sign bit for an `and'
-	 and assume that nonzero implies a negative result.  */
-    }
-  if (INTVAL (operands[1]) != 32)
-    cc_status.flags = CC_NOT_NEGATIVE;
-  return \"bftst %0{%b2:%b1}\";
-}")
-
-(define_insn "scc0_di"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-    (match_operator 1 "valid_dbcc_comparison_p"
-      [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
-  "! TARGET_5200"
-  "*
-{
-  return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
-} ")
-
-(define_insn "scc0_di_5200"
-  [(set (match_operand:QI 0 "general_operand" "=d")
-    (match_operator 1 "valid_dbcc_comparison_p"
-      [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
-  "TARGET_5200"
-  "*
-{
-  return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
-} ")
-
-(define_insn "scc_di"
-  [(set (match_operand:QI 0 "general_operand" "=dm,dm")
-    (match_operator 1 "valid_dbcc_comparison_p"
-      [(match_operand:DI 2 "general_operand" "ro,r")
-       (match_operand:DI 3 "general_operand" "r,ro")]))]
-  "! TARGET_5200"
-  "*
-{
-  return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
-} ")
-
-(define_insn "scc_di_5200"
-  [(set (match_operand:QI 0 "general_operand" "=d,d")
-    (match_operator 1 "valid_dbcc_comparison_p"
-      [(match_operand:DI 2 "general_operand" "ro,r")
-       (match_operand:DI 3 "general_operand" "r,ro")]))]
-  "TARGET_5200"
-  "*
-{
-  return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
-} ")
-
-(define_expand "seq"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(eq:QI (cc0) (const_int 0)))]
-  ""
-  "
-{
-  if (TARGET_68060 && m68k_last_compare_had_fp_operands)
-    {
-      m68k_last_compare_had_fp_operands = 0;
-      FAIL;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(eq:QI (cc0) (const_int 0)))]
-  "! TARGET_5200"
-  "*
-  cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
-")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(eq:QI (cc0) (const_int 0)))]
-  "TARGET_5200"
-  "*
-  cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
-")
-
-(define_expand "sne"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(ne:QI (cc0) (const_int 0)))]
-  ""
-  "
-{
-  if (TARGET_68060 && m68k_last_compare_had_fp_operands)
-    {
-      m68k_last_compare_had_fp_operands = 0;
-      FAIL;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(ne:QI (cc0) (const_int 0)))]
-  "! TARGET_5200"
-  "*
-  cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
-")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(ne:QI (cc0) (const_int 0)))]
-  "TARGET_5200"
-  "*
-  cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
-")
-
-(define_expand "sgt"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(gt:QI (cc0) (const_int 0)))]
-  ""
-  "
-{
-  if (TARGET_68060 && m68k_last_compare_had_fp_operands)
-    {
-      m68k_last_compare_had_fp_operands = 0;
-      FAIL;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(gt:QI (cc0) (const_int 0)))]
-  "! TARGET_5200"
-  "*
-  cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
-")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(gt:QI (cc0) (const_int 0)))]
-  "TARGET_5200"
-  "*
-  cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
-")
-
-(define_expand "sgtu"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(gtu:QI (cc0) (const_int 0)))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(gtu:QI (cc0) (const_int 0)))]
-  "! TARGET_5200"
-  "* cc_status = cc_prev_status;
-     return \"shi %0\"; ")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(gtu:QI (cc0) (const_int 0)))]
-  "TARGET_5200"
-  "* cc_status = cc_prev_status;
-     return \"shi %0\"; ")
-
-(define_expand "slt"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(lt:QI (cc0) (const_int 0)))]
-  ""
-  "
-{
-  if (TARGET_68060 && m68k_last_compare_had_fp_operands)
-    {
-      m68k_last_compare_had_fp_operands = 0;
-      FAIL;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(lt:QI (cc0) (const_int 0)))]
-  "! TARGET_5200"
-  "* cc_status = cc_prev_status;
-     OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(lt:QI (cc0) (const_int 0)))]
-  "TARGET_5200"
-  "* cc_status = cc_prev_status;
-     OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
-
-(define_expand "sltu"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(ltu:QI (cc0) (const_int 0)))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(ltu:QI (cc0) (const_int 0)))]
-  "! TARGET_5200"
-  "* cc_status = cc_prev_status;
-     return \"scs %0\"; ")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(ltu:QI (cc0) (const_int 0)))]
-  "TARGET_5200"
-  "* cc_status = cc_prev_status;
-     return \"scs %0\"; ")
-
-(define_expand "sge"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(ge:QI (cc0) (const_int 0)))]
-  ""
-  "
-{
-  if (TARGET_68060 && m68k_last_compare_had_fp_operands)
-    {
-      m68k_last_compare_had_fp_operands = 0;
-      FAIL;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(ge:QI (cc0) (const_int 0)))]
-  "! TARGET_5200"
-  "* cc_status = cc_prev_status;
-     OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(ge:QI (cc0) (const_int 0)))]
-  "TARGET_5200"
-  "* cc_status = cc_prev_status;
-     OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
-
-(define_expand "sgeu"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(geu:QI (cc0) (const_int 0)))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(geu:QI (cc0) (const_int 0)))]
-  "! TARGET_5200"
-  "* cc_status = cc_prev_status;
-     return \"scc %0\"; ")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(geu:QI (cc0) (const_int 0)))]
-  "TARGET_5200"
-  "* cc_status = cc_prev_status;
-     return \"scc %0\"; ")
-
-(define_expand "sle"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(le:QI (cc0) (const_int 0)))]
-  ""
-  "
-{
-  if (TARGET_68060 && m68k_last_compare_had_fp_operands)
-    {
-      m68k_last_compare_had_fp_operands = 0;
-      FAIL;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(le:QI (cc0) (const_int 0)))]
-  "! TARGET_5200"
-  "*
-  cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
-")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(le:QI (cc0) (const_int 0)))]
-  "TARGET_5200"
-  "*
-  cc_status = cc_prev_status;
-  OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
-")
-
-(define_expand "sleu"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(leu:QI (cc0) (const_int 0)))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(leu:QI (cc0) (const_int 0)))]
-  "! TARGET_5200"
-  "* cc_status = cc_prev_status;
-     return \"sls %0\"; ")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d")
-	(leu:QI (cc0) (const_int 0)))]
-  "TARGET_5200"
-  "* cc_status = cc_prev_status;
-     return \"sls %0\"; ")
-
-;; Basic conditional jump instructions.
-
-(define_insn "beq0_di"
-  [(set (pc)
-    (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
-            (const_int 0))
-        (label_ref (match_operand 1 "" ","))
-        (pc)))
-   (clobber (match_scratch:SI 2 "=d,d"))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (which_alternative == 1)
-#ifdef MOTOROLA
-    return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
-#else
-    return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
-#endif
-  if ((cc_prev_status.value1
-      && rtx_equal_p (cc_prev_status.value1, operands[0]))
-    || (cc_prev_status.value2
-      && rtx_equal_p (cc_prev_status.value2, operands[0])))
-    {
-      cc_status = cc_prev_status;
-#ifdef MOTOROLA
-      return \"jbeq %l1\";
-#else
-      return \"jeq %l1\";
-#endif
-    }
-  if (GET_CODE (operands[0]) == REG)
-    operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  else
-    operands[3] = adj_offsettable_operand (operands[0], 4);
-  if (! ADDRESS_REG_P (operands[0]))
-    {
-      if (reg_overlap_mentioned_p (operands[2], operands[0]))
-	{
-	  if (reg_overlap_mentioned_p (operands[2], operands[3]))
-	    {
-#ifdef MOTOROLA
-	      return \"or%.l %0,%2\;jbeq %l1\";
-#else
-	      return \"or%.l %0,%2\;jeq %l1\";
-#endif
-	    }
-	  else
-	    {
-#ifdef MOTOROLA
-	      return \"or%.l %3,%2\;jbeq %l1\";
-#else
-	      return \"or%.l %3,%2\;jeq %l1\";
-#endif
-	    }
-	}
-#ifdef MOTOROLA
-      return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
-#else
-      return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
-#endif
-    }
-  operands[4] = gen_label_rtx();
-  if (TARGET_68020 || TARGET_5200)
-    {
-#ifdef MOTOROLA
-      output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
-#else
-      output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
-#endif
-    }
-  else
-    {
-#ifdef MOTOROLA
-#ifdef SGS_CMP_ORDER
-      output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
-#else
-      output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
-#endif
-#else
-      output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
-#endif
-    }
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
-				CODE_LABEL_NUMBER (operands[4]));
-  return \"\";
-} ")
-
-(define_insn "bne0_di"
-  [(set (pc)
-    (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
-            (const_int 0))
-        (label_ref (match_operand 1 "" ","))
-        (pc)))
-   (clobber (match_scratch:SI 2 "=d,X"))]
-  ""
-  "*
-{
-  if ((cc_prev_status.value1
-      && rtx_equal_p (cc_prev_status.value1, operands[0]))
-    || (cc_prev_status.value2
-      && rtx_equal_p (cc_prev_status.value2, operands[0])))
-    {
-      cc_status = cc_prev_status;
-#ifdef MOTOROLA
-      return \"jbne %l1\";
-#else
-      return \"jne %l1\";
-#endif
-    }
-  CC_STATUS_INIT;
-  if (GET_CODE (operands[0]) == REG)
-    operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  else
-    operands[3] = adj_offsettable_operand (operands[0], 4);
-  if (!ADDRESS_REG_P (operands[0]))
-    {
-      if (reg_overlap_mentioned_p (operands[2], operands[0]))
-	{
-	  if (reg_overlap_mentioned_p (operands[2], operands[3]))
-	    {
-#ifdef MOTOROLA
-	      return \"or%.l %0,%2\;jbne %l1\";
-#else
-	      return \"or%.l %0,%2\;jne %l1\";
-#endif
-	    }
-	  else
-	    {
-#ifdef MOTOROLA
-	      return \"or%.l %3,%2\;jbne %l1\";
-#else
-	      return \"or%.l %3,%2\;jne %l1\";
-#endif
-	    }
-	}
-#ifdef MOTOROLA
-      return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
-#else
-      return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
-#endif
-    }
-  if (TARGET_68020 || TARGET_5200)
-    {
-#ifdef MOTOROLA
-      return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
-#else
-      return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
-#endif
-    }
-  else
-    {
-#ifdef MOTOROLA
-#ifdef SGS_CMP_ORDER
-      return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
-#else
-      return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
-#endif
-#else
-      return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
-#endif
-    }
-} ")
-
-(define_insn "bge0_di"
-  [(set (pc)
-    (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
-            (const_int 0))
-        (label_ref (match_operand 1 "" ""))
-        (pc)))]
-  ""
-  "*
-{
-  if ((cc_prev_status.value1
-      && rtx_equal_p (cc_prev_status.value1, operands[0]))
-    || (cc_prev_status.value2
-      && rtx_equal_p (cc_prev_status.value2, operands[0])))
-    {
-      cc_status = cc_prev_status;
-      if (cc_status.flags & CC_REVERSED)
-	{
-#ifdef MOTOROLA
-	  return \"jble %l1\";
-#else
-	  return \"jle %l1\";
-#endif
-	}
-      else
-	{
-#ifdef MOTOROLA
-	  return \"jbpl %l1\";
-#else
-	  return \"jpl %l1\";
-#endif
-	}
-    }
-  CC_STATUS_INIT;
-  if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
-    output_asm_insn(\"tst%.l %0\", operands);
-  else
-    {
-      /* On an address reg, cmpw may replace cmpl.  */
-#ifdef SGS_CMP_ORDER
-      output_asm_insn(\"cmp%.w %0,%#0\", operands);
-#else
-      output_asm_insn(\"cmp%.w %#0,%0\", operands);
-#endif
-    }
-
-#ifdef MOTOROLA
-  return \"jbpl %l1\";
-#else
-  return \"jpl %l1\";
-#endif
-} ")
-
-(define_insn "blt0_di"
-  [(set (pc)
-    (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
-            (const_int 0))
-        (label_ref (match_operand 1 "" ""))
-        (pc)))]
-  ""
-  "*
-{
-  if ((cc_prev_status.value1
-      && rtx_equal_p (cc_prev_status.value1, operands[0]))
-    || (cc_prev_status.value2
-      && rtx_equal_p (cc_prev_status.value2, operands[0])))
-    {
-      cc_status = cc_prev_status;
-      if (cc_status.flags & CC_REVERSED)
-	{
-#ifdef MOTOROLA
-	  return \"jbgt %l1\";
-#else
-	  return \"jgt %l1\";
-#endif
-	}
-      else
-	{
-#ifdef MOTOROLA
-	  return \"jbmi %l1\";
-#else
-	  return \"jmi %l1\";
-#endif
-	}
-    }
-  CC_STATUS_INIT;
-  if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
-    output_asm_insn(\"tst%.l %0\", operands);
-  else
-    {
-      /* On an address reg, cmpw may replace cmpl.  */
-#ifdef SGS_CMP_ORDER
-      output_asm_insn(\"cmp%.w %0,%#0\", operands);
-#else
-      output_asm_insn(\"cmp%.w %#0,%0\", operands);
-#endif
-    }
-
-#ifdef MOTOROLA
-  return \"jbmi %l1\";
-#else
-  return \"jmi %l1\";
-#endif
-} ")
-
-(define_insn "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-#ifdef MOTOROLA
-  OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
-#else
-  OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
-#endif
-}")
-
-(define_insn "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-#ifdef MOTOROLA
-  OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
-#else
-  OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
-#endif
-}")
-
-(define_insn "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-#ifdef MOTOROLA
-  OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
-#else
-  OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
-#endif
-")
-
-(define_insn "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-#ifdef MOTOROLA
-  return \"jbhi %l0\";
-#else
-  return \"jhi %l0\";
-#endif
-")
-
-(define_insn "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-#ifdef MOTOROLA
-  OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
-#else
-  OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
-#endif
-")
-
-(define_insn "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-#ifdef MOTOROLA
-  return \"jbcs %l0\";
-#else
-  return \"jcs %l0\";
-#endif
-")
-
-(define_insn "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-#ifdef MOTOROLA
-  OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
-#else
-  OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
-#endif
-")
-
-(define_insn "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-#ifdef MOTOROLA
-  return \"jbcc %l0\";
-#else
-  return \"jcc %l0\";
-#endif
-")
-
-(define_insn "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-#ifdef MOTOROLA
-  OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
-#else
-  OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
-#endif
-")
-
-(define_insn "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-#ifdef MOTOROLA
-  return \"jbls %l0\";
-#else
-  return \"jls %l0\";
-#endif
-")
-
-;; Negated conditional jump instructions.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-#ifdef MOTOROLA
-  OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
-#else
-  OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
-#endif
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-#ifdef MOTOROLA
-  OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
-#else
-  OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
-#endif
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-#ifdef MOTOROLA
-  OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
-#else
-  OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
-#endif
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-#ifdef MOTOROLA
-  return \"jbls %l0\";
-#else
-  return \"jls %l0\";
-#endif
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-#ifdef MOTOROLA
-  OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
-#else
-  OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
-#endif
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-#ifdef MOTOROLA
-  return \"jbcc %l0\";
-#else
-  return \"jcc %l0\";
-#endif
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-#ifdef MOTOROLA
-  OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
-#else
-  OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
-#endif
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-#ifdef MOTOROLA
-  return \"jbcs %l0\";
-#else
-  return \"jcs %l0\";
-#endif
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-#ifdef MOTOROLA
-  OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
-#else
-  OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
-#endif
-")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-#ifdef MOTOROLA
-  return \"jbhi %l0\";
-#else
-  return \"jhi %l0\";
-#endif
-")
-
-;; Unconditional and other jump instructions
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "*
-#ifdef MOTOROLA
-  return \"jbra %l0\";
-#else
-  return \"jra %l0\";
-#endif
-")
-
-;; We support two different ways of handling dispatch tables.
-;; The NeXT uses absolute tables, and other machines use relative.
-;; This define_expand can generate either kind.
-(define_expand "tablejump"
-  [(parallel [(set (pc) (match_operand 0 "" ""))
-	      (use (label_ref (match_operand 1 "" "")))])]
-  ""
-  "
-{
-#ifdef CASE_VECTOR_PC_RELATIVE
-    operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
-				gen_rtx_SIGN_EXTEND (SImode, operands[0]));
-#endif
-}")
-
-;; Jump to variable address from dispatch table of absolute addresses.
-(define_insn ""
-  [(set (pc) (match_operand:SI 0 "register_operand" "a"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "*
-#ifdef MOTOROLA
-  return \"jmp (%0)\";
-#else
-  return \"jmp %0@\";
-#endif
-")
-
-;; Jump to variable address from dispatch table of relative addresses.
-(define_insn ""
-  [(set (pc)
-	(plus:SI (pc)
-		 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "*
-#ifdef ASM_RETURN_CASE_JUMP
- ASM_RETURN_CASE_JUMP;
-#else
-#ifdef SGS
-#ifdef ASM_OUTPUT_CASE_LABEL
-  if (TARGET_5200) 
-    return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
-  else
-    return \"jmp 6(%%pc,%0.w)\";
-#else
-  if (TARGET_5200)
-    {
-#ifdef CRDS
-      return \"ext%.l %0\;jmp 2(pc,%0.l)\";
-#else
-      return \"extl %0\;jmp 2(%%pc,%0.l)\";
-#endif  /* end !CRDS */
-    }
-  else
-    {
-#ifdef CRDS
-      return \"jmp 2(pc,%0.w)\";
-#else
-      return \"jmp 2(%%pc,%0.w)\";
-#endif  /* end !CRDS */
-    }
-#endif
-#else /* not SGS */
-  if (TARGET_5200)
-    {
-#ifdef MOTOROLA
-      return \"ext%.l %0\;jmp (2,pc,%0.l)\";
-#else
-      return \"extl %0\;jmp pc@(2,%0:l)\";
-#endif
-    }
-  else
-    {
-#ifdef MOTOROLA
-      return \"jmp (2,pc,%0.w)\";
-#else
-      return \"jmp pc@(2,%0:w)\";
-#endif
-    }
-#endif
-#endif
-")
-
-;; Decrement-and-branch insns.
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (match_operand:HI 0 "general_operand" "+d*g")
-	     (const_int 0))
-	 (label_ref (match_operand 1 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:HI (match_dup 0)
-		 (const_int -1)))]
-  "!TARGET_5200"
-  "*
-{
-  CC_STATUS_INIT;
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    {
-#ifdef MOTOROLA
-#ifdef NO_ADDSUB_Q
-      return \"sub%.w %#1,%0\;jbcc %l1\";
-#else
-      return \"subq%.w %#1,%0\;jbcc %l1\";
-#endif
-#else /* not MOTOROLA */
-      return \"subqw %#1,%0\;jcc %l1\";
-#endif
-    }
-#ifdef MOTOROLA
-#ifdef SGS_CMP_ORDER
-#ifdef NO_ADDSUB_Q
-  return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
-#else
-  return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
-#endif
-#else /* not SGS_CMP_ORDER */
-  return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
-#endif
-#else /* not MOTOROLA */
-  return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
-#endif
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (match_operand:SI 0 "general_operand" "+d*g")
-	     (const_int 0))
-	 (label_ref (match_operand 1 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  "!TARGET_5200"
-  "*
-{
-  CC_STATUS_INIT;
-#ifdef MOTOROLA
-#ifdef NO_ADDSUB_Q
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    return \"sub%.l %#1,%0\;jbcc %l1\";
-#else
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    return \"subq%.l %#1,%0\;jbcc %l1\";
-#endif /* NO_ADDSUB_Q */
-#ifdef SGS_CMP_ORDER
-#ifdef NO_ADDSUB_Q
-  return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
-#else
-  return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
-#endif
-#else /* not SGS_CMP_ORDER */
-  return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
-#endif /* not SGS_CMP_ORDER */
-#else /* not MOTOROLA */
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    return \"subql %#1,%0\;jcc %l1\";
-  return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
-#endif /* not MOTOROLA */
-}")
-
-;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	  (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
-		       (const_int -1))
-	      (const_int 0))
-	  (label_ref (match_operand 1 "" ""))
-	  (pc)))
-   (set (match_dup 0)
-	(plus:HI (match_dup 0)
-		 (const_int -1)))]
-  "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
-  "*
-{
-  CC_STATUS_INIT;
-#ifdef MOTOROLA
-#ifdef NO_ADDSUB_Q
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    return \"sub%.w %#1,%0\;jbcc %l1\";
-#else
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    return \"subq%.w %#1,%0\;jbcc %l1\";
-#endif
-#ifdef SGS_CMP_ORDER
-#ifdef NO_ADDSUB_Q
-  return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
-#else
-  return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
-#endif
-#else /* not SGS_CMP_ORDER */
-  return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
-#endif /* not SGS_CMP_ORDER */
-#else /* not MOTOROLA */
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    return \"subqw %#1,%0\;jcc %l1\";
-  return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
-#endif /* not MOTOROLA */
-}")
-
-(define_expand "decrement_and_branch_until_zero"
-  [(parallel [(set (pc)
-		   (if_then_else
-		    (ge (plus:SI (match_operand:SI 0 "general_operand" "")
-				 (const_int -1))
-			(const_int 0))
-		    (label_ref (match_operand 1 "" ""))
-		    (pc)))
-	      (set (match_dup 0)
-		   (plus:SI (match_dup 0)
-			    (const_int -1)))])]
-  ""
-  "")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	  (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
-		       (const_int -1))
-	      (const_int 0))
-	  (label_ref (match_operand 1 "" ""))
-	  (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
-  "*
-{
-  CC_STATUS_INIT;
-#ifdef MOTOROLA
-#ifdef NO_ADDSUB_Q
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    return \"sub%.l %#1,%0\;jbcc %l1\";
-#else
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    return \"subq%.l %#1,%0\;jbcc %l1\";
-#endif
-#ifdef SGS_CMP_ORDER
-#ifdef NO_ADDSUB_Q
-  return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
-#else
-  return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
-#endif
-#else /* not SGS_CMP_ORDER */
-  return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
-#endif /* not SGS_CMP_ORDER */
-#else /* not MOTOROLA */
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    return \"subql %#1,%0\;jcc %l1\";
-  return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
-#endif /* not MOTOROLA */
-}")
-
-
-;; For PIC calls, in order to be able to support
-;; dynamic linker LAZY BINDING, all the procedure calls need to go
-;; through the PLT (Procedure Linkage Table) section in PIC mode.
-;;
-;; PIC calls are handled by loading the address of the function into a
-;; register (via movsi), then emitting a register indirect call using
-;; the "jsr" function call syntax.
-;;
-;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
-;; operand to the jbsr statement to indicate that this call should
-;; go through the PLT (why? because this is the way that Sun does it).
-;;
-;; We have different patterns for PIC calls and non-PIC calls.  The
-;; different patterns are only used to choose the right syntax.
-;;
-;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
-;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
-;; that tells the linker editor to create an entry for `FUNC' in PLT
-;; section at link time. However, all global objects reference are still
-;; done by using `OBJ@GOT'. So, the goal here is to output the function
-;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
-;; We need to have a way to differentiate these two different operands.
-;;
-;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
-;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
-;; to be changed to recognize function calls symbol_ref operand as a valid
-;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
-;; avoid the compiler to load this symbol_ref operand into a register.
-;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
-;; since the value is a PC relative offset, not a real address.
-;;
-;; All global objects are treated in the similar way as in SUN3. The only
-;; difference is: on m68k svr4, the reference of such global object needs
-;; to end with a suffix "@GOT" so the assembler and linker know to create
-;; an entry for it in GOT (Global Offset Table) section. This is done in
-;; m68k.c.
-
-;; Call subroutine with no return value.
-(define_expand "call"
-  [(call (match_operand:QI 0 "memory_operand" "")
-	 (match_operand:SI 1 "general_operand" ""))]
-  ;; Operand 1 not really used on the m68000.
-
-  ""
-  "
-{
-  if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
-    SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
-}")
-
-;; This is a normal call sequence.
-(define_insn ""
-  [(call (match_operand:QI 0 "memory_operand" "o")
-	 (match_operand:SI 1 "general_operand" "g"))]
-  ;; Operand 1 not really used on the m68000.
-
-  "! flag_pic"
-  "*
-#if defined (MOTOROLA) && !defined (USE_GAS)
-#ifdef MOTOROLA_BSR
-  if (GET_CODE (operands[0]) == MEM
-      && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
-    return \"bsr %0\";
-#endif
-  return \"jsr %0\";
-#else
-  return \"jbsr %0\";
-#endif
-")
-
-;; This is a PIC call sequence.
-(define_insn ""
-  [(call (match_operand:QI 0 "memory_operand" "o")
-	 (match_operand:SI 1 "general_operand" "g"))]
-  ;; Operand 1 not really used on the m68000.
-
-  "flag_pic"
-  "*
-  if (GET_CODE (operands[0]) == MEM
-      && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
-#ifdef MOTOROLA
-#ifdef HPUX_ASM
-    return \"bsr.l %0\";
-#else
-#ifdef USE_GAS
-    return \"bsr.l %0@PLTPC\";
-#else
-    return \"bsr %0@PLTPC\";
-#endif
-#endif
-#else
-    /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
-       GAS just plain ignores it.  */
-    return \"jbsr %0,a1\";
-#endif
-  return \"jsr %0\";
-")
-
-;; Call subroutine, returning value in operand 0
-;; (which must be a hard register).
-;; See comments before "call" regarding PIC calls.
-(define_expand "call_value"
-  [(set (match_operand 0 "" "")
-	(call (match_operand:QI 1 "memory_operand" "")
-     (match_operand:SI 2 "general_operand" "")))]
-  ;; Operand 2 not really used on the m68000.
-  ""
-  "
-{
-  if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
-    SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
-}")
-
-;; This is a normal call_value
-(define_insn ""
-  [(set (match_operand 0 "" "=rf")
-	(call (match_operand:QI 1 "memory_operand" "o")
-	      (match_operand:SI 2 "general_operand" "g")))]
-  ;; Operand 2 not really used on the m68000.
-  "! flag_pic"
-  "*
-#if defined (MOTOROLA) && !defined (USE_GAS)
-#ifdef MOTOROLA_BSR
-  if (GET_CODE (operands[1]) == MEM
-      && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
-    return \"bsr %1\";
-#endif
-  return \"jsr %1\";
-#else
-  return \"jbsr %1\";
-#endif
-")
-
-;; This is a PIC call_value
-(define_insn ""
-  [(set (match_operand 0 "" "=rf")
-	(call (match_operand:QI 1 "memory_operand" "o")
-	      (match_operand:SI 2 "general_operand" "g")))]
-  ;; Operand 2 not really used on the m68000.
-  "flag_pic"
-  "*
-  if (GET_CODE (operands[1]) == MEM
-      && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
-    {
-#ifdef MOTOROLA
-#ifdef HPUX_ASM
-      return \"bsr.l %1\";
-#else
-#ifdef USE_GAS
-      return \"bsr.l %1@PLTPC\";
-#else
-      return \"bsr %1@PLTPC\";
-#endif
-#endif
-#else
-      /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
-         GAS just plain ignores it.  */
-      return \"jbsr %1,a1\";
-#endif
-    }
-  return \"jsr %1\";
-")
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  "NEEDS_UNTYPED_CALL"
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
-
-(define_insn "probe"
- [(reg:SI 15)]
- "NEED_PROBE"
- "*
-{
-  operands[0] = gen_rtx_PLUS (SImode, stack_pointer_rtx,
-			      GEN_INT (NEED_PROBE));
-  return \"tstl %a0\";
-}")
-
-;; Used for frameless functions which save no regs and allocate no locals.
-(define_insn "return"
-  [(return)]
-  "USE_RETURN_INSN"
-  "*
-{
-  if (current_function_pops_args == 0)
-    return \"rts\";
-  operands[0] = GEN_INT (current_function_pops_args);
-  return \"rtd %0\";
-}")
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
-  ""
-  "jmp %a0")
-
-;; This should not be used unless the add/sub insns can't be.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=a")
-	(match_operand:QI 1 "address_operand" "p"))]
-  ""
-  "*
-{
-#ifndef SGS_NO_LI
-  /* Recognize an insn that refers to a table of offsets.  Such an insn will
-     need to refer to a label on the insn.  So output one.  Use the
-     label-number of the table of offsets to generate this label.  This code,
-     and similar code above, assumes that there will be at most one reference
-     to each table.  */
-  if (GET_CODE (operands[1]) == PLUS
-      && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
-      && GET_CODE (XEXP (operands[1], 0)) != PLUS)
-    {
-      rtx labelref = XEXP (operands[1], 1);
-#if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
-#ifdef SGS
-      asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
-		   CODE_LABEL_NUMBER (XEXP (labelref, 0)));
-#else /* not SGS */
-      asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
-	           CODE_LABEL_NUMBER (XEXP (labelref, 0)));
-#endif /* not SGS */
-#else /* SGS_SWITCH_TABLES or not MOTOROLA */
-      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
-				 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
-#ifdef SGS_SWITCH_TABLES
-      /* Set flag saying we need to define the symbol
-	 LD%n (with value L%n-LI%n) at the end of the switch table.  */
-      switch_table_difference_label_flag = 1;
-#endif /* SGS_SWITCH_TABLES */
-#endif /* SGS_SWITCH_TABLES or not MOTOROLA */
-    }
-#endif /* SGS_NO_LI */
-
-  return \"lea %a1,%0\";
-}")
-
-;; This is the first machine-dependent peephole optimization.
-;; It is useful when a floating value is returned from a function call
-;; and then is moved into an FP register.
-;; But it is mainly intended to test the support for these optimizations.
-
-(define_peephole
-  [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
-   (set (match_operand:DF 0 "register_operand" "=f")
-	(match_operand:DF 1 "register_operand" "ad"))]
-  "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
-  "*
-{
-  rtx xoperands[2];
-  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-  output_asm_insn (\"move%.l %1,%@\", xoperands);
-  output_asm_insn (\"move%.l %1,%-\", operands);
-  return \"fmove%.d %+,%0\";
-}
-")
-
-;; Optimize a stack-adjust followed by a push of an argument.
-;; This is said to happen frequently with -msoft-float
-;; when there are consecutive library calls.
-
-(define_peephole
-  [(set (reg:SI 15) (plus:SI (reg:SI 15)
-			     (match_operand:SI 0 "const_int_operand" "n")))
-   (set (match_operand:SF 1 "push_operand" "=m")
-	(match_operand:SF 2 "general_operand" "rmfF"))]
-  "INTVAL (operands[0]) >= 4
-   && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
-  "*
-{
-  if (INTVAL (operands[0]) > 4)
-    {
-      rtx xoperands[2];
-      xoperands[0] = stack_pointer_rtx;
-      xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
-#ifndef NO_ADDSUB_Q
-      if (INTVAL (xoperands[1]) <= 8)
-	{
-	  if (!TARGET_5200)
-	    output_asm_insn (\"addq%.w %1,%0\", xoperands);
-	  else
-	    output_asm_insn (\"addq%.l %1,%0\", xoperands);
-	}
-      else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16) 
-	{
-	  xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
-	  output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
-	}
-      else
-#endif
-        if (INTVAL (xoperands[1]) <= 0x7FFF)
-        {
-	  if (TARGET_68040)
-	    output_asm_insn (\"add%.w %1,%0\", xoperands);
-	  else
-#ifdef MOTOROLA  
-	    output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
-#else
-	    output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
-#endif
-        }
-      else
-        output_asm_insn (\"add%.l %1,%0\", xoperands);
-    }
-  if (FP_REG_P (operands[2]))
-    return \"fmove%.s %2,%@\";
-  return \"move%.l %2,%@\";
-}")
-
-;; Speed up stack adjust followed by a fullword fixedpoint push.
-
-(define_peephole
-  [(set (reg:SI 15) (plus:SI (reg:SI 15)
-			     (match_operand:SI 0 "const_int_operand" "n")))
-   (set (match_operand:SI 1 "push_operand" "=m")
-	(match_operand:SI 2 "general_operand" "g"))]
-  "INTVAL (operands[0]) >= 4
-   && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
-  "*
-{
-  if (INTVAL (operands[0]) > 4)
-    {
-      rtx xoperands[2];
-      xoperands[0] = stack_pointer_rtx;
-      xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
-#ifndef NO_ADDSUB_Q
-      if (INTVAL (xoperands[1]) <= 8)
-	{
-	  if (!TARGET_5200)
-	    output_asm_insn (\"addq%.w %1,%0\", xoperands);
-	  else
-	    output_asm_insn (\"addq%.l %1,%0\", xoperands);
-	}
-      else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
-	{
-	  xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
-	  output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
-	}
-      else
-#endif
-        if (INTVAL (xoperands[1]) <= 0x7FFF)
-        {
-	  if (TARGET_68040)
-	    output_asm_insn (\"add%.w %1,%0\", xoperands);
-	  else
-	    {
-#ifdef MOTOROLA  
-	      output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
-#else
-	      output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
-#endif
-	    }
-        }
-      else
-        output_asm_insn (\"add%.l %1,%0\", xoperands);
-    }
-  if (operands[2] == const0_rtx)
-    return \"clr%.l %@\";
-  return \"move%.l %2,%@\";
-}")
-
-;; Speed up pushing a single byte but leaving four bytes of space.
-
-(define_peephole
-  [(set (mem:QI (pre_dec:SI (reg:SI 15)))
-	(match_operand:QI 1 "general_operand" "dami"))
-   (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
-  "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
-  "*
-{
-  rtx xoperands[4];
-
-  if (GET_CODE (operands[1]) == REG)
-    return \"move%.l %1,%-\";
-
-  xoperands[1] = operands[1];
-  xoperands[2]
-    = gen_rtx_MEM (QImode,
-		   gen_rtx_PLUS (VOIDmode, stack_pointer_rtx,
-				 GEN_INT (3)));
-  xoperands[3] = stack_pointer_rtx;
-  if (!TARGET_5200)
-    output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
-  else
-    output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
-  return \"\";
-}")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(const_int 0))
-   (set (strict_low_part (subreg:HI (match_dup 0) 0))
-	(match_operand:HI 1 "general_operand" "rmn"))]
-  "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      if (operands[1] == const0_rtx
-	  && (DATA_REG_P (operands[0])
-	      || GET_CODE (operands[0]) == MEM)
-	  /* clr insns on 68000 read before writing.
-	     This isn't so on the 68010, but we have no TARGET_68010.  */
-	  && ((TARGET_68020 || TARGET_5200)
-	      || !(GET_CODE (operands[0]) == MEM
-		   && MEM_VOLATILE_P (operands[0]))))
-	return \"clr%.w %0\";
-    }
-  return \"move%.w %1,%0\";
-}")
-
-;; dbCC peepholes
-;;
-;; Turns
-;;   loop:
-;;           [ ... ]
-;;           jCC label		; abnormal loop termination
-;;           dbra dN, loop	; normal loop termination
-;;
-;; Into
-;;   loop:
-;;           [ ... ]
-;;           dbCC dN, loop
-;;           jCC label
-;;
-;; Which moves the jCC condition outside the inner loop for free.
-;;
-(define_peephole
-  [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
-                             [(cc0) (const_int 0)])
-                           (label_ref (match_operand 2 "" ""))
-                           (pc)))
-   (parallel
-    [(set (pc)
-	  (if_then_else
-	    (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
-		         (const_int -1))
-	        (const_int 0))
-	    (label_ref (match_operand 1 "" ""))
-	    (pc)))
-     (set (match_dup 0)
-	  (plus:HI (match_dup 0)
-		   (const_int -1)))])]
-  "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
-  "*
-{
-  CC_STATUS_INIT;
-  output_dbcc_and_branch (operands);
-  return \"\";
-}")
-
-(define_peephole
-  [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
-                             [(cc0) (const_int 0)])
-                           (label_ref (match_operand 2 "" ""))
-                           (pc)))
-   (parallel
-    [(set (pc)
-	  (if_then_else
-	    (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
-		         (const_int -1))
-	        (const_int 0))
-	    (label_ref (match_operand 1 "" ""))
-	    (pc)))
-     (set (match_dup 0)
-	  (plus:SI (match_dup 0)
-		   (const_int -1)))])]
-  "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
-  "*
-{
-  CC_STATUS_INIT;
-  output_dbcc_and_branch (operands);
-  return \"\";
-}")
-
-
-;; FPA multiply and add.
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=x,y,y")
-	(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
-			  (match_operand:DF 2 "general_operand" "xH,y,y"))
-		 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
-   "TARGET_FPA"
-   "@
-    fpma%.d %1,%w2,%w3,%0
-    fpma%.d %x1,%x2,%x3,%0
-    fpma%.d %x1,%x2,%x3,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=x,y,y")
-	(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
-			  (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
-		 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
-   "TARGET_FPA"
-   "@
-    fpma%.s %1,%w2,%w3,%0
-    fpma%.s %1,%2,%3,%0
-    fpma%.s %1,%2,%3,%0")
-
-;; FPA Multiply and subtract
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=x,y,y")
-	(minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
-		  (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
-			   (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
-  "TARGET_FPA"
-  "@
-   fpms%.d %3,%w2,%w1,%0
-   fpms%.d %x3,%2,%x1,%0
-   fpms%.d %x3,%2,%x1,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=x,y,y")
-	(minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
-		  (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
-			   (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
-  "TARGET_FPA"
-  "@
-   fpms%.s %3,%w2,%w1,%0
-   fpms%.s %3,%2,%1,%0
-   fpms%.s %3,%2,%1,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=x,y,y")
-	(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
-			   (match_operand:DF 2 "general_operand" "x,y,rmF"))
-		  (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
-  "TARGET_FPA"
-  "@
-   fpmr%.d %2,%w1,%w3,%0
-   fpmr%.d %x2,%1,%x3,%0
-   fpmr%.d %x2,%1,%x3,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=x,y,y")
-	(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
-			   (match_operand:SF 2 "general_operand" "x,y,yrmF"))
-		  (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
-  "TARGET_FPA"
-  "@
-   fpmr%.s %2,%w1,%w3,%0
-   fpmr%.s %x2,%1,%x3,%0
-   fpmr%.s %x2,%1,%x3,%0")
-
-;; FPA Add and multiply
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=x,y,y")
-	(mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
-			  (match_operand:DF 2 "general_operand" "x,y,rmF"))
-		 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
-  "TARGET_FPA"
-  "@
-   fpam%.d %2,%w1,%w3,%0
-   fpam%.d %x2,%1,%x3,%0
-   fpam%.d %x2,%1,%x3,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=x,y,y")
-	(mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
-			  (match_operand:SF 2 "general_operand" "x,y,yrmF"))
-		 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
-  "TARGET_FPA"
-  "@
-   fpam%.s %2,%w1,%w3,%0
-   fpam%.s %x2,%1,%x3,%0
-   fpam%.s %x2,%1,%x3,%0")
-
-;;FPA Subtract and multiply
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=x,y,y")
-	(mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
-			   (match_operand:DF 2 "general_operand" "x,y,rmF"))
-		 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
-  "TARGET_FPA"
-  "@
-   fpsm%.d %2,%w1,%w3,%0
-   fpsm%.d %x2,%1,%x3,%0
-   fpsm%.d %x2,%1,%x3,%0")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=x,y,y")
-	(mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
-		 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
-			   (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
-  "TARGET_FPA"
-  "@
-   fpsm%.d %3,%w2,%w1,%0
-   fpsm%.d %x3,%2,%x1,%0
-   fpsm%.d %x3,%2,%x1,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=x,y,y")
-	(mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
-			   (match_operand:SF 2 "general_operand" "x,y,yrmF"))
-		 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
-  "TARGET_FPA"
-  "@
-   fpsm%.s %2,%w1,%w3,%0
-   fpsm%.s %x2,%1,%x3,%0
-   fpsm%.s %x2,%1,%x3,%0")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=x,y,y")
-	(mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
-		 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
-			   (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
-  "TARGET_FPA"
-  "@
-   fpsm%.s %3,%w2,%w1,%0
-   fpsm%.s %x3,%2,%x1,%0
-   fpsm%.s %x3,%2,%x1,%0")
-
-(define_expand "tstxf"
-  [(set (cc0)
-	(match_operand:XF 0 "nonimmediate_operand" ""))]
-  "TARGET_68881"
-  "m68k_last_compare_had_fp_operands = 1;")
-
-(define_insn ""
-  [(set (cc0)
-	(match_operand:XF 0 "nonimmediate_operand" "fm"))]
-  "TARGET_68881"
-  "*
-{
-  cc_status.flags = CC_IN_68881;
-  return \"ftst%.x %0\";
-}")
-
-(define_expand "cmpxf"
-  [(set (cc0)
-	(compare (match_operand:XF 0 "nonimmediate_operand" "")
-		 (match_operand:XF 1 "nonimmediate_operand" "")))]
-  "TARGET_68881"
-  "m68k_last_compare_had_fp_operands = 1;")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
-		 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
-  "TARGET_68881"
-  "*
-{
-  cc_status.flags = CC_IN_68881;
-#ifdef SGS_CMP_ORDER
-  if (REG_P (operands[0]))
-    {
-      if (REG_P (operands[1]))
-	return \"fcmp%.x %0,%1\";
-      else
-        return \"fcmp%.x %0,%f1\";
-    }
-  cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.x %1,%f0\";
-#else
-  if (REG_P (operands[0]))
-    {
-      if (REG_P (operands[1]))
-	return \"fcmp%.x %1,%0\";
-      else
-        return \"fcmp%.x %f1,%0\";
-    }
-  cc_status.flags |= CC_REVERSED;
-  return \"fcmp%.x %f0,%1\";
-#endif
-}")
-
-(define_insn "extendsfxf2"
-  [(set (match_operand:XF 0 "general_operand" "=fm,f")
-	(float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
-  "TARGET_68881"
-  "*
-{
-  if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
-    {
-      if (REGNO (operands[0]) == REGNO (operands[1]))
-	{
-	  /* Extending float to double in an fp-reg is a no-op.
-	     NOTICE_UPDATE_CC has already assumed that the
-	     cc will be set.  So cancel what it did.  */
-	  cc_status = cc_prev_status;
-	  return \"\";
-	}
-      return \"f%$move%.x %1,%0\";
-    }
-  if (FP_REG_P (operands[0]))
-    return \"f%$move%.s %f1,%0\";
-  return \"fmove%.x %f1,%0\";
-}")
-
-
-(define_insn "extenddfxf2"
-  [(set (match_operand:XF 0 "general_operand" "=fm,f")
-	(float_extend:XF
-          (match_operand:DF 1 "general_operand" "f,m")))]
-  "TARGET_68881"
-  "*
-{
-  if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
-    {
-      if (REGNO (operands[0]) == REGNO (operands[1]))
-	{
-	  /* Extending float to double in an fp-reg is a no-op.
-	     NOTICE_UPDATE_CC has already assumed that the
-	     cc will be set.  So cancel what it did.  */
-	  cc_status = cc_prev_status;
-	  return \"\";
-	}
-      return \"fmove%.x %1,%0\";
-    }
-  if (FP_REG_P (operands[0]))
-    return \"f%&move%.d %f1,%0\";
-  return \"fmove%.x %f1,%0\";
-}")
-
-(define_insn "truncxfdf2"
-  [(set (match_operand:DF 0 "general_operand" "=m,!r")
-	(float_truncate:DF
-          (match_operand:XF 1 "general_operand" "f,f")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[0]))
-    {
-      output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
-      operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-      return \"move%.l %+,%0\";
-    }
-  return \"fmove%.d %f1,%0\";
-}")
-
-(define_insn "truncxfsf2"
-  [(set (match_operand:SF 0 "general_operand" "=dm")
-	(float_truncate:SF
-	  (match_operand:XF 1 "general_operand" "f")))]
-  "TARGET_68881"
-  "fmove%.s %f1,%0")
-
-(define_insn "floatsixf2"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(float:XF (match_operand:SI 1 "general_operand" "dmi")))]
-  "TARGET_68881"
-  "fmove%.l %1,%0")
-
-(define_insn "floathixf2"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(float:XF (match_operand:HI 1 "general_operand" "dmn")))]
-  "TARGET_68881"
-  "fmove%.w %1,%0")
-
-(define_insn "floatqixf2"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(float:XF (match_operand:QI 1 "general_operand" "dmn")))]
-  "TARGET_68881"
-  "fmove%.b %1,%0")
-
-(define_insn "ftruncxf2"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
-  "TARGET_68881"
-  "*
-{
-  if (FP_REG_P (operands[1]))
-    return \"fintrz%.x %f1,%0\";
-  return \"fintrz%.x %f1,%0\";
-}")
-
-(define_insn "fixxfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=dm")
-	(fix:QI (match_operand:XF 1 "general_operand" "f")))]
-  "TARGET_68881"
-  "fmove%.b %1,%0")
-
-(define_insn "fixxfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=dm")
-	(fix:HI (match_operand:XF 1 "general_operand" "f")))]
-  "TARGET_68881"
-  "fmove%.w %1,%0")
-
-(define_insn "fixxfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=dm")
-	(fix:SI (match_operand:XF 1 "general_operand" "f")))]
-  "TARGET_68881"
-  "fmove%.l %1,%0")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
-		 (match_operand:XF 1 "nonimmediate_operand" "0")))]
-  "TARGET_68881"
-  "fadd%.l %2,%0")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
-		 (match_operand:XF 1 "nonimmediate_operand" "0")))]
-  "TARGET_68881"
-  "fadd%.w %2,%0")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
-		 (match_operand:XF 1 "general_operand" "0")))]
-  "TARGET_68881"
-  "fadd%.b %2,%0")
-
-(define_insn "addxf3"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
-		 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[2]))
-    return \"fadd%.x %2,%0\";
-  return \"fadd%.x %f2,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
-		  (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
-  "TARGET_68881"
-  "fsub%.l %2,%0")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
-		  (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
-  "TARGET_68881"
-  "fsub%.w %2,%0")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
-		  (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
-  "TARGET_68881"
-  "fsub%.b %2,%0")
-
-(define_insn "subxf3"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
-		  (match_operand:XF 2 "nonimmediate_operand" "fm")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[2]))
-    return \"fsub%.x %2,%0\";
-  return \"fsub%.x %f2,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
-		 (match_operand:XF 1 "nonimmediate_operand" "0")))]
-  "TARGET_68881"
-  "fmul%.l %2,%0")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
-		 (match_operand:XF 1 "nonimmediate_operand" "0")))]
-  "TARGET_68881"
-  "fmul%.w %2,%0")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
-		 (match_operand:XF 1 "nonimmediate_operand" "0")))]
-  "TARGET_68881"
-  "fmul%.b %2,%0")
-
-(define_insn "mulxf3"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
-		 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[2]))
-    return \"fmul%.x %2,%0\";
-  return \"fmul%.x %f2,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
-		(float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
-  "TARGET_68881"
-  "fdiv%.l %2,%0")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
-		(float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
-  "TARGET_68881"
-  "fdiv%.w %2,%0")
-
-(define_insn ""
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
-		(float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
-  "TARGET_68881"
-  "fdiv%.b %2,%0")
-
-(define_insn "divxf3"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
-		(match_operand:XF 2 "nonimmediate_operand" "fm")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[2]))
-    return \"fdiv%.x %2,%0\";
-  return \"fdiv%.x %f2,%0\";
-}")
-
-(define_expand "negxf2"
-  [(set (match_operand:XF 0 "general_operand" "")
-	(neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  /* ??? There isn't an FPA define_insn so we could handle it here too.
-     For now we don't (paranoia).  */
-  if (!TARGET_68881)
-    {
-      rtx result;
-      rtx target;
-      rtx insns;
-
-      start_sequence ();
-      target = operand_subword (operands[0], 0, 1, XFmode);
-      result = expand_binop (SImode, xor_optab,
-			     operand_subword_force (operands[1], 0, XFmode),
-			     GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
-      if (result == 0)
-	abort ();
-
-      if (result != target)
-	emit_move_insn (result, target);
-
-      emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
-		      operand_subword_force (operands[1], 1, XFmode));
-      emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
-		      operand_subword_force (operands[1], 2, XFmode));
-
-      insns = get_insns ();
-      end_sequence ();
-
-      emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
-      DONE;
-    }
-}")
-
-(define_insn "negxf2_68881"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return \"fneg%.x %1,%0\";
-  return \"fneg%.x %f1,%0\";
-}")
-
-(define_expand "absxf2"
-  [(set (match_operand:XF 0 "general_operand" "")
-	(abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  /* ??? There isn't an FPA define_insn so we could handle it here too.
-     For now we don't (paranoia).  */
-  if (!TARGET_68881)
-    {
-      rtx result;
-      rtx target;
-      rtx insns;
-
-      start_sequence ();
-      target = operand_subword (operands[0], 0, 1, XFmode);
-      result = expand_binop (SImode, and_optab,
-			     operand_subword_force (operands[1], 0, XFmode),
-			     GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
-      if (result == 0)
-	abort ();
-
-      if (result != target)
-	emit_move_insn (result, target);
-
-      emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
-		      operand_subword_force (operands[1], 1, XFmode));
-      emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
-		      operand_subword_force (operands[1], 2, XFmode));
-
-      insns = get_insns ();
-      end_sequence ();
-
-      emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
-      DONE;
-    }
-}")
-
-(define_insn "absxf2_68881"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
-  "TARGET_68881"
-  "*
-{
-  if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
-    return \"fabs%.x %1,%0\";
-  return \"fabs%.x %f1,%0\";
-}")
-
-(define_insn "sqrtxf2"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
-  "TARGET_68881"
-  "fsqrt%.x %1,%0")
-
-(define_insn "sinsf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
-  "TARGET_68881 && flag_fast_math"
-  "*
-{
-  if (FP_REG_P (operands[1]))
-    return \"fsin%.x %1,%0\";
-  else
-    return \"fsin%.s %1,%0\";
-}")
-
-(define_insn "sindf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
-  "TARGET_68881 && flag_fast_math"
-  "*
-{
-  if (FP_REG_P (operands[1]))
-    return \"fsin%.x %1,%0\";
-  else
-    return \"fsin%.d %1,%0\";
-}")
-
-(define_insn "sinxf2"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
-  "TARGET_68881 && flag_fast_math"
-  "fsin%.x %1,%0")
-
-(define_insn "cossf2"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-	(unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
-  "TARGET_68881 && flag_fast_math"
-  "*
-{
-  if (FP_REG_P (operands[1]))
-    return \"fcos%.x %1,%0\";
-  else
-    return \"fcos%.s %1,%0\";
-}")
-
-(define_insn "cosdf2"
-  [(set (match_operand:DF 0 "general_operand" "=f")
-	(unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
-  "TARGET_68881 && flag_fast_math"
-  "*
-{
-  if (FP_REG_P (operands[1]))
-    return \"fcos%.x %1,%0\";
-  else
-    return \"fcos%.d %1,%0\";
-}")
-
-(define_insn "cosxf2"
-  [(set (match_operand:XF 0 "general_operand" "=f")
-	(unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
-  "TARGET_68881 && flag_fast_math"
-  "fcos%.x %1,%0")
diff --git a/gcc/config/m68k/m68kelf.h b/gcc/config/m68k/m68kelf.h
deleted file mode 100755
index 0257d1b..0000000
--- a/gcc/config/m68k/m68kelf.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/* m68kelf support, derived from m68kv4.h */
-
-/* Target definitions for GNU compiler for mc680x0 running System V.4
-   Copyright (C) 1991, 1993 Free Software Foundation, Inc.
-
-   Written by Ron Guilmette (rfg@netcom.com) and Fred Fish (fnf@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #notinclude "m68k/sgs.h"	/* The m68k/SVR4 assembler is SGS based */
-
-/* These are necessary for -fpic/-fPIC to work correctly.  */
-#ifndef MOTOROLA
-#define MOTOROLA                /* Use MOTOROLA syntax.  */
-#endif
-#ifdef  USE_GAS  /* when present, forces jsbr instead of jsr.  */
-#undef  USE_GAS
-#endif
-
-#ifndef SWBEG_ASM_OP
-#define SWBEG_ASM_OP ".swbeg"
-#endif
-
-/* Here are four prefixes that are used by asm_fprintf to
-   facilitate customization for alternate assembler syntaxes.
-   Machines with no likelihood of an alternate syntax need not
-   define these and need not use asm_fprintf.  */
-
-/* The prefix for register names.  Note that REGISTER_NAMES
-   is supposed to include this prefix. Also note that this is NOT an
-   fprintf format string, it is a literal string */
-
-#undef REGISTER_PREFIX
-#define REGISTER_PREFIX "%"
-
-/* The prefix for local (compiler generated) labels.
-   These labels will not appear in the symbol table. */
-
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX "."
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-
-/* The prefix for immediate operands.  */
-
-#undef  IMMEDIATE_PREFIX
-#define IMMEDIATE_PREFIX "#"
-
-/* In the machine description we can't use %R, because it will not be seen
-   by ASM_FPRINTF.  (Isn't that a design bug?).  */
-
-#undef REGISTER_PREFIX_MD
-#define REGISTER_PREFIX_MD "%%"
-
-/* config/m68k.md has an explicit reference to the program counter,
-   prefix this by the register prefix.  */
-
-#define ASM_RETURN_CASE_JUMP 			\
-  do {						\
-    if (TARGET_5200)				\
-      return "ext%.l %0\n\tjmp %%pc@(2,%0:l)";	\
-    else					\
-      return "jmp %%pc@(2,%0:w)";		\
-  } while (0)
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number.
-   Motorola format uses different register names than defined 
-   in m68k.h.  */
-
-#undef REGISTER_NAMES
-
-#define REGISTER_NAMES \
-{"%d0",   "%d1",   "%d2",   "%d3",   "%d4",   "%d5",   "%d6",   "%d7",	     \
- "%a0",   "%a1",   "%a2",   "%a3",   "%a4",   "%a5",   "%a6",   "%sp",	     \
- "%fp0",  "%fp1",  "%fp2",  "%fp3",  "%fp4",  "%fp5",  "%fp6",  "%fp7" }
-
-/* This is how to output an assembler line that says to advance the
-   location counter to a multiple of 2**LOG bytes.  */
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)				\
-  if ((LOG) > 0)						\
-    fprintf ((FILE), "\t%s \t%u\n", ALIGN_ASM_OP, 1 << (LOG));	\
-  else if ((LOG) > 31)						\
-    abort ();
-
-/* Use proper assembler syntax for these macros.  */
-#undef ASM_OUTPUT_REG_PUSH
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  asm_fprintf (FILE, "\t%Omove.l %s,-(%Rsp)\n", reg_names[REGNO])
-
-#undef ASM_OUTPUT_REG_POP
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  asm_fprintf (FILE, "\t%Omove.l (%Rsp)+,%s\n", reg_names[REGNO])
-
-/*  Override the definition of NO_DOLLAR_IN_LABEL in svr4.h, for special
-    g++ assembler names.  When this is defined, g++ uses embedded '.'
-    characters and some m68k assemblers have problems with this.  The
-    chances are much greater that any particular assembler will permit
-    embedded '$' characters. */
-
-#undef NO_DOLLAR_IN_LABEL
-
-/* Define PCC_STATIC_STRUCT_RETURN if the convention on the target machine
-   is to use the nonreentrant technique for returning structure and union
-   values, as commonly implemented by the AT&T Portable C Compiler (PCC).
-   When defined, the gcc option -fpcc-struct-return can be used to cause
-   this form to be generated.  When undefined, the option does nothing.
-   For m68k SVR4, the convention is to use a reentrant technique compatible
-   with the gcc default, so override the definition of this macro in m68k.h */
-
-#undef PCC_STATIC_STRUCT_RETURN
-
-/* Local common symbols are declared to the assembler with ".lcomm" rather
-   than ".bss", so override the definition in svr4.h */
-
-#undef BSS_ASM_OP
-#define BSS_ASM_OP	".lcomm"
-
-/* Register in which address to store a structure value is passed to a
-   function.  The default in m68k.h is a1.  For m68k/SVR4 it is a0. */
-
-#undef STRUCT_VALUE_REGNUM
-#define STRUCT_VALUE_REGNUM 8
-
-#define ASM_COMMENT_START "|"
-
-#undef TYPE_OPERAND_FMT
-#define TYPE_OPERAND_FMT      "@%s"
-
-/* Define how the m68k registers should be numbered for Dwarf output.
-   The numbering provided here should be compatible with the native
-   SVR4 SDB debugger in the m68k/SVR4 reference port, where d0-d7
-   are 0-7, a0-a8 are 8-15, and fp0-fp7 are 16-23. */
-
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* The ASM_OUTPUT_SKIP macro is first defined in m68k.h, using ".skip".
-   It is then overridden by m68k/sgs.h to use ".space", and again by svr4.h
-   to use ".zero".  The m68k/SVR4 assembler uses ".space", so repeat the
-   definition from m68k/sgs.h here.  Note that ASM_NO_SKIP_IN_TEXT is
-   defined in m68k/sgs.h, so we don't have to repeat it here. */
-
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t%s %u\n", SPACE_ASM_OP, (SIZE))
-
-#if 0
-/* SVR4 m68k assembler is bitching on the `comm i,1,1' which askes for 
-   1 byte alignment. Don't generate alignment for COMMON seems to be
-   safer until we the assembler is fixed. */
-#undef ASM_OUTPUT_ALIGNED_COMMON
-/* Same problem with this one.  */
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#endif
-
-/* The `string' directive on m68k svr4 does not handle string with
-   escape char (ie., `\') right. Use normal way to output ASCII bytes
-   seems to be safer. */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)				\
-do {								\
-  register int sp = 0, lp = 0, ch;				\
-  fprintf ((FILE), "\t%s ", BYTE_ASM_OP);			\
-  do {								\
-    ch = (PTR)[sp];						\
-    if (ch > ' ' && ! (ch & 0x80) && ch != '\\')		\
-      {								\
-	fprintf ((FILE), "'%c", ch);				\
-      }								\
-    else							\
-      {								\
-	fprintf ((FILE), "0x%x", ch);				\
-      }								\
-    if (++sp < (LEN))						\
-      {								\
-	if ((sp % 10) == 0)					\
-	  {							\
-	    fprintf ((FILE), "\n\t%s ", BYTE_ASM_OP);		\
-	  }							\
-	else							\
-	  {							\
-	    putc (',', (FILE));					\
-	  }							\
-      }								\
-  } while (sp < (LEN));						\
-  putc ('\n', (FILE));						\
-} while (0)
-
-/* SVR4 m68k assembler is bitching on the syntax `2.b'.
-   So use the "LLDnnn-LLnnn" format.  Define LLDnnn after the table.  */
-
-#undef ASM_OUTPUT_CASE_END
-#define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE)				\
-do {									\
-  if (switch_table_difference_label_flag)				\
-    asm_fprintf ((FILE), "\t%s %LLD%d,%LL%d\n", SET_ASM_OP, (NUM), (NUM));\
-  switch_table_difference_label_flag = 0;				\
-} while (0)
-
-extern int switch_table_difference_label_flag;
-
-#undef ASM_OUTPUT_COMMON
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (SIZE)))
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (SIZE)))
-
-/* Currently, JUMP_TABLES_IN_TEXT_SECTION must be defined in order to
-   keep switch tables in the text section. */
-   
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* Override the definition in svr4.h. In m68k svr4, using swbeg is the 
-   standard way to do switch table. */
-#undef ASM_OUTPUT_BEFORE_CASE_LABEL
-#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE)		\
-  fprintf ((FILE), "\t%s &%d\n", SWBEG_ASM_OP, XVECLEN (PATTERN (TABLE), 1));
-
-/* In m68k svr4, a symbol_ref rtx can be a valid PIC operand if it is an
-   operand of a function call. */
-#undef LEGITIMATE_PIC_OPERAND_P
-#define LEGITIMATE_PIC_OPERAND_P(X) \
-  (! symbolic_operand (X, VOIDmode) \
-   || ((GET_CODE(X) == SYMBOL_REF) && SYMBOL_REF_FLAG(X)))
-
-/* Turn off function cse if we are doing PIC. We always want function call
-   to be done as `bsr foo@PLTPC', so it will force the assembler to create 
-   the PLT entry for `foo'. Doing function cse will cause the address of `foo'
-   to be loaded into a register, which is exactly what we want to avoid when
-   we are doing PIC on svr4 m68k. */
-#undef OVERRIDE_OPTIONS
-#define OVERRIDE_OPTIONS		\
-{					\
-  if (flag_pic) flag_no_function_cse = 1; \
-  if (! TARGET_68020 && flag_pic == 2)	\
-    error("-fPIC is not currently supported on the 68000 or 68010\n");	\
-}
-/* end of stuff from m68kv4.h */
-
-#undef SGS_CMP_ORDER
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s"
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC "crtbegin.o%s"
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as
-   uninitialized global data.  If not defined, and neither
-   `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
-   uninitialized global data will be output in the data section if
-   `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
-   used.  */
-#ifndef BSS_SECTION_ASM_OP
-#define BSS_SECTION_ASM_OP	".section\t.bss"
-#endif
-
-/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
-   separate, explicit argument.  If you define this macro, it is used
-   in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
-   handling the required alignment of the variable.  The alignment is
-   specified as the number of bits.
-
-   Try to use function `asm_output_aligned_bss' defined in file
-   `varasm.c' when defining this macro. */
-#ifndef ASM_OUTPUT_ALIGNED_BSS
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
-#endif
diff --git a/gcc/config/m68k/m68kemb.h b/gcc/config/m68k/m68kemb.h
deleted file mode 100755
index 9fa0c69..0000000
--- a/gcc/config/m68k/m68kemb.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Definitions of target machine for GNU compiler.  "embedded" 68XXX.
-   This is meant to be included after m68k.h.
-   Copyright (C) 1994, 1995 Free Software Foundation, Inc.  */
-
-#define PTRDIFF_TYPE "long int"
-#define SIZE_TYPE "long unsigned int"
-
-/* In order for bitfields to work on a 68000, or with -mnobitfield, we must
-   define either PCC_BITFIELD_TYPE_MATTERS or STRUCTURE_SIZE_BOUNDARY.
-   Defining STRUCTURE_SIZE_BOUNDARY results in structure packing problems,
-   so we define PCC_BITFIELD_TYPE_MATTERS.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Undef PCC_STATIC_STRUCT_RETURN so that we get a re-entrant calling
-   convention.  */
-#undef PCC_STATIC_STRUCT_RETURN
-
-/* Don't default to pcc-struct-return, so that we can return small structures
-   and unions in registers, which is slightly more efficient.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Return floating point values in a fp register.  This make fp code a
-   little bit faster.  It also makes -msoft-float code incompatible with
-   -m68881 code, so people have to be careful not to mix the two.  */
-#undef FUNCTION_VALUE
-#define FUNCTION_VALUE(VALTYPE,FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
-
-#undef LIBCALL_VALUE
-#define LIBCALL_VALUE(MODE)                                                \
- gen_rtx (REG, (MODE),                                                     \
-          ((TARGET_68881                                                   \
-            && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) \
-           ? 16 : 0))
-
-#undef FUNCTION_VALUE_REGNO_P
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (TARGET_68881 && (N) == 16))
-
-#undef NEEDS_UNTYPED_CALL
-#define NEEDS_UNTYPED_CALL 1
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmc68000 -D__embedded__ -Asystem(embedded) \
-  -Amachine(mc68000)"
-
-/* Override the default LIB_SPEC from gcc.c.  We don't currently support
-   profiling, or libg.a.  */
-
-#undef  LIB_SPEC
-#define LIB_SPEC "-lc"
-
-/* Make this be null, since we want the crt0.o to come from the linker
-   script */
-
-#undef  STARTFILE_SPEC
-#define STARTFILE_SPEC ""
diff --git a/gcc/config/m68k/m68kv4.h b/gcc/config/m68k/m68kv4.h
deleted file mode 100755
index 16cc1c9..0000000
--- a/gcc/config/m68k/m68kv4.h
+++ /dev/null
@@ -1,346 +0,0 @@
-/* Target definitions for GNU compiler for mc680x0 running System V.4
-   Copyright (C) 1991, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Ron Guilmette (rfg@monkeys.com) and
-   Fred Fish (fnf@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Use SGS_* macros to control compilation in m68k.md */
-
-#define SGS_SWITCH_TABLES	/* Different switch table handling */
-
-#include "m68k/sgs.h"		/* The m68k/SVR4 assembler is SGS based */
-
-/* The SGS assembler requires a special definition of
-   ASM_IDENTIFY_GCC.  We combine the m68k/sgs.h and the svr4.h
-   definitions below.  */
-#undef ASM_IDENTIFY_GCC
-
-#include "svr4.h"		/* Pick up the generic SVR4 macros */
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-
-#ifndef TARGET_DEFAULT
-#define	TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-/* When using an SGS assembler, modify the name of the artificial label which
-   identifies this file as having been compiled with gcc, and the macro that
-   emits such a label in the assembly output, to use '%' rather than '.'  */
-
-#undef ASM_IDENTIFY_GCC
-#define ASM_IDENTIFY_GCC(FILE)						\
-do									\
-  {									\
-    if (write_symbols != DBX_DEBUG)					\
-      fputs ("gcc2_compiled%:\n", FILE);				\
-  }									\
-while (0)
-
-/*  Override the definition of NO_DOLLAR_IN_LABEL in svr4.h, for special
-    g++ assembler names.  When this is defined, g++ uses embedded '.'
-    characters and some m68k assemblers have problems with this.  The
-    chances are much greater that any particular assembler will permit
-    embedded '$' characters. */
-
-#undef NO_DOLLAR_IN_LABEL
-
-/* Define PCC_STATIC_STRUCT_RETURN if the convention on the target machine
-   is to use the nonreentrant technique for returning structure and union
-   values, as commonly implemented by the AT&T Portable C Compiler (PCC).
-   When defined, the gcc option -fpcc-struct-return can be used to cause
-   this form to be generated.  When undefined, the option does nothing.
-   For m68k SVR4, the convention is to use a reentrant technique compatible
-   with the gcc default, so override the definition of this macro in m68k.h */
-
-#undef PCC_STATIC_STRUCT_RETURN
-
-/* Provide a set of pre-definitions and pre-assertions appropriate for
-   the m68k running svr4.  __svr4__ is our extension.  */
-
-#define CPP_PREDEFINES \
-  "-Dm68k -Dunix -D__svr4__ -D__motorola__ \
- -Asystem(unix) -Asystem(svr4) -Acpu(m68k) -Amachine(m68k)"
-
-/* Test to see if the target includes a 68881 by default, and use CPP_SPEC
-   to control whether or not __HAVE_68881__ is defined by default or not.
-   If a 68881 is the default, gcc will use inline 68881 instructions, by
-   predefining __HAVE_68881__, unless -msoft-float is specified.
-   If a 68881 is not the default, gcc will only define __HAVE_68881__ if
-   -m68881 is specified. */
-
-#if TARGET_DEFAULT & MASK_68881
-#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__}"
-#else
-#define CPP_SPEC "%{m68881:-D__HAVE_68881__}"
-#endif
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  We override the definition in m68k.h
-   and match the way the native m68k/SVR4 compiler does profiling, with the
-   address of the profile counter in a1, not a0, and using bsr rather
-   than jsr. */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)				\
-  asm_fprintf ((FILE), "\tlea.l\t(%LLP%d,%Rpc),%Ra1\n\tbsr\t_mcount\n", \
-	       (LABELNO))
-
-/* Local common symbols are declared to the assembler with ".lcomm" rather
-   than ".bss", so override the definition in svr4.h */
-/* ??? svr4.h no longer defines this, and this is only used by m68k/amix.h.  */
-
-#undef BSS_ASM_OP
-#define BSS_ASM_OP	".lcomm"
-
-/* Register in which address to store a structure value is passed to a
-   function.  The default in m68k.h is a1.  For m68k/SVR4 it is a0. */
-
-#undef STRUCT_VALUE_REGNUM
-#define STRUCT_VALUE_REGNUM 8
-
-/* Register in which static-chain is passed to a function.  The
-   default in m68k.h is a0, but that is already the struct value
-   regnum.  Make it a1 instead.  */
-
-#undef STATIC_CHAIN_REGNUM
-#define STATIC_CHAIN_REGNUM 9
-
-#define ASM_COMMENT_START "#"
-
-#undef TYPE_OPERAND_FMT
-#define TYPE_OPERAND_FMT      "@%s"
-
-/* Define how the m68k registers should be numbered for Dwarf output.
-   The numbering provided here should be compatible with the native
-   SVR4 SDB debugger in the m68k/SVR4 reference port, where d0-d7
-   are 0-7, a0-a8 are 8-15, and fp0-fp7 are 16-23. */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* The ASM_OUTPUT_SKIP macro is first defined in m68k.h, using ".skip".
-   It is then overridden by m68k/sgs.h to use ".space", and again by svr4.h
-   to use ".zero".  The m68k/SVR4 assembler uses ".space", so repeat the
-   definition from m68k/sgs.h here.  Note that ASM_NO_SKIP_IN_TEXT is
-   defined in m68k/sgs.h, so we don't have to repeat it here. */
-
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t%s %u\n", SPACE_ASM_OP, (SIZE))
-
-/* 1 if N is a possible register number for a function value.
-   For m68k/SVR4 allow d0, a0, or fp0 as return registers, for integral,
-   pointer, or floating types, respectively. Reject fp0 if not using a
-   68881 coprocessor. */
-
-#undef FUNCTION_VALUE_REGNO_P
-#define FUNCTION_VALUE_REGNO_P(N) \
-  ((N) == 0 || (N) == 8 || (TARGET_68881 && (N) == 16))
-
-/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
-   more than one register.  */
-
-#undef NEEDS_UNTYPED_CALL
-#define NEEDS_UNTYPED_CALL 1
-
-/* Define how to generate (in the callee) the output value of a function
-   and how to find (in the caller) the value returned by a function.  VALTYPE
-   is the data type of the value (as a tree).  If the precise function being
-   called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
-   For m68k/SVR4 generate the result in d0, a0, or fp0 as appropriate. */
-   
-#undef FUNCTION_VALUE
-#define FUNCTION_VALUE(VALTYPE, FUNC)					\
-  (TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_68881			\
-   ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16)				\
-   : (POINTER_TYPE_P (VALTYPE)						\
-      ? gen_rtx (REG, TYPE_MODE (VALTYPE), 8)				\
-      : gen_rtx (REG, TYPE_MODE (VALTYPE), 0)))
-
-/* For compatibility with the large body of existing code which does not
-   always properly declare external functions returning pointer types, the
-   m68k/SVR4 convention is to copy the value returned for pointer functions
-   from a0 to d0 in the function epilogue, so that callers that have
-   neglected to properly declare the callee can still find the correct return
-   value. */
-
-extern int current_function_returns_pointer;
-#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)				\
-do {									\
-  if ((current_function_returns_pointer) && 				\
-      ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode))	\
-    asm_fprintf (FILE, "\tmov.l %Ra0,%Rd0\n");				\
-} while (0);
-
-/* Define how to find the value returned by a library function assuming the
-   value has mode MODE.
-   For m68k/SVR4 look for integer values in d0, pointer values in d0
-   (returned in both d0 and a0), and floating values in fp0. */
-
-#undef LIBCALL_VALUE
-#define LIBCALL_VALUE(MODE)						\
-  ((((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)		\
-    && TARGET_68881)							\
-   ? gen_rtx (REG, (MODE), 16)						\
-   : gen_rtx (REG, (MODE), 0))
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.
-   The m68k/SVR4 convention is to keep the stack pointer longword aligned. */
- 
-#undef STACK_BOUNDARY
-#define STACK_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure.
-   For m68k/SVR4, this is the next longword boundary. */
-
-#undef EMPTY_FIELD_BOUNDARY
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* No data type wants to be aligned rounder than this.
-   For m68k/SVR4, some types (doubles for example) are aligned on 8 byte
-   boundaries */
-	
-#undef BIGGEST_ALIGNMENT
-#define BIGGEST_ALIGNMENT 64
-
-/* SVR4 m68k assembler is bitching on the `comm i,1,1' which asks for 
-   1 byte alignment. Don't generate alignment for COMMON seems to be
-   safer until we the assembler is fixed. */
-#undef ASM_OUTPUT_ALIGNED_COMMON
-/* Same problem with this one.  */
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-
-/* The `string' directive on m68k svr4 does not handle string with
-   escape char (ie., `\') right. Use normal way to output ASCII bytes
-   seems to be safer. */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)				\
-do {								\
-  register int sp = 0, lp = 0, ch;				\
-  fprintf ((FILE), "\t%s ", BYTE_ASM_OP);			\
-  do {								\
-    ch = (PTR)[sp];						\
-    if (ch > ' ' && ! (ch & 0x80) && ch != '\\')		\
-      {								\
-	fprintf ((FILE), "'%c", ch);				\
-      }								\
-    else							\
-      {								\
-	fprintf ((FILE), "0x%x", ch);				\
-      }								\
-    if (++sp < (LEN))						\
-      {								\
-	if ((sp % 10) == 0)					\
-	  {							\
-	    fprintf ((FILE), "\n\t%s ", BYTE_ASM_OP);		\
-	  }							\
-	else							\
-	  {							\
-	    putc (',', (FILE));					\
-	  }							\
-      }								\
-  } while (sp < (LEN));						\
-  putc ('\n', (FILE));						\
-} while (0)
-
-/* SVR4 m68k assembler is bitching on the syntax `2.b'.
-   So use the "LLDnnn-LLnnn" format.  Define LLDnnn after the table.  */
-
-#undef ASM_OUTPUT_CASE_END
-#define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE)				\
-do {									\
-  if (switch_table_difference_label_flag)				\
-    asm_fprintf ((FILE), "\t%s %LLD%d,%LL%d\n", SET_ASM_OP, (NUM), (NUM));\
-  switch_table_difference_label_flag = 0;				\
-} while (0)
-
-int switch_table_difference_label_flag;
-
-#undef ASM_OUTPUT_COMMON
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (SIZE)))
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (SIZE)))
-
-/* Override the definition in svr4.h. In m68k svr4, using swbeg is the 
-   standard way to do switch table. */
-#undef ASM_OUTPUT_BEFORE_CASE_LABEL
-#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE)		\
-  fprintf ((FILE), "\t%s &%d\n", SWBEG_ASM_OP, XVECLEN (PATTERN (TABLE), 1));
-
-/* In m68k svr4, a symbol_ref rtx can be a valid PIC operand if it is an
-   operand of a function call. */
-#undef LEGITIMATE_PIC_OPERAND_P
-#define LEGITIMATE_PIC_OPERAND_P(X) \
-  ((! symbolic_operand (X, VOIDmode) \
-    && ! (GET_CODE (X) == CONST_DOUBLE && CONST_DOUBLE_MEM (X)	\
-	  && GET_CODE (CONST_DOUBLE_MEM (X)) == MEM		\
-	  && symbolic_operand (XEXP (CONST_DOUBLE_MEM (X), 0), VOIDmode))) \
-   || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)))
-
-/* Turn off function cse if we are doing PIC. We always want function call
-   to be done as `bsr foo@PLTPC', so it will force the assembler to create 
-   the PLT entry for `foo'. Doing function cse will cause the address of `foo'
-   to be loaded into a register, which is exactly what we want to avoid when
-   we are doing PIC on svr4 m68k. */
-#undef OVERRIDE_OPTIONS
-#define OVERRIDE_OPTIONS		\
-{					\
-  if (flag_pic) flag_no_function_cse = 1; \
-  if (! TARGET_68020 && flag_pic == 2)	\
-    error("-fPIC is not currently supported on the 68000 or 68010\n");	\
-}
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  */
-
-/* On m68k svr4, the trampoline is different from the generic version
-   in that we use a1 as the static call chain.  */
-
-#undef TRAMPOLINE_TEMPLATE
-#define TRAMPOLINE_TEMPLATE(FILE)					\
-{									\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x227a));				\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (8));					\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x2f3a));				\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (8));					\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x4e75));				\
-  ASM_OUTPUT_INT (FILE, const0_rtx);					\
-  ASM_OUTPUT_INT (FILE, const0_rtx);					\
-}
-
-/* Redefine since we are using a different trampoline */
-#undef TRAMPOLINE_SIZE
-#define TRAMPOLINE_SIZE 18
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#undef INITIALIZE_TRAMPOLINE
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)                       \
-{                                                                       \
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 10)), CXT); \
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 14)), FNADDR); \
-}
diff --git a/gcc/config/m68k/mot3300-crt0.S b/gcc/config/m68k/mot3300-crt0.S
deleted file mode 100755
index 6a32dc2..0000000
--- a/gcc/config/m68k/mot3300-crt0.S
+++ /dev/null
@@ -1,98 +0,0 @@
-/* The start module crt0.s for the SysV68 Motorola 3300 Delta Series.
-   Copyright (C) 1996 Free Software Foundation, Inc.
-   Contributed by Manfred Hollstein (manfred@lts.sel.alcatel.de).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#ifdef MOTOROLA
-# define COMM		comm
-# define DATA		data
-# define EVEN		even
-# define FILE(n)	file	n
-# define GLOBAL_SYM(s)	global	s
-# define LOCAL_LABEL(l)	L%##l
-# define IDENT(s)	ident	s
-# define TEXT		text
-#else /* Assume we are using GNU as.  */
-# define COMM		.comm
-# define DATA		.data
-# define EVEN		.even
-# define FILE(name)	.file	name
-# define GLOBAL_SYM(s)	.globl	s
-# define LOCAL_LABEL(l)	.L.##l
-# define IDENT(s)	.section .comment;.asciz s
-# define TEXT		.text
-#endif
-
-	FILE ("crt0.s")
-	TEXT
-	GLOBAL_SYM (_start)
-_start:	mov.l	%d0,splimit%
-	subq.w	&8,%sp
-	mov.l	8(%sp),(%sp)
-	lea	12(%sp),%a0
-	mov.l	%a0,4(%sp)
-	mov.l	%a0,%a1
-LOCAL_LABEL(0):
-	tst.l	(%a0)+
-	bne.b	LOCAL_LABEL(0)
-#ifdef SGS_CMP_ORDER
-	cmpa.l	%a0,(%a1)
-#else
-	cmpa.l	(%a1),%a0
-#endif
-	blt.b	LOCAL_LABEL(1)
-	subq.w	&4,%a0
-LOCAL_LABEL(1):
-	mov.l	%a0,8(%sp)
-	mov.l	%a0,environ
-	jsr	initfpu
-	
-	subq.w	&8,%sp
-	clr.l	%d0		/* if (! isatty (fileno (stderr))) */
-	mov.b	_iob+27,%d0
-	mov.l	%d0,-(%sp)
-	jsr	isatty
-	addq.w	&4,%sp
-	tst.l	%d0
-	bne.b	LOCAL_LABEL(isatty)
-	clr.l	-(%sp)		/*	setbuf (stderr, NULL) */
-	pea	_iob+28
-	jsr	setbuf
-	addq.w	&8,%sp
-LOCAL_LABEL(isatty):
-	addq.w	&8,%sp
-
-	jsr	main
-	mov.l	%d0,(%sp)
-	jsr	exit
-	moveq.l	&1,%d0
-	trap	&0
-	nop
-
-	GLOBAL_SYM (__stop_monitor)
-__stop_monitor:
-	rts
-	EVEN
-
-	COMM	splimit%,4
-	COMM	environ,4
-
-	IDENT ("$Id: mot3300-crt0.S,v 1.23 1999/01/15 07:37:19 law Exp $")
-	IDENT ("Contributed by Manfred Hollstein (manfred@lts.sel.alcatel.de)")
-	IDENT ("Corrections by Philippe De Muyter (phdm@macqel.be)")
diff --git a/gcc/config/m68k/mot3300.h b/gcc/config/m68k/mot3300.h
deleted file mode 100755
index e1b4060..0000000
--- a/gcc/config/m68k/mot3300.h
+++ /dev/null
@@ -1,816 +0,0 @@
-/* Definitions of target machine for GNU compiler,
-   SysV68 Motorola 3300 Delta Series.
-   Copyright (C) 1987, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
-   Contributed by Abramo and Roberto Bagnara (bagnara@dipisa.di.unipi.it)
-   based on Alex Crain's 3B1 definitions.
-   Maintained by Philippe De Muyter (phdm@info.ucl.ac.be).
-   Support for GAS added by merging mot3300g.h into this file by
-   Manfred Hollstein (manfred@lts.sel.alcatel.de).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#ifndef USE_GAS
-#define MOTOROLA		/* Use Motorola syntax rather than "MIT" */
-#define MOTOROLA_BSR		/* Use Span-dependent optimized bsr */
-#define SGS			/* Uses SGS assembler */
-#define SGS_CMP_ORDER		/* Takes cmp operands in reverse order */
-#define SGS_SWAP_W		/* Use swap.w rather than just plain swap */
-#endif /* USE_GAS */
-
-#define NO_DOLLAR_IN_LABEL
-#define NO_DOT_IN_LABEL
-
-#include "m68k/m68k.h"
-
-/* See m68k.h.  0407 means 68020-68040.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_68040|MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-/* -m[c]6800 requires special flag to the assembler.  */
-
-#undef ASM_SPEC
-#ifndef USE_GAS
-#define ASM_SPEC "%{m68000:-p 000}%{mc68000:-p 000}"
-#else /* USE_GAS */
-#define ASM_SPEC \
-  "%{v:-v} %{m68000:-mc68000}%{mc68000:-mc68000}%{!mc68000:%{!m68000:-mc68020}}"
-#endif /* USE_GAS */
-
-/* NYI: FP= is equivalent to -msoft-float  */
-
-/* We use /lib/libp/lib* when profiling.  */
-
-/* NYI: if FP=M68881U library is -lc881u  */
-/* NYI: if FP= library is -lc.  */
-/* Default for us: FP=M68881 library is -lc881  */
-#undef LIB_SPEC
-#define LIB_SPEC "%{!shlib:%{!msoft-float:-lc881}%{msoft-float:-lc}}"
-#ifdef CROSS_COMPILE
-#ifndef USE_GLD
-#define DEFAULT_A_OUT_NAME "m68ka.out"
-#endif
-#endif
-
-#ifdef USE_GLD
-#undef LINK_SPEC
-#define LINK_SPEC "%{v:-v}"
-#endif /* defined (USE_GLD) */
-
-#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__}\
-%{!mc68000:%{!m68000: -D__mc68020__}}"
-
-/* Shared libraries need to use crt0s.o  */
-
-#undef STARTFILE_SPEC
-#ifdef CROSS_COMPILE
-#define STARTFILE_SPEC \
-  "%{!shlib:%{pg:mcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}\
-   %{shlib:crt0s.o%s shlib.ifile%s} %{p:-L"TOOLDIR_BASE_PREFIX DEFAULT_TARGET_MACHINE"/lib/libp} %{pg:-L"TOOLDIR_BASE_PREFIX DEFAULT_TARGET_MACHINE"/lib/libp} "
-#else /* CROSS_COMPILE */
-#define STARTFILE_SPEC \
-  "%{!shlib:%{pg:mcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}\
-   %{shlib:crt0s.o%s shlib.ifile%s} %{p:-L/usr/lib/libp} %{pg:-L/usr/lib/libp} "
-#endif /* CROSS_COMPILE */
-
-/* Generate calls to memcpy, memcmp and memset.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* size_t is unsigned int.  */
-
-#define SIZE_TYPE "unsigned int"
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Follow sysV68 cc regarding alignment imposed by char:0; */
-
-#define PCC_BITFIELD_TYPE_MATTERS 1
-  
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-/* Be compatible with native compiler.  */
-#undef PARM_BOUNDARY
-#define PARM_BOUNDARY 16
-
-/* cpp has to support a #sccs directive for the /usr/include files */
-
-#define SCCS_DIRECTIVE
-
-/* Make output for SDB.  */
-
-#define SDB_DEBUGGING_INFO
-
-#undef REGISTER_PREFIX
-#define REGISTER_PREFIX "%"
-
-#undef LOCAL_LABEL_PREFIX
-#ifdef USE_GAS
-#define LOCAL_LABEL_PREFIX ".L"
-#else
-#define LOCAL_LABEL_PREFIX "L%"
-#endif
-
-#undef USER_LABEL_PREFIX
-
-#undef IMMEDIATE_PREFIX
-#define IMMEDIATE_PREFIX "&"
-
-#undef REGISTER_NAMES
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",	\
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",	\
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7"}
-
-#undef FUNCTION_EXTRA_EPILOGUE
-#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)				\
-  { extern int current_function_returns_pointer;			\
-    if ((current_function_returns_pointer) &&				\
-      ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode))        \
-      asm_fprintf (FILE, "\tmov.l %Ra0,%Rd0\n"); } 
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABEL_NO)	\
-    asm_fprintf (FILE, "\tmov.l %I%LLP%d,%Ra0\n\tjsr mcount%%\n", (LABEL_NO))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#undef ASM_OUTPUT_REG_PUSH
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tmov.l %s,-(%%sp)\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#undef ASM_OUTPUT_REG_POP
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tmov.l (%%sp)+,%s\n", reg_names[REGNO])
-
-#ifndef USE_GAS
-
-#undef ASM_APP_ON
-#define ASM_APP_ON ""
-
-#undef ASM_APP_OFF
-#define ASM_APP_OFF ""
-
-#undef TEXT_SECTION_ASM_OP
-#define TEXT_SECTION_ASM_OP "text"
-#undef DATA_SECTION_ASM_OP
-#define DATA_SECTION_ASM_OP "data"
-#undef ASCII_DATA_ASM_OP
-#define	ASCII_DATA_ASM_OP "byte"
-
-#undef SET_ASM_OP
-#define SET_ASM_OP "set"
-
-#endif /* USE_GAS */
-
-#ifdef USE_GLD
-/* Support the ctors and dtors sections for g++.  */
-
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"x\""
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"x\""
-
-/* A list of other sections which the compiler might be "in" at any
-   given time.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_ctors, in_dtors
-
-/* A list of extra section function definitions.  */
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", ASM_LONG);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", ASM_LONG);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-#endif /* defined (USE_GLD) */
-
-/* The file command should always begin the output.  */
-
-#undef ASM_FILE_START
-#ifndef USE_GAS
-#define ASM_FILE_START(FILE) \
-  output_file_directive ((FILE), main_input_filename)
-#else /* USE_GAS */
-#define ASM_FILE_START(FILE) \
-    { \
-       fprintf (FILE, "%s", ASM_APP_OFF); \
-       output_file_directive ((FILE), main_input_filename); \
-    }
-#endif /* USE_GAS */
-
-/* The sysV68 assembler does not accept dots in labels.
-   Let's use percent instead  */
-
-#define ASM_IDENTIFY_GCC(FILE)        fputs("gcc2_compiled%:\n", FILE)
-
-/* Names to predefine in the preprocessor for this target machine.  */
-/* ihnp4!lmayk!lgm@eddie.mit.edu says mc68000 and m68k should not be here,
-   on the other hand I don't care what he says.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dm68k -Dunix -DsysV68 -D__motorola__ -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)"
-
-#undef TARGET_VERSION
-#ifndef USE_GAS
-#define TARGET_VERSION fprintf (stderr, " (68k, SGS/AT&T sysV68 syntax)");
-#endif /* USE_GAS */
-
-/* This will return small structs in d0.  */
-#define RETURN_IN_MEMORY(type) \
-  ((TYPE_MODE (type) == BLKmode) \
-   || (AGGREGATE_TYPE_P (type) \
-       && GET_MODE_SIZE (TYPE_MODE (type)) > UNITS_PER_WORD))
-
-/* Don't default to pcc-struct-return, because we have already specified
-   exactly how to return structures in the RETURN_IN_MEMORY macro.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* If TARGET_68881, return SF and DF values in fp0 instead of d0.  */
-/* NYI: If FP=M68881U return SF and DF values in d0. */
-/* NYI: If -mold return pointer in a0 and d0 */
-
-#undef FUNCTION_VALUE
-/* sysV68 (brain damaged) cc convention support. */
-#define FUNCTION_VALUE(VALTYPE,FUNC) \
-  (TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_68881 	\
-   ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16)		\
-   : (POINTER_TYPE_P (VALTYPE)				\
-      ? gen_rtx (REG, TYPE_MODE (VALTYPE), 8)		\
-      : gen_rtx (REG, TYPE_MODE (VALTYPE), 0)))
-
-/* If TARGET_68881, SF and DF values are returned in fp0 instead of d0.  */
-
-/* Is LIBCALL_VALUE never called with a pointer ? */
-#undef LIBCALL_VALUE
-#define LIBCALL_VALUE(MODE)						   \
- gen_rtx (REG, (MODE),							   \
-	  ((TARGET_68881						   \
-	    && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) \
-	   ? 16 : 0))
-
-/* 1 if N is a possible register number for a function value.
-   d0 may be used, and fp0 as well if -msoft-float is not specified.  */
-
-#undef FUNCTION_VALUE_REGNO_P
-/* sysV68 (brain damaged) cc convention support. */
-#define FUNCTION_VALUE_REGNO_P(N) \
- ((N) == 0 || (N) == 8 || (TARGET_68881 && (N) == 16))
-
-/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
-   more than one register.  */
-
-#undef NEEDS_UNTYPED_CALL
-#define NEEDS_UNTYPED_CALL 1
- 
-#ifndef USE_GAS
-/* This is the command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#undef GLOBAL_ASM_OP
-#define GLOBAL_ASM_OP "global"
-#endif /* USE_GAS */
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#undef ASM_FORMAT_PRIVATE_NAME
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12),	\
-  sprintf ((OUTPUT), "%s_%%%d", (NAME), (LABELNO)))
-
-#ifdef USE_GAS
-#undef ASM_LONG
-#define ASM_LONG	".long"
-#undef ASM_SHORT
-#define ASM_SHORT	".short"
-#undef ASM_CHAR
-#define ASM_CHAR	".byte"
-#undef ASM_BYTE
-#define ASM_BYTE	".byte"
-#undef ASM_BYTE_OP
-#define ASM_BYTE_OP	".byte"
-#else
-#undef ASM_LONG
-#define ASM_LONG	"long"
-#undef ASM_SHORT
-#define ASM_SHORT	"short"
-#undef ASM_CHAR
-#define ASM_CHAR	"byte"
-#undef ASM_BYTE
-#define ASM_BYTE	"byte"
-#undef ASM_BYTE_OP
-#define ASM_BYTE_OP	"byte"
-#endif /* USE_GAS */
-
-/* The sysV68 as doesn't know about double's and float's.  */
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-do { long l[2];						\
-     REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l);		\
-     fprintf (FILE, "\t%s 0x%x,0x%x\n", ASM_LONG, l[0], l[1]); \
-   } while (0)
-
-#undef ASM_OUTPUT_LONG_DOUBLE
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE)  				\
-do { long l[3];								\
-     REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l);			\
-     fprintf (FILE, "\t%s 0x%x,0x%x,0x%x\n", ASM_LONG, l[0], l[1], l[2]);	\
-   } while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-do { long l;					\
-     REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);	\
-     fprintf ((FILE), "\t%s 0x%x\n", ASM_LONG, l);	\
-   } while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#undef ASM_OUTPUT_INT
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t%s ", ASM_LONG),		\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#undef ASM_OUTPUT_SHORT
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t%s ", ASM_SHORT),		\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#undef ASM_OUTPUT_CHAR
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t%s ", ASM_CHAR),		\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#undef ASM_OUTPUT_BYTE
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t%s 0x%x\n", ASM_BYTE, (VALUE))
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#ifndef USE_GAS
-#define ALIGN_ASM_OP	"even"
-#else /* USE_GAS */
-#define ALIGN_ASM_OP	".even"
-#endif /* USE_GAS */
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) >= 1)			\
-    fprintf (FILE, "\t%s\n", ALIGN_ASM_OP);
-
-#ifndef USE_GAS
-#define SKIP_ASM_OP	"space"
-#else /* USE_GAS */
-#define SKIP_ASM_OP	".skip"
-#endif /* USE_GAS */
-
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t%s %u\n", SKIP_ASM_OP, (SIZE))
-
-/* Can't use ASM_OUTPUT_SKIP in text section.  */
-
-#define ASM_NO_SKIP_IN_TEXT 1
-
-/* The beginnings of sdb support...  */
-
-/* Undefining these will allow `output_file_directive' (in toplev.c)
-   to default to the right thing. */
-#undef ASM_OUTPUT_MAIN_SOURCE_FILENAME
-#ifndef USE_GAS
-#define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) \
-  do {	fprintf (FILE, "\tfile\t");		\
-	output_quoted_string (FILE, FILENAME);	\
-	fprintf (FILE, "\n");			\
-  } while (0)
-
-#undef ASM_OUTPUT_SOURCE_LINE
-#define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO)	\
-  fprintf (FILE, "\tln\t%d\n",			\
-	   (sdb_begin_function_line		\
-	    ? last_linenum - sdb_begin_function_line : 1))
-
-/* Yet another null terminated string format.  */
-
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \
-  do { register int sp = 0, lp = 0;				\
-    fprintf ((FILE), "\t%s\t", ASM_BYTE_OP);			\
-  loop:								\
-    if ((PTR)[sp] > ' ' && ! ((PTR)[sp] & 0x80) && (PTR)[sp] != '\\')	\
-      { lp += 3;						\
-	fprintf ((FILE), "'%c", (PTR)[sp]); }			\
-    else							\
-      { lp += 5;						\
-	fprintf ((FILE), "0x%x", (PTR)[sp]); }			\
-    if (++sp < (LEN))						\
-      {	if (lp > 60)						\
-	  { lp = 0;						\
-	    fprintf ((FILE), "\n\t%s ", ASCII_DATA_ASM_OP); }	\
-	else							\
-	  putc (',', (FILE));					\
-	goto loop; }						\
-    putc ('\n', (FILE)); } while (0)
-#endif /* USE_GAS */
-
-#ifndef USE_GAS
-/* Output a float value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)			\
- do { long l;								\
-      REAL_VALUE_TO_TARGET_SINGLE (r, l);				\
-      /* Use hex representation even if CODE is f.  as needs it.  */	\
-      fprintf ((FILE), "&0x%lx", l);					\
-    } while (0)
-
-/* Output a double value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)				\
- do { long l[2];							\
-      REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l);				\
-      fprintf ((FILE), "&0x%lx%08lx", l[0], l[1]);			\
-    } while (0)
-#endif /* USE_GAS */
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)	\
-  sprintf ((LABEL), "%s%s%d", LOCAL_LABEL_PREFIX, (PREFIX), (NUM))
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-    asm_fprintf (FILE, "%L%s%d:\n", PREFIX, NUM)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-
-/* This is how to output an element of a case-vector that is absolute.
-   (The 68000 does not use such vectors,
-   but we must define this macro anyway.)  */
-/* The L after the local prefix is the "L" prefix for the normal labels
-   generated by gcc; why are ASM_OUTPUT_ADDR_VEC_ELT and
-   ASM_OUTPUT_ADDR_DIFF_ELT not called with a PREFIX parameter, like
-   ASM_OUTPUT_INTERNAL_LABEL ? */
-
-#undef ASM_OUTPUT_ADDR_VEC_ELT
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)	\
-    asm_fprintf (FILE, "\t%s %LL%d\n", ASM_LONG, (VALUE))
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)	\
-    asm_fprintf (FILE, "\t%s %LL%d-%LL%d\n", ASM_SHORT, (VALUE), (REL))
-
-#ifndef USE_GAS
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE)			\
-    asm_fprintf (FILE, "\tswbeg &%d\n%L%s%d:\n",			\
-	     XVECLEN (PATTERN (TABLE), 1), (PREFIX), (NUM))
-
-/* sysV68 as cannot handle LD%n(%pc,%reg) */ 
-#define SGS_NO_LI
-
-/* labelno is not used here */
-#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
-	asm_fprintf (file, "12(%Rpc,%s.", regname)
-
-#define ASM_RETURN_CASE_JUMP \
-  do {						\
-    if (TARGET_5200)				\
-      return "ext%.l %0\n\tjmp 8(%%pc,%0.l)";	\
-    else					\
-      return "jmp 8(%%pc,%0.w)";		\
-  } while (0)
-	     
-#else /* USE_GAS */
-
-/* labelno is not used here */
-#define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
-	asm_fprintf (file, "%Rpc@(6,%s:", regname)
-
-#define ASM_RETURN_CASE_JUMP return "jmp %%pc@(2,%0:w)"
-
-#endif /* USE_GAS */
-
-#ifndef USE_GAS
-
-/* Translate some opcodes to fit the sysV68 assembler syntax.  */
-/* The opcodes fdmov and fsmov are guesses.  */
-
-/* cliffm@netcom.com says no need for .w suffix on jumps.  */
-#undef ASM_OUTPUT_OPCODE
-#define ASM_OUTPUT_OPCODE(FILE, PTR)			\
-{ if ((PTR)[0] == 'j' && (PTR)[1] == 'b')		\
-    { ++(PTR);						\
-      while (*(PTR) != ' ')				\
-	{ putc (*(PTR), (FILE)); ++(PTR); }		\
-    }							\
-  else if ((PTR)[0] == 's')				\
-    {							\
-      if (!strncmp ((PTR), "swap", 4))			\
-	{ fprintf ((FILE), "swap.w"); (PTR) += 4; }	\
-    }							\
-  else if ((PTR)[0] == 'f')				\
-    {							\
-      if (!strncmp ((PTR), "fmove", 5))			\
-	{ fprintf ((FILE), "fmov"); (PTR) += 5; }	\
-      else if (!strncmp ((PTR), "f%$move", 7))		\
-	{ if (TARGET_68040_ONLY)			\
-	    { fprintf ((FILE), "fsmov"); (PTR) += 7; }	\
-	  else						\
-	    { fprintf ((FILE), "fmov"); (PTR) += 7; } }	\
-      else if (!strncmp ((PTR), "f%&move", 7))		\
-	{ if (TARGET_68040_ONLY)			\
-	    { fprintf ((FILE), "fdmov"); (PTR) += 7; }	\
-	  else						\
-	    { fprintf ((FILE), "fmov"); (PTR) += 7; } }	\
-      else if (!strncmp ((PTR), "ftst", 4))		\
-	{ fprintf ((FILE), "ftest"); (PTR) += 4; }	\
-      else if (!strncmp ((PTR), "fbne", 4))		\
-	{ fprintf ((FILE), "fbneq"); (PTR) += 4; }	\
-      else if (!strncmp ((PTR), "fsne", 4))		\
-	{ fprintf ((FILE), "fsneq"); (PTR) += 4; }	\
-    }							\
-/* MOVE, MOVEA, MOVEQ, MOVEC ==> MOV	*/		\
-  else if ((PTR)[0] == 'm' && (PTR)[1] == 'o'		\
-	   && (PTR)[2] == 'v' && (PTR)[3] == 'e')	\
-    { fprintf ((FILE), "mov"); (PTR) += 4;		\
-       if ((PTR)[0] == 'q' || (PTR)[0] == 'a'		\
-	   || (PTR)[0] == 'c') (PTR)++; }		\
-/* SUB, SUBQ, SUBA, SUBI ==> SUB */			\
-  else if ((PTR)[0] == 's' && (PTR)[1] == 'u' 		\
-	   && (PTR)[2] == 'b')				\
-    { fprintf ((FILE), "sub"); (PTR) += 3;		\
-       if ((PTR)[0] == 'q' || (PTR)[0] == 'i'	 	\
-	   || (PTR)[0] == 'a') (PTR)++; }		\
-/* CMP, CMPA, CMPI, CMPM ==> CMP	*/		\
-  else if ((PTR)[0] == 'c' && (PTR)[1] == 'm'		\
-	   && (PTR)[2] == 'p')				\
-    { fprintf ((FILE), "cmp"); (PTR) += 3;		\
-       if ((PTR)[0] == 'a' || (PTR)[0] == 'i'	 	\
-	   || (PTR)[0] == 'm') (PTR)++; }		\
-}
-#endif /* USE_GAS */
-
-/* phdm@info.ucl.ac.be says to pass SIZE, not ROUNDED.  */
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#undef ASM_OUTPUT_COMMON
-#ifndef USE_GAS
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\tcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (SIZE)))
-#else /* USE_GAS */
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\t.comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (SIZE)))
-#endif /* USE_GAS */
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#undef ASM_OUTPUT_LOCAL
-#ifndef USE_GAS
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\tlcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (SIZE)))
-#else /* USE_GAS */
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\t.lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (SIZE)))
-#endif /* USE_GAS */
-
-#ifndef USE_GAS
-/* Override usual definitions of SDB output macros.
-   These definitions differ only in the absence of the period
-   at the beginning of the name of the directive
-   and in the use of `~' as the symbol for the current location.  */
-
-#define PUT_SDB_SCL(a) fprintf(asm_out_file, "\tscl\t%d;", (a))
-#define PUT_SDB_INT_VAL(a) fprintf (asm_out_file, "\tval\t%d;", (a))
-#define PUT_SDB_VAL(a)				\
-( fputs ("\tval\t", asm_out_file),		\
-  output_addr_const (asm_out_file, (a)),	\
-  fputc (';', asm_out_file))
-
-#define PUT_SDB_DEF(a)				\
-do { fprintf (asm_out_file, "\tdef\t");	\
-     ASM_OUTPUT_LABELREF (asm_out_file, a); 	\
-     fprintf (asm_out_file, ";"); } while (0)
-
-#define PUT_SDB_PLAIN_DEF(a) fprintf(asm_out_file,"\tdef\t~%s;",a)
-#define PUT_SDB_ENDEF fputs("\tendef\n", asm_out_file)
-#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\ttype\t0%o;", a)
-#define PUT_SDB_SIZE(a) fprintf(asm_out_file, "\tsize\t%d;", a)
-#define PUT_SDB_START_DIM fprintf(asm_out_file, "\tdim\t")
-#define PUT_SDB_NEXT_DIM(a) fprintf(asm_out_file, "%d,", a)
-#define PUT_SDB_LAST_DIM(a) fprintf(asm_out_file, "%d;", a)
-
-#define PUT_SDB_TAG(a)				\
-do { fprintf (asm_out_file, "\ttag\t");	\
-     ASM_OUTPUT_LABELREF (asm_out_file, a);	\
-     fprintf (asm_out_file, ";"); } while (0)
-
-#define PUT_SDB_BLOCK_START(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~bb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n",	\
-	   (LINE))
-
-#define PUT_SDB_BLOCK_END(LINE)			\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~eb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n",	\
-	   (LINE))
-
-#define PUT_SDB_FUNCTION_START(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~bf;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n",	\
-	   (LINE))
-
-#define PUT_SDB_FUNCTION_END(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~ef;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n",	\
-	   (LINE))
-
-#define PUT_SDB_EPILOGUE_END(NAME)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t%s;\tval\t~;\tscl\t-1;\tendef\n",	\
-	   (NAME))
-
-#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
-  sprintf ((BUFFER), "~%dfake", (NUMBER));
-
-#endif /* USE_GAS */
-
-/* Define subroutines to call to handle multiply, divide, and remainder.
-   Use the subroutines that the sysV68's library provides.
-   The `*' prevents an underscore from being prepended by the compiler.  */
-/* The '*' is also used by INIT_CUMULATIVE_ARGS */
-
-#define DIVSI3_LIBCALL "*ldiv%%"
-#define UDIVSI3_LIBCALL "*uldiv%%"
-#define MODSI3_LIBCALL "*lrem%%"
-#define UMODSI3_LIBCALL "*ulrem%%"
-#define MULSI3_LIBCALL "*lmul%%"
-
-struct sysV68_cumulative_args
-	{
-	int	offset;
-	int	libcall;
-	};
-
-#undef CUMULATIVE_ARGS
-#define CUMULATIVE_ARGS struct sysV68_cumulative_args
-
-#undef INIT_CUMULATIVE_ARGS
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
-do {(CUM).offset = 0;\
-(CUM).libcall = (LIBNAME) && (*XSTR((LIBNAME), 0) == '*');} while(0)
-
-#undef FUNCTION_ARG_ADVANCE
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM).offset += ((MODE) != BLKmode			\
-	    ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
-	    : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-#undef FUNCTION_ARG
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-(((CUM).libcall && (CUM).offset == 0) ? gen_rtx(REG, (MODE), 0)\
-: (TARGET_REGPARM && (CUM).offset < 8) ? gen_rtx (REG, (MODE), (CUM).offset / 4) : 0)
-
-#undef FUNCTION_ARG_PARTIAL_NREGS
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-((TARGET_REGPARM && (CUM).offset < 8				\
-  && 8 < ((CUM).offset + ((MODE) == BLKmode			\
-		      ? int_size_in_bytes (TYPE)		\
-		      : GET_MODE_SIZE (MODE))))  		\
- ? 2 - (CUM).offset / 4 : 0)
-
-#undef FUNCTION_ARG_REGNO_P
-#define FUNCTION_ARG_REGNO_P(N) (TARGET_68020 ? 0 : (N) == 0)
-
-/* manfred@lts.sel.alcatel.de: I believe that most delta machines are configured to have
-   a 6888[12] FPU for which we need to link -lm881 instead of -lm; define ALT_LIBM to
-   tell g++.c about that.  */
-#define ALT_LIBM	"-lm881"
-
-#if (TARGET_DEFAULT & MASK_68881)      /* The default configuration has a 6888[12] FPU. */
-#define MATH_LIBRARY	"-lm881"
-#endif
-
-/* Currently we do not have the atexit() function,
-   so take that from libgcc2.c */
-
-#define NEED_ATEXIT 1
-#define HAVE_ATEXIT 1
-
-#define EXIT_BODY	\
-  do								\
-    { 								\
-      __stop_monitor ();					\
-      _cleanup ();						\
-    } while (0)
-
-/* FINALIZE_TRAMPOLINE clears the instruction cache. */
-
-#undef FINALIZE_TRAMPOLINE
-#define FINALIZE_TRAMPOLINE(TRAMP)	\
-  if (!TARGET_68040)			\
-    ;					\
-  else					\
-    emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__clear_insn_cache"), \
-		       0, VOIDmode, 0)
diff --git a/gcc/config/m68k/mot3300Mcrt0.S b/gcc/config/m68k/mot3300Mcrt0.S
deleted file mode 100755
index 539fe8e..0000000
--- a/gcc/config/m68k/mot3300Mcrt0.S
+++ /dev/null
@@ -1,142 +0,0 @@
-/* The start module mcrt0.s for the SysV68 Motorola 3300 Delta Series.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Manfred Hollstein (manfred@lts.sel.alcatel.de).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#ifdef MOTOROLA
-# define COMM		comm
-# define DATA		data
-# define EVEN		even
-# define FILE(n)	file	n
-# define GLOBAL_SYM(s)	global	s
-# define LOCAL_LABEL(l)	L%##l
-# define IDENT(s)	ident	s
-# define TEXT		text
-#else /* Assume we are using GNU as.  */
-# define COMM		.comm
-# define DATA		.data
-# define EVEN		.even
-# define FILE(name)	.file	name
-# define GLOBAL_SYM(s)	.globl	s
-# define LOCAL_LABEL(l)	.L.##l
-# define IDENT(s)	.section .comment;.asciz s
-# define TEXT		.text
-#endif
-
-	FILE ("mcrt0.s")
-	TEXT
-	GLOBAL_SYM (_start)
-_start:	mov.l	%d0,splimit%
-	subq.w	&8,%sp
-	mov.l	8(%sp),(%sp)
-	lea	12(%sp),%a0
-	mov.l	%a0,___Argv
-	mov.l	%a0,4(%sp)
-	mov.l	%a0,%a1
-LOCAL_LABEL(0):
-	tst.l	(%a0)+
-	bne.b	LOCAL_LABEL(0)
-#ifdef SGS_CMP_ORDER
-	cmpa.l	%a0,(%a1)
-#else
-	cmpa.l	(%a1),%a0
-#endif
-	blt.b	LOCAL_LABEL(1)
-	subq.w	&4,%a0
-LOCAL_LABEL(1):
-	mov.l	%a0,8(%sp)
-	mov.l	%a0,environ
-	jsr	initfpu
-	
-	sub	&8,%sp
-	clr.l	%d0		/* if (! isatty (fileno (stderr))) */
-	mov.b	_iob+27,%d0
-	mov.l	%d0,-(%sp)
-	jsr	isatty
-	addq.w	&4,%sp
-	tst.l	%d0
-	bne.b	LOCAL_LABEL(isatty)
-	clr.l	-(%sp)		/*	setbuf (stderr, NULL) */
-	pea	_iob+28
-	jsr	setbuf
-	addq.w	&8,%sp
-LOCAL_LABEL(isatty):
-	addq.w	&8,%sp
-
-	mov.l	&600,-(%sp)
-	mov.l	&etext,%d1
-	subi.l	&LOCAL_LABEL(endofstart),%d1
-	addq.l	&1,%d1
-	bclr	&0,%d1
-	addi.l	&4812,%d1
-	asr.l	&1,%d1
-	mov.l	%d1,-(%sp)
-	add.l	%d1,%d1
-	mov.l	%d1,-(%sp)
-	jsr	sbrk
-	addq.w	&4,%sp
-#ifdef SGS_CMP_ORDER
-	cmpa.l	%a0,&-1
-#else
-	cmpa.l	&-1,%a0
-#endif
-	beq.b	LOCAL_LABEL(3)
-	mov.l	%a0,-(%sp)
-	add.l	&12,%a0
-	mov.l	%a0,_countbase
-	mov.l	&etext,-(%sp)
-	mov.l	&LOCAL_LABEL(endofstart),-(%sp)
-	jsr	monitor
-	lea	20(%sp),%sp
-	jsr	main
-	mov.l	%d0,(%sp)
-	jsr	exit
-_exit:	moveq	&1,%d0
-	trap	&0
-
-	GLOBAL_SYM (__stop_monitor)
-__stop_monitor:
-	clr.l	-(%sp)
-	jsr	monitor
-	add.w	&4,%sp
-	rts
-
-LOCAL_LABEL(errtxt):
-	byte	'N,'o,' ,'s,'p,'a,'c,'e,' ,'f,'o,'r,' ,'m,'o,'n
-	byte	'i,'t,'o,'r,' ,'b,'u,'f,'f,'e,'r,'\n
-LOCAL_LABEL(errtxt_end):
-
-	EVEN
-LOCAL_LABEL(3):
-	pea	LOCAL_LABEL(errtxt_end)-LOCAL_LABEL(errtxt)
-	pea	LOCAL_LABEL(errtxt)(%pc)
-	pea	2
-	jsr	write
-	bra.b	_exit
-LOCAL_LABEL(endofstart):
-	
-	EVEN
-
-	COMM	splimit%,4
-	COMM	environ,4
-	COMM	_countbase,4
-
-	IDENT ("$Id: mot3300Mcrt0.S,v 1.23 1999/01/15 07:37:19 law Exp $")
-	IDENT ("Contributed by Manfred Hollstein (manfred@lts.sel.alcatel.de)")
-	IDENT ("Corrections by Philippe De Muyter (phdm@macqel.be)")
diff --git a/gcc/config/m68k/netbsd.h b/gcc/config/m68k/netbsd.h
deleted file mode 100755
index 6bd9161..0000000
--- a/gcc/config/m68k/netbsd.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#include <m68k/m68k.h>
-
-/* Get generic NetBSD definitions.  */
-
-#include <netbsd.h>
-
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-
-/* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified.
-   This will control the use of inline 68881 insns in certain macros.  */
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__ -D__HAVE_FPU__} %{posix:-D_POSIX_SOURCE}"
-
-#undef ASM_SPEC
-#define ASM_SPEC " %| %{m68030} %{m68040} %{m68060} %{fpic:-k} %{fPIC:-k -K}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dunix -Dm68k -Dmc68000 -Dmc68020 -D__NetBSD__ -Asystem(unix) -Asystem(NetBSD) -Acpu(m68k) -Amachine(m68k)"
-
-/* Make gcc agree with <machine/ansi.h> */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "int"
-
-#undef WCHAR_UNSIGNED
-#define WCHAR_UNSIGNED 0
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 32
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Do not break .stabs pseudos into continuations.  */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* This is the char to use for continuation (in case we need to turn
-   continuation back on).  */
-
-#define DBX_CONTIN_CHAR '?'
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Until they use ELF or something that handles dwarf2 unwinds
-   and initialization stuff better.  */
-#define DWARF2_UNWIND_INFO 0
-
diff --git a/gcc/config/m68k/news.h b/gcc/config/m68k/news.h
deleted file mode 100755
index f83524c..0000000
--- a/gcc/config/m68k/news.h
+++ /dev/null
@@ -1,552 +0,0 @@
-/* Definitions of target machine for GNU compiler.  SONY NEWS-OS 4 version.
-   Copyright (C) 1987, 89, 93, 94, 96, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#ifndef USE_GAS
-/* This controls conditionals in m68k.h.  */
-#define MOTOROLA		/* Use Motorola syntax rather than "MIT" */
-#define SGS_NO_LI		/* Suppress jump table label usage */
-#endif
-
-#define NO_DOLLAR_IN_LABEL
-#define NO_DOT_IN_LABEL
-
-#include "m68k/m68k.h"
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-
-/* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified.
-   This will control the use of inline 68881 insns in certain macros.  */
-
-#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-/* These are the ones defined by Sony, plus mc68000 for uniformity with
-   GCC on other 68000 systems.  */
-
-#ifdef MOTOROLA
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews700 -D__motorola__ -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-#else
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews700 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-#endif
-
-/* These conditionals tested for different submodels,
-   but they were incorrect since they tested the host rather than the target.
-   The choice of model shouldn't actually matter.  */
-
-#if 0
-#ifdef news800
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews800 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-#endif
-#ifdef news900
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews900 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-#endif
-#ifdef news1500
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dmc68030 -Dnews1500 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-#endif
-#ifdef news1700
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dmc68030 -Dnews1700 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-#endif
-#ifdef news1800
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dmc68030 -Dnews1800 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-#endif
-#ifdef news1900
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dmc68030 -Dnews1900 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-#endif
-#endif
-
-/* Link with libg.a when debugging, for dbx's sake.  */
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-#if 0
-/* This is to be compatible with types.h.
-   It was found to be necessary with Newsos 3.  */
-
-#define SIZE_TYPE "long int"
-#endif
-
-/* Override parts of m68k.h to fit Sony's assembler syntax.  */
-
-#undef BIGGEST_ALIGNMENT
-#undef CALL_USED_REGISTERS
-#undef FUNCTION_VALUE
-#undef LIBCALL_VALUE
-#undef FUNCTION_PROFILER
-
-#ifdef MOTOROLA
-#undef FUNCTION_PROLOGUE
-#undef FUNCTION_EPILOGUE
-#undef REGISTER_NAMES
-#undef ASM_OUTPUT_REG_PUSH
-#undef ASM_OUTPUT_REG_POP
-#undef ASM_OUTPUT_DOUBLE
-#undef ASM_OUTPUT_SKIP
-#undef ASM_FORMAT_PRIVATE_NAME
-#endif  
-
-#undef ASM_OUTPUT_ALIGN
-
-/* There is no point aligning anything to a rounder boundary than this.  */
-#define BIGGEST_ALIGNMENT 32
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-  
-/* NEWS makes d2, d3, fp2 and fp3 unsaved registers, unlike the Sun system.  */
-  
-#define CALL_USED_REGISTERS \
- {1, 1, 1, 1, 0, 0, 0, 0, \
-  1, 1, 0, 0, 0, 0, 0, 1, \
-  1, 1, 1, 1, 0, 0, 0, 0}
-
-/* NEWS returns floats and doubles in fp0, not d0/d1.  */
-
-#define FUNCTION_VALUE(VALTYPE,FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
-
-#define LIBCALL_VALUE(MODE)						   \
- gen_rtx (REG, (MODE),							   \
-	  ((TARGET_68881						   \
-	    && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) \
-	   ? 16 : 0))
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  fprintf (FILE, "\t.align %d\n", (LOG))
-
-#ifdef MOTOROLA
-
-/* Don't try to define `gcc_compiled.' since the assembler does not
-   accept symbols with periods.  This is no real loss since GDB only
-   really needs it for parms passed in registers.  */
-#define ASM_IDENTIFY_GCC(FILE)
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)     \
-{ register int regno;						\
-  register int mask = 0;					\
-  extern char call_used_regs[];					\
-  int fsize = ((SIZE) + 3) & -4;				\
-  if (frame_pointer_needed)					\
-    { if (fsize < 0x8000)			                \
-        fprintf (FILE, "\tlink fp,#%d\n", -fsize);		\
-      else if (TARGET_68020)                                    \
-        fprintf (FILE, "\tlink.l fp,#%d\n", -fsize);            \
-      else							\
-	fprintf (FILE, "\tlink fp,#0\n\tsub.l #%d,sp\n", fsize);\
-    }								\
-  else if (fsize)						\
-    {								\
-      int amt = fsize + 4;					\
-      /* Adding negative number is faster on the 68040.  */	\
-      if (fsize + 4 < 0x8000)					\
-	asm_fprintf (FILE, "\tadd.w %0I%d,%Rsp\n", - amt);	\
-      else							\
-	asm_fprintf (FILE, "\tadd.l %0I%d,%Rsp\n", - amt);	\
-    }								\
-  for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++)	\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-       mask |= 1 << (regno - 16);				\
-  if (mask != 0)						\
-    fprintf (FILE, "\tfmovem.x #0x%x,-(sp)\n", mask & 0xff);    \
-  mask = 0;							\
-  for (regno = 0; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-       mask |= 1 << (15 - regno);				\
-  if (frame_pointer_needed)					\
-    mask &= ~ (1 << (15-FRAME_POINTER_REGNUM));			\
-  if (exact_log2 (mask) >= 0)					\
-    fprintf (FILE, "\tmove.l %s,-(sp)\n", reg_names[15 - exact_log2 (mask)]);  \
-  else if (mask) fprintf (FILE, "\tmovem.l #0x%x,-(sp)\n", mask); }
-
-#define FUNCTION_PROFILER(FILE, LABEL_NO) \
-   fprintf (FILE, "\tmove.l #LP%d,d0\n\tjsr mcount\n", (LABEL_NO));
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-{ register int regno;						\
-  register int mask, fmask;					\
-  register int nregs;						\
-  int offset, foffset;						\
-  extern char call_used_regs[];					\
-  int fsize = ((SIZE) + 3) & -4;				\
-  int big = 0;							\
-  nregs = 0;  fmask = 0;					\
-  for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++)	\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      { nregs++; fmask |= 1 << (23 - regno); }			\
-  foffset = nregs * 12;						\
-  nregs = 0;  mask = 0;						\
-  if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \
-  for (regno = 0; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      { nregs++; mask |= 1 << regno; }				\
-  offset = foffset + nregs * 4;					\
-  if (offset + fsize >= 0x8000 					\
-      && frame_pointer_needed					\
-      && (mask || fmask))					\
-    { fprintf (FILE, "\tmove.l #%d,a0\n", -fsize);		\
-      fsize = 0, big = 1; }					\
-  if (exact_log2 (mask) >= 0) {					\
-    if (big)							\
-      fprintf (FILE, "\tmove.l (-%d,fp,a0.l),%s\n",		\
-	       offset + fsize, reg_names[exact_log2 (mask)]);	\
-    else if (! frame_pointer_needed)				\
-      fprintf (FILE, "\tmove.l (sp)+,%s\n",			\
-	       reg_names[exact_log2 (mask)]);			\
-    else							\
-      fprintf (FILE, "\tmove.l (-%d,fp),%s\n",			\
-	       offset + fsize, reg_names[exact_log2 (mask)]); }	\
-  else if (mask) {						\
-    if (big)							\
-      fprintf (FILE, "\tmovem.l (-%d,fp,a0.l),#0x%x\n",		\
-	       offset + fsize, mask);				\
-    else if (! frame_pointer_needed)				\
-      fprintf (FILE, "\tmovem.l (sp)+,#0x%x\n", mask);		\
-    else							\
-      fprintf (FILE, "\tmovem.l (-%d,fp),#0x%x\n",		\
-	       offset + fsize, mask); }				\
-  if (fmask) {							\
-    if (big)							\
-      fprintf (FILE, "\tfmovem.x (-%d,fp,a0.l),#0x%x\n",	\
-	       foffset + fsize, fmask);				\
-    else if (! frame_pointer_needed)				\
-      fprintf (FILE, "\tfmovem.x (sp)+,#0x%x\n", fmask);	\
-    else							\
-      fprintf (FILE, "\tfmovem.x (-%d,fp),#0x%x\n",		\
-	       foffset + fsize, fmask); }			\
-  if (frame_pointer_needed)					\
-    fprintf (FILE, "\tunlk fp\n");				\
-  else if (fsize)						\
-    {								\
-      if (fsize + 4 < 0x8000)					\
-	fprintf (FILE, "\tadd.w #%d,sp\n", fsize + 4);		\
-      else							\
-	fprintf (FILE, "\tadd.l #%d,sp\n", fsize + 4);		\
-    }								\
-  if (current_function_pops_args)				\
-    fprintf (FILE, "\trtd #%d\n", current_function_pops_args);	\
-  else fprintf (FILE, "\trts\n"); }
-
-/* Difference from m68k.h is in `fp' instead of `a6'.  */
-
-#define REGISTER_NAMES \
-{"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",	\
- "a0", "a1", "a2", "a3", "a4", "a5", "fp", "sp",	\
- "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7"}
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tmove.l %s,-(sp)\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tmove.l (sp)+,%s\n", reg_names[REGNO])
-  
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.double 0d%s\n", dstr);		\
-   } while (0)
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %u\n", (SIZE))
-
-#if 0
-/* The NEWS assembler in version 3.4 complains about fmove.d, but this
-   macro proved not to work right.  3.4 is old, so forget about it. */
-#define ASM_OUTPUT_OPCODE(FILE, STRING) \
-{						\
-  if (!strncmp (STRING, "fmove.d", 7)		\
-      && CONSTANT_P (operands[1]))		\
-    {						\
-      fprintf (FILE, "fmove.x");		\
-      STRING += 7;				\
-    }						\
-}
-#endif
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 13),	\
-  sprintf ((OUTPUT), "%s$$$%d", (NAME), (LABELNO)))
-
-/* Output a float value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)			\
- do {									\
-      if (CODE == 'f')							\
-        {								\
-          char dstr[30];						\
-          REAL_VALUE_TO_DECIMAL (VALUE, "%.9e", dstr);			\
-          if (REAL_VALUE_ISINF (VALUE) || REAL_VALUE_ISNAN (VALUE))	\
-	    {								\
-	      if (REAL_VALUE_NEGATIVE (VALUE))				\
-		fprintf (FILE, "#0f-99e999");				\
-	      else							\
-		fprintf (FILE, "#0f99e999");				\
-	    }								\
-          else if (REAL_VALUE_MINUS_ZERO (VALUE))			\
-            fprintf (FILE, "#0f-0.0");					\
-          else								\
-            fprintf (FILE, "#0f%s", dstr); 				\
-        }								\
-      else								\
-        {								\
-          long l;							\
-          REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);			\
-          fprintf (FILE, "#0x%lx", l);					\
-        }								\
-     } while (0)
-
-/* Output a double value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)				\
- do { char dstr[30];							\
-      REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", dstr );			\
-      if (REAL_VALUE_ISINF (VALUE) || REAL_VALUE_ISNAN (VALUE))		\
-	{								\
-        if (REAL_VALUE_NEGATIVE (VALUE))				\
-          fprintf (FILE, "#0d-99e999");					\
-        else								\
-          fprintf (FILE, "#0d99e999");					\
-	}								\
-      else if (REAL_VALUE_MINUS_ZERO (VALUE))				\
-          fprintf (FILE, "#0d-0.0");					\
-      else								\
-          fprintf (FILE, "#0d%s", dstr);				\
-    } while (0)
-
-/* Note, long double immediate operands are not actually
-   generated by m68k.md.  */
-#undef ASM_OUTPUT_LONG_DOUBLE_OPERAND
-#define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE)			\
- do { char dstr[30];							\
-      REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr);			\
-      asm_fprintf (FILE, "%I0r%s", dstr);				\
-    } while (0)
-
-#if 0
-#undef PRINT_OPERAND
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ if (CODE == '.') fprintf (FILE, ".");					\
-  else if (CODE == '#') fprintf (FILE, "#");				\
-  else if (CODE == '-') fprintf (FILE, "-(sp)");			\
-  else if (CODE == '+') fprintf (FILE, "(sp)+");			\
-  else if (CODE == '@') fprintf (FILE, "(sp)");				\
-  else if (CODE == '!') fprintf (FILE, "fpcr");				\
-  else if (CODE == '$') {if (TARGET_68040_ONLY) fprintf (FILE, "s");}	\
-  else if (CODE == '&') {if (TARGET_68040_ONLY) fprintf (FILE, "d");}	\
-  else if (CODE == '/')							\
-    ;									\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode)	\
-    { REAL_VALUE_TYPE r;						\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      if (CODE == 'f')							\
-        { char dstr[30];						\
-          REAL_VALUE_TO_DECIMAL (r, "%.9e", dstr);			\
-          if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r)) {		\
-            if (REAL_VALUE_NEGATIVE (r))				\
-              fprintf (FILE, "#0f-99e999");				\
-            else							\
-              fprintf (FILE, "#0f99e999"); }				\
-          else if (REAL_VALUE_MINUS_ZERO (r))				\
-            fprintf (FILE, "#0f-0.0");					\
-          else								\
-            fprintf (FILE, "#0f%s", dstr); 				\
-        }								\
-      else								\
-        { long l;							\
-          REAL_VALUE_TO_TARGET_SINGLE (r, l);				\
-          fprintf (FILE, "#0x%x", l);					\
-        }}								\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == XFmode)	\
-    { REAL_VALUE_TYPE r;						\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      ASM_OUTPUT_LONG_DOUBLE_OPERAND (FILE, r); }			\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode)	\
-    { REAL_VALUE_TYPE r; char dstr[30];					\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      REAL_VALUE_TO_DECIMAL (r, "%.20e", dstr );			\
-      if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r)) {		\
-        if (REAL_VALUE_NEGATIVE (r))					\
-          fprintf (FILE, "#0d-99e999");					\
-        else								\
-          fprintf (FILE, "#0d99e999"); }				\
-      else if (REAL_VALUE_MINUS_ZERO (r))				\
-          fprintf (FILE, "#0d-0.0");					\
-      else								\
-          fprintf (FILE, "#0d%s", dstr); }				\
-  else if (CODE == 'b') output_addr_const (FILE, X);			\
-  else { putc ('#', FILE); output_addr_const (FILE, X); }}
-#endif
-
-#undef PRINT_OPERAND_ADDRESS
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx reg1, reg2, breg, ireg;					\
-  register rtx addr = ADDR;						\
-  rtx offset;								\
-  switch (GET_CODE (addr))						\
-    {									\
-    case REG:								\
-      fprintf (FILE, "(%s)", reg_names[REGNO (addr)]);			\
-      break;								\
-    case PRE_DEC:							\
-      fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case POST_INC:							\
-      fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case PLUS:								\
-      reg1 = 0;	reg2 = 0;						\
-      ireg = 0;	breg = 0;						\
-      offset = 0;							\
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))				\
-	{								\
-	  offset = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))			\
-	{								\
-	  offset = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) != PLUS) ;					\
-      else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT		\
-	  || GET_CODE (addr) == SIGN_EXTEND)				\
-	{ if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; }	\
-      if (offset != 0) { if (addr != 0) abort (); addr = offset; }	\
-      if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND			\
-		    || GET_CODE (reg1) == MULT))			\
-	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))		\
-	{ breg = reg2; ireg = reg1; }					\
-      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))		\
-	{ breg = reg1; ireg = reg2; }					\
-      if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { int scale = 1;						\
-	  if (GET_CODE (ireg) == MULT)					\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (GET_CODE (ireg) == SIGN_EXTEND)				\
-	    fprintf (FILE, "(L%d.b,pc,%s.w",				\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (XEXP (ireg, 0))]); 		\
-	  else								\
-	    fprintf (FILE, "(L%d.b,pc,%s.l",				\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (ireg)]);				\
-	  if (scale != 1) fprintf (FILE, "*%d", scale);			\
-	  putc (')', FILE);						\
-	  break; }							\
-      if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { fprintf (FILE, "(L%d.b,pc,%s.l",				\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   reg_names[REGNO (breg)]);				\
-	  putc (')', FILE);						\
-	  break; }							\
-      if (ireg != 0 || breg != 0)					\
-	{ int scale = 1;						\
-	  if (breg == 0)						\
-	    abort ();							\
-	  if (addr && GET_CODE (addr) == LABEL_REF) abort ();		\
-	  fprintf (FILE, "(");						\
-	  if (addr != 0) {						\
-	    output_addr_const (FILE, addr);				\
-	    putc (',', FILE); }						\
-	  fprintf (FILE, "%s", reg_names[REGNO (breg)]);		\
-	  if (ireg != 0)						\
-	    putc (',', FILE);						\
-	  if (ireg != 0 && GET_CODE (ireg) == MULT)			\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)		\
-	    fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);	\
-	  else if (ireg != 0)						\
-	    fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]);		\
-	  if (scale != 1) fprintf (FILE, "*%d", scale);			\
-	  putc (')', FILE);						\
-	  break;							\
-	}								\
-      else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF)		\
-	{ fprintf (FILE, "(L%d.b,pc,%s.l)",				\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   reg_names[REGNO (reg1)]);				\
-	  break; }							\
-    default:								\
-      if (GET_CODE (addr) == CONST_INT					\
-	  && INTVAL (addr) < 0x8000					\
-	  && INTVAL (addr) >= -0x8000)					\
-	fprintf (FILE, "%d.w", INTVAL (addr));				\
-      else								\
-        output_addr_const (FILE, addr);					\
-    }}
-
-#else /* Using GAS, which uses the MIT assembler syntax, like a Sun.  */
-
-#define FUNCTION_PROFILER(FILE, LABEL_NO) \
-   fprintf (FILE, "\tmovl #LP%d,d0\n\tjsr mcount\n", (LABEL_NO));
-
-#endif /* MOTOROLA */
diff --git a/gcc/config/m68k/news3.h b/gcc/config/m68k/news3.h
deleted file mode 100755
index b4a3f41..0000000
--- a/gcc/config/m68k/news3.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#include "m68k/news.h"
-
-/* This is to be compatible with types.h.
-   It was found to be necessary with Newsos 3.  */
-
-#define SIZE_TYPE "long int"
diff --git a/gcc/config/m68k/news3gas.h b/gcc/config/m68k/news3gas.h
deleted file mode 100755
index 7c2d2b0..0000000
--- a/gcc/config/m68k/news3gas.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#include "m68k/newsgas.h"
-
-/* This is to be compatible with types.h.
-   It was found to be necessary with Newsos 3.  */
-
-#define SIZE_TYPE "long int"
diff --git a/gcc/config/m68k/newsgas.h b/gcc/config/m68k/newsgas.h
deleted file mode 100755
index 8dc7801..0000000
--- a/gcc/config/m68k/newsgas.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* In Sony versions before 3.0, use the GNU Assembler, because the
-   system's assembler has no way to assemble the difference of two
-   labels for the displacement in a switch-dispatch instruction.  */  
-
-#define USE_GAS
-
-/* This is the assembler directive to equate two values.  */
-
-#undef SET_ASM_OP
-#define SET_ASM_OP    ".set"
-
-/* This is how we tell the assembler that a symbol is weak.  */
-
-#undef ASM_WEAKEN_LABEL
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
-  do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \
-       fputc ('\n', FILE); } while (0)
-
-#include "m68k/news.h"
diff --git a/gcc/config/m68k/next.h b/gcc/config/m68k/next.h
deleted file mode 100755
index 8391ab5..0000000
--- a/gcc/config/m68k/next.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/* Target definitions for GNU compiler for mc680x0 running NeXTSTEP
-   Copyright (C) 1989, 90-94, 96, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m68k/m68k.h"
-#include "nextstep.h"
-
-/* See m68k.h.  0407 means 68040 (or 68030 or 68020, with 68881/2).  */
-
-#define TARGET_DEFAULT (MASK_68040|MASK_BITFIELD|MASK_68881|MASK_68020)
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-
-#undef	STACK_BOUNDARY
-#define STACK_BOUNDARY 32
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dmc68000 -Dm68k -DNeXT -Dunix -D__MACH__ -D__BIG_ENDIAN__ -D__ARCHITECTURE__=\"m68k\" -Asystem(unix)  -Asystem(mach) -Acpu(m68k) -Amachine(m68k) -D_NEXT_SOURCE"
-
-/* Every structure or union's size must be a multiple of 2 bytes.
-   (Why isn't this in m68k.h?)  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#undef	ASM_OUTPUT_DOUBLE
-#ifdef REAL_VALUE_TO_TARGET_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
-  do {									\
-    long hex[2];							\
-    REAL_VALUE_TO_TARGET_DOUBLE (VALUE, hex);				\
-    fprintf (FILE, "\t.long 0x%x\n\t.long 0x%x\n", hex[0], hex[1]);	\
-  } while (0)
-#else
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
- do { if (REAL_VALUE_ISINF (VALUE))					\
-        {								\
-          if (REAL_VALUE_NEGATIVE (VALUE))				\
-            fprintf (FILE, "\t.double 0r-99e999\n");			\
-          else								\
-            fprintf (FILE, "\t.double 0r99e999\n");			\
-        }								\
-      else								\
-        { char dstr[30];						\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);		\
-          fprintf (FILE, "\t.double 0r%s\n", dstr);			\
-        }								\
-    } while (0)
-#endif
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#undef	ASM_OUTPUT_FLOAT
-#ifdef REAL_VALUE_TO_TARGET_SINGLE
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
-  do {									\
-    long hex;								\
-    REAL_VALUE_TO_TARGET_SINGLE (VALUE, hex);				\
-    fprintf (FILE, "\t.long 0x%x\n", hex);				\
-  } while (0)
-#else
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
- do { if (REAL_VALUE_ISINF (VALUE))					\
-        {								\
-          if (REAL_VALUE_NEGATIVE (VALUE))				\
-            fprintf (FILE, "\t.single 0r-99e999\n");			\
-          else								\
-            fprintf (FILE, "\t.single 0r99e999\n");			\
-        }								\
-      else								\
-        { char dstr[30];						\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);		\
-          fprintf (FILE, "\t.single 0r%s\n", dstr);			\
-        }								\
-    } while (0)
-#endif
-
-#undef	ASM_OUTPUT_FLOAT_OPERAND
-#ifdef REAL_VALUE_TO_TARGET_SINGLE
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)			\
-  do {									\
-    long hex;								\
-    REAL_VALUE_TO_TARGET_SINGLE (VALUE, hex);				\
-    fprintf (FILE, "#0%c%x", (CODE) == 'f' ? 'b' : 'x', hex);		\
-  } while (0)
-#else
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)		\
-  do{ 								\
-      if (CODE != 'f')						\
-        {							\
-          long l;						\
-          REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-          if (sizeof (int) == sizeof (long))			\
-            asm_fprintf ((FILE), "%I0x%x", l);			\
-          else							\
-            asm_fprintf ((FILE), "%I0x%lx", l);			\
-        }							\
-      else if (REAL_VALUE_ISINF (VALUE))			\
-        {							\
-          if (REAL_VALUE_NEGATIVE (VALUE))			\
-            fprintf (FILE, "#0r-99e999");			\
-          else							\
-            fprintf (FILE, "#0r99e999");			\
-        }							\
-      else							\
-        { char dstr[30];					\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.9g", dstr);	\
-          fprintf (FILE, "#0r%s", dstr);			\
-        }							\
-    } while (0)
-#endif
-
-#undef	ASM_OUTPUT_DOUBLE_OPERAND
-#ifdef REAL_VALUE_TO_TARGET_DOUBLE
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)				\
-  do {									\
-    long hex[2];							\
-    REAL_VALUE_TO_TARGET_DOUBLE (VALUE, hex);				\
-    fprintf (FILE, "#0b%x%08x", hex[0], hex[1]);			\
-  } while (0)
-#else
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)				\
- do { if (REAL_VALUE_ISINF (VALUE))					\
-        {								\
-          if (REAL_VALUE_NEGATIVE (VALUE))				\
-            fprintf (FILE, "#0r-99e999");				\
-          else								\
-            fprintf (FILE, "#0r99e999");				\
-        }								\
-      else								\
-        { char dstr[30];						\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.20g", dstr);		\
-          fprintf (FILE, "#0r%s", dstr);				\
-        }								\
-    } while (0)
-#endif
-
-/* We do not define JUMP_TABLES_IN_TEXT_SECTION, since we wish to keep
-   the text section pure.  There is no point in addressing the jump
-   tables using pc relative addressing, since they are not in the text
-   section, so we undefine CASE_VECTOR_PC_RELATIVE.  This also
-   causes the compiler to use absolute addresses in the jump table,
-   so we redefine CASE_VECTOR_MODE to be SImode. */
-
-#undef	CASE_VECTOR_MODE
-#define CASE_VECTOR_MODE SImode
-#undef	CASE_VECTOR_PC_RELATIVE
-
-/* Make sure jump tables have the same alignment as other pointers.  */
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN)	\
-{ ASM_OUTPUT_ALIGN (FILE, 1); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
-
-/* Don't treat addresses involving labels differently from symbol names.
-   Previously, references to labels generated pc-relative addressing modes
-   while references to symbol names generated absolute addressing modes.  */
-
-#undef	GO_IF_INDEXABLE_BASE
-#define GO_IF_INDEXABLE_BASE(X, ADDR)	\
-{ if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
-
-/* This accounts for the return pc and saved fp on the m68k. */
-
-#define OBJC_FORWARDING_STACK_OFFSET 8
-#define OBJC_FORWARDING_MIN_OFFSET 8
-
-/* FINALIZE_TRAMPOLINE enables executable stack.  The
-   __enable_execute_stack also clears the insn cache. */
-
-#undef FINALIZE_TRAMPOLINE
-#define FINALIZE_TRAMPOLINE(TRAMP) \
-  emit_library_call(gen_rtx(SYMBOL_REF, Pmode, "__enable_execute_stack"), \
-		    0, VOIDmode, 1, memory_address(SImode, (TRAMP)), Pmode)
-
-/* A C expression used to clear the instruction cache from 
-   address BEG to address END.   On NeXTSTEP this i a system trap. */
-
-#define CLEAR_INSN_CACHE(BEG, END)   \
-   asm volatile ("trap #2")
-
-/* GCC is the primary compiler for NeXTSTEP, so we don't need this.  */
-#undef PCC_STATIC_STRUCT_RETURN
diff --git a/gcc/config/m68k/next21.h b/gcc/config/m68k/next21.h
deleted file mode 100755
index 5d18c4e..0000000
--- a/gcc/config/m68k/next21.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Target definitions for GNU compiler for mc680x0 running NeXTSTEP 2.1
-   Copyright (C) 1989, 90, 91, 92, 93, 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Changed for NeXTStep2.1, Ch. Kranz, 2/94, 3/94 */
-
-#include "m68k/next.h"
-#include "nextstep21.h"
-
-/* for #include <mach.h> in libgcc2.c */
-#define NeXTStep21	
-
-#undef	ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
- do { if (REAL_VALUE_ISINF (VALUE))					\
-        {								\
-          if (REAL_VALUE_NEGATIVE (VALUE))				\
-            fprintf (FILE, "#0r-99e999");				\
-          else								\
-            fprintf (FILE, "#0r99e999");				\
-        }								\
-      else								\
-        { char dstr[30];						\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);		\
-          fprintf (FILE, "\t.double 0r%s\n", dstr);			\
-        }								\
-    } while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#undef	ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
- do { if (REAL_VALUE_ISINF (VALUE))					\
-        {								\
-          if (REAL_VALUE_NEGATIVE (VALUE))				\
-            fprintf (FILE, "\t.single 0r-99e999\n");			\
-          else								\
-            fprintf (FILE, "\t.single 0r99e999\n");			\
-        }								\
-      else								\
-        { char dstr[30];						\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);		\
-          fprintf (FILE, "\t.single 0r%s\n", dstr);			\
-        }								\
-    } while (0)
-
-/* called from m68k.c line 1881 */
-#undef	ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)		\
-  do{ 								\
-      if (CODE != 'f')						\
-        {							\
-          long l;						\
-          REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-          if (sizeof (int) == sizeof (long))			\
-            asm_fprintf ((FILE), "%I0x%x", l);			\
-          else							\
-            asm_fprintf ((FILE), "%I0x%lx", l);			\
-        }							\
-      else if (REAL_VALUE_ISINF (VALUE))			\
-        {							\
-          if (REAL_VALUE_NEGATIVE (VALUE))			\
-            fprintf (FILE, "#0r-99e999");			\
-          else							\
-            fprintf (FILE, "#0r99e999");			\
-        }							\
-      else							\
-        { char dstr[30];					\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.9g", dstr);	\
-          fprintf (FILE, "#0r%s", dstr);			\
-        }							\
-    } while (0)
-
-#undef	ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)				\
- do { if (REAL_VALUE_ISINF (VALUE))					\
-        {								\
-          if (REAL_VALUE_NEGATIVE (VALUE))				\
-            fprintf (FILE, "#0r-99e999");				\
-          else								\
-            fprintf (FILE, "#0r99e999");				\
-        }								\
-      else								\
-       { char dstr[30];							\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.20g", dstr);		\
-          fprintf (FILE, "#0r%s", dstr);				\
-       }								\
-    } while (0)
-
diff --git a/gcc/config/m68k/os68000.h b/gcc/config/m68k/os68000.h
deleted file mode 100755
index 8f88769..0000000
--- a/gcc/config/m68k/os68000.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* CYGNUS LOCAL ericsson */
-/* Definitions of target machine for GNU compiler.  Vxworks 68010 version.
-   Copyright 1987, 1988, 1992 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-
-#include "m68k/m68k.h"
-#include "aoutos.h"
-
-/* See m68k.h.  0 means 68000 with no 68881.  */
-
-#define TARGET_DEFAULT 0
-
-/* Define __HAVE_68881 in preprocessor only if -m68881 is specified.
-   This will control the use of inline 68881 insns in certain macros.
-   Also inform the program which CPU this is for.  */
-
-#define CPP_SPEC "%{m68881:-D__HAVE_68881__} \
-%{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}"
-
-/* -m68020 requires special flags to the assembler.  */
-
-#define ASM_SPEC \
- "%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!m68020:-mc68000}}"
-  
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dmc68000"
-
-/* Prevent error on `-sun2' and `-target sun2' options.  */
-
-#define CC1_SPEC "%{sun2:} %{target:}"
-
-#define PTRDIFF_TYPE "int"
-#define SIZE_TYPE "unsigned int"
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
-
-/* Specify what to link with.  */
-
-/* VxWorks does all the library stuff itself.  */
-
-#define LIB_SPEC ""
-
-/* Provide required defaults for linker -e. */
- 
-#define LINK_SPEC "%{!nostdlib:%{!r*:%{!e*:-e start}}}"
-
-/* VxWorks provides the functionality of crt0.o and friends itself.  */
-
-#define STARTFILE_SPEC ""
-
-/* Alignment of field after `int : 0' in a structure.  */
-
-#undef EMPTY_FIELD_BOUNDARY
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
diff --git a/gcc/config/m68k/ose68k.h b/gcc/config/m68k/ose68k.h
deleted file mode 100755
index ebe8846..0000000
--- a/gcc/config/m68k/ose68k.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* CYGNUS LOCAL ericsson */
-/* Definitions of target machine for GNU compiler.  OSE ^68000/68020 version.
-   Copyright 1987, 1988, 1992, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* See m68k.h for the macro values */
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-
-#include "m68k/m68k-none.h"
-#include "aoutos.h"
-
-#define DBX_DEBUGGING_INFO
-#undef SDB_DEBUGGING_INFO
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
-
-/* Provide required defaults for linker -e. */
-#define LINK_SPEC "%{!nostdlib:%{!r*:%{!e*:-e start}}}"
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* User must provide startfile if desired.  */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
diff --git a/gcc/config/m68k/pbb.h b/gcc/config/m68k/pbb.h
deleted file mode 100755
index 41319c2..0000000
--- a/gcc/config/m68k/pbb.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Citicorp/TTI Unicom PBB version (using GAS with a %-register prefix)
-   Copyright (C) 1987, 1988, 1990, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Note:   This config uses a version of gas with a postprocessing stage that
-   converts the output of gas to coff containing stab debug symbols.
-   (See vasta@apollo.com or mb@soldev.tti.com) */
-
-#include "m68k/m68k.h"
-
-/* See m68k.h.  5 means 68020 without 68881.  */
-
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68020)
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Define __HAVE_68881__ in preprocessor if -m68881 is specified.
-   This will control the use of inline 68881 insns in certain macros.  */
-
-#define CPP_SPEC "%{m68881:-D__HAVE_68881__}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dm68k -Dunix -DUnicomPBB -Dmc68k -Dmc68020 -Dmc68k32 -Asystem(unix)  -Acpu(m68k) -Amachine(m68k)"
-
-/* We want DBX format for use with gdb under COFF.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Generate calls to memcpy, memcmp and memset.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* -m68000 requires special flags to the assembler. */
-
-#define ASM_SPEC \
- " %{m68000:-mc68010}%{mc68000:-mc68010}"
-
-/* we use /lib/libp/lib*  when profiling */
-
-#define LIB_SPEC "%{p:-L/usr/lib/libp} %{pg:-L/usr/lib/libp} -lc"
-
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-/*
- * The loader directive file gcc.ifile defines how to merge the constructor 
- * sections into the data section.  Also, since gas only puts out those 
- * sections in response to N_SETT stabs, and does not (yet) have a 
- * ".sections" directive, gcc.ifile also defines the list symbols 
- * __DTOR_LIST__ and __CTOR_LIST__.
- * 
- * Finally, we must explicitly specify the file from libgcc.a that defines
- * exit(), otherwise if the user specifies (for example) "-lc_s" on the 
- * command line, the wrong exit() will be used and global destructors will 
- * not get called .
- */
-
-#define STARTFILE_SPEC \
-"%{!r: gcc.ifile%s} %{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} \
-%{!r:_exit.o%s}"
-
-#define ENDFILE_SPEC "crtn.o%s"
-
-/* cpp has to support a #sccs directive for the /usr/include files */
-
-#define SCCS_DIRECTIVE
-
-/* GAS register prefix assembly syntax: */
-
-/* User labels have no prefix */
-#undef  USER_LABEL_PREFIX 
-#define USER_LABEL_PREFIX ""
-
-/* local labels are prefixed with ".L" */
-#undef  LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX "."
-
-/* registers are prefixed with "%" */
-#undef  REGISTER_PREFIX
-#define REGISTER_PREFIX "%"
-
-#undef REGISTER_NAMES
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",	\
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp",	\
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7"}
-
-#undef FUNCTION_EXTRA_EPILOGUE
-#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)				\
-  { extern int current_function_returns_pointer;			\
-    if ((current_function_returns_pointer) &&				\
-      ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode))        \
-      asm_fprintf (FILE, "\tmovl %Rd0,%Ra0\n"); } 
-
-#define ASM_RETURN_CASE_JUMP \
-  do {						\
-    if (TARGET_5200)				\
-      return "ext%.l %0\n\tjmp %%pc@(2,%0:l)";	\
-    else					\
-      return "jmp %%pc@(2,%0:w)";		\
-  } while (0)
-
-/* Although the gas we use can create .ctor and .dtor sections from N_SETT
-   stabs, it does not support section directives, so we need to have the loader
-   define the lists.
- */
-#define CTOR_LISTS_DEFINED_EXTERNALLY
-
-/* similar to default, but allows for the table defined by ld with gcc.ifile. 
-   nptrs is always 0.  So we need to instead check that __DTOR_LIST__[1] != 0.
-   The old check is left in so that the same macro can be used if and when  
-   a future version of gas does support section directives. */
-
-#define DO_GLOBAL_DTORS_BODY {int nptrs = *(int *)__DTOR_LIST__; int i; \
-  if (nptrs == -1 || (__DTOR_LIST__[0] == 0 && __DTOR_LIST__[1] != 0))  \
-    for (nptrs = 0; __DTOR_LIST__[nptrs + 1] != 0; nptrs++); 		\
-  for (i = nptrs; i >= 1; i--)						\
-    __DTOR_LIST__[i] (); }
-
-/* 
- * Here is an example gcc.ifile.  I've tested it on PBB 68k and on sco 386
- * systems. The NEXT(0x200000) works on just about all 386 and m68k systems, 
- * but can be reduced to any power of 2 that is >= NBPS (0x10000 on a pbb).
-
-   SECTIONS {
-       .text BIND(0x200200) BLOCK (0x200) : 
-		{ *(.init) *(.text) vfork = fork; *(.fini) }
-
-      	GROUP BIND( NEXT(0x200000) + ADDR(.text) + SIZEOF(.text)):
-	{      .data : { __CTOR_LIST__ = . ; . += 4; *(.ctor) . += 4 ;
-		       	 __DTOR_LIST__ = . ; . += 4; *(.dtor) . += 4 ; }
-	       .bss : { }
-       }
-  }
- */
-
-/*
-Local variables:
-version-control: t
-End:
-*/
diff --git a/gcc/config/m68k/plexus.h b/gcc/config/m68k/plexus.h
deleted file mode 100755
index 3ca99fd..0000000
--- a/gcc/config/m68k/plexus.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Definitions of target machine for GNU compiler, for 680X0 based Plexus
-   Computers running SYSVR2
-   Copyright (C) 1990, 1994, 1996 Free Software Foundation, Inc.
-   Contributed by Randy Welch (rwelch@netcom.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* The Plexus port of gcc requires you to use gas ( either 1.3X with COFF 
-   patches or 2.X ),  If you use gas 2.X you have to use binutils-2.X.
-      
-   With using gas-2.X the Plexus gcc port is now capable of generating
-   output suitable for use by gdb-4.X ( send mail to above address for
-   info on getting gdb patches or other GNU items for the Plexus )
-
-   This is configured for label output default by gas as LXXX instead of
-   plexus cc/as combination requires .LXXX  */
-
-#include "m68k/m68k.h"
-
-/* Define __HAVE_68881 in preprocessor only if -m68881 is specified.
-   This will control the use of inline 68881 insns in certain macros. */
-
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68020)
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-#define CPP_SPEC "%{m68881:-D__HAVE_68881__}"
-#define CPP_PREDEFINES "-Dm68 -Dunix -Dplexus -Asystem(unix)  -Acpu(m68k) -Amachine(m68k)"
-
-#if TARGET_DEFAULT & MASK_68020
-#define ASM_SPEC\
-"%{m68000:-mc68000}%{mc68000:-mc68000}%{!mc68000:%{!m68000:-mc68020}}"
-#undef STRICT_ALIGNMENT
-#define STRICT_ALIGNMENT 0
-#else
-#define ASM_SPEC\
-"%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!mc68020:-mc68000}}"
-#endif
-
-/***************************************************************************/
-/*  Un comment the following if you want adb to be able to follow a core   */
-/*  file if you compile a program with -O                                  */
-/***************************************************************************/
-/* #define FRAME_POINTER_REQUIRED */
-
-/* Let's be compatible with the Plexus C compiler by default.  Why not?  */
-#define PLEXUS_CC_COMPAT
-
-#ifdef PLEXUS_CC_COMPAT
-#define STRUCTURE_SIZE_BOUNDARY 16	/* for compatibility with cc */
-#undef STACK_BOUNDARY
-#define STACK_BOUNDARY 32		/* ditto */
-#endif
-
-#undef NEED_PROBE
-#define NEED_PROBE -132			/* plexus needs a stack probe */
-
-/***********************************************************************/
-/* if you have binutils-2.X and gas-2.X running you can generate code  */
-/* that gdb can understand ( gdb support available for 4.11 )          */
-/*                                                                     */
-/* If you use gas-1.3X don't define this as the version of the coff    */
-/* patches for gas-1.3x ( stabs in coff ) does not generate coff debug */
-/* syms                                                                */
-/***********************************************************************/
-#define HAVE_GAS_2_X
-
-#ifdef HAVE_GAS_2_X
-#undef DBX_DEBUGGING_INFO
-#define SDB_DEBUGGING_INFO
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
-  output_file_directive((FILE), main_input_filename)
-
-#else
-#undef DBX_DEBUGGING_INFO		/* no real debugger */
-#undef SDB_DEBUGGING_INFO
-#endif
-#define TARGET_MEM_FUNCTIONS
-
-/***********************************************************************/
-/*                          items for collect2                         */
-/***********************************************************************/
-
-#define NM_FLAGS ""
-#define NO_SYS_SIGLIST
-#define NO_DUP2
-
-#define SIZE_TYPE "int"
diff --git a/gcc/config/m68k/rtems.h b/gcc/config/m68k/rtems.h
deleted file mode 100755
index 20e623e..0000000
--- a/gcc/config/m68k/rtems.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Definitions for rtems targeting a Motorola m68k using coff.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m68k/m68k-coff.h"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmc68000 -Drtems -D__rtems__ \
-   -Asystem(rtems) -Acpu(mc68000) -Acpu(m68k) -Amachine(m68k)"
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#ifndef TARGET_MEM_FUNCTIONS
-#define TARGET_MEM_FUNCTIONS
-#endif
diff --git a/gcc/config/m68k/sgs.h b/gcc/config/m68k/sgs.h
deleted file mode 100755
index 62d2336..0000000
--- a/gcc/config/m68k/sgs.h
+++ /dev/null
@@ -1,446 +0,0 @@
-/* Definitions of target machine for GNU compiler for m68k targets using
-   assemblers derived from AT&T "SGS" releases.
-   Copyright (C) 1991, 1993, 1996 Free Software Foundation, Inc.
-   Written by Fred Fish (fnf@cygnus.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Control assembler-syntax conditionals in m68k.md and conditionals in
-   m68k.h.  Note that some systems may also require SGS_SWAP_W and/or
-   SGS_SWITCH_TABLES to be defined as well.  */
-
-#define MOTOROLA		/* Use Motorola syntax rather than "MIT" */
-#define SGS			/* Uses SGS assembler */
-#define SGS_CMP_ORDER		/* Takes cmp operands in reverse order */
-
-#include "m68k/m68k.h"
-
-/* SGS specific assembler pseudo ops. */
-
-#define	BYTE_ASM_OP		".byte"
-#define WORD_ASM_OP		".short"
-#define LONG_ASM_OP		".long"
-#define SPACE_ASM_OP		".space"
-#define ALIGN_ASM_OP		".align"
-#undef GLOBAL_ASM_OP
-#define GLOBAL_ASM_OP		".global"
-#define SWBEG_ASM_OP		".swbeg"
-#define SET_ASM_OP		".set"
-
-#define UNALIGNED_SHORT_ASM_OP	".short"	/* Used in dwarfout.c */
-#define UNALIGNED_INT_ASM_OP	".long"		/* Used in dwarfout.c */
-
-#define ASM_PN_FORMAT		"%s_%d"		/* Format for private names */
-
-/* Here are four prefixes that are used by asm_fprintf to
-   facilitate customization for alternate assembler syntaxes.
-   Machines with no likelihood of an alternate syntax need not
-   define these and need not use asm_fprintf.  */
-
-/* The prefix for register names.  Note that REGISTER_NAMES
-   is supposed to include this prefix. Also note that this is NOT an
-   fprintf format string, it is a literal string */
-
-#undef REGISTER_PREFIX
-#define REGISTER_PREFIX "%"
-
-/* The prefix for local (compiler generated) labels.
-   These labels will not appear in the symbol table. */
-
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX "."
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-
-/* The prefix for immediate operands.  */
-
-#undef IMMEDIATE_PREFIX
-#define IMMEDIATE_PREFIX "&"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number.
-   Motorola format uses different register names than defined in m68k.h.
-   We also take this chance to convert 'a6' to 'fp' */
-
-#undef REGISTER_NAMES
-
-#ifndef SUPPORT_SUN_FPA
-
-#define REGISTER_NAMES \
-{"%d0",   "%d1",   "%d2",   "%d3",   "%d4",   "%d5",   "%d6",   "%d7",	     \
- "%a0",   "%a1",   "%a2",   "%a3",   "%a4",   "%a5",   "%fp",   "%sp",	     \
- "%fp0",  "%fp1",  "%fp2",  "%fp3",  "%fp4",  "%fp5",  "%fp6",  "%fp7" }
-
-#else /* SUPPORTED_SUN_FPA */
-
-#define REGISTER_NAMES \
-{"%d0",   "%d1",   "%d2",   "%d3",   "%d4",   "%d5",   "%d6",   "%d7",	     \
- "%a0",   "%a1",   "%a2",   "%a3",   "%a4",   "%a5",   "%fp",   "%sp",	     \
- "%fp0",  "%fp1",  "%fp2",  "%fp3",  "%fp4",  "%fp5",  "%fp6",  "%fp7",	     \
- "%fpa0", "%fpa1", "%fpa2", "%fpa3", "%fpa4", "%fpa5", "%fpa6","%fpa7",	     \
- "%fpa8", "%fpa9", "%fpa10","%fpa11","%fpa12","%fpa13","%fpa14","%fpa15",    \
- "%fpa16","%fpa17","%fpa18","%fpa19","%fpa20","%fpa21","%fpa22","%fpa23",    \
- "%fpa24","%fpa25","%fpa26","%fpa27","%fpa28","%fpa29","%fpa30","%fpa31" }
-
-#endif /* defined SUPPORT_SUN_FPA */
-
-/* When using an SGS assembler, modify the name of the artificial label which
-   identifies this file as having been compiled with gcc, and the macro that
-   emits such a label in the assembly output, to use '%' rather than '.' */
-
-#define ASM_IDENTIFY_GCC(FILE)				\
- { fprintf ((FILE), "%s:\n", "gcc2_compiled%"); }
-
-/* This is how to output an assembler line defining an `int' constant.  */
-/* The SGS assembler doesn't understand ".word". */
-
-#undef ASM_OUTPUT_SHORT
-#define ASM_OUTPUT_SHORT(FILE,VALUE)			\
-( fprintf ((FILE), "\t%s ", WORD_ASM_OP),		\
-  output_addr_const ((FILE), (VALUE)),			\
-  fprintf ((FILE), "\n"))
-
-#undef ASM_OUTPUT_LONG_DOUBLE
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE)  			\
-do { long l[3];							\
-     REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l);		\
-     fprintf ((FILE), "\t%s 0x%x,0x%x,0x%x\n", LONG_ASM_OP,	\
-	     l[0], l[1], l[2]);					\
-   } while (0)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)			\
-do { long l[2];						\
-     REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l);		\
-     fprintf ((FILE), "\t%s 0x%x,0x%x\n", LONG_ASM_OP,	\
-	      l[0], l[1]);				\
-   } while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)			\
-do { long l;						\
-     REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-     fprintf ((FILE), "\t%s 0x%x\n", LONG_ASM_OP, l);	\
-   } while (0)
-
-/* This is how to output an assembler line that says to advance the
-   location counter to a multiple of 2**LOG bytes.  */
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)				\
-  if ((LOG) > 0)						\
-    fprintf ((FILE), "\t%s \t%u\n", ALIGN_ASM_OP, 1 << (LOG));	\
-  else if ((LOG) > 31)						\
-    abort ();
-
-/* The routine used to output null terminated string literals.  We cannot
-   use the ".string" pseudo op, because it silently truncates strings to
-   1023 bytes.  There is no "partial string op" which works like ".string"
-   but doesn't append a null byte, so we can't chop the input string up
-   into small pieces and use that.  Our only remaining alternative is to
-   output the string one byte at a time. */
-
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)				\
-do {								\
-  register int sp = 0, lp = 0, ch;				\
-  fprintf ((FILE), "\t%s ", BYTE_ASM_OP);			\
-  do {								\
-    ch = (PTR)[sp];						\
-    if (ch > ' ' && ! (ch & 0x80) && ch != '\\')		\
-      {								\
-	fprintf ((FILE), "'%c", ch);				\
-      }								\
-    else							\
-      {								\
-	fprintf ((FILE), "0x%x", ch);				\
-      }								\
-    if (++sp < (LEN))						\
-      {								\
-	if ((sp % 10) == 0)					\
-	  {							\
-	    fprintf ((FILE), "\n\t%s ", BYTE_ASM_OP);		\
-	  }							\
-	else							\
-	  {							\
-	    putc (',', (FILE));					\
-	  }							\
-      }								\
-  } while (sp < (LEN));						\
-  putc ('\n', (FILE));						\
-} while (0)
-
-
-/* SGS based assemblers don't understand #NO_APP and #APP, so just don't
-   bother emitting them. */
-
-#undef ASM_APP_ON
-#define ASM_APP_ON ""
-
-#undef ASM_APP_OFF
-#define ASM_APP_OFF ""
-
-/* When using SGS derived assemblers, change the "MIT" or "MOTOROLA"
-   to "SGS/AT&T"  */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (68k, SGS/AT&T syntax)");
-
-/* Use proper assembler syntax for these macros.  */
-#undef ASM_OUTPUT_REG_PUSH
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  asm_fprintf (FILE, "\t%Omove.l %s,-(%Rsp)\n", reg_names[REGNO])
-
-#undef ASM_OUTPUT_REG_POP
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  asm_fprintf (FILE, "\t%Omove.l (%Rsp)+,%s\n", reg_names[REGNO])
-
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)	\
-  do { long l;						\
-       REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-       asm_fprintf ((FILE), "%I0x%x", l);		\
-     } while (0)
-  
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)		\
-  do { long l[2];					\
-       REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l);		\
-       asm_fprintf ((FILE), "%I0x%x%08x", l[0], l[1]);	\
-     } while (0)
-
-/* How to output a block of SIZE zero bytes.  Note that the `space' pseudo,
-   when used in the text segment, causes SGS assemblers to output nop insns
-   rather than 0s, so we set ASM_NO_SKIP_IN_TEXT to prevent this. */
-
-#define ASM_NO_SKIP_IN_TEXT 1
-
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t%s %u\n", SPACE_ASM_OP, (SIZE))
-
-/* Translate Motorola opcodes such as `jbeq' into SGS opcodes such
-   as `beq.w'.
-   Delete the `e' in `move...' and `fmove'.
-   Change `ftst' to `ftest'.
-   Change `fbne' to `fbneq'
-   Change `fsne' to `fsneq'
-   Change `divsl' to `tdivs' (32/32 -> 32r:32q)
-   Change `divul' to `tdivu' (32/32 -> 32r:32q)
-   Optionally change swap to swap.w.
-   */
-
-#ifdef SGS_SWAP_W
-#define ASM_OUTPUT_OPCODE(FILE, PTR)			\
-{							\
-  extern int flag_pic;					\
-  if (!strncmp ((PTR), "jbsr", 4))			\
-    { if (flag_pic)					\
-        fprintf ((FILE), "bsr");			\
-      else						\
-        fprintf ((FILE), "jsr");			\
-    (PTR) += 4; }					\
-  else if ((PTR)[0] == 'j' && (PTR)[1] == 'b')		\
-    { ++(PTR);						\
-      while (*(PTR) != ' ')				\
-	{ putc (*(PTR), (FILE)); ++(PTR); }		\
-      fprintf ((FILE), ".w"); }				\
-  else if ((PTR)[0] == 's')				\
-    {							\
-      if (!strncmp ((PTR), "swap", 4))			\
-	{ fprintf ((FILE), "swap.w"); (PTR) += 4; }	\
-    }							\
-/* FMOVE ==> FMOV, (and F%& F%$ translations) */	\
-  else if ((PTR)[0] == 'f')				\
-    {							\
-      if (!strncmp ((PTR), "fmove", 5))			\
-	{ fprintf ((FILE), "fmov"); (PTR) += 5; }	\
-      else if (!strncmp ((PTR), "ftst", 4))		\
-	{ fprintf ((FILE), "ftest"); (PTR) += 4; }	\
-      else if (!strncmp ((PTR), "fbne", 4))		\
-	{ fprintf ((FILE), "fbneq"); (PTR) += 4; }	\
-      else if (!strncmp ((PTR), "fsne", 4))		\
-	{ fprintf ((FILE), "fsneq"); (PTR) += 4; }	\
-      else if (!strncmp ((PTR), "f%$move", 7))		\
-	{ (PTR) += 7;					\
-	  if (TARGET_68040_ONLY)			\
-	    fprintf ((FILE), "fsmov");			\
-	  else fprintf ((FILE), "fmov"); }		\
-      else if (!strncmp ((PTR), "f%&move", 7))		\
-	{ (PTR) += 7;					\
-	  if (TARGET_68040_ONLY)			\
-	    fprintf ((FILE), "fdmov");			\
-	  else fprintf ((FILE), "fmov"); }		\
-    }							\
-/* MOVE, MOVEA, MOVEQ, MOVEC ==> MOV	*/		\
-  else if ((PTR)[0] == 'm' && (PTR)[1] == 'o'		\
-	   && (PTR)[2] == 'v' && (PTR)[3] == 'e')	\
-    { fprintf ((FILE), "mov"); (PTR) += 4;		\
-       if ((PTR)[0] == 'q' || (PTR)[0] == 'a'		\
-	   || (PTR)[0] == 'c') (PTR)++; }		\
-/* SUB, SUBQ, SUBA, SUBI ==> SUB */			\
-  else if ((PTR)[0] == 's' && (PTR)[1] == 'u' 		\
-	   && (PTR)[2] == 'b')				\
-    { fprintf ((FILE), "sub"); (PTR) += 3;		\
-       if ((PTR)[0] == 'q' || (PTR)[0] == 'i'	 	\
-	   || (PTR)[0] == 'a') (PTR)++; }		\
-/* CMP, CMPA, CMPI, CMPM ==> CMP	*/		\
-  else if ((PTR)[0] == 'c' && (PTR)[1] == 'm'		\
-	   && (PTR)[2] == 'p')				\
-    { fprintf ((FILE), "cmp"); (PTR) += 3;		\
-       if ((PTR)[0] == 'a' || (PTR)[0] == 'i'	 	\
-	   || (PTR)[0] == 'm') (PTR)++; }		\
-/* DIVSL ==> TDIVS */					\
-  else if ((PTR)[0] == 'd' && (PTR)[1] == 'i'		\
-	   && (PTR)[2] == 'v' && (PTR)[3] == 's'	\
-	   && (PTR)[4] == 'l')				\
-    { fprintf ((FILE), "tdivs"); (PTR) += 5; }		\
-/* DIVUL ==> TDIVU */					\
-  else if ((PTR)[0] == 'd' && (PTR)[1] == 'i'		\
-	   && (PTR)[2] == 'v' && (PTR)[3] == 'u'	\
-	   && (PTR)[4] == 'l')				\
-    { fprintf ((FILE), "tdivu"); (PTR) += 5; }		\
-}
-
-#else /* not SGS_SWAP_W */
-
-#define ASM_OUTPUT_OPCODE(FILE, PTR)			\
-{							\
-  extern int flag_pic;					\
-  if (!strncmp ((PTR), "jbsr", 4))			\
-    { if (flag_pic)					\
-        fprintf ((FILE), "bsr");			\
-      else						\
-        fprintf ((FILE), "jsr");			\
-    (PTR) += 4; }					\
-  else if ((PTR)[0] == 'j' && (PTR)[1] == 'b')		\
-    { ++(PTR);						\
-      while (*(PTR) != ' ')				\
-	{ putc (*(PTR), (FILE)); ++(PTR); }		\
-      fprintf ((FILE), ".w"); }				\
-/* FMOVE ==> FMOV, (and F%& F%$ translations) */	\
-  else if ((PTR)[0] == 'f')				\
-    {							\
-      if (!strncmp ((PTR), "fmove", 5))			\
-	{ fprintf ((FILE), "fmov"); (PTR) += 5; }	\
-      else if (!strncmp ((PTR), "ftst", 4))		\
-	{ fprintf ((FILE), "ftest"); (PTR) += 4; }	\
-      else if (!strncmp ((PTR), "fbne", 4))		\
-	{ fprintf ((FILE), "fbneq"); (PTR) += 4; }	\
-      else if (!strncmp ((PTR), "fsne", 4))		\
-	{ fprintf ((FILE), "fsneq"); (PTR) += 4; }	\
-      else if (!strncmp ((PTR), "f%$move", 7))		\
-	{ (PTR) += 7;					\
-	  if (TARGET_68040_ONLY)			\
-	    fprintf ((FILE), "fsmov");			\
-	  else fprintf ((FILE), "fmov"); }		\
-      else if (!strncmp ((PTR), "f%&move", 7))		\
-	{ (PTR) += 7;					\
-	  if (TARGET_68040_ONLY)			\
-	    fprintf ((FILE), "fdmov");			\
-	  else fprintf ((FILE), "fmov"); }		\
-    }							\
-/* MOVE, MOVEA, MOVEQ, MOVEC ==> MOV	*/		\
-  else if ((PTR)[0] == 'm' && (PTR)[1] == 'o'		\
-	   && (PTR)[2] == 'v' && (PTR)[3] == 'e')	\
-    { fprintf ((FILE), "mov"); (PTR) += 4;		\
-       if ((PTR)[0] == 'q' || (PTR)[0] == 'a'		\
-	   || (PTR)[0] == 'c') (PTR)++; }		\
-/* SUB, SUBQ, SUBA, SUBI ==> SUB */			\
-  else if ((PTR)[0] == 's' && (PTR)[1] == 'u' 		\
-	   && (PTR)[2] == 'b')				\
-    { fprintf ((FILE), "sub"); (PTR) += 3;		\
-       if ((PTR)[0] == 'q' || (PTR)[0] == 'i'	 	\
-	   || (PTR)[0] == 'a') (PTR)++; }		\
-/* CMP, CMPA, CMPI, CMPM ==> CMP	*/		\
-  else if ((PTR)[0] == 'c' && (PTR)[1] == 'm'		\
-	   && (PTR)[2] == 'p')				\
-    { fprintf ((FILE), "cmp"); (PTR) += 3;		\
-       if ((PTR)[0] == 'a' || (PTR)[0] == 'i'	 	\
-	   || (PTR)[0] == 'm') (PTR)++; }		\
-/* DIVSL ==> TDIVS */					\
-  else if ((PTR)[0] == 'd' && (PTR)[1] == 'i'		\
-	   && (PTR)[2] == 'v' && (PTR)[3] == 's'	\
-	   && (PTR)[4] == 'l')				\
-    { fprintf ((FILE), "tdivs"); (PTR) += 5; }		\
-/* DIVUL ==> TDIVU */					\
-  else if ((PTR)[0] == 'd' && (PTR)[1] == 'i'		\
-	   && (PTR)[2] == 'v' && (PTR)[3] == 'u'	\
-	   && (PTR)[4] == 'l')				\
-    { fprintf ((FILE), "tdivu"); (PTR) += 5; }		\
-}
-
-#endif /* not SGS_SWAP_W */
-
-/* This macro outputs the label at the start of a switch table.  The
-   ".swbeg <N>" is an assembler directive that causes the switch table
-   size to be inserted into the object code so that disassemblers, for
-   example, can identify that it is the start of a switch table. */
-
-#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE)		\
-  fprintf ((FILE), "\t%s &%d\n", SWBEG_ASM_OP, XVECLEN (PATTERN (TABLE), 1));
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE)			\
-  do {									\
-    ASM_OUTPUT_BEFORE_CASE_LABEL((FILE),(PREFIX),(NUM),(TABLE));	\
-    ASM_OUTPUT_INTERNAL_LABEL((FILE),(PREFIX),(NUM));			\
-  } while (0)
-
-/* At end of a switch table, define LDnnn iff the symbol LInnn was defined.
-   Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
-   fails to assemble.  Luckily "LDnnn(pc,d0.l*2)" produces the results
-   we want.  This difference can be accommodated by making the assembler
-   define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
-   string, as necessary.  This is accomplished via the ASM_OUTPUT_CASE_END
-   macro. */
-
-#undef ASM_OUTPUT_CASE_END
-#define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE)		\
-{ if (switch_table_difference_label_flag)		\
-    asm_fprintf (FILE, "\t%s %LLD%d,%LL%d-%LLI%d-2.b\n",\
-		 SET_ASM_OP, (NUM), (NUM), (NUM));	\
-  switch_table_difference_label_flag = 0; }
-
-extern int switch_table_difference_label_flag;
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)	\
-  asm_fprintf (FILE, "\t%s %LL%d-%LL%d\n", WORD_ASM_OP, VALUE, REL)
-
-/* Currently, JUMP_TABLES_IN_TEXT_SECTION must be defined in order to
-   keep switch tables in the text section. */
-   
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#undef ASM_FORMAT_PRIVATE_NAME
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), ASM_PN_FORMAT, (NAME), (LABELNO)))
-
diff --git a/gcc/config/m68k/st2000.h b/gcc/config/m68k/st2000.h
deleted file mode 100755
index 3aea439..0000000
--- a/gcc/config/m68k/st2000.h
+++ /dev/null
@@ -1,610 +0,0 @@
-/* Definitions of target machine for GNU compiler.  
-   Tandem ST-2000 version
-   Copyright 1992 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-/*
- Contributed by Steve Chamberlain
- 		sac@cygnus.com
- */
-
-
-
-/* This controls conditionals in m68k.h.  */
-#define MOTOROLA		/* Use Motorola syntax rather than "MIT" */
-#define SGS_NO_LI		/* Suppress jump table label usage */
-
-#include "aoutos.h"
-#undef ASM_OUTPUT_LABELREF
-#include "m68k/m68k.h"
-
-
-#undef TARGET_SWITCHES 
-#undef USER_LABEL_PREFIX 
-#undef ASM_OUTPUT_LABEL 
-#undef ASM_GLOBALIZE_LABEL 
-#undef ASM_OUTPUT_INTERNAL_LABEL 
-#undef ASM_OUTPUT_DOUBLE 
-#undef ASM_OUTPUT_FLOAT 
-#undef ASM_OUTPUT_INT 
-#undef ASM_OUTPUT_SHORT 
-#undef ASM_OUTPUT_CHAR 
-#undef ASM_OUTPUT_BYTE 
-#undef ASM_OUTPUT_REG_PUSH 
-#undef ASM_OUTPUT_REG_POP 
-#undef ASM_OUTPUT_ADDR_VEC_ELT 
-#undef ASM_OUTPUT_ADDR_DIFF_ELT 
-#undef ASM_OUTPUT_ALIGN 
-#undef ASM_OUTPUT_SKIP 
-#undef ASM_OUTPUT_COMMON 
-#undef ASM_OUTPUT_LOCAL 
-#undef ASM_FORMAT_PRIVATE_NAME 
-#undef TEXT_SECTION_ASM_OP 
-#undef DATA_SECTION_ASM_OP 
-#undef ASM_FILE_START 
-#undef FUNCTION_PROLOGUE
-#undef FUNCTION_EPILOGUE
-#undef ASM_OUTPUT_LABELREF
-#undef REGISTER_NAMES
-#undef PRINT_OPERAND
-#undef PRINT_OPERAND_ADDRESS
-#undef ASM_OUTPUT_ALIGN
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-
-#define TARGET_SWITCHES  \
-  { { "68020", 5},				\
-    { "c68020", 5},				\
-    { "68881", 2},				\
-    { "bitfield", 4},				\
-    { "68000", -5},				\
-    { "c68000", -5},				\
-    { "soft-float", -0102},			\
-    { "nobitfield", -4},			\
-    { "rtd", 8},				\
-    { "nortd", -8},				\
-    { "short", 040},				\
-    { "noshort", -040},				\
-    { "fpa", 0100},				\
-    { "nofpa", -0100},				\
-    { "sky", 0200},				\
-    { "nosky", -0200},				\
-    { "68040", 0407},				\
-    { "68030", -01400},				\
-    { "68030", 7},				\
-    { "68040-only", 01000},			\
-    { "no-prefix",  02000},                     \
-    { "", TARGET_DEFAULT}}
-
-#define TARGET_DEFAULT 7
-
-#define USER_LABEL_PREFIX (target_flags & 02000) ? "" : "_"
-
-/* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified.
-   This will control the use of inline 68881 insns in certain macros.  */
-
-#define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-/* These are the ones defined by Sony, plus mc68000 for uniformity with
-   GCC on other 68000 systems.  */
-
-#define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews700"
-
-/* These conditionals tested for different submodels,
-   but they were incorrect since they tested the host rather than the target.
-   The choice of model shouldn't actually matter.  */
-
-
-/* Link with libg.a when debugging, for dbx's sake.  */
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Override parts of m68k.h to fit Sony's assembler syntax.  */
-
-#undef BIGGEST_ALIGNMENT
-#undef CALL_USED_REGISTERS
-#undef FUNCTION_VALUE
-#undef LIBCALL_VALUE
-#undef FUNCTION_PROFILER
-
-
-#undef ASM_OUTPUT_ALIGN
-
-/* There is no point aligning anything to a rounder boundary than this.  */
-#define BIGGEST_ALIGNMENT 32
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-  
-/* NEWS makes d2, d3, fp2 and fp3 unsaved registers, unlike the Sun system.  */
-  
-#define CALL_USED_REGISTERS \
- {1, 1, 1, 1, 0, 0, 0, 0, \
-  1, 1, 0, 0, 0, 0, 0, 1, \
-  1, 1, 1, 1, 0, 0, 0, 0}
-
-/* NEWS returns floats and doubles in fp0, not d0/d1.  */
-
-#define FUNCTION_VALUE(VALTYPE,FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
-
-#define LIBCALL_VALUE(MODE) \
- gen_rtx (REG, (MODE), ((TARGET_68881 && ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0))
-
-
-
-
-/* Don't try to define `gcc_compiled.' since the assembler does not
-   accept symbols with periods.  This is no real loss since GDB only
-   really needs it for parms passed in registers.  */
-#define ASM_IDENTIFY_GCC(FILE)
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)     \
-{ register int regno;						\
-  register int mask = 0;					\
-  extern char call_used_regs[];					\
-  int fsize = ((SIZE) + 3) & -4;				\
-  if (frame_pointer_needed)					\
-    { if (fsize < 0x8000)			                \
-        fprintf (FILE, "\tlink fp,#%d\n", -fsize);		\
-      else if (TARGET_68020)                                    \
-        fprintf (FILE, "\tlink.l fp,#%d\n", -fsize);            \
-      else							\
-	fprintf (FILE, "\tlink fp,#0\n\tsub.l #%d,sp\n", fsize); }  \
-  for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++)	\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-       mask |= 1 << (regno - 16);				\
-  if (mask != 0)						\
-    fprintf (FILE, "\tfmovem.x #0x%x,-(sp)\n", mask & 0xff);    \
-  mask = 0;							\
-  for (regno = 0; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-       mask |= 1 << (15 - regno);				\
-  if (frame_pointer_needed)					\
-    mask &= ~ (1 << (15-FRAME_POINTER_REGNUM));			\
-  if (exact_log2 (mask) >= 0)					\
-    fprintf (FILE, "\tmove.l %s,-(sp)\n", reg_names[15 - exact_log2 (mask)]);  \
-  else if (mask) fprintf (FILE, "\tmovem.l #0x%x,-(sp)\n", mask); }
-
-#define FUNCTION_PROFILER(FILE, LABEL_NO) \
-   fprintf (FILE, "\tmove.l #LP%d,d0\n\tjsr mcount\n", (LABEL_NO));
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-{ register int regno;						\
-  register int mask, fmask;					\
-  register int nregs;						\
-  int offset, foffset;						\
-  extern char call_used_regs[];					\
-  int fsize = ((SIZE) + 3) & -4;				\
-  int big = 0;							\
-  nregs = 0;  fmask = 0;					\
-  for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++)	\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      { nregs++; fmask |= 1 << (23 - regno); }			\
-  foffset = nregs * 12;						\
-  nregs = 0;  mask = 0;						\
-  if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \
-  for (regno = 0; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      { nregs++; mask |= 1 << regno; }				\
-  offset = foffset + nregs * 4;					\
-  if (offset + fsize >= 0x8000 					\
-      && frame_pointer_needed					\
-      && (mask || fmask))					\
-    { fprintf (FILE, "\tmove.l #%d,a0\n", -fsize);		\
-      fsize = 0, big = 1; }					\
-  if (exact_log2 (mask) >= 0) {					\
-    if (big)							\
-      fprintf (FILE, "\tmove.l (-%d,fp,a0.l),%s\n",		\
-	       offset + fsize, reg_names[exact_log2 (mask)]);	\
-    else if (! frame_pointer_needed)				\
-      fprintf (FILE, "\tmove.l (sp)+,%s\n",			\
-	       reg_names[exact_log2 (mask)]);			\
-    else							\
-      fprintf (FILE, "\tmove.l (-%d,fp),%s\n",			\
-	       offset + fsize, reg_names[exact_log2 (mask)]); }	\
-  else if (mask) {						\
-    if (big)							\
-      fprintf (FILE, "\tmovem.l (-%d,fp,a0.l),#0x%x\n",		\
-	       offset + fsize, mask);				\
-    else if (! frame_pointer_needed)				\
-      fprintf (FILE, "\tmovem.l (sp)+,#0x%x\n", mask);		\
-    else							\
-      fprintf (FILE, "\tmovem.l (-%d,fp),#0x%x\n",		\
-	       offset + fsize, mask); }				\
-  if (fmask) {							\
-    if (big)							\
-      fprintf (FILE, "\tfmovem.x (-%d,fp,a0.l),#0x%x\n",	\
-	       foffset + fsize, fmask);				\
-    else if (! frame_pointer_needed)				\
-      fprintf (FILE, "\tfmovem.x (sp)+,#0x%x\n", fmask);	\
-    else							\
-      fprintf (FILE, "\tfmovem.x (-%d,fp),#0x%x\n",		\
-	       foffset + fsize, fmask); }			\
-  if (frame_pointer_needed)					\
-    fprintf (FILE, "\tunlk fp\n");				\
-  if (current_function_pops_args)				\
-    fprintf (FILE, "\trtd #%d\n", current_function_pops_args);	\
-  else fprintf (FILE, "\trts\n"); }
-
-/* Difference from m68k.h is in `fp' instead of `a6'.  */
-
-#define REGISTER_NAMES \
-{"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",	\
- "a0", "a1", "a2", "a3", "a4", "a5", "fp", "sp",	\
- "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7"}
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tmove.l\t%s,-(sp)\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tmove.l\t(sp)+,%s\n", reg_names[REGNO])
-  
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ if (CODE == '.') fprintf (FILE, ".");					\
-  else if (CODE == '#') fprintf (FILE, "#");				\
-  else if (CODE == '-') fprintf (FILE, "-(sp)");			\
-  else if (CODE == '+') fprintf (FILE, "(sp)+");			\
-  else if (CODE == '@') fprintf (FILE, "(sp)");				\
-  else if (CODE == '!') fprintf (FILE, "ccr");				\
-  else if (CODE == '$') {if (TARGET_68040_ONLY) fprintf (FILE, "s");}	\
-  else if (CODE == '&') {if (TARGET_68040_ONLY) fprintf (FILE, "d");}	\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode)	\
-    { union { double d; int i[2]; } u;					\
-      union { float f; int i; } u1;					\
-      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
-      u1.f = u.d;							\
-      if (CODE == 'f')							\
-        fprintf (FILE, "#0f%.9e", u1.f);				\
-      else								\
-        fprintf (FILE, "#0x%x", u1.i); }				\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != DImode)	\
-    { union { double d; int i[2]; } u;					\
-      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
-      fprintf (FILE, "#0d%.20e", u.d); }				\
-  else if (CODE == 'b') { putc('#', FILE); output_addr_const (FILE, X);}\
-  else { putc ('#', FILE); output_addr_const (FILE, X); }}
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx reg1, reg2, breg, ireg;					\
-  register rtx addr = ADDR;						\
-  rtx offset;								\
-  switch (GET_CODE (addr))						\
-    {									\
-    case REG:								\
-      fprintf (FILE, "(%s)", reg_names[REGNO (addr)]);			\
-      break;								\
-    case PRE_DEC:							\
-      fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case POST_INC:							\
-      fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case PLUS:								\
-      reg1 = 0;	reg2 = 0;						\
-      ireg = 0;	breg = 0;						\
-      offset = 0;							\
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))				\
-	{								\
-	  offset = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))			\
-	{								\
-	  offset = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) != PLUS) ;					\
-      else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT		\
-	  || GET_CODE (addr) == SIGN_EXTEND)				\
-	{ if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; }	\
-      if (offset != 0) { if (addr != 0) abort (); addr = offset; }	\
-      if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND			\
-		    || GET_CODE (reg1) == MULT))			\
-	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))		\
-	{ breg = reg2; ireg = reg1; }					\
-      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))		\
-	{ breg = reg1; ireg = reg2; }					\
-      if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { int scale = 1;						\
-	  if (GET_CODE (ireg) == MULT)					\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (GET_CODE (ireg) == SIGN_EXTEND)				\
-	    fprintf (FILE, "(L%d.b,pc,%s.w",				\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (XEXP (ireg, 0))]); 		\
-	  else								\
-	    fprintf (FILE, "(L%d.b,pc,%s.l",				\
-		     CODE_LABEL_NUMBER (XEXP (addr, 0)),		\
-		     reg_names[REGNO (ireg)]);				\
-	  if (scale != 1) fprintf (FILE, "*%d", scale);			\
-	  putc (')', FILE);						\
-	  break; }							\
-      if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { fprintf (FILE, "(L%d.b,pc,%s.l",				\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   reg_names[REGNO (breg)]);				\
-	  putc (')', FILE);						\
-	  break; }							\
-      if (ireg != 0 || breg != 0)					\
-	{ int scale = 1;						\
-	  if (breg == 0)						\
-	    abort ();							\
-	  if (addr && GET_CODE (addr) == LABEL_REF) abort ();		\
-	  fprintf (FILE, "(");						\
-	  if (addr != 0) {						\
-	    output_addr_const (FILE, addr);				\
-	    putc (',', FILE); }						\
-	  fprintf (FILE, "%s", reg_names[REGNO (breg)]);		\
-	  if (ireg != 0)						\
-	    putc (',', FILE);						\
-	  if (ireg != 0 && GET_CODE (ireg) == MULT)			\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)		\
-	    fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);	\
-	  else if (ireg != 0)						\
-	    fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]);		\
-	  if (scale != 1) fprintf (FILE, "*%d", scale);			\
-	  putc (')', FILE);						\
-	  break;							\
-	}								\
-      else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF)		\
-	{ fprintf (FILE, "(L%d.b,pc,%s.l)",				\
-		   CODE_LABEL_NUMBER (XEXP (addr, 0)),			\
-		   reg_names[REGNO (reg1)]);				\
-	  break; }							\
-    default:								\
-      if (GET_CODE (addr) == CONST_INT					\
-	  && INTVAL (addr) < 0x8000					\
-	  && INTVAL (addr) >= -0x8000)					\
-	fprintf (FILE, "%d.w", INTVAL (addr));				\
-      else								\
-        output_addr_const (FILE, addr);					\
-    }}
-
-
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs ("\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs ("\tXDEF\t", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-
-#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
-  asm_fprintf (FILE, "%U%s", NAME)
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  asm_fprintf (FILE, "%s%d\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-  fprintf (FILE, "\tDC.D\t0r%.20g\n", (VALUE))
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-  fprintf (FILE, "\tDC.S\t0r%.20g\n", (VALUE))
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\tDC.L\t"),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\tDC.W\t"),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\tDC.B\t"),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\tDC.B\t0x%x\n", (VALUE))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-
-/* This is how to output an element of a case-vector that is absolute.
-   (The 68000 does not use such vectors,
-   but we must define this macro anyway.)  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  asm_fprintf (FILE, "\tDC.L\t%LL%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  asm_fprintf (FILE, "\tDC.W\t%LL%d-%LL%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-    fprintf (FILE, "\tALIGN\t%d\n", 1<<LOG);	
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\tDS.B\t%u\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\tXCOM\t", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-/* There doesn't seem to be a way to say this in MRI way */
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-(  data_section(), assemble_name ((FILE), (NAME)), fputs ("\n\tDS.B ", (FILE)),	\
-    fprintf ((FILE), "%u\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s__%d", (NAME), (LABELNO)))
-
-#define TEXT_SECTION_ASM_OP "\tSECT\t.text"
-#define DATA_SECTION_ASM_OP "\tSECT\t.data"
-#define BSS_SECTION_ASM_OP "\tSECT\t.bss"
-
-#define MAX_TEXT_ALIGN 32
-
-#define ASM_FILE_START(FILE) \
- fprintf (FILE, "* TANDEM ST-2000 M68K GCC\n"); \
- fprintf (FILE, "*    Cygnus Support (415) 322-3811\n"); \
- fprintf (FILE, "*    bugs@cygnus.com\n\n");
-
-
-#define SECTION_ASM_OP "\tSECT\t"
-
-#define EXTRA_SECTIONS in_user
-
-#undef SELECT_SECTION
-
-#define SELECT_SECTION(DECL,RELOC)	\
-do {									\
-  if (TREE_CODE (DECL) == VAR_DECL || TREE_CODE (DECL) == FUNCTION_DECL)\
-    {									\
-      if (GET_CODE (DECL_RTL (DECL)) == MEM				\
-	  && GET_CODE (XEXP (DECL_RTL (DECL), 0)) == SYMBOL_REF		\
-	  && SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)))		\
-	{								\
-	  rtx sym = XEXP (DECL_RTL (DECL), 0);				\
-	  int len = (char *) index (XEXP (sym, 0), ' ') - XSTR (sym, 0); \
-	  char *section_name = (char *)alloca (len+1);			\
-	  strncpy (section_name, XEXP (sym, 0), len);			\
-	  section_name[len] = '\0';					\
-	  in_section = in_user;						\
-	  fprintf (asm_out_file, "\tSECT\t%s\n", section_name);	\
-	  break;							\
-	}								\
-    }									\
-  if (TREE_CODE (DECL) == VAR_DECL)					\
-    {									\
-      if (TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL)		\
-	  && DECL_ALIGN (DECL) <= MAX_TEXT_ALIGN			\
-	  && ! (flag_pic && RELOC))					\
-	text_section ();						\
-      else								\
-	data_section ();						\
-    }									\
-  else if (TREE_CODE (DECL) == CONSTRUCTOR)				\
-    {									\
-      if (flag_pic != 0 && RELOC != 0)					\
-	data_section ();						\
-      else								\
-	text_section ();						\
-    }									\
-  else if (*tree_code_type[(int) TREE_CODE (DECL)] == 'c')		\
-    {									\
-      if ((TREE_CODE (DECL) == STRING_CST && flag_writable_strings)	\
-	  || TYPE_ALIGN (TREE_TYPE (DECL)) > MAX_TEXT_ALIGN)		\
-	data_section ();						\
-      else								\
-	text_section ();						\
-    } \
-  else text_section() ;\
-} while (0)
diff --git a/gcc/config/m68k/sun2.h b/gcc/config/m68k/sun2.h
deleted file mode 100755
index 679e57a..0000000
--- a/gcc/config/m68k/sun2.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Sun 68010 version.
-   Copyright (C) 1987, 1988, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "m68k/m68k.h"
-
-/* See m68k.h.  0 means 68000 with no 68881.  */
-
-#define TARGET_DEFAULT 0
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Define __HAVE_68881 in preprocessor only if -m68881 is specified.
-   This will control the use of inline 68881 insns in certain macros.
-   Also inform the program which CPU this is for.  */
-
-#define CPP_SPEC "%{m68881:-D__HAVE_68881__} \
-%{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}"
-
-/* -m68020 requires special flags to the assembler.  */
-
-#define ASM_SPEC \
- "%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!m68020:-mc68010}} \
-  %{fpic:-k} %{fPIC:-k} %{R} %{j} %{J} %{h} %{d2} %{keep-local-as-symbols:-L}"
-  
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dmc68000 -Dsun -Dunix -Asystem(unix)  -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-
-/* Prevent error on `-sun2' and `-target sun2' options.  */
-
-#define CC1_SPEC "%{sun2:} %{target:}"
-
-/* These compiler options take an argument.  We ignore -target for now.  */
-
-#define WORD_SWITCH_TAKES_ARG(STR)				\
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR)				\
-  || !strcmp (STR, "target") || !strcmp (STR, "assert"))
-
-/* Specify what to link with.  */
-
-/* Link with libg.a when debugging, for dbx's sake.  */
-/* Include the support for -a when appropriate.  */
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \
-%{a:/usr/lib/bb_link.o -lc} "
-
-/* Alignment of field after `int : 0' in a structure.  */
-
-#undef EMPTY_FIELD_BOUNDARY
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
diff --git a/gcc/config/m68k/sun2o4.h b/gcc/config/m68k/sun2o4.h
deleted file mode 100755
index da722cf..0000000
--- a/gcc/config/m68k/sun2o4.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Sun 2 running SunOS 4.
-   Copyright (C) 1987, 1988, 1993, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m68k/sun2.h"
-
-
-/* Define __HAVE_SKY__ in preprocessor, according to the -m flags.
-   Also inform the program which CPU this is for.  */
-
-#undef CPP_SPEC
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-#undef SIZE_TYPE
-#define SIZE_TYPE "int"
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
-
-#if TARGET_DEFAULT & MASK_SKY
-
-/* -msky is the default */
-#define CPP_SPEC \
-"%{!msoft-float:-D__HAVE_SKY__}\
-%{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}"
-
-#else
-
-/* -msoft-float is the default */
-#define CPP_SPEC \
-"%{msky:-D__HAVE_SKY__ }\
-%{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}"
-
-#endif
-
-/* STARTFILE_SPEC to include sun floating point initialization
-   This is necessary (tr: Sun does it) for the sky routines.
-   I'm not sure what would happen below if people gave contradictory
-   arguments (eg. -msoft-float -mfpa) */
-
-#undef STARTFILE_SPEC
-
-#if TARGET_DEFAULT & MASK_SKY
-/* -msky is the default */
-#define STARTFILE_SPEC					\
-  "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}	\
-   %{msoft-float:Fcrt1.o%s}				\
-   %{!msoft-float:Scrt1.o%s}"
-#else
-/* -msoft-float is the default */
-#define STARTFILE_SPEC					\
-  "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}	\
-   %{msky:Scrt1.o%s}					\
-   %{!msky:Fcrt1.o%s}"
-#endif
-
-/* Specify library to handle `-a' basic block profiling.
-   Control choice of libm.a (if user says -lm)
-   based on fp arith default and options.  */
-
-#undef LIB_SPEC
-
-#if TARGET_DEFAULT & MASK_SKY
-/* -msky is the default */
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \
-%{a:/usr/lib/bb_link.o -lc} %{g:-lg} \
-%{msoft-float:-L/usr/lib/fsoft} \
-%{!msoft_float:-L/usr/lib/fsky}"
-#else
-/* -msoft-float is the default */
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \
-%{a:/usr/lib/bb_link.o -lc} %{g:-lg} \
-%{!msky:-L/usr/lib/fsoft} \
-%{msky:-L/usr/lib/ffpa}"
-#endif
-
-#undef LINK_SPEC
-#define LINK_SPEC \
-  "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic}"
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
-  do { if (REAL_VALUE_ISINF (VALUE))					\
-        {								\
-          if (REAL_VALUE_NEGATIVE (VALUE))				\
-            fprintf (FILE, "\t.double 0r-99e999\n");			\
-          else								\
-            fprintf (FILE, "\t.double 0r99e999\n");			\
-        }								\
-      else if (REAL_VALUE_MINUS_ZERO (VALUE))				\
-        {								\
-          fprintf (FILE, "\t.long 0x80000000,0\n");			\
-        }								\
-      else								\
-        { char dstr[30];						\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);		\
-          fprintf (FILE, "\t.double 0r%s\n", dstr);			\
-        }								\
-    } while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
- do { if (REAL_VALUE_ISINF (VALUE))					\
-        {								\
-          if (REAL_VALUE_NEGATIVE (VALUE))				\
-            fprintf (FILE, "\t.single 0r-99e999\n");			\
-          else								\
-            fprintf (FILE, "\t.single 0r99e999\n");			\
-        }								\
-      else if (REAL_VALUE_MINUS_ZERO (VALUE))				\
-        {								\
-          fprintf (FILE, "\t.long 0x80000000\n");			\
-        }								\
-      else								\
-        { char dstr[30];						\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);		\
-          fprintf (FILE, "\t.single 0r%s\n", dstr);			\
-        }								\
-    } while (0)
-
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)		\
- do { 								\
-      if (CODE != 'f')						\
-        {							\
-          long l;						\
-          REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-          if (sizeof (int) == sizeof (long))			\
-            asm_fprintf ((FILE), "%I0x%x", l);			\
-          else							\
-            asm_fprintf ((FILE), "%I0x%lx", l);			\
-        }							\
-      else if (REAL_VALUE_ISINF (VALUE))			\
-        {							\
-          if (REAL_VALUE_NEGATIVE (VALUE))			\
-            fprintf (FILE, "#0r-99e999");			\
-          else							\
-            fprintf (FILE, "#0r99e999");			\
-        }							\
-      else if (REAL_VALUE_MINUS_ZERO (VALUE))			\
-        {							\
-          fprintf (FILE, "#0r-0.0");				\
-        }							\
-      else							\
-        { char dstr[30];					\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.9g", dstr);	\
-          fprintf (FILE, "#0r%s", dstr);			\
-        }							\
-    } while (0)
-
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)				\
- do { if (REAL_VALUE_ISINF (VALUE))					\
-        {								\
-          if (REAL_VALUE_NEGATIVE (VALUE))				\
-            fprintf (FILE, "#0r-99e999");				\
-          else								\
-            fprintf (FILE, "#0r99e999");				\
-        }								\
-      else if (REAL_VALUE_MINUS_ZERO (VALUE))				\
-        {								\
-          fprintf (FILE, "#0r-0.0");					\
-        }								\
-      else								\
-        { char dstr[30];						\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.20g", dstr);		\
-          fprintf (FILE, "#0r%s", dstr);				\
-        }								\
-    } while (0)
diff --git a/gcc/config/m68k/sun3.h b/gcc/config/m68k/sun3.h
deleted file mode 100755
index 13e927e..0000000
--- a/gcc/config/m68k/sun3.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Sun 68000/68020 version.
-   Copyright (C) 1987, 1988, 1993, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This comment is here to see if it will keep Sun's cpp from dying.  */
-
-/* If you do not need to generate floating point code for the optional
-   Sun FPA board, you can safely comment out the SUPPORT_SUN_FPA define
-   to gain a little speed and code size.  */
-
-#define SUPPORT_SUN_FPA
-
-#include "m68k/m68k.h"
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
-#endif
-
-/* Define __HAVE_FPA__ or __HAVE_68881__ in preprocessor,
-   according to the -m flags.
-   This will control the use of inline 68881 insns in certain macros.
-   Also inform the program which CPU this is for.  */
-
-#if TARGET_DEFAULT & MASK_68881
-
-/* -m68881 is the default */
-#define CPP_SPEC \
-"%{!msoft-float:%{mfpa:-D__HAVE_FPA__ }%{!mfpa:-D__HAVE_68881__ }}\
-%{m68000:-D__mc68010__}%{mc68000:-D__mc68010__}%{!mc68000:%{!m68000:-D__mc68020__}} \
-%{!ansi:%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}}"
-
-#else
-
-/* -msoft-float is the default */
-#define CPP_SPEC \
-"%{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }\
-%{m68000:-D__mc68010__}%{mc68000:-D__mc68010__}%{!mc68000:%{!m68000:-D__mc68020__}} \
-%{!ansi:%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}}"
-
-#endif
-
-/* Prevent error on `-sun3' and `-target sun3' options.  */
-
-#define CC1_SPEC "%{sun3:} %{target:}"
-
-#define PTRDIFF_TYPE "int"
-
-/* We must override m68k.h.  */
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE "short unsigned int"
-#define WCHAR_TYPE_SIZE 16
-
-/* These compiler options take an argument.  We ignore -target for now.  */
-
-#define WORD_SWITCH_TAKES_ARG(STR)				\
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR)				\
-  || !strcmp (STR, "target") || !strcmp (STR, "assert"))
-
-/* -m68000 requires special flags to the assembler.  */
-
-#define ASM_SPEC \
- "%{m68000:-mc68010}%{mc68000:-mc68010}%{!mc68000:%{!m68000:-mc68020}} \
-  %{fpic:-k} %{fPIC:-k} %{R} %{j} %{J} %{h} %{d2} %{keep-local-as-symbols:-L}"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-/* For a while,  -D_CROSS_TARGET_ARCH=SUN3 was included here,
-   but it doesn't work, partly because SUN3 etc. aren't defined
-   (and shouldn't be).  It seems that on a native compiler _CROSS_TARGET_ARCH
-   should not be defined.  For cross compilers, let's do things as we
-   normally do in GCC.  -- rms.  */
-
-#define CPP_PREDEFINES "-Dmc68000 -Dsun -Dunix -Asystem(unix)  -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)"
-
-/* STARTFILE_SPEC to include sun floating point initialization
-   This is necessary (tr: Sun does it) for both the m68881 and the fpa
-   routines.
-   Note that includes knowledge of the default specs for gcc, ie. no
-   args translates to the same effect as -m68881
-   I'm not sure what would happen below if people gave contradictory
-   arguments (eg. -msoft-float -mfpa) */
-
-#if TARGET_DEFAULT & MASK_FPA
-/* -mfpa is the default */
-#define STARTFILE_SPEC					\
-  "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}	\
-   %{m68881:Mcrt1.o%s}					\
-   %{msoft-float:Fcrt1.o%s}				\
-   %{!m68881:%{!msoft-float:Wcrt1.o%s}}"
-#else
-#if TARGET_DEFAULT & MASK_68881
-/* -m68881 is the default */
-#define STARTFILE_SPEC					\
-  "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}	\
-   %{mfpa:Wcrt1.o%s}					\
-   %{msoft-float:Fcrt1.o%s}				\
-   %{!mfpa:%{!msoft-float:Mcrt1.o%s}}"
-#else
-/* -msoft-float is the default */
-#define STARTFILE_SPEC					\
-  "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}	\
-   %{m68881:Mcrt1.o%s}					\
-   %{mfpa:Wcrt1.o%s}					\
-   %{!m68881:%{!mfpa:Fcrt1.o%s}}"
-#endif
-#endif
-
-/* Specify library to handle `-a' basic block profiling.
-   Control choice of libm.a (if user says -lm)
-   based on fp arith default and options.  */
-
-#if TARGET_DEFAULT & MASK_FPA
-/* -mfpa is the default */
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \
-%{g:-lg} \
-%{msoft-float:-L/usr/lib/fsoft}%{m68881:-L/usr/lib/f68881}\
-%{!msoft_float:%{!m68881:-L/usr/lib/ffpa}}"
-#else
-#if TARGET_DEFAULT & MASK_68881
-/* -m68881 is the default */
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \
-%{g:-lg} \
-%{msoft-float:-L/usr/lib/fsoft}%{!msoft-float:%{!mfpa:-L/usr/lib/f68881}}\
-%{mfpa:-L/usr/lib/ffpa}"
-#else
-/* -msoft-float is the default */
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \
-%{g:-lg} \
-%{!m68881:%{!mfpa:-L/usr/lib/fsoft}}%{m68881:-L/usr/lib/f68881}\
-%{mfpa:-L/usr/lib/ffpa}"
-#endif
-#endif
-
-/* Provide required defaults for linker -e and -d switches.  */
-
-#define LINK_SPEC \
- "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}"
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Allow folding division by zero.  */
-#define REAL_INFINITY
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* This is not a good idea.  It prevents interoperation between
-   files compiled with -m68881 and those compiled with -msoft-float.  */
-#if 0
-#define FUNCTION_VALUEX(MODE)						    \
-  gen_rtx (REG, (MODE),							    \
-	   ((TARGET_68881						    \
-	     && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) \
-	    ? 16 : 0))
-
-#undef FUNCTION_VALUE
-#define FUNCTION_VALUE(VALTYPE,FUNC) FUNCTION_VALUEX (TYPE_MODE (VALTYPE))
-#endif /* 0 */
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)				\
-  {								\
-    if (REAL_VALUE_ISINF (VALUE))				\
-      {								\
-        if (REAL_VALUE_NEGATIVE (VALUE))			\
-          fprintf (FILE, "\t.double 0r-99e999\n");		\
-        else							\
-          fprintf (FILE, "\t.double 0r99e999\n");		\
-      }								\
-    else if (REAL_VALUE_ISNAN (VALUE))				\
-      { long l[2];						\
-        REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), l);		\
-	fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", l[0], l[1]); \
-      }								\
-    else							\
-      { char dstr[30];						\
-        REAL_VALUE_TO_DECIMAL ((VALUE), "%.17g", dstr);		\
-        fprintf (FILE, "\t.double 0r%s\n", dstr);		\
-      }								\
-    }
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)				\
-  {								\
-    if (REAL_VALUE_ISINF (VALUE))				\
-      {								\
-        if (REAL_VALUE_NEGATIVE (VALUE))			\
-          fprintf (FILE, "\t.single 0r-99e999\n");		\
-        else							\
-          fprintf (FILE, "\t.single 0r99e999\n");			\
-      }								\
-    else if (REAL_VALUE_ISNAN (VALUE))				\
-      { long l;							\
-        REAL_VALUE_TO_TARGET_SINGLE ((VALUE), l);		\
-        fprintf (FILE, "\t.long 0x%lx\n", l);			\
-      }								\
-    else							\
-      { char dstr[30];						\
-        REAL_VALUE_TO_DECIMAL ((VALUE), "%.9g", dstr);		\
-        fprintf (FILE, "\t.single 0r%s\n", dstr);		\
-      }								\
-    }
-
-/* This is how to output an assembler lines defining floating operands.
-   There's no way to output a NaN's fraction, so we lose it.  */
-  
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)		\
- do { 								\
-      if (CODE != 'f')						\
-        {							\
-          long l;						\
-          REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);		\
-          if (sizeof (int) == sizeof (long))			\
-            asm_fprintf ((FILE), "%I0x%x", l);			\
-          else							\
-            asm_fprintf ((FILE), "%I0x%lx", l);			\
-        }							\
-      else if (REAL_VALUE_ISINF (VALUE))			\
-        {							\
-          if (REAL_VALUE_NEGATIVE (VALUE))			\
-            asm_fprintf (FILE, "%I0r-99e999");			\
-          else							\
-            asm_fprintf (FILE, "%I0r99e999");			\
-        }							\
-      else if (REAL_VALUE_MINUS_ZERO (VALUE))			\
-        {							\
-          asm_fprintf (FILE, "%I0r-0.0");			\
-        }							\
-      else							\
-        { char dstr[30];					\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.9g", dstr);	\
-          asm_fprintf (FILE, "%I0r%s", dstr);			\
-        }							\
-    } while (0)
-
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)				\
- do { if (REAL_VALUE_ISINF (VALUE))					\
-        {								\
-          if (REAL_VALUE_NEGATIVE (VALUE))				\
-            asm_fprintf (FILE, "%I0r-99e999");				\
-          else								\
-            asm_fprintf (FILE, "%I0r99e999");				\
-        }								\
-      else if (REAL_VALUE_MINUS_ZERO (VALUE))				\
-        {								\
-          asm_fprintf (FILE, "%I0r-0.0");				\
-        }								\
-      else								\
-        { char dstr[30];						\
-          REAL_VALUE_TO_DECIMAL ((VALUE), "%.17g", dstr);		\
-          asm_fprintf (FILE, "%I0r%s", dstr);				\
-        }								\
-    } while (0)
-
-#if 0
-/* This was turned off as it caused linking errors on sunos4.1.
-   `gcc -a' links in /usr/lib/bb_link.o which does not provide __bb_link
-   but its own version of __bb_init_func. */
-#undef BLOCK_PROFILER_CODE
-#define BLOCK_PROFILER_CODE						\
-extern int ___tcov_init;						\
-									\
-__bb_init_func (blocks)							\
-	struct bb *blocks;						\
-{									\
-  if (! ___tcov_init)							\
-    ___tcov_init_func ();						\
-									\
-  ___bb_link (blocks->filename, blocks->counts, blocks->ncounts);	\
-}
-#endif
diff --git a/gcc/config/m68k/sun3mach.h b/gcc/config/m68k/sun3mach.h
deleted file mode 100755
index 1c76cc4..0000000
--- a/gcc/config/m68k/sun3mach.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#include "m68k/sun3.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmc68000 -Dsun -Dsun3 -Dunix -DMACH -DCMU -DMTXINU -DBIT_MSF -DBYTE_MSF -Asystem(unix)  -Asystem(mach) -Acpu(m68k) -Amachine(m68k)"
-
-/* Specify extra dir to search for include files.  */
-#define SYSTEM_INCLUDE_DIR "/usr/mach/include"
-
-/* LINK_SPEC is needed only for SunOS 4.  */
-
-#undef LINK_SPEC
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
diff --git a/gcc/config/m68k/sun3n.h b/gcc/config/m68k/sun3n.h
deleted file mode 100755
index 32f5f65..0000000
--- a/gcc/config/m68k/sun3n.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Define target machine as a Sun 3 with no 68881.  */
-
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68020)
-
-#include "m68k/sun3.h"
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
diff --git a/gcc/config/m68k/sun3n3.h b/gcc/config/m68k/sun3n3.h
deleted file mode 100755
index 38680d8..0000000
--- a/gcc/config/m68k/sun3n3.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "m68k/sun3n.h"
-
-/* LINK_SPEC is needed only for SunOS 4.  */
-
-#undef LINK_SPEC
diff --git a/gcc/config/m68k/sun3o3.h b/gcc/config/m68k/sun3o3.h
deleted file mode 100755
index 95f1ff6..0000000
--- a/gcc/config/m68k/sun3o3.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "m68k/sun3.h"
-
-/* LINK_SPEC is needed only for SunOS 4.  */
-
-#undef LINK_SPEC
diff --git a/gcc/config/m68k/t-adobe b/gcc/config/m68k/t-adobe
deleted file mode 100755
index c46960c..0000000
--- a/gcc/config/m68k/t-adobe
+++ /dev/null
@@ -1,9 +0,0 @@
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = m68k/lb1sun3.asm
-
-LIB1ASMFUNCS = _mulsi3 _udivsi3 _divsi3 _umodsi3 _modsi3 \
-   _divdf3 _muldf3 _negdf2 _adddf3 _subdf3 \
-   _fixdfsi _fixsfsi _floatsidf _floatsisf _truncdfsf2 _extendsfdf2 \
-   _addsf3 _negsf2 _subsf3 _mulsf3 _divsf3 \
-   _eqdf2 _nedf2 _gtdf2 _gedf2 _ltdf2 _ledf2 \
-   _eqsf2 _nesf2 _gtsf2 _gesf2 _ltsf2 _lesf2
diff --git a/gcc/config/m68k/t-aux b/gcc/config/m68k/t-aux
deleted file mode 100755
index 3d59d67..0000000
--- a/gcc/config/m68k/t-aux
+++ /dev/null
@@ -1,44 +0,0 @@
-# Makefile additions for A/UX
-
-LIB2FUNCS_EXTRA=aux-mcount.c aux-exit.c
-
-FIXPROTO_DEFINES=-D_POSIX_SOURCE
-
-# Only really needed for collect2
-CLIB=-lld
-
-# Needed to support builds for multiple versions of A/UX
-# LDFLAGS=-static
-
-# Make sure we get the right assembler by letting gcc choose
-AS = $(GCC_FOR_TARGET) -xassembler-with-cpp -D__ASSEMBLY__ $(INCLUDES) -c
-
-aux-mcount.c: $(srcdir)/config/m68k/aux-mcount.c
-	cp $(srcdir)/config/m68k/aux-mcount.c aux-mcount.c
-
-aux-exit.c: $(srcdir)/config/m68k/aux-exit.c
-	cp $(srcdir)/config/m68k/aux-exit.c aux-exit.c
-
-crt1.o: $(srcdir)/config/m68k/aux-crt1.c $(GCC_PASSES)
-	$(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) $(INCLUDES) -o crt1.o -c \
-	  -fno-omit-frame-pointer $(srcdir)/config/m68k/aux-crt1.c
-
-mcrt1.o: $(srcdir)/config/m68k/aux-crt1.c $(GCC_PASSES)
-	$(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) $(INCLUDES) -o mcrt1.o -c \
-	  -fno-omit-frame-pointer -DMCRT1 $(srcdir)/config/m68k/aux-crt1.c
-
-maccrt1.o: $(srcdir)/config/m68k/aux-crt1.c $(GCC_PASSES)
-	$(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) $(INCLUDES) -o maccrt1.o -c \
-	  -fno-omit-frame-pointer -DMACCRT1 $(srcdir)/config/m68k/aux-crt1.c
-
-crt2.o: $(srcdir)/config/m68k/aux-crt2.asm $(GCC_PASSES)
-	$(AS) -o crt2.o $(srcdir)/config/m68k/aux-crt2.asm
-
-crtn.o: $(srcdir)/config/m68k/aux-crtn.asm $(GCC_PASSES)
-	$(AS) -o crtn.o $(srcdir)/config/m68k/aux-crtn.asm
-
-low.gld: $(srcdir)/config/m68k/aux-low.gld
-	sed -e 's|@libdir@|$(libdir)|' -e 's|@tooldir@|$(tooldir)|' \
-		-e 's|@local_prefix@|$(local_prefix)|' \
-		$(srcdir)/config/m68k/aux-low.gld > tmp-low.gld
-	mv tmp-low.gld low.gld
diff --git a/gcc/config/m68k/t-linux b/gcc/config/m68k/t-linux
deleted file mode 100755
index 99dc452..0000000
--- a/gcc/config/m68k/t-linux
+++ /dev/null
@@ -1,2 +0,0 @@
-# On GNU/Linux we can print long double
-ENQUIRE_CFLAGS = -DNO_MEM -O0
diff --git a/gcc/config/m68k/t-linux-aout b/gcc/config/m68k/t-linux-aout
deleted file mode 100755
index 99dc452..0000000
--- a/gcc/config/m68k/t-linux-aout
+++ /dev/null
@@ -1,2 +0,0 @@
-# On GNU/Linux we can print long double
-ENQUIRE_CFLAGS = -DNO_MEM -O0
diff --git a/gcc/config/m68k/t-lynx b/gcc/config/m68k/t-lynx
deleted file mode 100755
index 6f2caba..0000000
--- a/gcc/config/m68k/t-lynx
+++ /dev/null
@@ -1,6 +0,0 @@
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = m68k/lb1sf68.asm
-LIB1ASMFUNCS = _mulsi3 _udivsi3 _divsi3 _umodsi3 _modsi3 \
-   _double _float _floatex \
-   _eqdf2 _nedf2 _gtdf2 _gedf2 _ltdf2 _ledf2 \
-   _eqsf2 _nesf2 _gtsf2 _gesf2 _ltsf2 _lesf2
diff --git a/gcc/config/m68k/t-m68kbare b/gcc/config/m68k/t-m68kbare
deleted file mode 100755
index d334eab..0000000
--- a/gcc/config/m68k/t-m68kbare
+++ /dev/null
@@ -1,24 +0,0 @@
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = m68k/lb1sf68.asm
-LIB1ASMFUNCS = _mulsi3 _udivsi3 _divsi3 _umodsi3 _modsi3 \
-   _double _float _floatex \
-   _eqdf2 _nedf2 _gtdf2 _gedf2 _ltdf2 _ledf2 \
-   _eqsf2 _nesf2 _gtsf2 _gesf2 _ltsf2 _lesf2
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-LIB2FUNCS_EXTRA = fpgnulib.c xfgnulib.c
-
-fpgnulib.c: $(srcdir)/config/m68k/fpgnulib.c
-	cp $(srcdir)/config/m68k/fpgnulib.c fpgnulib.c
-xfgnulib.c: $(srcdir)/config/m68k/fpgnulib.c
-	echo '#define EXTFLOAT' > xfgnulib.c
-	cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c
-
-MULTILIB_OPTIONS = m68000/m68020/m5200/mcpu32 m68881/msoft-float
-MULTILIB_DIRNAMES =
-MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 m68020=m68040 m68020=m68060
-MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float mcpu32/m68881 mcpu32/msoft-float
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/m68k/t-m68kelf b/gcc/config/m68k/t-m68kelf
deleted file mode 100755
index d0f857a..0000000
--- a/gcc/config/m68k/t-m68kelf
+++ /dev/null
@@ -1,29 +0,0 @@
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = m68k/lb1sf68.asm
-LIB1ASMFUNCS = _mulsi3 _udivsi3 _divsi3 _umodsi3 _modsi3 \
-   _double _float _floatex \
-   _eqdf2 _nedf2 _gtdf2 _gedf2 _ltdf2 _ledf2 \
-   _eqsf2 _nesf2 _gtsf2 _gesf2 _ltsf2 _lesf2
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-LIB2FUNCS_EXTRA = fpgnulib.c xfgnulib.c
-
-fpgnulib.c: $(srcdir)/config/m68k/fpgnulib.c
-	cp $(srcdir)/config/m68k/fpgnulib.c fpgnulib.c
-xfgnulib.c: $(srcdir)/config/m68k/fpgnulib.c
-	echo '#define EXTFLOAT' > xfgnulib.c
-	cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c
-
-MULTILIB_OPTIONS = m68000/m68020/m5200/mcpu32 m68881/msoft-float
-MULTILIB_DIRNAMES =
-MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 m68020=m68040 m68020=m68060
-MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float mcpu32/m68881 mcpu32/msoft-float
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# from ../t-svr4
-EXTRA_PARTS=crtbegin.o crtend.o
-# no pic for now
-#CRTSTUFF_T_CFLAGS=-fpic
diff --git a/gcc/config/m68k/t-mot3300 b/gcc/config/m68k/t-mot3300
deleted file mode 100755
index 2fc1185..0000000
--- a/gcc/config/m68k/t-mot3300
+++ /dev/null
@@ -1,10 +0,0 @@
-MULTILIB_OPTIONS=m68000/m68020 msoft-float
-MULTILIB_DIRNAMES=
-MULTILIB_MATCHES=m68000=mc68000 m68000=m68302 m68000=m68332 m68020=mc68020 m68020=m68040
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-CRT0_S = $(srcdir)/config/m68k/mot3300-crt0.S
-MCRT0_S = $(srcdir)/config/m68k/mot3300Mcrt0.S
-CRT0STUFF_T_CFLAGS = -DMOTOROLA -DSGS_CMP_ORDER
diff --git a/gcc/config/m68k/t-mot3300-gald b/gcc/config/m68k/t-mot3300-gald
deleted file mode 100755
index 435afc4..0000000
--- a/gcc/config/m68k/t-mot3300-gald
+++ /dev/null
@@ -1,13 +0,0 @@
-T_CPPFLAGS = -DUSE_GAS -DUSE_GLD
-TARGET_LIBGCC2_CFLAGS = -DUSE_GAS
-
-MULTILIB_OPTIONS=m68000/m68020 msoft-float
-MULTILIB_DIRNAMES=
-MULTILIB_MATCHES=m68000=mc68000 m68000=m68302 m68000=m68332 m68020=mc68020 m68020=m68040
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-CRT0_S = $(srcdir)/config/m68k/mot3300-crt0.S
-MCRT0_S = $(srcdir)/config/m68k/mot3300Mcrt0.S
-CRT0STUFF_T_CFLAGS =
diff --git a/gcc/config/m68k/t-mot3300-gas b/gcc/config/m68k/t-mot3300-gas
deleted file mode 100755
index 5256674..0000000
--- a/gcc/config/m68k/t-mot3300-gas
+++ /dev/null
@@ -1,13 +0,0 @@
-T_CPPFLAGS = -DUSE_GAS
-TARGET_LIBGCC2_CFLAGS = -DUSE_GAS
-
-MULTILIB_OPTIONS=m68000/m68020 msoft-float
-MULTILIB_DIRNAMES=
-MULTILIB_MATCHES=m68000=mc68000 m68000=m68302 m68000=m68332 m68020=mc68020 m68020=m68040
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-CRT0_S = $(srcdir)/config/m68k/mot3300-crt0.S
-MCRT0_S = $(srcdir)/config/m68k/mot3300Mcrt0.S
-CRT0STUFF_T_CFLAGS =
diff --git a/gcc/config/m68k/t-mot3300-gld b/gcc/config/m68k/t-mot3300-gld
deleted file mode 100755
index 8cc3ed6..0000000
--- a/gcc/config/m68k/t-mot3300-gld
+++ /dev/null
@@ -1,12 +0,0 @@
-T_CPPFLAGS = -DUSE_GLD
-
-MULTILIB_OPTIONS=m68000/m68020 msoft-float
-MULTILIB_DIRNAMES=
-MULTILIB_MATCHES=m68000=mc68000 m68000=m68302 m68000=m68332 m68020=mc68020 m68020=m68040
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-CRT0_S = $(srcdir)/config/m68k/mot3300-crt0.S
-MCRT0_S = $(srcdir)/config/m68k/mot3300Mcrt0.S
-CRT0STUFF_T_CFLAGS = -DMOTOROLA -DSGS_CMP_ORDER
diff --git a/gcc/config/m68k/t-next b/gcc/config/m68k/t-next
deleted file mode 100755
index 787ee79..0000000
--- a/gcc/config/m68k/t-next
+++ /dev/null
@@ -1,6 +0,0 @@
-# libgcc1.c is not needed, since the standard library has these functions.
-LIBGCC1=
-CROSS_LIBGCC1=
-
-nextstep.o: $(srcdir)/config/nextstep.c $(CONFIG_H) flags.h tree.h
-	$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
diff --git a/gcc/config/m68k/t-ose68 b/gcc/config/m68k/t-ose68
deleted file mode 100755
index 5f9cba2..0000000
--- a/gcc/config/m68k/t-ose68
+++ /dev/null
@@ -1,26 +0,0 @@
-# CYGNUS LOCAL ericsson
-
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = m68k/lb1sf68.asm
-LIB1ASMFUNCS = _mulsi3 _udivsi3 _divsi3 _umodsi3 _modsi3 \
-   _double _float _floatex \
-   _eqdf2 _nedf2 _gtdf2 _gedf2 _ltdf2 _ledf2 \
-   _eqsf2 _nesf2 _gtsf2 _gesf2 _ltsf2 _lesf2
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-LIB2FUNCS_EXTRA = fpgnulib.c xfgnulib.c
-
-fpgnulib.c: $(srcdir)/config/m68k/fpgnulib.c
-	cp $(srcdir)/config/m68k/fpgnulib.c fpgnulib.c
-xfgnulib.c: $(srcdir)/config/m68k/fpgnulib.c
-	echo '#define EXTFLOAT' > xfgnulib.c
-	cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c
-
-MULTILIB_OPTIONS= m68000/m68020 m68881/msoft-float
-MULTILIB_DIRNAMES =
-MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 m68000=m68332 m68020=mc68020 m68020=m68040
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
diff --git a/gcc/config/m68k/t-vxworks68 b/gcc/config/m68k/t-vxworks68
deleted file mode 100755
index 7fa5943..0000000
--- a/gcc/config/m68k/t-vxworks68
+++ /dev/null
@@ -1,27 +0,0 @@
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = m68k/lb1sf68.asm
-LIB1ASMFUNCS = _mulsi3 _udivsi3 _divsi3 _umodsi3 _modsi3 \
-   _double _float _floatex \
-   _eqdf2 _nedf2 _gtdf2 _gedf2 _ltdf2 _ledf2 \
-   _eqsf2 _nesf2 _gtsf2 _gesf2 _ltsf2 _lesf2
-
-# We don't want to put exit in libgcc.a for VxWorks, because VxWorks
-# does not have _exit.
-TARGET_LIBGCC2_CFLAGS = -Dexit=unused_exit
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-LIB2FUNCS_EXTRA = fpgnulib.c xfgnulib.c
-
-fpgnulib.c: $(srcdir)/config/m68k/fpgnulib.c
-	cp $(srcdir)/config/m68k/fpgnulib.c fpgnulib.c
-xfgnulib.c: $(srcdir)/config/m68k/fpgnulib.c
-	echo '#define EXTFLOAT' > xfgnulib.c
-	cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c
-
-MULTILIB_OPTIONS = m68000/m68020 m68881/msoft-float
-MULTILIB_DIRNAMES =
-MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 m68000=m68332 m68020=mc68020 m68020=m68040
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/m68k/tower-as.h b/gcc/config/m68k/tower-as.h
deleted file mode 100755
index 7b5771a..0000000
--- a/gcc/config/m68k/tower-as.h
+++ /dev/null
@@ -1,616 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   For NCR Tower 32/4x0 and 32/6x0 running System V Release 3.
-   Copyright (C) 1990, 1993, 1994, 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Robert Andersson (ra@intsys.no), International Systems,
-   Oslo, Norway.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* This file outputs assembler source suitable for the native Tower as
-   and with sdb debugging symbols.  See tower.h for more comments.
-
-   This file was based on m68k.h, hp320.h and 3b1.h as of the
-   1.37.1 version.  */
-
-#include "m68k/tower.h"
-#undef SELECT_RTX_SECTION
-
-/* Use default settings for system V.3.  */
-
-#include "svr3.h"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_600 -D__motorola__ -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)"
-
-/* Define __HAVE_68881 in preprocessor only if -m68881 is specified.
-   This will control the use of inline 68881 insns in certain macros.
-   Also, define special define used to identify the Tower assembler.  */
-
-#define CPP_SPEC "-D__TOWER_ASM__ %{m68881:-D__HAVE_68881__}"
-
-/* We don't want local labels to start with period.
-   See ASM_OUTPUT_INTERNAL_LABEL.  */
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX ""
-
-/* The prefix to add to user-visible assembler symbols.  */
-/* We do not want leading underscores.  */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-
-/* These four macros control how m68k.md is expanded.  */
-
-#define MOTOROLA		/* Use Motorola syntax rather than "MIT" */
-#define SGS			/* Uses SGS assembler */
-#define SGS_CMP_ORDER		/* Takes cmp operands in reverse order */
-#define SGS_NO_LI		/* Suppress jump table label usage */
-
-/* Turn on SDB debugging info.  */
-
-#define SDB_DEBUGGING_INFO
-
-/* This is only useful if gdb is changed, but doesn't harm anyway.  */
-
-#define ASM_IDENTIFY_GCC(FILE) \
-  fprintf (FILE, "gcc2_compiled%%:\n")
-
-/* All the ASM_OUTPUT macros need to conform to the Tower as syntax.  */
-
-#define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) \
-  do {						   \
-    fprintf (FILE, "\tfile\t");			   \
-    output_quoted_string (FILE, FILENAME);	   \
-    fprintf (FILE, "\n");			   \
-    fprintf (FILE, "section ~init,\"x\"\n");	   \
-    fprintf (FILE, "section ~fini,\"x\"\n");	   \
-    fprintf (FILE, "section ~rodata,\"x\"\n");   \
-    fprintf (FILE, "text\n");			   \
-  } while (0)
-
-#define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO)	\
-  fprintf (FILE, "\tln\t%d\n",			\
-	   (sdb_begin_function_line		\
-	    ? last_linenum - sdb_begin_function_line : 1))
-
-#undef ASM_OUTPUT_IDENT
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  fprintf (FILE, "\tident\t\"%s\" \n", NAME)
-
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \
-  do { register int sp = 0, lp = 0; \
-    fprintf ((FILE), "\tbyte\t"); \
-  loop: \
-    if ((PTR)[sp] > ' ' && ! ((PTR)[sp] & 0x80) && (PTR)[sp] != '\\') \
-      { lp += 3; \
-	fprintf ((FILE), "'%c", (PTR)[sp]); } \
-    else \
-      { lp += 5; \
-	fprintf ((FILE), "0x%x", (PTR)[sp]); } \
-    if (++sp < (LEN)) \
-      {	if (lp > 60) \
-	  { lp = 0; \
-	    fprintf ((FILE), "\n\tbyte\t"); }	\
-	else \
-	  putc (',', (FILE)); \
-	goto loop; } \
-    putc ('\n', (FILE)); } while (0)
-
-/* Translate Motorola opcodes such as `jbeq'
-   into SGS/Tower opcodes such as `beq.w'.
-   Change `move' to `mov'.
-   Change `cmpm' to `cmp'.
-   Change `divsl' to `tdivs'.
-   Change `divul' to `tdivu'.
-   Change `ftst' to `ftest'.
-   Change `fmove' to `fmov'.  */
-
-#define ASM_OUTPUT_OPCODE(FILE, PTR)			\
-{ if ((PTR)[0] == 'j' && (PTR)[1] == 'b')		\
-    { ++(PTR);						\
-      while (*(PTR) != ' ')				\
-	{ putc (*(PTR), (FILE)); ++(PTR); }		\
-      fprintf ((FILE), ".w"); }				\
-  else if ((PTR)[0] == 'm' && (PTR)[1] == 'o'		\
-	   && (PTR)[2] == 'v' && (PTR)[3] == 'e')	\
-    { fprintf ((FILE), "mov"); (PTR) += 4; }		\
-  else if ((PTR)[0] == 'c' && (PTR)[1] == 'm'		\
-	   && (PTR)[2] == 'p' && (PTR)[3] == 'm')	\
-    { fprintf ((FILE), "cmp"); (PTR) += 4; }		\
-  else if ((PTR)[0] == 'd' && (PTR)[1] == 'i'		\
-	   && (PTR)[2] == 'v' && (PTR)[3] == 's'	\
-	   && (PTR)[4] == 'l')				\
-    { fprintf ((FILE), "tdivs"); (PTR) += 5; }		\
-  else if ((PTR)[0] == 'd' && (PTR)[1] == 'i'		\
-	   && (PTR)[2] == 'v' && (PTR)[3] == 'u'	\
-	   && (PTR)[4] == 'l')				\
-    { fprintf ((FILE), "tdivu"); (PTR) += 5; }		\
-  else if ((PTR)[0] == 'f' && (PTR)[1] == 't'		\
-	   && (PTR)[2] == 's' && (PTR)[3] == 't')	\
-    { fprintf ((FILE), "ftest"); (PTR) += 4; }		\
-  else if ((PTR)[0] == 'f' && (PTR)[1] == 'm'		\
-	   && (PTR)[2] == 'o' && (PTR)[3] == 'v' 	\
-	   && (PTR)[4] == 'e')				\
-    { fprintf ((FILE), "fmov"); (PTR) += 5; }		\
-}
-
-
-
-/* Override parts of m68k.h to fit the Tower assembler.
-   This section needs to track changes done to m68k.h in the future.  */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (68k, Motorola/SGS/Tower32 syntax)");
-
-#undef FUNCTION_BLOCK_PROFILER
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)				\
-  do {									\
-    char label1[20], label2[20];					\
-    ASM_GENERATE_INTERNAL_LABEL (label1, "LPBX", 0);			\
-    ASM_GENERATE_INTERNAL_LABEL (label2, "LPI", LABELNO);		\
-    fprintf (FILE, "\ttst.l %s\n\tbne %s\n\tpea %s\n\tjsr __bb_init_func\n\taddq.l &4,%%sp\n",	\
-	     label1, label2, label1);					\
-    ASM_OUTPUT_INTERNAL_LABEL (FILE, "LPI", LABELNO);			\
-    putc ('\n', FILE);						\
-    } while (0)
-
-#undef BLOCK_PROFILER
-#define BLOCK_PROFILER(FILE, BLOCKNO)				\
-  do {								\
-    char label[20];						\
-    ASM_GENERATE_INTERNAL_LABEL (label, "LPBX", 2);		\
-    fprintf (FILE, "\taddq.l &1,%s+%d\n", label, 4 * BLOCKNO);	\
-    } while (0)
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABEL_NO)	\
-    fprintf (FILE, "\tmov.l &LP%%%d,%%a0\n\tjsr mcount%%\n", (LABEL_NO))
-
-#undef FUNCTION_EXTRA_EPILOGUE
-#define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)				\
-  { extern int current_function_returns_pointer;			\
-    if ((current_function_returns_pointer) &&				\
-      ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode))        \
-      asm_fprintf (FILE, "\tmov.l %Rd0,%Ra0\n"); } 
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#undef ASM_OUTPUT_REG_PUSH
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tmov.l %s,-(%%sp)\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#undef ASM_OUTPUT_REG_POP
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tmov.l (%%sp)+,%s\n", reg_names[REGNO])
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
-( fprintf (FILE, "#NO_APP\n"), \
-  output_file_directive ((FILE), main_input_filename))
-
-#undef TEXT_SECTION_ASM_OP
-#define TEXT_SECTION_ASM_OP "text"
-
-#undef DATA_SECTION_ASM_OP
-#define DATA_SECTION_ASM_OP "data"
-
-/* This says how to output an assembler line to define a global common symbol.
-   We use SIZE rather than ROUNDED, as this is what the native cc does.  */
-
-#undef ASM_OUTPUT_COMMON
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\tcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%d\n", ((SIZE) == 0) ? (ROUNDED) : (SIZE)))
-
-/* This says how to output an assembler line to define a local common symbol.
-   We use SIZE rather than ROUNDED, as this is what the native cc does.  */
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\tlcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%d\n", ((SIZE) == 0) ? (ROUNDED) : (SIZE)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#undef ASM_FORMAT_PRIVATE_NAME
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 11),	\
-  sprintf ((OUTPUT), "%s%%%%%d", (NAME), (LABELNO)))
- 
-/* This is the command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#undef GLOBAL_ASM_OP
-#define GLOBAL_ASM_OP "global"
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)	\
-  sprintf ((LABEL), "%s%%%d", (PREFIX), (NUM))
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf ((FILE), "%s%%%d:\n", (PREFIX), (NUM))
-
-#undef ASM_OUTPUT_CASE_LABEL
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE)			\
-  fprintf (FILE, "\tswbeg &%d\n%s%%%d:\n",				\
-           XVECLEN (PATTERN (TABLE), 1), (PREFIX), (NUM));		\
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-do { long l[2];						\
-     REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l);		\
-     fprintf (FILE, "\tlong 0x%x,0x%x\n", l[0], l[1]); \
-   } while (0)
-
-#undef ASM_OUTPUT_LONG_DOUBLE
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE)  				\
-do { long l[3];								\
-     REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l);			\
-     fprintf (FILE, "\tlong 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]);	\
-   } while (0)
-
-#undef ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-do { long l;					\
-     REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);	\
-     fprintf ((FILE), "\tlong 0x%x\n", l);	\
-   } while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#undef ASM_OUTPUT_INT
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\tlong "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#undef ASM_OUTPUT_SHORT
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\tshort "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#undef ASM_OUTPUT_CHAR
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\tbyte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#undef ASM_OUTPUT_BYTE
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\tbyte 0x%x\n", (VALUE))
-
-#undef ASM_OUTPUT_ADDR_VEC_ELT
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\tlong L%%%d\n", (VALUE))
-
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\tshort L%%%d-L%%%d\n", (VALUE), (REL))
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) == 1)			\
-    fprintf (FILE, "\teven\n");	        \
-  else if ((LOG) != 0)			\
-    abort ();
-
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\tspace %d\n", (SIZE))
-
-/* Output a float value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-
-#undef ASM_OUTPUT_FLOAT_OPERAND
-#define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)			\
- do { long l;								\
-      REAL_VALUE_TO_TARGET_SINGLE (r, l);				\
-      /* Use hex representation even if CODE is f.  as needs it.  */	\
-      fprintf ((FILE), "&0x%lx", l);					\
-    } while (0)
-
-/* Output a double value (represented as a C double) as an immediate operand.
-   This macro is a 68k-specific macro.  */
-#undef ASM_OUTPUT_DOUBLE_OPERAND
-#define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)				\
- do { long l[2];							\
-      REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l);				\
-      fprintf ((FILE), "&0x%lx%08lx", l[0], l[1]);			\
-    } while (0)
-
-#if 0
-#undef PRINT_OPERAND
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ if (CODE == '.') fprintf (FILE, ".");					\
-  else if (CODE == '#') fprintf (FILE, "&");				\
-  else if (CODE == '-') fprintf (FILE, "-(%%sp)");			\
-  else if (CODE == '+') fprintf (FILE, "(%%sp)+");			\
-  else if (CODE == '@') fprintf (FILE, "(%%sp)");			\
-  else if (CODE == '!') fprintf (FILE, "%%fpcr");			\
-  else if (CODE == '/')							\
-    fprintf (FILE, "%%");						\
-  else if (CODE == '$') { if (TARGET_68040_ONLY) fprintf (FILE, "s"); }	\
-  else if (CODE == '&') { if (TARGET_68040_ONLY) fprintf (FILE, "d"); }	\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode)	\
-    { REAL_VALUE_TYPE r; long l;					\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      REAL_VALUE_TO_TARGET_SINGLE (r, l);				\
-      fprintf (FILE, "&0x%x", l); }					\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode)	\
-    { REAL_VALUE_TYPE r; int i[2];					\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      REAL_VALUE_TO_TARGET_DOUBLE (r, i);				\
-      fprintf (FILE, "&0x%x%08x", i[0], i[1]); }			\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == XFmode)	\
-    { REAL_VALUE_TYPE r;						\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      ASM_OUTPUT_LONG_DOUBLE_OPERAND (FILE, r); }			\
-  else { putc ('&', FILE); output_addr_const (FILE, X); }}
-#endif
-
-/* Note that this contains a kludge that knows that the only reason
-   we have an address (plus (label_ref...) (reg...))
-   is in the insn before a tablejump, and we know that the table is
-   exactly 10 bytes away.  */
-
-#undef PRINT_OPERAND_ADDRESS
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx reg1, reg2, breg, ireg;					\
-  register rtx addr = ADDR;						\
-  rtx offset;								\
-  switch (GET_CODE (addr))						\
-    {									\
-    case REG:								\
-      fprintf (FILE, "(%s)", reg_names[REGNO (addr)]);			\
-      break;								\
-    case PRE_DEC:							\
-      fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case POST_INC:							\
-      fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);	\
-      break;								\
-    case PLUS:								\
-      reg1 = 0;	reg2 = 0;						\
-      ireg = 0;	breg = 0;						\
-      offset = 0;							\
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))				\
-	{								\
-	  offset = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))			\
-	{								\
-	  offset = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) != PLUS) ;					\
-      else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)		\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT		\
-	  || GET_CODE (addr) == SIGN_EXTEND)				\
-	{ if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; }	\
-/*  for OLD_INDEXING							\
-      else if (GET_CODE (addr) == PLUS)					\
-	{								\
-	  if (GET_CODE (XEXP (addr, 0)) == REG)				\
-	    {								\
-	      reg2 = XEXP (addr, 0);					\
-	      addr = XEXP (addr, 1);					\
-	    }								\
-	  else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	    {								\
-	      reg2 = XEXP (addr, 1);					\
-	      addr = XEXP (addr, 0);					\
-	    }								\
-	}								\
-  */									\
-      if (offset != 0) { if (addr != 0) abort (); addr = offset; }	\
-      if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND			\
-		    || GET_CODE (reg1) == MULT))			\
-	  || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))		\
-	{ breg = reg2; ireg = reg1; }					\
-      else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))		\
-	{ breg = reg1; ireg = reg2; }					\
-      if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF)	\
-        { int scale = 1;						\
-	  if (GET_CODE (ireg) == MULT)					\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (GET_CODE (ireg) == SIGN_EXTEND)				\
-	    fprintf (FILE, "10(%%pc,%s.w",				\
-		     reg_names[REGNO (XEXP (ireg, 0))]); 		\
-	  else								\
-	    fprintf (FILE, "10(%%pc,%s.l",				\
-		     reg_names[REGNO (ireg)]);				\
-	  if (scale != 1) fprintf (FILE, "*%d", scale);			\
-	  putc (')', FILE);						\
-	  break; }							\
-      if (ireg != 0 || breg != 0)					\
-	{ int scale = 1;						\
-	  if (breg == 0)						\
-	    abort ();							\
-	  if (addr != 0)						\
-	    output_addr_const (FILE, addr);				\
-	  fprintf (FILE, "(%s", reg_names[REGNO (breg)]);		\
-	  if (ireg != 0)						\
-	    putc (',', FILE);						\
-	  if (ireg != 0 && GET_CODE (ireg) == MULT)			\
-	    { scale = INTVAL (XEXP (ireg, 1));				\
-	      ireg = XEXP (ireg, 0); }					\
-	  if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)		\
-	    fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);	\
-	  else if (ireg != 0)						\
-	    fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]);		\
-	  if (scale != 1) fprintf (FILE, "*%d", scale);			\
-	  putc (')', FILE);						\
-	  break;							\
-	}								\
-      else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF)		\
-	{ fprintf (FILE, "10(%%pc,%s.w)",				\
-		   reg_names[REGNO (reg1)]);				\
-	  break; }							\
-    default:								\
-        output_addr_const (FILE, addr);					\
-    }}
-
-
-
-/* Override usual definitions of SDB output macros.
-   These definitions differ only in the absence of the period
-   at the beginning of the name of the directive
-   and in the use of `~' as the symbol for the current location.  */
-
-#define PUT_SDB_SCL(a) fprintf(asm_out_file, "\tscl\t%d;", (a))
-#define PUT_SDB_INT_VAL(a) fprintf (asm_out_file, "\tval\t%d;", (a))
-#define PUT_SDB_VAL(a)				\
-( fputs ("\tval\t", asm_out_file),		\
-  output_addr_const (asm_out_file, (a)),	\
-  fputc (';', asm_out_file))
-
-#define PUT_SDB_DEF(a)				\
-do { fprintf (asm_out_file, "\tdef\t");	\
-     ASM_OUTPUT_LABELREF (asm_out_file, a); 	\
-     fprintf (asm_out_file, ";"); } while (0)
-
-#define PUT_SDB_PLAIN_DEF(a) fprintf(asm_out_file,"\tdef\t~%s;",a)
-#define PUT_SDB_ENDEF fputs("\tendef\n", asm_out_file)
-#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\ttype\t0%o;", a)
-#define PUT_SDB_SIZE(a) fprintf(asm_out_file, "\tsize\t%d;", a)
-#define PUT_SDB_START_DIM fprintf(asm_out_file, "\tdim\t")
-#define PUT_SDB_NEXT_DIM(a) fprintf(asm_out_file, "%d,", a)
-#define PUT_SDB_LAST_DIM(a) fprintf(asm_out_file, "%d;", a)
-
-#define PUT_SDB_TAG(a)				\
-do { fprintf (asm_out_file, "\ttag\t");	\
-     ASM_OUTPUT_LABELREF (asm_out_file, a);	\
-     fprintf (asm_out_file, ";"); } while (0)
-
-#define PUT_SDB_BLOCK_START(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~bb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n",	\
-	   (LINE))
-
-#define PUT_SDB_BLOCK_END(LINE)			\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~eb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n",	\
-	   (LINE))
-
-#define PUT_SDB_FUNCTION_START(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~bf;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n",	\
-	   (LINE))
-
-#define PUT_SDB_FUNCTION_END(LINE)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t~ef;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n",	\
-	   (LINE))
-
-#define PUT_SDB_EPILOGUE_END(NAME)		\
-  fprintf (asm_out_file,			\
-	   "\tdef\t%s;\tval\t~;\tscl\t-1;\tendef\n",	\
-	   (NAME))
-
-#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
-  sprintf ((BUFFER), "~%dfake", (NUMBER));
-
-#define NO_DOLLAR_IN_LABEL
-#define NO_DOT_IN_LABEL
-
-/* The usual definitions don't work because neither $ nor . is allowed.  */
-#define CONSTRUCTOR_NAME_FORMAT "_GLOBAL_%%I\%%%s"
-
-/* Define a few machine-specific details
-   of the implementation of constructors.
-
-   The __CTORS_LIST__ goes in the .init section.  Define CTOR_LIST_BEGIN
-   and CTOR_LIST_END to contribute to the .init section an instruction to
-   push a word containing 0 (or some equivalent of that).
-
-   ASM_OUTPUT_CONSTRUCTOR should be defined
-   to push the address of the constructor.  */
-
-#define ASM_LONG	"\tlong"
-#undef INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP	"section\t~init"
-#undef FINI_SECTION_ASM_OP
-#define FINI_SECTION_ASM_OP	"section\t~fini"
-#undef CONST_SECTION_ASM_OP
-#define CONST_SECTION_ASM_OP	"section\t~rodata"
-
-#define CTOR_LIST_BEGIN				\
-  asm (INIT_SECTION_ASM_OP);			\
-  asm ("clr.l -(%sp)")
-#define CTOR_LIST_END CTOR_LIST_BEGIN
-
-#define BSS_SECTION_ASM_OP	"section\t~bss"
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)	\
-  do {						\
-    init_section ();				\
-    fprintf (FILE, "\tmov.l &");		\
-    assemble_name (FILE, NAME);			\
-    fprintf (FILE, ",-(%%sp)\n");		\
-  } while (0)
diff --git a/gcc/config/m68k/tower.h b/gcc/config/m68k/tower.h
deleted file mode 100755
index 73faedb..0000000
--- a/gcc/config/m68k/tower.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Copyright (C) 1990, 1994, 1996 Free Software Foundation, Inc.
-   Contributed by Robert Andersson, International Systems, Oslo, ra@intsys.no.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* For NCR Tower 32/4x0 and 32/6x0 running System V Release 3.  I don't have
-   access to 200/700/800/850 machines, so I don't know if it works on those
-   as well.  It shouldn't be far from it however.  The hardware floating point
-   support is completely untested, as I do not have access to a machine with
-   a 6888x FPU in it.  It does not work on the System V Release 2 based OS
-   releases.  Making it work will not be easy, due to the silly way in which
-   stack expansion is implemented in the OS.
-
-   This file is included in tower-as.h.
-   Do *NOT* include this file directly.  */
-
-
-#include "m68k/m68k.h"
-
-#define TARGET_DEFAULT (MASK_BITFIELD|MASK_68020)
-
-/* Don't try using XFmode.  */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_200 -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)"
-
-#if 0  /* It is incorrect to test these symbols.
-	  They describe the host, not the target.
-	  It should not matter which model is specified.  */
-#ifdef tower32_600
-#define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_600 -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)"
-#endif
-#ifdef tower32_700
-#define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_700 -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)"
-#endif
-#ifdef tower32_800
-#define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_800 -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)"
-#endif
-#ifdef tower32_850
-#define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_850 -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)"
-#endif
-#endif
-
-/* The startfiles and libraries depend on the -p and -m68881 options.
-   The Tower does not support the -pg option.  */
-
-#define LINK_SPEC                                              \
-"%{p:%{m68881:-L/usr/lib/fp/libp} -L/usr/lib/libp}             \
- %{m68881:-L/usr/lib/fp}"
-
-#define LIB_SPEC \
-"%{shlib:-lc_s} -lc crtend.o%s crtn.o%s"
-
-#define STARTFILE_SPEC \
-"%{p:mcrt1.o%s} %{!p:crt1.o%s} crtbegin.o%s"
-
-/* Use mem* functions, recognize #ident lines.  */
-
-#define TARGET_MEM_FUNCTIONS
-#define IDENT_DIRECTIVE
-
-/* Every structure and union's size must be a multiple of two bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* All register names should have a leading % character.  */
-
-#undef REGISTER_NAMES
-#define REGISTER_NAMES \
-{"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",                      \
- "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp",                      \
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7"};
-
-#undef REGISTER_PREFIX
-#define REGISTER_PREFIX "%"
-
-#undef IMMEDIATE_PREFIX
-#define IMMEDIATE_PREFIX "&"
-
-/* The prefix to add to user-visible assembler symbols. */
-
-/* We do not want leading underscores.  */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
diff --git a/gcc/config/m68k/vxm68k.h b/gcc/config/m68k/vxm68k.h
deleted file mode 100755
index 063ded8..0000000
--- a/gcc/config/m68k/vxm68k.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Vxworks m68k version.
-   Copyright (C) 1994, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This comment is here to see if it will keep Sun's cpp from dying.  */
-
-#include "m68k/m68k-none.h"
-#include "aoutos.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmc68000 -D__vxworks -D__vxworks_5 -Acpu(m68k) -Amachine(m68k)"
-
-/* The default value for -DCPU=.  */
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68k || TARGET_CPU_DEFAULT == M68K_CPU_m68020
-#define CPP_SUBTARGET_CPU_DEFAULT_SPEC "-DCPU=MC68020"
-#else
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68000
-#define CPP_SUBTARGET_CPU_DEFAULT_SPEC "-DCPU=MC68000"
-#else
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68030
-#define CPP_SUBTARGET_CPU_DEFAULT_SPEC "-DCPU=MC68030"
-#else
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68040
-#define CPP_SUBTARGET_CPU_DEFAULT_SPEC "-DCPU=MC68040"
-#else
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68302
-#define CPP_SUBTARGET_CPU_DEFAULT_SPEC "-DCPU=MC68302"
-#else
-#if TARGET_CPU_DEFAULT == M68K_CPU_m68332
-#define CPP_SUBTARGET_CPU_DEFAULT_SPEC "-DCPU=MC68332"
-#else
-Unrecognized value in TARGET_CPU_DEFAULT.
-#endif
-#endif
-#endif
-#endif
-#endif
-#endif
-
-#undef SUBTARGET_EXTRA_SPECS
-#define SUBTARGET_EXTRA_SPECS \
-{ "cpp_subtarget_cpu_default", CPP_SUBTARGET_CPU_DEFAULT_SPEC }
-
-/* Vxworks header files require that the macro CPU be set.  */
-/* ??? The previous code didn't set CPU if -ansi.  */
-#undef CPP_SUBTARGET_SPEC
-#define CPP_SUBTARGET_SPEC "\
-%{m68000:-DCPU=MC68000 }%{m68010:-DCPU=MC68010 }%{m68020:-DCPU=MC68020 }%{mc68020:-DCPU=MC68020 }%{m68030:-DCPU=MC68030 }%{m68040:-DCPU=MC68040 }%{m68020-40:-DCPU=MC68020 }%{m68302:-DCPU=MC68000 }%{m68332:-DCPU=CPU32 } \
-%{!mc68000:%{!m68000:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68302:%{!m68332:%(cpp_subtarget_cpu_default) }}}}}}}}}} \
-"
-
-#define DBX_DEBUGGING_INFO
-#undef SDB_DEBUGGING_INFO
-
-/* These are the official values from WRS.  */
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "char"
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 8
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "long int"
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-/* VxWorks does all the library stuff itself.  */
-
-#define LIB_SPEC ""
-
-/* Provide required defaults for linker -e. */
- 
-#define LINK_SPEC "%{!nostdlib:%{!r*:%{!e*:-e start}}}"
-
-/* VxWorks provides the functionality of crt0.o and friends itself.  */
-
-#define STARTFILE_SPEC ""
-
-/* Every structure or union's size must be a multiple of 2 bytes.  */
-
-#define STRUCTURE_SIZE_BOUNDARY 16
-
-/* Allow folding division by zero.  */
-#define REAL_INFINITY
-
-/* GCC is the primary compiler for VxWorks, so we don't need this.  */
-#undef PCC_STATIC_STRUCT_RETURN
diff --git a/gcc/config/m68k/x-alloca-c b/gcc/config/m68k/x-alloca-c
deleted file mode 100755
index 3375d42..0000000
--- a/gcc/config/m68k/x-alloca-c
+++ /dev/null
@@ -1 +0,0 @@
-ALLOCA=alloca.o
diff --git a/gcc/config/m68k/x-amix b/gcc/config/m68k/x-amix
deleted file mode 100755
index 6ec4f63..0000000
--- a/gcc/config/m68k/x-amix
+++ /dev/null
@@ -1,27 +0,0 @@
-# Makefile configuration for Commodore Amiga running SVR4.
-# (configure amiga-amix)
-
-# The Amiga ships with gcc installed, so use it as the default CC.
-
-CC = /usr/public/bin/gcc
-
-# The AT&T compiler is still available in /usr/ccs/bin/cc and should
-# be used to compile the things that should not be compiled with gcc.
-
-OLDCC = /usr/ccs/bin/cc
-
-# Link the executables with -ansi to get ANSI floating point ranges.
-# Otherwise the values returned on overflow or underflow will be wrong.
-# NOTE: some early releases of Amiga Unix contained a bug in ptod.o
-# that prevents the correct values being returned from strtod/atof, even
-# when linked with -ansi.  Sometimes -static will fix this since at least
-# one version had a fixed copy in the static libc.a.
-
-LDFLAGS = -ansi
-
-# The manual pages go in /usr/man/1l (section 1, local) without any filename
-# extension.  The man command will automatically create the /usr/catman/1l
-# entry.
-
-mandir = /usr/man/1l
-manext =
diff --git a/gcc/config/m68k/x-apollo68 b/gcc/config/m68k/x-apollo68
deleted file mode 100755
index 4c809f9..0000000
--- a/gcc/config/m68k/x-apollo68
+++ /dev/null
@@ -1,15 +0,0 @@
-# x-apollo68 -- 680x0 based Apollos as host system
-
-# vasta@apollo.com says this is how to compile on an Apollo (SR10.x).
-# Use a Berkeley environment.
-CC=cc -g -A nansi -A cpu,3000 -A runtype,bsd4.3 -A systype,any -DSHORT_ENUM_BUG
-OLDCC=cc -g -A nansi -A cpu,3000 -A runtype,bsd4.3 -A systype,any -DSHORT_ENUM_BUG
-
-# This used to redefine CFLAGS and LIBGCC2_CFLAGS to eliminate the unsupported
-# -g flag from both macros.  This gives an undebuggable stage1 compiler which
-# is bad, and it also does the wrong thing if we are cross compiling to a
-# target which does support debugging.  There is currently no way to avoid
-# the -g option that doesn't break something else.
-
-# Apollo does not have B option.
-TAROUTOPTS=xpf
diff --git a/gcc/config/m68k/x-apollo68v b/gcc/config/m68k/x-apollo68v
deleted file mode 100755
index ccb76c1..0000000
--- a/gcc/config/m68k/x-apollo68v
+++ /dev/null
@@ -1,5 +0,0 @@
-# vasta@apollo.com says this is how to compile on an Apollo (SR10.x).
-# Use a Berkeley environment.
-CC=cc -g -A nansi -A cpu,3000 -A runtype,any -A systype,any -DSHORT_ENUM_BUG -DUSG -U__STDC__
-OLDCC=cc -g -A nansi -A cpu,3000 -A runtype,bsd4.3 -A systype,any -DSHORT_ENUM_BUG -DUSG -U__STDC__
-
diff --git a/gcc/config/m68k/x-ccur b/gcc/config/m68k/x-ccur
deleted file mode 100755
index 0f94e9d..0000000
--- a/gcc/config/m68k/x-ccur
+++ /dev/null
@@ -1,3 +0,0 @@
-# Specify the jobs library when building in the ATT universe. 
-CLIB = -ljobs
-X_CFLAGS = -O0 -DSHORT_ENUM_BUG -Dregister=
diff --git a/gcc/config/m68k/x-crds b/gcc/config/m68k/x-crds
deleted file mode 100755
index 172909c..0000000
--- a/gcc/config/m68k/x-crds
+++ /dev/null
@@ -1,7 +0,0 @@
-CC = cc -Wx,-X23
-
-# The following line might be necessary as well or instead of the above.
-# If you find out that it is necessary,
-# or if you find out that it is not necessary,
-# please inform bug-gcc@prep.ai.mit.edu.
-# ALLOCA = alloca.o
diff --git a/gcc/config/m68k/x-dpx2 b/gcc/config/m68k/x-dpx2
deleted file mode 100755
index a4a8c1b..0000000
--- a/gcc/config/m68k/x-dpx2
+++ /dev/null
@@ -1,16 +0,0 @@
-# need this when using cc
-ALLOCA = alloca.o
-# avoid lossage assembling alloca.
-ALLOCA_FLAGS=-S
-ALLOCA_FINISH = $(AS) -o alloca.o alloca.s
-# be sure not to confuse ./as with /bin/as
-AS=`if [ x$(OLDCC) = x$(CC) ] ; then echo /bin/as; else echo $(GAS); fi`
-GAS = gas
-#
-# as of gcc-2.2.1 gcc -g produces too many .stabd's for /bin/ld
-# to link cc1plus, so use -g with /bin/cc, but -O with gcc
-CFLAGS=`if [ x$(OLDCC) = x$(CC) ] ; then echo -g; else echo -O; fi`
-#
-CLIB=-lmalloc -lld -lm
-# tell CC whether we are a 200 or 300
-X_CFLAGS=-D_POSIX_SOURCE -D_XOPEN_SOURCE -D_BULL_SOURCE -D__DPX2__ `if [ -d /makesys/kernel/cf/ncl_mr ]; then echo -Dncl_mr=1; else echo -Dncl_el; fi`
diff --git a/gcc/config/m68k/x-hp2bsd b/gcc/config/m68k/x-hp2bsd
deleted file mode 100755
index 7dd651c..0000000
--- a/gcc/config/m68k/x-hp2bsd
+++ /dev/null
@@ -1,4 +0,0 @@
-# Make assignments for compilation for hp200 running 4.3bsd
-CC=gcc
-OLDCC=oldcc
-# You must have a previous version of gcc for bootstrapping
diff --git a/gcc/config/m68k/x-hp320 b/gcc/config/m68k/x-hp320
deleted file mode 100755
index 46f68e6..0000000
--- a/gcc/config/m68k/x-hp320
+++ /dev/null
@@ -1,17 +0,0 @@
-# Make assignments for compilation on HPUX with their C compiler.
-CC=cc -Wc,-Nw2000 -Wc,-Ns2000 -Wc,-Ne700 -Wc,-Np300
-OLDCC=cc -Wc,-Nw2000 -Wc,-Ns2000 -Wc,-Ne700 -Wc,-Np300
-ALLOCA=alloca.o
-# B option not supported on hpux.
-TAROUTOPTS = xpf
-
-# For CCLIBFLAGS you might want to specify the switch that
-# forces only 68000 instructions to be used.
-
-# Version 5 of HPUX had a compiler bug that made it crash with -g.
-# You must set CFLAGS to empty on version 5.
-
-# You must get alloca.c from GNU Emacs.
-
-# So putenv and other functions get seen by fixproto.
-FIXPROTO_DEFINES = -D_HPUX_SOURCE
diff --git a/gcc/config/m68k/x-hp320g b/gcc/config/m68k/x-hp320g
deleted file mode 100755
index 38f201e..0000000
--- a/gcc/config/m68k/x-hp320g
+++ /dev/null
@@ -1,17 +0,0 @@
-# Make assignments for compilation on HPUX with their C compiler.
-CC=cc -Wc,-Nw2000 -Wc,-Ns2000 -Wc,-Ne700 -Wc,-Np300
-OLDCC=cc -Wc,-Nw2000 -Wc,-Ns2000 -Wc,-Ne700 -Wc,-Np300
-ALLOCA=alloca.o
-# B option not supported on hpux.
-TAROUTOPTS = xpf
-
-# For CCLIBFLAGS you might want to specify the switch that
-# forces only 68000 instructions to be used.
-
-X_CFLAGS= -I../hp-include
-
-# Version 5 of HPUX had a compiler bug that made it crash with -g.
-# You must set CFLAGS to empty on version 5.
-
-# So putenv and other functions get seen by fixproto.
-FIXPROTO_DEFINES = -D_HPUX_SOURCE
diff --git a/gcc/config/m68k/x-hp3bsd44 b/gcc/config/m68k/x-hp3bsd44
deleted file mode 100755
index b8dffd0..0000000
--- a/gcc/config/m68k/x-hp3bsd44
+++ /dev/null
@@ -1 +0,0 @@
-USER_H =  $(EXTRA_HEADERS) $(LANG_EXTRA_HEADERS)
diff --git a/gcc/config/m68k/x-mot3300 b/gcc/config/m68k/x-mot3300
deleted file mode 100755
index 3d7e3c3..0000000
--- a/gcc/config/m68k/x-mot3300
+++ /dev/null
@@ -1,15 +0,0 @@
-ALLOCA=alloca.o
-
-# This disables the long/short jump optimization.
-# I use sysV68 R3V7.1 RM04 (phdm@info.ucl.ac.be)
-# Since ss-950318, with jump optimization enabled, "as" issues a warning
-# when assembling combine.s :
-#   aline nnnnn : Warning: Table overflow: some optimizations lost (SDIs)
-# but later "ld" complains with
-#   ld: relocation entry found for non-relocatable symbol in combine.o
-# and the produced "cc1" fails with SIGSEGV
-# Another possible fix would be to split combine.c.
-# Since ss-961013, the same happens for expr.c compiled by gcc, but not by cc;
-# and for cp/decl.c; aren't those files too big ?
-# With egcs-970910, this also happens for f/expr.o and f/stb.o
-XCFLAGS=`case $@ in combine.o|expr.o|decl.o|f/expr.o|f/stb.o) echo -Wa,-j;;esac`
diff --git a/gcc/config/m68k/x-mot3300-gas b/gcc/config/m68k/x-mot3300-gas
deleted file mode 100755
index cf27977..0000000
--- a/gcc/config/m68k/x-mot3300-gas
+++ /dev/null
@@ -1,12 +0,0 @@
-ALLOCA=alloca.o
-
-# This disables the long/short jump optimization.
-# I use sysV68 R3V7.1 RM04 (phdm@info.ucl.ac.be)
-# Since ss-950318, with jump optimization enabled, "as" issues a warning
-# when assembling combine.s :
-#   aline nnnnn : Warning: Table overflow: some optimizations lost (SDIs)
-# but later "ld" complains with
-#   ld: relocation entry found for non-relocatable symbol in combine.o
-# and the produced "cc1" fails with SIGSEGV
-# Another possible fix would be to split combine.c.
-XCFLAGS=`if [ x$@ = xcombine.o -a "${CC}" = "${OLDCC}" ]; then echo -Wa,-j; fi`
diff --git a/gcc/config/m68k/x-next b/gcc/config/m68k/x-next
deleted file mode 100755
index f1a9836..0000000
--- a/gcc/config/m68k/x-next
+++ /dev/null
@@ -1,13 +0,0 @@
-# Make assignments for compiling on NeXT with their compiler version.
-CC=cc -traditional-cpp
-OLDCC=CC -traditional-cpp
-
-# Specify other dirs of system header files to be fixed.
-OTHER_FIXINCLUDES_DIRS= /LocalDeveloper/Headers
-
-# <limits.h> is sometimes in /usr/include/ansi/limits.h.
-LIMITS_H_TEST = [ -f $(SYSTEM_HEADER_DIR)/limits.h -o -f $(SYSTEM_HEADER_DIR)/ansi/limits.h ]
-
-# f771 is so big, we need to tell linker on m68k-next-nextstep* to
-# make enough room for it.
-BOOT_LDFLAGS=-segaddr __DATA 6000000
diff --git a/gcc/config/m68k/x-sun3 b/gcc/config/m68k/x-sun3
deleted file mode 100755
index b3ee2ce..0000000
--- a/gcc/config/m68k/x-sun3
+++ /dev/null
@@ -1 +0,0 @@
-INSTALL_FLOAT_H =
diff --git a/gcc/config/m68k/x-tower b/gcc/config/m68k/x-tower
deleted file mode 100755
index 995e72b..0000000
--- a/gcc/config/m68k/x-tower
+++ /dev/null
@@ -1,9 +0,0 @@
-# On the NCR Tower 32 running SVR3, says ra@intsys.no :
-# Do *not* enable optimization in CFLAGS when using the native cc, because:
-# a) The optimizer seems to loop when invoked with -O2.
-# b) The -O1 level does stack/frame pointer optimizations that make the
-#    assembler alloca in libPW.a fail, and the C alloca eats *lots* of memory.
-# c) gcc will eventually be recompiled with itself, so all this doesn't matter.
-X_CFLAGS = -O0
-CCLIBFLAGS = -O2
-CLIB = -lmalloc -lPW
diff --git a/gcc/config/m68k/xm-3b1.h b/gcc/config/m68k/xm-3b1.h
deleted file mode 100755
index 035004f..0000000
--- a/gcc/config/m68k/xm-3b1.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/* Override part of the obstack macros.  */
-
-#define __PTR_TO_INT(P) ((int)(P))
-#define __INT_TO_PTR(P) ((char *)(P))
diff --git a/gcc/config/m68k/xm-altos3068.h b/gcc/config/m68k/xm-altos3068.h
deleted file mode 100755
index f540924..0000000
--- a/gcc/config/m68k/xm-altos3068.h
+++ /dev/null
@@ -1,3 +0,0 @@
-#define USG
-
-#include "m68k/xm-m68k.h"
diff --git a/gcc/config/m68k/xm-amix.h b/gcc/config/m68k/xm-amix.h
deleted file mode 100755
index c28ed78..0000000
--- a/gcc/config/m68k/xm-amix.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Definitions of host machine for GNU compiler.
-   Commodore Amiga A3000UX version.
-   Copyright (C) 1991, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m68k/xm-m68kv.h"	/* Use the System V flavor of m68k host */
-
-#define rindex strrchr
-#define index strchr
-
-/* Define FULL_PROTOTYPES for protoize.c, to get <unistd.h> included.
-   We need this file for things like R_OK, not necessarily prototypes. */
-
-#define FULL_PROTOTYPES
-
-#if defined (__GNUC__) && __GNUC__ == 1
-#define alloca __builtin_alloca
-#endif
-
-#if 0 /* I don't want individual ports to be inconsistent about this.
-	 I regard fancy_abort as a half-solution and not the right way
-	 to do things. --rms.  */
-/* The m88k and mips ports make use of fancy_abort to give possibly helpful
-   abort information rather than just dumping core.  They do it in their
-   tm-* files.  It seems more logical that this is a characteristic of
-   the host machine and not the target machine, so we do it here. */
-
-#define abort fancy_abort	/* give possibly helpful abort info */
-#endif
diff --git a/gcc/config/m68k/xm-atari.h b/gcc/config/m68k/xm-atari.h
deleted file mode 100755
index 59f4664..0000000
--- a/gcc/config/m68k/xm-atari.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* Add HZ define if missing */
-
-#ifndef HZ
-#define HZ 100			/* System clock */
-#endif
diff --git a/gcc/config/m68k/xm-aux.h b/gcc/config/m68k/xm-aux.h
deleted file mode 100755
index 5ac1f46..0000000
--- a/gcc/config/m68k/xm-aux.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef USG
-#define USG
-#endif
-
-#ifndef AUX
-#define AUX
-#endif
-
-#include "m68k/xm-m68k.h"
diff --git a/gcc/config/m68k/xm-crds.h b/gcc/config/m68k/xm-crds.h
deleted file mode 100755
index 2bf1bdb..0000000
--- a/gcc/config/m68k/xm-crds.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Avoid conflict with C library by changing name of this symbol.  */
-#define gettime gcc_gettime
-
-/* Override part of the obstack macros.  */
-
-#define __PTR_TO_INT(P) ((int)(P))
-#define __INT_TO_PTR(P) ((char *)(P))
diff --git a/gcc/config/m68k/xm-hp320.h b/gcc/config/m68k/xm-hp320.h
deleted file mode 100755
index f3009a6..0000000
--- a/gcc/config/m68k/xm-hp320.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* USG is needed to prevent trying to use getrusage and getwd.  */
-#define USG
-
-#include "m68k/xm-m68k.h"
-
-/* If compiling with HPUX compiler, we are probably using alloca.c,
-   so help it work right.  */
-#ifndef __GNUC__
-#define USE_C_ALLOCA
-#endif
-
-/* Don't try to use sys_siglist.  */
-#define NO_SYS_SIGLIST
diff --git a/gcc/config/m68k/xm-linux.h b/gcc/config/m68k/xm-linux.h
deleted file mode 100755
index bfac3ae..0000000
--- a/gcc/config/m68k/xm-linux.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/* Configuration for GCC for Motorola m68k running Linux-based GNU systems. */
-
-#include <m68k/xm-m68k.h>
-#include <xm-linux.h>
diff --git a/gcc/config/m68k/xm-lynx.h b/gcc/config/m68k/xm-lynx.h
deleted file mode 100755
index 78762b3..0000000
--- a/gcc/config/m68k/xm-lynx.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Configuration for GNU C-compiler for all platforms running LynxOS.
-   Copyright (C) 1993, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <xm-lynx.h>
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_WORDS_BIG_ENDIAN 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-
-#include "tm.h"
diff --git a/gcc/config/m68k/xm-m68k.h b/gcc/config/m68k/xm-m68k.h
deleted file mode 100755
index 757c9af..0000000
--- a/gcc/config/m68k/xm-m68k.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Configuration for GNU C-compiler for Motorola 68000 family.
-   Copyright (C) 1987, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_WORDS_BIG_ENDIAN
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
diff --git a/gcc/config/m68k/xm-m68kv.h b/gcc/config/m68k/xm-m68kv.h
deleted file mode 100755
index d0931f0..0000000
--- a/gcc/config/m68k/xm-m68kv.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Host environment for 68000's running System V.  */
-
-#include "m68k/xm-m68k.h"
-
-#define USG
-
-#ifndef __GNUC__
-#define USE_C_ALLOCA
-#endif
diff --git a/gcc/config/m68k/xm-mot3300.h b/gcc/config/m68k/xm-mot3300.h
deleted file mode 100755
index ea3b558..0000000
--- a/gcc/config/m68k/xm-mot3300.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Configuration for GNU C-compiler for Motorola 68000 family.
-   SysV68 Motorola 3300 Delta Series
-   Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#define USG 1
-
-/* do not use alloca from -lPW with cc, because function epilogues use %sp */
-#ifndef __GNUC__
-#ifdef __STDC__
-extern void *alloca ();
-#else
-extern char *alloca ();
-#endif
-#endif
-
-/* Override part of the obstack macros.  */
-
-#define __PTR_TO_INT(P) ((int)(P))
-#define __INT_TO_PTR(P) ((char *)(P))
-
-/* We need POSIX/XOPEN symbols; otherwise make check will fail.  */
-#define ADD_MISSING_POSIX 1
-#define ADD_MISSING_XOPEN 1
diff --git a/gcc/config/m68k/xm-netbsd.h b/gcc/config/m68k/xm-netbsd.h
deleted file mode 100755
index 27a33cd..0000000
--- a/gcc/config/m68k/xm-netbsd.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/* Configuration for GCC for Motorola 68k running NetBSD as host.  */
-
-#include <m68k/xm-m68k.h>
-#include <xm-netbsd.h>
diff --git a/gcc/config/m68k/xm-next.h b/gcc/config/m68k/xm-next.h
deleted file mode 100755
index e0b53f2..0000000
--- a/gcc/config/m68k/xm-next.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/* malloc does better with chunks the size of a page.  */ 
-
-#define OBSTACK_CHUNK_SIZE (getpagesize ())
diff --git a/gcc/config/m68k/xm-plexus.h b/gcc/config/m68k/xm-plexus.h
deleted file mode 100755
index 8498198..0000000
--- a/gcc/config/m68k/xm-plexus.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Host environment for 68000's running System V.  */
-
-#ifndef _SIZE_T_
-typedef int size_t;
-#define _SIZE_T_
-#endif
diff --git a/gcc/config/m68k/xm-sun3.h b/gcc/config/m68k/xm-sun3.h
deleted file mode 100755
index eafe716..0000000
--- a/gcc/config/m68k/xm-sun3.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* Configuration for GCC for Motorola m68k on sun3. */
-
-#define HAVE_POPEN
-
-#include "m68k/xm-m68k.h"
diff --git a/gcc/config/m68k/xm-tower.h b/gcc/config/m68k/xm-tower.h
deleted file mode 100755
index fcb456f..0000000
--- a/gcc/config/m68k/xm-tower.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#include "m68k/xm-m68k.h"
-#include "xm-svr3.h"
-
-#define HAVE_VPRINTF
diff --git a/gcc/config/m88k/dgux.h b/gcc/config/m88k/dgux.h
deleted file mode 100755
index 186735b..0000000
--- a/gcc/config/m88k/dgux.h
+++ /dev/null
@@ -1,305 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Motorola m88100 running DG/UX.
-   Copyright (C) 1988, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@mcc.com)
-   Currently maintained by (gcc@dg-rtp.dg.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* You're not seeing double!  To transition to dwarf debugging, both are
-   supported.  The option -msvr4 specifies elf.  With these combinations, 
-   -g means dwarf.  */
-/* DWARF_DEBUGGING_INFO defined in svr4.h.  */
-#define SDB_DEBUGGING_INFO
-#define PREFERRED_DEBUGGING_TYPE \
-  (TARGET_SVR4 ? DWARF_DEBUG : SDB_DEBUG)
-
-#ifndef VERSION_INFO2
-#define VERSION_INFO2   "$Revision: 1.54 $"
-#endif
-#ifndef NO_BUGS
-#define AS_BUG_IMMEDIATE_LABEL
-/* The DG/UX 4.30 assembler doesn't accept the symbol `fcr63'.  */
-#define AS_BUG_FLDCR
-#endif
-
-#include "svr4.h"
-#include "m88k/m88k.h"
-
-/* Augment TARGET_SWITCHES with the MXDB options.  */
-#define MASK_STANDARD		0x40000000 /* Retain standard information */
-#define MASK_NOLEGEND		0x20000000 /* Discard legend information */
-#define MASK_EXTERNAL_LEGEND	0x10000000 /* Make external legends */
-
-#define TARGET_STANDARD		  (target_flags & MASK_STANDARD)
-#define TARGET_NOLEGEND		  (target_flags & MASK_NOLEGEND)
-#define TARGET_EXTERNAL_LEGEND	  (target_flags & MASK_EXTERNAL_LEGEND)
-
-#undef  SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-    { "standard",			 MASK_STANDARD }, \
-    { "legend",				-MASK_NOLEGEND }, \
-    { "no-legend",			 MASK_NOLEGEND }, \
-    { "external-legend",		 MASK_EXTERNAL_LEGEND }, \
-    /* the following is used only in the *_SPEC's */ \
-    { "keep-coff",			 0 },
-
-/* Default switches */
-#undef	TARGET_DEFAULT
-#define TARGET_DEFAULT	(MASK_CHECK_ZERO_DIV	 | \
-			 MASK_OCS_DEBUG_INFO	 | \
-			 MASK_OCS_FRAME_POSITION | \
-			 MASK_STANDARD		 | \
-			 MASK_SVR4)
-#undef	CPU_DEFAULT
-#define CPU_DEFAULT MASK_88000
-
-/* Macros to be automatically defined.  __svr4__ is our extension.
-   __CLASSIFY_TYPE__ is used in the <varargs.h> and <stdarg.h> header
-   files with DG/UX revision 5.40 and later.  This allows GNU CC to
-   operate without installing the header files.  */
-
-#undef	CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dm88000 -Dm88k -Dunix -DDGUX -D__CLASSIFY_TYPE__=2\
-   -D__svr4__ -Asystem(unix) -Acpu(m88k) -Amachine(m88k)"
-
-/* If -m88100 is in effect, add -Dm88100; similarly for -m88110.
-   Here, the CPU_DEFAULT is assumed to be -m88000.  If not -ansi,
-   -traditional, or restricting include files to one specific source
-   target, specify full DG/UX features.  */
-#undef	CPP_SPEC
-#define	CPP_SPEC "%(cpp_cpu) %{msvr3:-D_M88KBCS_TARGET} %{!msvr3:-D_DGUX_TARGET}"
-
-/* Assembler support (-V, silicon filter, legends for mxdb).  */
-#undef	ASM_SPEC
-#define ASM_SPEC "%{pipe:%{!.s: - }\
-		   %{!msvr3:%{!m88110:-KV3 }%{m88110:-KV04.00 }}}\
-		  %(asm_cpu)"
-
-/* Override svr4.h.  */
-#undef	ASM_FINAL_SPEC
-#undef	STARTFILE_SPEC
-
-/* Linker and library spec's.
-   -msvr4 is the default if -msvr3 is not specified.
-   -static, -shared, -symbolic, -h* and -z* access AT&T V.4 link options.
-   -svr4 instructs gcc to place /usr/lib/values-X[cat].o on the link line.
-   -msvr3 indicates linking done in a COFF environment and the link
-   script is added to the link line.  In all environments, the first
-   and last objects are crtbegin.o (or bcscrtbegin.o) and crtend.o.
-   When the -G link option is used (-shared and -symbolic) a final
-   link is not being done.  */
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s"
-#undef	LIB_SPEC
-#define LIB_SPEC "%{!msvr3:%{!shared:-lstaticdgc}} %{!shared:%{!symbolic:-lc}}"
-#undef	LINK_SPEC
-#define LINK_SPEC "%{z*} %{h*} %{v:-V} \
-		   %{static:-dn -Bstatic} \
-		   %{shared:-G -dy} \
-		   %{symbolic:-Bsymbolic -G -dy} \
-		   %{pg:-L/usr/lib/libp}%{p:-L/usr/lib/libp}"
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC "%(startfile_default)"
-
-
-/* This macro defines names of additional specifications to put in the specs
-   that can be used in various specifications like CC1_SPEC.  Its definition
-   is an initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   specification name, and a string constant that used by the GNU CC driver
-   program.
-
-   Do not define this macro if it does not need to do anything.  */
-
-#define EXTRA_SPECS                                     \
-  { "cpp_cpu",          CPP_CPU_SPEC },                 \
-  { "asm_cpu",          ASM_CPU_SPEC },                 \
-  { "startfile_default", STARTFILE_DEFAULT_SPEC },  \
-  { "startfile_crtbegin", STARTFILE_CRTBEGIN_SPEC }
-   
-/* Keep this left justified, no white space is allowed between
-   the arguments to the -Wc option */
-#define ASM_CPU_SPEC "\
-		  %{v:-V}\
-		  %{g:\
-%{mno-legend:-Wc,off}\
-%{!mno-legend:-Wc,-fix-bb,-s\"%i\"\
-%{traditional:,-lc}\
-%{!traditional:,-lansi-c}\
-%{mstandard:,-keep-std}\
-%{mexternal-legend:,-external}\
-%{mocs-frame-position:,-ocs}}}"
-
-#define CPP_CPU_SPEC "\
-                  %{!m88000:%{!m88100:%{m88110:-D__m88110__}}} \
-		  %{!m88000:%{!m88110:%{m88100:-D__m88100__}}} \
-		  %{!ansi:%{!traditional:-D__OPEN_NAMESPACE__}}"
-
-#define STARTFILE_DEFAULT_SPEC "\
-                        %{!shared:%{!symbolic:%{pg:gcrt0.o%s} \
-			 %{!pg:%{p:/lib/mcrt0.o}%{!p:/lib/crt0.o}} \
-			  %(startfile_crtbegin) \
-			 %{svr4:%{ansi:/lib/values-Xc.o} \
-			  %{!ansi:%{traditional:/lib/values-Xt.o} \
-			   %{!traditional:/usr/lib/values-Xa.o}}}}}"
-
-#define STARTFILE_CRTBEGIN_SPEC "\
-			 %{msvr3:m88kdgux.ld%s bcscrtbegin.o%s} \
-			 %{!msvr3:crtbegin.o%s}"
-
-#undef	GPLUSPLUS_INCLUDE_DIR
-#define GPLUSPLUS_INCLUDE_DIR "/usr/opt/g++/lib/g++-include"
-
-/* Fast DG/UX version of profiler that does not require lots of
-   registers to be stored.  */
-#undef	FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
-  output_function_profiler (FILE, LABELNO, "gcc.mcount", 0)
-
-/* Output the legend info for mxdb when debugging except if standard
-   debugging information only is explicitly requested.  */
-#undef  ASM_FIRST_LINE
-#define ASM_FIRST_LINE(FILE)						\
-  do {									\
-    if (TARGET_SVR4)							\
-      {									\
-	if (TARGET_88110)						\
-	  fprintf (FILE, "\t%s\t \"%s\"\n", VERSION_ASM_OP, "04.00");   \
-	else								\
-	  fprintf (FILE, "\t%s\t \"%s\"\n", VERSION_ASM_OP, "03.00");   \
-      }									\
-    if (write_symbols != NO_DEBUG && !TARGET_NOLEGEND)			\
-      {									\
-	fprintf (FILE, ";legend_info -fix-bb -h\"gcc-%s\" -s\"%s\"",	\
-		 VERSION_STRING, main_input_filename);			\
-	fputs (flag_traditional ? " -lc" : " -lansi-c", FILE);		\
-	if (TARGET_STANDARD)						\
-	  fputs (" -keep-std", FILE);					\
-	if (TARGET_EXTERNAL_LEGEND)					\
-	  fputs (" -external", FILE);					\
-	if (TARGET_OCS_FRAME_POSITION)					\
-	  fputs (" -ocs", FILE);					\
-	fputc ('\n', FILE);						\
-      }									\
-  } while (0)
-
-/* Override svr4.h.  */
-#undef PTRDIFF_TYPE
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-
-/* Override svr4.h and m88k.h except when compiling crtstuff.c.  These must
-   be constant strings when compiling crtstuff.c.  Otherwise, respect the
-   -mversion-STRING option used.  */
-#undef INIT_SECTION_PREAMBLE
-#undef INIT_SECTION_ASM_OP
-#undef FINI_SECTION_ASM_OP
-#undef CTORS_SECTION_ASM_OP
-#undef DTORS_SECTION_ASM_OP
-
-#if defined (CRT_BEGIN) || defined (CRT_END) || defined (L__main)
-/* routines to invoke global constructors and destructors are always COFF 
-   to enable linking mixed COFF and ELF objects */
-#define FINI_SECTION_ASM_OP ("section  .fini,\"x\"")
-#ifndef BCS
-#define INIT_SECTION_PREAMBLE asm ("\taddu\tr31,r31,0x20")
-#endif
-#undef	INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP ("section\t .init,\"x\"")
-#undef	CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP ("section\t .ctors,\"d\"")
-#undef	DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP ("section\t .dtors,\"d\"")
-#undef OBJECT_FORMAT_ELF
-#else
-#undef        INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP (TARGET_SVR4                      \
-                           ? "section\t .init,\"xa\""         \
-                           : "section\t .init,\"x\"")
-#undef        CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP (TARGET_SVR4                     \
-                            ? "section\t .ctors,\"aw\""       \
-                            : "section\t .ctors,\"d\"")
-#undef        DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP (TARGET_SVR4                     \
-                            ? "section\t .dtors,\"aw\""       \
-                            : "section\t .dtors,\"d\"")
-#endif /* crtstuff.c */
-
-/* The lists of global object constructors and global destructors are always
-   placed in the .ctors/.dtors sections.  This requires the use of a link
-   script if the COFF linker is used, but otherwise COFF and ELF objects
-   can be intermixed.  A COFF object will pad the section to 16 bytes with
-   zeros; and ELF object will not contain padding.  We deal with this by
-   putting a -1 marker at the begin and end of the list and ignoring zero
-   entries.  */
-
-/* Mark the end of the .ctors/.dtors sections with a -1.  */
-
-#define CTOR_LIST_BEGIN			\
-asm (CTORS_SECTION_ASM_OP);		\
-func_ptr __CTOR_LIST__[1] = { (func_ptr) (-1) }
-
-#define CTOR_LIST_END			\
-asm (CTORS_SECTION_ASM_OP);		\
-func_ptr __CTOR_END__[1] = { (func_ptr) (-1) }
-
-#define DTOR_LIST_BEGIN			\
-asm (DTORS_SECTION_ASM_OP);		\
-func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) }
-
-#define DTOR_LIST_END			\
-asm (DTORS_SECTION_ASM_OP);		\
-func_ptr __DTOR_END__[1] = { (func_ptr) (-1) }
-
-/* Walk the list ignoring NULL entries till we hit the terminating -1.  */
-#define DO_GLOBAL_CTORS_BODY				\
-  do {							\
-    int i;						\
-    for (i=1;(int)(__CTOR_LIST__[i]) != -1; i++)	\
-      if (((int *)__CTOR_LIST__)[i] != 0)		\
-	__CTOR_LIST__[i] ();				\
-  } while (0)					
-
-/* Walk the list looking for the terminating -1 that marks the end.
-   Go backward and ignore any NULL entries.  */
-#define DO_GLOBAL_DTORS_BODY				\
-  do {							\
-    int i;						\
-    for (i=1;(int)(__DTOR_LIST__[i]) != -1; i++);	\
-    for (i-=1;(int)(__DTOR_LIST__[i]) != -1; i--)	\
-      if (((int *)__DTOR_LIST__)[i] != 0)		\
-	__DTOR_LIST__[i] ();				\
-  } while (0)					
-
-/* The maximum alignment which the object file format can support.
-   page alignment would seem to be enough */
-#undef MAX_OFILE_ALIGNMENT
-#define MAX_OFILE_ALIGNMENT 0x1000
-
-/* Must use data section for relocatable constants when pic.  */
-#undef SELECT_RTX_SECTION
-#define SELECT_RTX_SECTION(MODE,RTX)            \
-{                                               \
-  if (flag_pic && symbolic_operand (RTX))       \
-    data_section ();                            \
-  else                                          \
-    const_section ();                           \
-}
diff --git a/gcc/config/m88k/dgux.ld b/gcc/config/m88k/dgux.ld
deleted file mode 100755
index cc5dc0f..0000000
--- a/gcc/config/m88k/dgux.ld
+++ /dev/null
@@ -1,48 +0,0 @@
-/* m88kdgux.ld - COFF linker directives for G++ on an AViiON
-
-   This file is part of GNU CC.
-   
-   GNU CC is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-   
-   GNU CC is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-   
-   You should have received a copy of the GNU General Public License
-   along with GNU CC; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.
-   
-   On The AViiON we start the output .text section somewhere after the
-   first 64kb (0x10000) of logical address space so that the first
-   64kb can be mapped out, thus catching references through null
-   pointers.  We actually start at 0x10200 (for efficiency).  Ideally,
-   we want the page offset of a given word of the .text (output)
-   section to be the same as its page offset in the actual (output)
-   linked core file so that paging of the .text section is efficient.
-   In order to do this we allow for up to 0x200 bytes of header stuff
-   in the output (linked) object file.
-   
-   For .data, the OCS says that regions with different "protections"
-   (i.e. read/write, read-only) should not share any 4 megabyte chunk
-   of the logical address space, so we start the .data segment at the
-   first (lowest) 4 MB boundary past the end of the .text segment.
-   
-   For some reason, you can't start right at the 4 MB boundary.  You
-   have to start at some distance past that.  The distance must be
-   equal to the distance from the start of the last 64 KB segment in
-   the (output) .text segment to the actual end of the (output) .text
-   segment.  */
-
-SECTIONS {
-  .text 0x10200 BLOCK(0x200) :
-    { *(.init) *(.initp) *(.finip) *(.text) *(.tdesc) }
-
-  GROUP BIND (((((ADDR(.text) + SIZEOF(.text) - 1) / 0x400000) + 1) * 0x400000) + ((ADDR(.text) + SIZEOF (.text)) % 0x10000)) :
-    { .data : { *(.data) *(.ctors) *(.dtors) }
-      .bss  : {} }
-}
diff --git a/gcc/config/m88k/dguxbcs.h b/gcc/config/m88k/dguxbcs.h
deleted file mode 100755
index 00ef9b3..0000000
--- a/gcc/config/m88k/dguxbcs.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Motorola m88100 running DG/UX.
-   Copyright (C) 1988, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@mcc.com)
-   Currently maintained by (gcc@dg-rtp.dg.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m88k/dgux.h"
-
-/* dgux.h builds an elf gcc which compiles elf objects by default.
-   dguxbcs.h builds a bcs gcc which compiles bcs objects by default.
-   The default can be overridden in either case with -msvr3 and -msvr4 */
-
-/* Default switches */
-#undef	TARGET_DEFAULT
-#define TARGET_DEFAULT	(MASK_CHECK_ZERO_DIV	 | \
-			 MASK_OCS_DEBUG_INFO	 | \
-			 MASK_OCS_FRAME_POSITION | \
-			 MASK_SVR3)
-
-/* Assembler support (-V, silicon filter, legends for mxdb).  */
-#undef	ASM_SPEC
-#define ASM_SPEC "%{pipe:%{!.s: - }\
-		   %{msvr4:%{!m88110:-KV3 }%{m88110:-KV04.00 }}}\
-		  %(asm_cpu)"
-
-/* If -m88100 is in effect, add -Dm88100; similarly for -m88110.
-   Here, the CPU_DEFAULT is assumed to be -m88000.  If not -ansi,
-   -traditional, or restricting include files to one specific source
-   target, specify full DG/UX features.  */
-#undef	CPP_SPEC
-#define	CPP_SPEC "%(cpp_cpu) 
-		  %{!msvr4:-D_M88KBCS_TARGET} %{msvr4:-D_DGUX_TARGET}"
-
-/* Linker and library spec's.
-   -msvr3 is the default if -msvr4 is not specified. */
-#undef	LIB_SPEC
-#define LIB_SPEC "%{msvr4:%{!shared:-lstaticdgc}} %{!shared:%{!symbolic:-lc}}"
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC "%(startfile_default)"
-
-#undef  STARTFILE_CRTBEGIN_SPEC
-#define STARTFILE_CRTBEGIN_SPEC "\
-			 %{!msvr4:m88kdgux.ld%s bcscrtbegin.o%s} \
-			 %{msvr4:crtbegin.o%s}"
diff --git a/gcc/config/m88k/dolph.h b/gcc/config/m88k/dolph.h
deleted file mode 100755
index bd77227..0000000
--- a/gcc/config/m88k/dolph.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Motorola m88100 running the Dolphin UNIX System V/88 Release 3.2,
-   Version 3.8/7.83 and 3.6/5.86
-   Copyright (C) 1992, 1993, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m88k/sysv3.h"
-
-#define SDB_ALLOW_FORWARD_REFERENCES
-#define SDB_ALLOW_UNKNOWN_REFERENCES
-
-/* Override m88k/sysv3.h */
-
-#undef	CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dm88000 -Dm88k -DOCS88 -DDOLPHIN -Dunix -DsysV88 -D__CLASSIFY_TYPE__=2 -Asystem(unix) -Asystem(svr3) -Acpu(m88k) -Amachine(m88k)" 
-
-/* 
-  If you want to detect dereferencing of NULL pointers, uncomment the
-  following two lines. Alternatively, edit the appropriate specs file.
-  
-  #undef LINK_SPEC
-  #define LINK_SPEC "gcc.ld%s"
-  
-  */
-
-#undef CPU_DEFAULT
-#define CPU_DEFAULT MASK_88000
diff --git a/gcc/config/m88k/dolphin.ld b/gcc/config/m88k/dolphin.ld
deleted file mode 100755
index ce5c8f0..0000000
--- a/gcc/config/m88k/dolphin.ld
+++ /dev/null
@@ -1,40 +0,0 @@
-/* COFF linker directives for the Dolphin Triton88 for GNU compiler.
-   Copyright (C) 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-   
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* This file does the following:
-
-    - Sets VIRTUAL addr of .text to 0x400200 
-      Sets FILE addr of .text to 0x200 (BLOCK directive)
-    - Depending on size of .text section rounds up to next
-      4 MG boundary, adds (size of .text and vaddr of .text) mod 64K
-      This is to handle sections larger than 4 MG.   */
-
-SECTIONS {
-  .text 0x400200 BLOCK (0x200):
-    { *(.init) *(.text) *(.rodata) *(.tdesc) *(.fini)}
-
-  GROUP BIND( (((SIZEOF(.text)+ADDR(.text)) / 0x400000 * 0x400000) + 0x400000) +
-    ((SIZEOF(.text) + ADDR(.text)) % 0x10000) ) :
-    {
-      .data : { }
-      .bss  : { }
-    }
-}
diff --git a/gcc/config/m88k/luna.h b/gcc/config/m88k/luna.h
deleted file mode 100755
index ab6dbde..0000000
--- a/gcc/config/m88k/luna.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Motorola m88100 running Omron Luna/88k.
-   Copyright (C) 1991, 1997 Free Software Foundation, Inc.
-   Contributed by Jeffrey Friedl (jfriedl@omron.co.jp)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* The Omron Luna/88k is MACH and uses BSD a.out, not COFF or ELF.  */
-#ifndef MACH
-#define MACH
-#endif
-#define DBX_DEBUGGING_INFO
-#define DEFAULT_GDB_EXTENSIONS 0
-
-#include "aoutos.h"
-#include "m88k/m88k.h"
-
-/* Identify the compiler.  */
-#undef  VERSION_INFO1
-#define VERSION_INFO1 "Omron Luna/88k, "
-
-/* Macros to be automatically defined.  */
-#undef	CPP_PREDEFINES
-#define CPP_PREDEFINES \
-    "-DMACH -Dm88k -Dunix -Dluna -Dluna88k -D__CLASSIFY_TYPE__=2 -Asystem(unix) -Asystem(mach) -Acpu(m88k) -Amachine(m88k)"
-
-/* If -m88000 is in effect, add -Dmc88000; similarly for -m88100 and -m88110.
-   However, reproduce the effect of -Dmc88100 previously in CPP_PREDEFINES.
-   Here, the CPU_DEFAULT is assumed to be -m88100.  */
-#undef	CPP_SPEC
-#define	CPP_SPEC "%{m88000:-D__mc88000__} \
-		  %{!m88000:%{m88100:%{m88110:-D__mc88000__}}} \
-		  %{!m88000:%{!m88100:%{m88110:-D__mc88110__}}} \
-		  %{!m88000:%{!m88110:%{!ansi:%{traditional:-Dmc88100}} \
-				      -D__mc88100__ -D__mc88100}}"
-
-/* Specify extra dir to search for include files.  */
-#undef	SYSTEM_INCLUDE_DIR
-#define SYSTEM_INCLUDE_DIR "/usr/mach/include"
-
-/* For the Omron Luna/88k, a float function returns a double in traditional
-   mode (and a float in ansi mode).  */
-#undef TRADITIONAL_RETURN_FLOAT
diff --git a/gcc/config/m88k/m88k-aout.h b/gcc/config/m88k/m88k-aout.h
deleted file mode 100755
index 90f3fe7..0000000
--- a/gcc/config/m88k/m88k-aout.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Definitions for "naked" Motorola 88k using a.out object format files
-   and stabs debugging info.
-
-   Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef SDB_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-
-#include "m88k/m88k.h"
-#include "aoutos.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dm88000 -Dm88k -Acpu(m88k) -Amachine(m88k)"
-
-/* end of m88k-aout.h */
diff --git a/gcc/config/m88k/m88k-coff.h b/gcc/config/m88k/m88k-coff.h
deleted file mode 100755
index d32e1d9..0000000
--- a/gcc/config/m88k/m88k-coff.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Definitions for "naked" Motorola 88k using coff object format files
-   and coff debugging info.
-
-   Copyright (C) 1994, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m88k/m88k.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dm88000 -Dm88k -Acpu(m88k) -Amachine(m88k)"
-
-#define SDB_DEBUGGING_INFO
-
-/* Output DBX (stabs) debugging information if using -gstabs.  */
-
-#include "dbxcoff.h"
-
-/* end of m88k-coff.h */
diff --git a/gcc/config/m88k/m88k-move.sh b/gcc/config/m88k/m88k-move.sh
deleted file mode 100755
index 5e757bd..0000000
--- a/gcc/config/m88k/m88k-move.sh
+++ /dev/null
@@ -1,306 +0,0 @@
-#!/bin/sh
-#
-#	If your shell doesn't support functions (true for some BSD users),
-#	you might try using GNU's bash.
-#
-#ident "@(#) m88k-move.sh 1-Sep-92"
-#
-#	This file provided by Data General, February 1990.
-#
-#	This script generates the necessary movstr library functions
-#	for the m88100.  These functions are called from the expansion
-#	of movstrsi.  There are eight modules created by this script,
-#	each with multiple entry points.  One module, moveSI64n
-#	implements a word aligned loop; the other modules, moveXINx
-#	implement a straight line copy of N bytes in mode XI.
-#
-#	By analysis of the best memcpy function, it can be determined
-#	what appear to be certain magic numbers.  For example, a
-#	memcpy of 13 bytes, where the pointers are determined at run
-#	time to be word aligned takes 28 cycles.  A call to
-#	__movstrQI13x13 also takes 28 cycles.  The break even point
-#	for a HImode copy is 38 bytes.  Just to be on the safe side,
-#	these are bumped to 16 and 48 respectively.
-#
-#	The smaller, odd-remainder modules are provided to help
-#	mitigate the overhead of copying the last bytes.
-#
-#	Changes to these functions should not be taken lightly if you
-#	want to be able to link programs built with older movstr
-#	parameters.
-#
-#.Revision History
-#
-#	 1-Sep-92   Stan Cox   Added moveDI96x, moveDI41x through moveDI47x.
-#	 2-Jan-92   Tom Wood   Renamed files to comply with SVR3 14 char limit.
-#	26-Oct-90   Tom Wood   Delete movstr.h; moved to out-m88k.c.
-#	17-Oct-90   Tom Wood   Files are named *.asm rather than *.s.
-#	11-Sep-90   Jeffrey Friedl
-#			On my BSD 4.3 awk and my GNU-awk, only the
-#			first character of an argument to -F is passed
-#			through, so I can't get this to work.
-#	 5-Sep-90   Ray Essick/Tom Wood  
-#			Added a -no-tdesc option.
-#	27-Aug-90   Vince Guarna/Tom Wood   
-#			Version 3 assembler syntax (-abi).
-#	16-Aug-90   Ron Guilmette
-#			Avoid problems on a Sparc.  The common
-#			denominator among shells seems to be '...\'
-#			rather than '...\\'.
-#	15-Aug-90   Ron Guilmette
-#			Avoid awk syntax errors on a Sun by not using
-#			the `!' operator.
-#	22-Feb-90   Tom Wood  	Created.
-#	20-Jun-90   Tom Wood	Emit file directives.
-#
-#.End]=--------------------------------------------------------------*/
-
-usage() {
-    echo "usage: $0 [ -abi ] [ -no-tdesc ]" 1>&2
-    exit 1
-}
-
-awk_flag="-F:";
-awk_begin="BEGIN { "
-ps=""; us="_"; tf="x"; la="@L"; fb="8"; nt="";
-do_file() {
-    echo "	file	 $1";
-}
-
-while [ $# -gt 0 ] ; do
-    case $1 in
-	-no-tdesc) awk_begin="$awk_begin no_tdesc=1;"
-	      nt=";";;
-	-abi) awk_begin="$awk_begin abi=1;"
-	      ps="#"; us=""; tf="a"; la=".L"; fb="16";
-	      do_file() {
-		echo '	version	 "03.00"';
-		echo "	file	 $1";
-	      };;
-	*) usage;;
-    esac
-    shift
-done
-
-rm -f move?I*[xn].s move?I*[xn].asm
-
-#.Implementation_continued[=-----------------------------------------------
-#
-#	This generates the word aligned loop.  The loop is entered
-#	from the callable entry points ___movstrSI64nN, where at
-#	least N bytes will be copied.  r2 is the destination pointer
-#	offset by 4, r3 is the source pointer offset by 4, r6 is the
-#	loop count.  Thus, the total bytes moved is 64 * r6 + N.  The
-#	first value is preloaded into r4 or r5 (r4 if N/4 is odd;
-#	r5 if N/4 is even).  Upon returning, r2 and r3 have been
-#	updated and may be used for the remainder bytes to move.
-#
-#	The code for this loop is generated by the awk program
-#	following.  Edit *it*, not what it generates!
-#
-#.End]=------------------------------------------------------------------*/
-
-gen_movstrN() {
-  awk $awk_flag "$awk_begin"'
-    if (abi) {
-      ps="#"; us=""; tf="a"; la=".L"; fb=16;
-    } else {
-      ps=""; us="_"; tf="x"; la="@L"; fb=8;
-    }
-  }
-  NR == 1 && NF == 4 {
-    mode = $1; suffix = $2; align = $3; count = $4;
-    ld = align; st = 0;
-
-    printf "; The following was calculated using awk.\n";
-    printf "\ttext\n";
-    printf "\talign\t%d\n", fb;
-    printf "%sloop%s%d:\n", la, mode, count * align;
-    printf "\taddu\t%sr3,%sr3,%d\n", ps, ps, count * align;
-    printf "\taddu\t%sr2,%sr2,%d\n", ps, ps, count * align;
-    printf "\tsubu\t%sr6,%sr6,1\n", ps, ps;
-    for (r = count + 1; r >= 1; r--) {
-      evenp = r % 2;
-      name = sprintf("__%smovstr%s%dn%d", us, mode, count * align, r * align);
-      if (r > 1) {
-        printf "\tglobal\t%s\n", name;
-        printf "%s:\n", name;
-      }
-      if (r > 2) {
-	printf "\tld%s\t%sr%d,%sr3,%d\n", suffix, ps, 4 + evenp, ps, ld;
-        printf "\tst%s\t%sr%d,%sr2,%d\n", suffix, ps, 5 - evenp, ps, st;
-      } else if (r == 2) {
-	printf "\tld%s\t%sr%d,%sr3,%d\n", suffix, ps, 4 + evenp, ps, ld;
-	printf "\tbcnd.n\t%sgt0,%sr6,%sloop%s%d\n", ps, ps, la, mode, count * align;
-        printf "\tst%s\t%sr%d,%sr2,%d\n", suffix, ps, 5 - evenp, ps, st;
-        printf "\tjmp.n\t%sr1\n", ps;
-      } else {
-        printf "\tst%s\t%sr%d,%sr2,%d\n", suffix, ps, 5 - evenp, ps, st;
-      }
-      ld += align; st += align;
-    }
-    if (!no_tdesc) {
-      printf "%send%s%d:\n", la, mode, count * align;
-      printf "\tsection\t.tdesc,\"%s\"\n", tf;
-      printf "\tword\t0x42,1,%sloop%s%d", la, mode, count * align;
-      printf ",%send%s%d\n", la, mode, count * align;
-      printf "\tword\t0x0100001f,0,1,0\n";
-      printf "\ttext\n";
-    }
-    printf "; End of awk generated code.\n";
-    exit;
-  }'
-}
-
-(do_file '"movstrSI64n.s"';
- echo 'SI::4:16' | gen_movstrN) > moveSI64n.asm
-
-#.Implementation_continued[=-----------------------------------------------
-#
-#	This generates the even-remainder, straight-line modules.
-#	The code is entered from the callable entry points
-#	___movstrXINxM, where exactly M bytes will be copied in XI
-#	mode.  r2 is the destination pointer, r3 is the source
-#	pointer, neither being offset.  The first value is preloaded
-#	into r4 or r5 (r4 if M-N/B is even; r5 if M-N/B is odd, where
-#	B is the mode size of XI).  Upon returning, r2 and r3 have not
-#	been changed.
-#
-#	The code for these cases is generated by the awk program
-#	following.  Edit *it*, not what it generates!
-#
-#.End]=------------------------------------------------------------------*/
-
-gen_movstrX0() {
-    awk $awk_flag "$awk_begin"'
-      if (abi) {
-	ps="#"; us=""; tf="a"; la=".L"; fb=16;
-      } else {
-	ps=""; us="_"; tf="x"; la="@L"; fb=8;
-      }
-    }
-    NR == 1 && NF == 4 {
-    mode = $1; suffix = $2; align = $3; bytes = $4;
-    ld = align; st = 0; count = bytes / align;
-    reg[0] = 4; if (align == 8) reg[1] = 6; else reg[1] = 5;
-    printf "; The following was calculated using awk.\n";
-    printf "\ttext\n";
-    printf "\talign\t%d\n", fb;
-    for (r = count; r >= 1; r--) {
-      evenp = r % 2;
-      name = sprintf("__%smovstr%s%dx%d", us, mode, count * align, r * align);
-      if (r > 1) {
-        printf "\tglobal\t%s\n", name;
-        printf "%s:\n", name;
-      }
-      if (r == 1)
-        printf "\tjmp.n\t%sr1\n", ps;
-      else
-        printf "\tld%s\t%sr%d,%sr3,%d\n", suffix, ps, reg[evenp], ps, ld;
-      printf "\tst%s\t%sr%d,%sr2,%d\n", suffix, ps, reg[1-evenp], ps, st;
-      ld += align; st += align;
-    }
-    if (!no_tdesc) {
-      printf "%send%s%dx:\n", la, mode, count * align;
-      printf "\tsection\t.tdesc,\"%s\"\n", tf;
-      printf "\tword\t0x42,1,__%smovstr%s%dx%d", us, mode, count * align, count * align;
-      printf ",%send%s%dx\n", la, mode, count * align;
-      printf "\tword\t0x0100001f,0,1,0\n";
-      printf "\ttext\n";
-    }
-    printf "; End of awk generated code.\n"
-    exit;
-  }'
-}
-
-(do_file '"movstrQI16x.s"';
- echo 'QI:.b:1:16' | gen_movstrX0) > moveQI16x.asm
-(do_file '"movstrHI48x.s"';
- echo 'HI:.h:2:48' | gen_movstrX0) > moveHI48x.asm
-(do_file '"movstrSI96x.s"';
- echo 'SI::4:96'   | gen_movstrX0) > moveSI96x.asm
-(do_file '"movstrDI96x.s"';
- echo 'DI:.d:8:96'   | gen_movstrX0) > moveDI96x.asm
-
-#.Implementation_continued[=-----------------------------------------------
-#
-#	This generates the odd-remainder, straight-line modules.  The
-#	interface is the same as that for the even-remainder modules.
-#
-#.End]=------------------------------------------------------------------*/
-
-gen_movstrXr() {
-    awk $awk_flag "$awk_begin"'
-      if (abi) {
-	ps="#"; us=""; tf="a"; la=".L"; fb=16;
-      } else {
-	ps=""; us="_"; tf="x"; la="@L"; fb=8;
-      }
-    }
-    NR == 1 && NF == 4 {
-    mode = $1; rem = $2; most = $3; count = $4;
-    suffix[1] = ".b"; suffix[2] = ".h"; suffix[4] = ""; suffix[8] = ".d";
-
-    prev = align = most;
-    ld = align; st = 0; total = count - rem - most;
-    evenp = int(total/align) % 2;
-    reg[0] = 4; if (align == 8) reg[1] = 6; else reg[1] = 5;
-    printf "; The following was calculated using awk.\n";
-    printf "\ttext\n";
-    printf "\talign\t%d\n", fb;
-    for (bytes = total; bytes >= 0; bytes -= align) {
-      if (bytes < align) {
-	if (bytes >= 4) align = 4;
-	else if (bytes >= 2) align = 2;
-	else align = 1;
-      }
-      name = sprintf("__%smovstr%s%dx%d", us, mode, total + most, bytes + most);
-      if (bytes > most) {
-        printf "\tglobal\t%s\n", name;
-        printf "%s:\n", name;
-      }
-      if (bytes == 0)
-	printf "\tjmp.n\t%sr1\n", ps;
-      else
-	printf "\tld%s\t%sr%d,%sr3,%d\n", suffix[align], ps, reg[evenp], ps, ld;
-      printf "\tst%s\t%sr%d,%sr2,%d\n", suffix[prev], ps, reg[1-evenp], ps, st;
-      ld += align; st += prev; prev = align;
-      evenp = 1 - evenp;
-    }
-    if (!no_tdesc) {
-      printf "%send%s%dx:\n", la, mode, total + most;
-      printf "\tsection\t.tdesc,\"%s\"\n", tf;
-      printf "\tword\t0x42,1,__%smovstr%s%dx%d", us, mode, total + most, total + most;
-      printf ",%send%s%dx\n", la, mode, total + most;
-      printf "\tword\t0x0100001f,0,1,0\n";
-      printf "\ttext\n";
-    }
-    printf "; End of awk generated code.\n"
-    exit;
-  }'
-}
-
-(do_file '"movstrDI47x.s"';
- echo 'DI:1:8:48' | gen_movstrXr) > moveDI47x.asm
-(do_file '"movstrDI46x.s"';
- echo 'DI:2:8:48' | gen_movstrXr) > moveDI46x.asm
-(do_file '"movstrDI45x.s"';
- echo 'DI:3:8:48' | gen_movstrXr) > moveDI45x.asm
-(do_file '"movstrDI44x.s"';
- echo 'DI:4:8:48' | gen_movstrXr) > moveDI44x.asm
-(do_file '"movstrDI43x.s"';
- echo 'DI:5:8:48' | gen_movstrXr) > moveDI43x.asm
-(do_file '"movstrDI42x.s"';
- echo 'DI:6:8:48' | gen_movstrXr) > moveDI42x.asm
-(do_file '"movstrDI41x.s"';
- echo 'DI:7:8:48' | gen_movstrXr) > moveDI41x.asm
-
-(do_file '"movstrSI47x.s"';
- echo 'SI:1:4:48' | gen_movstrXr) > moveSI47x.asm
-(do_file '"movstrSI46x.s"';
- echo 'SI:2:4:48' | gen_movstrXr) > moveSI46x.asm
-(do_file '"movstrSI45x.s"';
- echo 'SI:3:4:48' | gen_movstrXr) > moveSI45x.asm
-
-(do_file '"movstrHI15x.s"';
- echo 'HI:1:2:16' | gen_movstrXr) > moveHI15x.asm
diff --git a/gcc/config/m88k/m88k.c b/gcc/config/m88k/m88k.c
deleted file mode 100755
index ef743cb..0000000
--- a/gcc/config/m88k/m88k.c
+++ /dev/null
@@ -1,3162 +0,0 @@
-/* Subroutines for insn-output.c for Motorola 88000.
-   Copyright (C) 1988, 92, 93, 94, 95, 16, 1997 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@mcc.com)
-   Currently maintained by (gcc@dg-rtp.dg.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-
-#include <stdio.h>
-#include <sys/types.h>
-#include <time.h>
-#include <ctype.h>
-
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "tree.h"
-#include "c-tree.h"
-#include "expr.h"
-#include "flags.h"
-
-extern char *version_string;
-extern time_t time ();
-extern char *ctime ();
-extern int flag_traditional;
-extern FILE *asm_out_file;
-
-static char out_rcs_id[] = "$What: <@(#) m88k.c,v	1.8> $";
-static char tm_rcs_id [] = TM_RCS_ID;
-
-char *m88k_pound_sign = "";	/* Either # for SVR4 or empty for SVR3 */
-char *m88k_short_data;
-char *m88k_version;
-char m88k_volatile_code;
-
-unsigned m88k_gp_threshold = 0;
-int m88k_prologue_done	= 0;	/* Ln directives can now be emitted */
-int m88k_function_number = 0;	/* Counter unique to each function */
-int m88k_fp_offset	= 0;	/* offset of frame pointer if used */
-int m88k_stack_size	= 0;	/* size of allocated stack (including frame) */
-int m88k_case_index;
-
-rtx m88k_compare_reg;		/* cmp output pseudo register */
-rtx m88k_compare_op0;		/* cmpsi operand 0 */
-rtx m88k_compare_op1;		/* cmpsi operand 1 */
-
-enum processor_type m88k_cpu;	/* target cpu */
-
-/* Determine what instructions are needed to manufacture the integer VALUE
-   in the given MODE.  */
-
-enum m88k_instruction
-classify_integer (mode, value)
-     enum machine_mode mode;
-     register int value;
-{
-  register int mask;
-
-  if (value == 0)
-    return m88k_zero;
-  else if (SMALL_INTVAL (value))
-    return m88k_or;
-  else if (SMALL_INTVAL (-value))
-    return m88k_subu;
-  else if (mode == HImode)
-    return m88k_or_lo16;
-  else if (mode == QImode)
-    return m88k_or_lo8;
-  else if ((value & 0xffff) == 0)
-    return m88k_oru_hi16;
-  else if (integer_ok_for_set (value))
-    return m88k_set;
-  else
-    return m88k_oru_or;
-}
-
-/* Return the bit number in a compare word corresponding to CONDITION.  */
-
-int
-condition_value (condition)
-     rtx condition;
-{
-  switch (GET_CODE (condition))
-    {
-    case EQ: return 2;
-    case NE: return 3;
-    case GT: return 4;
-    case LE: return 5;
-    case LT: return 6;
-    case GE: return 7;
-    case GTU: return 8;
-    case LEU: return 9;
-    case LTU: return 10;
-    case GEU: return 11;
-    default: abort ();
-    }
-}
-
-int
-integer_ok_for_set (value)
-     register unsigned value;
-{
-  /* All the "one" bits must be contiguous.  If so, MASK + 1 will be
-     a power of two or zero.  */
-  register unsigned mask = (value | (value - 1));
-  return (value && POWER_OF_2_or_0 (mask + 1));
-}
-
-char *
-output_load_const_int (mode, operands)
-     enum machine_mode mode;
-     rtx *operands;
-{
-  static char *patterns[] =
-    { "or %0,%#r0,0",
-      "or %0,%#r0,%1",
-      "subu %0,%#r0,%n1",
-      "or %0,%#r0,%h1",
-      "or %0,%#r0,%q1",
-      "set %0,%#r0,%s1",
-      "or.u %0,%#r0,%X1",
-      "or.u %0,%#r0,%X1\n\tor %0,%0,%x1",
-    };
-
-  if (! REG_P (operands[0])
-      || GET_CODE (operands[1]) != CONST_INT)
-    abort ();
-  return patterns[classify_integer (mode, INTVAL (operands[1]))];
-}
-
-/* These next two routines assume that floating point numbers are represented
-   in a manner which is consistent between host and target machines.  */
-
-char *
-output_load_const_float (operands)
-     rtx *operands;
-{
-  /* These can return 0 under some circumstances when cross-compiling.  */
-  operands[0] = operand_subword (operands[0], 0, 0, SFmode);
-  operands[1] = operand_subword (operands[1], 0, 0, SFmode);
-
-  return output_load_const_int (SImode, operands);
-}
-
-char *
-output_load_const_double (operands)
-     rtx *operands;
-{
-  rtx latehalf[2];
-
-  /* These can return zero on some cross-compilers, but there's nothing
-     we can do about it.  */
-  latehalf[0] = operand_subword (operands[0], 1, 0, DFmode);
-  latehalf[1] = operand_subword (operands[1], 1, 0, DFmode);
-
-  operands[0] = operand_subword (operands[0], 0, 0, DFmode);
-  operands[1] = operand_subword (operands[1], 0, 0, DFmode);
-
-  output_asm_insn (output_load_const_int (SImode, operands), operands);
-
-  operands[0] = latehalf[0];
-  operands[1] = latehalf[1];
-
-  return output_load_const_int (SImode, operands);
-}
-
-char *
-output_load_const_dimode (operands)
-     rtx *operands;
-{
-  rtx latehalf[2];
-
-  latehalf[0] = operand_subword (operands[0], 1, 0, DImode);
-  latehalf[1] = operand_subword (operands[1], 1, 0, DImode);
-
-  operands[0] = operand_subword (operands[0], 0, 0, DImode);
-  operands[1] = operand_subword (operands[1], 0, 0, DImode);
-
-  output_asm_insn (output_load_const_int (SImode, operands), operands);
-
-  operands[0] = latehalf[0];
-  operands[1] = latehalf[1];
-
-  return output_load_const_int (SImode, operands);
-}
-
-/* Emit insns to move operands[1] into operands[0].
-
-   Return 1 if we have written out everything that needs to be done to
-   do the move.  Otherwise, return 0 and the caller will emit the move
-   normally.
-
-   SCRATCH if non zero can be used as a scratch register for the move
-   operation.  It is provided by a SECONDARY_RELOAD_* macro if needed.  */
-
-int
-emit_move_sequence (operands, mode, scratch)
-     rtx *operands;
-     enum machine_mode mode;
-     rtx scratch;
-{
-  register rtx operand0 = operands[0];
-  register rtx operand1 = operands[1];
-
-  if (CONSTANT_P (operand1) && flag_pic
-      && pic_address_needs_scratch (operand1))
-    operands[1] = operand1 = legitimize_address (1, operand1, 0, 0);
-
-  /* Handle most common case first: storing into a register.  */
-  if (register_operand (operand0, mode))
-    {
-      if (register_operand (operand1, mode)
-	  || (GET_CODE (operand1) == CONST_INT && SMALL_INT (operand1))
-	  || GET_CODE (operand1) == HIGH
-	  /* Only `general_operands' can come here, so MEM is ok.  */
-	  || GET_CODE (operand1) == MEM)
-	{
-	  /* Run this case quickly.  */
-	  emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
-	  return 1;
-	}
-    }
-  else if (GET_CODE (operand0) == MEM)
-    {
-      if (register_operand (operand1, mode)
-	  || (operand1 == const0_rtx && GET_MODE_SIZE (mode) <= UNITS_PER_WORD))
-	{
-	  /* Run this case quickly.  */
-	  emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
-	  return 1;
-	}
-      if (! reload_in_progress && ! reload_completed)
-	{
-	  operands[0] = validize_mem (operand0);
-	  operands[1] = operand1 = force_reg (mode, operand1);
-	}
-    }
-
-  /* Simplify the source if we need to.  */
-  if (GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
-    {
-      if (GET_CODE (operand1) != CONST_INT
-	  && GET_CODE (operand1) != CONST_DOUBLE)
-	{
-	  rtx temp = ((reload_in_progress || reload_completed)
-		      ? operand0 : 0);
-	  operands[1] = legitimize_address (flag_pic
-					    && symbolic_address_p (operand1),
-					    operand1, temp, scratch);
-	  if (mode != SImode)
-	    operands[1] = gen_rtx (SUBREG, mode, operands[1], 0);
-	}
-    }
-
-  /* Now have insn-emit do whatever it normally does.  */
-  return 0;
-}
-
-/* Return a legitimate reference for ORIG (either an address or a MEM)
-   using the register REG.  If PIC and the address is already
-   position-independent, use ORIG.  Newly generated position-independent
-   addresses go into a reg.  This is REG if non zero, otherwise we
-   allocate register(s) as necessary.  If this is called during reload,
-   and we need a second temp register, then we use SCRATCH, which is
-   provided via the SECONDARY_INPUT_RELOAD_CLASS mechanism.  */
-
-struct rtx_def *
-legitimize_address (pic, orig, reg, scratch)
-     int pic;
-     rtx orig;
-     rtx reg;
-     rtx scratch;
-{
-  rtx addr = (GET_CODE (orig) == MEM ? XEXP (orig, 0) : orig);
-  rtx new = orig;
-  rtx temp, insn;
-
-  if (pic)
-    {
-      if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
-	{
-	  if (reg == 0)
-	    {
-	      if (reload_in_progress || reload_completed)
-		abort ();
-	      else
-		reg = gen_reg_rtx (Pmode);
-	    }
-
-	  if (flag_pic == 2)
-	    {
-	      /* If not during reload, allocate another temp reg here for
-		 loading in the address, so that these instructions can be
-		 optimized properly.  */
-	      temp = ((reload_in_progress || reload_completed)
-		      ? reg : gen_reg_rtx (Pmode));
-
-	      emit_insn (gen_rtx (SET, VOIDmode, temp,
-				  gen_rtx (HIGH, SImode,
-					   gen_rtx (UNSPEC, SImode,
-						    gen_rtvec (1, addr),
-						    0))));
-	      emit_insn (gen_rtx (SET, VOIDmode, temp,
-				  gen_rtx (LO_SUM, SImode, temp,
-					   gen_rtx (UNSPEC, SImode,
-						    gen_rtvec (1, addr),
-						    0))));
-	      addr = temp;
-	    }
-	  new = gen_rtx (MEM, Pmode,
-			 gen_rtx (PLUS, SImode,
-				  pic_offset_table_rtx, addr));
-	  current_function_uses_pic_offset_table = 1;
-	  RTX_UNCHANGING_P (new) = 1;
-	  insn = emit_move_insn (reg, new);
-	  /* Put a REG_EQUAL note on this insn, so that it can be optimized
-	     by loop.  */
-	  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig,
-				      REG_NOTES (insn));
-	  new = reg;
-	}
-      else if (GET_CODE (addr) == CONST)
-	{
-	  rtx base, offset;
-
-	  if (GET_CODE (XEXP (addr, 0)) == PLUS
-	      && XEXP (XEXP (addr, 0), 0) == pic_offset_table_rtx)
-	    return orig;
-
-	  if (reg == 0)
-	    {
-	      if (reload_in_progress || reload_completed)
-		abort ();
-	      else
-		reg = gen_reg_rtx (Pmode);
-	    }
-
-	  if (GET_CODE (XEXP (addr, 0)) != PLUS) abort ();
-
-	  base = legitimize_address (1, XEXP (XEXP (addr, 0), 0), reg, 0);
-	  addr = legitimize_address (1, XEXP (XEXP (addr, 0), 1),
-				     base == reg ? 0 : reg, 0);
-
-	  if (GET_CODE (addr) == CONST_INT)
-	    {
-	      if (ADD_INT (addr))
-		return plus_constant_for_output (base, INTVAL (addr));
-	      else if (! reload_in_progress && ! reload_completed)
-		addr = force_reg (Pmode, addr);
-	      /* We can't create any new registers during reload, so use the
-		 SCRATCH reg provided by the reload_insi pattern.  */
-	      else if (scratch)
-		{
-		  emit_move_insn (scratch, addr);
-		  addr = scratch;
-		}
-	      else
-		/* If we reach here, then the SECONDARY_INPUT_RELOAD_CLASS
-		   macro needs to be adjusted so that a scratch reg is provided
-		   for this address.  */
-		abort ();
-	    }
-	  new = gen_rtx (PLUS, SImode, base, addr);
-	  /* Should we set special REG_NOTEs here?  */
-	}
-    }
-  else if (! SHORT_ADDRESS_P (addr, temp))
-    {
-      if (reg == 0)
-	{
-	  if (reload_in_progress || reload_completed)
-	    abort ();
-	  else
-	    reg = gen_reg_rtx (Pmode);
-	}
-
-      emit_insn (gen_rtx (SET, VOIDmode,
-			  reg, gen_rtx (HIGH, SImode, addr)));
-      new = gen_rtx (LO_SUM, SImode, reg, addr);
-    }
-
-  if (new != orig
-      && GET_CODE (orig) == MEM)
-    {
-      new = gen_rtx (MEM, GET_MODE (orig), new);
-      RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (orig);
-      MEM_COPY_ATTRIBUTES (new, orig);
-    }
-  return new;
-}
-
-/* Support functions for code to emit a block move.  There are four methods
-   used to perform the block move:
-   + call memcpy
-   + call the looping library function, e.g. __movstrSI64n8
-   + call a non-looping library function, e.g. __movstrHI15x11
-   + produce an inline sequence of ld/st instructions
-
-   The parameters below describe the library functions produced by
-   movstr-m88k.sh.  */
-
-#define MOVSTR_LOOP	64 /* __movstrSI64n68 .. __movstrSI64n8 */
-#define MOVSTR_QI	16 /* __movstrQI16x16 .. __movstrQI16x2 */
-#define MOVSTR_HI	48 /* __movstrHI48x48 .. __movstrHI48x4 */
-#define MOVSTR_SI	96 /* __movstrSI96x96 .. __movstrSI96x8 */
-#define MOVSTR_DI	96 /* __movstrDI96x96 .. __movstrDI96x16 */
-#define MOVSTR_ODD_HI	16 /* __movstrHI15x15 .. __movstrHI15x5 */
-#define MOVSTR_ODD_SI	48 /* __movstrSI47x47 .. __movstrSI47x11,
-			      __movstrSI46x46 .. __movstrSI46x10,
-			      __movstrSI45x45 .. __movstrSI45x9 */
-#define MOVSTR_ODD_DI	48 /* __movstrDI47x47 .. __movstrDI47x23,
-			      __movstrDI46x46 .. __movstrDI46x22,
-			      __movstrDI45x45 .. __movstrDI45x21,
-			      __movstrDI44x44 .. __movstrDI44x20,
-			      __movstrDI43x43 .. __movstrDI43x19,
-			      __movstrDI42x42 .. __movstrDI42x18,
-			      __movstrDI41x41 .. __movstrDI41x17 */
-
-/* Limits for using the non-looping movstr functions.  For the m88100
-   processor, we assume the source and destination are word aligned.
-   The QImode and HImode limits are the break even points where memcpy
-   does just as well and beyond which memcpy does better.  For the
-   m88110, we tend to assume double word alignment, but also analyze
-   the word aligned cases.  The analysis is complicated because memcpy
-   may use the cache control instructions for better performance.  */
-
-#define MOVSTR_QI_LIMIT_88100   13
-#define MOVSTR_HI_LIMIT_88100   38
-#define MOVSTR_SI_LIMIT_88100   MOVSTR_SI
-#define MOVSTR_DI_LIMIT_88100   MOVSTR_SI
-  
-#define MOVSTR_QI_LIMIT_88000   16
-#define MOVSTR_HI_LIMIT_88000   38
-#define MOVSTR_SI_LIMIT_88000   72
-#define MOVSTR_DI_LIMIT_88000   72
-
-#define MOVSTR_QI_LIMIT_88110   16
-#define MOVSTR_HI_LIMIT_88110   38
-#define MOVSTR_SI_LIMIT_88110   72
-#define MOVSTR_DI_LIMIT_88110   72
-
-static enum machine_mode mode_from_align[] =
-			      {VOIDmode, QImode, HImode, VOIDmode, SImode,
-			       VOIDmode, VOIDmode, VOIDmode, DImode};
-static int max_from_align[] = {0, MOVSTR_QI, MOVSTR_HI, 0, MOVSTR_SI,
-			       0, 0, 0, MOVSTR_DI};
-static int all_from_align[] = {0, MOVSTR_QI, MOVSTR_ODD_HI, 0, MOVSTR_ODD_SI,
-			       0, 0, 0, MOVSTR_ODD_DI};
-
-static int best_from_align[3][9] =
-  {0, MOVSTR_QI_LIMIT_88100, MOVSTR_HI_LIMIT_88100, 0, MOVSTR_SI_LIMIT_88100, 
-   0, 0, 0, MOVSTR_DI_LIMIT_88100,
-   0, MOVSTR_QI_LIMIT_88110, MOVSTR_HI_LIMIT_88110, 0, MOVSTR_SI_LIMIT_88110, 
-   0, 0, 0, MOVSTR_DI_LIMIT_88110,  
-   0, MOVSTR_QI_LIMIT_88000, MOVSTR_HI_LIMIT_88000, 0, MOVSTR_SI_LIMIT_88000,
-   0, 0, 0, MOVSTR_DI_LIMIT_88000};
-
-static void block_move_loop ();
-static void block_move_no_loop ();
-static void block_move_sequence ();
-
-/* Emit code to perform a block move.  Choose the best method.
-
-   OPERANDS[0] is the destination.
-   OPERANDS[1] is the source.
-   OPERANDS[2] is the size.
-   OPERANDS[3] is the alignment safe to use.  */
-
-void
-expand_block_move (dest_mem, src_mem, operands)
-     rtx dest_mem;
-     rtx src_mem;
-     rtx *operands;
-{
-  int align = INTVAL (operands[3]);
-  int constp = (GET_CODE (operands[2]) == CONST_INT);
-  int bytes = (constp ? INTVAL (operands[2]) : 0);
-  int target = (int) m88k_cpu;
-
-  if (! (PROCESSOR_M88100 == 0
-	 && PROCESSOR_M88110 == 1
-	 && PROCESSOR_M88000 == 2))
-    abort ();
-
-  if (constp && bytes <= 0)
-    return;
-
-  /* Determine machine mode to do move with.  */
-  if (align > 4 && !TARGET_88110)
-    align = 4;
-  else if (align <= 0 || align == 3)
-    abort ();	/* block move invalid alignment.  */
-
-  if (constp && bytes <= 3 * align)
-    block_move_sequence (operands[0], dest_mem, operands[1], src_mem,
-			 bytes, align, 0);
-
-  else if (constp && bytes <= best_from_align[target][align])
-    block_move_no_loop (operands[0], dest_mem, operands[1], src_mem,
-			bytes, align);
-
-  else if (constp && align == 4 && TARGET_88100)
-    block_move_loop (operands[0], dest_mem, operands[1], src_mem,
-		     bytes, align);
-
-  else
-    {
-#ifdef TARGET_MEM_FUNCTIONS
-      emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
-			 VOIDmode, 3,
-			 operands[0], Pmode,
-			 operands[1], Pmode,
-			 convert_to_mode (TYPE_MODE (sizetype), operands[2],
-					  TREE_UNSIGNED (sizetype)),
-			 TYPE_MODE (sizetype));
-#else
-      emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
-			 VOIDmode, 3,
-			 operands[1], Pmode,
-			 operands[0], Pmode,
-			 convert_to_mode (TYPE_MODE (integer_type_node),
-					  operands[2],
-					  TREE_UNSIGNED (integer_type_node)),
-			 TYPE_MODE (integer_type_node));
-#endif
-    }
-}
-
-/* Emit code to perform a block move by calling a looping movstr library
-   function.  SIZE and ALIGN are known constants.  DEST and SRC are
-   registers.  */
-
-static void
-block_move_loop (dest, dest_mem, src, src_mem, size, align)
-     rtx dest, dest_mem;
-     rtx src, src_mem;
-     int size;
-     int align;
-{
-  enum machine_mode mode;
-  int count;
-  int units;
-  int remainder;
-  rtx offset_rtx;
-  rtx value_rtx;
-  char entry[30];
-  tree entry_name;
-
-  /* Determine machine mode to do move with.  */
-  if (align != 4)
-    abort ();
-
-  /* Determine the structure of the loop.  */
-  count = size / MOVSTR_LOOP;
-  units = (size - count * MOVSTR_LOOP) / align;
-
-  if (units < 2)
-    {
-      count--;
-      units += MOVSTR_LOOP / align;
-    }
-
-  if (count <= 0)
-    {
-      block_move_no_loop (dest, dest_mem, src, src_mem, size, align);
-      return;
-    }
-
-  remainder = size - count * MOVSTR_LOOP - units * align;
-
-  mode = mode_from_align[align];
-  sprintf (entry, "__movstr%s%dn%d",
-	   GET_MODE_NAME (mode), MOVSTR_LOOP, units * align);
-  entry_name = get_identifier (entry);
-
-  offset_rtx = GEN_INT (MOVSTR_LOOP + (1 - units) * align);
-
-  value_rtx = gen_rtx (MEM, MEM_IN_STRUCT_P (src_mem) ? mode : BLKmode,
-		       gen_rtx (PLUS, Pmode,
-				gen_rtx (REG, Pmode, 3),
-				offset_rtx));
-  RTX_UNCHANGING_P (value_rtx) = RTX_UNCHANGING_P (src_mem);
-  MEM_COPY_ATTRIBUTES (value_rtx, src_mem);
-
-  emit_insn (gen_call_movstrsi_loop
-	     (gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (entry_name)),
-	      dest, src, offset_rtx, value_rtx,
-	      gen_rtx (REG, mode, ((units & 1) ? 4 : 5)),
-	      GEN_INT (count)));
-
-  if (remainder)
-    block_move_sequence (gen_rtx (REG, Pmode, 2), dest_mem,
-			 gen_rtx (REG, Pmode, 3), src_mem,
-			 remainder, align, MOVSTR_LOOP + align);
-}
-
-/* Emit code to perform a block move by calling a non-looping library
-   function.  SIZE and ALIGN are known constants.  DEST and SRC are
-   registers.  OFFSET is the known starting point for the output pattern.  */
-
-static void
-block_move_no_loop (dest, dest_mem, src, src_mem, size, align)
-     rtx dest, dest_mem;
-     rtx src, src_mem;
-     int size;
-     int align;
-{
-  enum machine_mode mode = mode_from_align[align];
-  int units = size / align;
-  int remainder = size - units * align;
-  int most;
-  int value_reg;
-  rtx offset_rtx;
-  rtx value_rtx;
-  char entry[30];
-  tree entry_name;
-
-  if (remainder && size <= all_from_align[align])
-    {
-      most = all_from_align[align] - (align - remainder);
-      remainder = 0;
-    }
-  else
-    {
-      most = max_from_align[align];
-    }
-
-  sprintf (entry, "__movstr%s%dx%d",
-	   GET_MODE_NAME (mode), most, size - remainder);
-  entry_name = get_identifier (entry);
-
-  offset_rtx = GEN_INT (most - (size - remainder));
-
-  value_rtx = gen_rtx (MEM, MEM_IN_STRUCT_P (src_mem) ? mode : BLKmode,
-		       gen_rtx (PLUS, Pmode,
-				gen_rtx (REG, Pmode, 3),
-				offset_rtx));
-  RTX_UNCHANGING_P (value_rtx) = RTX_UNCHANGING_P (src_mem);
-  MEM_COPY_ATTRIBUTES (value_rtx, src_mem);
-
-  value_reg = ((((most - (size - remainder)) / align) & 1) == 0
-	       ? (align == 8 ? 6 : 5) : 4);
-
-  emit_insn (gen_call_block_move
-	     (gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (entry_name)),
-	      dest, src, offset_rtx, value_rtx,
-	      gen_rtx (REG, mode, value_reg)));
-
-  if (remainder)
-    block_move_sequence (gen_rtx (REG, Pmode, 2), dest_mem,
-			 gen_rtx (REG, Pmode, 3), src_mem,
-			 remainder, align, most);
-}
-
-/* Emit code to perform a block move with an offset sequence of ld/st
-   instructions (..., ld 0, st 1, ld 1, st 0, ...).  SIZE and ALIGN are
-   known constants.  DEST and SRC are registers.  OFFSET is the known
-   starting point for the output pattern.  */
-
-static void
-block_move_sequence (dest, dest_mem, src, src_mem, size, align, offset)
-     rtx dest, dest_mem;
-     rtx src, src_mem;
-     int size;
-     int align;
-     int offset;
-{
-  rtx temp[2];
-  enum machine_mode mode[2];
-  int amount[2];
-  int active[2];
-  int phase = 0;
-  int next;
-  int offset_ld = offset;
-  int offset_st = offset;
-
-  active[0] = active[1] = FALSE;
-
-  /* Establish parameters for the first load and for the second load if
-     it is known to be the same mode as the first.  */
-  amount[0] = amount[1] = align;
-  mode[0] = mode_from_align[align];
-  temp[0] = gen_reg_rtx (mode[0]);
-  if (size >= 2 * align)
-    {
-      mode[1] = mode[0];
-      temp[1] = gen_reg_rtx (mode[1]);
-    }
-
-  do
-    {
-      rtx srcp, dstp;
-      next = phase;
-      phase = !phase;
-
-      if (size > 0)
-	{
-	  /* Change modes as the sequence tails off.  */
-	  if (size < amount[next])
-	    {
-	      amount[next] = (size >= 4 ? 4 : (size >= 2 ? 2 : 1));
-	      mode[next] = mode_from_align[amount[next]];
-	      temp[next] = gen_reg_rtx (mode[next]);
-	    }
-	  size -= amount[next];
-	  srcp = gen_rtx (MEM,
-			  MEM_IN_STRUCT_P (src_mem) ? mode[next] : BLKmode,
-			  gen_rtx (PLUS, Pmode, src,
-				   GEN_INT (offset_ld)));
-	  RTX_UNCHANGING_P (srcp) = RTX_UNCHANGING_P (src_mem);
-	  MEM_COPY_ATTRIBUTES (srcp, src_mem);
-	  emit_insn (gen_rtx (SET, VOIDmode, temp[next], srcp));
-	  offset_ld += amount[next];
-	  active[next] = TRUE;
-	}
-
-      if (active[phase])
-	{
-	  active[phase] = FALSE;
-	  dstp = gen_rtx (MEM,
-			  MEM_IN_STRUCT_P (dest_mem) ? mode[phase] : BLKmode,
-			  gen_rtx (PLUS, Pmode, dest,
-				   GEN_INT (offset_st)));
-	  RTX_UNCHANGING_P (dstp) = RTX_UNCHANGING_P (dest_mem);
-	  MEM_COPY_ATTRIBUTES (dstp, dest_mem);
-	  emit_insn (gen_rtx (SET, VOIDmode, dstp, temp[phase]));
-	  offset_st += amount[phase];
-	}
-    }
-  while (active[next]);
-}
-
-/* Emit the code to do an AND operation.  */
-
-char *
-output_and (operands)
-     rtx operands[];
-{
-  unsigned int value;
-
-  if (REG_P (operands[2]))
-    return "and %0,%1,%2";
-
-  value = INTVAL (operands[2]);
-  if (SMALL_INTVAL (value))
-    return "mask %0,%1,%2";
-  else if ((value & 0xffff0000) == 0xffff0000)
-    return "and %0,%1,%x2";
-  else if ((value & 0xffff) == 0xffff)
-    return "and.u %0,%1,%X2";
-  else if ((value & 0xffff) == 0)
-    return "mask.u %0,%1,%X2";
-  else if (integer_ok_for_set (~value))
-    return "clr %0,%1,%S2";
-  else
-    return "and.u %0,%1,%X2\n\tand %0,%0,%x2";
-}
-
-/* Emit the code to do an inclusive OR operation.  */
-
-char *
-output_ior (operands)
-     rtx operands[];
-{
-  unsigned int value;
-
-  if (REG_P (operands[2]))
-    return "or %0,%1,%2";
-
-  value = INTVAL (operands[2]);
-  if (SMALL_INTVAL (value))
-    return "or %0,%1,%2";
-  else if ((value & 0xffff) == 0)
-    return "or.u %0,%1,%X2";
-  else if (integer_ok_for_set (value))
-    return "set %0,%1,%s2";
-  else
-    return "or.u %0,%1,%X2\n\tor %0,%0,%x2";
-}
-
-/* Emit the instructions for doing an XOR.  */
-
-char *
-output_xor (operands)
-     rtx operands[];
-{
-  unsigned int value;
-
-  if (REG_P (operands[2]))
-    return "xor %0,%1,%2";
-
-  value = INTVAL (operands[2]);
-  if (SMALL_INTVAL (value))
-    return "xor %0,%1,%2";
-  else if ((value & 0xffff) == 0)
-    return "xor.u %0,%1,%X2";
-  else
-    return "xor.u %0,%1,%X2\n\txor %0,%0,%x2";
-}
-
-/* Output a call.  Normally this is just bsr or jsr, but this also deals with
-   accomplishing a branch after the call by incrementing r1.  This requires
-   that various assembler bugs be accommodated.  The 4.30 DG/UX assembler
-   requires that forward references not occur when computing the difference of
-   two labels.  The [version?] Motorola assembler computes a word difference.
-   No doubt there's more to come!
-
-   It would seem the same idea could be used to tail call, but in this case,
-   the epilogue will be non-null.  */
-
-static rtx sb_name = 0;
-static rtx sb_high = 0;
-static rtx sb_low = 0;
-
-char *
-output_call (operands, addr)
-     rtx operands[];
-     rtx addr;
-{
-  operands[0] = addr;
-  if (final_sequence)
-    {
-      rtx jump;
-      rtx seq_insn;
-
-      /* This can be generalized, but there is currently no need.  */
-      if (XVECLEN (final_sequence, 0) != 2)
-	abort ();
-
-      /* The address of interior insns is not computed, so use the sequence.  */
-      seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
-      jump = XVECEXP (final_sequence, 0, 1);
-      if (GET_CODE (jump) == JUMP_INSN)
-	{
-	  rtx low, high;
-	  char *last;
-	  rtx dest = XEXP (SET_SRC (PATTERN (jump)), 0);
-	  int delta = 4 * (insn_addresses[INSN_UID (dest)]
-			   - insn_addresses[INSN_UID (seq_insn)]
-			   - 2);
-#if (MONITOR_GCC & 0x2) /* How often do long branches happen?  */
-	  if ((unsigned) (delta + 0x8000) >= 0x10000)
-	    warning ("Internal gcc monitor: short-branch(%x)", delta);
-#endif
-
-	  /* Delete the jump.  */
-	  PUT_CODE (jump, NOTE);
-	  NOTE_LINE_NUMBER (jump) = NOTE_INSN_DELETED;
-	  NOTE_SOURCE_FILE (jump) = 0;
-
-	  /* We only do this optimization if -O2, modifying the value of
-	     r1 in the delay slot confuses debuggers and profilers on some
-	     systems.
-
-	     If we loose, we must use the non-delay form.  This is unlikely
-	     to ever happen.  If it becomes a problem, claim that a call
-	     has two delay slots and only the second can be filled with
-	     a jump.  
-
-	     The 88110 can lose when a jsr.n r1 is issued and a page fault
-	     occurs accessing the delay slot.  So don't use jsr.n form when
-	     jumping thru r1.
-	   */
-#ifdef AS_BUG_IMMEDIATE_LABEL /* The assembler restricts immediate values.  */
-	  if (optimize < 2
-	      || ! ADD_INTVAL (delta * 2)
-#else
-	  if (optimize < 2
-	      || ! ADD_INTVAL (delta)
-#endif
-	      || (REG_P (addr) && REGNO (addr) == 1))
-	    {
-	      operands[1] = dest;
-	      return (REG_P (addr)
-		      ? "jsr %0\n\tbr %l1"
-		      : (flag_pic
-			 ? "bsr %0#plt\n\tbr %l1"
-			 : "bsr %0\n\tbr %l1"));
-	    }
-
-	  /* Output the short branch form.  */
-	  output_asm_insn ((REG_P (addr)
-			    ? "jsr.n %0"
-			    : (flag_pic ? "bsr.n %0#plt" : "bsr.n %0")),
-			   operands);
-
-#ifdef USE_GAS
-	  last = (delta < 0
-		  ? "subu %#r1,%#r1,.-%l0+4"
-		  : "addu %#r1,%#r1,%l0-.-4");
-	  operands[0] = dest;
-#else
-	  operands[0] = gen_label_rtx ();
-	  operands[1] = gen_label_rtx ();
-	  if (delta < 0)
-	    {
-	      low = dest;
-	      high = operands[1];
-	      last = "subu %#r1,%#r1,%l0\n%l1:";
-	    }
-	  else
-	    {
-	      low = operands[1];
-	      high = dest;
-	      last = "addu %#r1,%#r1,%l0\n%l1:";
-	    }
-
-	  /* Record the values to be computed later as "def name,high-low".  */
-	  sb_name = gen_rtx (EXPR_LIST, VOIDmode, operands[0], sb_name);
-	  sb_high = gen_rtx (EXPR_LIST, VOIDmode, high, sb_high);
-	  sb_low = gen_rtx (EXPR_LIST, VOIDmode, low, sb_low);
-#endif /* Don't USE_GAS */
-
-	  return last;
-	}
-    }
-  return (REG_P (addr)
-	  ? "jsr%. %0"
-	  : (flag_pic ? "bsr%. %0#plt" : "bsr%. %0"));
-}
-
-static void
-output_short_branch_defs (stream)
-     FILE *stream;
-{
-  char name[256], high[256], low[256];
-
-  for (; sb_name && sb_high && sb_low;
-       sb_name = XEXP (sb_name, 1),
-       sb_high = XEXP (sb_high, 1),
-       sb_low = XEXP (sb_low, 1))
-    {
-      ASM_GENERATE_INTERNAL_LABEL
-	(name, "L", CODE_LABEL_NUMBER (XEXP (sb_name, 0)));
-      ASM_GENERATE_INTERNAL_LABEL
-	(high, "L", CODE_LABEL_NUMBER (XEXP (sb_high, 0)));
-      ASM_GENERATE_INTERNAL_LABEL
-	(low, "L", CODE_LABEL_NUMBER (XEXP (sb_low, 0)));
-      /* This will change as the assembler requirements become known.  */
-      fprintf (stream, "\t%s\t %s,%s-%s\n",
-	       SET_ASM_OP, &name[1], &high[1], &low[1]);
-    }
-  if (sb_name || sb_high || sb_low)
-    abort ();
-}
-
-/* Return truth value of the statement that this conditional branch is likely
-   to fall through.  CONDITION, is the condition that JUMP_INSN is testing.  */
-
-int
-mostly_false_jump (jump_insn, condition)
-     rtx jump_insn, condition;
-{
-  rtx target_label = JUMP_LABEL (jump_insn);
-  rtx insnt, insnj;
-
-  /* Much of this isn't computed unless we're optimizing.  */
-  if (optimize == 0)
-    return 0;
-
-  /* Determine if one path or the other leads to a return.  */
-  for (insnt = NEXT_INSN (target_label);
-       insnt;
-       insnt = NEXT_INSN (insnt))
-    {
-      if (GET_CODE (insnt) == JUMP_INSN)
-	break;
-      else if (GET_CODE (insnt) == INSN
-	       && GET_CODE (PATTERN (insnt)) == SEQUENCE
-	       && GET_CODE (XVECEXP (PATTERN (insnt), 0, 0)) == JUMP_INSN)
-	{
-	  insnt = XVECEXP (PATTERN (insnt), 0, 0);
-	  break;
-	}
-    }
-  if (insnt
-      && (GET_CODE (PATTERN (insnt)) == RETURN
-	  || (GET_CODE (PATTERN (insnt)) == SET
-	      && GET_CODE (SET_SRC (PATTERN (insnt))) == REG
-	      && REGNO (SET_SRC (PATTERN (insnt))) == 1)))
-    insnt = 0;
-
-  for (insnj = NEXT_INSN (jump_insn);
-       insnj;
-       insnj = NEXT_INSN (insnj))
-    {
-      if (GET_CODE (insnj) == JUMP_INSN)
-	break;
-      else if (GET_CODE (insnj) == INSN
-	       && GET_CODE (PATTERN (insnj)) == SEQUENCE
-	       && GET_CODE (XVECEXP (PATTERN (insnj), 0, 0)) == JUMP_INSN)
-	{
-	  insnj = XVECEXP (PATTERN (insnj), 0, 0);
-	  break;
-	}
-    }
-  if (insnj
-      && (GET_CODE (PATTERN (insnj)) == RETURN
-	  || (GET_CODE (PATTERN (insnj)) == SET
-	      && GET_CODE (SET_SRC (PATTERN (insnj))) == REG
-	      && REGNO (SET_SRC (PATTERN (insnj))) == 1)))
-    insnj = 0;
-
-  /* Predict to not return.  */
-  if ((insnt == 0) != (insnj == 0))
-    return (insnt == 0);
-
-  /* Predict loops to loop.  */
-  for (insnt = PREV_INSN (target_label);
-       insnt && GET_CODE (insnt) == NOTE;
-       insnt = PREV_INSN (insnt))
-    if (NOTE_LINE_NUMBER (insnt) == NOTE_INSN_LOOP_END)
-      return 1;
-    else if (NOTE_LINE_NUMBER (insnt) == NOTE_INSN_LOOP_BEG)
-      return 0;
-    else if (NOTE_LINE_NUMBER (insnt) == NOTE_INSN_LOOP_CONT)
-      return 0;
-
-  /* Predict backward branches usually take.  */
-  if (final_sequence)
-    insnj = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
-  else
-    insnj = jump_insn;
-  if (insn_addresses[INSN_UID (insnj)]
-      > insn_addresses[INSN_UID (target_label)])
-    return 0;
-
-  /* EQ tests are usually false and NE tests are usually true.  Also,
-     most quantities are positive, so we can make the appropriate guesses
-     about signed comparisons against zero.  Consider unsigned comparisons
-     to be a range check and assume quantities to be in range.  */
-  switch (GET_CODE (condition))
-    {
-    case CONST_INT:
-      /* Unconditional branch.  */
-      return 0;
-    case EQ:
-      return 1;
-    case NE:
-      return 0;
-    case LE:
-    case LT:
-    case GEU:
-    case GTU: /* Must get casesi right at least.  */
-      if (XEXP (condition, 1) == const0_rtx)
-        return 1;
-      break;
-    case GE:
-    case GT:
-    case LEU:
-    case LTU:
-      if (XEXP (condition, 1) == const0_rtx)
-	return 0;
-      break;
-    }
-
-  return 0;
-}
-
-/* Return true if the operand is a power of two and is a floating
-   point type (to optimize division by power of two into multiplication).  */
-
-int
-real_power_of_2_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  union {
-    REAL_VALUE_TYPE d;
-    int i[sizeof (REAL_VALUE_TYPE) / sizeof (int)];
-    struct {				/* IEEE double precision format */
-      unsigned sign	 :  1;
-      unsigned exponent  : 11;
-      unsigned mantissa1 : 20;
-      unsigned mantissa2;
-    } s;
-    struct {				/* IEEE double format to quick check */
-      unsigned sign	 :  1;		/* if it fits in a float */
-      unsigned exponent1 :  4;
-      unsigned exponent2 :  7;
-      unsigned mantissa1 : 20;
-      unsigned mantissa2;
-    } s2;
-  } u;
-
-  if (GET_MODE (op) != DFmode && GET_MODE (op) != SFmode)
-    return 0;
-
-  if (GET_CODE (op) != CONST_DOUBLE)
-    return 0;
-
-  u.i[0] = CONST_DOUBLE_LOW  (op);
-  u.i[1] = CONST_DOUBLE_HIGH (op);
-
-  if (u.s.mantissa1 != 0 || u.s.mantissa2 != 0	/* not a power of two */
-      || u.s.exponent == 0			/* constant 0.0 */
-      || u.s.exponent == 0x7ff			/* NAN */
-      || (u.s2.exponent1 != 0x8 && u.s2.exponent1 != 0x7))
-    return 0;					/* const won't fit in float */
-
-  return 1;
-}
-
-/* Make OP legitimate for mode MODE.  Currently this only deals with DFmode
-   operands, putting them in registers and making CONST_DOUBLE values
-   SFmode where possible.  */
-
-struct rtx_def *
-legitimize_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  rtx temp;
-  union {
-    union real_extract r;
-    struct {				/* IEEE double precision format */
-      unsigned sign	 :  1;
-      unsigned exponent  : 11;
-      unsigned mantissa1 : 20;
-      unsigned mantissa2;
-    } d;
-    struct {				/* IEEE double format to quick check */
-      unsigned sign	 :  1;		/* if it fits in a float */
-      unsigned exponent1 :  4;
-      unsigned exponent2 :  7;
-      unsigned mantissa1 : 20;
-      unsigned mantissa2;
-    } s;
-  } u;
-
-  if (GET_CODE (op) == REG || mode != DFmode)
-    return op;
-
-  if (GET_CODE (op) == CONST_DOUBLE)
-    {
-      bcopy (&CONST_DOUBLE_LOW (op), &u.r, sizeof u);
-      if (u.d.exponent != 0x7ff /* NaN */
-	  && u.d.mantissa2 == 0 /* Mantissa fits */
-	  && (u.s.exponent1 == 0x8 || u.s.exponent1 == 0x7) /* Exponent fits */
-	  && (temp = simplify_unary_operation (FLOAT_TRUNCATE, SFmode,
-					       op, mode)) != 0)
-	return gen_rtx (FLOAT_EXTEND, mode, force_reg (SFmode, temp));
-    }
-  else if (register_operand (op, mode))
-    return op;
-
-  return force_reg (mode, op);
-}
-
-/* Return true if OP is a suitable input for a move insn.  */
-
-int
-move_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (register_operand (op, mode))
-    return 1;
-  if (GET_CODE (op) == CONST_INT)
-    return (classify_integer (mode, INTVAL (op)) < m88k_oru_hi16);
-  if (GET_MODE (op) != mode)
-    return 0;
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  if (GET_CODE (op) != MEM)
-    return 0;
-
-  op = XEXP (op, 0);
-  if (GET_CODE (op) == LO_SUM)
-    return (REG_P (XEXP (op, 0))
-	    && symbolic_address_p (XEXP (op, 1)));
-  return memory_address_p (mode, op);
-}
-
-/* Return true if OP is suitable for a call insn.  */
-
-int
-call_address_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (REG_P (op) || symbolic_address_p (op));
-}
-
-/* Returns true if OP is either a symbol reference or a sum of a symbol
-   reference and a constant.  */
-
-int
-symbolic_address_p (op)
-     register rtx op;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return 1;
-
-    case CONST:
-      op = XEXP (op, 0);
-      return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
-	       || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-	      && GET_CODE (XEXP (op, 1)) == CONST_INT);
-
-    default:
-      return 0;
-    }
-}
-
-/* Return true if OP is a register or const0_rtx.  */
-
-int
-reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (op == const0_rtx || register_operand (op, mode));
-}
-
-/* Nonzero if OP is a valid second operand for an arithmetic insn.  */
-
-int
-arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && SMALL_INT (op)));
-}
-
-/* Return true if OP is a  register or 5 bit integer.  */
-
-int
-arith5_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 32));
-}
-
-int
-arith32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode) || GET_CODE (op) == CONST_INT);
-}
-
-int
-arith64_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || GET_CODE (op) == CONST_INT
-	  || (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode));
-}
-
-int
-int5_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 32);
-}
-
-int
-int32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == CONST_INT);
-}
-
-/* Return true if OP is a register or a valid immediate operand for
-   addu or subu.  */
-
-int
-add_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && ADD_INT (op)));
-}
-
-/* Nonzero if this is a bitmask filling the bottom bits, for optimizing and +
-   shift left combinations into a single mak instruction.  */
-
-int
-mak_mask_p (value)
-     int value;
-{
-  return (value && POWER_OF_2_or_0 (value + 1));
-}
-
-int
-reg_or_bbx_mask_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int value;
-  if (register_operand (op, mode))
-    return 1;
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-
-  value = INTVAL (op);
-  if (POWER_OF_2 (value))
-    return 1;
-
-  return 0;
-}
-
-/* Return true if OP is valid to use in the context of a floating
-   point operation.  Special case 0.0, since we can use r0.  */
-
-int
-real_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (mode != SFmode && mode != DFmode)
-    return 0;
-
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_DOUBLE
-	      && op == CONST0_RTX (mode)));
-}
-
-/* Return true if OP is valid to use in the context of logic arithmetic
-   on condition codes. */
-
-int
-partial_ccmode_register_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return register_operand (op, CCmode) || register_operand (op, CCEVENmode);
-}
-
-/* Return true if OP is a relational operator.  */
-
-int
-relop (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case EQ:
-    case NE:
-    case LT:
-    case LE:
-    case GE:
-    case GT:
-    case LTU:
-    case LEU:
-    case GEU:
-    case GTU:
-      return 1;
-    default:
-      return 0;
-    }
-}
-
-int
-even_relop (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case EQ:
-    case LT:
-    case GT:
-    case LTU:
-    case GTU:
-      return 1;
-    default:
-      return 0;
-    }
-}
-
-int
-odd_relop (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case NE:
-    case LE:
-    case GE:
-    case LEU:
-    case GEU:
-      return 1;
-    default:
-      return 0;
-    }
-}
-
-/* Return true if OP is a relational operator, and is not an unsigned
-   relational operator.  */
-
-int
-relop_no_unsigned (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case EQ:
-    case NE:
-    case LT:
-    case LE:
-    case GE:
-    case GT:
-      /* @@ What is this test doing?  Why not use `mode'?  */
-      if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
-	  || GET_MODE (op) == DImode
-	  || GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_FLOAT
-	  || GET_MODE (XEXP (op, 0)) == DImode
-	  || GET_MODE_CLASS (GET_MODE (XEXP (op, 1))) == MODE_FLOAT
-	  || GET_MODE (XEXP (op, 1)) == DImode)
-	return 0;
-      return 1;
-    default:
-      return 0;
-    }
-}
-
-/* Return true if the code of this rtx pattern is EQ or NE.  */
-
-int
-equality_op (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
-}
-
-/* Return true if the code of this rtx pattern is pc or label_ref.  */
-
-int
-pc_or_label_ref (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
-}
-
-/* Output to FILE the start of the assembler file.  */
-
-struct options
-{
-  char *string;
-  int *variable;
-  int on_value;
-  char *description;
-};
-
-static int
-output_option (file, sep, type, name, indent, pos, max)
-     FILE *file;
-     char *sep;
-     char *type;
-     char *name;
-     char *indent;
-     int pos;
-     int max;
-{
-  if (strlen (sep) + strlen (type) + strlen (name) + pos > max)
-    {
-      fprintf (file, indent);
-      return fprintf (file, "%s%s", type, name);
-    }
-  return pos + fprintf (file, "%s%s%s", sep, type, name);
-}
-
-static struct { char *name; int value; } m_options[] = TARGET_SWITCHES;
-
-static void
-output_options (file, f_options, f_len, W_options, W_len,
-		pos, max, sep, indent, term)
-     FILE *file;
-     struct options *f_options;
-     struct options *W_options;
-     int f_len, W_len;
-     int pos;
-     int max;
-     char *indent;
-     char *term;
-{
-  register int j;
-
-  if (optimize)
-    pos = output_option (file, sep, "-O", "", indent, pos, max);
-  if (write_symbols != NO_DEBUG)
-    pos = output_option (file, sep, "-g", "", indent, pos, max);
-  if (flag_traditional)
-    pos = output_option (file, sep, "-traditional", "", indent, pos, max);
-  if (profile_flag)
-    pos = output_option (file, sep, "-p", "", indent, pos, max);
-  if (profile_block_flag)
-    pos = output_option (file, sep, "-a", "", indent, pos, max);
-
-  for (j = 0; j < f_len; j++)
-    if (*f_options[j].variable == f_options[j].on_value)
-      pos = output_option (file, sep, "-f", f_options[j].string,
-			   indent, pos, max);
-
-  for (j = 0; j < W_len; j++)
-    if (*W_options[j].variable == W_options[j].on_value)
-      pos = output_option (file, sep, "-W", W_options[j].string,
-			   indent, pos, max);
-
-  for (j = 0; j < sizeof m_options / sizeof m_options[0]; j++)
-    if (m_options[j].name[0] != '\0'
-	&& m_options[j].value > 0
-	&& ((m_options[j].value & target_flags)
-	    == m_options[j].value))
-      pos = output_option (file, sep, "-m", m_options[j].name,
-			   indent, pos, max);
-
-  if (m88k_short_data)
-    pos = output_option (file, sep, "-mshort-data-", m88k_short_data,
-			 indent, pos, max);
-
-  fprintf (file, term);
-}
-
-void
-output_file_start (file, f_options, f_len, W_options, W_len)
-     FILE *file;
-     struct options *f_options;
-     struct options *W_options;
-     int f_len, W_len;
-{
-  register int pos;
-
-  ASM_FIRST_LINE (file);
-  if (TARGET_88110
-      && TARGET_SVR4)
-    fprintf (file, "\t%s\n", REQUIRES_88110_ASM_OP);
-  output_file_directive (file, main_input_filename);
-  /* Switch to the data section so that the coffsem symbol and the
-     gcc2_compiled. symbol aren't in the text section.  */
-  data_section ();
-  ASM_COFFSEM (file);
-
-  if (TARGET_IDENTIFY_REVISION)
-    {
-      char indent[256];
-
-      time_t now = time ((time_t *)0);
-      sprintf (indent, "]\"\n\t%s\t \"@(#)%s [", IDENT_ASM_OP, main_input_filename);
-      fprintf (file, indent+3);
-      pos = fprintf (file, "gcc %s, %.24s,", VERSION_STRING, ctime (&now));
-#if 1
-      /* ??? It would be nice to call print_switch_values here (and thereby
-	 let us delete output_options) but this is kept in until it is known
-	 whether the change in content format matters.  */
-      output_options (file, f_options, f_len, W_options, W_len,
-		      pos, 150 - strlen (indent), " ", indent, "]\"\n\n");
-#else
-      fprintf (file, "]\"\n");
-      print_switch_values (file, 0, 150 - strlen (indent),
-			   indent + 3, " ", "]\"\n");
-#endif
-    }
-}
-
-/* Output an ascii string.  */
-
-void
-output_ascii (file, opcode, max, p, size)
-     FILE *file;
-     char *opcode;
-     int max;
-     unsigned char *p;
-     int size;
-{
-  int i;
-  int in_escape = 0;
-
-  register int num = 0;
-
-  fprintf (file, "\t%s\t \"", opcode);
-  for (i = 0; i < size; i++)
-    {
-      register int c = p[i];
-
-      if (num > max)
-	{
-	  fprintf (file, "\"\n\t%s\t \"", opcode);
-	  num = 0;
-	}
-	  
-      if (c == '\"' || c == '\\')
-	{
-	escape:
-	  putc ('\\', file);
-	  putc (c, file);
-	  num += 2;
-	  in_escape = 0;
-	}
-      else if (in_escape && c >= '0' && c <= '9')
-	{
-	  /* If a digit follows an octal-escape, the Vax assembler fails
-	     to stop reading the escape after three digits.  Continue to
-	     output the values as an octal-escape until a non-digit is
-	     found.  */
-	  fprintf (file, "\\%03o", c);
-	  num += 4;
-	}
-      else if ((c >= ' ' && c < 0177) || (c == '\t'))
-	{
-	  putc (c, file);
-	  num++;
-	  in_escape = 0;
-	}
-      else
-	{
-	  switch (c)
-	    {
-	      /* Some assemblers can't handle \a, \v, or \?.  */
-	    case '\f': c = 'f'; goto escape;
-	    case '\b': c = 'b'; goto escape;
-	    case '\r': c = 'r'; goto escape;
-	    case '\n': c = 'n'; goto escape;
-	    }
-
-	  fprintf (file, "\\%03o", c);
-	  num += 4;
-	  in_escape = 1;
-	}
-    }
-  fprintf (file, "\"\n");
-}
-
-/* Output a label (allows insn-output.c to be compiled without including
-   m88k.c or needing to include stdio.h).  */
-
-void
-output_label (label_number)
-     int label_number;
-{
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", label_number);
-}
-
-/* Generate the assembly code for function entry.
-
-   The prologue is responsible for setting up the stack frame,
-   initializing the frame pointer register, saving registers that must be
-   saved, and allocating SIZE additional bytes of storage for the
-   local variables.  SIZE is an integer.  FILE is a stdio
-   stream to which the assembler code should be output.
-
-   The label for the beginning of the function need not be output by this
-   macro.  That has already been done when the macro is run.
-
-   To determine which registers to save, the macro can refer to the array
-   `regs_ever_live': element R is nonzero if hard register
-   R is used anywhere within the function.  This implies the
-   function prologue should save register R, but not if it is one
-   of the call-used registers.
-
-   On machines where functions may or may not have frame-pointers, the
-   function entry code must vary accordingly; it must set up the frame
-   pointer if one is wanted, and not otherwise.  To determine whether a
-   frame pointer is in wanted, the macro can refer to the variable
-   `frame_pointer_needed'.  The variable's value will be 1 at run
-   time in a function that needs a frame pointer.
-
-   On machines where an argument may be passed partly in registers and
-   partly in memory, this macro must examine the variable
-   `current_function_pretend_args_size', and allocate that many bytes
-   of uninitialized space on the stack just underneath the first argument
-   arriving on the stack.  (This may not be at the very end of the stack,
-   if the calling sequence has pushed anything else since pushing the stack
-   arguments.  But usually, on such machines, nothing else has been pushed
-   yet, because the function prologue itself does all the pushing.)
-
-   If `ACCUMULATE_OUTGOING_ARGS' is defined, the variable
-   `current_function_outgoing_args_size' contains the size in bytes
-   required for the outgoing arguments.  This macro must add that
-   amount of uninitialized space to very bottom of the stack.
-
-   The stack frame we use looks like this:
-
- caller                                                  callee
-        |==============================================|
-        |                caller's frame                |
-        |==============================================|
-        |     [caller's outgoing memory arguments]     |
-        |==============================================|
-        |  caller's outgoing argument area (32 bytes)  |
-  sp -> |==============================================| <- ap
-        |            [local variable space]            |
-        |----------------------------------------------|
-        |            [return address (r1)]             |
-        |----------------------------------------------|
-        |        [previous frame pointer (r30)]        |
-        |==============================================| <- fp
-        |       [preserved registers (r25..r14)]       |
-        |----------------------------------------------|
-        |       [preserved registers (x29..x22)]       |
-        |==============================================|
-        |    [dynamically allocated space (alloca)]    |
-        |==============================================|
-        |     [callee's outgoing memory arguments]     |
-        |==============================================|
-        | [callee's outgoing argument area (32 bytes)] |
-        |==============================================| <- sp
-
-  Notes:
-
-  r1 and r30 must be saved if debugging.
-
-  fp (if present) is located two words down from the local
-  variable space.
-  */
-
-static void emit_add ();
-static void preserve_registers ();
-static void emit_ldst ();
-static void output_tdesc ();
-
-static int  nregs;
-static int  nxregs;
-static char save_regs[FIRST_PSEUDO_REGISTER];
-static int  frame_laid_out;
-static int  frame_size;
-static int  variable_args_p;
-static int  epilogue_marked;
-static int  prologue_marked;
-
-extern char call_used_regs[];
-extern int  current_function_pretend_args_size;
-extern int  current_function_outgoing_args_size;
-extern int  frame_pointer_needed;
-
-#define FIRST_OCS_PRESERVE_REGISTER	14
-#define LAST_OCS_PRESERVE_REGISTER	30
-
-#define FIRST_OCS_EXTENDED_PRESERVE_REGISTER	(32 + 22)
-#define LAST_OCS_EXTENDED_PRESERVE_REGISTER	(32 + 31)
-
-#define STACK_UNIT_BOUNDARY (STACK_BOUNDARY / BITS_PER_UNIT)
-#define ROUND_CALL_BLOCK_SIZE(BYTES) \
-  (((BYTES) + (STACK_UNIT_BOUNDARY - 1)) & ~(STACK_UNIT_BOUNDARY - 1))
-
-/* Establish the position of the FP relative to the SP.  This is done
-   either during FUNCTION_PROLOGUE or by INITIAL_ELIMINATION_OFFSET.  */
-
-void
-m88k_layout_frame ()
-{
-  int regno, sp_size;
-
-  frame_laid_out++;
-
-  bzero ((char *) &save_regs[0], sizeof (save_regs));
-  sp_size = nregs = nxregs = 0;
-  frame_size = get_frame_size ();
-
-  /* Since profiling requires a call, make sure r1 is saved.  */
-  if (profile_flag || profile_block_flag)
-    save_regs[1] = 1;
-
-  /* If we are producing debug information, store r1 and r30 where the
-     debugger wants to find them (r30 at r30+0, r1 at r30+4).  Space has
-     already been reserved for r1/r30 in STARTING_FRAME_OFFSET.  */
-  if (write_symbols != NO_DEBUG && !TARGET_OCS_FRAME_POSITION)
-    save_regs[1] = 1;
-
-  /* If there is a call, alloca is used, __builtin_alloca is used, or
-     a dynamic-sized object is defined, add the 8 additional words
-     for the callee's argument area.  The common denominator is that the
-     FP is required.  may_call_alloca only gets calls to alloca;
-     current_function_calls_alloca gets alloca and __builtin_alloca.  */
-  if (regs_ever_live[1] || frame_pointer_needed)
-    {
-      save_regs[1] = 1;
-      sp_size += REG_PARM_STACK_SPACE (0);
-    }
-
-  /* If we are producing PIC, save the addressing base register and r1.  */
-  if (flag_pic && current_function_uses_pic_offset_table)
-    {
-      save_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
-      nregs++;
-    }
-
-  /* If a frame is requested, save the previous FP, and the return
-     address (r1), so that a traceback can be done without using tdesc
-     information.  Otherwise, simply save the FP if it is used as
-     a preserve register.  */
-  if (frame_pointer_needed)
-    save_regs[FRAME_POINTER_REGNUM] = save_regs[1] = 1;
-  else if (regs_ever_live[FRAME_POINTER_REGNUM])
-    save_regs[FRAME_POINTER_REGNUM] = 1;
-
-  /* Figure out which extended register(s) needs to be saved.  */
-  for (regno = FIRST_EXTENDED_REGISTER + 1; regno < FIRST_PSEUDO_REGISTER;
-       regno++)
-    if (regs_ever_live[regno] && ! call_used_regs[regno])
-      {
-	save_regs[regno] = 1;
-	nxregs++;
-      }
-
-  /* Figure out which normal register(s) needs to be saved.  */
-  for (regno = 2; regno < FRAME_POINTER_REGNUM; regno++)
-    if (regs_ever_live[regno] && ! call_used_regs[regno])
-      {
-	save_regs[regno] = 1;
-	nregs++;
-      }
-
-  /* Achieve greatest use of double memory ops.  Either we end up saving
-     r30 or we use that slot to align the registers we do save.  */
-  if (nregs >= 2 && save_regs[1] && !save_regs[FRAME_POINTER_REGNUM])
-    sp_size += 4;
-
-  nregs += save_regs[1] + save_regs[FRAME_POINTER_REGNUM];
-  /* if we need to align extended registers, add a word */
-  if (nxregs > 0 && (nregs & 1) != 0)
-    sp_size +=4;
-  sp_size += 4 * nregs;
-  sp_size += 8 * nxregs;
-  sp_size += current_function_outgoing_args_size;
-
-  /* The first two saved registers are placed above the new frame pointer
-     if any.  In the only case this matters, they are r1 and r30. */
-  if (frame_pointer_needed || sp_size)
-    m88k_fp_offset = ROUND_CALL_BLOCK_SIZE (sp_size - STARTING_FRAME_OFFSET);
-  else
-    m88k_fp_offset = -STARTING_FRAME_OFFSET;
-  m88k_stack_size = m88k_fp_offset + STARTING_FRAME_OFFSET;
-
-  /* First, combine m88k_stack_size and size.  If m88k_stack_size is
-     non-zero, align the frame size to 8 mod 16; otherwise align the
-     frame size to 0 mod 16.  (If stacks are 8 byte aligned, this ends
-     up as a NOP.  */
-  {
-    int need
-      = ((m88k_stack_size ? STACK_UNIT_BOUNDARY - STARTING_FRAME_OFFSET : 0)
-	 - (frame_size % STACK_UNIT_BOUNDARY));
-    if (need)
-      {
-	if (need < 0)
-	  need += STACK_UNIT_BOUNDARY;
-	(void) assign_stack_local (BLKmode, need, BITS_PER_UNIT);
-	frame_size = get_frame_size ();
-      }
-    m88k_stack_size
-      = ROUND_CALL_BLOCK_SIZE (m88k_stack_size + frame_size
-			       + current_function_pretend_args_size);
-  }
-}
-
-/* Return true if this function is known to have a null prologue.  */
-
-int
-null_prologue ()
-{
-  if (! reload_completed)
-    return 0;
-  if (! frame_laid_out)
-    m88k_layout_frame ();
-  return (! frame_pointer_needed
-	  && nregs == 0
-	  && nxregs == 0
-	  && m88k_stack_size == 0);
-}
-
-/* Determine if the current function has any references to the arg pointer.
-   This is done indirectly by examining the DECL_ARGUMENTS' DECL_RTL.
-   It is OK to return TRUE if there are no references, but FALSE must be
-   correct.  */
-
-static int
-uses_arg_area_p ()
-{
-  register tree parm;
-
-  if (current_function_decl == 0
-      || current_function_varargs
-      || variable_args_p)
-    return 1;
-
-  for (parm = DECL_ARGUMENTS (current_function_decl);
-       parm;
-       parm = TREE_CHAIN (parm))
-    {
-      if (DECL_RTL (parm) == 0
-	  || GET_CODE (DECL_RTL (parm)) == MEM)
-	return 1;
-
-      if (DECL_INCOMING_RTL (parm) == 0
-	  || GET_CODE (DECL_INCOMING_RTL (parm)) == MEM)
-	return 1;
-    }
-  return 0;
-}
-
-void
-m88k_begin_prologue (stream, size)
-     FILE *stream;
-     int size;
-{
-  if (TARGET_OMIT_LEAF_FRAME_POINTER && ! quiet_flag && leaf_function_p ())
-    fprintf (stderr, "$");
-
-  m88k_prologue_done = 1;	/* it's ok now to put out ln directives */
-}
-
-void
-m88k_end_prologue (stream)
-     FILE *stream;
-{
-  if (TARGET_OCS_DEBUG_INFO && !prologue_marked)
-    {
-      PUT_OCS_FUNCTION_START (stream);
-      prologue_marked = 1;
-
-      /* If we've already passed the start of the epilogue, say that
-	 it starts here.  This marks the function as having a null body,
-	 but at a point where the return address is in a known location.
-
-	 Originally, I thought this couldn't happen, but the pic prologue
-	 for leaf functions ends with the instruction that restores the
-	 return address from the temporary register.  If the temporary
-	 register is never used, that instruction can float all the way
-	 to the end of the function.  */
-      if (epilogue_marked)
-	PUT_OCS_FUNCTION_END (stream);
-    }
-}
-
-void
-m88k_expand_prologue ()
-{
-  m88k_layout_frame ();
-
-  if (TARGET_OPTIMIZE_ARG_AREA
-      && m88k_stack_size
-      && ! uses_arg_area_p ())
-    {
-      /* The incoming argument area is used for stack space if it is not
-	 used (or if -mno-optimize-arg-area is given).  */
-      if ((m88k_stack_size -= REG_PARM_STACK_SPACE (0)) < 0)
-	m88k_stack_size = 0;
-    }
-
-  if (m88k_stack_size)
-    emit_add (stack_pointer_rtx, stack_pointer_rtx, -m88k_stack_size);
-
-  if (nregs || nxregs)
-    preserve_registers (m88k_fp_offset + 4, 1);
-
-  if (frame_pointer_needed)
-    emit_add (frame_pointer_rtx, stack_pointer_rtx, m88k_fp_offset);
-
-  if (flag_pic && save_regs[PIC_OFFSET_TABLE_REGNUM])
-    {
-      rtx return_reg = gen_rtx (REG, SImode, 1);
-      rtx label = gen_label_rtx ();
-      rtx temp_reg;
-
-      if (! save_regs[1])
-	{
-	  temp_reg = gen_rtx (REG, SImode, TEMP_REGNUM);
-	  emit_move_insn (temp_reg, return_reg);
-	}
-      emit_insn (gen_locate1 (pic_offset_table_rtx, label));
-      emit_insn (gen_locate2 (pic_offset_table_rtx, label));
-      emit_insn (gen_addsi3 (pic_offset_table_rtx,
-			     pic_offset_table_rtx, return_reg));
-      if (! save_regs[1])
-	emit_move_insn (return_reg, temp_reg);
-    }
-  if (profile_flag || profile_block_flag)
-    emit_insn (gen_blockage ());
-}
-
-/* This function generates the assembly code for function exit,
-   on machines that need it.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only, if there is a frame pointer.
-   This is mandatory because of alloca; we also take advantage of it to
-   omit stack adjustments before returning.  */
-
-void
-m88k_begin_epilogue (stream)
-     FILE *stream;
-{
-  if (TARGET_OCS_DEBUG_INFO && !epilogue_marked && prologue_marked)
-    {
-      PUT_OCS_FUNCTION_END (stream);
-    }
-  epilogue_marked = 1;
-}
-
-void
-m88k_end_epilogue (stream, size)
-     FILE *stream;
-     int size;
-{
-  rtx insn = get_last_insn ();
-
-  if (TARGET_OCS_DEBUG_INFO && !epilogue_marked)
-    PUT_OCS_FUNCTION_END (stream);
-
-  /* If the last insn isn't a BARRIER, we must write a return insn.  This
-     should only happen if the function has no prologue and no body.  */
-  if (GET_CODE (insn) == NOTE)
-    insn = prev_nonnote_insn (insn);
-  if (insn == 0 || GET_CODE (insn) != BARRIER)
-    fprintf (stream, "\tjmp\t %s\n", reg_names[1]);
-
-  /* If the last insn is a barrier, and the insn before that is a call,
-     then add a nop instruction so that tdesc can walk the stack correctly
-     even though there is no epilogue. (Otherwise, the label for the
-     end of the tdesc region ends up at the start of the next function. */
-  if (insn && GET_CODE (insn) == BARRIER)
-    {
-      insn = prev_nonnote_insn (insn);
-      if (insn && GET_CODE (insn) == CALL_INSN)
-        fprintf (stream, "\tor\t %s,%s,%s\n",reg_names[0],reg_names[0],reg_names[0]);
-    }
-
-  output_short_branch_defs (stream);
-
-  fprintf (stream, "\n");
-
-  if (TARGET_OCS_DEBUG_INFO)
-    output_tdesc (stream, m88k_fp_offset + 4);
-
-  m88k_function_number++;
-  m88k_prologue_done	= 0;		/* don't put out ln directives */
-  variable_args_p	= 0;		/* has variable args */
-  frame_laid_out	= 0;
-  epilogue_marked	= 0;
-  prologue_marked	= 0;
-}
-
-void
-m88k_expand_epilogue ()
-{
-#if (MONITOR_GCC & 0x4) /* What are interesting prologue/epilogue values?  */
-  fprintf (stream, "; size = %d, m88k_fp_offset = %d, m88k_stack_size = %d\n",
-	   size, m88k_fp_offset, m88k_stack_size);
-#endif
-
-  if (frame_pointer_needed)
-    emit_add (stack_pointer_rtx, frame_pointer_rtx, -m88k_fp_offset);
-
-  if (nregs || nxregs)
-    preserve_registers (m88k_fp_offset + 4, 0);
-
-  if (m88k_stack_size)
-    emit_add (stack_pointer_rtx, stack_pointer_rtx, m88k_stack_size);
-}
-
-/* Emit insns to set DSTREG to SRCREG + AMOUNT during the prologue or
-   epilogue.  */
-
-static void
-emit_add (dstreg, srcreg, amount)
-     rtx dstreg;
-     rtx srcreg;
-     int amount;
-{
-  rtx incr = GEN_INT (abs (amount));
-  if (! ADD_INTVAL (amount))
-    {
-      rtx temp = gen_rtx (REG, SImode, TEMP_REGNUM);
-      emit_move_insn (temp, incr);
-      incr = temp;
-    }
-  emit_insn ((amount < 0 ? gen_subsi3 : gen_addsi3) (dstreg, srcreg, incr));
-}
-
-/* Save/restore the preserve registers.  base is the highest offset from
-   r31 at which a register is stored.  store_p is true if stores are to
-   be done; otherwise loads.  */
-
-static void
-preserve_registers (base, store_p)
-     int base;
-     int store_p;
-{
-  int regno, offset;
-  struct mem_op {
-    int regno;
-    int nregs;
-    int offset;
-  } mem_op[FIRST_PSEUDO_REGISTER];
-  struct mem_op *mo_ptr = mem_op;
-
-  /* The 88open OCS mandates that preserved registers be stored in
-     increasing order.  For compatibility with current practice,
-     the order is r1, r30, then the preserve registers.  */
-
-  offset = base;
-  if (save_regs[1])
-    {
-      /* An extra word is given in this case to make best use of double
-	 memory ops.  */
-      if (nregs > 2 && !save_regs[FRAME_POINTER_REGNUM])
-	offset -= 4;
-      emit_ldst (store_p, 1, SImode, offset);
-      offset -= 4;
-      base = offset;
-    }
-
-  /* Walk the registers to save recording all single memory operations.  */
-  for (regno = FRAME_POINTER_REGNUM; regno > 1; regno--)
-    if (save_regs[regno])
-      {
-	if ((offset & 7) != 4 || (regno & 1) != 1 || !save_regs[regno-1])
-	  {
-	    mo_ptr->nregs = 1;
-	    mo_ptr->regno = regno;
-	    mo_ptr->offset = offset;
-	    mo_ptr++;
-	    offset -= 4;
-	  }
-        else
-	  {
-	    regno--;
-	    offset -= 2*4;
-	  }
-      }
-
-  /* Walk the registers to save recording all double memory operations.
-     This avoids a delay in the epilogue (ld.d/ld).  */
-  offset = base;
-  for (regno = FRAME_POINTER_REGNUM; regno > 1; regno--)
-    if (save_regs[regno])
-      {
-	if ((offset & 7) != 4 || (regno & 1) != 1 || !save_regs[regno-1])
-	  {
-	    offset -= 4;
-	  }
-        else
-	  {
-	    mo_ptr->nregs = 2;
-	    mo_ptr->regno = regno-1;
-	    mo_ptr->offset = offset-4;
-	    mo_ptr++;
-	    regno--;
-	    offset -= 2*4;
-	  }
-      }
-
-  /* Walk the extended registers to record all memory operations.  */
-  /*  Be sure the offset is double word aligned.  */
-  offset = (offset - 1) & ~7;
-  for (regno = FIRST_PSEUDO_REGISTER - 1; regno > FIRST_EXTENDED_REGISTER;
-       regno--)
-    if (save_regs[regno])
-      {
-	mo_ptr->nregs = 2;
-	mo_ptr->regno = regno;
-	mo_ptr->offset = offset;
-	mo_ptr++;
-	offset -= 2*4;
-      }
-
-  mo_ptr->regno = 0;
-
-  /* Output the memory operations.  */
-  for (mo_ptr = mem_op; mo_ptr->regno; mo_ptr++)
-    {
-      if (mo_ptr->nregs)
-	emit_ldst (store_p, mo_ptr->regno,
-		   (mo_ptr->nregs > 1 ? DImode : SImode),
-		   mo_ptr->offset);
-    }
-}
-
-static void
-emit_ldst (store_p, regno, mode, offset)
-     int store_p;
-     int regno;
-     enum machine_mode mode;
-     int offset;
-{
-  rtx reg = gen_rtx (REG, mode, regno);
-  rtx mem;
-
-  if (SMALL_INTVAL (offset))
-    {
-      mem = gen_rtx (MEM, mode, plus_constant (stack_pointer_rtx, offset));
-    }
-  else
-    {
-      /* offset is too large for immediate index must use register */
-
-      rtx disp = GEN_INT (offset);
-      rtx temp = gen_rtx (REG, SImode, TEMP_REGNUM);
-      rtx regi = gen_rtx (PLUS, SImode, stack_pointer_rtx, temp);
-      emit_move_insn (temp, disp);
-      mem = gen_rtx (MEM, mode, regi);
-    }
-
-  if (store_p)
-    emit_move_insn (mem, reg);
-  else
-    emit_move_insn (reg, mem);
-}
-
-/* Convert the address expression REG to a CFA offset.  */
-
-int
-m88k_debugger_offset (reg, offset)
-     register rtx reg;
-     register int offset;
-{
-  if (GET_CODE (reg) == PLUS)
-    {
-      offset = INTVAL (XEXP (reg, 1));
-      reg = XEXP (reg, 0);
-    }
-
-  /* Put the offset in terms of the CFA (arg pointer).  */
-  if (reg == frame_pointer_rtx)
-    offset += m88k_fp_offset - m88k_stack_size;
-  else if (reg == stack_pointer_rtx)
-    offset -= m88k_stack_size;
-  else if (reg != arg_pointer_rtx)
-    {
-#if (MONITOR_GCC & 0x10) /* Watch for suspicious symbolic locations.  */
-      if (! (GET_CODE (reg) == REG
-	     && REGNO (reg) >= FIRST_PSEUDO_REGISTER))
-	warning ("Internal gcc error: Can't express symbolic location");
-#endif
-      return 0;
-    }
-
-  return offset;
-}
-
-/* Output the 88open OCS proscribed text description information.
-   The information is:
-        0  8: zero
-	0 22: info-byte-length (16 or 20 bytes)
-	0  2: info-alignment (word 2)
-	1 32: info-protocol (version 1 or 2(pic))
-	2 32: starting-address (inclusive, not counting prologue)
-	3 32: ending-address (exclusive, not counting epilog)
-	4  8: info-variant (version 1 or 3(extended registers))
-	4 17: register-save-mask (from register 14 to 30)
-	4  1: zero
-	4  1: return-address-info-discriminant
-	4  5: frame-address-register
-	5 32: frame-address-offset
-	6 32: return-address-info
-	7 32: register-save-offset
-	8 16: extended-register-save-mask (x16 - x31)
-	8 16: extended-register-save-offset (WORDS from register-save-offset)  */
-
-static void
-output_tdesc (file, offset)
-     FILE *file;
-     int offset;
-{
-  int regno, i, j;
-  long mask, return_address_info, register_save_offset;
-  long xmask, xregister_save_offset;
-  char buf[256];
-
-  for (mask = 0, i = 0, regno = FIRST_OCS_PRESERVE_REGISTER;
-       regno <= LAST_OCS_PRESERVE_REGISTER;
-       regno++)
-    {
-      mask <<= 1;
-      if (save_regs[regno])
-	{
-	  mask |= 1;
-	  i++;
-	}
-    }
-
-  for (xmask = 0, j = 0, regno = FIRST_OCS_EXTENDED_PRESERVE_REGISTER;
-       regno <= LAST_OCS_EXTENDED_PRESERVE_REGISTER;
-       regno++)
-    {
-      xmask <<= 1;
-      if (save_regs[regno])
-	{
-	  xmask |= 1;
-	  j++;
-	}
-    }
-
-  if (save_regs[1])
-    {
-      if ((nxregs > 0 || nregs > 2) && !save_regs[FRAME_POINTER_REGNUM])
-	offset -= 4;
-      return_address_info = - m88k_stack_size + offset;
-      register_save_offset = return_address_info - i*4;
-    }
-  else
-    {
-      return_address_info = 1;
-      register_save_offset = - m88k_stack_size + offset + 4 - i*4;
-    }
-
-  xregister_save_offset = - (j * 2 + ((register_save_offset >> 2) & 1));
-
-  tdesc_section ();
-
-  fprintf (file, "\t%s\t %d,%d", INT_ASM_OP, /* 8:0,22:(20 or 16),2:2 */
-	   (((xmask != 0) ? 20 : 16) << 2) | 2,
-	   flag_pic ? 2 : 1);
-
-  ASM_GENERATE_INTERNAL_LABEL (buf, OCS_START_PREFIX, m88k_function_number);
-  fprintf (file, ",%s%s", buf+1, flag_pic ? "#rel" : "");
-  ASM_GENERATE_INTERNAL_LABEL (buf, OCS_END_PREFIX, m88k_function_number);
-  fprintf (file, ",%s%s", buf+1, flag_pic ? "#rel" : "");
-
-  fprintf (file, ",0x%x,0x%x,0x%x,0x%x",
-	   /* 8:1,17:0x%.3x,1:0,1:%d,5:%d */
-	   (((xmask ? 3 : 1) << (17+1+1+5))
-	    | (mask << (1+1+5))
-	    | ((!!save_regs[1]) << 5)
-	    | (frame_pointer_needed
-	       ? FRAME_POINTER_REGNUM
-	       : STACK_POINTER_REGNUM)),
-	   (m88k_stack_size - (frame_pointer_needed ? m88k_fp_offset : 0)),
-	   return_address_info,
-	   register_save_offset);
-  if (xmask)
-    fprintf (file, ",0x%x%04x", xmask, (0xffff & xregister_save_offset));
-  fputc ('\n', file);
-
-  text_section ();
-}
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  NAME is the mcount function name
-   (varies), SAVEP indicates whether the parameter registers need to
-   be saved and restored.  */
-
-void
-output_function_profiler (file, labelno, name, savep)
-     FILE *file;
-     int labelno;
-     char *name;
-     int savep;
-{
-  char label[256];
-  char dbi[256];
-  char *temp = (savep ? reg_names[2] : reg_names[10]);
-
-  /* Remember to update FUNCTION_PROFILER_LENGTH.  */
-
-  if (savep)
-    {
-      fprintf (file, "\tsubu\t %s,%s,64\n", reg_names[31], reg_names[31]);
-      fprintf (file, "\tst.d\t %s,%s,32\n", reg_names[2], reg_names[31]);
-      fprintf (file, "\tst.d\t %s,%s,40\n", reg_names[4], reg_names[31]);
-      fprintf (file, "\tst.d\t %s,%s,48\n", reg_names[6], reg_names[31]);
-      fprintf (file, "\tst.d\t %s,%s,56\n", reg_names[8], reg_names[31]);
-    }
-
-  ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
-  if (flag_pic == 2)
-    {
-      fprintf (file, "\tor.u\t %s,%s,%shi16(%s#got_rel)\n",
-	       temp, reg_names[0], m88k_pound_sign, &label[1]);
-      fprintf (file, "\tor\t %s,%s,%slo16(%s#got_rel)\n",
-	       temp, temp, m88k_pound_sign, &label[1]);
-      sprintf (dbi, "\tld\t %s,%s,%s\n", temp,
-	       reg_names[PIC_OFFSET_TABLE_REGNUM], temp);
-    }
-  else if (flag_pic)
-    {
-      sprintf (dbi, "\tld\t %s,%s,%s#got_rel\n", temp,
-	       reg_names[PIC_OFFSET_TABLE_REGNUM], &label[1]);
-    }
-  else
-    {
-      fprintf (file, "\tor.u\t %s,%s,%shi16(%s)\n",
-	       temp, reg_names[0], m88k_pound_sign, &label[1]);
-      sprintf (dbi, "\tor\t %s,%s,%slo16(%s)\n",
-	       temp, temp, m88k_pound_sign, &label[1]);
-    }
-
-  if (flag_pic)
-    fprintf (file, "\tbsr.n\t %s#plt\n", name);
-  else
-    fprintf (file, "\tbsr.n\t %s\n", name);
-  fputs (dbi, file);
-
-  if (savep)
-    {
-      fprintf (file, "\tld.d\t %s,%s,32\n", reg_names[2], reg_names[31]);
-      fprintf (file, "\tld.d\t %s,%s,40\n", reg_names[4], reg_names[31]);
-      fprintf (file, "\tld.d\t %s,%s,48\n", reg_names[6], reg_names[31]);
-      fprintf (file, "\tld.d\t %s,%s,56\n", reg_names[8], reg_names[31]);
-      fprintf (file, "\taddu\t %s,%s,64\n", reg_names[31], reg_names[31]);
-    }
-}
-
-/* Output assembler code to FILE to initialize basic-block profiling for
-   the current module.  LABELNO is unique to each instance.  */
-
-void
-output_function_block_profiler (file, labelno)
-     FILE *file;
-     int labelno;
-{
-  char block[256];
-  char label[256];
-
-  /* Remember to update FUNCTION_BLOCK_PROFILER_LENGTH.  */
-
-  ASM_GENERATE_INTERNAL_LABEL (block, "LPBX", 0);
-  ASM_GENERATE_INTERNAL_LABEL (label, "LPY", labelno);
-
-  /* @@ Need to deal with PIC.  I'm not sure what the requirements are on
-     register usage, so I used r26/r27 to be safe.  */
-  fprintf (file, "\tor.u\t %s,%s,%shi16(%s)\n", reg_names[27], reg_names[0],
-		 m88k_pound_sign, &block[1]);
-  fprintf (file, "\tld\t %s,%s,%slo16(%s)\n", reg_names[26], reg_names[27],
-		 m88k_pound_sign, &block[1]);
-  fprintf (file, "\tbcnd\t %sne0,%s,%s\n",
-		 m88k_pound_sign, reg_names[26], &label[1]);
-  fprintf (file, "\tsubu\t %s,%s,64\n", reg_names[31], reg_names[31]);
-  fprintf (file, "\tst.d\t %s,%s,32\n", reg_names[2], reg_names[31]);
-  fprintf (file, "\tst.d\t %s,%s,40\n", reg_names[4], reg_names[31]);
-  fprintf (file, "\tst.d\t %s,%s,48\n", reg_names[6], reg_names[31]);
-  fprintf (file, "\tst.d\t %s,%s,56\n", reg_names[8], reg_names[31]);
-  fputs ("\tbsr.n\t ", file);
-  ASM_OUTPUT_LABELREF (file, "__bb_init_func");
-  putc ('\n', file);
-  fprintf (file, "\tor\t %s,%s,%slo16(%s)\n", reg_names[2], reg_names[27],
-		 m88k_pound_sign, &block[1]);
-  fprintf (file, "\tld.d\t %s,%s,32\n", reg_names[2], reg_names[31]);
-  fprintf (file, "\tld.d\t %s,%s,40\n", reg_names[4], reg_names[31]);
-  fprintf (file, "\tld.d\t %s,%s,48\n", reg_names[6], reg_names[31]);
-  fprintf (file, "\tld.d\t %s,%s,56\n", reg_names[8], reg_names[31]);
-  fprintf (file, "\taddu\t %s,%s,64\n", reg_names[31], reg_names[31]);
-  ASM_OUTPUT_INTERNAL_LABEL (file, "LPY", labelno);
-}
-
-/* Output assembler code to FILE to increment the count associated with
-   the basic block number BLOCKNO.  */
-
-void
-output_block_profiler (file, blockno)
-     FILE *file;
-     int blockno;
-{
-  char block[256];
-
-  /* Remember to update BLOCK_PROFILER_LENGTH.  */
-
-  ASM_GENERATE_INTERNAL_LABEL (block, "LPBX", 2);
-
-  /* @@ Need to deal with PIC.  I'm not sure what the requirements are on
-     register usage, so I used r26/r27 to be safe.  */
-  fprintf (file, "\tor.u\t %s,%s,%shi16(%s+%d)\n", reg_names[27], reg_names[0],
-	   m88k_pound_sign, &block[1], 4 * blockno);
-  fprintf (file, "\tld\t %s,%s,%slo16(%s+%d)\n", reg_names[26], reg_names[27],
-	   m88k_pound_sign, &block[1], 4 * blockno);
-  fprintf (file, "\taddu\t %s,%s,1\n", reg_names[26], reg_names[26]);
-  fprintf (file, "\tst\t %s,%s,%slo16(%s+%d)\n", reg_names[26], reg_names[27],
-	   m88k_pound_sign, &block[1], 4 * blockno);
-}
-
-/* Determine whether a function argument is passed in a register, and
-   which register.
-
-   The arguments are CUM, which summarizes all the previous
-   arguments; MODE, the machine mode of the argument; TYPE,
-   the data type of the argument as a tree node or 0 if that is not known
-   (which happens for C support library functions); and NAMED,
-   which is 1 for an ordinary argument and 0 for nameless arguments that
-   correspond to `...' in the called function's prototype.
-
-   The value of the expression should either be a `reg' RTX for the
-   hard register in which to pass the argument, or zero to pass the
-   argument on the stack.
-
-   On the m88000 the first eight words of args are normally in registers
-   and the rest are pushed.  Double precision floating point must be
-   double word aligned (and if in a register, starting on an even
-   register). Structures and unions which are not 4 byte, and word
-   aligned are passed in memory rather than registers, even if they
-   would fit completely in the registers under OCS rules.
-
-   Note that FUNCTION_ARG and FUNCTION_INCOMING_ARG were different.
-   For structures that are passed in memory, but could have been
-   passed in registers, we first load the structure into the
-   register, and then when the last argument is passed, we store
-   the registers into the stack locations.  This fixes some bugs
-   where GCC did not expect to have register arguments, followed
-   by stack arguments, followed by register arguments.  */
-
-struct rtx_def *
-m88k_function_arg (args_so_far, mode, type, named)
-     CUMULATIVE_ARGS args_so_far;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int bytes, words;
-
-  if (type != 0			/* undo putting struct in register */
-      && (TREE_CODE (type) == RECORD_TYPE || TREE_CODE (type) == UNION_TYPE))
-    mode = BLKmode;
-
-  if (mode == BLKmode && TARGET_WARN_PASS_STRUCT)
-    warning ("argument #%d is a structure", args_so_far + 1);
-
-  if ((args_so_far & 1) != 0
-      && (mode == DImode || mode == DFmode
-	  || (type != 0 && TYPE_ALIGN (type) > 32)))
-    args_so_far++;
-
-#ifdef ESKIT
-  if (no_reg_params)
-    return (rtx) 0;             /* don't put args in registers */
-#endif
-
-  if (type == 0 && mode == BLKmode)
-    abort ();	/* m88k_function_arg argument `type' is NULL for BLKmode. */
-
-  bytes = (mode != BLKmode) ? GET_MODE_SIZE (mode) : int_size_in_bytes (type);
-  words = (bytes + 3) / 4;
-
-  if (args_so_far + words > 8)
-    return (rtx) 0;             /* args have exhausted registers */
-
-  else if (mode == BLKmode
-	   && (TYPE_ALIGN (type) != BITS_PER_WORD
-	       || bytes != UNITS_PER_WORD))
-    return (rtx) 0;
-
-  return gen_rtx (REG,
-		  ((mode == BLKmode) ? TYPE_MODE (type) : mode),
-		  2 + args_so_far);
-}
-
-/* Do what is necessary for `va_start'.  The argument is ignored;
-   We look at the current function to determine if stdargs or varargs
-   is used and fill in an initial va_list.  A pointer to this constructor
-   is returned.  */
-
-struct rtx_def *
-m88k_builtin_saveregs (arglist)
-     tree arglist;
-{
-  rtx block, addr, argsize, dest;
-  tree fntype = TREE_TYPE (current_function_decl);
-  int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
-		   && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
-		       != void_type_node)))
-		? -UNITS_PER_WORD : 0) + UNITS_PER_WORD - 1;
-  int fixed;
-  variable_args_p = 1;
-
-  if (CONSTANT_P (current_function_arg_offset_rtx))
-    {
-      fixed = (XINT (current_function_arg_offset_rtx, 0)
-	       + argadj) / UNITS_PER_WORD;
-      argsize = GEN_INT (fixed);
-    }
-  else
-    {
-      fixed = 0;
-      argsize = plus_constant (current_function_arg_offset_rtx, argadj);
-      argsize = expand_shift (RSHIFT_EXPR, Pmode, argsize,
-			      build_int_2 (2, 0), argsize, 0);
-    }
-
-  /* Allocate the va_list constructor */
-  block = assign_stack_local (BLKmode, 3 * UNITS_PER_WORD, BITS_PER_WORD);
-  MEM_SET_IN_STRUCT_P (block, 1);
-  RTX_UNCHANGING_P (block) = 1;
-  RTX_UNCHANGING_P (XEXP (block, 0)) = 1;
-
-  /* Store the argsize as the __va_arg member.  */
-  emit_move_insn (change_address (block, SImode, XEXP (block, 0)),
-		  argsize);
-
-  /* Store the arg pointer in the __va_stk member.  */
-  emit_move_insn (change_address (block, Pmode,
-				  plus_constant (XEXP (block, 0),
-						 UNITS_PER_WORD)),
-		  copy_to_reg (virtual_incoming_args_rtx));
-
-  /* Allocate the register space, and store it as the __va_reg member.  */
-  addr = assign_stack_local (BLKmode, 8 * UNITS_PER_WORD, -1);
-  MEM_SET_IN_STRUCT_P (addr, 1);
-  RTX_UNCHANGING_P (addr) = 1;
-  RTX_UNCHANGING_P (XEXP (addr, 0)) = 1;
-  emit_move_insn (change_address (block, Pmode,
-				  plus_constant (XEXP (block, 0),
-						 2 * UNITS_PER_WORD)),
-		  copy_to_reg (XEXP (addr, 0)));
-
-  /* Now store the incoming registers.  */
-  if (fixed < 8)
-    {
-      dest = change_address (addr, Pmode,
-			     plus_constant (XEXP (addr, 0),
-					    fixed * UNITS_PER_WORD));
-      move_block_from_reg (2 + fixed, dest, 8 - fixed,
-			   UNITS_PER_WORD * (8 - fixed));
-    }
-
-  if (current_function_check_memory_usage)
-    {
-      emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
-			 block, ptr_mode,
-			 GEN_INT (3 * UNITS_PER_WORD), TYPE_MODE (sizetype),
-			 GEN_INT (MEMORY_USE_RW),
-			 TYPE_MODE (integer_type_node));
-      if (fixed < 8)
-	emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
-			   dest, ptr_mode,
-			   GEN_INT (UNITS_PER_WORD * (8 - fixed)),
-			   TYPE_MODE (sizetype),
-			   GEN_INT (MEMORY_USE_RW),
-			   TYPE_MODE (integer_type_node));
-    }
-
-  /* Return the address of the va_list constructor, but don't put it in a
-     register.  This fails when not optimizing and produces worse code when
-     optimizing.  */
-  return XEXP (block, 0);
-}
-
-/* If cmpsi has not been generated, emit code to do the test.  Return the
-   expression describing the test of operator OP.  */
-
-rtx
-emit_test (op, mode)
-     enum rtx_code op;
-     enum machine_mode mode;
-{
-  if (m88k_compare_reg == 0)
-    emit_insn (gen_test (m88k_compare_op0, m88k_compare_op1));
-  return (gen_rtx (op, mode, m88k_compare_reg, const0_rtx));
-}
-
-/* Determine how to best perform cmpsi/bxx, where cmpsi has a constant
-   operand.  All tests with zero (albeit swapped) and all equality tests
-   with a constant are done with bcnd.  The remaining cases are swapped
-   as needed.  */
-
-void
-emit_bcnd (op, label)
-     enum rtx_code op;
-     rtx label;
-{
-  if (m88k_compare_op1 == const0_rtx)
-    emit_jump_insn( gen_bcnd (
-			gen_rtx (op, VOIDmode,m88k_compare_op0, const0_rtx),
-			label));
-  else if (m88k_compare_op0 == const0_rtx)
-    emit_jump_insn( gen_bcnd(
-		      gen_rtx(
-			swap_condition (op),
-			VOIDmode, m88k_compare_op1, const0_rtx),
-		      label));
-  else if (op != EQ && op != NE)
-    emit_jump_insn (gen_bxx (emit_test (op, VOIDmode), label));
-  else
-    {
-      rtx zero = gen_reg_rtx (SImode);
-      rtx reg, constant;
-      int value;
-
-      if (GET_CODE (m88k_compare_op1) == CONST_INT)
-	{
-	  reg = force_reg (SImode, m88k_compare_op0);
-	  constant = m88k_compare_op1;
-	}
-      else
-	{
-	  reg = force_reg (SImode, m88k_compare_op1);
-	  constant = m88k_compare_op0;
-	}
-      value = INTVAL (constant);
-
-      /* Perform an arithmetic computation to make the compared-to value
-	 zero, but avoid loosing if the bcnd is later changed into sxx.  */
-      if (SMALL_INTVAL (value))
-	emit_jump_insn (gen_bxx (emit_test (op, VOIDmode), label));
-      else
-	{
-	  if (SMALL_INTVAL (-value))
-	    emit_insn (gen_addsi3 (zero, reg,
-				   GEN_INT (-value)));
-	  else
-	    emit_insn (gen_xorsi3 (zero, reg, constant));
-
-	  emit_jump_insn (gen_bcnd (gen_rtx (op, VOIDmode,
-					     zero, const0_rtx),
-				    label));
-	}
-    }
-}
-
-/* Print an operand.  Recognize special options, documented below.  */
-
-void
-print_operand (file, x, code)
-    FILE *file;
-    rtx x;
-    char code;
-{
-  enum rtx_code xc = (x ? GET_CODE (x) : UNKNOWN);
-  register int value = (xc == CONST_INT ? INTVAL (x) : 0);
-  static int sequencep;
-  static int reversep;
-
-  if (sequencep)
-    {
-      if (code < 'B' || code > 'E')
-	output_operand_lossage ("%R not followed by %B/C/D/E");
-      if (reversep)
-	xc = reverse_condition (xc);
-      sequencep = 0;
-    }
-
-  switch (code)
-    {
-    case '*': /* addressing base register for PIC */
-      fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file); return;
-
-    case '#': /* SVR4 pound-sign syntax character (empty if SVR3) */
-      fputs (m88k_pound_sign, file); return;
-
-    case 'V': /* Output a serializing instruction as needed if the operand
-		 (assumed to be a MEM) is a volatile load.  */
-    case 'v': /* ditto for a volatile store.  */
-      if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE)
-	{
-	  /* The m88110 implements two FIFO queues, one for loads and
-	     one for stores.  These queues mean that loads complete in
-	     their issue order as do stores.  An interaction between the
-	     history buffer and the store reservation station ensures
-	     that a store will not bypass load.  Finally, a load will not
-	     bypass store, but only when they reference the same address.
-
-	     To avoid this reordering (a load bypassing a store) for
-	     volatile references, a serializing instruction is output.
-	     We choose the fldcr instruction as it does not serialize on
-	     the m88100 so that -m88000 code will not be degraded.
-
-	     The mechanism below is completed by having CC_STATUS_INIT set
-	     the code to the unknown value.  */
-
-	  /*
-	     hassey 6/30/93
-	     A problem with 88110 4.1 & 4.2 makes the use of fldcr for
-	     this purpose undesirable.  Instead we will use tb1, this will
-	     cause serialization on the 88100 but such is life.
-	  */
-
-	  static rtx last_addr = 0;
-	  if (code == 'V' /* Only need to serialize before a load.  */
-	      && m88k_volatile_code != 'V' /* Loads complete in FIFO order.  */
-	      && !(m88k_volatile_code == 'v'
-		   && GET_CODE (XEXP (x, 0)) == LO_SUM
-		   && rtx_equal_p (XEXP (XEXP (x, 0), 1), last_addr)))
-	    fprintf (file,
-#if 0
-#ifdef AS_BUG_FLDCR
-		     "fldcr\t %s,%scr63\n\t",
-#else
-		     "fldcr\t %s,%sfcr63\n\t",
-#endif
-		     reg_names[0], m88k_pound_sign);
-#else /* 0 */
-		     "tb1\t 1,%s,0xff\n\t", reg_names[0]);
-#endif /* 0 */
-	  m88k_volatile_code = code;
-	  last_addr = (GET_CODE (XEXP (x, 0)) == LO_SUM
-		       ? XEXP (XEXP (x, 0), 1) : 0);
-	}
-      return;
-
-    case 'X': /* print the upper 16 bits... */
-      value >>= 16;
-    case 'x': /* print the lower 16 bits of the integer constant in hex */
-      if (xc != CONST_INT)
-	output_operand_lossage ("invalid %x/X value");
-      fprintf (file, "0x%x", value & 0xffff); return;
-
-    case 'H': /* print the low 16 bits of the negated integer constant */
-      if (xc != CONST_INT)
-	output_operand_lossage ("invalid %H value");
-      value = -value;
-    case 'h': /* print the register or low 16 bits of the integer constant */
-      if (xc == REG)
-	goto reg;
-      if (xc != CONST_INT)
-	output_operand_lossage ("invalid %h value");
-      fprintf (file, "%d", value & 0xffff);
-      return;
-
-    case 'Q': /* print the low 8 bits of the negated integer constant */
-      if (xc != CONST_INT)
-	output_operand_lossage ("invalid %Q value");
-      value = -value;
-    case 'q': /* print the register or low 8 bits of the integer constant */
-      if (xc == REG)
-	goto reg;
-      if (xc != CONST_INT)
-	output_operand_lossage ("invalid %q value");
-      fprintf (file, "%d", value & 0xff);
-      return;
-
-    case 'w': /* print the integer constant (X == 32 ? 0 : 32 - X) */
-      if (xc != CONST_INT)
-	output_operand_lossage ("invalid %o value");
-      fprintf (file, "%d", value == 32 ? 0 : 32 - value);
-      return;
-
-    case 'p': /* print the logarithm of the integer constant */
-      if (xc != CONST_INT
-	  || (value = exact_log2 (value)) < 0)
-	output_operand_lossage ("invalid %p value");
-      fprintf (file, "%d", value);
-      return;
-
-    case 'S': /* compliment the value and then... */
-      value = ~value;
-    case 's': /* print the width and offset values forming the integer
-		 constant with a SET instruction.  See integer_ok_for_set. */
-      {
-	register unsigned mask, uval = value;
-	register int top, bottom;
-
-	if (xc != CONST_INT)
-	  output_operand_lossage ("invalid %s/S value");
-	/* All the "one" bits must be contiguous.  If so, MASK will be
-	   a power of two or zero.  */
-	mask = (uval | (uval - 1)) + 1;
-	if (!(uval && POWER_OF_2_or_0 (mask)))
-	  output_operand_lossage ("invalid %s/S value");
-	top = mask ? exact_log2 (mask) : 32;
-	bottom = exact_log2 (uval & ~(uval - 1));
-	fprintf (file,"%d<%d>", top - bottom, bottom);
-	return;
-      }
-
-    case 'P': /* print nothing if pc_rtx; output label_ref */
-      if (xc == LABEL_REF)
-	output_addr_const (file, x);
-      else if (xc != PC)
-	output_operand_lossage ("invalid %P operand");
-      return;
-
-    case 'L': /* print 0 or 1 if operand is label_ref and then...  */
-      fputc (xc == LABEL_REF ? '1' : '0', file);
-    case '.': /* print .n if delay slot is used */
-      fputs ((final_sequence
-	      && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
-	     ? ".n\t" : "\t", file);
-      return;
-
-    case '!': /* Reverse the following condition. */
-      sequencep++;
-      reversep = 1;
-      return; 
-    case 'R': /* reverse the condition of the next print_operand
-		 if operand is a label_ref.  */
-      sequencep++;
-      reversep = (xc == LABEL_REF);
-      return;
-
-    case 'B': /* bcnd branch values */
-      fputs (m88k_pound_sign, file);
-      switch (xc)
-	{
-	case EQ: fputs ("eq0", file); return;
-	case NE: fputs ("ne0", file); return;
-	case GT: fputs ("gt0", file); return;
-	case LE: fputs ("le0", file); return;
-	case LT: fputs ("lt0", file); return;
-	case GE: fputs ("ge0", file); return;
-	default: output_operand_lossage ("invalid %B value");
-	}
-
-    case 'C': /* bb0/bb1 branch values for comparisons */
-      fputs (m88k_pound_sign, file);
-      switch (xc)
-	{
-	case EQ:  fputs ("eq", file); return;
-	case NE:  fputs ("ne", file); return;
-	case GT:  fputs ("gt", file); return;
-	case LE:  fputs ("le", file); return;
-	case LT:  fputs ("lt", file); return;
-	case GE:  fputs ("ge", file); return;
-	case GTU: fputs ("hi", file); return;
-	case LEU: fputs ("ls", file); return;
-	case LTU: fputs ("lo", file); return;
-	case GEU: fputs ("hs", file); return;
-	default:  output_operand_lossage ("invalid %C value");
-	}
-
-    case 'D': /* bcnd branch values for float comparisons */
-      switch (xc)
-	{
-	case EQ: fputs ("0xa", file); return;
-	case NE: fputs ("0x5", file); return;
-	case GT: fputs (m88k_pound_sign, file);
-	  fputs ("gt0", file); return;
-	case LE: fputs ("0xe", file); return;
-	case LT: fputs ("0x4", file); return;
-	case GE: fputs ("0xb", file); return;
-	default: output_operand_lossage ("invalid %D value");
-	}
-
-    case 'E': /* bcnd branch values for special integers */
-      switch (xc)
-	{
-	case EQ: fputs ("0x8", file); return;
-	case NE: fputs ("0x7", file); return;
-	default: output_operand_lossage ("invalid %E value");
-	}
-
-    case 'd': /* second register of a two register pair */
-      if (xc != REG)
-	output_operand_lossage ("`%d' operand isn't a register");
-      fputs (reg_names[REGNO (x) + 1], file);
-      return;
-
-    case 'r': /* an immediate 0 should be represented as `r0' */
-      if (x == const0_rtx)
-	{
-	  fputs (reg_names[0], file);
-	  return;
-	}
-      else if (xc != REG)
-	output_operand_lossage ("invalid %r value");
-    case 0:
-    name:
-      if (xc == REG)
-	{
-	reg:
-	  if (REGNO (x) == ARG_POINTER_REGNUM)
-	    output_operand_lossage ("operand is r0");
-	  else
-	    fputs (reg_names[REGNO (x)], file);
-	}
-      else if (xc == PLUS)
-	output_address (x);
-      else if (xc == MEM)
-	output_address (XEXP (x, 0));
-      else if (flag_pic && xc == UNSPEC)
-	{
-	  output_addr_const (file, XVECEXP (x, 0, 0));
-	  fputs ("#got_rel", file);
-	}
-      else if (xc == CONST_DOUBLE)
-	output_operand_lossage ("operand is const_double");
-      else
-	output_addr_const (file, x);
-      return;
-
-    case 'g': /* append #got_rel as needed */
-      if (flag_pic && (xc == SYMBOL_REF || xc == LABEL_REF))
-	{
-	  output_addr_const (file, x);
-	  fputs ("#got_rel", file);
-	  return;
-	}
-      goto name;
-
-    case 'a': /* (standard), assume operand is an address */
-    case 'c': /* (standard), assume operand is an immediate value */
-    case 'l': /* (standard), assume operand is a label_ref */
-    case 'n': /* (standard), like %c, except negate first */
-    default:
-      output_operand_lossage ("invalid code");
-    }
-}
-
-void
-print_operand_address (file, addr)
-    FILE *file;
-    rtx addr;
-{
-  register rtx reg0, reg1, temp;
-
-  switch (GET_CODE (addr))
-    {
-    case REG:
-      if (REGNO (addr) == ARG_POINTER_REGNUM)
-	abort ();
-      else
-	fprintf (file, "%s,%s", reg_names[0], reg_names [REGNO (addr)]);
-      break;
-
-    case LO_SUM:
-      fprintf (file, "%s,%slo16(",
-	       reg_names[REGNO (XEXP (addr, 0))], m88k_pound_sign);
-      output_addr_const (file, XEXP (addr, 1));
-      fputc (')', file);
-      break;
-
-    case PLUS:
-      reg0 = XEXP (addr, 0);
-      reg1 = XEXP (addr, 1);
-      if (GET_CODE (reg0) == MULT || GET_CODE (reg0) == CONST_INT)
-	{
-	  rtx tmp = reg0;
-	  reg0 = reg1;
-	  reg1 = tmp;
-	}
-
-      if ((REG_P (reg0) && REGNO (reg0) == ARG_POINTER_REGNUM)
-	  || (REG_P (reg1) && REGNO (reg1) == ARG_POINTER_REGNUM))
-	abort ();
-
-      else if (REG_P (reg0))
-	{
-	  if (REG_P (reg1))
-	    fprintf (file, "%s,%s",
-		     reg_names [REGNO (reg0)], reg_names [REGNO (reg1)]);
-
-	  else if (GET_CODE (reg1) == CONST_INT)
-	    fprintf (file, "%s,%d",
-		     reg_names [REGNO (reg0)], INTVAL (reg1));
-
-	  else if (GET_CODE (reg1) == MULT)
-	    {
-	      rtx mreg = XEXP (reg1, 0);
-	      if (REGNO (mreg) == ARG_POINTER_REGNUM)
-		abort ();
-
-	      fprintf (file, "%s[%s]", reg_names[REGNO (reg0)],
-		       reg_names[REGNO (mreg)]);
-	    }
-
-	  else if (GET_CODE (reg1) == ZERO_EXTRACT)
-	    {
-	      fprintf (file, "%s,%slo16(",
-		       reg_names[REGNO (reg0)], m88k_pound_sign);
-	      output_addr_const (file, XEXP (reg1, 0));
-	      fputc (')', file);
-	    }
-
-	  else if (flag_pic)
-	    {
-	      fprintf (file, "%s,", reg_names[REGNO (reg0)]);
-	      output_addr_const (file, reg1);
-	      fputs ("#got_rel", file);
-	    }
-	  else abort ();
-	}
-
-      else
-	abort ();
-      break;
-
-    case MULT:
-      if (REGNO (XEXP (addr, 0)) == ARG_POINTER_REGNUM)
-	abort ();
-
-      fprintf (file, "%s[%s]",
-	       reg_names[0], reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case CONST_INT:
-      fprintf (file, "%s,%d", reg_names[0], INTVAL (addr));
-      break;
-
-    default:
-      fprintf (file, "%s,", reg_names[0]);
-      if (SHORT_ADDRESS_P (addr, temp))
-	{
-	  fprintf (file, "%siw16(", m88k_pound_sign);
-	  output_addr_const (file, addr);
-	  fputc (')', file);
-	}
-      else
-	  output_addr_const (file, addr);
-    }
-}
-
-/* Return true if X is an address which needs a temporary register when 
-   reloaded while generating PIC code.  */
-
-int
-pic_address_needs_scratch (x)
-     rtx x;
-{
-  /* An address which is a symbolic plus a non SMALL_INT needs a temp reg.  */
-  if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
-      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
-      && ! ADD_INT (XEXP (XEXP (x, 0), 1)))
-    return 1;
-
-  return 0;
-}
-
-/* Returns 1 if OP is either a symbol reference or a sum of a symbol
-   reference and a constant.  */
-
-int
-symbolic_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return 1;
-
-    case CONST:
-      op = XEXP (op, 0);
-      return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
-               || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-              && GET_CODE (XEXP (op, 1)) == CONST_INT);
-
-      /* ??? This clause seems to be irrelevant.  */
-    case CONST_DOUBLE:
-      return GET_MODE (op) == mode;
-
-    default:
-      return 0;
-    }
-}
diff --git a/gcc/config/m88k/m88k.h b/gcc/config/m88k/m88k.h
deleted file mode 100755
index 5735560..0000000
--- a/gcc/config/m88k/m88k.h
+++ /dev/null
@@ -1,2646 +0,0 @@
-/* Definitions of target machine for GNU compiler for
-   Motorola m88100 in an 88open OCS/BCS environment.
-   Copyright (C) 1988, 92-97, 1998 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@cygnus.com).
-   Currently maintained by (gcc@dg-rtp.dg.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* The m88100 port of GNU CC adheres to the various standards from 88open.
-   These documents are available by writing:
-
-	88open Consortium Ltd.
-	100 Homeland Court, Suite 800
-	San Jose, CA  95112
-	(408) 436-6600
-
-   In brief, the current standards are:
-
-   Binary Compatibility Standard, Release 1.1A, May 1991
-	This provides for portability of application-level software at the
-	executable level for AT&T System V Release 3.2.
-
-   Object Compatibility Standard, Release 1.1A, May 1991
-	This provides for portability of application-level software at the
-	object file and library level for C, Fortran, and Cobol, and again,
-	largely for SVR3.
-
-   Under development are standards for AT&T System V Release 4, based on the
-   [generic] System V Application Binary Interface from AT&T.  These include:
-
-   System V Application Binary Interface, Motorola 88000 Processor Supplement
-	Another document from AT&T for SVR4 specific to the m88100.
-	Available from Prentice Hall.
-
-   System V Application Binary Interface, Motorola 88000 Processor Supplement,
-   Release 1.1, Draft H, May 6, 1991
-	A proposed update to the AT&T document from 88open.
-
-   System V ABI Implementation Guide for the M88000 Processor,
-   Release 1.0, January 1991
-	A companion ABI document from 88open.  */
-
-/* Other *.h files in config/m88k include this one and override certain items.
-   Currently these are sysv3.h, sysv4.h, dgux.h, dolph.h, tekXD88.h, and luna.h.
-   Additionally, sysv4.h and dgux.h include svr4.h first.  All other
-   m88k targets except luna.h are based on svr3.h.  */
-
-/* Choose SVR3 as the default.  */
-#if !defined(DBX_DEBUGGING_INFO) && !defined(DWARF_DEBUGGING_INFO)
-#include "svr3.h"
-#endif
-
-/* External types used.  */
-
-/* What instructions are needed to manufacture an integer constant.  */
-enum m88k_instruction {
-  m88k_zero,
-  m88k_or,
-  m88k_subu,
-  m88k_or_lo16,
-  m88k_or_lo8,
-  m88k_set,
-  m88k_oru_hi16,
-  m88k_oru_or
-};
-
-/* Which processor to schedule for.  The elements of the enumeration
-   must match exactly the cpu attribute in the m88k.md machine description. */
-
-enum processor_type {
-  PROCESSOR_M88100,
-  PROCESSOR_M88110,
-  PROCESSOR_M88000,
-};
-
-/* Recast the cpu class to be the cpu attribute.  */
-#define m88k_cpu_attr ((enum attr_cpu)m88k_cpu)
-
-/* External variables/functions defined in m88k.c.  */
-
-extern char *m88k_pound_sign;
-extern char *m88k_short_data;
-extern char *m88k_version;
-extern char m88k_volatile_code;
-
-extern unsigned m88k_gp_threshold;
-extern int m88k_prologue_done;
-extern int m88k_function_number;
-extern int m88k_fp_offset;
-extern int m88k_stack_size;
-extern int m88k_case_index;
-
-extern struct rtx_def *m88k_compare_reg;
-extern struct rtx_def *m88k_compare_op0;
-extern struct rtx_def *m88k_compare_op1;
-
-extern enum processor_type m88k_cpu;
-
-extern int null_prologue ();
-extern int integer_ok_for_set ();
-extern int m88k_debugger_offset ();
-
-
-extern void emit_bcnd ();
-extern void expand_block_move ();
-extern void m88k_layout_frame ();
-extern void m88k_expand_prologue ();
-extern void m88k_begin_prologue ();
-extern void m88k_end_prologue ();
-extern void m88k_expand_epilogue ();
-extern void m88k_begin_epilogue ();
-extern void m88k_end_epilogue ();
-extern void output_function_profiler ();
-extern void output_function_block_profiler ();
-extern void output_block_profiler ();
-extern void output_file_start ();
-extern void output_ascii ();
-extern void output_label ();
-extern void print_operand ();
-extern void print_operand_address ();
-
-extern char *output_load_const_int ();
-extern char *output_load_const_float ();
-extern char *output_load_const_double ();
-extern char *output_load_const_dimode ();
-extern char *output_and ();
-extern char *output_ior ();
-extern char *output_xor ();
-extern char *output_call ();
-
-extern struct rtx_def *emit_test ();
-extern struct rtx_def *legitimize_address ();
-extern struct rtx_def *legitimize_operand ();
-extern struct rtx_def *m88k_function_arg ();
-extern struct rtx_def *m88k_builtin_saveregs ();
-
-extern enum m88k_instruction classify_integer ();
-
-/* external variables defined elsewhere in the compiler */
-
-extern int target_flags;			/* -m compiler switches */
-extern int frame_pointer_needed;		/* current function has a FP */
-extern int current_function_pretend_args_size;	/* args size without ... */
-extern int flag_delayed_branch;			/* -fdelayed-branch */
-extern int flag_pic;				/* -fpic */
-extern char * reg_names[];
-
-/* Specify the default monitors.  The meaning of these values can
-   be obtained by doing "grep MONITOR_GCC *m88k*".  Generally, the
-   values downward from 0x8000 are tests that will soon go away.
-   values upward from 0x1 are generally useful tests that will remain.  */
-
-#ifndef MONITOR_GCC
-#define MONITOR_GCC 0
-#endif
-
-/*** Controlling the Compilation Driver, `gcc' ***/
-/* Show we can debug even without a frame pointer.  */
-#define CAN_DEBUG_WITHOUT_FP
-
-/* If -m88100 is in effect, add -D__m88100__; similarly for -m88110.
-   Here, the CPU_DEFAULT is assumed to be -m88100.  */
-#undef	CPP_SPEC
-#define	CPP_SPEC "%{!m88000:%{!m88100:%{m88110:-D__m88110__}}} \
-		  %{!m88000:%{!m88110:-D__m88100__}}"
-
-/* LIB_SPEC, LINK_SPEC, and STARTFILE_SPEC defined in svr3.h.
-   ASM_SPEC, ASM_FINAL_SPEC, LIB_SPEC, LINK_SPEC, and STARTFILE_SPEC redefined
-   in svr4.h.
-   CPP_SPEC, ASM_SPEC, ASM_FINAL_SPEC, LIB_SPEC, LINK_SPEC, and
-   STARTFILE_SPEC redefined in dgux.h.  */
-
-/*** Run-time Target Specification ***/
-
-/* Names to predefine in the preprocessor for this target machine.
-   Redefined in sysv3.h, sysv4.h, dgux.h, and luna.h.  */
-#define CPP_PREDEFINES "-Dm88000 -Dm88k -Dunix -D__CLASSIFY_TYPE__=2"
-
-#define TARGET_VERSION fprintf (stderr, " (%s%s)", \
-				VERSION_INFO1, VERSION_INFO2)
-
-/* Print subsidiary information on the compiler version in use.
-   Redefined in sysv4.h, and luna.h.  */
-#define VERSION_INFO1	"m88k, "
-#ifndef VERSION_INFO2
-#define VERSION_INFO2   "$Revision: 1.70 $"
-#endif
-
-#ifndef VERSION_STRING
-#define VERSION_STRING  version_string
-#ifdef __STDC__
-#define TM_RCS_ID      "@(#)" __FILE__ " $Revision: 1.70 $ " __DATE__
-#else
-#define TM_RCS_ID      "$What: <@(#) m88k.h,v	1.1.1.2.2.2> $"
-#endif  /* __STDC__ */
-#else
-#define TM_RCS_ID      "@(#)" __FILE__ " " VERSION_INFO2 " " __DATE__
-#endif  /* VERSION_STRING */
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define MASK_88100		0x00000001 /* Target m88100 */
-#define MASK_88110		0x00000002 /* Target m88110 */
-#define MASK_88000 		(MASK_88100 | MASK_88110)
-
-#define MASK_OCS_DEBUG_INFO	0x00000004 /* Emit .tdesc info */
-#define MASK_OCS_FRAME_POSITION	0x00000008 /* Debug frame = CFA, not r30 */
-#define MASK_SVR4		0x00000010 /* Target is AT&T System V.4 */
-#define MASK_SVR3		0x00000020 /* Target is AT&T System V.3 */
-#define MASK_NO_UNDERSCORES	0x00000040 /* Don't emit a leading `_' */
-#define MASK_BIG_PIC		0x00000080 /* PIC with large got-rel's -fPIC */
-#define MASK_TRAP_LARGE_SHIFT	0x00000100 /* Trap if shift not <= 31 */
-#define MASK_HANDLE_LARGE_SHIFT	0x00000200 /* Handle shift count >= 32 */
-#define MASK_CHECK_ZERO_DIV	0x00000400 /* Check for int div. by 0 */
-#define MASK_USE_DIV		0x00000800 /* No signed div. checks */
-#define MASK_IDENTIFY_REVISION	0x00001000 /* Emit ident, with GCC rev */
-#define MASK_WARN_PASS_STRUCT	0x00002000 /* Warn about passed structs */
-#define MASK_OPTIMIZE_ARG_AREA	0x00004000 /* Save stack space */
-#define MASK_NO_SERIALIZE_VOLATILE 0x00008000 /* Serialize volatile refs */
-#define MASK_EITHER_LARGE_SHIFT	(MASK_TRAP_LARGE_SHIFT | \
-				 MASK_HANDLE_LARGE_SHIFT)
-#define MASK_OMIT_LEAF_FRAME_POINTER 0x00020000 /* omit leaf frame pointers */
-
-
-#define TARGET_88100   		 ((target_flags & MASK_88000) == MASK_88100)
-#define TARGET_88110		 ((target_flags & MASK_88000) == MASK_88110)
-#define TARGET_88000		 ((target_flags & MASK_88000) == MASK_88000)
-
-#define TARGET_OCS_DEBUG_INFO	  (target_flags & MASK_OCS_DEBUG_INFO)
-#define TARGET_OCS_FRAME_POSITION (target_flags & MASK_OCS_FRAME_POSITION)
-#define TARGET_SVR4		  (target_flags & MASK_SVR4)
-#define TARGET_SVR3		  (target_flags & MASK_SVR3)
-#define TARGET_NO_UNDERSCORES	  (target_flags & MASK_NO_UNDERSCORES)
-#define TARGET_BIG_PIC		  (target_flags & MASK_BIG_PIC)
-#define TARGET_TRAP_LARGE_SHIFT   (target_flags & MASK_TRAP_LARGE_SHIFT)
-#define TARGET_HANDLE_LARGE_SHIFT (target_flags & MASK_HANDLE_LARGE_SHIFT)
-#define TARGET_CHECK_ZERO_DIV	  (target_flags & MASK_CHECK_ZERO_DIV)
-#define	TARGET_USE_DIV		  (target_flags & MASK_USE_DIV)
-#define TARGET_IDENTIFY_REVISION  (target_flags & MASK_IDENTIFY_REVISION)
-#define TARGET_WARN_PASS_STRUCT   (target_flags & MASK_WARN_PASS_STRUCT)
-#define TARGET_OPTIMIZE_ARG_AREA  (target_flags & MASK_OPTIMIZE_ARG_AREA)
-#define TARGET_SERIALIZE_VOLATILE (!(target_flags & MASK_NO_SERIALIZE_VOLATILE))
-
-#define TARGET_EITHER_LARGE_SHIFT (target_flags & MASK_EITHER_LARGE_SHIFT)
-#define TARGET_OMIT_LEAF_FRAME_POINTER (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
-
-/*  Redefined in sysv3.h, sysv4.h, and dgux.h.  */
-#define TARGET_DEFAULT	(MASK_CHECK_ZERO_DIV)
-#define CPU_DEFAULT MASK_88100
-
-#define TARGET_SWITCHES \
-  { \
-    { "88110",				 MASK_88110 }, \
-    { "88100",				 MASK_88100 }, \
-    { "88000",			         MASK_88000 }, \
-    { "ocs-debug-info",			 MASK_OCS_DEBUG_INFO }, \
-    { "no-ocs-debug-info",		-MASK_OCS_DEBUG_INFO }, \
-    { "ocs-frame-position",		 MASK_OCS_FRAME_POSITION }, \
-    { "no-ocs-frame-position",		-MASK_OCS_FRAME_POSITION }, \
-    { "svr4",			         MASK_SVR4 }, \
-    { "svr3",			        -MASK_SVR4 }, \
-    { "no-underscores",			 MASK_NO_UNDERSCORES }, \
-    { "big-pic",			 MASK_BIG_PIC }, \
-    { "trap-large-shift",		 MASK_TRAP_LARGE_SHIFT }, \
-    { "handle-large-shift",		 MASK_HANDLE_LARGE_SHIFT }, \
-    { "check-zero-division",		 MASK_CHECK_ZERO_DIV }, \
-    { "no-check-zero-division",		-MASK_CHECK_ZERO_DIV }, \
-    { "use-div-instruction",		 MASK_USE_DIV }, \
-    { "identify-revision",		 MASK_IDENTIFY_REVISION }, \
-    { "warn-passed-structs",		 MASK_WARN_PASS_STRUCT }, \
-    { "optimize-arg-area",		 MASK_OPTIMIZE_ARG_AREA }, \
-    { "no-optimize-arg-area",		-MASK_OPTIMIZE_ARG_AREA }, \
-    { "no-serialize-volatile",		 MASK_NO_SERIALIZE_VOLATILE }, \
-    { "serialize-volatile",		-MASK_NO_SERIALIZE_VOLATILE }, \
-    { "omit-leaf-frame-pointer",	 MASK_OMIT_LEAF_FRAME_POINTER }, \
-    { "no-omit-leaf-frame-pointer",     -MASK_OMIT_LEAF_FRAME_POINTER }, \
-    SUBTARGET_SWITCHES \
-    /* Default switches */ \
-    { "",				 TARGET_DEFAULT }, \
-  }
-
-/* Redefined in dgux.h.  */
-#define SUBTARGET_SWITCHES
-
-/* Macro to define table for command options with values.  */
-
-#define TARGET_OPTIONS { { "short-data-", &m88k_short_data }, \
-			 { "version-", &m88k_version } }
-
-/* Do any checking or such that is needed after processing the -m switches.  */
-
-#define OVERRIDE_OPTIONS						     \
-  do {									     \
-    register int i;							     \
-									     \
-    if ((target_flags & MASK_88000) == 0)				     \
-      target_flags |= CPU_DEFAULT;					     \
-									     \
-    if (TARGET_88110)							     \
-      {									     \
-        target_flags |= MASK_USE_DIV;					     \
-        target_flags &= ~MASK_CHECK_ZERO_DIV;				     \
-      }									     \
-      									     \
-    m88k_cpu = (TARGET_88000 ? PROCESSOR_M88000				     \
-		: (TARGET_88100 ? PROCESSOR_M88100 : PROCESSOR_M88110));		     \
-									     \
-    if (TARGET_BIG_PIC)							     \
-      flag_pic = 2;							     \
-									     \
-    if ((target_flags & MASK_EITHER_LARGE_SHIFT) == MASK_EITHER_LARGE_SHIFT) \
-      error ("-mtrap-large-shift and -mhandle-large-shift are incompatible");\
-									     \
-    if (TARGET_SVR4)						     	     \
-      {									     \
-	for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)			     \
-	  reg_names[i]--;						     \
-	m88k_pound_sign = "#";						     \
-      }									     \
-    else								     \
-      {									     \
-	target_flags |= MASK_SVR3;					     \
-	target_flags &= ~MASK_SVR4;					     \
-      }									     \
-									     \
-    if (m88k_short_data)						     \
-      {									     \
-	char *p = m88k_short_data;					     \
-	while (*p)							     \
-	  if (*p >= '0' && *p <= '9')					     \
-	    p++;							     \
-	  else								     \
-	    {								     \
-	      error ("Invalid option `-mshort-data-%s'", m88k_short_data);   \
-	      break;							     \
-	    }								     \
-	m88k_gp_threshold = atoi (m88k_short_data);			     \
-	if (m88k_gp_threshold > 0x7fffffff)				     \
-	  error ("-mshort-data-%s is too large ", m88k_short_data);          \
-	if (flag_pic)							     \
-	  error ("-mshort-data-%s and PIC are incompatible", m88k_short_data); \
-      }									     \
-    if (TARGET_OMIT_LEAF_FRAME_POINTER)       /* keep nonleaf frame pointers */    \
-      flag_omit_frame_pointer = 1;                                         \
-  } while (0)
-
-/*** Storage Layout ***/
-
-/* Sizes in bits of the various types.  */
-#define CHAR_TYPE_SIZE		 8
-#define SHORT_TYPE_SIZE		16
-#define INT_TYPE_SIZE		32
-#define LONG_TYPE_SIZE		32
-#define LONG_LONG_TYPE_SIZE	64
-#define FLOAT_TYPE_SIZE		32
-#define	DOUBLE_TYPE_SIZE	64
-#define LONG_DOUBLE_TYPE_SIZE	64
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   Somewhat arbitrary.  It matches the bit field patterns.  */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.
-   That is true on the m88000.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.
-   For the m88000 we can decide arbitrarily since there are no machine
-   instructions for them.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Largest alignment for stack parameters (if greater than PARM_BOUNDARY).  */
-#define MAX_PARM_BOUNDARY 64
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 128
-
-/* Allocation boundary (in *bits*) for the code of a function.  On the
-   m88100, it is desirable to align to a cache line.  However, SVR3 targets
-   only provided 8 byte alignment.  The m88110 cache is small, so align
-   to an 8 byte boundary.  Pack code tightly when compiling crtstuff.c.  */
-#define FUNCTION_BOUNDARY (flag_inhibit_size_directive ? 32 : \
-			   (TARGET_88100 && TARGET_SVR4 ? 128 : 64))
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 64
-
-/* The best alignment to use in cases where we have a choice.  */
-#define FASTEST_ALIGNMENT (TARGET_88100 ? 32 : 64)
-
-/* Make strings 4/8 byte aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  ((TREE_CODE (EXP) == STRING_CST	\
-    && (ALIGN) < FASTEST_ALIGNMENT)	\
-   ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Make arrays of chars 4/8 byte aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Alignment of field after `int : 0' in a structure.
-   Ignored with PCC_BITFIELD_TYPE_MATTERS.  */
-/* #define EMPTY_FIELD_BOUNDARY 8 */
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Maximum size (in bits) to use for the largest integral type that
-   replaces a BLKmode type. */
-/* #define MAX_FIXED_MODE_SIZE 0 */
-
-/* Check a `double' value for validity for a particular machine mode.
-   This is defined to avoid crashes outputting certain constants.
-   Since we output the number in hex, the assembler won't choke on it.  */
-/* #define CHECK_FLOAT_VALUE(MODE,VALUE) */
-
-/* A code distinguishing the floating point format of the target machine.  */
-/* #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT */
-
-/*** Register Usage ***/
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   The m88100 has a General Register File (GRF) of 32 32-bit registers.
-   The m88110 adds an Extended Register File (XRF) of 32 80-bit registers.  */
-#define FIRST_PSEUDO_REGISTER 64
-#define FIRST_EXTENDED_REGISTER 32
-
-/*  General notes on extended registers, their use and misuse.
-
-    Possible good uses:
-
-    spill area instead of memory.
-      -waste if only used once
-
-    floating point calculations
-      -probably a waste unless we have run out of general purpose registers
-
-    freeing up general purpose registers
-      -e.g. may be able to have more loop invariants if floating
-       point is moved into extended registers.
-
-
-    I've noticed wasteful moves into and out of extended registers; e.g. a load
-    into x21, then inside a loop a move into r24, then r24 used as input to
-    an fadd.  Why not just load into r24 to begin with?  Maybe the new cse.c
-    will address this.  This wastes a move, but the load,store and move could
-    have been saved had extended registers been used throughout.
-    E.g. in the code following code, if z and xz are placed in extended
-    registers, there is no need to save preserve registers.
-
-	long c=1,d=1,e=1,f=1,g=1,h=1,i=1,j=1,k;
-
-	double z=0,xz=4.5;
-
-	foo(a,b)
-	long a,b;
-	{
-	  while (a < b)
-	    {
-	      k = b + c + d + e + f + g + h + a + i + j++;
-	      z += xz;
-	      a++;
-	    }
-	  printf("k= %d; z=%f;\n", k, z);
-	}
-
-    I've found that it is possible to change the constraints (putting * before
-    the 'r' constraints int the fadd.ddd instruction) and get the entire
-    addition and store to go into extended registers.  However, this also
-    forces simple addition and return of floating point arguments to a
-    function into extended registers.  Not the correct solution.
-
-    Found the following note in local-alloc.c which may explain why I can't
-    get both registers to be in extended registers since two are allocated in
-    local-alloc and one in global-alloc.  Doesn't explain (I don't believe)
-    why an extended register is used instead of just using the preserve
-    register.
-
-	from local-alloc.c:
-	We have provision to exempt registers, even when they are contained
-	within the block, that can be tied to others that are not contained in it.
-	This is so that global_alloc could process them both and tie them then.
-	But this is currently disabled since tying in global_alloc is not
-	yet implemented.
-
-    The explanation of why the preserved register is not used is as follows,
-    I believe.  The registers are being allocated in order.  Tying is not
-    done so efficiently, so when it comes time to do the first allocation,
-    there are no registers left to use without spilling except extended
-    registers.  Then when the next pseudo register needs a hard reg, there
-    are still no registers to be had for free, but this one must be a GRF
-    reg instead of an extended reg, so a preserve register is spilled.  Thus
-    the move from extended to GRF is necessitated.  I do not believe this can
-    be 'fixed' through the files in config/m88k.
-
-    gcc seems to sometimes make worse use of register allocation -- not counting
-    moves -- whenever extended registers are present.  For example in the
-    whetstone, the simple for loop (slightly modified)
-      for(i = 1; i <= n1; i++)
-	{
-	  x1 = (x1 + x2 + x3 - x4) * t;
-	  x2 = (x1 + x2 - x3 + x4) * t;
-	  x3 = (x1 - x2 + x3 + x4) * t;
-	  x4 = (x1 + x2 + x3 + x4) * t;
-	}
-    in general loads the high bits of the addresses of x2-x4 and i into registers
-    outside the loop.  Whenever extended registers are used, it loads all of
-    these inside the loop. My conjecture is that since the 88110 has so many
-    registers, and gcc makes no distinction at this point -- just that they are
-    not fixed, that in loop.c it believes it can expect a number of registers
-    to be available.  Then it allocates 'too many' in local-alloc which causes
-    problems later.  'Too many' are allocated because a large portion of the
-    registers are extended registers and cannot be used for certain purposes
-    ( e.g. hold the address of a variable).  When this loop is compiled on its
-    own, the problem does not occur.  I don't know the solution yet, though it
-    is probably in the base sources.  Possibly a different way to calculate
-    "threshold".  */
-
-/* 1 for registers that have pervasive standard uses and are not available
-   for the register allocator.  Registers r14-r25 and x22-x29 are expected
-   to be preserved across function calls.
-
-   On the 88000, the standard uses of the General Register File (GRF) are:
-   Reg 0	= Pseudo argument pointer (hardware fixed to 0).
-   Reg 1	= Subroutine return pointer (hardware).
-   Reg 2-9	= Parameter registers (OCS).
-   Reg 10	= OCS reserved temporary.
-   Reg 11	= Static link if needed [OCS reserved temporary].
-   Reg 12	= Address of structure return (OCS).
-   Reg 13	= OCS reserved temporary.
-   Reg 14-25	= Preserved register set.
-   Reg 26-29	= Reserved by OCS and ABI.
-   Reg 30	= Frame pointer (Common use).
-   Reg 31	= Stack pointer.
-
-   The following follows the current 88open UCS specification for the
-   Extended Register File (XRF):
-   Reg 32       = x0		Always equal to zero
-   Reg 33-53	= x1-x21	Temporary registers (Caller Save)
-   Reg 54-61	= x22-x29	Preserver registers (Callee Save)
-   Reg 62-63	= x30-x31	Reserved for future ABI use.
-
-   Note:  The current 88110 extended register mapping is subject to change.
-	  The bias towards caller-save registers is based on the
-	  presumption that memory traffic can potentially be reduced by
-	  allowing the "caller" to save only that part of the register
-	  which is actually being used.  (i.e. don't do a st.x if a st.d
-	  is sufficient).  Also, in scientific code (a.k.a. Fortran), the
-	  large number of variables defined in common blocks may require
-	  that almost all registers be saved across calls anyway.  */
-
-#define FIXED_REGISTERS \
- {1, 0, 0, 0,  0, 0, 0, 0,   0, 0, 0, 0,  0, 0, 0, 0, \
-  0, 0, 0, 0,  0, 0, 0, 0,   0, 0, 1, 1,  1, 1, 1, 1, \
-  1, 0, 0, 0,  0, 0, 0, 0,   0, 0, 0, 0,  0, 0, 0, 0, \
-  0, 0, 0, 0,  0, 0, 0, 0,   0, 0, 0, 0,  0, 0, 1, 1}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-
-#define CALL_USED_REGISTERS \
- {1, 1, 1, 1,  1, 1, 1, 1,   1, 1, 1, 1,  1, 1, 0, 0, \
-  0, 0, 0, 0,  0, 0, 0, 0,   0, 0, 1, 1,  1, 1, 1, 1, \
-  1, 1, 1, 1,  1, 1, 1, 1,   1, 1, 1, 1,  1, 1, 1, 1, \
-  1, 1, 1, 1,  1, 1, 0, 0,   0, 0, 0, 0,  0, 0, 1, 1}
-
-/* Macro to conditionally modify fixed_regs/call_used_regs.  */
-#define CONDITIONAL_REGISTER_USAGE			\
-  {							\
-    if (! TARGET_88110)					\
-      {							\
-	register int i;					\
-	  for (i = FIRST_EXTENDED_REGISTER; i < FIRST_PSEUDO_REGISTER; i++) \
-	    {						\
-	      fixed_regs[i] = 1;			\
-	      call_used_regs[i] = 1;			\
-	    }						\
-      }							\
-    if (flag_pic)					\
-      {							\
-	/* Current hack to deal with -fpic -O2 problems.  */ \
-	fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;	\
-	call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;	\
-	global_regs[PIC_OFFSET_TABLE_REGNUM] = 1;	\
-      }							\
-  }
-
-/* These interfaces that don't apply to the m88000.  */
-/* OVERLAPPING_REGNO_P(REGNO) 0 */
-/* INSN_CLOBBERS_REGNO_P(INSN, REGNO) 0 */
-
-/* True if register is an extended register.  */
-#define XRF_REGNO_P(N) ((N) < FIRST_PSEUDO_REGISTER && (N) >= FIRST_EXTENDED_REGISTER)
- 
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On the m88000, GRF registers hold 32-bits and XRF registers hold 80-bits.
-   An XRF register can hold any mode, but two GRF registers are required
-   for larger modes.  */
-#define HARD_REGNO_NREGS(REGNO, MODE)					\
-  (XRF_REGNO_P (REGNO)                                                 \
-   ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-
-   For double integers, we never put the value into an odd register so that
-   the operators don't run into the situation where the high part of one of
-   the inputs is the low part of the result register.  (It's ok if the output
-   registers are the same as the input registers.)  The XRF registers can
-   hold all modes, but only DF and SF modes can be manipulated in these
-   registers.  The compiler should be allowed to use these as a fast spill
-   area.  */
-#define HARD_REGNO_MODE_OK(REGNO, MODE)					\
-  (XRF_REGNO_P(REGNO)							\
-    ? (TARGET_88110 && GET_MODE_CLASS (MODE) == MODE_FLOAT)             \
-    : (((MODE) != DImode && (MODE) != DFmode && (MODE) != DCmode)	\
-       || ((REGNO) & 1) == 0))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  (((MODE1) == DFmode || (MODE1) == DCmode || (MODE1) == DImode \
-    || (TARGET_88110 && GET_MODE_CLASS (MODE1) == MODE_FLOAT)) \
-   == ((MODE2) == DFmode || (MODE2) == DCmode || (MODE2) == DImode \
-       || (TARGET_88110 && GET_MODE_CLASS (MODE2) == MODE_FLOAT)))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* the m88000 pc isn't overloaded on a register that the compiler knows about.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 31
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 30
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 0
-
-/* Register used in cases where a temporary is known to be safe to use.  */
-#define TEMP_REGNUM 10
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 11
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 12
-
-/* Register to hold the addressing base for position independent
-   code access to data items.  */
-#define PIC_OFFSET_TABLE_REGNUM 25
-
-/* Order in which registers are preferred (most to least).  Use temp
-   registers, then param registers top down.  Preserve registers are
-   top down to maximize use of double memory ops for register save.
-   The 88open reserved registers (r26-r29 and x30-x31) may commonly be used
-   in most environments with the -fcall-used- or -fcall-saved- options.  */
-#define REG_ALLOC_ORDER		  \
- {				  \
-  13, 12, 11, 10, 29, 28, 27, 26, \
-  62, 63,  9,  8,  7,  6,  5,  4, \
-   3,  2,  1, 53, 52, 51, 50, 49, \
-  48, 47, 46, 45, 44, 43, 42, 41, \
-  40, 39, 38, 37, 36, 35, 34, 33, \
-  25, 24, 23, 22, 21, 20, 19, 18, \
-  17, 16, 15, 14, 61, 60, 59, 58, \
-  57, 56, 55, 54, 30, 31,  0, 32}
-
-/* Order for leaf functions.  */
-#define REG_LEAF_ALLOC_ORDER	  \
- {				  \
-   9,  8,  7,  6, 13, 12, 11, 10, \
-  29, 28, 27, 26, 62, 63,  5,  4, \
-   3,  2,  0, 53, 52, 51, 50, 49, \
-  48, 47, 46, 45, 44, 43, 42, 41, \
-  40, 39, 38, 37, 36, 35, 34, 33, \
-  25, 24, 23, 22, 21, 20, 19, 18, \
-  17, 16, 15, 14, 61, 60, 59, 58, \
-  57, 56, 55, 54, 30, 31,  1, 32}
-
-/* Switch between the leaf and non-leaf orderings.  The purpose is to avoid
-   write-over scoreboard delays between caller and callee.  */
-#define ORDER_REGS_FOR_LOCAL_ALLOC				\
-{								\
-  static int leaf[] = REG_LEAF_ALLOC_ORDER;			\
-  static int nonleaf[] = REG_ALLOC_ORDER;			\
-								\
-  bcopy (regs_ever_live[1] ? nonleaf : leaf, reg_alloc_order,	\
-	 FIRST_PSEUDO_REGISTER * sizeof (int));			\
-}
-
-/*** Register Classes ***/
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-/* The m88000 hardware has two kinds of registers.  In addition, we denote
-   the arg pointer as a separate class.  */
-
-enum reg_class { NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS, AGRF_REGS,
-		 XGRF_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-#define REG_CLASS_NAMES {"NO_REGS", "AP_REG", "XRF_REGS", "GENERAL_REGS", \
-			 "AGRF_REGS", "XGRF_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-#define REG_CLASS_CONTENTS {{0x00000000, 0x00000000},	\
-			    {0x00000001, 0x00000000},	\
-			    {0x00000000, 0xffffffff},	\
-			    {0xfffffffe, 0x00000000},	\
-			    {0xffffffff, 0x00000000},	\
-			    {0xfffffffe, 0xffffffff},	\
-			    {0xffffffff, 0xffffffff}}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-#define REGNO_REG_CLASS(REGNO) \
-  ((REGNO) ? ((REGNO < 32) ? GENERAL_REGS : XRF_REGS) : AP_REG)
-
-/* The class value for index registers, and the one for base regs.  */
-#define BASE_REG_CLASS AGRF_REGS
-#define INDEX_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.
-   For the 88000, the following class/letter is defined for the XRF:
-	x - Extended register file  */
-#define REG_CLASS_FROM_LETTER(C) 	\
-   (((C) == 'x') ? XRF_REGS : NO_REGS)
-
-/* Macros to check register numbers against specific register classes.
-   These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-#define REGNO_OK_FOR_BASE_P(REGNO)				\
-  ((REGNO) < FIRST_EXTENDED_REGISTER				\
-   || (unsigned) reg_renumber[REGNO] < FIRST_EXTENDED_REGISTER)
-#define REGNO_OK_FOR_INDEX_P(REGNO)				\
-  (((REGNO) && (REGNO) < FIRST_EXTENDED_REGISTER)		\
-   || (unsigned) reg_renumber[REGNO] < FIRST_EXTENDED_REGISTER)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.
-   Double constants should be in a register iff they can be made cheaply.  */
-#define PREFERRED_RELOAD_CLASS(X,CLASS)	\
-   (CONSTANT_P(X) && (CLASS == XRF_REGS) ? NO_REGS : (CLASS))
-
-/* Return the register class of a scratch register needed to load IN
-   into a register of class CLASS in MODE.  On the m88k, when PIC, we
-   need a temporary when loading some addresses into a register.  */
-#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN)		\
-  ((flag_pic							\
-    && GET_CODE (IN) == CONST					\
-    && GET_CODE (XEXP (IN, 0)) == PLUS				\
-    && GET_CODE (XEXP (XEXP (IN, 0), 0)) == CONST_INT		\
-    && ! SMALL_INT (XEXP (XEXP (IN, 0), 1))) ? GENERAL_REGS : NO_REGS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-#define CLASS_MAX_NREGS(CLASS, MODE) \
-  ((((CLASS) == XRF_REGS) ? 1 \
-    : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
-
-/* Letters in the range `I' through `P' in a register constraint string can
-   be used to stand for particular ranges of immediate operands.  The C
-   expression is true iff C is a known letter and VALUE is appropriate for
-   that letter.
-
-   For the m88000, the following constants are used:
-   `I' requires a non-negative 16-bit value.
-   `J' requires a non-positive 16-bit value.
-   `K' requires a non-negative value < 32.
-   `L' requires a constant with only the upper 16-bits set.
-   `M' requires constant values that can be formed with `set'.
-   `N' requires a negative value.
-   `O' requires zero.
-   `P' requires a non-negative value.  */
-
-/* Quick tests for certain values.  */
-#define SMALL_INT(X) (SMALL_INTVAL (INTVAL (X)))
-#define SMALL_INTVAL(I) ((unsigned) (I) < 0x10000)
-#define ADD_INT(X) (ADD_INTVAL (INTVAL (X)))
-#define ADD_INTVAL(I) ((unsigned) (I) + 0xffff < 0x1ffff)
-#define POWER_OF_2(I) ((I) && POWER_OF_2_or_0(I))
-#define POWER_OF_2_or_0(I) (((I) & ((unsigned)(I) - 1)) == 0)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)			\
-  ((C) == 'I' ? SMALL_INTVAL (VALUE)			\
-   : (C) == 'J' ? SMALL_INTVAL (-(VALUE))		\
-   : (C) == 'K' ? (unsigned)(VALUE) < 32		\
-   : (C) == 'L' ? ((VALUE) & 0xffff) == 0		\
-   : (C) == 'M' ? integer_ok_for_set (VALUE)		\
-   : (C) == 'N' ? (VALUE) < 0				\
-   : (C) == 'O' ? (VALUE) == 0				\
-   : (C) == 'P' ? (VALUE) >= 0				\
-   : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  For the m88000, the
-   constraints are:  `G' requires zero, and `H' requires one or two.  */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)				\
-  ((C) == 'G' ? (CONST_DOUBLE_HIGH (VALUE) == 0				\
-		 && CONST_DOUBLE_LOW (VALUE) == 0)			\
-   : 0)
-
-/* Letters in the range `Q' through `U' in a register constraint string
-   may be defined in a machine-dependent fashion to stand for arbitrary
-   operand types.
-
-   For the m88k, `Q' handles addresses in a call context.  */
-
-#define EXTRA_CONSTRAINT(OP, C)				\
-  ((C) == 'Q' ? symbolic_address_p (OP) : 0)
-
-/*** Describing Stack Layout ***/
-
-/* Define this if pushing a word on the stack moves the stack pointer
-   to a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the addresses of local variable slots are at negative
-   offsets from the frame pointer.  */
-/* #define FRAME_GROWS_DOWNWARD */
-
-/* Offset from the frame pointer to the first local variable slot to be
-   allocated. For the m88k, the debugger wants the return address (r1)
-   stored at location r30+4, and the previous frame pointer stored at
-   location r30.  */
-#define STARTING_FRAME_OFFSET 8
-
-/* If we generate an insn to push BYTES bytes, this says how many the
-   stack pointer really advances by.  The m88k has no push instruction.  */
-/*  #define PUSH_ROUNDING(BYTES) */
-
-/* If defined, the maximum amount of space required for outgoing arguments
-   will be computed and placed into the variable
-   `current_function_outgoing_args_size'.  No space will be pushed
-   onto the stack for each call; instead, the function prologue should
-   increase the stack frame size by this amount.  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Offset from the stack pointer register to the first location at which
-   outgoing arguments are placed.  Use the default value zero.  */
-/* #define STACK_POINTER_OFFSET 0 */
-
-/* Offset of first parameter from the argument pointer register value.
-   Using an argument pointer, this is 0 for the m88k.  GCC knows
-   how to eliminate the argument pointer references if necessary.  */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Define this if functions should assume that stack space has been
-   allocated for arguments even when their values are passed in
-   registers.
-
-   The value of this macro is the size, in bytes, of the area reserved for
-   arguments passed in registers.
-
-   This space can either be allocated by the caller or be a part of the
-   machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
-   says which.  */
-#define REG_PARM_STACK_SPACE(FNDECL) 32
-
-/* Define this macro if REG_PARM_STACK_SPACE is defined but stack
-   parameters don't skip the area specified by REG_PARM_STACK_SPACE.
-   Normally, when a parameter is not passed in registers, it is placed on
-   the stack beyond the REG_PARM_STACK_SPACE area.  Defining this macro
-   suppresses this behavior and causes the parameter to be passed on the
-   stack in its natural location.  */
-#define STACK_PARMS_IN_REG_PARM_AREA
-
-/* Define this if it is the responsibility of the caller to allocate the
-   area reserved for arguments passed in registers.  If
-   `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect of this
-   macro is to determine whether the space is included in
-   `current_function_outgoing_args_size'.  */
-/* #define OUTGOING_REG_PARM_STACK_SPACE */
-
-/* Offset from the stack pointer register to an item dynamically allocated
-   on the stack, e.g., by `alloca'.
-
-   The default value for this macro is `STACK_POINTER_OFFSET' plus the
-   length of the outgoing arguments.  The default is correct for most
-   machines.  See `function.c' for details.  */
-/* #define STACK_DYNAMIC_OFFSET(FUNDECL) ... */
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-  gen_rtx (REG, \
-	   TYPE_MODE (VALTYPE) == BLKmode ? SImode : TYPE_MODE (VALTYPE), \
-	   2)
-
-/* Define this if it differs from FUNCTION_VALUE.  */
-/* #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) ... */
-
-/* Disable the promotion of some structures and unions to registers. */
-#define RETURN_IN_MEMORY(TYPE) \
-  (TYPE_MODE (TYPE) == BLKmode \
-   || ((TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE(TYPE) == UNION_TYPE) \
-       && !(TYPE_MODE (TYPE) == SImode \
-	    || (TYPE_MODE (TYPE) == BLKmode \
-		&& TYPE_ALIGN (TYPE) == BITS_PER_WORD \
-		&& int_size_in_bytes (TYPE) == UNITS_PER_WORD))))
-
-/* Don't default to pcc-struct-return, because we have already specified
-   exactly how to return structures in the RETURN_IN_MEMORY macro.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, 2)
-
-/* True if N is a possible register number for a function value
-   as seen by the caller.  */
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 2)
-
-/* Determine whether a function argument is passed in a register, and
-   which register.  See m88k.c.  */
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  m88k_function_arg (CUM, MODE, TYPE, NAMED)
-
-/* Define this if it differs from FUNCTION_ARG.  */
-/* #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) ... */
-
-/* A C expression for the number of words, at the beginning of an
-   argument, must be put in registers.  The value must be zero for
-   arguments that are passed entirely in registers or that are entirely
-   pushed on the stack.  */
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
-
-/* A C expression that indicates when an argument must be passed by
-   reference.  If nonzero for an argument, a copy of that argument is
-   made in memory and a pointer to the argument is passed instead of the
-   argument itself.  The pointer is passed in whatever way is appropriate
-   for passing a pointer to that type.  */
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) (0)
-
-/* A C type for declaring a variable that is used as the first argument
-   of `FUNCTION_ARG' and other related values.  It suffices to count
-   the number of words of argument so far.  */
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a
-   function whose data type is FNTYPE.  For a library call, FNTYPE is 0. */
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) ((CUM) = 0)
-
-/* A C statement (sans semicolon) to update the summarizer variable
-   CUM to advance past an argument in the argument list.  The values
-   MODE, TYPE and NAMED describe that argument.  Once this is done,
-   the variable CUM is suitable for analyzing the *following* argument
-   with `FUNCTION_ARG', etc.  (TYPE is null for libcalls where that
-   information may not be available.)  */
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
-  do {									\
-    enum machine_mode __mode = (TYPE) ? TYPE_MODE (TYPE) : (MODE);	\
-    if ((CUM & 1)							\
-	&& (__mode == DImode || __mode == DFmode			\
-	    || ((TYPE) && TYPE_ALIGN (TYPE) > BITS_PER_WORD)))		\
-      CUM++;								\
-    CUM += (((__mode != BLKmode)					\
-	     ? GET_MODE_SIZE (MODE) : int_size_in_bytes (TYPE))		\
-	    + 3) / 4;							\
-  } while (0)
-
-/* True if N is a possible register number for function argument passing.
-   On the m88000, these are registers 2 through 9.  */
-#define FUNCTION_ARG_REGNO_P(N) ((N) <= 9 && (N) >= 2)
-
-/* A C expression which determines whether, and in which direction,
-   to pad out an argument with extra space.  The value should be of
-   type `enum direction': either `upward' to pad above the argument,
-   `downward' to pad below, or `none' to inhibit padding.
-
-   This macro does not control the *amount* of padding; that is always
-   just enough to reach the next multiple of `FUNCTION_ARG_BOUNDARY'.  */
-#define FUNCTION_ARG_PADDING(MODE, TYPE) \
-  ((MODE) == BLKmode \
-   || ((TYPE) && (TREE_CODE (TYPE) == RECORD_TYPE \
-		  || TREE_CODE (TYPE) == UNION_TYPE)) \
-   ? upward : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY ? downward : none)
-
-/* If defined, a C expression that gives the alignment boundary, in bits,
-   of an argument with the specified mode and type.  If it is not defined,
-   `PARM_BOUNDARY' is used for all arguments.  */
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
-  (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
-    ? PARM_BOUNDARY : 2 * PARM_BOUNDARY)
-
-/* Generate necessary RTL for __builtin_saveregs().
-   ARGLIST is the argument list; see expr.c.  */
-#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) m88k_builtin_saveregs (ARGLIST)
-
-/* Generate the assembly code for function entry. */
-#define FUNCTION_PROLOGUE(FILE, SIZE) m88k_begin_prologue(FILE, SIZE)
-
-/* Perform special actions at the point where the prologue ends.  */
-#define FUNCTION_END_PROLOGUE(FILE) m88k_end_prologue(FILE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  Redefined in sysv3.h, sysv4.h and
-   dgux.h.  */
-#define FUNCTION_PROFILER(FILE, LABELNO) \
-  output_function_profiler (FILE, LABELNO, "mcount", 1)
-
-/* Maximum length in instructions of the code output by FUNCTION_PROFILER.  */
-#define FUNCTION_PROFILER_LENGTH (5+3+1+5)
-
-/* Output assembler code to FILE to initialize basic-block profiling for
-   the current module.  LABELNO is unique to each instance.  */
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
-  output_function_block_profiler (FILE, LABELNO)
-
-/* Maximum length in instructions of the code output by
-   FUNCTION_BLOCK_PROFILER.  */
-#define FUNCTION_BLOCK_PROFILER_LENGTH (3+5+2+5)
-
-/* Output assembler code to FILE to increment the count associated with
-   the basic block number BLOCKNO.  */
-#define BLOCK_PROFILER(FILE, BLOCKNO) output_block_profiler (FILE, BLOCKNO)
-
-/* Maximum length in instructions of the code output by BLOCK_PROFILER.  */
-#define BLOCK_PROFILER_LENGTH 4
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-#define EXIT_IGNORE_STACK (1)
-
-/* Generate the assembly code for function exit. */
-#define FUNCTION_EPILOGUE(FILE, SIZE) m88k_end_epilogue(FILE, SIZE)
-
-/* Perform special actions at the point where the epilogue begins.  */
-#define FUNCTION_BEGIN_EPILOGUE(FILE) m88k_begin_epilogue(FILE)
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED \
-(current_function_varargs 					\
- || (TARGET_OMIT_LEAF_FRAME_POINTER && !leaf_function_p ()) 	\
- || (write_symbols != NO_DEBUG && !TARGET_OCS_FRAME_POSITION))
-
-/* Definitions for register eliminations.
-
-   We have two registers that can be eliminated on the m88k.  First, the
-   frame pointer register can often be eliminated in favor of the stack
-   pointer register.  Secondly, the argument pointer register can always be
-   eliminated; it is replaced with either the stack or frame pointer.  */
-
-/* This is an array of structures.  Each structure initializes one pair
-   of eliminable registers.  The "from" register number is given first,
-   followed by "to".  Eliminations of the same "from" register are listed
-   in order of preference.  */
-#define ELIMINABLE_REGS				\
-{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},	\
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
-
-/* Given FROM and TO register numbers, say whether this elimination
-   is allowed.  */
-#define CAN_ELIMINATE(FROM, TO) \
-  (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
-
-/* Define the offset between two registers, one to be eliminated, and the other
-   its replacement, at the start of a routine.  */
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			 \
-{ m88k_layout_frame ();							 \
-  if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	 \
-      (OFFSET) = m88k_fp_offset;					 \
-  else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
-    (OFFSET) = m88k_stack_size - m88k_fp_offset;			 \
-  else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
-    (OFFSET) = m88k_stack_size;						 \
-  else									 \
-    abort ();								 \
-}
-
-/*** Trampolines for Nested Functions ***/
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.
-
-   This block is placed on the stack and filled in.  It is aligned
-   0 mod 128 and those portions that are executed are constant.
-   This should work for instruction caches that have cache lines up
-   to the aligned amount (128 is arbitrary), provided no other code
-   producer is attempting to play the same game.  This of course is
-   in violation of any number of 88open standards.  */
-
-#define TRAMPOLINE_TEMPLATE(FILE)					\
-{									\
-  char buf[256];							\
-  static int labelno = 0;						\
-  labelno++;								\
-  ASM_GENERATE_INTERNAL_LABEL (buf, "LTRMP", labelno);			\
-  /* Save the return address (r1) in the static chain reg (r11).  */	\
-  fprintf (FILE, "\tor\t %s,%s,0\n", reg_names[11], reg_names[1]);	\
-  /* Locate this block; transfer to the next instruction.  */		\
-  fprintf (FILE, "\tbsr\t %s\n", &buf[1]);					\
-  ASM_OUTPUT_INTERNAL_LABEL (FILE, "LTRMP", labelno);			\
-  /* Save r10; use it as the relative pointer; restore r1.  */		\
-  fprintf (FILE, "\tst\t %s,%s,24\n", reg_names[10], reg_names[1]);	\
-  fprintf (FILE, "\tor\t %s,%s,0\n", reg_names[10], reg_names[1]);	\
-  fprintf (FILE, "\tor\t %s,%s,0\n", reg_names[1], reg_names[11]);	\
-  /* Load the function's address and go there.  */			\
-  fprintf (FILE, "\tld\t %s,%s,32\n", reg_names[11], reg_names[10]);	\
-  fprintf (FILE, "\tjmp.n\t %s\n", reg_names[11]);			\
-  /* Restore r10 and load the static chain register.  */		\
-  fprintf (FILE, "\tld.d\t %s,%s,24\n", reg_names[10], reg_names[10]);	\
-  /* Storage: r10 save area, static chain, function address.  */	\
-  ASM_OUTPUT_INT (FILE, const0_rtx);					\
-  ASM_OUTPUT_INT (FILE, const0_rtx);					\
-  ASM_OUTPUT_INT (FILE, const0_rtx);					\
-}
-
-/* Length in units of the trampoline for entering a nested function.
-   This is really two components.  The first 32 bytes are fixed and
-   must be copied; the last 12 bytes are just storage that's filled
-   in later.  So for allocation purposes, it's 32+12 bytes, but for
-   initialization purposes, it's 32 bytes.  */
-
-#define TRAMPOLINE_SIZE (32+12)
-
-/* Alignment required for a trampoline.  128 is used to find the
-   beginning of a line in the instruction cache and to allow for
-   instruction cache lines of up to 128 bytes.  */
-
-#define TRAMPOLINE_ALIGNMENT 128
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 40)), FNADDR); \
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 36)), CXT); \
-}
-
-/*** Library Subroutine Names ***/
-
-/* Define this macro if GNU CC should generate calls to the System V
-   (and ANSI C) library functions `memcpy' and `memset' rather than
-   the BSD functions `bcopy' and `bzero'.  */
-#define TARGET_MEM_FUNCTIONS
-
-/*** Addressing Modes ***/
-
-#define EXTRA_CC_MODES CCEVENmode
-
-#define EXTRA_CC_NAMES "CCEVEN"
-
-#define SELECT_CC_MODE(OP,X,Y) CCmode
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Recognize any constant value that is a valid address.
-   When PIC, we do not accept an address that would require a scratch reg
-   to load into a register.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH                 \
-   || (GET_CODE (X) == CONST                                            \
-       && ! (flag_pic && pic_address_needs_scratch (X))))
-
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-#define MAX_REGS_PER_ADDRESS 2
-
-/* The condition for memory shift insns.  */
-#define SCALED_ADDRESS_P(ADDR)			\
-  (GET_CODE (ADDR) == PLUS			\
-   && (GET_CODE (XEXP (ADDR, 0)) == MULT	\
-       || GET_CODE (XEXP (ADDR, 1)) == MULT))
-
-/* Can the reference to X be made short?  */
-#define SHORT_ADDRESS_P(X,TEMP) \
-  ((TEMP) = (GET_CODE (X) == CONST ? get_related_value (X) : X), \
-   ((TEMP) && GET_CODE (TEMP) == SYMBOL_REF && SYMBOL_REF_FLAG (TEMP)))
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   On the m88000, a legitimate address has the form REG, REG+REG,
-   REG+SMALLINT, REG+(REG*modesize) (REG[REG]), or SMALLINT.
-
-   The register elimination process should deal with the argument
-   pointer and frame pointer changing to REG+SMALLINT.  */
-
-#define LEGITIMATE_INDEX_P(X, MODE)			\
-   ((GET_CODE (X) == CONST_INT				\
-     && SMALL_INT (X))					\
-    || (REG_P (X)					\
-	&& REG_OK_FOR_INDEX_P (X))			\
-    || (GET_CODE (X) == MULT				\
-	&& REG_P (XEXP (X, 0))				\
-	&& REG_OK_FOR_INDEX_P (XEXP (X, 0))		\
-	&& GET_CODE (XEXP (X, 1)) == CONST_INT		\
-	&& INTVAL (XEXP (X, 1)) == GET_MODE_SIZE (MODE)))
-
-#define RTX_OK_FOR_BASE_P(X)						\
-  ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
-  || (GET_CODE (X) == SUBREG						\
-      && GET_CODE (SUBREG_REG (X)) == REG				\
-      && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
-
-#define RTX_OK_FOR_INDEX_P(X)						\
-  ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))			\
-  || (GET_CODE (X) == SUBREG						\
-      && GET_CODE (SUBREG_REG (X)) == REG				\
-      && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)		\
-{							\
-  register rtx _x;					\
-  if (REG_P (X))					\
-    {							\
-      if (REG_OK_FOR_BASE_P (X))			\
-	goto ADDR;					\
-    }							\
-  else if (GET_CODE (X) == PLUS)			\
-    {							\
-      register rtx _x0 = XEXP (X, 0);			\
-      register rtx _x1 = XEXP (X, 1);			\
-      if ((flag_pic					\
-	   && _x0 == pic_offset_table_rtx		\
-	   && (flag_pic == 2				\
-	       ? RTX_OK_FOR_BASE_P (_x1)		\
-	       : (GET_CODE (_x1) == SYMBOL_REF		\
-		  || GET_CODE (_x1) == LABEL_REF)))	\
-	  || (REG_P (_x0)				\
-	      && (REG_OK_FOR_BASE_P (_x0)		\
-		  && LEGITIMATE_INDEX_P (_x1, MODE)))	\
-	  || (REG_P (_x1)				\
-	      && (REG_OK_FOR_BASE_P (_x1)		\
-		  && LEGITIMATE_INDEX_P (_x0, MODE))))	\
-	goto ADDR;					\
-    }							\
-  else if (GET_CODE (X) == LO_SUM)			\
-    {							\
-      register rtx _x0 = XEXP (X, 0);			\
-      register rtx _x1 = XEXP (X, 1);			\
-      if (((REG_P (_x0)					\
-	    && REG_OK_FOR_BASE_P (_x0))			\
-	   || (GET_CODE (_x0) == SUBREG			\
-	       && REG_P (SUBREG_REG (_x0))		\
-	       && REG_OK_FOR_BASE_P (SUBREG_REG (_x0)))) \
-	  && CONSTANT_P (_x1))				\
-	goto ADDR;					\
-    }							\
-  else if (GET_CODE (X) == CONST_INT			\
-	   && SMALL_INT (X))				\
-    goto ADDR;						\
-  else if (SHORT_ADDRESS_P (X, _x))			\
-    goto ADDR;						\
-}
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  Not the argument pointer.  */
-#define REG_OK_FOR_INDEX_P(X)                                         \
-  (!XRF_REGNO_P(REGNO (X)))
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) (REG_OK_FOR_INDEX_P (X))
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.  */
-
-/* On the m88000, change REG+N into REG+REG, and REG+(X*Y) into REG+REG.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)			\
-{								\
-  if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1)))	\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 0),			\
-		   copy_to_mode_reg (SImode, XEXP (X, 1)));	\
-  if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0)))	\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 1),			\
-		   copy_to_mode_reg (SImode, XEXP (X, 0)));	\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT)	\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 1),			\
-		   force_operand (XEXP (X, 0), 0));		\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT)	\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 0),			\
-		   force_operand (XEXP (X, 1), 0));		\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS)	\
-    (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
-		   XEXP (X, 1));				\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS)	\
-    (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0),			\
-		   force_operand (XEXP (X, 1), NULL_RTX));	\
-  if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST	\
-	   || GET_CODE (X) == LABEL_REF)			\
-    (X) = legitimize_address (flag_pic, X, 0, 0);		\
-  if (memory_address_p (MODE, X))				\
-    goto WIN; }
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the m88000 this is never true.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-#define LEGITIMATE_CONSTANT_P(X) (1)
-
-/* Define this, so that when PIC, reload won't try to reload invalid
-   addresses which require two reload registers.  */
-
-#define LEGITIMATE_PIC_OPERAND_P(X)  (! pic_address_needs_scratch (X))
-
-
-/*** Condition Code Information ***/
-
-/* C code for a data type which is used for declaring the `mdep'
-   component of `cc_status'.  It defaults to `int'.  */
-/* #define CC_STATUS_MDEP int */
-
-/* A C expression to initialize the `mdep' field to "empty".  */
-/* #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0) */
-
-/* Macro to zap the normal portions of CC_STATUS, but leave the
-   machine dependent parts (ie, literal synthesis) alone.  */
-/* #define CC_STATUS_INIT_NO_MDEP \
-  (cc_status.flags = 0, cc_status.value1 = 0, cc_status.value2 = 0) */
-
-/* When using a register to hold the condition codes, the cc_status
-   mechanism cannot be used.  */
-#define NOTICE_UPDATE_CC(EXP, INSN) (0)
-
-/*** Miscellaneous Parameters ***/
-
-/* Define the codes that are matched by predicates in m88k.c.  */
-#define PREDICATE_CODES	  						\
-  {"move_operand", {SUBREG, REG, CONST_INT, LO_SUM, MEM}},		\
-  {"call_address_operand", {SUBREG, REG, SYMBOL_REF, LABEL_REF, CONST}}, \
-  {"arith_operand", {SUBREG, REG, CONST_INT}},				\
-  {"arith5_operand", {SUBREG, REG, CONST_INT}},				\
-  {"arith32_operand", {SUBREG, REG, CONST_INT}},			\
-  {"arith64_operand", {SUBREG, REG, CONST_INT}},			\
-  {"int5_operand", {CONST_INT}},					\
-  {"int32_operand", {CONST_INT}},					\
-  {"add_operand", {SUBREG, REG, CONST_INT}},				\
-  {"reg_or_bbx_mask_operand", {SUBREG, REG, CONST_INT}},		\
-  {"real_or_0_operand", {SUBREG, REG, CONST_DOUBLE}},			\
-  {"reg_or_0_operand", {SUBREG, REG, CONST_INT}},                       \
-  {"relop", {EQ, NE, LT, LE, GE, GT, LTU, LEU, GEU, GTU}},		\
-  {"even_relop", {EQ, LT, GT, LTU, GTU}},		\
-  {"odd_relop", { NE, LE, GE, LEU, GEU}},		\
-  {"partial_ccmode_register_operand", { SUBREG, REG}},			\
-  {"relop_no_unsigned", {EQ, NE, LT, LE, GE, GT}},			\
-  {"equality_op", {EQ, NE}},						\
-  {"pc_or_label_ref", {PC, LABEL_REF}},
-
-/* The case table contains either words or branch instructions.  This says
-   which.  We always claim that the vector is PC-relative.  It is position
-   independent when -fpic is used.  */
-#define CASE_VECTOR_INSNS (TARGET_88100 || flag_pic)
-
-/* An alias for a machine mode name.  This is the machine mode that
-   elements of a jump-table should have.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE 1
-
-/* Define this if control falls through a `case' insn when the index
-   value is out of range.  This means the specified default-label is
-   actually ignored by the `case' insn proper.  */
-/* #define CASE_DROPS_THROUGH */
-
-/* Define this to be the smallest number of different values for which it
-   is best to use a jump-table instead of a tree of conditional branches.
-   The default is 4 for machines with a casesi instruction and 5 otherwise.
-   The best 88110 number is around 7, though the exact number isn't yet
-   known.  A third alternative for the 88110 is to use a binary tree of
-   bb1 instructions on bits 2/1/0 if the range is dense.  This may not
-   win very much though.  */
-#define CASE_VALUES_THRESHOLD (TARGET_88100 ? 4 : 7)
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* The 88open ABI says size_t is unsigned int.  */
-#define SIZE_TYPE "unsigned int"
-
-/* Allow and ignore #sccs directives */
-#define SCCS_DIRECTIVE
-
-/* Handle #pragma pack and sometimes #pragma weak.  */
-#define HANDLE_SYSV_PRAGMA
-
-/* Tell when to handle #pragma weak.  This is only done for V.4.  */
-#define SUPPORTS_WEAK TARGET_SVR4
-#define SUPPORTS_ONE_ONLY TARGET_SVR4
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 8
-
-/* Define if normal loads of shorter-than-word items from memory clears
-   the rest of the bigs in the register.  */
-#define BYTE_LOADS_ZERO_EXTEND
-
-/* Zero if access to memory by bytes is faster.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.  */
-#define NO_FUNCTION_CSE
-
-/* Define this macro if an argument declared as `char' or
-   `short' in a prototype should actually be passed as an
-   `int'.  In addition to avoiding errors in certain cases of
-   mismatch, it also makes for better code on certain machines.  */
-#define PROMOTE_PROTOTYPES
-
-/* Define this macro if a float function always returns float
-   (even in traditional mode).  Redefined in luna.h.  */
-#define TRADITIONAL_RETURN_FLOAT
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-#define STORE_FLAG_VALUE -1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a word address (for indexing purposes)
-   so give the MEM rtx word mode.  */
-#define FUNCTION_MODE SImode
-
-/* A barrier will be aligned so account for the possible expansion.
-   A volatile load may be preceded by a serializing instruction.
-   Account for profiling code output at NOTE_INSN_PROLOGUE_END.
-   Account for block profiling code at basic block boundaries.  */
-#define ADJUST_INSN_LENGTH(RTX, LENGTH)					\
-  if (GET_CODE (RTX) == BARRIER						\
-      || (TARGET_SERIALIZE_VOLATILE					\
-	  && GET_CODE (RTX) == INSN					\
-	  && GET_CODE (PATTERN (RTX)) == SET				\
-	  && ((GET_CODE (SET_SRC (PATTERN (RTX))) == MEM		\
-	       && MEM_VOLATILE_P (SET_SRC (PATTERN (RTX)))))))		\
-    LENGTH += 1;							\
-  else if (GET_CODE (RTX) == NOTE					\
-	   && NOTE_LINE_NUMBER (RTX) == NOTE_INSN_PROLOGUE_END)		\
-    {									\
-      if (profile_block_flag)						\
-	LENGTH += FUNCTION_BLOCK_PROFILER_LENGTH;			\
-      if (profile_flag)							\
-	LENGTH += (FUNCTION_PROFILER_LENGTH + REG_PUSH_LENGTH		\
-		   + REG_POP_LENGTH);					\
-    }									\
-  else if (profile_block_flag						\
-	   && (GET_CODE (RTX) == CODE_LABEL				\
-	       || GET_CODE (RTX) == JUMP_INSN				\
-	       || (GET_CODE (RTX) == INSN				\
-		   && GET_CODE (PATTERN (RTX)) == SEQUENCE		\
-		   && GET_CODE (XVECEXP (PATTERN (RTX), 0, 0)) == JUMP_INSN)))\
-    LENGTH += BLOCK_PROFILER_LENGTH;
-
-/* Track the state of the last volatile memory reference.  Clear the
-   state with CC_STATUS_INIT for now.  */
-#define CC_STATUS_INIT m88k_volatile_code = '\0'
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.
-
-   We assume that any 16 bit integer can easily be recreated, so we
-   indicate 0 cost, in an attempt to get GCC not to optimize things
-   like comparison against a constant.
-
-   The cost of CONST_DOUBLE is zero (if it can be placed in an insn, it
-   is as good as a register; since it can't be placed in any insn, it
-   won't do anything in cse, but it will cause expand_binop to pass the
-   constant to the define_expands).  */
-#define CONST_COSTS(RTX,CODE,OUTER_CODE)		\
-  case CONST_INT:					\
-    if (SMALL_INT (RTX))				\
-      return 0;						\
-    else if (SMALL_INTVAL (- INTVAL (RTX)))		\
-      return 2;						\
-    else if (classify_integer (SImode, INTVAL (RTX)) != m88k_oru_or) \
-      return 4;						\
-    return 7;						\
-  case HIGH:						\
-    return 2;						\
-  case CONST:						\
-  case LABEL_REF:					\
-  case SYMBOL_REF:					\
-    if (flag_pic)					\
-      return (flag_pic == 2) ? 11 : 8;			\
-    return 5;						\
-  case CONST_DOUBLE:					\
-    return 0;
-
-/* Provide the costs of an addressing mode that contains ADDR.
-   If ADDR is not a valid address, its cost is irrelevant.
-   REG+REG is made slightly more expensive because it might keep
-   a register live for longer than we might like.  */
-#define ADDRESS_COST(ADDR)				\
-  (GET_CODE (ADDR) == REG ? 1 :				\
-   GET_CODE (ADDR) == LO_SUM ? 1 :			\
-   GET_CODE (ADDR) == HIGH ? 2 :			\
-   GET_CODE (ADDR) == MULT ? 1 :			\
-   GET_CODE (ADDR) != PLUS ? 4 :			\
-   (REG_P (XEXP (ADDR, 0)) && REG_P (XEXP (ADDR, 1))) ? 2 : 1)
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  */
-#define RTX_COSTS(X,CODE,OUTER_CODE)				\
-  case MEM:						\
-    return COSTS_N_INSNS (2);				\
-  case MULT:						\
-    return COSTS_N_INSNS (3);				\
-  case DIV:						\
-  case UDIV:						\
-  case MOD:						\
-  case UMOD:						\
-    return COSTS_N_INSNS (38);
-
-/* A C expressions returning the cost of moving data of MODE from a register
-   to or from memory.  This is more costly than between registers.  */
-#define MEMORY_MOVE_COST(MODE,CLASS,IN) 4
-
-/* Provide the cost of a branch.  Exact meaning under development.  */
-#define BRANCH_COST (TARGET_88100 ? 1 : 2)
-
-/* A C statement (sans semicolon) to update the integer variable COST
-   based on the relationship between INSN that is dependent on
-   DEP_INSN through the dependence LINK.  The default is to make no
-   adjustment to COST.  On the m88k, ignore the cost of anti- and
-   output-dependencies.  On the m88100, a store can issue two cycles
-   before the value (not the address) has finished computing.  */
-#define ADJUST_COST(INSN,LINK,DEP_INSN,COST)				\
-  do {									\
-    if (REG_NOTE_KIND (LINK) != 0)					\
-      (COST) = 0; /* Anti or output dependence.  */			\
-    else if (! TARGET_88100						\
-	     && recog_memoized (INSN) >= 0				\
-	     && get_attr_type (INSN) == TYPE_STORE			\
-	     && SET_SRC (PATTERN (INSN)) == SET_DEST (PATTERN (DEP_INSN))) \
-      (COST) -= 4; /* 88110 store reservation station.  */		\
-  } while (0)
-
-/* Do not break .stabs pseudos into continuations.  */
-#define DBX_CONTIN_LENGTH 0
-
-/*** Output of Assembler Code ***/
-
-/* Control the assembler format that we output.  */
-
-/* A C string constant describing how to begin a comment in the target
-   assembler language.  The compiler assumes that the comment will end at
-   the end of the line.  */
-#define ASM_COMMENT_START ";"
-
-/* Allow pseudo-ops to be overridden.  Override these in svr[34].h.  */
-#undef	INT_ASM_OP
-#undef	ASCII_DATA_ASM_OP
-#undef	CONST_SECTION_ASM_OP
-#undef	CTORS_SECTION_ASM_OP
-#undef	DTORS_SECTION_ASM_OP
-#undef  ASM_OUTPUT_SECTION_NAME
-#undef	INIT_SECTION_ASM_OP
-#undef	FINI_SECTION_ASM_OP
-#undef	TYPE_ASM_OP
-#undef	SIZE_ASM_OP
-#undef	SET_ASM_OP
-#undef	SKIP_ASM_OP
-#undef	COMMON_ASM_OP
-#undef	ALIGN_ASM_OP
-#undef	IDENT_ASM_OP
-
-/* These are used in varasm.c as well.  */
-#define TEXT_SECTION_ASM_OP	"text"
-#define DATA_SECTION_ASM_OP	"data"
-
-/* Other sections.  */
-#define CONST_SECTION_ASM_OP (TARGET_SVR4			\
-			      ? "section\t .rodata,\"a\""	\
-			      : "section\t .rodata,\"x\"")
-#define TDESC_SECTION_ASM_OP (TARGET_SVR4			\
-			      ? "section\t .tdesc,\"a\""	\
-			      : "section\t .tdesc,\"x\"")
-
-/* These must be constant strings for crtstuff.c.  */
-#define CTORS_SECTION_ASM_OP	"section\t .ctors,\"d\""
-#define DTORS_SECTION_ASM_OP	"section\t .dtors,\"d\""
-#define INIT_SECTION_ASM_OP	"section\t .init,\"x\""
-#define FINI_SECTION_ASM_OP	"section\t .fini,\"x\""
-
-/* These are pretty much common to all assemblers.  */
-#define IDENT_ASM_OP		"ident"
-#define FILE_ASM_OP		"file"
-#define SECTION_ASM_OP		"section"
-#define SET_ASM_OP		"def"
-#define GLOBAL_ASM_OP		"global"
-#define ALIGN_ASM_OP		"align"
-#define SKIP_ASM_OP		"zero"
-#define COMMON_ASM_OP		"comm"
-#define BSS_ASM_OP		"bss"
-#define FLOAT_ASM_OP		"float"
-#define DOUBLE_ASM_OP		"double"
-#define INT_ASM_OP		"word"
-#define ASM_LONG		INT_ASM_OP
-#define SHORT_ASM_OP		"half"
-#define CHAR_ASM_OP		"byte"
-#define ASCII_DATA_ASM_OP	"string"
-
-/* These are particular to the global pool optimization.  */
-#define SBSS_ASM_OP		"sbss"
-#define SCOMM_ASM_OP		"scomm"
-#define SDATA_SECTION_ASM_OP	"sdata"
-
-/* These are specific to PIC.  */
-#define TYPE_ASM_OP		"type"
-#define SIZE_ASM_OP		"size"
-#ifndef AS_BUG_POUND_TYPE /* Faulty assemblers require @ rather than #.  */
-#undef	TYPE_OPERAND_FMT
-#define TYPE_OPERAND_FMT	"#%s"
-#endif
-
-/* This is how we tell the assembler that a symbol is weak.  */
-
-#undef ASM_WEAKEN_LABEL
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
-  do { fputs ("\tweak\t", FILE); assemble_name (FILE, NAME); \
-       fputc ('\n', FILE); } while (0)
-
-/* These are specific to version 03.00 assembler syntax.  */
-#define INTERNAL_ASM_OP		"local"
-#define VERSION_ASM_OP		"version"
-#define UNALIGNED_SHORT_ASM_OP	"uahalf"
-#define UNALIGNED_INT_ASM_OP	"uaword"
-#define PUSHSECTION_ASM_OP	"section"
-#define POPSECTION_ASM_OP	"previous"
-
-/* These are specific to the version 04.00 assembler syntax.  */
-#define REQUIRES_88110_ASM_OP	"requires_88110"
-
-/* Output any initial stuff to the assembly file.  Always put out
-   a file directive, even if not debugging.
-
-   Immediately after putting out the file, put out a "sem.<value>"
-   declaration.  This should be harmless on other systems, and
-   is used in DG/UX by the debuggers to supplement COFF.  The
-   fields in the integer value are as follows:
-
-   Bits	Value	Meaning
-   ----	-----	-------
-   0-1	0	No information about stack locations
-	1	Auto/param locations are based on r30
-	2	Auto/param locations are based on CFA
-
-   3-2	0	No information on dimension order
-	1	Array dims in sym table matches source language
-	2	Array dims in sym table is in reverse order
-
-   5-4	0	No information about the case of global names
-	1	Global names appear in the symbol table as in the source
-	2	Global names have been converted to lower case
-	3	Global names have been converted to upper case.  */
-
-#ifdef SDB_DEBUGGING_INFO
-#define ASM_COFFSEM(FILE)						\
-    if (write_symbols == SDB_DEBUG)					\
-      {									\
-	fprintf (FILE, "\nsem.%x:\t\t; %s\n",				\
-		 (((TARGET_OCS_FRAME_POSITION) ? 2 : 1) << 0) + (1 << 2) + (1 << 4),\
-		 (TARGET_OCS_FRAME_POSITION)				\
-			? "frame is CFA, normal array dims, case unchanged" \
-			: "frame is r30, normal array dims, case unchanged"); \
-      }
-#else
-#define ASM_COFFSEM(FILE)
-#endif
-
-/* Output the first line of the assembly file.  Redefined in dgux.h.  */
-
-#define ASM_FIRST_LINE(FILE)						\
-  do {									\
-    if (TARGET_SVR4)							\
-      {									\
-	if (TARGET_88110)						\
-	  fprintf (FILE, "\t%s\t \"%s\"\n", VERSION_ASM_OP, "04.00");   \
-	else								\
-	  fprintf (FILE, "\t%s\t \"%s\"\n", VERSION_ASM_OP, "03.00");   \
-      }									\
-  } while (0)
-
-/* Override svr[34].h.  */
-#undef	ASM_FILE_START
-#define ASM_FILE_START(FILE) \
-  output_file_start (FILE, f_options, sizeof f_options / sizeof f_options[0], \
-		     W_options, sizeof W_options / sizeof W_options[0])
-
-#undef	ASM_FILE_END
-
-#define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) \
-  fprintf (FILE, "\t%s\t \"%s\"\n", FILE_ASM_OP, NAME)
-
-#ifdef SDB_DEBUGGING_INFO
-#undef ASM_OUTPUT_SOURCE_LINE
-#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE)			\
-  if (m88k_prologue_done)					\
-    fprintf (FILE, "\n\tln\t %d\t\t\t\t; Real source line %d\n",\
-	     LINE - sdb_begin_function_line, LINE)
-#endif
-
-/* Code to handle #ident directives.  Override svr[34].h definition.  */
-#undef	ASM_OUTPUT_IDENT
-#ifdef DBX_DEBUGGING_INFO
-#define ASM_OUTPUT_IDENT(FILE, NAME)
-#else
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  output_ascii (FILE, IDENT_ASM_OP, 4000, NAME, strlen (NAME));
-#endif
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-#define ASM_APP_OFF ""
-
-/* Format the assembly opcode so that the arguments are all aligned.
-   The maximum instruction size is 8 characters (fxxx.xxx), so a tab and a
-   space will do to align the output.  Abandon the output if a `%' is
-   encountered.  */
-#define ASM_OUTPUT_OPCODE(STREAM, PTR)					\
-  {									\
-    int ch;								\
-    char *orig_ptr;							\
-									\
-    for (orig_ptr = (PTR);						\
-	 (ch = *(PTR)) && ch != ' ' && ch != '\t' && ch != '\n' && ch != '%'; \
-	 (PTR)++)							\
-      putc (ch, STREAM);						\
-									\
-    if (ch == ' ' && orig_ptr != (PTR) && (PTR) - orig_ptr < 8)		\
-      putc ('\t', STREAM);						\
-  }
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number.
-   Updated by OVERRIDE_OPTIONS to include the # for version 03.00 syntax.  */
-
-#define REGISTER_NAMES \
-  {"#r0"+1, "#r1"+1, "#r2"+1, "#r3"+1, "#r4"+1, "#r5"+1, "#r6"+1, "#r7"+1, \
-   "#r8"+1, "#r9"+1, "#r10"+1,"#r11"+1,"#r12"+1,"#r13"+1,"#r14"+1,"#r15"+1,\
-   "#r16"+1,"#r17"+1,"#r18"+1,"#r19"+1,"#r20"+1,"#r21"+1,"#r22"+1,"#r23"+1,\
-   "#r24"+1,"#r25"+1,"#r26"+1,"#r27"+1,"#r28"+1,"#r29"+1,"#r30"+1,"#r31"+1,\
-   "#x0"+1, "#x1"+1, "#x2"+1, "#x3"+1, "#x4"+1, "#x5"+1, "#x6"+1, "#x7"+1, \
-   "#x8"+1, "#x9"+1, "#x10"+1,"#x11"+1,"#x12"+1,"#x13"+1,"#x14"+1,"#x15"+1,\
-   "#x16"+1,"#x17"+1,"#x18"+1,"#x19"+1,"#x20"+1,"#x21"+1,"#x22"+1,"#x23"+1,\
-   "#x24"+1,"#x25"+1,"#x26"+1,"#x27"+1,"#x28"+1,"#x29"+1,"#x30"+1,"#x31"+1}
-
-/* Define additional names for use in asm clobbers and asm declarations.
-
-   We define the fake Condition Code register as an alias for reg 0 (which
-   is our `condition code' register), so that condition codes can easily
-   be clobbered by an asm.  The carry bit in the PSR is now used.  */
-
-#define ADDITIONAL_REGISTER_NAMES	{"psr", 0, "cc", 0}
-
-/* How to renumber registers for dbx and gdb.  */
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Tell when to declare ASM names.  Override svr4.h to provide this hook.  */
-#undef	DECLARE_ASM_NAME
-#define DECLARE_ASM_NAME TARGET_SVR4
-
-/* Write the extra assembler code needed to declare a function properly.  */
-#undef	ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-  do {									\
-    if (DECLARE_ASM_NAME)						\
-      {									\
-	fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-	putc (',', FILE);						\
-	fprintf (FILE, TYPE_OPERAND_FMT, "function");			\
-	putc ('\n', FILE);						\
-      }									\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Write the extra assembler code needed to declare an object properly.  */
-#undef	ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			    \
-  do {									    \
-    if (DECLARE_ASM_NAME)						    \
-      {									    \
-	fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				    \
-	assemble_name (FILE, NAME);					    \
-	putc (',', FILE);						    \
-	fprintf (FILE, TYPE_OPERAND_FMT, "object");			    \
-	putc ('\n', FILE);						    \
-        size_directive_output = 0;					    \
-	if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		    \
-	  {								    \
-            size_directive_output = 1;					    \
-	    fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			    \
-	    assemble_name (FILE, NAME);					    \
-	    fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL))); \
-	  }								    \
-      }									    \
-    ASM_OUTPUT_LABEL(FILE, NAME);					    \
-  } while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#undef ASM_FINISH_DECLARE_OBJECT
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-	 && DECLARE_ASM_NAME						 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
-	 assemble_name (FILE, name);					 \
-	 fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL))); \
-       }								 \
-   } while (0)
-
-/* This is how to declare the size of a function.  */
-#undef	ASM_DECLARE_FUNCTION_SIZE
-#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)			\
-  do {									\
-    if (DECLARE_ASM_NAME)						\
-      {									\
-	if (!flag_inhibit_size_directive)				\
-	  {								\
-	    char label[256];						\
-	    static int labelno = 0;					\
-	    labelno++;							\
-	    ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno);	\
-	    ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno);		\
-	    fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			\
-	    assemble_name (FILE, (FNAME));				\
-	    fprintf (FILE, ",%s-", &label[1]);				\
-	    assemble_name (FILE, (FNAME));				\
-	    putc ('\n', FILE);						\
-	  }								\
-      }									\
-  } while (0)
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)			\
-  do {							\
-    fprintf (FILE, "\t%s\t ", GLOBAL_ASM_OP);		\
-    assemble_name (FILE, NAME);				\
-    putc ('\n', FILE);					\
-  } while (0)
-
-/* The prefix to add to user-visible assembler symbols.
-   Override svr[34].h.  */
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output a reference to a user-level label named NAME.
-   Override svr[34].h.  */
-#undef	ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE,NAME)			\
-  {							\
-    if (!TARGET_NO_UNDERSCORES && !TARGET_SVR4) 	\
-      fputc ('_', FILE);				\
-    fputs (NAME, FILE);					\
-  }
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   For V.4, labels use `.' rather than `@'.  */
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#ifdef AS_BUG_DOT_LABELS /* The assembler requires a declaration of local.  */
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)			\
-  fprintf (FILE, TARGET_SVR4 ? ".%s%d:\n\t%s\t .%s%d\n" : "@%s%d:\n", \
-	   PREFIX, NUM, INTERNAL_ASM_OP, PREFIX, NUM)
-#else
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)			\
-  fprintf (FILE, TARGET_SVR4 ? ".%s%d:\n" : "@%s%d:\n", PREFIX, NUM)
-#endif /* AS_BUG_DOT_LABELS */
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  This must agree
-   with ASM_OUTPUT_INTERNAL_LABEL above, except for being prefixed
-   with an `*'.  */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)			\
-  sprintf (LABEL, TARGET_SVR4 ? "*.%s%d" : "*@%s%d", PREFIX, NUM)
-
-/* Internal macro to get a single precision floating point value into
-   an int, so we can print its value in hex.  */
-#define FLOAT_TO_INT_INTERNAL( FVALUE, IVALUE )				\
-  { union {								\
-      REAL_VALUE_TYPE d;						\
-      struct {								\
-	unsigned sign      :  1;					\
-	unsigned exponent1 :  1;					\
-	unsigned exponent2 :  3;					\
-	unsigned exponent3 :  7;					\
-	unsigned mantissa1 : 20;					\
-	unsigned mantissa2 :  3;					\
-	unsigned mantissa3 : 29;					\
-      } s;								\
-    } _u;								\
-									\
-    union {								\
-      int i;								\
-      struct {								\
-        unsigned sign      :  1;					\
-	unsigned exponent1 :  1;					\
-	unsigned exponent3 :  7;					\
-        unsigned mantissa1 : 20;					\
-        unsigned mantissa2 :  3;					\
-      } s;								\
-    } _u2;								\
-									\
-    _u.d = REAL_VALUE_TRUNCATE (SFmode, FVALUE);			\
-    _u2.s.sign = _u.s.sign;						\
-    _u2.s.exponent1 = _u.s.exponent1;					\
-    _u2.s.exponent3 = _u.s.exponent3;					\
-    _u2.s.mantissa1 = _u.s.mantissa1;					\
-    _u2.s.mantissa2 = _u.s.mantissa2;					\
-    IVALUE = _u2.i;							\
-  }
-
-/* This is how to output an assembler line defining a `double' constant.
-   Use "word" pseudos to avoid printing NaNs, infinity, etc.  */
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)					\
-  do {									\
-    union { REAL_VALUE_TYPE d; long l[2]; } x;				\
-    x.d = (VALUE);							\
-    fprintf (FILE, "\t%s\t 0x%.8x, 0x%.8x\n", INT_ASM_OP,			\
-	     x.l[0], x.l[1]);						\
-  } while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
-  do {									\
-    int i;								\
-    FLOAT_TO_INT_INTERNAL (VALUE, i);					\
-    fprintf (FILE, "\t%s\t 0x%.8x\n", INT_ASM_OP, i);			\
-  } while (0)
-
-/* Likewise for `int', `short', and `char' constants.  */
-#define ASM_OUTPUT_INT(FILE,VALUE)					\
-( fprintf (FILE, "\t%s\t ", INT_ASM_OP),				\
-  output_addr_const (FILE, (VALUE)),					\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)					\
-( fprintf (FILE, "\t%s\t ", SHORT_ASM_OP),				\
-  output_addr_const (FILE, (VALUE)),					\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)					\
-( fprintf (FILE, "\t%s\t ", CHAR_ASM_OP),				\
-  output_addr_const (FILE, (VALUE)),					\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t%s\t 0x%x\n", CHAR_ASM_OP, (VALUE))
-
-/* The single-byte pseudo-op is the default.  Override svr[34].h.  */
-#undef	ASM_BYTE_OP
-#define ASM_BYTE_OP "byte"
-#undef	ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE, P, SIZE)  \
-  output_ascii (FILE, ASCII_DATA_ASM_OP, 48, P, SIZE)
-
-/* Override svr4.h.  Change to the readonly data section for a table of
-   addresses.  final_scan_insn changes back to the text section.  */
-#undef	ASM_OUTPUT_CASE_LABEL
-#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, TABLE)			\
-  do {									\
-    if (! CASE_VECTOR_INSNS)						\
-      {									\
-        readonly_data_section ();					\
-        ASM_OUTPUT_ALIGN (FILE, 2);					\
-      }									\
-    ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM);			\
-  } while (0)
-
-/* Epilogue for case labels.  This jump instruction is called by casesi
-   to transfer to the appropriate branch instruction within the table.
-   The label `@L<n>e' is coined to mark the end of the table.  */
-#define ASM_OUTPUT_CASE_END(FILE, NUM, TABLE)				\
-  do {									\
-    if (CASE_VECTOR_INSNS)						\
-      {									\
-	char label[256]; 						\
-	ASM_GENERATE_INTERNAL_LABEL (label, "L", NUM);			\
-	fprintf (FILE, "%se:\n", &label[1]);				\
-	if (! flag_delayed_branch)					\
-	  fprintf (FILE, "\tlda\t %s,%s[%s]\n", reg_names[1],		\
-		   reg_names[1], reg_names[m88k_case_index]);		\
-	fprintf (FILE, "\tjmp\t %s\n", reg_names[1]);			\
-      }									\
-  } while (0)
-
-/* This is how to output an element of a case-vector that is absolute.  */
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)				\
-  do {									\
-    char buffer[256];							\
-    ASM_GENERATE_INTERNAL_LABEL (buffer, "L", VALUE);			\
-    fprintf (FILE, CASE_VECTOR_INSNS ? "\tbr\t %s\n" : "\tword\t %s\n",	\
-	     &buffer[1]);						\
-  } while (0)
-
-/* This is how to output an element of a case-vector that is relative.  */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  ASM_OUTPUT_ADDR_VEC_ELT (FILE, VALUE)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t%s\t %d\n", ALIGN_ASM_OP, 1<<(LOG))
-
-/* On the m88100, align the text address to half a cache boundary when it
-   can only be reached by jumping.  Pack code tightly when compiling
-   crtstuff.c.  */
-#define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
-  (TARGET_88100 && !flag_inhibit_size_directive ? 3 : 2)
-
-/* Override svr[34].h.  */
-#undef	ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t%s\t %u\n", SKIP_ASM_OP, (SIZE))
-
-/* Override svr4.h.  */
-#undef	ASM_OUTPUT_EXTERNAL_LIBCALL
-
-/* This says how to output an assembler line to define a global common
-   symbol.  Size can be zero for the unusual case of a `struct { int : 0; }'.
-   Override svr[34].h.  */
-#undef	ASM_OUTPUT_COMMON
-#undef	ASM_OUTPUT_ALIGNED_COMMON
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)	\
-( fprintf ((FILE), "\t%s\t ",				\
-	   ((SIZE) ? (SIZE) : 1) <= m88k_gp_threshold ? SCOMM_ASM_OP : COMMON_ASM_OP), \
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ",%u\n", (SIZE) ? (SIZE) : 1))
-
-/* This says how to output an assembler line to define a local common
-   symbol.  Override svr[34].h.  */
-#undef	ASM_OUTPUT_LOCAL
-#undef	ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
-( fprintf ((FILE), "\t%s\t ",				\
-	   ((SIZE) ? (SIZE) : 1) <= m88k_gp_threshold ? SBSS_ASM_OP : BSS_ASM_OP), \
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ",%u,%d\n", (SIZE) ? (SIZE) : 1, (SIZE) <= 4 ? 4 : 8))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tsubu\t %s,%s,%d\n\tst\t %s,%s,0\n",	\
-	   reg_names[STACK_POINTER_REGNUM],		\
-	   reg_names[STACK_POINTER_REGNUM],		\
-	   (STACK_BOUNDARY / BITS_PER_UNIT),		\
-	   reg_names[REGNO],				\
-	   reg_names[STACK_POINTER_REGNUM])
-
-/* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH.  */
-#define REG_PUSH_LENGTH 2
-
-/* This is how to output an insn to pop a register from the stack.  */
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tld\t %s,%s,0\n\taddu\t %s,%s,%d\n",	\
-	   reg_names[REGNO],				\
-	   reg_names[STACK_POINTER_REGNUM],		\
-	   reg_names[STACK_POINTER_REGNUM],		\
-	   reg_names[STACK_POINTER_REGNUM],		\
-	   (STACK_BOUNDARY / BITS_PER_UNIT))
-
-/* Length in instructions of the code output by ASM_OUTPUT_REG_POP.  */
-#define REG_POP_LENGTH 2
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Macros to deal with OCS debug information */
-
-#define OCS_START_PREFIX	"Ltb"
-#define OCS_END_PREFIX		"Lte"
-
-#define PUT_OCS_FUNCTION_START(FILE) \
-  { ASM_OUTPUT_INTERNAL_LABEL (FILE, OCS_START_PREFIX, m88k_function_number); }
-
-#define PUT_OCS_FUNCTION_END(FILE) \
-  { ASM_OUTPUT_INTERNAL_LABEL (FILE, OCS_END_PREFIX, m88k_function_number); }
-
-/* Macros for debug information */
-#define DEBUGGER_AUTO_OFFSET(X) \
-  (m88k_debugger_offset (X, 0) \
-   + (TARGET_OCS_FRAME_POSITION ? 0 : m88k_stack_size - m88k_fp_offset))
-
-#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
-  (m88k_debugger_offset (X, OFFSET) \
-   + (TARGET_OCS_FRAME_POSITION ? 0 : m88k_stack_size - m88k_fp_offset))
-
-/* Macros to deal with SDB debug information */
-#ifdef SDB_DEBUGGING_INFO
-
-/* Output structure tag names even when it causes a forward reference. */
-#define SDB_ALLOW_FORWARD_REFERENCES
-
-/* Print out extra debug information in the assembler file */
-#define PUT_SDB_SCL(a)						\
-  do {								\
-    register int s = (a);					\
-    register char *scl;						\
-    switch (s)							\
-      {								\
-      case C_EFCN:	scl = "end of function";	break;	\
-      case C_NULL:	scl = "NULL storage class";	break;	\
-      case C_AUTO:	scl = "automatic";		break;	\
-      case C_EXT:	scl = "external";		break;	\
-      case C_STAT:	scl = "static";			break;	\
-      case C_REG:	scl = "register";		break;	\
-      case C_EXTDEF:	scl = "external definition";	break;	\
-      case C_LABEL:	scl = "label";			break;	\
-      case C_ULABEL:	scl = "undefined label";	break;	\
-      case C_MOS:	scl = "structure member";	break;	\
-      case C_ARG:	scl = "argument";		break;	\
-      case C_STRTAG:	scl = "structure tag";		break;	\
-      case C_MOU:	scl = "union member";		break;	\
-      case C_UNTAG:	scl = "union tag";		break;	\
-      case C_TPDEF:	scl = "typedef";		break;	\
-      case C_USTATIC:	scl = "uninitialized static";	break;	\
-      case C_ENTAG:	scl = "enumeration tag";	break;	\
-      case C_MOE:	scl = "member of enumeration";	break;	\
-      case C_REGPARM:	scl = "register parameter";	break;	\
-      case C_FIELD:	scl = "bit field";		break;	\
-      case C_BLOCK:	scl = "block start/end";	break;	\
-      case C_FCN:	scl = "function start/end";	break;	\
-      case C_EOS:	scl = "end of structure";	break;	\
-      case C_FILE:	scl = "filename";		break;	\
-      case C_LINE:	scl = "line";			break;	\
-      case C_ALIAS:	scl = "duplicated tag";		break;	\
-      case C_HIDDEN:	scl = "hidden";			break;	\
-      default:		scl = "unknown";		break;	\
-      }								\
-								\
-    fprintf(asm_out_file, "\tscl\t %d\t\t\t\t; %s\n", s, scl);	\
-  } while (0)
-
-#define PUT_SDB_TYPE(a)						\
-  do {								\
-    register int t = (a);					\
-    static char buffer[100];					\
-    register char *p = buffer, *q;				\
-    register int typ = t;					\
-    register int i,d;						\
-								\
-    for (i = 0; i <= 5; i++)					\
-      {								\
-	switch ((typ >> ((i*N_TSHIFT) + N_BTSHFT)) & 03)	\
-	  {							\
-	  case DT_PTR:						\
-	    strcpy (p, "ptr to ");				\
-	    p += sizeof("ptr to");				\
-	    break;						\
-								\
-	  case DT_ARY:						\
-	    strcpy (p, "array of ");				\
-	    p += sizeof("array of");				\
-	    break;						\
-								\
-	  case DT_FCN:						\
-	    strcpy (p, "func ret ");				\
-	    p += sizeof("func ret");				\
-	    break;						\
-	  }							\
-      }								\
-								\
-  switch (typ & N_BTMASK)					\
-    {								\
-    case T_NULL:	q = "<no type>";	break;		\
-    case T_CHAR:	q = "char";		break;		\
-    case T_SHORT:	q = "short";		break;		\
-    case T_INT:		q = "int";		break;		\
-    case T_LONG:	q = "long";		break;		\
-    case T_FLOAT:	q = "float";		break;		\
-    case T_DOUBLE:	q = "double";		break;		\
-    case T_STRUCT:	q = "struct";		break;		\
-    case T_UNION:	q = "union";		break;		\
-    case T_ENUM:	q = "enum";		break;		\
-    case T_MOE:		q = "enum member";	break;		\
-    case T_UCHAR:	q = "unsigned char";	break;		\
-    case T_USHORT:	q = "unsigned short";	break;		\
-    case T_UINT:	q = "unsigned int";	break;		\
-    case T_ULONG:	q = "unsigned long";	break;		\
-    default:		q = "void";		break;		\
-    }								\
-								\
-    strcpy (p, q);						\
-    fprintf(asm_out_file, "\ttype\t %d\t\t\t\t; %s\n",		\
-	    t, buffer);						\
-  } while (0)
-
-#define PUT_SDB_INT_VAL(a) \
-  fprintf (asm_out_file, "\tval\t %d\n", (a))
-
-#define PUT_SDB_VAL(a)					\
-( fprintf (asm_out_file, "\tval\t "),			\
-  output_addr_const (asm_out_file, (a)),		\
-  fputc ('\n', asm_out_file))
-
-#define PUT_SDB_DEF(a)						\
-  do { fprintf (asm_out_file, "\tsdef\t ");			\
-    ASM_OUTPUT_LABELREF (asm_out_file, a);			\
-    fputc ('\n', asm_out_file);					\
-  } while (0)
-
-#define PUT_SDB_PLAIN_DEF(a) \
-  fprintf(asm_out_file,"\tsdef\t .%s\n", a)
-
-/* Simply and endef now.  */
-#define PUT_SDB_ENDEF \
-  fputs("\tendef\n\n", asm_out_file)
-
-#define PUT_SDB_SIZE(a) \
-  fprintf (asm_out_file, "\tsize\t %d\n", (a))
-
-/* Max dimensions to store for debug information (limited by COFF).  */
-#define SDB_MAX_DIM 6
-
-/* New method for dim operations.  */
-#define PUT_SDB_START_DIM \
-  fputs("\tdim\t ", asm_out_file)
-
-/* How to end the DIM sequence.  */
-#define PUT_SDB_LAST_DIM(a) \
-  fprintf(asm_out_file, "%d\n", a)
-
-#define PUT_SDB_TAG(a)						\
-  do {								\
-    fprintf (asm_out_file, "\ttag\t ");				\
-    ASM_OUTPUT_LABELREF (asm_out_file, a);			\
-    fputc ('\n', asm_out_file);					\
-  } while( 0 )
-
-#define PUT_SDB_BLOCK_OR_FUNCTION(NAME, SCL, LINE)		\
-  do {								\
-    fprintf (asm_out_file, "\n\tsdef\t %s\n\tval\t .\n",	\
-	     NAME);						\
-    PUT_SDB_SCL( SCL );						\
-    fprintf (asm_out_file, "\tline\t %d\n\tendef\n\n",		\
-	     (LINE));						\
-  } while (0)
-
-#define PUT_SDB_BLOCK_START(LINE) \
-  PUT_SDB_BLOCK_OR_FUNCTION (".bb", C_BLOCK, (LINE))
-
-#define PUT_SDB_BLOCK_END(LINE) \
-  PUT_SDB_BLOCK_OR_FUNCTION (".eb", C_BLOCK, (LINE))
-
-#define PUT_SDB_FUNCTION_START(LINE)				\
-  do {								\
-    fprintf (asm_out_file, "\tln\t 1\n");			\
-    PUT_SDB_BLOCK_OR_FUNCTION (".bf", C_FCN, (LINE));		\
-  } while (0)
-
-#define PUT_SDB_FUNCTION_END(LINE)				\
-  do {								\
-    PUT_SDB_BLOCK_OR_FUNCTION (".ef", C_FCN, (LINE));		\
-  } while (0)
-
-#define PUT_SDB_EPILOGUE_END(NAME)				\
-  do {								\
-    text_section ();						\
-    fprintf (asm_out_file, "\n\tsdef\t ");			\
-    ASM_OUTPUT_LABELREF(asm_out_file, (NAME));			\
-    fputc('\n', asm_out_file);					\
-    PUT_SDB_SCL( C_EFCN );					\
-    fprintf (asm_out_file, "\tendef\n\n");			\
-  } while (0)
-
-#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
-  sprintf ((BUFFER), ".%dfake", (NUMBER));
-
-#endif /* SDB_DEBUGGING_INFO */
-
-/* Support const and tdesc sections.  Generally, a const section will
-   be distinct from the text section whenever we do V.4-like things
-   and so follows DECLARE_ASM_NAME.  Note that strings go in text
-   rather than const.  Override svr[34].h.  */
-
-#undef	USE_CONST_SECTION
-#undef	EXTRA_SECTIONS
-
-#define USE_CONST_SECTION DECLARE_ASM_NAME
-
-#if defined(USING_SVR4_H)
-
-#define EXTRA_SECTIONS in_const, in_tdesc, in_sdata, in_ctors, in_dtors
-#define INIT_SECTION_FUNCTION
-#define FINI_SECTION_FUNCTION
-
-#else
-#if defined(USING_SVR3_H)
-
-#define EXTRA_SECTIONS in_const, in_tdesc, in_sdata, in_ctors, in_dtors, \
-		       in_init, in_fini
-
-#else /* luna or other not based on svr[34].h.  */
-
-#undef INIT_SECTION_ASM_OP
-#define EXTRA_SECTIONS in_const, in_tdesc, in_sdata
-#define CONST_SECTION_FUNCTION						\
-void									\
-const_section ()							\
-{									\
-  text_section();							\
-}
-#define CTORS_SECTION_FUNCTION
-#define DTORS_SECTION_FUNCTION
-#define INIT_SECTION_FUNCTION
-#define FINI_SECTION_FUNCTION
-
-#endif /* USING_SVR3_H */
-#endif /* USING_SVR4_H */
-
-#undef	EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CONST_SECTION_FUNCTION						\
-									\
-void									\
-tdesc_section ()							\
-{									\
-  if (in_section != in_tdesc)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", TDESC_SECTION_ASM_OP);		\
-      in_section = in_tdesc;						\
-    }									\
-}									\
-									\
-void									\
-sdata_section ()							\
-{									\
-  if (in_section != in_sdata)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP);		\
-      in_section = in_sdata;						\
-    }									\
-}									\
-									\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION						\
-  INIT_SECTION_FUNCTION							\
-  FINI_SECTION_FUNCTION
-
-/* A C statement or statements to switch to the appropriate
-   section for output of DECL.  DECL is either a `VAR_DECL' node
-   or a constant of some sort.  RELOC indicates whether forming
-   the initial value of DECL requires link-time relocations.
-
-   For strings, the section is selected before the segment info is encoded.  */
-#undef	SELECT_SECTION
-#define SELECT_SECTION(DECL,RELOC)					\
-{									\
-  if (TREE_CODE (DECL) == STRING_CST)					\
-    {									\
-      if (! flag_writable_strings)					\
-	const_section ();						\
-      else if ( TREE_STRING_LENGTH (DECL) <= m88k_gp_threshold)		\
-	sdata_section ();						\
-      else								\
-	data_section ();						\
-    }									\
-  else if (TREE_CODE (DECL) == VAR_DECL)				\
-    {									\
-      if (SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)))			\
-	sdata_section ();						\
-      else if ((flag_pic && RELOC)					\
-	       || !TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)	\
-	       || !DECL_INITIAL (DECL)					\
-	       || (DECL_INITIAL (DECL) != error_mark_node		\
-		   && !TREE_CONSTANT (DECL_INITIAL (DECL))))		\
-	data_section ();						\
-      else								\
-	const_section ();						\
-    }									\
-  else									\
-    const_section ();							\
-}
-
-/* Jump tables consist of branch instructions and should be output in
-   the text section.  When we use a table of addresses, we explicitly
-   change to the readonly data section.  */
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* Define this macro if references to a symbol must be treated differently
-   depending on something about the variable or function named by the
-   symbol (such as what section it is in).
-
-   The macro definition, if any, is executed immediately after the rtl for
-   DECL has been created and stored in `DECL_RTL (DECL)'.  The value of the
-   rtl will be a `mem' whose address is a `symbol_ref'.
-
-   For the m88k, determine if the item should go in the global pool.  */
-#define ENCODE_SECTION_INFO(DECL)					\
-  do {									\
-    if (m88k_gp_threshold > 0)						\
-      if (TREE_CODE (DECL) == VAR_DECL)					\
-	{								\
-	  if (!TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL))	\
-	    {								\
-	      int size = int_size_in_bytes (TREE_TYPE (DECL));		\
-									\
-	      if (size > 0 && size <= m88k_gp_threshold)		\
-		SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;	\
-	    }								\
-	}								\
-      else if (TREE_CODE (DECL) == STRING_CST				\
-	       && flag_writable_strings					\
-	       && TREE_STRING_LENGTH (DECL) <= m88k_gp_threshold)	\
-	SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1;		\
-  } while (0)
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-#define PRINT_OPERAND_PUNCT_VALID_P(c) \
-  ((c) == '#' || (c) == '.' || (c) == '!' || (c) == '*' || (c) == ';')
-
-#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
-
-/* Print a memory address as an operand to reference that memory location.  */
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
-
-/* This says not to strength reduce the addr calculations within loops
-   (otherwise it does not take advantage of m88k scaled loads and stores */
-
-#define DONT_REDUCE_ADDR
diff --git a/gcc/config/m88k/m88k.md b/gcc/config/m88k/m88k.md
deleted file mode 100755
index 118ebe3..0000000
--- a/gcc/config/m88k/m88k.md
+++ /dev/null
@@ -1,4023 +0,0 @@
-;;- Machine description for the Motorola 88000 for GNU C compiler
-;;;  Copyright (C) 1988, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
-;;  Contributed by Michael Tiemann (tiemann@mcc.com)
-;;  Currently maintained by (gcc@dg-rtp.dg.com)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; RCS rev field.  This is a NOP, just to get the RCS id into the
-;; program image.
-(define_expand "m88k_rcs_id"
-  [(match_operand:SI 0 "" "")]
-  ""
-  "{ static char rcs_id[] = \"$What: <@(#) m88k.md,v	1.1.1.2.2.2> $\";
-     FAIL; }")
-
-;; Attribute describing the processor.  This attribute must match exactly
-;; with the processor_type enumeration in m88k.h.
-
-; Target CPU.
-(define_attr "cpu" "m88100,m88110,m88000"
-  (const (symbol_ref "m88k_cpu")))
-
-; Type of each instruction.  Default is arithmetic.
-; I'd like to write the list as this, but genattrtab won't accept it.
-;
-; "branch,jump,call,			; flow-control instructions
-;  load,store,loadd,loada,		; data unit instructions
-;  spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv, ; FPU add instructions
-;  spmul,dpmul,imul,			; FPU multiply instructions
-;  arith,bit,mov			; integer unit instructions
-;  marith,weird"			; multi-word instructions
-
-; Classification of each insn.  Some insns of TYPE_BRANCH are multi-word.
-(define_attr "type"
-  "branch,jump,call,load,store,loadd,loada,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv,spmul,dpmul,imul,arith,bit,mov,marith,weird"
-  (const_string "arith"))
-
-(define_attr "fpu" "yes,no"
-  (if_then_else
-   (eq_attr "type" "spmul,dpmul,imul,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv")
-   (const_string "yes") (const_string "no")))
-
-; Length in # of instructions of each insn.  The values are not exact, but
-; are safe.
-(define_attr "length" ""
-  (cond [(eq_attr "type" "marith,weird,branch")
-	 (const_int 2)]
-	(const_int 1)))
-
-; Describe a user's asm statement.
-(define_asm_attributes
-  [(set_attr "type" "weird")])
-
-; Define the delay slot requirements for branches and calls.
-; The m88100 annuls instructions if a conditional branch is taken.
-; For insns of TYPE_BRANCH that are multi-word instructions, the
-; delay slot applies to the first instruction.
-
-; @@ For the moment, reorg.c requires that the delay slot of a branch not
-; be a call or branch.
-
-(define_delay (eq_attr "type" "branch,jump")
-  [(and
-    (and
-     (eq_attr "type" "!branch,jump,call,marith,weird") ; required.
-     (eq_attr "type" "!load,loadd")) ; issue as-soon-as-possible.
-    (eq_attr "fpu" "no")) ; issue as-soon-as-possible.
-   (eq_attr "type" "!call,branch,jump") (nil)]) ; @@ was (const_int 1)
-
-; output_call supports an unconditional branch in the delay slot of
-; a call.  (@@ Support for this case is expected in reorg.c soon.)
-
-(define_delay (eq_attr "type" "call")
-  [(eq_attr "type" "!branch,call,marith,weird") ; required.
-   (nil) (nil)])
-
-; An abstract block diagram of the function units for the m88100.
-;
-;			    *
-;			    |
-;			+---v----+
-;			| decode |
-;			+-vv-v-v-+	 fpu
-;	       ,----------'| | `----------------------.
-;	       |	   | |			      |	,-----.
-;	  load |     store | | arith		      |	|     |
-;	       |	   | |			    +-v-v-+   |	dp source
-;	       |	   | |			    | fp1 |---'
-;     store    |	   | |	    div		    +-v-v-+
-;   ,------.   |	   | |	  ,-----. ,-----------'	`-----------.
-;   |	   |   |	   | |	  |	| |			    |
-;   |	+--v---v--+    ,---' |	  |   +-v-v---+			+---v---+
-;   |	| stage	2 |    |     |	  `---|	add 2 |			| mul 2	|
-;   |	+---------+    |  +--v--+     +-------+		  imul	+-------+
-;   |	| stage	1 |    |  | alu	|     |	add 3 |	       ,--------| mul 3	|
-;   |	+---------+    |  +--v--+     +-------+	       |	+-------+
-;   |	| stage	0 |    |     |	      |	add 4 |	       |	| mul 4	|
-;   |	+--v---v--+    |     |	      +---v---+	       |	+-------+
-;   |	   |   |       |     |		  |	       |	| mul 5	|
-;   |	   *   |       |     |		  |	       |	+---v---+
-;   |	       |       |     |		  |	  +----v----+	    |
-;   |	  load |       |     |	   fp add `------>| fp last |<------' fp mul
-;   |	       |       |     |			  +---v-v--^+
-;   |	       |       |     |			      |	|  |
-;   |	       |       |     |			      |	`--' dp	dest
-;   |	       |    +--v-----v--+		      |
-;   |	       `--->| writeback	|<--------------------'
-;   |		    +--v-----v--+
-;   |		       |     |
-;   `------------------'     *
-;
-; The decode unit need not be specified.
-; Consideration of writeback contention is critical to superb scheduling.
-;
-; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
-;			TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
-
-; Describing the '100 alu is currently not useful.
-;(define_function_unit "alu" 1 0 (eq_attr "type"
-;					 "!store,marith,weird") 1 0)
-;(define_function_unit "alu" 1 0 (eq_attr "type" "marith,weird") 2 0)
-
-(define_function_unit "alu" 1 0
-  (and (eq_attr "type" "loada,arith,mov") (eq_attr "cpu" "!m88100")) 2 0)
-(define_function_unit "alu" 1 0
-  (and (eq_attr "type" "marith,weird") (eq_attr "cpu" "!m88100")) 4 0)
-
-(define_function_unit "bit" 1 0
-  (and (eq_attr "type" "bit") (eq_attr "cpu" "!m88100")) 2 2)
-
-(define_function_unit "mem100" 1 0
-  (and (eq_attr "type" "store,loada") (eq_attr "cpu" "m88100")) 1 0)
-(define_function_unit "mem100" 1 0
-  (and (eq_attr "type" "load") (eq_attr "cpu" "m88100")) 3 0)
-(define_function_unit "mem100" 1 0
-  (and (eq_attr "type" "loadd") (eq_attr "cpu" "m88100")) 3 2)
-
-(define_function_unit "mem110" 1 0
-  (and (eq_attr "type" "load,loadd") (eq_attr "cpu" "!m88100")) 3 2)
-(define_function_unit "mem110" 1 0
-  (and (eq_attr "type" "store") (eq_attr "cpu" "!m88100")) 1 2)
-
-; The times are adjusted to include fp1 and fplast, but then are further
-; adjusted based on the actual generated code.  The notation to the right
-; is the total latency.  A range denotes a group of instructions and/or
-; conditions (the extra clock of fplast time with some sequences).
-
-(define_function_unit "fpmul100" 1 0
-  (and (eq_attr "type" "spmul") (eq_attr "cpu" "m88100")) 4 0)		; 6-8
-(define_function_unit "fpmul100" 1 0
-  (and (eq_attr "type" "dpmul") (eq_attr "cpu" "m88100")) 7 0)		; 9-10
-(define_function_unit "fpmul100" 1 0
-  (and (eq_attr "type" "imul") (eq_attr "cpu" "m88100")) 3 0)		; 4
-
-(define_function_unit "fpmul110" 1 0
-  (and (eq_attr "type" "imul,spmul,dpmul")
-       (eq_attr "cpu" "!m88100")) 5 2)					; 3
-
-(define_function_unit "fpadd100" 1 5
-  (and (eq_attr "type" "spadd,spcmp") (eq_attr "cpu" "m88100")) 3 0)	; 5-6
-(define_function_unit "fpadd100" 1 5
-  (and (eq_attr "type" "dpadd,dpcmp") (eq_attr "cpu" "m88100")) 4 0)	; 6-7
-
-(define_function_unit "fpadd110" 1 0
-  (and (eq_attr "type" "spadd,dpadd") (eq_attr "cpu" "!m88100")) 5 2)	; 3
-(define_function_unit "fpadd110" 1 0
-  (and (eq_attr "type" "spcmp,dpcmp") (eq_attr "cpu" "!m88100")) 2 2)	; 1
-
-(define_function_unit "fpadd100" 1 5
-  (and (eq_attr "type" "spdiv") (eq_attr "cpu" "m88100")) 30 0)		; 30-31
-(define_function_unit "fpadd100" 1 5
-  (and (eq_attr "type" "dpdiv") (eq_attr "cpu" "m88100")) 60 0)		; 60-61
-(define_function_unit "fpadd100" 1 5
-  (and (eq_attr "type" "idiv") (eq_attr "cpu" "m88100")) 38 0)		; 38
-
-(define_function_unit "div" 1 1
-  (and (eq_attr "type" "spdiv") (eq_attr "cpu" "!m88100")) 25 2)	; 13
-(define_function_unit "div" 1 1
-  (and (eq_attr "type" "dpdiv") (eq_attr "cpu" "!m88100")) 45 2)	; 23
-(define_function_unit "div" 1 1
-  (and (eq_attr "type" "idiv") (eq_attr "cpu" "!m88100")) 35 2)		; 18
-
-;; Superoptimizer sequences
-
-;; geu+: { r = ((unsigned_word) v0 >= (unsigned_word) v1) + v2; }
-;;      subu.co r5,r2,r3
-;;      addu.cio r6,r4,r0
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (geu:SI (match_operand:SI 2 "register_operand" "r")
-			  (match_operand:SI 3 "register_operand" "r"))))]
-  ""
-  [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1))
-   (set (match_dup 0)
-	(plus:SI (match_dup 1)
-		 (unspec:SI [(const_int 0)
-			     (reg:CC 0)] 0)))]
-  "")
-
-;; leu+: { r = ((unsigned_word) v0 <= (unsigned_word) v1) + v2; }
-;;      subu.co r5,r3,r2
-;;      addu.cio r6,r4,r0
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (leu:SI (match_operand:SI 3 "register_operand" "r")
-			  (match_operand:SI 2 "register_operand" "r"))))]
-  ""
-  [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1))
-   (set (match_dup 0)
-	(plus:SI (match_dup 1)
-		 (unspec:SI [(const_int 0)
-			     (reg:CC 0)] 0)))]
-  "")
-
-;; eq0+: { r = (v0 == 0) + v1; }
-;;      subu.co r4,r0,r2
-;;      addu.cio r5,r3,r0
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (eq:SI (match_operand:SI 2 "register_operand" "r")
-			 (const_int 0))))]
-  ""
-  [(set (reg:CC 0) (unspec:CC [(const_int 0) (match_dup 2)] 1))
-   (set (match_dup 0)
-	(plus:SI (match_dup 1)
-		 (unspec:SI [(const_int 0)
-			     (reg:CC 0)] 0)))]
-  "")
-
-;; ltu-:  { r = v2 - ((unsigned_word) v0 < (unsigned_word) v1); }
-;;      subu.co r5,r2,r3
-;;      subu.cio r6,r4,r0
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (ltu:SI (match_operand:SI 2 "register_operand" "r")
-			 (match_operand:SI 3 "register_operand" "r"))
-		 (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1))
-   (set (match_dup 0)
-	(minus:SI (match_dup 1)
-		  (unspec:SI [(const_int 0)
-			      (reg:CC 0)] 1)))]
-  "")
-
-;; gtu-: { r = v2 - ((unsigned_word) v0 > (unsigned_word) v1); }
-;;      subu.co r5,r3,r2
-;;      subu.cio r6,r4,r0
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (gtu:SI (match_operand:SI 3 "register_operand" "r")
-			 (match_operand:SI 2 "register_operand" "r"))
-		 (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1))
-   (set (match_dup 0)
-	(minus:SI (match_dup 1)
-		 (unspec:SI [(const_int 0)
-			     (reg:CC 0)] 1)))]
-  "")
-
-;; ne0-: { r = v1 - (v0 != 0); }
-;;      subu.co r4,r0,r2
-;;      subu.cio r5,r3,r0
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (ne:SI (match_operand:SI 2 "register_operand" "r")
-			(const_int 0))
-		 (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  [(set (reg:CC 0) (unspec:CC [(const_int 0) (match_dup 2)] 1))
-   (set (match_dup 0)
-	(minus:SI (match_dup 1)
-		  (unspec:SI [(const_int 0)
-			      (reg:CC 0)] 1)))]
-  "")
-
-;; ges0-: { r = v1 - ((signed_word) v0 >= 0); }
-;;	addu.co	r4,r2,r2
-;;	subu.cio r5,r3,r0
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (xor:SI (lshiftrt:SI
-			   (match_operand:SI 2 "register_operand" "r")
-			   (const_int 31))
-			  (const_int 1))))]
-  ""
-  [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 2)] 0))
-   (set (match_dup 0)
-	(minus:SI (match_dup 1)
-		  (unspec:SI [(const_int 0)
-			      (reg:CC 0)] 1)))]
-  "")
-
-;; This rich set of complex patterns are mostly due to Torbjorn Granlund
-;; (tege@sics.se).  They've changed since then, so don't complain to him
-;; if they don't work right.
-
-;; Regarding shifts, gen_lshlsi3 generates ASHIFT.  The gen functions
-;; produce the necessary insns to support TARGET_*_LARGE_SHIFT, so nothing
-;; special needs to be done here.
-
-;; Optimize possible cases of the set instruction.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (ashift:SI (const_int -1)
-       	    (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "set %0,%#r0,%1"
-  [(set_attr "type" "bit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (ior:SI (ashift:SI (const_int -1)
-       		    (match_operand:SI 1 "register_operand" "r"))
-       	 (match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "set %0,%2,%1"
-  [(set_attr "type" "bit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (ior:SI (match_operand:SI 1 "register_operand" "r")
-       	 (ashift:SI (const_int -1)
-       		    (match_operand:SI 2 "register_operand" "r"))))]
-  ""
-  "set %0,%1,%2"
-  [(set_attr "type" "bit")])
-
-;; Optimize possible cases of the mak instruction.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-			   (match_operand:SI 2 "int5_operand" ""))
-		(match_operand:SI 3 "immediate_operand" "n")))]
-  "mak_mask_p (INTVAL (operands[3]) >> INTVAL (operands[2]))"
-  "*
-{
-  operands[4] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3])
-					  >> INTVAL(operands[2]))));
-  return \"mak %0,%1,%4<%2>\";
-}"
-  [(set_attr "type" "bit")])
-
-;; Optimize possible cases of output_and.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-				    (match_operand:SI 2 "int5_operand" "")
-				    (match_operand:SI 3 "int5_operand" ""))
-		   (match_operand:SI 4 "int5_operand" "")))]
-  "INTVAL (operands[2]) + INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
-  "*
-{
-  operands[2]
-    = GEN_INT (((1 << INTVAL (operands[2])) - 1) << INTVAL (operands[4]));
-  return output_and (operands);
-}"
-  [(set_attr "type" "marith")]) ; arith,bit,marith.  length is 1 or 2.
-
-;; Improve logical operations on compare words
-;;
-;; We define all logical operations on CCmode values to preserve the pairwise
-;; relationship of the compare bits.  This allows a future branch prediction
-;; pass the degree of freedom needed to change and/bb0-le into or/bb1-gt.
-;; THIS IS CURRENTLY FALSE! 
-;;
-;; Opportunities arise when conditional expressions using && and || are made
-;; unconditional.  When these are used to branch, the sequence is
-;; cmp/cmp/extu/extu/{and,or}/bcnd-{eq0,ne0}.  When these are used to create
-;; a value, the sequence is cmp/cmp/extu/extu/{and,or} for 1 or 0 or
-;; cmp/cmp/ext/ext/{and,or} for -1 or 0.
-;;
-;; When the extracted conditions are the same, the define_split patterns
-;; below change extu/extu/{and,or} into {and,or}/extu.  If the reversed
-;; conditions match, one compare word can be complimented, resulting in
-;; {and.c,or.c}/extu.  These changes are done for ext/ext/{and,or} as well.
-;; If the conditions don't line up, one can be rotated.  To keep the pairwise
-;; relationship, it may be necessary to both rotate and compliment.  Rotating
-;; makes branching cheaper, but doesn't help (or hurt) creating a value, so
-;; we don't do this for ext/ext/{and,or}.
-;;
-;; These changes result in the sequence extu/bcnd-{eq0,ne0} which is combined
-;; into an alternate form of bb0 and bb1.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (neg:SI 
-		 (match_operator 1 "even_relop"
-				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
-				  (const_int 0)]))
-		(neg:SI
-		 (match_operator 3 "relop"
-				 [(match_operand 4 "partial_ccmode_register_operand" "r")
-				  (const_int 0)]))))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  ""
-  [(set (match_dup 5)
-	(ior:CCEVEN (match_dup 4)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
-  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
-   if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
-     ; /* The conditions match.  */
-   else if (GET_CODE (operands[1])
-	    == reverse_condition (GET_CODE (operands[3])))
-     /* Reverse the condition by complimenting the compare word.  */
-     operands[4] = gen_rtx (NOT, CCmode, operands[4]);
-   else
-     {
-       /* Make the condition pairs line up by rotating the compare word.  */
-       int cv1 = condition_value (operands[1]);
-       int cv2 = condition_value (operands[3]);
-
-       operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
-			      GEN_INT (((cv2 & ~1) - (cv1 & ~1)) & 0x1f));
-       /* Reverse the condition if needed.  */
-       if ((cv1 & 1) != (cv2 & 1))
-	 operands[4] = gen_rtx (NOT, CCmode, operands[4]);
-     }")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (neg:SI 
-		 (match_operator 1 "odd_relop"
-				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
-				  (const_int 0)]))
-		(neg:SI
-		 (match_operator 3 "odd_relop"
-				 [(match_operand 4 "partial_ccmode_register_operand" "r")
-				  (const_int 0)]))))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  ""
-  [(set (match_dup 5)
-	(and:CCEVEN (match_dup 4)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
-  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
-   if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
-     ; /* The conditions match.  */
-   else
-     {
-       /* Make the condition pairs line up by rotating the compare word.  */
-       int cv1 = condition_value (operands[1]);
-       int cv2 = condition_value (operands[3]);
-
-       operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
-			      GEN_INT ((cv2 - cv1) & 0x1f));
-     }")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (neg:SI 
-		 (match_operator 1 "odd_relop"
-				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
-				  (const_int 0)]))
-		(neg:SI
-		 (match_operator 3 "even_relop"
-				 [(match_operand 4 "partial_ccmode_register_operand" "r")
-				  (const_int 0)]))))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  ""
-  [(set (match_dup 5)
-	(ior:CCEVEN (not:CC (match_dup 2))
-		(match_dup 4)))
-   (set (match_dup 0)
-	(neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))]
-  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
-  if (GET_CODE (operands[1])
-	    == reverse_condition (GET_CODE (operands[3])))
-     ; 
-   else
-     {
-       /* Make the condition pairs line up by rotating the compare word.  */
-       int cv1 = condition_value (operands[1]);
-       int cv2 = condition_value (operands[3]);
-
-       operands[2] = gen_rtx (ROTATE, CCmode, operands[2],
-			      GEN_INT (((cv1 & ~1) - (cv2 & ~1)) & 0x1f));
-     }")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (match_operator 1 "even_relop"
-				[(match_operand 2 "partial_ccmode_register_operand" "%r")
-				 (const_int 0)])
-		(match_operator 3 "relop"
-				[(match_operand 4 "partial_ccmode_register_operand" "r")
-				 (const_int 0)])))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  "GET_CODE (operands[1]) == GET_CODE (operands[3])
-   || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
-  [(set (match_dup 5)
-	(ior:CCEVEN (match_dup 4)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
-  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
-   /* Reverse the condition by  complimenting the compare word.  */
-   if (GET_CODE (operands[1]) != GET_CODE (operands[3]))
-      operands[4] = gen_rtx (NOT, CCmode, operands[4]);")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (match_operator 1 "odd_relop"
-				[(match_operand 2 "partial_ccmode_register_operand" "%r")
-				 (const_int 0)])
-		(match_operator 3 "odd_relop"
-				[(match_operand 4 "partial_ccmode_register_operand" "r")
-				 (const_int 0)])))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  "GET_CODE (operands[1]) == GET_CODE (operands[3])"
-  [(set (match_dup 5)
-	(and:CCEVEN (match_dup 4)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
-  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (match_operator 1 "odd_relop"
-				[(match_operand 2 "partial_ccmode_register_operand" "%r")
-				 (const_int 0)])
-		(match_operator 3 "even_relop"
-				[(match_operand 4 "partial_ccmode_register_operand" "r")
-				 (const_int 0)])))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
-  [(set (match_dup 5)
-	(ior:CCEVEN (not:CC (match_dup 4))
-		(match_dup 2)))
-   (set (match_dup 0)
-	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
-  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (neg:SI 
-		 (match_operator 1 "even_relop"
-				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
-				  (const_int 0)]))
-		(neg:SI
-		 (match_operator 3 "relop"
-				 [(match_operand 4 "partial_ccmode_register_operand" "r")
-				  (const_int 0)]))))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  ""
-  [(set (match_dup 5)
-	(and:CCEVEN (match_dup 4)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
-  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
-   if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
-     ; /* The conditions match.  */
-   else if (GET_CODE (operands[1])
-	    == reverse_condition (GET_CODE (operands[3])))
-     /* Reverse the condition by complimenting the compare word.  */
-     operands[4] = gen_rtx (NOT, CCmode, operands[4]);
-   else
-     {
-       /* Make the condition pairs line up by rotating the compare word.  */
-       int cv1 = condition_value (operands[1]);
-       int cv2 = condition_value (operands[3]);
-       operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
-			      GEN_INT (((cv2 & ~1) - (cv1 & ~1)) & 0x1f));
-       /* Reverse the condition if needed.  */
-       if ((cv1 & 1) != (cv2 & 1))
-	 operands[4] = gen_rtx (NOT, CCmode, operands[4]);
-     }")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (neg:SI 
-		 (match_operator 1 "odd_relop"
-				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
-				  (const_int 0)]))
-		(neg:SI
-		 (match_operator 3 "odd_relop"
-				 [(match_operand 4 "partial_ccmode_register_operand" "r")
-				  (const_int 0)]))))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  ""
-  [(set (match_dup 5)
-	(ior:CCEVEN (match_dup 4)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
-  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
-   if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
-     ; /* The conditions match.  */
-   else
-     {
-       /* Make the condition pairs line up by rotating the compare word.  */
-       int cv1 = condition_value (operands[1]);
-       int cv2 = condition_value (operands[3]);
-       operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
-			      GEN_INT ((cv2 - cv1) & 0x1f));
-     }")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (neg:SI 
-		 (match_operator 1 "odd_relop"
-				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
-				  (const_int 0)]))
-		(neg:SI
-		 (match_operator 3 "even_relop"
-				 [(match_operand 4 "partial_ccmode_register_operand" "r")
-				  (const_int 0)]))))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  ""
-  [(set (match_dup 5)
-	(and:CCEVEN (not:CC (match_dup 2))
-		(match_dup 4)))
-   (set (match_dup 0)
-	(neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))]
-  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
-   if (GET_CODE (operands[1])
-	    == reverse_condition (GET_CODE (operands[3])))
-	;
-   else
-     {
-       /* Make the condition pairs line up by rotating the compare word.  */
-       int cv1 = condition_value (operands[1]);
-       int cv2 = condition_value (operands[3]);
-       operands[2] = gen_rtx (ROTATE, CCmode, operands[2],
-			      GEN_INT (((cv1 & ~1) - (cv2 & ~1)) & 0x1f));
-     }")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (match_operator 1 "even_relop"
-				[(match_operand 2 "partial_ccmode_register_operand" "%r")
-				 (const_int 0)])
-		(match_operator 3 "relop"
-				[(match_operand 4 "partial_ccmode_register_operand" "r")
-				 (const_int 0)])))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  "GET_CODE (operands[1]) == GET_CODE (operands[3])
-   || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
-  [(set (match_dup 5)
-	(and:CCEVEN (match_dup 4)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
-  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
-   /* Reverse the condition by  complimenting the compare word.  */
-   if (GET_CODE (operands[1]) != GET_CODE (operands[3]))
-      operands[4] = gen_rtx (NOT, CCmode, operands[4]);")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (match_operator 1 "odd_relop"
-				[(match_operand 2 "partial_ccmode_register_operand" "%r")
-				 (const_int 0)])
-		(match_operator 3 "odd_relop"
-				[(match_operand 4 "partial_ccmode_register_operand" "r")
-				 (const_int 0)])))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  "GET_CODE (operands[1]) == GET_CODE (operands[3])"
-  [(set (match_dup 5)
-	(ior:CCEVEN (match_dup 4)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
-  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (match_operator 1 "odd_relop"
-				[(match_operand 2 "partial_ccmode_register_operand" "%r")
-				 (const_int 0)])
-		(match_operator 3 "even_relop"
-				[(match_operand 4 "partial_ccmode_register_operand" "r")
-				 (const_int 0)])))
-   (clobber (match_operand:SI 5 "register_operand" "=r"))]
-  "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
-  [(set (match_dup 5)
-	(and:CCEVEN (not:CC (match_dup 2))
-		(match_dup 4)))
-   (set (match_dup 0)
-	(match_op_dup 3 [(match_dup 5) (const_int 0)]))]
-  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
-
-
-;; Logical operations on compare words.
-
-(define_insn ""
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(and:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r"))
-		(match_operand 2 "partial_ccmode_register_operand" "r")))]
-  ""
-  "and.c %0,%2,%1")
-
-(define_insn ""
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(and:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r")
-		(match_operand 2 "partial_ccmode_register_operand" "r")))]
-  ""
-  "and %0,%1,%2")
-
-(define_insn ""
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(ior:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r"))
-		(match_operand 2 "partial_ccmode_register_operand" "r")))]
-  ""
-  "or.c %0,%2,%1")
-
-(define_insn ""
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(ior:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r")
-		(match_operand 2 "partial_ccmode_register_operand" "r")))]
-  ""
-  "or %0,%1,%2")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(rotate:CC (match_operand:CC 1 "register_operand" "r")
-		   (match_operand:CC 2 "int5_operand" "")))]
-  ""
-  "rot %0,%1,%2"
-  [(set_attr "type" "bit")])
-
-(define_insn ""
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
-		   (match_operand:CC 2 "int5_operand" "")))]
-  ""
-  "rot %0,%1,%2"
-  [(set_attr "type" "bit")])
-
-;; rotate/and[.c] and rotate/ior[.c]
-
-(define_split
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(ior:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
-			   (match_operand:CC 2 "int5_operand" ""))
-		(match_operand 3 "partial_ccmode_register_operand" "r")))
-   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
-  ""
-  [(set (match_dup 4)
-	(rotate:CC (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(ior:CCEVEN (match_dup 4) (match_dup 3)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(ior:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
-			   (match_operand:CC 2 "int5_operand" ""))
-		(match_operand 3 "partial_ccmode_register_operand" "r")))
-   (clobber (match_scratch:CCEVEN 4 "=r"))]
-  ""
-  "#")
-
-(define_split
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
-				   (match_operand:CC 2 "int5_operand" "")))
-		(match_operand 3 "partial_ccmode_register_operand" "r")))
-   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
-  ""
-  [(set (match_dup 4)
-	(rotate:CC (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(ior:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
-				   (match_operand:CC 2 "int5_operand" "")))
-		(match_operand 3 "partial_ccmode_register_operand" "r")))
-   (clobber (match_scratch:CCEVEN 4 "=r"))]
-  ""
-  "#")
-
-(define_split
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
-			   (match_operand:CC 2 "int5_operand" ""))
-		(match_operand 3 "partial_ccmode_register_operand" "r")))
-   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
-  ""
-  [(set (match_dup 4)
-	(rotate:CC (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(and:CCEVEN (match_dup 4) (match_dup 3)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
-			   (match_operand:CC 2 "int5_operand" ""))
-		(match_operand 3 "partial_ccmode_register_operand" "r")))
-   (clobber (match_scratch:CCEVEN 4 "=r"))]
-  ""
-  "#")
-
-(define_split
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
-				   (match_operand:CC 2 "int5_operand" "")))
-		(match_operand 3 "partial_ccmode_register_operand" "r")))
-   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
-  ""
-  [(set (match_dup 4)
-	(rotate:CC (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(and:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
-	(and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
-				   (match_operand:CC 2 "int5_operand" "")))
-		(match_operand 3 "partial_ccmode_register_operand" "r")))
-   (clobber (match_scratch:CCEVEN 4 "=r"))]
-  ""
-  "#")
-
-
-;; Recognize bcnd instructions for integer values.  This is distinguished
-;; from a conditional branch instruction (below) with SImode instead of
-;; CCmode.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "relop_no_unsigned"
-			 [(match_operand:SI 1 "register_operand" "r")
-			  (const_int 0)])
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bcnd%. %R3%B0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-;; Recognize tests for sign and zero.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "equality_op"
-			 [(match_operand:SI 1 "register_operand" "r")
-			  (const_int -2147483648)])
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bcnd%. %R3%E0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "equality_op"
-			 [(zero_extract:SI
-			   (match_operand:SI 1 "register_operand" "r")
-			   (const_int 31)
-			   (const_int 1))
-			  (const_int 0)])
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bcnd%. %R3%D0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-;; Recognize bcnd instructions for double integer values
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "relop_no_unsigned"
-			 [(sign_extend:DI
-			   (match_operand:SI 1 "register_operand" "r"))
-			  (const_int 0)])
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bcnd%. %R3%B0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "equality_op"
-			 [(zero_extend:DI
-			   (match_operand:SI 1 "register_operand" "r"))
-			  (const_int 0)])
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bcnd%. %R3%B0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-; @@ I doubt this is interesting until cmpdi is provided.  Anyway, it needs
-; to be reworked.
-;
-;(define_insn ""
-;  [(set (pc)
-;	(if_then_else
-;	 (match_operator 0 "relop_no_unsigned"
-;			 [(match_operand:DI 1 "register_operand" "r")
-;			  (const_int 0)])
-;	 (match_operand 2 "pc_or_label_ref" "")
-;	 (match_operand 3 "pc_or_label_ref" "")))]
-;  ""
-;  "*
-;{
-;  switch (GET_CODE (operands[0]))
-;    {
-;    case EQ:
-;    case NE:
-;      /* I'm not sure if it's safe to use .n here.  */
-;      return \"or %!,%1,%d1\;bcnd %R3%B0,%!,%P2%P3\";
-;    case GE:
-;    case LT:
-;      return \"bcnd%. %R3%B0,%1,%P2%P3\";
-;    case GT:
-;      {
-;	rtx op2 = operands[2];
-;	operands[2] = operands[3];
-;	operands[3] = op2;
-;      }
-;    case LE:
-;      if (GET_CODE (operands[3]) == LABEL_REF)
-;	{
-;	  int label_num;
-;	  operands[2] = gen_label_rtx ();
-;	  label_num = XINT (operands[2], 3);
-;	  output_asm_insn
-;	    (\"bcnd%. %#lt0,%1,%2\;or %!,%1,%d1\;bcnd %#ne0,%!,%3\", operands);
-;	  output_label (label_num);
-;	  return \"\";
-;	}
-;      else
-;	return \"bcnd%. %#lt0,%1,%2\;or %!,%1,%d1\;bcnd %#eq0,%!,%2\";
-;    }
-;}")
-
-;; Recognize bcnd instructions for single precision float values
-;; Exclude relational operations as they must signal NaNs.
-
-;; @@ These bcnd insns for float and double values don't seem to be recognized.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "equality_op"
-			 [(float_extend:DF
-			   (match_operand:SF 1 "register_operand" "r"))
-			  (const_int 0)])
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bcnd%. %R3%D0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "equality_op"
-			 [(match_operand:SF 1 "register_operand" "r")
-			  (const_int 0)])
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bcnd%. %R3%D0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-;; Recognize bcnd instructions for double precision float values
-;; Exclude relational operations as they must signal NaNs.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "equality_op"
-			 [(match_operand:DF 1 "register_operand" "r")
-			  (const_int 0)])
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "*
-{
-  int label_num;
-
-  if (GET_CODE (operands[0]) == NE)
-    {
-      rtx op2 = operands[2];
-      operands[2] = operands[3];
-      operands[3] = op2;
-    }
-  if (GET_CODE (operands[3]) == LABEL_REF)
-    return \"bcnd 0x5,%1,%3\;bcnd %#ne0,%d1,%3\";
-
-  operands[3] = gen_label_rtx ();
-  label_num = XINT (operands[3], 3);
-  output_asm_insn (\"bcnd 0x5,%1,%3\;bcnd %#eq0,%d1,%2\", operands);
-  output_label (label_num);
-  return \"\";
-}"
-  [(set_attr "type" "weird")
-   (set_attr "length" "3")])
-
-;; Recognize bb0 and bb1 instructions.  These use two unusual template
-;; patterns, %Lx and %Px.  %Lx outputs a 1 if operand `x' is a LABEL_REF
-;; otherwise it outputs a 0.  It then may print ".n" if the delay slot
-;; is used.  %Px does noting if `x' is PC and outputs the operand if `x'
-;; is a LABEL_REF.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
-			      (const_int 1)
-			      (match_operand:SI 1 "int5_operand" ""))
-	     (const_int 0))
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bb%L2 (31-%1),%0,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
-			      (const_int 1)
-			      (match_operand:SI 1 "int5_operand" ""))
-	     (const_int 0))
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bb%L3 (31-%1),%0,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
-			      (const_int 1)
-			      (match_operand:SI 1 "int5_operand" ""))
-	     (const_int 0))
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bb%L2 (31-%1),%0,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
-			      (const_int 1)
-			      (match_operand:SI 1 "int5_operand" ""))
-	     (const_int 0))
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bb%L3 (31-%1),%0,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (and:SI (match_operand:SI 0 "reg_or_bbx_mask_operand" "%r")
-		     (match_operand:SI 1 "reg_or_bbx_mask_operand" "n"))
-	      (const_int 0))
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  "(GET_CODE (operands[0]) == CONST_INT)
-   != (GET_CODE (operands[1]) == CONST_INT)"
-  "bb%L3 %p1,%0,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (and:SI (match_operand:SI 0 "reg_or_bbx_mask_operand" "%r")
-		     (match_operand:SI 1 "reg_or_bbx_mask_operand" "n"))
-	     (const_int 0))
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  "(GET_CODE (operands[0]) == CONST_INT)
-   != (GET_CODE (operands[1]) == CONST_INT)"
-  "bb%L2 %p1,%0,%P2%P3"
-  [(set_attr "type" "branch")])
-
-;; The comparison operations store the comparison into a register and
-;; record that register.  The following Bxx or Sxx insn uses that
-;; register as an input.  To facilitate use of bcnd instead of cmp/bb1,
-;; cmpsi records its operands and produces no code when any operand
-;; is constant.  In this case, the Bxx insns use gen_bcnd and the
-;; Sxx insns use gen_test to ensure a cmp has been emitted.
-;;
-;; This could also be done for SFmode and DFmode having only beq and bne
-;; use gen_bcnd.  The others must signal NaNs.  It seems though that zero
-;; has already been copied into a register.
-;;
-;; cmpsi/beq and cmpsi/bne can always be done with bcnd if any operand
-;; is a constant.  (This idea is due to Torbjorn Granlund.)  Others can
-;; use bcnd only if an operand is zero.
-;;
-;; It is necessary to distinguish a register holding condition codes.
-;; This is done by context.
-
-(define_expand "test"
-  [(set (match_dup 2)
-	(compare:CC (match_operand 0 "" "")
-		    (match_operand 1 "" "")))]
-  ""
-  "
-{
-  if (m88k_compare_reg)
-    abort ();
-
-  if (GET_CODE (operands[0]) == CONST_INT
-      && ! SMALL_INT (operands[0]))
-    operands[0] = force_reg (SImode, operands[0]);
-
-  if (GET_CODE (operands[1]) == CONST_INT
-      && ! SMALL_INT (operands[1]))
-    operands[1] = force_reg (SImode, operands[1]);
-
-  operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode);
-}")
-
-; @@ The docs say don't do this.  It's probably a nop since the insn looks
-; identical to cmpsi against zero.  Is there an advantage to providing
-; this, perhaps with a different form?
-
-;(define_expand "tstsi"
-;  [(set (match_dup 1)
-;	(compare:CC (match_operand:SI 0 "register_operand" "")
-;		    (const_int 0)))]
-; ""
-; "
-;{
-;  m88k_compare_reg = 0;
-;  m88k_compare_op0 = operands[0];
-;  m88k_compare_op1 = const0_rtx;
-;  DONE;
-;}")
-
-(define_expand "cmpsi"
-  [(set (match_dup 2)
-	(compare:CC (match_operand:SI 0 "register_operand" "")
-		    (match_operand:SI 1 "arith32_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == CONST_INT
-      || GET_CODE (operands[1]) == CONST_INT)
-    {
-      m88k_compare_reg = 0;
-      m88k_compare_op0 = operands[0];
-      m88k_compare_op1 = operands[1];
-      DONE;
-    }
-  operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode);
-}")
-
-(define_expand "cmpsf"
-  [(set (match_dup 2)
-	(compare:CC (match_operand:SF 0 "register_operand" "")
-		    (match_operand:SF 1 "register_operand" "")))]
-  ""
-  "operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode);")
-
-(define_expand "cmpdf"
-  [(set (match_dup 2)
-	(compare:CC (match_operand:DF 0 "general_operand" "")
-		    (match_operand:DF 1 "general_operand" "")))]
-  ""
-  "
-{
-  operands[0] = legitimize_operand (operands[0], DFmode);
-  operands[1] = legitimize_operand (operands[1], DFmode);
-  operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode);
-}")
-
-; @@ Get back to this later on.
-;
-;(define_insn "cmpdi"
-;  [(set (cc0)
-;	(compare:CC (match_operand:DI 0 "register_operand" "r")
-;		    (match_operand:DI 1 "register_operand" "r")))]
-;  ""
-;  "*
-;{
-;  if ((cc_status.mdep & MDEP_LS_CHANGE) != 0)
-;    abort ();	/* output_move_double MDEP_LS_CHANGE bits were set. */
-;
-;  cc_status.mdep &= ~ MDEP_LS_MASK;
-;
-;  operands[2] = gen_label_rtx ();
-;  /* Remember, %! is the condition code register and %@ is the
-;     literal synthesis register.  */
-;
-;  output_asm_insn (\"cmp %!,%0,%1\;bb0 %#eq,%!,%l2\;cmp %!,%d0,%d1\",
-;		   operands);
-;
-;  output_asm_insn (\"extu %@,%!,4<8>\;clr %!,%!,4<4>\", operands);
-;  output_asm_insn (\"mak %@,%@,4<4>\;or %!,%!,%@\", operands);
-;  output_label (XINT (operands[2], 3));
-;  return \"\";
-;}"
-
-;; The actual compare instructions.
-
-(define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(compare:CC (match_operand:SI 1 "register_operand" "rO")
-		    (match_operand:SI 2 "arith_operand" "rI")))]
-  ""
-  "cmp %0,%r1,%2")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r,r,r,r")
-	(compare:CC (match_operand:SF 1 "register_operand" "r,r,x,x")
-		    (match_operand:SF 2 "real_or_0_operand" "r,G,x,G")))]
-  ""
-  "@
-   fcmp.sss %0,%1,%2
-   fcmp.sss %0,%1,%#r0
-   fcmp.sss %0,%1,%2
-   fcmp.sss %0,%1,%#x0"
-  [(set_attr "type" "spcmp")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r,r")
-	(compare:CC (match_operand:DF 1 "register_operand" "r,x")
-		    (float_extend:DF
-		     (match_operand:SF 2 "register_operand" "r,x"))))]
-  ""
-  "fcmp.sds %0,%1,%2"
-  [(set_attr "type" "dpcmp")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r,r")
-	(compare:CC (float_extend:DF
-		     (match_operand:SF 1 "register_operand" "r,x"))
-		    (match_operand:DF 2 "register_operand" "r,x")))]
-  ""
-  "fcmp.ssd %0,%1,%2"
-  [(set_attr "type" "dpcmp")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r,r,r,r")
-	(compare:CC (match_operand:DF 1 "register_operand" "r,r,x,x")
-		    (match_operand:DF 2 "real_or_0_operand" "r,G,x,G")))]
-  ""
-  "@
-   fcmp.sdd %0,%1,%2
-   fcmp.sds %0,%1,%#r0
-   fcmp.sdd %0,%1,%2
-   fcmp.sds %0,%1,%#x0"
-  [(set_attr "type" "dpcmp")])
-
-;; Store condition code insns.  The compare insns set a register
-;; rather than cc0 and record that register for use here.  See above
-;; for the special treatment of cmpsi with a constant operand.
-
-;; @@ For the m88110, use fcmpu for bxx sxx inequality comparisons.
-
-(define_expand "seq"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = emit_test (EQ, SImode);")
-
-(define_expand "sne"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = emit_test (NE, SImode);")
-
-(define_expand "sgt"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = emit_test (GT, SImode);")
-
-(define_expand "sgtu"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = emit_test (GTU, SImode);")
-
-(define_expand "slt"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = emit_test (LT, SImode);")
-
-(define_expand "sltu"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = emit_test (LTU, SImode);")
-
-(define_expand "sge"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = emit_test (GE, SImode);")
-
-(define_expand "sgeu"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = emit_test (GEU, SImode);")
-
-(define_expand "sle"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = emit_test (LE, SImode);")
-
-(define_expand "sleu"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = emit_test (LEU, SImode);")
-
-;; The actual set condition code instruction.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operator:SI 1 "relop"
-			   [(match_operand:CC 2 "register_operand" "r")
-			    (const_int 0)]))]
-  ""
-  "ext %0,%2,1<%C1>"
-  [(set_attr "type" "bit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operator:SI 1 "even_relop"
-			   [(match_operand:CCEVEN 2 "register_operand" "r")
-			    (const_int 0)]))]
-  ""
-  "ext %0,%2,1<%C1>"
-  [(set_attr "type" "bit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operator:SI 1 "odd_relop"
-			   [(match_operand:CCEVEN 2 "register_operand" "r")
-			    (const_int 0)])))]
-  ""
-  "ext %0,%2,1<%!%C1>"
-  [(set_attr "type" "bit")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operator:SI 1 "odd_relop"
-			   [(match_operand:CCEVEN 2 "register_operand" "r")
-			    (const_int 0)]))
-   (clobber (match_operand:SI 3 "register_operand" "=r"))]
-  ""
-  [(set (match_dup 3) (not:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])))
-   (set (match_dup 0) (not:SI (match_dup 3)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operator:SI 1 "odd_relop"
-			   [(match_operand:CCEVEN 2 "register_operand" "r")
-			    (const_int 0)]))
-   (clobber (match_scratch:SI 3 "=r"))]
-  ""
-  "#")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI
-	 (match_operator:SI 1 "relop"
-			    [(match_operand:CC 2 "register_operand" "r")
-			     (const_int 0)])))]
-  ""
-  "extu %0,%2,1<%C1>"
-  [(set_attr "type" "bit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI
-	 (match_operator:SI 1 "even_relop"
-			    [(match_operand:CCEVEN 2 "register_operand" "r")
-			     (const_int 0)])))]
-  ""
-  "extu %0,%2,1<%C1>"
-  [(set_attr "type" "bit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI
-	 (not:SI (match_operator:SI 1 "odd_relop"
-			    [(match_operand:CCEVEN 2 "register_operand" "r")
-			     (const_int 0)]))))]
-  ""
-  "extu %0,%2,1<%!%C1>"
-  [(set_attr "type" "bit")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operator:SI 1 "odd_relop"
-			   [(match_operand:CCEVEN 2 "register_operand" "r")
-			    (const_int 0)])))
-   (clobber (match_operand:SI 3 "register_operand" "=r"))]
-  ""
-  [(set (match_dup 3) (neg:SI (not:SI (match_op_dup 1 [(match_dup 2)
-                                                       (const_int 0)]))))
-   (set (match_dup 0) (xor:SI (match_dup 3) (const_int 1)))]
-  "")
-
-(define_insn
- ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operator:SI 1 "odd_relop"
-			   [(match_operand:CCEVEN 2 "register_operand" "r")
-			    (const_int 0)])))
-   (clobber (match_scratch:SI 3 "=r"))]
-  ""
-  "#")
-
-
-
-
-;; Conditional branch insns.  The compare insns set a register
-;; rather than cc0 and record that register for use here.  See above
-;; for the special case of cmpsi with a constant operand.
-
-(define_expand "bcnd"
-  [(set (pc)
-	(if_then_else (match_operand 0 "" "")
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))]
-  ""
-  "if (m88k_compare_reg) abort ();")
-
-(define_expand "bxx"
-  [(set (pc)
-	(if_then_else (match_operand 0 "" "")
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))]
-  ""
-  "if (m88k_compare_reg == 0) abort ();")
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "if (m88k_compare_reg == 0)
-     {
-       emit_bcnd (EQ, operands[0]);
-       DONE;
-     }
-   operands[1] = m88k_compare_reg;")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "if (m88k_compare_reg == 0)
-     {
-       emit_bcnd (NE, operands[0]);
-       DONE;
-     }
-   operands[1] = m88k_compare_reg;")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "if (m88k_compare_reg == 0)
-     {
-       emit_bcnd (GT, operands[0]);
-       DONE;
-     }
-   operands[1] = m88k_compare_reg;")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "if (m88k_compare_reg == 0)
-     {
-       emit_jump_insn (gen_bxx (emit_test (GTU, VOIDmode), operands[0]));
-       DONE;
-     }
-   operands[1] = m88k_compare_reg;")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "if (m88k_compare_reg == 0)
-     {
-       emit_bcnd (LT, operands[0]);
-       DONE;
-     }
-   operands[1] = m88k_compare_reg;")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "if (m88k_compare_reg == 0)
-     {
-       emit_jump_insn (gen_bxx (emit_test (LTU, VOIDmode), operands[0]));
-       DONE;
-     }
-   operands[1] = m88k_compare_reg;")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "if (m88k_compare_reg == 0)
-     {
-       emit_bcnd (GE, operands[0]);
-       DONE;
-     }
-   operands[1] = m88k_compare_reg;")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "if (m88k_compare_reg == 0)
-     {
-       emit_jump_insn (gen_bxx (emit_test (GEU, VOIDmode), operands[0]));
-       DONE;
-     }
-   operands[1] = m88k_compare_reg;")
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "if (m88k_compare_reg == 0)
-     {
-       emit_bcnd (LE, operands[0]);
-       DONE;
-     }
-   operands[1] = m88k_compare_reg;")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "if (m88k_compare_reg == 0)
-     {
-       emit_jump_insn (gen_bxx (emit_test (LEU, VOIDmode), operands[0]));
-       DONE;
-     }
-   operands[1] = m88k_compare_reg;")
-
-;; The actual conditional branch instruction (both directions).  This
-;; uses two unusual template patterns, %Rx and %Px.  %Rx is a prefix code
-;; for the immediately following condition and reverses the condition iff
-;; operand `x' is a LABEL_REF.  %Px does nothing if `x' is PC and outputs
-;; the operand if `x' is a LABEL_REF.
-
-(define_insn ""
-  [(set (pc) (if_then_else
-	      (match_operator 0 "relop"
-			      [(match_operand:CC 1 "register_operand" "r")
-			       (const_int 0)])
-	      (match_operand 2 "pc_or_label_ref" "")
-	      (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "*
-{
-  if (mostly_false_jump (insn, operands[0]))
-    return \"bb0%. %R2%C0,%1,%P2%P3\";
-  else
-    return \"bb1%. %R3%C0,%1,%P2%P3\";
-}"
-  [(set_attr "type" "branch")])
-
-;;
-;; Here branch prediction is sacrificed. To get it back, you need 
-;;  - CCODD (CC mode where the ODD bits are valid)
-;;  - several define_split that can apply De Morgan's Law.
-;;  - transformations between CCEVEN and CCODD modes. 
-;;  
-
-(define_insn ""
-  [(set (pc) (if_then_else
-	      (match_operator 0 "even_relop"
-			      [(match_operand:CCEVEN 1 "register_operand" "r")
-			       (const_int 0)])
-	      (match_operand 2 "pc_or_label_ref" "")
-	      (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bb%L2%. %C0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc) (if_then_else
-	      (match_operator 0 "odd_relop"
-			      [(match_operand:CCEVEN 1 "register_operand" "r")
-			       (const_int 0)])
-	      (match_operand 2 "pc_or_label_ref" "")
-	      (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bb%L3%. %!%C0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-;; Branch conditional on scc values.  These arise from manipulations on
-;; compare words above.
-;; Are these really used ? 
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (match_operator 0 "relop"
-			     [(match_operand:CC 1 "register_operand" "r")
-			      (const_int 0)])
-	     (const_int 0))
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bb%L2 %C0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (match_operator 0 "even_relop"
-			     [(match_operand:CCEVEN 1 "register_operand" "r")
-			      (const_int 0)])
-	     (const_int 0))
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bb%L2 %C0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (match_operator 0 "odd_relop"
-			     [(match_operand:CCEVEN 1 "register_operand" "r")
-			      (const_int 0)])
-	     (const_int 0))
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bb%L3 %!%C0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (match_operator 0 "relop"
-			     [(match_operand:CC 1 "register_operand" "r")
-			      (const_int 0)])
-	     (const_int 0))
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bb%L3 %C0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (match_operator 0 "even_relop"
-			     [(match_operand:CCEVEN 1 "register_operand" "r")
-			      (const_int 0)])
-	     (const_int 0))
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bb%L3 %C0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (match_operator 0 "odd_relop"
-			     [(match_operand:CCEVEN 1 "register_operand" "r")
-			      (const_int 0)])
-	     (const_int 0))
-	 (match_operand 2 "pc_or_label_ref" "")
-	 (match_operand 3 "pc_or_label_ref" "")))]
-  ""
-  "bb%L2 %!%C0,%1,%P2%P3"
-  [(set_attr "type" "branch")])
-
-(define_insn "locate1"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(high:SI (unspec:SI [(label_ref (match_operand 1 "" ""))] 0)))]
-  ""
-  "or.u %0,%#r0,%#hi16(%1#abdiff)")
-
-(define_insn "locate2"
-  [(parallel [(set (reg:SI 1) (pc))
-	      (set (match_operand:SI 0 "register_operand" "=r")
-		   (lo_sum:SI (match_dup 0)
-			      (unspec:SI
-			       [(label_ref (match_operand 1 "" ""))] 0)))])]
-  ""
-  "bsr.n %1\;or %0,%0,%#lo16(%1#abdiff)\\n%1:"
-  [(set_attr "length" "2")])
-
-;; SImode move instructions
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, SImode, 0))
-    DONE;
-}")
-
-(define_expand "reload_insi"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "general_operand" ""))
-   (clobber (match_operand:SI 2 "register_operand" "=&r"))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, SImode, operands[2]))
-    DONE;
-
-  /* We don't want the clobber emitted, so handle this ourselves.  */
-  emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,x,x,x,m")
-	(match_operand:SI 1 "move_operand" "rI,m,rO,J,M,x,r,x,m,x"))]
-  "(register_operand (operands[0], SImode)
-    || register_operand (operands[1], SImode)
-    || operands[1] == const0_rtx)"
-  "@
-   or %0,%#r0,%1
-   %V1ld\\t %0,%1
-   %v0st\\t %r1,%0
-   subu %0,%#r0,%n1
-   set %0,%#r0,%s1
-   mov.s %0,%1
-   mov.s %0,%1
-   mov %0,%1
-   %V1ld\\t %0,%1
-   %v0st\\t %1,%0"
-  [(set_attr "type" "arith,load,store,arith,bit,mov,mov,mov,load,store")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
-	(match_operand:SI 1 "arith32_operand" "rI,J,L,M,n"))]
-  ""
-  "@
-   or %0,%#r0,%1
-   subu %0,%#r0,%n1
-   or.u %0,%#r0,%X1
-   set %0,%#r0,%s1
-   or.u %0,%#r0,%X1\;or %0,%0,%x1"
-  [(set_attr "type" "arith,arith,arith,bit,marith")])
-
-;; @@ Why the constraint "in"?  Doesn't `i' include `n'?
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-		   (match_operand:SI 2 "immediate_operand" "in")))]
-  ""
-  "or %0,%1,%#lo16(%g2)")
-
-;; For PIC, symbol_refs are put inside unspec so that the optimizer won't
-;; confuse them with real addresses.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-		   (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))]
-  ""
-  "or %0,%1,%#lo16(%g2)"
-  ;; Need to set length for this arith insn because operand2
-  ;; is not an "arith_operand".
-  [(set_attr "length" "1")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(high:SI (match_operand 1 "" "")))]
-  ""
-  "or.u %0,%#r0,%#hi16(%g1)")
-
-;; For PIC, symbol_refs are put inside unspec so that the optimizer won't
-;; confuse them with real addresses.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(high:SI (unspec:SI [(match_operand 1 "" "")] 0)))]
-  ""
-  "or.u %0,%#r0,%#hi16(%g1)"
-  ;; Need to set length for this arith insn because operand2
-  ;; is not an arith_operand.
-  [(set_attr "length" "1")])
-
-;; HImode move instructions
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, HImode, 0))
-    DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
-	(match_operand:HI 1 "move_operand" "rP,m,rO,N"))]
-  "(register_operand (operands[0], HImode)
-    || register_operand (operands[1], HImode)
-    || operands[1] == const0_rtx)"
-  "@
-   or %0,%#r0,%h1
-   %V1ld.hu\\t %0,%1
-   %v0st.h\\t %r1,%0
-   subu %0,%#r0,%H1"
-  [(set_attr "type" "arith,load,store,arith")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(subreg:HI (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-			      (match_operand:SI 2 "immediate_operand" "in")) 0))]
-  "!flag_pic"
-  "or %0,%1,%#lo16(%2)")
-
-;; QImode move instructions
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, QImode, 0))
-    DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r")
-	(match_operand:QI 1 "move_operand" "rP,m,rO,N"))]
-  "(register_operand (operands[0], QImode)
-    || register_operand (operands[1], QImode)
-    || operands[1] == const0_rtx)"
-  "@
-   or %0,%#r0,%q1
-   %V1ld.bu\\t %0,%1
-   %v0st.b\\t %r1,%0
-   subu %r0,%#r0,%Q1"
-  [(set_attr "type" "arith,load,store,arith")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(subreg:QI (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-			      (match_operand:SI 2 "immediate_operand" "in")) 0))]
-  "!flag_pic"
-  "or %0,%1,%#lo16(%2)")
-
-;; DImode move instructions
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, DImode, 0))
-    DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r,x")
-	(const_int 0))]
-  ""
-  "@
-   or %0,%#r0,0\;or %d0,%#r0,0
-   mov %0,%#x0"
-  [(set_attr "type" "marith,mov")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,x,x,x,m")
-	(match_operand:DI 1 "nonimmediate_operand" "r,m,r,x,r,x,m,x"))]
-  ""
-  "@
-   or %0,%#r0,%1\;or %d0,%#r0,%d1
-   %V1ld.d\\t %0,%1
-   %v0st.d\\t %1,%0
-   mov.d %0,%1
-   mov.d %0,%1
-   mov %0,%1
-   %V1ld.d\\t %0,%1
-   %v0st.d\\t %1,%0"
-  [(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(subreg:DI (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-			      (match_operand:SI 2 "immediate_operand" "in")) 0))]
-  "!flag_pic"
-  "or %0,%1,%#lo16(%2)")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(match_operand:DI 1 "immediate_operand" "n"))]
-   ""
-   "* return output_load_const_dimode (operands);"
-  [(set_attr "type" "marith")
-   (set_attr "length" "4")]) ; length is 2, 3 or 4.
-
-;; DFmode move instructions
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, DFmode, 0))
-    DONE;
-}")
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(match_operand:DF 1 "register_operand" "r"))]
-  "reload_completed
-   && GET_CODE (operands[0]) == REG && !XRF_REGNO_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && !XRF_REGNO_P (REGNO (operands[1]))"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 5))]
-  "
-{ operands[2] = operand_subword (operands[0], 0, 0, DFmode);
-  operands[3] = operand_subword (operands[1], 0, 0, DFmode);
-  operands[4] = operand_subword (operands[0], 1, 0, DFmode);
-  operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
-
-;; @@ This pattern is incomplete and doesn't appear necessary.
-;;
-;; This pattern forces (set (reg:DF ...) (const_double ...))
-;; to be reloaded by putting the constant into memory.
-;; It must come before the more general movdf pattern.
-
-;(define_insn ""
-;  [(set (match_operand:DF 0 "general_operand" "=r,o")
-;	(match_operand:DF 1 "" "G,G"))]
-;  "GET_CODE (operands[1]) == CONST_DOUBLE"
-;  "*
-;{
-;  switch (which_alternative)
-;    {
-;    case 0:
-;      return \"or %0,%#r0,0\;or %d0,%#r0,0\";
-;    case 1:
-;      operands[1] = adj_offsettable_operand (operands[0], 4);
-;      return \"%v0st\\t %#r0,%0\;st %#r0,%1\";
-;    }
-;}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(const_int 0))]
-  ""
-  "@
-   or %0,%#r0,0\;or %d0,%#r0,0
-   mov %0,%#x0"
-  [(set_attr "type" "marith,mov")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,x,r,x,x,m")
-	(match_operand:DF 1 "nonimmediate_operand" "r,m,r,r,x,x,m,x"))]
-  ""
-  "@
-   or %0,%#r0,%1\;or %d0,%#r0,%d1
-   %V1ld.d\\t %0,%1
-   %v0st.d\\t %1,%0
-   mov.d %0,%1
-   mov.d %0,%1
-   mov %0,%1
-   %V1ld.d\\t %0,%1
-   %v0st.d\\t %1,%0"
-  [(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(subreg:DF (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-			      (match_operand:SI 2 "immediate_operand" "in")) 0))]
-  "!flag_pic"
-  "or %0,%1,%#lo16(%2)")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(match_operand:DF 1 "immediate_operand" "F"))]
-   ""
-   "* return output_load_const_double (operands);"
-  [(set_attr "type" "marith")
-   (set_attr "length" "4")]) ; length is 2, 3, or 4.
-
-;; SFmode move instructions
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, SFmode, 0))
-    DONE;
-}")
-
-;; @@ What happens to fconst0_rtx?
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r,x")
-	(const_int 0))]
-  ""
-  "@
-   or %0,%#r0,0
-   mov %0,%#x0"
-  [(set_attr "type" "arith,mov")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,x,r,x,x,m")
-	(match_operand:SF 1 "nonimmediate_operand" "r,m,r,r,x,x,m,x"))]
-  ""
-  "@
-   or %0,%#r0,%1
-   %V1ld\\t %0,%1
-   %v0st\\t %r1,%0
-   mov.s %0,%1
-   mov.s %0,%1
-   mov %0,%1
-   %V1ld\\t %0,%1
-   %v0st\\t %r1,%0"
-  [(set_attr "type" "arith,load,store,mov,mov,mov,load,store")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(subreg:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-			      (match_operand:SI 2 "immediate_operand" "in")) 0))]
-  "!flag_pic"
-  "or %0,%1,%#lo16(%2)")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(match_operand:SF 1 "immediate_operand" "F"))]
-  "operands[1] != const0_rtx"
-  "* return output_load_const_float (operands);"
-  [(set_attr "type" "marith")]) ; length is 1 or 2.
-
-;; String/block move insn.  See m88k.c for details.
-
-(define_expand "movstrsi"
-  [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
-		   (mem:BLK (match_operand:BLK 1 "" "")))
-	      (use (match_operand:SI 2 "arith32_operand" ""))
-	      (use (match_operand:SI 3 "immediate_operand" ""))])]
-  ""
-  "
-{
-  rtx dest_mem = operands[0];
-  rtx src_mem = operands[1];
-  operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
-  operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
-  expand_block_move (dest_mem, src_mem, operands);
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(match_operand:BLK 1 "memory_operand" "m"))]
-  ""
-  "%V1ld.bu\\t %0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(match_operand:BLK 1 "memory_operand" "m"))]
-  ""
-  "%V1ld.hu\\t %0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:BLK 1 "memory_operand" "m"))]
-  ""
-  "%V1ld\\t %0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(match_operand:BLK 1 "memory_operand" "m"))]
-  ""
-  "%V1ld.d\\t %0,%1"
-  [(set_attr "type" "loadd")])
-
-(define_insn ""
-  [(set (match_operand:BLK 0 "memory_operand" "=m")
-	(match_operand:QI 1 "register_operand" "r"))]
-  ""
-  "%v0st.b\\t %1,%0"
-  [(set_attr "type" "store")])
-
-(define_insn ""
-  [(set (match_operand:BLK 0 "memory_operand" "=m")
-	(match_operand:HI 1 "register_operand" "r"))]
-  ""
-  "%v0st.h\\t %1,%0"
-  [(set_attr "type" "store")])
-
-(define_insn ""
-  [(set (match_operand:BLK 0 "memory_operand" "=m")
-	(match_operand:SI 1 "register_operand" "r"))]
-  ""
-  "%v0st\\t %1,%0"
-  [(set_attr "type" "store")])
-
-(define_insn ""
-  [(set (match_operand:BLK 0 "memory_operand" "=m")
-	(match_operand:DI 1 "register_operand" "r"))]
-  ""
-  "%v0st.d\\t %1,%0"
-  [(set_attr "type" "store")])
-
-;; Call a non-looping block move library function (e.g. __movstrSI96x64).
-;; operand 0 is the function name
-;; operand 1 is the destination pointer
-;; operand 2 is the source pointer
-;; operand 3 is the offset for the source and destination pointers
-;; operand 4 is the first value to be loaded
-;; operand 5 is the register to hold the value (r4 or r5)
-
-(define_expand "call_block_move"
-  [(set (reg:SI 3) (minus:SI (match_operand:SI 2 "register_operand" "")
-			     (match_operand:SI 3 "immediate_operand" "")))
-   (set (match_operand 5 "register_operand" "")
-	(match_operand 4 "memory_operand" ""))
-   (set (reg:SI 2) (minus:SI (match_operand:SI 1 "register_operand" "")
-			     (match_dup 3)))
-   (use (reg:SI 2))
-   (use (reg:SI 3))
-   (use (match_dup 5))
-   (parallel [(set (reg:DI 2)
-		   (call (mem:SI (match_operand 0 "" ""))
-			 (const_int 0)))
-	      (clobber (reg:SI 1))])]
-  ""
-  "")
-
-;; Call an SImode looping block move library function (e.g. __movstrSI64n68).
-;; operands 0-5 as in the non-looping interface
-;; operand 6 is the loop count
-
-(define_expand "call_movstrsi_loop"
-  [(set (reg:SI 3) (minus:SI (match_operand:SI 2 "register_operand" "")
-			     (match_operand:SI 3 "immediate_operand" "")))
-   (set (match_operand:SI 5 "register_operand" "")
-	(match_operand 4 "memory_operand" ""))
-   (set (reg:SI 2) (minus:SI (match_operand:SI 1 "register_operand" "")
-			     (match_dup 3)))
-   (set (reg:SI 6) (match_operand:SI 6 "immediate_operand" ""))
-   (use (reg:SI 2))
-   (use (reg:SI 3))
-   (use (match_dup 5))
-   (use (reg:SI 6))
-   (parallel [(set (reg:DI 2)
-		   (call (mem:SI (match_operand 0 "" ""))
-			 (const_int 0)))
-	      (clobber (reg:SI 1))])]
-  ""
-  "")
-
-;;- zero extension instructions
-
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == MEM
-      && symbolic_address_p (XEXP (operands[1], 0)))
-    operands[1]
-      = legitimize_address (flag_pic, operands[1], 0, 0);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(zero_extend:SI (match_operand:HI 1 "move_operand" "!r,n,m")))]
-  "GET_CODE (operands[1]) != CONST_INT"
-  "@
-   mask %0,%1,0xffff
-   or %0,%#r0,%h1
-   %V1ld.hu\\t %0,%1"
-  [(set_attr "type" "arith,arith,load")])
-
-(define_expand "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == MEM
-      && symbolic_address_p (XEXP (operands[1], 0)))
-    operands[1]
-      = legitimize_address (flag_pic, operands[1], 0, 0);
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
-	(zero_extend:HI (match_operand:QI 1 "move_operand" "r,n,m")))]
-  "GET_CODE (operands[1]) != CONST_INT"
-  "@
-   mask %0,%1,0xff
-   or %0,%#r0,%q1
-   %V1ld.bu\\t %0,%1"
-  [(set_attr "type" "arith,arith,load")])
-
-(define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == MEM
-      && symbolic_address_p (XEXP (operands[1], 0)))
-    {
-      operands[1]
-	= legitimize_address (flag_pic, operands[1], 0, 0);
-      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-			  gen_rtx (ZERO_EXTEND, SImode, operands[1])));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(zero_extend:SI (match_operand:QI 1 "move_operand" "r,n,m")))]
-  "GET_CODE (operands[1]) != CONST_INT"
-  "@
-   mask %0,%1,0xff
-   or %0,%#r0,%q1
-   %V1ld.bu\\t %0,%1"
-  [(set_attr "type" "arith,arith,load")])
-
-;;- sign extension instructions
-
-(define_expand "extendsidi2"
-  [(set (subreg:SI (match_operand:DI 0 "register_operand" "=r") 1)
-        (match_operand:SI 1 "general_operand" "g"))
-   (set (subreg:SI (match_dup 0) 0)
-        (ashiftrt:SI (subreg:SI (match_dup 0) 1)
-                     (const_int 31)))]
-  ""
-  "")
-
-(define_expand "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == MEM
-      && symbolic_address_p (XEXP (operands[1], 0)))
-    operands[1]
-      = legitimize_address (flag_pic, operands[1], 0, 0);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(sign_extend:SI (match_operand:HI 1 "move_operand" "!r,P,N,m")))]
-  "GET_CODE (operands[1]) != CONST_INT"
-  "@
-   ext %0,%1,16<0>
-   or %0,%#r0,%h1
-   subu %0,%#r0,%H1
-   %V1ld.h\\t %0,%1"
-  [(set_attr "type" "bit,arith,arith,load")])
-
-(define_expand "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == MEM
-      && symbolic_address_p (XEXP (operands[1], 0)))
-    operands[1]
-      = legitimize_address (flag_pic, operands[1], 0, 0);
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
-	(sign_extend:HI (match_operand:QI 1 "move_operand" "!r,P,N,m")))]
-  "GET_CODE (operands[1]) != CONST_INT"
-  "@
-   ext %0,%1,8<0>
-   or %0,%#r0,%q1
-   subu %0,%#r0,%Q1
-   %V1ld.b\\t %0,%1"
-  [(set_attr "type" "bit,arith,arith,load")])
-
-(define_expand "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == MEM
-      && symbolic_address_p (XEXP (operands[1], 0)))
-    operands[1]
-      = legitimize_address (flag_pic, operands[1], 0, 0);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(sign_extend:SI (match_operand:QI 1 "move_operand" "!r,P,N,m")))]
-  "GET_CODE (operands[1]) != CONST_INT"
-  "@
-   ext %0,%1,8<0>
-   or %0,%#r0,%q1
-   subu %0,%#r0,%Q1
-   %V1ld.b\\t %0,%1"
-  [(set_attr "type" "bit,arith,arith,load")])
-
-;; Conversions between float and double.
-
-;; The fadd instruction does not conform to IEEE 754 when used to
-;; convert between float and double.  In particular, the sign of -0 is
-;; not preserved.  Interestingly, fsub does conform.
-
-(define_expand "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
-  "! TARGET_88110"
-  "fsub.dss %0,%1,%#r0"
-  [(set_attr "type" "spadd")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(float_extend:DF (match_operand:SF 1 "register_operand" "r,x")))]
-  "TARGET_88110"
-  "fcvt.ds %0,%1"
-  [(set_attr "type" "spadd")])
-
-(define_expand "truncdfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
-  "! TARGET_88110"
-  "fsub.sds %0,%1,%#r0"
-  [(set_attr "type" "dpadd")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r,x")
-	(float_truncate:SF (match_operand:DF 1 "register_operand" "r,x")))]
-  "TARGET_88110"
-  "fcvt.sd %0,%1"
-  [(set_attr "type" "dpadd")])
-
-;; Conversions between floating point and integer
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(float:DF (match_operand:SI 1 "register_operand" "r,r")))]
-  ""
-  "flt.ds %0,%1"
-  [(set_attr "type" "spadd,dpadd")])
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "register_operand" "=r,x")
-	(float:SF (match_operand:SI 1 "register_operand" "r,r")))]
-  ""
-  "flt.ss %0,%1"
-  [(set_attr "type" "spadd,spadd")])
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(fix:SI (match_operand:DF 1 "register_operand" "r,x")))]
-  ""
-  "trnc.sd %0,%1"
-  [(set_attr "type" "dpadd,dpadd")])
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(fix:SI (match_operand:SF 1 "register_operand" "r,x")))]
-  ""
-  "trnc.ss %0,%1"
-  [(set_attr "type" "spadd,dpadd")])
-
-
-;;- arithmetic instructions
-;;- add instructions
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (match_operand:SI 1 "add_operand" "%r,r")
-		 (match_operand:SI 2 "add_operand" "rI,J")))]
-  ""
-  "@
-   addu %0,%1,%2
-   subu %0,%1,%n2")
-
-;; patterns for mixed mode floating point.
-;; Do not define patterns that utilize mixed mode arithmetic that result
-;; in narrowing the precision, because it loses accuracy, since the standard
-;; requires double rounding, whereas the 88000 instruction only rounds once.
-
-(define_expand "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(plus:DF (match_operand:DF 1 "general_operand" "%r,x")
-		 (match_operand:DF 2 "general_operand" "r,x")))]
-  ""
-  "
-{
-  operands[1] = legitimize_operand (operands[1], DFmode);
-  operands[2] = legitimize_operand (operands[2], DFmode);
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
-		 (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
-  ""
-  "fadd.dss %0,%1,%2"
-  [(set_attr "type" "spadd")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(plus:DF (match_operand:DF 1 "register_operand" "r,x")
-		 (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
-  ""
-  "fadd.dds %0,%1,%2"
-  [(set_attr "type" "dpadd")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
-		 (match_operand:DF 2 "register_operand" "r,x")))]
-  ""
-  "fadd.dsd %0,%1,%2"
-  [(set_attr "type" "dpadd")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(plus:DF (match_operand:DF 1 "register_operand" "%r,x")
-		 (match_operand:DF 2 "register_operand" "r,x")))]
-  ""
-  "fadd.ddd %0,%1,%2"
-  [(set_attr "type" "dpadd")])
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r,x")
-	(plus:SF (match_operand:SF 1 "register_operand" "%r,x")
-		 (match_operand:SF 2 "register_operand" "r,x")))]
-  ""
-  "fadd.sss %0,%1,%2"
-  [(set_attr "type" "spadd")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_operand:DI 1 "register_operand" "r")
-		 (zero_extend:DI
-		  (match_operand:SI 2 "register_operand" "r"))))
-   (clobber (reg:CC 0))]
-  ""
-  "addu.co %d0,%d1,%2\;addu.ci %0,%1,%#r0"
-  [(set_attr "type" "marith")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (zero_extend:DI
-		  (match_operand:SI 1 "register_operand" "r"))
-		 (match_operand:DI 2 "register_operand" "r")))
-   (clobber (reg:CC 0))]
-  ""
-  "addu.co %d0,%1,%d2\;addu.ci %0,%#r0,%2"
-  [(set_attr "type" "marith")])
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_operand:DI 1 "register_operand" "%r")
-		 (match_operand:DI 2 "register_operand" "r")))
-   (clobber (reg:CC 0))]
-  ""
-  "addu.co %d0,%d1,%d2\;addu.ci %0,%1,%2"
-  [(set_attr "type" "marith")])
-
-;; Add with carry insns.
-
-(define_insn ""
-  [(parallel [(set (match_operand:SI 0 "reg_or_0_operand" "=r")
-		   (plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
-			    (match_operand:SI 2 "reg_or_0_operand" "rO")))
-	      (set (reg:CC 0)
-		   (unspec:CC [(match_dup 1) (match_dup 2)] 0))])]
-  ""
-  "addu.co %r0,%r1,%r2")
-
-(define_insn ""
-  [(set (reg:CC 0) (unspec:CC [(match_operand:SI 0 "reg_or_0_operand" "rO")
-			       (match_operand:SI 1 "reg_or_0_operand" "rO")]
-			      0))]
-  ""
-  "addu.co %#r0,%r0,%r1")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "reg_or_0_operand" "=r")
-	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
-		 (unspec:SI [(match_operand:SI 2 "reg_or_0_operand" "rO")
-			     (reg:CC 0)] 0)))]
-  ""
-  "addu.ci %r0,%r1,%r2")
-
-;;- subtract instructions
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (match_operand:SI 2 "arith32_operand" "rI")))]
-  ""
-  "subu %0,%1,%2")
-
-;; patterns for mixed mode floating point
-;; Do not define patterns that utilize mixed mode arithmetic that result
-;; in narrowing the precision, because it loses accuracy, since the standard
-;; requires double rounding, whereas the 88000 instruction only rounds once.
-
-(define_expand "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(minus:DF (match_operand:DF 1 "general_operand" "r,x")
-		  (match_operand:DF 2 "general_operand" "r,x")))]
-  ""
-  "
-{
-  operands[1] = legitimize_operand (operands[1], DFmode);
-  operands[2] = legitimize_operand (operands[2], DFmode);
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
-		  (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
-  ""
-  "fsub.dss %0,%1,%2"
-  [(set_attr "type" "spadd")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(minus:DF (match_operand:DF 1 "register_operand" "r,x")
-		  (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
-  ""
-  "fsub.dds %0,%1,%2"
-  [(set_attr "type" "dpadd")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
-		  (match_operand:DF 2 "register_operand" "r,x")))]
-  ""
-  "fsub.dsd %0,%1,%2"
-  [(set_attr "type" "dpadd")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(minus:DF (match_operand:DF 1 "register_operand" "r,x")
-		  (match_operand:DF 2 "register_operand" "r,x")))]
-  ""
-  "fsub.ddd %0,%1,%2"
-  [(set_attr "type" "dpadd")])
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r,x")
-	(minus:SF (match_operand:SF 1 "register_operand" "r,x")
-		  (match_operand:SF 2 "register_operand" "r,x")))]
-  ""
-  "fsub.sss %0,%1,%2"
-  [(set_attr "type" "spadd")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "register_operand" "r")
-		  (zero_extend:DI
-		   (match_operand:SI 2 "register_operand" "r"))))
-   (clobber (reg:CC 0))]
-  ""
-  "subu.co %d0,%d1,%2\;subu.ci %0,%1,%#r0"
-  [(set_attr "type" "marith")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (zero_extend:DI
-		   (match_operand:SI 1 "register_operand" "r"))
-		  (match_operand:DI 2 "register_operand" "r")))
-   (clobber (reg:CC 0))]
-  ""
-  "subu.co %d0,%1,%d2\;subu.ci %0,%#r0,%2"
-  [(set_attr "type" "marith")])
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "register_operand" "r")
-		  (match_operand:DI 2 "register_operand" "r")))
-   (clobber (reg:CC 0))]
-  ""
-  "subu.co %d0,%d1,%d2\;subu.ci %0,%1,%2"
-  [(set_attr "type" "marith")])
-
-;; Subtract with carry insns.
-
-(define_insn ""
-  [(parallel [(set (match_operand:SI 0 "reg_or_0_operand" "=r")
-		   (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
-			     (match_operand:SI 2 "reg_or_0_operand" "rO")))
-	      (set (reg:CC 0)
-		   (unspec:CC [(match_dup 1) (match_dup 2)] 1))])]
-  ""
-  "subu.co %r0,%r1,%r2")
-
-(define_insn ""
-  [(set (reg:CC 0) (unspec:CC [(match_operand:SI 0 "reg_or_0_operand" "rO")
-			       (match_operand:SI 1 "reg_or_0_operand" "rO")]
-			      1))]
-  ""
-  "subu.co %#r0,%r0,%r1")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "reg_or_0_operand" "=r")
-	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
-		  (unspec:SI [(match_operand:SI 2 "reg_or_0_operand" "rO")
-			      (reg:CC 0)] 1)))]
-  ""
-  "subu.ci %r0,%r1,%r2")
-
-;;- multiply instructions
-;;
-;; There is an unfounded silicon errata for E.1 requiring that an
-;; immediate constant value in div/divu/mul instructions be less than
-;; 0x800.  This is no longer provided for.
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (match_operand:SI 1 "arith32_operand" "%r")
-		 (match_operand:SI 2 "arith32_operand" "rI")))]
-  ""
-  "mul %0,%1,%2"
-  [(set_attr "type" "imul")])
-
-(define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
-                 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
-  "TARGET_88110"
-  "mulu.d %0,%1,%2"
-  [(set_attr "type" "imul")])
-
-;; patterns for mixed mode floating point
-;; Do not define patterns that utilize mixed mode arithmetic that result
-;; in narrowing the precision, because it loses accuracy, since the standard
-;; requires double rounding, whereas the 88000 instruction only rounds once.
-
-(define_expand "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(mult:DF (match_operand:DF 1 "general_operand" "%r,x")
-		 (match_operand:DF 2 "general_operand" "r,x")))]
-  ""
-  "
-{
-  operands[1] = legitimize_operand (operands[1], DFmode);
-  operands[2] = legitimize_operand (operands[2], DFmode);
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
-		 (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
-  ""
-  "fmul.dss %0,%1,%2"
-  [(set_attr "type" "spmul")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(mult:DF (match_operand:DF 1 "register_operand" "r,x")
-		 (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
-  ""
-  "fmul.dds %0,%1,%2"
-  [(set_attr "type" "spmul")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
-		 (match_operand:DF 2 "register_operand" "r,x")))]
-  ""
-  "fmul.dsd %0,%1,%2"
-  [(set_attr "type" "spmul")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(mult:DF (match_operand:DF 1 "register_operand" "%r,x")
-		 (match_operand:DF 2 "register_operand" "r,x")))]
-  ""
-  "fmul.ddd %0,%1,%2"
-  [(set_attr "type" "dpmul")])
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r,x")
-	(mult:SF (match_operand:SF 1 "register_operand" "%r,x")
-		 (match_operand:SF 2 "register_operand" "r,x")))]
-  ""
-  "fmul.sss %0,%1,%2"
-  [(set_attr "type" "spmul")])
-
-;;- divide instructions
-;;
-;; The 88k div and divu instructions don't reliably trap on
-;; divide-by-zero.  A trap to vector 503 asserts divide-by-zero.  The
-;; general scheme for doing divide is to do a 4-way split based on the
-;; sign of the two operand and do the appropriate negates.
-;;
-;; The conditional trap instruction is not used as this serializes the
-;; processor.  Instead a conditional branch and an unconditional trap
-;; are used, but after the divu.  Since the divu takes up to 38 cycles,
-;; the conditional branch is essentially free.
-;;
-;; Two target options control how divide is done.  One options selects
-;; whether to do the branch and negate scheme instead of using the div
-;; instruction; the other option selects whether to explicitly check
-;; for divide-by-zero or take your chances.  If the div instruction is
-;; used, the O/S must complete the operation if the operands are
-;; negative.  The O/S will signal an overflow condition if the most
-;; negative number (-2147483648) is divided by negative 1.
-;;
-;; There is an unfounded silicon errata for E.1 requiring that an
-;; immediate constant value in div/divu/mul instructions be less than
-;; 0x800.  This is no longer provided for.
-
-;; Division by 0 trap
-(define_insn "trap_divide_by_zero"
-  [(trap_if (const_int 1) (const_int 503))]
-  ""
-  "tb0 0,%#r0,503"
-  [(set_attr "type" "weird")])
-
-;; Conditional division by 0 trap.
-(define_expand "tcnd_divide_by_zero"
-  [(set (pc)
-	(if_then_else (eq (match_operand:SI 0 "register_operand" "")
-			  (const_int 0))
-		      (pc)
-		      (match_operand 1 "" "")))
-   (trap_if (const_int 1) (const_int 503))]
-  ""
-  "
-{
-  emit_insn (gen_cmpsi (operands[0], const0_rtx));
-  emit_jump_insn (gen_bne (operands[1]));
-  emit_insn (gen_trap_divide_by_zero ());
-  DONE;
-}")
-
-(define_expand "divsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(div:SI (match_operand:SI 1 "arith32_operand" "")
-		(match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-  rtx op2 = operands[2];
-  rtx join_label;
-
-  /* @@ This needs to be reworked.  Torbjorn Granlund has suggested making
-     it a runtime (perhaps quite special).  */
-
-  if (GET_CODE (op1) == CONST_INT)
-    op1 = force_reg (SImode, op1);
-
-  else if (GET_CODE (op2) == CONST_INT
-	   && ! SMALL_INT (operands[2]))
-    op2 = force_reg (SImode, op2);
-
-  if (op2 == const0_rtx)
-    {
-      emit_insn (gen_trap_divide_by_zero ());
-      emit_insn (gen_dummy (op0));
-      DONE;
-    }
-
-  if (TARGET_USE_DIV)
-    {
-      emit_move_insn (op0, gen_rtx (DIV, SImode, op1, op2));
-      if (TARGET_CHECK_ZERO_DIV && GET_CODE (op2) != CONST_INT)
-	{
-	  rtx label = gen_label_rtx ();
-	  emit_insn (gen_tcnd_divide_by_zero (op2, label));
-	  emit_label (label);
-	  emit_insn (gen_dummy (op0));
-	}
-      DONE;
-    }
-
-  join_label = gen_label_rtx ();
-  if (GET_CODE (op1) == CONST_INT)
-    {
-      int neg = FALSE;
-      rtx neg_op2 = gen_reg_rtx (SImode);
-      rtx label1 = gen_label_rtx ();
-
-      if (INTVAL (op1) < 0)
-	{
-	  neg = TRUE;
-	  op1 = GEN_INT (-INTVAL (op1));
-	}
-      op1 = force_reg (SImode, op1);
-
-      emit_insn (gen_negsi2 (neg_op2, op2));
-      emit_insn (gen_cmpsi (op2, const0_rtx));
-      emit_jump_insn (gen_bgt (label1));
-						/* constant / 0-or-negative */
-      emit_move_insn (op0, gen_rtx (UDIV, SImode, op1, neg_op2));
-      if (!neg)
-	emit_insn (gen_negsi2 (op0, op0));
-
-      if (TARGET_CHECK_ZERO_DIV)
-	emit_insn (gen_tcnd_divide_by_zero (op2, join_label));
-      emit_jump_insn (gen_jump (join_label));
-      emit_barrier ();
-
-      emit_label (label1);			/* constant / positive */
-      emit_move_insn (op0, gen_rtx (UDIV, SImode, op1, op2));
-      if (neg)
-	emit_insn (gen_negsi2 (op0, op0));
-    }
-
-  else if (GET_CODE (op2) == CONST_INT)
-    {
-      int neg = FALSE;
-      rtx neg_op1 = gen_reg_rtx (SImode);
-      rtx label1 = gen_label_rtx ();
-
-      if (INTVAL (op2) < 0)
-	{
-	  neg = TRUE;
-	  op2 = GEN_INT (-INTVAL (op2));
-	}
-      else if (! SMALL_INT (operands[2]))
-	op2 = force_reg (SImode, op2);
-
-      emit_insn (gen_negsi2 (neg_op1, op1));
-      emit_insn (gen_cmpsi (op1, const0_rtx));
-      emit_jump_insn (gen_bge (label1));
-						/* 0-or-negative / constant */
-      emit_move_insn (op0, gen_rtx (UDIV, SImode, neg_op1, op2));
-      if (!neg)
-	emit_insn (gen_negsi2 (op0, op0));
-
-      emit_jump_insn (gen_jump (join_label));
-      emit_barrier ();
-
-      emit_label (label1);			/* positive / constant */
-      emit_move_insn (op0, gen_rtx (UDIV, SImode, op1, op2));
-      if (neg)
-	emit_insn (gen_negsi2 (op0, op0));
-    }
-
-  else
-    {
-      rtx neg_op1 = gen_reg_rtx (SImode);
-      rtx neg_op2 = gen_reg_rtx (SImode);
-      rtx label1 = gen_label_rtx ();
-      rtx label2 = gen_label_rtx ();
-      rtx label3 = gen_label_rtx ();
-      rtx label4;
-
-      emit_insn (gen_negsi2 (neg_op2, op2));
-      emit_insn (gen_cmpsi (op2, const0_rtx));
-      emit_jump_insn (gen_bgt (label1));
-
-      emit_insn (gen_negsi2 (neg_op1, op1));
-      emit_insn (gen_cmpsi (op1, const0_rtx));
-      emit_jump_insn (gen_bge (label2));
-						/* negative / negative-or-0 */
-      emit_move_insn (op0, gen_rtx (UDIV, SImode, neg_op1, neg_op2));
-
-      if (TARGET_CHECK_ZERO_DIV)
-	{
-	  label4 = gen_label_rtx ();
-	  emit_insn (gen_cmpsi (op2, const0_rtx));
-	  emit_jump_insn (gen_bne (join_label));
-	  emit_label (label4);
-	  emit_insn (gen_trap_divide_by_zero ());
-	}
-      emit_jump_insn (gen_jump (join_label));
-      emit_barrier ();
-
-      emit_label (label2);			/* pos.-or-0 / neg.-or-0 */
-      emit_move_insn (op0, gen_rtx (UDIV, SImode, op1, neg_op2));
-
-      if (TARGET_CHECK_ZERO_DIV)
-	{
-	  emit_insn (gen_cmpsi (op2, const0_rtx));
-	  emit_jump_insn (gen_beq (label4));
-	}
-
-      emit_insn (gen_negsi2 (op0, op0));
-      emit_jump_insn (gen_jump (join_label));
-      emit_barrier ();
-
-      emit_label (label1);
-      emit_insn (gen_negsi2 (neg_op1, op1));
-      emit_insn (gen_cmpsi (op1, const0_rtx));
-      emit_jump_insn (gen_bge (label3));
-						/* negative / positive */
-      emit_move_insn (op0, gen_rtx (UDIV, SImode, neg_op1, op2));
-      emit_insn (gen_negsi2 (op0, op0));
-      emit_jump_insn (gen_jump (join_label));
-      emit_barrier ();
-
-      emit_label (label3);			/* positive-or-0 / positive */
-      emit_move_insn (op0, gen_rtx (UDIV, SImode, op1, op2));
-    }
-
-  emit_label (join_label);
-
-  emit_insn (gen_dummy (op0));
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(div:SI (match_operand:SI 1 "register_operand" "r")
-		(match_operand:SI 2 "arith_operand" "rI")))]
-  ""
-  "div %0,%1,%2"
-  [(set_attr "type" "idiv")])
-
-(define_expand "udivsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(udiv:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  rtx op2 = operands[2];
-
-  if (op2 == const0_rtx)
-    {
-      emit_insn (gen_trap_divide_by_zero ());
-      emit_insn (gen_dummy (operands[0]));
-      DONE;
-    }
-  else if (GET_CODE (op2) != CONST_INT && TARGET_CHECK_ZERO_DIV)
-    {
-      rtx label = gen_label_rtx ();
-      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-			  gen_rtx (UDIV, SImode, operands[1], op2)));
-      emit_insn (gen_tcnd_divide_by_zero (op2, label));
-      emit_label (label);
-      emit_insn (gen_dummy (operands[0]));
-      DONE;
-    }
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
-       (udiv:SI (match_operand:SI 1 "register_operand" "r")
-		(match_operand:SI 2 "arith32_operand" "rI")))]
-  "operands[2] != const0_rtx"
-  "divu %0,%1,%2"
-  [(set_attr "type" "idiv")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
-       (udiv:SI (match_operand:SI 1 "register_operand" "r")
-		(const_int 0)))]
-  ""
-  "tb0 0,%#r0,503"
-  [(set_attr "type" "weird")])
-
-;; patterns for mixed mode floating point.
-;; Do not define patterns that utilize mixed mode arithmetic that result
-;; in narrowing the precision, because it loses accuracy, since the standard
-;; requires double rounding, whereas the 88000 instruction only rounds once.
-
-(define_expand "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(div:DF (match_operand:DF 1 "general_operand" "r,x")
-		(match_operand:DF 2 "general_operand" "r,x")))]
-  ""
-  "
-{
-  operands[1] = legitimize_operand (operands[1], DFmode);
-  if (real_power_of_2_operand (operands[2]))
-    {
-      union real_extract u;
-      bcopy (&CONST_DOUBLE_LOW (operands[2]), &u, sizeof u);
-      emit_insn (gen_muldf3 (operands[0], operands[1],
-			     CONST_DOUBLE_FROM_REAL_VALUE (1.0/u.d, DFmode)));
-      DONE;
-    }
-  else if (! register_operand (operands[2], DFmode))
-    operands[2] = force_reg (DFmode, operands[2]);
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
-		(float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
-  ""
-  "fdiv.dss %0,%1,%2"
-  [(set_attr "type" "dpdiv")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(div:DF (match_operand:DF 1 "register_operand" "r,x")
-		(float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
-  ""
-  "fdiv.dds %0,%1,%2"
-  [(set_attr "type" "dpdiv")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
-		(match_operand:DF 2 "register_operand" "r,x")))]
-  ""
-  "fdiv.dsd %0,%1,%2"
-  [(set_attr "type" "dpdiv")])
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r,x")
-	(div:SF (match_operand:SF 1 "register_operand" "r,x")
-		(match_operand:SF 2 "register_operand" "r,x")))]
-  ""
-  "fdiv.sss %0,%1,%2"
-  [(set_attr "type" "spdiv")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r,x")
-	(div:DF (match_operand:DF 1 "register_operand" "r,x")
-		(match_operand:DF 2 "register_operand" "r,x")))]
-  ""
-  "fdiv.ddd %0,%1,%2"
-  [(set_attr "type" "dpdiv")])
-
-;; - remainder instructions, don't define, since the hardware doesn't have any
-;; direct support, and GNU can synthesis them out of div/mul just fine.
-
-;;- load effective address, must come after add, so that we favor using
-;;  addu reg,reg,reg  instead of:  lda reg,reg,reg (addu doesn't require
-;;  the data unit), and also future 88k chips might not support unscaled
-;;  lda instructions.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "address_operand" "p"))]
-  "m88k_gp_threshold > 0 && symbolic_address_p (operands[1])"
-  "addu %0,%a1")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:HI 1 "address_operand" "p"))]
-  ""
-  "lda.h %0,%a1"
-  [(set_attr "type" "loada")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "address_operand" "p"))]
-  ""
-  "lda %0,%a1"
-  [(set_attr "type" "loada")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:DI 1 "address_operand" "p"))]
-  ""
-  "lda.d %0,%a1"
-  [(set_attr "type" "loada")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SF 1 "address_operand" "p"))]
-  ""
-  "lda %0,%a1"
-  [(set_attr "type" "loada")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:DF 1 "address_operand" "p"))]
-  ""
-  "lda.d %0,%a1"
-  [(set_attr "type" "loada")])
-
-;;- and instructions (with complement also)
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
-		(match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "and.c %0,%2,%1")
-
-;; If the operation is being performed on a 32-bit constant such that
-;; it cannot be done in one insn, do it in two.  We may lose a bit on
-;; CSE in pathological cases, but it seems better doing it this way.
-
-(define_expand "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(and:SI (match_operand:SI 1 "arith32_operand" "")
-		(match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int value = INTVAL (operands[2]);
-
-      if (! (SMALL_INTVAL (value)
-	     || (value & 0xffff0000) == 0xffff0000
-	     || (value & 0xffff) == 0xffff
-	     || (value & 0xffff) == 0
-	     || integer_ok_for_set (~value)))
-	{
-	  emit_insn (gen_andsi3 (operands[0], operands[1],
-				 GEN_INT (value | 0xffff)));
-	  operands[1] = operands[0];
-	  operands[2] = GEN_INT (value | 0xffff0000);
-	}
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(and:SI (match_operand:SI 1 "arith32_operand" "%r,r")
-		(match_operand:SI 2 "arith32_operand" "rIJL,rn")))]
-  ""
-  "* return output_and (operands);"
-  [(set_attr "type" "arith,marith")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
-		(match_operand:DI 2 "register_operand" "r")))]
-  ""
-  "and.c %d0,%d2,%d1\;and.c %0,%2,%1"
-  [(set_attr "type" "marith")])
-
-(define_insn "anddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI (match_operand:DI 1 "arith64_operand" "%r")
-		(match_operand:DI 2 "arith64_operand" "rn")))]
-  ""
-  "*
-{
-  rtx xoperands[10];
-
-  xoperands[0] = operand_subword (operands[0], 1, 0, DImode);
-  xoperands[1] = operand_subword (operands[1], 1, 0, DImode);
-  xoperands[2] = operand_subword (operands[2], 1, 0, DImode);
-
-  output_asm_insn (output_and (xoperands), xoperands);
-
-  operands[0] = operand_subword (operands[0], 0, 0, DImode);
-  operands[1] = operand_subword (operands[1], 0, 0, DImode);
-  operands[2] = operand_subword (operands[2], 0, 0, DImode);
-
-  return output_and (operands);
-}"
-  [(set_attr "type" "marith")
-   (set_attr "length" "4")]) ; length is 2, 3, or 4.
-
-;;- Bit set (inclusive or) instructions (with complement also)
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
-		(match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "or.c %0,%2,%1")
-
-(define_expand "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ior:SI (match_operand:SI 1 "arith32_operand" "")
-		(match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int value = INTVAL (operands[2]);
-
-      if (! (SMALL_INTVAL (value)
-	     || (value & 0xffff) == 0
-	     || integer_ok_for_set (value)))
-	{
-	  emit_insn (gen_iorsi3 (operands[0], operands[1],
-				 GEN_INT (value & 0xffff0000)));
-	  operands[1] = operands[0];
-	  operands[2] = GEN_INT (value & 0xffff);
-	}
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(ior:SI (match_operand:SI 1 "arith32_operand" "%r,r,r,r")
-		(match_operand:SI 2 "arith32_operand" "rI,L,M,n")))]
-  ""
-  "@
-   or %0,%1,%2
-   or.u %0,%1,%X2
-   set %0,%1,%s2
-   or.u %0,%1,%X2\;or %0,%0,%x2"
-  [(set_attr "type" "arith,arith,bit,marith")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ior:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
-		(match_operand:DI 2 "register_operand" "r")))]
-  ""
-  "or.c %d0,%d2,%d1\;or.c %0,%2,%1"
-  [(set_attr "type" "marith")])
-
-(define_insn "iordi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ior:DI (match_operand:DI 1 "arith64_operand" "%r")
-		(match_operand:DI 2 "arith64_operand" "rn")))]
-  ""
-  "*
-{
-  rtx xoperands[10];
-
-  xoperands[0] = operand_subword (operands[0], 1, 0, DImode);
-  xoperands[1] = operand_subword (operands[1], 1, 0, DImode);
-  xoperands[2] = operand_subword (operands[2], 1, 0, DImode);
-
-  output_asm_insn (output_ior (xoperands), xoperands);
-
-  operands[0] = operand_subword (operands[0], 0, 0, DImode);
-  operands[1] = operand_subword (operands[1], 0, 0, DImode);
-  operands[2] = operand_subword (operands[2], 0, 0, DImode);
-
-  return output_ior (operands);
-}"
-  [(set_attr "type" "marith")
-   (set_attr "length" "4")]) ; length is 2, 3, or 4.
-
-;;- xor instructions (with complement also)
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (xor:SI (match_operand:SI 1 "register_operand" "%r")
-			(match_operand:SI 2 "register_operand" "r"))))]
-  ""
-  "xor.c %0,%1,%2")
-
-(define_expand "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(xor:SI (match_operand:SI 1 "arith32_operand" "")
-		(match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int value = INTVAL (operands[2]);
-
-      if (! (SMALL_INTVAL (value)
-	     || (value & 0xffff) == 0))
-	{
-	  emit_insn (gen_xorsi3 (operands[0], operands[1],
-				 GEN_INT (value & 0xffff0000)));
-	  operands[1] = operands[0];
-	  operands[2] = GEN_INT (value & 0xffff);
-	}
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(xor:SI (match_operand:SI 1 "arith32_operand" "%r,r,r")
-		(match_operand:SI 2 "arith32_operand" "rI,L,n")))]
-  ""
-  "@
-   xor %0,%1,%2
-   xor.u %0,%1,%X2
-   xor.u %0,%1,%X2\;xor %0,%0,%x2"
-  [(set_attr "type" "arith,arith,marith")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(not:DI (xor:DI (match_operand:DI 1 "register_operand" "r")
-			(match_operand:DI 2 "register_operand" "r"))))]
-  ""
-  "xor.c %d0,%d1,%d2\;xor.c %0,%1,%2"
-  [(set_attr "type" "marith")])
-
-(define_insn "xordi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(xor:DI (match_operand:DI 1 "arith64_operand" "%r")
-		(match_operand:DI 2 "arith64_operand" "rn")))]
-  ""
-  "*
-{
-  rtx xoperands[10];
-
-  xoperands[0] = operand_subword (operands[0], 1, 0, DImode);
-  xoperands[1] = operand_subword (operands[1], 1, 0, DImode);
-  xoperands[2] = operand_subword (operands[2], 1, 0, DImode);
-
-  output_asm_insn (output_xor (xoperands), xoperands);
-
-  operands[0] = operand_subword (operands[0], 0, 0, DImode);
-  operands[1] = operand_subword (operands[1], 0, 0, DImode);
-  operands[2] = operand_subword (operands[2], 0, 0, DImode);
-
-  return output_xor (operands);
-}"
-  [(set_attr "type" "marith")
-   (set_attr "length" "4")]) ; length is 2, 3, or 4.
-
-;;- ones complement instructions
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "xor.c %0,%1,%#r0")
-
-(define_insn "one_cmpldi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(not:DI (match_operand:DI 1 "register_operand" "r")))]
-  ""
-  "xor.c %d0,%d1,%#r0\;xor.c %0,%1,%#r0"
-  [(set_attr "type" "marith")])
-
-;; Optimized special cases of shifting.
-;; Must precede the general case.
-
-;; @@ What about HImode shifted by 8?
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
-		     (const_int 24)))]
-  "! SCALED_ADDRESS_P (XEXP (operands[1], 0))"
-  "%V1ld.b\\t %0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
-		     (const_int 24)))]
-  "! SCALED_ADDRESS_P (XEXP (operands[1], 0))"
-  "%V1ld.bu\\t %0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
-		     (const_int 16)))]
-  "! SCALED_ADDRESS_P (XEXP (operands[1], 0))"
-  "%V1ld.h\\t %0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
-		     (const_int 16)))]
-  "! SCALED_ADDRESS_P (XEXP (operands[1], 0))"
-  "%V1ld.hu\\t %0,%1"
-  [(set_attr "type" "load")])
-
-;;- arithmetic shift instructions.
-
-;; @@ Do the optimized patterns with -1 get used?  Perhaps operand 1 should
-;; be arith32_operand?
-
-;; Use tbnd to support TARGET_TRAP_LARGE_SHIFT.
-(define_insn "tbnd"
-  [(trap_if (gtu (match_operand:SI 0 "register_operand" "r")
-		 (match_operand:SI 1 "arith_operand" "rI"))
-	    (const_int 7))]
-  ""
-  "tbnd %r0,%1"
-  [(set_attr "type" "weird")])
-
-;; Just in case the optimizer decides to fold away the test.
-(define_insn ""
-  [(trap_if (const_int 1) (const_int 7))]
-  ""
-  "tbnd %#r31,0"
-  [(set_attr "type" "weird")])
-
-(define_expand "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashift:SI (match_operand:SI 1 "register_operand" "")
-		   (match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if ((unsigned) INTVAL (operands[2]) > 31)
-	{
-	  if (TARGET_TRAP_LARGE_SHIFT)
-	    emit_insn (gen_tbnd (force_reg (SImode, operands[2]),
-				 GEN_INT (31)));
-	  else
-	    emit_move_insn (operands[0], const0_rtx);
-	  DONE;
-	}
-    }
-
-  else if (TARGET_TRAP_LARGE_SHIFT)
-    emit_insn (gen_tbnd (operands[2], GEN_INT (31)));
-
-  else if (TARGET_HANDLE_LARGE_SHIFT)
-    {
-      rtx reg = gen_reg_rtx (SImode);
-      emit_insn (gen_cmpsi (operands[2], GEN_INT (31)));
-      emit_insn (gen_sleu (reg));
-      emit_insn (gen_andsi3 (reg, operands[1], reg));
-      operands[1] = reg;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
-		   (match_operand:SI 2 "arith5_operand" "r,K")))]
-  ""
-  "@
-   mak %0,%1,%2
-   mak %0,%1,0<%2>"
-  [(set_attr "type" "bit")])
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if ((unsigned) INTVAL (operands[2]) > 31)
-	{
-	  if (TARGET_TRAP_LARGE_SHIFT)
-	    {
-	      emit_insn (gen_tbnd (force_reg (SImode, operands[2]),
-				   GEN_INT (31)));
-	      DONE;
-	    }
-	  else
-	    operands[2] = GEN_INT (31);
-	}
-    }
-
-  else if (TARGET_TRAP_LARGE_SHIFT)
-    emit_insn (gen_tbnd (operands[2], GEN_INT (31)));
-
-  else if (TARGET_HANDLE_LARGE_SHIFT)
-    {
-      rtx reg = gen_reg_rtx (SImode);
-      emit_insn (gen_cmpsi (operands[2], GEN_INT (31)));
-      emit_insn (gen_sgtu (reg));
-      emit_insn (gen_iorsi3 (reg, operands[2], reg));
-      operands[2] = reg;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
-		     (match_operand:SI 2 "arith5_operand" "r,K")))]
-  ""
-  "@
-   ext %0,%1,%2
-   ext %0,%1,0<%2>"
-  [(set_attr "type" "bit")])
-
-;;- logical shift instructions.  Logical shift left becomes arithmetic
-;; shift left.  
-
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if ((unsigned) INTVAL (operands[2]) > 31)
-	{
-	  if (TARGET_TRAP_LARGE_SHIFT)
-	    emit_insn (gen_tbnd (force_reg (SImode, operands[2]),
-				 GEN_INT (31)));
-	  else
-	    emit_move_insn (operands[0], const0_rtx);
-	  DONE;
-	}
-    }
-
-  else if (TARGET_TRAP_LARGE_SHIFT)
-    emit_insn (gen_tbnd (operands[2], GEN_INT (31)));
-
-  else if (TARGET_HANDLE_LARGE_SHIFT)
-    {
-      rtx reg = gen_reg_rtx (SImode);
-      emit_insn (gen_cmpsi (operands[2], GEN_INT (31)));
-      emit_insn (gen_sleu (reg));
-      emit_insn (gen_andsi3 (reg, operands[1], reg));
-      operands[1] = reg;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
-		     (match_operand:SI 2 "arith5_operand" "r,K")))]
-  ""
-  "@
-   extu %0,%1,%2
-   extu %0,%1,0<%2>"
-  [(set_attr "type" "bit")])
-
-;;- rotate instructions
-
-(define_expand "rotlsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(rotatert:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned) INTVAL (operands[2]) >= 32)
-    operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32);
-  else
-    {
-      rtx op = gen_reg_rtx (SImode);
-      emit_insn (gen_negsi2 (op, operands[2]));
-      operands[2] = op;
-    }
-}")
-
-(define_insn "rotrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(rotatert:SI (match_operand:SI 1 "register_operand" "r")
-		     (match_operand:SI 2 "arith_operand" "rI")))]
-  ""
-  "rot %0,%1,%2"
-  [(set_attr "type" "bit")])
-
-;; find first set.
-
-;; The ff1 instruction searches from the most significant bit while ffs
-;; searches from the least significant bit.  The bit index and treatment of
-;; zero also differ.  This amazing sequence was discovered using the GNU
-;; Superoptimizer.
-
-(define_insn "ffssi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,&r")
-	(ffs:SI (match_operand:SI 1 "register_operand" "0,r")))
-   (clobber (reg:CC 0))
-   (clobber (match_scratch:SI 2 "=r,X"))]
-  ""
-  "@
-   subu.co %2,%#r0,%1\;and %2,%2,%1\;addu.ci %2,%2,%2\;ff1 %0,%2
-   subu.co %0,%#r0,%1\;and %0,%0,%1\;addu.ci %0,%0,%0\;ff1 %0,%0"
-  [(set_attr "type" "marith")
-   (set_attr "length" "4")])
-
-;; Bit field instructions.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (const_int 32)
-			 (const_int 0)))]
-  ""
-  "or %0,%#r0,%1")
-
-(define_insn "extv"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "int5_operand" "")
-			 (match_operand:SI 3 "int5_operand" "")))]
-  ""
-  "*
-{
-  operands[4] = GEN_INT ((32 - INTVAL (operands[2])) - INTVAL (operands[3]));
-  return \"ext %0,%1,%2<%4>\";  /* <(32-%2-%3)> */
-}"
-  [(set_attr "type" "bit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (const_int 32)
-			 (const_int 0)))]
-  ""
-  "or %0,%#r0,%1")
-
-(define_insn "extzv"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "int5_operand" "")
-			 (match_operand:SI 3 "int5_operand" "")))]
-  ""
-  "*
-{
-  operands[4] = GEN_INT ((32 - INTVAL (operands[2])) - INTVAL (operands[3]));
-  return \"extu %0,%1,%2<%4>\";  /* <(32-%2-%3)> */
-}"
-  [(set_attr "type" "bit")])
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-			 (match_operand:SI 1 "int5_operand" "")
-			 (match_operand:SI 2 "int5_operand" ""))
-	(const_int 0))]
-  ""
-  "*
-{
-  operands[3] = GEN_INT ((32 - INTVAL (operands[1])) - INTVAL (operands[2]));
-  return \"clr %0,%0,%1<%3>\";  /* <(32-%1-%2)> */
-}"
-  [(set_attr "type" "bit")])
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-			 (match_operand:SI 1 "int5_operand" "")
-			 (match_operand:SI 2 "int5_operand" ""))
-	(const_int -1))]
-  ""
-  "*
-{
-  operands[3] = GEN_INT ((32 - INTVAL (operands[1])) - INTVAL (operands[2]));
-  return \"set %0,%0,%1<%3>\";  /* <(32-%1-%2)> */
-}"
-  [(set_attr "type" "bit")])
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-			 (match_operand:SI 1 "int5_operand" "")
-			 (match_operand:SI 2 "int5_operand" ""))
-	(match_operand:SI 3 "int32_operand" "n"))]
-  ""
-  "*
-{
-  int value = INTVAL (operands[3]);
-
-  if (INTVAL (operands[1]) < 32)
-    value &= (1 << INTVAL (operands[1])) - 1;
-
-  operands[2] = GEN_INT (32 - (INTVAL(operands[1]) + INTVAL(operands[2])));
-
-  value <<= INTVAL (operands[2]);
-  operands[3] = GEN_INT (value);
-
-  if (SMALL_INTVAL (value))
-    return \"clr %0,%0,%1<%2>\;or %0,%0,%3\";
-  else if ((value & 0x0000ffff) == 0)
-    return \"clr %0,%0,%1<%2>\;or.u %0,%0,%X3\";
-  else
-    return \"clr %0,%0,%1<%2>\;or.u %0,%0,%X3\;or %0,%0,%x3\";
-}"
-  [(set_attr "type" "marith")
-   (set_attr "length" "3")]) ; may be 2 or 3.
-
-;; negate insns
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
-  ""
-  "subu %0,%#r0,%1")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r,x")
-	(float_truncate:SF (neg:DF (match_operand:DF 1 "register_operand" "r,x"))))]
-  ""
-  "@
-   fsub.ssd %0,%#r0,%1
-   fsub.ssd %0,%#x0,%1"
-  [(set_attr "type" "dpadd")])
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=&r,r")
-	(neg:DF (match_operand:DF 1 "register_operand" "r,0")))]
-  ""
-  "@
-   xor.u %0,%1,0x8000\;or %d0,%#r0,%d1
-   xor.u %0,%0,0x8000"
-  [(set_attr "type" "marith,arith")])
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(neg:SF (match_operand:SF 1 "register_operand" "r")))]
-  ""
-  "xor.u %0,%1,0x8000")
-
-;; absolute value insns for floating-point (integer abs can be done using the
-;; machine-independent sequence).
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "=&r,r")
-	(abs:DF (match_operand:DF 1 "register_operand" "r,0")))]
-  ""
-  "@
-   and.u %0,%1,0x7fff\;or %d0,%#r0,%d1
-   and.u %0,%0,0x7fff"
-  [(set_attr "type" "marith,arith")])
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(abs:SF (match_operand:SF 1 "register_operand" "r")))]
-  ""
-  "and.u %0,%1,0x7fff")
-
-;; Subroutines of "casesi".
-
-;; Operand 0 is index
-;; operand 1 is the minimum bound
-;; operand 2 is the maximum bound - minimum bound + 1
-;; operand 3 is CODE_LABEL for the table;
-;; operand 4 is the CODE_LABEL to go to if index out of range.
-
-(define_expand "casesi"
-  ;; We don't use these for generating the RTL, but we must describe
-  ;; the operands here.
-  [(match_operand:SI 0 "general_operand" "")
-   (match_operand:SI 1 "immediate_operand" "")
-   (match_operand:SI 2 "immediate_operand" "")
-   (match_operand 3 "" "")
-   (match_operand 4 "" "")]
-  ""
-  "
-{
-  register rtx index_diff = gen_reg_rtx (SImode);
-  register rtx low = GEN_INT (-INTVAL (operands[1]));
-  register rtx label = gen_rtx (LABEL_REF, VOIDmode, operands[3]);
-  register rtx base;
-
-  if (! CASE_VECTOR_INSNS)
-    /* These instructions are likely to be scheduled and made loop invariant.
-       This decreases the cost of the dispatch at the expense of the default
-       case.  */
-    base = force_reg (SImode, memory_address_noforce (SImode, label));
-
-  /* Compute the index difference and handle the default case.  */
-  emit_insn (gen_addsi3 (index_diff,
-			 force_reg (SImode, operands[0]),
-			 ADD_INT (low) ? low : force_reg (SImode, low)));
-  emit_insn (gen_cmpsi (index_diff, operands[2]));
-  /* It's possible to replace this branch with sgtu/iorsi3 and adding a -1
-     entry to the table.  However, that doesn't seem to win on the m88110.  */
-  emit_jump_insn (gen_bgtu (operands[4]));
-
-  if (CASE_VECTOR_INSNS)
-    /* Call the jump that will branch to the appropriate case.  */
-    emit_jump_insn (gen_casesi_enter (label, index_diff, operands[3]));
-  else
-    /* Load the table entry and jump to it.  */
-    emit_jump_insn (gen_casesi_jump (gen_reg_rtx (SImode), base, index_diff, operands[3]));
-
-  /* Claim that flow drops into the table so it will be adjacent by not
-     emitting a barrier.  */
-  DONE;
-}")
-
-(define_expand "casesi_jump"
-  [(set (match_operand:SI 0 "" "")
-	(mem:SI (plus:SI (match_operand:SI 1 "" "")
-			 (mult:SI (match_operand:SI 2 "" "")
-				  (const_int 4)))))
-   (parallel [(set (pc) (match_dup 0))
-              (use (label_ref (match_operand 3 "" "")))])]
-  ""
-  "")
-
-(define_insn ""
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmp%. %0"
-  [(set_attr "type" "jump")])
-
-;; The bsr.n instruction is directed to the END of the table.  See
-;; ASM_OUTPUT_CASE_END.
-
-(define_insn "casesi_enter"
-  [(set (pc) (match_operand 0 "" ""))
-   (use (match_operand:SI 1 "register_operand" "r"))
-   ;; The USE here is so that at least one jump-insn will refer to the label,
-   ;; to keep it alive in jump_optimize.
-   (use (label_ref (match_operand 2 "" "")))
-   (clobber (reg:SI 1))]
-  ""
-  "*
-{
-  if (flag_delayed_branch)
-    return \"bsr.n %0e\;lda %#r1,%#r1[%1]\";
-  m88k_case_index = REGNO (operands[1]);
-  return \"bsr %0e\";
-}"
-  [(set_attr "type" "weird")
-   (set_attr "length" "3")]) ; Including the "jmp r1".
-
-;;- jump to subroutine
-(define_expand "call"
-  [(parallel [(call (match_operand:SI 0 "" "")
-		    (match_operand 1 "" ""))
-	      (clobber (reg:SI 1))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM
-      && ! call_address_operand (XEXP (operands[0], 0), SImode))
-    operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
-			   force_reg (Pmode, XEXP (operands[0], 0)));
-}")
-
-(define_insn ""
-  [(parallel [(call (mem:SI (match_operand:SI 0 "call_address_operand" "rQ"))
-		    (match_operand 1 "" ""))
-	      (clobber (reg:SI 1))])]
-  ""
-  "* return output_call (operands, operands[0]);"
-  [(set_attr "type" "call")])
-
-(define_expand "call_value"
-  [(parallel [(set (match_operand 0 "register_operand" "")
-		   (call (match_operand:SI 1 "" "")
-			 (match_operand 2 "" "")))
-	      (clobber (reg:SI 1))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == MEM
-      && ! call_address_operand (XEXP (operands[1], 0), SImode))
-    operands[1] = gen_rtx (MEM, GET_MODE (operands[1]),
-			   force_reg (Pmode, XEXP (operands[1], 0)));
-}")
-
-(define_insn ""
-  [(parallel [(set (match_operand 0 "register_operand" "=r")
-		   (call (mem:SI
-			  (match_operand:SI 1 "call_address_operand" "rQ"))
-			 (match_operand 2 "" "")))
-	      (clobber (reg:SI 1))])]
-  ""
-  "* return output_call (operands, operands[1]);"
-  [(set_attr "type" "call")])
-
-;; Nop instruction and others
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "ff0 %#r0,%#r0"
-  [(set_attr "type" "bit")])
-
-(define_insn "return"
-  [(return)]
-  "reload_completed"
-  "jmp%. %#r1"
-  [(set_attr "type" "jump")])
-
-(define_expand "prologue"
-  [(const_int 0)]
-  ""
-  "m88k_expand_prologue (); DONE;")
-
-(define_expand "epilogue"
-  [(return)]
-  "! null_prologue ()"
-  "m88k_expand_epilogue ();")
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  ""
-  [(set_attr "length" "0")])
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
-  ""
-  "jmp%. %0"
-  [(set_attr "type" "jump")])
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "br%. %l0"
-  [(set_attr "type" "jump")])
-
-;; This insn is used for some loop tests, typically loops reversed when
-;; strength reduction is used.  It is actually created when the instruction
-;; combination phase combines the special loop test.  Since this insn
-;; is both a jump insn and has an output, it must deal with its own
-;; reloads, hence the `m' constraints.  The `!' constraints direct reload
-;; to not choose the register alternatives in the event a reload is needed.
-
-(define_expand "decrement_and_branch_until_zero"
-  [(parallel [(set (pc)
-		   (if_then_else
-		    (match_operator 0 "relop_no_unsigned"
-				    [(match_operand:SI 1 "register_operand" "")
-				     (const_int 0)])
-		    (label_ref (match_operand 2 "" ""))
-		    (pc)))
-	      (set (match_dup 1)
-		   (plus:SI (match_dup 1)
-			    (match_operand:SI 3 "add_operand" "")))
-	      (clobber (match_scratch:SI 4 ""))
-	      (clobber (match_scratch:SI 5 "=X,X,&r,&r"))])]
-  ""
-  "")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 0 "relop_no_unsigned"
-			 [(match_operand:SI 1 "register_operand" "+!r,!r,m,m")
-			  (const_int 0)])
-	  (label_ref (match_operand 2 "" ""))
-	  (pc)))
-   (set (match_dup 1)
-	(plus:SI (match_dup 1)
-		 (match_operand:SI 3 "add_operand" "rI,J,rI,J")))
-   (clobber (match_scratch:SI 4 "=X,X,&r,&r"))
-   (clobber (match_scratch:SI 5 "=X,X,&r,&r"))]
-  "find_reg_note (insn, REG_NONNEG, 0)"
-  "@
-   bcnd.n %B0,%1,%2\;addu %1,%1,%3
-   bcnd.n %B0,%1,%2\;subu %1,%1,%n3
-   ld %4,%1\;addu %5,%4,%3\;bcnd.n %B0,%4,%2\;st %5,%1
-   ld %4,%1\;subu %5,%4,%n3\;bcnd.n %B0,%4,%2\;st %5,%1"
-  [(set_attr "type" "weird")
-   (set_attr "length" "2,2,4,4")])
-
-;; Special insn to serve as the last insn of a define_expand.  This insn
-;; will generate no code.
-
-(define_expand "dummy"
-  [(set (match_operand 0 "" "") (match_dup 0))]
-  ""
-  "")
diff --git a/gcc/config/m88k/sysv3.h b/gcc/config/m88k/sysv3.h
deleted file mode 100755
index ef35189..0000000
--- a/gcc/config/m88k/sysv3.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Motorola m88100 running the AT&T/Unisoft/Motorola V.3 reference port.
-   Copyright (C) 1990, 1991, 1997 Free Software Foundation, Inc.
-   Contributed by Ray Essick (ressick@mot.com)
-   Enhanced by Tom Wood (Tom_Wood@NeXT.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "m88k/m88k.h"
-
-/* Default switches */
-#undef	TARGET_DEFAULT
-#define TARGET_DEFAULT	(MASK_CHECK_ZERO_DIV	| \
-			 MASK_OCS_DEBUG_INFO	| \
-			 MASK_OCS_FRAME_POSITION)
-
-/* Macros to be automatically defined.  */
-#undef	CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dm88000 -Dm88k -Dunix -DsysV88 -D__CLASSIFY_TYPE__=2 -Asystem(unix) -Asystem(svr3) -Acpu(m88k) -Amachine(m88k)"
-
-/* Override svr3.h to link with ?crt0.o instead of ?crt1.o and ?crtn.o.
-   From arul@sdsu.edu.  */
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC \
-   "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} crtbegin.o%s"
-
-/* Profiled libraries live in a different directory but keep the same
-   names other than that.  arul@sdsu.edu says -lg is always needed.  */
-#undef	LIB_SPEC
-#define LIB_SPEC "%{p:-L/lib/libp}%{pg:%{!p:-L/lib/libp}} -lg -lc crtend.o%s"
-
-/* Hot version of the profiler that uses r10 to pass the address of
-   the counter.  the _gcc_mcount routine knows not to screw with
-   the parameter registers.
-
-   DG/UX does this; i wrote a gnu-c/88k specific version and put it
-   in libgcc2.c -- RBE; this macro knows about the leading underscore
-   convention.  */
-#undef	FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
-  output_function_profiler (FILE, LABELNO, "_gcc_mcount", 0)
-
-/* Various other changes that we want to have in place without
-   too many changes to the m88k.h file.  */
-#undef	USE_LIBG
-#define	USE_LIBG
-
-/* Define a few machine-specific details of the implementation of
-   constructors.  */
-
-/* Although the .init section is used, it is not automatically invoked.  */
-#define INVOKE__main
-
-/* State that atexit exists so __do_global_ctors will register
-   __do_global_dtors.  */
-#define HAVE_ATEXIT
-
-#define CTOR_LIST_BEGIN	    		\
-  asm (INIT_SECTION_ASM_OP);		\
-  asm ("\tsubu\t r31,r31,16");	/* (STACK_BOUNDARY / BITS_PER_UNIT) == 16 */ \
-  asm ("\tst\t r0,r31,32");	/* REG_PARM_STACK_SPACE (0) == 32 */
-#define CTOR_LIST_END
-
-/* ASM_OUTPUT_CONSTRUCTOR outputs code into the .init section to push the
-   address of the constructor.  This becomes the body of __do_global_ctors
-   in crtstuff.c.  r13 is a temporary register.  */
-#undef	ASM_OUTPUT_CONSTRUCTOR
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    init_section ();							\
-    fprintf (FILE, "\tor.u\t r13,r0,hi16(");				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, ")\n\tor\t r13,r13,lo16(");				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, ")\n\tsubu\t r31,r31,%d\n\tst\t r13,r31,%d\n",	\
-	     STACK_BOUNDARY / BITS_PER_UNIT, REG_PARM_STACK_SPACE (0));	\
-  } while (0)
-
-#undef	DO_GLOBAL_CTORS_BODY
-#define DO_GLOBAL_CTORS_BODY						\
-do {									\
-  func_ptr *__CTOR_LIST__ = __builtin_alloca (1), *p;			\
-  for (p = __CTOR_LIST__ + 4; *p; p += 4)				\
-    (*p) ();								\
-} while (0)
-
-#define DTOR_LIST_BEGIN							\
-  asm (FINI_SECTION_ASM_OP);						\
-  func_ptr __DTOR_LIST__[4] = { (func_ptr) (-1), (func_ptr) (-1),	\
-				(func_ptr) (-1), (func_ptr) (-1) }
-#define DTOR_LIST_END						  	\
-  asm (FINI_SECTION_ASM_OP);						\
-  func_ptr __DTOR_END__[4] = { (func_ptr) 0, (func_ptr) 0,		\
-			       (func_ptr) 0, (func_ptr) 0 }  
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  The table is constructed in the .fini section
-   so that an explicit linker script is not required.  The complication
-   is that this section is padded with NOP instructions and to either
-   8 or 16 byte alignment depending on the specific system.  A clever
-   way to avoid trouble is to output a block of 16 bytes where the
-   extra words are known values (-1).  */
-#undef	ASM_OUTPUT_DESTRUCTOR
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)	\
-  do {						\
-    register int i;				\
-    fini_section ();				\
-    fprintf (FILE, "\t%s\t ", ASM_LONG);	\
-    assemble_name (FILE,NAME);			\
-    fprintf (FILE, "\n");			\
-    for (i = 1; i < 4; i++)			\
-      fprintf (FILE, "\t%s\t -1\n", ASM_LONG);	\
-    } while (0)
-
-/* Walk the list looking for the terminating zero and ignoring all values of
-   -1.  */
-#undef	DO_GLOBAL_DTORS_BODY
-#define DO_GLOBAL_DTORS_BODY			\
-  do {						\
-    int i;					\
-    for (i = 0; __DTOR_LIST__[i] != 0; i++)	\
-      if (((int *)__DTOR_LIST__)[i] != -1)	\
-	__DTOR_LIST__[i] ();			\
-  } while (0)					
-
-#undef INITIALIZE_TRAMPOLINE 
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 40)), FNADDR); \
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 36)), CXT); \
-  emit_call_insn (gen_call (gen_rtx (MEM, SImode,			\
-				     gen_rtx (SYMBOL_REF, Pmode,	\
-					     "__enable_execute_stack")), \
-			   const0_rtx));				\
-}
diff --git a/gcc/config/m88k/sysv4.h b/gcc/config/m88k/sysv4.h
deleted file mode 100755
index ff6dc78..0000000
--- a/gcc/config/m88k/sysv4.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Motorola 88100 in an 88open ABI environment.
-   Copyright (C) 1990, 1991 Free Software Foundation, Inc.
-
-   Written by Ron Guilmette (rfg@netcom.com).
-   Contributed to FSF by Network Computing Devices.
-
-   Other contributions by Vince Guarna (vguarna@urbana.mcd.mot.com),
-   Ray Essick (essick@i88.isc.com), Wilson Tien (wtien@urbana.mcd.mot.com),
-   and Tom Wood (Tom_Wood@NeXT.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* DWARF_DEBUGGING_INFO defined in svr4.h.  */
-
-#ifndef NO_BUGS
-#define AS_BUG_DOT_LABELS
-#define AS_BUG_POUND_TYPE
-#endif
-
-#include "svr4.h"
-#include "m88k/m88k.h"
-
-/* Identify the compiler.  */
-#undef  VERSION_INFO1
-#define VERSION_INFO1 "88open ABI, "
-
-/* Default switches */
-#undef	TARGET_DEFAULT
-#define TARGET_DEFAULT	(MASK_CHECK_ZERO_DIV | \
-			 MASK_OCS_DEBUG_INFO | \
-			 MASK_SVR4)
-
-/* Cpp spec.  These pre-assertions are needed for SVR4 as they occur
-   often in the system header files.  __svr4__ is our extension.  */
-
-#undef  CPP_PREDEFINES
-#define CPP_PREDEFINES \
-  "-Dm88000 -Dm88k -Dunix -D__svr4__ -Amachine(m88k) -Acpu(m88k) -Asystem(unix) -Asystem(svr4)"
-
-/* For the AT&T SVR4 port, the function is _mcount.  */
-#undef	FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO) \
-  output_function_profiler (FILE, LABELNO, "_mcount", 1)
-
-/* Override svr4.h and m88k.h.  */
-#undef	INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP "section\t.init,\"xa\",#progbits"
-#undef	FINI_SECTION_ASM_OP
-#define FINI_SECTION_ASM_OP "section\t.fini,\"xa\",#progbits"
-
-/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
- 
-   Note that we want to give these sections the SHF_WRITE attribute
-   because these sections will actually contain data (i.e. tables of
-   addresses of functions in the current root executable or shared library
-   file) and, in the case of a shared library, the relocatable addresses
-   will have to be properly resolved/relocated (and then written into) by
-   the dynamic linker when it actually attaches the given shared library
-   to the executing process.  (Note that on SVR4, you may wish to use the
-   `-z text' option to the ELF linker, when building a shared library, as
-   an additional check that you are doing everything right.  But if you do
-   use the `-z text' option when building a shared library, you will get
-   errors unless the .ctors and .dtors sections are marked as writable
-   via the SHF_WRITE attribute.)  */
- 
-#undef	CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP	"section\t.ctors,\"aw\""
-#undef	DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP	"section\t.dtors,\"aw\""
diff --git a/gcc/config/m88k/t-bug b/gcc/config/m88k/t-bug
deleted file mode 100755
index a5e71dd..0000000
--- a/gcc/config/m88k/t-bug
+++ /dev/null
@@ -1,12 +0,0 @@
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
-	   moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
-	   moveDI96x.asm
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
-	$(srcdir)/config/m88k/m88k-move.sh
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
diff --git a/gcc/config/m88k/t-dgux b/gcc/config/m88k/t-dgux
deleted file mode 100755
index cced6b1..0000000
--- a/gcc/config/m88k/t-dgux
+++ /dev/null
@@ -1,26 +0,0 @@
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
-	   moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
-	   moveDI96x.asm
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
-	$(srcdir)/config/m88k/m88k-move.sh
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
-
-# In a coff environment, a link script is required for ctors and dtors.
-m88kdgux.ld: $(srcdir)/config/m88k/dgux.ld
-	rm -f m88kdgux.ld; cp $(srcdir)/config/m88k/dgux.ld ./m88kdgux.ld
-
-# A bcs crtbegin.o is needed since bcs does not  
-# increment the stack pointer in the init section as elf does 
-bcscrtbegin.o:     crtstuff.c $(GCC_PASSES) $(CONFIG_H) gbl-ctors.h
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) -DCRT_BEGIN -DBCS \
-	-finhibit-size-directive -fno-inline-functions \
-	-g0 -c $(srcdir)/crtstuff.c -o bcscrtbegin.o 
-
-# Build libgcc.a, crtbegin.o, and crtend.o as bcs objects
-GCC_FOR_TARGET = PATH=/usr/sde/m88kbcs/usr/bin/:/usr/bin TARGET_BINARY_INTERFACE=m88kbcs ./xgcc -B./ -msvr3 -D_M88KBCS_TARGET -mno-ocs-debug-info
diff --git a/gcc/config/m88k/t-dgux-gas b/gcc/config/m88k/t-dgux-gas
deleted file mode 100755
index c7368c3..0000000
--- a/gcc/config/m88k/t-dgux-gas
+++ /dev/null
@@ -1,17 +0,0 @@
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
-	   moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
-	   moveDI96x.asm
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
-	$(srcdir)/config/m88k/m88k-move.sh
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
-T_CPPFLAGS = -DUSE_GAS
-
-# In a coff environment, a link script is required.
-m88kdgux.ld: $(srcdir)/config/m88k/dgux.ld
-	rm -f m88kdgux.ld; cp $(srcdir)/config/m88k/dgux.ld ./m88kdgux.ld
diff --git a/gcc/config/m88k/t-dguxbcs b/gcc/config/m88k/t-dguxbcs
deleted file mode 100755
index c42a9bf..0000000
--- a/gcc/config/m88k/t-dguxbcs
+++ /dev/null
@@ -1,28 +0,0 @@
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
-	   moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
-	   moveDI96x.asm
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
-	$(srcdir)/config/m88k/m88k-move.sh
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
-
-# In a coff environment, a link script is required for ctors and dtors.
-m88kdgux.ld: $(srcdir)/config/m88k/dgux.ld
-	rm -f m88kdgux.ld; cp $(srcdir)/config/m88k/dgux.ld ./m88kdgux.ld
-
-# A bcs crtbegin.o is needed since bcs does not  
-# increment the stack pointer in the init section as elf does 
-bcscrtbegin.o:     crtstuff.c $(GCC_PASSES) $(CONFIG_H) gbl-ctors.h
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) -DCRT_BEGIN -DBCS \
-	-finhibit-size-directive -fno-inline-functions \
-	-g0 -c $(srcdir)/crtstuff.c -o bcscrtbegin.o 
-
-# Build libgcc.a, crtbegin.o, and crtend.o as bcs objects
-GCC_FOR_TARGET = PATH=/usr/sde/m88kbcs/usr/bin/:/usr/bin TARGET_BINARY_INTERFACE=m88kbcs ./xgcc -B./ -msvr3 -D_M88KBCS_TARGET -mno-ocs-debug-info
-
-T_CFLAGS = -O -D_M88KBCS_TARGET
diff --git a/gcc/config/m88k/t-luna b/gcc/config/m88k/t-luna
deleted file mode 100755
index dce5f22..0000000
--- a/gcc/config/m88k/t-luna
+++ /dev/null
@@ -1,12 +0,0 @@
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
-	   moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
-	   moveDI96x.asm
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
-	$(srcdir)/config/m88k/m88k-move.sh -no-tdesc
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
diff --git a/gcc/config/m88k/t-luna-gas b/gcc/config/m88k/t-luna-gas
deleted file mode 100755
index 1d6692a..0000000
--- a/gcc/config/m88k/t-luna-gas
+++ /dev/null
@@ -1,13 +0,0 @@
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
-	   moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
-	   moveDI96x.asm
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
-	bash $(srcdir)/config/m88k/m88k-move.sh -no-tdesc
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
-T_CPPFLAGS = -DUSE_GAS
diff --git a/gcc/config/m88k/t-m88k b/gcc/config/m88k/t-m88k
deleted file mode 100755
index a5e71dd..0000000
--- a/gcc/config/m88k/t-m88k
+++ /dev/null
@@ -1,12 +0,0 @@
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
-	   moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
-	   moveDI96x.asm
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
-	$(srcdir)/config/m88k/m88k-move.sh
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
diff --git a/gcc/config/m88k/t-m88k-gas b/gcc/config/m88k/t-m88k-gas
deleted file mode 100755
index dc436e1..0000000
--- a/gcc/config/m88k/t-m88k-gas
+++ /dev/null
@@ -1,18 +0,0 @@
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
-	   moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
-	   moveDI96x.asm
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
-	$(srcdir)/config/m88k/m88k-move.sh
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
-T_CPPFLAGS = -DUSE_GAS
-
-# For svr4 we build crtbegin.o and crtend.o which serve to add begin and
-# end labels to the .ctors and .dtors section when we link using gcc.
-
-EXTRA_PARTS=crtbegin.o crtend.o
diff --git a/gcc/config/m88k/t-sysv4 b/gcc/config/m88k/t-sysv4
deleted file mode 100755
index 3f90cd5..0000000
--- a/gcc/config/m88k/t-sysv4
+++ /dev/null
@@ -1,22 +0,0 @@
-# Specify how to create the *.asm files
-
-MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \
-	   moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \
-	   moveDI96x.asm
-
-# Use the -abi option for version 03.00 syntax.
-
-$(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh
-	$(srcdir)/config/m88k/m88k-move.sh -abi
-
-LIB2FUNCS_EXTRA = $(MOVE_ASM)
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
-
-# We need to use -fPIC when we are using gcc to compile the routines in
-# crtstuff.c.  This is only really needed when we are going to use gcc/g++
-# to produce a shared library, but since we don't know ahead of time when
-# we will be doing that, we just always use -fPIC when compiling the
-# routines in crtstuff.c.
-
-CRTSTUFF_T_CFLAGS=-fPIC
diff --git a/gcc/config/m88k/tekXD88.h b/gcc/config/m88k/tekXD88.h
deleted file mode 100755
index 5b37dea..0000000
--- a/gcc/config/m88k/tekXD88.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Tektronix XD88 UTekV 3.2e   (svr3 derived from UniSoft System V/88)
-
-   Copyright (C) 1993 Free Software Foundation, Inc.
-   Contributed by Kaveh R. Ghazi (ghazi@caip.rutgers.edu)  2/22/93.
-
-   This file is part of GNU CC.
-   
-   GNU CC is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-   
-   GNU CC is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-   
-   You should have received a copy of the GNU General Public License
-   along with GNU CC; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.
-   */
-
-#include "m88k/sysv3.h"
-
-/* Don't output structure tag names when it causes a forward reference.
-   Symptom:
-   Error messages like
-   as: "/usr/tmp/cca22733.s": cannot reduce symbol table, unused symbols remain
-   when compiling some programs.
-   example program (C++): struct bad { bad(); }; bad::bad() {}
-
-   This problem seems to have gone away, perhaps with release 3.6 of the O/S
-   from Dolphin.  */
-/* #undef SDB_ALLOW_FORWARD_REFERENCES */
-/* I don't know if this SDB thing is needed or not --KRG */
-
-
-/* Use T_ARG as T_VOID.  T_VOID is not defined in <syms.h> as it should be.  */
-#define T_VOID T_ARG
-
-
-/* The bundled ld program needs link editor directives which normally
-   reside in /lib/default.ld.  We'll pass our own copy during the link
-   phase because additional information about extra sections must be added
-   so that gcc generated files will link properly.
-   --KRG.
-   */
-#undef LINK_SPEC
-#define LINK_SPEC "gcc.ld%s"
diff --git a/gcc/config/m88k/tekXD88.ld b/gcc/config/m88k/tekXD88.ld
deleted file mode 100755
index 86c6522..0000000
--- a/gcc/config/m88k/tekXD88.ld
+++ /dev/null
@@ -1,39 +0,0 @@
-/* gcc.ld - COFF linker directives for the Tektronix XD88.
-
-   This file is part of GNU CC.
-   
-   GNU CC is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-   
-   GNU CC is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-   
-   You should have received a copy of the GNU General Public License
-   along with GNU CC; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.
-
-
-   This file does the following:
-	- Sets VIRTUAL addr of .text to 0x10200 
-	  Sets FILE addr of .text to 0x200 (BLOCK directive)
-   	- Depending on size of .text section rounds up to next
-	  4 MG boundary, adds (size of .text and vaddr of .text) mod 64K
-	  This is to handle sections larger than 4 MG.
-*/
-
-SECTIONS {
-  .text 0x10200 BLOCK (0x200):
-    { *(.init) *(.text) *(.rodata) *(.tdesc) *(.fini)}
-
-  GROUP BIND( ((SIZEOF(.text) / 0x400000 * 0x400000) + 0x400000) +
-    ((SIZEOF(.text) + ADDR(.text)) % 0x10000) ) :
-    {
-      .data : { }
-      .bss  : { }
-    }
-}
diff --git a/gcc/config/m88k/x-dgux b/gcc/config/m88k/x-dgux
deleted file mode 100755
index f2c55a7..0000000
--- a/gcc/config/m88k/x-dgux
+++ /dev/null
@@ -1,6 +0,0 @@
-CC = gcc
-BISONFLAGS = -l
-USER_H =  $(EXTRA_HEADERS) $(LANG_EXTRA_HEADERS)
-
-STMP_FIXPROTO = 
-X_CFLAGS = -O -mstandard -mlegend
diff --git a/gcc/config/m88k/x-dguxbcs b/gcc/config/m88k/x-dguxbcs
deleted file mode 100755
index 8baf0ca..0000000
--- a/gcc/config/m88k/x-dguxbcs
+++ /dev/null
@@ -1,4 +0,0 @@
-CC = gcc
-BISONFLAGS = -l
-USER_H =  $(EXTRA_HEADERS) $(LANG_EXTRA_HEADERS)
-STMP_FIXPROTO = 
diff --git a/gcc/config/m88k/x-dolph b/gcc/config/m88k/x-dolph
deleted file mode 100755
index b31a7a9..0000000
--- a/gcc/config/m88k/x-dolph
+++ /dev/null
@@ -1,19 +0,0 @@
-# Use link editor directives to make NULL pointers point to 
-# invalid addresses.
-
-EXTRA_PARTS=crtbegin.o crtend.o gcc.ld
-
-gcc.ld: $(srcdir)/config/m88k/dolphin.ld
-	rm -f gcc.ld; cp $(srcdir)/config/m88k/dolphin.ld gcc.ld
-
-# Green Hills C on Dolphin UNIX System V/88 Release 3.2  Version 3.6/5.86 does
-# not provide alloca. It does not harm to have it defined on version 3.8.alfa
-# even though it's not needed there.
-
-ALLOCA=alloca.o
-
-# Under DolphinOS 3.8.alfa, /bin/cc defines __GNUC__, but not __m88k__, 
-# causing gdstarg.h to fail. Defining __m88k__ does probably not hurt on
-# DolphinOS 3.6.
-
-X_CFLAGS =-D__m88k__
diff --git a/gcc/config/m88k/x-sysv3 b/gcc/config/m88k/x-sysv3
deleted file mode 100755
index 3ee9067..0000000
--- a/gcc/config/m88k/x-sysv3
+++ /dev/null
@@ -1,7 +0,0 @@
-# this is m88k/x-sysv3
-
-# native compiler does not provide alloca
-
-ALLOCA = alloca.o
-
-# end m88k/x-sysv3
diff --git a/gcc/config/m88k/x-sysv4 b/gcc/config/m88k/x-sysv4
deleted file mode 100755
index dd24287..0000000
--- a/gcc/config/m88k/x-sysv4
+++ /dev/null
@@ -1,10 +0,0 @@
-# Problems in early version of the assembler have been fixed (-DNO_BUGS).
-# There are peculiar problems with the include files that require __STDC__
-# to be defined as 0.  This results in sigset_t being defined which otherwise
-# results in a problem when <wait.h> includes <siginfo.h>.
-
-X_CFLAGS = -DNO_BUGS -D__STDC__=0
-
-# The CI5 compiler does not provide alloca.
-
-ALLOCA = alloca.o
diff --git a/gcc/config/m88k/x-tekXD88 b/gcc/config/m88k/x-tekXD88
deleted file mode 100755
index b8b4a2f..0000000
--- a/gcc/config/m88k/x-tekXD88
+++ /dev/null
@@ -1,12 +0,0 @@
-# Install the custom Tektronix XD88 link editor directives file.
-EXTRA_PARTS=crtbegin.o crtend.o gcc.ld
-
-gcc.ld: $(srcdir)/config/m88k/tekXD88.ld
-	rm -f gcc.ld; cp $(srcdir)/config/m88k/tekXD88.ld ./gcc.ld
-
-# Green Hills C on the Tektronix XD88 does not provide alloca.
-ALLOCA=alloca.o
-
-# rc is cleaner, but the ar program sometimes crashes.
-# This is a workaround.
-AR_FLAGS=qc
diff --git a/gcc/config/m88k/xm-m88k.h b/gcc/config/m88k/xm-m88k.h
deleted file mode 100755
index b330f59..0000000
--- a/gcc/config/m88k/xm-m88k.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Configuration for GNU compiler.
-   Motorola m88100 in an 88open OCS/BCS environment.
-   Copyright (C) 1988, 89, 90, 91, 93, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_WORDS_BIG_ENDIAN
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* The 88open BCS (and ABI) environment doesn't support BSD features
-   (vfork, getrusage), so use USG.  The Omron Luna/88k is BSD though.  */
-#ifndef luna88k
-#ifndef USG
-#define USG
-#endif
-#define NO_SYS_SIGLIST
-#endif
-
-/* If not compiled with GNU C, use the C alloca */
-#ifndef __GNUC__
-#define USE_C_ALLOCA
-#endif
-
-/* For DG/UX, the best size is different.  */
-#ifdef __DGUX__
-#define OBSTACK_CHUNK_SIZE (8192-16)
-#endif
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
diff --git a/gcc/config/m88k/xm-sysv3.h b/gcc/config/m88k/xm-sysv3.h
deleted file mode 100755
index 84110d7..0000000
--- a/gcc/config/m88k/xm-sysv3.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Configuration for GNU C-compiler.
-   Motorola m88100 running the AT&T/Unisoft/Motorola V.3 reference port.
-   Copyright (C) 1990, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define R_OK 4
-#define W_OK 2
-#define X_OK 1
-#define F_OK 0
-
-/* for the emacs version of alloca */
-#define STACK_DIRECTION -1
-
-/* We need POSIX/XOPEN symbols; otherwise make check will fail.  */
-#define ADD_MISSING_POSIX 1
-#define ADD_MISSING_XOPEN 1
diff --git a/gcc/config/mips/abi64.h b/gcc/config/mips/abi64.h
deleted file mode 100755
index 3af89dc..0000000
--- a/gcc/config/mips/abi64.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/* Definitions of target machine for GNU compiler.  64 bit ABI support.
-   Copyright (C) 1994, 1995, 1996, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Macros to implement the 64 bit ABI.  This file is meant to be included
-   after mips.h.  */
-
-#undef SUBTARGET_TARGET_OPTIONS
-#define SUBTARGET_TARGET_OPTIONS\
-  { "abi=", &mips_abi_string	},
-
-#undef STACK_BOUNDARY
-#define STACK_BOUNDARY \
-  ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
-   ? 64 : 128)
-
-#undef MIPS_STACK_ALIGN
-#define MIPS_STACK_ALIGN(LOC)						\
-  ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)	\
-   ? ((LOC) + 7) & ~7							\
-   : ((LOC) + 15) & ~15)
-
-#undef GP_ARG_LAST
-#define GP_ARG_LAST  ((mips_abi == ABI_32 || mips_abi == ABI_O64)	\
-		      ? GP_REG_FIRST + 7 : GP_REG_FIRST + 11)
-#undef FP_ARG_LAST
-#define FP_ARG_LAST  ((mips_abi == ABI_32 || mips_abi == ABI_O64)	\
-		      ? FP_REG_FIRST + 15 : FP_REG_FIRST + 19)
-
-#undef SUBTARGET_CONDITIONAL_REGISTER_USAGE
-#define SUBTARGET_CONDITIONAL_REGISTER_USAGE \
-{									\
-  /* fp20-23 are now caller saved.  */					\
-  if (mips_abi == ABI_64)						\
-    {									\
-      int regno;							\
-      for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++) \
-	call_used_regs[regno] = 1;					\
-    }									\
-  /* odd registers from fp21 to fp31 are now caller saved.  */		\
-  if (mips_abi == ABI_N32)						\
-    {									\
-      int regno;							\
-      for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2) \
-	call_used_regs[regno] = 1;					\
-    }									\
-}
-
-#undef MAX_ARGS_IN_REGISTERS
-#define MAX_ARGS_IN_REGISTERS ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
-			       ? 4 : 8)
-
-#undef REG_PARM_STACK_SPACE
-#define REG_PARM_STACK_SPACE(FNDECL) 					 \
-  ((mips_abi == ABI_32 || mips_abi == ABI_O64)				 \
-   ? (MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
-   : 0)
-
-#define FUNCTION_ARG_PADDING(MODE, TYPE)				\
-  (! BYTES_BIG_ENDIAN							\
-   ? upward								\
-   : (((MODE) == BLKmode						\
-       ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST		\
-	  && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
-       : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY			\
-	  && (mips_abi == ABI_32					\
-	      || mips_abi == ABI_O64					\
-	      || mips_abi == ABI_EABI					\
-	      || GET_MODE_CLASS (MODE) == MODE_INT)))			\
-      ? downward : upward))
-
-#undef RETURN_IN_MEMORY
-#define RETURN_IN_MEMORY(TYPE)						\
-  ((mips_abi == ABI_32 || mips_abi == ABI_O64)				\
-   ? TYPE_MODE (TYPE) == BLKmode					\
-   : (int_size_in_bytes (TYPE)						\
-      > (mips_abi == ABI_EABI ? 2 * UNITS_PER_WORD : 16)))
-
-extern struct rtx_def *mips_function_value ();
-#undef FUNCTION_VALUE
-#define FUNCTION_VALUE(VALTYPE, FUNC)	mips_function_value (VALTYPE, FUNC)
-
-/* For varargs, we must save the current argument, because it is the fake
-   argument va_alist, and will need to be converted to the real argument.
-   For stdarg, we do not need to save the current argument, because it
-   is a real argument.  */
-#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL)	\
-{ int mips_off = (! current_function_varargs) && (! (CUM).last_arg_fp);	\
-  int mips_fp_off = (! current_function_varargs) && ((CUM).last_arg_fp); \
-  if (((mips_abi != ABI_32 && mips_abi != ABI_O64)			\
-       && (CUM).arg_words < MAX_ARGS_IN_REGISTERS - mips_off)		\
-      || (mips_abi == ABI_EABI						\
-	  && ! TARGET_SOFT_FLOAT					\
-	  && (CUM).fp_arg_words < MAX_ARGS_IN_REGISTERS - mips_fp_off))	\
-    {									\
-      int mips_save_gp_regs =						\
-        MAX_ARGS_IN_REGISTERS - (CUM).arg_words - mips_off;		\
-      int mips_save_fp_regs =						\
-        (mips_abi != ABI_EABI ? 0					\
-	 : MAX_ARGS_IN_REGISTERS - (CUM).fp_arg_words - mips_fp_off);	\
-									\
-      if (mips_save_gp_regs < 0)					\
-	mips_save_gp_regs = 0;						\
-      if (mips_save_fp_regs < 0)					\
-	mips_save_fp_regs = 0;						\
-      PRETEND_SIZE = ((mips_save_gp_regs * UNITS_PER_WORD)		\
-		      + (mips_save_fp_regs * UNITS_PER_FPREG));		\
-									\
-      if (! (NO_RTL))							\
-	{								\
-	  if ((CUM).arg_words < MAX_ARGS_IN_REGISTERS - mips_off)	\
-	    {								\
-	      rtx ptr, mem;						\
-	      if (mips_abi != ABI_EABI)					\
-		ptr = virtual_incoming_args_rtx;			\
-	      else							\
-		ptr = plus_constant (virtual_incoming_args_rtx,		\
-				     - (mips_save_gp_regs		\
-					* UNITS_PER_WORD));		\
-	      mem = gen_rtx (MEM, BLKmode, ptr);			\
-	      /* va_arg is an array access in this case, which causes	\
-		 it to get MEM_IN_STRUCT_P set.  We must set it here	\
-		 so that the insn scheduler won't assume that these	\
-		 stores can't possibly overlap with the va_arg loads.  */ \
-	      if (mips_abi != ABI_EABI && BYTES_BIG_ENDIAN)		\
-	        MEM_SET_IN_STRUCT_P (mem, 1);				\
-	      move_block_from_reg					\
-		((CUM).arg_words + GP_ARG_FIRST + mips_off,		\
-		 mem,							\
-		 mips_save_gp_regs,					\
-		 mips_save_gp_regs * UNITS_PER_WORD);			\
-	    }								\
-	  if (mips_abi == ABI_EABI					\
-	      && ! TARGET_SOFT_FLOAT					\
-	      && (CUM).fp_arg_words < MAX_ARGS_IN_REGISTERS - mips_fp_off) \
-	    {								\
-	      enum machine_mode mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode; \
-	      int size = GET_MODE_SIZE (mode);				\
-	      int off;							\
-	      int i;							\
-	      /* We can't use move_block_from_reg, because it will use	\
-                 the wrong mode.  */					\
-	      off = - (mips_save_gp_regs * UNITS_PER_WORD);		\
-	      if (! TARGET_SINGLE_FLOAT)				\
-	        off &= ~ 7;						\
-	      if (! TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)		\
-		off -= (mips_save_fp_regs / 2) * size;			\
-	      else							\
-		off -= mips_save_fp_regs * size;			\
-	      for (i = 0; i < mips_save_fp_regs; i++)			\
-		{							\
-		  rtx tem =						\
-		    gen_rtx (MEM, mode,					\
-			     plus_constant (virtual_incoming_args_rtx,	\
-					    off));			\
-		  emit_move_insn (tem,					\
-				  gen_rtx (REG, mode,			\
-					   ((CUM).fp_arg_words		\
-					    + FP_ARG_FIRST		\
-					    + i				\
-					    + mips_fp_off)));		\
-		  off += size;						\
-		  if (! TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)		\
-		    ++i;						\
-		}							\
-	    }								\
-	}								\
-    }									\
-}
-
-#define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
-
-/* A C expression that indicates when an argument must be passed by
-   reference.  If nonzero for an argument, a copy of that argument is
-   made in memory and a pointer to the argument is passed instead of the
-   argument itself.  The pointer is passed in whatever way is appropriate
-   for passing a pointer to that type.  */
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)		\
-  (mips_abi == ABI_EABI							\
-   && function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED))
-
-/* A C expression that indicates when it is the called function's
-   responsibility to make a copy of arguments passed by invisible
-   reference.  Normally, the caller makes a copy and passes the
-   address of the copy to the routine being called.  When
-   FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller
-   does not make a copy.  Instead, it passes a pointer to the "live"
-   value.  The called function must not modify this value.  If it can
-   be determined that the value won't be modified, it need not make a
-   copy; otherwise a copy must be made.
-
-   ??? The MIPS EABI says that the caller should copy in ``K&R mode.''
-   I don't know how to detect that here, since flag_traditional is not
-   a back end flag.  */
-#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED)		\
-  (mips_abi == ABI_EABI && (NAMED)					\
-   && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
-
-/* Define LONG_MAX correctly for all users.  We need to handle 32 bit EABI,
-   64 bit EABI, N32, and N64 as possible defaults.  The checks performed here
-   are the same as the checks in override_options in mips.c that determines
-   whether MASK_LONG64 will be set.
-
-   This does not handle inappropriate options or ununusal option
-   combinations.  */
-
-#undef LONG_MAX_SPEC
-#if ((MIPS_ABI_DEFAULT == ABI_64) || ((MIPS_ABI_DEFAULT == ABI_EABI) && ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_64BIT)))
-#define LONG_MAX_SPEC \
-  "%{!mabi=n32:%{!mno-long64:%{!mgp32:%{!mips1:%{!mips2:-D__LONG_MAX__=9223372036854775807L}}}}}"
-#else
-  /* CYGNUS LOCAL gavin */
-#define LONG_MAX_SPEC \
-  "%{mabi=64:-D__LONG_MAX__=9223372036854775807L} \
-   %{mabi=eabi:%{!mips1:%{!mips2:-D__LONG_MAX__=9223372036854775807L}}} \
-   %{mlong64:-D__LONG_MAX__=9223372036854775807L} \
-   %{mgp64:-D__LONG_MAX__=9223372036854775807L}"
-#endif
-
-/* ??? Unimplemented stuff follows.  */
-
-/* ??? Add support for 16 byte/128 bit long doubles here when
-   mips_abi != ABI32.  */
-
-/* ??? Make main return zero if user did not specify return value.  */
-
-/* ??? Add support for .interfaces section, so as to get linker warnings
-   when stdarg functions called without prototype in scope?  */
-
-/* ??? Could optimize structure passing by putting the right register rtx
-   into the field decl, so that if we use the field, we can take the value from
-   a register instead of from memory.  */
-
-
-
diff --git a/gcc/config/mips/big.h b/gcc/config/mips/big.h
deleted file mode 100755
index a165b09..0000000
--- a/gcc/config/mips/big.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* CYGNUS LOCAL: Entire file.  */
-
-/* Definitions of target machine for GNU compiler.
-   Little-endian flavor.
-   Copyright (c) 1997 Cygnus Support Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
-#define MULTILIB_ENDIAN_DEFAULT "EB"
diff --git a/gcc/config/mips/bsd-4.h b/gcc/config/mips/bsd-4.h
deleted file mode 100755
index c2aee83..0000000
--- a/gcc/config/mips/bsd-4.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Definitions of target machine for GNU compiler.  MIPS RISC-OS BSD version.
-   Copyright (C) 1991 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MIPS_BSD43
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
--Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
-
-#define STANDARD_INCLUDE_DIR "/bsd43/usr/include"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
--systype /bsd43/"
-		    
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}"
-
-#define MACHINE_TYPE "RISC-OS BSD Mips"
-
-/* Generate calls to memcpy, etc., not bcopy, etc.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Override defaults for finding the MIPS tools.  */
-#define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/"
diff --git a/gcc/config/mips/bsd-5.h b/gcc/config/mips/bsd-5.h
deleted file mode 100755
index f97af5e..0000000
--- a/gcc/config/mips/bsd-5.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   MIPS RISC-OS, 5.0 BSD version.
-   Copyright (C) 1991 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MIPS_BSD43
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
--Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
-
-#define STANDARD_INCLUDE_DIR "/bsd43/usr/include"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \
--systype /bsd43/"
-		    
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}"
-
-#define MACHINE_TYPE "RISC-OS BSD Mips"
-
-/* Generate calls to memcpy, etc., not bcopy, etc.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Override defaults for finding the MIPS tools.  */
-#define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/"
-
-#include "mips/mips.h"
-
-/* Some assemblers have a bug that causes backslash escaped chars in .ascii
-   to be misassembled, so we just completely avoid it.  */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)			\
-do {							\
-  unsigned char *s;					\
-  int i;						\
-  for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++)	\
-    {							\
-      if ((i % 8) == 0)					\
-	fputs ("\n\t.byte\t", (FILE));			\
-      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
-    }							\
-  fputs ("\n", (FILE));					\
-} while (0)
diff --git a/gcc/config/mips/cross64.h b/gcc/config/mips/cross64.h
deleted file mode 100755
index 4462e5e..0000000
--- a/gcc/config/mips/cross64.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Configuration for an Irix 5 host and Irix 6 target using SGI's cross64
-   package.  */
-
-#define STANDARD_INCLUDE_DIR "/usr/cross64/usr/include"
-#undef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "/usr/cross64/usr/bin/"
-#undef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/cross64/usr/lib/lib64/"
-
-/* Must add TOOLROOT to the environment, or else the assembler will not
-   work.  */
-#define INIT_ENVIRONMENT	\
-  "TOOLROOT=/usr/cross64"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{mips1:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}} \
-   %{mips2:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}} \
-   %{!mips1:%{!mips2:%{pg:/usr/cross64/usr/lib64/mips4/gcrt1.o}		    \
-   %{!pg:%{p:/usr/cross64/usr/lib64/mips4/mcrt1.o			    \
-     /usr/cross64/usr/lib64/mips4/libprof1.a}				    \
-   %{!p:/usr/cross64/usr/lib64/mips4/crt1.o}}}}"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC \
-  "%{mips1:crtn.o%s}%{mips2:crtn.o%s}%{!mips1:%{!mips2:/usr/cross64/usr/lib64/mips4/crtn.o}}"
-
-#undef LINK_SPEC
-#define LINK_SPEC "\
--64 -_SYSTYPE_SVR4 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -call_shared -no_unresolved}}} \
-%{!mips1:%{!mips2:-L/usr/cross64/usr/lib64/mips4 -L/usr/cross64/usr/lib64}}"
diff --git a/gcc/config/mips/dec-bsd.h b/gcc/config/mips/dec-bsd.h
deleted file mode 100755
index 126353b..0000000
--- a/gcc/config/mips/dec-bsd.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Definitions for DECstation running BSD as target machine for GNU compiler.
-   Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define DECSTATION
-
-#ifndef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D__ANSI_COMPAT \
--DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -Dbsd4_4 -Dhost_mips -Dmips \
--Dunix -D_mips -D_unix -D_host_mips -D_MIPSEL -D_R3000 \
--Asystem(unix) -Asystem(bsd) -Amachine(mips)"
-#endif
-
-/* Always uses GNU ld.  */
-#ifndef LINK_SPEC
-#define LINK_SPEC "%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3}"
-#endif
-
-#define LIB_SPEC ""
-#define STARTFILE_SPEC ""
-
-#ifndef MACHINE_TYPE
-#define MACHINE_TYPE "DECstation running BSD 4.4"
-#endif
-
-#define TARGET_DEFAULT MASK_GAS
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#include "mips/mips.h"
-
-/* Since gas and gld are standard on 4.4 BSD, we don't need these */
-#undef MD_EXEC_PREFIX
-#undef MD_STARTFILE_PREFIX
-#undef ASM_FINAL_SPEC
-#undef LIB_SPEC
-#undef STARTFILE_SPEC
-
diff --git a/gcc/config/mips/dec-osf1.h b/gcc/config/mips/dec-osf1.h
deleted file mode 100755
index ee7e787..0000000
--- a/gcc/config/mips/dec-osf1.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Definitions of target machine for GNU compiler.  DECstation (OSF/1) version.
-   Copyright (C) 1992, 1996, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define DEC_OSF1
-
-#define CPP_PREDEFINES "\
--D__ANSI_COMPAT -DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD \
--Dbsd4_2 -Dhost_mips -Dmips -Dosf -Dunix \
--Asystem(unix) -Asystem(xpg4) -Acpu(mips) -Amachine(mips)"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}"
-
-#include "mips/ultrix.h"
-#include "mips/mips.h"
-
-/* Specify size_t and wchar_t types.  */
-#undef	SIZE_TYPE
-#undef	WCHAR_TYPE
-#undef	WCHAR_TYPE_SIZE
-
-#define SIZE_TYPE	"long unsigned int"
-#define WCHAR_TYPE	"short unsigned int"
-#define WCHAR_TYPE_SIZE SHORT_TYPE_SIZE
-
-#undef SUBTARGET_CPP_SIZE_SPEC
-#define SUBTARGET_CPP_SIZE_SPEC "\
-%{mlong64:-D__PTRDIFF_TYPE__=long\\ int} \
-%{!mlong64:-D__PTRDIFF_TYPE__=int}"
-
-/* turn off collect2 COFF support, since ldfcn now has elf declaration */
-#undef OBJECT_FORMAT_COFF
-
-#undef MACHINE_TYPE
-#define MACHINE_TYPE "DECstation running DEC OSF/1"
diff --git a/gcc/config/mips/ecoff.h b/gcc/config/mips/ecoff.h
deleted file mode 100755
index dcc00a4..0000000
--- a/gcc/config/mips/ecoff.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Definitions of target machine for GNU compiler.  MIPS version with
-   GOFAST floating point library.
-   Copyright (C) 1994, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* US Software GOFAST library support.  */
-#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS
-
-#include "mips/mips.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR3000 -D_mips -D_MIPSEB -D_R3000"
-
-/* Use memcpy, et. al., rather than bcopy.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Don't assume anything about startfiles.  The linker script will load the
-   appropriate startfiles.  */
-#define STARTFILE_SPEC ""
diff --git a/gcc/config/mips/ecoffl.h b/gcc/config/mips/ecoffl.h
deleted file mode 100755
index 9fe90e8..0000000
--- a/gcc/config/mips/ecoffl.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Little endian MIPS
-   version with GOFAST floating point library.
-   Copyright (C) 1994, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This is a little endian version of ecoff.h.  */
-
-#define TARGET_ENDIAN_DEFAULT 0
-
-#include "gofast.h"
-#include "mips/ecoff.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR3000 -D_mips -D_MIPSEL -D_R3000"
diff --git a/gcc/config/mips/elf.h b/gcc/config/mips/elf.h
deleted file mode 100755
index 8603047..0000000
--- a/gcc/config/mips/elf.h
+++ /dev/null
@@ -1,352 +0,0 @@
-/* Definitions of target machine for GNU compiler.  MIPS R3000 version with
-   GOFAST floating point library.
-   Copyright (C) 1994, 1997, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Use ELF.  */
-#define OBJECT_FORMAT_ELF
-
-/* Until we figure out what MIPS ELF targets normally use, just do
-   stabs in ELF.  */
-#ifndef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-#endif
-
-/* Mostly like ECOFF.  */
-#include "gofast.h"
-#include "mips/ecoff.h"
-
-/* We need to use .esize and .etype instead of .size and .type to
-   avoid conflicting with ELF directives.  */
-#undef PUT_SDB_SIZE
-#define PUT_SDB_SIZE(a)					\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t.esize\t%d;", (a));	\
-} while (0)
-
-#undef PUT_SDB_TYPE
-#define PUT_SDB_TYPE(a)					\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a));	\
-} while (0)
-
-/* Biggest alignment supported by the object file format of this
-   machine.  Use this macro to limit the alignment which can be
-   specified using the `__attribute__ ((aligned (N)))' construct.  If
-   not defined, the default value is `BIGGEST_ALIGNMENT'.  */
-
-#define MAX_OFILE_ALIGNMENT (32768*8)
-
-/* A C statement to output something to the assembler file to switch to section
-   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
-   NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
-   define this macro in such cases.  */
-
-#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC) \
-do {								\
-  extern FILE *asm_out_text_file;				\
-  if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL)		\
-    fprintf (asm_out_text_file, "\t.section %s,\"ax\",@progbits\n", (NAME)); \
-  else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC))	\
-    fprintf (F, "\t.section %s,\"a\",@progbits\n", (NAME));	\
-  else								\
-    fprintf (F, "\t.section %s,\"aw\",@progbits\n", (NAME));	\
-} while (0)
-
-/* The following macro defines the format used to output the second
-   operand of the .type assembler directive.  Different svr4 assemblers
-   expect various different forms for this operand.  The one given here
-   is just a default.  You may need to override it in your machine-
-   specific tm.h file (depending upon the particulars of your assembler).  */
-
-#define TYPE_OPERAND_FMT        "@%s"
-
-/* Define the strings used for the special svr4 .type and .size directives.
-   These strings generally do not vary from one system running svr4 to
-   another, but if a given system (e.g. m88k running svr) needs to use
-   different pseudo-op names for these, they may be overridden in the
-   file which includes this one.  */
-
-#undef TYPE_ASM_OP
-#undef SIZE_ASM_OP
-#define TYPE_ASM_OP	".type"
-#define SIZE_ASM_OP	".size"
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as
-   uninitialized global data.  If not defined, and neither
-   `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
-   uninitialized global data will be output in the data section if
-   `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
-   used.  */
-#ifndef BSS_SECTION_ASM_OP
-#define BSS_SECTION_ASM_OP	".section\t.bss"
-#endif
-
-/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
-   separate, explicit argument.  If you define this macro, it is used
-   in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
-   handling the required alignment of the variable.  The alignment is
-   specified as the number of bits.
-
-   Try to use function `asm_output_aligned_bss' defined in file
-   `varasm.c' when defining this macro. */
-#ifndef ASM_OUTPUT_ALIGNED_BSS
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
-#endif
-
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare an object properly.  */
-
-#undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
-    putc ('\n', FILE);							\
-    size_directive_output = 0;						\
-    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-      {									\
-	size_directive_output = 1;					\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-	fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));	\
-      }									\
-    mips_declare_object (FILE, NAME, "", ":\n", 0);			\
-  } while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#undef ASM_FINISH_DECLARE_OBJECT
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
-	 assemble_name (FILE, name);					 \
-	 fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL)));  \
-       }								 \
-   } while (0)
-
-#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)                            \
- do { fputc ( '\t', FILE);                                            \
-      assemble_name (FILE, LABEL1);                                   \
-      fputs ( " = ", FILE);                                           \
-      assemble_name (FILE, LABEL2);                                   \
-      fputc ( '\n', FILE);                                            \
- } while (0)
-
-/* Note about .weak vs. .weakext
-   The mips native assemblers support .weakext, but not .weak.
-   mips-elf gas supports .weak, but not .weakext.
-   mips-elf gas has been changed to support both .weak and .weakext,
-   but until that support is generally available, the 'if' below
-   should serve. */
-
-#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0)
-#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE)	\
- do {						\
-  if (TARGET_GAS)                               \
-      fputs ("\t.weak\t", FILE);		\
-  else                                          \
-      fputs ("\t.weakext\t", FILE);		\
-  assemble_name (FILE, NAME);			\
-  if (VALUE)					\
-    {						\
-      fputc (' ', FILE);			\
-      assemble_name (FILE, VALUE);		\
-    }						\
-  fputc ('\n', FILE);				\
- } while (0)
-
-#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
-#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
-#define UNIQUE_SECTION(DECL,RELOC)					   \
-do {									   \
-  int len, size, sec;							   \
-  char *name, *string, *prefix;						   \
-  static char *prefixes[4][2] = {					   \
-    { ".text.", ".gnu.linkonce.t." },					   \
-    { ".rodata.", ".gnu.linkonce.r." },					   \
-    { ".data.", ".gnu.linkonce.d." },					   \
-    { ".sdata.", ".gnu.linkonce.s." }					   \
-  };									   \
-									   \
-  name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL));		   \
-  size = int_size_in_bytes (TREE_TYPE (decl));				   \
-									   \
-  /* Determine the base section we are interested in:			   \
-     0=text, 1=rodata, 2=data, 3=sdata.  */				   \
-  if (TREE_CODE (DECL) == FUNCTION_DECL)				   \
-    sec = 0;								   \
-  else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)			   \
-      && TREE_CODE (decl) == STRING_CST					   \
-      && !flag_writable_strings)					   \
-    {									   \
-      /* For embedded position independent code, put constant strings	   \
-	 in the text section, because the data section is limited to	   \
-	 64K in size.  For mips16 code, put strings in the text		   \
-	 section so that a PC relative load instruction can be used to	   \
-	 get their address.  */						   \
-      sec = 0;								   \
-    }									   \
-  else if (TARGET_EMBEDDED_DATA)					   \
-    {									   \
-      /* For embedded applications, always put an object in read-only data \
-	 if possible, in order to reduce RAM usage.  */			   \
-									   \
-      if (DECL_READONLY_SECTION (DECL, RELOC))				   \
-	sec = 1;							   \
-      else if (size > 0 && size <= mips_section_threshold)		   \
-	sec = 3;							   \
-      else								   \
-	sec = 2;							   \
-    }									   \
-  else									   \
-    {									   \
-      /* For hosted applications, always put an object in small data if	   \
-	 possible, as this gives the best performance.  */		   \
-									   \
-      if (size > 0 && size <= mips_section_threshold)			   \
-	sec = 3;							   \
-      else if (DECL_READONLY_SECTION (DECL, RELOC))			   \
-	sec = 1;							   \
-      else								   \
-	sec = 2;							   \
-    }									   \
-									   \
-  prefix = prefixes[sec][DECL_ONE_ONLY (DECL)];				   \
-  len = strlen (name) + strlen (prefix);				   \
-  string = alloca (len + 1);						   \
-  sprintf (string, "%s%s", prefix, name);				   \
-									   \
-  DECL_SECTION_NAME (DECL) = build_string (len, string);		   \
-} while (0)
-
-/* Support the ctors/dtors and other sections.  */
- 
-/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
- 
-   Note that we want to give these sections the SHF_WRITE attribute
-   because these sections will actually contain data (i.e. tables of
-   addresses of functions in the current root executable or shared library
-   file) and, in the case of a shared library, the relocatable addresses
-   will have to be properly resolved/relocated (and then written into) by
-   the dynamic linker when it actually attaches the given shared library
-   to the executing process.  (Note that on SVR4, you may wish to use the
-   `-z text' option to the ELF linker, when building a shared library, as
-   an additional check that you are doing everything right.  But if you do
-   use the `-z text' option when building a shared library, you will get
-   errors unless the .ctors and .dtors sections are marked as writable
-   via the SHF_WRITE attribute.)  */
-
-#define CTORS_SECTION_ASM_OP    "\t.section\t.ctors,\"aw\""
-#define DTORS_SECTION_ASM_OP    "\t.section\t.dtors,\"aw\""
- 
-/* A list of other sections which the compiler might be "in" at any
-   given time.  */
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_sdata, in_rdata, in_ctors, in_dtors
- 
-#define INVOKE__main
-#define NAME__MAIN "__gccmain"
-#define SYMBOL__MAIN __gccmain
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS                                         \
-  SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \
-  SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP) \
-  SECTION_FUNCTION_TEMPLATE(ctors_section, in_ctors, CTORS_SECTION_ASM_OP) \
-  SECTION_FUNCTION_TEMPLATE(dtors_section, in_dtors, DTORS_SECTION_ASM_OP)
-
-#define SECTION_FUNCTION_TEMPLATE(FN, ENUM, OP)                               \
-void FN ()                                                            \
-{                                                                     \
-  if (in_section != ENUM)                                             \
-    {                                                                 \
-      fprintf (asm_out_file, "%s\n", OP);                             \
-      in_section = ENUM;                                              \
-    }                                                                 \
-}
-
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)                             \
-  do {                                                                \
-    ctors_section ();                                                 \
-    fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word");     \
-    assemble_name (FILE, NAME);                                       \
-    fprintf (FILE, "\n");                                             \
-  } while (0)
-
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)                              \
-  do {                                                                \
-    dtors_section ();                                                 \
-    fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word");     \
-    assemble_name (FILE, NAME);                                       \
-    fprintf (FILE, "\n");                                             \
-  } while (0)
-
-#define CTOR_LIST_BEGIN                                 \
-asm (CTORS_SECTION_ASM_OP);                             \
-func_ptr __CTOR_LIST__[1] = { (func_ptr) (-1) }
- 
-#define CTOR_LIST_END                                   \
-asm (CTORS_SECTION_ASM_OP);                             \
-func_ptr __CTOR_END__[1] = { (func_ptr) 0 };
- 
-#define DTOR_LIST_BEGIN                                 \
-asm (DTORS_SECTION_ASM_OP);                             \
-func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) }
-
-#define DTOR_LIST_END                                   \
-asm (DTORS_SECTION_ASM_OP);                             \
-func_ptr __DTOR_END__[1] = { (func_ptr) 0 };
-
-/* Don't set the target flags, this is done by the linker script */
-#undef LIB_SPEC
-#define LIB_SPEC ""
-
-#undef  STARTFILE_SPEC
-#define STARTFILE_SPEC "crtbegin%O%s crt0%O%s"
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend%O%s"
diff --git a/gcc/config/mips/elf5400.h b/gcc/config/mips/elf5400.h
deleted file mode 100755
index 1a6d9fc..0000000
--- a/gcc/config/mips/elf5400.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* CYGNUS LOCAL: Entire file.  */
-
-/* Definitions of target machine for GNU compiler.
-   NEC VR5400 version.
-   Copyright (c) 1997 Cygnus Support Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#define MIPS_CPU_STRING_DEFAULT "VR5400"
-
-#define MIPS_ABI_DEFAULT ABI_EABI
-
-#include "mips/elf64.h"
-#include "mips/abi64.h"
-
-#undef MULTILIB_DEFAULTS
-#define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT }
-
-#undef CPP_PREDEFINES
-#if TARGET_ENDIAN_DEFAULT == 0
-#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR5400 -D_mips -D_MIPSEL -D_R5400"
-#else
-#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR5400 -D_mips -D_MIPSEB -D_R5400"
-#endif
-
-#undef SUBTARGET_CPP_SIZE_SPEC
-#define SUBTARGET_CPP_SIZE_SPEC "\
--D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int"
-
-#undef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC "\
-%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}}\
-%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}}"
-
-#undef MIPS_ISA_DEFAULT
-#define MIPS_ISA_DEFAULT 4
diff --git a/gcc/config/mips/elf64.h b/gcc/config/mips/elf64.h
deleted file mode 100755
index 4c72334..0000000
--- a/gcc/config/mips/elf64.h
+++ /dev/null
@@ -1,354 +0,0 @@
-/* Definitions of target machine for GNU compiler.  MIPS R4000 version with
-   GOFAST floating point library.
-   Copyright (C) 1994, 1995, 1996, 1997, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define OBJECT_FORMAT_ELF
-
-/* Default to -mips3.  */
-#define TARGET_DEFAULT MASK_FLOAT64|MASK_64BIT
-#define MIPS_ISA_DEFAULT 3
-
-/* Until we figure out what MIPS ELF targets normally use, just do
-   stabs in ELF.  */
-#ifndef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-#endif
-
-/* US Software GOFAST library support.  */
-#include "gofast.h"
-#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS
-
-#include "mips/mips.h"
-
-/* This must be done after mips.h, because mips.h defines
-   TARGET_ENDIAN_DEFAULT.  */
-#undef MULTILIB_DEFAULTS
-#if TARGET_ENDIAN_DEFAULT == 0
-#define MULTILIB_DEFAULTS { "EL", "mips3" }
-#else
-#define MULTILIB_DEFAULTS { "EB", "mips3" }
-#endif
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4000 -D_mips -D_MIPSEB -D_R4000"
-
-/* I would rather put this in CPP_PREDEFINES, but the gcc driver
-   doesn't handle -U options in CPP_PREDEFINES.  */
-#undef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC "\
-%{!mips1:%{!mips2:-U__mips -D__mips=3 %{!mgp32: -D__mips64}}}"
-
-/* Use memcpy, et. al., rather than bcopy.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Biggest alignment supported by the object file format of this
-   machine.  Use this macro to limit the alignment which can be
-   specified using the `__attribute__ ((aligned (N)))' construct.  If
-   not defined, the default value is `BIGGEST_ALIGNMENT'.  */
-
-#define MAX_OFILE_ALIGNMENT (32768*8)
-
-/* We need to use .esize and .etype instead of .size and .type to
-   avoid conflicting with ELF directives.  */
-#undef PUT_SDB_SIZE
-#define PUT_SDB_SIZE(a)					\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t.esize\t%d;", (a));	\
-} while (0)
-
-#undef PUT_SDB_TYPE
-#define PUT_SDB_TYPE(a)					\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a));	\
-} while (0)
-
-/* A C statement to output something to the assembler file to switch to section
-   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
-   NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
-   define this macro in such cases.  */
-
-#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC) \
-do {								\
-  extern FILE *asm_out_text_file;				\
-  if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL)		\
-    fprintf (asm_out_text_file, "\t.section %s,\"ax\",@progbits\n", (NAME)); \
-  else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC))	\
-    fprintf (F, "\t.section %s,\"a\",@progbits\n", (NAME));	\
-  else								\
-    fprintf (F, "\t.section %s,\"aw\",@progbits\n", (NAME));	\
-} while (0)
-
-/* The following macro defines the format used to output the second
-   operand of the .type assembler directive.  Different svr4 assemblers
-   expect various different forms for this operand.  The one given here
-   is just a default.  You may need to override it in your machine-
-   specific tm.h file (depending upon the particulars of your assembler).  */
-
-#define TYPE_OPERAND_FMT        "@%s"
-
-/* Define the strings used for the special svr4 .type and .size directives.
-   These strings generally do not vary from one system running svr4 to
-   another, but if a given system (e.g. m88k running svr) needs to use
-   different pseudo-op names for these, they may be overridden in the
-   file which includes this one.  */
-
-#undef TYPE_ASM_OP
-#undef SIZE_ASM_OP
-#define TYPE_ASM_OP	".type"
-#define SIZE_ASM_OP	".size"
-
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare an object properly.  */
-
-#undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
-    putc ('\n', FILE);							\
-    size_directive_output = 0;						\
-    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-      {									\
-	size_directive_output = 1;					\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-	fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));	\
-      }									\
-    mips_declare_object (FILE, NAME, "", ":\n", 0);			\
-  } while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#undef ASM_FINISH_DECLARE_OBJECT
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
-	 assemble_name (FILE, name);					 \
-	 fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL)));  \
-       }								 \
-   } while (0)
-
-#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)                            \
- do { fputc ( '\t', FILE);                                            \
-      assemble_name (FILE, LABEL1);                                   \
-      fputs ( " = ", FILE);                                           \
-      assemble_name (FILE, LABEL2);                                   \
-      fputc ( '\n', FILE);                                            \
- } while (0)
-
-/* Note about .weak vs. .weakext
-   The mips native assemblers support .weakext, but not .weak.
-   mips-elf gas supports .weak, but not .weakext.
-   mips-elf gas has been changed to support both .weak and .weakext,
-   but until that support is generally available, the 'if' below
-   should serve. */
-
-#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0)
-#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE)	\
- do {						\
-  if (TARGET_GAS)                               \
-      fputs ("\t.weak\t", FILE);		\
-  else                                          \
-      fputs ("\t.weakext\t", FILE);		\
-  assemble_name (FILE, NAME);			\
-  if (VALUE)					\
-    {						\
-      fputc (' ', FILE);			\
-      assemble_name (FILE, VALUE);		\
-    }						\
-  fputc ('\n', FILE);				\
- } while (0)
-
-#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
-#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
-#define UNIQUE_SECTION(DECL,RELOC)					   \
-do {									   \
-  int len, size, sec;							   \
-  char *name, *string, *prefix;						   \
-  static char *prefixes[4][2] = {					   \
-    { ".text.", ".gnu.linkonce.t." },					   \
-    { ".rodata.", ".gnu.linkonce.r." },					   \
-    { ".data.", ".gnu.linkonce.d." },					   \
-    { ".sdata.", ".gnu.linkonce.s." }					   \
-  };									   \
-									   \
-  name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL));		   \
-  size = int_size_in_bytes (TREE_TYPE (decl));				   \
-									   \
-  /* Determine the base section we are interested in:			   \
-     0=text, 1=rodata, 2=data, 3=sdata.  */				   \
-  if (TREE_CODE (DECL) == FUNCTION_DECL)				   \
-    sec = 0;								   \
-  else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)			   \
-      && TREE_CODE (decl) == STRING_CST					   \
-      && !flag_writable_strings)					   \
-    {									   \
-      /* For embedded position independent code, put constant strings	   \
-	 in the text section, because the data section is limited to	   \
-	 64K in size.  For mips16 code, put strings in the text		   \
-	 section so that a PC relative load instruction can be used to	   \
-	 get their address.  */						   \
-      sec = 0;								   \
-    }									   \
-  else if (TARGET_EMBEDDED_DATA)					   \
-    {									   \
-      /* For embedded applications, always put an object in read-only data \
-	 if possible, in order to reduce RAM usage.  */			   \
-									   \
-      if (DECL_READONLY_SECTION (DECL, RELOC))				   \
-	sec = 1;							   \
-      else if (size > 0 && size <= mips_section_threshold)		   \
-	sec = 3;							   \
-      else								   \
-	sec = 2;							   \
-    }									   \
-  else									   \
-    {									   \
-      /* For hosted applications, always put an object in small data if	   \
-	 possible, as this gives the best performance.  */		   \
-									   \
-      if (size > 0 && size <= mips_section_threshold)			   \
-	sec = 3;							   \
-      else if (DECL_READONLY_SECTION (DECL, RELOC))			   \
-	sec = 1;							   \
-      else								   \
-	sec = 2;							   \
-    }									   \
-									   \
-  prefix = prefixes[sec][DECL_ONE_ONLY (DECL)];				   \
-  len = strlen (name) + strlen (prefix);				   \
-  string = alloca (len + 1);						   \
-  sprintf (string, "%s%s", prefix, name);				   \
-									   \
-  DECL_SECTION_NAME (DECL) = build_string (len, string);		   \
-} while (0)
-
-/* Support the ctors/dtors and other sections.  */
- 
-/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
- 
-   Note that we want to give these sections the SHF_WRITE attribute
-   because these sections will actually contain data (i.e. tables of
-   addresses of functions in the current root executable or shared library
-   file) and, in the case of a shared library, the relocatable addresses
-   will have to be properly resolved/relocated (and then written into) by
-   the dynamic linker when it actually attaches the given shared library
-   to the executing process.  (Note that on SVR4, you may wish to use the
-   `-z text' option to the ELF linker, when building a shared library, as
-   an additional check that you are doing everything right.  But if you do
-   use the `-z text' option when building a shared library, you will get
-   errors unless the .ctors and .dtors sections are marked as writable
-   via the SHF_WRITE attribute.)  */
-
-#define CTORS_SECTION_ASM_OP    "\t.section\t.ctors,\"aw\""
-#define DTORS_SECTION_ASM_OP    "\t.section\t.dtors,\"aw\""
- 
-/* A list of other sections which the compiler might be "in" at any
-   given time.  */
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_sdata, in_rdata, in_ctors, in_dtors
- 
-#define INVOKE__main
-#define NAME__MAIN "__gccmain"
-#define SYMBOL__MAIN __gccmain
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS                                         \
-  SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \
-  SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP) \
-  SECTION_FUNCTION_TEMPLATE(ctors_section, in_ctors, CTORS_SECTION_ASM_OP) \
-  SECTION_FUNCTION_TEMPLATE(dtors_section, in_dtors, DTORS_SECTION_ASM_OP)
-
-#define SECTION_FUNCTION_TEMPLATE(FN, ENUM, OP)                               \
-void FN ()                                                            \
-{                                                                     \
-  if (in_section != ENUM)                                             \
-    {                                                                 \
-      fprintf (asm_out_file, "%s\n", OP);                             \
-      in_section = ENUM;                                              \
-    }                                                                 \
-}
-
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)                             \
-  do {                                                                \
-    ctors_section ();                                                 \
-    fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word");     \
-    assemble_name (FILE, NAME);                                       \
-    fprintf (FILE, "\n");                                             \
-  } while (0)
-
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)                              \
-  do {                                                                \
-    dtors_section ();                                                 \
-    fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word");     \
-    assemble_name (FILE, NAME);                                       \
-    fprintf (FILE, "\n");                                             \
-  } while (0)
-
-#define CTOR_LIST_BEGIN                                 \
-asm (CTORS_SECTION_ASM_OP);                             \
-func_ptr __CTOR_LIST__[1] = { (func_ptr) (-1) }
- 
-#define CTOR_LIST_END                                   \
-asm (CTORS_SECTION_ASM_OP);                             \
-func_ptr __CTOR_END__[1] = { (func_ptr) 0 };
- 
-#define DTOR_LIST_BEGIN                                 \
-asm (DTORS_SECTION_ASM_OP);                             \
-func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) }
-
-#define DTOR_LIST_END                                   \
-asm (DTORS_SECTION_ASM_OP);                             \
-func_ptr __DTOR_END__[1] = { (func_ptr) 0 };
-
-/* Don't set the target flags, this is done by the linker script */
-#undef LIB_SPEC
-#define LIB_SPEC ""
-
-#undef  STARTFILE_SPEC
-#define STARTFILE_SPEC "crtbegin%O%s crt0%O%s"
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend%O%s"
diff --git a/gcc/config/mips/elfb4100.h b/gcc/config/mips/elfb4100.h
deleted file mode 100755
index bdba495..0000000
--- a/gcc/config/mips/elfb4100.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   NEC VR4100 version.
-   Copyright (c) 1995 Cygnus Support Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#define MIPS_CPU_STRING_DEFAULT "VR4100"
-
-/* Use the MIPS EABI by default.  */
-#define MIPS_ABI_DEFAULT ABI_EABI
-
-/* The following is needed because -mips3 and -mips4 set gp64 which in
-   combination with abi=eabi, causes long64 to be set. */
-#define SUBTARGET_CPP_SIZE_SPEC "\
--D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int"
-
-/* Debugging */
-
-#define DWARF2_DEBUGGING_INFO
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-/* For the 'preferred' cases ("gN" and "ggdbN") we need to tell the 
-   gnu assembler not to generate debugging information. */
-   
-#define SUBTARGET_ASM_DEBUGGING_SPEC "\
-%{!mmips-as: \
-  %{g:-g0} %{g0:-g0} %{g1:-g0} %{g2:-g0} %{g3:-g0} \
-  %{ggdb:-g0} %{ggdb0:-g0} %{ggdb1:-g0} %{ggdb2:-g0} %{ggdb3:-g0} \
-  %{gdwarf-2*:-g0}} \
-%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
-%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
-%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
-
-#include "mips/elf64.h"
-
-#undef MULTILIB_DEFAULTS
-#define MULTILIB_DEFAULTS { "EB", "mno-mips16" }
-
-#undef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC "\
-%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}} \
-%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}}"
-
-/* __mips_soft_float must be defined by default because libgloss uses it.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4100 -D_mips -D_MIPSEB -D_R4100 -D__mips_soft_float"
diff --git a/gcc/config/mips/elfb4300.h b/gcc/config/mips/elfb4300.h
deleted file mode 100755
index d12cb46..0000000
--- a/gcc/config/mips/elfb4300.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   NEC VR4300 version.
-   Copyright (c) 1995 Cygnus Support Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#define MIPS_CPU_STRING_DEFAULT "VR4300"
-
-#define DWARF2_DEBUGGING_INFO
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-#define SUBTARGET_ASM_DEBUGGING_SPEC "\
-%{!mmips-as: \
-  %{g:-g0} %{g0:-g0} %{g1:-g0} %{g2:-g0} %{g3:-g0} \
-  %{ggdb:-g0} %{ggdb0:-g0} %{ggdb1:-g0} %{ggdb2:-g0} %{ggdb3:-g0} \
-  %{gdwarf-2*:-g0}} \
-%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
-%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
-%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
-
-#include "mips/elf64.h"
-
-#undef MULTILIB_DEFAULTS
-#define MULTILIB_DEFAULTS { "EB" }
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4300 -D_mips -D_MIPSEB -D_R4300"
diff --git a/gcc/config/mips/elfb5000.h b/gcc/config/mips/elfb5000.h
deleted file mode 100755
index 63ca5ee..0000000
--- a/gcc/config/mips/elfb5000.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* CYGNUS LOCAL: Entire file.  */
-
-/* Definitions of target machine for GNU compiler.
-   NEC VR5000 version.
-   Copyright (c) 1996 Cygnus Support Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#define MIPS_CPU_STRING_DEFAULT "VR5000"
-
-/* We use the MIPS EABI by default.  */
-#define MIPS_ABI_DEFAULT ABI_EABI
-
-#include "mips/elf64.h"
-#include "mips/abi64.h"
-
-#undef MULTILIB_DEFAULTS
-#define MULTILIB_DEFAULTS { "EB" }
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR5000 -D_mips -D_MIPSEB -D_R5000"
-
-#undef SUBTARGET_CPP_SIZE_SPEC
-#define SUBTARGET_CPP_SIZE_SPEC "\
--D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int"
-
-#undef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC "\
-%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}}\
-%{m5400: -DR5400 -D_R5400}\
-%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}}"
-
-#undef MIPS_ISA_DEFAULT
-#define MIPS_ISA_DEFAULT 4
diff --git a/gcc/config/mips/elfl.h b/gcc/config/mips/elfl.h
deleted file mode 100755
index 7575e3d..0000000
--- a/gcc/config/mips/elfl.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Little endian MIPS
-   R3000 version with GOFAST floating point library.
-   Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This is a little endian version of elf.h.  */
-
-#define TARGET_ENDIAN_DEFAULT 0
-
-#include "mips/elf.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR3000 -D_mips -D_MIPSEL -D_R3000"
diff --git a/gcc/config/mips/elfl4100.h b/gcc/config/mips/elfl4100.h
deleted file mode 100755
index 41b583d..0000000
--- a/gcc/config/mips/elfl4100.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   NEC VR4100 little-endian version.
-   Copyright (c) 1995 Cygnus Support Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#define MIPS_CPU_STRING_DEFAULT "VR4100"
-
-/* Use the MIPS EABI by default.  */
-#define MIPS_ABI_DEFAULT ABI_EABI
-
-/* The following is needed because -mips3 and -mips4 set gp64 which in
-   combination with abi=eabi, causes long64 to be set. */
-#define SUBTARGET_CPP_SIZE_SPEC "\
--D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int"
-
-/* Debugging */
-
-#define DWARF2_DEBUGGING_INFO
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-/* For the 'preferred' cases ("gN" and "ggdbN") we need to tell the 
-   gnu assembler not to generate debugging information. */
-   
-#define SUBTARGET_ASM_DEBUGGING_SPEC "\
-%{!mmips-as: \
-  %{g:-g0} %{g0:-g0} %{g1:-g0} %{g2:-g0} %{g3:-g0} \
-  %{ggdb:-g0} %{ggdb0:-g0} %{ggdb1:-g0} %{ggdb2:-g0} %{ggdb3:-g0} \
-  %{gdwarf-2*:-g0}} \
-%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
-%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
-%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
-
-#include "mips/elfl64.h"
-
-#undef MULTILIB_DEFAULTS
-#define MULTILIB_DEFAULTS { "EL", "mno-mips16" }
-
-#undef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC "\
-%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}} \
-%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}}"
-
-/* __mips_soft_float must be defined by default because libgloss uses it.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR4100 -D_mips -D_MIPSEL -D_R4100 -D__mips_soft_float"
diff --git a/gcc/config/mips/elfl4300.h b/gcc/config/mips/elfl4300.h
deleted file mode 100755
index 4bad15b..0000000
--- a/gcc/config/mips/elfl4300.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   NEC VR4300 little-endian version.
-   Copyright (c) 1995 Cygnus Support Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#define MIPS_CPU_STRING_DEFAULT "VR4300"
-
-#define DWARF2_DEBUGGING_INFO
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-#define SUBTARGET_ASM_DEBUGGING_SPEC "\
-%{!mmips-as: \
-  %{g:-g0} %{g0:-g0} %{g1:-g0} %{g2:-g0} %{g3:-g0} \
-  %{ggdb:-g0} %{ggdb0:-g0} %{ggdb1:-g0} %{ggdb2:-g0} %{ggdb3:-g0} \
-  %{gdwarf-2*:-g0}} \
-%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
-%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
-%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
-
-#include "mips/elfl64.h"
-
-#undef MULTILIB_DEFAULTS
-#define MULTILIB_DEFAULTS { "EL" }
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR4300 -D_mips -D_MIPSEL -D_R4300"
diff --git a/gcc/config/mips/elfl5000.h b/gcc/config/mips/elfl5000.h
deleted file mode 100755
index 439e177..0000000
--- a/gcc/config/mips/elfl5000.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* CYGNUS LOCAL: Entire file.  */
-
-/* Definitions of target machine for GNU compiler.
-   NEC VR5000 little-endian version.
-   Copyright (c) 1995 Cygnus Support Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#define MIPS_CPU_STRING_DEFAULT "VR5000"
-
-/* We use the MIPS EABI by default.  */
-#define MIPS_ABI_DEFAULT ABI_EABI
-
-#include "mips/elfl64.h"
-#include "mips/abi64.h"
-
-#undef MULTILIB_DEFAULTS
-#define MULTILIB_DEFAULTS { "EL" }
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR5000 -D_mips -D_MIPSEL -D_R5000"
-
-#undef SUBTARGET_CPP_SIZE_SPEC
-#define SUBTARGET_CPP_SIZE_SPEC "\
--D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int"
-
-#undef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC "\
-%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}}\
-%{m5400: -DR5400 -D_R5400}\
-%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}}"
-
-#undef MIPS_ISA_DEFAULT
-#define MIPS_ISA_DEFAULT 4
diff --git a/gcc/config/mips/elfl64.h b/gcc/config/mips/elfl64.h
deleted file mode 100755
index 5e18c09..0000000
--- a/gcc/config/mips/elfl64.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Little endian MIPS
-   R4000 version with GOFAST floating point library.
-   Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This is a little endian version of elf64.h.  */
-
-#define TARGET_ENDIAN_DEFAULT 0
-
-#include "mips/elf64.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR4000 -D_mips -D_MIPSEL -D_R4000"
diff --git a/gcc/config/mips/elflorion.h b/gcc/config/mips/elflorion.h
deleted file mode 100755
index 4b7f111..0000000
--- a/gcc/config/mips/elflorion.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Definitions of target machine for GNU compiler.  MIPS ORION version with
-   GOFAST floating point library.
-   Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MIPS_CPU_STRING_DEFAULT "orion"
-
-#include "mips/elfl64.h"
diff --git a/gcc/config/mips/elforion.h b/gcc/config/mips/elforion.h
deleted file mode 100755
index aa1a058..0000000
--- a/gcc/config/mips/elforion.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Definitions of target machine for GNU compiler.  MIPS ORION version with
-   GOFAST floating point library.
-   Copyright (C) 1994, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MIPS_CPU_STRING_DEFAULT "orion"
diff --git a/gcc/config/mips/gnu.h b/gcc/config/mips/gnu.h
deleted file mode 100755
index bf48bc4..0000000
--- a/gcc/config/mips/gnu.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* Definitions of target machine for GNU compiler.  MIPS GNU Hurd version.
-   Copyright (C) 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define TARGET_DEFAULT MASK_GAS
-
-#include <mips/mips.h>
-
-#undef SWITCH_TAKES_ARG
-#undef ASM_FILE_END
-#undef ASM_OUTPUT_IDENT
-#undef ASM_OUTPUT_SOURCE_LINE
-#undef READONLY_DATA_SECTION
-#undef SELECT_SECTION
-#undef ASM_DECLARE_FUNCTION_NAME
-#undef ASM_DECLARE_OBJECT_NAME
-/* #undef PREFERRED_DEBUGGING_TYPE */
-
-#include <svr4.h>
-
-#undef MD_EXEC_PREFIX
-#undef MD_STARTFILE_PREFIX
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (MIPS GNU/ELF)");
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)						\
-  do {									\
-	mips_asm_file_start (FILE);					\
-	fprintf (FILE, "\t.version\t\"01.01\"\n");			\
-  } while (0)
-
-#undef ASM_FILE_END
-#define ASM_FILE_END(FILE)						\
-  do {				 					\
-	mips_asm_file_end(FILE);					\
-	fprintf ((FILE), "\t%s\t\"GCC: (GNU) %s\"\n",			\
-		IDENT_ASM_OP, version_string);				\
-  } while (0)
-
-#undef ASM_OUTPUT_SOURCE_LINE
-#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE)				\
-  do {									\
-      ++sym_lineno;							\
-      fprintf ((FILE), ".LM%d:\n\t%s %d,0,%d,.LM%d\n",			\
-	       sym_lineno, ASM_STABN_OP, N_SLINE, (LINE), sym_lineno);	\
-  } while (0)
-
-#undef ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL)			\
-  do {									\
-    extern FILE *asm_out_text_file;					\
-									\
-    if (TARGET_GP_OPT)							\
-      STREAM = asm_out_text_file;					\
-    fprintf (STREAM, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (STREAM, NAME);					\
-    putc (',', STREAM);							\
-    fprintf (STREAM, TYPE_OPERAND_FMT, "function");			\
-    putc ('\n', STREAM);						\
-    ASM_DECLARE_RESULT (STREAM, DECL_RESULT (DECL));			\
-    HALF_PIC_DECLARE (NAME);						\
-  } while (0)
-
-/* Switch  Recognition by gcc.c.  Add -G xx support */
-#undef SWITCH_TAKES_ARG
-#define SWITCH_TAKES_ARG(CHAR)						\
-  (DEFAULT_SWITCH_TAKES_ARG(CHAR) || (CHAR) == 'G')
-
-#undef DEFAULT_PCC_STRUCT_RETURN
-#define DEFAULT_PCC_STRUCT_RETURN 1
-
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
-
-#define MIPS_GNU
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -Acpu(mips) -Amachine(mips) \
--Dunix -Asystem(unix)  -DMACH -Asystem(mach) -D__GNU__ -Asystem(gnu) \
--DMIPSEB -DR3000 -D_MIPSEB -D_R3000 \
--D_MIPS_SZINT=32 -D_MIPS_SZLONG=32 -D_MIPS_SZPTR=32"
-
-#undef LINK_SPEC
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \
--systype /gnu/ "
-		    
-#undef LIB_SPEC
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC  "%{pg:gcrt0.o%s} %{!pg:%{p:gcrt0.o%s} %{!p:crt0.o%s}} %{static:-static}"
-
-#undef MACHINE_TYPE
-#define MACHINE_TYPE "GNU MIPS/ELF"
-
-#undef YES_UNDERSCORE
-
-#undef SDB_DEBUGGING_INFO
-#undef DBX_DEBUGGING_INFO
-#undef MIPS_DEBUGGING_INFO
-#define DWARF_DEBUGGING_INFO
-
-#define NO_MIPS_SELECT_SECTION
-
-/* Get machine-independent configuration parameters for the GNU system.  */
-#include <gnu.h>
diff --git a/gcc/config/mips/iris3.h b/gcc/config/mips/iris3.h
deleted file mode 100755
index 1f690ff..0000000
--- a/gcc/config/mips/iris3.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Iris version.
-   Copyright (C) 1991, 1993, 1995, 1996, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define SGI_TARGET 1		/* inform other mips files this is SGI */
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES	"\
--Dunix -Dmips -Dsgi -DSVR3 -Dhost_mips -DMIPSEB -DSYSTYPE_SYSV \
--Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)"
-
-#define STARTFILE_SPEC	"%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
-
-#define SUBTARGET_CPP_SPEC "\
-%{!ansi:-D__EXTENSIONS__} -D_MIPSEB -D_SYSTYPE_SYSV"
-
-#define LIB_SPEC	\
-	"%{!p:%{!pg:%{!static:%{!g*:-lc_s}} -lc}}%{p:-lc_p}%{pg:-lc_p} crtn.o%s"
-
-#define MACHINE_TYPE	"Silicon Graphics Mips"
-
-/* Always use 1 for .file number.  I [meissner@osf.org] wonder why
-   IRIS needs this.  */
-
-#define SET_FILE_NUMBER() num_source_filenames = 1
-
-/* Put out a label after a .loc.  I [meissner@osf.org] wonder why
-   IRIS needs this.  */
-
-#define LABEL_AFTER_LOC(STREAM) fprintf (STREAM, "LM%d:\n", ++sym_lineno)
-
-#define STACK_ARGS_ADJUST(SIZE)                                         \
-{                                                                       \
-  SIZE.constant += 4;                                                   \
-  if (SIZE.constant < 32)						\
-    SIZE.constant = 32;                                                 \
-}
-
-/* Do not allow `$' in identifiers.  */
-
-#define DOLLARS_IN_IDENTIFIERS 0
-
-/* Tell G++ not to create constructors or destructors with $'s in them.  */
-
-#define NO_DOLLAR_IN_LABEL 1
-
-/* Specify wchar_t type.  */
-#define WCHAR_TYPE	"unsigned char"
-#define WCHAR_TYPE_SIZE BITS_PER_UNIT
-
-/* Generate calls to memcpy, etc., not bcopy, etc.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Plain char is unsigned in the SGI compiler.  */
-#define DEFAULT_SIGNED_CHAR 0
diff --git a/gcc/config/mips/iris4.h b/gcc/config/mips/iris4.h
deleted file mode 100755
index 7ca0459..0000000
--- a/gcc/config/mips/iris4.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Iris version 4.
-   Copyright (C) 1991, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Use atexit for static constructors/destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
-/* Profiling is supported via libprof1.a not -lc_p as in Irix 3.  */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}"
-
-#undef LIB_SPEC
-#define LIB_SPEC \
-  "%{!p:%{!pg:%{!static:%{!g*:-lc_s}}}}%{p:libprof1.a%s}%{pg:libprof1.a%s} -lc crtn.o%s"
-
-/* Some assemblers have a bug that causes backslash escaped chars in .ascii
-   to be misassembled, so we just completely avoid it.  */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)			\
-do {							\
-  unsigned char *s;					\
-  int i;						\
-  for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++)	\
-    {							\
-      if ((i % 8) == 0)					\
-	fputs ("\n\t.byte\t", (FILE));			\
-      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
-    }							\
-  fputs ("\n", (FILE));					\
-} while (0)
diff --git a/gcc/config/mips/iris4loser.h b/gcc/config/mips/iris4loser.h
deleted file mode 100755
index 426c822..0000000
--- a/gcc/config/mips/iris4loser.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* Like iris4.h, but always inhibits assembler optimization for MIPS as.
-   Use this via mips-sgi-iris4loser if you need it.  */
-
-#define SUBTARGET_MIPS_AS_ASM_SPEC "-O0 %{v}"
-#define SUBTARGET_ASM_OPTIMIZING_SPEC ""
diff --git a/gcc/config/mips/iris5.h b/gcc/config/mips/iris5.h
deleted file mode 100755
index 7910eef..0000000
--- a/gcc/config/mips/iris5.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Iris version 5.
-   Copyright (C) 1993, 1995, 1996, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#ifndef TARGET_DEFAULT
-#define	TARGET_DEFAULT	MASK_ABICALLS
-#endif
-#define ABICALLS_ASM_OP ".option pic2"
-
-#include "mips/iris3.h"
-#include "mips/mips.h"
-#include "mips/iris4.h"
-
-/* Irix 5 doesn't use COFF, so disable special COFF handling in collect2.c.  */
-#undef OBJECT_FORMAT_COFF
-
-/* ??? This is correct, but not very useful, because there is no file that
-   uses this macro.  */
-/* ??? The best way to handle global constructors under ELF is to use .init
-   and .fini sections.  Unfortunately, there is apparently no way to get
-   the Irix 5.x (x <= 2) assembler to create these sections.  So we instead
-   use collect.  The linker can create these sections via -init and -fini
-   options, but using this would require modifying how crtstuff works, and
-   I will leave that for another time (or someone else).  */
-#define OBJECT_FORMAT_ELF
-#define HAS_INIT_SECTION
-#define LD_INIT_SWITCH "-init"
-#define LD_FINI_SWITCH "-fini"
-
-/* Specify wchar_t types.  */
-#undef	WCHAR_TYPE
-#undef	WCHAR_TYPE_SIZE
-#undef	MAX_WCHAR_TYPE_SIZE
-
-#define WCHAR_TYPE	"long int"
-#define WCHAR_TYPE_SIZE	LONG_TYPE_SIZE
-#define MAX_WCHAR_TYPE_SIZE	MAX_LONG_TYPE_SIZE
-
-#define WORD_SWITCH_TAKES_ARG(STR)			\
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR)			\
-  || !strcmp (STR, "rpath"))
-
-#undef SUBTARGET_CC1_SPEC
-#define SUBTARGET_CC1_SPEC "%{static: -mno-abicalls}"
-
-/* ??? _MIPS_SIM and _MIPS_SZPTR should eventually depend on options when
-   options for them exist.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -D_MIPSEB -DSYSTYPE_SVR4 \
-  -D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \
-  -D_MIPS_SIM=_MIPS_SIM_ABI32 -D_MIPS_SZPTR=32 \
-  -Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(sgi)"
-
-#undef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC "\
-%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE -D_LONGLONG} \
-%{!mfp64: -D_MIPS_FPSET=16}%{mfp64: -D_MIPS_FPSET=32} \
-%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
-%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \
-%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
-%{!mips1: %{!mips2: %{!mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS1}}} \
-%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \
-%{!mlong64: -D_MIPS_SZLONG=32}%{mlong64: -D_MIPS_SZLONG=64}"
-
-#undef LINK_SPEC
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{static: -non_shared} \
-%{!static: \
-  %{!shared:%{!non_shared:%{!call_shared: -call_shared -no_unresolved}}}} \
-%{rpath} \
--_SYSTYPE_SVR4"
-
-/* We now support shared libraries.  */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "\
-%{!static: \
-  %{!shared:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}}} \
-%{static: \
-  %{pg:gcrt1.o%s} \
-  %{!pg:%{p:/usr/lib/nonshared/mcrt1.o%s libprof1.a%s} \
-  %{!p:/usr/lib/nonshared/crt1.o%s}}}"
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{!shared:%{p:-lprof1} %{pg:-lprof1} -lc}"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "%{!shared:crtn.o%s}"
-
-/* We do not want to run mips-tfile!  */
-#undef ASM_FINAL_SPEC
-
-/* The system header files are C++ aware. */
-/* ??? Unfortunately, most but not all of the headers are C++ aware.
-   Specifically, curses.h is not, and as a consequence, defining this
-   used to prevent libg++ building.  This is no longer the case so
-   define it again to prevent other problems, e.g. with getopt in
-   unistd.h.  We still need some way to fix just those files that need
-   fixing.  */
-#define NO_IMPLICIT_EXTERN_C 1
-
-/* We don't support debugging info for now. */
-#undef DBX_DEBUGGING_INFO
-#undef SDB_DEBUGGING_INFO
-#undef MIPS_DEBUGGING_INFO
-#undef PREFERRED_DEBUGGING_TYPE
-
-/* Likewise, the assembler doesn't handle DWARF2 directives.  */
-#define DWARF2_UNWIND_INFO 0
-
-#undef MACHINE_TYPE
-#define MACHINE_TYPE "SGI running IRIX 5.x"
-
- /* Dollar signs are OK in Irix5 but not in Irix3.  */
-#undef DOLLARS_IN_IDENTIFIERS
-#undef NO_DOLLAR_IN_LABEL
-
-/* -G is incompatible with -KPIC which is the default, so only allow objects
-   in the small data section if the user explicitly asks for it.  */
-#undef MIPS_DEFAULT_GVALUE
-#define MIPS_DEFAULT_GVALUE 0
-
-/* In Irix 5, we must output a `.global name .text' directive for every used
-   but undefined function.  If we don't, the linker may perform an optimization
-   (skipping over the insns that set $gp) when it is unsafe.  This is used
-   indirectly by ASM_OUTPUT_EXTERNAL.  */
-#define ASM_OUTPUT_UNDEF_FUNCTION(FILE, NAME)	\
-do {						\
-  fputs ("\t.globl ", FILE);			\
-  assemble_name (FILE, NAME);			\
-  fputs (" .text\n", FILE);			\
-} while (0)
-
-/* Also do this for libcalls.  */
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN)	\
-  mips_output_external_libcall (FILE, XSTR (FUN, 0))
-
-/* This does for functions what ASM_DECLARE_OBJECT_NAME does for variables.
-   This is used indirectly by ASM_OUTPUT_EXTERNAL.  */
-#define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL)	\
-do {							\
-  tree name_tree = get_identifier (NAME);		\
-  TREE_ASM_WRITTEN (name_tree) = 1;			\
-} while (0)
diff --git a/gcc/config/mips/iris5gas.h b/gcc/config/mips/iris5gas.h
deleted file mode 100755
index 477a55f..0000000
--- a/gcc/config/mips/iris5gas.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Irix version 5 with gas. */
-
-/* Enable debugging.  */
-#define DBX_DEBUGGING_INFO
-#define SDB_DEBUGGING_INFO
-#define MIPS_DEBUGGING_INFO
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
-
-/* GNU as does handle DWARF2 directives.  */
-#undef DWARF2_UNWIND_INFO
-#define DWARF2_UNWIND_INFO 1
-
-/* Irix 5 does not have some strange restrictions that Irix 3 had.  */
-#undef SET_FILE_NUMBER
-#define SET_FILE_NUMBER() ++num_source_filenames
-#undef LABEL_AFTER_LOC
-#define LABEL_AFTER_LOC(STREAM)
-
-/* We need to use .esize and .etype instead of .size and .type to
-   avoid conflicting with ELF directives.  These are only recognized
-   by gas, anyhow, not the native assembler.  */
-#undef PUT_SDB_SIZE
-#define PUT_SDB_SIZE(a)                                       \
-do {                                                  \
-  extern FILE *asm_out_text_file;                     \
-  fprintf (asm_out_text_file, "\t.esize\t%d;", (a));  \
-} while (0)
-
-#undef PUT_SDB_TYPE
-#define PUT_SDB_TYPE(a)                                       \
-do {                                                  \
-  extern FILE *asm_out_text_file;                     \
-  fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a));        \
-} while (0)
diff --git a/gcc/config/mips/iris6.h b/gcc/config/mips/iris6.h
deleted file mode 100755
index 3a456b5..0000000
--- a/gcc/config/mips/iris6.h
+++ /dev/null
@@ -1,567 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Iris version 6.
-   Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Default to -mabi=n32 and -mips3.  */
-#define MIPS_ISA_DEFAULT 3
-#define MIPS_ABI_DEFAULT ABI_N32
-#define MULTILIB_DEFAULTS { "mabi=n32" }
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_ABICALLS|MASK_FLOAT64|MASK_64BIT)
-#endif
-
-#include "mips/iris5.h"
-#include "mips/abi64.h"
-
-/* Irix6 assembler does handle DWARF2 directives.  Override setting in
- irix5.h file.  */
-#undef DWARF2_UNWIND_INFO
-
-/* For Irix 6, -mabi=64 implies TARGET_LONG64.  */
-/* This is handled in override_options.  */
-
-#undef SUBTARGET_CC1_SPEC
-#define SUBTARGET_CC1_SPEC "%{static: -mno-abicalls}"
-
-/* We must pass -D_LONGLONG always, even when -ansi is used, because irix6
-   system header files require it.  This is OK, because gcc never warns
-   when long long is used in system header files.  Alternatively, we can
-   add support for the SGI builtin type __long_long.  */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -D_MIPSEB -DSYSTYPE_SVR4 \
-  -D_LONGLONG -D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \
-  -Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(sgi)"
-
-#undef SUBTARGET_CPP_SIZE_SPEC
-#define SUBTARGET_CPP_SIZE_SPEC "\
-%{mabi=32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
-%{mabi=n32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
-%{mabi=64: -D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
-%{!mabi*: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
-
-/* We must make -mips3 do what -mlong64 used to do.  */
-/* ??? If no mipsX option given, but a mabi=X option is, then should set
-   _MIPS_ISA based on the mabi=X option.  */
-/* ??? If no mabi=X option give, but a mipsX option is, then should set
-   _MIPS_SIM based on the mipsX option.  */
-/* ??? Same for _MIPS_SZINT.  */
-/* ??? Same for _MIPS_SZPTR.  */
-/* ??? Same for __SIZE_TYPE and __PTRDIFF_TYPE.  */
-#undef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC "\
-%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE} \
-%{mfp32: -D_MIPS_FPSET=16}%{!mfp32: -D_MIPS_FPSET=32} \
-%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
-%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \
-%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
-%{mips4: -D_MIPS_ISA=_MIPS_ISA_MIPS4} \
-%{!mips*: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
-%{mabi=32: -D_MIPS_SIM=_MIPS_SIM_ABI32}	\
-%{mabi=n32: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \
-%{mabi=64: -D_ABI64=3 -D_MIPS_SIM=_ABI64} \
-%{!mabi*: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \
-%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \
-%{mabi=32: -D_MIPS_SZLONG=32} \
-%{mabi=n32: -D_MIPS_SZLONG=32} \
-%{mabi=64: -D_MIPS_SZLONG=64} \
-%{!mabi*: -D_MIPS_SZLONG=32} \
-%{mabi=32: -D_MIPS_SZPTR=32} \
-%{mabi=n32: -D_MIPS_SZPTR=32} \
-%{mabi=64: -D_MIPS_SZPTR=64} \
-%{!mabi*: -D_MIPS_SZPTR=32} \
-%{!mips1:%{!mips2: -D_COMPILER_VERSION=601}}		\
-%{!mips*: -U__mips -D__mips=3} \
-%{mabi=32: -U__mips64} \
-%{mabi=n32: -D__mips64} \
-%{mabi=64: -D__mips64} \
-%{!mabi*: -D__mips64}"
-
-/* Irix 6 uses DWARF-2.  */
-#define DWARF2_DEBUGGING_INFO
-#define MIPS_DEBUGGING_INFO
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-/* Force the generation of dwarf .debug_frame sections even if not
-   compiling -g.  This guarantees that we can unwind the stack. */
-#define DWARF2_FRAME_INFO 1
-/* The size in bytes of a DWARF field indicating an offset or length
-   relative to a debug info section, specified to be 4 bytes in the DWARF-2
-   specification.  The SGI/MIPS ABI defines it to be the same as PTR_SIZE.  */
-#define DWARF_OFFSET_SIZE PTR_SIZE
-
-/* There is no GNU as port for Irix6 yet, so we set MD_EXEC_PREFIX so that
-   gcc will automatically find SGI as instead of searching the user's path.
-   The latter can fail when building a cross compiler if the user has . in
-   the path before /usr/bin, since then gcc will find and try to use the link
-   to the cross assembler which can't possibly work.  */
-
-#undef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "/usr/bin/"
-
-/* We have no need for MD_STARTFILE_PREFIX.  */
-#undef MD_STARTFILE_PREFIX
-
-#undef MACHINE_TYPE
-#define MACHINE_TYPE "SGI running IRIX 6.x"
-
-/* The Irix 6.0.1 assembler doesn't like labels in the text section, so
-   just avoid emitting them.  */
-#define ASM_IDENTIFY_GCC(x) ((void)0)
-#define ASM_IDENTIFY_LANGUAGE(x) ((void)0)
-
-/* Irix 5 stuff that we don't need for Irix 6.  */
-/* ??? We do need this for the -mabi=32 switch though.  */
-#undef ASM_OUTPUT_UNDEF_FUNCTION
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-#undef ASM_DECLARE_FUNCTION_SIZE
-
-/* Stuff we need for Irix 6 that isn't in Irix 5.  */
-
-/* The SGI assembler doesn't like labels before the .ent, so we must output
-   the .ent and function name here, which is the normal place for it.  */
-
-#undef ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL)			\
-  do {									\
-    fputs ("\t.ent\t", STREAM);						\
-    assemble_name (STREAM, NAME);					\
-    fputs ("\n", STREAM);						\
-    assemble_name (STREAM, NAME);					\
-    fputs (":\n", STREAM);						\
-  } while (0)
-
-/* Likewise, the SGI assembler doesn't like labels after the .end, so we
-   must output the .end here.  */
-#define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL)			\
-  do {									\
-    fputs ("\t.end\t", STREAM);						\
-    assemble_name (STREAM, NAME);					\
-    fputs ("\n", STREAM);						\
-  } while (0)
-
-/* Tell function_prologue in mips.c that we have already output the .ent/.end
-   pseudo-ops.  */
-#define FUNCTION_NAME_ALREADY_DECLARED
-
-#undef SET_ASM_OP	/* Has no equivalent.  See ASM_OUTPUT_DEF below.  */
-
-#if 0
-/* This is *NOT* how to equate one symbol to another symbol.  The assembler
-   '=' syntax just equates a name to a constant expression.
-   See ASM_OUTPUT_WEAK_ALIAS.  */
-
-#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)				\
- do {	fprintf ((FILE), "\t");						\
-	assemble_name (FILE, LABEL1);					\
-	fprintf (FILE, " = ");						\
-	assemble_name (FILE, LABEL2);					\
-	fprintf (FILE, "\n");						\
-  } while (0)
-#endif
-
-/* Define the strings used for the special svr4 .type and .size directives.  */
-
-#define TYPE_ASM_OP	".type"
-#define SIZE_ASM_OP	".size"
-
-/* This is how we tell the assembler that a symbol is weak.  */
-
-#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE)	\
- do {						\
-  ASM_GLOBALIZE_LABEL (FILE, NAME);		\
-  fputs ("\t.weakext\t", FILE);			\
-  assemble_name (FILE, NAME);			\
-  if (VALUE)					\
-    {						\
-      fputc (' ', FILE);			\
-      assemble_name (FILE, VALUE);		\
-    }						\
-  fputc ('\n', FILE);				\
- } while (0)
-
-#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0)
-
-#define POPSECTION_ASM_OP	".popsection"
-
-#define DEBUG_INFO_SECTION	".debug_info,0x7000001e,0,0,1"
-#define DEBUG_LINE_SECTION	".debug_line,0x7000001e,0,0,1"
-#define SFNAMES_SECTION		".debug_sfnames,0x7000001e,0,0,1"
-#define SRCINFO_SECTION		".debug_srcinfo,0x7000001e,0,0,1"
-#define MACINFO_SECTION		".debug_macinfo,0x7000001e,0,0,1"
-#define PUBNAMES_SECTION	".debug_pubnames,0x7000001e,0,0,1"
-#define ARANGES_SECTION		".debug_aranges,0x7000001e,0,0,1"
-#define FRAME_SECTION		".debug_frame,0x7000001e,0x08000000,0,1"
-#define ABBREV_SECTION		".debug_abbrev,0x7000001e,0,0,1"
-
-/* ??? If no mabi=X option give, but a mipsX option is, then should depend
-   on the mipsX option.  */
-#undef SUBTARGET_ASM_SPEC
-#define SUBTARGET_ASM_SPEC "%{!mabi*:-n32}"
-
-/* Must pass -g0 to the assembler, otherwise it may overwrite our
-   debug info with its own debug info. */
-/* Must pass -show instead of -v.  */
-/* Must pass -G 0 to the assembler, otherwise we may get warnings about
-   GOT overflow.  */
-/* ??? We pass -w to disable all assembler warnings.  The `label should be
-   inside .ent/.end block' warning that we get for DWARF II debug info labels
-   is particularly annoying.  */
-#undef SUBTARGET_MIPS_AS_ASM_SPEC
-#define SUBTARGET_MIPS_AS_ASM_SPEC "%{v:-show} -G 0 -w"
-
-#undef SUBTARGET_ASM_DEBUGGING_SPEC
-#define SUBTARGET_ASM_DEBUGGING_SPEC "-g0"
-
-/* Stuff for constructors.  Start here.  */
-
-/* The assembler now accepts .section pseudo-ops, but it does not allow
-   one to change the section in the middle of a function, so we can't use
-   the INIT_SECTION_ASM_OP code in crtstuff.  But we can build up the ctor
-   and dtor lists this way, so we use -init and -fini to invoke the
-   do_global_* functions instead of running collect2.  */
-
-#define BSS_SECTION_ASM_OP	".section\t.bss"
-#define CONST_SECTION_ASM_OP_32	"\t.rdata"
-#define CONST_SECTION_ASM_OP_64	".section\t.rodata"
-
-/* The IRIX 6 assembler .section directive takes four additional args:
-   section type, flags, entry size, and alignment.  The alignment of the
-   .ctors and .dtors sections needs to be the same as the size of a pointer
-   so that the linker doesn't add padding between elements.  */
-#if defined (CRT_BEGIN) || defined (CRT_END)
-
-/* If we are included from crtstuff.c, these need to be plain strings.
-   _MIPS_SZPTR is defined in SUBTARGET_CPP_SPEC above.  */
-#if _MIPS_SZPTR == 64
-#define CTORS_SECTION_ASM_OP ".section\t.ctors,1,2,0,8"
-#define DTORS_SECTION_ASM_OP ".section\t.dtors,1,2,0,8"
-#else /* _MIPS_SZPTR != 64 */
-#define CTORS_SECTION_ASM_OP ".section\t.ctors,1,2,0,4"
-#define DTORS_SECTION_ASM_OP ".section\t.dtors,1,2,0,4"
-#endif /* _MIPS_SZPTR == 64 */
-
-#else /* ! (defined (CRT_BEGIN) || defined (CRT_END)) */
-
-/* If we are included from varasm.c, these need to depend on -mabi.  */
-#define CTORS_SECTION_ASM_OP \
-  (TARGET_LONG64 ? ".section\t.ctors,1,2,0,8" : ".section\t.ctors,1,2,0,4")
-#define DTORS_SECTION_ASM_OP \
-  (TARGET_LONG64 ? ".section\t.dtors,1,2,0,8" : ".section\t.dtors,1,2,0,4")
-#endif /* defined (CRT_BEGIN) || defined (CRT_END) */
-
-/* dwarf2out will handle padding this data properly.  We definitely don't
-   want it 8-byte aligned on n32.  */
-#define EH_FRAME_SECTION_ASM_OP ".section\t.eh_frame,1,2,0,1"
-
-/* A default list of other sections which we might be "in" at any given
-   time.  For targets that use additional sections (e.g. .tdesc) you
-   should override this definition in the target-specific file which
-   includes this file.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_sdata, in_rdata, in_const, in_ctors, in_dtors
-
-/* A default list of extra section function definitions.  For targets
-   that use additional sections (e.g. .tdesc) you should override this
-   definition in the target-specific file which includes this file.  */
-
-/* ??? rdata_section is now same as svr4 const_section.  */
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-void									\
-sdata_section ()							\
-{									\
-  if (in_section != in_sdata)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP);		\
-      in_section = in_sdata;						\
-    }									\
-}									\
-									\
-void									\
-rdata_section ()							\
-{									\
-  if (in_section != in_rdata)						\
-    {									\
-      if (mips_abi != ABI_32 && mips_abi != ABI_O64)			\
-	fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP_64);	\
-      else								\
-	fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP_32);	\
-      in_section = in_rdata;						\
-    }									\
-}									\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ",						\
-	     TARGET_LONG64 ? ".dword" : ".word");			\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ",						\
-	     TARGET_LONG64 ? ".dword" : ".word");			\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement to output something to the assembler file to switch to section
-   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
-   NULL_TREE.  */
-
-#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC)			\
-do {									\
-  extern FILE *asm_out_text_file;					\
-  if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL)			\
-    fprintf (asm_out_text_file, "\t.section %s,1,6,4,4\n", (NAME));	\
-  else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC))		\
-    fprintf (F, "\t.section %s,1,2,0,8\n", (NAME));			\
-  else									\
-    fprintf (F, "\t.section %s,1,3,0,8\n", (NAME));			\
-} while (0)
-
-/* Stuff for constructors.  End here.  */
-
-/* ??? Perhaps just include svr4.h in this file?  */
-
-/* ??? SGI assembler may core dump when compiling with -g.
-   Sometimes as succeeds, but then we get a linker error. (cmds.c in 072.sc)
-   Getting rid of .file solves both problems.  */
-#undef ASM_OUTPUT_FILENAME
-#define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
-do								\
-  {								\
-    fprintf (STREAM, "\t#.file\t%d ", NUM_SOURCE_FILENAMES);	\
-    output_quoted_string (STREAM, NAME);			\
-    fputs ("\n", STREAM);					\
-  }								\
-while (0)
-
-/* ??? SGI assembler gives warning whenever .lcomm is used.  */
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN)		   \
-do									   \
-  {									   \
-    if (mips_abi != ABI_32 && mips_abi != ABI_O64)			   \
-      {									   \
-	fprintf (STREAM, "%s\n", BSS_SECTION_ASM_OP);			   \
-	mips_declare_object (STREAM, NAME, "", ":\n", 0);		   \
-	ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT));	   \
-	ASM_OUTPUT_SKIP (STREAM, SIZE);					   \
-	fprintf (STREAM, "\t%s\n", POPSECTION_ASM_OP);			   \
-      }									   \
-    else								   \
-      mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE)); \
-  }									   \
-while (0)
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of uninitialized global DECL named
-   NAME whose size is SIZE bytes and alignment is ALIGN bytes.
-   Try to use asm_output_aligned_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
-
-/* Write the extra assembler code needed to declare an object properly.  */
-
-#undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL)			\
-do									\
- {									\
-   size_directive_output = 0;						\
-   if (!flag_inhibit_size_directive && DECL_SIZE (DECL))	\
-     {									\
-       size_directive_output = 1;					\
-       fprintf (STREAM, "\t%s\t ", SIZE_ASM_OP);			\
-       assemble_name (STREAM, NAME);					\
-       fprintf (STREAM, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL)));	\
-     }									\
-   mips_declare_object (STREAM, NAME, "", ":\n", 0);			\
- }									\
-while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
-	 assemble_name (FILE, name);					 \
-	 fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL))); \
-       }								 \
-   } while (0)
-
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
-			    ? "$" : ".")
-
-/* Profiling is supported via libprof1.a not -lc_p as in Irix 3.  */
-/* ??? If no mabi=X option give, but a mipsX option is, then should depend
-   on the mipsX option.  */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{!static:%{!shared: \
-     %{mabi=32:%{pg:gcrt1.o%s} \
-       %{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}} \
-     %{mabi=n32: \
-       %{mips4:%{pg:/usr/lib32/mips4/gcrt1.o%s} \
-         %{!pg:%{p:/usr/lib32/mips4/mcrt1.o%s /usr/lib32/mips4/libprof1.a%s} \
-           %{!p:/usr/lib32/mips4/crt1.o%s}}} \
-       %{!mips4:%{pg:/usr/lib32/mips3/gcrt1.o%s} \
-         %{!pg:%{p:/usr/lib32/mips3/mcrt1.o%s /usr/lib32/mips3/libprof1.a%s} \
-           %{!p:/usr/lib32/mips3/crt1.o%s}}}} \
-     %{mabi=64: \
-       %{mips4:%{pg:/usr/lib64/mips4/gcrt1.o} \
-         %{!pg:%{p:/usr/lib64/mips4/mcrt1.o /usr/lib64/mips4/libprof1.a} \
-           %{!p:/usr/lib64/mips4/crt1.o}}} \
-       %{!mips4:%{pg:/usr/lib64/mips3/gcrt1.o} \
-         %{!pg:%{p:/usr/lib64/mips3/mcrt1.o /usr/lib64/mips3/libprof1.a} \
-           %{!p:/usr/lib64/mips3/crt1.o}}}} \
-     %{!mabi*: \
-       %{mips4:%{pg:/usr/lib32/mips4/gcrt1.o%s} \
-         %{!pg:%{p:/usr/lib32/mips4/mcrt1.o%s /usr/lib32/mips4/libprof1.a%s} \
-           %{!p:/usr/lib32/mips4/crt1.o%s}}} \
-       %{!mips4:%{pg:/usr/lib32/mips3/gcrt1.o%s} \
-         %{!pg:%{p:/usr/lib32/mips3/mcrt1.o%s /usr/lib32/mips3/libprof1.a%s} \
-           %{!p:/usr/lib32/mips3/crt1.o%s}}}}}} \
-   %{static: \
-     %{mabi=32:%{pg:/usr/lib/nonshared/gcrt1.o%s} \
-       %{!pg:%{p:/usr/lib/nonshared/mcrt1.o%s /usr/lib/nonshared/libprof1.a%s} \
-         %{!p:/usr/lib/nonshared/crt1.o%s}}} \
-     %{mabi=n32: \
-       %{mips4:%{pg:/usr/lib32/mips4/nonshared/gcrt1.o%s} \
-         %{!pg:%{p:/usr/lib32/mips4/nonshared/mcrt1.o%s \
-             /usr/lib32/mips4/nonshared/libprof1.a%s} \
-           %{!p:/usr/lib32/mips4/nonshared/crt1.o%s}}} \
-       %{!mips4:%{pg:/usr/lib32/mips3/nonshared/gcrt1.o%s} \
-         %{!pg:%{p:/usr/lib32/mips3/nonshared/mcrt1.o%s \
-             /usr/lib32/mips3/nonshared/libprof1.a%s} \
-           %{!p:/usr/lib32/mips3/nonshared/crt1.o%s}}}} \
-     %{mabi=64: \
-       %{mips4:%{pg:/usr/lib64/mips4/nonshared/gcrt1.o} \
-         %{!pg:%{p:/usr/lib64/mips4/nonshared/mcrt1.o \
-             /usr/lib64/mips4/nonshared/libprof1.a} \
-           %{!p:/usr/lib64/mips4/nonshared/crt1.o}}} \
-       %{!mips4:%{pg:/usr/lib64/mips3/nonshared/gcrt1.o} \
-         %{!pg:%{p:/usr/lib64/mips3/nonshared/mcrt1.o \
-             /usr/lib64/mips3/nonshared/libprof1.a} \
-           %{!p:/usr/lib64/mips3/nonshared/crt1.o}}}} \
-     %{!mabi*: \
-       %{mips4:%{pg:/usr/lib32/mips4/nonshared/gcrt1.o%s} \
-         %{!pg:%{p:/usr/lib32/mips4/nonshared/mcrt1.o%s \
-             /usr/lib32/mips4/nonshared/libprof1.a%s} \
-           %{!p:/usr/lib32/mips4/nonshared/crt1.o%s}}} \
-       %{!mips4:%{pg:/usr/lib32/mips3/nonshared/gcrt1.o%s} \
-         %{!pg:%{p:/usr/lib32/mips3/nonshared/mcrt1.o%s \
-           /usr/lib32/mips3/nonshared/libprof1.a%s} \
-         %{!pg:%{p:/usr/lib32/mips3/nonshared/mcrt1.o%s \
-             /usr/lib32/mips3/nonshared/libprof1.a%s} \
-           %{!p:/usr/lib32/mips3/nonshared/crt1.o%s}}}}}} \
-   crtbegin.o%s"
-
-#undef LIB_SPEC
-#define LIB_SPEC \
-  "%{mabi=n32: %{mips4:-L/usr/lib32/mips4} %{!mips4:-L/usr/lib32/mips3} \
-     -L/usr/lib32} \
-   %{mabi=64: %{mips4:-L/usr/lib64/mips4} %{!mips4:-L/usr/lib64/mips3} \
-     -L/usr/lib64} \
-   %{!mabi*: %{mips4:-L/usr/lib32/mips4} %{!mips4:-L/usr/lib32/mips3} \
-     -L/usr/lib32} \
-   %{!shared: \
-     -dont_warn_unused %{p:libprof1.a%s}%{pg:libprof1.a%s} -lc -warn_unused}"
-
-/* Avoid getting two warnings for libgcc.a everytime we link.  */
-#undef LIBGCC_SPEC
-#define LIBGCC_SPEC "-dont_warn_unused -lgcc -warn_unused"
-
-/* ??? If no mabi=X option give, but a mipsX option is, then should depend
-   on the mipsX option.  */
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC \
-  "crtend.o%s \
-   %{!shared: \
-     %{mabi=32:crtn.o%s}\
-     %{mabi=n32:%{mips4:/usr/lib32/mips4/crtn.o%s}\
-       %{!mips4:/usr/lib32/mips3/crtn.o%s}}\
-     %{mabi=64:%{mips4:/usr/lib64/mips4/crtn.o%s}\
-       %{!mips4:/usr/lib64/mips3/crtn.o%s}}\
-     %{!mabi*:%{mips4:/usr/lib32/mips4/crtn.o%s}\
-       %{!mips4:/usr/lib32/mips3/crtn.o%s}}}"
-
-/* ??? If no mabi=X option give, but a mipsX option is, then should depend
-   on the mipsX option.  */
-#undef LINK_SPEC
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} %{w} \
-%{static: -non_shared} \
-%{!static: \
-  %{!shared: %{!non_shared: %{!call_shared: -call_shared -no_unresolved}}}} \
-%{rpath} -init __do_global_ctors -fini __do_global_dtors \
-%{shared:-hidden_symbol __do_global_ctors,__do_global_dtors,__EH_FRAME_BEGIN__,__frame_dummy} \
--_SYSTYPE_SVR4 -woff 131 \
-%{mabi=32: -32}%{mabi=n32: -n32}%{mabi=64: -64}%{!mabi*: -n32}"
diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
deleted file mode 100755
index f4ed424..0000000
--- a/gcc/config/mips/linux.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Definitions for MIPS running Linux-based GNU systems with ELF format.
-   Copyright (C) 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Required to keep collect2.c happy */
-#undef OBJECT_FORMAT_COFF 
-
-#define HAVE_ATEXIT
-
-/* If we don't set MASK_ABICALLS, we can't default to PIC. */
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_ABICALLS|MASK_GAS)
-
-
-/* Provide a STARTFILE_SPEC appropriate for GNU/Linux.  Here we add
-   the GNU/Linux magical crtbegin.o file (see crtstuff.c) which
-   provides part of the support for getting C++ file-scope static
-   object constructed before entering `main'. */
-
-#undef  STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{!shared: \
-     %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\
-   crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}"
-
-/* Provide a ENDFILE_SPEC appropriate for GNU/Linux.  Here we tack on
-   the GNU/Linux magical crtend.o file (see crtstuff.c) which
-   provides part of the support for getting C++ file-scope static
-   object constructed before entering `main', followed by a normal
-   GNU/Linux "finalizer" file, `crtn.o'.  */
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC \
-  "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s"
-
-/* From iris5.h */
-/* -G is incompatible with -KPIC which is the default, so only allow objects
-   in the small data section if the user explicitly asks for it.  */
-#undef MIPS_DEFAULT_GVALUE
-#define MIPS_DEFAULT_GVALUE 0
-
-/* Borrowed from sparc/linux.h */
-#undef LINK_SPEC
-#define LINK_SPEC "-Y P,/usr/lib %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-        %{rdynamic:-export-dynamic} \
-        %{!dynamic-linker:-dynamic-linker /lib/ld.so.1}} \
-        %{static:-static}}}"
-
-
-#undef SUBTARGET_ASM_SPEC
-#define SUBTARGET_ASM_SPEC "-KPIC"
-
-/* Undefine the following which were defined in elf.h.  This will cause the linux
-   port to continue to use collect2 for constructors/destructors.  These may be removed
-   when .ctor/.dtor section support is desired. */
-
-#undef CTORS_SECTION_ASM_OP
-#undef DTORS_SECTION_ASM_OP
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_sdata, in_rdata
-
-#undef INVOKE__main
-#undef NAME__MAIN
-#undef SYMBOL__MAIN
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS                                         \
-  SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \
-  SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP)
-
-#undef ASM_OUTPUT_CONSTRUCTOR
-#undef ASM_OUTPUT_DESTRUCTOR
-
-#undef CTOR_LIST_BEGIN
-#undef CTOR_LIST_END
-#undef DTOR_LIST_BEGIN
-#undef DTOR_LIST_END
-
-/*  End of undefines to turn off .ctor/.dtor section support */
diff --git a/gcc/config/mips/little.h b/gcc/config/mips/little.h
deleted file mode 100755
index 0ce01b4..0000000
--- a/gcc/config/mips/little.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* CYGNUS LOCAL: Entire file.  */
-
-/* Definitions of target machine for GNU compiler.
-   Little-endian flavor.
-   Copyright (c) 1997 Cygnus Support Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#define TARGET_ENDIAN_DEFAULT 0
-#define MULTILIB_ENDIAN_DEFAULT "EL"
diff --git a/gcc/config/mips/mips-5.h b/gcc/config/mips/mips-5.h
deleted file mode 100755
index f8b0941..0000000
--- a/gcc/config/mips/mips-5.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Definitions of target machine for GNU compiler.  MIPS RISC-OS 5.0
-   default version.
-   Copyright (C) 1992 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}"
-
-#include "mips/mips.h"
-
-/* Some assemblers have a bug that causes backslash escaped chars in .ascii
-   to be misassembled, so we just completely avoid it.  */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)			\
-do {							\
-  unsigned char *s;					\
-  int i;						\
-  for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++)	\
-    {							\
-      if ((i % 8) == 0)					\
-	fputs ("\n\t.byte\t", (FILE));			\
-      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
-    }							\
-  fputs ("\n", (FILE));					\
-} while (0)
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
deleted file mode 100755
index c4c217c..0000000
--- a/gcc/config/mips/mips.c
+++ /dev/null
@@ -1,8711 +0,0 @@
-/* Subroutines for insn-output.c for MIPS
-   Copyright (C) 1989, 90, 91, 93-97, 1998 Free Software Foundation, Inc.
-   Contributed by A. Lichnewsky, lich@inria.inria.fr.
-   Changes by Michael Meissner, meissner@osf.org.
-   64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
-   Brendan Eich, brendan@microunity.com.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
-   calling convention in 64 bit mode.  It doesn't work though, and should
-   be replaced with something better designed.  */
-
-#include "config.h"
-#include "system.h"
-#include <signal.h>
-
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "insn-attr.h"
-#include "insn-codes.h"
-#include "recog.h"
-#include "toplev.h"
-
-#undef MAX			/* sys/param.h may also define these */
-#undef MIN
-
-#include "tree.h"
-#include "expr.h"
-#include "flags.h"
-#include "reload.h"
-#include "output.h"
-
-#if defined(USG) || !defined(HAVE_STAB_H)
-#include "gstab.h"  /* If doing DBX on sysV, use our own stab.h.  */
-#else
-#include <stab.h>  /* On BSD, use the system's stab.h.  */
-#endif /* not USG */
-
-#ifdef __GNU_STAB__
-#define STAB_CODE_TYPE enum __stab_debug_code
-#else
-#define STAB_CODE_TYPE int
-#endif
-
-extern char  *mktemp ();
-extern tree   lookup_name ();
-
-/* Enumeration for all of the relational tests, so that we can build
-   arrays indexed by the test type, and not worry about the order
-   of EQ, NE, etc. */
-
-enum internal_test {
-    ITEST_EQ,
-    ITEST_NE,
-    ITEST_GT,
-    ITEST_GE,
-    ITEST_LT,
-    ITEST_LE,
-    ITEST_GTU,
-    ITEST_GEU,
-    ITEST_LTU,
-    ITEST_LEU,
-    ITEST_MAX
-  };
-
-
-struct constant;
-static enum internal_test map_test_to_internal_test	PROTO ((enum rtx_code));
-static int mips16_simple_memory_operand		PROTO ((rtx, rtx,
-							enum machine_mode));
-static int m16_check_op				PROTO ((rtx, int, int, int));
-static void block_move_loop			PROTO ((rtx, rtx, int, int,
-							rtx, rtx));
-static void block_move_call			PROTO ((rtx, rtx, rtx));
-static FILE *make_temp_file			PROTO ((void));
-static void save_restore_insns			PROTO ((int, rtx,
-							long, FILE *));
-static void mips16_output_gp_offset		PROTO ((FILE *, rtx));
-static void mips16_fp_args			PROTO ((FILE *, int, int));
-static void build_mips16_function_stub		PROTO ((FILE *));
-static void mips16_optimize_gp			PROTO ((rtx));
-static rtx add_constant				PROTO ((struct constant **,
-							rtx,
-							enum machine_mode));
-static void dump_constants			PROTO ((struct constant *,
-							rtx));
-static rtx mips_find_symbol			PROTO ((rtx));
-
-
-/* Global variables for machine-dependent things.  */
-
-/* Threshold for data being put into the small data/bss area, instead
-   of the normal data area (references to the small data/bss area take
-   1 instruction, and use the global pointer, references to the normal
-   data area takes 2 instructions).  */
-int mips_section_threshold = -1;
-
-/* Count the number of .file directives, so that .loc is up to date.  */
-int num_source_filenames = 0;
-
-/* Count the number of sdb related labels are generated (to find block
-   start and end boundaries).  */
-int sdb_label_count = 0;
-
-/* Next label # for each statement for Silicon Graphics IRIS systems. */
-int sym_lineno = 0;
-
-/* Non-zero if inside of a function, because the stupid MIPS asm can't
-   handle .files inside of functions.  */
-int inside_function = 0;
-
-/* Files to separate the text and the data output, so that all of the data
-   can be emitted before the text, which will mean that the assembler will
-   generate smaller code, based on the global pointer.  */
-FILE *asm_out_data_file;
-FILE *asm_out_text_file;
-
-/* Linked list of all externals that are to be emitted when optimizing
-   for the global pointer if they haven't been declared by the end of
-   the program with an appropriate .comm or initialization.  */
-
-struct extern_list
-{
-  struct extern_list *next;	/* next external */
-  char *name;			/* name of the external */
-  int size;			/* size in bytes */
-} *extern_head = 0;
-
-/* Name of the file containing the current function.  */
-char *current_function_file = "";
-
-/* Warning given that Mips ECOFF can't support changing files
-   within a function.  */
-int file_in_function_warning = FALSE;
-
-/* Whether to suppress issuing .loc's because the user attempted
-   to change the filename within a function.  */
-int ignore_line_number = FALSE;
-
-/* Number of nested .set noreorder, noat, nomacro, and volatile requests.  */
-int set_noreorder;
-int set_noat;
-int set_nomacro;
-int set_volatile;
-
-/* The next branch instruction is a branch likely, not branch normal.  */
-int mips_branch_likely;
-
-/* Count of delay slots and how many are filled.  */
-int dslots_load_total;
-int dslots_load_filled;
-int dslots_jump_total;
-int dslots_jump_filled;
-
-/* # of nops needed by previous insn */
-int dslots_number_nops;
-
-/* Number of 1/2/3 word references to data items (ie, not jal's).  */
-int num_refs[3];
-
-/* registers to check for load delay */
-rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
-
-/* Cached operands, and operator to compare for use in set/branch on
-   condition codes.  */
-rtx branch_cmp[2];
-
-/* what type of branch to use */
-enum cmp_type branch_type;
-
-/* Number of previously seen half-pic pointers and references.  */
-static int prev_half_pic_ptrs = 0;
-static int prev_half_pic_refs = 0;
-
-/* which cpu are we scheduling for */
-enum processor_type mips_cpu;
-
-/* which instruction set architecture to use.  */
-int mips_isa;
-
-#ifdef MIPS_ABI_DEFAULT
-/* Which ABI to use.  This is defined to a constant in mips.h if the target
-   doesn't support multiple ABIs.  */
-int mips_abi;
-#endif
-
-/* Strings to hold which cpu and instruction set architecture to use.  */
-char *mips_cpu_string;		/* for -mcpu=<xxx> */
-char *mips_isa_string;		/* for -mips{1,2,3,4} */
-char *mips_abi_string;		/* for -mabi={32,n32,64,eabi} */
-
-/* Whether we are generating mips16 code.  This is a synonym for
-   TARGET_MIPS16, and exists for use as an attribute.  */
-int mips16;
-
-/* This variable is set by -mno-mips16.  We only care whether
-   -mno-mips16 appears or not, and using a string in this fashion is
-   just a way to avoid using up another bit in target_flags.  */
-char *mips_no_mips16_string;
-
-/* Whether we are generating mips16 hard float code.  In mips16 mode
-   we always set TARGET_SOFT_FLOAT; this variable is nonzero if
-   -msoft-float was not specified by the user, which means that we
-   should arrange to call mips32 hard floating point code.  */
-int mips16_hard_float;
-
-/* This variable is set by -mentry.  We only care whether -mentry
-   appears or not, and using a string in this fashion is just a way to
-   avoid using up another bit in target_flags.  */
-char *mips_entry_string;
-
-/* Whether we should entry and exit pseudo-ops in mips16 mode.  */
-int mips_entry;
-
-/* If TRUE, we split addresses into their high and low parts in the RTL.  */
-int mips_split_addresses;
-
-/* Generating calls to position independent functions?  */
-enum mips_abicalls_type mips_abicalls;
-
-/* High and low marks for floating point values which we will accept
-   as legitimate constants for LEGITIMATE_CONSTANT_P.  These are
-   initialized in override_options.  */
-REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
-
-/* Array giving truth value on whether or not a given hard register
-   can support a given mode.  */
-char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
-
-/* The mode that will be used to save a given gpr on the stack.  Note
-   the entry for $0 is special; it indicates the generic size of a gpr
-   save/restore by the prologue/epilogue and must be the maximum mode
-   ever used to save a GPR.  This is typically WORD_MODE.  */
-enum machine_mode mips_reg_mode[GP_REG_NUM];
-
-/* Current frame information calculated by compute_frame_size.  */
-struct mips_frame_info current_frame_info;
-
-/* Zero structure to initialize current_frame_info.  */
-struct mips_frame_info zero_frame_info;
-
-/* Temporary filename used to buffer .text until end of program
-   for -mgpopt.  */
-static char *temp_filename;
-
-/* Pseudo-reg holding the address of the current function when
-   generating embedded PIC code.  Created by LEGITIMIZE_ADDRESS, used
-   by mips_finalize_pic if it was created.  */
-rtx embedded_pic_fnaddr_rtx;
-
-/* The length of all strings seen when compiling for the mips16.  This
-   is used to tell how many strings are in the constant pool, so that
-   we can see if we may have an overflow.  This is reset each time the
-   constant pool is output.  */
-int mips_string_length;
-
-/* Pseudo-reg holding the value of $28 in a mips16 function which
-   refers to GP relative global variables.  */
-rtx mips16_gp_pseudo_rtx;
-
-/* In mips16 mode, we build a list of all the string constants we see
-   in a particular function.  */
-
-struct string_constant
-{
-  struct string_constant *next;
-  char *label;
-};
-
-static struct string_constant *string_constants;
-
-/* CYGNUS LOCAL law */
-/* Specify power of two alignment for loop starts, labels after barriers
-   and functions.  Also specify maximum fill/skip allowed to achieve those
-   alignments (in bytes).
-
-   These are strings filled in by the generic code with the user arguments,
-   they are parsed in OVERRIDE_OPTIONS, then never referenced again.  */
-char *mips_align_loops_string;
-char *mips_max_skip_loops_string;
-char *mips_align_jumps_string;
-char *mips_max_skip_jumps_string;
-char *mips_align_funcs_string;
-char *mips_max_skip_funcs_string;
-
-/* Specify power of two alignment for loop starts, labels after barriers
-   and functions.  Also specify maximum fill/skip allowed to achieve those
-   alignments (in bytes).
-
-   Once the above strings are parsed, the resulting values are placed in
-   these variables.  */
-int mips_align_loops;
-int mips_max_skip_loops;
-int mips_align_jumps;
-int mips_max_skip_jumps;
-int mips_align_funcs;
-int mips_max_skip_funcs;
-/* END CYGNUS LOCAL */
-
-/* List of all MIPS punctuation characters used by print_operand.  */
-char mips_print_operand_punct[256];
-
-/* Map GCC register number to debugger register number.  */
-int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
-
-/* Buffer to use to enclose a load/store operation with %{ %} to
-   turn on .set volatile.  */
-static char volatile_buffer[60];
-
-/* Hardware names for the registers.  If -mrnames is used, this
-   will be overwritten with mips_sw_reg_names.  */
-
-char mips_reg_names[][8] =
-{
- "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
- "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
- "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
- "$24",  "$25",  "$26",  "$27",  "$28",  "$sp",  "$fp",  "$31",
- "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
- "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
- "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
- "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
- "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
- "$fcc5","$fcc6","$fcc7","$rap"
-};
-
-/* Mips software names for the registers, used to overwrite the
-   mips_reg_names array.  */
-
-char mips_sw_reg_names[][8] =
-{
-  "$zero","$at",  "$v0",  "$v1",  "$a0",  "$a1",  "$a2",  "$a3",
-  "$t0",  "$t1",  "$t2",  "$t3",  "$t4",  "$t5",  "$t6",  "$t7",
-  "$s0",  "$s1",  "$s2",  "$s3",  "$s4",  "$s5",  "$s6",  "$s7",
-  "$t8",  "$t9",  "$k0",  "$k1",  "$gp",  "$sp",  "$fp",  "$ra",
-  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
-  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
-  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
-  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
-  "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
-  "$fcc5","$fcc6","$fcc7","$rap"
-};
-
-/* Map hard register number to register class */
-enum reg_class mips_regno_to_class[] =
-{
-  GR_REGS,	GR_REGS,	M16_NA_REGS,	M16_NA_REGS,
-  M16_REGS,	M16_REGS,	M16_REGS,	M16_REGS,
-  GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,
-  GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,
-  M16_NA_REGS,	M16_NA_REGS,	GR_REGS,	GR_REGS,
-  GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,
-  T_REG,	GR_REGS,	GR_REGS,	GR_REGS,
-  GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,
-  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
-  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
-  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
-  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
-  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
-  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
-  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
-  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
-  HI_REG,	LO_REG,		HILO_REG,	ST_REGS,
-  ST_REGS,	ST_REGS,	ST_REGS,	ST_REGS,
-  ST_REGS,	ST_REGS,	ST_REGS,	GR_REGS
-};
-
-/* Map register constraint character to register class.  */
-enum reg_class mips_char_to_class[256] =
-{
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-};
-
-
-/* Return truth value of whether OP can be used as an operands
-   where a register or 16 bit unsigned integer is needed.  */
-
-int
-uns_arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
-    return 1;
-
-  return register_operand (op, mode);
-}
-
-/* Return truth value of whether OP can be used as an operands
-   where a 16 bit integer is needed  */
-
-int
-arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
-    return 1;
-
-  /* On the mips16, a GP relative value is a signed 16 bit offset.  */
-  if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
-    return 1;
-
-  return register_operand (op, mode);
-}
-
-/* Return truth value of whether OP can be used as an operand in a two
-   address arithmetic insn (such as set 123456,%o4) of mode MODE.  */
-
-int
-arith32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return 1;
-
-  return register_operand (op, mode);
-}
-
-/* Return truth value of whether OP is a integer which fits in 16 bits  */
-
-int
-small_int (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
-}
-
-/* Return truth value of whether OP is a 32 bit integer which is too big to
-   be loaded with one instruction.  */
-
-int
-large_int (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  HOST_WIDE_INT value;
-
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-
-  value = INTVAL (op);
-
-  /* ior reg,$r0,value */
-  if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
-    return 0;
-
-  /* subu reg,$r0,value */
-  if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
-    return 0;
-
-  /* lui reg,value>>16 */
-  if ((value & 0x0000ffff) == 0)
-    return 0;
-
-  return 1;
-}
-
-/* Return truth value of whether OP is a register or the constant 0.
-   In mips16 mode, we only accept a register, since the mips16 does
-   not have $0.  */
-
-int
-reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case CONST_INT:
-      if (TARGET_MIPS16)
-	return 0;
-      return INTVAL (op) == 0;
-
-    case CONST_DOUBLE:
-      if (TARGET_MIPS16)
-	return 0;
-      return op == CONST0_RTX (mode);
-
-    case REG:
-    case SUBREG:
-      return register_operand (op, mode);
-
-    default:
-      break;
-    }
-
-  return 0;
-}
-
-
-/* Return truth value of whether OP is a register or the constant 0,
-   even in mips16 mode. */
-
-int
-true_reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case CONST_INT:
-      return INTVAL (op) == 0;
-
-    case CONST_DOUBLE:
-      return op == CONST0_RTX (mode);
-
-    case REG:
-    case SUBREG:
-      return register_operand (op, mode);
-
-    default:
-      break;
-    }
-
-  return 0;
-}
-
-/* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant.  */
-
-int
-mips_const_double_ok (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  REAL_VALUE_TYPE d;
-
-  if (GET_CODE (op) != CONST_DOUBLE)
-    return 0;
-
-  if (mode == VOIDmode)
-    return 1;
-
-  if (mode != SFmode && mode != DFmode)
-    return 0;
-
-  if (op == CONST0_RTX (mode))
-    return 1;
-
-  /* ??? li.s does not work right with SGI's Irix 6 assembler.  */
-  if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
-    return 0;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (d, op);
-
-  if (REAL_VALUE_ISNAN (d))
-    return FALSE;
-
-  if (REAL_VALUE_NEGATIVE (d))
-    d = REAL_VALUE_NEGATE (d);
-
-  if (mode == DFmode)
-    {
-      if (REAL_VALUES_LESS (d, dfhigh)
-	  && REAL_VALUES_LESS (dflow, d))
-	return 1;
-    }
-  else
-    {
-      if (REAL_VALUES_LESS (d, sfhigh)
-	  && REAL_VALUES_LESS (sflow, d))
-	return 1;
-    }
-
-  return 0;
-}
-
-/* Accept the floating point constant 1 in the appropriate mode.  */
-
-int
-const_float_1_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  REAL_VALUE_TYPE d;
-  static REAL_VALUE_TYPE onedf;
-  static REAL_VALUE_TYPE onesf;
-  static int one_initialized;
-
-  if (GET_CODE (op) != CONST_DOUBLE
-      || mode != GET_MODE (op)
-      || (mode != DFmode && mode != SFmode))
-    return 0;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (d, op);
-
-  /* We only initialize these values if we need them, since we will
-     never get called unless mips_isa >= 4.  */
-  if (! one_initialized)
-    {
-      onedf = REAL_VALUE_ATOF ("1.0", DFmode);
-      onesf = REAL_VALUE_ATOF ("1.0", SFmode);
-      one_initialized = 1;
-    }
-
-  if (mode == DFmode)
-    return REAL_VALUES_EQUAL (d, onedf);
-  else
-    return REAL_VALUES_EQUAL (d, onesf);
-}
-
-/* Return true if a memory load or store of REG plus OFFSET in MODE
-   can be represented in a single word on the mips16.  */
-
-static int
-mips16_simple_memory_operand (reg, offset, mode)
-     rtx reg;
-     rtx offset;
-     enum machine_mode mode;
-{
-  int size, off;
-
-  if (mode == BLKmode)
-    {
-      /* We can't tell, because we don't know how the value will
-         eventually be accessed.  Returning 0 here does no great
-         harm; it just prevents some possible instruction scheduling.  */
-      return 0;
-    }
-
-  size = GET_MODE_SIZE (mode);
-
-  if (INTVAL (offset) % size != 0)
-    return 0;
-  if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
-    off = 0x100;
-  else
-    off = 0x20;
-  if (INTVAL (offset) >= 0 && INTVAL (offset) < off * size)
-    return 1;
-  return 0;
-}
-
-/* Return truth value if a memory operand fits in a single instruction
-   (ie, register + small offset).  */
-
-int
-simple_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  rtx addr, plus0, plus1;
-
-  /* Eliminate non-memory operations */
-  if (GET_CODE (op) != MEM)
-    return 0;
-
-  /* dword operations really put out 2 instructions, so eliminate them.  */
-  /* ??? This isn't strictly correct.  It is OK to accept multiword modes
-     here, since the length attributes are being set correctly, but only
-     if the address is offsettable.  LO_SUM is not offsettable.  */
-  if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD)
-    return 0;
-
-  /* Decode the address now.  */
-  addr = XEXP (op, 0);
-  switch (GET_CODE (addr))
-    {
-    case REG:
-    case LO_SUM:
-      return 1;
-
-    case CONST_INT:
-      if (TARGET_MIPS16)
-	return 0;
-      return SMALL_INT (op);
-
-    case PLUS:
-      plus0 = XEXP (addr, 0);
-      plus1 = XEXP (addr, 1);
-      if (GET_CODE (plus0) == REG
-	  && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
-	  && (! TARGET_MIPS16
-	      || mips16_simple_memory_operand (plus0, plus1, mode)))
-	return 1;
-
-      else if (GET_CODE (plus1) == REG
-	       && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
-	       && (! TARGET_MIPS16
-		   || mips16_simple_memory_operand (plus1, plus0, mode)))
-	return 1;
-
-      else
-	return 0;
-
-#if 0
-      /* We used to allow small symbol refs here (ie, stuff in .sdata
-	 or .sbss), but this causes some bugs in G++.  Also, it won't
-	 interfere if the MIPS linker rewrites the store instruction
-	 because the function is PIC.  */
-
-    case LABEL_REF:		/* never gp relative */
-      break;
-
-    case CONST:
-      /* If -G 0, we can never have a GP relative memory operation.
-	 Also, save some time if not optimizing.  */
-      if (!TARGET_GP_OPT)
-	return 0;
-
-      {
-	rtx offset = const0_rtx;
-	addr = eliminate_constant_term (XEXP (addr, 0), &offset);
-	if (GET_CODE (op) != SYMBOL_REF)
-	  return 0;
-
-	/* let's be paranoid.... */
-	if (! SMALL_INT (offset))
-	  return 0;
-      }
-
-      /* fall through */
-
-    case SYMBOL_REF:
-      return SYMBOL_REF_FLAG (addr);
-#endif
-
-      /* This SYMBOL_REF case is for the mips16.  If the above case is
-         reenabled, this one should be merged in.  */
-    case SYMBOL_REF:
-      /* References to the constant pool on the mips16 use a small
-         offset if the function is small.  The only time we care about
-         getting this right is during delayed branch scheduling, so
-         don't need to check until then.  The machine_dependent_reorg
-         function will set the total length of the instructions used
-         in the function in current_frame_info.  If that is small
-         enough, we know for sure that this is a small offset.  It
-         would be better if we could take into account the location of
-         the instruction within the function, but we can't, because we
-         don't know where we are.  */
-      if (TARGET_MIPS16
-	  && CONSTANT_POOL_ADDRESS_P (addr)
-	  && current_frame_info.insns_len > 0)
-	{
-	  long size;
-
-	  size = current_frame_info.insns_len + get_pool_size ();
-	  if (GET_MODE_SIZE (mode) == 4)
-	    return size < 4 * 0x100;
-	  else if (GET_MODE_SIZE (mode) == 8)
-	    return size < 8 * 0x20;
-	  else
-	    return 0;
-	}
-
-      return 0;
-
-    default:
-      break;
-    }
-
-  return 0;
-}
-
-/* Return nonzero for a memory address that can be used to load or store
-   a doubleword.  */
-
-int
-double_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  rtx addr;
-
-  if (GET_CODE (op) != MEM
-      || ! memory_operand (op, mode))
-    {
-      /* During reload, we accept a pseudo register if it has an
-	 appropriate memory address.  If we don't do this, we will
-	 wind up reloading into a register, and then reloading that
-	 register from memory, when we could just reload directly from
-	 memory.  */
-      if (reload_in_progress
-	  && GET_CODE (op) == REG
-	  && REGNO (op) >= FIRST_PSEUDO_REGISTER
-	  && reg_renumber[REGNO (op)] < 0
-	  && reg_equiv_mem[REGNO (op)] != 0
-	  && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
-	return 1;
-
-      /* All reloaded addresses are valid in TARGET_64BIT mode.  This is
-	 the same test performed for 'm' in find_reloads.  */
-
-      if (reload_in_progress
-	  && TARGET_64BIT
-	  && (GET_CODE (op) == MEM
-	      || (GET_CODE (op) == REG
-		  && REGNO (op) >= FIRST_PSEUDO_REGISTER
-		  && reg_renumber[REGNO (op)] < 0)))
-	return 1;
-
-      if (reload_in_progress
-	  && TARGET_MIPS16
-	  && GET_CODE (op) == MEM)
-	{
-	  rtx addr;
-
-	  addr = XEXP (op, 0);
-
-	  /* During reload on the mips16, we accept a large offset
-	     from the frame pointer or the stack pointer.  This large
-	     address will get reloaded anyhow.  */
-	  if (GET_CODE (addr) == PLUS
-	      && GET_CODE (XEXP (addr, 0)) == REG
-	      && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
-		  || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
-	      && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
-		   && ! SMALL_INT (XEXP (addr, 1)))
-		  || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
-		      && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
-	    return 1;
-
-	  /* Similarly, we accept a case where the memory address is
-             itself on the stack, and will be reloaded. */
-	  if (GET_CODE (addr) == MEM)
-	    {
-	      rtx maddr;
-
-	      maddr = XEXP (addr, 0);
-	      if (GET_CODE (maddr) == PLUS
-		  && GET_CODE (XEXP (maddr, 0)) == REG
-		  && (REGNO (XEXP (maddr, 0)) == HARD_FRAME_POINTER_REGNUM
-		      || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
-		  && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
-		       && ! SMALL_INT (XEXP (maddr, 1)))
-		      || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
-			  && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
-		return 1;
-	    }
-
-	  /* We also accept the same case when we have a 16 bit signed
-	     offset mixed in as well.  The large address will get
-	     reloaded, and the 16 bit offset will be OK.  */
-	  if (GET_CODE (addr) == PLUS
-	      && GET_CODE (XEXP (addr, 0)) == MEM
-	      && GET_CODE (XEXP (addr, 1)) == CONST_INT
-	      && SMALL_INT (XEXP (addr, 1)))
-	    {
-	      addr = XEXP (XEXP (addr, 0), 0);
-	      if (GET_CODE (addr) == PLUS
-		  && GET_CODE (XEXP (addr, 0)) == REG
-		  && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
-		      || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
-		  && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
-		       && ! SMALL_INT (XEXP (addr, 1)))
-		      || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
-			  && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
-		return 1;
-	    }
-	}
-
-      return 0;
-    }
-
-  if (TARGET_64BIT)
-    {
-      /* In this case we can use an instruction like sd.  */
-      return 1;
-    }
-
-  /* Make sure that 4 added to the address is a valid memory address.
-     This essentially just checks for overflow in an added constant.  */
-
-  addr = XEXP (op, 0);
-
-  if (CONSTANT_ADDRESS_P (addr))
-    return 1;
-
-  return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
-			    ? SImode
-			    : SFmode),
-			   plus_constant_for_output (addr, 4));
-}
-
-/* Return nonzero if the code of this rtx pattern is EQ or NE.  */
-
-int
-equality_op (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (mode != GET_MODE (op))
-    return 0;
-
-  return GET_CODE (op) == EQ || GET_CODE (op) == NE;
-}
-
-/* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
-
-int
-cmp_op (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (mode != GET_MODE (op))
-    return 0;
-
-  return GET_RTX_CLASS (GET_CODE (op)) == '<';
-}
-
-/* Return nonzero if the operand is either the PC or a label_ref.  */
-
-int
-pc_or_label_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (op == pc_rtx)
-    return 1;
-
-  if (GET_CODE (op) == LABEL_REF)
-    return 1;
-
-  return 0;
-}
-
-/* Test for a valid operand for a call instruction.
-   Don't allow the arg pointer register or virtual regs
-   since they may change into reg + const, which the patterns
-   can't handle yet.  */
-
-int
-call_insn_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (CONSTANT_ADDRESS_P (op)
-	  || (GET_CODE (op) == REG && op != arg_pointer_rtx
-	      && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
-		    && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
-}
-
-/* Return nonzero if OPERAND is valid as a source operand for a move
-   instruction.  */
-
-int
-move_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  /* Accept any general operand after reload has started; doing so
-     avoids losing if reload does an in-place replacement of a register
-     with a SYMBOL_REF or CONST.  */
-  return (general_operand (op, mode)
-	  && (! (mips_split_addresses && mips_check_split (op, mode))
-	      || reload_in_progress || reload_completed)
-	  && ! (TARGET_MIPS16
-		&& GET_CODE (op) == SYMBOL_REF
-		&& ! mips16_constant (op, mode, 1, 0)));
-}
-
-/* Return nonzero if OPERAND is valid as a source operand for movdi.
-   This accepts not only general_operand, but also sign extended
-   constants and registers.  We need to accept sign extended constants
-   in case a sign extended register which is used in an expression,
-   and is equivalent to a constant, is spilled.  */
-
-int
-movdi_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (TARGET_64BIT
-      && mode == DImode
-      && GET_CODE (op) == SIGN_EXTEND
-      && GET_MODE (op) == DImode
-      && (GET_MODE (XEXP (op, 0)) == SImode
-	  || (GET_CODE (XEXP (op, 0)) == CONST_INT
-	      && GET_MODE (XEXP (op, 0)) == VOIDmode))
-      && (register_operand (XEXP (op, 0), SImode)
-	  || immediate_operand (XEXP (op, 0), SImode)))
-    return 1;
-
-  return (general_operand (op, mode)
-	  && ! (TARGET_MIPS16
-		&& GET_CODE (op) == SYMBOL_REF
-		&& ! mips16_constant (op, mode, 1, 0)));
-}
-
-/* Like register_operand, but when in 64 bit mode also accept a sign
-   extend of a 32 bit register, since the value is known to be already
-   sign extended.  */
-
-int
-se_register_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (TARGET_64BIT
-      && mode == DImode
-      && GET_CODE (op) == SIGN_EXTEND
-      && GET_MODE (op) == DImode
-      && GET_MODE (XEXP (op, 0)) == SImode
-      && register_operand (XEXP (op, 0), SImode))
-    return 1;
-
-  return register_operand (op, mode);
-}
-
-/* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
-   extend of a 32 bit register, since the value is known to be already
-   sign extended.  */
-
-int
-se_reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (TARGET_64BIT
-      && mode == DImode
-      && GET_CODE (op) == SIGN_EXTEND
-      && GET_MODE (op) == DImode
-      && GET_MODE (XEXP (op, 0)) == SImode
-      && register_operand (XEXP (op, 0), SImode))
-    return 1;
-
-  return reg_or_0_operand (op, mode);
-}
-
-/* Like uns_arith_operand, but when in 64 bit mode also accept a sign
-   extend of a 32 bit register, since the value is known to be already
-   sign extended.  */
-
-int
-se_uns_arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (TARGET_64BIT
-      && mode == DImode
-      && GET_CODE (op) == SIGN_EXTEND
-      && GET_MODE (op) == DImode
-      && GET_MODE (XEXP (op, 0)) == SImode
-      && register_operand (XEXP (op, 0), SImode))
-    return 1;
-
-  return uns_arith_operand (op, mode);
-}
-
-/* Like arith_operand, but when in 64 bit mode also accept a sign
-   extend of a 32 bit register, since the value is known to be already
-   sign extended.  */
-
-int
-se_arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (TARGET_64BIT
-      && mode == DImode
-      && GET_CODE (op) == SIGN_EXTEND
-      && GET_MODE (op) == DImode
-      && GET_MODE (XEXP (op, 0)) == SImode
-      && register_operand (XEXP (op, 0), SImode))
-    return 1;
-
-  return arith_operand (op, mode);
-}
-
-/* Like nonmemory_operand, but when in 64 bit mode also accept a sign
-   extend of a 32 bit register, since the value is known to be already
-   sign extended.  */
-
-int
-se_nonmemory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (TARGET_64BIT
-      && mode == DImode
-      && GET_CODE (op) == SIGN_EXTEND
-      && GET_MODE (op) == DImode
-      && GET_MODE (XEXP (op, 0)) == SImode
-      && register_operand (XEXP (op, 0), SImode))
-    return 1;
-
-  return nonmemory_operand (op, mode);
-}
-
-/* Like nonimmediate_operand, but when in 64 bit mode also accept a
-   sign extend of a 32 bit register, since the value is known to be
-   already sign extended.  */
-
-int
-se_nonimmediate_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (TARGET_64BIT
-      && mode == DImode
-      && GET_CODE (op) == SIGN_EXTEND
-      && GET_MODE (op) == DImode
-      && GET_MODE (XEXP (op, 0)) == SImode
-      && register_operand (XEXP (op, 0), SImode))
-    return 1;
-
-  return nonimmediate_operand (op, mode);
-}
-
-/* Accept any operand that can appear in a mips16 constant table
-   instruction.  We can't use any of the standard operand functions
-   because for these instructions we accept values that are not
-   accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs.  */
-
-int
-consttable_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return CONSTANT_P (op);
-}
-
-/* Return nonzero if we split the address into high and low parts.  */
-
-/* ??? We should also handle reg+array somewhere.  We get four
-   instructions currently, lui %hi/addui %lo/addui reg/lw.  Better is
-   lui %hi/addui reg/lw %lo.  Fixing GO_IF_LEGITIMATE_ADDRESS to accept
-   (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
-   out of the address, then we have 4 instructions to combine.  Perhaps
-   add a 3->2 define_split for combine.  */
-
-/* ??? We could also split a CONST_INT here if it is a large_int().
-   However, it doesn't seem to be very useful to have %hi(constant).
-   We would be better off by doing the masking ourselves and then putting
-   the explicit high part of the constant in the RTL.  This will give better
-   optimization.  Also, %hi(constant) needs assembler changes to work.
-   There is already a define_split that does this.  */
-
-int
-mips_check_split (address, mode)
-     rtx address;
-     enum machine_mode mode;
-{     
-  /* ??? This is the same check used in simple_memory_operand.
-     We use it here because LO_SUM is not offsettable.  */
-  if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
-    return 0;
-
-  if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
-      || (GET_CODE (address) == CONST
-	  && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
-	  && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
-      || GET_CODE (address) == LABEL_REF)
-    return 1;
-
-  return 0;
-}
-
-/* We need a lot of little routines to check constant values on the
-   mips16.  These are used to figure out how long the instruction will
-   be.  It would be much better to do this using constraints, but
-   there aren't nearly enough letters available.  */
-
-static int
-m16_check_op (op, low, high, mask)
-     rtx op;
-     int low;
-     int high;
-     int mask;
-{
-  return (GET_CODE (op) == CONST_INT
-	  && INTVAL (op) >= low
-	  && INTVAL (op) <= high
-	  && (INTVAL (op) & mask) == 0);
-}
-
-int
-m16_uimm3_b (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, 0x1, 0x8, 0);
-}
-
-int
-m16_simm4_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, - 0x8, 0x7, 0);
-}
-
-int
-m16_nsimm4_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, - 0x7, 0x8, 0);
-}
-
-int
-m16_simm5_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, - 0x10, 0xf, 0);
-}
-
-int
-m16_nsimm5_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, - 0xf, 0x10, 0);
-}
-
-int
-m16_uimm5_4 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
-}
-
-int
-m16_nuimm5_4 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
-}
-
-int
-m16_simm8_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, - 0x80, 0x7f, 0);
-}
-
-int
-m16_nsimm8_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, - 0x7f, 0x80, 0);
-}
-
-int
-m16_uimm8_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, 0x0, 0xff, 0);
-}
-
-int
-m16_nuimm8_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, - 0xff, 0x0, 0);
-}
-
-int
-m16_uimm8_m1_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, - 0x1, 0xfe, 0);
-}
-
-int
-m16_uimm8_4 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, 0x0, 0xff << 2, 3);
-}
-
-int
-m16_nuimm8_4 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
-}
-
-int
-m16_simm8_8 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
-}
-
-int
-m16_nsimm8_8 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
-}
-
-/* References to the string table on the mips16 only use a small
-   offset if the function is small.  See the comment in the SYMBOL_REF
-   case in simple_memory_operand.  We can't check for LABEL_REF here,
-   because the offset is always large if the label is before the
-   referencing instruction.  */
-
-int
-m16_usym8_4 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) == SYMBOL_REF
-      && SYMBOL_REF_FLAG (op)
-      && current_frame_info.insns_len > 0
-      && XSTR (op, 0)[0] == '*'
-      && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
-		  sizeof LOCAL_LABEL_PREFIX - 1) == 0
-      && (current_frame_info.insns_len + get_pool_size () + mips_string_length
-	  < 4 * 0x100))
-    {
-      struct string_constant *l;
-
-      /* Make sure this symbol is on thelist of string constants to be
-         output for this function.  It is possible that it has already
-         been output, in which case this requires a large offset.  */
-      for (l = string_constants; l != NULL; l = l->next)
-	if (strcmp (l->label, XSTR (op, 0)) == 0)
-	  return 1;
-    }
-
-  return 0;
-}
-
-int
-m16_usym5_4 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) == SYMBOL_REF
-      && SYMBOL_REF_FLAG (op)
-      && current_frame_info.insns_len > 0
-      && XSTR (op, 0)[0] == '*'
-      && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
-		  sizeof LOCAL_LABEL_PREFIX - 1) == 0
-      && (current_frame_info.insns_len + get_pool_size () + mips_string_length
-	  < 4 * 0x20))
-    {
-      struct string_constant *l;
-
-      /* Make sure this symbol is on thelist of string constants to be
-         output for this function.  It is possible that it has already
-         been output, in which case this requires a large offset.  */
-      for (l = string_constants; l != NULL; l = l->next)
-	if (strcmp (l->label, XSTR (op, 0)) == 0)
-	  return 1;
-    }
-
-  return 0;
-}
-
-/* Returns an operand string for the given instruction's delay slot,
-   after updating filled delay slot statistics.
-
-   We assume that operands[0] is the target register that is set.
-
-   In order to check the next insn, most of this functionality is moved
-   to FINAL_PRESCAN_INSN, and we just set the global variables that
-   it needs.  */
-
-/* ??? This function no longer does anything useful, because final_prescan_insn
-   now will never emit a nop.  */
-
-char *
-mips_fill_delay_slot (ret, type, operands, cur_insn)
-     char *ret;			/* normal string to return */
-     enum delay_type type;	/* type of delay */
-     rtx operands[];		/* operands to use */
-     rtx cur_insn;		/* current insn */
-{
-  register rtx set_reg;
-  register enum machine_mode mode;
-  register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
-  register int num_nops;
-
-  if (type == DELAY_LOAD || type == DELAY_FCMP)
-    num_nops = 1;
-
-  else if (type == DELAY_HILO)
-    num_nops = 2;
-
-
-  else
-    num_nops = 0;
-
-  /* Make sure that we don't put nop's after labels.  */
-  next_insn = NEXT_INSN (cur_insn);
-  while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
-    next_insn = NEXT_INSN (next_insn);
-
-  dslots_load_total += num_nops;
-  if (TARGET_DEBUG_F_MODE
-      || !optimize
-      || type == DELAY_NONE
-      || operands == 0
-      || cur_insn == 0
-      || next_insn == 0
-      || GET_CODE (next_insn) == CODE_LABEL
-      || (set_reg = operands[0]) == 0)
-    {
-      dslots_number_nops = 0;
-      mips_load_reg  = 0;
-      mips_load_reg2 = 0;
-      mips_load_reg3 = 0;
-      mips_load_reg4 = 0;
-      return ret;
-    }
-
-  set_reg = operands[0];
-  if (set_reg == 0)
-    return ret;
-
-  while (GET_CODE (set_reg) == SUBREG)
-    set_reg = SUBREG_REG (set_reg);
-
-  mode = GET_MODE (set_reg);
-  dslots_number_nops = num_nops;
-  mips_load_reg = set_reg;
-  if (GET_MODE_SIZE (mode)
-      > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
-    mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1);
-  else
-    mips_load_reg2 = 0;
-
-  if (type == DELAY_HILO)
-    {
-      mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST);
-      mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1);
-    }
-  else
-    {
-      mips_load_reg3 = 0;
-      mips_load_reg4 = 0;
-    }
-
-  return ret;
-}
-
-
-/* Determine whether a memory reference takes one (based off of the GP
-   pointer), two (normal), or three (label + reg) instructions, and bump the
-   appropriate counter for -mstats.  */
-
-void
-mips_count_memory_refs (op, num)
-     rtx op;
-     int num;
-{
-  int additional = 0;
-  int n_words = 0;
-  rtx addr, plus0, plus1;
-  enum rtx_code code0, code1;
-  int looping;
-
-  if (TARGET_DEBUG_B_MODE)
-    {
-      fprintf (stderr, "\n========== mips_count_memory_refs:\n");
-      debug_rtx (op);
-    }
-
-  /* Skip MEM if passed, otherwise handle movsi of address.  */
-  addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
-
-  /* Loop, going through the address RTL.  */
-  do
-    {
-      looping = FALSE;
-      switch (GET_CODE (addr))
-	{
-	case REG:
-	case CONST_INT:
-	case LO_SUM:
-	  break;
-
-	case PLUS:
-	  plus0 = XEXP (addr, 0);
-	  plus1 = XEXP (addr, 1);
-	  code0 = GET_CODE (plus0);
-	  code1 = GET_CODE (plus1);
-
-	  if (code0 == REG)
-	    {
-	      additional++;
-	      addr = plus1;
-	      looping = 1;
-	      continue;
-	    }
-
-	  if (code0 == CONST_INT)
-	    {
-	      addr = plus1;
-	      looping = 1;
-	      continue;
-	    }
-
-	  if (code1 == REG)
-	    {
-	      additional++;
-	      addr = plus0;
-	      looping = 1;
-	      continue;
-	    }
-
-	  if (code1 == CONST_INT)
-	    {
-	      addr = plus0;
-	      looping = 1;
-	      continue;
-	    }
-
-	  if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
-	    {
-	      addr = plus0;
-	      looping = 1;
-	      continue;
-	    }
-
-	  if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
-	    {
-	      addr = plus1;
-	      looping = 1;
-	      continue;
-	    }
-
-	  break;
-
-	case LABEL_REF:
-	  n_words = 2;		/* always 2 words */
-	  break;
-
-	case CONST:
-	  addr = XEXP (addr, 0);
-	  looping = 1;
-	  continue;
-
-	case SYMBOL_REF:
-	  n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
-	  break;
-
-	default:
-	  break;
-	}
-    }
-  while (looping);
-
-  if (n_words == 0)
-    return;
-
-  n_words += additional;
-  if (n_words > 3)
-    n_words = 3;
-
-  num_refs[n_words-1] += num;
-}
-
-
-/* Return RTL for the offset from the current function to the argument.
-
-   ??? Which argument is this?  */
-
-rtx
-embedded_pic_offset (x)
-     rtx x;
-{
-  if (embedded_pic_fnaddr_rtx == NULL)
-    {
-      rtx seq;
-
-      embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
-      
-      /* Output code at function start to initialize the pseudo-reg.  */
-      /* ??? We used to do this in FINALIZE_PIC, but that does not work for
-	 inline functions, because it is called after RTL for the function
-	 has been copied.  The pseudo-reg in embedded_pic_fnaddr_rtx however
-	 does not get copied, and ends up not matching the rest of the RTL.
-	 This solution works, but means that we get unnecessary code to
-	 initialize this value every time a function is inlined into another
-	 function.  */
-      start_sequence ();
-      emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
-				 XEXP (DECL_RTL (current_function_decl), 0)));
-      seq = gen_sequence ();
-      end_sequence ();
-      push_topmost_sequence ();
-      emit_insn_after (seq, get_insns ());
-      pop_topmost_sequence ();
-    }
-
-  return gen_rtx (CONST, Pmode,
-		  gen_rtx (MINUS, Pmode, x,
-			   XEXP (DECL_RTL (current_function_decl), 0)));
-}
-
-/* Return the appropriate instructions to move one operand to another.  */
-
-char *
-mips_move_1word (operands, insn, unsignedp)
-     rtx operands[];
-     rtx insn;
-     int unsignedp;
-{
-  char *ret = 0;
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-  enum rtx_code code0 = GET_CODE (op0);
-  enum rtx_code code1 = GET_CODE (op1);
-  enum machine_mode mode = GET_MODE (op0);
-  int subreg_word0 = 0;
-  int subreg_word1 = 0;
-  enum delay_type delay = DELAY_NONE;
-
-  while (code0 == SUBREG)
-    {
-      subreg_word0 += SUBREG_WORD (op0);
-      op0 = SUBREG_REG (op0);
-      code0 = GET_CODE (op0);
-    }
-
-  while (code1 == SUBREG)
-    {
-      subreg_word1 += SUBREG_WORD (op1);
-      op1 = SUBREG_REG (op1);
-      code1 = GET_CODE (op1);
-    }
-
-  /* For our purposes, a condition code mode is the same as SImode.  */
-  if (mode == CCmode)
-    mode = SImode;
-
-  if (code0 == REG)
-    {
-      int regno0 = REGNO (op0) + subreg_word0;
-
-      if (code1 == REG)
-	{
-	  int regno1 = REGNO (op1) + subreg_word1;
-
-	  /* Just in case, don't do anything for assigning a register
-	     to itself, unless we are filling a delay slot.  */
-	  if (regno0 == regno1 && set_nomacro == 0)
-	    ret = "";
-
-	  else if (GP_REG_P (regno0))
-	    {
-	      if (GP_REG_P (regno1))
-		ret = "move\t%0,%1";
-
-	      else if (MD_REG_P (regno1))
-		{
-		  delay = DELAY_HILO;
-		  if (regno1 != HILO_REGNUM)
-		    ret = "mf%1\t%0";
-		  else
-		    ret = "mflo\t%0";
-		}
-
-
-	      else if (ST_REG_P (regno1) && mips_isa >= 4)
-		ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
-
-	      else
-		{
-		  delay = DELAY_LOAD;
-		  if (FP_REG_P (regno1))
-		    ret = "mfc1\t%0,%1";
-
-		  else if (regno1 == FPSW_REGNUM && mips_isa < 4)
-		    ret = "cfc1\t%0,$31";
-		}
-	    }
-
-	  else if (FP_REG_P (regno0))
-	    {
-	      if (GP_REG_P (regno1))
-		{
-		  delay = DELAY_LOAD;
-		  ret = "mtc1\t%1,%0";
-		}
-
-	      if (FP_REG_P (regno1))
-		ret = "mov.s\t%0,%1";
-	    }
-
-	  else if (MD_REG_P (regno0))
-	    {
-	      if (GP_REG_P (regno1))
-		{
-		  delay = DELAY_HILO;
-		  if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
-		    ret = "mt%0\t%1";
-		}
-	    }
-
-
-	  else if (regno0 == FPSW_REGNUM && mips_isa < 4)
-	    {
-	      if (GP_REG_P (regno1))
-		{
-		  delay = DELAY_LOAD;
-		  ret = "ctc1\t%0,$31";
-		}
-	    }
-	}
-
-      else if (code1 == MEM)
-	{
-	  delay = DELAY_LOAD;
-
-	  if (TARGET_STATS)
-	    mips_count_memory_refs (op1, 1);
-
-	  if (GP_REG_P (regno0))
-	    {
-	      /* For loads, use the mode of the memory item, instead of the
-		 target, so zero/sign extend can use this code as well.  */
-	      switch (GET_MODE (op1))
-		{
-		default:
-		  break;
-		case SFmode:
-		  ret = "lw\t%0,%1";
-		  break;
-		case SImode:
-		case CCmode:
-		  ret = ((unsignedp && TARGET_64BIT)
-			 ? "lwu\t%0,%1"
-			 : "lw\t%0,%1");
-		  break;
-		case HImode:
-		  ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
-		  break;
-		case QImode:
-		  ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
-		  break;
-		}
-	    }
-
-	  else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
-	    ret = "l.s\t%0,%1";
-
-	  if (ret != (char *)0 && MEM_VOLATILE_P (op1))
-	    {
-	      size_t i = strlen (ret);
-	      if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
-		abort ();
-
-	      sprintf (volatile_buffer, "%%{%s%%}", ret);
-	      ret = volatile_buffer;
-	    }
-	}
-
-      else if (code1 == CONST_INT
-	       || (code1 == CONST_DOUBLE
-		   && GET_MODE (op1) == VOIDmode))
-	{
-	  if (code1 == CONST_DOUBLE)
-	    {
-	      /* This can happen when storing constants into long long
-                 bitfields.  Just store the least significant word of
-                 the value.  */
-	      operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
-	    }
-
-	  if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
-	    {
-	      if (GP_REG_P (regno0))
-		ret = "move\t%0,%z1";
-
-	      else if (FP_REG_P (regno0))
-		{
-		  delay = DELAY_LOAD;
-		  ret = "mtc1\t%z1,%0";
-		}
-
-	      else if (MD_REG_P (regno0))
-		{
-		  delay = DELAY_HILO;
-		  ret = "mt%0\t%.";
-		}
-
-	    }
-
-	  else if (GP_REG_P (regno0))
-	    {
-	      /* Don't use X format, because that will give out of
-		 range numbers for 64 bit host and 32 bit target.  */
-	      if (! TARGET_MIPS16)
-		ret = "li\t%0,%1\t\t\t# %X1";
-	      else
-		{
-		  if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
-		    ret = "li\t%0,%1";
-		  else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
-		    ret = "li\t%0,%n1\n\tneg\t%0";
-		}
-	    }
-	}
-
-      else if (code1 == CONST_DOUBLE && mode == SFmode)
-	{
-	  if (op1 == CONST0_RTX (SFmode))
-	    {
-	      if (GP_REG_P (regno0))
-		ret = "move\t%0,%.";
-
-	      else if (FP_REG_P (regno0))
-		{
-		  delay = DELAY_LOAD;
-		  ret = "mtc1\t%.,%0";
-		}
-	    }
-
-	  else
-	    {
-	      delay = DELAY_LOAD;
-	      ret = "li.s\t%0,%1";
-	    }
-	}
-
-      else if (code1 == LABEL_REF)
-	{
-	  if (TARGET_STATS)
-	    mips_count_memory_refs (op1, 1);
-
-	  ret = "la\t%0,%a1";
-	}
-
-      else if (code1 == SYMBOL_REF || code1 == CONST)
-	{
-	  if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
-	    {
-	      rtx offset = const0_rtx;
-
-	      if (GET_CODE (op1) == CONST)
-		op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
-
-	      if (GET_CODE (op1) == SYMBOL_REF)
-		{
-		  operands[2] = HALF_PIC_PTR (op1);
-
-		  if (TARGET_STATS)
-		    mips_count_memory_refs (operands[2], 1);
-
-		  if (INTVAL (offset) == 0)
-		    {
-		      delay = DELAY_LOAD;
-		      ret = (unsignedp && TARGET_64BIT
-			     ? "lwu\t%0,%2"
-			     : "lw\t%0,%2");
-		    }
-		  else
-		    {
-		      dslots_load_total++;
-		      operands[3] = offset;
-		      if (unsignedp && TARGET_64BIT)
-			ret = (SMALL_INT (offset)
-			       ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
-			       : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
-		      else
-			ret = (SMALL_INT (offset)
-			       ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
-			       : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
-		    }
-		}
-	    }
-	  else if (TARGET_MIPS16
-		   && code1 == CONST
-		   && GET_CODE (XEXP (op1, 0)) == REG
-		   && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
-	    {
-	      /* This case arises on the mips16; see
-                 mips16_gp_pseudo_reg.  */
-	      ret = "move\t%0,%+";
-	    }
-	  else if (TARGET_MIPS16
-		   && code1 == SYMBOL_REF
-		   && SYMBOL_REF_FLAG (op1)
-		   && (XSTR (op1, 0)[0] != '*'
-		       || strncmp (XSTR (op1, 0) + 1,
-				   LOCAL_LABEL_PREFIX,
-				   sizeof LOCAL_LABEL_PREFIX - 1) != 0))
-	    {
-	      /* This can occur when reloading the address of a GP
-                 relative symbol on the mips16.  */
-	      ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
-	    }
-	  else
-	    {
-	      if (TARGET_STATS)
-		mips_count_memory_refs (op1, 1);
-
-	      ret = "la\t%0,%a1";
-	    }
-	}
-
-      else if (code1 == PLUS)
-	{
-	  rtx add_op0 = XEXP (op1, 0);
-	  rtx add_op1 = XEXP (op1, 1);
-
-	  if (GET_CODE (XEXP (op1, 1)) == REG
-	      && GET_CODE (XEXP (op1, 0)) == CONST_INT)
-	    add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
-
-	  operands[2] = add_op0;
-	  operands[3] = add_op1;
-	  ret = "add%:\t%0,%2,%3";
-	}
-
-      else if (code1 == HIGH)
-	{
-	  operands[1] = XEXP (op1, 0);
-	  ret = "lui\t%0,%%hi(%1)";
-	}
-    }
-
-  else if (code0 == MEM)
-    {
-      if (TARGET_STATS)
-	mips_count_memory_refs (op0, 1);
-
-      if (code1 == REG)
-	{
-	  int regno1 = REGNO (op1) + subreg_word1;
-
-	  if (GP_REG_P (regno1))
-	    {
-	      switch (mode)
-		{
-		case SFmode: ret = "sw\t%1,%0"; break;
-		case SImode: ret = "sw\t%1,%0"; break;
-		case HImode: ret = "sh\t%1,%0"; break;
-		case QImode: ret = "sb\t%1,%0"; break;
-		default: break;
-		}
-	    }
-
-	  else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
-	    ret = "s.s\t%1,%0";
-	}
-
-      else if (code1 == CONST_INT && INTVAL (op1) == 0)
-	{
-	  switch (mode)
-	    {
-	    case SFmode: ret = "sw\t%z1,%0"; break;
-	    case SImode: ret = "sw\t%z1,%0"; break;
-	    case HImode: ret = "sh\t%z1,%0"; break;
-	    case QImode: ret = "sb\t%z1,%0"; break;
-	    default: break;
-	    }
-	}
-
-      else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
-	{
-	  switch (mode)
-	    {
-	    case SFmode: ret = "sw\t%.,%0"; break;
-	    case SImode: ret = "sw\t%.,%0"; break;
-	    case HImode: ret = "sh\t%.,%0"; break;
-	    case QImode: ret = "sb\t%.,%0"; break;
-	    default: break;
-	    }
-	}
-
-      if (ret != 0 && MEM_VOLATILE_P (op0))
-	{
-	  size_t i = strlen (ret);
-
-	  if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
-	    abort ();
-	  
-	  sprintf (volatile_buffer, "%%{%s%%}", ret);
-	  ret = volatile_buffer;
-	}
-    }
-
-  if (ret == 0)
-    {
-      abort_with_insn (insn, "Bad move");
-      return 0;
-    }
-
-  if (delay != DELAY_NONE)
-    return mips_fill_delay_slot (ret, delay, operands, insn);
-
-  return ret;
-}
-
-
-/* Return the appropriate instructions to move 2 words */
-
-char *
-mips_move_2words (operands, insn)
-     rtx operands[];
-     rtx insn;
-{
-  char *ret = 0;
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-  enum rtx_code code0 = GET_CODE (operands[0]);
-  enum rtx_code code1 = GET_CODE (operands[1]);
-  int subreg_word0 = 0;
-  int subreg_word1 = 0;
-  enum delay_type delay = DELAY_NONE;
-
-  while (code0 == SUBREG)
-    {
-      subreg_word0 += SUBREG_WORD (op0);
-      op0 = SUBREG_REG (op0);
-      code0 = GET_CODE (op0);
-    }
-
-  if (code1 == SIGN_EXTEND)
-    {
-      op1 = XEXP (op1, 0);
-      code1 = GET_CODE (op1);
-    }
-
-  while (code1 == SUBREG)
-    {
-      subreg_word1 += SUBREG_WORD (op1);
-      op1 = SUBREG_REG (op1);
-      code1 = GET_CODE (op1);
-    }
-      
-  /* Sanity check.  */
-  if (GET_CODE (operands[1]) == SIGN_EXTEND
-      && code1 != REG
-      && code1 != CONST_INT
-      /* The following three can happen as the result of a questionable
-	 cast.  */
-      && code1 != LABEL_REF
-      && code1 != SYMBOL_REF
-      && code1 != CONST)
-    abort ();
-
-  if (code0 == REG)
-    {
-      int regno0 = REGNO (op0) + subreg_word0;
-
-      if (code1 == REG)
-	{
-	  int regno1 = REGNO (op1) + subreg_word1;
-
-	  /* Just in case, don't do anything for assigning a register
-	     to itself, unless we are filling a delay slot.  */
-	  if (regno0 == regno1 && set_nomacro == 0)
-	    ret = "";
-
-	  else if (FP_REG_P (regno0))
-	    {
-	      if (FP_REG_P (regno1))
-		ret = "mov.d\t%0,%1";
-
-	      else
-		{
-		  delay = DELAY_LOAD;
-		  if (TARGET_FLOAT64)
-		    {
-		      if (!TARGET_64BIT)
-			abort_with_insn (insn, "Bad move");
-
-#ifdef TARGET_FP_CALL_32
-		      if (FP_CALL_GP_REG_P (regno1))
-			ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
-		      else
-#endif
-			ret = "dmtc1\t%1,%0";
-		    }
-		  else
-		    ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
-		}
-	    }
-
-	  else if (FP_REG_P (regno1))
-	    {
-	      delay = DELAY_LOAD;
-	      if (TARGET_FLOAT64)
-		{
-		  if (!TARGET_64BIT)
-		    abort_with_insn (insn, "Bad move");
-
-#ifdef TARGET_FP_CALL_32
-		  if (FP_CALL_GP_REG_P (regno0))
-		    ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
-		  else
-#endif
-		    ret = "dmfc1\t%0,%1";
-		}
-	      else
-		ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
-	    }
-
-	  else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
-	    {
-	      delay = DELAY_HILO;
-	      if (TARGET_64BIT)
-		{
-		  if (regno0 != HILO_REGNUM)
-		    ret = "mt%0\t%1";
-		  else if (regno1 == 0)
-		    ret = "mtlo\t%.\n\tmthi\t%.";
-		}
-	      else
-		ret = "mthi\t%M1\n\tmtlo\t%L1";
-	    }
-
-
-	  else if (GP_REG_P (regno0) && MD_REG_P (regno1))
-	    {
-	      delay = DELAY_HILO;
-	      if (TARGET_64BIT)
-		{
-		  if (regno1 != HILO_REGNUM)
-		    ret = "mf%1\t%0";
-		}
-	      else
-		ret = "mfhi\t%M0\n\tmflo\t%L0";
-	    }
-
-
-	  else if (TARGET_64BIT)
-	    ret = "move\t%0,%1";
-
-	  else if (regno0 != (regno1+1))
-	    ret = "move\t%0,%1\n\tmove\t%D0,%D1";
-
-	  else
-	    ret = "move\t%D0,%D1\n\tmove\t%0,%1";
-	}
-
-      else if (code1 == CONST_DOUBLE)
-	{
-	  /* Move zero from $0 unless !TARGET_64BIT and recipient
-	     is 64-bit fp reg, in which case generate a constant.  */
-	  if (op1 != CONST0_RTX (GET_MODE (op1))
-	      || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
-	    {
-	      if (GET_MODE (op1) == DFmode)
-		{
-		  delay = DELAY_LOAD;
-
-#ifdef TARGET_FP_CALL_32
-		  if (FP_CALL_GP_REG_P (regno0))
-		    {
-		      if (TARGET_FLOAT64 && !TARGET_64BIT)
-			{
-			  split_double (op1, operands + 2, operands + 3);
-			  ret = "li\t%0,%2\n\tli\t%D0,%3";
-			}
-		      else
-			ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
-		    }
-		  else
-#endif
-		    {
-		      /* GNU as emits 64-bit code for li.d if the ISA is 3
-			 or higher. To avoid this we must use two li
-			 instructions for 32-bit targets. */
-		      if (mips_isa >= 3 && !TARGET_64BIT && !FP_REG_P (regno0))
-			{
-			  split_double (op1, operands + 2, operands + 3);
-			  ret = "li\t%0,%2\n\tli\t%D0,%3";
-			}
-		      else
-			ret = "li.d\t%0,%1";
-		    }
-		}
-
-	      else if (TARGET_64BIT)
-		{
-		  if (! TARGET_MIPS16)
-		    ret = "dli\t%0,%1";
-		}
-
-	      else
-		{
-		  split_double (op1, operands + 2, operands + 3);
-		  ret = "li\t%0,%2\n\tli\t%D0,%3";
-		}
-	    }
-
-	  else
-	    {
-	      if (GP_REG_P (regno0))
-		ret = (TARGET_64BIT
-#ifdef TARGET_FP_CALL_32
-		       && ! FP_CALL_GP_REG_P (regno0)
-#endif
-		       ? "move\t%0,%."
-		       : "move\t%0,%.\n\tmove\t%D0,%.");
-
-	      else if (FP_REG_P (regno0))
-		{
-		  delay = DELAY_LOAD;
-		  ret = (TARGET_64BIT
-			 ? "dmtc1\t%.,%0"
-			 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
-		}
-	    }
-	}
-
-      else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
-	{
-	  if (GP_REG_P (regno0))
-	    ret = (TARGET_64BIT
-		   ? "move\t%0,%."
-		   : "move\t%0,%.\n\tmove\t%D0,%.");
-
-	  else if (FP_REG_P (regno0))
-	    {
-	      delay = DELAY_LOAD;
-	      ret = (TARGET_64BIT
-		     ? "dmtc1\t%.,%0"
-		     : (TARGET_FLOAT64
-			? "li.d\t%0,%1"
-			: "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
-	    }
-	  else if (MD_REG_P (regno0))
-	    {
-	      delay = DELAY_HILO;
-	      ret =  (regno0 == HILO_REGNUM
-		      ? "mtlo\t%.\n\tmthi\t%."
-		      : "mt%0\t%.\n");
-	    }
-	}
-	
-      else if (code1 == CONST_INT && GET_MODE (op0) == DImode
-	       && GP_REG_P (regno0))
-	{
-	  if (TARGET_64BIT)
-	    {
-	      if (TARGET_MIPS16)
-		{
-		  if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
-		    ret = "li\t%0,%1";
-		  else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
-		    ret = "li\t%0,%n1\n\tneg\t%0";
-		}
-	      else if (GET_CODE (operands[1]) == SIGN_EXTEND)
-		ret = "li\t%0,%1\t\t# %X1";
-	      else if (HOST_BITS_PER_WIDE_INT < 64)
-		/* We can't use 'X' for negative numbers, because then we won't
-		   get the right value for the upper 32 bits.  */
-		ret = (INTVAL (op1) < 0
-		       ? "dli\t%0,%1\t\t\t# %X1"
-		       : "dli\t%0,%X1\t\t# %1");
-	      else
-		/* We must use 'X', because otherwise LONG_MIN will print as
-		   a number that the assembler won't accept.  */
-		ret = "dli\t%0,%X1\t\t# %1";
-	    }
-	  else if (HOST_BITS_PER_WIDE_INT < 64)
-	    {
-	      operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
-	      if (TARGET_MIPS16)
-		{
-		  if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
-		    ret = "li\t%M0,%2\n\tli\t%L0,%1";
-		  else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
-		    {
-		      operands[2] = GEN_INT (1);
-		      ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
-		    }
-		}
-	      else
-		ret = "li\t%M0,%2\n\tli\t%L0,%1";
-	    }
-	  else
-	    {
-	      /* We use multiple shifts here, to avoid warnings about out
-		 of range shifts on 32 bit hosts.  */
-	      operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
-	      operands[1]
-		= GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
-	      ret = "li\t%M0,%2\n\tli\t%L0,%1";
-	    }
-	}
-
-      else if (code1 == MEM)
-	{
-	  delay = DELAY_LOAD;
-
-	  if (TARGET_STATS)
-	    mips_count_memory_refs (op1, 2);
-
-	  if (FP_REG_P (regno0))
-	    ret = "l.d\t%0,%1";
-
-	  else if (TARGET_64BIT)
-	    {
-
-#ifdef TARGET_FP_CALL_32
-	      if (FP_CALL_GP_REG_P (regno0))
-		ret = (double_memory_operand (op1, GET_MODE (op1))
-		       ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
-		       : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
-	      else
-#endif
-		ret = "ld\t%0,%1";
-	    }
-
-	  else if (double_memory_operand (op1, GET_MODE (op1)))
-	    {
-	      operands[2] = adj_offsettable_operand (op1, 4);
-	      ret = (reg_mentioned_p (op0, op1)
-		     ? "lw\t%D0,%2\n\tlw\t%0,%1"
-		     : "lw\t%0,%1\n\tlw\t%D0,%2");
-	    }
-
-	  if (ret != 0 && MEM_VOLATILE_P (op1))
-	    {
-	      size_t i = strlen (ret);
-
-	      if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
-		abort ();
-
-	      sprintf (volatile_buffer, "%%{%s%%}", ret);
-	      ret = volatile_buffer;
-	    }
-	}
-
-      else if (code1 == LABEL_REF)
-	{
-	  if (TARGET_STATS)
-	    mips_count_memory_refs (op1, 2);
-
-	  if (GET_CODE (operands[1]) == SIGN_EXTEND)
-	    /* We deliberately remove the 'a' from '%1', so that we don't
-	       have to add SIGN_EXTEND support to print_operand_address.
-	       print_operand will just call print_operand_address in this
-	       case, so there is no problem.  */
-	    ret = "la\t%0,%1";
-	  else
-	    ret = "dla\t%0,%a1";
-	}
-      else if (code1 == SYMBOL_REF || code1 == CONST)
-	{
-	  if (TARGET_MIPS16
-	      && code1 == CONST
-	      && GET_CODE (XEXP (op1, 0)) == REG
-	      && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
-	    {
-	      /* This case arises on the mips16; see
-                 mips16_gp_pseudo_reg.  */
-	      ret = "move\t%0,%+";
-	    }
-	  else if (TARGET_MIPS16
-		   && code1 == SYMBOL_REF
-		   && SYMBOL_REF_FLAG (op1)
-		   && (XSTR (op1, 0)[0] != '*'
-		       || strncmp (XSTR (op1, 0) + 1,
-				   LOCAL_LABEL_PREFIX,
-				   sizeof LOCAL_LABEL_PREFIX - 1) != 0))
-	    {
-	      /* This can occur when reloading the address of a GP
-                 relative symbol on the mips16.  */
-	      ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
-	    }
-	  else
-	    {
-	      if (TARGET_STATS)
-		mips_count_memory_refs (op1, 2);
-
-	      if (GET_CODE (operands[1]) == SIGN_EXTEND)
-		/* We deliberately remove the 'a' from '%1', so that we don't
-		   have to add SIGN_EXTEND support to print_operand_address.
-		   print_operand will just call print_operand_address in this
-		   case, so there is no problem.  */
-		ret = "la\t%0,%1";
-	      else
-		ret = "dla\t%0,%a1";
-	    }
-	}
-    }
-
-  else if (code0 == MEM)
-    {
-      if (code1 == REG)
-	{
-	  int regno1 = REGNO (op1) + subreg_word1;
-
-	  if (FP_REG_P (regno1))
-	    ret = "s.d\t%1,%0";
-
-	  else if (TARGET_64BIT)
-	    {
-
-#ifdef TARGET_FP_CALL_32
-	      if (FP_CALL_GP_REG_P (regno1))
-		ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
-	      else
-#endif
-		ret = "sd\t%1,%0";
-	    }
-
-	  else if (double_memory_operand (op0, GET_MODE (op0)))
-	    {
-	      operands[2] = adj_offsettable_operand (op0, 4);
-	      ret = "sw\t%1,%0\n\tsw\t%D1,%2";
-	    }
-	}
-
-      else if (((code1 == CONST_INT && INTVAL (op1) == 0)
-		|| (code1 == CONST_DOUBLE
-		    && op1 == CONST0_RTX (GET_MODE (op1))))
-	       && (TARGET_64BIT
-		   || double_memory_operand (op0, GET_MODE (op0))))
-	{
-	  if (TARGET_64BIT)
-	    ret = "sd\t%.,%0";
-	  else
-	    {
-	      operands[2] = adj_offsettable_operand (op0, 4);
-	      ret = "sw\t%.,%0\n\tsw\t%.,%2";
-	    }
-	}
-
-      if (TARGET_STATS)
-	mips_count_memory_refs (op0, 2);
-
-      if (ret != 0 && MEM_VOLATILE_P (op0))
-	{
-	  size_t i = strlen (ret);
-
-	  if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
-	    abort ();
-	  
-	  sprintf (volatile_buffer, "%%{%s%%}", ret);
-	  ret = volatile_buffer;
-	}
-    }
-
-  if (ret == 0)
-    {
-      abort_with_insn (insn, "Bad move");
-      return 0;
-    }
-
-  if (delay != DELAY_NONE)
-    return mips_fill_delay_slot (ret, delay, operands, insn);
-
-  return ret;
-}
-
-/* Provide the costs of an addressing mode that contains ADDR.
-   If ADDR is not a valid address, its cost is irrelevant.  */
-
-int
-mips_address_cost (addr)
-     rtx addr;
-{
-  switch (GET_CODE (addr))
-    {
-    case LO_SUM:
-      return 1;
-
-    case LABEL_REF:
-      return 2;
-
-    case CONST:
-      {
-	rtx offset = const0_rtx;
-	addr = eliminate_constant_term (XEXP (addr, 0), &offset);
-	if (GET_CODE (addr) == LABEL_REF)
-	  return 2;
-
-	if (GET_CODE (addr) != SYMBOL_REF)
-	  return 4;
-
-	if (! SMALL_INT (offset))
-	  return 2;
-      }
-
-      /* ... fall through ... */
-
-    case SYMBOL_REF:
-      return SYMBOL_REF_FLAG (addr) ? 1 : 2;
-
-    case PLUS:
-      {
-	register rtx plus0 = XEXP (addr, 0);
-	register rtx plus1 = XEXP (addr, 1);
-
-	if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
-	  plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
-
-	if (GET_CODE (plus0) != REG)
-	  break;
-
-	switch (GET_CODE (plus1))
-	  {
-	  case CONST_INT:
-	    return SMALL_INT (plus1) ? 1 : 2;
-
-	  case CONST:
-	  case SYMBOL_REF:
-	  case LABEL_REF:
-	  case HIGH:
-	  case LO_SUM:
-	    return mips_address_cost (plus1) + 1;
-
-	  default:
-	    break;
-	  }
-      }
-
-    default:
-      break;
-    }
-
-  return 4;
-}
-
-/* Return nonzero if X is an address which needs a temporary register when 
-   reloaded while generating PIC code.  */
-
-int
-pic_address_needs_scratch (x)
-     rtx x;
-{
-  /* An address which is a symbolic plus a non SMALL_INT needs a temp reg.  */
-  if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
-      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
-      && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
-    return 1;
-
-  return 0;
-}
-
-/* Make normal rtx_code into something we can index from an array */
-
-static enum internal_test
-map_test_to_internal_test (test_code)
-     enum rtx_code test_code;
-{
-  enum internal_test test = ITEST_MAX;
-
-  switch (test_code)
-    {
-    case EQ:  test = ITEST_EQ;  break;
-    case NE:  test = ITEST_NE;  break;
-    case GT:  test = ITEST_GT;  break;
-    case GE:  test = ITEST_GE;  break;
-    case LT:  test = ITEST_LT;  break;
-    case LE:  test = ITEST_LE;  break;
-    case GTU: test = ITEST_GTU; break;
-    case GEU: test = ITEST_GEU; break;
-    case LTU: test = ITEST_LTU; break;
-    case LEU: test = ITEST_LEU; break;
-    default:			break;
-    }
-
-  return test;
-}
-
-
-/* Generate the code to compare two integer values.  The return value is:
-   (reg:SI xx)		The pseudo register the comparison is in
-   0		       	No register, generate a simple branch.
-
-   ??? This is called with result nonzero by the Scond patterns in
-   mips.md.  These patterns are called with a target in the mode of
-   the Scond instruction pattern.  Since this must be a constant, we
-   must use SImode.  This means that if RESULT is non-zero, it will
-   always be an SImode register, even if TARGET_64BIT is true.  We
-   cope with this by calling convert_move rather than emit_move_insn.
-   This will sometimes lead to an unnecessary extension of the result;
-   for example:
-
-   long long
-   foo (long long i)
-   {
-     return i < 5;
-   }
-
-   */
-
-rtx
-gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
-     enum rtx_code test_code;	/* relational test (EQ, etc) */
-     rtx result;		/* result to store comp. or 0 if branch */
-     rtx cmp0;			/* first operand to compare */
-     rtx cmp1;			/* second operand to compare */
-     int *p_invert;		/* NULL or ptr to hold whether branch needs */
-				/* to reverse its test */
-{
-  struct cmp_info
-  {
-    enum rtx_code test_code;	/* code to use in instruction (LT vs. LTU) */
-    int const_low;		/* low bound of constant we can accept */
-    int const_high;		/* high bound of constant we can accept */
-    int const_add;		/* constant to add (convert LE -> LT) */
-    int reverse_regs;		/* reverse registers in test */
-    int invert_const;		/* != 0 if invert value if cmp1 is constant */
-    int invert_reg;		/* != 0 if invert value if cmp1 is register */
-    int unsignedp;		/* != 0 for unsigned comparisons.  */
-  };
-
-  static struct cmp_info info[ (int)ITEST_MAX ] = {
-
-    { XOR,	 0,  65535,  0,	 0,  0,	 0, 0 },	/* EQ  */
-    { XOR,	 0,  65535,  0,	 0,  1,	 1, 0 },	/* NE  */
-    { LT,   -32769,  32766,  1,	 1,  1,	 0, 0 },	/* GT  */
-    { LT,   -32768,  32767,  0,	 0,  1,	 1, 0 },	/* GE  */
-    { LT,   -32768,  32767,  0,	 0,  0,	 0, 0 },	/* LT  */
-    { LT,   -32769,  32766,  1,	 1,  0,	 1, 0 },	/* LE  */
-    { LTU,  -32769,  32766,  1,	 1,  1,	 0, 1 },	/* GTU */
-    { LTU,  -32768,  32767,  0,	 0,  1,	 1, 1 },	/* GEU */
-    { LTU,  -32768,  32767,  0,	 0,  0,	 0, 1 },	/* LTU */
-    { LTU,  -32769,  32766,  1,	 1,  0,	 1, 1 },	/* LEU */
-  };
-
-  enum internal_test test;
-  enum machine_mode mode;
-  struct cmp_info *p_info;
-  int branch_p;
-  int eqne_p;
-  int invert;
-  rtx reg;
-  rtx reg2;
-
-  test = map_test_to_internal_test (test_code);
-  if (test == ITEST_MAX)
-    abort ();
-
-  p_info = &info[(int) test];
-  eqne_p = (p_info->test_code == XOR);
-
-  mode = GET_MODE (cmp0);
-  if (mode == VOIDmode)
-    mode = GET_MODE (cmp1);
-
-  /* Eliminate simple branches */
-  branch_p = (result == 0);
-  if (branch_p)
-    {
-      if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
-	{
-	  /* Comparisons against zero are simple branches */
-	  if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
-	      && (! TARGET_MIPS16 || eqne_p))
-	    return 0;
-
-	  /* Test for beq/bne.  */
-	  if (eqne_p && ! TARGET_MIPS16)
-	    return 0;
-	}
-
-      /* allocate a pseudo to calculate the value in.  */
-      result = gen_reg_rtx (mode);
-    }
-
-  /* Make sure we can handle any constants given to us.  */
-  if (GET_CODE (cmp0) == CONST_INT)
-    cmp0 = force_reg (mode, cmp0);
-
-  if (GET_CODE (cmp1) == CONST_INT)
-    {
-      HOST_WIDE_INT value = INTVAL (cmp1);
-
-      if (value < p_info->const_low
-	  || value > p_info->const_high
-	  /* ??? Why?  And why wasn't the similar code below modified too?  */
-	  || (TARGET_64BIT
-	      && HOST_BITS_PER_WIDE_INT < 64
-	      && p_info->const_add != 0
-	      && ((p_info->unsignedp
-		   ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
-		      > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
-		   : (value + p_info->const_add) > INTVAL (cmp1))
-		  != (p_info->const_add > 0))))
-	cmp1 = force_reg (mode, cmp1);
-    }
-
-  /* See if we need to invert the result.  */
-  invert = (GET_CODE (cmp1) == CONST_INT
-	    ? p_info->invert_const : p_info->invert_reg);
-
-  if (p_invert != (int *)0)
-    {
-      *p_invert = invert;
-      invert = 0;
-    }
-
-  /* Comparison to constants, may involve adding 1 to change a LT into LE.
-     Comparison between two registers, may involve switching operands.  */
-  if (GET_CODE (cmp1) == CONST_INT)
-    {
-      if (p_info->const_add != 0)
-	{
-	  HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
-
-	  /* If modification of cmp1 caused overflow,
-	     we would get the wrong answer if we follow the usual path;
-	     thus, x > 0xffffffffU would turn into x > 0U.  */
-	  if ((p_info->unsignedp
-	       ? (unsigned HOST_WIDE_INT) new >
-	       (unsigned HOST_WIDE_INT) INTVAL (cmp1)
-	       : new > INTVAL (cmp1))
-	      != (p_info->const_add > 0))
-	    {
-	      /* This test is always true, but if INVERT is true then
-		 the result of the test needs to be inverted so 0 should
-		 be returned instead.  */
-	      emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
-	      return result;
-	    }
-	  else
-	    cmp1 = GEN_INT (new);
-	}
-    }
-
-  else if (p_info->reverse_regs)
-    {
-      rtx temp = cmp0;
-      cmp0 = cmp1;
-      cmp1 = temp;
-    }
-
-  if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
-    reg = cmp0;
-  else
-    {
-      reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
-      convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
-    }
-
-  if (test == ITEST_NE)
-    {
-      if (! TARGET_MIPS16)
-	{
-	  convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
-	  invert = 0;
-	}
-      else
-	{
-	  reg2 = invert ? gen_reg_rtx (mode) : result;
-	  convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
-	  reg = reg2;
-	}
-    }
-
-  else if (test == ITEST_EQ)
-    {
-      reg2 = invert ? gen_reg_rtx (mode) : result;
-      convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
-      reg = reg2;
-    }
-
-  if (invert)
-    {
-      rtx one;
-
-      if (! TARGET_MIPS16)
-	one = const1_rtx;
-      else
-	{
-	  /* The value is in $24.  Copy it to another register, so
-             that reload doesn't think it needs to store the $24 and
-             the input to the XOR in the same location.  */
-	  reg2 = gen_reg_rtx (mode);
-	  emit_move_insn (reg2, reg);
-	  reg = reg2;
-	  one = force_reg (mode, const1_rtx);
-	}
-      convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
-    }
-
-  return result;
-}
-
-/* Emit the common code for doing conditional branches.
-   operand[0] is the label to jump to.
-   The comparison operands are saved away by cmp{si,di,sf,df}.  */
-
-void
-gen_conditional_branch (operands, test_code)
-     rtx operands[];
-     enum rtx_code test_code;
-{
-  enum cmp_type type = branch_type;
-  rtx cmp0 = branch_cmp[0];
-  rtx cmp1 = branch_cmp[1];
-  enum machine_mode mode;
-  rtx reg;
-  int invert;
-  rtx label1, label2;
-
-  switch (type)
-    {
-    case CMP_SI:
-    case CMP_DI:
-      mode = type == CMP_SI ? SImode : DImode;
-      invert = 0;
-      reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
-
-      if (reg)
-	{
-	  cmp0 = reg;
-	  cmp1 = const0_rtx;
-	  test_code = NE;
-	}
-      else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
-	/* We don't want to build a comparison against a non-zero
-	   constant.  */
-	cmp1 = force_reg (mode, cmp1);
-
-      break;
-
-    case CMP_SF:
-    case CMP_DF:
-      if (mips_isa < 4)
-	reg = gen_rtx (REG, CCmode, FPSW_REGNUM);
-      else
-	reg = gen_reg_rtx (CCmode);
-
-      /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
-         0 in the instruction built below.  The MIPS FPU handles
-         inequality testing by testing for equality and looking for a
-         false result.  */
-      emit_insn (gen_rtx (SET, VOIDmode, reg,
-			  gen_rtx (test_code == NE ? EQ : test_code,
-				   CCmode, cmp0, cmp1)));
-
-      test_code = test_code == NE ? EQ : NE;
-      mode = CCmode;
-      cmp0 = reg;
-      cmp1 = const0_rtx;
-      invert = 0;
-      break;
-
-    default:
-      abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
-    }
-
-  /* Generate the branch.  */
-
-  label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]);
-  label2 = pc_rtx;
-
-  if (invert)
-    {
-      label2 = label1;
-      label1 = pc_rtx;
-    }
-
-  emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
-			   gen_rtx (IF_THEN_ELSE, VOIDmode,
-				    gen_rtx (test_code, mode, cmp0, cmp1),
-				    label1, label2)));
-}
-
-/* Emit the common code for conditional moves.  OPERANDS is the array
-   of operands passed to the conditional move defined_expand.  */
-
-void
-gen_conditional_move (operands)
-     rtx *operands;
-{
-  rtx op0 = branch_cmp[0];
-  rtx op1 = branch_cmp[1];
-  enum machine_mode mode = GET_MODE (branch_cmp[0]);
-  enum rtx_code cmp_code = GET_CODE (operands[1]);
-  enum rtx_code move_code = NE;
-  enum machine_mode op_mode = GET_MODE (operands[0]);
-  enum machine_mode cmp_mode;
-  rtx cmp_reg;
-
-  if (GET_MODE_CLASS (mode) != MODE_FLOAT)
-    {
-      switch (cmp_code)
-	{
-	case EQ:
-	  cmp_code = XOR;
-	  move_code = EQ;
-	  break;
-	case NE:
-	  cmp_code = XOR;
-	  break;
-	case LT:
-	  break;
-	case GE:
-	  cmp_code = LT;
-	  move_code = EQ;
-	  break;
-	case GT:
-	  cmp_code = LT;
-	  op0 = force_reg (mode, branch_cmp[1]);
-	  op1 = branch_cmp[0];
-	  break;
-	case LE:
-	  cmp_code = LT;
-	  op0 = force_reg (mode, branch_cmp[1]);
-	  op1 = branch_cmp[0];
-	  move_code = EQ;
-	  break;
-	case LTU:
-	  break;
-	case GEU:
-	  cmp_code = LTU;
-	  move_code = EQ;
-	  break;
-	case GTU:
-	  cmp_code = LTU;
-	  op0 = force_reg (mode, branch_cmp[1]);
-	  op1 = branch_cmp[0];
-	  break;
-	case LEU:
-	  cmp_code = LTU;
-	  op0 = force_reg (mode, branch_cmp[1]);
-	  op1 = branch_cmp[0];
-	  move_code = EQ;
-	  break;
-	default:
-	  abort ();
-	}
-    }
-  else if (cmp_code == NE)
-    cmp_code = EQ, move_code = EQ;
-	  
-  if (mode == SImode || mode == DImode)
-    cmp_mode = mode;
-  else if (mode == SFmode || mode == DFmode)
-    cmp_mode = CCmode;
-  else
-    abort ();
-
-  cmp_reg = gen_reg_rtx (cmp_mode);
-  emit_insn (gen_rtx (SET, cmp_mode, cmp_reg,
-		      gen_rtx (cmp_code, cmp_mode, op0, op1)));
-
-  emit_insn (gen_rtx (SET, op_mode, operands[0],
-		      gen_rtx (IF_THEN_ELSE, op_mode,
-			       gen_rtx (move_code, VOIDmode,
-					cmp_reg, CONST0_RTX (SImode)),
-			       operands[2], operands[3])));
-}
-
-/* Write a loop to move a constant number of bytes.
-   Generate load/stores as follows:
-
-   do {
-     temp1 = src[0];
-     temp2 = src[1];
-     ...
-     temp<last> = src[MAX_MOVE_REGS-1];
-     dest[0] = temp1;
-     dest[1] = temp2;
-     ...
-     dest[MAX_MOVE_REGS-1] = temp<last>;
-     src += MAX_MOVE_REGS;
-     dest += MAX_MOVE_REGS;
-   } while (src != final);
-
-   This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
-   registers are needed.
-
-   Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
-   cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
-   (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses.  */
-
-#define MAX_MOVE_REGS 4
-#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
-
-static void
-block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
-     rtx dest_reg;		/* register holding destination address */
-     rtx src_reg;		/* register holding source address */
-     int bytes;			/* # bytes to move */
-     int align;			/* alignment */
-     rtx orig_dest;		/* original dest for change_address */
-     rtx orig_src;		/* original source for making a reg note */
-{
-  rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg);
-  rtx src_mem = change_address (orig_src, BLKmode, src_reg);
-  rtx align_rtx = GEN_INT (align);
-  rtx label;
-  rtx final_src;
-  rtx bytes_rtx;
-  int leftover;
-
-  if (bytes < 2 * MAX_MOVE_BYTES)
-    abort ();
-
-  leftover = bytes % MAX_MOVE_BYTES;
-  bytes -= leftover;
-
-  label = gen_label_rtx ();
-  final_src = gen_reg_rtx (Pmode);
-  bytes_rtx = GEN_INT (bytes);
-
-  if (bytes > 0x7fff)
-    {
-      if (Pmode == DImode)
-	{
-	  emit_insn (gen_movdi (final_src, bytes_rtx));
-	  emit_insn (gen_adddi3 (final_src, final_src, src_reg));
-	}
-      else
-	{
-	  emit_insn (gen_movsi (final_src, bytes_rtx));
-	  emit_insn (gen_addsi3 (final_src, final_src, src_reg));
-	}
-    }
-  else
-    {
-      if (Pmode == DImode)
-	emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
-      else
-	emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
-    }
-
-  emit_label (label);
-
-  bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
-  emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
-
-  if (Pmode == DImode)
-    {
-      emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
-      emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
-      emit_insn (gen_cmpdi (src_reg, final_src));
-    }
-  else
-    {
-      emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
-      emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
-      emit_insn (gen_cmpsi (src_reg, final_src));
-    }
-
-  emit_jump_insn (gen_bne (label));
-
-  if (leftover)
-    emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
-				      align_rtx));
-}
-
-/* Use a library function to move some bytes.  */
-
-static void
-block_move_call (dest_reg, src_reg, bytes_rtx)
-     rtx dest_reg;
-     rtx src_reg;
-     rtx bytes_rtx;
-{
-  /* We want to pass the size as Pmode, which will normally be SImode
-     but will be DImode if we are using 64 bit longs and pointers.  */
-  if (GET_MODE (bytes_rtx) != VOIDmode
-      && GET_MODE (bytes_rtx) != Pmode)
-    bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
-
-#ifdef TARGET_MEM_FUNCTIONS
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
-		     VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
-		     convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
-				      TREE_UNSIGNED (sizetype)),
-		     TYPE_MODE (sizetype));
-#else
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
-		     VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
-		     convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
-				      TREE_UNSIGNED (integer_type_node)),
-		     TYPE_MODE (integer_type_node));
-#endif
-}
-
-/* Expand string/block move operations.
-
-   operands[0] is the pointer to the destination.
-   operands[1] is the pointer to the source.
-   operands[2] is the number of bytes to move.
-   operands[3] is the alignment.  */
-
-void
-expand_block_move (operands)
-     rtx operands[];
-{
-  rtx bytes_rtx	= operands[2];
-  rtx align_rtx = operands[3];
-  int constp = GET_CODE (bytes_rtx) == CONST_INT;
-  HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
-  int align = INTVAL (align_rtx);
-  rtx orig_src	= operands[1];
-  rtx orig_dest	= operands[0];
-  rtx src_reg;
-  rtx dest_reg;
-
-  if (constp && bytes <= 0)
-    return;
-
-  if (align > UNITS_PER_WORD)
-    align = UNITS_PER_WORD;
-
-  /* Move the address into scratch registers.  */
-  dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
-  src_reg  = copy_addr_to_reg (XEXP (orig_src, 0));
-
-  if (TARGET_MEMCPY)
-    block_move_call (dest_reg, src_reg, bytes_rtx);
-
-  else if (constp && bytes <= 2 * MAX_MOVE_BYTES
-	   && align == UNITS_PER_WORD)
-    move_by_pieces (orig_dest, orig_src, bytes, align);
-	
-  else if (constp && bytes <= 2 * MAX_MOVE_BYTES)
-    emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
-						      dest_reg),
-				      change_address (orig_src, BLKmode,
-						      src_reg),
-				      bytes_rtx, align_rtx));
-
-  else if (constp && align >= UNITS_PER_WORD && optimize)
-    block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
-
-  else if (constp && optimize)
-    {
-      /* If the alignment is not word aligned, generate a test at
-	 runtime, to see whether things wound up aligned, and we
-	 can use the faster lw/sw instead ulw/usw.  */
-
-      rtx temp = gen_reg_rtx (Pmode);
-      rtx aligned_label = gen_label_rtx ();
-      rtx join_label = gen_label_rtx ();
-      int leftover = bytes % MAX_MOVE_BYTES;
-
-      bytes -= leftover;
-
-      if (Pmode == DImode)
-	{
-	  emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
-	  emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
-	  emit_insn (gen_cmpdi (temp, const0_rtx));
-	}
-      else
-	{
-	  emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
-	  emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
-	  emit_insn (gen_cmpsi (temp, const0_rtx));
-	}
-
-      emit_jump_insn (gen_beq (aligned_label));
-
-      /* Unaligned loop.  */
-      block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
-      emit_jump_insn (gen_jump (join_label));
-      emit_barrier ();
-
-      /* Aligned loop.  */
-      emit_label (aligned_label);
-      block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
-		       orig_src);
-      emit_label (join_label);
-
-      /* Bytes at the end of the loop.  */
-      if (leftover)
-	emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
-							  dest_reg),
-					  change_address (orig_src, BLKmode,
-							  src_reg),
-					  GEN_INT (leftover),
-					  GEN_INT (align)));
-    }
-
-  else
-    block_move_call (dest_reg, src_reg, bytes_rtx);
-}
-
-/* Emit load/stores for a small constant block_move. 
-
-   operands[0] is the memory address of the destination.
-   operands[1] is the memory address of the source.
-   operands[2] is the number of bytes to move.
-   operands[3] is the alignment.
-   operands[4] is a temp register.
-   operands[5] is a temp register.
-   ...
-   operands[3+num_regs] is the last temp register.
-
-   The block move type can be one of the following:
-	BLOCK_MOVE_NORMAL	Do all of the block move.
-	BLOCK_MOVE_NOT_LAST	Do all but the last store.
-	BLOCK_MOVE_LAST		Do just the last store. */
-
-char *
-output_block_move (insn, operands, num_regs, move_type)
-     rtx insn;
-     rtx operands[];
-     int num_regs;
-     enum block_move_type move_type;
-{
-  rtx dest_reg = XEXP (operands[0], 0);
-  rtx src_reg = XEXP (operands[1], 0);
-  HOST_WIDE_INT bytes = INTVAL (operands[2]);
-  int align = INTVAL (operands[3]);
-  int num = 0;
-  int offset = 0;
-  int use_lwl_lwr = 0;
-  int last_operand = num_regs + 4;
-  int safe_regs = 4;
-  int i;
-  rtx xoperands[10];
-
-  struct {
-    char *load;			/* load insn without nop */
-    char *load_nop;		/* load insn with trailing nop */
-    char *store;		/* store insn */
-    char *final;		/* if last_store used: NULL or swr */
-    char *last_store;		/* last store instruction */
-    int offset;			/* current offset */
-    enum machine_mode mode;	/* mode to use on (MEM) */
-  } load_store[4];
-
-  /* ??? Detect a bug in GCC, where it can give us a register
-     the same as one of the addressing registers and reduce
-     the number of registers available.  */
-  for (i = 4;
-       i < last_operand
-       && safe_regs < (int)(sizeof(xoperands) / sizeof(xoperands[0]));
-       i++)
-    if (! reg_mentioned_p (operands[i], operands[0])
-	&& ! reg_mentioned_p (operands[i], operands[1]))
-      xoperands[safe_regs++] = operands[i];
-
-  if (safe_regs < last_operand)
-    {
-      xoperands[0] = operands[0];
-      xoperands[1] = operands[1];
-      xoperands[2] = operands[2];
-      xoperands[3] = operands[3];
-      return output_block_move (insn, xoperands, safe_regs - 4, move_type);
-    }
-
-  /* If we are given global or static addresses, and we would be
-     emitting a few instructions, try to save time by using a
-     temporary register for the pointer.  */
-  /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
-     an ldl/ldr instruction pair.  We play it safe, and always move
-     constant addresses into registers when generating N32/N64 code, just
-     in case we might emit an unaligned load instruction.  */
-  if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
-		       || mips_abi == ABI_N32 || mips_abi == ABI_64))
-    {
-      if (CONSTANT_P (src_reg))
-	{
-	  if (TARGET_STATS)
-	    mips_count_memory_refs (operands[1], 1);
-
-	  src_reg = operands[3 + num_regs--];
-	  if (move_type != BLOCK_MOVE_LAST)
-	    {
-	      xoperands[1] = operands[1];
-	      xoperands[0] = src_reg;
-	      if (Pmode == DImode)
-		output_asm_insn ("dla\t%0,%1", xoperands);
-	      else
-		output_asm_insn ("la\t%0,%1", xoperands);
-	    }
-	}
-
-      if (CONSTANT_P (dest_reg))
-	{
-	  if (TARGET_STATS)
-	    mips_count_memory_refs (operands[0], 1);
-
-	  dest_reg = operands[3 + num_regs--];
-	  if (move_type != BLOCK_MOVE_LAST)
-	    {
-	      xoperands[1] = operands[0];
-	      xoperands[0] = dest_reg;
-	      if (Pmode == DImode)
-		output_asm_insn ("dla\t%0,%1", xoperands);
-	      else
-		output_asm_insn ("la\t%0,%1", xoperands);
-	    }
-	}
-    }
-
-  /* ??? We really shouldn't get any LO_SUM addresses here, because they
-     are not offsettable, however, offsettable_address_p says they are
-     offsettable. I think this is a bug in offsettable_address_p.
-     For expediency, we fix this by just loading the address into a register
-     if we happen to get one.  */
-
-  if (GET_CODE (src_reg) == LO_SUM)
-    {
-      src_reg = operands[3 + num_regs--];
-      if (move_type != BLOCK_MOVE_LAST)
-	{
-	  xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
-	  xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
-	  xoperands[0] = src_reg;
-	  if (Pmode == DImode)
-	    output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
-	  else
-	    output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
-	}
-    }
-
-  if (GET_CODE (dest_reg) == LO_SUM)
-    {
-      dest_reg = operands[3 + num_regs--];
-      if (move_type != BLOCK_MOVE_LAST)
-	{
-	  xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
-	  xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
-	  xoperands[0] = dest_reg;
-	  if (Pmode == DImode)
-	    output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
-	  else
-	    output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
-	}
-    }
-
-  if (num_regs > (int)(sizeof (load_store) / sizeof (load_store[0])))
-    num_regs = sizeof (load_store) / sizeof (load_store[0]);
-
-  else if (num_regs < 1)
-    abort_with_insn (insn,
-		     "Cannot do block move, not enough scratch registers");
-
-  while (bytes > 0)
-    {
-      load_store[num].offset = offset;
-
-      if (TARGET_64BIT && bytes >= 8 && align >= 8)
-	{
-	  load_store[num].load = "ld\t%0,%1";
-	  load_store[num].load_nop = "ld\t%0,%1%#";
-	  load_store[num].store = "sd\t%0,%1";
-	  load_store[num].last_store = "sd\t%0,%1";
-	  load_store[num].final = 0;
-	  load_store[num].mode = DImode;
-	  offset += 8;
-	  bytes -= 8;
-	}
-
-      /* ??? Fails because of a MIPS assembler bug?  */
-      else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
-	{
-	  if (BYTES_BIG_ENDIAN)
-	    {
-	      load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
-	      load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
-	      load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
-	      load_store[num].last_store = "sdr\t%0,%2";
-	      load_store[num].final = "sdl\t%0,%1";
-	    }
-	  else
-	    {
-	      load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
-	      load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
-	      load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
-	      load_store[num].last_store = "sdr\t%0,%1";
-	      load_store[num].final = "sdl\t%0,%2";
-	    }
-
-	  load_store[num].mode = DImode;
-	  offset += 8;
-	  bytes -= 8;
-	  use_lwl_lwr = 1;
-	}
-
-      else if (bytes >= 4 && align >= 4)
-	{
-	  load_store[num].load = "lw\t%0,%1";
-	  load_store[num].load_nop = "lw\t%0,%1%#";
-	  load_store[num].store = "sw\t%0,%1";
-	  load_store[num].last_store = "sw\t%0,%1";
-	  load_store[num].final = 0;
-	  load_store[num].mode = SImode;
-	  offset += 4;
-	  bytes -= 4;
-	}
-
-      else if (bytes >= 4 && ! TARGET_MIPS16)
-	{
-	  if (BYTES_BIG_ENDIAN)
-	    {
-	      load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
-	      load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
-	      load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
-	      load_store[num].last_store = "swr\t%0,%2";
-	      load_store[num].final = "swl\t%0,%1";
-	    }
-	  else
-	    {
-	      load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
-	      load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
-	      load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
-	      load_store[num].last_store = "swr\t%0,%1";
-	      load_store[num].final = "swl\t%0,%2";
-	    }
-
-	  load_store[num].mode = SImode;
-	  offset += 4;
-	  bytes -= 4;
-	  use_lwl_lwr = 1;
-	}
-
-      else if (bytes >= 2 && align >= 2)
-	{
-	  load_store[num].load = "lh\t%0,%1";
-	  load_store[num].load_nop = "lh\t%0,%1%#";
-	  load_store[num].store = "sh\t%0,%1";
-	  load_store[num].last_store = "sh\t%0,%1";
-	  load_store[num].final = 0;
-	  load_store[num].mode = HImode;
-	  offset += 2;
-	  bytes -= 2;
-	}
-      else
-	{
-	  load_store[num].load = "lb\t%0,%1";
-	  load_store[num].load_nop = "lb\t%0,%1%#";
-	  load_store[num].store = "sb\t%0,%1";
-	  load_store[num].last_store = "sb\t%0,%1";
-	  load_store[num].final = 0;
-	  load_store[num].mode = QImode;
-	  offset++;
-	  bytes--;
-	}
-
-      if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
-	{
-	  dslots_load_total++;
-	  dslots_load_filled++;
-
-	  if (CONSTANT_P (src_reg))
-	    mips_count_memory_refs (src_reg, 1);
-
-	  if (CONSTANT_P (dest_reg))
-	    mips_count_memory_refs (dest_reg, 1);
-	}
-
-      /* Emit load/stores now if we have run out of registers or are
-	 at the end of the move.  */
-
-      if (++num == num_regs || bytes == 0)
-	{
-	  /* If only load/store, we need a NOP after the load.  */
-	  if (num == 1)
-	    {
-	      load_store[0].load = load_store[0].load_nop;
-	      if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
-		dslots_load_filled--;
-	    }
-
-	  if (move_type != BLOCK_MOVE_LAST)
-	    {
-	      for (i = 0; i < num; i++)
-		{
-		  int offset;
-
-		  if (!operands[i + 4])
-		    abort ();
-
-		  if (GET_MODE (operands[i + 4]) != load_store[i].mode)
-		    operands[i + 4] = gen_rtx (REG, load_store[i].mode,
-					       REGNO (operands[i + 4]));
-
-		  offset = load_store[i].offset;
-		  xoperands[0] = operands[i + 4];
-		  xoperands[1] = gen_rtx (MEM, load_store[i].mode,
-					  plus_constant (src_reg, offset));
-
-		  if (use_lwl_lwr)
-		    {
-		      int extra_offset
-			= GET_MODE_SIZE (load_store[i].mode) - 1;
-
-		      xoperands[2] = gen_rtx (MEM, load_store[i].mode,
-					      plus_constant (src_reg,
-							     extra_offset
-							     + offset));
-		    }
-
-		  output_asm_insn (load_store[i].load, xoperands);
-		}
-	    }
-
-	  for (i = 0; i < num; i++)
-	    {
-	      int last_p = (i == num-1 && bytes == 0);
-	      int offset = load_store[i].offset;
-
-	      xoperands[0] = operands[i + 4];
-	      xoperands[1] = gen_rtx (MEM, load_store[i].mode,
-				      plus_constant (dest_reg, offset));
-
-
-	      if (use_lwl_lwr)
-		{
-		  int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
-		  xoperands[2] = gen_rtx (MEM, load_store[i].mode,
-					  plus_constant (dest_reg,
-							 extra_offset
-							 + offset));
-		}
-
-	      if (move_type == BLOCK_MOVE_NORMAL)
-		output_asm_insn (load_store[i].store, xoperands);
-
-	      else if (move_type == BLOCK_MOVE_NOT_LAST)
-		{
-		  if (!last_p)
-		    output_asm_insn (load_store[i].store, xoperands);
-
-		  else if (load_store[i].final != 0)
-		    output_asm_insn (load_store[i].final, xoperands);
-		}
-
-	      else if (last_p)
-		output_asm_insn (load_store[i].last_store, xoperands);
-	    }
-
-	  num = 0;		/* reset load_store */
-	  use_lwl_lwr = 0;
-	}
-    }
-
-  return "";
-}
-
-/* Argument support functions.  */
-
-/* Initialize CUMULATIVE_ARGS for a function.  */
-
-void
-init_cumulative_args (cum, fntype, libname)
-     CUMULATIVE_ARGS *cum;		/* argument info to initialize */
-     tree fntype;			/* tree ptr for function decl */
-     rtx libname ATTRIBUTE_UNUSED;	/* SYMBOL_REF of library name or 0 */
-{
-  static CUMULATIVE_ARGS zero_cum;
-  tree param, next_param;
-
-  if (TARGET_DEBUG_E_MODE)
-    {
-      fprintf (stderr,
-	       "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
-
-      if (!fntype)
-	fputc ('\n', stderr);
-
-      else
-	{
-	  tree ret_type = TREE_TYPE (fntype);
-	  fprintf (stderr, ", fntype code = %s, ret code = %s\n",
-		   tree_code_name[(int)TREE_CODE (fntype)],
-		   tree_code_name[(int)TREE_CODE (ret_type)]);
-	}
-    }
-
-  *cum = zero_cum;
-
-  /* Determine if this function has variable arguments.  This is
-     indicated by the last argument being 'void_type_mode' if there
-     are no variable arguments.  The standard MIPS calling sequence
-     passes all arguments in the general purpose registers in this case. */
-
-  for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
-       param != 0; param = next_param)
-    {
-      next_param = TREE_CHAIN (param);
-      if (next_param == 0 && TREE_VALUE (param) != void_type_node)
-	cum->gp_reg_found = 1;
-    }
-}
-
-/* Advance the argument to the next argument position.  */
-
-void
-function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;	/* current arg information */
-     enum machine_mode mode;	/* current arg mode */
-     tree type;			/* type of the argument or 0 if lib support */
-     int named;			/* whether or not the argument was named */
-{
-  if (TARGET_DEBUG_E_MODE)
-    {
-      fprintf (stderr,
-	       "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
-	       cum->gp_reg_found, cum->arg_number, cum->arg_words,
-	       GET_MODE_NAME (mode));
-      fprintf (stderr, HOST_PTR_PRINTF, type);
-      fprintf (stderr, ", %d )\n\n", named);
-    }
-
-  cum->arg_number++;
-  switch (mode)
-    {
-    case VOIDmode:
-      break;
-
-    default:
-      if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
-	  && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
-	abort ();
-
-      cum->gp_reg_found = 1;
-      cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
-			 / UNITS_PER_WORD);
-      break;
-
-    case BLKmode:
-      cum->gp_reg_found = 1;
-      cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
-			 / UNITS_PER_WORD);
-      break;
-
-    case SFmode:
-      if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
-	cum->fp_arg_words++;
-      else
-	cum->arg_words++;
-      if (! cum->gp_reg_found && cum->arg_number <= 2)
-	cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
-      break;
-
-    case DFmode:
-      if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
-	cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
-      else
-	cum->arg_words += (TARGET_64BIT ? 1 : 2);
-      if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
-	cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
-      break;
-
-    case DImode:
-      cum->gp_reg_found = 1;
-      cum->arg_words += (TARGET_64BIT ? 1 : 2);
-      break;
-
-
-    case QImode:
-    case HImode:
-    case SImode:
-      cum->gp_reg_found = 1;
-      cum->arg_words++;
-      break;
-    }
-}
-
-/* Return an RTL expression containing the register for the given mode,
-   or 0 if the argument is to be passed on the stack.  */
-
-struct rtx_def *
-function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;	/* current arg information */
-     enum machine_mode mode;	/* current arg mode */
-     tree type;			/* type of the argument or 0 if lib support */
-     int named;			/* != 0 for normal args, == 0 for ... args */
-{
-  rtx ret;
-  int regbase = -1;
-  int bias = 0;
-  int *arg_words = &cum->arg_words;
-  int struct_p = (type != 0
-		  && (TREE_CODE (type) == RECORD_TYPE
-		      || TREE_CODE (type) == UNION_TYPE
-		      || TREE_CODE (type) == QUAL_UNION_TYPE));
-
-  if (TARGET_DEBUG_E_MODE)
-    {
-      fprintf (stderr,
-	       "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
-	       cum->gp_reg_found, cum->arg_number, cum->arg_words,
-	       GET_MODE_NAME (mode));
-      fprintf (stderr, HOST_PTR_PRINTF, type);
-      fprintf (stderr, ", %d ) = ", named);
-    }
-  
-
-  cum->last_arg_fp = 0;
-  switch (mode)
-    {
-    case SFmode:
-      if (mips_abi == ABI_32 || mips_abi == ABI_O64)
-	{
-	  if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
-	    regbase = GP_ARG_FIRST;
-	  else
-	    {
-	      regbase = FP_ARG_FIRST;
-
-	      /* If the first arg was a float in a floating point register,
-		 then set bias to align this float arg properly.  */
-	      if (cum->arg_words == 1)
-		bias = 1;
-	    }
-	}
-      else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
-	{
-	  if (! TARGET_64BIT)
-	    cum->fp_arg_words += cum->fp_arg_words & 1;
-	  cum->last_arg_fp = 1;
-	  arg_words = &cum->fp_arg_words;
-	  regbase = FP_ARG_FIRST;
-	}
-      else
-	regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
-      break;
-
-    case DFmode:
-      if (! TARGET_64BIT)
-	{
-	  if (mips_abi == ABI_EABI
-	      && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
-	    cum->fp_arg_words += cum->fp_arg_words & 1;
-	  else
-	    cum->arg_words += cum->arg_words & 1;
-	}
-
-      if (mips_abi == ABI_32 || mips_abi == ABI_O64)
-	regbase = ((cum->gp_reg_found
-		    || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
-		    || cum->arg_number >= 2)
-		   ? GP_ARG_FIRST : FP_ARG_FIRST);
-      else if (mips_abi == ABI_EABI
-	       && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
-	{
-	  cum->last_arg_fp = 1;
-	  arg_words = &cum->fp_arg_words;
-	  regbase = FP_ARG_FIRST;
-	}
-      else
-	regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
-		   ? GP_ARG_FIRST : FP_ARG_FIRST);
-      break;
-
-    default:
-      if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
-	  && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
-	abort ();
-
-      /* Drops through.  */
-    case BLKmode:
-      if (type != (tree)0 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD
-	  && ! TARGET_64BIT && mips_abi != ABI_EABI)
-	cum->arg_words += (cum->arg_words & 1);
-      regbase = GP_ARG_FIRST;
-      break;
-
-    case VOIDmode:
-    case QImode:
-    case HImode:
-    case SImode:
-      regbase = GP_ARG_FIRST;
-      break;
-
-    case DImode:
-      if (! TARGET_64BIT)
-	cum->arg_words += (cum->arg_words & 1);
-      regbase = GP_ARG_FIRST;
-      break;
-
-    }
-
-  if (*arg_words >= MAX_ARGS_IN_REGISTERS)
-    {
-      if (TARGET_DEBUG_E_MODE)
-	fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
-
-      ret = 0;
-    }
-  else
-    {
-      if (regbase == -1)
-	abort ();
-
-      if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
-	  || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named)
-	ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
-      else
-	{
-	  /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
-	     structure contains a double in its entirety, then that 64 bit
-	     chunk is passed in a floating point register.  */
-	  tree field;
-
-	  /* First check to see if there is any such field.  */
-	  for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
-	    if (TREE_CODE (field) == FIELD_DECL
-		&& TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
-		&& TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
-		&& (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
-		    % BITS_PER_WORD == 0))
-	      break;
-
-	  /* If the whole struct fits a DFmode register,
-	     we don't need the PARALLEL.  */
-	  if (! field || mode == DFmode)
-	    ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
-	  else
-	    {
-	      /* Now handle the special case by returning a PARALLEL
-		 indicating where each 64 bit chunk goes.  */
-	      int chunks;
-	      int bitpos;
-	      int regno;
-	      int i;
-
-	      /* ??? If this is a packed structure, then the last hunk won't
-		 be 64 bits.  */
-
-	      chunks = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_WORD;
-	      if (chunks + *arg_words + bias > MAX_ARGS_IN_REGISTERS)
-		chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
-
-	      /* assign_parms checks the mode of ENTRY_PARM, so we must
-		 use the actual mode here.  */
-	      ret = gen_rtx (PARALLEL, mode, rtvec_alloc (chunks));
-
-	      bitpos = 0;
-	      regno = regbase + *arg_words + bias;
-	      field = TYPE_FIELDS (type);
-	      for (i = 0; i < chunks; i++)
-		{
-		  rtx reg;
-
-		  for (; field; field = TREE_CHAIN (field))
-		    if (TREE_CODE (field) == FIELD_DECL
-			&& (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
-			    >= bitpos))
-		      break;
-
-		  if (field
-		      && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos
-		      && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
-		      && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
-		    reg = gen_rtx (REG, DFmode,
-				   regno + FP_ARG_FIRST - GP_ARG_FIRST);
-		  else
-		    reg = gen_rtx (REG, word_mode, regno);
-
-		  XVECEXP (ret, 0, i) 
-		    = gen_rtx (EXPR_LIST, VOIDmode, reg,
-			       GEN_INT (bitpos / BITS_PER_UNIT));
-
-		  bitpos += 64;
-		  regno++;
-		}
-	    }
-	}
-
-      if (TARGET_DEBUG_E_MODE)
-	fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
-		 struct_p ? ", [struct]" : "");
-
-      /* The following is a hack in order to pass 1 byte structures
-	 the same way that the MIPS compiler does (namely by passing
-	 the structure in the high byte or half word of the register).
-	 This also makes varargs work.  If we have such a structure,
-	 we save the adjustment RTL, and the call define expands will
-	 emit them.  For the VOIDmode argument (argument after the
-	 last real argument), pass back a parallel vector holding each
-	 of the adjustments.  */
-
-      /* ??? function_arg can be called more than once for each argument.
-	 As a result, we compute more adjustments than we need here.
-	 See the CUMULATIVE_ARGS definition in mips.h.  */
-
-      /* ??? This scheme requires everything smaller than the word size to
-	 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
-	 that would mean every int needs to be shifted left, which is very
-	 inefficient.  Let's not carry this compatibility to the 64 bit
-	 calling convention for now.  */
-
-      if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
-	  && ! TARGET_64BIT && mips_abi != ABI_EABI)
-	{
-	  rtx amount = GEN_INT (BITS_PER_WORD
-				- int_size_in_bytes (type) * BITS_PER_UNIT);
-	  rtx reg = gen_rtx (REG, word_mode, regbase + *arg_words + bias);
-
-	  if (TARGET_64BIT)
-	    cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
-	  else
-	    cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
-	}
-    }
-
-  /* We will be called with a mode of VOIDmode after the last argument
-     has been seen.  Whatever we return will be passed to the call
-     insn.  If we need any shifts for small structures, return them in
-     a PARALLEL; in that case, stuff the mips16 fp_code in as the
-     mode.  Otherwise, if we have need a mips16 fp_code, return a REG
-     with the code stored as the mode.  */
-  if (mode == VOIDmode)
-    {
-      if (cum->num_adjusts > 0)
-	ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
-		       gen_rtvec_v (cum->num_adjusts, cum->adjust));
-      else if (TARGET_MIPS16 && cum->fp_code != 0)
-	ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
-    }
-
-  return ret;
-}
-
-int
-function_arg_partial_nregs (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;	/* current arg information */
-     enum machine_mode mode;	/* current arg mode */
-     tree type;			/* type of the argument or 0 if lib support */
-     int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
-{
-  if ((mode == BLKmode
-       || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
-       || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
-      && cum->arg_words < MAX_ARGS_IN_REGISTERS
-      && mips_abi != ABI_EABI)
-    {
-      int words;
-      if (mode == BLKmode)
-	words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
-		 / UNITS_PER_WORD);
-      else
-	words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-
-      if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS)
-	return 0;		/* structure fits in registers */
-
-      if (TARGET_DEBUG_E_MODE)
-	fprintf (stderr, "function_arg_partial_nregs = %d\n",
-		 MAX_ARGS_IN_REGISTERS - cum->arg_words);
-
-      return MAX_ARGS_IN_REGISTERS - cum->arg_words;
-    }
-
-  else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1
-	   && ! TARGET_64BIT && mips_abi != ABI_EABI)
-    {
-      if (TARGET_DEBUG_E_MODE)
-	fprintf (stderr, "function_arg_partial_nregs = 1\n");
-
-      return 1;
-    }
-
-  return 0;
-}
-
-/* Abort after printing out a specific insn.  */
-
-void
-abort_with_insn (insn, reason)
-     rtx insn;
-     char *reason;
-{
-  error (reason);
-  debug_rtx (insn);
-  abort ();
-}
-
-/* Write a message to stderr (for use in macros expanded in files that do not
-   include stdio.h).  */
-
-void
-trace (s, s1, s2)
-     char *s, *s1, *s2;
-{
-  fprintf (stderr, s, s1, s2);
-}
-
-/* Set up the threshold for data to go into the small data area, instead
-   of the normal data area, and detect any conflicts in the switches.  */
-
-void
-override_options ()
-{
-  register int i, start;
-  register int regno;
-  register enum machine_mode mode;
-
-  mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
-
-  if (mips_section_threshold <= 0)
-    target_flags &= ~MASK_GPOPT;
-  else if (optimize)
-    target_flags |= MASK_GPOPT;
-
-#ifndef MIPS_ISA_DEFAULT
-#define MIPS_ISA_DEFAULT 1
-#endif
-
-  /* If both single-float and soft-float are set, then clear the one that
-     was set by TARGET_DEFAULT, leaving the one that was set by the
-     user.  We assume here that the specs prevent both being set by the 
-     user. */
-#ifdef TARGET_DEFAULT
-  if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
-    target_flags &= ~(TARGET_DEFAULT&(MASK_SOFT_FLOAT|MASK_SINGLE_FLOAT));
-#endif
-
-  /* Get the architectural level.  */
-  if (mips_isa_string == 0)
-    mips_isa = MIPS_ISA_DEFAULT;
-
-  else if (ISDIGIT (*mips_isa_string))
-    {
-      mips_isa = atoi (mips_isa_string);
-      if (mips_isa == 16)
-	{
-	  /* -mno-mips16 overrides -mips16.  */
-	  if (mips_no_mips16_string == NULL)
-	    {
-	      target_flags |= MASK_MIPS16;
-	      if (TARGET_64BIT)
-		mips_isa = 3;
-	      else
-		mips_isa = MIPS_ISA_DEFAULT;
-	    }
-	  else
-	    {
-	      mips_isa = MIPS_ISA_DEFAULT;
-	    }
-	}
-      else if (mips_isa < 1 || mips_isa > 4)
-	{
-	  error ("-mips%d not supported", mips_isa);
-	  mips_isa = 1;
-	}
-    }
-
-  else
-    {
-      error ("bad value (%s) for -mips switch", mips_isa_string);
-      mips_isa = 1;
-    }
-
-#ifdef MIPS_ABI_DEFAULT
-  /* Get the ABI to use. */
-  if (mips_abi_string == (char *) 0)
-    mips_abi = MIPS_ABI_DEFAULT;
-  else if (! strcmp (mips_abi_string, "32"))
-    mips_abi = ABI_32;
-  else if (! strcmp (mips_abi_string, "o64"))
-    mips_abi = ABI_O64;
-  else if (! strcmp (mips_abi_string, "n32"))
-    mips_abi = ABI_N32;
-  else if (! strcmp (mips_abi_string, "64"))
-    mips_abi = ABI_64;
-  else if (! strcmp (mips_abi_string, "eabi"))
-    mips_abi = ABI_EABI;
-  else
-    error ("bad value (%s) for -mabi= switch", mips_abi_string);
-
-  /* A specified ISA defaults the ABI if it was not specified.  */
-  if (mips_abi_string == 0 && mips_isa_string 
-      && mips_abi != ABI_EABI && mips_abi != ABI_O64)
-    {
-      if (mips_isa <= 2)
-	mips_abi = ABI_32;
-      else
-	mips_abi = ABI_64;
-    }
-
-  /* A specified ABI defaults the ISA if it was not specified.  */
-  else if (mips_isa_string == 0 && mips_abi_string 
-	   && mips_abi != ABI_EABI && mips_abi != ABI_O64)
-    {
-      if (mips_abi == ABI_32)
-	mips_isa = 1;
-      else if (mips_abi == ABI_N32)
-	mips_isa = 3;
-      else
-	mips_isa = 4;
-    }
-
-  /* If both ABI and ISA were specified, check for conflicts.  */
-  else if (mips_isa_string && mips_abi_string)
-    {
-      if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64
-			     || mips_abi == ABI_O64))
-	  || (mips_isa >= 3 && mips_abi == ABI_32))
-	error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
-    }
-
-  /* Override TARGET_DEFAULT if necessary.  */
-  if (mips_abi == ABI_32)
-    target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
-
-  /* In the EABI in 64 bit mode, longs and pointers are 64 bits.  Likewise
-   for the SGI Irix6 N64 ABI.  */
-  if ((mips_abi == ABI_EABI && TARGET_64BIT)
-      || mips_abi == ABI_64)
-    target_flags |= MASK_LONG64;
-
-  /* ??? This doesn't work yet, so don't let people try to use it.  */
-  if (mips_abi == ABI_32)
-    error ("The -mabi=32 support does not work yet.");
-
-#else
-  if (mips_abi_string)
-    error ("This target does not support the -mabi switch.");
-#endif
-
-#ifdef MIPS_CPU_STRING_DEFAULT
-  /* ??? There is a minor inconsistency here.  If the user specifies an ISA
-     greater than that supported by the default processor, then the user gets
-     an error.  Normally, the compiler will just default to the base level cpu
-     for the indicated isa.  */
-  if (mips_cpu_string == 0)
-    mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
-#endif
-
-  /* Identify the processor type */
-  if (mips_cpu_string == 0
-      || !strcmp (mips_cpu_string, "default")
-      || !strcmp (mips_cpu_string, "DEFAULT"))
-    {
-      switch (mips_isa)
-	{
-	default:
-	  mips_cpu_string = "3000";
-	  mips_cpu = PROCESSOR_R3000;
-	  break;
-	case 2:
-	  mips_cpu_string = "6000";
-	  mips_cpu = PROCESSOR_R6000;
-	  break;
-	case 3:
-	  mips_cpu_string = "4000";
-	  mips_cpu = PROCESSOR_R4000;
-	  break;
-	case 4:
-	  mips_cpu_string = "8000";
-	  mips_cpu = PROCESSOR_R8000;
-	  break;
-	}
-    }
-
-  else
-    {
-      char *p = mips_cpu_string;
-      int seen_v = 0;
-
-      /* We need to cope with the various "vr" prefixes for the NEC 4300
-	 and 4100 processors.  */
-      if (*p == 'v' || *p == 'V')
-	seen_v = 1, p++;
-
-      if (*p == 'r' || *p == 'R')
-	p++;
-
-      /* Since there is no difference between a R2000 and R3000 in
-	 terms of the scheduler, we collapse them into just an R3000. */
-
-      mips_cpu = PROCESSOR_DEFAULT;
-      switch (*p)
-	{
-
-	case '2':
-	  if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
-	    mips_cpu = PROCESSOR_R3000;
-	  break;
-
-	case '3':
-	  if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
-	    mips_cpu = PROCESSOR_R3000;
-	  else if (!strcmp (p, "3900"))
-	    mips_cpu = PROCESSOR_R3900;
-	  break;
-
-	case '4':
-	  if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
-	    mips_cpu = PROCESSOR_R4000;
-          /* The vr4100 is a non-FP ISA III processor with some extra
-             instructions.  */
-	  else if (!strcmp (p, "4100"))
-	    {
-              mips_cpu = PROCESSOR_R4100;
-              target_flags |= MASK_SOFT_FLOAT ;
-	    }
-	  /* The vr4300 is a standard ISA III processor, but with a different
-	     pipeline.  */
-	  else if (!strcmp (p, "4300"))
-            mips_cpu = PROCESSOR_R4300;
-	  /* The r4400 is exactly the same as the r4000 from the compiler's
-	     viewpoint.  */
-	  else if (!strcmp (p, "4400"))
-	    mips_cpu = PROCESSOR_R4000;
-	  else if (!strcmp (p, "4600"))
-	    mips_cpu = PROCESSOR_R4600;
-	  else if (!strcmp (p, "4650"))
-	    mips_cpu = PROCESSOR_R4650;
-	  break;
-
-	case '5':
-	  if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
-	    mips_cpu = PROCESSOR_R5000;
-	  /* CYGNUS LOCAL vr5400/raeburn */
-	  else if (!strcmp (p, "5400"))
-	    mips_cpu = PROCESSOR_R5400;
-	  /* END CYGNUS LOCAL vr5400/raeburn */
-	  break;
-
-	case '6':
-	  if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
-	    mips_cpu = PROCESSOR_R6000;
-	  break;
-
-	case '8':
-	  if (!strcmp (p, "8000"))
-	    mips_cpu = PROCESSOR_R8000;
-	  break;
-
-	case 'o':
-	  if (!strcmp (p, "orion"))
-	    mips_cpu = PROCESSOR_R4600;
-	  break;
-	}
-
-      if (seen_v
-	  && mips_cpu != PROCESSOR_R4300
-	  && mips_cpu != PROCESSOR_R4100
-	  && mips_cpu != PROCESSOR_R5400 /* CYGNUS LOCAL vr5400/raeburn */
-	  && mips_cpu != PROCESSOR_R5000)
-	mips_cpu = PROCESSOR_DEFAULT;
-
-      if (mips_cpu == PROCESSOR_DEFAULT)
-	{
-	  error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
-	  mips_cpu_string = "default";
-	}
-    }
-
-  if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
-      || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
-      || ((mips_cpu == PROCESSOR_R4000
-           || mips_cpu == PROCESSOR_R4100
-           || mips_cpu == PROCESSOR_R4300
-	   || mips_cpu == PROCESSOR_R4600
-	   || mips_cpu == PROCESSOR_R4650)
-	  && mips_isa > 3))
-    error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
-
-  /* make sure sizes of ints/longs/etc. are ok */
-  if (mips_isa < 3)
-    {
-      if (TARGET_INT64)
-	fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
-
-      else if (TARGET_LONG64)
-	fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
-
-      else if (TARGET_FLOAT64)
-	fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
-
-      else if (TARGET_64BIT)
-	fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
-    }
-
-  if (mips_abi != ABI_32 && mips_abi != ABI_O64)
-    flag_pcc_struct_return = 0;
-
-  /* Tell halfpic.c that we have half-pic code if we do.  */
-  if (TARGET_HALF_PIC)
-    HALF_PIC_INIT ();
-
-  /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined.  We need
-     to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work.  */
-  /* ??? -non_shared turns off pic code generation, but this is not
-     implemented.  */
-  if (TARGET_ABICALLS)
-    {
-      mips_abicalls = MIPS_ABICALLS_YES;
-      flag_pic = 1;
-      if (mips_section_threshold > 0)
-	warning ("-G is incompatible with PIC code which is the default");
-    }
-  else
-    mips_abicalls = MIPS_ABICALLS_NO;
-
-  /* -membedded-pic is a form of PIC code suitable for embedded
-     systems.  All calls are made using PC relative addressing, and
-     all data is addressed using the $gp register.  This requires gas,
-     which does most of the work, and GNU ld, which automatically
-     expands PC relative calls which are out of range into a longer
-     instruction sequence.  All gcc really does differently is
-     generate a different sequence for a switch.  */
-  if (TARGET_EMBEDDED_PIC)
-    {
-      flag_pic = 1;
-      if (TARGET_ABICALLS)
-	warning ("-membedded-pic and -mabicalls are incompatible");
-
-      if (g_switch_set)
-	warning ("-G and -membedded-pic are incompatible");
-
-      /* Setting mips_section_threshold is not required, because gas
-	 will force everything to be GP addressable anyhow, but
-	 setting it will cause gcc to make better estimates of the
-	 number of instructions required to access a particular data
-	 item.  */
-      mips_section_threshold = 0x7fffffff;
-    }
-
-  /* This optimization requires a linker that can support a R_MIPS_LO16
-     relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
-     GNU ld has this support, but not all other MIPS linkers do, so we enable
-     this optimization only if the user requests it, or if GNU ld is the
-     standard linker for this configuration.  */
-  /* ??? This does not work when target addresses are DImode.
-     This is because we are missing DImode high/lo_sum patterns.  */
-  if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
-      && Pmode == SImode)
-    mips_split_addresses = 1;
-  else
-    mips_split_addresses = 0;
-
-  /* -mrnames says to use the MIPS software convention for register
-     names instead of the hardware names (ie, $a0 instead of $4).
-     We do this by switching the names in mips_reg_names, which the
-     reg_names points into via the REGISTER_NAMES macro.  */
-
-  if (TARGET_NAME_REGS)
-    bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names,
-	   sizeof (mips_reg_names));
-
-  /* When compiling for the mips16, we can not use floating point.  We
-     record the original hard float value in mips16_hard_float.  */
-  if (TARGET_MIPS16)
-    {
-      if (TARGET_SOFT_FLOAT)
-	mips16_hard_float = 0;
-      else
-	mips16_hard_float = 1;
-      target_flags |= MASK_SOFT_FLOAT;
-
-      /* Don't run the scheduler before reload, since it tends to
-         increase register pressure.  */
-      flag_schedule_insns = 0;
-    }
-
-  /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
-     to avoid using up another bit in target_flags.  */
-  if (mips_entry_string != NULL)
-    {
-      if (*mips_entry_string != '\0')
-	error ("Invalid option `entry%s'", mips_entry_string);
-
-      if (! TARGET_MIPS16)
-	warning ("-mentry is only meaningful with -mips-16");
-      else
-	mips_entry = 1;
-    }
-
-  /* We copy TARGET_MIPS16 into the mips16 global variable, so that
-     attributes can access it.  */
-  if (TARGET_MIPS16)
-    mips16 = 1;
-  else
-    mips16 = 0;
-
-  /* Initialize the high and low values for legitimate floating point
-     constants.  Rather than trying to get the accuracy down to the
-     last bit, just use approximate ranges.  */
-  dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
-  dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
-  sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
-  sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
-
-  mips_print_operand_punct['?'] = 1;
-  mips_print_operand_punct['#'] = 1;
-  mips_print_operand_punct['&'] = 1;
-  mips_print_operand_punct['!'] = 1;
-  mips_print_operand_punct['*'] = 1;
-  mips_print_operand_punct['@'] = 1;
-  mips_print_operand_punct['.'] = 1;
-  mips_print_operand_punct['('] = 1;
-  mips_print_operand_punct[')'] = 1;
-  mips_print_operand_punct['['] = 1;
-  mips_print_operand_punct[']'] = 1;
-  mips_print_operand_punct['<'] = 1;
-  mips_print_operand_punct['>'] = 1;
-  mips_print_operand_punct['{'] = 1;
-  mips_print_operand_punct['}'] = 1;
-  mips_print_operand_punct['^'] = 1;
-  mips_print_operand_punct['$'] = 1;
-  mips_print_operand_punct['+'] = 1;
-
-  mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
-  mips_char_to_class['e'] = M16_NA_REGS;
-  mips_char_to_class['t'] = T_REG;
-  mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
-  mips_char_to_class['h'] = HI_REG;
-  mips_char_to_class['l'] = LO_REG;
-  mips_char_to_class['a'] = HILO_REG;
-  mips_char_to_class['x'] = MD_REGS;
-  mips_char_to_class['b'] = ALL_REGS;
-  mips_char_to_class['y'] = GR_REGS;
-  mips_char_to_class['z'] = ST_REGS;
-
-  /* Set up array to map GCC register number to debug register number.
-     Ignore the special purpose register numbers.  */
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    mips_dbx_regno[i] = -1;
-
-  start = GP_DBX_FIRST - GP_REG_FIRST;
-  for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
-    mips_dbx_regno[i] = i + start;
-
-  start = FP_DBX_FIRST - FP_REG_FIRST;
-  for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
-    mips_dbx_regno[i] = i + start;
-
-  /* Set up array giving whether a given register can hold a given mode.
-     At present, restrict ints from being in FP registers, because reload
-     is a little enthusiastic about storing extra values in FP registers,
-     and this is not good for things like OS kernels.  Also, due to the
-     mandatory delay, it is as fast to load from cached memory as to move
-     from the FP register.  */
-
-  for (mode = VOIDmode;
-       mode != MAX_MACHINE_MODE;
-       mode = (enum machine_mode) ((int)mode + 1))
-    {
-      register int size		     = GET_MODE_SIZE (mode);
-      register enum mode_class class = GET_MODE_CLASS (mode);
-
-      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
-	{
-	  register int temp;
-
-	  if (mode == CCmode)
-	    {
-	      if (mips_isa < 4)
-		temp = (regno == FPSW_REGNUM);
-	      else
-		temp = (ST_REG_P (regno) || GP_REG_P (regno)
-			|| FP_REG_P (regno));
-	    }
-
-
-	  else if (GP_REG_P (regno))
-	    temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
-
-	  else if (FP_REG_P (regno))
-	    temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
-		    && (class == MODE_FLOAT
-			|| class == MODE_COMPLEX_FLOAT
-			|| (TARGET_DEBUG_H_MODE && class == MODE_INT))
-		    && (! TARGET_SINGLE_FLOAT || size <= 4));
-
-	  else if (MD_REG_P (regno))
-	    temp = (class == MODE_INT
-		    && (size <= UNITS_PER_WORD
-			|| (regno == MD_REG_FIRST
-			    && size == 2 * UNITS_PER_WORD)));
-
-
-	  else
-	    temp = 0;
-
-	  mips_hard_regno_mode_ok[(int)mode][regno] = temp;
-	}
-    }
-
-  /* Save GPR registers in word_mode sized hunks.  word_mode hasn't been
-     initialized yet, so we can't use that here.  */
-
-  for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
-    {
-      mips_reg_mode[regno] = TARGET_64BIT ? DImode : SImode;
-    }
-
-
-  /* CYGNUS LOCAL law */
-  {
-    int min_align = 2;
-    int max_align = 15;
-    int min_max_skip = 0;
-    int max_max_skip = 32767;
-
-    /* Validate -malign-loops= value, or provide default */
-    if (mips_align_loops_string)
-      {
-	if (TARGET_MIPS16)
-	  fatal ("the combination of -mips16 and -malign-loops is not supported");
-	mips_align_loops = atoi (mips_align_loops_string);
-	if (mips_align_loops < min_align || mips_align_loops > max_align)
-	  fatal ("-malign-loops=%d is not between %d and %d",
-	         mips_align_loops, min_align, max_align);
-      }
-    else
-      {
-	if (TARGET_MIPS16)
-	  mips_align_loops = 0;
-	else
-	  mips_align_loops = DEFAULT_LOOP_ALIGN;
-      }
-
-    /* Validate -malign-jumps= value, or provide default */
-    if (mips_align_jumps_string)
-      {
-	mips_align_jumps = atoi (mips_align_jumps_string);
-	if (mips_align_jumps < min_align || mips_align_jumps > max_align)
-	  fatal ("-malign-jumps=%d is not between %d and %d",
-	         mips_align_jumps, min_align, min_align);
-      }
-    else
-      mips_align_jumps = DEFAULT_JUMP_ALIGN;
-
-    /* Validate -malign-functions= value, or provide default */
-    if (mips_align_funcs_string)
-      {
-	mips_align_funcs = atoi (mips_align_funcs_string);
-	if (mips_align_funcs < min_align || mips_align_funcs > max_align)
-	  fatal ("-malign-functions=%d is not between %d and %d",
-	         mips_align_funcs, min_align, max_align);
-      }
-    else
-      mips_align_funcs = DEFAULT_FUNCTION_ALIGN;
-
-    /* Validate -mmax-skip-loops= value, or provide default */
-    if (mips_max_skip_loops_string)
-      {
-	mips_max_skip_loops = atoi (mips_max_skip_loops_string);
-	if (mips_max_skip_loops < min_max_skip
-	    || mips_max_skip_loops > max_max_skip)
-	  fatal ("-mmax-skip-loops=%d is not between %d and %d",
-		 mips_max_skip_loops, min_max_skip, max_max_skip);
-      }
-    else
-      mips_max_skip_loops = DEFAULT_LOOP_MAX_SKIP;
-
-    /* Validate -mmax-skip-jumps= value, or provide default */
-    if (mips_max_skip_jumps_string)
-      {
-	mips_max_skip_jumps = atoi (mips_max_skip_jumps_string);
-	if (mips_max_skip_jumps < min_max_skip
-	    || mips_max_skip_jumps > max_max_skip)
-	  fatal ("-mmax-skip-jumps=%d is not between %d and %d",
-		 mips_max_skip_jumps, min_max_skip, max_max_skip);
-      }
-    else
-      mips_max_skip_jumps = DEFAULT_JUMP_MAX_SKIP;
-
-    /* Validate -mmax-skip-functions= value, or provide default */
-    if (mips_max_skip_funcs_string)
-      {
-	mips_max_skip_funcs = atoi (mips_max_skip_funcs_string);
-	if (mips_max_skip_funcs < min_max_skip
-	    || mips_max_skip_funcs > max_max_skip)
-	  fatal ("-mmax-skip-functions=%d is not between 3 and %d",
-		 mips_max_skip_funcs, min_max_skip, max_max_skip);
-      }
-    else
-      mips_max_skip_funcs = DEFAULT_FUNCTION_MAX_SKIP;
-  }
-  /* END CYGNUS LOCAL */
-
-}
-/* On the mips16, we want to allocate $24 (T_REG) before other
-   registers for instructions for which it is possible.  This helps
-   avoid shuffling registers around in order to set up for an xor,
-   encouraging the compiler to use a cmp instead.  */
-
-void
-mips_order_regs_for_local_alloc ()
-{
-  register int i;
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    reg_alloc_order[i] = i;
-
-  if (TARGET_MIPS16)
-    {
-      /* It really doesn't matter where we put register 0, since it is
-         a fixed register anyhow.  */
-      reg_alloc_order[0] = 24;
-      reg_alloc_order[24] = 0;
-    }
-}
-
-
-/* The MIPS debug format wants all automatic variables and arguments
-   to be in terms of the virtual frame pointer (stack pointer before
-   any adjustment in the function), while the MIPS 3.0 linker wants
-   the frame pointer to be the stack pointer after the initial
-   adjustment.  So, we do the adjustment here.  The arg pointer (which
-   is eliminated) points to the virtual frame pointer, while the frame
-   pointer (which may be eliminated) points to the stack pointer after
-   the initial adjustments.  */
-
-HOST_WIDE_INT
-mips_debugger_offset (addr, offset)
-     rtx addr;
-     HOST_WIDE_INT offset;
-{
-  rtx offset2 = const0_rtx;
-  rtx reg = eliminate_constant_term (addr, &offset2);
-
-  if (offset == 0)
-    offset = INTVAL (offset2);
-
-  if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
-      || reg == hard_frame_pointer_rtx)
-    {
-      HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
-				  ? compute_frame_size (get_frame_size ())
-				  : current_frame_info.total_size;
-
-      /* MIPS16 frame is smaller */
-      if (frame_pointer_needed && TARGET_MIPS16)
-	frame_size -= current_function_outgoing_args_size;
-
-      offset = offset - frame_size;
-    }
-
-  /* sdbout_parms does not want this to crash for unrecognized cases.  */
-#if 0
-  else if (reg != arg_pointer_rtx)
-    abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
-#endif
-
-  return offset;
-}
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand X.  X is an RTL
-   expression.
-
-   CODE is a value that can be used to specify one of several ways
-   of printing the operand.  It is used when identical operands
-   must be printed differently depending on the context.  CODE
-   comes from the `%' specification that was used to request
-   printing of the operand.  If the specification was just `%DIGIT'
-   then CODE is 0; if the specification was `%LTR DIGIT' then CODE
-   is the ASCII code for LTR.
-
-   If X is a register, this macro should print the register's name.
-   The names can be found in an array `reg_names' whose type is
-   `char *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
-
-   When the machine description has a specification `%PUNCT' (a `%'
-   followed by a punctuation character), this macro is called with
-   a null pointer for X and the punctuation character for CODE.
-
-   The MIPS specific codes are:
-
-   'X'  X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
-   'x'  X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
-   'd'  output integer constant in decimal,
-   'z'	if the operand is 0, use $0 instead of normal operand.
-   'D'  print second register of double-word register operand.
-   'L'  print low-order register of double-word register operand.
-   'M'  print high-order register of double-word register operand.
-   'C'  print part of opcode for a branch condition.
-   'N'  print part of opcode for a branch condition, inverted.
-   'S'  X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
-   'B'  print 'z' for EQ, 'n' for NE
-   'b'  print 'n' for EQ, 'z' for NE
-   'T'  print 'f' for EQ, 't' for NE
-   't'  print 't' for EQ, 'f' for NE
-   'Z'  print register and a comma, but print nothing for $fcc0
-   '('	Turn on .set noreorder
-   ')'	Turn on .set reorder
-   '['	Turn on .set noat
-   ']'	Turn on .set at
-   '<'	Turn on .set nomacro
-   '>'	Turn on .set macro
-   '{'	Turn on .set volatile (not GAS)
-   '}'	Turn on .set novolatile (not GAS)
-   '&'	Turn on .set noreorder if filling delay slots
-   '*'	Turn on both .set noreorder and .set nomacro if filling delay slots
-   '!'	Turn on .set nomacro if filling delay slots
-   '#'	Print nop if in a .set noreorder section.
-   '?'	Print 'l' if we are to use a branch likely instead of normal branch.
-   '@'	Print the name of the assembler temporary register (at or $1).
-   '.'	Print the name of the register with a hard-wired zero (zero or $0).
-   '^'	Print the name of the pic call-through register (t9 or $25).
-   '$'	Print the name of the stack pointer register (sp or $29).
-   '+'	Print the name of the gp register (gp or $28).  */
-
-void
-print_operand (file, op, letter)
-     FILE *file;		/* file to write to */
-     rtx op;			/* operand to print */
-     int letter;		/* %<letter> or 0 */
-{
-  register enum rtx_code code;
-
-  if (PRINT_OPERAND_PUNCT_VALID_P (letter))
-    {
-      switch (letter)
-	{
-	case '?':
-	  if (mips_branch_likely)
-	    putc ('l', file);
-	  break;
-
-	case '@':
-	  fputs (reg_names [GP_REG_FIRST + 1], file);
-	  break;
-
-	case '^':
-	  fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
-	  break;
-
-	case '.':
-	  fputs (reg_names [GP_REG_FIRST + 0], file);
-	  break;
-
-	case '$':
-	  fputs (reg_names[STACK_POINTER_REGNUM], file);
-	  break;
-
-	case '+':
-	  fputs (reg_names[GP_REG_FIRST + 28], file);
-	  break;
-
-	case '&':
-	  if (final_sequence != 0 && set_noreorder++ == 0)
-	    fputs (".set\tnoreorder\n\t", file);
-	  break;
-
-	case '*':
-	  if (final_sequence != 0)
-	    {
-	      if (set_noreorder++ == 0)
-		fputs (".set\tnoreorder\n\t", file);
-
-	      if (set_nomacro++ == 0)
-		fputs (".set\tnomacro\n\t", file);
-	    }
-	  break;
-
-	case '!':
-	  if (final_sequence != 0 && set_nomacro++ == 0)
-	    fputs ("\n\t.set\tnomacro", file);
-	  break;
-
-	case '#':
-	  if (set_noreorder != 0)
-	    fputs ("\n\tnop", file);
-	  else if (TARGET_STATS)
-	    fputs ("\n\t#nop", file);
-
-	  break;
-
-	case '(':
-	  if (set_noreorder++ == 0)
-	    fputs (".set\tnoreorder\n\t", file);
-	  break;
-
-	case ')':
-	  if (set_noreorder == 0)
-	    error ("internal error: %%) found without a %%( in assembler pattern");
-
-	  else if (--set_noreorder == 0)
-	    fputs ("\n\t.set\treorder", file);
-
-	  break;
-
-	case '[':
-	  if (set_noat++ == 0)
-	    fputs (".set\tnoat\n\t", file);
-	  break;
-
-	case ']': 
-	  if (set_noat == 0)
-	    error ("internal error: %%] found without a %%[ in assembler pattern");
-	  else if (--set_noat == 0)
-	    fputs ("\n\t.set\tat", file);
-
-	  break;
-
-	case '<':
-	  if (set_nomacro++ == 0)
-	    fputs (".set\tnomacro\n\t", file);
-	  break;
-
-	case '>':
-	  if (set_nomacro == 0)
-	    error ("internal error: %%> found without a %%< in assembler pattern");
-	  else if (--set_nomacro == 0)
-	    fputs ("\n\t.set\tmacro", file);
-
-	  break;
-
-	case '{':
-	  if (set_volatile++ == 0)
-	    fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
-	  break;
-
-	case '}':
-	  if (set_volatile == 0)
-	    error ("internal error: %%} found without a %%{ in assembler pattern");
-	  else if (--set_volatile == 0)
-	    fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
-
-	  break;
-
-	default:
-	  error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
-	  break;
-	}
-
-      return;
-    }
-
-  if (! op)
-    {
-      error ("PRINT_OPERAND null pointer");
-      return;
-    }
-
-  code = GET_CODE (op);
-
-  if (code == SIGN_EXTEND)
-    op = XEXP (op, 0), code = GET_CODE (op);
-
-  if (letter == 'C')
-    switch (code)
-      {
-      case EQ:	fputs ("eq",  file); break;
-      case NE:	fputs ("ne",  file); break;
-      case GT:	fputs ("gt",  file); break;
-      case GE:	fputs ("ge",  file); break;
-      case LT:	fputs ("lt",  file); break;
-      case LE:	fputs ("le",  file); break;
-      case GTU: fputs ("gtu", file); break;
-      case GEU: fputs ("geu", file); break;
-      case LTU: fputs ("ltu", file); break;
-      case LEU: fputs ("leu", file); break;
-      default:
-	abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
-      }
-
-  else if (letter == 'N')
-    switch (code)
-      {
-      case EQ:	fputs ("ne",  file); break;
-      case NE:	fputs ("eq",  file); break;
-      case GT:	fputs ("le",  file); break;
-      case GE:	fputs ("lt",  file); break;
-      case LT:	fputs ("ge",  file); break;
-      case LE:	fputs ("gt",  file); break;
-      case GTU: fputs ("leu", file); break;
-      case GEU: fputs ("ltu", file); break;
-      case LTU: fputs ("geu", file); break;
-      case LEU: fputs ("gtu", file); break;
-      default:
-	abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
-      }
-
-  else if (letter == 'S')
-    {
-      char buffer[100];
-
-      ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
-      assemble_name (file, buffer);
-    }
-
-  else if (letter == 'Z')
-    {
-      register int regnum;
-
-      if (code != REG)
-	abort ();
-
-      regnum = REGNO (op);
-      if (! ST_REG_P (regnum))
-	abort ();
-
-      if (regnum != ST_REG_FIRST)
-	fprintf (file, "%s,", reg_names[regnum]);
-    }
-
-  else if (code == REG || code == SUBREG)
-    {
-      register int regnum;
-
-      if (code == REG)
-	regnum = REGNO (op);
-      else
-	regnum = true_regnum (op);
-
-      if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
-	  || (letter == 'L' && WORDS_BIG_ENDIAN)
-	  || letter == 'D')
-	regnum++;
-
-      fprintf (file, "%s", reg_names[regnum]);
-    }
-
-  else if (code == MEM)
-    output_address (XEXP (op, 0));
-
-  else if (code == CONST_DOUBLE
-	   && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
-    {
-      REAL_VALUE_TYPE d;
-      char s[30];
-
-      REAL_VALUE_FROM_CONST_DOUBLE (d, op);
-      REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
-      fprintf (file, s);
-    }
-
-  else if (letter == 'x' && GET_CODE (op) == CONST_INT)
-    fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
-
-  else if (letter == 'X' && GET_CODE(op) == CONST_INT)
-    fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
-
-  else if (letter == 'd' && GET_CODE(op) == CONST_INT)
-    fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
-
-  else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
-    fputs (reg_names[GP_REG_FIRST], file);
-
-  else if (letter == 'd' || letter == 'x' || letter == 'X')
-    fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT",
-	   letter);
-
-  else if (letter == 'B')
-    fputs (code == EQ ? "z" : "n", file);
-  else if (letter == 'b')
-    fputs (code == EQ ? "n" : "z", file);
-  else if (letter == 'T')
-    fputs (code == EQ ? "f" : "t", file);
-  else if (letter == 't')
-    fputs (code == EQ ? "t" : "f", file);
-
-  else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
-    {
-      /* This case arises on the mips16; see mips16_gp_pseudo_reg.  */
-      print_operand (file, XEXP (op, 0), letter);
-    }
-
-  else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
-    {
-      fputs ("%gprel(", file);
-      mips16_output_gp_offset (file, op);
-      fputs (")", file);
-    }
-
-  else
-    output_addr_const (file, op);
-}
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand that is a memory
-   reference whose address is ADDR.  ADDR is an RTL expression.
-
-   On some machines, the syntax for a symbolic address depends on
-   the section that the address refers to.  On these machines,
-   define the macro `ENCODE_SECTION_INFO' to store the information
-   into the `symbol_ref', and then check for it here.  */
-
-void
-print_operand_address (file, addr)
-     FILE *file;
-     rtx addr;
-{
-  if (!addr)
-    error ("PRINT_OPERAND_ADDRESS, null pointer");
-
-  else
-    switch (GET_CODE (addr))
-      {
-      case REG:
-	if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
-	  abort_with_insn (addr, "Arg pointer not eliminated.");
-
-	fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
-	break;
-
-      case LO_SUM:
-	{
-	  register rtx arg0 = XEXP (addr, 0);
-	  register rtx arg1 = XEXP (addr, 1);
-
-	  if (! mips_split_addresses)
-	    abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
-
-	  if (GET_CODE (arg0) != REG)
-	    abort_with_insn (addr,
-			     "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
-
-	  fprintf (file, "%%lo(");
-	  print_operand_address (file, arg1);
-	  fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
-	}
-	break;
-
-      case PLUS:
-	{
-	  register rtx reg = 0;
-	  register rtx offset = 0;
-	  register rtx arg0 = XEXP (addr, 0);
-	  register rtx arg1 = XEXP (addr, 1);
-
-	  if (GET_CODE (arg0) == REG)
-	    {
-	      reg = arg0;
-	      offset = arg1;
-	      if (GET_CODE (offset) == REG)
-		abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
-	    }
-
-	  else if (GET_CODE (arg1) == REG)
-	      reg = arg1, offset = arg0;
-	  else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
-	    {
-	      output_addr_const (file, addr);
-	      break;
-	    }
-	  else
-	    abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
-
-	  if (! CONSTANT_P (offset))
-	    abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
-
-	  if (REGNO (reg) == ARG_POINTER_REGNUM)
-	    abort_with_insn (addr, "Arg pointer not eliminated.");
-
-	  if (TARGET_MIPS16
-	      && GET_CODE (offset) == CONST
-	      && mips16_gp_offset_p (offset))
-	    {
-	      fputs ("%gprel(", file);
-	      mips16_output_gp_offset (file, offset);
-	      fputs (")", file);
-	    }
-	  else
-	    output_addr_const (file, offset);
-	  fprintf (file, "(%s)", reg_names [REGNO (reg)]);
-	}
-	break;
-
-      case LABEL_REF:
-      case SYMBOL_REF:
-      case CONST_INT:
-      case CONST:
-	output_addr_const (file, addr);
-	break;
-
-      default:
-	abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
-	break;
-    }
-}
-
-
-/* If optimizing for the global pointer, keep track of all of the externs, so
-   that at the end of the file, we can emit the appropriate .extern
-   declaration for them, before writing out the text section.  We assume all
-   names passed to us are in the permanent obstack, so they will be valid at
-   the end of the compilation.
-
-   If we have -G 0, or the extern size is unknown, or the object is in a user
-   specified section that is not .sbss/.sdata, don't bother emitting the
-   .externs.  In the case of user specified sections this behaviour is
-   required as otherwise GAS will think the object lives in .sbss/.sdata.  */
-
-int
-mips_output_external (file, decl, name)
-     FILE *file ATTRIBUTE_UNUSED;
-     tree decl;
-     char *name;
-{
-  register struct extern_list *p;
-  int len;
-  tree section_name;
-
-  if (TARGET_GP_OPT
-      && TREE_CODE (decl) != FUNCTION_DECL
-      && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
-      && ((section_name = DECL_SECTION_NAME (decl)) == NULL
-	  || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
-	  || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
-    {
-      p = (struct extern_list *) permalloc (sizeof (struct extern_list));
-      p->next = extern_head;
-      p->name = name;
-      p->size = len;
-      extern_head = p;
-    }
-
-#ifdef ASM_OUTPUT_UNDEF_FUNCTION
-  if (TREE_CODE (decl) == FUNCTION_DECL
-      /* ??? Don't include alloca, since gcc will always expand it
-	 inline.  If we don't do this, the C++ library fails to build.  */
-      && strcmp (name, "alloca")
-      /* ??? Don't include __builtin_next_arg, because then gcc will not
-	 bootstrap under Irix 5.1.  */
-      && strcmp (name, "__builtin_next_arg"))
-    {
-      p = (struct extern_list *) permalloc (sizeof (struct extern_list));
-      p->next = extern_head;
-      p->name = name;
-      p->size = -1;
-      extern_head = p;
-    }
-#endif
-
-  return 0;
-}
-
-#ifdef ASM_OUTPUT_UNDEF_FUNCTION
-int
-mips_output_external_libcall (file, name)
-     FILE *file;
-     char *name;
-{
-  register struct extern_list *p;
-
-  p = (struct extern_list *) permalloc (sizeof (struct extern_list));
-  p->next = extern_head;
-  p->name = name;
-  p->size = -1;
-  extern_head = p;
-
-  return 0;
-}
-#endif
-
-/* Compute a string to use as a temporary file name.  */
-
-/* On MSDOS, write temp files in current dir
-   because there's no place else we can expect to use.  */
-#if __MSDOS__
-#ifndef P_tmpdir
-#define P_tmpdir "./"
-#endif
-#endif
-
-static FILE *
-make_temp_file ()
-{
-  FILE *stream;
-  char *base = getenv ("TMPDIR");
-  int len;
-
-  if (base == 0)
-    {
-#ifdef P_tmpdir
-      if (access (P_tmpdir, R_OK | W_OK) == 0)
-	base = P_tmpdir;
-      else
-#endif
-	if (access ("/usr/tmp", R_OK | W_OK) == 0)
-	  base = "/usr/tmp/";
-	else
-	  base = "/tmp/";
-    }
-
-  len = strlen (base);
-  /* temp_filename is global, so we must use malloc, not alloca.  */
-  temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
-  strcpy (temp_filename, base);
-  if (len > 0 && temp_filename[len-1] != '/')
-    temp_filename[len++] = '/';
-
-  strcpy (temp_filename + len, "ctXXXXXX");
-  mktemp (temp_filename);
-
-  stream = fopen (temp_filename, "w+");
-  if (!stream)
-    pfatal_with_name (temp_filename);
-
-#ifndef __MSDOS__
-  /* In MSDOS, we cannot unlink the temporary file until we are finished using
-     it.  Otherwise, we delete it now, so that it will be gone even if the
-     compiler happens to crash.  */
-  unlink (temp_filename);
-#endif
-  return stream;
-}
-
-/* Emit a new filename to a stream.  If this is MIPS ECOFF, watch out
-   for .file's that start within a function.  If we are smuggling stabs, try to
-   put out a MIPS ECOFF file and a stab.  */
-
-void
-mips_output_filename (stream, name)
-     FILE *stream;
-     char *name;
-{
-  static int first_time = 1;
-  char ltext_label_name[100];
-
-  if (first_time)
-    {
-      first_time = 0;
-      SET_FILE_NUMBER ();
-      current_function_file = name;
-      ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
-      /* This tells mips-tfile that stabs will follow.  */
-      if (!TARGET_GAS && write_symbols == DBX_DEBUG)
-	fprintf (stream, "\t#@stabs\n");
-    }
-
-  else if (write_symbols == DBX_DEBUG)
-    {
-      ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
-      fprintf (stream, "%s ", ASM_STABS_OP);
-      output_quoted_string (stream, name);
-      fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
-    }
-
-  else if (name != current_function_file
-      && strcmp (name, current_function_file) != 0)
-    {
-      if (inside_function && !TARGET_GAS)
-	{
-	  if (!file_in_function_warning)
-	    {
-	      file_in_function_warning = 1;
-	      ignore_line_number = 1;
-	      warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
-	    }
-	}
-      else
-	{
-	  SET_FILE_NUMBER ();
-	  current_function_file = name;
-	  ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
-	}
-    }
-}
-
-/* Emit a linenumber.  For encapsulated stabs, we need to put out a stab
-   as well as a .loc, since it is possible that MIPS ECOFF might not be
-   able to represent the location for inlines that come from a different
-   file.  */
-
-void
-mips_output_lineno (stream, line)
-     FILE *stream;
-     int line;
-{
-  if (write_symbols == DBX_DEBUG)
-    {
-      ++sym_lineno;
-      fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
-	       LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
-	       LOCAL_LABEL_PREFIX, sym_lineno);
-    }
-
-  else
-    {
-      fprintf (stream, "\n\t%s.loc\t%d %d\n",
-	       (ignore_line_number) ? "#" : "",
-	       num_source_filenames, line);
-  
-      LABEL_AFTER_LOC (stream);
-    }
-}
-
-/* If defined, a C statement to be executed just prior to the output of
-   assembler code for INSN, to modify the extracted operands so they will be
-   output differently.
-
-   Here the argument OPVEC is the vector containing the operands extracted
-   from INSN, and NOPERANDS is the number of elements of the vector which
-   contain meaningful data for this insn.  The contents of this vector are
-   what will be used to convert the insn template into assembler code, so you
-   can change the assembler output by changing the contents of the vector.
-
-   We use it to check if the current insn needs a nop in front of it because
-   of load delays, and also to update the delay slot statistics.  */
-
-/* ??? There is no real need for this function, because it never actually
-   emits a NOP anymore.  */
-
-void
-final_prescan_insn (insn, opvec, noperands)
-     rtx insn;
-     rtx opvec[] ATTRIBUTE_UNUSED;
-     int noperands ATTRIBUTE_UNUSED;
-{
-  if (dslots_number_nops > 0)
-    {
-      rtx pattern = PATTERN (insn);
-      int length = get_attr_length (insn);
-
-      /* Do we need to emit a NOP? */
-      if (length == 0
-	  || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg,  pattern))
-	  || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
-	  || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
-	  || (mips_load_reg4 != 0
-	      && reg_mentioned_p (mips_load_reg4, pattern)))
-	fputs ("\t#nop\n", asm_out_file);
-
-      else
-	dslots_load_filled++;
-
-      while (--dslots_number_nops > 0)
-	fputs ("\t#nop\n", asm_out_file);
-
-      mips_load_reg = 0;
-      mips_load_reg2 = 0;
-      mips_load_reg3 = 0;
-      mips_load_reg4 = 0;
-    }
-
-  if (TARGET_STATS
-      && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
-    dslots_jump_total++;
-}
-
-/* Output at beginning of assembler file.
-
-   If we are optimizing to use the global pointer, create a temporary file to
-   hold all of the text stuff, and write it out to the end. This is needed
-   because the MIPS assembler is evidently one pass, and if it hasn't seen the
-   relevant .comm/.lcomm/.extern/.sdata declaration when the code is
-   processed, it generates a two instruction sequence.  */
-
-void
-mips_asm_file_start (stream)
-     FILE *stream;
-{
-  ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
-
-  /* Versions of the MIPS assembler before 2.20 generate errors if a branch
-     inside of a .set noreorder section jumps to a label outside of the .set
-     noreorder section.  Revision 2.20 just set nobopt silently rather than
-     fixing the bug.  */
-
-  if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
-    fprintf (stream, "\t.set\tnobopt\n");
-
-  /* Generate the pseudo ops that System V.4 wants.  */
-#ifndef ABICALLS_ASM_OP
-#define ABICALLS_ASM_OP ".abicalls"
-#endif
-  if (TARGET_ABICALLS)
-    /* ??? but do not want this (or want pic0) if -non-shared? */
-    fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
-
-  if (TARGET_MIPS16)
-    fprintf (stream, "\t.set\tmips16\n");
-
-  /* Start a section, so that the first .popsection directive is guaranteed
-     to have a previously defined section to pop back to.  */
-  if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
-    fprintf (stream, "\t.section\t.text\n");
-
-  /* This code exists so that we can put all externs before all symbol
-     references.  This is necessary for the MIPS assembler's global pointer
-     optimizations to work.  */
-  if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
-    {
-      asm_out_data_file = stream;
-      asm_out_text_file = make_temp_file ();
-    }
-
-  else
-    asm_out_data_file = asm_out_text_file = stream;
-
-  if (flag_verbose_asm)
-    fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
-	     ASM_COMMENT_START,
-	     mips_section_threshold, mips_cpu_string, mips_isa);
-}
-
-/* If we are optimizing the global pointer, emit the text section now and any
-   small externs which did not have .comm, etc that are needed.  Also, give a
-   warning if the data area is more than 32K and -pic because 3 instructions
-   are needed to reference the data pointers.  */
-
-void
-mips_asm_file_end (file)
-     FILE *file;
-{
-  char buffer[8192];
-  tree name_tree;
-  struct extern_list *p;
-  int len;
-
-  if (HALF_PIC_P ())
-    {
-      HALF_PIC_FINISH (file);
-    }
-
-  if (extern_head)
-    {
-      fputs ("\n", file);
-
-      for (p = extern_head; p != 0; p = p->next)
-	{
-	  name_tree = get_identifier (p->name);
-
-	  /* Positively ensure only one .extern for any given symbol.  */
-	  if (! TREE_ASM_WRITTEN (name_tree))
-	    {
-	      TREE_ASM_WRITTEN (name_tree) = 1;
-#ifdef ASM_OUTPUT_UNDEF_FUNCTION
-	      if (p->size == -1)
-		ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
-	      else
-#endif
-		{
-		  fputs ("\t.extern\t", file);
-		  assemble_name (file, p->name);
-		  fprintf (file, ", %d\n", p->size);
-		}
-	    }
-	}
-    }
-      
-  if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
-    {
-      fprintf (file, "\n\t.text\n");
-      rewind (asm_out_text_file);
-      if (ferror (asm_out_text_file))
-	fatal_io_error (temp_filename);
-
-      while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
-	if ((int) fwrite (buffer, 1, len, file) != len)
-	  pfatal_with_name (asm_file_name);
-
-      if (len < 0)
-	pfatal_with_name (temp_filename);
-
-      if (fclose (asm_out_text_file) != 0)
-	pfatal_with_name (temp_filename);
-
-#ifdef __MSDOS__
-      unlink (temp_filename);
-#endif
-    }
-}
-
-/* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
-   is used, so that we don't emit an .extern for it in mips_asm_file_end.  */
-
-void
-mips_declare_object (stream, name, init_string, final_string, size)
-     FILE *stream;
-     char *name;
-     char *init_string;
-     char *final_string;
-     int size;
-{
-  fputs (init_string, stream);		/* "", "\t.comm\t", or "\t.lcomm\t" */
-  assemble_name (stream, name);
-  fprintf (stream, final_string, size);	/* ":\n", ",%u\n", ",%u\n" */
-
-  if (TARGET_GP_OPT)
-    {
-      tree name_tree = get_identifier (name);
-      TREE_ASM_WRITTEN (name_tree) = 1;
-    }
-}
-
-/* Output a double precision value to the assembler.  If both the
-   host and target are IEEE, emit the values in hex.  */
-
-void
-mips_output_double (stream, value)
-     FILE *stream;
-     REAL_VALUE_TYPE value;
-{
-#ifdef REAL_VALUE_TO_TARGET_DOUBLE
-  long value_long[2];
-  REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
-
-  fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
-	   value_long[0], value, value_long[1]);
-#else
-  fprintf (stream, "\t.double\t%.20g\n", value);
-#endif
-}
-
-/* Output a single precision value to the assembler.  If both the
-   host and target are IEEE, emit the values in hex.  */
-
-void
-mips_output_float (stream, value)
-     FILE *stream;
-     REAL_VALUE_TYPE value;
-{
-#ifdef REAL_VALUE_TO_TARGET_SINGLE
-  long value_long;
-  REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
-
-  fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
-#else
-  fprintf (stream, "\t.float\t%.12g\n", value);
-#endif
-}
-
-/* Return the bytes needed to compute the frame pointer from the current
-   stack pointer.
-
-   Mips stack frames look like:
-
-             Before call		        After call
-        +-----------------------+	+-----------------------+
-   high |			|       |      			|
-   mem. |		        |	|			|
-        |  caller's temps.    	|       |  caller's temps.    	|
-	|       		|       |       	        |
-        +-----------------------+	+-----------------------+
- 	|       		|	|		        |
-        |  arguments on stack.  |	|  arguments on stack.  |
-	|       		|	|			|
-        +-----------------------+	+-----------------------+
- 	|  4 words to save     	|	|  4 words to save	|
-	|  arguments passed	|	|  arguments passed	|
-	|  in registers, even	|	|  in registers, even	|
-    SP->|  if not passed.       |  VFP->|  if not passed.	|
-	+-----------------------+       +-----------------------+
-					|		        |
-                                        |  fp register save     |
-					|			|
-					+-----------------------+
-					|		        |
-                                        |  gp register save     |
-                                        |       		|
-					+-----------------------+
-					|			|
-					|  local variables	|
-					|			|
-					+-----------------------+
-					|			|
-                                        |  alloca allocations   |
-        				|			|
-					+-----------------------+
-					|			|
-					|  GP save for V.4 abi	|
-					|			|
-					+-----------------------+
-					|			|
-                                        |  arguments on stack   |
-        				|		        |
-					+-----------------------+
-                                        |  4 words to save      |
-					|  arguments passed     |
-                                        |  in registers, even   |
-   low                              SP->|  if not passed.       |
-   memory        			+-----------------------+
-
-*/
-
-HOST_WIDE_INT
-compute_frame_size (size)
-     HOST_WIDE_INT size;	/* # of var. bytes allocated */
-{
-  int regno;
-  HOST_WIDE_INT total_size;	/* # bytes that the entire frame takes up */
-  HOST_WIDE_INT var_size;	/* # bytes that variables take up */
-  HOST_WIDE_INT args_size;	/* # bytes that outgoing arguments take up */
-  HOST_WIDE_INT extra_size;	/* # extra bytes */
-  HOST_WIDE_INT gp_reg_rounded;	/* # bytes needed to store gp after rounding */
-  HOST_WIDE_INT gp_reg_size;	/* # bytes needed to store gp regs */
-  HOST_WIDE_INT fp_reg_size;	/* # bytes needed to store fp regs */
-  long mask;			/* mask of saved gp registers */
-  long fmask;			/* mask of saved fp registers */
-  int  fp_inc;			/* 1 or 2 depending on the size of fp regs */
-  long fp_bits;			/* bitmask to use for each fp register */
-
-  gp_reg_size = 0;
-  fp_reg_size = 0;
-  mask = 0;
-  fmask	= 0;
-  extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
-  var_size = MIPS_STACK_ALIGN (size);
-  args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
-
-  /* The MIPS 3.0 linker does not like functions that dynamically
-     allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
-     looks like we are trying to create a second frame pointer to the
-     function, so allocate some stack space to make it happy.  */
-
-  if (args_size == 0 && current_function_calls_alloca)
-    args_size = 4 * UNITS_PER_WORD;
-
-  total_size = var_size + args_size + extra_size;
-
-  /* Calculate space needed for gp registers.  */
-  for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
-    {
-      /* $18 is a special case on the mips16.  It may be used to call
-         a function which returns a floating point value, but it is
-         marked in call_used_regs.  $31 is also a special case.  When
-         not using -mentry, it will be used to copy a return value
-         into the floating point registers if the return value is
-         floating point.  */
-      if (MUST_SAVE_REGISTER (regno)
-	  || (TARGET_MIPS16
-	      && regno == GP_REG_FIRST + 18
-	      && regs_ever_live[regno])
-	  || (TARGET_MIPS16
-	      && regno == GP_REG_FIRST + 31
-	      && mips16_hard_float
-	      && ! mips_entry
-	      && ! aggregate_value_p (DECL_RESULT (current_function_decl))
-	      && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
-		  == MODE_FLOAT)
-	      && (! TARGET_SINGLE_FLOAT
-		  || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
-		      <= 4))))
-	{
-	  gp_reg_size += GET_MODE_SIZE (mips_reg_mode[0]);
-	  mask |= 1L << (regno - GP_REG_FIRST);
-
-	  /* The entry and exit pseudo instructions can not save $17
-	     without also saving $16.  */
-	  if (mips_entry
-	      && regno == GP_REG_FIRST + 17
-	      && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
-	    {
-	      gp_reg_size += UNITS_PER_WORD;
-	      mask |= 1L << 16;
-	    }
-	}
-    }
-
-  /* Calculate space needed for fp registers.  */
-  if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
-    {
-      fp_inc = 1;
-      fp_bits = 1;
-    }
-  else
-    {
-      fp_inc = 2;
-      fp_bits = 3;
-    }
-
-  /* This loop must iterate over the same space as its companion in
-     save_restore_regs.  */
-  for (regno = (FP_REG_LAST - fp_inc + 1);
-       regno >= FP_REG_FIRST;
-       regno -= fp_inc)
-    {
-      if (regs_ever_live[regno] && !call_used_regs[regno])
-	{
-	  fp_reg_size += fp_inc * UNITS_PER_FPREG;
-	  fmask |= fp_bits << (regno - FP_REG_FIRST);
-	}
-    }
-
-  gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
-  total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
-
-  /* The gp reg is caller saved in the 32 bit ABI, so there is no need
-     for leaf routines (total_size == extra_size) to save the gp reg.
-     The gp reg is callee saved in the 64 bit ABI, so all routines must
-     save the gp reg.  This is not a leaf routine if -p, because of the
-     call to mcount.  */
-  if (total_size == extra_size 
-      && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
-      && ! profile_flag)
-    total_size = extra_size = 0;
-  else if (TARGET_ABICALLS)
-    {
-      /* Add the context-pointer to the saved registers.  */
-      gp_reg_size += UNITS_PER_WORD;
-      mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
-      total_size -= gp_reg_rounded;
-      gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
-      total_size += gp_reg_rounded;
-    }
-
-  /* Add in space reserved on the stack by the callee for storing arguments
-     passed in registers.  */
-  if (mips_abi != ABI_32 && mips_abi != ABI_O64)
-    total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
-
-  /* The entry pseudo instruction will allocate 32 bytes on the stack.  */
-  if (mips_entry && total_size > 0 && total_size < 32)
-    total_size = 32;
-
-  /* Save other computed information.  */
-  current_frame_info.total_size = total_size;
-  current_frame_info.var_size = var_size;
-  current_frame_info.args_size = args_size;
-  current_frame_info.extra_size = extra_size;
-  current_frame_info.gp_reg_size = gp_reg_size;
-  current_frame_info.fp_reg_size = fp_reg_size;
-  current_frame_info.mask = mask;
-  current_frame_info.fmask = fmask;
-  current_frame_info.initialized = reload_completed;
-  current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
-  current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
-
-  if (mask)
-    {
-      unsigned long offset;
-
-      /* When using mips_entry, the registers are always saved at the
-         top of the stack.  */
-      if (! mips_entry)
-	offset = (args_size + extra_size + var_size
-		  + gp_reg_size - GET_MODE_SIZE (mips_reg_mode[0]));
-      else
-	offset = total_size - GET_MODE_SIZE (mips_reg_mode[0]);
-
-      current_frame_info.gp_sp_offset = offset;
-      current_frame_info.gp_save_offset = offset - total_size;
-    }
-  else
-    {
-      current_frame_info.gp_sp_offset = 0;
-      current_frame_info.gp_save_offset = 0;
-    }
-
-  if (fmask)
-    {
-      unsigned long offset = (args_size + extra_size + var_size
-			      + gp_reg_rounded + fp_reg_size
-			      - fp_inc * UNITS_PER_FPREG);
-      current_frame_info.fp_sp_offset = offset;
-      current_frame_info.fp_save_offset = offset - total_size;
-    }
-  else
-    {
-      current_frame_info.fp_sp_offset = 0;
-      current_frame_info.fp_save_offset = 0;
-    }
-
-  /* Ok, we're done.  */
-  return total_size;
-}
-
-/* Common code to emit the insns (or to write the instructions to a file)
-   to save/restore registers.
-
-   Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
-   is not modified within save_restore_insns.  */
-
-#define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
-
-/* If modifying X uses a larger mode than in mips_reg_mode,
-   indicate that fact by setting mips_reg_mode.  */
-
-static
-void
-mips_check_reg_mode (x, set)
-     rtx x;
-     rtx set;
-{
-  if (GET_CODE (x) == REG 
-      && REGNO (x) <= GP_REG_LAST
-      && (GET_MODE_SIZE (GET_MODE (x))
-	  > GET_MODE_SIZE (mips_reg_mode[REGNO (x)])))
-    {
-      mips_reg_mode[REGNO (x)] = GET_MODE (x);
-    }
-}
-
-static void
-save_restore_insns (store_p, large_reg, large_offset, file)
-     int store_p;	/* true if this is prologue */
-     rtx large_reg;	/* register holding large offset constant or NULL */
-     long large_offset;	/* large constant offset value */
-     FILE *file;	/* file to write instructions instead of making RTL */
-{
-  long mask = current_frame_info.mask;
-  long fmask = current_frame_info.fmask;
-  int regno;
-  rtx base_reg_rtx;
-  HOST_WIDE_INT base_offset;
-  HOST_WIDE_INT gp_offset;
-  HOST_WIDE_INT fp_offset;
-  HOST_WIDE_INT end_offset;
-  rtx insn;
-
-
-  if (frame_pointer_needed
-      && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
-    abort ();
-
-  if (mask == 0 && fmask == 0)
-    return;
-
-  /* Save registers starting from high to low.  The debuggers prefer at least
-     the return register be stored at func+4, and also it allows us not to
-     need a nop in the epilog if at least one register is reloaded in
-     addition to return address.  */
-
-
-  /* Save GP registers if needed.  */
-  if (mask)
-    {
-      /* Pick which pointer to use as a base register.  For small frames, just
-	 use the stack pointer.  Otherwise, use a temporary register.  Save 2
-	 cycles if the save area is near the end of a large frame, by reusing
-	 the constant created in the prologue/epilogue to adjust the stack
-	 frame.  */
-
-      gp_offset = current_frame_info.gp_sp_offset;
-      end_offset
-	= gp_offset - (current_frame_info.gp_reg_size
-		       - GET_MODE_SIZE (mips_reg_mode[0]));
-
-      if (gp_offset < 0 || end_offset < 0)
-	fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
-	       (long) gp_offset, (long) end_offset);
-
-      /* If we see a large frame in mips16 mode, we save the registers
-         before adjusting the stack pointer, and load them afterward.  */
-      else if (TARGET_MIPS16 && large_offset > 32767)
-	base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
-
-      else if (gp_offset < 32768)
-	base_reg_rtx = stack_pointer_rtx, base_offset  = 0;
-
-      else if (large_reg != 0
-	       && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
-	       && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
-	{
-	  base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
-	  base_offset = large_offset;
-	  if (file == 0)
-	    {
-	      if (Pmode == DImode)
-		insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
-					      stack_pointer_rtx));
-	      else
-		insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
-					      stack_pointer_rtx));
-	      if (store_p)
-		RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	  else
-	    fprintf (file, "\t%s\t%s,%s,%s\n",
-		     Pmode == DImode ? "daddu" : "addu",
-		     reg_names[MIPS_TEMP2_REGNUM],
-		     reg_names[REGNO (large_reg)],
-		     reg_names[STACK_POINTER_REGNUM]);
-	}
-
-      else
-	{
-	  base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
-	  base_offset = gp_offset;
-	  if (file == 0)
-	    {
-	      rtx gp_offset_rtx = GEN_INT (gp_offset);
-
-	      /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
-		 bit, so make sure that we don't emit anything that can be
-		 split.  */
-	      /* ??? There is no DImode ori immediate pattern, so we can only
-		 do this for 32 bit code.  */
-	      if (large_int (gp_offset_rtx)
-		  && GET_MODE (base_reg_rtx) == SImode)
-		{
-		  insn = emit_move_insn (base_reg_rtx,
-					 GEN_INT (gp_offset & 0xffff0000));
-		  if (store_p)
-		    RTX_FRAME_RELATED_P (insn) = 1;
-		  insn
-		    = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
-					     GEN_INT (gp_offset & 0x0000ffff)));
-		  if (store_p)
-		    RTX_FRAME_RELATED_P (insn) = 1;
-		}
-	      else
-		{
-		  insn = emit_move_insn (base_reg_rtx, gp_offset_rtx);
-		  if (store_p)
-		    RTX_FRAME_RELATED_P (insn) = 1;
-		}
-
-	      if (Pmode == DImode)
-		insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
-				 	      stack_pointer_rtx));
-	      else
-		insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
-					      stack_pointer_rtx));
-	      if (store_p)
-		RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	  else
-	    {
-	      fprintf (file, "\tli\t%s,0x%.08lx\t# ",
-		       reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
-	      fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
-	      fprintf (file, "\n\t%s\t%s,%s,%s\n",
-		       Pmode == DImode ? "daddu" : "addu",
-		       reg_names[MIPS_TEMP2_REGNUM],
-		       reg_names[MIPS_TEMP2_REGNUM],
-		       reg_names[STACK_POINTER_REGNUM]);
-	    }
-	}
-
-      /* When we restore the registers in MIPS16 mode, then if we are
-         using a frame pointer, and this is not a large frame, the
-         current stack pointer will be offset by
-         current_function_outgoing_args_size.  Doing it this way lets
-         us avoid offsetting the frame pointer before copying it into
-         the stack pointer; there is no instruction to set the stack
-         pointer to the sum of a register and a constant.  */
-      if (TARGET_MIPS16
-	  && ! store_p
-	  && frame_pointer_needed
-	  && large_offset <= 32767)
-	base_offset += current_function_outgoing_args_size;
-
-      for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
-	if (BITSET_P (mask, regno - GP_REG_FIRST))
-	  {
-	    if (file == 0)
-	      {
-		rtx reg_rtx;
-		rtx mem_rtx
-		  = gen_rtx (MEM,
-			     mips_reg_mode[regno],
-			     gen_rtx (PLUS, Pmode, base_reg_rtx,
-				      GEN_INT (gp_offset - base_offset)));
-
-		RTX_UNCHANGING_P (mem_rtx) = 1;
-
-		/* The mips16 does not have an instruction to load
-                   $31, so we load $7 instead, and work things out
-                   in the caller.  */
-		if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
-		  reg_rtx = gen_rtx (REG, mips_reg_mode[7], GP_REG_FIRST + 7);
-		/* The mips16 sometimes needs to save $18.  */
-		else if (TARGET_MIPS16
-			 && regno != GP_REG_FIRST + 31
-			 && ! M16_REG_P (regno))
-		  {
-		    if (! store_p)
-		      reg_rtx = gen_rtx (REG, mips_reg_mode[6], 6);
-		    else
-		      {
-			reg_rtx = gen_rtx (REG, mips_reg_mode[3], 3);
-			emit_move_insn (reg_rtx,
-					gen_rtx (REG, mips_reg_mode[regno],
-						 regno));
-		      }
-		  }
-		else
-		      reg_rtx = gen_rtx (REG,
-					 mips_reg_mode[regno],
-					 regno);
-		if (store_p)
-		  {
-		    insn = emit_move_insn (mem_rtx, reg_rtx);
-		    RTX_FRAME_RELATED_P (insn) = 1;
-		  }
-		else if (!TARGET_ABICALLS 
-			 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
-			 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
-		  {
-		    emit_move_insn (reg_rtx, mem_rtx);
-		    if (TARGET_MIPS16
-			&& regno != GP_REG_FIRST + 31
-			&& ! M16_REG_P (regno))
-		      emit_move_insn (gen_rtx (REG, mips_reg_mode[regno],
-					       regno),
-				      reg_rtx);
-		  }
-	      }
-	    else
-	      {
-		if (store_p || !TARGET_ABICALLS 
-		    || (mips_abi != ABI_32 && mips_abi != ABI_O64)
-		    || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
-		  {
-		    int r = regno;
-
-		    /* The mips16 does not have an instruction to
-                       load $31, so we load $7 instead, and work
-                       things out in the caller.  */
-		    if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
-		      r = GP_REG_FIRST + 7;
-		      /* The mips16 sometimes needs to save $18.  */
-		    if (TARGET_MIPS16
-			&& regno != GP_REG_FIRST + 31
-			&& ! M16_REG_P (regno))
-		      {
-			if (! store_p)
-			  r = GP_REG_FIRST + 6;
-			else
-			  {
-			    r = GP_REG_FIRST + 3;
-			    fprintf (file, "\tmove\t%s,%s\n",
-				     reg_names[r], reg_names[regno]);
-			  }
-		      }
-		    fprintf (file, "\t%s\t%s,",
-			     (TARGET_64BIT
-			      ? (store_p) ? "sd" : "ld"
-			      : (store_p) ? "sw" : "lw"),
-			     reg_names[r]);
-		    fprintf (file, HOST_WIDE_INT_PRINT_DEC, 
-			     gp_offset - base_offset);
-		    fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
-		    if (! store_p
-			&& TARGET_MIPS16
-			&& regno != GP_REG_FIRST + 31
-			&& ! M16_REG_P (regno))
-		      fprintf (file, "\tmove\t%s,%s\n",
-			       reg_names[regno], reg_names[r]);
-		  }
-
-	      }
-	    gp_offset -= GET_MODE_SIZE (mips_reg_mode[0]);
-	  }
-    }
-  else
-    base_reg_rtx = 0, base_offset  = 0;
-
-  /* Save floating point registers if needed.  */
-  if (fmask)
-    {
-      int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
-      int fp_size = fp_inc * UNITS_PER_FPREG;
-
-      /* Pick which pointer to use as a base register.  */
-      fp_offset = current_frame_info.fp_sp_offset;
-      end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
-
-      if (fp_offset < 0 || end_offset < 0)
-	fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
-	       (long) fp_offset, (long) end_offset);
-
-      else if (fp_offset < 32768)
-	base_reg_rtx = stack_pointer_rtx, base_offset  = 0;
-
-      else if (base_reg_rtx != 0
-	       && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
-	       && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
-	;			/* already set up for gp registers above */
-
-      else if (large_reg != (rtx)0
-	       && (((unsigned HOST_WIDE_INT)(large_offset - fp_offset))  < 32768)
-	       && (((unsigned HOST_WIDE_INT)(large_offset - end_offset)) < 32768))
-	{
-	  base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
-	  base_offset = large_offset;
-	  if (file == 0)
-	    {
-	      if (Pmode == DImode)
-		insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
-					      stack_pointer_rtx));
-	      else
-		insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
-					      stack_pointer_rtx));
-	      if (store_p)
-		RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-
-	  else
-	    fprintf (file, "\t%s\t%s,%s,%s\n",
-		     Pmode == DImode ? "daddu" : "addu",
-		     reg_names[MIPS_TEMP2_REGNUM],
-		     reg_names[REGNO (large_reg)],
-		     reg_names[STACK_POINTER_REGNUM]);
-	}
-
-      else
-	{
-	  base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
-	  base_offset = fp_offset;
-	  if (file == 0)
-	    {
-	      rtx fp_offset_rtx = GEN_INT (fp_offset);
-
-	      /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
-		 bit, so make sure that we don't emit anything that can be
-		 split.  */
-	      /* ??? There is no DImode ori immediate pattern, so we can only
-		 do this for 32 bit code.  */
-	      if (large_int (fp_offset_rtx)
-		  && GET_MODE (base_reg_rtx) == SImode)
-		{
-		  insn = emit_move_insn (base_reg_rtx,
-					 GEN_INT (fp_offset & 0xffff0000));
-		  if (store_p)
-		    RTX_FRAME_RELATED_P (insn) = 1;
-		  insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
-						GEN_INT (fp_offset & 0x0000ffff)));
-		  if (store_p)
-		    RTX_FRAME_RELATED_P (insn) = 1;
-		}
-	      else
-		{
-		  insn = emit_move_insn (base_reg_rtx, fp_offset_rtx);
-		  if (store_p)
-		    RTX_FRAME_RELATED_P (insn) = 1;
-		}
-
-	      if (store_p)
-		RTX_FRAME_RELATED_P (insn) = 1;
-	      if (Pmode == DImode)
-		insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
-					      stack_pointer_rtx));
-	      else
-		insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
-					      stack_pointer_rtx));
-	      if (store_p)
-		RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	  else
-	    {
-	      fprintf (file, "\tli\t%s,0x%.08lx\t# ",
-		       reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
-	      fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
-	      fprintf (file, "\n\t%s\t%s,%s,%s\n",
-		       Pmode == DImode ? "daddu" : "addu",
-		       reg_names[MIPS_TEMP2_REGNUM],
-		       reg_names[MIPS_TEMP2_REGNUM],
-		       reg_names[STACK_POINTER_REGNUM]);
-	    }
-	}
-
-      /* This loop must iterate over the same space as its companion in
-	 compute_frame_size.  */
-      for (regno = (FP_REG_LAST - fp_inc + 1);
-	   regno >= FP_REG_FIRST;
-	   regno -= fp_inc)
-	if (BITSET_P (fmask, regno - FP_REG_FIRST))
-	  {
-	    if (file == 0)
-	      {
-		enum machine_mode sz
-		  = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
-		rtx reg_rtx = gen_rtx (REG, sz, regno);
-		rtx mem_rtx = gen_rtx (MEM, sz,
-				       gen_rtx (PLUS, Pmode, base_reg_rtx,
-						GEN_INT (fp_offset
-							 - base_offset)));
-		RTX_UNCHANGING_P (mem_rtx) = 1;
-
-		if (store_p)
-		  {
-		    insn = emit_move_insn (mem_rtx, reg_rtx);
-		    RTX_FRAME_RELATED_P (insn) = 1;
-		  }
-		else
-		  emit_move_insn (reg_rtx, mem_rtx);
-	      }
-	    else
-	      {
-		fprintf (file, "\t%s\t%s,",
-			 (TARGET_SINGLE_FLOAT
-			  ? (store_p ? "s.s" : "l.s")
-			  : (store_p ? "s.d" : "l.d")),
-			 reg_names[regno]);
-		fprintf (file, HOST_WIDE_INT_PRINT_DEC,
-			 fp_offset - base_offset);
-		fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
-	      }
-
-	    fp_offset -= fp_size;
-	  }
-    }
-}
-
-/* Set up the stack and frame (if desired) for the function.  */
-
-void
-function_prologue (file, size)
-     FILE *file;
-     int size ATTRIBUTE_UNUSED;
-{
-#ifndef FUNCTION_NAME_ALREADY_DECLARED
-  char *fnname;
-#endif
-  long tsize = current_frame_info.total_size;
-
-  ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
-
-#ifdef SDB_DEBUGGING_INFO
-  if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
-    ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
-#endif
-
-  /* In mips16 mode, we may need to generate a 32 bit to handle
-     floating point arguments.  The linker will arrange for any 32 bit
-     functions to call this stub, which will then jump to the 16 bit
-     function proper.  */
-  if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
-      && current_function_args_info.fp_code != 0)
-    build_mips16_function_stub (file);
-
-  inside_function = 1;
-
-#ifndef FUNCTION_NAME_ALREADY_DECLARED
-  /* Get the function name the same way that toplev.c does before calling
-     assemble_start_function.  This is needed so that the name used here
-     exactly matches the name used in ASM_DECLARE_FUNCTION_NAME.  */
-  fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
-
-  if (!flag_inhibit_size_directive)
-    {
-      fputs ("\t.ent\t", file);
-      assemble_name (file, fnname);
-      fputs ("\n", file);
-    }
-
-  assemble_name (file, fnname);
-  fputs (":\n", file);
-#endif
-
-  if (!flag_inhibit_size_directive)
-    {
-      /* .frame FRAMEREG, FRAMESIZE, RETREG */
-      fprintf (file,
-	       "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
-	       (reg_names[(frame_pointer_needed)
-			  ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
-	       ((frame_pointer_needed && TARGET_MIPS16)
-		? (tsize - current_function_outgoing_args_size)
-		: tsize),
-	       reg_names[31 + GP_REG_FIRST],
-	       current_frame_info.var_size,
-	       current_frame_info.num_gp,
-	       current_frame_info.num_fp,
-	       current_function_outgoing_args_size,
-	       current_frame_info.extra_size);
-
-      /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
-      fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
-	       current_frame_info.mask,
-	       current_frame_info.gp_save_offset,
-	       current_frame_info.fmask,
-	       current_frame_info.fp_save_offset);
-
-      /* Require:
-	 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
-	 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
-    }
-
-  if (mips_entry && ! mips_can_use_return_insn ())
-    {
-      int save16 = BITSET_P (current_frame_info.mask, 16);
-      int save17 = BITSET_P (current_frame_info.mask, 17);
-      int save31 = BITSET_P (current_frame_info.mask, 31);
-      int savearg = 0;
-      rtx insn;
-
-      /* Look through the initial insns to see if any of them store
-	 the function parameters into the incoming parameter storage
-	 area.  If they do, we delete the insn, and save the register
-	 using the entry pseudo-instruction instead.  We don't try to
-	 look past a label, jump, or call.  */
-      for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
-	{
-	  rtx note, set, src, dest, base, offset;
-	  int hireg;
-
-	  if (GET_CODE (insn) == CODE_LABEL
-	      || GET_CODE (insn) == JUMP_INSN
-	      || GET_CODE (insn) == CALL_INSN)
-	    break;
-	  if (GET_CODE (insn) != INSN)
-	    continue;
-	  set = PATTERN (insn);
-	  if (GET_CODE (set) != SET)
-	    continue;
-
-	  /* An insn storing a function parameter will still have a
-             REG_EQUIV note on it mentioning the argument pointer.  */
-	  note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
-	  if (note == NULL_RTX)
-	    continue;
-	  if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
-	    continue;
-
-	  src = SET_SRC (set);
-	  if (GET_CODE (src) != REG
-	      || REGNO (src) < GP_REG_FIRST + 4
-	      || REGNO (src) > GP_REG_FIRST + 7)
-	    continue;
-
-	  dest = SET_DEST (set);
-	  if (GET_CODE (dest) != MEM)
-	    continue;
-	  if (GET_MODE_SIZE (GET_MODE (dest)) == UNITS_PER_WORD)
-	    ;
-	  else if (GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
-		   && REGNO (src) < GP_REG_FIRST + 7)
-	    ;
-	  else
-	    continue;
-	  offset = const0_rtx;
-	  base = eliminate_constant_term (XEXP (dest, 0), &offset);
-	  if (GET_CODE (base) != REG
-	      || GET_CODE (offset) != CONST_INT)
-	    continue;
-	  if (REGNO (base) == STACK_POINTER_REGNUM
-	      && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
-	    ;
-	  else if (REGNO (base) == HARD_FRAME_POINTER_REGNUM
-		   && (INTVAL (offset)
-		       == (tsize
-			   + (REGNO (src) - 4) * UNITS_PER_WORD
-			   - current_function_outgoing_args_size)))
-	    ;
-	  else
-	    continue;
-
-	  /* This insn stores a parameter onto the stack, in the same
-             location where the entry pseudo-instruction will put it.
-             Delete the insn, and arrange to tell the entry
-             instruction to save the register.  */
-	  PUT_CODE (insn, NOTE);
-	  NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
-	  NOTE_SOURCE_FILE (insn) = 0;
-
-	  hireg = (REGNO (src)
-		   + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
-		   - 1);
-	  if (hireg > savearg)
-	    savearg = hireg;
-	}
-
-      /* If this is a varargs function, we need to save all the
-         registers onto the stack anyhow.  */
-      if (current_function_stdarg || current_function_varargs)
-	savearg = GP_REG_FIRST + 7;
-
-      fprintf (file, "\tentry\t");
-      if (savearg > 0)
-	{
-	  if (savearg == GP_REG_FIRST + 4)
-	    fprintf (file, "%s", reg_names[savearg]);
-	  else
-	    fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
-		     reg_names[savearg]);
-	}
-      if (save16 || save17)
-	{
-	  if (savearg > 0)
-	    fprintf (file, ",");
-	  fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
-	  if (save17)
-	    fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
-	}
-      if (save31)
-	{
-	  if (savearg > 0 || save16 || save17)
-	    fprintf (file, ",");
-	  fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
-	}
-      fprintf (file, "\n");
-    }
-
-  if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
-    {
-      char *sp_str = reg_names[STACK_POINTER_REGNUM];
-
-      fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
-	       reg_names[PIC_FUNCTION_ADDR_REGNUM]);
-      if (tsize > 0)
-	{
-	  fprintf (file, "\t%s\t%s,%s,%ld\n",
-		   (Pmode == DImode ? "dsubu" : "subu"),
-		   sp_str, sp_str, tsize);
-	  fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
-	}
-
-      if (dwarf2out_do_frame ())
-	dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
-    }
-}
-
-/* Expand the prologue into a bunch of separate insns.  */
-
-void
-mips_expand_prologue ()
-{
-  int regno;
-  HOST_WIDE_INT tsize;
-  rtx tmp_rtx = 0;
-  char *arg_name = 0;
-  tree fndecl = current_function_decl;
-  tree fntype = TREE_TYPE (fndecl);
-  tree fnargs = DECL_ARGUMENTS (fndecl);
-  rtx next_arg_reg;
-  int i;
-  tree next_arg;
-  tree cur_arg;
-  CUMULATIVE_ARGS args_so_far;
-  rtx reg_18_save = NULL_RTX;
-
-  /* If struct value address is treated as the first argument, make it so.  */
-  if (aggregate_value_p (DECL_RESULT (fndecl))
-      && ! current_function_returns_pcc_struct
-      && struct_value_incoming_rtx == 0)
-    {
-      tree type = build_pointer_type (fntype);
-      tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
-
-      DECL_ARG_TYPE (function_result_decl) = type;
-      TREE_CHAIN (function_result_decl) = fnargs;
-      fnargs = function_result_decl;
-    }
-
-  /* Determine the last argument, and get its name.  */
-
-  INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
-  regno = GP_ARG_FIRST;
-
-  for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
-    {
-      tree passed_type = DECL_ARG_TYPE (cur_arg);
-      enum machine_mode passed_mode = TYPE_MODE (passed_type);
-      rtx entry_parm;
-
-      if (TREE_ADDRESSABLE (passed_type))
-	{
-	  passed_type = build_pointer_type (passed_type);
-	  passed_mode = Pmode;
-	}
-
-      entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
-
-      if (entry_parm)
-	{
-	  int words;
-
-	  /* passed in a register, so will get homed automatically */
-	  if (GET_MODE (entry_parm) == BLKmode)
-	    words = (int_size_in_bytes (passed_type) + 3) / 4;
-	  else
-	    words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
-
-	  regno = REGNO (entry_parm) + words - 1;
-	}
-      else
-	{
-	  regno = GP_ARG_LAST+1;
-	  break;
-	}
-
-      FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
-
-      next_arg = TREE_CHAIN (cur_arg);
-      if (next_arg == 0)
-	{
-	  if (DECL_NAME (cur_arg))
-	    arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg));
-
-	  break;
-	}
-    }
-
-  /* In order to pass small structures by value in registers compatibly with
-     the MIPS compiler, we need to shift the value into the high part of the
-     register.  Function_arg has encoded a PARALLEL rtx, holding a vector of
-     adjustments to be made as the next_arg_reg variable, so we split up the
-     insns, and emit them separately.  */
-
-  next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
-  if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
-    {
-      rtvec adjust = XVEC (next_arg_reg, 0);
-      int num = GET_NUM_ELEM (adjust);
-
-      for (i = 0; i < num; i++)
-	{
-	  rtx pattern = RTVEC_ELT (adjust, i);
-	  if (GET_CODE (pattern) != SET
-	      || GET_CODE (SET_SRC (pattern)) != ASHIFT)
-	    abort_with_insn (pattern, "Insn is not a shift");
-
-	  PUT_CODE (SET_SRC (pattern), ASHIFTRT);
-	  emit_insn (pattern);
-	}
-    }
-
-  tsize = compute_frame_size (get_frame_size ());
-
-  /* If this function is a varargs function, store any registers that
-     would normally hold arguments ($4 - $7) on the stack.  */
-  if ((mips_abi == ABI_32 || mips_abi == ABI_O64)
-      && (! mips_entry || mips_can_use_return_insn ())
-      && ((TYPE_ARG_TYPES (fntype) != 0
-	   && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
-	       != void_type_node))
-	  || (arg_name != 0
-	      && ((arg_name[0] == '_'
-		   && strcmp (arg_name, "__builtin_va_alist") == 0)
-		  || (arg_name[0] == 'v'
-		      && strcmp (arg_name, "va_alist") == 0)))))
-    {
-      int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
-      rtx ptr = stack_pointer_rtx;
-
-      /* If we are doing svr4-abi, sp has already been decremented by tsize. */
-      if (TARGET_ABICALLS)
-	offset += tsize;
-
-      for (; regno <= GP_ARG_LAST; regno++)
-	{
-	  if (offset != 0)
-	    ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
-	  emit_move_insn (gen_rtx (MEM, mips_reg_mode[regno], ptr),
-			  gen_rtx (REG, mips_reg_mode[regno], regno));
-
-	  offset += GET_MODE_SIZE (mips_reg_mode[0]);
-	}
-    }
-
-  /* If we are using the entry pseudo instruction, it will
-     automatically subtract 32 from the stack pointer, so we don't
-     need to.  The entry pseudo instruction is emitted by
-     function_prologue.  */
-  if (mips_entry && ! mips_can_use_return_insn ())
-    {
-      if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
-	{
-          rtx insn;
-
-	  /* If we are using a frame pointer with a small stack frame,
-             we need to initialize it here since it won't be done
-             below.  */
-	  if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
-	    {
-	      rtx incr = GEN_INT (current_function_outgoing_args_size);
-	      if (Pmode == DImode)
-		insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
-                                              stack_pointer_rtx,
-                                              incr));
-	      else
-		insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
-                                              stack_pointer_rtx,
-                                              incr));
-	    }
-	  else if (Pmode == DImode)
-	    insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
-					 stack_pointer_rtx));
-	  else
-	    insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
-					 stack_pointer_rtx));
-
-          RTX_FRAME_RELATED_P (insn) = 1;
-	}
-
-      /* We may need to save $18, if it is used to call a function
-	 which may return a floating point value.  Set up a sequence
-	 of instructions to do so.  Later on we emit them at the right
-	 moment.  */
-      if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
-	{
-	  rtx reg_rtx = gen_rtx (REG, mips_reg_mode[GP_REG_FIRST + 3],
-				 GP_REG_FIRST + 3);
-	  long gp_offset, base_offset;
-
-	  gp_offset = current_frame_info.gp_sp_offset;
-	  if (BITSET_P (current_frame_info.mask, 16))
-	    gp_offset -= UNITS_PER_WORD;
-	  if (BITSET_P (current_frame_info.mask, 17))
-	    gp_offset -= UNITS_PER_WORD;
-	  if (BITSET_P (current_frame_info.mask, 31))
-	    gp_offset -= UNITS_PER_WORD;
-	  if (tsize > 32767)
-	    base_offset = tsize;
-	  else
-	    base_offset = 0;
-	  start_sequence ();
-	  emit_move_insn (reg_rtx,
-			  gen_rtx (REG, mips_reg_mode[GP_REG_FIRST + 18],
-				   GP_REG_FIRST + 18));
-	  emit_move_insn (gen_rtx (MEM, mips_reg_mode[GP_REG_FIRST + 18],
-				   gen_rtx (PLUS, Pmode, stack_pointer_rtx,
-					    GEN_INT (gp_offset
-						     - base_offset))),
-			  reg_rtx);
-	  reg_18_save = gen_sequence ();
-	  end_sequence ();
-	}
-
-      if (tsize > 32)
-	tsize -= 32;
-      else
-	{
-	  tsize = 0;
-	  if (reg_18_save != NULL_RTX)
-	    emit_insn (reg_18_save);
-	}
-    }
-
-  if (tsize > 0)
-    {
-      rtx tsize_rtx = GEN_INT (tsize);
-
-      /* If we are doing svr4-abi, sp move is done by
-         function_prologue.  In mips16 mode with a large frame, we
-         save the registers before adjusting the stack.  */
-      if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
-	  && (!TARGET_MIPS16 || tsize <= 32767))
-	{
-	  rtx insn;
-
-	  if (tsize > 32767)
-	    {
-	      tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
-
-	      /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
-		 bit, so make sure that we don't emit anything that can be
-		 split.  */
-	      /* ??? There is no DImode ori immediate pattern, so we can only
-		 do this for 32 bit code.  */
-	      if (large_int (tsize_rtx) && GET_MODE (tmp_rtx) == SImode)
-		{
-		  insn = emit_move_insn (tmp_rtx,
-					 GEN_INT (tsize & 0xffff0000));
-		  RTX_FRAME_RELATED_P (insn) = 1;
-		  insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
-						GEN_INT (tsize & 0x0000ffff)));
-		  RTX_FRAME_RELATED_P (insn) = 1;
-		}
-	      else
-		{
-		  insn = emit_move_insn (tmp_rtx, tsize_rtx);
-		  RTX_FRAME_RELATED_P (insn) = 1;
-		}
-
-	      tsize_rtx = tmp_rtx;
-	    }
-
-	  if (Pmode == DImode)
-	    insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
-					  tsize_rtx));
-	  else
-	    insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
-					  tsize_rtx));
-
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	}
-
-      if (! mips_entry)
-	save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
-      else if (reg_18_save != NULL_RTX)
-	emit_insn (reg_18_save);
-
-      if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
-	  && TARGET_MIPS16
-	  && tsize > 32767)
-	{
-	  rtx reg_rtx;
-
-	  if (!frame_pointer_needed)
-	    abort ();
-
-	  reg_rtx = gen_rtx (REG, Pmode, 3);
-  	  emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
-  	  emit_move_insn (reg_rtx, tsize_rtx);
-  	  if (Pmode == DImode)
-	    emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
-				   hard_frame_pointer_rtx,
-				   reg_rtx));
-	  else
-	    emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
-				   hard_frame_pointer_rtx,
-				   reg_rtx));
-	  emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
-	}
-
-      if (frame_pointer_needed)
-	{
-          rtx insn = 0;
-
-	  /* On the mips16, we encourage the use of unextended
-             instructions when using the frame pointer by pointing the
-             frame pointer ahead of the argument space allocated on
-             the stack.  */
-	  if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
-	      && TARGET_MIPS16
-	      && tsize > 32767)
-	    {
-	      /* In this case, we have already copied the stack
-                 pointer into the frame pointer, above.  We need only
-                 adjust for the outgoing argument size.  */
-	      if (current_function_outgoing_args_size != 0)
-		{
-		  rtx incr = GEN_INT (current_function_outgoing_args_size);
-		  if (Pmode == DImode)
-		    insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
-                                                  hard_frame_pointer_rtx,
-                                                  incr));
-		  else
-		    insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
-                                                  hard_frame_pointer_rtx,
-                                                  incr));
-		}
-	    }
-	  else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
-	    {
-	      rtx incr = GEN_INT (current_function_outgoing_args_size);
-	      if (Pmode == DImode)
-		insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
-                                              stack_pointer_rtx,
-                                              incr));
-	      else
-		insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
-                                              stack_pointer_rtx,
-                                              incr));
-	    }
-	  else if (Pmode == DImode)
-	    insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
-					 stack_pointer_rtx));
-	  else
-	    insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
-					 stack_pointer_rtx));
-
-	  if (insn)
-	    RTX_FRAME_RELATED_P (insn) = 1;
-	}
-
-      if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
-	emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
-			       gen_rtx (REG, DImode, 25)));
-    }
-
-  /* If we are profiling, make sure no instructions are scheduled before
-     the call to mcount.  */
-
-  if (profile_flag || profile_block_flag)
-    emit_insn (gen_blockage ());
-}
-
-/* Do any necessary cleanup after a function to restore stack, frame,
-   and regs. */
-
-#define RA_MASK ((long) 0x80000000)	/* 1 << 31 */
-#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
-
-void
-function_epilogue (file, size)
-     FILE *file ATTRIBUTE_UNUSED;
-     HOST_WIDE_INT size ATTRIBUTE_UNUSED;
-{
-  char *fnname;
-
-#ifndef FUNCTION_NAME_ALREADY_DECLARED
-  /* Get the function name the same way that toplev.c does before calling
-     assemble_start_function.  This is needed so that the name used here
-     exactly matches the name used in ASM_DECLARE_FUNCTION_NAME.  */
-  fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
-
-  if (!flag_inhibit_size_directive)
-    {
-      fputs ("\t.end\t", file);
-      assemble_name (file, fnname);
-      fputs ("\n", file);
-    }
-#endif
-
-  if (TARGET_STATS)
-    {
-      int num_gp_regs = current_frame_info.gp_reg_size / 4;
-      int num_fp_regs = current_frame_info.fp_reg_size / 8;
-      int num_regs = num_gp_regs + num_fp_regs;
-      char *name = fnname;
-
-      if (name[0] == '*')
-	name++;
-
-      dslots_load_total += num_regs;
-
-      fprintf (stderr,
-	       "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
-	       name, frame_pointer_needed ? 'y' : 'n',
-	       (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
-	       current_function_calls_alloca ? 'y' : 'n',
-	       current_function_calls_setjmp ? 'y' : 'n',
-	       current_frame_info.total_size,
-	       current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
-	       dslots_load_total, dslots_load_filled,
-	       dslots_jump_total, dslots_jump_filled,
-	       num_refs[0], num_refs[1], num_refs[2]);
-
-      if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
-	{
-	  fprintf (stderr,
-		   " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
-	  prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
-	}
-
-      if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
-	{
-	  fprintf (stderr,
-		   " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
-	  prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
-	}
-
-      fputc ('\n', stderr);
-    }
-
-  /* Reset state info for each function.  */
-  inside_function = 0;
-  ignore_line_number = 0;
-  dslots_load_total = 0;
-  dslots_jump_total = 0;
-  dslots_load_filled = 0;
-  dslots_jump_filled = 0;
-  num_refs[0] = 0;
-  num_refs[1] = 0;
-  num_refs[2] = 0;
-  mips_load_reg = 0;
-  mips_load_reg2 = 0;
-  current_frame_info = zero_frame_info;
-
-  while (string_constants != NULL)
-    {
-      struct string_constant *next;
-
-      next = string_constants->next;
-      free (string_constants);
-      string_constants = next;
-    }
-
-  /* Restore the output file if optimizing the GP (optimizing the GP causes
-     the text to be diverted to a tempfile, so that data decls come before
-     references to the data).  */
-
-  if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS)
-    asm_out_file = asm_out_data_file;
-}
-
-/* Expand the epilogue into a bunch of separate insns.  */
-
-void
-mips_expand_epilogue ()
-{
-  HOST_WIDE_INT tsize = current_frame_info.total_size;
-  rtx tsize_rtx = GEN_INT (tsize);
-  rtx tmp_rtx = (rtx)0;
-
-  if (mips_can_use_return_insn ())
-    {
-      emit_insn (gen_return ());
-      return;
-    }
-
-  if (mips_entry && ! mips_can_use_return_insn ())
-    tsize -= 32;
-
-  if (tsize > 32767 && ! TARGET_MIPS16)
-    {
-      tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
-      emit_move_insn (tmp_rtx, tsize_rtx);
-      tsize_rtx = tmp_rtx;
-    }
-
-  if (tsize > 0)
-    {
-      long orig_tsize = tsize;
-
-      if (frame_pointer_needed)
-	{
-	  emit_insn (gen_blockage ());
-
-	  /* On the mips16, the frame pointer is offset from the stack
-             pointer by current_function_outgoing_args_size.  We
-             account for that by changing tsize.  Note that this can
-             actually make tsize negative.  */
-	  if (TARGET_MIPS16)
-	    {
-	      tsize -= current_function_outgoing_args_size;
-
-	      /* If we have a large frame, it's easier to add to $17
-                 than to $sp, since the mips16 has no instruction to
-                 add a register to $sp.  */
-	      if (orig_tsize > 32767)
-		{
-		  rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
-
-		  emit_move_insn (g6_rtx, GEN_INT (tsize));
-		  if (Pmode == DImode)
-		    emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
-					   hard_frame_pointer_rtx,
-					   g6_rtx));
-		  else
-		    emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
-					   hard_frame_pointer_rtx,
-					   g6_rtx));
-		  tsize = 0;
-		}
-	      
-	      if (tsize && tsize != orig_tsize)
-		tsize_rtx = GEN_INT (tsize);
-	    }
-
-	  if (Pmode == DImode)
-	    emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
-	  else
-	    emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
-	}
-
-      /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
-	 are going to restore it, then we must emit a blockage insn to
-	 prevent the scheduler from moving the restore out of the epilogue.  */
-      else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
-	       && (current_frame_info.mask
-		   & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
-	emit_insn (gen_blockage ());
-
-      save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
-
-      /* In mips16 mode with a large frame, we adjust the stack
-         pointer before restoring the registers.  In this case, we
-         should always be using a frame pointer, so everything should
-         have been handled above.  */
-      if (tsize > 32767 && TARGET_MIPS16)
-	abort ();
-
-      emit_insn (gen_blockage ());
-      if (Pmode == DImode && tsize != 0)
-	emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
-			       tsize_rtx));
-      else if (tsize != 0)
-	emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
-			       tsize_rtx));
-    }
-
-  /* The mips16 loads the return address into $7, not $31.  */
-  if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
-    emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
-						  GP_REG_FIRST + 7)));
-  else
-    emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
-						  GP_REG_FIRST + 31)));
-}
-
-/* Return nonzero if this function is known to have a null epilogue.
-   This allows the optimizer to omit jumps to jumps if no stack
-   was created.  */
-
-int
-mips_can_use_return_insn ()
-{
-  if (! reload_completed)
-    return 0;
-
-  if (regs_ever_live[31] || profile_flag)
-    return 0;
-
-  /* In mips16 mode, a function which returns a floating point value
-     needs to arrange to copy the return value into the floating point
-     registers.  */
-  if (TARGET_MIPS16
-      && mips16_hard_float
-      && ! aggregate_value_p (DECL_RESULT (current_function_decl))
-      && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
-	  == MODE_FLOAT)
-      && (! TARGET_SINGLE_FLOAT
-	  || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
-	      <= 4)))
-    return 0;
-
-  if (current_frame_info.initialized)
-    return current_frame_info.total_size == 0;
-
-  return compute_frame_size (get_frame_size ()) == 0;
-}
-
-/* Choose the section to use for the constant rtx expression X that has
-   mode MODE.  */
-
-void
-mips_select_rtx_section (mode, x)
-     enum machine_mode mode;
-     rtx x ATTRIBUTE_UNUSED;
-{
-  if (TARGET_MIPS16)
-    {
-      /* In mips16 mode, the constant table always goes in the same section
-         as the function, so that constants can be loaded using PC relative
-         addressing.  */
-      function_section (current_function_decl);
-    }
-  else if (TARGET_EMBEDDED_DATA)
-    {
-      /* For embedded applications, always put constants in read-only data,
-	 in order to reduce RAM usage.  */
-      READONLY_DATA_SECTION ();
-    }
-  else
-    {
-      /* For hosted applications, always put constants in small data if
-	 possible, as this gives the best performance.  */
-     
-      if (GET_MODE_SIZE (mode) <= mips_section_threshold
-	  && mips_section_threshold > 0)
-	SMALL_DATA_SECTION ();
-      else
-	READONLY_DATA_SECTION ();
-    }
-}
-
-/* Choose the section to use for DECL.  RELOC is true if its value contains
-   any relocatable expression.
-
-   Some of the logic used here needs to be replicated in
-   ENCODE_SECTION_INFO in mips.h so that references to these symbols
-   are done correctly.  Specifically, at least all symbols assigned
-   here to rom (.text and/or .rodata) must not be referenced via
-   ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
-
-   If you need to make a change here, you probably should check
-   ENCODE_SECTION_INFO to see if it needs a similar change.  */
-
-void
-mips_select_section (decl, reloc)
-     tree decl;
-     int reloc;
-{
-  int size = int_size_in_bytes (TREE_TYPE (decl));
-
-  if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
-      && TREE_CODE (decl) == STRING_CST
-      && !flag_writable_strings)
-    /* For embedded position independent code, put constant strings in the
-       text section, because the data section is limited to 64K in size.
-       For mips16 code, put strings in the text section so that a PC
-       relative load instruction can be used to get their address.  */
-    text_section ();
-  else if (TARGET_EMBEDDED_DATA)
-    {
-      /* For embedded applications, always put an object in read-only data
-	 if possible, in order to reduce RAM usage.  */
-
-      if (((TREE_CODE (decl) == VAR_DECL
-	    && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
-	    && DECL_INITIAL (decl)
-	    && (DECL_INITIAL (decl) == error_mark_node
-		|| TREE_CONSTANT (DECL_INITIAL (decl))))
-	   /* Deal with calls from output_constant_def_contents.  */
-	   || (TREE_CODE (decl) != VAR_DECL
-	       && (TREE_CODE (decl) != STRING_CST
-		   || !flag_writable_strings)))
-	  && ! (flag_pic && reloc))
-	READONLY_DATA_SECTION ();
-      else if (size > 0 && size <= mips_section_threshold)
-	SMALL_DATA_SECTION ();
-      else
-	data_section ();
-    }
-  else
-    {
-      /* For hosted applications, always put an object in small data if
-	 possible, as this gives the best performance.  */
-
-      if (size > 0 && size <= mips_section_threshold)
-	SMALL_DATA_SECTION ();
-      else if (((TREE_CODE (decl) == VAR_DECL
-		 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
-		 && DECL_INITIAL (decl)
-		 && (DECL_INITIAL (decl) == error_mark_node
-		     || TREE_CONSTANT (DECL_INITIAL (decl))))
-		/* Deal with calls from output_constant_def_contents.  */
-		|| (TREE_CODE (decl) != VAR_DECL
-		    && (TREE_CODE (decl) != STRING_CST
-			|| !flag_writable_strings)))
-	       && ! (flag_pic && reloc))
-	READONLY_DATA_SECTION ();
-      else
-	data_section ();
-    }
-}
-
-#ifdef MIPS_ABI_DEFAULT
-
-/* Support functions for the 64 bit ABI.  */
-
-/* Return register to use for a function return value with VALTYPE for function
-   FUNC.  */
-
-rtx
-mips_function_value (valtype, func)
-     tree valtype;
-     tree func ATTRIBUTE_UNUSED;
-{
-  int reg = GP_RETURN;
-  enum machine_mode mode = TYPE_MODE (valtype);
-  enum mode_class mclass = GET_MODE_CLASS (mode);
-  int unsignedp = TREE_UNSIGNED (valtype);
-
-  /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
-     just as PROMOTE_MODE does.  */
-  mode = promote_mode (valtype, mode, &unsignedp, 1);
-
-  /* ??? How should we return complex float?  */
-  if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
-    {
-      if (TARGET_SINGLE_FLOAT
-	  && (mclass == MODE_FLOAT
-	      ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
-	reg = GP_RETURN;
-      else
-	reg = FP_RETURN;
-    }
-
-  else if (TREE_CODE (valtype) == RECORD_TYPE
-	   && mips_abi != ABI_32 
-	   && mips_abi != ABI_O64 
-	   && mips_abi != ABI_EABI)
-    {
-      /* A struct with only one or two floating point fields is returned in
-	 the floating point registers.  */
-      tree field, fields[2];
-      int i;
-
-      for (i = 0, field = TYPE_FIELDS (valtype); field;
-	   field = TREE_CHAIN (field))
-	{
-	  if (TREE_CODE (field) != FIELD_DECL)
-	    continue;
-
-	  if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
-	    break;
-
-	  fields[i++] = field;
-	}
-	  
-      /* Must check i, so that we reject structures with no elements.  */
-      if (! field)
-	{
-	  if (i == 1)
-	    {
-	      /* The structure has DImode, but we don't allow DImode values
-		 in FP registers, so we use a PARALLEL even though it isn't
-		 strictly necessary.  */
-	      enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
-
-	      return gen_rtx (PARALLEL, mode,
-			      gen_rtvec (1,
-					 gen_rtx (EXPR_LIST, VOIDmode,
-						  gen_rtx (REG, field_mode,
-							   FP_RETURN),
-						  const0_rtx)));
-	    }
-
-	  else if (i == 2)
-	    {
-	      enum machine_mode first_mode
-		= TYPE_MODE (TREE_TYPE (fields[0]));
-	      enum machine_mode second_mode
-		= TYPE_MODE (TREE_TYPE (fields[1]));
-	      int first_offset
-		= TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[0]));
-	      int second_offset
-		= TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1]));
-
-	      return gen_rtx (PARALLEL, mode,
-			      gen_rtvec (2,
-					 gen_rtx (EXPR_LIST, VOIDmode,
-						  gen_rtx (REG, first_mode,
-							   FP_RETURN),
-						  GEN_INT (first_offset
-							   / BITS_PER_UNIT)),
-					 gen_rtx (EXPR_LIST, VOIDmode,
-						  gen_rtx (REG, second_mode,
-							   FP_RETURN + 2),
-						  GEN_INT (second_offset
-							   / BITS_PER_UNIT))));
-	    }
-	}
-    }
-
-  return gen_rtx (REG, mode, reg);
-}
-
-/* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE.  Return
-   nonzero when an argument must be passed by reference.  */
-
-int
-function_arg_pass_by_reference (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
-     enum machine_mode mode;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
-{
-  int size;
-
-  if (mips_abi != ABI_EABI)
-    return 0;
-
-  /* ??? How should SCmode be handled?  */
-  if (type == NULL_TREE || mode == DImode || mode == DFmode)
-    return 0;
-
-
-  size = int_size_in_bytes (type);
-  return size == -1 || size > UNITS_PER_WORD;
-}
-#endif
-
-/* This function returns the register class required for a secondary
-   register when copying between one of the registers in CLASS, and X,
-   using MODE.  If IN_P is nonzero, the copy is going from X to the
-   register, otherwise the register is the source.  A return value of
-   NO_REGS means that no secondary register is required.  */
-
-enum reg_class
-mips_secondary_reload_class (class, mode, x, in_p)
-     enum reg_class class;
-     enum machine_mode mode;
-     rtx x;
-     int in_p;
-{
-  enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
-  int regno = -1;
-  int gp_reg_p;
-
-  if (GET_CODE (x) == SIGN_EXTEND)
-    {
-      int off = 0;
-
-      x = XEXP (x, 0);
-
-      /* We may be called with reg_renumber NULL from regclass.
-	 ??? This is probably a bug.  */
-      if (reg_renumber)
-	regno = true_regnum (x);
-      else
-	{
-	  while (GET_CODE (x) == SUBREG)
-	    {
-	      off += SUBREG_WORD (x);
-	      x = SUBREG_REG (x);
-	    }
-
-	  if (GET_CODE (x) == REG)
-	    regno = REGNO (x) + off;
-	}
-    }
-
-  else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
-    regno = true_regnum (x);
-
-  gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
-
-  /* We always require a general register when copying anything to
-     HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
-     to a general register, or when copying from register 0.  */
-  if (class == HILO_REG && regno != GP_REG_FIRST + 0)
-    return ((! in_p
-	     && gp_reg_p
-	     && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
-	    ? NO_REGS : gr_regs);
-  else if (regno == HILO_REGNUM)
-    return ((in_p
-	     && class == gr_regs
-	     && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
-	    ? NO_REGS : gr_regs);
-
-  /* Copying from HI or LO to anywhere other than a general register
-     requires a general register.  */
-  if (class == HI_REG || class == LO_REG || class == MD_REGS)
-    {
-      if (TARGET_MIPS16 && in_p)
-	{
-	  /* We can't really copy to HI or LO at all in mips16 mode.  */
-	  return M16_REGS;
-	}
-      return gp_reg_p ? NO_REGS : gr_regs;
-    }
-  if (MD_REG_P (regno))
-    {
-      if (TARGET_MIPS16 && ! in_p)
-	{
-	  /* We can't really copy to HI or LO at all in mips16 mode.  */
-	  return M16_REGS;
-	}
-      return class == gr_regs ? NO_REGS : gr_regs;
-    }
-
-  /* We can only copy a value to a condition code register from a
-     floating point register, and even then we require a scratch
-     floating point register.  We can only copy a value out of a
-     condition code register into a general register.  */
-  if (class == ST_REGS)
-    {
-      if (in_p)
-	return FP_REGS;
-      return GP_REG_P (regno) ? NO_REGS : GR_REGS;
-    }
-  if (ST_REG_P (regno))
-    {
-      if (! in_p)
-	return FP_REGS;
-      return class == GR_REGS ? NO_REGS : GR_REGS;
-    }
-
-  /* In mips16 mode, going between memory and anything but M16_REGS
-     requires an M16_REG.  */
-  if (TARGET_MIPS16)
-    {
-      if (class != M16_REGS && class != M16_NA_REGS)
-	{
-	  if (gp_reg_p)
-	    return NO_REGS;
-	  return M16_REGS;
-	}
-      if (! gp_reg_p)
-	{
-	  /* The stack pointer isn't a valid operand to an add instruction,
-	     so we need to load it into M16_REGS first.  This can happen as
-	     a result of register elimination and form_sum converting
-	     (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST).  We
-	     need an extra register if the dest is the same as the other
-	     register.  In that case, we can't fix the problem by loading SP
-	     into the dest first.  */
-	  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
-	      && GET_CODE (XEXP (x, 1)) == REG
-	      && (XEXP (x, 0) == stack_pointer_rtx
-		  || XEXP (x, 1) == stack_pointer_rtx))
-	    return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
-
-	  if (class == M16_REGS || class == M16_NA_REGS)
-	    return NO_REGS;
-	  return M16_REGS;
-	}
-    }
-
-  return NO_REGS;
-}
-
-/* For each mips16 function which refers to GP relative symbols, we
-   use a pseudo register, initialized at the start of the function, to
-   hold the $gp value.  */
-
-rtx
-mips16_gp_pseudo_reg ()
-{
-  if (mips16_gp_pseudo_rtx == NULL_RTX)
-    {
-      rtx const_gp;
-      rtx insn, scan;
-
-      mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
-      RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
-
-      /* We want to initialize this to a value which gcc will believe
-         is constant.  */
-      const_gp = gen_rtx (CONST, Pmode,
-			  gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
-
-      start_sequence ();
-      emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
-      insn = gen_sequence ();
-      end_sequence ();
-
-      push_topmost_sequence ();
-      /* We need to emit the initialization after the FUNCTION_BEG
-         note, so that it will be integrated.  */
-      for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
-	if (GET_CODE (scan) == NOTE
-	    && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
-	  break;
-      if (scan == NULL_RTX)
-	scan = get_insns ();
-      insn = emit_insn_after (insn, scan);
-      pop_topmost_sequence ();
-    }
-
-  return mips16_gp_pseudo_rtx;
-}
-
-/* Return an RTX which represents the signed 16 bit offset from the
-   $gp register for the given symbol.  This is only used on the
-   mips16.  */
-
-rtx
-mips16_gp_offset (sym)
-     rtx sym;
-{
-  tree gp;
-
-  if (GET_CODE (sym) != SYMBOL_REF
-      || ! SYMBOL_REF_FLAG (sym))
-    abort ();
-
-  /* We use a special identifier to represent the value of the gp
-     register.  */
-  gp = get_identifier ("__mips16_gp_value");
-
-  return gen_rtx (CONST, Pmode,
-		  gen_rtx (MINUS, Pmode, sym,
-			   gen_rtx (SYMBOL_REF, Pmode,
-				    IDENTIFIER_POINTER (gp))));
-}
-
-/* Return nonzero if the given RTX represents a signed 16 bit offset
-   from the $gp register.  */
-
-int
-mips16_gp_offset_p (x)
-     rtx x;
-{
-  if (GET_CODE (x) == CONST)
-    x = XEXP (x, 0);
-
-  /* It's OK to add a small integer value to a gp offset.  */
-  if (GET_CODE (x) == PLUS)
-    {
-      if (GET_CODE (XEXP (x, 1)) == CONST_INT
-	  && SMALL_INT (XEXP (x, 1)))
-	return mips16_gp_offset_p (XEXP (x, 0));
-      if (GET_CODE (XEXP (x, 0)) == CONST_INT
-	  && SMALL_INT (XEXP (x, 0)))
-	return mips16_gp_offset_p (XEXP (x, 1));
-      return 0;
-    }
-
-  /* Make sure it is in the form SYM - __mips16_gp_value.  */
-  return (GET_CODE (x) == MINUS
-	  && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
-	  && SYMBOL_REF_FLAG (XEXP (x, 0))
-	  && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
-	  && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
-}
-
-/* Output a GP offset.  We don't want to print the subtraction of
-   __mips16_gp_value; it is implicitly represented by the %gprel which
-   should have been printed by the caller.  */
-
-static void
-mips16_output_gp_offset (file, x)
-     FILE *file;
-     rtx x;
-{
-  if (GET_CODE (x) == CONST)
-    x = XEXP (x, 0);
-
-  if (GET_CODE (x) == PLUS)
-    {
-      mips16_output_gp_offset (file, XEXP (x, 0));
-      fputs ("+", file);
-      mips16_output_gp_offset (file, XEXP (x, 1));
-      return;
-    }
-
-  if (GET_CODE (x) == MINUS
-      && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
-      && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
-    {
-      mips16_output_gp_offset (file, XEXP (x, 0));
-      return;
-    }
-
-  output_addr_const (file, x);
-}
-
-/* Return nonzero if a constant should not be output until after the
-   function.  This is true of most string constants, so that we can
-   use a more efficient PC relative reference.  However, a static
-   inline function may never call assemble_function_end to write out
-   the constant pool, so don't try to postpone the constant in that
-   case.
-
-   ??? It's really a bug that a static inline function can put stuff
-   in the constant pool even if the function itself is not output.
-
-   We record which string constants we've seen, so that we know which
-   ones might use the more efficient reference.  */
-
-int
-mips16_constant_after_function_p (x)
-     tree x;
-{
-  if (TREE_CODE (x) == STRING_CST
-      && ! flag_writable_strings
-      && current_function_decl != 0
-      && ! DECL_DEFER_OUTPUT (current_function_decl)
-      && ! (DECL_INLINE (current_function_decl)
-	    && ((! TREE_PUBLIC (current_function_decl)
-		 && ! TREE_ADDRESSABLE (current_function_decl)
-		 && ! flag_keep_inline_functions)
-		|| DECL_EXTERNAL (current_function_decl))))
-    {
-      struct string_constant *n;
-
-      n = (struct string_constant *) xmalloc (sizeof *n);
-      n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
-      n->next = string_constants;
-      string_constants = n;
-
-      return 1;
-    }
-
-  return 0;
-}
-
-/* Validate a constant for the mips16.  This rejects general symbolic
-   addresses, which must be loaded from memory.  If ADDR is nonzero,
-   this should reject anything which is not a legal address.  If
-   ADDEND is nonzero, this is being added to something else.  */
-
-int
-mips16_constant (x, mode, addr, addend)
-     rtx x;
-     enum machine_mode mode;
-     int addr;
-     int addend;
-{
-  while (GET_CODE (x) == CONST)
-    x = XEXP (x, 0);
-
-  switch (GET_CODE (x))
-    {
-    default:
-      return 0;
-
-    case PLUS:
-      return (mips16_constant (XEXP (x, 0), mode, addr, 1)
-	      && mips16_constant (XEXP (x, 1), mode, addr, 1));
-
-    case SYMBOL_REF:
-      if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
-	return 0;
-      if (CONSTANT_POOL_ADDRESS_P (x))
-	return 1;
-
-      /* If we aren't looking for a memory address, we can accept a GP
-         relative symbol, which will have SYMBOL_REF_FLAG set; movsi
-         knows how to handle this.  We can always accept a string
-         constant, which is the other case in which SYMBOL_REF_FLAG
-         will be set.  */
-      if (! addr && ! addend && SYMBOL_REF_FLAG (x) && mode == Pmode)
-	return 1;
-
-      /* We can accept a string constant, which will have
-         SYMBOL_REF_FLAG set but must be recognized by name to
-         distinguish from a GP accessible symbol.  The name of a
-         string constant will have been generated by
-         ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def.  */
-      if (SYMBOL_REF_FLAG (x))
-	{
-	  char *name = XSTR (x, 0);
-
-	  return (name[0] == '*'
-		  && strncmp (name + 1, LOCAL_LABEL_PREFIX,
-			      sizeof LOCAL_LABEL_PREFIX - 1) == 0);
-	}
-
-      return 0;
-
-    case LABEL_REF:
-      if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
-	return 0;
-      return 1;
-
-    case CONST_INT:
-      if (addr && ! addend)
-	return 0;
-      return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
-
-    case REG:
-      /* We need to treat $gp as a legitimate constant, because
-         mips16_gp_pseudo_reg assumes that.  */
-      return REGNO (x) == GP_REG_FIRST + 28;
-    }
-}
-
-/* Write out code to move floating point arguments in or out of
-   general registers.  Output the instructions to FILE.  FP_CODE is
-   the code describing which arguments are present (see the comment at
-   the definition of CUMULATIVE_ARGS in mips.h).  FROM_FP_P is non-zero if
-   we are copying from the floating point registers.  */
-
-static void
-mips16_fp_args (file, fp_code, from_fp_p)
-     FILE *file;
-     int fp_code;
-     int from_fp_p;
-{
-  char *s;
-  int gparg, fparg;
-  unsigned int f;
-
-  /* This code only works for the original 32 bit ABI and the O64 ABI.  */
-  if (mips_abi != ABI_32 && mips_abi != ABI_O64)
-    abort ();
-
-  if (from_fp_p)
-    s = "mfc1";
-  else
-    s = "mtc1";
-  gparg = GP_ARG_FIRST;
-  fparg = FP_ARG_FIRST;
-  for (f = (unsigned int) fp_code; f != 0; f >>= 2)
-    {
-      if ((f & 3) == 1)
-	{
-	  if ((fparg & 1) != 0)
-	    ++fparg;
-	  fprintf (file, "\t%s\t%s,%s\n", s,
-		   reg_names[gparg], reg_names[fparg]);
-	}
-      else if ((f & 3) == 2)
-	{
-	  if (TARGET_64BIT)
-	    fprintf (file, "\td%s\t%s,%s\n", s,
-		     reg_names[gparg], reg_names[fparg]);
-	  else
-	    {
-	      if ((fparg & 1) != 0)
-		++fparg;
-	      if (TARGET_BIG_ENDIAN)
-		fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
-			 reg_names[gparg], reg_names[fparg + 1], s,
-			 reg_names[gparg + 1], reg_names[fparg]);
-	      else
-		fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
-			 reg_names[gparg], reg_names[fparg], s,
-			 reg_names[gparg + 1], reg_names[fparg + 1]);
-	      ++gparg;
-	      ++fparg;
-	    }
-	}
-      else
-	abort ();
-
-      ++gparg;
-      ++fparg;
-    }
-}
-
-/* Build a mips16 function stub.  This is used for functions which
-   take aruments in the floating point registers.  It is 32 bit code
-   that moves the floating point args into the general registers, and
-   then jumps to the 16 bit code.  */
-
-static void
-build_mips16_function_stub (file)
-     FILE *file;
-{
-  char *fnname;
-  char *secname, *stubname;
-  tree stubid, stubdecl;
-  int need_comma;
-  unsigned int f;
-
-  fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
-  secname = (char *) alloca (strlen (fnname) + 20);
-  sprintf (secname, ".mips16.fn.%s", fnname);
-  stubname = (char *) alloca (strlen (fnname) + 20);
-  sprintf (stubname, "__fn_stub_%s", fnname);
-  stubid = get_identifier (stubname);
-  stubdecl = build_decl (FUNCTION_DECL, stubid,
-			 build_function_type (void_type_node, NULL_TREE));
-  DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
-
-  fprintf (file, "\t# Stub function for %s (", current_function_name);
-  need_comma = 0;
-  for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
-    {
-      fprintf (file, "%s%s",
-	       need_comma ? ", " : "",
-	       (f & 3) == 1 ? "float" : "double");
-      need_comma = 1;
-    }
-  fprintf (file, ")\n");
-
-  fprintf (file, "\t.set\tnomips16\n");
-  function_section (stubdecl);
-  ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
-
-  /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
-     within a .ent, and we can not emit another .ent.  */
-#ifndef FUNCTION_NAME_ALREADY_DECLARED
-  fputs ("\t.ent\t", file);
-  assemble_name (file, stubname);
-  fputs ("\n", file);
-#endif
-
-  assemble_name (file, stubname);
-  fputs (":\n", file);
-
-  /* We don't want the assembler to insert any nops here.  */
-  fprintf (file, "\t.set\tnoreorder\n");
-
-  mips16_fp_args (file, current_function_args_info.fp_code, 1);
-
-  fprintf (asm_out_file, "\t.set\tnoat\n");
-  fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
-  assemble_name (file, fnname);
-  fprintf (file, "\n");
-  fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
-  fprintf (asm_out_file, "\t.set\tat\n");
-
-  /* Unfortunately, we can't fill the jump delay slot.  We can't fill
-     with one of the mfc1 instructions, because the result is not
-     available for one instruction, so if the very first instruction
-     in the function refers to the register, it will see the wrong
-     value.  */
-  fprintf (file, "\tnop\n");
-
-  fprintf (file, "\t.set\treorder\n");
-
-#ifndef FUNCTION_NAME_ALREADY_DECLARED
-  fputs ("\t.end\t", file);
-  assemble_name (file, stubname);
-  fputs ("\n", file);
-#endif
-
-  fprintf (file, "\t.set\tmips16\n");
-
-  function_section (current_function_decl);
-}
-
-/* We keep a list of functions for which we have already built stubs
-   in build_mips16_call_stub.  */
-
-struct mips16_stub
-{
-  struct mips16_stub *next;
-  char *name;
-  int fpret;
-};
-
-static struct mips16_stub *mips16_stubs;
-
-/* Build a call stub for a mips16 call.  A stub is needed if we are
-   passing any floating point values which should go into the floating
-   point registers.  If we are, and the call turns out to be to a 32
-   bit function, the stub will be used to move the values into the
-   floating point registers before calling the 32 bit function.  The
-   linker will magically adjust the function call to either the 16 bit
-   function or the 32 bit stub, depending upon where the function call
-   is actually defined.
-
-   Similarly, we need a stub if the return value might come back in a
-   floating point register.
-
-   RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
-   (RETVAL is NULL if this is call rather than call_value).  FP_CODE
-   is the code built by function_arg.  This function returns a nonzero
-   value if it builds the call instruction itself.  */
-
-int
-build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
-     rtx retval;
-     rtx fnmem;
-     rtx arg_size;
-     int fp_code;
-{
-  int fpret;
-  rtx fn;
-  char *fnname, *secname, *stubname;
-  struct mips16_stub *l;
-  tree stubid, stubdecl;
-  int need_comma;
-  unsigned int f;
-
-  /* We don't need to do anything if we aren't in mips16 mode, or if
-     we were invoked with the -msoft-float option.  */
-  if (! TARGET_MIPS16 || ! mips16_hard_float)
-    return 0;
-
-  /* Figure out whether the value might come back in a floating point
-     register.  */
-  fpret = (retval != 0
-	   && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
-	   && (! TARGET_SINGLE_FLOAT
-	       || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
-
-  /* We don't need to do anything if there were no floating point
-     arguments and the value will not be returned in a floating point
-     register.  */
-  if (fp_code == 0 && ! fpret)
-    return 0;
-
-  if (GET_CODE (fnmem) != MEM)
-    abort ();
-  fn = XEXP (fnmem, 0);
-
-  /* We don't need to do anything if this is a call to a special
-     mips16 support function.  */
-  if (GET_CODE (fn) == SYMBOL_REF
-      && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
-    return 0;
-
-  /* This code will only work for o32 and o64 abis.  The other ABI's 
-     require more sophisticated support.  */
-  if (mips_abi != ABI_32 && mips_abi != ABI_O64)
-    abort ();
-
-  /* We can only handle SFmode and DFmode floating point return
-     values.  */
-  if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
-    abort ();
-
-  /* If we're calling via a function pointer, then we must always call
-     via a stub.  There are magic stubs provided in libgcc.a for each
-     of the required cases.  Each of them expects the function address
-     to arrive in register $2.  */
-
-  if (GET_CODE (fn) != SYMBOL_REF)
-    {
-      char buf[30];
-      tree id;
-      rtx stub_fn, stub_mem, insn;
-
-      /* ??? If this code is modified to support other ABI's, we need
-         to handle PARALLEL return values here.  */
-
-      sprintf (buf, "__mips16_call_stub_%s%d",
-	       (fpret
-		? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
-		: ""),
-	       fp_code);
-      id = get_identifier (buf);
-      stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
-      stub_mem = gen_rtx (MEM, Pmode, stub_fn);
-
-      emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
-
-      if (retval == NULL_RTX)
-	insn = gen_call_internal0 (stub_mem, arg_size,
-				   gen_rtx (REG, SImode,
-					    GP_REG_FIRST + 31));
-      else
-	insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
-					 gen_rtx (REG, SImode,
-						  GP_REG_FIRST + 31));
-      insn = emit_call_insn (insn);
-
-      /* Put the register usage information on the CALL.  */
-      if (GET_CODE (insn) != CALL_INSN)
-	abort ();
-      CALL_INSN_FUNCTION_USAGE (insn) =
-	gen_rtx (EXPR_LIST, VOIDmode,
-		 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
-		 CALL_INSN_FUNCTION_USAGE (insn));
-
-      /* If we are handling a floating point return value, we need to
-         save $18 in the function prologue.  Putting a note on the
-         call will mean that regs_ever_live[$18] will be true if the
-         call is not eliminated, and we can check that in the prologue
-         code.  */
-      if (fpret)
-	CALL_INSN_FUNCTION_USAGE (insn) =
-	  gen_rtx (EXPR_LIST, VOIDmode,
-		   gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
-		   CALL_INSN_FUNCTION_USAGE (insn));
-
-      /* Return 1 to tell the caller that we've generated the call
-         insn.  */
-      return 1;
-    }
-
-  /* We know the function we are going to call.  If we have already
-     built a stub, we don't need to do anything further.  */
-
-  fnname = XSTR (fn, 0);
-  for (l = mips16_stubs; l != NULL; l = l->next)
-    if (strcmp (l->name, fnname) == 0)
-      break;
-
-  if (l == NULL)
-    {
-      /* Build a special purpose stub.  When the linker sees a
-	 function call in mips16 code, it will check where the target
-	 is defined.  If the target is a 32 bit call, the linker will
-	 search for the section defined here.  It can tell which
-	 symbol this section is associated with by looking at the
-	 relocation information (the name is unreliable, since this
-	 might be a static function).  If such a section is found, the
-	 linker will redirect the call to the start of the magic
-	 section.
-
-	 If the function does not return a floating point value, the
-	 special stub section is named
-	     .mips16.call.FNNAME
-
-	 If the function does return a floating point value, the stub
-	 section is named
-	     .mips16.call.fp.FNNAME
-	 */
-
-      secname = (char *) alloca (strlen (fnname) + 40);
-      sprintf (secname, ".mips16.call.%s%s",
-	       fpret ? "fp." : "",
-	       fnname);
-      stubname = (char *) alloca (strlen (fnname) + 20);
-      sprintf (stubname, "__call_stub_%s%s",
-	       fpret ? "fp_" : "",
-	       fnname);
-      stubid = get_identifier (stubname);
-      stubdecl = build_decl (FUNCTION_DECL, stubid,
-			     build_function_type (void_type_node, NULL_TREE));
-      DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
-
-      fprintf (asm_out_file, "\t# Stub function to call %s%s (",
-	       (fpret
-		? (GET_MODE (retval) == SFmode ? "float " : "double ")
-		: ""),
-	       fnname);
-      need_comma = 0;
-      for (f = (unsigned int) fp_code; f != 0; f >>= 2)
-	{
-	  fprintf (asm_out_file, "%s%s",
-		   need_comma ? ", " : "",
-		   (f & 3) == 1 ? "float" : "double");
-	  need_comma = 1;
-	}
-      fprintf (asm_out_file, ")\n");
-
-      fprintf (asm_out_file, "\t.set\tnomips16\n");
-      assemble_start_function (stubdecl, stubname);
-
-#ifndef FUNCTION_NAME_ALREADY_DECLARED
-      fputs ("\t.ent\t", asm_out_file);
-      assemble_name (asm_out_file, stubname);
-      fputs ("\n", asm_out_file);
-
-      assemble_name (asm_out_file, stubname);
-      fputs (":\n", asm_out_file);
-#endif
-
-      /* We build the stub code by hand.  That's the only way we can
-	 do it, since we can't generate 32 bit code during a 16 bit
-	 compilation. */
-
-      /* We don't want the assembler to insert any nops here.  */
-      fprintf (asm_out_file, "\t.set\tnoreorder\n");
-
-      mips16_fp_args (asm_out_file, fp_code, 0);
-
-      if (! fpret)
-	{
-	  fprintf (asm_out_file, "\t.set\tnoat\n");
-	  fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
-		   fnname);
-	  fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
-	  fprintf (asm_out_file, "\t.set\tat\n");
-	  /* Unfortunately, we can't fill the jump delay slot.  We
-	     can't fill with one of the mtc1 instructions, because the
-	     result is not available for one instruction, so if the
-	     very first instruction in the function refers to the
-	     register, it will see the wrong value.  */
-	  fprintf (asm_out_file, "\tnop\n");
-	}
-      else
-	{
-	  fprintf (asm_out_file, "\tmove\t%s,%s\n",
-		   reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
-	  fprintf (asm_out_file, "\tjal\t%s\n", fnname);
-	  /* As above, we can't fill the delay slot.  */
-	  fprintf (asm_out_file, "\tnop\n");
-	  if (GET_MODE (retval) == SFmode)
-	    fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
-		     reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
-	  else
-	    {
-	      if (TARGET_BIG_ENDIAN)
-		{
-		  fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
-			   reg_names[GP_REG_FIRST + 2],
-			   reg_names[FP_REG_FIRST + 1]);
-		  fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
-			   reg_names[GP_REG_FIRST + 3],
-			   reg_names[FP_REG_FIRST + 0]);
-		}
-	      else
-		{
-		  fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
-			   reg_names[GP_REG_FIRST + 2],
-			   reg_names[FP_REG_FIRST + 0]);
-		  fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
-			   reg_names[GP_REG_FIRST + 3],
-			   reg_names[FP_REG_FIRST + 1]);
-		}
-	    }
-	  fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
-	  /* As above, we can't fill the delay slot.  */
-	  fprintf (asm_out_file, "\tnop\n");
-	}
-
-      fprintf (asm_out_file, "\t.set\treorder\n");
-
-#ifdef ASM_DECLARE_FUNCTION_SIZE
-      ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
-#endif
-
-#ifndef FUNCTION_NAME_ALREADY_DECLARED
-      fputs ("\t.end\t", asm_out_file);
-      assemble_name (asm_out_file, stubname);
-      fputs ("\n", asm_out_file);
-#endif
-
-      fprintf (asm_out_file, "\t.set\tmips16\n");
-
-      /* Record this stub.  */
-      l = (struct mips16_stub *) xmalloc (sizeof *l);
-      l->name = (char *) xmalloc (strlen (fnname) + 1);
-      strcpy (l->name, fnname);
-      l->fpret = fpret;
-      l->next = mips16_stubs;
-      mips16_stubs = l;
-    }
-
-  /* If we expect a floating point return value, but we've built a
-     stub which does not expect one, then we're in trouble.  We can't
-     use the existing stub, because it won't handle the floating point
-     value.  We can't build a new stub, because the linker won't know
-     which stub to use for the various calls in this object file.
-     Fortunately, this case is illegal, since it means that a function
-     was declared in two different ways in a single compilation.  */
-  if (fpret && ! l->fpret)
-    error ("can not handle inconsistent calls to `%s'", fnname);
-
-  /* If we are calling a stub which handles a floating point return
-     value, we need to arrange to save $18 in the prologue.  We do
-     this by marking the function call as using the register.  The
-     prologue will later see that it is used, and emit code to save
-     it.  */
-
-  if (l->fpret)
-    {
-      rtx insn;
-
-      if (retval == NULL_RTX)
-	insn = gen_call_internal0 (fnmem, arg_size,
-				   gen_rtx (REG, SImode,
-					    GP_REG_FIRST + 31));
-      else
-	insn = gen_call_value_internal0 (retval, fnmem, arg_size,
-					 gen_rtx (REG, SImode,
-						  GP_REG_FIRST + 31));
-      insn = emit_call_insn (insn);
-
-      if (GET_CODE (insn) != CALL_INSN)
-	abort ();
-
-      CALL_INSN_FUNCTION_USAGE (insn) =
-	gen_rtx (EXPR_LIST, VOIDmode,
-		 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
-		 CALL_INSN_FUNCTION_USAGE (insn));
-
-      /* Return 1 to tell the caller that we've generated the call
-         insn.  */
-      return 1;
-    }
-
-  /* Return 0 to let the caller generate the call insn.  */
-  return 0;
-}
-
-/* This function looks through the code for a function, and tries to
-   optimize the usage of the $gp register.  We arrange to copy $gp
-   into a pseudo-register, and then let gcc's normal reload handling
-   deal with the pseudo-register.  Unfortunately, if reload choose to
-   put the pseudo-register into a call-clobbered register, it will
-   emit saves and restores for that register around any function
-   calls.  We don't need the saves, and it's faster to copy $gp than
-   to do an actual restore.  ??? This still means that we waste a
-   stack slot.
-
-   This is an optimization, and the code which gcc has actually
-   generated is correct, so we do not need to catch all cases.  */
-
-static void
-mips16_optimize_gp (first)
-     rtx first;
-{
-  rtx gpcopy, slot, insn;
-
-  /* Look through the instructions.  Set GPCOPY to the register which
-     holds a copy of $gp.  Set SLOT to the stack slot where it is
-     saved.  If we find an instruction which sets GPCOPY to anything
-     other than $gp or SLOT, then we can't use it.  If we find an
-     instruction which sets SLOT to anything other than GPCOPY, we
-     can't use it.  */
-
-  gpcopy = NULL_RTX;
-  slot = NULL_RTX;
-  for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
-    {
-      rtx set;
-
-      if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
-	continue;
-
-      set = PATTERN (insn);
-
-      /* We know that all references to memory will be inside a SET,
-         because there is no other way to access memory on the mips16.
-         We don't have to worry about a PARALLEL here, because the
-         mips.md file will never generate them for memory references.  */
-      if (GET_CODE (set) != SET)
-	continue;
-
-      if (gpcopy == NULL_RTX
-	  && GET_CODE (SET_SRC (set)) == CONST
-	  && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
-	  && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
-	  && GET_CODE (SET_DEST (set)) == REG
-	  && GET_MODE (SET_DEST (set)) == Pmode)
-	gpcopy = SET_DEST (set);
-      else if (slot == NULL_RTX
-	       && gpcopy != NULL_RTX
-	       && GET_CODE (SET_DEST (set)) == MEM
-	       && GET_CODE (SET_SRC (set)) == REG
-	       && REGNO (SET_SRC (set)) == REGNO (gpcopy)
-	       && GET_MODE (SET_DEST (set)) == Pmode)
-	{
-	  rtx base, offset;
-
-	  offset = const0_rtx;
-	  base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
-	  if (GET_CODE (base) == REG
-	      && (REGNO (base) == STACK_POINTER_REGNUM
-		  || REGNO (base) == FRAME_POINTER_REGNUM))
-	    slot = SET_DEST (set);
-	}
-      else if (gpcopy != NULL_RTX
-	       && (GET_CODE (SET_DEST (set)) == REG
-		   || GET_CODE (SET_DEST (set)) == SUBREG)
-	       && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
-	       && (GET_CODE (SET_DEST (set)) != REG
-		   || REGNO (SET_DEST (set)) != REGNO (gpcopy)
-		   || GET_MODE (SET_DEST (set)) != Pmode
-		   || ((GET_CODE (SET_SRC (set)) != CONST
-			|| GET_CODE (XEXP (SET_SRC (set), 0)) != REG
-			|| (REGNO (XEXP (SET_SRC (set), 0))
-			    != GP_REG_FIRST + 28))
-		       && ! rtx_equal_p (SET_SRC (set), slot))))
-	break;
-      else if (slot != NULL_RTX
-	       && GET_CODE (SET_DEST (set)) == MEM
-	       && rtx_equal_p (SET_DEST (set), slot)
-	       && (GET_CODE (SET_SRC (set)) != REG
-		   || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
-	break;
-    }
-
-  /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
-     different optimization.  Any time we find a copy of $28 into a
-     register, followed by an add of a symbol_ref to that register, we
-     convert it to load the value from the constant table instead.
-     The copy and add will take six bytes, just as the load and
-     constant table entry will take six bytes.  However, it is
-     possible that the constant table entry will be shared.
-
-     This could be a peephole optimization, but I don't know if the
-     peephole code can call force_const_mem.
-
-     Using the same register for the copy of $28 and the add of the
-     symbol_ref is actually pretty likely, since the add instruction
-     requires the destination and the first addend to be the same
-     register.  */
-
-  if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
-    {
-      rtx next;
-
-      /* This optimization is only reasonable if the constant table
-         entries are only 4 bytes.  */
-      if (Pmode != SImode)
-	return;
-
-      for (insn = first; insn != NULL_RTX; insn = next)
-	{
-	  rtx set1, set2;
-
-	  next = insn;
-	  do
-	    {
-	      next = NEXT_INSN (next);
-	    }
-	  while (next != NULL_RTX
-		 && (GET_CODE (next) == NOTE
-		     || (GET_CODE (next) == INSN
-			 && (GET_CODE (PATTERN (next)) == USE
-			     || GET_CODE (PATTERN (next)) == CLOBBER))));
-
-	  if (next == NULL_RTX)
-	    break;
-
-	  if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
-	    continue;
-
-	  if (GET_RTX_CLASS (GET_CODE (next)) != 'i')
-	    continue;
-
-	  set1 = PATTERN (insn);
-	  if (GET_CODE (set1) != SET)
-	    continue;
-	  set2 = PATTERN (next);
-	  if (GET_CODE (set2) != SET)
-	    continue;
-
-	  if (GET_CODE (SET_DEST (set1)) == REG
-	      && GET_CODE (SET_SRC (set1)) == CONST
-	      && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
-	      && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
-	      && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
-	      && GET_CODE (SET_SRC (set2)) == PLUS
-	      && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
-	      && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
-	      && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
-	    {
-	      rtx sym;
-
-	      /* We've found a case we can change to load from the
-                 constant table.  */
-
-	      sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
-	      if (GET_CODE (sym) != SYMBOL_REF)
-		abort ();
-	      emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
-					force_const_mem (Pmode, sym)),
-			       next);
-	      
-	      PUT_CODE (insn, NOTE);
-	      NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
-	      NOTE_SOURCE_FILE (insn) = 0;
-
-	      PUT_CODE (next, NOTE);
-	      NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
-	      NOTE_SOURCE_FILE (next) = 0;
-	    }
-	}
-
-      return;
-    }
-
-  /* We can safely remove all assignments to SLOT from GPCOPY, and
-     replace all assignments from SLOT to GPCOPY with assignments from
-     $28.  */
-
-  for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
-    {
-      rtx set;
-
-      if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
-	continue;
-
-      set = PATTERN (insn);
-      if (GET_CODE (set) != SET
-	  || GET_MODE (SET_DEST (set)) != Pmode)
-	continue;
-
-      if (GET_CODE (SET_DEST (set)) == MEM
-	  && rtx_equal_p (SET_DEST (set), slot)
-	  && GET_CODE (SET_SRC (set)) == REG
-	  && REGNO (SET_SRC (set)) == REGNO (gpcopy))
-	{
-	  PUT_CODE (insn, NOTE);
-	  NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
-	  NOTE_SOURCE_FILE (insn) = 0;
-	}
-      else if (GET_CODE (SET_DEST (set)) == REG
-	       && REGNO (SET_DEST (set)) == REGNO (gpcopy)
-	       && GET_CODE (SET_SRC (set)) == MEM
-	       && rtx_equal_p (SET_SRC (set), slot))
-	{
-	  emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
-				    gen_rtx (CONST, Pmode,
-					     gen_rtx (REG, Pmode,
-						      GP_REG_FIRST + 28))),
-			   insn);
-	  PUT_CODE (insn, NOTE);
-	  NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
-	  NOTE_SOURCE_FILE (insn) = 0;
-	}
-    }
-}
-
-/* We keep a list of constants we which we have to add to internal
-   constant tables in the middle of large functions.  */
-
-struct constant
-{
-  struct constant *next;
-  rtx value;
-  rtx label;
-  enum machine_mode mode;
-};
-
-/* Add a constant to the list in *PCONSTANTS.  */
-
-static rtx
-add_constant (pconstants, val, mode)
-     struct constant **pconstants;
-     rtx val;
-     enum machine_mode mode;
-{
-  struct constant *c;
-
-  for (c = *pconstants; c != NULL; c = c->next)
-    if (mode == c->mode && rtx_equal_p (val, c->value))
-      return c->label;
-
-  c = (struct constant *) xmalloc (sizeof *c);
-  c->value = val;
-  c->mode = mode;
-  c->label = gen_label_rtx ();
-  c->next = *pconstants;
-  *pconstants = c;
-  return c->label;
-}
-
-/* Dump out the constants in CONSTANTS after INSN.  */
-
-static void
-dump_constants (constants, insn)
-     struct constant *constants;
-     rtx insn;
-{
-  struct constant *c;
-  int align;
-
-  c = constants;
-  align = 0;
-  while (c != NULL)
-    {
-      rtx r;
-      struct constant *next;
-
-      switch (GET_MODE_SIZE (c->mode))
-	{
-	case 1:
-	  align = 0;
-	  break;
-	case 2:
-	  if (align < 1)
-	    insn = emit_insn_after (gen_align_2 (), insn);
-	  align = 1;
-	  break;
-	case 4:
-	  if (align < 2)
-	    insn = emit_insn_after (gen_align_4 (), insn);
-	  align = 2;
-	  break;
-	default:
-	  if (align < 3)
-	    insn = emit_insn_after (gen_align_8 (), insn);
-	  align = 3;
-	  break;
-	}
-
-      insn = emit_label_after (c->label, insn);
-
-      switch (c->mode)
-	{
-	case QImode:
-	  r = gen_consttable_qi (c->value);
-	  break;
-	case HImode:
-	  r = gen_consttable_hi (c->value);
-	  break;
-	case SImode:
-	  r = gen_consttable_si (c->value);
-	  break;
-	case SFmode:
-	  r = gen_consttable_sf (c->value);
-	  break;
-	case DImode:
-	  r = gen_consttable_di (c->value);
-	  break;
-	case DFmode:
-	  r = gen_consttable_df (c->value);
-	  break;
-	default:
-	  abort ();
-	}
-
-      insn = emit_insn_after (r, insn);
-
-      next = c->next;
-      free (c);
-      c = next;
-    }
-
-  emit_barrier_after (insn);
-}
-
-/* Find the symbol in an address expression.  */
-
-static rtx
-mips_find_symbol (addr)
-     rtx addr;
-{
-  if (GET_CODE (addr) == MEM)
-    addr = XEXP (addr, 0);
-  while (GET_CODE (addr) == CONST)
-    addr = XEXP (addr, 0);
-  if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
-    return addr;
-  if (GET_CODE (addr) == PLUS)
-    {
-      rtx l1, l2;
-
-      l1 = mips_find_symbol (XEXP (addr, 0));
-      l2 = mips_find_symbol (XEXP (addr, 1));
-      if (l1 != NULL_RTX && l2 == NULL_RTX)
-	return l1;
-      else if (l1 == NULL_RTX && l2 != NULL_RTX)
-	return l2;
-    }
-  return NULL_RTX;
-}
-
-/* Exported to toplev.c.
-
-   Do a final pass over the function, just before delayed branch
-   scheduling.  */
-
-void
-machine_dependent_reorg (first)
-     rtx first;
-{
-  int insns_len, max_internal_pool_size, pool_size, addr;
-  rtx insn;
-  struct constant *constants;
-
-  if (! TARGET_MIPS16)
-    return;
-
-  /* If $gp is used, try to remove stores, and replace loads with
-     copies from $gp.  */
-  if (optimize)
-    mips16_optimize_gp (first);
-
-  /* Scan the function looking for PC relative loads which may be out
-     of range.  All such loads will either be from the constant table,
-     or be getting the address of a constant string.  If the size of
-     the function plus the size of the constant table is less than
-     0x8000, then all loads are in range.  */
-
-  insns_len = 0;
-  for (insn = first; insn; insn = NEXT_INSN (insn))
-    {
-      insns_len += get_attr_length (insn) * 2;
-
-      /* ??? We put switch tables in .text, but we don't define
-         JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
-         compute their lengths correctly.  */
-      if (GET_CODE (insn) == JUMP_INSN)
-	{
-	  rtx body;
-
-	  body = PATTERN (insn);
-	  if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
-	    insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
-			  * GET_MODE_SIZE (GET_MODE (body)));
-	  insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
-	}
-    }
-
-  /* Store the original value of insns_len in current_frame_info, so
-     that simple_memory_operand can look at it.  */
-  current_frame_info.insns_len = insns_len;
-
-  pool_size = get_pool_size ();
-  if (insns_len + pool_size + mips_string_length < 0x8000)
-    return;
-
-  /* Loop over the insns and figure out what the maximum internal pool
-     size could be.  */
-  max_internal_pool_size = 0;
-  for (insn = first; insn; insn = NEXT_INSN (insn))
-    {
-      if (GET_CODE (insn) == INSN
-	  && GET_CODE (PATTERN (insn)) == SET)
-	{
-	  rtx src;
-
-	  src = mips_find_symbol (SET_SRC (PATTERN (insn)));
-	  if (src == NULL_RTX)
-	    continue;
-	  if (CONSTANT_POOL_ADDRESS_P (src))
-	    max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
-	  else if (SYMBOL_REF_FLAG (src))
-	    max_internal_pool_size += GET_MODE_SIZE (Pmode);
-	}
-    }
-
-  constants = NULL;
-  addr = 0;
-
-  for (insn = first; insn; insn = NEXT_INSN (insn))
-    {
-      if (GET_CODE (insn) == INSN
-	  && GET_CODE (PATTERN (insn)) == SET)
-	{
-	  rtx val, src;
-	  enum machine_mode mode;
-
-	  val = NULL_RTX;
-	  src = mips_find_symbol (SET_SRC (PATTERN (insn)));
-	  if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
-	    {
-	      /* ??? This is very conservative, which means that we
-                 will generate too many copies of the constant table.
-                 The only solution would seem to be some form of
-                 relaxing.  */
-	      if (((insns_len - addr)
-		   + max_internal_pool_size
-		   + get_pool_offset (src))
-		  >= 0x8000)
-		{
-		  val = get_pool_constant (src);
-		  mode = get_pool_mode (src);
-		}
-	      max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
-	    }
-	  else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
-	    {
-	      /* Including all of mips_string_length is conservative,
-                 and so is including all of max_internal_pool_size.  */
-	      if (((insns_len - addr)
-		   + max_internal_pool_size
-		   + pool_size
-		   + mips_string_length)
-		  >= 0x8000)
-	      val = src;
-	      mode = Pmode;
-	      max_internal_pool_size -= Pmode;
-	    }
-
-	  if (val != NULL_RTX)
-	    {
-	      rtx lab, newsrc;
-
-	      /* This PC relative load is out of range.  ??? In the
-		 case of a string constant, we are only guessing that
-		 it is range, since we don't know the offset of a
-		 particular string constant.  */
-
-	      lab = add_constant (&constants, val, mode);
-	      newsrc = gen_rtx (MEM, mode,
-				gen_rtx (LABEL_REF, VOIDmode, lab));
-	      RTX_UNCHANGING_P (newsrc) = 1;
-	      PATTERN (insn) = gen_rtx (SET, VOIDmode,
-					SET_DEST (PATTERN (insn)),
-					newsrc);
-	      INSN_CODE (insn) = -1;
-	    }
-	}
-
-      addr += get_attr_length (insn) * 2;
-
-      /* ??? We put switch tables in .text, but we don't define
-         JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
-         compute their lengths correctly.  */
-      if (GET_CODE (insn) == JUMP_INSN)
-	{
-	  rtx body;
-
-	  body = PATTERN (insn);
-	  if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
-	    addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
-			  * GET_MODE_SIZE (GET_MODE (body)));
-	  addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
-	}
-
-      if (GET_CODE (insn) == BARRIER)
-	{
-	  /* Output any constants we have accumulated.  Note that we
-             don't need to change ADDR, since its only use is
-             subtraction from INSNS_LEN, and both would be changed by
-             the same amount.
-	     ??? If the instructions up to the next barrier reuse a
-	     constant, it would often be better to continue
-	     accumulating.  */
-	  if (constants != NULL)
-	    dump_constants (constants, insn);
-	  constants = NULL;
-	}
-
-      /* ??? If we don't find a barrier within 0x8000 bytes of
-         instructions and constants in CONSTANTS, we need to invent
-         one.  This seems sufficiently unlikely that I am not going to
-         worry about it.  */
-    }
-
-  if (constants != NULL)
-    {
-      rtx label, jump, barrier;
-
-      label = gen_label_rtx ();
-      jump = emit_jump_insn_after (gen_jump (label), get_last_insn ());
-      JUMP_LABEL (jump) = label;
-      LABEL_NUSES (label) = 1;
-      barrier = emit_barrier_after (jump);
-      emit_label_after (label, barrier);
-      dump_constants (constants, barrier);
-      constants = NULL;
-    }
-
-  /* ??? If we output all references to a constant in internal
-     constants table, we don't need to output the constant in the real
-     constant table, but we have no way to prevent that.  */
-}
-
-/* Return nonzero if X is a SIGN or ZERO extend operator.  */
-int
-extend_operator (x, mode)
-     rtx x;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  enum rtx_code code = GET_CODE (x);
-  return code == SIGN_EXTEND || code == ZERO_EXTEND;
-}
-
-/* Accept any operator that can be used to shift the high half of the
-   input value to the lower half, suitable for truncation.  The
-   remainder (the lower half of the input, and the upper half of the
-   output) will be discarded.  */
-int
-highpart_shift_operator (x, mode)
-     rtx x;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  enum rtx_code code = GET_CODE (x);
-  return (code == LSHIFTRT
-	  || code == ASHIFTRT
-	  || code == ROTATERT
-	  || code == ROTATE);
-}
-
-
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
deleted file mode 100755
index df6e28d..0000000
--- a/gcc/config/mips/mips.h
+++ /dev/null
@@ -1,4760 +0,0 @@
-/* Definitions of target machine for GNU compiler.  MIPS version.
-   Copyright (C) 1989, 90-97, 1998 Free Software Foundation, Inc.
-   Contributed by A. Lichnewsky (lich@inria.inria.fr).
-   Changed by Michael Meissner	(meissner@osf.org).
-   64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
-   Brendan Eich (brendan@microunity.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Standard GCC variables that we reference.  */
-
-extern char    *asm_file_name;
-extern char	call_used_regs[];
-extern int	current_function_calls_alloca;
-extern char    *language_string;
-extern int	may_call_alloca;
-extern char   **save_argv;
-extern int	target_flags;
-extern char    *version_string;
-
-/* MIPS external variables defined in mips.c.  */
-
-/* comparison type */
-enum cmp_type {
-  CMP_SI,				/* compare four byte integers */
-  CMP_DI,				/* compare eight byte integers */
-  CMP_SF,				/* compare single precision floats */
-  CMP_DF,				/* compare double precision floats */
-  CMP_MAX				/* max comparison type */
-};
-
-/* types of delay slot */
-enum delay_type {
-  DELAY_NONE,				/* no delay slot */
-  DELAY_LOAD,				/* load from memory delay */
-  DELAY_HILO,				/* move from/to hi/lo registers */
-  DELAY_FCMP				/* delay after doing c.<xx>.{d,s} */
-};
-
-/* Which processor to schedule for.  Since there is no difference between
-   a R2000 and R3000 in terms of the scheduler, we collapse them into
-   just an R3000.  The elements of the enumeration must match exactly
-   the cpu attribute in the mips.md machine description.  */
-
-enum processor_type {
-  PROCESSOR_DEFAULT,
-  PROCESSOR_R3000,
-  PROCESSOR_R3900,
-  PROCESSOR_R6000,
-  PROCESSOR_R4000,
-  PROCESSOR_R4100,
-  PROCESSOR_R4300,
-  PROCESSOR_R4600,
-  PROCESSOR_R4650,
-  PROCESSOR_R5000,
-  PROCESSOR_R5400,		/* CYGNUS LOCAL vr5400/raeburn */
-  PROCESSOR_R8000
-};
-
-/* Recast the cpu class to be the cpu attribute.  */
-#define mips_cpu_attr ((enum attr_cpu)mips_cpu)
-
-/* Which ABI to use.  These are constants because abi64.h must check their
-   value at preprocessing time.
-
-   ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
-   defined by SGI.  ABI_O64 is o32 extended to work on a 64 bit machine. */
-
-#define ABI_32  0
-#define ABI_N32 1
-#define ABI_64  2
-#define ABI_EABI 3
-#define ABI_O64  4
-
-#ifndef MIPS_ABI_DEFAULT
-/* We define this away so that there is no extra runtime cost if the target
-   doesn't support multiple ABIs.  */
-#define mips_abi ABI_32
-#else
-extern int mips_abi;
-#endif
-
-/* Whether to emit abicalls code sequences or not.  */
-
-enum mips_abicalls_type {
-  MIPS_ABICALLS_NO,
-  MIPS_ABICALLS_YES
-};
-
-/* Recast the abicalls class to be the abicalls attribute.  */
-#define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
-
-/* Which type of block move to do (whether or not the last store is
-   split out so it can fill a branch delay slot).  */
-
-enum block_move_type {
-  BLOCK_MOVE_NORMAL,			/* generate complete block move */
-  BLOCK_MOVE_NOT_LAST,			/* generate all but last store */
-  BLOCK_MOVE_LAST			/* generate just the last store */
-};
-
-extern char mips_reg_names[][8];	/* register names (a0 vs. $4). */
-extern char mips_print_operand_punct[];	/* print_operand punctuation chars */
-extern char *current_function_file;	/* filename current function is in */
-extern int num_source_filenames;	/* current .file # */
-extern int inside_function;		/* != 0 if inside of a function */
-extern int ignore_line_number;		/* != 0 if we are to ignore next .loc */
-extern int file_in_function_warning;	/* warning given about .file in func */
-extern int sdb_label_count;		/* block start/end next label # */
-extern int sdb_begin_function_line;     /* Starting Line of current function */
-extern int mips_section_threshold;	/* # bytes of data/sdata cutoff */
-extern int g_switch_value;		/* value of the -G xx switch */
-extern int g_switch_set;		/* whether -G xx was passed.  */
-extern int sym_lineno;			/* sgi next label # for each stmt */
-extern int set_noreorder;		/* # of nested .set noreorder's  */
-extern int set_nomacro;			/* # of nested .set nomacro's  */
-extern int set_noat;			/* # of nested .set noat's  */
-extern int set_volatile;		/* # of nested .set volatile's  */
-extern int mips_branch_likely;		/* emit 'l' after br (branch likely) */
-extern int mips_dbx_regno[];		/* Map register # to debug register # */
-extern struct rtx_def *branch_cmp[2];	/* operands for compare */
-extern enum cmp_type branch_type;	/* what type of branch to use */
-extern enum processor_type mips_cpu;	/* which cpu are we scheduling for */
-extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
-extern int mips_isa;			/* architectural level */
-extern int mips16;			/* whether generating mips16 code */
-extern int mips16_hard_float;		/* mips16 without -msoft-float */
-extern int mips_entry;			/* generate entry/exit for mips16 */
-extern char *mips_cpu_string;		/* for -mcpu=<xxx> */
-extern char *mips_isa_string;		/* for -mips{1,2,3,4} */
-extern char *mips_abi_string;		/* for -mabi={32,n32,64} */
-extern char *mips_entry_string;		/* for -mentry */
-extern char *mips_no_mips16_string;	/* for -mno-mips16 */
-extern int mips_split_addresses;	/* perform high/lo_sum support */
-extern int dslots_load_total;		/* total # load related delay slots */
-extern int dslots_load_filled;		/* # filled load delay slots */
-extern int dslots_jump_total;		/* total # jump related delay slots */
-extern int dslots_jump_filled;		/* # filled jump delay slots */
-extern int dslots_number_nops;		/* # of nops needed by previous insn */
-extern int num_refs[3];			/* # 1/2/3 word references */
-extern struct rtx_def *mips_load_reg;	/* register to check for load delay */
-extern struct rtx_def *mips_load_reg2;	/* 2nd reg to check for load delay */
-extern struct rtx_def *mips_load_reg3;	/* 3rd reg to check for load delay */
-extern struct rtx_def *mips_load_reg4;	/* 4th reg to check for load delay */
-extern struct rtx_def *embedded_pic_fnaddr_rtx;	/* function address */
-extern int mips_string_length;		/* length of strings for mips16 */
-extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
-
-/* Functions within mips.c that we reference.  Some of these return  type
-   HOST_WIDE_INT, so define that here.  This is a copy of code in machmode.h.
-
-   ??? It would be good to try to put this as common code someplace.  */
-
-#ifndef HOST_BITS_PER_WIDE_INT
-
-#if HOST_BITS_PER_LONG > HOST_BITS_PER_INT
-#define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONG
-#define HOST_WIDE_INT long
-#else
-#define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_INT
-#define HOST_WIDE_INT int
-#endif
-
-#endif
-
-extern void		abort_with_insn ();
-extern int		arith32_operand ();
-extern int		arith_operand ();
-extern int		cmp_op ();
-extern HOST_WIDE_INT	compute_frame_size ();
-extern int		const_float_1_operand ();
-extern void		expand_block_move ();
-extern int		equality_op ();
-extern void		final_prescan_insn ();
-extern struct rtx_def *	function_arg ();
-extern void		function_arg_advance ();
-extern int		function_arg_partial_nregs ();
-extern int		function_arg_pass_by_reference ();
-extern void		function_epilogue ();
-extern void		function_prologue ();
-extern void		gen_conditional_branch ();
-extern void		gen_conditional_move ();
-extern struct rtx_def * gen_int_relational ();
-extern void		init_cumulative_args ();
-extern int		large_int ();
-extern void		machine_dependent_reorg ();
-extern int		mips_address_cost ();
-extern void		mips_asm_file_end ();
-extern void		mips_asm_file_start ();
-extern int		mips_can_use_return_insn ();
-extern int		mips_const_double_ok ();
-extern void		mips_count_memory_refs ();
-extern HOST_WIDE_INT	mips_debugger_offset ();
-extern void		mips_declare_object ();
-extern int		mips_epilogue_delay_slots ();
-extern void		mips_expand_epilogue ();
-extern void		mips_expand_prologue ();
-extern int		mips_check_split ();
-extern char	       *mips_fill_delay_slot ();
-extern char	       *mips_move_1word ();
-extern char	       *mips_move_2words ();
-extern void		mips_output_double ();
-extern int		mips_output_external ();
-extern void		mips_output_float ();
-extern void		mips_output_filename ();
-extern void		mips_output_lineno ();
-extern char	       *output_block_move ();
-extern void		override_options ();
-extern int		pc_or_label_operand ();
-extern void		print_operand_address ();
-extern void		print_operand ();
-extern void		print_options ();
-extern int		reg_or_0_operand ();
-extern int		true_reg_or_0_operand ();
-extern int		simple_epilogue_p ();
-extern int		simple_memory_operand ();
-extern int		double_memory_operand ();
-extern int		small_int ();
-extern void		trace ();
-extern int		uns_arith_operand ();
-extern struct rtx_def *	embedded_pic_offset ();
-extern void		mips_order_regs_for_local_alloc ();
-extern struct rtx_def *	mips16_gp_pseudo_reg ();
-extern struct rtx_def * mips16_gp_offset ();
-extern int		mips16_gp_offset_p ();
-extern int		mips16_constant ();
-extern int		mips16_constant_after_function_p ();
-extern int		build_mips16_call_stub ();
-
-/* Recognition functions that return if a condition is true.  */
-extern int		address_operand ();
-extern int		call_insn_operand ();
-extern int		const_double_operand ();
-extern int		const_int_operand ();
-extern int		consttable_operand ();
-extern int		general_operand ();
-extern int		immediate_operand ();
-extern int		memory_address_p ();
-extern int		memory_operand ();
-extern int		nonimmediate_operand ();
-extern int		nonmemory_operand ();
-extern int		pic_address_needs_scratch ();
-extern int		register_operand ();
-extern int		scratch_operand ();
-extern int		move_operand ();
-extern int		movdi_operand ();
-extern int		se_register_operand ();
-extern int		se_reg_or_0_operand ();
-extern int		se_uns_arith_operand ();
-extern int		se_arith_operand ();
-extern int		se_nonmemory_operand ();
-extern int		se_nonimmediate_operand ();
-extern int              extend_operator ();
-extern int              highpart_shift_operator ();
-extern int		m16_uimm3_b ();
-extern int		m16_simm4_1 ();
-extern int		m16_nsimm4_1 ();
-extern int		m16_simm5_1 ();
-extern int		m16_nsimm5_1 ();
-extern int		m16_uimm5_4 ();
-extern int		m16_nuimm5_4 ();
-extern int		m16_simm8_1 ();
-extern int		m16_nsimm8_1 ();
-extern int		m16_uimm8_1 ();
-extern int		m16_nuimm8_1 ();
-extern int		m16_uimm8_m1_1 ();
-extern int		m16_uimm8_4 ();
-extern int		m16_nuimm8_4 ();
-extern int		m16_simm8_8 ();
-extern int		m16_nsimm8_8 ();
-extern int		m16_usym8_4 ();
-extern int		m16_usym5_4 ();
-
-/* Functions to change what output section we are using.  */
-extern void		data_section ();
-extern void		rdata_section ();
-extern void		readonly_data_section ();
-extern void		sdata_section ();
-extern void		text_section ();
-extern void		mips_select_rtx_section ();
-extern void		mips_select_section ();
-
-/* Stubs for half-pic support if not OSF/1 reference platform.  */
-
-#ifndef HALF_PIC_P
-#define HALF_PIC_P() 0
-#define HALF_PIC_NUMBER_PTRS 0
-#define HALF_PIC_NUMBER_REFS 0
-#define HALF_PIC_ENCODE(DECL)
-#define HALF_PIC_DECLARE(NAME)
-#define HALF_PIC_INIT()	error ("half-pic init called on systems that don't support it.")
-#define HALF_PIC_ADDRESS_P(X) 0
-#define HALF_PIC_PTR(X) X
-#define HALF_PIC_FINISH(STREAM)
-#endif
-
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-/* Macros used in the machine description to test the flags.  */
-
-					/* Bits for real switches */
-#define MASK_INT64	0x00000001	/* ints are 64 bits */
-#define MASK_LONG64	0x00000002	/* longs and pointers are 64 bits */
-#define MASK_SPLIT_ADDR	0x00000004	/* Address splitting is enabled.  */
-#define MASK_GPOPT	0x00000008	/* Optimize for global pointer */
-#define MASK_GAS	0x00000010	/* Gas used instead of MIPS as */
-#define MASK_NAME_REGS	0x00000020	/* Use MIPS s/w reg name convention */
-#define MASK_STATS	0x00000040	/* print statistics to stderr */
-#define MASK_MEMCPY	0x00000080	/* call memcpy instead of inline code*/
-#define MASK_SOFT_FLOAT	0x00000100	/* software floating point */
-#define MASK_FLOAT64	0x00000200	/* fp registers are 64 bits */
-#define MASK_ABICALLS	0x00000400	/* emit .abicalls/.cprestore/.cpload */
-#define MASK_HALF_PIC	0x00000800	/* Emit OSF-style pic refs to externs*/
-#define MASK_LONG_CALLS	0x00001000	/* Always call through a register */
-#define MASK_64BIT	0x00002000	/* Use 64 bit GP registers and insns */
-#define MASK_EMBEDDED_PIC 0x00004000	/* Generate embedded PIC code */
-#define MASK_EMBEDDED_DATA 0x00008000	/* Reduce RAM usage, not fast code */
-#define MASK_BIG_ENDIAN	0x00010000	/* Generate big endian code */
-#define MASK_SINGLE_FLOAT 0x00020000	/* Only single precision FPU.  */
-#define MASK_MAD	0x00040000	/* Generate mad/madu as on 4650.  */
-#define MASK_4300_MUL_FIX 0x00080000    /* Work-around early Vr4300 CPU bug */
-#define MASK_MIPS3900	0x00100000	/* like -mips1 only 3900 */
-#define MASK_MIPS5400	0x00800000	/* vr5400 port */ /* CYGNUS LOCAL vr5400/raeburn */
-#define MASK_MIPS16	0x01000000	/* Generate mips16 code */
-#define MASK_NO_CHECK_ZERO_DIV 0x04000000	/* divide by zero checking */
-#define MASK_CHECK_RANGE_DIV 0x08000000	/* divide result range checking */
-
-					/* Dummy switches used only in spec's*/
-#define MASK_MIPS_TFILE	0x00000000	/* flag for mips-tfile usage */
-
-					/* Debug switches, not documented */
-#define MASK_DEBUG	0		/* Eliminate version # in .s file */
-#define MASK_DEBUG_A	0x40000000	/* don't allow <label>($reg) addrs */
-#define MASK_DEBUG_B	0x20000000	/* GO_IF_LEGITIMATE_ADDRESS debug */
-#define MASK_DEBUG_C	0x10000000	/* don't expand seq, etc. */
-#define MASK_DEBUG_D	0		/* don't do define_split's */
-#define MASK_DEBUG_E	0		/* function_arg debug */
-#define MASK_DEBUG_F	0
-#define MASK_DEBUG_G	0		/* don't support 64 bit arithmetic */
-#define MASK_DEBUG_H	0               /* allow ints in FP registers */
-#define MASK_DEBUG_I	0		/* unused */
-
-					/* r4000 64 bit sizes */
-#define TARGET_INT64		(target_flags & MASK_INT64)
-#define TARGET_LONG64		(target_flags & MASK_LONG64)
-#define TARGET_FLOAT64		(target_flags & MASK_FLOAT64)
-#define TARGET_64BIT		(target_flags & MASK_64BIT)
-
-					/* Mips vs. GNU linker */
-#define TARGET_SPLIT_ADDRESSES	(target_flags & MASK_SPLIT_ADDR)
-
-/* generate mips 3900 insns */
-#define TARGET_MIPS3900         (target_flags & MASK_MIPS3900)
-
-
-/* CYGNUS LOCAL vr5400/raeburn */
-/* Generate mips vr5400 insns.  */
-#define TARGET_MIPS5400		(target_flags & MASK_MIPS5400)
-/* END CYGNUS LOCAL vr5400/raeburn */
-
-
-
-					/* Mips vs. GNU assembler */
-#define TARGET_GAS		(target_flags & MASK_GAS)
-#define TARGET_UNIX_ASM		(!TARGET_GAS)
-#define TARGET_MIPS_AS		TARGET_UNIX_ASM
-
-					/* Debug Mode */
-#define TARGET_DEBUG_MODE	(target_flags & MASK_DEBUG)
-#define TARGET_DEBUG_A_MODE	(target_flags & MASK_DEBUG_A)
-#define TARGET_DEBUG_B_MODE	(target_flags & MASK_DEBUG_B)
-#define TARGET_DEBUG_C_MODE	(target_flags & MASK_DEBUG_C)
-#define TARGET_DEBUG_D_MODE	(target_flags & MASK_DEBUG_D)
-#define TARGET_DEBUG_E_MODE	(target_flags & MASK_DEBUG_E)
-#define TARGET_DEBUG_F_MODE	(target_flags & MASK_DEBUG_F)
-#define TARGET_DEBUG_G_MODE	(target_flags & MASK_DEBUG_G)
-#define TARGET_DEBUG_H_MODE	(target_flags & MASK_DEBUG_H)
-#define TARGET_DEBUG_I_MODE	(target_flags & MASK_DEBUG_I)
-
-					/* Reg. Naming in .s ($21 vs. $a0) */
-#define TARGET_NAME_REGS	(target_flags & MASK_NAME_REGS)
-
-					/* Optimize for Sdata/Sbss */
-#define TARGET_GP_OPT		(target_flags & MASK_GPOPT)
-
-					/* print program statistics */
-#define TARGET_STATS		(target_flags & MASK_STATS)
-
-					/* call memcpy instead of inline code */
-#define TARGET_MEMCPY		(target_flags & MASK_MEMCPY)
-
-					/* .abicalls, etc from Pyramid V.4 */
-#define TARGET_ABICALLS		(target_flags & MASK_ABICALLS)
-
-					/* OSF pic references to externs */
-#define TARGET_HALF_PIC		(target_flags & MASK_HALF_PIC)
-
-					/* software floating point */
-#define TARGET_SOFT_FLOAT	(target_flags & MASK_SOFT_FLOAT)
-#define TARGET_HARD_FLOAT	(! TARGET_SOFT_FLOAT)
-
-					/* always call through a register */
-#define TARGET_LONG_CALLS	(target_flags & MASK_LONG_CALLS)
-
-					/* generate embedded PIC code;
-					   requires gas.  */
-#define TARGET_EMBEDDED_PIC	(target_flags & MASK_EMBEDDED_PIC)
-
-					/* for embedded systems, optimize for
-					   reduced RAM space instead of for
-					   fastest code.  */
-#define TARGET_EMBEDDED_DATA	(target_flags & MASK_EMBEDDED_DATA)
-
-					/* generate big endian code.  */
-#define TARGET_BIG_ENDIAN	(target_flags & MASK_BIG_ENDIAN)
-
-#define TARGET_SINGLE_FLOAT	(target_flags & MASK_SINGLE_FLOAT)
-#define TARGET_DOUBLE_FLOAT	(! TARGET_SINGLE_FLOAT)
-
-#define TARGET_MAD		(target_flags & MASK_MAD)
-
-#define TARGET_4300_MUL_FIX     (target_flags & MASK_4300_MUL_FIX)
-
-#define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
-#define TARGET_CHECK_RANGE_DIV  (target_flags & MASK_CHECK_RANGE_DIV)
-
-/* This is true if we must enable the assembly language file switching
-   code.  */
-
-#define TARGET_FILE_SWITCHING	(TARGET_GP_OPT && ! TARGET_GAS)
-
-/* We must disable the function end stabs when doing the file switching trick,
-   because the Lscope stabs end up in the wrong place, making it impossible
-   to debug the resulting code.  */
-#define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
-
-					/* Generate mips16 code */
-#define TARGET_MIPS16		(target_flags & MASK_MIPS16)
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES							\
-{									\
-  {"int64",		  MASK_INT64 | MASK_LONG64},			\
-  {"long64",		  MASK_LONG64},					\
-  {"split-addresses",	  MASK_SPLIT_ADDR},				\
-  {"no-split-addresses", -MASK_SPLIT_ADDR},				\
-  {"mips-as",		 -MASK_GAS},					\
-  {"gas",		  MASK_GAS},					\
-  {"rnames",		  MASK_NAME_REGS},				\
-  {"no-rnames",		 -MASK_NAME_REGS},				\
-  {"gpOPT",		  MASK_GPOPT},					\
-  {"gpopt",		  MASK_GPOPT},					\
-  {"no-gpOPT",		 -MASK_GPOPT},					\
-  {"no-gpopt",		 -MASK_GPOPT},					\
-  {"stats",		  MASK_STATS},					\
-  {"no-stats",		 -MASK_STATS},					\
-  {"memcpy",		  MASK_MEMCPY},					\
-  {"no-memcpy",		 -MASK_MEMCPY},					\
-  {"mips-tfile",	  MASK_MIPS_TFILE},				\
-  {"no-mips-tfile",	 -MASK_MIPS_TFILE},				\
-  {"soft-float",	  MASK_SOFT_FLOAT},				\
-  {"hard-float",	 -MASK_SOFT_FLOAT},				\
-  {"fp64",		  MASK_FLOAT64},				\
-  {"fp32",		 -MASK_FLOAT64},				\
-  {"gp64",		  MASK_64BIT},					\
-  {"gp32",		 -MASK_64BIT},					\
-  {"abicalls",		  MASK_ABICALLS},				\
-  {"no-abicalls",	 -MASK_ABICALLS},				\
-  {"half-pic",		  MASK_HALF_PIC},				\
-  {"no-half-pic",	 -MASK_HALF_PIC},				\
-  {"long-calls",	  MASK_LONG_CALLS},				\
-  {"no-long-calls",	 -MASK_LONG_CALLS},				\
-  {"embedded-pic",	  MASK_EMBEDDED_PIC},				\
-  {"no-embedded-pic",	 -MASK_EMBEDDED_PIC},				\
-  {"embedded-data",	  MASK_EMBEDDED_DATA},				\
-  {"no-embedded-data",	 -MASK_EMBEDDED_DATA},				\
-  {"eb",		  MASK_BIG_ENDIAN},				\
-  {"el",		 -MASK_BIG_ENDIAN},				\
-  {"single-float",	  MASK_SINGLE_FLOAT},				\
-  {"double-float",	 -MASK_SINGLE_FLOAT},				\
-  {"mad",		  MASK_MAD},					\
-  {"no-mad",		 -MASK_MAD},					\
-  {"fix4300",             MASK_4300_MUL_FIX},				\
-  {"no-fix4300",         -MASK_4300_MUL_FIX},				\
-  {"4650",		  MASK_MAD | MASK_SINGLE_FLOAT},		\
-  {"3900",		  MASK_MIPS3900},                               \
-  {"5400",		  MASK_MIPS5400}, /* CYGNUS LOCAL vr5400/raeburn */ \
-  {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV},			\
-  {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV},			\
-  {"check-range-division",MASK_CHECK_RANGE_DIV},			\
-  {"no-check-range-division",-MASK_CHECK_RANGE_DIV},			\
-  {"debug",		  MASK_DEBUG},					\
-  {"debuga",		  MASK_DEBUG_A},				\
-  {"debugb",		  MASK_DEBUG_B},				\
-  {"debugc",		  MASK_DEBUG_C},				\
-  {"debugd",		  MASK_DEBUG_D},				\
-  {"debuge",		  MASK_DEBUG_E},				\
-  {"debugf",		  MASK_DEBUG_F},				\
-  {"debugg",		  MASK_DEBUG_G},				\
-  {"debugh",		  MASK_DEBUG_H},				\
-  {"debugi",		  MASK_DEBUG_I},				\
-  {"",			  (TARGET_DEFAULT				\
-			   | TARGET_CPU_DEFAULT				\
-			   | TARGET_ENDIAN_DEFAULT)}			\
-}
-
-/* Default target_flags if no switches are specified  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 0
-#endif
-
-#ifndef TARGET_CPU_DEFAULT
-#define TARGET_CPU_DEFAULT 0
-#endif
-
-#ifndef TARGET_ENDIAN_DEFAULT
-#ifndef DECSTATION
-#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
-#else
-#define TARGET_ENDIAN_DEFAULT 0
-#endif
-#endif
-
-#ifndef MULTILIB_DEFAULTS
-#if TARGET_ENDIAN_DEFAULT == 0
-#define MULTILIB_DEFAULTS { "EL", "mips1" }
-#else
-#define MULTILIB_DEFAULTS { "EB", "mips1" }
-#endif
-#endif
-
-/* We must pass -EL to the linker by default for little endian embedded
-   targets using linker scripts with a OUTPUT_FORMAT line.  Otherwise, the
-   linker will default to using big-endian output files.  The OUTPUT_FORMAT
-   line must be in the linker script, otherwise -EB/-EL will not work.  */
-
-#ifndef LINKER_ENDIAN_SPEC
-#if TARGET_ENDIAN_DEFAULT == 0
-#define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
-#else
-#define LINKER_ENDIAN_SPEC ""
-#endif
-#endif
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an
-   initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   fixed part of the option name, and the address of a variable. 
-   The variable, type `char *', is set to the variable part of the
-   given option if the fixed part matches.  The actual option name
-   is made by appending `-m' to the specified name.
-
-   Here is an example which defines `-mshort-data-NUMBER'.  If the
-   given option is `-mshort-data-512', the variable `m88k_short_data'
-   will be set to the string `"512"'.
-
-	extern char *m88k_short_data;
-	#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } }  */
-
-#define TARGET_OPTIONS							\
-{									\
-  SUBTARGET_TARGET_OPTIONS						\
-  { "cpu=",	&mips_cpu_string	},				\
-  { "ips",	&mips_isa_string	},				\
-  { "entry",	&mips_entry_string	},				\
-  /* CYGNUS LOCAL law */						\
-  { "align-loops=",	&mips_align_loops_string },			\
-  { "align-jumps=",	&mips_align_jumps_string },			\
-  { "align-functions=",	&mips_align_funcs_string },			\
-  { "max-skip-loops=",	&mips_max_skip_loops_string },			\
-  { "max-skip-jumps=",	&mips_max_skip_jumps_string },			\
-  { "max-skip-functions=",	&mips_max_skip_funcs_string },		\
-  /* END CYGNUS LOCAL */						\
-  { "no-mips16", &mips_no_mips16_string	}                               \
-}
-
-/* This is meant to be redefined in the host dependent files.  */
-#define SUBTARGET_TARGET_OPTIONS
-
-#define GENERATE_BRANCHLIKELY  (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
-
-/* Generate three-operand multiply instructions for both SImode and DImode.  */
-#define GENERATE_MULT3         ((TARGET_MIPS3900                         \
-				 )					 \
-				&& !TARGET_MIPS16)
-
-/* Macros to decide whether certain features are available or not,
-   depending on the instruction set architecture level.  */
-
-#define BRANCH_LIKELY_P()	GENERATE_BRANCHLIKELY
-#define HAVE_SQRT_P()		(mips_isa >= 2)
-
-/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
-   -mips2 sets -mfp32 and -mgp32.  This can be overridden by an explicit
-   -mfp32, -mfp64, -mgp32 or -mgp64.  -mfp64 sets MASK_FLOAT64 in
-   target_flags, and -mgp64 sets MASK_64BIT.
-
-   Setting MASK_64BIT in target_flags will cause gcc to assume that
-   registers are 64 bits wide.  int, long and void * will be 32 bit;
-   this may be changed with -mint64 or -mlong64.
-
-   The gen* programs link code that refers to MASK_64BIT.  They don't
-   actually use the information in target_flags; they just refer to
-   it.  */
-
-/* Switch  Recognition by gcc.c.  Add -G xx support */
-
-#ifdef SWITCH_TAKES_ARG
-#undef SWITCH_TAKES_ARG
-#endif
-
-#define SWITCH_TAKES_ARG(CHAR)						\
-  (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
-
-/* Sometimes certain combinations of command options do not make sense
-   on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   On the MIPS, it is used to handle -G.  We also use it to set up all
-   of the tables referenced in the other macros.  */
-
-#define OVERRIDE_OPTIONS override_options ()
-
-/* Zero or more C statements that may conditionally modify two
-   variables `fixed_regs' and `call_used_regs' (both of type `char
-   []') after they have been initialized from the two preceding
-   macros.
-
-   This is necessary in case the fixed or call-clobbered registers
-   depend on target flags.
-
-   You need not define this macro if it has no work to do.
-
-   If the usage of an entire class of registers depends on the target
-   flags, you may indicate this to GCC by using this macro to modify
-   `fixed_regs' and `call_used_regs' to 1 for each of the registers in
-   the classes which should not be used by GCC.  Also define the macro
-   `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
-   letter for a class that shouldn't be used.
-
-   (However, if this class is not included in `GENERAL_REGS' and all
-   of the insn patterns whose constraints permit this class are
-   controlled by target switches, then GCC will automatically avoid
-   using these registers when the target switches are opposed to
-   them.)  */
-
-#define CONDITIONAL_REGISTER_USAGE					\
-do									\
-  {									\
-    if (!TARGET_HARD_FLOAT)						\
-      {									\
-	int regno;							\
-									\
-	for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)	\
-	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
-	for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)	\
-	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
-      }									\
-    else if (mips_isa < 4)						\
-      {									\
-	int regno;							\
-									\
-	/* We only have a single condition code register.  We		\
-           implement this by hiding all the condition code registers,	\
-           and generating RTL that refers directly to ST_REG_FIRST.  */	\
-	for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)	\
-	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
-      }									\
-    /* In mips16 mode, we permit the $t temporary registers to be used	\
-       for reload.  We prohibit the unused $s registers, since they	\
-       are caller saved, and saving them via a mips16 register would	\
-       probably waste more time than just reloading the value.  */	\
-    if (TARGET_MIPS16)							\
-      {									\
-	fixed_regs[18] = call_used_regs[18] = 1;                        \
-	fixed_regs[19] = call_used_regs[19] = 1;                        \
-	fixed_regs[20] = call_used_regs[20] = 1;                        \
-	fixed_regs[21] = call_used_regs[21] = 1;                        \
-	fixed_regs[22] = call_used_regs[22] = 1;                        \
-	fixed_regs[23] = call_used_regs[23] = 1;                        \
-	fixed_regs[26] = call_used_regs[26] = 1;                        \
-	fixed_regs[27] = call_used_regs[27] = 1;                        \
-	fixed_regs[30] = call_used_regs[30] = 1;                        \
-      }									\
-    SUBTARGET_CONDITIONAL_REGISTER_USAGE				\
-  }									\
-while (0)
-
-/* This is meant to be redefined in the host dependent files.  */
-#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
-
-/* Show we can debug even without a frame pointer.  */
-#define CAN_DEBUG_WITHOUT_FP
-
-/* Complain about missing specs and predefines that should be defined in each
-   of the target tm files to override the defaults.  This is mostly a place-
-   holder until I can get each of the files updated [mm].  */
-
-#if defined(OSF_OS) \
-    || defined(DECSTATION) \
-    || defined(SGI_TARGET) \
-    || defined(MIPS_NEWS) \
-    || defined(MIPS_SYSV) \
-    || defined(MIPS_SVR4) \
-    || defined(MIPS_BSD43)
-
-#ifndef CPP_PREDEFINES
-	#error "Define CPP_PREDEFINES in the appropriate tm.h file"
-#endif
-
-#ifndef LIB_SPEC
-	#error "Define LIB_SPEC in the appropriate tm.h file"
-#endif
-
-#ifndef STARTFILE_SPEC
-	#error "Define STARTFILE_SPEC in the appropriate tm.h file"
-#endif
-
-#ifndef MACHINE_TYPE
-	#error "Define MACHINE_TYPE in the appropriate tm.h file"
-#endif
-#endif
-
-/* Tell collect what flags to pass to nm.  */
-#ifndef NM_FLAGS
-#define NM_FLAGS "-Bn"
-#endif
-
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#ifndef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
--Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
-#endif
-
-/* Assembler specs.  */
-
-/* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
-   than gas.  */
-
-#define MIPS_AS_ASM_SPEC "\
-%{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
-%{pipe: %e-pipe is not supported.} \
-%{K} %(subtarget_mips_as_asm_spec)"
-
-/* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
-   rather than gas.  It may be overridden by subtargets.  */
-
-#ifndef SUBTARGET_MIPS_AS_ASM_SPEC
-#define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
-#endif
-
-/* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
-   assembler.  */
-
-/* CYGNUS LOCAL law; vr5400/raeburn; abi_gas_asm_spec/gavin */
-#define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{m5400}  %{v} %(abi_gas_asm_spec)" /*  */
-/* END CYGNUS LOCAL */
-
-/* CYGNUS LOCAL abi_gas_asm_spec/gavin */
-#ifndef MIPS_ABI_DEFAULT
-#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=32}"
-
-#elif MIPS_ABI_DEFAULT == ABI_32
-#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=32}"
-
-#elif MIPS_ABI_DEFAULT == ABI_N32
-#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=n32}"
-
-#elif MIPS_ABI_DEFAULT == ABI_64
-#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=64}"
-
-#elif MIPS_ABI_DEFAULT == ABI_EABI
-#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=eabi}"
-
-#elif MIPS_ABI_DEFAULT == ABI_O64
-#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=o64}"
-
-#else
-#error "Unhandled MIPS_ABI_DEFAULT"
-#endif
-/* END CYGNUS LOCAL abi_gas_asm_spec/gavin */
-
-
-
-
-/* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
-   GAS_ASM_SPEC as the default, depending upon the value of
-   TARGET_DEFAULT.  */
-
-#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
-/* GAS */
-
-#define TARGET_ASM_SPEC "\
-%{mmips-as: %(mips_as_asm_spec)} \
-%{!mmips-as: %(gas_asm_spec)}"
-
-#else /* not GAS */
-
-#define TARGET_ASM_SPEC "\
-%{!mgas: %(mips_as_asm_spec)} \
-%{mgas: %(gas_asm_spec)}"
-
-#endif /* not GAS */
-
-/* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
-   to the assembler.  It may be overridden by subtargets.  */
-#ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
-#define SUBTARGET_ASM_OPTIMIZING_SPEC "\
-%{noasmopt:-O0} \
-%{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
-#endif
-
-/* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
-   the assembler.  It may be overridden by subtargets.  */
-#ifndef SUBTARGET_ASM_DEBUGGING_SPEC
-#define SUBTARGET_ASM_DEBUGGING_SPEC "\
-%{g} %{g0} %{g1} %{g2} %{g3} \
-%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
-%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
-%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
-%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
-#endif
-
-/* SUBTARGET_ASM_SPEC is always passed to the assembler.  It may be
-   overridden by subtargets.  */
-
-#ifndef SUBTARGET_ASM_SPEC
-#define SUBTARGET_ASM_SPEC ""
-#endif
-
-/* ASM_SPEC is the set of arguments to pass to the assembler.  */
-
-#define ASM_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
-%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
-%(subtarget_asm_optimizing_spec) \
-%(subtarget_asm_debugging_spec) \
-%{membedded-pic} \
-%{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
-%(target_asm_spec) \
-%(subtarget_asm_spec)"
-
-/* Specify to run a post-processor, mips-tfile after the assembler
-   has run to stuff the mips debug information into the object file.
-   This is needed because the $#!%^ MIPS assembler provides no way
-   of specifying such information in the assembly file.  If we are
-   cross compiling, disable mips-tfile unless the user specifies
-   -mmips-tfile.  */
-
-#ifndef ASM_FINAL_SPEC
-#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
-/* GAS */
-#define ASM_FINAL_SPEC "\
-%{mmips-as: %{!mno-mips-tfile: \
-	\n mips-tfile %{v*: -v} \
-		%{K: -I %b.o~} \
-		%{!K: %{save-temps: -I %b.o~}} \
-		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
-		%{.s:%i} %{!.s:%g.s}}}"
-
-#else
-/* not GAS */
-#define ASM_FINAL_SPEC "\
-%{!mgas: %{!mno-mips-tfile: \
-	\n mips-tfile %{v*: -v} \
-		%{K: -I %b.o~} \
-		%{!K: %{save-temps: -I %b.o~}} \
-		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
-		%{.s:%i} %{!.s:%g.s}}}"
-
-#endif
-#endif	/* ASM_FINAL_SPEC */
-
-/* Redefinition of libraries used.  Mips doesn't support normal
-   UNIX style profiling via calling _mcount.  It does offer
-   profiling that samples the PC, so do what we can... */
-
-#ifndef LIB_SPEC
-#define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
-#endif
-
-/* Extra switches sometimes passed to the linker.  */
-/* ??? The bestGnum will never be passed to the linker, because the gcc driver
-  will interpret it as a -b option.  */
-
-#ifndef LINK_SPEC
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
-%{bestGnum} %{shared} %{non_shared} \
-%(linker_endian_spec)"
-#endif	/* LINK_SPEC defined */
-
-/* Specs for the compiler proper */
-
-/* SUBTARGET_CC1_SPEC is passed to the compiler proper.  It may be
-   overridden by subtargets.  */
-#ifndef SUBTARGET_CC1_SPEC
-#define SUBTARGET_CC1_SPEC ""
-#endif
-
-/* CC1_SPEC is the set of arguments to pass to the compiler proper.  */
-
-#ifndef CC1_SPEC
-#define CC1_SPEC "\
-%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
-%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
-%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
-%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
-%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
-%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
-%{m4650:-mcpu=r4650} \
-%{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
-%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
-%{pic-none:   -mno-half-pic} \
-%{pic-lib:    -mhalf-pic} \
-%{pic-extern: -mhalf-pic} \
-%{pic-calls:  -mhalf-pic} \
-%{save-temps: } \
-%(subtarget_cc1_spec) "
-#endif
-
-/* Preprocessor specs.  */
-
-/* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE.  It may
-   be overridden by subtargets.  */
-
-#ifndef SUBTARGET_CPP_SIZE_SPEC
-#define SUBTARGET_CPP_SIZE_SPEC "\
-%{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
-%{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
-#endif
-
-/* SUBTARGET_CPP_SPEC is passed to the preprocessor.  It may be
-   overridden by subtargets.  */
-#ifndef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC ""
-#endif
-
-/* If we're using 64bit longs, then we have to define __LONG_MAX__
-   correctly.  Similarly for 64bit ints and __INT_MAX__.  */
-#ifndef LONG_MAX_SPEC
-#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
-#define LONG_MAX_SPEC "%{!mno-long64:-D__LONG_MAX__=9223372036854775807L}"
-#else
-#define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
-#endif
-#endif
-
-/* CPP_SPEC is the set of arguments to pass to the preprocessor.  */
-
-#ifndef CPP_SPEC
-#define CPP_SPEC "\
-%{.cc:	-D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
-%{.cxx:	-D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
-%{.C:	-D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
-%{.m:	-D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
-%{.S:	-D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
-%{.s:	-D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
-%{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
-%(subtarget_cpp_size_spec) \
-%{mips3:-U__mips -D__mips=3 -D__mips64} \
-%{mips4:-U__mips -D__mips=4 -D__mips64} \
-%{mgp32:-U__mips64} %{mgp64:-D__mips64} \
-%{msingle-float:%{!msoft-float:-D__mips_single_float}} \
-%{m4650:%{!msoft-float:-D__mips_single_float}} \
-%{msoft-float:-D__mips_soft_float} \
-%{mabi=eabi:-D__mips_eabi} \
-%{mips16:%{!mno-mips16:-D__mips16}} \
-%{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
-%{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
-%(long_max_spec) \
-%(subtarget_cpp_spec) "
-#endif
-
-/* This macro defines names of additional specifications to put in the specs
-   that can be used in various specifications like CC1_SPEC.  Its definition
-   is an initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   specification name, and a string constant that used by the GNU CC driver
-   program.
-
-   Do not define this macro if it does not need to do anything.  */
-
-#define EXTRA_SPECS							\
-  { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC },				\
-  { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },				\
-  { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC },		\
-  { "long_max_spec", LONG_MAX_SPEC },					\
-  { "mips_as_asm_spec", MIPS_AS_ASM_SPEC },				\
-  { "gas_asm_spec", GAS_ASM_SPEC },					\
-  { "abi_gas_asm_spec", ABI_GAS_ASM_SPEC }, /* CYGNUS LOCAL gavin */	\
-  { "target_asm_spec", TARGET_ASM_SPEC },				\
-  { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, 	\
-  { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC },	\
-  { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC },	\
-  { "subtarget_asm_spec", SUBTARGET_ASM_SPEC },				\
-  { "linker_endian_spec", LINKER_ENDIAN_SPEC },				\
-  SUBTARGET_EXTRA_SPECS
-
-#ifndef SUBTARGET_EXTRA_SPECS
-#define SUBTARGET_EXTRA_SPECS
-#endif
-
-/* If defined, this macro is an additional prefix to try after
-   `STANDARD_EXEC_PREFIX'.  */
-
-#ifndef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
-#endif
-
-#ifndef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
-#endif
-
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define MIPS_VERSION "[AL 1.1, MM 40]"
-
-#ifndef MACHINE_TYPE
-#define MACHINE_TYPE "BSD Mips"
-#endif
-
-#ifndef TARGET_VERSION_INTERNAL
-#define TARGET_VERSION_INTERNAL(STREAM)					\
-  fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
-#endif
-
-#ifndef TARGET_VERSION
-#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
-#endif
-
-
-#define SDB_DEBUGGING_INFO		/* generate info for mips-tfile */
-#define DBX_DEBUGGING_INFO		/* generate stabs (OSF/rose) */
-#define MIPS_DEBUGGING_INFO		/* MIPS specific debugging info */
-
-#ifndef PREFERRED_DEBUGGING_TYPE	/* assume SDB_DEBUGGING_INFO */
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
-#endif
-
-/* By default, turn on GDB extensions.  */
-#define DEFAULT_GDB_EXTENSIONS 1
-
-/* If we are passing smuggling stabs through the MIPS ECOFF object
-   format, put a comment in front of the .stab<x> operation so
-   that the MIPS assembler does not choke.  The mips-tfile program
-   will correctly put the stab into the object file.  */
-
-#define ASM_STABS_OP	((TARGET_GAS) ? ".stabs" : " #.stabs")
-#define ASM_STABN_OP	((TARGET_GAS) ? ".stabn" : " #.stabn")
-#define ASM_STABD_OP	((TARGET_GAS) ? ".stabd" : " #.stabd")
-
-/* Local compiler-generated symbols must have a prefix that the assembler
-   understands.   By default, this is $, although some targets (e.g.,
-   NetBSD-ELF) need to override this. */
-
-#ifndef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX	"$"
-#endif
-
-/* By default on the mips, external symbols do not have an underscore
-   prepended, but some targets (e.g., NetBSD) require this. */
-
-#ifndef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX	""
-#endif
-
-/* Forward references to tags are allowed.  */
-#define SDB_ALLOW_FORWARD_REFERENCES
-
-/* Unknown tags are also allowed.  */
-#define SDB_ALLOW_UNKNOWN_REFERENCES
-
-/* On Sun 4, this limit is 2048.  We use 1500 to be safe,
-   since the length can run past this up to a continuation point.  */
-#define DBX_CONTIN_LENGTH 1500
-
-/* How to renumber registers for dbx and gdb. */
-#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
-
-/* The mapping from gcc register number to DWARF 2 CFA column number.
-   This mapping does not allow for tracking register 0, since SGI's broken
-   dwarf reader thinks column 0 is used for the frame address, but since
-   register 0 is fixed this is not a problem.  */
-#define DWARF_FRAME_REGNUM(REG)				\
-  (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
-
-/* The DWARF 2 CFA column which tracks the return address.  */
-#define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
-
-/* Before the prologue, RA lives in r31.  */
-#define INCOMING_RETURN_ADDR_RTX  gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
-
-/* Overrides for the COFF debug format.  */
-#define PUT_SDB_SCL(a)					\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t.scl\t%d;", (a));	\
-} while (0)
-
-#define PUT_SDB_INT_VAL(a)				\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t.val\t%d;", (a));	\
-} while (0)
-
-#define PUT_SDB_VAL(a)					\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fputs ("\t.val\t", asm_out_text_file);		\
-  output_addr_const (asm_out_text_file, (a));		\
-  fputc (';', asm_out_text_file);			\
-} while (0)
-
-#define PUT_SDB_DEF(a)					\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t%s.def\t",		\
-	   (TARGET_GAS) ? "" : "#");			\
-  ASM_OUTPUT_LABELREF (asm_out_text_file, a); 		\
-  fputc (';', asm_out_text_file);			\
-} while (0)
-
-#define PUT_SDB_PLAIN_DEF(a)				\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t%s.def\t.%s;",		\
-	   (TARGET_GAS) ? "" : "#", (a));		\
-} while (0)
-
-#define PUT_SDB_ENDEF					\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t.endef\n");		\
-} while (0)
-
-#define PUT_SDB_TYPE(a)					\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t.type\t0x%x;", (a));	\
-} while (0)
-
-#define PUT_SDB_SIZE(a)					\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t.size\t%d;", (a));	\
-} while (0)
-
-#define PUT_SDB_DIM(a)					\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t.dim\t%d;", (a));	\
-} while (0)
-
-#ifndef PUT_SDB_START_DIM
-#define PUT_SDB_START_DIM				\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t.dim\t");		\
-} while (0)
-#endif
-
-#ifndef PUT_SDB_NEXT_DIM
-#define PUT_SDB_NEXT_DIM(a)				\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "%d,", a);		\
-} while (0)
-#endif
-
-#ifndef PUT_SDB_LAST_DIM
-#define PUT_SDB_LAST_DIM(a)				\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "%d;", a);		\
-} while (0)
-#endif
-
-#define PUT_SDB_TAG(a)					\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file, "\t.tag\t");		\
-  ASM_OUTPUT_LABELREF (asm_out_text_file, a); 		\
-  fputc (';', asm_out_text_file);			\
-} while (0)
-
-/* For block start and end, we create labels, so that
-   later we can figure out where the correct offset is.
-   The normal .ent/.end serve well enough for functions,
-   so those are just commented out.  */
-
-#define PUT_SDB_BLOCK_START(LINE)			\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file,				\
-	   "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n",		\
-	   LOCAL_LABEL_PREFIX,				\
-	   sdb_label_count,				\
-	   (TARGET_GAS) ? "" : "#",			\
-	   LOCAL_LABEL_PREFIX,				\
-	   sdb_label_count,				\
-	   (LINE));					\
-  sdb_label_count++;					\
-} while (0)
-
-#define PUT_SDB_BLOCK_END(LINE)				\
-do {							\
-  extern FILE *asm_out_text_file;			\
-  fprintf (asm_out_text_file,				\
-	   "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n",		\
-	   LOCAL_LABEL_PREFIX,				\
-	   sdb_label_count,				\
-	   (TARGET_GAS) ? "" : "#",			\
-	   LOCAL_LABEL_PREFIX,				\
-	   sdb_label_count,				\
-	   (LINE));					\
-  sdb_label_count++;					\
-} while (0)
-
-#define PUT_SDB_FUNCTION_START(LINE)
-
-#define PUT_SDB_FUNCTION_END(LINE)            \
-do {                                                  \
-  extern FILE *asm_out_text_file;             \
-  ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
-} while (0)
-
-#define PUT_SDB_EPILOGUE_END(NAME)
-
-#define PUT_SDB_SRC_FILE(FILENAME) \
-do {							\
-  extern FILE *asm_out_text_file;			\
-  output_file_directive (asm_out_text_file, (FILENAME)); \
-} while (0)
-
-#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
-  sprintf ((BUFFER), ".%dfake", (NUMBER));
-
-/* Correct the offset of automatic variables and arguments.  Note that
-   the MIPS debug format wants all automatic variables and arguments
-   to be in terms of the virtual frame pointer (stack pointer before
-   any adjustment in the function), while the MIPS 3.0 linker wants
-   the frame pointer to be the stack pointer after the initial
-   adjustment.  */
-
-#define DEBUGGER_AUTO_OFFSET(X)  \
-  mips_debugger_offset (X, (HOST_WIDE_INT) 0)
-#define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
-  mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
-
-/* Tell collect that the object format is ECOFF */
-#ifndef OBJECT_FORMAT_ROSE
-#define OBJECT_FORMAT_COFF	/* Object file looks like COFF */
-#define EXTENDED_COFF		/* ECOFF, not normal coff */
-#endif
-
-#if 0 /* These definitions normally have no effect because
-	 MIPS systems define USE_COLLECT2, so
-	 assemble_constructor does nothing anyway.  */
-
-/* Don't use the default definitions, because we don't have gld.
-   Also, we don't want stabs when generating ECOFF output.
-   Instead we depend on collect to handle these.  */
-
-#define ASM_OUTPUT_CONSTRUCTOR(file, name)
-#define ASM_OUTPUT_DESTRUCTOR(file, name)
-
-#endif /* 0 */
-
-/* Target machine storage layout */
-
-/* Define in order to support both big and little endian float formats
-   in the same gcc binary.  */
-#define REAL_ARITHMETIC
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-*/
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered. */
-#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
-
-/* Define this if most significant word of a multiword number is the lowest. */
-#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
-
-/* Define this to set the endianness to use in libgcc2.c, which can
-   not depend on target_flags.  */
-#if !defined(MIPSEL) && !defined(__MIPSEL__)
-#define LIBGCC2_WORDS_BIG_ENDIAN 1
-#else
-#define LIBGCC2_WORDS_BIG_ENDIAN 0
-#endif
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
-#define MAX_BITS_PER_WORD 64
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
-#define MIN_UNITS_PER_WORD 4
-
-/* For MIPS, width of a floating point register.  */
-#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
-
-/* A C expression for the size in bits of the type `int' on the
-   target machine.  If you don't define this, the default is one
-   word.  */
-#define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
-#define MAX_INT_TYPE_SIZE 64
-
-/* Tell the preprocessor the maximum size of wchar_t.  */
-#ifndef MAX_WCHAR_TYPE_SIZE
-#ifndef WCHAR_TYPE_SIZE
-#define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
-#endif
-#endif
-
-/* A C expression for the size in bits of the type `short' on the
-   target machine.  If you don't define this, the default is half a
-   word.  (If this would be less than one storage unit, it is
-   rounded up to one unit.)  */
-#define SHORT_TYPE_SIZE 16
-
-/* A C expression for the size in bits of the type `long' on the
-   target machine.  If you don't define this, the default is one
-   word.  */
-#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
-#define MAX_LONG_TYPE_SIZE 64
-
-/* A C expression for the size in bits of the type `long long' on the
-   target machine.  If you don't define this, the default is two
-   words.  */
-#define LONG_LONG_TYPE_SIZE 64
-
-/* A C expression for the size in bits of the type `char' on the
-   target machine.  If you don't define this, the default is one
-   quarter of a word.  (If this would be less than one storage unit,
-   it is rounded up to one unit.)  */
-#define CHAR_TYPE_SIZE BITS_PER_UNIT
-
-/* A C expression for the size in bits of the type `float' on the
-   target machine.  If you don't define this, the default is one
-   word.  */
-#define FLOAT_TYPE_SIZE 32
-
-/* A C expression for the size in bits of the type `double' on the
-   target machine.  If you don't define this, the default is two
-   words.  */
-#define DOUBLE_TYPE_SIZE 64
-
-/* A C expression for the size in bits of the type `long double' on
-   the target machine.  If you don't define this, the default is two
-   words.  */
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#ifndef POINTER_SIZE
-#define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
-#endif
-
-/* Allocation boundary (in *bits*) for storing pointers in memory.  */
-#define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
-
-/* CYGNUS LOCAL law */
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY (1 << (mips_align_funcs + 3))
-#define FUNCTION_BOUNDARY_MAX_SKIP (mips_max_skip_funcs)
-/* END CYGNUS LOCAL */
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-/* 8 is observed right on a DECstation and on riscos 4.02.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* There is no point aligning anything to a rounder boundary than this.  */
-#define BIGGEST_ALIGNMENT 64
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* CYGNUS LOCAL law */
-/* Align loop starts for optimal branching.  */
-#define LOOP_ALIGN(LABEL) (mips_align_loops)
-#define LOOP_ALIGN_MAX_SKIP (mips_max_skip_loops)
-
-/* This is how to align an instruction for optimal branching. */
-#define LABEL_ALIGN_AFTER_BARRIER(LABEL) (mips_align_jumps)
-#define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP (mips_max_skip_jumps)
-
-#ifndef DEFAULT_LOOP_ALIGN
-#define DEFAULT_LOOP_ALIGN 2
-#endif
-
-#ifndef DEFAULT_JUMP_ALIGN
-#define DEFAULT_JUMP_ALIGN 2
-#endif
-
-#ifndef DEFAULT_FUNCTION_ALIGN
-#define DEFAULT_FUNCTION_ALIGN 2
-#endif
-
-#ifndef DEFAULT_LOOP_MAX_SKIP
-#define DEFAULT_LOOP_MAX_SKIP 0
-#endif
-
-#ifndef DEFAULT_JUMP_MAX_SKIP
-#define DEFAULT_JUMP_MAX_SKIP 0
-#endif
-
-#ifndef DEFAULT_FUNCTION_MAX_SKIP
-#define DEFAULT_FUNCTION_MAX_SKIP 0
-#endif
-
-extern char *mips_align_loops_string;
-extern char *mips_align_jumps_string;
-extern char *mips_align_funcs_string;
-extern int mips_align_loops;
-extern int mips_align_jumps;
-extern int mips_align_funcs;
-extern char *mips_max_skip_loops_string;
-extern char *mips_max_skip_jumps_string;
-extern char *mips_max_skip_funcs_string;
-extern int mips_max_skip_loops;
-extern int mips_max_skip_jumps;
-extern int mips_max_skip_funcs;
-/* END CYGNUS LOCAL */
-
-/* Define this if you wish to imitate the way many other C compilers
-   handle alignment of bitfields and the structures that contain
-   them.
-
-   The behavior is that the type written for a bitfield (`int',
-   `short', or other integer type) imposes an alignment for the
-   entire structure, as if the structure really did contain an
-   ordinary field of that type.  In addition, the bitfield is placed
-   within the structure so that it would fit within such a field,
-   not crossing a boundary for it.
-
-   Thus, on most machines, a bitfield whose type is written as `int'
-   would not cross a four-byte boundary, and would force four-byte
-   alignment for the whole structure.  (The alignment used may not
-   be four bytes; it is controlled by the other alignment
-   parameters.)
-
-   If the macro is defined, its definition should be a C expression;
-   a nonzero value for the expression enables this behavior.  */
-
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* If defined, a C expression to compute the alignment given to a
-   constant that is being placed in memory.  CONSTANT is the constant
-   and ALIGN is the alignment that the object would ordinarily have.
-   The value of this macro is used instead of that alignment to align
-   the object.
-
-   If this macro is not defined, then ALIGN is used.
-
-   The typical use of this macro is to increase alignment for string
-   constants to be word aligned so that `strcpy' calls that copy
-   constants can be done inline.  */
-
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)					\
-  ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)	\
-   && (ALIGN) < BITS_PER_WORD						\
-	? BITS_PER_WORD							\
-	: (ALIGN))
-
-/* If defined, a C expression to compute the alignment for a static
-   variable.  TYPE is the data type, and ALIGN is the alignment that
-   the object would ordinarily have.  The value of this macro is used
-   instead of that alignment to align the object.
-
-   If this macro is not defined, then ALIGN is used.
-
-   One use of this macro is to increase alignment of medium-size
-   data to make it all fit in fewer cache lines.  Another is to
-   cause character arrays to be word-aligned so that `strcpy' calls
-   that copy constants to character arrays can be done inline.  */
-
-#undef DATA_ALIGNMENT
-#define DATA_ALIGNMENT(TYPE, ALIGN)					\
-  ((((ALIGN) < BITS_PER_WORD)						\
-    && (TREE_CODE (TYPE) == ARRAY_TYPE					\
-	|| TREE_CODE (TYPE) == UNION_TYPE				\
-	|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
-
-/* Define this macro if an argument declared as `char' or `short' in a
-   prototype should actually be passed as an `int'.  In addition to
-   avoiding errors in certain cases of mismatch, it also makes for
-   better code on certain machines. */
-
-#define PROMOTE_PROTOTYPES
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none. 
-
-   When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
-   moves.  All other referces are zero extended.  */
-#define LOAD_EXTEND_OP(MODE) \
-  (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
-   ? SIGN_EXTEND : ZERO_EXTEND)
-
-/* Define this macro if it is advisable to hold scalars in registers
-   in a wider mode than that declared by the program.  In such cases, 
-   the value is constrained to be within the bounds of the declared
-   type, but kept valid in the wider mode.  The signedness of the
-   extension may differ from that of the type.
-
-   We promote any value smaller than SImode up to SImode.  We don't
-   want to promote to DImode when in 64 bit mode, because that would
-   prevent us from using the faster SImode multiply and divide
-   instructions.  */
-
-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
-  if (GET_MODE_CLASS (MODE) == MODE_INT		\
-      && GET_MODE_SIZE (MODE) < 4)		\
-    (MODE) = SImode;
-
-/* Define this if function arguments should also be promoted using the above
-   procedure.  */
-
-#define PROMOTE_FUNCTION_ARGS
-
-/* Likewise, if the function return value is promoted.  */
-
-#define PROMOTE_FUNCTION_RETURN
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   On the Mips, we have 32 integer registers, 32 floating point
-   registers, 8 condition code registers, and the special registers
-   hi, lo, hilo, and rap.  The 8 condition code registers are only
-   used if mips_isa >= 4.  The hilo register is only used in 64 bit
-   mode.  It represents a 64 bit value stored as two 32 bit values in
-   the hi and lo registers; this is the result of the mult
-   instruction.  rap is a pointer to the stack where the return
-   address reg ($31) was stored.  This is needed for C++ exception
-   handling.  */
-
-#define FIRST_PSEUDO_REGISTER 76
-
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   On the MIPS, see conventions, page D-2  */
-
-#define FIXED_REGISTERS							\
-{									\
-  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1,			\
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
-  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1					\
-}
-
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-
-#define CALL_USED_REGISTERS						\
-{									\
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
-  0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1,			\
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
-  1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
-  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1					\
-}
-
-
-/* Internal macros to classify a register number as to whether it's a
-   general purpose register, a floating point register, a
-   multiply/divide register, or a status register.  */
-
-#define GP_REG_FIRST 0
-#define GP_REG_LAST  31
-#define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
-#define GP_DBX_FIRST 0
-
-#define FP_REG_FIRST 32
-#define FP_REG_LAST  63
-#define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
-#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
-
-#define MD_REG_FIRST 64
-#define MD_REG_LAST  66
-#define MD_REG_NUM   (MD_REG_LAST - MD_REG_FIRST + 1)
-
-
-#define ST_REG_FIRST 67
-#define ST_REG_LAST  74
-#define ST_REG_NUM   (ST_REG_LAST - ST_REG_FIRST + 1)
-
-#define RAP_REG_NUM   75
-
-#define AT_REGNUM	(GP_REG_FIRST + 1)
-#define HI_REGNUM	(MD_REG_FIRST + 0)
-#define LO_REGNUM	(MD_REG_FIRST + 1)
-#define HILO_REGNUM	(MD_REG_FIRST + 2)
-
-/* FPSW_REGNUM is the single condition code used if mips_isa < 4.  If
-   mips_isa >= 4, it should not be used, and an arbitrary ST_REG
-   should be used instead.  */
-#define FPSW_REGNUM	ST_REG_FIRST
-
-#define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
-#define M16_REG_P(REGNO) \
-  (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
-#define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
-#define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
-#define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On the MIPS, all general registers are one word long.  Except on
-   the R4000 with the FR bit set, the floating point uses register
-   pairs, with the second register not being allocable.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)					\
-  (! FP_REG_P (REGNO)							\
-	? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
-	: ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
-
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
-   MODE.  In 32 bit mode, require that DImode and DFmode be in even
-   registers.  For DImode, this makes some of the insns easier to
-   write, since you don't have to worry about a DImode value in
-   registers 3 & 4, producing a result in 4 & 5.
-
-   To make the code simpler HARD_REGNO_MODE_OK now just references an
-   array built in override_options.  Because machmodes.h is not yet
-   included before this file is processed, the MODE bound can't be
-   expressed here.  */
-
-extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE)					\
-  mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2)					\
-  ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||				\
-    GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)			\
-   == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||				\
-       GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
-
-/* MIPS pc is not overloaded on a register.	*/
-/* #define PC_REGNUM xx				*/
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
-
-/* Offset from the stack pointer to the first available location.  Use
-   the default value zero.  */
-/* #define STACK_POINTER_OFFSET 0 */
-
-/* Base register for access to local variables of the function.  We
-   pretend that the frame pointer is $1, and then eliminate it to
-   HARD_FRAME_POINTER_REGNUM.  We can get away with this because $1 is
-   a fixed register, and will not be used for anything else.  */
-#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
-
-/* $30 is not available on the mips16, so we use $17 as the frame
-   pointer.  */
-#define HARD_FRAME_POINTER_REGNUM \
-  (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM GP_REG_FIRST
-
-/* Fake register that holds the address on the stack of the
-   current function's return address.  */
-#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
-
-/* If the structure value address is passed in a register, then
-   `STRUCT_VALUE_REGNUM' should be the number of that register.  */
-/* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
-
-/* If the structure value address is not passed in a register, define
-   `STRUCT_VALUE' as an expression returning an RTX for the place
-   where the address is passed.  If it returns 0, the address is
-   passed as an "invisible" first argument.  */
-#define STRUCT_VALUE 0
-
-/* Mips registers used in prologue/epilogue code when the stack frame
-   is larger than 32K bytes.  These registers must come from the
-   scratch register set, and not used for passing and returning
-   arguments and any other information used in the calling sequence
-   (such as pic).  Must start at 12, since t0/t3 are parameter passing
-   registers in the 64 bit ABI.  */
-
-#define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
-#define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
-
-/* Define this macro if it is as good or better to call a constant
-   function address than to call an address kept in a register.  */
-#define NO_FUNCTION_CSE 1
-
-/* Define this macro if it is as good or better for a function to
-   call itself with an explicit address than to call an address
-   kept in a register.  */
-#define NO_RECURSIVE_FUNCTION_CSE 1
-
-/* The register number of the register used to address a table of
-   static data addresses in memory.  In some cases this register is
-   defined by a processor's "application binary interface" (ABI). 
-   When this macro is defined, RTL is generated for this register
-   once, as with the stack pointer and frame pointer registers.  If
-   this macro is not defined, it is up to the machine-dependent
-   files to allocate such a register (if necessary).  */
-#define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
-
-#define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
-
-/* Initialize embedded_pic_fnaddr_rtx before RTL generation for
-   each function.  We used to do this in FINALIZE_PIC, but FINALIZE_PIC
-   isn't always called for static inline functions.  */
-#define INIT_EXPANDERS			\
-do {					\
-  embedded_pic_fnaddr_rtx = NULL;	\
-  mips16_gp_pseudo_rtx = NULL;		\
-} while (0)
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-enum reg_class
-{
-  NO_REGS,			/* no registers in set */
-  M16_NA_REGS,			/* mips16 regs not used to pass args */
-  M16_REGS,			/* mips16 directly accessible registers */
-  T_REG,			/* mips16 T register ($24) */
-  M16_T_REGS,			/* mips16 registers plus T register */
-  GR_REGS,			/* integer registers */
-  FP_REGS,			/* floating point registers */
-  HI_REG,			/* hi register */
-  LO_REG,			/* lo register */
-  HILO_REG,			/* hilo register pair for 64 bit mode mult */
-  MD_REGS,			/* multiply/divide registers (hi/lo) */
-  HI_AND_GR_REGS,		/* union classes */
-  LO_AND_GR_REGS,
-  HILO_AND_GR_REGS,
-  ST_REGS,			/* status registers (fp status) */
-  ALL_REGS,			/* all registers */
-  LIM_REG_CLASSES		/* max value + 1 */
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-#define GENERAL_REGS GR_REGS
-
-/* An initializer containing the names of the register classes as C
-   string constants.  These names are used in writing some of the
-   debugging dumps.  */
-
-#define REG_CLASS_NAMES							\
-{									\
-  "NO_REGS",								\
-  "M16_NA_REGS",							\
-  "M16_REGS",								\
-  "T_REG",								\
-  "M16_T_REGS",								\
-  "GR_REGS",								\
-  "FP_REGS",								\
-  "HI_REG",								\
-  "LO_REG",								\
-  "HILO_REG",								\
-  "MD_REGS",								\
-  "HI_AND_GR_REGS",							\
-  "LO_AND_GR_REGS",							\
-  "HILO_AND_GR_REGS",							\
-  "ST_REGS",								\
-  "ALL_REGS"								\
-}
-
-/* An initializer containing the contents of the register classes,
-   as integers which are bit masks.  The Nth integer specifies the
-   contents of class N.  The way the integer MASK is interpreted is
-   that register R is in the class if `MASK & (1 << R)' is 1.
-
-   When the machine has more than 32 registers, an integer does not
-   suffice.  Then the integers are replaced by sub-initializers,
-   braced groupings containing several integers.  Each
-   sub-initializer must be suitable as an initializer for the type
-   `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
-
-#define REG_CLASS_CONTENTS						\
-{									\
-  { 0x00000000, 0x00000000, 0x00000000 },	/* no registers */	\
-  { 0x0003000c, 0x00000000, 0x00000000 },	/* mips16 nonarg regs */\
-  { 0x000300fc, 0x00000000, 0x00000000 },	/* mips16 registers */	\
-  { 0x01000000, 0x00000000, 0x00000000 },	/* mips16 T register */	\
-  { 0x010300fc, 0x00000000, 0x00000000 },	/* mips16 and T regs */ \
-  { 0xffffffff, 0x00000000, 0x00000000 },	/* integer registers */	\
-  { 0x00000000, 0xffffffff, 0x00000000 },	/* floating registers*/	\
-  { 0x00000000, 0x00000000, 0x00000001 },	/* hi register */	\
-  { 0x00000000, 0x00000000, 0x00000002 },	/* lo register */	\
-  { 0x00000000, 0x00000000, 0x00000004 },	/* hilo register */	\
-  { 0x00000000, 0x00000000, 0x00000003 },	/* mul/div registers */	\
-  { 0xffffffff, 0x00000000, 0x00000001 },	/* union classes */     \
-  { 0xffffffff, 0x00000000, 0x00000002 },				\
-  { 0xffffffff, 0x00000000, 0x00000004 },				\
-  { 0x00000000, 0x00000000, 0x000007f8 },	/* status registers */	\
-  { 0xffffffff, 0xffffffff, 0x000078ff }	/* all registers */	\
-}
-
-
-/* A C expression whose value is a register class containing hard
-   register REGNO.  In general there is more that one such class;
-   choose a class which is "minimal", meaning that no smaller class
-   also contains the register.  */
-
-extern enum reg_class mips_regno_to_class[];
-
-#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
-
-/* A macro whose definition is the name of the class to which a
-   valid base register must belong.  A base register is one used in
-   an address which is the register value plus a displacement.  */
-
-#define BASE_REG_CLASS  (TARGET_MIPS16 ? M16_REGS : GR_REGS)
-
-/* A macro whose definition is the name of the class to which a
-   valid index register must belong.  An index register is one used
-   in an address where its value is either multiplied by a scale
-   factor or added to another register (as well as added to a
-   displacement).  */
-
-#define INDEX_REG_CLASS NO_REGS
-
-/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
-   registers explicitly used in the rtl to be used as spill registers
-   but prevents the compiler from extending the lifetime of these
-   registers. */
-
-#define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
-
-/* This macro is used later on in the file.  */
-#define GR_REG_CLASS_P(CLASS)						\
-  ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG	\
-   || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
-
-/* REG_ALLOC_ORDER is to order in which to allocate registers.  This
-   is the default value (allocate the registers in numeric order).  We
-   define it just so that we can override it for the mips16 target in
-   ORDER_REGS_FOR_LOCAL_ALLOC.  */
-
-#define REG_ALLOC_ORDER							\
-{  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,	\
-  16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,	\
-  32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,	\
-  48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,	\
-  64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75			\
-}
-
-/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
-   to be rearranged based on a particular function.  On the mips16, we
-   want to allocate $24 (T_REG) before other registers for
-   instructions for which it is possible.  */
-
-#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
-
-/* REGISTER AND CONSTANT CLASSES */
-
-/* Get reg_class from a letter such as appears in the machine
-   description.
-
-   DEFINED REGISTER CLASSES:
-
-   'd'  General (aka integer) registers
-        Normally this is GR_REGS, but in mips16 mode this is M16_REGS
-   'y'  General registers (in both mips16 and non mips16 mode)
-   'e'	mips16 non argument registers (M16_NA_REGS)
-   't'  mips16 temporary register ($24)
-   'f'	Floating point registers
-   'h'	Hi register
-   'l'	Lo register
-   'x'	Multiply/divide registers
-   'a'	HILO_REG
-   'z'	FP Status register
-   'b'	All registers */
-
-extern enum reg_class mips_char_to_class[];
-
-#define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
-
-/* The letters I, J, K, L, M, N, O, and P in a register constraint
-   string can be used to stand for particular ranges of immediate
-   operands.  This macro defines what the ranges are.  C is the
-   letter, and VALUE is a constant value.  Return 1 if VALUE is
-   in the range specified by C.  */
-
-/* For MIPS:
-
-   `I'	is used for the range of constants an arithmetic insn can
-	actually contain (16 bits signed integers).
-
-   `J'	is used for the range which is just zero (ie, $r0).
-
-   `K'	is used for the range of constants a logical insn can actually
-	contain (16 bit zero-extended integers).
-
-   `L'	is used for the range of constants that be loaded with lui
-	(ie, the bottom 16 bits are zero).
-
-   `M'	is used for the range of constants that take two words to load
-	(ie, not matched by `I', `K', and `L').
-
-   `N'	is used for negative 16 bit constants other than -65536.
-
-   `O'	is a 15 bit signed integer.
-
-   `P'	is used for positive 16 bit constants.  */
-
-#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
-#define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)					\
-  ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000)	\
-   : (C) == 'J' ? ((VALUE) == 0)					\
-   : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000)		\
-   : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0				\
-		   && (((VALUE) & ~2147483647) == 0			\
-		       || ((VALUE) & ~2147483647) == ~2147483647))	\
-   : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0)			\
-		   && (((VALUE) & ~0x0000ffff) != ~0x0000ffff)		\
-		   && (((VALUE) & 0x0000ffff) != 0			\
-		       || (((VALUE) & ~2147483647) != 0			\
-			   && ((VALUE) & ~2147483647) != ~2147483647)))	\
-   : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
-   : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
-   : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0))	\
-   : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-
-/* For Mips
-
-  'G'	: Floating point 0 */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)				\
-  ((C) == 'G'								\
-   && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
-
-/* Letters in the range `Q' through `U' may be defined in a
-   machine-dependent fashion to stand for arbitrary operand types. 
-   The machine description macro `EXTRA_CONSTRAINT' is passed the
-   operand as its first argument and the constraint letter as its
-   second operand.
-
-   `Q'	is for mips16 GP relative constants
-   `R'	is for memory references which take 1 word for the instruction.
-   `S'	is for references to extern items which are PIC for OSF/rose.
-   `T'	is for memory addresses that can be used to load two words.  */
-
-#define EXTRA_CONSTRAINT(OP,CODE)					\
-  (((CODE) == 'T')	  ? double_memory_operand (OP, GET_MODE (OP))	\
-   : ((CODE) == 'Q')	  ? (GET_CODE (OP) == CONST			\
-			     && mips16_gp_offset_p (OP))		\
-   : (GET_CODE (OP) != MEM) ? FALSE					\
-   : ((CODE) == 'R')	  ? simple_memory_operand (OP, GET_MODE (OP))	\
-   : ((CODE) == 'S')	  ? (HALF_PIC_P () && CONSTANT_P (OP)		\
-			     && HALF_PIC_ADDRESS_P (OP))		\
-   : FALSE)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)					\
-  ((CLASS) != ALL_REGS							\
-   ? (! TARGET_MIPS16							\
-      ? (CLASS)								\
-      : ((CLASS) != GR_REGS						\
-	 ? (CLASS)							\
-	 : M16_REGS))							\
-   : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT			\
-       || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)		\
-      ? (TARGET_SOFT_FLOAT						\
-	 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS)				\
-	 : FP_REGS)							\
-      : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT			\
-	  || GET_MODE (X) == VOIDmode)					\
-	 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS)				\
-	 : (CLASS))))
-
-/* Certain machines have the property that some registers cannot be
-   copied to some other registers without using memory.  Define this
-   macro on those machines to be a C expression that is non-zero if
-   objects of mode MODE in registers of CLASS1 can only be copied to
-   registers of class CLASS2 by storing a register of CLASS1 into
-   memory and loading that memory location into a register of CLASS2.
-
-   Do not define this macro if its value would always be zero.  */
-
-#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)			\
-  ((!TARGET_DEBUG_H_MODE						\
-    && GET_MODE_CLASS (MODE) == MODE_INT				\
-    && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2))			\
-	|| (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS)))		\
-   || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode		\
-       && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS)		\
-	   || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
-
-/* The HI and LO registers can only be reloaded via the general
-   registers.  Condition code registers can only be loaded to the
-   general registers, and from the floating point registers.  */
-
-#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)			\
-  mips_secondary_reload_class (CLASS, MODE, X, 1)
-#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)			\
-  mips_secondary_reload_class (CLASS, MODE, X, 0)
-
-/* Not declared above, with the other functions, because enum
-   reg_class is not declared yet.  */
-extern enum reg_class	mips_secondary_reload_class ();
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-
-#define CLASS_UNITS(mode, size)						\
-  ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
-
-#define CLASS_MAX_NREGS(CLASS, MODE)					\
-  ((CLASS) == FP_REGS							\
-   ? (TARGET_FLOAT64							\
-      ? CLASS_UNITS (MODE, 8)						\
-      : 2 * CLASS_UNITS (MODE, 8))					\
-   : CLASS_UNITS (MODE, UNITS_PER_WORD))
-
-/* If defined, gives a class of registers that cannot be used as the
-   operand of a SUBREG that changes the size of the object.  */
-
-#define CLASS_CANNOT_CHANGE_SIZE                                      \
-  (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
-
-/* If defined, this is a C expression whose value should be
-   nonzero if the insn INSN has the effect of mysteriously
-   clobbering the contents of hard register number REGNO.  By
-   "mysterious" we mean that the insn's RTL expression doesn't
-   describe such an effect.
-
-   If this macro is not defined, it means that no insn clobbers
-   registers mysteriously.  This is the usual situation; all else
-   being equal, it is best for the RTL expression to show all the
-   activity.  */
-
-/* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
-
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-/* #define FRAME_GROWS_DOWNWARD */
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET						\
-  (current_function_outgoing_args_size					\
-   + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
-
-/* Offset from the stack pointer register to an item dynamically
-   allocated on the stack, e.g., by `alloca'.
-
-   The default value for this macro is `STACK_POINTER_OFFSET' plus the
-   length of the outgoing arguments.  The default is correct for most
-   machines.  See `function.c' for details.
-
-   The MIPS ABI states that functions which dynamically allocate the
-   stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
-   we are trying to create a second frame pointer to the function, so
-   allocate some stack space to make it happy.
-
-   However, the linker currently complains about linking any code that
-   dynamically allocates stack space, and there seems to be a bug in
-   STACK_DYNAMIC_OFFSET, so don't define this right now.  */
-
-#if 0
-#define STACK_DYNAMIC_OFFSET(FUNDECL)					\
-  ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
-	? 4*UNITS_PER_WORD						\
-	: current_function_outgoing_args_size)
-#endif
-
-/* The return address for the current frame is in r31 is this is a leaf
-   function.  Otherwise, it is on the stack.  It is at a variable offset
-   from sp/fp/ap, so we define a fake hard register rap which is a
-   poiner to the return address on the stack.  This always gets eliminated
-   during reload to be either the frame pointer or the stack pointer plus
-   an offset.  */
-
-/* ??? This definition fails for leaf functions.  There is currently no
-   general solution for this problem.  */
-
-/* ??? There appears to be no way to get the return address of any previous
-   frame except by disassembling instructions in the prologue/epilogue.
-   So currently we support only the current frame.  */
-
-#define RETURN_ADDR_RTX(count, frame)			\
-  ((count == 0)						\
-   ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
-   : (rtx) 0)
-
-/* Structure to be filled in by compute_frame_size with register
-   save masks, and offsets for the current function.  */
-
-struct mips_frame_info
-{
-  long total_size;		/* # bytes that the entire frame takes up */
-  long var_size;		/* # bytes that variables take up */
-  long args_size;		/* # bytes that outgoing arguments take up */
-  long extra_size;		/* # bytes of extra gunk */
-  int  gp_reg_size;		/* # bytes needed to store gp regs */
-  int  fp_reg_size;		/* # bytes needed to store fp regs */
-  long mask;			/* mask of saved gp registers */
-  long fmask;			/* mask of saved fp registers */
-  long gp_save_offset;		/* offset from vfp to store gp registers */
-  long fp_save_offset;		/* offset from vfp to store fp registers */
-  long gp_sp_offset;		/* offset from new sp to store gp registers */
-  long fp_sp_offset;		/* offset from new sp to store fp registers */
-  int  initialized;		/* != 0 if frame size already calculated */
-  int  num_gp;			/* number of gp registers saved */
-  int  num_fp;			/* number of fp registers saved */
-  long insns_len;		/* length of insns; mips16 only */
-};
-
-extern struct mips_frame_info current_frame_info;
-
-/* If defined, this macro specifies a table of register pairs used to
-   eliminate unneeded registers that point into the stack frame.  If
-   it is not defined, the only elimination attempted by the compiler
-   is to replace references to the frame pointer with references to
-   the stack pointer.
-
-   The definition of this macro is a list of structure
-   initializations, each of which specifies an original and
-   replacement register.
-
-   On some machines, the position of the argument pointer is not
-   known until the compilation is completed.  In such a case, a
-   separate hard register must be used for the argument pointer. 
-   This register can be eliminated by replacing it with either the
-   frame pointer or the argument pointer, depending on whether or not
-   the frame pointer has been eliminated.
-
-   In this case, you might specify:
-        #define ELIMINABLE_REGS  \
-        {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
-         {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
-         {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
-
-   Note that the elimination of the argument pointer with the stack
-   pointer is specified first since that is the preferred elimination.
-
-   The eliminations to $17 are only used on the mips16.  See the
-   definition of HARD_FRAME_POINTER_REGNUM.  */
-
-#define ELIMINABLE_REGS							\
-{{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},				\
- { ARG_POINTER_REGNUM,   GP_REG_FIRST + 30},				\
- { ARG_POINTER_REGNUM,   GP_REG_FIRST + 17},				\
- { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},		\
- { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30},			\
- { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17},			\
- { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31},			\
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},				\
- { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30},				\
- { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
-
-/* A C expression that returns non-zero if the compiler is allowed to
-   try to replace register number FROM-REG with register number
-   TO-REG.  This macro need only be defined if `ELIMINABLE_REGS' is
-   defined, and will usually be the constant 1, since most of the
-   cases preventing register elimination are things that the compiler
-   already knows about.
-
-   When not in mips16 and mips64, we can always eliminate to the
-   frame pointer.  We can eliminate to the stack pointer unless
-   a frame pointer is needed.  In mips16 mode, we need a frame
-   pointer for a large frame; otherwise, reload may be unable
-   to compute the address of a local variable, since there is
-   no way to add a large constant to the stack pointer
-   without using a temporary register.
-
-   In mips16, for some instructions (eg lwu), we can't eliminate the
-   frame pointer for the stack pointer.  These instructions are
-   only generated in TARGET_64BIT mode.
-   */
-
-#define CAN_ELIMINATE(FROM, TO)						\
-  (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p ()	\
-   || (TO == GP_REG_FIRST + 31 && leaf_function_p)))   			\
-  || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM				\
-   && ((TO) == HARD_FRAME_POINTER_REGNUM 				\
-   || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed		\
-       && ! (TARGET_MIPS16 && TARGET_64BIT)                             \
-       && (! TARGET_MIPS16						\
-	   || compute_frame_size (get_frame_size ()) < 32768)))))
-
-/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'.  It
-   specifies the initial difference between the specified pair of
-   registers.  This macro must be defined if `ELIMINABLE_REGS' is
-   defined.  */
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			 \
-{  compute_frame_size (get_frame_size ());				 \
-  if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM			 \
-      && (TO) == HARD_FRAME_POINTER_REGNUM)				 \
-    (OFFSET) = - current_function_outgoing_args_size;			 \
-  else if ((FROM) == FRAME_POINTER_REGNUM)				 \
-    (OFFSET) = 0;							 \
-  else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM		 \
-	   && (TO) == HARD_FRAME_POINTER_REGNUM)			 \
-    (OFFSET) = (current_frame_info.total_size				 \
-		- current_function_outgoing_args_size			 \
-		- ((mips_abi != ABI_32 					 \
-		    && mips_abi != ABI_O64				 \
-		    && mips_abi != ABI_EABI)				 \
-		   ? current_function_pretend_args_size			 \
-		   : 0));						 \
-  else if ((FROM) == ARG_POINTER_REGNUM)				 \
-    (OFFSET) = (current_frame_info.total_size				 \
-		- ((mips_abi != ABI_32 					 \
-		    && mips_abi != ABI_O64				 \
-		    && mips_abi != ABI_EABI)				 \
-		   ? current_function_pretend_args_size			 \
-		   : 0));						 \
-  /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits,	 \
-     so we must add 4 bytes to the offset to get the right value.  */	 \
-  else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM)			 \
-  {									 \
-   if (leaf_function_p ()) 						 \
-      (OFFSET) = 0;				 			 \
-   else (OFFSET) = current_frame_info.gp_sp_offset			 \
-	       + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT))	 \
-		  * (BYTES_BIG_ENDIAN != 0));				 \
-  }									 \
-}
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On the vax, sp@- in a byte insn really pushes a word.  */
-
-/* #define PUSH_ROUNDING(BYTES) 0 */
-
-/* If defined, the maximum amount of space required for outgoing
-   arguments will be computed and placed into the variable
-   `current_function_outgoing_args_size'.  No space will be pushed
-   onto the stack for each call; instead, the function prologue
-   should increase the stack frame size by this amount.
-
-   It is not proper to define both `PUSH_ROUNDING' and
-   `ACCUMULATE_OUTGOING_ARGS'.  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Offset from the argument pointer register to the first argument's
-   address.  On some machines it may depend on the data type of the
-   function.
-
-   If `ARGS_GROW_DOWNWARD', this is the offset to the location above
-   the first argument's address.
-
-   On the MIPS, we must skip the first argument position if we are
-   returning a structure or a union, to account for its address being
-   passed in $4.  However, at the current time, this produces a compiler
-   that can't bootstrap, so comment it out for now.  */
-
-#if 0
-#define FIRST_PARM_OFFSET(FNDECL)					\
-  (FNDECL != 0								\
-   && TREE_TYPE (FNDECL) != 0						\
-   && TREE_TYPE (TREE_TYPE (FNDECL)) != 0				\
-   && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE	\
-       || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE)	\
-		? UNITS_PER_WORD					\
-		: 0)
-#else
-#define FIRST_PARM_OFFSET(FNDECL) 0
-#endif
-
-/* When a parameter is passed in a register, stack space is still
-   allocated for it.  For the MIPS, stack space must be allocated, cf
-   Asm Lang Prog Guide page 7-8.
-
-   BEWARE that some space is also allocated for non existing arguments
-   in register. In case an argument list is of form GF used registers
-   are a0 (a2,a3), but we should push over a1...  */
-
-#define REG_PARM_STACK_SPACE(FNDECL)	\
-  ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
-
-/* Define this if it is the responsibility of the caller to
-   allocate the area reserved for arguments passed in registers. 
-   If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
-   of this macro is to determine whether the space is included in 
-   `current_function_outgoing_args_size'.  */
-#define OUTGOING_REG_PARM_STACK_SPACE
-
-/* Align stack frames on 64 bits (Double Word ).  */
-#ifndef STACK_BOUNDARY
-#define STACK_BOUNDARY 64
-#endif
-
-/* Make sure 4 words are always allocated on the stack.  */
-
-#ifndef STACK_ARGS_ADJUST
-#define STACK_ARGS_ADJUST(SIZE)						\
-{									\
-  if (SIZE.constant < 4 * UNITS_PER_WORD)				\
-    SIZE.constant = 4 * UNITS_PER_WORD;					\
-}
-#endif
-
-
-/* A C expression that should indicate the number of bytes of its
-   own arguments that a function pops on returning, or 0
-   if the function pops no arguments and the caller must therefore
-   pop them all after the function returns.
-
-   FUNDECL is the declaration node of the function (as a tree).
-
-   FUNTYPE is a C variable whose value is a tree node that
-   describes the function in question.  Normally it is a node of
-   type `FUNCTION_TYPE' that describes the data type of the function.
-   From this it is possible to obtain the data types of the value
-   and arguments (if known).
-
-   When a call to a library function is being considered, FUNTYPE
-   will contain an identifier node for the library function.  Thus,
-   if you need to distinguish among various library functions, you
-   can do so by their names.  Note that "library function" in this
-   context means a function used to perform arithmetic, whose name
-   is known specially in the compiler and was not mentioned in the
-   C code being compiled.
-
-   STACK-SIZE is the number of bytes of arguments passed on the
-   stack.  If a variable number of bytes is passed, it is zero, and
-   argument popping will always be the responsibility of the
-   calling function.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-
-/* Symbolic macros for the registers used to return integer and floating
-   point values.  */
-
-#define GP_RETURN (GP_REG_FIRST + 2)
-#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
-
-/* Symbolic macros for the first/last argument registers.  */
-
-#define GP_ARG_FIRST (GP_REG_FIRST + 4)
-#define GP_ARG_LAST  (GP_REG_FIRST + 7)
-#define FP_ARG_FIRST (FP_REG_FIRST + 12)
-#define FP_ARG_LAST  (FP_REG_FIRST + 15)
-
-#define MAX_ARGS_IN_REGISTERS	4
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  Because we define
-   PROMOTE_FUNCTION_RETURN, we must promote the mode just as
-   PROMOTE_MODE does.  */
-
-#define LIBCALL_VALUE(MODE)						\
-  gen_rtx (REG,								\
-	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
-	     || GET_MODE_SIZE (MODE) >= 4)				\
-	    ? (MODE)							\
-	    : SImode),							\
-	   ((GET_MODE_CLASS (MODE) == MODE_FLOAT			\
-	     && (! TARGET_SINGLE_FLOAT					\
-		 || GET_MODE_SIZE (MODE) <= 4))				\
-	    ? FP_RETURN							\
-	    : GP_RETURN))
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
-
-
-/* 1 if N is a possible register number for a function value.
-   On the MIPS, R2 R3 and F0 F2 are the only register thus used.
-   Currently, R2 and F0 are only implemented  here (C has no complex type)  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
-
-/* 1 if N is a possible register number for function argument passing.
-   We have no FP argument registers when soft-float.  When FP registers
-   are 32 bits, we can't directly reference the odd numbered ones.  */
-
-#define FUNCTION_ARG_REGNO_P(N)					\
-  (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST)			\
-   || ((! TARGET_SOFT_FLOAT					\
-       && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST)		\
-       && (TARGET_FLOAT64 || (0 == (N) % 2)))			\
-       && ! fixed_regs[N]))
-
-/* A C expression which can inhibit the returning of certain function
-   values in registers, based on the type of value.  A nonzero value says
-   to return the function value in memory, just as large structures are
-   always returned.  Here TYPE will be a C expression of type
-   `tree', representing the data type of the value.
-
-   Note that values of mode `BLKmode' must be explicitly
-   handled by this macro.  Also, the option `-fpcc-struct-return'
-   takes effect regardless of this macro.  On most systems, it is
-   possible to leave the macro undefined; this causes a default
-   definition to be used, whose value is the constant 1 for BLKmode
-   values, and 0 otherwise.
-
-   GCC normally converts 1 byte structures into chars, 2 byte
-   structs into shorts, and 4 byte structs into ints, and returns
-   them this way.  Defining the following macro overrides this,
-   to give us MIPS cc compatibility.  */
-
-#define RETURN_IN_MEMORY(TYPE)	\
-  (TYPE_MODE (TYPE) == BLKmode)
-
-/* A code distinguishing the floating point format of the target
-   machine.  There are three defined values: IEEE_FLOAT_FORMAT,
-   VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT.  */
-
-#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
-
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the mips16, we need to keep track of which floating point
-   arguments were passed in general registers, but would have been
-   passed in the FP regs if this were a 32 bit function, so that we
-   can move them to the FP regs if we wind up calling a 32 bit
-   function.  We record this information in fp_code, encoded in base
-   four.  A zero digit means no floating point argument, a one digit
-   means an SFmode argument, and a two digit means a DFmode argument,
-   and a three digit is not used.  The low order digit is the first
-   argument.  Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
-   an SFmode argument.  ??? A more sophisticated approach will be
-   needed if MIPS_ABI != ABI_32.  */
-
-typedef struct mips_args {
-  int gp_reg_found;		/* whether a gp register was found yet */
-  int arg_number;		/* argument number */
-  int arg_words;		/* # total words the arguments take */
-  int fp_arg_words;		/* # words for FP args (MIPS_EABI only) */
-  int last_arg_fp;		/* nonzero if last arg was FP (EABI only) */
-  int fp_code;			/* Mode of FP arguments (mips16) */
-  int num_adjusts;		/* number of adjustments made */
-				/* Adjustments made to args pass in regs.  */
-				/* ??? The size is doubled to work around a 
-				   bug in the code that sets the adjustments
-				   in function_arg.  */
-  struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
-} CUMULATIVE_ARGS;
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-*/
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)		\
-  init_cumulative_args (&CUM, FNTYPE, LIBNAME)				\
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
-  function_arg_advance (&CUM, MODE, TYPE, NAMED)
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  function_arg( &CUM, MODE, TYPE, NAMED)
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero. */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-  function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
-
-/* If defined, a C expression that gives the alignment boundary, in
-   bits, of an argument with the specified mode and type.  If it is
-   not defined,  `PARM_BOUNDARY' is used for all arguments.  */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE)				\
-  (((TYPE) != 0)							\
-	? ((TYPE_ALIGN(TYPE) <= (unsigned)PARM_BOUNDARY)		\
-		? PARM_BOUNDARY						\
-		: TYPE_ALIGN(TYPE))					\
-	: ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY)			\
-		? PARM_BOUNDARY						\
-		: GET_MODE_ALIGNMENT(MODE)))
-
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
-
-
-/* Tell prologue and epilogue if register REGNO should be saved / restored.  */
-
-#define MUST_SAVE_REGISTER(regno) \
- ((regs_ever_live[regno] && !call_used_regs[regno])			\
-  || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)	\
-  || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
-
-/* ALIGN FRAMES on double word boundaries */
-#ifndef MIPS_STACK_ALIGN
-#define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
-#endif
-
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)				\
-{									\
-  if (TARGET_MIPS16)							\
-    sorry ("mips16 function profiling");				\
-  fprintf (FILE, "\t.set\tnoreorder\n");				\
-  fprintf (FILE, "\t.set\tnoat\n");					\
-  fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",	\
-	   reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);	\
-  fprintf (FILE, "\tjal\t_mcount\n");					\
-  fprintf (FILE,							\
-	   "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",	\
-	   TARGET_64BIT ? "dsubu" : "subu",				\
-	   reg_names[STACK_POINTER_REGNUM],				\
-	   reg_names[STACK_POINTER_REGNUM],				\
-	   Pmode == DImode ? 16 : 8);					\
-  fprintf (FILE, "\t.set\treorder\n");					\
-  fprintf (FILE, "\t.set\tat\n");					\
-}
-
-/* Define this macro if the code for function profiling should come
-   before the function prologue.  Normally, the profiling code comes
-   after.  */
-
-/* #define PROFILE_BEFORE_PROLOGUE */
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-
-/* A C statement to output, on the stream FILE, assembler code for a
-   block of data that contains the constant parts of a trampoline. 
-   This code should not include a label--the label is taken care of
-   automatically.  */
-
-#define TRAMPOLINE_TEMPLATE(STREAM)					 \
-{									 \
-  fprintf (STREAM, "\t.word\t0x03e00821\t\t# move   $1,$31\n");		\
-  fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n");		\
-  fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n");			\
-  if (Pmode == DImode)							\
-    {									\
-      fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld     $3,20($31)\n");	\
-      fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld     $2,28($31)\n");	\
-    }									\
-  else									\
-    {									\
-      fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw     $3,20($31)\n");	\
-      fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw     $2,24($31)\n");	\
-    }									\
-  fprintf (STREAM, "\t.word\t0x0060c821\t\t# move   $25,$3 (abicalls)\n"); \
-  fprintf (STREAM, "\t.word\t0x00600008\t\t# jr     $3\n");		\
-  fprintf (STREAM, "\t.word\t0x0020f821\t\t# move   $31,$1\n");		\
-  if (Pmode == DImode)							\
-    {									\
-      fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
-      fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
-    }									\
-  else									\
-    {									\
-      fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
-      fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
-    }									\
-}
-
-/* A C expression for the size in bytes of the trampoline, as an
-   integer.  */
-
-#define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
-
-/* Alignment required for trampolines, in bits.  */
-
-#define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
-
-/* INITIALIZE_TRAMPOLINE calls this library function to flush
-   program and data caches.  */
-
-#ifndef CACHE_FLUSH_FUNC
-#define CACHE_FLUSH_FUNC "_flush_cache"
-#endif
-
-/* A C statement to initialize the variable parts of a trampoline. 
-   ADDR is an RTX for the address of the trampoline; FNADDR is an
-   RTX for the address of the nested function; STATIC_CHAIN is an
-   RTX for the static chain value that should be passed to the
-   function when it is called.  */
-
-#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN)			    \
-{									    \
-  rtx addr = ADDR;							    \
-  if (Pmode == DImode)							    \
-    {									    \
-      emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
-      emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
-    }									    \
-  else									    \
-    {									    \
-      emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
-      emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
-    }									    \
-									    \
-  /* Flush both caches.  We need to flush the data cache in case	    \
-     the system has a write-back cache.  */				    \
-  /* ??? Should check the return value for errors.  */			    \
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, CACHE_FLUSH_FUNC),	    \
-		     0, VOIDmode, 3, addr, Pmode,			    \
-		     GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
-		     GEN_INT (3), TYPE_MODE (integer_type_node));	    \
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   These definitions are NOT overridden anywhere.  */
-
-#define BASE_REG_P(regno, mode)					\
-  (TARGET_MIPS16						\
-   ? (M16_REG_P (regno)						\
-      || (regno) == FRAME_POINTER_REGNUM			\
-      || (regno) == ARG_POINTER_REGNUM				\
-      || ((regno) == STACK_POINTER_REGNUM			\
-	  && (GET_MODE_SIZE (mode) == 4				\
-	      || GET_MODE_SIZE (mode) == 8)))			\
-   : GP_REG_P (regno))
-
-#define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)				    \
-  BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
-	     (mode))
-
-#define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
-  (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
-
-#define REGNO_OK_FOR_INDEX_P(regno)	0
-#define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
-  GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects them all.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Some source files that are used after register allocation
-   need to be strict.  */
-
-#ifndef REG_OK_STRICT
-
-#define REG_OK_STRICT_P 0
-#define REG_OK_FOR_INDEX_P(X) 0
-#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
-  GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
-
-#else
-
-#define REG_OK_STRICT_P 1
-#define REG_OK_FOR_INDEX_P(X) 0
-#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
-  REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
-
-#endif
-
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 1
-
-/* A C compound statement with a conditional `goto LABEL;' executed
-   if X (an RTX) is a legitimate memory address on the target
-   machine for a memory operand of mode MODE.
-
-   It usually pays to define several simpler macros to serve as
-   subroutines for this one.  Otherwise it may be too complicated
-   to understand.
-
-   This macro must exist in two variants: a strict variant and a
-   non-strict one.  The strict variant is used in the reload pass. 
-   It must be defined so that any pseudo-register that has not been
-   allocated a hard register is considered a memory reference.  In
-   contexts where some kind of register is required, a
-   pseudo-register with no hard register must be rejected.
-
-   The non-strict variant is used in other passes.  It must be
-   defined to accept all pseudo-registers in every context where
-   some kind of register is required.
-
-   Compiler source files that want to use the strict variant of
-   this macro define the macro `REG_OK_STRICT'.  You should use an
-   `#ifdef REG_OK_STRICT' conditional to define the strict variant
-   in that case and the non-strict variant otherwise.
-
-   Typically among the subroutines used to define
-   `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
-   acceptable registers for various purposes (one for base
-   registers, one for index registers, and so on).  Then only these
-   subroutine macros need have two variants; the higher levels of
-   macros may be the same whether strict or not.
-
-   Normally, constant addresses which are the sum of a `symbol_ref'
-   and an integer are stored inside a `const' RTX to mark them as
-   constant.  Therefore, there is no need to recognize such sums
-   specifically as legitimate addresses.  Normally you would simply
-   recognize any `const' as legitimate.
-
-   Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
-   constant sums that are not marked with  `const'.  It assumes
-   that a naked `plus' indicates indexing.  If so, then you *must*
-   reject such naked constant sums as illegitimate addresses, so
-   that none of them will be given to `PRINT_OPERAND_ADDRESS'.
-
-   On some machines, whether a symbolic address is legitimate
-   depends on the section that the address refers to.  On these
-   machines, define the macro `ENCODE_SECTION_INFO' to store the
-   information into the `symbol_ref', and then check for it here. 
-   When you see a `const', you will have to look inside it to find
-   the `symbol_ref' in order to determine the section.  */
-
-#if 1
-#define GO_PRINTF(x)	trace(x)
-#define GO_PRINTF2(x,y)	trace(x,y)
-#define GO_DEBUG_RTX(x) debug_rtx(x)
-
-#else
-#define GO_PRINTF(x)
-#define GO_PRINTF2(x,y)
-#define GO_DEBUG_RTX(x)
-#endif
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-{									\
-  register rtx xinsn = (X);						\
-									\
-  if (TARGET_DEBUG_B_MODE)						\
-    {									\
-      GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",	\
-		  (REG_OK_STRICT_P) ? "" : "not ");			\
-      GO_DEBUG_RTX (xinsn);						\
-    }									\
-									\
-  /* The mips16 can only use the stack pointer as a base register when	\
-     loading SImode or DImode values.  */				\
-  if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE))	\
-    goto ADDR;								\
-									\
-  if (CONSTANT_ADDRESS_P (xinsn)					\
-      && ! (mips_split_addresses && mips_check_split (xinsn, MODE))	\
-      && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0)))	\
-    goto ADDR;								\
-									\
-  if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)		\
-    {									\
-      register rtx xlow0 = XEXP (xinsn, 0);				\
-      register rtx xlow1 = XEXP (xinsn, 1);				\
-									\
-      if (GET_CODE (xlow0) == REG					\
-	  && REG_MODE_OK_FOR_BASE_P (xlow0, MODE)			\
-	  && mips_check_split (xlow1, MODE))				\
-	goto ADDR;							\
-    }									\
-									\
-  if (GET_CODE (xinsn) == PLUS)						\
-    {									\
-      register rtx xplus0 = XEXP (xinsn, 0);				\
-      register rtx xplus1 = XEXP (xinsn, 1);				\
-      register enum rtx_code code0 = GET_CODE (xplus0);			\
-      register enum rtx_code code1 = GET_CODE (xplus1);			\
-									\
-      /* The mips16 can only use the stack pointer as a base register	\
-         when loading SImode or DImode values.  */			\
-      if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE))	\
-	{								\
-	  if (code1 == CONST_INT					\
-	      && INTVAL (xplus1) >= -32768				\
-	      && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767)	\
-	    goto ADDR;							\
-									\
-	  /* On the mips16, we represent GP relative offsets in RTL.	\
-             These are 16 bit signed values, and can serve as register	\
-             offsets.  */						\
-	  if (TARGET_MIPS16						\
-	      && mips16_gp_offset_p (xplus1))				\
-	    goto ADDR;							\
-									\
-	  /* For some code sequences, you actually get better code by	\
-	     pretending that the MIPS supports an address mode of a	\
-	     constant address + a register, even though the real	\
-	     machine doesn't support it.  This is because the		\
-	     assembler can use $r1 to load just the high 16 bits, add	\
-	     in the register, and fold the low 16 bits into the memory	\
-	     reference, whereas the compiler generates a 4 instruction	\
-	     sequence.  On the other hand, CSE is not as effective.	\
-	     It would be a win to generate the lui directly, but the	\
-	     MIPS assembler does not have syntax to generate the	\
-	     appropriate relocation.  */				\
-									\
-	  /* Also accept CONST_INT addresses here, so no else.  */	\
-	  /* Reject combining an embedded PIC text segment reference	\
-	     with a register.  That requires an additional		\
-	     instruction.  */						\
-          /* ??? Reject combining an address with a register for the MIPS  \
-	     64 bit ABI, because the SGI assembler can not handle this.  */ \
-	  if (!TARGET_DEBUG_A_MODE					\
-	      && (mips_abi == ABI_32					\
-		  || mips_abi == ABI_O64				\
-		  || mips_abi == ABI_EABI)				\
-	      && CONSTANT_ADDRESS_P (xplus1)				\
-	      && ! mips_split_addresses					\
-	      && (!TARGET_EMBEDDED_PIC					\
-		  || code1 != CONST					\
-		  || GET_CODE (XEXP (xplus1, 0)) != MINUS)		\
-	      && !TARGET_MIPS16)					\
-	    goto ADDR;							\
-	}								\
-    }									\
-									\
-  if (TARGET_DEBUG_B_MODE)						\
-    GO_PRINTF ("Not a legitimate address\n");				\
-}
-
-
-/* A C expression that is 1 if the RTX X is a constant which is a
-   valid address.  This is defined to be the same as `CONSTANT_P (X)',
-   but rejecting CONST_DOUBLE.  */
-/* When pic, we must reject addresses of the form symbol+large int.
-   This is because an instruction `sw $4,s+70000' needs to be converted
-   by the assembler to `lw $at,s($gp);sw $4,70000($at)'.  Normally the
-   assembler would use $at as a temp to load in the large offset.  In this
-   case $at is already in use.  We convert such problem addresses to
-   `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS.  */
-/* ??? SGI Irix 6 assembler fails for CONST address, so reject them.  */
-#define CONSTANT_ADDRESS_P(X)						\
-  ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-    || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH		\
-    || (GET_CODE (X) == CONST						\
-	&& ! (flag_pic && pic_address_needs_scratch (X))		\
-	&& (mips_abi == ABI_32						\
-	    || mips_abi == ABI_O64					\
-	    || mips_abi == ABI_EABI)))					\
-   && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
-
-/* Define this, so that when PIC, reload won't try to reload invalid
-   addresses which require two reload registers.  */
-
-#define LEGITIMATE_PIC_OPERAND_P(X)  (! pic_address_needs_scratch (X))
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
-
-   At present, GAS doesn't understand li.[sd], so don't allow it
-   to be generated at present.  Also, the MIPS assembler does not
-   grok li.d Infinity.  */
-
-/* ??? SGI Irix 6 assembler fails for CONST address, so reject them.  */
-#define LEGITIMATE_CONSTANT_P(X)					\
-  ((GET_CODE (X) != CONST_DOUBLE					\
-    || mips_const_double_ok (X, GET_MODE (X)))				\
-   && ! (GET_CODE (X) == CONST						\
-	 && mips_abi != ABI_32 						\
-	 && mips_abi != ABI_O64 					\
-         && mips_abi != ABI_EABI)					\
-   && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
-
-/* A C compound statement that attempts to replace X with a valid
-   memory address for an operand of mode MODE.  WIN will be a C
-   statement label elsewhere in the code; the macro definition may
-   use
-
-          GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
-
-   to avoid further processing if the address has become legitimate.
-
-   X will always be the result of a call to `break_out_memory_refs',
-   and OLDX will be the operand that was given to that function to
-   produce X.
-
-   The code generated by this macro should not alter the
-   substructure of X.  If it transforms X into a more legitimate
-   form, it should assign X (which will always be a C variable) a
-   new value.
-
-   It is not necessary for this macro to come up with a legitimate
-   address.  The compiler has standard ways of doing so in all
-   cases.  In fact, it is safe for this macro to do nothing.  But
-   often a machine-dependent strategy can generate better code.
-
-   For the MIPS, transform:
-
-	memory(X + <large int>)
-
-   into:
-
-	Y = <large int> & ~0x7fff;
-	Z = X + Y
-	memory (Z + (<large int> & 0x7fff));
-
-   This is for CSE to find several similar references, and only use one Z.
-
-   When PIC, convert addresses of the form memory (symbol+large int) to
-   memory (reg+large int).  */
-   
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)				\
-{									\
-  register rtx xinsn = (X);						\
-									\
-  if (TARGET_DEBUG_B_MODE)						\
-    {									\
-      GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n");			\
-      GO_DEBUG_RTX (xinsn);						\
-    }									\
-									\
-  if (mips_split_addresses && mips_check_split (X, MODE))		\
-    {									\
-      /* ??? Is this ever executed?  */					\
-      X = gen_rtx (LO_SUM, Pmode,					\
-		   copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
-      goto WIN;								\
-    }									\
-									\
-  if (GET_CODE (xinsn) == CONST						\
-      && ((flag_pic && pic_address_needs_scratch (xinsn))		\
-	  /* ??? SGI's Irix 6 assembler can't handle CONST.  */		\
-	  || (mips_abi != ABI_32 					\
-	      && mips_abi != ABI_O64					\
-	      && mips_abi != ABI_EABI)))				\
-    {									\
-      rtx ptr_reg = gen_reg_rtx (Pmode);				\
-      rtx constant = XEXP (XEXP (xinsn, 0), 1);				\
-									\
-      emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0));		\
-									\
-      X = gen_rtx (PLUS, Pmode, ptr_reg, constant);			\
-      if (SMALL_INT (constant))						\
-	goto WIN;							\
-      /* Otherwise we fall through so the code below will fix the	\
-	 constant.  */							\
-      xinsn = X;							\
-    }									\
-									\
-  if (GET_CODE (xinsn) == PLUS)						\
-    {									\
-      register rtx xplus0 = XEXP (xinsn, 0);				\
-      register rtx xplus1 = XEXP (xinsn, 1);				\
-      register enum rtx_code code0 = GET_CODE (xplus0);			\
-      register enum rtx_code code1 = GET_CODE (xplus1);			\
-									\
-      if (code0 != REG && code1 == REG)					\
-	{								\
-	  xplus0 = XEXP (xinsn, 1);					\
-	  xplus1 = XEXP (xinsn, 0);					\
-	  code0 = GET_CODE (xplus0);					\
-	  code1 = GET_CODE (xplus1);					\
-	}								\
-									\
-      if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)		\
-	  && code1 == CONST_INT && !SMALL_INT (xplus1))			\
-	{								\
-	  rtx int_reg = gen_reg_rtx (Pmode);				\
-	  rtx ptr_reg = gen_reg_rtx (Pmode);				\
-									\
-	  emit_move_insn (int_reg,					\
-			  GEN_INT (INTVAL (xplus1) & ~ 0x7fff));	\
-									\
-	  emit_insn (gen_rtx (SET, VOIDmode,				\
-			      ptr_reg,					\
-			      gen_rtx (PLUS, Pmode, xplus0, int_reg)));	\
-									\
-	  X = gen_rtx (PLUS, Pmode, ptr_reg,				\
-		       GEN_INT (INTVAL (xplus1) & 0x7fff));		\
-	  goto WIN;							\
-	}								\
-    }									\
-									\
-  if (TARGET_DEBUG_B_MODE)						\
-    GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n");			\
-}
-
-
-/* A C statement or compound statement with a conditional `goto
-   LABEL;' executed if memory address X (an RTX) can have different
-   meanings depending on the machine mode of the memory reference it
-   is used for.
-
-   Autoincrement and autodecrement addresses typically have
-   mode-dependent effects because the amount of the increment or
-   decrement is the size of the operand being addressed.  Some
-   machines have other mode-dependent addresses.  Many RISC machines
-   have no mode-dependent addresses.
-
-   You may assume that ADDR is a valid address for the machine.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
-
-
-/* Define this macro if references to a symbol must be treated
-   differently depending on something about the variable or
-   function named by the symbol (such as what section it is in).
-
-   The macro definition, if any, is executed immediately after the
-   rtl for DECL has been created and stored in `DECL_RTL (DECL)'. 
-   The value of the rtl will be a `mem' whose address is a
-   `symbol_ref'.
-
-   The usual thing for this macro to do is to a flag in the
-   `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
-   name string in the `symbol_ref' (if one bit is not enough
-   information).
-
-   The best way to modify the name string is by adding text to the
-   beginning, with suitable punctuation to prevent any ambiguity. 
-   Allocate the new name in `saveable_obstack'.  You will have to
-   modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
-   and output the name accordingly.
-
-   You can also check the information stored in the `symbol_ref' in
-   the definition of `GO_IF_LEGITIMATE_ADDRESS' or
-   `PRINT_OPERAND_ADDRESS'.
-
-   When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
-   small objects.
-
-   When generating embedded PIC code, SYMBOL_REF_FLAG is set for
-   symbols which are not in the .text section.
-
-   When generating mips16 code, SYMBOL_REF_FLAG is set for string
-   constants which are put in the .text section.  We also record the
-   total length of all such strings; this total is used to decide
-   whether we need to split the constant table, and need not be
-   precisely correct. 
-
-   When not mips16 code nor embedded PIC, if a symbol is in a
-   gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
-   splitting the reference so that gas can generate a gp relative
-   reference.
-
-   When TARGET_EMBEDDED_DATA is set, we assume that all const
-   variables will be stored in ROM, which is too far from %gp to use
-   %gprel addressing.  Note that (1) we include "extern const"
-   variables in this, which mips_select_section doesn't, and (2) we
-   can't always tell if they're really const (they might be const C++
-   objects with non-const constructors), so we err on the side of
-   caution and won't use %gprel anyway (otherwise we'd have to defer
-   this decision to the linker/loader).  The handling of extern consts
-   is why the DECL_INITIAL macros differ from mips_select_section.
-
-   If you are changing this macro, you should look at
-   mips_select_section and see if it needs a similar change.  */
-
-#define ENCODE_SECTION_INFO(DECL)					\
-do									\
-  {									\
-    if (TARGET_MIPS16)							\
-      {									\
-	if (TREE_CODE (DECL) == STRING_CST				\
-	    && ! flag_writable_strings					\
-	    /* If this string is from a function, and the function will	\
-	       go in a gnu linkonce section, then we can't directly	\
-	       access the string.  This gets an assembler error		\
-	       "unsupported PC relative reference to different section".\
-	       If we modify SELECT_SECTION to put it in function_section\
-	       instead of text_section, it still fails because		\
-	       DECL_SECTION_NAME isn't set until assemble_start_function.\
-	       If we fix that, it still fails because strings are shared\
-	       among multiple functions, and we have cross section	\
-	       references again.  We force it to work by putting string	\
-	       addresses in the constant pool and indirecting.  */	\
-	    && (! current_function_decl					\
-		|| ! UNIQUE_SECTION_P (current_function_decl)))		\
-	  {								\
-	    SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1;	\
-	    mips_string_length += TREE_STRING_LENGTH (DECL);		\
-	  }								\
-      }									\
-									\
-    if (TARGET_EMBEDDED_DATA						\
-	&& (TREE_CODE (DECL) == VAR_DECL				\
-	    && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL))	\
-	    && (!DECL_INITIAL (DECL)					\
-		|| TREE_CONSTANT (DECL_INITIAL (DECL))))		\
-      {									\
-	SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0;		\
-      }									\
-									\
-    else if (TARGET_EMBEDDED_PIC)					\
-      {									\
-        if (TREE_CODE (DECL) == VAR_DECL)				\
-	  SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;		\
-        else if (TREE_CODE (DECL) == FUNCTION_DECL)			\
-	  SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0;		\
-	else if (TREE_CODE (DECL) == STRING_CST				\
-		 && ! flag_writable_strings)				\
-	  SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0;		\
-        else								\
-	  SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1;		\
-      }									\
-									\
-    else if (TREE_CODE (DECL) == VAR_DECL				\
-             && DECL_SECTION_NAME (DECL) != NULL_TREE                   \
-             && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
-                              ".sdata")                                 \
-                || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
-                              ".sbss")))                                \
-      {									\
-        SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;		\
-      }									\
-									\
-    else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL)		\
-      {									\
-	int size = int_size_in_bytes (TREE_TYPE (DECL));		\
-									\
-	if (size > 0 && size <= mips_section_threshold)			\
-	  SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;		\
-      }									\
-									\
-    else if (HALF_PIC_P ())						\
-      {									\
-        HALF_PIC_ENCODE (DECL);						\
-      }									\
-  }									\
-while (0)
-
-/* The mips16 wants the constant pool to be after the function,
-   because the PC relative load instructions use unsigned offsets.  */
-
-#define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
-
-#define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE)	\
-  mips_string_length = 0;
-
-#if 0
-/* In mips16 mode, put most string constants after the function.  */
-#define CONSTANT_AFTER_FUNCTION_P(tree)				\
-  (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
-#endif
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.
-   ??? Using HImode in mips16 mode can cause overflow.  However, the
-   overflow is no more likely than the overflow in a branch
-   instruction.  Large functions can currently break in both ways.  */
-#define CASE_VECTOR_MODE \
-  (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#ifndef DEFAULT_SIGNED_CHAR
-#define DEFAULT_SIGNED_CHAR 1
-#endif
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX (TARGET_64BIT ? 8 : 4)
-#define MAX_MOVE_MAX 8
-
-/* Define this macro as a C expression which is nonzero if
-   accessing less than a word of memory (i.e. a `char' or a
-   `short') is no faster than accessing a word of memory, i.e., if
-   such access require more than one instruction or if there is no
-   difference in cost between byte and (aligned) word loads.
-
-   On RISC machines, it tends to generate better code to define
-   this as 1, since it avoids making a QI or HI mode register.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-#define SLOW_ZERO_EXTEND
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
-   few bits. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-/* In 64 bit mode, 32 bit instructions require that register values be properly
-   sign-extended to 64 bits.  As a result, a truncate is not a no-op if it
-   converts a value >32 bits to a value <32 bits.  */
-/* ??? This results in inefficient code for 64 bit to 32 conversions.
-   Something needs to be done about this.  Perhaps not use any 32 bit
-   instructions?  Perhaps use PROMOTE_MODE?  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
-  (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-
-#ifndef Pmode
-#define Pmode ((enum machine_mode)(TARGET_LONG64 ? DImode : SImode))
-#endif
-
-/* A function address in a call instruction
-   is a word address (for indexing purposes)
-   so give the MEM rtx a words's mode.  */
-
-#define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
-
-/* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
-   memset, instead of the BSD functions bcopy and bzero.  */
-
-#if defined(MIPS_SYSV) || defined(OSF_OS)
-#define TARGET_MEM_FUNCTIONS
-#endif
-
-
-/* A part of a C `switch' statement that describes the relative
-   costs of constant RTL expressions.  It must contain `case'
-   labels for expression codes `const_int', `const', `symbol_ref',
-   `label_ref' and `const_double'.  Each case must ultimately reach
-   a `return' statement to return the relative cost of the use of
-   that kind of constant value in an expression.  The cost may
-   depend on the precise value of the constant, which is available
-   for examination in X.
-
-   CODE is the expression code--redundant, since it can be obtained
-   with `GET_CODE (X)'.  */
-
-#define CONST_COSTS(X,CODE,OUTER_CODE)					\
-  case CONST_INT:							\
-    if (! TARGET_MIPS16)						\
-      {									\
-	/* Always return 0, since we don't have different sized		\
-	   instructions, hence different costs according to Richard	\
-	   Kenner */							\
-	return 0;							\
-      }									\
-    if ((OUTER_CODE) == SET)						\
-      {									\
-	if (INTVAL (X) >= 0 && INTVAL (X) < 0x100)			\
-	  return 0;							\
-	else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000)		\
-		 || (INTVAL (X) < 0 && INTVAL (X) > -0x100))		\
-	  return COSTS_N_INSNS (1);					\
-	else								\
-	  return COSTS_N_INSNS (2);					\
-      }									\
-    /* A PLUS could be an address.  We don't want to force an address	\
-       to use a register, so accept any signed 16 bit value without	\
-       complaint.  */							\
-    if ((OUTER_CODE) == PLUS						\
-	&& INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000)		\
-      return 0;								\
-    /* A number between 1 and 8 inclusive is efficient for a shift.	\
-       Otherwise, we will need an extended instruction.  */		\
-    if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT		\
-	|| (OUTER_CODE) == LSHIFTRT)					\
-      {									\
-	if (INTVAL (X) >= 1 && INTVAL (X) <= 8)				\
-	  return 0;							\
-	return COSTS_N_INSNS (1);					\
-      }									\
-    /* We can use cmpi for an xor with an unsigned 16 bit value.  */	\
-    if ((OUTER_CODE) == XOR						\
-	&& INTVAL (X) >= 0 && INTVAL (X) < 0x10000)			\
-      return 0;								\
-    /* We may be able to use slt or sltu for a comparison with a	\
-       signed 16 bit value.  (The boundary conditions aren't quite	\
-       right, but this is just a heuristic anyhow.)  */			\
-    if (((OUTER_CODE) == LT || (OUTER_CODE) == LE			\
-	 || (OUTER_CODE) == GE || (OUTER_CODE) == GT			\
-	 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU			\
-	 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU)			\
-	&& INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000)		\
-      return 0;								\
-    /* Equality comparisons with 0 are cheap.  */			\
-    if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE)			\
-	&& INTVAL (X) == 0)						\
-      return 0;								\
-									\
-    /* Otherwise, work out the cost to load the value into a		\
-       register.  */							\
-    if (INTVAL (X) >= 0 && INTVAL (X) < 0x100)				\
-      return COSTS_N_INSNS (1);						\
-    else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000)			\
-	     || (INTVAL (X) < 0 && INTVAL (X) > -0x100))		\
-      return COSTS_N_INSNS (2);						\
-    else								\
-      return COSTS_N_INSNS (3);						\
-									\
-  case LABEL_REF:							\
-    return COSTS_N_INSNS (2);						\
-									\
-  case CONST:								\
-    {									\
-      rtx offset = const0_rtx;						\
-      rtx symref = eliminate_constant_term (XEXP (X, 0), &offset);	\
-									\
-      if (TARGET_MIPS16 && mips16_gp_offset_p (X))			\
-	{								\
-	  /* Treat this like a signed 16 bit CONST_INT.  */		\
-	  if ((OUTER_CODE) == PLUS)					\
-	    return 0;							\
-	  else if ((OUTER_CODE) == SET)					\
-	    return COSTS_N_INSNS (1);					\
-	  else								\
-	    return COSTS_N_INSNS (2);					\
-	}								\
-									\
-      if (GET_CODE (symref) == LABEL_REF)				\
-	return COSTS_N_INSNS (2);					\
-									\
-      if (GET_CODE (symref) != SYMBOL_REF)				\
-	return COSTS_N_INSNS (4);					\
-									\
-      /* let's be paranoid.... */					\
-      if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767)		\
-	return COSTS_N_INSNS (2);					\
-									\
-      return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2);		\
-    }									\
-									\
-  case SYMBOL_REF:							\
-    return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2);			\
-									\
-  case CONST_DOUBLE:							\
-    {									\
-      rtx high, low;							\
-      if (TARGET_MIPS16)						\
-	return COSTS_N_INSNS (4);					\
-      split_double (X, &high, &low);					\
-      return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high))	\
-			     || low == CONST0_RTX (GET_MODE (low)))	\
-			    ? 2 : 4);					\
-    }
-
-/* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
-   This can be used, for example, to indicate how costly a multiply
-   instruction is.  In writing this macro, you can use the construct
-   `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
-
-   This macro is optional; do not define it if the default cost
-   assumptions are adequate for the target machine.
-
-   If -mdebugd is used, change the multiply cost to 2, so multiply by
-   a constant isn't converted to a series of shifts.  This helps
-   strength reduction, and also makes it easier to identify what the
-   compiler is doing.  */
-
-/* ??? Fix this to be right for the R8000.  */
-#define RTX_COSTS(X,CODE,OUTER_CODE)					\
-  case MEM:								\
-    {									\
-      int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
-      if (simple_memory_operand (X, GET_MODE (X)))			\
-	return COSTS_N_INSNS (num_words);				\
-									\
-      return COSTS_N_INSNS (2*num_words);				\
-    }									\
-									\
-  case FFS:								\
-    return COSTS_N_INSNS (6);						\
-									\
-  case NOT:								\
-    return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
-									\
-  case AND:								\
-  case IOR:								\
-  case XOR:								\
-    if (GET_MODE (X) == DImode && !TARGET_64BIT)			\
-      return COSTS_N_INSNS (2);						\
-									\
-    break;								\
-									\
-  case ASHIFT:								\
-  case ASHIFTRT:							\
-  case LSHIFTRT:							\
-    if (GET_MODE (X) == DImode && !TARGET_64BIT)			\
-      return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
-									\
-    break;								\
-									\
-  case ABS:								\
-    {									\
-      enum machine_mode xmode = GET_MODE (X);				\
-      if (xmode == SFmode || xmode == DFmode)				\
-	return COSTS_N_INSNS (1);					\
-									\
-      return COSTS_N_INSNS (4);						\
-    }									\
-									\
-  case PLUS:								\
-  case MINUS:								\
-    {									\
-      enum machine_mode xmode = GET_MODE (X);				\
-      if (xmode == SFmode || xmode == DFmode)				\
-	{								\
-	  if (mips_cpu == PROCESSOR_R3000				\
-              || mips_cpu == PROCESSOR_R3900)				\
-	    return COSTS_N_INSNS (2);					\
-	  else if (mips_cpu == PROCESSOR_R6000)				\
-	    return COSTS_N_INSNS (3);					\
-	  else								\
-	    return COSTS_N_INSNS (6);					\
-	}								\
-									\
-      if (xmode == DImode && !TARGET_64BIT)				\
-	return COSTS_N_INSNS (4);					\
-									\
-      break;								\
-    }									\
-									\
-  case NEG:								\
-    if (GET_MODE (X) == DImode && !TARGET_64BIT)			\
-      return 4;								\
-									\
-    break;								\
-									\
-  case MULT:								\
-    {									\
-      enum machine_mode xmode = GET_MODE (X);				\
-      if (xmode == SFmode)						\
-	{								\
-	  if (mips_cpu == PROCESSOR_R3000				\
-	      || mips_cpu == PROCESSOR_R3900				\
-	      || mips_cpu == PROCESSOR_R5000)				\
-	    return COSTS_N_INSNS (4);					\
-	  else if (mips_cpu == PROCESSOR_R6000)				\
-	    return COSTS_N_INSNS (5);					\
-	  else								\
-	    return COSTS_N_INSNS (7);					\
-	}								\
-									\
-      if (xmode == DFmode)						\
-	{								\
-	  if (mips_cpu == PROCESSOR_R3000				\
-	      || mips_cpu == PROCESSOR_R3900				\
-	      || mips_cpu == PROCESSOR_R5000)				\
-	    return COSTS_N_INSNS (5);					\
-	  else if (mips_cpu == PROCESSOR_R6000)				\
-	    return COSTS_N_INSNS (6);					\
-	  else								\
-	    return COSTS_N_INSNS (8);					\
-	}								\
-									\
-      if (mips_cpu == PROCESSOR_R3000)					\
-	return COSTS_N_INSNS (12);					\
-      else if (mips_cpu == PROCESSOR_R3900)				\
-	return COSTS_N_INSNS (2);					\
-      else if (mips_cpu == PROCESSOR_R6000)				\
-	return COSTS_N_INSNS (17);					\
-      else if (mips_cpu == PROCESSOR_R5000)				\
-	return COSTS_N_INSNS (5);					\
-      else								\
-	return COSTS_N_INSNS (10);					\
-    }									\
-									\
-  case DIV:								\
-  case MOD:								\
-    {									\
-      enum machine_mode xmode = GET_MODE (X);				\
-      if (xmode == SFmode)						\
-	{								\
-	  if (mips_cpu == PROCESSOR_R3000				\
-              || mips_cpu == PROCESSOR_R3900)				\
-	    return COSTS_N_INSNS (12);					\
-	  else if (mips_cpu == PROCESSOR_R6000)				\
-	    return COSTS_N_INSNS (15);					\
-	  else								\
-	    return COSTS_N_INSNS (23);					\
-	}								\
-									\
-      if (xmode == DFmode)						\
-	{								\
-	  if (mips_cpu == PROCESSOR_R3000				\
-              || mips_cpu == PROCESSOR_R3900)				\
-	    return COSTS_N_INSNS (19);					\
-	  else if (mips_cpu == PROCESSOR_R6000)				\
-	    return COSTS_N_INSNS (16);					\
-	  else								\
-	    return COSTS_N_INSNS (36);					\
-	}								\
-    }									\
-    /* fall through */							\
-									\
-  case UDIV:								\
-  case UMOD:								\
-    if (mips_cpu == PROCESSOR_R3000					\
-        || mips_cpu == PROCESSOR_R3900)					\
-      return COSTS_N_INSNS (35);					\
-    else if (mips_cpu == PROCESSOR_R6000)				\
-      return COSTS_N_INSNS (38);					\
-    else if (mips_cpu == PROCESSOR_R5000)				\
-      return COSTS_N_INSNS (36);					\
-    else								\
-      return COSTS_N_INSNS (69);					\
-									\
-  case SIGN_EXTEND:							\
-    /* A sign extend from SImode to DImode in 64 bit mode is often	\
-       zero instructions, because the result can often be used		\
-       directly by another instruction; we'll call it one.  */		\
-    if (TARGET_64BIT && GET_MODE (X) == DImode				\
-	&& GET_MODE (XEXP (X, 0)) == SImode)				\
-      return COSTS_N_INSNS (1);						\
-    else								\
-      return COSTS_N_INSNS (2);						\
-									\
-  case ZERO_EXTEND:							\
-    if (TARGET_64BIT && GET_MODE (X) == DImode				\
-	&& GET_MODE (XEXP (X, 0)) == SImode)				\
-      return COSTS_N_INSNS (2);						\
-    else								\
-      return COSTS_N_INSNS (1);
-
-/* An expression giving the cost of an addressing mode that
-   contains ADDRESS.  If not defined, the cost is computed from the
-   form of the ADDRESS expression and the `CONST_COSTS' values.
-
-   For most CISC machines, the default cost is a good approximation
-   of the true cost of the addressing mode.  However, on RISC
-   machines, all instructions normally have the same length and
-   execution time.  Hence all addresses will have equal costs.
-
-   In cases where more than one form of an address is known, the
-   form with the lowest cost will be used.  If multiple forms have
-   the same, lowest, cost, the one that is the most complex will be
-   used.
-
-   For example, suppose an address that is equal to the sum of a
-   register and a constant is used twice in the same basic block. 
-   When this macro is not defined, the address will be computed in
-   a register and memory references will be indirect through that
-   register.  On machines where the cost of the addressing mode
-   containing the sum is no higher than that of a simple indirect
-   reference, this will produce an additional instruction and
-   possibly require an additional register.  Proper specification
-   of this macro eliminates this overhead for such machines.
-
-   Similar use of this macro is made in strength reduction of loops.
-
-   ADDRESS need not be valid as an address.  In such a case, the
-   cost is not relevant and can be any value; invalid addresses
-   need not be assigned a different cost.
-
-   On machines where an address involving more than one register is
-   as cheap as an address computation involving only one register,
-   defining `ADDRESS_COST' to reflect this can cause two registers
-   to be live over a region of code where only one would have been
-   if `ADDRESS_COST' were not defined in that manner.  This effect
-   should be considered in the definition of this macro. 
-   Equivalent costs should probably only be given to addresses with
-   different numbers of registers on machines with lots of registers.
-
-   This macro will normally either not be defined or be defined as
-   a constant. */
-
-#define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
-
-/* A C expression for the cost of moving data from a register in
-   class FROM to one in class TO.  The classes are expressed using
-   the enumeration values such as `GENERAL_REGS'.  A value of 2 is
-   the default; other values are interpreted relative to that.
-
-   It is not required that the cost always equal 2 when FROM is the
-   same as TO; on some machines it is expensive to move between
-   registers if they are not general registers.
-
-   If reload sees an insn consisting of a single `set' between two
-   hard registers, and if `REGISTER_MOVE_COST' applied to their
-   classes returns a value of 2, reload does not check to ensure
-   that the constraints of the insn are met.  Setting a cost of
-   other than 2 will allow reload to verify that the constraints are
-   met.  You should do this if the `movM' pattern's constraints do
-   not allow such copying.  */
-
-#define REGISTER_MOVE_COST(FROM, TO)	\
-  ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2			\
-   : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2			\
-   : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2			\
-   : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2			\
-   : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
-   : (FROM) == FP_REGS && (TO) == FP_REGS ? 2				\
-   : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4			\
-   : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4			\
-   : (((FROM) == HI_REG || (FROM) == LO_REG				\
-       || (FROM) == MD_REGS || (FROM) == HILO_REG)			\
-      && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 12		\
-   : (((FROM) == HI_REG || (FROM) == LO_REG				\
-       || (FROM) == MD_REGS || (FROM) == HILO_REG)			\
-      && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6)		\
-   : (((TO) == HI_REG || (TO) == LO_REG					\
-       || (TO) == MD_REGS || (TO) == HILO_REG)				\
-      && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6)		\
-   : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4			\
-   : (FROM) == FP_REGS && (TO) == ST_REGS ? 8				\
-   : 12)
-
-/* ??? Fix this to be right for the R8000.  */
-#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
-  (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
-   + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
-
-/* Define if copies to/from condition code registers should be avoided.
-
-   This is needed for the MIPS because reload_outcc is not complete;
-   it needs to handle cases where the source is a general or another
-   condition code register.  */
-#define AVOID_CCMODE_COPIES
-
-/* A C expression for the cost of a branch instruction.  A value of
-   1 is the default; other values are interpreted relative to that.  */
-
-/* ??? Fix this to be right for the R8000.  */
-#define BRANCH_COST							\
-  ((! TARGET_MIPS16							\
-    && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000))	\
-   ? 2 : 1)
-
-/* A C statement (sans semicolon) to update the integer variable COST
-   based on the relationship between INSN that is dependent on
-   DEP_INSN through the dependence LINK.  The default is to make no
-   adjustment to COST.  On the MIPS, ignore the cost of anti- and
-   output-dependencies.  */
-
-#define ADJUST_COST(INSN,LINK,DEP_INSN,COST)				\
-  if (REG_NOTE_KIND (LINK) != 0)					\
-    (COST) = 0; /* Anti or output dependence.  */
-
-#define ISSUE_RATE (TARGET_MIPS5400 ? 2 : 1) /* CYGNUS LOCAL vr5400/raeburn */
-
-/* Optionally define this if you have added predicates to
-   `MACHINE.c'.  This macro is called within an initializer of an
-   array of structures.  The first field in the structure is the
-   name of a predicate and the second field is an array of rtl
-   codes.  For each predicate, list all rtl codes that can be in
-   expressions matched by the predicate.  The list should have a
-   trailing comma.  Here is an example of two entries in the list
-   for a typical RISC machine:
-
-   #define PREDICATE_CODES \
-     {"gen_reg_rtx_operand", {SUBREG, REG}},  \
-     {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
-
-   Defining this macro does not affect the generated code (however,
-   incorrect definitions that omit an rtl code that may be matched
-   by the predicate can cause the compiler to malfunction). 
-   Instead, it allows the table built by `genrecog' to be more
-   compact and efficient, thus speeding up the compiler.  The most
-   important predicates to include in the list specified by this
-   macro are thoses used in the most insn patterns.  */
-
-#define PREDICATE_CODES							\
-  {"uns_arith_operand",		{ REG, CONST_INT, SUBREG }},		\
-  {"arith_operand",		{ REG, CONST_INT, SUBREG }},		\
-  {"arith32_operand",		{ REG, CONST_INT, SUBREG }},		\
-  {"reg_or_0_operand",		{ REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
-  {"true_reg_or_0_operand",	{ REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
-  {"small_int",			{ CONST_INT }},				\
-  {"large_int",			{ CONST_INT }},				\
-  {"mips_const_double_ok",	{ CONST_DOUBLE }},			\
-  {"const_float_1_operand",	{ CONST_DOUBLE }},			\
-  {"simple_memory_operand",	{ MEM, SUBREG }},			\
-  {"equality_op",		{ EQ, NE }},				\
-  {"cmp_op",			{ EQ, NE, GT, GE, GTU, GEU, LT, LE,	\
-				  LTU, LEU }},				\
-  {"pc_or_label_operand",	{ PC, LABEL_REF }},			\
-  {"call_insn_operand",		{ CONST_INT, CONST, SYMBOL_REF, REG}},	\
-  {"move_operand", 		{ CONST_INT, CONST_DOUBLE, CONST,	\
-				  SYMBOL_REF, LABEL_REF, SUBREG,	\
-				  REG, MEM}},				\
-  {"movdi_operand",		{ CONST_INT, CONST_DOUBLE, CONST,	\
-				  SYMBOL_REF, LABEL_REF, SUBREG, REG,	\
-				  MEM, SIGN_EXTEND }},			\
-  {"se_register_operand",	{ SUBREG, REG, SIGN_EXTEND }},		\
-  {"se_reg_or_0_operand",	{ REG, CONST_INT, CONST_DOUBLE, SUBREG,	\
-				  SIGN_EXTEND }},			\
-  {"se_uns_arith_operand",	{ REG, CONST_INT, SUBREG,		\
-				  SIGN_EXTEND }},			\
-  {"se_arith_operand",		{ REG, CONST_INT, SUBREG,		\
-				  SIGN_EXTEND }},			\
-  {"se_nonmemory_operand",	{ CONST_INT, CONST_DOUBLE, CONST,	\
-				  SYMBOL_REF, LABEL_REF, SUBREG,	\
-				  REG, SIGN_EXTEND }},			\
-  {"se_nonimmediate_operand",   { SUBREG, REG, MEM, SIGN_EXTEND }},	\
-  {"consttable_operand",	{ LABEL_REF, SYMBOL_REF, CONST_INT,	\
-				  CONST_DOUBLE, CONST }},		\
-  {"extend_operator",           { SIGN_EXTEND, ZERO_EXTEND }},          \
-  {"highpart_shift_operator",   { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
-
-
-
-/* If defined, a C statement to be executed just prior to the
-   output of assembler code for INSN, to modify the extracted
-   operands so they will be output differently.
-
-   Here the argument OPVEC is the vector containing the operands
-   extracted from INSN, and NOPERANDS is the number of elements of
-   the vector which contain meaningful data for this insn.  The
-   contents of this vector are what will be used to convert the
-   insn template into assembler code, so you can change the
-   assembler output by changing the contents of the vector.
-
-   We use it to check if the current insn needs a nop in front of it
-   because of load delays, and also to update the delay slot
-   statistics.  */
-
-#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)			\
-  final_prescan_insn (INSN, OPVEC, NOPERANDS)
-
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.
-   If we are optimizing to use the global pointer, create a temporary
-   file to hold all of the text stuff, and write it out to the end.
-   This is needed because the MIPS assembler is evidently one pass,
-   and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
-   declaration when the code is processed, it generates a two
-   instruction sequence.  */
-
-#define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON " #APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF " #NO_APP\n"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).
-
-   In order to support the two different conventions for register names,
-   we use the name of a table set up in mips.c, which is overwritten
-   if -mrnames is used.  */
-
-#define REGISTER_NAMES							\
-{									\
-  &mips_reg_names[ 0][0],						\
-  &mips_reg_names[ 1][0],						\
-  &mips_reg_names[ 2][0],						\
-  &mips_reg_names[ 3][0],						\
-  &mips_reg_names[ 4][0],						\
-  &mips_reg_names[ 5][0],						\
-  &mips_reg_names[ 6][0],						\
-  &mips_reg_names[ 7][0],						\
-  &mips_reg_names[ 8][0],						\
-  &mips_reg_names[ 9][0],						\
-  &mips_reg_names[10][0],						\
-  &mips_reg_names[11][0],						\
-  &mips_reg_names[12][0],						\
-  &mips_reg_names[13][0],						\
-  &mips_reg_names[14][0],						\
-  &mips_reg_names[15][0],						\
-  &mips_reg_names[16][0],						\
-  &mips_reg_names[17][0],						\
-  &mips_reg_names[18][0],						\
-  &mips_reg_names[19][0],						\
-  &mips_reg_names[20][0],						\
-  &mips_reg_names[21][0],						\
-  &mips_reg_names[22][0],						\
-  &mips_reg_names[23][0],						\
-  &mips_reg_names[24][0],						\
-  &mips_reg_names[25][0],						\
-  &mips_reg_names[26][0],						\
-  &mips_reg_names[27][0],						\
-  &mips_reg_names[28][0],						\
-  &mips_reg_names[29][0],						\
-  &mips_reg_names[30][0],						\
-  &mips_reg_names[31][0],						\
-  &mips_reg_names[32][0],						\
-  &mips_reg_names[33][0],						\
-  &mips_reg_names[34][0],						\
-  &mips_reg_names[35][0],						\
-  &mips_reg_names[36][0],						\
-  &mips_reg_names[37][0],						\
-  &mips_reg_names[38][0],						\
-  &mips_reg_names[39][0],						\
-  &mips_reg_names[40][0],						\
-  &mips_reg_names[41][0],						\
-  &mips_reg_names[42][0],						\
-  &mips_reg_names[43][0],						\
-  &mips_reg_names[44][0],						\
-  &mips_reg_names[45][0],						\
-  &mips_reg_names[46][0],						\
-  &mips_reg_names[47][0],						\
-  &mips_reg_names[48][0],						\
-  &mips_reg_names[49][0],						\
-  &mips_reg_names[50][0],						\
-  &mips_reg_names[51][0],						\
-  &mips_reg_names[52][0],						\
-  &mips_reg_names[53][0],						\
-  &mips_reg_names[54][0],						\
-  &mips_reg_names[55][0],						\
-  &mips_reg_names[56][0],						\
-  &mips_reg_names[57][0],						\
-  &mips_reg_names[58][0],						\
-  &mips_reg_names[59][0],						\
-  &mips_reg_names[60][0],						\
-  &mips_reg_names[61][0],						\
-  &mips_reg_names[62][0],						\
-  &mips_reg_names[63][0],						\
-  &mips_reg_names[64][0],						\
-  &mips_reg_names[65][0],						\
-  &mips_reg_names[66][0],						\
-  &mips_reg_names[67][0],						\
-  &mips_reg_names[68][0],						\
-  &mips_reg_names[69][0],						\
-  &mips_reg_names[70][0],						\
-  &mips_reg_names[71][0],						\
-  &mips_reg_names[72][0],						\
-  &mips_reg_names[73][0],						\
-  &mips_reg_names[74][0],						\
-  &mips_reg_names[75][0],						\
-}
-
-/* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
-   So define this for it.  */
-#define DEBUG_REGISTER_NAMES						\
-{									\
-  "$0",   "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",		\
-  "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",		\
-  "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",		\
-  "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "$fp",   "ra",	\
-  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",	\
-  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",	\
-  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",	\
-  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",	\
-  "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",	\
-  "$fcc5","$fcc6","$fcc7","$rap"					\
-}
-
-/* If defined, a C initializer for an array of structures
-   containing a name and a register number.  This macro defines
-   additional names for hard registers, thus allowing the `asm'
-   option in declarations to refer to registers using alternate
-   names.
-
-   We define both names for the integer registers here.  */
-
-#define ADDITIONAL_REGISTER_NAMES					\
-{									\
-  { "$0",	 0 + GP_REG_FIRST },					\
-  { "$1",	 1 + GP_REG_FIRST },					\
-  { "$2",	 2 + GP_REG_FIRST },					\
-  { "$3",	 3 + GP_REG_FIRST },					\
-  { "$4",	 4 + GP_REG_FIRST },					\
-  { "$5",	 5 + GP_REG_FIRST },					\
-  { "$6",	 6 + GP_REG_FIRST },					\
-  { "$7",	 7 + GP_REG_FIRST },					\
-  { "$8",	 8 + GP_REG_FIRST },					\
-  { "$9",	 9 + GP_REG_FIRST },					\
-  { "$10",	10 + GP_REG_FIRST },					\
-  { "$11",	11 + GP_REG_FIRST },					\
-  { "$12",	12 + GP_REG_FIRST },					\
-  { "$13",	13 + GP_REG_FIRST },					\
-  { "$14",	14 + GP_REG_FIRST },					\
-  { "$15",	15 + GP_REG_FIRST },					\
-  { "$16",	16 + GP_REG_FIRST },					\
-  { "$17",	17 + GP_REG_FIRST },					\
-  { "$18",	18 + GP_REG_FIRST },					\
-  { "$19",	19 + GP_REG_FIRST },					\
-  { "$20",	20 + GP_REG_FIRST },					\
-  { "$21",	21 + GP_REG_FIRST },					\
-  { "$22",	22 + GP_REG_FIRST },					\
-  { "$23",	23 + GP_REG_FIRST },					\
-  { "$24",	24 + GP_REG_FIRST },					\
-  { "$25",	25 + GP_REG_FIRST },					\
-  { "$26",	26 + GP_REG_FIRST },					\
-  { "$27",	27 + GP_REG_FIRST },					\
-  { "$28",	28 + GP_REG_FIRST },					\
-  { "$29",	29 + GP_REG_FIRST },					\
-  { "$30",	30 + GP_REG_FIRST },					\
-  { "$31",	31 + GP_REG_FIRST },					\
-  { "$sp",	29 + GP_REG_FIRST },					\
-  { "$fp",	30 + GP_REG_FIRST },					\
-  { "at",	 1 + GP_REG_FIRST },					\
-  { "v0",	 2 + GP_REG_FIRST },					\
-  { "v1",	 3 + GP_REG_FIRST },					\
-  { "a0",	 4 + GP_REG_FIRST },					\
-  { "a1",	 5 + GP_REG_FIRST },					\
-  { "a2",	 6 + GP_REG_FIRST },					\
-  { "a3",	 7 + GP_REG_FIRST },					\
-  { "t0",	 8 + GP_REG_FIRST },					\
-  { "t1",	 9 + GP_REG_FIRST },					\
-  { "t2",	10 + GP_REG_FIRST },					\
-  { "t3",	11 + GP_REG_FIRST },					\
-  { "t4",	12 + GP_REG_FIRST },					\
-  { "t5",	13 + GP_REG_FIRST },					\
-  { "t6",	14 + GP_REG_FIRST },					\
-  { "t7",	15 + GP_REG_FIRST },					\
-  { "s0",	16 + GP_REG_FIRST },					\
-  { "s1",	17 + GP_REG_FIRST },					\
-  { "s2",	18 + GP_REG_FIRST },					\
-  { "s3",	19 + GP_REG_FIRST },					\
-  { "s4",	20 + GP_REG_FIRST },					\
-  { "s5",	21 + GP_REG_FIRST },					\
-  { "s6",	22 + GP_REG_FIRST },					\
-  { "s7",	23 + GP_REG_FIRST },					\
-  { "t8",	24 + GP_REG_FIRST },					\
-  { "t9",	25 + GP_REG_FIRST },					\
-  { "k0",	26 + GP_REG_FIRST },					\
-  { "k1",	27 + GP_REG_FIRST },					\
-  { "gp",	28 + GP_REG_FIRST },					\
-  { "sp",	29 + GP_REG_FIRST },					\
-  { "fp",	30 + GP_REG_FIRST },					\
-  { "ra",	31 + GP_REG_FIRST },					\
-  { "$sp",	29 + GP_REG_FIRST },					\
-  { "$fp",	30 + GP_REG_FIRST }					\
-}
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL	007
-#define TARGET_BS	010
-#define TARGET_TAB	011
-#define TARGET_NEWLINE	012
-#define TARGET_VT	013
-#define TARGET_FF	014
-#define TARGET_CR	015
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand X.  X is an RTL
-   expression.
-
-   CODE is a value that can be used to specify one of several ways
-   of printing the operand.  It is used when identical operands
-   must be printed differently depending on the context.  CODE
-   comes from the `%' specification that was used to request
-   printing of the operand.  If the specification was just `%DIGIT'
-   then CODE is 0; if the specification was `%LTR DIGIT' then CODE
-   is the ASCII code for LTR.
-
-   If X is a register, this macro should print the register's name.
-   The names can be found in an array `reg_names' whose type is
-   `char *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
-
-   When the machine description has a specification `%PUNCT' (a `%'
-   followed by a punctuation character), this macro is called with
-   a null pointer for X and the punctuation character for CODE.
-
-   See mips.c for the MIPS specific codes.  */
-
-#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
-
-/* A C expression which evaluates to true if CODE is a valid
-   punctuation character for use in the `PRINT_OPERAND' macro.  If
-   `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
-   punctuation characters (except for the standard one, `%') are
-   used in this way.  */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
-
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand that is a memory
-   reference whose address is ADDR.  ADDR is an RTL expression.
-
-   On some machines, the syntax for a symbolic address depends on
-   the section that the address refers to.  On these machines,
-   define the macro `ENCODE_SECTION_INFO' to store the information
-   into the `symbol_ref', and then check for it here.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
-
-
-/* A C statement, to be executed after all slot-filler instructions
-   have been output.  If necessary, call `dbr_sequence_length' to
-   determine the number of slots filled in a sequence (zero if not
-   currently outputting a sequence), to decide how many no-ops to
-   output, or whatever.
-
-   Don't define this macro if it has nothing to do, but it is
-   helpful in reading assembly output if the extent of the delay
-   sequence is made explicit (e.g. with white space).
-
-   Note that output routines for instructions with delay slots must
-   be prepared to deal with not being output as part of a sequence
-   (i.e.  when the scheduling pass is not run, or when no slot
-   fillers could be found.)  The variable `final_sequence' is null
-   when not processing a sequence, otherwise it contains the
-   `sequence' rtx being output.  */
-
-#define DBR_OUTPUT_SEQEND(STREAM)					\
-do									\
-  {									\
-    if (set_nomacro > 0 && --set_nomacro == 0)				\
-      fputs ("\t.set\tmacro\n", STREAM);				\
-									\
-    if (set_noreorder > 0 && --set_noreorder == 0)			\
-      fputs ("\t.set\treorder\n", STREAM);				\
-									\
-    dslots_jump_filled++;						\
-    fputs ("\n", STREAM);						\
-  }									\
-while (0)
-
-
-/* How to tell the debugger about changes of source files.  Note, the
-   mips ECOFF format cannot deal with changes of files inside of
-   functions, which means the output of parser generators like bison
-   is generally not debuggable without using the -l switch.  Lose,
-   lose, lose.  Silicon graphics seems to want all .file's hardwired
-   to 1.  */
-
-#ifndef SET_FILE_NUMBER
-#define SET_FILE_NUMBER() ++num_source_filenames
-#endif
-
-#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME)			\
-  mips_output_filename (STREAM, NAME)
-
-/* This is defined so that it can be overridden in iris6.h.  */
-#define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
-do								\
-  {								\
-    fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES);	\
-    output_quoted_string (STREAM, NAME);			\
-    fputs ("\n", STREAM);					\
-  }								\
-while (0)
-
-/* This is how to output a note the debugger telling it the line number
-   to which the following sequence of instructions corresponds.
-   Silicon graphics puts a label after each .loc.  */
-
-#ifndef LABEL_AFTER_LOC
-#define LABEL_AFTER_LOC(STREAM)
-#endif
-
-#define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE)				\
-  mips_output_lineno (STREAM, LINE)
-
-/* The MIPS implementation uses some labels for its own purpose.  The
-   following lists what labels are created, and are all formed by the
-   pattern $L[a-z].*.  The machine independent portion of GCC creates
-   labels matching:  $L[A-Z][0-9]+ and $L[0-9]+.
-
-	LM[0-9]+	Silicon Graphics/ECOFF stabs label before each stmt.
-	$Lb[0-9]+	Begin blocks for MIPS debug support
-	$Lc[0-9]+	Label for use in s<xx> operation.
-	$Le[0-9]+	End blocks for MIPS debug support
-	$Lp\..+		Half-pic labels. */
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.
-
-   If we are optimizing the gp, remember that this label has been put
-   out, so we know not to emit an .extern for it in mips_asm_file_end.
-   We use one of the common bits in the IDENTIFIER tree node for this,
-   since those bits seem to be unused, and we don't have any method
-   of getting the decl nodes from the name.  */
-
-#define ASM_OUTPUT_LABEL(STREAM,NAME)					\
-do {									\
-  assemble_name (STREAM, NAME);						\
-  fputs (":\n", STREAM);						\
-} while (0)
-
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   STREAM any text necessary for declaring the name NAME of an
-   initialized variable which is being defined.  This macro must
-   output the label definition (perhaps using `ASM_OUTPUT_LABEL'). 
-   The argument DECL is the `VAR_DECL' tree node representing the
-   variable.
-
-   If this macro is not defined, then the variable name is defined
-   in the usual manner as a label (by means of `ASM_OUTPUT_LABEL').  */
-
-#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL)			\
-do									\
- {									\
-   mips_declare_object (STREAM, NAME, "", ":\n", 0);			\
-   HALF_PIC_DECLARE (NAME);						\
- }									\
-while (0)
-
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(STREAM,NAME)				\
-  do {									\
-    fputs ("\t.globl\t", STREAM);					\
-    assemble_name (STREAM, NAME);					\
-    fputs ("\n", STREAM);						\
-  } while (0)
-
-/* This says how to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED)			\
-  mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
-
-/* This says how to define a local common symbol (ie, not visible to
-   linker).  */
-
-#define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED)			\
-  mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
-
-
-/* This says how to output an external.  It would be possible not to
-   output anything and let undefined symbol become external. However
-   the assembler uses length information on externals to allocate in
-   data/sdata bss/sbss, thereby saving exec time.  */
-
-#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
-  mips_output_external(STREAM,DECL,NAME)
-
-/* This says what to print at the end of the assembly file */
-#define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
-
-
-/* This is how to declare a function name.  The actual work of
-   emitting the label is moved to function_prologue, so that we can
-   get the line number correctly emitted before the .ent directive,
-   and after any .file directives.
-
-   Also, switch files if we are optimizing the global pointer.  */
-
-#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)			\
-{									\
-  extern FILE *asm_out_text_file;					\
-  if (TARGET_GP_OPT && ! TARGET_MIPS16)					\
-    {									\
-      STREAM = asm_out_text_file;					\
-      /* ??? text_section gets called too soon.  If the previous	\
-	 function is in a special section and we're not, we have	\
-	 to switch back to the text section.  We can't call		\
-	 text_section again as gcc thinks we're already there.  */	\
-      /* ??? See varasm.c.  There are other things that get output	\
-	 too early, like alignment (before we've switched STREAM).  */	\
-      if (DECL_SECTION_NAME (DECL) == NULL_TREE)			\
-	fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP);			\
-    }									\
-									\
-  HALF_PIC_DECLARE (NAME);						\
-}
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM)			\
-  fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)			\
-  sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(STREAM,VALUE)					\
-  mips_output_double (STREAM, VALUE)
-
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(STREAM,VALUE)					\
-  mips_output_float (STREAM, VALUE)
-
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(STREAM,VALUE)					\
-do {									\
-  fprintf (STREAM, "\t.word\t");					\
-  output_addr_const (STREAM, (VALUE));					\
-  fprintf (STREAM, "\n");						\
-} while (0)
-
-/* Likewise for 64 bit, `char' and `short' constants.  */
-
-#define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE)				\
-do {									\
-  if (TARGET_64BIT)							\
-    {									\
-      fprintf (STREAM, "\t.dword\t");					\
-      if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT)	\
-	/* We can't use 'X' for negative numbers, because then we won't	\
-	   get the right value for the upper 32 bits.  */		\
-        output_addr_const (STREAM, VALUE);				\
-      else								\
-	/* We must use 'X', because otherwise LONG_MIN will print as	\
-	   a number that the Irix 6 assembler won't accept.  */		\
-        print_operand (STREAM, VALUE, 'X');				\
-      fprintf (STREAM, "\n");						\
-    }									\
-  else									\
-    {									\
-      assemble_integer (operand_subword ((VALUE), 0, 0, DImode),	\
-			UNITS_PER_WORD, 1);				\
-      assemble_integer (operand_subword ((VALUE), 1, 0, DImode),	\
-			UNITS_PER_WORD, 1);				\
-    }									\
-} while (0)
-
-#define ASM_OUTPUT_SHORT(STREAM,VALUE)					\
-{									\
-  fprintf (STREAM, "\t.half\t");					\
-  output_addr_const (STREAM, (VALUE));					\
-  fprintf (STREAM, "\n");						\
-}
-
-#define ASM_OUTPUT_CHAR(STREAM,VALUE)					\
-{									\
-  fprintf (STREAM, "\t.byte\t");					\
-  output_addr_const (STREAM, (VALUE));					\
-  fprintf (STREAM, "\n");						\
-}
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(STREAM,VALUE)					\
-  fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)				\
-  fprintf (STREAM, "\t%s\t%sL%d\n",					\
-	   Pmode == DImode ? ".dword" : ".word",			\
-	   LOCAL_LABEL_PREFIX,						\
-	   VALUE)
-
-/* This is how to output an element of a case-vector that is relative.
-   This is used for pc-relative code (e.g. when TARGET_ABICALLS or
-   TARGET_EMBEDDED_PIC).  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)		\
-do {									\
-  if (TARGET_MIPS16)							\
-    fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n",				\
-	     LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL);	\
-  else if (TARGET_EMBEDDED_PIC)						\
-    fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n",				\
-	     Pmode == DImode ? ".dword" : ".word",			\
-	     LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL);	\
-  else if (mips_abi == ABI_32 || mips_abi == ABI_O64)			\
-    fprintf (STREAM, "\t%s\t%sL%d\n",					\
-	     Pmode == DImode ? ".gpdword" : ".gpword",			\
-	     LOCAL_LABEL_PREFIX, VALUE);				\
-  else									\
-    fprintf (STREAM, "\t%s\t%sL%d\n",					\
-	     Pmode == DImode ? ".dword" : ".word",			\
-	     LOCAL_LABEL_PREFIX, VALUE);				\
-} while (0)
-
-/* When generating embedded PIC or mips16 code we want to put the jump
-   table in the .text section.  In all other cases, we want to put the
-   jump table in the .rdata section.  Unfortunately, we can't use
-   JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
-   Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
-   section if appropriate.  */
-#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN)			\
-do {									\
-  if (TARGET_EMBEDDED_PIC || TARGET_MIPS16)				\
-    function_section (current_function_decl);				\
-  ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM);			\
-} while (0)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(STREAM,LOG)					\
-  fprintf (STREAM, "\t.align\t%d\n", (LOG))
-
-/* CYGNUS LOCAL law */
-#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
-#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
-  if ((LOG)!=0) \
-    if ((MAX_SKIP)==0) fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
-    else fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP))
-#endif
-/* END CYGNUS LOCAL */
-
-
-/* This is how to output an assembler line to advance the location
-   counter by SIZE bytes.  */
-
-#define ASM_OUTPUT_SKIP(STREAM,SIZE)					\
-  fprintf (STREAM, "\t.space\t%u\n", (SIZE))
-
-/* This is how to output a string.  */
-#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN)				\
-do {									\
-  register int i, c, len = (LEN), cur_pos = 17;				\
-  register unsigned char *string = (unsigned char *)(STRING);		\
-  fprintf ((STREAM), "\t.ascii\t\"");					\
-  for (i = 0; i < len; i++)						\
-    {									\
-      register int c = string[i];					\
-									\
-      switch (c)							\
-	{								\
-	case '\"':							\
-	case '\\':							\
-	  putc ('\\', (STREAM));					\
-	  putc (c, (STREAM));						\
-	  cur_pos += 2;							\
-	  break;							\
-									\
-	case TARGET_NEWLINE:						\
-	  fputs ("\\n", (STREAM));					\
-	  if (i+1 < len							\
-	      && (((c = string[i+1]) >= '\040' && c <= '~')		\
-		  || c == TARGET_TAB))					\
-	    cur_pos = 32767;		/* break right here */		\
-	  else								\
-	    cur_pos += 2;						\
-	  break;							\
-									\
-	case TARGET_TAB:						\
-	  fputs ("\\t", (STREAM));					\
-	  cur_pos += 2;							\
-	  break;							\
-									\
-	case TARGET_FF:							\
-	  fputs ("\\f", (STREAM));					\
-	  cur_pos += 2;							\
-	  break;							\
-									\
-	case TARGET_BS:							\
-	  fputs ("\\b", (STREAM));					\
-	  cur_pos += 2;							\
-	  break;							\
-									\
-	case TARGET_CR:							\
-	  fputs ("\\r", (STREAM));					\
-	  cur_pos += 2;							\
-	  break;							\
-									\
-	default:							\
-	  if (c >= ' ' && c < 0177)					\
-	    {								\
-	      putc (c, (STREAM));					\
-	      cur_pos++;						\
-	    }								\
-	  else								\
-	    {								\
-	      fprintf ((STREAM), "\\%03o", c);				\
-	      cur_pos += 4;						\
-	    }								\
-	}								\
-									\
-      if (cur_pos > 72 && i+1 < len)					\
-	{								\
-	  cur_pos = 17;							\
-	  fprintf ((STREAM), "\"\n\t.ascii\t\"");			\
-	}								\
-    }									\
-  fprintf ((STREAM), "\"\n");						\
-} while (0)
-
-/* Handle certain cpp directives used in header files on sysV.  */
-#define SCCS_DIRECTIVE
-
-/* Output #ident as a in the read-only data section.  */
-#define ASM_OUTPUT_IDENT(FILE, STRING)					\
-{									\
-  char *p = STRING;							\
-  int size = strlen (p) + 1;						\
-  rdata_section ();							\
-  assemble_string (p, size);						\
-}
-
-/* Default to -G 8 */
-#ifndef MIPS_DEFAULT_GVALUE
-#define MIPS_DEFAULT_GVALUE 8
-#endif
-
-/* Define the strings to put out for each section in the object file.  */
-#define TEXT_SECTION_ASM_OP	"\t.text"	/* instructions */
-#define DATA_SECTION_ASM_OP	"\t.data"	/* large data */
-#define SDATA_SECTION_ASM_OP	"\t.sdata"	/* small data */
-#define RDATA_SECTION_ASM_OP	"\t.rdata"	/* read-only data */
-#define READONLY_DATA_SECTION	rdata_section
-#define SMALL_DATA_SECTION	sdata_section
-
-/* What other sections we support other than the normal .data/.text.  */
-
-#define EXTRA_SECTIONS in_sdata, in_rdata
-
-/* Define the additional functions to select our additional sections.  */
-
-/* on the MIPS it is not a good idea to put constants in the text
-   section, since this defeats the sdata/data mechanism. This is
-   especially true when -O is used. In this case an effort is made to
-   address with faster (gp) register relative addressing, which can
-   only get at sdata and sbss items (there is no stext !!)  However,
-   if the constant is too large for sdata, and it's readonly, it
-   will go into the .rdata section. */
-
-#define EXTRA_SECTION_FUNCTIONS						\
-void									\
-sdata_section ()							\
-{									\
-  if (in_section != in_sdata)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP);		\
-      in_section = in_sdata;						\
-    }									\
-}									\
-									\
-void									\
-rdata_section ()							\
-{									\
-  if (in_section != in_rdata)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP);		\
-      in_section = in_rdata;						\
-    }									\
-}
-
-/* Given a decl node or constant node, choose the section to output it in
-   and select that section.  */
-
-#define SELECT_RTX_SECTION(MODE,RTX)	mips_select_rtx_section (MODE, RTX)
-
-#define SELECT_SECTION(DECL, RELOC)	mips_select_section (DECL, RELOC)
-
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)			\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),			\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)				\
-do									\
-  {									\
-    fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n",			\
-	     TARGET_64BIT ? "dsubu" : "subu",				\
-	     reg_names[STACK_POINTER_REGNUM],				\
-	     reg_names[STACK_POINTER_REGNUM],				\
-	     TARGET_64BIT ? "sd" : "sw",				\
-	     reg_names[REGNO],						\
-	     reg_names[STACK_POINTER_REGNUM]);				\
-  }									\
-while (0)
-
-#define ASM_OUTPUT_REG_POP(STREAM,REGNO)				\
-do									\
-  {									\
-    if (! set_noreorder)						\
-      fprintf (STREAM, "\t.set\tnoreorder\n");				\
-									\
-    dslots_load_total++;						\
-    dslots_load_filled++;						\
-    fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n",			\
-	     TARGET_64BIT ? "ld" : "lw",				\
-	     reg_names[REGNO],						\
-	     reg_names[STACK_POINTER_REGNUM],				\
-	     TARGET_64BIT ? "daddu" : "addu",				\
-	     reg_names[STACK_POINTER_REGNUM],				\
-	     reg_names[STACK_POINTER_REGNUM]);				\
-									\
-    if (! set_noreorder)						\
-      fprintf (STREAM, "\t.set\treorder\n");				\
-  }									\
-while (0)
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* How to start an assembler comment.
-   The leading space is important (the mips native assembler requires it).  */
-#ifndef ASM_COMMENT_START
-#define ASM_COMMENT_START " #"
-#endif
-
-
-/* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
-   and mips-tdump.c to print them out.
-
-   These must match the corresponding definitions in gdb/mipsread.c.
-   Unfortunately, gcc and gdb do not currently share any directories. */
-
-#define CODE_MASK 0x8F300
-#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
-#define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
-#define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
-
-
-/* Default definitions for size_t and ptrdiff_t.  */
-
-#ifndef SIZE_TYPE
-#define NO_BUILTIN_SIZE_TYPE
-#define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
-#endif
-
-#ifndef PTRDIFF_TYPE
-#define NO_BUILTIN_PTRDIFF_TYPE
-#define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
-#endif
-
-/* See mips_expand_prologue's use of loadgp for when this should be
-   true.  */
-
-#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS 		\
-					 && mips_abi != ABI_32		\
-					 && mips_abi != ABI_O64)
-
-/* In mips16 mode, we need to look through the function to check for
-   PC relative loads that are out of range.  */
-#define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
-
-/* We need to use a special set of functions to handle hard floating
-   point code in mips16 mode.  */
-
-#ifndef INIT_SUBTARGET_OPTABS
-#define INIT_SUBTARGET_OPTABS
-#endif
-
-#define INIT_TARGET_OPTABS						\
-do									\
-  {									\
-    if (! TARGET_MIPS16 || ! mips16_hard_float)				\
-      INIT_SUBTARGET_OPTABS;						\
-    else								\
-      {									\
-	add_optab->handlers[(int) SFmode].libfunc =			\
-	  gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3");		\
-	sub_optab->handlers[(int) SFmode].libfunc =			\
-	  gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3");		\
-	smul_optab->handlers[(int) SFmode].libfunc =			\
-	  gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3");		\
-	flodiv_optab->handlers[(int) SFmode].libfunc =			\
-	  gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3");		\
-									\
-	eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2");	\
-	nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2");	\
-	gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2");	\
-	gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2");	\
-	ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2");	\
-	lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2");	\
-									\
-	floatsisf_libfunc =						\
-	  gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf");		\
-	fixsfsi_libfunc =						\
-	  gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi");		\
-									\
-	if (TARGET_DOUBLE_FLOAT)					\
-	  {								\
-	    add_optab->handlers[(int) DFmode].libfunc =			\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3");		\
-	    sub_optab->handlers[(int) DFmode].libfunc =			\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3");		\
-	    smul_optab->handlers[(int) DFmode].libfunc =		\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3");		\
-	    flodiv_optab->handlers[(int) DFmode].libfunc =		\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3");		\
-									\
-	    extendsfdf2_libfunc =					\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2");	\
-	    truncdfsf2_libfunc =					\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2");	\
-									\
-	    eqdf2_libfunc =						\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2");		\
-	    nedf2_libfunc =						\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2");		\
-	    gtdf2_libfunc =						\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2");		\
-	    gedf2_libfunc =						\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2");		\
-	    ltdf2_libfunc =						\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2");		\
-	    ledf2_libfunc =						\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2");		\
-									\
-	    floatsidf_libfunc =						\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf");	\
-	    fixdfsi_libfunc =						\
-	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi");		\
-	  }								\
-      }									\
-  }									\
-while (0)
-
-
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
deleted file mode 100755
index 7e18299..0000000
--- a/gcc/config/mips/mips.md
+++ /dev/null
@@ -1,10710 +0,0 @@
-;;  Mips.md	     Machine Description for MIPS based processors
-;;  Contributed by   A. Lichnewsky, lich@inria.inria.fr
-;;  Changes by       Michael Meissner, meissner@osf.org
-;;  64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
-;;  Brendan Eich, brendan@microunity.com.
-;;  Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;; ??? Currently does not have define_function_unit support for the R8000.
-;; Must include new entries for fmadd in addition to existing entries.
-
-
-
-;; ....................
-;;	Attributes
-;; ....................
-
-;; Classification of each insn.
-;; branch	conditional branch
-;; jump		unconditional jump
-;; call		unconditional call
-;; load		load instruction(s)
-;; store	store instruction(s)
-;; move		data movement within same register set
-;; xfer		transfer to/from coprocessor
-;; hilo		transfer of hi/lo registers
-;; arith	integer arithmetic instruction
-;; darith	double precision integer arithmetic instructions
-;; imul		integer multiply
-;; idiv		integer divide
-;; icmp		integer compare
-;; fadd		floating point add/subtract
-;; fmul		floating point multiply
-;; fmadd	floating point multiply-add
-;; fdiv		floating point divide
-;; fabs		floating point absolute value
-;; fneg		floating point negation
-;; fcmp		floating point compare
-;; fcvt		floating point convert
-;; fsqrt	floating point square root
-;; frsqrt	floating point reciprocal square root CYGNUS LOCAL vr5400/raeburn
-;; multi	multiword sequence (or user asm statements)
-;; nop		no operation
-
-(define_attr "type"
-  "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop" ; CYGNUS LOCAL vr5400/raeburn
-  (const_string "unknown"))
-
-;; Main data type used by the insn
-(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
-
-;; # instructions (4 bytes each)
-(define_attr "length" "" (const_int 1))
-
-;; Attribute describing the processor.  This attribute must match exactly
-;; with the processor_type enumeration in mips.h.
-
-;; Attribute describing the processor
-;; (define_attr "cpu" "default,r3000,r6000,r4000"
-;;   (const
-;;    (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000"))   (const_string "r3000")
-;;           (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000"))   (const_string "r4000")
-;;           (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000"))   (const_string "r6000")]
-;;          (const_string "default"))))
-
-;; ??? Fix everything that tests this attribute.
-(define_attr "cpu"
-  "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r5400,r8000" ;   CYGNUS LOCAL vr5400/raeburn
-  (const (symbol_ref "mips_cpu_attr")))
-
-;; Does the instruction have a mandatory delay slot?
-;;   The 3900, is (mostly) mips1, but does not have a manditory load delay
-;;   slot. 
-(define_attr "dslot" "no,yes"
-  (if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp")
-		     (and (eq_attr "type" "load")
-			  (and (eq (symbol_ref "mips_isa") (const_int 1))
-			       (and (eq (symbol_ref "mips16") (const_int 0))
-                                    (eq_attr "cpu" "!r3900")))))
-		(const_string "yes")
-		(const_string "no")))
-
-;; Attribute defining whether or not we can use the branch-likely instructions
-
-(define_attr "branch_likely" "no,yes"
-  (const
-   (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
-		 (const_string "yes")
-		 (const_string "no"))))
-
-
-;; Describe a user's asm statement.
-(define_asm_attributes
-  [(set_attr "type" "multi")])
-
-;; whether or not generating calls to position independent functions
-(define_attr "abicalls" "no,yes"
-  (const (symbol_ref "mips_abicalls_attr")))
-
-
-
-;; .........................
-;;	Delay slots, can't describe load/fcmp/xfer delay slots here
-;; .........................
-
-(define_delay (and (eq_attr "type" "branch")
-		   (eq (symbol_ref "mips16") (const_int 0)))
-  [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
-   (nil)
-   (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "no") (eq_attr "length" "1")))])
-
-(define_delay (eq_attr "type" "jump")
-  [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
-   (nil)
-   (nil)])
-
-(define_delay (and (eq_attr "type" "call") (eq_attr "abicalls" "no"))
-  [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
-   (nil)
-   (nil)])
-
-
-
-;; .........................
-;;	Functional units
-;; .........................
-
-; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
-;			TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
-
-;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
-
-(define_function_unit "memory" 1 0
-  (and (eq_attr "type" "load")
-       (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000,r5400")) ;   CYGNUS LOCAL vr5400/raeburn
-  3 0)
-
-(define_function_unit "memory" 1 0
-  (and (eq_attr "type" "load")
-       (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000,r5400")) ;  CYGNUS LOCAL vr5400/raeburn
-  2 0)
-
-;; CYGNUS LOCAL law
-(define_function_unit "memory"   1 0
-  (and (eq_attr "type" "store") (const_int 1)) 1 0) ; 
-
-(define_function_unit "memory"   1 0
-  (and (eq_attr "type" "xfer") (const_int 1)) 2 0) ; 
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "hilo")
-       (const_int 1)) ; 
-  1 3)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000,r5400")) ;   CYGNUS LOCAL vr5400/raeburn
-  17 17)
-;; END CYGNUS LOCAL
-
-;; On them mips16, we want to stronly discourage a mult from appearing
-;; after an mflo, since that requires explicit nop instructions.  We
-;; do this by pretending that mflo ties up the function unit for long
-;; enough that the scheduler will ignore load stalls and the like when
-;; selecting instructions to between the two instructions.
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "hilo") (ne (symbol_ref "mips16") (const_int 0)))
-  1 5)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "imul") (eq_attr "cpu" "r3000,r3900"))
-  12 12)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "imul") (eq_attr "cpu" "r4000,r4600"))
-  10 10)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "imul") (eq_attr "cpu" "r4650"))
-  4 4)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "imul")
-       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
-  1 1)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "imul")
-       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
-  4 4)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "imul")
-       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000"))) ; 
-  5 5)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "imul")
-       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300"))) ; 
-  8 8)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "imul")
-       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
-  9 9)
-
-;; CYGNUS LOCAL vr5400/raeburn
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "imul")
-       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5400")))
-  3 1)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "imul")
-       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5400")))
-  4 2)
-;; END CYGNUS LOCAL
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000,r5400")) ;   CYGNUS LOCAL vr5400/raeburn
-  38 38)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000,r3900"))
-  35 35)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
-  42 42)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650"))
-  36 36)
-
-(define_function_unit "imuldiv"  1 0
-  (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
-  69 69)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
-  35 35)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
-  67 67)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300"))) ; 
-  37 37)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300"))) ; 
-  69 69)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000")))
-  36 36)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
-  68 68)
-
-;; CYGNUS LOCAL vr5400/raeburn
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5400")))
-  34 34)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5400")))
-  66 66)
-;; END CYGNUS LOCAL
-
-;; The R4300 does *NOT* have a separate Floating Point Unit, instead
-;; the FP hardware is part of the normal ALU circuitry.  This means FP
-;; instructions affect the pipe-line, and no functional unit
-;; parallelism can occur on R4300 processors.  To force GCC into coding
-;; for only a single functional unit, we force the R4300 FP
-;; instructions to be processed in the "imuldiv" unit.
-
-(define_function_unit "adder" 1 1
-  (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000,r5400")) ;   CYGNUS LOCAL vr5400/raeburn
-  3 0)
-
-(define_function_unit "adder" 1 1
-  (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000"))
-  2 0)
-
-(define_function_unit "adder" 1 1
-  (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000"))
-  1 0)
-
-(define_function_unit "adder" 1 1
-  (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5400")) ;   CYGNUS LOCAL vr5400/raeburn
-  4 0)
-
-(define_function_unit "adder" 1 1
-  (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000,r3900"))
-  2 0)
-
-(define_function_unit "adder" 1 1
-  (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
-  3 0)
-
-(define_function_unit "adder" 1 1
-  (and (eq_attr "type" "fabs,fneg")
-       (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000,r5400")) ;   CYGNUS LOCAL vr5400/raeburn
-  2 0)
-
-(define_function_unit "adder" 1 1
-  (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
-  1 0)
-
-(define_function_unit "mult" 1 1
-  (and (eq_attr "type" "fmul")
-       (and (eq_attr "mode" "SF")
-	    (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000,r5400"))) ;   CYGNUS LOCAL vr5400/raeburn
-  7 0)
-
-(define_function_unit "mult" 1 1
-  (and (eq_attr "type" "fmul")
-       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900,r5000")))
-  4 0)
-
-(define_function_unit "mult" 1 1
-  (and (eq_attr "type" "fmul")
-       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
-  5 0)
-
-(define_function_unit "mult" 1 1
-  (and (eq_attr "type" "fmul")
-       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
-  8 0)
-
-(define_function_unit "mult" 1 1
-  (and (eq_attr "type" "fmul")
-       (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000,r5400"))) ;  CYGNUS LOCAL vr5400/raeburn
-  8 0)
-
-(define_function_unit "mult" 1 1
-  (and (eq_attr "type" "fmul")
-       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900,r5000")))
-  5 0)
-
-(define_function_unit "mult" 1 1
-  (and (eq_attr "type" "fmul")
-       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
-  6 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fdiv")
-       (and (eq_attr "mode" "SF")
-	    (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000,r5400"))) ;   CYGNUS LOCAL vr5400/raeburn
-  23 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fdiv")
-       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900")))
-  12 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fdiv")
-       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
-  15 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fdiv")
-       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
-  32 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fdiv")
-       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
-  21 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fdiv")
-       (and (eq_attr "mode" "DF")
-	    (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5400"))) ;  CYGNUS LOCAL vr5400/raeburn
-  36 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fdiv")
-       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900")))
-  19 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fdiv")
-       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
-  16 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fdiv")
-       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
-  61 0)
-
-;;; ??? Is this number right?
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fsqrt,frsqrt") ; CYGNUS LOCAL vr5400/raeburn
-       (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000,r5400"))) ;   CYGNUS LOCAL vr5400/raeburn
-  54 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fsqrt,frsqrt") ; CYGNUS LOCAL vr5400/raeburn
-       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
-  31 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fsqrt,frsqrt") ; CYGNUS LOCAL vr5400/raeburn
-       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
-  21 0)
-
-;;; ??? Is this number right?
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fsqrt,frsqrt") ; CYGNUS LOCAL vr5400/raeburn
-       (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000,r5400"))) ;  CYGNUS LOCAL vr5400/raeburn
-  112 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fsqrt,frsqrt") ; CYGNUS LOCAL vr5400/raeburn
-       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
-  60 0)
-
-(define_function_unit "divide" 1 1
-  (and (eq_attr "type" "fsqrt,frsqrt") ; CYGNUS LOCAL vr5400/raeburn
-       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
-  36 0)
-
-;; R4300 FP instruction classes treated as part of the "imuldiv"
-;; functional unit:
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300")) ; 
-  3 3)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300")) ; 
-  1 1)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300"))) ; 
-  5 5)
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300"))) ; 
-  8 8)
-
-(define_function_unit "imuldiv" 1 0
-  (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt")) ; CYGNUS LOCAL vr5400/raeburn
-       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300"))) ; 
-  29 29)
-(define_function_unit "imuldiv" 1 0
-  (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt")) ; CYGNUS LOCAL vr5400/raeburn
-       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300"))) ;  
-  58 58)
-
-;; CYGNUS LOCAL vr5400/raeburn
-(define_function_unit "alu_5400" 2 0
-  (and (eq_attr "type" "move,arith,darith,icmp,nop")
-       (eq_attr "cpu" "r5400"))
-  1 0)
-
-(define_function_unit "alu_5400" 2 0
-  (and (eq_attr "type" "fadd")
-       (eq_attr "cpu" "r5400"))
-  4 3)
-
-(define_function_unit "alu_5400" 2 0
-  (and (eq_attr "type" "fcmp,fabs,fneg")
-       (eq_attr "cpu" "r5400"))
-  2 1)
-
-(define_function_unit "alu_5400" 2 0
-  (and (and (eq_attr "type" "fmul")
-	    (eq_attr "mode" "SF"))
-       (eq_attr "cpu" "r5400"))
-  5 4)
-
-(define_function_unit "alu_5400" 2 0
-  (and (and (eq_attr "type" "fmul")
-	    (eq_attr "mode" "DF"))
-       (eq_attr "cpu" "r5400"))
-  6 5)
-
-(define_function_unit "alu_5400" 2 0
-  (and (and (eq_attr "type" "fdiv,fsqrt")
-	    (eq_attr "mode" "SF"))
-       (eq_attr "cpu" "r5400"))
-  31 30)
-
-(define_function_unit "alu_5400" 2 0
-  (and (and (eq_attr "type" "fdiv,fsqrt")
-	    (eq_attr "mode" "DF"))
-       (eq_attr "cpu" "r5400"))
-  59 58)
-
-(define_function_unit "alu_5400" 2 0
-  (and (and (eq_attr "type" "frsqrt")
-	    (eq_attr "mode" "SF"))
-       (eq_attr "cpu" "r5400"))
-  61 60)
-
-(define_function_unit "alu_5400" 2 0
-  (and (and (eq_attr "type" "frsqrt")
-	    (eq_attr "mode" "DF"))
-       (eq_attr "cpu" "r5400"))
-  121 120)
-
-(define_function_unit "alu_5400" 2 0
-  (and (and (eq_attr "type" "fmadd")
-	    (eq_attr "mode" "SF"))
-       (eq_attr "cpu" "r5400"))
-  9 8)
-
-(define_function_unit "alu_5400" 2 0
-  (and (and (eq_attr "type" "fmadd")
-	    (eq_attr "mode" "DF"))
-       (eq_attr "cpu" "r5400"))
-  10 9)
-
-(define_function_unit "alu_5400" 2 0
-  (and (eq_attr "type" "fcvt")
-       (eq_attr "cpu" "r5400"))
-  6 5)
-;; END CYGNUS LOCAL
-
-
-
-;; The following functional units do not use the cpu type, and use
-;; much less memory in genattrtab.c.
-
-;; (define_function_unit "memory"   1 0 (eq_attr "type" "load")                                3 0)
-;; (define_function_unit "memory"   1 0 (eq_attr "type" "store")                               1 0)
-;; (define_function_unit "fp_comp"  1 0 (eq_attr "type" "fcmp")                                2 0)
-;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer")                                2 0)
-;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo")                                3 0)
-;; (define_function_unit "imuldiv"  1 1 (eq_attr "type" "imul")                               17 0)
-;; (define_function_unit "imuldiv"  1 1 (eq_attr "type" "idiv")                               38 0)
-;; (define_function_unit "adder"    1 1 (eq_attr "type" "fadd")                                4 0)
-;; (define_function_unit "adder"    1 1 (eq_attr "type" "fabs,fneg")                           2 0)
-;; (define_function_unit "mult"     1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF"))    7 0)
-;; (define_function_unit "mult"     1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF"))    8 0)
-;; (define_function_unit "divide"   1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF"))   23 0)
-;; (define_function_unit "divide"   1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF"))   36 0)
-;; (define_function_unit "sqrt"     1 1 (and (eq_attr "type" "fsqrt,frsqrt") (eq_attr "mode" "SF"))  54 0) CYGNUS LOCAL vr5400/raeburn
-;; (define_function_unit "sqrt"     1 1 (and (eq_attr "type" "fsqrt,frsqrt") (eq_attr "mode" "DF")) 112 0) CYGNUS LOCAL vr5400/raeburn
-
-
-;;  ....................
-;;	ADDITION
-;;  ....................
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (match_operand:DF 1 "register_operand" "f")
-		 (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "add.d\\t%0,%1,%2"
-  [(set_attr "type"	"fadd")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "add.s\\t%0,%1,%2"
-  [(set_attr "type"	"fadd")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
-		 (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "
-{
-  /* The mips16 assembler handles -32768 correctly, and so does gas,
-     but some other MIPS assemblers think that -32768 needs to be
-     loaded into a register before it can be added in.  */
-  if (! TARGET_MIPS16
-      && ! TARGET_GAS
-      && GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) == -32768)
-    operands[2] = force_reg (SImode, operands[2]);
-}")
-
-(define_insn "addsi3_internal"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
-		 (match_operand:SI 2 "arith_operand" "dI")))]
-  "! TARGET_MIPS16
-   && (TARGET_GAS
-       || GET_CODE (operands[2]) != CONST_INT
-       || INTVAL (operands[2]) != -32768)"
-  "addu\\t%0,%z1,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-;; For the mips16, we need to recognize stack pointer additions
-;; explicitly, since we don't have a constraint for $sp.  These insns
-;; will be generated by the save_restore_insns functions.
-
-(define_insn ""
-  [(set (reg:SI 29)
-	(plus:SI (reg:SI 29)
-		 (match_operand:SI 0 "small_int" "I")))]
-  "TARGET_MIPS16"
-  "addu\\t%$,%$,%0"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
-				      (const_int 1)
-				      (const_int 2)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(plus:SI (reg:SI 29)
-		 (match_operand:SI 1 "small_int" "I")))]
-  "TARGET_MIPS16"
-  "addu\\t%0,%$,%1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set (attr "length")	(if_then_else (match_operand:VOID 1 "m16_uimm8_4" "")
-				      (const_int 1)
-				      (const_int 2)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
-	(plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
-		 (match_operand:SI 2 "arith_operand" "IQ,O,d")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[1]) != REG
-       || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
-       || M16_REG_P (REGNO (operands[1]))
-       || REGNO (operands[1]) == ARG_POINTER_REGNUM
-       || REGNO (operands[1]) == FRAME_POINTER_REGNUM
-       || REGNO (operands[1]) == STACK_POINTER_REGNUM)
-   && (GET_CODE (operands[2]) != REG
-       || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER
-       || M16_REG_P (REGNO (operands[2]))
-       || REGNO (operands[2]) == ARG_POINTER_REGNUM
-       || REGNO (operands[2]) == FRAME_POINTER_REGNUM
-       || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
-  "*
-{
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"addu\\t%0,%2\";
-  return \"addu\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (const_int 1)])])
-
-
-;; On the mips16, we can sometimes split an add of a constant which is
-;; a 4 byte instruction into two adds which are both 2 byte
-;; instructions.  There are two cases: one where we are adding a
-;; constant plus a register to another register, and one where we are
-;; simply adding a constant to a register.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_dup 0)
-		 (match_operand:SI 1 "const_int_operand" "")))]
-  "TARGET_MIPS16 && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && ((INTVAL (operands[1]) > 0x7f
-	&& INTVAL (operands[1]) <= 0x7f + 0x7f)
-       || (INTVAL (operands[1]) < - 0x80
-	   && INTVAL (operands[1]) >= - 0x80 - 0x80))"
-  [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
-   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-  if (val >= 0)
-    {
-      operands[1] = GEN_INT (0x7f);
-      operands[2] = GEN_INT (val - 0x7f);
-    }
-  else
-    {
-      operands[1] = GEN_INT (- 0x80);
-      operands[2] = GEN_INT (val + 0x80);
-    }
-}")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "const_int_operand" "")))]
-  "TARGET_MIPS16 && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG
-   && M16_REG_P (REGNO (operands[1]))
-   && REGNO (operands[0]) != REGNO (operands[1])
-   && GET_CODE (operands[2]) == CONST_INT
-   && ((INTVAL (operands[2]) > 0x7
-	&& INTVAL (operands[2]) <= 0x7 + 0x7f)
-       || (INTVAL (operands[2]) < - 0x8
-	   && INTVAL (operands[2]) >= - 0x8 - 0x80))"
-  [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[2]);
-
-  if (val >= 0)
-    {
-      operands[2] = GEN_INT (0x7);
-      operands[3] = GEN_INT (val - 0x7);
-    }
-  else
-    {
-      operands[2] = GEN_INT (- 0x8);
-      operands[3] = GEN_INT (val + 0x8);
-    }
-}")
-
-(define_expand "adddi3"
-  [(parallel [(set (match_operand:DI 0 "register_operand" "")
-		   (plus:DI (match_operand:DI 1 "se_register_operand" "")
-			    (match_operand:DI 2 "se_arith_operand" "")))
-	      (clobber (match_dup 3))])]
-  "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
-  "
-{
-  /* The mips16 assembler handles -32768 correctly, and so does gas,
-     but some other MIPS assemblers think that -32768 needs to be
-     loaded into a register before it can be added in.  */
-  if (! TARGET_MIPS16
-      && ! TARGET_GAS
-      && GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) == -32768)
-    operands[2] = force_reg (DImode, operands[2]);
-
-  if (TARGET_64BIT)
-    {
-      emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],
-					operands[2]));
-      DONE;
-    }
-
-  operands[3] = gen_reg_rtx (SImode);
-}")
-
-(define_insn "adddi3_internal_1"
-  [(set (match_operand:DI 0 "register_operand" "=d,&d")
-	(plus:DI (match_operand:DI 1 "register_operand" "0,d")
-		 (match_operand:DI 2 "register_operand" "d,d")))
-   (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-  "*
-{
-  return (REGNO (operands[0]) == REGNO (operands[1])
-	  && REGNO (operands[0]) == REGNO (operands[2]))
-    ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\"
-    : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(plus:DI (match_operand:DI 1 "register_operand" "")
-		 (match_operand:DI 2 "register_operand" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
-   && (REGNO (operands[0]) != REGNO (operands[1])
-       || REGNO (operands[0]) != REGNO (operands[2]))"
-
-  [(set (subreg:SI (match_dup 0) 0)
-	(plus:SI (subreg:SI (match_dup 1) 0)
-		 (subreg:SI (match_dup 2) 0)))
-
-   (set (match_dup 3)
-	(ltu:SI (subreg:SI (match_dup 0) 0)
-		(subreg:SI (match_dup 2) 0)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(plus:SI (subreg:SI (match_dup 1) 1)
-		 (subreg:SI (match_dup 2) 1)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(plus:SI (subreg:SI (match_dup 0) 1)
-		 (match_dup 3)))]
-  "")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(plus:DI (match_operand:DI 1 "register_operand" "")
-		 (match_operand:DI 2 "register_operand" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
-   && (REGNO (operands[0]) != REGNO (operands[1])
-       || REGNO (operands[0]) != REGNO (operands[2]))"
-
-  [(set (subreg:SI (match_dup 0) 1)
-	(plus:SI (subreg:SI (match_dup 1) 1)
-		 (subreg:SI (match_dup 2) 1)))
-
-   (set (match_dup 3)
-	(ltu:SI (subreg:SI (match_dup 0) 1)
-		(subreg:SI (match_dup 2) 1)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(plus:SI (subreg:SI (match_dup 1) 0)
-		 (subreg:SI (match_dup 2) 0)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(plus:SI (subreg:SI (match_dup 0) 0)
-		 (match_dup 3)))]
-  "")
-
-(define_insn "adddi3_internal_2"
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-	(plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
-		 (match_operand:DI 2 "small_int" "P,J,N")))
-   (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && (TARGET_GAS
-       || GET_CODE (operands[2]) != CONST_INT
-       || INTVAL (operands[2]) != -32768)"
-  "@
-   addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
-   move\\t%L0,%L1\;move\\t%M0,%M1
-   subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"3,2,4")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(plus:DI (match_operand:DI 1 "register_operand" "")
-		 (match_operand:DI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && INTVAL (operands[2]) > 0"
-
-  [(set (subreg:SI (match_dup 0) 0)
-	(plus:SI (subreg:SI (match_dup 1) 0)
-		 (match_dup 2)))
-
-   (set (match_dup 3)
-	(ltu:SI (subreg:SI (match_dup 0) 0)
-		(match_dup 2)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(plus:SI (subreg:SI (match_dup 1) 1)
-		 (match_dup 3)))]
-  "")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(plus:DI (match_operand:DI 1 "register_operand" "")
-		 (match_operand:DI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && INTVAL (operands[2]) > 0"
-
-  [(set (subreg:SI (match_dup 0) 1)
-	(plus:SI (subreg:SI (match_dup 1) 1)
-		 (match_dup 2)))
-
-   (set (match_dup 3)
-	(ltu:SI (subreg:SI (match_dup 0) 1)
-		(match_dup 2)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(plus:SI (subreg:SI (match_dup 1) 0)
-		 (match_dup 3)))]
-  "")
-
-(define_insn "adddi3_internal_3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(plus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ")
-		 (match_operand:DI 2 "se_arith_operand" "dI")))]
-  "TARGET_64BIT
-   && !TARGET_MIPS16
-   && (TARGET_GAS
-       || GET_CODE (operands[2]) != CONST_INT
-       || INTVAL (operands[2]) != -32768)"
-  "*
-{
-  return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    ? \"dsubu\\t%0,%z1,%n2\"
-    : \"daddu\\t%0,%z1,%2\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-;; For the mips16, we need to recognize stack pointer additions
-;; explicitly, since we don't have a constraint for $sp.  These insns
-;; will be generated by the save_restore_insns functions.
-
-(define_insn ""
-  [(set (reg:DI 29)
-	(plus:DI (reg:DI 29)
-		 (match_operand:DI 0 "small_int" "I")))]
-  "TARGET_MIPS16 && TARGET_64BIT"
-  "daddu\\t%$,%$,%0"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
-				      (const_int 1)
-				      (const_int 2)))])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(plus:DI (reg:DI 29)
-		 (match_operand:DI 1 "small_int" "I")))]
-  "TARGET_MIPS16 && TARGET_64BIT"
-  "daddu\\t%0,%$,%1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_uimm5_4" "")
-				      (const_int 1)
-				      (const_int 2)))])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-	(plus:DI (match_operand:DI 1 "register_operand" "0,d,d")
-		 (match_operand:DI 2 "arith_operand" "IQ,O,d")))]
-  "TARGET_MIPS16 && TARGET_64BIT
-   && (GET_CODE (operands[1]) != REG
-       || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
-       || M16_REG_P (REGNO (operands[1]))
-       || REGNO (operands[1]) == ARG_POINTER_REGNUM
-       || REGNO (operands[1]) == FRAME_POINTER_REGNUM
-       || REGNO (operands[1]) == STACK_POINTER_REGNUM)
-   && (GET_CODE (operands[2]) != REG
-       || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER
-       || M16_REG_P (REGNO (operands[2]))
-       || REGNO (operands[2]) == ARG_POINTER_REGNUM
-       || REGNO (operands[2]) == FRAME_POINTER_REGNUM
-       || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
-  "*
-{
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"daddu\\t%0,%2\";
-  return \"daddu\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr_alternative "length"
-		[(if_then_else (match_operand:VOID 2 "m16_simm5_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (const_int 1)])])
-
-
-;; On the mips16, we can sometimes split an add of a constant which is
-;; a 4 byte instruction into two adds which are both 2 byte
-;; instructions.  There are two cases: one where we are adding a
-;; constant plus a register to another register, and one where we are
-;; simply adding a constant to a register.
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(plus:DI (match_dup 0)
-		 (match_operand:DI 1 "const_int_operand" "")))]
-  "TARGET_MIPS16 && TARGET_64BIT && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && ((INTVAL (operands[1]) > 0xf
-	&& INTVAL (operands[1]) <= 0xf + 0xf)
-       || (INTVAL (operands[1]) < - 0x10
-	   && INTVAL (operands[1]) >= - 0x10 - 0x10))"
-  [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
-   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-  if (val >= 0)
-    {
-      operands[1] = GEN_INT (0xf);
-      operands[2] = GEN_INT (val - 0xf);
-    }
-  else
-    {
-      operands[1] = GEN_INT (- 0x10);
-      operands[2] = GEN_INT (val + 0x10);
-    }
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(plus:DI (match_operand:DI 1 "register_operand" "")
-		 (match_operand:DI 2 "const_int_operand" "")))]
-  "TARGET_MIPS16 && TARGET_64BIT && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG
-   && M16_REG_P (REGNO (operands[1]))
-   && REGNO (operands[0]) != REGNO (operands[1])
-   && GET_CODE (operands[2]) == CONST_INT
-   && ((INTVAL (operands[2]) > 0x7
-	&& INTVAL (operands[2]) <= 0x7 + 0xf)
-       || (INTVAL (operands[2]) < - 0x8
-	   && INTVAL (operands[2]) >= - 0x8 - 0x10))"
-  [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[2]);
-
-  if (val >= 0)
-    {
-      operands[2] = GEN_INT (0x7);
-      operands[3] = GEN_INT (val - 0x7);
-    }
-  else
-    {
-      operands[2] = GEN_INT (- 0x8);
-      operands[3] = GEN_INT (val + 0x8);
-    }
-}")
-
-(define_insn "addsi3_internal_2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
-				 (match_operand:SI 2 "arith_operand" "dI"))))]
-  "TARGET_64BIT
-   && !TARGET_MIPS16
-   && (TARGET_GAS
-       || GET_CODE (operands[2]) != CONST_INT
-       || INTVAL (operands[2]) != -32768)"
-  "*
-{
-  return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    ? \"subu\\t%0,%z1,%n2\"
-    : \"addu\\t%0,%z1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-	(sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
-				 (match_operand:SI 2 "arith_operand" "I,O,d"))))]
-  "TARGET_MIPS16 && TARGET_64BIT"
-  "*
-{
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"addu\\t%0,%2\";
-  return \"addu\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (const_int 1)])])
-
-
-;;  ....................
-;;	SUBTRACTION
-;;  ....................
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 1 "register_operand" "f")
-		  (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "sub.d\\t%0,%1,%2"
-  [(set_attr "type"	"fadd")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (match_operand:SF 1 "register_operand" "f")
-		  (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "sub.s\\t%0,%1,%2"
-  [(set_attr "type"	"fadd")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
-		  (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (INTVAL (operands[2]) == -32768
-	  || (TARGET_MIPS16
-	      && INTVAL (operands[2]) == -0x4000)))
-    operands[2] = force_reg (SImode, operands[2]);
-}")
-
-(define_insn "subsi3_internal"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
-		  (match_operand:SI 2 "arith_operand" "dI")))]
-  "!TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "subu\\t%0,%z1,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-;; For the mips16, we need to recognize stack pointer subtractions
-;; explicitly, since we don't have a constraint for $sp.  These insns
-;; will be generated by the save_restore_insns functions.
-
-(define_insn ""
-  [(set (reg:SI 29)
-	(minus:SI (reg:SI 29)
-		  (match_operand:SI 0 "small_int" "I")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "addu\\t%$,%$,%n0"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
-				      (const_int 1)
-				      (const_int 2)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(minus:SI (reg:SI 29)
-		  (match_operand:SI 1 "small_int" "I")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "addu\\t%0,%$,%n1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set (attr "length")	(if_then_else (match_operand:VOID 1 "m16_nuimm8_4" "")
-				      (const_int 1)
-				      (const_int 2)))])
-
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
-	(minus:SI (match_operand:SI 1 "register_operand" "0,d,d")
-		  (match_operand:SI 2 "arith_operand" "I,O,d")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT
-       || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
-  "*
-{
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"subu\\t%0,%2\";
-  return \"subu\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (const_int 1)])])
-
-;; On the mips16, we can sometimes split an subtract of a constant
-;; which is a 4 byte instruction into two adds which are both 2 byte
-;; instructions.  There are two cases: one where we are setting a
-;; register to a register minus a constant, and one where we are
-;; simply subtracting a constant from a register.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_dup 0)
-		  (match_operand:SI 1 "const_int_operand" "")))]
-  "TARGET_MIPS16 && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && ((INTVAL (operands[1]) > 0x80
-	&& INTVAL (operands[1]) <= 0x80 + 0x80)
-       || (INTVAL (operands[1]) < - 0x7f
-	   && INTVAL (operands[1]) >= - 0x7f - 0x7f))"
-  [(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 1)))
-   (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-  if (val >= 0)
-    {
-      operands[1] = GEN_INT (0x80);
-      operands[2] = GEN_INT (val - 0x80);
-    }
-  else
-    {
-      operands[1] = GEN_INT (- 0x7f);
-      operands[2] = GEN_INT (val + 0x7f);
-    }
-}")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 1 "register_operand" "")
-		  (match_operand:SI 2 "const_int_operand" "")))]
-  "TARGET_MIPS16 && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG
-   && M16_REG_P (REGNO (operands[1]))
-   && REGNO (operands[0]) != REGNO (operands[1])
-   && GET_CODE (operands[2]) == CONST_INT
-   && ((INTVAL (operands[2]) > 0x8
-	&& INTVAL (operands[2]) <= 0x8 + 0x80)
-       || (INTVAL (operands[2]) < - 0x7
-	   && INTVAL (operands[2]) >= - 0x7 - 0x7f))"
-  [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 3)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[2]);
-
-  if (val >= 0)
-    {
-      operands[2] = GEN_INT (0x8);
-      operands[3] = GEN_INT (val - 0x8);
-    }
-  else
-    {
-      operands[2] = GEN_INT (- 0x7);
-      operands[3] = GEN_INT (val + 0x7);
-    }
-}")
-
-(define_expand "subdi3"
-  [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
-		   (minus:DI (match_operand:DI 1 "se_register_operand" "d")
-			     (match_operand:DI 2 "se_register_operand" "d")))
-	      (clobber (match_dup 3))])]
-  "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
-  "
-{
-  if (TARGET_64BIT)
-    {
-      emit_insn (gen_subdi3_internal_3 (operands[0], operands[1],
-					operands[2]));
-      DONE;
-    }
-
-  operands[3] = gen_reg_rtx (SImode);
-}")
-
-(define_insn "subdi3_internal"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(minus:DI (match_operand:DI 1 "register_operand" "d")
-		  (match_operand:DI 2 "register_operand" "d")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-  "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(minus:DI (match_operand:DI 1 "register_operand" "")
-		  (match_operand:DI 2 "register_operand" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
-  [(set (match_dup 3)
-	(ltu:SI (subreg:SI (match_dup 1) 0)
-		(subreg:SI (match_dup 2) 0)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(minus:SI (subreg:SI (match_dup 1) 0)
-		  (subreg:SI (match_dup 2) 0)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(minus:SI (subreg:SI (match_dup 1) 1)
-		  (subreg:SI (match_dup 2) 1)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(minus:SI (subreg:SI (match_dup 0) 1)
-		  (match_dup 3)))]
-  "")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(minus:DI (match_operand:DI 1 "register_operand" "")
-		  (match_operand:DI 2 "register_operand" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
-  [(set (match_dup 3)
-	(ltu:SI (subreg:SI (match_dup 1) 1)
-	        (subreg:SI (match_dup 2) 1)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(minus:SI (subreg:SI (match_dup 1) 1)
-		  (subreg:SI (match_dup 2) 1)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(minus:SI (subreg:SI (match_dup 1) 0)
-		  (subreg:SI (match_dup 2) 0)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(minus:SI (subreg:SI (match_dup 0) 0)
-		  (match_dup 3)))]
-  "")
-
-(define_insn "subdi3_internal_2"
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
-		  (match_operand:DI 2 "small_int" "P,J,N")))
-   (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && INTVAL (operands[2]) != -32768"
-  "@
-   sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3
-   move\\t%L0,%L1\;move\\t%M0,%M1
-   sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"3,2,4")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(minus:DI (match_operand:DI 1 "register_operand" "")
-		  (match_operand:DI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && INTVAL (operands[2]) > 0"
-
-  [(set (match_dup 3)
-	(ltu:SI (subreg:SI (match_dup 1) 0)
-		(match_dup 2)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(minus:SI (subreg:SI (match_dup 1) 0)
-		  (match_dup 2)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(minus:SI (subreg:SI (match_dup 1) 1)
-		  (match_dup 3)))]
-  "")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(minus:DI (match_operand:DI 1 "register_operand" "")
-		  (match_operand:DI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && INTVAL (operands[2]) > 0"
-
-  [(set (match_dup 3)
-	(ltu:SI (subreg:SI (match_dup 1) 1)
-		(match_dup 2)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(minus:SI (subreg:SI (match_dup 1) 1)
-		  (match_dup 2)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(minus:SI (subreg:SI (match_dup 1) 0)
-		  (match_dup 3)))]
-  "")
-
-(define_insn "subdi3_internal_3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(minus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ")
-		  (match_operand:DI 2 "se_arith_operand" "dI")))]
-  "TARGET_64BIT && !TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "*
-{
-  return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    ? \"daddu\\t%0,%z1,%n2\"
-    : \"dsubu\\t%0,%z1,%2\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-;; For the mips16, we need to recognize stack pointer subtractions
-;; explicitly, since we don't have a constraint for $sp.  These insns
-;; will be generated by the save_restore_insns functions.
-
-(define_insn ""
-  [(set (reg:DI 29)
-	(minus:DI (reg:DI 29)
-		  (match_operand:DI 0 "small_int" "I")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "daddu\\t%$,%$,%n0"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
-				      (const_int 1)
-				      (const_int 2)))])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(minus:DI (reg:DI 29)
-		  (match_operand:DI 1 "small_int" "I")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "daddu\\t%0,%$,%n1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_nuimm5_4" "")
-				      (const_int 1)
-				      (const_int 2)))])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-	(minus:DI (match_operand:DI 1 "register_operand" "0,d,d")
-		  (match_operand:DI 2 "arith_operand" "I,O,d")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT
-       || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
-  "*
-{
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"dsubu\\t%0,%2\";
-  return \"dsubu\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr_alternative "length"
-		[(if_then_else (match_operand:VOID 2 "m16_nsimm5_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (const_int 1)])])
-
-;; On the mips16, we can sometimes split an add of a constant which is
-;; a 4 byte instruction into two adds which are both 2 byte
-;; instructions.  There are two cases: one where we are adding a
-;; constant plus a register to another register, and one where we are
-;; simply adding a constant to a register.
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(minus:DI (match_dup 0)
-		  (match_operand:DI 1 "const_int_operand" "")))]
-  "TARGET_MIPS16 && TARGET_64BIT && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && ((INTVAL (operands[1]) > 0x10
-	&& INTVAL (operands[1]) <= 0x10 + 0x10)
-       || (INTVAL (operands[1]) < - 0xf
-	   && INTVAL (operands[1]) >= - 0xf - 0xf))"
-  [(set (match_dup 0) (minus:DI (match_dup 0) (match_dup 1)))
-   (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-  if (val >= 0)
-    {
-      operands[1] = GEN_INT (0xf);
-      operands[2] = GEN_INT (val - 0xf);
-    }
-  else
-    {
-      operands[1] = GEN_INT (- 0x10);
-      operands[2] = GEN_INT (val + 0x10);
-    }
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(minus:DI (match_operand:DI 1 "register_operand" "")
-		  (match_operand:DI 2 "const_int_operand" "")))]
-  "TARGET_MIPS16 && TARGET_64BIT && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG
-   && M16_REG_P (REGNO (operands[1]))
-   && REGNO (operands[0]) != REGNO (operands[1])
-   && GET_CODE (operands[2]) == CONST_INT
-   && ((INTVAL (operands[2]) > 0x8
-	&& INTVAL (operands[2]) <= 0x8 + 0x10)
-       || (INTVAL (operands[2]) < - 0x7
-	   && INTVAL (operands[2]) >= - 0x7 - 0xf))"
-  [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[2]);
-
-  if (val >= 0)
-    {
-      operands[2] = GEN_INT (0x8);
-      operands[3] = GEN_INT (val - 0x8);
-    }
-  else
-    {
-      operands[2] = GEN_INT (- 0x7);
-      operands[3] = GEN_INT (val + 0x7);
-    }
-}")
-
-(define_insn "subsi3_internal_2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
-				  (match_operand:SI 2 "arith_operand" "dI"))))]
-  "TARGET_64BIT && !TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "*
-{
-  return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    ? \"addu\\t%0,%z1,%n2\"
-    : \"subu\\t%0,%z1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-	(sign_extend:DI (minus:SI (match_operand:SI 1 "register_operand" "0,d,d")
-				  (match_operand:SI 2 "arith_operand" "I,O,d"))))]
-  "TARGET_64BIT && TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT
-       || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
-  "*
-{
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"subu\\t%0,%2\";
-  return \"subu\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (const_int 1)])])
-  
-
-
-;;  ....................
-;;	MULTIPLICATION
-;;  ....................
-
-;; Early Vr4300 silicon has a CPU bug where multiplies with certain
-;; operands may corrupt immediately following multiplies. This is a
-;; simple fix to insert NOPs.
-
-(define_expand "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mult:DF (match_operand:DF 1 "register_operand" "f")
-		 (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "
-{
-  if (mips_cpu != PROCESSOR_R4300)
-    emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn "muldf3_internal"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mult:DF (match_operand:DF 1 "register_operand" "f")
-		 (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu != PROCESSOR_R4300"
-  "mul.d\\t%0,%1,%2"
-  [(set_attr "type"	"fmul")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn "muldf3_r4300"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mult:DF (match_operand:DF 1 "register_operand" "f")
-		 (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu == PROCESSOR_R4300"
-  "*
-{
-  output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
-  if (TARGET_4300_MUL_FIX)
-    output_asm_insn (\"nop\", operands);
-  return \"\";
-}"
-  [(set_attr "type"	"fmul")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"2")])	;; mul.d + nop
-
-(define_expand "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(mult:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "
-{
-  if (mips_cpu != PROCESSOR_R4300)
-    emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
-  else
-    emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn "mulsf3_internal"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(mult:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && mips_cpu != PROCESSOR_R4300"
-  "mul.s\\t%0,%1,%2"
-  [(set_attr "type"	"fmul")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_insn "mulsf3_r4300"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(mult:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && mips_cpu == PROCESSOR_R4300"
-  "*
-{
-  output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
-  if (TARGET_4300_MUL_FIX)
-    output_asm_insn (\"nop\", operands);
-  return \"\";
-}"
-  [(set_attr "type"	"fmul")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"2")])	;; mul.s + nop
-
-
-;; ??? The R4000 (only) has a cpu bug.  If a double-word shift executes while
-;; a multiply is in progress, it may give an incorrect result.  Avoid
-;; this by keeping the mflo with the mult on the R4000.
-
-(define_expand "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "=l")
-	(mult:SI (match_operand:SI 1 "register_operand" "d")
-		 (match_operand:SI 2 "register_operand" "d")))
-   (clobber (match_scratch:SI 3 "=h"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  ""
-  "
-{
-  if (HAVE_mulsi3_mult3)
-    emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
-  else if (mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16)
-    emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-
-(define_insn "mulsi3_mult3"
-  [(set (match_operand:SI 0 "register_operand" "=d,l")
-	(mult:SI (match_operand:SI 1 "register_operand" "d,d")
-		 (match_operand:SI 2 "register_operand" "d,d")))
-   (clobber (match_scratch:SI 3 "=h,h"))
-   (clobber (match_scratch:SI 4 "=l,X"))
-   (clobber (match_scratch:SI 5 "=a,a"))]
-  "(GENERATE_MULT3
-    || TARGET_MIPS5400 /* CYGNUS LOCAL vr5400/raeburn */
-    || TARGET_MAD)
-   && !0" ;;  CYGNUS LOCAL law
-  "*
-{
-  if (which_alternative == 1)
-    return \"mult\\t%1,%2\";
-  if (TARGET_MIPS5400			/* CYGNUS LOCAL vr5400/raeburn */
-      || TARGET_MAD)
-    return \"mul\\t%0,%1,%2\";
-  return \"mult\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn "mulsi3_internal"
-  [(set (match_operand:SI 0 "register_operand" "=l")
-	(mult:SI (match_operand:SI 1 "register_operand" "d")
-		 (match_operand:SI 2 "register_operand" "d")))
-   (clobber (match_scratch:SI 3 "=h"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16"
-  "mult\\t%1,%2"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn "mulsi3_r4000"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(mult:SI (match_operand:SI 1 "register_operand" "d")
-		 (match_operand:SI 2 "register_operand" "d")))
-   (clobber (match_scratch:SI 3 "=h"))
-   (clobber (match_scratch:SI 4 "=l"))
-   (clobber (match_scratch:SI 5 "=a"))]
-  "mips_cpu == PROCESSOR_R4000 && !TARGET_MIPS16"
-  "*
-{
-  rtx xoperands[10];
-
-  xoperands[0] = operands[0];
-  xoperands[1] = gen_rtx (REG, SImode, LO_REGNUM);
-
-  output_asm_insn (\"mult\\t%1,%2\", operands);
-  output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
-  return \"\";
-}"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"3")])		;; mult + mflo + delay
-
-;; Multiply-accumulate patterns
-
-;; For processors that can copy the output to a general register:
-;; The all-d alternative is needed because the combiner will find this
-;; pattern and then register alloc/reload will move registers around to
-;; make them fit, and we don't want to trigger unnecessary loads to LO.
-;; The last alternative should be made slightly less desirable, but adding
-;; "?" to the constraint is too strong, and causes values to be loaded into
-;; LO even when that's more costly.  For now, using "*d" mostly does the
-;; trick.
-
-(define_insn "*mul_acc_si"
-  [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
-	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
-			  (match_operand:SI 2 "register_operand" "d,d,d"))
-		 (match_operand:SI 3 "register_operand" "0,l,*d")))
-   (clobber (match_scratch:SI 4 "=h,h,h"))
-   (clobber (match_scratch:SI 5 "=X,3,l"))
-   (clobber (match_scratch:SI 6 "=a,a,a"))
-   (clobber (match_scratch:SI 7 "=X,X,d"))]
-  "(TARGET_MIPS3900
-    || TARGET_MIPS5400)			/* CYGNUS LOCAL vr5400/raeburn */
-   && !TARGET_MIPS16"
-  "*
-{
-  static char *const madd[] = { \"madd\\t%1,%2\",    \"madd\\t%0,%1,%2\" };
-  static char *const macc[] = { \"macc\\t$0,%1,%2\", \"macc\\t%0,%1,%2\" }; /* CYGNUS LOCAL vr5400/raeburn */
-  if (which_alternative == 2)
-    return \"#\";
-  /* CYGNUS LOCAL vr5400/raeburn */
-  if (TARGET_MIPS5400)
-    return macc[which_alternative];
-  /* END CYGNUS LOCAL */
-  return madd[which_alternative];
-}"
-  [(set_attr "type"	"imul,imul,multi")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1,1,2")])
-
-;; Split the above insn if we failed to get LO allocated.
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
-			  (match_operand:SI 2 "register_operand" ""))
-		 (match_operand:SI 3 "register_operand" "")))
-   (clobber (match_scratch:SI 4 ""))
-   (clobber (match_scratch:SI 5 ""))
-   (clobber (match_scratch:SI 6 ""))
-   (clobber (match_scratch:SI 7 ""))]
-  "reload_completed && GP_REG_P (true_regnum (operands[0])) && GP_REG_P (true_regnum (operands[3]))"
-  [(parallel [(set (match_dup 7)
-		   (mult:SI (match_dup 1) (match_dup 2)))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))])
-   (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 3)))]
-  "")
-
-;; CYGNUS LOCAL vr5400/raeburn
-(define_insn "*muls_r5400"
-  [(set (match_operand:SI 0 "register_operand" "=l,d")
-	(neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
-			 (match_operand:SI 2 "register_operand" "d,d"))))
-   (clobber (match_scratch:SI 3 "=h,h"))
-   (clobber (match_scratch:SI 4 "=a,a"))
-   (clobber (match_scratch:SI 5 "=X,l"))]
-  "TARGET_MIPS5400"
-  "@
-   muls\\t$0,%1,%2
-   muls\\t%0,%1,%2"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")])
-
-;; See comments above for mul_acc_si.
-(define_insn "*msac_r5400"
-  [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
-	(minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
-		  (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
-			   (match_operand:SI 3 "register_operand" "d,d,d"))))
-   (clobber (match_scratch:SI 4 "=h,h,h"))
-   (clobber (match_scratch:SI 5 "=X,1,l"))
-   (clobber (match_scratch:SI 6 "=a,a,a"))
-   (clobber (match_scratch:SI 7 "=X,X,d"))]
-  "TARGET_MIPS5400"
-  "@
-   msac\\t$0,%2,%3
-   msac\\t%0,%2,%3
-   #"
-  [(set_attr "type"	"imul,imul,multi")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1,1,2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 1 "register_operand" "")
-		  (mult:SI (match_operand:SI 2 "register_operand" "")
-			   (match_operand:SI 3 "register_operand" ""))))
-   (clobber (match_scratch:SI 4 ""))
-   (clobber (match_scratch:SI 5 ""))
-   (clobber (match_scratch:SI 6 ""))
-   (clobber (match_scratch:SI 7 ""))]
-  "reload_completed && GP_REG_P (true_regnum (operands[0])) && GP_REG_P (true_regnum (operands[1]))"
-  [(parallel [(set (match_dup 7)
-		   (mult:SI (match_dup 2) (match_dup 3)))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))])
-   (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 7)))]
-  "")
-;; END CYGNUS LOCAL
-
-(define_expand "muldi3"
-  [(set (match_operand:DI 0 "register_operand" "=l")
-	(mult:DI (match_operand:DI 1 "se_register_operand" "d")
-		 (match_operand:DI 2 "register_operand" "d")))
-   (clobber (match_scratch:DI 3 "=h"))
-   (clobber (match_scratch:DI 4 "=a"))]
-  "TARGET_64BIT && !0" ;;  CYGNUS LOCAL law
-
-  "
-{
-  if (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)
-    emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-;; Don't accept both operands using se_register_operand, because if
-;; both operands are sign extended we would prefer to use mult in the
-;; mulsidi3 pattern.  Commutativity should permit either operand to be
-;; sign extended.
-
-(define_insn "muldi3_internal"
-  [(set (match_operand:DI 0 "register_operand" "=l")
-	(mult:DI (match_operand:DI 1 "se_register_operand" "d")
-		 (match_operand:DI 2 "register_operand" "d")))
-   (clobber (match_scratch:DI 3 "=h"))
-   (clobber (match_scratch:DI 4 "=a"))]
-  "TARGET_64BIT && mips_cpu != PROCESSOR_R4000 && !TARGET_MIPS16 && !0" ;;  CYGNUS LOCAL law
-  "dmult\\t%1,%2"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn "muldi3_internal2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(mult:DI (match_operand:DI 1 "se_register_operand" "d")
-		 (match_operand:DI 2 "register_operand" "d")))
-   (clobber (match_scratch:DI 3 "=h"))
-   (clobber (match_scratch:DI 4 "=l"))
-   (clobber (match_scratch:DI 5 "=a"))]
-  "TARGET_64BIT && (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16) && !0" ;;  CYGNUS LOCAL law
-  "*
-{
-  if (GENERATE_MULT3)
-    output_asm_insn (\"dmult\\t%0,%1,%2\", operands);
-  else 
-    {
-    rtx xoperands[10];
-
-    xoperands[0] = operands[0];
-    xoperands[1] = gen_rtx (REG, DImode, LO_REGNUM);
-
-    output_asm_insn (\"dmult\\t%1,%2\", operands);
-    output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
-    }
-  return \"\";
-}"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"DI")
-   (set (attr "length")
-	(if_then_else (ne (symbol_ref "GENERATE_MULT3") (const_int 0))
-		       (const_int 1)
-		       (const_int 3)))]) 	;; mult + mflo + delay
-
-;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
-
-(define_expand "mulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=x")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
-		 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
-  ""
-  "
-{
-  rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
-  if (TARGET_64BIT)
-    emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
-				   dummy, dummy));
-  else
-    emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2],
-				      dummy, dummy));
-  DONE;
-}")
-
-(define_expand "umulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=x")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
-		 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
-  ""
-  "
-{
-  rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
-  if (TARGET_64BIT)
-    emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
-				   dummy, dummy));
-  else
-    emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2],
-				      dummy, dummy));
-  DONE;
-}")
-
-(define_insn "mulsidi3_internal"
-  [(set (match_operand:DI 0 "register_operand" "=x")
-	(mult:DI (match_operator:DI 3 "extend_operator"
-				    [(match_operand:SI 1 "register_operand" "d")])
-		 (match_operator:DI 4 "extend_operator"
-				    [(match_operand:SI 2 "register_operand" "d")])))
-   (clobber (match_scratch:SI 5 "=a"))]
-  "!TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])"
-  "*
-{
-  if (GET_CODE (operands[3]) == SIGN_EXTEND)
-    return \"mult\\t%1,%2\";
-  return \"multu\\t%1,%2\";
-}"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-
-(define_insn "mulsidi3_64bit"
-  [(set (match_operand:DI 0 "register_operand" "=a")
-	(mult:DI (match_operator:DI 3 "extend_operator"
-				    [(match_operand:SI 1 "register_operand" "d")])
-		 (match_operator:DI 4 "extend_operator"
-				    [(match_operand:SI 2 "register_operand" "d")])))
-   (clobber (match_scratch:DI 5 "=l"))
-   (clobber (match_scratch:DI 6 "=h"))]
-  "TARGET_64BIT && !0 && GET_CODE (operands[3]) == GET_CODE (operands[4])" ;;  CYGNUS LOCAL law
-  "*
-{
-  if (GET_CODE (operands[3]) == SIGN_EXTEND)
-    return \"mult\\t%1,%2\";
-  return \"multu\\t%1,%2\";
-}"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-;; CYGNUS LOCAL vr5400/raeburn
-
-;; widening multiply with accumulator and/or negation
-;; These don't match yet for zero-extending; too complex for combine?
-;; Possible additions we should have:
-;;  "=x" variants for when !TARGET_64BIT ?
-;;  all-d alternatives with splits like pure SImode versions
-(define_insn "*muls_r5400_di"
-  [(set (match_operand:DI 0 "register_operand" "=a")
-	(neg:DI
-	 (mult:DI (match_operator:DI 3 "extend_operator"
-				     [(match_operand:SI 1 "register_operand" "d")])
-		  (match_operator:DI 4 "extend_operator"
-				     [(match_operand:SI 2 "register_operand" "d")]))))
-   (clobber (match_scratch:SI 5 "=h"))
-   (clobber (match_scratch:SI 6 "=l"))]
-  "TARGET_64BIT && TARGET_MIPS5400 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
-  "*
-{
-  if (GET_CODE (operands[3]) == SIGN_EXTEND)
-    return \"muls\\t$0,%1,%2\";
-  else
-    return \"mulsu\\t$0,%1,%2\";
-}"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")])
-
-(define_insn "*msac_r5400_di"
-  [(set (match_operand:DI 0 "register_operand" "=a")
-	(minus:DI (match_operand:DI 3 "register_operand" "0")
-		  (mult:DI (match_operator:DI 4 "extend_operator"
-					      [(match_operand:SI 1 "register_operand" "d")])
-			   (match_operator:DI 5 "extend_operator"
-					      [(match_operand:SI 2 "register_operand" "d")]))))
-   (clobber (match_scratch:SI 6 "=h"))
-   (clobber (match_scratch:SI 7 "=l"))]
-  "TARGET_64BIT && TARGET_MIPS5400 && GET_CODE (operands[4]) == GET_CODE (operands[5])"
-  "*
-{
-  if (GET_CODE (operands[4]) == SIGN_EXTEND)
-    return \"msac\\t$0,%1,%2\";
-  else
-    return \"msacu\\t$0,%1,%2\";
-}"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")])
-;; END CYGNUS LOCAL
-
-;; _highpart patterns
-(define_expand "smulsi3_highpart"
-  [(set (match_operand:SI 0 "register_operand" "=h")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
-			       (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
-		      (const_int 32))))]
-  ""
-  "
-{
-  rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
-  rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
-#ifndef NO_MD_PROTOTYPES
-  rtx (*genfn) PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
-#else
-  rtx (*genfn) ();
-#endif
-  genfn = gen_xmulsi3_highpart_internal;
-  /* CYGNUS LOCAL vr5400/raeburn */
-  if (TARGET_MIPS5400)
-    genfn = gen_xmulsi3_highpart_5400;
-  /* END CYGNUS LOCAL */
-  emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
-		       dummy, dummy2));
-  DONE;
-}")
-
-(define_expand "umulsi3_highpart"
-  [(set (match_operand:SI 0 "register_operand" "=h")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
-			       (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
-		      (const_int 32))))]
-  ""
-  "
-{
-  rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
-  rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
-#ifndef NO_MD_PROTOTYPES
-  rtx (*genfn) PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
-#else
-  rtx (*genfn) ();
-#endif
-  genfn = gen_xmulsi3_highpart_internal;
-  /* CYGNUS LOCAL vr5400/raeburn */
-  if (TARGET_MIPS5400)
-    genfn = gen_xmulsi3_highpart_5400;
-  /* END CYGNUS LOCAL */
-  emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
-		       dummy, dummy2));
-  DONE;
-}")
-
-
-(define_insn "xmulsi3_highpart_internal"
-  [(set (match_operand:SI 0 "register_operand" "=h")
-	(truncate:SI
-	 (match_operator:DI 5 "highpart_shift_operator"
-			    [(mult:DI (match_operator:DI 3 "extend_operator"
-							 [(match_operand:SI 1 "register_operand" "d")])
-				      (match_operator:DI 4 "extend_operator"
-							 [(match_operand:SI 2 "register_operand" "d")]))
-			     (const_int 32)])))
-   (clobber (match_scratch:SI 6 "=l"))
-   (clobber (match_scratch:SI 7 "=a"))]
-  "! TARGET_MIPS5400 && !0 && GET_CODE (operands[3]) == GET_CODE (operands[4])" ;; CYGNUS LOCAL vr5400/raeburn ;;  CYGNUS LOCAL law
-  "*
-{
-  if (GET_CODE (operands[3]) == SIGN_EXTEND)
-    return \"mult\\t%1,%2\";
-  else
-    return \"multu\\t%1,%2\";
-}"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-;; CYGNUS LOCAL vr5400/raeburn
-(define_insn "xmulsi3_highpart_5400"
-  [(set (match_operand:SI 0 "register_operand" "=h,d")
-	(truncate:SI
-	 (match_operator:DI 5 "highpart_shift_operator"
-			    [(mult:DI (match_operator:DI 3 "extend_operator"
-							 [(match_operand:SI 1 "register_operand" "d,d")])
-				      (match_operator:DI 4 "extend_operator"
-							 [(match_operand:SI 2 "register_operand" "d,d")]))
-			     (const_int 32)])))
-   (clobber (match_scratch:SI 6 "=l,l"))
-   (clobber (match_scratch:SI 7 "=a,a"))
-   (clobber (match_scratch:SI 8 "=X,h"))]
-  "TARGET_MIPS5400 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
-  "*
-{
-  char *const sign[] = { \"mult\\t%1,%2\",  \"mulhi\\t%0,%1,%2\"  };
-  char *const zero[] = { \"multu\\t%1,%2\", \"mulhiu\\t%0,%1,%2\" };
-  if (GET_CODE (operands[3]) == SIGN_EXTEND)
-    return sign[which_alternative];
-  else
-    return zero[which_alternative];
-}"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn "*xmulsi3_neg_highpart_5400"
-  [(set (match_operand:SI 0 "register_operand" "=h,d")
-	(truncate:SI
-	 (match_operator:DI 5 "highpart_shift_operator"
-			    [(neg:DI
-			      (mult:DI (match_operator:DI 3 "extend_operator"
-							  [(match_operand:SI 1 "register_operand" "d,d")])
-				       (match_operator:DI 4 "extend_operator"
-							  [(match_operand:SI 2 "register_operand" "d,d")])))
-			     (const_int 32)])))
-   (clobber (match_scratch:SI 6 "=l,l"))
-   (clobber (match_scratch:SI 7 "=a,a"))
-   (clobber (match_scratch:SI 8 "=X,h"))]
-  "TARGET_MIPS5400 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
-  "*
-{
-  char *const sign[] = { \"mulshi\\t$0,%1,%2\",  \"mulshi\\t%0,%1,%2\"  };
-  char *const zero[] = { \"mulshiu\\t$0,%1,%2\", \"mulshiu\\t%0,%1,%2\" };
-  if (GET_CODE (operands[3]) == SIGN_EXTEND)
-    return sign[which_alternative];
-  else
-    return zero[which_alternative];
-}"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-;; END CYGNUS LOCAL
-
-(define_insn "smuldi3_highpart"
-  [(set (match_operand:DI 0 "register_operand" "=h")
-	(truncate:DI
-	 (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "se_register_operand" "d"))
-			       (sign_extend:TI (match_operand:DI 2 "se_register_operand" "d")))
-		      (const_int 64))))
-   (clobber (match_scratch:DI 3 "=l"))
-   (clobber (match_scratch:DI 4 "=a"))]
-  "TARGET_64BIT && !0" ;;  CYGNUS LOCAL law
-  "dmult\\t%1,%2"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn "umuldi3_highpart"
-  [(set (match_operand:DI 0 "register_operand" "=h")
-	(truncate:DI
-	 (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "se_register_operand" "d"))
-			       (zero_extend:TI (match_operand:DI 2 "se_register_operand" "d")))
-		      (const_int 64))))
-   (clobber (match_scratch:DI 3 "=l"))
-   (clobber (match_scratch:DI 4 "=a"))]
-  "TARGET_64BIT && !0" ;;  CYGNUS LOCAL law
-  "dmultu\\t%1,%2"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
-;; instruction.  The HI/LO registers are used as a 64 bit accumulator.
-
-(define_insn "madsi"
-  [(set (match_operand:SI 0 "register_operand" "+l")
-	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
-			  (match_operand:SI 2 "register_operand" "d"))
-		 (match_dup 0)))
-   (clobber (match_scratch:SI 3 "=h"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "TARGET_MAD"
-  "mad\\t%1,%2"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")
-   (set_attr "length"   "1")])
-
-(define_insn "*mul_acc_di"
-  [(set (match_operand:DI 0 "register_operand" "+x")
-	(plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
-			   [(match_operand:SI 1 "register_operand" "d")])
-			  (match_operator:DI 4 "extend_operator"
-			   [(match_operand:SI 2 "register_operand" "d")]))
-		 (match_dup 0)))
-   (clobber (match_scratch:SI 5 "=a"))]
-  "TARGET_MAD
-   && ! TARGET_64BIT
-   && GET_CODE (operands[3]) == GET_CODE (operands[4])"
-  "*
-{
-  if (GET_CODE (operands[3]) == SIGN_EXTEND)
-    return \"mad\\t%1,%2\";
-  else
-    return \"madu\\t%1,%2\";
-}"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")
-   (set_attr "length"   "1")])
-
-(define_insn "*mul_acc_64bit_di"
-  [(set (match_operand:DI 0 "register_operand" "+a")
-	(plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
-			   [(match_operand:SI 1 "register_operand" "d")])
-			  (match_operator:DI 4 "extend_operator"
-			   [(match_operand:SI 2 "register_operand" "d")]))
-		 (match_dup 0)))
-   (clobber (match_scratch:SI 5 "=h"))
-   (clobber (match_scratch:SI 6 "=l"))]
-  "(TARGET_MAD || TARGET_MIPS5400) /* CYGNUS LOCAL vr5400/raeburn */
-   && TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])"
-  "*
-{
-  if (TARGET_MAD)
-    {
-      if (GET_CODE (operands[3]) == SIGN_EXTEND)
-	return \"mad\\t%1,%2\";
-      else
-	return \"madu\\t%1,%2\";
-    }
-  /* CYGNUS LOCAL vr5400/raeburn */
-  else if (TARGET_MIPS5400)
-    {
-      if (GET_CODE (operands[3]) == SIGN_EXTEND)
-	return \"macc\\t$0,%1,%2\";
-      else
-	return \"maccu\\t$0,%1,%2\";
-    }
-  /* END CYGNUS LOCAL */
-  else
-    abort ();
-}"
-  [(set_attr "type"	"imul")
-   (set_attr "mode"	"SI")
-   (set_attr "length"   "1")])
-
-;; Floating point multiply accumulate instructions.
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
-			  (match_operand:DF 2 "register_operand" "f"))
-		 (match_operand:DF 3 "register_operand" "f")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "madd.d\\t%0,%3,%1,%2"
-  [(set_attr "type"	"fmadd")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
-			  (match_operand:SF 2 "register_operand" "f"))
-		 (match_operand:SF 3 "register_operand" "f")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "madd.s\\t%0,%3,%1,%2"
-  [(set_attr "type"	"fmadd")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
-			   (match_operand:DF 2 "register_operand" "f"))
-		  (match_operand:DF 3 "register_operand" "f")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "msub.d\\t%0,%3,%1,%2"
-  [(set_attr "type"	"fmadd")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
-			   (match_operand:SF 2 "register_operand" "f"))
-		  (match_operand:SF 3 "register_operand" "f")))]
-		  
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "msub.s\\t%0,%3,%1,%2"
-  [(set_attr "type"	"fmadd")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
-				  (match_operand:DF 2 "register_operand" "f"))
-			 (match_operand:DF 3 "register_operand" "f"))))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "nmadd.d\\t%0,%3,%1,%2"
-  [(set_attr "type"	"fmadd")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
-				  (match_operand:SF 2 "register_operand" "f"))
-			 (match_operand:SF 3 "register_operand" "f"))))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "nmadd.s\\t%0,%3,%1,%2"
-  [(set_attr "type"	"fmadd")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 1 "register_operand" "f")
-		  (mult:DF (match_operand:DF 2 "register_operand" "f")
-			   (match_operand:DF 3 "register_operand" "f"))))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "nmsub.d\\t%0,%1,%2,%3"
-  [(set_attr "type"	"fmadd")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (match_operand:SF 1 "register_operand" "f")
-		  (mult:SF (match_operand:SF 2 "register_operand" "f")
-			   (match_operand:SF 3 "register_operand" "f"))))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "nmsub.s\\t%0,%1,%2,%3"
-  [(set_attr "type"	"fmadd")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-;;  ....................
-;;	DIVISION and REMAINDER
-;;  ....................
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (match_operand:DF 1 "register_operand" "f")
-		(match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "div.d\\t%0,%1,%2"
-  [(set_attr "type"	"fdiv")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(div:SF (match_operand:SF 1 "register_operand" "f")
-		(match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "div.s\\t%0,%1,%2"
-  [(set_attr "type"	"fdiv")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (match_operand:DF 1 "const_float_1_operand" "")
-		(match_operand:DF 2 "register_operand" "f")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
-  "recip.d\\t%0,%2"
-  [(set_attr "type"	"fdiv")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(div:SF (match_operand:SF 1 "const_float_1_operand" "")
-		(match_operand:SF 2 "register_operand" "f")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math"
-  "recip.s\\t%0,%2"
-  [(set_attr "type"	"fdiv")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-;; If optimizing, prefer the divmod functions over separate div and
-;; mod functions, since this will allow using one instruction for both
-;; the quotient and remainder.  At present, the divmod is not moved out
-;; of loops if it is constant within the loop, so allow -mdebugc to
-;; use the old method of doing things.
-
-;; 64 is the multiply/divide hi register
-;; 65 is the multiply/divide lo register
-
-;; ??? We can't accept constants here, because the MIPS assembler will replace
-;; a divide by power of 2 with a shift, and then the remainder is no longer
-;; available.
-
-(define_expand "divmodsi4"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(div:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "register_operand" "d")))
-   (set (match_operand:SI 3 "register_operand" "=d")
-	(mod:SI (match_dup 1)
-		(match_dup 2)))
-   (clobber (match_scratch:SI 4 "=l"))
-   (clobber (match_scratch:SI 5 "=h"))
-   (clobber (match_scratch:SI 6 "=a"))]
-  "optimize"
-  "
-{
-  rtx label;
-
-
-  emit_insn (gen_divmodsi4_internal (operands[0], operands[1], operands[2],
-	     operands[3]));
-  if (!TARGET_NO_CHECK_ZERO_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       GEN_INT (0),
-			       GEN_INT (0x7)));
-    }
-  if (TARGET_CHECK_RANGE_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (SImode, GEN_INT (-1)),
-			       GEN_INT (0x6)));
-      emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
-			       GEN_INT (0x6)));
-    }
-  
-  DONE;
-}")
-
-
-(define_insn "divmodsi4_internal"
-  [(set (match_operand:SI 0 "register_operand" "=l")
-	(div:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "register_operand" "d")))
-   (set (match_operand:SI 3 "register_operand" "=h")
-	(mod:SI (match_dup 1)
-		(match_dup 2)))
-   (clobber (match_scratch:SI 6 "=a"))]
-  "optimize && !0" ;;  CYGNUS LOCAL law
-  "div\\t$0,%1,%2"
-  [(set_attr "type"	"idiv")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_expand "divmoddi4"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(div:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_register_operand" "d")))
-   (set (match_operand:DI 3 "register_operand" "=d")
-	(mod:DI (match_dup 1)
-		(match_dup 2)))
-   (clobber (match_scratch:DI 4 "=l"))
-   (clobber (match_scratch:DI 5 "=h"))
-   (clobber (match_scratch:DI 6 "=a"))]
-  "TARGET_64BIT && optimize && !0" ;;  CYGNUS LOCAL law
-  "
-{
-  rtx label;
-
-  emit_insn (gen_divmoddi4_internal (operands[0], operands[1], operands[2],
-             operands[3]));
-  if (!TARGET_NO_CHECK_ZERO_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       GEN_INT (0),
-			       GEN_INT (0x7)));
-    }
-  if (TARGET_CHECK_RANGE_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (DImode, GEN_INT (-1)),
-			       GEN_INT (0x6)));
-      emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
-			       GEN_INT (0x6)));
-    }
-  
-  DONE;
-}")
-
-(define_insn "divmoddi4_internal"
-  [(set (match_operand:DI 0 "register_operand" "=l")
-	(div:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_register_operand" "d")))
-   (set (match_operand:DI 3 "register_operand" "=h")
-	(mod:DI (match_dup 1)
-		(match_dup 2)))
-   (clobber (match_scratch:DI 6 "=a"))]
-  "TARGET_64BIT && optimize && !0" ;;  CYGNUS LOCAL law
-  "ddiv\\t$0,%1,%2"
-  [(set_attr "type"	"idiv")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_expand "udivmodsi4"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(udiv:SI (match_operand:SI 1 "register_operand" "d")
-		 (match_operand:SI 2 "register_operand" "d")))
-   (set (match_operand:SI 3 "register_operand" "=d")
-	(umod:SI (match_dup 1)
-		 (match_dup 2)))
-   (clobber (match_scratch:SI 4 "=l"))
-   (clobber (match_scratch:SI 5 "=h"))
-   (clobber (match_scratch:SI 6 "=a"))]
-  "optimize"
-  "
-{
-  rtx label;
-
-  emit_insn (gen_udivmodsi4_internal (operands[0], operands[1], operands[2],
-                                      operands[3]));
-  if (!TARGET_NO_CHECK_ZERO_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       GEN_INT (0),
-			       GEN_INT (0x7)));
-    }
-  
-  DONE;
-}")
-
-
-(define_insn "udivmodsi4_internal"
-  [(set (match_operand:SI 0 "register_operand" "=l")
-	(udiv:SI (match_operand:SI 1 "register_operand" "d")
-		 (match_operand:SI 2 "register_operand" "d")))
-   (set (match_operand:SI 3 "register_operand" "=h")
-	(umod:SI (match_dup 1)
-		 (match_dup 2)))
-   (clobber (match_scratch:SI 6 "=a"))]
-  "optimize && !0" ;;  CYGNUS LOCAL law
-  "divu\\t$0,%1,%2"
-  [(set_attr "type"	"idiv")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_expand "udivmoddi4"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(udiv:DI (match_operand:DI 1 "se_register_operand" "d")
-		 (match_operand:DI 2 "se_register_operand" "d")))
-   (set (match_operand:DI 3 "register_operand" "=d")
-	(umod:DI (match_dup 1)
-		 (match_dup 2)))
-   (clobber (match_scratch:DI 4 "=l"))
-   (clobber (match_scratch:DI 5 "=h"))
-   (clobber (match_scratch:DI 6 "=a"))]
-  "TARGET_64BIT && optimize && !0" ;;  CYGNUS LOCAL law
-  "
-{
-  rtx label;
-
-  emit_insn (gen_udivmoddi4_internal (operands[0], operands[1], operands[2],
-                                      operands[3]));
-  if (!TARGET_NO_CHECK_ZERO_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       GEN_INT (0),
-			       GEN_INT (0x7)));
-    }
-  
-  DONE;
-}")
-
-(define_insn "udivmoddi4_internal"
-  [(set (match_operand:DI 0 "register_operand" "=l")
-	(udiv:DI (match_operand:DI 1 "se_register_operand" "d")
-		 (match_operand:DI 2 "se_register_operand" "d")))
-   (set (match_operand:DI 3 "register_operand" "=h")
-	(umod:DI (match_dup 1)
-		 (match_dup 2)))
-   (clobber (match_scratch:DI 6 "=a"))]
-  "TARGET_64BIT && optimize && !0" ;;  CYGNUS LOCAL law
-  "ddivu\\t$0,%1,%2"
-  [(set_attr "type"	"idiv")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-;; Division trap
-
- ;; Division trap
- 
-(define_expand "div_trap"
-   [(trap_if (eq (match_operand 0 "register_operand" "d")
-		(match_operand 1 "true_reg_or_0_operand" "dJ"))
-             (match_operand 2 "immediate_operand" ""))]
-   ""
-  "
-{
-  if (TARGET_MIPS16)
-    emit_insn (gen_div_trap_mips16 (operands[0],operands[1],operands[2]));
-  else
-    emit_insn (gen_div_trap_normal (operands[0],operands[1],operands[2]));
-  DONE;
-}")
-
-(define_insn "div_trap_normal"
-  [(trap_if (eq (match_operand 0 "register_operand" "d")
-		(match_operand 1 "true_reg_or_0_operand" "dJ"))
-            (match_operand 2 "immediate_operand" ""))]
-  "!TARGET_MIPS16"
-  "*
-{
-  rtx link;
-  int have_dep_anti = 0;
-
-  /* For divmod if one division is not needed then we don't need an extra
-     divide by zero trap, which is anti dependent on previous trap */
-  for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
-
-    if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
-        && GET_CODE (XEXP (link, 0)) == INSN
-        && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
-	&& REGNO (operands[1]) == 0)
-      have_dep_anti = 1;
-  if (! have_dep_anti)
-    {
-      if (GENERATE_BRANCHLIKELY)
-	{
-          if (GET_CODE (operands[1]) == CONST_INT)
-	    return \"%(beql\\t%0,$0,1f\\n\\tbreak\\t%2\\n1:%)\";
-	  else
-	    return \"%(beql\\t%0,%1,1f\\n\\tbreak\\t%2\\n1:%)\";
-	}
-      else
-	{
-          if (GET_CODE (operands[1]) == CONST_INT)
-	    return \"%(bne\\t%0,$0,1f\\n\\tnop\\n\\tbreak\\t%2\\n1:%)\";
-	  else
-	    return \"%(bne\\t%0,%1,1f\\n\\tnop\\n\\tbreak\\t%2\\n1:%)\";
-	}
-    }
-  return \"\";
-}"
-  [(set_attr "type" "unknown")
-   (set_attr "length" "3")])
-
-
-;; The mips16 bne insns is a macro which uses reg 24 as an intermediate.
-
-(define_insn "div_trap_mips16"
-  [(trap_if (eq (match_operand 0 "register_operand" "d")
-		(match_operand 1 "true_reg_or_0_operand" "dJ"))
-            (match_operand 2 "immediate_operand" ""))
-   (clobber (reg:SI 24))]
-  "TARGET_MIPS16"
-  "*
-{
-  rtx link;
-  int have_dep_anti = 0;
-
-  /* For divmod if one division is not needed then we don't need an extra
-     divide by zero trap, which is anti dependent on previous trap */
-  for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
-
-    if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
-        && GET_CODE (XEXP (link, 0)) == INSN
-        && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
-	&& REGNO (operands[1]) == 0)
-      have_dep_anti = 1;
-  if (! have_dep_anti)
-    {
-      /* No branch delay slots on mips16. */ 
-      if (GET_CODE (operands[1]) == CONST_INT)
-        return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n1:%)\";
-      else
-        return \"%(bne\\t%0,%1,1f\\n\\tbreak\\t%2\\n1:%)\";
-    }
-  return \"\";
-}"
-  [(set_attr "type" "unknown")
-   (set_attr "length" "3")])
-
-(define_expand "divsi3"
-  [(set (match_operand:SI 0 "register_operand" "=l")
-	(div:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "register_operand" "d")))
-   (clobber (match_scratch:SI 3 "=h"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "!optimize"
-  "
-{
-  rtx label;
-
-  emit_insn (gen_divsi3_internal (operands[0], operands[1], operands[2]));
-  if (!TARGET_NO_CHECK_ZERO_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       GEN_INT (0),
-			       GEN_INT (0x7)));
-    }
-  if (TARGET_CHECK_RANGE_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (SImode, GEN_INT (-1)),
-			       GEN_INT (0x6)));
-      emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
-			       GEN_INT (0x6)));
-    }
-  
-  DONE;
-}")
-
-(define_insn "divsi3_internal"
-  [(set (match_operand:SI 0 "register_operand" "=l")
-	(div:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "nonmemory_operand" "di")))
-   (clobber (match_scratch:SI 3 "=h"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "!optimize"
-  "div\\t$0,%1,%2"
-  [(set_attr "type"	"idiv")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_expand "divdi3"
-  [(set (match_operand:DI 0 "register_operand" "=l")
-	(div:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_register_operand" "d"))) 
-   (clobber (match_scratch:DI 3 "=h"))
-   (clobber (match_scratch:DI 4 "=a"))]
-  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
-  "
-{
-  rtx label;
-
-  emit_insn (gen_divdi3_internal (operands[0], operands[1], operands[2]));
-  if (!TARGET_NO_CHECK_ZERO_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       GEN_INT (0),
-			       GEN_INT (0x7)));
-    }
-  if (TARGET_CHECK_RANGE_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (DImode, GEN_INT (-1)),
-			       GEN_INT (0x6)));
-      emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
-			       GEN_INT (0x6)));
-    }
-  
-  DONE;
-}")
-
-(define_insn "divdi3_internal"
-  [(set (match_operand:DI 0 "register_operand" "=l")
-	(div:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_nonmemory_operand" "di")))
-   (clobber (match_scratch:SI 3 "=h"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
-  "ddiv\\t$0,%1,%2"
-  [(set_attr "type"	"idiv")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_expand "modsi3"
-  [(set (match_operand:SI 0 "register_operand" "=h")
-	(mod:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "register_operand" "d")))
-   (clobber (match_scratch:SI 3 "=l"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "!optimize"
-  "
-{
-  rtx label;
-
-  emit_insn (gen_modsi3_internal (operands[0], operands[1], operands[2]));
-  if (!TARGET_NO_CHECK_ZERO_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       GEN_INT (0),
-			       GEN_INT (0x7)));
-    }
-  if (TARGET_CHECK_RANGE_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (SImode, GEN_INT (-1)),
-			       GEN_INT (0x6)));
-      emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
-			       GEN_INT (0x6)));
-    }
-  
-  DONE;
-}")
-
-(define_insn "modsi3_internal"
-  [(set (match_operand:SI 0 "register_operand" "=h")
-	(mod:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "nonmemory_operand" "di")))
-   (clobber (match_scratch:SI 3 "=l"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "!optimize"
-  "div\\t$0,%1,%2"
-  [(set_attr "type"	"idiv")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_expand "moddi3"
-  [(set (match_operand:DI 0 "register_operand" "=h")
-	(mod:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_register_operand" "d")))
-   (clobber (match_scratch:DI 3 "=l"))
-   (clobber (match_scratch:DI 4 "=a"))]
-  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
-  "
-{
-  rtx label;
-
-  emit_insn (gen_moddi3_internal (operands[0], operands[1], operands[2]));
-  if (!TARGET_NO_CHECK_ZERO_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       GEN_INT (0),
-			       GEN_INT (0x7)));
-    }
-  if (TARGET_CHECK_RANGE_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (DImode, GEN_INT (-1)),
-			       GEN_INT (0x6)));
-      emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
-			       GEN_INT (0x6)));
-    }
-  
-  DONE;
-}")
-
-(define_insn "moddi3_internal"
-  [(set (match_operand:DI 0 "register_operand" "=h")
-	(mod:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_nonmemory_operand" "di")))
-   (clobber (match_scratch:SI 3 "=l"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
-  "ddiv\\t$0,%1,%2"
-  [(set_attr "type"	"idiv")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_expand "udivsi3"
-  [(set (match_operand:SI 0 "register_operand" "=l")
-	(udiv:SI (match_operand:SI 1 "register_operand" "d")
-		 (match_operand:SI 2 "register_operand" "d")))
-   (clobber (match_scratch:SI 3 "=h"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "!optimize"
-  "
-{
-  rtx label;
-
-  emit_insn (gen_udivsi3_internal (operands[0], operands[1], operands[2]));
-  if (!TARGET_NO_CHECK_ZERO_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       GEN_INT (0),
-			       GEN_INT (0x7)));
-    }
-  
-  DONE;
-}")
-
-(define_insn "udivsi3_internal"
-  [(set (match_operand:SI 0 "register_operand" "=l")
-	(udiv:SI (match_operand:SI 1 "register_operand" "d")
-		 (match_operand:SI 2 "nonmemory_operand" "di")))
-   (clobber (match_scratch:SI 3 "=h"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "!optimize"
-  "divu\\t$0,%1,%2"
-  [(set_attr "type"	"idiv")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_expand "udivdi3"
-  [(set (match_operand:DI 0 "register_operand" "=l")
-	(udiv:DI (match_operand:DI 1 "se_register_operand" "d")
-		 (match_operand:DI 2 "se_register_operand" "di")))
-   (clobber (match_scratch:DI 3 "=h"))
-   (clobber (match_scratch:DI 4 "=a"))]
-  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
-  "
-{
-  rtx label;
-
-  emit_insn (gen_udivdi3_internal (operands[0], operands[1], operands[2]));
-  if (!TARGET_NO_CHECK_ZERO_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       GEN_INT (0),
-			       GEN_INT (0x7)));
-    }
-  
-  DONE;
-}")
-
-(define_insn "udivdi3_internal"
-  [(set (match_operand:DI 0 "register_operand" "=l")
-	(udiv:DI (match_operand:DI 1 "se_register_operand" "d")
-		 (match_operand:DI 2 "se_nonmemory_operand" "di")))
-   (clobber (match_scratch:SI 3 "=h"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
-  "ddivu\\t$0,%1,%2"
-  [(set_attr "type"	"idiv")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_expand "umodsi3"
-  [(set (match_operand:SI 0 "register_operand" "=h")
-	(umod:SI (match_operand:SI 1 "register_operand" "d")
-		 (match_operand:SI 2 "register_operand" "d")))
-   (clobber (match_scratch:SI 3 "=l"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "!optimize"
-  "
-{
-  rtx label;
-
-  emit_insn (gen_umodsi3_internal (operands[0], operands[1], operands[2]));
-  if (!TARGET_NO_CHECK_ZERO_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       GEN_INT (0),
-			       GEN_INT (0x7)));
-    }
-  
-  DONE;
-}")
-
-(define_insn "umodsi3_internal"
-  [(set (match_operand:SI 0 "register_operand" "=h")
-	(umod:SI (match_operand:SI 1 "register_operand" "d")
-		 (match_operand:SI 2 "nonmemory_operand" "di")))
-   (clobber (match_scratch:SI 3 "=l"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "!optimize"
-  "divu\\t$0,%1,%2"
-  [(set_attr "type"	"idiv")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_expand "umoddi3"
-  [(set (match_operand:DI 0 "register_operand" "=h")
-	(umod:DI (match_operand:DI 1 "se_register_operand" "d")
-		 (match_operand:DI 2 "se_register_operand" "di")))
-   (clobber (match_scratch:DI 3 "=l"))
-   (clobber (match_scratch:DI 4 "=a"))]
-  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
-  "
-{
-  rtx label;
-
-  emit_insn (gen_umoddi3_internal (operands[0], operands[1], operands[2]));
-  if (!TARGET_NO_CHECK_ZERO_DIV)
-    {
-      emit_insn (gen_div_trap (operands[2],
-			       GEN_INT (0),
-			       GEN_INT (0x7)));
-    }
-  
-  DONE;
-}")
-
-(define_insn "umoddi3_internal"
-  [(set (match_operand:DI 0 "register_operand" "=h")
-	(umod:DI (match_operand:DI 1 "se_register_operand" "d")
-		 (match_operand:DI 2 "se_nonmemory_operand" "di")))
-   (clobber (match_scratch:SI 3 "=l"))
-   (clobber (match_scratch:SI 4 "=a"))]
-  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
-  "ddivu\\t$0,%1,%2"
-  [(set_attr "type"	"idiv")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-;;  ....................
-;;	SQUARE ROOT
-;;  ....................
-
-(define_insn "sqrtdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT"
-  "sqrt.d\\t%0,%1"
-  [(set_attr "type"	"fsqrt")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn "sqrtsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
-  "sqrt.s\\t%0,%1"
-  [(set_attr "type"	"fsqrt")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (match_operand:DF 1 "const_float_1_operand" "")
-		(sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
-  "rsqrt.d\\t%0,%2"
-  [(set_attr "type"	"frsqrt") ; CYGNUS LOCAL vr5400/raeburn
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(div:SF (match_operand:SF 1 "const_float_1_operand" "")
-		(sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math"
-  "rsqrt.s\\t%0,%2"
-  [(set_attr "type"	"frsqrt") ; CYGNUS LOCAL vr5400/raeburn
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-
-;;  ....................
-;;	ABSOLUTE VALUE
-;;  ....................
-
-;; Do not use the integer abs macro instruction, since that signals an
-;; exception on -2147483648 (sigh).
-
-(define_insn "abssi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(abs:SI (match_operand:SI 1 "register_operand" "d")))]
-  "!TARGET_MIPS16"
-  "*
-{
-  dslots_jump_total++;
-  dslots_jump_filled++;
-  operands[2] = const0_rtx;
-
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    {
-      if (GENERATE_BRANCHLIKELY)
-	return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n1:%)\";
-      else
-	return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n1:\";
-    }	  
-  else
-    return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n1:%)\";
-}"
-  [(set_attr "type"	"multi")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"3")])
-
-(define_insn "absdi2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(abs:DI (match_operand:DI 1 "se_register_operand" "d")))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "*
-{
-  dslots_jump_total++;
-  dslots_jump_filled++;
-  operands[2] = const0_rtx;
-
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"%(bltzl\\t%1,1f\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\";
-  else
-    return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\";
-}"
-  [(set_attr "type"	"multi")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"3")])
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(abs:DF (match_operand:DF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "abs.d\\t%0,%1"
-  [(set_attr "type"	"fabs")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(abs:SF (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "abs.s\\t%0,%1"
-  [(set_attr "type"	"fabs")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-
-;;  ....................
-;;	FIND FIRST BIT INSTRUCTION
-;;  ....................
-
-(define_insn "ffssi2"
-  [(set (match_operand:SI 0 "register_operand" "=&d")
-	(ffs:SI (match_operand:SI 1 "register_operand" "d")))
-   (clobber (match_scratch:SI 2 "=&d"))
-   (clobber (match_scratch:SI 3 "=&d"))]
-  "!TARGET_MIPS16"
-  "*
-{
-  dslots_jump_total += 2;
-  dslots_jump_filled += 2;
-  operands[4] = const0_rtx;
-
-  if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
-    return \"%(\\
-move\\t%0,%z4\\n\\
-\\tbeq\\t%1,%z4,2f\\n\\
-1:\\tand\\t%2,%1,0x0001\\n\\
-\\taddu\\t%0,%0,1\\n\\
-\\tbeq\\t%2,%z4,1b\\n\\
-\\tsrl\\t%1,%1,1\\n\\
-2:%)\";
-
-  return \"%(\\
-move\\t%0,%z4\\n\\
-\\tmove\\t%3,%1\\n\\
-\\tbeq\\t%3,%z4,2f\\n\\
-1:\\tand\\t%2,%3,0x0001\\n\\
-\\taddu\\t%0,%0,1\\n\\
-\\tbeq\\t%2,%z4,1b\\n\\
-\\tsrl\\t%3,%3,1\\n\\
-2:%)\";
-}"
-  [(set_attr "type"	"multi")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"6")])
-
-(define_insn "ffsdi2"
-  [(set (match_operand:DI 0 "register_operand" "=&d")
-	(ffs:DI (match_operand:DI 1 "se_register_operand" "d")))
-   (clobber (match_scratch:DI 2 "=&d"))
-   (clobber (match_scratch:DI 3 "=&d"))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "*
-{
-  dslots_jump_total += 2;
-  dslots_jump_filled += 2;
-  operands[4] = const0_rtx;
-
-  if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
-    return \"%(\\
-move\\t%0,%z4\\n\\
-\\tbeq\\t%1,%z4,2f\\n\\
-1:\\tand\\t%2,%1,0x0001\\n\\
-\\tdaddu\\t%0,%0,1\\n\\
-\\tbeq\\t%2,%z4,1b\\n\\
-\\tdsrl\\t%1,%1,1\\n\\
-2:%)\";
-
-  return \"%(\\
-move\\t%0,%z4\\n\\
-\\tmove\\t%3,%1\\n\\
-\\tbeq\\t%3,%z4,2f\\n\\
-1:\\tand\\t%2,%3,0x0001\\n\\
-\\tdaddu\\t%0,%0,1\\n\\
-\\tbeq\\t%2,%z4,1b\\n\\
-\\tdsrl\\t%3,%3,1\\n\\
-2:%)\";
-}"
-  [(set_attr "type"	"multi")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"6")])
-
-
-;;  ....................
-;;	NEGATION and ONE'S COMPLEMENT
-;;  ....................
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(neg:SI (match_operand:SI 1 "register_operand" "d")))]
-  ""
-  "*
-{
-  if (TARGET_MIPS16)
-    return \"neg\\t%0,%1\";
-  operands[2] = const0_rtx;
-  return \"subu\\t%0,%z2,%1\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_expand "negdi2"
-  [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
-		   (neg:DI (match_operand:DI 1 "se_register_operand" "d")))
-	      (clobber (match_dup 2))])]
-  "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
-  "
-{
-  if (TARGET_64BIT)
-    {
-      emit_insn (gen_negdi2_internal_2 (operands[0], operands[1]));
-      DONE;
-    }
-
-  operands[2] = gen_reg_rtx (SImode);
-}")
-
-(define_insn "negdi2_internal"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(neg:DI (match_operand:DI 1 "register_operand" "d")))
-   (clobber (match_operand:SI 2 "register_operand" "=d"))]
-  "! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-  "*
-{
-  operands[3] = const0_rtx;
-  return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4")])
-
-(define_insn "negdi2_internal_2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(neg:DI (match_operand:DI 1 "se_register_operand" "d")))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "*
-{
-  operands[2] = const0_rtx;
-  return \"dsubu\\t%0,%z2,%1\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (match_operand:DF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "neg.d\\t%0,%1"
-  [(set_attr "type"	"fneg")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "neg.s\\t%0,%1"
-  [(set_attr "type"	"fneg")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(not:SI (match_operand:SI 1 "register_operand" "d")))]
-  ""
-  "*
-{
-  if (TARGET_MIPS16)
-    return \"not\\t%0,%1\";
-  operands[2] = const0_rtx;
-  return \"nor\\t%0,%z2,%1\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn "one_cmpldi2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(not:DI (match_operand:DI 1 "se_register_operand" "d")))]
-  ""
-  "*
-{
-  if (TARGET_MIPS16)
-    {
-      if (TARGET_64BIT)
-	return \"not\\t%0,%1\";
-      return \"not\\t%M0,%M1\;not\\t%L0,%L1\";
-    }
-  operands[2] = const0_rtx;
-  if (TARGET_64BIT)
-    return \"nor\\t%0,%z2,%1\";
-  return \"nor\\t%M0,%z2,%M1\;nor\\t%L0,%z2,%L1\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")
-	(if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
-		       (const_int 1)
-		       (const_int 2)))])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(not:DI (match_operand:DI 1 "register_operand" "")))]
-  "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
-
-  [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
-   (set (subreg:SI (match_dup 0) 1) (not:SI (subreg:SI (match_dup 1) 1)))]
-  "")
-
-
-;;  ....................
-;;	LOGICAL
-;;  ....................
-
-;; Many of these instructions uses trivial define_expands, because we
-;; want to use a different set of constraints when TARGET_MIPS16.
-
-(define_expand "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
-		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
-  ""
-  "
-{
-  if (TARGET_MIPS16)
-    operands[2] = force_reg (SImode, operands[2]);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
-		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
-  "!TARGET_MIPS16"
-  "@
-   and\\t%0,%1,%2
-   andi\\t%0,%1,%x2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(and:SI (match_operand:SI 1 "register_operand" "%0")
-		(match_operand:SI 2 "register_operand" "d")))]
-  "TARGET_MIPS16"
-  "and\\t%0,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_expand "anddi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(and:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_register_operand" "d")))]
-  "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
-  "
-{
-  if (TARGET_MIPS16)
-    operands[2] = force_reg (DImode, operands[2]);
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(and:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_register_operand" "d")))]
-  "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
-  "*
-{
-  if (TARGET_64BIT)
-    return \"and\\t%0,%1,%2\";
-  return \"and\\t%M0,%M1,%M2\;and\\t%L0,%L1,%L2\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")
-	(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
-		       (const_int 1)
-		       (const_int 2)))])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(and:DI (match_operand:DI 1 "se_register_operand" "0")
-		(match_operand:DI 2 "se_register_operand" "d")))]
-  "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && TARGET_MIPS16"
-  "*
-{
-  if (TARGET_64BIT)
-    return \"and\\t%0,%2\";
-  return \"and\\t%M0,%M2\;and\\t%L0,%L2\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")
-	(if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
-		       (const_int 1)
-		       (const_int 2)))])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(and:DI (match_operand:DI 1 "register_operand" "")
-		(match_operand:DI 2 "register_operand" "")))]
-  "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
-  [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
-   (set (subreg:SI (match_dup 0) 1) (and:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
-  "")
-
-(define_insn "anddi3_internal1"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(and:DI (match_operand:DI 1 "se_register_operand" "%d,d")
-		(match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "@
-   and\\t%0,%1,%2
-   andi\\t%0,%1,%x2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_expand "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
-		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
-  ""
-  "
-{
-  if (TARGET_MIPS16)
-    operands[2] = force_reg (SImode, operands[2]);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
-		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
-  "!TARGET_MIPS16"
-  "@
-   or\\t%0,%1,%2
-   ori\\t%0,%1,%x2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ior:SI (match_operand:SI 1 "register_operand" "%0")
-		(match_operand:SI 2 "register_operand" "d")))]
-  "TARGET_MIPS16"
-  "or\\t%0,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-;;; ??? There is no iordi3 pattern which accepts 'K' constants when
-;;; TARGET_64BIT
-
-(define_expand "iordi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ior:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_register_operand" "d")))]
-  "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ior:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_register_operand" "d")))]
-  "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
-  "*
-{
-  if (TARGET_64BIT)
-    return \"or\\t%0,%1,%2\";
-  return \"or\\t%M0,%M1,%M2\;or\\t%L0,%L1,%L2\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")
-	(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
-		       (const_int 1)
-		       (const_int 2)))])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ior:DI (match_operand:DI 1 "se_register_operand" "0")
-		(match_operand:DI 2 "se_register_operand" "d")))]
-  "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && TARGET_MIPS16"
-  "*
-{
-  if (TARGET_64BIT)
-    return \"or\\t%0,%2\";
-  return \"or\\t%M0,%M2\;or\\t%L0,%L2\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")
-	(if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
-		       (const_int 1)
-		       (const_int 2)))])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ior:DI (match_operand:DI 1 "register_operand" "")
-		(match_operand:DI 2 "register_operand" "")))]
-  "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
-  [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
-   (set (subreg:SI (match_dup 0) 1) (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
-  "")
-
-(define_expand "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
-		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
-		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
-  "!TARGET_MIPS16"
-  "@
-   xor\\t%0,%1,%2
-   xori\\t%0,%1,%x2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,t,t")
-	(xor:SI (match_operand:SI 1 "uns_arith_operand" "%0,d,d")
-		(match_operand:SI 2 "uns_arith_operand" "d,K,d")))]
-  "TARGET_MIPS16"
-  "@
-   xor\\t%0,%2
-   cmpi\\t%1,%2
-   cmp\\t%1,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (const_int 1)])])
-
-;; ??? If delete the 32-bit long long patterns, then could merge this with
-;; the following xordi3_internal pattern.
-(define_expand "xordi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(xor:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_register_operand" "d")))]
-  "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(xor:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_register_operand" "d")))]
-  "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
-  "*
-{
-  if (TARGET_64BIT)
-    return \"xor\\t%0,%1,%2\";
-  return \"xor\\t%M0,%M1,%M2\;xor\\t%L0,%L1,%L2\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")
-	(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
-		       (const_int 1)
-		       (const_int 2)))])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(xor:DI (match_operand:DI 1 "se_register_operand" "0")
-		(match_operand:DI 2 "se_register_operand" "d")))]
-  "!TARGET_64BIT && TARGET_MIPS16"
-  "xor\\t%M0,%M2\;xor\\t%L0,%L2"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"2")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,t,t")
-	(xor:DI (match_operand:DI 1 "se_register_operand" "%0,d,d")
-		(match_operand:DI 2 "se_uns_arith_operand" "d,K,d")))]
-  "TARGET_64BIT && TARGET_MIPS16"
-  "@
-   xor\\t%0,%2
-   cmpi\\t%1,%2
-   cmp\\t%1,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (const_int 1)])])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(xor:DI (match_operand:DI 1 "register_operand" "")
-		(match_operand:DI 2 "register_operand" "")))]
-  "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
-  [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
-   (set (subreg:SI (match_dup 0) 1) (xor:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
-  "")
-
-(define_insn "xordi3_immed"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(xor:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_uns_arith_operand" "K")))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "xori\\t%0,%1,%x2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn "*norsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
-		(not:SI (match_operand:SI 2 "register_operand" "d"))))]
-  "!TARGET_MIPS16"
-  "nor\\t%0,%z1,%z2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn "*nordi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(and:DI (not:DI (match_operand:DI 1 "se_register_operand" "d"))
-		(not:DI (match_operand:DI 2 "se_register_operand" "d"))))]
-  "!TARGET_MIPS16"
-  "*
-{
-  if (TARGET_64BIT)
-    return \"nor\\t%0,%z1,%z2\";
-  return \"nor\\t%M0,%M1,%M2\;nor\\t%L0,%L1,%L2\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")
-	(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
-		       (const_int 1)
-		       (const_int 2)))])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(and:DI (not:DI (match_operand:DI 1 "register_operand" ""))
-		(not:DI (match_operand:DI 2 "register_operand" ""))))]
-  "reload_completed && !TARGET_MIPS16 && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
-  [(set (subreg:SI (match_dup 0) 0) (and:SI (not:SI (subreg:SI (match_dup 1) 0)) (not:SI (subreg:SI (match_dup 2) 0))))
-   (set (subreg:SI (match_dup 0) 1) (and:SI (not:SI (subreg:SI (match_dup 1) 1)) (not:SI (subreg:SI (match_dup 2) 1))))]
-  "")
-
-;;  ....................
-;;	TRUNCATION
-;;  ....................
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "cvt.s.d\\t%0,%1"
-  [(set_attr "type"	"fcvt")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_insn "truncdisi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI (match_operand:DI 1 "se_register_operand" "d")))]
-  "TARGET_64BIT"
-  "*
-{
-  if (TARGET_MIPS16)
-    return \"dsll\\t%0,%1,32\;dsra\\t%0,32\";
-  return \"dsll\\t%0,%1,32\;dsra\\t%0,%0,32\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"SI")
-   (set (attr "length")	(if_then_else (eq (symbol_ref "mips16") (const_int 0))
-				      (const_int 2)
-				      (const_int 4)))])
-
-(define_insn "truncdihi2"
-  [(set (match_operand:HI 0 "register_operand" "=d")
-	(truncate:HI (match_operand:DI 1 "se_register_operand" "d")))]
-  "TARGET_64BIT"
-  "*
-{
-  if (TARGET_MIPS16)
-    return \"dsll\\t%0,%1,48\;dsra\\t%0,48\";
-  return \"andi\\t%0,%1,0xffff\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"HI")
-   (set (attr "length")	(if_then_else (eq (symbol_ref "mips16") (const_int 0))
-				      (const_int 1)
-				      (const_int 4)))])
-(define_insn "truncdiqi2"
-  [(set (match_operand:QI 0 "register_operand" "=d")
-	(truncate:QI (match_operand:DI 1 "se_register_operand" "d")))]
-  "TARGET_64BIT"
-  "*
-{
-  if (TARGET_MIPS16)
-    return \"dsll\\t%0,%1,56\;dsra\\t%0,56\";
-  return \"andi\\t%0,%1,0x00ff\"; 
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"QI")
-   (set (attr "length")	(if_then_else (eq (symbol_ref "mips16") (const_int 0))
-				      (const_int 1)
-				      (const_int 4)))])
-
-;; Combiner patterns to optimize shift/truncate combinations.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
-				  (match_operand:DI 2 "small_int" "I"))))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "*
-{
-  int shift_amt = INTVAL (operands[2]) & 0x3f;
-
-  if (shift_amt < 32)
-    {
-      operands[2] = GEN_INT (32 - shift_amt);
-      return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
-    }
-  else
-    {
-      operands[2] = GEN_INT (shift_amt);
-      return \"dsra\\t%0,%1,%2\";
-    }
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2")])
-	
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
-				  (match_operand:DI 2 "small_int" "I"))))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "*
-{
-  int shift_amt = INTVAL (operands[2]) & 0x3f;
-
-  if (shift_amt < 32)
-    {
-      operands[2] = GEN_INT (32 - shift_amt);
-      return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
-    }
-  else if (shift_amt == 32)
-    return \"dsra\\t%0,%1,32\";
-  else
-    {
-      operands[2] = GEN_INT (shift_amt);
-      return \"dsrl\\t%0,%1,%2\";
-    }
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(truncate:SI (ashift:DI (match_operand:DI 1 "se_register_operand" "d")
-				(match_operand:DI 2 "small_int" "I"))))]
-  "TARGET_64BIT"
-  "*
-{
-  int shift_amt = INTVAL (operands[2]) & 0x3f;
-
-  if (shift_amt < 32)
-    {
-      operands[2] = GEN_INT (32 + shift_amt);
-      if (TARGET_MIPS16)
-	return \"dsll\\t%0,%1,%2\;dsra\\t%0,32\";
-      return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
-    }
-  else
-    return \"move\\t%0,%.\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2")])
-
-;; Combiner patterns to optimize truncate/zero_extend combinations.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(zero_extend:SI (truncate:HI
-			 (match_operand:DI 1 "se_register_operand" "d"))))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "andi\\t%0,%1,0xffff"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(zero_extend:SI (truncate:QI
-			 (match_operand:DI 1 "se_register_operand" "d"))))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "andi\\t%0,%1,0xff"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=d")
-	(zero_extend:HI (truncate:QI
-			 (match_operand:DI 1 "se_register_operand" "d"))))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "andi\\t%0,%1,0xff"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"HI")
-   (set_attr "length"	"1")])
-
-;;  ....................
-;;	ZERO EXTENSION
-;;  ....................
-
-;; Extension insns.
-;; Those for integer source operand are ordered widest source type first.
-
-(define_expand "zero_extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
-  "TARGET_64BIT"
-  "
-{
-  if (optimize && GET_CODE (operands[1]) == MEM)
-    operands[1] = force_not_mem (operands[1]);
-
-  if (GET_CODE (operands[1]) != MEM)
-    {
-      rtx op1   = gen_lowpart (DImode, operands[1]);
-      rtx temp  = gen_reg_rtx (DImode);
-      rtx shift = GEN_INT (32);
-
-      emit_insn (gen_ashldi3 (temp, op1, shift));
-      emit_insn (gen_lshrdi3 (operands[0], temp, shift));
-      DONE;
-    }
-}")
-
-(define_insn "zero_extendsidi2_internal"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(zero_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))]
-  "TARGET_64BIT"
-  "* return mips_move_1word (operands, insn, TRUE);"
-  [(set_attr "type"	"load")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1,2")])
-
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
-    {
-      rtx op = gen_lowpart (SImode, operands[1]);
-      rtx temp = force_reg (SImode, GEN_INT (0xffff));
-
-      emit_insn (gen_andsi3 (operands[0], op, temp));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
-  "!TARGET_MIPS16"
-  "*
-{
-  if (which_alternative == 0)
-    return \"andi\\t%0,%1,0xffff\";
-  else
-    return mips_move_1word (operands, insn, TRUE);
-}"
-  [(set_attr "type"	"arith,load,load")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1,1,2")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(zero_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
-  "TARGET_MIPS16"
-  "* return mips_move_1word (operands, insn, TRUE);"
-  [(set_attr "type"	"load,load")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1,2")])
-
-(define_expand "zero_extendhidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
-  "TARGET_64BIT"
-  "
-{
-  if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
-    {
-      rtx op = gen_lowpart (DImode, operands[1]);
-      rtx temp = force_reg (DImode, GEN_INT (0xffff));
-
-      emit_insn (gen_anddi3 (operands[0], op, temp));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "*
-{
-  if (which_alternative == 0)
-    return \"andi\\t%0,%1,0xffff\";
-  else
-    return mips_move_1word (operands, insn, TRUE);
-}"
-  [(set_attr "type"	"arith,load,load")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1,1,2")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(zero_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
-  "TARGET_64BIT && TARGET_MIPS16"
-  "* return mips_move_1word (operands, insn, TRUE);"
-  [(set_attr "type"	"load,load")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1,2")])
-
-(define_expand "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
-    {
-      rtx op0 = gen_lowpart (SImode, operands[0]);
-      rtx op1 = gen_lowpart (SImode, operands[1]);
-      rtx temp = force_reg (SImode, GEN_INT (0xff));
-
-      emit_insn (gen_andsi3 (op0, op1, temp));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=d,d,d")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
-  "!TARGET_MIPS16"
-  "*
-{
-  if (which_alternative == 0)
-    return \"andi\\t%0,%1,0x00ff\";
-  else
-    return mips_move_1word (operands, insn, TRUE);
-}"
-  [(set_attr "type"	"arith,load,load")
-   (set_attr "mode"	"HI")
-   (set_attr "length"	"1,1,2")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=d,d")
-	(zero_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
-  "TARGET_MIPS16"
-  "* return mips_move_1word (operands, insn, TRUE);"
-  [(set_attr "type"	"load,load")
-   (set_attr "mode"	"HI")
-   (set_attr "length"	"1,2")])
-
-(define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
-    {
-      rtx op = gen_lowpart (SImode, operands[1]);
-      rtx temp = force_reg (SImode, GEN_INT (0xff));
-
-      emit_insn (gen_andsi3 (operands[0], op, temp));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
-  "!TARGET_MIPS16"
-  "*
-{
-  if (which_alternative == 0)
-    return \"andi\\t%0,%1,0x00ff\";
-  else
-    return mips_move_1word (operands, insn, TRUE);
-}"
-  [(set_attr "type"	"arith,load,load")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1,1,2")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(zero_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
-  "TARGET_MIPS16"
-  "* return mips_move_1word (operands, insn, TRUE);"
-  [(set_attr "type"	"load,load")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1,2")])
-
-(define_expand "zero_extendqidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  "TARGET_64BIT"
-  "
-{
-  if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
-    {
-      rtx op = gen_lowpart (DImode, operands[1]);
-      rtx temp = force_reg (DImode, GEN_INT (0xff));
-
-      emit_insn (gen_anddi3 (operands[0], op, temp));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "*
-{
-  if (which_alternative == 0)
-    return \"andi\\t%0,%1,0x00ff\";
-  else
-    return mips_move_1word (operands, insn, TRUE);
-}"
-  [(set_attr "type"	"arith,load,load")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1,1,2")])
-
-;; These can be created when a paradoxical subreg operand with an implicit
-;; sign_extend operator is reloaded.  Because of the subreg, this is really
-;; a zero extend.
-;; ??? It might be possible to eliminate the need for these patterns by adding
-;; more support to reload for implicit sign_extend operators.
-(define_insn "*paradoxical_extendhidi2"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(sign_extend:DI
-	 (subreg:SI (match_operand:HI 1 "memory_operand" "R,m") 0)))]
-  "TARGET_64BIT"
-  "*
-{
-  return mips_move_1word (operands, insn, TRUE);
-}"
-  [(set_attr "type"	"load,load")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1,2")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(zero_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
-  "TARGET_64BIT && TARGET_MIPS16"
-  "* return mips_move_1word (operands, insn, TRUE);"
-  [(set_attr "type"	"load,load")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1,2")])
-
-;;  ....................
-;;	SIGN EXTENSION
-;;  ....................
-
-;; Extension insns.
-;; Those for integer source operand are ordered widest source type first.
-
-;; In 64 bit mode, 32 bit values in general registers are always
-;; correctly sign extended.  That means that if the target is a
-;; general register, we can sign extend from SImode to DImode just by
-;; doing a move.
-
-;; CYGNUS LOCAL law
-(define_insn "extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=d,y,d,*d,d,d")
-	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,d,y,*x*w,R,m")))]
-  "TARGET_64BIT"
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"move,move,move,hilo,load,load")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1,1,1,1,1,2")])
-
-;; These patterns originally accepted general_operands, however, slightly
-;; better code is generated by only accepting register_operands, and then
-;; letting combine generate the lh and lb insns.
-
-(define_expand "extendhidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
-  "TARGET_64BIT"
-  "
-{
-  if (optimize && GET_CODE (operands[1]) == MEM)
-    operands[1] = force_not_mem (operands[1]);
-
-  if (GET_CODE (operands[1]) != MEM)
-    {
-      rtx op1   = gen_lowpart (DImode, operands[1]);
-      rtx temp  = gen_reg_rtx (DImode);
-      rtx shift = GEN_INT (48);
-
-      emit_insn (gen_ashldi3 (temp, op1, shift));
-      emit_insn (gen_ashrdi3 (operands[0], temp, shift));
-      DONE;
-    }
-}")
-
-(define_insn "extendhidi2_internal"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(sign_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
-  "TARGET_64BIT"
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"load")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1,2")])
-
-(define_expand "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (optimize && GET_CODE (operands[1]) == MEM)
-    operands[1] = force_not_mem (operands[1]);
-
-  if (GET_CODE (operands[1]) != MEM)
-    {
-      rtx op1   = gen_lowpart (SImode, operands[1]);
-      rtx temp  = gen_reg_rtx (SImode);
-      rtx shift = GEN_INT (16);
-
-      emit_insn (gen_ashlsi3 (temp, op1, shift));
-      emit_insn (gen_ashrsi3 (operands[0], temp, shift));
-      DONE;
-    }
-}")
-
-(define_insn "extendhisi2_internal"
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
-  ""
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"load")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1,2")])
-
-(define_expand "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (optimize && GET_CODE (operands[1]) == MEM)
-    operands[1] = force_not_mem (operands[1]);
-
-  if (GET_CODE (operands[1]) != MEM)
-    {
-      rtx op0   = gen_lowpart (SImode, operands[0]);
-      rtx op1   = gen_lowpart (SImode, operands[1]);
-      rtx temp  = gen_reg_rtx (SImode);
-      rtx shift = GEN_INT (24);
-
-      emit_insn (gen_ashlsi3 (temp, op1, shift));
-      emit_insn (gen_ashrsi3 (op0, temp, shift));
-      DONE;
-    }
-}")
-
-(define_insn "extendqihi2_internal"
-  [(set (match_operand:HI 0 "register_operand" "=d,d")
-	(sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
-  ""
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"load")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1,2")])
-
-
-(define_expand "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  ""
-  "
-{
-  if (optimize && GET_CODE (operands[1]) == MEM)
-    operands[1] = force_not_mem (operands[1]);
-
-  if (GET_CODE (operands[1]) != MEM)
-    {
-      rtx op1   = gen_lowpart (SImode, operands[1]);
-      rtx temp  = gen_reg_rtx (SImode);
-      rtx shift = GEN_INT (24);
-
-      emit_insn (gen_ashlsi3 (temp, op1, shift));
-      emit_insn (gen_ashrsi3 (operands[0], temp, shift));
-      DONE;
-    }
-}")
-
-(define_insn "extendqisi2_insn"
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
-  ""
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"load")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1,2")])
-
-(define_expand "extendqidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  "TARGET_64BIT"
-  "
-{
-  if (optimize && GET_CODE (operands[1]) == MEM)
-    operands[1] = force_not_mem (operands[1]);
-
-  if (GET_CODE (operands[1]) != MEM)
-    {
-      rtx op1   = gen_lowpart (DImode, operands[1]);
-      rtx temp  = gen_reg_rtx (DImode);
-      rtx shift = GEN_INT (56);
-
-      emit_insn (gen_ashldi3 (temp, op1, shift));
-      emit_insn (gen_ashrdi3 (operands[0], temp, shift));
-      DONE;
-    }
-}")
-
-(define_insn "extendqidi2_insn"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(sign_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
-  "TARGET_64BIT"
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"load")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1,2")])
-
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "cvt.d.s\\t%0,%1"
-  [(set_attr "type"	"fcvt")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-
-
-;;  ....................
-;;	CONVERSIONS
-;;  ....................
-
-;; The SImode scratch register can not be shared with address regs used for
-;; operand zero, because then the address in the move instruction will be
-;; clobbered.  We mark the scratch register as early clobbered to prevent this.
-
-;; We need the ?X in alternative 1 so that it will be choosen only if the
-;; destination is a floating point register.  Otherwise, alternative 1 can
-;; have lower cost than alternative 0 (because there is one less loser), and
-;; can be choosen when it won't work (because integral reloads into FP
-;; registers are not supported).
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=d,*f,R,To")
-	(fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
-   (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
-   (clobber (match_scratch:DF 3 "=f,?*X,f,f"))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "*
-{
-  rtx xoperands[10];
-
-  if (which_alternative == 1)
-    return \"trunc.w.d %0,%1,%2\";
-
-  output_asm_insn (\"trunc.w.d %3,%1,%2\", operands);
-
-  xoperands[0] = operands[0];
-  xoperands[1] = operands[3];
-  output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
-  return \"\";
-}"
-  [(set_attr "type"	"fcvt")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"11,9,10,11")])
-
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=d,*f,R,To")
-	(fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
-   (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
-   (clobber (match_scratch:SF 3 "=f,?*X,f,f"))]
-  "TARGET_HARD_FLOAT && !0" ;;  CYGNUS LOCAL law
-  "*
-{
-  rtx xoperands[10];
-
-  if (which_alternative == 1)
-    return \"trunc.w.s %0,%1,%2\";
-
-  output_asm_insn (\"trunc.w.s %3,%1,%2\", operands);
-
-  xoperands[0] = operands[0];
-  xoperands[1] = operands[3];
-  output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
-  return \"\";
-}"
-  [(set_attr "type"	"fcvt")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"11,9,10,11")])
-
-
-;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
-;;; but not in the chapter that describes the FPU.  It is not mentioned at all
-;;; in the 1991 manuals.  The r4000 at Cygnus does not have this instruction.
-
-;;; Deleting this means that we now need two libgcc2.a libraries.  One for
-;;; the 32 bit calling convention and one for the 64 bit calling convention.
-
-;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also.
-
-(define_insn "fix_truncdfdi2"
-  [(set (match_operand:DI 0 "general_operand" "=d,*f,R,To")
-	(fix:DI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
-   (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
-  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
-  "*
-{
-  rtx xoperands[10];
-
-  if (which_alternative == 1)
-    return \"trunc.l.d %0,%1\";
-
-  output_asm_insn (\"trunc.l.d %2,%1\", operands);
-
-  xoperands[0] = operands[0];
-  xoperands[1] = operands[2];
-  output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands);
-  return \"\";
-}"
-  [(set_attr "type"	"fcvt")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"2,1,2,3")])
-
-
-;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
-;;; but not in the chapter that describes the FPU.  It is not mentioned at all
-;;; in the 1991 manuals.  The r4000 at Cygnus does not have this instruction.
-(define_insn "fix_truncsfdi2"
-  [(set (match_operand:DI 0 "general_operand" "=d,*f,R,To")
-	(fix:DI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
-   (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
-  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
-  "*
-{
-  rtx xoperands[10];
-
-  if (which_alternative == 1)
-    return \"trunc.l.s %0,%1\";
-
-  output_asm_insn (\"trunc.l.s %2,%1\", operands);
-
-  xoperands[0] = operands[0];
-  xoperands[1] = operands[2];
-  output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands);
-  return \"\";
-}"
-  [(set_attr "type"	"fcvt")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"2,1,2,3")])
-
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
-	(float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "*
-{
-  dslots_load_total++;
-  if (GET_CODE (operands[1]) == MEM)
-    return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\";
-
-  return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\";
-}"
-  [(set_attr "type"	"fcvt")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"3,4,3")])
-
-
-(define_insn "floatdidf2"
-  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
-	(float:DF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
-  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
-  "*
-{
-  dslots_load_total++;
-  if (GET_CODE (operands[1]) == MEM)
-    return \"l.d\\t%0,%1%#\;cvt.d.l\\t%0,%0\";
-
-  return \"dmtc1\\t%1,%0%#\;cvt.d.l\\t%0,%0\";
-}"
-  [(set_attr "type"	"fcvt")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"3,4,3")])
-
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "register_operand" "=f,f,f")
-	(float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  dslots_load_total++;
-  if (GET_CODE (operands[1]) == MEM)
-    return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\";
-
-  return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\";
-}"
-  [(set_attr "type"	"fcvt")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"3,4,3")])
-
-
-(define_insn "floatdisf2"
-  [(set (match_operand:SF 0 "register_operand" "=f,f,f")
-	(float:SF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
-  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
-  "*
-{
-  dslots_load_total++;
-  if (GET_CODE (operands[1]) == MEM)
-    return \"l.d\\t%0,%1%#\;cvt.s.l\\t%0,%0\";
-
-  return \"dmtc1\\t%1,%0%#\;cvt.s.l\\t%0,%0\";
-}"
-  [(set_attr "type"	"fcvt")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"3,4,3")])
-
-
-(define_expand "fixuns_truncdfsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "
-{
-  rtx reg1 = gen_reg_rtx (DFmode);
-  rtx reg2 = gen_reg_rtx (DFmode);
-  rtx reg3 = gen_reg_rtx (SImode);
-  rtx label1 = gen_label_rtx ();
-  rtx label2 = gen_label_rtx ();
-  REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
-
-  if (reg1)			/* turn off complaints about unreached code */
-    {
-      emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
-      do_pending_stack_adjust ();
-
-      emit_insn (gen_cmpdf (operands[1], reg1));
-      emit_jump_insn (gen_bge (label1));
-
-      emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
-      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
-			       gen_rtx (LABEL_REF, VOIDmode, label2)));
-      emit_barrier ();
-
-      emit_label (label1);
-      emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
-      emit_move_insn (reg3, GEN_INT (0x80000000));
-
-      emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
-      emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
-
-      emit_label (label2);
-
-      /* allow REG_NOTES to be set on last insn (labels don't have enough
-	 fields, and can't be used for REG_NOTES anyway).  */
-      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
-      DONE;
-    }
-}")
-
-
-(define_expand "fixuns_truncdfdi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
-  "
-{
-  rtx reg1 = gen_reg_rtx (DFmode);
-  rtx reg2 = gen_reg_rtx (DFmode);
-  rtx reg3 = gen_reg_rtx (DImode);
-  rtx label1 = gen_label_rtx ();
-  rtx label2 = gen_label_rtx ();
-  REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
-
-  if (reg1)			/* turn off complaints about unreached code */
-    {
-      emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
-      do_pending_stack_adjust ();
-
-      emit_insn (gen_cmpdf (operands[1], reg1));
-      emit_jump_insn (gen_bge (label1));
-
-      emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
-      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
-			       gen_rtx (LABEL_REF, VOIDmode, label2)));
-      emit_barrier ();
-
-      emit_label (label1);
-      emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
-      emit_move_insn (reg3, GEN_INT (0x80000000));
-      emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
-
-      emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
-      emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
-
-      emit_label (label2);
-
-      /* allow REG_NOTES to be set on last insn (labels don't have enough
-	 fields, and can't be used for REG_NOTES anyway).  */
-      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
-      DONE;
-    }
-}")
-
-
-(define_expand "fixuns_truncsfsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT && !0" ;;  CYGNUS LOCAL law
-  "
-{
-  rtx reg1 = gen_reg_rtx (SFmode);
-  rtx reg2 = gen_reg_rtx (SFmode);
-  rtx reg3 = gen_reg_rtx (SImode);
-  rtx label1 = gen_label_rtx ();
-  rtx label2 = gen_label_rtx ();
-  REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
-
-  if (reg1)			/* turn off complaints about unreached code */
-    {
-      emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
-      do_pending_stack_adjust ();
-
-      emit_insn (gen_cmpsf (operands[1], reg1));
-      emit_jump_insn (gen_bge (label1));
-
-      emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
-      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
-			       gen_rtx (LABEL_REF, VOIDmode, label2)));
-      emit_barrier ();
-
-      emit_label (label1);
-      emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
-      emit_move_insn (reg3, GEN_INT (0x80000000));
-
-      emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
-      emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
-
-      emit_label (label2);
-
-      /* allow REG_NOTES to be set on last insn (labels don't have enough
-	 fields, and can't be used for REG_NOTES anyway).  */
-      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
-      DONE;
-    }
-}")
-
-
-(define_expand "fixuns_truncsfdi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
-  "
-{
-  rtx reg1 = gen_reg_rtx (SFmode);
-  rtx reg2 = gen_reg_rtx (SFmode);
-  rtx reg3 = gen_reg_rtx (DImode);
-  rtx label1 = gen_label_rtx ();
-  rtx label2 = gen_label_rtx ();
-  REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
-
-  if (reg1)			/* turn off complaints about unreached code */
-    {
-      emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
-      do_pending_stack_adjust ();
-
-      emit_insn (gen_cmpsf (operands[1], reg1));
-      emit_jump_insn (gen_bge (label1));
-
-      emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
-      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
-			       gen_rtx (LABEL_REF, VOIDmode, label2)));
-      emit_barrier ();
-
-      emit_label (label1);
-      emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
-      emit_move_insn (reg3, GEN_INT (0x80000000));
-      emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
-
-      emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
-      emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
-
-      emit_label (label2);
-
-      /* allow REG_NOTES to be set on last insn (labels don't have enough
-	 fields, and can't be used for REG_NOTES anyway).  */
-      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
-      DONE;
-    }
-}")
-
-
-;;  ....................
-;;	DATA MOVEMENT
-;;  ....................
-
-;; Bit field extract patterns which use lwl/lwr.
-
-;; ??? There could be HImode variants for the ulh/ulhu/ush macros.
-;; It isn't clear whether this will give better code.
-
-;; Only specify the mode operand 1, the rest are assumed to be word_mode.
-(define_expand "extv"
-  [(set (match_operand 0 "register_operand" "")
-	(sign_extract (match_operand:QI 1 "memory_operand" "")
-		      (match_operand 2 "immediate_operand" "")
-		      (match_operand 3 "immediate_operand" "")))]
-  "!TARGET_MIPS16"
-  "
-{
-  /* If the field does not start on a byte boundary, then fail.  */
-  if (INTVAL (operands[3]) % 8 != 0) 
-    FAIL;
-
-  /* MIPS I and MIPS II can only handle a 32bit field.  */
-  if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
-    FAIL;
-
-  /* MIPS III and MIPS IV can handle both 32bit and 64bit fields.  */
-  if (TARGET_64BIT
-      && INTVAL (operands[2]) != 64
-      && INTVAL (operands[2]) != 32)
-    FAIL;
-
-  /* This can happen for a 64 bit target, when extracting a value from
-     a 64 bit union member.  extract_bit_field doesn't verify that our
-     source matches the predicate, so we force it to be a MEM here.  */
-  if (GET_CODE (operands[1]) != MEM)
-    FAIL;
-
-  /* Change the mode to BLKmode for aliasing purposes.  */
-  operands[1] = change_address (operands[1], BLKmode, XEXP (operands[1], 0));
-
-  /* Otherwise, emit a l[wd]l/l[wd]r pair to load the value.  */
-  if (INTVAL (operands[2]) == 64)
-    emit_insn (gen_movdi_uld (operands[0], operands[1]));
-  else
-    {
-      if (TARGET_64BIT)
-	{
-	  operands[0] = gen_lowpart (SImode, operands[0]);
-	  if (operands[0] == NULL_RTX)
-	    FAIL;
-	}
-      emit_insn (gen_movsi_ulw (operands[0], operands[1]));
-    }
-  DONE;
-}")
-
-;; Only specify the mode operand 1, the rest are assumed to be word_mode.
-(define_expand "extzv"
-  [(set (match_operand 0 "register_operand" "")
-	(zero_extract (match_operand:QI 1 "memory_operand" "")
-		      (match_operand 2 "immediate_operand" "")
-		      (match_operand 3 "immediate_operand" "")))]
-  "!TARGET_MIPS16"
-  "
-{
-  /* If the field does not start on a byte boundary, then fail.  */
-  if (INTVAL (operands[3]) % 8 != 0) 
-    FAIL;
-
-  /* MIPS I and MIPS II can only handle a 32bit field.  */
-  if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
-    FAIL;
-
-  /* MIPS III and MIPS IV can handle both 32bit and 64bit fields.  */
-  if (TARGET_64BIT
-      && INTVAL (operands[2]) != 64
-      && INTVAL (operands[2]) != 32)
-    FAIL;
-
-  /* This can happen for a 64 bit target, when extracting a value from
-     a 64 bit union member.  extract_bit_field doesn't verify that our
-     source matches the predicate, so we force it to be a MEM here.  */
-  if (GET_CODE (operands[1]) != MEM)
-    FAIL;
-
-  /* Change the mode to BLKmode for aliasing purposes.  */
-  operands[1] = change_address (operands[1], BLKmode, XEXP (operands[1], 0));
-
-  /* Otherwise, emit a lwl/lwr pair to load the value.  */
-  if (INTVAL (operands[2]) == 64)
-    emit_insn (gen_movdi_uld (operands[0], operands[1]));
-  else
-    {
-      if (TARGET_64BIT)
-	{
-	  operands[0] = gen_lowpart (SImode, operands[0]);
-	  if (operands[0] == NULL_RTX)
-	    FAIL;
-	}
-      emit_insn (gen_movsi_ulw (operands[0], operands[1]));
-    }
-  DONE;
-}")
-
-;; Only specify the mode operands 0, the rest are assumed to be word_mode.
-(define_expand "insv"
-  [(set (zero_extract (match_operand:QI 0 "memory_operand" "")
-		      (match_operand 1 "immediate_operand" "")
-		      (match_operand 2 "immediate_operand" ""))
-	(match_operand 3 "register_operand" ""))]
-  "!TARGET_MIPS16"
-  "
-{
-  /* If the field does not start on a byte boundary, then fail.  */
-  if (INTVAL (operands[2]) % 8 != 0) 
-    FAIL;
-
-  /* MIPS I and MIPS II can only handle a 32bit field.  */
-  if (!TARGET_64BIT && INTVAL (operands[1]) != 32)
-    FAIL;
-
-  /* MIPS III and MIPS IV can handle both 32bit and 64bit fields.  */
-  if (TARGET_64BIT
-      && INTVAL (operands[1]) != 64
-      && INTVAL (operands[1]) != 32)
-    FAIL;
-
-  /* This can happen for a 64 bit target, when storing into a 32 bit union
-     member.  store_bit_field doesn't verify that our target matches the
-     predicate, so we force it to be a MEM here.  */
-  if (GET_CODE (operands[0]) != MEM)
-    FAIL;
-
-  /* Change the mode to BLKmode for aliasing purposes.  */
-  operands[0] = change_address (operands[0], BLKmode, XEXP (operands[0], 0));
-
-  /* Otherwise, emit a s[wd]l/s[wd]r pair to load the value.  */
-  if (INTVAL (operands[1]) == 64)
-    emit_insn (gen_movdi_usd (operands[0], operands[3]));
-  else
-    {
-      if (TARGET_64BIT)
-	{
-	  operands[3] = gen_lowpart (SImode, operands[3]);
-	  if (operands[3] == NULL_RTX)
-	    FAIL;
-	}
-      emit_insn (gen_movsi_usw (operands[0], operands[3]));
-    }
-  DONE;
-}")
-
-;; unaligned word moves generated by the bit field patterns
-
-(define_insn "movsi_ulw"
-  [(set (match_operand:SI 0 "register_operand" "=&d,&d")
-	(unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")] 0))]
-  "!TARGET_MIPS16"
-  "*
-{
-  rtx offset = const0_rtx;
-  rtx addr = XEXP (operands[1], 0);
-  rtx mem_addr = eliminate_constant_term (addr, &offset);
-  char *ret;
-
-  if (TARGET_STATS)
-    mips_count_memory_refs (operands[1], 2);
-
-  /* The stack/frame pointers are always aligned, so we can convert
-     to the faster lw if we are referencing an aligned stack location.  */
-
-  if ((INTVAL (offset) & 3) == 0
-      && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
-    ret = \"lw\\t%0,%1\";
-  else
-    ret = \"ulw\\t%0,%1\";
-
-  return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
-}"
-  [(set_attr "type"	"load,load")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2,4")])
-
-(define_insn "movsi_usw"
-  [(set (match_operand:BLK 0 "memory_operand" "=R,o")
-	(unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
-  "!TARGET_MIPS16"
-  "*
-{
-  rtx offset = const0_rtx;
-  rtx addr = XEXP (operands[0], 0);
-  rtx mem_addr = eliminate_constant_term (addr, &offset);
-
-  if (TARGET_STATS)
-    mips_count_memory_refs (operands[0], 2);
-
-  /* The stack/frame pointers are always aligned, so we can convert
-     to the faster sw if we are referencing an aligned stack location.  */
-
-  if ((INTVAL (offset) & 3) == 0
-      && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
-    return \"sw\\t%1,%0\";
-
-  return \"usw\\t%z1,%0\";
-}"
-  [(set_attr "type"	"store")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2,4")])
-
-;; Bit field extract patterns which use ldl/ldr.
-
-;; unaligned double word moves generated by the bit field patterns
-
-(define_insn "movdi_uld"
-  [(set (match_operand:DI 0 "register_operand" "=&d,&d")
-	(unspec:DI [(match_operand:BLK 1 "general_operand" "R,o")] 0))]
-  ""
-  "*
-{
-  rtx offset = const0_rtx;
-  rtx addr = XEXP (operands[1], 0);
-  rtx mem_addr = eliminate_constant_term (addr, &offset);
-  char *ret;
-
-  if (TARGET_STATS)
-    mips_count_memory_refs (operands[1], 2);
-
-  /* The stack/frame pointers are always aligned, so we can convert
-     to the faster lw if we are referencing an aligned stack location.  */
-
-  if ((INTVAL (offset) & 7) == 0
-      && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
-    ret = \"ld\\t%0,%1\";
-  else
-    ret = \"uld\\t%0,%1\";
-
-  return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
-}"
-  [(set_attr "type"	"load,load")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2,4")])
-
-(define_insn "movdi_usd"
-  [(set (match_operand:BLK 0 "memory_operand" "=R,o")
-	(unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
-  ""
-  "*
-{
-  rtx offset = const0_rtx;
-  rtx addr = XEXP (operands[0], 0);
-  rtx mem_addr = eliminate_constant_term (addr, &offset);
-
-  if (TARGET_STATS)
-    mips_count_memory_refs (operands[0], 2);
-
-  /* The stack/frame pointers are always aligned, so we can convert
-     to the faster sw if we are referencing an aligned stack location.  */
-
-  if ((INTVAL (offset) & 7) == 0
-      && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
-    return \"sd\\t%1,%0\";
-
-  return \"usd\\t%z1,%0\";
-}"
-  [(set_attr "type"	"store")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2,4")])
-
-;; These two patterns support loading addresses with two instructions instead
-;; of using the macro instruction la.
-
-;; ??? mips_move_1word has support for HIGH, so this pattern may be
-;; unnecessary.
-
-(define_insn "high"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(high:SI (match_operand:SI 1 "immediate_operand" "")))]
-  "mips_split_addresses && !TARGET_MIPS16"
-  "lui\\t%0,%%hi(%1) # high"
-  [(set_attr "type"	"move")
-   (set_attr "length"	"1")])
-
-(define_insn "low"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-		   (match_operand:SI 2 "immediate_operand" "")))]
-  "mips_split_addresses && !TARGET_MIPS16"
-  "addiu\\t%0,%1,%%lo(%2) # low"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-
-;; 64-bit integer moves
-
-;; Unlike most other insns, the move insns can't be split with
-;; different predicates, because register spilling and other parts of
-;; the compiler, have memoized the insn number already.
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (mips_split_addresses && mips_check_split (operands[1], DImode))
-    {
-      enum machine_mode mode = GET_MODE (operands[0]);
-      rtx tem = ((reload_in_progress | reload_completed)
-		 ? operands[0] : gen_reg_rtx (mode));
-
-      emit_insn (gen_rtx (SET, VOIDmode, tem,
-			  gen_rtx (HIGH, mode, operands[1])));
-
-      operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]);
-    }
-
-  /* If we are generating embedded PIC code, and we are referring to a
-     symbol in the .text section, we must use an offset from the start
-     of the function.  */
-  if (TARGET_EMBEDDED_PIC
-      && (GET_CODE (operands[1]) == LABEL_REF
-	  || (GET_CODE (operands[1]) == SYMBOL_REF
-	      && ! SYMBOL_REF_FLAG (operands[1]))))
-    {
-      rtx temp;
-
-      temp = embedded_pic_offset (operands[1]);
-      temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx,
-		      force_reg (DImode, temp));
-      emit_move_insn (operands[0], force_reg (DImode, temp));
-      DONE;
-    }
-
-  /* If operands[1] is a constant address illegal for pic, then we need to
-     handle it just like LEGITIMIZE_ADDRESS does.  */
-  if (flag_pic && pic_address_needs_scratch (operands[1]))
-    {
-      rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
-      rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
-
-      if (! SMALL_INT (temp2))
-	temp2 = force_reg (DImode, temp2);
-
-      emit_move_insn (operands[0], gen_rtx (PLUS, DImode, temp, temp2));
-      DONE;
-    }
-
-  /* On the mips16, we can handle a GP relative reference by adding in
-     $gp.  We need to check the name to see whether this is a string
-     constant.  */
-  if (TARGET_MIPS16
-      && register_operand (operands[0], DImode)
-      && GET_CODE (operands[1]) == SYMBOL_REF
-      && SYMBOL_REF_FLAG (operands[1]))
-    {
-      char *name = XSTR (operands[1], 0);
-
-      if (name[0] != '*'
-	  || strncmp (name + 1, LOCAL_LABEL_PREFIX,
-		      sizeof LOCAL_LABEL_PREFIX - 1) != 0)
-	{
-	  rtx base_reg;
-
-	  if (reload_in_progress || reload_completed)
-	    {
-	      /* In movsi we use the constant table here.  However, in
-                 this case, we're better off copying $28 into a
-                 register and adding, because the constant table entry
-                 would be 8 bytes.  */
-	      base_reg = operands[0];
-	      emit_move_insn (base_reg,
-			      gen_rtx (CONST, DImode,
-				       gen_rtx (REG, DImode,
-						GP_REG_FIRST + 28)));
-	    }
-	  else
-	    {
-	      base_reg = gen_reg_rtx (Pmode);
-	      emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
-	    }
-
-	  emit_move_insn (operands[0],
-			  gen_rtx (PLUS, Pmode, base_reg,
-				   mips16_gp_offset (operands[1])));
-	  DONE;
-	}
-    }
-
-  if ((reload_in_progress | reload_completed) == 0
-      && !register_operand (operands[0], DImode)
-      && !register_operand (operands[1], DImode)
-      && (TARGET_MIPS16
-	  || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
-	       && operands[1] != CONST0_RTX (DImode))))
-    {
-      rtx temp = force_reg (DImode, operands[1]);
-      emit_move_insn (operands[0], temp);
-      DONE;
-    }
-}")
-
-;; For mips16, we need a special case to handle storing $31 into
-;; memory, since we don't have a constraint to match $31.  This
-;; instruction can be generated by save_restore_insns.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "memory_operand" "R,m")
-	(reg:DI 31))]
-  "TARGET_MIPS16 && TARGET_64BIT"
-  "*
-{
-  operands[1] = gen_rtx (REG, DImode, 31);
-  return mips_move_2words (operands, insn);
-}"
-  [(set_attr "type"	"store")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1,2")])
-
-;; CYGNUS LOCAL law
-(define_insn "movdi_internal"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x*w,*d,*x*w")
-	(match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,J,*x,*d"))]
-  "!TARGET_64BIT && !TARGET_MIPS16
-   && (register_operand (operands[0], DImode)
-       || register_operand (operands[1], DImode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
-       || operands[1] == CONST0_RTX (DImode))"
-  "* return mips_move_2words (operands, insn); "
-  [(set_attr "type"	"move,arith,load,load,store,store,hilo,hilo,hilo")
-   (set_attr "mode"	"DI")
-   (set_attr "length"   "2,4,2,4,2,4,2,2,2")])
-
-;; CYGNUS LOCAL law
-(define_insn ""
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,To,*d")
-	(match_operand:DI 1 "general_operand" "d,d,y,K,N,R,To,d,d,*x*w"))]
-  "!TARGET_64BIT && TARGET_MIPS16
-   && (register_operand (operands[0], DImode)
-       || register_operand (operands[1], DImode))"
-  "* return mips_move_2words (operands, insn);"
-  [(set_attr "type"	"move,move,move,arith,arith,load,load,store,store,hilo")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"2,2,2,2,3,2,4,2,4,2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_operand:DI 1 "register_operand" ""))]
-  "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
-
-  [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
-   (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
-  "")
-
-;; CYGNUS LOCAL law
-(define_insn "movdi_internal2"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*x*w,*d,*x*w,*a*q")
-	(match_operand:DI 1 "movdi_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,J,*x*w,*d,*J"))]
-  "TARGET_64BIT && !TARGET_MIPS16
-   && (register_operand (operands[0], DImode)
-       || se_register_operand (operands[1], DImode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
-       || operands[1] == CONST0_RTX (DImode))"
-  "* return mips_move_2words (operands, insn); "
-  [(set_attr "type"	"move,load,arith,arith,load,load,store,store,hilo,hilo,hilo,hilo")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1,2,1,2,1,2,1,2,1,1,1,2")])
-
-;; CYGNUS LOCAL law
-(define_insn ""
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,R,m,*d")
-	(match_operand:DI 1 "movdi_operand" "d,d,y,K,N,s,R,m,d,d,*x*w"))]
-  "TARGET_64BIT && TARGET_MIPS16
-   && (register_operand (operands[0], DImode)
-       || se_register_operand (operands[1], DImode))"
-  "* return mips_move_2words (operands, insn);"
-  [(set_attr "type"	"move,move,move,arith,arith,arith,load,load,store,store,hilo")
-   (set_attr "mode"	"DI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (const_int 1)
-		 (const_int 1)
-		 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
-			       (const_int 2)
-			       (const_int 3))
-		 (if_then_else (match_operand:VOID 1 "m16_usym5_4" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (const_int 1)
-		 (const_int 2)
-		 (const_int 1)
-		 (const_int 2)
-		 (const_int 1)])])
-
-;; On the mips16, we can split ld $r,N($r) into an add and a load,
-;; when the original load is a 4 byte instruction but the add and the
-;; load are 2 2 byte instructions.
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(mem:DI (plus:DI (match_dup 0)
-			 (match_operand:DI 1 "const_int_operand" ""))))]
-  "TARGET_64BIT && TARGET_MIPS16 && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && ((INTVAL (operands[1]) < 0
-	&& INTVAL (operands[1]) >= -0x10)
-       || (INTVAL (operands[1]) >= 32 * 8
-	   && INTVAL (operands[1]) <= 31 * 8 + 0x8)
-       || (INTVAL (operands[1]) >= 0
-	   && INTVAL (operands[1]) < 32 * 8
-	   && (INTVAL (operands[1]) & 7) != 0))"
-  [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
-   (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-  if (val < 0)
-    operands[2] = GEN_INT (0);
-  else if (val >= 32 * 8)
-    {
-      int off = val & 7;
-
-      operands[1] = GEN_INT (0x8 + off);
-      operands[2] = GEN_INT (val - off - 0x8);
-    }
-  else
-    {
-      int off = val & 7;
-
-      operands[1] = GEN_INT (off);
-      operands[2] = GEN_INT (val - off);
-    }
-}")
-
-;; Handle input reloads in DImode.
-;; This is mainly to handle reloading HILO_REGNUM.  Note that we may
-;; see it as the source or the destination, depending upon which way
-;; reload handles the instruction.
-;; Making the second operand TImode is a trick.  The compiler may
-;; reuse the same register for operand 0 and operand 2.  Using TImode
-;; gives us two registers, so we can always use the one which is not
-;; used.
-
-(define_expand "reload_indi"
-  [(set (match_operand:DI 0 "register_operand" "=b")
-	(match_operand:DI 1 "" "b"))
-   (clobber (match_operand:TI 2 "register_operand" "=&d"))]
-  "TARGET_64BIT"
-  "
-{
-  rtx scratch = gen_rtx (REG, DImode,
-			 (REGNO (operands[0]) == REGNO (operands[2]) 
-			  ? REGNO (operands[2]) + 1
-			  : REGNO (operands[2])));
-
-  if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
-    {
-      if (GET_CODE (operands[1]) == MEM)
-	{
-	  rtx memword, offword, hiword, loword;
-	  rtx addr = find_replacement (&XEXP (operands[1], 0));
-	  rtx op1 = change_address (operands[1], VOIDmode, addr);
-
-	  scratch = gen_rtx (REG, SImode, REGNO (scratch));
-	  memword = change_address (op1, SImode, NULL_RTX);
-	  offword = change_address (adj_offsettable_operand (op1, 4),
-				    SImode, NULL_RTX);
-	  if (BYTES_BIG_ENDIAN)
-	    {
-	      hiword = memword;
-	      loword = offword;
-	    }
-	  else
-	    {
-	      hiword = offword;
-	      loword = memword;
-	    }
-	  emit_move_insn (scratch, hiword);
-	  emit_move_insn (gen_rtx (REG, SImode, 64), scratch);
-	  emit_move_insn (scratch, loword);
-	  emit_move_insn (gen_rtx (REG, SImode, 65), scratch);
-          emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
-	}
-      else
-	{
-	  emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
-	  emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch));
-	  emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
-	  emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
-	  emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
-          emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
-	}
-      DONE;
-    }
-  if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
-    {
-      emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
-      emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
-      emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
-      emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
-      emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
-      emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
-      emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
-      DONE;
-    }
-  /* This handles moves between a float register and HI/LO.  */
-  emit_move_insn (scratch, operands[1]);
-  emit_move_insn (operands[0], scratch);
-  DONE;
-}")
-
-;; Handle output reloads in DImode.
-
-;; Reloading HILO_REG in MIPS16 mode requires two scratch registers, so we
-;; use a TImode scratch reg.
-
-(define_expand "reload_outdi"
-  [(set (match_operand:DI 0 "" "=b")
-	(match_operand:DI 1 "se_register_operand" "b"))
-   (clobber (match_operand:TI 2 "register_operand" "=&d"))]
-  "TARGET_64BIT"
-  "
-{
-  rtx scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
-
-  if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
-    {
-      emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
-      emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch));
-      emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
-      emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
-      emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
-      emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
-      DONE;
-    }
-  if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
-    {
-      if (GET_CODE (operands[0]) == MEM)
-	{
-	  rtx scratch, memword, offword, hiword, loword;
-	  rtx addr = find_replacement (&XEXP (operands[0], 0));
-	  rtx op0 = change_address (operands[0], VOIDmode, addr);
-
-	  scratch = gen_rtx (REG, SImode, REGNO (operands[2]));
-	  memword = change_address (op0, SImode, NULL_RTX);
-	  offword = change_address (adj_offsettable_operand (op0, 4),
-				    SImode, NULL_RTX);
-	  if (BYTES_BIG_ENDIAN)
-	    {
-	      hiword = memword;
-	      loword = offword;
-	    }
-	  else
-	    {
-	      hiword = offword;
-	      loword = memword;
-	    }
-	  emit_move_insn (scratch, gen_rtx (REG, SImode, 64));
-	  emit_move_insn (hiword, scratch);
-	  emit_move_insn (scratch, gen_rtx (REG, SImode, 65));
-	  emit_move_insn (loword, scratch);
-	  emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
-	}
-      else if (TARGET_MIPS16 && ! M16_REG_P (REGNO (operands[0])))
-	{
-	  /* Handle the case where operand[0] is not a 'd' register,
-	     and hence we can not directly move from the HILO register
-	     into it.  */
-	  rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
-	  emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
-	  emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
-	  emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
-	  emit_insn (gen_movdi (scratch2, gen_rtx (REG, DImode, 64)));
-	  emit_insn (gen_ashldi3 (scratch2, scratch2, GEN_INT (32)));
-	  emit_insn (gen_iordi3 (scratch, scratch, scratch2));
-	  emit_insn (gen_movdi (operands[0], scratch));
-	  emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
-	}
-      else
-	{
-	  emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
-	  emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
-	  emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
-	  emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
-	  emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
-	  emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
-	  emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
-	}
-      DONE;
-    }
-  /* This handles moves between a float register and HI/LO.  */
-  emit_move_insn (scratch, operands[1]);
-  emit_move_insn (operands[0], scratch);
-  DONE;
-}")
-
-;; 32-bit Integer moves
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operand:SI 1 "large_int" ""))]
-  "!TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
-  [(set (match_dup 0)
-	(match_dup 2))
-   (set (match_dup 0)
-     	(ior:SI (match_dup 0)
-		(match_dup 3)))]
-  "
-{
-  operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
-  operands[3] = GEN_INT (INTVAL (operands[1]) & 0x0000ffff);
-}")
-
-;; Unlike most other insns, the move insns can't be split with
-;; different predicates, because register spilling and other parts of
-;; the compiler, have memoized the insn number already.
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (mips_split_addresses && mips_check_split (operands[1], SImode))
-    {
-      enum machine_mode mode = GET_MODE (operands[0]);
-      rtx tem = ((reload_in_progress | reload_completed)
-		 ? operands[0] : gen_reg_rtx (mode));
-
-      emit_insn (gen_rtx (SET, VOIDmode, tem,
-			  gen_rtx (HIGH, mode, operands[1])));
-
-      operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]);
-    }
-
-  /* If we are generating embedded PIC code, and we are referring to a
-     symbol in the .text section, we must use an offset from the start
-     of the function.  */
-  if (TARGET_EMBEDDED_PIC
-      && (GET_CODE (operands[1]) == LABEL_REF
-	  || (GET_CODE (operands[1]) == SYMBOL_REF
-	      && ! SYMBOL_REF_FLAG (operands[1]))))
-    {
-      rtx temp;
-
-      temp = embedded_pic_offset (operands[1]);
-      temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx,
-		      force_reg (SImode, temp));
-      emit_move_insn (operands[0], force_reg (SImode, temp));
-      DONE;
-    }
-
-  /* If operands[1] is a constant address invalid for pic, then we need to
-     handle it just like LEGITIMIZE_ADDRESS does.  */
-  if (flag_pic && pic_address_needs_scratch (operands[1]))
-    {
-      rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0));
-      rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
-
-      if (! SMALL_INT (temp2))
-	temp2 = force_reg (SImode, temp2);
-
-      emit_move_insn (operands[0], gen_rtx (PLUS, SImode, temp, temp2));
-      DONE;
-    }
-
-  /* On the mips16, we can handle a GP relative reference by adding in
-     $gp.  We need to check the name to see whether this is a string
-     constant.  */
-  if (TARGET_MIPS16
-      && register_operand (operands[0], SImode)
-      && GET_CODE (operands[1]) == SYMBOL_REF
-      && SYMBOL_REF_FLAG (operands[1]))
-    {
-      char *name = XSTR (operands[1], 0);
-
-      if (name[0] != '*'
-	  || strncmp (name + 1, LOCAL_LABEL_PREFIX,
-		      sizeof LOCAL_LABEL_PREFIX - 1) != 0)
-	{
-	  rtx base_reg;
-
-	  if (reload_in_progress || reload_completed)
-	    {
-	      /* We need to reload this address.  In this case we
-                 aren't going to have a chance to combine loading the
-                 address with the load or store.  That means that we
-                 can either generate a 2 byte move followed by a 4
-                 byte addition, or a 2 byte load with a 4 byte entry
-                 in the constant table.  Since the entry in the
-                 constant table might be shared, we're better off, on
-                 average, loading the address from the constant table.  */
-	      emit_move_insn (operands[0],
-			      force_const_mem (SImode, operands[1]));
-	      DONE;
-	    }
-
-	  base_reg = gen_reg_rtx (Pmode);
-	  emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
-
-	  emit_move_insn (operands[0],
-			  gen_rtx (PLUS, Pmode, base_reg,
-				   mips16_gp_offset (operands[1])));
-	  DONE;
-	}
-    }
-
-  if ((reload_in_progress | reload_completed) == 0
-      && !register_operand (operands[0], SImode)
-      && !register_operand (operands[1], SImode)
-      && (TARGET_MIPS16
-	  || GET_CODE (operands[1]) != CONST_INT
-	  || INTVAL (operands[1]) != 0))
-    {
-      rtx temp = force_reg (SImode, operands[1]);
-      emit_move_insn (operands[0], temp);
-      DONE;
-    }
-}")
-
-;; For mips16, we need a special case to handle storing $31 into
-;; memory, since we don't have a constraint to match $31.  This
-;; instruction can be generated by save_restore_insns.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "memory_operand" "R,m")
-	(reg:SI 31))]
-  "TARGET_MIPS16"
-  "*
-{
-  operands[1] = gen_rtx (REG, SImode, 31);
-  return mips_move_1word (operands, insn, FALSE);
-}"
-  [(set_attr "type"	"store")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1,2")])
-
-;; The difference between these two is whether or not ints are allowed
-;; in FP registers (off by default, use -mdebugh to enable).
-
-;; CYGNUS LOCAL law
-(define_insn "movsi_internal1"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x*w,*x*w,*d,*d")
-	(match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x*w,*a*q"))]
-  "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
-   && (register_operand (operands[0], SImode)
-       || register_operand (operands[1], SImode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1,2,1,2,1,2,1,2,1,1,1,1,2,1,2,1,1,1,1")])
-
-;; CYGNUS LOCAL law
-(define_insn "movsi_internal2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x*w,*d,*x*w,*d")
-	(match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x*w,*d,*a*q"))]
-  "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
-   && (register_operand (operands[0], SImode)
-       || register_operand (operands[1], SImode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1,2,1,2,1,2,1,2,1,1,1,1,1,1")])
-
-;; This is the mips16 movsi instruction.  We accept a small integer as
-;; the source if the destination is a GP memory reference.  This is
-;; because we want the combine pass to turn adding a GP reference to a
-;; register into a direct GP reference, but the combine pass will pass
-;; in the source as a constant if it finds an equivalent one.  If the
-;; instruction is recognized, reload will force the constant back out
-;; into a register.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,d,R,m,*d,*d")
-	(match_operand:SI 1 "move_operand" "d,d,y,S,K,N,s,R,m,d,d,*x,*a"))]
-  "TARGET_MIPS16
-   && (register_operand (operands[0], SImode)
-       || register_operand (operands[1], SImode)
-       || (GET_CODE (operands[0]) == MEM
-	   && GET_CODE (XEXP (operands[0], 0)) == PLUS
-	   && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST
-	   && mips16_gp_offset_p (XEXP (XEXP (operands[0], 0), 1))
-	   && GET_CODE (operands[1]) == CONST_INT
-	   && (SMALL_INT (operands[1])
-	       || SMALL_INT_UNSIGNED (operands[1]))))"
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"move,move,move,load,arith,arith,arith,load,load,store,store,hilo,hilo")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (const_int 1)
-		 (const_int 1)
-		 (const_int 2)
-		 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
-			       (const_int 2)
-			       (const_int 3))
-		 (if_then_else (match_operand:VOID 1 "m16_usym8_4" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (const_int 1)
-		 (const_int 2)
-		 (const_int 1)
-		 (const_int 2)
-		 (const_int 1)
-		 (const_int 1)])])
-
-;; On the mips16, we can split lw $r,N($r) into an add and a load,
-;; when the original load is a 4 byte instruction but the add and the
-;; load are 2 2 byte instructions.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(mem:SI (plus:SI (match_dup 0)
-			 (match_operand:SI 1 "const_int_operand" ""))))]
-  "TARGET_MIPS16 && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && ((INTVAL (operands[1]) < 0
-	&& INTVAL (operands[1]) >= -0x80)
-       || (INTVAL (operands[1]) >= 32 * 4
-	   && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
-       || (INTVAL (operands[1]) >= 0
-	   && INTVAL (operands[1]) < 32 * 4
-	   && (INTVAL (operands[1]) & 3) != 0))"
-  [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
-   (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-  if (val < 0)
-    operands[2] = GEN_INT (0);
-  else if (val >= 32 * 4)
-    {
-      int off = val & 3;
-
-      operands[1] = GEN_INT (0x7c + off);
-      operands[2] = GEN_INT (val - off - 0x7c);
-    }
-  else
-    {
-      int off = val & 3;
-
-      operands[1] = GEN_INT (off);
-      operands[2] = GEN_INT (val - off);
-    }
-}")
-
-;; On the mips16, we can split a load of certain constants into a load
-;; and an add.  This turns a 4 byte instruction into 2 2 byte
-;; instructions.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operand:SI 1 "const_int_operand" ""))]
-  "TARGET_MIPS16 && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && INTVAL (operands[1]) >= 0x100
-   && INTVAL (operands[1]) <= 0xff + 0x7f"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
-  "
-{
-  int val = INTVAL (operands[1]);
-
-  operands[1] = GEN_INT (0xff);
-  operands[2] = GEN_INT (val - 0xff);
-}")
-
-;; On the mips16, we can split a load of a negative constant into a
-;; load and a neg.  That's what mips_move_1word will generate anyhow.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operand:SI 1 "const_int_operand" ""))]
-  "TARGET_MIPS16 && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && INTVAL (operands[1]) < 0
-   && INTVAL (operands[1]) > - 0x8000"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0) (neg:SI (match_dup 0)))]
-  "
-{
-  operands[1] = GEN_INT (- INTVAL (operands[1]));
-}")
-
-;; Reload HILO_REGNUM in SI mode.  This needs a scratch register in
-;; order to set the sign bit correctly in the HI register.
-
-(define_expand "reload_outsi"
-  [(set (match_operand:SI 0 "general_operand" "=b")
-	(match_operand:SI 1 "register_operand" "b"))
-   (clobber (match_operand:SI 2 "register_operand" "=&d"))]
-  "TARGET_64BIT || TARGET_MIPS16"
-  "
-{
-  if (TARGET_64BIT
-      && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
-    {
-      emit_insn (gen_movsi (gen_rtx (REG, SImode, 65), operands[1]));
-      emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31)));
-      emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2]));
-      emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
-      DONE;
-    }
-  /* Use a mult to reload LO on mips16.  ??? This is hideous.  */
-  if (TARGET_MIPS16
-      && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
-    {
-      emit_insn (gen_movsi (operands[2], GEN_INT (1)));
-      /* This is gen_mulsi3_internal, but we need to fill in the
-	 scratch registers.  */
-      emit_insn (gen_rtx (PARALLEL, VOIDmode,
-			  gen_rtvec (3,
-				     gen_rtx (SET, VOIDmode,
-					      operands[0],
-					      gen_rtx (MULT, SImode,
-						       operands[1],
-						       operands[2])),
-				     gen_rtx (CLOBBER, VOIDmode,
-					      gen_rtx (REG, SImode, 64)),
-				     gen_rtx (CLOBBER, VOIDmode,
-					      gen_rtx (REG, SImode, 66)))));
-      DONE;
-    }
-  /* FIXME: I don't know how to get a value into the HI register.  */
-  if (GET_CODE (operands[0]) == REG
-      && (TARGET_MIPS16 ? M16_REG_P (REGNO (operands[0]))
-	  : GP_REG_P (REGNO (operands[0]))))
-    {
-      emit_move_insn (operands[0], operands[1]);
-      DONE;
-    }
-  /* This handles moves between a float register and HI/LO.  */
-  emit_move_insn (operands[2], operands[1]);
-  emit_move_insn (operands[0], operands[2]);
-  DONE;
-}")
-
-;; Reload a value into HI or LO.  There is no mthi or mtlo on mips16,
-;; so we use a mult.  ??? This is hideous, and we ought to figure out
-;; something better.
-
-;; We use no predicate for operand1, because it may be a PLUS, and there
-;; is no convenient predicate for that.
-
-(define_expand "reload_insi"
-  [(set (match_operand:SI 0 "register_operand" "=b")
-	(match_operand:SI 1 "" "b"))
-   (clobber (match_operand:SI 2 "register_operand" "=&d"))]
-  "TARGET_MIPS16"
-  "
-{
-  if (TARGET_MIPS16
-      && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
-    {
-      emit_insn (gen_movsi (operands[2], GEN_INT (1)));
-      /* This is gen_mulsi3_internal, but we need to fill in the
-	 scratch registers.  */
-      emit_insn (gen_rtx (PARALLEL, VOIDmode,
-			  gen_rtvec (3,
-				     gen_rtx (SET, VOIDmode,
-					      operands[0],
-					      gen_rtx (MULT, SImode,
-						       operands[1],
-						       operands[2])),
-				     gen_rtx (CLOBBER, VOIDmode,
-					      gen_rtx (REG, SImode, 64)),
-				     gen_rtx (CLOBBER, VOIDmode,
-					      gen_rtx (REG, SImode, 66)))));
-      DONE;
-    }
-
-  /* If this is a plus, then this must be an add of the stack pointer against
-     either a hard register or a pseudo.  */
-  if (TARGET_MIPS16 && GET_CODE (operands[1]) == PLUS)
-    {
-      rtx plus_op;
-
-      if (XEXP (operands[1], 0) == stack_pointer_rtx)
-	plus_op = XEXP (operands[1], 1);
-      else if (XEXP (operands[1], 1) == stack_pointer_rtx)
-	plus_op = XEXP (operands[1], 0);
-      else
-	abort ();
-
-      /* We should have a register now.  */
-      if (GET_CODE (plus_op) != REG)
-	abort ();
-
-      if (REGNO (plus_op) < FIRST_PSEUDO_REGISTER)
-	{
-	  /* We have to have at least one temporary register which is not
-	     overlapping plus_op.  */
-	  if (! rtx_equal_p (plus_op, operands[0]))
-	    {
-	      emit_move_insn (operands[0], stack_pointer_rtx);
-	      emit_insn (gen_addsi3 (operands[0], operands[0], plus_op));
-	    }
-	  else if (! rtx_equal_p (plus_op, operands[2]))
-	    {
-	      emit_move_insn (operands[2], stack_pointer_rtx);
-	      emit_insn (gen_addsi3 (operands[0], plus_op, operands[2]));
-	    }
-	  else
-	    abort ();
-	}
-      else
-	{
-	  /* We need two registers in this case.  */
-	  if (! rtx_equal_p (operands[0], operands[2]))
-	    {
-	      emit_move_insn (operands[0], stack_pointer_rtx);
-	      emit_move_insn (operands[2], plus_op);
-	      emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
-	    }
-	  else
-	    abort ();
-	}
-      DONE;
-    }
-
-  /* FIXME: I don't know how to get a value into the HI register.  */
-  emit_move_insn (operands[0], operands[1]);
-  DONE;
-}")
-
-;; This insn handles moving CCmode values.  It's really just a
-;; slightly simplified copy of movsi_internal2, with additional cases
-;; to move a condition register to a general register and to move
-;; between the general registers and the floating point registers.
-
-(define_insn "movcc"
-  [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m")
-	(match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2,1,1,2,1,2,1,1,1,1,2,1,2")])
-
-;; Reload condition code registers.  These need scratch registers.
-
-(define_expand "reload_incc"
-  [(set (match_operand:CC 0 "register_operand" "=z")
-	(match_operand:CC 1 "general_operand" "z"))
-   (clobber (match_operand:TF 2 "register_operand" "=&f"))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "
-{
-  rtx source;
-  rtx fp1, fp2;
-
-  /* This is called when are copying some value into a condition code
-     register.  Operand 0 is the condition code register.  Operand 1
-     is the source.  Operand 2 is a scratch register; we use TFmode
-     because we actually need two floating point registers.  */
-  if (! ST_REG_P (true_regnum (operands[0]))
-      || ! FP_REG_P (true_regnum (operands[2])))
-    abort ();
-
-  /* We need to get the source in SFmode so that the insn is
-     recognized.  */
-  if (GET_CODE (operands[1]) == MEM)
-    source = change_address (operands[1], SFmode, NULL_RTX);
-  else if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)
-    source = gen_rtx (REG, SFmode, true_regnum (operands[1]));
-  else
-    source = operands[1];
-
-  fp1 = gen_rtx (REG, SFmode, REGNO (operands[2]));
-  fp2 = gen_rtx (REG, SFmode, REGNO (operands[2]) + 1);
-
-  emit_insn (gen_move_insn (fp1, source));
-  emit_insn (gen_move_insn (fp2, gen_rtx (REG, SFmode, 0)));
-  emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-		      gen_rtx (LT, CCmode, fp2, fp1)));
-
-  DONE;
-}")
-
-(define_expand "reload_outcc"
-  [(set (match_operand:CC 0 "general_operand" "=z")
-	(match_operand:CC 1 "register_operand" "z"))
-   (clobber (match_operand:CC 2 "register_operand" "=&d"))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "
-{
-  /* This is called when we are copying a condition code register out
-     to save it somewhere.  Operand 0 should be the location we are
-     going to save it to.  Operand 1 should be the condition code
-     register.  Operand 2 should be a scratch general purpose register
-     created for us by reload.  The mips_secondary_reload_class
-     function should have told reload that we don't need a scratch
-     register if the destination is a general purpose register anyhow.  */
-  if (ST_REG_P (true_regnum (operands[0]))
-      || GP_REG_P (true_regnum (operands[0]))
-      || ! ST_REG_P (true_regnum (operands[1]))
-      || ! GP_REG_P (true_regnum (operands[2])))
-    abort ();
-
-  /* All we have to do is copy the value from the condition code to
-     the data register, which movcc can handle, and then store the
-     value into the real final destination.  */
-  emit_insn (gen_move_insn (operands[2], operands[1]));
-  emit_insn (gen_move_insn (operands[0], operands[2]));
-
-  DONE;
-}")
-
-;; MIPS4 supports loading and storing a floating point register from
-;; the sum of two general registers.  We use two versions for each of
-;; these four instructions: one where the two general registers are
-;; SImode, and one where they are DImode.  This is because general
-;; registers will be in SImode when they hold 32 bit values, but,
-;; since the 32 bit values are always sign extended, the [ls][wd]xc1
-;; instructions will still work correctly.
-
-;; ??? Perhaps it would be better to support these instructions by
-;; modifying GO_IF_LEGITIMATE_ADDRESS and friends.  However, since
-;; these instructions can only be used to load and store floating
-;; point registers, that would probably cause trouble in reload.
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "register_operand" "d"))))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "lwxc1\\t%0,%1(%2)"
-  [(set_attr "type"	"load")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
-			 (match_operand:DI 2 "se_register_operand" "d"))))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "lwxc1\\t%0,%1(%2)"
-  [(set_attr "type"	"load")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "register_operand" "d"))))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "ldxc1\\t%0,%1(%2)"
-  [(set_attr "type"	"load")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
-			 (match_operand:DI 2 "se_register_operand" "d"))))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "ldxc1\\t%0,%1(%2)"
-  [(set_attr "type"	"load")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "register_operand" "d")))
-	(match_operand:SF 0 "register_operand" "=f"))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "swxc1\\t%0,%1(%2)"
-  [(set_attr "type"	"store")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
-			 (match_operand:DI 2 "se_register_operand" "d")))
-	(match_operand:SF 0 "register_operand" "=f"))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "swxc1\\t%0,%1(%2)"
-  [(set_attr "type"	"store")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "register_operand" "d")))
-	(match_operand:DF 0 "register_operand" "=f"))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "sdxc1\\t%0,%1(%2)"
-  [(set_attr "type"	"store")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
-			 (match_operand:DI 2 "se_register_operand" "d")))
-	(match_operand:DF 0 "register_operand" "=f"))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "sdxc1\\t%0,%1(%2)"
-  [(set_attr "type"	"store")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1")])
-
-;; 16-bit Integer moves
-
-;; Unlike most other insns, the move insns can't be split with
-;; different predicates, because register spilling and other parts of
-;; the compiler, have memoized the insn number already.
-;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if ((reload_in_progress | reload_completed) == 0
-      && !register_operand (operands[0], HImode)
-      && !register_operand (operands[1], HImode)
-      && (TARGET_MIPS16
-	  || (GET_CODE (operands[1]) != CONST_INT
-	  || INTVAL (operands[1]) != 0)))
-    {
-      rtx temp = force_reg (HImode, operands[1]);
-      emit_move_insn (operands[0], temp);
-      DONE;
-    }
-}")
-
-;; The difference between these two is whether or not ints are allowed
-;; in FP registers (off by default, use -mdebugh to enable).
-
-(define_insn "movhi_internal1"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d")
-	(match_operand:HI 1 "general_operand"       "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
-  "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
-   && (register_operand (operands[0], HImode)
-       || register_operand (operands[1], HImode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
-  "* return mips_move_1word (operands, insn, TRUE);"
-  [(set_attr "type"	"move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
-   (set_attr "mode"	"HI")
-   (set_attr "length"	"1,1,1,2,1,2,1,1,1,1,1")])
-
-(define_insn "movhi_internal2"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
-	(match_operand:HI 1 "general_operand"       "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
-  "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
-   && (register_operand (operands[0], HImode)
-       || register_operand (operands[1], HImode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
-  "* return mips_move_1word (operands, insn, TRUE);"
-  [(set_attr "type"	"move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
-   (set_attr "mode"	"HI")
-   (set_attr "length"	"1,1,1,2,1,2,1,1,1,1")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
-	(match_operand:HI 1 "general_operand"      "d,d,y,K,N,R,m,d,d,*x"))]
-  "TARGET_MIPS16
-   && (register_operand (operands[0], HImode)
-       || register_operand (operands[1], HImode))"
-  "* return mips_move_1word (operands, insn, TRUE);"
-  [(set_attr "type"	"move,move,move,arith,arith,load,load,store,store,hilo")
-   (set_attr "mode"	"HI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (const_int 1)
-		 (const_int 1)
-		 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
-			       (const_int 2)
-			       (const_int 3))
-		 (const_int 1)
-		 (const_int 2)
-		 (const_int 1)
-		 (const_int 2)
-		 (const_int 1)])])
-
-
-;; On the mips16, we can split lh $r,N($r) into an add and a load,
-;; when the original load is a 4 byte instruction but the add and the
-;; load are 2 2 byte instructions.
-
-(define_split
-  [(set (match_operand:HI 0 "register_operand" "")
-	(mem:HI (plus:SI (match_dup 0)
-			 (match_operand:SI 1 "const_int_operand" ""))))]
-  "TARGET_MIPS16 && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && ((INTVAL (operands[1]) < 0
-	&& INTVAL (operands[1]) >= -0x80)
-       || (INTVAL (operands[1]) >= 32 * 2
-	   && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
-       || (INTVAL (operands[1]) >= 0
-	   && INTVAL (operands[1]) < 32 * 2
-	   && (INTVAL (operands[1]) & 1) != 0))"
-  [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
-   (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-  if (val < 0)
-    operands[2] = GEN_INT (0);
-  else if (val >= 32 * 2)
-    {
-      int off = val & 1;
-
-      operands[1] = GEN_INT (0x7e + off);
-      operands[2] = GEN_INT (val - off - 0x7e);
-    }
-  else
-    {
-      int off = val & 1;
-
-      operands[1] = GEN_INT (off);
-      operands[2] = GEN_INT (val - off);
-    }
-}")
-
-;; 8-bit Integer moves
-
-;; Unlike most other insns, the move insns can't be split with
-;; different predicates, because register spilling and other parts of
-;; the compiler, have memoized the insn number already.
-;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if ((reload_in_progress | reload_completed) == 0
-      && !register_operand (operands[0], QImode)
-      && !register_operand (operands[1], QImode)
-      && (TARGET_MIPS16
-	  || (GET_CODE (operands[1]) != CONST_INT
-	  || INTVAL (operands[1]) != 0)))
-    {
-      rtx temp = force_reg (QImode, operands[1]);
-      emit_move_insn (operands[0], temp);
-      DONE;
-    }
-}")
-
-;; The difference between these two is whether or not ints are allowed
-;; in FP registers (off by default, use -mdebugh to enable).
-
-(define_insn "movqi_internal1"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
-	(match_operand:QI 1 "general_operand"       "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
-  "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
-   && (register_operand (operands[0], QImode)
-       || register_operand (operands[1], QImode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
-  "* return mips_move_1word (operands, insn, TRUE);"
-  [(set_attr "type"	"move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
-   (set_attr "mode"	"QI")
-   (set_attr "length"	"1,1,1,2,1,2,1,1,1,1,1")])
-
-(define_insn "movqi_internal2"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
-	(match_operand:QI 1 "general_operand"       "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
-  "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
-   && (register_operand (operands[0], QImode)
-       || register_operand (operands[1], QImode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
-  "* return mips_move_1word (operands, insn, TRUE);"
-  [(set_attr "type"	"move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
-   (set_attr "mode"	"QI")
-   (set_attr "length"	"1,1,1,2,1,2,1,1,1,1")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
-	(match_operand:QI 1 "general_operand"      "d,d,y,K,N,R,m,d,d,*x"))]
-  "TARGET_MIPS16
-   && (register_operand (operands[0], QImode)
-       || register_operand (operands[1], QImode))"
-  "* return mips_move_1word (operands, insn, TRUE);"
-  [(set_attr "type"	"move,move,move,arith,arith,load,load,store,store,hilo")
-   (set_attr "mode"	"QI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (const_int 1)
-		 (const_int 1)
-		 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
-			       (const_int 1)
-			       (const_int 2))
-		 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
-			       (const_int 2)
-			       (const_int 3))
-		 (const_int 1)
-		 (const_int 2)
-		 (const_int 1)
-		 (const_int 2)
-		 (const_int 1)])])
-
-
-;; On the mips16, we can split lb $r,N($r) into an add and a load,
-;; when the original load is a 4 byte instruction but the add and the
-;; load are 2 2 byte instructions.
-
-(define_split
-  [(set (match_operand:QI 0 "register_operand" "")
-	(mem:QI (plus:SI (match_dup 0)
-			 (match_operand:SI 1 "const_int_operand" ""))))]
-  "TARGET_MIPS16 && reload_completed
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && ((INTVAL (operands[1]) < 0
-	&& INTVAL (operands[1]) >= -0x80)
-       || (INTVAL (operands[1]) >= 32
-	   && INTVAL (operands[1]) <= 31 + 0x7f))"
-  [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
-   (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-  if (val < 0)
-    operands[2] = GEN_INT (0);
-  else
-    {
-      operands[1] = GEN_INT (0x7f);
-      operands[2] = GEN_INT (val - 0x7f);
-    }
-}")
-
-;; 32-bit floating point moves
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if ((reload_in_progress | reload_completed) == 0
-      && !register_operand (operands[0], SFmode)
-      && !register_operand (operands[1], SFmode)
-      && (TARGET_MIPS16
-	  || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
-	       && operands[1] != CONST0_RTX (SFmode))))
-    {
-      rtx temp = force_reg (SFmode, operands[1]);
-      emit_move_insn (operands[0], temp);
-      DONE;
-    }
-}")
-
-(define_insn "movsf_internal1"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m")
-	(match_operand:SF 1 "general_operand" "f,G,R,Fm,fG,fG,*d,*f,*G*d,*R,*F*m,*d,*d"))]
-  "TARGET_HARD_FLOAT
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
-       || operands[1] == CONST0_RTX (SFmode))"
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1,1,1,2,1,2,1,1,1,1,2,1,2")])
-
-
-(define_insn "movsf_internal2"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,R,m")
-	(match_operand:SF 1 "general_operand" "      Gd,R,Fm,d,d"))]
-  "TARGET_SOFT_FLOAT && !TARGET_MIPS16
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
-       || operands[1] == CONST0_RTX (SFmode))"
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"move,load,load,store,store")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1,1,2,1,2")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,d,R,m")
-	(match_operand:SF 1 "general_operand"      "d,d,y,R,Fm,d,d"))]
-  "TARGET_MIPS16
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode))"
-  "* return mips_move_1word (operands, insn, FALSE);"
-  [(set_attr "type"	"move,move,move,load,load,store,store")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"1,1,1,1,2,1,2")])
-
-
-;; 64-bit floating point moves
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if ((reload_in_progress | reload_completed) == 0
-      && !register_operand (operands[0], DFmode)
-      && !register_operand (operands[1], DFmode)
-      && (TARGET_MIPS16
-	  || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
-	       && operands[1] != CONST0_RTX (DFmode))))
-    {
-      rtx temp = force_reg (DFmode, operands[1]);
-      emit_move_insn (operands[0], temp);
-      DONE;
-    }
-}")
-
-(define_insn "movdf_internal1"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,To,f,*f,*d,*d,*d,*d,*R,*T")
-	(match_operand:DF 1 "general_operand" "f,R,To,fG,fG,F,*d,*f,*d*G,*R,*T*F,*d,*d"))]
-  "TARGET_HARD_FLOAT && !(TARGET_FLOAT64 && !TARGET_64BIT)
-   && TARGET_DOUBLE_FLOAT
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
-       || operands[1] == CONST0_RTX (DFmode))"
-  "* return mips_move_2words (operands, insn); "
-  [(set_attr "type"	"move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1,2,4,2,4,4,2,2,2,2,4,2,4")])
-
-(define_insn "movdf_internal1a"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,R,R,To,To,f,*d,*d,*d,*To,*R")
-	(match_operand:DF 1 "general_operand"      " f,To,f,G,f,G,F,*F,*To,*R,*d,*d"))]
-  "TARGET_HARD_FLOAT && (TARGET_FLOAT64 && !TARGET_64BIT)
-   && TARGET_DOUBLE_FLOAT
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode)
-       || (GET_CODE (operands [0]) == MEM
-	   && ((GET_CODE (operands[1]) == CONST_INT
-		&& INTVAL (operands[1]) == 0)
-	       || operands[1] == CONST0_RTX (DFmode))))"
-  "* return mips_move_2words (operands, insn); "
-  [(set_attr "type"	"move,load,store,store,store,store,load,load,load,load,store,store")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"1,2,1,1,2,2,2,2,2,1,2,1")])
-
-(define_insn "movdf_internal2"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,To")
-	(match_operand:DF 1 "general_operand" "dG,R,ToF,d,d"))]
-  "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode)
-       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
-       || operands[1] == CONST0_RTX (DFmode))"
-  "* return mips_move_2words (operands, insn); "
-  [(set_attr "type"	"move,load,load,store,store")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"2,2,4,2,4")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,d,R,To")
-	(match_operand:DF 1 "general_operand" "d,d,y,R,ToF,d,d"))]
-  "TARGET_MIPS16
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
-  "* return mips_move_2words (operands, insn);"
-  [(set_attr "type"	"move,move,move,load,load,store,store")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"2,2,2,2,4,2,4")])
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-	(match_operand:DF 1 "register_operand" ""))]
-  "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
-  [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
-   (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
-  "")
-
-;; Instructions to load the global pointer register.
-;; This is volatile to make sure that the scheduler won't move any symbol_ref
-;; uses in front of it.  All symbol_refs implicitly use the gp reg.
-
-(define_insn "loadgp"
-  [(set (reg:DI 28)
-	(unspec_volatile:DI [(match_operand:DI 0 "address_operand" "")
-			     (match_operand:DI 1 "register_operand" "")] 2))
-   (clobber (reg:DI 1))]
-  ""
-  "%[lui\\t$1,%%hi(%%neg(%%gp_rel(%a0)))\\n\\taddiu\\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\\n\\tdaddu\\t$gp,$1,%1%]"
-  [(set_attr "type"	"move")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"3")])
-
-;; Block moves, see mips.c for more details.
-;; Argument 0 is the destination
-;; Argument 1 is the source
-;; Argument 2 is the length
-;; Argument 3 is the alignment
-
-(define_expand "movstrsi"
-  [(parallel [(set (match_operand:BLK 0 "general_operand" "")
-		   (match_operand:BLK 1 "general_operand" ""))
-	      (use (match_operand:SI 2 "arith32_operand" ""))
-	      (use (match_operand:SI 3 "immediate_operand" ""))])]
-  "!TARGET_MIPS16"
-  "
-{
-  if (operands[0])		/* avoid unused code messages */
-    {
-      expand_block_move (operands);
-      DONE;
-    }
-}")
-
-;; Insn generated by block moves
-
-(define_insn "movstrsi_internal"
-  [(set (match_operand:BLK 0 "memory_operand" "=o")	;; destination
-	(match_operand:BLK 1 "memory_operand" "o"))	;; source
-   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
-   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
-   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
-   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
-   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
-   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
-   (use (const_int 0))]					;; normal block move
-  ""
-  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
-  [(set_attr "type"	"store")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"20")])
-
-;; We need mips16 versions, because an offset from the stack pointer
-;; is not offsettable, since the stack pointer can only handle 4 and 8
-;; byte loads.
-
-(define_insn ""
-  [(set (match_operand:BLK 0 "memory_operand" "=d")	;; destination
-	(match_operand:BLK 1 "memory_operand" "d"))	;; source
-   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
-   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
-   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
-   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
-   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
-   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
-   (use (const_int 0))]					;; normal block move
-  "TARGET_MIPS16"
-  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
-  [(set_attr "type"	"multi")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"20")])
-
-(define_insn ""
-  [(set (match_operand:BLK 0 "memory_operand" "=d")	;; destination
-	(match_operand:BLK 1 "memory_operand" "o"))	;; source
-   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
-   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
-   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
-   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
-   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
-   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
-   (use (const_int 0))]					;; normal block move
-  "TARGET_MIPS16"
-  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
-  [(set_attr "type"	"multi")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"20")])
-
-(define_insn ""
-  [(set (match_operand:BLK 0 "memory_operand" "=o")	;; destination
-	(match_operand:BLK 1 "memory_operand" "d"))	;; source
-   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
-   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
-   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
-   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
-   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
-   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
-   (use (const_int 0))]					;; normal block move
-  "TARGET_MIPS16"
-  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
-  [(set_attr "type"	"multi")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"20")])
-
-;; Split a block move into 2 parts, the first part is everything
-;; except for the last move, and the second part is just the last
-;; store, which is exactly 1 instruction (ie, not a usw), so it can
-;; fill a delay slot.  This also prevents a bug in delayed branches
-;; from showing up, which reuses one of the registers in our clobbers.
-
-(define_split
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
-	(mem:BLK (match_operand:SI 1 "register_operand" "")))
-   (clobber (match_operand:SI 4 "register_operand" ""))
-   (clobber (match_operand:SI 5 "register_operand" ""))
-   (clobber (match_operand:SI 6 "register_operand" ""))
-   (clobber (match_operand:SI 7 "register_operand" ""))
-   (use (match_operand:SI 2 "small_int" ""))
-   (use (match_operand:SI 3 "small_int" ""))
-   (use (const_int 0))]
-
-  "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0"
-
-  ;; All but the last move
-  [(parallel [(set (mem:BLK (match_dup 0))
-		   (mem:BLK (match_dup 1)))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))
-	      (clobber (match_dup 7))
-	      (use (match_dup 2))
-	      (use (match_dup 3))
-	      (use (const_int 1))])
-
-   ;; The last store, so it can fill a delay slot
-   (parallel [(set (mem:BLK (match_dup 0))
-		   (mem:BLK (match_dup 1)))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))
-	      (clobber (match_dup 7))
-	      (use (match_dup 2))
-	      (use (match_dup 3))
-	      (use (const_int 2))])]
-
-  "")
-
-(define_insn "movstrsi_internal2"
-  [(set (match_operand:BLK 0 "memory_operand" "=o")	;; destination
-	(match_operand:BLK 1 "memory_operand" "o"))	;; source
-   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
-   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
-   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
-   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
-   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
-   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
-   (use (const_int 1))]					;; all but last store
-  ""
-  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
-  [(set_attr "type"	"store")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"20")])
-
-(define_insn ""
-  [(set (match_operand:BLK 0 "memory_operand" "=d")	;; destination
-	(match_operand:BLK 1 "memory_operand" "d"))	;; source
-   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
-   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
-   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
-   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
-   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
-   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
-   (use (const_int 1))]					;; all but last store
-  "TARGET_MIPS16"
-  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
-  [(set_attr "type"	"multi")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"20")])
-
-(define_insn "movstrsi_internal3"
-  [(set (match_operand:BLK 0 "memory_operand" "=Ro")	;; destination
-	(match_operand:BLK 1 "memory_operand" "Ro"))	;; source
-   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
-   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
-   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
-   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
-   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
-   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
-   (use (const_int 2))]					;; just last store of block move
-  ""
-  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
-  [(set_attr "type"	"store")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:BLK 0 "memory_operand" "=d")	;; destination
-	(match_operand:BLK 1 "memory_operand" "d"))	;; source
-   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
-   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
-   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
-   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
-   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
-   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
-   (use (const_int 2))]					;; just last store of block move
-  "TARGET_MIPS16"
-  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
-  [(set_attr "type"	"store")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-
-;;  ....................
-;;	SHIFTS
-;;  ....................
-
-;; Many of these instructions uses trivial define_expands, because we
-;; want to use a different set of constraints when TARGET_MIPS16.
-
-(define_expand "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashift:SI (match_operand:SI 1 "register_operand" "d")
-		   (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "
-{
-  /* On the mips16, a shift of more than 8 is a four byte instruction,
-     so, for a shift between 8 and 16, it is just as fast to do two
-     shifts of 8 or less.  If there is a lot of shifting going on, we
-     may win in CSE.  Otherwise combine will put the shifts back
-     together again.  This can be called by function_arg, so we must
-     be careful not to allocate a new register if we've reached the
-     reload pass.  */
-  if (TARGET_MIPS16
-      && optimize
-      && GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) > 8
-      && INTVAL (operands[2]) <= 16
-      && ! reload_in_progress
-      && ! reload_completed)
-    {
-      rtx temp = gen_reg_rtx (SImode);
-
-      emit_insn (gen_ashlsi3_internal2 (temp, operands[1], GEN_INT (8)));
-      emit_insn (gen_ashlsi3_internal2 (operands[0], temp,
-					GEN_INT (INTVAL (operands[2]) - 8)));
-      DONE;
-    }
-}")
-
-(define_insn "ashlsi3_internal1"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashift:SI (match_operand:SI 1 "register_operand" "d")
-		   (match_operand:SI 2 "arith_operand" "dI")))]
-  "!TARGET_MIPS16"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
-  return \"sll\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn "ashlsi3_internal2"
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0,d")
-		   (match_operand:SI 2 "arith_operand" "d,I")))]
-  "TARGET_MIPS16"
-  "*
-{
-  if (which_alternative == 0)
-    return \"sll\\t%0,%2\";
-
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
-  return \"sll\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
-			       (const_int 1)
-			       (const_int 2))])])
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashift:SI (match_operand:SI 1 "register_operand" "")
-		   (match_operand:SI 2 "const_int_operand" "")))]
-  "TARGET_MIPS16
-   && reload_completed
-   && GET_CODE (operands[2]) == CONST_INT
-   && INTVAL (operands[2]) > 8
-   && INTVAL (operands[2]) <= 16"
-  [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 8)))
-   (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
-"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-(define_expand "ashldi3"
-  [(parallel [(set (match_operand:DI 0 "register_operand" "")
-		   (ashift:DI (match_operand:DI 1 "se_register_operand" "")
-			      (match_operand:SI 2 "arith_operand" "")))
-	      (clobber (match_dup  3))])]
-  "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
-  "
-{
-  if (TARGET_64BIT)
-    {
-      /* On the mips16, a shift of more than 8 is a four byte
-	 instruction, so, for a shift between 8 and 16, it is just as
-	 fast to do two shifts of 8 or less.  If there is a lot of
-	 shifting going on, we may win in CSE.  Otherwise combine will
-	 put the shifts back together again.  This can be called by
-	 function_arg, so we must be careful not to allocate a new
-	 register if we've reached the reload pass.  */
-      if (TARGET_MIPS16
-	  && optimize
-	  && GET_CODE (operands[2]) == CONST_INT
-	  && INTVAL (operands[2]) > 8
-	  && INTVAL (operands[2]) <= 16
-	  && ! reload_in_progress
-	  && ! reload_completed)
-	{
-	  rtx temp = gen_reg_rtx (DImode);
-
-	  emit_insn (gen_ashldi3_internal4 (temp, operands[1], GEN_INT (8)));
-	  emit_insn (gen_ashldi3_internal4 (operands[0], temp,
-					    GEN_INT (INTVAL (operands[2]) - 8)));
-	  DONE;
-	}
-
-      emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
-					operands[2]));
-      DONE;
-    }
-
-  operands[3] = gen_reg_rtx (SImode);
-}")
-
-
-(define_insn "ashldi3_internal"
-  [(set (match_operand:DI 0 "register_operand" "=&d")
-	(ashift:DI (match_operand:DI 1 "register_operand" "d")
-		   (match_operand:SI 2 "register_operand" "d")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-  "* 
-{
-  operands[4] = const0_rtx;
-  dslots_jump_total += 3;
-  dslots_jump_filled += 2;
-
-  return \"sll\\t%3,%2,26\\n\\
-\\tbgez\\t%3,1f\\n\\
-\\tsll\\t%M0,%L1,%2\\n\\
-\\t%(b\\t3f\\n\\
-\\tmove\\t%L0,%z4%)\\n\\
-\\n\\
-1:\\n\\
-\\t%(beq\\t%3,%z4,2f\\n\\
-\\tsll\\t%M0,%M1,%2%)\\n\\
-\\n\\
-\\tsubu\\t%3,%z4,%2\\n\\
-\\tsrl\\t%3,%L1,%3\\n\\
-\\tor\\t%M0,%M0,%3\\n\\
-2:\\n\\
-\\tsll\\t%L0,%L1,%2\\n\\
-3:\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"12")])
-
-
-(define_insn "ashldi3_internal2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ashift:DI (match_operand:DI 1 "register_operand" "d")
-		   (match_operand:SI 2 "small_int" "IJK")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && (INTVAL (operands[2]) & 32) != 0"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-  operands[4] = const0_rtx;
-  return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"2")])
-
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashift:DI (match_operand:DI 1 "register_operand" "")
-		   (match_operand:SI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-   && (INTVAL (operands[2]) & 32) != 0"
-
-  [(set (subreg:SI (match_dup 0) 1) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
-   (set (subreg:SI (match_dup 0) 0) (const_int 0))]
-
-  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashift:DI (match_operand:DI 1 "register_operand" "")
-		   (match_operand:SI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-   && (INTVAL (operands[2]) & 32) != 0"
-
-  [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
-   (set (subreg:SI (match_dup 0) 1) (const_int 0))]
-
-  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "ashldi3_internal3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ashift:DI (match_operand:DI 1 "register_operand" "d")
-		   (match_operand:SI 2 "small_int" "IJK")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && (INTVAL (operands[2]) & 63) < 32
-   && (INTVAL (operands[2]) & 63) != 0"
-  "*
-{
-  int amount = INTVAL (operands[2]);
-
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = const0_rtx;
-  operands[5] = GEN_INT (((-amount) & 31));
-
-  return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4")])
-
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashift:DI (match_operand:DI 1 "register_operand" "")
-		   (match_operand:SI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-   && (INTVAL (operands[2]) & 63) < 32
-   && (INTVAL (operands[2]) & 63) != 0"
-
-  [(set (subreg:SI (match_dup 0) 1)
-	(ashift:SI (subreg:SI (match_dup 1) 1)
-		   (match_dup 2)))
-
-   (set (match_dup 3)
-	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
-		     (match_dup 4)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(ior:SI (subreg:SI (match_dup 0) 1)
-		(match_dup 3)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(ashift:SI (subreg:SI (match_dup 1) 0)
-		   (match_dup 2)))]
-  "
-{
-  int amount = INTVAL (operands[2]);
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
-}")
-
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashift:DI (match_operand:DI 1 "register_operand" "")
-		   (match_operand:SI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-   && (INTVAL (operands[2]) & 63) < 32
-   && (INTVAL (operands[2]) & 63) != 0"
-
-  [(set (subreg:SI (match_dup 0) 0)
-	(ashift:SI (subreg:SI (match_dup 1) 0)
-		   (match_dup 2)))
-
-   (set (match_dup 3)
-	(lshiftrt:SI (subreg:SI (match_dup 1) 1)
-		     (match_dup 4)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(ior:SI (subreg:SI (match_dup 0) 0)
-		(match_dup 3)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(ashift:SI (subreg:SI (match_dup 1) 1)
-		   (match_dup 2)))]
-  "
-{
-  int amount = INTVAL (operands[2]);
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
-}")
-
-
-(define_insn "ashldi3_internal4"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ashift:DI (match_operand:DI 1 "se_register_operand" "d")
-		   (match_operand:SI 2 "arith_operand" "dI")))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
-  return \"dsll\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(ashift:DI (match_operand:DI 1 "se_register_operand" "0,d")
-		   (match_operand:SI 2 "arith_operand" "d,I")))]
-  "TARGET_64BIT && TARGET_MIPS16"
-  "*
-{
-  if (which_alternative == 0)
-    return \"dsll\\t%0,%2\";
-
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
-  return \"dsll\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
-			       (const_int 1)
-			       (const_int 2))])])
-
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashift:DI (match_operand:DI 1 "register_operand" "")
-		   (match_operand:SI 2 "const_int_operand" "")))]
-  "TARGET_MIPS16 && TARGET_64BIT
-   && reload_completed
-   && GET_CODE (operands[2]) == CONST_INT
-   && INTVAL (operands[2]) > 8
-   && INTVAL (operands[2]) <= 16"
-  [(set (match_dup 0) (ashift:DI (match_dup 1) (const_int 8)))
-   (set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))]
-"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
-		     (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "
-{
-  /* On the mips16, a shift of more than 8 is a four byte instruction,
-     so, for a shift between 8 and 16, it is just as fast to do two
-     shifts of 8 or less.  If there is a lot of shifting going on, we
-     may win in CSE.  Otherwise combine will put the shifts back
-     together again.  */
-  if (TARGET_MIPS16
-      && optimize
-      && GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) > 8
-      && INTVAL (operands[2]) <= 16)
-    {
-      rtx temp = gen_reg_rtx (SImode);
-
-      emit_insn (gen_ashrsi3_internal2 (temp, operands[1], GEN_INT (8)));
-      emit_insn (gen_ashrsi3_internal2 (operands[0], temp,
-					GEN_INT (INTVAL (operands[2]) - 8)));
-      DONE;
-    }
-}")
-
-(define_insn "ashrsi3_internal1"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
-		     (match_operand:SI 2 "arith_operand" "dI")))]
-  "!TARGET_MIPS16"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
-  return \"sra\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn "ashrsi3_internal2"
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
-		     (match_operand:SI 2 "arith_operand" "d,I")))]
-  "TARGET_MIPS16"
-  "*
-{
-  if (which_alternative == 0)
-    return \"sra\\t%0,%2\";
-
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
-  return \"sra\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
-			       (const_int 1)
-			       (const_int 2))])])
-
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:SI 2 "const_int_operand" "")))]
-  "TARGET_MIPS16
-   && reload_completed
-   && GET_CODE (operands[2]) == CONST_INT
-   && INTVAL (operands[2]) > 8
-   && INTVAL (operands[2]) <= 16"
-  [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 8)))
-   (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
-"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-(define_expand "ashrdi3"
-  [(parallel [(set (match_operand:DI 0 "register_operand" "")
-		   (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "")
-				(match_operand:SI 2 "arith_operand" "")))
-	      (clobber (match_dup  3))])]
-  "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
-  "
-{
-  if (TARGET_64BIT)
-    {
-      /* On the mips16, a shift of more than 8 is a four byte
-	 instruction, so, for a shift between 8 and 16, it is just as
-	 fast to do two shifts of 8 or less.  If there is a lot of
-	 shifting going on, we may win in CSE.  Otherwise combine will
-	 put the shifts back together again.  */
-      if (TARGET_MIPS16
-	  && optimize
-	  && GET_CODE (operands[2]) == CONST_INT
-	  && INTVAL (operands[2]) > 8
-	  && INTVAL (operands[2]) <= 16)
-	{
-	  rtx temp = gen_reg_rtx (DImode);
-
-	  emit_insn (gen_ashrdi3_internal4 (temp, operands[1], GEN_INT (8)));
-	  emit_insn (gen_ashrdi3_internal4 (operands[0], temp,
-					    GEN_INT (INTVAL (operands[2]) - 8)));
-	  DONE;
-	}
-
-      emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
-					operands[2]));
-      DONE;
-    }
-
-  operands[3] = gen_reg_rtx (SImode);
-}")
-
-
-(define_insn "ashrdi3_internal"
-  [(set (match_operand:DI 0 "register_operand" "=&d")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
-		     (match_operand:SI 2 "register_operand" "d")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-  "* 
-{
-  operands[4] = const0_rtx;
-  dslots_jump_total += 3;
-  dslots_jump_filled += 2;
-
-  return \"sll\\t%3,%2,26\\n\\
-\\tbgez\\t%3,1f\\n\\
-\\tsra\\t%L0,%M1,%2\\n\\
-\\t%(b\\t3f\\n\\
-\\tsra\\t%M0,%M1,31%)\\n\\
-\\n\\
-1:\\n\\
-\\t%(beq\\t%3,%z4,2f\\n\\
-\\tsrl\\t%L0,%L1,%2%)\\n\\
-\\n\\
-\\tsubu\\t%3,%z4,%2\\n\\
-\\tsll\\t%3,%M1,%3\\n\\
-\\tor\\t%L0,%L0,%3\\n\\
-2:\\n\\
-\\tsra\\t%M0,%M1,%2\\n\\
-3:\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"12")])
-
-
-(define_insn "ashrdi3_internal2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
-		     (match_operand:SI 2 "small_int" "IJK")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-  return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"2")])
-
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (match_operand:SI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
-   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-   && (INTVAL (operands[2]) & 32) != 0"
-
-  [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
-   (set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (const_int 31)))]
-
-  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (match_operand:SI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
-   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-   && (INTVAL (operands[2]) & 32) != 0"
-
-  [(set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
-   (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
-
-  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "ashrdi3_internal3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
-		     (match_operand:SI 2 "small_int" "IJK")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && (INTVAL (operands[2]) & 63) < 32
-   && (INTVAL (operands[2]) & 63) != 0"
-  "*
-{
-  int amount = INTVAL (operands[2]);
-
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
-
-  return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4")])
-
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (match_operand:SI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-   && (INTVAL (operands[2]) & 63) < 32
-   && (INTVAL (operands[2]) & 63) != 0"
-
-  [(set (subreg:SI (match_dup 0) 0)
-	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
-		     (match_dup 2)))
-
-   (set (match_dup 3)
-	(ashift:SI (subreg:SI (match_dup 1) 1)
-		   (match_dup 4)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(ior:SI (subreg:SI (match_dup 0) 0)
-		(match_dup 3)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(ashiftrt:SI (subreg:SI (match_dup 1) 1)
-		     (match_dup 2)))]
-  "
-{
-  int amount = INTVAL (operands[2]);
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
-}")
-
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (match_operand:SI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-   && (INTVAL (operands[2]) & 63) < 32
-   && (INTVAL (operands[2]) & 63) != 0"
-
-  [(set (subreg:SI (match_dup 0) 1)
-	(lshiftrt:SI (subreg:SI (match_dup 1) 1)
-		     (match_dup 2)))
-
-   (set (match_dup 3)
-	(ashift:SI (subreg:SI (match_dup 1) 0)
-		   (match_dup 4)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(ior:SI (subreg:SI (match_dup 0) 1)
-		(match_dup 3)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(ashiftrt:SI (subreg:SI (match_dup 1) 0)
-		     (match_dup 2)))]
-  "
-{
-  int amount = INTVAL (operands[2]);
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
-}")
-
-
-(define_insn "ashrdi3_internal4"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
-		     (match_operand:SI 2 "arith_operand" "dI")))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
-  return \"dsra\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(ashiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0")
-		     (match_operand:SI 2 "arith_operand" "d,I")))]
-  "TARGET_64BIT && TARGET_MIPS16"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
-  return \"dsra\\t%0,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
-			       (const_int 1)
-			       (const_int 2))])])
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (match_operand:SI 2 "const_int_operand" "")))]
-  "TARGET_MIPS16 && TARGET_64BIT
-   && reload_completed
-   && GET_CODE (operands[2]) == CONST_INT
-   && INTVAL (operands[2]) > 8
-   && INTVAL (operands[2]) <= 16"
-  [(set (match_dup 0) (ashiftrt:DI (match_dup 1) (const_int 8)))
-   (set (match_dup 0) (ashiftrt:DI (match_dup 0) (match_dup 2)))]
-"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
-		     (match_operand:SI 2 "arith_operand" "dI")))]
-  ""
-  "
-{
-  /* On the mips16, a shift of more than 8 is a four byte instruction,
-     so, for a shift between 8 and 16, it is just as fast to do two
-     shifts of 8 or less.  If there is a lot of shifting going on, we
-     may win in CSE.  Otherwise combine will put the shifts back
-     together again.  */
-  if (TARGET_MIPS16
-      && optimize
-      && GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) > 8
-      && INTVAL (operands[2]) <= 16)
-    {
-      rtx temp = gen_reg_rtx (SImode);
-
-      emit_insn (gen_lshrsi3_internal2 (temp, operands[1], GEN_INT (8)));
-      emit_insn (gen_lshrsi3_internal2 (operands[0], temp,
-					GEN_INT (INTVAL (operands[2]) - 8)));
-      DONE;
-    }
-}")
-
-(define_insn "lshrsi3_internal1"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
-		     (match_operand:SI 2 "arith_operand" "dI")))]
-  "!TARGET_MIPS16"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
-  return \"srl\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn "lshrsi3_internal2"
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
-		     (match_operand:SI 2 "arith_operand" "d,I")))]
-  "TARGET_MIPS16"
-  "*
-{
-  if (which_alternative == 0)
-    return \"srl\\t%0,%2\";
-
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
-  return \"srl\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
-			       (const_int 1)
-			       (const_int 2))])])
-
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:SI 2 "const_int_operand" "")))]
-  "TARGET_MIPS16
-   && reload_completed
-   && GET_CODE (operands[2]) == CONST_INT
-   && INTVAL (operands[2]) > 8
-   && INTVAL (operands[2]) <= 16"
-  [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 8)))
-   (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
-"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-;; If we load a byte on the mips16 as a bitfield, the resulting
-;; sequence of instructions is too complicated for combine, because it
-;; involves four instructions: a load, a shift, a constant load into a
-;; register, and an and (the key problem here is that the mips16 does
-;; not have and immediate).  We recognize a shift of a load in order
-;; to make it simple enough for combine to understand.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "R,m")
-		     (match_operand:SI 2 "immediate_operand" "I,I")))]
-  "TARGET_MIPS16"
-  "lw\\t%0,%1\;srl\\t%0,%2"
-  [(set_attr "type"	"load")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
-			       (const_int 2)
-			       (const_int 3))
-		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
-			       (const_int 3)
-			       (const_int 4))])])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "")
-		     (match_operand:SI 2 "immediate_operand" "")))]
-  "TARGET_MIPS16"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
-  "")
-
-(define_expand "lshrdi3"
-  [(parallel [(set (match_operand:DI 0 "register_operand" "")
-		   (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "")
-				(match_operand:SI 2 "arith_operand" "")))
-	      (clobber (match_dup  3))])]
-  "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
-  "
-{
-  if (TARGET_64BIT)
-    {
-      /* On the mips16, a shift of more than 8 is a four byte
-	 instruction, so, for a shift between 8 and 16, it is just as
-	 fast to do two shifts of 8 or less.  If there is a lot of
-	 shifting going on, we may win in CSE.  Otherwise combine will
-	 put the shifts back together again.  */
-      if (TARGET_MIPS16
-	  && optimize
-	  && GET_CODE (operands[2]) == CONST_INT
-	  && INTVAL (operands[2]) > 8
-	  && INTVAL (operands[2]) <= 16)
-	{
-	  rtx temp = gen_reg_rtx (DImode);
-
-	  emit_insn (gen_lshrdi3_internal4 (temp, operands[1], GEN_INT (8)));
-	  emit_insn (gen_lshrdi3_internal4 (operands[0], temp,
-					    GEN_INT (INTVAL (operands[2]) - 8)));
-	  DONE;
-	}
-
-      emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
-					operands[2]));
-      DONE;
-    }
-
-  operands[3] = gen_reg_rtx (SImode);
-}")
-
-
-(define_insn "lshrdi3_internal"
-  [(set (match_operand:DI 0 "register_operand" "=&d")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
-		     (match_operand:SI 2 "register_operand" "d")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-  "* 
-{
-  operands[4] = const0_rtx;
-  dslots_jump_total += 3;
-  dslots_jump_filled += 2;
-
-  return \"sll\\t%3,%2,26\\n\\
-\\tbgez\\t%3,1f\\n\\
-\\tsrl\\t%L0,%M1,%2\\n\\
-\\t%(b\\t3f\\n\\
-\\tmove\\t%M0,%z4%)\\n\\
-\\n\\
-1:\\n\\
-\\t%(beq\\t%3,%z4,2f\\n\\
-\\tsrl\\t%L0,%L1,%2%)\\n\\
-\\n\\
-\\tsubu\\t%3,%z4,%2\\n\\
-\\tsll\\t%3,%M1,%3\\n\\
-\\tor\\t%L0,%L0,%3\\n\\
-2:\\n\\
-\\tsrl\\t%M0,%M1,%2\\n\\
-3:\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"12")])
-
-
-(define_insn "lshrdi3_internal2"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
-		     (match_operand:SI 2 "small_int" "IJK")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && (INTVAL (operands[2]) & 32) != 0"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-  operands[4] = const0_rtx;
-  return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"2")])
-
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (match_operand:SI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-   && (INTVAL (operands[2]) & 32) != 0"
-
-  [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
-   (set (subreg:SI (match_dup 0) 1) (const_int 0))]
-
-  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (match_operand:SI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-   && (INTVAL (operands[2]) & 32) != 0"
-
-  [(set (subreg:SI (match_dup 0) 1) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
-   (set (subreg:SI (match_dup 0) 0) (const_int 0))]
-
-  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "lshrdi3_internal3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
-		   (match_operand:SI 2 "small_int" "IJK")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && (INTVAL (operands[2]) & 63) < 32
-   && (INTVAL (operands[2]) & 63) != 0"
-  "*
-{
-  int amount = INTVAL (operands[2]);
-
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
-
-  return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
-}"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4")])
-
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (match_operand:SI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-   && (INTVAL (operands[2]) & 63) < 32
-   && (INTVAL (operands[2]) & 63) != 0"
-
-  [(set (subreg:SI (match_dup 0) 0)
-	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
-		     (match_dup 2)))
-
-   (set (match_dup 3)
-	(ashift:SI (subreg:SI (match_dup 1) 1)
-		   (match_dup 4)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(ior:SI (subreg:SI (match_dup 0) 0)
-		(match_dup 3)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(lshiftrt:SI (subreg:SI (match_dup 1) 1)
-		     (match_dup 2)))]
-  "
-{
-  int amount = INTVAL (operands[2]);
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
-}")
-
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (match_operand:SI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-   && (INTVAL (operands[2]) & 63) < 32
-   && (INTVAL (operands[2]) & 63) != 0"
-
-  [(set (subreg:SI (match_dup 0) 1)
-	(lshiftrt:SI (subreg:SI (match_dup 1) 1)
-		     (match_dup 2)))
-
-   (set (match_dup 3)
-	(ashift:SI (subreg:SI (match_dup 1) 0)
-		   (match_dup 4)))
-
-   (set (subreg:SI (match_dup 0) 1)
-	(ior:SI (subreg:SI (match_dup 0) 1)
-		(match_dup 3)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
-		     (match_dup 2)))]
-  "
-{
-  int amount = INTVAL (operands[2]);
-  operands[2] = GEN_INT ((amount & 31));
-  operands[4] = GEN_INT (((-amount) & 31));
-}")
-
-
-(define_insn "lshrdi3_internal4"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
-		     (match_operand:SI 2 "arith_operand" "dI")))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
-  return \"dsrl\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-;; CYGNUS LOCAL vr5400/raeburn
-(define_insn "rotrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(rotatert:SI (match_operand:SI 1 "register_operand" "d")
-		     (match_operand:SI 2 "arith_operand" "dn")))]
-  "TARGET_MIPS5400"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
-  return \"ror\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")])
-
-(define_insn "rotrdi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(rotatert:DI (match_operand:DI 1 "register_operand" "d")
-		     (match_operand:DI 2 "arith_operand" "dn")))]
-  "TARGET_MIPS5400 && TARGET_64BIT"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
-  return \"dror\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")])
-;; END CYGNUS LOCAL
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(lshiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0")
-		     (match_operand:SI 2 "arith_operand" "d,I")))]
-  "TARGET_64BIT && TARGET_MIPS16"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
-  return \"dsrl\\t%0,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
-			       (const_int 1)
-			       (const_int 2))])])
-
-;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
-		     (match_operand:SI 2 "const_int_operand" "")))]
-  "TARGET_MIPS16
-   && reload_completed
-   && GET_CODE (operands[2]) == CONST_INT
-   && INTVAL (operands[2]) > 8
-   && INTVAL (operands[2]) <= 16"
-  [(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 8)))
-   (set (match_dup 0) (lshiftrt:DI (match_dup 0) (match_dup 2)))]
-"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
-
-;;  ....................
-;;	COMPARISONS
-;;  ....................
-
-;; Flow here is rather complex:
-;;  1)	The cmp{si,di,sf,df} routine is called.  It deposits the
-;;	arguments into the branch_cmp array, and the type into
-;;	branch_type.  No RTL is generated.
-;;  2)	The appropriate branch define_expand is called, which then
-;;	creates the appropriate RTL for the comparison and branch.
-;;	Different CC modes are used, based on what type of branch is
-;;	done, so that we can constrain things appropriately.  There
-;;	are assumptions in the rest of GCC that break if we fold the
-;;	operands into the branchs for integer operations, and use cc0
-;;	for floating point, so we use the fp status register instead.
-;;	If needed, an appropriate temporary is created to hold the
-;;	of the integer compare.
-
-(define_expand "cmpsi"
-  [(set (cc0)
-	(compare:CC (match_operand:SI 0 "register_operand" "")
-		    (match_operand:SI 1 "arith_operand" "")))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code message */
-    {
-      branch_cmp[0] = operands[0];
-      branch_cmp[1] = operands[1];
-      branch_type = CMP_SI;
-      DONE;
-    }
-}")
-
-(define_expand "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "register_operand" ""))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code message */
-    {
-      branch_cmp[0] = operands[0];
-      branch_cmp[1] = const0_rtx;
-      branch_type = CMP_SI;
-      DONE;
-    }
-}")
-
-(define_expand "cmpdi"
-  [(set (cc0)
-	(compare:CC (match_operand:DI 0 "se_register_operand" "")
-		    (match_operand:DI 1 "se_arith_operand" "")))]
-  "TARGET_64BIT"
-  "
-{
-  if (operands[0])		/* avoid unused code message */
-    {
-      branch_cmp[0] = operands[0];
-      branch_cmp[1] = operands[1];
-      branch_type = CMP_DI;
-      DONE;
-    }
-}")
-
-(define_expand "tstdi"
-  [(set (cc0)
-	(match_operand:DI 0 "se_register_operand" ""))]
-  "TARGET_64BIT"
-  "
-{
-  if (operands[0])		/* avoid unused code message */
-    {
-      branch_cmp[0] = operands[0];
-      branch_cmp[1] = const0_rtx;
-      branch_type = CMP_DI;
-      DONE;
-    }
-}")
-
-(define_expand "cmpdf"
-  [(set (cc0)
-	(compare:CC (match_operand:DF 0 "register_operand" "")
-		    (match_operand:DF 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "
-{
-  if (operands[0])		/* avoid unused code message */
-    {
-      branch_cmp[0] = operands[0];
-      branch_cmp[1] = operands[1];
-      branch_type = CMP_DF;
-      DONE;
-    }
-}")
-
-(define_expand "cmpsf"
-  [(set (cc0)
-	(compare:CC (match_operand:SF 0 "register_operand" "")
-		    (match_operand:SF 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "
-{
-  if (operands[0])		/* avoid unused code message */
-    {
-      branch_cmp[0] = operands[0];
-      branch_cmp[1] = operands[1];
-      branch_type = CMP_SF;
-      DONE;
-    }
-}")
-
-
-;;  ....................
-;;	CONDITIONAL BRANCHES
-;;  ....................
-
-(define_insn "branch_fp_ne"
-  [(set (pc)
-	(if_then_else (ne:CC (match_operand:CC 0 "register_operand" "z")
-			     (const_int 0))
-		      (match_operand 1 "pc_or_label_operand" "")
-		      (match_operand 2 "pc_or_label_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
-  return (operands[1] != pc_rtx) ? \"%*bc1t%?\\t%Z0%1\" : \"%*bc1f%?\\t%Z0%2\";
-}"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn "branch_fp_eq"
-  [(set (pc)
-	(if_then_else (eq:CC (match_operand:CC 0 "register_operand" "z")
-			     (const_int 0))
-		      (match_operand 1 "pc_or_label_operand" "")
-		      (match_operand 2 "pc_or_label_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
-  return (operands[1] != pc_rtx) ? \"%*bc1f%?\\t%Z0%1\" : \"%*bc1t%?\\t%Z0%2\";
-}"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn "branch_zero"
-  [(set (pc)
-	(if_then_else (match_operator:SI 0 "cmp_op"
-					 [(match_operand:SI 1 "register_operand" "d")
-					  (const_int 0)])
-	(match_operand 2 "pc_or_label_operand" "")
-	(match_operand 3 "pc_or_label_operand" "")))]
-  "!TARGET_MIPS16"
-  "*
-{
-  mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
-  if (operands[2] != pc_rtx)
-    {				/* normal jump */
-      switch (GET_CODE (operands[0]))
-	{
-	case EQ:  return \"%*beq%?\\t%z1,%.,%2\";
-	case NE:  return \"%*bne%?\\t%z1,%.,%2\";
-	case GTU: return \"%*bne%?\\t%z1,%.,%2\";
-	case LEU: return \"%*beq%?\\t%z1,%.,%2\";
-	case GEU: return \"%*j\\t%2\";
-	case LTU: return \"%*bne%?\\t%.,%.,%2\";
-	default:
-	  break;
-	}
-
-      return \"%*b%C0z%?\\t%z1,%2\";
-    }
-  else
-    {				/* inverted jump */
-      switch (GET_CODE (operands[0]))
-	{
-	case EQ:  return \"%*bne%?\\t%z1,%.,%3\";
-	case NE:  return \"%*beq%?\\t%z1,%.,%3\";
-	case GTU: return \"%*beq%?\\t%z1,%.,%3\";
-	case LEU: return \"%*bne%?\\t%z1,%.,%3\";
-	case GEU: return \"%*beq%?\\t%.,%.,%3\";
-	case LTU: return \"%*j\\t%3\";
-	default:
-	  break;
-	}
-
-      return \"%*b%N0z%?\\t%z1,%3\";
-    }
-}"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator:SI 0 "equality_op"
-					 [(match_operand:SI 1 "register_operand" "d,t")
-					  (const_int 0)])
-	(match_operand 2 "pc_or_label_operand" "")
-	(match_operand 3 "pc_or_label_operand" "")))]
-  "TARGET_MIPS16"
-  "*
-{
-  if (operands[2] != pc_rtx)
-    {
-      if (which_alternative == 0)
-	return \"%*b%C0z\\t%1,%2\";
-      else
-	return \"%*bt%C0z\\t%2\";
-    }
-  else
-    {
-      if (which_alternative == 0)
-	return \"%*b%N0z\\t%1,%3\";
-      else
-	return \"%*bt%N0z\\t%3\";
-    }
-}"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-(define_insn "branch_zero_di"
-  [(set (pc)
-	(if_then_else (match_operator:DI 0 "cmp_op"
-					 [(match_operand:DI 1 "se_register_operand" "d")
-					  (const_int 0)])
-	(match_operand 2 "pc_or_label_operand" "")
-	(match_operand 3 "pc_or_label_operand" "")))]
-  "!TARGET_MIPS16"
-  "*
-{
-  mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
-  if (operands[2] != pc_rtx)
-    {				/* normal jump */
-      switch (GET_CODE (operands[0]))
-	{
-	case EQ:  return \"%*beq%?\\t%z1,%.,%2\";
-	case NE:  return \"%*bne%?\\t%z1,%.,%2\";
-	case GTU: return \"%*bne%?\\t%z1,%.,%2\";
-	case LEU: return \"%*beq%?\\t%z1,%.,%2\";
-	case GEU: return \"%*j\\t%2\";
-	case LTU: return \"%*bne%?\\t%.,%.,%2\";
-	default:
-	  break;
-	}
-
-      return \"%*b%C0z%?\\t%z1,%2\";
-    }
-  else
-    {				/* inverted jump */
-      switch (GET_CODE (operands[0]))
-	{
-	case EQ:  return \"%*bne%?\\t%z1,%.,%3\";
-	case NE:  return \"%*beq%?\\t%z1,%.,%3\";
-	case GTU: return \"%*beq%?\\t%z1,%.,%3\";
-	case LEU: return \"%*bne%?\\t%z1,%.,%3\";
-	case GEU: return \"%*beq%?\\t%.,%.,%3\";
-	case LTU: return \"%*j\\t%3\";
-	default:
-	  break;
-	}
-
-      return \"%*b%N0z%?\\t%z1,%3\";
-    }
-}"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator:DI 0 "equality_op"
-					 [(match_operand:DI 1 "se_register_operand" "d,t")
-					  (const_int 0)])
-	(match_operand 2 "pc_or_label_operand" "")
-	(match_operand 3 "pc_or_label_operand" "")))]
-  "TARGET_MIPS16"
-  "*
-{
-  if (operands[2] != pc_rtx)
-    {
-      if (which_alternative == 0)
-	return \"%*b%C0z\\t%1,%2\";
-      else
-	return \"%*bt%C0z\\t%2\";
-    }
-  else
-    {
-      if (which_alternative == 0)
-	return \"%*b%N0z\\t%1,%3\";
-      else
-	return \"%*bt%N0z\\t%3\";
-    }
-}"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-
-(define_insn "branch_equality"
-  [(set (pc)
-	(if_then_else (match_operator:SI 0 "equality_op"
-					 [(match_operand:SI 1 "register_operand" "d")
-					  (match_operand:SI 2 "register_operand" "d")])
-	(match_operand 3 "pc_or_label_operand" "")
-	(match_operand 4 "pc_or_label_operand" "")))]
-  "!TARGET_MIPS16"
-  "*
-{
-  mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
-  return (operands[3] != pc_rtx)
-	? \"%*b%C0%?\\t%z1,%z2,%3\"
-	: \"%*b%N0%?\\t%z1,%z2,%4\";
-}"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-
-(define_insn "branch_equality_di"
-  [(set (pc)
-	(if_then_else (match_operator:DI 0 "equality_op"
-					 [(match_operand:DI 1 "se_register_operand" "d")
-					  (match_operand:DI 2 "se_register_operand" "d")])
-	(match_operand 3 "pc_or_label_operand" "")
-	(match_operand 4 "pc_or_label_operand" "")))]
-  "!TARGET_MIPS16"
-  "*
-{
-  mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
-  return (operands[3] != pc_rtx)
-	? \"%*b%C0%?\\t%z1,%z2,%3\"
-	: \"%*b%N0%?\\t%z1,%z2,%4\";
-}"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq:CC (cc0)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, EQ);
-      DONE;
-    }
-}")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne:CC (cc0)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, NE);
-      DONE;
-    }
-}")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt:CC (cc0)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, GT);
-      DONE;
-    }
-}")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge:CC (cc0)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, GE);
-      DONE;
-    }
-}")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt:CC (cc0)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, LT);
-      DONE;
-    }
-}")
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le:CC (cc0)
-			     (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, LE);
-      DONE;
-    }
-}")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu:CC (cc0)
-			      (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, GTU);
-      DONE;
-    }
-}")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu:CC (cc0)
-			      (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, GEU);
-      DONE;
-    }
-}")
-
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu:CC (cc0)
-			      (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, LTU);
-      DONE;
-    }
-}")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu:CC (cc0)
-			      (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, LEU);
-      DONE;
-    }
-}")
-
-
-;;  ....................
-;;	SETTING A REGISTER FROM A COMPARISON
-;;  ....................
-
-(define_expand "seq"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(eq:SI (match_dup 1)
-	       (match_dup 2)))]
-  ""
-  "
-{
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
-    FAIL;
-
-  /* set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    operands[2] = force_reg (SImode, operands[2]);
-
-  /* fall through and generate default code */
-}")
-
-
-(define_insn "seq_si_zero"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(eq:SI (match_operand:SI 1 "register_operand" "d")
-	       (const_int 0)))]
-  "!TARGET_MIPS16"
-  "sltu\\t%0,%1,1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=t")
-	(eq:SI (match_operand:SI 1 "register_operand" "d")
-	       (const_int 0)))]
-  "TARGET_MIPS16"
-  "sltu\\t%1,1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn "seq_di_zero"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(eq:DI (match_operand:DI 1 "se_register_operand" "d")
-	       (const_int 0)))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "sltu\\t%0,%1,1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=t")
-	(eq:DI (match_operand:DI 1 "se_register_operand" "d")
-	       (const_int 0)))]
-  "TARGET_64BIT && TARGET_MIPS16"
-  "sltu\\t%1,1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn "seq_si"
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(eq:SI (match_operand:SI 1 "register_operand" "%d,d")
-	       (match_operand:SI 2 "uns_arith_operand" "d,K")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "@
-   xor\\t%0,%1,%2\;sltu\\t%0,%0,1
-   xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(eq:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "uns_arith_operand" "")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
-    && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
-  [(set (match_dup 0)
-	(xor:SI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(ltu:SI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-(define_insn "seq_di"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(eq:DI (match_operand:DI 1 "se_register_operand" "%d,d")
-	       (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "@
-   xor\\t%0,%1,%2\;sltu\\t%0,%0,1
-   xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(eq:DI (match_operand:DI 1 "se_register_operand" "")
-	       (match_operand:DI 2 "se_uns_arith_operand" "")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
-    && !TARGET_MIPS16
-    && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
-  [(set (match_dup 0)
-	(xor:DI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(ltu:DI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-;; On the mips16 the default code is better than using sltu.
-
-(define_expand "sne"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ne:SI (match_dup 1)
-	       (match_dup 2)))]
-  "!TARGET_MIPS16"
-  "
-{
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
-    FAIL;
-
-  /* set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
-    {
-      gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    operands[2] = force_reg (SImode, operands[2]);
-
-  /* fall through and generate default code */
-}")
-
-(define_insn "sne_si_zero"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ne:SI (match_operand:SI 1 "register_operand" "d")
-	       (const_int 0)))]
-  "!TARGET_MIPS16"
-  "sltu\\t%0,%.,%1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn "sne_di_zero"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ne:DI (match_operand:DI 1 "se_register_operand" "d")
-	       (const_int 0)))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "sltu\\t%0,%.,%1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn "sne_si"
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(ne:SI (match_operand:SI 1 "register_operand" "%d,d")
-	       (match_operand:SI 2 "uns_arith_operand" "d,K")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "@
-    xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
-    xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ne:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "uns_arith_operand" "")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
-    && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
-  [(set (match_dup 0)
-	(xor:SI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(gtu:SI (match_dup 0)
-		(const_int 0)))]
-  "")
-
-(define_insn "sne_di"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(ne:DI (match_operand:DI 1 "se_register_operand" "%d,d")
-	       (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "@
-    xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
-    xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ne:DI (match_operand:DI 1 "se_register_operand" "")
-	       (match_operand:DI 2 "se_uns_arith_operand" "")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
-    && !TARGET_MIPS16
-    && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
-  [(set (match_dup 0)
-	(xor:DI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(gtu:DI (match_dup 0)
-		(const_int 0)))]
-  "")
-
-(define_expand "sgt"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(gt:SI (match_dup 1)
-	       (match_dup 2)))]
-  ""
-  "
-{
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
-    FAIL;
-
-  /* set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
-    operands[2] = force_reg (SImode, operands[2]);
-
-  /* fall through and generate default code */
-}")
-
-(define_insn "sgt_si"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(gt:SI (match_operand:SI 1 "register_operand" "d")
-	       (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
-  "!TARGET_MIPS16"
-  "slt\\t%0,%z2,%1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=t")
-	(gt:SI (match_operand:SI 1 "register_operand" "d")
-	       (match_operand:SI 2 "register_operand" "d")))]
-  "TARGET_MIPS16"
-  "slt\\t%2,%1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn "sgt_di"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(gt:DI (match_operand:DI 1 "se_register_operand" "d")
-	       (match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "slt\\t%0,%z2,%1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(gt:DI (match_operand:DI 1 "se_register_operand" "d")
-	       (match_operand:DI 2 "se_register_operand" "d")))]
-  "TARGET_64BIT && TARGET_MIPS16"
-  "slt\\t%2,%1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_expand "sge"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ge:SI (match_dup 1)
-	       (match_dup 2)))]
-  ""
-  "
-{
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
-    FAIL;
-
-  /* set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  /* fall through and generate default code */
-}")
-
-(define_insn "sge_si"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ge:SI (match_operand:SI 1 "register_operand" "d")
-	       (match_operand:SI 2 "arith_operand" "dI")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ge:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "arith_operand" "")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
-  [(set (match_dup 0)
-	(lt:SI (match_dup 1)
-	       (match_dup 2)))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-(define_insn "sge_di"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ge:DI (match_operand:DI 1 "se_register_operand" "d")
-	       (match_operand:DI 2 "se_arith_operand" "dI")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ge:DI (match_operand:DI 1 "se_register_operand" "")
-	       (match_operand:DI 2 "se_arith_operand" "")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
-   && !TARGET_MIPS16"
-  [(set (match_dup 0)
-	(lt:DI (match_dup 1)
-	       (match_dup 2)))
-   (set (match_dup 0)
-	(xor:DI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-(define_expand "slt"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(lt:SI (match_dup 1)
-	       (match_dup 2)))]
-  ""
-  "
-{
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
-    FAIL;
-
-  /* set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  /* fall through and generate default code */
-}")
-
-(define_insn "slt_si"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(lt:SI (match_operand:SI 1 "register_operand" "d")
-	       (match_operand:SI 2 "arith_operand" "dI")))]
-  "!TARGET_MIPS16"
-  "slt\\t%0,%1,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=t,t")
-	(lt:SI (match_operand:SI 1 "register_operand" "d,d")
-	       (match_operand:SI 2 "arith_operand" "d,I")))]
-  "TARGET_MIPS16"
-  "slt\\t%1,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
-			       (const_int 1)
-			       (const_int 2))])])
-
-(define_insn "slt_di"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(lt:DI (match_operand:DI 1 "se_register_operand" "d")
-	       (match_operand:DI 2 "se_arith_operand" "dI")))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "slt\\t%0,%1,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=t,t")
-	(lt:DI (match_operand:DI 1 "se_register_operand" "d,d")
-	       (match_operand:DI 2 "se_arith_operand" "d,I")))]
-  "TARGET_64BIT && TARGET_MIPS16"
-  "slt\\t%1,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
-			       (const_int 1)
-			       (const_int 2))])])
-
-(define_expand "sle"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(le:SI (match_dup 1)
-	       (match_dup 2)))]
-  ""
-  "
-{
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
-    FAIL;
-
-  /* set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
-    operands[2] = force_reg (SImode, operands[2]);
-
-  /* fall through and generate default code */
-}")
-
-(define_insn "sle_si_const"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(le:SI (match_operand:SI 1 "register_operand" "d")
-	       (match_operand:SI 2 "small_int" "I")))]
-  "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"slt\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=t")
-	(le:SI (match_operand:SI 1 "register_operand" "d")
-	       (match_operand:SI 2 "small_int" "I")))]
-  "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"slt\\t%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
-				      (const_int 1)
-				      (const_int 2)))])
-
-(define_insn "sle_di_const"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(le:DI (match_operand:DI 1 "se_register_operand" "d")
-	       (match_operand:DI 2 "small_int" "I")))]
-  "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"slt\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=t")
-	(le:DI (match_operand:DI 1 "se_register_operand" "d")
-	       (match_operand:DI 2 "small_int" "I")))]
-  "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"slt\\t%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
-				      (const_int 1)
-				      (const_int 2)))])
-
-(define_insn "sle_si_reg"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(le:SI (match_operand:SI 1 "register_operand" "d")
-	       (match_operand:SI 2 "register_operand" "d")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(le:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "register_operand" "")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
-  [(set (match_dup 0)
-	(lt:SI (match_dup 2)
-	       (match_dup 1)))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-(define_insn "sle_di_reg"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(le:DI (match_operand:DI 1 "se_register_operand" "d")
-	       (match_operand:DI 2 "se_register_operand" "d")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(le:DI (match_operand:DI 1 "se_register_operand" "")
-	       (match_operand:DI 2 "se_register_operand" "")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
-   && !TARGET_MIPS16"
-  [(set (match_dup 0)
-	(lt:DI (match_dup 2)
-	       (match_dup 1)))
-   (set (match_dup 0)
-	(xor:DI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-(define_expand "sgtu"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(gtu:SI (match_dup 1)
-		(match_dup 2)))]
-  ""
-  "
-{
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
-    FAIL;
-
-  /* set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
-    operands[2] = force_reg (SImode, operands[2]);
-
-  /* fall through and generate default code */
-}")
-
-(define_insn "sgtu_si"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(gtu:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "reg_or_0_operand" "dJ")))]
-  ""
-  "sltu\\t%0,%z2,%1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=t")
-	(gtu:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "register_operand" "d")))]
-  ""
-  "sltu\\t%2,%1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn "sgtu_di"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(gtu:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
-  "TARGET_64BIT"
-  "sltu\\t%0,%z2,%1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=t")
-	(gtu:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_register_operand" "d")))]
-  "TARGET_64BIT"
-  "sltu\\t%2,%1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_expand "sgeu"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-        (geu:SI (match_dup 1)
-                (match_dup 2)))]
-  ""
-  "
-{
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
-    FAIL;
-
-  /* set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  /* fall through and generate default code */
-}")
-
-(define_insn "sgeu_si"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(geu:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "arith_operand" "dI")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(geu:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "arith_operand" "")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
-  [(set (match_dup 0)
-	(ltu:SI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-(define_insn "sgeu_di"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(geu:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_arith_operand" "dI")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(geu:DI (match_operand:DI 1 "se_register_operand" "")
-		(match_operand:DI 2 "se_arith_operand" "")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
-   && !TARGET_MIPS16"
-  [(set (match_dup 0)
-	(ltu:DI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(xor:DI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-(define_expand "sltu"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ltu:SI (match_dup 1)
-		(match_dup 2)))]
-  ""
-  "
-{
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
-    FAIL;
-
-  /* set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  /* fall through and generate default code */
-}")
-
-(define_insn "sltu_si"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(ltu:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "arith_operand" "dI")))]
-  "!TARGET_MIPS16"
-  "sltu\\t%0,%1,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=t,t")
-	(ltu:SI (match_operand:SI 1 "register_operand" "d,d")
-		(match_operand:SI 2 "arith_operand" "d,I")))]
-  "TARGET_MIPS16"
-  "sltu\\t%1,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
-			       (const_int 1)
-			       (const_int 2))])])
-
-(define_insn "sltu_di"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(ltu:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_arith_operand" "dI")))]
-  "TARGET_64BIT && !TARGET_MIPS16"
-  "sltu\\t%0,%1,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=t,t")
-	(ltu:DI (match_operand:DI 1 "se_register_operand" "d,d")
-		(match_operand:DI 2 "se_arith_operand" "d,I")))]
-  "TARGET_64BIT && TARGET_MIPS16"
-  "sltu\\t%1,%2"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr_alternative "length"
-		[(const_int 1)
-		 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
-			       (const_int 1)
-			       (const_int 2))])])
-
-(define_expand "sleu"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(leu:SI (match_dup 1)
-		(match_dup 2)))]
-  ""
-  "
-{
-  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
-    FAIL;
-
-  /* set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
-    operands[2] = force_reg (SImode, operands[2]);
-
-  /* fall through and generate default code */
-}")
-
-(define_insn "sleu_si_const"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(leu:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "small_int" "I")))]
-  "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"sltu\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=t")
-	(leu:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "small_int" "I")))]
-  "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"sltu\\t%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
-				      (const_int 1)
-				      (const_int 2)))])
-
-(define_insn "sleu_di_const"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(leu:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "small_int" "I")))]
-  "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"sltu\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"1")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=t")
-	(leu:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "small_int" "I")))]
-  "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"sltu\\t%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
-				      (const_int 1)
-				      (const_int 2)))])
-
-(define_insn "sleu_si_reg"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(leu:SI (match_operand:SI 1 "register_operand" "d")
-		(match_operand:SI 2 "register_operand" "d")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(leu:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "register_operand" "")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
-  [(set (match_dup 0)
-	(ltu:SI (match_dup 2)
-		(match_dup 1)))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-(define_insn "sleu_di_reg"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(leu:DI (match_operand:DI 1 "se_register_operand" "d")
-		(match_operand:DI 2 "se_register_operand" "d")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(leu:DI (match_operand:DI 1 "se_register_operand" "")
-		(match_operand:DI 2 "se_register_operand" "")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
-   && !TARGET_MIPS16"
-  [(set (match_dup 0)
-	(ltu:DI (match_dup 2)
-		(match_dup 1)))
-   (set (match_dup 0)
-	(xor:DI (match_dup 0)
-		(const_int 1)))]
-  "")
-
-
-;;  ....................
-;;	FLOATING POINT COMPARISONS
-;;  ....................
-
-(define_insn "seq_df"
-  [(set (match_operand:CC 0 "register_operand" "=z")
-	(eq:CC (match_operand:DF 1 "register_operand" "f")
-	       (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "*
-{
-  return mips_fill_delay_slot (\"c.eq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type"	"fcmp")
-  (set_attr "mode"	"FPSW")
-  (set_attr "length"	"1")])
-
-(define_insn "slt_df"
-  [(set (match_operand:CC 0 "register_operand" "=z")
-	(lt:CC (match_operand:DF 1 "register_operand" "f")
-	       (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "*
-{
-  return mips_fill_delay_slot (\"c.lt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type"	"fcmp")
-  (set_attr "mode"	"FPSW")
-  (set_attr "length"	"1")])
-
-(define_insn "sle_df"
-  [(set (match_operand:CC 0 "register_operand" "=z")
-	(le:CC (match_operand:DF 1 "register_operand" "f")
-	       (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "*
-{
-  return mips_fill_delay_slot (\"c.le.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type"	"fcmp")
-  (set_attr "mode"	"FPSW")
-  (set_attr "length"	"1")])
-
-(define_insn "sgt_df"
-  [(set (match_operand:CC 0 "register_operand" "=z")
-	(gt:CC (match_operand:DF 1 "register_operand" "f")
-	       (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "*
-{
-  return mips_fill_delay_slot (\"c.lt.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type"	"fcmp")
-  (set_attr "mode"	"FPSW")
-  (set_attr "length"	"1")])
-
-(define_insn "sge_df"
-  [(set (match_operand:CC 0 "register_operand" "=z")
-	(ge:CC (match_operand:DF 1 "register_operand" "f")
-	       (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "*
-{
-  return mips_fill_delay_slot (\"c.le.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type"	"fcmp")
-  (set_attr "mode"	"FPSW")
-  (set_attr "length"	"1")])
-
-(define_insn "seq_sf"
-  [(set (match_operand:CC 0 "register_operand" "=z")
-	(eq:CC (match_operand:SF 1 "register_operand" "f")
-	       (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  return mips_fill_delay_slot (\"c.eq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type"	"fcmp")
-  (set_attr "mode"	"FPSW")
-  (set_attr "length"	"1")])
-
-(define_insn "slt_sf"
-  [(set (match_operand:CC 0 "register_operand" "=z")
-	(lt:CC (match_operand:SF 1 "register_operand" "f")
-	       (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  return mips_fill_delay_slot (\"c.lt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type"	"fcmp")
-  (set_attr "mode"	"FPSW")
-  (set_attr "length"	"1")])
-
-(define_insn "sle_sf"
-  [(set (match_operand:CC 0 "register_operand" "=z")
-	(le:CC (match_operand:SF 1 "register_operand" "f")
-	       (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  return mips_fill_delay_slot (\"c.le.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type"	"fcmp")
-  (set_attr "mode"	"FPSW")
-  (set_attr "length"	"1")])
-
-(define_insn "sgt_sf"
-  [(set (match_operand:CC 0 "register_operand" "=z")
-	(gt:CC (match_operand:SF 1 "register_operand" "f")
-	       (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  return mips_fill_delay_slot (\"c.lt.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type"	"fcmp")
-  (set_attr "mode"	"FPSW")
-  (set_attr "length"	"1")])
-
-(define_insn "sge_sf"
-  [(set (match_operand:CC 0 "register_operand" "=z")
-	(ge:CC (match_operand:SF 1 "register_operand" "f")
-	       (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  return mips_fill_delay_slot (\"c.le.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
-}"
- [(set_attr "type"	"fcmp")
-  (set_attr "mode"	"FPSW")
-  (set_attr "length"	"1")])
-
-
-;;  ....................
-;;	UNCONDITIONAL BRANCHES
-;;  ....................
-
-;; Unconditional branches.
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  "!TARGET_MIPS16"
-  "*
-{
-  if (GET_CODE (operands[0]) == REG)
-    return \"%*j\\t%0\";
-  /* ??? I don't know why this is necessary.  This works around an
-     assembler problem that appears when a label is defined, then referenced
-     in a switch table, then used in a `j' instruction.  */
-  else if (mips_abi != ABI_32 && mips_abi != ABI_O64)
-    return \"%*b\\t%l0\";
-  else	
-    return \"%*j\\t%l0\";
-}"
-  [(set_attr "type"	"jump")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-;; We need a different insn for the mips16, because a mips16 branch
-;; does not have a delay slot.
-
-(define_insn ""
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  "TARGET_MIPS16 && GET_CODE (operands[0]) != REG"
-  "b\\t%l0"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-(define_expand "indirect_jump"
-  [(set (pc) (match_operand 0 "register_operand" "d"))]
-  ""
-  "
-{
-  rtx dest;
-
-  if (operands[0])		/* eliminate unused code warnings */
-    {
-      dest = operands[0];
-      if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
-	operands[0] = copy_to_mode_reg (Pmode, dest);
-
-      if (!(Pmode == DImode))
-	emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
-      else
-	emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
-
-      DONE;
-    }
-}")
-
-(define_insn "indirect_jump_internal1"
-  [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
-  "!(Pmode == DImode)"
-  "%*j\\t%0"
-  [(set_attr "type"	"jump")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn "indirect_jump_internal2"
-  [(set (pc) (match_operand:DI 0 "se_register_operand" "d"))]
-  "Pmode == DImode"
-  "%*j\\t%0"
-  [(set_attr "type"	"jump")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_expand "tablejump"
-  [(set (pc)
-	(match_operand 0 "register_operand" "d"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "
-{
-  if (operands[0])		/* eliminate unused code warnings */
-    {
-      if (TARGET_MIPS16)
-	{
-	  if (GET_MODE (operands[0]) != HImode)
-	    abort ();
-	  if (!(Pmode == DImode))
-	    emit_jump_insn (gen_tablejump_mips161 (operands[0], operands[1]));
-	  else
-	    emit_jump_insn (gen_tablejump_mips162 (operands[0], operands[1]));
-	  DONE;
-	}
-
-      if (GET_MODE (operands[0]) != Pmode)
-	abort ();
-
-      if (! flag_pic)
-	{
-	  if (!(Pmode == DImode))
-	    emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
-	  else
-	    emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
-	}
-      else
-	{
-	  if (!(Pmode == DImode))
-	    emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
-	  else
-	    emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
-	}
-
-      DONE;
-    }
-}")
-
-(define_insn "tablejump_internal1"
-  [(set (pc)
-	(match_operand:SI 0 "register_operand" "d"))
-   (use (label_ref (match_operand 1 "" "")))]
-  "!(Pmode == DImode)"
-  "%*j\\t%0"
-  [(set_attr "type"	"jump")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn "tablejump_internal2"
-  [(set (pc)
-	(match_operand:DI 0 "se_register_operand" "d"))
-   (use (label_ref (match_operand 1 "" "")))]
-  "Pmode == DImode"
-  "%*j\\t%0"
-  [(set_attr "type"	"jump")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_expand "tablejump_internal3"
-  [(parallel [(set (pc)
-		   (plus:SI (match_operand:SI 0 "register_operand" "d")
-			    (label_ref:SI (match_operand:SI 1 "" ""))))
-	      (use (label_ref:SI (match_dup 1)))])]
-  ""
-  "")
-
-(define_expand "tablejump_mips161"
-  [(set (pc) (plus:SI (sign_extend:SI
-		       (match_operand:HI 0 "register_operand" "d"))
-		      (label_ref:SI (match_operand:SI 1 "" ""))))]
-  "TARGET_MIPS16 && !(Pmode == DImode)"
-  "
-{
-  if (operands[0])	/* eliminate unused code warnings.  */
-    {
-      rtx t1, t2, t3;
-
-      t1 = gen_reg_rtx (SImode);
-      t2 = gen_reg_rtx (SImode);
-      t3 = gen_reg_rtx (SImode);
-      emit_insn (gen_extendhisi2 (t1, operands[0]));
-      emit_move_insn (t2, gen_rtx (LABEL_REF, SImode, operands[1]));
-      emit_insn (gen_addsi3 (t3, t1, t2));
-      emit_insn (gen_tablejump_internal1 (t3, operands[1]));
-      DONE;
-    }
-}")
-
-(define_expand "tablejump_mips162"
-  [(set (pc) (plus:DI (sign_extend:DI
-		       (match_operand:HI 0 "register_operand" "d"))
-		      (label_ref:DI (match_operand:SI 1 "" ""))))]
-  "TARGET_MIPS16 && Pmode == DImode"
-  "
-{
-  if (operands[0])	/* eliminate unused code warnings.  */
-    {
-      rtx t1, t2, t3;
-
-      t1 = gen_reg_rtx (DImode);
-      t2 = gen_reg_rtx (DImode);
-      t3 = gen_reg_rtx (DImode);
-      emit_insn (gen_extendhidi2 (t1, operands[0]));
-      emit_move_insn (t2, gen_rtx (LABEL_REF, DImode, operands[1]));
-      emit_insn (gen_adddi3 (t3, t1, t2));
-      emit_insn (gen_tablejump_internal2 (t3, operands[1]));
-      DONE;
-    }
-}")
-
-;;; Make sure that this only matches the insn before ADDR_DIFF_VEC.  Otherwise
-;;; it is not valid.  ??? With the USE, the condition tests may not be required
-;;; any longer.
-
-;;; ??? The length depends on the ABI.  It is two for o32, and one for n32.
-;;; We just use the conservative number here.
-
-(define_insn ""
-  [(set (pc)
-	(plus:SI (match_operand:SI 0 "register_operand" "d")
-		 (label_ref:SI (match_operand:SI 1 "" ""))))
-   (use (label_ref:SI (match_dup 1)))]
-  "!(Pmode == DImode) && next_active_insn (insn) != 0
-   && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
-   && PREV_INSN (next_active_insn (insn)) == operands[1]"
-  "*
-{
-  /* .cpadd expands to add REG,REG,$gp when pic, and nothing when not pic.  */
-  if (mips_abi == ABI_32 || mips_abi == ABI_O64)
-    output_asm_insn (\".cpadd\\t%0\", operands);
-  return \"%*j\\t%0\";
-}"
-  [(set_attr "type"	"jump")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-(define_expand "tablejump_internal4"
-  [(parallel [(set (pc)
-		   (plus:DI (match_operand:DI 0 "se_register_operand" "d")
-			    (label_ref:DI (match_operand:SI 1 "" ""))))
-	      (use (label_ref:DI (match_dup 1)))])]
-  ""
-  "")
-
-;;; Make sure that this only matches the insn before ADDR_DIFF_VEC.  Otherwise
-;;; it is not valid.  ??? With the USE, the condition tests may not be required
-;;; any longer.
-
-(define_insn ""
-  [(set (pc)
-	(plus:DI (match_operand:DI 0 "se_register_operand" "d")
-		 (label_ref:DI (match_operand:SI 1 "" ""))))
-   (use (label_ref:DI (match_dup 1)))]
-  "Pmode == DImode && next_active_insn (insn) != 0
-   && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
-   && PREV_INSN (next_active_insn (insn)) == operands[1]"
-  "%*j\\t%0"
-  [(set_attr "type"	"jump")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-;; Implement a switch statement when generating embedded PIC code.
-;; Switches are implemented by `tablejump' when not using -membedded-pic.
-
-(define_expand "casesi"
-  [(set (match_dup 5)
-	(minus:SI (match_operand:SI 0 "register_operand" "d")
-		  (match_operand:SI 1 "arith_operand" "dI")))
-   (set (cc0)
-	(compare:CC (match_dup 5)
-		    (match_operand:SI 2 "arith_operand" "")))
-   (set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 4 "" ""))
-		      (pc)))
-   (parallel
-    [(set (pc)
-	  (mem:SI (plus:SI (mult:SI (match_dup 5)
-				    (const_int 4))
-			   (label_ref (match_operand 3 "" "")))))
-     (clobber (match_scratch:SI 6 ""))
-     (clobber (reg:SI 31))])]
-  "TARGET_EMBEDDED_PIC"
-  "
-{
-  /* We need slightly different code for eight byte table entries.  */
-  if (Pmode == DImode)
-    abort ();
-
-  if (operands[0])
-    {
-      rtx reg = gen_reg_rtx (SImode);
-
-      /* If the index is too large, go to the default label.  */
-      emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
-      emit_insn (gen_cmpsi (reg, operands[2]));
-      emit_insn (gen_bgtu (operands[4]));
-
-      /* Do the PIC jump.  */
-      emit_insn (gen_casesi_internal (reg, operands[3], gen_reg_rtx (SImode)));
-
-      DONE;
-    }
-}")
-
-;; An embedded PIC switch statement looks like this:
-;;	bal	$LS1
-;;	sll	$reg,$index,2
-;; $LS1:
-;;	addu	$reg,$reg,$31
-;;	lw	$reg,$L1-$LS1($reg)
-;;	addu	$reg,$reg,$31
-;;	j	$reg
-;; $L1:
-;;	.word	case1-$LS1
-;;	.word	case2-$LS1
-;;	...
-
-(define_insn "casesi_internal"
-  [(set (pc)
-	(mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d")
-				  (const_int 4))
-			 (label_ref (match_operand 1 "" "")))))
-   (clobber (match_operand:SI 2 "register_operand" "d"))
-   (clobber (reg:SI 31))]
-  "TARGET_EMBEDDED_PIC"
-  "*
-{
-  output_asm_insn (\"%(bal\\t%S1\;sll\\t%0,2\\n%S1:\", operands);
-  output_asm_insn (\"addu\\t%0,%0,$31%)\", operands);
-  output_asm_insn (\"lw\\t%0,%1-%S1(%0)\;addu\\t%0,%0,$31\", operands);
-  return \"j\\t%0\";
-}"
-  [(set_attr "type"	"jump")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"6")])
-
-;; For o32/n32/n64, we save the gp in the jmp_buf as well.  While it is
-;; possible to either pull it off the stack (in the o32 case) or recalculate
-;; it given t9 and our target label, it takes 3 or 4 insns to do so, and
-;; this is easy.
-
-(define_expand "builtin_setjmp_setup"
-  [(unspec [(match_operand 0 "register_operand" "r")] 20)]
-  "TARGET_ABICALLS"
-  "
-{
-  if (Pmode == DImode)
-    emit_insn (gen_builtin_setjmp_setup_64 (operands[0]));
-  else
-    emit_insn (gen_builtin_setjmp_setup_32 (operands[0]));
-  DONE;
-}")
-
-(define_expand "builtin_setjmp_setup_32"
-  [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
-		   (const_int 12)))
-      (reg:SI 28))]
-  "TARGET_ABICALLS && ! (Pmode == DImode)"
-  "")
-
-(define_expand "builtin_setjmp_setup_64"
-  [(set (mem:DI (plus:DI (match_operand:DI 0 "register_operand" "r")
-		   (const_int 24)))
-      (reg:DI 28))]
-  "TARGET_ABICALLS && Pmode == DImode"
-  "")
-
-;; For o32/n32/n64, we need to arrange for longjmp to put the 
-;; target address in t9 so that we can use it for loading $gp.
-
-(define_expand "builtin_longjmp"
-  [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
-  "TARGET_ABICALLS"
-  "
-{
-  /* The elements of the buffer are, in order:  */
-  int W = (Pmode == DImode ? 8 : 4);
-  rtx fp = gen_rtx_MEM (Pmode, operands[0]);
-  rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
-  rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
-  rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
-  rtx pv = gen_rtx_REG (Pmode, 25);
-  rtx gp = gen_rtx_REG (Pmode, 28);
-
-  /* This bit is the same as expand_builtin_longjmp.  */
-  emit_move_insn (hard_frame_pointer_rtx, fp);
-  emit_move_insn (pv, lab);
-  emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
-  emit_move_insn (gp, gpv);
-  emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
-  emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
-  emit_insn (gen_rtx_USE (VOIDmode, gp));
-  emit_indirect_jump (pv);
-  DONE;
-}")
-
-;;  ....................
-;;	Function prologue/epilogue
-;;  ....................
-
-(define_expand "prologue"
-  [(const_int 1)]
-  ""
-  "
-{
-  if (mips_isa >= 0)		/* avoid unused code warnings */
-    {
-      mips_expand_prologue ();
-      DONE;
-    }
-}")
-
-;; Block any insns from being moved before this point, since the
-;; profiling call to mcount can use various registers that aren't
-;; saved or used to pass arguments.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  ""
-  [(set_attr "type"	"unknown")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"0")])
-
-(define_expand "epilogue"
-  [(const_int 2)]
-  ""
-  "
-{
-  if (mips_isa >= 0)            /* avoid unused code warnings */
-    {
-      mips_expand_epilogue ();
-      DONE;
-    }
-}")
-
-;; Trivial return.  Make it look like a normal return insn as that
-;; allows jump optimizations to work better .
-(define_insn "return"
-  [(return)]
-  "mips_can_use_return_insn ()"
-  "%*j\\t$31"
-  [(set_attr "type"	"jump")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-;; Normal return.
-;; We match any mode for the return address, so that this will work with
-;; both 32 bit and 64 bit targets.
-(define_insn "return_internal"
-  [(use (match_operand 0 "register_operand" ""))
-   (return)]
-  ""
-  "*
-{
-  return \"%*j\\t%0\";
-}"
-  [(set_attr "type"	"jump")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-  
-;; When generating embedded PIC code we need to get the address of the
-;; current function.  This specialized instruction does just that.
-
-(define_insn "get_fnaddr"
-  [(set (match_operand 0 "register_operand" "=d")
-	(unspec [(match_operand 1 "" "")] 1))
-   (clobber (reg:SI 31))]
-  "TARGET_EMBEDDED_PIC
-   && GET_CODE (operands[1]) == SYMBOL_REF"
-  "%($LF%= = . + 8\;bal\\t$LF%=\;la\\t%0,%1-$LF%=%)\;addu\\t%0,%0,$31"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"4")])
-
-
-;;  ....................
-;;	FUNCTION CALLS
-;;  ....................
-
-;; calls.c now passes a third argument, make saber happy
-
-(define_expand "call"
-  [(parallel [(call (match_operand 0 "memory_operand" "m")
-		    (match_operand 1 "" "i"))
-	      (clobber (reg:SI 31))
-	      (use (match_operand 2 "" ""))		;; next_arg_reg
-	      (use (match_operand 3 "" ""))])]		;; struct_value_size_rtx
-  ""
-  "
-{
-  rtx addr;
-
-  if (operands[0])		/* eliminate unused code warnings */
-    {
-      addr = XEXP (operands[0], 0);
-      if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
-	  || ! call_insn_operand (addr, VOIDmode))
-	XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
-
-      /* In order to pass small structures by value in registers
-	 compatibly with the MIPS compiler, we need to shift the value
-	 into the high part of the register.  Function_arg has encoded
-	 a PARALLEL rtx, holding a vector of adjustments to be made
-	 as the next_arg_reg variable, so we split up the insns,
-	 and emit them separately.  */
-
-      if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
-	{
-	  rtvec adjust = XVEC (operands[2], 0);
-	  int num = GET_NUM_ELEM (adjust);
-	  int i;
-
-	  for (i = 0; i < num; i++)
-	    emit_insn (RTVEC_ELT (adjust, i));
-	}
-
-      if (TARGET_MIPS16
-	  && mips16_hard_float
-	  && operands[2] != 0
-	  && (int) GET_MODE (operands[2]) != 0)
-	{
-	  if (build_mips16_call_stub (NULL_RTX, operands[0], operands[1],
-				      (int) GET_MODE (operands[2])))
-	    DONE;
-	}
-
-      emit_call_insn (gen_call_internal0 (operands[0], operands[1],
-					  gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
-
-      DONE;
-    }
-}")
-
-(define_expand "call_internal0"
-  [(parallel [(call (match_operand 0 "" "")
-		    (match_operand 1 "" ""))
-	      (clobber (match_operand:SI 2 "" ""))])]
-  ""
-  "")
-
-;; We need to recognize reg:SI 31 specially for the mips16, because we
-;; don't have a constraint letter for it.
-
-(define_insn ""
-  [(call (mem (match_operand 0 "call_insn_operand" "ei"))
-	 (match_operand 1 "" "i"))
-   (clobber (match_operand:SI 2 "register_operand" "=y"))]
-  "TARGET_MIPS16 && !TARGET_ABICALLS && !TARGET_LONG_CALLS
-   && GET_CODE (operands[2]) == REG && REGNO (operands[2]) == 31"
-  "%*jal\\t%0"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-(define_insn "call_internal1"
-  [(call (mem (match_operand 0 "call_insn_operand" "ri"))
-	 (match_operand 1 "" "i"))
-   (clobber (match_operand:SI 2 "register_operand" "=d"))]
-  "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
-  "*
-{
-  register rtx target = operands[0];
-
-  if (GET_CODE (target) == SYMBOL_REF)
-    return \"%*jal\\t%0\";
-  else if (GET_CODE (target) == CONST_INT)
-    return \"%[li\\t%@,%0\\n\\t%*jal\\t%2,%@%]\";
-  else
-    return \"%*jal\\t%2,%0\";
-}"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn "call_internal2"
-  [(call (mem (match_operand 0 "call_insn_operand" "ri"))
-	 (match_operand 1 "" "i"))
-   (clobber (match_operand:SI 2 "register_operand" "=d"))]
-  "TARGET_ABICALLS && !TARGET_LONG_CALLS"
-  "*
-{
-  register rtx target = operands[0];
-
-  if (GET_CODE (target) == SYMBOL_REF)
-    {
-      if (GET_MODE (target) == SImode)
-	return \"la\\t%^,%0\\n\\tjal\\t%2,%^\";
-      else
-	return \"dla\\t%^,%0\\n\\tjal\\t%2,%^\";
-    }
-  else if (GET_CODE (target) == CONST_INT)
-    return \"li\\t%^,%0\\n\\tjal\\t%2,%^\";
-  else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
-    return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
-  else
-    return \"jal\\t%2,%0\";
-}"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-(define_insn "call_internal3a"
-  [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
-	 (match_operand 1 "" "i"))
-   (clobber (match_operand:SI 2 "register_operand" "=d"))]
-  "!(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
-  "%*jal\\t%2,%0"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn "call_internal3b"
-  [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
-	 (match_operand 1 "" "i"))
-   (clobber (match_operand:SI 2 "register_operand" "=d"))]
-  "Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
-  "%*jal\\t%2,%0"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn "call_internal4a"
-  [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
-	 (match_operand 1 "" "i"))
-   (clobber (match_operand:SI 2 "register_operand" "=d"))]
-  "!(Pmode == DImode) && TARGET_ABICALLS && TARGET_LONG_CALLS"
-  "*
-{
-  if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
-    return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
-  else
-    return \"jal\\t%2,%0\";
-}"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-(define_insn "call_internal4b"
-  [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
-	 (match_operand 1 "" "i"))
-   (clobber (match_operand:SI 2 "register_operand" "=d"))]
-  "Pmode == DImode && TARGET_ABICALLS && TARGET_LONG_CALLS"
-  "*
-{
-  if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
-    return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
-  else
-    return \"jal\\t%2,%0\";
-}"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-;; calls.c now passes a fourth argument, make saber happy
-
-(define_expand "call_value"
-  [(parallel [(set (match_operand 0 "register_operand" "=df")
-		   (call (match_operand 1 "memory_operand" "m")
-			 (match_operand 2 "" "i")))
-	      (clobber (reg:SI 31))
-	      (use (match_operand 3 "" ""))])]		;; next_arg_reg
-  ""
-  "
-{
-  rtx addr;
-
-  if (operands[0])		/* eliminate unused code warning */
-    {
-      addr = XEXP (operands[1], 0);
-      if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
-	  || ! call_insn_operand (addr, VOIDmode))
-	XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
-
-      /* In order to pass small structures by value in registers
-	 compatibly with the MIPS compiler, we need to shift the value
-	 into the high part of the register.  Function_arg has encoded
-	 a PARALLEL rtx, holding a vector of adjustments to be made
-	 as the next_arg_reg variable, so we split up the insns,
-	 and emit them separately.  */
-
-      if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
-	{
-	  rtvec adjust = XVEC (operands[3], 0);
-	  int num = GET_NUM_ELEM (adjust);
-	  int i;
-
-	  for (i = 0; i < num; i++)
-	    emit_insn (RTVEC_ELT (adjust, i));
-	}
-
-      if (TARGET_MIPS16
-	  && mips16_hard_float
-	  && ((operands[3] != 0
-	       && (int) GET_MODE (operands[3]) != 0)
-	      || GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT))
-	{
-	  if (build_mips16_call_stub (operands[0], operands[1], operands[2],
-				      (operands[3] == 0 ? 0
-				       : (int) GET_MODE (operands[3]))))
-	    DONE;
-	}
-
-      /* Handle Irix6 function calls that have multiple non-contiguous
-	 results.  */
-      if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
-	{
-	  emit_call_insn (gen_call_value_multiple_internal0
-			  (XEXP (XVECEXP (operands[0], 0, 0), 0),
-			   operands[1], operands[2],
-			   XEXP (XVECEXP (operands[0], 0, 1), 0),
-			   gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
-	  DONE;
-	}
-
-      /* We have a call returning a DImode structure in an FP reg.
-	 Strip off the now unnecessary PARALLEL.  */
-      if (GET_CODE (operands[0]) == PARALLEL)
-	operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
-
-      emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
-					        gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
-
-      DONE;
-    }
-}")
-
-(define_expand "call_value_internal0"
-  [(parallel [(set (match_operand 0 "" "")
-		   (call (match_operand 1 "" "")
-			 (match_operand 2 "" "")))
-	      (clobber (match_operand:SI 3 "" ""))])]
-  ""
-  "")
-
-;; Recognize $31 specially on the mips16, because we don't have a
-;; constraint letter for it.
-
-(define_insn ""
-  [(set (match_operand 0 "register_operand" "=d")
-        (call (mem (match_operand 1 "call_insn_operand" "ei"))
-              (match_operand 2 "" "i")))
-   (clobber (match_operand:SI 3 "register_operand" "=y"))]
-  "TARGET_MIPS16 && !TARGET_ABICALLS && !TARGET_LONG_CALLS
-   && GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31"
-  "%*jal\\t%1"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-(define_insn "call_value_internal1"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem (match_operand 1 "call_insn_operand" "ri"))
-              (match_operand 2 "" "i")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
-  "*
-{
-  register rtx target = operands[1];
-
-  if (GET_CODE (target) == SYMBOL_REF)
-    return \"%*jal\\t%1\";
-  else if (GET_CODE (target) == CONST_INT)
-    return \"%[li\\t%@,%1\\n\\t%*jal\\t%3,%@%]\";
-  else
-    return \"%*jal\\t%3,%1\";
-}"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn "call_value_internal2"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem (match_operand 1 "call_insn_operand" "ri"))
-              (match_operand 2 "" "i")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "TARGET_ABICALLS && !TARGET_LONG_CALLS"
-  "*
-{
-  register rtx target = operands[1];
-
-  if (GET_CODE (target) == SYMBOL_REF)
-    {
-      if (GET_MODE (target) == SImode)
-	return \"la\\t%^,%1\\n\\tjal\\t%3,%^\";
-      else
-	return \"dla\\t%^,%1\\n\\tjal\\t%3,%^\";
-    }
-  else if (GET_CODE (target) == CONST_INT)
-    return \"li\\t%^,%1\\n\\tjal\\t%3,%^\";
-  else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
-    return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
-  else
-    return \"jal\\t%3,%1\";
-}"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-(define_insn "call_value_internal3a"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
-	      (match_operand 2 "" "i")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_MIPS16 
-   && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
-  "%*jal\\t%3,%1"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn "call_value_internal3b"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
-	      (match_operand 2 "" "i")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!TARGET_MIPS16 
-   && Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
-  "%*jal\\t%3,%1"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn "call_value_internal3c"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:SI (match_operand:SI 1 "register_operand" "e"))
-	      (match_operand 2 "" "i")))
-   (clobber (match_operand:SI 3 "register_operand" "=y"))]
-  "TARGET_MIPS16 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS
-   && GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31"
-  "%*jal\\t%3,%1"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-(define_insn "call_value_internal4a"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
-	      (match_operand 2 "" "i")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "!(Pmode == DImode) && TARGET_ABICALLS && TARGET_LONG_CALLS"
-  "*
-{
-  if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
-    return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
-  else
-    return \"jal\\t%3,%1\";
-}"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-(define_insn "call_value_internal4b"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
-	      (match_operand 2 "" "i")))
-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-  "Pmode == DImode && TARGET_ABICALLS && TARGET_LONG_CALLS"
-  "*
-{
-  if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
-    return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
-  else
-    return \"jal\\t%3,%1\";
-}"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-(define_expand "call_value_multiple_internal0"
-  [(parallel [(set (match_operand 0 "" "")
-		   (call (match_operand 1 "" "")
-			 (match_operand 2 "" "")))
-	      (set (match_operand 3 "" "")
-		   (call (match_dup 1)
-			 (match_dup 2)))
-	      (clobber (match_operand:SI 4 "" ""))])]
-  ""
-  "")
-
-;; ??? May eventually need all 6 versions of the call patterns with multiple
-;; return values.
-
-(define_insn "call_value_multiple_internal2"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem (match_operand 1 "call_insn_operand" "ri"))
-              (match_operand 2 "" "i")))
-   (set (match_operand 3 "register_operand" "=df")
-        (call (mem (match_dup 1))
-              (match_dup 2)))
-   (clobber (match_operand:SI 4 "register_operand" "=d"))]
-  "TARGET_ABICALLS && !TARGET_LONG_CALLS"
-  "*
-{
-  register rtx target = operands[1];
-
-  if (GET_CODE (target) == SYMBOL_REF)
-    {
-      if (GET_MODE (target) == SImode)
-	return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
-      else
-	return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
-    }
-  else if (GET_CODE (target) == CONST_INT)
-    return \"li\\t%^,%1\\n\\tjal\\t%4,%^\";
-  else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
-    return \"move\\t%^,%1\\n\\tjal\\t%4,%^\";
-  else
-    return \"jal\\t%4,%1\";
-}"
-  [(set_attr "type"	"call")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  if (operands[0])		/* silence statement not reached warnings */
-    {
-      int i;
-
-      emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
-
-      for (i = 0; i < XVECLEN (operands[2], 0); i++)
-	{
-	  rtx set = XVECEXP (operands[2], 0, i);
-	  emit_move_insn (SET_DEST (set), SET_SRC (set));
-	}
-
-      emit_insn (gen_blockage ());
-      DONE;
-    }
-}")
-
-;;  ....................
-;;	MISC.
-;;  ....................
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "%(nop%)"
-  [(set_attr "type"	"nop")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"1")])
-
-;; The MIPS chip does not seem to require stack probes.
-;; (define_expand "probe"
-;;   [(set (match_dup 0)
-;; 	(match_dup 1))]
-;;   ""
-;;   "
-;; {
-;;   operands[0] = gen_reg_rtx (SImode);
-;;   operands[1] = gen_rtx (MEM, SImode, stack_pointer_rtx);
-;;   MEM_VOLATILE_P (operands[1]) = TRUE;
-;;   /* fall through and generate default code */
-;; }")
-
-;; MIPS4 Conditional move instructions.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(if_then_else:SI
-	 (match_operator 4 "equality_op"
-			 [(match_operand:SI 1 "register_operand" "d,d")
-			  (const_int 0)])
-	 (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
-	 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
-  "mips_isa >= 4 || 0" ;;  CYGNUS LOCAL law
-  "@
-    mov%B4\\t%0,%z2,%1
-    mov%b4\\t%0,%z3,%1"
-  [(set_attr "type" "move")
-   (set_attr "mode" "SI")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(if_then_else:SI
-	 (match_operator 4 "equality_op"
-			 [(match_operand:DI 1 "se_register_operand" "d,d")
-			  (const_int 0)])
-	 (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
-	 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
-  "mips_isa >= 4 || 0" ;;  CYGNUS LOCAL law
-  "@
-    mov%B4\\t%0,%z2,%1
-    mov%b4\\t%0,%z3,%1"
-  [(set_attr "type" "move")
-   (set_attr "mode" "SI")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-	(if_then_else:SI
-	 (match_operator 3 "equality_op" [(match_operand:CC 4
-							    "register_operand"
-							    "z,z")
-					  (const_int 0)])
-	 (match_operand:SI 1 "reg_or_0_operand" "dJ,0")
-	 (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "@
-    mov%T3\\t%0,%z1,%4
-    mov%t3\\t%0,%z2,%4"
-  [(set_attr "type" "move")
-   (set_attr "mode" "SI")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(if_then_else:DI
-	 (match_operator 4 "equality_op"
-			 [(match_operand:SI 1 "register_operand" "d,d")
-			  (const_int 0)])
-	 (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
-	 (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
-  "mips_isa >= 4 || 0" ;;  CYGNUS LOCAL law
-  "@
-    mov%B4\\t%0,%z2,%1
-    mov%b4\\t%0,%z3,%1"
-  [(set_attr "type" "move")
-   (set_attr "mode" "DI")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(if_then_else:DI
-	 (match_operator 4 "equality_op"
-			 [(match_operand:DI 1 "se_register_operand" "d,d")
-			  (const_int 0)])
-	 (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
-	 (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
-  "mips_isa >= 4 || 0" ;;  CYGNUS LOCAL law
-  "@
-    mov%B4\\t%0,%z2,%1
-    mov%b4\\t%0,%z3,%1"
-  [(set_attr "type" "move")
-   (set_attr "mode" "DI")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-	(if_then_else:DI
-	 (match_operator 3 "equality_op" [(match_operand:CC 4
-							    "register_operand"
-							    "z,z")
-					  (const_int 0)])
-	 (match_operand:DI 1 "se_reg_or_0_operand" "dJ,0")
-	 (match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "@
-    mov%T3\\t%0,%z1,%4
-    mov%t3\\t%0,%z2,%4"
-  [(set_attr "type" "move")
-   (set_attr "mode" "DI")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-	(if_then_else:SF
-	 (match_operator 4 "equality_op"
-			 [(match_operand:SI 1 "register_operand" "d,d")
-			  (const_int 0)])
-	 (match_operand:SF 2 "register_operand" "f,0")
-	 (match_operand:SF 3 "register_operand" "0,f")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "@
-    mov%B4.s\\t%0,%2,%1
-    mov%b4.s\\t%0,%3,%1"
-  [(set_attr "type" "move")
-   (set_attr "mode" "SF")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-	(if_then_else:SF
-	 (match_operator 3 "equality_op" [(match_operand:CC 4
-							    "register_operand"
-							    "z,z")
-					  (const_int 0)])
-	 (match_operand:SF 1 "register_operand" "f,0")
-	 (match_operand:SF 2 "register_operand" "0,f")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "@
-    mov%T3.s\\t%0,%1,%4
-    mov%t3.s\\t%0,%2,%4"
-  [(set_attr "type" "move")
-   (set_attr "mode" "SF")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(if_then_else:DF
-	 (match_operator 4 "equality_op"
-			 [(match_operand:SI 1 "register_operand" "d,d")
-			  (const_int 0)])
-	 (match_operand:DF 2 "register_operand" "f,0")
-	 (match_operand:DF 3 "register_operand" "0,f")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "@
-    mov%B4.d\\t%0,%2,%1
-    mov%b4.d\\t%0,%3,%1"
-  [(set_attr "type" "move")
-   (set_attr "mode" "DF")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(if_then_else:DF
-	 (match_operator 3 "equality_op" [(match_operand:CC 4
-							    "register_operand"
-							    "z,z")
-					  (const_int 0)])
-	 (match_operand:DF 1 "register_operand" "f,0")
-	 (match_operand:DF 2 "register_operand" "0,f")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "@
-    mov%T3.d\\t%0,%1,%4
-    mov%t3.d\\t%0,%2,%4"
-  [(set_attr "type" "move")
-   (set_attr "mode" "DF")])
-
-;; These are the main define_expand's used to make conditional moves.
-
-(define_expand "movsicc"
-  [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
-   (set (match_operand:SI 0 "register_operand" "")
-	(if_then_else:SI (match_dup 5)
-			 (match_operand:SI 2 "reg_or_0_operand" "")
-			 (match_operand:SI 3 "reg_or_0_operand" "")))]
-  "mips_isa >= 4 || 0" ;;  CYGNUS LOCAL law
-  "
-{
-
-  gen_conditional_move (operands);
-  DONE;
-}")
-
-(define_expand "movdicc"
-  [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
-   (set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI (match_dup 5)
-			 (match_operand:DI 2 "se_reg_or_0_operand" "")
-			 (match_operand:DI 3 "se_reg_or_0_operand" "")))]
-  "mips_isa >= 4 || 0" ;;  CYGNUS LOCAL law
-  "
-{
-
-  gen_conditional_move (operands);
-  DONE;
-}")
-
-(define_expand "movsfcc"
-  [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
-   (set (match_operand:SF 0 "register_operand" "")
-	(if_then_else:SF (match_dup 5)
-			 (match_operand:SF 2 "register_operand" "")
-			 (match_operand:SF 3 "register_operand" "")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT"
-  "
-{
-  gen_conditional_move (operands);
-  DONE;
-}")
-
-(define_expand "movdfcc"
-  [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
-   (set (match_operand:DF 0 "register_operand" "")
-	(if_then_else:DF (match_dup 5)
-			 (match_operand:DF 2 "register_operand" "")
-			 (match_operand:DF 3 "register_operand" "")))]
-  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "
-{
-  gen_conditional_move (operands);
-  DONE;
-}")
-
-;;  ....................
-;;	mips16 inline constant tables
-;;  ....................
-
-(define_insn "consttable_qi"
-  [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "=g")] 10)]
-  "TARGET_MIPS16"
-  "*
-{
-  assemble_integer (operands[0], 1, 1);
-  return \"\";
-}"
-  [(set_attr "type"	"unknown")
-   (set_attr "mode"	"QI")
-   (set_attr "length"	"2")])
-
-(define_insn "consttable_hi"
-  [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "=g")] 11)]
-  "TARGET_MIPS16"
-  "*
-{
-  assemble_integer (operands[0], 2, 1);
-  return \"\";
-}"
-  [(set_attr "type"	"unknown")
-   (set_attr "mode"	"HI")
-   (set_attr "length"	"2")])
-
-(define_insn "consttable_si"
-  [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "=g")] 12)]
-  "TARGET_MIPS16"
-  "*
-{
-  assemble_integer (operands[0], 4, 1);
-  return \"\";
-}"
-  [(set_attr "type"	"unknown")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2")])
-
-(define_insn "consttable_di"
-  [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "=g")] 13)]
-  "TARGET_MIPS16"
-  "*
-{
-  assemble_integer (operands[0], 8, 1);
-  return \"\";
-}"
-  [(set_attr "type"	"unknown")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4")])
-
-(define_insn "consttable_sf"
-  [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "=g")] 14)]
-  "TARGET_MIPS16"
-  "*
-{
-  union real_extract u;
-
-  if (GET_CODE (operands[0]) != CONST_DOUBLE)
-    abort ();
-  bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
-  assemble_real (u.d, SFmode);
-  return \"\";
-}"
-  [(set_attr "type"	"unknown")
-   (set_attr "mode"	"SF")
-   (set_attr "length"	"2")])
-
-(define_insn "consttable_df"
-  [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "=g")] 15)]
-  "TARGET_MIPS16"
-  "*
-{
-  union real_extract u;
-
-  if (GET_CODE (operands[0]) != CONST_DOUBLE)
-    abort ();
-  bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
-  assemble_real (u.d, DFmode);
-  return \"\";
-}"
-  [(set_attr "type"	"unknown")
-   (set_attr "mode"	"DF")
-   (set_attr "length"	"4")])
-
-(define_insn "align_2"
-  [(unspec_volatile [(const_int 0)] 16)]
-  "TARGET_MIPS16"
-  ".align 1"
-  [(set_attr "type"	"unknown")
-   (set_attr "mode"	"HI")
-   (set_attr "length"	"2")])
-
-(define_insn "align_4"
-  [(unspec_volatile [(const_int 0)] 17)]
-  "TARGET_MIPS16"
-  ".align 2"
-  [(set_attr "type"	"unknown")
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"2")])
-
-(define_insn "align_8"
-  [(unspec_volatile [(const_int 0)] 18)]
-  "TARGET_MIPS16"
-  ".align 3"
-  [(set_attr "type"	"unknown")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"3")])
-
-;;  ....................
-;;	mips16 peepholes
-;;  ....................
-
-;; On the mips16, reload will sometimes decide that a pseudo register
-;; should go into $24, and then later on have to reload that register.
-;; When that happens, we get a load of a general register followed by
-;; a move from the general register to $24 followed by a branch.
-;; These peepholes catch the common case, and fix it to just use the
-;; general register for the branch.
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=t")
-	(match_operand:SI 1 "register_operand" "d"))
-   (set (pc)
-	(if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
-							  (const_int 0)])
-		      (match_operand 3 "pc_or_label_operand" "")
-		      (match_operand 4 "pc_or_label_operand" "")))]
-  "TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG
-   && REGNO (operands[0]) == 24
-   && dead_or_set_p (insn, operands[0])
-   && GET_CODE (operands[1]) == REG
-   && M16_REG_P (REGNO (operands[1]))"
-  "*
-{
-  if (operands[3] != pc_rtx)
-    return \"%*b%C2z\\t%1,%3\";
-  else
-    return \"%*b%N2z\\t%1,%4\";
-}"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-(define_peephole
-  [(set (match_operand:DI 0 "register_operand" "=t")
-	(match_operand:DI 1 "register_operand" "d"))
-   (set (pc)
-	(if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
-							  (const_int 0)])
-		      (match_operand 3 "pc_or_label_operand" "")
-		      (match_operand 4 "pc_or_label_operand" "")))]
-  "TARGET_MIPS16 && TARGET_64BIT
-   && GET_CODE (operands[0]) == REG
-   && REGNO (operands[0]) == 24
-   && dead_or_set_p (insn, operands[0])
-   && GET_CODE (operands[1]) == REG
-   && M16_REG_P (REGNO (operands[1]))"
-  "*
-{
-  if (operands[3] != pc_rtx)
-    return \"%*b%C2z\\t%1,%3\";
-  else
-    return \"%*b%N2z\\t%1,%4\";
-}"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-;; We can also have the reverse reload: reload will spill $24 into
-;; another register, and then do a branch on that register when it
-;; could have just stuck with $24.
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(match_operand:SI 1 "register_operand" "t"))
-   (set (pc)
-	(if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
-							  (const_int 0)])
-		      (match_operand 3 "pc_or_label_operand" "")
-		      (match_operand 4 "pc_or_label_operand" "")))]
-  "TARGET_MIPS16
-   && GET_CODE (operands[1]) == REG
-   && REGNO (operands[1]) == 24
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && dead_or_set_p (insn, operands[0])"
-  "*
-{
-  if (operands[3] != pc_rtx)
-    return \"%*bt%C2z\\t%3\";
-  else
-    return \"%*bt%N2z\\t%4\";
-}"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
-
-(define_peephole
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(match_operand:DI 1 "register_operand" "t"))
-   (set (pc)
-	(if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
-							  (const_int 0)])
-		      (match_operand 3 "pc_or_label_operand" "")
-		      (match_operand 4 "pc_or_label_operand" "")))]
-  "TARGET_MIPS16 && TARGET_64BIT
-   && GET_CODE (operands[1]) == REG
-   && REGNO (operands[1]) == 24
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && dead_or_set_p (insn, operands[0])"
-  "*
-{
-  if (operands[3] != pc_rtx)
-    return \"%*bt%C2z\\t%3\";
-  else
-    return \"%*bt%N2z\\t%4\";
-}"
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"2")])
diff --git a/gcc/config/mips/mips16.S b/gcc/config/mips/mips16.S
deleted file mode 100755
index f21f10f..0000000
--- a/gcc/config/mips/mips16.S
+++ /dev/null
@@ -1,740 +0,0 @@
-/* mips16 floating point support code
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Support
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with other files,
-   some of which are compiled with GCC, to produce an executable,
-   this library does not by itself cause the resulting executable
-   to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-/* This file contains mips16 floating point support functions.  These
-   functions are called by mips16 code to handle floating point when
-   -msoft-float is not used.  They accept the arguments and return
-   values using the soft-float calling convention, but do the actual
-   operation using the hard floating point instructions.  */
-
-/* This file contains 32 bit assembly code.  */
-	.set nomips16
-
-/* Start a function. */
-
-#define STARTFN(NAME) .globl NAME; .ent NAME; NAME:
-
-/* Finish a function.  */
-
-#define ENDFN(NAME) .end NAME
-
-/* Single precision math.  */
-
-/* This macro defines a function which loads two single precision
-   values, performs an operation, and returns the single precision
-   result.  */
-
-#define SFOP(NAME, OPCODE)	\
-STARTFN (NAME);			\
-	.set	noreorder;	\
-	mtc1	$4,$f0;		\
-	mtc1	$5,$f2;		\
-	nop;			\
-	OPCODE	$f0,$f0,$f2;	\
-	mfc1	$2,$f0;		\
-	j	$31;		\
-	nop;			\
-	.set	reorder;	\
-	ENDFN (NAME)
-
-#ifdef L_m16addsf3
-SFOP(__mips16_addsf3, add.s)
-#endif
-#ifdef L_m16subsf3
-SFOP(__mips16_subsf3, sub.s)
-#endif
-#ifdef L_m16mulsf3
-SFOP(__mips16_mulsf3, mul.s)
-#endif
-#ifdef L_m16divsf3
-SFOP(__mips16_divsf3, div.s)
-#endif
-
-#define SFOP2(NAME, OPCODE)	\
-STARTFN (NAME);			\
-	.set	noreorder;	\
-	mtc1	$4,$f0;		\
-	nop;			\
-	OPCODE	$f0,$f0;	\
-	mfc1	$2,$f0;		\
-	j	$31;		\
-	nop;			\
-	.set	reorder;	\
-	ENDFN (NAME)
-	
-#ifdef L_m16negsf2
-SFOP2(__mips16_negsf2, neg.s)
-#endif
-#ifdef L_m16abssf2
-SFOP2(__mips16_abssf2, abs.s)
-#endif
-	
-/* Single precision comparisons.  */
-
-/* This macro defines a function which loads two single precision
-   values, performs a floating point comparison, and returns the
-   specified values according to whether the comparison is true or
-   false.  */
-
-#define SFCMP(NAME, OPCODE, TRUE, FALSE)	\
-STARTFN (NAME);					\
-	mtc1	$4,$f0;				\
-	mtc1	$5,$f2;				\
-	OPCODE	$f0,$f2;			\
-	li	$2,TRUE;			\
-	bc1t	1f;				\
-	li	$2,FALSE;			\
-1:;						\
-	j	$31;				\
-	ENDFN (NAME)
-
-/* This macro is like SFCMP, but it reverses the comparison.  */
-
-#define SFREVCMP(NAME, OPCODE, TRUE, FALSE)	\
-STARTFN (NAME);					\
-	mtc1	$4,$f0;				\
-	mtc1	$5,$f2;				\
-	OPCODE	$f2,$f0;			\
-	li	$2,TRUE;			\
-	bc1t	1f;				\
-	li	$2,FALSE;			\
-1:;						\
-	j	$31;				\
-	ENDFN (NAME)
-
-#ifdef L_m16eqsf2
-SFCMP(__mips16_eqsf2, c.eq.s, 0, 1)
-#endif
-#ifdef L_m16nesf2
-SFCMP(__mips16_nesf2, c.eq.s, 0, 1)
-#endif
-#ifdef L_m16gtsf2
-SFREVCMP(__mips16_gtsf2, c.lt.s, 1, 0)
-#endif
-#ifdef L_m16gesf2
-SFREVCMP(__mips16_gesf2, c.le.s, 0, -1)
-#endif
-#ifdef L_m16lesf2
-SFCMP(__mips16_lesf2, c.le.s, 0, 1)
-#endif
-#ifdef L_m16ltsf2
-SFCMP(__mips16_ltsf2, c.lt.s, -1, 0)
-#endif
-
-/* Single precision conversions.  */
-
-#ifdef L_m16fltsisf
-STARTFN (__mips16_floatsisf)
-	.set	noreorder
-	mtc1	$4,$f0
-	nop
-	cvt.s.w	$f0,$f0
-	mfc1	$2,$f0
-	j	$31
-	nop
-	.set	reorder
-	ENDFN (__mips16_floatsisf)
-#endif
-
-#ifdef L_m16fixsfsi
-STARTFN (__mips16_fixsfsi)
-	.set	noreorder
-	mtc1	$4,$f0
-	nop
-	trunc.w.s $f0,$f0,$4
-	mfc1	$2,$f0
-	j	$31
-	nop	
-	.set	reorder
-	ENDFN (__mips16_fixsfsi)
-#endif
-
-#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
-		
-/* The double precision operations.  We need to use different code
-   based on the preprocessor symbol __mips64, because the way in which
-   double precision values will change.  Without __mips64, the value
-   is passed in two 32 bit registers.  With __mips64, the value is
-   passed in a single 64 bit register.  */
-
-/* Load the first double precision operand.  */
-
-#if defined(__mips64)
-#define LDDBL1 dmtc1 $4,$f12
-#elif defined(__mipsfp64)
-#define LDDBL1 sw $4,0($29); sw $5,4($29); l.d $f12,0($29)
-#elif defined(__MIPSEB__)	
-#define LDDBL1 mtc1 $4,$f13; mtc1 $5,$f12
-#else	
-#define LDDBL1 mtc1 $4,$f12; mtc1 $5,$f13
-#endif
-
-/* Load the second double precision operand.  */
-
-#if defined(__mips64)
-/* XXX this should be $6 for Algo arg passing model */
-#define LDDBL2 dmtc1 $5,$f14
-#elif defined(__mipsfp64)
-#define LDDBL2 sw $6,8($29); sw $7,12($29); l.d $f14,8($29)
-#elif defined(__MIPSEB__)	
-#define LDDBL2 mtc1 $6,$f15; mtc1 $7,$f14
-#else	
-#define LDDBL2 mtc1 $6,$f14; mtc1 $7,$f15
-#endif
-	
-/* Move the double precision return value to the right place.  */
-
-#if defined(__mips64)
-#define RETDBL dmfc1 $2,$f0
-#elif defined(__mipsfp64)
-#define RETDBL s.d $f0,0($29); lw $2,0($29); lw $3,4($29)
-#elif defined(__MIPSEB__)	
-#define RETDBL mfc1 $2,$f1; mfc1 $3,$f0
-#else	
-#define RETDBL mfc1 $2,$f0; mfc1 $3,$f1
-#endif
-	
-/* Double precision math.  */
-
-/* This macro defines a function which loads two double precision
-   values, performs an operation, and returns the double precision
-   result.  */
-
-#define DFOP(NAME, OPCODE)	\
-STARTFN (NAME);			\
-	.set	noreorder;	\
-	LDDBL1;			\
-	LDDBL2;			\
-	nop;			\
-	OPCODE	$f0,$f12,$f14;	\
-	RETDBL;			\
-	j	$31;		\
-	nop;			\
-	.set	reorder;	\
-	ENDFN (NAME)
-
-#ifdef L_m16adddf3
-DFOP(__mips16_adddf3, add.d)
-#endif
-#ifdef L_m16subdf3
-DFOP(__mips16_subdf3, sub.d)
-#endif
-#ifdef L_m16muldf3
-DFOP(__mips16_muldf3, mul.d)
-#endif
-#ifdef L_m16divdf3
-DFOP(__mips16_divdf3, div.d)
-#endif
-
-#define DFOP2(NAME, OPCODE)	\
-STARTFN (NAME);			\
-	.set	noreorder;	\
-	LDDBL1;			\
-	nop;			\
-	OPCODE	$f0,$f12;	\
-	RETDBL;			\
-	j	$31;		\
-	nop;			\
-	.set	reorder;	\
-	ENDFN (NAME)
-	
-#ifdef L_m16negdf2
-DFOP2(__mips16_negdf2, neg.d)
-#endif
-#ifdef L_m16absdf2
-DFOP2(__mips16_absdf2, abs.d)
-#endif
-
-	
-/* Conversions between single and double precision.  */
-
-#ifdef L_m16extsfdf2
-STARTFN (__mips16_extendsfdf2)
-	.set	noreorder
-	mtc1	$4,$f12
-	nop
-	cvt.d.s	$f0,$f12
-	RETDBL
-	j	$31
-	nop
-	.set	reorder
-	ENDFN (__mips16_extendsfdf2)
-#endif
-
-#ifdef L_m16trdfsf2
-STARTFN (__mips16_truncdfsf2)
-	.set	noreorder
-	LDDBL1
-	nop
-	cvt.s.d	$f0,$f12
-	mfc1	$2,$f0
-	j	$31
-	nop
-	.set	reorder
-	ENDFN (__mips16_truncdfsf2)
-#endif
-
-/* Double precision comparisons.  */
-
-/* This macro defines a function which loads two double precision
-   values, performs a floating point comparison, and returns the
-   specified values according to whether the comparison is true or
-   false.  */
-
-#define DFCMP(NAME, OPCODE, TRUE, FALSE)	\
-STARTFN (NAME);					\
-	LDDBL1;					\
-	LDDBL2;					\
-	OPCODE	$f12,$f14;			\
-	li	$2,TRUE;			\
-	bc1t	1f;				\
-	li	$2,FALSE;			\
-1:;						\
-	j	$31;				\
-	ENDFN (NAME)
-
-/* This macro is like DFCMP, but it reverses the comparison.  */
-
-#define DFREVCMP(NAME, OPCODE, TRUE, FALSE)	\
-STARTFN (NAME);					\
-	LDDBL1;					\
-	LDDBL2;					\
-	OPCODE	$f14,$f12;			\
-	li	$2,TRUE;			\
-	bc1t	1f;				\
-	li	$2,FALSE;			\
-1:;						\
-	j	$31;				\
-	ENDFN (NAME)
-
-#ifdef L_m16eqdf2
-DFCMP(__mips16_eqdf2, c.eq.d, 0, 1)
-#endif
-#ifdef L_m16nedf2
-DFCMP(__mips16_nedf2, c.eq.d, 0, 1)
-#endif
-#ifdef L_m16gtdf2
-DFREVCMP(__mips16_gtdf2, c.lt.d, 1, 0)
-#endif
-#ifdef L_m16gedf2
-DFREVCMP(__mips16_gedf2, c.le.d, 0, -1)
-#endif
-#ifdef L_m16ledf2
-DFCMP(__mips16_ledf2, c.le.d, 0, 1)
-#endif
-#ifdef L_m16ltdf2
-DFCMP(__mips16_ltdf2, c.lt.d, -1, 0)
-#endif
-
-/* Double precision conversions.  */
-
-#ifdef L_m16fltsidf
-STARTFN (__mips16_floatsidf)
-	.set	noreorder
-	mtc1	$4,$f12
-	nop
-	cvt.d.w	$f0,$f12
-	RETDBL
-	j	$31
-	nop
-	.set	reorder
-	ENDFN (__mips16_floatsidf)
-#endif
-
-#ifdef L_m16fixdfsi
-STARTFN (__mips16_fixdfsi)
-	.set	noreorder
-	LDDBL1
-	nop
-	trunc.w.d $f0,$f12,$4
-	mfc1	$2,$f0
-	j	$31
-	nop
-	.set	reorder
-	ENDFN (__mips16_fixdfsi)
-#endif
-#endif /* !__mips_single_float */
-
-/* These functions are used to return floating point values from
-   mips16 functions which do not use -mentry.  In this case we can
-   put mtc1 in a jump delay slot, because we know that the next
-   instruction will not refer to a floating point register.  */
-
-#ifdef L_m16retsf
-STARTFN (__mips16_ret_sf)
-	.set	noreorder
-	j	$31
-	mtc1	$2,$f0
-	.set	reorder
-	ENDFN (__mips16_ret_sf)
-#endif
-
-#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
-#ifdef L_m16retdf
-STARTFN (__mips16_ret_df)
-	.set	noreorder
-#if defined(__mips64)
-	j	$31
-	dmtc1	$2,$f0
-#elif defined(__mipsfp64)
-	sw	$2,0($29)
-	sw	$3,4($29)
-	l.d	$f0,0($29) 
-#elif defined(__MIPSEB__)	
-	mtc1	$2,$f1
-	j	$31
-	mtc1	$3,$f0
-#else	
-	mtc1	$2,$f0
-	j	$31
-	mtc1	$3,$f1
-#endif
-	.set	reorder
-	ENDFN (__mips16_ret_df)
-#endif
-#endif /* !__mips_single_float */
-
-/* These functions are used by 16 bit code when calling via a function
-   pointer.  They must copy the floating point arguments from the gp
-   regs into the fp regs.  The function to call will be in $2.  The
-   exact set of floating point arguments to copy is encoded in the
-   function name; the final number is an fp_code, as described in
-   mips.h in the comment about CUMULATIVE_ARGS.  */
-
-#ifdef L_m16stub1
-/* (float) */
-STARTFN (__mips16_call_stub_1)
-	.set	noreorder
-	mtc1	$4,$f12
-	j	$2
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_1)
-#endif
-
-#ifdef L_m16stub5
-/* (float, float) */
-STARTFN (__mips16_call_stub_5)
-	.set	noreorder
-	mtc1	$4,$f12
-	mtc1	$5,$f14
-	j	$2
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_5)
-#endif
-
-#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
-
-#ifdef L_m16stub2
-/* (double) */
-STARTFN (__mips16_call_stub_2)
-	.set	noreorder
-	LDDBL1
-	j	$2
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_2)
-#endif
-
-#ifdef L_m16stub6
-/* (double, float) */
-STARTFN (__mips16_call_stub_6)
-	.set	noreorder
-	LDDBL1
-	mtc1	$6,$f14
-	j	$2
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_6)
-#endif
-
-#ifdef L_m16stub9
-/* (float, double) */
-STARTFN (__mips16_call_stub_9)
-	.set	noreorder
-	mtc1	$4,$f12
-	LDDBL2
-	j	$2
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_9)
-#endif
-
-#ifdef L_m16stub10
-/* (double, double) */
-STARTFN (__mips16_call_stub_10)
-	.set	noreorder
-	LDDBL1
-	LDDBL2
-	j	$2
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_10)
-#endif
-#endif /* !__mips_single_float */
-
-/* Now we have the same set of functions, except that this time the
-   function being called returns an SFmode value.  The calling
-   function will arrange to preserve $18, so these functions are free
-   to use it to hold the return address.
-
-   Note that we do not know whether the function we are calling is 16
-   bit or 32 bit.  However, it does not matter, because 16 bit
-   functions always return floating point values in both the gp and
-   the fp regs.  It would be possible to check whether the function
-   being called is 16 bits, in which case the copy is unnecessary;
-   however, it's faster to always do the copy.  */
-
-#ifdef L_m16stubsf0
-/* () */
-STARTFN (__mips16_call_stub_sf_0)
-	.set	noreorder
-	move	$18,$31
-	jal	$2
-	nop
-	mfc1	$2,$f0
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_sf_0)
-#endif
-
-#ifdef L_m16stubsf1
-/* (float) */
-STARTFN (__mips16_call_stub_sf_1)
-	.set	noreorder
-	mtc1	$4,$f12
-	move	$18,$31
-	jal	$2
-	nop
-	mfc1	$2,$f0
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_sf_1)
-#endif
-
-#ifdef L_m16stubsf5
-/* (float, float) */
-STARTFN (__mips16_call_stub_sf_5)
-	.set	noreorder
-	mtc1	$4,$f12
-	mtc1	$5,$f14
-	move	$18,$31
-	jal	$2
-	nop
-	mfc1	$2,$f0
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_sf_5)
-#endif
-
-#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
-#ifdef L_m16stubsf2
-/* (double) */
-STARTFN (__mips16_call_stub_sf_2)
-	.set	noreorder
-	LDDBL1
-	move	$18,$31
-	jal	$2
-	nop
-	mfc1	$2,$f0
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_sf_2)
-#endif
-
-#ifdef L_m16stubsf6
-/* (double, float) */
-STARTFN (__mips16_call_stub_sf_6)
-	.set	noreorder
-	LDDBL1
-	mtc1	$6,$f14
-	move	$18,$31
-	jal	$2
-	nop
-	mfc1	$2,$f0
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_sf_6)
-#endif
-
-#ifdef L_m16stubsf9
-/* (float, double) */
-STARTFN (__mips16_call_stub_sf_9)
-	.set	noreorder
-	mtc1	$4,$f12
-	LDDBL2
-	move	$18,$31
-	jal	$2
-	nop
-	mfc1	$2,$f0
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_sf_9)
-#endif
-
-#ifdef L_m16stubsf10
-/* (double, double) */
-STARTFN (__mips16_call_stub_sf_10)
-	.set	noreorder
-	LDDBL1
-	LDDBL2
-	move	$18,$31
-	jal	$2
-	nop
-	mfc1	$2,$f0
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_sf_10)
-#endif
-
-/* Now we have the same set of functions again, except that this time
-   the function being called returns an DFmode value.  */
-
-#ifdef L_m16stubdf0
-/* () */
-STARTFN (__mips16_call_stub_df_0)
-	.set	noreorder
-	move	$18,$31
-	jal	$2
-	nop
-	RETDBL
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_df_0)
-#endif
-
-#ifdef L_m16stubdf1
-/* (float) */
-STARTFN (__mips16_call_stub_df_1)
-	.set	noreorder
-	mtc1	$4,$f12
-	move	$18,$31
-	jal	$2
-	nop
-	RETDBL
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_df_1)
-#endif
-
-#ifdef L_m16stubdf2
-/* (double) */
-STARTFN (__mips16_call_stub_df_2)
-	.set	noreorder
-	LDDBL1
-	move	$18,$31
-	jal	$2
-	nop
-	RETDBL
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_df_2)
-#endif
-
-#ifdef L_m16stubdf5
-/* (float, float) */
-STARTFN (__mips16_call_stub_df_5)
-	.set	noreorder
-	mtc1	$4,$f12
-	mtc1	$5,$f14
-	move	$18,$31
-	jal	$2
-	nop
-	RETDBL
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_df_5)
-#endif
-
-#ifdef L_m16stubdf6
-/* (double, float) */
-STARTFN (__mips16_call_stub_df_6)
-	.set	noreorder
-	LDDBL1
-	mtc1	$6,$f14
-	move	$18,$31
-	jal	$2
-	nop
-	RETDBL
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_df_6)
-#endif
-
-#ifdef L_m16stubdf9
-/* (float, double) */
-STARTFN (__mips16_call_stub_df_9)
-	.set	noreorder
-	mtc1	$4,$f12
-	LDDBL2
-	move	$18,$31
-	jal	$2
-	nop
-	RETDBL
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_df_9)
-#endif
-
-#ifdef L_m16stubdf10
-/* (double, double) */
-STARTFN (__mips16_call_stub_df_10)
-	.set	noreorder
-	LDDBL1
-	LDDBL2
-	move	$18,$31
-	jal	$2
-	nop
-	RETDBL
-	j	$18
-	nop
-	.set	reorder
-	ENDFN (__mips16_call_stub_df_10)
-#endif
-#endif /* !__mips_single_float */
-
diff --git a/gcc/config/mips/ncd.h b/gcc/config/mips/ncd.h
deleted file mode 100755
index 5767d68..0000000
--- a/gcc/config/mips/ncd.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* CYGNUS LOCAL: entire file */
-
-/* Definitions of target machine for GNU compiler.
-   NCD R3000 or R4000 based X terminal.
-   Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#define CC1_SPEC "\
-%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
-%{g: -ggdb} \
-%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32} %{mips3:-mfp64 -mgp64} \
-%{G*} \
-%{pic-none:   -mno-half-pic} \
-%{pic-lib:    -mhalf-pic} \
-%{pic-extern: -mhalf-pic} \
-%{pic-calls:  -mhalf-pic} \
-%{save-temps: }"
-
-#define BLOCK_PROFILER_CODE
-#define DEFAULT_GDB_EXTENSIONS 1
-#define TARGET_DEFAULT MASK_GAS
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-#define MACHINE_TYPE "NCD R3000- or R4000-based X terminal"
-
-#include "mips/mips.h"
-
-#undef SDB_DEBUGGING_INFO
diff --git a/gcc/config/mips/netbsd.h b/gcc/config/mips/netbsd.h
deleted file mode 100755
index 3fce9fb..0000000
--- a/gcc/config/mips/netbsd.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/* Definitions for DECstation running BSD as target machine for GNU compiler.
-   Copyright (C) 1993, 1995, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define DECSTATION
-
-/* Look for the include files in the system-defined places.  */
-
-#ifndef CROSS_COMPILE
-#undef GPLUSPLUS_INCLUDE_DIR
-#define GPLUSPLUS_INCLUDE_DIR "/usr/include/g++"
-
-#undef GCC_INCLUDE_DIR
-#define GCC_INCLUDE_DIR "/usr/include"
-
-#undef INCLUDE_DEFAULTS
-#define INCLUDE_DEFAULTS			\
-  {						\
-    { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1 },	\
-    { GCC_INCLUDE_DIR, "GCC", 0, 0 },		\
-    { 0, 0, 0, 0 }				\
-  }
-
-/* Under NetBSD, the normal location of the various *crt*.o files is the
-   /usr/lib directory.  */
-
-#undef STANDARD_STARTFILE_PREFIX
-#define STANDARD_STARTFILE_PREFIX "/usr/lib/"
-#endif
-
-/* Provide a LINK_SPEC appropriate for NetBSD.  Here we provide support
-   for the special GCC options -static, -assert, and -nostdlib.  */
-
-#undef LINK_SPEC
-#define LINK_SPEC \
-  "%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-   %{!nostartfiles:%{!r*:%{!e*:-e __start}}} -dc -dp %{static:-Bstatic} %{assert*}"
-
-/* We have atexit(3).  */
-
-#define HAVE_ATEXIT
-
-/* Implicit library calls should use memcpy, not bcopy, etc.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Define mips-specific netbsd predefines... */
-#ifndef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D__ANSI_COMPAT \
--DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -D__NetBSD__ -Dmips \
--D__NO_LEADING_UNDERSCORES__ -D__GP_SUPPORT__ \
--Dunix -D_R3000 \
--Asystem(unix) -Asystem(NetBSD) -Amachine(mips)"
-#endif
-
-#ifndef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC "%{posix:-D_POSIX_SOURCE}"
-#endif
-
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
-#define STARTFILE_SPEC ""
-
-#ifndef MACHINE_TYPE
-#define MACHINE_TYPE "NetBSD/pmax"
-#endif
-
-#define TARGET_DEFAULT MASK_GAS
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#include "mips/mips.h"
-
-/*
- * Some imports from svr4.h in support of shared libraries.
- * Currently, we need the DECLARE_OBJECT_SIZE stuff.
- */
-
-/* Define the strings used for the special svr4 .type and .size directives.
-   These strings generally do not vary from one system running svr4 to
-   another, but if a given system (e.g. m88k running svr) needs to use
-   different pseudo-op names for these, they may be overridden in the
-   file which includes this one.  */
-
-#undef TYPE_ASM_OP
-#undef SIZE_ASM_OP
-#undef WEAK_ASM_OP
-#define TYPE_ASM_OP	".type"
-#define SIZE_ASM_OP	".size"
-#define WEAK_ASM_OP	".weak"
-
-/* The following macro defines the format used to output the second
-   operand of the .type assembler directive.  Different svr4 assemblers
-   expect various different forms for this operand.  The one given here
-   is just a default.  You may need to override it in your machine-
-   specific tm.h file (depending upon the particulars of your assembler).  */
-
-#undef TYPE_OPERAND_FMT
-#define TYPE_OPERAND_FMT	"@%s"
-
-/* Write the extra assembler code needed to declare a function's result.
-   Most svr4 assemblers don't require any special declaration of the
-   result value, but there are exceptions.  */
-
-#ifndef ASM_DECLARE_RESULT
-#define ASM_DECLARE_RESULT(FILE, RESULT)
-#endif
-
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare a function properly.
-   Some svr4 assemblers need to also have something extra said about the
-   function's return value.  We allow for that here.  */
-
-#undef ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "function");			\
-    putc ('\n', FILE);							\
-    ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));			\
-  } while (0)
-
-/* Write the extra assembler code needed to declare an object properly.  */
-
-#undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
-    putc ('\n', FILE);							\
-    size_directive_output = 0;						\
-    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-      {									\
-	size_directive_output = 1;					\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-	fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));	\
-      }									\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#undef ASM_FINISH_DECLARE_OBJECT
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
-	 assemble_name (FILE, name);					 \
-	 fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL))); \
-       }								 \
-   } while (0)
-
-/* This is how to declare the size of a function.  */
-
-#undef ASM_DECLARE_FUNCTION_SIZE
-#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)			\
-  do {									\
-    if (!flag_inhibit_size_directive)					\
-      {									\
-        char label[256];						\
-	static int labelno;						\
-	labelno++;							\
-	ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno);		\
-	ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno);		\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, (FNAME));					\
-        fprintf (FILE, ",");						\
-	assemble_name (FILE, label);					\
-        fprintf (FILE, "-");						\
-	assemble_name (FILE, (FNAME));					\
-	putc ('\n', FILE);						\
-      }									\
-  } while (0)
-
-/*
- A C statement to output something to the assembler file to switch to section
- NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
- NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
- define this macro in such cases.
-*/
-#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC)                        \
-do {                                                                         \
-  extern FILE *asm_out_text_file;                                            \
-  if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL)                           \
-    fprintf (asm_out_text_file, "\t.section %s,\"ax\",@progbits\n", (NAME)); \
-  else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC))                    \
-    fprintf (F, "\t.section %s,\"a\",@progbits\n", (NAME));                  \
-  else                                                                       \
-    fprintf (F, "\t.section %s,\"aw\",@progbits\n", (NAME));                 \
-} while (0)
-
-/* Since gas and gld are standard on NetBSD, we don't need these */
-#undef ASM_FINAL_SPEC
-#undef STARTFILE_SPEC
diff --git a/gcc/config/mips/news4.h b/gcc/config/mips/news4.h
deleted file mode 100755
index 502affa..0000000
--- a/gcc/config/mips/news4.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Sony RISC NEWS (mips)
-   Copyright (C) 1991, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MIPS_NEWS
-
-#define CPP_PREDEFINES "\
--Dr3000 -Dnews3700 -DLANGUAGE_C -DMIPSEB -DSYSTYPE_BSD \
--Dsony_news -Dsony -Dunix -Dmips -Dhost_mips \
--Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
-
-#define SYSTEM_INCLUDE_DIR "/usr/include2.0"
-
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-
-#define MACHINE_TYPE "RISC NEWS-OS"
-
-/* INITIALIZE_TRAMPOLINE calls this library function to flush
-   program and data caches.  */
-#define CACHE_FLUSH_FUNC "cacheflush"
-
diff --git a/gcc/config/mips/news5.h b/gcc/config/mips/news5.h
deleted file mode 100755
index a776064..0000000
--- a/gcc/config/mips/news5.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Definitions of target machine for GNU compiler. 
-   Sony RISC NEWS (mips) System V version.
-   Copyright (C) 1992 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MIPS_SYSV
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -Dsony -Dsonyrisc -DMIPSEB -DSYSTYPE_SYSV \
--Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)"
-
-#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
-
-#define LIB_SPEC "\
-%{ZBSD43: -L/usr/ucblib -lucb -lresolv -lsocket -lnsl} \
--nocount %{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s values-Xt.o%s"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:-nocount crt1.o%s -count}}"
-
-#define MACHINE_TYPE "Sony RISC NEWS (SVR4 mips)"
-
-#define NO_LIB_PROTOTYPE
-
-#define NO_DOLLAR_IN_LABEL
-
-#define NM_FLAGS "-Bp"
-
-/* Generate calls to memcpy, etc., not bcopy, etc.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Mips System V.4 doesn't have a getpagesize() function needed by the
-   trampoline code, so use the POSIX sysconf function to get it.
-   This is only done when compiling the trampoline code.  */
-
-#ifdef  L_trampoline
-#include <sys/param.h>
-#include <unistd.h>
-
-#ifdef _SC_PAGE_SIZE
-#define getpagesize()	sysconf(_SC_PAGE_SIZE)
-
-#else				/* older rev of OS */
-#define getpagesize()	(NBPC)
-#endif /* !_SC_PAGE_SIZE */
-#endif /*  L_trampoline */
-
diff --git a/gcc/config/mips/nws3250v4.h b/gcc/config/mips/nws3250v4.h
deleted file mode 100755
index 611effe..0000000
--- a/gcc/config/mips/nws3250v4.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Sony RISC NEWS (mips)
-   Copyright (C) 1991 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MIPS_NEWS
-
-#define CPP_PREDEFINES "\
--Dmips -Dhost_mips -Dsony -Dsonyrisc -Dunix \
--DLANGUAGE_C -DMIPSEB -DSYSTYPE_SYSV \
--Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)"
-
-#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
-
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s values-Xt.o%s"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}"
-
-#define MACHINE_TYPE "RISC NEWS-OS SVr4"
-
-#include "mips/mips.h"
diff --git a/gcc/config/mips/osfrose.h b/gcc/config/mips/osfrose.h
deleted file mode 100755
index ee76053..0000000
--- a/gcc/config/mips/osfrose.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   DECstation (OSF/1 reference port with OSF/rose) version.
-   Copyright (C) 1991, 1992, 1995, 1996, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define DECSTATION
-#define OSF_OS
-
-#define HALF_PIC_DEBUG	TARGET_DEBUG_B_MODE
-#define HALF_PIC_PREFIX	"$Lp."
-
-#include "halfpic.h"
-
-#define WORD_SWITCH_TAKES_ARG(STR)					\
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) || !strcmp (STR, "pic-names"))
-
-#define CPP_PREDEFINES "\
--DOSF -DOSF1 -Dbsd4_2 -DMIPSEL -Dhost_mips -Dmips -Dunix -DR3000 -DSYSTYPE_BSD \
--Asystem(unix) -Asystem(xpg4) -Acpu(mips) -Amachine(mips)"
-
-#define SUBTARGET_CPP_SIZE_SPEC "\
-%{mlong64:-D__PTRDIFF_TYPE__=long\\ int} \
-%{!mlong64:-D__PTRDIFF_TYPE__=int}"
-
-#define SUBTARGET_CPP_SPEC "\
-%{.S:	%{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}} \
-%{.s:	%{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}}"
-
-/* ??? This assumes that GNU as is always used with GNU ld, and MIPS as is
-   always used with MIPS ld.  */
-#define LINK_SPEC "\
-%{G*} %{EL} %{EB} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} \
-%{!mmips-as: \
- 	%{v*: -v} \
-	%{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \
-	%{nostdlib} %{noshrlib} %{glue}}"
-
-#define LIB_SPEC "-lc"
-
-/* Define this macro meaning that `gcc' should find the library
-   `libgcc.a' by hand, rather than passing the argument `-lgcc' to
-   tell the linker to do the search. */
-
-#define LINK_LIBGCC_SPECIAL 1
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-
-#define MACHINE_TYPE "DECstation with OSF/rose objects"
-
-#ifndef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX		"/usr/ccs/gcc/"
-#endif
-
-#ifndef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX	"/usr/ccs/lib/"
-#endif
-
-/* Turn on -mpic-extern by default.  */
-#define CC1_SPEC "\
-%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
-%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32} %{mips3:-mfp64 -mgp64} \
-%{G*} \
-%{pic-none:   -mno-half-pic} \
-%{pic-lib:    -mhalf-pic} \
-%{pic-extern: -mhalf-pic} \
-%{pic-calls:  -mhalf-pic} \
-%{pic-names*: -mhalf-pic} \
-%{!pic-*:     -mhalf-pic}"
-
-/* Specify size_t and wchar_t types.  */
-#define SIZE_TYPE	"long unsigned int"
-#define WCHAR_TYPE	"unsigned int"
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-#define MAX_WCHAR_TYPE_SIZE MAX_LONG_TYPE_SIZE
-
-/* OSF/1 uses gas, not the mips assembler.  */
-#define TARGET_DEFAULT MASK_GAS
-
-/* OSF/rose uses stabs, not ECOFF.  */
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* enable dwarf debugging for testing */
-#define DWARF_DEBUGGING_INFO
-/* This is needed by dwarfout.c.  */
-#define SET_ASM_OP	".set"
-
-/* Tell collect that the object format is OSF/rose.  */
-#define OBJECT_FORMAT_ROSE
-
-/* Tell collect where the appropriate binaries are.  */
-#define REAL_LD_FILE_NAME	"/usr/ccs/gcc/gld"
-#define REAL_NM_FILE_NAME	"/usr/ccs/bin/nm"
-#define REAL_STRIP_FILE_NAME	"/usr/ccs/bin/strip"
-
-/* Default to -G 0 unless doing ecoff work.  */
-#define MIPS_DEFAULT_GVALUE ((TARGET_MIPS_AS) ? 8 : 0)
-
-/* Use atexit for static constructors/destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
-/* Generate calls to memcpy, etc., not bcopy, etc.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* A C statement to output assembler commands which will identify
-   the object file as having been compiled with GNU CC (or another
-   GNU compiler).
-
-   If you don't define this macro, the string `gcc2_compiled.:' is
-   output.  This string is calculated to define a symbol which, on
-   BSD systems, will never be defined for any other reason.  GDB
-   checks for the presence of this symbol when reading the symbol
-   table of an executable.
-
-   On non-BSD systems, you must arrange communication with GDB in
-   some other fashion.  If GDB is not used on your system, you can
-   define this macro with an empty body.
-
-   On OSF/1, gcc2_compiled. confuses the kernel debugger, so don't
-   put it out.  */
-
-#define ASM_IDENTIFY_GCC(STREAM)
-
-/* Identify the front-end which produced this file.  To keep symbol
-   space down, and not confuse kdb, only do this if the language is
-   not C.  */
-
-#define ASM_IDENTIFY_LANGUAGE(STREAM)					\
-{									\
-  if (strcmp (lang_identify (), "c") != 0)				\
-    output_lang_identify (STREAM);					\
-}
diff --git a/gcc/config/mips/r3900.h b/gcc/config/mips/r3900.h
deleted file mode 100755
index 3d7cac5..0000000
--- a/gcc/config/mips/r3900.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Definitions of MIPS sub target machine for GNU compiler. 
-   Toshiba r3900.  You should include mips.h after this.
-
-   Copyright (C) 1989, 90-6, 1997 Free Software Foundation, Inc.
-   Contributed by Gavin Koch (gavin@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define SUBTARGET_CPP_SPEC "\
-%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}} \
-%{!msingle-float:-D__mips_soft_float} \
-%{mhard-float:%e-mhard-float not supported.} \
-%{msingle-float:%{msoft-float: \
-  %e-msingle-float and -msoft-float can not both be specified.}}"
-
-/* The following is needed because -mips3 and -mips4 set gp64 which in
-   combination with abi=eabi, causes long64 to be set. */
-#define SUBTARGET_CPP_SIZE_SPEC "\
-%{mips3:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
-%{mips4:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
-%{!mips3:%{!mips4:%{!m4650:\
-  -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}} "
-
-/* by default (if not mips-something-else) produce code for the r3900 */
-#define SUBTARGET_CC1_SPEC "\
-%{mhard-float:%e-mhard-float not supported.} \
-%{msingle-float:%{msoft-float: \
-  %e-msingle-float and -msoft-float can not both be specified.}}"
-
-#define TARGET_DEFAULT (MASK_SOFT_FLOAT | MASK_MIPS3900)
-#define MIPS_CPU_STRING_DEFAULT "R3900"
-#define MIPS_ISA_DEFAULT 1
-
-#define MULTILIB_DEFAULTS { "EB", "msoft-float" }
-
-/* We use the MIPS EABI by default.  */
-#define MIPS_ABI_DEFAULT ABI_EABI
-
-
-/* Debugging */
-
-#define DWARF2_DEBUGGING_INFO
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-/* For the 'preferred' cases ("gN" and "ggdbN") we need to tell the 
-   gnu assembler not to generate debugging information. */
-   
-#define SUBTARGET_ASM_DEBUGGING_SPEC "\
-%{!mmips-as: \
-  %{g:-g0} %{g0:-g0} %{g1:-g0} %{g2:-g0} %{g3:-g0} \
-  %{ggdb:-g0} %{ggdb0:-g0} %{ggdb1:-g0} %{ggdb2:-g0} %{ggdb3:-g0} \
-  %{gdwarf-2*:-g0}} \
-%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
-%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
-%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
-
-/* eof */
diff --git a/gcc/config/mips/rtems64.h b/gcc/config/mips/rtems64.h
deleted file mode 100755
index cd79970..0000000
--- a/gcc/config/mips/rtems64.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Definitions for rtems targeting a MIPS ORION using ecoff.
-   Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-   Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4000 -D_mips -D_MIPSEB -D_R4000 \
-   -Drtems -D__rtems__ -Asystem(rtems)"
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#ifndef TARGET_MEM_FUNCTIONS
-#define TARGET_MEM_FUNCTIONS
-#endif
-
-/* Undefine the following which were defined in elf64.h.  This will cause the rtems64
-   port to continue to use collect2 for constructors/destructors.  These may be removed
-   when .ctor/.dtor section support is desired. */
-
-#undef CTORS_SECTION_ASM_OP
-#undef DTORS_SECTION_ASM_OP
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_sdata, in_rdata
-
-#undef INVOKE__main
-#undef NAME__MAIN
-#undef SYMBOL__MAIN
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS                                         \
-  SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \
-  SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP)
-
-#undef ASM_OUTPUT_CONSTRUCTOR
-#undef ASM_OUTPUT_DESTRUCTOR
-
-#undef CTOR_LIST_BEGIN
-#undef CTOR_LIST_END
-#undef DTOR_LIST_BEGIN
-#undef DTOR_LIST_END
-
-#undef STARTFILE_SPEC
-#undef ENDFILE_SPEC
-
-/*  End of undefines to turn off .ctor/.dtor section support */
diff --git a/gcc/config/mips/sni-gas.h b/gcc/config/mips/sni-gas.h
deleted file mode 100755
index 5b36998..0000000
--- a/gcc/config/mips/sni-gas.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Enable debugging.  */
-#define DBX_DEBUGGING_INFO
-#define SDB_DEBUGGING_INFO
-#define MIPS_DEBUGGING_INFO
-
-#define DWARF_DEBUGGING_INFO
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF_DEBUG
-
-/* We need to use .esize and .etype instead of .size and .type to
-   avoid conflicting with ELF directives.  These are only recognized
-   by gas, anyhow, not the native assembler.  */
-#undef PUT_SDB_SIZE
-#define PUT_SDB_SIZE(a)                                       \
-do {                                                  \
-  extern FILE *asm_out_text_file;                     \
-  fprintf (asm_out_text_file, "\t.esize\t%d;", (a));  \
-} while (0)
-
-#undef PUT_SDB_TYPE
-#define PUT_SDB_TYPE(a)                                       \
-do {                                                  \
-  extern FILE *asm_out_text_file;                     \
-  fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a));        \
-} while (0)
-
-
-/* This is how to equate one symbol to another symbol.  The syntax used is
-   `SYM1=SYM2'.  Note that this is different from the way equates are done
-   with most svr4 assemblers, where the syntax is `.set SYM1,SYM2'.  */
-
-#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)				\
- do {	fprintf ((FILE), "\t");						\
-	assemble_name (FILE, LABEL1);					\
-	fprintf (FILE, " = ");						\
-	assemble_name (FILE, LABEL2);					\
-	fprintf (FILE, "\n");						\
-  } while (0)
diff --git a/gcc/config/mips/sni-svr4.h b/gcc/config/mips/sni-svr4.h
deleted file mode 100755
index cf6edbc..0000000
--- a/gcc/config/mips/sni-svr4.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* Definitions of target machine for GNU compiler.  SNI SINIX version.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Marco Walther (Marco.Walther@mch.sni.de).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MIPS_SVR4
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SVR4 -Dsinix -DSNI \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SVR4 \
--Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(mips)"
-
-#define SUBTARGET_CPP_SIZE_SPEC "\
--D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
-
-#define LINK_SPEC "\
-%{G*} \
-%{!mgas: \
-	%{dy} %{dn}}"
-		    
-#define LIB_SPEC "\
-	%{p:-lprof1} \
-	%{!p:%{pg:-lprof1} \
-	     %{!pg:-L/usr/ccs/lib/ -lc /usr/ccs/lib/crtn.o%s}}"
-
-#define STARTFILE_SPEC "\
-	%{pg:gcrt0.o%s} \
-	%{!pg:%{p:mcrt0.o%s} \
-	       %{!p:/usr/ccs/lib/crt1.o /usr/ccs/lib/crti.o /usr/ccs/lib/values-Xt.o%s}}"
-
-/* Mips System V.4 doesn't have a getpagesize() function needed by the
-   trampoline code, so use the POSIX sysconf function to get it.
-   This is only done when compiling the trampoline code.  */
-
-#ifdef  L_trampoline
-#include <unistd.h>
-
-#define getpagesize()	sysconf(_SC_PAGE_SIZE)
-#endif /*  L_trampoline */
-
-/* Use atexit for static constructors/destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
-/* Generate calls to memcpy, etc., not bcopy, etc.  */
-#define TARGET_MEM_FUNCTIONS
-
-#define OBJECT_FORMAT_ELF
-
-#define	TARGET_DEFAULT	MASK_ABICALLS
-#define ABICALLS_ASM_OP ".option pic2"
-
-#define MACHINE_TYPE "SNI running SINIX 5.42"
-
-#define MIPS_DEFAULT_GVALUE	0
-
-#define NM_FLAGS	"-p"
-
-/* wir haben ein Problem, wenn in einem Assembler-File keine .text-section
-   erzeugt wird. Dann landen diese Pseudo-Labels in irgendeiner anderen
-   section, z.B. .reginfo. Das macht den ld sehr ungluecklich. */
-
-#define ASM_IDENTIFY_GCC(mw_stream) \
-	fprintf(mw_stream, "\t.ident \"gcc2_compiled.\"\n");
-
-#define ASM_IDENTIFY_LANGUAGE(STREAM)
-
-#define ASM_LONG	".word\t"
-#define ASM_GLOBAL	".rdata\n\t\t.globl\t"
-
-#include "mips/mips.h"
-
-/* We do not want to run mips-tfile!  */
-#undef ASM_FINAL_SPEC
-
-#undef OBJECT_FORMAT_COFF
-
-/* We don't support debugging info for now. */
-#undef DBX_DEBUGGING_INFO
-#undef SDB_DEBUGGING_INFO
-#undef MIPS_DEBUGGING_INFO
-#undef PREFERRED_DEBUGGING_TYPE
-
-#define DWARF2_UNWIND_INFO 0
diff --git a/gcc/config/mips/svr3-4.h b/gcc/config/mips/svr3-4.h
deleted file mode 100755
index 18303ac..0000000
--- a/gcc/config/mips/svr3-4.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Definitions of target machine for GNU compiler. 
-   MIPS RISC-OS System V version.
-   Copyright (C) 1991 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MIPS_SYSV
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SYSV \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SYSV \
--Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)"
-
-#define STANDARD_INCLUDE_DIR "/sysv/usr/include"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
--systype /sysv/"
-		    
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}"
-
-#define MACHINE_TYPE "RISC-OS System V Mips"
-
-/* Override defaults for finding the MIPS tools.  */
-#define MD_STARTFILE_PREFIX "/sysv/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/sysv/usr/lib/cmplrs/cc/"
-
-/* Mips System V doesn't have a getpagesize() function needed by the
-   trampoline code, so use the POSIX sysconf function to get it.
-   This is only done when compiling the trampoline code.  */
-
-#ifdef  L_trampoline
-#include <sys/param.h>
-#include <unistd.h>
-
-#ifdef _SC_PAGE_SIZE
-#define getpagesize()	sysconf(_SC_PAGE_SIZE)
-
-#else				/* older rev of OS */
-#define getpagesize()	(NBPC)
-#endif /* !_SC_PAGE_SIZE */
-#endif /*  L_trampoline */
-
-/* Generate calls to memcpy, etc., not bcopy, etc.  */
-#define TARGET_MEM_FUNCTIONS
diff --git a/gcc/config/mips/svr3-5.h b/gcc/config/mips/svr3-5.h
deleted file mode 100755
index 495b389..0000000
--- a/gcc/config/mips/svr3-5.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Definitions of target machine for GNU compiler. 
-   MIPS RISC-OS 5.0 System V version.
-   Copyright (C) 1991, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MIPS_SYSV
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SYSV \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SYSV \
--Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)"
-
-#define STANDARD_INCLUDE_DIR "/sysv/usr/include"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \
--systype /sysv/ "
-		    
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}"
-
-#define MACHINE_TYPE "RISC-OS System V Mips"
-
-/* Override defaults for finding the MIPS tools.  */
-#define MD_STARTFILE_PREFIX "/sysv/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/sysv/usr/lib/cmplrs/cc/"
-
-/* Mips System V doesn't have a getpagesize() function needed by the
-   trampoline code, so use the POSIX sysconf function to get it.
-   This is only done when compiling the trampoline code.  */
-
-#ifdef  L_trampoline
-#include <sys/param.h>
-#include <unistd.h>
-
-/* In at least 5.0 and 5.01, there is no _SC_PAGE_SIZE macro, only a
-   _SC_PAGESIZE macro.  */
-#ifdef _SC_PAGESIZE
-#define _SC_PAGE_SIZE _SC_PAGESIZE
-#endif
-
-#ifdef _SC_PAGE_SIZE
-#define getpagesize()	sysconf(_SC_PAGE_SIZE)
-
-#else				/* older rev of OS */
-#define getpagesize()	(NBPC)
-#endif /* !_SC_PAGE_SIZE */
-#endif /*  L_trampoline */
-
-/* Generate calls to memcpy, etc., not bcopy, etc.  */
-#define TARGET_MEM_FUNCTIONS
-
-#include "mips/mips.h"
-
-/* Some assemblers have a bug that causes backslash escaped chars in .ascii
-   to be misassembled, so we just completely avoid it.  */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)			\
-do {							\
-  unsigned char *s;					\
-  int i;						\
-  for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++)	\
-    {							\
-      if ((i % 8) == 0)					\
-	fputs ("\n\t.byte\t", (FILE));			\
-      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
-    }							\
-  fputs ("\n", (FILE));					\
-} while (0)
diff --git a/gcc/config/mips/svr4-4.h b/gcc/config/mips/svr4-4.h
deleted file mode 100755
index d1ba64d..0000000
--- a/gcc/config/mips/svr4-4.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   MIPS RISC-OS System V.4 version.
-   Copyright (C) 1992, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MIPS_SVR4
-
-#define CPP_PREDEFINES "\
--Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SVR4 \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SVR4 \
--Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(mips)"
-
-#define STANDARD_INCLUDE_DIR "/svr4/usr/include"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
--systype /svr4/"
-		    
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}"
-
-#define MACHINE_TYPE "RISC-OS System V.4 Mips"
-
-/* Override defaults for finding the MIPS tools.  */
-#define MD_STARTFILE_PREFIX "/svr4/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/svr4/usr/lib/cmplrs/cc/"
-
-/* Mips System V.4 doesn't have a getpagesize() function needed by the
-   trampoline code, so use the POSIX sysconf function to get it.
-   This is only done when compiling the trampoline code.  */
-
-#ifdef  L_trampoline
-#include <unistd.h>
-
-#define getpagesize()	sysconf(_SC_PAGE_SIZE)
-#endif /*  L_trampoline */
-
-/* Use atexit for static constructors/destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
-/* Generate calls to memcpy, etc., not bcopy, etc.  */
-#define TARGET_MEM_FUNCTIONS
diff --git a/gcc/config/mips/svr4-5.h b/gcc/config/mips/svr4-5.h
deleted file mode 100755
index 799e1cd..0000000
--- a/gcc/config/mips/svr4-5.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   MIPS RISC-OS 5.0 System V.4 version.
-   Copyright (C) 1992 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MIPS_SVR4
-
-#define CPP_PREDEFINES \
-"-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SVR4 \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SVR4 \
--D_MIPS_SZINT=32 -D_MIPS_SZLONG=32 -D_MIPS_SZPTR=32 \
--Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(mips)"
-
-#define STANDARD_INCLUDE_DIR "/svr4/usr/include"
-
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \
--systype /svr4/ "
-		    
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
-
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}\
-	%{ansi:/svr4/usr/ccs/lib/values-Xc.o%s} \
-                          %{!ansi: \
-                           %{traditional:/svr4/usr/ccs/lib/values-Xt.o%s} \
-                           %{!traditional:/svr4/usr/ccs/lib/values-Xa.o%s}}"
-
-#define MACHINE_TYPE "RISC-OS System V.4 Mips"
-
-/* Override defaults for finding the MIPS tools.  */
-#define MD_STARTFILE_PREFIX "/svr4/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/svr4/usr/lib/cmplrs/cc/"
-
-/* Mips System V.4 doesn't have a getpagesize() function needed by the
-   trampoline code, so use the POSIX sysconf function to get it.
-   This is only done when compiling the trampoline code.  */
-
-#ifdef  L_trampoline
-#include <unistd.h>
-
-/* In at least 5.0 and 5.01, there is no _SC_PAGE_SIZE macro, only a
-   _SC_PAGESIZE macro.  */
-#ifdef _SC_PAGESIZE
-#define _SC_PAGE_SIZE _SC_PAGESIZE
-#endif
-
-#define getpagesize()	sysconf(_SC_PAGE_SIZE)
-#endif /*  L_trampoline */
-
-/* Use atexit for static constructors/destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
-/* Generate calls to memcpy, etc., not bcopy, etc.  */
-#define TARGET_MEM_FUNCTIONS
-
-#include "mips/mips.h"
-
-/* Some assemblers have a bug that causes backslash escaped chars in .ascii
-   to be misassembled, so we just completely avoid it.  */
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)			\
-do {							\
-  unsigned char *s;					\
-  int i;						\
-  for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++)	\
-    {							\
-      if ((i % 8) == 0)					\
-	fputs ("\n\t.byte\t", (FILE));			\
-      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
-    }							\
-  fputs ("\n", (FILE));					\
-} while (0)
diff --git a/gcc/config/mips/svr4-t.h b/gcc/config/mips/svr4-t.h
deleted file mode 100755
index b457aa5..0000000
--- a/gcc/config/mips/svr4-t.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Tandem S2 w/ NonStop UX. */
-
-/* Use the default value for this.  */
-#undef STANDARD_INCLUDE_DIR
-
-#undef MACHINE_TYPE
-#define MACHINE_TYPE "TANDEM System V.4 Mips"
-
-/* Use the default values in mips.h.  */
-#undef MD_STARTFILE_PREFIX
-#undef MD_EXEC_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
-#define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
-
-/* These are the same as the ones in svr4-5.h, except that references to
-   /svr4/ have been removed.  */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}\
-	%{ansi:/usr/lib/values-Xc.o%s} \
-                          %{!ansi: \
-                           %{traditional:/usr/lib/values-Xt.o%s} \
-                           %{!traditional:/usr/lib/values-Xa.o%s}}"
-
-#undef LINK_SPEC
-#define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
-%{bestGnum} %{shared} %{non_shared} \
-%{call_shared} %{no_archive} %{exact_version} \
-%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}"
diff --git a/gcc/config/mips/t-biendian b/gcc/config/mips/t-biendian
deleted file mode 100755
index ada0c2e..0000000
--- a/gcc/config/mips/t-biendian
+++ /dev/null
@@ -1,18 +0,0 @@
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
-# Don't let CTOR_LIST end up in sdata section.
-CRTSTUFF_T_CFLAGS = -G 0
-
-# We must build libgcc2.a with -G 0, in case the user wants to link
-# without the $gp register.
-TARGET_LIBGCC2_CFLAGS = -G 0
-
-MULTILIB_OPTIONS = EL/EB
-MULTILIB_DIRNAMES = el eb
-MULTILIB_MATCHES = EL=mel EB=meb
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/mips/t-bsd b/gcc/config/mips/t-bsd
deleted file mode 100755
index f9c6fc8..0000000
--- a/gcc/config/mips/t-bsd
+++ /dev/null
@@ -1,12 +0,0 @@
-# Exactly the same as t-mips, except we must define SYSTEM_HEADER_DIR
-# to point to the bsd43 include files.
-SYSTEM_HEADER_DIR = /bsd43/usr/include
-
-# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
-# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
-# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-bsd-gas b/gcc/config/mips/t-bsd-gas
deleted file mode 100755
index bfa5a7e..0000000
--- a/gcc/config/mips/t-bsd-gas
+++ /dev/null
@@ -1,8 +0,0 @@
-# Exactly the same as t-mips-gas, except we must define SYSTEM_HEADER_DIR
-# to point to the bsd43 include files.
-SYSTEM_HEADER_DIR = /bsd43/usr/include
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-cross64 b/gcc/config/mips/t-cross64
deleted file mode 100755
index bfca950..0000000
--- a/gcc/config/mips/t-cross64
+++ /dev/null
@@ -1,17 +0,0 @@
-SYSTEM_HEADER_DIR = /usr/cross64/usr/include
-
-AR = /usr/cross64/usr/bin/ar
-
-# The rest of the file is identical to t-iris6.
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 = 
-CROSS_LIBGCC1 = 
-
-MULTILIB_OPTIONS=mips1/mips2/mips3/mips4
-MULTILIB_DIRNAMES=
-MULTILIB_MATCHES=
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/mips/t-ecoff b/gcc/config/mips/t-ecoff
deleted file mode 100755
index 8de03ff..0000000
--- a/gcc/config/mips/t-ecoff
+++ /dev/null
@@ -1,92 +0,0 @@
-CONFIG2_H	= $(srcdir)/config/mips/ecoff.h
-
-# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
-# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
-# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-
-# When building a cross compiler, put the mips16 support functions in
-# libgcc1.a.
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = mips/mips16.S
-LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
-	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
-	_m16fltsisf _m16fixsfsi \
-	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
-	_m16extsfdf2 _m16trdfsf2 \
-	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
-	_m16fltsidf _m16fixdfsi \
-	_m16retsf _m16retdf \
-	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
-	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
-	_m16stubsf9 _m16stubsf10 \
-	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
-	_m16stubdf9 _m16stubdf10
-
-# We must build libgcc2.a with -G 0, in case the user wants to link
-# without the $gp register.
-TARGET_LIBGCC2_CFLAGS = -G 0
-
-# fp-bit and dp-bit are really part of libgcc1, but this will cause
-# them to be built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#ifdef __MIPSEL__' > dp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
-	echo '#endif' >> dp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#ifdef __MIPSEL__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
-	echo '#endif' >> fp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# Build the libraries for both hard and soft floating point
-
-MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3
-MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3
-MULTILIB_MATCHES = msingle-float=m4650
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# Add additional dependencies to recompile selected modules whenever the
-# tm.h file changes.  The files compiled are:
-#
-#	gcc.c		(*_SPEC changes)
-#	toplev.c	(new switches + assembly output changes)
-#	sdbout.c	(debug format changes)
-#	dbxout.c	(debug format changes)
-#	dwarfout.c	(debug format changes)
-#	final.c		(assembly output changes)
-#	varasm.c	(assembly output changes)
-#	cse.c		(cost functions)
-#	insn-output.c	(possible ifdef changes in tm.h)
-#	regclass.c	(fixed/call used register changes)
-#	cccp.c		(new preprocessor macros, -v version #)
-#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
-#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
-#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
-
-gcc.o: $(CONFIG2_H)
-toplev.o: $(CONFIG2_H)
-sdbout.o: $(CONFIG2_H)
-dbxout.o: $(CONFIG2_H)
-dwarfout.o: $(CONFIG2_H)
-final.o: $(CONFIG2_H)
-varasm.o: $(CONFIG2_H)
-cse.o: $(CONFIG2_H)
-insn-output.o: $(CONFIG2_H)
-regclass.o: $(CONFIG2_H)
-cccp.o: $(CONFIG2_H)
-explow.o: $(CONFIG2_H)
-recog.o: $(CONFIG2_H)
-reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/t-elf b/gcc/config/mips/t-elf
deleted file mode 100755
index dd01b7f..0000000
--- a/gcc/config/mips/t-elf
+++ /dev/null
@@ -1,96 +0,0 @@
-CONFIG2_H	= $(srcdir)/config/mips/ecoff.h
-
-# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
-# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
-# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-
-EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
-# Don't let CTOR_LIST end up in sdata section.
-CRTSTUFF_T_CFLAGS = -G 0
-
-# When building a cross compiler, put the mips16 support functions in
-# libgcc1.a.
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = mips/mips16.S
-LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
-	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
-	_m16fltsisf _m16fixsfsi \
-	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
-	_m16extsfdf2 _m16trdfsf2 \
-	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
-	_m16fltsidf _m16fixdfsi \
-	_m16retsf _m16retdf \
-	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
-	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
-	_m16stubsf9 _m16stubsf10 \
-	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
-	_m16stubdf9 _m16stubdf10
-
-# We must build libgcc2.a with -G 0, in case the user wants to link
-# without the $gp register.
-TARGET_LIBGCC2_CFLAGS = -G 0
-
-# fp-bit and dp-bit are really part of libgcc1, but this will cause
-# them to be built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#ifdef __MIPSEL__' > dp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
-	echo '#endif' >> dp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#ifdef __MIPSEL__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
-	echo '#endif' >> fp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# Build the libraries for both hard and soft floating point
-
-MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3
-MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3
-MULTILIB_MATCHES = msingle-float=m4650
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# Add additional dependencies to recompile selected modules whenever the
-# tm.h file changes.  The files compiled are:
-#
-#	gcc.c		(*_SPEC changes)
-#	toplev.c	(new switches + assembly output changes)
-#	sdbout.c	(debug format changes)
-#	dbxout.c	(debug format changes)
-#	dwarfout.c	(debug format changes)
-#	final.c		(assembly output changes)
-#	varasm.c	(assembly output changes)
-#	cse.c		(cost functions)
-#	insn-output.c	(possible ifdef changes in tm.h)
-#	regclass.c	(fixed/call used register changes)
-#	cccp.c		(new preprocessor macros, -v version #)
-#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
-#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
-#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
-
-gcc.o: $(CONFIG2_H)
-toplev.o: $(CONFIG2_H)
-sdbout.o: $(CONFIG2_H)
-dbxout.o: $(CONFIG2_H)
-dwarfout.o: $(CONFIG2_H)
-final.o: $(CONFIG2_H)
-varasm.o: $(CONFIG2_H)
-cse.o: $(CONFIG2_H)
-insn-output.o: $(CONFIG2_H)
-regclass.o: $(CONFIG2_H)
-cccp.o: $(CONFIG2_H)
-explow.o: $(CONFIG2_H)
-recog.o: $(CONFIG2_H)
-reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/t-iris6 b/gcc/config/mips/t-iris6
deleted file mode 100755
index 85a63f0..0000000
--- a/gcc/config/mips/t-iris6
+++ /dev/null
@@ -1,20 +0,0 @@
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 = 
-CROSS_LIBGCC1 = 
-
-# ??? If no mabi=X option given, but a mipsX option is, then should deal
-# with that.
-# ??? mabi=32 is deliberately left off the list because it doesn't work yet.
-MULTILIB_OPTIONS=mabi=n32/mabi=64
-MULTILIB_DIRNAMES=
-MULTILIB_MATCHES=
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# For svr4 we build crtbegin.o and crtend.o which serve to add begin and
-# end labels to the .ctors and .dtors section when we link using gcc.
-
-EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o
-CRTSTUFF_T_CFLAGS=-g1
diff --git a/gcc/config/mips/t-lsi b/gcc/config/mips/t-lsi
deleted file mode 100755
index b771834..0000000
--- a/gcc/config/mips/t-lsi
+++ /dev/null
@@ -1,100 +0,0 @@
-# CYGNUS LOCAL entire file angela
-# ??? The list of multilibs is probably overkill, but is conservatively
-# correct.  We probably don't need single-float, and mips3 libs.
-
-CONFIG2_H	= $(srcdir)/config/mips/ecoff.h
-
-# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
-# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
-# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-
-EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
-# Don't let CTOR_LIST end up in sdata section.
-CRTSTUFF_T_CFLAGS = -G 0
-
-# When building a cross compiler, put the mips16 support functions in
-# libgcc1.a.
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = mips/mips16.S
-LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
-	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
-	_m16fltsisf _m16fixsfsi \
-	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
-	_m16extsfdf2 _m16trdfsf2 \
-	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
-	_m16fltsidf _m16fixdfsi \
-	_m16retsf _m16retdf \
-	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
-	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
-	_m16stubsf9 _m16stubsf10 \
-	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
-	_m16stubdf9 _m16stubdf10
-
-# We must build libgcc2.a with -G 0, in case the user wants to link
-# without the $gp register.
-TARGET_LIBGCC2_CFLAGS = -G 0
-
-# fp-bit and dp-bit are really part of libgcc1, but this will cause
-# them to be built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#ifdef __MIPSEL__' > dp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
-	echo '#endif' >> dp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#ifdef __MIPSEL__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
-	echo '#endif' >> fp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# Build the libraries for both hard and soft floating point
-
-MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3/mips16
-MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3 mips16
-MULTILIB_MATCHES = msingle-float=m4650
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# Add additional dependencies to recompile selected modules whenever the
-# tm.h file changes.  The files compiled are:
-#
-#	gcc.c		(*_SPEC changes)
-#	toplev.c	(new switches + assembly output changes)
-#	sdbout.c	(debug format changes)
-#	dbxout.c	(debug format changes)
-#	dwarfout.c	(debug format changes)
-#	final.c		(assembly output changes)
-#	varasm.c	(assembly output changes)
-#	cse.c		(cost functions)
-#	insn-output.c	(possible ifdef changes in tm.h)
-#	regclass.c	(fixed/call used register changes)
-#	cccp.c		(new preprocessor macros, -v version #)
-#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
-#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
-#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
-
-gcc.o: $(CONFIG2_H)
-toplev.o: $(CONFIG2_H)
-sdbout.o: $(CONFIG2_H)
-dbxout.o: $(CONFIG2_H)
-dwarfout.o: $(CONFIG2_H)
-final.o: $(CONFIG2_H)
-varasm.o: $(CONFIG2_H)
-cse.o: $(CONFIG2_H)
-insn-output.o: $(CONFIG2_H)
-regclass.o: $(CONFIG2_H)
-cccp.o: $(CONFIG2_H)
-explow.o: $(CONFIG2_H)
-recog.o: $(CONFIG2_H)
-reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/t-mips b/gcc/config/mips/t-mips
deleted file mode 100755
index e57a55a..0000000
--- a/gcc/config/mips/t-mips
+++ /dev/null
@@ -1,8 +0,0 @@
-# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
-# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
-# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-mips-gas b/gcc/config/mips/t-mips-gas
deleted file mode 100755
index 94f1c44..0000000
--- a/gcc/config/mips/t-mips-gas
+++ /dev/null
@@ -1,4 +0,0 @@
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-ncd b/gcc/config/mips/t-ncd
deleted file mode 100755
index 6160b7e..0000000
--- a/gcc/config/mips/t-ncd
+++ /dev/null
@@ -1,2 +0,0 @@
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
diff --git a/gcc/config/mips/t-osfrose b/gcc/config/mips/t-osfrose
deleted file mode 100755
index e57a55a..0000000
--- a/gcc/config/mips/t-osfrose
+++ /dev/null
@@ -1,8 +0,0 @@
-# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
-# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
-# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-r3900 b/gcc/config/mips/t-r3900
deleted file mode 100755
index 055143f..0000000
--- a/gcc/config/mips/t-r3900
+++ /dev/null
@@ -1,95 +0,0 @@
-CONFIG2_H	= $(srcdir)/config/mips/ecoff.h
-
-# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
-# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
-# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-
-# When building a cross compiler, put the mips16 support functions in
-# libgcc1.a.
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = mips/mips16.S
-LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
-	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
-	_m16fltsisf _m16fixsfsi \
-	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
-	_m16extsfdf2 _m16trdfsf2 \
-	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
-	_m16fltsidf _m16fixdfsi \
-	_m16retsf _m16retdf \
-	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
-	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
-	_m16stubsf9 _m16stubsf10 \
-	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
-	_m16stubdf9 _m16stubdf10
-
-# We must build libgcc2.a with -G 0, in case the user wants to link
-# without the $gp register.
-TARGET_LIBGCC2_CFLAGS = -G 0
-
-# fp-bit and dp-bit are really part of libgcc1, but this will cause
-# them to be built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#ifdef __MIPSEL__' > dp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
-	echo '#endif' >> dp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#ifdef __MIPSEL__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
-	echo '#endif' >> fp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
-# Don't let CTOR_LIST end up in sdata section.
-CRTSTUFF_T_CFLAGS = -G 0
-
-# Build the libraries for both hard and soft floating point
-
-MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB
-MULTILIB_DIRNAMES = soft-float single el eb
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# Add additional dependencies to recompile selected modules whenever the
-# tm.h file changes.  The files compiled are:
-#
-#	gcc.c		(*_SPEC changes)
-#	toplev.c	(new switches + assembly output changes)
-#	sdbout.c	(debug format changes)
-#	dbxout.c	(debug format changes)
-#	dwarfout.c	(debug format changes)
-#	final.c		(assembly output changes)
-#	varasm.c	(assembly output changes)
-#	cse.c		(cost functions)
-#	insn-output.c	(possible ifdef changes in tm.h)
-#	regclass.c	(fixed/call used register changes)
-#	cccp.c		(new preprocessor macros, -v version #)
-#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
-#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
-#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
-
-gcc.o: $(CONFIG2_H)
-toplev.o: $(CONFIG2_H)
-sdbout.o: $(CONFIG2_H)
-dbxout.o: $(CONFIG2_H)
-dwarfout.o: $(CONFIG2_H)
-final.o: $(CONFIG2_H)
-varasm.o: $(CONFIG2_H)
-cse.o: $(CONFIG2_H)
-insn-output.o: $(CONFIG2_H)
-regclass.o: $(CONFIG2_H)
-cccp.o: $(CONFIG2_H)
-explow.o: $(CONFIG2_H)
-recog.o: $(CONFIG2_H)
-reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/t-svr3 b/gcc/config/mips/t-svr3
deleted file mode 100755
index 273c710..0000000
--- a/gcc/config/mips/t-svr3
+++ /dev/null
@@ -1,12 +0,0 @@
-# Exactly the same as t-mips, except we must define SYSTEM_HEADER_DIR
-# to point to the svr3 include files.
-SYSTEM_HEADER_DIR = /sysv/usr/include
-
-# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
-# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
-# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-svr3-gas b/gcc/config/mips/t-svr3-gas
deleted file mode 100755
index 99238f2..0000000
--- a/gcc/config/mips/t-svr3-gas
+++ /dev/null
@@ -1,8 +0,0 @@
-# Exactly the same as t-mips-gas, except we must define SYSTEM_HEADER_DIR
-# to point to the svr3 include files.
-SYSTEM_HEADER_DIR = /sysv/usr/include
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-svr4 b/gcc/config/mips/t-svr4
deleted file mode 100755
index 88029b9..0000000
--- a/gcc/config/mips/t-svr4
+++ /dev/null
@@ -1,12 +0,0 @@
-# Exactly the same as t-mips, except we must define SYSTEM_HEADER_DIR
-# to point to the svr4 include files.
-SYSTEM_HEADER_DIR = /svr4/usr/include
-
-# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
-# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
-# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-svr4-gas b/gcc/config/mips/t-svr4-gas
deleted file mode 100755
index 845b091..0000000
--- a/gcc/config/mips/t-svr4-gas
+++ /dev/null
@@ -1,8 +0,0 @@
-# Exactly the same as t-mips-gas, except we must define SYSTEM_HEADER_DIR
-# to point to the svr4 include files.
-SYSTEM_HEADER_DIR = /svr4/usr/include
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-ultrix b/gcc/config/mips/t-ultrix
deleted file mode 100755
index 7c1a845..0000000
--- a/gcc/config/mips/t-ultrix
+++ /dev/null
@@ -1,10 +0,0 @@
-CONFIG2_H	= $(srcdir)/config/mips/mips.h
-
-# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
-# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
-# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-vr4100 b/gcc/config/mips/t-vr4100
deleted file mode 100755
index 710c708..0000000
--- a/gcc/config/mips/t-vr4100
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG2_H	= $(srcdir)/config/mips/elf.h
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# We must build libgcc2.a with -G 0, in case the user wants to link
-# without the $gp register.
-TARGET_LIBGCC2_CFLAGS = -G 0
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c $(srcdir)/config/mips/mips16.S
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#ifdef __MIPSEL__' > dp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
-	echo '#endif' >> dp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#ifdef __MIPSEL__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
-	echo '#endif' >> fp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
-# Don't let CTOR_LIST end up in sdata section.
-CRTSTUFF_T_CFLAGS = -G 0
-
-# Build the libraries for soft floating point only
-
-MULTILIB_OPTIONS = EL/EB mno-mips16/mips16
-MULTILIB_DIRNAMES = el eb nomips16 mips16
-MULTILIB_MATCHES = EL=mel EB=meb
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# Add additional dependencies to recompile selected modules whenever the
-# tm.h file changes.  The files compiled are:
-#
-#	gcc.c		(*_SPEC changes)
-#	toplev.c	(new switches + assembly output changes)
-#	sdbout.c	(debug format changes)
-#	dbxout.c	(debug format changes)
-#	dwarfout.c	(debug format changes)
-#	final.c		(assembly output changes)
-#	varasm.c	(assembly output changes)
-#	cse.c		(cost functions)
-#	insn-output.c	(possible ifdef changes in tm.h)
-#	regclass.c	(fixed/call used register changes)
-#	cccp.c		(new preprocessor macros, -v version #)
-#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
-#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
-#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
-
-gcc.o: $(CONFIG2_H)
-toplev.o: $(CONFIG2_H)
-sdbout.o: $(CONFIG2_H)
-dbxout.o: $(CONFIG2_H)
-dwarfout.o: $(CONFIG2_H)
-final.o: $(CONFIG2_H)
-varasm.o: $(CONFIG2_H)
-cse.o: $(CONFIG2_H)
-insn-output.o: $(CONFIG2_H)
-regclass.o: $(CONFIG2_H)
-cccp.o: $(CONFIG2_H)
-explow.o: $(CONFIG2_H)
-recog.o: $(CONFIG2_H)
-reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/t-vr4300 b/gcc/config/mips/t-vr4300
deleted file mode 100755
index d91a716..0000000
--- a/gcc/config/mips/t-vr4300
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG2_H	= $(srcdir)/config/mips/elf.h
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# We must build libgcc2.a with -G 0, in case the user wants to link
-# without the $gp register.
-TARGET_LIBGCC2_CFLAGS = -G 0
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c $(srcdir)/config/mips/mips16.S
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#ifdef __MIPSEL__' > dp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
-	echo '#endif' >> dp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#ifdef __MIPSEL__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
-	echo '#endif' >> fp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# Build the libraries for hard floating point only
-
-MULTILIB_OPTIONS = EL/EB mgp32
-MULTILIB_DIRNAMES = el eb mgp32
-MULTILIB_MATCHES = EL=mel EB=meb
-
-EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
-# Don't let CTOR_LIST end up in sdata section.
-CRTSTUFF_T_CFLAGS = -G 0
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# Add additional dependencies to recompile selected modules whenever the
-# tm.h file changes.  The files compiled are:
-#
-#	gcc.c		(*_SPEC changes)
-#	toplev.c	(new switches + assembly output changes)
-#	sdbout.c	(debug format changes)
-#	dbxout.c	(debug format changes)
-#	dwarfout.c	(debug format changes)
-#	final.c		(assembly output changes)
-#	varasm.c	(assembly output changes)
-#	cse.c		(cost functions)
-#	insn-output.c	(possible ifdef changes in tm.h)
-#	regclass.c	(fixed/call used register changes)
-#	cccp.c		(new preprocessor macros, -v version #)
-#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
-#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
-#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
-
-gcc.o: $(CONFIG2_H)
-toplev.o: $(CONFIG2_H)
-sdbout.o: $(CONFIG2_H)
-dbxout.o: $(CONFIG2_H)
-dwarfout.o: $(CONFIG2_H)
-final.o: $(CONFIG2_H)
-varasm.o: $(CONFIG2_H)
-cse.o: $(CONFIG2_H)
-insn-output.o: $(CONFIG2_H)
-regclass.o: $(CONFIG2_H)
-cccp.o: $(CONFIG2_H)
-explow.o: $(CONFIG2_H)
-recog.o: $(CONFIG2_H)
-reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/t-vr5000 b/gcc/config/mips/t-vr5000
deleted file mode 100755
index 6ec11d8..0000000
--- a/gcc/config/mips/t-vr5000
+++ /dev/null
@@ -1,75 +0,0 @@
-#CYGNUS LOCAL entire file law
-CONFIG2_H	= $(srcdir)/config/mips/elf.h
-
-EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
-# Don't let CTOR_LIST end up in sdata section.
-CRTSTUFF_T_CFLAGS = -G 0
-
-# Suppress building libgcc1.a, since the MIPS compiler port is complete
-# and does not need anything from libgcc1.a.
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# We must build libgcc2.a with -G 0, in case the user wants to link
-# without the $gp register.
-TARGET_LIBGCC2_CFLAGS = -G 0
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#ifdef __MIPSEL__' > dp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
-	echo '#endif' >> dp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#ifdef __MIPSEL__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
-	echo '#endif' >> fp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# Build the libraries for hard floating point only
-MULTILIB_OPTIONS = EL/EB m5400
-MULTILIB_DIRNAMES = el eb vr5400
-MULTILIB_MATCHES = EL=mel EB=meb
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# Add additional dependencies to recompile selected modules whenever the
-# tm.h file changes.  The files compiled are:
-#
-#	gcc.c		(*_SPEC changes)
-#	toplev.c	(new switches + assembly output changes)
-#	sdbout.c	(debug format changes)
-#	dbxout.c	(debug format changes)
-#	dwarfout.c	(debug format changes)
-#	final.c		(assembly output changes)
-#	varasm.c	(assembly output changes)
-#	cse.c		(cost functions)
-#	insn-output.c	(possible ifdef changes in tm.h)
-#	regclass.c	(fixed/call used register changes)
-#	cccp.c		(new preprocessor macros, -v version #)
-#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
-#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
-#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
-
-gcc.o: $(CONFIG2_H)
-toplev.o: $(CONFIG2_H)
-sdbout.o: $(CONFIG2_H)
-dbxout.o: $(CONFIG2_H)
-dwarfout.o: $(CONFIG2_H)
-final.o: $(CONFIG2_H)
-varasm.o: $(CONFIG2_H)
-cse.o: $(CONFIG2_H)
-insn-output.o: $(CONFIG2_H)
-regclass.o: $(CONFIG2_H)
-cccp.o: $(CONFIG2_H)
-explow.o: $(CONFIG2_H)
-recog.o: $(CONFIG2_H)
-reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/ultrix.h b/gcc/config/mips/ultrix.h
deleted file mode 100755
index d6da6a8..0000000
--- a/gcc/config/mips/ultrix.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Definitions of target machine for GNU compiler; DECstation (Ultrix) version.
-   Copyright (C) 1991, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define DECSTATION
-
-#ifndef CPP_PREDEFINES
-#define CPP_PREDEFINES "\
--D__ANSI_COMPAT -DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD \
--Dbsd4_2 -Dhost_mips -Dmips -Dultrix -Dunix \
--Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
-#endif
-
-#ifndef LIB_SPEC
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc"
-#endif
-
-#define SUBTARGET_CPP_SPEC "\
-%{.cc:	-D__LANGUAGE_C -D_LANGUAGE_C} \
-%{.cxx:	-D__LANGUAGE_C -D_LANGUAGE_C} \
-%{.C:	-D__LANGUAGE_C -D_LANGUAGE_C} \
-"
-
-#ifndef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
-#endif
-
-#ifndef MACHINE_TYPE
-#define MACHINE_TYPE "DECstation running ultrix"
-#endif
-
-/* Use atexit for static constructors/destructors, instead of defining
-   our own exit function.  Ultrix 4.x has this, 3.x probably does not.  */
-#define HAVE_ATEXIT
-
-/* Generate calls to memcpy, etc., not bcopy, etc.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Work around assembler forward label references generated in exception
-   handling code. */
-#define DWARF2_UNWIND_INFO 0
-
-/* INITIALIZE_TRAMPOLINE calls this library function to flush
-   program and data caches.  */
-#define CACHE_FLUSH_FUNC "cacheflush"
diff --git a/gcc/config/mips/vxworks.h b/gcc/config/mips/vxworks.h
deleted file mode 100755
index 0856c37..0000000
--- a/gcc/config/mips/vxworks.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright (C) 1999 Free Software Foundation, Inc. */
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Undefine the following which were defined in elf.h.  Thise will cause the mips-vxworks
-   port to continue to use collect2 for constructors/destructors.  This entire file may
-   be removed when .ctor/.dtor section support is desired. */
-
-#undef CTORS_SECTION_ASM_OP
-#undef DTORS_SECTION_ASM_OP
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_sdata, in_rdata
-
-#undef INVOKE__main
-#undef NAME__MAIN
-#undef SYMBOL__MAIN
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS                                         \
-  SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \
-  SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP)
-
-#undef ASM_OUTPUT_CONSTRUCTOR
-#undef ASM_OUTPUT_DESTRUCTOR
-
-#undef CTOR_LIST_BEGIN
-#undef CTOR_LIST_END
-#undef DTOR_LIST_BEGIN
-#undef DTOR_LIST_END
-
-#undef STARTFILE_SPEC
-#undef ENDFILE_SPEC
-
-/*  End of undefines to turn off .ctor/.dtor section support */
diff --git a/gcc/config/mips/x-dec-osf1 b/gcc/config/mips/x-dec-osf1
deleted file mode 100755
index 6e46f0e..0000000
--- a/gcc/config/mips/x-dec-osf1
+++ /dev/null
@@ -1,17 +0,0 @@
-# Define CC and OLDCC as the same, so that the tests:
-#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
-#
-# will succeed (if OLDCC != CC, it is assumed that GCC is
-# being used in secondary stage builds).  We need to pass
-# the -Wf,-XNg1500 option so the compiler can compile the
-# G++ file cp-parse.c.  Otherwise it complains about
-# too many case statements.  -Olimit is so the user
-# can use -O2.  Down with fixed size tables!
-
-CC		= $(OLDCC)
-OPT		= -O1
-OLDCC		= cc -Wf,-XNg1500 -Olimit 3000 $(OPT)
-
-# The bison output files are machine-indep,
-# so different flags for a particular machine are not useful.
-#BISONFLAGS	= -l
diff --git a/gcc/config/mips/x-iris b/gcc/config/mips/x-iris
deleted file mode 100755
index cf135d1..0000000
--- a/gcc/config/mips/x-iris
+++ /dev/null
@@ -1,31 +0,0 @@
-# Define CC and OLDCC as the same, so that the tests:
-#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
-#
-# will succeed (if OLDCC != CC, it is assumed that GCC is
-# being used in secondary stage builds).  We need to pass
-# the -Wf,-XNg1500 option so the compiler can compile the
-# G++ file cp-parse.c.  Otherwise it complains about
-# too many case statements.  -Olimit is so the user
-# can use -O2.  Down with fixed size tables!
-# The -cckr is to turn off strict ANSI checking.
-
-# These definitions are commented out because they cause trouble with
-# autoconf.  It is believed that they aren't needed anymore.
-#CC		= $(OLDCC)
-#OPT		= -O1
-#OLDCC		= cc -Wf,-XNh2000,-XNg1500 -Olimit 3000 -cckr $(OPT)
-
-# The bison output files are machine-indep,
-# so different flags for a particular machine are not useful.
-#BISONFLAGS	= -l
-
-# -lmld is so we can link collect2 running native.
-# -lmalloc is supposed to be faster than the normal malloc
-CLIB		= -lmld -lmalloc
-
-# Show we need to use the C version of ALLOCA
-ALLOCA		= alloca.o
-
-# Find all of the declarations from the header files
-FIXPROTO_DEFINES= -D__EXTENSIONS__ -D_SGI_SOURCE -D_LANGUAGE_C_PLUS_PLUS
-
diff --git a/gcc/config/mips/x-iris3 b/gcc/config/mips/x-iris3
deleted file mode 100755
index 2743ab7..0000000
--- a/gcc/config/mips/x-iris3
+++ /dev/null
@@ -1,30 +0,0 @@
-# Define CC and OLDCC as the same, so that the tests:
-#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
-#
-# will succeed (if OLDCC != CC, it is assumed that GCC is
-# being used in secondary stage builds).  We need to pass
-# the -Wf,-XNg1500 option so the compiler can compile the
-# G++ file cp-parse.c.  Otherwise it complains about
-# too many case statements.  -Olimit is so the user
-# can use -O2.  Down with fixed size tables!
-
-# In at least one version of Irix, v3.3.2, the compiler does not accept
-# the -cckr option, so, lets try without it for all versions of Irix 3.x.
-# The -cckr is to turn off strict ANSI checking.
-
-# These definitions are commented out because they cause trouble with
-# autoconf.  It is believed that they aren't needed anymore.
-#CC		= $(OLDCC)
-#OPT		= -O1
-#OLDCC		= cc -Wf,-XNh2000,-XNg1500 -Olimit 3000 $(OPT)
-
-# The bison output files are machine-indep,
-# so different flags for a particular machine are not useful.
-#BISONFLAGS	= -l
-
-# -lmld is so we can link collect2 running native.
-# -lmalloc is supposed to be faster than the normal malloc
-CLIB		= -lmld -lmalloc
-
-# Show we need to use the C version of ALLOCA
-ALLOCA		= alloca.o
diff --git a/gcc/config/mips/x-iris6 b/gcc/config/mips/x-iris6
deleted file mode 100755
index 88c41f4..0000000
--- a/gcc/config/mips/x-iris6
+++ /dev/null
@@ -1,11 +0,0 @@
-# We force the use of the O32 ABI for two reasons.
-# 1) For consistency, because some versions of Irix 6 default to the O32 ABI
-#    and some versions default to the N64 ABI.
-# 2) To avoid SGI compiler bugs.  The v6.x and v7.0 compilers from SGI have
-#    bugs that cause gcc to be miscompiled when the N32 or N64 ABIs are used.
-#    The O32 ABI is known to be OK.
-CC = $(OLDCC)
-OLDCC = cc -32
-
-# Find all of the declarations from the header files
-FIXPROTO_DEFINES= -D__EXTENSIONS__  -D_SGI_SOURCE -D_LANGUAGE_C_PLUS_PLUS
diff --git a/gcc/config/mips/x-mips b/gcc/config/mips/x-mips
deleted file mode 100755
index 7b40743..0000000
--- a/gcc/config/mips/x-mips
+++ /dev/null
@@ -1,20 +0,0 @@
-# Define CC and OLDCC as the same, so that the tests:
-#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
-#
-# will succeed (if OLDCC != CC, it is assumed that GCC is
-# being used in secondary stage builds).  We need to pass
-# the -Wf,-XNg1500 option so the compiler can compile the
-# G++ file cp-parse.c.  Otherwise it complains about
-# too many case statements.  The -Olimit is so the user
-# can use -O2.  Down with fixed size tables!
-
-CC		= $(OLDCC)
-OPT		= -O1
-OLDCC		= cc -Wf,-XNg1500,-XNh2000 -Olimit 3000 $(OPT)
-
-# The bison output files are machine-indep,
-# so different flags for a particular machine are not useful.
-#BISONFLAGS	= -l
-
-# This is so we can link collect2 running native.
-CLIB		= -lmld
diff --git a/gcc/config/mips/x-netbsd b/gcc/config/mips/x-netbsd
deleted file mode 100755
index 49a89f3..0000000
--- a/gcc/config/mips/x-netbsd
+++ /dev/null
@@ -1,17 +0,0 @@
-# Don't run fixproto
-STMP_FIXPROTO =
-
-# We don't need GCC's own include files.
-USER_H = $(srcdir)/ginclude/stdarg.h $(srcdir)/ginclude/varargs.h \
-	 $(srcdir)/ginclude/va-mips.h $(EXTRA_HEADERS) $(LANG_EXTRA_HEADERS)
-
-XLIMITS_H =
-
-# We don't need even the files GCC insists we need.
-GENINCLUDES = Makefile.in
-
-# A lot of stuff needs to go elsewhere.
-includedir=$(exec_prefix)/include
-infodir=$(exec_prefix)/share/info
-tooldir=$(libdir)/cross/$(target)
-mandir=$(exec_prefix)/share/man/man1
diff --git a/gcc/config/mips/x-nws3250v4 b/gcc/config/mips/x-nws3250v4
deleted file mode 100755
index 4f5cf26..0000000
--- a/gcc/config/mips/x-nws3250v4
+++ /dev/null
@@ -1,19 +0,0 @@
-# Define CC and OLDCC as the same, so that the tests:
-#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
-#
-# will succeed (if OLDCC != CC, it is assumed that GCC is
-# being used in secondary stage builds).  We need to pass
-# the -Wf,-XNg1500 option so the compiler can compile the
-# G++ file cp-parse.c.  Otherwise it complains about
-# too many case statements.  Down with fixed size tables!
-
-CC		= $(OLDCC)
-OLDCC		= cc -Wf,-XNg1500
-CCLIBFLAGS	= -G 0
-
-ALLOCA		= alloca.o
-
-# The bison output files are machine-indep,
-# so different flags for a particular machine are not useful.
-#BISONFLAGS	= -l
-
diff --git a/gcc/config/mips/x-osfrose b/gcc/config/mips/x-osfrose
deleted file mode 100755
index 825276c..0000000
--- a/gcc/config/mips/x-osfrose
+++ /dev/null
@@ -1,32 +0,0 @@
-# Define CC and OLDCC as the same, so that the tests:
-#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
-#
-# will succeed (if OLDCC != CC, it is assumed that GCC is
-# being used in secondary stage builds).
-
-BUILD		=
-CC		= $(OLDCC)
-CLIB		= -lld
-X_CFLAGS	= $(DEB_OPT) $(MSTATS) $(SHLIB) $(X_DEFINES)
-X_CFLAGS_NODEBUG = $(NO_DEBUG) $(MSTATS) $(OPT) $(PROFILE) $(SHLIB) $(X_DEFINES) $(XCFLAGS)
-CCLIBFLAGS	= -O -pic-extern
-CPP_ABORT	= # -Dabort=fancy_abort
-CPPFLAGS	= $(CPP_ABORT) $(SYSTEM_INCLUDES)
-DEB_OPT		= $(OPT) $(DEBUG) $(PROFILE)
-DEBUG		= 
-DEBUG_COLLECT	= # -DDEBUG
-CCLIBFLAGS	= -O -DNO_HALF_PIC
-GCC_CFLAGS	= $(INTERNAL_CFLAGS) $(X_CFLAGS) $(T_CFLAGS) $(CFLAGS) -B./ -DPOSIX -DNO_HALF_PIC
-LIBGCC2_CFLAGS	= -O2 $(GCC_CFLAGS) -g1 -pic-extern
-LDFLAGS		=
-MSTATS		= # -mstats
-OLDCC		= /usr/ccs/gcc/gcc
-OPT		= -O2
-PROFILE		=
-SHLIB		= -pic-none
-SYSTEM_INCLUDES	= # -I${BUILD}/usr/include
-X_DEFINES	= -Dvfork=fork
-
-libdir		= /usr/ccs
-mandir		= /usr/ccs/gcc/$(target)/$(version)
-bindir		= /usr/ccs/gcc/$(target)/$(version)
diff --git a/gcc/config/mips/x-sni-svr4 b/gcc/config/mips/x-sni-svr4
deleted file mode 100755
index f986f88..0000000
--- a/gcc/config/mips/x-sni-svr4
+++ /dev/null
@@ -1,18 +0,0 @@
-# Define CC and OLDCC as the same, so that the tests:
-#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
-#
-# will succeed (if OLDCC != CC, it is assumed that GCC is
-# being used in secondary stage builds).
-# -Olimit is so the user can use -O2.  Down with fixed
-# size tables!
-
-CC		= $(OLDCC)
-OPT		=
-OLDCC		= cc -Olimit 3000 $(OPT)
-
-X_CFLAGS	= -DNO_SYS_SIGLIST
-
-# Show we need to use the C version of ALLOCA
-# The SVR3 configurations have it, but the SVR4 configurations don't.
-# For now, just try using it for all SVR* configurations.
-ALLOCA		= alloca.o
diff --git a/gcc/config/mips/x-sony b/gcc/config/mips/x-sony
deleted file mode 100755
index c64593d..0000000
--- a/gcc/config/mips/x-sony
+++ /dev/null
@@ -1,18 +0,0 @@
-# Make internal tables bigger.
-OLDCC=cc -Wf,-XNg1500,-XNh2000 -Olimit 3000 $(OPT)
-
-# Define CC and OLDCC as the same, so that the tests:
-#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
-#
-# will succeed (if OLDCC != CC, it is assumed that GCC is
-# being used in secondary stage builds).  We need to pass
-# the -Wf,-XNg1500 option so the compiler can compile the
-# G++ file cp-parse.c.  Otherwise it complains about
-# too many case statements.  The -Olimit is so the user
-# can use -O2.  Down with fixed size tables!
-
-CC		= $(OLDCC)
-OPT		= -O1
-
-# This is so we can link collect2 running native.
-CLIB		= -lmld
diff --git a/gcc/config/mips/x-sysv b/gcc/config/mips/x-sysv
deleted file mode 100755
index 2c173b1..0000000
--- a/gcc/config/mips/x-sysv
+++ /dev/null
@@ -1,26 +0,0 @@
-# Define CC and OLDCC as the same, so that the tests:
-#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
-#
-# will succeed (if OLDCC != CC, it is assumed that GCC is
-# being used in secondary stage builds).  We need to pass
-# the -Wf,-XNg1500 option so the compiler can compile the
-# G++ file cp-parse.c.  Otherwise it complains about
-# too many case statements.  -Olimit is so the user
-# can use -O2.  Down with fixed size tables!
-
-CC		= $(OLDCC)
-OPT		= -O1
-OLDCC		= cc -Wf,-XNg1500,-XNh2000 -Olimit 3000 $(OPT)
-
-# The bison output files are machine-indep,
-# so different flags for a particular machine are not useful.
-#BISONFLAGS	= -l
-
-# This enables collect2 to link.
-# Some systems use version 2.11 of the compilers.  Some use version 3.11.
-CLIB= -L/usr/lib/cmplrs/cc2.11 -L/usr/lib/cmplrs/cc3.11 -lmld
-
-# Show we need to use the C version of ALLOCA
-# The SVR3 configurations have it, but the SVR4 configurations don't.
-# For now, just try using it for all SVR* configurations.
-ALLOCA		= alloca.o
diff --git a/gcc/config/mips/x-ultrix b/gcc/config/mips/x-ultrix
deleted file mode 100755
index 6e46f0e..0000000
--- a/gcc/config/mips/x-ultrix
+++ /dev/null
@@ -1,17 +0,0 @@
-# Define CC and OLDCC as the same, so that the tests:
-#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
-#
-# will succeed (if OLDCC != CC, it is assumed that GCC is
-# being used in secondary stage builds).  We need to pass
-# the -Wf,-XNg1500 option so the compiler can compile the
-# G++ file cp-parse.c.  Otherwise it complains about
-# too many case statements.  -Olimit is so the user
-# can use -O2.  Down with fixed size tables!
-
-CC		= $(OLDCC)
-OPT		= -O1
-OLDCC		= cc -Wf,-XNg1500 -Olimit 3000 $(OPT)
-
-# The bison output files are machine-indep,
-# so different flags for a particular machine are not useful.
-#BISONFLAGS	= -l
diff --git a/gcc/config/mips/xm-iris3.h b/gcc/config/mips/xm-iris3.h
deleted file mode 100755
index 448b7ac..0000000
--- a/gcc/config/mips/xm-iris3.h
+++ /dev/null
@@ -1,3 +0,0 @@
-#include "mips/xm-mips.h"
-
-#define USG
diff --git a/gcc/config/mips/xm-iris4.h b/gcc/config/mips/xm-iris4.h
deleted file mode 100755
index c01d3f4..0000000
--- a/gcc/config/mips/xm-iris4.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#include "mips/xm-mips.h"
-
-#define USG
-
-#if 0
-#ifdef __GNUC__
-/* The normal irix compiler requires alloca.h or alloca doesn't work.
-   However, the IRIX compiler doesn't allow alloca to be stored in
-   something like ptr->field = alloca(), so we just use the normal
-   C alloca.  */
-#include <alloca.h>
-#endif
-#endif
diff --git a/gcc/config/mips/xm-iris5.h b/gcc/config/mips/xm-iris5.h
deleted file mode 100755
index 616055f..0000000
--- a/gcc/config/mips/xm-iris5.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#include "mips/xm-mips.h"
-
-/* On SGI IRIX 5.3, inttypes.h clashes with sys/types.h, but the clash
-   (when compiled with GCC) is a warning, so configure.in thinks it's OK
-   to use it.  Work around this problem.  */
-
-#ifdef HAVE_INTTYPES_H
-#undef HAVE_INTTYPES_H
-#endif
diff --git a/gcc/config/mips/xm-iris6.h b/gcc/config/mips/xm-iris6.h
deleted file mode 100755
index 4d429c7..0000000
--- a/gcc/config/mips/xm-iris6.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#define MIPS_OVERRIDE_ALLOCA
-#ifndef __GNUC__
-#include <alloca.h>
-#else
-extern void *alloca ();
-#endif
-
-#include "mips/xm-mips.h"
-
-#define USG
-
-#undef HOST_BITS_PER_LONG
-#define HOST_BITS_PER_LONG	_MIPS_SZLONG
-
-#ifndef inhibit_libc
-#include "string.h"
-#endif
diff --git a/gcc/config/mips/xm-mips.h b/gcc/config/mips/xm-mips.h
deleted file mode 100755
index ad49d7f..0000000
--- a/gcc/config/mips/xm-mips.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Configuration for GNU C-compiler for MIPS Rx000 family
-   Copyright (C) 1989, 1990, 1991, 1993, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#if !defined(MIPSEL) && !defined(__MIPSEL__)
-#define HOST_WORDS_BIG_ENDIAN
-#endif
-
-/* Enable host-conditionals for MIPS machines.  */
-#ifndef MIPS
-#define MIPS 1
-#endif
-
-/* A code distinguishing the floating point format of the host
-   machine.  There are three defined values: IEEE_FLOAT_FORMAT,
-   VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT.  */
-
-#define HOST_FLOAT_FORMAT IEEE_FLOAT_FORMAT
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-#ifndef __GNUC__
-/* The MIPS compiler gets it wrong, and treats enumerated bitfields
-   as signed quantities, making it impossible to use an 8-bit enum
-   for compiling GNU C++.  */
-#define ONLY_INT_FIELDS 1
-#endif
-
-#ifndef MIPS_OVERRIDE_ALLOCA
-#ifndef __GNUC__
-#define USE_C_ALLOCA
-
-#ifdef __STDC__
-extern void * alloca ();
-#else
-extern char * alloca ();
-#endif
-
-/* for the emacs version of alloca */
-#define STACK_DIRECTION	-1
-#endif
-#endif /* not MIPS_OVERRIDE_ALLOCA */
diff --git a/gcc/config/mips/xm-netbsd.h b/gcc/config/mips/xm-netbsd.h
deleted file mode 100755
index b9d3c70..0000000
--- a/gcc/config/mips/xm-netbsd.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include "mips/xm-mips.h"
-#include "config/xm-netbsd.h"
diff --git a/gcc/config/mips/xm-news.h b/gcc/config/mips/xm-news.h
deleted file mode 100755
index e3eda9d..0000000
--- a/gcc/config/mips/xm-news.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* This file is for the Sony Mips News running "NewsOS Version 5",
-   which is really System V.  */
-#include "mips/xm-sysv.h"
-
-/* Sony has a funny name for this symbol.  */
-#define sys_siglist _sys_siglist
-#undef SYS_SIGLIST_DECLARED
-#define SYS_SIGLIST_DECLARED
diff --git a/gcc/config/mips/xm-nws3250v4.h b/gcc/config/mips/xm-nws3250v4.h
deleted file mode 100755
index 34ab631..0000000
--- a/gcc/config/mips/xm-nws3250v4.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#define USG
-
-#include "xm-mips.h"
-
-/* If compiling with mips compiler, we are probably using alloca.c,
-   so help it work right.  */
-#ifndef __GNUC__
-#define USE_C_ALLOCA
-#endif
diff --git a/gcc/config/mips/xm-sysv.h b/gcc/config/mips/xm-sysv.h
deleted file mode 100755
index 05a8d6c..0000000
--- a/gcc/config/mips/xm-sysv.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Configuration for GNU C-compiler for UMIPS operating system
-   Copyright (C) 1989, 1990, 1991, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/*
- *  Notes for compiling gcc on umips (v3.0)
- *	- change the -g in the CFLAGS to a -g3 or take it out all together.
- *	- do not define DBX_DEBUGGING_INFO in tm.h, it doesn't exist (unless
- *	you get one from a bsd system)
- */
-
-#define USG
-
-#include "mips/xm-mips.h"
diff --git a/gcc/config/mips/xm-sysv4.h b/gcc/config/mips/xm-sysv4.h
deleted file mode 100755
index b79664b..0000000
--- a/gcc/config/mips/xm-sysv4.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#include "mips/xm-sysv.h"
-
-/* SVR4 provides no sys_siglist,
-   but does offer the same data under another name.  */
-#define sys_siglist _sys_siglist
-#undef SYS_SIGLIST_DECLARED
-#define SYS_SIGLIST_DECLARED
diff --git a/gcc/config/mn10200/divmod.c b/gcc/config/mn10200/divmod.c
deleted file mode 100755
index 6faa091..0000000
--- a/gcc/config/mn10200/divmod.c
+++ /dev/null
@@ -1,50 +0,0 @@
-long udivmodsi4 ();
-
-long
-__divsi3 (long a, long b)
-{
-  int neg = 0;
-  long res;
-
-  if (a < 0)
-    {
-      a = -a;
-      neg = !neg;
-    }
-
-  if (b < 0)
-    {
-      b = -b;
-      neg = !neg;
-    }
-
-  res = udivmodsi4 (a, b, 0);
-
-  if (neg)
-    res = -res;
-
-  return res;
-}
-
-long
-__modsi3 (long a, long b)
-{
-  int neg = 0;
-  long res;
-
-  if (a < 0)
-    {
-      a = -a;
-      neg = 1;
-    }
-
-  if (b < 0)
-    b = -b;
-
-  res = udivmodsi4 (a, b, 1);
-
-  if (neg)
-    res = -res;
-
-  return res;
-}
diff --git a/gcc/config/mn10200/lib1funcs.asm b/gcc/config/mn10200/lib1funcs.asm
deleted file mode 100755
index ff98fcc..0000000
--- a/gcc/config/mn10200/lib1funcs.asm
+++ /dev/null
@@ -1,609 +0,0 @@
-/* libgcc1 routines for Matsushita mn10200.
-   Copyright (C) 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with files
-   compiled with GCC to produce an executable, this does not cause
-   the resulting executable to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-#ifdef L_divhi3
-	/* Derive signed division/modulo from unsigned "divu" instruction.  */
-	.text
-	.globl ___divhi3
-	.type ___divhi3,@function
-___divhi3:
-
-	/* We're going to need some scratch registers, so save d2/d3
-	   into the stack.  */
-	add -8,a3
-	movx d2,(0,a3)
-	movx d3,(4,a3)
-
-	/* Loading zeros into registers now allows us to use them
-	   in the compare instructions, which saves a total of
-	   two bytes (egad).  */
-	sub d3,d3
-	sub d2,d2
-	sub a0,a0
-
-	/* If first operand is negative, then make it positive.
-	   It will be contained in d2 just before .L1. 
-
-	   a0 tells us if the first operand was negated.  */
-	cmp d2,d0
-	bge .L0
-	sub d0,d2
-	mov 1,a0
-	bra .L1
-.L0:
-	mov d0,d2
-.L1:
-	/* If the second operand is negative, then make it positive.
-	   It will be contained in d3 just before .L3. 
-
-	   d0 tells us if the second operand was negated.  */
-	cmp d3,d1
-	bge .L2
-	sub d1,d3
-	mov 1,d0
-	bra .L3
-.L2:
-	sub d0,d0
-	mov d1,d3
-.L3:
-	/* Loading d1 with zero here allows us to save one byte
-	   in the comparison below.  */
-
-	sub d1,d1
-
-	/* Make sure to clear the mdr register, then do the unsigned
-	   division.  Result will be in d2/mdr.  */
-	mov d1,mdr
-	divu d3,d2
-
-	/* Negate the remainder based on the first argument negation
-	   flag only.  */
-	cmp d1,a0
-	beq .L4
-	mov mdr,d3
-	sub d3,d1
-	bra .L5
-.L4:
-	mov mdr,d1
-
-.L5:
-	/* Negate the result if either, but not both of the inputs
-	   were negated.  */
-	mov a0,d3
-	xor d3,d0
-	beq .L6
-	sub d0,d0
-	sub d2,d0
-	bra .L7
-.L6:
-	mov d2,d0
-.L7:
-	
-	/* Restore our scratch registers, deallocate our stack and return.  */
-	movx (0,a3),d2
-	movx (4,a3),d3
-	add 8,a3
-	rts
-	.size ___divhi3,.-___divhi3
-#endif
-
-#ifdef L_modhi3
-	.text
-	.globl ___modhi3
-	.type ___modhi3,@function
-___modhi3:
-	jsr ___divhi3
-	mov d1,d0
-	rts
-	.size ___modhi3,.-___modhi3
-#endif
-
-#ifdef L_addsi3
-	.text
-	.globl ___addsi3
-	.type  ___addsi3,@function
-___addsi3:
-	add -4,a3
-	movx d2,(0,a3)
-	mov (8,a3),d2
-	add d2,d0
-	mov (10,a3),d2
-	addc d2,d1
-	movx (0,a3),d2
-	add 4,a3
-	rts
-
-	.size ___addsi3,.-___addsi3
-#endif
-
-#ifdef L_subsi3
-	.text
-	.globl ___subsi3
-	.type  ___subsi3,@function
-___subsi3:
-	add -4,a3
-	movx d2,(0,a3)
-	mov (8,a3),d2
-	sub d2,d0
-	mov (10,a3),d2
-	subc d2,d1
-	movx (0,a3),d2
-	add 4,a3
-	rts
-
-	.size ___subsi3,.-___subsi3
-#endif
-
-#ifdef L_mulsi3
-	.text
-	.globl ___mulsi3
-	.type  ___mulsi3,@function
-___mulsi3:
-	add -4,a3
-	mov a1,(0,a3)
-	mov d0,a0
-	/* Multiply arg0 msb with arg1 lsb.
-	   arg0 msb is in register d1,
-	   arg1 lsb is in memory.  */
-	mov (8,a3),d0
-	mulu d0,d1
-	mov d1,a1
-
-	/* Multiply arg0 lsb with arg1 msb.
-	   arg0 msb is in register a0,
-	   arg1 lsb is in memory.  */
-	mov a0,d0
-	mov (10,a3),d1
-	mulu d0,d1
-
-	/* Add the cross products.  */
-	add d1,a1
-
-	/* Now multiply arg0 lsb with arg1 lsb.  */
-	mov (8,a3),d1
-	mulu d1,d0
-
-	/* Add in the upper 16 bits to the cross product sum.  */
-	mov mdr,d1
-	add a1,d1
-	mov (0,a3),a1
-	add 4,a3
-	rts
-
-	.size ___mulsi3,.-___mulsi3
-#endif
-
-#ifdef  L_ashlsi3
-	.text
-	.globl ___ashlsi3
-	.type  ___ashlsi3,@function
-___ashlsi3:
-	mov (4,a3),a0
-	cmp 0,a0
-	beq .L0
-.L1:
-	add d0,d0
-	addc d1,d1
-	add -1,a0
-	bne .L1
-.L0:
-	rts
-
-	.size ___ashlsi3,.-___ashlsi3
-#endif
-
-#ifdef  L_lshrsi3
-	.text
-	.globl ___lshrsi3
-	.type  ___lshrsi3,@function
-___lshrsi3:
-	mov (4,a3),a0
-	cmp 0,a0
-	beq .L0
-.L1:
-	lsr d1
-	ror d0
-	add -1,a0
-	bne .L1
-.L0:
-	rts
-
-	.size ___lshrsi3,.-___lshrsi3
-#endif
-
-#ifdef  L_ashrsi3
-	.text
-	.globl ___ashrsi3
-	.type  ___ashrsi3,@function
-___ashrsi3:
-	mov (4,a3),a0
-	cmp 0,a0
-	beq .L0
-.L1:
-	asr d1
-	ror d0
-	add -1,a0
-	bne .L1
-.L0:
-	rts
-
-	.size ___ashrsi3,.-___ashrsi3
-#endif
-
-/* All functions beyond this point pass their arguments in registers! */
-#ifdef  L_negsi2_d0
-	.text
-	.globl ___negsi2_d0
-	.type  ___negsi2_d0,@function
-___negsi2_d0:
-	add -8,a3
-	movx d3,(0,a3)
-	movx d2,(4,a3)
-	mov d0,d2
-	mov d1,d3
-	sub d0,d0
-	sub d1,d1
-	sub d2,d0
-	subc d3,d1
-	movx (0,a3),d3
-	movx (4,a3),d2
-	add 8,a3
-	rts
-
-	.size ___negsi2_d0,.-___negsi2_d0
-#endif
-
-#ifdef  L_negsi2_d2
-	.text
-	.globl ___negsi2_d2
-	.type  ___negsi2_d2,@function
-___negsi2_d2:
-	add -8,a3
-	movx d1,(0,a3)
-	movx d0,(4,a3)
-	mov d2,d0
-	mov d3,d1
-	sub d2,d2
-	sub d3,d3
-	sub d0,d2
-	subc d1,d3
-	movx (0,a3),d1
-	movx (4,a3),d0
-	add 8,a3
-	rts
-
-	.size ___negsi2_d2,.-___negsi2_d2
-#endif
-
-#ifdef  L_zero_extendpsisi2_d0
-	.text
-	.globl ___zero_extendpsisi2_d0
-	.type  ___zero_extendpsisi2_d0,@function
-___zero_extendpsisi2_d0:
-	add -4,a3
-	movx d0,(0,a3)
-	movbu (2,a3),d1
-	add 4,a3
-	rts
-
-	.size ___zero_extendpsisi2_d0,.-___zero_extendpsisi2_d0
-#endif
-
-#ifdef  L_zero_extendpsisi2_d2
-	.text
-	.globl ___zero_extendpsisi2_d2
-	.type  ___zero_extendpsisi2_d2,@function
-___zero_extendpsisi2_d2:
-	add -4,a3
-	movx d2,(0,a3)
-	movbu (2,a3),d3
-	add 4,a3
-	rts
-
-	.size ___zero_extendpsisi2_d2,.-___zero_extendpsisi2_d2
-#endif
-
-#ifdef  L_sign_extendpsisi2_d0
-	.text
-	.globl ___sign_extendpsisi2_d0
-	.type  ___sign_extendpsisi2_d0,@function
-___sign_extendpsisi2_d0:
-	add -4,a3
-	movx d0,(0,a3)
-	movb (2,a3),d1
-	add 4,a3
-	rts
-
-	.size ___sign_extendpsisi2_d0,.-___sign_extendpsisi2_d0
-#endif
-
-#ifdef  L_sign_extendpsisi2_d2
-	.text
-	.globl ___sign_extendpsisi2_d2
-	.type  ___sign_extendpsisi2_d2,@function
-___sign_extendpsisi2_d2:
-	add -4,a3
-	movx d2,(0,a3)
-	movb (2,a3),d3
-	add 4,a3
-	rts
-
-	.size ___sign_extendpsisi2_d2,.-___sign_extendpsisi2_d2
-#endif
-
-#ifdef  L_truncsipsi2_d0_d0
-	.text
-	.globl ___truncsipsi2_d0_d0
-	.type  ___truncsipsi2_d0_d0,@function
-___truncsipsi2_d0_d0:
-	add -4,a3
-	mov d0,(a3)
-	mov d1,(2,a3)
-	movx (0,a3),d0
-	add 4,a3
-	rts
-
-	.size ___truncsipsi2_d0_d0,.-___truncsipsi2_d0_d0
-#endif
-
-#ifdef  L_truncsipsi2_d0_d1
-	.text
-	.globl ___truncsipsi2_d0_d1
-	.type  ___truncsipsi2_d0_d1,@function
-___truncsipsi2_d0_d1:
-	add -4,a3
-	mov d0,(a3)
-	mov d1,(2,a3)
-	movx (0,a3),d1
-	add 4,a3
-	rts
-
-	.size ___truncsipsi2_d0_d1,.-___truncsipsi2_d0_d1
-#endif
-
-#ifdef  L_truncsipsi2_d0_d2
-	.text
-	.globl ___truncsipsi2_d0_d2
-	.type  ___truncsipsi2_d0_d2,@function
-___truncsipsi2_d0_d2:
-	add -4,a3
-	mov d0,(a3)
-	mov d1,(2,a3)
-	movx (0,a3),d2
-	add 4,a3
-	rts
-
-	.size ___truncsipsi2_d0_d2,.-___truncsipsi2_d0_d2
-#endif
-
-#ifdef  L_truncsipsi2_d0_d3
-	.text
-	.globl ___truncsipsi2_d0_d3
-	.type  ___truncsipsi2_d0_d3,@function
-___truncsipsi2_d0_d3:
-	add -4,a3
-	mov d0,(a3)
-	mov d1,(2,a3)
-	movx (0,a3),d3
-	add 4,a3
-	rts
-
-	.size ___truncsipsi2_d0_d3,.-___truncsipsi2_d0_d3
-#endif
-
-#ifdef  L_truncsipsi2_d2_d0
-	.text
-	.globl ___truncsipsi2_d2_d0
-	.type  ___truncsipsi2_d2_d0,@function
-___truncsipsi2_d2_d0:
-	add -4,a3
-	mov d2,(a3)
-	mov d3,(2,a3)
-	movx (0,a3),d0
-	add 4,a3
-	rts
-
-	.size ___truncsipsi2_d2_d0,.-___truncsipsi2_d2_d0
-#endif
-
-#ifdef  L_truncsipsi2_d2_d1
-	.text
-	.globl ___truncsipsi2_d2_d1
-	.type  ___truncsipsi2_d2_d1,@function
-___truncsipsi2_d2_d1:
-	add -4,a3
-	mov d2,(a3)
-	mov d3,(2,a3)
-	movx (0,a3),d1
-	add 4,a3
-	rts
-
-	.size ___truncsipsi2_d2_d1,.-___truncsipsi2_d2_d1
-#endif
-
-#ifdef  L_truncsipsi2_d2_d2
-	.text
-	.globl ___truncsipsi2_d2_d2
-	.type  ___truncsipsi2_d2_d2,@function
-___truncsipsi2_d2_d2:
-	add -4,a3
-	mov d2,(a3)
-	mov d3,(2,a3)
-	movx (0,a3),d2
-	add 4,a3
-	rts
-
-	.size ___truncsipsi2_d2_d2,.-___truncsipsi2_d2_d2
-#endif
-
-#ifdef  L_truncsipsi2_d2_d3
-	.text
-	.globl ___truncsipsi2_d2_d3
-	.type  ___truncsipsi2_d2_d3,@function
-___truncsipsi2_d2_d3:
-	add -4,a3
-	mov d2,(a3)
-	mov d3,(2,a3)
-	movx (0,a3),d3
-	add 4,a3
-	rts
-
-	.size ___truncsipsi2_d2_d3,.-___truncsipsi2_d2_d3
-#endif
-
-
-#ifdef  L_cmpsi2
-	.text
-	.globl ___cmpsi2
-	.type  ___cmpsi2,@function
-___cmpsi2:
-	add -4,a3
-	mov a1,(0,a3)
-        mov (10,a3),a1
-        mov (8,a3),a0
-        cmp a1,d1
-        blt .L9
-        bgt .L6
-        cmp a0,d0
-        bcc .L5
-.L9:
-        sub d0,d0
-        jmp .L8
-.L5:
-        cmp a0,d0
-        bhi .L6
-        mov 1,d0
-        jmp .L8
-.L6:
-        mov 2,d0
-.L8:
-	mov (0,a3),a1
-	add 4,a3
-        rts
-	.size ___cmpsi2,.-___cmpsi2
-#endif
-
-#ifdef  L_ucmpsi2
-	.text
-	.globl ___ucmpsi2
-	.type  ___ucmpsi2,@function
-___ucmpsi2:
-	add -4,a3
-	mov a1,(0,a3)
-        mov (10,a3),a1
-        mov (8,a3),a0
-        cmp a1,d1
-        bcs .L9
-        bhi .L6
-        cmp a0,d0
-        bcc .L5
-.L9:
-        sub d0,d0
-        jmp .L8
-.L5:
-        cmp a0,d0
-        bhi .L6
-        mov 1,d0
-        jmp .L8
-.L6:
-        mov 2,d0
-.L8:
-	mov (0,a3),a1
-	add 4,a3
-        rts
-	.size ___ucmpsi2,.-___ucmpsi2
-#endif
-
-
-#ifdef L_prologue
-	.text
-	.globl ___prologue
-	.type ___prologue,@function
-___prologue:
-	mov (0,a3),a0
-	add -16,a3
-	movx d2,(4,a3)
-	movx d3,(8,a3)
-	mov a1,(12,a3)
-	mov a2,(16,a3)
-	mov a0,(0,a3)
-	rts
-	.size ___prologue,.-___prologue
-#endif
-
-#ifdef L_epilogue_a0
-	.text
-	.globl ___epilogue_a0
-	.type ___epilogue_a0,@function
-___epilogue_a0:
-	mov (0,a3),a0
-	movx (4,a3),d2
-	movx (8,a3),d3
-	mov (12,a3),a1
-	mov (16,a3),a2
-	add 16,a3
-	mov a0,(0,a3)
-	rts
-	.size ___epilogue_a0,.-___epilogue_a0
-#endif
-
-#ifdef L_epilogue_d0
-	.text
-	.globl ___epilogue_d0
-	.type ___epilogue_d0,@function
-___epilogue_d0:
-	movx (0,a3),d0
-	movx (4,a3),d2
-	movx (8,a3),d3
-	mov (12,a3),a1
-	mov (16,a3),a2
-	add 16,a3
-	movx d0,(0,a3)
-	rts
-	.size ___epilogue_d0,.-___epilogue_d0
-#endif
-
-#ifdef L_epilogue_noreturn
-	.text
-	.globl ___epilogue_noreturn
-	.type ___epilogue_noreturn,@function
-___epilogue_noreturn:
-	movx (0,a3),d2
-	movx (4,a3),d3
-	mov (8,a3),a1
-	mov (12,a3),a2
-	add 16,a3
-	rts
-	.size ___epilogue_noreturn,.-___epilogue_noreturn
-#endif
diff --git a/gcc/config/mn10200/mn10200.c b/gcc/config/mn10200/mn10200.c
deleted file mode 100755
index 5435f77..0000000
--- a/gcc/config/mn10200/mn10200.c
+++ /dev/null
@@ -1,1532 +0,0 @@
-/* Subroutines for insn-output.c for Matsushita MN10200 series
-   Copyright (C) 1997 Free Software Foundation, Inc.
-   Contributed by Jeff Law (law@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#include "expr.h"
-#include "tree.h"
-#include "obstack.h"
-
-/* Global registers known to hold the value zero.
-
-   Normally we'd depend on CSE and combine to put zero into a
-   register and re-use it.
-
-   However, on the mn10x00 processors we implicitly use the constant
-   zero in tst instructions, so we might be able to do better by
-   loading the value into a register in the prologue, then re-useing
-   that register throughout the function.
-
-   We could perform similar optimizations for other constants, but with
-   gcse due soon, it doesn't seem worth the effort.
-
-   These variables hold a rtx for a register known to hold the value
-   zero throughout the entire function, or NULL if no register of
-   the appropriate class has such a value throughout the life of the
-   function.  */
-rtx zero_dreg;
-rtx zero_areg;
-
-/* Note whether or not we need an out of line epilogue.  */
-static int out_of_line_epilogue;
-
-/* Indicate this file was compiled by gcc and what optimization
-   level was used.  */
-void
-asm_file_start (file)
-     FILE *file;
-{
-  fprintf (file, "#\tGCC For the Matsushita MN10200\n");
-  if (optimize)
-    fprintf (file, "# -O%d\n", optimize);
-  else
-    fprintf (file, "\n\n");
-  output_file_directive (file, main_input_filename);
-}
-
-/* Print operand X using operand code CODE to assembly language output file
-   FILE.  */
-
-void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
-{
-  switch (code)
-    {
-      case 'b':
-      case 'B':
-	/* These are normal and reversed branches.  */
-	switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
-	  {
-	  case NE:
-	    fprintf (file, "ne");
-	    break;
-	  case EQ:
-	    fprintf (file, "eq");
-	    break;
-	  case GE:
-	    fprintf (file, "ge");
-	    break;
-	  case GT:
-	    fprintf (file, "gt");
-	    break;
-	  case LE:
-	    fprintf (file, "le");
-	    break;
-	  case LT:
-	    fprintf (file, "lt");
-	    break;
-	  case GEU:
-	    fprintf (file, "cc");
-	    break;
-	  case GTU:
-	    fprintf (file, "hi");
-	    break;
-	  case LEU:
-	    fprintf (file, "ls");
-	    break;
-	  case LTU:
-	    fprintf (file, "cs");
-	    break;
-	  default:
-	    abort ();
-	  }
-	break;
-      case 'C':
-	/* This is used for the operand to a call instruction;
-	   if it's a REG, enclose it in parens, else output
-	   the operand normally.  */
-	if (GET_CODE (x) == REG)
-	  {
-	    fputc ('(', file);
-	    print_operand (file, x, 0);
-	    fputc (')', file);
-	  }
-	else
-	  print_operand (file, x, 0);
-	break;
-     
-      /* These are the least significant word in a 32bit value.
-	 'o' allows us to sign extend a constant if doing so
-	 makes for more compact code.  */
-      case 'L':
-      case 'o':
-	switch (GET_CODE (x))
-	  {
-	  case MEM:
-	    fputc ('(', file);
-	    output_address (XEXP (x, 0));
-	    fputc (')', file);
-	    break;
-
-	  case REG:
-	    fprintf (file, "%s", reg_names[REGNO (x)]);
-	    break;
-
-	  case SUBREG:
-	    fprintf (file, "%s",
-		     reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]);
-	    break;
-
-	  case CONST_DOUBLE:
-	    if (code == 'L')
-	      {
-		long val;
-		REAL_VALUE_TYPE rv;
-
-		REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-		REAL_VALUE_TO_TARGET_SINGLE (rv, val);
-		print_operand_address (file, GEN_INT (val & 0xffff));
-	      }
-	    else
-	      {
-		long val;
-		REAL_VALUE_TYPE rv;
-
-		REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-		REAL_VALUE_TO_TARGET_SINGLE (rv, val);
-
-		val &= 0xffff;
-		val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000;
-		print_operand_address (file, GEN_INT (val));
-	      }
-	    break;
-
-	  case CONST_INT:
-	    if (code == 'L')
-	      print_operand_address (file, GEN_INT ((INTVAL (x) & 0xffff)));
-	    else
-	      {
-	        unsigned int val = INTVAL (x) & 0xffff;
-		val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000;
-		print_operand_address (file, GEN_INT (val));
-	      }
-	    break;
-	  default:
-	    abort ();
-	  }
-	break;
-
-      /* Similarly, but for the most significant word.  */
-      case 'H':
-      case 'h':
-	switch (GET_CODE (x))
-	  {
-	  case MEM:
-	    fputc ('(', file);
-	    x = adj_offsettable_operand (x, 2);
-	    output_address (XEXP (x, 0));
-	    fputc (')', file);
-	    break;
-
-	  case REG:
-	    fprintf (file, "%s", reg_names[REGNO (x) + 1]);
-	    break;
-
-	  case SUBREG:
-	    fprintf (file, "%s",
-		     reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)] + 1);
-	    break;
-
-	  case CONST_DOUBLE:
-	    if (code == 'H')
-	      {
-		long val;
-		REAL_VALUE_TYPE rv;
-
-		REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-		REAL_VALUE_TO_TARGET_SINGLE (rv, val);
-
-		print_operand_address (file, GEN_INT ((val >> 16) & 0xffff));
-	      }
-	    else
-	      {
-		long val;
-		REAL_VALUE_TYPE rv;
-
-		REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-		REAL_VALUE_TO_TARGET_SINGLE (rv, val);
-
-		val = (val >> 16) & 0xffff;
-		val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000;
-
-		print_operand_address (file, GEN_INT (val));
-	      }
-	    break;
-
-	  case CONST_INT:
-	    if (code == 'H')
-	      print_operand_address (file,
-				     GEN_INT ((INTVAL (x) >> 16) & 0xffff));
-	    else
-	      {
-	        unsigned int val = (INTVAL (x) >> 16) & 0xffff;
-		val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000;
-
-		print_operand_address (file, GEN_INT (val));
-	      }
-	    break;
-	  default:
-	    abort ();
-	  }
-	break;
-
-      /* Output ~CONST_INT.  */
-      case 'N':
-	if (GET_CODE (x) != CONST_INT)
-	  abort ();
-        fprintf (file, "%d", ~INTVAL (x));
-        break;
-
-      /* An address which can not be register indirect, if it is
-	 register indirect, then turn it into reg + disp.  */
-      case 'A':
-	if (GET_CODE (x) != MEM)
-	  abort ();
-	if (GET_CODE (XEXP (x, 0)) == REG)
-	  x = gen_rtx (PLUS, PSImode, XEXP (x, 0), GEN_INT (0));
-	else
-	  x = XEXP (x, 0);
-	fputc ('(', file);
-	output_address (x);
-	fputc (')', file);
-	break;
-
-      case 'Z':
-        print_operand (file, XEXP (x, 1), 0);
-	break;
-
-      /* More cases where we can sign-extend a CONST_INT if it
-	 results in more compact code.  */
-      case 's':
-      case 'S':
-	if (GET_CODE (x) == CONST_INT)
-	  {
-	    int val = INTVAL (x);
-
-	    if (code == 's')
-	      x = GEN_INT (((val & 0xffff) ^ (~0x7fff)) + 0x8000);
-	    else
-	      x = GEN_INT (((val & 0xff) ^ (~0x7f)) + 0x80);
-	  }
-        /* FALL THROUGH */
-      default:
-	switch (GET_CODE (x))
-	  {
-	  case MEM:
-	    fputc ('(', file);
-	    output_address (XEXP (x, 0));
-	    fputc (')', file);
-	    break;
-
-	  case REG:
-	    fprintf (file, "%s", reg_names[REGNO (x)]);
-	    break;
-
-	  case SUBREG:
-	    fprintf (file, "%s",
-		     reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]);
-	    break;
-
-	  case CONST_INT:
-	  case CONST_DOUBLE:
-	  case SYMBOL_REF:
-	  case CONST:
-	  case LABEL_REF:
-	  case CODE_LABEL:
-	    print_operand_address (file, x);
-	    break;
-	  default:
-	    abort ();
-	  }
-	break;
-   }
-}
-
-/* Output assembly language output for the address ADDR to FILE.  */
-
-void
-print_operand_address (file, addr)
-     FILE *file;
-     rtx addr;
-{
-  switch (GET_CODE (addr))
-    {
-    case REG:
-      print_operand (file, addr, 0);
-      break;
-    case PLUS:
-      {
-	rtx base, index;
-	/* The base and index could be in any order, so we have
-	   to figure out which is the base and which is the index.
-	   Uses the same code as GO_IF_LEGITIMATE_ADDRESS.  */
-	if (REG_P (XEXP (addr, 0))
-	    && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
-	  base = XEXP (addr, 0), index = XEXP (addr, 1);
-	else if (REG_P (XEXP (addr, 1))
-	    && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
-	  base = XEXP (addr, 1), index = XEXP (addr, 0);
-      	else
-	  abort ();
-	print_operand (file, index, 0);
-	fputc (',', file);
-	print_operand (file, base, 0);;
-	break;
-      }
-    case SYMBOL_REF:
-      output_addr_const (file, addr);
-      break;
-    default:
-      output_addr_const (file, addr);
-      break;
-    }
-}
-
-/* Count the number of tst insns which compare an address register
-   with zero.  */
-static void 
-count_tst_insns (areg_countp)
-     int *areg_countp;
-{
-  rtx insn;
-
-  /* Assume no tst insns exist.  */
-  *areg_countp = 0;
-
-  /* If not optimizing, then quit now.  */
-  if (!optimize)
-    return;
-
-  /* Walk through all the insns.  */
-  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-    {
-      rtx pat;
-
-      /* Ignore anything that is not a normal INSN.  */
-      if (GET_CODE (insn) != INSN)
-	continue;
-
-      /* Ignore anything that isn't a SET.  */
-      pat = PATTERN (insn);
-      if (GET_CODE (pat) != SET)
-	continue;
-
-      /* Check for a tst insn.  */
-      if (SET_DEST (pat) == cc0_rtx
-	  && GET_CODE (SET_SRC (pat)) == REG
-	  && REGNO_REG_CLASS (REGNO (SET_SRC (pat))) == ADDRESS_REGS)
-	(*areg_countp)++;
-    }
-}
-
-/* Return the total size (in bytes) of the current function's frame.
-   This is the size of the register save area + the size of locals,
-   spills, etc.  */
-int
-total_frame_size ()
-{
-  unsigned int size = get_frame_size ();
-  unsigned int outgoing_args_size = current_function_outgoing_args_size;
-  int i;
-
-  /* First figure out if we're going to use an out of line
-     prologue, if so we have to make space for all the
-     registers, even if we don't use them.  */
-  if (optimize && !current_function_needs_context && !frame_pointer_needed)
-    {
-      int inline_count, outline_count;
-
-      /* Compute how many bytes an inline prologue would take.
-
-         Each address register store takes two bytes, each data register
-	 store takes three bytes.  */
-      inline_count = 0;
-      if (regs_ever_live[5])
-	inline_count += 2;
-      if (regs_ever_live[6])
-	inline_count += 2;
-      if (regs_ever_live[2])
-	inline_count += 3;
-      if (regs_ever_live[3])
-	inline_count += 3;
-
-      /* If this function has any stack, then the stack adjustment
-	 will take two (or more) bytes.  */
-      if (size || outgoing_args_size
-	  || regs_ever_live[5] || regs_ever_live[6]
-	  || regs_ever_live[2] || regs_ever_live[3])
-      inline_count += 2;
-
-      /* Multiply the current count by two and add one to account for the
-	 epilogue insns.  */
-      inline_count = inline_count * 2 + 1;
-    
-      /* Now compute how many bytes an out of line sequence would take.  */
-      /* A relaxed jsr will be three bytes.  */
-      outline_count = 3;
-
-      /* If there are outgoing arguments, then we will need a stack
-	 pointer adjustment after the call to the prologue, two
-	 more bytes.  */
-      outline_count += (outgoing_args_size == 0 ? 0 : 2);
-
-      /* If there is some local frame to allocate, it will need to be
-	 done before the call to the prologue, two more bytes.  */
-      if (get_frame_size () != 0)
-	outline_count += 2;
-
-      /* Now account for the epilogue, multiply the base count by two,
-	 then deal with optimizing away the rts instruction.  */
-      outline_count = outline_count * 2 + 1;
-
-      if (get_frame_size () == 0 && outgoing_args_size == 0)
-	outline_count -= 1;
-
-      /* If an out of line prologue is smaller, use it.  */
-      if (inline_count > outline_count)
-	return size + outgoing_args_size + 16;
-    }
-
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      if (regs_ever_live[i] && !call_used_regs[i] && ! fixed_regs[i]
-	  || (i == FRAME_POINTER_REGNUM && frame_pointer_needed))
-	size += 4;
-    }
-
-  return (size + outgoing_args_size);
-}
-
-/* Expand the prologue into RTL.  */
-void
-expand_prologue ()
-{
-  unsigned int size = total_frame_size ();
-  unsigned int outgoing_args_size = current_function_outgoing_args_size;
-  int offset, i;
-
-  zero_areg = NULL_RTX;
-  zero_dreg = NULL_RTX;
-
-  /* If optimizing, see if we should do an out of line prologue/epilogue
-     sequence.
-
-     We don't support out of line prologues if the current function
-     needs a context or frame pointer.  */
-  if (optimize && !current_function_needs_context && !frame_pointer_needed)
-    {
-      int inline_count, outline_count, areg_count;
-
-      /* We need to end the current sequence so that count_tst_insns can
-	 look at all the insns in this function.  Normally this would be
-	 unsafe, but it's OK in the prologue/epilogue expanders.  */
-      end_sequence ();
-
-      /* Get a count of the number of tst insns which use address
-	 registers (it's not profitable to try and improve tst insns
-	 which use data registers).  */
-      count_tst_insns (&areg_count);
-
-      /* Now start a new sequence.  */
-      start_sequence ();
-
-      /* Compute how many bytes an inline prologue would take.
-
-         Each address register store takes two bytes, each data register
-	 store takes three bytes.  */
-      inline_count = 0;
-      if (regs_ever_live[5])
-	inline_count += 2;
-      if (regs_ever_live[6])
-	inline_count += 2;
-      if (regs_ever_live[2])
-	inline_count += 3;
-      if (regs_ever_live[3])
-	inline_count += 3;
-
-      /* If this function has any stack, then the stack adjustment
-	 will take two (or more) bytes.  */
-      if (size || outgoing_args_size
-	  || regs_ever_live[5] || regs_ever_live[6]
-	  || regs_ever_live[2] || regs_ever_live[3])
-      inline_count += 2;
-
-      /* Multiply the current count by two and add one to account for the
-	 epilogue insns.  */
-      inline_count = inline_count * 2 + 1;
-    
-      /* Now compute how many bytes an out of line sequence would take.  */
-      /* A relaxed jsr will be three bytes.  */
-      outline_count = 3;
-
-      /* If there are outgoing arguments, then we will need a stack
-	 pointer adjustment after the call to the prologue, two
-	 more bytes.  */
-      outline_count += (outgoing_args_size == 0 ? 0 : 2);
-
-      /* If there is some local frame to allocate, it will need to be
-	 done before the call to the prologue, two more bytes.  */
-      if (get_frame_size () != 0)
-	outline_count += 2;
-
-      /* Now account for the epilogue, multiply the base count by two,
-	 then deal with optimizing away the rts instruction.  */
-      outline_count = outline_count * 2 + 1;
-
-      if (get_frame_size () == 0 && outgoing_args_size == 0)
-	outline_count -= 1;
-     
-      /* If an out of line prologue is smaller, use it.  */
-      if (inline_count > outline_count)
-	{
-	  if (get_frame_size () != 0)
-	    emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
-				    GEN_INT (-size + outgoing_args_size + 16)));
-	  emit_insn (gen_outline_prologue_call ());
-
-	  if (outgoing_args_size)
-	    emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
-				    GEN_INT (-outgoing_args_size)));
-	
-	  out_of_line_epilogue = 1;
-
-	  /* Determine if it is profitable to put the value zero into a register
-	     for the entire function.  If so, set ZERO_DREG and ZERO_AREG.  */
-
-	  /* First see if we could load the value into a data register
-	     since that's the most efficient way.  */
-	  if (areg_count > 1
-	      && (!regs_ever_live[2] || !regs_ever_live[3]))
-	    {
-	      if (!regs_ever_live[2])
-		{
-		  regs_ever_live[2] = 1;
-		  zero_dreg = gen_rtx (REG, HImode, 2);
-		}
-	      if (!regs_ever_live[3])
-		{
-		  regs_ever_live[3] = 1;
-		  zero_dreg = gen_rtx (REG, HImode, 3);
-		}
-	    }
-
-	  /* Now see if we could load the value into a address register.  */
-	  if (zero_dreg == NULL_RTX
-	      && areg_count > 2
-	      && (!regs_ever_live[5] || !regs_ever_live[6]))
-	    {
-	      if (!regs_ever_live[5])
-		{
-		  regs_ever_live[5] = 1;
-		  zero_areg = gen_rtx (REG, HImode, 5);
-		}
-	      if (!regs_ever_live[6])
-		{
-		  regs_ever_live[6] = 1;
-		  zero_areg = gen_rtx (REG, HImode, 6);
-		}
-	    }
-
-	  if (zero_dreg)
-	    emit_move_insn (zero_dreg, const0_rtx);
-
-	  if (zero_areg)
-	    emit_move_insn (zero_areg, const0_rtx);
-
-	  return;
-	}
-    }
-
-  out_of_line_epilogue = 0;
-
-  /* Temporarily stuff the static chain onto the stack so we can
-     use a0 as a scratch register during the prologue.  */
-  if (current_function_needs_context)
-    {
-      emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
-			      GEN_INT (-4)));
-      emit_move_insn (gen_rtx (MEM, PSImode, stack_pointer_rtx),
-		      gen_rtx (REG, PSImode, STATIC_CHAIN_REGNUM));
-    }
-
-  if (frame_pointer_needed)
-    {
-      /* Store a2 into a0 temporarily.  */
-      emit_move_insn (gen_rtx (REG, PSImode, 4), frame_pointer_rtx);
-
-      /* Set up the frame pointer.  */
-      emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
-    }
-
-  /* Make any necessary space for the saved registers and local frame.  */
-  if (size)
-    emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
-			    GEN_INT (-size)));
-
-  /* Save the callee saved registers.  They're saved into the top
-     of the frame, using the stack pointer.  */
-  for (i = 0, offset = outgoing_args_size;
-       i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      if (regs_ever_live[i] && !call_used_regs[i] && ! fixed_regs[i]
-	  || (i == FRAME_POINTER_REGNUM && frame_pointer_needed))
-	{
-	  int regno;
-
-	  /* If we're saving the frame pointer, then it will be found in
-	     register 4 (a0).  */
-	  regno = (i == FRAME_POINTER_REGNUM && frame_pointer_needed) ? 4 : i;
-	
-	  emit_move_insn (gen_rtx (MEM, PSImode,
-				   gen_rtx (PLUS, Pmode,
-					    stack_pointer_rtx,
-					    GEN_INT (offset))),
-			  gen_rtx (REG, PSImode, regno));
-	  offset += 4;
-	}
-    }
-
-  /* Now put the static chain back where the rest of the function
-     expects to find it.  */
-  if (current_function_needs_context)
-    {
-      emit_move_insn (gen_rtx (REG, PSImode, STATIC_CHAIN_REGNUM),
-		      gen_rtx (MEM, PSImode,
-			       gen_rtx (PLUS, PSImode, stack_pointer_rtx,
-					GEN_INT (size))));
-    }
-}
-
-/* Expand the epilogue into RTL.  */
-void
-expand_epilogue ()
-{
-  unsigned int size;
-  unsigned int outgoing_args_size = current_function_outgoing_args_size;
-  int offset, i, temp_regno;
-  rtx basereg;
-
-  size = total_frame_size ();
-
-  if (DECL_RESULT (current_function_decl)
-      && DECL_RTL (DECL_RESULT (current_function_decl))
-      && REG_P (DECL_RTL (DECL_RESULT (current_function_decl))))
-    temp_regno = (REGNO (DECL_RTL (DECL_RESULT (current_function_decl))) == 4
-		  ? 0 : 4);
-  else
-    temp_regno = 4;
-
-  /* Emit an out of line epilogue sequence if it's profitable to do so.  */
-  if (out_of_line_epilogue)
-    {
-      /* If there were no outgoing arguments and no local frame, then
-	 we will be able to omit the rts at the end of this function,
-	 so just jump to the epilogue_noreturn routine.  */
-      if (get_frame_size () == 0 && outgoing_args_size == 0)
-	{
-	  emit_jump_insn (gen_outline_epilogue_jump ());
-	  return;
-	}
-
-      if (outgoing_args_size)
-	emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
-				GEN_INT (outgoing_args_size)));
-
-      if (temp_regno == 0)
-	emit_insn (gen_outline_epilogue_call_d0 ());
-      else if (temp_regno == 4)
-	emit_insn (gen_outline_epilogue_call_a0 ());
-
-      if (get_frame_size () != 0)
-	emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
-				GEN_INT (size - outgoing_args_size - 16)));
-      emit_jump_insn (gen_return_internal ());
-      return;
-    }
-
-  /* Registers are restored from the frame pointer if we have one,
-     else they're restored from the stack pointer.  Figure out
-     the appropriate offset to the register save area for both cases.  */
-  if (frame_pointer_needed)
-    {
-      basereg = frame_pointer_rtx;
-      offset = -(size - outgoing_args_size);
-    }
-  else
-    {
-      basereg = stack_pointer_rtx;
-      offset = outgoing_args_size;
-    }
-
-  /* Restore each register.  */
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      if (regs_ever_live[i] && !call_used_regs[i] && ! fixed_regs[i]
-	  || (i == FRAME_POINTER_REGNUM && frame_pointer_needed))
-	{
-	  int regno;
-
-	  /* Restore the frame pointer (if it exists) into a temporary
-	     register.  */
-	  regno = ((i == FRAME_POINTER_REGNUM && frame_pointer_needed)
-		   ? temp_regno : i);
-	
-	  emit_move_insn (gen_rtx (REG, PSImode, regno),
-			  gen_rtx (MEM, PSImode,
-				   gen_rtx (PLUS, Pmode,
-					    basereg,
-					    GEN_INT (offset))));
-	  offset += 4;
-	}
-    }
-
-  if (frame_pointer_needed)
-    {
-      /* Deallocate this frame's stack.  */
-      emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
-      /* Restore the old frame pointer.  */
-      emit_move_insn (frame_pointer_rtx, gen_rtx (REG, PSImode, temp_regno));
-    }
-  else if (size)
-    {
-      /* Deallocate this function's stack.  */
-      emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx,
-			      GEN_INT (size)));
-    }
-
-  /* If we had to allocate a slot to save the context pointer,
-     then it must be deallocated here.  */
-  if (current_function_needs_context)
-    emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (4)));
-
-  /* Emit the return insn, if this function had no stack, then we
-     can use the standard return (which allows more optimizations),
-     else we have to use the special one which inhibits optimizations.  */
-  if (size == 0 && !current_function_needs_context)
-    emit_jump_insn (gen_return ());
-  else
-    emit_jump_insn (gen_return_internal ());
-}
-
-/* Update the condition code from the insn.  */
-
-void
-notice_update_cc (body, insn)
-     rtx body;
-     rtx insn;
-{
-  switch (get_attr_cc (insn))
-    {
-    case CC_NONE:
-      /* Insn does not affect CC at all.  */
-      break;
-
-    case CC_NONE_0HIT:
-      /* Insn does not change CC, but the 0'th operand has been changed.  */
-      if (cc_status.value1 != 0
-	  && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1))
-	cc_status.value1 = 0;
-      break;
-
-    case CC_SET_ZN:
-      /* Insn sets the Z,N flags of CC to recog_operand[0].
-	 V,C is in an unusable state.  */
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
-      cc_status.value1 = recog_operand[0];
-      break;
-
-    case CC_SET_ZNV:
-      /* Insn sets the Z,N,V flags of CC to recog_operand[0].
-	 C is in an unusable state.  */
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_NO_CARRY;
-      cc_status.value1 = recog_operand[0];
-      break;
-
-    case CC_COMPARE:
-      /* The insn is a compare instruction.  */
-      CC_STATUS_INIT;
-      cc_status.value1 = SET_SRC (body);
-      break;
-
-    case CC_CLOBBER:
-      /* Insn doesn't leave CC in a usable state.  */
-      CC_STATUS_INIT;
-      break;
-
-    default:
-      CC_STATUS_INIT;
-      break;
-    }
-}
-
-/* Return true if OP is a valid call operand.  Valid call operands
-   are SYMBOL_REFs and REGs.  */
-int
-call_address_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
-}
-
-/* Return true if OP is a memory operand with a constant address.
-   A special PSImode move pattern uses this predicate.  */
-int
-constant_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return GET_CODE (op) == MEM && CONSTANT_ADDRESS_P (XEXP (op, 0));
-}
-
-/* What (if any) secondary registers are needed to move IN with mode
-   MODE into a register from in register class CLASS. 
-
-   We might be able to simplify this.  */
-enum reg_class
-secondary_reload_class (class, mode, in, input)
-     enum reg_class class;
-     enum machine_mode mode;
-     rtx in;
-     int input;
-{
-  int regno;
-
-  /* Memory loads less than a full word wide can't have an
-     address or stack pointer destination.  They must use
-     a data register as an intermediate register.  */
-  if (input
-      && GET_CODE (in) == MEM
-      && (mode == QImode)
-      && class == ADDRESS_REGS)
-    return DATA_REGS;
-
-  /* Address register stores which are not PSImode need a scratch register.  */
-  if (! input
-      && GET_CODE (in) == MEM
-      && (mode != PSImode)
-      && class == ADDRESS_REGS)
-    return DATA_REGS;
-
-  /* Otherwise assume no secondary reloads are needed.  */
-  return NO_REGS;
-}
-
-
-/* Shifts.
-
-   We devote a fair bit of code to getting efficient shifts since we can only
-   shift one bit at a time, and each single bit shift may take multiple
-   instructions.
-
-   The basic shift methods:
-
-     * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
-     this is the default.  SHIFT_LOOP
-
-     * inlined shifts -- emit straight line code for the shift; this is
-     used when a straight line shift is about the same size or smaller
-     than a loop.  We allow the inline version to be slightly longer in
-     some cases as it saves a register.  SHIFT_INLINE
-
-     * There other oddballs.  Not worth explaining.  SHIFT_SPECIAL
-
-
-   HImode shifts:
-
-     1-4    do them inline
-
-     5-7    If ashift, then multiply, else loop.
-	
-     8-14 - If ashift, then multiply, if lshiftrt, then divide, else loop.
-     15   - rotate the bit we want into the carry, clear the destination,
-	    (use mov 0,dst, not sub as sub will clobber the carry), then
-	    move bit into place.
-
-   Don't Panic, it's not nearly as bad as the H8 shifting code!!!  */
-
-int
-nshift_operator (x, mode)
-     rtx x;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (x))
-    {
-    case ASHIFTRT:
-    case LSHIFTRT:
-    case ASHIFT:
-      return 1;
-
-    default:
-      return 0;
-    }
-}
-
-/* Called from the .md file to emit code to do shifts.
-   Returns a boolean indicating success
-   (currently this is always TRUE).  */
-
-int
-expand_a_shift (mode, code, operands)
-     enum machine_mode mode;
-     int code;
-     rtx operands[];
-{
-  emit_move_insn (operands[0], operands[1]);
-
-  /* need a loop to get all the bits we want  - we generate the
-     code at emit time, but need to allocate a scratch reg now  */
-
-  emit_insn (gen_rtx
-	     (PARALLEL, VOIDmode,
-	      gen_rtvec (2,
-			 gen_rtx (SET, VOIDmode, operands[0],
-				  gen_rtx (code, mode,
-					   operands[0], operands[2])),
-			 gen_rtx (CLOBBER, VOIDmode,
-				  gen_rtx (SCRATCH, HImode, 0)))));
-
-  return 1;
-}
-
-/* Shift algorithm determination.
-
-   There are various ways of doing a shift:
-   SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
-                 shifts as we need.
-   SHIFT_SPECIAL: Hand crafted assembler.
-   SHIFT_LOOP:    If the above methods fail, just loop.  */
-
-enum shift_alg
-{
-  SHIFT_INLINE,
-  SHIFT_SPECIAL,
-  SHIFT_LOOP,
-  SHIFT_MAX
-};
-
-/* Symbols of the various shifts which can be used as indices.  */
-
-enum shift_type
-  {
-    SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
-  };
-
-/* Symbols of the various modes which can be used as indices.  */
-
-enum shift_mode
-  {
-    HIshift, 
-  };
-
-/* For single bit shift insns, record assembler and what bits of the
-   condition code are valid afterwards (represented as various CC_FOO
-   bits, 0 means CC isn't left in a usable state).  */
-
-struct shift_insn
-{
-  char *assembler;
-  int cc_valid;
-};
-
-/* Assembler instruction shift table.
-
-   These tables are used to look up the basic shifts.
-   They are indexed by cpu, shift_type, and mode.
-*/
-
-static const struct shift_insn shift_one[3][3] =
-{
-  {
-/* SHIFT_ASHIFT */
-      { "add\t%0,%0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
-  },
-/* SHIFT_LSHIFTRT */
-  {
-      { "lsr\t%0", CC_NO_CARRY },
-  },
-/* SHIFT_ASHIFTRT */
-  {
-      { "asr\t%0", CC_NO_CARRY },
-  },
-};
-
-/* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
-   algorithm for doing the shift.  The assembler code is stored in ASSEMBLER.
-   We don't achieve maximum efficiency in all cases, but the hooks are here
-   to do so.
-
-   For now we just use lots of switch statements.  Since we don't even come
-   close to supporting all the cases, this is simplest.  If this function ever
-   gets too big, perhaps resort to a more table based lookup.  Of course,
-   at this point you may just wish to do it all in rtl.  */
-
-static enum shift_alg
-get_shift_alg (shift_type, mode, count, assembler_p, cc_valid_p)
-     enum shift_type shift_type;
-     enum machine_mode mode;
-     int count;
-     const char **assembler_p;
-     int *cc_valid_p;
-{
-  /* The default is to loop.  */
-  enum shift_alg alg = SHIFT_LOOP;
-  enum shift_mode shift_mode;
-
-  /* We don't handle negative shifts or shifts greater than the word size,
-     they should have been handled already.  */
-
-  if (count < 0 || count > GET_MODE_BITSIZE (mode))
-    abort ();
-
-  switch (mode)
-    {
-    case HImode:
-      shift_mode = HIshift;
-      break;
-    default:
-      abort ();
-    }
-
-  /* Assume either SHIFT_LOOP or SHIFT_INLINE.
-     It is up to the caller to know that looping clobbers cc.  */
-  *assembler_p = shift_one[shift_type][shift_mode].assembler;
-  *cc_valid_p = shift_one[shift_type][shift_mode].cc_valid;
-
-  /* Now look for cases we want to optimize.  */
-
-  switch (shift_mode)
-    {
-    case HIshift:
-      if (count <= 4)
-	return SHIFT_INLINE;
-      else if (count < 15 && shift_type != SHIFT_ASHIFTRT)
-	{
-	  switch (count)
-	    {
-	    case 5:
-	      if (shift_type == SHIFT_ASHIFT)
-		*assembler_p = "mov 32,%4\n\tmul %4,%0";
-	      else if (shift_type == SHIFT_LSHIFTRT)
-		*assembler_p
-		  = "sub %4,%4\n\tmov %4,mdr\n\tmov 32,%4\n\tdivu %4,%0";
-	      *cc_valid_p = CC_NO_CARRY;
-	      return SHIFT_SPECIAL;
-	    case 6:
-	      if (shift_type == SHIFT_ASHIFT)
-		*assembler_p = "mov 64,%4\n\tmul %4,%0";
-	      else if (shift_type == SHIFT_LSHIFTRT)
-		*assembler_p
-		  = "sub %4,%4\n\tmov %4,mdr\n\tmov 64,%4\n\tdivu %4,%0";
-	      *cc_valid_p = CC_NO_CARRY;
-	      return SHIFT_SPECIAL;
-	    case 7:
-	      if (shift_type == SHIFT_ASHIFT)
-		*assembler_p = "mov 128,%4\n\tmul %4,%0";
-	      else if (shift_type == SHIFT_LSHIFTRT)
-		*assembler_p
-		  = "sub %4,%4\n\tmov %4,mdr\n\tmov 128,%4\n\tdivu %4,%0";
-	      *cc_valid_p = CC_NO_CARRY;
-	      return SHIFT_SPECIAL;
-	    case 8:
-	      if (shift_type == SHIFT_ASHIFT)
-		*assembler_p = "mov 256,%4\n\tmul %4,%0";
-	      else if (shift_type == SHIFT_LSHIFTRT)
-		*assembler_p
-		  = "sub %4,%4\n\tmov %4,mdr\n\tmov 256,%4\n\tdivu %4,%0";
-	      *cc_valid_p = CC_NO_CARRY;
-	      return SHIFT_SPECIAL;
-	    case 9:
-	      if (shift_type == SHIFT_ASHIFT)
-		*assembler_p = "mov 512,%4\n\tmul %4,%0";
-	      else if (shift_type == SHIFT_LSHIFTRT)
-		*assembler_p
-		  = "sub %4,%4\n\tmov %4,mdr\n\tmov 512,%4\n\tdivu %4,%0";
-	      *cc_valid_p = CC_NO_CARRY;
-	      return SHIFT_SPECIAL;
-	    case 10:
-	      if (shift_type == SHIFT_ASHIFT)
-		*assembler_p = "mov 1024,%4\n\tmul %4,%0";
-	      else if (shift_type == SHIFT_LSHIFTRT)
-		*assembler_p
-		  = "sub %4,%4\n\tmov %4,mdr\n\tmov 1024,%4\n\tdivu %4,%0";
-	      *cc_valid_p = CC_NO_CARRY;
-	      return SHIFT_SPECIAL;
-	    case 11:
-	      if (shift_type == SHIFT_ASHIFT)
-		*assembler_p = "mov 2048,%4\n\tmul %4,%0";
-	      else if (shift_type == SHIFT_LSHIFTRT)
-		*assembler_p
-		  = "sub %4,%4\n\tmov %4,mdr\n\tmov 2048,%4\n\tdivu %4,%0";
-	      *cc_valid_p = CC_NO_CARRY;
-	      return SHIFT_SPECIAL;
-	    case 12:
-	      if (shift_type == SHIFT_ASHIFT)
-		*assembler_p = "mov 4096,%4\n\tmul %4,%0";
-	      else if (shift_type == SHIFT_LSHIFTRT)
-		*assembler_p
-		  = "sub %4,%4\n\tmov %4,mdr\n\tmov 4096,%4\n\tdivu %4,%0";
-	      *cc_valid_p = CC_NO_CARRY;
-	      return SHIFT_SPECIAL;
-	    case 13:
-	      if (shift_type == SHIFT_ASHIFT)
-		*assembler_p = "mov 8192,%4\n\tmul %4,%0";
-	      else if (shift_type == SHIFT_LSHIFTRT)
-		*assembler_p
-		  = "sub %4,%4\n\tmov %4,mdr\n\tmov 8192,%4\n\tdivu %4,%0";
-	      *cc_valid_p = CC_NO_CARRY;
-	      return SHIFT_SPECIAL;
-	    case 14:
-	      if (shift_type == SHIFT_ASHIFT)
-		*assembler_p = "mov 16384,%4\n\tmul %4,%0";
-	      else if (shift_type == SHIFT_LSHIFTRT)
-		*assembler_p
-		  = "sub %4,%4\n\tmov %4,mdr\n\tmov 16384,%4\n\tdivu %4,%0";
-	      *cc_valid_p = CC_NO_CARRY;
-	      return SHIFT_SPECIAL;
-	    }
-	}
-      else if (count == 15)
-	{
-          if (shift_type == SHIFT_ASHIFTRT)
-            {
-              *assembler_p = "add\t%0,%0\n\tsubc\t%0,%0\n";
-              *cc_valid_p = CC_NO_CARRY;
-              return SHIFT_SPECIAL;
-	    }
-          if (shift_type == SHIFT_LSHIFTRT)
-            {
-              *assembler_p = "add\t%0,%0\n\tmov 0,%0\n\trol %0\n";
-              *cc_valid_p = CC_NO_CARRY;
-              return SHIFT_SPECIAL;
-	    }
-          if (shift_type == SHIFT_ASHIFT)
-            {
-              *assembler_p = "ror\t%0\n\tmov 0,%0\n\tror %0\n";
-              *cc_valid_p = CC_NO_CARRY;
-              return SHIFT_SPECIAL;
-	    }
-	}
-      break;
-
-    default:
-      abort ();
-    }
-
-  return alg;
-}
-
-/* Emit the assembler code for doing shifts.  */
-
-char *
-emit_a_shift (insn, operands)
-     rtx insn;
-     rtx *operands;
-{
-  static int loopend_lab;
-  char *assembler;
-  int cc_valid;
-  rtx inside = PATTERN (insn);
-  rtx shift = operands[3];
-  enum machine_mode mode = GET_MODE (shift);
-  enum rtx_code code = GET_CODE (shift);
-  enum shift_type shift_type;
-  enum shift_mode shift_mode;
-
-  loopend_lab++;
-
-  switch (mode)
-    {
-    case HImode:
-      shift_mode = HIshift;
-      break;
-    default:
-      abort ();
-    }
-
-  switch (code)
-    {
-    case ASHIFTRT:
-      shift_type = SHIFT_ASHIFTRT;
-      break;
-    case LSHIFTRT:
-      shift_type = SHIFT_LSHIFTRT;
-      break;
-    case ASHIFT:
-      shift_type = SHIFT_ASHIFT;
-      break;
-    default:
-      abort ();
-    }
-
-  if (GET_CODE (operands[2]) != CONST_INT)
-    {
-      /* Indexing by reg, so have to loop and test at top */
-      output_asm_insn ("mov	%2,%4", operands);
-      output_asm_insn ("cmp	0,%4", operands);
-      fprintf (asm_out_file, "\tble	.Lle%d\n", loopend_lab);
-
-      /* Get the assembler code to do one shift.  */
-      get_shift_alg (shift_type, mode, 1, &assembler, &cc_valid);
-    }
-  else
-    {
-      int n = INTVAL (operands[2]);
-      enum shift_alg alg;
-
-      /* If the count is negative, make it 0.  */
-      if (n < 0)
-	n = 0;
-      /* If the count is too big, truncate it.
-         ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
-	 do the intuitive thing.  */
-      else if (n > GET_MODE_BITSIZE (mode))
-	n = GET_MODE_BITSIZE (mode);
-
-      alg = get_shift_alg (shift_type, mode, n, &assembler, &cc_valid);
-
-
-      switch (alg)
-	{
-	case SHIFT_INLINE:
-	  /* Emit one bit shifts.  */
-	  while (n > 0)
-	    {
-	      output_asm_insn (assembler, operands);
-	      n -= 1;
-	    }
-
-	  /* Keep track of CC.  */
-	  if (cc_valid)
-	    {
-	      cc_status.value1 = operands[0];
-	      cc_status.flags |= cc_valid;
-	    }
-	  return "";
-
-	case SHIFT_SPECIAL:
-	  output_asm_insn (assembler, operands);
-
-	  /* Keep track of CC.  */
-	  if (cc_valid)
-	    {
-	      cc_status.value1 = operands[0];
-	      cc_status.flags |= cc_valid;
-	    }
-	  return "";
-	}
-
-	{
-	  fprintf (asm_out_file, "\tmov	%d,%s\n", n,
-		   reg_names[REGNO (operands[4])]);
-	  fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
-	  output_asm_insn (assembler, operands);
-	  output_asm_insn ("add	-1,%4", operands);
-	  fprintf (asm_out_file, "\tbne	.Llt%d\n", loopend_lab);
-	  return "";
-	}
-    }
-
-  fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
-  output_asm_insn (assembler, operands);
-  output_asm_insn ("add	-1,%4", operands);
-  fprintf (asm_out_file, "\tbne	.Llt%d\n", loopend_lab);
-  fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
-
-  return "";
-}
-
-/* Return an RTX to represent where a value with mode MODE will be returned
-   from a function.  If the result is 0, the argument is pushed.  */
-
-rtx
-function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  rtx result = 0;
-  int size, align;
-
-  /* We only support using 2 data registers as argument registers.  */
-  int nregs = 2;
-
-  /* Only pass named arguments in registers.  */
-  if (!named)
-    return NULL_RTX;
-
-  /* Figure out the size of the object to be passed.  We lie and claim
-     PSImode values are only two bytes since they fit in a single
-     register.  */
-  if (mode == BLKmode)
-    size = int_size_in_bytes (type);
-  else if (mode == PSImode)
-    size = 2;
-  else
-    size = GET_MODE_SIZE (mode);
-
-  /* Figure out the alignment of the object to be passed.  */
-    align = size;
-
-  cum->nbytes = (cum->nbytes + 1) & ~1;
-
-  /* Don't pass this arg via a register if all the argument registers
-     are used up.  */
-  if (cum->nbytes + size > nregs * UNITS_PER_WORD)
-    return 0;
-
-  switch (cum->nbytes / UNITS_PER_WORD)
-    {
-    case 0:
-      result = gen_rtx (REG, mode, 0);
-      break;
-    case 1:
-      result = gen_rtx (REG, mode, 1);
-      break;
-    default:
-      result = 0;
-    }
-
-  return result;
-}
-
-/* Return the number of registers to use for an argument passed partially
-   in registers and partially in memory.  */
-
-int
-function_arg_partial_nregs (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int size, align;
-
-  /* We only support using 2 data registers as argument registers.  */
-  int nregs = 2;
-
-  return 0;
-  /* Only pass named arguments in registers.  */
-  if (!named)
-    return 0;
-
-  /* Figure out the size of the object to be passed.  */
-  if (mode == BLKmode)
-    size = int_size_in_bytes (type);
-  else if (mode == PSImode)
-    size = 2;
-  else
-    size = GET_MODE_SIZE (mode);
-
-  /* Figure out the alignment of the object to be passed.  */
-  align = size;
-
-  cum->nbytes = (cum->nbytes + 1) & ~1;
-
-  /* Don't pass this arg via a register if all the argument registers
-     are used up.  */
-  if (cum->nbytes > nregs * UNITS_PER_WORD)
-    return 0;
-
-  if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
-    return 0;
-
-  /* Don't pass this arg via a register if it would be split between
-     registers and memory.  */
-  if (type == NULL_TREE
-      && cum->nbytes + size > nregs * UNITS_PER_WORD)
-    return 0;
-
-  return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
-}
-
-char *
-output_tst (operand, insn)
-     rtx operand, insn;
-{
-  
-  rtx temp;
-  int past_call = 0;
-
-  /* Only tst insns using address registers can be optimized.  */
-  if (REGNO_REG_CLASS (REGNO (operand)) != ADDRESS_REGS)
-    return "cmp 0,%0";
-
-  /* If testing an address register against zero, we can do better if
-     we know there's a register already holding the value zero.  First
-     see if a global register has been set to zero, else we do a search
-     for a register holding zero, if both of those fail, then we use a
-     compare against zero.  */
-  if (zero_dreg || zero_areg)
-    {
-      rtx xoperands[2];
-      xoperands[0] = operand;
-      xoperands[1] = zero_dreg ? zero_dreg : zero_areg;
-
-      output_asm_insn ("cmp %1,%0", xoperands);
-      return "";
-    }
-
-  /* We can save a byte if we can find a register which has the value
-     zero in it.  */
-  temp = PREV_INSN (insn);
-  while (temp)
-    {
-      rtx set;
-
-      /* We allow the search to go through call insns.  We record
-	 the fact that we've past a CALL_INSN and reject matches which
-	 use call clobbered registers.  */
-      if (GET_CODE (temp) == CODE_LABEL
-	  || GET_CODE (temp) == JUMP_INSN
-	  || GET_CODE (temp) == BARRIER)
-	break;
-
-      if (GET_CODE (temp) == CALL_INSN)
-	past_call = 1;
-
-      if (GET_CODE (temp) == NOTE)
-	{
-	  temp = PREV_INSN (temp);
-	  continue;
-	}
-
-      /* It must be an insn, see if it is a simple set. */
-      set = single_set (temp);
-      if (!set)
-	{
-	  temp = PREV_INSN (temp);
-	  continue;
-	}
-
-      /* Are we setting a register to zero?
-
-	 If it's a call clobbered register, have we past a call?  */
-      if (REG_P (SET_DEST (set))
-	  && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
-	  && !reg_set_between_p (SET_DEST (set), temp, insn)
-	  && (!past_call 
-	      || !call_used_regs[REGNO (SET_DEST (set))]))
-	{
-	  rtx xoperands[2];
-	  xoperands[0] = operand;
-	  xoperands[1] = SET_DEST (set);
-
-	  output_asm_insn ("cmp %1,%0", xoperands);
-	  return "";
-	}
-      temp = PREV_INSN (temp);
-    }
-  return "cmp 0,%0";
-}
-
-/* Return nonzero if OP is a valid operand for a {zero,sign}_extendpsisi
-   instruction.
-
-   It accepts anything that is a general operand or the sum of the
-   stack pointer and a general operand.  */
-extendpsi_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (general_operand (op, mode)
-	  || (GET_CODE (op) == PLUS
-	      && XEXP (op, 0) == stack_pointer_rtx
-	      && general_operand (XEXP (op, 1), VOIDmode)));
-}
diff --git a/gcc/config/mn10200/mn10200.h b/gcc/config/mn10200/mn10200.h
deleted file mode 100755
index d2b474d..0000000
--- a/gcc/config/mn10200/mn10200.h
+++ /dev/null
@@ -1,1078 +0,0 @@
-/* Definitions of target machine for GNU compiler. Matsushita MN10200 series
-   Copyright (C) 1997 Free Software Foundation, Inc.
-   Contributed by Jeff Law (law@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "svr4.h"
-
-/* Get rid of svr4.h stuff we don't want/need.  */
-#undef ASM_SPEC
-#undef ASM_FINAL_SPEC
-#undef LIB_SPEC
-#undef ENDFILE_SPEC
-#undef LINK_SPEC
-#undef STARTFILE_SPEC
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-D__mn10200__ -D__MN10200__ -D__LONG_MAX__=2147483647L -D__LONG_LONG_MAX__=2147483647L -D__INT_MAX__=32767"
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-/* We don't have any switched on the mn10200.  Though there are some things
-   that might be worth a switch:
-
-   -mspace to optimize even more for space.
-
-   -mrelax to enable the relaxing linker.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  {{ "", TARGET_DEFAULT}}
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 0
-#endif
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fprintf (stderr, " (MN10200)");
-
-
-/* Target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is not true on the Matsushita MN10300.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* This is not true on the Matsushita MN10200.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered.
-   This is not true on the Matsushita MN10200.  */
-#define WORDS_BIG_ENDIAN 0
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.
-
-   This is a white lie.  Registers are really 24bits, but most operations
-   only operate on 16 bits.   GCC chokes badly if we set this to a value
-   that is not a power of two.  */
-#define BITS_PER_WORD		16
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD		2
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.
-
-   This differs from Pmode because we need to allocate 32bits of space
-   to hold the 24bit pointers on this machine.  */
-#define POINTER_SIZE 		32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY		16
-
-/* The stack goes in 16 bit lumps.  */
-#define STACK_BOUNDARY 		16
-
-/* Allocation boundary (in *bits*) for the code of a function.
-   8 is the minimum boundary; it's unclear if bigger alignments
-   would improve performance.  */
-#define FUNCTION_BOUNDARY 8
-
-/* No data type wants to be aligned rounder than this.   */
-#define BIGGEST_ALIGNMENT	16
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* Seems to be how the Matsushita compiler does things, and there's
-   no real reason to be different.  */
-#define STRUCTURE_SIZE_BOUNDARY 16
-#undef PCC_BITFIELD_TYPE_MATTERS
-
-/* Define this if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   XXX Long term we should probably expose the MDR register, we use
-   it for division, multiplication, and some extension operations.  */
-
-#define FIRST_PSEUDO_REGISTER 8
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.  */
-
-#define FIXED_REGISTERS \
-  { 0, 0, 0, 0, 0, 0, 0, 1}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you
-   like.  */
-
-#define CALL_USED_REGISTERS \
-  { 1, 1, 0, 0, 1, 0, 0, 1}
-
-#define REG_ALLOC_ORDER \
-  { 0, 1, 4, 2, 3, 5, 6, 7}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((MODE) == PSImode ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
-			    / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
-   MODE.
-
-   We allow any register to hold a PSImode value.  We allow any register
-   to hold values <= 16 bits.  For values > 16 bits we require aligned
-   register pairs.  */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((MODE) == PSImode ? 1 : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 2)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  (MODE1 == MODE2 || (GET_MODE_SIZE (MODE1) <= 2 && GET_MODE_SIZE (MODE2) <= 2))
-
-/* 4 data, and effectively 2 address registers is small as far as I'm
-   concerned.  Especially since we use 2 data registers for argument
-   passing and return values.
-
-   We used to define CLASS_LIKELY_SPILLED_P as true for DATA_REGS too,
-   but we've made improvements to the port which greatly reduce register
-   pressure.  As a result we no longer need to define CLASS_LIKELY_SPILLED_P
-   for DATA_REGS (and by not defining it we get significantly better code).  */
-#define SMALL_REGISTER_CLASSES 1
-#define CLASS_LIKELY_SPILLED_P(CLASS) (CLASS == ADDRESS_REGS)
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-enum reg_class {
-  NO_REGS, DATA_REGS, ADDRESS_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
-{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \
-  "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS  			\
-{     0,		/* No regs      */	\
-   0x0f,		/* DATA_REGS */		\
-   0xf0,		/* ADDRESS_REGS */	\
-   0xff,		/* GENERAL_REGS */    	\
-   0xff,		/* ALL_REGS 	*/	\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) \
-  ((REGNO) < 4 ? DATA_REGS : ADDRESS_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS DATA_REGS
-#define BASE_REG_CLASS  ADDRESS_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'd' ? DATA_REGS : \
-   (C) == 'a' ? ADDRESS_REGS : NO_REGS)
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
- 
-#define REGNO_OK_FOR_BASE_P(regno) \
-  (((regno) > 3 && regno < FIRST_PSEUDO_REGISTER)	\
-   || (reg_renumber[regno] > 3 && reg_renumber[regno] < FIRST_PSEUDO_REGISTER))
-
-#define REGNO_OK_FOR_INDEX_P(regno) \
-  (((regno) >= 0 && regno < 4)	\
-   || (reg_renumber[regno] >= 0 && reg_renumber[regno] < 4))
-
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
-  ((GET_MODE (X) != PSImode) ? DATA_REGS : CLASS)
-
-/* We want to use DATA_REGS for anything that is not PSImode.  */
-#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
-  ((MODE != PSImode) ? DATA_REGS : CLASS)
-
-/* We have/need secondary reloads on the mn10200.  Mostly to deal
-   with problems using address registers.  */
-#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
-  secondary_reload_class(CLASS,MODE,IN, 1)
-
-#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,IN) \
-  secondary_reload_class(CLASS,MODE,IN, 0)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
-  ((MODE) == PSImode ? 1 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* The letters I, J, K, L, M, N, O, P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.  */
-
-#define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100)
-#define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000)
-
-#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
-#define CONST_OK_FOR_J(VALUE) ((VALUE) >= 1 && (VALUE) <= 3)
-#define CONST_OK_FOR_K(VALUE) ((VALUE) >= 1 && (VALUE) <= 4)
-#define CONST_OK_FOR_L(VALUE) ((VALUE) == 15)
-#define CONST_OK_FOR_M(VALUE) ((VALUE) == 255)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
-   (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
-   (C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
-   (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
-   (C) == 'M' ? CONST_OK_FOR_M (VALUE) : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself. 
-     
-  `G' is a floating-point zero.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT	\
-		 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))		\
-   : 0)
-
-
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-
-#define STARTING_FRAME_OFFSET 0
-
-/* Offset of first parameter from the argument pointer register value.  */
-/* Is equal to the size of the saved fp + pc, even if an fp isn't
-   saved since the value is used before we know.  */
-
-#define FIRST_PARM_OFFSET(FNDECL) (current_function_needs_context ? 8 : 4)
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 7
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 6
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 6
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 4
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.
-
-   We allow frame pointers to be eliminated when not having one will
-   not interfere with debugging.  */
-#define ACCUMULATE_OUTGOING_ARGS
-#define FRAME_POINTER_REQUIRED 0
-#define CAN_DEBUG_WITHOUT_FP
-
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved.  */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = total_frame_size()
-
-/* Various type size information.
-
-   The mn10200 has a limited number of small registers.  Sizes of basic
-   data types are adjusted accordingly.  */
-#define SHORT_TYPE_SIZE         16
-#define INT_TYPE_SIZE           16
-#define LONG_TYPE_SIZE          32
-#define LONG_LONG_TYPE_SIZE     32
-#define FLOAT_TYPE_SIZE         32
-#define DOUBLE_TYPE_SIZE        32
-#define LONG_DOUBLE_TYPE_SIZE   DOUBLE_TYPE_SIZE
-
-/* Any size less than 64bits will work; but a smarter definition
-   can make G++ code smaller and faster.  Most operations on the
-   mn10200 occur on 16bit hunks, so the best size for a boolean
-   is 16bits.  */
-#define BOOL_TYPE_SIZE		16
-
-/* The difference of two pointers must be at least 24bits since pointers
-   are 24bits; however, no basic data type is 24bits, so we have to round
-   up to a 32bits for the difference of pointers.  */
-#undef SIZE_TYPE
-#undef PTRDIFF_TYPE
-#define SIZE_TYPE "long unsigned int"
-#define PTRDIFF_TYPE "long unsigned int"
-
-/* Note sizeof (WCHAR_TYPE) must be equal to the value of WCHAR_TYPE_SIZE!  */
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-#define MAX_FIXED_MODE_SIZE     32
-
-/* A guess for the MN10200.  */
-#define PROMOTE_PROTOTYPES 1
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* 1 if N is a possible register number for function argument passing.  */
-
-#define FUNCTION_ARG_REGNO_P(N) ((N) <= 1)
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.  */
-
-#define CUMULATIVE_ARGS struct cum_arg
-struct cum_arg { int nbytes; };
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the MN10200, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM).nbytes = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM).nbytes += ((MODE) != BLKmode			\
-	? (MODE) == PSImode ? 2 :			\
-	    (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD \
-	: (int_size_in_bytes (TYPE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-extern struct rtx_def *function_arg();
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  function_arg (&CUM, MODE, TYPE, NAMED)
-
-
-/* For "large" items, we pass them by invisible reference, and the
-   callee is responsible for copying the data item if it might be
-   modified.  */
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)		\
-  ((TYPE) && int_size_in_bytes (TYPE) > 8)
- 
-#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
-  ((TYPE) && int_size_in_bytes (TYPE) > 8)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.   */
-   
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), TYPE_MODE (VALTYPE) == PSImode ? 4 : 0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, (MODE) == PSImode ? 4 : 0)
-
-/* 1 if N is a possible register number for a function value.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 4)
-
-/* Return values > 8 bytes in length in memory.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-#define RETURN_IN_MEMORY(TYPE)  \
-  (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode)
-
-/* Register in which address to store a structure value
-   is passed to a function.  On the MN10200 it's passed as
-   the first parameter.  */
-
-#define STRUCT_VALUE 0
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.
-
-   ?!? Profiling is not currently supported.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) ;
-
-/* Yes, we actually support trampolines on this machine, even though
-   nobody is likely to ever use them.  */
-#define TRAMPOLINE_TEMPLATE(FILE)			\
-  do {							\
-    fprintf (FILE, "\t.byte 0xfd\n");			\
-    fprintf (FILE, "\t.byte 0x00\n");			\
-    fprintf (FILE, "\t.byte 0x00\n");			\
-    fprintf (FILE, "\tmov (a3),a0\n");			\
-    fprintf (FILE, "\tadd -4,a3\n");			\
-    fprintf (FILE, "\tmov a0,(0,a3)\n");		\
-    fprintf (FILE, "\tmov (21,a0),a0\n");		\
-    fprintf (FILE, "\tmov a0,(4,a3)\n");		\
-    fprintf (FILE, "\tmov (0,a3),a0\n");		\
-    fprintf (FILE, "\tmov (17,a0),a0\n");		\
-    fprintf (FILE, "\tadd 4,a3\n");			\
-    fprintf (FILE, "\trts\n");				\
-    fprintf (FILE, "\t.long 0\n");			\
-    fprintf (FILE, "\t.long 0\n");			\
-  } while (0)
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 0x1c
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx (MEM, PSImode, plus_constant ((TRAMP), 20)),  \
-		  (CXT));						\
-  emit_move_insn (gen_rtx (MEM, PSImode, plus_constant ((TRAMP), 24)),  \
-		  (FNADDR));						\
-}
-
-/* A C expression whose value is RTL representing the value of the return
-   address for the frame COUNT steps up from the current frame.  */
-
-#define RETURN_ADDR_RTX(COUNT, FRAME)   \
-  ((COUNT == 0)                         \
-   ? gen_rtx (MEM, Pmode, frame_pointer_rtx) \
-   : (rtx) 0)
-
-
-/* Addressing modes, and classification of registers for them.  */
-
-
-/* 1 if X is an rtx for a constant that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   CONSTANT_P (X)
-
-/* Extra constraints.  */
-#define OK_FOR_R(OP) \
-   (GET_CODE (OP) == MEM					\
-    && GET_MODE (OP) == QImode					\
-    && REG_P (XEXP (OP, 0)))
- 
-/* Q is used for sp + <something> in the {zero,sign}_extendpsisi2 patterns.  */
-#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'R' ? OK_FOR_R (OP) : \
-  (C) == 'S' ? GET_CODE (OP) == SYMBOL_REF : \
-  (C) == 'Q' ? GET_CODE (OP) == PLUS : 0)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X)  \
-  (((REGNO (X) >= 0 && REGNO(X) <= 3) || REGNO (X) >= FIRST_PSEUDO_REGISTER))
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-  (((REGNO (X) >= 4 && REGNO(X) <= 8) || REGNO (X) >= FIRST_PSEUDO_REGISTER))
-#else
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) \
-  REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-  REGNO_OK_FOR_BASE_P (REGNO (X))
-#endif
-
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   We used to allow reg+reg addresses for QImode and HImode; however,
-   they tended to cause the register allocator to run out of registers.
-   Basically, an indexed load/store always keeps 2 data and one address
-   register live, which is just too many for this machine.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
-   except for CONSTANT_ADDRESS_P which is actually machine-independent.  */
-
-/* Accept either REG or SUBREG where a register is valid.  */
-  
-#define RTX_OK_FOR_BASE_P(X)					\
-  ((REG_P (X) && REG_OK_FOR_BASE_P (X))				\
-   || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))		\
-       && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)    	\
-{							\
-  if ((MODE != PSImode) && CONSTANT_ADDRESS_P (X))	\
-    goto ADDR;						\
-  if (RTX_OK_FOR_BASE_P (X))				\
-    goto ADDR;						\
-  if (GET_CODE (X) == PLUS)				\
-    {							\
-      rtx base = 0, index = 0;				\
-      if (RTX_OK_FOR_BASE_P (XEXP (X, 0)))		\
-	base = XEXP (X, 0), index = XEXP (X, 1);	\
-      if (RTX_OK_FOR_BASE_P (XEXP (X, 1)))		\
-	base = XEXP (X, 1), index = XEXP (X, 0);	\
-      if (base != 0 && index != 0)			\
-	{						\
-	  if (GET_CODE (index) == CONST_INT)		\
-	    goto ADDR;					\
-	}						\
-    }							\
-}
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.   */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)  {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  {}
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  No extra ones are needed for the vax.  */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define CC_OVERFLOW_UNUSABLE 0x200
-#define CC_NO_CARRY CC_NO_OVERFLOW
-#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
-
-/* The mn10200 has a limited number of registers, so CSE of function
-   addresses generally makes code worse due to register pressure.  */
-#define NO_FUNCTION_CSE
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:							\
-    /* Zeros are extremely cheap.  */					\
-    if (INTVAL (RTX) == 0)						\
-      return 0;								\
-    /* If it fits in 8 bits, then it's still relatively cheap.  */	\
-    if (INT_8_BITS (INTVAL (RTX)))					\
-      return 1;								\
-    /* This is the "base" cost, includes constants where either the	\
-       upper or lower 16bits are all zeros.  */				\
-    if (INT_16_BITS (INTVAL (RTX))					\
-	|| (INTVAL (RTX) & 0xffff) == 0					\
-	|| (INTVAL (RTX) & 0xffff0000) == 0)				\
-      return 2;								\
-    return 4;								\
-  /* These are more costly than a CONST_INT, but we can relax them,	\
-     so they're less costly than a CONST_DOUBLE.  */			\
-  case CONST:								\
-  case LABEL_REF:							\
-  case SYMBOL_REF:							\
-    return 6;								\
-  /* We don't optimize CONST_DOUBLEs well nor do we relax them well,	\
-     so their cost is very high.  */					\
-  case CONST_DOUBLE:							\
-    return 8;
-
-/* Make moves between different classes more expensive than moves
-   within the same class.  */
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)  (CLASS1 != CLASS2 ? 4 : 2)
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE. 
-
-   ?!? This probably needs more work.  The definitions below were first
-   taken from the H8 port, then tweaked slightly to improve code density
-   on various sample codes.  */
-
-#define RTX_COSTS(RTX,CODE,OUTER_CODE) \
-  case MOD:						\
-  case DIV:						\
-    return 8;						\
-  case MULT:						\
-    return (GET_MODE (RTX) == SImode ? 20 : 8);
-
-/* Nonzero if access to memory by bytes or half words is no faster
-   than accessing full words.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* According expr.c, a value of around 6 should minimize code size, and
-   for the MN10200 series, code size our primary concern.  */
-#define MOVE_RATIO 6
-
-#define TEXT_SECTION_ASM_OP "\t.section .text"
-#define DATA_SECTION_ASM_OP "\t.section .data"
-#define BSS_SECTION_ASM_OP "\t.section .bss"
-
-/* Output at beginning/end of assembler file.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) asm_file_start(FILE)
-
-#define ASM_COMMENT_START "#"
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* This is how to output an assembler line defining a `double' constant.
-   It is .dfloat or .gfloat, depending.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.double %s\n", dstr);		\
-   } while (0)
-
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.float %s\n", dstr);		\
-   } while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE, VALUE)		\
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE, VALUE)		\
-( fprintf (FILE, "\t.hword "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE, VALUE)		\
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-#define ASM_OUTPUT_BYTE(FILE, VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* This says how to output the assembler to define a global
-   uninitialized but not common symbol.
-   Try to use asm_output_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE, NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE, NAME)	\
-  do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE, NAME)	          \
-  do {                                            \
-  char* real_name;                                \
-  STRIP_NAME_ENCODING (real_name, (NAME));        \
-  fprintf (FILE, "_%s", real_name);               \
-  } while (0)           
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
-
-/* This is how we tell the assembler that two symbols have the same value.  */
-
-#define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
-  do { assemble_name(FILE, NAME1); 	 \
-       fputs(" = ", FILE);		 \
-       assemble_name(FILE, NAME2);	 \
-       fputc('\n', FILE); } while (0)
-
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3"}
-
-/* Print an instruction operand X on file FILE.
-   look in mn10200.c for details */
-
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand(FILE,X,CODE)
-
-/* Print a memory operand whose address is X, on file FILE.
-   This uses a function in output-vax.c.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-  asm_fprintf (FILE, "\t%s .L%d\n", ".long", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL)
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", (LOG))
-
-/* We don't have to worry about dbx compatibility for the mn10200.  */
-#define DEFAULT_GDB_EXTENSIONS 1
-
-/* Use stabs debugging info by default.  */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#define DBX_REGISTER_NUMBER(REGNO) REGNO
-
-/* GDB always assumes the current function's frame begins at the value
-   of the stack pointer upon entry to the current function.  Accessing
-   local variables and parameters passed on the stack is done using the
-   base of the frame + an offset provided by GCC.
-
-   For functions which have frame pointers this method works fine;
-   the (frame pointer) == (stack pointer at function entry) and GCC provides
-   an offset relative to the frame pointer.
-
-   This loses for functions without a frame pointer; GCC provides an offset
-   which is relative to the stack pointer after adjusting for the function's
-   frame size.  GDB would prefer the offset to be relative to the value of
-   the stack pointer at the function's entry.  Yuk!  */
-#define DEBUGGER_AUTO_OFFSET(X) \
-  ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
-    + (frame_pointer_needed ? 0 : -total_frame_size ()))
-
-#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
-  ((GET_CODE (X) == PLUS ? OFFSET : 0) \
-    + (frame_pointer_needed ? 0 : -total_frame_size ()))
-
-/* We need to prepend underscores.  */
-#define ASM_OUTPUT_DWARF2_ADDR_CONST(FILE,ADDR) \
-  fprintf ((FILE), "\t%s\t_%s", UNALIGNED_WORD_ASM_OP, (ADDR))
-  
-/* Define to use software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion. */
-#define REAL_ARITHMETIC
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE Pmode
-
-/* Define this if the case instruction drops through after the table
-   when the index is out of range.  Don't define it if the case insn
-   jumps to the default label instead.  */
-#define CASE_DROPS_THROUGH
-
-/* Dispatch tables on the mn10200 are extremely expensive in terms of code
-   and readonly data size.  So we crank up the case threshold value to
-   encourage a series of if/else comparisons to implement many small switch
-   statements.  In theory, this value could be increased much more if we
-   were solely optimizing for space, but we keep it "reasonable" to avoid
-   serious code efficiency lossage.  */
-#define CASE_VALUES_THRESHOLD 8
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* We could define this either way.  Using ZERO_EXTEND for QImode makes slightly
-   fast and more compact code.  */
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.  */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX	2
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) (OUTPREC != 32)
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode PSImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* Perform target dependent optabs initialization.  */
-#define MODHI3_LIBCALL "__modhi3"
-#define DIVHI3_LIBCALL "__divhi3"
-
-#define INIT_TARGET_OPTABS \
-  do { \
-    sdiv_optab->handlers[(int) HImode].libfunc		\
-      = gen_rtx (SYMBOL_REF, Pmode, DIVHI3_LIBCALL);	\
-    smod_optab->handlers[(int) HImode].libfunc		\
-      = gen_rtx (SYMBOL_REF, Pmode, MODHI3_LIBCALL);	\
-  } while (0)
-
-/* The assembler op to get a word.  */
-
-#define FILE_ASM_OP "\t.file\n"
-
-extern void asm_file_start ();
-extern void print_operand ();
-extern void print_operand_address ();
-extern void expand_prologue ();
-extern void expand_epilogue ();
-extern void notice_update_cc ();
-extern int call_address_operand ();
-extern enum reg_class secondary_reload_class ();
-extern char *emit_a_shift ();
-extern int current_function_needs_context;
-extern char *output_tst ();
-extern int extendpsi_operand ();
-extern int rtx_equal_function_value_matters;
-extern struct rtx_def *zero_dreg;
-extern struct rtx_def *zero_areg;
diff --git a/gcc/config/mn10200/mn10200.md b/gcc/config/mn10200/mn10200.md
deleted file mode 100755
index c0149d8..0000000
--- a/gcc/config/mn10200/mn10200.md
+++ /dev/null
@@ -1,2052 +0,0 @@
-;; GCC machine description for Matsushita MN10200
-;; Copyright (C) 1997, 1998 Free Software Foundation, Inc.
-
-;; Contributed by Jeff Law (law@cygnus.com).
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;; The original PO technology requires these to be ordered by speed,
-;; so that assigner will pick the fastest.
-
-;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; Condition code settings.
-;; none - insn does not affect cc
-;; none_0hit - insn does not affect cc but it does modify operand 0
-;;	This attribute is used to keep track of when operand 0 changes.
-;; 	See the description of NOTICE_UPDATE_CC for more info.
-;; set_znv - sets z,n,v to usable values; c is unknown.
-;; set_zn  - sets z,n to usable values; v,c is unknown.
-;; compare - compare instruction
-;; clobber - value of cc is unknown
-(define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
-  (const_string "clobber"))
-
-;; ----------------------------------------------------------------------
-;; MOVE INSTRUCTIONS
-;; ----------------------------------------------------------------------
-;;
-;; Some general notes on move instructions.
-;;
-;; The hardware can't encode nop moves involving data registers, so
-;; we catch them and emit a nop instead.
-;;
-;; Loads/stores to/from address registers must be 16bit aligned,
-;; thus we avoid them for QImode.
-;;
-;; Stores from address registers always store 24bits, so avoid
-;; stores from address registers in HImode, SImode, and SFmode.
-;;
-;; As a result of the various problems using address registers in
-;; QImode, HImode, SImode, and SFmode, we discourage their use via
-;; '*' in their constraints.  They're still allowed, but they're never
-;; the preferred class for insns with those modes.
-
-;; movqi
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand (operand0, QImode)
-      && !register_operand (operand1, QImode))
-    operands[1] = copy_to_mode_reg (QImode, operand1);
-}")
-
-;; We avoid memory operations involving address registers because we
-;; can't be sure they'll be suitably aligned.
-;;
-;; We also discourage holding QImode values in address registers.
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=d,d,*a,d,d,m,d,*a,*a")
-	(match_operand:QI 1 "general_operand" "0,I,I,di,m,d,*a,d,i*a"))]
-  "register_operand (operands[0], QImode)
-   || register_operand (operands[1], QImode)"
-  "@
-  nop
-  sub %0,%0
-  sub %0,%0
-  mov %S1,%0
-  movbu %1,%0
-  movb %1,%0
-  mov %1,%0
-  mov %1,%0
-  mov %1,%0"
-  [(set_attr "cc" "none,clobber,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
-
-;; movhi
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand (operand1, HImode)
-      && !register_operand (operand0, HImode))
-    operands[1] = copy_to_mode_reg (HImode, operand1);
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d,d,*a,d,d,m,d,*a,*a,*a")
-	(match_operand:HI 1 "general_operand" "0,I,I,di,m,d,*a,d,i*a,m"))]
-  "register_operand (operands[0], HImode)
-   || register_operand (operands[1], HImode)"
-  "@
-  nop
-  sub %0,%0
-  sub %0,%0
-  mov %s1,%0
-  mov %1,%0
-  mov %1,%0
-  mov %1,%0
-  mov %1,%0
-  mov %1,%0
-  mov %A1,%0"
-  [(set_attr "cc" "none,clobber,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
-
-;; movpsi and helpers
-
-(define_expand "movpsi"
-  [(set (match_operand:PSI 0 "general_operand" "")
-	(match_operand:PSI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand (operand1, PSImode)
-      && !register_operand (operand0, PSImode))
-    operands[1] = copy_to_mode_reg (PSImode, operand1);
-}")
-
-
-;; Constant and indexed addresses are not valid addresses for PSImode,
-;; therefore they won't be matched by the general movpsi pattern below.
-;; ??? We had patterns to handle indexed addresses, but they kept making
-;; us run out of regs, so they were eliminated.
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "register_operand" "=a")
-	(match_operand:PSI 1 "constant_memory_operand" ""))]
-  ""
-  "mov %A1,%0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "constant_memory_operand" "=X")
-	(match_operand:PSI 1 "register_operand" "a"))]
-  ""
-  "mov %1,%A0"
-  [(set_attr "cc" "none_0hit")])
-
-;; We want to prefer address registers here because 24bit moves to/from
-;; memory are shorter and faster when done via address registers.
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d,a?d,?da,a,m,?d,m")
-	(match_operand:PSI 1 "general_operand" "0,I,?dai,m,a,m,?d"))]
-  "register_operand (operands[0], PSImode)
-   || register_operand (operands[1], PSImode)"
-  "@
-  nop
-  sub %0,%0
-  mov %1,%0
-  mov %A1,%0
-  mov %1,%A0
-  movx %A1,%0
-  movx %1,%A0"
-  [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand (operand1, SImode)
-      && !register_operand (operand0, SImode))
-    operands[1] = copy_to_mode_reg (SImode, operand1);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d,d,*a,dm,d,d,*a,*a,*a")
-	(match_operand:SI 1 "general_operand" "0,I,I,d,dim,*a,d,*a,i"))]
-  "register_operand (operands[0], SImode)
-   || register_operand (operands[1], SImode)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      return \"nop\";
-    case 1:
-    case 2:
-      return \"sub %H0,%H0\;sub %L0,%L0\";
-    case 3:
-    case 5:
-    case 6:
-    case 7:
-      return \"mov %H1,%H0\;mov %L1,%L0\";
-
-    /* The next two cases try to optimize cases where one half
-       of the constant is all zeros, or when the two halves are
-       the same.  */
-    case 4:
-    case 8:
-      if (REG_P (operands[0])
-	  && GET_CODE (operands[1]) == CONST_INT
-	  && (INTVAL (operands[1]) & 0xffff0000) == 0)
-	output_asm_insn (\"sub %H0,%H0\", operands);
-      else
-	output_asm_insn (\"mov %h1,%H0\", operands);
-
-      if (GET_CODE (operands[1]) == CONST_INT
-	  && ((INTVAL (operands[1]) & 0xffff)
-	      == ((INTVAL (operands[1]) >> 16) & 0xffff)))
-	output_asm_insn (\"mov %H0,%L0\", operands);
-      else if (GET_CODE (operands[1]) == CONST_INT
-	       && (INTVAL (operands[1]) & 0xffff) == 0)
-	output_asm_insn (\"sub %L0,%L0\", operands);
-      else
-	output_asm_insn (\"mov %o1,%L0\", operands);
-      return \"\";
-    }
-}"
-  [(set_attr "cc" "none,clobber,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand (operand1, SFmode)
-      && !register_operand (operand0, SFmode))
-    operands[1] = copy_to_mode_reg (SFmode, operand1);
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=d,d,*a,dm,d,d,*a,*a,*a")
-	(match_operand:SF 1 "general_operand" "0,G,G,d,dim,*a,d,*a,i"))]
-  "register_operand (operands[0], SFmode)
-   || register_operand (operands[1], SFmode)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      return \"nop\";
-
-    case 1:
-    case 2:
-      return \"sub %H0,%H0\;sub %L0,%L0\";
-
-    default:
-      {
-        long val;
-        REAL_VALUE_TYPE rv;
-
-	if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	  {
-	    REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-	    REAL_VALUE_TO_TARGET_SINGLE (rv, val);
-	  }
-
-	if (GET_CODE (operands[1]) == CONST_INT)
-	  val = INTVAL (operands[1]);
-
-        if ((GET_CODE (operands[1]) == CONST_INT
-	     || GET_CODE (operands[1]) == CONST_DOUBLE)
-	    && (val & 0xffff0000) == 0)
-	  output_asm_insn (\"sub %H0,%H0\", operands);
-	else
-	  output_asm_insn (\"mov %h1,%H0\", operands);
-	
-	if (GET_CODE (operands[1]) == CONST_INT
-	    && ((INTVAL (operands[1]) & 0xffff)
-		 == ((INTVAL (operands[1]) >> 16) & 0xffff)))
-	  output_asm_insn (\"mov %H0,%L0\", operands);
-        else if ((GET_CODE (operands[1]) == CONST_INT
-		  || GET_CODE (operands[1]) == CONST_DOUBLE)
-		 && (val & 0x0000ffff) == 0)
-	  output_asm_insn (\"sub %L0,%L0\", operands);
-	else
-	  output_asm_insn (\"mov %o1,%L0\", operands);
-	return \"\";
-      }
-    }
-}"
-  [(set_attr "cc" "none,clobber,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
-
-
-;; ----------------------------------------------------------------------
-;; TEST INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; Go ahead and define tsthi and tstpsi so we can eliminate redundant tst insns
-;; when we start trying to optimize this port.
-(define_insn "tsthi"
-  [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "da"))]
-  ""
-  "* return output_tst (operands[0], insn);"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn "tstpsi"
-  [(set (cc0) (match_operand:PSI 0 "nonimmediate_operand" "da"))]
-  ""
-  "* return output_tst (operands[0], insn);"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (cc0) (zero_extend:HI (match_operand:QI 0 "memory_operand" "d")))]
-  ""
-  "* return output_tst (operands[0], insn);"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (cc0) (zero_extend:PSI (match_operand:QI 0 "memory_operand" "d")))]
-  ""
-  "* return output_tst (operands[0], insn);"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn "cmphi"
-  [(set (cc0)
-	(compare:HI (match_operand:HI 0 "nonimmediate_operand" "da")
-		    (match_operand:HI 1 "general_operand" "dai")))]
-  ""
-  "cmp %1,%0"
-  [(set_attr "cc" "compare")])
-
-(define_insn "cmppsi"
-  [(set (cc0)
-	(compare:PSI (match_operand:PSI 0 "nonimmediate_operand" "da")
-		     (match_operand:PSI 1 "general_operand" "dai")))]
-  ""
-  "cmp %1,%0"
-  [(set_attr "cc" "compare")])
-
-;; ----------------------------------------------------------------------
-;; ADD INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(plus:HI (match_operand:HI 1 "general_operand" "%0")
-		 (match_operand:HI 2 "general_operand" "dai")))]
-  ""
-  "add %2,%0"
-  [(set_attr "cc" "set_zn")])
-
-(define_insn "addpsi3"
-  [(set (match_operand:PSI 0 "general_operand" "=da")
-	(plus:PSI (match_operand:PSI 1 "general_operand" "%0")
-		  (match_operand:PSI 2 "general_operand" "dai")))]
-  ""
-  "add %2,%0"
-  [(set_attr "cc" "set_zn")])
-
-;; We want to avoid using explicit registers; reload won't tell us
-;; if it has to spill them and may generate incorrect code in such
-;; cases.
-;;
-;; So we call out to a library routine to perform 32bit add or
-;; subtract operations.
-;;
-;; operand2 must be nonmemory_operand so that we will accept CONST_INTs
-;; during initial code generation.
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  /* If adding a CONST_INT, we are better off generating code ourselves.
-
-     During RTL generation we call out to library routines.
-
-     After RTL generation we can not call the library routines as
-     they need to push arguments via virtual_outgoing_args_rtx which
-     has already been instantiated.  So, after RTL generation we just
-     FAIL and open code the operation.  */
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (!rtx_equal_p (operands[0], operands[1]))
-	emit_move_insn (operands[0], operands[1]);
-      emit_insn (gen_addsi3_const (operands[0], operands[0], operands[2]));
-      DONE;
-    }
-  else if (rtx_equal_function_value_matters)
-    {
-      rtx ret, insns;
-      extern rtx emit_library_call_value ();
-
-      start_sequence ();
-      ret = emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"__addsi3\"),
-				     NULL_RTX, 1, SImode, 2, operands[1],
-				     SImode, operands[2], SImode);
-      insns = get_insns ();
-      end_sequence ();
-      emit_libcall_block (insns, operands[0], ret,
-			  gen_rtx (PLUS, SImode, operands[1], operands[2]));
-      DONE;
-    }
-  else
-    FAIL;
-}")
-
-(define_insn "addsi3_const"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(plus:SI (match_operand:SI 1 "register_operand" "0")
-		 (match_operand:SI 2 "const_int_operand" "i")))
-   (clobber (match_scratch:SI 3 "=&d"))]
-  ""
-  "*
-{
-  unsigned long value = INTVAL (operands[2]);
-
-  /* If only the high bits are set in the constant, then we only
-     need a single add operation.  It might be better to catch this
-     at RTL expansion time.  */
-  if ((value & 0xffff) == 0)
-    return \"add %h2,%H0\";
-
-  value >>= 16;
-  value &= 0xffff;
-
-  if (value == 0)
-    return \"sub %3,%3\;add %o2,%L0\;addc %3,%H0\";
-  else
-    return \"mov %h2,%3\;add %o2,%L0\;addc %3,%H0\";
-}"
-  [(set_attr "cc" "clobber")])
-
-;; ----------------------------------------------------------------------
-;; SUBTRACT INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(minus:HI (match_operand:HI 1 "general_operand" "0")
-		  (match_operand:HI 2 "general_operand" "dai")))]
-  ""
-  "sub %2,%0"
-  [(set_attr "cc" "set_zn")])
-
-(define_insn "subpsi3"
-  [(set (match_operand:PSI 0 "general_operand" "=da")
-	(minus:PSI (match_operand:PSI 1 "general_operand" "0")
-		  (match_operand:PSI 2 "general_operand" "dai")))]
-  ""
-  "sub %2,%0"
-  [(set_attr "cc" "set_zn")])
-
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 1 "register_operand" "")
-		  (match_operand:SI 2 "register_operand" "")))]
-  ""
-  "
-{
-  /* During RTL generation we call out to library routines.
-
-     After RTL generation we can not call the library routines as
-     they need to push arguments via virtual_outgoing_args_rtx which
-     has already been instantiated.  So, after RTL generation we just
-     FAIL and open code the operation.  */
-  if (rtx_equal_function_value_matters)
-    {
-      rtx ret, insns;
-      extern rtx emit_library_call_value ();
-
-      start_sequence ();
-      ret = emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"__subsi3\"),
-				     NULL_RTX, 1, SImode, 2, operands[1],
-				     SImode, operands[2], SImode);
-      insns = get_insns ();
-      end_sequence ();
-      emit_libcall_block (insns, operands[0], ret,
-			  gen_rtx (MINUS, SImode, operands[1], operands[2]));
-      DONE;
-    }
-  else
-    FAIL;
-}")
-
-;; There isn't a negate instruction, so we fake it.
-;;
-;; We used to expand this into patterns, but a single pattern
-;; actually generates better overall code.
-;; 
-;; We could do HImode negations with a "not;add" sequence, but
-;; generally it's generated slightly worse code.
-;;
-;; The second alternative is not strictly necesasry, but helps
-;; when the register allocators start running short of registers.
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "general_operand" "=&d,d")
-        (neg:HI (match_operand:HI 1 "general_operand" "d,0")))]
-  ""
-  "@
-  sub %0,%0\;sub %1,%0
-  not %0\;add 1,%0"
-  [(set_attr "cc" "set_zn")])
-
-;; The not/and sequence won't work here.  It's not clear if we'll
-;; ever need to provide an alternate sequence since this should
-;; be used much less frequently than neghi2.
-(define_insn "negpsi2"
-  [(set (match_operand:PSI 0 "general_operand" "=&d")
-        (neg:PSI (match_operand:PSI 1 "general_operand" "d")))]
-  ""
-  "sub %0,%0\;sub %1,%0"
-  [(set_attr "cc" "set_zn")])
-
-;; Using a magic libcall that accepts its arguments in any
-;; data register pair has proven to be the most efficient
-;; and most compact way to represent negsi2.
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(neg:SI (match_operand:SI 1 "register_operand" "0")))]
-  ""
-  "jsr ___negsi2_%0"
-  [(set_attr "cc" "clobber")])
- 
-;; ----------------------------------------------------------------------
-;; MULTIPLY INSTRUCTIONS
-;; ----------------------------------------------------------------------
-;;
-;; The mn10200 has HIxHI->SI widening multiply, but we get _severe_
-;; code density regressions if we enable such a pattern.
-
-(define_insn "mulhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(mult:HI (match_operand:HI 1 "general_operand" "%0")
-		 (match_operand:HI 2 "general_operand" "d")))]
-  ""
-  "mul %2,%0"
-  [(set_attr "cc" "set_zn")])
-
-(define_insn "udivmodhi4"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(udiv:HI (match_operand:HI 1 "general_operand" "0")
-		 (match_operand:HI 2 "general_operand" "d")))
-   (set (match_operand:HI 3 "general_operand" "=&d")
-	(umod:HI (match_dup 1) (match_dup 2)))]
-  ""
-  "*
-{
-  if (zero_dreg)
-    output_asm_insn (\"mov %0,mdr\", &zero_dreg);
-  else
-    output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
-    
-  if (find_reg_note (insn, REG_UNUSED, operands[3]))
-    return \"divu %2,%0\";
-  else
-    return \"divu %2,%0\;mov mdr,%3\";
-}"
-  [(set_attr "cc" "set_zn")])
-
-
-;; ----------------------------------------------------------------------
-;; AND INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d,d")
-	(and:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "general_operand" "M,di")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
-    return \"extxbu %0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fff)
-    return \"add %0,%0\;lsr %0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffe)
-    return \"lsr %0\;add %0,%0\";
-  return \"and %2,%0\";
-}"
-  [(set_attr "cc" "none_0hit,set_znv")])
-
-;; This expander + pattern exist only to allow trampolines to be aligned
-;; in the stack.
-(define_expand "andpsi3"
-  [(set (match_operand:PSI 0 "general_operand" "")
-	(and:PSI (match_operand:PSI 1 "general_operand" "")
-		(match_operand:PSI 2 "const_int_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT
-      || (INTVAL (operands[2]) & 0xff0000) != 0xff0000)
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d")
-	(and:PSI (match_operand:PSI 1 "general_operand" "%0")
-		(match_operand:PSI 2 "const_int_operand" "i")))]
-  "GET_CODE (operands[2]) == CONST_INT
-   && (INTVAL (operands[2]) & 0xff0000) == 0xff0000"
-  "and %2,%0"
-  [(set_attr "cc" "clobber")])
-
-;; ----------------------------------------------------------------------
-;; OR INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(ior:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "di")))]
-  ""
-  "or %2,%0"
-  [(set_attr "cc" "set_znv")])
-
-;; ----------------------------------------------------------------------
-;; XOR INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(xor:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "di")))]
-  ""
-  "xor %2,%0"
-  [(set_attr "cc" "set_znv")])
-
-;; ----------------------------------------------------------------------
-;; NOT INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(not:HI (match_operand:HI 1 "general_operand" "0")))]
-  ""
-  "not %0"
-  [(set_attr "cc" "set_znv")])
-
-
-;; -----------------------------------------------------------------
-;; BIT INSTRUCTIONS
-;; -----------------------------------------------------------------
-
-;; These clears a constant set of bits in memory or in a register.
-;; We must support register destinations to make reload happy.
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "+R,d")
-	(subreg:QI
-	  (and:HI (subreg:HI (match_dup 0) 0)
-		  (match_operand 1 "const_int_operand" "")) 0))
-   (clobber (match_scratch:HI 2 "=&d,X"))]
-  ""
-  "@
-  mov %N1,%2\;bclr %2,%0
-  and %1,%0"
-  [(set_attr "cc" "clobber")])
-
-;; This clears a variable set of bits in memory or in a register.
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "+R,d")
-	(subreg:QI
-	  (and:HI (subreg:HI (match_dup 0) 0)
-		  (not:HI (match_operand:HI 1 "general_operand" "d,d"))) 0))
-   (clobber (match_scratch:HI 2 "=X,&d"))]
-  ""
-  "@
-  bclr %1,%0
-  mov %1,%2\;not %2\;and %2,%0"
-  [(set_attr "cc" "clobber")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "+R,d")
-	(subreg:QI
-	  (and:HI (not:HI (match_operand:HI 1 "general_operand" "d,d"))
-		  (subreg:HI (match_dup 0) 0)) 0))
-   (clobber (match_scratch:HI 2 "=X,&d"))]
-  ""
-  "@
-  bclr %1,%0
-  mov %1,%2\;not %2\;and %2,%0"
-  [(set_attr "cc" "clobber")])
-
-;; These set bits in memory.
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "+R,d")
-	(subreg:QI
-	  (ior:HI (subreg:HI (match_dup 0) 0)
-		  (match_operand:HI 1 "general_operand" "d,d")) 0))]
-  ""
-  "@
-  bset %1,%0
-  or %1,%0"
-  [(set_attr "cc" "clobber")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "+R,d")
-	(subreg:QI
-	  (ior:HI (match_operand:HI 1 "general_operand" "d,d")
-		  (subreg:HI (match_dup 0) 0)) 0))]
-  ""
-  "@
-  bset %1,%0
-  or %1,%0"
-  [(set_attr "cc" "clobber")])
-
-;; Not any shorter/faster than using cmp, but it might save a
-;; register if the result of the AND isn't ever used.
-
-(define_insn ""
-  [(set (cc0)
-     (zero_extract:HI (match_operand:HI 0 "general_operand" "d")
-		      (match_operand 1 "const_int_operand" "")
-		      (match_operand 2 "const_int_operand" "")))]
-  ""
-  "*
-{
-  int len = INTVAL (operands[1]);
-  int bit = INTVAL (operands[2]);
-  int mask = 0;
-  rtx xoperands[2];
-
-  while (len > 0)
-    {
-      mask |= (1 << bit);
-      bit++;
-      len--;
-    }
-
-  xoperands[0] = operands[0];
-  xoperands[1] = GEN_INT (mask);
-  output_asm_insn (\"btst %1,%0\", xoperands);
-  return \"\";
-}"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (cc0) (and:HI (match_operand:HI 0 "general_operand" "d")
-		      (match_operand:HI 1 "const_int_operand" "i")))]
-  ""
-  "btst %1,%0"
-  [(set_attr "cc" "set_znv")])
-
-
-;; ----------------------------------------------------------------------
-;; JUMP INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; Conditional jump instructions
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
-      && (GET_CODE (operands[1]) == GT
-          || GET_CODE (operands[1]) == GE
-          || GET_CODE (operands[1]) == LE
-          || GET_CODE (operands[1]) == LT))
-    return 0;
-
-  if (GET_MODE (SET_SRC (PATTERN (PREV_INSN (insn)))) == PSImode)
-    return \"b%b1x %0\";
-  else
-    return \"b%b1 %0\";
-}"
- [(set_attr "cc" "none")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
-      && (GET_CODE (operands[1]) == GT
-          || GET_CODE (operands[1]) == GE
-          || GET_CODE (operands[1]) == LE
-          || GET_CODE (operands[1]) == LT))
-    return 0;
-
-  if (GET_MODE (SET_SRC (PATTERN (PREV_INSN (insn)))) == PSImode)
-    return \"b%B1x %0\";
-  else
-    return \"b%B1 %0\";
-}"
- [(set_attr "cc" "none")])
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "jmp %l0"
- [(set_attr "cc" "none")])
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:PSI 0 "general_operand" "a"))]
-  ""
-  "jmp (%0)"
-  [(set_attr "cc" "none")])
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:PSI 0 "general_operand" "a"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmp  (%0)"
-  [(set_attr "cc" "none")])
-
-;; Call subroutine with no return value.
-
-(define_expand "call"
-  [(call (match_operand:QI 0 "general_operand" "")
-	 (match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (! call_address_operand (XEXP (operands[0], 0)))
-    XEXP (operands[0], 0) = force_reg (PSImode, XEXP (operands[0], 0));
-  emit_call_insn (gen_call_internal (XEXP (operands[0], 0), operands[1]));
-  DONE;
-}")
-
-(define_insn "call_internal"
-  [(call (mem:QI (match_operand:PSI 0 "call_address_operand" "aS"))
-	 (match_operand:HI 1 "general_operand" "g"))]
-  ""
-  "jsr %C0"
-  [(set_attr "cc" "clobber")])
-
-;; Call subroutine, returning value in operand 0
-;; (which must be a hard register).
-
-(define_expand "call_value"
-  [(set (match_operand 0 "" "")
-	(call (match_operand:QI 1 "general_operand" "")
-	      (match_operand:HI 2 "general_operand" "")))]
-  ""
-  "
-{
-  if (! call_address_operand (XEXP (operands[1], 0)))
-    XEXP (operands[1], 0) = force_reg (PSImode, XEXP (operands[1], 0));
-  emit_call_insn (gen_call_value_internal (operands[0],
-					   XEXP (operands[1], 0),
-					   operands[2]));
-  DONE;
-}")
-
-(define_insn "call_value_internal"
-  [(set (match_operand 0 "" "=da")
-	(call (mem:QI (match_operand:PSI 1 "call_address_operand" "aS"))
-	      (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "jsr %C1"
-  [(set_attr "cc" "clobber")])
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-                    (const_int 0))
-              (match_operand 1 "" "")
-              (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-  DONE;
-}")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-  [(set_attr "cc" "none")])
-
-;; ----------------------------------------------------------------------
-;; EXTEND INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=d,d,d")
-	(zero_extend:HI
-	 (match_operand:QI 1 "general_operand" "0,di,m")))]
-  ""
-  "@
-  extxbu %0
-  mov %1,%0\;extxbu %0
-  movbu %1,%0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn "zero_extendqipsi2"
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
-	(zero_extend:PSI
-	 (match_operand:QI 1 "general_operand" "0,di,m")))]
-  ""
-  "@
-  extxbu %0
-  mov %1,%0\;extxbu %0
-  movbu %1,%0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=d,d,d")
-	(zero_extend:SI
-	 (match_operand:QI 1 "general_operand" "0,di,m")))]
-  ""
-  "@
-  extxbu %L0\;sub %H0,%H0
-  mov %1,%L0\;extxbu %L0\;sub %H0,%H0
-  movbu %1,%L0\;sub %H0,%H0"
-  [(set_attr "cc" "clobber")])
-
-(define_insn "zero_extendhipsi2"
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
-	(zero_extend:PSI
-	 (match_operand:HI 1 "general_operand" "0,di,m")))]
-  ""
-  "@
-  extxu %0
-  mov %1,%0\;extxu %0
-  mov %1,%0\;extxu %0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=d,d")
-	(zero_extend:SI
-	 (match_operand:HI 1 "general_operand" "0,dim")))]
-  ""
-  "@
-  sub %H0,%H0
-  mov %1,%L0\;sub %H0,%H0"
-  [(set_attr "cc" "clobber,clobber")])
-
-;; The last alternative is necessary because the second operand might
-;; have been the frame pointer.  The frame pointer would get replaced
-;; by (plus (stack_pointer) (const_int)).
-;;
-;; Reload would think that it only needed a PSImode register in
-;; push_reload and at the start of allocate_reload_regs.  However,
-;; at the end of allocate_reload_reg it would realize that the
-;; reload register must also be valid for SImode, and if it was
-;; not valid reload would abort.
-(define_insn "zero_extendpsisi2"
-  [(set (match_operand:SI 0 "register_operand" "=d,?d,?*d,?*d")
-	(zero_extend:SI (match_operand:PSI 1 "extendpsi_operand"
-						"m,?0,?*dai,Q")))]
-  ""
-  "@
-  mov %L1,%L0\;movbu %H1,%H0
-  jsr ___zero_extendpsisi2_%0
-  mov %1,%L0\;jsr ___zero_extendpsisi2_%0
-  mov a3,%L0\;add %Z1,%L0\;jsr ___zero_extendpsisi2_%0"
-  [(set_attr "cc" "clobber")])
-
-;;- sign extension instructions
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=d,d,d")
-	(sign_extend:HI
-	 (match_operand:QI 1 "general_operand" "0,di,m")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"extxb %0\";
-  else if (which_alternative == 1)
-    return \"mov %1,%0\;extxb %0\";
-  else if (GET_CODE (XEXP (operands[1], 0)) == REG)
-    return \"movbu %1,%0\;extxb %0\";
-  else
-    return \"movb %1,%0\";
-}"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn "extendqipsi2"
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
-	(sign_extend:PSI
-	 (match_operand:QI 1 "general_operand" "0,di,m")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"extxb %0\";
-  else if (which_alternative == 1)
-    return \"mov %1,%0\;extxb %0\";
-  else if (GET_CODE (XEXP (operands[1], 0)) == REG)
-    return \"movbu %1,%0\;extxb %0\";
-  else
-    return \"movb %1,%0\";
-}"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=d,d,d")
-	(sign_extend:SI
-	 (match_operand:QI 1 "general_operand" "0,di,m")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"extxb %L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\";
-  else if (which_alternative == 1)
-    return \"mov %1,%L0\;extxb %L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\";
-  else if (GET_CODE (XEXP (operands[1], 0)) == REG)
-    return \"movbu %1,%L0\;extxb %L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\";
-  else
-    return \"movb %1,%L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\";
-}"
-  [(set_attr "cc" "clobber")])
-
-(define_insn "extendhipsi2"
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
-	(sign_extend:PSI
-	 (match_operand:HI 1 "general_operand" "0,di,m")))]
-  ""
-  "@
-  extx %0
-  mov %1,%0\;extx %0
-  mov %1,%0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=d,d,d")
-	(sign_extend:SI
-	 (match_operand:HI 1 "general_operand" "0,di,m")))]
-  ""
-  "@
-  mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0
-  mov %1,%L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0
-  mov %1,%L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0"
-  [(set_attr "cc" "clobber")])
-
-;; The last alternative is necessary because the second operand might
-;; have been the frame pointer.  The frame pointer would get replaced
-;; by (plus (stack_pointer) (const_int)).
-;;
-;; Reload would think that it only needed a PSImode register in
-;; push_reload and at the start of allocate_reload_regs.  However,
-;; at the end of allocate_reload_reg it would realize that the
-;; reload register must also be valid for SImode, and if it was
-;; not valid reload would abort.
-(define_insn "extendpsisi2"
-  [(set (match_operand:SI 0 "general_operand" "=d,?d,?*d,?*d")
-	(sign_extend:SI (match_operand:PSI 1 "extendpsi_operand"
-						"m,?0,?*dai,Q")))]
-  ""
-  "@
-  mov %L1,%L0\;movb %H1,%H0
-  jsr ___sign_extendpsisi2_%0
-  mov %1,%L0\;jsr ___sign_extendpsisi2_%0
-  mov a3,%L0\;add %Z1,%L0\;jsr ___sign_extendpsisi2_%0"
-  [(set_attr "cc" "clobber")])
-
-(define_insn "truncsipsi2"
-  [(set (match_operand:PSI 0 "general_operand" "=a,?d,?*d,da")
-	(truncate:PSI (match_operand:SI 1 "general_operand" "m,?m,?*d,i")))]
-   ""
-   "@
-   mov %1,%0
-   movx %A1,%0
-   jsr ___truncsipsi2_%1_%0
-   mov %1,%0"
-  [(set_attr "cc" "clobber")])
-
-
-;; Combine should be simplifying this stuff, but isn't.
-;;
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d,d,d")
-	(sign_extend:SI
-	  (zero_extend:HI (match_operand:QI 1 "general_operand" "0,di,m"))))]
-  ""
-  "@
-  extxbu %L0\;sub %H0,%H0
-  mov %1,%L0\;extxbu %L0\;sub %H0,%H0
-  movbu %1,%L0\;sub %H0,%H0"
-  [(set_attr "cc" "clobber")])
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
-        (truncate:PSI
-	  (sign_extend:SI (match_operand:QI 1 "general_operand" "0,di,m"))))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"extxb %0\";
-  else if (which_alternative == 1)
-    return \"mov %1,%0\;extxb %0\";
-  else if (GET_CODE (XEXP (operands[1], 0)) == REG)
-    return \"movbu %1,%0\;extxb %0\";
-  else
-    return \"movb %1,%0\";
-}"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
-	(truncate:PSI
-	  (sign_extend:SI (match_operand:HI 1 "general_operand" "0,di,m"))))]
-  ""
-  "@
-  extx %0
-  mov %1,%0\;extx %0
-  mov %1,%0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
-	(truncate:PSI
-	  (sign_extend:SI
-	    (zero_extend:HI (match_operand:QI 1 "general_operand" "0,di,m")))))]
-  ""
-  "@
-  extxbu %0
-  mov %1,%0\;extxbu %0
-  movbu %1,%0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
-	(truncate:PSI
-	  (zero_extend:SI (match_operand:HI 1 "general_operand" "0,di,m"))))]
-  ""
-  "@
-  extxu %0
-  mov %1,%0\;extxu %0
-  mov %1,%0\;extxu %0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
-        (truncate:PSI
-	  (zero_extend:SI (match_operand:QI 1 "general_operand" "0,di,m"))))]
-  ""
-  "@
-  extxbu %0
-  mov %1,%0\;extxbu %0
-  movbu %1,%0"
-  [(set_attr "cc" "none_0hit")])
-
-;; ----------------------------------------------------------------------
-;; SHIFTS
-;; ----------------------------------------------------------------------
-
-;; If the shift count is small, we expand it into several single bit
-;; shift insns.  Otherwise we expand into a generic shift insn which
-;; handles larger shift counts, shift by variable amounts, etc.
-(define_expand "ashlhi3"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(ashift:HI (match_operand:HI 1 "general_operand" "")
-		   (match_operand:HI 2 "general_operand" "")))]
-  ""
-  "
-{
-  /* This is an experiment to see if exposing more of the underlying
-     operations results in better code.  */
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) <= 4)
-    {
-      int count = INTVAL (operands[2]);
-      emit_move_insn (operands[0], operands[1]);
-      while (count > 0)
-	{
-	  emit_insn (gen_rtx (SET, HImode, operands[0],
-			      gen_rtx (ASHIFT, HImode,
-				       operands[0], GEN_INT (1))));
-	  count--;
-	}
-      DONE;
-    }
-  else
-    {
-      expand_a_shift (HImode, ASHIFT, operands);
-      DONE;
-    }
-}")
-
-;; ASHIFT one bit.
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(ashift:HI (match_operand:HI 1 "general_operand" "0")
-		   (const_int 1)))]
-  ""
-  "add %0,%0"
-  [(set_attr "cc" "set_zn")])
-
-(define_expand "lshrhi3"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(lshiftrt:HI (match_operand:HI 1 "general_operand" "")
-		     (match_operand:HI 2 "general_operand" "")))]
-  ""
-  "
-{
-  /* This is an experiment to see if exposing more of the underlying
-     operations results in better code.  */
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) <= 4)
-    {
-      int count = INTVAL (operands[2]);
-      emit_move_insn (operands[0], operands[1]);
-      while (count > 0)
-	{
-	  emit_insn (gen_rtx (SET, HImode, operands[0],
-			      gen_rtx (LSHIFTRT, HImode,
-				       operands[0], GEN_INT (1))));
-	  count--;
-	}
-      DONE;
-    }
-  else
-    {
-      expand_a_shift (HImode, LSHIFTRT, operands);
-      DONE;
-    }
-}")
-
-;; LSHIFTRT one bit.
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
-		     (const_int 1)))]
-  ""
-  "lsr %0"
-  [(set_attr "cc" "set_znv")])
-
-(define_expand "ashrhi3"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(ashiftrt:HI (match_operand:HI 1 "general_operand" "")
-		     (match_operand:HI 2 "general_operand" "")))]
-  ""
-  "
-{
-  /* This is an experiment to see if exposing more of the underlying
-     operations results in better code.  */
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) <= 4)
-    {
-      int count = INTVAL (operands[2]);
-      emit_move_insn (operands[0], operands[1]);
-      while (count > 0)
-	{
-	  emit_insn (gen_rtx (SET, HImode, operands[0],
-			      gen_rtx (ASHIFTRT, HImode,
-				       operands[0], GEN_INT (1))));
-	  count--;
-	}
-      DONE;
-    }
-  else
-    {
-      expand_a_shift (HImode, ASHIFTRT, operands);
-      DONE;
-    }
-}")
-
-;; ASHIFTRT one bit.
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
-		     (const_int 1)))]
-  ""
-  "asr %0"
-  [(set_attr "cc" "set_znv")])
-
-;; And the general HImode shift pattern.  Handles both shift by constants
-;; and shift by variable counts.
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d,d")
-	(match_operator:HI 3 "nshift_operator" 
-			[ (match_operand:HI 1 "general_operand" "0,0")
-			  (match_operand:HI 2 "general_operand" "KL,dan")]))
-   (clobber (match_scratch:HI 4 "=X,&d"))]
-  ""
-  "* return emit_a_shift (insn, operands);"
-  [(set_attr "cc" "clobber")])
-
-;; We expect only ASHIFT with constant shift counts to be common for
-;; PSImode, so we optimize just that case.  For all other cases we
-;; extend the value to SImode and perform the shift in SImode.
-(define_expand "ashlpsi3"
-  [(set (match_operand:PSI 0 "general_operand" "")
-	(ashift:PSI (match_operand:PSI 1 "general_operand" "")
-		   (match_operand:HI 2 "general_operand" "")))]
-  ""
-  "
-{
-  /* This is an experiment to see if exposing more of the underlying
-     operations results in better code.  */
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) <= 7)
-    {
-      int count = INTVAL (operands[2]);
-      emit_move_insn (operands[0], operands[1]);
-      while (count > 0)
-	{
-	  emit_insn (gen_rtx (SET, PSImode, operands[0],
-			      gen_rtx (ASHIFT, PSImode,
-				       operands[0], GEN_INT (1))));
-	  count--;
-	}
-      DONE;
-    }
-  else
-    {
-      expand_a_shift (PSImode, ASHIFT, operands);
-      DONE;
-    }
-}")
-
-;; ASHIFT one bit.
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d")
-	(ashift:PSI (match_operand:PSI 1 "general_operand" "0")
-		    (const_int 1)))]
-  ""
-  "add %0,%0"
-  [(set_attr "cc" "set_zn")])
-
-(define_expand "lshrpsi3"
-  [(set (match_operand:PSI 0 "general_operand" "")
-	(lshiftrt:PSI (match_operand:PSI 1 "general_operand" "")
-		     (match_operand:HI 2 "general_operand" "")))]
-  ""
-  "
-{
-  rtx reg = gen_reg_rtx (SImode);
-
-  emit_insn (gen_zero_extendpsisi2 (reg, operands[1]));
-  reg = expand_binop (SImode, lshr_optab, reg,
-		      operands[2], reg, 1, OPTAB_WIDEN);
-  emit_insn (gen_truncsipsi2 (operands[0], reg));
-  DONE;
-}")
-
-(define_expand "ashrpsi3"
-  [(set (match_operand:PSI 0 "general_operand" "")
-	(ashiftrt:PSI (match_operand:PSI 1 "general_operand" "")
-		     (match_operand:HI 2 "general_operand" "")))]
-  ""
-  "
-{
-  rtx reg = gen_reg_rtx (SImode);
-
-  emit_insn (gen_extendpsisi2 (reg, operands[1]));
-  reg = expand_binop (SImode, ashr_optab, reg,
-		      operands[2], reg, 0, OPTAB_WIDEN);
-  emit_insn (gen_truncsipsi2 (operands[0], reg));
-  DONE;
-}")
-
-(define_expand "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashift:SI (match_operand:SI 1 "nonmemory_operand" "")
-		   (match_operand:HI 2 "general_operand" "")))]
-  ""
-  "
-{
-  /* For small shifts, just emit a series of single bit shifts inline.
-
-     For other constant shift counts smaller than a word or non-constant
-     shift counts we call out to a library call during RTL generation time;
-     after RTL generation time we allow optabs.c to open code the operation.
-     See comments in addsi3/subsi3 expanders.
-
-     Otherwise we allow optabs.c to open code the operation.  */
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (INTVAL (operands[2]) <= 3))
-    {
-      int count = INTVAL (operands[2]);
-      emit_move_insn (operands[0], operands[1]);
-      while (count > 0)
-	{
-	  emit_insn (gen_rtx (SET, SImode, operands[0],
-				   gen_rtx (ASHIFT, SImode,
-					    operands[0], GEN_INT (1))));
-	  count--;
-	}
-      DONE;
-    }
-  else if (rtx_equal_function_value_matters
-	   && (GET_CODE (operands[2]) != CONST_INT
-	       || INTVAL (operands[2]) <= 15))
-    {
-      rtx ret, insns;
-      extern rtx emit_library_call_value ();
-
-      start_sequence ();
-      ret = emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"__ashlsi3\"),
-				     NULL_RTX, 1, SImode, 2, operands[1],
-				     SImode, operands[2], HImode);
-      insns = get_insns ();
-      end_sequence ();
-      emit_libcall_block (insns, operands[0], ret,
-			  gen_rtx (ASHIFT, SImode, operands[1], operands[2]));
-      DONE;
-    }
-  else
-    FAIL;
-}")
-
-;; ASHIFT one bit.
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(ashift:SI (match_operand:SI 1 "general_operand" "0")
-		     (const_int 1)))]
-  ""
-  "add %L0,%L0\;addc %H0,%H0"
-  [(set_attr "cc" "clobber")])
-
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lshiftrt:SI (match_operand:SI 1 "general_operand" "")
-		     (match_operand:HI 2 "general_operand" "")))]
-  ""
-  "
-{
-  /* For small shifts, just emit a series of single bit shifts inline.
-
-     For other constant shift counts smaller than a word or non-constant
-     shift counts we call out to a library call during RTL generation time;
-     after RTL generation time we allow optabs.c to open code the operation.
-     See comments in addsi3/subsi3 expanders.
-
-     Otherwise we allow optabs.c to open code the operation.  */
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (INTVAL (operands[2]) <= 2))
-    {
-      int count = INTVAL (operands[2]);
-      emit_move_insn (operands[0], operands[1]);
-      while (count > 0)
-	{
-	  emit_insn (gen_rtx (SET, SImode, operands[0],
-				   gen_rtx (LSHIFTRT, SImode,
-					    operands[0], GEN_INT (1))));
-	  count--;
-	}
-      DONE;
-    }
-  else if (rtx_equal_function_value_matters
-	   && (GET_CODE (operands[2]) != CONST_INT
-	       || INTVAL (operands[2]) <= 15))
-    {
-      rtx ret, insns;
-      extern rtx emit_library_call_value ();
-
-      start_sequence ();
-      ret = emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"__lshrsi3\"),
-				     NULL_RTX, 1, SImode, 2, operands[1],
-				     SImode, operands[2], HImode);
-      insns = get_insns ();
-      end_sequence ();
-      emit_libcall_block (insns, operands[0], ret,
-			  gen_rtx (LSHIFTRT, SImode, operands[1], operands[2]));
-      DONE;
-    }
-  else
-    FAIL;
-}")
-
-;; LSHIFTRT one bit.
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
-		     (const_int 1)))]
-  ""
-  "lsr %H0\;ror %L0"
-  [(set_attr "cc" "clobber")])
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:HI 2 "general_operand" "")))]
-  ""
-  "
-{
-  /* For small shifts, just emit a series of single bit shifts inline.
-
-     For other constant shift counts smaller than a word or non-constant
-     shift counts we call out to a library call during RTL generation time;
-     after RTL generation time we allow optabs.c to open code the operation.
-     See comments in addsi3/subsi3 expanders.
-
-     Otherwise we allow optabs.c to open code the operation.  */
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (INTVAL (operands[2]) <= 2))
-    {
-      int count = INTVAL (operands[2]);
-      emit_move_insn (operands[0], operands[1]);
-      while (count > 0)
-	{
-	  emit_insn (gen_rtx (SET, SImode, operands[0],
-				   gen_rtx (ASHIFTRT, SImode,
-					    operands[0], GEN_INT (1))));
-	  count--;
-	}
-      DONE;
-    }
-  else if (rtx_equal_function_value_matters
-	   && (GET_CODE (operands[2]) != CONST_INT
-	       || INTVAL (operands[2]) <= 15))
-    {
-      rtx ret, insns;
-      extern rtx emit_library_call_value ();
-
-      start_sequence ();
-      ret = emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"__ashrsi3\"),
-				     NULL_RTX, 1, SImode, 2, operands[1],
-				     SImode, operands[2], HImode);
-      insns = get_insns ();
-      end_sequence ();
-      emit_libcall_block (insns, operands[0], ret,
-			  gen_rtx (ASHIFTRT, SImode, operands[1], operands[2]));
-      DONE;
-    }
-  else
-    FAIL;
-}")
-
-;; ASHIFTRT one bit.
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=d")
-	(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
-		     (const_int 1)))]
-  ""
-  "asr %H0\;ror %L0"
-  [(set_attr "cc" "clobber")])
-
-;; ----------------------------------------------------------------------
-;; FP INSTRUCTIONS
-;; ----------------------------------------------------------------------
-;;
-;; The mn102 series does not have floating point instructions, but since
-;; FP values are held in integer regs, we can clear the high bit easily
-;; which gives us an efficient inline floating point absolute value.
-;;
-;; Similarly for negation of a FP value.
-;;
-
-(define_expand "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "")
-        (abs:SF (match_operand:SF 1 "register_operand" "")))]
-  ""
-  "
-{
-  rtx target, result, insns;
-
-  start_sequence ();
-  target = operand_subword (operands[0], 1, 1, SFmode);
-  result = expand_binop (HImode, and_optab,
-			 operand_subword_force (operands[1], 1, SFmode),
-			 GEN_INT(0x7fff), target, 0, OPTAB_WIDEN);
-
-  if (result == 0)
-    abort ();
-
-  if (result != target)
-    emit_move_insn (result, target);
-
-  emit_move_insn (operand_subword (operands[0], 0, 1, SFmode),
-		  operand_subword_force (operands[1], 0, SFmode));
-
-  insns = get_insns ();
-  end_sequence ();
-
-  emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
-  DONE;
-}")
-
-(define_expand "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "")
-        (neg:SF (match_operand:SF 1 "register_operand" "")))]
-  ""
-  "
-{
-  rtx target, result, insns;
-
-  start_sequence ();
-  target = operand_subword (operands[0], 1, 1, SFmode);
-  result = expand_binop (HImode, xor_optab,
-			 operand_subword_force (operands[1], 1, SFmode),
-			 GEN_INT(0x8000), target, 0, OPTAB_WIDEN);
-
-  if (result == 0)
-    abort ();
-
-  if (result != target)
-    emit_move_insn (result, target);
-
-  emit_move_insn (operand_subword (operands[0], 0, 1, SFmode),
-		  operand_subword_force (operands[1], 0, SFmode));
-
-  insns = get_insns ();
-  end_sequence ();
-
-  emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
-  DONE;
-}")
-
-;; ----------------------------------------------------------------------
-;; PROLOGUE/EPILOGUE
-;; ----------------------------------------------------------------------
-(define_expand "prologue"
-  [(const_int 0)]
-  ""
-  "expand_prologue (); DONE;")
-
-(define_insn "outline_prologue_call"
-  [(const_int 1)]
-  ""
-  "jsr ___prologue"
-  [(set_attr "cc" "clobber")])
-
-(define_expand "epilogue"
-  [(return)]
-  ""
-  "
-{
-  expand_epilogue ();
-  DONE;
-}")
-
-(define_insn "outline_epilogue_call_a0"
-  [(const_int 2)]
-  ""
-  "jsr ___epilogue_a0"
-  [(set_attr "cc" "clobber")])
-
-(define_insn "outline_epilogue_call_d0"
-  [(const_int 3)]
-  ""
-  "jsr ___epilogue_d0"
-  [(set_attr "cc" "clobber")])
-
-(define_insn "outline_epilogue_jump"
-  [(const_int 4)]
-  ""
-  "jmp ___epilogue_noreturn"
-  [(set_attr "cc" "clobber")])
-
-(define_insn "return"
-  [(return)]
-  "reload_completed && total_frame_size () == 0
-   && !current_function_needs_context"
-  "*
-{
-  rtx next = next_active_insn (insn);
-
-  if (next
-      && GET_CODE (next) == JUMP_INSN
-      && GET_CODE (PATTERN (next)) == RETURN)
-    return \"\";
-  return \"rts\";
-}"
-  [(set_attr "cc" "clobber")])
-
-(define_insn "return_internal"
-  [(const_int 0)
-   (return)]
-  ""
-  "rts"
-  [(set_attr "cc" "clobber")])
-
-;; These are special combiner patterns to improve array/pointer accesses.
-;;
-;; A typical sequence involves extending an integer/char, shifting it left
-;; a few times, then truncating the value to PSImode.
-;;
-;; This first pattern combines the shifting & truncation operations, by
-;; itself it is a win because the shifts end up occurring in PSImode instead
-;; of SImode.  However, it has the secondary effect of giving us the
-;; opportunity to match patterns which allow us to remove the initial
-;; extension completely, which is a big win.
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,a,da")
-	(truncate:PSI
-	  (ashift:SI (match_operand:SI 1 "general_operand" "d,m,m,i")
-		     (match_operand:HI 2 "const_int_operand" "i,i,i,i"))))]
-  ""
-  "*
-{
-  int count = INTVAL (operands[2]);
-  if (which_alternative == 0)
-    output_asm_insn (\"jsr ___truncsipsi2_%1_%0\", operands);
-  else if (which_alternative == 1)
-    output_asm_insn (\"movx %A1,%0\", operands);
-  else
-    output_asm_insn (\" mov %1,%0\", operands);
-
-  while (count)
-    {
-      output_asm_insn (\"add %0,%0\", operands);
-      count--;
-    }
-  return \"\";
-}"
-  [(set_attr "cc" "clobber")])
-
-;; Similarly, except that we also have zero/sign extension of the
-;; original operand.  */
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d,d")
-	(truncate:PSI
-	  (ashift:SI
-	    (zero_extend:SI (match_operand:HI 1 "general_operand" "0,dim"))
-	    (match_operand:HI 2 "const_int_operand" "i,i"))))]
-  ""
-  "*
-{
-  int count = INTVAL (operands[2]);
-
-  /* First extend operand 1 to PSImode.  */
-  if (which_alternative == 0)
-    output_asm_insn (\"extxu %0\", operands);
-  else
-    output_asm_insn (\"mov %1,%0\;extxu %0\", operands);
-
-  /* Now do the shifting.  */
-  while (count)
-    {
-      output_asm_insn (\"add %0,%0\", operands);
-      count--;
-    }
-  return \"\";
-}"
-  [(set_attr "cc" "clobber")])
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
-	(truncate:PSI
-	  (ashift:SI
-	    (sign_extend:SI (match_operand:HI 1 "general_operand" "0,di,m"))
-	    (match_operand:HI 2 "const_int_operand" "i,i,i"))))]
-  ""
-  "*
-{
-  int count = INTVAL (operands[2]);
-
-  /* First extend operand 1 to PSImode.  */
-  if (which_alternative == 0)
-    output_asm_insn (\"extx %0\", operands);
-  else if (which_alternative == 1)
-    output_asm_insn (\"mov %1,%0\;extx %0\", operands);
-  else
-    output_asm_insn (\"mov %1,%0\", operands);
-
-  /* Now do the shifting.  */
-  while (count)
-    {
-      output_asm_insn (\"add %0,%0\", operands);
-      count--;
-    }
-  return \"\";
-}"
-  [(set_attr "cc" "clobber")])
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
-	(truncate:PSI
-	  (ashift:SI
-	    (sign_extend:SI
-	      (zero_extend:HI (match_operand:QI 1 "general_operand" "0,di,m")))
-	    (match_operand:HI 2 "const_int_operand" "i,i,i"))))]
-  ""
-  "*
-{
-  int count = INTVAL (operands[2]);
-
-  /* First extend operand 1 to PSImode.  */
-  if (which_alternative == 0)
-    output_asm_insn (\"extxbu %0\", operands);
-  else if (which_alternative == 1)
-    output_asm_insn (\"mov %1,%0\;extxbu %0\", operands);
-  else
-    output_asm_insn (\"movbu %1,%0\", operands);
-
-  /* Now do the shifting.  */
-  while (count)
-    {
-      output_asm_insn (\"add %0,%0\", operands);
-      count--;
-    }
-  return \"\";
-}"
-  [(set_attr "cc" "clobber")])
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
-	(truncate:PSI
-	  (ashift:SI
-	    (sign_extend:SI
-	      (match_operand:QI 1 "general_operand" "0,di,m"))
-	    (match_operand:HI 2 "const_int_operand" "i,i,i"))))]
-  ""
-  "*
-{
-  int count = INTVAL (operands[2]);
-
-  /* First extend operand 1 to PSImode.  */
-  if (which_alternative == 0)
-    output_asm_insn (\"extxb %0\", operands);
-  else if (which_alternative == 1)
-    output_asm_insn (\"mov %1,%0\;extxb %0\", operands);
-  else if (GET_CODE (XEXP (operands[1], 0)) == REG)
-    output_asm_insn (\"movbu %1,%0\;extxb %0\", operands);
-  else
-    output_asm_insn (\"movb %1,%0\", operands);
-
-  /* Now do the shifting.  */
-  while (count)
-    {
-      output_asm_insn (\"add %0,%0\", operands);
-      count--;
-    }
-  return \"\";
-}"
-  [(set_attr "cc" "clobber")])
-
-;; Try to combine consecutive updates of the stack pointer (or any
-;; other register for that matter).
-(define_peephole
-  [(set (match_operand:PSI 0 "register_operand" "=da")
-	(plus:PSI (match_dup 0)
-		  (match_operand 1 "const_int_operand" "")))
-   (set (match_dup 0)
-	(plus:PSI (match_dup 0)
-		  (match_operand 2 "const_int_operand" "")))]
-  ""
-  "*
-{
-  operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]));
-  return \"add %1,%0\";
-}"
-  [(set_attr "cc" "clobber")])
-
-;;
-;; We had patterns to check eq/ne, but the they don't work because
-;; 0x80000000 + 0x80000000 = 0x0 with a carry out.
-;;
-;; The Z flag and C flag would be set, and we have no way to
-;; check for the Z flag set and C flag clear.
-;;
-;; This will work on the mn10200 because we can check the ZX flag
-;; if the comparison is in HImode.
-(define_peephole
-  [(set (cc0) (match_operand:HI 0 "register_operand" "d"))
-   (set (pc) (if_then_else (ge (cc0) (const_int 0))
-			   (match_operand 1 "" "")
-			   (pc)))]
-  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
-  "add %0,%0\;bcc %1"
-  [(set_attr "cc" "clobber")])
-
-(define_peephole
-  [(set (cc0) (match_operand:HI 0 "register_operand" "d"))
-   (set (pc) (if_then_else (lt (cc0) (const_int 0))
-			   (match_operand 1 "" "")
-			   (pc)))]
-  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
-  "add %0,%0\;bcs %1"
-  [(set_attr "cc" "clobber")])
-
-(define_peephole
-  [(set (cc0) (match_operand:HI 0 "register_operand" "d"))
-   (set (pc) (if_then_else (ge (cc0) (const_int 0))
-			   (pc)
-			   (match_operand 1 "" "")))]
-  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
-  "add %0,%0\;bcs %1"
-  [(set_attr "cc" "clobber")])
-
-(define_peephole
-  [(set (cc0) (match_operand:HI 0 "register_operand" "d"))
-   (set (pc) (if_then_else (lt (cc0) (const_int 0))
-			   (pc)
-			   (match_operand 1 "" "")))]
-  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
-  "add %0,%0\;bcc %1"
-  [(set_attr "cc" "clobber")])
-
-(define_peephole
-  [(set (cc0) (match_operand:PSI 0 "register_operand" "d"))
-   (set (pc) (if_then_else (ge (cc0) (const_int 0))
-			   (match_operand 1 "" "")
-			   (pc)))]
-  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
-  "add %0,%0\;bccx %1"
-  [(set_attr "cc" "clobber")])
-
-(define_peephole
-  [(set (cc0) (match_operand:PSI 0 "register_operand" "d"))
-   (set (pc) (if_then_else (lt (cc0) (const_int 0))
-			   (match_operand 1 "" "")
-			   (pc)))]
-  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
-  "add %0,%0\;bcsx %1"
-  [(set_attr "cc" "clobber")])
-
-(define_peephole
-  [(set (cc0) (match_operand:PSI 0 "register_operand" "d"))
-   (set (pc) (if_then_else (ge (cc0) (const_int 0))
-			   (pc)
-			   (match_operand 1 "" "")))]
-  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
-  "add %0,%0\;bcsx %1"
-  [(set_attr "cc" "clobber")])
-
-(define_peephole
-  [(set (cc0) (match_operand:PSI 0 "register_operand" "d"))
-   (set (pc) (if_then_else (lt (cc0) (const_int 0))
-			   (pc)
-			   (match_operand 1 "" "")))]
-  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
-  "add %0,%0\;bccx %1"
-  [(set_attr "cc" "clobber")])
-
-;; We call out to library routines to perform 32bit addition and subtraction
-;; operations (see addsi3/subsi3 expanders for why).  These peepholes catch
-;; the trivial case where the operation could be done with an add;addc or
-;; sub;subc sequence.
-(define_peephole
-  [(set (mem:SI (reg:PSI 7)) (reg:SI 2))
-   (set (reg:SI 0) (call (match_operand:QI 1 "general_operand" "")
-			 (match_operand:HI 2 "general_operand" "")))]
-  "GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
-   && strcmp (XSTR (XEXP (operands[1], 0), 0), \"__addsi3\") == 0"
-  "add d2,d0\;addc d3,d1"
-  [(set_attr "cc" "clobber")])
-
-(define_peephole
-  [(set (mem:SI (reg:PSI 7)) (reg:SI 2))
-   (set (reg:SI 0) (call (match_operand:QI 1 "general_operand" "")
-			 (match_operand:HI 2 "general_operand" "")))]
-  "GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
-   && strcmp (XSTR (XEXP (operands[1], 0), 0), \"__subsi3\") == 0"
-  "sub d2,d0\;subc d3,d1"
-  [(set_attr "cc" "clobber")])
diff --git a/gcc/config/mn10200/mn10200_020422.h b/gcc/config/mn10200/mn10200_020422.h
deleted file mode 100755
index c36937c..0000000
--- a/gcc/config/mn10200/mn10200_020422.h
+++ /dev/null
@@ -1,1074 +0,0 @@
-/* Definitions of target machine for GNU compiler. Matsushita MN10200 series
-   Copyright (C) 1997, 2001 Free Software Foundation, Inc.
-   Contributed by Jeff Law (law@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "svr4.h"
-
-/* Get rid of svr4.h stuff we don't want/need.  */
-#undef ASM_SPEC
-#undef ASM_FINAL_SPEC
-#undef LIB_SPEC
-#undef ENDFILE_SPEC
-#undef LINK_SPEC
-#undef STARTFILE_SPEC
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-D__mn10200__ -D__MN10200__ -D__LONG_MAX__=2147483647L -D__LONG_LONG_MAX__=2147483647L -D__INT_MAX__=32767"
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-/* We don't have any switched on the mn10200.  Though there are some things
-   that might be worth a switch:
-
-   -mspace to optimize even more for space.
-
-   -mrelax to enable the relaxing linker.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  {{ "", TARGET_DEFAULT}}
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 0
-#endif
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fprintf (stderr, " (MN10200)");
-
-
-/* Target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is not true on the Matsushita MN10300.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* This is not true on the Matsushita MN10200.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered.
-   This is not true on the Matsushita MN10200.  */
-#define WORDS_BIG_ENDIAN 0
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.
-
-   This is a white lie.  Registers are really 24bits, but most operations
-   only operate on 16 bits.   GCC chokes badly if we set this to a value
-   that is not a power of two.  */
-#define BITS_PER_WORD		16
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD		2
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.
-
-   This differs from Pmode because we need to allocate 32bits of space
-   to hold the 24bit pointers on this machine.  */
-#define POINTER_SIZE 		32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY		16
-
-/* The stack goes in 16 bit lumps.  */
-#define STACK_BOUNDARY 		16
-
-/* Allocation boundary (in *bits*) for the code of a function.
-   8 is the minimum boundary; it's unclear if bigger alignments
-   would improve performance.  */
-#define FUNCTION_BOUNDARY 8
-
-/* No data type wants to be aligned rounder than this.   */
-#define BIGGEST_ALIGNMENT	16
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* Seems to be how the Matsushita compiler does things, and there's
-   no real reason to be different.  */
-#define STRUCTURE_SIZE_BOUNDARY 16
-#undef PCC_BITFIELD_TYPE_MATTERS
-
-/* Define this if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   XXX Long term we should probably expose the MDR register, we use
-   it for division, multiplication, and some extension operations.  */
-
-#define FIRST_PSEUDO_REGISTER 8
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.  */
-
-#define FIXED_REGISTERS \
-  { 0, 0, 0, 0, 0, 0, 0, 1}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you
-   like.  */
-
-#define CALL_USED_REGISTERS \
-  { 1, 1, 0, 0, 1, 0, 0, 1}
-
-#define REG_ALLOC_ORDER \
-  { 0, 1, 4, 2, 3, 5, 6, 7}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((MODE) == PSImode ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
-			    / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
-   MODE.
-
-   We allow any register to hold a PSImode value.  We allow any register
-   to hold values <= 16 bits.  For values > 16 bits we require aligned
-   register pairs.  */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((MODE) == PSImode ? 1 : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 2)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  (MODE1 == MODE2 || (GET_MODE_SIZE (MODE1) <= 2 && GET_MODE_SIZE (MODE2) <= 2))
-
-/* 4 data, and effectively 2 address registers is small as far as I'm
-   concerned.  Especially since we use 2 data registers for argument
-   passing and return values.
-
-   We used to define CLASS_LIKELY_SPILLED_P as true for DATA_REGS too,
-   but we've made improvements to the port which greatly reduce register
-   pressure.  As a result we no longer need to define CLASS_LIKELY_SPILLED_P
-   for DATA_REGS (and by not defining it we get significantly better code).  */
-#define SMALL_REGISTER_CLASSES 1
-#define CLASS_LIKELY_SPILLED_P(CLASS) (CLASS == ADDRESS_REGS)
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-enum reg_class {
-  NO_REGS, DATA_REGS, ADDRESS_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
-{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \
-  "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS  			\
-{     0,		/* No regs      */	\
-   0x0f,		/* DATA_REGS */		\
-   0xf0,		/* ADDRESS_REGS */	\
-   0xff,		/* GENERAL_REGS */    	\
-   0xff,		/* ALL_REGS 	*/	\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) \
-  ((REGNO) < 4 ? DATA_REGS : ADDRESS_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS DATA_REGS
-#define BASE_REG_CLASS  ADDRESS_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'd' ? DATA_REGS : \
-   (C) == 'a' ? ADDRESS_REGS : NO_REGS)
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
- 
-#define REGNO_OK_FOR_BASE_P(regno) \
-  (((regno) > 3 && regno < FIRST_PSEUDO_REGISTER)	\
-   || (reg_renumber[regno] > 3 && reg_renumber[regno] < FIRST_PSEUDO_REGISTER))
-
-#define REGNO_OK_FOR_INDEX_P(regno) \
-  (((regno) >= 0 && regno < 4)	\
-   || (reg_renumber[regno] >= 0 && reg_renumber[regno] < 4))
-
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
-  ((GET_MODE (X) != PSImode) ? DATA_REGS : CLASS)
-
-/* We want to use DATA_REGS for anything that is not PSImode.  */
-#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
-  ((MODE != PSImode) ? DATA_REGS : CLASS)
-
-/* We have/need secondary reloads on the mn10200.  Mostly to deal
-   with problems using address registers.  */
-#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
-  secondary_reload_class(CLASS,MODE,IN, 1)
-
-#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,IN) \
-  secondary_reload_class(CLASS,MODE,IN, 0)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
-  ((MODE) == PSImode ? 1 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* The letters I, J, K, L, M, N, O, P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.  */
-
-#define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100)
-#define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000)
-
-#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
-#define CONST_OK_FOR_J(VALUE) ((VALUE) >= 1 && (VALUE) <= 3)
-#define CONST_OK_FOR_K(VALUE) ((VALUE) >= 1 && (VALUE) <= 4)
-#define CONST_OK_FOR_L(VALUE) ((VALUE) == 15)
-#define CONST_OK_FOR_M(VALUE) ((VALUE) == 255)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
-   (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
-   (C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
-   (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
-   (C) == 'M' ? CONST_OK_FOR_M (VALUE) : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself. 
-     
-  `G' is a floating-point zero.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT	\
-		 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))		\
-   : 0)
-
-
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-
-#define STARTING_FRAME_OFFSET 0
-
-/* Offset of first parameter from the argument pointer register value.  */
-/* Is equal to the size of the saved fp + pc, even if an fp isn't
-   saved since the value is used before we know.  */
-
-#define FIRST_PARM_OFFSET(FNDECL) (current_function_needs_context ? 8 : 4)
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 7
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 6
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 6
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 4
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.
-
-   We allow frame pointers to be eliminated when not having one will
-   not interfere with debugging.  */
-#define ACCUMULATE_OUTGOING_ARGS
-#define FRAME_POINTER_REQUIRED 0
-#define CAN_DEBUG_WITHOUT_FP
-
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved.  */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = total_frame_size()
-
-/* Various type size information.
-
-   The mn10200 has a limited number of small registers.  Sizes of basic
-   data types are adjusted accordingly.  */
-#define SHORT_TYPE_SIZE         16
-#define INT_TYPE_SIZE           16
-#define LONG_TYPE_SIZE          32
-#define LONG_LONG_TYPE_SIZE     32
-#define FLOAT_TYPE_SIZE         32
-#define DOUBLE_TYPE_SIZE        32
-#define LONG_DOUBLE_TYPE_SIZE   DOUBLE_TYPE_SIZE
-
-/* Any size less than 64bits will work; but a smarter definition
-   can make G++ code smaller and faster.  Most operations on the
-   mn10200 occur on 16bit hunks, so the best size for a boolean
-   is 16bits.  */
-#define BOOL_TYPE_SIZE		16
-
-/* The difference of two pointers must be at least 24bits since pointers
-   are 24bits; however, no basic data type is 24bits, so we have to round
-   up to a 32bits for the difference of pointers.  */
-#undef SIZE_TYPE
-#undef PTRDIFF_TYPE
-#define SIZE_TYPE "long unsigned int"
-#define PTRDIFF_TYPE "long unsigned int"
-
-/* Note sizeof (WCHAR_TYPE) must be equal to the value of WCHAR_TYPE_SIZE!  */
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-#define MAX_FIXED_MODE_SIZE     32
-
-/* A guess for the MN10200.  */
-#define PROMOTE_PROTOTYPES 1
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* 1 if N is a possible register number for function argument passing.  */
-
-#define FUNCTION_ARG_REGNO_P(N) ((N) <= 1)
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.  */
-
-#define CUMULATIVE_ARGS struct cum_arg
-struct cum_arg { int nbytes; };
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the MN10200, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM).nbytes = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM).nbytes += ((MODE) != BLKmode			\
-	? (MODE) == PSImode ? 2 :			\
-	    (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD \
-	: (int_size_in_bytes (TYPE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-extern struct rtx_def *function_arg();
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  function_arg (&CUM, MODE, TYPE, NAMED)
-
-
-/* For "large" items, we pass them by invisible reference, and the
-   callee is responsible for copying the data item if it might be
-   modified.  */
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)		\
-  ((TYPE) && int_size_in_bytes (TYPE) > 8)
- 
-#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
-  ((TYPE) && int_size_in_bytes (TYPE) > 8)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.   */
-   
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), TYPE_MODE (VALTYPE) == PSImode ? 4 : 0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, (MODE) == PSImode ? 4 : 0)
-
-/* 1 if N is a possible register number for a function value.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 4)
-
-/* Return values > 8 bytes in length in memory.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-#define RETURN_IN_MEMORY(TYPE)  \
-  (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode)
-
-/* Register in which address to store a structure value
-   is passed to a function.  On the MN10200 it's passed as
-   the first parameter.  */
-
-#define STRUCT_VALUE 0
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.
-
-   ?!? Profiling is not currently supported.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) ;
-
-/* Yes, we actually support trampolines on this machine, even though
-   nobody is likely to ever use them.  */
-#define TRAMPOLINE_TEMPLATE(FILE)			\
-  do {							\
-    fprintf (FILE, "\t.byte 0xfd\n");			\
-    fprintf (FILE, "\t.byte 0x00\n");			\
-    fprintf (FILE, "\t.byte 0x00\n");			\
-    fprintf (FILE, "\tmov (a3),a0\n");			\
-    fprintf (FILE, "\tadd -4,a3\n");			\
-    fprintf (FILE, "\tmov a0,(0,a3)\n");		\
-    fprintf (FILE, "\tmov (21,a0),a0\n");		\
-    fprintf (FILE, "\tmov a0,(4,a3)\n");		\
-    fprintf (FILE, "\tmov (0,a3),a0\n");		\
-    fprintf (FILE, "\tmov (17,a0),a0\n");		\
-    fprintf (FILE, "\tadd 4,a3\n");			\
-    fprintf (FILE, "\trts\n");				\
-    fprintf (FILE, "\t.long 0\n");			\
-    fprintf (FILE, "\t.long 0\n");			\
-  } while (0)
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 0x1c
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx (MEM, PSImode, plus_constant ((TRAMP), 20)),  \
-		  (CXT));						\
-  emit_move_insn (gen_rtx (MEM, PSImode, plus_constant ((TRAMP), 24)),  \
-		  (FNADDR));						\
-}
-
-/* A C expression whose value is RTL representing the value of the return
-   address for the frame COUNT steps up from the current frame.  */
-
-#define RETURN_ADDR_RTX(COUNT, FRAME)   \
-  ((COUNT == 0)                         \
-   ? gen_rtx (MEM, Pmode, frame_pointer_rtx) \
-   : (rtx) 0)
-
-
-/* Addressing modes, and classification of registers for them.  */
-
-
-/* 1 if X is an rtx for a constant that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   CONSTANT_P (X)
-
-/* Extra constraints.  */
-#define OK_FOR_R(OP) \
-   (GET_CODE (OP) == MEM					\
-    && GET_MODE (OP) == QImode					\
-    && REG_P (XEXP (OP, 0)))
- 
-/* Q is used for sp + <something> in the {zero,sign}_extendpsisi2 patterns.  */
-#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'R' ? OK_FOR_R (OP) : \
-  (C) == 'S' ? GET_CODE (OP) == SYMBOL_REF : \
-  (C) == 'Q' ? GET_CODE (OP) == PLUS : 0)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X)  \
-  (((REGNO (X) >= 0 && REGNO(X) <= 3) || REGNO (X) >= FIRST_PSEUDO_REGISTER))
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-  (((REGNO (X) >= 4 && REGNO(X) <= 8) || REGNO (X) >= FIRST_PSEUDO_REGISTER))
-#else
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) \
-  REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-  REGNO_OK_FOR_BASE_P (REGNO (X))
-#endif
-
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   We used to allow reg+reg addresses for QImode and HImode; however,
-   they tended to cause the register allocator to run out of registers.
-   Basically, an indexed load/store always keeps 2 data and one address
-   register live, which is just too many for this machine.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
-   except for CONSTANT_ADDRESS_P which is actually machine-independent.  */
-
-/* Accept either REG or SUBREG where a register is valid.  */
-  
-#define RTX_OK_FOR_BASE_P(X)					\
-  ((REG_P (X) && REG_OK_FOR_BASE_P (X))				\
-   || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))		\
-       && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)    	\
-{							\
-  if ((MODE != PSImode) && CONSTANT_ADDRESS_P (X))	\
-    goto ADDR;						\
-  if (RTX_OK_FOR_BASE_P (X))				\
-    goto ADDR;						\
-  if (GET_CODE (X) == PLUS)				\
-    {							\
-      rtx base = 0, index = 0;				\
-      if (RTX_OK_FOR_BASE_P (XEXP (X, 0)))		\
-	base = XEXP (X, 0), index = XEXP (X, 1);	\
-      if (RTX_OK_FOR_BASE_P (XEXP (X, 1)))		\
-	base = XEXP (X, 1), index = XEXP (X, 0);	\
-      if (base != 0 && index != 0)			\
-	{						\
-	  if (GET_CODE (index) == CONST_INT)		\
-	    goto ADDR;					\
-	}						\
-    }							\
-}
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.   */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)  {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  {}
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  No extra ones are needed for the vax.  */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define CC_OVERFLOW_UNUSABLE 0x200
-#define CC_NO_CARRY CC_NO_OVERFLOW
-#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
-
-/* The mn10200 has a limited number of registers, so CSE of function
-   addresses generally makes code worse due to register pressure.  */
-#define NO_FUNCTION_CSE
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:							\
-    /* Zeros are extremely cheap.  */					\
-    if (INTVAL (RTX) == 0)						\
-      return 0;								\
-    /* If it fits in 8 bits, then it's still relatively cheap.  */	\
-    if (INT_8_BITS (INTVAL (RTX)))					\
-      return 1;								\
-    /* This is the "base" cost, includes constants where either the	\
-       upper or lower 16bits are all zeros.  */				\
-    if (INT_16_BITS (INTVAL (RTX))					\
-	|| (INTVAL (RTX) & 0xffff) == 0					\
-	|| (INTVAL (RTX) & 0xffff0000) == 0)				\
-      return 2;								\
-    return 4;								\
-  /* These are more costly than a CONST_INT, but we can relax them,	\
-     so they're less costly than a CONST_DOUBLE.  */			\
-  case CONST:								\
-  case LABEL_REF:							\
-  case SYMBOL_REF:							\
-    return 6;								\
-  /* We don't optimize CONST_DOUBLEs well nor do we relax them well,	\
-     so their cost is very high.  */					\
-  case CONST_DOUBLE:							\
-    return 8;
-
-/* Make moves between different classes more expensive than moves
-   within the same class.  */
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)  (CLASS1 != CLASS2 ? 4 : 2)
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE. 
-
-   ?!? This probably needs more work.  The definitions below were first
-   taken from the H8 port, then tweaked slightly to improve code density
-   on various sample codes.  */
-
-#define RTX_COSTS(RTX,CODE,OUTER_CODE) \
-  case MOD:						\
-  case DIV:						\
-    return 8;						\
-  case MULT:						\
-    return (GET_MODE (RTX) == SImode ? 20 : 8);
-
-/* Nonzero if access to memory by bytes or half words is no faster
-   than accessing full words.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* According expr.c, a value of around 6 should minimize code size, and
-   for the MN10200 series, code size our primary concern.  */
-#define MOVE_RATIO 6
-
-#define TEXT_SECTION_ASM_OP "\t.section .text"
-#define DATA_SECTION_ASM_OP "\t.section .data"
-#define BSS_SECTION_ASM_OP "\t.section .bss"
-
-/* Output at beginning/end of assembler file.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) asm_file_start(FILE)
-
-#define ASM_COMMENT_START "#"
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* This is how to output an assembler line defining a `double' constant.
-   It is .dfloat or .gfloat, depending.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.double %s\n", dstr);		\
-   } while (0)
-
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.float %s\n", dstr);		\
-   } while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE, VALUE)		\
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE, VALUE)		\
-( fprintf (FILE, "\t.hword "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE, VALUE)		\
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-#define ASM_OUTPUT_BYTE(FILE, VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* This says how to output the assembler to define a global
-   uninitialized but not common symbol.
-   Try to use asm_output_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE, NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE, NAME)	\
-  do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE, NAME)	          \
-  do {                                            \
-  char* real_name;                                \
-  STRIP_NAME_ENCODING (real_name, (NAME));        \
-  fprintf (FILE, "_%s", real_name);               \
-  } while (0)           
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
-
-/* This is how we tell the assembler that two symbols have the same value.  */
-
-#define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
-  do { assemble_name(FILE, NAME1); 	 \
-       fputs(" = ", FILE);		 \
-       assemble_name(FILE, NAME2);	 \
-       fputc('\n', FILE); } while (0)
-
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3"}
-
-/* Print an instruction operand X on file FILE.
-   look in mn10200.c for details */
-
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand(FILE,X,CODE)
-
-/* Print a memory operand whose address is X, on file FILE.
-   This uses a function in output-vax.c.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-  asm_fprintf (FILE, "\t%s .L%d\n", ".long", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL)
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", (LOG))
-
-/* We don't have to worry about dbx compatibility for the mn10200.  */
-#define DEFAULT_GDB_EXTENSIONS 1
-
-/* Use stabs debugging info by default.  */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#define DBX_REGISTER_NUMBER(REGNO) REGNO
-
-/* GDB always assumes the current function's frame begins at the value
-   of the stack pointer upon entry to the current function.  Accessing
-   local variables and parameters passed on the stack is done using the
-   base of the frame + an offset provided by GCC.
-
-   For functions which have frame pointers this method works fine;
-   the (frame pointer) == (stack pointer at function entry) and GCC provides
-   an offset relative to the frame pointer.
-
-   This loses for functions without a frame pointer; GCC provides an offset
-   which is relative to the stack pointer after adjusting for the function's
-   frame size.  GDB would prefer the offset to be relative to the value of
-   the stack pointer at the function's entry.  Yuk!  */
-#define DEBUGGER_AUTO_OFFSET(X) \
-  ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
-    + (frame_pointer_needed ? 0 : -total_frame_size ()))
-
-#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
-  ((GET_CODE (X) == PLUS ? OFFSET : 0) \
-    + (frame_pointer_needed ? 0 : -total_frame_size ()))
-
-/* Define to use software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion. */
-#define REAL_ARITHMETIC
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE Pmode
-
-/* Define this if the case instruction drops through after the table
-   when the index is out of range.  Don't define it if the case insn
-   jumps to the default label instead.  */
-#define CASE_DROPS_THROUGH
-
-/* Dispatch tables on the mn10200 are extremely expensive in terms of code
-   and readonly data size.  So we crank up the case threshold value to
-   encourage a series of if/else comparisons to implement many small switch
-   statements.  In theory, this value could be increased much more if we
-   were solely optimizing for space, but we keep it "reasonable" to avoid
-   serious code efficiency lossage.  */
-#define CASE_VALUES_THRESHOLD 8
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* We could define this either way.  Using ZERO_EXTEND for QImode makes slightly
-   fast and more compact code.  */
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.  */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX	2
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) (OUTPREC != 32)
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode PSImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* Perform target dependent optabs initialization.  */
-#define MODHI3_LIBCALL "__modhi3"
-#define DIVHI3_LIBCALL "__divhi3"
-
-#define INIT_TARGET_OPTABS \
-  do { \
-    sdiv_optab->handlers[(int) HImode].libfunc		\
-      = gen_rtx (SYMBOL_REF, Pmode, DIVHI3_LIBCALL);	\
-    smod_optab->handlers[(int) HImode].libfunc		\
-      = gen_rtx (SYMBOL_REF, Pmode, MODHI3_LIBCALL);	\
-  } while (0)
-
-/* The assembler op to get a word.  */
-
-#define FILE_ASM_OP "\t.file\n"
-
-extern void asm_file_start ();
-extern void print_operand ();
-extern void print_operand_address ();
-extern void expand_prologue ();
-extern void expand_epilogue ();
-extern void notice_update_cc ();
-extern int call_address_operand ();
-extern enum reg_class secondary_reload_class ();
-extern char *emit_a_shift ();
-extern int current_function_needs_context;
-extern char *output_tst ();
-extern int extendpsi_operand ();
-extern int rtx_equal_function_value_matters;
-extern struct rtx_def *zero_dreg;
-extern struct rtx_def *zero_areg;
diff --git a/gcc/config/mn10200/t-mn10200 b/gcc/config/mn10200/t-mn10200
deleted file mode 100755
index d02d151..0000000
--- a/gcc/config/mn10200/t-mn10200
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBGCC1=libgcc1.null
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = mn10200/lib1funcs.asm
-LIB1ASMFUNCS    = _divhi3 \
-		  _modhi3 \
-		  _addsi3 \
-		  _subsi3 \
-		  _mulsi3 \
-		  _ashlsi3 \
-		  _lshrsi3 \
-		  _ashrsi3 \
-		  _negsi2_d0 \
-		  _negsi2_d2 \
-		  _zero_extendpsisi2_d0 \
-		  _zero_extendpsisi2_d2 \
-		  _sign_extendpsisi2_d0 \
-		  _sign_extendpsisi2_d2 \
-		  _truncsipsi2_d0_d0 \
-		  _truncsipsi2_d0_d1 \
-		  _truncsipsi2_d0_d2 \
-		  _truncsipsi2_d0_d3 \
-		  _truncsipsi2_d2_d0 \
-		  _truncsipsi2_d2_d1 \
-		  _truncsipsi2_d2_d2 \
-		  _truncsipsi2_d2_d3 \
-		  _cmpsi2 \
-		  _ucmpsi2 \
-		  _prologue \
-		  _epilogue_a0 \
-		  _epilogue_d0 \
-		  _epilogue_noreturn
-
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-
-# We do not have DF or DI types, so fake out the libgcc2 compilation.
-TARGET_LIBGCC2_CFLAGS=-DDF=SF -DDI=SI
-LIB2FUNCS_EXTRA = $(srcdir)/config/mn10200/udivmodsi4.c \
-	$(srcdir)/config/mn10200/divmod.c $(srcdir)/config/mn10200/udivmod.c
-
-# We want fine grained libraries, so use the new code to build the
-# floating point emulation libraries.  The mn10200 only has single
-# precision floating point.
-FPBIT = fp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#define FLOAT_ONLY' >> fp-bit.c
-	echo '#define SMALL_MACHINE' >> fp-bit.c
-	echo '#define CMPtype HItype' >> fp-bit.c
-	echo '#ifdef __LITTLE_ENDIAN__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>fp-bit.c
-	echo '#endif' 		>> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
diff --git a/gcc/config/mn10200/udivmod.c b/gcc/config/mn10200/udivmod.c
deleted file mode 100755
index 1395e9c..0000000
--- a/gcc/config/mn10200/udivmod.c
+++ /dev/null
@@ -1,14 +0,0 @@
-long udivmodsi4 ();
-
-long
-__udivsi3 (long a, long b)
-{
-  return udivmodsi4 (a, b, 0);
-}
-
-long
-__umodsi3 (long a, long b)
-{
-  return udivmodsi4 (a, b, 1);
-}
-
diff --git a/gcc/config/mn10200/udivmodsi4.c b/gcc/config/mn10200/udivmodsi4.c
deleted file mode 100755
index 83c2340..0000000
--- a/gcc/config/mn10200/udivmodsi4.c
+++ /dev/null
@@ -1,24 +0,0 @@
-unsigned long
-udivmodsi4(unsigned long num, unsigned long den, int modwanted)
-{
-  unsigned long bit = 1;
-  unsigned long res = 0;
-
-  while (den < num && bit && !(den & (1L<<31)))
-    {
-      den <<=1;
-      bit <<=1;
-    }
-  while (bit)
-    {
-      if (num >= den)
-	{
-	  num -= den;
-	  res |= bit;
-	}
-      bit >>=1;
-      den >>=1;
-    }
-  if (modwanted) return num;
-  return res;
-}
diff --git a/gcc/config/mn10200/xm-mn10200.h b/gcc/config/mn10200/xm-mn10200.h
deleted file mode 100755
index 7ebac70..0000000
--- a/gcc/config/mn10200/xm-mn10200.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Configuration for Matsushita MN10200. 
-   Copyright (C) 1997 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 16
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-
-#include "tm.h"
-
-#ifndef __STDC__
-extern char *malloc (), *realloc (), *calloc ();
-#else
-extern void *malloc (), *realloc (), *calloc ();
-#endif
-extern void free ();
diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c
deleted file mode 100755
index 325d8bd..0000000
--- a/gcc/config/mn10300/mn10300.c
+++ /dev/null
@@ -1,1006 +0,0 @@
-/* Subroutines for insn-output.c for Matsushita MN10300 series
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Jeff Law (law@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#include "expr.h"
-#include "tree.h"
-#include "obstack.h"
-
-/* The size of the callee register save area.  Right now we save everything
-   on entry since it costs us nothing in code size.  It does cost us from a
-   speed standpoint, so we want to optimize this sooner or later.  */
-#define REG_SAVE_BYTES (4 * regs_ever_live[2] \
-			+ 4 * regs_ever_live[3] \
-			+ 4 * regs_ever_live[6] \
-			+ 4 * regs_ever_live[7])
-
-#undef REG_SAVE_BYTES
-#define REG_SAVE_BYTES (4 * regs_ever_live[2] \
-			+ 4 * regs_ever_live[3] \
-		        + 4 * regs_ever_live[6] \
-			+ 4 * regs_ever_live[7] \
-			+ 16 * (regs_ever_live[14] || regs_ever_live[15] \
-				|| regs_ever_live[16] || regs_ever_live[17]))
-
-void
-asm_file_start (file)
-     FILE *file;
-{
-  fprintf (file, "#\tGCC For the Matsushita MN10300\n");
-  if (optimize)
-    fprintf (file, "# -O%d\n", optimize);
-  else
-    fprintf (file, "\n\n");
-
-  if (TARGET_AM33)
-    fprintf (file, "\t.am33\n");
-  output_file_directive (file, main_input_filename);
-}
-
-
-/* Print operand X using operand code CODE to assembly language output file
-   FILE.  */
-
-void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
-{
-  switch (code)
-    {
-      case 'b':
-      case 'B':
-	/* These are normal and reversed branches.  */
-	switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
-	  {
-	  case NE:
-	    fprintf (file, "ne");
-	    break;
-	  case EQ:
-	    fprintf (file, "eq");
-	    break;
-	  case GE:
-	    fprintf (file, "ge");
-	    break;
-	  case GT:
-	    fprintf (file, "gt");
-	    break;
-	  case LE:
-	    fprintf (file, "le");
-	    break;
-	  case LT:
-	    fprintf (file, "lt");
-	    break;
-	  case GEU:
-	    fprintf (file, "cc");
-	    break;
-	  case GTU:
-	    fprintf (file, "hi");
-	    break;
-	  case LEU:
-	    fprintf (file, "ls");
-	    break;
-	  case LTU:
-	    fprintf (file, "cs");
-	    break;
-	  default:
-	    abort ();
-	  }
-	break;
-      case 'C':
-	/* This is used for the operand to a call instruction;
-	   if it's a REG, enclose it in parens, else output
-	   the operand normally.  */
-	if (GET_CODE (x) == REG)
-	  {
-	    fputc ('(', file);
-	    print_operand (file, x, 0);
-	    fputc (')', file);
-	  }
-	else
-	  print_operand (file, x, 0);
-	break;
-     
-      /* These are the least significant word in a 64bit value.  */
-      case 'L':
-	switch (GET_CODE (x))
-	  {
-	  case MEM:
-	    fputc ('(', file);
-	    output_address (XEXP (x, 0));
-	    fputc (')', file);
-	    break;
-
-	  case REG:
-	    fprintf (file, "%s", reg_names[REGNO (x)]);
-	    break;
-
-	  case SUBREG:
-	    fprintf (file, "%s",
-		     reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]);
-	    break;
-
-	  case CONST_DOUBLE:
-	      {
-		long val[2];
-		REAL_VALUE_TYPE rv;
-
-		switch (GET_MODE (x))
-		  {
-		    case DFmode:
-		      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-		      REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
-		      print_operand_address (file, GEN_INT (val[0]));
-		      break;;
-		    case SFmode:
-		      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-		      REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
-		      print_operand_address (file, GEN_INT (val[0]));
-		      break;;
-		    case VOIDmode:
-		    case DImode:
-		      print_operand_address (file,
-					     GEN_INT (CONST_DOUBLE_LOW (x)));
-		      break;
-		  }
-		break;
-	      }
-
-	  case CONST_INT:
-	    print_operand_address (file, x);
-	    break;
-
-	  default:
-	    abort ();
-	  }
-	break;
-
-      /* Similarly, but for the most significant word.  */
-      case 'H':
-	switch (GET_CODE (x))
-	  {
-	  case MEM:
-	    fputc ('(', file);
-	    x = adj_offsettable_operand (x, 4);
-	    output_address (XEXP (x, 0));
-	    fputc (')', file);
-	    break;
-
-	  case REG:
-	    fprintf (file, "%s", reg_names[REGNO (x) + 1]);
-	    break;
-
-	  case SUBREG:
-	    fprintf (file, "%s",
-		     reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)] + 1);
-	    break;
-
-	  case CONST_DOUBLE:
-	      {
-		long val[2];
-		REAL_VALUE_TYPE rv;
-
-		switch (GET_MODE (x))
-		  {
-		    case DFmode:
-		      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-		      REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
-		      print_operand_address (file, GEN_INT (val[1]));
-		      break;;
-		    case SFmode:
-		      abort ();
-		    case VOIDmode:
-		    case DImode:
-		      print_operand_address (file, 
-					     GEN_INT (CONST_DOUBLE_HIGH (x)));
-		      break;
-		  }
-		break;
-	      }
-
-	  case CONST_INT:
-	    if (INTVAL (x) < 0)
-	      print_operand_address (file, GEN_INT (-1));
- 	    else
-	      print_operand_address (file, GEN_INT (0));
-	    break;
-	  default:
-	    abort ();
-	  }
-	break;
-
-      case 'A':
-	fputc ('(', file);
-	if (GET_CODE (XEXP (x, 0)) == REG)
-	  output_address (gen_rtx (PLUS, SImode, XEXP (x, 0), GEN_INT (0)));
-	else
-	  output_address (XEXP (x, 0));
-	fputc (')', file);
-	break;
-
-      case 'N':
-	output_address (GEN_INT ((~INTVAL (x)) & 0xff));
-	break;
-
-      /* For shift counts.  The hardware ignores the upper bits of
-	 any immediate, but the assembler will flag an out of range
-	 shift count as an error.  So we mask off the high bits
-	 of the immediate here.  */
-      case 'S':
-	if (GET_CODE (x) == CONST_INT)
-	  {
-	    fprintf (file, "%d", INTVAL (x) & 0x1f);
-	    break;
-	  }
-	/* FALL THROUGH */
-
-      default:
-	switch (GET_CODE (x))
-	  {
-	  case MEM:
-	    fputc ('(', file);
-	    output_address (XEXP (x, 0));
-	    fputc (')', file);
-	    break;
-
-	  case PLUS:
-	    output_address (x);
-	    break;
-
-	  case REG:
-	    fprintf (file, "%s", reg_names[REGNO (x)]);
-	    break;
-
-	  case SUBREG:
-	    fprintf (file, "%s",
-		     reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]);
-	    break;
-
-	  /* This will only be single precision....  */
-	  case CONST_DOUBLE:
-	    {
-	      unsigned long val;
-	      REAL_VALUE_TYPE rv;
-
-	      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-	      REAL_VALUE_TO_TARGET_SINGLE (rv, val);
-	      print_operand_address (file, GEN_INT (val));
-	      break;
-	    }
-
-	  case CONST_INT:
-	  case SYMBOL_REF:
-	  case CONST:
-	  case LABEL_REF:
-	  case CODE_LABEL:
-	    print_operand_address (file, x);
-	    break;
-	  default:
-	    abort ();
-	  }
-	break;
-   }
-}
-
-/* Output assembly language output for the address ADDR to FILE.  */
-
-void
-print_operand_address (file, addr)
-     FILE *file;
-     rtx addr;
-{
-  switch (GET_CODE (addr))
-    {
-    case POST_INC:
-      print_operand_address (file, XEXP (addr, 0));
-      fputc ('+', file);
-      break;
-    case REG:
-      if (addr == stack_pointer_rtx)
-	print_operand_address (file, gen_rtx (PLUS, SImode,
-					      stack_pointer_rtx,
-					      GEN_INT (0)));
-      else
-	print_operand (file, addr, 0);
-      break;
-    case PLUS:
-      {
-	rtx base, index;
-	if (REG_P (XEXP (addr, 0))
-	    && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
-	  base = XEXP (addr, 0), index = XEXP (addr, 1);
-	else if (REG_P (XEXP (addr, 1))
-	    && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
-	  base = XEXP (addr, 1), index = XEXP (addr, 0);
-      	else
-	  abort ();
-	print_operand (file, index, 0);
-	fputc (',', file);
-	print_operand (file, base, 0);;
-	break;
-      }
-    case SYMBOL_REF:
-      output_addr_const (file, addr);
-      break;
-    default:
-      output_addr_const (file, addr);
-      break;
-    }
-}
-
-int
-can_use_return_insn ()
-{
-  /* size includes the fixed stack space needed for function calls.  */
-  int size = get_frame_size () + current_function_outgoing_args_size;
-
-  /* And space for the return pointer.  */
-  size += current_function_outgoing_args_size ? 4 : 0;
-
-  return (reload_completed
-	  && size == 0
-	  && !regs_ever_live[2]
-	  && !regs_ever_live[3]
-	  && !regs_ever_live[6]
-	  && !regs_ever_live[7]
-	  && !regs_ever_live[14]
-	  && !regs_ever_live[15]
-	  && !regs_ever_live[16]
-	  && !regs_ever_live[17]
-	  && !frame_pointer_needed);
-}
-
-void
-expand_prologue ()
-{
-  unsigned int size;
-
-  /* SIZE includes the fixed stack space needed for function calls.  */
-  size = get_frame_size () + current_function_outgoing_args_size;
-  size += (current_function_outgoing_args_size ? 4 : 0);
-
-  /* If this is an old-style varargs function, then its arguments
-     need to be flushed back to the stack.  */
-  if (current_function_varargs)
-    {
-      emit_move_insn (gen_rtx (MEM, SImode,
-			       gen_rtx (PLUS, Pmode, stack_pointer_rtx,
-					GEN_INT (4))),
-		      gen_rtx (REG, SImode, 0));
-      emit_move_insn (gen_rtx (MEM, SImode,
-			       gen_rtx (PLUS, Pmode, stack_pointer_rtx,
-					GEN_INT (8))),
-		      gen_rtx (REG, SImode, 1));
-    }
-
-  /* And now store all the registers onto the stack with a
-     single two byte instruction.  */
-  if (regs_ever_live[2] || regs_ever_live[3]
-      || regs_ever_live[6] || regs_ever_live[7]
-      || regs_ever_live[14] || regs_ever_live[15]
-      || regs_ever_live[16] || regs_ever_live[17]
-      || frame_pointer_needed)
-    emit_insn (gen_store_movm ());
-
-  /* Now put the frame pointer into the frame pointer register.  */
-  if (frame_pointer_needed)
-    emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
-
-  /* Allocate stack for this frame.  */
-  if (size)
-    emit_insn (gen_addsi3 (stack_pointer_rtx,
-			   stack_pointer_rtx,
-			   GEN_INT (-size)));
-}
-
-void
-expand_epilogue ()
-{
-  unsigned int size;
-
-  /* SIZE includes the fixed stack space needed for function calls.  */
-  size = get_frame_size () + current_function_outgoing_args_size;
-  size += (current_function_outgoing_args_size ? 4 : 0);
-
-  /* Maybe cut back the stack, except for the register save area.
-
-     If the frame pointer exists, then use the frame pointer to
-     cut back the stack.
-
-     If the stack size + register save area is more than 255 bytes,
-     then the stack must be cut back here since the size + register
-     save size is too big for a ret/retf instruction. 
-
-     Else leave it alone, it will be cut back as part of the
-     ret/retf instruction, or there wasn't any stack to begin with.
-
-     Under no circumstanes should the register save area be
-     deallocated here, that would leave a window where an interrupt
-     could occur and trash the register save area.  */
-  if (frame_pointer_needed)
-    {
-      emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
-      size = 0;
-    }
-  else if ((regs_ever_live[2] || regs_ever_live[3]
-	    || regs_ever_live[14] || regs_ever_live[15]
-	    || regs_ever_live[16] || regs_ever_live[17]
-	    || regs_ever_live[6] || regs_ever_live[7])
-	   && size + REG_SAVE_BYTES > 255)
-    {
-      emit_insn (gen_addsi3 (stack_pointer_rtx,
-			     stack_pointer_rtx,
-			     GEN_INT (size)));
-      size = 0;
-    }
-
-  /* For simplicity, we just movm all the callee saved registers to
-     the stack with one instruction.
-
-     ?!? Only save registers which are actually used.  Reduces
-     stack requirements and is faster.  */
-  if (regs_ever_live[2] || regs_ever_live[3]
-      || regs_ever_live[6] || regs_ever_live[7]
-      || regs_ever_live[14] || regs_ever_live[15]
-      || regs_ever_live[16] || regs_ever_live[17]
-      || frame_pointer_needed)
-    emit_jump_insn (gen_return_internal_regs (GEN_INT (size + REG_SAVE_BYTES)));
-  else
-    {
-      if (size)
-	{
-	  emit_insn (gen_addsi3 (stack_pointer_rtx,
-				 stack_pointer_rtx,
-				 GEN_INT (size)));
-	  emit_jump_insn (gen_return_internal ());
-	}
-      else
-	{
-	  emit_jump_insn (gen_return ());
-	}
-    }
-}
-
-/* Update the condition code from the insn.  */
-
-void
-notice_update_cc (body, insn)
-     rtx body;
-     rtx insn;
-{
-  switch (get_attr_cc (insn))
-    {
-    case CC_NONE:
-      /* Insn does not affect CC at all.  */
-      break;
-
-    case CC_NONE_0HIT:
-      /* Insn does not change CC, but the 0'th operand has been changed.  */
-      if (cc_status.value1 != 0
-	  && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1))
-	cc_status.value1 = 0;
-      break;
-
-    case CC_SET_ZN:
-      /* Insn sets the Z,N flags of CC to recog_operand[0].
-	 V,C are unusable.  */
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
-      cc_status.value1 = recog_operand[0];
-      break;
-
-    case CC_SET_ZNV:
-      /* Insn sets the Z,N,V flags of CC to recog_operand[0].
-	 C is unusable.  */
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_NO_CARRY;
-      cc_status.value1 = recog_operand[0];
-      break;
-
-    case CC_COMPARE:
-      /* The insn is a compare instruction.  */
-      CC_STATUS_INIT;
-      cc_status.value1 = SET_SRC (body);
-      break;
-
-    case CC_INVERT:
-      /* The insn is a compare instruction.  */
-      CC_STATUS_INIT;
-      cc_status.value1 = SET_SRC (body);
-      cc_status.flags |= CC_INVERTED;
-      break;
-
-    case CC_CLOBBER:
-      /* Insn doesn't leave CC in a usable state.  */
-      CC_STATUS_INIT;
-      break;
-
-    default:
-      abort ();
-    }
-}
-
-/* Return true if OP is a valid call operand.  */
-
-int
-call_address_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
-}
-
-/* What (if any) secondary registers are needed to move IN with mode
-   MODE into a register from in register class CLASS. 
-
-   We might be able to simplify this.  */
-enum reg_class
-secondary_reload_class (class, mode, in)
-     enum reg_class class;
-     enum machine_mode mode;
-     rtx in;
-{
-  int regno;
-
-  /* Memory loads less than a full word wide can't have an
-     address or stack pointer destination.  They must use
-     a data register as an intermediate register.  */
-  if (GET_CODE (in) == MEM
-      && (mode == QImode || mode == HImode)
-      && (class == ADDRESS_REGS || class == SP_REGS))
-    {
-      if (TARGET_AM33)
-	return DATA_OR_EXTENDED_REGS;
-      return DATA_REGS;
-    }
-
-  /* We can't directly load sp + const_int into a data register;
-     we must use an address register as an intermediate.  */
-  if (class != SP_REGS
-      && class != ADDRESS_REGS
-      && class != SP_OR_ADDRESS_REGS
-      && class != SP_OR_EXTENDED_REGS
-      && class != ADDRESS_OR_EXTENDED_REGS
-      && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
-      && (in == stack_pointer_rtx
-	  || (GET_CODE (in) == PLUS
-	      && (XEXP (in, 0) == stack_pointer_rtx
-		  || XEXP (in, 1) == stack_pointer_rtx))))
-    return ADDRESS_REGS;
-
-  if (GET_CODE (in) == PLUS
-      && (XEXP (in, 0) == stack_pointer_rtx
-	  || XEXP (in, 1) == stack_pointer_rtx))
-    {
-      if (TARGET_AM33)
-	return DATA_OR_EXTENDED_REGS;
-      return DATA_REGS;
-    }
- 
-  /* Otherwise assume no secondary reloads are needed.  */
-  return NO_REGS;
-}
-
-int
-initial_offset (from, to)
-     int from, to;
-{
-  /* The difference between the argument pointer and the frame pointer
-     is the size of the callee register save area.  */
-  if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
-    {
-      if (regs_ever_live[2] || regs_ever_live[3]
-	  || regs_ever_live[6] || regs_ever_live[7]
-	  || regs_ever_live[14] || regs_ever_live[15]
-	  || regs_ever_live[16] || regs_ever_live[17]
-	  || frame_pointer_needed)
-	return REG_SAVE_BYTES;
-      else
-	return 0;
-    }
-
-  /* The difference between the argument pointer and the stack pointer is
-     the sum of the size of this function's frame, the callee register save
-     area, and the fixed stack space needed for function calls (if any).  */
-  if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
-    {
-      if (regs_ever_live[2] || regs_ever_live[3]
-	  || regs_ever_live[6] || regs_ever_live[7]
-	  || regs_ever_live[14] || regs_ever_live[15]
-	  || regs_ever_live[16] || regs_ever_live[17]
-	  || frame_pointer_needed)
-	return (get_frame_size () + REG_SAVE_BYTES
-		+ (current_function_outgoing_args_size
-		   ? current_function_outgoing_args_size + 4 : 0)); 
-      else
-	return (get_frame_size ()
-		+ (current_function_outgoing_args_size
-		   ? current_function_outgoing_args_size + 4 : 0)); 
-    }
-
-  /* The difference between the frame pointer and stack pointer is the sum
-     of the size of this function's frame and the fixed stack space needed
-     for function calls (if any).  */
-  if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
-    return (get_frame_size ()
-	    + (current_function_outgoing_args_size
-	       ? current_function_outgoing_args_size + 4 : 0)); 
-
-  abort ();
-}
-
-/* Flush the argument registers to the stack for a stdarg function;
-   return the new argument pointer.  */
-rtx
-mn10300_builtin_saveregs (arglist)
-     tree arglist;
-{
-  rtx offset;
-  tree fntype = TREE_TYPE (current_function_decl);
-  int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
-                   && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
-                       != void_type_node)))
-                ? UNITS_PER_WORD : 0);
-
-  if (argadj)
-    offset = plus_constant (current_function_arg_offset_rtx, argadj);
-  else
-    offset = current_function_arg_offset_rtx;
-
-  emit_move_insn (gen_rtx (MEM, SImode, current_function_internal_arg_pointer),
-		  gen_rtx (REG, SImode, 0));
-  emit_move_insn (gen_rtx (MEM, SImode,
-			   plus_constant
-			     (current_function_internal_arg_pointer, 4)),
-		  gen_rtx (REG, SImode, 1));
-  return copy_to_reg (expand_binop (Pmode, add_optab,
-				    current_function_internal_arg_pointer,
-				    offset, 0, 0, OPTAB_LIB_WIDEN));
-}
-
-/* Return an RTX to represent where a value with mode MODE will be returned
-   from a function.  If the result is 0, the argument is pushed.  */
-
-rtx
-function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  rtx result = 0;
-  int size, align;
-
-  /* We only support using 2 data registers as argument registers.  */
-  int nregs = 2;
-
-  /* Figure out the size of the object to be passed.  */
-  if (mode == BLKmode)
-    size = int_size_in_bytes (type);
-  else
-    size = GET_MODE_SIZE (mode);
-
-  /* Figure out the alignment of the object to be passed.  */
-  align = size;
-
-  cum->nbytes = (cum->nbytes + 3) & ~3;
-
-  /* Don't pass this arg via a register if all the argument registers
-     are used up.  */
-  if (cum->nbytes > nregs * UNITS_PER_WORD)
-    return 0;
-
-  /* Don't pass this arg via a register if it would be split between
-     registers and memory.  */
-  if (type == NULL_TREE
-      && cum->nbytes + size > nregs * UNITS_PER_WORD)
-    return 0;
-
-  switch (cum->nbytes / UNITS_PER_WORD)
-    {
-    case 0:
-      result = gen_rtx (REG, mode, 0);
-      break;
-    case 1:
-      result = gen_rtx (REG, mode, 1);
-      break;
-    default:
-      result = 0;
-    }
-
-  return result;
-}
-
-/* Return the number of registers to use for an argument passed partially
-   in registers and partially in memory.  */
-
-int
-function_arg_partial_nregs (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int size, align;
-
-  /* We only support using 2 data registers as argument registers.  */
-  int nregs = 2;
-
-  /* Figure out the size of the object to be passed.  */
-  if (mode == BLKmode)
-    size = int_size_in_bytes (type);
-  else
-    size = GET_MODE_SIZE (mode);
-
-  /* Figure out the alignment of the object to be passed.  */
-  align = size;
-
-  cum->nbytes = (cum->nbytes + 3) & ~3;
-
-  /* Don't pass this arg via a register if all the argument registers
-     are used up.  */
-  if (cum->nbytes > nregs * UNITS_PER_WORD)
-    return 0;
-
-  if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
-    return 0;
-
-  /* Don't pass this arg via a register if it would be split between
-     registers and memory.  */
-  if (type == NULL_TREE
-      && cum->nbytes + size > nregs * UNITS_PER_WORD)
-    return 0;
-
-  return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
-}
-
-/* Output a tst insn.  */
-char *
-output_tst (operand, insn)
-     rtx operand, insn;
-{
-  rtx temp;
-  int past_call = 0;
-
-  /* We can save a byte if we can find a register which has the value
-     zero in it.  */
-  temp = PREV_INSN (insn);
-  while (optimize && temp)
-    {
-      rtx set;
-
-      /* We allow the search to go through call insns.  We record
-	 the fact that we've past a CALL_INSN and reject matches which
-	 use call clobbered registers.  */
-      if (GET_CODE (temp) == CODE_LABEL
-	  || GET_CODE (temp) == JUMP_INSN
-	  || GET_CODE (temp) == BARRIER)
-	break;
-
-      if (GET_CODE (temp) == CALL_INSN)
-	past_call = 1;
-
-      if (GET_CODE (temp) == NOTE)
-	{
-	  temp = PREV_INSN (temp);
-	  continue;
-	}
-
-      /* It must be an insn, see if it is a simple set. */
-      set = single_set (temp);
-      if (!set)
-	{
-	  temp = PREV_INSN (temp);
-	  continue;
-	}
-
-      /* Are we setting a data register to zero (this does not win for
-	 address registers)? 
-
-	 If it's a call clobbered register, have we past a call?
-
-	 Make sure the register we find isn't the same as ourself;
-	 the mn10300 can't encode that.
-
-	 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
-	 so the code to detect calls here isn't doing anything useful.  */
-      if (REG_P (SET_DEST (set))
-	  && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
-	  && !reg_set_between_p (SET_DEST (set), temp, insn)
-	  && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
-	      == REGNO_REG_CLASS (REGNO (operand)))
-	  && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
-	  && REGNO (SET_DEST (set)) != REGNO (operand)
-	  && (!past_call 
-	      || !call_used_regs[REGNO (SET_DEST (set))]))
-	{
-	  rtx xoperands[2];
-	  xoperands[0] = operand;
-	  xoperands[1] = SET_DEST (set);
-
-	  output_asm_insn ("cmp %1,%0", xoperands);
-	  return "";
-	}
-
-      if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
-	  && REG_P (SET_DEST (set))
-	  && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
-	  && !reg_set_between_p (SET_DEST (set), temp, insn)
-	  && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
-	      != REGNO_REG_CLASS (REGNO (operand)))
-	  && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
-	  && REGNO (SET_DEST (set)) != REGNO (operand)
-	  && (!past_call 
-	      || !call_used_regs[REGNO (SET_DEST (set))]))
-	{
-	  rtx xoperands[2];
-	  xoperands[0] = operand;
-	  xoperands[1] = SET_DEST (set);
-
-	  output_asm_insn ("cmp %1,%0", xoperands);
-	  return "";
-	}
-
-      temp = PREV_INSN (temp);
-    }
-  return "cmp 0,%0";
-}
-
-int
-impossible_plus_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  extern rtx *reg_equiv_mem;
-  rtx reg1, reg2;
-  
-  if (GET_CODE (op) != PLUS)
-    return 0;
-
-  if (XEXP (op, 0) == stack_pointer_rtx
-      || XEXP (op, 1) == stack_pointer_rtx)
-    return 1;
-
-  return 0;
-}
-
-/* Return 1 if X is a CONST_INT that is only 8 bits wide.  This is used
-   for the btst insn which may examine memory or a register (the memory
-   variant only allows an unsigned 8 bit integer).  */
-int
-const_8bit_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  return (GET_CODE (op) == CONST_INT
-	  && INTVAL (op) >= 0
-	  && INTVAL (op) < 256);
-}
-
-/* Similarly, but when using a zero_extract pattern for a btst where
-   the source operand might end up in memory.  */
-int
-mask_ok_for_mem_btst (len, bit)
-     int len;
-     int bit;
-{
-  int mask = 0;
-
-  while (len > 0)
-    {
-      mask |= (1 << bit);
-      bit++;
-      len--;
-    }
-
-  /* MASK must bit into an 8bit value.  */
-  return (((mask & 0xff) == mask)
-	  || ((mask & 0xff00) == mask)
-	  || ((mask & 0xff0000) == mask)
-	  || ((mask & 0xff000000) == mask));
-}
-
-/* Return 1 if X contains a symbolic expression.  We know these
-   expressions will have one of a few well defined forms, so
-   we need only check those forms.  */
-int
-symbolic_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return 1;
-    case CONST:
-      op = XEXP (op, 0);
-      return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
-               || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-              && GET_CODE (XEXP (op, 1)) == CONST_INT);
-    default:
-      return 0;
-    }
-}
-
-/* Try machine dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   Normally it is always safe for this macro to do nothing.  It exists to
-   recognize opportunities to optimize the output.
-
-   But on a few ports with segmented architectures and indexed addressing
-   (mn10300, hppa) it is used to rewrite certain problematical addresses.  */
-rtx
-legitimize_address (x, oldx, mode)
-     rtx x;
-     rtx oldx;
-     enum machine_mode mode;
-{
-  /* Uh-oh.  We might have an address for x[n-100000].  This needs
-     special handling to avoid creating an indexed memory address
-     with x-100000 as the base.  */
-  if (GET_CODE (x) == PLUS
-      && symbolic_operand (XEXP (x, 1), VOIDmode))
-    {
-      /* Ugly.  We modify things here so that the address offset specified
-         by the index expression is computed first, then added to x to form
-         the entire address.  */
-
-      rtx regx1, regx2, regy1, regy2, y;
-
-      /* Strip off any CONST.  */
-      y = XEXP (x, 1);
-      if (GET_CODE (y) == CONST)
-        y = XEXP (y, 0);
-
-      if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
-	{
-	  regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
-	  regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
-	  regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
-	  regx1 = force_reg (Pmode,
-			     gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
-	  return force_reg (Pmode, gen_rtx (PLUS, Pmode, regx1, regy1));
-	}
-    }
-  return x;
-}
diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h
deleted file mode 100755
index 0e2a7ea..0000000
--- a/gcc/config/mn10300/mn10300.h
+++ /dev/null
@@ -1,1170 +0,0 @@
-/* Definitions of target machine for GNU compiler. Matsushita MN10300 series
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Jeff Law (law@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "svr4.h"
-
-#undef ASM_SPEC
-#undef ASM_FINAL_SPEC
-#undef LIB_SPEC
-#undef ENDFILE_SPEC
-#undef LINK_SPEC
-#undef STARTFILE_SPEC
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-D__mn10300__ -D__MN10300__"
-
-#define CPP_SPEC "%{mam33:-D__AM33__}"
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-/* Generate code to work around mul/mulq bugs on the mn10300.  */
-#define TARGET_MULT_BUG			(target_flags & 0x1)
-
-/* Generate code for the AM33 processor.  */
-#define TARGET_AM33			(target_flags & 0x2)
-
-#define TARGET_SWITCHES  \
-  {{ "mult-bug",	0x1},	\
-   { "no-mult-bug", 	-0x1},	\
-   { "am33", 		0x2},	\
-   { "am33", 		-(0x1)},\
-   { "no-am33", 	-0x2},	\
-   { "", TARGET_DEFAULT}}
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 0x1
-#endif
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fprintf (stderr, " (MN10300)");
-
-
-/* Target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is not true on the Matsushita MN1003.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* This is not true on the Matsushita MN10300.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered.
-   This is not true on the Matsushita MN10300.  */
-#define WORDS_BIG_ENDIAN 0
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD		32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD		4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 		32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY		32
-
-/* The stack goes in 32 bit lumps.  */
-#define STACK_BOUNDARY 		32
-
-/* Allocation boundary (in *bits*) for the code of a function.
-   8 is the minimum boundary; it's unclear if bigger alignments
-   would improve performance.  */
-#define FUNCTION_BOUNDARY 8
-
-/* No data type wants to be aligned rounder than this.   */
-#define BIGGEST_ALIGNMENT	32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Define this if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  */
-
-#define FIRST_PSEUDO_REGISTER 10
-#undef FIRST_PSEUDO_REGISTER
-#define FIRST_PSEUDO_REGISTER 18
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.  */
-
-#define FIXED_REGISTERS \
-  { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1}
-#undef FIXED_REGISTERS
-#define FIXED_REGISTERS \
-  { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you
-   like.  */
-
-#define CALL_USED_REGISTERS \
-  { 1, 1, 0, 0, 1, 1, 0, 0, 1, 1}
-
-#define REG_ALLOC_ORDER \
-  { 0, 1, 4, 5, 2, 3, 6, 7, 8, 9}
-
-#undef CALL_USED_REGISTERS
-#define CALL_USED_REGISTERS \
-  { 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0}
-
-#undef REG_ALLOC_ORDER
-#define REG_ALLOC_ORDER \
-  { 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9}
-
-#define CONDITIONAL_REGISTER_USAGE \
-{						\
-  if (!TARGET_AM33)				\
-    {						\
-      for (i = 10; i < 18; i++) 		\
-	fixed_regs[i] = call_used_regs[i] = 1; 	\
-    }						\
-}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
-   MODE.  */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (REGNO_REG_CLASS (REGNO) == DATA_REGS 			\
-  ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4	\
-  : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
-
-#undef HARD_REGNO_MODE_OK
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((REGNO_REG_CLASS (REGNO) == DATA_REGS \
-   || (TARGET_AM33 && REGNO_REG_CLASS (REGNO) == ADDRESS_REGS) \
-   || REGNO_REG_CLASS (REGNO) == EXTENDED_REGS) \
-  ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4	\
-  : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  (MODE1 == MODE2 || (GET_MODE_SIZE (MODE1) <= 4 && GET_MODE_SIZE (MODE2) <= 4))
-
-#undef MODES_TIEABLE_P
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  (TARGET_AM33  \
-   || MODE1 == MODE2 \
-   || (GET_MODE_SIZE (MODE1) <= 4 && GET_MODE_SIZE (MODE2) <= 4))
-
-/* 4 data, and effectively 3 address registers is small as far as I'm
-   concerned.  */
-#define SMALL_REGISTER_CLASSES 1
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-enum reg_class {
-  NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,
-  DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, 
-  EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS,
-  SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS, 
-  GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
-{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \
-  "SP_REGS", "DATA_OR_ADDRESS_REGS", "SP_OR_ADDRESS_REGS", \
-  "EXTENDED_REGS", \
-  "DATA_OR_EXTENDED_REGS", "ADDRESS_OR_EXTENDED_REGS", \
-  "SP_OR_EXTENDED_REGS", "SP_OR_ADDRESS_OR_EXTENDED_REGS", \
-  "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS  			\
-{      0,		/* No regs      */	\
-   0x00f,		/* DATA_REGS */		\
-   0x1f0,		/* ADDRESS_REGS */	\
-   0x200,		/* SP_REGS */		\
-   0x1ff,		/* DATA_OR_ADDRESS_REGS */\
-   0x1f0,		/* SP_OR_ADDRESS_REGS */\
-   0x1ff,		/* GENERAL_REGS */    	\
-   0x3ff,		/* ALL_REGS 	*/	\
-}
-
-/* This may not be strictly necessary, but I don't offhand know if having bits
-   higher than FIRST_PSEUDO_REGISTER set in this macro is safe.  */
-#undef REG_CLASS_CONTENTS
-#define REG_CLASS_CONTENTS  			\
-{      0,		/* No regs      */	\
-   0x0000f,		/* DATA_REGS */		\
-   0x001f0,		/* ADDRESS_REGS */	\
-   0x00200,		/* SP_REGS */		\
-   0x001ff,		/* DATA_OR_ADDRESS_REGS */\
-   0x003f0,		/* SP_OR_ADDRESS_REGS */\
-   0x2fc00,		/* EXTENDED_REGS */	\
-   0x2fc0f,		/* DATA_OR_EXTENDED_REGS */	\
-   0x2fdf0,		/* ADDRESS_OR_EXTENDED_REGS */	\
-   0x2fe00,		/* SP_OR_EXTENDED_REGS */	\
-   0x2fff0,		/* SP_OR_ADDRESS_OR_EXTENDED_REGS */	\
-   0x2fdff,		/* GENERAL_REGS */    	\
-   0x2ffff,		/* ALL_REGS 	*/	\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) \
-  ((REGNO) < 4 ? DATA_REGS : \
-   (REGNO) < 9 ? ADDRESS_REGS : \
-    (REGNO) == 9 ? SP_REGS : 0)
-
-#undef REGNO_REG_CLASS
-#define REGNO_REG_CLASS(REGNO) \
-  ((REGNO) < 4 ? DATA_REGS : \
-   (REGNO) < 9 ? ADDRESS_REGS : \
-    (REGNO) == 9 ? SP_REGS : \
-     (REGNO) < 18 ? EXTENDED_REGS : 0)
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS DATA_REGS
-#define BASE_REG_CLASS  SP_OR_ADDRESS_REGS
-
-#undef INDEX_REG_CLASS
-#define INDEX_REG_CLASS DATA_OR_EXTENDED_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'd' ? DATA_REGS : \
-   (C) == 'a' ? ADDRESS_REGS : \
-   (C) == 'x' ? EXTENDED_REGS : \
-   (C) == 'y' ? SP_REGS : NO_REGS)
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
- 
-#define REGNO_OK_FOR_BASE_P(regno) \
-  (((regno) > 3 && regno < FIRST_PSEUDO_REGISTER)	\
-   || (reg_renumber[regno] > 3 && reg_renumber[regno] < FIRST_PSEUDO_REGISTER))
-
-#define REGNO_OK_FOR_BIT_BASE_P(regno) \
-  (((regno) > 3 && regno < 10)	\
-   || (reg_renumber[regno] > 3 && reg_renumber[regno] < 10))
-
-#define REGNO_OK_FOR_INDEX_P(regno) \
-  (((regno) >= 0 && regno < 4)	\
-   || ((regno) >= 10 && regno < 18)	\
-   || (reg_renumber[regno] >= 10 && reg_renumber[regno] < 18) \
-   || (reg_renumber[regno] >= 0 && reg_renumber[regno] < 4))
-
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
-  (X == stack_pointer_rtx && CLASS != SP_REGS ? ADDRESS_REGS : CLASS)
-
-#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) \
-  (X == stack_pointer_rtx && CLASS != SP_REGS ? ADDRESS_REGS : CLASS)
-
-#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
-  ((MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
-
-#undef PREFERRED_RELOAD_CLASS
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
-  (X == stack_pointer_rtx && CLASS != SP_REGS \
-   ? ADDRESS_OR_EXTENDED_REGS : CLASS)
-
-#undef PREFERRED_OUTPUT_RELOAD_CLASS
-#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) \
-  (X == stack_pointer_rtx && CLASS != SP_REGS \
-   ? ADDRESS_OR_EXTENDED_REGS : CLASS)
-
-#undef LIMIT_RELOAD_CLASS
-#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
-  (!TARGET_AM33 && (MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
-
-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
-  secondary_reload_class(CLASS,MODE,IN)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* The letters I, J, K, L, M, N, O, P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.  */
-
-#define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100)
-#define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000)
-
-#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
-#define CONST_OK_FOR_J(VALUE) ((VALUE) == 1)
-#define CONST_OK_FOR_K(VALUE) ((VALUE) == 2)
-#define CONST_OK_FOR_L(VALUE) ((VALUE) == 4)
-#define CONST_OK_FOR_M(VALUE) ((VALUE) == 3)
-#define CONST_OK_FOR_N(VALUE) ((VALUE) == 255 || (VALUE) == 65535)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
-   (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
-   (C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
-   (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
-   (C) == 'M' ? CONST_OK_FOR_M (VALUE) : \
-   (C) == 'N' ? CONST_OK_FOR_N (VALUE) : 0)
-
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself. 
-     
-  `G' is a floating-point zero.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT	\
-		 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) : 0)
-
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-
-#define STARTING_FRAME_OFFSET 0
-
-/* Offset of first parameter from the argument pointer register value.  */
-/* Is equal to the size of the saved fp + pc, even if an fp isn't
-   saved since the value is used before we know.  */
-
-#define FIRST_PARM_OFFSET(FNDECL) 4
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 9
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 7
-
-/* Base register for access to arguments of the function.  This
-   is a fake register and will be eliminated into either the frame
-   pointer or stack pointer.  */
-#define ARG_POINTER_REGNUM 8
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 5
-
-#define ELIMINABLE_REGS				\
-{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},	\
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
-
-#define CAN_ELIMINATE(FROM, TO) 1
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
-  OFFSET = initial_offset (FROM, TO)
-
-/* We can debug without frame pointers on the mn10300, so eliminate
-   them whenever possible.  */
-#define FRAME_POINTER_REQUIRED 0
-#define CAN_DEBUG_WITHOUT_FP
-
-/* A guess for the MN10300.  */
-#define PROMOTE_PROTOTYPES 1
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* We use d0/d1 for passing parameters, so allocate 8 bytes of space
-   for a register flushback area.  */
-#define REG_PARM_STACK_SPACE(DECL) 8
-#define OUTGOING_REG_PARM_STACK_SPACE
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* So we can allocate space for return pointers once for the function
-   instead of around every call.  */
-#define STACK_POINTER_OFFSET 4
-
-/* 1 if N is a possible register number for function argument passing.
-   On the MN10300, no registers are used in this way.  */
-
-#define FUNCTION_ARG_REGNO_P(N) ((N) <= 1)
-
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the MN10300, this is a single integer, which is a number of bytes
-   of arguments scanned so far.  */
-
-#define CUMULATIVE_ARGS struct cum_arg
-struct cum_arg {int nbytes; };
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the MN10300, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM).nbytes = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM).nbytes += ((MODE) != BLKmode			\
-	           ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
-	           : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On the MN10300 all args are pushed.  */   
-
-extern struct rtx_def *function_arg ();
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  function_arg (&CUM, MODE, TYPE, NAMED)
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-  function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
-
-
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)		\
-  ((TYPE) && int_size_in_bytes (TYPE) > 8)
- 
-#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
-  ((TYPE) && int_size_in_bytes (TYPE) > 8)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.   */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), POINTER_TYPE_P (VALTYPE) ? 4 : 0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
-
-/* 1 if N is a possible register number for a function value.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 4)
-
-/* Return values > 8 bytes in length in memory.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-#define RETURN_IN_MEMORY(TYPE)  \
-  (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode)
-
-/* Register in which address to store a structure value
-   is passed to a function.  On the MN10300 it's passed as
-   the first parameter.  */
-
-#define STRUCT_VALUE 0
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) ;
-
-#define TRAMPOLINE_TEMPLATE(FILE)			\
-  do {							\
-    fprintf (FILE, "\tadd -4,sp\n");			\
-    fprintf (FILE, "\t.long 0x0004fffa\n");		\
-    fprintf (FILE, "\tmov (0,sp),a0\n");		\
-    fprintf (FILE, "\tadd 4,sp\n");			\
-    fprintf (FILE, "\tmov (13,a0),a1\n");		\
-    fprintf (FILE, "\tmov (17,a0),a0\n");		\
-    fprintf (FILE, "\tjmp (a0)\n");			\
-    fprintf (FILE, "\t.long 0\n");			\
-    fprintf (FILE, "\t.long 0\n");			\
-  } while (0)
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 0x1b
-
-#define TRAMPOLINE_ALIGNMENT 32
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 0x14)),	\
- 		 (CXT));						\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 0x18)),	\
-		 (FNADDR));						\
-}
-/* A C expression whose value is RTL representing the value of the return
-   address for the frame COUNT steps up from the current frame.
-
-   On the mn10300, the return address is not at a constant location
-   due to the frame layout.  Luckily, it is at a constant offset from
-   the argument pointer, so we define RETURN_ADDR_RTX to return a
-   MEM using arg_pointer_rtx.  Reload will replace arg_pointer_rtx
-   with a reference to the stack/frame pointer + an appropriate offset.  */
-
-#define RETURN_ADDR_RTX(COUNT, FRAME)   \
-  ((COUNT == 0)                         \
-   ? gen_rtx (MEM, Pmode, arg_pointer_rtx) \
-   : (rtx) 0)
-
-/* Emit code for a call to builtin_saveregs.  We must emit USE insns which
-   reference the 2 integer arg registers.
-   Ordinarily they are not call used registers, but they are for
-   _builtin_saveregs, so we must make this explicit.  */
-
-extern struct rtx_def *mn10300_builtin_saveregs ();
-#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) mn10300_builtin_saveregs (ARGLIST)
-
-/* Addressing modes, and classification of registers for them.  */
-
-
-/* 1 if X is an rtx for a constant that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   CONSTANT_P (X)
-
-/* Extra constraints.  */
- 
-#define OK_FOR_R(OP) \
-   (GET_CODE (OP) == MEM					\
-    && GET_MODE (OP) == QImode					\
-    && (CONSTANT_ADDRESS_P (XEXP (OP, 0))			\
-	|| (GET_CODE (XEXP (OP, 0)) == REG			\
-	    && REG_OK_FOR_BIT_BASE_P (XEXP (OP, 0))		\
-	    && XEXP (OP, 0) != stack_pointer_rtx)		\
-	|| (GET_CODE (XEXP (OP, 0)) == PLUS			\
-	    && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG		\
-	    && REG_OK_FOR_BIT_BASE_P (XEXP (XEXP (OP, 0), 0))	\
-	    && XEXP (XEXP (OP, 0), 0) != stack_pointer_rtx	\
-	    && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT	\
-	    && INT_8_BITS (INTVAL (XEXP (XEXP (OP, 0), 1))))))
-	 
-#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'R' ? OK_FOR_R (OP) : (C) == 'S' ? GET_CODE (OP) == SYMBOL_REF : 0)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X)  \
-  ((REGNO (X) >= 0 && REGNO(X) <= 3) || REGNO (X) >= 10)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-  ((REGNO (X) >= 4 && REGNO(X) <= 9) || REGNO (X) >= 10)
-#define REG_OK_FOR_BIT_BASE_P(X) \
-  ((REGNO (X) >= 4 && REGNO(X) <= 9))
-#else
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BIT_BASE_P(X) REGNO_OK_FOR_BIT_BASE_P (REGNO (X))
-#endif
-
-
-#define HAVE_POST_INCREMENT (TARGET_AM33)
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
-   except for CONSTANT_ADDRESS_P which is actually
-   machine-independent.
-
-   On the mn10300, the value in the address register must be
-   in the same memory space/segment as the effective address.
-
-   This is problematical for reload since it does not understand
-   that base+index != index+base in a memory reference.
-
-   Note it is still possible to use reg+reg addressing modes,
-   it's just much more difficult.  For a discussion of a possible
-   workaround and solution, see the comments in pa.c before the
-   function record_unscaled_index_insn_codes.  */
-
-/* Accept either REG or SUBREG where a register is valid.  */
-  
-#define RTX_OK_FOR_BASE_P(X)					\
-  ((REG_P (X) && REG_OK_FOR_BASE_P (X))				\
-   || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))		\
-       && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)    	\
-{							\
-  if (CONSTANT_ADDRESS_P (X))				\
-    goto ADDR;						\
-  if (RTX_OK_FOR_BASE_P (X))				\
-    goto ADDR;						\
-  if (TARGET_AM33					\
-      && GET_CODE (X) == POST_INC			\
-      && RTX_OK_FOR_BASE_P (XEXP (X, 0))		\
-      && (MODE == SImode || MODE == SFmode || MODE == HImode))\
-    goto ADDR;						\
-  if (GET_CODE (X) == PLUS)				\
-    {							\
-      rtx base = 0, index = 0;				\
-      if (REG_P (XEXP (X, 0))				\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 0)))		\
-	base = XEXP (X, 0), index = XEXP (X, 1);	\
-      if (REG_P (XEXP (X, 1))				\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 1)))		\
-	base = XEXP (X, 1), index = XEXP (X, 0);	\
-      if (base != 0 && index != 0)			\
-	{						\
-	  if (GET_CODE (index) == CONST_INT)		\
-	    goto ADDR;					\
-	}						\
-    }							\
-}
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.   */
-
-extern struct rtx_def *legitimize_address ();
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)  \
-{ rtx orig_x = (X);				\
-  (X) = legitimize_address (X, OLDX, MODE);	\
-  if ((X) != orig_x && memory_address_p (MODE, X)) \
-    goto WIN; }
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.  */
-
-#undef GO_IF_MODE_DEPENDENT_ADDRESS
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)        \
-  if (GET_CODE (ADDR) == POST_INC) \
-    goto LABEL
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  No extra ones are needed for the vax.  */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define CC_OVERFLOW_UNUSABLE 0x200
-#define CC_NO_CARRY CC_NO_OVERFLOW
-#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:							\
-    /* Zeros are extremely cheap.  */					\
-    if (INTVAL (RTX) == 0 && OUTER_CODE == SET)				\
-      return 0;								\
-    /* If it fits in 8 bits, then it's still relatively cheap.  */	\
-    if (INT_8_BITS (INTVAL (RTX)))					\
-      return 1;								\
-    /* This is the "base" cost, includes constants where either the	\
-       upper or lower 16bits are all zeros.  */				\
-    if (INT_16_BITS (INTVAL (RTX))					\
-	|| (INTVAL (RTX) & 0xffff) == 0					\
-	|| (INTVAL (RTX) & 0xffff0000) == 0)				\
-      return 2;								\
-    return 4;								\
-  /* These are more costly than a CONST_INT, but we can relax them,	\
-     so they're less costly than a CONST_DOUBLE.  */			\
-  case CONST:								\
-  case LABEL_REF:							\
-  case SYMBOL_REF:							\
-    return 6;								\
-  /* We don't optimize CONST_DOUBLEs well nor do we relax them well,	\
-     so their cost is very high.  */					\
-  case CONST_DOUBLE:							\
-    return 8;
-
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)  (CLASS1 != CLASS2 ? 4 : 2)
-
-#undef REGISTER_MOVE_COST
-#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
-  ((CLASS1 == CLASS2 && (CLASS1 == ADDRESS_REGS || CLASS1 == DATA_REGS)) ? 2 :\
-   CLASS1 == CLASS2 && CLASS1 == EXTENDED_REGS ? 6 : 4)
-
-/* A crude cut at RTX_COSTS for the MN10300.  */
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  */
-#define RTX_COSTS(RTX,CODE,OUTER_CODE) \
-  case UMOD:		\
-  case UDIV:		\
-  case MOD:		\
-  case DIV:		\
-    return 8;		\
-  case MULT:		\
-    return 8;
-
-/* Nonzero if access to memory by bytes or half words is no faster
-   than accessing full words.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* Dispatch tables on the mn10300 are extremely expensive in terms of code
-   and readonly data size.  So we crank up the case threshold value to
-   encourage a series of if/else comparisons to implement many small switch
-   statements.  In theory, this value could be increased much more if we
-   were solely optimizing for space, but we keep it "reasonable" to avoid
-   serious code efficiency lossage.  */
-#define CASE_VALUES_THRESHOLD 6
-
-#define NO_FUNCTION_CSE
-
-/* According expr.c, a value of around 6 should minimize code size, and
-   for the MN10300 series, that's our primary concern.  */
-#define MOVE_RATIO 6
-
-#define TEXT_SECTION_ASM_OP "\t.section .text"
-#define DATA_SECTION_ASM_OP "\t.section .data"
-#define BSS_SECTION_ASM_OP "\t.section .bss"
-
-/* Output at beginning/end of assembler file.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) asm_file_start(FILE)
-
-#define ASM_COMMENT_START "#"
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* This is how to output an assembler line defining a `double' constant.
-   It is .dfloat or .gfloat, depending.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.double %s\n", dstr);		\
-   } while (0)
-
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.float %s\n", dstr);		\
-   } while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE, VALUE)		\
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE, VALUE)		\
-( fprintf (FILE, "\t.hword "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE, VALUE)		\
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-#define ASM_OUTPUT_BYTE(FILE, VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* This says how to output the assembler to define a global
-   uninitialized but not common symbol.
-   Try to use asm_output_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE, NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE, NAME)	\
-  do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE, NAME)	          \
-  do {                                            \
-  char* real_name;                                \
-  STRIP_NAME_ENCODING (real_name, (NAME));        \
-  fprintf (FILE, "_%s", real_name);               \
-  } while (0)           
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
-
-/* This is how we tell the assembler that two symbols have the same value.  */
-
-#define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
-  do { assemble_name(FILE, NAME1); 	 \
-       fputs(" = ", FILE);		 \
-       assemble_name(FILE, NAME2);	 \
-       fputc('\n', FILE); } while (0)
-
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp" }
-
-#undef REGISTER_NAMES
-#define REGISTER_NAMES \
-{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp", \
-  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" }
-
-/* Print an instruction operand X on file FILE.
-   look in mn10300.c for details */
-
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand(FILE,X,CODE)
-
-/* Print a memory operand whose address is X, on file FILE.
-   This uses a function in output-vax.c.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-  asm_fprintf (FILE, "\t%s .L%d\n", ".long", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL)
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", (LOG))
-
-/* We don't have to worry about dbx compatibility for the mn10300.  */
-#define DEFAULT_GDB_EXTENSIONS 1
-
-/* Use stabs debugging info by default.  */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#define DBX_REGISTER_NUMBER(REGNO) REGNO
-
-/* GDB always assumes the current function's frame begins at the value
-   of the stack pointer upon entry to the current function.  Accessing
-   local variables and parameters passed on the stack is done using the
-   base of the frame + an offset provided by GCC.
-
-   For functions which have frame pointers this method works fine;
-   the (frame pointer) == (stack pointer at function entry) and GCC provides
-   an offset relative to the frame pointer.
-
-   This loses for functions without a frame pointer; GCC provides an offset
-   which is relative to the stack pointer after adjusting for the function's
-   frame size.  GDB would prefer the offset to be relative to the value of
-   the stack pointer at the function's entry.  Yuk!  */
-#define DEBUGGER_AUTO_OFFSET(X) \
-  ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
-    + (frame_pointer_needed \
-       ? 0 : -initial_offset (FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM)))
-
-#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
-  ((GET_CODE (X) == PLUS ? OFFSET : 0) \
-    + (frame_pointer_needed \
-       ? 0 : -initial_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM)))
-
-/* We need to prepend underscores.  */
-#define ASM_OUTPUT_DWARF2_ADDR_CONST(FILE,ADDR) \
-  fprintf ((FILE), "\t%s\t_%s", UNALIGNED_WORD_ASM_OP, (ADDR))
-
-/* Define to use software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion. */
-#define REAL_ARITHMETIC
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE Pmode
-
-/* Define this if the case instruction drops through after the table
-   when the index is out of range.  Don't define it if the case insn
-   jumps to the default label instead.  */
-#define CASE_DROPS_THROUGH
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.  */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX	4
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* The assembler op to get a word.  */
-
-#define FILE_ASM_OP "\t.file\n"
-
-extern void asm_file_start ();
-extern int const_costs ();
-extern void print_operand ();
-extern void print_operand_address ();
-extern void expand_prologue ();
-extern void expand_epilogue ();
-extern void notice_update_cc ();
-extern int call_address_operand ();
-extern int impossible_plus_operand ();
-extern enum reg_class secondary_reload_class ();
-extern int initial_offset ();
-extern char *output_tst ();
-int symbolic_operand ();
diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md
deleted file mode 100755
index 61baf62..0000000
--- a/gcc/config/mn10300/mn10300.md
+++ /dev/null
@@ -1,2169 +0,0 @@
-;; GCC machine description for Matsushita MN10300
-;; Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-
-;;   Contributed by Jeff Law (law@cygnus.com).
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;; The original PO technology requires these to be ordered by speed,
-;; so that assigner will pick the fastest.
-
-;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; Condition code settings.
-;; none - insn does not affect cc
-;; none_0hit - insn does not affect cc but it does modify operand 0
-;;	This attribute is used to keep track of when operand 0 changes.
-;; 	See the description of NOTICE_UPDATE_CC for more info.
-;; set_znv - insn sets z,n,v to usable values; c is unusable.
-;; set_zn  - insn sets z,n to usable values; v,c are unusable.
-;; compare - compare instruction
-;; invert -- like compare, but flags are inverted.
-;; clobber - value of cc is unknown
-(define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber,invert"
-  (const_string "clobber"))
-
-;; ----------------------------------------------------------------------
-;; MOVE INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; movqi
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand (operand0, QImode)
-      && !register_operand (operand1, QImode))
-    operands[1] = copy_to_mode_reg (QImode, operand1);
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=dx,a,dx,a,dx,a,dx,a,dxa,m")
-	(match_operand:QI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dxa"))]
-  "TARGET_AM33
-   && (register_operand (operands[0], QImode)
-       || register_operand (operands[1], QImode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-      return \"nop\";
-    case 2:
-      return \"clr %0\";
-    case 3:
-    case 4:
-    case 5:
-    case 6:
-    case 7:
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	{
-	  rtx xoperands[2];
-	  xoperands[0] = operands[0];
-	  xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-	  output_asm_insn (\"mov %1,%0\", xoperands);
-	  return \"\";
-	}
-
-      if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
-	  && GET_CODE (operands[1]) == CONST_INT)
-	{
-	  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-	  if (((val & 0x80) && ! (val & 0xffffff00))
-	      || ((val & 0x800000) && ! (val & 0xff000000)))
-	    return \"movu %1,%0\";
-	}
-      return \"mov %1,%0\";
-    case 8:
-    case 9:
-      return \"movbu %1,%0\";
-    }
-}"
-  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=dx,*a,dx,*a,dx,*a,dx,*a,dx,m")
-	(match_operand:QI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dx"))]
-  "register_operand (operands[0], QImode)
-   || register_operand (operands[1], QImode)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-      return \"nop\";
-    case 2:
-      return \"clr %0\";
-    case 3:
-    case 4:
-    case 5:
-    case 6:
-    case 7:
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	{
-	  rtx xoperands[2];
-	  xoperands[0] = operands[0];
-	  xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-	  output_asm_insn (\"mov %1,%0\", xoperands);
-	  return \"\";
-	}
-
-      return \"mov %1,%0\";
-    case 8:
-    case 9:
-      return \"movbu %1,%0\";
-    }
-}"
-  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
-
-;; movhi
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand (operand1, HImode)
-      && !register_operand (operand0, HImode))
-    operands[1] = copy_to_mode_reg (HImode, operand1);
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=dx,a,dx,a,dx,a,dx,a,dxa,m")
-	(match_operand:HI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dxa"))]
-  "TARGET_AM33
-   && (register_operand (operands[0], HImode)
-       || register_operand (operands[1], HImode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-      return \"nop\";
-    case 2:
-      return \"clr %0\";
-    case 3:
-    case 4:
-    case 5:
-    case 6:
-    case 7:
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	{
-	  rtx xoperands[2];
-	  xoperands[0] = operands[0];
-	  xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-	  output_asm_insn (\"mov %1,%0\", xoperands);
-	  return \"\";
-	}
-
-      if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
-	  && GET_CODE (operands[1]) == CONST_INT)
-	{
-	  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-	  if (((val & 0x80) && ! (val & 0xffffff00))
-	      || ((val & 0x800000) && ! (val & 0xff000000)))
-	    return \"movu %1,%0\";
-	}
-      return \"mov %1,%0\";
-    case 8:
-    case 9:
-      return \"movhu %1,%0\";
-    }
-}"
-  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=dx,*a,dx,*a,dx,*a,dx,*a,dx,m")
-	(match_operand:HI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dx"))]
-  "register_operand (operands[0], HImode)
-   || register_operand (operands[1], HImode)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-      return \"nop\";
-    case 2:
-      return \"clr %0\";
-    case 3:
-    case 4:
-    case 5:
-    case 6:
-    case 7:
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	{
-	  rtx xoperands[2];
-	  xoperands[0] = operands[0];
-	  xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-	  output_asm_insn (\"mov %1,%0\", xoperands);
-	  return \"\";
-	}
-      return \"mov %1,%0\";
-    case 8:
-    case 9:
-      return \"movhu %1,%0\";
-    }
-}"
-  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
-
-;; movsi and helpers
-
-;; We use this to handle addition of two values when one operand is the
-;; stack pointer and the other is a memory reference of some kind.  Reload
-;; does not handle them correctly without this expander.
-(define_expand "reload_insi"
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(match_operand:SI 1 "impossible_plus_operand" ""))
-   (clobber (match_operand:SI 2 "register_operand" "=&r"))]
-  ""
-  "
-{
-  if (XEXP (operands[1], 0) == stack_pointer_rtx)
-    {
-      if (GET_CODE (XEXP (operands[1], 1)) == SUBREG
-	  && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 1)))
-	      > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 1))))))
-	emit_move_insn (operands[2],
-			gen_rtx (ZERO_EXTEND, GET_MODE (XEXP (operands[1], 1)),
-				 SUBREG_REG (XEXP (operands[1], 1))));
-      else
-	emit_move_insn (operands[2], XEXP (operands[1], 1));
-      emit_move_insn (operands[0], XEXP (operands[1], 0));
-    }
-  else
-    {
-      if (GET_CODE (XEXP (operands[1], 0)) == SUBREG
-	  && (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 0)))
-	      > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 0))))))
-	emit_move_insn (operands[2],
-			gen_rtx (ZERO_EXTEND, GET_MODE (XEXP (operands[1], 0)),
-				 SUBREG_REG (XEXP (operands[1], 0))));
-      else
-	emit_move_insn (operands[2], XEXP (operands[1], 0));
-      emit_move_insn (operands[0], XEXP (operands[1], 1));
-    }
-  emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
-  DONE;
-}")
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand (operand1, SImode)
-      && !register_operand (operand0, SImode))
-    operands[1] = copy_to_mode_reg (SImode, operand1);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand"
-				"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax,axR,y")
-	(match_operand:SI 1 "general_operand"
-				"0,0,I,I,dx,ax,dx,ax,dixm,aixm,dixm,aixm,xy,axR"))]
-  "register_operand (operands[0], SImode)
-   || register_operand (operands[1], SImode)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-      return \"nop\";
-    case 2:
-      return \"clr %0\";
-    case 3:
-    case 4:
-    case 5:
-    case 6:
-    case 7:
-    case 8:
-    case 9:
-    case 10:
-    case 11:
-    case 12:
-    case 13:
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	{
-	  rtx xoperands[2];
-	  xoperands[0] = operands[0];
-	  xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-	  output_asm_insn (\"mov %1,%0\", xoperands);
-	  return \"\";
-	}
-
-      if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
-	  && GET_CODE (operands[1]) == CONST_INT)
-	{
-	  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-	  if (((val & 0x80) && ! (val & 0xffffff00))
-	      || ((val & 0x800000) && ! (val & 0xff000000)))
-	    return \"movu %1,%0\";
-	}
-      return \"mov %1,%0\";
-    }
-}"
-  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand (operand1, SFmode)
-      && !register_operand (operand0, SFmode))
-    operands[1] = copy_to_mode_reg (SFmode, operand1);
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=dx,ax,dx,a,daxm,dax")
-	(match_operand:SF 1 "general_operand" "0,0,G,G,dax,daxim"))]
-  "register_operand (operands[0], SFmode)
-   || register_operand (operands[1], SFmode)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-      return \"nop\";
-    case 2:
-      return \"clr %0\";
-    case 3:
-    case 4:
-    case 5:
-      if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
-	  && GET_CODE (operands[1]) == CONST_INT)
-	{
-	  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-	  if (((val & 0x80) && ! (val & 0xffffff00))
-	      || ((val & 0x800000) && ! (val & 0xff000000)))
-	    return \"movu %1,%0\";
-	}
-      return \"mov %1,%0\";
-    }
-}"
-  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit")])
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand (operand1, DImode)
-      && !register_operand (operand0, DImode))
-    operands[1] = copy_to_mode_reg (DImode, operand1);
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "general_operand"
-				"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
-	(match_operand:DI 1 "general_operand"
-				"0,0,I,I,dx,ax,dx,ax,dxim,axim,dxim,axim"))]
-  "register_operand (operands[0], DImode)
-   || register_operand (operands[1], DImode)"
-  "*
-{
-  long val[2];
-  REAL_VALUE_TYPE rv;
-
-  switch (which_alternative)
-    {
-      case 0:
-      case 1:
-	return \"nop\";
-
-      case 2:
-	return \"clr %L0\;clr %H0\";
-
-      case 3:
-	if (rtx_equal_p (operands[0], operands[1]))
-	  return \"sub %L1,%L0\;mov %L0,%H0\";
-	else
-	  return \"mov %1,%L0\;mov %L0,%H0\";
-      case 4:
-      case 5:
-      case 6:
-      case 7:
-      case 8:
-      case 9:
-      case 10:
-      case 11:
-	if (GET_CODE (operands[1]) == CONST_INT)
-	  {
-	    val[0] = INTVAL (operands[1]);
-	    val[1] = val[0] < 0 ? -1 : 0;
-	  }
-	if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	  {
-	    if (GET_MODE (operands[1]) == DFmode)
-	      {
-		REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-		REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
-	      }
-	    else if (GET_MODE (operands[1]) == VOIDmode
-		     || GET_MODE (operands[1]) == DImode)
-	      {
-		val[0] = CONST_DOUBLE_LOW (operands[1]);
-		val[1] = CONST_DOUBLE_HIGH (operands[1]);
-	      }
-	  }
-
-	if (GET_CODE (operands[1]) == MEM
-	    && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
-	  {
-	    rtx temp = operands[0];
-
-	    while (GET_CODE (temp) == SUBREG)
-	      temp = SUBREG_REG (temp);
-
-	    if (GET_CODE (temp) != REG)
-	      abort ();
-
-	    if (reg_overlap_mentioned_p (gen_rtx (REG, SImode, REGNO (temp)),
-					 XEXP (operands[1], 0)))
-	      return \"mov %H1,%H0\;mov %L1,%L0\";
-	    else
-	      return \"mov %L1,%L0\;mov %H1,%H0\";
-	      
-	  }
-	else if (GET_CODE (operands[1]) == MEM
-		 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
-		 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
-	  {
-	    rtx xoperands[2];
-
-	    xoperands[0] = operands[0];
-	    xoperands[1] = XEXP (operands[1], 0);
-
-	    output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
-			     xoperands);
-	    return \"\";
-	  }
-	else
-	  {
-	    if ((GET_CODE (operands[1]) == CONST_INT
-		 || GET_CODE (operands[1]) == CONST_DOUBLE)
-		&& val[0] == 0)
-	      {
-		if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
-		  output_asm_insn (\"clr %L0\", operands);
-		else
-		  output_asm_insn (\"mov %L1,%L0\", operands);
-	      }
-	    else if ((REGNO_REG_CLASS (true_regnum (operands[0]))
-		      == EXTENDED_REGS)
-		     && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
-			 || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
-	      output_asm_insn (\"movu %1,%0\", operands);
-	    else
-	      output_asm_insn (\"mov %L1,%L0\", operands);
-
-	    if ((GET_CODE (operands[1]) == CONST_INT
-		 || GET_CODE (operands[1]) == CONST_DOUBLE)
-		&& val[1] == 0)
-	      {
-		if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
-		  output_asm_insn (\"clr %H0\", operands);
-		else
-		  output_asm_insn (\"mov %H1,%H0\", operands);
-	      }
-	    else if ((GET_CODE (operands[1]) == CONST_INT
-		      || GET_CODE (operands[1]) == CONST_DOUBLE)
-		     && val[0] == val[1])
-	      output_asm_insn (\"mov %L0,%H0\", operands);
-	    else if ((REGNO_REG_CLASS (true_regnum (operands[0]))
-		      == EXTENDED_REGS)
-		     && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
-			 || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
-	      output_asm_insn (\"movu %1,%0\", operands);
-	    else
-	      output_asm_insn (\"mov %H1,%H0\", operands);
-	    return \"\";
-	  }
-    }
-}"
-  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register */
-  if (!register_operand (operand1, DFmode)
-      && !register_operand (operand0, DFmode))
-    operands[1] = copy_to_mode_reg (DFmode, operand1);
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand"
-				"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
-	(match_operand:DF 1 "general_operand"
-				"0,0,G,G,dx,ax,dx,ax,dxim,axim,dxim,axim"))]
-  "register_operand (operands[0], DFmode)
-   || register_operand (operands[1], DFmode)"
-  "*
-{
-  long val[2];
-  REAL_VALUE_TYPE rv;
-
-  switch (which_alternative)
-    {
-      case 0:
-      case 1:
-	return \"nop\";
-
-      case 2:
-	return \"clr %L0\;clr %H0\";
-
-      case 3:
-	 if (rtx_equal_p (operands[0], operands[1]))
-	   return \"sub %L1,%L0\;mov %L0,%H0\";
-	 else
-	   return \"mov %1,%L0\;mov %L0,%H0\";
-      case 4:
-      case 5:
-      case 6:
-      case 7:
-      case 8:
-      case 9:
-      case 10:
-      case 11:
-	if (GET_CODE (operands[1]) == CONST_INT)
-	  {
-	    val[0] = INTVAL (operands[1]);
-	    val[1] = val[0] < 0 ? -1 : 0;
-	  }
-	if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	  {
-	    if (GET_MODE (operands[1]) == DFmode)
-	      {
-		REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-		REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
-	      }
-	    else if (GET_MODE (operands[1]) == VOIDmode
-		     || GET_MODE (operands[1]) == DImode)
-	      {
-		val[0] = CONST_DOUBLE_LOW (operands[1]);
-		val[1] = CONST_DOUBLE_HIGH (operands[1]);
-	      }
-	  }
-
-	if (GET_CODE (operands[1]) == MEM
-	    && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
-	  {
-	    rtx temp = operands[0];
-
-	    while (GET_CODE (temp) == SUBREG)
-	      temp = SUBREG_REG (temp);
-
-	    if (GET_CODE (temp) != REG)
-	      abort ();
-
-	    if (reg_overlap_mentioned_p (gen_rtx (REG, SImode, REGNO (temp)),
-					 XEXP (operands[1], 0)))
-	      return \"mov %H1,%H0\;mov %L1,%L0\";
-	    else
-	      return \"mov %L1,%L0\;mov %H1,%H0\";
-	      
-	  }
-	else if (GET_CODE (operands[1]) == MEM
-		 && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
-		 && REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
-	  {
-	    rtx xoperands[2];
-
-	    xoperands[0] = operands[0];
-	    xoperands[1] = XEXP (operands[1], 0);
-
-	    output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
-			     xoperands);
-	    return \"\";
-	  }
-	else
-	  {
-	    if ((GET_CODE (operands[1]) == CONST_INT
-		 || GET_CODE (operands[1]) == CONST_DOUBLE)
-		&& val[0] == 0)
-	      {
-		if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
-		  output_asm_insn (\"clr %L0\", operands);
-		else
-		  output_asm_insn (\"mov %L1,%L0\", operands);
-	      }
-	    else if ((REGNO_REG_CLASS (true_regnum (operands[0]))
-		      == EXTENDED_REGS)
-		     && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
-			 || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
-	      output_asm_insn (\"movu %1,%0\", operands);
-	    else
-	      output_asm_insn (\"mov %L1,%L0\", operands);
-
-	    if ((GET_CODE (operands[1]) == CONST_INT
-		 || GET_CODE (operands[1]) == CONST_DOUBLE)
-		&& val[1] == 0)
-	      {
-		if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
-		  output_asm_insn (\"clr %H0\", operands);
-		else
-		  output_asm_insn (\"mov %H1,%H0\", operands);
-	      }
-	    else if ((GET_CODE (operands[1]) == CONST_INT
-		      || GET_CODE (operands[1]) == CONST_DOUBLE)
-		     && val[0] == val[1])
-	      output_asm_insn (\"mov %L0,%H0\", operands);
-	    else if ((REGNO_REG_CLASS (true_regnum (operands[0]))
-		      == EXTENDED_REGS)
-		     && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
-			 || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
-	      output_asm_insn (\"movu %1,%0\", operands);
-	    else
-	      output_asm_insn (\"mov %H1,%H0\", operands);
-	    return \"\";
-	  }
-    }
-}"
-  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
-  
-
-
-;; ----------------------------------------------------------------------
-;; TEST INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; Go ahead and define tstsi so we can eliminate redundant tst insns
-;; when we start trying to optimize this port.
-(define_insn "tstsi"
-  [(set (cc0) (match_operand:SI 0 "register_operand" "dax"))]
-  ""
-  "* return output_tst (operands[0], insn);"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx,!a")))]
-  "TARGET_AM33"
-  "* return output_tst (operands[0], insn);"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx")))]
-  ""
-  "* return output_tst (operands[0], insn);"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx,!a")))]
-  "TARGET_AM33"
-  "* return output_tst (operands[0], insn);"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx")))]
-  ""
-  "* return output_tst (operands[0], insn);"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "register_operand" "!*d*a*x,dax")
-		 (match_operand:SI 1 "nonmemory_operand" "!*0,daxi")))]
-  ""
-  "@
-  add 0,%0
-  cmp %1,%0"
-  [(set_attr "cc" "invert,compare")])
-
-;; ----------------------------------------------------------------------
-;; ADD INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  /* We can't add a variable amount directly to the stack pointer;
-     so do so via a temporary register.  */
-  if (operands[0] == stack_pointer_rtx
-      && GET_CODE (operands[1]) != CONST_INT
-      && GET_CODE (operands[2]) != CONST_INT)
-   {
-     rtx temp = gen_reg_rtx (SImode);
-     emit_move_insn (temp, gen_rtx (PLUS, SImode, operands[1], operands[2]));
-     emit_move_insn (operands[0], temp);
-     DONE;
-   }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
-		 (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
-  "TARGET_AM33"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-      return \"inc %0\";
-    case 2:
-      return \"inc4 %0\";
-    case 3:
-    case 4:
-      return \"add %2,%0\";
-    case 5:
-      {
-	enum reg_class src1_class, src2_class, dst_class;
-
-	src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
-	src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
-	dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
-	
-	/* I'm not sure if this can happen or not.  Might as well be prepared
-	  and generate the best possible code if it does happen.  */
-	if (true_regnum (operands[0]) == true_regnum (operands[1]))
-	  return \"add %2,%0\";
-	if (true_regnum (operands[0]) == true_regnum (operands[2]))
-	  return \"add %1,%0\";
-
-	/* Catch cases where no extended register was used.  These should be
-	   handled just like the mn10300.  */
-	if (src1_class != EXTENDED_REGS
-	    && src2_class != EXTENDED_REGS
-	    && dst_class != EXTENDED_REGS)
-	  {
-	    /* We have to copy one of the sources into the destination, then
-	       add the other source to the destination.
-
-	       Carefully select which source to copy to the destination; a naive
-	       implementation will waste a byte when the source classes are 
-	       different and the destination is an address register.  Selecting
-	       the lowest cost register copy will optimize this sequence.  */
-	    if (REGNO_REG_CLASS (true_regnum (operands[1]))
-		== REGNO_REG_CLASS (true_regnum (operands[0])))
-	      return \"mov %1,%0\;add %2,%0\";
-	    return \"mov %2,%0\;add %1,%0\";
-	  }
-
-	/* At least one register is an extended register.  */
-
-	/* The three operand add instruction on the am33 is a win iff the
-	   output register is an extended register, or if both source
-	   registers are extended registers.  */
-	if (dst_class == EXTENDED_REGS
-	    || src1_class == src2_class)
-	  return \"add %2,%1,%0\";
-
-      /* It is better to copy one of the sources to the destination, then
-	 perform a 2 address add.  The destination in this case must be
-	 an address or data register and one of the sources must be an
-	 extended register and the remaining source must not be an extended
-	 register.
-
-	 The best code for this case is to copy the extended reg to the
-	 destination, then emit a two address add.  */
-      if (src1_class == EXTENDED_REGS)
-	return \"mov %1,%0\;add %2,%0\";
-      return \"mov %2,%0\;add %1,%0\";
-      }
-    }
-}"
-  [(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
-		 (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-    case 1:
-      return \"inc %0\";
-    case 2:
-      return \"inc4 %0\";
-    case 3:
-    case 4:
-      return \"add %2,%0\";
-    case 5:
-      /* I'm not sure if this can happen or not.  Might as well be prepared
-	 and generate the best possible code if it does happen.  */
-      if (true_regnum (operands[0]) == true_regnum (operands[1]))
-	return \"add %2,%0\";
-      if (true_regnum (operands[0]) == true_regnum (operands[2]))
-	return \"add %1,%0\";
-
-      /* We have to copy one of the sources into the destination, then add
-	 the other source to the destination.
-
-	 Carefully select which source to copy to the destination; a naive
-	 implementation will waste a byte when the source classes are different
-	 and the destination is an address register.  Selecting the lowest
-	 cost register copy will optimize this sequence.  */
-      if (REGNO_REG_CLASS (true_regnum (operands[1]))
-	  == REGNO_REG_CLASS (true_regnum (operands[0])))
-	return \"mov %1,%0\;add %2,%0\";
-      return \"mov %2,%0\;add %1,%0\";
-    }
-}"
-  [(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
-
-;; ----------------------------------------------------------------------
-;; SUBTRACT INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 1 "register_operand" "")
-		  (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dax,!dax")
-	(minus:SI (match_operand:SI 1 "register_operand" "0,dax")
-		  (match_operand:SI 2 "nonmemory_operand" "daxi,dax")))]
-  "TARGET_AM33"
-  "*
-{
-  if (true_regnum (operands[0]) == true_regnum (operands[1]))
-    return \"sub %2,%0\";
-  else
-    {
-      enum reg_class src1_class, src2_class, dst_class;
-
-      src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
-      src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
-      dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
-
-      /* If no extended registers are used, then the best way to handle
-	 this is to copy the first source operand into the destination
-	 and emit a two address subtraction.  */
-      if (src1_class != EXTENDED_REGS
-	  && src2_class != EXTENDED_REGS
-	  && dst_class != EXTENDED_REGS
-	  && true_regnum (operands[0]) != true_regnum (operands[2]))
-	return \"mov %1,%0\;sub %2,%0\";
-      return \"sub %2,%1,%0\";
-    }
-}"
-  [(set_attr "cc" "set_zn")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dax")
-	(minus:SI (match_operand:SI 1 "register_operand" "0")
-		  (match_operand:SI 2 "nonmemory_operand" "daxi")))]
-  ""
-  "sub %2,%0"
-  [(set_attr "cc" "set_zn")])
-
-(define_expand "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-        (neg:SI (match_operand:SI 1 "register_operand" "")))]
-  ""
-  "
-{
-  rtx target = gen_reg_rtx (SImode);
-
-  emit_move_insn (target, GEN_INT (0));
-  emit_insn (gen_subsi3 (target, target, operands[1]));
-  emit_move_insn (operands[0], target);
-  DONE;
-}")
-
-;; ----------------------------------------------------------------------
-;; MULTIPLY INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "mulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=dax")
-        (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "dax"))
-                 (sign_extend:DI (match_operand:SI 2 "register_operand" "dax"))))]
-  "TARGET_AM33"
-  "mul %1,%2,%H0,%L0"
-  [(set_attr "cc" "set_zn")])
-
-(define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=dax")
-        (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "dax"))
-                 (zero_extend:DI (match_operand:SI 2 "register_operand" "dax"))))]
-  "TARGET_AM33"
-  "mulu %1,%2,%H0,%L0"
-  [(set_attr "cc" "set_zn")])
-
-(define_expand "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(mult:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
-	(mult:SI (match_operand:SI 1 "register_operand" "%0,0")
-		 (match_operand:SI 2 "nonmemory_operand" "dx,daxi")))]
-  "TARGET_AM33"
-  "*
-{
-  if (TARGET_MULT_BUG)
-    return \"nop\;nop\;mul %2,%0\";
-  else
-    return \"mul %2,%0\";
-}"
-  [(set_attr "cc" "set_zn")])
-  
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx")
-	(mult:SI (match_operand:SI 1 "register_operand" "%0")
-		 (match_operand:SI 2 "register_operand" "dx")))]
-  ""
-  "*
-{
-  if (TARGET_MULT_BUG)
-    return \"nop\;nop\;mul %2,%0\";
-  else
-    return \"mul %2,%0\";
-}"
-  [(set_attr "cc" "set_zn")])
-
-(define_insn "udivmodsi4"
-  [(set (match_operand:SI 0 "general_operand" "=dx")
-	(udiv:SI (match_operand:SI 1 "general_operand" "0")
-		 (match_operand:SI 2 "general_operand" "dx")))
-   (set (match_operand:SI 3 "general_operand" "=&d")
-	(umod:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "*
-{
-  output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
-
-  if (find_reg_note (insn, REG_UNUSED, operands[3]))
-    return \"divu %2,%0\";
-  else
-    return \"divu %2,%0\;mov mdr,%3\";
-}"
-  [(set_attr "cc" "set_zn")])
-
-(define_insn "divmodsi4"
-  [(set (match_operand:SI 0 "general_operand" "=dx")
-	(div:SI (match_operand:SI 1 "general_operand" "0")
-		 (match_operand:SI 2 "general_operand" "dx")))
-   (set (match_operand:SI 3 "general_operand" "=d")
-	(mod:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "*
-{
-  if (find_reg_note (insn, REG_UNUSED, operands[3]))
-    return \"ext %0\;div %2,%0\";
-  else
-    return \"ext %0\;div %2,%0\;mov mdr,%3\";
-}"
-  [(set_attr "cc" "set_zn")])
-
-
-;; ----------------------------------------------------------------------
-;; AND INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_expand "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(and:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax")
-	(and:SI (match_operand:SI 1 "register_operand" "%0,0,dax")
-		(match_operand:SI 2 "nonmemory_operand" "N,dxi,dax")))]
-  "TARGET_AM33"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
-    return \"extbu %0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
-    return \"exthu %0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
-    return \"add %0,%0\;lsr 1,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
-    return \"asl2 %0\;lsr 2,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
-    return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
-    return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
-    return \"lsr 1,%0\;add %0,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
-    return \"lsr 2,%0\;asl2 %0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
-    return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
-    return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
-  if (REG_P (operands[2]) && REG_P (operands[1])
-      && true_regnum (operands[0]) != true_regnum (operands[1])
-      && true_regnum (operands[0]) != true_regnum (operands[2])
-      && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
-      && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
-      && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
-    return \"mov %1,%0\;and %2,%0\";
-  if (REG_P (operands[2]) && REG_P (operands[1])
-      && true_regnum (operands[0]) != true_regnum (operands[1])
-      && true_regnum (operands[0]) != true_regnum (operands[2]))
-    return \"and %1,%2,%0\";
-  if (REG_P (operands[2]) && REG_P (operands[0])
-      && true_regnum (operands[2]) == true_regnum (operands[0]))
-    return \"and %1,%0\";
-  return \"and %2,%0\";
-}"
-  [(set_attr "cc" "none_0hit,set_znv,set_znv")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx,dx")
-	(and:SI (match_operand:SI 1 "register_operand" "%0,0")
-		(match_operand:SI 2 "nonmemory_operand" "N,dxi")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
-    return \"extbu %0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
-    return \"exthu %0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
-    return \"add %0,%0\;lsr 1,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
-    return \"asl2 %0\;lsr 2,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
-    return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
-    return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
-    return \"lsr 1,%0\;add %0,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
-    return \"lsr 2,%0\;asl2 %0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
-    return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
-    return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
-  return \"and %2,%0\";
-}"
-  [(set_attr "cc" "none_0hit,set_znv")])
-
-;; ----------------------------------------------------------------------
-;; OR INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_expand "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ior:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
-	(ior:SI (match_operand:SI 1 "register_operand" "%0,dax")
-		(match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
-  "TARGET_AM33"
-  "*
-{
-  if (REG_P (operands[2]) && REG_P (operands[1])
-      && true_regnum (operands[0]) != true_regnum (operands[1])
-      && true_regnum (operands[0]) != true_regnum (operands[2])
-      && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
-      && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
-      && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
-    return \"mov %1,%0\;or %2,%0\";
-  if (REG_P (operands[2]) && REG_P (operands[1])
-      && true_regnum (operands[0]) != true_regnum (operands[1])
-      && true_regnum (operands[0]) != true_regnum (operands[2]))
-    return \"or %1,%2,%0\";
-  if (REG_P (operands[2]) && REG_P (operands[0])
-      && true_regnum (operands[2]) == true_regnum (operands[0]))
-    return \"or %1,%0\";
-  return \"or %2,%0\";
-}"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx")
-	(ior:SI (match_operand:SI 1 "register_operand" "%0")
-		(match_operand:SI 2 "nonmemory_operand" "dxi")))]
-  ""
-  "or %2,%0"
-  [(set_attr "cc" "set_znv")])
-
-;; ----------------------------------------------------------------------
-;; XOR INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_expand "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(xor:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
-	(xor:SI (match_operand:SI 1 "register_operand" "%0,dax")
-		(match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
-  "TARGET_AM33"
-  "*
-{
-  if (REG_P (operands[2]) && REG_P (operands[1])
-      && true_regnum (operands[0]) != true_regnum (operands[1])
-      && true_regnum (operands[0]) != true_regnum (operands[2])
-      && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
-      && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
-      && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
-    return \"mov %1,%0\;xor %2,%0\";
-  if (REG_P (operands[2]) && REG_P (operands[1])
-      && true_regnum (operands[0]) != true_regnum (operands[1])
-      && true_regnum (operands[0]) != true_regnum (operands[2]))
-    return \"xor %1,%2,%0\";
-  if (REG_P (operands[2]) && REG_P (operands[0])
-      && true_regnum (operands[2]) == true_regnum (operands[0]))
-    return \"xor %1,%0\";
-  return \"xor %2,%0\";
-}"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx")
-	(xor:SI (match_operand:SI 1 "register_operand" "%0")
-		(match_operand:SI 2 "nonmemory_operand" "dxi")))]
-  ""
-  "xor %2,%0"
-  [(set_attr "cc" "set_znv")])
-
-;; ----------------------------------------------------------------------
-;; NOT INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_expand "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(not:SI (match_operand:SI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
-	(not:SI (match_operand:SI 1 "register_operand" "0,0")))]
-  "TARGET_AM33"
-  "not %0"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx")
-	(not:SI (match_operand:SI 1 "register_operand" "0")))]
-  ""
-  "not %0"
-  [(set_attr "cc" "set_znv")])
-
-;; -----------------------------------------------------------------
-;; BIT FIELDS
-;; -----------------------------------------------------------------
-
-
-;; These set/clear memory in byte sized chunks.
-;;
-;; They are no smaller/faster than loading the value into a register
-;; and storing the register, but they don't need a scratch register
-;; which may allow for better code generation.
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=R,d") (const_int 0))]
-  ""
-  "@
-  bclr 255,%A0
-  clr %0"
-  [(set_attr "cc" "clobber")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=R,d") (const_int -1))]
-  ""
-  "@
-  bset 255,%A0
-  mov -1,%0"
-  [(set_attr "cc" "clobber,none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "+R,d")
-	(subreg:QI
-	  (and:SI (subreg:SI (match_dup 0) 0)
-		  (match_operand:SI 1 "const_int_operand" "i,i")) 0))]
-  ""
-  "@
-  bclr %N1,%A0
-  and %1,%0"
-  [(set_attr "cc" "clobber,set_znv")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "+R,d")
-	(subreg:QI
-	  (ior:SI (subreg:SI (match_dup 0) 0)
-		  (match_operand:SI 1 "const_int_operand" "i,i")) 0))]
-  ""
-  "@
-  bset %1,%A0
-  or %1,%0"
-  [(set_attr "cc" "clobber,set_znv")])
-
-(define_insn ""
-  [(set (cc0)
-     (zero_extract:SI (match_operand:SI 0 "register_operand" "dx")
-		      (match_operand 1 "const_int_operand" "")
-		      (match_operand 2 "const_int_operand" "")))]
-  ""
-  "*
-{
-  int len = INTVAL (operands[1]);
-  int bit = INTVAL (operands[2]);
-  int mask = 0;
-  rtx xoperands[2];
-
-  while (len > 0)
-    {
-      mask |= (1 << bit);
-      bit++;
-      len--;
-    }
-
-  xoperands[0] = operands[0];
-  xoperands[1] = GEN_INT (mask);
-  output_asm_insn (\"btst %1,%0\", xoperands);
-  return \"\";
-}"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (cc0)
-     (zero_extract:SI (match_operand:QI 0 "general_operand" "R,dx")
-		      (match_operand 1 "const_int_operand" "")
-		      (match_operand 2 "const_int_operand" "")))]
-  "mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))"
-  "*
-{
-  int len = INTVAL (operands[1]);
-  int bit = INTVAL (operands[2]);
-  int mask = 0;
-  rtx xoperands[2];
-
-  while (len > 0)
-    {
-      mask |= (1 << bit);
-      bit++;
-      len--;
-    }
-
-  /* If the source operand is not a reg (ie it is memory), then extract the
-     bits from mask that we actually want to test.  Note that the mask will
-     never cross a byte boundary.  */
-  if (!REG_P (operands[0]))
-    {
-      if (mask & 0xff)
-	mask = mask & 0xff;
-      else if (mask & 0xff00)
-	mask = (mask >> 8) & 0xff;
-      else if (mask & 0xff0000)
-	mask = (mask >> 16) & 0xff;
-      else if (mask & 0xff000000)
-	mask = (mask >> 24) & 0xff;
-    }
-  
-  xoperands[0] = operands[0];
-  xoperands[1] = GEN_INT (mask);
-  if (GET_CODE (operands[0]) == REG)
-    output_asm_insn (\"btst %1,%0\", xoperands);
-  else
-    output_asm_insn (\"btst %1,%A0\", xoperands);
-  return \"\";
-}"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "dx")
-		      (match_operand:SI 1 "const_int_operand" "")))]
-  ""
-  "btst %1,%0"
-  [(set_attr "cc" "set_znv")])
-
-(define_insn ""
-  [(set (cc0)
-     (and:SI
-       (subreg:SI (match_operand:QI 0 "general_operand" "R,dx") 0)
-       (match_operand:SI 1 "const_8bit_operand" "")))]
-  ""
-  "@
-  btst %1,%A0
-  btst %1,%0"
-  [(set_attr "cc" "set_znv")])
-
-
-;; ----------------------------------------------------------------------
-;; JUMP INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; Conditional jump instructions
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
-      && (GET_CODE (operands[1]) == GT
-	  || GET_CODE (operands[1]) == GE
-	  || GET_CODE (operands[1]) == LE
-	  || GET_CODE (operands[1]) == LT))
-    return 0;
-  return \"b%b1 %0\";
-}"
- [(set_attr "cc" "none")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
-      && (GET_CODE (operands[1]) == GT
-	  || GET_CODE (operands[1]) == GE
-	  || GET_CODE (operands[1]) == LE
-	  || GET_CODE (operands[1]) == LT))
-    return 0;
-  return \"b%B1 %0\";
-}"
- [(set_attr "cc" "none")])
-
-;; Unconditional and other jump instructions.
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "jmp %l0"
- [(set_attr "cc" "none")])
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "a"))]
-  ""
-  "jmp (%0)"
-  [(set_attr "cc" "none")])
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "a"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmp  (%0)"
-  [(set_attr "cc" "none")])
-
-;; Call subroutine with no return value.
-
-(define_expand "call"
-  [(call (match_operand:QI 0 "general_operand" "")
-	 (match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (! call_address_operand (XEXP (operands[0], 0)))
-    XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
-  emit_call_insn (gen_call_internal (XEXP (operands[0], 0), operands[1]));
-  DONE;
-}")
-
-(define_insn "call_internal"
-  [(call (mem:QI (match_operand:SI 0 "call_address_operand" "aS"))
-	 (match_operand:SI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  if (REG_P (operands[0]))
-    return \"calls %C0\";
-  else
-    return \"call %C0,[],0\";
-}"
-  [(set_attr "cc" "clobber")])
-
-;; Call subroutine, returning value in operand 0
-;; (which must be a hard register).
-
-(define_expand "call_value"
-  [(set (match_operand 0 "" "")
-	(call (match_operand:QI 1 "general_operand" "")
-	      (match_operand:SI 2 "general_operand" "")))]
-  ""
-  "
-{
-  if (! call_address_operand (XEXP (operands[1], 0)))
-    XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
-  emit_call_insn (gen_call_value_internal (operands[0],
-					   XEXP (operands[1], 0),
-					   operands[2]));
-  DONE;
-}")
-
-(define_insn "call_value_internal"
-  [(set (match_operand 0 "" "=dax")
-	(call (mem:QI (match_operand:SI 1 "call_address_operand" "aS"))
-	      (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (REG_P (operands[1]))
-    return \"calls %C1\";
-  else
-    return \"call %C1,[],0\";
-}"
-  [(set_attr "cc" "clobber")])
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-                    (const_int 0))
-              (match_operand 1 "" "")
-              (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-  DONE;
-}")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-  [(set_attr "cc" "none")])
-
-;; ----------------------------------------------------------------------
-;; EXTEND INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(zero_extend:SI
-	 (match_operand:QI 1 "general_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx,!dax,!dax,!dax")
-	(zero_extend:SI
-	 (match_operand:QI 1 "general_operand" "0,dax,m,0,dax,m")))]
-  "TARGET_AM33"
-  "@
-  extbu %0
-  mov %1,%0\;extbu %0
-  movbu %1,%0
-  extbu %0
-  mov %1,%0\;extbu %0
-  movbu %1,%0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx")
-	(zero_extend:SI
-	 (match_operand:QI 1 "general_operand" "0,d,m")))]
-  ""
-  "@
-  extbu %0
-  mov %1,%0\;extbu %0
-  movbu %1,%0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(zero_extend:SI
-	 (match_operand:HI 1 "general_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx,!dax,!dax,!dax")
-	(zero_extend:SI
-	 (match_operand:HI 1 "general_operand" "0,dax,m,0,dax,m")))]
-  "TARGET_AM33"
-  "@
-  exthu %0
-  mov %1,%0\;exthu %0
-  movhu %1,%0
-  exthu %0
-  mov %1,%0\;exthu %0
-  movhu %1,%0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx")
-	(zero_extend:SI
-	 (match_operand:HI 1 "general_operand" "0,dx,m")))]
-  ""
-  "@
-  exthu %0
-  mov %1,%0\;exthu %0
-  movhu %1,%0"
-  [(set_attr "cc" "none_0hit")])
-
-;;- sign extension instructions
-
-(define_expand "extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(sign_extend:SI
-	 (match_operand:QI 1 "general_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=dx,dx,!dax,!dax")
-	(sign_extend:SI
-	 (match_operand:QI 1 "general_operand" "0,dx,0,dax")))]
-  "TARGET_AM33"
-  "@
-  extb %0
-  mov %1,%0\;extb %0
-  extb %0
-  mov %1,%0\;extb %0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=dx,dx")
-	(sign_extend:SI
-	 (match_operand:QI 1 "general_operand" "0,dx")))]
-  ""
-  "@
-  extb %0
-  mov %1,%0\;extb %0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_expand "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(sign_extend:SI
-	 (match_operand:HI 1 "general_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=dx,dx,!dax,!dax")
-	(sign_extend:SI
-	 (match_operand:HI 1 "general_operand" "0,dax,0,dax")))]
-  "TARGET_AM33"
-  "@
-  exth %0
-  mov %1,%0\;exth %0
-  exth %0
-  mov %1,%0\;exth %0"
-  [(set_attr "cc" "none_0hit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=dx,dx")
-	(sign_extend:SI
-	 (match_operand:HI 1 "general_operand" "0,dx")))]
-  ""
-  "@
-  exth %0
-  mov %1,%0\;exth %0"
-  [(set_attr "cc" "none_0hit")])
-
-;; ----------------------------------------------------------------------
-;; SHIFTS
-;; ----------------------------------------------------------------------
-
-(define_expand "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashift:SI
-	 (match_operand:SI 1 "register_operand" "")
-	 (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dax,dx,!dax")
-	(ashift:SI
-	 (match_operand:SI 1 "register_operand" "0,0,dax")
-	 (match_operand:QI 2 "nonmemory_operand" "J,dxi,dax")))]
-  "TARGET_AM33"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 1)
-    return \"add %0,%0\";
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 2)
-    return \"asl2 %0\";
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 3
-      && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
-    return \"asl2 %0\;add %0,%0\";
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 4
-      && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
-    return \"asl2 %0\;asl2 %0\";
-
-  if (true_regnum (operands[1]) == true_regnum (operands[0]))
-    return \"asl %S2,%0\";
-
-  if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
-      && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
-      && true_regnum (operands[0]) != true_regnum (operands[2]))
-    return \"mov %1,%0\;asl %S2,%0\";
-  return \"asl %2,%1,%0\";
-}"
-  [(set_attr "cc" "set_zn")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dax,dx,dx,dx,dx")
-	(ashift:SI
-	 (match_operand:SI 1 "register_operand" "0,0,0,0,0")
-	 (match_operand:QI 2 "nonmemory_operand" "J,K,M,L,dxi")))]
-  ""
-  "@
-  add %0,%0
-  asl2 %0
-  asl2 %0\;add %0,%0
-  asl2 %0\;asl2 %0
-  asl %S2,%0"
-  [(set_attr "cc" "set_zn")])
-
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lshiftrt:SI
-	 (match_operand:SI 1 "register_operand" "")
-	 (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
-	(lshiftrt:SI
-	 (match_operand:SI 1 "register_operand" "0,dax")
-	 (match_operand:QI 2 "nonmemory_operand" "dxi,dax")))]
-  "TARGET_AM33"
-  "*
-{
-  if (true_regnum (operands[1]) == true_regnum (operands[0]))
-    return \"lsr %S2,%0\";
-
-  if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
-      && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
-      && true_regnum (operands[0]) != true_regnum (operands[2]))
-    return \"mov %1,%0\;lsr %S2,%0\";
-  return \"lsr %2,%1,%0\";
-}"
-  [(set_attr "cc" "set_zn")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx")
-	(lshiftrt:SI
-	 (match_operand:SI 1 "register_operand" "0")
-	 (match_operand:QI 2 "nonmemory_operand" "dxi")))]
-  ""
-  "lsr %S2,%0"
-  [(set_attr "cc" "set_zn")])
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:SI
-	 (match_operand:SI 1 "register_operand" "")
-	 (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
-	(ashiftrt:SI
-	 (match_operand:SI 1 "register_operand" "0,dax")
-	 (match_operand:QI 2 "nonmemory_operand" "dxi,dax")))]
-  "TARGET_AM33"
-  "*
-{
-  if (true_regnum (operands[1]) == true_regnum (operands[0]))
-    return \"asr %S2,%0\";
-
-  if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
-      && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
-      && true_regnum (operands[0]) != true_regnum (operands[2]))
-    return \"mov %1,%0\;asr %S2,%0\";
-  return \"asr %2,%1,%0\";
-}"
-  [(set_attr "cc" "set_zn")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=dx")
-	(ashiftrt:SI
-	 (match_operand:SI 1 "register_operand" "0")
-	 (match_operand:QI 2 "nonmemory_operand" "dxi")))]
-  ""
-  "asr %S2,%0"
-  [(set_attr "cc" "set_zn")])
-
-;; ----------------------------------------------------------------------
-;; FP INSTRUCTIONS
-;; ----------------------------------------------------------------------
-;;
-;; The mn103 series does not have floating point instructions, but since
-;; FP values are held in integer regs, we can clear the high bit easily
-;; which gives us an efficient inline floating point absolute value.
-;;
-;; Similarly for negation of a FP value.
-;;
-
-(define_expand "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "")
-        (abs:DF (match_operand:DF 1 "register_operand" "")))]
-  ""
-  "
-{
-  rtx target, result, insns;
-
-  start_sequence ();
-  target = operand_subword (operands[0], 1, 1, DFmode);
-  result = expand_binop (SImode, and_optab,
-			 operand_subword_force (operands[1], 1, DFmode),
-			 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
-
-  if (result == 0)
-    abort ();
-
-  if (result != target)
-    emit_move_insn (result, target);
-
-  emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
-		  operand_subword_force (operands[1], 0, DFmode));
-
-  insns = get_insns ();
-  end_sequence ();
-
-  emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
-  DONE;
-}")
-
-(define_expand "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "")
-        (abs:SF (match_operand:SF 1 "register_operand" "")))]
-  ""
-  "
-{
-  rtx result;
-  rtx target;
-
-  target = operand_subword_force (operands[0], 0, SFmode);
-  result = expand_binop (SImode, and_optab,
-			 operand_subword_force (operands[1], 0, SFmode),
-			 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
-  if (result == 0)
-    abort ();
-
-  if (result != target)
-    emit_move_insn (result, target);
-
-  /* Make a place for REG_EQUAL.  */
-  emit_move_insn (operands[0], operands[0]);
-  DONE;
-}")
-
-
-(define_expand "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "")
-        (neg:DF (match_operand:DF 1 "register_operand" "")))]
-  ""
-  "
-{
-  rtx target, result, insns;
-
-  start_sequence ();
-  target = operand_subword (operands[0], 1, 1, DFmode);
-  result = expand_binop (SImode, xor_optab,
-			 operand_subword_force (operands[1], 1, DFmode),
-			 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
-
-  if (result == 0)
-    abort ();
-
-  if (result != target)
-    emit_move_insn (result, target);
-
-  emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
-		  operand_subword_force (operands[1], 0, DFmode));
-
-  insns = get_insns ();
-  end_sequence ();
-
-  emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
-  DONE;
-}")
-
-(define_expand "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "")
-        (neg:SF (match_operand:SF 1 "register_operand" "")))]
-  ""
-  "
-{
-  rtx result;
-  rtx target;
-
-  target = operand_subword_force (operands[0], 0, SFmode);
-  result = expand_binop (SImode, xor_optab,
-			 operand_subword_force (operands[1], 0, SFmode),
-			 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
-  if (result == 0)
-    abort ();
-
-  if (result != target)
-    emit_move_insn (result, target);
-
-  /* Make a place for REG_EQUAL.  */
-  emit_move_insn (operands[0], operands[0]);
-  DONE;
-}")
-
-
-;; ----------------------------------------------------------------------
-;; PROLOGUE/EPILOGUE
-;; ----------------------------------------------------------------------
-(define_expand "prologue"
-  [(const_int 0)]
-  ""
-  "expand_prologue (); DONE;")
-
-(define_expand "epilogue"
-  [(return)]
-  ""
-  "
-{
-  expand_epilogue ();
-  DONE;
-}")
-
-(define_insn "return_internal"
-  [(const_int 2)]
-  ""
-  "rets"
-  [(set_attr "cc" "clobber")])
-
-;; This insn restores the callee saved registers and does a return, it
-;; can also deallocate stack space.
-(define_insn "return_internal_regs"
-  [(const_int 0)
-   (match_operand:SI 0  "const_int_operand" "i")
-   (return)]
-  ""
-  "*
-{
-  int i, need_comma;
-  int d2, d3, a2, a3;
-  int exreg1;
-
-  need_comma = 0;
-  fputs (\"\\tret [\", asm_out_file);
-  if (regs_ever_live[2])
-    {
-      fputs (\"d2\", asm_out_file);
-      need_comma = 1;
-    }
-  if (regs_ever_live[3])
-    {
-      if (need_comma)
-	fputc (',', asm_out_file); 
-      fputs (\"d3\", asm_out_file);
-      need_comma = 1;
-    }
-  if (regs_ever_live[6])
-    {
-      if (need_comma)
-	fputc (',', asm_out_file); 
-      fputs (\"a2\", asm_out_file);
-      need_comma = 1;
-    }
-  if (regs_ever_live[7])
-    {
-      if (need_comma)
-	fputc (',', asm_out_file); 
-      fputs (\"a3\", asm_out_file);
-      need_comma = 1;
-    }
-  if (regs_ever_live[14] || regs_ever_live[15]
-      || regs_ever_live[16] || regs_ever_live[17])
-    {
-      if (need_comma)
-	fputc (',', asm_out_file); 
-      fputs (\"exreg1\", asm_out_file);
-      need_comma = 1;
-    }
-  fprintf (asm_out_file, \"],%d\\n\", INTVAL (operands[0]));
-  return \"\";
-}"
-  [(set_attr "cc" "clobber")])
-
-(define_insn "store_movm"
-  [(const_int 1)]
-  ""
-  "*
-{
-  int i, need_comma;
-  int d2, d3, a2, a3;
-  int exreg1;
-
-  need_comma = 0;
-  fputs (\"\\tmovm [\", asm_out_file);
-  if (regs_ever_live[2])
-    {
-      fputs (\"d2\", asm_out_file);
-      need_comma = 1;
-    }
-  if (regs_ever_live[3])
-    {
-      if (need_comma)
-	fputc (',', asm_out_file); 
-      fputs (\"d3\", asm_out_file);
-      need_comma = 1;
-    }
-  if (regs_ever_live[6])
-    {
-      if (need_comma)
-	fputc (',', asm_out_file); 
-      fputs (\"a2\", asm_out_file);
-      need_comma = 1;
-    }
-  if (regs_ever_live[7])
-    {
-      if (need_comma)
-	fputc (',', asm_out_file); 
-      fputs (\"a3\", asm_out_file);
-      need_comma = 1;
-    }
-  if (regs_ever_live[14] || regs_ever_live[15]
-      || regs_ever_live[16] || regs_ever_live[17])
-    {
-      if (need_comma)
-	fputc (',', asm_out_file); 
-      fputs (\"exreg1\", asm_out_file);
-      need_comma = 1;
-    }
-  fputs (\"],(sp)\\n\", asm_out_file);
-  return \"\";
-}"
-  [(set_attr "cc" "clobber")])
-
-(define_insn "return"
-  [(return)]
-  "can_use_return_insn ()"
-  "*
-{
-  rtx next = next_active_insn (insn);
-
-  if (next
-      && GET_CODE (next) == JUMP_INSN
-      && GET_CODE (PATTERN (next)) == RETURN)
-    return \"\";
-  else
-    return \"rets\";
-}"
-  [(set_attr "cc" "clobber")])
-
-;; Try to combine consecutive updates of the stack pointer (or any
-;; other register for that matter).
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=dxay")
-	(plus:SI (match_dup 0)
-		 (match_operand 1 "const_int_operand" "")))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (match_operand 2 "const_int_operand" "")))]
-  ""
-  "*
-{
-  operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]));
-  return \"add %1,%0\";
-}"
-  [(set_attr "cc" "clobber")])
-
-;;
-;; We had patterns to check eq/ne, but the they don't work because
-;; 0x80000000 + 0x80000000 = 0x0 with a carry out.
-;;
-;; The Z flag and C flag would be set, and we have no way to
-;; check for the Z flag set and C flag clear.
-;;
-;; This will work on the mn10200 because we can check the ZX flag
-;; if the comparison is in HImode.
-(define_peephole
-  [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
-   (set (pc) (if_then_else (ge (cc0) (const_int 0))
-			   (match_operand 1 "" "")
-			   (pc)))]
-  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
-  "add %0,%0\;bcc %1"
-  [(set_attr "cc" "clobber")])
-
-(define_peephole
-  [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
-   (set (pc) (if_then_else (lt (cc0) (const_int 0))
-			   (match_operand 1 "" "")
-			   (pc)))]
-  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
-  "add %0,%0\;bcs %1"
-  [(set_attr "cc" "clobber")])
-
-(define_peephole
-  [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
-   (set (pc) (if_then_else (ge (cc0) (const_int 0))
-			   (pc)
-			   (match_operand 1 "" "")))]
-  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
-  "add %0,%0\;bcs %1"
-  [(set_attr "cc" "clobber")])
-
-(define_peephole
-  [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
-   (set (pc) (if_then_else (lt (cc0) (const_int 0))
-			   (pc)
-			   (match_operand 1 "" "")))]
-  "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
-  "add %0,%0\;bcc %1"
-  [(set_attr "cc" "clobber")])
-
diff --git a/gcc/config/mn10300/mn10300_020422.h b/gcc/config/mn10300/mn10300_020422.h
deleted file mode 100755
index 21ae6c4..0000000
--- a/gcc/config/mn10300/mn10300_020422.h
+++ /dev/null
@@ -1,1166 +0,0 @@
-/* Definitions of target machine for GNU compiler. Matsushita MN10300 series
-   Copyright (C) 1996, 1997, 1998, 2001 Free Software Foundation, Inc.
-   Contributed by Jeff Law (law@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "svr4.h"
-
-#undef ASM_SPEC
-#undef ASM_FINAL_SPEC
-#undef LIB_SPEC
-#undef ENDFILE_SPEC
-#undef LINK_SPEC
-#undef STARTFILE_SPEC
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-D__mn10300__ -D__MN10300__"
-
-#define CPP_SPEC "%{mam33:-D__AM33__}"
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-/* Generate code to work around mul/mulq bugs on the mn10300.  */
-#define TARGET_MULT_BUG			(target_flags & 0x1)
-
-/* Generate code for the AM33 processor.  */
-#define TARGET_AM33			(target_flags & 0x2)
-
-#define TARGET_SWITCHES  \
-  {{ "mult-bug",	0x1},	\
-   { "no-mult-bug", 	-0x1},	\
-   { "am33", 		0x2},	\
-   { "am33", 		-(0x1)},\
-   { "no-am33", 	-0x2},	\
-   { "", TARGET_DEFAULT}}
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 0x1
-#endif
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fprintf (stderr, " (MN10300)");
-
-
-/* Target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is not true on the Matsushita MN1003.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* This is not true on the Matsushita MN10300.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered.
-   This is not true on the Matsushita MN10300.  */
-#define WORDS_BIG_ENDIAN 0
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD		32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD		4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 		32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY		32
-
-/* The stack goes in 32 bit lumps.  */
-#define STACK_BOUNDARY 		32
-
-/* Allocation boundary (in *bits*) for the code of a function.
-   8 is the minimum boundary; it's unclear if bigger alignments
-   would improve performance.  */
-#define FUNCTION_BOUNDARY 8
-
-/* No data type wants to be aligned rounder than this.   */
-#define BIGGEST_ALIGNMENT	32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Define this if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  */
-
-#define FIRST_PSEUDO_REGISTER 10
-#undef FIRST_PSEUDO_REGISTER
-#define FIRST_PSEUDO_REGISTER 18
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.  */
-
-#define FIXED_REGISTERS \
-  { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1}
-#undef FIXED_REGISTERS
-#define FIXED_REGISTERS \
-  { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you
-   like.  */
-
-#define CALL_USED_REGISTERS \
-  { 1, 1, 0, 0, 1, 1, 0, 0, 1, 1}
-
-#define REG_ALLOC_ORDER \
-  { 0, 1, 4, 5, 2, 3, 6, 7, 8, 9}
-
-#undef CALL_USED_REGISTERS
-#define CALL_USED_REGISTERS \
-  { 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0}
-
-#undef REG_ALLOC_ORDER
-#define REG_ALLOC_ORDER \
-  { 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9}
-
-#define CONDITIONAL_REGISTER_USAGE \
-{						\
-  if (!TARGET_AM33)				\
-    {						\
-      for (i = 10; i < 18; i++) 		\
-	fixed_regs[i] = call_used_regs[i] = 1; 	\
-    }						\
-}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
-   MODE.  */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (REGNO_REG_CLASS (REGNO) == DATA_REGS 			\
-  ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4	\
-  : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
-
-#undef HARD_REGNO_MODE_OK
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((REGNO_REG_CLASS (REGNO) == DATA_REGS \
-   || (TARGET_AM33 && REGNO_REG_CLASS (REGNO) == ADDRESS_REGS) \
-   || REGNO_REG_CLASS (REGNO) == EXTENDED_REGS) \
-  ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4	\
-  : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  (MODE1 == MODE2 || (GET_MODE_SIZE (MODE1) <= 4 && GET_MODE_SIZE (MODE2) <= 4))
-
-#undef MODES_TIEABLE_P
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  (TARGET_AM33  \
-   || MODE1 == MODE2 \
-   || (GET_MODE_SIZE (MODE1) <= 4 && GET_MODE_SIZE (MODE2) <= 4))
-
-/* 4 data, and effectively 3 address registers is small as far as I'm
-   concerned.  */
-#define SMALL_REGISTER_CLASSES 1
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-enum reg_class {
-  NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,
-  DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, 
-  EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS,
-  SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS, 
-  GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
-{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \
-  "SP_REGS", "DATA_OR_ADDRESS_REGS", "SP_OR_ADDRESS_REGS", \
-  "EXTENDED_REGS", \
-  "DATA_OR_EXTENDED_REGS", "ADDRESS_OR_EXTENDED_REGS", \
-  "SP_OR_EXTENDED_REGS", "SP_OR_ADDRESS_OR_EXTENDED_REGS", \
-  "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS  			\
-{      0,		/* No regs      */	\
-   0x00f,		/* DATA_REGS */		\
-   0x1f0,		/* ADDRESS_REGS */	\
-   0x200,		/* SP_REGS */		\
-   0x1ff,		/* DATA_OR_ADDRESS_REGS */\
-   0x1f0,		/* SP_OR_ADDRESS_REGS */\
-   0x1ff,		/* GENERAL_REGS */    	\
-   0x3ff,		/* ALL_REGS 	*/	\
-}
-
-/* This may not be strictly necessary, but I don't offhand know if having bits
-   higher than FIRST_PSEUDO_REGISTER set in this macro is safe.  */
-#undef REG_CLASS_CONTENTS
-#define REG_CLASS_CONTENTS  			\
-{      0,		/* No regs      */	\
-   0x0000f,		/* DATA_REGS */		\
-   0x001f0,		/* ADDRESS_REGS */	\
-   0x00200,		/* SP_REGS */		\
-   0x001ff,		/* DATA_OR_ADDRESS_REGS */\
-   0x003f0,		/* SP_OR_ADDRESS_REGS */\
-   0x2fc00,		/* EXTENDED_REGS */	\
-   0x2fc0f,		/* DATA_OR_EXTENDED_REGS */	\
-   0x2fdf0,		/* ADDRESS_OR_EXTENDED_REGS */	\
-   0x2fe00,		/* SP_OR_EXTENDED_REGS */	\
-   0x2fff0,		/* SP_OR_ADDRESS_OR_EXTENDED_REGS */	\
-   0x2fdff,		/* GENERAL_REGS */    	\
-   0x2ffff,		/* ALL_REGS 	*/	\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) \
-  ((REGNO) < 4 ? DATA_REGS : \
-   (REGNO) < 9 ? ADDRESS_REGS : \
-    (REGNO) == 9 ? SP_REGS : 0)
-
-#undef REGNO_REG_CLASS
-#define REGNO_REG_CLASS(REGNO) \
-  ((REGNO) < 4 ? DATA_REGS : \
-   (REGNO) < 9 ? ADDRESS_REGS : \
-    (REGNO) == 9 ? SP_REGS : \
-     (REGNO) < 18 ? EXTENDED_REGS : 0)
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS DATA_REGS
-#define BASE_REG_CLASS  SP_OR_ADDRESS_REGS
-
-#undef INDEX_REG_CLASS
-#define INDEX_REG_CLASS DATA_OR_EXTENDED_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'd' ? DATA_REGS : \
-   (C) == 'a' ? ADDRESS_REGS : \
-   (C) == 'x' ? EXTENDED_REGS : \
-   (C) == 'y' ? SP_REGS : NO_REGS)
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
- 
-#define REGNO_OK_FOR_BASE_P(regno) \
-  (((regno) > 3 && regno < FIRST_PSEUDO_REGISTER)	\
-   || (reg_renumber[regno] > 3 && reg_renumber[regno] < FIRST_PSEUDO_REGISTER))
-
-#define REGNO_OK_FOR_BIT_BASE_P(regno) \
-  (((regno) > 3 && regno < 10)	\
-   || (reg_renumber[regno] > 3 && reg_renumber[regno] < 10))
-
-#define REGNO_OK_FOR_INDEX_P(regno) \
-  (((regno) >= 0 && regno < 4)	\
-   || ((regno) >= 10 && regno < 18)	\
-   || (reg_renumber[regno] >= 10 && reg_renumber[regno] < 18) \
-   || (reg_renumber[regno] >= 0 && reg_renumber[regno] < 4))
-
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
-  (X == stack_pointer_rtx && CLASS != SP_REGS ? ADDRESS_REGS : CLASS)
-
-#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) \
-  (X == stack_pointer_rtx && CLASS != SP_REGS ? ADDRESS_REGS : CLASS)
-
-#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
-  ((MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
-
-#undef PREFERRED_RELOAD_CLASS
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
-  (X == stack_pointer_rtx && CLASS != SP_REGS \
-   ? ADDRESS_OR_EXTENDED_REGS : CLASS)
-
-#undef PREFERRED_OUTPUT_RELOAD_CLASS
-#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) \
-  (X == stack_pointer_rtx && CLASS != SP_REGS \
-   ? ADDRESS_OR_EXTENDED_REGS : CLASS)
-
-#undef LIMIT_RELOAD_CLASS
-#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
-  (!TARGET_AM33 && (MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
-
-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
-  secondary_reload_class(CLASS,MODE,IN)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* The letters I, J, K, L, M, N, O, P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.  */
-
-#define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100)
-#define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000)
-
-#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
-#define CONST_OK_FOR_J(VALUE) ((VALUE) == 1)
-#define CONST_OK_FOR_K(VALUE) ((VALUE) == 2)
-#define CONST_OK_FOR_L(VALUE) ((VALUE) == 4)
-#define CONST_OK_FOR_M(VALUE) ((VALUE) == 3)
-#define CONST_OK_FOR_N(VALUE) ((VALUE) == 255 || (VALUE) == 65535)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
-   (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
-   (C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
-   (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
-   (C) == 'M' ? CONST_OK_FOR_M (VALUE) : \
-   (C) == 'N' ? CONST_OK_FOR_N (VALUE) : 0)
-
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself. 
-     
-  `G' is a floating-point zero.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT	\
-		 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) : 0)
-
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-
-#define STARTING_FRAME_OFFSET 0
-
-/* Offset of first parameter from the argument pointer register value.  */
-/* Is equal to the size of the saved fp + pc, even if an fp isn't
-   saved since the value is used before we know.  */
-
-#define FIRST_PARM_OFFSET(FNDECL) 4
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 9
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 7
-
-/* Base register for access to arguments of the function.  This
-   is a fake register and will be eliminated into either the frame
-   pointer or stack pointer.  */
-#define ARG_POINTER_REGNUM 8
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 5
-
-#define ELIMINABLE_REGS				\
-{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},	\
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
-
-#define CAN_ELIMINATE(FROM, TO) 1
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
-  OFFSET = initial_offset (FROM, TO)
-
-/* We can debug without frame pointers on the mn10300, so eliminate
-   them whenever possible.  */
-#define FRAME_POINTER_REQUIRED 0
-#define CAN_DEBUG_WITHOUT_FP
-
-/* A guess for the MN10300.  */
-#define PROMOTE_PROTOTYPES 1
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* We use d0/d1 for passing parameters, so allocate 8 bytes of space
-   for a register flushback area.  */
-#define REG_PARM_STACK_SPACE(DECL) 8
-#define OUTGOING_REG_PARM_STACK_SPACE
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* So we can allocate space for return pointers once for the function
-   instead of around every call.  */
-#define STACK_POINTER_OFFSET 4
-
-/* 1 if N is a possible register number for function argument passing.
-   On the MN10300, no registers are used in this way.  */
-
-#define FUNCTION_ARG_REGNO_P(N) ((N) <= 1)
-
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the MN10300, this is a single integer, which is a number of bytes
-   of arguments scanned so far.  */
-
-#define CUMULATIVE_ARGS struct cum_arg
-struct cum_arg {int nbytes; };
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the MN10300, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM).nbytes = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM).nbytes += ((MODE) != BLKmode			\
-	           ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
-	           : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On the MN10300 all args are pushed.  */   
-
-extern struct rtx_def *function_arg ();
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  function_arg (&CUM, MODE, TYPE, NAMED)
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-  function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
-
-
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)		\
-  ((TYPE) && int_size_in_bytes (TYPE) > 8)
- 
-#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
-  ((TYPE) && int_size_in_bytes (TYPE) > 8)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.   */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), POINTER_TYPE_P (VALTYPE) ? 4 : 0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
-
-/* 1 if N is a possible register number for a function value.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 4)
-
-/* Return values > 8 bytes in length in memory.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-#define RETURN_IN_MEMORY(TYPE)  \
-  (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode)
-
-/* Register in which address to store a structure value
-   is passed to a function.  On the MN10300 it's passed as
-   the first parameter.  */
-
-#define STRUCT_VALUE 0
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) ;
-
-#define TRAMPOLINE_TEMPLATE(FILE)			\
-  do {							\
-    fprintf (FILE, "\tadd -4,sp\n");			\
-    fprintf (FILE, "\t.long 0x0004fffa\n");		\
-    fprintf (FILE, "\tmov (0,sp),a0\n");		\
-    fprintf (FILE, "\tadd 4,sp\n");			\
-    fprintf (FILE, "\tmov (13,a0),a1\n");		\
-    fprintf (FILE, "\tmov (17,a0),a0\n");		\
-    fprintf (FILE, "\tjmp (a0)\n");			\
-    fprintf (FILE, "\t.long 0\n");			\
-    fprintf (FILE, "\t.long 0\n");			\
-  } while (0)
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 0x1b
-
-#define TRAMPOLINE_ALIGNMENT 32
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 0x14)),	\
- 		 (CXT));						\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 0x18)),	\
-		 (FNADDR));						\
-}
-/* A C expression whose value is RTL representing the value of the return
-   address for the frame COUNT steps up from the current frame.
-
-   On the mn10300, the return address is not at a constant location
-   due to the frame layout.  Luckily, it is at a constant offset from
-   the argument pointer, so we define RETURN_ADDR_RTX to return a
-   MEM using arg_pointer_rtx.  Reload will replace arg_pointer_rtx
-   with a reference to the stack/frame pointer + an appropriate offset.  */
-
-#define RETURN_ADDR_RTX(COUNT, FRAME)   \
-  ((COUNT == 0)                         \
-   ? gen_rtx (MEM, Pmode, arg_pointer_rtx) \
-   : (rtx) 0)
-
-/* Emit code for a call to builtin_saveregs.  We must emit USE insns which
-   reference the 2 integer arg registers.
-   Ordinarily they are not call used registers, but they are for
-   _builtin_saveregs, so we must make this explicit.  */
-
-extern struct rtx_def *mn10300_builtin_saveregs ();
-#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) mn10300_builtin_saveregs (ARGLIST)
-
-/* Addressing modes, and classification of registers for them.  */
-
-
-/* 1 if X is an rtx for a constant that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   CONSTANT_P (X)
-
-/* Extra constraints.  */
- 
-#define OK_FOR_R(OP) \
-   (GET_CODE (OP) == MEM					\
-    && GET_MODE (OP) == QImode					\
-    && (CONSTANT_ADDRESS_P (XEXP (OP, 0))			\
-	|| (GET_CODE (XEXP (OP, 0)) == REG			\
-	    && REG_OK_FOR_BIT_BASE_P (XEXP (OP, 0))		\
-	    && XEXP (OP, 0) != stack_pointer_rtx)		\
-	|| (GET_CODE (XEXP (OP, 0)) == PLUS			\
-	    && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG		\
-	    && REG_OK_FOR_BIT_BASE_P (XEXP (XEXP (OP, 0), 0))	\
-	    && XEXP (XEXP (OP, 0), 0) != stack_pointer_rtx	\
-	    && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT	\
-	    && INT_8_BITS (INTVAL (XEXP (XEXP (OP, 0), 1))))))
-	 
-#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'R' ? OK_FOR_R (OP) : (C) == 'S' ? GET_CODE (OP) == SYMBOL_REF : 0)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X)  \
-  ((REGNO (X) >= 0 && REGNO(X) <= 3) || REGNO (X) >= 10)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-  ((REGNO (X) >= 4 && REGNO(X) <= 9) || REGNO (X) >= 10)
-#define REG_OK_FOR_BIT_BASE_P(X) \
-  ((REGNO (X) >= 4 && REGNO(X) <= 9))
-#else
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BIT_BASE_P(X) REGNO_OK_FOR_BIT_BASE_P (REGNO (X))
-#endif
-
-
-#define HAVE_POST_INCREMENT (TARGET_AM33)
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
-   except for CONSTANT_ADDRESS_P which is actually
-   machine-independent.
-
-   On the mn10300, the value in the address register must be
-   in the same memory space/segment as the effective address.
-
-   This is problematical for reload since it does not understand
-   that base+index != index+base in a memory reference.
-
-   Note it is still possible to use reg+reg addressing modes,
-   it's just much more difficult.  For a discussion of a possible
-   workaround and solution, see the comments in pa.c before the
-   function record_unscaled_index_insn_codes.  */
-
-/* Accept either REG or SUBREG where a register is valid.  */
-  
-#define RTX_OK_FOR_BASE_P(X)					\
-  ((REG_P (X) && REG_OK_FOR_BASE_P (X))				\
-   || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))		\
-       && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)    	\
-{							\
-  if (CONSTANT_ADDRESS_P (X))				\
-    goto ADDR;						\
-  if (RTX_OK_FOR_BASE_P (X))				\
-    goto ADDR;						\
-  if (TARGET_AM33					\
-      && GET_CODE (X) == POST_INC			\
-      && RTX_OK_FOR_BASE_P (XEXP (X, 0))		\
-      && (MODE == SImode || MODE == SFmode || MODE == HImode))\
-    goto ADDR;						\
-  if (GET_CODE (X) == PLUS)				\
-    {							\
-      rtx base = 0, index = 0;				\
-      if (REG_P (XEXP (X, 0))				\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 0)))		\
-	base = XEXP (X, 0), index = XEXP (X, 1);	\
-      if (REG_P (XEXP (X, 1))				\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 1)))		\
-	base = XEXP (X, 1), index = XEXP (X, 0);	\
-      if (base != 0 && index != 0)			\
-	{						\
-	  if (GET_CODE (index) == CONST_INT)		\
-	    goto ADDR;					\
-	}						\
-    }							\
-}
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.   */
-
-extern struct rtx_def *legitimize_address ();
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)  \
-{ rtx orig_x = (X);				\
-  (X) = legitimize_address (X, OLDX, MODE);	\
-  if ((X) != orig_x && memory_address_p (MODE, X)) \
-    goto WIN; }
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.  */
-
-#undef GO_IF_MODE_DEPENDENT_ADDRESS
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)        \
-  if (GET_CODE (ADDR) == POST_INC) \
-    goto LABEL
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  No extra ones are needed for the vax.  */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define CC_OVERFLOW_UNUSABLE 0x200
-#define CC_NO_CARRY CC_NO_OVERFLOW
-#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:							\
-    /* Zeros are extremely cheap.  */					\
-    if (INTVAL (RTX) == 0 && OUTER_CODE == SET)				\
-      return 0;								\
-    /* If it fits in 8 bits, then it's still relatively cheap.  */	\
-    if (INT_8_BITS (INTVAL (RTX)))					\
-      return 1;								\
-    /* This is the "base" cost, includes constants where either the	\
-       upper or lower 16bits are all zeros.  */				\
-    if (INT_16_BITS (INTVAL (RTX))					\
-	|| (INTVAL (RTX) & 0xffff) == 0					\
-	|| (INTVAL (RTX) & 0xffff0000) == 0)				\
-      return 2;								\
-    return 4;								\
-  /* These are more costly than a CONST_INT, but we can relax them,	\
-     so they're less costly than a CONST_DOUBLE.  */			\
-  case CONST:								\
-  case LABEL_REF:							\
-  case SYMBOL_REF:							\
-    return 6;								\
-  /* We don't optimize CONST_DOUBLEs well nor do we relax them well,	\
-     so their cost is very high.  */					\
-  case CONST_DOUBLE:							\
-    return 8;
-
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)  (CLASS1 != CLASS2 ? 4 : 2)
-
-#undef REGISTER_MOVE_COST
-#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
-  ((CLASS1 == CLASS2 && (CLASS1 == ADDRESS_REGS || CLASS1 == DATA_REGS)) ? 2 :\
-   CLASS1 == CLASS2 && CLASS1 == EXTENDED_REGS ? 6 : 4)
-
-/* A crude cut at RTX_COSTS for the MN10300.  */
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  */
-#define RTX_COSTS(RTX,CODE,OUTER_CODE) \
-  case UMOD:		\
-  case UDIV:		\
-  case MOD:		\
-  case DIV:		\
-    return 8;		\
-  case MULT:		\
-    return 8;
-
-/* Nonzero if access to memory by bytes or half words is no faster
-   than accessing full words.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* Dispatch tables on the mn10300 are extremely expensive in terms of code
-   and readonly data size.  So we crank up the case threshold value to
-   encourage a series of if/else comparisons to implement many small switch
-   statements.  In theory, this value could be increased much more if we
-   were solely optimizing for space, but we keep it "reasonable" to avoid
-   serious code efficiency lossage.  */
-#define CASE_VALUES_THRESHOLD 6
-
-#define NO_FUNCTION_CSE
-
-/* According expr.c, a value of around 6 should minimize code size, and
-   for the MN10300 series, that's our primary concern.  */
-#define MOVE_RATIO 6
-
-#define TEXT_SECTION_ASM_OP "\t.section .text"
-#define DATA_SECTION_ASM_OP "\t.section .data"
-#define BSS_SECTION_ASM_OP "\t.section .bss"
-
-/* Output at beginning/end of assembler file.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) asm_file_start(FILE)
-
-#define ASM_COMMENT_START "#"
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* This is how to output an assembler line defining a `double' constant.
-   It is .dfloat or .gfloat, depending.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.double %s\n", dstr);		\
-   } while (0)
-
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.float %s\n", dstr);		\
-   } while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE, VALUE)		\
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE, VALUE)		\
-( fprintf (FILE, "\t.hword "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE, VALUE)		\
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-#define ASM_OUTPUT_BYTE(FILE, VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* This says how to output the assembler to define a global
-   uninitialized but not common symbol.
-   Try to use asm_output_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE, NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE, NAME)	\
-  do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE, NAME)	          \
-  do {                                            \
-  char* real_name;                                \
-  STRIP_NAME_ENCODING (real_name, (NAME));        \
-  fprintf (FILE, "_%s", real_name);               \
-  } while (0)           
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
-
-/* This is how we tell the assembler that two symbols have the same value.  */
-
-#define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
-  do { assemble_name(FILE, NAME1); 	 \
-       fputs(" = ", FILE);		 \
-       assemble_name(FILE, NAME2);	 \
-       fputc('\n', FILE); } while (0)
-
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp" }
-
-#undef REGISTER_NAMES
-#define REGISTER_NAMES \
-{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp", \
-  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" }
-
-/* Print an instruction operand X on file FILE.
-   look in mn10300.c for details */
-
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand(FILE,X,CODE)
-
-/* Print a memory operand whose address is X, on file FILE.
-   This uses a function in output-vax.c.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-  asm_fprintf (FILE, "\t%s .L%d\n", ".long", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL)
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", (LOG))
-
-/* We don't have to worry about dbx compatibility for the mn10300.  */
-#define DEFAULT_GDB_EXTENSIONS 1
-
-/* Use stabs debugging info by default.  */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#define DBX_REGISTER_NUMBER(REGNO) REGNO
-
-/* GDB always assumes the current function's frame begins at the value
-   of the stack pointer upon entry to the current function.  Accessing
-   local variables and parameters passed on the stack is done using the
-   base of the frame + an offset provided by GCC.
-
-   For functions which have frame pointers this method works fine;
-   the (frame pointer) == (stack pointer at function entry) and GCC provides
-   an offset relative to the frame pointer.
-
-   This loses for functions without a frame pointer; GCC provides an offset
-   which is relative to the stack pointer after adjusting for the function's
-   frame size.  GDB would prefer the offset to be relative to the value of
-   the stack pointer at the function's entry.  Yuk!  */
-#define DEBUGGER_AUTO_OFFSET(X) \
-  ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
-    + (frame_pointer_needed \
-       ? 0 : -initial_offset (FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM)))
-
-#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
-  ((GET_CODE (X) == PLUS ? OFFSET : 0) \
-    + (frame_pointer_needed \
-       ? 0 : -initial_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM)))
-
-/* Define to use software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion. */
-#define REAL_ARITHMETIC
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE Pmode
-
-/* Define this if the case instruction drops through after the table
-   when the index is out of range.  Don't define it if the case insn
-   jumps to the default label instead.  */
-#define CASE_DROPS_THROUGH
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.  */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX	4
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* The assembler op to get a word.  */
-
-#define FILE_ASM_OP "\t.file\n"
-
-extern void asm_file_start ();
-extern int const_costs ();
-extern void print_operand ();
-extern void print_operand_address ();
-extern void expand_prologue ();
-extern void expand_epilogue ();
-extern void notice_update_cc ();
-extern int call_address_operand ();
-extern int impossible_plus_operand ();
-extern enum reg_class secondary_reload_class ();
-extern int initial_offset ();
-extern char *output_tst ();
-int symbolic_operand ();
diff --git a/gcc/config/mn10300/t-mn10300 b/gcc/config/mn10300/t-mn10300
deleted file mode 100755
index 04a5ea0..0000000
--- a/gcc/config/mn10300/t-mn10300
+++ /dev/null
@@ -1,29 +0,0 @@
-LIBGCC1=libgcc1.null
-CROSS_LIBGCC1=libgcc1.null
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-
-# We want fine grained libraries, so use the new code to build the
-# floating point emulation libraries.
-FPBIT = fp-bit.c
-DPBIT = dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#ifdef __LITTLE_ENDIAN__' > dp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>dp-bit.c
-	echo '#endif' 		>> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#ifdef __LITTLE_ENDIAN__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>fp-bit.c
-	echo '#endif' 		>> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-MULTILIB_OPTIONS = mam33
-MULTILIB_DIRNAMES = am33 
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/mn10300/xm-mn10300.h b/gcc/config/mn10300/xm-mn10300.h
deleted file mode 100755
index 63d61c2..0000000
--- a/gcc/config/mn10300/xm-mn10300.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Configuration for Matsushita MN10300. 
-   Copyright (C) 1996 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-
-#include "tm.h"
-
-#ifndef __STDC__
-extern char *malloc (), *realloc (), *calloc ();
-#else
-extern void *malloc (), *realloc (), *calloc ();
-#endif
-extern void free ();
diff --git a/gcc/config/msdos/configur.bat b/gcc/config/msdos/configur.bat
deleted file mode 100755
index 03e4109..0000000
--- a/gcc/config/msdos/configur.bat
+++ /dev/null
@@ -1,47 +0,0 @@
-@echo off

-echo Configuring GCC for go32

-rem This batch file assumes a unix-type "sed" program

-

-if not exist config\msdos\configure.bat chdir ..\..

-

-update config\i386\xm-dos.h config.h

-update config\i386\xm-dos.h hconfig.h

-update config\i386\xm-dos.h tconfig.h

-update config\i386\go32.h tm.h

-update config\i386\i386.md md

-update config\i386\i386.c aux-output.c

-

-echo # Makefile generated by "configure.bat"> Makefile

-echo all.dos: cccp cc1 cc1obj xgcc libgcc.a s-objlist >> Makefile

-sed -f config/msdos/top.sed Makefile.in >> Makefile

-

-set LANG=

-

-if not exist ada\make-lang.in goto no_ada

-sed -f config/msdos/top.sed ada\make-lang.in >> Makefile

-sed -f config/msdos/top.sed ada\makefile.in > ada\Makefile

-set LANG=%LANG% ada.&   

-:no_ada

-

-if not exist cp\make-lang.in goto no_cp

-sed -f config/msdos/top.sed cp\make-lang.in >> Makefile

-sed -f config/msdos/top.sed cp\makefile.in > cp\Makefile

-set LANG=%LANG% c++.&	

-:no_cp

-

-echo lang.mostlyclean: %LANG% | sed "s/&/mostlyclean/g" >> Makefile

-echo lang.clean: %LANG% | sed "s/&/clean/g" >> Makefile

-echo lang.distclean: %LANG% | sed "s/&/distclean/g" >> Makefile

-echo lang.maintainer-clean: %LANG% | sed "s/&/maintainer-clean/g" >> Makefile

-echo /* options.h */ > options.h

-if exist cp\lang-options.h echo #include "cp/lang-options.h" >> options.h

-if exist ada\lang-options.h echo #include "ada/lang-options.h" >> options.h

-if exist f\lang-options.h echo #include "f/lang-options.h" >> options.h

-echo /* specs.h */ > specs.h

-if exist cp\lang-specs.h echo #include "cp/lang-specs.h" >> specs.h

-if exist ada\lang-specs.h echo #include "ada/lang-specs.h" >> specs.h

-if exist f\lang-specs.h echo #include "f/lang-specs.h" >> specs.h

-

-echo #define MULTILIB_SELECT ". ;" > multilib.h1

-update multilib.h1 multilib.h

-del multilib.h1

diff --git a/gcc/config/msdos/libgcc.mak b/gcc/config/msdos/libgcc.mak
deleted file mode 100755
index 5f480b1..0000000
--- a/gcc/config/msdos/libgcc.mak
+++ /dev/null
@@ -1,14 +0,0 @@
-# Build libgcc.a

-

-libgcc.a : libgcc1.c libgcc2.c mklibgcc

-	./mklibgcc -c

-	./mklibgcc '$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES)' libgcc1.c $(LIB1FUNCS)

-	./mklibgcc '$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES)' libgcc2.c $(LIB2FUNCS)

-	-command /c mklibnow.bat

-	-command /c del libgcc.a

-	ar rvs libgcc.a lgcctmp/*.o

-

-mklibgcc : config/msdos/mklibgcc.c

-	gcc $(CFLAGS) $^ -o $@

-

-

diff --git a/gcc/config/msdos/mklibgcc.c b/gcc/config/msdos/mklibgcc.c
deleted file mode 100755
index 705b3d5..0000000
--- a/gcc/config/msdos/mklibgcc.c
+++ /dev/null
@@ -1,98 +0,0 @@
-#include <stdio.h>

-#include <string.h>

-#include <dirent.h>

-

-char *skips[] = {

-  "__main",

-  "_ctors",

-  "_exit",

-  "_ctor_list",

-  "_dtor_list",

-  0

-};

-

-int

-do_clean()

-{

-  DIR *dir;

-  struct dirent *de;

-  remove("mklibnow.bat");

-

-  dir = opendir("lgcctmp");

-  if (!dir)

-    return 0;

-  while ((de=readdir(dir)))

-  {

-    char buf[30];

-    if (de->d_name[0] == '.')

-      continue;

-    sprintf(buf, "lgcctmp/%s", de->d_name);

-    unlink(buf);

-  }

-  closedir(dir);

-  return 0;

-}

-

-int

-main(int argc, char **argv)

-{

-  char *cc = argv[1];

-  char *csrc=argv[2];

-  int i;

-  FILE *batfile;

-  FILE *cfile;

-

-  if (argc > 1 && strcmp(argv[1], "-c")==0)

-    return do_clean();

-

-  mkdir("lgcctmp", 0755);

-

-  batfile = fopen("mklibnow.bat", "a");

-  if (!batfile)

-  {

-    perror("mklibnow.bat");

-    return 1;

-  }

-  fprintf(batfile, "@echo off\n");

-

-  for (i=3; i<argc; i++)

-  {

-    char basename[30], *bp;

-    int s;

-    for (s=0; skips[s]; s++)

-      if (strcmp(skips[s], argv[i]) == 0)

-	break;

-    if (skips[s])

-      continue;

-    strcpy(basename, "lgcctmp/");

-    if (strncmp(argv[i], "_fix", 4)==0)

-    {

-      strcat(basename, "fx");

-      strcat(basename, argv[i]+4);

-    }

-    else if (strncmp(argv[i], "_float", 4)==0)

-    {

-      strcat(basename, "flt");

-      strcat(basename, argv[i]+6);

-    }

-    else

-    {

-      strcat(basename, argv[i]);

-    }

-    bp = basename + strlen(basename);

-    fprintf(batfile, "%s -c %s.c -o %s.o\n", cc, basename, basename);

-    strcpy(bp, ".c");

-    cfile = fopen(basename, "w");

-    if (cfile)

-    {

-      *bp = 0;

-      fprintf(cfile, "#define L%s\n#include \"%s\"\n", argv[i], csrc);

-      fclose(cfile);

-    }

-    else

-      perror(basename);

-  }

-

-  fclose(batfile);

-  return 0;

-}

diff --git a/gcc/config/msdos/top.sed b/gcc/config/msdos/top.sed
deleted file mode 100755
index 64027f5..0000000
--- a/gcc/config/msdos/top.sed
+++ /dev/null
@@ -1,57 +0,0 @@
-/\.o[ 	]*:/ s/config.status//
-/^multilib.h/ s/multilib/not-multilib/
-/^target=/ c\
-target=go32
-/^out_file=/ c\
-out_file=config/i386/i386.c
-/^out_object_file=/ c\
-out_object_file=i386.o
-/^md_file=/ c\
-md_file=config/i386/i386.md
-/^tm_file=/ c\
-tm_file=config/i386/go32.h
-/^build_xm_file=/ c\
-build_xm_file=config/i386/xm-dos.h
-/^host_xm_file=/ c\
-host_xm_file=config/i386/xm-dos.h
-/^lang_specs_files=/ d
-/^lang_options_files=/ d
-/^xmake_file=/ d
-/^tmake_file=/ d
-/^version=/ c\
-version=2.8.1
-/^mainversion=/ c\
-mainversion=2.8.1
-s/CC = cc/CC = gcc/
-s/:\$/: \$/g
-s/^	\ *\.\//	/
-s/<\ *\$(srcdir)\//< $(srcdir)\\/g
-s/^	\$(srcdir)\/move-if-change/	update/
-s/^USE_/# USE_/
-s/`echo \$(srcdir)\///g
-s/ | sed 's,\^\\\.\/,,'`//g
-s/^	cd \$(srcdir)[ 	]*;/	/
-/^# USE_HOST_OBSTACK/ i\
-USE_HOST_OBSTACK=obstack.o
-/^stamp-attrtab/,/update/ {
-  /\\/d
-  /[ 	]fi[ 	]/d
-  /[ 	]fi$/d
-  /update/ i\
-	genattrtab md > t-attrtab.c
-}
-/^enquire[ 	]*:/ s/\$(GCC_PARTS)//g
-/^enquire.o[ 	]*:/ s/\$(GCC_PASSES)//g
-/^GCC_FOR_TARGET =/ c\
-GCC_FOR_TARGET = gcc
-s/; *@true//
-s/stamp-/s-/g
-s/tmp-/t-/g
-/> *s-objlist/ c\
-	echo.exe -o s-objlist $(addprefix ../,$(OBJS))
-/^OBJS.*s-objlist/ s?`cat ../s-objlist`?@../s-objlist?
-s/^\(SUBDIR_OBSTACK *=\).*$/\1 ..\/obstack.o/
-s/^\(SUBDIR_USE_ALLOCA *=\).*$/\1/
-s/^\(SUBDIR_MALLOC *=\).*$/\1/
-/^# Build libgcc.a/ r config/msdos/libgcc.mak
-/^# Build libgcc.a/,// d
diff --git a/gcc/config/netbsd.h b/gcc/config/netbsd.h
deleted file mode 100755
index 0fb4d40..0000000
--- a/gcc/config/netbsd.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/* NETBSD_NATIVE is defined when gcc is integrated into the NetBSD
-   source tree so it can be configured appropriately without using
-   the GNU configure/build mechanism. */
-
-#ifdef NETBSD_NATIVE
-
-/* Look for the include files in the system-defined places.  */
-
-#undef GPLUSPLUS_INCLUDE_DIR
-#define GPLUSPLUS_INCLUDE_DIR "/usr/include/g++"
-
-#undef GCC_INCLUDE_DIR
-#define GCC_INCLUDE_DIR "/usr/include"
-
-#undef INCLUDE_DEFAULTS
-#define INCLUDE_DEFAULTS			\
-  {						\
-    { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1 },	\
-    { GCC_INCLUDE_DIR, "GCC", 0, 0 },		\
-    { 0, 0, 0, 0 }				\
-  }
-
-/* Under NetBSD, the normal location of the compiler back ends is the
-   /usr/libexec directory.  */
-
-#undef STANDARD_EXEC_PREFIX
-#define STANDARD_EXEC_PREFIX		"/usr/libexec/"
-
-/* Under NetBSD, the normal location of the various *crt*.o files is the
-   /usr/lib directory.  */
-
-#undef STANDARD_STARTFILE_PREFIX
-#define STANDARD_STARTFILE_PREFIX	"/usr/lib/"
-
-#endif
-
-
-/* Provide a CPP_SPEC appropriate for NetBSD.  Current we just deal with
-   the GCC option `-posix'.  */
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{posix:-D_POSIX_SOURCE}"
-
-/* Provide an ASM_SPEC appropriate for NetBSD.  Currently we only deal
-   with the options for generating PIC code.  */
-
-#undef ASM_SPEC
-#define ASM_SPEC " %| %{fpic:-k} %{fPIC:-k -K}"
-
-/* Provide a LIB_SPEC appropriate for NetBSD.  Just select the appropriate
-   libc, depending on whether we're doing profiling.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
-
-/* Provide a LINK_SPEC appropriate for NetBSD.  Here we provide support
-   for the special GCC options -static, -assert, and -nostdlib.  */
-
-#undef LINK_SPEC
-#define LINK_SPEC \
-  "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{R*} %{static:-Bstatic} %{assert*}"
-
-/* This defines which switch letters take arguments. */
-#undef SWITCH_TAKES_ARG
-#define SWITCH_TAKES_ARG(CHAR) \
-  (DEFAULT_SWITCH_TAKES_ARG(CHAR) \
-   || (CHAR) == 'R')
-
-/* We have atexit(3).  */
-
-#define HAVE_ATEXIT
-
-/* Implicit library calls should use memcpy, not bcopy, etc.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Handle #pragma weak and #pragma pack.  */
-
-#define HANDLE_SYSV_PRAGMA
-
-/*
- * Some imports from svr4.h in support of shared libraries.
- * Currently, we need the DECLARE_OBJECT_SIZE stuff.
- */
-
-/* Define the strings used for the .type, .size, and .set directives.
-   These strings generally do not vary from one system running netbsd
-   to another, but if a given system needs to use different pseudo-op
-   names for these, they may be overridden in the file which includes
-   this one.  */
-
-#undef TYPE_ASM_OP
-#undef SIZE_ASM_OP
-#undef SET_ASM_OP
-#define TYPE_ASM_OP	".type"
-#define SIZE_ASM_OP	".size"
-#define SET_ASM_OP	".set"
-
-/* This is how we tell the assembler that a symbol is weak.  */
-
-#undef ASM_WEAKEN_LABEL
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
-  do { fputs ("\t.globl\t", FILE); assemble_name (FILE, NAME); \
-       fputc ('\n', FILE); \
-       fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \
-       fputc ('\n', FILE); } while (0)
-
-/* The following macro defines the format used to output the second
-   operand of the .type assembler directive.  Different svr4 assemblers
-   expect various different forms for this operand.  The one given here
-   is just a default.  You may need to override it in your machine-
-   specific tm.h file (depending upon the particulars of your assembler).  */
-
-#undef TYPE_OPERAND_FMT
-#define TYPE_OPERAND_FMT	"@%s"
-
-/* Write the extra assembler code needed to declare a function's result.
-   Most svr4 assemblers don't require any special declaration of the
-   result value, but there are exceptions.  */
-
-#ifndef ASM_DECLARE_RESULT
-#define ASM_DECLARE_RESULT(FILE, RESULT)
-#endif
-
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare a function properly.
-   Some svr4 assemblers need to also have something extra said about the
-   function's return value.  We allow for that here.  */
-
-#undef ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "function");			\
-    putc ('\n', FILE);							\
-    ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));			\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Write the extra assembler code needed to declare an object properly.  */
-
-#undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
-    putc ('\n', FILE);							\
-    size_directive_output = 0;						\
-    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-      {									\
-	size_directive_output = 1;					\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-	fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));	\
-      }									\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#undef ASM_FINISH_DECLARE_OBJECT
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
-	 assemble_name (FILE, name);					 \
-	 fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL))); \
-       }								 \
-   } while (0)
-
-/* This is how to declare the size of a function.  */
-
-#undef ASM_DECLARE_FUNCTION_SIZE
-#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)			\
-  do {									\
-    if (!flag_inhibit_size_directive)					\
-      {									\
-        char label[256];						\
-	static int labelno;						\
-	labelno++;							\
-	ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno);		\
-	ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno);		\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, (FNAME));					\
-        fprintf (FILE, ",");						\
-	assemble_name (FILE, label);					\
-        fprintf (FILE, "-");						\
-	assemble_name (FILE, (FNAME));					\
-	putc ('\n', FILE);						\
-      }									\
-  } while (0)
diff --git a/gcc/config/netware.h b/gcc/config/netware.h
deleted file mode 100755
index e509249..0000000
--- a/gcc/config/netware.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* This file is CYGNUS LOCAL.  */
-
-/* netware.h -- operating system specific defines to be used when 
-   targeting GCC for some generic NetWare 4 system.
-   Copyright (C) 1993, 1994 Free Software Foundation, Inc.
-
-   Written by David V. Henkel-Wallace (gumby@cygnus.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-/* We don't actually need any of these; the MD_ vars are ignored
-   anyway for cross-compilers, and the other specs won't get picked up
-   'coz the user is supposed to do ld -r (hmm, perhaps that should be
-   the default).  In any case, setting them thus will catch some
-   common user errors. */
-
-#undef MD_EXEC_PREFIX
-#undef MD_STARTFILE_PREFIX
-
-#undef	LIB_SPEC
-#define LIB_SPEC ""
-
-/* Kinda useless, but what the hell */
-#undef	LINK_SPEC
-#define LINK_SPEC "%{h*} %{V} %{v:%{!V:-V}} \
-		   %{b} %{Wl,*:%*} \
-		   %{Qy:} %{!Qn:-Qy}"
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-
-#undef	ENDFILE_SPEC
-#define ENDFILE_SPEC ""
-
-#undef	RELATIVE_PREFIX_NOT_LINKDIR
-#undef	LIBGCC_SPEC
-
-/* set debugging info */
-#define	DBX_DEBUGGING_INFO
-#undef	SDB_DEBUGGING_INFO
-#undef	DWARF_DEBUGGING_INFO
-#undef	XCOFF_DEBUGGING_INFO
-#undef	PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* Support const sections and the ctors and dtors sections for g++.
-   Note that there appears to be two different ways to support const
-   sections at the moment.  You can either #define the symbol
-   READONLY_DATA_SECTION (giving it some code which switches to the
-   readonly data section) or else you can #define the symbols
-   EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
-   SELECT_RTX_SECTION.  We do both here just to be on the safe side.  */
-
-#define	HAVE_ATEXIT
-
-#undef	HAS_INIT_SECTION
-#undef	INIT_SECTION_ASM_OP
-
-#undef	READONLY_DATA_SECTION
-#define	READONLY_DATA_SECTION	const_section 
-
-#undef	CONST_SECTION_ASM_OP
-#define CONST_SECTION_ASM_OP    ".section\t.rodata"
-#undef	CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"x\""
-#undef	DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"x\""
-
-/* A list of other sections which the compiler might be "in" at any
-   given time.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_ctors, in_dtors
-
-/* A list of extra section function definitions.  */
-
-#undef	EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CONST_SECTION_FUNCTION						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-#undef	CONST_SECTION_FUNCTION
-#define CONST_SECTION_FUNCTION                                          \
-void                                                                    \
-const_section ()                                                        \
-{                                                                       \
-  if (in_section != in_const)                                      	\
-    {                                                                   \
-      fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP);             \
-      in_section = in_const;                                            \
-    }                                                                   \
-}
-
-#undef	CTORS_SECTION_FUNCTION
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#undef	DTORS_SECTION_FUNCTION
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-#define INT_ASM_OP ".long"
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
diff --git a/gcc/config/nextstep.c b/gcc/config/nextstep.c
deleted file mode 100755
index 1c658fb..0000000
--- a/gcc/config/nextstep.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Functions for generic NeXT as target machine for GNU C compiler.
-   Copyright (C) 1989, 90-93, 96, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include "flags.h"
-#include "tree.h"
-
-/* Make everything that used to go in the text section really go there.  */
-
-int flag_no_mach_text_sections = 0;
-
-#define OPT_STRCMP(opt) (!strncmp (opt, p, sizeof (opt)-1))
-
-/* 1 if handle_pragma has been called yet.  */
-
-static int pragma_initialized;
-
-/* Initial setting of `optimize'.  */
-
-static int initial_optimize_flag;
-
-extern char *get_directive_line ();
-
-/* Called from check_newline via the macro HANDLE_PRAGMA.
-   FINPUT is the source file input stream.
-   CH is the first character after `#pragma'.
-   The result is 1 if the pragma was handled.  */
-
-int
-handle_pragma (p_getc, p_ungetc, pname)
-     int (*  p_getc) PROTO ((void));
-     void (* p_ungetc) PROTO ((int));
-     char * pname;
-{
-  int retval = 0;
-
-  /* Record initial setting of optimize flag, so we can restore it.  */
-  if (!pragma_initialized)
-    {
-      pragma_initialized = 1;
-      initial_optimize_flag = optimize;
-    }
-
-  if (strcmp (pname, "CC_OPT_ON") == 0)
-    {
-      optimize = 1, obey_regdecls = 0;
-      warning ("optimization turned on");
-      retval = 1;
-    }
-  else if (strcmp (pname, "CC_OPT_OFF") == 0)
-    {
-      optimize = 0, obey_regdecls = 1;
-      warning ("optimization turned off");
-      retval = 1;
-    }
-  else if (strcmp (pname, "CC_OPT_RESTORE") == 0)
-    {
-      extern int initial_optimize_flag;
-
-      if (optimize != initial_optimize_flag)
-	{
-	  if (initial_optimize_flag)
-	    obey_regdecls = 0;
-	  else
-	    obey_regdecls = 1;
-	  optimize = initial_optimize_flag;
-	}
-      warning ("optimization level restored");
-      retval = 1;
-    }
-  else if (strcmp (pname, "CC_WRITABLE_STRINGS") == 0)
-    flag_writable_strings = retval = 1;
-  else if (strcmp (pname, "CC_NON_WRITABLE_STRINGS") == 0)
-    flag_writable_strings = 0, retval = 1;
-  else if (strcmp (pname, "CC_NO_MACH_TEXT_SECTIONS") == 0)
-    flag_no_mach_text_sections = retval = 1;
-
-  return retval;
-}
diff --git a/gcc/config/nextstep.h b/gcc/config/nextstep.h
deleted file mode 100755
index 59050a1..0000000
--- a/gcc/config/nextstep.h
+++ /dev/null
@@ -1,601 +0,0 @@
-/* Operating system specific defines to be used when targeting GCC
-   for NeXTSTEP.
-   Copyright (C) 1989, 90-93, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Use new NeXT include file search path.
-   In a cross compiler with NeXT as target, don't expect
-   the host to use Next's directory scheme.  */
-
-#ifndef CROSS_COMPILE
-#undef	INCLUDE_DEFAULTS
-#define INCLUDE_DEFAULTS				\
-  {							\
-    { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1 },		\
-    { LOCAL_INCLUDE_DIR, 0, 0, 1 },			\
-    { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1 },		\
-    { GCC_INCLUDE_DIR, "GCC", 0, 0 },			\
-    /* These are for fixincludes-fixed ansi/bsd headers	\
-       which wouldn't be found otherwise.		\
-       (The use of string catenation here is OK since	\
-	NeXT's native compiler is derived from GCC.) */	\
-    { GCC_INCLUDE_DIR "/ansi", 0, 0, 0 },		\
-    { GCC_INCLUDE_DIR "/bsd", 0, 0, 0 },		\
-    { "/NextDeveloper/Headers", 0, 0, 0 },		\
-    { "/NextDeveloper/Headers/ansi", 0, 0, 0 },		\
-    { "/NextDeveloper/Headers/bsd", 0, 0, 0 },		\
-    { "/LocalDeveloper/Headers", 0, 0, 0 },		\
-    { "/LocalDeveloper/Headers/ansi", 0, 0, 0 },	\
-    { "/LocalDeveloper/Headers/bsd", 0, 0, 0 },		\
-    { "/NextDeveloper/2.0CompatibleHeaders", 0, 0, 0 },	\
-    { STANDARD_INCLUDE_DIR, 0, 0, 0 },                  \
-    { "/usr/include/bsd", 0, 0, 0 },			\
-    { 0, 0, 0, 0 }				       	\
-  }
-#else /* CROSS_COMPILE */
-#undef	INCLUDE_DEFAULTS
-#define INCLUDE_DEFAULTS				\
-  {							\
-    { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1 },		\
-    { GPLUSPLUS_INCLUDE_DIR, 0, 1, 1 },			\
-    { LOCAL_INCLUDE_DIR, 0, 0, 1 },			\
-    { GCC_INCLUDE_DIR, "GCC", 0, 0 },			\
-    { GCC_INCLUDE_DIR "/ansi", 0, 0, 0 },		\
-    { GCC_INCLUDE_DIR "/bsd", 0, 0, 0 },		\
-    { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1 },		\
-    { TOOL_INCLUDE_DIR "/ansi", 0, 0, 0 },		\
-    { TOOL_INCLUDE_DIR "/bsd", 0, 0, 0 },		\
-    { STANDARD_INCLUDE_DIR, 0, 0, 0 },			\
-    { "/usr/include/bsd", 0, 0, 0 },			\
-    { 0, 0, 0, 0 }					\
-  }
-#endif /* CROSS_COMPILE */
-
-#undef	EXTRA_FORMAT_FUNCTIONS
-#define EXTRA_FORMAT_FUNCTIONS \
-      "NXPrintf",	FALSE,	2,	FALSE,	\
-      "NXScanf",	TRUE,	2,	FALSE,	\
-      "NXVPrintf",	FALSE,	2,	TRUE,	\
-      "NXVScanf",	TRUE,	2,	TRUE,	\
-      "DPSPrintf",	FALSE,	2,	FALSE,	\
-      "bsd_sprintf",	FALSE,	2,	FALSE,	\
-      "bsd_vsprintf",	FALSE,	2,	TRUE,
-
-/* Make -fnext-runtime the default.  */
-
-#define NEXT_OBJC_RUNTIME
-
-/* We have atexit.  */
-
-#define HAVE_ATEXIT
-
-/* Enable recent gcc to compile under the old gcc in Next release 1.0.  */
-
-#define __inline inline
-
-/* wchar_t is unsigned short */
-
-#undef	WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-#undef	WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE (BITS_PER_WORD / 2)
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-
-#undef	DEFAULT_PCC_STRUCT_RETURN
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* These compiler options take n arguments.  */
-
-#undef	WORD_SWITCH_TAKES_ARG
-#define WORD_SWITCH_TAKES_ARG(STR)	 	\
-  (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) ? 1 :	\
-   !strcmp (STR, "segalign") ? 1 :		\
-   !strcmp (STR, "seg1addr") ? 1 :		\
-   !strcmp (STR, "segaddr") ? 2 :		\
-   !strcmp (STR, "sectobjectsymbols") ? 2 :	\
-   !strcmp (STR, "segprot") ? 3 :		\
-   !strcmp (STR, "sectcreate") ? 3 :		\
-   !strcmp (STR, "sectalign") ? 3 :		\
-   !strcmp (STR, "segcreate") ? 3 :		\
-   !strcmp (STR, "sectorder") ? 3 :		\
-   !strcmp (STR, "siff-mask") ? 1 :		\
-   !strcmp (STR, "siff-filter") ? 1 :		\
-   !strcmp (STR, "siff-warning") ? 1 :		\
-   !strcmp (STR, "arch") ? 1 :			\
-   !strcmp (STR, "pagezero_size") ? 1 :		\
-   0)
-
-#undef	WORD_SWITCH
-#define WORD_SWITCH(STR)			\
-  (WORD_SWITCH_TAKES_ARG (STR)			\
-   || !strcmp (STR, "bsd")			\
-   || !strcmp (STR, "object")			\
-   || !strcmp (STR, "ObjC")			\
-   || !strcmp (STR, "all_load"))
-
-/* Machine dependent ccp options.  */
-
-#undef	CPP_SPEC
-#define CPP_SPEC "%{!traditional: -D__STDC__}            \
-                  %{posixstrict:-D_POSIX_SOURCE}         \
-                  %{!posixstrict:%{bsd:-D__STRICT_BSD__} \
-                  %{posix:-D_POSIX_SOURCE}               \
-                  %{!ansi:-D_NEXT_SOURCE}}               \
-                  %{MD:-MD %M} %{MMD:-MMD %M}"
-
-/* Machine dependent ld options.  */
-
-#undef	LINK_SPEC
-#define LINK_SPEC "%{Z} %{M} \
-%{execute*} %{preload*} %{fvmlib*} \
-%{segalign*} %{seg1addr*} %{segaddr*} %{segprot*} \
-%{pagezero_size*} \
-%{seglinkedit*} %{noseglinkedit*} \
-%{sectcreate*} %{sectalign*} %{sectobjectsymbols}\
-%{segcreate*} %{Mach*} %{whyload} %{w} \
-%{sectorder*} %{whatsloaded} %{ObjC} %{all_load} %{object}"
-
-/* Machine dependent libraries.  */
-
-#undef	LIB_SPEC
-#define LIB_SPEC "%{!posix*:-lsys_s} %{posix*:-lposix}"
-
-/* We specify crt0.o as -lcrt0.o so that ld will search the library path. */
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC  \
-    "%{!posix*:%{pg:-lgcrt0.o}%{!pg: \
-     %{p:%e-p profiling is no longer supported.  Use -pg instead.} \
-     %{!p:-lcrt0.o}}}\
-     %{posix*:%{pg:-lgposixcrt0.o}%{!pg: \
-     %{p:%e-p profiling is no longer supported.  Use -pg instead.} \
-     %{!p:-lposixcrt0.o}}} \
-     -lcrtbegin.o"
-
-#undef	ENDFILE_SPEC
-#define ENDFILE_SPEC \
-    "-lcrtend.o"
-
-/* Allow #sscs (but don't do anything). */
-
-#define SCCS_DIRECTIVE
-
-/* We use Dbx symbol format.  */
-
-#undef	SDB_DEBUGGING_INFO
-#undef	XCOFF_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-
-/* This saves a fair amount of space. */
-
-#undef	DBX_CONTIN_LENGTH
-#define DBX_CONTIN_LENGTH 0
-
-/* These screw up NeXT's gdb at the moment, so don't use them. */
-
-#undef	DBX_OUTPUT_MAIN_SOURCE_DIRECTORY
-#define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(FILE, FILENAME)
-
-/* These come from bsd386.h, but are specific to sequent, so make sure
-   they don't bite us.  */
-
-#undef	DBX_NO_XREFS
-#undef	DBX_CONTIN_LENGTH
-
-/* gdb needs a null N_SO at the end of each file for scattered loading. */
-
-#undef	DBX_OUTPUT_MAIN_SOURCE_FILE_END
-#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME)			\
-  fprintf (FILE,							\
-	   "\t.text\n\t.stabs \"%s\",%d,0,0,Letext\nLetext:\n",		\
-	   "" , N_SO)
-
-/* Define our object format type for crtstuff.c */
-#define OBJECT_FORMAT_MACHO
-
-/* Don't use .gcc_compiled symbols to communicate with GDB;
-   They interfere with numerically sorted symbol lists. */
-
-#undef	ASM_IDENTIFY_GCC
-#define ASM_IDENTIFY_GCC(asm_out_file)
-#undef	INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP
-#undef	INVOKE__main
-
-#undef	ASM_OUTPUT_CONSTRUCTOR
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)                       \
-  do { constructor_section ();                                  \
-       ASM_OUTPUT_ALIGN (FILE, 1);                              \
-       fprintf (FILE, "\t.long ");                              \
-       assemble_name (FILE, NAME);                              \
-       fprintf (FILE, "\n");                                    \
-       fprintf (FILE, ".reference .constructors_used\n");       \
-      } while (0)
-
-#undef	ASM_OUTPUT_DESTRUCTOR
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)                        \
-  do { destructor_section ();                                   \
-       ASM_OUTPUT_ALIGN (FILE, 1);                              \
-       fprintf (FILE, "\t.long ");                              \
-       assemble_name (FILE, NAME);                              \
-       fprintf (FILE, "\n");                                    \
-       fprintf (FILE, ".reference .destructors_used\n");        \
-      } while (0)
-
-#define EH_FRAME_SECTION_ASM_OP ".section __TEXT,__eh_frame,regular"
-
-/* Don't output a .file directive.  That is only used by the assembler for
-   error reporting.  */
-#undef	ASM_FILE_START
-#define ASM_FILE_START(FILE)
-
-#undef	ASM_FILE_END
-#define ASM_FILE_END(FILE)					\
-  do {								\
-    extern char *language_string;				\
-    if (strcmp (language_string, "GNU C++") == 0)		\
-      {								\
-	constructor_section ();					\
-	destructor_section ();					\
-	ASM_OUTPUT_ALIGN (FILE, 1);				\
-      }								\
-  } while (0)
-
-/* How to parse #pragma's */
-
-#undef	HANDLE_PRAGMA
-#define HANDLE_PRAGMA(GETC, UNGETC, NAME) handle_pragma (GETC, UNGETC, NAME)
-extern int handle_pragma ();
-
-/* Give methods pretty symbol names on NeXT. */
-
-#undef	OBJC_GEN_METHOD_LABEL
-#define OBJC_GEN_METHOD_LABEL(BUF,IS_INST,CLASS_NAME,CAT_NAME,SEL_NAME,NUM) \
-  do { if (CAT_NAME)							\
-	 sprintf (BUF, "%c[%s(%s) %s]", (IS_INST) ? '-' : '+',		\
-		  (CLASS_NAME), (CAT_NAME), (SEL_NAME));		\
-       else								\
-	 sprintf (BUF, "%c[%s %s]", (IS_INST) ? '-' : '+',		\
-		  (CLASS_NAME), (SEL_NAME));				\
-     } while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX "_"
-
-/* Wrap new method names in quotes so the assembler doesn't gag.
-   Make Objective-C internal symbols local.  */
-
-#undef	ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
-  do { if (NAME[0] == '+' || NAME[0] == '-') fprintf (FILE, "\"%s\"", NAME); \
-       else if (!strncmp (NAME, "_OBJC_", 6)) fprintf (FILE, "L%s", NAME);   \
-       else if (!strncmp (NAME, ".objc_class_name_", 17))		\
-	 fprintf (FILE, "%s", NAME);					\
-       else asm_fprintf (FILE, "%U%s", NAME); } while (0)
-
-#undef	ALIGN_ASM_OP
-#define ALIGN_ASM_OP		".align"
-
-#undef	ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t%s %d\n", ALIGN_ASM_OP, (LOG))
-
-/* Ensure correct alignment of bss data.  */
-
-#undef	ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
-( fputs (".lcomm ", (FILE)),				\
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ",%u,%u\n", (SIZE), floor_log2 ((ALIGN) / BITS_PER_UNIT)))
-
-/* Output #ident as a .ident.  */
-
-#undef	ASM_OUTPUT_IDENT
-#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-
-/* The maximum alignment which the object file format can support.
-   For NeXT's Mach-O format, this is 2^15.  */
-
-#undef	MAX_OFILE_ALIGNMENT
-#define MAX_OFILE_ALIGNMENT 0x8000
-
-/* Create new Mach-O sections. */
-
-#undef	SECTION_FUNCTION
-#define SECTION_FUNCTION(FUNCTION, SECTION, DIRECTIVE, WAS_TEXT, OBJC)	\
-void									\
-FUNCTION ()								\
-{									\
-  extern void text_section ();					 	\
-  extern void objc_section_init ();					\
-  extern int flag_no_mach_text_sections;				\
-  									\
-  if (WAS_TEXT && flag_no_mach_text_sections)       			\
-    text_section ();							\
-  else if (in_section != SECTION)					\
-    {									\
-      if (OBJC)								\
-	objc_section_init ();						\
-      fprintf (asm_out_file, "%s\n", DIRECTIVE);			\
-      in_section = SECTION;						\
-    }									\
-}									\
-
-#undef	EXTRA_SECTIONS
-#define EXTRA_SECTIONS					\
-  in_const, in_cstring, in_literal4, in_literal8,	\
-  in_constructor, in_destructor,			\
-  in_objc_class, in_objc_meta_class, in_objc_category,	\
-  in_objc_class_vars, in_objc_instance_vars,		\
-  in_objc_cls_meth, in_objc_inst_meth,			\
-  in_objc_cat_cls_meth, in_objc_cat_inst_meth,		\
-  in_objc_selector_refs,				\
-  in_objc_symbols, in_objc_module_info,			\
-  in_objc_protocol, in_objc_string_object,		\
-  in_objc_class_names, in_objc_meth_var_names,		\
-  in_objc_meth_var_types, in_objc_cls_refs
-
-#undef	EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS			\
-SECTION_FUNCTION (const_section,		\
-		  in_const,			\
-		  ".const", 1, 0)		\
-SECTION_FUNCTION (cstring_section,		\
-		  in_cstring,			\
-		  ".cstring", 1, 0)		\
-SECTION_FUNCTION (literal4_section,		\
-		  in_literal4,			\
-		  ".literal4", 1, 0)		\
-SECTION_FUNCTION (literal8_section,		\
-		  in_literal8,			\
-		  ".literal8", 1, 0)		\
-SECTION_FUNCTION (constructor_section,		\
-		  in_constructor,		\
-		  ".constructor", 0, 0)		\
-SECTION_FUNCTION (destructor_section,		\
-		  in_destructor,		\
-		  ".destructor", 0, 0)		\
-SECTION_FUNCTION (objc_class_section,		\
-		  in_objc_class,		\
-		  ".objc_class", 0, 1)		\
-SECTION_FUNCTION (objc_meta_class_section,	\
-		  in_objc_meta_class,		\
-		  ".objc_meta_class", 0, 1)	\
-SECTION_FUNCTION (objc_category_section,	\
-		  in_objc_category,		\
-		".objc_category", 0, 1)		\
-SECTION_FUNCTION (objc_class_vars_section,	\
-		  in_objc_class_vars,		\
-		  ".objc_class_vars", 0, 1)	\
-SECTION_FUNCTION (objc_instance_vars_section,	\
-		  in_objc_instance_vars,	\
-		  ".objc_instance_vars", 0, 1)	\
-SECTION_FUNCTION (objc_cls_meth_section,	\
-		  in_objc_cls_meth,		\
-		  ".objc_cls_meth", 0, 1)	\
-SECTION_FUNCTION (objc_inst_meth_section,	\
-		  in_objc_inst_meth,		\
-		  ".objc_inst_meth", 0, 1)	\
-SECTION_FUNCTION (objc_cat_cls_meth_section,	\
-		  in_objc_cat_cls_meth,		\
-		  ".objc_cat_cls_meth", 0, 1)	\
-SECTION_FUNCTION (objc_cat_inst_meth_section,	\
-		  in_objc_cat_inst_meth,	\
-		  ".objc_cat_inst_meth", 0, 1)	\
-SECTION_FUNCTION (objc_selector_refs_section,	\
-		  in_objc_selector_refs,	\
-		  ".objc_message_refs", 0, 1)	\
-SECTION_FUNCTION (objc_symbols_section,		\
-		  in_objc_symbols,		\
-		  ".objc_symbols", 0, 1)	\
-SECTION_FUNCTION (objc_module_info_section,	\
-		  in_objc_module_info,		\
-		  ".objc_module_info", 0, 1)	\
-SECTION_FUNCTION (objc_protocol_section,	\
-		  in_objc_protocol,		\
-		  ".objc_protocol", 0, 1)	\
-SECTION_FUNCTION (objc_string_object_section,	\
-		  in_objc_string_object,	\
-		  ".objc_string_object", 0, 1)	\
-SECTION_FUNCTION (objc_class_names_section,	\
-		in_objc_class_names,		\
-		".objc_class_names", 0, 1)	\
-SECTION_FUNCTION (objc_meth_var_names_section,	\
-		in_objc_meth_var_names,		\
-		".objc_meth_var_names", 0, 1)	\
-SECTION_FUNCTION (objc_meth_var_types_section,	\
-		in_objc_meth_var_types,		\
-		".objc_meth_var_types", 0, 1)	\
-SECTION_FUNCTION (objc_cls_refs_section,	\
-		in_objc_cls_refs,		\
-		".objc_cls_refs", 0, 1)		\
-						\
-void						\
-objc_section_init ()				\
-{						\
-  static int been_here = 0;			\
-						\
-  if (been_here == 0)				\
-    {						\
-      been_here = 1;				\
-      objc_class_section ();			\
-      objc_meta_class_section ();		\
-      objc_cat_cls_meth_section ();		\
-      objc_cat_inst_meth_section ();		\
-      objc_cls_meth_section ();			\
-      objc_inst_meth_section ();		\
-      objc_selector_refs_section ();		\
-      objc_symbols_section ();			\
-      objc_category_section ();			\
-      objc_protocol_section ();			\
-      objc_class_vars_section ();		\
-      objc_instance_vars_section ();		\
-      objc_module_info_section ();		\
-      objc_string_object_section ();		\
-      objc_class_names_section ();		\
-      objc_meth_var_names_section ();		\
-      objc_meth_var_types_section ();		\
-      objc_cls_refs_section ();			\
-    }						\
-}
-
-#undef	READONLY_DATA_SECTION
-#define READONLY_DATA_SECTION const_section
-
-#undef	SELECT_SECTION
-#define SELECT_SECTION(exp,reloc)				\
-  do								\
-    {								\
-      if (TREE_CODE (exp) == STRING_CST)			\
-	{							\
-	  if (flag_writable_strings)				\
-	    data_section ();					\
-	  else if (TREE_STRING_LENGTH (exp) !=			\
-		   strlen (TREE_STRING_POINTER (exp)) + 1)	\
-	    readonly_data_section ();				\
-	  else							\
-	    cstring_section ();					\
-	}							\
-      else if (TREE_CODE (exp) == INTEGER_CST			\
-	       || TREE_CODE (exp) == REAL_CST)			\
-        {							\
-	  tree size = TYPE_SIZE (TREE_TYPE (exp));		\
-	  							\
-	  if (TREE_CODE (size) == INTEGER_CST &&		\
-	      TREE_INT_CST_LOW (size) == 4 &&			\
-	      TREE_INT_CST_HIGH (size) == 0)			\
-	    literal4_section ();				\
-	  else if (TREE_CODE (size) == INTEGER_CST &&		\
-	      TREE_INT_CST_LOW (size) == 8 &&			\
-	      TREE_INT_CST_HIGH (size) == 0)			\
-	    literal8_section ();				\
-	  else							\
-	    readonly_data_section ();				\
-	}							\
-      else if (TREE_CODE (exp) == CONSTRUCTOR				\
-	       && TREE_TYPE (exp)					\
-	       && TREE_CODE (TREE_TYPE (exp)) == RECORD_TYPE		\
-	       && TYPE_NAME (TREE_TYPE (exp))				\
-	       && TREE_CODE (TYPE_NAME (TREE_TYPE (exp))) == IDENTIFIER_NODE \
-	       && IDENTIFIER_POINTER (TYPE_NAME (TREE_TYPE (exp))))	\
-	{								\
-	  if (!strcmp (IDENTIFIER_POINTER (TYPE_NAME (TREE_TYPE (exp))), \
-			"NXConstantString"))				\
-	  objc_string_object_section ();				\
-	else if ((TREE_READONLY (exp) || TREE_CONSTANT (exp))		\
-		&& !TREE_SIDE_EFFECTS (exp))				\
-	  readonly_data_section ();					\
-	else								\
-	  data_section ();						\
-      }									\
-      else if (TREE_CODE (exp) == VAR_DECL &&				\
-	       DECL_NAME (exp) &&					\
-	       TREE_CODE (DECL_NAME (exp)) == IDENTIFIER_NODE &&	\
-	       IDENTIFIER_POINTER (DECL_NAME (exp)) &&			\
-	       !strncmp (IDENTIFIER_POINTER (DECL_NAME (exp)), "_OBJC_", 6)) \
-	{								\
-	  const char *name = IDENTIFIER_POINTER (DECL_NAME (exp));	\
-	  								\
-	  if (!strncmp (name, "_OBJC_CLASS_METHODS_", 20))		\
-	    objc_cls_meth_section ();					\
-	  else if (!strncmp (name, "_OBJC_INSTANCE_METHODS_", 23))	\
-	    objc_inst_meth_section ();					\
-	  else if (!strncmp (name, "_OBJC_CATEGORY_CLASS_METHODS_", 20)) \
-	    objc_cat_cls_meth_section ();				\
-	  else if (!strncmp (name, "_OBJC_CATEGORY_INSTANCE_METHODS_", 23)) \
-	    objc_cat_inst_meth_section ();				\
-	  else if (!strncmp (name, "_OBJC_CLASS_VARIABLES_", 22))	\
-	    objc_class_vars_section ();					\
-	  else if (!strncmp (name, "_OBJC_INSTANCE_VARIABLES_", 25))	\
-	    objc_instance_vars_section ();				\
-	  else if (!strncmp (name, "_OBJC_CLASS_PROTOCOLS_", 22))	\
-	    objc_cat_cls_meth_section ();				\
-	  else if (!strncmp (name, "_OBJC_CLASS_NAME_", 17))		\
-	    objc_class_names_section ();				\
-	  else if (!strncmp (name, "_OBJC_METH_VAR_NAME_", 20))		\
-	    objc_meth_var_names_section ();				\
-	  else if (!strncmp (name, "_OBJC_METH_VAR_TYPE_", 20))		\
-	    objc_meth_var_types_section ();				\
-	  else if (!strncmp (name, "_OBJC_CLASS_REFERENCES", 22))	\
-	    objc_cls_refs_section ();					\
-	  else if (!strncmp (name, "_OBJC_CLASS_", 12))			\
-	    objc_class_section ();					\
-	  else if (!strncmp (name, "_OBJC_METACLASS_", 16))		\
-	    objc_meta_class_section ();					\
-	  else if (!strncmp (name, "_OBJC_CATEGORY_", 15))		\
-	    objc_category_section ();					\
-	  else if (!strncmp (name, "_OBJC_SELECTOR_REFERENCES", 25))	\
-	    objc_selector_refs_section ();				\
-	  else if (!strncmp (name, "_OBJC_SYMBOLS", 13))		\
-	    objc_symbols_section ();					\
-	  else if (!strncmp (name, "_OBJC_MODULES", 13))		\
-	    objc_module_info_section ();				\
-	  else if (!strncmp (name, "_OBJC_PROTOCOL_INSTANCE_METHODS_", 32)) \
-	    objc_cat_inst_meth_section ();                              \
-	  else if (!strncmp (name, "_OBJC_PROTOCOL_CLASS_METHODS_", 29)) \
-	    objc_cat_cls_meth_section ();                               \
-	  else if (!strncmp (name, "_OBJC_PROTOCOL_REFS_", 20))         \
-	    objc_cat_cls_meth_section ();                               \
-	  else if (!strncmp (name, "_OBJC_PROTOCOL_", 15))              \
-	    objc_protocol_section ();                                   \
-	  else if ((TREE_READONLY (exp) || TREE_CONSTANT (exp))		\
-		&& !TREE_SIDE_EFFECTS (exp))     			\
-	    readonly_data_section ();                                   \
-	  else								\
-	    data_section ();						\
-	}								\
-      else if (TREE_CODE (exp) == VAR_DECL)				\
-	{								\
-	  if ((flag_pic && reloc)					\
-	      || !TREE_READONLY (exp) || TREE_SIDE_EFFECTS (exp)	\
-	      || !DECL_INITIAL (exp)					\
-	      || (DECL_INITIAL (exp) != error_mark_node			\
-		  && !TREE_CONSTANT (DECL_INITIAL (exp))))		\
-	    data_section ();						\
-	  else								\
-	    readonly_data_section ();					\
-	}								\
-      else								\
-	readonly_data_section ();					\
-    }									\
-  while (0)
-
-#undef	SELECT_RTX_SECTION
-#define SELECT_RTX_SECTION(mode, rtx)					\
-  do									\
-    {									\
-      if (GET_MODE_SIZE(mode) == 8)					\
-	literal8_section();						\
-      else if (GET_MODE_SIZE(mode) == 4)				\
-	literal4_section();						\
-      else								\
-	const_section ();						\
-    }									\
-  while (0)
-
-#ifdef ASM_COMMENT_START
-# undef ASM_COMMENT_START
-#endif
-
-#define ASM_COMMENT_START ";#"
diff --git a/gcc/config/nextstep21.h b/gcc/config/nextstep21.h
deleted file mode 100755
index 8009571..0000000
--- a/gcc/config/nextstep21.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* nextstep.h -- operating system specific defines to be used when
-   targeting GCC for NeXTSTEP.
-   Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* changed for NeXTStep 2.1, Ch. Kranz, 2/94, 3/94 */
-#include "nextstep.h"
-
-/* set flag_gnu_linker=0, use collect2 for linking */
-#undef USE_COLLECT2
-#define USE_COLLECT2
-
-/* use this until a newer gdb for NeXTStep21 is available */
-#define DEFAULT_GDB_EXTENSIONS 0
-
-/* we need the call to __main to start all global destructors and constructors
-   correctly, so undef INIT_SECTION_ASM_OP, (see libgcc2.c line 1965) 
-   and define INVOKE_main */
-#undef	INIT_SECTION_ASM_OP
-#define INVOKE__main
-
-/* We call the global destructors, constructors from __main */
-#undef	ASM_OUTPUT_CONSTRUCTOR
-#undef	ASM_OUTPUT_DESTRUCTOR
-
-#undef ASM_FILE_END
-#define ASM_FILE_END(FILE)					\
-  do {								\
-    extern char *language_string;				\
-      if (strcmp (language_string, "GNU C++") == 0)		\
-      {								\
-	ASM_OUTPUT_ALIGN (FILE, 1);				\
-      }								\
-  } while (0) 
-/* deleted: destructor_section ();				\ */
-/* deleted: constructor_section ();				\ */
-
-/* Ensure correct alignment of bss data.  */
-/* ASM_OUTPUT_ALIGNED_LOCAL not needed */
-/* need ASM_OUTPUT_LOCAL instead for old NeXT-as */
-/* look in varasm.c, line 1062 and 1476 */
-#undef	ASM_OUTPUT_ALIGNED_LOCAL
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
diff --git a/gcc/config/ns32k/encore.h b/gcc/config/ns32k/encore.h
deleted file mode 100755
index 31e2894..0000000
--- a/gcc/config/ns32k/encore.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* Definitions of target machine for GNU compiler.  ENCORE NS32000 version.
-   Copyright (C) 1988, 1993 Free Software Foundation, Inc.
-   Adapted by Robert Brown (brown@harvard.harvard.edu) from the Sequent
-   version by Michael Tiemann (tiemann@mcc.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#define EXTERNAL_PREFIX '?'
-#define IMMEDIATE_PREFIX '$'
-
-#include "ns32k/ns32k.h"
-
-#define SDB_DEBUGGING_INFO
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Cause long-jump assembler to be used,
-   since otherwise some files fail to be assembled right.  */
-#define ASM_SPEC "-j"
-
-#undef ASM_FILE_START
-#undef ASM_GENERATE_INTERNAL_LABEL
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#undef ASM_OUTPUT_ALIGN
-#undef ASM_OUTPUT_ASCII
-#undef ASM_OUTPUT_DOUBLE
-#undef ASM_OUTPUT_INT
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#undef ASM_OUTPUT_LOCAL
-#undef CPP_PREDEFINES
-#undef FUNCTION_BOUNDARY
-#undef PRINT_OPERAND
-#undef PRINT_OPERAND_ADDRESS
-#undef TARGET_VERSION
-#undef FUNCTION_PROFILER
-#undef ASM_OUTPUT_LABELREF_AS_INT
-
-#define TARGET_DEFAULT 9  /* 32332 with 32081.  */
-#define TARGET_VERSION fprintf (stderr, " (32000, Encore syntax)");
-/* Note Encore does not standardly do -Dencore.  */
-/* budd: should have a -ns32332 (or -apc) switch! but no harm for now */
-#define CPP_PREDEFINES "-Dns32000 -Dn16 -Dns16000 -Dns32332 -Dunix -Asystem(unix) -Acpu(ns32k) -Amachine(ns32k)"
-
-/* Ignore certain cpp directives used in header files on sysV.  */
-#define SCCS_DIRECTIVE
-
-/* Output #ident as a .ident.  */
-#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-
-/* The .file command should always begin the output.  */
-#define ASM_FILE_START(FILE) \
-output_file_directive ((FILE), main_input_filename)
-
-#define FUNCTION_BOUNDARY 128		/* speed optimization */
-
-/*
- *  The Encore assembler uses ".align 2" to align on 2-byte boundaries.
- */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)					\
-	fprintf (FILE, "\t.align %d\n", 1 << (LOG))
-
-/* The Encore assembler doesn't seem to accept the usual second argument
-   and warns that .align may not work in the text section if optimization
-   is on.  */
-#undef LABEL_ALIGN_AFTER_BARRIER
-#define LABEL_ALIGN_AFTER_BARRIER(LABEL) 0
-
-/*
- *  Internal labels are prefixed with a period.
- */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)			\
-	sprintf (LABEL, "*.%s%d", PREFIX, NUM)
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)			\
-	fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)		\
-	fprintf (FILE, "\t.double .L%d-.LI%d\n", VALUE, REL)
-
-/*
- *  Different syntax for integer constants, double constants, and
- *  uninitialized locals.
- */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)				\
-( fprintf (FILE, "\t.double "),					\
-  output_addr_const (FILE, (VALUE)),				\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_LABELREF_AS_INT(STREAM, NAME)			\
-do {									\
-  fprintf (STREAM, "\t.double\t");					\
-  ASM_OUTPUT_LABELREF (STREAM, NAME);					\
-  fprintf (STREAM, "\n");						\
-} while (0)
-
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)				\
- fprintf (FILE, "\t.long 0f%.20e\n", (VALUE))
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)		\
-( fputs ("\t.bss ", (FILE)),					\
-  assemble_name ((FILE), (NAME)),				\
-  fprintf ((FILE), ",%u,%u\n", (SIZE), (ROUNDED)))
-
- /*
-  *  Encore assembler can't handle huge string constants like the one in
-  *  gcc.c.  If the default routine in varasm.c were more conservative, this
-  *  code could be eliminated.  It starts a new .ascii directive every 40
-  *  characters.
-  */
-
-#define ASM_OUTPUT_ASCII(file, p, size)			\
-do {							\
-  int i;						\
-  for (i = 0; i < (size); i++)				\
-    {							\
-      register int c = (p)[i];				\
-      if ((i / 40) * 40 == i)				\
-      if (i == 0)					\
-        fprintf ((file), "\t.ascii \"");		\
-      else						\
-        fprintf ((file), "\"\n\t.ascii \"");		\
-      if (c == '\"' || c == '\\')			\
-        putc ('\\', (file));				\
-      if (c >= ' ' && c < 0177)				\
-        putc (c, (file));				\
-      else						\
-        {						\
-          fprintf ((file), "\\%o", c);			\
-          if (i < (size) - 1 				\
-              && (p)[i + 1] >= '0' && (p)[i + 1] <= '9')\
-          fprintf ((file), "\"\n\t.ascii \"");		\
-        }						\
-    }							\
-  fprintf ((file), "\"\n");				\
-} while (0)
-
-/* Modify syntax of jsr instructions.  */
-#define CALL_MEMREF_IMPLICIT
-
-#define NO_ABSOLUTE_PREFIX_IF_SYMBOLIC
-
-#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE)
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  print_operand_address(FILE, ADDR)
-
-/* Change the way in which data is allocated and initialized on the
-   encore so that both private and shared data are supported.  Shared data
-   that is initialized must be contained in the ".shrdata" section
-   of the program.  This is accomplished by defining the SHARED_SECTION_ASM_OP
-   macro.  Share data that is simply allocated, and not initialized must
-   be prefixed with the ".shrcomm" or ".shrbss" pseudo op, for common or
-   local data respectively.  This is accomplished by redefining the
-   ASM_OUTPUT_COMMON and ASM_OUTPUT_LOCAL macros. */
-    
-/* Assembler pseudo-op for shared data segment. */
-
-#define SHARED_SECTION_ASM_OP ".shrdata"
-
-/* This says how to output an assembler line
-   to define a shared common symbol. */
-
-#define ASM_OUTPUT_SHARED_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs (".shrcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%d\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a shared local symbol. */
-
-#define ASM_OUTPUT_SHARED_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\t.shrbss ", (FILE)),				\
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ",%d,%d\n", (SIZE), (ROUNDED)))
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   fprintf (FILE, "\taddr .LP%d,r0\n\tjsr mcount\n", (LABELNO))
-
-#define ENCORE_ASM
diff --git a/gcc/config/ns32k/genix.h b/gcc/config/ns32k/genix.h
deleted file mode 100755
index ac84cfc..0000000
--- a/gcc/config/ns32k/genix.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Genix ns32000 version.
-   Copyright (C) 1987, 1988, 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "ns32k/encore.h"
-
-/* We don't want the one Encore needs.  */
-#undef ASM_SPEC
-
-/* The following defines override ones in ns32k.h and prevent any attempts
-   to explicitly or implicitly make references to the SB register in the GCC
-   generated code.  It is necessary to avoid such references under Genix V.3.1
-   because this OS doesn't even save/restore the SB on context switches!  */
-
-#define IS_OK_REG_FOR_BASE_P(X)						\
-  ( (GET_CODE (X) == REG) && REG_OK_FOR_BASE_P (X) )
-
-#undef INDIRECTABLE_1_ADDRESS_P
-#define INDIRECTABLE_1_ADDRESS_P(X)					\
-  (CONSTANT_ADDRESS_NO_LABEL_P (X)					\
-   || IS_OK_REG_FOR_BASE_P (X)						\
-   || (GET_CODE (X) == PLUS						\
-       && IS_OK_REG_FOR_BASE_P (XEXP (X, 0))				\
-       && CONSTANT_ADDRESS_P (XEXP (X, 1))  )  )
-
-/* Note that for double indirects, only FP, SP, and SB are allowed
-   as the inner-most base register.  But we are avoiding use of SB.  */
-
-#undef MEM_REG
-#define MEM_REG(X)							\
-  ( (GET_CODE (X) == REG)						\
-  && ( (REGNO (X) == FRAME_POINTER_REGNUM)				\
-    || (REGNO (X) == STACK_POINTER_REGNUM) ) )
-
-#undef INDIRECTABLE_2_ADDRESS_P
-#define INDIRECTABLE_2_ADDRESS_P(X)					\
-  (GET_CODE (X) == MEM							\
-   && (((xfoo0 = XEXP (X, 0), MEM_REG (xfoo0))				\
-       || (GET_CODE (xfoo0) == PLUS					\
-	   && MEM_REG (XEXP (xfoo0, 0))					\
-	   && CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfoo0, 1))))		\
-       || CONSTANT_ADDRESS_NO_LABEL_P (xfoo0)))
-
-/* Go to ADDR if X is a valid address not using indexing.
-   (This much is the easy part.)  */
-#undef GO_IF_NONINDEXED_ADDRESS
-#define GO_IF_NONINDEXED_ADDRESS(X, ADDR)				\
-{ register rtx xfoob = (X);						\
-  if (GET_CODE (xfoob) == REG) goto ADDR;				\
-  if (INDIRECTABLE_1_ADDRESS_P(X)) goto ADDR;				\
-  if (CONSTANT_P(X)) goto ADDR;						\
-  if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR;				\
-  if (GET_CODE (X) == PLUS)						\
-    if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (X, 1)))			\
-      if (INDIRECTABLE_2_ADDRESS_P (XEXP (X, 0)))			\
-	goto ADDR;							\
-}
-
-/* A bug in the GNX 3.X assembler causes references to external symbols to
-   be mishandled if the symbol is also used as the name of a function-local
-   variable or as the name of a struct or union field.  The problem only
-   appears when you are also using the -g option so that SDB debugging
-   directives are also being produced by GCC.  In such cases, the assembler
-   gets the external entity confused with the local entity and addressing
-   havoc ensues.  The solution is to get GCC to produce .global directives
-   for all external entities which are actually referenced within the current
-   source file.  The following macro does this.  */
-
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)				\
-    ASM_GLOBALIZE_LABEL(FILE,NAME);
-
-/* Genix wants 0l instead of 0f.  */
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)				\
- fprintf (FILE, "\t.long 0l%.20e\n", (VALUE))
-
-/*  A bug in the GNX 3.X linker prevents symbol-table entries with a storage-
-    class field of C_EFCN (-1) from being accepted. */
-
-#ifdef PUT_SDB_EPILOGUE_END
-#undef PUT_SDB_EPILOGUE_END
-#endif
-#define PUT_SDB_EPILOGUE_END(NAME)
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (32000, National syntax)");
-
-/* Same as the encore definition except
-   * Different syntax for double constants.
-   * Don't output `?' before external regs.
-   * Output `(sb)' in certain indirect refs.  */
-
-#error this has not been updated since version 1.
-#error it is certainly wrong.
-
-#undef PRINT_OPERAND
-#define PRINT_OPERAND(FILE, X, CODE)					\
-{ if (CODE == '$') putc ('$', FILE);					\
-  else if (CODE == '?');						\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    {									\
-      rtx xfoo;								\
-      xfoo = XEXP (X, 0);						\
-      switch (GET_CODE (xfoo))						\
-	{								\
-	case MEM:							\
-	  if (GET_CODE (XEXP (xfoo, 0)) == REG)				\
-	    if (REGNO (XEXP (xfoo, 0)) == STACK_POINTER_REGNUM)		\
-	      fprintf (FILE, "0(0(sp))");				\
-	    else fprintf (FILE, "0(0(%s))",				\
-			  reg_names[REGNO (XEXP (xfoo, 0))]);		\
-	  else								\
-	    {								\
-	      extern int paren_base_reg_printed;			\
-	      fprintf (FILE, "0(");					\
-	      paren_base_reg_printed = 0;				\
-	      output_address (xfoo);					\
-	      if (!paren_base_reg_printed)				\
-		fprintf (FILE, "(sb)");					\
-	      putc (')', FILE);						\
-	    }								\
-	  break;							\
-	case REG:							\
-	  fprintf (FILE, "0(%s)", reg_names[REGNO (xfoo)]);		\
-	  break;							\
-	case PRE_DEC:							\
-	case POST_INC:							\
-	  fprintf (FILE, "tos");					\
-	  break;							\
-	case CONST_INT:							\
-	  fprintf (FILE, "@%d", INTVAL (xfoo));				\
-	  break;							\
-	default:							\
-	  output_address (xfoo);					\
-	  break;							\
-	}								\
-    }									\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)	\
-    if (GET_MODE (X) == DFmode)						\
-      { union { double d; int i[2]; } u;				\
-        u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
-	fprintf (FILE, "$0l%.20e", u.d); }				\
-    else { union { double d; int i[2]; } u;				\
-	   u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
-	   fprintf (FILE, "$0f%.20e", u.d); }				\
-  else if (GET_CODE (X) == CONST)					\
-    output_addr_const (FILE, X);					\
-  else { putc ('$', FILE); output_addr_const (FILE, X); }}
diff --git a/gcc/config/ns32k/merlin.h b/gcc/config/ns32k/merlin.h
deleted file mode 100755
index d385395..0000000
--- a/gcc/config/ns32k/merlin.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/* Definitions of target machine for GNU compiler.  MERLIN NS32000 version.
-   Copyright (C) 1990, 1994 Free Software Foundation, Inc.
-   By Mark Mason (mason@reed.bitnet, pyramid!unify!mason@uunet.uu.net).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Two flags to control how addresses are printed in assembler insns.  */
-
-#define SEQUENT_ADDRESS_BUG 1
-#define SEQUENT_BASE_REGS
-
-#include "ns32k/ns32k.h"
-
-/* This is BSD, so it wants DBX format.  */
-#define DBX_DEBUGGING_INFO
-
-/* Sequent has some changes in the format of DBX symbols.  */
-#define DBX_NO_XREFS 1
-
-/* Don't split DBX symbols into continuations.  */
-#define DBX_CONTIN_LENGTH 0
-
-#define TARGET_DEFAULT 1
-
-/* Print subsidiary information on the compiler version in use.  */
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (32000, UTek syntax)");
-
-/* These control the C++ compiler somehow.  */
-#define FASCIST_ASSEMBLER
-#define USE_COLLECT
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-	"-Dns32000 -Dns32k -Dns16000 -Dmerlin -Dunix -DUtek -Dbsd \
-	-Asystem(unix) -Asystem(bsd) -Acpu(ns32k) -Amachine(ns32k)"
-
-/* This is how to align the code that follows an unconditional branch.
-   Don't define it, since it confuses the assembler (we hear).  */
-
-#undef LABEL_ALIGN_AFTER_BARRIER
-
-/* Assembler pseudo-op for shared data segment. */
-#define SHARED_SECTION_ASM_OP ".shdata"
-
-/* %$ means print the prefix for an immediate operand. */
-
-#ifdef UTEK_ASM
-#undef PRINT_OPERAND
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ if (CODE == '$') putc('$', FILE);					\
-  else if (CODE == '?');						\
-  else if (GET_CODE (X) == CONST_INT)					\
-    fprintf(FILE, "$%d", INTVAL(X));					\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    {									\
-      rtx xfoo;								\
-      xfoo = XEXP (X, 0);						\
-      switch (GET_CODE (xfoo))						\
-	{								\
-	case MEM:							\
-	  if (GET_CODE (XEXP (xfoo, 0)) == REG)				\
-	    if (REGNO (XEXP (xfoo, 0)) == STACK_POINTER_REGNUM)		\
-	      fprintf (FILE, "0(0(sp))");				\
-	    else fprintf (FILE, "0(0(%s))",				\
-			  reg_names[REGNO (XEXP (xfoo, 0))]);		\
-	  else								\
-	    {								\
-	      if (GET_CODE (XEXP (xfoo, 0)) == SYMBOL_REF		\
-		  || GET_CODE (XEXP (xfoo, 0)) == CONST)		\
-	        {							\
-		  fprintf(FILE, "0(");					\
-		  output_address(xfoo);					\
-		  fprintf(FILE, "(sb))");				\
-		}							\
-	      else							\
-	        {							\
-		  fprintf (FILE, "0(");					\
-		  output_address (xfoo);				\
-		  putc (')', FILE);					\
-		}							\
-	    }								\
-	  break;							\
-	case REG:							\
-	  fprintf (FILE, "0(%s)", reg_names[REGNO (xfoo)]);		\
-	  break;							\
-	case PRE_DEC:							\
-	case POST_INC:							\
-	  fprintf (FILE, "tos");					\
-	  break;							\
-	case CONST_INT:							\
-	  fprintf (FILE, "$%d", INTVAL (xfoo));				\
-	  break;							\
-	default:							\
-	  output_address (xfoo);					\
-	  break;							\
-	}								\
-    }									\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)	\
-    if (GET_MODE (X) == DFmode)						\
-      { union { double d; int i[2]; } u;				\
-	u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
-	fprintf (FILE, "$0d%.20e", u.d); }				\
-    else { union { double d; int i[2]; } u;				\
-	   u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
-	   fprintf (FILE, "$0f%.20e", u.d); }				\
-  else output_addr_const (FILE, X); }
-
-#undef  FUNCTION_PROLOGUE
-
-/* This differs from the one in ns32k.h in printing a bitmask
-   rather than a register list in the enter or save instruction.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)     \
-{ register int regno, g_regs_used = 0;				\
-  int used_regs_buf[8], *bufp = used_regs_buf;			\
-  int used_fregs_buf[8], *fbufp = used_fregs_buf;		\
-  extern char call_used_regs[];					\
-  MAIN_FUNCTION_PROLOGUE;					\
-  for (regno = 0; regno < 8; regno++)				\
-    if (regs_ever_live[regno]					\
-	&& ! call_used_regs[regno])				\
-    {								\
-      *bufp++ = regno; g_regs_used++;				\
-    }								\
-  *bufp = -1;							\
-  for (; regno < 16; regno++)					\
-    if (regs_ever_live[regno] && !call_used_regs[regno]) {	\
-      *fbufp++ = regno;						\
-    }								\
-  *fbufp = -1;							\
-  bufp = used_regs_buf;						\
-  if (frame_pointer_needed)					\
-    fprintf (FILE, "\tenter ");					\
-  else if (g_regs_used)						\
-    fprintf (FILE, "\tsave ");					\
-  if (frame_pointer_needed || g_regs_used)			\
-    {								\
-      char mask = 0;						\
-      while (*bufp >= 0)					\
-	mask |= 1 << *bufp++;					\
-      fprintf (FILE, "$0x%x", (int) mask & 0xff);		\
-    }								\
-  if (frame_pointer_needed)					\
-    fprintf (FILE, ",%d\n", SIZE);				\
-  else if (g_regs_used)						\
-    fprintf (FILE, "\n");					\
-  fbufp = used_fregs_buf;					\
-  while (*fbufp >= 0)						\
-    {								\
-      if ((*fbufp & 1) || (fbufp[0] != fbufp[1] - 1))		\
-	fprintf (FILE, "\tmovf f%d,tos\n", *fbufp++ - 8);	\
-      else							\
-	{							\
-	  fprintf (FILE, "\tmovl f%d,tos\n", fbufp[0] - 8);	\
-	  fbufp += 2;						\
-	}							\
-    }								\
-}
-
-#undef  FUNCTION_EPILOGUE
-
-/* This differs from the one in ns32k.h in printing a bitmask
-   rather than a register list in the exit or restore instruction.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-{ register int regno, g_regs_used = 0, f_regs_used = 0;		\
-  int used_regs_buf[8], *bufp = used_regs_buf;			\
-  int used_fregs_buf[8], *fbufp = used_fregs_buf;		\
-  extern char call_used_regs[];					\
-  *fbufp++ = -2;						\
-  for (regno = 8; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && !call_used_regs[regno]) {	\
-       *fbufp++ = regno; f_regs_used++;				\
-    }								\
-  fbufp--;							\
-  for (regno = 0; regno < 8; regno++)				\
-    if (regs_ever_live[regno]					\
-	&& ! call_used_regs[regno])				\
-    {                                                         	\
-      *bufp++ = regno; g_regs_used++;				\
-    }                                                         	\
-  while (fbufp > used_fregs_buf)				\
-    {								\
-      if ((*fbufp & 1) && fbufp[0] == fbufp[-1] + 1)		\
-	{							\
-	  fprintf (FILE, "\tmovl tos,f%d\n", fbufp[-1] - 8);	\
-	  fbufp -= 2;						\
-	}							\
-      else fprintf (FILE, "\tmovf tos,f%d\n", *fbufp-- - 8);	\
-    }								\
-  if (frame_pointer_needed)					\
-    fprintf (FILE, "\texit ");					\
-  else if (g_regs_used)						\
-    fprintf (FILE, "\trestore ");				\
-  if (g_regs_used || frame_pointer_needed)			\
-    {								\
-      char mask = 0;						\
-								\
-      while (bufp > used_regs_buf)				\
-	{							\
-	  /* Utek assembler takes care of reversing this */	\
-	  mask |= 1 << *--bufp;					\
-	}							\
-      fprintf (FILE, "$0x%x\n", (int) mask & 0xff);		\
-    }								\
-  if (current_function_pops_args)				\
-    fprintf (FILE, "\tret %d\n", current_function_pops_args);	\
-  else fprintf (FILE, "\tret 0\n"); }
-
-#endif /* UTEK_ASM */
-
-#undef PRINT_OPERAND_ADDRESS
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  print_operand_address(FILE, ADDR)
diff --git a/gcc/config/ns32k/netbsd.h b/gcc/config/ns32k/netbsd.h
deleted file mode 100755
index bc86e31..0000000
--- a/gcc/config/ns32k/netbsd.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Configuration for a ns32532 running NetBSD as the target machine.
-   Copyright (C) 1988, 1994, 1995, 1996, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.
-
-*/
-
-#include <ns32k/ns32k.h>
-
-/* Compile for the floating point unit & 32532 by default;
-   Don't assume SB is zero;
-   Don't use bitfield instructions;
-   FPU is 32381; */
-
-#define TARGET_DEFAULT (1 + 24 + 32 + 64 + 256)
-
-/* 32-bit alignment for efficiency */
-
-#undef POINTER_BOUNDARY
-#define POINTER_BOUNDARY 32
-
-/* 32-bit alignment for efficiency */
-
-#undef FUNCTION_BOUNDARY
-#define FUNCTION_BOUNDARY 32
-
-/* 32532 spec says it can handle any alignment.  Rumor from tm-ns32k.h
-   tells this might not be actually true (but it's for 32032, perhaps
-   National has fixed the bug for 32532).  You might have to change this
-   if the bug still exists. */
-
-#undef STRICT_ALIGNMENT
-#define STRICT_ALIGNMENT 0
-
-/* Use pc relative addressing whenever possible,
-   it's more efficient than absolute (ns32k.c)
-   You have to fix a bug in gas 1.38.1 to make this work with gas,
-   patch available from jkp@cs.hut.fi.
-   (NetBSD's gas version has this patch already applied) */
-
-#define PC_RELATIVE
-
-/* Operand of bsr or jsr should be just the address.  */
-
-#define CALL_MEMREF_IMPLICIT
-
-/* movd insns may have floating point constant operands.  */
-
-#define MOVD_FLOAT_OK
-
-/* Get generic NetBSD definitions. */
-#include <netbsd.h>
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dns32k -Dns32000 -Dns32532 -D__NetBSD__ -Dpc532 -D__ns32k__ -D__KPRINTF_ATTRIBUTE__ -Asystem(unix) -Asystem(NetBSD) -Acpu(ns32k) -Amachine(ns32k)"
-
-/* Make gcc agree with <machine/ansi.h> */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE	"int"
-
-#undef WCHAR_UNSIGNED
-#define WCHAR_UNSIGNED	0
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE	32
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Do not break .stabs pseudos into continuations.  */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* This is the char to use for continuation (in case we need to turn
-   continuation back on).  */
-
-#define DBX_CONTIN_CHAR '?'
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-
-#undef PCC_STATIC_STRUCT_RETURN
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Until they use ELF or something that handles dwarf2 unwinds
-   and initialization stuff better.  */
-#define DWARF2_UNWIND_INFO 0
-
diff --git a/gcc/config/ns32k/ns32k.c b/gcc/config/ns32k/ns32k.c
deleted file mode 100755
index af89e59..0000000
--- a/gcc/config/ns32k/ns32k.c
+++ /dev/null
@@ -1,1196 +0,0 @@
-/* Subroutines for assembler code output on the NS32000.
-   Copyright (C) 1988, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Some output-actions in ns32k.md need these.  */
-#include "config.h"
-#include "system.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "tree.h"
-#include "expr.h"
-#include "flags.h"
-
-#ifdef OSF_OS
-int ns32k_num_files = 0;
-#endif
-
-/* This duplicates reg_class_contens in reg_class.c, but maybe that isn't
-   initialized in time. Also this is more convenient as an array of ints.
-   We know that HARD_REG_SET fits in an unsigned int */
-
-unsigned int ns32k_reg_class_contents[N_REG_CLASSES] = REG_CLASS_CONTENTS;
-
-enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
-{
-  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
-  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
-  FLOAT_REG0, LONG_FLOAT_REG0, FLOAT_REGS, FLOAT_REGS,
-  FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
-  FP_REGS, FP_REGS, FP_REGS, FP_REGS,
-  FP_REGS, FP_REGS, FP_REGS, FP_REGS,
-  FRAME_POINTER_REG, STACK_POINTER_REG
-};
-
-char *ns32k_out_reg_names[] = OUTPUT_REGISTER_NAMES;
-
-void
-trace (s, s1, s2)
-     char *s, *s1, *s2;
-{
-  fprintf (stderr, s, s1, s2);
-}
-
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 
-int
-hard_regno_mode_ok (regno, mode)
-     int regno;
-     enum machine_mode mode;
-{
-  int size = GET_MODE_UNIT_SIZE(mode);
-
-  if (FLOAT_MODE_P(mode))
-    {
-      if (size == UNITS_PER_WORD && regno < L1_REGNUM)
-	return 1;
-      if (size == UNITS_PER_WORD * 2
-	  && (((regno & 1) == 0 && regno < FRAME_POINTER_REGNUM)))
-	return 1;
-      return 0;
-    }
-  if (size == UNITS_PER_WORD * 2
-      && (regno & 1) == 0 && regno < F0_REGNUM)
-    return 1;
-  if (size <= UNITS_PER_WORD
-      && (regno < F0_REGNUM || regno == FRAME_POINTER_REGNUM
-	  || regno == STACK_POINTER_REGNUM))
-    return 1;
-  return 0;
-}
-
-int register_move_cost(CLASS1, CLASS2)
-     enum reg_class CLASS1;
-     enum reg_class CLASS2;
-{
-  if (CLASS1 == NO_REGS || CLASS2 == NO_REGS)
-    return 2;
-  if((SUBSET_P(CLASS1, FP_REGS) && !SUBSET_P(CLASS2, FP_REGS))
-   || (!SUBSET_P(CLASS1, FP_REGS) && SUBSET_P(CLASS2, FP_REGS)))
-    return 8;
-  if (((CLASS1) == STACK_POINTER_REG && !SUBSET_P(CLASS2,GENERAL_REGS))
-      || ((CLASS2) == STACK_POINTER_REG && !SUBSET_P(CLASS1,GENERAL_REGS)))
-    return 6;
-  if (((CLASS1) == FRAME_POINTER_REG && !SUBSET_P(CLASS2,GENERAL_REGS))
-      || ((CLASS2) == FRAME_POINTER_REG && !SUBSET_P(CLASS1,GENERAL_REGS)))
-    return 6;
-  return 2;
-}
-
-#if 0
-/* We made the insn definitions copy from floating point to general
-  registers via the stack. */
-int secondary_memory_needed(CLASS1, CLASS2, M)
-     enum reg_class CLASS1;
-     enum reg_class CLASS2;
-     enum machine_mode M;
-{
-  int ret = ((SUBSET_P(CLASS1, FP_REGS) && !SUBSET_P(CLASS2, FP_REGS))
-   || (!SUBSET_P(CLASS1, FP_REGS) && SUBSET_P(CLASS2, FP_REGS)));
-  return ret;
-}
-#endif
-    
-
-/* ADDRESS_COST calls this.  This function is not optimal
-   for the 32032 & 32332, but it probably is better than
-   the default. */
-
-int
-calc_address_cost (operand)
-     rtx operand;
-{
-  int i;
-  int cost = 0;
-  
-  if (GET_CODE (operand) == MEM)
-    cost += 3;
-  if (GET_CODE (operand) == MULT)
-    cost += 2;
-#if 0
-  if (GET_CODE (operand) == REG)
-    cost += 1;			/* not really, but the documentation
-				   says different amount of registers
-				   shouldn't return the same costs */
-#endif
-  switch (GET_CODE (operand))
-    {
-    case REG:
-    case CONST:
-    case CONST_INT:
-    case CONST_DOUBLE:
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case POST_DEC:
-    case PRE_DEC:
-      break;
-    case MEM:
-      cost += calc_address_cost (XEXP (operand, 0));
-      break;
-    case MULT:
-    case PLUS:
-      for (i = 0; i < GET_RTX_LENGTH (GET_CODE (operand)); i++)
-	{
-	  cost += calc_address_cost (XEXP (operand, i));
-	}
-    default:
-      break;
-    }
-  return cost;
-}
-
-/* Return the register class of a scratch register needed to copy IN into
-   or out of a register in CLASS in MODE.  If it can be done directly,
-   NO_REGS is returned.  */
-
-enum reg_class
-secondary_reload_class (class, mode, in)
-     enum reg_class class;
-     enum machine_mode mode;
-     rtx in;
-{
-  int regno = true_regnum (in);
-
-  if (regno >= FIRST_PSEUDO_REGISTER)
-    regno = -1;
-
-  if ((class == FRAME_POINTER_REG && regno == STACK_POINTER_REGNUM)
-      || ( class == STACK_POINTER_REG && regno == FRAME_POINTER_REGNUM))
-    return GENERAL_REGS;
-  else
-    return NO_REGS;
-}
-
-/* Generate the rtx that comes from an address expression in the md file */
-/* The expression to be build is BASE[INDEX:SCALE].  To recognize this,
-   scale must be converted from an exponent (from ASHIFT) to a
-   multiplier (for MULT). */
-static rtx
-gen_indexed_expr (base, index, scale)
-     rtx base, index, scale;
-{
-  rtx addr;
-
-  /* This generates an invalid addressing mode, if BASE is
-     fp or sp.  This is handled by PRINT_OPERAND_ADDRESS.  */
-  if (GET_CODE (base) != REG && GET_CODE (base) != CONST_INT)
-    base = gen_rtx (MEM, SImode, base);
-  addr = gen_rtx (MULT, SImode, index,
-		  GEN_INT (1 << INTVAL (scale)));
-  addr = gen_rtx (PLUS, SImode, base, addr);
-  return addr;
-}
-
-/* Return 1 if OP is a valid operand of mode MODE.  This
-   predicate rejects operands which do not have a mode
-   (such as CONST_INT which are VOIDmode).  */
-int
-reg_or_mem_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return (GET_MODE (op) == mode
-	  && (GET_CODE (op) == REG
-	      || GET_CODE (op) == SUBREG
-	      || GET_CODE (op) == MEM));
-}
-
-
-/* Split one or more DImode RTL references into pairs of SImode
-   references.  The RTL can be REG, offsettable MEM, integer constant, or
-   CONST_DOUBLE.  "operands" is a pointer to an array of DImode RTL to
-   split and "num" is its length.  lo_half and hi_half are output arrays
-   that parallel "operands". */
-
-void
-split_di (operands, num, lo_half, hi_half)
-     rtx operands[];
-     int num;
-     rtx lo_half[], hi_half[];
-{
-  while (num--)
-    {
-      if (GET_CODE (operands[num]) == REG)
-	{
-	  lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]));
-	  hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1);
-	}
-      else if (CONSTANT_P (operands[num]))
-	{
-	  split_double (operands[num], &lo_half[num], &hi_half[num]);
-	}
-      else if (offsettable_memref_p (operands[num]))
-	{
-	  lo_half[num] = operands[num];
-	  hi_half[num] = adj_offsettable_operand (operands[num], 4);
-	}
-      else
-	abort();
-    }
-}
-
-/* Return the best assembler insn template
-   for moving operands[1] into operands[0] as a fullword.  */
-
-static char *
-singlemove_string (operands)
-     rtx *operands;
-{
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL (operands[1]) <= 7
-      && INTVAL (operands[1]) >= -8)
-    return "movqd %1,%0";
-  return "movd %1,%0";
-}
-
-char *
-output_move_double (operands)
-     rtx *operands;
-{
-  enum anon1 { REGOP, OFFSOP, PUSHOP, CNSTOP, RNDOP } optype0, optype1;
-  rtx latehalf[2];
-
-  /* First classify both operands.  */
-
-  if (REG_P (operands[0]))
-    optype0 = REGOP;
-  else if (offsettable_memref_p (operands[0]))
-    optype0 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    optype0 = PUSHOP;
-  else
-    optype0 = RNDOP;
-
-  if (REG_P (operands[1]))
-    optype1 = REGOP;
-  else if (CONSTANT_P (operands[1])
-	   || GET_CODE (operands[1]) == CONST_DOUBLE)
-    optype1 = CNSTOP;
-  else if (offsettable_memref_p (operands[1]))
-    optype1 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
-    optype1 = PUSHOP;
-  else
-    optype1 = RNDOP;
-
-  /* Check for the cases that the operand constraints are not
-     supposed to allow to happen.  Abort if we get one,
-     because generating code for these cases is painful.  */
-
-  if (optype0 == RNDOP || optype1 == RNDOP)
-    abort ();
-
-  /* Ok, we can do one word at a time.
-     Normally we do the low-numbered word first,
-     but if either operand is autodecrementing then we
-     do the high-numbered word first.
-
-     In either case, set up in LATEHALF the operands to use
-     for the high-numbered word and in some cases alter the
-     operands in OPERANDS to be suitable for the low-numbered word.  */
-
-  if (optype0 == REGOP)
-    latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  else if (optype0 == OFFSOP)
-    latehalf[0] = adj_offsettable_operand (operands[0], 4);
-  else
-    latehalf[0] = operands[0];
-
-  if (optype1 == REGOP)
-    latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-  else if (optype1 == OFFSOP)
-    latehalf[1] = adj_offsettable_operand (operands[1], 4);
-  else if (optype1 == CNSTOP)
-    split_double (operands[1], &operands[1], &latehalf[1]);
-  else
-    latehalf[1] = operands[1];
-
-  /* If insn is effectively movd N(sp),tos then we will do the
-     high word first.  We should use the adjusted operand 1 (which is N+4(sp))
-     for the low word as well, to compensate for the first decrement of sp.
-     Given this, it doesn't matter which half we do "first".  */
-  if (optype0 == PUSHOP
-      && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
-      && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
-    operands[1] = latehalf[1];
-
-  /* If one or both operands autodecrementing,
-     do the two words, high-numbered first.  */
-  else if (optype0 == PUSHOP || optype1 == PUSHOP)
-    {
-      output_asm_insn (singlemove_string (latehalf), latehalf);
-      return singlemove_string (operands);
-    }
-
-  /* If the first move would clobber the source of the second one,
-     do them in the other order.  */
-
-  /* Overlapping registers.  */
-  if (optype0 == REGOP && optype1 == REGOP
-      && REGNO (operands[0]) == REGNO (latehalf[1]))
-    {
-      /* Do that word.  */
-      output_asm_insn (singlemove_string (latehalf), latehalf);
-      /* Do low-numbered word.  */
-      return singlemove_string (operands);
-    }
-  /* Loading into a register which overlaps a register used in the address.  */
-  else if (optype0 == REGOP && optype1 != REGOP
-	   && reg_overlap_mentioned_p (operands[0], operands[1]))
-    {
-      if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
-	  && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
-	{
-	  /* If both halves of dest are used in the src memory address,
-	     load the destination address into the low reg (operands[0]).
-	     Then it works to load latehalf first.  */
-	  rtx xops[2];
-	  xops[0] = XEXP (operands[1], 0);
-	  xops[1] = operands[0];
-	  output_asm_insn ("addr %a0,%1", xops);
-	  operands[1] = gen_rtx (MEM, DImode, operands[0]);
-	  latehalf[1] = adj_offsettable_operand (operands[1], 4);
-	  /* The first half has the overlap, Do the late half first.  */
-	  output_asm_insn (singlemove_string (latehalf), latehalf);
-	  /* Then clobber.  */
-	  return singlemove_string (operands);
-	}
-      if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
-	{
-	  /* The first half has the overlap, Do the late half first.  */
-	  output_asm_insn (singlemove_string (latehalf), latehalf);
-	  /* Then clobber.  */
-	  return singlemove_string (operands);
-	}
-    }
-
-  /* Normal case.  Do the two words, low-numbered first.  */
-
-  output_asm_insn (singlemove_string (operands), operands);
-
-  operands[0] = latehalf[0];
-  operands[1] = latehalf[1];
-  return singlemove_string (operands);
-}
-
-
-#define MAX_UNALIGNED_COPY (32)
-/* Expand string/block move operations.
-
-   operands[0] is the pointer to the destination.
-   operands[1] is the pointer to the source.
-   operands[2] is the number of bytes to move.
-   operands[3] is the alignment.  */
-
-static void
-move_tail(operands, bytes, offset)
-     rtx operands[];
-     int bytes;
-     int offset;
-{
-  if (bytes & 2)
-    {
-      rtx src, dest;
-      dest = change_address(operands[0], HImode,
-			    plus_constant(XEXP(operands[0], 0), offset));
-      src = change_address(operands[1], HImode,
-			   plus_constant(XEXP(operands[1], 0), offset));
-      emit_move_insn(dest, src);
-      offset += 2;
-    }
-  if (bytes & 1)
-    {
-      rtx src, dest;
-      dest = change_address(operands[0], QImode,
-			    plus_constant(XEXP(operands[0], 0), offset));
-      src = change_address(operands[1], QImode,
-			   plus_constant(XEXP(operands[1], 0), offset));
-      emit_move_insn(dest, src);
-    }
-}
-
-void
-expand_block_move (operands)
-     rtx operands[];
-{
-  rtx bytes_rtx	= operands[2];
-  rtx align_rtx = operands[3];
-  int constp	= (GET_CODE (bytes_rtx) == CONST_INT);
-  int bytes	= (constp ? INTVAL (bytes_rtx) : 0);
-  int align	= INTVAL (align_rtx);
-  rtx src_reg = gen_rtx(REG, Pmode, 1);
-  rtx dest_reg = gen_rtx(REG, Pmode, 2);
-  rtx count_reg = gen_rtx(REG, SImode, 0);
-  rtx insn;
-
-  if (constp && bytes <= 0)
-    return;
-
-  if (constp && bytes < 20)
-    {
-      int words = bytes >> 2;
-      if (words)
-	if (words < 3 || flag_unroll_loops)
-	  {
-	    int offset = 0;
-	    for (; words; words--, offset += 4)
-	      {
-		rtx src, dest;
-		dest = change_address(operands[0], SImode,
-				      plus_constant(XEXP(operands[0], 0), offset));
-		src = change_address(operands[1], SImode,
-				     plus_constant(XEXP(operands[1], 0), offset));
-		emit_move_insn(dest, src);
-	      }
-	  }
-	else
-	  {
-	    /* Use movmd. It is slower than multiple movd's but more
-	       compact. It is also slower than movsd for large copies
-	       but causes less registers reloading so is better than movsd
-	       for small copies. */
-	    rtx src, dest;
-	    dest = copy_addr_to_reg (XEXP(operands[0], 0));
-	    src = copy_addr_to_reg (XEXP(operands[1], 0));
-	    
-	    emit_insn(gen_movstrsi2(dest, src, GEN_INT(words)));
-	  }
-      move_tail(operands, bytes & 3, bytes & ~3);
-      return;
-    }
-
-  if (align > UNITS_PER_WORD)
-    align = UNITS_PER_WORD;
-
-  /* Move the address into scratch registers.  */
-  emit_insn(gen_rtx(CLOBBER, VOIDmode, dest_reg));
-  emit_move_insn(dest_reg, XEXP (operands[0], 0));
-  emit_insn(gen_rtx(CLOBBER, VOIDmode, src_reg));
-  emit_move_insn(src_reg, XEXP (operands[1], 0));
-  emit_insn(gen_rtx(CLOBBER, VOIDmode, count_reg));
-
-  if (constp && (align == UNITS_PER_WORD || bytes < MAX_UNALIGNED_COPY))
-    {
-      rtx  bytes_reg;
-
-      /* constant no of bytes and aligned or small enough copy to not bother
-       * aligning. Emit insns to copy by words.
-       */
-      if (bytes >> 2)
-	{
-	  emit_move_insn(count_reg, GEN_INT(bytes >> 2));
-	  emit_insn(gen_movstrsi1 (GEN_INT(4)));
-	}
-      /* insns to copy rest */
-      move_tail(operands, bytes & 3, bytes & ~3);
-    }
-  else if (align == UNITS_PER_WORD)
-    {
-      /* insns to copy by words */
-      emit_insn(gen_lshrsi3 (count_reg, bytes_rtx, GEN_INT(2)));
-      emit_insn(gen_movstrsi1 (GEN_INT(4)));
-      /* insns to copy rest */
-      emit_insn(gen_andsi3 (count_reg, bytes_rtx, GEN_INT(3)));
-      emit_insn(gen_movstrsi1 (const1_rtx));
-    }
-  else
-    {
-      /* Not aligned and we may have a lot to copy so it is worth
-       * aligning.
-       */
-      rtx aligned_label = gen_label_rtx ();
-      rtx bytes_reg;
-
-      bytes_reg = copy_to_mode_reg(SImode, bytes_rtx);
-      if (!constp)
-	{
-	  /* Emit insns to test and skip over the alignment if it is
-	   * not worth it. This doubles as a test to ensure that the alignment
-	   * operation can't copy too many bytes
-	   */
-	  emit_insn(gen_cmpsi (bytes_reg, GEN_INT(MAX_UNALIGNED_COPY)));
-	  emit_jump_insn (gen_blt (aligned_label));
-	}
-
-      /* Emit insns to do alignment at run time */
-      emit_insn(gen_negsi2 (count_reg, src_reg));
-      emit_insn(gen_andsi3 (count_reg, count_reg, GEN_INT(3)));
-      emit_insn(gen_subsi3 (bytes_reg, bytes_reg, count_reg));
-      emit_insn(gen_movstrsi1 (const1_rtx));
-      if (!constp)
-	emit_label (aligned_label);
-
-      /* insns to copy by words */
-      emit_insn (gen_lshrsi3 (count_reg, bytes_reg, GEN_INT(2)));
-      emit_insn(gen_movstrsi1 (GEN_INT(4)));
-
-      /* insns to copy rest */
-      emit_insn (gen_andsi3 (count_reg, bytes_reg, GEN_INT(3)));
-      emit_insn(gen_movstrsi1 (const1_rtx));    
-    }
-}
-
-
-/* Returns 1 if OP contains a global symbol reference */
-
-int
-global_symbolic_reference_mentioned_p (op, f)
-     rtx op;
-     int f;
-{
-  register char *fmt;
-  register int i;
-
-  if (GET_CODE (op) == SYMBOL_REF)
-    {
-      if (! SYMBOL_REF_FLAG (op))
-	return 1;
-      else
-        return 0;
-    }
-  else if (f && GET_CODE (op) != CONST)
-    return 0;
-
-  fmt = GET_RTX_FORMAT (GET_CODE (op));
-  for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
-    {
-      if (fmt[i] == 'E')
-	{
-	  register int j;
-
-	  for (j = XVECLEN (op, i) - 1; j >= 0; j--)
-	    if (global_symbolic_reference_mentioned_p (XVECEXP (op, i, j), 0))
-	      return 1;
-	}
-      else if (fmt[i] == 'e' 
-	       && global_symbolic_reference_mentioned_p (XEXP (op, i), 0))
-	return 1;
-    }
-
-  return 0;
-}
-
-
-/* Returns 1 if OP contains a symbol reference */
-
-int
-symbolic_reference_mentioned_p (op)
-     rtx op;
-{
-  register char *fmt;
-  register int i;
-
-  if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
-    return 1;
-
-  fmt = GET_RTX_FORMAT (GET_CODE (op));
-  for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
-    {
-      if (fmt[i] == 'E')
-	{
-	  register int j;
-
-	  for (j = XVECLEN (op, i) - 1; j >= 0; j--)
-	    if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
-	      return 1;
-	}
-      else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
-	return 1;
-    }
-
-  return 0;
-}
-
-/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
-   attribute for DECL.  The attributes in ATTRIBUTES have previously been
-   assigned to DECL.  */
-
-int
-ns32k_valid_decl_attribute_p (decl, attributes, identifier, args)
-     tree decl;
-     tree attributes;
-     tree identifier;
-     tree args;
-{
-  return 0;
-}
-
-/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
-   attribute for TYPE.  The attributes in ATTRIBUTES have previously been
-   assigned to TYPE.  */
-
-int
-ns32k_valid_type_attribute_p (type, attributes, identifier, args)
-     tree type;
-     tree attributes;
-     tree identifier;
-     tree args;
-{
-  if (TREE_CODE (type) != FUNCTION_TYPE
-      && TREE_CODE (type) != FIELD_DECL
-      && TREE_CODE (type) != TYPE_DECL)
-    return 0;
-
-  /* Stdcall attribute says callee is responsible for popping arguments
-     if they are not variable.  */
-  if (is_attribute_p ("stdcall", identifier))
-    return (args == NULL_TREE);
-
-  /* Cdecl attribute says the callee is a normal C declaration */
-  if (is_attribute_p ("cdecl", identifier))
-    return (args == NULL_TREE);
-
-  return 0;
-}
-
-/* Return 0 if the attributes for two types are incompatible, 1 if they
-   are compatible, and 2 if they are nearly compatible (which causes a
-   warning to be generated).  */
-
-int
-ns32k_comp_type_attributes (type1, type2)
-     tree type1;
-     tree type2;
-{
-  return 1;
-}
-
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.
-
-   On the ns32k, the RET insn may be used to pop them if the number
-     of args is fixed, but if the number is variable then the caller
-     must pop them all.  RET can't be used for library calls now
-     because the library is compiled with the Unix compiler.
-   Use of RET is a selectable option, since it is incompatible with
-   standard Unix calling sequences.  If the option is not selected,
-   the caller must always pop the args.
-
-   The attribute stdcall is equivalent to RET on a per module basis.  */
-
-int
-ns32k_return_pops_args (fundecl, funtype, size)
-     tree fundecl;
-     tree funtype;
-     int size;
-{
-  int rtd = TARGET_RTD;
-
-  if (TREE_CODE (funtype) == IDENTIFIER_NODE)
-    return rtd ? size : 0;
-
-  /* Cdecl functions override -mrtd, and never pop the stack */
-  if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
-    return 0;
-
-  /* Stdcall functions will pop the stack if not variable args */
-  if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype)))
-    rtd = 1;
-
-  if (rtd)
-    {
-      if (TYPE_ARG_TYPES (funtype) == NULL_TREE
-	  || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype))) == void_type_node))
-	return size;
-    }
-
-  return 0;
-}
-
-/* PRINT_OPERAND is defined to call this function,
-   which is easier to debug than putting all the code in
-   a macro definition in ns32k.h.  */
-
-/* XXX time 12% of cpu time is in fprintf for non optimizing */
-void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     char code;
-{
-  if (code == '$')
-    PUT_IMMEDIATE_PREFIX (file);
-  else if (code == '?')
-    PUT_EXTERNAL_PREFIX (file);
-  else if (GET_CODE (x) == REG)
-    fprintf (file, "%s", ns32k_out_reg_names[REGNO (x)]);
-  else if (GET_CODE (x) == MEM)
-    {
-      rtx tmp = XEXP (x, 0);
-      output_address (XEXP (x, 0));
-    }
-  else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
-    {
-      if (GET_MODE (x) == DFmode)
-	{ 
-	  union { double d; int i[2]; } u;
-	  u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
-	  PUT_IMMEDIATE_PREFIX(file);
-#ifdef SEQUENT_ASM
-	  /* Sequent likes its floating point constants as integers */
-	  fprintf (file, "0Dx%08x%08x", u.i[1], u.i[0]);
-#else
-#ifdef ENCORE_ASM
-	  fprintf (file, "0f%.20e", u.d); 
-#else
-	  fprintf (file, "0d%.20e", u.d); 
-#endif
-#endif
-	}
-      else
-	{ 
-	  union { double d; int i[2]; } u;
-	  u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
-	  PUT_IMMEDIATE_PREFIX (file);
-#ifdef SEQUENT_ASM
-	  /* We have no way of winning if we can't get the bits
-	     for a sequent floating point number.  */
-#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
-	  abort ();
-#endif
-	  {
-	    union { float f; long l; } uu;
-	    uu.f = u.d;
-	    fprintf (file, "0Fx%08x", uu.l);
-	  }
-#else
-	  fprintf (file, "0f%.20e", u.d); 
-#endif
-	}
-    }
-  else
-    {
-      if (flag_pic
-          && GET_CODE (x) == CONST
-          && symbolic_reference_mentioned_p (x))
-        {
-	  fprintf(stderr, "illegal constant for pic-mode: \n");
-	  print_rtl(stderr, x);
-          fprintf(stderr, "\nGET_CODE (x) == %d, CONST == %d, symbolic_reference_mentioned_p (x) == %d\n",
-		  GET_CODE (x), CONST, symbolic_reference_mentioned_p(x));
-	  abort ();
-	}
-      else if (flag_pic
-               && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
-	{
-	  output_addr_const (file, x);
-	  fprintf (file, "(sb)");
-	}
-      else
-        {
-#ifdef NO_IMMEDIATE_PREFIX_IF_SYMBOLIC
-          if (GET_CODE (x) == CONST_INT)
-#endif
-	    PUT_IMMEDIATE_PREFIX (file);
-          output_addr_const (file, x);
-	}
-    }
-}
-
-/* PRINT_OPERAND_ADDRESS is defined to call this function,
-   which is easier to debug than putting all the code in
-   a macro definition in ns32k.h .  */
-
-/* Completely rewritten to get this to work with Gas for PC532 Mach.
-   This function didn't work and I just wasn't able (nor very willing) to
-   figure out how it worked.
-   90-11-25 Tatu Yl|nen <ylo@cs.hut.fi> */
-
-void
-print_operand_address (file, addr)
-     register FILE *file;
-     register rtx addr;
-{
-  static char scales[] = { 'b', 'w', 'd', 0, 'q', };
-  rtx offset, base, indexexp, tmp;
-  int scale;
-  extern int flag_pic;
-
-  if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == POST_DEC)
-    {
-      fprintf (file, "tos");
-      return;
-    }
-
-  offset = NULL;
-  base = NULL;
-  indexexp = NULL;
-  while (addr != NULL)
-    {
-      if (GET_CODE (addr) == PLUS)
-	{
-	  if (GET_CODE (XEXP (addr, 0)) == PLUS)
-	    {
-	      tmp = XEXP (addr, 1);
-	      addr = XEXP (addr, 0);
-	    }
-	  else
-	    {
-	      tmp = XEXP (addr,0);
-	      addr = XEXP (addr,1);
-	    }
-	}
-      else
-	{
-	  tmp = addr;
-	  addr = NULL;
-	}
-      switch (GET_CODE (tmp))
-	{
-	case PLUS:
-	  abort ();
-	case MEM:
-	  if (base)
-	    {
-	      indexexp = base;
-	      base = tmp;
-	    }
-	  else
-	    base = tmp;
-	  break;
-	case REG:
-	  if (REGNO (tmp) < F0_REGNUM)
-	    if (base)
-	      {
-		indexexp = tmp;
-	      }
-	    else
-	      base = tmp;
-	  else
-	    if (base)
-	      {
-		indexexp = base;
-		base = tmp;
-	      }
-	    else
-	      base = tmp;
-	  break;
-	case MULT:
-	  indexexp = tmp;
-	  break;
-	case SYMBOL_REF:
-	  if (flag_pic && ! CONSTANT_POOL_ADDRESS_P (tmp)
-	      && ! SYMBOL_REF_FLAG (tmp))
-	    {
-	      if (base)
-		{
-		  if (indexexp)
-		    abort ();
-		  indexexp = base;
-		}
-	      base = tmp;
-	      break;
-	    }
-	case CONST:
-	  if (flag_pic && GET_CODE (tmp) == CONST)
-	    {
-	      rtx sym, off, tmp1;
-	      tmp1 = XEXP (tmp,0);
-	      if (GET_CODE (tmp1)  != PLUS)
-		abort ();
-
-	      sym = XEXP (tmp1,0);
-	      if (GET_CODE (sym) != SYMBOL_REF)
-	        {
-	          off = sym;
-		  sym = XEXP (tmp1,1);
-		}
-	      else
-	        off = XEXP (tmp1,1);
-	      if (GET_CODE (sym) == SYMBOL_REF)
-		{
-		  if (GET_CODE (off) != CONST_INT)
-		    abort ();
-
-		  if (CONSTANT_POOL_ADDRESS_P (sym)
-		      || SYMBOL_REF_FLAG (sym))
-		    {
-		      SYMBOL_REF_FLAG (tmp) = 1;
-		    }
-		  else
-		    {
-		      if (base)
-			{
-			  if (indexexp)
-			    abort ();
-
-			  indexexp = base;
-			}
-
-		      if (offset != 0)
-			abort ();
-
-		      base = sym;
-		      offset = off;
-		      break;
-		    }
-		}
-	    }
-	case CONST_INT:
-	case LABEL_REF:
-	  if (offset)
-	    offset = gen_rtx (PLUS, SImode, tmp, offset);
-	  else
-	    offset = tmp;
-	  break;
-	default:
-	  abort ();
-	}
-    }
-  if (! offset)
-    offset = const0_rtx;
-
-  if (base
-#ifndef INDEX_RATHER_THAN_BASE
-      && (flag_pic || TARGET_HIMEM)
-      && GET_CODE (base) != SYMBOL_REF 
-      && GET_CODE (offset) != CONST_INT
-#else
-  /* This is a re-implementation of the SEQUENT_ADDRESS_BUG fix.  */
-#endif
-      && !indexexp && GET_CODE (base) == REG
-      && REG_OK_FOR_INDEX_P (base))
-    {
-      indexexp = base;
-      base = NULL;
-    }
-
-  /* now, offset, base and indexexp are set */
-#ifndef BASE_REG_NEEDED
-  if (! base)
-    {
-#if defined (PC_RELATIVE) || defined (NO_ABSOLUTE_PREFIX_IF_SYMBOLIC)
-      if (GET_CODE (offset) == CONST_INT)
-#endif
-	PUT_ABSOLUTE_PREFIX (file);
-    }
-#endif
-
-  output_addr_const (file, offset);
-  if (base) /* base can be (REG ...) or (MEM ...) */
-    switch (GET_CODE (base))
-      {
-	/* now we must output base.  Possible alternatives are:
-	   (rN)       (REG ...)
-	   (sp)	      (REG ...)
-	   (fp)       (REG ...)
-	   (pc)       (REG ...)  used for SYMBOL_REF and LABEL_REF, output
-	   (disp(fp)) (MEM ...)       just before possible [rX:y]
-	   (disp(sp)) (MEM ...)
-	   (disp(sb)) (MEM ...)
-	   */
-      case REG:
-	fprintf (file, "(%s)", ns32k_out_reg_names[REGNO (base)]);
-	break;
-      case SYMBOL_REF:
-	if (! flag_pic)
-	  abort ();
-
-        fprintf (file, "(");
-	output_addr_const (file, base);
-	fprintf (file, "(sb))");
-        break;
-      case MEM:
-	addr = XEXP(base,0);
-	base = NULL;
-	offset = NULL;
-	while (addr != NULL)
-	  {
-	    if (GET_CODE (addr) == PLUS)
-	      {
-		if (GET_CODE (XEXP (addr, 0)) == PLUS)
-		  {
-		    tmp = XEXP (addr, 1);
-		    addr = XEXP (addr, 0);
-		  }
-		else
-		  {
-		    tmp = XEXP (addr, 0);
-		    addr = XEXP (addr, 1);
-		  }
-	      }
-	    else
-	      {
-		tmp = addr;
-		addr = NULL;
-	      }
-	    switch (GET_CODE (tmp))
-	      {
-	      case REG:
-		base = tmp;
-		break;
-	      case CONST:
-	      case CONST_INT:
-	      case SYMBOL_REF:
-	      case LABEL_REF:
-		if (offset)
-		  offset = gen_rtx (PLUS, SImode, tmp, offset);
-		else
-		  offset = tmp;
-		break;
-	      default:
-		abort ();
-	      }
-	  }
-	if (! offset)
-	  offset = const0_rtx;
-	fprintf (file, "(");
-	output_addr_const (file, offset);
-	if (base)
-	  fprintf (file, "(%s)", ns32k_out_reg_names[REGNO (base)]);
-	else if (TARGET_SB)
-	  fprintf (file, "(sb)");
-	else
-	  abort ();
-	fprintf (file, ")");
-	break;
-      default:
-	abort ();
-      }
-#ifdef PC_RELATIVE
-  else if (GET_CODE (offset) != CONST_INT)
-    fprintf (file, "(pc)");
-#ifdef BASE_REG_NEEDED
-  else if (TARGET_SB)
-    fprintf (file, "(sb)");
-  else
-    abort ();
-#endif
-#endif /* PC_RELATIVE */
-
-  /* now print index if we have one */
-  if (indexexp)
-    {
-      if (GET_CODE (indexexp) == MULT)
-	{
-	  scale = INTVAL (XEXP (indexexp, 1)) >> 1;
-	  indexexp = XEXP (indexexp, 0);
-	}
-      else
-	scale = 0;
-      if (GET_CODE (indexexp) != REG || REGNO (indexexp) >= F0_REGNUM)
-	abort ();
-
-#ifdef UTEK_ASM
-      fprintf (file, "[%c`%s]",
-	       scales[scale],
-	       ns32k_out_reg_names[REGNO (indexexp)]);
-#else
-      fprintf (file, "[%s:%c]",
-	       ns32k_out_reg_names[REGNO (indexexp)],
-	       scales[scale]);
-#endif
-    }
-}
-
-/* National 32032 shifting is so bad that we can get
-   better performance in many common cases by using other
-   techniques.  */
-char *
-output_shift_insn (operands)
-     rtx *operands;
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) > 0
-      && INTVAL (operands[2]) <= 3)
-    if (GET_CODE (operands[0]) == REG)
-      {
-	if (GET_CODE (operands[1]) == REG)
-	  {
-	    if (REGNO (operands[0]) == REGNO (operands[1]))
-	      {
-		if (operands[2] == const1_rtx)
-		  return "addd %0,%0";
-		else if (INTVAL (operands[2]) == 2)
-		  return "addd %0,%0\n\taddd %0,%0";
-	      }
-	    if (operands[2] == const1_rtx)
-	      return "movd %1,%0\n\taddd %0,%0";
-	    
-	    operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
-	    return "addr %a1,%0";
-	  }
-	if (operands[2] == const1_rtx)
-	  return "movd %1,%0\n\taddd %0,%0";
-      }
-    else if (GET_CODE (operands[1]) == REG)
-      {
-	operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
-	return "addr %a1,%0";
-      }
-    else if (INTVAL (operands[2]) == 1
-	     && GET_CODE (operands[1]) == MEM
-	     && rtx_equal_p (operands [0], operands[1]))
-      {
-	rtx temp = XEXP (operands[1], 0);
-	
-	if (GET_CODE (temp) == REG
-	    || (GET_CODE (temp) == PLUS
-		&& GET_CODE (XEXP (temp, 0)) == REG
-		&& GET_CODE (XEXP (temp, 1)) == CONST_INT))
-	  return "addd %0,%0";
-      }
-    else return "ashd %2,%0";
-  return "ashd %2,%0";
-}
-
-char *
-output_move_dconst (n, s)
-	int n;
-	char *s;
-{
-  static char r[32];
-
-  if (n > -9 && n < 8)
-    strcpy (r, "movqd ");
-  else if (n > 0 && n < 256)
-    strcpy (r, "movzbd ");
-  else if (n > 0 && n < 65536)
-    strcpy (r, "movzwd ");
-  else if (n < 0 && n > -129)
-    strcpy (r, "movxbd ");
-  else if (n < 0 && n > -32769)
-    strcpy (r, "movxwd ");
-  else
-    strcpy (r, "movd ");
-  strcat (r, s);
-  return r;
-}
diff --git a/gcc/config/ns32k/ns32k.h b/gcc/config/ns32k/ns32k.h
deleted file mode 100755
index d409ac2..0000000
--- a/gcc/config/ns32k/ns32k.h
+++ /dev/null
@@ -1,1722 +0,0 @@
-/* Definitions of target machine for GNU compiler.  NS32000 version.
-   Copyright (C) 1988, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@cygnus.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Note that some other tm.h files include this one and then override
-   many of the definitions that relate to assembler syntax.  */
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dns32000 -Dunix -Asystem(unix) -Acpu(ns32k) -Amachine(ns32k)"
-
-/* Print subsidiary information on the compiler version in use.  */
-#define TARGET_VERSION fprintf (stderr, " (32000, GAS syntax)");
-
-
-/* ABSOLUTE PREFIX, IMMEDIATE_PREFIX and EXTERNAL_PREFIX can be defined
-   to cover most NS32k addressing syntax variations.  This way we don't
-   need to redefine long macros in all the tm.h files for just slight
-   variations in assembler syntax. */
-
-#ifndef ABSOLUTE_PREFIX
-#define ABSOLUTE_PREFIX '@'
-#endif
-
-#if defined(IMMEDIATE_PREFIX) && IMMEDIATE_PREFIX
-#define PUT_IMMEDIATE_PREFIX(FILE) putc(IMMEDIATE_PREFIX, FILE)
-#else
-#define PUT_IMMEDIATE_PREFIX(FILE)
-#endif
-#if defined(ABSOLUTE_PREFIX) && ABSOLUTE_PREFIX
-#define PUT_ABSOLUTE_PREFIX(FILE) putc(ABSOLUTE_PREFIX, FILE)
-#else
-#define PUT_ABSOLUTE_PREFIX(FILE)
-#endif
-#if defined(EXTERNAL_PREFIX) && EXTERNAL_PREFIX
-#define PUT_EXTERNAL_PREFIX(FILE) putc(EXTERNAL_PREFIX, FILE)
-#else
-#define PUT_EXTERNAL_PREFIX(FILE)
-#endif
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Compile 32081 insns for floating point (not library calls). */
-#define TARGET_32081 (target_flags & 1)
-#define TARGET_32381 (target_flags & 256)
-
-/* The use of multiply-add instructions is optional because it can
- * cause an abort due to being unable to find a spill register. The
- * main problem is that the multiply-add instructions require f0 and
- * f0 is not available for spilling because it is "explicitly
- * mentioned" in the rtl for function return values. This can be fixed
- * by defining SMALL_REGISTER_CLASSES, but that causes worse code for
- * the (more common) integer case. We really need better reload code.
- */
-
-#define TARGET_MULT_ADD (target_flags & 512)
-
-/* Compile using rtd insn calling sequence.
-   This will not work unless you use prototypes at least
-   for all functions that can take varying numbers of args.  */
-#define TARGET_RTD (target_flags & 2)
-
-/* Compile passing first two args in regs 0 and 1.  */
-#define TARGET_REGPARM (target_flags & 4)
-
-/* Options to select type of CPU, for better optimization.
-   The output is correct for any kind of 32000 regardless of these options.  */
-#define TARGET_32532 (target_flags & 8)
-#define TARGET_32332 (target_flags & 16)
-
-/* Ok to use the static base register (and presume it's 0) */
-#define TARGET_SB    ((target_flags & 32) == 0)
-#define TARGET_HIMEM (target_flags & 128)
-
-/* Compile using bitfield insns.  */
-#define TARGET_BITFIELD ((target_flags & 64) == 0)
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES				\
-  { { "32081", 1},				\
-    { "soft-float", -257},			\
-    { "rtd", 2},				\
-    { "nortd", -2},				\
-    { "regparm", 4},				\
-    { "noregparm", -4},				\
-    { "32532", 24},				\
-    { "32332", -8},				\
-    { "32332", 16},				\
-    { "32032", -24},				\
-    { "sb", -32},				\
-    { "nosb", 32},				\
-    { "bitfield", -64},				\
-    { "nobitfield", 64},			\
-    { "himem", 128},				\
-    { "nohimem", -128},				\
-    { "32381", 256},				\
-    { "mult-add", 512},				\
-    { "nomult-add", -512},            		\
-    { "", TARGET_DEFAULT}}
-
-/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc.  */
-
-/* When we are generating PIC, the sb is used as a pointer
-   to the GOT. 32381 is a superset of 32081  */
-
-#define OVERRIDE_OPTIONS				\
-{							\
-  if (flag_pic || TARGET_HIMEM) target_flags |= 32;	\
-  if (TARGET_32381) target_flags |= 1;			\
-  else target_flags &= ~512;				\
-}
-
-/* Zero or more C statements that may conditionally modify two
-   variables `fixed_regs' and `call_used_regs' (both of type `char
-   []') after they have been initialized from the two preceding
-   macros.
-
-   This is necessary in case the fixed or call-clobbered registers
-   depend on target flags.
-
-   You need not define this macro if it has no work to do.
-
-   If the usage of an entire class of registers depends on the target
-   flags, you may indicate this to GCC by using this macro to modify
-   `fixed_regs' and `call_used_regs' to 1 for each of the registers in
-   the classes which should not be used by GCC.  Also define the macro
-   `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
-   letter for a class that shouldn't be used.
-
-   (However, if this class is not included in `GENERAL_REGS' and all
-   of the insn patterns whose constraints permit this class are
-   controlled by target switches, then GCC will automatically avoid
-   using these registers when the target switches are opposed to
-   them.)  */
-
-#define CONDITIONAL_REGISTER_USAGE					\
-do									\
-  {									\
-    if (!TARGET_32081)						\
-      {									\
-	int regno;							\
-									\
-	for (regno = F0_REGNUM; regno <= F0_REGNUM + 8; regno++)	\
-	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
-      }									\
-    if (!TARGET_32381)						\
-      {									\
-	int regno;							\
-									\
-	for (regno = L1_REGNUM; regno <= L1_REGNUM + 8; regno++)	\
-	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
-      }									\
-  }									\
-while (0)
-
-
-/* target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is not true on the ns32k.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is not true on the ns32k.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered. This is not true on the ns32k.  */
-#define WORDS_BIG_ENDIAN 0
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 32000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 16
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 32
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  National claims that the NS32032
-   works without strict alignment, but rumor has it that operands
-   crossing a page boundary cause unpredictable results.  */
-#define STRICT_ALIGNMENT 1
-
-/* If bit field type is int, dont let it cross an int,
-   and give entire struct the alignment of an int.  */
-/* Required on the 386 since it doesn't have a full set of bitfield insns.
-   (There is no signed extv insn.)  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  */
-#define FIRST_PSEUDO_REGISTER 26
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   On the ns32k, these are the FP, SP, (SB and PC are not included here).  */
-#define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, \
-			 0, 0, 0, 0, 0, 0, 0, 0, \
-                         0, 0, 0, 0, 0, 0, 0, 0, \
-			 1, 1}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS {1, 1, 1, 0, 0, 0, 0, 0, \
-			     1, 1, 1, 1, 0, 0, 0, 0, \
-			     1, 1, 0, 0, 0, 0, 0, 0, \
-			     1, 1}
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
- "l1", "l1h","l3", "l3h","l5", "l5h","l7", "l7h", \
- "fp", "sp"}
-
-
-#define ADDITIONAL_REGISTER_NAMES \
-{{"l0", 8}, {"l2", 10}, {"l4", 12}, {"l6", 14}}
-
-/* l0-7 are not recognized by the assembler. These are the names to use,
- * but we don't want ambiguous names in REGISTER_NAMES
- */
-#define OUTPUT_REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
- "f1", "l1h","f3", "l3h","f5", "l5h","f7", "f7h", \
- "fp", "sp"}
-
-#define REG_ALLOC_ORDER \
-{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16, 10, 11, 18, 12, 13, 20, 14, 15, 22, 24, 25, 17, 19, 23}
-
-/* How to renumber registers for dbx and gdb.
-   NS32000 may need more change in the numeration. XXX */
-
-#define DBX_REGISTER_NUMBER(REGNO) \
-  ((REGNO) < L1_REGNUM? (REGNO) \
-   : (REGNO) < FRAME_POINTER_REGNUM? (REGNO) - L1_REGNUM + 22 \
-   : (REGNO) == FRAME_POINTER_REGNUM? 17 \
-   : 16)
-
-
-
-
-#define R0_REGNUM 0
-#define F0_REGNUM 8
-#define L1_REGNUM 16
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* NS32000 pc is not overloaded on a register.  */
-/* #define PC_REGNUM */
-
-/* Register to use for pushing function arguments. */
-#define STACK_POINTER_REGNUM 25
-
-/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 24
-
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-   On the ns32k, all registers are 32 bits long except for the 32381 "long"
-   registers but we treat those as pairs  */
-#define LONG_FP_REGS_P(REGNO) ((REGNO) >= L1_REGNUM && (REGNO) < L1_REGNUM + 8)
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok (REGNO, MODE)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.
-
-   Early documentation says SI and DI are not tieable if some reg can
-   be OK for SI but not for DI. However other ports (mips, i860, mvs
-   and tahoe) don't meet the above criterion. Evidently the real
-   requirement is somewhat laxer. Documentation was changed for gcc
-   2.8 but was not picked up by egcs (at least egcs 1.0). Having all
-   integer modes tieable definitely generates faster code. */
-
-#define MODES_TIEABLE_P(MODE1, MODE2)					\
-  ((FLOAT_MODE_P(MODE1) && FLOAT_MODE_P(MODE2)				\
-    && (GET_MODE_UNIT_SIZE(MODE1) == GET_MODE_UNIT_SIZE(MODE2)))	\
-   || (!FLOAT_MODE_P(MODE1) && !FLOAT_MODE_P(MODE2)))
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 24
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 1
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 2
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-enum reg_class
-{ NO_REGS, GENERAL_REGS, FLOAT_REG0, LONG_FLOAT_REG0, FLOAT_REGS,
-  FP_REGS, GEN_AND_FP_REGS, FRAME_POINTER_REG, STACK_POINTER_REG,
-  GEN_AND_MEM_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "GENERAL_REGS", "FLOAT_REG0", "LONG_FLOAT_REG0", "FLOAT_REGS", \
-  "FP_REGS", "GEN_AND_FP_REGS", "FRAME_POINTER_REG", "STACK_POINTER_REG", \
-  "GEN_AND_MEM_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS {0, 0x00ff, 0x100, 0x300, 0xff00, \
-                            0xffff00, 0xffffff, 0x1000000, 0x2000000, \
-                            0x30000ff, 0x3ffffff }
-
-#define SUBSET_P(CLASS1, CLASS2) \
-   ((ns32k_reg_class_contents[CLASS1] & ~ns32k_reg_class_contents[CLASS2]) \
-     == 0)
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO)  (regclass_map[REGNO])
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS  GEN_AND_MEM_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C)		\
- ((C) == 'u' ? FLOAT_REG0			\
-  : (C) == 'v' ? LONG_FLOAT_REG0		\
-  : (C) == 'f' ? FLOAT_REGS			\
-  : (C) == 'l' ? FP_REGS			\
-  : (C) == 'x' ? FRAME_POINTER_REG		\
-  : (C) == 'y' ? STACK_POINTER_REG		\
-  : NO_REGS)
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   On the ns32k, these letters are used as follows:
-
-   I : Matches integers which are valid shift amounts for scaled indexing.
-       These are 0, 1, 2, 3 for byte, word, double, and quadword.
-       Used for matching arithmetic shifts only on 32032 & 32332.
-   J : Matches integers which fit a "quick" operand.
-   K : Matches integers 0 to 7 (for inss and exts instructions).
-  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
-  ((VALUE) < 8 && (VALUE) + 8 >= 0 ?		\
-   ((C) == 'I' ? (!TARGET_32532 && 0 <= (VALUE) && (VALUE) <= 3) : \
-    (C) == 'J' ? (VALUE) <= 7 :			\
-    (C) == 'K' ? 0 <= (VALUE) : 0) : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-/* We return GENERAL_REGS instead of GEN_AND_MEM_REGS.
-   The latter offers no real additional possibilities
-   and can cause spurious secondary reloading.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
- ((CLASS) == GEN_AND_MEM_REGS ? GENERAL_REGS : (CLASS))
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-/* On the 32000, this is the size of MODE in words */
-
-#define CLASS_MAX_NREGS(CLASS, MODE) \
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET 0
-
-/* A C expression whose value is RTL representing the location of the
-   incoming return address at the beginning of any function, before
-   the prologue.  This RTL is either a `REG', indicating that the
-   return value is saved in `REG', or a `MEM' representing a location
-   in the stack.
-
-   You only need to define this macro if you want to support call
-   frame debugging information like that provided by DWARF 2.
-
-   Before the prologue, RA is at 0(sp).  */
-
-#define INCOMING_RETURN_ADDR_RTX \
-  gen_rtx (MEM, VOIDmode, gen_rtx (REG, VOIDmode, STACK_POINTER_REGNUM))
-
-/* A C expression whose value is RTL representing the value of the
-   return address for the frame COUNT steps up from the current frame,
-   after the prologue.  FRAMEADDR is the frame pointer of the COUNT
-   frame, or the frame pointer of the COUNT - 1 frame if
-   `RETURN_ADDR_IN_PREVIOUS_FRAME' is defined.
-
-   After the prologue, RA is at 4(fp) in the current frame.  */
-
-#define RETURN_ADDR_RTX(COUNT, FRAME)					\
-  (gen_rtx (MEM, Pmode, gen_rtx (PLUS, Pmode, (FRAME), GEN_INT(4))))
-
-/* A C expression whose value is an integer giving the offset, in
-   bytes, from the value of the stack pointer register to the top of
-   the stack frame at the beginning of any function, before the
-   prologue.  The top of the frame is defined to be the value of the
-   stack pointer in the previous frame, just before the call
-   instruction.
-
-   You only need to define this macro if you want to support call
-   frame debugging information like that provided by DWARF 2. */
-
-#define INCOMING_FRAME_SP_OFFSET 4
-
-/* Offset of the CFA from the argument pointer register value.  */
-#define ARG_POINTER_CFA_OFFSET 8
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On the 32000, sp@- in a byte insn really pushes a BYTE.  */
-#define PUSH_ROUNDING(BYTES) (BYTES)
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 8
-
-/* Value is the number of byte of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.
-
-   On the 32000, the RET insn may be used to pop them if the number
-     of args is fixed, but if the number is variable then the caller
-     must pop them all.  RET can't be used for library calls now
-     because the library is compiled with the Unix compiler.
-   Use of RET is a selectable option, since it is incompatible with
-   standard Unix calling sequences.  If the option is not selected,
-   the caller must always pop the args.
-
-   The attribute stdcall is equivalent to RTD on a per module basis.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
-  (ns32k_return_pops_args (FUNDECL, FUNTYPE, SIZE))
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-/* On the 32000 the return value is in R0,
-   or perhaps in F0 if there is fp support.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE(TYPE_MODE (VALTYPE))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-/* On the 32000 the return value is in R0,
-   or perhaps F0 is there is fp support.  */
-
-#define LIBCALL_VALUE(MODE)  \
-  gen_rtx (REG, MODE,				  \
-	   FLOAT_MODE_P(MODE) && TARGET_32081 ? F0_REGNUM: R0_REGNUM)
-
-/* Define this if PCC uses the nonreentrant convention for returning
-   structure and union values.  */
-
-#define PCC_STATIC_STRUCT_RETURN
-
-/* 1 if N is a possible register number for a function value.
-   On the 32000, R0 and F0 are the only registers thus used.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) (((N) & ~8) == 0)
-
-/* 1 if N is a possible register number for function argument passing.
-   On the 32000, no registers are used in this way.  */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the ns32k, this is a single integer, which is a number of bytes
-   of arguments scanned so far.  */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the ns32k, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM) += ((MODE) != BLKmode			\
-	    ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
-	    : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On the 32000 all args are pushed, except if -mregparm is specified
-   then the first two words of arguments are passed in r0, r1.
-   *NOTE* -mregparm does not work.
-   It exists only to test register calling conventions.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)	\
-((TARGET_REGPARM && (CUM) < 8					\
-  && 8 < ((CUM) + ((MODE) == BLKmode				\
-		      ? int_size_in_bytes (TYPE)		\
-		      : GET_MODE_SIZE (MODE))))  		\
- ? 2 - (CUM) / 4 : 0)
-
-#ifndef MAIN_FUNCTION_PROLOGUE
-#define MAIN_FUNCTION_PROLOGUE
-#endif
-
-/*
- * The function prologue for the ns32k is fairly simple.
- * If a frame pointer is needed (decided in reload.c ?) then
- * we need assembler of the form
- *
- *  # Save the oldframe pointer, set the new frame pointer, make space
- *  # on the stack and save any general purpose registers necessary
- *
- *  enter [<general purpose regs to save>], <local stack space>
- *
- *  movf  fn, tos    # Save any floating point registers necessary
- *  .
- *  .
- *
- * If a frame pointer is not needed we need assembler of the form
- *
- *  # Make space on the stack
- *
- *  adjspd <local stack space + 4>
- *
- *  # Save any general purpose registers necessary
- *
- *  save [<general purpose regs to save>]
- *
- *  movf  fn, tos    # Save any floating point registers necessary
- *  .
- *  .
- */
-#if defined(IMMEDIATE_PREFIX) && IMMEDIATE_PREFIX
-#define ADJSP(FILE, n) \
-        fprintf (FILE, "\tadjspd %c%d\n", IMMEDIATE_PREFIX, (n))
-#else
-#define ADJSP(FILE, n) \
-        fprintf (FILE, "\tadjspd %d\n", (n))
-#endif
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)     \
-{ register int regno, g_regs_used = 0;				\
-  int used_regs_buf[8], *bufp = used_regs_buf;			\
-  int used_fregs_buf[17], *fbufp = used_fregs_buf;		\
-  extern char call_used_regs[];					\
-  extern int current_function_uses_pic_offset_table, flag_pic;	\
-  MAIN_FUNCTION_PROLOGUE;					\
-  for (regno = R0_REGNUM; regno < F0_REGNUM; regno++)		\
-    if (regs_ever_live[regno]					\
-	&& ! call_used_regs[regno])				\
-      {								\
-        *bufp++ = regno; g_regs_used++;				\
-      }								\
-  *bufp = -1;							\
-  for (; regno < FRAME_POINTER_REGNUM; regno++)			\
-    if (regs_ever_live[regno] && !call_used_regs[regno])	\
-      {								\
-        *fbufp++ = regno;					\
-      }								\
-  *fbufp = -1;							\
-  bufp = used_regs_buf;						\
-  if (frame_pointer_needed)					\
-    fprintf (FILE, "\tenter [");				\
-  else								\
-    {								\
-      if (SIZE)							\
-        ADJSP (FILE, SIZE + 4);					\
-      if (g_regs_used && g_regs_used > 4)			\
-        fprintf (FILE, "\tsave [");				\
-      else							\
-	{							\
-	  while (*bufp >= 0)					\
-            fprintf (FILE, "\tmovd r%d,tos\n", *bufp++);	\
-	  g_regs_used = 0;					\
-	}							\
-    }								\
-  while (*bufp >= 0)						\
-    {								\
-      fprintf (FILE, "r%d", *bufp++);				\
-      if (*bufp >= 0)						\
-	fputc (',', FILE);					\
-    }								\
-  if (frame_pointer_needed)					\
-    fprintf (FILE, "],%d\n", SIZE);				\
-  else if (g_regs_used)						\
-    fprintf (FILE, "]\n");					\
-  fbufp = used_fregs_buf;					\
-  while (*fbufp >= 0)						\
-    {								\
-      if ((*fbufp & 1) || (fbufp[0] != fbufp[1] - 1))	\
-	fprintf (FILE, "\tmovf %s,tos\n", ns32k_out_reg_names[*fbufp++]); \
-      else							\
-	{							\
-	  fprintf (FILE, "\tmovl %s,tos\n",                     \
-		   ns32k_out_reg_names[fbufp[0]]);                    \
-	  fbufp += 2;						\
-	}							\
-    }								\
-  if (flag_pic && current_function_uses_pic_offset_table)	\
-    {								\
-      fprintf (FILE, "\tsprd sb,tos\n");			\
-      if (TARGET_REGPARM)					\
-	{							\
-	  fprintf (FILE, "\taddr __GLOBAL_OFFSET_TABLE_(pc),tos\n"); \
-	  fprintf (FILE, "\tlprd sb,tos\n");			\
-	}							\
-      else							\
-	{							\
-	  fprintf (FILE, "\taddr __GLOBAL_OFFSET_TABLE_(pc),r0\n"); \
-	  fprintf (FILE, "\tlprd sb,r0\n");			\
-	}							\
-    }								\
-}
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.
-
-   THIS DEFINITION FOR THE 32000 IS A GUESS.  IT HAS NOT BEEN TESTED.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   fprintf (FILE, "\taddr LP%d,r0\n\tbsr mcount\n", (LABELNO))
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.
-
-   We use 0, because using 1 requires hair in FUNCTION_EPILOGUE
-   that is worse than the stack adjust we could save.  */
-
-/* #define EXIT_IGNORE_STACK 1 */
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer,
-   if EXIT_IGNORE_STACK is nonzero.  That doesn't apply here.
-
-   If a frame pointer is needed (decided in reload.c ?) then
-   we need assembler of the form
-
-    movf  tos, fn	# Restore any saved floating point registers
-    .
-    .
-
-    # Restore any saved general purpose registers, restore the stack
-    # pointer from the frame pointer, restore the old frame pointer.
-    exit [<general purpose regs to save>]
-
-   If a frame pointer is not needed we need assembler of the form
-    # Restore any general purpose registers saved
-
-    movf  tos, fn	# Restore any saved floating point registers
-    .
-    .
-    .
-    restore [<general purpose regs to save>]
-
-    # reclaim space allocated on stack
-
-    adjspd <-(local stack space + 4)> */
-
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-{ register int regno, g_regs_used = 0, f_regs_used = 0;		\
-  int used_regs_buf[8], *bufp = used_regs_buf;			\
-  int used_fregs_buf[17], *fbufp = used_fregs_buf;		\
-  extern char call_used_regs[];					\
-  extern int current_function_uses_pic_offset_table, flag_pic;	\
-  if (flag_pic && current_function_uses_pic_offset_table)	\
-    fprintf (FILE, "\tlprd sb,tos\n");				\
-  *fbufp++ = -2;						\
-  for (regno = F0_REGNUM; regno < FRAME_POINTER_REGNUM; regno++) \
-    if (regs_ever_live[regno] && !call_used_regs[regno])	\
-      {								\
-       *fbufp++ = regno; f_regs_used++;				\
-      }								\
-  fbufp--;							\
-  for (regno = 0; regno < F0_REGNUM; regno++)			\
-    if (regs_ever_live[regno]					\
-	&& ! call_used_regs[regno])				\
-      {                                                        	\
-        *bufp++ = regno; g_regs_used++;				\
-      }                                                        	\
-  while (fbufp > used_fregs_buf)				\
-    {								\
-      if ((*fbufp & 1) && fbufp[0] == fbufp[-1] + 1)	        \
-	{							\
-	  fprintf (FILE, "\tmovl tos,%s\n",                     \
-		   ns32k_out_reg_names[fbufp[-1]]);                   \
-	  fbufp -= 2;						\
-	}							\
-      else fprintf (FILE, "\tmovf tos,%s\n", ns32k_out_reg_names[*fbufp--]); \
-    }								\
-  if (frame_pointer_needed)					\
-    fprintf (FILE, "\texit [");					\
-  else								\
-    {								\
-      if (g_regs_used && g_regs_used > 4)			\
-        fprintf (FILE, "\trestore [");				\
-      else							\
-        {							\
-	  while (bufp > used_regs_buf)				\
-            fprintf (FILE, "\tmovd tos,r%d\n", *--bufp);	\
-	  g_regs_used = 0;					\
-        }							\
-    }								\
-  while (bufp > used_regs_buf)					\
-    {								\
-      fprintf (FILE, "r%d", *--bufp);				\
-      if (bufp > used_regs_buf)					\
-	fputc (',', FILE);					\
-    }								\
-  if (g_regs_used || frame_pointer_needed)			\
-    fprintf (FILE, "]\n");					\
-  if (SIZE && !frame_pointer_needed)				\
-    ADJSP (FILE, -(SIZE + 4));					\
-  if (current_function_pops_args)				\
-    fprintf (FILE, "\tret %d\n", current_function_pops_args);	\
-  else fprintf (FILE, "\tret 0\n"); }
-
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved.  */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)			\
-{								\
-  int regno;							\
-  int offset = -4;						\
-  extern int current_function_uses_pic_offset_table, flag_pic;	\
-  for (regno = 0; regno < L1_REGNUM; regno++)			\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      offset += 4;						\
-  for (; regno < FRAME_POINTER_REGNUM; regno++)			\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      offset += 8;						\
-  if (flag_pic && current_function_uses_pic_offset_table)	\
-    offset += 4;						\
-  (DEPTH) = (offset + get_frame_size ()				\
-	     + (get_frame_size () == 0 ? 0 : 4));		\
-}
-
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  */
-
-/* On the 32k, the trampoline looks like this:
-     addr  0(pc),r2
-     jump  @__trampoline
-     .int STATIC
-     .int FUNCTION
-Doing trampolines with a library assist function is easier than figuring
-out how to do stores to memory in reverse byte order (the way immediate
-operands on the 32k are stored).  */
-
-#define TRAMPOLINE_TEMPLATE(FILE)					\
-{									\
-  fprintf (FILE, "\taddr 0(pc),r2\n" );					\
-  fprintf (FILE, "\tjump " );						\
-  PUT_ABSOLUTE_PREFIX (FILE);						\
-  fprintf (FILE, "__trampoline\n" );					\
-  ASM_OUTPUT_INT (FILE, const0_rtx);					\
-  ASM_OUTPUT_INT (FILE, const0_rtx);					\
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 20
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			     \
-{									     \
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), CXT);    \
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), FNADDR); \
-}
-
-/* This is the library routine that is used
-   to transfer control from the trampoline
-   to the actual nested function.  */
-
-/* The function name __transfer_from_trampoline is not actually used.
-   The function definition just permits use of "asm with operands"
-   (though the operand list is empty).  */
-#define TRANSFER_FROM_TRAMPOLINE	\
-void					\
-__transfer_from_trampoline ()		\
-{					\
-  asm (".globl __trampoline");		\
-  asm ("__trampoline:");		\
-  asm ("movd 16(r2),tos");		\
-  asm ("movd 12(r2),r1");		\
-  asm ("ret 0");			\
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-/* note that FP and SP cannot be used as an index. What about PC? */
-#define REGNO_OK_FOR_INDEX_P(REGNO)  \
-((REGNO) < F0_REGNUM || (unsigned)reg_renumber[REGNO] < F0_REGNUM)
-#define REGNO_OK_FOR_BASE_P(REGNO)   \
-((REGNO) < F0_REGNUM || (unsigned)reg_renumber[REGNO] < F0_REGNUM \
- || (REGNO) == FRAME_POINTER_REGNUM || (REGNO) == STACK_POINTER_REGNUM)
-
-#define FP_REG_P(X) \
- (GET_CODE (X) == REG && REGNO (X) >= F0_REGNUM && REGNO (X) < FRAME_POINTER_REGNUM)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address.
-   This might not work on future ns32k processors as negative
-   displacements are not officially allowed but a mode reserved
-   to National.  This works on processors up to 32532, though,
-   and we don't expect any new ones in the series ;-( */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST						\
-   || (GET_CODE (X) == CONST_INT					\
-       && NS32K_DISPLACEMENT_P (INTVAL (X))))
-
-#define CONSTANT_ADDRESS_NO_LABEL_P(X)   \
-  (GET_CODE (X) == CONST_INT						\
-   && NS32K_DISPLACEMENT_P (INTVAL (X)))
-
-/* Return the register class of a scratch register needed to copy IN into
-   or out of a register in CLASS in MODE.  If it can be done directly,
-   NO_REGS is returned.  */
-
-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
-  secondary_reload_class (CLASS, MODE, IN)
-
-/*  Certain machines have the property that some registers cannot be
-    copied to some other registers without using memory.  Define this
-    macro on those machines to be a C expression that is non-zero if
-    objects of mode M in registers of CLASS1 can only be copied to
-    registers of class CLASS2 by storing a register of CLASS1 into
-    memory and loading that memory location into a register of CLASS2.
-
-    On the ns32k, floating point regs can only be loaded through memory
-
-    The movdf and movsf insns in ns32k.md copy between general and
-    floating registers using the stack. In principle, we could get
-    better code not allowing that case in the constraints and defining
-    SECONDARY_MEMORY_NEEDED in practice, though the stack slots used
-    are not available for optimization.  */
-
-#if 0
-#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, M)			\
-     secondary_memory_needed(CLASS1, CLASS2, M)
-#endif
-
-/* SMALL_REGISTER_CLASSES is true only if we have said we are using the
- * multiply-add instructions.
- */
-#define SMALL_REGISTER_CLASSES (target_flags & 512)
-
-/* A C expression whose value is nonzero if pseudos that have been
-   assigned to registers of class CLASS would likely be spilled
-   because registers of CLASS are needed for spill registers.
-
-   The default definition won't do because class LONG_FLOAT_REG0 has two
-   registers which are always acessed as a pair */
-
-#define CLASS_LIKELY_SPILLED_P(CLASS) \
-  (reg_class_size[(int) (CLASS)] == 1 || (CLASS) == LONG_FLOAT_REG0)
-
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) \
-  (REGNO (X) < F0_REGNUM || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   of if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) (REGNO (X) < F0_REGNUM || REGNO (X) >= FRAME_POINTER_REGNUM)
-/* Nonzero if X is a floating point reg or a pseudo reg.  */
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS.  */
-
-/* 1 if X is an address that we could indirect through.  */
-/***** NOTE ***** There is a bug in the Sequent assembler which fails
- to fixup addressing information for symbols used as offsets
- from registers which are not FP or SP (or SB or PC).  This
- makes _x(fp) valid, while _x(r0) is invalid.  */
-
-#define INDIRECTABLE_1_ADDRESS_P(X)  \
-  (CONSTANT_ADDRESS_P (X)						\
-   || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
-   || (GET_CODE (X) == PLUS						\
-       && GET_CODE (XEXP (X, 0)) == REG					\
-       && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
-       && ((flag_pic || TARGET_HIMEM) ? 				\
-	     CONSTANT_ADDRESS_NO_LABEL_P (XEXP (X, 1))	 		\
-	   :								\
-	     CONSTANT_ADDRESS_P (XEXP (X, 1))) 				\
-       && (GET_CODE (X) != CONST_INT || NS32K_DISPLACEMENT_P (INTVAL (X)))))
-
-/* 1 if integer I will fit in a 4 byte displacement field.
-   Strictly speaking, we can't be sure that a symbol will fit this range.
-   But, in practice, it always will.  */
-
-/* idall@eleceng.adelaide.edu.au says that the 32016 and 32032
-   can handle the full range of displacements--it is only the addresses
-   that have a limited range.  So the following was deleted:
- (((i) <= 16777215 && (i) >= -16777216)
-  || ((TARGET_32532 || TARGET_32332) && ...))  */
-#define NS32K_DISPLACEMENT_P(i) 				\
-  ((i) < (1 << 29) && (i) >= - (1 << 29))
-
-/* Check for frame pointer or stack pointer.  */
-#define MEM_REG(X) \
-  (GET_CODE (X) == REG && (REGNO (X) == FRAME_POINTER_REGNUM  \
-			   || REGNO(X) == STACK_POINTER_REGNUM))
-
-/* A memory ref whose address is the FP or SP, with optional integer offset,
-   or (on certain machines) a constant address.  */
-#define INDIRECTABLE_2_ADDRESS_P(X)  \
-  (GET_CODE (X) == MEM							\
-   && (((xfoo0 = XEXP (X, 0), MEM_REG (xfoo0))				\
-       || (GET_CODE (xfoo0) == PLUS					\
-	   && MEM_REG (XEXP (xfoo0, 0))					\
-	   && CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfoo0, 1))))		\
-       || (TARGET_SB && CONSTANT_ADDRESS_P (xfoo0))))
-
-/* Go to ADDR if X is a valid address not using indexing.
-   (This much is the easy part.)  */
-#define GO_IF_NONINDEXED_ADDRESS(X, ADDR)  \
-{ register rtx xfoob = (X);						\
-  if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR;				\
-  if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR;				\
-  if (GET_CODE (X) == PLUS)						\
-    if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (X, 1)))			\
-      if (INDIRECTABLE_2_ADDRESS_P (XEXP (X, 0)))			\
-	goto ADDR;							\
-}
-
-/* Go to ADDR if X is a valid address not using indexing.
-   (This much is the easy part.)  */
-#define GO_IF_INDEXING(X, MODE, ADDR)  \
-{ register rtx xfoob = (X);						\
-  if (GET_CODE (xfoob) == PLUS && INDEX_TERM_P (XEXP (xfoob, 0), MODE))	\
-    GO_IF_INDEXABLE_ADDRESS (XEXP (xfoob, 1), ADDR);			\
-  if (GET_CODE (xfoob) == PLUS && INDEX_TERM_P (XEXP (xfoob, 1), MODE))	\
-    GO_IF_INDEXABLE_ADDRESS (XEXP (xfoob, 0), ADDR); }			\
-
-#define GO_IF_INDEXABLE_ADDRESS(X, ADDR) \
-{ if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR;		\
-  if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR;				\
-  if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR;				\
-}
-
-/* 1 if PROD is either a reg times size of mode MODE
-   or just a reg, if MODE is just one byte. Actually, on the ns32k,
-   since the index mode is independent of the operand size,
-   we can match more stuff...
-
-   This macro's expansion uses the temporary variables xfoo0, xfoo1
-   and xfoo2 that must be declared in the surrounding context.  */
-#define INDEX_TERM_P(PROD, MODE)   \
-((GET_CODE (PROD) == REG && REG_OK_FOR_INDEX_P (PROD))			\
- || (GET_CODE (PROD) == MULT						\
-     &&	(xfoo0 = XEXP (PROD, 0), xfoo1 = XEXP (PROD, 1),		\
-	 (GET_CODE (xfoo1) == CONST_INT					\
-	  && GET_CODE (xfoo0) == REG					\
-	  && FITS_INDEX_RANGE (INTVAL (xfoo1))				\
-	  && REG_OK_FOR_INDEX_P (xfoo0)))))
-
-#define FITS_INDEX_RANGE(X)  \
-  ((xfoo2 = (unsigned)(X)-1),						\
-   ((xfoo2 < 4 && xfoo2 != 2) || xfoo2 == 7))
-
-/* Note that xfoo0, xfoo1, xfoo2 are used in some of the submacros above.  */
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ register rtx xfooy, xfoo0, xfoo1;					\
-  unsigned xfoo2;							\
-  extern int current_function_uses_pic_offset_table, flag_pic;		\
-  xfooy = X;								\
-  if (flag_pic && ! current_function_uses_pic_offset_table		\
-      && global_symbolic_reference_mentioned_p (X, 1))			\
-    current_function_uses_pic_offset_table = 1;				\
-  GO_IF_NONINDEXED_ADDRESS (xfooy, ADDR);				\
-  if (GET_CODE (xfooy) == PLUS)						\
-    {									\
-      if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfooy, 1))			\
-	  && GET_CODE (XEXP (xfooy, 0)) == PLUS)			\
-	xfooy = XEXP (xfooy, 0);					\
-      else if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfooy, 0))		\
-	  && GET_CODE (XEXP (xfooy, 1)) == PLUS)			\
-	xfooy = XEXP (xfooy, 1);					\
-      GO_IF_INDEXING (xfooy, MODE, ADDR);				\
-    }									\
-  else if (INDEX_TERM_P (xfooy, MODE))					\
-    goto ADDR;								\
-  else if (GET_CODE (xfooy) == PRE_DEC)					\
-    if (REGNO (XEXP (xfooy, 0)) == STACK_POINTER_REGNUM) goto ADDR;	\
-  else abort ();							\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the ns32k, we do nothing */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)   {}
-
-/* Nonzero if the constant value X is a legitimate general operand
-   when generating PIC code.  It is given that flag_pic is on and
-   that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-extern int current_function_uses_pic_offset_table, flag_pic;
-#define LEGITIMATE_PIC_OPERAND_P(X) \
-  (((! current_function_uses_pic_offset_table			\
-     && symbolic_reference_mentioned_p (X))?			\
-      (current_function_uses_pic_offset_table = 1):0		\
-   ), (! SYMBOLIC_CONST (X)					\
-   || GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF))
-
-#define SYMBOLIC_CONST(X)	\
-(GET_CODE (X) == SYMBOL_REF						\
- || GET_CODE (X) == LABEL_REF						\
- || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
-
-/* Define this macro if references to a symbol must be treated
-   differently depending on something about the variable or
-   function named by the symbol (such as what section it is in).
-
-   On the ns32k, if using PIC, mark a SYMBOL_REF for a non-global
-   symbol or a code symbol. These symbols are referenced via pc
-   and not via sb. */
-
-#define ENCODE_SECTION_INFO(DECL) \
-do									\
-  {									\
-    extern int flag_pic;						\
-    if (flag_pic)							\
-      {									\
-	rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd'		\
-		   ? TREE_CST_RTL (DECL) : DECL_RTL (DECL));		\
-	SYMBOL_REF_FLAG (XEXP (rtl, 0))					\
-	  = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd'			\
-	     || ! TREE_PUBLIC (DECL));					\
-      }									\
-  }									\
-while (0)
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the ns32k, only predecrement and postincrement address depend thus
-   (the amount of decrement or increment being the length of the operand).  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
- { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC)	\
-     goto LABEL;}
-
-/* If defined, a C expression whose value is nonzero if IDENTIFIER
-   with arguments ARGS is a valid machine specific attribute for DECL.
-   The attributes in ATTRIBUTES have previously been assigned to DECL.  */
-
-#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, NAME, ARGS) \
-  (ns32k_valid_decl_attribute_p (DECL, ATTRIBUTES, NAME, ARGS))
-
-/* If defined, a C expression whose value is nonzero if IDENTIFIER
-   with arguments ARGS is a valid machine specific attribute for TYPE.
-   The attributes in ATTRIBUTES have previously been assigned to TYPE.  */
-
-#define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
-  (ns32k_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
-
-/* If defined, a C expression whose value is zero if the attributes on
-   TYPE1 and TYPE2 are incompatible, one if they are compatible, and
-   two if they are nearly compatible (which causes a warning to be
-   generated).  */
-
-#define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
-  (ns32k_comp_type_attributes (TYPE1, TYPE2))
-
-/* If defined, a C statement that assigns default attributes to newly
-   defined TYPE.  */
-
-/* #define SET_DEFAULT_TYPE_ATTRIBUTES (TYPE) */
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.
-   HI mode is more efficient but the range is not wide enough for
-   all programs. */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE 1
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 4
-
-/* The number of scalar move insns which should be generated instead
-   of a string move insn or a library call.
-   
-   We have a smart movstrsi insn */
-#define MOVE_RATIO 0
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of address ADDRESS. */
-
-#define ADDRESS_COST(RTX) calc_address_cost (RTX)
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    if (INTVAL (RTX) <= 7 && INTVAL (RTX) >= -8) return 0;	\
-    if (INTVAL (RTX) < 0x2000 && INTVAL (RTX) >= -0x2000)	\
-      return 1;							\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 3;							\
-  case CONST_DOUBLE:						\
-    return 5;
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  */
-
-/* This bit means that what ought to be in the Z bit
-   should be tested in the F bit.  */
-#define CC_Z_IN_F 04000
-
-/* This bit means that what ought to be in the Z bit
-   is complemented in the F bit.  */
-#define CC_Z_IN_NOT_F 010000
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-{ if (GET_CODE (EXP) == SET)					\
-    { if (GET_CODE (SET_DEST (EXP)) == CC0)			\
-	{ cc_status.flags = 0;					\
-	  cc_status.value1 = SET_DEST (EXP);			\
-	  cc_status.value2 = SET_SRC (EXP);			\
-	}							\
-      else if (GET_CODE (SET_SRC (EXP)) == CALL)		\
-	{ CC_STATUS_INIT; }					\
-      else if (GET_CODE (SET_DEST (EXP)) == REG)		\
-	{ if (cc_status.value1					\
-	      && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value1)) \
-	    cc_status.value1 = 0;				\
-	  if (cc_status.value2					\
-	      && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value2)) \
-	    cc_status.value2 = 0;				\
-	}							\
-      else if (GET_CODE (SET_DEST (EXP)) == MEM)		\
-	{ CC_STATUS_INIT; }					\
-    }								\
-  else if (GET_CODE (EXP) == PARALLEL				\
-	   && GET_CODE (XVECEXP (EXP, 0, 0)) == SET)		\
-    { if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) == CC0)	\
-	{ cc_status.flags = 0;					\
-	  cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0));	\
-	  cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0));	\
-	}							\
-      else if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) == REG) \
-	{ if (cc_status.value1					\
-	      && reg_overlap_mentioned_p (SET_DEST (XVECEXP (EXP, 0, 0)), cc_status.value1)) \
-	    cc_status.value1 = 0;				\
-	  if (cc_status.value2					\
-	      && reg_overlap_mentioned_p (SET_DEST (XVECEXP (EXP, 0, 0)), cc_status.value2)) \
-	    cc_status.value2 = 0;				\
-	}							\
-      else if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) == MEM) \
-	{ CC_STATUS_INIT; }					\
-    }								\
-  else if (GET_CODE (EXP) == CALL)				\
-    { /* all bets are off */ CC_STATUS_INIT; }			\
-  else { /* nothing happens? CC_STATUS_INIT; */}		\
-  if (cc_status.value1 && GET_CODE (cc_status.value1) == REG	\
-      && cc_status.value2					\
-      && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))	\
-    abort ();			\
-}
-
-/* Describe the costs of the following register moves which are discouraged:
-   1.) Moves between the Floating point registers and the frame pointer and stack pointer
-   2.) Moves between the stack pointer and the frame pointer
-   3.) Moves between the floating point and general registers
-
-  These all involve two memory references. This is worse than a memory
-  to memory move (default cost 4)
- */
-
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)  register_move_cost(CLASS1, CLASS2)
-
-#define OUTPUT_JUMP(NORMAL, NO_OV)  \
-{ if (cc_status.flags & CC_NO_OVERFLOW)				\
-    return NO_OV;						\
-  return NORMAL; }
-
-/* Dividing the output into sections */
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* Define the output Assembly Language */
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(FILE) fprintf (FILE, "#NO_APP\n");
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* Output of Data */
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-  fprintf (FILE, "\t.double 0d%.20e\n", (VALUE))
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-  fprintf (FILE, "\t.float 0f%.20e\n", (VALUE))
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* This is how to output an assembler line defining an external/static
-   address which is not in tree format (for collect.c).  */
-
-/* The prefix to add to user-visible assembler symbols. */
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tmovd %s,tos\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tmovd tos,%s\n", reg_names[REGNO])
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#ifndef COLLECT
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-#else
-#define ASM_OUTPUT_LABEL(STREAM,NAME)					\
-do {									\
-  fprintf (STREAM, "%s:\n", NAME);					\
-} while (0)
-#endif
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#ifndef COLLECT
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-#else
-#define ASM_GLOBALIZE_LABEL(STREAM,NAME)				\
-do {									\
-  fprintf (STREAM, "\t.globl\t%s\n", NAME);				\
-} while (0)
-#endif
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-
-#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
-  fprintf (FILE, "_%s", NAME)
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to align the code that follows an unconditional branch.  */
-
-#define LABEL_ALIGN_AFTER_BARRIER(LABEL) (2)
-
-/* This is how to output an element of a case-vector that is absolute.
-   (The ns32k does not use such vectors,
-   but we must define this macro anyway.)  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.long L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-/* ** Notice that the second element is LI format! */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.long L%d-LI%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
-  fprintf (FILE, "\t.align %d\n", (LOG))
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %u\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print an instruction operand X on file FILE.
-   CODE is the code from the %-spec that requested printing this operand;
-   if `%z3' was used to print operand 3, then CODE is 'z'. */
-
-/* %$ means print the prefix for an immediate operand.  */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)				\
-  ((CODE) == '$' || (CODE) == '?')
-
-#define PRINT_OPERAND(FILE, X, CODE)       print_operand(FILE, X, CODE)
-
-/* Print a memory operand whose address is X, on file FILE.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE, ADDR)
-
-/* Prototypes for functions in ns32k.c */
-
-/* Prototypes would be nice, but for now it causes too many problems.
-   This file gets included in places where the types (such as "rtx"
-   and enum machine_mode) are not defined. */
-#define NS32K_PROTO(ARGS) ()
-
-int hard_regno_mode_ok NS32K_PROTO((int regno, enum machine_mode mode));
-int register_move_cost NS32K_PROTO((enum reg_class CLASS1, enum reg_class CLASS2));
-int calc_address_cost NS32K_PROTO((rtx operand));
-enum reg_class secondary_reload_class NS32K_PROTO((enum reg_class class,
-					     enum machine_mode mode, rtx in));
-int reg_or_mem_operand NS32K_PROTO((register rtx op, enum machine_mode mode));
-
-void split_di NS32K_PROTO((rtx operands[], int num, rtx lo_half[], hi_half[]));
-
-void expand_block_move NS32K_PROTO((rtx operands[]));
-int global_symbolic_reference_mentioned_p NS32K_PROTO((rtx op, int f));
-int ns32k_comp_type_attributes NS32K_PROTO((tree type1, tree type2));
-int ns32k_return_pops_args NS32K_PROTO((tree fundecl, tree funtype, int size));
-int ns32k_valid_decl_attribute_p NS32K_PROTO((tree decl, tree attributes,
-						tree identifier, tree args));
-int ns32k_valid_type_attribute_p NS32K_PROTO((tree decl, tree attributes,
-						tree identifier, tree args));
-void print_operand NS32K_PROTO((FILE *file, rtx x, char code));
-void print_operand_address NS32K_PROTO((register FILE *file, register rtx addr));
-char *output_move_dconst NS32K_PROTO((int n, char *s));
-char *output_move_double NS32K_PROTO((rtx *operands));
-char *output_shift_insn NS32K_PROTO((rtx *operands));
-
-extern unsigned int ns32k_reg_class_contents[N_REG_CLASSES];
-extern char *ns32k_out_reg_names[];
-extern enum reg_class regclass_map[];		/* smalled class containing REGNO */
-
-/*
-Local variables:
-version-control: t
-End:
-*/
diff --git a/gcc/config/ns32k/ns32k.md b/gcc/config/ns32k/ns32k.md
deleted file mode 100755
index 161b74e..0000000
--- a/gcc/config/ns32k/ns32k.md
+++ /dev/null
@@ -1,3058 +0,0 @@
-;;- Machine description for GNU compiler, ns32000 Version
-;;  Copyright (C) 1988, 1994, 1996 Free Software Foundation, Inc.
-;;  Contributed by Michael Tiemann (tiemann@cygnus.com)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-; BUGS:
-;; Insert no-op between an insn with memory read-write operands
-;;   following by a scale-indexing operation.
-;; The Sequent assembler does not allow addresses to be used
-;;   except in insns which explicitly compute an effective address.
-;;   I.e., one cannot say "cmpd _p,@_x"
-;; Implement unsigned multiplication??
-
-;;- Instruction patterns.  When multiple patterns apply,
-;;- the first one in the file is chosen.
-;;-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-;;-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
-;; be folded while optimizing anyway.
-;;
-;; In order for pic mode to work we cannot generate, for example
-;;
-;;   addd _x+5,r1
-;;
-;; instead we must force gcc to generate something like
-;;
-;;   addr 5(_x(sb)),r0
-;;   addd r0,r1
-;;
-;; This was done through operand constraints (using "rmn" in place of "g"),
-;; but with the proper definition of LEGITIMATE_PIC_OPERAND (ns32k.h)
-;; this is unnecessary.
-;;
-(define_insn "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "nonimmediate_operand" "rm"))]
-  ""
-  "*
-{ cc_status.flags |= CC_REVERSED;
-  operands[1] = const0_rtx;
-  return \"cmpqd %1,%0\"; }")
-
-(define_insn "tsthi"
-  [(set (cc0)
-	(match_operand:HI 0 "nonimmediate_operand" "g"))]
-  ""
-  "*
-{ cc_status.flags |= CC_REVERSED;
-  operands[1] = const0_rtx;
-  return \"cmpqw %1,%0\"; }")
-
-(define_insn "tstqi"
-  [(set (cc0)
-	(match_operand:QI 0 "nonimmediate_operand" "g"))]
-  ""
-  "*
-{ cc_status.flags |= CC_REVERSED;
-  operands[1] = const0_rtx;
-  return \"cmpqb %1,%0\"; }")
-
-(define_insn "tstdf"
-  [(set (cc0)
-	(match_operand:DF 0 "general_operand" "lmF"))]
-  "TARGET_32081"
-  "*
-{ cc_status.flags |= CC_REVERSED;
-  operands[1] = CONST0_RTX (DFmode);
-  return \"cmpl %1,%0\"; }")
-
-(define_insn "tstsf"
-  [(set (cc0)
-	(match_operand:SF 0 "general_operand" "fmF"))]
-  "TARGET_32081"
-  "*
-{ cc_status.flags |= CC_REVERSED;
-  operands[1] = CONST0_RTX (SFmode);
-  return \"cmpf %1,%0\"; }")
-
-;; See note 1
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "general_operand" "g")
-		 (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      int i = INTVAL (operands[1]);
-      if (i <= 7 && i >= -8)
-	{
-	  cc_status.flags |= CC_REVERSED;
-	  return \"cmpqd %1,%0\";
-	}
-    }
-  cc_status.flags &= ~CC_REVERSED;
-  if (GET_CODE (operands[0]) == CONST_INT)
-    {
-      int i = INTVAL (operands[0]);
-      if (i <= 7 && i >= -8)
-	return \"cmpqd %0,%1\";
-    }
-  return \"cmpd %0,%1\";
-}")
-
-(define_insn "cmphi"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "general_operand" "g")
-		 (match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      short i = INTVAL (operands[1]);
-    if (i <= 7 && i >= -8)
-      {
-	cc_status.flags |= CC_REVERSED;
-	if (INTVAL (operands[1]) > 7)
-	  operands[1] = GEN_INT (i);
-	return \"cmpqw %1,%0\";
-      }
-    }
-  cc_status.flags &= ~CC_REVERSED;
-  if (GET_CODE (operands[0]) == CONST_INT)
-    {
-      short i = INTVAL (operands[0]);
-      if (i <= 7 && i >= -8)
-	{
-	  if (INTVAL (operands[0]) > 7)
-	    operands[0] = GEN_INT (i);
-	  return \"cmpqw %0,%1\";
-	}
-    }
-  return \"cmpw %0,%1\";
-}")
-
-(define_insn "cmpqi"
-  [(set (cc0)
-	(compare (match_operand:QI 0 "general_operand" "g")
-		 (match_operand:QI 1 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      char i = INTVAL (operands[1]);
-      if (i <= 7 && i >= -8)
-	{
-	  cc_status.flags |= CC_REVERSED;
-	  if (INTVAL (operands[1]) > 7)
-	    operands[1] = GEN_INT (i);
-	  return \"cmpqb %1,%0\";
-	}
-    }
-  cc_status.flags &= ~CC_REVERSED;
-  if (GET_CODE (operands[0]) == CONST_INT)
-    {
-      char i = INTVAL (operands[0]);
-      if (i <= 7 && i >= -8)
-	{
-	  if (INTVAL (operands[0]) > 7)
-	    operands[0] = GEN_INT (i);
-	  return \"cmpqb %0,%1\";
-	}
-    }
-  return \"cmpb %0,%1\";
-}")
-
-(define_insn "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "general_operand" "lmF")
-		 (match_operand:DF 1 "general_operand" "lmF")))]
-  "TARGET_32081"
-  "cmpl %0,%1")
-
-(define_insn "cmpsf"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "general_operand" "fmF")
-		 (match_operand:SF 1 "general_operand" "fmF")))]
-  "TARGET_32081"
-  "cmpf %0,%1")
-
-;; movdf and movsf copy between general and floating registers using
-;; the stack. In principle, we could get better code not allowing
-;; that case in the constraints and defining SECONDARY_MEMORY_NEEDED
-;; in practice, though the stack slots used are not available for
-;; optimization.
-(define_insn "movdf"
-  [(set (match_operand:DF 0 "general_operand" "=lg<")
-	(match_operand:DF 1 "general_operand" "lFg"))]
-  ""
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
-	return \"movl %1,%0\";
-      if (REG_P (operands[1]))
-	{
-	  rtx xoperands[2];
-	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"movd %1,tos\", xoperands);
-	  output_asm_insn (\"movd %1,tos\", operands);
-	  return \"movl tos,%0\";
-	}
-      return \"movl %1,%0\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	{
-	  output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
-	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-	  return \"movd tos,%0\";
-	}
-      else
-        return \"movl %1,%0\";
-    }
-  return output_move_double (operands);
-}")
-
-(define_insn "movsf"
-  [(set (match_operand:SF 0 "general_operand" "=fg<")
-	(match_operand:SF 1 "general_operand" "fFg"))]
-  ""
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    {
-      if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
-	return \"movd %1,tos\;movf tos,%0\";
-      else
-	return \"movf %1,%0\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	return \"movf %1,tos\;movd tos,%0\";
-      return \"movf %1,%0\";
-    }
-#if 0 /* Someone suggested this for the Sequent.  Is it needed?  */
-  else if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    return \"movf %1,%0\";
-#endif
-/* There was a #if 0 around this, but that was erroneous
-   for many machines -- rms.  */
-#ifndef MOVD_FLOAT_OK
-  /* GAS understands floating constants in ordinary movd instructions
-     but other assemblers might object.  */
-  else if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    {
-      union {int i[2]; float f; double d;} convrt;
-      convrt.i[0] = CONST_DOUBLE_LOW (operands[1]);
-      convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]);
-      convrt.f = convrt.d;
-
-      /* Is there a better machine-independent way to do this?  */
-      operands[1] = GEN_INT (convrt.i[0]);
-      return \"movd %1,%0\";
-    }
-#endif
-  else return \"movd %1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:TI 0 "memory_operand" "=m")
-	(match_operand:TI 1 "memory_operand" "m"))]
-  ""
-  "movmd %1,%0,4")
-
-(define_insn "movdi"
-  [(set (match_operand:DI 0 "general_operand" "=g<,*f,g")
-	(match_operand:DI 1 "general_operand" "gF,g,*f"))]
-  ""
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
-	return \"movl %1,%0\";
-      if (REG_P (operands[1]))
-	{
-	  rtx xoperands[2];
-	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-	  output_asm_insn (\"movd %1,tos\", xoperands);
-	  output_asm_insn (\"movd %1,tos\", operands);
-	  return \"movl tos,%0\";
-	}
-      return \"movl %1,%0\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	{
-	  output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
-	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-	  return \"movd tos,%0\";
-	}
-      else
-        return \"movl %1,%0\";
-    }
-  return output_move_double (operands);
-}")
-
-;; This special case must precede movsi.
-(define_insn ""
-  [(set (reg:SI 25)
-	(match_operand:SI 0 "general_operand" "g"))]
-  ""
-  "lprd sp,%0")
-
-(define_insn "movsi"
-  [(set (match_operand:SI 0 "general_operand" "=g<,g<,*f,g,x")
-	(match_operand:SI 1 "general_operand" "g,?xy,g,*f,rmn"))]
-  ""
-  "*
-{
-  extern int flag_pic;						\
-
-  if (FP_REG_P (operands[0]))
-    {
-      if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
-	return \"movd %1,tos\;movf tos,%0\";
-      else
-	return \"movf %1,%0\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	return \"movf %1,tos\;movd tos,%0\";
-      return \"movf %1,%0\";
-    }
-  if (GET_CODE (operands[0]) == REG
-      && REGNO (operands[0]) == FRAME_POINTER_REGNUM)
-    return \"lprd fp,%1\";
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    operands[1]
-      = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      int i = INTVAL (operands[1]);
-      if (! TARGET_32532)
-	{
-	  if (i <= 7 && i >= -8)
-	    return \"movqd %1,%0\";
-	  if (NS32K_DISPLACEMENT_P (i))
-#if defined (GNX_V3) || defined (UTEK_ASM)
-	    return \"addr %c1,%0\";
-#else
-	    return \"addr @%c1,%0\";
-#endif
-	  return \"movd %1,%0\";
-	}
-      else
-        return output_move_dconst(i, \"%1,%0\");
-    }
-  else if (GET_CODE (operands[1]) == CONST && ! flag_pic)
-    {
-	/* Must contain symbols so we don`t know how big it is. In
-	 * that case addr might lead to overflow. For PIC symbolic
-	 * address loads always have to be done with addr.
-	 */
-	return \"movd %1,%0\";
-    }
-  else if (GET_CODE (operands[1]) == REG)
-    {
-      if (REGNO (operands[1]) < F0_REGNUM)
-        return \"movd %1,%0\";
-      else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM)
-	{
-	  if (GET_CODE(operands[0]) == REG)
-	    return \"sprd fp,%0\";
-	  else
-	    return \"addr 0(fp),%0\" ;
-	}
-      else if (REGNO (operands[1]) == STACK_POINTER_REGNUM)
-	{
-	  if (GET_CODE(operands[0]) == REG)
-	    return \"sprd sp,%0\";
-	  else
-	    return \"addr 0(sp),%0\" ;
-	}
-      else abort ();
-    }
-  else if (GET_CODE (operands[1]) == MEM)
-    return \"movd %1,%0\";
-
-  /* Check if this effective address can be
-     calculated faster by pulling it apart.  */
-  if (REG_P (operands[0])
-      && GET_CODE (operands[1]) == MULT
-      && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
-      && (INTVAL (XEXP (operands[1], 1)) == 2
-	  || INTVAL (XEXP (operands[1], 1)) == 4))
-    {
-      rtx xoperands[3];
-      xoperands[0] = operands[0];
-      xoperands[1] = XEXP (operands[1], 0);
-      xoperands[2] = GEN_INT (INTVAL (XEXP (operands[1], 1)) >> 1);
-      return output_shift_insn (xoperands);
-    }
-  return \"addr %a1,%0\";
-}")
-
-(define_insn "movhi"
-  [(set (match_operand:HI 0 "general_operand" "=g<,*f,g")
-	(match_operand:HI 1 "general_operand" "g,g,*f"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      short i = INTVAL (operands[1]);
-      if (i <= 7 && i >= -8)
-	{
-	  if (INTVAL (operands[1]) > 7)
-	    operands[1] =
-	      GEN_INT (i);
-	  return \"movqw %1,%0\";
-	}
-	return \"movw %1,%0\";
-    }
-  else if (FP_REG_P (operands[0]))
-    {
-      if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
-	return \"movwf %1,tos\;movf tos,%0\";
-      else
-	return \"movwf %1,%0\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	return \"movf %1,tos\;movd tos,%0\";
-      return \"movf %1,%0\";
-    }
-  else
-     return \"movw %1,%0\";
-}")
-
-(define_insn "movstricthi"
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
-	(match_operand:HI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
-    return \"movqw %1,%0\";
-  return \"movw %1,%0\";
-}")
-
-(define_insn "movqi"
-  [(set (match_operand:QI 0 "general_operand" "=g<,*f,g")
-	(match_operand:QI 1 "general_operand" "g,g,*f"))]
-  ""
-  "*
-{ if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      char char_val = (char)INTVAL (operands[1]);
-      if (char_val <= 7 && char_val >= -8)
-	{
-	  if (INTVAL (operands[1]) > 7)
-	    operands[1] =
-	      GEN_INT (char_val);
-	  return \"movqb %1,%0\";
-	}
-	return \"movb %1,%0\";
-    }
-  else if (FP_REG_P (operands[0]))
-    {
-      if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
-	return \"movbf %1,tos\;movf tos,%0\";
-      else
-	return \"movbf %1,%0\";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      if (REG_P (operands[0]))
-	return \"movf %1,tos\;movd tos,%0\";
-      return \"movf %1,%0\";
-    }
-  else
-     return \"movb %1,%0\";
-}")
-
-(define_insn "movstrictqi"
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
-	(match_operand:QI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
-    return \"movqb %1,%0\";
-  return \"movb %1,%0\";
-}")
-
-;; Block moves
-;; Argument 0 is the destination
-;; Argument 1 is the source
-;; Argument 2 is the length
-;; Argument 3 is the alignment
-;;
-;; Strategy: Use define_expand to
-;; either emit insns directly if it can be done simply or
-;; emit rtl to match movstrsi1 which has extra scratch registers
-;; which can be used to generate more complex code.
-
-(define_expand "movstrsi"
-  [(parallel [(set (match_operand:BLK 0 "general_operand" "")
-		   (match_operand:BLK 1 "general_operand" ""))
-	      (use (match_operand:SI 2 "general_operand" ""))
-	      (use (match_operand:SI 3 "const_int_operand" ""))])]
-  ""
-  "
-{
-  if (operands[0])		/* avoid unused code messages */
-    {
-      expand_block_move (operands);
-      DONE;
-    }
-}")
-
-;; Special Registers:
-;; r0  count
-;; r1  from 
-;; r2  to   
-;; r3  match
-
-
-(define_insn "movstrsi1"
-  [(set (mem:BLK (reg:SI 2))
-	(mem:BLK (reg:SI 1)))
-   (use (reg:SI 0))
-   (set (reg:SI 2) (plus:SI (reg:SI 2) (mult:SI (reg:SI 0) (match_operand:SI 0 "const_int_operand" ""))))
-   (set (reg:SI 1) (plus:SI (reg:SI 1) (mult:SI (reg:SI 0) (match_dup 0))))
-   (set (reg:SI 0) (const_int 0))]
-  ""
-  "*
-  {
-     int align = INTVAL(operands[0]);
-     if (align == 4)
-       return \"movsd\";
-     else
-       return \"movsb\";
-  }")
-
-(define_insn "movstrsi2"
-  [(set (mem:BLK (match_operand:SI 0 "address_operand" "g"))
-	(mem:BLK (match_operand:SI 1 "address_operand" "g")))
-   (use (match_operand 2 "immediate_operand" "i"))]
-  ""
-  "movmd %a1,%a0,%2")
-
-
-;; Extension and truncation insns.
-;; Those for integer source operand
-;; are ordered widest source type first.
-
-(define_insn "truncsiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
-  ""
-  "movb %1,%0")
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
-  ""
-  "movw %1,%0")
-
-(define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
-  ""
-  "movb %1,%0")
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
-  ""
-  "movxwd %1,%0")
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
-  ""
-  "movxbw %1,%0")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
-  ""
-  "movxbd %1,%0")
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "general_operand" "=lm<")
-	(float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
-  "TARGET_32081"
-  "movfl %1,%0")
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "general_operand" "=fm<")
-	(float_truncate:SF (match_operand:DF 1 "general_operand" "lmF")))]
-  "TARGET_32081"
-  "movlf %1,%0")
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
-  ""
-  "movzwd %1,%0")
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
-  ""
-  "movzbw %1,%0")
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
-  ""
-  "movzbd %1,%0")
-
-;; Fix-to-float conversion insns.
-;; Note that the ones that start with SImode come first.
-;; That is so that an operand that is a CONST_INT
-;; (and therefore lacks a specific machine mode).
-;; will be recognized as SImode (which is always valid)
-;; rather than as QImode or HImode.
-
-;; Rumor has it that the National part does not correctly convert
-;; constant ints to floats.  This conversion is therefore disabled.
-;; A register must be used to perform the conversion.
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "general_operand" "=fm<")
-	(float:SF (match_operand:SI 1 "general_operand" "rm")))]
-  "TARGET_32081"
-  "movdf %1,%0")
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "general_operand" "=lm<")
-	(float:DF (match_operand:SI 1 "general_operand" "rm")))]
-  "TARGET_32081"
-  "movdl %1,%0")
-
-(define_insn "floathisf2"
-  [(set (match_operand:SF 0 "general_operand" "=fm<")
-	(float:SF (match_operand:HI 1 "general_operand" "rm")))]
-  "TARGET_32081"
-  "movwf %1,%0")
-
-(define_insn "floathidf2"
-  [(set (match_operand:DF 0 "general_operand" "=lm<")
-	(float:DF (match_operand:HI 1 "general_operand" "rm")))]
-  "TARGET_32081"
-  "movwl %1,%0")
-
-(define_insn "floatqisf2"
-  [(set (match_operand:SF 0 "general_operand" "=fm<")
-	(float:SF (match_operand:QI 1 "general_operand" "rm")))]
-  "TARGET_32081"
-  "movbf %1,%0")
-
-; Some assemblers warn that this insn doesn't work.
-; Maybe they know something we don't.
-;(define_insn "floatqidf2"
-;  [(set (match_operand:DF 0 "general_operand" "=lm<")
-;	(float:DF (match_operand:QI 1 "general_operand" "rm")))]
-;  "TARGET_32081"
-;  "movbl %1,%0")
-
-;; Float-to-fix conversion insns.
-;; The sequent compiler always generates "trunc" insns.
-
-(define_insn "fixsfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
-  "TARGET_32081"
-  "truncfb %1,%0")
-
-(define_insn "fixsfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
-  "TARGET_32081"
-  "truncfw %1,%0")
-
-(define_insn "fixsfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
-  "TARGET_32081"
-  "truncfd %1,%0")
-
-(define_insn "fixdfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(fix:QI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
-  "TARGET_32081"
-  "trunclb %1,%0")
-
-(define_insn "fixdfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(fix:HI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
-  "TARGET_32081"
-  "trunclw %1,%0")
-
-(define_insn "fixdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(fix:SI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
-  "TARGET_32081"
-  "truncld %1,%0")
-
-;; Unsigned
-
-(define_insn "fixunssfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
-  "TARGET_32081"
-  "truncfb %1,%0")
-
-(define_insn "fixunssfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
-  "TARGET_32081"
-  "truncfw %1,%0")
-
-(define_insn "fixunssfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
-  "TARGET_32081"
-  "truncfd %1,%0")
-
-(define_insn "fixunsdfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
-  "TARGET_32081"
-  "trunclb %1,%0")
-
-(define_insn "fixunsdfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
-  "TARGET_32081"
-  "trunclw %1,%0")
-
-(define_insn "fixunsdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
-  "TARGET_32081"
-  "truncld %1,%0")
-
-;;; These are not yet used by GCC
-(define_insn "fix_truncsfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(fix:QI (match_operand:SF 1 "general_operand" "fm")))]
-  "TARGET_32081"
-  "truncfb %1,%0")
-
-(define_insn "fix_truncsfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(fix:HI (match_operand:SF 1 "general_operand" "fm")))]
-  "TARGET_32081"
-  "truncfw %1,%0")
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(fix:SI (match_operand:SF 1 "general_operand" "fm")))]
-  "TARGET_32081"
-  "truncfd %1,%0")
-
-(define_insn "fix_truncdfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(fix:QI (match_operand:DF 1 "general_operand" "lm")))]
-  "TARGET_32081"
-  "trunclb %1,%0")
-
-(define_insn "fix_truncdfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(fix:HI (match_operand:DF 1 "general_operand" "lm")))]
-  "TARGET_32081"
-  "trunclw %1,%0")
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(fix:SI (match_operand:DF 1 "general_operand" "lm")))]
-  "TARGET_32081"
-  "truncld %1,%0")
-
-;; Multiply-add instructions
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=v,v")
-	(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
-		          (match_operand:DF 2 "general_operand" "lmF,lmF"))
-                 (match_operand:DF 3 "general_operand" "0,lmF")))]
-  "TARGET_MULT_ADD"
-  "@
-   dotl %1,%2
-   polyl %2,%3")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=u,u")
-	(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
-		          (match_operand:SF 2 "general_operand" "fmF,fmF"))
-                 (match_operand:SF 3 "general_operand" "0,fmF")))]
-  "TARGET_MULT_ADD"
-  "@
-   dotf %1,%2
-   polyf %2,%3")
-
-
-;; Multiply-sub instructions
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=v")
-	(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF")
-		          (match_operand:DF 2 "general_operand" "lmF"))
-                 (match_operand:DF 3 "general_operand" "0")))]
-  "TARGET_MULT_ADD"
-  "@
-   negl %0,%0\;dotl %1,%2")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=u")
-	(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF")
-		          (match_operand:SF 2 "general_operand" "fmF"))
-                 (match_operand:SF 3 "general_operand" "0")))]
-  "TARGET_MULT_ADD"
-  "@
-   negf %0,%0\;dotf %1,%2")
-
-;;- All kinds of add instructions.
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "general_operand" "=lm")
-	(plus:DF (match_operand:DF 1 "general_operand" "%0")
-		 (match_operand:DF 2 "general_operand" "lmF")))]
-  "TARGET_32081"
-  "addl %2,%0")
-
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "general_operand" "=fm")
-	(plus:SF (match_operand:SF 1 "general_operand" "%0")
-		 (match_operand:SF 2 "general_operand" "fmF")))]
-  "TARGET_32081"
-  "addf %2,%0")
-
-(define_insn ""
-  [(set (reg:SI 25)
-	(plus:SI (reg:SI 25)
-		 (match_operand:SI 0 "immediate_operand" "i")))]
-  "GET_CODE (operands[0]) == CONST_INT"
-  "*
-{
-#ifndef SEQUENT_ADJUST_STACK
-  if (TARGET_32532)
-    if (INTVAL (operands[0]) == 8)
-      return \"cmpd tos,tos\";
-  if (TARGET_32532 || TARGET_32332)
-    if (INTVAL (operands[0]) == 4)
-      return \"cmpqd %$0,tos\";
-#endif
-  if (! TARGET_32532)
-    {
-      if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64)
-        return \"adjspb %n0\";
-      else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
-        return \"adjspw %n0\";
-    }
-  return \"adjspd %n0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(plus:SI (reg:SI 24)
-		 (match_operand:SI 1 "immediate_operand" "i")))]
-  "GET_CODE (operands[1]) == CONST_INT"
-  "addr %c1(fp),%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(plus:SI (reg:SI 25)
-		 (match_operand:SI 1 "immediate_operand" "i")))]
-  "GET_CODE (operands[1]) == CONST_INT"
-  "addr %c1(sp),%0")
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "general_operand" "=ro")
-	(plus:DI (match_operand:DI 1 "general_operand" "%0")
-		 (match_operand:DI 2 "general_operand" "ron")))]
-  ""
-  "*
-{
-  rtx low[3], high[3], xops[4];
-  split_di (operands, 3, low, high);
-  xops[0] = low[0];
-  xops[1] = high[0];
-  xops[2] = low[2];
-  xops[3] = high[2];
-
-  if (GET_CODE (xops[2]) == CONST_INT)
-    {
-      int i = INTVAL (xops[2]);
-
-      if (i <= 7 && i >= -8) 
-        {
-          if (i == 0)
-	    {
-	      i = INTVAL (xops[3]);
-	      if (i <= 7 && i >= -8)
-                output_asm_insn (\"addqd %3,%1\", xops);
-	      else
-                output_asm_insn (\"addd %3,%1\", xops);
-	    }
-	  else
-	    {
-              output_asm_insn (\"addqd %2,%0\", xops);
-              output_asm_insn (\"addcd %3,%1\", xops);
-	    }
-	  return \"\";
-	}
-    }
-  output_asm_insn (\"addd %2,%0\", xops);
-  output_asm_insn (\"addcd %3,%1\", xops);
-  return \"\";
-}")
-
-;; See Note 1
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g,=g&<")
-	(plus:SI (match_operand:SI 1 "general_operand" "%0,r")
-		 (match_operand:SI 2 "general_operand" "g,i")))]
-  ""
-  "*
-{
-  if (which_alternative == 1)
-    {
-      if (GET_CODE (operands[2]) == CONST_INT)
-        {
-	  int i = INTVAL (operands[2]);
-	  if (NS32K_DISPLACEMENT_P (i))
-	    return \"addr %c2(%1),%0\";
-	  else
-	    return \"movd %1,%0\;addd %2,%0\";
-        }
-      else
-        {
-          if (flag_pic) 
-            return \"addr %a2[%1:b],%0\";
-	  else
-	    return \"addr %c2(%1),%0\";
-        }
-    }
-  else if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-
-      if (i <= 7 && i >= -8)
-	return \"addqd %2,%0\";
-      else if (! TARGET_32532 && GET_CODE (operands[0]) == REG
-	       && NS32K_DISPLACEMENT_P (i))
-	return \"addr %c2(%0),%0\";
-    }
-  return \"addd %2,%0\";
-}")
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(plus:HI (match_operand:HI 1 "general_operand" "%0")
-		 (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{ if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-      if (i <= 7 && i >= -8)
-	return \"addqw %2,%0\";
-    }
-  return \"addw %2,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
-	(plus:HI (match_operand:HI 1 "general_operand" "0")
-		 (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
-    return \"addqw %2,%0\";
-  return \"addw %2,%0\";
-}")
-
-(define_insn "addqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(plus:QI (match_operand:QI 1 "general_operand" "%0")
-		 (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{ if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-      if (i <= 7 && i >= -8)
-	return \"addqb %2,%0\";
-    }
-  return \"addb %2,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
-	(plus:QI (match_operand:QI 1 "general_operand" "0")
-		 (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
-    return \"addqb %2,%0\";
-  return \"addb %2,%0\";
-}")
-
-;;- All kinds of subtract instructions.
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "general_operand" "=lm")
-	(minus:DF (match_operand:DF 1 "general_operand" "0")
-		  (match_operand:DF 2 "general_operand" "lmF")))]
-  "TARGET_32081"
-  "subl %2,%0")
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "general_operand" "=fm")
-	(minus:SF (match_operand:SF 1 "general_operand" "0")
-		  (match_operand:SF 2 "general_operand" "fmF")))]
-  "TARGET_32081"
-  "subf %2,%0")
-
-(define_insn ""
-  [(set (reg:SI 25)
-	(minus:SI (reg:SI 25)
-		  (match_operand:SI 0 "immediate_operand" "i")))]
-  "GET_CODE (operands[0]) == CONST_INT"
-  "*
-{
-  if (! TARGET_32532 && GET_CODE(operands[0]) == CONST_INT 
-      && INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
-    return \"adjspb %0\";
-  return \"adjspd %0\";
-}")
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "general_operand" "=ro")
-	(minus:DI (match_operand:DI 1 "general_operand" "0")
-		  (match_operand:DI 2 "general_operand" "ron")))]
-  ""
-  "*
-{
-  rtx low[3], high[3], xops[4];
-  split_di (operands, 3, low, high);
-  xops[0] = low[0];
-  xops[1] = high[0];
-  xops[2] = low[2];
-  xops[3] = high[2];
-
-  if (GET_CODE (xops[2]) == CONST_INT)
-    {
-      int i = INTVAL (xops[2]);
-
-      if (i <= 8 && i >= -7)
-        {
-          if (i == 0)
-	    {
-	      i = INTVAL (xops[3]);
-	      if (i <= 8 && i >= -7)
-                output_asm_insn (\"addqd %n3,%1\", xops);
-	      else
-                output_asm_insn (\"subd %3,%1\", xops);
-	    }
-	  else
-	    {
-              output_asm_insn (\"addqd %n2,%0\", xops);
-              output_asm_insn (\"subcd %3,%1\", xops);
-	    }
-	  return \"\";
-	}
-    }
-  output_asm_insn (\"subd %2,%0\", xops);
-  output_asm_insn (\"subcd %3,%1\", xops);
-  return \"\";
-}")
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(minus:SI (match_operand:SI 1 "general_operand" "0")
-		  (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{ if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-
-      if (i <= 8 && i >= -7)
-        return \"addqd %n2,%0\";
-    }
-  return \"subd %2,%0\";
-}")
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(minus:HI (match_operand:HI 1 "general_operand" "0")
-		  (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{ if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-
-      if (i <= 8 && i >= -7)
-        return \"addqw %n2,%0\";
-    }
-  return \"subw %2,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
-	(minus:HI (match_operand:HI 1 "general_operand" "0")
-		  (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
-    return \"addqw %n2,%0\";
-  return \"subw %2,%0\";
-}")
-
-(define_insn "subqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(minus:QI (match_operand:QI 1 "general_operand" "0")
-		  (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{ if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-
-      if (i <= 8 && i >= -7)
-	return \"addqb %n2,%0\";
-    }
-  return \"subb %2,%0\";
-}")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
-	(minus:QI (match_operand:QI 1 "general_operand" "0")
-		  (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
-    return \"addqb %n2,%0\";
-  return \"subb %2,%0\";
-}")
-
-;;- Multiply instructions.
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "general_operand" "=lm")
-	(mult:DF (match_operand:DF 1 "general_operand" "%0")
-		 (match_operand:DF 2 "general_operand" "lmF")))]
-  "TARGET_32081"
-  "mull %2,%0")
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "general_operand" "=fm")
-	(mult:SF (match_operand:SF 1 "general_operand" "%0")
-		 (match_operand:SF 2 "general_operand" "fmF")))]
-  "TARGET_32081"
-  "mulf %2,%0")
-
-;; See note 1
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(mult:SI (match_operand:SI 1 "general_operand" "%0")
-		 (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "muld %2,%0")
-
-(define_insn "mulhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(mult:HI (match_operand:HI 1 "general_operand" "%0")
-		 (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "mulw %2,%0")
-
-(define_insn "mulqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(mult:QI (match_operand:QI 1 "general_operand" "%0")
-		 (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "mulb %2,%0")
-
-(define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "general_operand" "=g")
-	(mult:DI (zero_extend:DI
-		  (match_operand:SI 1 "nonimmediate_operand" "0"))
-		 (zero_extend:DI
-		  (match_operand:SI 2 "nonimmediate_operand" "g"))))]
-  ""
-  "meid %2,%0")
-
-;; divmod insns: We can only do the unsigned case.
-(define_expand "udivmodsi4"
-  [(parallel
-  [(set (match_operand:SI 0 "reg_or_mem_operand" "")
-	(udiv:SI (match_operand:SI 1 "general_operand" "")
-		     (match_operand:SI 2 "general_operand" "")))
-   (set (match_operand:SI 3 "reg_or_mem_operand" "")
-	(umod:SI (match_dup 1) (match_dup 2)))])]
-  ""
-  "
-{
-  rtx temp = gen_reg_rtx(DImode);
-  rtx insn, first, last;
-  first = emit_move_insn(gen_lowpart(SImode, temp), operands[1]);
-  emit_move_insn(gen_highpart(SImode, temp), const0_rtx);
-  emit_insn(gen_udivmoddisi4_internal(temp, temp, operands[2]));
-  last = emit_move_insn(temp, temp);
-  {
-    rtx divdi, moddi, divsi, modsi;
-    divsi = gen_rtx (UDIV, SImode, operands[1], operands[2]);
-    modsi = gen_rtx (UMOD, SImode, operands[1], operands[2]);
-    divdi = gen_rtx (ZERO_EXTEND, DImode, divsi);
-    moddi = gen_rtx (ZERO_EXTEND, DImode, modsi);
-    REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
-			         REG_NOTES (first));
-    REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
-                                gen_rtx (EXPR_LIST, REG_EQUAL,
-                       gen_rtx (IOR, DImode, moddi,
-                               gen_rtx (ASHIFT, DImode, divdi, GEN_INT(32))),
-                       REG_NOTES (last)));
-  }
-
-  insn = emit_move_insn(operands[0], gen_highpart(SImode, temp));
-  insn = emit_move_insn(operands[3], gen_lowpart(SImode, temp));
-  DONE;
-}")
-
-;; If we try and describe what this does, we have to zero-expand an
-;; operand, which prevents it being a constant (VOIDmode) (see udivmoddisi4
-;; below. This udivmoddisi4_internal never matches anything and is only
-;; ever used when explicitly emitted by a define_expand.
-(define_insn "udivmoddisi4_internal"
-  [(set (match_operand:DI 0 "reg_or_mem_operand" "=rm")
-        (unspec:SI [(match_operand:DI 1 "reg_or_mem_operand" "0")
-                    (match_operand:SI 2 "general_operand" "g")] 0))]
-  ""
-  "deid %2,%0")
-
-;; Retain this insn which *does* have a pattern indicating what it does,
-;; just in case the compiler is smart enough to recognize a substitution.
-(define_insn "udivmoddisi4"
-  [(set (subreg:SI (match_operand:DI 0 "register_operand" "=rm") 1)
-	(truncate:SI (udiv:DI (match_operand:DI 1 "reg_or_mem_operand" "0")
-		 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "g")))))
-   (set (subreg:SI (match_operand:DI 3 "register_operand" "=0") 0)
-	(truncate:SI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
-  ""
-  "deid %2,%0")
-
-;; Part word variants. These seem to never be used at the moment (gcc
-;; 2.7.2.2). The code generation prefers to zero extend hi's and qi's
-;; and use signed div and mod. Keep these insns incase that changes.
-;; divmod should have an advantage when both div and mod are needed. However,
-;; divmod uses two registers, so maybe the compiler knows best.
-
-(define_expand "udivmodhi4"
-  [(parallel
-  [(set (match_operand:HI 0 "reg_or_mem_operand" "")
-	(udiv:HI (match_operand:HI 1 "general_operand" "")
-		     (match_operand:HI 2 "general_operand" "")))
-   (set (match_operand:HI 3 "reg_or_mem_operand" "")
-	(umod:HI (match_dup 1) (match_dup 2)))])]
-  ""
-  "
-{
-  rtx temp = gen_reg_rtx(DImode);
-  rtx insn, first, last;
-  first = emit_move_insn(gen_lowpart(HImode, temp), operands[1]);
-  emit_move_insn(gen_highpart (HImode, temp), const0_rtx);
-  operands[2] = force_reg(HImode, operands[2]);
-  emit_insn(gen_udivmoddihi4_internal(temp, temp, operands[2]));
-  last = emit_move_insn(temp, temp);
-  {
-    rtx divdi, moddi, divhi, modhi;
-    divhi = gen_rtx (UDIV, HImode, operands[1], operands[2]);
-    modhi = gen_rtx (UMOD, HImode, operands[1], operands[2]);
-    divdi = gen_rtx (ZERO_EXTEND, DImode, divhi);
-    moddi = gen_rtx (ZERO_EXTEND, DImode, modhi);
-    REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
-			         REG_NOTES (first));
-    REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
-                                gen_rtx (EXPR_LIST, REG_EQUAL,
-                       gen_rtx(IOR, DImode, moddi,
-                               gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
-                       REG_NOTES (last)));
-  }
-
-  insn = emit_move_insn(operands[0], gen_highpart(HImode, temp));
-  insn = emit_move_insn(operands[3], gen_lowpart(HImode, temp));
-  DONE;
-}")
-
-;; deiw wants two hi's in seperate registers or else they can be adjacent
-;; in memory. DI mode will ensure two registers are available, but if we
-;; want to allow memory as an operand we would need SI mode. There is no
-;; way to do this, so just restrict operand 0 and 1 to be in registers.
-(define_insn "udivmoddihi4_internal"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (unspec:HI [(match_operand:DI 1 "register_operand" "0")
-                    (match_operand:HI 2 "general_operand" "g")] 0))]
-  ""
-  "deiw %2,%0")
-
-(define_insn "udivmoddihi4"
-  [(set (subreg:HI (match_operand:DI 0 "register_operand" "=r") 1)
-	(truncate:HI (udiv:DI (match_operand:DI 1 "reg_or_mem_operand" "0")
-		 (zero_extend:DI (match_operand:HI 2 "nonimmediate_operand" "g")))))
-   (set (subreg:HI (match_operand:DI 3 "register_operand" "=0") 0)
-	(truncate:HI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
-  ""
-  "deiw %2,%0")
-
-(define_expand "udivmodqi4"
-  [(parallel
-  [(set (match_operand:QI 0 "reg_or_mem_operand" "")
-	(udiv:QI (match_operand:QI 1 "general_operand" "")
-		     (match_operand:QI 2 "general_operand" "")))
-   (set (match_operand:QI 3 "reg_or_mem_operand" "")
-	(umod:QI (match_dup 1) (match_dup 2)))])]
-  ""
-  "
-{
-  rtx temp = gen_reg_rtx(DImode);
-  rtx insn, first, last;
-  first = emit_move_insn(gen_lowpart(QImode, temp), operands[1]);
-  emit_move_insn(gen_highpart(QImode, temp), const0_rtx);
-  operands[2] = force_reg(QImode, operands[2]);
-  emit_insn(gen_udivmoddiqi4_internal(temp, temp, operands[2]));
-  last = emit_move_insn(temp, temp);
-  {
-    rtx divdi, moddi, divqi, modqi;
-    divqi = gen_rtx (UDIV, QImode, operands[1], operands[2]);
-    modqi = gen_rtx (UMOD, QImode, operands[1], operands[2]);
-    divdi = gen_rtx (ZERO_EXTEND, DImode, divqi);
-    moddi = gen_rtx (ZERO_EXTEND, DImode, modqi);
-    REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
-			         REG_NOTES (first));
-    REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
-                                gen_rtx (EXPR_LIST, REG_EQUAL,
-                       gen_rtx(IOR, DImode, moddi,
-                               gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
-                       REG_NOTES (last)));
-  }
-
-  insn = emit_move_insn(operands[0], gen_highpart(QImode, temp));
-  insn = emit_move_insn(operands[3], gen_lowpart(QImode, temp));
-  DONE;
-}")
-
-;; deib wants two qi's in seperate registers or else they can be adjacent
-;; in memory. DI mode will ensure two registers are available, but if we
-;; want to allow memory as an operand we would need HI mode. There is no
-;; way to do this, so just restrict operand 0 and 1 to be in registers.
-(define_insn "udivmoddiqi4_internal"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (unspec:QI [(match_operand:DI 1 "reg_or_mem_operand" "0")
-                    (match_operand:QI 2 "general_operand" "g")] 0))]
-  ""
-  "deib %2,%0")
-
-(define_insn "udivmoddiqi4"
-  [(set (subreg:QI (match_operand:DI 0 "register_operand" "=r") 1)
-	(truncate:QI (udiv:DI (match_operand:DI 1 "reg_or_mem_operand" "0")
-		 (zero_extend:DI (match_operand:QI 2 "nonimmediate_operand" "g")))))
-   (set (subreg:QI (match_operand:DI 3 "register_operand" "=0") 0)
-	(truncate:QI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
-  ""
-  "deib %2,%0")
-
-;;- Divide instructions.
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "general_operand" "=lm")
-	(div:DF (match_operand:DF 1 "general_operand" "0")
-		(match_operand:DF 2 "general_operand" "lmF")))]
-  "TARGET_32081"
-  "divl %2,%0")
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "general_operand" "=fm")
-	(div:SF (match_operand:SF 1 "general_operand" "0")
-		(match_operand:SF 2 "general_operand" "fmF")))]
-  "TARGET_32081"
-  "divf %2,%0")
-
-;; See note 1
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(div:SI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "quod %2,%0")
-
-(define_insn "divhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(div:HI (match_operand:HI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "quow %2,%0")
-
-(define_insn "divqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(div:QI (match_operand:QI 1 "general_operand" "0")
-		(match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "quob %2,%0")
-
-;; Remainder instructions.
-
-;; See note 1
-(define_insn "modsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(mod:SI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "remd %2,%0")
-
-(define_insn "modhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(mod:HI (match_operand:HI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "remw %2,%0")
-
-(define_insn "modqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(mod:QI (match_operand:QI 1 "general_operand" "0")
-		(match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "remb %2,%0")
-
-
-;;- Logical Instructions: AND
-
-;; See note 1
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(and:SI (match_operand:SI 1 "general_operand" "%0")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
-	{
-	  if (INTVAL (operands[2]) == 0xffffff00)
-	    return \"movqb %$0,%0\";
-	  else
-	    {
-	      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
-	      return \"andb %2,%0\";
-	    }
-	}
-      if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
-        {
-	  if (INTVAL (operands[2]) == 0xffff0000)
-	    return \"movqw %$0,%0\";
-	  else
-	    {
-	      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
-	      return \"andw %2,%0\";
-	    }
-	}
-    }
-  return \"andd %2,%0\";
-}")
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(and:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
-    {
-      if (INTVAL (operands[2]) == 0xffffff00)
-	return \"movqb %$0,%0\";
-      else
-	{
-	  operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
-	  return \"andb %2,%0\";
-	}
-    }
-  return \"andw %2,%0\";
-}")
-
-(define_insn "andqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(and:QI (match_operand:QI 1 "general_operand" "%0")
-		(match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "andb %2,%0")
-
-;; See note 1
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
-		(match_operand:SI 2 "general_operand" "0")))]
-  ""
-  "bicd %1,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
-		(match_operand:HI 2 "general_operand" "0")))]
-  ""
-  "bicw %1,%0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
-		(match_operand:QI 2 "general_operand" "0")))]
-  ""
-  "bicb %1,%0")
-
-;;- Bit set instructions.
-
-;; See note 1
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(ior:SI (match_operand:SI 1 "general_operand" "%0")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT) {
-    if ((INTVAL (operands[2]) & 0xffffff00) == 0)
-      return \"orb %2,%0\";
-    if ((INTVAL (operands[2]) & 0xffff0000) == 0)
-      return \"orw %2,%0\";
-  }
-  return \"ord %2,%0\";
-}")
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(ior:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE(operands[2]) == CONST_INT &&
-      (INTVAL(operands[2]) & 0xffffff00) == 0)
-    return \"orb %2,%0\";
-  return \"orw %2,%0\";
-}")
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(ior:QI (match_operand:QI 1 "general_operand" "%0")
-		(match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "orb %2,%0")
-
-;;- xor instructions.
-
-;; See note 1
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(xor:SI (match_operand:SI 1 "general_operand" "%0")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT) {
-    if ((INTVAL (operands[2]) & 0xffffff00) == 0)
-      return \"xorb %2,%0\";
-    if ((INTVAL (operands[2]) & 0xffff0000) == 0)
-      return \"xorw %2,%0\";
-  }
-  return \"xord %2,%0\";
-}")
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(xor:HI (match_operand:HI 1 "general_operand" "%0")
-		(match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE(operands[2]) == CONST_INT &&
-      (INTVAL(operands[2]) & 0xffffff00) == 0)
-    return \"xorb %2,%0\";
-  return \"xorw %2,%0\";
-}")
-
-(define_insn "xorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(xor:QI (match_operand:QI 1 "general_operand" "%0")
-		(match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "xorb %2,%0")
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "general_operand" "=lm<")
-	(neg:DF (match_operand:DF 1 "general_operand" "lmF")))]
-  "TARGET_32081"
-  "negl %1,%0")
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "general_operand" "=fm<")
-	(neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
-  "TARGET_32081"
-  "negf %1,%0")
-
-(define_insn "negdi2"
-  [(set (match_operand:DI 0 "general_operand" "=ro")
-	(neg:DI (match_operand:DI 1 "general_operand" "ro")))]
-  ""
-  "*
-{
-  rtx low[2], high[2], xops[4];
-  split_di (operands, 2, low, high);
-  xops[0] = low[0];
-  xops[1] = high[0];
-  xops[2] = low[1];
-  xops[3] = high[1];
-
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      output_asm_insn (\"negd %3,%1\", xops);
-      output_asm_insn (\"negd %2,%0\", xops);
-      output_asm_insn (\"subcd %$0,%1\", xops);
-    }
-  else
-    {
-      output_asm_insn (\"negd %2,%0\", xops);
-      output_asm_insn (\"movqd %$0,%1\", xops);
-      output_asm_insn (\"subcd %3,%1\", xops);
-    }
-  return \"\"; 
-}")
-
-;; See note 1
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(neg:SI (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "negd %1,%0")
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(neg:HI (match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "negw %1,%0")
-
-(define_insn "negqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(neg:QI (match_operand:QI 1 "general_operand" "g")))]
-  ""
-  "negb %1,%0")
-
-;; See note 1
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(not:SI (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "comd %1,%0")
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(not:HI (match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "comw %1,%0")
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(not:QI (match_operand:QI 1 "general_operand" "g")))]
-  ""
-  "comb %1,%0")
-
-;; arithmetic left and right shift operations
-;; on the 32532 we will always use lshd for arithmetic left shifts,
-;; because it is three times faster.  Broken programs which
-;; use negative shift counts are probably broken differently
-;; than elsewhere.
-
-;; alternative 0 never matches on the 32532
-;; See note 1
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g,g")
-	(ashift:SI (match_operand:SI 1 "general_operand" "r,0")
-		   (match_operand:SI 2 "general_operand" "I,g")))]
-  ""
-  "*
-{ if (TARGET_32532)
-    return \"lshd %2,%0\";
-  else
-    return output_shift_insn (operands);
-}")
-
-(define_insn "ashlhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(ashift:HI (match_operand:HI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{ if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) == 1)
-	return \"addw %0,%0\";
-      else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
-	return \"addw %0,%0\;addw %0,%0\";
-    }
-  if (TARGET_32532)
-    return \"lshw %2,%0\";
-  else
-    return \"ashw %2,%0\";
-}")
-
-(define_insn "ashlqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(ashift:QI (match_operand:QI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{ if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) == 1)
-	return \"addb %0,%0\";
-      else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
-	return \"addb %0,%0\;addb %0,%0\";
-    }
-  if (TARGET_32532)
-    return \"lshb %2,%0\";
-  else
-    return \"ashb %2,%0\";
-}")
-
-;; Arithmetic right shift on the 32k works by negating the shift count.
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
-		     (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "ashd %n2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
-		     (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
-  ""
-  "ashd %2,%0")
-
-(define_expand "ashrhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(ashiftrt:HI (match_operand:HI 1 "general_operand" "g")
-		     (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "ashw %n2,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
-		     (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
-  ""
-  "ashw %2,%0")
-
-(define_expand "ashrqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(ashiftrt:QI (match_operand:QI 1 "general_operand" "g")
-		     (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "ashb %n2,%0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
-		     (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
-  ""
-  "ashb %2,%0")
-
-;; logical shift instructions
-
-;; Logical right shift on the 32k works by negating the shift count.
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
-		     (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "lshd %n2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
-		     (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
-  ""
-  "lshd %2,%0")
-
-(define_expand "lshrhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
-		     (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "lshw %n2,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
-		     (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
-  ""
-  "lshw %2,%0")
-
-(define_expand "lshrqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
-		     (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "lshb %n2,%0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
-		     (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
-  ""
-  "lshb %2,%0")
-
-;; Rotate instructions
-
-;; See note 1
-(define_insn "rotlsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(rotate:SI (match_operand:SI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "rotd %2,%0")
-
-(define_insn "rotlhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(rotate:HI (match_operand:HI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "rotw %2,%0")
-
-(define_insn "rotlqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(rotate:QI (match_operand:QI 1 "general_operand" "0")
-		   (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "rotb %2,%0")
-
-;; Right rotate on the 32k works by negating the shift count.
-(define_expand "rotrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(rotatert:SI (match_operand:SI 1 "general_operand" "g")
-		     (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(rotatert:SI (match_operand:SI 1 "general_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "rotd %n2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(rotatert:SI (match_operand:SI 1 "general_operand" "0")
-		     (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
-  ""
-  "rotd %2,%0")
-
-(define_expand "rotrhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(rotatert:HI (match_operand:HI 1 "general_operand" "g")
-		     (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(rotatert:HI (match_operand:HI 1 "general_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "rotw %n2,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(rotatert:HI (match_operand:HI 1 "general_operand" "0")
-		     (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
-  ""
-  "rotw %2,%0")
-
-(define_expand "rotrqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(rotatert:QI (match_operand:QI 1 "general_operand" "g")
-		     (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(rotatert:QI (match_operand:QI 1 "general_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "rotb %n2,%0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(rotatert:QI (match_operand:QI 1 "general_operand" "0")
-		     (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
-  ""
-  "rotb %2,%0")
-
-;;- load or push effective address 
-;; These come after the move, add, and multiply patterns
-;; because we don't want pushl $1 turned into pushad 1.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(match_operand:QI 1 "address_operand" "p"))]
-  ""
-  "*
-{
-  if (REG_P (operands[0])
-      && GET_CODE (operands[1]) == MULT
-      && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
-      && (INTVAL (XEXP (operands[1], 1)) == 2
-	  || INTVAL (XEXP (operands[1], 1)) == 4))
-    {
-      rtx xoperands[3];
-      xoperands[0] = operands[0];
-      xoperands[1] = XEXP (operands[1], 0);
-      xoperands[2] = GEN_INT (INTVAL (XEXP (operands[1], 1)) >> 1);
-      return output_shift_insn (xoperands);
-    }
-  return \"addr %a1,%0\";
-}")
-
-;;; Index insns.  These are about the same speed as multiply-add counterparts.
-;;; but slower then using power-of-2 shifts if we can use them
-;
-;;; See note 1
-;(define_insn ""
-;  [(set (match_operand:SI 0 "register_operand" "=r")
-;	(plus:SI (match_operand:SI 1 "general_operand" "g")
-;		 (mult:SI (match_operand:SI 2 "register_operand" "0")
-;			  (plus:SI (match_operand:SI 3 "general_operand" "g") (const_int 1)))))]
-;  "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
-;  "indexd %0,%3,%1")
-;
-;(define_insn ""
-;  [(set (match_operand:SI 0 "register_operand" "=r")
-;	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
-;			  (plus:SI (match_operand:SI 2 "general_operand" "g") (const_int 1)))
-;		 (match_operand:SI 3 "general_operand" "g")))]
-;  "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
-;  "indexd %0,%2,%3")
-
-;; Set, Clear, and Invert bit
-
-;; See note 1
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
-			 (const_int 1)
-			 (match_operand:SI 1 "general_operand" "g"))
-	(const_int 1))]
-  ""
-  "sbitd %1,%0")
-
-;; See note 1
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
-			 (const_int 1)
-			 (match_operand:SI 1 "general_operand" "g"))
-	(const_int 0))]
-  ""
-  "cbitd %1,%0")
-
-;; See note 1
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "+g")
-	(xor:SI (ashift:SI (const_int 1)
-			   (match_operand:SI 1 "general_operand" "g"))
-		(match_dup 0)))]
-  ""
-  "ibitd %1,%0")
-
-;; See note 1
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(xor:QI (subreg:QI
-		 (ashift:SI (const_int 1)
-			    (match_operand:QI 1 "general_operand" "g")) 0)
-		(match_dup 0)))]
-  ""
-  "ibitb %1,%0")
-
-;; Recognize jbs and jbc instructions.
-
-(define_insn ""
-  [(set (cc0)
-	(zero_extract (match_operand:SI 0 "general_operand" "rm")
-		      (const_int 1)
-		      (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "*
-{ cc_status.flags = CC_Z_IN_F;
-  return \"tbitd %1,%0\";
-}")
-
-;; extract(base, width, offset)
-;; Signed bitfield extraction is not supported in hardware on the
-;; NS 32032.  It is therefore better to let GCC figure out a
-;; good strategy for generating the proper instruction sequence
-;; and represent it as rtl.
-
-;; Optimize the case of extracting a byte or word from a register.
-;; Otherwise we must load a register with the offset of the
-;; chunk we want, and perform an extract insn (each of which
-;; is very expensive).  Since we use the stack to do our bit-twiddling
-;; we cannot use it for a destination.  Perhaps things are fast
-;; enough on the 32532 that such hacks are not needed.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=ro")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "const_int_operand" "i")
-			 (match_operand:SI 3 "const_int_operand" "i")))]
-  "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
-  "*
-{
-  output_asm_insn (\"movd %1,tos\", operands);
-  if (INTVAL (operands[2]) == 16)
-    {
-      if (INTVAL (operands[3]) == 8)
-	output_asm_insn (\"movzwd 1(sp),%0\", operands);
-      else
-	output_asm_insn (\"movzwd 2(sp),%0\", operands);
-    }
-  else
-    {
-      if (INTVAL (operands[3]) == 8)
-	output_asm_insn (\"movzbd 1(sp),%0\", operands);
-      else if (INTVAL (operands[3]) == 16)
-	output_asm_insn (\"movzbd 2(sp),%0\", operands);
-      else
-	output_asm_insn (\"movzbd 3(sp),%0\", operands);
-    }
-  if (TARGET_32532 || TARGET_32332)
-    return \"cmpqd %$0,tos\";
-  else
-    return \"adjspb %$-4\";
-}")
-
-;; The exts/ext instructions have the problem that they always access
-;; 32 bits even if the bitfield is smaller. For example the instruction
-;; 	extsd 7(r1),r0,2,5
-;; would read not only at address 7(r1) but also at 8(r1) to 10(r1).
-;; If these addresses are in a different (unmapped) page a memory fault
-;; is the result.
-;;
-;; Timing considerations:
-;;	movd	0(r1),r0	3 bytes
-;;	lshd	-26,r0		4
-;;	andd	0x1f,r0		5
-;; takes about 13 cycles on the 532 while
-;;	extsd	7(r1),r0,2,5	5 bytes
-;; takes about 21 cycles.
-;;
-;; The inss/ins instructions suffer from the same problem.
-;;
-;; A machine specific option (-mbitfield/-mnobitfield) is used
-;; to allow/disallow the use of these instructions.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "g")
-			 (match_operand:SI 2 "const_int_operand" "i")
-			 (match_operand:SI 3 "general_operand" "rK")))]
-  "TARGET_BITFIELD"
-  "*
-{ if (GET_CODE (operands[3]) == CONST_INT)
-    return \"extsd %1,%0,%3,%2\";
-  else return \"extd %3,%1,%0,%2\";
-}")
-
-(define_insn "extzv"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(zero_extract:SI (match_operand:QI 1 "general_operand" "g")
-			 (match_operand:SI 2 "const_int_operand" "i")
-			 (match_operand:SI 3 "general_operand" "rK")))]
-  "TARGET_BITFIELD"
-  "*
-{ if (GET_CODE (operands[3]) == CONST_INT)
-    return \"extsd %1,%0,%3,%2\";
-  else return \"extd %3,%1,%0,%2\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o")
-			 (match_operand:SI 1 "const_int_operand" "i")
-			 (match_operand:SI 2 "general_operand" "rn"))
-	(match_operand:SI 3 "general_operand" "rm"))]
-  "TARGET_BITFIELD"
-  "*
-{ if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) >= 8)
-	{
-	  operands[0] = adj_offsettable_operand (operands[0],
-					        INTVAL (operands[2]) / 8);
-          operands[2] = GEN_INT (INTVAL (operands[2]) % 8);
-	}
-      if (INTVAL (operands[1]) <= 8)
-        return \"inssb %3,%0,%2,%1\";
-      else if (INTVAL (operands[1]) <= 16)
-	return \"inssw %3,%0,%2,%1\";
-      else
-	return \"inssd %3,%0,%2,%1\";
-    }
-  return \"insd %2,%3,%0,%1\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-			 (match_operand:SI 1 "const_int_operand" "i")
-			 (match_operand:SI 2 "general_operand" "rK"))
-	(match_operand:SI 3 "general_operand" "rm"))]
-  "TARGET_BITFIELD"
-  "*
-{ if (GET_CODE (operands[2]) == CONST_INT)
-    if (INTVAL (operands[1]) <= 8)
-      return \"inssb %3,%0,%2,%1\";
-    else if (INTVAL (operands[1]) <= 16)
-      return \"inssw %3,%0,%2,%1\";
-    else
-      return \"inssd %3,%0,%2,%1\";
-  return \"insd %2,%3,%0,%1\";
-}")
-
-(define_insn "insv"
-  [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
-			 (match_operand:SI 1 "const_int_operand" "i")
-			 (match_operand:SI 2 "general_operand" "rK"))
-	(match_operand:SI 3 "general_operand" "rm"))]
-  "TARGET_BITFIELD"
-  "*
-{ if (GET_CODE (operands[2]) == CONST_INT)
-    if (INTVAL (operands[1]) <= 8)
-      return \"inssb %3,%0,%2,%1\";
-    else if (INTVAL (operands[1]) <= 16)
-      return \"inssw %3,%0,%2,%1\";
-    else
-      return \"inssd %3,%0,%2,%1\";
-  return \"insd %2,%3,%0,%1\";
-}")
-
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "br %l0")
-
-(define_insn "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{ if (cc_prev_status.flags & CC_Z_IN_F)
-    return \"bfc %l0\";
-  else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
-    return \"bfs %l0\";
-  else return \"beq %l0\";
-}")
-
-(define_insn "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{ if (cc_prev_status.flags & CC_Z_IN_F)
-    return \"bfs %l0\";
-  else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
-    return \"bfc %l0\";
-  else return \"bne %l0\";
-}")
-
-(define_insn "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "bgt %l0")
-
-(define_insn "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "bhi %l0")
-
-(define_insn "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "blt %l0")
-
-(define_insn "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "blo %l0")
-
-(define_insn "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "bge %l0")
-
-(define_insn "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "bhs %l0")
-
-(define_insn "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "ble %l0")
-
-(define_insn "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "bls %l0")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{ if (cc_prev_status.flags & CC_Z_IN_F)
-    return \"bfs %l0\";
-  else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
-    return \"bfc %l0\";
-  else return \"bne %l0\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{ if (cc_prev_status.flags & CC_Z_IN_F)
-    return \"bfc %l0\";
-  else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
-    return \"bfs %l0\";
-  else return \"beq %l0\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "ble %l0")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "bls %l0")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "bge %l0")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "bhs %l0")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "blt %l0")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "blo %l0")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "bgt %l0")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "bhi %l0")
-
-;; Subtract-and-jump and Add-and-jump insns.
-;; These can actually be used for adding numbers in the range -8 to 7
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (match_operand:SI 0 "general_operand" "+g")
-	     (match_operand:SI 1 "const_int_operand" "i"))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))
-  (set (match_dup 0)
-       (minus:SI (match_dup 0)
-		 (match_dup 1)))]
-  "INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
-  "acbd %n1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (match_operand:SI 0 "general_operand" "+g")
-	     (match_operand:SI 1 "const_int_operand" "i"))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))
-  (set (match_dup 0)
-       (plus:SI (match_dup 0)
-		(match_operand:SI 3 "const_int_operand" "i")))]
-  "INTVAL (operands[1]) == - INTVAL (operands[3])
-   && INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8"
-  "acbd %3,%0,%l2")
-
-(define_insn "call"
-  [(call (match_operand:QI 0 "memory_operand" "m")
-	 (match_operand:QI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-#ifndef JSR_ALWAYS
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      rtx temp = XEXP (operands[0], 0);
-      if (CONSTANT_ADDRESS_P (temp))
-	{
-#ifdef ENCORE_ASM
-	  return \"bsr %?%0\";
-#else
-#ifdef CALL_MEMREF_IMPLICIT
-	  operands[0] = temp;
-	  return \"bsr %0\";
-#else
-#ifdef GNX_V3
-	  return \"bsr %0\";
-#else
-	  return \"bsr %?%a0\";
-#endif
-#endif
-#endif
-	}
-      if (GET_CODE (XEXP (operands[0], 0)) == REG)
-#if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
-	return \"jsr %0\";
-#else
-        return \"jsr %a0\";
-#endif
-    }
-#endif /* not JSR_ALWAYS */
-  return \"jsr %0\";
-}")
-
-(define_insn "call_value"
-  [(set (match_operand 0 "" "=rf")
-	(call (match_operand:QI 1 "memory_operand" "m")
-	      (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-#ifndef JSR_ALWAYS
-  if (GET_CODE (operands[1]) == MEM)
-    {
-      rtx temp = XEXP (operands[1], 0);
-      if (CONSTANT_ADDRESS_P (temp))
-	{
-#ifdef ENCORE_ASM
-	  return \"bsr %?%1\";
-#else
-#ifdef CALL_MEMREF_IMPLICIT
-	  operands[1] = temp;
-	  return \"bsr %1\";
-#else
-#ifdef GNX_V3
-	  return \"bsr %1\";
-#else
-	  return \"bsr %?%a1\";
-#endif
-#endif
-#endif
-	}
-      if (GET_CODE (XEXP (operands[1], 0)) == REG)
-#if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
-	return \"jsr %1\";
-#else
-        return \"jsr %a1\";
-#endif
-    }
-#endif /* not JSR_ALWAYS */
-  return \"jsr %1\";
-}")
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-(define_insn "return"
-  [(return)]
-  "0"
-  "ret 0")
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "general_operand" "=fm<")
-	(abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
-  "TARGET_32081"
-  "absf %1,%0")
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "general_operand" "=lm<")
-	(abs:DF (match_operand:DF 1 "general_operand" "lmF")))]
-  "TARGET_32081"
-  "absl %1,%0")
-
-;; See note 1
-(define_insn "abssi2"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(abs:SI (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "absd %1,%0")
-
-(define_insn "abshi2"
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(abs:HI (match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "absw %1,%0")
-
-(define_insn "absqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(abs:QI (match_operand:QI 1 "general_operand" "g")))]
-  ""
-  "absb %1,%0")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
-  ""
-  "jump %0")
-
-(define_insn "tablejump"
-  [(set (pc)
-	(plus:SI (pc) (match_operand:SI 0 "general_operand" "g")))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "*
-{
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
-			     CODE_LABEL_NUMBER (operands[1]));
-  return \"cased %0\";
-}")
-
-;; Scondi instructions
-(define_insn "seq"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(eq:SI (cc0) (const_int 0)))]
-  ""
-  "*
-{ if (cc_prev_status.flags & CC_Z_IN_F)
-    return \"sfcd %0\";
-  else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
-    return \"sfsd %0\";
-  else return \"seqd %0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(eq:HI (cc0) (const_int 0)))]
-  ""
-  "*
-{ if (cc_prev_status.flags & CC_Z_IN_F)
-    return \"sfcw %0\";
-  else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
-    return \"sfsw %0\";
-  else return \"seqw %0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(eq:QI (cc0) (const_int 0)))]
-  ""
-  "*
-{ if (cc_prev_status.flags & CC_Z_IN_F)
-    return \"sfcb %0\";
-  else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
-    return \"sfsb %0\";
-  else return \"seqb %0\";
-}")
-
-(define_insn "sne"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(ne:SI (cc0) (const_int 0)))]
-  ""
-  "*
-{ if (cc_prev_status.flags & CC_Z_IN_F)
-    return \"sfsd %0\";
-  else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
-    return \"sfcd %0\";
-  else return \"sned %0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(ne:HI (cc0) (const_int 0)))]
-  ""
-  "*
-{ if (cc_prev_status.flags & CC_Z_IN_F)
-    return \"sfsw %0\";
-  else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
-    return \"sfcw %0\";
-  else return \"snew %0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(ne:QI (cc0) (const_int 0)))]
-  ""
-  "*
-{ if (cc_prev_status.flags & CC_Z_IN_F)
-    return \"sfsb %0\";
-  else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
-    return \"sfcb %0\";
-  else return \"sneb %0\";
-}")
-
-(define_insn "sgt"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(gt:SI (cc0) (const_int 0)))]
-  ""
-  "sgtd %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(gt:HI (cc0) (const_int 0)))]
-  ""
-  "sgtw %0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(gt:QI (cc0) (const_int 0)))]
-  ""
-  "sgtb %0")
-
-(define_insn "sgtu"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(gtu:SI (cc0) (const_int 0)))]
-  ""
-  "shid %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(gtu:HI (cc0) (const_int 0)))]
-  ""
-  "shiw %0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(gtu:QI (cc0) (const_int 0)))]
-  ""
-  "shib %0")
-
-(define_insn "slt"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(lt:SI (cc0) (const_int 0)))]
-  ""
-  "sltd %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(lt:HI (cc0) (const_int 0)))]
-  ""
-  "sltw %0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(lt:QI (cc0) (const_int 0)))]
-  ""
-  "sltb %0")
-
-(define_insn "sltu"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(ltu:SI (cc0) (const_int 0)))]
-  ""
-  "slod %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(ltu:HI (cc0) (const_int 0)))]
-  ""
-  "slow %0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(ltu:QI (cc0) (const_int 0)))]
-  ""
-  "slob %0")
-
-(define_insn "sge"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(ge:SI (cc0) (const_int 0)))]
-  ""
-  "sged %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(ge:HI (cc0) (const_int 0)))]
-  ""
-  "sgew %0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(ge:QI (cc0) (const_int 0)))]
-  ""
-  "sgeb %0")
-
-(define_insn "sgeu"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(geu:SI (cc0) (const_int 0)))]
-  ""
-  "shsd %0")  
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(geu:HI (cc0) (const_int 0)))]
-  ""
-  "shsw %0")  
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(geu:QI (cc0) (const_int 0)))]
-  ""
-  "shsb %0")  
-
-(define_insn "sle"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(le:SI (cc0) (const_int 0)))]
-  ""
-  "sled %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(le:HI (cc0) (const_int 0)))]
-  ""
-  "slew %0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(le:QI (cc0) (const_int 0)))]
-  ""
-  "sleb %0")
-
-(define_insn "sleu"
-  [(set (match_operand:SI 0 "general_operand" "=g<")
-	(leu:SI (cc0) (const_int 0)))]
-  ""
-  "slsd %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g<")
-	(leu:HI (cc0) (const_int 0)))]
-  ""
-  "slsw %0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g<")
-	(leu:QI (cc0) (const_int 0)))]
-  ""
-  "slsb %0")
-
-;; ffs instructions
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "ro")
-	(minus:SI 
-		(plus:SI (ffs:SI (zero_extract:SI 
-				(match_operand:SI 1 "general_operand" "g") 
-				(minus:SI (const_int 32) (match_dup 0))
-				(match_dup 0)))
-			(match_dup 0)) 
-		(const_int 1)))]
-  ""
-  "ffsd %1,%0; bfc 1f; addqd %$-1,%0; 1:")
-
-(define_expand "ffssi2"
-  [(set (match_operand:SI 0 "general_operand" "=g") (const_int 0))
-   (set (match_dup 0)
-	(minus:SI 
-		(plus:SI (ffs:SI (zero_extract:SI 
-				(match_operand:SI 1 "general_operand" "g") 
-				(minus:SI (const_int 32) (match_dup 0))
-				(match_dup 0)))
-			(match_dup 0)) 
-		(const_int 1)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int 1)))]
-  ""
-  "operands[1] = make_safe_from(operands[1], operands[0]);")
-
-;; Speed up stack adjust followed by a HI fixedpoint push.
-
-(define_peephole
-  [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -2)))
-   (set (match_operand:HI 0 "push_operand" "=m")
-	(match_operand:HI 1 "general_operand" "g"))]
-  "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-	output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
-			 operands);
-  else
-	output_asm_insn (\"movzwd %1,tos\", operands);
-  return \"\";
-}")
-
-;; Speed up stack adjust followed by a zero_extend:HI(QI) fixedpoint push.
-
-(define_peephole
-  [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -2)))
-   (set (match_operand:HI 0 "push_operand" "=m")
-	(zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
-  "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-	output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
-			 operands);
-  else
-	output_asm_insn (\"movzbd %1,tos\", operands);
-  return \"\";
-}")
-
-;; Speed up stack adjust followed by a sign_extend:HI(QI) fixedpoint push.
-
-(define_peephole
-  [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -2)))
-   (set (match_operand:HI 0 "push_operand" "=m")
-	(sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
-  "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-	output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
-			 operands);
-  else
-	output_asm_insn (\"movxbd %1,tos\", operands);
-  return \"\";
-}")
-
-;; Speed up stack adjust followed by a QI fixedpoint push.
-
-(define_peephole
-  [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -3)))
-   (set (match_operand:QI 0 "push_operand" "=m")
-	(match_operand:QI 1 "general_operand" "g"))]
-  "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-	output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
-			 operands);
-  else
-	output_asm_insn (\"movzbd %1,tos\", operands);
-  return \"\";
-}")
-
-;; Speed up stack adjust followed by a SI fixedpoint push.
-
-(define_peephole
-  [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int 4)))
-   (set (match_operand:SI 0 "push_operand" "=m")
-	(match_operand:SI 1 "general_operand" "g"))]
-  "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-	output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,0(sp)\"),
-			 operands);
-  else if (GET_CODE (operands[1]) != REG
-	   && GET_CODE (operands[1]) != MEM
-	   && address_operand (operands[1], SImode))
-	output_asm_insn (\"addr %a1,0(sp)\", operands);
-  else
-	output_asm_insn (\"movd %1,0(sp)\", operands);
-  return \"\";
-}")
-
-;; Speed up stack adjust followed by two fullword fixedpoint pushes.
-
-(define_peephole
-  [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int 8)))
-   (set (match_operand:SI 0 "push_operand" "=m")
-	(match_operand:SI 1 "general_operand" "g"))
-   (set (match_operand:SI 2 "push_operand" "=m")
-	(match_operand:SI 3 "general_operand" "g"))]
-  "! reg_mentioned_p (stack_pointer_rtx, operands[1])
-   && ! reg_mentioned_p (stack_pointer_rtx, operands[3])"
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-	output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,4(sp)\"),
-			 operands);
-  else if (GET_CODE (operands[1]) != REG
-	   && GET_CODE (operands[1]) != MEM
-	   && address_operand (operands[1], SImode))
-	output_asm_insn (\"addr %a1,4(sp)\", operands);
-  else
-	output_asm_insn (\"movd %1,4(sp)\", operands);
-
-  if (GET_CODE (operands[3]) == CONST_INT)
-	output_asm_insn (output_move_dconst (INTVAL (operands[3]), \"%3,0(sp)\"),
-			 operands);
-  else if (GET_CODE (operands[3]) != REG
-	   && GET_CODE (operands[3]) != MEM
-	   && address_operand (operands[3], SImode))
-	output_asm_insn (\"addr %a3,0(sp)\", operands);
-  else
-	output_asm_insn (\"movd %3,0(sp)\", operands);
-  return \"\";
-}")
diff --git a/gcc/config/ns32k/pc532-mach.h b/gcc/config/ns32k/pc532-mach.h
deleted file mode 100755
index 0aeabad..0000000
--- a/gcc/config/ns32k/pc532-mach.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   PC532 with National 32532, running Mach 3.0.
-   Copyright (C) 1992, 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "ns32k/pc532.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dns32532 -DPC532 -DMACH=1 -Asystem(unix) -Asystem(mach) -Acpu(ns32k) -Amachine(ns32k)"
-
-/* There's a bug in the setjmp implementation that strikes
-   if the caller of setjmp doesn't have a frame pointer.  */
-#undef FRAME_POINTER_REQUIRED
-#define FRAME_POINTER_REQUIRED current_function_calls_setjmp
diff --git a/gcc/config/ns32k/pc532-min.h b/gcc/config/ns32k/pc532-min.h
deleted file mode 100755
index 9d3d5de..0000000
--- a/gcc/config/ns32k/pc532-min.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   PC532 with National 32532, running Minix.
-   Works with pc532 Minix 1.5hybrid.
-   Copyright (C) 1990 Free Software Foundation, Inc.
-
-   Derived from SEQUENT NS32000, written originally
-   by Bruce Culbertson <culberts@hplabs.hp.com>,
-   hacked for easier fit in gcc by Jyrki Kuoppala <jkp@cs.hut.fi>.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "ns32k/pc532.h"
-
-/* Minix has crtso.o instead of crt0.o */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC  \
-  "%{pg:gcrtso.o%s}%{!pg:%{p:mcrtso.o%s}%{!p:crtso.o%s}}"
-
-/* our setjmp doesn't save registers, so we must tell gcc to save
-   call-saved-regs in a function calling setjmp */
-
-#define NON_SAVING_SETJMP (current_function_calls_setjmp)
-
-/* at least with estdio there's no _cleanup() but we have atexit() */
-
-#define HAVE_ATEXIT
diff --git a/gcc/config/ns32k/pc532.h b/gcc/config/ns32k/pc532.h
deleted file mode 100755
index d98bf43..0000000
--- a/gcc/config/ns32k/pc532.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   PC532 with National 32532.
-   Copyright (C) 1990, 1994 Free Software Foundation, Inc.
-   Contributed by Jukka Virtanen <jtv@hut.fi>, Jyrki Kuoppala <jkp@cs.hut.fi>,
-   Tatu Yl|nen <ylo@ngs.fi>, Johannes Helander <jvh@cs.hut.fi>.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "ns32k/ns32k.h"
-
-/* Compile for the floating point unit & 32532 by default;
-   also presume SB is zero and no bitfield instructions */
-
-#define TARGET_DEFAULT (1 + 24 + 64)
-
-/* Write DBX debugging info for gdb to read */
-
-#define DBX_DEBUGGING_INFO
-
-/* Use the re-entrant and potentially faster method */
-
-#undef PCC_STATIC_STRUCT_RETURN
-
-/* 32-bit alignment for efficiency */
-#undef POINTER_BOUNDARY
-#define POINTER_BOUNDARY 32
-
-/* 32-bit alignment for efficiency */
-#undef FUNCTION_BOUNDARY
-#define FUNCTION_BOUNDARY 32
-
-/* 32532 spec says it can handle any alignment.  Rumor from tm-ns32k.h
-   tells this might not be actually true (but it's for 32032, perhaps
-   National has fixed the bug for 32532).  You might have to change this
-   if the bug still exists. */
-
-#undef STRICT_ALIGNMENT
-#define STRICT_ALIGNMENT 0
-
-/* Maybe someone needs to know which processor we're running on */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dns32000 -Dns32532 -Dpc532 -Dunix -Asystem(unix) -Acpu(ns32k) -Amachine(ns32k)"
-
-/* Use pc relative addressing whenever possible,
-   it's more efficient than absolute (ns32k.c)
-   You have to fix a bug in gas 1.38.1 to make this work with gas,
-   patch available from jkp@cs.hut.fi. */
-
-#define PC_RELATIVE
-
-/* Operand of bsr or jsr should be just the address.  */
-
-#define CALL_MEMREF_IMPLICIT
-
-/* movd insns may have floating point constant operands.  */
-
-#define MOVD_FLOAT_OK
diff --git a/gcc/config/ns32k/sequent.h b/gcc/config/ns32k/sequent.h
deleted file mode 100755
index 1e8c353..0000000
--- a/gcc/config/ns32k/sequent.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Definitions of target machine for GNU compiler.  SEQUENT NS32000 version.
-   Copyright (C) 1987 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@mcc.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "ns32k/ns32k.h"
-
-/* This is BSD, so it wants DBX format.  */
-#define DBX_DEBUGGING_INFO
-
-/* Sequent has some changes in the format of DBX symbols.  */
-#define DBX_NO_XREFS 1
-
-/* Don't split DBX symbols into continuations.  */
-#define DBX_CONTIN_LENGTH 0
-
-#define TARGET_DEFAULT 9  /* 32332 with 32081 (guessing).  */
-
-/* Print subsidiary information on the compiler version in use.  */
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (32000, Sequent syntax)");
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dns32000 -Dsequent -Dunix -Asystem(unix) -Asystem(bsd) -Acpu(ns32k) -Amachine(ns32k)"
-
-/* Link with libg.a when debugging, for dbx's sake.  */
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
-
-/* gcc should find libgcc.a itself, not ask linker to do so.  */
-
-#define LINK_LIBGCC_SPECIAL
-
-/* GCC must match what sys/types.h uses for size_t.  */
-
-#define SIZE_TYPE "int"
-
-/* This is how to align the code that follows an unconditional branch.
-   Don't define it, since it confuses the assembler (we hear).  */
-
-#undef LABEL_ALIGN_AFTER_BARRIER
-
-/* Assembler pseudo-op for shared data segment. */
-#define SHARED_SECTION_ASM_OP ".shdata"
-
-/* Control how stack adjust insns are output.  */
-#define SEQUENT_ADJUST_STACK
-
-#define NO_ABSOLUTE_PREFIX_IF_SYMBOLIC
-
-#define IMMEDIATE_PREFIX 0
-
-#define SEQUENT_ASM
-
-/* Operand of bsr or jsr should be just the address.  */
-
-#define CALL_MEMREF_IMPLICIT
-
-/* Output a reg as an index rather than a base if we have the choice.  */
-
-#define INDEX_RATHER_THAN_BASE
diff --git a/gcc/config/ns32k/tek6000.h b/gcc/config/ns32k/tek6000.h
deleted file mode 100755
index 01c88e3..0000000
--- a/gcc/config/ns32k/tek6000.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/* Definitions of target machine for GNU compiler.
-   Generic Tektronix 6000 series NS32000 version.
-   See ns32k/tek6100.h and ns32k/tek6200.h, which include this file.
-   Copyright (C) 1990 Free Software Foundation, Inc.
-   Created by Snoopy  (sopwith.uucp!snoopy).
-   Based on work by Mark Mason (mason@reed.bitnet,
-   pyramid!unify!mason@uunet.uu.net) and Keith Packard.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Generate syntax for the UTek assembler. */
-#ifndef UTEK_ASM
-#define UTEK_ASM
-#endif
-
-/* Two flags to control how addresses are printed in assembler insns.  */
-
-/* The way PUT_ABSOLUTE_PREFIX in ns32k.h works, setting it to 0 will
- * turn it off.  Define ABSOLUTE_PREFIX before including ns32k.h.
- */
-#define ABSOLUTE_PREFIX		0
-#define IMMEDIATE_PREFIX	'$'
-
-#include "ns32k/ns32k.h"
-
-/* Define these after ns32k.c so we will notice if gcc tries to
- * output external mode addressing.  UTek's as and ld do not support
- * external mode addressing, according to Daryl McDaniel (illian.uucp!darylm).
- * Hopefully the UTek assembler will complain if gcc feeds it this stuff.
- * They don't seem to do anything, I think that gcc is not actually
- * trying to generate external mode operands.
- */
-#undef PUT_EXTERNAL_PREFIX
-#define PUT_EXTERNAL_PREFIX(arg)  fprintf(arg, "  Should not be using external mode under UTek.  ")
-#define EXTERNAL_PREFIX '%'
-
-/* Used in ns32k.c to control syntax. */
-#define NO_ABSOLUTE_PREFIX_IF_SYMBOLIC
-#define NO_IMMEDIATE_PREFIX_IF_SYMBOLIC
-
-/* Used in ns32k.md to specify syntax of bsr/jsr operand. */
-#define CALL_MEMREF_IMPLICIT
-
-/* #define PC_RELATIVE */	/* Seems to break things. */
-#define BASE_REG_NEEDED		/* Seems to fix problem where external mode
-				 * syntax was being generated.
-				 */
-
-/*  ------------   Debugging Support   ----------------------------- */
-
-/* The sdb support does not yet work with UTek.  Need to teach gcc
- * how to create sdb type stabs as well as dbx style stabs.
- */
-#define DBX_DEBUGGING_INFO
-/* #define SDB_DEBUGGING_INFO */
-
-/* Act the same as the UTek complier: -g for dbx, -go for sdb.
- * This is used in toplev.c.
- */
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#define CC1_SPEC "{go:-gcoff}"
-#define CC1PLUS_SPEC "{go:-gcoff}"
-
-/* Sequent has some changes in the format of DBX symbols.  */
-#define DBX_NO_XREFS 1
-
-/* Don't split DBX symbols into continuations.  */
-#define DBX_CONTIN_LENGTH 0
-
-/* ------------------------------------------- */
-
-#define TARGET_DEFAULT 1
-
-/* These control the C++ compiler somehow.  */
-#define FASCIST_ASSEMBLER
-#define USE_COLLECT
-
-/* Print subsidiary information on the compiler version in use.  */
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (ns32k, UTek syntax)");
-
-/* The tek6100.h and tek6200.h files add stratos or merlin respectively. */
-
-#define CPP_PREDEFINES_Tek6000 \
-  "-Dns16000 -Dns32000 -Dns32k -Dns32016 -DUTek -DUTEK -Dbsd -DBSD \
-   -Asystem(unix) -Asystem(bsd) -Acpu(ns32k) -Amachine(ns32k)"
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES CPP_PREDEFINES_Tek6000
-
-/* This is how to align the code that follows an unconditional branch.
-   Don't define it, since it confuses the assembler (we hear).  */
-
-#undef LABEL_ALIGN_AFTER_BARRIER
-
-/* Assembler pseudo-op for shared data segment. */
-#define SHARED_SECTION_ASM_OP ".shdata"
-
-#ifdef UTEK_ASM
-#undef  FUNCTION_PROLOGUE
-
-/* This differs from the one in ns32k.h in printing a bitmask
-   rather than a register list in the enter or save instruction.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)     \
-{ register int regno, g_regs_used = 0;				\
-  int used_regs_buf[8], *bufp = used_regs_buf;			\
-  int used_fregs_buf[8], *fbufp = used_fregs_buf;		\
-  extern char call_used_regs[];					\
-  MAIN_FUNCTION_PROLOGUE;					\
-  for (regno = 0; regno < 8; regno++)				\
-    if (regs_ever_live[regno]					\
-	&& ! call_used_regs[regno])				\
-    {								\
-      *bufp++ = regno; g_regs_used++;				\
-    }								\
-  *bufp = -1;							\
-  for (; regno < 16; regno++)					\
-    if (regs_ever_live[regno] && !call_used_regs[regno]) {	\
-      *fbufp++ = regno;						\
-    }								\
-  *fbufp = -1;							\
-  bufp = used_regs_buf;						\
-  if (frame_pointer_needed)					\
-    fprintf (FILE, "\tenter ");					\
-  else if (g_regs_used)						\
-    fprintf (FILE, "\tsave ");					\
-  if (frame_pointer_needed || g_regs_used)			\
-    {								\
-      char mask = 0;						\
-      while (*bufp >= 0)					\
-	mask |= 1 << *bufp++;					\
-      fprintf (FILE, "$0x%x", (int) mask & 0xff);		\
-    }								\
-  if (frame_pointer_needed)					\
-    fprintf (FILE, ",$%d\n", SIZE);				\
-  else if (g_regs_used)						\
-    fprintf (FILE, "\n");					\
-  fbufp = used_fregs_buf;					\
-  while (*fbufp >= 0)						\
-    {								\
-      if ((*fbufp & 1) || (fbufp[0] != fbufp[1] - 1))		\
-	fprintf (FILE, "\tmovf f%d,tos\n", *fbufp++ - 8);	\
-      else							\
-	{							\
-	  fprintf (FILE, "\tmovl f%d,tos\n", fbufp[0] - 8);	\
-	  fbufp += 2;						\
-	}							\
-    }								\
-}
-
-#undef  FUNCTION_EPILOGUE
-
-/* This differs from the one in ns32k.h in printing a bitmask
-   rather than a register list in the exit or restore instruction.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-{ register int regno, g_regs_used = 0, f_regs_used = 0;		\
-  int used_regs_buf[8], *bufp = used_regs_buf;			\
-  int used_fregs_buf[8], *fbufp = used_fregs_buf;		\
-  extern char call_used_regs[];					\
-  *fbufp++ = -2;						\
-  for (regno = 8; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && !call_used_regs[regno]) {	\
-       *fbufp++ = regno; f_regs_used++;				\
-    }								\
-  fbufp--;							\
-  for (regno = 0; regno < 8; regno++)				\
-    if (regs_ever_live[regno]					\
-	&& ! call_used_regs[regno])				\
-    {                                                         	\
-      *bufp++ = regno; g_regs_used++;				\
-    }                                                         	\
-  while (fbufp > used_fregs_buf)				\
-    {								\
-      if ((*fbufp & 1) && fbufp[0] == fbufp[-1] + 1)		\
-	{							\
-	  fprintf (FILE, "\tmovl tos,f%d\n", fbufp[-1] - 8);	\
-	  fbufp -= 2;						\
-	}							\
-      else fprintf (FILE, "\tmovf tos,f%d\n", *fbufp-- - 8);	\
-    }								\
-  if (frame_pointer_needed)					\
-    fprintf (FILE, "\texit ");					\
-  else if (g_regs_used)						\
-    fprintf (FILE, "\trestore ");				\
-  if (g_regs_used || frame_pointer_needed)			\
-    {								\
-      char mask = 0;						\
-								\
-      while (bufp > used_regs_buf)				\
-	{							\
-	  /* Utek assembler takes care of reversing this */	\
-	  mask |= 1 << *--bufp;					\
-	}							\
-      fprintf (FILE, "$0x%x\n", (int) mask & 0xff);		\
-    }								\
-  if (current_function_pops_args)				\
-    fprintf (FILE, "\tret $%d\n", current_function_pops_args);	\
-  else fprintf (FILE, "\tret $0\n"); }
-
-/* UTek assembler needs "ret $0", not "ret 0". */
-#undef  TRANSFER_FROM_TRAMPOLINE
-#define TRANSFER_FROM_TRAMPOLINE	\
-void					\
-__transfer_from_trampoline ()		\
-{					\
-  asm ("___trampoline:");		\
-  asm ("movd 16(r2),tos");		\
-  asm ("movd 12(r2),r2");		\
-  asm ("ret $0");			\
-}
-
-#endif /* UTEK_ASM */
-
-#undef PRINT_OPERAND_ADDRESS
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  print_operand_address(FILE, ADDR)
-
-/* The UTek library supplies bcopy() and friends, not memcpy(). */
-#ifdef TARGET_MEM_FUNCTIONS
-#undef TARGET_MEM_FUNCTIONS
-#endif
diff --git a/gcc/config/ns32k/tek6100.h b/gcc/config/ns32k/tek6100.h
deleted file mode 100755
index e5b385f..0000000
--- a/gcc/config/ns32k/tek6100.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#include "ns32k/tek6000.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-Dns32000 -Dns32k -Dns16000 -Dns32016 -DUTek -DUTEK -Dbsd -DBSD -Dstratos \
-  -Asystem(unix) -Asystem(bsd) -Acpu(ns32k) -Amachine(ns32k)"
-
diff --git a/gcc/config/ns32k/tek6200.h b/gcc/config/ns32k/tek6200.h
deleted file mode 100755
index c03f255..0000000
--- a/gcc/config/ns32k/tek6200.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#include "ns32k/tek6000.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-Dns32000 -Dns32k -Dns16000 -Dns32016 -DUTek -DUTEK -Dbsd -DBSD -Dmerlin \
-  -Asystem(unix) -Asystem(bsd) -Acpu(ns32k) -Amachine(ns32k)"
-
diff --git a/gcc/config/ns32k/x-genix b/gcc/config/ns32k/x-genix
deleted file mode 100755
index 0598df8..0000000
--- a/gcc/config/ns32k/x-genix
+++ /dev/null
@@ -1,6 +0,0 @@
-# Makefile modifications for compilation on Genix.
-ALLOCA=alloca.o
-MALLOC = malloc.o
-
-# You must get malloc.c and getpagesize.h from GNU Emacs.
-
diff --git a/gcc/config/ns32k/xm-genix.h b/gcc/config/ns32k/xm-genix.h
deleted file mode 100755
index 15ff46f..0000000
--- a/gcc/config/ns32k/xm-genix.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* Config file for ns32k running system V.  */
-
-#include "ns32k/xm-ns32k.h"
-
-#define USG
diff --git a/gcc/config/ns32k/xm-netbsd.h b/gcc/config/ns32k/xm-netbsd.h
deleted file mode 100755
index 9d344dc..0000000
--- a/gcc/config/ns32k/xm-netbsd.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* Configuration for GCC for ns32k running NetBSD as host.  */
-
-#include <ns32k/xm-ns32k.h>
-
-/* ns32k/xm-ns32k.h defines these macros, but we don't need them */
-#undef memcmp
-#undef memcpy
-#undef memset
diff --git a/gcc/config/ns32k/xm-ns32k.h b/gcc/config/ns32k/xm-ns32k.h
deleted file mode 100755
index a5ef337..0000000
--- a/gcc/config/ns32k/xm-ns32k.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Configuration for GNU C-compiler for Vax.
-   Copyright (C) 1987, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
- 
-#define memcpy(src,dst,len) bcopy ((dst),(src),(len))
-#define memset gcc_memset
-#define memcmp(left,right,len) bcmp ((left),(right),(len))
diff --git a/gcc/config/ns32k/xm-pc532-min.h b/gcc/config/ns32k/xm-pc532-min.h
deleted file mode 100755
index 7097d7e..0000000
--- a/gcc/config/ns32k/xm-pc532-min.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef HZ
-#define HZ 60
-#endif
-
-#ifndef MAXPATHLEN
-#define MAXPATHLEN 1024
-#endif
diff --git a/gcc/config/pa/ee.asm b/gcc/config/pa/ee.asm
deleted file mode 100755
index 787bda7..0000000
--- a/gcc/config/pa/ee.asm
+++ /dev/null
@@ -1,261 +0,0 @@
-;  Subroutines for out of line prologues and epilogues on for the HPPA
-;  Copyright (C) 1994, 1995, 1996 Free Software Foundation, Inc.
-
-;  This file is part of GNU CC.
-
-;  GNU CC is free software; you can redistribute it and/or modify
-;  it under the terms of the GNU General Public License as published by
-;  the Free Software Foundation; either version 2, or (at your option)
-;  any later version.
-
-;  GNU CC is distributed in the hope that it will be useful,
-;  but WITHOUT ANY WARRANTY; without even the implied warranty of
-;  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;  GNU General Public License for more details.
-
-;  You should have received a copy of the GNU General Public License
-;  along with GNU CC; see the file COPYING.  If not, write to
-;  the Free Software Foundation, 59 Temple Place - Suite 330,
-;  Boston, MA 02111-1307, USA.
-
-	.SPACE $PRIVATE$
-	.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31
-	.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82
-	.SPACE $TEXT$
-	.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44
-	.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY
-	.SUBSPA $MILLICODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=8
-
-; This is an out-of-line prologue.
-;
-; It performs the following operations:
-;
-;	* Saves the return pointer at sp - 20
-;
-;	* Creates a new stack frame (sp'), size of the frame is passed in %r21
-;
-;	* The old stack pointer is saved at sp (frame pointer version only).
-;
-;	* Saves grs (passed in low 16 bits of %r22 into the stack frame
-;	at sp' + local_fsize (passed in %r19).
-;
-;	* Saves frs (passed in high 16 bits of %r22) into the stack
-;	frame at sp' + local_fsize (passed in %r19).
-;
-;	* Sets up a frame pointer (in %r3) (frame pointer version only).
-;
-;	* Returns to the instruction _immediately_ after the call to
-;	this function.
-
-	.SPACE $TEXT$
-	.SUBSPA $MILLICODE$
-	.EXPORT __outline_prologue,MILLICODE
-	.align 32
-__outline_prologue
-	.PROC
-	.CALLINFO FRAME=0,NO_CALLS
-	.ENTRY
-	copy %r30,%r20
-
-	; Subtract 4 from our return pointer so that we return to
-	; the right location.
-        ldo -4(%r31),%r31
-
-	; Save off %r2
-	stw %r2,-20(0,%r30)
-
-	; Make our new frame.
-	add %r21,%r30,%r30
-
-	; Add in local_fsize to our frame pointer so we do register
-	; saves into the right place
-	add %r20,%r19,%r20
-
-	; %r22 tells us what registers we need to save.  The upper half
-	; is for fp registers, the lower half for integer registers.
-	; We put the lower half in %r1 and the upper half into %r22
-	; for later use.
-	extru %r22,31,16,%r1
-	extrs %r22,15,16,%r22
-
-	; %r1 now olds a value 0-18 which corresponds to the number
-	; of grs we need to save.  We need to reverse that value so
-	; we can just into the table and straight-line execute to the
-	; end of the gr saves.
-	comb,= %r0,%r1,L$0000
-	subi 18,%r1,%r1
-	blr,n %r1,%r0
-	b,n L$0000
-	stws,ma %r18,4(0,%r20)
-	nop
-	stws,ma %r17,4(0,%r20)
-	nop
-	stws,ma %r16,4(0,%r20)
-	nop
-	stws,ma %r15,4(0,%r20)
-	nop
-	stws,ma %r14,4(0,%r20)
-	nop
-	stws,ma %r13,4(0,%r20)
-	nop
-	stws,ma %r12,4(0,%r20)
-	nop
-	stws,ma %r11,4(0,%r20)
-	nop
-	stws,ma %r10,4(0,%r20)
-	nop
-	stws,ma %r9,4(0,%r20)
-	nop
-	stws,ma %r8,4(0,%r20)
-	nop
-	stws,ma %r7,4(0,%r20)
-	nop
-	stws,ma %r6,4(0,%r20)
-	nop
-	stws,ma %r5,4(0,%r20)
-	nop
-	stws,ma %r4,4(0,%r20)
-	nop
-	stws,ma %r3,4(0,%r20)
-	nop
-L$0000
-	; All gr saves are done.  Align the temporary frame pointer and
-	; do the fr saves.
-	ldo 7(%r20),%r20
-	depi 0,31,3,%r20
-
-	comb,= %r0,%r22,L$0001
-	subi 21,%r22,%r22
-	blr,n %r22,%r0
-	b,n L$0001
-	fstws,ma %fr21,8(0,%r20)
-	nop
-	fstws,ma %fr20,8(0,%r20)
-	nop
-	fstws,ma %fr19,8(0,%r20)
-	nop
-	fstws,ma %fr18,8(0,%r20)
-	nop
-	fstws,ma %fr17,8(0,%r20)
-	nop
-	fstws,ma %fr16,8(0,%r20)
-	nop
-	fstws,ma %fr15,8(0,%r20)
-	nop
-	fstws,ma %fr14,8(0,%r20)
-	nop
-	fstws,ma %fr13,8(0,%r20)
-	nop
-	fstws,ma %fr12,8(0,%r20)
-	nop
-L$0001
-	; Return
-	bv,n 0(%r31)
-	.EXIT
-	.PROCEND
-
-
-
-	.EXPORT __outline_epilogue,MILLICODE
-	.align 32
-__outline_epilogue
-	.PROC
-	.CALLINFO FRAME=0,NO_CALLS
-	.ENTRY
-	; Get our original stack pointer and put it in %r20
-	sub %r30,%r21,%r20
-
-	; Subtract 4 from our return pointer so that we return to
-	; the right location.
-        ldo -4(%r31),%r31
-
-	; Reload %r2
-	ldw -20(0,%r20),%r2
-
-	; Add in local_fsize (%r19) to the frame pointer to find
-	; the saved registers.
-	add %r20,%r19,%r20
-
-	; %r22 tells us what registers we need to restore.  The upper half
-	; is for fp registers, the lower half for integer registers.
-	; We put the lower half in %r1 and the upper half into %r22
-	; for later use.
-	extru %r22,31,16,%r1
-	extrs %r22,15,16,%r22
-
-	; %r1 now olds a value 0-18 which corresponds to the number
-	; of grs we need to restore.  We need to reverse that value so
-	; we can just into the table and straight-line execute to the
-	; end of the gr restore.
-	comb,= %r0,%r1,L$0004
-	subi 18,%r1,%r1
-	blr,n %r1,%r0
-	b,n L$0004
-	ldws,ma 4(0,%r20),%r18
-	nop
-	ldws,ma 4(0,%r20),%r17
-	nop
-	ldws,ma 4(0,%r20),%r16
-	nop
-	ldws,ma 4(0,%r20),%r15
-	nop
-	ldws,ma 4(0,%r20),%r14
-	nop
-	ldws,ma 4(0,%r20),%r13
-	nop
-	ldws,ma 4(0,%r20),%r12
-	nop
-	ldws,ma 4(0,%r20),%r11
-	nop
-	ldws,ma 4(0,%r20),%r10
-	nop
-	ldws,ma 4(0,%r20),%r9
-	nop
-	ldws,ma 4(0,%r20),%r8
-	nop
-	ldws,ma 4(0,%r20),%r7
-	nop
-	ldws,ma 4(0,%r20),%r6
-	nop
-	ldws,ma 4(0,%r20),%r5
-	nop
-	ldws,ma 4(0,%r20),%r4
-	nop
-	ldws,ma 4(0,%r20),%r3
-	nop
-L$0004
-	; All gr restore are done.  Align the temporary frame pointer and
-	; do the fr restore.
-	ldo 7(%r20),%r20
-	depi 0,31,3,%r20
-
-	comb,= %r0,%r22,L$0005
-	subi 21,%r22,%r22
-	blr,n %r22,%r0
-	b,n L$0005
-	fldws,ma 8(0,%r20),%fr21
-	nop
-	fldws,ma 8(0,%r20),%fr20
-	nop
-	fldws,ma 8(0,%r20),%fr19
-	nop
-	fldws,ma 8(0,%r20),%fr18
-	nop
-	fldws,ma 8(0,%r20),%fr17
-	nop
-	fldws,ma 8(0,%r20),%fr16
-	nop
-	fldws,ma 8(0,%r20),%fr15
-	nop
-	fldws,ma 8(0,%r20),%fr14
-	nop
-	fldws,ma 8(0,%r20),%fr13
-	nop
-	fldws,ma 8(0,%r20),%fr12
-	nop
-L$0005
-	; Return and deallocate our frame.
-	bv 0(%r31)
-	sub %r30,%r21,%r30
-	.EXIT
-	.PROCEND
diff --git a/gcc/config/pa/ee_fp.asm b/gcc/config/pa/ee_fp.asm
deleted file mode 100755
index ef040cf..0000000
--- a/gcc/config/pa/ee_fp.asm
+++ /dev/null
@@ -1,274 +0,0 @@
-;  Subroutines for out of line prologues and epilogues on for the HPPA
-;  Copyright (C) 1994, 1995, 1996 Free Software Foundation, Inc.
-
-;  This file is part of GNU CC.
-
-;  GNU CC is free software; you can redistribute it and/or modify
-;  it under the terms of the GNU General Public License as published by
-;  the Free Software Foundation; either version 2, or (at your option)
-;  any later version.
-
-;  GNU CC is distributed in the hope that it will be useful,
-;  but WITHOUT ANY WARRANTY; without even the implied warranty of
-;  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;  GNU General Public License for more details.
-
-;  You should have received a copy of the GNU General Public License
-;  along with GNU CC; see the file COPYING.  If not, write to
-;  the Free Software Foundation, 59 Temple Place - Suite 330,
-;  Boston, MA 02111-1307, USA.
-
-	.SPACE $PRIVATE$
-	.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31
-	.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82
-	.SPACE $TEXT$
-	.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44
-	.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY
-	.SUBSPA $MILLICODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=8
-
-
-; This is an out-of-line prologue.
-;
-; It performs the following operations:
-;
-;	* Saves the return pointer at sp - 20
-;
-;	* Creates a new stack frame (sp'), size of the frame is passed in %r21
-;
-;	* The old stack pointer is saved at sp (frame pointer version only).
-;
-;	* Saves grs (passed in low 16 bits of %r22 into the stack frame
-;	at sp' + local_fsize (passed in %r19).
-;
-;	* Saves frs (passed in high 16 bits of %r22) into the stack
-;	frame at sp' + local_fsize (passed in %r19).
-;
-;	* Sets up a frame pointer (in %r3) (frame pointer version only).
-;
-;	* Returns to the instruction _immediately_ after the call to
-;	this function.
-
-	.SPACE $TEXT$
-	.SUBSPA $MILLICODE$
-	.EXPORT __outline_prologue_fp,MILLICODE
-	.align 32
-__outline_prologue_fp
-	.PROC
-	.CALLINFO FRAME=0,NO_CALLS
-	.ENTRY
-	copy %r30,%r20
-
-	; Subtract 4 from our return pointer so that we return to
-	; the right location.
-        ldo -4(%r31),%r31
-
-	; Save off %r2
-	stw %r2,-20(0,%r30)
-
-	; Make our new frame.
-	add %r21,%r30,%r30
-
-	; Save our old stack pointer.
-	stw %r20,0(0,%r20)
-
-	; Add in local_fsize to our frame pointer so we do register
-	; saves into the right place
-	add %r20,%r19,%r20
-
-	; %r22 tells us what registers we need to save.  The upper half
-	; is for fp registers, the lower half for integer registers.
-	; We put the lower half in %r1 and the upper half into %r22
-	; for later use.
-	extru %r22,31,16,%r1
-	extrs %r22,15,16,%r22
-
-	; %r1 now olds a value 0-18 which corresponds to the number
-	; of grs we need to save.  We need to reverse that value so
-	; we can just into the table and straight-line execute to the
-	; end of the gr saves.
-	comb,= %r0,%r1,L$0002
-	subi 18,%r1,%r1
-	blr,n %r1,%r0
-	b,n L$0002
-	stws,ma %r18,4(0,%r20)
-	nop
-	stws,ma %r17,4(0,%r20)
-	nop
-	stws,ma %r16,4(0,%r20)
-	nop
-	stws,ma %r15,4(0,%r20)
-	nop
-	stws,ma %r14,4(0,%r20)
-	nop
-	stws,ma %r13,4(0,%r20)
-	nop
-	stws,ma %r12,4(0,%r20)
-	nop
-	stws,ma %r11,4(0,%r20)
-	nop
-	stws,ma %r10,4(0,%r20)
-	nop
-	stws,ma %r9,4(0,%r20)
-	nop
-	stws,ma %r8,4(0,%r20)
-	nop
-	stws,ma %r7,4(0,%r20)
-	nop
-	stws,ma %r6,4(0,%r20)
-	nop
-	stws,ma %r5,4(0,%r20)
-	nop
-	stws,ma %r4,4(0,%r20)
-	nop
-	stws,ma %r3,4(0,%r20)
-	nop
-L$0002
-	; All gr saves are done.  Align the temporary frame pointer and
-	; do the fr saves.
-	ldo 7(%r20),%r20
-	depi 0,31,3,%r20
-
-	comb,= %r0,%r22,L$0003
-	subi 21,%r22,%r22
-	blr,n %r22,%r0
-	b,n L$0003
-	fstws,ma %fr21,8(0,%r20)
-	nop
-	fstws,ma %fr20,8(0,%r20)
-	nop
-	fstws,ma %fr19,8(0,%r20)
-	nop
-	fstws,ma %fr18,8(0,%r20)
-	nop
-	fstws,ma %fr17,8(0,%r20)
-	nop
-	fstws,ma %fr16,8(0,%r20)
-	nop
-	fstws,ma %fr15,8(0,%r20)
-	nop
-	fstws,ma %fr14,8(0,%r20)
-	nop
-	fstws,ma %fr13,8(0,%r20)
-	nop
-	fstws,ma %fr12,8(0,%r20)
-	nop
-L$0003
-	; Return, setting up a frame pointer in the delay slot
-	bv 0(%r31)
-	sub %r30,%r21,%r3
-	.EXIT
-	.PROCEND
-
-
-; This is an out-of-line epilogue.  It's operation is basically the reverse
-; of the out-of-line prologue.
-
-	.EXPORT __outline_epilogue_fp,MILLICODE
-	.align 32
-__outline_epilogue_fp
-	.PROC
-	.CALLINFO FRAME=0,NO_CALLS
-	.ENTRY
-	; Make a copy of our frame pointer into %r20
-	copy %r3,%r20
-
-	; Subtract 4 from our return pointer so that we return to
-	; the right location.
-        ldo -4(%r31),%r31
-
-	; Reload %r2
-	; First save off %r2
-	ldw -20(0,%r20),%r2
-
-	; Load our old stack pointer, save it in %r21.
-	ldw 0(0,%r20),%r21
-
-	; Add in local_fsize (%r19) to the frame pointer to find
-	; the saved registers.
-	add %r20,%r19,%r20
-
-	; %r22 tells us what registers we need to restore.  The upper half
-	; is for fp registers, the lower half for integer registers.
-	; We put the lower half in %r1 and the upper half into %r22
-	; for later use.
-	extru %r22,31,16,%r1
-	extrs %r22,15,16,%r22
-
-	; %r1 now olds a value 0-18 which corresponds to the number
-	; of grs we need to restore.  We need to reverse that value so
-	; we can just into the table and straight-line execute to the
-	; end of the gr restore.
-	comb,= %r0,%r1,L$0006
-	subi 18,%r1,%r1
-	blr,n %r1,%r0
-	b,n L$0006
-	ldws,ma 4(0,%r20),%r18
-	nop
-	ldws,ma 4(0,%r20),%r17
-	nop
-	ldws,ma 4(0,%r20),%r16
-	nop
-	ldws,ma 4(0,%r20),%r15
-	nop
-	ldws,ma 4(0,%r20),%r14
-	nop
-	ldws,ma 4(0,%r20),%r13
-	nop
-	ldws,ma 4(0,%r20),%r12
-	nop
-	ldws,ma 4(0,%r20),%r11
-	nop
-	ldws,ma 4(0,%r20),%r10
-	nop
-	ldws,ma 4(0,%r20),%r9
-	nop
-	ldws,ma 4(0,%r20),%r8
-	nop
-	ldws,ma 4(0,%r20),%r7
-	nop
-	ldws,ma 4(0,%r20),%r6
-	nop
-	ldws,ma 4(0,%r20),%r5
-	nop
-	ldws,ma 4(0,%r20),%r4
-	nop
-	ldws,ma 4(0,%r20),%r3
-	nop
-L$0006
-	; All gr restore are done.  Align the temporary frame pointer and
-	; do the fr restore.
-	ldo 7(%r20),%r20
-	depi 0,31,3,%r20
-
-	comb,= %r0,%r22,L$0007
-	subi 21,%r22,%r22
-	blr,n %r22,%r0
-	b,n L$0007
-	fldws,ma 8(0,%r20),%fr21
-	nop
-	fldws,ma 8(0,%r20),%fr20
-	nop
-	fldws,ma 8(0,%r20),%fr19
-	nop
-	fldws,ma 8(0,%r20),%fr18
-	nop
-	fldws,ma 8(0,%r20),%fr17
-	nop
-	fldws,ma 8(0,%r20),%fr16
-	nop
-	fldws,ma 8(0,%r20),%fr15
-	nop
-	fldws,ma 8(0,%r20),%fr14
-	nop
-	fldws,ma 8(0,%r20),%fr13
-	nop
-	fldws,ma 8(0,%r20),%fr12
-	nop
-L$0007
-	; Return and deallocate our frame.
-	bv 0(%r31)
-	copy %r21,%r30
-	.EXIT
-	.PROCEND
-
-
diff --git a/gcc/config/pa/lib1funcs.asm b/gcc/config/pa/lib1funcs.asm
deleted file mode 100755
index 95eb75e..0000000
--- a/gcc/config/pa/lib1funcs.asm
+++ /dev/null
@@ -1,1146 +0,0 @@
-;  Low level integer divide, multiply, remainder, etc routines for the HPPA.
-;  Copyright (C) 1995 Free Software Foundation, Inc.
-
-;  This file is part of GNU CC.
-
-;  GNU CC is free software; you can redistribute it and/or modify
-;  it under the terms of the GNU General Public License as published by
-;  the Free Software Foundation; either version 2, or (at your option)
-;  any later version.
-
-; In addition to the permissions in the GNU General Public License, the
-; Free Software Foundation gives you unlimited permission to link the
-; compiled version of this file with other programs, and to distribute
-; those programs without any restriction coming from the use of this
-; file.  (The General Public License restrictions do apply in other
-; respects; for example, they cover modification of the file, and
-; distribution when not linked into another program.)
-
-;  GNU CC is distributed in the hope that it will be useful,
-;  but WITHOUT ANY WARRANTY; without even the implied warranty of
-;  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;  GNU General Public License for more details.
-
-;  You should have received a copy of the GNU General Public License
-;  along with GNU CC; see the file COPYING.  If not, write to
-;  the Free Software Foundation, 59 Temple Place - Suite 330,
-;  Boston, MA 02111-1307, USA.
-
-#ifdef L_dyncall
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.export	$$dyncall
-$$dyncall
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	bb,>=,n	%r22,30,L$1		; branch if not plabel address
-	depi	0,31,2,%r22		; clear the two least significant bits
-	ldw	4(%sr0,%r22),%r19	; load new LTP value
-	ldw	0(%sr0,%r22),%r22	; load address of target
-L$1	ldsid	(%sr0,%r22),%r1		; get the "space ident" selected by r22
-	mtsp	%r1,%sr0		; move that space identifier into sr0
-	be	0(%sr0,%r22)		; branch to the real target
-	stw	%r2,-24(%sr0,%r30)	; save return address into frame marker
-	.exit
-	.procend
-#endif
-
-
-#ifdef L_multiply
-#define	op0	%r26
-#define	op1	%r25
-#define res	%r29
-#define ret	%r31
-#define tmp	%r1
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align 4
-	.export	$$mulU
-	.export	$$mulI
-$$mulU
-$$mulI
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	addi,tr		0,%r0,res	; clear out res, skip next insn
-L$loop	zdep		op1,26,27,op1	; shift up op1 by 5
-L$lo	zdep		op0,30,5,tmp	; extract next 5 bits and shift up
-	blr		tmp,%r0
-	extru		op0,26,27,op0	; shift down op0 by 5
-L$0	comib,<>	0,op0,L$lo
-	zdep		op1,26,27,op1	; shift up op1 by 5
-	bv		%r0(ret)
-	nop
-L$1	b		L$loop
-	addl		op1,res,res
-	nop
-	nop
-L$2	b		L$loop
-	sh1addl		op1,res,res
-	nop
-	nop
-L$3	sh1addl		op1,op1,tmp	; 3x
-	b		L$loop
-	addl		tmp,res,res
-	nop
-L$4	b		L$loop
-	sh2addl		op1,res,res
-	nop
-	nop
-L$5	sh2addl		op1,op1,tmp	; 5x
-	b		L$loop
-	addl		tmp,res,res
-	nop
-L$6	sh1addl		op1,op1,tmp	; 3x
-	b		L$loop
-	sh1addl		tmp,res,res
-	nop
-L$7	zdep		op1,28,29,tmp	; 8x
-	sub		tmp,op1,tmp	; 7x
-	b		L$loop
-	addl		tmp,res,res
-L$8	b		L$loop
-	sh3addl		op1,res,res
-	nop
-	nop
-L$9	sh3addl		op1,op1,tmp	; 9x
-	b		L$loop
-	addl		tmp,res,res
-	nop
-L$10	sh2addl		op1,op1,tmp	; 5x
-	b		L$loop
-	sh1addl		tmp,res,res
-	nop
-L$11	sh2addl		op1,op1,tmp	; 5x
-	sh1addl		tmp,op1,tmp	; 11x
-	b		L$loop
-	addl		tmp,res,res
-L$12	sh1addl		op1,op1,tmp	; 3x
-	b		L$loop
-	sh2addl		tmp,res,res
-	nop
-L$13	sh1addl		op1,op1,tmp	; 3x
-	sh2addl		tmp,op1,tmp	; 13x
-	b		L$loop
-	addl		tmp,res,res
-L$14	zdep		op1,28,29,tmp	; 8x
-	sub		tmp,op1,tmp	; 7x
-	b		L$loop
-	sh1addl		tmp,res,res
-L$15	zdep		op1,27,28,tmp	; 16x
-	sub		tmp,op1,tmp	; 15x
-	b		L$loop
-	addl		tmp,res,res
-L$16	zdep		op1,27,28,tmp	; 16x
-	b		L$loop
-	addl		tmp,res,res
-	nop
-L$17	zdep		op1,27,28,tmp	; 16x
-	addl		tmp,op1,tmp	; 17x
-	b		L$loop
-	addl		tmp,res,res
-L$18	sh3addl		op1,op1,tmp	; 9x
-	b		L$loop
-	sh1addl		tmp,res,res
-	nop
-L$19	sh3addl		op1,op1,tmp	; 9x
-	sh1addl		tmp,op1,tmp	; 19x
-	b		L$loop
-	addl		tmp,res,res
-L$20	sh2addl		op1,op1,tmp	; 5x
-	b		L$loop
-	sh2addl		tmp,res,res
-	nop
-L$21	sh2addl		op1,op1,tmp	; 5x
-	sh2addl		tmp,op1,tmp	; 21x
-	b		L$loop
-	addl		tmp,res,res
-L$22	sh2addl		op1,op1,tmp	; 5x
-	sh1addl		tmp,op1,tmp	; 11x
-	b		L$loop
-	sh1addl		tmp,res,res
-L$23	sh1addl		op1,op1,tmp	; 3x
-	sh3addl		tmp,res,res	; += 8x3
-	b		L$loop
-	sub		res,op1,res	; -= x
-L$24	sh1addl		op1,op1,tmp	; 3x
-	b		L$loop
-	sh3addl		tmp,res,res	; += 8x3
-	nop
-L$25	sh2addl		op1,op1,tmp	; 5x
-	sh2addl		tmp,tmp,tmp	; 25x
-	b		L$loop
-	addl		tmp,res,res
-L$26	sh1addl		op1,op1,tmp	; 3x
-	sh2addl		tmp,op1,tmp	; 13x
-	b		L$loop
-	sh1addl		tmp,res,res	; += 2x13
-L$27	sh1addl		op1,op1,tmp	; 3x
-	sh3addl		tmp,tmp,tmp	; 27x
-	b		L$loop
-	addl		tmp,res,res
-L$28	zdep		op1,28,29,tmp	; 8x
-	sub		tmp,op1,tmp	; 7x
-	b		L$loop
-	sh2addl		tmp,res,res	; += 4x7
-L$29	sh1addl		op1,op1,tmp	; 3x
-	sub		res,tmp,res	; -= 3x
-	b		L$foo
-	zdep		op1,26,27,tmp	; 32x
-L$30	zdep		op1,27,28,tmp	; 16x
-	sub		tmp,op1,tmp	; 15x
-	b		L$loop
-	sh1addl		tmp,res,res	; += 2x15
-L$31	zdep		op1,26,27,tmp	; 32x
-	sub		tmp,op1,tmp	; 31x
-L$foo	b		L$loop
-	addl		tmp,res,res
-	.exit
-	.procend
-#endif
-
-
-#ifdef L_divU
-#define dividend %r26
-#define divisor %r25
-#define tmp %r1
-#define quotient %r29
-#define ret %r31
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align 4
-	.export	$$divU
-$$divU
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	comb,<		divisor,0,L$largedivisor
-	 sub		%r0,divisor,%r1		; clear cy as side-effect
-	ds		%r0,%r1,%r0
-	addc		dividend,dividend,dividend
-	ds		%r0,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,quotient
-	ds		%r1,divisor,%r1
-	bv		0(ret)
-	addc		quotient,quotient,quotient
-L$largedivisor
-	comclr,<<	dividend,divisor,quotient
-	ldi		1,quotient
-	bv,n		0(ret)
-	.exit
-	.procend
-#endif
-
-
-#ifdef L_remU
-#define dividend %r26
-#define divisor %r25
-#define quotient %r29
-#define tmp %r1
-#define ret %r31
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align 4
-	.export	$$remU
-$$remU
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	comb,<		divisor,0,L$largedivisor
-	 sub		%r0,divisor,%r1		; clear cy as side-effect
-	ds		%r0,%r1,%r0
-	addc		dividend,dividend,dividend
-	ds		%r0,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,quotient
-	ds		%r1,divisor,%r1
-	comclr,>=	%r1,%r0,%r0
-	addl		%r1,divisor,%r1
-	bv		0(ret)
-	copy		%r1,quotient
-L$largedivisor
-	sub,>>=		dividend,divisor,quotient
-	copy		dividend,quotient
-	bv,n		0(ret)
-	.exit
-	.procend
-#endif
-
-
-#ifdef L_divI
-#define dividend %r26
-#define divisor %r25
-#define quotient %r29
-#define tmp %r1
-#define ret %r31
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align 4
-	.export	$$divI
-$$divI
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	xor		dividend,divisor,quotient	; result sign
-	comclr,>=	divisor,%r0,%r0			; get absolute values
-	sub		%r0,divisor,divisor
-	comclr,>=	dividend,%r0,%r0
-	sub		%r0,dividend,dividend
-
-	comb,<		divisor,0,L$largedivisor
-	 sub		%r0,divisor,%r1		; clear cy as side-effect
-	ds		%r0,%r1,%r0
-	addc		dividend,dividend,dividend
-	ds		%r0,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	comclr,>=	%r1,%r0,%r0
-	addl		%r1,divisor,%r1
-	comclr,>=	quotient,%r0,%r0	; skip of no need to negate
-	sub		%r0,dividend,dividend
-	bv		0(ret)
-	copy		dividend,quotient
-L$largedivisor
-	comclr,<<	dividend,divisor,quotient
-	ldi		1,quotient
-	bv,n		0(ret)
-	.exit
-	.procend
-#endif
-
-
-#ifdef L_remI
-#define dividend %r26
-#define divisor %r25
-#define quotient %r29
-#define tmp %r1
-#define ret %r31
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align 4
-	.export	$$remI
-$$remI
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	xor		dividend,%r0,quotient		; result sign
-	comclr,>=	divisor,%r0,%r0			; get absolute values
-	sub		%r0,divisor,divisor
-	comclr,>=	dividend,%r0,%r0
-	sub		%r0,dividend,dividend
-
-	comb,<		divisor,0,L$largedivisor
-	 sub		%r0,divisor,%r1		; clear cy as side-effect
-	ds		%r0,%r1,%r0
-	addc		dividend,dividend,dividend
-	ds		%r0,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	ds		%r1,divisor,%r1
-	addc		dividend,dividend,dividend
-	comclr,>=	%r1,%r0,%r0
-	addl		%r1,divisor,%r1
-	comclr,>=	quotient,%r0,%r0	; skip of no need to negate
-	sub		%r0,%r1,%r1
-	bv		0(ret)
-	copy		%r1,quotient
-L$largedivisor
-	sub,>>=		dividend,divisor,quotient
-	copy		dividend,quotient
-	bv,n		0(ret)
-	.exit
-	.procend
-#endif
-
-
-#if defined (L_divU_3) && !defined (SMALL_LIB)
-#undef L_divU_3
-#define dividend %r26
-#define divisor %r25
-#define tmp %r1
-#define result %r29
-#define ret %r31
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align 4
-	.export	$$divU_3
-$$divU_3
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	sh2add	%r26,%r26,%r29		; r29 = lo(101 x r)
-	shd	%r0,%r26,30,%r1		;  r1 = hi(100 x r)
-	addc	%r1,%r0,%r1		;  r1 = hi(101 x r)
-; r in r1,,r29
-	zdep	%r29,27,28,%r25		; r25 = lo(10000 x r)
-	add	%r25,%r29,%r25		; r25 = lo(10001 x r)
-	shd	%r1,%r29,28,%r29	; r29 = hi(10000 x r)
-	addc	%r29,%r1,%r29		; r29 = hi(10001 x r)
-; r in r29,,r25
-	zdep	%r25,23,24,%r1		;  r1 = lo(100000000 x r)
-	add	%r1,%r25,%r1		;  r1 = lo(100000001 x r)
-	shd	%r29,%r25,24,%r25	; r25 = hi(100000000 x r)
-	addc	%r25,%r29,%r25		; r25 = hi(100000001 x r)
-; r in r25,,r1
-	zdep	%r1,15,16,%r29
-	add	%r29,%r1,%r29
-	shd	%r25,%r1,16,%r1
-	addc	%r1,%r25,%r1
-; r in r1,,r29
-	sh1add	%r29,%r26,%r0		;  r0 = lo(10 x r) + dividend
-	shd	%r1,%r29,31,%r29	; r29 = hi(10 x r)
-	addc	%r29,%r0,%r29
-	bv	0(ret)
-	extru	%r29,30,31,result
-	.exit
-	.procend
-#endif
-
-
-#if defined (L_divU_5) && !defined (SMALL_LIB)
-#undef L_divU_5
-#define dividend %r26
-#define divisor %r25
-#define tmp %r1
-#define result %r29
-#define ret %r31
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align 4
-	.export	$$divU_5
-$$divU_5
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	sh1add	%r26,%r26,%r29		; r29 = lo(11 x r)
-	shd	%r0,%r26,31,%r1		;  r1 = hi(10 x r)
-	addc	%r1,%r0,%r1		;  r1 = hi(11 x r)
-; r in r1,,r29
-	zdep	%r29,27,28,%r25		; r25 = lo(10000 x r)
-	add	%r25,%r29,%r25		; r25 = lo(10001 x r)
-	shd	%r1,%r29,28,%r29	; r29 = hi(10000 x r)
-	addc	%r29,%r1,%r29		; r29 = hi(10001 x r)
-; r in r29,,r25
-	zdep	%r25,23,24,%r1		;  r1 = lo(100000000 x r)
-	add	%r1,%r25,%r1		;  r1 = lo(100000001 x r)
-	shd	%r29,%r25,24,%r25	; r25 = hi(100000000 x r)
-	addc	%r25,%r29,%r25		; r25 = hi(100000001 x r)
-; r in r25,,r1
-	zdep	%r1,15,16,%r29
-	add	%r29,%r1,%r29
-	shd	%r25,%r1,16,%r1
-	addc	%r1,%r25,%r1
-; r in r1,,r29
-	sh2add	%r29,%r26,%r0		;  r0 = lo(1000 x r) + dividend
-	shd	%r1,%r29,30,%r29	; r29 = hi(1000 x r)
-	addc	%r29,%r0,%r29
-	bv	0(ret)
-	extru	%r29,29,30,result
-	.exit
-	.procend
-#endif
-
-
-#if defined (L_divU_6) && !defined (SMALL_LIB)
-#undef L_divU_6
-#define dividend %r26
-#define divisor %r25
-#define tmp %r1
-#define result %r29
-#define ret %r31
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align 4
-	.export	$$divU_6
-$$divU_6
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	sh2add	%r26,%r26,%r29		; r29 = lo(101 x r)
-	shd	%r0,%r26,30,%r1		;  r1 = hi(100 x r)
-	addc	%r1,%r0,%r1		;  r1 = hi(101 x r)
-; r in r1,,r29
-	zdep	%r29,27,28,%r25		; r25 = lo(10000 x r)
-	add	%r25,%r29,%r25		; r25 = lo(10001 x r)
-	shd	%r1,%r29,28,%r29	; r29 = hi(10000 x r)
-	addc	%r29,%r1,%r29		; r29 = hi(10001 x r)
-; r in r29,,r25
-	zdep	%r25,23,24,%r1		;  r1 = lo(100000000 x r)
-	add	%r1,%r25,%r1		;  r1 = lo(100000001 x r)
-	shd	%r29,%r25,24,%r25	; r25 = hi(100000000 x r)
-	addc	%r25,%r29,%r25		; r25 = hi(100000001 x r)
-; r in r25,,r1
-	zdep	%r1,15,16,%r29
-	add	%r29,%r1,%r29
-	shd	%r25,%r1,16,%r1
-	addc	%r1,%r25,%r1
-; r in r1,,r29
-	sh1add	%r29,%r26,%r0		;  r0 = lo(10 x r) + dividend
-	shd	%r1,%r29,31,%r29	; r29 = hi(10 x r)
-	addc	%r29,%r0,%r29
-	bv	0(ret)
-	extru	%r29,29,30,result
-	.exit
-	.procend
-#endif
-
-
-#if defined (L_divU_9) && !defined (SMALL_LIB)
-#undef L_divU_9
-#define dividend %r26
-#define divisor %r25
-#define tmp %r1
-#define result %r29
-#define ret %r31
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align 4
-	.export	$$divU_9
-$$divU_9
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	zdep	%r26,28,29,%r29
-	sub	%r29,%r26,%r29
-	shd	0,%r26,29,%r1
-	subb	%r1,0,%r1		/* 111 */
-
-	zdep	%r29,25,26,%r25
-	add	%r25,%r29,%r25
-	shd	%r1,%r29,26,%r29
-	addc	%r29,%r1,%r29		/* 111000111 */
-
-	sh3add	%r25,%r26,%r1
-	shd	%r29,%r25,29,%r25
-	addc	%r25,0,%r25		/* 111000111001 */
-
-	zdep	%r1,16,17,%r29
-	sub	%r29,%r1,%r29
-	shd	%r25,%r1,17,%r1
-	subb	%r1,%r25,%r1		/* 111000111000111000111000111 */
-
-	sh3add	%r29,%r26,%r0
-	shd	%r1,%r29,29,%r29
-	addc	%r29,0,%r29		/* 111000111000111000111000111001 */
-	bv	0(ret)
-	extru	%r29,30,31,result
-	.exit
-	.procend
-#endif
-
-
-#if defined (L_divU_10) && !defined (SMALL_LIB)
-#undef L_divU_10
-#define dividend %r26
-#define divisor %r25
-#define tmp %r1
-#define result %r29
-#define ret %r31
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align 4
-	.export	$$divU_10
-$$divU_10
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	sh1add	%r26,%r26,%r29		; r29 = lo(11 x r)
-	shd	%r0,%r26,31,%r1		;  r1 = hi(10 x r)
-	addc	%r1,%r0,%r1		;  r1 = hi(11 x r)
-; r in r1,,r29
-	zdep	%r29,27,28,%r25		; r25 = lo(10000 x r)
-	add	%r25,%r29,%r25		; r25 = lo(10001 x r)
-	shd	%r1,%r29,28,%r29	; r29 = hi(10000 x r)
-	addc	%r29,%r1,%r29		; r29 = hi(10001 x r)
-; r in r29,,r25
-	zdep	%r25,23,24,%r1		;  r1 = lo(100000000 x r)
-	add	%r1,%r25,%r1		;  r1 = lo(100000001 x r)
-	shd	%r29,%r25,24,%r25	; r25 = hi(100000000 x r)
-	addc	%r25,%r29,%r25		; r25 = hi(100000001 x r)
-; r in r25,,r1
-	zdep	%r1,15,16,%r29
-	add	%r29,%r1,%r29
-	shd	%r25,%r1,16,%r1
-	addc	%r1,%r25,%r1
-; r in r1,,r29
-	sh2add	%r29,%r26,%r0		;  r0 = lo(1000 x r) + dividend
-	shd	%r1,%r29,30,%r29	; r29 = hi(1000 x r)
-	addc	%r29,%r0,%r29
-	bv	0(ret)
-	extru	%r29,28,29,result
-	.exit
-	.procend
-#endif
-
-
-#if defined (L_divU_12) && !defined (SMALL_LIB)
-#undef L_divU_12
-#define dividend %r26
-#define divisor %r25
-#define tmp %r1
-#define result %r29
-#define ret %r31
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align 4
-	.export	$$divU_12
-$$divU_12
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	sh2add	%r26,%r26,%r29		; r29 = lo(101 x r)
-	shd	%r0,%r26,30,%r1		;  r1 = hi(100 x r)
-	addc	%r1,%r0,%r1		;  r1 = hi(101 x r)
-; r in r1,,r29
-	zdep	%r29,27,28,%r25		; r25 = lo(10000 x r)
-	add	%r25,%r29,%r25		; r25 = lo(10001 x r)
-	shd	%r1,%r29,28,%r29	; r29 = hi(10000 x r)
-	addc	%r29,%r1,%r29		; r29 = hi(10001 x r)
-; r in r29,,r25
-	zdep	%r25,23,24,%r1		;  r1 = lo(100000000 x r)
-	add	%r1,%r25,%r1		;  r1 = lo(100000001 x r)
-	shd	%r29,%r25,24,%r25	; r25 = hi(100000000 x r)
-	addc	%r25,%r29,%r25		; r25 = hi(100000001 x r)
-; r in r25,,r1
-	zdep	%r1,15,16,%r29
-	add	%r29,%r1,%r29
-	shd	%r25,%r1,16,%r1
-	addc	%r1,%r25,%r1
-; r in r1,,r29
-	sh1add	%r29,%r26,%r0		;  r0 = lo(10 x r) + dividend
-	shd	%r1,%r29,31,%r29	; r29 = hi(10 x r)
-	addc	%r29,%r0,%r29
-	bv	0(ret)
-	extru	%r29,28,29,result
-	.exit
-	.procend
-#endif
-
-
-#ifdef L_divU_3
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divU_3
-$$divU_3
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divU
-	ldi		3,%r25
-	.exit
-	.procend
-	.import		$$divU,MILLICODE
-#endif
-
-#ifdef L_divU_5
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divU_5
-$$divU_5
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divU
-	ldi		5,%r25
-	.exit
-	.procend
-	.import		$$divU,MILLICODE
-#endif
-
-#ifdef L_divU_6
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divU_6
-$$divU_6
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divU
-	ldi		6,%r25
-	.exit
-	.procend
-	.import		$$divU,MILLICODE
-#endif
-
-#ifdef L_divU_7
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divU_7
-$$divU_7
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divU
-	ldi		7,%r25
-	.exit
-	.procend
-	.import		$$divU,MILLICODE
-#endif
-
-#ifdef L_divU_9
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divU_9
-$$divU_9
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divU
-	ldi		9,%r25
-	.exit
-	.procend
-	.import		$$divU,MILLICODE
-#endif
-
-#ifdef L_divU_10
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divU_10
-$$divU_10
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divU
-	ldi		10,%r25
-	.exit
-	.procend
-	.import		$$divU,MILLICODE
-#endif
-
-#ifdef L_divU_12
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divU_12
-$$divU_12
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divU
-	ldi		12,%r25
-	.exit
-	.procend
-	.import		$$divU,MILLICODE
-#endif
-
-#ifdef L_divU_14
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divU_14
-$$divU_14
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divU
-	ldi		14,%r25
-	.exit
-	.procend
-	.import		$$divU,MILLICODE
-#endif
-
-#ifdef L_divU_15
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divU_15
-$$divU_15
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divU
-	ldi		15,%r25
-	.exit
-	.procend
-	.import		$$divU,MILLICODE
-#endif
-
-#ifdef L_divI_3
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divI_3
-$$divI_3
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divI
-	ldi		3,%r25
-	.exit
-	.procend
-	.import		$$divI,MILLICODE
-#endif
-
-#ifdef L_divI_5
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divI_5
-$$divI_5
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divI
-	ldi		5,%r25
-	.exit
-	.procend
-	.import		$$divI,MILLICODE
-#endif
-
-#ifdef L_divI_6
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divI_6
-$$divI_6
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divI
-	ldi		6,%r25
-	.exit
-	.procend
-	.import		$$divI,MILLICODE
-#endif
-
-#ifdef L_divI_7
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divI_7
-$$divI_7
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divI
-	ldi		7,%r25
-	.exit
-	.procend
-	.import		$$divI,MILLICODE
-#endif
-
-#ifdef L_divI_9
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divI_9
-$$divI_9
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divI
-	ldi		9,%r25
-	.exit
-	.procend
-	.import		$$divI,MILLICODE
-#endif
-
-#ifdef L_divI_10
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divI_10
-$$divI_10
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divI
-	ldi		10,%r25
-	.exit
-	.procend
-	.import		$$divI,MILLICODE
-#endif
-
-#ifdef L_divI_12
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divI_12
-$$divI_12
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divI
-	ldi		12,%r25
-	.exit
-	.procend
-	.import		$$divI,MILLICODE
-#endif
-
-#ifdef L_divI_14
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divI_14
-$$divI_14
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divI
-	ldi		14,%r25
-	.exit
-	.procend
-	.import		$$divI,MILLICODE
-#endif
-
-#ifdef L_divI_15
-	.space	$TEXT$
-	.subspa	$MILLICODE$,quad=0,align=8,access=0x2c,sort=8
-	.align	4
-	.export	$$divI_15
-$$divI_15
-	.proc
-	.callinfo	frame=0,no_calls
-	.entry
-	b		$$divI
-	ldi		15,%r25
-	.exit
-	.procend
-	.import		$$divI,MILLICODE
-#endif
diff --git a/gcc/config/pa/lib2funcs.asm b/gcc/config/pa/lib2funcs.asm
deleted file mode 100755
index cf57cbb..0000000
--- a/gcc/config/pa/lib2funcs.asm
+++ /dev/null
@@ -1,74 +0,0 @@
-;  Subroutines for calling unbound dynamic functions from within GDB for HPPA.
-;  Subroutines for out of line prologues and epilogues on for the HPPA
-;  Copyright (C) 1994, 1995, 1996 Free Software Foundation, Inc.
-
-;  This file is part of GNU CC.
-
-;  GNU CC is free software; you can redistribute it and/or modify
-;  it under the terms of the GNU General Public License as published by
-;  the Free Software Foundation; either version 2, or (at your option)
-;  any later version.
-
-;  GNU CC is distributed in the hope that it will be useful,
-;  but WITHOUT ANY WARRANTY; without even the implied warranty of
-;  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;  GNU General Public License for more details.
-
-; In addition to the permissions in the GNU General Public License, the
-; Free Software Foundation gives you unlimited permission to link the
-; compiled version of this file with other programs, and to distribute
-; those programs without any restriction coming from the use of this
-; file.  (The General Public License restrictions do apply in other
-; respects; for example, they cover modification of the file, and
-; distribution when not linked into another program.)
-
-;  You should have received a copy of the GNU General Public License
-;  along with GNU CC; see the file COPYING.  If not, write to
-;  the Free Software Foundation, 59 Temple Place - Suite 330,
-;  Boston, MA 02111-1307, USA.
-
-	.SPACE $PRIVATE$
-	.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31
-	.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82
-	.SPACE $TEXT$
-	.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44
-	.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY
-	.SUBSPA $MILLICODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=8
-
-	.IMPORT $$dyncall,MILLICODE
-; gcc_compiled.:
-	.SPACE $TEXT$
-	.SUBSPA $CODE$
-
-; Simply call with the address of the desired import stub in %r22 and
-; arguments in the normal place (%r26-%r23 and stack slots).
-;
-	.align 4
-	.EXPORT __gcc_plt_call,ENTRY,PRIV_LEV=3,RTNVAL=GR
-__gcc_plt_call
-	.PROC
-	.CALLINFO
-	.ENTRY
-	; Our return address comes in %r31, not %r2!
-	stw %r31,-8(0,%r30)
-
-	; An inline version of dyncall so we don't have to worry
-	; about long calls to millicode, PIC and other complexities.
-	bb,>=,n %r22,30,L$foo
-        depi 0,31,2,%r22
-        ldw 4(%r22),%r19
-        ldw 0(%r22),%r22
-L$foo
-        ldsid (%r22),%r1
-        mtsp %r1,%sr0
-        ble 0(%sr0,%r22)
-	copy %r31,%r2
-	ldw -8(0,%r30),%r2
-
-	; We're going to be returning to a stack address, so we
-	; need to do an intra-space return.
-	ldsid (%rp),%r1
-	mtsp %r1,%sr0
-	be,n 0(%sr0,%rp)
-	.EXIT
-	.PROCEND
diff --git a/gcc/config/pa/pa-gas.h b/gcc/config/pa/pa-gas.h
deleted file mode 100755
index 4106b70..0000000
--- a/gcc/config/pa/pa-gas.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Definitions of target machine for GNU compiler, for HP-UX using GNU as.
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT 0x88		/* TARGET_GAS + TARGET_JUMP_IN_DELAY */
diff --git a/gcc/config/pa/pa-hiux.h b/gcc/config/pa/pa-hiux.h
deleted file mode 100755
index f4be95b..0000000
--- a/gcc/config/pa/pa-hiux.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Definitions of target machine for GNU compiler, for HI-UX.
-   Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* HIUX is just a HPUX variant.  We can simply use the HPUX configuration
-   for just about everything.  */
-
-/* Predefines are the one noteworthy difference between HPUX and HIUX.  */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dhppa -DPWB -Dunix -D__H3050R -D__H3050RX -Asystem(unix) -Asystem(hiux) -Acpu(hppa) -Amachine(hppa)"
diff --git a/gcc/config/pa/pa-hpux.h b/gcc/config/pa/pa-hpux.h
deleted file mode 100755
index e001ebe..0000000
--- a/gcc/config/pa/pa-hpux.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Definitions of target machine for GNU compiler, for HP-UX.
-   Copyright (C) 1991, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT 0
-
-/* Make GCC agree with types.h.  */
-#undef SIZE_TYPE
-#undef PTRDIFF_TYPE
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-
-/* Like the default, except no -lg.  */
-#undef LIB_SPEC
-#define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p: -L/lib/libp/ -lc}%{pg: -L/lib/libp/ -lc}}"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dhppa -Dhp9000s800 -D__hp9000s800 -Dhp9k8 -DPWB -Dhpux -Dunix -Asystem(unix) -Asystem(hpux) -Acpu(hppa) -Amachine(hppa)"
-
-#undef LINK_SPEC
-#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 1)
-#define LINK_SPEC \
-  "%{!mpa-risc-1-0:%{!shared:-L/lib/pa1.1 -L/usr/lib/pa1.1 }}%{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{g*:-a archive} %{shared:-b}"
-#else
-#define LINK_SPEC \
-  "%{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{g*:-a archive} %{shared:-b}"
-#endif
-
-/* hpux8 and later have C++ compatible include files, so do not
-   pretend they are `extern "C"'.  */
-#define NO_IMPLICIT_EXTERN_C
diff --git a/gcc/config/pa/pa-hpux10.h b/gcc/config/pa/pa-hpux10.h
deleted file mode 100755
index e00c107..0000000
--- a/gcc/config/pa/pa-hpux10.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Definitions of target machine for GNU compiler, for HP PA-RISC 1.1
-   Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Tim Moore (moore@defmacro.cs.utah.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* We can debug dynamically linked executables on hpux9; we also want
-   dereferencing of a NULL pointer to cause a SEGV.  */
-#undef LINK_SPEC
-#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 1)
-#define LINK_SPEC \
-  "%{!mpa-risc-1-0:%{!shared:-L/lib/pa1.1 -L/usr/lib/pa1.1 }} -z %{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{shared:-b}"
-#else
-#define LINK_SPEC \
-  "-z %{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{shared:-b}"
-#endif
-
-/* Like the default, except no -lg.  */
-#undef LIB_SPEC
-#define LIB_SPEC \
-  "%{!shared:\
-     %{!p:\
-       %{!pg:\
-         %{!threads:-lc}\
-         %{threads:-lcma -lc_r}}\
-       %{p: -L/lib/libp/ -lc}\
-       %{pg: -L/lib/libp/ -lc}}}"
-
-/* The hpux10 assembler requires a .LEVEL pseudo-op at the start of
-   the assembly file.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
-do {  \
-     /* CYGNUS LOCAL pa8000/law */ \
-     if (TARGET_PARISC_2_0) \
-       fputs("\t.LEVEL 2.0\n", FILE); \
-     else if (TARGET_SNAKE) \
-       fputs("\t.LEVEL 1.1\n", FILE); \
-     else \
-       fputs("\t.LEVEL 1.0\n", FILE); \
-     /* END CYGNUS LOCAL */ \
-     fputs ("\t.SPACE $PRIVATE$\n\
-\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31\n\
-\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82\n\
-\t.SPACE $TEXT$\n\
-\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44\n\
-\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n\
-\t.IMPORT $global$,DATA\n\
-\t.IMPORT $$dyncall,MILLICODE\n", FILE);\
-     if (profile_flag)\
-       fprintf (FILE, "\t.IMPORT _mcount, CODE\n");\
-     if (write_symbols != NO_DEBUG) \
-       output_file_directive ((FILE), main_input_filename); \
-   } while (0)
-
-/* Under hpux10, the normal location of the `ld' and `as' programs is the
-   /usr/ccs/bin directory.  */
-
-#ifndef CROSS_COMPILE
-#undef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "/usr/ccs/bin/"
-#endif
-
-/* Under hpux10, the normal location of the various *crt*.o files is the
-   /usr/ccs/lib directory.  */
-
-#ifndef CROSS_COMPILE
-#undef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
-#endif
-
-/* hpux10 has the new HP assembler.  It's still lousy, but it's a whole lot
-   better than the assembler shipped with older versions of hpux.  */
-#define NEW_HP_ASSEMBLER
diff --git a/gcc/config/pa/pa-hpux11.h b/gcc/config/pa/pa-hpux11.h
deleted file mode 100755
index 2959c5c..0000000
--- a/gcc/config/pa/pa-hpux11.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* CYGNUS LOCAL entire file hpux11/law */
-/* Definitions of target machine for GNU compiler, for HP PA-RISC 1.1
-   Copyright (C) 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* We can debug dynamically linked executables on hpux11; we also
-   want dereferencing of a NULL pointer to cause a SEGV.  */
-#undef LINK_SPEC
-#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 1)
-#define LINK_SPEC \
-  "%{!mpa-risc-1-0:%{!shared:-L/lib/pa1.1 -L/usr/lib/pa1.1 }} -z %{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{shared:-b}"
-#else
-#define LINK_SPEC \
-  "-z %{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{shared:-b}"
-#endif
-
-/* Like the default, except no -lg.  */
-#undef LIB_SPEC
-#define LIB_SPEC \
-  "%{!shared:\
-     %{!p:\
-       %{!pg:\
-         %{!threads:-lc}\
-         %{threads:-lcma -lc_r}}\
-       %{p: -L/lib/libp/ -lc}\
-       %{pg: -L/lib/libp/ -lc}}}"
-
-/* The hpux11 assembler requires a .LEVEL pseudo-op at the start of the
-   assembly file.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
-do {  \
-     /* CYGNUS LOCAL pa8000/law */ \
-     if (TARGET_PARISC_2_0) \
-       fputs("\t.LEVEL 2.0\n", FILE); \
-     else if (TARGET_SNAKE) \
-       fputs("\t.LEVEL 1.1\n", FILE); \
-     else \
-       fputs("\t.LEVEL 1.0\n", FILE); \
-     /* END CYGNUS LOCAL */ \
-     fputs ("\t.SPACE $PRIVATE$\n\
-\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31\n\
-\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82\n\
-\t.SPACE $TEXT$\n\
-\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44\n\
-\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n\
-\t.IMPORT $global$,DATA\n\
-\t.IMPORT $$dyncall,MILLICODE\n", FILE);\
-     if (profile_flag)\
-       fprintf (FILE, "\t.IMPORT _mcount, CODE\n");\
-     if (write_symbols != NO_DEBUG) \
-       output_file_directive ((FILE), main_input_filename); \
-   } while (0)
-
-/* Under hpux11, the normal location of the `ld' and `as' programs is the
-   /usr/ccs/bin directory.  */
-
-#ifndef CROSS_COMPILE
-#undef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "/usr/ccs/bin/"
-#endif
-
-/* Under hpux11 the normal location of the various *crt*.o files is the
-   /usr/ccs/lib directory.  */
-
-#ifndef CROSS_COMPILE
-#undef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
-#endif
-
-/* hpux11 has the new HP assembler.  It's still lousy, but it's a whole lot
-   better than the assembler shipped with older versions of hpux.  */
-#define NEW_HP_ASSEMBLER
-
-/* Make GCC agree with types.h.  */
-#undef SIZE_TYPE
-#undef PTRDIFF_TYPE
-
-#define SIZE_TYPE "long unsigned int"
-#define PTRDIFF_TYPE "long int"
-
-/* END CYGNUS LOCAL */
diff --git a/gcc/config/pa/pa-hpux7.h b/gcc/config/pa/pa-hpux7.h
deleted file mode 100755
index dc75ec2..0000000
--- a/gcc/config/pa/pa-hpux7.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Definitions of target machine for GNU compiler, for HP-UX.
-   Copyright (C) 1991, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 0
-#endif
-
-/* Make GCC agree with types.h.  */
-#undef SIZE_TYPE
-#undef PTRDIFF_TYPE
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-
-/* Like the default, except no -lg.  */
-#undef LIB_SPEC
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p: -L/lib/libp/ -lc}%{pg: -L/lib/libp/ -lc}"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dhppa -Dhp9000s800 -D__hp9000s800 -Dhp9k8 -DPWB -Dhpux -Dunix -Asystem(unix) -Asystem(hpux) -Acpu(hppa) -Amachine(hppa)"
diff --git a/gcc/config/pa/pa-hpux9.h b/gcc/config/pa/pa-hpux9.h
deleted file mode 100755
index 8d039d2..0000000
--- a/gcc/config/pa/pa-hpux9.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Definitions of target machine for GNU compiler, for HP PA-RISC 1.1
-   Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Tim Moore (moore@defmacro.cs.utah.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* We can debug dynamically linked executables on hpux9; we also want
-   dereferencing of a NULL pointer to cause a SEGV.  */
-#undef LINK_SPEC
-#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 1)
-#define LINK_SPEC \
-  "%{!mpa-risc-1-0:%{!shared:-L/lib/pa1.1 -L/usr/lib/pa1.1 }} -z %{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{shared:-b}"
-#else
-#define LINK_SPEC \
-  "-z %{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{shared:-b}"
-#endif
diff --git a/gcc/config/pa/pa-oldas.h b/gcc/config/pa/pa-oldas.h
deleted file mode 100755
index 8ff741f..0000000
--- a/gcc/config/pa/pa-oldas.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Definitions of target machine for GNU compiler, for HP PA-RISC 1.1
-   Copyright (C) 1991, 1996 Free Software Foundation, Inc.
-   Contributed by Tim Moore (moore@defmacro.cs.utah.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define HP_FP_ARG_DESCRIPTOR_REVERSED
diff --git a/gcc/config/pa/pa-osf.h b/gcc/config/pa/pa-osf.h
deleted file mode 100755
index 047d20e..0000000
--- a/gcc/config/pa/pa-osf.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Definitions of target machine for GNU compiler, for HP PA-RISC 1.1
-   Copyright (C) 1991, 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Tim Moore (moore@defmacro.cs.utah.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef CPP_PREDEFINES
-#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 1)
-#define CPP_PREDEFINES "-Dhppa -Dunix -Dhp9000 -Dspectrum -DREVARGV -Dhp700 -DHP700 -Dparisc -D__pa_risc -DPARISC -DBYTE_MSF -DBIT_MSF -Asystem(unix) -Asystem(mach) -Acpu(hppa) -Amachine(hppa)"
-#else
-#define CPP_PREDEFINES "-Dhppa -Dhp9000s800 -D__hp9000s800 -Dhp9k8 -Dunix -Dhp9000 -Dhp800 -Dspectrum -DREVARGV -Dparisc -D__pa_risc -DPARISC -DBYTE_MSF -DBIT_MSF -Asystem(unix) -Asystem(mach) -Acpu(hppa) -Amachine(hppa)"
-#endif
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* OSF1 on the PA still uses 16bit wchar_t.  */
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-
-#define WCHAR_TYPE "short unsigned int"
-#define WCHAR_TYPE_SIZE 16
-
-/* OSF1 wants to be different and use unsigned long as size_t.  */
-#undef SIZE_TYPE
-#define SIZE_TYPE "long unsigned int"
diff --git a/gcc/config/pa/pa-pro-end.h b/gcc/config/pa/pa-pro-end.h
deleted file mode 100755
index de88036..0000000
--- a/gcc/config/pa/pa-pro-end.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Definitions of target machine for GNU compiler, for PRO.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Make GCC agree with types.h.  */
-#undef SIZE_TYPE
-#undef PTRDIFF_TYPE
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-
-/* Like the default, except no -lg.  */
-#undef LIB_SPEC
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p: -L/lib/libp/ -lc}%{pg: -L/lib/libp/ -lc}"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dhppa -DPWB -Acpu(hppa) -Amachine(hppa)"
-
-/* hpux8 and later have C++ compatible include files, so do not
-   pretend they are `extern "C"'.  */
-#define NO_IMPLICIT_EXTERN_C
-
-/* We don't want a crt0.o to get linked in automatically, we want the
-   linker script to pull it in.
- */
-#define STARTFILE_SPEC ""
diff --git a/gcc/config/pa/pa-pro.h b/gcc/config/pa/pa-pro.h
deleted file mode 100755
index 2ec832b..0000000
--- a/gcc/config/pa/pa-pro.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Definitions of target machine for GNU compiler, for PRO.
-   Copyright (C) 1994, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Global constructor and destructor support.  */
-/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
- 
-   Note that we want to give these sections the SHF_WRITE attribute
-   because these sections will actually contain data (i.e. tables of
-   addresses of functions in the current root executable or shared library
-   file) and, in the case of a shared library, the relocatable addresses
-   will have to be properly resolved/relocated (and then written into) by
-   the dynamic linker when it actually attaches the given shared library
-   to the executing process.  */
- 
-#define CTORS_SECTION_ASM_OP    "\t.section\t\".ctors\",#alloc,#write"
-#define DTORS_SECTION_ASM_OP    "\t.section\t\".dtors\",#alloc,#write"
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fputs ("\t.word\t ", FILE);				\
-    assemble_name (FILE, NAME);              				\
-    fputs ("\n", FILE);						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fputs ("\t.word\t ", FILE);				\
-    assemble_name (FILE, NAME);						\
-    fputs ("\n", FILE);						\
-  } while (0)
-
-/* JUMP_IN_DELAY + PORTABLE_RUNTIME + GAS + NO_SPACE_REGS + SOFT_FLOAT */
-#define TARGET_DEFAULT (4 + 8 + 64 + 128 + 256)
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
deleted file mode 100755
index de7f698..0000000
--- a/gcc/config/pa/pa.c
+++ /dev/null
@@ -1,6491 +0,0 @@
-/* Subroutines for insn-output.c for HPPA.
-   Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
-   Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include "system.h"
-
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "tree.h"
-#include "reload.h"
-#include "c-tree.h"
-#include "expr.h"
-#include "obstack.h"
-#include "toplev.h"
-
-static void restore_unscaled_index_insn_codes		PROTO((rtx));
-static void record_unscaled_index_insn_codes		PROTO((rtx));
-static void pa_combine_instructions			PROTO((rtx));
-static int pa_can_combine_p	PROTO((rtx, rtx, rtx, int, rtx, rtx, rtx));
-static int forward_branch_p				PROTO((rtx));
-static int shadd_constant_p				PROTO((int));
-
-/* Save the operands last given to a compare for use when we
-   generate a scc or bcc insn.  */
-
-rtx hppa_compare_op0, hppa_compare_op1;
-enum cmp_type hppa_branch_type;
-
-/* Which cpu we are scheduling for.  */
-enum processor_type pa_cpu;
-
-/* String to hold which cpu we are scheduling for.  */
-char *pa_cpu_string;
-
-/* Set by the FUNCTION_PROFILER macro. */
-int hp_profile_labelno;
-
-/* Counts for the number of callee-saved general and floating point
-   registers which were saved by the current function's prologue.  */
-static int gr_saved, fr_saved;
-
-/* Whether or not the current function uses an out-of-line prologue
-   and epilogue.  */
-static int out_of_line_prologue_epilogue;
-
-static rtx find_addr_reg ();
-
-/* Keep track of the number of bytes we have output in the CODE subspaces
-   during this compilation so we'll know when to emit inline long-calls.  */
-
-unsigned int total_code_bytes;
-
-/* Variables to handle plabels that we discover are necessary at assembly
-   output time.  They are output after the current function.  */
-
-struct deferred_plabel
-{
-  rtx internal_label;
-  char *name;
-} *deferred_plabels = 0;
-int n_deferred_plabels = 0;
-
-/* Array indexed by INSN_UIDs holding the INSN_CODE of an insn which
-   uses an unscaled indexed address before delay slot scheduling.  */
-static int *unscaled_index_insn_codes;
-
-/* Upper bound for the array.  */
-static int max_unscaled_index_insn_codes_uid;
-
-void
-override_options ()
-{
-  /* Default to 7100 scheduling.  If the 7100LC scheduling ever
-     gets reasonably tuned, it should be the default since that
-     what most PAs sold now are.  */
-  if (pa_cpu_string == NULL
-      || ! strcmp (pa_cpu_string, "7100"))
-    {
-      pa_cpu_string = "7100";
-      pa_cpu = PROCESSOR_7100;
-    }
-  else if (! strcmp (pa_cpu_string, "700"))
-    {
-      pa_cpu_string = "700";
-      pa_cpu = PROCESSOR_700;
-    }
-  else if (! strcmp (pa_cpu_string, "7100LC"))
-    {
-      pa_cpu_string = "7100LC";
-      pa_cpu = PROCESSOR_7100LC;
-    }
-  else if (! strcmp (pa_cpu_string, "7200"))
-    {
-      pa_cpu_string = "7200";
-      pa_cpu = PROCESSOR_7200;
-    }
-  /* CYGNUS LOCAL PA8000/law */
-  else if (! strcmp (pa_cpu_string, "8000"))
-    {
-      pa_cpu_string = "8000";
-      pa_cpu = PROCESSOR_8000;
-    }
-  else
-    {
-      warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100 and 7100LC, 7200 and 8000\n", pa_cpu_string);
-    }
-  /* END CYGNUS LOCAL */
-
-  if (flag_pic && TARGET_PORTABLE_RUNTIME)
-    {
-      warning ("PIC code generation is not supported in the portable runtime model\n");
-    }
-
-  if (flag_pic && (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS))
-   {
-      warning ("PIC code generation is not compatible with fast indirect calls\n");
-   }
-
-  if (flag_pic && profile_flag)
-    {
-      warning ("PIC code generation is not compatible with profiling\n");
-    }
-
-  if (TARGET_SPACE && (flag_pic || profile_flag))
-    {
-      warning ("Out of line entry/exit sequences are not compatible\n");
-      warning ("with PIC or profiling\n");
-    }
-
-  if (! TARGET_GAS && write_symbols != NO_DEBUG)
-    {
-      warning ("-g is only supported when using GAS on this processor,");
-      warning ("-g option disabled.");
-      write_symbols = NO_DEBUG;
-    }
-}
-
-
-/* Return non-zero only if OP is a register of mode MODE,
-   or CONST0_RTX.  */
-int
-reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (op == CONST0_RTX (mode) || register_operand (op, mode));
-}
-
-/* Return non-zero if OP is suitable for use in a call to a named
-   function.
-
-   (???) For 2.5 try to eliminate either call_operand_address or
-   function_label_operand, they perform very similar functions.  */
-int
-call_operand_address (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
-}
-
-/* Return 1 if X contains a symbolic expression.  We know these
-   expressions will have one of a few well defined forms, so
-   we need only check those forms.  */
-int
-symbolic_expression_p (x)
-     register rtx x;
-{
-
-  /* Strip off any HIGH. */
-  if (GET_CODE (x) == HIGH)
-    x = XEXP (x, 0);
-
-  return (symbolic_operand (x, VOIDmode));
-}
-
-int
-symbolic_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return 1;
-    case CONST:
-      op = XEXP (op, 0);
-      return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
-	       || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-	      && GET_CODE (XEXP (op, 1)) == CONST_INT);
-    default:
-      return 0;
-    }
-}
-
-/* Return truth value of statement that OP is a symbolic memory
-   operand of mode MODE.  */
-
-int
-symbolic_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  if (GET_CODE (op) != MEM)
-    return 0;
-  op = XEXP (op, 0);
-  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
-	  || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
-}
-
-/* Return 1 if the operand is either a register or a memory operand that is
-   not symbolic.  */
-
-int
-reg_or_nonsymb_mem_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  if (register_operand (op, mode))
-    return 1;
-
-  if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
-    return 1;
-
-  return 0;
-}
-
-/* Return 1 if the operand is either a register, zero, or a memory operand
-   that is not symbolic.  */
-
-int
-reg_or_0_or_nonsymb_mem_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  if (register_operand (op, mode))
-    return 1;
-
-  if (op == CONST0_RTX (mode))
-    return 1;
-
-  if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
-    return 1;
-
-  return 0;
-}
-
-/* Accept any constant that can be moved in one instructions into a
-   general register.  */
-int
-cint_ok_for_move (intval)
-     HOST_WIDE_INT intval;
-{
-  /* OK if ldo, ldil, or zdepi, can be used.  */
-  return (VAL_14_BITS_P (intval) || (intval & 0x7ff) == 0
-	  || zdepi_cint_p (intval));
-}
-
-/* Accept anything that can be moved in one instruction into a general
-   register.  */
-int
-move_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (register_operand (op, mode))
-    return 1;
-
-  if (GET_CODE (op) == CONSTANT_P_RTX)
-    return 1;
-
-  if (GET_CODE (op) == CONST_INT)
-    return cint_ok_for_move (INTVAL (op));
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  if (GET_CODE (op) != MEM)
-    return 0;
-
-  op = XEXP (op, 0);
-  if (GET_CODE (op) == LO_SUM)
-    return (register_operand (XEXP (op, 0), Pmode)
-	    && CONSTANT_P (XEXP (op, 1)));
-
-  /* Since move_operand is only used for source operands, we can always
-     allow scaled indexing!  */
-  if (! TARGET_DISABLE_INDEXING
-      && GET_CODE (op) == PLUS
-      && ((GET_CODE (XEXP (op, 0)) == MULT
-	   && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
-	   && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
-	   && INTVAL (XEXP (XEXP (op, 0), 1)) == GET_MODE_SIZE (mode)
-	   && GET_CODE (XEXP (op, 1)) == REG)
-	  || (GET_CODE (XEXP (op, 1)) == MULT
-	      &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
-	      && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
-	      && INTVAL (XEXP (XEXP (op, 1), 1)) == GET_MODE_SIZE (mode)
-	      && GET_CODE (XEXP (op, 0)) == REG)))
-    return 1;
-
-  return memory_address_p (mode, op);
-}
-
-/* Accept REG and any CONST_INT that can be moved in one instruction into a
-   general register.  */
-int
-reg_or_cint_move_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (register_operand (op, mode))
-    return 1;
-
-  if (GET_CODE (op) == CONST_INT)
-    return cint_ok_for_move (INTVAL (op));
-
-  return 0;
-}
-
-int
-pic_label_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (!flag_pic)
-    return 0;
-
-  switch (GET_CODE (op))
-    {
-    case LABEL_REF:
-      return 1;
-    case CONST:
-      op = XEXP (op, 0);
-      return (GET_CODE (XEXP (op, 0)) == LABEL_REF
-	      && GET_CODE (XEXP (op, 1)) == CONST_INT);
-    default:
-      return 0;
-    }
-}
-
-int
-fp_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return reg_renumber && FP_REG_P (op);
-}
-
-
-
-/* Return truth value of whether OP can be used as an operand in a
-   three operand arithmetic insn that accepts registers of mode MODE
-   or 14-bit signed integers.  */
-int
-arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
-}
-
-/* Return truth value of whether OP can be used as an operand in a
-   three operand arithmetic insn that accepts registers of mode MODE
-   or 11-bit signed integers.  */
-int
-arith11_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
-}
-
-/* A constant integer suitable for use in a PRE_MODIFY memory
-   reference.  */
-int
-pre_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT
-	  && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
-}
-
-/* A constant integer suitable for use in a POST_MODIFY memory
-   reference.  */
-int
-post_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT
-	  && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
-}
-
-int
-arith_double_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_DOUBLE
-	      && GET_MODE (op) == mode
-	      && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
-	      && ((CONST_DOUBLE_HIGH (op) >= 0)
-		  == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
-}
-
-/* Return truth value of whether OP is a integer which fits the
-   range constraining immediate operands in three-address insns, or
-   is an integer register.  */
-
-int
-ireg_or_int5_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
-	  || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
-}
-
-/* Return truth value of whether OP is a integer which fits the
-   range constraining immediate operands in three-address insns.  */
-
-int
-int5_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
-}
-
-int
-uint5_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
-}
-
-int
-int11_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
-}
-
-int
-uint32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-#if HOST_BITS_PER_WIDE_INT > 32
-  /* All allowed constants will fit a CONST_INT.  */
-  return (GET_CODE (op) == CONST_INT
-	  && (INTVAL (op) >= 0 && INTVAL (op) < 0x100000000L));
-#else
-  return (GET_CODE (op) == CONST_INT
-	  || (GET_CODE (op) == CONST_DOUBLE
-	      && CONST_DOUBLE_HIGH (op) == 0));
-#endif
-}
-
-int
-arith5_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return register_operand (op, mode) || int5_operand (op, mode);
-}
-
-/* True iff zdepi can be used to generate this CONST_INT.  */
-int
-zdepi_cint_p (x)
-     unsigned HOST_WIDE_INT x;
-{
-  unsigned HOST_WIDE_INT lsb_mask, t;
-
-  /* This might not be obvious, but it's at least fast.
-     This function is critical; we don't have the time loops would take.  */
-  lsb_mask = x & -x;
-  t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
-  /* Return true iff t is a power of two.  */
-  return ((t & (t - 1)) == 0);
-}
-
-/* True iff depi or extru can be used to compute (reg & mask).
-   Accept bit pattern like these:
-   0....01....1
-   1....10....0
-   1..10..01..1  */
-int
-and_mask_p (mask)
-     unsigned HOST_WIDE_INT mask;
-{
-  mask = ~mask;
-  mask += mask & -mask;
-  return (mask & (mask - 1)) == 0;
-}
-
-/* True iff depi or extru can be used to compute (reg & OP).  */
-int
-and_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
-}
-
-/* True iff depi can be used to compute (reg | MASK).  */
-int
-ior_mask_p (mask)
-     unsigned HOST_WIDE_INT mask;
-{
-  mask += mask & -mask;
-  return (mask & (mask - 1)) == 0;
-}
-
-/* True iff depi can be used to compute (reg | OP).  */
-int
-ior_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
-}
-
-int
-lhs_lshift_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
-}
-
-/* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
-   Such values can be the left hand side x in (x << r), using the zvdepi
-   instruction.  */
-int
-lhs_lshift_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  unsigned HOST_WIDE_INT x;
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  x = INTVAL (op) >> 4;
-  return (x & (x + 1)) == 0;
-}
-
-int
-arith32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
-}
-
-int
-pc_or_label_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
-}
-
-/* Legitimize PIC addresses.  If the address is already
-   position-independent, we return ORIG.  Newly generated
-   position-independent addresses go to REG.  If we need more
-   than one register, we lose.  */
-
-rtx
-legitimize_pic_address (orig, mode, reg)
-     rtx orig, reg;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  rtx pic_ref = orig;
-
-  /* Labels need special handling.  */
-  if (pic_label_operand (orig))
-    {
-      emit_insn (gen_pic_load_label (reg, orig));
-      current_function_uses_pic_offset_table = 1;
-      return reg;
-    }
-  if (GET_CODE (orig) == SYMBOL_REF)
-    {
-      if (reg == 0)
-	abort ();
-
-      if (flag_pic == 2)
-	{
-	  emit_insn (gen_pic2_highpart (reg, pic_offset_table_rtx, orig));
-	  pic_ref
-	    = gen_rtx_MEM (Pmode,
-			   gen_rtx_LO_SUM (Pmode, reg,
-					   gen_rtx_UNSPEC (SImode,
-							   gen_rtvec (1, orig),
-							   0)));
-	}
-      else
-	pic_ref = gen_rtx_MEM (Pmode,
-			       gen_rtx_PLUS (Pmode,
-					     pic_offset_table_rtx, orig));
-      current_function_uses_pic_offset_table = 1;
-      RTX_UNCHANGING_P (pic_ref) = 1;
-      emit_move_insn (reg, pic_ref);
-      return reg;
-    }
-  else if (GET_CODE (orig) == CONST)
-    {
-      rtx base;
-
-      if (GET_CODE (XEXP (orig, 0)) == PLUS
-	  && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
-	return orig;
-
-      if (reg == 0)
-	abort ();
-
-      if (GET_CODE (XEXP (orig, 0)) == PLUS)
-	{
-	  base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
-	  orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
-					 base == reg ? 0 : reg);
-	}
-      else abort ();
-      if (GET_CODE (orig) == CONST_INT)
-	{
-	  if (INT_14_BITS (orig))
-	    return plus_constant_for_output (base, INTVAL (orig));
-	  orig = force_reg (Pmode, orig);
-	}
-      pic_ref = gen_rtx_PLUS (Pmode, base, orig);
-      /* Likewise, should we set special REG_NOTEs here?  */
-    }
-  return pic_ref;
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the PA, transform:
-
-	memory(X + <large int>)
-
-   into:
-
-	if (<large int> & mask) >= 16
-	  Y = (<large int> & ~mask) + mask + 1	Round up.
-	else
-	  Y = (<large int> & ~mask)		Round down.
-	Z = X + Y
-	memory (Z + (<large int> - Y));
-
-   This is for CSE to find several similar references, and only use one Z.
-
-   X can either be a SYMBOL_REF or REG, but because combine can not
-   perform a 4->2 combination we do nothing for SYMBOL_REF + D where
-   D will not fit in 14 bits.
-
-   MODE_FLOAT references allow displacements which fit in 5 bits, so use
-   0x1f as the mask.
-
-   MODE_INT references allow displacements which fit in 14 bits, so use
-   0x3fff as the mask.
-
-   This relies on the fact that most mode MODE_FLOAT references will use FP
-   registers and most mode MODE_INT references will use integer registers.
-   (In the rare case of an FP register used in an integer MODE, we depend
-   on secondary reloads to clean things up.)
-
-
-   It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
-   manner if Y is 2, 4, or 8.  (allows more shadd insns and shifted indexed
-   addressing modes to be used).
-
-   Put X and Z into registers.  Then put the entire expression into
-   a register.  */
-
-rtx
-hppa_legitimize_address (x, oldx, mode)
-     rtx x, oldx ATTRIBUTE_UNUSED;
-     enum machine_mode mode;
-{
-  rtx orig = x;
-
-  if (flag_pic)
-    return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
-
-  /* Strip off CONST. */
-  if (GET_CODE (x) == CONST)
-    x = XEXP (x, 0);
-
-  /* Special case.  Get the SYMBOL_REF into a register and use indexing.
-     That should always be safe.  */
-  if (GET_CODE (x) == PLUS
-      && GET_CODE (XEXP (x, 0)) == REG
-      && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
-    {
-      rtx reg = force_reg (SImode, XEXP (x, 1));
-      return force_reg (SImode, gen_rtx_PLUS (SImode, reg, XEXP (x, 0)));
-    }
-
-  /* Note we must reject symbols which represent function addresses
-     since the assembler/linker can't handle arithmetic on plabels.  */
-  if (GET_CODE (x) == PLUS
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
-      && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
-	   && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
-	  || GET_CODE (XEXP (x, 0)) == REG))
-    {
-      rtx int_part, ptr_reg;
-      int newoffset;
-      int offset = INTVAL (XEXP (x, 1));
-      int mask = GET_MODE_CLASS (mode) == MODE_FLOAT ? 0x1f : 0x3fff;
-
-      /* CYGNUS LOCAL pa8000/law */
-      mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
-	      ? (TARGET_PARISC_2_0 ? 0x3fff : 0x1f) : 0x3fff);
-      /* END CYGNUS LOCAL */
-
-      /* Choose which way to round the offset.  Round up if we
-	 are >= halfway to the next boundary.  */
-      if ((offset & mask) >= ((mask + 1) / 2))
-	newoffset = (offset & ~ mask) + mask + 1;
-      else
-	newoffset = (offset & ~ mask);
-
-      /* If the newoffset will not fit in 14 bits (ldo), then
-	 handling this would take 4 or 5 instructions (2 to load
-	 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
-	 add the new offset and the SYMBOL_REF.)  Combine can
-	 not handle 4->2 or 5->2 combinations, so do not create
-	 them.  */
-      if (! VAL_14_BITS_P (newoffset)
-	  && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
-	{
-	  rtx const_part
-	    = gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (Pmode,
-						     XEXP (x, 0),
-						     GEN_INT (newoffset)));
-	  rtx tmp_reg
-	    = force_reg (Pmode,
-			 gen_rtx_HIGH (Pmode, const_part));
-	  ptr_reg
-	    = force_reg (Pmode,
-			 gen_rtx_LO_SUM (Pmode, tmp_reg, const_part));
-	}
-      else
-	{
-	  if (! VAL_14_BITS_P (newoffset))
-	    int_part = force_reg (Pmode, GEN_INT (newoffset));
-	  else
-	    int_part = GEN_INT (newoffset);
-
-	  ptr_reg = force_reg (Pmode,
-			       gen_rtx_PLUS (Pmode,
-					     force_reg (Pmode, XEXP (x, 0)),
-					     int_part));
-	}
-      return plus_constant (ptr_reg, offset - newoffset);
-    }
-
-  /* Handle (plus (mult (a) (shadd_constant)) (b)).  */
-
-  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
-      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
-      && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
-      && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
-	  || GET_CODE (XEXP (x, 1)) == SUBREG)
-      && GET_CODE (XEXP (x, 1)) != CONST)
-    {
-      int val = INTVAL (XEXP (XEXP (x, 0), 1));
-      rtx reg1, reg2;
-
-      reg1 = XEXP (x, 1);
-      if (GET_CODE (reg1) != REG)
-	reg1 = force_reg (Pmode, force_operand (reg1, 0));
-
-      reg2 = XEXP (XEXP (x, 0), 0);
-      if (GET_CODE (reg2) != REG)
-        reg2 = force_reg (Pmode, force_operand (reg2, 0));
-
-      return force_reg (Pmode, gen_rtx_PLUS (Pmode,
-					     gen_rtx_MULT (Pmode, reg2,
-						           GEN_INT (val)),
-					     reg1));
-    }
-
-  /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
-
-     Only do so for floating point modes since this is more speculative
-     and we lose if it's an integer store.  */
-  if (GET_CODE (x) == PLUS
-      && GET_CODE (XEXP (x, 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
-      && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
-      && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
-      && (mode == SFmode || mode == DFmode))
-    {
-
-      /* First, try and figure out what to use as a base register.  */
-      rtx reg1, reg2, base, idx, orig_base;
-
-      reg1 = XEXP (XEXP (x, 0), 1);
-      reg2 = XEXP (x, 1);
-      base = NULL_RTX;
-      idx = NULL_RTX;
-
-      /* Make sure they're both regs.  If one was a SYMBOL_REF [+ const],
-	 then emit_move_sequence will turn on REGNO_POINTER_FLAG so we'll
-	 know it's a base register below.  */
-      if (GET_CODE (reg1) != REG)
-	reg1 = force_reg (Pmode, force_operand (reg1, 0));
-
-      if (GET_CODE (reg2) != REG)
-	reg2 = force_reg (Pmode, force_operand (reg2, 0));
-
-      /* Figure out what the base and index are.  */
-	 
-      if (GET_CODE (reg1) == REG
-	  && REGNO_POINTER_FLAG (REGNO (reg1)))
-	{
-	  base = reg1;
-	  orig_base = XEXP (XEXP (x, 0), 1);
-	  idx = gen_rtx_PLUS (Pmode,
-			      gen_rtx_MULT (Pmode,
-					    XEXP (XEXP (XEXP (x, 0), 0), 0),
-					    XEXP (XEXP (XEXP (x, 0), 0), 1)),
-			      XEXP (x, 1));
-	}
-      else if (GET_CODE (reg2) == REG
-	       && REGNO_POINTER_FLAG (REGNO (reg2)))
-	{
-	  base = reg2;
-	  orig_base = XEXP (x, 1);
-	  idx = XEXP (x, 0);
-	}
-
-      if (base == 0)
-	return orig;
-
-      /* If the index adds a large constant, try to scale the
-	 constant so that it can be loaded with only one insn.  */
-      if (GET_CODE (XEXP (idx, 1)) == CONST_INT
-	  && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
-			    / INTVAL (XEXP (XEXP (idx, 0), 1)))
-	  && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
-	{
-	  /* Divide the CONST_INT by the scale factor, then add it to A.  */
-	  int val = INTVAL (XEXP (idx, 1));
-
-	  val /= INTVAL (XEXP (XEXP (idx, 0), 1));
-	  reg1 = XEXP (XEXP (idx, 0), 0);
-	  if (GET_CODE (reg1) != REG)
-	    reg1 = force_reg (Pmode, force_operand (reg1, 0));
-
-	  reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
-
-	  /* We can now generate a simple scaled indexed address.  */
-	  return force_reg (Pmode,
-			    gen_rtx_PLUS (Pmode,
-					  gen_rtx_MULT (Pmode, reg1,
-						        XEXP (XEXP (idx, 0), 1)),
-					  base));
-	}
-
-      /* If B + C is still a valid base register, then add them.  */
-      if (GET_CODE (XEXP (idx, 1)) == CONST_INT
-	  && INTVAL (XEXP (idx, 1)) <= 4096
-	  && INTVAL (XEXP (idx, 1)) >= -4096)
-	{
-	  int val = INTVAL (XEXP (XEXP (idx, 0), 1));
-	  rtx reg1, reg2;
-
-	  reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
-
-	  reg2 = XEXP (XEXP (idx, 0), 0);
-	  if (GET_CODE (reg2) != CONST_INT)
-	    reg2 = force_reg (Pmode, force_operand (reg2, 0));
-
-	  return force_reg (Pmode, gen_rtx_PLUS (Pmode,
-					         gen_rtx_MULT (Pmode, reg2,
-							       GEN_INT (val)),
-						 reg1));
-	}
-
-      /* Get the index into a register, then add the base + index and
-	 return a register holding the result.  */
-
-      /* First get A into a register.  */
-      reg1 = XEXP (XEXP (idx, 0), 0);
-      if (GET_CODE (reg1) != REG)
-	reg1 = force_reg (Pmode, force_operand (reg1, 0));
-
-      /* And get B into a register.  */
-      reg2 = XEXP (idx, 1);
-      if (GET_CODE (reg2) != REG)
-	reg2 = force_reg (Pmode, force_operand (reg2, 0));
-
-      reg1 = force_reg (Pmode,
-			gen_rtx_PLUS (Pmode,
-				      gen_rtx_MULT (Pmode, reg1,
-						    XEXP (XEXP (idx, 0), 1)),
-				      reg2));
-
-      /* Add the result to our base register and return.  */
-      return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
-      
-    }
-
-  /* Uh-oh.  We might have an address for x[n-100000].  This needs
-     special handling to avoid creating an indexed memory address
-     with x-100000 as the base.
-    
-     If the constant part is small enough, then it's still safe because
-     there is a guard page at the beginning and end of the data segment.
-
-     Scaled references are common enough that we want to try and rearrange the
-     terms so that we can use indexing for these addresses too.  Only
-     do the optimization for floatint point modes.  */
-
-  if (GET_CODE (x) == PLUS
-      && symbolic_expression_p (XEXP (x, 1)))
-    {
-      /* Ugly.  We modify things here so that the address offset specified
-	 by the index expression is computed first, then added to x to form
-	 the entire address.  */
-
-      rtx regx1, regx2, regy1, regy2, y;
-
-      /* Strip off any CONST.  */
-      y = XEXP (x, 1);
-      if (GET_CODE (y) == CONST)
-	y = XEXP (y, 0);
-
-      if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
-	{
-	  /* See if this looks like
-		(plus (mult (reg) (shadd_const))
-		      (const (plus (symbol_ref) (const_int))))
-
-	     Where const_int is small.  In that case the const
-	     expression is a valid pointer for indexing. 
-
-	     If const_int is big, but can be divided evenly by shadd_const
-	     and added to (reg).  This allows more scaled indexed addresses.  */
-	  if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
-	      && GET_CODE (XEXP (x, 0)) == MULT
-	      && GET_CODE (XEXP (y, 1)) == CONST_INT
-	      && INTVAL (XEXP (y, 1)) >= -4096
-	      && INTVAL (XEXP (y, 1)) <= 4095
-	      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
-	      && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
-	    {
-	      int val = INTVAL (XEXP (XEXP (x, 0), 1));
-	      rtx reg1, reg2;
-
-	      reg1 = XEXP (x, 1);
-	      if (GET_CODE (reg1) != REG)
-		reg1 = force_reg (Pmode, force_operand (reg1, 0));
-
-	      reg2 = XEXP (XEXP (x, 0), 0);
-	      if (GET_CODE (reg2) != REG)
-	        reg2 = force_reg (Pmode, force_operand (reg2, 0));
-
-	      return force_reg (Pmode,
-				gen_rtx_PLUS (Pmode,
-					      gen_rtx_MULT (Pmode, reg2,
-							    GEN_INT (val)),
-						reg1));
-	    }
-	  else if ((mode == DFmode || mode == SFmode)
-		   && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
-		   && GET_CODE (XEXP (x, 0)) == MULT
-		   && GET_CODE (XEXP (y, 1)) == CONST_INT
-		   && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
-		   && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
-		   && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
-	    {
-	      regx1
-		= force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
-					     / INTVAL (XEXP (XEXP (x, 0), 1))));
-	      regx2 = XEXP (XEXP (x, 0), 0);
-	      if (GET_CODE (regx2) != REG)
-		regx2 = force_reg (Pmode, force_operand (regx2, 0));
-	      regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
-							regx2, regx1));
-	      return force_reg (Pmode,
-				gen_rtx_PLUS (Pmode,
-					      gen_rtx_MULT (Pmode, regx2,
-						            XEXP (XEXP (x, 0),
-							    1)),
-					      force_reg (Pmode, XEXP (y, 0))));
-	    }
-	  else if (GET_CODE (XEXP (y, 1)) == CONST_INT
-		   && INTVAL (XEXP (y, 1)) >= -4096
-		   && INTVAL (XEXP (y, 1)) <= 4095)
-	    {
-	      /* This is safe because of the guard page at the
-		 beginning and end of the data space.  Just
-		 return the original address.  */
-	      return orig;
-	    }
-	  else
-	    {
-	      /* Doesn't look like one we can optimize.  */
-	      regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
-	      regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
-	      regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
-	      regx1 = force_reg (Pmode,
-				 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
-						 regx1, regy2));
-	      return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
-	    }
-	}
-    }
-
-  return orig;
-}
-
-/* For the HPPA, REG and REG+CONST is cost 0
-   and addresses involving symbolic constants are cost 2.
-
-   PIC addresses are very expensive.
-
-   It is no coincidence that this has the same structure
-   as GO_IF_LEGITIMATE_ADDRESS.  */
-int
-hppa_address_cost (X)
-     rtx X;
-{
-  if (GET_CODE (X) == PLUS)
-      return 1;
-  else if (GET_CODE (X) == LO_SUM)
-    return 1;
-  else if (GET_CODE (X) == HIGH)
-    return 2;
-  return 4;
-}
-
-/* Emit insns to move operands[1] into operands[0].
-
-   Return 1 if we have written out everything that needs to be done to
-   do the move.  Otherwise, return 0 and the caller will emit the move
-   normally.  */
-
-int
-emit_move_sequence (operands, mode, scratch_reg)
-     rtx *operands;
-     enum machine_mode mode;
-     rtx scratch_reg;
-{
-  register rtx operand0 = operands[0];
-  register rtx operand1 = operands[1];
-  register rtx tem;
-
-  if (scratch_reg
-      && reload_in_progress && GET_CODE (operand0) == REG
-      && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
-    operand0 = reg_equiv_mem[REGNO (operand0)];
-  else if (scratch_reg
-	   && reload_in_progress && GET_CODE (operand0) == SUBREG
-	   && GET_CODE (SUBREG_REG (operand0)) == REG
-	   && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
-    {
-      SUBREG_REG (operand0) = reg_equiv_mem[REGNO (SUBREG_REG (operand0))];
-      operand0 = alter_subreg (operand0);
-    }
-
-  if (scratch_reg
-      && reload_in_progress && GET_CODE (operand1) == REG
-      && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
-    operand1 = reg_equiv_mem[REGNO (operand1)];
-  else if (scratch_reg
-	   && reload_in_progress && GET_CODE (operand1) == SUBREG
-	   && GET_CODE (SUBREG_REG (operand1)) == REG
-	   && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
-    {
-      SUBREG_REG (operand1) = reg_equiv_mem[REGNO (SUBREG_REG (operand1))];
-      operand1 = alter_subreg (operand1);
-    }
-
-  if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
-      && ((tem = find_replacement (&XEXP (operand0, 0)))
-	  != XEXP (operand0, 0)))
-    operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
-  if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
-      && ((tem = find_replacement (&XEXP (operand1, 0)))
-	  != XEXP (operand1, 0)))
-    operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
-
-  /* Handle secondary reloads for loads/stores of FP registers from
-     REG+D addresses where D does not fit in 5 bits, including 
-     (subreg (mem (addr))) cases.  */
-  if (fp_reg_operand (operand0, mode)
-      && ((GET_CODE (operand1) == MEM
-	   && ! memory_address_p (DFmode, XEXP (operand1, 0)))
-	  || ((GET_CODE (operand1) == SUBREG
-	       && GET_CODE (XEXP (operand1, 0)) == MEM
-	       && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
-      && scratch_reg)
-    {
-      if (GET_CODE (operand1) == SUBREG)
-	operand1 = XEXP (operand1, 0);
-
-      scratch_reg = gen_rtx_REG (SImode, REGNO (scratch_reg));
-
-      /* D might not fit in 14 bits either; for such cases load D into
-	 scratch reg.  */
-      if (!memory_address_p (SImode, XEXP (operand1, 0)))
-	{
-	  emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
-	  emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
-						       SImode,
-						       XEXP (XEXP (operand1, 0), 0),
-						       scratch_reg));
-	}
-      else
-	emit_move_insn (scratch_reg, XEXP (operand1, 0));
-      emit_insn (gen_rtx_SET (VOIDmode, operand0, gen_rtx_MEM (mode,
-							       scratch_reg)));
-      return 1;
-    }
-  else if (fp_reg_operand (operand1, mode)
-	   && ((GET_CODE (operand0) == MEM
-		&& ! memory_address_p (DFmode, XEXP (operand0, 0)))
-	       || ((GET_CODE (operand0) == SUBREG)
-		   && GET_CODE (XEXP (operand0, 0)) == MEM
-		   && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
-	   && scratch_reg)
-    {
-      if (GET_CODE (operand0) == SUBREG)
-	operand0 = XEXP (operand0, 0);
-
-      scratch_reg = gen_rtx_REG (SImode, REGNO (scratch_reg));
-      /* D might not fit in 14 bits either; for such cases load D into
-	 scratch reg.  */
-      if (!memory_address_p (SImode, XEXP (operand0, 0)))
-	{
-	  emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
-	  emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
-								        0)),
-						       SImode,
-						       XEXP (XEXP (operand0, 0),
-								   0),
-						       scratch_reg));
-	}
-      else
-	emit_move_insn (scratch_reg, XEXP (operand0, 0));
-      emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
-			      operand1));
-      return 1;
-    }
-  /* Handle secondary reloads for loads of FP registers from constant
-     expressions by forcing the constant into memory.
-
-     use scratch_reg to hold the address of the memory location.
-
-     ??? The proper fix is to change PREFERRED_RELOAD_CLASS to return
-     NO_REGS when presented with a const_int and an register class
-     containing only FP registers.  Doing so unfortunately creates
-     more problems than it solves.   Fix this for 2.5.  */
-  else if (fp_reg_operand (operand0, mode)
-	   && CONSTANT_P (operand1)
-	   && scratch_reg)
-    {
-      rtx xoperands[2];
-
-      /* Force the constant into memory and put the address of the
-	 memory location into scratch_reg.  */
-      xoperands[0] = scratch_reg;
-      xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
-      emit_move_sequence (xoperands, Pmode, 0);
-
-      /* Now load the destination register.  */
-      emit_insn (gen_rtx_SET (mode, operand0, gen_rtx_MEM (mode, scratch_reg)));
-      return 1;
-    }
-  /* Handle secondary reloads for SAR.  These occur when trying to load
-     the SAR from memory a FP register, or with a constant.  */
-  else if (GET_CODE (operand0) == REG
-	   && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
-	   && (GET_CODE (operand1) == MEM
-	       || GET_CODE (operand1) == CONST_INT
-	       || (GET_CODE (operand1) == REG
-		   && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
-	   && scratch_reg)
-    {
-      /* D might not fit in 14 bits either; for such cases load D into
-	 scratch reg.  */
-      if (GET_CODE (operand1) == MEM
-	  && !memory_address_p (SImode, XEXP (operand1, 0)))
-	{
-	  emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));	
-	  emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
-								        0)),
-						       SImode,
-						       XEXP (XEXP (operand1, 0),
-						       0),
-						       scratch_reg));
-	  emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand1),
-						    scratch_reg));
-	}
-      else
-	emit_move_insn (scratch_reg, operand1);
-      emit_move_insn (operand0, scratch_reg);
-      return 1;
-    }
-  /* Handle most common case: storing into a register.  */
-  else if (register_operand (operand0, mode))
-    {
-      if (register_operand (operand1, mode)
-	  || (GET_CODE (operand1) == CONST_INT && INT_14_BITS (operand1))
-	  || (operand1 == CONST0_RTX (mode))
-	  || (GET_CODE (operand1) == HIGH
-	      && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
-	  /* Only `general_operands' can come here, so MEM is ok.  */
-	  || GET_CODE (operand1) == MEM)
-	{
-	  /* Run this case quickly.  */
-	  emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
-	  return 1;
-	}
-    }
-  else if (GET_CODE (operand0) == MEM)
-    {
-      if (mode == DFmode && operand1 == CONST0_RTX (mode)
-	  && !(reload_in_progress || reload_completed))
-	{
-	  rtx temp = gen_reg_rtx (DFmode);
-
-	  emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
-	  emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
-	  return 1;
-	}
-      if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
-	{
-	  /* Run this case quickly.  */
-	  emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
-	  return 1;
-	}
-      if (! (reload_in_progress || reload_completed))
-	{
-	  operands[0] = validize_mem (operand0);
-	  operands[1] = operand1 = force_reg (mode, operand1);
-	}
-    }
-
-  /* Simplify the source if we need to.
-     Note we do have to handle function labels here, even though we do
-     not consider them legitimate constants.  Loop optimizations can
-     call the emit_move_xxx with one as a source.  */
-  if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
-      || function_label_operand (operand1, mode)
-      || (GET_CODE (operand1) == HIGH
-	  && symbolic_operand (XEXP (operand1, 0), mode)))
-    {
-      int ishighonly = 0;
-
-      if (GET_CODE (operand1) == HIGH)
-	{
-	  ishighonly = 1;
-	  operand1 = XEXP (operand1, 0);
-	}
-      if (symbolic_operand (operand1, mode))
-	{
-	  /* Argh.  The assembler and linker can't handle arithmetic
-	     involving plabels.
-
-	     So we force the plabel into memory, load operand0 from
-	     the memory location, then add in the constant part.  */
-	  if ((GET_CODE (operand1) == CONST
-	       && GET_CODE (XEXP (operand1, 0)) == PLUS
-	       && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
-	      || function_label_operand (operand1, mode))
-	    {
-	      rtx temp, const_part;
-
-	      /* Figure out what (if any) scratch register to use.  */
-	      if (reload_in_progress || reload_completed)
-		scratch_reg = scratch_reg ? scratch_reg : operand0;
-	      else if (flag_pic)
-		scratch_reg = gen_reg_rtx (Pmode);
-
-	      if (GET_CODE (operand1) == CONST)
-		{
-		  /* Save away the constant part of the expression.  */
-		  const_part = XEXP (XEXP (operand1, 0), 1);
-		  if (GET_CODE (const_part) != CONST_INT)
-		    abort ();
-
-		  /* Force the function label into memory.  */
-		  temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
-		}
-	      else
-		{
-		  /* No constant part.  */
-		  const_part = NULL_RTX;
-
-		  /* Force the function label into memory.  */
-		  temp = force_const_mem (mode, operand1);
-		}
-		
-
-	      /* Get the address of the memory location.  PIC-ify it if
-		 necessary.  */
-	      temp = XEXP (temp, 0);
-	      if (flag_pic)
-		temp = legitimize_pic_address (temp, mode, scratch_reg);
-
-	      /* Put the address of the memory location into our destination
-		 register.  */
-	      operands[1] = temp;
-	      emit_move_sequence (operands, mode, scratch_reg);
-
-	      /* Now load from the memory location into our destination
-		 register.  */
-	      operands[1] = gen_rtx_MEM (Pmode, operands[0]);
-	      emit_move_sequence (operands, mode, scratch_reg);
-
-	      /* And add back in the constant part.  */
-	      if (const_part != NULL_RTX)
-		expand_inc (operand0, const_part);
-
-	      return 1;
-	    }
-
-	  if (flag_pic)
-	    {
-	      rtx temp;
-
-	      if (reload_in_progress || reload_completed)
-		temp = scratch_reg ? scratch_reg : operand0;
-	      else
-		temp = gen_reg_rtx (Pmode);
-
-	      /* (const (plus (symbol) (const_int))) must be forced to
-		 memory during/after reload if the const_int will not fit
-		 in 14 bits.  */
-	      if (GET_CODE (operand1) == CONST
-		       && GET_CODE (XEXP (operand1, 0)) == PLUS
-		       && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
-		       && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
-		       && (reload_completed || reload_in_progress)
-		       && flag_pic)
-		{
-		  operands[1] = force_const_mem (mode, operand1);
-		  operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
-							mode, temp);
-		  emit_move_sequence (operands, mode, temp);
-		}
-	      else
-		{
-		  operands[1] = legitimize_pic_address (operand1, mode, temp);
-		  emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
-		}
-	    }
-	  /* On the HPPA, references to data space are supposed to use dp,
-	     register 27, but showing it in the RTL inhibits various cse
-	     and loop optimizations.  */
-	  else
-	    {
-	      rtx temp, set;
-
-	      if (reload_in_progress || reload_completed)
-		temp = scratch_reg ? scratch_reg : operand0;
-	      else
-		temp = gen_reg_rtx (mode);
-
-	      /* Loading a SYMBOL_REF into a register makes that register
-		 safe to be used as the base in an indexed address. 
-
-		 Don't mark hard registers though.  That loses.  */
-	      if (GET_CODE (operand0) == REG
-		  && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
-		REGNO_POINTER_FLAG (REGNO (operand0)) = 1;
-	      if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
-		REGNO_POINTER_FLAG (REGNO (temp)) = 1;
-	      if (ishighonly)
-		set = gen_rtx_SET (mode, operand0, temp);
-	      else
-		set = gen_rtx_SET (VOIDmode, operand0,
-				   gen_rtx_LO_SUM (mode, temp, operand1));
-
-	      emit_insn (gen_rtx_SET (VOIDmode,
-				      temp,
-				      gen_rtx_HIGH (mode, operand1)));
-	      emit_insn (set);
-
-	    }
-	  return 1;
-	}
-      else if (GET_CODE (operand1) != CONST_INT
-	       || ! cint_ok_for_move (INTVAL (operand1)))
-	{
-	  rtx temp;
-
-	  if (reload_in_progress || reload_completed)
-	    temp = operand0;
-	  else
-	    temp = gen_reg_rtx (mode);
-
-	  emit_insn (gen_rtx_SET (VOIDmode, temp,
-				  gen_rtx_HIGH (mode, operand1)));
-	  operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
-	}
-    }
-  /* Now have insn-emit do whatever it normally does.  */
-  return 0;
-}
-
-/* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
-   it will need a link/runtime reloc).  */
-
-int
-reloc_needed (exp)
-     tree exp;
-{
-  int reloc = 0;
-
-  switch (TREE_CODE (exp))
-    {
-    case ADDR_EXPR:
-      return 1;
-
-    case PLUS_EXPR:
-    case MINUS_EXPR:
-      reloc = reloc_needed (TREE_OPERAND (exp, 0));
-      reloc |= reloc_needed (TREE_OPERAND (exp, 1));
-      break;
-
-    case NOP_EXPR:
-    case CONVERT_EXPR:
-    case NON_LVALUE_EXPR:
-      reloc = reloc_needed (TREE_OPERAND (exp, 0));
-      break;
-
-    case CONSTRUCTOR:
-      {
-	register tree link;
-	for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
-	  if (TREE_VALUE (link) != 0)
-	    reloc |= reloc_needed (TREE_VALUE (link));
-      }
-      break;
-
-    case ERROR_MARK:
-      break;
-
-    default:
-      break;
-    }
-  return reloc;
-}
-
-/* Does operand (which is a symbolic_operand) live in text space? If
-   so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true.  */
-
-int
-read_only_operand (operand)
-     rtx operand;
-{
-  if (GET_CODE (operand) == CONST)
-    operand = XEXP (XEXP (operand, 0), 0);
-  if (flag_pic)
-    {
-      if (GET_CODE (operand) == SYMBOL_REF)
-	return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
-    }
-  else
-    {
-      if (GET_CODE (operand) == SYMBOL_REF)
-	return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
-    }
-  return 1;
-}
-
-
-/* Return the best assembler insn template
-   for moving operands[1] into operands[0] as a fullword.   */
-char *
-singlemove_string (operands)
-     rtx *operands;
-{
-  HOST_WIDE_INT intval;
-
-  if (GET_CODE (operands[0]) == MEM)
-    return "stw %r1,%0";
-  if (GET_CODE (operands[1]) == MEM)
-    return "ldw %1,%0";
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    {
-      long i;
-      REAL_VALUE_TYPE d;
-
-      if (GET_MODE (operands[1]) != SFmode)
-	abort ();
-
-      /* Translate the CONST_DOUBLE to a CONST_INT with the same target
-	 bit pattern.  */
-      REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
-      REAL_VALUE_TO_TARGET_SINGLE (d, i);
-
-      operands[1] = GEN_INT (i);
-      /* Fall through to CONST_INT case.  */
-    }
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      intval = INTVAL (operands[1]);
-
-      if (VAL_14_BITS_P (intval))
-	return "ldi %1,%0";
-      else if ((intval & 0x7ff) == 0)
-	return "ldil L'%1,%0";
-      else if (zdepi_cint_p (intval))
-	return "zdepi %Z1,%0";
-      else
-	return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
-    }
-  return "copy %1,%0";
-}
-
-
-/* Compute position (in OP[1]) and width (in OP[2])
-   useful for copying IMM to a register using the zdepi
-   instructions.  Store the immediate value to insert in OP[0].  */
-void
-compute_zdepi_operands (imm, op)
-     unsigned HOST_WIDE_INT imm;
-     unsigned *op;
-{
-  int lsb, len;
-
-  /* Find the least significant set bit in IMM.  */
-  for (lsb = 0; lsb < 32; lsb++)
-    {
-      if ((imm & 1) != 0)
-        break;
-      imm >>= 1;
-    }
-
-  /* Choose variants based on *sign* of the 5-bit field.  */
-  if ((imm & 0x10) == 0)
-    len = (lsb <= 28) ? 4 : 32 - lsb;
-  else
-    {
-      /* Find the width of the bitstring in IMM.  */
-      for (len = 5; len < 32; len++)
-	{
-	  if ((imm & (1 << len)) == 0)
-	    break;
-	}
-
-      /* Sign extend IMM as a 5-bit value.  */
-      imm = (imm & 0xf) - 0x10;
-    }
-
-  op[0] = imm;
-  op[1] = 31 - lsb;
-  op[2] = len;
-}
-
-/* Output assembler code to perform a doubleword move insn
-   with operands OPERANDS.  */
-
-char *
-output_move_double (operands)
-     rtx *operands;
-{
-  enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
-  rtx latehalf[2];
-  rtx addreg0 = 0, addreg1 = 0;
-
-  /* First classify both operands.  */
-
-  if (REG_P (operands[0]))
-    optype0 = REGOP;
-  else if (offsettable_memref_p (operands[0]))
-    optype0 = OFFSOP;
-  else if (GET_CODE (operands[0]) == MEM)
-    optype0 = MEMOP;
-  else
-    optype0 = RNDOP;
-
-  if (REG_P (operands[1]))
-    optype1 = REGOP;
-  else if (CONSTANT_P (operands[1]))
-    optype1 = CNSTOP;
-  else if (offsettable_memref_p (operands[1]))
-    optype1 = OFFSOP;
-  else if (GET_CODE (operands[1]) == MEM)
-    optype1 = MEMOP;
-  else
-    optype1 = RNDOP;
-
-  /* Check for the cases that the operand constraints are not
-     supposed to allow to happen.  Abort if we get one,
-     because generating code for these cases is painful.  */
-
-  if (optype0 != REGOP && optype1 != REGOP)
-    abort ();
-
-   /* Handle auto decrementing and incrementing loads and stores
-     specifically, since the structure of the function doesn't work
-     for them without major modification.  Do it better when we learn
-     this port about the general inc/dec addressing of PA.
-     (This was written by tege.  Chide him if it doesn't work.)  */
-
-  if (optype0 == MEMOP)
-    {
-      /* We have to output the address syntax ourselves, since print_operand
-	 doesn't deal with the addresses we want to use.  Fix this later.  */
-
-      rtx addr = XEXP (operands[0], 0);
-      if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
-	{
-	  rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
-
-	  operands[0] = XEXP (addr, 0);
-	  if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
-	    abort ();
-
-	  if (!reg_overlap_mentioned_p (high_reg, addr))
-	    {
-	      /* No overlap between high target register and address
-		 register.  (We do this in a non-obvious way to
-		 save a register file writeback)  */
-	      if (GET_CODE (addr) == POST_INC)
-		return "stws,ma %1,8(0,%0)\n\tstw %R1,-4(0,%0)";
-	      return "stws,ma %1,-8(0,%0)\n\tstw %R1,12(0,%0)";
-	    }
-	  else
-	    abort();
-	}
-      else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
-	{
-	  rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
-
-	  operands[0] = XEXP (addr, 0);
-	  if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
-	    abort ();
-
-	  if (!reg_overlap_mentioned_p (high_reg, addr))
-	    {
-	      /* No overlap between high target register and address
-		 register.  (We do this in a non-obvious way to
-		 save a register file writeback)  */
-	      if (GET_CODE (addr) == PRE_INC)
-		return "stws,mb %1,8(0,%0)\n\tstw %R1,4(0,%0)";
-	      return "stws,mb %1,-8(0,%0)\n\tstw %R1,4(0,%0)";
-	    }
-	  else
-	    abort();
-	}
-    }
-  if (optype1 == MEMOP)
-    {
-      /* We have to output the address syntax ourselves, since print_operand
-	 doesn't deal with the addresses we want to use.  Fix this later.  */
-
-      rtx addr = XEXP (operands[1], 0);
-      if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
-	{
-	  rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
-
-	  operands[1] = XEXP (addr, 0);
-	  if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
-	    abort ();
-
-	  if (!reg_overlap_mentioned_p (high_reg, addr))
-	    {
-	      /* No overlap between high target register and address
-		 register.  (We do this in a non-obvious way to
-		 save a register file writeback)  */
-	      if (GET_CODE (addr) == POST_INC)
-		return "ldws,ma 8(0,%1),%0\n\tldw -4(0,%1),%R0";
-	      return "ldws,ma -8(0,%1),%0\n\tldw 12(0,%1),%R0";
-	    }
-	  else
-	    {
-	      /* This is an undefined situation.  We should load into the
-		 address register *and* update that register.  Probably
-		 we don't need to handle this at all.  */
-	      if (GET_CODE (addr) == POST_INC)
-		return "ldw 4(0,%1),%R0\n\tldws,ma 8(0,%1),%0";
-	      return "ldw 4(0,%1),%R0\n\tldws,ma -8(0,%1),%0";
-	    }
-	}
-      else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
-	{
-	  rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
-
-	  operands[1] = XEXP (addr, 0);
-	  if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
-	    abort ();
-
-	  if (!reg_overlap_mentioned_p (high_reg, addr))
-	    {
-	      /* No overlap between high target register and address
-		 register.  (We do this in a non-obvious way to
-		 save a register file writeback)  */
-	      if (GET_CODE (addr) == PRE_INC)
-		return "ldws,mb 8(0,%1),%0\n\tldw 4(0,%1),%R0";
-	      return "ldws,mb -8(0,%1),%0\n\tldw 4(0,%1),%R0";
-	    }
-	  else
-	    {
-	      /* This is an undefined situation.  We should load into the
-		 address register *and* update that register.  Probably
-		 we don't need to handle this at all.  */
-	      if (GET_CODE (addr) == PRE_INC)
-		return "ldw 12(0,%1),%R0\n\tldws,mb 8(0,%1),%0";
-	      return "ldw -4(0,%1),%R0\n\tldws,mb -8(0,%1),%0";
-	    }
-	}
-      else if (GET_CODE (addr) == PLUS
-	       && GET_CODE (XEXP (addr, 0)) == MULT)
-	{
-	  rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
-
-	  if (!reg_overlap_mentioned_p (high_reg, addr))
-	    {
-	      rtx xoperands[3];
-
-	      xoperands[0] = high_reg;
-	      xoperands[1] = XEXP (addr, 1);
-	      xoperands[2] = XEXP (XEXP (addr, 0), 0);
-	      xoperands[3] = XEXP (XEXP (addr, 0), 1);
-	      output_asm_insn ("sh%O3addl %2,%1,%0", xoperands);
-	      return "ldw 4(0,%0),%R0\n\tldw 0(0,%0),%0";
-	    }
-	  else
-	    {
-	      rtx xoperands[3];
-
-	      xoperands[0] = high_reg;
-	      xoperands[1] = XEXP (addr, 1);
-	      xoperands[2] = XEXP (XEXP (addr, 0), 0);
-	      xoperands[3] = XEXP (XEXP (addr, 0), 1);
-	      output_asm_insn ("sh%O3addl %2,%1,%R0", xoperands);
-	      return "ldw 0(0,%R0),%0\n\tldw 4(0,%R0),%R0";
-	    }
-	   
-	}
-    }
-
-  /* If an operand is an unoffsettable memory ref, find a register
-     we can increment temporarily to make it refer to the second word.  */
-
-  if (optype0 == MEMOP)
-    addreg0 = find_addr_reg (XEXP (operands[0], 0));
-
-  if (optype1 == MEMOP)
-    addreg1 = find_addr_reg (XEXP (operands[1], 0));
-
-  /* Ok, we can do one word at a time.
-     Normally we do the low-numbered word first.
-
-     In either case, set up in LATEHALF the operands to use
-     for the high-numbered word and in some cases alter the
-     operands in OPERANDS to be suitable for the low-numbered word.  */
-
-  if (optype0 == REGOP)
-    latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  else if (optype0 == OFFSOP)
-    latehalf[0] = adj_offsettable_operand (operands[0], 4);
-  else
-    latehalf[0] = operands[0];
-
-  if (optype1 == REGOP)
-    latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-  else if (optype1 == OFFSOP)
-    latehalf[1] = adj_offsettable_operand (operands[1], 4);
-  else if (optype1 == CNSTOP)
-    split_double (operands[1], &operands[1], &latehalf[1]);
-  else
-    latehalf[1] = operands[1];
-
-  /* If the first move would clobber the source of the second one,
-     do them in the other order.
-
-     This can happen in two cases:
-
-	mem -> register where the first half of the destination register
- 	is the same register used in the memory's address.  Reload
-	can create such insns.
-
-	mem in this case will be either register indirect or register
-	indirect plus a valid offset. 
-
-	register -> register move where REGNO(dst) == REGNO(src + 1)
-	someone (Tim/Tege?) claimed this can happen for parameter loads. 
-
-     Handle mem -> register case first.  */
-  if (optype0 == REGOP
-      && (optype1 == MEMOP || optype1 == OFFSOP)
-      && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			    operands[1], 0))
-    {
-      /* Do the late half first.  */
-      if (addreg1)
-	output_asm_insn ("ldo 4(%0),%0", &addreg1);
-      output_asm_insn (singlemove_string (latehalf), latehalf);
-
-      /* Then clobber.  */
-      if (addreg1)
-	output_asm_insn ("ldo -4(%0),%0", &addreg1);
-      return singlemove_string (operands);
-    }
-
-  /* Now handle register -> register case.  */
-  if (optype0 == REGOP && optype1 == REGOP
-      && REGNO (operands[0]) == REGNO (operands[1]) + 1)
-    {
-      output_asm_insn (singlemove_string (latehalf), latehalf);
-      return singlemove_string (operands);
-    }
-
-  /* Normal case: do the two words, low-numbered first.  */
-
-  output_asm_insn (singlemove_string (operands), operands);
-
-  /* Make any unoffsettable addresses point at high-numbered word.  */
-  if (addreg0)
-    output_asm_insn ("ldo 4(%0),%0", &addreg0);
-  if (addreg1)
-    output_asm_insn ("ldo 4(%0),%0", &addreg1);
-
-  /* Do that word.  */
-  output_asm_insn (singlemove_string (latehalf), latehalf);
-
-  /* Undo the adds we just did.  */
-  if (addreg0)
-    output_asm_insn ("ldo -4(%0),%0", &addreg0);
-  if (addreg1)
-    output_asm_insn ("ldo -4(%0),%0", &addreg1);
-
-  return "";
-}
-
-char *
-output_fp_move_double (operands)
-     rtx *operands;
-{
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1])
-	  || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
-	output_asm_insn ("fcpy,dbl %r1,%0", operands);
-      else
-	output_asm_insn ("fldd%F1 %1,%0", operands);
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      output_asm_insn ("fstd%F0 %1,%0", operands);
-    }
-  else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
-    {
-      if (GET_CODE (operands[0]) == REG)
-	{
-	  rtx xoperands[2];
-	  xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-	  xoperands[0] = operands[0];
-	  output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
-	}
-      /* This is a pain.  You have to be prepared to deal with an
-	 arbitrary address here including pre/post increment/decrement.
-
-	 so avoid this in the MD.  */
-      else
-	abort ();
-    }
-  else abort ();
-  return "";
-}
-
-/* Return a REG that occurs in ADDR with coefficient 1.
-   ADDR can be effectively incremented by incrementing REG.  */
-
-static rtx
-find_addr_reg (addr)
-     rtx addr;
-{
-  while (GET_CODE (addr) == PLUS)
-    {
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-	addr = XEXP (addr, 0);
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	addr = XEXP (addr, 1);
-      else if (CONSTANT_P (XEXP (addr, 0)))
-	addr = XEXP (addr, 1);
-      else if (CONSTANT_P (XEXP (addr, 1)))
-	addr = XEXP (addr, 0);
-      else
-	abort ();
-    }
-  if (GET_CODE (addr) == REG)
-    return addr;
-  abort ();
-}
-
-/* Emit code to perform a block move.
-
-   OPERANDS[0] is the destination pointer as a REG, clobbered.
-   OPERANDS[1] is the source pointer as a REG, clobbered.
-   OPERANDS[2] is a register for temporary storage.
-   OPERANDS[4] is the size as a CONST_INT
-   OPERANDS[3] is a register for temporary storage.
-   OPERANDS[5] is the alignment safe to use, as a CONST_INT. 
-   OPERANDS[6] is another temporary register.   */
-
-char *
-output_block_move (operands, size_is_constant)
-     rtx *operands;
-     int size_is_constant ATTRIBUTE_UNUSED;
-{
-  int align = INTVAL (operands[5]);
-  unsigned long n_bytes = INTVAL (operands[4]);
-
-  /* We can't move more than four bytes at a time because the PA
-     has no longer integer move insns.  (Could use fp mem ops?)  */
-  if (align > 4)
-    align = 4;
-
-  /* Note that we know each loop below will execute at least twice
-     (else we would have open-coded the copy).  */
-  switch (align)
-    {
-      case 4:
-	/* Pre-adjust the loop counter.  */
-	operands[4] = GEN_INT (n_bytes - 8);
-	output_asm_insn ("ldi %4,%2", operands);
-
-	/* Copying loop.  */
-	output_asm_insn ("ldws,ma 4(0,%1),%3", operands);
-	output_asm_insn ("ldws,ma 4(0,%1),%6", operands);
-	output_asm_insn ("stws,ma %3,4(0,%0)", operands);
-	output_asm_insn ("addib,>= -8,%2,.-12", operands);
-	output_asm_insn ("stws,ma %6,4(0,%0)", operands);
-
-	/* Handle the residual.  There could be up to 7 bytes of
-	   residual to copy!  */
-	if (n_bytes % 8 != 0)
-	  {
-	    operands[4] = GEN_INT (n_bytes % 4);
-	    if (n_bytes % 8 >= 4)
-	      output_asm_insn ("ldws,ma 4(0,%1),%3", operands);
-	    if (n_bytes % 4 != 0)
-	      output_asm_insn ("ldw 0(0,%1),%6", operands);
-	    if (n_bytes % 8 >= 4)
-	      output_asm_insn ("stws,ma %3,4(0,%0)", operands);
-	    if (n_bytes % 4 != 0)
-	      output_asm_insn ("stbys,e %6,%4(0,%0)", operands);
-	  }
-	return "";
-
-      case 2:
-	/* Pre-adjust the loop counter.  */
-	operands[4] = GEN_INT (n_bytes - 4);
-	output_asm_insn ("ldi %4,%2", operands);
-
-	/* Copying loop.  */
-	output_asm_insn ("ldhs,ma 2(0,%1),%3", operands);
-	output_asm_insn ("ldhs,ma 2(0,%1),%6", operands);
-	output_asm_insn ("sths,ma %3,2(0,%0)", operands);
-	output_asm_insn ("addib,>= -4,%2,.-12", operands);
-	output_asm_insn ("sths,ma %6,2(0,%0)", operands);
-
-	/* Handle the residual.  */
-	if (n_bytes % 4 != 0)
-	  {
-	    if (n_bytes % 4 >= 2)
-	      output_asm_insn ("ldhs,ma 2(0,%1),%3", operands);
-	    if (n_bytes % 2 != 0)
-	      output_asm_insn ("ldb 0(0,%1),%6", operands);
-	    if (n_bytes % 4 >= 2)
-	      output_asm_insn ("sths,ma %3,2(0,%0)", operands);
-	    if (n_bytes % 2 != 0)
-	      output_asm_insn ("stb %6,0(0,%0)", operands);
-	  }
-	return "";
-
-      case 1:
-	/* Pre-adjust the loop counter.  */
-	operands[4] = GEN_INT (n_bytes - 2);
-	output_asm_insn ("ldi %4,%2", operands);
-
-	/* Copying loop.  */
-	output_asm_insn ("ldbs,ma 1(0,%1),%3", operands);
-	output_asm_insn ("ldbs,ma 1(0,%1),%6", operands);
-	output_asm_insn ("stbs,ma %3,1(0,%0)", operands);
-	output_asm_insn ("addib,>= -2,%2,.-12", operands);
-	output_asm_insn ("stbs,ma %6,1(0,%0)", operands);
-
-	/* Handle the residual.  */
-	if (n_bytes % 2 != 0)
-	  {
-	    output_asm_insn ("ldb 0(0,%1),%3", operands);
-	    output_asm_insn ("stb %3,0(0,%0)", operands);
-	  }
-	return "";
-
-      default:
-	abort ();
-    }
-}
-
-/* Count the number of insns necessary to handle this block move.
-
-   Basic structure is the same as emit_block_move, except that we
-   count insns rather than emit them.  */
-
-int
-compute_movstrsi_length (insn)
-     rtx insn;
-{
-  rtx pat = PATTERN (insn);
-  int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
-  unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
-  unsigned int n_insns = 0;
-
-  /* We can't move more than four bytes at a time because the PA
-     has no longer integer move insns.  (Could use fp mem ops?)  */
-  if (align > 4)
-    align = 4;
-
-  /* The basic copying loop.  */
-  n_insns = 6;
-
-  /* Residuals.  */
-  if (n_bytes % (2 * align) != 0)
-    {
-      if ((n_bytes % (2 * align)) >= align)
-	n_insns += 2;
-
-      if ((n_bytes % align) != 0)
-	n_insns += 2;
-    }
-
-  /* Lengths are expressed in bytes now; each insn is 4 bytes.  */
-  return n_insns * 4;
-}
-
-
-char *
-output_and (operands)
-     rtx *operands;
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
-    {
-      unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
-      int ls0, ls1, ms0, p, len;
-
-      for (ls0 = 0; ls0 < 32; ls0++)
-	if ((mask & (1 << ls0)) == 0)
-	  break;
-
-      for (ls1 = ls0; ls1 < 32; ls1++)
-	if ((mask & (1 << ls1)) != 0)
-	  break;
-
-      for (ms0 = ls1; ms0 < 32; ms0++)
-	if ((mask & (1 << ms0)) == 0)
-	  break;
-
-      if (ms0 != 32)
-	abort();
-
-      if (ls1 == 32)
-	{
-	  len = ls0;
-
-	  if (len == 0)
-	    abort ();
-
-	  operands[2] = GEN_INT (len);
-	  return "extru %1,31,%2,%0";
-	}
-      else
-	{
-	  /* We could use this `depi' for the case above as well, but `depi'
-	     requires one more register file access than an `extru'.  */
-
-	  p = 31 - ls0;
-	  len = ls1 - ls0;
-
-	  operands[2] = GEN_INT (p);
-	  operands[3] = GEN_INT (len);
-	  return "depi 0,%2,%3,%0";
-	}
-    }
-  else
-    return "and %1,%2,%0";
-}
-
-char *
-output_ior (operands)
-     rtx *operands;
-{
-  unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
-  int bs0, bs1, p, len;
-
-  if (INTVAL (operands[2]) == 0)
-    return "copy %1,%0";
-
-  for (bs0 = 0; bs0 < 32; bs0++)
-    if ((mask & (1 << bs0)) != 0)
-      break;
-
-  for (bs1 = bs0; bs1 < 32; bs1++)
-    if ((mask & (1 << bs1)) == 0)
-      break;
-
-  if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
-    abort();
-
-  p = 31 - bs0;
-  len = bs1 - bs0;
-
-  operands[2] = GEN_INT (p);
-  operands[3] = GEN_INT (len);
-  return "depi -1,%2,%3,%0";
-}
-
-/* Output an ascii string.  */
-void
-output_ascii (file, p, size)
-     FILE *file;
-     unsigned char *p;
-     int size;
-{
-  int i;
-  int chars_output;
-  unsigned char partial_output[16];	/* Max space 4 chars can occupy.   */
-
-  /* The HP assembler can only take strings of 256 characters at one
-     time.  This is a limitation on input line length, *not* the
-     length of the string.  Sigh.  Even worse, it seems that the
-     restriction is in number of input characters (see \xnn &
-     \whatever).  So we have to do this very carefully.  */
-
-  fputs ("\t.STRING \"", file);
-
-  chars_output = 0;
-  for (i = 0; i < size; i += 4)
-    {
-      int co = 0;
-      int io = 0;
-      for (io = 0, co = 0; io < MIN (4, size - i); io++)
-	{
-	  register unsigned int c = p[i + io];
-
-	  if (c == '\"' || c == '\\')
-	    partial_output[co++] = '\\';
-	  if (c >= ' ' && c < 0177)
-	    partial_output[co++] = c;
-	  else
-	    {
-	      unsigned int hexd;
-	      partial_output[co++] = '\\';
-	      partial_output[co++] = 'x';
-	      hexd =  c  / 16 - 0 + '0';
-	      if (hexd > '9')
-		hexd -= '9' - 'a' + 1;
-	      partial_output[co++] = hexd;
-	      hexd =  c % 16 - 0 + '0';
-	      if (hexd > '9')
-		hexd -= '9' - 'a' + 1;
-	      partial_output[co++] = hexd;
-	    }
-	}
-      if (chars_output + co > 243)
-	{
-	  fputs ("\"\n\t.STRING \"", file);
-	  chars_output = 0;
-	}
-      fwrite (partial_output, 1, co, file);
-      chars_output += co;
-      co = 0;
-    }
-  fputs ("\"\n", file);
-}
-
-/* Try to rewrite floating point comparisons & branches to avoid
-   useless add,tr insns.
-
-   CHECK_NOTES is nonzero if we should examine REG_DEAD notes
-   to see if FPCC is dead.  CHECK_NOTES is nonzero for the
-   first attempt to remove useless add,tr insns.  It is zero
-   for the second pass as reorg sometimes leaves bogus REG_DEAD
-   notes lying around.
-
-   When CHECK_NOTES is zero we can only eliminate add,tr insns
-   when there's a 1:1 correspondence between fcmp and ftest/fbranch
-   instructions.  */
-void
-remove_useless_addtr_insns (insns, check_notes)
-     rtx insns;
-     int check_notes;
-{
-  rtx insn;
-  static int pass = 0;
-
-  /* This is fairly cheap, so always run it when optimizing.  */
-  if (optimize > 0)
-    {
-      int fcmp_count = 0;
-      int fbranch_count = 0;
-
-      /* Walk all the insns in this function looking for fcmp & fbranch
-	 instructions.  Keep track of how many of each we find.  */
-      insns = get_insns ();
-      for (insn = insns; insn; insn = next_insn (insn))
-	{
-	  rtx tmp;
-
-	  /* Ignore anything that isn't an INSN or a JUMP_INSN.  */
-	  if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
-	    continue;
-
-	  tmp = PATTERN (insn);
-
-	  /* It must be a set.  */
-	  if (GET_CODE (tmp) != SET)
-	    continue;
-
-	  /* If the destination is CCFP, then we've found an fcmp insn.  */
-	  tmp = SET_DEST (tmp);
-	  if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
-	    {
-	      fcmp_count++;
-	      continue;
-	    }
-	    
-	  tmp = PATTERN (insn);
-	  /* If this is an fbranch instruction, bump the fbranch counter.  */
-	  if (GET_CODE (tmp) == SET
-	      && SET_DEST (tmp) == pc_rtx
-	      && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
-	      && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
-	      && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
-	      && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
-	    {
-	      fbranch_count++;
-	      continue;
-	    }
-	}
-
-
-      /* Find all floating point compare + branch insns.  If possible,
-	 reverse the comparison & the branch to avoid add,tr insns.  */
-      for (insn = insns; insn; insn = next_insn (insn))
-	{
-	  rtx tmp, next;
-
-	  /* Ignore anything that isn't an INSN.  */
-	  if (GET_CODE (insn) != INSN)
-	    continue;
-
-	  tmp = PATTERN (insn);
-
-	  /* It must be a set.  */
-	  if (GET_CODE (tmp) != SET)
-	    continue;
-
-	  /* The destination must be CCFP, which is register zero.  */
-	  tmp = SET_DEST (tmp);
-	  if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
-	    continue;
-
-	  /* INSN should be a set of CCFP.
-
-	     See if the result of this insn is used in a reversed FP
-	     conditional branch.  If so, reverse our condition and
-	     the branch.  Doing so avoids useless add,tr insns.  */
-	  next = next_insn (insn);
-	  while (next)
-	    {
-	      /* Jumps, calls and labels stop our search.  */
-	      if (GET_CODE (next) == JUMP_INSN
-		  || GET_CODE (next) == CALL_INSN
-		  || GET_CODE (next) == CODE_LABEL)
-		break;
-
-	      /* As does another fcmp insn.  */
-	      if (GET_CODE (next) == INSN
-		  && GET_CODE (PATTERN (next)) == SET
-		  && GET_CODE (SET_DEST (PATTERN (next))) == REG
-		  && REGNO (SET_DEST (PATTERN (next))) == 0)
-		break;
-
-	      next = next_insn (next);
-	    }
-
-	  /* Is NEXT_INSN a branch?  */
-	  if (next
-	      && GET_CODE (next) == JUMP_INSN)
-	    {
-	      rtx pattern = PATTERN (next);
-
-	      /* If it a reversed fp conditional branch (eg uses add,tr)
-		 and CCFP dies, then reverse our conditional and the branch
-		 to avoid the add,tr.  */
-	      if (GET_CODE (pattern) == SET
-		  && SET_DEST (pattern) == pc_rtx
-		  && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
-		  && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
-		  && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
-		  && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
-		  && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
-		  && (fcmp_count == fbranch_count
-		      || (check_notes
-			  && find_regno_note (next, REG_DEAD, 0))))
-		{
-		  /* Reverse the branch.  */
-		  tmp = XEXP (SET_SRC (pattern), 1);
-		  XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
-		  XEXP (SET_SRC (pattern), 2) = tmp;
-		  INSN_CODE (next) = -1;
-
-		  /* Reverse our condition.  */
-		  tmp = PATTERN (insn);
-		  PUT_CODE (XEXP (tmp, 1),
-			    reverse_condition (GET_CODE (XEXP (tmp, 1))));
-		}
-	    }
-	}
-    }
-
-  pass = !pass;
-
-}
-
-/* You may have trouble believing this, but this is the HP-PA stack
-   layout.  Wow.
-
-   Offset		Contents
-
-   Variable arguments	(optional; any number may be allocated)
-
-   SP-(4*(N+9))		arg word N
-   	:		    :
-      SP-56		arg word 5
-      SP-52		arg word 4
-
-   Fixed arguments	(must be allocated; may remain unused)
-
-      SP-48		arg word 3
-      SP-44		arg word 2
-      SP-40		arg word 1
-      SP-36		arg word 0
-
-   Frame Marker
-
-      SP-32		External Data Pointer (DP)
-      SP-28		External sr4
-      SP-24		External/stub RP (RP')
-      SP-20		Current RP
-      SP-16		Static Link
-      SP-12		Clean up
-      SP-8		Calling Stub RP (RP'')
-      SP-4		Previous SP
-
-   Top of Frame
-
-      SP-0		Stack Pointer (points to next available address)
-
-*/
-
-/* This function saves registers as follows.  Registers marked with ' are
-   this function's registers (as opposed to the previous function's).
-   If a frame_pointer isn't needed, r4 is saved as a general register;
-   the space for the frame pointer is still allocated, though, to keep
-   things simple.
-
-
-   Top of Frame
-
-       SP (FP')		Previous FP
-       SP + 4		Alignment filler (sigh)
-       SP + 8		Space for locals reserved here.
-       .
-       .
-       .
-       SP + n		All call saved register used.
-       .
-       .
-       .
-       SP + o		All call saved fp registers used.
-       .
-       .
-       .
-       SP + p (SP')	points to next available address.
-
-*/
-
-/* Emit RTL to store REG at the memory location specified by BASE+DISP.
-   Handle case where DISP > 8k by using the add_high_const pattern.
-
-   Note in DISP > 8k case, we will leave the high part of the address
-   in %r1.  There is code in expand_hppa_{prologue,epilogue} that knows this.*/
-static void
-store_reg (reg, disp, base)
-     int reg, disp, base;
-{
-  if (VAL_14_BITS_P (disp))
-    {
-      emit_move_insn (gen_rtx_MEM (SImode,
-				   gen_rtx_PLUS (SImode,
-						 gen_rtx_REG (SImode, base),
-						 GEN_INT (disp))),
-				   gen_rtx_REG (SImode, reg));
-    }
-  else
-    {
-      emit_insn (gen_add_high_const (gen_rtx_REG (SImode, 1),
-				     gen_rtx_REG (SImode, base),
-				     GEN_INT (disp)));
-      emit_move_insn (gen_rtx_MEM (SImode,
-				   gen_rtx_LO_SUM (SImode,
-						   gen_rtx_REG (SImode, 1),
-						   GEN_INT (disp))),
-		      gen_rtx_REG (SImode, reg));
-    }
-}
-
-/* Emit RTL to load REG from the memory location specified by BASE+DISP.
-   Handle case where DISP > 8k by using the add_high_const pattern.
-
-   Note in DISP > 8k case, we will leave the high part of the address
-   in %r1.  There is code in expand_hppa_{prologue,epilogue} that knows this.*/
-static void
-load_reg (reg, disp, base)
-     int reg, disp, base;
-{
-  if (VAL_14_BITS_P (disp))
-    {
-      emit_move_insn (gen_rtx_REG (SImode, reg),
-		      gen_rtx_MEM (SImode,
-				   gen_rtx_PLUS (SImode,
-						 gen_rtx_REG (SImode, base),
-				            GEN_INT (disp))));
-    }
-  else
-    {
-      emit_insn (gen_add_high_const (gen_rtx_REG (SImode, 1),
-				     gen_rtx_REG (SImode, base),
-				     GEN_INT (disp)));
-      emit_move_insn (gen_rtx_REG (SImode, reg),
-		      gen_rtx_MEM (SImode,
-				   gen_rtx_LO_SUM (SImode,
-						   gen_rtx_REG (SImode, 1),
-						   GEN_INT (disp))));
-    }
-}
-
-/* Emit RTL to set REG to the value specified by BASE+DISP.
-   Handle case where DISP > 8k by using the add_high_const pattern.
-
-   Note in DISP > 8k case, we will leave the high part of the address
-   in %r1.  There is code in expand_hppa_{prologue,epilogue} that knows this.*/
-static void
-set_reg_plus_d(reg, base, disp)
-     int reg, base, disp;
-{
-  if (VAL_14_BITS_P (disp))
-    {
-      emit_move_insn (gen_rtx_REG (SImode, reg),
-		      gen_rtx_PLUS (SImode,
-				    gen_rtx_REG (SImode, base),
-				    GEN_INT (disp)));
-    }
-  else
-    {
-      emit_insn (gen_add_high_const (gen_rtx_REG (SImode, 1),
-				     gen_rtx_REG (SImode, base),
-				     GEN_INT (disp)));
-      emit_move_insn (gen_rtx_REG (SImode, reg),
-		      gen_rtx_LO_SUM (SImode,
-				      gen_rtx_REG (SImode, 1),
-				       GEN_INT (disp)));
-    }
-}
-
-/* Global variables set by FUNCTION_PROLOGUE.  */
-/* Size of frame.  Need to know this to emit return insns from
-   leaf procedures.  */
-static int actual_fsize;
-static int local_fsize, save_fregs;
-
-int
-compute_frame_size (size, fregs_live)
-     int size;
-     int *fregs_live;
-{
-  extern int current_function_outgoing_args_size;
-  int i, fsize;
-
-  /* 8 is space for frame pointer + filler. If any frame is allocated
-     we need to add this in because of STARTING_FRAME_OFFSET. */
-  fsize = size + (size || frame_pointer_needed ? 8 : 0);
-
-  /* We must leave enough space for all the callee saved registers
-     from 3 .. highest used callee save register since we don't
-     know if we're going to have an inline or out of line prologue
-     and epilogue.  */
-  for (i = 18; i >= 3; i--)
-    if (regs_ever_live[i])
-      {
-	fsize += 4 * (i - 2);
-	break;
-      }
-
-  /* Round the stack.  */
-  fsize = (fsize + 7) & ~7;
-
-  /* We must leave enough space for all the callee saved registers
-     from 3 .. highest used callee save register since we don't
-     know if we're going to have an inline or out of line prologue
-     and epilogue.  */
-  for (i = 66; i >= 48; i -= 2)
-    if (regs_ever_live[i] || regs_ever_live[i + 1])
-      {
-	if (fregs_live)
-	  *fregs_live = 1;
-
-	fsize += 4 * (i - 46);
-	break;
-      }
-
-  fsize += current_function_outgoing_args_size;
-  if (! leaf_function_p () || fsize)
-    fsize += 32;
-  return (fsize + 63) & ~63;
-}
-
-rtx hp_profile_label_rtx;
-static char hp_profile_label_name[8];
-void
-output_function_prologue (file, size)
-     FILE *file;
-     int size ATTRIBUTE_UNUSED;
-{
-  /* The function's label and associated .PROC must never be
-     separated and must be output *after* any profiling declarations
-     to avoid changing spaces/subspaces within a procedure.  */
-  ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
-  fputs ("\t.PROC\n", file);
-
-  /* hppa_expand_prologue does the dirty work now.  We just need
-     to output the assembler directives which denote the start
-     of a function.  */
-  fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
-  if (regs_ever_live[2] || profile_flag)
-    fputs (",CALLS,SAVE_RP", file);
-  else
-    fputs (",NO_CALLS", file);
-
-  if (frame_pointer_needed)
-    fputs (",SAVE_SP", file);
-
-  /* Pass on information about the number of callee register saves
-     performed in the prologue.
-
-     The compiler is supposed to pass the highest register number
-     saved, the assembler then has to adjust that number before
-     entering it into the unwind descriptor (to account for any
-     caller saved registers with lower register numbers than the
-     first callee saved register).  */
-  if (gr_saved)
-    fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
-
-  if (fr_saved)
-    fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
-
-  fputs ("\n\t.ENTRY\n", file);
-
-  /* Horrid hack.  emit_function_prologue will modify this RTL in
-     place to get the expected results.  */
-  if (profile_flag)
-    ASM_GENERATE_INTERNAL_LABEL (hp_profile_label_name, "LP",
-				 hp_profile_labelno);
-
-  /* If we're using GAS and not using the portable runtime model, then
-     we don't need to accumulate the total number of code bytes.  */
-  if (TARGET_GAS && ! TARGET_PORTABLE_RUNTIME)
-    total_code_bytes = 0;
-  else if (insn_addresses)
-    {
-      unsigned int old_total = total_code_bytes;
-
-      total_code_bytes += insn_addresses[INSN_UID (get_last_insn())];
-      total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
-
-      /* Be prepared to handle overflows.  */
-      total_code_bytes = old_total > total_code_bytes ? -1 : total_code_bytes;
-    }
-  else
-    total_code_bytes = -1;
-
-  remove_useless_addtr_insns (get_insns (), 0);
-
-  /* Restore INSN_CODEs for insn which use unscaled indexed addresses.  */
-  restore_unscaled_index_insn_codes (get_insns ());
-}
-
-void
-hppa_expand_prologue()
-{
-  extern char call_used_regs[];
-  int size = get_frame_size ();
-  int merge_sp_adjust_with_store = 0;
-  int i, offset;
-  rtx tmpreg, size_rtx;
-
-  gr_saved = 0;
-  fr_saved = 0;
-  save_fregs = 0;
-  local_fsize =  size + (size || frame_pointer_needed ? 8 : 0);
-  actual_fsize = compute_frame_size (size, &save_fregs);
-
-  /* Compute a few things we will use often.  */
-  tmpreg = gen_rtx_REG (SImode, 1);
-  size_rtx = GEN_INT (actual_fsize);
-
-  /* Handle out of line prologues and epilogues.  */
-  if (TARGET_SPACE)
-    {
-      rtx operands[2];
-      int saves = 0;
-      int outline_insn_count = 0;
-      int inline_insn_count = 0;
-
-      /* Count the number of insns for the inline and out of line
-	 variants so we can choose one appropriately.
-
-	 No need to screw with counting actual_fsize operations -- they're
-	 done for both inline and out of line prologues.  */
-      if (regs_ever_live[2])
-	inline_insn_count += 1;
-
-      if (! cint_ok_for_move (local_fsize))
-	outline_insn_count += 2;
-      else
-	outline_insn_count += 1;
-
-      /* Put the register save info into %r22.  */
-      for (i = 18; i >= 3; i--)
-	if (regs_ever_live[i] && ! call_used_regs[i])
-	  {
-	    /* -1 because the stack adjustment is normally done in
-	       the same insn as a register save.  */
-	    inline_insn_count += (i - 2) - 1;
-	    saves = i;
-            break;
-	  }
-  
-      for (i = 66; i >= 48; i -= 2)
-	if (regs_ever_live[i] || regs_ever_live[i + 1])
-	  {
-	    /* +1 needed as we load %r1 with the start of the freg
-	       save area.  */
-	    inline_insn_count += (i/2 - 23) + 1;
-	    saves |= ((i/2 - 12 ) << 16);
-	    break;
-	  }
-
-      if (frame_pointer_needed)
-	inline_insn_count += 3;
-
-      if (! cint_ok_for_move (saves))
-	outline_insn_count += 2;
-      else
-	outline_insn_count += 1;
-
-      if (TARGET_PORTABLE_RUNTIME)
-	outline_insn_count += 2;
-      else
-	outline_insn_count += 1;
-	
-      /* If there's a lot of insns in the prologue, then do it as
-	 an out-of-line sequence.  */
-      if (inline_insn_count > outline_insn_count)
-	{
-	  /* Put the local_fisze into %r19.  */
-	  operands[0] = gen_rtx_REG (SImode, 19);
-	  operands[1] = GEN_INT (local_fsize);
-	  emit_move_insn (operands[0], operands[1]);
-
-	  /* Put the stack size into %r21.  */
-	  operands[0] = gen_rtx_REG (SImode, 21);
-	  operands[1] = size_rtx;
-	  emit_move_insn (operands[0], operands[1]);
-
-	  operands[0] = gen_rtx_REG (SImode, 22);
-	  operands[1] = GEN_INT (saves);
-	  emit_move_insn (operands[0], operands[1]);
-
-	  /* Now call the out-of-line prologue.  */
-	  emit_insn (gen_outline_prologue_call ());
-	  emit_insn (gen_blockage ());
-
-	  /* Note that we're using an out-of-line prologue.  */
-	  out_of_line_prologue_epilogue = 1;
-	  return;     
-	}
-    }
-
-  out_of_line_prologue_epilogue = 0;
-
-  /* Save RP first.  The calling conventions manual states RP will
-     always be stored into the caller's frame at sp-20.  */
-  if (regs_ever_live[2] || profile_flag)
-    store_reg (2, -20, STACK_POINTER_REGNUM);
-
-  /* Allocate the local frame and set up the frame pointer if needed.  */
-  if (actual_fsize)
-  {
-    if (frame_pointer_needed)
-      {
-	/* Copy the old frame pointer temporarily into %r1.  Set up the
-	   new stack pointer, then store away the saved old frame pointer
-	   into the stack at sp+actual_fsize and at the same time update
-	   the stack pointer by actual_fsize bytes.  Two versions, first
-	   handles small (<8k) frames.  The second handles large (>8k)
-	   frames.  */
-	emit_move_insn (tmpreg, frame_pointer_rtx);
-	emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
-	if (VAL_14_BITS_P (actual_fsize))
-	  emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, size_rtx));
-	else
-	  {
-	    /* It is incorrect to store the saved frame pointer at *sp,
-	       then increment sp (writes beyond the current stack boundary).
-
-	       So instead use stwm to store at *sp and post-increment the
-	       stack pointer as an atomic operation.  Then increment sp to
-	       finish allocating the new frame.  */
-	    emit_insn (gen_post_stwm (stack_pointer_rtx, tmpreg, GEN_INT (64)));
-	    set_reg_plus_d (STACK_POINTER_REGNUM,
-			    STACK_POINTER_REGNUM,
-			    actual_fsize - 64);
-	  }
-      }
-    /* no frame pointer needed.  */
-    else
-      {
-	/* In some cases we can perform the first callee register save
-	   and allocating the stack frame at the same time.   If so, just
-	   make a note of it and defer allocating the frame until saving
-	   the callee registers.  */
-	if (VAL_14_BITS_P (-actual_fsize)
-	    && local_fsize == 0
-	    && ! profile_flag
-	    && ! flag_pic)
-	  merge_sp_adjust_with_store = 1;
-	/* Can not optimize.  Adjust the stack frame by actual_fsize bytes.  */
-	else if (actual_fsize != 0)
-	  set_reg_plus_d (STACK_POINTER_REGNUM,
-			  STACK_POINTER_REGNUM,
-			  actual_fsize);
-      }
-  }
-
-  /* The hppa calling conventions say that %r19, the pic offset
-     register, is saved at sp - 32 (in this function's frame)  when
-     generating PIC code.  FIXME:  What is the correct thing to do
-     for functions which make no calls and allocate no frame?  Do
-     we need to allocate a frame, or can we just omit the save?   For
-     now we'll just omit the save.  */
-  if (actual_fsize != 0 && flag_pic)
-    store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
-
-  /* Profiling code.
-
-     Instead of taking one argument, the counter label, as most normal
-     mcounts do, _mcount appears to behave differently on the HPPA.  It
-     takes the return address of the caller, the address of this routine,
-     and the address of the label.  Also, it isn't magic, so
-     argument registers have to be preserved.  */
-  if (profile_flag)
-    {
-      int pc_offset, i, arg_offset, basereg, offsetadj;
-
-      pc_offset = 4 + (frame_pointer_needed
-		       ? (VAL_14_BITS_P (actual_fsize) ? 12 : 20)
-		       : (VAL_14_BITS_P (actual_fsize) ? 4 : 8));
-
-      /* When the function has a frame pointer, use it as the base
-	 register for saving/restore registers.  Else use the stack
-	 pointer.  Adjust the offset according to the frame size if
-	 this function does not have a frame pointer.  */
-
-      basereg = frame_pointer_needed ? FRAME_POINTER_REGNUM
-				     : STACK_POINTER_REGNUM;
-      offsetadj = frame_pointer_needed ? 0 : actual_fsize;
-
-      /* Horrid hack.  emit_function_prologue will modify this RTL in
-	 place to get the expected results.   sprintf here is just to
-	 put something in the name.  */
-      sprintf(hp_profile_label_name, "LP$%04d", -1);
-      hp_profile_label_rtx = gen_rtx_SYMBOL_REF (SImode, hp_profile_label_name);
-      if (current_function_returns_struct)
-	store_reg (STRUCT_VALUE_REGNUM, - 12 - offsetadj, basereg);
-
-      for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
-	if (regs_ever_live [i])
-	  {
-	    store_reg (i, arg_offset, basereg);
-	    /* Deal with arg_offset not fitting in 14 bits.  */
-	    pc_offset += VAL_14_BITS_P (arg_offset) ? 4 : 8;
-	  }
-
-      emit_move_insn (gen_rtx_REG (SImode, 26), gen_rtx_REG (SImode, 2));
-      emit_move_insn (tmpreg, gen_rtx_HIGH (SImode, hp_profile_label_rtx));
-      emit_move_insn (gen_rtx_REG (SImode, 24),
-		      gen_rtx_LO_SUM (SImode, tmpreg, hp_profile_label_rtx));
-      /* %r25 is set from within the output pattern.  */
-      emit_insn (gen_call_profiler (GEN_INT (- pc_offset - 20)));
-
-      /* Restore argument registers.  */
-      for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
-	if (regs_ever_live [i])
-	  load_reg (i, arg_offset, basereg);
-
-      if (current_function_returns_struct)
-	load_reg (STRUCT_VALUE_REGNUM, -12 - offsetadj, basereg);
-
-    }
-
-  /* Normal register save.
-
-     Do not save the frame pointer in the frame_pointer_needed case.  It
-     was done earlier.  */
-  if (frame_pointer_needed)
-    {
-      for (i = 18, offset = local_fsize; i >= 4; i--)
-	if (regs_ever_live[i] && ! call_used_regs[i])
-	  {
-	    store_reg (i, offset, FRAME_POINTER_REGNUM);
-	    offset += 4;
-	    gr_saved++;
-	  }
-      /* Account for %r3 which is saved in a special place.  */
-      gr_saved++;
-    }
-  /* No frame pointer needed.  */
-  else
-    {
-      for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
-      	if (regs_ever_live[i] && ! call_used_regs[i])
-	  {
-	    /* If merge_sp_adjust_with_store is nonzero, then we can
-	       optimize the first GR save.  */
-	    if (merge_sp_adjust_with_store)
-	      {
-		merge_sp_adjust_with_store = 0;
-	        emit_insn (gen_post_stwm (stack_pointer_rtx,
-					  gen_rtx_REG (SImode, i),
-					  GEN_INT (-offset)));
-	      }
-	    else
-	      store_reg (i, offset, STACK_POINTER_REGNUM);
-	    offset += 4;
-	    gr_saved++;
-	  }
-
-      /* If we wanted to merge the SP adjustment with a GR save, but we never
-	 did any GR saves, then just emit the adjustment here.  */
-      if (merge_sp_adjust_with_store)
-	set_reg_plus_d (STACK_POINTER_REGNUM,
-			STACK_POINTER_REGNUM,
-			actual_fsize);
-    }
-
-  /* Align pointer properly (doubleword boundary).  */
-  offset = (offset + 7) & ~7;
-
-  /* Floating point register store.  */
-  if (save_fregs)
-    {
-      /* First get the frame or stack pointer to the start of the FP register
-	 save area.  */
-      if (frame_pointer_needed)
-	set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
-      else
-	set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
-
-      /* Now actually save the FP registers.  */
-      for (i = 66; i >= 48; i -= 2)
-	{
-	  if (regs_ever_live[i] || regs_ever_live[i + 1])
-	    {
-	      emit_move_insn (gen_rtx_MEM (DFmode,
-				           gen_rtx_POST_INC (DFmode, tmpreg)),
-			      gen_rtx_REG (DFmode, i));
-	      fr_saved++;
-	    }
-	}
-    }
-
-  /* When generating PIC code it is necessary to save/restore the
-     PIC register around each function call.  We used to do this
-     in the call patterns themselves, but that implementation
-     made incorrect assumptions about using global variables to hold
-     per-function rtl code generated in the backend.
-
-     So instead, we copy the PIC register into a reserved callee saved
-     register in the prologue.  Then after each call we reload the PIC
-     register from the callee saved register.  We also reload the PIC
-     register from the callee saved register in the epilogue ensure the
-     PIC register is valid at function exit.
-
-     This may (depending on the exact characteristics of the function)
-     even be more efficient. 
-
-     Avoid this if the callee saved register wasn't used (these are
-     leaf functions).  */
-  if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM_SAVED])
-    emit_move_insn (gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM_SAVED),
-		    gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM));
-}
-
-
-void
-output_function_epilogue (file, size)
-     FILE *file;
-     int size ATTRIBUTE_UNUSED;
-{
-  rtx insn = get_last_insn ();
-
-  /* hppa_expand_epilogue does the dirty work now.  We just need
-     to output the assembler directives which denote the end
-     of a function.
-
-     To make debuggers happy, emit a nop if the epilogue was completely
-     eliminated due to a volatile call as the last insn in the
-     current function.  That way the return address (in %r2) will
-     always point to a valid instruction in the current function.  */
-
-  /* Get the last real insn.  */
-  if (GET_CODE (insn) == NOTE)
-    insn = prev_real_insn (insn);
-
-  /* If it is a sequence, then look inside.  */
-  if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
-    insn = XVECEXP (PATTERN (insn), 0, 0);
-
-  /* If insn is a CALL_INSN, then it must be a call to a volatile
-     function (otherwise there would be epilogue insns).  */
-  if (insn && GET_CODE (insn) == CALL_INSN)
-    fputs ("\tnop\n", file);
-
-  fputs ("\t.EXIT\n\t.PROCEND\n", file);
-
-  /* Free up stuff we don't need anymore.  */
-  if (unscaled_index_insn_codes)
-    free (unscaled_index_insn_codes);
-  max_unscaled_index_insn_codes_uid = 0;
-}
-
-void
-hppa_expand_epilogue ()
-{
-  rtx tmpreg;
-  int offset,i;
-  int merge_sp_adjust_with_load  = 0;
-
-  /* Handle out of line prologues and epilogues.  */
-  if (TARGET_SPACE && out_of_line_prologue_epilogue)
-    {
-      int saves = 0;
-      rtx operands[2];
-
-      /* Put the register save info into %r22.  */
-      for (i = 18; i >= 3; i--)
-	if (regs_ever_live[i] && ! call_used_regs[i])
-	  {
-	    saves = i;
-            break;
-	  }
-	  
-      for (i = 66; i >= 48; i -= 2)
-	if (regs_ever_live[i] || regs_ever_live[i + 1])
-	  {
-	    saves |= ((i/2 - 12 ) << 16);
-	    break;
-	  }
-
-      emit_insn (gen_blockage ());
-
-      /* Put the local_fisze into %r19.  */
-      operands[0] = gen_rtx_REG (SImode, 19);
-      operands[1] = GEN_INT (local_fsize);
-      emit_move_insn (operands[0], operands[1]);
-
-      /* Put the stack size into %r21.  */
-      operands[0] = gen_rtx_REG (SImode, 21);
-      operands[1] = GEN_INT (actual_fsize);
-      emit_move_insn (operands[0], operands[1]);
-
-      operands[0] = gen_rtx_REG (SImode, 22);
-      operands[1] = GEN_INT (saves);
-      emit_move_insn (operands[0], operands[1]);
-
-      /* Now call the out-of-line epilogue.  */
-      emit_insn (gen_outline_epilogue_call ());
-      return;
-    }
-
-  /* We will use this often.  */
-  tmpreg = gen_rtx_REG (SImode, 1);
-
-  /* Try to restore RP early to avoid load/use interlocks when
-     RP gets used in the return (bv) instruction.  This appears to still
-     be necessary even when we schedule the prologue and epilogue. */
-  if (frame_pointer_needed
-      && (regs_ever_live [2] || profile_flag))
-    load_reg (2, -20, FRAME_POINTER_REGNUM);
-
-  /* No frame pointer, and stack is smaller than 8k.  */
-  else if (! frame_pointer_needed
-	   && VAL_14_BITS_P (actual_fsize + 20)
-	   && (regs_ever_live[2] || profile_flag))
-    load_reg (2, - (actual_fsize + 20), STACK_POINTER_REGNUM);
-
-  /* General register restores.  */
-  if (frame_pointer_needed)
-    {
-      for (i = 18, offset = local_fsize; i >= 4; i--)
-	if (regs_ever_live[i] && ! call_used_regs[i])
-	  {
-	    load_reg (i, offset, FRAME_POINTER_REGNUM);
-	    offset += 4;
-	  }
-    }
-  else
-    {
-      for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
-	{
-	  if (regs_ever_live[i] && ! call_used_regs[i])
-	    {
-	      /* Only for the first load.
-	         merge_sp_adjust_with_load holds the register load
-	         with which we will merge the sp adjustment.  */
-	      if (VAL_14_BITS_P (actual_fsize + 20)
-		  && local_fsize == 0
-		  && ! merge_sp_adjust_with_load)
-	        merge_sp_adjust_with_load = i;
-	      else
-	        load_reg (i, offset, STACK_POINTER_REGNUM);
-	      offset += 4;
-	    }
-	}
-    }
-
-  /* Align pointer properly (doubleword boundary).  */
-  offset = (offset + 7) & ~7;
-
-  /* FP register restores.  */
-  if (save_fregs)
-    {
-      /* Adjust the register to index off of.  */
-      if (frame_pointer_needed)
-	set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
-      else
-	set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
-
-      /* Actually do the restores now.  */
-      for (i = 66; i >= 48; i -= 2)
-	{
-	  if (regs_ever_live[i] || regs_ever_live[i + 1])
-	    {
-	      emit_move_insn (gen_rtx_REG (DFmode, i),
-			      gen_rtx_MEM (DFmode,
-				           gen_rtx_POST_INC (DFmode, tmpreg)));
-	    }
-	}
-    }
-
-  /* Emit a blockage insn here to keep these insns from being moved to
-     an earlier spot in the epilogue, or into the main instruction stream.
-
-     This is necessary as we must not cut the stack back before all the
-     restores are finished.  */
-  emit_insn (gen_blockage ());
-  /* No frame pointer, but we have a stack greater than 8k.  We restore
-     %r2 very late in this case.  (All other cases are restored as early
-     as possible.)  */
-  if (! frame_pointer_needed
-      && ! VAL_14_BITS_P (actual_fsize + 20)
-      && (regs_ever_live[2] || profile_flag))
-    {
-      set_reg_plus_d (STACK_POINTER_REGNUM,
-		      STACK_POINTER_REGNUM,
-		      - actual_fsize);
-
-      /* This used to try and be clever by not depending on the value in
-	 %r30 and instead use the value held in %r1 (so that the 2nd insn
-	 which sets %r30 could be put in the delay slot of the return insn).
-	
-	 That won't work since if the stack is exactly 8k set_reg_plus_d
-	 doesn't set %r1, just %r30.  */
-      load_reg (2, - 20, STACK_POINTER_REGNUM);
-    }
-
-  /* Reset stack pointer (and possibly frame pointer).  The stack 
-     pointer is initially set to fp + 64 to avoid a race condition.  */
-  else if (frame_pointer_needed)
-    {
-      set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64);
-      emit_insn (gen_pre_ldwm (frame_pointer_rtx, 
-			       stack_pointer_rtx,
-			       GEN_INT (-64)));
-    }
-  /* If we were deferring a callee register restore, do it now.  */
-  else if (! frame_pointer_needed  && merge_sp_adjust_with_load)
-    emit_insn (gen_pre_ldwm (gen_rtx_REG (SImode, merge_sp_adjust_with_load),
-			     stack_pointer_rtx,
-			     GEN_INT (- actual_fsize)));
-  else if (actual_fsize != 0)
-    set_reg_plus_d (STACK_POINTER_REGNUM,
-		    STACK_POINTER_REGNUM,
-		    - actual_fsize);
-}
-
-/* Fetch the return address for the frame COUNT steps up from
-   the current frame, after the prologue.  FRAMEADDR is the
-   frame pointer of the COUNT frame.
-
-   We want to ignore any export stub remnants here.
-
-   The value returned is used in two different ways:
-
-	1. To find a function's caller.
-
-	2. To change the return address for a function.
-
-   This function handles most instances of case 1; however, it will
-   fail if there are two levels of stubs to execute on the return
-   path.  The only way I believe that can happen is if the return value
-   needs a parameter relocation, which never happens for C code.
-
-   This function handles most instances of case 2; however, it will
-   fail if we did not originally have stub code on the return path
-   but will need code on the new return path.  This can happen if
-   the caller & callee are both in the main program, but the new
-   return location is in a shared library.
-
-   To handle this correctly we need to set the return pointer at
-   frame-20 to point to a return stub frame-24 to point to the
-   location we wish to return to.  */
-
-rtx
-return_addr_rtx (count, frameaddr)
-     int count ATTRIBUTE_UNUSED;
-     rtx frameaddr;
-{
-  rtx label;
-  rtx saved_rp;
-  rtx ins;
-
-  saved_rp = gen_reg_rtx (Pmode);
-
-  /* First, we start off with the normal return address pointer from
-     -20[frameaddr].  */
-
-  emit_move_insn (saved_rp, plus_constant (frameaddr, -5 * UNITS_PER_WORD));
-
-  /* Get pointer to the instruction stream.  We have to mask out the
-     privilege level from the two low order bits of the return address
-     pointer here so that ins will point to the start of the first
-     instruction that would have been executed if we returned.  */
-  ins = copy_to_reg (gen_rtx_AND (Pmode,
-				  copy_to_reg (gen_rtx_MEM (Pmode, saved_rp)),
-				  MASK_RETURN_ADDR));
-  label = gen_label_rtx ();
-
-  /* Check the instruction stream at the normal return address for the
-     export stub:
-
-	0x4bc23fd1 | stub+8:   ldw -18(sr0,sp),rp
-	0x004010a1 | stub+12:  ldsid (sr0,rp),r1
-	0x00011820 | stub+16:  mtsp r1,sr0
-	0xe0400002 | stub+20:  be,n 0(sr0,rp)
-
-     If it is an export stub, than our return address is really in
-     -24[frameaddr].  */
-
-  emit_cmp_insn (gen_rtx_MEM (SImode, ins),
-		 GEN_INT (0x4bc23fd1),
-		 NE, NULL_RTX, SImode, 1, 0);
-  emit_jump_insn (gen_bne (label));
-
-  emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
-		 GEN_INT (0x004010a1),
-		 NE, NULL_RTX, SImode, 1, 0);
-  emit_jump_insn (gen_bne (label));
-
-  emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
-		 GEN_INT (0x00011820),
-		 NE, NULL_RTX, SImode, 1, 0);
-  emit_jump_insn (gen_bne (label));
-
-  emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
-		 GEN_INT (0xe0400002),
-		 NE, NULL_RTX, SImode, 1, 0);
-
-  /* If there is no export stub then just use our initial guess of
-     -20[frameaddr].  */
-
-  emit_jump_insn (gen_bne (label));
-
-  /* Here we know that our return address pointer points to an export
-     stub.  We don't want to return the address of the export stub,
-     but rather the return address that leads back into user code.
-     That return address is stored at -24[frameaddr].  */
-
-  emit_move_insn (saved_rp, plus_constant (frameaddr, -6 * UNITS_PER_WORD));
-
-  emit_label (label);
-  return gen_rtx_MEM (Pmode, memory_address (Pmode, saved_rp));
-}
-
-/* This is only valid once reload has completed because it depends on
-   knowing exactly how much (if any) frame there is and...
-
-   It's only valid if there is no frame marker to de-allocate and...
-
-   It's only valid if %r2 hasn't been saved into the caller's frame
-   (we're not profiling and %r2 isn't live anywhere).  */
-int
-hppa_can_use_return_insn_p ()
-{
-  return (reload_completed
-	  && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
-	  && ! profile_flag
-	  && ! regs_ever_live[2]
-	  && ! frame_pointer_needed);
-}
-
-void
-emit_bcond_fp (code, operand0)
-     enum rtx_code code;
-     rtx operand0;
-{
-  emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
-			       gen_rtx_IF_THEN_ELSE (VOIDmode,
-						     gen_rtx_fmt_ee (code,
-							      VOIDmode,
-							      gen_rtx_REG (CCFPmode, 0),
-							      const0_rtx),
-						     gen_rtx_LABEL_REF (VOIDmode, operand0),
-						     pc_rtx)));
-
-}
-
-rtx
-gen_cmp_fp (code, operand0, operand1)
-     enum rtx_code code;
-     rtx operand0, operand1;
-{
-  return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
-		      gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
-}
-
-/* Adjust the cost of a scheduling dependency.  Return the new cost of
-   a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
-
-int
-pa_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
-{
-  enum attr_type attr_type;
-
-  if (! recog_memoized (insn))
-    return 0;
-
-  /* CYGNUS LOCAL PA8000/law */
-  /* No cost adjustments are needed for the PA8000 */
-  if (pa_cpu == PROCESSOR_8000)
-    return 0;
-  /* END CYGNUS LOCAL */
-
-  attr_type = get_attr_type (insn);
-
-  if (REG_NOTE_KIND (link) == 0)
-    {
-      /* Data dependency; DEP_INSN writes a register that INSN reads some
-	 cycles later.  */
-
-      if (attr_type == TYPE_FPSTORE)
-	{
-	  rtx pat = PATTERN (insn);
-	  rtx dep_pat = PATTERN (dep_insn);
-	  if (GET_CODE (pat) == PARALLEL)
-	    {
-	      /* This happens for the fstXs,mb patterns.  */
-	      pat = XVECEXP (pat, 0, 0);
-	    }
-	  if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
-	    /* If this happens, we have to extend this to schedule
-	       optimally.  Return 0 for now.  */
-	  return 0;
-
-	  if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
-	    {
-	      if (! recog_memoized (dep_insn))
-		return 0;
-	      /* DEP_INSN is writing its result to the register
-		 being stored in the fpstore INSN.  */
-	      switch (get_attr_type (dep_insn))
-		{
-		case TYPE_FPLOAD:
-		  /* This cost 3 cycles, not 2 as the md says for the
-		     700 and 7100.  */
-		  return cost + 1;
-
-		case TYPE_FPALU:
-		case TYPE_FPMULSGL:
-		case TYPE_FPMULDBL:
-		case TYPE_FPDIVSGL:
-		case TYPE_FPDIVDBL:
-		case TYPE_FPSQRTSGL:
-		case TYPE_FPSQRTDBL:
-		  /* In these important cases, we save one cycle compared to
-		     when flop instruction feed each other.  */
-		  return cost - 1;
-
-		default:
-		  return cost;
-		}
-	    }
-	}
-
-      /* For other data dependencies, the default cost specified in the
-	 md is correct.  */
-      return cost;
-    }
-  else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
-    {
-      /* Anti dependency; DEP_INSN reads a register that INSN writes some
-	 cycles later.  */
-
-      if (attr_type == TYPE_FPLOAD)
-	{
-	  rtx pat = PATTERN (insn);
-	  rtx dep_pat = PATTERN (dep_insn);
-	  if (GET_CODE (pat) == PARALLEL)
-	    {
-	      /* This happens for the fldXs,mb patterns.  */
-	      pat = XVECEXP (pat, 0, 0);
-	    }
-	  if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
-	    /* If this happens, we have to extend this to schedule
-	       optimally.  Return 0 for now.  */
-	  return 0;
-
-	  if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
-	    {
-	      if (! recog_memoized (dep_insn))
-		return 0;
-	      switch (get_attr_type (dep_insn))
-		{
-		case TYPE_FPALU:
-		case TYPE_FPMULSGL:
-		case TYPE_FPMULDBL:
-		case TYPE_FPDIVSGL:
-		case TYPE_FPDIVDBL:
-		case TYPE_FPSQRTSGL:
-		case TYPE_FPSQRTDBL:
-		  /* A fpload can't be issued until one cycle before a
-		     preceding arithmetic operation has finished if
-		     the target of the fpload is any of the sources
-		     (or destination) of the arithmetic operation.  */
-		  return cost - 1;
-
-		default:
-		  return 0;
-		}
-	    }
-	}
-      else if (attr_type == TYPE_FPALU)
-	{
-	  rtx pat = PATTERN (insn);
-	  rtx dep_pat = PATTERN (dep_insn);
-	  if (GET_CODE (pat) == PARALLEL)
-	    {
-	      /* This happens for the fldXs,mb patterns.  */
-	      pat = XVECEXP (pat, 0, 0);
-	    }
-	  if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
-	    /* If this happens, we have to extend this to schedule
-	       optimally.  Return 0 for now.  */
-	  return 0;
-
-	  if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
-	    {
-	      if (! recog_memoized (dep_insn))
-		return 0;
-	      switch (get_attr_type (dep_insn))
-		{
-		case TYPE_FPDIVSGL:
-		case TYPE_FPDIVDBL:
-		case TYPE_FPSQRTSGL:
-		case TYPE_FPSQRTDBL:
-		  /* An ALU flop can't be issued until two cycles before a
-		     preceding divide or sqrt operation has finished if
-		     the target of the ALU flop is any of the sources
-		     (or destination) of the divide or sqrt operation.  */
-		  return cost - 2;
-
-		default:
-		  return 0;
-		}
-	    }
-	}
-
-      /* For other anti dependencies, the cost is 0.  */
-      return 0;
-    }
-  else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
-    {
-      /* Output dependency; DEP_INSN writes a register that INSN writes some
-	 cycles later.  */
-      if (attr_type == TYPE_FPLOAD)
-	{
-	  rtx pat = PATTERN (insn);
-	  rtx dep_pat = PATTERN (dep_insn);
-	  if (GET_CODE (pat) == PARALLEL)
-	    {
-	      /* This happens for the fldXs,mb patterns.  */
-	      pat = XVECEXP (pat, 0, 0);
-	    }
-	  if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
-	    /* If this happens, we have to extend this to schedule
-	       optimally.  Return 0 for now.  */
-	  return 0;
-
-	  if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
-	    {
-	      if (! recog_memoized (dep_insn))
-		return 0;
-	      switch (get_attr_type (dep_insn))
-		{
-		case TYPE_FPALU:
-		case TYPE_FPMULSGL:
-		case TYPE_FPMULDBL:
-		case TYPE_FPDIVSGL:
-		case TYPE_FPDIVDBL:
-		case TYPE_FPSQRTSGL:
-		case TYPE_FPSQRTDBL:
-		  /* A fpload can't be issued until one cycle before a
-		     preceding arithmetic operation has finished if
-		     the target of the fpload is the destination of the
-		     arithmetic operation.  */
-		  return cost - 1;
-
-		default:
-		  return 0;
-		}
-	    }
-	}
-      else if (attr_type == TYPE_FPALU)
-	{
-	  rtx pat = PATTERN (insn);
-	  rtx dep_pat = PATTERN (dep_insn);
-	  if (GET_CODE (pat) == PARALLEL)
-	    {
-	      /* This happens for the fldXs,mb patterns.  */
-	      pat = XVECEXP (pat, 0, 0);
-	    }
-	  if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
-	    /* If this happens, we have to extend this to schedule
-	       optimally.  Return 0 for now.  */
-	  return 0;
-
-	  if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
-	    {
-	      if (! recog_memoized (dep_insn))
-		return 0;
-	      switch (get_attr_type (dep_insn))
-		{
-		case TYPE_FPDIVSGL:
-		case TYPE_FPDIVDBL:
-		case TYPE_FPSQRTSGL:
-		case TYPE_FPSQRTDBL:
-		  /* An ALU flop can't be issued until two cycles before a
-		     preceding divide or sqrt operation has finished if
-		     the target of the ALU flop is also the target of
-		     the divide or sqrt operation.  */
-		  return cost - 2;
-
-		default:
-		  return 0;
-		}
-	    }
-	}
-
-      /* For other output dependencies, the cost is 0.  */
-      return 0;
-    }
-  else
-    abort ();
-}
-
-/* Return any length adjustment needed by INSN which already has its length
-   computed as LENGTH.   Return zero if no adjustment is necessary.
-
-   For the PA: function calls, millicode calls, and backwards short
-   conditional branches with unfilled delay slots need an adjustment by +1
-   (to account for the NOP which will be inserted into the instruction stream).
-
-   Also compute the length of an inline block move here as it is too
-   complicated to express as a length attribute in pa.md.  */
-int
-pa_adjust_insn_length (insn, length)
-    rtx insn;
-    int length;
-{
-  rtx pat = PATTERN (insn);
-
-  /* Call insns which are *not* indirect and have unfilled delay slots.  */
-  if (GET_CODE (insn) == CALL_INSN)
-    {
-
-      if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
-	  && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
-	return 4;
-      else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
-	       && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
-		  == SYMBOL_REF)
-	return 4;
-      else
-	return 0;
-    }
-  /* Jumps inside switch tables which have unfilled delay slots 
-     also need adjustment.  */
-  else if (GET_CODE (insn) == JUMP_INSN
-	   && simplejump_p (insn)
-	   && GET_MODE (insn) == SImode)
-    return 4;
-  /* Millicode insn with an unfilled delay slot.  */
-  else if (GET_CODE (insn) == INSN
-	   && GET_CODE (pat) != SEQUENCE
-	   && GET_CODE (pat) != USE
-	   && GET_CODE (pat) != CLOBBER
-	   && get_attr_type (insn) == TYPE_MILLI)
-    return 4;
-  /* Block move pattern.  */
-  else if (GET_CODE (insn) == INSN
-	   && GET_CODE (pat) == PARALLEL
-	   && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
-	   && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
-	   && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
-	   && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
-    return compute_movstrsi_length (insn) - 4;
-  /* Conditional branch with an unfilled delay slot.  */
-  else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
-    {
-      /* Adjust a short backwards conditional with an unfilled delay slot.  */
-      if (GET_CODE (pat) == SET
-	  && length == 4
-	  && ! forward_branch_p (insn))
-	return 4;
-      else if (GET_CODE (pat) == PARALLEL
-	       && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
-	       && length == 4)
-	return 4;
-      /* Adjust dbra insn with short backwards conditional branch with
-	 unfilled delay slot -- only for case where counter is in a
-	 general register register. */
-      else if (GET_CODE (pat) == PARALLEL
-	       && GET_CODE (XVECEXP (pat, 0, 1)) == SET
-	       && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
- 	       && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
-	       && length == 4
-	       && ! forward_branch_p (insn))
-	return 4;
-      else
-	return 0;
-    }
-  return 0;
-}
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
-{
-  switch (code)
-    {
-    case '#':
-      /* Output a 'nop' if there's nothing for the delay slot.  */
-      if (dbr_sequence_length () == 0)
-	fputs ("\n\tnop", file);
-      return;
-    case '*':
-      /* Output an nullification completer if there's nothing for the */
-      /* delay slot or nullification is requested.  */
-      if (dbr_sequence_length () == 0 ||
-	  (final_sequence &&
-	   INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
-        fputs (",n", file);
-      return;
-    case 'R':
-      /* Print out the second register name of a register pair.
-	 I.e., R (6) => 7.  */
-      fputs (reg_names[REGNO (x)+1], file);
-      return;
-    case 'r':
-      /* A register or zero. */
-      if (x == const0_rtx
-	  || (x == CONST0_RTX (DFmode))
-	  || (x == CONST0_RTX (SFmode)))
-	{
-	  fputs ("0", file);
-	  return;
-	}
-      else
-	break;
-    case 'C':			/* Plain (C)ondition */
-    case 'X':
-      switch (GET_CODE (x))
-	{
-	case EQ:
-	  fputs ("=", file);  break;
-	case NE:
-	  fputs ("<>", file);  break;
-	case GT:
-	  fputs (">", file);  break;
-	case GE:
-	  fputs (">=", file);  break;
-	case GEU:
-	  fputs (">>=", file);  break;
-	case GTU:
-	  fputs (">>", file);  break;
-	case LT:
-	  fputs ("<", file);  break;
-	case LE:
-	  fputs ("<=", file);  break;
-	case LEU:
-	  fputs ("<<=", file);  break;
-	case LTU:
-	  fputs ("<<", file);  break;
-	default:
-	  abort ();
-	}
-      return;
-    case 'N':			/* Condition, (N)egated */
-      switch (GET_CODE (x))
-	{
-	case EQ:
-	  fputs ("<>", file);  break;
-	case NE:
-	  fputs ("=", file);  break;
-	case GT:
-	  fputs ("<=", file);  break;
-	case GE:
-	  fputs ("<", file);  break;
-	case GEU:
-	  fputs ("<<", file);  break;
-	case GTU:
-	  fputs ("<<=", file);  break;
-	case LT:
-	  fputs (">=", file);  break;
-	case LE:
-	  fputs (">", file);  break;
-	case LEU:
-	  fputs (">>", file);  break;
-	case LTU:
-	  fputs (">>=", file);  break;
-	default:
-	  abort ();
-	}
-      return;
-    /* For floating point comparisons.  Need special conditions to deal
-       with NaNs properly.  */
-    case 'Y':
-      switch (GET_CODE (x))
-	{
-	case EQ:
-	  fputs ("!=", file);  break;
-	case NE:
-	  fputs ("=", file);  break;
-	case GT:
-	  fputs ("<=", file);  break;
-	case GE:
-	  fputs ("<", file);  break;
-	case LT:
-	  fputs (">=", file);  break;
-	case LE:
-	  fputs (">", file);  break;
-	default:
-	  abort ();
-	}
-      return;
-    case 'S':			/* Condition, operands are (S)wapped.  */
-      switch (GET_CODE (x))
-	{
-	case EQ:
-	  fputs ("=", file);  break;
-	case NE:
-	  fputs ("<>", file);  break;
-	case GT:
-	  fputs ("<", file);  break;
-	case GE:
-	  fputs ("<=", file);  break;
-	case GEU:
-	  fputs ("<<=", file);  break;
-	case GTU:
-	  fputs ("<<", file);  break;
-	case LT:
-	  fputs (">", file);  break;
-	case LE:
-	  fputs (">=", file);  break;
-	case LEU:
-	  fputs (">>=", file);  break;
-	case LTU:
-	  fputs (">>", file);  break;
-	default:
-	  abort ();
-	}
-      return;
-    case 'B':			/* Condition, (B)oth swapped and negate.  */
-      switch (GET_CODE (x))
-	{
-	case EQ:
-	  fputs ("<>", file);  break;
-	case NE:
-	  fputs ("=", file);  break;
-	case GT:
-	  fputs (">=", file);  break;
-	case GE:
-	  fputs (">", file);  break;
-	case GEU:
-	  fputs (">>", file);  break;
-	case GTU:
-	  fputs (">>=", file);  break;
-	case LT:
-	  fputs ("<=", file);  break;
-	case LE:
-	  fputs ("<", file);  break;
-	case LEU:
-	  fputs ("<<", file);  break;
-	case LTU:
-	  fputs ("<<=", file);  break;
-	default:
-	  abort ();
-	}
-      return;
-    case 'k':
-      if (GET_CODE (x) == CONST_INT)
-	{
-	  fprintf (file, "%d", ~INTVAL (x));
-	  return;
-	}
-      abort();
-    case 'L':
-      if (GET_CODE (x) == CONST_INT)
-	{
-	  fprintf (file, "%d", 32 - (INTVAL (x) & 31));
-	  return;
-	}
-      abort();
-    case 'O':
-      if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
-	{
-	  fprintf (file, "%d", exact_log2 (INTVAL (x)));
-	  return;
-	}
-      abort();
-    case 'P':
-      if (GET_CODE (x) == CONST_INT)
-	{
-	  fprintf (file, "%d", 31 - (INTVAL (x) & 31));
-	  return;
-	}
-      abort();
-    case 'I':
-      if (GET_CODE (x) == CONST_INT)
-	fputs ("i", file);
-      return;
-    case 'M':
-    case 'F':
-      switch (GET_CODE (XEXP (x, 0)))
-	{
-	case PRE_DEC:
-	case PRE_INC:
-	  fputs ("s,mb", file);
-	  break;
-	case POST_DEC:
-	case POST_INC:
-	  fputs ("s,ma", file);
-	  break;
-	case PLUS:
-	  if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
-	      || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
-	    fputs ("x,s", file);
-	  else if (code == 'F')
-	    fputs ("s", file);
-	  break;
-	default:
-	  if (code == 'F')
-	    fputs ("s", file);
-	  break;
-	}
-      return;
-    case 'G':
-      output_global_address (file, x, 0);
-      return;
-    case 'H':
-      output_global_address (file, x, 1);
-      return;
-    case 0:			/* Don't do anything special */
-      break;
-    case 'Z':
-      {
-	unsigned op[3];
-	compute_zdepi_operands (INTVAL (x), op);
-	fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
-	return;
-      }
-    default:
-      abort ();
-    }
-  if (GET_CODE (x) == REG)
-    {
-      fputs (reg_names [REGNO (x)], file);
-      if (FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4 && (REGNO (x) & 1) == 0)
-	fputs ("L", file);
-    }
-  else if (GET_CODE (x) == MEM)
-    {
-      int size = GET_MODE_SIZE (GET_MODE (x));
-      rtx base = XEXP (XEXP (x, 0), 0);
-      switch (GET_CODE (XEXP (x, 0)))
-	{
-	case PRE_DEC:
-	case POST_DEC:
-	  fprintf (file, "-%d(0,%s)", size, reg_names [REGNO (base)]);
-	  break;
-	case PRE_INC:
-	case POST_INC:
-	  fprintf (file, "%d(0,%s)", size, reg_names [REGNO (base)]);
-	  break;
-	default:
-	  if (GET_CODE (XEXP (x, 0)) == PLUS
-	      && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
-	    fprintf (file, "%s(0,%s)",
-		     reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
-		     reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
-	  else if (GET_CODE (XEXP (x, 0)) == PLUS
-		   && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
-	    fprintf (file, "%s(0,%s)",
-		     reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
-		     reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
-	  else
-	    output_address (XEXP (x, 0));
-	  break;
-	}
-    }
-  else
-    output_addr_const (file, x);
-}
-
-/* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
-
-void
-output_global_address (file, x, round_constant)
-     FILE *file;
-     rtx x;
-     int round_constant;
-{
-
-  /* Imagine  (high (const (plus ...))).  */
-  if (GET_CODE (x) == HIGH)
-    x = XEXP (x, 0);
-
-  if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x))
-    assemble_name (file, XSTR (x, 0));
-  else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
-    {
-      assemble_name (file, XSTR (x, 0));
-      fputs ("-$global$", file);
-    }
-  else if (GET_CODE (x) == CONST)
-    {
-      char *sep = "";
-      int offset = 0;		/* assembler wants -$global$ at end */
-      rtx base = NULL_RTX;
-
-      if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
-	{
-	  base = XEXP (XEXP (x, 0), 0);
-	  output_addr_const (file, base);
-	}
-      else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
-	offset = INTVAL (XEXP (XEXP (x, 0), 0));
-      else abort ();
-
-      if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
-	{
-	  base = XEXP (XEXP (x, 0), 1);
-	  output_addr_const (file, base);
-	}
-      else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
-	offset = INTVAL (XEXP (XEXP (x, 0),1));
-      else abort ();
-
-      /* How bogus.  The compiler is apparently responsible for
-	 rounding the constant if it uses an LR field selector.
-
-	 The linker and/or assembler seem a better place since
-	 they have to do this kind of thing already.
-
-	 If we fail to do this, HP's optimizing linker may eliminate
-	 an addil, but not update the ldw/stw/ldo instruction that
-	 uses the result of the addil.  */
-      if (round_constant)
-	offset = ((offset + 0x1000) & ~0x1fff);
-
-      if (GET_CODE (XEXP (x, 0)) == PLUS)
-	{
-	  if (offset < 0)
-	    {
-	      offset = -offset;
-	      sep = "-";
-	    }
-	  else
-	    sep = "+";
-	}
-      else if (GET_CODE (XEXP (x, 0)) == MINUS
-	       && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
-	sep = "-";
-      else abort ();
-
-      if (!read_only_operand (base) && !flag_pic)
-	fputs ("-$global$", file);
-      if (offset)
-	fprintf (file,"%s%d", sep, offset);
-    }
-  else
-    output_addr_const (file, x);
-}
-
-void
-output_deferred_plabels (file)
-     FILE *file;
-{
-  int i;
-  /* If we have deferred plabels, then we need to switch into the data
-     section and align it to a 4 byte boundary before we output the
-     deferred plabels.  */
-  if (n_deferred_plabels)
-    {
-      data_section ();
-      ASM_OUTPUT_ALIGN (file, 2);
-    }
-
-  /* Now output the deferred plabels.  */
-  for (i = 0; i < n_deferred_plabels; i++)
-    {
-      ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
-      assemble_integer (gen_rtx_SYMBOL_REF (VOIDmode,
-					    deferred_plabels[i].name), 4, 1);
-    }
-}
-
-/* HP's millicode routines mean something special to the assembler.
-   Keep track of which ones we have used.  */
-
-enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
-static char imported[(int)end1000];
-static char *milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
-static char import_string[] = ".IMPORT $$....,MILLICODE";
-#define MILLI_START 10
-
-static void
-import_milli (code)
-     enum millicodes code;
-{
-  char str[sizeof (import_string)];
-
-  if (!imported[(int)code])
-    {
-      imported[(int)code] = 1;
-      strcpy (str, import_string);
-      strncpy (str + MILLI_START, milli_names[(int)code], 4);
-      output_asm_insn (str, 0);
-    }
-}
-
-/* The register constraints have put the operands and return value in
-   the proper registers. */
-
-char *
-output_mul_insn (unsignedp, insn)
-     int unsignedp ATTRIBUTE_UNUSED;
-     rtx insn;
-{
-  import_milli (mulI);
-  return output_millicode_call (insn, gen_rtx_SYMBOL_REF (SImode, "$$mulI"));
-}
-
-/* Emit the rtl for doing a division by a constant. */
-
-/* Do magic division millicodes exist for this value? */
-static int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
-			     1, 1};
-
-/* We'll use an array to keep track of the magic millicodes and
-   whether or not we've used them already. [n][0] is signed, [n][1] is
-   unsigned. */
-
-static int div_milli[16][2];
-
-int
-div_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (mode == SImode
-	  && ((GET_CODE (op) == REG && REGNO (op) == 25)
-	      || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
-		  && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
-}
-
-int
-emit_hpdiv_const (operands, unsignedp)
-     rtx *operands;
-     int unsignedp;
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) > 0
-      && INTVAL (operands[2]) < 16
-      && magic_milli[INTVAL (operands[2])])
-    {
-      emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
-      emit
-	(gen_rtx
-	 (PARALLEL, VOIDmode,
-	  gen_rtvec (5, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
-				     gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
-						     SImode,
-						     gen_rtx_REG (SImode, 26),
-						     operands[2])),
-		     gen_rtx_CLOBBER (VOIDmode, operands[3]),
-		     gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
-		     gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
-		     gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 31)))));
-      emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
-      return 1;
-    }
-  return 0;
-}
-
-char *
-output_div_insn (operands, unsignedp, insn)
-     rtx *operands;
-     int unsignedp;
-     rtx insn;
-{
-  int divisor;
-
-  /* If the divisor is a constant, try to use one of the special
-     opcodes .*/
-  if (GET_CODE (operands[0]) == CONST_INT)
-    {
-      static char buf[100];
-      divisor = INTVAL (operands[0]);
-      if (!div_milli[divisor][unsignedp])
-	{
-	  div_milli[divisor][unsignedp] = 1;
-	  if (unsignedp)
-	    output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
-	  else
-	    output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
-	}
-      if (unsignedp)
-	{
-	  sprintf (buf, "$$divU_%d", INTVAL (operands[0]));
-	  return output_millicode_call (insn,
-					gen_rtx_SYMBOL_REF (SImode, buf));
-	}
-      else
-	{
-	  sprintf (buf, "$$divI_%d", INTVAL (operands[0]));
-	  return output_millicode_call (insn,
-					gen_rtx_SYMBOL_REF (SImode, buf));
-	}
-    }
-  /* Divisor isn't a special constant. */
-  else
-    {
-      if (unsignedp)
-	{
-	  import_milli (divU);
-	  return output_millicode_call (insn,
-					gen_rtx_SYMBOL_REF (SImode, "$$divU"));
-	}
-      else
-	{
-	  import_milli (divI);
-	  return output_millicode_call (insn,
-					gen_rtx_SYMBOL_REF (SImode, "$$divI"));
-	}
-    }
-}
-
-/* Output a $$rem millicode to do mod. */
-
-char *
-output_mod_insn (unsignedp, insn)
-     int unsignedp;
-     rtx insn;
-{
-  if (unsignedp)
-    {
-      import_milli (remU);
-      return output_millicode_call (insn,
-				    gen_rtx_SYMBOL_REF (SImode, "$$remU"));
-    }
-  else
-    {
-      import_milli (remI);
-      return output_millicode_call (insn,
-				    gen_rtx_SYMBOL_REF (SImode, "$$remI"));
-    }
-}
-
-void
-output_arg_descriptor (call_insn)
-     rtx call_insn;
-{
-  char *arg_regs[4];
-  enum machine_mode arg_mode;
-  rtx link;
-  int i, output_flag = 0;
-  int regno;
-
-  for (i = 0; i < 4; i++)
-    arg_regs[i] = 0;
-
-  /* Specify explicitly that no argument relocations should take place
-     if using the portable runtime calling conventions.  */
-  if (TARGET_PORTABLE_RUNTIME)
-    {
-      fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
-	     asm_out_file);
-      return;
-    }
-
-  if (GET_CODE (call_insn) != CALL_INSN)
-    abort ();
-  for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
-    {
-      rtx use = XEXP (link, 0);
-
-      if (! (GET_CODE (use) == USE
-	     && GET_CODE (XEXP (use, 0)) == REG
-	     && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
-	continue;
-
-      arg_mode = GET_MODE (XEXP (use, 0));
-      regno = REGNO (XEXP (use, 0));
-      if (regno >= 23 && regno <= 26)
-	{
-	  arg_regs[26 - regno] = "GR";
-	  if (arg_mode == DImode)
-	    arg_regs[25 - regno] = "GR";
-	}
-      else if (regno >= 32 && regno <= 39)
-	{
-	  if (arg_mode == SFmode)
-	    arg_regs[(regno - 32) / 2] = "FR";
-	  else
-	    {
-#ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
-	      arg_regs[(regno - 34) / 2] = "FR";
-	      arg_regs[(regno - 34) / 2 + 1] = "FU";
-#else
-	      arg_regs[(regno - 34) / 2] = "FU";
-	      arg_regs[(regno - 34) / 2 + 1] = "FR";
-#endif
-	    }
-	}
-    }
-  fputs ("\t.CALL ", asm_out_file);
-  for (i = 0; i < 4; i++)
-    {
-      if (arg_regs[i])
-	{
-	  if (output_flag++)
-	    fputc (',', asm_out_file);
-	  fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
-	}
-    }
-  fputc ('\n', asm_out_file);
-}
-
-/* Return the class of any secondary reload register that is needed to
-   move IN into a register in class CLASS using mode MODE.
-
-   Profiling has showed this routine and its descendants account for
-   a significant amount of compile time (~7%).  So it has been
-   optimized to reduce redundant computations and eliminate useless
-   function calls.
-
-   It might be worthwhile to try and make this a leaf function too.  */
-
-enum reg_class
-secondary_reload_class (class, mode, in)
-     enum reg_class class;
-     enum machine_mode mode;
-     rtx in;
-{
-  int regno, is_symbolic;
-
-  /* Trying to load a constant into a FP register during PIC code
-     generation will require %r1 as a scratch register.  */
-  if (flag_pic == 2
-      && GET_MODE_CLASS (mode) == MODE_INT
-      && FP_REG_CLASS_P (class)
-      && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
-    return R1_REGS;
-
-  /* Profiling showed the PA port spends about 1.3% of its compilation
-     time in true_regnum from calls inside secondary_reload_class.  */
-
-  if (GET_CODE (in) == REG)
-    {
-      regno = REGNO (in);
-      if (regno >= FIRST_PSEUDO_REGISTER)
-	regno = true_regnum (in);
-    }
-  else if (GET_CODE (in) == SUBREG)
-    regno = true_regnum (in);
-  else
-    regno = -1;
-
-  /* If we have something like (mem (mem (...)), we can safely assume the
-     inner MEM will end up in a general register after reloading, so there's
-     no need for a secondary reload.  */
-  if (GET_CODE (in) == MEM
-      && GET_CODE (XEXP (in, 0)) == MEM)
-    return NO_REGS;
-
-  /* Handle out of range displacement for integer mode loads/stores of
-     FP registers.  */
-  if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
-       && GET_MODE_CLASS (mode) == MODE_INT
-       && FP_REG_CLASS_P (class))
-      || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
-    return GENERAL_REGS;
-
-  if (GET_CODE (in) == HIGH)
-    in = XEXP (in, 0);
-
-  /* Profiling has showed GCC spends about 2.6% of its compilation
-     time in symbolic_operand from calls inside secondary_reload_class.
-
-     We use an inline copy and only compute its return value once to avoid
-     useless work.  */
-  switch (GET_CODE (in))
-    {
-      rtx tmp;
-
-      case SYMBOL_REF:
-      case LABEL_REF:
-        is_symbolic = 1;
-        break;
-      case CONST:
-	tmp = XEXP (in, 0);
-	is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
-			|| GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
-		       && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
-        break;
-
-      default:
-        is_symbolic = 0;
-        break;
-    }
-  
-  if (!flag_pic
-      && is_symbolic
-      && read_only_operand (in))
-    return NO_REGS;
-
-  if (class != R1_REGS && is_symbolic)
-    return R1_REGS;
-
-  return NO_REGS;
-}
-
-enum direction
-function_arg_padding (mode, type)
-     enum machine_mode mode;
-     tree type;
-{
-  int size;
-
-  if (mode == BLKmode)
-    {
-      if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
-	size = int_size_in_bytes (type) * BITS_PER_UNIT;
-      else
-	return upward;		/* Don't know if this is right, but */
-				/* same as old definition. */
-    }
-  else
-    size = GET_MODE_BITSIZE (mode);
-  if (size < PARM_BOUNDARY)
-    return downward;
-  else if (size % PARM_BOUNDARY)
-    return upward;
-  else
-    return none;
-}
-
-
-/* Do what is necessary for `va_start'.  The argument is ignored;
-   We look at the current function to determine if stdargs or varargs
-   is used and fill in an initial va_list.  A pointer to this constructor
-   is returned.  */
-
-struct rtx_def *
-hppa_builtin_saveregs (arglist)
-     tree arglist ATTRIBUTE_UNUSED;
-{
-  rtx offset, dest;
-  tree fntype = TREE_TYPE (current_function_decl);
-  int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
-		   && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
-		       != void_type_node)))
-		? UNITS_PER_WORD : 0);
-
-  if (argadj)
-    offset = plus_constant (current_function_arg_offset_rtx, argadj);
-  else
-    offset = current_function_arg_offset_rtx;
-
-  /* Store general registers on the stack. */
-  dest = gen_rtx_MEM (BLKmode,
-		      plus_constant (current_function_internal_arg_pointer,
-				     -16));
-  move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
-
-  /* move_block_from_reg will emit code to store the argument registers
-     individually as scalar stores.
-
-     However, other insns may later load from the same addresses for
-     a structure load (passing a struct to a varargs routine).
-
-     The alias code assumes that such aliasing can never happen, so we
-     have to keep memory referencing insns from moving up beyond the
-     last argument register store.  So we emit a blockage insn here.  */
-  emit_insn (gen_blockage ());
-
-  if (current_function_check_memory_usage)
-    emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
-		       dest, ptr_mode,
-		       GEN_INT (4 * UNITS_PER_WORD), TYPE_MODE (sizetype),
-		       GEN_INT (MEMORY_USE_RW),
-		       TYPE_MODE (integer_type_node));
-
-  return copy_to_reg (expand_binop (Pmode, add_optab,
-				    current_function_internal_arg_pointer,
-				    offset, 0, 0, OPTAB_LIB_WIDEN));
-}
-
-/* This routine handles all the normal conditional branch sequences we
-   might need to generate.  It handles compare immediate vs compare
-   register, nullification of delay slots, varying length branches,
-   negated branches, and all combinations of the above.  It returns the
-   output appropriate to emit the branch corresponding to all given
-   parameters.  */
-
-char *
-output_cbranch (operands, nullify, length, negated, insn)
-  rtx *operands;
-  int nullify, length, negated;
-  rtx insn;
-{
-  static char buf[100];
-  int useskip = 0;
-
-  /* A conditional branch to the following instruction (eg the delay slot) is
-     asking for a disaster.  This can happen when not optimizing.
-
-     In such cases it is safe to emit nothing.  */
-
-  if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
-    return "";
-
-  /* If this is a long branch with its delay slot unfilled, set `nullify'
-     as it can nullify the delay slot and save a nop.  */
-  if (length == 8 && dbr_sequence_length () == 0)
-    nullify = 1;
-
-  /* If this is a short forward conditional branch which did not get
-     its delay slot filled, the delay slot can still be nullified.  */
-  if (! nullify && length == 4 && dbr_sequence_length () == 0)
-    nullify = forward_branch_p (insn);
-
-  /* A forward branch over a single nullified insn can be done with a
-     comclr instruction.  This avoids a single cycle penalty due to
-     mis-predicted branch if we fall through (branch not taken).  */
-  if (length == 4
-      && next_real_insn (insn) != 0
-      && get_attr_length (next_real_insn (insn)) == 4
-      && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
-      && nullify)
-    useskip = 1;
-
-  switch (length)
-    {
-      /* All short conditional branches except backwards with an unfilled
-	 delay slot.  */
-      case 4:
-	if (useskip)
-	  strcpy (buf, "com%I2clr,");
-	else
-	  strcpy (buf, "com%I2b,");
-	if (negated)
-	  strcat (buf, "%B3");
-	else
-	  strcat (buf, "%S3");
-	if (useskip)
-	  strcat (buf, " %2,%r1,0");
-	else if (nullify)
-	  strcat (buf, ",n %2,%r1,%0");
-	else
-	  strcat (buf, " %2,%r1,%0");
-	break;
-
-     /* All long conditionals.  Note an short backward branch with an
-	unfilled delay slot is treated just like a long backward branch
-	with an unfilled delay slot.  */
-      case 8:
-	/* Handle weird backwards branch with a filled delay slot
-	   with is nullified.  */
-	if (dbr_sequence_length () != 0
-	    && ! forward_branch_p (insn)
-	    && nullify)
-	  {
-	    strcpy (buf, "com%I2b,");
-	    if (negated)
-	      strcat (buf, "%S3");
-	    else
-	      strcat (buf, "%B3");
-	    strcat (buf, ",n %2,%r1,.+12\n\tbl %0,0");
-	  }
-	/* Handle short backwards branch with an unfilled delay slot.
-	   Using a comb;nop rather than comiclr;bl saves 1 cycle for both
-	   taken and untaken branches.  */
-	else if (dbr_sequence_length () == 0
-		 && ! forward_branch_p (insn)
-		 && insn_addresses
-		 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
-				    - insn_addresses[INSN_UID (insn)] - 8))
-	  {
-	    strcpy (buf, "com%I2b,");
-	    if (negated)
-	      strcat (buf, "%B3 %2,%r1,%0%#");
-	    else
-	      strcat (buf, "%S3 %2,%r1,%0%#");
-	  }
-	else
-	  {
-	    strcpy (buf, "com%I2clr,");
-	    if (negated)
-	      strcat (buf, "%S3");
-	    else
-	      strcat (buf, "%B3");
-	    if (nullify)
-	      strcat (buf, " %2,%r1,0\n\tbl,n %0,0");
-	    else
-	      strcat (buf, " %2,%r1,0\n\tbl %0,0");
-	  }
-	break;
-
-      case 20:
-	/* Very long branch.  Right now we only handle these when not
-	   optimizing.  See "jump" pattern in pa.md for details.  */
-	if (optimize)
-	  abort ();
-
-	/* Create a reversed conditional branch which branches around
-	   the following insns.  */
-	if (negated)
-	  strcpy (buf, "com%I2b,%S3,n %2,%r1,.+20");
-	else
-	  strcpy (buf, "com%I2b,%B3,n %2,%r1,.+20");
-	output_asm_insn (buf, operands);
-
-	/* Output an insn to save %r1.  */
-	output_asm_insn ("stw %%r1,-16(%%r30)", operands);
-
-	/* Now output a very long branch to the original target.  */
-	output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
-
-	/* Now restore the value of %r1 in the delay slot.  We're not
-	   optimizing so we know nothing else can be in the delay slot.  */
-	return "ldw -16(%%r30),%%r1";
-
-      case 28:
-	/* Very long branch when generating PIC code.  Right now we only
-	   handle these when not optimizing.  See "jump" pattern in pa.md
-	   for details.  */
-	if (optimize)
-	  abort ();
-
-	/* Create a reversed conditional branch which branches around
-	   the following insns.  */
-	if (negated)
-	  strcpy (buf, "com%I2b,%S3,n %2,%r1,.+28");
-	else
-	  strcpy (buf, "com%I2b,%B3,n %2,%r1,.+28");
-	output_asm_insn (buf, operands);
-
-	/* Output an insn to save %r1.  */
-	output_asm_insn ("stw %%r1,-16(%%r30)", operands);
-
-	/* Now output a very long PIC branch to the original target.  */
-	{
-	  rtx xoperands[5];
-
-	  xoperands[0] = operands[0];
-	  xoperands[1] = operands[1];
-	  xoperands[2] = operands[2];
-	  xoperands[3] = operands[3];
-	  xoperands[4] = gen_label_rtx ();
-
-	  output_asm_insn ("bl .+8,%%r1\n\taddil L'%l0-%l4,%%r1", xoperands);
-	  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				     CODE_LABEL_NUMBER (xoperands[4]));
-	  output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv 0(%%r1)", xoperands);
-	}
-
-	/* Now restore the value of %r1 in the delay slot.  We're not
-	   optimizing so we know nothing else can be in the delay slot.  */
-	return "ldw -16(%%r30),%%r1";
-	
-      default:
-	abort();
-    }
-  return buf;
-}
-
-/* This routine handles all the branch-on-bit conditional branch sequences we
-   might need to generate.  It handles nullification of delay slots,
-   varying length branches, negated branches and all combinations of the
-   above.  it returns the appropriate output template to emit the branch.  */
-
-char *
-output_bb (operands, nullify, length, negated, insn, which)
-  rtx *operands ATTRIBUTE_UNUSED;
-  int nullify, length, negated;
-  rtx insn;
-  int which;
-{
-  static char buf[100];
-  int useskip = 0;
-
-  /* A conditional branch to the following instruction (eg the delay slot) is
-     asking for a disaster.  I do not think this can happen as this pattern
-     is only used when optimizing; jump optimization should eliminate the
-     jump.  But be prepared just in case.  */
-
-  if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
-    return "";
-
-  /* If this is a long branch with its delay slot unfilled, set `nullify'
-     as it can nullify the delay slot and save a nop.  */
-  if (length == 8 && dbr_sequence_length () == 0)
-    nullify = 1;
-
-  /* If this is a short forward conditional branch which did not get
-     its delay slot filled, the delay slot can still be nullified.  */
-  if (! nullify && length == 4 && dbr_sequence_length () == 0)
-    nullify = forward_branch_p (insn);
-
-  /* A forward branch over a single nullified insn can be done with a
-     extrs instruction.  This avoids a single cycle penalty due to
-     mis-predicted branch if we fall through (branch not taken).  */
-
-  if (length == 4
-      && next_real_insn (insn) != 0
-      && get_attr_length (next_real_insn (insn)) == 4
-      && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
-      && nullify)
-    useskip = 1;
-
-  switch (length)
-    {
-
-      /* All short conditional branches except backwards with an unfilled
-	 delay slot.  */
-      case 4:
-	if (useskip)
-	  strcpy (buf, "extrs,");
-	else
-	  strcpy (buf, "bb,");
-	if ((which == 0 && negated)
-	     || (which == 1 && ! negated))
-	  strcat (buf, ">=");
-	else
-	  strcat (buf, "<");
-	if (useskip)
-	  strcat (buf, " %0,%1,1,0");
-	else if (nullify && negated)
-	  strcat (buf, ",n %0,%1,%3");
-	else if (nullify && ! negated)
-	  strcat (buf, ",n %0,%1,%2");
-	else if (! nullify && negated)
-	  strcat (buf, "%0,%1,%3");
-	else if (! nullify && ! negated)
-	  strcat (buf, " %0,%1,%2");
-	break;
-
-     /* All long conditionals.  Note an short backward branch with an
-	unfilled delay slot is treated just like a long backward branch
-	with an unfilled delay slot.  */
-      case 8:
-	/* Handle weird backwards branch with a filled delay slot
-	   with is nullified.  */
-	if (dbr_sequence_length () != 0
-	    && ! forward_branch_p (insn)
-	    && nullify)
-	  {
-	    strcpy (buf, "bb,");
-	    if ((which == 0 && negated)
-		|| (which == 1 && ! negated))
-	      strcat (buf, "<");
-	    else
-	      strcat (buf, ">=");
-	    if (negated)
-	      strcat (buf, ",n %0,%1,.+12\n\tbl %3,0");
-	    else
-	      strcat (buf, ",n %0,%1,.+12\n\tbl %2,0");
-	  }
-	/* Handle short backwards branch with an unfilled delay slot.
-	   Using a bb;nop rather than extrs;bl saves 1 cycle for both
-	   taken and untaken branches.  */
-	else if (dbr_sequence_length () == 0
-		 && ! forward_branch_p (insn)
-		 && insn_addresses
-		 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
-				    - insn_addresses[INSN_UID (insn)] - 8))
-	  {
-	    strcpy (buf, "bb,");
-	    if ((which == 0 && negated)
-		|| (which == 1 && ! negated))
-	      strcat (buf, ">=");
-	    else
-	      strcat (buf, "<");
-	    if (negated)
-	      strcat (buf, " %0,%1,%3%#");
-	    else
-	      strcat (buf, " %0,%1,%2%#");
-	  }
-	else
-	  {
-	    strcpy (buf, "extrs,");
-	    if ((which == 0 && negated)
-		|| (which == 1 && ! negated))
-	      strcat (buf, "<");
-	    else
-	      strcat (buf, ">=");
-	    if (nullify && negated)
-	      strcat (buf, " %0,%1,1,0\n\tbl,n %3,0");
-	    else if (nullify && ! negated)
-	      strcat (buf, " %0,%1,1,0\n\tbl,n %2,0");
-	    else if (negated)
-	      strcat (buf, " %0,%1,1,0\n\tbl %3,0");
-	    else
-	      strcat (buf, " %0,%1,1,0\n\tbl %2,0");
-	  }
-	break;
-
-      default:
-	abort();
-    }
-  return buf;
-}
-
-/* This routine handles all the branch-on-variable-bit conditional branch
-   sequences we might need to generate.  It handles nullification of delay
-   slots, varying length branches, negated branches and all combinations
-   of the above.  it returns the appropriate output template to emit the
-   branch.  */
-
-char *
-output_bvb (operands, nullify, length, negated, insn, which)
-  rtx *operands ATTRIBUTE_UNUSED;
-  int nullify, length, negated;
-  rtx insn;
-  int which;
-{
-  static char buf[100];
-  int useskip = 0;
-
-  /* A conditional branch to the following instruction (eg the delay slot) is
-     asking for a disaster.  I do not think this can happen as this pattern
-     is only used when optimizing; jump optimization should eliminate the
-     jump.  But be prepared just in case.  */
-
-  if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
-    return "";
-
-  /* If this is a long branch with its delay slot unfilled, set `nullify'
-     as it can nullify the delay slot and save a nop.  */
-  if (length == 8 && dbr_sequence_length () == 0)
-    nullify = 1;
-
-  /* If this is a short forward conditional branch which did not get
-     its delay slot filled, the delay slot can still be nullified.  */
-  if (! nullify && length == 4 && dbr_sequence_length () == 0)
-    nullify = forward_branch_p (insn);
-
-  /* A forward branch over a single nullified insn can be done with a
-     extrs instruction.  This avoids a single cycle penalty due to
-     mis-predicted branch if we fall through (branch not taken).  */
-
-  if (length == 4
-      && next_real_insn (insn) != 0
-      && get_attr_length (next_real_insn (insn)) == 4
-      && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
-      && nullify)
-    useskip = 1;
-
-  switch (length)
-    {
-
-      /* All short conditional branches except backwards with an unfilled
-	 delay slot.  */
-      case 4:
-	if (useskip)
-	  strcpy (buf, "vextrs,");
-	else
-	  strcpy (buf, "bvb,");
-	if ((which == 0 && negated)
-	     || (which == 1 && ! negated))
-	  strcat (buf, ">=");
-	else
-	  strcat (buf, "<");
-	if (useskip)
-	  strcat (buf, " %0,1,0");
-	else if (nullify && negated)
-	  strcat (buf, ",n %0,%3");
-	else if (nullify && ! negated)
-	  strcat (buf, ",n %0,%2");
-	else if (! nullify && negated)
-	  strcat (buf, "%0,%3");
-	else if (! nullify && ! negated)
-	  strcat (buf, " %0,%2");
-	break;
-
-     /* All long conditionals.  Note an short backward branch with an
-	unfilled delay slot is treated just like a long backward branch
-	with an unfilled delay slot.  */
-      case 8:
-	/* Handle weird backwards branch with a filled delay slot
-	   with is nullified.  */
-	if (dbr_sequence_length () != 0
-	    && ! forward_branch_p (insn)
-	    && nullify)
-	  {
-	    strcpy (buf, "bvb,");
-	    if ((which == 0 && negated)
-		|| (which == 1 && ! negated))
-	      strcat (buf, "<");
-	    else
-	      strcat (buf, ">=");
-	    if (negated)
-	      strcat (buf, ",n %0,.+12\n\tbl %3,0");
-	    else
-	      strcat (buf, ",n %0,.+12\n\tbl %2,0");
-	  }
-	/* Handle short backwards branch with an unfilled delay slot.
-	   Using a bb;nop rather than extrs;bl saves 1 cycle for both
-	   taken and untaken branches.  */
-	else if (dbr_sequence_length () == 0
-		 && ! forward_branch_p (insn)
-		 && insn_addresses
-		 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
-				    - insn_addresses[INSN_UID (insn)] - 8))
-	  {
-	    strcpy (buf, "bvb,");
-	    if ((which == 0 && negated)
-		|| (which == 1 && ! negated))
-	      strcat (buf, ">=");
-	    else
-	      strcat (buf, "<");
-	    if (negated)
-	      strcat (buf, " %0,%3%#");
-	    else
-	      strcat (buf, " %0,%2%#");
-	  }
-	else
-	  {
-	    strcpy (buf, "vextrs,");
-	    if ((which == 0 && negated)
-		|| (which == 1 && ! negated))
-	      strcat (buf, "<");
-	    else
-	      strcat (buf, ">=");
-	    if (nullify && negated)
-	      strcat (buf, " %0,1,0\n\tbl,n %3,0");
-	    else if (nullify && ! negated)
-	      strcat (buf, " %0,1,0\n\tbl,n %2,0");
-	    else if (negated)
-	      strcat (buf, " %0,1,0\n\tbl %3,0");
-	    else
-	      strcat (buf, " %0,1,0\n\tbl %2,0");
-	  }
-	break;
-
-      default:
-	abort();
-    }
-  return buf;
-}
-
-/* Return the output template for emitting a dbra type insn.
-
-   Note it may perform some output operations on its own before
-   returning the final output string.  */
-char *
-output_dbra (operands, insn, which_alternative)
-     rtx *operands;
-     rtx insn;
-     int which_alternative;
-{
-
-  /* A conditional branch to the following instruction (eg the delay slot) is
-     asking for a disaster.  Be prepared!  */
-
-  if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
-    {
-      if (which_alternative == 0)
-	return "ldo %1(%0),%0";
-      else if (which_alternative == 1)
-	{
-	  output_asm_insn ("fstws %0,-16(0,%%r30)",operands);
-	  output_asm_insn ("ldw -16(0,%%r30),%4",operands);
-	  output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands);
-	  return "fldws -16(0,%%r30),%0";
-	}
-      else
-	{
-	  output_asm_insn ("ldw %0,%4", operands);
-	  return "ldo %1(%4),%4\n\tstw %4,%0";
-	}
-    }
-
-  if (which_alternative == 0)
-    {
-      int nullify = INSN_ANNULLED_BRANCH_P (insn);
-      int length = get_attr_length (insn);
-
-      /* If this is a long branch with its delay slot unfilled, set `nullify'
-	 as it can nullify the delay slot and save a nop.  */
-      if (length == 8 && dbr_sequence_length () == 0)
-	nullify = 1;
-
-      /* If this is a short forward conditional branch which did not get
-	 its delay slot filled, the delay slot can still be nullified.  */
-      if (! nullify && length == 4 && dbr_sequence_length () == 0)
-	nullify = forward_branch_p (insn);
-
-      /* Handle short versions first.  */
-      if (length == 4 && nullify)
-	return "addib,%C2,n %1,%0,%3";
-      else if (length == 4 && ! nullify)
-	return "addib,%C2 %1,%0,%3";
-      else if (length == 8)
-	{
-	  /* Handle weird backwards branch with a fulled delay slot
-	     which is nullified.  */
-	  if (dbr_sequence_length () != 0
-	      && ! forward_branch_p (insn)
-	      && nullify)
-	    return "addib,%N2,n %1,%0,.+12\n\tbl %3,0";
-	  /* Handle short backwards branch with an unfilled delay slot.
-	     Using a addb;nop rather than addi;bl saves 1 cycle for both
-	     taken and untaken branches.  */
-	  else if (dbr_sequence_length () == 0
-		   && ! forward_branch_p (insn)
-		   && insn_addresses
-		   && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
-				      - insn_addresses[INSN_UID (insn)] - 8))
-	      return "addib,%C2 %1,%0,%3%#";
-
-	  /* Handle normal cases.  */
-	  if (nullify)
-	    return "addi,%N2 %1,%0,%0\n\tbl,n %3,0";
-	  else
-	    return "addi,%N2 %1,%0,%0\n\tbl %3,0";
-	}
-      else
-	abort();
-    }
-  /* Deal with gross reload from FP register case.  */
-  else if (which_alternative == 1)
-    {
-      /* Move loop counter from FP register to MEM then into a GR,
-	 increment the GR, store the GR into MEM, and finally reload
-	 the FP register from MEM from within the branch's delay slot.  */
-      output_asm_insn ("fstws %0,-16(0,%%r30)\n\tldw -16(0,%%r30),%4",operands);
-      output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands);
-      if (get_attr_length (insn) == 24)
-	return "comb,%S2 0,%4,%3\n\tfldws -16(0,%%r30),%0";
-      else
-	return "comclr,%B2 0,%4,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
-    }
-  /* Deal with gross reload from memory case.  */
-  else
-    {
-      /* Reload loop counter from memory, the store back to memory
-	 happens in the branch's delay slot.   */
-      output_asm_insn ("ldw %0,%4", operands);
-      if (get_attr_length (insn) == 12)
-	return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
-      else
-	return "addi,%N2 %1,%4,%4\n\tbl %3,0\n\tstw %4,%0";
-    }
-}
-
-/* Return the output template for emitting a dbra type insn.
-
-   Note it may perform some output operations on its own before
-   returning the final output string.  */
-char *
-output_movb (operands, insn, which_alternative, reverse_comparison)
-     rtx *operands;
-     rtx insn;
-     int which_alternative;
-     int reverse_comparison;
-{
-
-  /* A conditional branch to the following instruction (eg the delay slot) is
-     asking for a disaster.  Be prepared!  */
-
-  if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
-    {
-      if (which_alternative == 0)
-	return "copy %1,%0";
-      else if (which_alternative == 1)
-	{
-	  output_asm_insn ("stw %1,-16(0,%%r30)",operands);
-	  return "fldws -16(0,%%r30),%0";
-	}
-      else if (which_alternative == 2)
-	return "stw %1,%0";
-      else
-	return "mtsar %r1";
-    }
-
-  /* Support the second variant.  */
-  if (reverse_comparison)
-    PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
-
-  if (which_alternative == 0)
-    {
-      int nullify = INSN_ANNULLED_BRANCH_P (insn);
-      int length = get_attr_length (insn);
-
-      /* If this is a long branch with its delay slot unfilled, set `nullify'
-	 as it can nullify the delay slot and save a nop.  */
-      if (length == 8 && dbr_sequence_length () == 0)
-	nullify = 1;
-
-      /* If this is a short forward conditional branch which did not get
-	 its delay slot filled, the delay slot can still be nullified.  */
-      if (! nullify && length == 4 && dbr_sequence_length () == 0)
-	nullify = forward_branch_p (insn);
-
-      /* Handle short versions first.  */
-      if (length == 4 && nullify)
-	return "movb,%C2,n %1,%0,%3";
-      else if (length == 4 && ! nullify)
-	return "movb,%C2 %1,%0,%3";
-      else if (length == 8)
-	{
-	  /* Handle weird backwards branch with a filled delay slot
-	     which is nullified.  */
-	  if (dbr_sequence_length () != 0
-	      && ! forward_branch_p (insn)
-	      && nullify)
-	    return "movb,%N2,n %1,%0,.+12\n\tbl %3,0";
-
-	  /* Handle short backwards branch with an unfilled delay slot.
-	     Using a movb;nop rather than or;bl saves 1 cycle for both
-	     taken and untaken branches.  */
-	  else if (dbr_sequence_length () == 0
-		   && ! forward_branch_p (insn)
-		   && insn_addresses
-		   && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
-				      - insn_addresses[INSN_UID (insn)] - 8))
-	    return "movb,%C2 %1,%0,%3%#";
-	  /* Handle normal cases.  */
-	  if (nullify)
-	    return "or,%N2 %1,%%r0,%0\n\tbl,n %3,0";
-	  else
-	    return "or,%N2 %1,%%r0,%0\n\tbl %3,0";
-	}
-      else
-	abort();
-    }
-  /* Deal with gross reload from FP register case.  */
-  else if (which_alternative == 1)
-    {
-      /* Move loop counter from FP register to MEM then into a GR,
-	 increment the GR, store the GR into MEM, and finally reload
-	 the FP register from MEM from within the branch's delay slot.  */
-      output_asm_insn ("stw %1,-16(0,%%r30)",operands);
-      if (get_attr_length (insn) == 12)
-	return "comb,%S2 0,%1,%3\n\tfldws -16(0,%%r30),%0";
-      else
-	return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
-    }
-  /* Deal with gross reload from memory case.  */
-  else if (which_alternative == 2)
-    {
-      /* Reload loop counter from memory, the store back to memory
-	 happens in the branch's delay slot.   */
-      if (get_attr_length (insn) == 8)
-	return "comb,%S2 0,%1,%3\n\tstw %1,%0";
-      else
-	return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tstw %1,%0";
-    }
-  /* Handle SAR as a destination.  */
-  else
-    {
-      if (get_attr_length (insn) == 8)
-	return "comb,%S2 0,%1,%3\n\tmtsar %r1";
-      else
-	return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tmtsar %r1";
-    }
-}
-
-
-/* INSN is a millicode call.  It may have an unconditional jump in its delay
-   slot.
-
-   CALL_DEST is the routine we are calling.  */
-
-char *
-output_millicode_call (insn, call_dest)
-  rtx insn;
-  rtx call_dest;
-{
-  int distance;
-  rtx xoperands[4];
-  rtx seq_insn;
-
-  /* Handle common case -- empty delay slot or no jump in the delay slot,
-     and we're sure that the branch will reach the beginning of the $CODE$
-     subspace.  */
-  if ((dbr_sequence_length () == 0
-       && (get_attr_length (insn) == 8 || get_attr_length (insn) == 28))
-      || (dbr_sequence_length () != 0
-	  && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
-	  && get_attr_length (insn) == 4))
-    {
-      xoperands[0] = call_dest;
-      output_asm_insn ("bl %0,%%r31%#", xoperands);
-      return "";
-    }
-
-  /* This call may not reach the beginning of the $CODE$ subspace.  */
-  if (get_attr_length (insn) > 4)
-    {
-      int delay_insn_deleted = 0;
-      rtx xoperands[2];
-
-      /* We need to emit an inline long-call branch.  */
-      if (dbr_sequence_length () != 0
-	  && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
-	{
-	  /* A non-jump insn in the delay slot.  By definition we can
-	     emit this insn before the call.  */
-	  final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
-
-	  /* Now delete the delay insn.  */
-	  PUT_CODE (NEXT_INSN (insn), NOTE);
-	  NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
-	  NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
-	  delay_insn_deleted = 1;
-	}
-
-      /* If we're allowed to use be/ble instructions, then this is the
-	 best sequence to use for a long millicode call.  */
-      if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS
-	  || ! (flag_pic  || TARGET_PORTABLE_RUNTIME))
-	{
-	  xoperands[0] = call_dest;
-	  output_asm_insn ("ldil L%%%0,%%r31", xoperands);
-	  output_asm_insn ("ble R%%%0(%%sr4,%%r31)", xoperands);
-	  output_asm_insn ("nop", xoperands);
-	}
-      /* Pure portable runtime doesn't allow be/ble; we also don't have
-	 PIC support int he assembler/linker, so this sequence is needed.  */
-      else if (TARGET_PORTABLE_RUNTIME)
-	{
-	  xoperands[0] = call_dest;
-	  /* Get the address of our target into %r29. */
-	  output_asm_insn ("ldil L%%%0,%%r29", xoperands);
-	  output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
-
-	  /* Get our return address into %r31.  */
-	  output_asm_insn ("blr 0,%%r31", xoperands);
-
-	  /* Jump to our target address in %r29.  */
-	  output_asm_insn ("bv,n 0(%%r29)", xoperands);
-
-	  /* Empty delay slot.  Note this insn gets fetched twice and
-	     executed once.  To be safe we use a nop.  */
-	  output_asm_insn ("nop", xoperands);
-	  return "";
-	}
-      /* PIC long millicode call sequence.  */
-      else
-	{
-	  xoperands[0] = call_dest;
-	  xoperands[1] = gen_label_rtx ();
-	  /* Get our address + 8 into %r1.  */
-	  output_asm_insn ("bl .+8,%%r1", xoperands);
-
-	  /* Add %r1 to the offset of our target from the next insn.  */
-	  output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
-	  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				     CODE_LABEL_NUMBER (xoperands[1]));
-	  output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
-
-	  /* Get the return address into %r31.  */
-	  output_asm_insn ("blr 0,%%r31", xoperands);
-
-	  /* Branch to our target which is in %r1.  */
-	  output_asm_insn ("bv,n 0(%%r1)", xoperands);
-
-	  /* Empty delay slot.  Note this insn gets fetched twice and
-	     executed once.  To be safe we use a nop.  */
-	  output_asm_insn ("nop", xoperands);
-	}
-
-      /* If we had a jump in the call's delay slot, output it now.  */
-      if (dbr_sequence_length () != 0
-	  && !delay_insn_deleted)
-	{
-	  xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
-	  output_asm_insn ("b,n %0", xoperands);
-
-	  /* Now delete the delay insn.  */
-	  PUT_CODE (NEXT_INSN (insn), NOTE);
-	  NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
-	  NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
-	}
-      return "";
-    }
-
-  /* This call has an unconditional jump in its delay slot and the
-     call is known to reach its target or the beginning of the current
-     subspace.  */
-
-  /* Use the containing sequence insn's address.  */
-  seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
-
-  distance = insn_addresses[INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))]
-	       - insn_addresses[INSN_UID (seq_insn)] - 8;
-
-  /* If the branch was too far away, emit a normal call followed
-     by a nop, followed by the unconditional branch.
-
-     If the branch is close, then adjust %r2 from within the
-     call's delay slot.  */
-
-  xoperands[0] = call_dest;
-  xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
-  if (! VAL_14_BITS_P (distance))
-    output_asm_insn ("bl %0,%%r31\n\tnop\n\tbl,n %1,%%r0", xoperands);
-  else
-    {
-      xoperands[3] = gen_label_rtx ();
-      output_asm_insn ("\n\tbl %0,%%r31\n\tldo %1-%3(%%r31),%%r31", xoperands);
-      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				 CODE_LABEL_NUMBER (xoperands[3]));
-    }
-
-  /* Delete the jump.  */
-  PUT_CODE (NEXT_INSN (insn), NOTE);
-  NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
-  NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
-  return "";
-}
-
-extern struct obstack permanent_obstack;
-extern struct obstack *saveable_obstack;
-extern struct obstack *rtl_obstack;
-extern struct obstack *current_obstack;
-
-/* INSN is either a function call.  It may have an unconditional jump
-   in its delay slot.
-
-   CALL_DEST is the routine we are calling.  */
-
-char *
-output_call (insn, call_dest)
-  rtx insn;
-  rtx call_dest;
-{
-  int distance;
-  rtx xoperands[4];
-  rtx seq_insn;
-
-  /* Handle common case -- empty delay slot or no jump in the delay slot,
-     and we're sure that the branch will reach the beginning of the $CODE$
-     subspace.  */
-  if ((dbr_sequence_length () == 0
-       && get_attr_length (insn) == 8)
-      || (dbr_sequence_length () != 0
-	  && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
-	  && get_attr_length (insn) == 4))
-    {
-      xoperands[0] = call_dest;
-      output_asm_insn ("bl %0,%%r2%#", xoperands);
-      return "";
-    }
-
-  /* This call may not reach the beginning of the $CODE$ subspace.  */
-  if (get_attr_length (insn) > 8)
-    {
-      int delay_insn_deleted = 0;
-      rtx xoperands[2];
-      rtx link;
-
-      /* We need to emit an inline long-call branch.  Furthermore,
-	 because we're changing a named function call into an indirect
-	 function call well after the parameters have been set up, we
-	 need to make sure any FP args appear in both the integer
-	 and FP registers.  Also, we need move any delay slot insn
-	 out of the delay slot.  And finally, we can't rely on the linker
-	 being able to fix the call to $$dyncall!  -- Yuk!.  */
-      if (dbr_sequence_length () != 0
-	  && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
-	{
-	  /* A non-jump insn in the delay slot.  By definition we can
-	     emit this insn before the call (and in fact before argument
-	     relocating.  */
-	  final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
-
-	  /* Now delete the delay insn.  */
-	  PUT_CODE (NEXT_INSN (insn), NOTE);
-	  NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
-	  NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
-	  delay_insn_deleted = 1;
-	}
-
-      /* Now copy any FP arguments into integer registers.  */
-      for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
-	{
-	  int arg_mode, regno;
-	  rtx use = XEXP (link, 0);
-	  if (! (GET_CODE (use) == USE
-		 && GET_CODE (XEXP (use, 0)) == REG
-		 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
-	    continue;
-
-	  arg_mode = GET_MODE (XEXP (use, 0));
-	  regno = REGNO (XEXP (use, 0));
-	  /* Is it a floating point register?  */
-	  if (regno >= 32 && regno <= 39)
-	    {
-	      /* Copy from the FP register into an integer register
-		 (via memory).  */
-	      if (arg_mode == SFmode)
-		{
-		  xoperands[0] = XEXP (use, 0);
-		  xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
-		  output_asm_insn ("fstws %0,-16(%%sr0,%%r30)", xoperands);
-		  output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
-		}
-	      else
-		{
-		  xoperands[0] = XEXP (use, 0);
-		  xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
-		  output_asm_insn ("fstds %0,-16(%%sr0,%%r30)", xoperands);
-		  output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
-		  output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
-		}
-	    }
-	}
-
-      /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
-	 we don't have any direct calls in that case.  */
-	{
-	  int i;
-	  char *name = XSTR (call_dest, 0);
-
-	  /* See if we have already put this function on the list
-	     of deferred plabels.  This list is generally small,
-	     so a liner search is not too ugly.  If it proves too
-	     slow replace it with something faster.  */
-	  for (i = 0; i < n_deferred_plabels; i++)
-	    if (strcmp (name, deferred_plabels[i].name) == 0)
-	      break;
-
-	  /* If the deferred plabel list is empty, or this entry was
-	     not found on the list, create a new entry on the list.  */
-	  if (deferred_plabels == NULL || i == n_deferred_plabels)
-	    {
-	      struct obstack *ambient_obstack = current_obstack;
-	      struct obstack *ambient_rtl_obstack = rtl_obstack;
-	      char *real_name;
-
-	      /* Any RTL we create here needs to live until the end of
-		 the compilation unit and therefore must live on the
-		 permanent obstack.  */
-	      current_obstack = &permanent_obstack;
-	      rtl_obstack = &permanent_obstack;
-
-	      if (deferred_plabels == 0)
-		deferred_plabels = (struct deferred_plabel *)
-		  xmalloc (1 * sizeof (struct deferred_plabel));
-	      else
-		deferred_plabels = (struct deferred_plabel *)
-		  xrealloc (deferred_plabels,
-			    ((n_deferred_plabels + 1)
-			     * sizeof (struct deferred_plabel)));
-
-	      i = n_deferred_plabels++;
-	      deferred_plabels[i].internal_label = gen_label_rtx ();
-	      deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
-							strlen (name) + 1);
-	      strcpy (deferred_plabels[i].name, name);
-
-	      /* Switch back to normal obstack allocation.  */
-	      current_obstack = ambient_obstack;
-	      rtl_obstack = ambient_rtl_obstack;
-
-	      /* Gross.  We have just implicitly taken the address of this
-		 function, mark it as such.  */
-	      STRIP_NAME_ENCODING (real_name, name);
-	      TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
-	    }
-
-	  /* We have to load the address of the function using a procedure
-	     label (plabel).  Inline plabels can lose for PIC and other
-	     cases, so avoid them by creating a 32bit plabel in the data
-	     segment.  */
-	  if (flag_pic)
-	    {
-	      xoperands[0] = deferred_plabels[i].internal_label;
-	      xoperands[1] = gen_label_rtx ();
-
-	      output_asm_insn ("addil LT%%%0,%%r19", xoperands);
-	      output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
-	      output_asm_insn ("ldw 0(0,%%r22),%%r22", xoperands);
-
-	      /* Get our address + 8 into %r1.  */
-	      output_asm_insn ("bl .+8,%%r1", xoperands);
-
-	      /* Add %r1 to the offset of dyncall from the next insn.  */
-	      output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
-	      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-					 CODE_LABEL_NUMBER (xoperands[1]));
-	      output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
-
-	      /* Get the return address into %r31.  */
-	      output_asm_insn ("blr 0,%%r31", xoperands);
-
-	      /* Branch to our target which is in %r1.  */
-	      output_asm_insn ("bv 0(%%r1)", xoperands);
-
-	      /* Copy the return address into %r2 also.  */
-	      output_asm_insn ("copy %%r31,%%r2", xoperands);
-	    }
-	  else
-	    {
-	      xoperands[0] = deferred_plabels[i].internal_label;
-
-	      /* Get the address of our target into %r22.  */
-	      output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
-	      output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
-
-	      /* Get the high part of the  address of $dyncall into %r2, then
-		 add in the low part in the branch instruction.  */
-	      output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
-	      output_asm_insn ("ble  R%%$$dyncall(%%sr4,%%r2)", xoperands);
-
-	      /* Copy the return pointer into both %r31 and %r2.  */
-	      output_asm_insn ("copy %%r31,%%r2", xoperands);
-	    }
-	}
-
-      /* If we had a jump in the call's delay slot, output it now.  */
-      if (dbr_sequence_length () != 0
-	  && !delay_insn_deleted)
-	{
-	  xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
-	  output_asm_insn ("b,n %0", xoperands);
-
-	  /* Now delete the delay insn.  */
-	  PUT_CODE (NEXT_INSN (insn), NOTE);
-	  NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
-	  NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
-	}
-      return "";
-    }
-
-  /* This call has an unconditional jump in its delay slot and the
-     call is known to reach its target or the beginning of the current
-     subspace.  */
-
-  /* Use the containing sequence insn's address.  */
-  seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
-
-  distance = insn_addresses[INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))]
-	       - insn_addresses[INSN_UID (seq_insn)] - 8;
-
-  /* If the branch was too far away, emit a normal call followed
-     by a nop, followed by the unconditional branch.
-
-     If the branch is close, then adjust %r2 from within the
-     call's delay slot.  */
-
-  xoperands[0] = call_dest;
-  xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
-  if (! VAL_14_BITS_P (distance))
-    output_asm_insn ("bl %0,%%r2\n\tnop\n\tbl,n %1,%%r0", xoperands);
-  else
-    {
-      xoperands[3] = gen_label_rtx ();
-      output_asm_insn ("\n\tbl %0,%%r2\n\tldo %1-%3(%%r2),%%r2", xoperands);
-      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				 CODE_LABEL_NUMBER (xoperands[3]));
-    }
-
-  /* Delete the jump.  */
-  PUT_CODE (NEXT_INSN (insn), NOTE);
-  NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
-  NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
-  return "";
-}
-
-/* In HPUX 8.0's shared library scheme, special relocations are needed
-   for function labels if they might be passed to a function
-   in a shared library (because shared libraries don't live in code
-   space), and special magic is needed to construct their address.
-
-   For reasons too disgusting to describe storage for the new name
-   is allocated either on the saveable_obstack (released at function
-   exit) or on the permanent_obstack for things that can never change
-   (libcall names for example). */
-
-void
-hppa_encode_label (sym, permanent)
-     rtx sym;
-     int permanent;
-{
-  char *str = XSTR (sym, 0);
-  int len = strlen (str);
-  char *newstr;
-
-  newstr = obstack_alloc ((permanent ? &permanent_obstack : saveable_obstack),
-			  len + 2);
-
-  if (str[0] == '*')
-    *newstr++ = *str++;
-  strcpy (newstr + 1, str);
-  *newstr = '@';
-  XSTR (sym,0) = newstr;
-}
-
-int
-function_label_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
-}
-
-/* Returns 1 if OP is a function label involved in a simple addition
-   with a constant.  Used to keep certain patterns from matching
-   during instruction combination.  */
-int
-is_function_label_plus_const (op)
-     rtx op;
-{
-  /* Strip off any CONST.  */
-  if (GET_CODE (op) == CONST)
-    op = XEXP (op, 0);
-
-  return (GET_CODE (op) == PLUS
-	  && function_label_operand (XEXP (op, 0), Pmode)
-	  && GET_CODE (XEXP (op, 1)) == CONST_INT);
-}
-
-/* Returns 1 if the 6 operands specified in OPERANDS are suitable for
-   use in fmpyadd instructions.  */
-int
-fmpyaddoperands (operands)
-     rtx *operands;
-{
-  enum machine_mode mode = GET_MODE (operands[0]);
-
-  /* Must be a floating point mode.  */
-  if (mode != SFmode && mode != DFmode)
-    return 0;
-
-  /* All modes must be the same.  */
-  if (! (mode == GET_MODE (operands[1])
-	 && mode == GET_MODE (operands[2])
-	 && mode == GET_MODE (operands[3])
-	 && mode == GET_MODE (operands[4])
-	 && mode == GET_MODE (operands[5])))
-    return 0;
-
-  /* All operands must be registers.  */
-  if (! (GET_CODE (operands[1]) == REG
-	 && GET_CODE (operands[2]) == REG
-	 && GET_CODE (operands[3]) == REG
-	 && GET_CODE (operands[4]) == REG
-	 && GET_CODE (operands[5]) == REG))
-    return 0;
-
-  /* Only 2 real operands to the addition.  One of the input operands must
-     be the same as the output operand.  */
-  if (! rtx_equal_p (operands[3], operands[4])
-      && ! rtx_equal_p (operands[3], operands[5]))
-    return 0;
-
-  /* Inout operand of add can not conflict with any operands from multiply.  */
-  if (rtx_equal_p (operands[3], operands[0])
-     || rtx_equal_p (operands[3], operands[1])
-     || rtx_equal_p (operands[3], operands[2]))
-    return 0;
-
-  /* multiply can not feed into addition operands.  */
-  if (rtx_equal_p (operands[4], operands[0])
-      || rtx_equal_p (operands[5], operands[0]))
-    return 0;
-
-  /* SFmode limits the registers to the upper 32 of the 32bit FP regs.  */
-  if (mode == SFmode
-      && (REGNO (operands[0]) < 57
-	  || REGNO (operands[1]) < 57
-	  || REGNO (operands[2]) < 57
-	  || REGNO (operands[3]) < 57
-	  || REGNO (operands[4]) < 57
-	  || REGNO (operands[5]) < 57))
-    return 0;
-
-  /* Passed.  Operands are suitable for fmpyadd.  */
-  return 1;
-}
-
-/* Returns 1 if the 6 operands specified in OPERANDS are suitable for
-   use in fmpysub instructions.  */
-int
-fmpysuboperands (operands)
-     rtx *operands;
-{
-  enum machine_mode mode = GET_MODE (operands[0]);
-
-  /* Must be a floating point mode.  */
-  if (mode != SFmode && mode != DFmode)
-    return 0;
-
-  /* All modes must be the same.  */
-  if (! (mode == GET_MODE (operands[1])
-	 && mode == GET_MODE (operands[2])
-	 && mode == GET_MODE (operands[3])
-	 && mode == GET_MODE (operands[4])
-	 && mode == GET_MODE (operands[5])))
-    return 0;
-
-  /* All operands must be registers.  */
-  if (! (GET_CODE (operands[1]) == REG
-	 && GET_CODE (operands[2]) == REG
-	 && GET_CODE (operands[3]) == REG
-	 && GET_CODE (operands[4]) == REG
-	 && GET_CODE (operands[5]) == REG))
-    return 0;
-
-  /* Only 2 real operands to the subtraction.  Subtraction is not a commutative
-     operation, so operands[4] must be the same as operand[3].  */
-  if (! rtx_equal_p (operands[3], operands[4]))
-    return 0;
-
-  /* multiply can not feed into subtraction.  */
-  if (rtx_equal_p (operands[5], operands[0]))
-    return 0;
-
-  /* Inout operand of sub can not conflict with any operands from multiply.  */
-  if (rtx_equal_p (operands[3], operands[0])
-     || rtx_equal_p (operands[3], operands[1])
-     || rtx_equal_p (operands[3], operands[2]))
-    return 0;
-
-  /* SFmode limits the registers to the upper 32 of the 32bit FP regs.  */
-  if (mode == SFmode
-      && (REGNO (operands[0]) < 57
-	  || REGNO (operands[1]) < 57
-	  || REGNO (operands[2]) < 57
-	  || REGNO (operands[3]) < 57
-	  || REGNO (operands[4]) < 57
-	  || REGNO (operands[5]) < 57))
-    return 0;
-
-  /* Passed.  Operands are suitable for fmpysub.  */
-  return 1;
-}
-
-int
-plus_xor_ior_operator (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
-	  || GET_CODE (op) == IOR);
-}
-
-/* Return 1 if the given constant is 2, 4, or 8.  These are the valid
-   constants for shadd instructions.  */
-static int
-shadd_constant_p (val)
-     int val;
-{
-  if (val == 2 || val == 4 || val == 8)
-    return 1;
-  else
-    return 0;
-}
-
-/* Return 1 if OP is a CONST_INT with the value 2, 4, or 8.  These are
-   the valid constant for shadd instructions.  */
-int
-shadd_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
-}
-
-/* Return 1 if OP is valid as a base register in a reg + reg address.  */
-
-int
-basereg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  /* cse will create some unscaled indexed addresses, however; it
-     generally isn't a win on the PA, so avoid creating unscaled
-     indexed addresses until after cse is finished.  */
-  if (!cse_not_expected)
-    return 0;
-
-  /* Once reload has started everything is considered valid.  Reload should
-     only create indexed addresses using the stack/frame pointer, and any
-     others were checked for validity when created by the combine pass. 
-
-     Also allow any register when TARGET_NO_SPACE_REGS is in effect since
-     we don't have to worry about the braindamaged implicit space register
-     selection using the basereg only (rather than effective address)
-     screwing us over.  */
-  if (TARGET_NO_SPACE_REGS || reload_in_progress || reload_completed)
-    return (GET_CODE (op) == REG);
-
-  /* Stack is always OK for indexing.  */
-  if (op == stack_pointer_rtx)
-    return 1;
-
-  /* While it's always safe to index off the frame pointer, it's not
-     always profitable, particularly when the frame pointer is being
-     eliminated.  */
-  if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
-    return 1;
-
-  /* The only other valid OPs are pseudo registers with
-     REGNO_POINTER_FLAG set.  */
-  if (GET_CODE (op) != REG
-      || REGNO (op) < FIRST_PSEUDO_REGISTER
-      || ! register_operand (op, mode))
-    return 0;
-    
-  return REGNO_POINTER_FLAG (REGNO (op));
-}
-
-/* Return 1 if this operand is anything other than a hard register.  */
-
-int
-non_hard_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
-}
-
-/* Return 1 if INSN branches forward.  Should be using insn_addresses
-   to avoid walking through all the insns... */
-static int
-forward_branch_p (insn)
-     rtx insn;
-{
-  rtx label = JUMP_LABEL (insn);
-
-  while (insn)
-    {
-      if (insn == label)
-	break;
-      else
-	insn = NEXT_INSN (insn);
-    }
-
-  return (insn == label);
-}
-
-/* Return 1 if OP is an equality comparison, else return 0.  */
-int
-eq_neq_comparison_operator (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
-}
-
-/* Return 1 if OP is an operator suitable for use in a movb instruction.  */
-int
-movb_comparison_operator (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == EQ || GET_CODE (op) == NE
-	  || GET_CODE (op) == LT || GET_CODE (op) == GE);
-}
-
-/* Return 1 if INSN is in the delay slot of a call instruction.  */
-int
-jump_in_call_delay (insn)
-     rtx insn;
-{
-
-  if (GET_CODE (insn) != JUMP_INSN)
-    return 0;
-
-  if (PREV_INSN (insn)
-      && PREV_INSN (PREV_INSN (insn))
-      && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
-    {
-      rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
-
-      return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
-	      && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
-
-    }
-  else
-    return 0;
-}
-
-/* Output an unconditional move and branch insn.  */
-
-char *
-output_parallel_movb (operands, length)
-     rtx *operands;
-     int length;
-{
-  /* These are the cases in which we win.  */
-  if (length == 4)
-    return "mov%I1b,tr %1,%0,%2";
-
-  /* None of these cases wins, but they don't lose either.  */
-  if (dbr_sequence_length () == 0)
-    {
-      /* Nothing in the delay slot, fake it by putting the combined
-	 insn (the copy or add) in the delay slot of a bl.  */
-      if (GET_CODE (operands[1]) == CONST_INT)
-	return "bl %2,0\n\tldi %1,%0";
-      else
-	return "bl %2,0\n\tcopy %1,%0";
-    }
-  else
-    {
-      /* Something in the delay slot, but we've got a long branch.  */
-      if (GET_CODE (operands[1]) == CONST_INT)
-	return "ldi %1,%0\n\tbl %2,0";
-      else
-	return "copy %1,%0\n\tbl %2,0";
-    }
-}
-
-/* Output an unconditional add and branch insn.  */
-
-char *
-output_parallel_addb (operands, length)
-     rtx *operands;
-     int length;
-{
-  /* To make life easy we want operand0 to be the shared input/output
-     operand and operand1 to be the readonly operand.  */
-  if (operands[0] == operands[1])
-    operands[1] = operands[2];
-
-  /* These are the cases in which we win.  */
-  if (length == 4)
-    return "add%I1b,tr %1,%0,%3";
-
-  /* None of these cases win, but they don't lose either.  */
-  if (dbr_sequence_length () == 0)
-    {
-      /* Nothing in the delay slot, fake it by putting the combined
-	 insn (the copy or add) in the delay slot of a bl.  */
-      return "bl %3,0\n\tadd%I1 %1,%0,%0";
-    }
-  else
-    {
-      /* Something in the delay slot, but we've got a long branch.  */
-      return "add%I1 %1,%0,%0\n\tbl %3,0";
-    }
-}
-
-/* Return nonzero if INSN (a jump insn) immediately follows a call to
-   a named function.  This is used to discourage creating parallel movb/addb
-   insns since a jump which immediately follows a call can execute in the
-   delay slot of the call.
-
-   It is also used to avoid filling the delay slot of a jump which
-   immediately follows a call since the jump can usually be eliminated
-   completely by modifying RP in the delay slot of the call.  */
-   
-int
-following_call (insn)
-     rtx insn;
-{
-  /* CYGNUS LOCAL PA8000/law */
-  /* We do not parallel movb,addb or place jumps into call delay slots when
-     optimizing for the PA8000.  */
-  if (pa_cpu != PROCESSOR_8000)
-    return 0;
-  /* END CYGNUS LOCAL */
-
-  /* Find the previous real insn, skipping NOTEs.  */
-  insn = PREV_INSN (insn);
-  while (insn && GET_CODE (insn) == NOTE)
-    insn = PREV_INSN (insn);
-
-  /* Check for CALL_INSNs and millicode calls.  */
-  if (insn
-      && ((GET_CODE (insn) == CALL_INSN
-	   && get_attr_type (insn) != TYPE_DYNCALL)
-	  || (GET_CODE (insn) == INSN
-	      && GET_CODE (PATTERN (insn)) != SEQUENCE
-	      && GET_CODE (PATTERN (insn)) != USE
-	      && GET_CODE (PATTERN (insn)) != CLOBBER
-	      && get_attr_type (insn) == TYPE_MILLI)))
-    return 1;
-
-  return 0;
-}
-
-/* Restore any INSN_CODEs for insns with unscaled indexed addresses since
-   the INSN_CODE might be clobberd by rerecognition triggered by reorg.  */
-
-static void
-restore_unscaled_index_insn_codes (insns)
-     rtx insns;
-{
-  rtx insn;
-
-  for (insn = insns; insn; insn = NEXT_INSN (insn))
-    {
-      if (INSN_UID (insn) < max_unscaled_index_insn_codes_uid
-	  && unscaled_index_insn_codes[INSN_UID (insn)] != -1)
-	INSN_CODE (insn) = unscaled_index_insn_codes[INSN_UID (insn)];
-    }
-}
-
-/* Severe braindamage:
-
-   On the PA, address computations within MEM expressions are not
-   commutative because of the implicit space register selection
-   from the base register (instead of the entire effective address).
-
-   Because of this mis-feature we have to know which register in a reg+reg
-   address is the base and which is the index.
-
-   Before reload, the base can be identified by REGNO_POINTER_FLAG.  We use
-   this to force base + index addresses to match a different insn than
-   index + base addresses.
-
-   We assume that no pass during or after reload creates new unscaled indexed
-   addresses, so any unscaled indexed address we find after reload must have
-   at one time been recognized a base + index or index + base and we accept
-   any register as a base register.
-
-   This scheme assumes that no pass during/after reload will rerecognize an
-   insn with an unscaled indexed address.  This failed due to a reorg call
-   to rerecognize certain insns.
-
-   So, we record if an insn uses an unscaled indexed address and which
-   register is the base (via recording of the INSN_CODE for such insns).
-
-   Just before we output code for the function, we make sure all the insns
-   using unscaled indexed addresses have the same INSN_CODE as they did
-   immediately before delay slot scheduling.
-
-   This is extremely gross.  Long term, I'd like to be able to look at
-   REG_POINTER_FLAG to handle these kinds of problems.  */
- 
-static void
-record_unscaled_index_insn_codes (insns)
-     rtx insns;
-{
-  rtx insn;
-
-  max_unscaled_index_insn_codes_uid = get_max_uid ();
-  unscaled_index_insn_codes
-    = (int *)xmalloc (max_unscaled_index_insn_codes_uid * sizeof (int));
-  memset (unscaled_index_insn_codes, -1,
-	  max_unscaled_index_insn_codes_uid * sizeof (int));
-
-  for (insn = insns; insn; insn = NEXT_INSN (insn))
-    {
-      rtx set = single_set (insn);
-      rtx mem = NULL_RTX;
-
-      /* Ignore anything that isn't a normal SET.  */
-      if (set == NULL_RTX)
-	continue;
-
-      /* No insns can have more than one MEM.  */
-      if (GET_CODE (SET_SRC (set)) == MEM)
-	mem = SET_SRC (set);
-
-      if (GET_CODE (SET_DEST (set)) == MEM)
-	mem = SET_DEST (set);
-	
-      /* If neither operand is a mem, then there's nothing to do.  */
-      if (mem == NULL_RTX)
-	continue;
-
-      if (GET_CODE (XEXP (mem, 0)) != PLUS)
-	continue;
-
-      /* If both are REGs (or SUBREGs), then record the insn code for
-	 this insn.  */
-      if (REG_P (XEXP (XEXP (mem, 0), 0)) && REG_P (XEXP (XEXP (mem, 0), 1)))
-        unscaled_index_insn_codes[INSN_UID (insn)] = INSN_CODE (insn);
-    }
-}
-
-/* We use this hook to perform a PA specific optimization which is difficult
-   to do in earlier passes.
-
-   We want the delay slots of branches within jump tables to be filled.
-   None of the compiler passes at the moment even has the notion that a
-   PA jump table doesn't contain addresses, but instead contains actual
-   instructions!
-
-   Because we actually jump into the table, the addresses of each entry
-   must stay constant in relation to the beginning of the table (which
-   itself must stay constant relative to the instruction to jump into
-   it).  I don't believe we can guarantee earlier passes of the compiler
-   will adhere to those rules.
-
-   So, late in the compilation process we find all the jump tables, and
-   expand them into real code -- eg each entry in the jump table vector
-   will get an appropriate label followed by a jump to the final target.
-
-   Reorg and the final jump pass can then optimize these branches and
-   fill their delay slots.  We end up with smaller, more efficient code.
-
-   The jump instructions within the table are special; we must be able 
-   to identify them during assembly output (if the jumps don't get filled
-   we need to emit a nop rather than nullifying the delay slot)).  We
-   identify jumps in switch tables by marking the SET with DImode. 
-
-   We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
-   insns.  This serves two purposes, first it prevents jump.c from
-   noticing that the last N entries in the table jump to the instruction
-   immediately after the table and deleting the jumps.  Second, those
-   insns mark where we should emit .begin_brtab and .end_brtab directives
-   when using GAS (allows for better link time optimizations).  */
-
-void
-pa_reorg (insns)
-     rtx insns;
-{
-  rtx insn;
-
-  /* Keep track of which insns have unscaled indexed addresses, and which
-     register is the base address in such insns.  */
-  record_unscaled_index_insn_codes (insns);
-
-  remove_useless_addtr_insns (insns, 1);
-
-  /* CYGNUS LOCAL PA8000/law */
-  /* These optimizations hurt PA8000 performance.  */
-  if (pa_cpu != PROCESSOR_8000)
-    pa_combine_instructions (get_insns ());
-  /* END CYGNUS LOCAL */
-
-  /* This is fairly cheap, so always run it if optimizing.  */
-  if (optimize > 0 && !TARGET_BIG_SWITCH)
-    {
-      /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns.  */
-      insns = get_insns ();
-      for (insn = insns; insn; insn = NEXT_INSN (insn))
-	{
-	  rtx pattern, tmp, location;
-	  unsigned int length, i;
-
-	  /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode.  */
-	  if (GET_CODE (insn) != JUMP_INSN
-	      || (GET_CODE (PATTERN (insn)) != ADDR_VEC
-		  && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
-	    continue;
-
-	  /* Emit marker for the beginning of the branch table.  */
-	  emit_insn_before (gen_begin_brtab (), insn);
-
-	  pattern = PATTERN (insn);
-	  location = PREV_INSN (insn);
-          length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
-
-	  for (i = 0; i < length; i++)
-	    {
-	      /* Emit a label before each jump to keep jump.c from
-		 removing this code.  */
-	      tmp = gen_label_rtx ();
-	      LABEL_NUSES (tmp) = 1;
-	      emit_label_after (tmp, location);
-	      location = NEXT_INSN (location);
-
-	      if (GET_CODE (pattern) == ADDR_VEC)
-		{
-		  /* Emit the jump itself.  */
-		  tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
-		  tmp = emit_jump_insn_after (tmp, location);
-		  JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
-		  /* It is easy to rely on the branch table markers
-		     during assembly output to trigger the correct code
-		     for a switch table jump with an unfilled delay slot,
-
-		     However, that requires state and assumes that we look
-		     at insns in order.
-
-		     We can't make such assumptions when computing the length
-		     of instructions.  Ugh.  We could walk the insn chain to
-		     determine if this instruction is in a branch table, but
-		     that can get rather expensive, particularly during the
-		     branch shortening phase of the compiler.
-
-		     So instead we mark this jump as being special.  This is
-		     far from ideal and knows that no code after this will
-		     muck around with the mode of the JUMP_INSN itself.  */
-		  PUT_MODE (tmp, SImode);
-		  LABEL_NUSES (JUMP_LABEL (tmp))++;
-		  location = NEXT_INSN (location);
-		}
-	      else
-		{
-		  /* Emit the jump itself.  */
-		  tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
-		  tmp = emit_jump_insn_after (tmp, location);
-		  JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
-		  /* It is easy to rely on the branch table markers
-		     during assembly output to trigger the correct code
-		     for a switch table jump with an unfilled delay slot,
-
-		     However, that requires state and assumes that we look
-		     at insns in order.
-
-		     We can't make such assumptions when computing the length
-		     of instructions.  Ugh.  We could walk the insn chain to
-		     determine if this instruction is in a branch table, but
-		     that can get rather expensive, particularly during the
-		     branch shortening phase of the compiler.
-
-		     So instead we mark this jump as being special.  This is
-		     far from ideal and knows that no code after this will
-		     muck around with the mode of the JUMP_INSN itself.  */
-		  PUT_MODE (tmp, SImode);
-		  LABEL_NUSES (JUMP_LABEL (tmp))++;
-		  location = NEXT_INSN (location);
-		}
-
-	      /* Emit a BARRIER after the jump.  */
-	      emit_barrier_after (location);
-	      location = NEXT_INSN (location);
-	    }
-
-	  /* Emit marker for the end of the branch table.  */
-	  emit_insn_before (gen_end_brtab (), location);
-	  location = NEXT_INSN (location);
-	  emit_barrier_after (location);
-
-	  /* Delete the ADDR_VEC or ADDR_DIFF_VEC.  */
-	  delete_insn (insn);
-	}
-    }
-  else
-    {
-      /* Sill need an end_brtab insn.  */
-      insns = get_insns ();
-      for (insn = insns; insn; insn = NEXT_INSN (insn))
-	{
-	  /* Find an ADDR_VEC insn.  */
-	  if (GET_CODE (insn) != JUMP_INSN
-	      || (GET_CODE (PATTERN (insn)) != ADDR_VEC
-		  && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
-	    continue;
-
-	  /* Now generate markers for the beginning and end of the
-	     branch table.  */
-	  emit_insn_before (gen_begin_brtab (), insn);
-	  emit_insn_after (gen_end_brtab (), insn);
-	}
-    }
-}
-
-/* The PA has a number of odd instructions which can perform multiple
-   tasks at once.  On first generation PA machines (PA1.0 and PA1.1)
-   it may be profitable to combine two instructions into one instruction
-   with two outputs.  It's not profitable PA2.0 machines because the
-   two outputs would take two slots in the reorder buffers.
-
-   This routine finds instructions which can be combined and combines
-   them.  We only support some of the potential combinations, and we
-   only try common ways to find suitable instructions.
-
-      * addb can add two registers or a register and a small integer
-      and jump to a nearby (+-8k) location.  Normally the jump to the
-      nearby location is conditional on the result of the add, but by
-      using the "true" condition we can make the jump unconditional.
-      Thus addb can perform two independent operations in one insn.
-
-      * movb is similar to addb in that it can perform a reg->reg
-      or small immediate->reg copy and jump to a nearby (+-8k location).
-
-      * fmpyadd and fmpysub can perform a FP multiply and either an
-      FP add or FP sub if the operands of the multiply and add/sub are
-      independent (there are other minor restrictions).  Note both
-      the fmpy and fadd/fsub can in theory move to better spots according
-      to data dependencies, but for now we require the fmpy stay at a
-      fixed location.
-
-      * Many of the memory operations can perform pre & post updates
-      of index registers.  GCC's pre/post increment/decrement addressing
-      is far too simple to take advantage of all the possibilities.  This
-      pass may not be suitable since those insns may not be independent.
-
-      * comclr can compare two ints or an int and a register, nullify
-      the following instruction and zero some other register.  This
-      is more difficult to use as it's harder to find an insn which
-      will generate a comclr than finding something like an unconditional
-      branch.  (conditional moves & long branches create comclr insns).
-
-      * Most arithmetic operations can conditionally skip the next
-      instruction.  They can be viewed as "perform this operation
-      and conditionally jump to this nearby location" (where nearby
-      is an insns away).  These are difficult to use due to the
-      branch length restrictions.  */
-
-static void
-pa_combine_instructions (insns)
-     rtx insns ATTRIBUTE_UNUSED;
-{
-  rtx anchor, new;
-
-  /* This can get expensive since the basic algorithm is on the
-     order of O(n^2) (or worse).  Only do it for -O2 or higher
-     levels of optimization.  */
-  if (optimize < 2)
-    return;
-
-  /* Walk down the list of insns looking for "anchor" insns which
-     may be combined with "floating" insns.  As the name implies,
-     "anchor" instructions don't move, while "floating" insns may
-     move around.  */
-  new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
-  new = make_insn_raw (new);
-
-  for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
-    {
-      enum attr_pa_combine_type anchor_attr;
-      enum attr_pa_combine_type floater_attr;
-
-      /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
-	 Also ignore any special USE insns.  */
-      if ((GET_CODE (anchor) != INSN
-	  && GET_CODE (anchor) != JUMP_INSN
-	  && GET_CODE (anchor) != CALL_INSN)
-	  || GET_CODE (PATTERN (anchor)) == USE
-	  || GET_CODE (PATTERN (anchor)) == CLOBBER
-	  || GET_CODE (PATTERN (anchor)) == ADDR_VEC
-	  || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
-	continue;
-
-      anchor_attr = get_attr_pa_combine_type (anchor);
-      /* See if anchor is an insn suitable for combination.  */
-      if (anchor_attr == PA_COMBINE_TYPE_FMPY
-	  || anchor_attr == PA_COMBINE_TYPE_FADDSUB
-	  || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
-	      && ! forward_branch_p (anchor)))
-	{
-	  rtx floater;
-
-	  for (floater = PREV_INSN (anchor);
-	       floater;
-	       floater = PREV_INSN (floater))
-	    {
-	      if (GET_CODE (floater) == NOTE
-		  || (GET_CODE (floater) == INSN
-		      && (GET_CODE (PATTERN (floater)) == USE
-			  || GET_CODE (PATTERN (floater)) == CLOBBER)))
-		continue;
-
-	      /* Anything except a regular INSN will stop our search.  */
-	      if (GET_CODE (floater) != INSN
-		  || GET_CODE (PATTERN (floater)) == ADDR_VEC
-		  || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
-		{
-		  floater = NULL_RTX;
-		  break;
-		}
-
-	      /* See if FLOATER is suitable for combination with the
-		 anchor.  */
-	      floater_attr = get_attr_pa_combine_type (floater);
-	      if ((anchor_attr == PA_COMBINE_TYPE_FMPY
-		   && floater_attr == PA_COMBINE_TYPE_FADDSUB)
-		  || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
-		      && floater_attr == PA_COMBINE_TYPE_FMPY))
-		{
-		  /* If ANCHOR and FLOATER can be combined, then we're
-		     done with this pass.  */
-		  if (pa_can_combine_p (new, anchor, floater, 0,
-					SET_DEST (PATTERN (floater)),
-					XEXP (SET_SRC (PATTERN (floater)), 0),
-					XEXP (SET_SRC (PATTERN (floater)), 1)))
-		    break;
-		}
-
-	      else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
-		       && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
-		{
-		  if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
-		    {
-		      if (pa_can_combine_p (new, anchor, floater, 0,
-					    SET_DEST (PATTERN (floater)),
-					XEXP (SET_SRC (PATTERN (floater)), 0),
-					XEXP (SET_SRC (PATTERN (floater)), 1)))
-			break;
-		    }
-		  else
-		    {
-		      if (pa_can_combine_p (new, anchor, floater, 0,
-					    SET_DEST (PATTERN (floater)),
-					    SET_SRC (PATTERN (floater)),
-					    SET_SRC (PATTERN (floater))))
-			break;
-		    }
-		}
-	    }
-
-	  /* If we didn't find anything on the backwards scan try forwards.  */
-	  if (!floater
-	      && (anchor_attr == PA_COMBINE_TYPE_FMPY
-		  || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
-	    {
-	      for (floater = anchor; floater; floater = NEXT_INSN (floater))
-		{
-		  if (GET_CODE (floater) == NOTE
-		      || (GET_CODE (floater) == INSN
-			  && (GET_CODE (PATTERN (floater)) == USE
-			      || GET_CODE (PATTERN (floater)) == CLOBBER)))
-			
-		    continue;
-
-		  /* Anything except a regular INSN will stop our search.  */
-		  if (GET_CODE (floater) != INSN
-		      || GET_CODE (PATTERN (floater)) == ADDR_VEC
-		      || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
-		    {
-		      floater = NULL_RTX;
-		      break;
-		    }
-
-		  /* See if FLOATER is suitable for combination with the
-		     anchor.  */
-		  floater_attr = get_attr_pa_combine_type (floater);
-		  if ((anchor_attr == PA_COMBINE_TYPE_FMPY
-		       && floater_attr == PA_COMBINE_TYPE_FADDSUB)
-		      || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
-			  && floater_attr == PA_COMBINE_TYPE_FMPY))
-		    {
-		      /* If ANCHOR and FLOATER can be combined, then we're
-			 done with this pass.  */
-		      if (pa_can_combine_p (new, anchor, floater, 1,
-					    SET_DEST (PATTERN (floater)),
-					    XEXP (SET_SRC (PATTERN(floater)),0),
-					    XEXP(SET_SRC(PATTERN(floater)),1)))
-			break;
-		    }
-		}
-	    }
-
-	  /* FLOATER will be nonzero if we found a suitable floating
-	     insn for combination with ANCHOR.  */
-	  if (floater
-	      && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
-		  || anchor_attr == PA_COMBINE_TYPE_FMPY))
-	    {
-	      /* Emit the new instruction and delete the old anchor.  */
-	      emit_insn_before (gen_rtx_PARALLEL (VOIDmode,
-						  gen_rtvec (2,
-							     PATTERN (anchor),
-							     PATTERN (floater))),
-						  anchor);
-	      PUT_CODE (anchor, NOTE);
-	      NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
-	      NOTE_SOURCE_FILE (anchor) = 0;
-
-	      /* Emit a special USE insn for FLOATER, then delete
-		 the floating insn.  */
-	      emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
-	      delete_insn (floater);
-
-	      continue;
-	    }
-	  else if (floater
-		   && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
-	    {
-	      rtx temp;
-	      /* Emit the new_jump instruction and delete the old anchor.  */
-	      temp = emit_jump_insn_before (gen_rtx_PARALLEL (VOIDmode,
-					      gen_rtvec (2, PATTERN (anchor),
-							 PATTERN (floater))),
-				anchor);
-	      JUMP_LABEL (temp) = JUMP_LABEL (anchor);
-	      PUT_CODE (anchor, NOTE);
-	      NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
-	      NOTE_SOURCE_FILE (anchor) = 0;
-
-	      /* Emit a special USE insn for FLOATER, then delete
-		 the floating insn.  */
-	      emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
-	      delete_insn (floater);
-	      continue;
-	    }
-	}
-    }
-}
-
-int
-pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
-     rtx new, anchor, floater;
-     int reversed;
-     rtx dest, src1, src2;
-{
-  int insn_code_number;
-  rtx start, end;
-
-  /* Create a PARALLEL with the patterns of ANCHOR and
-     FLOATER, try to recognize it, then test constraints
-     for the resulting pattern.
-
-     If the pattern doesn't match or the constraints
-     aren't met keep searching for a suitable floater
-     insn.  */
-  XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
-  XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
-  INSN_CODE (new) = -1;
-  insn_code_number = recog_memoized (new);
-  if (insn_code_number < 0
-      || !constrain_operands (insn_code_number, 1))
-    return 0;
-
-  if (reversed)
-    {
-      start = anchor;
-      end = floater;
-    }
-  else
-    {
-      start = floater;
-      end = anchor;
-    }
-
-  /* There's up to three operands to consider.  One
-     output and two inputs.
-
-     The output must not be used between FLOATER & ANCHOR
-     exclusive.  The inputs must not be set between
-     FLOATER and ANCHOR exclusive.  */
-
-  if (reg_used_between_p (dest, start, end))
-    return 0;
-
-  if (reg_set_between_p (src1, start, end))
-    return 0;
-
-  if (reg_set_between_p (src2, start, end))
-    return 0;
-
-  /* If we get here, then everything is good.  */
-  return 1;
-}
-
-/* Return nonzero if sets and references for INSN are delayed.
-
-   Millicode insns are actually function calls with some special
-   constraints on arguments and register usage.
-
-   Millicode calls always expect their arguments in the integer argument
-   registers, and always return their result in %r29 (ret1).  They
-   are expected to clobber their arguments, %r1, %r29, and %r31 and
-   nothing else.
-
-   By considering this effects delayed reorg reorg can put insns
-   which set the argument registers into the delay slot of the millicode
-   call -- thus they act more like traditional CALL_INSNs.
-
-   get_attr_type will try to recognize the given insn, so make sure to
-   filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
-   in particular.  */
-int
-insn_sets_and_refs_are_delayed (insn)
-     rtx insn;
-{
-  return ((GET_CODE (insn) == INSN 
-	   && GET_CODE (PATTERN (insn)) != SEQUENCE
-	   && GET_CODE (PATTERN (insn)) != USE
-	   && GET_CODE (PATTERN (insn)) != CLOBBER
-	   && get_attr_type (insn) == TYPE_MILLI));
-}
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
deleted file mode 100755
index a63d955..0000000
--- a/gcc/config/pa/pa.h
+++ /dev/null
@@ -1,2601 +0,0 @@
-/* Definitions of target machine for GNU compiler, for the HP Spectrum.
-   Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
-   and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
-   Software Science at the University of Utah.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-enum cmp_type				/* comparison type */
-{
-  CMP_SI,				/* compare integers */
-  CMP_SF,				/* compare single precision floats */
-  CMP_DF,				/* compare double precision floats */
-  CMP_MAX				/* max comparison type */
-};
-
-/* For long call handling.  */
-extern unsigned int total_code_bytes;
-
-/* Which processor to schedule for.  */
-
-enum processor_type
-{
-  PROCESSOR_700,
-  PROCESSOR_7100,
-  PROCESSOR_7100LC,
-  PROCESSOR_7200,
-  /* CYGNUS LOCAL PA8000/law */
-  PROCESSOR_8000
-  /* END CYGNUS LCOAL */
-};
-
-/* For -mschedule= option.  */
-extern char *pa_cpu_string;
-extern enum processor_type pa_cpu;
-
-#define pa_cpu_attr ((enum attr_cpu)pa_cpu)
-
-/* CYGNUS LOCAL PA8000/law */
-/* The 700 can only issue a single insn at a time.
-   The 7XXX processors can issue two insns at a time.  */
-#define ISSUE_RATE \
-  (pa_cpu == PROCESSOR_700 ? 1 : pa_cpu == PROCESSOR_8000 ? 4 : 2)
-/* END CYGNUS LOCAL */
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fputs (" (hppa)", stderr);
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* compile code for HP-PA 1.1 ("Snake") */
-
-#define TARGET_SNAKE (target_flags & 1)
-
-/* Disable all FP registers (they all become fixed).  This may be necessary
-   for compiling kernels which perform lazy context switching of FP regs.
-   Note if you use this option and try to perform floating point operations
-   the compiler will abort!  */
-
-#define TARGET_DISABLE_FPREGS (target_flags & 2)
-
-/* Generate code which assumes that calls through function pointers will
-   never cross a space boundary.  Such assumptions are generally safe for
-   building kernels and statically linked executables.  Code compiled with
-   this option will fail miserably if the executable is dynamically linked
-   or uses nested functions!
-
-   This is also used to trigger aggressive unscaled index addressing.  */
-#define TARGET_NO_SPACE_REGS (target_flags & 4)
-
-/* Allow unconditional jumps in the delay slots of call instructions.  */
-#define TARGET_JUMP_IN_DELAY (target_flags & 8)
-
-/* Optimize for space.  Currently this only turns on out of line
-   prologues and epilogues.  */
-#define TARGET_SPACE (target_flags & 16)
-
-/* Disable indexed addressing modes.  */
-
-#define TARGET_DISABLE_INDEXING (target_flags & 32)
-
-/* Emit code which follows the new portable runtime calling conventions
-   HP wants everyone to use for ELF objects.  If at all possible you want
-   to avoid this since it's a performance loss for non-prototyped code.
-
-   Note TARGET_PORTABLE_RUNTIME also forces all calls to use inline
-   long-call stubs which is quite expensive.  */
-
-#define TARGET_PORTABLE_RUNTIME (target_flags & 64)
-
-/* Emit directives only understood by GAS.  This allows parameter
-   relocations to work for static functions.  There is no way
-   to make them work the HP assembler at this time.  */
-
-#define TARGET_GAS (target_flags & 128)
-
-/* Emit code for processors which do not have an FPU.  */
-
-#define TARGET_SOFT_FLOAT (target_flags & 256)
-
-/* Use 3-insn load/store sequences for access to large data segments
-   in shared libraries on hpux10.  */
-#define TARGET_LONG_LOAD_STORE (target_flags & 512)
-
-/* Use a faster sequence for indirect calls.  */
-#define TARGET_FAST_INDIRECT_CALLS (target_flags & 1024)
-
-/* Generate code with big switch statements to avoid out of range branches
-   occurring within the switch table.  */
-#define TARGET_BIG_SWITCH (target_flags & 2048)
-
-/* CYGNUS LOCAL pa8000/law */
-/* Generate PA2.0 instructions.  */
-#define TARGET_PARISC_2_0 (target_flags & 4096)
-/* END CYGNUS LOCAL */
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES \
-  {{"snake", 1},		\
-   {"nosnake", -1},		\
-   {"pa-risc-1-0", -1},		\
-   {"pa-risc-1-1", 1},		\
-   {"disable-fpregs", 2},	\
-   {"no-disable-fpregs", -2},	\
-   {"no-space-regs", 4},	\
-   {"space-regs", -4},		\
-   {"jump-in-delay", 8},	\
-   {"no-jump-in-delay", -8},	\
-   {"space", 16},		\
-   {"no-space", -16},		\
-   {"disable-indexing", 32},	\
-   {"no-disable-indexing", -32},\
-   {"portable-runtime", 64},	\
-   {"no-portable-runtime", -64},\
-   {"gas", 128},		\
-   {"no-gas", -128},		\
-   {"soft-float", 256},		\
-   {"no-soft-float", -256},	\
-   {"long-load-store", 512},	\
-   {"no-long-load-store", -512},\
-   {"fast-indirect-calls", 1024},\
-   {"no-fast-indirect-calls", -1024},\
-   {"big-switch", 2048},	\
-   {"no-big-switch", -2048},	\
-   /* CYGNUS LOCAL pa8000/law */\
-   {"pa-risc-2-0", 4097},	\
-   {"no-pa-risc-2-0", -4096},	\
-   /* END CYGNUS LOCAL */	\
-   {"linker-opt", 0},		\
-   { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}}
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 0x88		/* TARGET_GAS + TARGET_JUMP_IN_DELAY */
-#endif
-
-#ifndef TARGET_CPU_DEFAULT
-#define TARGET_CPU_DEFAULT 0
-#endif
-
-#define TARGET_OPTIONS			\
-{					\
-  { "schedule=",	&pa_cpu_string }\
-}
-
-#define OVERRIDE_OPTIONS override_options ()
-
-#define DBX_DEBUGGING_INFO
-#define DEFAULT_GDB_EXTENSIONS 1
-
-/* This is the way other stabs-in-XXX tools do things.  We will be
-   compatible.  */
-#define DBX_BLOCKS_FUNCTION_RELATIVE 1
-
-/* Likewise for linenos.
-
-   We make the first line stab special to avoid adding several
-   gross hacks to GAS.  */
-#undef  ASM_OUTPUT_SOURCE_LINE
-#define ASM_OUTPUT_SOURCE_LINE(file, line)		\
-  { static int sym_lineno = 1;				\
-    static tree last_function_decl = NULL;		\
-    if (current_function_decl == last_function_decl)	\
-      fprintf (file, "\t.stabn 68,0,%d,L$M%d-%s\nL$M%d:\n",	\
-	       line, sym_lineno,			\
-	       XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0) + 1, \
-	       sym_lineno);				\
-    else						\
-      fprintf (file, "\t.stabn 68,0,%d,0\n", line);	\
-    last_function_decl = current_function_decl;		\
-    sym_lineno += 1; }
-
-/* But, to make this work, we have to output the stabs for the function
-   name *first*...  */
-#define DBX_FUNCTION_FIRST
-
-/* Only labels should ever begin in column zero.  */
-#define ASM_STABS_OP "\t.stabs"
-#define ASM_STABN_OP "\t.stabn"
-
-/* GDB always assumes the current function's frame begins at the value
-   of the stack pointer upon entry to the current function.  Accessing
-   local variables and parameters passed on the stack is done using the
-   base of the frame + an offset provided by GCC.
-
-   For functions which have frame pointers this method works fine;
-   the (frame pointer) == (stack pointer at function entry) and GCC provides
-   an offset relative to the frame pointer.
-
-   This loses for functions without a frame pointer; GCC provides an offset
-   which is relative to the stack pointer after adjusting for the function's
-   frame size.  GDB would prefer the offset to be relative to the value of
-   the stack pointer at the function's entry.  Yuk!  */
-#define DEBUGGER_AUTO_OFFSET(X) \
-  ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
-    + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
-
-#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
-  ((GET_CODE (X) == PLUS ? OFFSET : 0) \
-    + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
-
-/* gdb needs a null N_SO at the end of each file for scattered loading. */
-
-#undef	DBX_OUTPUT_MAIN_SOURCE_FILE_END
-#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME) \
-  text_section (); \
-  if (!TARGET_PORTABLE_RUNTIME) \
-    fputs ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n", FILE); \
-  else \
-    fprintf (FILE, "%s\n", TEXT_SECTION_ASM_OP); \
-  fprintf (FILE,							\
-	   "\t.stabs \"\",%d,0,0,L$text_end0000\nL$text_end0000:\n", N_SO)
-
-/* CYGNUS LOCAL hpux11/law */
-#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 1) == 0
-#define CPP_SPEC "%{msnake:-D__hp9000s700 -D_PA_RISC1_1}\
- %{mpa-risc-1-1:-D__hp9000s700 -D_PA_RISC1_1}\
- %{!ansi: -D_HPUX_SOURCE -D_HIUX_SOURCE -D__STDC_EXT__}\
- %{threads:-D_REENTRANT -D_DCE_THREADS}"
-#else
-#define CPP_SPEC "%{!mpa-risc-1-0:%{!mnosnake:%{!msoft-float:-D__hp9000s700 -D_PA_RISC1_1}}} \
- %{!ansi: -D_HPUX_SOURCE -D_HIUX_SOURCE -D__STDC_EXT__}\
- %{threads:-D_REENTRANT -D_DCE_THREADS}"
-#endif
-/* END CYGNUS LOCAL */
-
-/* Defines for a K&R CC */
-
-#define CC1_SPEC "%{pg:} %{p:}"
-
-#define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}"
-
-/* We don't want -lg.  */
-#ifndef LIB_SPEC
-#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
-#endif
-
-/* Make gcc agree with <machine/ansi.h> */
-
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-#define WCHAR_TYPE "unsigned int"
-#define WCHAR_TYPE_SIZE 32
-
-/* Show we can debug even without a frame pointer.  */
-#define CAN_DEBUG_WITHOUT_FP
-
-/* Machine dependent reorg pass.  */
-#define MACHINE_DEPENDENT_REORG(X) pa_reorg(X)
-
-/* Prototype function used in MACHINE_DEPENDENT_REORG macro. */
-void pa_reorg ();
-
-/* Prototype function used in various macros. */
-int symbolic_operand ();
-
-/* Used in insn-*.c. */
-int following_call ();
-int function_label_operand ();
-int lhs_lshift_cint_operand ();
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dhppa -Dhp9000s800 -D__hp9000s800 -Dhp9k8 -Dunix -Dhp9000 -Dhp800 -Dspectrum -DREVARGV -Asystem(unix) -Asystem(bsd) -Acpu(hppa) -Amachine(hppa)"
-
-/* HPUX has a program 'chatr' to list the dependencies of dynamically
-   linked executables and shared libraries.  */
-#define LDD_SUFFIX "chatr"
-/* Look for lines like "dynamic   /usr/lib/X11R5/libX11.sl"
-   or "static    /usr/lib/X11R5/libX11.sl". 
-
-   HPUX 10.20 also has lines like "static branch prediction ..."
-   so we filter that out explicitly.
-
-   We also try to bound our search for libraries with marker
-   lines.  What a pain.  */
-#define PARSE_LDD_OUTPUT(PTR)					\
-do {								\
-  static int in_shlib_list = 0;					\
-  while (*PTR == ' ') PTR++;					\
-  if (strncmp (PTR, "shared library list:",			\
-	       sizeof ("shared library list:") - 1) == 0)	\
-    {								\
-      PTR = 0;							\
-      in_shlib_list = 1;					\
-    }								\
-  else if (strncmp (PTR, "shared library binding:",		\
-		    sizeof ("shared library binding:") - 1) == 0)\
-    {								\
-      PTR = 0;							\
-      in_shlib_list = 0;					\
-    }								\
-  else if (strncmp (PTR, "static branch prediction disabled",	\
-		    sizeof ("static branch prediction disabled") - 1) == 0)\
-    {								\
-      PTR = 0;							\
-      in_shlib_list = 0;					\
-    }								\
-  else if (in_shlib_list					\
-	   &&  strncmp (PTR, "dynamic", sizeof ("dynamic") - 1) == 0) \
-    {								\
-      PTR += sizeof ("dynamic") - 1;				\
-      while (*p == ' ') PTR++;					\
-    }								\
-  else if (in_shlib_list					\
-	   && strncmp (PTR, "static", sizeof ("static") - 1) == 0) \
-    {								\
-      PTR += sizeof ("static") - 1;				\
-      while (*p == ' ') PTR++;					\
-    }								\
-  else								\
-    PTR = 0;							\
-} while (0)
-
-/* target machine storage layout */
-
-/* Define for cross-compilation from a host with a different float format
-   or endianness (e.g. VAX, x86).  */
-#define REAL_ARITHMETIC
-
-/* Define this macro if it is advisable to hold scalars in registers
-   in a wider mode than that declared by the program.  In such cases, 
-   the value is constrained to be within the bounds of the declared
-   type, but kept valid in the wider mode.  The signedness of the
-   extension may differ from that of the type.  */
-
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)  \
-  if (GET_MODE_CLASS (MODE) == MODE_INT	\
-      && GET_MODE_SIZE (MODE) < 4)  	\
-    (MODE) = SImode;
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.  */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is true on the HP-PA.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Largest alignment required for any stack parameter, in bits.
-   Don't define this if it is equal to PARM_BOUNDARY */
-#define MAX_PARM_BOUNDARY 64
-
-/* Boundary (in *bits*) on which stack pointer is always aligned;
-   certain optimizations in combine depend on this.
-
-   GCC for the PA always rounds its stacks to a 512bit boundary,
-   but that happens late in the compilation process.  */
-#define STACK_BOUNDARY 64
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 64
-
-/* The .align directive in the HP assembler allows up to a 32 alignment.  */
-#define MAX_OFILE_ALIGNMENT 32768
-
-/* Get around hp-ux assembler bug, and make strcpy of constants fast. */
-#define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
-  ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   HP-PA 1.0 has 32 fullword registers and 16 floating point
-   registers. The floating point registers hold either word or double
-   word values.
-
-   16 additional registers are reserved.
-
-   HP-PA 1.1 has 32 fullword registers and 32 floating point
-   registers. However, the floating point registers behave
-   differently: the left and right halves of registers are addressable
-   as 32 bit registers. So, we will set things up like the 68k which
-   has different fp units: define separate register sets for the 1.0
-   and 1.1 fp units. */
-
-#define FIRST_PSEUDO_REGISTER 89  /* 32 general regs + 56 fp regs +
-				     + 1 shift reg */
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   On the HP-PA, these are:
-   Reg 0	= 0 (hardware). However, 0 is used for condition code,
-                  so is not fixed.
-   Reg 1	= ADDIL target/Temporary (hardware).
-   Reg 2	= Return Pointer
-   Reg 3	= Frame Pointer
-   Reg 4	= Frame Pointer (>8k varying frame with HP compilers only)
-   Reg 4-18	= Preserved Registers
-   Reg 19	= Linkage Table Register in HPUX 8.0 shared library scheme.
-   Reg 20-22	= Temporary Registers
-   Reg 23-26	= Temporary/Parameter Registers
-   Reg 27	= Global Data Pointer (hp)
-   Reg 28	= Temporary/???/Return Value register
-   Reg 29	= Temporary/Static Chain/Return Value register #2
-   Reg 30	= stack pointer
-   Reg 31	= Temporary/Millicode Return Pointer (hp)
-
-   Freg 0-3	= Status Registers	 -- Not known to the compiler.
-   Freg 4-7	= Arguments/Return Value
-   Freg 8-11	= Temporary Registers
-   Freg 12-15	= Preserved Registers
-
-   Freg 16-31	= Reserved
-
-   On the Snake, fp regs are
-
-   Freg 0-3	= Status Registers	-- Not known to the compiler.
-   Freg 4L-7R	= Arguments/Return Value
-   Freg 8L-11R	= Temporary Registers
-   Freg 12L-21R	= Preserved Registers
-   Freg 22L-31R = Temporary Registers
-
-*/
-
-#define FIXED_REGISTERS  \
- {0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 1, 0, 0, 1, 0, \
-  /* fp registers */	  \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS  \
- {1, 1, 1, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1, \
-  /* fp registers */	  \
-  1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 0, 0, 0, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 1, 1, 1, 1, 1, 1, 1, \
-  1}
-
-#define CONDITIONAL_REGISTER_USAGE \
-{						\
-  if (!TARGET_SNAKE)				\
-    {						\
-      for (i = 56; i < 88; i++) 		\
-	fixed_regs[i] = call_used_regs[i] = 1; 	\
-      for (i = 33; i < 88; i += 2) 		\
-	fixed_regs[i] = call_used_regs[i] = 1; 	\
-    }						\
-  if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
-    {						\
-      for (i = 32; i < 88; i++) 		\
-	fixed_regs[i] = call_used_regs[i] = 1; 	\
-    }						\
-  if (flag_pic)					\
-    {						\
-      fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;	\
-      fixed_regs[PIC_OFFSET_TABLE_REGNUM_SAVED] = 1;\
-    }						\
-}
-
-/* CYGNUS LOCAL PA8000/law */
-/* Allocate the call used registers first.  This should minimize
-   the number of registers that need to be saved (as call used
-   registers will generally not be allocated across a call).
-
-   Experimentation has shown slightly better results by allocating
-   FP registers first. 
-
-   The PA8000 triggers a depedency stall if we use both halves of a 
-   floating point register in the same bundle.  So we separate out the
-   halves to discourage using them in nearby insns.  This should be
-   fixed in the register allocator/scheduler.  */
-
-#define REG_ALLOC_ORDER \
- {					\
-  /* caller-saved fp regs.  */		\
-  68, 70, 72, 74, 76, 78, 80, 82, 	\
-  84, 86, 40, 42, 44, 46, 32, 34, 	\
-  36, 38, 				\
-  69, 71, 73, 75, 77, 79, 81, 83, 	\
-  85, 87, 41, 43, 45, 47, 33, 35, 	\
-  37, 39, 				\
-  /* caller-saved general regs.  */	\
-  19, 20, 21, 22, 23, 24, 25, 26,	\
-  27, 28, 29, 31,  2,			\
-  /* callee-saved fp regs.  */		\
-  48, 50, 52, 54, 56, 58, 60, 62,	\
-  64, 66, 				\
-  49, 51, 53, 55, 57, 59, 61, 63,	\
-  65, 67,				\
-  /* callee-saved general regs.  */	\
-   3,  4,  5,  6,  7,  8,  9, 10, 	\
-  11, 12, 13, 14, 15, 16, 17, 18,	\
-  /* special registers.  */		\
-   1, 30,  0, 88}
-/* END CYGNUS LOCAL */
-
-
-/* True if register is floating-point.  */
-#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 87)
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On the HP-PA, ordinary registers hold 32 bits worth;
-   The floating point registers are 64 bits wide. Snake fp regs are 32
-   bits wide */
-#define HARD_REGNO_NREGS(REGNO, MODE)					\
-  (!TARGET_SNAKE && FP_REGNO_P (REGNO) ? 1				\
-   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On the HP-PA, the cpu registers can hold any mode.  We
-   force this to be an even register is it cannot hold the full mode.  */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-  ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode		\
-   /* On 1.0 machines, don't allow wide non-fp modes in fp regs. */	\
-   : !TARGET_SNAKE && FP_REGNO_P (REGNO)				\
-     ? GET_MODE_SIZE (MODE) <= 4 || GET_MODE_CLASS (MODE) == MODE_FLOAT	\
-   /* Make wide modes be in aligned registers. */			\
-   : GET_MODE_SIZE (MODE) <= 4 || ((REGNO) & 1) == 0)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* The HP-PA pc isn't overloaded on a register that the compiler knows about.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 30
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 3
-
-/* Value should be nonzero if functions must have frame pointers.  */
-#define FRAME_POINTER_REQUIRED \
-  (current_function_calls_alloca)
-
-/* C statement to store the difference between the frame pointer
-   and the stack pointer values immediately after the function prologue.
-
-   Note, we always pretend that this is a leaf function because if
-   it's not, there's no point in trying to eliminate the
-   frame pointer.  If it is a leaf function, we guessed right!  */
-#define INITIAL_FRAME_POINTER_OFFSET(VAR) \
-  do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0)
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 3
-
-/* Register in which static-chain is passed to a function.  */
-/* ??? */
-#define STATIC_CHAIN_REGNUM 29
-
-/* Register which holds offset table for position-independent
-   data references.  */
-
-#define PIC_OFFSET_TABLE_REGNUM 19
-#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
-
-/* Register into which we save the PIC_OFFEST_TABLE_REGNUM so that it
-   can be restore across function calls.  */
-#define PIC_OFFSET_TABLE_REGNUM_SAVED 4
-
-/* SOM ABI says that objects larger than 64 bits are returned in memory.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-#define RETURN_IN_MEMORY(TYPE)	\
-  (int_size_in_bytes (TYPE) > 8)
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 28
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-  /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
-     1.1 fp regs, and the high 1.1 fp regs, to which the operands of
-     fmpyadd and fmpysub are restricted.  */
-
-enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS,
-  SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
-  {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
-   "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES. Register 0, the "condition code" register,
-   is in no class. */
-
-#define REG_CLASS_CONTENTS	\
- {{0x00000000, 0x00000000, 0x00000000},	/* NO_REGS */			\
-  {0x00000002, 0x00000000, 0x00000000},	/* R1_REGS */			\
-  {0xfffffffe, 0x00000000, 0x00000000},	/* GENERAL_REGS */		\
-  {0x00000000, 0xff000000, 0x00ffffff},	/* FPUPPER_REGS */			\
-  {0x00000000, 0xffffffff, 0x00ffffff},	/* FP_REGS */			\
-  {0xfffffffe, 0xffffffff, 0x00ffffff},	/* GENERAL_OR_FP_REGS */	\
-  {0x00000000, 0x00000000, 0x01000000},	/* SHIFT_REGS */		\
-  {0xfffffffe, 0xffffffff, 0x01ffffff}}	/* ALL_REGS */
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO)						\
-  ((REGNO) == 0 ? NO_REGS 						\
-   : (REGNO) == 1 ? R1_REGS						\
-   : (REGNO) < 32 ? GENERAL_REGS					\
-   : (REGNO) < 56 ? FP_REGS						\
-   : (REGNO) < 88 ? FPUPPER_REGS						\
-   : SHIFT_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-#define FP_REG_CLASS_P(CLASS) \
-  ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-/* Keep 'x' for backward compatibility with user asm.   */
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'f' ? FP_REGS :					\
-   (C) == 'y' ? FPUPPER_REGS :					\
-   (C) == 'x' ? FP_REGS :					\
-   (C) == 'q' ? SHIFT_REGS :					\
-   (C) == 'a' ? R1_REGS :					\
-   (C) == 'Z' ? ALL_REGS : NO_REGS)
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   `I' is used for the 11 bit constants.
-   `J' is used for the 14 bit constants.
-   `K' is used for values that can be moved with a zdepi insn.
-   `L' is used for the 5 bit constants.
-   `M' is used for 0.
-   `N' is used for values with the least significant 11 bits equal to zero.
-   `O' is used for numbers n such that n+1 is a power of 2.
-   */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'I' ? VAL_11_BITS_P (VALUE)				\
-   : (C) == 'J' ? VAL_14_BITS_P (VALUE)				\
-   : (C) == 'K' ? zdepi_cint_p (VALUE)				\
-   : (C) == 'L' ? VAL_5_BITS_P (VALUE)				\
-   : (C) == 'M' ? (VALUE) == 0					\
-   : (C) == 'N' ? ((VALUE) & 0x7ff) == 0			\
-   : (C) == 'O' ? (((VALUE) & ((VALUE) + 1)) == 0)		\
-   : (C) == 'P' ? and_mask_p (VALUE)				\
-   : 0)
-
-/* Prototype function used in macro CONST_OK_FOR_LETTER_P. */
-int zdepi_cint_p ();
-
-/* Similar, but for floating or large integer constants, and defining letters
-   G and H.   Here VALUE is the CONST_DOUBLE rtx itself.
-
-   For PA, `G' is the floating-point constant zero.  `H' is undefined.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  			\
-  ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT	\
-		 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))		\
-   : 0)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
-
-/* Return the register class of a scratch register needed to copy IN into
-   or out of a register in CLASS in MODE.  If it can be done directly
-   NO_REGS is returned. 
-
-  Avoid doing any work for the common case calls.  */
-
-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
-  ((CLASS == BASE_REG_CLASS && GET_CODE (IN) == REG		\
-    && REGNO (IN) < FIRST_PSEUDO_REGISTER)			\
-   ? NO_REGS : secondary_reload_class (CLASS, MODE, IN))
-
-/* On the PA it is not possible to directly move data between
-   GENERAL_REGS and FP_REGS.  */
-#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)  \
-  (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
-
-/* Return the stack location to use for secondary memory needed reloads.  */
-#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
-  gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-16)))
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)					\
-  (!TARGET_SNAKE && ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS) ? 1 :				\
-   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-/* #define STACK_GROWS_DOWNWARD */
-
-/* Believe it or not.  */
-#define ARGS_GROW_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-/* #define FRAME_GROWS_DOWNWARD */
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET 8
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On the HP-PA, don't define this because there are no push insns.  */
-/*  #define PUSH_ROUNDING(BYTES) */
-
-/* Offset of first parameter from the argument pointer register value.
-   This value will be negated because the arguments grow down.
-   Also note that on STACK_GROWS_UPWARD machines (such as this one)
-   this is the distance from the frame pointer to the end of the first
-   argument, not it's beginning.  To get the real offset of the first
-   argument, the size of the argument must be added.
-
-   ??? Have to check on this.*/
-
-#define FIRST_PARM_OFFSET(FNDECL) -32
-
-/* Absolute value of offset from top-of-stack address to location to store the
-   function parameter if it can't go in a register.
-   Addresses for following parameters are computed relative to this one.  */
-#define FIRST_PARM_CALLER_OFFSET(FNDECL) -32
-
-
-/* When a parameter is passed in a register, stack space is still
-   allocated for it.  */
-#define REG_PARM_STACK_SPACE(DECL) 16
-
-/* Define this if the above stack space is to be considered part of the
-   space allocated by the caller.  */
-#define OUTGOING_REG_PARM_STACK_SPACE
-
-/* Keep the stack pointer constant throughout the function.
-   This is both an optimization and a necessity: longjmp
-   doesn't behave itself when the stack pointer moves within
-   the function!  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* The weird HPPA calling conventions require a minimum of 48 bytes on
-   the stack: 16 bytes for register saves, and 32 bytes for magic.
-   This is the difference between the logical top of stack and the
-   actual sp. */
-#define STACK_POINTER_OFFSET -32
-
-#define STACK_DYNAMIC_OFFSET(FNDECL)	\
-  ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size)
-
-/* Value is 1 if returning from a function call automatically
-   pops the arguments described by the number-of-args field in the call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-/* On the HP-PA the value is found in register(s) 28(-29), unless
-   the mode is SF or DF. Then the value is returned in fr4 (32, ) */
-
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx_REG (TYPE_MODE (VALTYPE), ((! TARGET_SOFT_FLOAT		     \
-				      && (TYPE_MODE (VALTYPE) == SFmode ||  \
-					  TYPE_MODE (VALTYPE) == DFmode)) ? \
-				     32 : 28))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE)	\
-  gen_rtx_REG (MODE,							\
-	       (! TARGET_SOFT_FLOAT					\
-	        && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) \
-  ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
-
-/* 1 if N is a possible register number for function argument passing.  */
-
-#define FUNCTION_ARG_REGNO_P(N) \
-  (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the HP-PA, this is a single integer, which is a number of words
-   of arguments scanned so far (including the invisible argument,
-   if any, which holds the structure-value-address).
-   Thus 4 or more means all following args should go on the stack.  */
-
-struct hppa_args {int words, nargs_prototype, indirect; };
-
-#define CUMULATIVE_ARGS struct hppa_args
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
-  (CUM).words = 0, 							\
-  (CUM).indirect = INDIRECT,						\
-  (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE)		\
-			   ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1	\
-			      + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
-				 || RETURN_IN_MEMORY (TREE_TYPE (FNTYPE)))) \
-			   : 0)
-
-
-
-/* Similar, but when scanning the definition of a procedure.  We always
-   set NARGS_PROTOTYPE large so we never return a PARALLEL.  */
-
-#define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
-  (CUM).words = 0,				\
-  (CUM).indirect = 0,				\
-  (CUM).nargs_prototype = 1000
-
-/* Figure out the size in words of the function argument. */
-
-#define FUNCTION_ARG_SIZE(MODE, TYPE)	\
-  ((((MODE) != BLKmode ? GET_MODE_SIZE (MODE) : int_size_in_bytes (TYPE))+3)/4)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
-{ (CUM).nargs_prototype--;						\
-  ((((CUM).words & 01) && (TYPE) != 0					\
-    && FUNCTION_ARG_SIZE(MODE, TYPE) > 1)				\
-   && (CUM).words++),							\
-     (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE);			\
-}
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-
-   On the HP-PA the first four words of args are normally in registers
-   and the rest are pushed.  But any arg that won't entirely fit in regs
-   is pushed.
-
-   Arguments passed in registers are either 1 or 2 words long.
-
-   The caller must make a distinction between calls to explicitly named
-   functions and calls through pointers to functions -- the conventions
-   are different!  Calls through pointers to functions only use general
-   registers for the first four argument words.
-
-   Of course all this is different for the portable runtime model
-   HP wants everyone to use for ELF.  Ugh.  Here's a quick description
-   of how it's supposed to work.
-
-   1) callee side remains unchanged.  It expects integer args to be
-   in the integer registers, float args in the float registers and
-   unnamed args in integer registers.
-
-   2) caller side now depends on if the function being called has
-   a prototype in scope (rather than if it's being called indirectly).
-
-      2a) If there is a prototype in scope, then arguments are passed
-      according to their type (ints in integer registers, floats in float
-      registers, unnamed args in integer registers.
-
-      2b) If there is no prototype in scope, then floating point arguments
-      are passed in both integer and float registers.  egad.
-
-  FYI: The portable parameter passing conventions are almost exactly like
-  the standard parameter passing conventions on the RS6000.  That's why
-  you'll see lots of similar code in rs6000.h.  */
-
-#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
-
-/* Do not expect to understand this without reading it several times.  I'm
-   tempted to try and simply it, but I worry about breaking something.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)		      		\
-  (4 >= ((CUM).words + FUNCTION_ARG_SIZE ((MODE), (TYPE)))		\
-   ? (!TARGET_PORTABLE_RUNTIME || (TYPE) == 0				\
-      || !FLOAT_MODE_P (MODE) || TARGET_SOFT_FLOAT			\
-      || (CUM).nargs_prototype > 0)					\
-      ? gen_rtx_REG ((MODE),						\
-		 (FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1		\
-		  ? (((!(CUM).indirect 					\
-		       || TARGET_PORTABLE_RUNTIME)			\
-		      && (MODE) == DFmode				\
-		      && ! TARGET_SOFT_FLOAT)				\
-		     ? ((CUM).words ? 38 : 34)				\
-		     : ((CUM).words ? 23 : 25))				\
-		  : (((!(CUM).indirect					\
-		       || TARGET_PORTABLE_RUNTIME)			\
-		      && (MODE) == SFmode				\
-		      && ! TARGET_SOFT_FLOAT)				\
-		     ? (32 + 2 * (CUM).words)				\
-		     : (27 - (CUM).words - FUNCTION_ARG_SIZE ((MODE),	\
-							      (TYPE))))))\
-   /* We are calling a non-prototyped function with floating point	\
-      arguments using the portable conventions.  */			\
-   : gen_rtx_PARALLEL ((MODE),						\
-	      gen_rtvec							\
-	      (2,							\
-	       gen_rtx_EXPR_LIST (VOIDmode,				\
-			gen_rtx_REG ((MODE),				\
-				 (FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1 \
-				  ? ((CUM).words ? 38 : 34)		\
-				  : (32 + 2 * (CUM).words))),		\
-			const0_rtx),					\
-	       gen_rtx_EXPR_LIST (VOIDmode,				\
-			gen_rtx_REG ((MODE),				\
-				 (FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1 \
-				  ? ((CUM).words ? 23 : 25)		\
-				  : (27 - (CUM).words -			\
-				     FUNCTION_ARG_SIZE ((MODE),		\
-							(TYPE))))),	\
-			const0_rtx)))					\
-  /* Pass this parameter in the stack.  */				\
-  : 0)
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
-/* If defined, a C expression that gives the alignment boundary, in
-   bits, of an argument with the specified mode and type.  If it is
-   not defined,  `PARM_BOUNDARY' is used for all arguments.  */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE)				\
-  (((TYPE) != 0)							\
-	? (((int_size_in_bytes (TYPE)) + 3) / 4) * BITS_PER_WORD	\
-	: ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY)			\
-		? PARM_BOUNDARY						\
-		: GET_MODE_ALIGNMENT(MODE)))
-
-/* Arguments larger than eight bytes are passed by invisible reference */
-
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)		\
-  ((TYPE) && int_size_in_bytes (TYPE) > 8)
- 
-#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
-  ((TYPE) && int_size_in_bytes (TYPE) > 8)
-
-
-extern struct rtx_def *hppa_compare_op0, *hppa_compare_op1;
-extern enum cmp_type hppa_branch_type;
-
-/* Output the label for a function definition.  */
-#ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
-#define ASM_DOUBLE_ARG_DESCRIPTORS(FILE, ARG0, ARG1)	\
-  do { fprintf (FILE, ",ARGW%d=FR", (ARG0));		\
-       fprintf (FILE, ",ARGW%d=FU", (ARG1));} while (0)
-#define DFMODE_RETURN_STRING ",RTNVAL=FU"
-#define SFMODE_RETURN_STRING ",RTNVAL=FR"
-#else
-#define ASM_DOUBLE_ARG_DESCRIPTORS(FILE, ARG0, ARG1)	\
-  do { fprintf (FILE, ",ARGW%d=FU", (ARG0));		\
-       fprintf (FILE, ",ARGW%d=FR", (ARG1));} while (0)
-#define DFMODE_RETURN_STRING ",RTNVAL=FR"
-#define SFMODE_RETURN_STRING ",RTNVAL=FU"
-#endif
-
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
-{ char *target_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \
-  STRIP_NAME_ENCODING (target_name, target_name); \
-  output_function_prologue (FILE, 0); \
-  if (VAL_14_BITS_P (DELTA)) \
-    fprintf (FILE, "\tb %s\n\tldo %d(%%r26),%%r26\n", target_name, DELTA); \
-  else \
-    fprintf (FILE, "\taddil L%%%d,%%r26\n\tb %s\n\tldo R%%%d(%%r1),%%r26\n", \
-	     DELTA, target_name, DELTA); \
-  fprintf (FILE, "\n\t.EXIT\n\t.PROCEND\n"); \
-}
-
-/* NAME refers to the function's name.  If we are placing each function into
-   its own section, we need to switch to the section for this function.  Note
-   that the section name will have a "." prefix.  */
-#define ASM_OUTPUT_FUNCTION_PREFIX(FILE, NAME) \
-  {									\
-    char *name;								\
-    STRIP_NAME_ENCODING (name, NAME);					\
-    if (!TARGET_PORTABLE_RUNTIME && TARGET_GAS && in_section == in_text) \
-      fputs ("\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n", FILE); \
-    else if (! TARGET_PORTABLE_RUNTIME && TARGET_GAS)			\
-      fprintf (FILE,							\
-	       "\t.SUBSPA .%s\n", name);				\
-  }
-    
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
-    do { tree fntype = TREE_TYPE (TREE_TYPE (DECL));			\
-	 tree tree_type = TREE_TYPE (DECL);				\
-	 tree parm;							\
-	 int i;								\
-	 if (TREE_PUBLIC (DECL) || TARGET_GAS)				\
-	   { extern int current_function_varargs;			\
-	     if (TREE_PUBLIC (DECL))					\
-	       {							\
-		 fputs ("\t.EXPORT ", FILE);				\
-		 assemble_name (FILE, NAME);				\
-		 fputs (",ENTRY,PRIV_LEV=3", FILE);			\
-	       }							\
-	     else							\
-	       {							\
-		 fputs ("\t.PARAM ", FILE);				\
-		 assemble_name (FILE, NAME);				\
-	       }							\
-	     if (TARGET_PORTABLE_RUNTIME)				\
-	       {							\
-		 fputs (",ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,", FILE);	\
-		 fputs ("RTNVAL=NO\n", FILE);				\
-		 break;							\
-	       }							\
-	     for (parm = DECL_ARGUMENTS (DECL), i = 0; parm && i < 4;	\
-		  parm = TREE_CHAIN (parm))				\
-	       {							\
-		 if (TYPE_MODE (DECL_ARG_TYPE (parm)) == SFmode		\
-		     && ! TARGET_SOFT_FLOAT)				\
-		   fprintf (FILE, ",ARGW%d=FR", i++);			\
-		 else if (TYPE_MODE (DECL_ARG_TYPE (parm)) == DFmode	\
-			  && ! TARGET_SOFT_FLOAT)			\
-		   {							\
-		     if (i <= 2)					\
-		       {						\
-			 if (i == 1) i++;				\
-			 ASM_DOUBLE_ARG_DESCRIPTORS (FILE, i++, i++);	\
-		       }						\
-		     else						\
-		       break;						\
-		   }							\
-		 else							\
-		   {							\
-		     int arg_size =					\
-		       FUNCTION_ARG_SIZE (TYPE_MODE (DECL_ARG_TYPE (parm)),\
-					  DECL_ARG_TYPE (parm));	\
-		     /* Passing structs by invisible reference uses	\
-			one general register.  */			\
-		     if (arg_size > 2					\
-			 || TREE_ADDRESSABLE (DECL_ARG_TYPE (parm)))	\
-		       arg_size = 1;					\
-		     if (arg_size == 2 && i <= 2)			\
-		       {						\
-			 if (i == 1) i++;				\
-			 fprintf (FILE, ",ARGW%d=GR", i++);		\
-			 fprintf (FILE, ",ARGW%d=GR", i++);		\
-		       }						\
-		     else if (arg_size == 1)				\
-		       fprintf (FILE, ",ARGW%d=GR", i++);		\
-		     else						\
-		       i += arg_size;					\
-		   }							\
-	       }							\
-	     /* anonymous args */					\
-	     if ((TYPE_ARG_TYPES (tree_type) != 0			\
-		  && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (tree_type)))\
-		      != void_type_node))				\
-		 || current_function_varargs)				\
-	       {							\
-		 for (; i < 4; i++)					\
-		   fprintf (FILE, ",ARGW%d=GR", i);			\
-	       }							\
-	     if (TYPE_MODE (fntype) == DFmode && ! TARGET_SOFT_FLOAT)	\
-	       fputs (DFMODE_RETURN_STRING, FILE);			\
-	     else if (TYPE_MODE (fntype) == SFmode && ! TARGET_SOFT_FLOAT) \
-	       fputs (SFMODE_RETURN_STRING, FILE);			\
-	     else if (fntype != void_type_node)				\
-	       fputs (",RTNVAL=GR", FILE);				\
-	     fputs ("\n", FILE);					\
-	   }} while (0)
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-/* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
-   of memory.  If any fpu reg is used in the function, we allocate
-   such a block here, at the bottom of the frame, just in case it's needed.
-
-   If this function is a leaf procedure, then we may choose not
-   to do a "save" insn.  The decision about whether or not
-   to do this is made in regclass.c.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) \
-  output_function_prologue (FILE, SIZE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.
-
-   Because HPUX _mcount is so different, we actually emit the
-   profiling code in function_prologue. This just stores LABELNO for
-   that. */
-
-#define PROFILE_BEFORE_PROLOGUE
-#define FUNCTION_PROFILER(FILE, LABELNO) \
-{ extern int hp_profile_labelno; hp_profile_labelno = (LABELNO);}
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-extern int may_call_alloca;
-extern int current_function_pretend_args_size;
-
-#define EXIT_IGNORE_STACK	\
- (get_frame_size () != 0	\
-  || current_function_calls_alloca || current_function_outgoing_args_size)
-
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-/* This declaration is needed due to traditional/ANSI
-   incompatibilities which cannot be #ifdefed away
-   because they occur inside of macros.  Sigh.  */
-extern union tree_node *current_function_decl;
-
-#define FUNCTION_EPILOGUE(FILE, SIZE)			\
-  output_function_epilogue (FILE, SIZE)
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.\
-
-   The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
-   and then branches to the specified routine.
-
-   This code template is copied from text segment to stack location
-   and then patched with INITIALIZE_TRAMPOLINE to contain
-   valid values, and then entered as a subroutine.
-
-   It is best to keep this as small as possible to avoid having to
-   flush multiple lines in the cache.  */
-
-#define TRAMPOLINE_TEMPLATE(FILE) \
-  {							\
-    fputs ("\tldw	36(0,%r22),%r21\n", FILE);	\
-    fputs ("\tbb,>=,n	%r21,30,.+16\n", FILE);	\
-    fputs ("\tdepi	0,31,2,%r21\n", FILE);		\
-    fputs ("\tldw	4(0,%r21),%r19\n", FILE);	\
-    fputs ("\tldw	0(0,%r21),%r21\n", FILE);	\
-    fputs ("\tldsid	(0,%r21),%r1\n", FILE);	\
-    fputs ("\tmtsp	%r1,%sr0\n", FILE);		\
-    fputs ("\tbe	0(%sr0,%r21)\n", FILE);	\
-    fputs ("\tldw	40(0,%r22),%r29\n", FILE);	\
-    fputs ("\t.word	0\n", FILE);			\
-    fputs ("\t.word	0\n", FILE);			\
-  }
-
-/* Length in units of the trampoline for entering a nested function.
-
-   Flush the cache entries corresponding to the first and last addresses
-   of the trampoline.  This is necessary as the trampoline may cross two
-   cache lines.
-
-   If the code part of the trampoline ever grows to > 32 bytes, then it
-   will become necessary to hack on the cacheflush pattern in pa.md.  */
-
-#define TRAMPOLINE_SIZE (11 * 4)
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.
-
-   Move the function address to the trampoline template at offset 12.
-   Move the static chain value to trampoline template at offset 16.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-{									\
-  rtx start_addr, end_addr;						\
-									\
-  start_addr = memory_address (Pmode, plus_constant ((TRAMP), 36));	\
-  emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (FNADDR));		\
-  start_addr = memory_address (Pmode, plus_constant ((TRAMP), 40));	\
-  emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (CXT));		\
-  /* fdc and fic only use registers for the address to flush,		\
-     they do not accept integer displacements.  */ 			\
-  start_addr = force_reg (SImode, (TRAMP));				\
-  end_addr = force_reg (SImode, plus_constant ((TRAMP), 32));		\
-  emit_insn (gen_dcacheflush (start_addr, end_addr));			\
-  end_addr = force_reg (SImode, plus_constant (start_addr, 32));	\
-  emit_insn (gen_icacheflush (start_addr, end_addr, start_addr,		\
-			      gen_reg_rtx (SImode), gen_reg_rtx (SImode)));\
-}
-
-/* Emit code for a call to builtin_saveregs.  We must emit USE insns which
-   reference the 4 integer arg registers and 4 fp arg registers.
-   Ordinarily they are not call used registers, but they are for
-   _builtin_saveregs, so we must make this explicit.  */
-
-extern struct rtx_def *hppa_builtin_saveregs ();
-#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) hppa_builtin_saveregs (ARGLIST)
-
-
-/* Addressing modes, and classification of registers for them.  */
-/* CYGNUS LOCAL PA8000/law */
-/* It is advisable to avoid autoincrement addressing modes on the PA8000
-   series processors.  This definition disables the most critical autoinc
-   usages (in loops).  When the prologue/epilogue code is converted we
-   can probably disable autoinc entirely for the PA8000.  */
-#define HAVE_POST_INCREMENT (pa_cpu == PROCESSOR_8000 ? flow2_completed : 1)
-#define HAVE_POST_DECREMENT (pa_cpu == PROCESSOR_8000 ? flow2_completed : 1)
-
-#define HAVE_PRE_DECREMENT (pa_cpu == PROCESSOR_8000 ? flow2_completed : 1)
-#define HAVE_PRE_INCREMENT (pa_cpu == PROCESSOR_8000 ? flow2_completed : 1)
-/* END CYGNUS LOCAL */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-  ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
-#define REGNO_OK_FOR_BASE_P(REGNO)  \
-  ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
-#define REGNO_OK_FOR_FP_P(REGNO) \
-  (FP_REGNO_P (REGNO) || FP_REGNO_P (reg_renumber[REGNO]))
-
-/* Now macros that check whether X is a register and also,
-   strictly, whether it is in a specified class.
-
-   These macros are specific to the HP-PA, and may be used only
-   in code for printing assembler insns and in conditions for
-   define_optimization.  */
-
-/* 1 if X is an fp register.  */
-
-#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address except
-   for symbolic addresses.  We get better CSE by rejecting them
-   here and allowing hppa_legitimize_address to break them up.  We
-   use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE.  */
-
-#define CONSTANT_ADDRESS_P(X) \
-  ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH) 						\
-   && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
-
-/* Include all constant integers and constant doubles, but not
-   floating-point, except for floating-point zero.
-
-   Reject LABEL_REFs if we're not using gas or the new HP assembler.  */
-#ifdef NEW_HP_ASSEMBLER
-#define LEGITIMATE_CONSTANT_P(X)  		\
-  ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT	\
-    || (X) == CONST0_RTX (GET_MODE (X)))	\
-   && !function_label_operand (X, VOIDmode))
-#else
-#define LEGITIMATE_CONSTANT_P(X)  		\
-  ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT	\
-    || (X) == CONST0_RTX (GET_MODE (X)))	\
-   && (GET_CODE (X) != LABEL_REF || TARGET_GAS)\
-   && !function_label_operand (X, VOIDmode))
-#endif
-
-/* Subroutine for EXTRA_CONSTRAINT.
-
-   Return 1 iff OP is a pseudo which did not get a hard register and
-   we are running the reload pass.  */
-
-#define IS_RELOADING_PSEUDO_P(OP) \
-  ((reload_in_progress					\
-    && GET_CODE (OP) == REG				\
-    && REGNO (OP) >= FIRST_PSEUDO_REGISTER		\
-    && reg_renumber [REGNO (OP)] < 0))
-
-/* CYGNUS LOCAL PA8000/law */
-/* Optional extra constraints for this machine. Borrowed from sparc.h.
-
-   For the HPPA, `Q' means that this is a memory operand but not a
-   symbolic memory operand.  Note that an unassigned pseudo register
-   is such a memory operand.  Needed because reload will generate
-   these things in insns and then not re-recognize the insns, causing
-   constrain_operands to fail.
-
-   `R' is for certain scaled indexed addresses
-
-   `S' is the constant 31.
-
-   `T' is for fp loads and stores.  */
-#define EXTRA_CONSTRAINT(OP, C)				\
-  ((C) == 'Q' ?						\
-   (IS_RELOADING_PSEUDO_P (OP)				\
-    || (GET_CODE (OP) == MEM				\
-	&& (memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
-	    || reload_in_progress)			\
-	&& ! symbolic_memory_operand (OP, VOIDmode)	\
-        && !(GET_CODE (XEXP (OP, 0)) == PLUS		\
-	     && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
-		 || GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT))))\
-   : ((C) == 'R' ?					\
-     (GET_CODE (OP) == MEM				\
-      && GET_CODE (XEXP (OP, 0)) == PLUS		\
-      && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT	\
-	  || GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT)	\
-      && (move_operand (OP, GET_MODE (OP))		\
-	  || memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
-	  || reload_in_progress))			\
-   : ((C) == 'T' ? 					\
-      (GET_CODE (OP) == MEM				\
-       /* Using DFmode forces only short displacements	\
-	  to be recognized as valid in reg+d addresses.  */\
-       && memory_address_p (DFmode, XEXP (OP, 0))	\
-       && !(GET_CODE (XEXP (OP, 0)) == PLUS		\
-	    && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
-		|| GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT))) \
-   : ((C) == 'S' ?					\
-      (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) : 0))))
-/* END CYGNUS LOCAL */
-	
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) \
-(REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-(REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   On the HP-PA, the actual legitimate addresses must be
-   REG+REG, REG+(REG*SCALE) or REG+SMALLINT.
-   But we can treat a SYMBOL_REF as legitimate if it is part of this
-   function's constant-pool, because such addresses can actually
-   be output as REG+SMALLINT. 
-
-   Note we only allow 5 bit immediates for access to a constant address;
-   doing so avoids losing for loading/storing a FP register at an address
-   which will not fit in 5 bits.  */
-
-#define VAL_5_BITS_P(X) ((unsigned)(X) + 0x10 < 0x20)
-#define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
-
-#define VAL_U5_BITS_P(X) ((unsigned)(X) < 0x20)
-#define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
-
-#define VAL_11_BITS_P(X) ((unsigned)(X) + 0x400 < 0x800)
-#define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
-
-#define VAL_14_BITS_P(X) ((unsigned)(X) + 0x2000 < 0x4000)
-#define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
-{							\
-  if ((REG_P (X) && REG_OK_FOR_BASE_P (X))		\
-      || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC		\
-	   || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC)	\
-	  && REG_P (XEXP (X, 0))			\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 0))))		\
-    goto ADDR;						\
-  else if (GET_CODE (X) == PLUS)			\
-    {							\
-      rtx base = 0, index = 0;				\
-      if (flag_pic && XEXP (X, 0) == pic_offset_table_rtx)\
-	{						\
-	  if (GET_CODE (XEXP (X, 1)) == REG		\
-	      && REG_OK_FOR_BASE_P (XEXP (X, 1)))	\
-	    goto ADDR;					\
-	  else if (flag_pic == 1			\
-		   && GET_CODE (XEXP (X, 1)) == SYMBOL_REF)\
-	    goto ADDR;					\
-	}						\
-      else if (REG_P (XEXP (X, 0))			\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 0)))		\
-	base = XEXP (X, 0), index = XEXP (X, 1);	\
-      else if (REG_P (XEXP (X, 1))			\
-	       && REG_OK_FOR_BASE_P (XEXP (X, 1)))	\
-	base = XEXP (X, 1), index = XEXP (X, 0);	\
-      if (base != 0)					\
-	if (GET_CODE (index) == CONST_INT		\
-	    && ((INT_14_BITS (index)			\
-		 && (TARGET_SOFT_FLOAT			\
-		     /* CYGNUS LOCAL pa8000/law */	\
-		     || (TARGET_PARISC_2_0		\
-			 && ((MODE == SFmode		\
-			      && (INTVAL (index) % 4) == 0)\
-			     || (MODE == DFmode		\
-				 && (INTVAL (index) % 8) == 0)))\
-		     /* END CYGNUS LOCAL pa8000/law */	\
-		     || ((MODE) != SFmode && (MODE) != DFmode))) \
-		|| INT_5_BITS (index)))			\
-	  goto ADDR;					\
-      if (! TARGET_SOFT_FLOAT				\
-	  && ! TARGET_DISABLE_INDEXING			\
-	  && base					\
-	  && (mode == SFmode || mode == DFmode)		\
-	  && GET_CODE (index) == MULT			\
-	  && GET_CODE (XEXP (index, 0)) == REG		\
-	  && REG_OK_FOR_BASE_P (XEXP (index, 0))	\
-	  && GET_CODE (XEXP (index, 1)) == CONST_INT	\
-	  && INTVAL (XEXP (index, 1)) == (mode == SFmode ? 4 : 8))\
-	goto ADDR;					\
-    }							\
-  else if (GET_CODE (X) == LO_SUM			\
-	   && GET_CODE (XEXP (X, 0)) == REG		\
-	   && REG_OK_FOR_BASE_P (XEXP (X, 0))		\
-	   && CONSTANT_P (XEXP (X, 1))			\
-	   && (TARGET_SOFT_FLOAT			\
-	       || ((MODE) != SFmode			\
-		   && (MODE) != DFmode)))		\
-    goto ADDR;						\
-  else if (GET_CODE (X) == LO_SUM			\
-	   && GET_CODE (XEXP (X, 0)) == SUBREG		\
-	   && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG\
-	   && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0)))\
-	   && CONSTANT_P (XEXP (X, 1))			\
-	   && (TARGET_SOFT_FLOAT			\
-	       || ((MODE) != SFmode			\
-		   && (MODE) != DFmode)))		\
-    goto ADDR;						\
-  else if (GET_CODE (X) == LABEL_REF			\
-	   || (GET_CODE (X) == CONST_INT		\
-	       && INT_5_BITS (X)))			\
-    goto ADDR;						\
-  /* Needed for -fPIC */				\
-  else if (GET_CODE (X) == LO_SUM			\
-	   && GET_CODE (XEXP (X, 0)) == REG             \
-	   && REG_OK_FOR_BASE_P (XEXP (X, 0))		\
-	   && GET_CODE (XEXP (X, 1)) == UNSPEC)		\
-    goto ADDR;						\
-}
-
-/* Look for machine dependent ways to make the invalid address AD a
-   valid address.
-
-   For the PA, transform:
-
-        memory(X + <large int>)
-
-   into:
-
-        if (<large int> & mask) >= 16
-          Y = (<large int> & ~mask) + mask + 1  Round up.
-        else
-          Y = (<large int> & ~mask)             Round down.
-        Z = X + Y
-        memory (Z + (<large int> - Y));
-
-   This makes reload inheritance and reload_cse work better since Z
-   can be reused.
-
-   There may be more opportunities to improve code with this hook.  */
-#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) 	\
-do { 									\
-  int offset, newoffset, mask;						\
-  rtx new, temp = NULL_RTX;						\
-  mask = GET_MODE_CLASS (MODE) == MODE_FLOAT ? 0x1f : 0x3fff;		\
-									\
-  /* CYGNUS LOCAL pa8000/law */						\
-  mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT				\
-	  ? (TARGET_PARISC_2_0 ? 0x3fff : 0x1f) : 0x3fff);		\
-  /* END CYGNUS LOCAL */						\
-									\
-  if (optimize								\
-      && GET_CODE (AD) == PLUS)						\
-    temp = simplify_binary_operation (PLUS, Pmode,			\
-				      XEXP (AD, 0), XEXP (AD, 1));	\
-									\
-  new = temp ? temp : AD;						\
-									\
-  if (optimize								\
-      && GET_CODE (new) == PLUS						\
-      && GET_CODE (XEXP (new, 0)) == REG				\
-      && GET_CODE (XEXP (new, 1)) == CONST_INT)				\
-    {									\
-      offset = INTVAL (XEXP ((new), 1));				\
-									\
-      /* Choose rounding direction.  Round up if we are >= halfway.  */	\
-      if ((offset & mask) >= ((mask + 1) / 2))				\
-	newoffset = (offset & ~mask) + mask + 1;			\
-      else								\
-	newoffset = offset & ~mask;					\
-									\
-      if (newoffset != 0						\
-	  && VAL_14_BITS_P (newoffset))					\
-	{								\
-									\
-	  temp = gen_rtx_PLUS (Pmode, XEXP (new, 0),			\
-			       GEN_INT (newoffset));			\
-	  AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
-	  push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0,		\
-			     BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,	\
-			     (OPNUM), (TYPE));				\
-	  goto WIN;							\
-	}								\
-    }									\
-} while (0)
-
-
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.  */
-
-extern struct rtx_def *hppa_legitimize_address ();
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)	\
-{ rtx orig_x = (X);				\
-  (X) = hppa_legitimize_address (X, OLDX, MODE);	\
-  if ((X) != orig_x && memory_address_p (MODE, X)) \
-    goto WIN; }
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
-  if (GET_CODE (ADDR) == PRE_DEC	\
-      || GET_CODE (ADDR) == POST_DEC	\
-      || GET_CODE (ADDR) == PRE_INC	\
-      || GET_CODE (ADDR) == POST_INC)	\
-    goto LABEL
-
-/* Define this macro if references to a symbol must be treated
-   differently depending on something about the variable or
-   function named by the symbol (such as what section it is in).
-
-   The macro definition, if any, is executed immediately after the
-   rtl for DECL or other node is created.
-   The value of the rtl will be a `mem' whose address is a
-   `symbol_ref'.
-
-   The usual thing for this macro to do is to a flag in the
-   `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
-   name string in the `symbol_ref' (if one bit is not enough
-   information).
-
-   On the HP-PA we use this to indicate if a symbol is in text or
-   data space.  Also, function labels need special treatment. */
-
-#define TEXT_SPACE_P(DECL)\
-  (TREE_CODE (DECL) == FUNCTION_DECL					\
-   || (TREE_CODE (DECL) == VAR_DECL					\
-       && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL)		\
-       && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
-       && !flag_pic)							\
-   || (TREE_CODE_CLASS (TREE_CODE (DECL)) == 'c'			\
-       && !(TREE_CODE (DECL) == STRING_CST && flag_writable_strings)))
-
-#define FUNCTION_NAME_P(NAME) \
-(*(NAME) == '@' || (*(NAME) == '*' && *((NAME) + 1) == '@'))
-
-#define ENCODE_SECTION_INFO(DECL)\
-do							\
-  { if (TEXT_SPACE_P (DECL))				\
-      {	rtx _rtl;					\
-	if (TREE_CODE (DECL) == FUNCTION_DECL		\
-	    || TREE_CODE (DECL) == VAR_DECL)		\
-	  _rtl = DECL_RTL (DECL);			\
-	else						\
-	  _rtl = TREE_CST_RTL (DECL);			\
-	SYMBOL_REF_FLAG (XEXP (_rtl, 0)) = 1;		\
-	if (TREE_CODE (DECL) == FUNCTION_DECL)		\
-	  hppa_encode_label (XEXP (DECL_RTL (DECL), 0), 0);\
-      }							\
-  }							\
-while (0)
-
-/* Store the user-specified part of SYMBOL_NAME in VAR.
-   This is sort of inverse to ENCODE_SECTION_INFO.  */
-
-#define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME)	\
-  (VAR) = ((SYMBOL_NAME)  + ((SYMBOL_NAME)[0] == '*' ?	\
-			     1 + (SYMBOL_NAME)[1] == '@'\
-			     : (SYMBOL_NAME)[0] == '@'))
-
-/* On hpux10, the linker will give an error if we have a reference
-   in the read-only data section to a symbol defined in a shared
-   library.  Therefore, expressions that might require a reloc can
-   not be placed in the read-only data section.  */
-#define SELECT_SECTION(EXP,RELOC) \
-  if (TREE_CODE (EXP) == VAR_DECL \
-      && TREE_READONLY (EXP) \
-      && !TREE_THIS_VOLATILE (EXP) \
-      && DECL_INITIAL (EXP) \
-      && (DECL_INITIAL (EXP) == error_mark_node \
-          || TREE_CONSTANT (DECL_INITIAL (EXP))) \
-      && !RELOC) \
-    readonly_data_section (); \
-  else if (TREE_CODE_CLASS (TREE_CODE (EXP)) == 'c' \
-	   && !(TREE_CODE (EXP) == STRING_CST && flag_writable_strings) \
-	   && !RELOC) \
-    readonly_data_section (); \
-  else \
-    data_section ();
-   
-/* Arghh.  The hpux10 linker chokes if we have a reference to symbols
-   in a readonly data section when the symbol is defined in a shared
-   library.  Since we can't know at compile time if a symbol will be
-   satisfied by a shared library or main program we put any symbolic
-   constant into the normal data section.  */
-#define SELECT_RTX_SECTION(MODE,RTX)	\
-  if (symbolic_operand (RTX, MODE))	\
-    data_section ();			\
-  else					\
-    readonly_data_section ();
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? TImode : DImode)
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 8
-
-/* Higher than the default as we prefer to use simple move insns
-   (better scheduling and delay slot filling) and because our
-   built-in block move is really a 2X unrolled loop.  */
-#define MOVE_RATIO 4
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.  */
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* Do not break .stabs pseudos into continuations.
-
-   This used to be zero (no max length), but big enums and such can
-   cause huge strings which killed gas.
-
-   We also have to avoid lossage in dbxout.c -- it does not compute the
-   string size accurately, so we are real conservative here.  */
-#define DBX_CONTIN_LENGTH 3000
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
-/* When a prototype says `char' or `short', really pass an `int'.  */
-#define PROMOTE_PROTOTYPES
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* Add any extra modes needed to represent the condition code.
-
-   HPPA floating comparisons produce condition codes. */
-#define EXTRA_CC_MODES CCFPmode
-
-/* Define the names for the modes specified above.  */
-#define EXTRA_CC_NAMES "CCFP"
-
-/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
-   return the mode to be used for the comparison.  For floating-point, CCFPmode
-   should be used.  CC_NOOVmode should be used when the first operand is a
-   PLUS, MINUS, or NEG.  CCmode should be used when no special processing is
-   needed.  */
-#define SELECT_CC_MODE(OP,X,Y) \
-  (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode)    \
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE SImode
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.  */
-#define NO_FUNCTION_CSE
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
-   few bits. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Use atexit for static constructors/destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:							\
-    if (INTVAL (RTX) == 0) return 0;					\
-    if (INT_14_BITS (RTX)) return 1;					\
-  case HIGH:								\
-    return 2;								\
-  case CONST:								\
-  case LABEL_REF:							\
-  case SYMBOL_REF:							\
-    return 4;								\
-  case CONST_DOUBLE:							\
-    if ((RTX == CONST0_RTX (DFmode) || RTX == CONST0_RTX (SFmode))	\
-	&& OUTER_CODE != SET)						\
-      return 0;								\
-    else								\
-      return 8;
-
-#define ADDRESS_COST(RTX) \
-  (GET_CODE (RTX) == REG ? 1 : hppa_address_cost (RTX))
-
-/* Compute extra cost of moving data between one register class
-   and another.
-
-   Make moves from SAR so expensive they should never happen.  We used to
-   have 0xffff here, but that generates overflow in rare cases.
-
-   Copies involving a FP register and a non-FP register are relatively
-   expensive because they must go through memory.
-
-   Other copies are reasonably cheap.  */
-#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
- (CLASS1 == SHIFT_REGS ? 0x100					\
-  : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16	\
-  : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16	\
-  : 2)
-
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  The purpose for the cost of MULT is to encourage
-   `synth_mult' to find a synthetic multiply when reasonable.  */
-
-#define RTX_COSTS(X,CODE,OUTER_CODE)					\
-  case MULT:								\
-    if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT)			\
-      return COSTS_N_INSNS (3);						\
-    return (TARGET_SNAKE && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT) \
-	    ? COSTS_N_INSNS (8) : COSTS_N_INSNS (20);	\
-  case DIV:								\
-    if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT)			\
-      return COSTS_N_INSNS (14);					\
-  case UDIV:								\
-  case MOD:								\
-  case UMOD:								\
-    return COSTS_N_INSNS (60);						\
-  case PLUS: /* this includes shNadd insns */				\
-  case MINUS:								\
-    if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT)			\
-      return COSTS_N_INSNS (3);						\
-    return COSTS_N_INSNS (1);						\
-  case ASHIFT:								\
-  case ASHIFTRT:							\
-  case LSHIFTRT:							\
-    return COSTS_N_INSNS (1);
-
-/* Adjust the cost of dependencies.  */
-
-#define ADJUST_COST(INSN,LINK,DEP,COST) \
-  (COST) = pa_adjust_cost (INSN, LINK, DEP, COST)
-
-/* Adjust scheduling priorities.  We use this to try and keep addil
-   and the next use of %r1 close together.  */
-#define ADJUST_PRIORITY(PREV) \
-  {								\
-    rtx set = single_set (PREV);				\
-    rtx src, dest;						\
-    if (set)							\
-      {								\
-        src = SET_SRC (set);					\
-	dest = SET_DEST (set);					\
-	if (GET_CODE (src) == LO_SUM				\
-	    && symbolic_operand (XEXP (src, 1), VOIDmode)	\
-	    && ! read_only_operand (XEXP (src, 1), VOIDmode))   \
-	  INSN_PRIORITY (PREV) >>= 3;				\
-        else if (GET_CODE (src) == MEM				\
-		 && GET_CODE (XEXP (src, 0)) == LO_SUM		\
-		 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)\
-		 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))\
-	  INSN_PRIORITY (PREV) >>= 1;				\
-	else if (GET_CODE (dest) == MEM				\
-		 && GET_CODE (XEXP (dest, 0)) == LO_SUM		\
-		 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)\
-		 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))\
-	  INSN_PRIORITY (PREV) >>= 3;				\
-      }								\
-  }
-
-/* Handling the special cases is going to get too complicated for a macro,
-   just call `pa_adjust_insn_length' to do the real work.  */
-#define ADJUST_INSN_LENGTH(INSN, LENGTH)	\
-  LENGTH += pa_adjust_insn_length (INSN, LENGTH);
-
-/* Millicode insns are actually function calls with some special
-   constraints on arguments and register usage.
-
-   Millicode calls always expect their arguments in the integer argument
-   registers, and always return their result in %r29 (ret1).  They
-   are expected to clobber their arguments, %r1, %r29, and %r31 and
-   nothing else.
-
-   These macros tell reorg that the references to arguments and
-   register clobbers for millicode calls do not appear to happen
-   until after the millicode call.  This allows reorg to put insns
-   which set the argument registers into the delay slot of the millicode
-   call -- thus they act more like traditional CALL_INSNs.
-
-   get_attr_type will try to recognize the given insn, so make sure to
-   filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
-   in particular.  */
-#define INSN_SETS_ARE_DELAYED(X) (insn_sets_and_refs_are_delayed (X))
-#define INSN_REFERENCES_ARE_DELAYED(X) (insn_sets_and_refs_are_delayed (X))
-
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(FILE) \
-do { fputs ("\t.SPACE $PRIVATE$\n\
-\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31\n\
-\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82\n\
-\t.SPACE $TEXT$\n\
-\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44\n\
-\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n\
-\t.IMPORT $global$,DATA\n\
-\t.IMPORT $$dyncall,MILLICODE\n", FILE);\
-     if (profile_flag)\
-       fprintf (FILE, "\t.IMPORT _mcount, CODE\n");\
-     if (write_symbols != NO_DEBUG) \
-       output_file_directive ((FILE), main_input_filename); \
-   } while (0)
-
-#define ASM_FILE_END(FILE) output_deferred_plabels (FILE)
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-
-/* We don't yet know how to identify GCC to HP-PA machines.  */
-#define ASM_IDENTIFY_GCC(FILE) fputs ("; gcc_compiled.:\n", FILE)
-
-/* Output before code.  */
-
-/* Supposedly the assembler rejects the command if there is no tab!  */
-#define TEXT_SECTION_ASM_OP "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$\n"
-
-/* Output before read-only data.  */
-
-/* Supposedly the assembler rejects the command if there is no tab!  */
-#define READONLY_DATA_ASM_OP "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$\n"
-
-#define READONLY_DATA_SECTION readonly_data
-
-/* Output before writable data.  */
-
-/* Supposedly the assembler rejects the command if there is no tab!  */
-#define DATA_SECTION_ASM_OP "\t.SPACE $PRIVATE$\n\t.SUBSPA $DATA$\n"
-
-/* Output before uninitialized data.  */
-
-#define BSS_SECTION_ASM_OP "\t.SPACE $PRIVATE$\n\t.SUBSPA $BSS$\n"
-
-/* Define the .bss section for ASM_OUTPUT_LOCAL to use. */
-
-#ifndef CTORS_SECTION_FUNCTION
-#define EXTRA_SECTIONS in_readonly_data
-#define CTORS_SECTION_FUNCTION
-#define DTORS_SECTION_FUNCTION
-#else
-#define EXTRA_SECTIONS in_readonly_data, in_ctors, in_dtors
-#endif
-
-/* Switch into a generic section.
-   This is currently only used to support section attributes.
-
-   We make the section read-only and executable for a function decl,
-   read-only for a const data decl, and writable for a non-const data decl.  */
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
-  if (DECL && TREE_CODE (DECL) == FUNCTION_DECL)		\
-    {								\
-      fputs ("\t.SPACE $TEXT$\n", FILE);			\
-      fprintf (FILE,						\
-	       "\t.SUBSPA %s%s%s,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY,SORT=24\n",\
-	       TARGET_GAS ? "" : "$", NAME, TARGET_GAS ? "" : "$"); \
-    }								\
-  else if (DECL && DECL_READONLY_SECTION (DECL, RELOC))		\
-    {								\
-      fputs ("\t.SPACE $TEXT$\n", FILE);			\
-      fprintf (FILE,						\
-	       "\t.SUBSPA %s%s%s,QUAD=0,ALIGN=8,ACCESS=44,SORT=16\n", \
-	       TARGET_GAS ? "" : "$", NAME, TARGET_GAS ? "" : "$"); \
-    }								\
-  else								\
-    {								\
-      fputs ("\t.SPACE $PRIVATE$\n", FILE);			\
-      fprintf (FILE,						\
-	       "\t.SUBSPA %s%s%s,QUAD=1,ALIGN=8,ACCESS=31,SORT=16\n", \
-	       TARGET_GAS ? "" : "$", NAME, TARGET_GAS ? "" : "$"); \
-    }
-
-/* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups
-   which reference data within the $TEXT$ space (for example constant
-   strings in the $LIT$ subspace).
-
-   The assemblers (GAS and HP as) both have problems with handling
-   the difference of two symbols which is the other correct way to
-   reference constant data during PIC code generation.
-
-   So, there's no way to reference constant data which is in the
-   $TEXT$ space during PIC generation.  Instead place all constant
-   data into the $PRIVATE$ subspace (this reduces sharing, but it
-   works correctly).  */
-
-#define EXTRA_SECTION_FUNCTIONS						\
-void									\
-readonly_data ()							\
-{									\
-  if (in_section != in_readonly_data)					\
-    {									\
-      if (flag_pic)							\
-	fprintf (asm_out_file, "%s\n", DATA_SECTION_ASM_OP);		\
-      else								\
-	fprintf (asm_out_file, "%s\n", READONLY_DATA_ASM_OP);		\
-      in_section = in_readonly_data;					\
-    }									\
-}									\
-CTORS_SECTION_FUNCTION							\
-DTORS_SECTION_FUNCTION
-
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"%r0",   "%r1",    "%r2",   "%r3",    "%r4",   "%r5",    "%r6",   "%r7",    \
- "%r8",   "%r9",    "%r10",  "%r11",   "%r12",  "%r13",   "%r14",  "%r15",   \
- "%r16",  "%r17",   "%r18",  "%r19",   "%r20",  "%r21",   "%r22",  "%r23",   \
- "%r24",  "%r25",   "%r26",  "%r27",   "%r28",  "%r29",   "%r30",  "%r31",   \
- "%fr4",  "%fr4R",  "%fr5",  "%fr5R",  "%fr6",  "%fr6R",  "%fr7",  "%fr7R",  \
- "%fr8",  "%fr8R",  "%fr9",  "%fr9R",  "%fr10", "%fr10R", "%fr11", "%fr11R", \
- "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \
- "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \
- "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \
- "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \
- "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \
- "SAR"}
-
-#define ADDITIONAL_REGISTER_NAMES \
-{{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38},		\
- {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46},		\
- {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54},		\
- {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62},		\
- {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70},		\
- {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78},		\
- {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86},		\
- {"%cr11",88}}
-
-/* How to renumber registers for dbx and gdb.
-
-   Registers 0  - 31 remain unchanged.
-
-   Registers 32 - 87 are mapped to 72 - 127
-
-   Register 88 is mapped to 32.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) \
-  ((REGNO) <= 31 ? (REGNO) :						\
-   ((REGNO) > 31 && (REGNO) <= 87 ? (REGNO) + 40 : 32))
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE, NAME)	\
-  do { assemble_name (FILE, NAME); 	\
-       fputc ('\n', FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.
-
-   We call assemble_name, which in turn sets TREE_SYMBOL_REFERENCED.  This
-   macro will restore the original value of TREE_SYMBOL_REFERENCED to avoid
-   placing useless function definitions in the output file.  */
-
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)	\
-  do { int save_referenced;					\
-       save_referenced = TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (DECL)); \
-       fputs ("\t.IMPORT ", FILE);					\
-	 assemble_name (FILE, NAME);				\
-       if (FUNCTION_NAME_P (NAME))     				\
-	 fputs (",CODE\n", FILE);				\
-       else							\
-	 fputs (",DATA\n", FILE);				\
-       TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (DECL)) = save_referenced; \
-     } while (0)
-
-/* The bogus HP assembler requires ALL external references to be
-   "imported", even library calls. They look a bit different, so
-   here's this macro.
-
-   Also note not all libcall names are passed to ENCODE_SECTION_INFO
-   (__main for example).  To make sure all libcall names have section
-   info recorded in them, we do it here.  */
-
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, RTL) \
-  do { fputs ("\t.IMPORT ", FILE);					\
-       if (!function_label_operand (RTL, VOIDmode))			\
-	 hppa_encode_label (RTL, 1);					\
-       assemble_name (FILE, XSTR ((RTL), 0));		       		\
-       fputs (",CODE\n", FILE);						\
-     } while (0)
-
-#define ASM_GLOBALIZE_LABEL(FILE, NAME)					\
-  do {									\
-    /* We only handle DATA objects here, functions are globalized in	\
-       ASM_DECLARE_FUNCTION_NAME.  */					\
-    if (! FUNCTION_NAME_P (NAME))					\
-      {									\
-	fputs ("\t.EXPORT ", FILE);					\
-	assemble_name (FILE, NAME);					\
-	fputs (",DATA\n", FILE);					\
-      }									\
-  } while (0)
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-
-#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
-  fprintf ((FILE), "%s", (NAME) + (FUNCTION_NAME_P (NAME) ? 1 : 0))
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  {fprintf (FILE, "%c$%s%04d\n", (PREFIX)[0], (PREFIX) + 1, NUM);}
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%c$%s%04d", (PREFIX)[0], (PREFIX) + 1, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-  do { long l[2];							\
-       REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l);				\
-       fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", l[0], l[1]);	\
-     } while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-  do { long l;								\
-       REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);				\
-       fprintf (FILE, "\t.word 0x%lx\n", l);				\
-     } while (0)
-
-/* This is how to output an assembler line defining an `int' constant. 
-
-   This is made more complicated by the fact that functions must be
-   prefixed by a P% as well as code label references for the exception
-   table -- otherwise the linker chokes.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-{ fputs ("\t.word ", FILE);			\
-  if (function_label_operand (VALUE, VOIDmode)	\
-      && !TARGET_PORTABLE_RUNTIME)		\
-    fputs ("P%", FILE);				\
-  output_addr_const (FILE, (VALUE));		\
-  fputs ("\n", FILE);}
-
-/* Likewise for `short' and `char' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fputs ("\t.half ", FILE),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fputs ("\n", FILE))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fputs ("\t.byte ", FILE),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fputs ("\n", FILE))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-#define ASM_OUTPUT_ASCII(FILE, P, SIZE)  \
-  output_ascii ((FILE), (P), (SIZE))
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)
-/* This is how to output an element of a case-vector that is absolute.
-   Note that this method makes filling these branch delay slots
-   impossible.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  if (TARGET_BIG_SWITCH)					\
-    fprintf (FILE, "\tstw %%r1,-16(%%r30)\n\tldil LR'L$%04d,%%r1\n\tbe RR'L$%04d(%%sr4,%%r1)\n\tldw -16(%%r30),%%r1\n", VALUE, VALUE);		\
-  else								\
-    fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
-
-/* Jump tables are executable code and live in the TEXT section on the PA.  */
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* This is how to output an element of a case-vector that is relative.
-   This must be defined correctly as it is used when generating PIC code.
-
-   I believe it safe to use the same definition as ASM_OUTPUT_ADDR_VEC_ELT
-   on the PA since ASM_OUTPUT_ADDR_VEC_ELT uses pc-relative jump instructions
-   rather than a table of absolute addresses.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  if (TARGET_BIG_SWITCH)					\
-    fprintf (FILE, "\tstw %%r1,-16(%%r30)\n\tldw T'L$%04d(%%r19),%%r1\n\tbv 0(%%r1)\n\tldw -16(%%r30),%%r1\n", VALUE);				\
-  else								\
-    fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-    fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.blockz %d\n", (SIZE))
-
-/* This says how to output an assembler line to define a global common symbol
-   with size SIZE (in bytes) and alignment ALIGN (in bits).  */
-
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGNED)  		\
-{ bss_section ();							\
-  assemble_name ((FILE), (NAME));					\
-  fputs ("\t.comm ", (FILE));						\
-  fprintf ((FILE), "%d\n", MAX ((SIZE), ((ALIGNED) / BITS_PER_UNIT)));}
-
-/* This says how to output an assembler line to define a local common symbol
-   with size SIZE (in bytes) and alignment ALIGN (in bits).  */
-
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED)		\
-{ bss_section ();							\
-  fprintf ((FILE), "\t.align %d\n", ((ALIGNED) / BITS_PER_UNIT));	\
-  assemble_name ((FILE), (NAME));				\
-  fprintf ((FILE), "\n\t.block %d\n", (SIZE));}
-  
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12),	\
-  sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* All HP assemblers use "!" to separate logical lines.  */
-#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '!')
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
-  ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.
-
-   On the HP-PA, the CODE can be `r', meaning this is a register-only operand
-   and an immediate zero should be represented as `r0'.
-
-   Several % codes are defined:
-   O an operation
-   C compare conditions
-   N extract conditions
-   M modifier to handle preincrement addressing for memory refs.
-   F modifier to handle preincrement addressing for fp memory refs */
-
-#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
-
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx addr = ADDR;						\
-  register rtx base;							\
-  int offset;								\
-  switch (GET_CODE (addr))						\
-    {									\
-    case REG:								\
-      fprintf (FILE, "0(0,%s)", reg_names [REGNO (addr)]);		\
-      break;								\
-    case PLUS:								\
-      if (GET_CODE (XEXP (addr, 0)) == CONST_INT)			\
-	offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);	\
-      else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)			\
-	offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);	\
-      else								\
-	abort ();							\
-      fprintf (FILE, "%d(0,%s)", offset, reg_names [REGNO (base)]);	\
-      break;								\
-    case LO_SUM:							\
-      if (!symbolic_operand (XEXP (addr, 1)))				\
-	fputs ("R'", FILE);						\
-      else if (flag_pic == 0)						\
-	fputs ("RR'", FILE);						\
-      else if (flag_pic == 1)						\
-	abort ();							\
-      else if (flag_pic == 2)						\
-	fputs ("RT'", FILE);						\
-      output_global_address (FILE, XEXP (addr, 1), 0);			\
-      fputs ("(", FILE);						\
-      output_operand (XEXP (addr, 0), 0);				\
-      fputs (")", FILE);						\
-      break;								\
-    case CONST_INT:							\
-      fprintf (FILE, "%d(0,0)", INTVAL (addr));				\
-      break;								\
-    default:								\
-      output_addr_const (FILE, addr);					\
-    }}
-
-
-/* Define functions in pa.c and used in insn-output.c.  */
-
-extern char *output_and ();
-extern char *output_ior ();
-extern char *output_move_double ();
-extern char *output_fp_move_double ();
-extern char *output_block_move ();
-extern char *output_cbranch ();
-extern char *output_bb ();
-extern char *output_bvb ();
-extern char *output_dbra ();
-extern char *output_movb ();
-extern char *output_parallel_movb ();
-extern char *output_parallel_addb ();
-extern char *output_return ();
-extern char *output_call ();
-extern char *output_millicode_call ();
-extern char *output_mul_insn ();
-extern char *output_div_insn ();
-extern char *output_mod_insn ();
-extern char *singlemove_string ();
-extern void output_arg_descriptor ();
-extern void output_deferred_plabels ();
-extern void override_options ();
-extern void output_ascii ();
-extern void output_function_prologue ();
-extern void output_function_epilogue ();
-extern void output_global_address ();
-extern void print_operand ();
-extern struct rtx_def *legitimize_pic_address ();
-extern struct rtx_def *gen_cmp_fp ();
-extern void hppa_encode_label ();
-extern int arith11_operand ();
-extern int symbolic_expression_p ();
-extern int reloc_needed ();
-extern int compute_frame_size ();
-extern int hppa_address_cost ();
-extern int and_mask_p ();
-extern int symbolic_memory_operand ();
-extern int pa_adjust_cost ();
-extern int pa_adjust_insn_length ();
-extern int int11_operand ();
-extern int reg_or_cint_move_operand ();
-extern int arith5_operand ();
-extern int uint5_operand ();
-extern int pic_label_operand ();
-extern int plus_xor_ior_operator ();
-extern int basereg_operand ();
-extern int shadd_operand ();
-extern int arith_operand ();
-extern int read_only_operand ();
-extern int move_operand ();
-extern int and_operand ();
-extern int ior_operand ();
-extern int arith32_operand ();
-extern int uint32_operand ();
-extern int reg_or_nonsymb_mem_operand ();
-extern int reg_or_0_operand ();
-extern int reg_or_0_or_nonsymb_mem_operand ();
-extern int pre_cint_operand ();
-extern int post_cint_operand ();
-extern int div_operand ();
-extern int int5_operand ();
-extern int movb_comparison_operator ();
-extern int ireg_or_int5_operand ();
-extern int fmpyaddoperands ();
-extern int fmpysuboperands ();
-extern int call_operand_address ();
-extern int cint_ok_for_move ();
-extern int ior_operand ();
-extern void emit_bcond_fp ();
-extern int emit_move_sequence ();
-extern int emit_hpdiv_const ();
-extern void hppa_expand_prologue ();
-extern void hppa_expand_epilogue ();
-extern int hppa_can_use_return_insn_p ();
-extern int is_function_label_plus_const ();
-extern int jump_in_call_delay ();
-extern enum reg_class secondary_reload_class ();
-extern int insn_sets_and_refs_are_delayed ();
-
-/* Declare functions defined in pa.c and used in templates.  */
-
-extern struct rtx_def *return_addr_rtx ();
-
-/* We want __gcc_plt_call to appear in every program built by
-   gcc, so we make a reference to it out of __main.
-   We use the asm statement to fool the optimizer into not
-   removing the dead (but important) initialization of
-   REFERENCE.  */
-
-#define DO_GLOBAL_DTORS_BODY			\
-do {						\
-  extern void __gcc_plt_call ();		\
-  void (*reference)() = &__gcc_plt_call;	\
-  func_ptr *p;					\
-  __asm__ ("" : : "r" (reference));		\
-  for (p = __DTOR_LIST__ + 1; *p; )		\
-    (*p++) ();					\
-} while (0)
-
-/* Find the return address associated with the frame given by
-   FRAMEADDR.  */
-#define RETURN_ADDR_RTX(COUNT, FRAMEADDR)				 \
-  (return_addr_rtx (COUNT, FRAMEADDR))
-
-/* Used to mask out junk bits from the return address, such as
-   processor state, interrupt status, condition codes and the like.  */
-#define MASK_RETURN_ADDR						\
-  /* The privilege level is in the two low order bits, mask em out	\
-     of the return address.  */						\
-  (GEN_INT (0xfffffffc))
-
-/* The number of Pmode words for the setjmp buffer.  */
-#define JMP_BUF_SIZE 50
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
deleted file mode 100755
index 174bbd7..0000000
--- a/gcc/config/pa/pa.md
+++ /dev/null
@@ -1,5729 +0,0 @@
-;;- Machine description for HP PA-RISC architecture for GNU C compiler
-;;   Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
-;;   Contributed by the Center for Software Science at the University
-;;   of Utah.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;; This gcc Version 2 machine description is inspired by sparc.md and
-;; mips.md.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; Insn type.  Used to default other attribute values.
-
-;; type "unary" insns have one input operand (1) and one output operand (0)
-;; type "binary" insns have two input operands (1,2) and one output (0)
-
-(define_attr "type"
-  "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
-  (const_string "binary"))
-
-(define_attr "pa_combine_type"
-  "fmpy,faddsub,uncond_branch,addmove,none"
-  (const_string "none"))
-
-;; Processor type (for scheduling, not code generation) -- this attribute
-;; must exactly match the processor_type enumeration in pa.h.
-;;
-;; FIXME: Add 800 scheduling for completeness?
-
-;; CYGNUS LOCAL PA8000/law
-(define_attr "cpu" "700,7100,7100LC,7200,8000" (const (symbol_ref "pa_cpu_attr")))
-;; END CYGNUS LOCAL
-
-;; Length (in # of insns).
-(define_attr "length" ""
-  (cond [(eq_attr "type" "load,fpload")
-	 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
-		       (const_int 8) (const_int 4))
-
-	 (eq_attr "type" "store,fpstore")
-	 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
-		       (const_int 8) (const_int 4))
-
-	 (eq_attr "type" "binary,shift,nullshift")
-	 (if_then_else (match_operand 2 "arith_operand" "")
-		       (const_int 4) (const_int 12))
-
-	 (eq_attr "type" "move,unary,shift,nullshift")
-	 (if_then_else (match_operand 1 "arith_operand" "")
-		       (const_int 4) (const_int 8))]
-
-	(const_int 4)))
-
-(define_asm_attributes
-  [(set_attr "length" "4")
-   (set_attr "type" "multi")])
-
-;; Attributes for instruction and branch scheduling
-
-;; For conditional branches.
-(define_attr "in_branch_delay" "false,true"
-  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
-		     (eq_attr "length" "4"))
-		(const_string "true")
-		(const_string "false")))
-
-;; Disallow instructions which use the FPU since they will tie up the FPU
-;; even if the instruction is nullified.
-(define_attr "in_nullified_branch_delay" "false,true"
-  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
-		     (eq_attr "length" "4"))
-		(const_string "true")
-		(const_string "false")))
-
-;; For calls and millicode calls.  Allow unconditional branches in the
-;; delay slot.
-(define_attr "in_call_delay" "false,true"
-  (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
-	      (eq_attr "length" "4"))
-	   (const_string "true")
-	 (eq_attr "type" "uncond_branch")
-	   (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
-			     (const_int 0))
-			 (const_string "true")
-			 (const_string "false"))]
-	(const_string "false")))
-
-
-;; Call delay slot description.
-(define_delay (eq_attr "type" "call")
-  [(eq_attr "in_call_delay" "true") (nil) (nil)])
-
-;; millicode call delay slot description.  Note it disallows delay slot
-;; when TARGET_PORTABLE_RUNTIME is true.
-(define_delay (eq_attr "type" "milli")
-  [(and (eq_attr "in_call_delay" "true")
-	(eq (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0)))
-   (nil) (nil)])
-
-;; Return and other similar instructions.
-(define_delay (eq_attr "type" "branch,parallel_branch")
-  [(eq_attr "in_branch_delay" "true") (nil) (nil)])
-
-;; Floating point conditional branch delay slot description and
-(define_delay (eq_attr "type" "fbranch")
-  [(eq_attr "in_branch_delay" "true")
-   (eq_attr "in_nullified_branch_delay" "true")
-   (nil)])
-
-;; Integer conditional branch delay slot description.
-;; Nullification of conditional branches on the PA is dependent on the
-;; direction of the branch.  Forward branches nullify true and
-;; backward branches nullify false.  If the direction is unknown
-;; then nullification is not allowed.
-(define_delay (eq_attr "type" "cbranch")
-  [(eq_attr "in_branch_delay" "true")
-   (and (eq_attr "in_nullified_branch_delay" "true")
-	(attr_flag "forward"))
-   (and (eq_attr "in_nullified_branch_delay" "true")
-	(attr_flag "backward"))])
-
-(define_delay (and (eq_attr "type" "uncond_branch")
-		   (eq (symbol_ref "following_call (insn)")
-		       (const_int 0)))
-  [(eq_attr "in_branch_delay" "true") (nil) (nil)])
-
-;; Function units of the HPPA. The following data is for the 700 CPUs
-;; (Mustang CPU + Timex FPU aka PA-89) because that's what I have the docs for.
-;; Scheduling instructions for PA-83 machines according to the Snake
-;; constraints shouldn't hurt.
-
-;; (define_function_unit {name} {num-units} {n-users} {test}
-;;                       {ready-delay} {issue-delay} [{conflict-list}])
-
-;; The integer ALU.
-;; (Noted only for documentation; units that take one cycle do not need to
-;; be specified.)
-
-;; (define_function_unit "alu" 1 0
-;;  (and (eq_attr "type" "unary,shift,nullshift,binary,move,address")
-;;	 (eq_attr "cpu" "700"))
-;;  1 0)
-
-
-;; Memory. Disregarding Cache misses, the Mustang memory times are:
-;; load: 2, fpload: 3
-;; store, fpstore: 3, no D-cache operations should be scheduled.
-
-(define_function_unit "pa700memory" 1 0
-  (and (eq_attr "type" "load,fpload")
-       (eq_attr "cpu" "700")) 2 0)
-(define_function_unit "pa700memory" 1 0 
-  (and (eq_attr "type" "store,fpstore")
-       (eq_attr "cpu" "700")) 3 3)
-
-;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
-;; Timings:
-;; Instruction	Time	Unit	Minimum Distance (unit contention)
-;; fcpy		3	ALU	2
-;; fabs		3	ALU	2
-;; fadd		3	ALU	2
-;; fsub		3	ALU	2
-;; fcmp		3	ALU	2
-;; fcnv		3	ALU	2
-;; fmpyadd	3	ALU,MPY	2
-;; fmpysub	3	ALU,MPY 2
-;; fmpycfxt	3	ALU,MPY 2
-;; fmpy		3	MPY	2
-;; fmpyi	3	MPY	2
-;; fdiv,sgl	10	MPY	10
-;; fdiv,dbl	12	MPY	12
-;; fsqrt,sgl	14	MPY	14
-;; fsqrt,dbl	18	MPY	18
-
-(define_function_unit "pa700fp_alu" 1 0
-  (and (eq_attr "type" "fpcc")
-       (eq_attr "cpu" "700")) 4 2)
-(define_function_unit "pa700fp_alu" 1 0
-  (and (eq_attr "type" "fpalu")
-       (eq_attr "cpu" "700")) 3 2)
-(define_function_unit "pa700fp_mpy" 1 0
-  (and (eq_attr "type" "fpmulsgl,fpmuldbl")
-       (eq_attr "cpu" "700")) 3 2)
-(define_function_unit "pa700fp_mpy" 1 0
-  (and (eq_attr "type" "fpdivsgl")
-       (eq_attr "cpu" "700")) 10 10)
-(define_function_unit "pa700fp_mpy" 1 0
-  (and (eq_attr "type" "fpdivdbl")
-       (eq_attr "cpu" "700")) 12 12)
-(define_function_unit "pa700fp_mpy" 1 0
-  (and (eq_attr "type" "fpsqrtsgl")
-       (eq_attr "cpu" "700")) 14 14)
-(define_function_unit "pa700fp_mpy" 1 0
-  (and (eq_attr "type" "fpsqrtdbl")
-      (eq_attr "cpu" "700")) 18 18)
-
-;; Function units for the 7100 and 7150.  The 7100/7150 can dual-issue
-;; floating point computations with non-floating point computations (fp loads
-;; and stores are not fp computations).
-;;
-
-;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
-;; take two cycles, during which no Dcache operations should be scheduled.
-;; Any special cases are handled in pa_adjust_cost.  The 7100, 7150 and 7100LC
-;; all have the same memory characteristics if one disregards cache misses.
-(define_function_unit "pa7100memory" 1 0
-  (and (eq_attr "type" "load,fpload")
-       (eq_attr "cpu" "7100,7100LC")) 2 0)
-(define_function_unit "pa7100memory" 1 0 
-  (and (eq_attr "type" "store,fpstore")
-       (eq_attr "cpu" "7100,7100LC")) 2 2)
-
-;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
-;; Timings:
-;; Instruction	Time	Unit	Minimum Distance (unit contention)
-;; fcpy		2	ALU	1
-;; fabs		2	ALU	1
-;; fadd		2	ALU	1
-;; fsub		2	ALU	1
-;; fcmp		2	ALU	1
-;; fcnv		2	ALU	1
-;; fmpyadd	2	ALU,MPY	1
-;; fmpysub	2	ALU,MPY 1
-;; fmpycfxt	2	ALU,MPY 1
-;; fmpy		2	MPY	1
-;; fmpyi	2	MPY	1
-;; fdiv,sgl	8	DIV	8
-;; fdiv,dbl	15	DIV	15
-;; fsqrt,sgl	8	DIV	8
-;; fsqrt,dbl	15	DIV	15
-
-(define_function_unit "pa7100fp_alu" 1 0
-  (and (eq_attr "type" "fpcc,fpalu")
-       (eq_attr "cpu" "7100")) 2 1)
-(define_function_unit "pa7100fp_mpy" 1 0
-  (and (eq_attr "type" "fpmulsgl,fpmuldbl")
-       (eq_attr "cpu" "7100")) 2 1)
-(define_function_unit "pa7100fp_div" 1 0
-  (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
-       (eq_attr "cpu" "7100")) 8 8)
-(define_function_unit "pa7100fp_div" 1 0
-  (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
-       (eq_attr "cpu" "7100")) 15 15)
-
-;; To encourage dual issue we define function units corresponding to
-;; the instructions which can be dual issued.    This is a rather crude
-;; approximation, the "pa7100nonflop" test in particular could be refined.
-(define_function_unit "pa7100flop" 1 1
-  (and
-    (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
-    (eq_attr "cpu" "7100")) 1 1)
-
-(define_function_unit "pa7100nonflop" 1 1
-  (and
-    (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
-    (eq_attr "cpu" "7100")) 1 1)
-
-
-;; Memory subsystem works just like 7100/7150 (except for cache miss times which
-;; we don't model here).  
-
-;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
-;; Note divides and sqrt flops lock the cpu until the flop is
-;; finished.  fmpy and xmpyu (fmpyi) lock the cpu for one cycle.
-;; There's no way to avoid the penalty.
-;; Timings:
-;; Instruction	Time	Unit	Minimum Distance (unit contention)
-;; fcpy		2	ALU	1
-;; fabs		2	ALU	1
-;; fadd		2	ALU	1
-;; fsub		2	ALU	1
-;; fcmp		2	ALU	1
-;; fcnv		2	ALU	1
-;; fmpyadd,sgl	2	ALU,MPY	1
-;; fmpyadd,dbl	3	ALU,MPY	2
-;; fmpysub,sgl	2	ALU,MPY 1
-;; fmpysub,dbl	3	ALU,MPY 2
-;; fmpycfxt,sgl	2	ALU,MPY 1
-;; fmpycfxt,dbl	3	ALU,MPY 2
-;; fmpy,sgl	2	MPY	1
-;; fmpy,dbl	3	MPY	2
-;; fmpyi	3	MPY	2
-;; fdiv,sgl	8	DIV	8
-;; fdiv,dbl	15	DIV	15
-;; fsqrt,sgl	8	DIV	8
-;; fsqrt,dbl	15	DIV	15
-
-(define_function_unit "pa7100LCfp_alu" 1 0
-  (and (eq_attr "type" "fpcc,fpalu")
-       (eq_attr "cpu" "7100LC,7200")) 2 1)
-(define_function_unit "pa7100LCfp_mpy" 1 0
-  (and (eq_attr "type" "fpmulsgl")
-       (eq_attr "cpu" "7100LC,7200")) 2 1)
-(define_function_unit "pa7100LCfp_mpy" 1 0
-  (and (eq_attr "type" "fpmuldbl")
-       (eq_attr "cpu" "7100LC,7200")) 3 2)
-(define_function_unit "pa7100LCfp_div" 1 0
-  (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
-       (eq_attr "cpu" "7100LC,7200")) 8 8)
-(define_function_unit "pa7100LCfp_div" 1 0
-  (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
-       (eq_attr "cpu" "7100LC,7200")) 15 15)
-
-;; Define the various functional units for dual-issue.
-
-;; There's only one floating point unit.
-(define_function_unit "pa7100LCflop" 1 1
-  (and
-    (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
-    (eq_attr "cpu" "7100LC,7200")) 1 1)
-
-;; Shifts and memory ops actually execute in one of the integer
-;; ALUs, but we can't really model that.
-(define_function_unit "pa7100LCshiftmem" 1 1
-  (and
-    (eq_attr "type" "shift,nullshift,load,fpload,store,fpstore")
-    (eq_attr "cpu" "7100LC,7200")) 1 1)
-
-;; We have two basic ALUs.
-(define_function_unit "pa7100LCalu" 2 2
-  (and
-    (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
-   (eq_attr "cpu" "7100LC,7200")) 1 1)
-
-;; I don't have complete information on the PA7200; however, most of
-;; what I've heard makes it look like a 7100LC without the store-store
-;; penalty.  So that's how we'll model it.
-
-;; Memory. Disregarding Cache misses, memory loads and stores take
-;; two cycles.  Any special cases are handled in pa_adjust_cost.
-(define_function_unit "pa7200memory" 1 0
-  (and (eq_attr "type" "load,fpload,store,fpstore")
-       (eq_attr "cpu" "7200")) 2 0)
-
-;; I don't have detailed information on the PA7200 FP pipeline, so I
-;; treat it just like the 7100LC pipeline.
-;; Similarly for the multi-issue fake units.
-
-;; CYGNUS LOCAL PA8000/law
-;; 
-;; Scheduling for the PA8000 is somewhat different than scheduling for a
-;; traditional architecture.
-;;
-;; The PA8000 has a large (56) entry reorder buffer that is split between
-;; memory and non-memory operations.
-;;
-;; The PA800 can issue two memory and two non-memory operations per cycle to
-;; the function units.  Similarly, the PA8000 can retire two memory and two
-;; non-memory operations per cycle.
-;;
-;; Given the large reorder buffer, the processor can hide most latencies.
-;; According to HP, they've got the best results by scheduling for retirement
-;; bandwidth with limited latency scheduling for floating point operations.
-;; Latency for integer operations and memory references is ignored.
-;;
-;; We claim floating point operations have a 2 cycle latency and are
-;; fully pipelined, except for div and sqrt which are not pipelined.
-;;
-;; It is not necessary to define the shifter and integer alu units.
-;;
-;; These first two define_unit_unit descriptions model retirement from
-;; the reorder buffer.
-(define_function_unit "pa8000lsu" 2 2
-  (and
-    (eq_attr "type" "load,fpload,store,fpstore")
-    (eq_attr "cpu" "8000")) 1 0)
-
-(define_function_unit "pa8000alu" 2 2
-  (and
-    (eq_attr "type" "!load,fpload,store,fpstore")
-    (eq_attr "cpu" "8000")) 1 0)
-
-;; Claim floating point ops have a 2 cycle latency, including div and
-;; sqrt, but div and sqrt are not pipelined and issue to different units.
-(define_function_unit "pa8000fmac" 2 0
-  (and
-    (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
-    (eq_attr "cpu" "8000")) 2 0)
-
-(define_function_unit "pa8000fdiv" 2 2
-  (and
-    (eq_attr "type" "fpdivsgl,fpsqrtsgl")
-    (eq_attr "cpu" "8000")) 17 17)
-
-(define_function_unit "pa8000fdiv" 2 2
-  (and
-    (eq_attr "type" "fpdivdbl,fpsqrtdbl")
-    (eq_attr "cpu" "8000")) 31 31)
-;; END CYGNUS LOCAL
-
-;; Compare instructions.
-;; This controls RTL generation and register allocation.
-
-;; We generate RTL for comparisons and branches by having the cmpxx
-;; patterns store away the operands.  Then, the scc and bcc patterns
-;; emit RTL for both the compare and the branch.
-;;
-
-(define_expand "cmpsi"
-  [(set (reg:CC 0)
-	(compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
-		    (match_operand:SI 1 "arith5_operand" "")))]
-  ""
-  "
-{
- hppa_compare_op0 = operands[0];
- hppa_compare_op1 = operands[1];
- hppa_branch_type = CMP_SI;
- DONE;
-}")
-
-(define_expand "cmpsf"
-  [(set (reg:CCFP 0)
-	(compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
-		      (match_operand:SF 1 "reg_or_0_operand" "")))]
-  "! TARGET_SOFT_FLOAT"
-  "
-{
-  hppa_compare_op0 = operands[0];
-  hppa_compare_op1 = operands[1];
-  hppa_branch_type = CMP_SF;
-  DONE;
-}")
-
-(define_expand "cmpdf"
-  [(set (reg:CCFP 0)
-      (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
-                    (match_operand:DF 1 "reg_or_0_operand" "")))]
-  "! TARGET_SOFT_FLOAT"
-  "
-{
-  hppa_compare_op0 = operands[0];
-  hppa_compare_op1 = operands[1];
-  hppa_branch_type = CMP_DF;
-  DONE;
-}")
-
-(define_insn ""
-  [(set (reg:CCFP 0)
-	(match_operator:CCFP 2 "comparison_operator"
-			     [(match_operand:SF 0 "reg_or_0_operand" "fG")
-			      (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
-  "! TARGET_SOFT_FLOAT"
-  "fcmp,sgl,%Y2 %r0,%r1"
-  [(set_attr "length" "4")
-   (set_attr "type" "fpcc")])
-
-(define_insn ""
-  [(set (reg:CCFP 0)
-	(match_operator:CCFP 2 "comparison_operator"
-			     [(match_operand:DF 0 "reg_or_0_operand" "fG")
-			      (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
-  "! TARGET_SOFT_FLOAT"
-  "fcmp,dbl,%Y2 %r0,%r1"
-  [(set_attr "length" "4")
-   (set_attr "type" "fpcc")])
-
-;; scc insns.
-
-(define_expand "seq"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(eq:SI (match_dup 1)
-	       (match_dup 2)))]
-  ""
-  "
-{
-  /* fp scc patterns rarely match, and are not a win on the PA.  */
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  /* set up operands from compare.  */
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-  /* fall through and generate default code */
-}")
-
-(define_expand "sne"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ne:SI (match_dup 1)
-	       (match_dup 2)))]
-  ""
-  "
-{
-  /* fp scc patterns rarely match, and are not a win on the PA.  */
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "slt"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lt:SI (match_dup 1)
-	       (match_dup 2)))]
-  ""
-  "
-{
-  /* fp scc patterns rarely match, and are not a win on the PA.  */
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "sgt"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(gt:SI (match_dup 1)
-	       (match_dup 2)))]
-  ""
-  "
-{
-  /* fp scc patterns rarely match, and are not a win on the PA.  */
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "sle"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(le:SI (match_dup 1)
-	       (match_dup 2)))]
-  ""
-  "
-{
-  /* fp scc patterns rarely match, and are not a win on the PA.  */
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "sge"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ge:SI (match_dup 1)
-	       (match_dup 2)))]
-  ""
-  "
-{
-  /* fp scc patterns rarely match, and are not a win on the PA.  */
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "sltu"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ltu:SI (match_dup 1)
-	        (match_dup 2)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "sgtu"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(gtu:SI (match_dup 1)
-	        (match_dup 2)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "sleu"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(leu:SI (match_dup 1)
-	        (match_dup 2)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "sgeu"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(geu:SI (match_dup 1)
-	        (match_dup 2)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-;; Instruction canonicalization puts immediate operands second, which
-;; is the reverse of what we want.
-
-(define_insn "scc"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operator:SI 3 "comparison_operator"
-			   [(match_operand:SI 1 "register_operand" "r")
-			    (match_operand:SI 2 "arith11_operand" "rI")]))]
-  ""
-  "com%I2clr,%B3 %2,%1,%0\;ldi 1,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_insn "iorscc"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (match_operator:SI 3 "comparison_operator"
-				   [(match_operand:SI 1 "register_operand" "r")
-				    (match_operand:SI 2 "arith11_operand" "rI")])
-		(match_operator:SI 6 "comparison_operator"
-				   [(match_operand:SI 4 "register_operand" "r")
-				    (match_operand:SI 5 "arith11_operand" "rI")])))]
-  ""
-  "com%I2clr,%S3 %2,%1,0\;com%I5clr,%B6 %5,%4,%0\;ldi 1,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "12")])
-
-;; Combiner patterns for common operations performed with the output
-;; from an scc insn (negscc and incscc).
-(define_insn "negscc"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operator:SI 3 "comparison_operator"
-	       [(match_operand:SI 1 "register_operand" "r")
-		(match_operand:SI 2 "arith11_operand" "rI")])))]
-  ""
-  "com%I2clr,%B3 %2,%1,%0\;ldi -1,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-;; Patterns for adding/subtracting the result of a boolean expression from
-;; a register.  First we have special patterns that make use of the carry
-;; bit, and output only two instructions.  For the cases we can't in
-;; general do in two instructions, the incscc pattern at the end outputs
-;; two or three instructions.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
-			 (match_operand:SI 3 "arith11_operand" "rI"))
-		 (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "sub%I3 %3,%2,0\;addc 0,%1,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-; This need only accept registers for op3, since canonicalization
-; replaces geu with gtu when op3 is an integer.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
-			 (match_operand:SI 3 "register_operand" "r"))
-		 (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "sub %2,%3,0\;addc 0,%1,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-; Match only integers for op3 here.  This is used as canonical form of the
-; geu pattern when op3 is an integer.  Don't match registers since we can't
-; make better code than the general incscc pattern.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
-			 (match_operand:SI 3 "int11_operand" "I"))
-		 (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "addi %k3,%2,0\;addc 0,%1,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_insn "incscc"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
- 	(plus:SI (match_operator:SI 4 "comparison_operator"
-		    [(match_operand:SI 2 "register_operand" "r,r")
-		     (match_operand:SI 3 "arith11_operand" "rI,rI")])
-		 (match_operand:SI 1 "register_operand" "0,?r")))]
-  ""
-  "@
-   com%I3clr,%B4 %3,%2,0\;addi 1,%0,%0
-   com%I3clr,%B4 %3,%2,0\;addi,tr 1,%1,%0\;copy %1,%0"
-  [(set_attr "type" "binary,binary")
-   (set_attr "length" "8,12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (gtu:SI (match_operand:SI 2 "register_operand" "r")
-			  (match_operand:SI 3 "arith11_operand" "rI"))))]
-  ""
-  "sub%I3 %3,%2,0\;subb %1,0,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
-			    (gtu:SI (match_operand:SI 2 "register_operand" "r")
-				    (match_operand:SI 3 "arith11_operand" "rI")))
-		  (match_operand:SI 4 "register_operand" "r")))]
-  ""
-  "sub%I3 %3,%2,0\;subb %1,%4,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-; This need only accept registers for op3, since canonicalization
-; replaces ltu with leu when op3 is an integer.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (ltu:SI (match_operand:SI 2 "register_operand" "r")
-			  (match_operand:SI 3 "register_operand" "r"))))]
-  ""
-  "sub %2,%3,0\;subb %1,0,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
-			    (ltu:SI (match_operand:SI 2 "register_operand" "r")
-				    (match_operand:SI 3 "register_operand" "r")))
-		  (match_operand:SI 4 "register_operand" "r")))]
-  ""
-  "sub %2,%3,0\;subb %1,%4,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-; Match only integers for op3 here.  This is used as canonical form of the
-; ltu pattern when op3 is an integer.  Don't match registers since we can't
-; make better code than the general incscc pattern.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (leu:SI (match_operand:SI 2 "register_operand" "r")
-			  (match_operand:SI 3 "int11_operand" "I"))))]
-  ""
-  "addi %k3,%2,0\;subb %1,0,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
-			    (leu:SI (match_operand:SI 2 "register_operand" "r")
-				    (match_operand:SI 3 "int11_operand" "I")))
-		  (match_operand:SI 4 "register_operand" "r")))]
-  ""
-  "addi %k3,%2,0\;subb %1,%4,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_insn "decscc"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(minus:SI (match_operand:SI 1 "register_operand" "0,?r")
-		  (match_operator:SI 4 "comparison_operator"
-		     [(match_operand:SI 2 "register_operand" "r,r")
-		      (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
-  ""
-  "@
-   com%I3clr,%B4 %3,%2,0\;addi -1,%0,%0
-   com%I3clr,%B4 %3,%2,0\;addi,tr -1,%1,%0\;copy %1,%0"
-  [(set_attr "type" "binary,binary")
-   (set_attr "length" "8,12")])
-
-; Patterns for max and min.  (There is no need for an earlyclobber in the
-; last alternative since the middle alternative will match if op0 == op1.)
-
-(define_insn "sminsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
-		 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
-  ""
-  "@
-  comclr,> %2,%0,0\;copy %2,%0
-  comiclr,> %2,%0,0\;ldi %2,%0
-  comclr,> %1,%2,%0\;copy %1,%0"
-[(set_attr "type" "multi,multi,multi")
- (set_attr "length" "8,8,8")])
-
-(define_insn "uminsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(umin:SI (match_operand:SI 1 "register_operand" "%0,0")
-		 (match_operand:SI 2 "arith11_operand" "r,I")))]
-  ""
-  "@
-  comclr,>> %2,%0,0\;copy %2,%0
-  comiclr,>> %2,%0,0\;ldi %2,%0"
-[(set_attr "type" "multi,multi")
- (set_attr "length" "8,8")])
-
-(define_insn "smaxsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
-		 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
-  ""
-  "@
-  comclr,< %2,%0,0\;copy %2,%0
-  comiclr,< %2,%0,0\;ldi %2,%0
-  comclr,< %1,%2,%0\;copy %1,%0"
-[(set_attr "type" "multi,multi,multi")
- (set_attr "length" "8,8,8")])
-
-(define_insn "umaxsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(umax:SI (match_operand:SI 1 "register_operand" "%0,0")
-		 (match_operand:SI 2 "arith11_operand" "r,I")))]
-  ""
-  "@
-  comclr,<< %2,%0,0\;copy %2,%0
-  comiclr,<< %2,%0,0\;ldi %2,%0"
-[(set_attr "type" "multi,multi")
- (set_attr "length" "8,8")])
-
-(define_insn "abssi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(abs:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "or,>= %%r0,%1,%0\;subi 0,%0,%0"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
-;;; Experimental conditional move patterns
-
-(define_expand "movsicc"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(if_then_else:SI
-	 (match_operator 1 "comparison_operator"
-	    [(match_dup 4)
-	     (match_dup 5)])
-	 (match_operand:SI 2 "reg_or_cint_move_operand" "")
-	 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
-  ""
-  "
-{
-  enum rtx_code code = GET_CODE (operands[1]);
-
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-
-  /* operands[1] is currently the result of compare_from_rtx.  We want to
-     emit a compare of the original operands.  */
-  operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
-  operands[4] = hppa_compare_op0;
-  operands[5] = hppa_compare_op1;
-}")
-
-; We need the first constraint alternative in order to avoid
-; earlyclobbers on all other alternatives.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
-	(if_then_else:SI
-	 (match_operator 5 "comparison_operator"
-	    [(match_operand:SI 3 "register_operand" "r,r,r,r,r")
-	     (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
-	 (match_operand:SI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
-	 (const_int 0)))]
-  ""
-  "@
-   com%I4clr,%S5 %4,%3,0\;ldi 0,%0
-   com%I4clr,%B5 %4,%3,%0\;copy %1,%0
-   com%I4clr,%B5 %4,%3,%0\;ldi %1,%0
-   com%I4clr,%B5 %4,%3,%0\;ldil L'%1,%0
-   com%I4clr,%B5 %4,%3,%0\;zdepi %Z1,%0"
-  [(set_attr "type" "multi,multi,multi,multi,nullshift")
-   (set_attr "length" "8,8,8,8,8")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
-	(if_then_else:SI
-	 (match_operator 5 "comparison_operator"
-	    [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
-	     (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
-	 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
-	 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
-  ""
-  "@
-   com%I4clr,%S5 %4,%3,0\;copy %2,%0
-   com%I4clr,%S5 %4,%3,0\;ldi %2,%0
-   com%I4clr,%S5 %4,%3,0\;ldil L'%2,%0
-   com%I4clr,%S5 %4,%3,0\;zdepi %Z2,%0
-   com%I4clr,%B5 %4,%3,0\;copy %1,%0
-   com%I4clr,%B5 %4,%3,0\;ldi %1,%0
-   com%I4clr,%B5 %4,%3,0\;ldil L'%1,%0
-   com%I4clr,%B5 %4,%3,0\;zdepi %Z1,%0"
-  [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
-   (set_attr "length" "8,8,8,8,8,8,8,8")])
-
-;; Conditional Branches
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (match_dup 1) (match_dup 2))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    {
-      emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
-      emit_bcond_fp (NE, operands[0]);
-      DONE;
-    }
-  /* set up operands from compare.  */
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-  /* fall through and generate default code */
-}")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (match_dup 1) (match_dup 2))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    {
-      emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
-      emit_bcond_fp (NE, operands[0]);
-      DONE;
-    }
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (match_dup 1) (match_dup 2))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    {
-      emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
-      emit_bcond_fp (NE, operands[0]);
-      DONE;
-    }
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (match_dup 1) (match_dup 2))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    {
-      emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
-      emit_bcond_fp (NE, operands[0]);
-      DONE;
-    }
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (match_dup 1) (match_dup 2))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    {
-      emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
-      emit_bcond_fp (NE, operands[0]);
-      DONE;
-    }
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (match_dup 1) (match_dup 2))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    {
-      emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
-      emit_bcond_fp (NE, operands[0]);
-      DONE;
-    }
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (match_dup 1) (match_dup 2))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (match_dup 1) (match_dup 2))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (match_dup 1) (match_dup 2))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (match_dup 1) (match_dup 2))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (hppa_branch_type != CMP_SI)
-    FAIL;
-  operands[1] = hppa_compare_op0;
-  operands[2] = hppa_compare_op1;
-}")
-
-;; Match the branch patterns.
-
-
-;; Note a long backward conditional branch with an annulled delay slot
-;; has a length of 12.
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 3 "comparison_operator"
-			 [(match_operand:SI 1 "reg_or_0_operand" "rM")
-			  (match_operand:SI 2 "arith5_operand" "rL")])
-	 (label_ref (match_operand 0 "" ""))
-	 (pc)))]
-  ""
-  "*
-{
-  return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
-			 get_attr_length (insn), 0, insn);
-}"
-[(set_attr "type" "cbranch")
- (set (attr "length")
-    (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
-	       (const_int 8184))
-	   (const_int 4)
-	   (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
-	       (const_int 262100))
-	   (const_int 8)
-	   (eq (symbol_ref "flag_pic") (const_int 0))
-	   (const_int 20)]
-	  (const_int 28)))])
-
-;; Match the negated branch.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (match_operator 3 "comparison_operator"
-			 [(match_operand:SI 1 "reg_or_0_operand" "rM")
-			  (match_operand:SI 2 "arith5_operand" "rL")])
-	 (pc)
-	 (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
-			 get_attr_length (insn), 1, insn);
-}"
-[(set_attr "type" "cbranch")
- (set (attr "length")
-    (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
-	       (const_int 8184))
-	   (const_int 4)
-	   (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
-	       (const_int 262100))
-	   (const_int 8)
-	   (eq (symbol_ref "flag_pic") (const_int 0))
-	   (const_int 20)]
-	  (const_int 28)))])
-
-;; Branch on Bit patterns.
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
-			      (const_int 1)
-			      (match_operand:SI 1 "uint5_operand" ""))
-	     (const_int 0))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))]
-  ""
-  "*
-{
-  return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
-			 get_attr_length (insn), 0, insn, 0);
-}"
-[(set_attr "type" "cbranch")
- (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
-			      (const_int 1)
-			      (match_operand:SI 1 "uint5_operand" ""))
-	     (const_int 0))
-	 (pc)
-	 (label_ref (match_operand 2 "" ""))))]
-  ""
-  "*
-{
-  return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
-			 get_attr_length (insn), 1, insn, 0);
-}"
-[(set_attr "type" "cbranch")
- (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
-			      (const_int 1)
-			      (match_operand:SI 1 "uint5_operand" ""))
-	     (const_int 0))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))]
-  ""
-  "*
-{
-  return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
-			 get_attr_length (insn), 0, insn, 1);
-}"
-[(set_attr "type" "cbranch")
- (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
-			      (const_int 1)
-			      (match_operand:SI 1 "uint5_operand" ""))
-	     (const_int 0))
-	 (pc)
-	 (label_ref (match_operand 2 "" ""))))]
-  ""
-  "*
-{
-  return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
-			 get_attr_length (insn), 1, insn, 1);
-}"
-[(set_attr "type" "cbranch")
- (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-;; Branch on Variable Bit patterns.
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
-			      (const_int 1)
-			      (match_operand:SI 1 "register_operand" "q"))
-	     (const_int 0))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))]
-  ""
-  "*
-{
-  return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
-		     get_attr_length (insn), 0, insn, 0);
-}"
-[(set_attr "type" "cbranch")
- (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
-			      (const_int 1)
-			      (match_operand:SI 1 "register_operand" "q"))
-	     (const_int 0))
-	 (pc)
-	 (label_ref (match_operand 2 "" ""))))]
-  ""
-  "*
-{
-  return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
-		     get_attr_length (insn), 1, insn, 0);
-}"
-[(set_attr "type" "cbranch")
- (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
-			      (const_int 1)
-			      (match_operand:SI 1 "register_operand" "q"))
-	     (const_int 0))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))]
-  ""
-  "*
-{
-  return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
-		     get_attr_length (insn), 0, insn, 1);
-}"
-[(set_attr "type" "cbranch")
- (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
-			      (const_int 1)
-			      (match_operand:SI 1 "register_operand" "q"))
-	     (const_int 0))
-	 (pc)
-	 (label_ref (match_operand 2 "" ""))))]
-  ""
-  "*
-{
-  return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
-		     get_attr_length (insn), 1, insn, 1);
-}"
-[(set_attr "type" "cbranch")
- (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-;; Floating point branches
-(define_insn ""
-  [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
-			   (label_ref (match_operand 0 "" ""))
-			   (pc)))]
-  "! TARGET_SOFT_FLOAT"
-  "*
-{
-  if (INSN_ANNULLED_BRANCH_P (insn))
-    return \"ftest\;bl,n %0,0\";
-  else
-    return \"ftest\;bl%* %0,0\";
-}"
-  [(set_attr "type" "fbranch")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
-			   (pc)
-			   (label_ref (match_operand 0 "" ""))))]
-  "! TARGET_SOFT_FLOAT"
-  "*
-{
-  if (INSN_ANNULLED_BRANCH_P (insn))
-    return \"ftest\;add,tr 0,0,0\;bl,n %0,0\";
-  else
-    return \"ftest\;add,tr 0,0,0\;bl%* %0,0\";
-}"
-  [(set_attr "type" "fbranch")
-   (set_attr "length" "12")])
-
-;; Move instructions
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, SImode, 0))
-    DONE;
-}")
-
-;; Reloading an SImode or DImode value requires a scratch register if
-;; going in to or out of float point registers.
-
-(define_expand "reload_insi"
-  [(set (match_operand:SI 0 "register_operand" "=Z")
-	(match_operand:SI 1 "non_hard_reg_operand" ""))
-   (clobber (match_operand:SI 2 "register_operand" "=&r"))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, SImode, operands[2]))
-    DONE;
-
-  /* We don't want the clobber emitted, so handle this ourselves.  */
-  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
-  DONE;
-}")
-
-(define_expand "reload_outsi"
-  [(set (match_operand:SI 0 "non_hard_reg_operand" "")
-	(match_operand:SI 1  "register_operand" "Z"))
-   (clobber (match_operand:SI 2 "register_operand" "=&r"))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, SImode, operands[2]))
-    DONE;
-
-  /* We don't want the clobber emitted, so handle this ourselves.  */
-  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
-  DONE;
-}")
-
-;;; pic symbol references
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "symbolic_operand" ""))))]
-  "flag_pic && operands[1] == pic_offset_table_rtx"
-  "ldw T'%2(%1),%0"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
-				"=r,r,r,r,r,Q,*q,!f,f,*TR")
-	(match_operand:SI 1 "move_operand"
-				"r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
-  "(register_operand (operands[0], SImode)
-    || reg_or_0_operand (operands[1], SImode))
-   && ! TARGET_SOFT_FLOAT"
-  "@
-   copy %1,%0
-   ldi %1,%0
-   ldil L'%1,%0
-   zdepi %Z1,%0
-   ldw%M1 %1,%0
-   stw%M0 %r1,%0
-   mtsar %r1
-   fcpy,sgl %r1,%0
-   fldw%F1 %1,%0
-   fstw%F0 %1,%0"
-  [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
-   (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
-				"=r,r,r,r,r,Q,*q")
-	(match_operand:SI 1 "move_operand"
-				"r,J,N,K,RQ,rM,rM"))]
-  "(register_operand (operands[0], SImode)
-    || reg_or_0_operand (operands[1], SImode))
-   && TARGET_SOFT_FLOAT"
-  "@
-   copy %1,%0
-   ldi %1,%0
-   ldil L'%1,%0
-   zdepi %Z1,%0
-   ldw%M1 %1,%0
-   stw%M0 %r1,%0
-   mtsar %r1"
-  [(set_attr "type" "move,move,move,move,load,store,move")
-   (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4,4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mem:SI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
-			 (match_operand:SI 2 "register_operand" "r"))))]
-  "! TARGET_DISABLE_INDEXING"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[2] == hard_frame_pointer_rtx
-      || operands[2] == stack_pointer_rtx)
-    return \"ldwx %1(0,%2),%0\";
-  else
-    return \"ldwx %2(0,%1),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "basereg_operand" "r"))))]
-  "! TARGET_DISABLE_INDEXING"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[1] == hard_frame_pointer_rtx
-      || operands[1] == stack_pointer_rtx)
-    return \"ldwx %2(0,%1),%0\";
-  else
-    return \"ldwx %1(0,%2),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-;; Load or store with base-register modification.
-
-(define_insn "pre_ldwm"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
-			 (match_operand:SI 2 "pre_cint_operand" ""))))
-   (set (match_dup 1)
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "*
-{
-  if (INTVAL (operands[2]) < 0)
-    return \"ldwm %2(0,%1),%0\";
-  return \"ldws,mb %2(0,%1),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn "pre_stwm"
-  [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
-			 (match_operand:SI 1 "pre_cint_operand" "")))
-	(match_operand:SI 2 "reg_or_0_operand" "rM"))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0) (match_dup 1)))]
-  ""
-  "*
-{
-  if (INTVAL (operands[1]) < 0)
-    return \"stwm %r2,%1(0,%0)\";
-  return \"stws,mb %r2,%1(0,%0)\";
-}"
-  [(set_attr "type" "store")
-   (set_attr "length" "4")])
-
-(define_insn "post_ldwm"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mem:SI (match_operand:SI 1 "register_operand" "+r")))
-   (set (match_dup 1)
-	(plus:SI (match_dup 1)
-		 (match_operand:SI 2 "post_cint_operand" "")))]
-  ""
-  "*
-{
-  if (INTVAL (operands[2]) > 0)
-    return \"ldwm %2(0,%1),%0\";
-  return \"ldws,ma %2(0,%1),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn "post_stwm"
-  [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
-	(match_operand:SI 1 "reg_or_0_operand" "rM"))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (match_operand:SI 2 "post_cint_operand" "")))]
-  ""
-  "*
-{
-  if (INTVAL (operands[2]) > 0)
-    return \"stwm %r1,%2(0,%0)\";
-  return \"stws,ma %r1,%2(0,%0)\";
-}"
-  [(set_attr "type" "store")
-   (set_attr "length" "4")])
-
-;; For pic
-;; Note since this pattern can be created at reload time (via movsi), all
-;; the same rules for movsi apply here.  (no new pseudos, no temporaries).
-(define_insn "pic_load_label"
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(match_operand:SI 1 "pic_label_operand" ""))]
-  ""
-  "*
-{
-  rtx label_rtx = gen_label_rtx ();
-  rtx xoperands[3];
-  extern FILE *asm_out_file;
-
-  xoperands[0] = operands[0];
-  xoperands[1] = operands[1];
-  xoperands[2] = label_rtx;
-  output_asm_insn (\"bl .+8,%0\", xoperands);
-  output_asm_insn (\"depi 0,31,2,%0\", xoperands);
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
-			     CODE_LABEL_NUMBER (label_rtx));
-
-  /* If we're trying to load the address of a label that happens to be
-     close, then we can use a shorter sequence.  */
-  if (GET_CODE (operands[1]) == LABEL_REF
-      && insn_addresses
-      && abs (insn_addresses[INSN_UID (XEXP (operands[1], 0))]
-	        - insn_addresses[INSN_UID (insn)]) < 8100)
-    {
-      /* Prefixing with R% here is wrong, it extracts just 11 bits and is
-	 always non-negative.  */
-      output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
-    }
-  else
-    {
-      output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
-      output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
-    }
-  return \"\";
-}"
-  [(set_attr "type" "multi")
-   (set_attr "length" "16")])		; 12 or 16
-
-(define_insn "pic2_highpart"
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(plus:SI (match_operand:SI 1 "register_operand" "r")
-		 (high:SI (match_operand 2 "" ""))))]
-  "symbolic_operand (operands[2], Pmode)
-   && ! function_label_operand (operands[2])
-   && flag_pic == 2"
-  "addil LT'%G2,%1"
-  [(set_attr "type" "binary")
-   (set_attr "length" "4")])
-
-; We need this to make sure CSE doesn't simplify a memory load with a
-; symbolic address, whose content it think it knows.  For PIC, what CSE
-; think is the real value will be the address of that value.
-(define_insn "pic2_lo_sum"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mem:SI (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-			   (unspec:SI [(match_operand:SI 2 "symbolic_operand" "")] 0))))]
-  ""
-  "*
-{
-  if (flag_pic != 2)
-    abort ();
-  return \"ldw RT'%G2(%1),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-
-;; Always use addil rather than ldil;add sequences.  This allows the
-;; HP linker to eliminate the dp relocation if the symbolic operand
-;; lives in the TEXT space.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=a")
-	(high:SI (match_operand 1 "" "")))]
-  "symbolic_operand (operands[1], Pmode)
-   && ! function_label_operand (operands[1])
-   && ! read_only_operand (operands[1])
-   && ! flag_pic"
-  "*
-{
-  if (TARGET_LONG_LOAD_STORE)
-    return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
-  else
-    return \"addil LR'%H1,%%r27\";
-}"
-  [(set_attr "type" "binary")
-   (set (attr "length")
-      (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
-		    (const_int 4)
-		    (const_int 8)))])
-
-
-;; This is for use in the prologue/epilogue code.  We need it
-;; to add large constants to a stack pointer or frame pointer.
-;; Because of the additional %r1 pressure, we probably do not
-;; want to use this in general code, so make it available
-;; only after reload.
-(define_insn "add_high_const"
-  [(set (match_operand:SI 0 "register_operand" "=!a,*r")
-	(plus:SI (match_operand:SI 1 "register_operand" "r,r")
-		 (high:SI (match_operand 2 "const_int_operand" ""))))]
-  "reload_completed"
-  "@
-   addil L'%G2,%1
-   ldil L'%G2,%0\;addl %0,%1,%0"
-  [(set_attr "type" "binary,binary")
-   (set_attr "length" "4,8")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(high:SI (match_operand 1 "" "")))]
-  "(!flag_pic || !symbolic_operand (operands[1]), Pmode)
-    && !is_function_label_plus_const (operands[1])"
-  "*
-{
-  if (symbolic_operand (operands[1], Pmode))
-    return \"ldil LR'%H1,%0\";
-  else
-    return \"ldil L'%G1,%0\";
-}"
-  [(set_attr "type" "move")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-		   (match_operand:SI 2 "immediate_operand" "i")))]
-  "!is_function_label_plus_const (operands[2])"
-  "*
-{
-  if (flag_pic && symbolic_operand (operands[2], Pmode))
-    abort ();
-  else if (symbolic_operand (operands[2], Pmode))
-    return \"ldo RR'%G2(%1),%0\";
-  else
-    return \"ldo R'%G2(%1),%0\";
-}"
-  [(set_attr "type" "move")
-   (set_attr "length" "4")])
-
-;; Now that a symbolic_address plus a constant is broken up early
-;; in the compilation phase (for better CSE) we need a special
-;; combiner pattern to load the symbolic address plus the constant
-;; in only 2 instructions. (For cases where the symbolic address
-;; was not a common subexpression.)
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operand:SI 1 "symbolic_operand" ""))
-   (clobber (match_operand:SI 2 "register_operand" ""))]
-  "! (flag_pic && pic_label_operand (operands[1], SImode))"
-  [(set (match_dup 2) (high:SI (match_dup 1)))
-   (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
-  "")
-
-;; hppa_legitimize_address goes to a great deal of trouble to
-;; create addresses which use indexing.  In some cases, this
-;; is a lose because there isn't any store instructions which
-;; allow indexed addresses (with integer register source).
-;;
-;; These define_splits try to turn a 3 insn store into
-;; a 2 insn store with some creative RTL rewriting.
-(define_split
-  [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
-			       (match_operand:SI 1 "shadd_operand" ""))
-		   (plus:SI (match_operand:SI 2 "register_operand" "")
-			    (match_operand:SI 3 "const_int_operand" ""))))
-	(match_operand:SI 4 "register_operand" ""))
-   (clobber (match_operand:SI 5 "register_operand" ""))]
-  ""
-  [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
-			       (match_dup 2)))
-   (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
-  "")
-
-(define_split
-  [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
-			       (match_operand:SI 1 "shadd_operand" ""))
-		   (plus:SI (match_operand:SI 2 "register_operand" "")
-			    (match_operand:SI 3 "const_int_operand" ""))))
-	(match_operand:HI 4 "register_operand" ""))
-   (clobber (match_operand:SI 5 "register_operand" ""))]
-  ""
-  [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
-			       (match_dup 2)))
-   (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
-  "")
-
-(define_split
-  [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
-			       (match_operand:SI 1 "shadd_operand" ""))
-		   (plus:SI (match_operand:SI 2 "register_operand" "")
-			    (match_operand:SI 3 "const_int_operand" ""))))
-	(match_operand:QI 4 "register_operand" ""))
-   (clobber (match_operand:SI 5 "register_operand" ""))]
-  ""
-  [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
-			       (match_dup 2)))
-   (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
-  "")
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, HImode, 0))
-    DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!f")
-	(match_operand:HI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!fM"))]
-  "register_operand (operands[0], HImode)
-   || reg_or_0_operand (operands[1], HImode)"
-  "@
-   copy %1,%0
-   ldi %1,%0
-   ldil L'%1,%0
-   zdepi %Z1,%0
-   ldh%M1 %1,%0
-   sth%M0 %r1,%0
-   mtsar %r1
-   fcpy,sgl %r1,%0"
-  [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
-   (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4,4,4")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(mem:HI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
-			 (match_operand:SI 2 "register_operand" "r"))))]
-  "! TARGET_DISABLE_INDEXING"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[2] == hard_frame_pointer_rtx
-      || operands[2] == stack_pointer_rtx)
-    return \"ldhx %1(0,%2),%0\";
-  else
-    return \"ldhx %2(0,%1),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "basereg_operand" "r"))))]
-  "! TARGET_DISABLE_INDEXING"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[1] == hard_frame_pointer_rtx
-      || operands[1] == stack_pointer_rtx)
-    return \"ldhx %2(0,%1),%0\";
-  else
-    return \"ldhx %1(0,%2),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-; Now zero extended variants.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (mem:HI
-			  (plus:SI
-			    (match_operand:SI 1 "basereg_operand" "r")
-			    (match_operand:SI 2 "register_operand" "r")))))]
-  "! TARGET_DISABLE_INDEXING"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[2] == hard_frame_pointer_rtx
-      || operands[2] == stack_pointer_rtx)
-    return \"ldhx %1(0,%2),%0\";
-  else
-    return \"ldhx %2(0,%1),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (mem:HI
-			  (plus:SI
-			     (match_operand:SI 1 "register_operand" "r")
-			     (match_operand:SI 2 "basereg_operand" "r")))))]
-  "! TARGET_DISABLE_INDEXING"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[1] == hard_frame_pointer_rtx
-      || operands[1] == stack_pointer_rtx)
-    return \"ldhx %2(0,%1),%0\";
-  else
-    return \"ldhx %1(0,%2),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
-			 (match_operand:SI 2 "int5_operand" "L"))))
-   (set (match_dup 1)
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldhs,mb %2(0,%1),%0"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-; And a zero extended variant.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (mem:HI
-			  (plus:SI
-			    (match_operand:SI 1 "register_operand" "+r")
-			    (match_operand:SI 2 "int5_operand" "L")))))
-   (set (match_dup 1)
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldhs,mb %2(0,%1),%0"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
-			 (match_operand:SI 1 "int5_operand" "L")))
-	(match_operand:HI 2 "reg_or_0_operand" "rM"))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0) (match_dup 1)))]
-  ""
-  "sths,mb %r2,%1(0,%0)"
-  [(set_attr "type" "store")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(high:HI (match_operand 1 "const_int_operand" "")))]
-  ""
-  "ldil L'%G1,%0"
-  [(set_attr "type" "move")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(lo_sum:HI (match_operand:HI 1 "register_operand" "r")
-		   (match_operand 2 "const_int_operand" "")))]
-  ""
-  "ldo R'%G2(%1),%0"
-  [(set_attr "type" "move")
-   (set_attr "length" "4")])
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, QImode, 0))
-    DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!f")
-	(match_operand:QI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!fM"))]
-  "register_operand (operands[0], QImode)
-   || reg_or_0_operand (operands[1], QImode)"
-  "@
-   copy %1,%0
-   ldi %1,%0
-   ldil L'%1,%0
-   zdepi %Z1,%0
-   ldb%M1 %1,%0
-   stb%M0 %r1,%0
-   mtsar %r1
-   fcpy,sgl %r1,%0"
-  [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
-   (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4,4,4")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(mem:QI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
-			 (match_operand:SI 2 "register_operand" "r"))))]
-  "! TARGET_DISABLE_INDEXING"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[2] == hard_frame_pointer_rtx
-      || operands[2] == stack_pointer_rtx)
-    return \"ldbx %1(0,%2),%0\";
-  else
-    return \"ldbx %2(0,%1),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "basereg_operand" "r"))))]
-  "! TARGET_DISABLE_INDEXING"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[1] == hard_frame_pointer_rtx
-      || operands[1] == stack_pointer_rtx)
-    return \"ldbx %2(0,%1),%0\";
-  else
-    return \"ldbx %1(0,%2),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-; Indexed byte load with zero extension to SImode or HImode.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (mem:QI
-			  (plus:SI
-			    (match_operand:SI 1 "basereg_operand" "r")
-			    (match_operand:SI 2 "register_operand" "r")))))]
-  "! TARGET_DISABLE_INDEXING"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[2] == hard_frame_pointer_rtx
-      || operands[2] == stack_pointer_rtx)
-    return \"ldbx %1(0,%2),%0\";
-  else
-    return \"ldbx %2(0,%1),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (mem:QI
-			  (plus:SI
-			    (match_operand:SI 1 "register_operand" "r")
-			    (match_operand:SI 2 "basereg_operand" "r")))))]
-  "! TARGET_DISABLE_INDEXING"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[1] == hard_frame_pointer_rtx
-      || operands[1] == stack_pointer_rtx)
-    return \"ldbx %2(0,%1),%0\";
-  else
-    return \"ldbx %1(0,%2),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(zero_extend:HI (mem:QI
-			  (plus:SI
-			    (match_operand:SI 1 "basereg_operand" "r")
-			    (match_operand:SI 2 "register_operand" "r")))))]
-  "! TARGET_DISABLE_INDEXING"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[2] == hard_frame_pointer_rtx
-      || operands[2] == stack_pointer_rtx)
-    return \"ldbx %1(0,%2),%0\";
-  else
-    return \"ldbx %2(0,%1),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(zero_extend:HI (mem:QI
-			  (plus:SI
-			    (match_operand:SI 1 "register_operand" "r")
-			    (match_operand:SI 2 "basereg_operand" "r")))))]
-  "! TARGET_DISABLE_INDEXING"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[1] == hard_frame_pointer_rtx
-      || operands[1] == stack_pointer_rtx)
-    return \"ldbx %2(0,%1),%0\";
-  else
-    return \"ldbx %1(0,%2),%0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
-			 (match_operand:SI 2 "int5_operand" "L"))))
-   (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldbs,mb %2(0,%1),%0"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-; Now the same thing with zero extensions.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (mem:QI (plus:SI
-				  (match_operand:SI 1 "register_operand" "+r")
-				  (match_operand:SI 2 "int5_operand" "L")))))
-   (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldbs,mb %2(0,%1),%0"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(zero_extend:HI (mem:QI (plus:SI
-				  (match_operand:SI 1 "register_operand" "+r")
-				  (match_operand:SI 2 "int5_operand" "L")))))
-   (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "ldbs,mb %2(0,%1),%0"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
-			 (match_operand:SI 1 "int5_operand" "L")))
-	(match_operand:QI 2 "reg_or_0_operand" "rM"))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0) (match_dup 1)))]
-  ""
-  "stbs,mb %r2,%1(0,%0)"
-  [(set_attr "type" "store")
-   (set_attr "length" "4")])
-
-;; The definition of this insn does not really explain what it does,
-;; but it should suffice
-;; that anything generated as this insn will be recognized as one
-;; and that it will not successfully combine with anything.
-(define_expand "movstrsi"
-  [(parallel [(set (match_operand:BLK 0 "" "")
-		   (match_operand:BLK 1 "" ""))
-	      (clobber (match_dup 7))
-	      (clobber (match_dup 8))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))
-	      (use (match_operand:SI 2 "arith_operand" ""))
-	      (use (match_operand:SI 3 "const_int_operand" ""))])]
-  ""
-  "
-{
-  int size, align;
-
-  /* HP provides very fast block move library routine for the PA;
-     this routine includes:
-
-	4x4 byte at a time block moves,
-	1x4 byte at a time with alignment checked at runtime with
-	    attempts to align the source and destination as needed
-	1x1 byte loop
-
-     With that in mind, here's the heuristics to try and guess when
-     the inlined block move will be better than the library block
-     move:
-
-	If the size isn't constant, then always use the library routines.
-
-	If the size is large in respect to the known alignment, then use
-	the library routines.
-
-	If the size is small in repsect to the known alignment, then open
-	code the copy (since that will lead to better scheduling).
-
-        Else use the block move pattern.   */
-
-  /* Undetermined size, use the library routine.  */
-  if (GET_CODE (operands[2]) != CONST_INT)
-    FAIL;
-
-  size = INTVAL (operands[2]);
-  align = INTVAL (operands[3]);
-  align = align > 4 ? 4 : align;
-
-  /* If size/alignment > 8 (eg size is large in respect to alignment),
-     then use the library routines.  */
-  if (size / align > 16)
-    FAIL;
-
-  /* This does happen, but not often enough to worry much about.  */
-  if (size / align < MOVE_RATIO)
-    FAIL;
-  
-  /* Fall through means we're going to use our block move pattern.  */
-  operands[0]
-    = change_address (operands[0], VOIDmode,
-		      copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
-  operands[1]
-    = change_address (operands[1], VOIDmode,
-		      copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
-  operands[4] = gen_reg_rtx (SImode);
-  operands[5] = gen_reg_rtx (SImode);
-  operands[6] = gen_reg_rtx (SImode);
-  operands[7] = XEXP (operands[0], 0);
-  operands[8] = XEXP (operands[1], 0);
-}")
-
-;; The operand constraints are written like this to support both compile-time
-;; and run-time determined byte count.  If the count is run-time determined,
-;; the register with the byte count is clobbered by the copying code, and
-;; therefore it is forced to operand 2.  If the count is compile-time
-;; determined, we need two scratch registers for the unrolled code.
-(define_insn "movstrsi_internal"
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
-   (clobber (match_dup 0))
-   (clobber (match_dup 1))
-   (clobber (match_operand:SI 2 "register_operand" "=r,r"))	;loop cnt/tmp
-   (clobber (match_operand:SI 3 "register_operand" "=&r,&r"))	;item tmp
-   (clobber (match_operand:SI 6 "register_operand" "=&r,&r"))	;item tmp2
-   (use (match_operand:SI 4 "arith_operand" "J,2"))	 ;byte count
-   (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
-  ""
-  "* return output_block_move (operands, !which_alternative);"
-  [(set_attr "type" "multi,multi")])
-
-;; Floating point move insns
-
-;; This pattern forces (set (reg:DF ...) (const_double ...))
-;; to be reloaded by putting the constant into memory when
-;; reg is a floating point register.
-;;
-;; For integer registers we use ldil;ldo to set the appropriate
-;; value.
-;;
-;; This must come before the movdf pattern, and it must be present
-;; to handle obscure reloading cases.
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=?r,f")
-	(match_operand:DF 1 "" "?F,m"))]
-  "GET_CODE (operands[1]) == CONST_DOUBLE
-   && operands[1] != CONST0_RTX (DFmode)
-   && ! TARGET_SOFT_FLOAT"
-  "* return (which_alternative == 0 ? output_move_double (operands)
-				    : \"fldd%F1 %1,%0\");"
-  [(set_attr "type" "move,fpload")
-   (set_attr "length" "16,4")])
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, DFmode, 0))
-    DONE;
-}")
-
-;; Reloading an SImode or DImode value requires a scratch register if
-;; going in to or out of float point registers.
-
-(define_expand "reload_indf"
-  [(set (match_operand:DF 0 "register_operand" "=Z")
-	(match_operand:DF 1 "non_hard_reg_operand" ""))
-   (clobber (match_operand:DF 2 "register_operand" "=&r"))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, DFmode, operands[2]))
-    DONE;
-
-  /* We don't want the clobber emitted, so handle this ourselves.  */
-  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
-  DONE;
-}")
-
-(define_expand "reload_outdf" 
- [(set (match_operand:DF 0 "non_hard_reg_operand" "")
-	(match_operand:DF 1  "register_operand" "Z"))
-   (clobber (match_operand:DF 2 "register_operand" "=&r"))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, DFmode, operands[2]))
-    DONE;
-
-  /* We don't want the clobber emitted, so handle this ourselves.  */
-  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
-			  "=f,*r,RQ,?o,?Q,f,*r,*r")
-	(match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
-			  "fG,*rG,f,*r,*r,RQ,o,RQ"))]
-  "(register_operand (operands[0], DFmode)
-    || reg_or_0_operand (operands[1], DFmode))
-   && ! (GET_CODE (operands[1]) == CONST_DOUBLE
-	 && GET_CODE (operands[0]) == MEM)
-   && ! TARGET_SOFT_FLOAT"
-  "*
-{
-  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
-      || operands[1] == CONST0_RTX (DFmode))
-    return output_fp_move_double (operands);
-  return output_move_double (operands);
-}"
-  [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
-   (set_attr "length" "4,8,4,8,16,4,8,16")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
-			  "=r,?o,?Q,r,r")
-	(match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
-			  "rG,r,r,o,Q"))]
-  "(register_operand (operands[0], DFmode)
-    || reg_or_0_operand (operands[1], DFmode))
-   && TARGET_SOFT_FLOAT"
-  "*
-{
-  return output_move_double (operands);
-}"
-  [(set_attr "type" "move,store,store,load,load")
-   (set_attr "length" "8,8,16,8,16")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=fx")
-	(mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
-			 (match_operand:SI 2 "register_operand" "r"))))]
-  "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[2] == hard_frame_pointer_rtx
-      || operands[2] == stack_pointer_rtx)
-    return \"flddx %1(0,%2),%0\";
-  else
-    return \"flddx %2(0,%1),%0\";
-}"
-  [(set_attr "type" "fpload")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=fx")
-	(mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "basereg_operand" "r"))))]
-  "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[1] == hard_frame_pointer_rtx
-      || operands[1] == stack_pointer_rtx)
-    return \"flddx %2(0,%1),%0\";
-  else
-    return \"flddx %1(0,%2),%0\";
-}"
-  [(set_attr "type" "fpload")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
-			 (match_operand:SI 2 "register_operand" "r")))
-	(match_operand:DF 0 "register_operand" "fx"))]
-  "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[2] == hard_frame_pointer_rtx
-      || operands[2] == stack_pointer_rtx)
-    return \"fstdx %0,%1(0,%2)\";
-  else
-    return \"fstdx %0,%2(0,%1)\";
-}"
-  [(set_attr "type" "fpstore")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "basereg_operand" "r")))
-	(match_operand:DF 0 "register_operand" "fx"))]
-  "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[1] == hard_frame_pointer_rtx
-      || operands[1] == stack_pointer_rtx)
-    return \"fstdx %0,%2(0,%1)\";
-  else
-    return \"fstdx %0,%1(0,%2)\";
-}"
-  [(set_attr "type" "fpstore")
-   (set_attr "length" "4")])
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, DImode, 0))
-    DONE;
-}")
-
-(define_expand "reload_indi"
-  [(set (match_operand:DI 0 "register_operand" "=f")
-	(match_operand:DI 1 "non_hard_reg_operand" ""))
-   (clobber (match_operand:SI 2 "register_operand" "=&r"))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, DImode, operands[2]))
-    DONE;
-
-  /* We don't want the clobber emitted, so handle this ourselves.  */
-  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
-  DONE;
-}")
-
-(define_expand "reload_outdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "register_operand" "f"))
-   (clobber (match_operand:SI 2 "register_operand" "=&r"))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, DImode, operands[2]))
-    DONE;
-
-  /* We don't want the clobber emitted, so handle this ourselves.  */
-  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(high:DI (match_operand 1 "" "")))]
-  ""
-  "*
-{
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-
-  if (GET_CODE (op1) == CONST_INT)
-    {
-      operands[0] = operand_subword (op0, 1, 0, DImode);
-      output_asm_insn (\"ldil L'%1,%0\", operands);
-
-      operands[0] = operand_subword (op0, 0, 0, DImode);
-      if (INTVAL (op1) < 0)
-	output_asm_insn (\"ldi -1,%0\", operands);
-      else
-	output_asm_insn (\"ldi 0,%0\", operands);
-      return \"\";
-    }
-  else if (GET_CODE (op1) == CONST_DOUBLE)
-    {
-      operands[0] = operand_subword (op0, 1, 0, DImode);
-      operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
-      output_asm_insn (\"ldil L'%1,%0\", operands);
-
-      operands[0] = operand_subword (op0, 0, 0, DImode);
-      operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
-      output_asm_insn (singlemove_string (operands), operands);
-      return \"\";
-    }
-  else
-    abort ();
-}"
-  [(set_attr "type" "move")
-   (set_attr "length" "8")])
-
-;;; Experimental
-
-(define_insn ""
-  [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
-			  "=r,o,Q,r,r,r,f,f,*TR")
-	(match_operand:DI 1 "general_operand"
-			  "rM,r,r,o*R,Q,i,fM,*TR,f"))]
-  "(register_operand (operands[0], DImode)
-    || reg_or_0_operand (operands[1], DImode))
-   && ! TARGET_SOFT_FLOAT"
-  "*
-{
-  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
-      || (operands[1] == CONST0_RTX (DImode)))
-    return output_fp_move_double (operands);
-  return output_move_double (operands);
-}"
-  [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
-   (set_attr "length" "8,8,16,8,16,16,4,4,4")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
-			  "=r,o,Q,r,r,r")
-	(match_operand:DI 1 "general_operand"
-			  "rM,r,r,o,Q,i"))]
-  "(register_operand (operands[0], DImode)
-    || reg_or_0_operand (operands[1], DImode))
-   && TARGET_SOFT_FLOAT"
-  "*
-{
-  return output_move_double (operands);
-}"
-  [(set_attr "type" "move,store,store,load,load,multi")
-   (set_attr "length" "8,8,16,8,16,16")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r,&r")
-	(lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
-		   (match_operand:DI 2 "immediate_operand" "i,i")))]
-  ""
-  "*
-{
-  /* Don't output a 64 bit constant, since we can't trust the assembler to
-     handle it correctly.  */
-  if (GET_CODE (operands[2]) == CONST_DOUBLE)
-    operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
-  if (which_alternative == 1)
-    output_asm_insn (\"copy %1,%0\", operands);
-  return \"ldo R'%G2(%R1),%R0\";
-}"
-  [(set_attr "type" "move,move")
-   (set_attr "length" "4,8")])
-
-;; This pattern forces (set (reg:SF ...) (const_double ...))
-;; to be reloaded by putting the constant into memory when
-;; reg is a floating point register.
-;;
-;; For integer registers we use ldil;ldo to set the appropriate
-;; value.
-;;
-;; This must come before the movsf pattern, and it must be present
-;; to handle obscure reloading cases.
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=?r,f")
-	(match_operand:SF 1 "" "?F,m"))]
-  "GET_CODE (operands[1]) == CONST_DOUBLE
-   && operands[1] != CONST0_RTX (SFmode)
-   && ! TARGET_SOFT_FLOAT"
-  "* return (which_alternative == 0 ? singlemove_string (operands)
-				    : \" fldw%F1 %1,%0\");"
-  [(set_attr "type" "move,fpload")
-   (set_attr "length" "8,4")])
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, SFmode, 0))
-    DONE;
-}")
-
-;; Reloading an SImode or DImode value requires a scratch register if
-;; going in to or out of float point registers.
-
-(define_expand "reload_insf"
-  [(set (match_operand:SF 0 "register_operand" "=Z")
-	(match_operand:SF 1 "non_hard_reg_operand" ""))
-   (clobber (match_operand:SF 2 "register_operand" "=&r"))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, SFmode, operands[2]))
-    DONE;
-
-  /* We don't want the clobber emitted, so handle this ourselves.  */
-  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
-  DONE;
-}")
-
-(define_expand "reload_outsf"
-  [(set (match_operand:SF 0 "non_hard_reg_operand" "")
-	(match_operand:SF 1  "register_operand" "Z"))
-   (clobber (match_operand:SF 2 "register_operand" "=&r"))]
-  ""
-  "
-{
-  if (emit_move_sequence (operands, SFmode, operands[2]))
-    DONE;
-
-  /* We don't want the clobber emitted, so handle this ourselves.  */
-  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
-			  "=f,r,f,r,RQ,Q")
-	(match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
-			  "fG,rG,RQ,RQ,f,rG"))]
-  "(register_operand (operands[0], SFmode)
-    || reg_or_0_operand (operands[1], SFmode))
-   && ! TARGET_SOFT_FLOAT"
-  "@
-   fcpy,sgl %r1,%0
-   copy %r1,%0
-   fldw%F1 %1,%0
-   ldw%M1 %1,%0
-   fstw%F0 %r1,%0
-   stw%M0 %r1,%0"
-  [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
-   (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
-			  "=r,r,Q")
-	(match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
-			  "rG,RQ,rG"))]
-  "(register_operand (operands[0], SFmode)
-    || reg_or_0_operand (operands[1], SFmode))
-   && TARGET_SOFT_FLOAT"
-  "@
-   copy %r1,%0
-   ldw%M1 %1,%0
-   stw%M0 %r1,%0"
-  [(set_attr "type" "move,load,store")
-   (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=fx")
-	(mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
-			 (match_operand:SI 2 "register_operand" "r"))))]
-  "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[2] == hard_frame_pointer_rtx
-      || operands[2] == stack_pointer_rtx)
-    return \"fldwx %1(0,%2),%0\";
-  else
-    return \"fldwx %2(0,%1),%0\";
-}"
-  [(set_attr "type" "fpload")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=fx")
-	(mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "basereg_operand" "r"))))]
-  "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[1] == hard_frame_pointer_rtx
-      || operands[1] == stack_pointer_rtx)
-    return \"fldwx %2(0,%1),%0\";
-  else
-    return \"fldwx %1(0,%2),%0\";
-}"
-  [(set_attr "type" "fpload")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
-			 (match_operand:SI 2 "register_operand" "r")))
-      (match_operand:SF 0 "register_operand" "fx"))]
-  "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[2] == hard_frame_pointer_rtx
-      || operands[2] == stack_pointer_rtx)
-    return \"fstwx %0,%1(0,%2)\";
-  else
-    return \"fstwx %0,%2(0,%1)\";
-}"
-  [(set_attr "type" "fpstore")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "basereg_operand" "r")))
-      (match_operand:SF 0 "register_operand" "fx"))]
-  "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
-  "*
-{
-  /* Reload can create backwards (relative to cse) unscaled index
-     address modes when eliminating registers and possibly for
-     pseudos that don't get hard registers.  Deal with it.  */
-  if (operands[1] == hard_frame_pointer_rtx
-      || operands[1] == stack_pointer_rtx)
-    return \"fstwx %0,%2(0,%1)\";
-  else
-    return \"fstwx %0,%1(0,%2)\";
-}"
-  [(set_attr "type" "fpstore")
-   (set_attr "length" "4")])
-
-
-;;- zero extension instructions
-;; We have define_expand for zero extension patterns to make sure the
-;; operands get loaded into registers.  The define_insns accept
-;; memory operands.  This gives us better overall code than just
-;; having a pattern that does or does not accept memory operands.
-
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI
-	 (match_operand:HI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(zero_extend:SI
-	 (match_operand:HI 1 "move_operand" "r,RQ")))]
-  "GET_CODE (operands[1]) != CONST_INT"
-  "@
-   extru %1,31,16,%0
-   ldh%M1 %1,%0"
-  [(set_attr "type" "shift,load")
-   (set_attr "length" "4,4")])
-
-(define_expand "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(zero_extend:HI
-	 (match_operand:QI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(zero_extend:HI
-	 (match_operand:QI 1 "move_operand" "r,RQ")))]
-  "GET_CODE (operands[1]) != CONST_INT"
-  "@
-   extru %1,31,8,%0
-   ldb%M1 %1,%0"
-  [(set_attr "type" "shift,load")
-   (set_attr "length" "4,4")])
-
-(define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI
-	 (match_operand:QI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(zero_extend:SI
-	 (match_operand:QI 1 "move_operand" "r,RQ")))]
-  "GET_CODE (operands[1]) != CONST_INT"
-  "@
-   extru %1,31,8,%0
-   ldb%M1 %1,%0"
-  [(set_attr "type" "shift,load")
-   (set_attr "length" "4,4")])
-
-;;- sign extension instructions
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
-  ""
-  "extrs %1,31,16,%0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
-  ""
-  "extrs %1,31,8,%0"
-  [(set_attr "type" "shift") 
-  (set_attr "length" "4")])
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
-  ""
-  "extrs %1,31,8,%0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-;; Conversions between float and double.
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float_extend:DF
-	 (match_operand:SF 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fcnvff,sgl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float_truncate:SF
-	 (match_operand:DF 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fcnvff,dbl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-;; Conversion between fixed point and floating point.
-;; Note that among the fix-to-float insns
-;; the ones that start with SImode come first.
-;; That is so that an operand that is a CONST_INT
-;; (and therefore lacks a specific machine mode).
-;; will be recognized as SImode (which is always valid)
-;; rather than as QImode or HImode.
-
-;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
-;; to be reloaded by putting the constant into memory.
-;; It must come before the more general floatsisf2 pattern.
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float:SF (match_operand:SI 1 "const_int_operand" "m")))]
-  "! TARGET_SOFT_FLOAT"
-  "fldw%F1 %1,%0\;fcnvxf,sgl,sgl %0,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "8")])
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float:SF (match_operand:SI 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fcnvxf,sgl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-
-;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
-;; to be reloaded by putting the constant into memory.
-;; It must come before the more general floatsidf2 pattern.
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float:DF (match_operand:SI 1 "const_int_operand" "m")))]
-  "! TARGET_SOFT_FLOAT"
-  "fldw%F1 %1,%0\;fcnvxf,sgl,dbl %0,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "8")])
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float:DF (match_operand:SI 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fcnvxf,sgl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-;; CYGNUS LOCAL pa8000/law */
-(define_expand "floatunssisf2"
-  [(set (subreg:SI (match_dup 2) 1)
-	(match_operand:SI 1 "register_operand" ""))
-   (set (subreg:SI (match_dup 2) 0)
-	(const_int 0))
-   (set (match_operand:SF 0 "register_operand" "")
-	(float:SF (match_dup 2)))]
-  "TARGET_SNAKE && ! TARGET_SOFT_FLOAT"
-  "
-{
-  if (TARGET_PARISC_2_0)
-    {
-      emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
-      DONE;
-    }
-  operands[2] = gen_reg_rtx (DImode);
-}")
-
-(define_expand "floatunssidf2"
-  [(set (subreg:SI (match_dup 2) 1)
-	(match_operand:SI 1 "register_operand" ""))
-   (set (subreg:SI (match_dup 2) 0)
-	(const_int 0))
-   (set (match_operand:DF 0 "register_operand" "")
-	(float:DF (match_dup 2)))]
-  "TARGET_SNAKE && ! TARGET_SOFT_FLOAT"
-  "
-{
-  if (TARGET_PARISC_2_0)
-    {
-      emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
-      DONE;
-    }
-  operands[2] = gen_reg_rtx (DImode);
-}")
-;; END CYGNUS LOCAL
-
-(define_insn "floatdisf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float:SF (match_operand:DI 1 "register_operand" "f")))]
-  "TARGET_SNAKE && ! TARGET_SOFT_FLOAT"
-  "fcnvxf,dbl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "floatdidf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(float:DF (match_operand:DI 1 "register_operand" "f")))]
-  "TARGET_SNAKE && ! TARGET_SOFT_FLOAT"
-  "fcnvxf,dbl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-;; Convert a float to an actual integer.
-;; Truncation is performed as part of the conversion.
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=f")
-	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
-  "! TARGET_SOFT_FLOAT"
-  "fcnvfxt,sgl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=f")
-	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
-  "! TARGET_SOFT_FLOAT"
-  "fcnvfxt,dbl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "fix_truncsfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=f")
-	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
-  "TARGET_SNAKE && ! TARGET_SOFT_FLOAT"
-  "fcnvfxt,sgl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "fix_truncdfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=f")
-	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
-  "TARGET_SNAKE && ! TARGET_SOFT_FLOAT"
-  "fcnvfxt,dbl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-;; CYGNUS LOCAL pa8000/law
-(define_insn "floatunssidf2_pa20"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fcnvuf,sgl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "floatunssisf2_pa20"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fcnvuf,sgl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "floatunsdisf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fcnvuf,dbl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "floatunsdidf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fcnvuf,dbl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "fixuns_truncsfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=f")
-	(unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fcnvfut,sgl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "fixuns_truncdfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=f")
-	(unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fcnvfut,dbl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "fixuns_truncsfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=f")
-	(unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fcnvfut,sgl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "fixuns_truncdfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=f")
-	(unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fcnvfut,dbl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-;; END CYGNUS LOCAL
-
-;;- arithmetic instructions
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_operand:DI 1 "register_operand" "%r")
-		 (match_operand:DI 2 "arith11_operand" "rI")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) >= 0)
-	return \"addi %2,%R1,%R0\;addc %1,0,%0\";
-      else
-	return \"addi %2,%R1,%R0\;subb %1,0,%0\";
-    }
-  else
-    return \"add %R2,%R1,%R0\;addc %2,%1,%0\";
-}"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
-		 (match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "uaddcm %2,%1,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "4")])
-
-;; define_splits to optimize cases of adding a constant integer
-;; to a register when the constant does not fit in 14 bits.  */
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "const_int_operand" "")))
-   (clobber (match_operand:SI 4 "register_operand" ""))]
-  "! cint_ok_for_move (INTVAL (operands[2]))
-   && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
-  [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
-  "
-{
-  int val = INTVAL (operands[2]);
-  int low = (val < 0) ? -0x2000 : 0x1fff;
-  int rest = val - low;
-
-  operands[2] = GEN_INT (rest);
-  operands[3] = GEN_INT (low);
-}")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "const_int_operand" "")))
-   (clobber (match_operand:SI 4 "register_operand" ""))]
-  "! cint_ok_for_move (INTVAL (operands[2]))"
-  [(set (match_dup 4) (match_dup 2))
-   (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
-			       (match_dup 1)))]
-  "
-{
-  HOST_WIDE_INT intval = INTVAL (operands[2]);
-
-  /* Try dividing the constant by 2, then 4, and finally 8 to see
-     if we can get a constant which can be loaded into a register
-     in a single instruction (cint_ok_for_move). 
-
-     If that fails, try to negate the constant and subtract it
-     from our input operand.  */
-  if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
-    {
-      operands[2] = GEN_INT (intval / 2);
-      operands[3] = GEN_INT (2);
-    }
-  else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
-    {
-      operands[2] = GEN_INT (intval / 4);
-      operands[3] = GEN_INT (4);
-    }
-  else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
-    {
-      operands[2] = GEN_INT (intval / 8);
-      operands[3] = GEN_INT (8);
-    }
-  else if (cint_ok_for_move (-intval))
-    {
-      emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
-      emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
-      DONE;
-    }
-  else
-    FAIL;
-}")
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (match_operand:SI 1 "register_operand" "%r,r")
-		 (match_operand:SI 2 "arith_operand" "r,J")))]
-  ""
-  "@
-   addl %1,%2,%0
-   ldo %2(%1),%0"
-  [(set_attr "type" "binary,binary")
-   (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4")])
-
-;; Disgusting kludge to work around reload bugs with frame pointer
-;; elimination.  Similar to other magic reload patterns in the
-;; indexed memory operations.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(plus:SI (plus:SI (match_operand:SI 1 "register_operand" "%r")
-			  (match_operand:SI 2 "register_operand" "r"))
-		 (match_operand:SI 3 "const_int_operand" "rL")))]
-  "reload_in_progress"
-  "*
-{
-  if (GET_CODE (operands[3]) == CONST_INT)
-    return \"ldo %3(%2),%0\;addl %1,%0,%0\";
-  else
-    return \"addl %3,%2,%0\;addl %1,%0,%0\";
-}"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "register_operand" "r")
-		  (match_operand:DI 2 "register_operand" "r")))]
-  ""
-  "sub %R1,%R2,%R0\;subb %1,%2,%0"
-  [(set_attr "type" "binary")
-  (set_attr "length" "8")])
-
-;; CYGNUS LOCAL PA8000/law
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 1 "arith11_operand" "")
-		  (match_operand:SI 2 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
-		  (match_operand:SI 2 "register_operand" "r,r")))]
-  "!TARGET_PARISC_2_0"
-  "@
-   sub %1,%2,%0
-   subi %1,%2,%0"
-  [(set_attr "type" "binary,binary")
-   (set_attr "length" "4,4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,q")
-	(minus:SI (match_operand:SI 1 "arith11_operand" "r,I,S")
-		  (match_operand:SI 2 "register_operand" "r,r,r")))]
-  "TARGET_PARISC_2_0"
-  "@
-   sub %1,%2,%0
-   subi %1,%2,%0
-   mtsarcm %2"
-  [(set_attr "type" "binary,binary,move")
-   (set_attr "length" "4,4,4")])
-;; END CYGNUS LOCAL
-
-;; Clobbering a "register_operand" instead of a match_scratch
-;; in operand3 of millicode calls avoids spilling %r1 and
-;; produces better code.
-
-;; The mulsi3 insns set up registers for the millicode call.
-(define_expand "mulsi3"
-  [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
-   (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
-   (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
-	      (clobber (match_dup 3))
-	      (clobber (reg:SI 26))
-	      (clobber (reg:SI 25))
-	      (clobber (reg:SI 31))])
-   (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
-  ""
-  "
-{
-  if (TARGET_SNAKE && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT)
-    {
-      rtx scratch = gen_reg_rtx (DImode);
-      operands[1] = force_reg (SImode, operands[1]);
-      operands[2] = force_reg (SImode, operands[2]);
-      emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
-      emit_insn (gen_rtx_SET (VOIDmode,
-			      operands[0],
-			      gen_rtx_SUBREG (SImode, scratch, 1)));
-      DONE;
-    }
-  operands[3] = gen_reg_rtx (SImode);
-}")
-
-(define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
-		 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
-  "TARGET_SNAKE && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
-  "xmpyu %1,%2,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
-		 (match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_SNAKE && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
-  "xmpyu %1,%R2,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
-   (clobber (match_operand:SI 0 "register_operand" "=a"))
-   (clobber (reg:SI 26))
-   (clobber (reg:SI 25))
-   (clobber (reg:SI 31))]
-  ""
-  "* return output_mul_insn (0, insn);"
-  [(set_attr "type" "milli")
-   (set (attr "length")
-     (cond [
-;; Target (or stub) within reach
-            (and (lt (plus (symbol_ref "total_code_bytes") (pc))
-                     (const_int 240000))
-                 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-                     (const_int 0)))
-            (const_int 4)
-
-;; NO_SPACE_REGS
-            (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
-                (const_int 0))
-            (const_int 8)
-
-;; Out of reach, but not PIC or PORTABLE_RUNTIME
-;; same as NO_SPACE_REGS code
-            (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-                     (const_int 0))
-                 (eq (symbol_ref "flag_pic")
-                     (const_int 0)))
-            (const_int 8)]
-
-;; Out of range and either PIC or PORTABLE_RUNTIME
-	  (const_int 24)))])
-
-;;; Division and mod.
-(define_expand "divsi3"
-  [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
-   (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
-   (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
-	      (clobber (match_dup 3))
-	      (clobber (reg:SI 26))
-	      (clobber (reg:SI 25))
-	      (clobber (reg:SI 31))])
-   (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
-  ""
-  "
-{
-  operands[3] = gen_reg_rtx (SImode);
-  if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
-    DONE;
-}")
-
-(define_insn ""
-  [(set (reg:SI 29)
-	(div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
-   (clobber (match_operand:SI 1 "register_operand" "=a"))
-   (clobber (reg:SI 26))
-   (clobber (reg:SI 25))
-   (clobber (reg:SI 31))]
-  ""
-  "*
-   return output_div_insn (operands, 0, insn);"
-  [(set_attr "type" "milli")
-   (set (attr "length")
-     (cond [
-;; Target (or stub) within reach
-            (and (lt (plus (symbol_ref "total_code_bytes") (pc))
-                     (const_int 240000))
-                 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-                     (const_int 0)))
-            (const_int 4)
-
-;; NO_SPACE_REGS
-            (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
-                (const_int 0))
-            (const_int 8)
-
-;; Out of reach, but not PIC or PORTABLE_RUNTIME
-;; same as NO_SPACE_REGS code
-            (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-                     (const_int 0))
-                 (eq (symbol_ref "flag_pic")
-                     (const_int 0)))
-            (const_int 8)]
-
-;; Out of range and either PIC or PORTABLE_RUNTIME
-	  (const_int 24)))])
-
-(define_expand "udivsi3"
-  [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
-   (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
-   (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
-	      (clobber (match_dup 3))
-	      (clobber (reg:SI 26))
-	      (clobber (reg:SI 25))
-	      (clobber (reg:SI 31))])
-   (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
-  ""
-  "
-{
-  operands[3] = gen_reg_rtx (SImode);
-  if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
-    DONE;
-}")
-
-(define_insn ""
-  [(set (reg:SI 29)
-	(udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
-   (clobber (match_operand:SI 1 "register_operand" "=a"))
-   (clobber (reg:SI 26))
-   (clobber (reg:SI 25))
-   (clobber (reg:SI 31))]
-  ""
-  "*
-   return output_div_insn (operands, 1, insn);"
-  [(set_attr "type" "milli")
-   (set (attr "length")
-     (cond [
-;; Target (or stub) within reach
-            (and (lt (plus (symbol_ref "total_code_bytes") (pc))
-                     (const_int 240000))
-                 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-                     (const_int 0)))
-            (const_int 4)
-
-;; NO_SPACE_REGS
-            (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
-                (const_int 0))
-            (const_int 8)
-
-;; Out of reach, but not PIC or PORTABLE_RUNTIME
-;; same as NO_SPACE_REGS code
-            (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-                     (const_int 0))
-                 (eq (symbol_ref "flag_pic")
-                     (const_int 0)))
-            (const_int 8)]
-
-;; Out of range and either PIC or PORTABLE_RUNTIME
-	  (const_int 24)))])
-
-(define_expand "modsi3"
-  [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
-   (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
-   (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
-	      (clobber (match_dup 3))
-	      (clobber (reg:SI 26))
-	      (clobber (reg:SI 25))
-	      (clobber (reg:SI 31))])
-   (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
-  ""
-  "
-{
-  operands[3] = gen_reg_rtx (SImode);
-}")
-
-(define_insn ""
-  [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
-   (clobber (match_operand:SI 0 "register_operand" "=a"))
-   (clobber (reg:SI 26))
-   (clobber (reg:SI 25))
-   (clobber (reg:SI 31))]
-  ""
-  "*
-  return output_mod_insn (0, insn);"
-  [(set_attr "type" "milli")
-   (set (attr "length")
-     (cond [
-;; Target (or stub) within reach
-            (and (lt (plus (symbol_ref "total_code_bytes") (pc))
-                     (const_int 240000))
-                 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-                     (const_int 0)))
-            (const_int 4)
-
-;; NO_SPACE_REGS
-            (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
-                (const_int 0))
-            (const_int 8)
-
-;; Out of reach, but not PIC or PORTABLE_RUNTIME
-;; same as NO_SPACE_REGS code
-            (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-                     (const_int 0))
-                 (eq (symbol_ref "flag_pic")
-                     (const_int 0)))
-            (const_int 8)]
-
-;; Out of range and either PIC or PORTABLE_RUNTIME
-	  (const_int 24)))])
-
-(define_expand "umodsi3"
-  [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
-   (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
-   (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
-	      (clobber (match_dup 3))
-	      (clobber (reg:SI 26))
-	      (clobber (reg:SI 25))
-	      (clobber (reg:SI 31))])
-   (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
-  ""
-  "
-{
-  operands[3] = gen_reg_rtx (SImode);
-}")
-
-(define_insn ""
-  [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
-   (clobber (match_operand:SI 0 "register_operand" "=a"))
-   (clobber (reg:SI 26))
-   (clobber (reg:SI 25))
-   (clobber (reg:SI 31))]
-  ""
-  "*
-  return output_mod_insn (1, insn);"
-  [(set_attr "type" "milli")
-   (set (attr "length")
-     (cond [
-;; Target (or stub) within reach
-            (and (lt (plus (symbol_ref "total_code_bytes") (pc))
-                     (const_int 240000))
-                 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-                     (const_int 0)))
-            (const_int 4)
-
-;; NO_SPACE_REGS
-            (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
-                (const_int 0))
-            (const_int 8)
-
-;; Out of reach, but not PIC or PORTABLE_RUNTIME
-;; same as NO_SPACE_REGS code
-            (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-                     (const_int 0))
-                 (eq (symbol_ref "flag_pic")
-                     (const_int 0)))
-            (const_int 8)]
-
-;; Out of range and either PIC or PORTABLE_RUNTIME
-	  (const_int 24)))])
-
-;;- and instructions
-;; We define DImode `and` so with DImode `not` we can get
-;; DImode `andn`.  Other combinations are possible.
-
-(define_expand "anddi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(and:DI (match_operand:DI 1 "arith_double_operand" "")
-		(match_operand:DI 2 "arith_double_operand" "")))]
-  ""
-  "
-{
-  if (! register_operand (operands[1], DImode)
-      || ! register_operand (operands[2], DImode))
-    /* Let GCC break this into word-at-a-time operations.  */
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI (match_operand:DI 1 "register_operand" "%r")
-		(match_operand:DI 2 "register_operand" "r")))]
-  ""
-  "and %1,%2,%0\;and %R1,%R2,%R0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-; The ? for op1 makes reload prefer zdepi instead of loading a huge
-; constant with ldil;ldo.
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(and:SI (match_operand:SI 1 "register_operand" "%?r,0")
-		(match_operand:SI 2 "and_operand" "rO,P")))]
-  ""
-  "* return output_and (operands); "
-  [(set_attr "type" "binary,shift")
-   (set_attr "length" "4,4")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
-		(match_operand:DI 2 "register_operand" "r")))]
-  ""
-  "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
-		(match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "andcm %2,%1,%0"
-  [(set_attr "type" "binary")
-  (set_attr "length" "4")])
-
-(define_expand "iordi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ior:DI (match_operand:DI 1 "arith_double_operand" "")
-		(match_operand:DI 2 "arith_double_operand" "")))]
-  ""
-  "
-{
-  if (! register_operand (operands[1], DImode)
-      || ! register_operand (operands[2], DImode))
-    /* Let GCC break this into word-at-a-time operations.  */
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ior:DI (match_operand:DI 1 "register_operand" "%r")
-		(match_operand:DI 2 "register_operand" "r")))]
-  ""
-  "or %1,%2,%0\;or %R1,%R2,%R0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-;; Need a define_expand because we've run out of CONST_OK... characters.
-(define_expand "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ior:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  if (! (ior_operand (operands[2], SImode)
-         || register_operand (operands[2], SImode)))
-    operands[2] = force_reg (SImode, operands[2]);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ior:SI (match_operand:SI 1 "register_operand" "0,0")
-		(match_operand:SI 2 "ior_operand" "M,i")))]
-  ""
-  "* return output_ior (operands); "
-  [(set_attr "type" "binary,shift")
-   (set_attr "length" "4,4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (match_operand:SI 1 "register_operand" "%r")
-		(match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "or %1,%2,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "4")])
-
-(define_expand "xordi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(xor:DI (match_operand:DI 1 "arith_double_operand" "")
-		(match_operand:DI 2 "arith_double_operand" "")))]
-  ""
-  "
-{
-  if (! register_operand (operands[1], DImode)
-      || ! register_operand (operands[2], DImode))
-    /* Let GCC break this into word-at-a-time operations.  */
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(xor:DI (match_operand:DI 1 "register_operand" "%r")
-		(match_operand:DI 2 "register_operand" "r")))]
-  ""
-  "xor %1,%2,%0\;xor %R1,%R2,%R0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(xor:SI (match_operand:SI 1 "register_operand" "%r")
-		(match_operand:SI 2 "register_operand" "r")))]
-  ""
-  "xor %1,%2,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "4")])
-
-(define_insn "negdi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(neg:DI (match_operand:DI 1 "register_operand" "r")))]
-  ""
-  "sub 0,%R1,%R0\;subb 0,%1,%0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "8")])
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "sub 0,%1,%0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "4")])
-
-(define_expand "one_cmpldi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(not:DI (match_operand:DI 1 "arith_double_operand" "")))]
-  ""
-  "
-{
-  if (! register_operand (operands[1], DImode))
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(not:DI (match_operand:DI 1 "register_operand" "r")))]
-  ""
-  "uaddcm 0,%1,%0\;uaddcm 0,%R1,%R0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "8")])
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "uaddcm 0,%1,%0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "4")])
-
-;; Floating point arithmetic instructions.
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (match_operand:DF 1 "register_operand" "f")
-		 (match_operand:DF 2 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fadd,dbl %1,%2,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "pa_combine_type" "faddsub")
-   (set_attr "length" "4")])
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fadd,sgl %1,%2,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "pa_combine_type" "faddsub")
-   (set_attr "length" "4")])
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 1 "register_operand" "f")
-		  (match_operand:DF 2 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fsub,dbl %1,%2,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "pa_combine_type" "faddsub")
-   (set_attr "length" "4")])
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (match_operand:SF 1 "register_operand" "f")
-		  (match_operand:SF 2 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fsub,sgl %1,%2,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "pa_combine_type" "faddsub")
-   (set_attr "length" "4")])
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mult:DF (match_operand:DF 1 "register_operand" "f")
-		 (match_operand:DF 2 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fmpy,dbl %1,%2,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "pa_combine_type" "fmpy")
-   (set_attr "length" "4")])
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(mult:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fmpy,sgl %1,%2,%0"
-  [(set_attr "type" "fpmulsgl")
-   (set_attr "pa_combine_type" "fmpy")
-   (set_attr "length" "4")])
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (match_operand:DF 1 "register_operand" "f")
-		(match_operand:DF 2 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fdiv,dbl %1,%2,%0"
-  [(set_attr "type" "fpdivdbl")
-   (set_attr "length" "4")])
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(div:SF (match_operand:SF 1 "register_operand" "f")
-		(match_operand:SF 2 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fdiv,sgl %1,%2,%0"
-  [(set_attr "type" "fpdivsgl")
-   (set_attr "length" "4")])
-
-;; CYGNUS LOCAL pa8000/law
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (match_operand:DF 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "*
-{
-  if (TARGET_PARISC_2_0)
-    return \"fneg,dbl %1,%0\";
-  return \"fsub,dbl 0,%1,%0\";
-}"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (match_operand:SF 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "*
-{
-  if (TARGET_PARISC_2_0)
-    return \"fneg,sgl %1,%0\";
-  return \"fsub,sgl 0,%1,%0\";
-}"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-;; END CYGNUS LOCAL
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(abs:DF (match_operand:DF 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fabs,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(abs:SF (match_operand:SF 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fabs,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-;; CYGNUS LOCAL pa8000/law
-;; Simple fused multiply-add sequences.  
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
-			  (match_operand:DF 2 "register_operand" "f"))
-		 (match_operand:DF 3 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fmpyfadd,dbl %1,%2,%3,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
-			  (match_operand:SF 2 "register_operand" "f"))
-		 (match_operand:SF 3 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fmpyfadd,sgl %1,%2,%3,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-;; Generating a fused multiply sequence is a win for this case as it will
-;; reduce the latency for the fused case without impacting the plain
-;; multiply case.
-;;
-;; Similar possibilities exist for fnegabs, shadd and other insns which
-;; perform two operations with the result of the first feeding the second.
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
-			  (match_operand:DF 2 "register_operand" "f"))
-		 (match_operand:DF 3 "register_operand" "f")))
-   (set (match_operand:DF 4 "register_operand" "=&f")
-	(mult:DF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "#"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "8")])
-
-;; We want to split this up during scheduling since we want both insns
-;; to schedule independently.
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
-			  (match_operand:DF 2 "register_operand" "f"))
-		 (match_operand:DF 3 "register_operand" "f")))
-   (set (match_operand:DF 4 "register_operand" "=&f")
-	(mult:DF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
-			       (match_dup 3)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
-			  (match_operand:SF 2 "register_operand" "f"))
-		 (match_operand:SF 3 "register_operand" "f")))
-   (set (match_operand:SF 4 "register_operand" "=&f")
-	(mult:SF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "#"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "8")])
-
-;; We want to split this up during scheduling since we want both insns
-;; to schedule independently.
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
-			  (match_operand:SF 2 "register_operand" "f"))
-		 (match_operand:SF 3 "register_operand" "f")))
-   (set (match_operand:SF 4 "register_operand" "=&f")
-	(mult:SF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
-			       (match_dup 3)))]
-  "")
-
-;; Negating a multiply can be faked by adding zero in a fused multiply-add
-;; instruction.
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
-			 (match_operand:DF 2 "register_operand" "f"))))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fmpynfadd,dbl %1,%2,0,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
-			 (match_operand:SF 2 "register_operand" "f"))))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fmpynfadd,sgl %1,%2,0,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
-			 (match_operand:DF 2 "register_operand" "f"))))
-   (set (match_operand:DF 3 "register_operand" "=&f")
-	(mult:DF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "#"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
-			 (match_operand:DF 2 "register_operand" "f"))))
-   (set (match_operand:DF 3 "register_operand" "=&f")
-	(mult:DF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
-			 (match_operand:SF 2 "register_operand" "f"))))
-   (set (match_operand:SF 3 "register_operand" "=&f")
-	(mult:SF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "#"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
-			 (match_operand:SF 2 "register_operand" "f"))))
-   (set (match_operand:SF 3 "register_operand" "=&f")
-	(mult:SF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
-  "")
-
-;; Now fused multiplies with the result of the multiply negated.
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
-				  (match_operand:DF 2 "register_operand" "f")))
-		 (match_operand:DF 3 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fmpynfadd,dbl %1,%2,%3,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
-			 (match_operand:SF 2 "register_operand" "f")))
-		 (match_operand:SF 3 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fmpynfadd,sgl %1,%2,%3,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
-				  (match_operand:DF 2 "register_operand" "f")))
-		 (match_operand:DF 3 "register_operand" "f")))
-   (set (match_operand:DF 4 "register_operand" "=&f")
-	(mult:DF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "#"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
-				  (match_operand:DF 2 "register_operand" "f")))
-		 (match_operand:DF 3 "register_operand" "f")))
-   (set (match_operand:DF 4 "register_operand" "=&f")
-	(mult:DF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
-			       (match_dup 3)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
-				  (match_operand:SF 2 "register_operand" "f")))
-		 (match_operand:SF 3 "register_operand" "f")))
-   (set (match_operand:SF 4 "register_operand" "=&f")
-	(mult:SF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "#"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
-				  (match_operand:SF 2 "register_operand" "f")))
-		 (match_operand:SF 3 "register_operand" "f")))
-   (set (match_operand:SF 4 "register_operand" "=&f")
-	(mult:SF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
-			       (match_dup 3)))]
-  "")
-
-;; Same thing, but using minus instead of negation
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 3 "register_operand" "f")
-		  (mult:DF (match_operand:DF 1 "register_operand" "f")
-			   (match_operand:DF 2 "register_operand" "f"))))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fmpynfadd,dbl %1,%2,%3,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (match_operand:SF 3 "register_operand" "f")
-		  (mult:SF (match_operand:SF 1 "register_operand" "f")
-			   (match_operand:SF 2 "register_operand" "f"))))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fmpynfadd,sgl %1,%2,%3,%0"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 3 "register_operand" "f")
-		  (mult:DF (match_operand:DF 1 "register_operand" "f")
-			   (match_operand:DF 2 "register_operand" "f"))))
-   (set (match_operand:DF 4 "register_operand" "=&f")
-	(mult:DF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "#"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 3 "register_operand" "f")
-		  (mult:DF (match_operand:DF 1 "register_operand" "f")
-			   (match_operand:DF 2 "register_operand" "f"))))
-   (set (match_operand:DF 4 "register_operand" "=&f")
-	(mult:DF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (minus:DF (match_dup 3)
-				(mult:DF (match_dup 1) (match_dup 2))))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (match_operand:SF 3 "register_operand" "f")
-		  (mult:SF (match_operand:SF 1 "register_operand" "f")
-			   (match_operand:SF 2 "register_operand" "f"))))
-   (set (match_operand:SF 4 "register_operand" "=&f")
-	(mult:SF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "#"
-  [(set_attr "type" "fpmuldbl")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (match_operand:SF 3 "register_operand" "f")
-		  (mult:SF (match_operand:SF 1 "register_operand" "f")
-			   (match_operand:SF 2 "register_operand" "f"))))
-   (set (match_operand:SF 4 "register_operand" "=&f")
-	(mult:SF (match_dup 1) (match_dup 2)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (minus:SF (match_dup 3)
-				(mult:SF (match_dup 1) (match_dup 2))))]
-  "")
-
-;; And similarly for negation of an absolute value.
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fnegabs,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "fnegabs,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
-   (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "#"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
-   (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  [(set (match_dup 2) (abs:DF (match_dup 1)))
-   (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
-   (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  "#"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
-   (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
-  "! TARGET_SOFT_FLOAT && TARGET_PARISC_2_0"
-  [(set (match_dup 2) (abs:SF (match_dup 1)))
-   (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
-  "")
-
-;; END CYGNUS LOCAL
-
-(define_insn "sqrtdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fsqrt,dbl %1,%0"
-  [(set_attr "type" "fpsqrtdbl")
-   (set_attr "length" "4")])
-
-(define_insn "sqrtsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
-  "! TARGET_SOFT_FLOAT"
-  "fsqrt,sgl %1,%0"
-  [(set_attr "type" "fpsqrtsgl")
-   (set_attr "length" "4")])
-
-;;- Shift instructions
-
-;; Optimized special case of shifting.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
-		     (const_int 24)))]
-  ""
-  "ldb%M1 %1,%0"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
-		     (const_int 16)))]
-  ""
-  "ldh%M1 %1,%0"
-  [(set_attr "type" "load")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
-			  (match_operand:SI 3 "shadd_operand" ""))
-		 (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "sh%O3addl %2,%1,%0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "4")])
-
-;; This variant of the above insn can occur if the first operand
-;; is the frame pointer.  This is a kludge, but there doesn't
-;; seem to be a way around it.  Only recognize it while reloading.
-;; Note how operand 3 uses a predicate of "const_int_operand", but 
-;; has constraints allowing a register.  I don't know how this works,
-;; but it somehow makes sure that out-of-range constants are placed
-;; in a register which somehow magically is a "const_int_operand".
-;; (this was stolen from alpha.md, I'm not going to try and change it.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r,r")
-	(plus:SI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r")
-				   (match_operand:SI 4 "shadd_operand" ""))
-			  (match_operand:SI 1 "register_operand" "r,r"))
-		 (match_operand:SI 3 "const_int_operand" "r,J")))]
-  "reload_in_progress"
-  "@
-   sh%O4addl %2,%1,%0\;addl %3,%0,%0
-   sh%O4addl %2,%1,%0\;ldo %3(%0),%0"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
-;; This anonymous pattern and splitter wins because it reduces the latency
-;; of the shadd sequence without increasing the latency of the shift.
-;;
-;; We want to make sure and split up the operations for the scheduler since
-;; these instructions can (and should) schedule independently.
-;;
-;; It would be clearer if combine used the same operator for both expressions,
-;; it's somewhat confusing to have a mult in ine operation and an ashift
-;; in the other.
-;;
-;; If this pattern is not split before register allocation, then we must expose
-;; the fact that operand 4 is set before operands 1, 2 and 3 have been read.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
-			  (match_operand:SI 3 "shadd_operand" ""))
-		 (match_operand:SI 1 "register_operand" "r")))
-   (set (match_operand:SI 4 "register_operand" "=&r")
-	(ashift:SI (match_dup 2)
-		   (match_operand:SI 5 "const_int_operand" "i")))]
-  "INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))"
-  "#"
-  [(set_attr "type" "binary")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
-			  (match_operand:SI 3 "shadd_operand" ""))
-		 (match_operand:SI 1 "register_operand" "r")))
-   (set (match_operand:SI 4 "register_operand" "=&r")
-	(ashift:SI (match_dup 2)
-		   (match_operand:SI 5 "const_int_operand" "i")))]
-  "INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))"
-  [(set (match_dup 4) (ashift:SI (match_dup 2) (match_dup 5)))
-   (set (match_dup 0) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
-			       (match_dup 1)))]
-  "")
-
-(define_expand "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
-		   (match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    {
-      rtx temp = gen_reg_rtx (SImode);
-      emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
-      if (GET_CODE (operands[1]) == CONST_INT)
-	emit_insn (gen_zvdep_imm (operands[0], operands[1], temp));
-      else
-	emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
-      DONE;
-    }
-  /* Make sure both inputs are not constants,
-     there are no patterns for that.  */
-  operands[1] = force_reg (SImode, operands[1]);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "r")
-		   (match_operand:SI 2 "const_int_operand" "n")))]
-  ""
-  "zdep %1,%P2,%L2,%0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-; Match cases of op1 a CONST_INT here that zvdep_imm doesn't handle.
-; Doing it like this makes slightly better code since reload can
-; replace a register with a known value in range -16..15 with a
-; constant.  Ideally, we would like to merge zvdep32 and zvdep_imm,
-; but since we have no more CONST_OK... characters, that is not
-; possible.
-(define_insn "zvdep32"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
-		   (minus:SI (const_int 31)
-			     (match_operand:SI 2 "register_operand" "q,q"))))]
-  ""
-  "@
-   zvdep %1,32,%0
-   zvdepi %1,32,%0"
-  [(set_attr "type" "shift,shift")
-   (set_attr "length" "4,4")])
-
-(define_insn "zvdep_imm"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
-		   (minus:SI (const_int 31)
-			     (match_operand:SI 2 "register_operand" "q"))))]
-  ""
-  "*
-{
-  int x = INTVAL (operands[1]);
-  operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
-  operands[1] = GEN_INT ((x & 0xf) - 0x10);
-  return \"zvdepi %1,%2,%0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn "vdepi_ior"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
-			   (minus:SI (const_int 31)
-				     (match_operand:SI 2 "register_operand" "q")))
-		(match_operand:SI 3 "register_operand" "0")))]
-  ; accept ...0001...1, can this be generalized?
-  "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
-  "*
-{
-  int x = INTVAL (operands[1]);
-  operands[2] = GEN_INT (exact_log2 (x + 1));
-  return \"vdepi -1,%2,%0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn "vdepi_and"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
-			   (minus:SI (const_int 31)
-				     (match_operand:SI 2 "register_operand" "q")))
-		(match_operand:SI 3 "register_operand" "0")))]
-  ; this can be generalized...!
-  "INTVAL (operands[1]) == -2"
-  "*
-{
-  int x = INTVAL (operands[1]);
-  operands[2] = GEN_INT (exact_log2 ((~x) + 1));
-  return \"vdepi 0,%2,%0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    {
-      rtx temp = gen_reg_rtx (SImode);
-      emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
-      emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
-		     (match_operand:SI 2 "const_int_operand" "n")))]
-  ""
-  "extrs %1,%P2,%L2,%0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn "vextrs32"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
-		     (minus:SI (const_int 31)
-			       (match_operand:SI 2 "register_operand" "q"))))]
-  ""
-  "vextrs %1,32,%0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
-		     (match_operand:SI 2 "arith32_operand" "q,n")))]
-  ""
-  "@
-   vshd 0,%1,%0
-   extru %1,%P2,%L2,%0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn "rotrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
-		     (match_operand:SI 2 "arith32_operand" "q,n")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
-      return \"shd %1,%1,%2,%0\";
-    }
-  else
-    return \"vshd %1,%1,%0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operator:SI 5 "plus_xor_ior_operator"
-	  [(ashift:SI (match_operand:SI 1 "register_operand" "r")
-		      (match_operand:SI 3 "const_int_operand" "n"))
-	   (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
-			(match_operand:SI 4 "const_int_operand" "n"))]))]
-  "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
-  "shd %1,%2,%4,%0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operator:SI 5 "plus_xor_ior_operator"
-	  [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
-			(match_operand:SI 4 "const_int_operand" "n"))
-	   (ashift:SI (match_operand:SI 1 "register_operand" "r")
-		      (match_operand:SI 3 "const_int_operand" "n"))]))]
-  "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
-  "shd %1,%2,%4,%0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-			   (match_operand:SI 2 "const_int_operand" ""))
-		(match_operand:SI 3 "const_int_operand" "")))]
-  "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
-  "*
-{
-  int cnt = INTVAL (operands[2]) & 31;
-  operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
-  operands[2] = GEN_INT (31 - cnt);
-  return \"zdep %1,%2,%3,%0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-;; Unconditional and other jump instructions.
-
-;; CYGNUS LOCAL PA8000/law
-(define_insn "return"
-  [(return)]
-  "hppa_can_use_return_insn_p ()"
-  "*
-{
-  if (TARGET_PARISC_2_0)
-    return \"bve%* 0(%%r2)\";
-  return \"bv%* 0(%%r2)\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "4")])
-
-;; Use a different pattern for functions which have non-trivial
-;; epilogues so as not to confuse jump and reorg.
-(define_insn "return_internal"
-  [(use (reg:SI 2))
-   (return)]
-  ""
-  "*
-{
-  if (TARGET_PARISC_2_0)
-    return \"bve%* 0(%%r2)\";
-  return \"bv%* 0(%%r2)\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "4")])
-;; END CYGNUS LOCAL
-
-(define_expand "prologue"
-  [(const_int 0)]
-  ""
-  "hppa_expand_prologue ();DONE;")
-
-(define_expand "epilogue"
-  [(return)]
-  ""
-  "
-{
-  /* Try to use the trivial return first.  Else use the full
-     epilogue.  */
-  if (hppa_can_use_return_insn_p ())
-   emit_jump_insn (gen_return ());
-  else
-    {
-      hppa_expand_epilogue ();
-      emit_jump_insn (gen_return_internal ());
-    }
-  DONE;
-}")
-
-;; Special because we use the value placed in %r2 by the bl instruction
-;; from within its delay slot to set the value for the 2nd parameter to
-;; the call.
-(define_insn "call_profiler"
-  [(unspec_volatile [(const_int 0)] 0)
-   (use (match_operand:SI 0 "const_int_operand" ""))]
-  ""
-  "bl _mcount,%%r2\;ldo %0(%%r2),%%r25"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 2)] 0)]
-  ""
-  ""
-  [(set_attr "length" "0")])
-
-(define_insn "jump"
-  [(set (pc) (label_ref (match_operand 0 "" "")))]
-  ""
-  "*
-{
-  extern int optimize;
-
-  if (GET_MODE (insn) == SImode)
-    return \"bl %l0,0%#\";
-
-  /* An unconditional branch which can reach its target.  */
-  if (get_attr_length (insn) != 24
-      && get_attr_length (insn) != 16)
-    return \"bl%* %l0,0\";
-
-  /* An unconditional branch which can not reach its target.
-
-     We need to be able to use %r1 as a scratch register; however,
-     we can never be sure whether or not it's got a live value in
-     it.  Therefore, we must restore its original value after the
-     jump.
-
-     To make matters worse, we don't have a stack slot which we
-     can always clobber.  sp-12/sp-16 shouldn't ever have a live
-     value during a non-optimizing compilation, so we use those
-     slots for now.  We don't support very long branches when
-     optimizing -- they should be quite rare when optimizing.
-
-     Really the way to go long term is a register scavenger; goto
-     the target of the jump and find a register which we can use
-     as a scratch to hold the value in %r1.  */
-
-  /* We don't know how to register scavenge yet.  */
-  if (optimize)
-    abort ();
-
-  /* First store %r1 into the stack.  */
-  output_asm_insn (\"stw %%r1,-16(%%r30)\", operands);
-
-  /* Now load the target address into %r1 and do an indirect jump
-     to the value specified in %r1.  Be careful to generate PIC
-     code as needed.  */
-  if (flag_pic)
-    {
-      rtx xoperands[2];
-      xoperands[0] = operands[0];
-      xoperands[1] = gen_label_rtx ();
-
-      output_asm_insn (\"bl .+8,%%r1\\n\\taddil L'%l0-%l1,%%r1\", xoperands);
-      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
-                                 CODE_LABEL_NUMBER (xoperands[1]));
-      output_asm_insn (\"ldo R'%l0-%l1(%%r1),%%r1\\n\\tbv 0(%%r1)\",
-		       xoperands);
-    }
-  else
-    output_asm_insn (\"ldil L'%l0,%%r1\\n\\tbe R'%l0(%%sr4,%%r1)\", operands);;
-
-  /* And restore the value of %r1 in the delay slot.  We're not optimizing,
-     so we know nothing else can be in the delay slot.  */
-  return \"ldw -16(%%r30),%%r1\";
-}"
-  [(set_attr "type" "uncond_branch")
-   (set_attr "pa_combine_type" "uncond_branch")
-   (set (attr "length")
-    (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
-	   (if_then_else (lt (abs (minus (match_dup 0)
-					 (plus (pc) (const_int 8))))
-			     (const_int 8184))
-			 (const_int 4)
-			 (const_int 8))
-	   (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
-	       (const_int 262100))
-	   (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
-			 (const_int 16)
-			 (const_int 24))]
-	  (const_int 4)))])
-
-;; Subroutines of "casesi".
-;; operand 0 is index
-;; operand 1 is the minimum bound
-;; operand 2 is the maximum bound - minimum bound + 1
-;; operand 3 is CODE_LABEL for the table;
-;; operand 4 is the CODE_LABEL to go to if index out of range.
-
-(define_expand "casesi"
-  [(match_operand:SI 0 "general_operand" "")
-   (match_operand:SI 1 "const_int_operand" "")
-   (match_operand:SI 2 "const_int_operand" "")
-   (match_operand 3 "" "")
-   (match_operand 4 "" "")]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) != REG)
-    operands[0] = force_reg (SImode, operands[0]);
-
-  if (operands[1] != const0_rtx)
-    {
-      rtx reg = gen_reg_rtx (SImode);
-
-      operands[1] = GEN_INT (-INTVAL (operands[1]));
-      if (!INT_14_BITS (operands[1]))
-	operands[1] = force_reg (SImode, operands[1]);
-      emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
-
-      operands[0] = reg;
-    }
-
-  if (!INT_5_BITS (operands[2]))
-    operands[2] = force_reg (SImode, operands[2]);
-
-  emit_insn (gen_cmpsi (operands[0], operands[2]));
-  emit_jump_insn (gen_bgtu (operands[4]));
-  if (TARGET_BIG_SWITCH)
-    {
-      rtx temp = gen_reg_rtx (SImode);
-      emit_move_insn (temp, gen_rtx_PLUS (SImode, operands[0], operands[0]));
-      operands[0] = temp;
-    }
-  emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
-  DONE;
-}")
-
-(define_insn "casesi0"
-  [(set (pc) (plus:SI
-	       (mem:SI (plus:SI (pc)
-				(match_operand:SI 0 "register_operand" "r")))
-	       (label_ref (match_operand 1 "" ""))))]
-  ""
-  "blr %0,0\;nop"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
-;; Need nops for the calls because execution is supposed to continue
-;; past; we don't want to nullify an instruction that we need.
-;;- jump to subroutine
-
-(define_expand "call"
-  [(parallel [(call (match_operand:SI 0 "" "")
-		    (match_operand 1 "" ""))
-	      (clobber (reg:SI 2))])]
-  ""
-  "
-{
-  rtx op;
-  rtx call_insn;
-
-  if (TARGET_PORTABLE_RUNTIME)
-    op = force_reg (SImode, XEXP (operands[0], 0));
-  else
-    op = XEXP (operands[0], 0);
-
-  /* Use two different patterns for calls to explicitly named functions
-     and calls through function pointers.  This is necessary as these two
-     types of calls use different calling conventions, and CSE might try
-     to change the named call into an indirect call in some cases (using
-     two patterns keeps CSE from performing this optimization).  */
-  if (GET_CODE (op) == SYMBOL_REF)
-    call_insn = emit_call_insn (gen_call_internal_symref (op, operands[1]));
-  else
-    {
-      rtx tmpreg = gen_rtx_REG (SImode, 22);
-      emit_move_insn (tmpreg, force_reg (SImode, op));
-      call_insn = emit_call_insn (gen_call_internal_reg (operands[1]));
-    }
-
-  if (flag_pic)
-    {
-      use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
-
-      /* After each call we must restore the PIC register, even if it
-	 doesn't appear to be used.
-
-         This will set regs_ever_live for the callee saved register we
-	 stored the PIC register in.  */
-      emit_move_insn (pic_offset_table_rtx,
-		      gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM_SAVED));
-      emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
-
-      /* Gross.  We have to keep the scheduler from moving the restore
-	 of the PIC register away from the call.  SCHED_GROUP_P is
-	 supposed to do this, but for some reason the compiler will
-	 go into an infinite loop when we use that.
-
-	 This method (blockage insn) may make worse code (then again
-	 it may not since calls are nearly blockages anyway), but at
-	 least it should work.  */
-      emit_insn (gen_blockage ());
-    }
-  DONE;
-}")
-
-(define_insn "call_internal_symref"
-  [(call (mem:SI (match_operand:SI 0 "call_operand_address" ""))
-	 (match_operand 1 "" "i"))
-   (clobber (reg:SI 2))
-   (use (const_int 0))]
-  "! TARGET_PORTABLE_RUNTIME"
-  "*
-{
-  output_arg_descriptor (insn);
-  return output_call (insn, operands[0], gen_rtx_REG (SImode, 2));
-}"
-  [(set_attr "type" "call")
-   (set (attr "length")
-;;       If we're sure that we can either reach the target or that the
-;;	 linker can use a long-branch stub, then the length is 4 bytes.
-;;
-;;	 For long-calls the length will be either 52 bytes (non-pic)
-;;	 or 68 bytes (pic).  */
-;;	 Else we have to use a long-call;
-      (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
-			(const_int 240000))
-		    (const_int 4)
-		    (if_then_else (eq (symbol_ref "flag_pic")
-				      (const_int 0))
-				  (const_int 52)
-				  (const_int 68))))])
-
-(define_insn "call_internal_reg"
-  [(call (mem:SI (reg:SI 22))
-	 (match_operand 0 "" "i"))
-   (clobber (reg:SI 2))
-   (use (const_int 1))]
-  ""
-  "*
-{
-  rtx xoperands[2];
-
-  /* First the special case for kernels, level 0 systems, etc.  */
-  if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS)
-    return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\";
-
-  /* Now the normal case -- we can reach $$dyncall directly or
-     we're sure that we can get there via a long-branch stub. 
-
-     No need to check target flags as the length uniquely identifies
-     the remaining cases.  */
-  if (get_attr_length (insn) == 8)
-    return \".CALL\\tARGW0=GR\;bl $$dyncall,%%r31\;copy %%r31,%%r2\";
-
-  /* Long millicode call, but we are not generating PIC or portable runtime
-     code.  */
-  if (get_attr_length (insn) == 12)
-    return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\";
-
-  /* Long millicode call for portable runtime.  */
-  if (get_attr_length (insn) == 20)
-    return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr 0,%%r2\;bv,n 0(%%r31)\;nop\";
-
-  /* If we're generating PIC code.  */
-  xoperands[0] = operands[0];
-  xoperands[1] = gen_label_rtx ();
-  output_asm_insn (\"bl .+8,%%r1\", xoperands);
-  output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
-			     CODE_LABEL_NUMBER (xoperands[1]));
-  output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands);
-  output_asm_insn (\"blr 0,%%r2\", xoperands);
-  output_asm_insn (\"bv,n 0(%%r1)\\n\\tnop\", xoperands);
-  return \"\";
-}"
-  [(set_attr "type" "dyncall")
-   (set (attr "length")
-     (cond [
-;; First NO_SPACE_REGS
-	    (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
-		(const_int 0))
-	    (const_int 8)
-
-;; Target (or stub) within reach
-	    (and (lt (plus (symbol_ref "total_code_bytes") (pc))
-		     (const_int 240000))
-		 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-		     (const_int 0)))
-	    (const_int 8)
-
-;; Out of reach, but not PIC or PORTABLE_RUNTIME
-	    (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-		     (const_int 0))
-		 (eq (symbol_ref "flag_pic")
-		     (const_int 0)))
-	    (const_int 12)
-
-	    (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
-		(const_int 0))
-	    (const_int 20)]
-
-;; Out of range PIC case
-	  (const_int 24)))])
-
-(define_expand "call_value"
-  [(parallel [(set (match_operand 0 "" "")
-		   (call (match_operand:SI 1 "" "")
-			 (match_operand 2 "" "")))
-	      (clobber (reg:SI 2))])]
-  ""
-  "
-{
-  rtx op;
-  rtx call_insn;
-
-  if (TARGET_PORTABLE_RUNTIME)
-    op = force_reg (SImode, XEXP (operands[1], 0));
-  else
-    op = XEXP (operands[1], 0);
-
-  /* Use two different patterns for calls to explicitly named functions
-     and calls through function pointers.  This is necessary as these two
-     types of calls use different calling conventions, and CSE might try
-     to change the named call into an indirect call in some cases (using
-     two patterns keeps CSE from performing this optimization).  */
-  if (GET_CODE (op) == SYMBOL_REF)
-    call_insn = emit_call_insn (gen_call_value_internal_symref (operands[0],
-								op,
-								operands[2]));
-  else
-    {
-      rtx tmpreg = gen_rtx_REG (SImode, 22);
-      emit_move_insn (tmpreg, force_reg (SImode, op));
-      call_insn = emit_call_insn (gen_call_value_internal_reg (operands[0],
-							       operands[2]));
-    }
-  if (flag_pic)
-    {
-      use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
-
-      /* After each call we must restore the PIC register, even if it
-	 doesn't appear to be used.
-
-         This will set regs_ever_live for the callee saved register we
-	 stored the PIC register in.  */
-      emit_move_insn (pic_offset_table_rtx,
-		      gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM_SAVED));
-      emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
-
-      /* Gross.  We have to keep the scheduler from moving the restore
-	 of the PIC register away from the call.  SCHED_GROUP_P is
-	 supposed to do this, but for some reason the compiler will
-	 go into an infinite loop when we use that.
-
-	 This method (blockage insn) may make worse code (then again
-	 it may not since calls are nearly blockages anyway), but at
-	 least it should work.  */
-      emit_insn (gen_blockage ());
-    }
-  DONE;
-}")
-
-(define_insn "call_value_internal_symref"
-  [(set (match_operand 0 "" "=rf")
-	(call (mem:SI (match_operand:SI 1 "call_operand_address" ""))
-	      (match_operand 2 "" "i")))
-   (clobber (reg:SI 2))
-   (use (const_int 0))]
-  ;;- Don't use operand 1 for most machines.
-  "! TARGET_PORTABLE_RUNTIME"
-  "*
-{
-  output_arg_descriptor (insn);
-  return output_call (insn, operands[1], gen_rtx_REG (SImode, 2));
-}"
-  [(set_attr "type" "call")
-   (set (attr "length")
-;;       If we're sure that we can either reach the target or that the
-;;	 linker can use a long-branch stub, then the length is 4 bytes.
-;;
-;;	 For long-calls the length will be either 52 bytes (non-pic)
-;;	 or 68 bytes (pic).  */
-;;	 Else we have to use a long-call;
-      (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
-			(const_int 240000))
-		    (const_int 4)
-		    (if_then_else (eq (symbol_ref "flag_pic")
-				      (const_int 0))
-				  (const_int 52)
-				  (const_int 68))))])
-
-(define_insn "call_value_internal_reg"
-  [(set (match_operand 0 "" "=rf")
-	(call (mem:SI (reg:SI 22))
-	      (match_operand 1 "" "i")))
-   (clobber (reg:SI 2))
-   (use (const_int 1))]
-  ""
-  "*
-{
-  rtx xoperands[2];
-
-  /* First the special case for kernels, level 0 systems, etc.  */
-  if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS)
-    return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\";
-
-  /* Now the normal case -- we can reach $$dyncall directly or
-     we're sure that we can get there via a long-branch stub. 
-
-     No need to check target flags as the length uniquely identifies
-     the remaining cases.  */
-  if (get_attr_length (insn) == 8)
-    return \".CALL\\tARGW0=GR\;bl $$dyncall,%%r31\;copy %%r31,%%r2\";
-
-  /* Long millicode call, but we are not generating PIC or portable runtime
-     code.  */
-  if (get_attr_length (insn) == 12)
-    return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\";
-
-  /* Long millicode call for portable runtime.  */
-  if (get_attr_length (insn) == 20)
-    return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr 0,%%r2\;bv,n 0(%%r31)\;nop\";
-
-  /* If we're generating PIC code.  */
-  xoperands[0] = operands[1];
-  xoperands[1] = gen_label_rtx ();
-  output_asm_insn (\"bl .+8,%%r1\", xoperands);
-  output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
-			     CODE_LABEL_NUMBER (xoperands[1]));
-  output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands);
-  output_asm_insn (\"blr 0,%%r2\", xoperands);
-  output_asm_insn (\"bv,n 0(%%r1)\\n\\tnop\", xoperands);
-  return \"\";
-}"
-  [(set_attr "type" "dyncall")
-   (set (attr "length")
-     (cond [
-;; First NO_SPACE_REGS
-	    (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
-		(const_int 0))
-	    (const_int 8)
-
-;; Target (or stub) within reach
-	    (and (lt (plus (symbol_ref "total_code_bytes") (pc))
-		     (const_int 240000))
-		 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-		     (const_int 0)))
-	    (const_int 8)
-
-;; Out of reach, but not PIC or PORTABLE_RUNTIME
-	    (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-		     (const_int 0))
-		 (eq (symbol_ref "flag_pic")
-		     (const_int 0)))
-	    (const_int 12)
-
-	    (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
-		(const_int 0))
-	    (const_int 20)]
-
-;; Out of range PIC case
-	  (const_int 24)))])
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-  [(set_attr "type" "move")
-   (set_attr "length" "4")])
-
-;; These are just placeholders so we know where branch tables
-;; begin and end.
-(define_insn "begin_brtab"
-  [(const_int 1)]
-  ""
-  "*
-{
-  /* Only GAS actually supports this pseudo-op.  */
-  if (TARGET_GAS)
-    return \".begin_brtab\";
-  else
-    return \"\";
-}"
-  [(set_attr "type" "move")
-   (set_attr "length" "0")])
-
-(define_insn "end_brtab"
-  [(const_int 2)]
-  ""
-  "*
-{
-  /* Only GAS actually supports this pseudo-op.  */
-  if (TARGET_GAS)
-    return \".end_brtab\";
-  else
-    return \"\";
-}"
-  [(set_attr "type" "move")
-   (set_attr "length" "0")])
-
-;;; Hope this is only within a function...
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
-  ""
-  "bv%* 0(%0)"
-  [(set_attr "type" "branch")
-   (set_attr "length" "4")])
-
-(define_insn "extzv"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "uint5_operand" "")
-			 (match_operand:SI 3 "uint5_operand" "")))]
-  ""
-  "extru %1,%3+%2-1,%2,%0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (const_int 1)
-			 (match_operand:SI 3 "register_operand" "q")))]
-  ""
-  "vextru %1,1,%0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn "extv"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "uint5_operand" "")
-			 (match_operand:SI 3 "uint5_operand" "")))]
-  ""
-  "extrs %1,%3+%2-1,%2,%0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (const_int 1)
-			 (match_operand:SI 3 "register_operand" "q")))]
-  ""
-  "vextrs %1,1,%0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-(define_insn "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
-			 (match_operand:SI 1 "uint5_operand" "")
-			 (match_operand:SI 2 "uint5_operand" ""))
-	(match_operand:SI 3 "arith5_operand" "r,L"))]
-  ""
-  "@
-   dep %3,%2+%1-1,%1,%0
-   depi %3,%2+%1-1,%1,%0"
-  [(set_attr "type" "shift,shift")
-   (set_attr "length" "4,4")])
-
-;; Optimize insertion of const_int values of type 1...1xxxx.
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-			 (match_operand:SI 1 "uint5_operand" "")
-			 (match_operand:SI 2 "uint5_operand" ""))
-	(match_operand:SI 3 "const_int_operand" ""))]
-  "(INTVAL (operands[3]) & 0x10) != 0 &&
-   (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
-  "*
-{
-  operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
-  return \"depi %3,%2+%1-1,%1,%0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "4")])
-
-;; This insn is used for some loop tests, typically loops reversed when
-;; strength reduction is used.  It is actually created when the instruction
-;; combination phase combines the special loop test.  Since this insn
-;; is both a jump insn and has an output, it must deal with its own
-;; reloads, hence the `m' constraints.  The `!' constraints direct reload
-;; to not choose the register alternatives in the event a reload is needed.
-(define_insn "decrement_and_branch_until_zero"
-  [(set (pc)
-	(if_then_else
-	  (match_operator 2 "comparison_operator"
-	   [(plus:SI (match_operand:SI 0 "register_operand" "+!r,!*f,!*m")
-		     (match_operand:SI 1 "int5_operand" "L,L,L"))
-	    (const_int 0)])
-	  (label_ref (match_operand 3 "" ""))
-	  (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0) (match_dup 1)))
-   (clobber (match_scratch:SI 4 "=X,r,r"))]
-  ""
-  "* return output_dbra (operands, insn, which_alternative); "
-;; Do not expect to understand this the first time through.
-[(set_attr "type" "cbranch,multi,multi")
- (set (attr "length")
-      (if_then_else (eq_attr "alternative" "0")
-;; Loop counter in register case
-;; Short branch has length of 4
-;; Long branch has length of 8
-	(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8))
-
-;; Loop counter in FP reg case.
-;; Extra goo to deal with additional reload insns.
-	(if_then_else (eq_attr "alternative" "1")
-	  (if_then_else (lt (match_dup 3) (pc))
-	    (if_then_else
-	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
-		  (const_int 8184))
-	      (const_int 24)
-	      (const_int 28))
-	    (if_then_else
-	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
-		  (const_int 8184))
-	      (const_int 24)
-	      (const_int 28)))
-;; Loop counter in memory case.
-;; Extra goo to deal with additional reload insns.
-	(if_then_else (lt (match_dup 3) (pc))
-	  (if_then_else
-	    (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
-		(const_int 8184))
-	    (const_int 12)
-	    (const_int 16))
-	  (if_then_else
-	    (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
-		(const_int 8184))
-	    (const_int 12)
-	    (const_int 16))))))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	  (match_operator 2 "movb_comparison_operator"
-	   [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
-	  (label_ref (match_operand 3 "" ""))
-	  (pc)))
-   (set (match_operand:SI 0 "register_operand" "=!r,!*f,!*m,!*q")
-	(match_dup 1))]
-  ""
-"* return output_movb (operands, insn, which_alternative, 0); "
-;; Do not expect to understand this the first time through.
-[(set_attr "type" "cbranch,multi,multi,multi")
- (set (attr "length")
-      (if_then_else (eq_attr "alternative" "0")
-;; Loop counter in register case
-;; Short branch has length of 4
-;; Long branch has length of 8
-	(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8))
-
-;; Loop counter in FP reg case.
-;; Extra goo to deal with additional reload insns.
-	(if_then_else (eq_attr "alternative" "1")
-	  (if_then_else (lt (match_dup 3) (pc))
-	    (if_then_else
-	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
-		  (const_int 8184))
-	      (const_int 12)
-	      (const_int 16))
-	    (if_then_else
-	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
-		  (const_int 8184))
-	      (const_int 12)
-	      (const_int 16)))
-;; Loop counter in memory or sar case.
-;; Extra goo to deal with additional reload insns.
-	(if_then_else
-	  (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
-	      (const_int 8184))
-	  (const_int 8)
-	  (const_int 12)))))])
-
-;; Handle negated branch.
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	  (match_operator 2 "movb_comparison_operator"
-	   [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
-	  (pc)
-	  (label_ref (match_operand 3 "" ""))))
-   (set (match_operand:SI 0 "register_operand" "=!r,!*f,!*m,!*q")
-	(match_dup 1))]
-  ""
-"* return output_movb (operands, insn, which_alternative, 1); "
-;; Do not expect to understand this the first time through.
-[(set_attr "type" "cbranch,multi,multi,multi")
- (set (attr "length")
-      (if_then_else (eq_attr "alternative" "0")
-;; Loop counter in register case
-;; Short branch has length of 4
-;; Long branch has length of 8
-	(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8))
-
-;; Loop counter in FP reg case.
-;; Extra goo to deal with additional reload insns.
-	(if_then_else (eq_attr "alternative" "1")
-	  (if_then_else (lt (match_dup 3) (pc))
-	    (if_then_else
-	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
-		  (const_int 8184))
-	      (const_int 12)
-	      (const_int 16))
-	    (if_then_else
-	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
-		  (const_int 8184))
-	      (const_int 12)
-	      (const_int 16)))
-;; Loop counter in memory or SAR case.
-;; Extra goo to deal with additional reload insns.
-	(if_then_else
-	  (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
-	      (const_int 8184))
-	  (const_int 8)
-	  (const_int 12)))))])
-
-;; The next several patterns (parallel_addb, parallel_movb, fmpyadd and
-;; fmpysub aren't currently used by the FSF sources, but will be soon.
-;;
-;; They're in the FSF tree for documentation and to make Cygnus<->FSF
-;; merging easier.
-(define_insn ""
-  [(set (pc) (label_ref (match_operand 3 "" "" )))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_operand:SI 1 "register_operand" "r")
-		 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
-  "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
-  "*
-{
-  return output_parallel_addb (operands, get_attr_length (insn));
-}"
-  [(set_attr "type" "parallel_branch")
-   (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-(define_insn ""
-  [(set (pc) (label_ref (match_operand 2 "" "" )))
-   (set (match_operand:SF 0 "register_operand" "=r")
-	(match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
-  "reload_completed"
-  "*
-{
-  return output_parallel_movb (operands, get_attr_length (insn));
-}"
-  [(set_attr "type" "parallel_branch")
-   (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-(define_insn ""
-  [(set (pc) (label_ref (match_operand 2 "" "" )))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
-  "reload_completed"
-  "*
-{
-  return output_parallel_movb (operands, get_attr_length (insn));
-}"
-  [(set_attr "type" "parallel_branch")
-   (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-(define_insn ""
-  [(set (pc) (label_ref (match_operand 2 "" "" )))
-   (set (match_operand:HI 0 "register_operand" "=r")
-	(match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
-  "reload_completed"
-  "*
-{
-  return output_parallel_movb (operands, get_attr_length (insn));
-}"
-  [(set_attr "type" "parallel_branch")
-   (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-(define_insn ""
-  [(set (pc) (label_ref (match_operand 2 "" "" )))
-   (set (match_operand:QI 0 "register_operand" "=r")
-	(match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
-  "reload_completed"
-  "*
-{
-  return output_parallel_movb (operands, get_attr_length (insn));
-}"
-  [(set_attr "type" "parallel_branch")
-   (set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
-		      (const_int 8184))
-           (const_int 4)
-	   (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand 0 "register_operand" "=f")
-	(mult (match_operand 1 "register_operand" "f")
-	      (match_operand 2 "register_operand" "f")))
-   (set (match_operand 3 "register_operand" "+f")
-	(plus (match_operand 4 "register_operand" "f")
-	      (match_operand 5 "register_operand" "f")))]
-  "TARGET_SNAKE && ! TARGET_SOFT_FLOAT
-   && reload_completed && fmpyaddoperands (operands)"
-  "*
-{
-  if (GET_MODE (operands[0]) == DFmode)
-    {
-      if (rtx_equal_p (operands[3], operands[5]))
-	return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
-      else
-	return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
-    }
-  else
-    {
-      if (rtx_equal_p (operands[3], operands[5]))
-	return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
-      else
-	return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
-    }
-}"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand 3 "register_operand" "+f")
-	(plus (match_operand 4 "register_operand" "f")
-	      (match_operand 5 "register_operand" "f")))
-   (set (match_operand 0 "register_operand" "=f")
-	(mult (match_operand 1 "register_operand" "f")
-	      (match_operand 2 "register_operand" "f")))]
-  "TARGET_SNAKE && ! TARGET_SOFT_FLOAT
-   && reload_completed && fmpyaddoperands (operands)"
-  "*
-{
-  if (GET_MODE (operands[0]) == DFmode)
-    {
-      if (rtx_equal_p (operands[3], operands[5]))
-	return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
-      else
-	return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
-    }
-  else
-    {
-      if (rtx_equal_p (operands[3], operands[5]))
-	return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
-      else
-	return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
-    }
-}"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand 0 "register_operand" "=f")
-	(mult (match_operand 1 "register_operand" "f")
-	      (match_operand 2 "register_operand" "f")))
-   (set (match_operand 3 "register_operand" "+f")
-	(minus (match_operand 4 "register_operand" "f")
-	       (match_operand 5 "register_operand" "f")))]
-  "TARGET_SNAKE && ! TARGET_SOFT_FLOAT
-   && reload_completed && fmpysuboperands (operands)"
-  "*
-{
-  if (GET_MODE (operands[0]) == DFmode)
-    return \"fmpysub,dbl %1,%2,%0,%5,%3\";
-  else
-    return \"fmpysub,sgl %1,%2,%0,%5,%3\";
-}"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-(define_insn ""
-  [(set (match_operand 3 "register_operand" "+f")
-	(minus (match_operand 4 "register_operand" "f")
-	       (match_operand 5 "register_operand" "f")))
-   (set (match_operand 0 "register_operand" "=f")
-	(mult (match_operand 1 "register_operand" "f")
-	      (match_operand 2 "register_operand" "f")))]
-  "TARGET_SNAKE && ! TARGET_SOFT_FLOAT
-   && reload_completed && fmpysuboperands (operands)"
-  "*
-{
-  if (GET_MODE (operands[0]) == DFmode)
-    return \"fmpysub,dbl %1,%2,%0,%5,%3\";
-  else
-    return \"fmpysub,sgl %1,%2,%0,%5,%3\";
-}"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "4")])
-
-;; Clean up turds left by reload.
-(define_peephole
-  [(set (match_operand 0 "reg_or_nonsymb_mem_operand" "")
-	(match_operand 1 "register_operand" "fr"))
-   (set (match_operand 2 "register_operand" "fr")
-	(match_dup 0))]
-  "! TARGET_SOFT_FLOAT
-   && GET_CODE (operands[0]) == MEM
-   && ! MEM_VOLATILE_P (operands[0])
-   && GET_MODE (operands[0]) == GET_MODE (operands[1])
-   && GET_MODE (operands[0]) == GET_MODE (operands[2])
-   && GET_MODE (operands[0]) == DFmode
-   && GET_CODE (operands[1]) == REG
-   && GET_CODE (operands[2]) == REG
-   && ! side_effects_p (XEXP (operands[0], 0))
-   && REGNO_REG_CLASS (REGNO (operands[1]))
-      == REGNO_REG_CLASS (REGNO (operands[2]))"
-  "*
-{
-  rtx xoperands[2];
-
-  if (FP_REG_P (operands[1]))
-    output_asm_insn (output_fp_move_double (operands), operands);
-  else
-    output_asm_insn (output_move_double (operands), operands);
-
-  if (rtx_equal_p (operands[1], operands[2]))
-    return \"\";
-
-  xoperands[0] = operands[2];
-  xoperands[1] = operands[1];
-      
-  if (FP_REG_P (xoperands[1]))
-    output_asm_insn (output_fp_move_double (xoperands), xoperands);
-  else
-    output_asm_insn (output_move_double (xoperands), xoperands);
-
-  return \"\";
-}")
-
-(define_peephole
-  [(set (match_operand 0 "register_operand" "fr")
-	(match_operand 1 "reg_or_nonsymb_mem_operand" ""))
-   (set (match_operand 2 "register_operand" "fr")
-	(match_dup 1))]
-  "! TARGET_SOFT_FLOAT
-   && GET_CODE (operands[1]) == MEM
-   && ! MEM_VOLATILE_P (operands[1])
-   && GET_MODE (operands[0]) == GET_MODE (operands[1])
-   && GET_MODE (operands[0]) == GET_MODE (operands[2])
-   && GET_MODE (operands[0]) == DFmode
-   && GET_CODE (operands[0]) == REG
-   && GET_CODE (operands[2]) == REG
-   && ! side_effects_p (XEXP (operands[1], 0))
-   && REGNO_REG_CLASS (REGNO (operands[0]))
-      == REGNO_REG_CLASS (REGNO (operands[2]))"
-  "*
-{
-  rtx xoperands[2];
-
-  if (FP_REG_P (operands[0]))
-    output_asm_insn (output_fp_move_double (operands), operands);
-  else
-    output_asm_insn (output_move_double (operands), operands);
-
-  xoperands[0] = operands[2];
-  xoperands[1] = operands[0];
-      
-  if (FP_REG_P (xoperands[1]))
-    output_asm_insn (output_fp_move_double (xoperands), xoperands);
-  else
-    output_asm_insn (output_move_double (xoperands), xoperands);
-
-  return \"\";
-}")
-
-;; Flush the I and D cache line found at the address in operand 0.
-;; This is used by the trampoline code for nested functions.
-;; So long as the trampoline itself is less than 32 bytes this
-;; is sufficient.
-
-(define_insn "dcacheflush"
-  [(unspec_volatile [(const_int 1)] 0)
-   (use (mem:SI (match_operand:SI 0 "register_operand" "r")))
-   (use (mem:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "fdc 0(0,%0)\;fdc 0(0,%1)\;sync"
-  [(set_attr "type" "multi")
-   (set_attr "length" "12")])
-
-(define_insn "icacheflush"
-  [(unspec_volatile [(const_int 2)] 0)
-   (use (mem:SI (match_operand:SI 0 "register_operand" "r")))
-   (use (mem:SI (match_operand:SI 1 "register_operand" "r")))
-   (use (match_operand:SI 2 "register_operand" "r"))
-   (clobber (match_operand:SI 3 "register_operand" "=&r"))
-   (clobber (match_operand:SI 4 "register_operand" "=&r"))]
-  ""
-  "mfsp %%sr0,%4\;ldsid (0,%2),%3\;mtsp %3,%%sr0\;fic 0(%%sr0,%0)\;fic 0(%%sr0,%1)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
-  [(set_attr "type" "multi")
-   (set_attr "length" "52")])
-
-;; An out-of-line prologue.
-(define_insn "outline_prologue_call"
-  [(unspec_volatile [(const_int 0)] 0)
-   (clobber (reg:SI 31))
-   (clobber (reg:SI 22))
-   (clobber (reg:SI 21))
-   (clobber (reg:SI 20))
-   (clobber (reg:SI 19))
-   (clobber (reg:SI 1))]
-  ""
-  "*
-{
-  extern int frame_pointer_needed;
-
-  /* We need two different versions depending on whether or not we
-     need a frame pointer.   Also note that we return to the instruction
-     immediately after the branch rather than two instructions after the
-     break as normally is the case.  */
-  if (frame_pointer_needed)
-    {
-      /* Must import the magic millicode routine(s).  */
-      output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
-
-      if (TARGET_PORTABLE_RUNTIME)
-	{
-	  output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
-	  output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
-			   NULL);
-	}
-      else
-	output_asm_insn (\"bl,n __outline_prologue_fp,%%r31\", NULL);
-    }
-  else
-    {
-      /* Must import the magic millicode routine(s).  */
-      output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
-
-      if (TARGET_PORTABLE_RUNTIME)
-	{
-	  output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
-	  output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
-	}
-      else
-	output_asm_insn (\"bl,n __outline_prologue,%%r31\", NULL);
-    }
-  return \"\";
-}"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
-;; An out-of-line epilogue.
-(define_insn "outline_epilogue_call"
-  [(unspec_volatile [(const_int 1)] 0)
-   (use (reg:SI 29))
-   (use (reg:SI 28))
-   (clobber (reg:SI 31))
-   (clobber (reg:SI 22))
-   (clobber (reg:SI 21))
-   (clobber (reg:SI 20))
-   (clobber (reg:SI 19))
-   (clobber (reg:SI 2))
-   (clobber (reg:SI 1))]
-  ""
-  "*
-{
-  extern int frame_pointer_needed;
-
-  /* We need two different versions depending on whether or not we
-     need a frame pointer.   Also note that we return to the instruction
-     immediately after the branch rather than two instructions after the
-     break as normally is the case.  */
-  if (frame_pointer_needed)
-    {
-      /* Must import the magic millicode routine.  */
-      output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
-
-      /* The out-of-line prologue will make sure we return to the right
-	 instruction.  */
-      if (TARGET_PORTABLE_RUNTIME)
-	{
-	  output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
-	  output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
-			   NULL);
-	}
-      else
-	output_asm_insn (\"bl,n __outline_epilogue_fp,%%r31\", NULL);
-    }
-  else
-    {
-      /* Must import the magic millicode routine.  */
-      output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
-
-      /* The out-of-line prologue will make sure we return to the right
-	 instruction.  */
-      if (TARGET_PORTABLE_RUNTIME)
-	{
-	  output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
-	  output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
-	}
-      else
-	output_asm_insn (\"bl,n __outline_epilogue,%%r31\", NULL);
-    }
-  return \"\";
-}"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
-;; Given a function pointer, canonicalize it so it can be 
-;; reliably compared to another function pointer.  */
-(define_expand "canonicalize_funcptr_for_compare"
-  [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
-   (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
-	      (clobber (match_dup 2))
-	      (clobber (reg:SI 26))
-	      (clobber (reg:SI 22))
-	      (clobber (reg:SI 31))])
-   (set (match_operand:SI 0 "register_operand" "")
-	(reg:SI 29))]
-  "! TARGET_PORTABLE_RUNTIME"
-  "
-{
-  operands[2] = gen_reg_rtx (SImode);
-  if (GET_CODE (operands[1]) != REG)
-    {
-      rtx tmp = gen_reg_rtx (Pmode);
-      emit_move_insn (tmp, operands[1]);
-      operands[1] = tmp;
-    }
-}")
-
-(define_insn ""
-  [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
-   (clobber (match_operand:SI 0 "register_operand" "=a"))
-   (clobber (reg:SI 26))
-   (clobber (reg:SI 22))
-   (clobber (reg:SI 31))]
-  ""
-  "*
-{
-  /* Must import the magic millicode routine.  */
-  output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
-
-  /* This is absolutely amazing.
-
-     First, copy our input parameter into %r29 just in case we don't
-     need to call $$sh_func_adrs.  */
-  output_asm_insn (\"copy %%r26,%%r29\", NULL);
-
-  /* Next, examine the low two bits in %r26, if they aren't 0x2, then
-     we use %r26 unchanged.  */
-  if (get_attr_length (insn) == 32)
-    output_asm_insn (\"extru %%r26,31,2,%%r31\;comib,<>,n 2,%%r31,.+24\", NULL);
-  else if (get_attr_length (insn) == 40)
-    output_asm_insn (\"extru %%r26,31,2,%%r31\;comib,<>,n 2,%%r31,.+32\", NULL);
-  else if (get_attr_length (insn) == 44)
-    output_asm_insn (\"extru %%r26,31,2,%%r31\;comib,<>,n 2,%%r31,.+36\", NULL);
-  else
-    output_asm_insn (\"extru %%r26,31,2,%%r31\;comib,<>,n 2,%%r31,.+20\", NULL);
-
-  /* Next, compare %r26 with 4096, if %r26 is less than or equal to
-     4096, then we use %r26 unchanged.  */
-  if (get_attr_length (insn) == 32)
-    output_asm_insn (\"ldi 4096,%%r31\;comb,<<,n %%r26,%%r31,.+16\", NULL);
-  else if (get_attr_length (insn) == 40)
-    output_asm_insn (\"ldi 4096,%%r31\;comb,<<,n %%r26,%%r31,.+24\", NULL);
-  else if (get_attr_length (insn) == 44)
-    output_asm_insn (\"ldi 4096,%%r31\;comb,<<,n %%r26,%%r31,.+28\", NULL);
-  else
-    output_asm_insn (\"ldi 4096,%%r31\;comb,<<,n %%r26,%%r31,.+12\", NULL);
-
-  /* Else call $$sh_func_adrs to extract the function's real add24.  */
-  return output_millicode_call (insn,
-				gen_rtx_SYMBOL_REF (SImode, \"$$sh_func_adrs\"));
-}"
-  [(set_attr "type" "multi")
-   (set (attr "length")
-     (cond [
-;; Target (or stub) within reach
-            (and (lt (plus (symbol_ref "total_code_bytes") (pc))
-                     (const_int 240000))
-                 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-                     (const_int 0)))
-            (const_int 28)
-
-;; NO_SPACE_REGS
-            (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
-                (const_int 0))
-            (const_int 32)
-
-;; Out of reach, but not PIC or PORTABLE_RUNTIME
-;; same as NO_SPACE_REGS code
-            (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
-                     (const_int 0))
-                 (eq (symbol_ref "flag_pic")
-                     (const_int 0)))
-            (const_int 32)
-
-;; PORTABLE_RUNTIME
-	    (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
-		(const_int 0))
-	    (const_int 40)]
-
-;; Out of range and PIC 
-	  (const_int 44)))])
-
-;; On the PA, the PIC register is call clobbered, so it must
-;; be saved & restored around calls by the caller.  If the call
-;; doesn't return normally (nonlocal goto, or an exception is
-;; thrown), then the code at the exception handler label must
-;; restore the PIC register.
-(define_expand "exception_receiver"
-  [(const_int 4)]
-  "!TARGET_PORTABLE_RUNTIME && flag_pic"
-  "
-{
-  /* Load the PIC register from the stack slot (in our caller's
-     frame).  */
-  emit_move_insn (pic_offset_table_rtx,
-		  gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, -32)));
-  emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
-  emit_insn (gen_blockage ());
-  DONE;
-}")
-
-
diff --git a/gcc/config/pa/pa1.h b/gcc/config/pa/pa1.h
deleted file mode 100755
index 418de75..0000000
--- a/gcc/config/pa/pa1.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Definitions of target machine for GNU compiler, for HP PA-RISC 1.1
-   Copyright (C) 1991 Free Software Foundation, Inc.
-   Contributed by Tim Moore (moore@defmacro.cs.utah.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define TARGET_DEFAULT 0x89	/* TARGET_SNAKE + TARGET_GAS
-				   + TARGET_JUMP_IN_DELAY */
-
-/* This is the same as pa.h, except that we generate snake code by
-   default. */
-
-#include "pa/pa.h"
diff --git a/gcc/config/pa/rtems.h b/gcc/config/pa/rtems.h
deleted file mode 100755
index a0d5b7a..0000000
--- a/gcc/config/pa/rtems.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Definitions of target machine for GNU compiler, for PRO.
-   Copyright (C) 1997 Free Software Foundation, Inc.
-   Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dhppa -DPWB -Acpu(hppa) -Amachine(hppa) \
-   -Drtems -D__rtems__ -Asystem(rtems)"
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#ifndef TARGET_MEM_FUNCTIONS
-#define TARGET_MEM_FUNCTIONS
-#endif
diff --git a/gcc/config/pa/t-dce-thr b/gcc/config/pa/t-dce-thr
deleted file mode 100755
index 8d86a41..0000000
--- a/gcc/config/pa/t-dce-thr
+++ /dev/null
@@ -1,5 +0,0 @@
-MULTILIB_OPTIONS = threads
-MULTILIB_DIRNAMES = threads
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/pa/t-pa b/gcc/config/pa/t-pa
deleted file mode 100755
index a359918..0000000
--- a/gcc/config/pa/t-pa
+++ /dev/null
@@ -1,18 +0,0 @@
-LIBGCC1=libgcc1.null
-CROSS_LIBGCC1=libgcc1.null
-ADA_CFLAGS=-mdisable-indexing
-LIB2FUNCS_EXTRA=lib2funcs.asm ee.asm ee_fp.asm
-
-lib2funcs.asm: $(srcdir)/config/pa/lib2funcs.asm
-	rm -f lib2funcs.asm
-	cp $(srcdir)/config/pa/lib2funcs.asm .
-
-ee.asm: $(srcdir)/config/pa/ee.asm
-	rm -f ee.asm
-	cp $(srcdir)/config/pa/ee.asm .
-
-ee_fp.asm: $(srcdir)/config/pa/ee_fp.asm
-	rm -f ee_fp.asm
-	cp $(srcdir)/config/pa/ee_fp.asm .
-
-TARGET_LIBGCC2_CFLAGS = -fPIC
diff --git a/gcc/config/pa/t-pro b/gcc/config/pa/t-pro
deleted file mode 100755
index f40b2e4..0000000
--- a/gcc/config/pa/t-pro
+++ /dev/null
@@ -1,38 +0,0 @@
-LIBGCC1=libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
-LIB1ASMSRC =
-LIB1ASMFUNCS =
-
-LIBGCC1_TEST =
-
-ADA_CFLAGS=-mdisable-indexing
-
-LIB2FUNCS_EXTRA=fp-bit.c dp-bit.c lib2funcs.asm ee.asm ee_fp.asm
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-lib2funcs.asm: $(srcdir)/config/pa/lib2funcs.asm
-	rm -f lib2funcs.asm
-	cp $(srcdir)/config/pa/lib2funcs.asm .
-
-ee.asm: $(srcdir)/config/pa/ee.asm
-	rm -f ee.asm
-	cp $(srcdir)/config/pa/ee.asm .
-
-ee_fp.asm: $(srcdir)/config/pa/ee_fp.asm
-	rm -f ee_fp.asm
-	cp $(srcdir)/config/pa/ee_fp.asm .
-
-# Build the libraries for both speed and space optimizations
-
-MULTILIB_OPTIONS=mspace
-MULTILIB_DIRNAMES=space
-MULTILIB_MATCHES=
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/pa/x-pa b/gcc/config/pa/x-pa
deleted file mode 100755
index 4c25047..0000000
--- a/gcc/config/pa/x-pa
+++ /dev/null
@@ -1,3 +0,0 @@
-# BSD on the PA already has ANSI include files which are c++ compatible.
-USER_H = $(EXTRA_HEADERS) $(LANG_EXTRA_HEADERS)
-STMP_FIXPROTO=
diff --git a/gcc/config/pa/x-pa-hpux b/gcc/config/pa/x-pa-hpux
deleted file mode 100755
index 1b8bb9f..0000000
--- a/gcc/config/pa/x-pa-hpux
+++ /dev/null
@@ -1,4 +0,0 @@
-ALLOCA=alloca.o
-
-# So putenv and other functions get seen by fixproto.
-FIXPROTO_DEFINES = -D_HPUX_SOURCE
diff --git a/gcc/config/pa/xm-pa.h b/gcc/config/pa/xm-pa.h
deleted file mode 100755
index 0249055..0000000
--- a/gcc/config/pa/xm-pa.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Configuration for GNU C-compiler for PA-RISC.
-   Copyright (C) 1988, 1995 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-extern int errno;
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Doubles are stored in memory with the high order word first.  This
-   matters when cross-compiling.  */
-#define HOST_WORDS_BIG_ENDIAN 1
-
-/* Place any machine-dependent include files here, in case we
-   are bootstrapping.  */
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* Don't try to use sys_siglist.  */
-#define NO_SYS_SIGLIST
-
-/* 4.3BSD, OSF1 and Lites on the PA are all derived from NET2 or
-   later code from Berkeley.  */
-#define __BSD_NET2__
-
-/* HP's compiler has problems with enum bitfields.  */
-#define ONLY_INT_FIELDS
-
-/* Always claim to use C alloca; this prevents losing if building with
-   gcc -fno-builtin ... */
-#define USE_C_ALLOCA
diff --git a/gcc/config/pa/xm-pahpux.h b/gcc/config/pa/xm-pahpux.h
deleted file mode 100755
index 09c949b..0000000
--- a/gcc/config/pa/xm-pahpux.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Configuration for GNU C-compiler for PA-RISC.
-   Copyright (C) 1988, 1995, 1997 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* HP-UX is a flavor of System V */
-#define USG
-
-/* Use System V memory functions.  */
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Doubles are stored in memory with the high order word first.  This
-   matters when cross-compiling.  */
-#define HOST_WORDS_BIG_ENDIAN 1
-
-/* Place any machine-dependent include files here, in case we
-   are bootstrapping.  */
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* Don't try to use sys_siglist.  */
-#define NO_SYS_SIGLIST
-
-/* HP's compiler has problems with enum bitfields.  */
-#define ONLY_INT_FIELDS
-
-/* Always claim to use C alloca; this prevents losing if building with
-   gcc -fno-builtin ... "  */
-#define USE_C_ALLOCA
diff --git a/gcc/config/pa/xm-papro.h b/gcc/config/pa/xm-papro.h
deleted file mode 100755
index d36e201..0000000
--- a/gcc/config/pa/xm-papro.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Configuration for GNU C-compiler for PA-RISC.
-   Copyright (C) 1994, 1995 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-extern int errno;
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Doubles are stored in memory with the high order word first.  This
-   matters when cross-compiling.  */
-#define HOST_WORDS_BIG_ENDIAN 1
-
-/* Place any machine-dependent include files here, in case we
-   are bootstrapping.  */
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* Don't try to use sys_siglist.  */
-#define NO_SYS_SIGLIST
-
-/* HP's compiler has problems with enum bitfields.  */
-#define ONLY_INT_FIELDS
-
-/* Always claim to use C alloca; this prevents losing if building with
-   gcc -fno-builtin ... */
-#define USE_C_ALLOCA
diff --git a/gcc/config/pdp11/2bsd.h b/gcc/config/pdp11/2bsd.h
deleted file mode 100755
index 401df17..0000000
--- a/gcc/config/pdp11/2bsd.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Definitions of target machine for GNU compiler, for a PDP with 2BSD
-   Copyright (C) 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This macro generates the assembly code for function entry. */
-#undef FUNCTION_PROLOGUE
-#define FUNCTION_PROLOGUE(FILE, SIZE) \
-do {									\
-fprintf(FILE, "\tjsr	r5, csv\n");					\
-if ((SIZE) != 0)							\
-  {									\
-    fprintf(FILE, "\t/*abuse empty parameter slot for locals!*/\n");	\
-    if ((SIZE) > 2)							\
-      fprintf(FILE, "\tsub $%d, sp\n", (SIZE)-2);			\
-  };									\
-} while (0)
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#undef EXIT_IGNORE_STACK
-#define EXIT_IGNORE_STACK	1
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-*/
-
-#undef FUNCTION_EPILOGUE
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-do {                                                                    \
-fprintf(FILE, "\t/* SP ignored by cret? */\n");     			\
-fprintf(FILE, "\tjmp cret\n");                                    	\
-} while (0)
-
-#undef INITIAL_FRAME_POINTER_OFFSET  
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR)	\
-{								\
-  int offset, regno;		      				\
-  offset = get_frame_size();					\
-  offset = (offset <= 2)? 0: (offset -2);			\
-  (DEPTH_VAR) = offset+10;						\
-}   
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.
-  */
-
-#undef FRAME_POINTER_REQUIRED 
-#define FRAME_POINTER_REQUIRED 1
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#undef STARTING_FRAME_OFFSET
-#define STARTING_FRAME_OFFSET -8
-
-
-#undef ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL)	\
-do {							\
-ASM_OUTPUT_LABEL (STREAM, NAME);			\
-fprintf (STREAM, "~~%s:\n", NAME); 			\
-} while (0)
diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c
deleted file mode 100755
index 9bf69dd..0000000
--- a/gcc/config/pdp11/pdp11.c
+++ /dev/null
@@ -1,1415 +0,0 @@
-/* Subroutines for gcc2 for pdp11.
-   Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-
-/*
-#define FPU_REG_P(X)	((X)>=8 && (X)<14)
-#define CPU_REG_P(X)	((X)>=0 && (X)<8)
-*/
-
-/* this is the current value returned by the macro FIRST_PARM_OFFSET 
-   defined in tm.h */
-int current_first_parm_offset;
-
-/* This is where the condition code register lives.  */
-/* rtx cc0_reg_rtx; - no longer needed? */
-
-static rtx find_addr_reg (); 
-
-/* Nonzero if OP is a valid second operand for an arithmetic insn.  */
-
-int
-arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode) || GET_CODE (op) == CONST_INT);
-}
-
-int
-const_immediate_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == CONST_INT);
-}
-
-int 
-immediate15_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-    return (GET_CODE (op) == CONST_INT && ((INTVAL (op) & 0x8000) == 0x0000));
-}
-
-int
-expand_shift_operand (op, mode)
-  rtx op;
-  enum machine_mode mode;
-{
-    return (GET_CODE (op) == CONST_INT 
-	    && abs (INTVAL(op)) > 1 
-	    && abs (INTVAL(op)) <= 4);
-}
-
-/*
-   stream is a stdio stream to output the code to.
-   size is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  
-*/
-
-void 
-output_function_prologue(stream, size)
-  FILE *stream;
-  int size;
-{							       
-    int fsize = ((size) + 1) & ~1;      				
-    int regno, nregs, i;						
-    int offset = 0;
-
-    int via_ac = -1;
-    
-    fprintf (stream, "\n\t;	/* function prologue %s*/\n", current_function_name);		
-
-    /* if we are outputting code for main, 
-       the switch FPU to right mode if TARGET_FPU */
-    if ( (strcmp ("main", current_function_name) == 0)
-	 && TARGET_FPU)
-    {
-	fprintf(stream, "\t;/* switch cpu to double float, single integer */\n");
-	fprintf(stream, "\tsetd\n");
-	fprintf(stream, "\tseti\n\n");
-    }
-    
-    if (frame_pointer_needed) 					
-    {								
-	fprintf(stream, "\tmov fp, -(sp)\n");			
-	fprintf(stream, "\tmov sp, fp\n");				
-    }								
-    else 								
-    {								
-	/* DON'T SAVE FP */
-    }								
-
-    /* make frame */
-    if (fsize)							
-	fprintf (stream, "\tsub $%d, sp\n", fsize);			
-
-    /* save CPU registers  */
-    for (regno = 0; regno < 8; regno++)				
-	if (regs_ever_live[regno] && ! call_used_regs[regno])	
-	    if (! ((regno == FRAME_POINTER_REGNUM)			
-		   && frame_pointer_needed))				
-		fprintf (stream, "\tmov %s, -(sp)\n", reg_names[regno]);	
-    /* fpu regs saving */
-    
-    /* via_ac specifies the ac to use for saving ac4, ac5 */
-    via_ac = -1;
-    
-    for (regno = 8; regno < FIRST_PSEUDO_REGISTER ; regno++) 
-    {
-	/* ac0 - ac3 */						
-	if (LOAD_FPU_REG_P(regno)
-	    && regs_ever_live[regno] 
-	    && ! call_used_regs[regno])
-	{
-	    fprintf (stream, "\tfstd %s, -(sp)\n", reg_names[regno]);
-	    via_ac = regno;
-	}
-	
-	/* maybe make ac4, ac5 call used regs?? */
-	/* ac4 - ac5 */
-	if (NO_LOAD_FPU_REG_P(regno)
-	    && regs_ever_live[regno]
-	    && ! call_used_regs[regno])
-	{
-	    if (via_ac == -1)
-		abort();
-	    
-	    fprintf (stream, "\tfldd %s, %s\n", reg_names[regno], reg_names[via_ac]);
-	    fprintf (stream, "\tfstd %s, -(sp)\n", reg_names[via_ac]);
-	}
-    }
-
-    fprintf (stream, "\t;/* end of prologue */\n\n");		
-}
-
-/*
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-/* maybe we can make leaf functions faster by switching to the
-   second register file - this way we don't have to save regs!
-   leaf functions are ~ 50% of all functions (dynamically!) 
-
-   set/clear bit 11 (dec. 2048) of status word for switching register files - 
-   but how can we do this? the pdp11/45 manual says bit may only 
-   be set (p.24), but not cleared!
-
-   switching to kernel is probably more expensive, so we'll leave it 
-   like this and not use the second set of registers... 
-
-   maybe as option if you want to generate code for kernel mode? */
-
-
-void 
-output_function_epilogue(stream, size)
-  FILE *stream;
-  int size;
-{								
-    extern int may_call_alloca;
-
-    int fsize = ((size) + 1) & ~1;      				
-    int nregs, regno, i, j, k, adjust_fp;				
-
-    int via_ac;
-    
-    fprintf (stream, "\n\t;	/*function epilogue */\n");		
-
-    if (frame_pointer_needed)					
-    {								
-	/* hope this is safe - m68k does it also .... */		
-	regs_ever_live[FRAME_POINTER_REGNUM] = 0;			
-								
-	for (i =7, j = 0 ; i >= 0 ; i--)				
-	    if (regs_ever_live[i] && ! call_used_regs[i])		
-		j++;
-	
-	/* remember # of pushed bytes for CPU regs */
-	k = 2*j;
-	
-	for (i =7 ; i >= 0 ; i--)					
-	    if (regs_ever_live[i] && ! call_used_regs[i])		
-		fprintf(stream, "\tmov %d(fp), %s\n",-fsize-2*j--, reg_names[i]);
-
-	/* get ACs */						
-	via_ac = FIRST_PSEUDO_REGISTER -1;
-	
-	for (i = FIRST_PSEUDO_REGISTER; i > 7; i--)
-	    if (regs_ever_live[i] && ! call_used_regs[i])
-	    {
-		via_ac = i;
-		k += 8;
-	    }
-	
-	for (i = FIRST_PSEUDO_REGISTER; i > 7; i--)
-	{
-	    if (LOAD_FPU_REG_P(i)
-		&& regs_ever_live[i]
-		&& ! call_used_regs[i])
-	    {
-		fprintf(stream, "\tfldd %d(fp), %s\n", -fsize-k, reg_names[i]);
-		k -= 8;
-	    }
-	    
-	    if (NO_LOAD_FPU_REG_P(i)
-		&& regs_ever_live[i]
-		&& ! call_used_regs[i])
-	    {
-		if (! LOAD_FPU_REG_P(via_ac))
-		    abort();
-		    
-		fprintf(stream, "\tfldd %d(fp), %s\n", -fsize-k, reg_names[via_ac]);
-		fprintf(stream, "\tfstd %s, %s\n", reg_names[via_ac], reg_names[i]);
-		k -= 8;
-	    }
-	}
-	
-	fprintf(stream, "\tmov fp, sp\n");				
-	fprintf (stream, "\tmov (sp)+, fp\n");     			
-    }								
-    else								
-    {		   
-	via_ac = FIRST_PSEUDO_REGISTER -1;
-	
-	/* get ACs */
-	for (i = FIRST_PSEUDO_REGISTER; i > 7; i--)
-	    if (regs_ever_live[i] && call_used_regs[i])
-		via_ac = i;
-	
-	for (i = FIRST_PSEUDO_REGISTER; i > 7; i--)
-	{
-	    if (LOAD_FPU_REG_P(i)
-		&& regs_ever_live[i]
-		&& ! call_used_regs[i])
-	      fprintf(stream, "\tfldd (sp)+, %s\n", reg_names[i]);
-	    
-	    if (NO_LOAD_FPU_REG_P(i)
-		&& regs_ever_live[i]
-		&& ! call_used_regs[i])
-	    {
-		if (! LOAD_FPU_REG_P(via_ac))
-		    abort();
-		    
-		fprintf(stream, "\tfldd (sp)+, %s\n", reg_names[via_ac]);
-		fprintf(stream, "\tfstd %s, %s\n", reg_names[via_ac], reg_names[i]);
-	    }
-	}
-
-	for (i=7; i >= 0; i--)					
-	    if (regs_ever_live[i] && !call_used_regs[i])		
-		fprintf(stream, "\tmov (sp)+, %s\n", reg_names[i]);	
-								
-	if (fsize)						
-	    fprintf((stream), "\tadd $%d, sp\n", fsize);      		
-    }			
-					
-    fprintf (stream, "\trts pc\n");					
-    fprintf (stream, "\t;/* end of epilogue*/\n\n\n");		
-}
-	
-/* Return the best assembler insn template
-   for moving operands[1] into operands[0] as a fullword.  */
-static char *
-singlemove_string (operands)
-     rtx *operands;
-{
-  if (operands[1] != const0_rtx)
-    return "mov %1,%0";
-
-  return "clr %0";
-}
-
-
-/* Output assembler code to perform a doubleword move insn
-   with operands OPERANDS.  */
-
-char *
-output_move_double (operands)
-     rtx *operands;
-{
-  enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
-  rtx latehalf[2];
-  rtx addreg0 = 0, addreg1 = 0;
-
-  /* First classify both operands.  */
-
-  if (REG_P (operands[0]))
-    optype0 = REGOP;
-  else if (offsettable_memref_p (operands[0]))
-    optype0 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    optype0 = POPOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    optype0 = PUSHOP;
-  else if (GET_CODE (operands[0]) == MEM)
-    optype0 = MEMOP;
-  else
-    optype0 = RNDOP;
-
-  if (REG_P (operands[1]))
-    optype1 = REGOP;
-  else if (CONSTANT_P (operands[1]))
-#if 0
-	   || GET_CODE (operands[1]) == CONST_DOUBLE)
-#endif
-    optype1 = CNSTOP;
-  else if (offsettable_memref_p (operands[1]))
-    optype1 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
-    optype1 = POPOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
-    optype1 = PUSHOP;
-  else if (GET_CODE (operands[1]) == MEM)
-    optype1 = MEMOP;
-  else
-    optype1 = RNDOP;
-
-  /* Check for the cases that the operand constraints are not
-     supposed to allow to happen.  Abort if we get one,
-     because generating code for these cases is painful.  */
-
-  if (optype0 == RNDOP || optype1 == RNDOP)
-    abort ();
-
-  /* If one operand is decrementing and one is incrementing
-     decrement the former register explicitly
-     and change that operand into ordinary indexing.  */
-
-  if (optype0 == PUSHOP && optype1 == POPOP)
-    {
-      operands[0] = XEXP (XEXP (operands[0], 0), 0);
-      output_asm_insn ("sub $4,%0", operands);
-      operands[0] = gen_rtx (MEM, SImode, operands[0]);
-      optype0 = OFFSOP;
-    }
-  if (optype0 == POPOP && optype1 == PUSHOP)
-    {
-      operands[1] = XEXP (XEXP (operands[1], 0), 0);
-      output_asm_insn ("sub $4,%1", operands);
-      operands[1] = gen_rtx (MEM, SImode, operands[1]);
-      optype1 = OFFSOP;
-    }
-
-  /* If an operand is an unoffsettable memory ref, find a register
-     we can increment temporarily to make it refer to the second word.  */
-
-  if (optype0 == MEMOP)
-    addreg0 = find_addr_reg (XEXP (operands[0], 0));
-
-  if (optype1 == MEMOP)
-    addreg1 = find_addr_reg (XEXP (operands[1], 0));
-
-  /* Ok, we can do one word at a time.
-     Normally we do the low-numbered word first,
-     but if either operand is autodecrementing then we
-     do the high-numbered word first.
-
-     In either case, set up in LATEHALF the operands to use
-     for the high-numbered word and in some cases alter the
-     operands in OPERANDS to be suitable for the low-numbered word.  */
-
-  if (optype0 == REGOP)
-    latehalf[0] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
-  else if (optype0 == OFFSOP)
-    latehalf[0] = adj_offsettable_operand (operands[0], 2);
-  else
-    latehalf[0] = operands[0];
-
-  if (optype1 == REGOP)
-    latehalf[1] = gen_rtx (REG, HImode, REGNO (operands[1]) + 1);
-  else if (optype1 == OFFSOP)
-    latehalf[1] = adj_offsettable_operand (operands[1], 2);
-  else if (optype1 == CNSTOP)
-    {
-	if (CONSTANT_P (operands[1]))
-	{
-	    /* now the mess begins, high word is in lower word??? 
-
-	       that's what ashc makes me think, but I don't remember :-( */
-	    latehalf[1] = GEN_INT (INTVAL(operands[1])>>16);
-	    operands[1] = GEN_INT (INTVAL(operands[1])&0xff);
-	}
-      else if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	{
-	    /* immediate 32 bit values not allowed */
-	    abort();
-	}
-    }
-  else
-    latehalf[1] = operands[1];
-
-  /* If insn is effectively movd N(sp),-(sp) then we will do the
-     high word first.  We should use the adjusted operand 1 (which is N+4(sp))
-     for the low word as well, to compensate for the first decrement of sp.  */
-  if (optype0 == PUSHOP
-      && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
-      && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
-    operands[1] = latehalf[1];
-
-  /* If one or both operands autodecrementing,
-     do the two words, high-numbered first.  */
-
-  /* Likewise,  the first move would clobber the source of the second one,
-     do them in the other order.  This happens only for registers;
-     such overlap can't happen in memory unless the user explicitly
-     sets it up, and that is an undefined circumstance.  */
-
-  if (optype0 == PUSHOP || optype1 == PUSHOP
-      || (optype0 == REGOP && optype1 == REGOP
-	  && REGNO (operands[0]) == REGNO (latehalf[1])))
-    {
-      /* Make any unoffsettable addresses point at high-numbered word.  */
-      if (addreg0)
-	output_asm_insn ("add $2,%0", &addreg0);
-      if (addreg1)
-	output_asm_insn ("add $2,%0", &addreg1);
-
-      /* Do that word.  */
-      output_asm_insn (singlemove_string (latehalf), latehalf);
-
-      /* Undo the adds we just did.  */
-      if (addreg0)
-	output_asm_insn ("sub $2,%0", &addreg0);
-      if (addreg1)
-	output_asm_insn ("sub $2,%0", &addreg1);
-
-      /* Do low-numbered word.  */
-      return singlemove_string (operands);
-    }
-
-  /* Normal case: do the two words, low-numbered first.  */
-
-  output_asm_insn (singlemove_string (operands), operands);
-
-  /* Make any unoffsettable addresses point at high-numbered word.  */
-  if (addreg0)
-    output_asm_insn ("add $2,%0", &addreg0);
-  if (addreg1)
-    output_asm_insn ("add $2,%0", &addreg1);
-
-  /* Do that word.  */
-  output_asm_insn (singlemove_string (latehalf), latehalf);
-
-  /* Undo the adds we just did.  */
-  if (addreg0)
-    output_asm_insn ("sub $2,%0", &addreg0);
-  if (addreg1)
-    output_asm_insn ("sub $2,%0", &addreg1);
-
-  return "";
-}
-/* Output assembler code to perform a quadword move insn
-   with operands OPERANDS.  */
-
-char *
-output_move_quad (operands)
-     rtx *operands;
-{
-  enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
-  rtx latehalf[2];
-  rtx addreg0 = 0, addreg1 = 0;
-
-  output_asm_insn(";; movdi/df: %1 -> %0", operands);
-  
-  if (REG_P (operands[0]))
-    optype0 = REGOP;
-  else if (offsettable_memref_p (operands[0]))
-    optype0 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    optype0 = POPOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-    optype0 = PUSHOP;
-  else if (GET_CODE (operands[0]) == MEM)
-    optype0 = MEMOP;
-  else
-    optype0 = RNDOP;
-
-  if (REG_P (operands[1]))
-    optype1 = REGOP;
-  else if (CONSTANT_P (operands[1])
-	   || GET_CODE (operands[1]) == CONST_DOUBLE)
-    optype1 = CNSTOP;
-  else if (offsettable_memref_p (operands[1]))
-    optype1 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
-    optype1 = POPOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
-    optype1 = PUSHOP;
-  else if (GET_CODE (operands[1]) == MEM)
-    optype1 = MEMOP;
-  else
-    optype1 = RNDOP;
-
-  /* Check for the cases that the operand constraints are not
-     supposed to allow to happen.  Abort if we get one,
-     because generating code for these cases is painful.  */
-
-  if (optype0 == RNDOP || optype1 == RNDOP)
-    abort ();
-  
-  /* check if we move a CPU reg to an FPU reg, or vice versa! */
-  if (optype0 == REGOP && optype1 == REGOP)
-      /* bogus - 64 bit cannot reside in CPU! */
-      if (CPU_REG_P(REGNO(operands[0]))
-	  || CPU_REG_P (REGNO(operands[1])))
-	  abort();
-  
-  if (optype0 == REGOP || optype1 == REGOP)
-  {
-      /* check for use of clrd???? 
-         if you ever allow ac4 and ac5 (now we require secondary load) 
-	 you must check whether 
-	 you want to load into them or store from them - 
-	 then dump ac0 into $help$ movce ac4/5 to ac0, do the 
-	 store from ac0, and restore ac0 - if you can find 
-	 an unused ac[0-3], use that and you save a store and a load!*/
-
-      if (FPU_REG_P(REGNO(operands[0])))
-      {
-	  if (GET_CODE(operands[1]) == CONST_DOUBLE)
-	  {
-	      union { double d; int i[2]; } u;
-	      u.i[0] = CONST_DOUBLE_LOW (operands[1]); 
-	      u.i[1] = CONST_DOUBLE_HIGH (operands[1]); 
-	      
-	      if (u.d == 0.0)
-		  return "clrd %0";
-	  }
-	      
-	  return "ldd %1, %0";
-      }
-      
-      if (FPU_REG_P(REGNO(operands[1])))
-	  return "std %1, %0";
-  }
-      
-  /* If one operand is decrementing and one is incrementing
-     decrement the former register explicitly
-     and change that operand into ordinary indexing.  */
-
-  if (optype0 == PUSHOP && optype1 == POPOP)
-    {
-      operands[0] = XEXP (XEXP (operands[0], 0), 0);
-      output_asm_insn ("sub $8,%0", operands);
-      operands[0] = gen_rtx (MEM, DImode, operands[0]);
-      optype0 = OFFSOP;
-    }
-  if (optype0 == POPOP && optype1 == PUSHOP)
-    {
-      operands[1] = XEXP (XEXP (operands[1], 0), 0);
-      output_asm_insn ("sub $8,%1", operands);
-      operands[1] = gen_rtx (MEM, SImode, operands[1]);
-      optype1 = OFFSOP;
-    }
-
-  /* If an operand is an unoffsettable memory ref, find a register
-     we can increment temporarily to make it refer to the second word.  */
-
-  if (optype0 == MEMOP)
-    addreg0 = find_addr_reg (XEXP (operands[0], 0));
-
-  if (optype1 == MEMOP)
-    addreg1 = find_addr_reg (XEXP (operands[1], 0));
-
-  /* Ok, we can do one word at a time.
-     Normally we do the low-numbered word first,
-     but if either operand is autodecrementing then we
-     do the high-numbered word first.
-
-     In either case, set up in LATEHALF the operands to use
-     for the high-numbered word and in some cases alter the
-     operands in OPERANDS to be suitable for the low-numbered word.  */
-
-  if (optype0 == REGOP)
-    latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
-  else if (optype0 == OFFSOP)
-    latehalf[0] = adj_offsettable_operand (operands[0], 4);
-  else
-    latehalf[0] = operands[0];
-
-  if (optype1 == REGOP)
-    latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
-  else if (optype1 == OFFSOP)
-    latehalf[1] = adj_offsettable_operand (operands[1], 4);
-  else if (optype1 == CNSTOP)
-    {
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	{
-	    /* floats only. not yet supported!
-
-	     -- compute it into PDP float format, - internally,
-	     just use IEEE and ignore possible problems ;-)
-
-	     we might get away with it !!!! */
-
-	    abort();
-	    
-#ifndef HOST_WORDS_BIG_ENDIAN
-	  latehalf[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-	  operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
-#else /* HOST_WORDS_BIG_ENDIAN */
-	  latehalf[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
-	  operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-#endif /* HOST_WORDS_BIG_ENDIAN */
-	}
-      else if (GET_CODE(operands[1]) == CONST_INT)
-      {
-	  latehalf[1] = GEN_INT (0);
-      }
-      else
-	  abort();
-      
-    }
-  else
-    latehalf[1] = operands[1];
-
-  /* If insn is effectively movd N(sp),-(sp) then we will do the
-     high word first.  We should use the adjusted operand 1 (which is N+4(sp))
-     for the low word as well, to compensate for the first decrement of sp.  */
-  if (optype0 == PUSHOP
-      && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
-      && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
-    operands[1] = latehalf[1];
-
-  /* If one or both operands autodecrementing,
-     do the two words, high-numbered first.  */
-
-  /* Likewise,  the first move would clobber the source of the second one,
-     do them in the other order.  This happens only for registers;
-     such overlap can't happen in memory unless the user explicitly
-     sets it up, and that is an undefined circumstance.  */
-
-  if (optype0 == PUSHOP || optype1 == PUSHOP
-      || (optype0 == REGOP && optype1 == REGOP
-	  && REGNO (operands[0]) == REGNO (latehalf[1])))
-    {
-      /* Make any unoffsettable addresses point at high-numbered word.  */
-      if (addreg0)
-	output_asm_insn ("add $4,%0", &addreg0);
-      if (addreg1)
-	output_asm_insn ("add $4,%0", &addreg1);
-
-      /* Do that word.  */
-      output_asm_insn(output_move_double(latehalf), latehalf);
-
-      /* Undo the adds we just did.  */
-      if (addreg0)
-	output_asm_insn ("sub $4,%0", &addreg0);
-      if (addreg1)
-	output_asm_insn ("sub $4,%0", &addreg1);
-
-      /* Do low-numbered word.  */
-      return output_move_double (operands);
-    }
-
-  /* Normal case: do the two words, low-numbered first.  */
-
-  output_asm_insn (output_move_double (operands), operands);
-
-  /* Make any unoffsettable addresses point at high-numbered word.  */
-  if (addreg0)
-    output_asm_insn ("add $4,%0", &addreg0);
-  if (addreg1)
-    output_asm_insn ("add $4,%0", &addreg1);
-
-  /* Do that word.  */
-  output_asm_insn (output_move_double (latehalf), latehalf);
-
-  /* Undo the adds we just did.  */
-  if (addreg0)
-    output_asm_insn ("sub $4,%0", &addreg0);
-  if (addreg1)
-    output_asm_insn ("sub $4,%0", &addreg1);
-
-  return "";
-}
-
-
-/* Return a REG that occurs in ADDR with coefficient 1.
-   ADDR can be effectively incremented by incrementing REG.  */
-
-static rtx
-find_addr_reg (addr)
-     rtx addr;
-{
-  while (GET_CODE (addr) == PLUS)
-    {
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-	addr = XEXP (addr, 0);
-      if (GET_CODE (XEXP (addr, 1)) == REG)
-	addr = XEXP (addr, 1);
-      if (CONSTANT_P (XEXP (addr, 0)))
-	addr = XEXP (addr, 1);
-      if (CONSTANT_P (XEXP (addr, 1)))
-	addr = XEXP (addr, 0);
-    }
-  if (GET_CODE (addr) == REG)
-    return addr;
-  return 0;
-}
-
-/* Output an ascii string.  */
-output_ascii (file, p, size)
-     FILE *file;
-     char *p;
-     int size;
-{
-  int i;
-
-  fprintf (file, "\t.byte \"");
-
-  for (i = 0; i < size; i++)
-    {
-      register int c = p[i];
-      if (c == '\"' || c == '\\')
-	putc ('\\', file);
-      if (c >= ' ' && c < 0177)
-	putc (c, file);
-      else
-	{
-	  fprintf (file, "\\%03o", c);
-	  /* After an octal-escape, if a digit follows,
-	     terminate one string constant and start another.
-	     The Vax assembler fails to stop reading the escape
-	     after three digits, so this is the only way we
-	     can get it to parse the data properly.  */
-	  if (i < size - 1 && p[i + 1] >= '0' && p[i + 1] <= '9')
-	    fprintf (file, "\"\n\tstring \"");
-	}
-    }
-  fprintf (file, "\"\n");
-}
-
-
-/* --- stole from out-vax, needs changes */
-
-print_operand_address (file, addr)
-     FILE *file;
-     register rtx addr;
-{
-  register rtx reg1, reg2, breg, ireg;
-  rtx offset;
-
- retry:
-
-  switch (GET_CODE (addr))
-    {
-    case MEM:
-      fprintf (file, "@");
-      addr = XEXP (addr, 0);
-      goto retry;
-
-    case REG:
-      fprintf (file, "(%s)", reg_names[REGNO (addr)]);
-      break;
-
-    case PRE_DEC:
-      fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case POST_INC:
-      fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case PLUS:
-      reg1 = 0;	reg2 = 0;
-      ireg = 0;	breg = 0;
-      offset = 0;
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
-	  || GET_CODE (XEXP (addr, 0)) == MEM)
-	{
-	  offset = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
-	}
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
-	       || GET_CODE (XEXP (addr, 1)) == MEM)
-	{
-	  offset = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-      if (GET_CODE (addr) != PLUS)
-	;
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)
-	{
-	  reg1 = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
-	}
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)
-	{
-	  reg1 = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-      else if (GET_CODE (XEXP (addr, 0)) == REG)
-	{
-	  reg1 = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
-	}
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	{
-	  reg1 = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
-	{
-	  if (reg1 == 0)
-	    reg1 = addr;
-	  else
-	    reg2 = addr;
-	  addr = 0;
-	}
-      if (offset != 0)
-	{
-	  if (addr != 0) abort ();
-	  addr = offset;
-	}
-      if (reg1 != 0 && GET_CODE (reg1) == MULT)
-	{
-	  breg = reg2;
-	  ireg = reg1;
-	}
-      else if (reg2 != 0 && GET_CODE (reg2) == MULT)
-	{
-	  breg = reg1;
-	  ireg = reg2;
-	}
-      else if (reg2 != 0 || GET_CODE (addr) == MEM)
-	{
-	  breg = reg2;
-	  ireg = reg1;
-	}
-      else
-	{
-	  breg = reg1;
-	  ireg = reg2;
-	}
-      if (addr != 0)
-	output_address (addr);
-      if (breg != 0)
-	{
-	  if (GET_CODE (breg) != REG)
-	    abort ();
-	  fprintf (file, "(%s)", reg_names[REGNO (breg)]);
-	}
-      if (ireg != 0)
-	{
-	  if (GET_CODE (ireg) == MULT)
-	    ireg = XEXP (ireg, 0);
-	  if (GET_CODE (ireg) != REG)
-	    abort ();
-	  abort();
-	  fprintf (file, "[%s]", reg_names[REGNO (ireg)]);
-	}
-      break;
-
-    default:
-      output_addr_const (file, addr);
-    }
-}
-
-/* register move costs, indexed by regs */
-
-static int move_costs[N_REG_CLASSES][N_REG_CLASSES] = 
-{
-             /* NO  MUL  GEN  LFPU  NLFPU FPU ALL */
-
-/* NO */     {  0,   0,   0,    0,    0,    0,   0},
-/* MUL */    {  0,   2,   2,   10,   22,   22,  22},
-/* GEN */    {  0,   2,   2,   10,   22,   22,  22},
-/* LFPU */   {  0,  10,  10,    2,    2,    2,  10},
-/* NLFPU */  {  0,  22,  22,    2,    2,    2,  22},
-/* FPU */    {  0,  22,  22,    2,    2,    2,  22},
-/* ALL */    {  0,  22,  22,   10,   22,   22,  22}
-}  ;
-
-
-/* -- note that some moves are tremendously expensive, 
-   because they require lots of tricks! do we have to 
-   charge the costs incurred by secondary reload class 
-   -- as we do here with 22 -- or not ? */
-
-int 
-register_move_cost(c1, c2)
-  enum reg_class c1, c2;
-{
-    return move_costs[(int)c1][(int)c2];
-}
-
-char *
-output_jump(pos, neg, length)
-  int length;
-  char *pos, *neg;
-{
-    static int x = 0;
-    
-    static char buf[1000];
-
-#if 0
-/* currently we don't need this, because the tstdf and cmpdf 
-   copy the condition code immediately, and other float operations are not 
-   yet recognized as changing the FCC - if so, then the length-cost of all
-   jump insns increases by one, because we have to potentially copy the 
-   FCC! */
-    if (cc_status.flags & CC_IN_FPU)
-	output_asm_insn("cfcc", NULL);
-#endif
-	
-    switch (length)
-    {
-      case 1:
-	
-	strcpy(buf, pos);
-	strcat(buf, " %l0");
-	
-	return buf;
-	
-      case 3:
-	
-	sprintf(buf, "%s JMP_%d\n\tjmp %%l0\nJMP_%d:", neg, x, x);
-	
-	x++;
-	
-	return buf;
-	
-      default:
-	
-	abort();
-    }
-    
-}
-
-void
-notice_update_cc_on_set(exp, insn)
-  rtx exp;
-  rtx insn;
-{
-    if (GET_CODE (SET_DEST (exp)) == CC0)
-    { 
-	cc_status.flags = 0;					
-	cc_status.value1 = SET_DEST (exp);			
-	cc_status.value2 = SET_SRC (exp);			
-
-/*
-	if (GET_MODE(SET_SRC(exp)) == DFmode)
-	    cc_status.flags |= CC_IN_FPU;
-*/	
-    }							
-    else if ((GET_CODE (SET_DEST (exp)) == REG		
-	      || GET_CODE (SET_DEST (exp)) == MEM)		
-	     && GET_CODE (SET_SRC (exp)) != PC		
-	     && (GET_MODE (SET_DEST(exp)) == HImode		
-		 || GET_MODE (SET_DEST(exp)) == QImode)	
-		&& (GET_CODE (SET_SRC(exp)) == PLUS		
-		    || GET_CODE (SET_SRC(exp)) == MINUS	
-		    || GET_CODE (SET_SRC(exp)) == AND	
-		    || GET_CODE (SET_SRC(exp)) == IOR	
-		    || GET_CODE (SET_SRC(exp)) == XOR	
-		    || GET_CODE (SET_SRC(exp)) == NOT	
-		    || GET_CODE (SET_SRC(exp)) == NEG	
-			|| GET_CODE (SET_SRC(exp)) == REG	
-		    || GET_CODE (SET_SRC(exp)) == MEM))	
-    { 
-	cc_status.flags = 0;					
-	cc_status.value1 = SET_SRC (exp);   			
-	cc_status.value2 = SET_DEST (exp);			
-	
-	if (cc_status.value1 && GET_CODE (cc_status.value1) == REG	
-	    && cc_status.value2					
-	    && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
-    	    cc_status.value2 = 0;					
-	if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM	
-	    && cc_status.value2					
-	    && GET_CODE (cc_status.value2) == MEM)			
-	    cc_status.value2 = 0; 					
-    }							
-    else if (GET_CODE (SET_SRC (exp)) == CALL)		
-    { 
-	CC_STATUS_INIT; 
-    }
-    else if (GET_CODE (SET_DEST (exp)) == REG)       		
-	/* what's this ? */					
-    { 
-	if ((cc_status.value1					
-	     && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)))
-	    cc_status.value1 = 0;				
-	if ((cc_status.value2					
-	     && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)))
-	    cc_status.value2 = 0;				
-    }							
-    else if (SET_DEST(exp) == pc_rtx)
-    { 
-	/* jump */
-    }
-    else /* if (GET_CODE (SET_DEST (exp)) == MEM)	*/	
-    {  
-	/* the last else is a bit paranoiac, but since nearly all instructions 
-	   play with condition codes, it's reasonable! */
-
-	CC_STATUS_INIT; /* paranoia*/ 
-    }		        
-}
-
-
-int simple_memory_operand(op, mode)
-  rtx op;
-  enum machine_mode mode;
-{
-    rtx addr, plus0, plus1;
-    int offset = 0;
-
-    /* Eliminate non-memory operations */
-    if (GET_CODE (op) != MEM)
-	return FALSE;
-
-#if 0
-    /* dword operations really put out 2 instructions, so eliminate them.  */
-    if (GET_MODE_SIZE (GET_MODE (op)) > (HAVE_64BIT_P () ? 8 : 4))
-	return FALSE;
-#endif
-
-    /* Decode the address now.  */
-
-  indirection:
-    
-    addr = XEXP (op, 0);
-
-    switch (GET_CODE (addr))
-    {
-      case REG:
-	/* (R0) - no extra cost */
-	return 1;
-	
-      case PRE_DEC:
-      case POST_INC:
-	/* -(R0), (R0)+ - cheap! */
-	return 0;
-	
-      case MEM:
-	/* cheap - is encoded in addressing mode info! 
-
-	   -- except for @(R0), which has to be @0(R0) !!! */
-
-	if (GET_CODE (XEXP (addr, 0)) == REG)
-	    return 0;
-	
-	op=addr;
-	goto indirection;
-	
-      case CONST_INT:
-      case LABEL_REF:	       
-      case CONST:
-      case SYMBOL_REF:
-	/* @#address - extra cost */
-	return 0;
-
-      case PLUS:
-	/* X(R0) - extra cost */
-	return 0;
-    }
-    
-    return FALSE;
-}
-
-
-/*
- * output a block move:
- *
- * operands[0]	... to
- * operands[1]  ... from
- * operands[2]  ... length
- * operands[3]  ... alignment
- * operands[4]  ... scratch register
- */
-
- 
-char *
-output_block_move(operands)
-  rtx *operands;
-{
-    static int count = 0;
-    char buf[200];
-    
-    if (GET_CODE(operands[2]) == CONST_INT
-	&& ! optimize_size)
-    {
-	if (INTVAL(operands[2]) < 16
-	    && INTVAL(operands[3]) == 1)
-	{
-	    register int i;
-	    
-	    for (i = 1; i <= INTVAL(operands[2]); i++)
-		output_asm_insn("movb (%1)+, (%0)+", operands);
-
-	    return "";
-	}
-	else if (INTVAL(operands[2]) < 32)
-	{
-	    register int i;
-	    
-	    for (i = 1; i <= INTVAL(operands[2])/2; i++)
-		output_asm_insn("mov (%1)+, (%0)+", operands);
-	    
-	    /* may I assume that moved quantity is 
-	       multiple of alignment ???
-
-	       I HOPE SO !
-	    */
-
-	    return "";
-	}
-	
-
-	/* can do other clever things, maybe... */
-    }
-
-    if (CONSTANT_P(operands[2]) )
-    {
-	/* just move count to scratch */
-	output_asm_insn("mov %2, %4", operands);
-    }
-    else
-    {
-	/* just clobber the register */
-	operands[4] = operands[2];
-    }
-    
-
-    /* switch over alignment */
-    switch (INTVAL(operands[3]))
-    {
-      case 1:
-	
-	/* 
-	  x:
-	  movb (%1)+, (%0)+
-	  
-	  if (TARGET_45)
-	     sob %4,x
-	  else
-	     dec %4
-	     bgt x
-
-	*/
-
-	sprintf(buf, "\nmovestrhi%d:", count);
-	output_asm_insn(buf, NULL);
-	
-	output_asm_insn("movb (%1)+, (%0)+", operands);
-	
-	if (TARGET_45)
-	{
-	    sprintf(buf, "sob %%4, movestrhi%d", count);
-	    output_asm_insn(buf, operands);
-	}
-	else
-	{
-	    output_asm_insn("dec %4", operands);
-	    
-	    sprintf(buf, "bgt movestrhi%d", count);
-	    output_asm_insn(buf, NULL);
-	}
-	
-	count ++;
-	break;
-	
-      case 2:
-	
-	/* 
-	   asr %4
-
-	   x:
-
-	   mov (%1)+, (%0)+
-
-	   if (TARGET_45)
-	     sob %4, x
-	   else
-	     dec %4
-	     bgt x
-	*/
-
-      generate_compact_code:
-
-	output_asm_insn("asr %4", operands);
-
-	sprintf(buf, "\nmovestrhi%d:", count);
-	output_asm_insn(buf, NULL);
-	
-	output_asm_insn("mov (%1)+, (%0)+", operands);
-	
-	if (TARGET_45)
-	{
-	    sprintf(buf, "sob %%4, movestrhi%d", count);
-	    output_asm_insn(buf, operands);
-	}
-	else
-	{
-	    output_asm_insn("dec %4", operands);
-	    
-	    sprintf(buf, "bgt movestrhi%d", count);
-	    output_asm_insn(buf, NULL);
-	}
-	
-	count ++;
-	break;
-
-      case 4:
-	
-	/*
-
-	   asr %4
-	   asr %4
-
-	   x:
-
-	   mov (%1)+, (%0)+
-	   mov (%1)+, (%0)+
-
-	   if (TARGET_45)
-	     sob %4, x
-	   else
-	     dec %4
-	     bgt x
-	*/
-
-	if (optimize_size)
-	    goto generate_compact_code;
-	
-	output_asm_insn("asr %4", operands);
-	output_asm_insn("asr %4", operands);
-
-	sprintf(buf, "\nmovestrhi%d:", count);
-	output_asm_insn(buf, NULL);
-	
-	output_asm_insn("mov (%1)+, (%0)+", operands);
-	output_asm_insn("mov (%1)+, (%0)+", operands);
-	
-	if (TARGET_45)
-	{
-	    sprintf(buf, "sob %%4, movestrhi%d", count);
-	    output_asm_insn(buf, operands);
-	}
-	else
-	{
-	    output_asm_insn("dec %4", operands);
-	    
-	    sprintf(buf, "bgt movestrhi%d", count);
-	    output_asm_insn(buf, NULL);
-	}
-	
-	count ++;
-	break;
-       
-      default:
-	
-	/*
-	   
-	   asr %4
-	   asr %4
-	   asr %4
-
-	   x:
-
-	   mov (%1)+, (%0)+
-	   mov (%1)+, (%0)+
-	   mov (%1)+, (%0)+
-	   mov (%1)+, (%0)+
-	   
-	   if (TARGET_45)
-	     sob %4, x
-	   else
-	     dec %4
-	     bgt x
-	*/
-
-
-	if (optimize_size)
-	    goto generate_compact_code;
-	
-	output_asm_insn("asr %4", operands);
-	output_asm_insn("asr %4", operands);
-	output_asm_insn("asr %4", operands);
-
-	sprintf(buf, "\nmovestrhi%d:", count);
-	output_asm_insn(buf, NULL);
-	
-	output_asm_insn("mov (%1)+, (%0)+", operands);
-	output_asm_insn("mov (%1)+, (%0)+", operands);
-	output_asm_insn("mov (%1)+, (%0)+", operands);
-	output_asm_insn("mov (%1)+, (%0)+", operands);
-	
-	if (TARGET_45)
-	{
-	    sprintf(buf, "sob %%4, movestrhi%d", count);
-	    output_asm_insn(buf, operands);
-	}
-	else
-	{
-	    output_asm_insn("dec %4", operands);
-	    
-	    sprintf(buf, "bgt movestrhi%d", count);
-	    output_asm_insn(buf, NULL);
-	}
-	
-	count ++;
-	break;
-	
-	;
-	
-    }
-    
-    return "";
-}
-
-/* for future use */
-int
-comparison_operator_index(op)
-  rtx op;
-{
-    switch (GET_CODE(op))
-    {
-      case NE:
-	return 0;
-	
-      case EQ:
-	return 1;
-	
-      case GE:
-	return 2;
-	
-      case GT:
-	return 3;
-	
-      case LE:
-	return 4;
-	
-      case LT:
-	return 5;
-	
-      case GEU:
-	return 6;
-	
-      case GTU:
-	return 7;
-
-      case LEU:
-	return 8;
-	
-      case LTU:
-	return 9;
-	
-      default:
-	return -1;
-    }
-}    
-	
-/* tests whether the rtx is a comparison operator */
-int
-comp_operator (op, mode)
-  rtx op;
-  enum machine_mode mode;
-{
-    return comparison_operator_index(op) >= 0;
-}
-
-    
-int
-legitimate_address_p (mode, address)
-  enum machine_mode mode;
-  rtx address;
-{
-/* #define REG_OK_STRICT */
-    GO_IF_LEGITIMATE_ADDRESS(mode, address, win);
-    
-    return 0;
-    
-  win:
-    return 1;
-
-/* #undef REG_OK_STRICT */
-}
diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h
deleted file mode 100755
index 7912bea..0000000
--- a/gcc/config/pdp11/pdp11.h
+++ /dev/null
@@ -1,1393 +0,0 @@
-/* Definitions of target machine for GNU compiler, for the pdp-11
-   Copyright (C) 1994, 1995, 1996, 1998 Free Software Foundation, Inc.
-   Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* declarations */
-char *output_jump();
-char *output_move_double();
-char *output_move_quad();
-char *output_block_move();
-
-/* check whether load_fpu_reg or not */
-#define LOAD_FPU_REG_P(x) ((x)>=8 && (x)<=11)
-#define NO_LOAD_FPU_REG_P(x) ((x)==12 || (x)==13)
-#define FPU_REG_P(x)	(LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x))
-#define CPU_REG_P(x)	((x)<8)
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dpdp11"
-
-/* Print subsidiary information on the compiler version in use.  */
-#define TARGET_VERSION fprintf (stderr, " (pdp11)");
-
-
-/* Generate DBX debugging information.  */
-
-/* #define DBX_DEBUGGING_INFO */
-
-/* Run-time compilation parameters selecting different hardware subsets.
-*/
-
-extern int target_flags;
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-{   { "fpu", 1},		\
-    { "soft-float", -1},       	\
-/* return float result in ac0 */\
-    { "ac0", 2},		\
-    { "no-ac0", -2},		\
-/* is 11/40 */			\
-    { "40", 4},			\
-    { "no-40", -4},		\
-/* is 11/45 */			\
-    { "45", 8},			\
-    { "no-45", -8},		\
-/* is 11/10 */			\
-    { "10", -12},		\
-/* use movstrhi for bcopy */	\
-    { "bcopy", 16},		\
-    { "bcopy-builtin", -16},	\
-/* use 32 bit for int */	\
-    { "int32", 32},		\
-    { "no-int16", 32},		\
-    { "int16", -32},		\
-    { "no-int32", -32},		\
-/* use 32 bit for float */	\
-    { "float32", 64},		\
-    { "no-float64", 64},	\
-    { "float64", -64},		\
-    { "no-float32", -64},	\
-/* allow abshi pattern? - can trigger "optimizations" which make code SLOW! */\
-    { "abshi", 128},		\
-    { "no-abshi", -128},	\
-/* is branching expensive - on a PDP, it's actually really cheap */ \
-/* this is just to play around and check what code gcc generates */ \
-    { "branch-expensive", 256}, \
-    { "branch-cheap", -256},	\
-/* split instruction and data memory? */ \
-    { "split", 1024 },		\
-    { "no-split", -1024 },	\
-/* default */			\
-    { "", TARGET_DEFAULT}	\
-}
-
-#define TARGET_DEFAULT (1 | 8 | 128)
-
-#define TARGET_FPU 		(target_flags & 1)
-#define TARGET_SOFT_FLOAT 	(!TARGET_FPU)
-
-#define TARGET_AC0		((target_flags & 2) && TARGET_FPU)
-#define TARGET_NO_AC0		(! TARGET_AC0)
-
-#define TARGET_45		(target_flags & 8)
-#define TARGET_40_PLUS		((target_flags & 4) || (target_flags & 8))
-#define TARGET_10		(! TARGET_40_PLUS)
-
-#define TARGET_BCOPY_BUILTIN	(! (target_flags & 16))
-
-#define TARGET_INT16		(! TARGET_INT32)
-#define TARGET_INT32		(target_flags & 32)
-
-#define TARGET_FLOAT32		(target_flags & 64)
-#define TARGET_FLOAT64		(! TARGET_FLOAT32)
-
-#define TARGET_ABSHI_BUILTIN	(target_flags & 128)
-
-#define TARGET_BRANCH_EXPENSIVE	(target_flags & 256)
-#define TARGET_BRANCH_CHEAP 	(!TARGET_BRANCH_EXPENSIVE)
-
-#define TARGET_SPLIT		(target_flags & 1024)
-#define TARGET_NOSPLIT		(! TARGET_SPLIT)
-
-
-/* TYPE SIZES */
-#define CHAR_TYPE_SIZE		8
-#define SHORT_TYPE_SIZE		16
-#define INT_TYPE_SIZE		(TARGET_INT16 ? 16 : 32)
-#define LONG_TYPE_SIZE		32
-#define LONG_LONG_TYPE_SIZE	64     
-
-/* if we set FLOAT_TYPE_SIZE to 32, we could have the benefit 
-   of saving core for huge arrays - the definitions are 
-   already in md - but floats can never reside in 
-   an FPU register - we keep the FPU in double float mode 
-   all the time !! */
-#define FLOAT_TYPE_SIZE		(TARGET_FLOAT32 ? 32 : 64)
-#define DOUBLE_TYPE_SIZE	64
-#define LONG_DOUBLE_TYPE_SIZE	64
-
-/* machine types from ansi */
-#define SIZE_TYPE "unsigned int" 	/* definition of size_t */
-
-/* is used in cexp.y - we don't have target_flags there, 
-   so just give default definition 
-
-   hope it does not come back to haunt us! */
-#define WCHAR_TYPE "int" 		/* or long int???? */
-#define WCHAR_TYPE_SIZE 16
-
-#define PTRDIFF_TYPE "int"
-
-/* target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is numbered.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-/*  This is a machine with 16-bit registers */
-#define BITS_PER_WORD 16
-
-/* Width of a word, in units (bytes). 
-
-   UNITS OR BYTES - seems like units */
-#define UNITS_PER_WORD 2
-
-/* Maximum sized of reasonable data type 
-   DImode or Dfmode ...*/
-#define MAX_FIXED_MODE_SIZE 64	
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 16
-
-/* Allocation boundary (in *bits*) for storing pointers in memory.  */
-#define POINTER_BOUNDARY 16
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 16
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 16
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 16
-
-/* Define this if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   we have 8 integer registers, plus 6 float 
-   (don't use scratch float !) */
-
-#define FIRST_PSEUDO_REGISTER 14
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   On the pdp, these are:
-   Reg 7	= pc;
-   reg 6	= sp;
-   reg 5	= fp;  not necessarily! 
-*/
-
-/* don't let them touch fp regs for the time being !*/
-
-#define FIXED_REGISTERS  \
-{0, 0, 0, 0, 0, 0, 1, 1, \
- 0, 0, 0, 0, 0, 0     }
-
-
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-
-/* don't know about fp */
-#define CALL_USED_REGISTERS  \
-{1, 1, 0, 0, 0, 0, 1, 1, \
- 0, 0, 0, 0, 0, 0 }
-
-
-/* Make sure everything's fine if we *don't* have an FPU.
-   This assumes that putting a register in fixed_regs will keep the
-   compiler's mitts completely off it.  We don't bother to zero it out
-   of register classes.  
-*/
-#define CONDITIONAL_REGISTER_USAGE \
-{ 						\
-  int i; 					\
-  HARD_REG_SET x; 				\
-  if (!TARGET_FPU)				\
-    { 						\
-      COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]); \
-      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
-       if (TEST_HARD_REG_BIT (x, i)) 		\
-	fixed_regs[i] = call_used_regs[i] = 1; 	\
-    } 						\
-						\
-  if (TARGET_AC0)				\
-      call_used_regs[8] = 1;			\
-}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-*/
-
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-((REGNO < 8)?								\
-    ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)	\
-    :1)
-    
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On the pdp, the cpu registers can hold any mode - check alignment
-
-   FPU can only hold DF - simplifies life!
-*/
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-((REGNO < 8)?						\
-  ((GET_MODE_BITSIZE(MODE) <= 16) 			\
-   || (GET_MODE_BITSIZE(MODE) == 32 && !(REGNO & 1)))	\
-  :(MODE) == DFmode)
-    
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) 0
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* the pdp11 pc overloaded on a register that the compiler knows about.  */
-#define PC_REGNUM  7
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 6
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 5
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.
-  */
-
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 5
-
-/* Register in which static-chain is passed to a function.  */
-/* ??? - i don't want to give up a reg for this! */
-#define STATIC_CHAIN_REGNUM 4
-
-/* Register in which address to store a structure value
-   is passed to a function.  
-   let's make it an invisible first argument!!! */
-
-#define STRUCT_VALUE 0
-
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-/* The pdp has a couple of classes:
-
-MUL_REGS are used for odd numbered regs, to use in 16 bit multiplication
-         (even numbered do 32 bit multiply)
-LMUL_REGS long multiply registers (even numbered regs )
-	  (don't need them, all 32 bit regs are even numbered!)
-GENERAL_REGS is all cpu
-LOAD_FPU_REGS is the first four cpu regs, they are easier to load
-NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them
-FPU_REGS is all fpu regs 
-*/
-
-enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS, FPU_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* have to allow this till cmpsi/tstsi are fixed in a better way !! */
-#define SMALL_REGISTER_CLASSES 1
-
-/* Since GENERAL_REGS is the same class as ALL_REGS,
-   don't give it a different class number; just make it an alias.  */
-
-/* #define GENERAL_REGS ALL_REGS */
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES {"NO_REGS", "MUL_REGS", "GENERAL_REGS", "LOAD_FPU_REGS", "NO_LOAD_FPU_REGS", "FPU_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS {0, 0x00aa, 0x00ff, 0x0f00, 0x3000, 0x3f00, 0x3fff}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) 		\
-((REGNO)>=8?((REGNO)<=11?LOAD_FPU_REGS:NO_LOAD_FPU_REGS):((REGNO&1)?MUL_REGS:GENERAL_REGS))
-
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C)	\
-((C) == 'f' ? FPU_REGS :			\
-  ((C) == 'd' ? MUL_REGS : 			\
-   ((C) == 'a' ? LOAD_FPU_REGS : NO_REGS)))
-    
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   I		bits 31-16 0000
-   J		bits 15-00 0000
-   K		completely random 32 bit
-   L,M,N	-1,1,0 respectively
-   O 		where doing shifts in sequence is faster than 
-                one big shift 
-*/
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'I' ? ((VALUE) & 0xffff0000) == 0		\
-   : (C) == 'J' ? ((VALUE) & 0x0000ffff) == 0  	       	\
-   : (C) == 'K' ? (((VALUE) & 0xffff0000) != 0		\
-		   && ((VALUE) & 0x0000ffff) != 0)	\
-   : (C) == 'L' ? ((VALUE) == 1)			\
-   : (C) == 'M' ? ((VALUE) == -1)			\
-   : (C) == 'N' ? ((VALUE) == 0)			\
-   : (C) == 'O' ? (abs(VALUE) >1 && abs(VALUE) <= 4)		\
-   : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'G' && XINT (VALUE, 0) == 0 && XINT (VALUE, 1) == 0)
-
-
-/* Letters in the range `Q' through `U' may be defined in a
-   machine-dependent fashion to stand for arbitrary operand types. 
-   The machine description macro `EXTRA_CONSTRAINT' is passed the
-   operand as its first argument and the constraint letter as its
-   second operand.
-
-   `Q'	is for memory references using take more than 1 instruction.
-   `R'	is for memory references which take 1 word for the instruction.  */
-
-#define EXTRA_CONSTRAINT(OP,CODE)					\
-  ((GET_CODE (OP) != MEM) ? 0						\
-   : !legitimate_address_p (GET_MODE (OP), XEXP (OP, 0)) ? 0		\
-   : ((CODE) == 'Q')	  ? !simple_memory_operand (OP, GET_MODE (OP))	\
-   : ((CODE) == 'R')	  ? simple_memory_operand (OP, GET_MODE (OP))	\
-   : 0)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  
-
-loading is easier into LOAD_FPU_REGS than FPU_REGS! */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) 	\
-(((CLASS) != FPU_REGS)?(CLASS):LOAD_FPU_REGS)
-
-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,x)	\
-(((CLASS) == NO_LOAD_FPU_REGS && !(REG_P(x) && LOAD_FPU_REG_P(REGNO(x))))?LOAD_FPU_REGS:NO_REGS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
-((CLASS == GENERAL_REGS || CLASS == MUL_REGS)?				\
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD):	\
-  1									\
-)
-
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.
-*/
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On the pdp11, the stack is on an even boundary */
-#define PUSH_ROUNDING(BYTES) ((BYTES + 1) & ~1)
-
-/* current_first_parm_offset stores the # of registers pushed on the 
-   stack */
-extern int current_first_parm_offset;
-
-/* Offset of first parameter from the argument pointer register value.  
-   For the pdp11, this is non-zero to account for the return address.
-	1 - return address
-	2 - frame pointer (always saved, even when not used!!!!)
-		-- chnage some day !!!:q!
-
-*/
-#define FIRST_PARM_OFFSET(FNDECL) 4
-
-/* Value is 1 if returning from a function call automatically
-   pops the arguments described by the number-of-args field in the call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-#define BASE_RETURN_VALUE_REG(MODE) \
- ((MODE) == DFmode ? 8 : 0) 
-
-/* On the pdp11 the value is found in R0 (or ac0??? 
-not without FPU!!!! ) */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE)))
-
-/* and the called function leaves it in the first register.
-   Difference only on machines with register windows.  */
-
-#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE)))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG(MODE))
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.
-   On the pdp, the first "output" reg is the only register thus used. 
-
-maybe ac0 ? - as option someday! */
-
-#define FUNCTION_VALUE_REGNO_P(N) (((N) == 0) || (TARGET_AC0 && (N) == 8))
-
-/* should probably return DImode and DFmode in memory,lest
-   we fill up all regs!
-
- have to, else we crash - exception: maybe return result in 
- ac0 if DFmode and FPU present - compatibility problem with
- libraries for non-floating point ...
-*/
-
-#define RETURN_IN_MEMORY(TYPE)	\
-  (TYPE_MODE(TYPE) == DImode || (TYPE_MODE(TYPE) == DFmode && ! TARGET_AC0))
-
-
-/* 1 if N is a possible register number for function argument passing.
-   - not used on pdp */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-*/
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   ...., the offset normally starts at 0, but starts at 1 word
-   when the function gets a structure-value-address as an
-   invisible first argument.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  
-
-*/
-
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM) += ((MODE) != BLKmode			\
-	    ? (GET_MODE_SIZE (MODE))		\
-	    : (int_size_in_bytes (TYPE))))	
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)  0
-
-/* Define where a function finds its arguments.
-   This would be different from FUNCTION_ARG if we had register windows.  */
-/*
-#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED)	\
-  FUNCTION_ARG (CUM, MODE, TYPE, NAMED)
-*/
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
-/* This macro generates the assembly code for function entry. */
-#define FUNCTION_PROLOGUE(FILE, SIZE) \
-    output_function_prologue(FILE, SIZE);
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   abort ();
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-extern int may_call_alloca;
-extern int current_function_pretend_args_size;
-
-#define EXIT_IGNORE_STACK	1
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-*/
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-    output_function_epilogue(FILE, SIZE);
-  
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR)	\
-{								\
-  int offset, regno;		      				\
-  offset = get_frame_size();					\
-  for (regno = 0; regno < 8; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      offset += 2;						\
-  for (regno = 8; regno < 14; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      offset += 8;						\
-  /* offset -= 2;   no fp on stack frame */			\
-  (DEPTH_VAR) = offset;						\
-}   
-    
-
-/* Addressing modes, and classification of registers for them.  */
-
-#define HAVE_POST_INCREMENT 1
-/* #define HAVE_POST_DECREMENT 0 */
-
-#define HAVE_PRE_DECREMENT 1
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-  ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
-#define REGNO_OK_FOR_BASE_P(REGNO)  \
-  ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
-
-/* Now macros that check whether X is a register and also,
-   strictly, whether it is in a specified class.
-*/
-
-
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)  CONSTANT_P (X)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) (1)
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) (1)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) (1)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-*/
-
-#define GO_IF_LEGITIMATE_ADDRESS(mode, operand, ADDR) \
-{						      \
-    rtx xfoob;								\
-									\
-    /* accept (R0) */							\
-    if (GET_CODE (operand) == REG					\
-	&& REG_OK_FOR_BASE_P(operand))					\
-      goto ADDR;							\
-									\
-    /* accept @#address */						\
-    if (CONSTANT_ADDRESS_P (operand))					\
-      goto ADDR;							\
-    									\
-    /* accept X(R0) */							\
-    if (GET_CODE (operand) == PLUS       				\
-	&& GET_CODE (XEXP (operand, 0)) == REG				\
-	&& REG_OK_FOR_BASE_P (XEXP (operand, 0))			\
-	&& CONSTANT_ADDRESS_P (XEXP (operand, 1)))			\
-      goto ADDR;							\
-    									\
-    /* accept -(R0) */							\
-    if (GET_CODE (operand) == PRE_DEC					\
-	&& GET_CODE (XEXP (operand, 0)) == REG				\
-	&& REG_OK_FOR_BASE_P (XEXP (operand, 0)))			\
-      goto ADDR;							\
-									\
-    /* accept (R0)+ */							\
-    if (GET_CODE (operand) == POST_INC					\
-	&& GET_CODE (XEXP (operand, 0)) == REG				\
-	&& REG_OK_FOR_BASE_P (XEXP (operand, 0)))			\
-      goto ADDR;							\
-    									\
-    /* handle another level of indirection ! */				\
-    if (GET_CODE(operand) != MEM)					\
-      goto fail;							\
-									\
-    xfoob = XEXP (operand, 0);						\
-									\
-    /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently */    \
-    /* also forbidden for float, because we have to handle this */  	\
-    /* in output_move_double and/or output_move_quad() - we could */   	\
-    /* do it, but currently it's not worth it!!! */			\
-    /* now that DFmode cannot go into CPU register file, */		\
-    /* maybe I should allow float ... */				\
-    /*  but then I have to handle memory-to-memory moves in movdf ?? */ \
-									\
-    if (GET_MODE_BITSIZE(mode) > 16)					\
-      goto fail;							\
-									\
-    /* accept @(R0) - which is @0(R0) */				\
-    if (GET_CODE (xfoob) == REG						\
-	&& REG_OK_FOR_BASE_P(xfoob))					\
-      goto ADDR;							\
-									\
-    /* accept @address */						\
-    if (CONSTANT_ADDRESS_P (xfoob))					\
-      goto ADDR;							\
-    									\
-    /* accept @X(R0) */							\
-    if (GET_CODE (xfoob) == PLUS       					\
-	&& GET_CODE (XEXP (xfoob, 0)) == REG				\
-	&& REG_OK_FOR_BASE_P (XEXP (xfoob, 0))				\
-	&& CONSTANT_ADDRESS_P (XEXP (xfoob, 1)))			\
-      goto ADDR;							\
-									\
-    /* accept @-(R0) */							\
-    if (GET_CODE (xfoob) == PRE_DEC					\
-	&& GET_CODE (XEXP (xfoob, 0)) == REG				\
-	&& REG_OK_FOR_BASE_P (XEXP (xfoob, 0)))				\
-      goto ADDR;							\
-									\
-    /* accept @(R0)+ */							\
-    if (GET_CODE (xfoob) == POST_INC					\
-	&& GET_CODE (XEXP (xfoob, 0)) == REG				\
-	&& REG_OK_FOR_BASE_P (XEXP (xfoob, 0)))				\
-      goto ADDR;							\
-									\
-  /* anything else is invalid */					\
-  fail: ;								\
-}
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)	{}
-
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the pdp this is for predec/postinc */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
- { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC)	\
-     goto LABEL; 							\
- }
-
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE HImode
-
-/* Define this if a raw index is all that is needed for a
-   `tablejump' insn.  */
-#define CASE_TAKES_INDEX_RAW
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  
-*/
-
-#define MOVE_MAX 2
-
-/* Zero extension is faster if the target is known to be zero */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Nonzero if access to memory by byte is slow and undesirable. -
-*/
-#define SLOW_BYTE_ACCESS 0
-
-/* Do not break .stabs pseudos into continuations.  */
-#define DBX_CONTIN_LENGTH 0
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-
-/* Add any extra modes needed to represent the condition code.
-
-   CCFPmode is used for FPU, but should we use a separate reg? */
-#define EXTRA_CC_MODES CCFPmode
-
-/* the name for the mode above */
-#define EXTRA_CC_NAMES "CCFPmode"
-
-/* Give a comparison code (EQ, NE etc) and the first operand of a COMPARE,
-   return the mode to be used for the comparison.  For floating-point, CCFPmode
-   should be used. */
-
-#define SELECT_CC_MODE(OP,X,Y)	\
-(GET_MODE_CLASS(GET_MODE(X)) == MODE_FLOAT? CCFPmode : CCmode)
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-/* #define STORE_FLAG_VALUE 1 */
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode HImode
-
-/* A function address in a call instruction
-   is a word address (for indexing purposes)
-   so give the MEM rtx a word's mode.  */
-#define FUNCTION_MODE HImode
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.  */
-/* #define NO_FUNCTION_CSE */
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch. 
-
-   -1, 0, 1 are cheaper for add, sub ... 
-*/
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    if (INTVAL(RTX) == 0					\
-	|| INTVAL(RTX) == -1					\
-	|| INTVAL(RTX) == 1)					\
-      return 0;							\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    /* twice as expensive as REG */				\
-    return 2;							\
-  case CONST_DOUBLE:						\
-    /* twice (or 4 times) as expensive as 16 bit */		\
-    return 4;
-
-/* cost of moving one register class to another */
-#define REGISTER_MOVE_COST(CLASS1, CLASS2) register_move_cost(CLASS1, CLASS2)
-
-/* Tell emit-rtl.c how to initialize special values on a per-function base.  */
-extern int optimize;
-extern struct rtx_def *cc0_reg_rtx;
-
-#define CC_STATUS_MDEP rtx
-
-#define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  */
-
-#define CC_IN_FPU 04000 
-
-/* Do UPDATE_CC if EXP is a set, used in
-   NOTICE_UPDATE_CC 
-
-   floats only do compare correctly, else nullify ...
-
-   get cc0 out soon ...
-*/
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-{ if (GET_CODE (EXP) == SET)					\
-    {								\
-      notice_update_cc_on_set(EXP, INSN);			\
-    }								\
-  else if (GET_CODE (EXP) == PARALLEL				\
-	   && GET_CODE (XVECEXP (EXP, 0, 0)) == SET)		\
-    {								\
-      notice_update_cc_on_set(XVECEXP (EXP, 0, 0), INSN);	\
-    }								\
-  else if (GET_CODE (EXP) == CALL)				\
-    { /* all bets are off */ CC_STATUS_INIT; }			\
-  if (cc_status.value1 && GET_CODE (cc_status.value1) == REG	\
-      && cc_status.value2					\
-      && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))	\
-    printf ("here!\n", cc_status.value2 = 0);			\
-}
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#if 0
-#define ASM_FILE_START(FILE) \
-(								\
-fprintf (FILE, "\t.data\n"),					\
-fprintf (FILE, "$help$: . = .+8 ; space for tmp moves!\n")	\
-/* do we need reg def's R0 = %0 etc ??? */			\
-)
-#else
-#define ASM_FILE_START(FILE)	(0)
-#endif
-
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP "\t.text\n"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP "\t.data\n"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "fp", "sp", "pc",     \
- "ac0", "ac1", "ac2", "ac3", "ac4", "ac5" }
-
-/* How to renumber registers for dbx and gdb.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs("\n", FILE); } while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s_%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s_%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-  fprintf (FILE, "\tdouble %.20e\n", (VALUE))
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-  fprintf (FILE, "\tfloat %.12e\n", (VALUE))
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `short' and `char' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, " /*short*/\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, " /* char */\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.-
-
-   do we really NEED it ? let's output it with a comment and grep the 
-   assembly source ;-)
-*/
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-#define ASM_OUTPUT_ASCII(FILE, P, SIZE)  \
-  output_ascii (FILE, P, SIZE)
-
-#define ASM_OUTPUT_ADDR_VEC_PROLOGUE(FILE, MODE, LEN)	\
-  fprintf (FILE, "\t/* HELP! */\n");
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.word L_%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.
-   Don't define this if it is not supported. */
-
-/* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes. 
-
-   who needs this????
-*/
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", 1<<(LOG))
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.=.+ %d\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fprintf ((FILE), ".globl "),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), "\n"),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ": .=.+ %d\n", (ROUNDED))		\
-)
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( assemble_name ((FILE), (NAME)),				\
-  fprintf ((FILE), ":\t.=.+ %d\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.
-
-*/
-
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ if (CODE == '#') fprintf (FILE, "#");					\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != SImode)	\
-    { union { double d; int i[2]; } u;					\
-      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
-      fprintf (FILE, "#%.20e", u.d); }					\
-  else { putc ('$', FILE); output_addr_const (FILE, X); }}
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
- print_operand_address (FILE, ADDR)
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)			\
-(							\
-  fprintf (FILE, "\tmov %s, -(sp)\n", reg_names[REGNO])	\
-)
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)                 		\
-(                                                       	\
-  fprintf (FILE, "\tmov (sp)+, %s\n", reg_names[REGNO])     	\
-)
-
-
-#define ASM_IDENTIFY_GCC(FILE)			\
-    fprintf(FILE, "gcc_compiled:\n")
-
-#define ASM_OUTPUT_DOUBLE_INT(a,b)	fprintf(a,"%d", b)
-
-/* trampoline - how should i do it in separate i+d ? 
-   have some allocate_trampoline magic??? 
-
-   the following should work for shared I/D: */
-
-/* lets see whether this works as trampoline:
-MV	#STATIC, $4	0x940Y	0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM
-JMP	FUNCTION	0x0058  0x0000 <- FUNCTION
-*/
-
-#define TRAMPOLINE_TEMPLATE(FILE)	\
-{					\
-  if (TARGET_SPLIT)			\
-    abort();				\
-					\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0x9400+STATIC_CHAIN_REGNUM)); \
-  ASM_OUTPUT_INT (FILE, const0_rtx);				\
-  ASM_OUTPUT_INT (FILE, GEN_INT(0x0058));			\
-  ASM_OUTPUT_INT (FILE, const0_rtx);				\
-}
-
-#define TRAMPOLINE_SIZE 8
-#define TRAMPOLINE_ALIGN 16
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP,FNADDR,CXT)	\
-{					\
-  if (TARGET_SPLIT)			\
-    abort();				\
-					\
-  emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 2)), CXT); \
-  emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 6)), FNADDR); \
-}
-
-
-/* Some machines may desire to change what optimizations are
-   performed for various optimization levels.   This macro, if
-   defined, is executed once just after the optimization level is
-   determined and before the remainder of the command options have
-   been parsed.  Values set in this macro are used as the default
-   values for the other command line options.
-
-   LEVEL is the optimization level specified; 2 if -O2 is
-   specified, 1 if -O is specified, and 0 if neither is specified.  */
-
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)				\
-{									\
-  if (LEVEL >= 3)							\
-    {									\
-      if (! SIZE)							\
-        flag_inline_functions		= 1;				\
-      flag_omit_frame_pointer		= 1;				\
-      /* flag_unroll_loops			= 1; */			\
-    }									\
-}
-
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE. 
-
-   we don't say how expensive SImode is - pretty expensive!!!
-
-   there is something wrong in MULT because MULT is not 
-   as cheap as total = 2 even if we can shift!
-
-   if optimizing for size make mult etc cheap, but not 1, so when 
-   in doubt the faster insn is chosen.
-*/
-
-#define RTX_COSTS(X,CODE,OUTER_CODE) \
-  case MULT:								\
-    if (optimize_size)							\
-      total = COSTS_N_INSNS(2);						\
-    else								\
-      total = COSTS_N_INSNS (11);					\
-    break;								\
-  case DIV:								\
-    if (optimize_size)							\
-      total = COSTS_N_INSNS(2);						\
-    else								\
-      total = COSTS_N_INSNS (25);					\
-    break;								\
-  case MOD:								\
-    if (optimize_size)							\
-      total = COSTS_N_INSNS(2);						\
-    else								\
-      total = COSTS_N_INSNS (26);					\
-    break;								\
-  case ABS:								\
-    /* equivalent to length, so same for optimize_size */		\
-    total = COSTS_N_INSNS (3);						\
-    break;								\
-  case ZERO_EXTEND:							\
-    /* only used for: qi->hi */						\
-    total = COSTS_N_INSNS(1);						\
-    break;								\
-  case SIGN_EXTEND:							\
-    if (GET_MODE(X) == HImode)						\
-      	total = COSTS_N_INSNS(1);					\
-    else if (GET_MODE(X) == SImode)					\
-	total = COSTS_N_INSNS(6);					\
-    else								\
-	total = COSTS_N_INSNS(2);					\
-    break;								\
-  /* case LSHIFT: */		       					\
-  case ASHIFT:								\
-  case LSHIFTRT:							\
-  case ASHIFTRT:							\
-    if (optimize_size)							\
-      total = COSTS_N_INSNS(1);						\
-    else if (GET_MODE(X) ==  QImode)					\
-    {									\
-      if (GET_CODE(XEXP (X,1)) != CONST_INT)				\
-   	total = COSTS_N_INSNS(8); /* worst case */ 			\
-      else                                                              \
-	total = COSTS_N_INSNS(INTVAL(XEXP (X,1)));			\
-    }									\
-    else if (GET_MODE(X) == HImode)					\
-    {									\
-      if (GET_CODE(XEXP (X,1)) == CONST_INT)				\
-      {									\
-	if (abs (INTVAL (XEXP (X, 1))) == 1)				\
-          total = COSTS_N_INSNS(1);					\
-        else								\
-	  total = COSTS_N_INSNS(2.5 + 0.5 *INTVAL(XEXP(X,1)));		\
-      }									\
-      else /* worst case */						\
-        total = COSTS_N_INSNS (10);					\
-    }									\
-    else if (GET_MODE(X) == SImode)					\
-    {									\
-      if (GET_CODE(XEXP (X,1)) == CONST_INT)				\
-	  total = COSTS_N_INSNS(2.5 + 0.5 *INTVAL(XEXP(X,1)));		\
-      else /* worst case */						\
-        total = COSTS_N_INSNS(18);					\
-    }									\
-    break;
-
-
-/* there is no point in avoiding branches on a pdp, 
-   since branches are really cheap - I just want to find out
-   how much difference the BRANCH_COST macro makes in code */
-#define BRANCH_COST (TARGET_BRANCH_CHEAP ? 0 : 1)
-
-
-#define COMPARE_FLAG_MODE HImode
-
diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md
deleted file mode 100755
index 621b874..0000000
--- a/gcc/config/pdp11/pdp11.md
+++ /dev/null
@@ -1,1824 +0,0 @@
-;;- Machine description for the pdp11 for GNU C compiler
-;; Copyright (C) 1994, 1995, 1997 Free Software Foundation, Inc.
-;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 1, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;; HI is 16 bit
-;; QI is 8 bit 
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-;;- Operand classes for the register allocator:
-
-;; Compare instructions.
-
-;; currently we only support df floats, which saves us quite some
-;; hassle switching the FP mode! 
-;; we assume that CPU is always in long float mode, and 
-;; 16 bit integer mode - currently, the prologue for main does this,
-;; but maybe we should just set up a NEW crt0 properly, 
-;; -- and what about signal handling code?
-;; (we don't even let sf floats in the register file, so
-;; we only should have to worry about truncating and widening 
-;; when going to memory)
-
-;; abort() call by g++ - must define libfunc for cmp_optab
-;; and ucmp_optab for mode SImode, because we don't have that!!!
-;; - yet since no libfunc is there, we abort ()
-
-;; The only thing that remains to be done then is output 
-;; the floats in a way the assembler can handle it (and 
-;; if you're really into it, use a PDP11 float emulation
-;; library to do floating point constant folding - but 
-;; I guess you'll get reasonable results even when not
-;; doing this)
-;; the last thing to do is fix the UPDATE_CC macro to check
-;; for floating point condition codes, and set cc_status
-;; properly, also setting the CC_IN_FCCR flag. 
-
-;; define attributes
-;; currently type is only fpu or arith or unknown, maybe branch later ?
-;; default is arith
-(define_attr "type" "unknown,arith,fp" (const_string "arith"))
-
-;; length default is 1 word each
-(define_attr "length" "" (const_int 1))
-
-;; a user's asm statement
-(define_asm_attributes
-  [(set_attr "type" "unknown")
-; all bets are off how long it is - make it 256, forces long jumps 
-; whenever jumping around it !!!
-   (set_attr "length" "256")])
-
-;; define function units
-
-;; arithmetic - values here immediately when next insn issued
-;; or does it mean the number of cycles after this insn was issued?
-;; how do I say that fpu insns use cpu also? (pre-interaction phase)
-
-;(define_function_unit "cpu" 1 1 (eq_attr "type" "arith") 0 0)
-;(define_function_unit "fpu" 1 1 (eq_attr "type" "fp") 0 0)
-
-;; compare
-(define_insn "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "general_operand" "fR,Q,F")
-		 (match_operand:DF 1 "register_operand" "a,a,a")))]
-  "TARGET_FPU"
-  "*
-{
-  cc_status.flags = CC_IN_FPU;
-  return \"cmpd %0, %1\;cfcc\";
-}"
-  [(set_attr "length" "2,3,6")])
-
-;; a bit of brain damage, maybe inline later - 
-;; problem is - gcc seems to NEED SImode because 
-;; of the cmp weirdness - maybe change gcc to handle this?
-
-(define_expand "cmpsi"
-  [(set (reg:SI 0)
-	(match_operand:SI 0 "general_operand" "g"))
-   (set (reg:SI 2)
-	(match_operand:SI 1 "general_operand" "g"))
-   (parallel [(set (cc0)
-		   (compare (reg:SI 0)
-			    (reg:SI 2)))
-	      (clobber (reg:SI 0))])]
-  "0" ;; disable for test
-  "")
-
-;; check for next insn for branch code - does this still
-;; work in gcc 2.* ?
-
-(define_insn ""
-  [(set (cc0)
-	(compare (reg:SI 0)
-		 (reg:SI 2)))
-   (clobber (reg:SI 0))]
-  ""
-  "*
-{
-  rtx br_insn = NEXT_INSN (insn);
-  RTX_CODE br_code;
-
-  if (GET_CODE (br_insn) != JUMP_INSN)
-    abort();
-  br_code =  GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));
-  
-  switch(br_code)
-  {
-    case GEU:
-    case LTU:
-    case GTU:
-    case LEU:
-      
-      return \"jsr pc, ___ucmpsi\;cmp $1,r0\";
-
-    case GE:
-    case LT:
-    case GT:
-    case LE:
-    case EQ:
-    case NE:
-
-      return \"jsr pc, ___cmpsi\;tst r0\";
-
-    default:
-
-      abort();
-  }
-}"
-  [(set_attr "length" "4")])
-
-
-(define_insn "cmphi"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "general_operand" "rR,rR,Qi,Qi")
-		 (match_operand:HI 1 "general_operand" "rR,Qi,rR,Qi")))]
-  ""
-  "cmp %0,%1"
-  [(set_attr "length" "1,2,2,3")])
-
-(define_insn "cmpqi"
-  [(set (cc0)
-	(compare (match_operand:QI 0 "general_operand" "rR,rR,Qi,Qi")
-		 (match_operand:QI 1 "general_operand" "rR,Qi,rR,Qi")))]
-  ""
-  "cmpb %0,%1"
-  [(set_attr "length" "1,2,2,3")])
-			   
-
-;; We have to have this because cse can optimize the previous pattern
-;; into this one.
-
-(define_insn "tstdf"
-  [(set (cc0)
-	(match_operand:DF 0 "general_operand" "fR,Q"))]
-  "TARGET_FPU"
-  "*
-{
-  cc_status.flags = CC_IN_FPU;
-  return \"tstd %0\;cfcc\";
-}"
-  [(set_attr "length" "2,3")])
-
-
-(define_expand "tstsi"
-  [(set (reg:SI 0)
-	(match_operand:SI 0 "general_operand" "g"))
-   (parallel [(set (cc0)
-		   (reg:SI 0))
-	      (clobber (reg:SI 0))])]
-  "0" ;; disable for test
-  "")
-
-(define_insn ""
-  [(set (cc0)
-	(reg:SI 0))
-   (clobber (reg:SI 0))]
-  ""
-  "jsr pc, ___tstsi\;tst r0"
-  [(set_attr "length" "3")])
-
-
-(define_insn "tsthi"
-  [(set (cc0)
-	(match_operand:HI 0 "general_operand" "rR,Q"))]
-  ""
-  "tst %0"
-  [(set_attr "length" "1,2")])
-
-(define_insn "tstqi"
-  [(set (cc0)
-	(match_operand:QI 0 "general_operand" "rR,Q"))]
-  ""
-  "tstb %0"
-  [(set_attr "length" "1,2")])
-
-;; sob instruction - we need an assembler which can make this instruction
-;; valid under _all_ circumstances!
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (plus:HI (match_operand:HI 0 "register_operand" "r")
-		      (const_int -1))
-	     (const_int 0))
-	 (label_ref (match_operand 1 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:HI (match_dup 0)
-		 (const_int -1)))]
-  "TARGET_40_PLUS"
-  "*
-{
- static int labelcount = 0;
- static char buf[1000];
-
- if (get_attr_length (insn) == 1)
-    return \"sob %0, %l1\";
-
- /* emulate sob */
- output_asm_insn (\"dec %0\", operands);
- 
- sprintf (buf, \"bge LONG_SOB%d\", labelcount);
- output_asm_insn (buf, NULL);
-
- output_asm_insn (\"jmp %l1\", operands);
- 
- sprintf (buf, \"LONG_SOB%d:\", labelcount++);
- output_asm_insn (buf, NULL);
-
- return \"\";
-}"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						       (pc))
-						(const_int -256))
-					   (ge (minus (match_dup 0)
-						       (pc))
-						(const_int 0)))
-				      (const_int 4)
-				      (const_int 1)))])
-
-;; These control RTL generation for conditional jump insns
-;; and match them for register allocation.
-
-;; problem with too short jump distance! we need an assembler which can 
-;; make this valid for all jump distances!
-;; e.g. gas!
-
-;; these must be changed to check for CC_IN_FCCR if float is to be 
-;; enabled
-
-(define_insn "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_jump(\"beq\", \"bne\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-
-(define_insn "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_jump(\"bne\", \"beq\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_jump(\"bgt\", \"ble\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_jump(\"bhi\", \"blos\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_jump(\"blt\", \"bge\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-
-(define_insn "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_jump(\"blo\", \"bhis\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_jump(\"bge\", \"blt\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_jump(\"bhis\", \"blo\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_jump(\"ble\", \"bgt\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_jump(\"blos\", \"bhi\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-
-;; These match inverted jump insns for register allocation.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_jump(\"bne\", \"beq\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_jump(\"beq\", \"bne\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_jump(\"ble\", \"bgt\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_jump(\"blos\", \"bhi\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_jump(\"bge\", \"blt\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_jump(\"bhis\", \"blo\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""  
-  "* return output_jump(\"blt\", \"bge\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_jump(\"blo\", \"bhis\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_jump(\"bgt\", \"ble\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_jump(\"bhi\", \"blos\", get_attr_length(insn));"
-  [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
-						      (pc))
-					       (const_int -128))
-					   (ge (minus (match_dup 0)
-						      (pc))
-					       (const_int 128)))
-				      (const_int 3)
-				      (const_int 1)))])
-
-;; Move instructions
-
-(define_insn "movdi"
-  [(set (match_operand:DI 0 "general_operand" "=g")
-	(match_operand:DI 1 "general_operand" "g"))]
-  ""
-  "* return output_move_quad (operands);"
-;; what's the mose expensive code - say twice movsi = 16
-  [(set_attr "length" "16")])
-
-(define_insn "movsi"
-  [(set (match_operand:SI 0 "general_operand" "=r,r,r,rm,m")
-	(match_operand:SI 1 "general_operand" "rN,IJ,K,m,r"))]
-  ""
-  "* return output_move_double (operands);"
-;; what's the most expensive code ? - I think 8!
-;; we could split it up and make several sub-cases...
-  [(set_attr "length" "2,3,4,8,8")])
-
-(define_insn "movhi"
-  [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
-	(match_operand:HI 1 "general_operand" "rRN,Qi,rRN,Qi"))]
-  ""
-  "*
-{
-  if (operands[1] == const0_rtx)
-    return \"clr %0\";
-
-  return \"mov %1, %0\";
-}"
-  [(set_attr "length" "1,2,2,3")])
-
-(define_insn "movqi"
-  [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
-	(match_operand:QI 1 "general_operand" "rRN,Qi,rRN,Qi"))]
-  ""
-  "*
-{
-  if (operands[1] == const0_rtx)
-    return \"clrb %0\";
-
-  return \"movb %1, %0\";
-}"
-  [(set_attr "length" "1,2,2,3")])
-
-;; do we have to supply all these moves? e.g. to 
-;; NO_LOAD_FPU_REGs ? 
-(define_insn "movdf"
-  [(set (match_operand:DF 0 "general_operand" "=f,R,f,Q,f,m")
-        (match_operand:DF 1 "general_operand" "fR,f,Q,f,F,m"))]
-  ""
-  "* return output_move_quad (operands);"
-;; just a guess..
-  [(set_attr "length" "1,1,2,2,5,16")])
-
-(define_insn "movsf"
-  [(set (match_operand:SF 0 "general_operand" "=g,r,g")
-        (match_operand:SF 1 "general_operand" "r,rmF,g"))]
-  "TARGET_FPU"
-  "* return output_move_double (operands);"
-  [(set_attr "length" "8,8,8")])
-
-;; maybe fiddle a bit with move_ratio, then 
-;; let constraints only accept a register ...
-
-(define_expand "movstrhi"
-  [(parallel [(set (match_operand:BLK 0 "general_operand" "=g,g")
-		   (match_operand:BLK 1 "general_operand" "g,g"))
-	      (use (match_operand:HI 2 "arith_operand" "n,&mr"))
-	      (use (match_operand:HI 3 "immediate_operand" "i,i"))
-	      (clobber (match_scratch:HI 4 "=&r,X"))
-	      (clobber (match_dup 5))
-	      (clobber (match_dup 6))
-	      (clobber (match_dup 2))])]
-  "(TARGET_BCOPY_BUILTIN)"
-  "
-{
-  operands[0]
-    = change_address (operands[0], VOIDmode,
-		      copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
-  operands[1]
-    = change_address (operands[1], VOIDmode,
-		      copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
-
-  operands[5] = XEXP (operands[0], 0);
-  operands[6] = XEXP (operands[1], 0);
-}")
-
-
-(define_insn "" ; "movstrhi"
-  [(set (mem:BLK (match_operand:HI 0 "general_operand" "=r,r"))
-	(mem:BLK (match_operand:HI 1 "general_operand" "r,r")))
-   (use (match_operand:HI 2 "arith_operand" "n,&r"))
-   (use (match_operand:HI 3 "immediate_operand" "i,i"))
-   (clobber (match_scratch:HI 4 "=&r,X"))
-   (clobber (match_dup 0))
-   (clobber (match_dup 1))
-   (clobber (match_dup 2))]
-  "(TARGET_BCOPY_BUILTIN)"
-  "* return output_block_move (operands);"
-;;; just a guess
-  [(set_attr "length" "40")])
-   
-
-
-;;- truncation instructions
-
-(define_insn  "truncdfsf2"
-  [(set (match_operand:SF 0 "general_operand" "=r,R,Q")
-	(float_truncate:SF (match_operand:DF 1 "register_operand" "a,a,a")))]
-  "TARGET_FPU"
-  "* if (which_alternative ==0)
-     {
-       output_asm_insn(\"stcdf %1, -(sp)\", operands);
-       output_asm_insn(\"mov (sp)+, %0\", operands);
-       operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
-       output_asm_insn(\"mov (sp)+, %0\", operands);
-       return \"\";
-     }
-     else if (which_alternative == 1)
-       return \"stcdf %1, %0\";
-     else 
-       return \"stcdf %1, %0\";
-  "
-  [(set_attr "length" "3,1,2")])
-
-
-(define_expand "truncsihi2"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(subreg:HI 
-	  (match_operand:SI 1 "general_operand" "or")
-          0))]
-  ""
-  "")
-
-
-;;- zero extension instructions
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=r")
-	(zero_extend:HI (match_operand:QI 1 "general_operand" "0")))]
-  ""
-  "bic $(256*255), %0"
-  [(set_attr "length" "2")])
-			 
-(define_expand "zero_extendhisi2"
-  [(set (subreg:HI 
-          (match_dup 0)
-          1)
-        (match_operand:HI 1 "register_operand" "r"))
-   (set (subreg:HI 
-          (match_operand:SI 0 "register_operand" "=r")
-          0)
-        (const_int 0))]
-  ""
-  "/* operands[1] = make_safe_from (operands[1], operands[0]); */")
-
-
-;;- sign extension instructions
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=a,a,a")
-	(float_extend:DF (match_operand:SF 1 "general_operand" "r,R,Q")))]
-  "TARGET_FPU"
-  "@
-   mov %1, -(sp)\;ldcfd (sp)+,%0
-   ldcfd %1, %0
-   ldcfd %1, %0"
-  [(set_attr "length" "2,1,2")])
-
-;; does movb sign extend in register-to-register move?
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(sign_extend:HI (match_operand:QI 1 "general_operand" "rR,Q")))]
-  ""
-  "movb %1, %0"
-  [(set_attr "length" "1,2")])
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(sign_extend:SI (match_operand:QI 1 "general_operand" "rR,Q")))]
-  "TARGET_40_PLUS"
-  "*
-{
-  rtx latehalf[2];
-
-  /* make register pair available */
-  latehalf[0] = operands[0];
-  operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
-    
-  output_asm_insn(\"movb %1, %0\", operands);
-  output_asm_insn(\"sxt %0\", latehalf);
-    
-  return \"\";
-}"
-  [(set_attr "length" "2,3")])
-
-;; maybe we have to use define_expand to say that we have the instruction,
-;; unconditionally, and then match dependent on CPU type:
-
-(define_expand "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "")
-  
-(define_insn "" ; "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=o,<,r")
-	(sign_extend:SI (match_operand:HI 1 "general_operand" "g,g,g")))]
-  "TARGET_40_PLUS"
-  "*
-{
-  rtx latehalf[2];
-
-  /* we don't want to mess with auto increment */
-  
-  switch(which_alternative)
-  {
-    case 0:
-
-      latehalf[0] = operands[0];
-      operands[0] = adj_offsettable_operand(operands[0], 2);
-  
-      output_asm_insn(\"mov %1, %0\", operands);
-      output_asm_insn(\"sxt %0\", latehalf);
-
-      return \"\";
-
-    case 1:
-
-      /* - auto-decrement - right direction ;-) */
-      output_asm_insn(\"mov %1, %0\", operands);
-      output_asm_insn(\"sxt %0\", operands);
-
-      return \"\";
-
-    case 2:
-
-      /* make register pair available */
-      latehalf[0] = operands[0];
-      operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
-
-      output_asm_insn(\"mov %1, %0\", operands);
-      output_asm_insn(\"sxt %0\", latehalf);
-
-      return \"\";
-
-    default:
-
-      abort();
-  }
-}"
-  [(set_attr "length" "5,3,3")])
-
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI (match_operand:HI 1 "general_operand" "0")))]
-  "(! TARGET_40_PLUS)"
-  "*
-{
-  static count = 0;
-  char buf[100];
-  rtx lateoperands[2];
-
-  lateoperands[0] = operands[0];
-  operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
-
-  output_asm_insn(\"tst %0\", operands);
-  sprintf(buf, \"bge extendhisi%d\", count);
-  output_asm_insn(buf, NULL);
-  output_asm_insn(\"mov -1, %0\", lateoperands);
-  sprintf(buf, \"bne extendhisi%d\", count+1);
-  output_asm_insn(buf, NULL);
-  sprintf(buf, \"\\nextendhisi%d:\", count);
-  output_asm_insn(buf, NULL);
-  output_asm_insn(\"clr %0\", lateoperands);
-  sprintf(buf, \"\\nextendhisi%d:\", count+1);
-  output_asm_insn(buf, NULL);
-
-  count += 2;
-
-  return \"\";
-}"
-  [(set_attr "length" "6")])
-
-;; make float to int and vice versa 
-;; using the cc_status.flag field we could probably cut down
-;; on seti and setl
-;; assume that we are normally in double and integer mode -
-;; what do pdp library routines do to fpu mode ?
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "register_operand" "=a,a,a")
-	(float:DF (match_operand:SI 1 "general_operand" "r,R,Q")))]
-  "TARGET_FPU"
-  "* if (which_alternative ==0)
-     {
-       rtx latehalf[2];
-
-       latehalf[0] = NULL; 
-       latehalf[1] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
-       output_asm_insn(\"mov %1, -(sp)\", latehalf);
-       output_asm_insn(\"mov %1, -(sp)\", operands);
-       
-       output_asm_insn(\"setl\", operands);
-       output_asm_insn(\"ldcld (sp)+, %0\", operands);
-       output_asm_insn(\"seti\", operands);
-       return \"\";
-     }
-     else if (which_alternative == 1)
-       return \"setl\;ldcld %1, %0\;seti\";
-     else 
-       return \"setl\;ldcld %1, %0\;seti\";
-  "
-  [(set_attr "length" "5,3,4")])
-
-(define_insn "floathidf2"
-  [(set (match_operand:DF 0 "register_operand" "=a,a")
-	(float:DF (match_operand:HI 1 "general_operand" "rR,Qi")))]
-  "TARGET_FPU"
-  "ldcid %1, %0"
-  [(set_attr "length" "1,2")])
-	
-;; cut float to int
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=r,R,Q")
-	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a,a,a"))))]
-  "TARGET_FPU"
-  "* if (which_alternative ==0)
-     {
-       output_asm_insn(\"setl\", operands);
-       output_asm_insn(\"stcdl %1, -(sp)\", operands);
-       output_asm_insn(\"seti\", operands);
-       output_asm_insn(\"mov (sp)+, %0\", operands);
-       operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
-       output_asm_insn(\"mov (sp)+, %0\", operands);
-       return \"\";
-     }
-     else if (which_alternative == 1)
-       return \"setl\;stcdl %1, %0\;seti\";
-     else 
-       return \"setl\;stcdl %1, %0\;seti\";
-  "
-  [(set_attr "length" "5,3,4")])
-
-(define_insn "fix_truncdfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=rR,Q")
-	(fix:HI (fix:DF (match_operand:DF 1 "register_operand" "a,a"))))]
-  "TARGET_FPU"
-  "stcdi %1, %0"
-  [(set_attr "length" "1,2")])
-
-
-;;- arithmetic instructions
-;;- add instructions
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=a,a,a")
-	(plus:DF (match_operand:DF 1 "register_operand" "%0,0,0")
-		 (match_operand:DF 2 "general_operand" "fR,Q,F")))]
-  "TARGET_FPU"
-  "addd %2, %0"
-  [(set_attr "length" "1,2,5")])
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
-	(plus:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0")
-		 (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))]
-  ""
-  "*
-{ /* Here we trust that operands don't overlap 
-
-     or is lateoperands the low word?? - looks like it! */
-
-  unsigned int i;
-  rtx lateoperands[3];
-  
-  lateoperands[0] = operands[0];
-
-  if (REG_P (operands[0]))
-    operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
-  else
-    operands[0] = adj_offsettable_operand (operands[0], 2);
-  
-  if (! CONSTANT_P(operands[2]))
-  {
-    lateoperands[2] = operands[2];
-
-    if (REG_P (operands[2]))
-      operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
-    else
-      operands[2] = adj_offsettable_operand(operands[2], 2);
-
-    output_asm_insn (\"add %2, %0\", operands);
-    output_asm_insn (\"adc %0\", lateoperands);
-    output_asm_insn (\"add %2, %0\", lateoperands);
-    return \"\";
-  }
-
-  lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff);
-  operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff);
-  
-  if (INTVAL(operands[2]))
-  { 
-    output_asm_insn (\"add %2, %0\", operands);
-    output_asm_insn (\"adc %0\", lateoperands);
-  }
-
-  if (INTVAL(lateoperands[2]))
-    output_asm_insn (\"add %2, %0\", lateoperands);
-
-  return \"\";
-}"
-  [(set_attr "length" "3,5,6,8,3,1,5,5,3,8")])
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
-	(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0")
-		 (match_operand:HI 2 "general_operand" "rRLM,Qi,rRLM,Qi")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    if (INTVAL(operands[2]) == 1)
-      return \"inc %0\";
-    else if (INTVAL(operands[2]) == -1)
-      return \"dec %0\";
-
-  return \"add %2, %0\";
-}"
-  [(set_attr "length" "1,2,2,3")])
-
-(define_insn "addqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
-	(plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
-		 (match_operand:QI 2 "general_operand" "rRLM,Qi,rRLM,Qi")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    if (INTVAL(operands[2]) == 1)
-      return \"incb %0\";
-    else if (INTVAL(operands[2]) == -1)
-      return \"decb %0\";
-
-  return \"addb %2, %0\";
-}"
-  [(set_attr "length" "1,2,2,3")])
-
-
-;;- subtract instructions
-;; we don't have to care for constant second 
-;; args, since they are canonical plus:xx now!
-;; also for minus:DF ??
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=a,a")
-	(minus:DF (match_operand:DF 1 "register_operand" "0,0")
-		  (match_operand:DF 2 "general_operand" "fR,Q")))]
-  "TARGET_FPU"
-  "subd %2, %0"
-  [(set_attr "length" "1,2")])
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "general_operand" "=r,r,o,o")
-        (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0")
-                  (match_operand:SI 2 "general_operand" "r,o,r,o")))]
-  ""
-  "*
-{ /* Here we trust that operands don't overlap 
-
-     or is lateoperands the low word?? - looks like it! */
-
-  unsigned int i;
-  rtx lateoperands[3];
-  
-  lateoperands[0] = operands[0];
-
-  if (REG_P (operands[0]))
-    operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
-  else
-    operands[0] = adj_offsettable_operand (operands[0], 2);
-  
-  lateoperands[2] = operands[2];
-
-  if (REG_P (operands[2]))
-    operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
-  else
-    operands[2] = adj_offsettable_operand(operands[2], 2);
-
-  output_asm_insn (\"sub %2, %0\", operands);
-  output_asm_insn (\"sbc %0\", lateoperands);
-  output_asm_insn (\"sub %2, %0\", lateoperands);
-  return \"\";
-}"
-;; offsettable memory addresses always are expensive!!!
-  [(set_attr "length" "3,5,6,8")])
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
-	(minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
-		  (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    abort();
-
-  return \"sub %2, %0\";
-}"
-  [(set_attr "length" "1,2,2,3")])
-
-(define_insn "subqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
-	(minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0")
-		  (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    abort();
-
-  return \"subb %2, %0\";
-}"
-  [(set_attr "length" "1,2,2,3")])
-
-;;;;- and instructions
-;; Bit-and on the pdp (like on the vax) is done with a clear-bits insn.
-(define_expand "andsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(and:SI (match_operand:SI 1 "general_operand" "0")
-		(not:SI (match_operand:SI 2 "general_operand" "g"))))]
-  ""
-  "
-{
-  extern rtx expand_unop ();
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (~INTVAL (operands[2]));
-  else
-    operands[2] = expand_unop (SImode, one_cmpl_optab, operands[2], 0, 1);
-}")
-
-(define_expand "andhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(and:HI (match_operand:HI 1 "general_operand" "0")
-		(not:HI (match_operand:HI 2 "general_operand" "g"))))]
-  ""
-  "
-{
-  extern rtx expand_unop ();
-  if (GET_CODE (operands[2]) == CONST_INT)
-    operands[2] = GEN_INT (~INTVAL (operands[2]));
-  else
-    operands[2] = expand_unop (HImode, one_cmpl_optab, operands[2], 0, 1);
-}")
-
-(define_expand "andqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(and:QI (match_operand:QI 1 "general_operand" "0")
-		(not:QI (match_operand:QI 2 "general_operand" "g"))))]
-  ""
-  "
-{
-  extern rtx expand_unop ();
-  rtx op = operands[2];
-  if (GET_CODE (op) == CONST_INT)
-    operands[2] = GEN_INT (((1 << 8) - 1) & ~INTVAL (op));
-  else
-    operands[2] = expand_unop (QImode, one_cmpl_optab, op, 0, 1);
-}")
-
-(define_insn "andcbsi3"
-  [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
-        (and:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0")
-                (not:SI (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K"))))]
-  ""
-  "*
-{ /* Here we trust that operands don't overlap 
-
-     or is lateoperands the low word?? - looks like it! */
-
-  unsigned int i;
-  rtx lateoperands[3];
-  
-  lateoperands[0] = operands[0];
-
-  if (REG_P (operands[0]))
-    operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
-  else
-    operands[0] = adj_offsettable_operand (operands[0], 2);
-  
-  if (! CONSTANT_P(operands[2]))
-  {
-    lateoperands[2] = operands[2];
-
-    if (REG_P (operands[2]))
-      operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
-    else
-      operands[2] = adj_offsettable_operand(operands[2], 2);
-
-    output_asm_insn (\"bic %2, %0\", operands);
-    output_asm_insn (\"bic %2, %0\", lateoperands);
-    return \"\";
-  }
-
-  lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff);
-  operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff);
-  
-  /* these have different lengths, so we should have 
-     different constraints! */
-  if (INTVAL(operands[2]))
-    output_asm_insn (\"bic %2, %0\", operands);
-
-  if (INTVAL(lateoperands[2]))
-    output_asm_insn (\"bic %2, %0\", lateoperands);
-
-  return \"\";
-}"
-  [(set_attr "length" "2,4,4,6,2,2,4,3,3,6")])
-
-(define_insn "andcbhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
-	(and:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
-		(not:HI (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi"))))]
-  ""
-  "bic %2, %0"
-  [(set_attr "length" "1,2,2,3")])
-
-(define_insn "andcbqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
-	(and:QI (match_operand:QI 1 "general_operand" "0,0,0,0")
-		(not:QI (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi"))))]
-  ""
-  "bicb %2, %0"
-  [(set_attr "length" "1,2,2,3")])
-
-;;- Bit set (inclusive or) instructions
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
-        (ior:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0")
-                  (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))]
-  ""
-  "*
-{ /* Here we trust that operands don't overlap 
-
-     or is lateoperands the low word?? - looks like it! */
-
-  unsigned int i;
-  rtx lateoperands[3];
-  
-  lateoperands[0] = operands[0];
-
-  if (REG_P (operands[0]))
-    operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
-  else
-    operands[0] = adj_offsettable_operand (operands[0], 2);
-  
-  if (! CONSTANT_P(operands[2]))
-  {
-    lateoperands[2] = operands[2];
-
-    if (REG_P (operands[2]))
-      operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
-    else
-      operands[2] = adj_offsettable_operand(operands[2], 2);
-
-    output_asm_insn (\"bis %2, %0\", operands);
-    output_asm_insn (\"bis %2, %0\", lateoperands);
-    return \"\";
-  }
-
-  lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff);
-  operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff);
-  
-  /* these have different lengths, so we should have 
-     different constraints! */
-  if (INTVAL(operands[2]))
-    output_asm_insn (\"bis %2, %0\", operands);
-
-  if (INTVAL(lateoperands[2]))
-    output_asm_insn (\"bis %2, %0\", lateoperands);
-
-  return \"\";
-}"
-  [(set_attr "length" "2,4,4,6,2,2,4,3,3,6")])
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
-	(ior:HI (match_operand:HI 1 "general_operand" "%0,0,0,0")
-		(match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))]
-  ""
-  "bis %2, %0"
-  [(set_attr "length" "1,2,2,3")])
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
-	(ior:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
-		(match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi")))]
-  ""
-  "bisb %2, %0")
-
-;;- xor instructions
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-        (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
-                  (match_operand:SI 2 "arith_operand" "r,I,J,K")))]
-  "TARGET_40_PLUS"
-  "*
-{ /* Here we trust that operands don't overlap */
-
-  unsigned int i;
-  rtx lateoperands[3];
-
-  lateoperands[0] = operands[0];
-  operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
-
-  if (REG_P(operands[2]))
-  {
-    lateoperands[2] = operands[2];
-    operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
-    
-    output_asm_insn (\"xor %2, %0\", operands);
-    output_asm_insn (\"xor %2, %0\", lateoperands);
-
-    return \"\";
-  }
-
-  lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff);
-  operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff);
-  
-  if (INTVAL(operands[2]))
-    output_asm_insn (\"xor %2, %0\", operands);
-
-  if (INTVAL(lateoperands[2]))
-    output_asm_insn (\"xor %2, %0\", lateoperands);
-
-  return \"\";
-}"
-  [(set_attr "length" "2,1,1,2")])
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=rR,Q")
-	(xor:HI (match_operand:HI 1 "general_operand" "%0,0")
-		(match_operand:HI 2 "register_operand" "r,r")))]
-  "TARGET_40_PLUS"
-  "xor %2, %0"
-  [(set_attr "length" "1,2")])
-
-;;- one complement instructions
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "general_operand" "=rR,Q")
-        (not:HI (match_operand:HI 1 "general_operand" "0,0")))]
-  ""
-  "com %0"
-  [(set_attr "length" "1,2")])
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "general_operand" "=rR,Q")
-        (not:QI (match_operand:QI 1 "general_operand" "0,0")))]
-  ""
-  "comb %0"
-  [(set_attr "length" "1,2")])
-
-;;- arithmetic shift instructions
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
-		   (match_operand:HI 2 "general_operand" "rR,Qi")))]
-  "TARGET_45"
-  "ashc %2,%0"
-  [(set_attr "length" "1,2")])
-
-;; Arithmetic right shift on the pdp works by negating the shift count.
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  operands[2] = negate_rtx (HImode, operands[2]);
-}")
-
-;; define asl aslb asr asrb - ashc missing!
-
-;; asl 
-(define_insn "" 
-  [(set (match_operand:HI 0 "general_operand" "=rR,Q")
-	(ashift:HI (match_operand:HI 1 "general_operand" "0,0")
-		   (const_int 1)))]
-  ""
-  "asl %0"
-  [(set_attr "length" "1,2")])
-
-;; and another possibility for asr is << -1
-;; might cause problems since -1 can also be encoded as 65535!
-;; not in gcc2 ??? 
-
-;; asr
-(define_insn "" 
-  [(set (match_operand:HI 0 "general_operand" "=rR,Q")
-	(ashift:HI (match_operand:HI 1 "general_operand" "0,0")
-		   (const_int -1)))]
-  ""
-  "asr %0"
-  [(set_attr "length" "1,2")])
-
-;; shift is by arbitrary count is expensive, 
-;; shift by one cheap - so let's do that, if
-;; space doesn't matter
-(define_insn "" 
-  [(set (match_operand:HI 0 "general_operand" "=r")
-	(ashift:HI (match_operand:HI 1 "general_operand" "0")
-		   (match_operand:HI 2 "expand_shift_operand" "O")))]
-  "! optimize_size"
-  "*
-{
-  register int i;
-
-  for (i = 1; i <= abs(INTVAL(operands[2])); i++)
-    if (INTVAL(operands[2]) < 0)
-      output_asm_insn(\"asr %0\", operands);
-    else
-      output_asm_insn(\"asl %0\", operands);
-      
-  return \"\";
-}"
-;; longest is 4
-  [(set (attr "length") (const_int 4))])
-
-;; aslb
-(define_insn "" 
-  [(set (match_operand:QI 0 "general_operand" "=r,o")
-	(ashift:QI (match_operand:QI 1 "general_operand" "0,0")
-		   (match_operand:HI 2 "const_immediate_operand" "n,n")))]
-  ""
-  "*
-{ /* allowing predec or post_inc is possible, but hairy! */
-  int i, cnt;
-
-  cnt = INTVAL(operands[2]) & 0x0007;
-
-  for (i=0 ; i < cnt ; i++)
-       output_asm_insn(\"aslb %0\", operands);
-
-  return \"\";
-}"
-;; set attribute length ( match_dup 2 & 7 ) *(1 or 2) !!!
-  [(set_attr_alternative "length" 
-                         [(const_int 7)
-                          (const_int 14)])])
-
-;;; asr 
-;(define_insn "" 
-;  [(set (match_operand:HI 0 "general_operand" "=rR,Q")
-;	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0,0")
-;		     (const_int 1)))]
-;  ""
-;  "asr %0"
-;  [(set_attr "length" "1,2")])
-
-;; asrb
-(define_insn "" 
-  [(set (match_operand:QI 0 "general_operand" "=r,o")
-	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0")
-		     (match_operand:HI 2 "const_immediate_operand" "n,n")))]
-  ""
-  "*
-{ /* allowing predec or post_inc is possible, but hairy! */
-  int i, cnt;
-
-  cnt = INTVAL(operands[2]) & 0x0007;
-
-  for (i=0 ; i < cnt ; i++)
-       output_asm_insn(\"asrb %0\", operands);
-
-  return \"\";
-}"
-  [(set_attr_alternative "length" 
-                         [(const_int 7)
-                          (const_int 14)])])
-
-;; the following is invalid - too complex!!! - just say 14 !!!
-;  [(set (attr "length") (plus (and (match_dup 2)
-;                                   (const_int 7))
-;                              (and (match_dup 2)
-;                                   (const_int 7))))])
-
-
-
-;; can we get +-1 in the next pattern? should 
-;; have been caught by previous patterns!
-
-(define_insn "ashlhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(ashift:HI (match_operand:HI 1 "register_operand" "0,0")
-		   (match_operand:HI 2 "general_operand" "rR,Qi")))]
-  ""
-  "*
-{
-  if (GET_CODE(operands[2]) == CONST_INT)
-    if (INTVAL(operands[2]) == 1)
-      return \"asl %0\";
-    else if (INTVAL(operands[2]) == -1)
-      return \"asr %0\";
-
-  return \"ash %2,%0\";
-}"
-  [(set_attr "length" "1,2")])
-
-;; Arithmetic right shift on the pdp works by negating the shift count.
-(define_expand "ashrhi3"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(ashift:HI (match_operand:HI 1 "register_operand" "0")
-		   (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  operands[2] = negate_rtx (HImode, operands[2]);
-}")
-
-;;;;- logical shift instructions
-;;(define_insn "lshrsi3"
-;;  [(set (match_operand:HI 0 "register_operand" "=r")
-;;	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
-;;		     (match_operand:HI 2 "arith_operand" "rI")))]
-;;  ""
-;;  "srl %0,%2")
-
-;; absolute 
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "general_operand" "=fR,Q")
-	(abs:DF (match_operand:DF 1 "general_operand" "0,0")))]
-  "TARGET_FPU"
-  "absd %0"
-  [(set_attr "length" "1,2")])
-
-(define_insn "abshi2"
-  [(set (match_operand:HI 0 "general_operand" "=r,o")
-	(abs:HI (match_operand:HI 1 "general_operand" "0,0")))]
-  "TARGET_ABSHI_BUILTIN"
-  "*
-{
-  static count = 0;
-  char buf[200];
-	
-  output_asm_insn(\"tst %0\", operands);
-  sprintf(buf, \"bge abshi%d\", count);
-  output_asm_insn(buf, NULL);
-  output_asm_insn(\"neg %0\", operands);
-  sprintf(buf, \"\\nabshi%d:\", count++);
-  output_asm_insn(buf, NULL);
-
-  return \"\";
-}"
-  [(set_attr "length" "3,5")])
-
-
-;; define expand abshi - is much better !!! - but
-;; will it be optimized into an abshi2 ?
-;; it will leave better code, because the tsthi might be 
-;; optimized away!!
-; -- just a thought - don't have time to check 
-;
-;(define_expand "abshi2"
-;  [(match_operand:HI 0 "general_operand" "")
-;   (match_operand:HI 1 "general_operand" "")]
-;  ""
-;  "
-;{
-;  rtx label = gen_label_rtx ();
-;
-;  /* do I need this? */
-;  do_pending_stack_adjust ();
-;
-;  emit_move_insn (operands[0], operands[1]);
-;
-;  emit_insn (gen_tsthi (operands[0]));
-;  emit_insn (gen_bge (label1));
-;
-;  emit_insn (gen_neghi(operands[0], operands[0])
-;  
-;  emit_barrier ();
-;
-;  emit_label (label);
-;
-;  /* allow REG_NOTES to be set on last insn (labels don't have enough
-;     fields, and can't be used for REG_NOTES anyway).  */
-;  emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
-;  DONE;
-;}")
-
-;; negate insns
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "general_operand" "=fR,Q")
-	(neg:DF (match_operand:DF 1 "register_operand" "0,0")))]
-  "TARGET_FPU"
-  "negd %0"
-  [(set_attr "length" "1,2")])
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "general_operand" "=rR,Q")
-	(neg:HI (match_operand:HI 1 "general_operand" "0,0")))]
-  ""
-  "neg %0"
-  [(set_attr "length" "1,2")])
-
-(define_insn "negqi2"
-  [(set (match_operand:QI 0 "general_operand" "=rR,Q")
-	(neg:QI (match_operand:QI 1 "general_operand" "0,0")))]
-  ""
-  "negb %0"
-  [(set_attr "length" "1,2")])
-
-
-;; Unconditional and other jump instructions
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "jmp %l0"
-  [(set_attr "length" "2")])
-
-(define_insn ""
-  [(set (pc)
-    (label_ref (match_operand 0 "" "")))
-   (clobber (const_int 1))]
-  ""
-  "jmp %l0"
-  [(set_attr "length" "2")])
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:HI 0 "general_operand" "rR,Q"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmp %0"
-  [(set_attr "length" "1,2")])
-
-;; indirect jump - let's be conservative!
-;; allow only register_operand, even though we could also 
-;; allow labels etc.
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:HI 0 "register_operand" "r"))]
-  ""
-  "jmp (%0)")
-
-;;- jump to subroutine
-
-(define_insn "call"
-  [(call (match_operand:HI 0 "general_operand" "R,Q")
-	 (match_operand:HI 1 "general_operand" "g,g"))
-;;   (use (reg:HI 0)) what was that ???
-  ]
-  ;;- Don't use operand 1 for most machines.
-  ""
-  "jsr pc, %0"
-  [(set_attr "length" "1,2")])
-
-;;- jump to subroutine
-(define_insn "call_value"
-  [(set (match_operand 0 "" "")
-	(call (match_operand:HI 1 "general_operand" "R,Q")
-	      (match_operand:HI 2 "general_operand" "g,g")))
-;;   (use (reg:HI 0)) - what was that ????
-  ]
-  ;;- Don't use operand 2 for most machines.
-  ""
-  "jsr pc, %1"
-  [(set_attr "length" "1,2")])
-
-;;- nop instruction
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
-
-
-;;- multiply 
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=a,a,a")
-	(mult:DF (match_operand:DF 1 "register_operand" "%0,0,0")
-		 (match_operand:DF 2 "general_operand" "fR,Q,F")))]
-  "TARGET_FPU"
-  "muld %2, %0"
-  [(set_attr "length" "1,2,5")])
-
-;; 16 bit result multiply:
-;; currently we multiply only into odd registers, so we don't use two 
-;; registers - but this is a bit inefficient at times. If we define 
-;; a register class for each register, then we can specify properly 
-;; which register need which scratch register ....
-
-(define_insn "mulhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d,d") ; multiply regs
-	(mult:HI (match_operand:HI 1 "register_operand" "%0,0")
-		 (match_operand:HI 2 "general_operand" "rR,Qi")))]
-  "TARGET_45"
-  "mul %2, %0"
-  [(set_attr "length" "1,2")])
-
-;; 32 bit result
-(define_expand "mulhisi3"
-  [(set (match_dup 3)
-	(match_operand:HI 1 "general_operand" "g,g"))
-   (set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered!
-	(mult:SI (truncate:HI 
-                  (match_dup 0))
-		 (match_operand:HI 2 "general_operand" "rR,Qi")))]
-  "TARGET_45"
-  "operands[3] = gen_lowpart(HImode, operands[1]);")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered!
-	(mult:SI (truncate:HI 
-                  (match_operand:SI 1 "register_operand" "%0,0"))
-		 (match_operand:HI 2 "general_operand" "rR,Qi")))]
-  "TARGET_45"
-  "mul %2, %0"
-  [(set_attr "length" "1,2")])
-
-;(define_insn "mulhisi3"
-;  [(set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered!
-;	(mult:SI (truncate:HI 
-;                  (match_operand:SI 1 "register_operand" "%0,0"))
-;		 (match_operand:HI 2 "general_operand" "rR,Qi")))]
-;  "TARGET_45"
-;  "mul %2, %0"
-;  [(set_attr "length" "1,2")])
-
-;;- divide
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=a,a,a")
-	(div:DF (match_operand:DF 1 "register_operand" "0,0,0")
-		(match_operand:DF 2 "general_operand" "fR,Q,F")))]
-  "TARGET_FPU"
-  "divd %2, %0"
-  [(set_attr "length" "1,2,5")])
-
-	 
-(define_expand "divhi3"
-  [(set (subreg:HI (match_dup 1) 0)
-	(div:HI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "g")))
-   (set (match_operand:HI 0 "general_operand" "=r")
-        (subreg:HI (match_dup 1) 0))]
-  "TARGET_45"
-  "")
-
-(define_insn ""
-  [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 0)
-	(div:HI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "g")))]
-  "TARGET_45"
-  "div %2,%0"
-  [(set_attr "length" "2")])
-
-(define_expand "modhi3"
-  [(set (subreg:HI (match_dup 1) 1)
-	(mod:HI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "g")))
-   (set (match_operand:HI 0 "general_operand" "=r")
-        (subreg:HI (match_dup 1) 1))]
-  "TARGET_45"
-  "")
-
-(define_insn ""
-  [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 1)
-	(mod:HI (match_operand:SI 1 "general_operand" "0")
-		(match_operand:HI 2 "general_operand" "g")))]
-  "TARGET_45"
-  "div %2,%0"
-  [(set_attr "length" "2")])
-
-;(define_expand "divmodhi4"
-;  [(parallel [(set (subreg:HI (match_dup 1) 0)
-;	           (div:HI (match_operand:SI 1 "general_operand" "0")
-;		           (match_operand:HI 2 "general_operand" "g")))
-;              (set (subreg:HI (match_dup 1) 1)
-;	           (mod:HI (match_dup 1)
-;		           (match_dup 2)))])
-;   (set (match_operand:HI 3 "general_operand" "=r")
-;        (subreg:HI (match_dup 1) 1))
-;   (set (match_operand:HI 0 "general_operand" "=r")
-;        (subreg:HI (match_dup 1) 0))]
-;  "TARGET_45"
-;  "")
-;
-;(define_insn ""
-;  [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 0)
-;	           (div:HI (match_operand:SI 1 "general_operand" "0")
-;		           (match_operand:HI 2 "general_operand" "g")))
-;   (set (subreg:HI (match_dup 0) 1)
-;	           (mod:HI (match_dup 1)
-;		           (match_dup 2)))]
-;  "TARGET_45"
-;  "div %2, %0")
-;
-   
-;; is rotate doing the right thing to be included here ????
diff --git a/gcc/config/pdp11/t-pdp11 b/gcc/config/pdp11/t-pdp11
deleted file mode 100755
index ebcdbb3..0000000
--- a/gcc/config/pdp11/t-pdp11
+++ /dev/null
@@ -1,8 +0,0 @@
-LIBGCC1 = libgcc1.null
-CROSS_LIBGCC1 = libgcc1.null
-
-# forget the libgcc1...
-LIBGCC1_TEST =
-
-TARGET_LIBGCC2_CFLAGS = -O2 -mfloat32
-#LIB2FUNCS_EXTRA =
diff --git a/gcc/config/pdp11/xm-pdp11.h b/gcc/config/pdp11/xm-pdp11.h
deleted file mode 100755
index f6a5467..0000000
--- a/gcc/config/pdp11/xm-pdp11.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Configuration for GNU C-compiler for pdp-11 family.
-   Copyright (C) 1994, 1995 Free Software Foundation, Inc.
-   Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* gcc can never run on a PDP, since it needs too much memory */
-/* but we need the xm-pdp.h file to compile libgcc2           */
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
diff --git a/gcc/config/psos.h b/gcc/config/psos.h
deleted file mode 100755
index d404300..0000000
--- a/gcc/config/psos.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/* Operating system specific defines to be used when targeting GCC for some
-   embedded system running pSOS. We assume GNU tools with ELF, but
-   try to maintain compatibility with the MRI tools. Based on svr4.h.
-   Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.
-
-   To use this file, make up a file with a name like:
-
-	?????-psos.h
-
-   where ????? is replaced by the name of the basic hardware that you
-   are targeting for.  Then, in the file ?????-psos.h, put something
-   like:
-
-	#include "?????.h"
-	#include "psos.h"
-
-   followed by any really system-specific defines (or overrides of
-   defines) which you find that you need.
-*/
-
-
-/* Define a symbol indicating that we are using psos.h.  */
-
-#define USING_PSOS_H
-
-
-/* All pSOS targets currently use the ELF object file format.  */
-
-#define OBJECT_FORMAT_ELF
-
-
-/* Provide a NULL STARTFILE_SPEC. The startfile cannot be specified
-   here because it depends on the architecture (e.g. 68K), the
-   board-support package (e.g. M162) and the run-time configuration
-   (e.g. application vs. ram-image vs. rom-image). Specify the
-   startfile in a linker-script created from the generic
-   architecture-specific linker-scripts. */
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-
-
-/* Predefined macros (independent of processor type). */
-
-#define CPP_PREDEFINES "-Dpsos"
-
-
-/* Implicit library calls should use ANSI memcpy rather than BSD
-   bcopy, etc.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-
-/* When using stabs, gcc2_compiled must be a stabs entry, not an
-   ordinary symbol, or gdb won't see it.  The stabs entry must be
-   before the N_SO in order for gdb to find it.  */
-
-#define ASM_IDENTIFY_GCC(FILE)						\
-do									\
-  {									\
-    fputs (".stabs \"gcc2_compiled.\", 0x3c, 0, 0, 0\n", FILE);	\
-  }									\
-while (0)
-
-/* This is how we tell the assembler that a symbol is weak.  */
-
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
-  do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \
-       fputc ('\n', FILE); } while (0)
-
-/* Switch into a generic section. */
-
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
-  fprintf (FILE, ".section\t%s,\"%s\",@progbits\n", NAME, \
-	   (DECL) && TREE_CODE (DECL) == FUNCTION_DECL ? "ax" : \
-	   (DECL) && DECL_READONLY_SECTION (DECL, RELOC) ? "a" : "aw")
-
-
-/* Define the pseudo-ops used to switch to the .ctors and .dtors
-   sections. */
-
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"aw\""
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"aw\""
-
-/* A default list of other sections which we might be "in" at any given
-   time.  For targets that use additional sections (e.g. .tdesc) you
-   should override this definition in the target-specific file which
-   includes this file.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_ctors, in_dtors
-
-/* A default list of extra section function definitions.  For targets
-   that use additional sections (e.g. .tdesc) you should override this
-   definition in the target-specific file which includes this file.  */
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-extern void text_section ();
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-
-#ifndef INT_ASM_OP
-#define INT_ASM_OP		".long"
-#endif
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-
-/* Use DBX debugging info by default.  */
-
-#ifndef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-#endif
-
-/* For pSOS we use DBX debugging info.  */
-
-#define DBX_DEBUGGING_INFO
-
-
-/* Prevent generation of an exit function.  */
-
-#define HAVE_ATEXIT
-
diff --git a/gcc/config/ptx4.h b/gcc/config/ptx4.h
deleted file mode 100755
index aa31924..0000000
--- a/gcc/config/ptx4.h
+++ /dev/null
@@ -1,859 +0,0 @@
-/* Operating system specific defines to be used when targeting GCC for some
-   generic System V Release 4 system.
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Ron Guilmette (rfg@monkeys.com).
-   Renamed and changed to suit Dynix/ptx v4 and later.
-   Modified by Tim Wright (timw@sequent.com).
-  
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.
-
-*/
-
-/* Define a symbol indicating that we are using svr4.h.  */
-#define USING_SVR4_H
-
-/* For the sake of libgcc2.c, indicate target supports atexit.  */
-#define HAVE_ATEXIT
-
-/* Cpp, assembler, linker, library, and startfile spec's.  */
-
-/* This defines which switch letters take arguments.  On svr4, most of
-   the normal cases (defined in gcc.c) apply, and we also have -h* and
-   -z* options (for the linker).  Note however that there is no such
-   thing as a -T option for svr4.  */
-
-#define SWITCH_TAKES_ARG(CHAR) \
-  (   (CHAR) == 'D' \
-   || (CHAR) == 'U' \
-   || (CHAR) == 'o' \
-   || (CHAR) == 'e' \
-   || (CHAR) == 'u' \
-   || (CHAR) == 'I' \
-   || (CHAR) == 'm' \
-   || (CHAR) == 'L' \
-   || (CHAR) == 'A' \
-   || (CHAR) == 'h' \
-   || (CHAR) == 'z')
-
-/* This defines which multi-letter switches take arguments.  On svr4,
-   there are no such switches except those implemented by GCC itself.  */
-
-#define WORD_SWITCH_TAKES_ARG(STR)			\
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR)			\
-  && strcmp (STR, "Tdata") && strcmp (STR, "Ttext")	\
-  && strcmp (STR, "Tbss"))
-
-/* You should redefine CPP_PREDEFINES in any file which includes this one.
-   The definition should be appropriate for the type of target system
-   involved, and it should include any -A (assertion) options which are
-   appropriate for the given target system.  */
-#undef CPP_PREDEFINES
-
-/* Provide an ASM_SPEC appropriate for svr4.  Here we try to support as
-   many of the specialized svr4 assembler options as seems reasonable,
-   given that there are certain options which we can't (or shouldn't)
-   support directly due to the fact that they conflict with other options 
-   for other svr4 tools (e.g. ld) or with other options for GCC itself.
-   For example, we don't support the -o (output file) or -R (remove
-   input file) options because GCC already handles these things.  We
-   also don't support the -m (run m4) option for the assembler because
-   that conflicts with the -m (produce load map) option of the svr4
-   linker.  We do however allow passing arbitrary options to the svr4
-   assembler via the -Wa, option.
-
-   Note that gcc doesn't allow a space to follow -Y in a -Ym,* or -Yd,*
-   option.
-*/
-
-#undef ASM_SPEC
-#define ASM_SPEC \
-  "-no_0f_fix %{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*}"
-
-/* svr4 assemblers need the `-' (indicating input from stdin) to come after
-   the -o option (and its argument) for some reason.  If we try to put it
-   before the -o option, the assembler will try to read the file named as
-   the output file in the -o option as an input file (after it has already
-   written some stuff to it) and the binary stuff contained therein will
-   cause totally confuse the assembler, resulting in many spurious error
-   messages.  */
-
-#undef ASM_FINAL_SPEC
-#define ASM_FINAL_SPEC "%{pipe:-}"
-
-/* Provide a LIB_SPEC appropriate for svr4.  Here we tack on the default
-   standard C library (unless we are building a shared library).  */
-
-#undef	LIB_SPEC
-#define LIB_SPEC "%{!shared:%{!symbolic:-lc}}"
-
-/* Provide a LIBGCC_SPEC appropriate for svr4.  We also want to exclude
-   libgcc when -symbolic.  */
-
-#undef  LIBGCC_SPEC
-#define LIBGCC_SPEC "%{!shared:%{!symbolic:-lgcc}}"
-
-/* Provide an ENDFILE_SPEC appropriate for svr4.  Here we tack on our own
-   magical crtend.o file (see crtstuff.c) which provides part of the
-   support for getting C++ file-scope static object constructed before
-   entering `main', followed by the normal svr3/svr4 "finalizer" file,
-   which is either `gcrtn.o' or `crtn.o'.  */
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s %{pg:gcrtn.o}%{!pg:crtn.o%s}"
-
-/* Provide a LINK_SPEC appropriate for svr4.  Here we provide support
-   for the special GCC options -static, -shared, and -symbolic which
-   allow us to link things in one of these three modes by applying the
-   appropriate combinations of options at link-time.  We also provide
-   support here for as many of the other svr4 linker options as seems
-   reasonable, given that some of them conflict with options for other
-   svr4 tools (e.g. the assembler).  In particular, we do support the
-   -z*, -V, -b, -t, -Qy, -Qn, and -YP* options here, and the -e*,
-   -l*, -o*, -r, -s, -u*, and -L* options are directly supported
-   by gcc.c itself.  We don't directly support the -m (generate load
-   map) option because that conflicts with the -m (run m4) option of
-   the svr4 assembler.  We also don't directly support the svr4 linker's
-   -I* or -M* options because these conflict with existing GCC options.
-   We do however allow passing arbitrary options to the svr4 linker
-   via the -Wl, option.  We don't support the svr4 linker's -a option
-   at all because it is totally useless and because it conflicts with
-   GCC's own -a option.
-
-   Note that gcc doesn't allow a space to follow -Y in a -YP,* option.
-
-   When the -G link option is used (-shared and -symbolic) a final link is
-   not being done.  */
-
-#undef	LINK_SPEC
-#define LINK_SPEC "%{h*} %{v:-V} \
-		   %{b} %{Wl,*:%*} \
-		   %{static:-dn -Bstatic} \
-		   %{shared:-G -dy -z text} \
-		   %{symbolic:-Bsymbolic -G -dy -z text} \
-		   %{G:-G} \
-		   %{YP,*} \
-		   %{!YP,*:%{p:-Y P,/lib/libp:/usr/lib/libp:/lib:/usr/lib} \
-		    %{!p:-Y P,/lib:/usr/lib}} \
-		   %{Qy:} %{!Qn:-Qy}"
-
-/* Gcc automatically adds in one of the files /lib/values-Xc.o,
-   /lib/values-Xa.o, or /lib/values-Xt.o for each final link
-   step (depending upon the other gcc options selected, such as
-   -traditional and -ansi).  These files each contain one (initialized)
-   copy of a special variable called `_lib_version'.  Each one of these
-   files has `_lib_version' initialized to a different (enum) value.
-   The SVR4 library routines query the value of `_lib_version' at run
-   to decide how they should behave.  Specifically, they decide (based
-   upon the value of `_lib_version') if they will act in a strictly ANSI
-   conforming manner or not.
-*/
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared: \
-			 %{!symbolic: \
-			  %{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}\
-			%{pg:gcrti.o%s}%{!pg:crti.o%s} \
-			%{ansi:values-Xc.o%s} \
-			%{!ansi: \
-			 %{traditional:values-Xt.o%s} \
-			 %{!traditional:values-Xa.o%s}} \
- 			crtbegin.o%s"
-
-/* Attach a special .ident directive to the end of the file to identify
-   the version of GCC which compiled this code.  The format of the
-   .ident string is patterned after the ones produced by native svr4
-   C compilers.  */
-
-#define IDENT_ASM_OP ".ident"
-
-#define ASM_FILE_END(FILE)					\
-do {				 				\
-     fprintf ((FILE), "\t%s\t\"GCC: (GNU) %s\"\n",		\
-	      IDENT_ASM_OP, version_string);			\
-   } while (0)
-
-/* Allow #sccs in preprocessor.  */
-
-#define SCCS_DIRECTIVE
-
-/* Output #ident as a .ident.  */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
-
-/* Use periods rather than dollar signs in special g++ assembler names.  */
-
-#define NO_DOLLAR_IN_LABEL
-
-/* Writing `int' for a bitfield forces int alignment for the structure.  */
-
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Implicit library calls should use memcpy, not bcopy, etc.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Handle #pragma weak and #pragma pack.  */
-
-#define HANDLE_SYSV_PRAGMA
-
-/* System V Release 4 uses DWARF debugging info.  */
-
-#define DWARF_DEBUGGING_INFO
-
-/* The numbers used to denote specific machine registers in the System V
-   Release 4 DWARF debugging information are quite likely to be totally
-   different from the numbers used in BSD stabs debugging information
-   for the same kind of target machine.  Thus, we undefine the macro
-   DBX_REGISTER_NUMBER here as an extra inducement to get people to
-   provide proper machine-specific definitions of DBX_REGISTER_NUMBER
-   (which is also used to provide DWARF registers numbers in dwarfout.c)
-   in their tm.h files which include this file.  */
-
-#undef DBX_REGISTER_NUMBER
-
-/* gas on SVR4 supports the use of .stabs.  Permit -gstabs to be used
-   in general, although it will only work when using gas.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Use DWARF debugging info by default.  */
-
-#ifndef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF_DEBUG
-#endif
-
-/* Make LBRAC and RBRAC addresses relative to the start of the
-   function.  The native Solaris stabs debugging format works this
-   way, gdb expects it, and it reduces the number of relocation
-   entries.  */
-
-#define DBX_BLOCKS_FUNCTION_RELATIVE 1
-
-/* When using stabs, gcc2_compiled must be a stabs entry, not an
-   ordinary symbol, or gdb won't see it.  The stabs entry must be
-   before the N_SO in order for gdb to find it.  */
-
-#define ASM_IDENTIFY_GCC(FILE)						\
-do									\
-  {									\
-    if (write_symbols != DBX_DEBUG)					\
-      fputs ("gcc2_compiled.:\n", FILE);				\
-    else								\
-      fputs ("\t.stabs\t\"gcc2_compiled.\", 0x3c, 0, 0, 0\n", FILE);	\
-  }									\
-while (0)
-
-/* Like block addresses, stabs line numbers are relative to the
-   current function.  */
-
-#define ASM_OUTPUT_SOURCE_LINE(file, line)				\
-do									\
-  {									\
-    static int sym_lineno = 1;						\
-    fprintf (file, ".stabn 68,0,%d,.LM%d-",				\
-	     line, sym_lineno);						\
-    assemble_name (file,						\
-		   XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));\
-    fprintf (file, "\n.LM%d:\n", sym_lineno);				\
-    sym_lineno += 1;							\
-  }									\
-while (0)
-
-/* In order for relative line numbers to work, we must output the
-   stabs entry for the function name first.  */
-
-#define DBX_FUNCTION_FIRST
-
-/* Generate a blank trailing N_SO to mark the end of the .o file, since
-   we can't depend upon the linker to mark .o file boundaries with
-   embedded stabs.  */
-
-#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME)			\
-  fprintf (FILE,							\
-	   "\t.text\n\t.stabs \"\",%d,0,0,.Letext\n.Letext:\n", N_SO)
-
-/* Define the actual types of some ANSI-mandated types.  (These
-   definitions should work for most SVR4 systems).  */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-/* This causes trouble, because it requires the host machine
-   to support ANSI C.  */
-/* #define MULTIBYTE_CHARS */
-
-#undef ASM_BYTE_OP
-#define ASM_BYTE_OP	".byte"
-
-#undef SET_ASM_OP
-#define SET_ASM_OP	".set"
-
-/* This is how to begin an assembly language file.  Most svr4 assemblers want
-   at least a .file directive to come first, and some want to see a .version
-   directive come right after that.  Here we just establish a default
-   which generates only the .file directive.  If you need a .version
-   directive for any specific target, you should override this definition
-   in the target-specific file which includes this one.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)                                    \
-  output_file_directive ((FILE), main_input_filename)
-
-/* This is how to allocate empty space in some section.  The .zero
-   pseudo-op is used for this on most svr4 assemblers.  */
-
-#define SKIP_ASM_OP	".zero"
-
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
-  fprintf (FILE, "\t%s\t%u\n", SKIP_ASM_OP, (SIZE))
-
-/* The prefix to add to user-visible assembler symbols.
-
-   For System V Release 4 the convention is *not* to prepend a leading
-   underscore onto user-level symbol names.  */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-
-   For most svr4 systems, the convention is that any symbol which begins
-   with a period is not put into the linker symbol table by the assembler. */
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM)			\
-do {									\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM);				\
-} while (0)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.
-
-   For most svr4 systems, the convention is that any symbol which begins
-   with a period is not put into the linker symbol table by the assembler. */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)			\
-do {									\
-  sprintf (LABEL, "*.%s%d", PREFIX, NUM);				\
-} while (0)
-
-/* Output the label which precedes a jumptable.  Note that for all svr4
-   systems where we actually generate jumptables (which is to say every
-   svr4 target except i386, where we use casesi instead) we put the jump-
-   tables into the .rodata section and since other stuff could have been
-   put into the .rodata section prior to any given jumptable, we have to
-   make sure that the location counter for the .rodata section gets pro-
-   perly re-aligned prior to the actual beginning of the jump table.  */
-
-#define ALIGN_ASM_OP ".align"
-
-#ifndef ASM_OUTPUT_BEFORE_CASE_LABEL
-#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
-  ASM_OUTPUT_ALIGN ((FILE), 2);
-#endif
-
-#undef ASM_OUTPUT_CASE_LABEL
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,JUMPTABLE)		\
-  do {									\
-    ASM_OUTPUT_BEFORE_CASE_LABEL (FILE, PREFIX, NUM, JUMPTABLE)		\
-    ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM);			\
-  } while (0)
-
-/* The standard SVR4 assembler seems to require that certain builtin
-   library routines (e.g. .udiv) be explicitly declared as .globl
-   in each assembly file where they are referenced.  */
-
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN)				\
-  ASM_GLOBALIZE_LABEL (FILE, XSTR (FUN, 0))
-
-/* This says how to output assembler code to declare an
-   uninitialized external linkage data object.  Under SVR4,
-   the linker seems to want the alignment of data objects
-   to depend on their types.  We do exactly that here.  */
-
-#define COMMON_ASM_OP	".comm"
-
-#undef ASM_OUTPUT_ALIGNED_COMMON
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fprintf ((FILE), "\t%s\t", COMMON_ASM_OP);				\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
-} while (0)
-
-/* This says how to output assembler code to declare an
-   uninitialized internal linkage data object.  Under SVR4,
-   the linker seems to want the alignment of data objects
-   to depend on their types.  We do exactly that here.  */
-
-#define LOCAL_ASM_OP	".local"
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fprintf ((FILE), "\t%s\t", LOCAL_ASM_OP);				\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), "\n");						\
-  ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);			\
-} while (0)
-
-/* This is the pseudo-op used to generate a 32-bit word of data with a
-   specific value in some section.  This is the same for all known svr4
-   assemblers.  */
-
-#define INT_ASM_OP		".long"
-
-/* This is the pseudo-op used to generate a contiguous sequence of byte
-   values from a double-quoted string WITHOUT HAVING A TERMINATING NUL
-   AUTOMATICALLY APPENDED.  This is the same for most svr4 assemblers.  */
-
-#undef ASCII_DATA_ASM_OP
-#define ASCII_DATA_ASM_OP	".ascii"
-
-/* Support const sections and the ctors and dtors sections for g++.
-   Note that there appears to be two different ways to support const
-   sections at the moment.  You can either #define the symbol
-   READONLY_DATA_SECTION (giving it some code which switches to the
-   readonly data section) or else you can #define the symbols
-   EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
-   SELECT_RTX_SECTION.  We do both here just to be on the safe side.  */
-
-#define USE_CONST_SECTION	1
-
-#define CONST_SECTION_ASM_OP	".section\t.rodata"
-
-/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
-
-   Note that we want to give these sections the SHF_WRITE attribute
-   because these sections will actually contain data (i.e. tables of
-   addresses of functions in the current root executable or shared library
-   file) and, in the case of a shared library, the relocatable addresses
-   will have to be properly resolved/relocated (and then written into) by
-   the dynamic linker when it actually attaches the given shared library
-   to the executing process.  (Note that on SVR4, you may wish to use the
-   `-z text' option to the ELF linker, when building a shared library, as
-   an additional check that you are doing everything right.  But if you do
-   use the `-z text' option when building a shared library, you will get
-   errors unless the .ctors and .dtors sections are marked as writable
-   via the SHF_WRITE attribute.)  */
-
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"aw\""
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"aw\""
-
-/* On svr4, we *do* have support for the .init and .fini sections, and we
-   can put stuff in there to be executed before and after `main'.  We let
-   crtstuff.c and other files know this by defining the following symbols.
-   The definitions say how to change sections to the .init and .fini
-   sections.  This is the same for all known svr4 assemblers.  */
-
-#define INIT_SECTION_ASM_OP	".section\t.init"
-#define FINI_SECTION_ASM_OP	".section\t.fini"
-
-/* A default list of other sections which we might be "in" at any given
-   time.  For targets that use additional sections (e.g. .tdesc) you
-   should override this definition in the target-specific file which
-   includes this file.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_ctors, in_dtors
-
-/* A default list of extra section function definitions.  For targets
-   that use additional sections (e.g. .tdesc) you should override this
-   definition in the target-specific file which includes this file.  */
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CONST_SECTION_FUNCTION						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-#define READONLY_DATA_SECTION() const_section ()
-
-extern void text_section ();
-
-#define CONST_SECTION_FUNCTION						\
-void									\
-const_section ()							\
-{									\
-  if (!USE_CONST_SECTION)						\
-    text_section();							\
-  else if (in_section != in_const)					\
-    {									\
-      fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP);		\
-      in_section = in_const;						\
-    }									\
-}
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-/* Switch into a generic section.
-   This is currently only used to support section attributes.
-
-   We make the section read-only and executable for a function decl,
-   read-only for a const data decl, and writable for a non-const data decl. */
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
-  fprintf (FILE, ".section\t%s,\"%s\",@progbits\n", NAME, \
-	   (DECL) && TREE_CODE (DECL) == FUNCTION_DECL ? "ax" : \
-	   (DECL) && DECL_READONLY_SECTION (DECL, RELOC) ? "a" : "aw")
-
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement or statements to switch to the appropriate
-   section for output of DECL.  DECL is either a `VAR_DECL' node
-   or a constant of some sort.  RELOC indicates whether forming
-   the initial value of DECL requires link-time relocations.  */
-
-#define SELECT_SECTION(DECL,RELOC)					\
-{									\
-  if (TREE_CODE (DECL) == STRING_CST)					\
-    {									\
-      if (! flag_writable_strings)					\
-	const_section ();						\
-      else								\
-	data_section ();						\
-    }									\
-  else if (TREE_CODE (DECL) == VAR_DECL)				\
-    {									\
-      if ((flag_pic && RELOC)						\
-	  || !TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)		\
-	  || !DECL_INITIAL (DECL)					\
-	  || (DECL_INITIAL (DECL) != error_mark_node			\
-	      && !TREE_CONSTANT (DECL_INITIAL (DECL))))			\
-	data_section ();						\
-      else								\
-	const_section ();						\
-    }									\
-  else									\
-    const_section ();							\
-}
-
-/* A C statement or statements to switch to the appropriate
-   section for output of RTX in mode MODE.  RTX is some kind
-   of constant in RTL.  The argument MODE is redundant except
-   in the case of a `const_int' rtx.  Currently, these always
-   go into the const section.  */
-
-#undef SELECT_RTX_SECTION
-#define SELECT_RTX_SECTION(MODE,RTX) const_section()
-
-/* Define the strings used for the special svr4 .type and .size directives.
-   These strings generally do not vary from one system running svr4 to
-   another, but if a given system (e.g. m88k running svr) needs to use
-   different pseudo-op names for these, they may be overridden in the
-   file which includes this one.  */
-
-#define TYPE_ASM_OP	".type"
-#define SIZE_ASM_OP	".size"
-
-/* This is how we tell the assembler that a symbol is weak.  */
-
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
-  do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \
-       fputc ('\n', FILE); } while (0)
-
-/* The following macro defines the format used to output the second
-   operand of the .type assembler directive.  Different svr4 assemblers
-   expect various different forms for this operand.  The one given here
-   is just a default.  You may need to override it in your machine-
-   specific tm.h file (depending upon the particulars of your assembler).  */
-
-#define TYPE_OPERAND_FMT	"@%s"
-
-/* Write the extra assembler code needed to declare a function's result.
-   Most svr4 assemblers don't require any special declaration of the
-   result value, but there are exceptions.  */
-
-#ifndef ASM_DECLARE_RESULT
-#define ASM_DECLARE_RESULT(FILE, RESULT)
-#endif
-
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare a function properly.
-   Some svr4 assemblers need to also have something extra said about the
-   function's return value.  We allow for that here.  */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "function");			\
-    putc ('\n', FILE);							\
-    ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));			\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Write the extra assembler code needed to declare an object properly.  */
-
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
-    putc ('\n', FILE);							\
-    size_directive_output = 0;						\
-    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-      {									\
-	size_directive_output = 1;					\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-	fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));	\
-      }									\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
-	 assemble_name (FILE, name);					 \
-	 fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL))); \
-       }								 \
-   } while (0)
-
-/* This is how to declare the size of a function.  */
-
-#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)			\
-  do {									\
-    if (!flag_inhibit_size_directive)					\
-      {									\
-        char label[256];						\
-	static int labelno;						\
-	labelno++;							\
-	ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno);		\
-	ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno);		\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, (FNAME));					\
-        fprintf (FILE, ",");						\
-	assemble_name (FILE, label);					\
-        fprintf (FILE, "-");						\
-	assemble_name (FILE, (FNAME));					\
-	putc ('\n', FILE);						\
-      }									\
-  } while (0)
-
-/* A table of bytes codes used by the ASM_OUTPUT_ASCII and
-   ASM_OUTPUT_LIMITED_STRING macros.  Each byte in the table
-   corresponds to a particular byte value [0..255].  For any
-   given byte value, if the value in the corresponding table
-   position is zero, the given character can be output directly.
-   If the table value is 1, the byte must be output as a \ooo
-   octal escape.  If the tables value is anything else, then the
-   byte value should be output as a \ followed by the value
-   in the table.  Note that we can use standard UN*X escape
-   sequences for many control characters, but we don't use
-   \a to represent BEL because some svr4 assemblers (e.g. on
-   the i386) don't know about that.  Also, we don't use \v
-   since some versions of gas, such as 2.2 did not accept it.  */
-
-#define ESCAPES \
-"\1\1\1\1\1\1\1\1btn\1fr\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\0\0\"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
-\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\\\0\0\0\
-\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1"
-
-/* Some svr4 assemblers have a limit on the number of characters which
-   can appear in the operand of a .string directive.  If your assembler
-   has such a limitation, you should define STRING_LIMIT to reflect that
-   limit.  Note that at least some svr4 assemblers have a limit on the
-   actual number of bytes in the double-quoted string, and that they
-   count each character in an escape sequence as one byte.  Thus, an
-   escape sequence like \377 would count as four bytes.
-
-   If your target assembler doesn't support the .string directive, you
-   should define this to zero.
-*/
-
-#define STRING_LIMIT	((unsigned) 256)
-
-#define STRING_ASM_OP	".string"
-
-/* The routine used to output NUL terminated strings.  We use a special
-   version of this for most svr4 targets because doing so makes the
-   generated assembly code more compact (and thus faster to assemble)
-   as well as more readable, especially for targets like the i386
-   (where the only alternative is to output character sequences as
-   comma separated lists of numbers).   */
-
-#define ASM_OUTPUT_LIMITED_STRING(FILE, STR)				\
-  do									\
-    {									\
-      register unsigned char *_limited_str = (unsigned char *) (STR);	\
-      register unsigned ch;						\
-      fprintf ((FILE), "\t%s\t\"", STRING_ASM_OP);			\
-      for (; ch = *_limited_str; _limited_str++)			\
-        {								\
-	  register int escape;						\
-	  switch (escape = ESCAPES[ch])					\
-	    {								\
-	    case 0:							\
-	      putc (ch, (FILE));					\
-	      break;							\
-	    case 1:							\
-	      fprintf ((FILE), "\\%03o", ch);				\
-	      break;							\
-	    default:							\
-	      putc ('\\', (FILE));					\
-	      putc (escape, (FILE));					\
-	      break;							\
-	    }								\
-        }								\
-      fprintf ((FILE), "\"\n");						\
-    }									\
-  while (0)
-
-/* The routine used to output sequences of byte values.  We use a special
-   version of this for most svr4 targets because doing so makes the
-   generated assembly code more compact (and thus faster to assemble)
-   as well as more readable.  Note that if we find subparts of the
-   character sequence which end with NUL (and which are shorter than
-   STRING_LIMIT) we output those using ASM_OUTPUT_LIMITED_STRING.  */
-
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH)				\
-  do									\
-    {									\
-      register unsigned char *_ascii_bytes = (unsigned char *) (STR);	\
-      register unsigned char *limit = _ascii_bytes + (LENGTH);		\
-      register unsigned bytes_in_chunk = 0;				\
-      for (; _ascii_bytes < limit; _ascii_bytes++)			\
-        {								\
-	  register unsigned char *p;					\
-	  if (bytes_in_chunk >= 60)					\
-	    {								\
-	      fprintf ((FILE), "\"\n");					\
-	      bytes_in_chunk = 0;					\
-	    }								\
-	  for (p = _ascii_bytes; p < limit && *p != '\0'; p++)		\
-	    continue;							\
-	  if (p < limit && (p - _ascii_bytes) <= STRING_LIMIT)		\
-	    {								\
-	      if (bytes_in_chunk > 0)					\
-		{							\
-		  fprintf ((FILE), "\"\n");				\
-		  bytes_in_chunk = 0;					\
-		}							\
-	      ASM_OUTPUT_LIMITED_STRING ((FILE), _ascii_bytes);		\
-	      _ascii_bytes = p;						\
-	    }								\
-	  else								\
-	    {								\
-	      register int escape;					\
-	      register unsigned ch;					\
-	      if (bytes_in_chunk == 0)					\
-		fprintf ((FILE), "\t%s\t\"", ASCII_DATA_ASM_OP);	\
-	      switch (escape = ESCAPES[ch = *_ascii_bytes])		\
-		{							\
-		case 0:							\
-		  putc (ch, (FILE));					\
-		  bytes_in_chunk++;					\
-		  break;						\
-		case 1:							\
-		  fprintf ((FILE), "\\%03o", ch);			\
-		  bytes_in_chunk += 4;					\
-		  break;						\
-		default:						\
-		  putc ('\\', (FILE));					\
-		  putc (escape, (FILE));				\
-		  bytes_in_chunk += 2;					\
-		  break;						\
-		}							\
-	    }								\
-	}								\
-      if (bytes_in_chunk > 0)						\
-        fprintf ((FILE), "\"\n");					\
-    }									\
-  while (0)
-
-/* All SVR4 targets use the ELF object file format.  */
-#define OBJECT_FORMAT_ELF
diff --git a/gcc/config/pyr/pyr.c b/gcc/config/pyr/pyr.c
deleted file mode 100755
index 9a2e3bc..0000000
--- a/gcc/config/pyr/pyr.c
+++ /dev/null
@@ -1,857 +0,0 @@
-/* Subroutines for insn-output.c for Pyramid 90x, 9000, and MIServer Series.
-   Copyright (C) 1989, 1991, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Some output-actions in pyr.md need these.  */
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "tree.h"
-
-/*
- * Do FUNCTION_ARG.
- * This cannot be defined as a macro on pyramids, because Pyramid Technology's
- * C compiler dies on (several equivalent definitions of) this macro.
- * The only way around this cc bug was to make this a function.
- * While it would be possible to use a macro version for gcc, it seems
- * more reliable to have a single version of the code.
- */
-void *
-pyr_function_arg(cum, mode, type, named)
-  CUMULATIVE_ARGS cum;
-  enum machine_mode mode;
-  tree type;
-{
-  return (void *)(FUNCTION_ARG_HELPER (cum, mode,type,named));
-}
-
-/* Do the hard part of PARAM_SAFE_FOR_REG_P.
- * This cannot be defined as a macro on pyramids, because Pyramid Technology's
- * C compiler dies on (several equivalent definitions of) this macro.
- * The only way around this cc bug was to make this a function.
- */
-int
-inner_param_safe_helper (type)
-    tree type;
-{
-  return (INNER_PARAM_SAFE_HELPER(type));
-}
-
-
-/* Return 1 if OP is a non-indexed operand of mode MODE.
-   This is either a register reference, a memory reference,
-   or a constant.  In the case of a memory reference, the address
-   is checked to make sure it isn't indexed.
-
-   Register and memory references must have mode MODE in order to be valid,
-   but some constants have no machine mode and are valid for any mode.
-
-   If MODE is VOIDmode, OP is checked for validity for whatever mode
-   it has.
-
-   The main use of this function is as a predicate in match_operand
-   expressions in the machine description.
-
-   It is  useful to compare this with general_operand().  They should
-   be identical except for one line.
-
-   This function seems necessary because of the non-orthogonality of
-   Pyramid insns.
-   For any 2-operand insn, and any combination of operand modes,
-   if indexing is valid for the isn's second operand, it is invalid
-   for the first operand to be indexed. */
-
-extern int volatile_ok;
-
-int
-nonindexed_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  register RTX_CODE code = GET_CODE (op);
-  int mode_altering_drug = 0;
-
-  if (mode == VOIDmode)
-    mode = GET_MODE (op);
-
-  /* Don't accept CONST_INT or anything similar
-     if the caller wants something floating.  */
-  if (GET_MODE (op) == VOIDmode && mode != VOIDmode
-      && GET_MODE_CLASS (mode) != MODE_INT)
-    return 0;
-
-  if (CONSTANT_P (op))
-    return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode)
-	    && LEGITIMATE_CONSTANT_P (op));
-
-  /* Except for certain constants with VOIDmode, already checked for,
-     OP's mode must match MODE if MODE specifies a mode.  */
-
-  if (GET_MODE (op) != mode)
-    return 0;
-
-  while (code == SUBREG)
-    {
-      op = SUBREG_REG (op);
-      code = GET_CODE (op);
-#if 0
-      /* No longer needed, since (SUBREG (MEM...))
-	 will load the MEM into a reload reg in the MEM's own mode.  */
-      mode_altering_drug = 1;
-#endif
-    }
-  if (code == REG)
-    return 1;
-  if (code == CONST_DOUBLE)
-    return LEGITIMATE_CONSTANT_P (op);
-  if (code == MEM)
-    {
-      register rtx y = XEXP (op, 0);
-      if (! volatile_ok && MEM_VOLATILE_P (op))
-	return 0;
-    GO_IF_NONINDEXED_ADDRESS (y, win);
-    }
-  return 0;
-
- win:
-  if (mode_altering_drug)
-    return ! mode_dependent_address_p (XEXP (op, 0));
-  return 1;
-}
-
-/* Return non-zero if the rtx OP has an immediate component.  An
-   immediate component or additive term equal to zero is rejected
-   due to assembler problems.  */
-
-int
-has_direct_base (op)
-     rtx op;
-{
-  if ((CONSTANT_ADDRESS_P (op)
-       && op != const0_rtx)
-      || (GET_CODE (op) == PLUS
-	  && ((CONSTANT_ADDRESS_P (XEXP (op, 1))
-	       && XEXP (op, 1) != const0_rtx)
-	      || (CONSTANT_ADDRESS_P (XEXP (op, 0))
-		  && XEXP (op, 0) != const0_rtx))))
-    return 1;
-
-  return 0;
-}
-
-/* Return zero if the rtx OP has a (scaled) index.  */
-
-int
-has_index (op)
-     rtx op;
-{
-  if (GET_CODE (op) == PLUS
-      && (GET_CODE (XEXP (op, 0)) == MULT
-	  || (GET_CODE (XEXP (op, 1)) == MULT)))
-    return 1;
-  else
-    return 0;
-}
-
-int swap_operands;
-
-/* weird_memory_memory -- return 1 if OP1 and OP2 can be compared (or
-   exchanged with xchw) with one instruction.  If the operands need to
-   be swapped, set the global variable SWAP_OPERANDS.  This function
-   silently assumes that both OP0 and OP1 are valid memory references.
-   */
-
-int
-weird_memory_memory (op0, op1)
-     rtx op0, op1;
-{
-  RTX_CODE code0, code1;
-
-  op0 = XEXP (op0, 0);
-  op1 = XEXP (op1, 0);
-  code0 = GET_CODE (op0);
-  code1 = GET_CODE (op1);
-
-  swap_operands = 0;
-
-  if (code1 == REG || code1 == SUBREG)
-    {
-      return 1;
-    }
-  if (code0 == REG || code0 == SUBREG)
-    {
-      swap_operands = 1;
-      return 1;
-    }
-  if (has_direct_base (op0) && has_direct_base (op1))
-    {
-      if (has_index (op1))
-	{
-	  if (has_index (op0))
-	    return 0;
-	  swap_operands = 1;
-	}
-
-      return 1;
-    }
-  return 0;
-}
-
-int
-signed_comparison (x, mode)
-     rtx x;
-     enum machine_mode mode;
-{
-  return ! TRULY_UNSIGNED_COMPARE_P (GET_CODE (x));
-}
-
-extern rtx force_reg ();
-rtx test_op0, test_op1;
-enum machine_mode test_mode;
-
-/* Sign-extend or zero-extend constant X from FROM_MODE to TO_MODE.  */
-
-rtx
-extend_const (x, extop, from_mode, to_mode)
-    rtx x;
-    RTX_CODE extop;
-    enum machine_mode from_mode, to_mode;
-{
-  int val;
-  int negative;
-  if (from_mode == to_mode)
-    return x;
-  if (GET_CODE (x) != CONST_INT)
-    abort ();
-  val = INTVAL (x);
-  negative = val & (1 << (GET_MODE_BITSIZE (from_mode) - 1));
-  if (GET_MODE_BITSIZE (from_mode) == HOST_BITS_PER_INT)
-    abort ();
-  if (negative && extop == SIGN_EXTEND)
-    val = val | ((-1) << (GET_MODE_BITSIZE (from_mode)));
-  else
-    val = val & ~((-1) << (GET_MODE_BITSIZE (from_mode)));
-  if (GET_MODE_BITSIZE (to_mode) == HOST_BITS_PER_INT)
-    return GEN_INT (val);
-  return GEN_INT (val & ~((-1) << (GET_MODE_BITSIZE (to_mode))));
-}
-
-rtx
-ensure_extended (op, extop, from_mode)
-     rtx op;
-     RTX_CODE extop;
-     enum machine_mode from_mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return extend_const (op, extop, from_mode, SImode);
-  else
-    return force_reg (SImode, gen_rtx (extop, SImode, op));
-}
-
-/* Emit rtl for a branch, as well as any delayed (integer) compare insns.
-   The compare insn to perform is determined by the global variables
-   test_op0 and test_op1.  */
-
-void
-extend_and_branch (extop)
-     RTX_CODE extop;
-{
-  rtx op0, op1;
-  RTX_CODE code0, code1;
-
-  op0 = test_op0, op1 = test_op1;
-  if (op0 == 0)
-    return;
-
-  code0 = GET_CODE (op0);
-  if (op1 != 0)
-    code1 = GET_CODE (op1);
-  test_op0 = test_op1 = 0;
-
-  if (op1 == 0)
-    {
-      op0 = ensure_extended (op0, extop, test_mode);
-      emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, op0));
-    }
-  else
-    {
-      if (CONSTANT_P (op0) && CONSTANT_P (op1))
-	{
-	  op0 = ensure_extended (op0, extop, test_mode);
-	  op1 = ensure_extended (op1, extop, test_mode);
-	}
-      else if (extop == ZERO_EXTEND && test_mode == HImode)
-	{
-	  /* Pyramids have no unsigned "cmphi" instructions.  We need to
-	     zero extend unsigned halfwords into temporary registers. */
-	  op0 = ensure_extended (op0, extop, test_mode);
-	  op1 = ensure_extended (op1, extop, test_mode);
-	}
-      else if (CONSTANT_P (op0))
-	{
-	  op0 = ensure_extended (op0, extop, test_mode);
-	  op1 = ensure_extended (op1, extop, test_mode);
-	}
-      else if (CONSTANT_P (op1))
-	{
-	  op1 = ensure_extended (op1, extop, test_mode);
-	  op0 = ensure_extended (op0, extop, test_mode);
-	}
-      else if ((code0 == REG || code0 == SUBREG)
-	       && (code1 == REG || code1 == SUBREG))
-	{
-	  /* I could do this case without extension, by using the virtual
-	     register address (but that would lose for global regs).  */
-	  op0 = ensure_extended (op0, extop, test_mode);
-	  op1 = ensure_extended (op1, extop, test_mode);
-	}
-      else if (code0 == MEM && code1 == MEM)
-	{
-	  /* Load into a reg if the address combination can't be handled
-	     directly.  */
-	  if (! weird_memory_memory (op0, op1))
-	    op0 = force_reg (test_mode, op0);
-	}
-
-      emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx,
-			  gen_rtx (COMPARE, VOIDmode, op0, op1)));
-    }
-}
-
-/* Return non-zero if the two single-word moves with operands[0]
-   and operands[1] for the first single-word move, and operands[2]
-   and operands[3] for the second single-word move, is possible to
-   combine to a double word move.
-
-   The criterion is whether the operands are in consecutive memory cells,
-   registers, etc.  */
-
-int
-movdi_possible (operands)
-     rtx operands[];
-{
-  int cnst_diff0, cnst_diff1;
-  RTX_CODE code0 = GET_CODE (operands[0]);
-  RTX_CODE code1 = GET_CODE (operands[1]);
-
-  /* Don't dare to combine (possibly overlapping) memory -> memory moves.  */
-  /* It would be possible to detect the cases where we dare, by using
-     constant_diff (operands[0], operands[1])!!!  */
-  if (code0 == MEM && code1 == MEM)
-    return 0;
-
-  cnst_diff0 = consecutive_operands (operands[0], operands[2]);
-  if (cnst_diff0 == 0)
-    return 0;
-
-  cnst_diff1 = consecutive_operands (operands[1], operands[3]);
-  if (cnst_diff1 == 0)
-    return 0;
-
-  if (cnst_diff0 & cnst_diff1)
-    {
-      /* The source and destination operands are consecutive.  */
-
-      /* If the first move writes into the source of the second move,
-	 we cannot combine.  */
-      if ((code0 == REG
-	   && reg_overlap_mentioned_p (operands[0], operands[3]))
-	  || (code0 == SUBREG
-	      && subreg_overlap_mentioned_p (operands[0], operands[3])))
-	  return 0;
-
-      if (cnst_diff0 & 1)
-	/* operands[0],[1] has higher addresses than operands[2],[3].  */
-	swap_operands = 0;
-      else
-	/* operands[0],[1] has lower addresses than operands[2],[3].  */
-	swap_operands = 1;
-      return 1;
-    }
-  return 0;
-}
-
-/* Like reg_overlap_mentioned_p, but accepts a subreg rtx instead
-   of a reg.  */
-
-int
-subreg_overlap_mentioned_p (subreg, x)
-     rtx subreg, x;
-{
-  rtx reg = SUBREG_REG (subreg);
-  int regno = REGNO (reg) + SUBREG_WORD (subreg);
-  int endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (subreg));
-  return refers_to_regno_p (regno, endregno, x, 0);
-}
-
-/* Return 1 if OP0 is a consecutive operand to OP1, 2 if OP1 is a
-   consecutive operand to OP0.
-
-   This function is used to determine if addresses are consecutive,
-   and therefore possible to combine to fewer instructions.  */
-
-int
-consecutive_operands (op0, op1)
-     rtx op0, op1;
-{
-  RTX_CODE code0, code1;
-  int cnst_diff;
-  int regno_off0, regno_off1;
-
-  code0 = GET_CODE (op0);
-  code1 = GET_CODE (op1);
-
-  regno_off0 = 0;
-  if (code0 == SUBREG)
-    {
-      if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))) <= UNITS_PER_WORD)
-	return 0;
-      regno_off0 = SUBREG_WORD (op0);
-      op0 = SUBREG_REG (op0);
-      code0 = REG;
-    }
-
-  regno_off1 = 0;
-  if (code1 == SUBREG)
-    {
-      if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (op1))) <= UNITS_PER_WORD)
-	return 0;
-      regno_off1 = SUBREG_WORD (op1);
-      op1 = SUBREG_REG (op1);
-      code1 = REG;
-    }
-
-  if (code0 != code1)
-    return 0;
-
-  switch (code0)
-    {
-    case CONST_INT:
-      /* Cannot permit any symbolic constants, even if the consecutive
-	 operand is 0, since a movl really performs sign extension.  */
-      if (code1 != CONST_INT)
-	return 0;
-      if ((INTVAL (op0) == 0 && INTVAL (op1) == 0)
-	  || (INTVAL (op0) == -1 && INTVAL (op1) == -1))
-	return 3;
-      if ((INTVAL (op0) == 0 && INTVAL (op1) > 0)
-	  || (INTVAL (op0) == -1 && INTVAL (op1) < 0))
-	return 2;
-      if ((INTVAL (op1) == 0 && INTVAL (op0) > 0)
-	  || (INTVAL (op1) == -1 && INTVAL (op0) < 0))
-	return 1;
-      break;
-
-    case REG:
-      regno_off0 = REGNO (op0) + regno_off0;
-      regno_off1 = REGNO (op1) + regno_off1;
-
-      cnst_diff = regno_off0 - regno_off1;
-      if (cnst_diff == 1)
-	{
-	  /* movl with the highest numbered parameter (local) register as
-	     source or destination, doesn't wrap to the lowest numbered local
-	     (temporary) register.  */
-
-	  if (regno_off0 % 16 != 0)
-	    return 1;
-	  else
-	    return 0;
-	}
-      else if (cnst_diff == -1)
-	{
-	  if (regno_off1 % 16 != 0)
-	    return 2;
-	  else
-	    return 0;
-	}
-      break;
-
-    case MEM:
-      op0 = XEXP (op0, 0);
-      op1 = XEXP (op1, 0);
-      if (GET_CODE (op0) == CONST)
-	op0 = XEXP (op0, 0);
-      if (GET_CODE (op1) == CONST)
-	op1 = XEXP (op1, 0);
-
-      cnst_diff = constant_diff (op0, op1);
-      if (cnst_diff)
-	{
-	  if (cnst_diff == 4)
-	    return 1;
-	  else if (cnst_diff == -4)
-	    return 2;
-	}
-      break;
-    }
-  return 0;
-}
-
-/* Return the constant difference of the rtx expressions OP0 and OP1,
-   or 0 if they don't have a constant difference.
-
-   This function is used to determine if addresses are consecutive,
-   and therefore possible to combine to fewer instructions.  */
-
-int
-constant_diff (op0, op1)
-     rtx op0, op1;
-{
-  RTX_CODE code0, code1;
-  int cnst_diff;
-
-  code0 = GET_CODE (op0);
-  code1 = GET_CODE (op1);
-
-  if (code0 != code1)
-    {
-      if (code0 == PLUS)
-	{
-	  if (GET_CODE (XEXP (op0, 1)) == CONST_INT
-	      && rtx_equal_p (op1, XEXP (op0, 0)))
-	    return INTVAL (XEXP (op0, 1));
-	}
-      else if (code1 == PLUS)
-	{
-	  if (GET_CODE (XEXP (op1, 1)) == CONST_INT
-	      && rtx_equal_p (op0, XEXP (op1, 0)))
-	    return -INTVAL (XEXP (op1, 1));
-	}
-      return 0;
-    }
-
-  if (code0 == CONST_INT)
-    return INTVAL (op0) - INTVAL (op1);
-
-  if (code0 == PLUS)
-    {
-      cnst_diff = constant_diff (XEXP (op0, 0), XEXP (op1, 0));
-      if (cnst_diff)
-	return (rtx_equal_p (XEXP (op0, 1), XEXP (op1, 1)))
-	  ? cnst_diff : 0;
-      cnst_diff = constant_diff (XEXP (op0, 1), XEXP (op1, 1));
-      if (cnst_diff)
-	return (rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0)))
-	  ? cnst_diff : 0;
-    }
-
-  return 0;
-}
-
-int
-already_sign_extended (insn, from_mode, op)
-     rtx insn;
-     enum machine_mode from_mode;
-     rtx op;
-{
-  rtx xinsn, xdest, xsrc;
-
-  for (;;)
-    {
-      insn = PREV_INSN (insn);
-      if (insn == 0)
-	return 0;
-      if (GET_CODE (insn) == NOTE || GET_CODE (insn) == JUMP_INSN)
-	continue;
-      if (GET_CODE (insn) == CALL_INSN && ! call_used_regs[REGNO (op)])
-	continue;
-      if (GET_CODE (insn) != INSN)
-	return 0;
-      xinsn = PATTERN (insn);
-
-      if (GET_CODE (xinsn) != SET)
-	return 0;
-
-      xdest = SET_DEST (xinsn);
-      xsrc = SET_SRC (xinsn);
-
-      if (GET_CODE (xdest) == SUBREG)
-	abort ();
-
-      if ( ! REG_P (xdest))
-	continue;
-
-      if (REGNO (op) == REGNO (xdest)
-	  && ((GET_CODE (xsrc) == SIGN_EXTEND
-	   && GET_MODE (XEXP (xsrc, 0)) == from_mode)
-	  || (GET_CODE (xsrc) == MEM
-	      && GET_MODE (xsrc) == from_mode)))
-	return 1;
-
-      /* The register is modified by another operation.  */
-      if (reg_overlap_mentioned_p (xdest, op))
-	return 0;
-    }
-}
-
-char *
-output_move_double (operands)
-     rtx *operands;
-{
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    {
-      if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT)
-	{
-	  /* In an integer, the low-order word is in CONST_DOUBLE_LOW.  */
-	  rtx const_op = operands[1];
-	  if ((CONST_DOUBLE_HIGH (const_op) == 0
-	       && CONST_DOUBLE_LOW (const_op) >= 0)
-	      || (CONST_DOUBLE_HIGH (const_op) == -1
-		  && CONST_DOUBLE_LOW (const_op) < 0))
-	    {
-	      operands[1] = GEN_INT (CONST_DOUBLE_LOW (const_op));
-	      return "movl %1,%0";
-	    }
-	  operands[1] = GEN_INT (CONST_DOUBLE_HIGH (const_op));
-	  output_asm_insn ("movw %1,%0", operands);
-	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-	  operands[1] = GEN_INT (CONST_DOUBLE_LOW (const_op));
-	  return "movw %1,%0";
-	}
-      else
-	{
-	  /* In a real, the low-address word is in CONST_DOUBLE_LOW.  */
-	  rtx const_op = operands[1];
-	  if ((CONST_DOUBLE_LOW (const_op) == 0
-	       && CONST_DOUBLE_HIGH (const_op) >= 0)
-	      || (CONST_DOUBLE_LOW (const_op) == -1
-		  && CONST_DOUBLE_HIGH (const_op) < 0))
-	    {
-	      operands[1] = GEN_INT (CONST_DOUBLE_HIGH (const_op));
-	      return "movl %1,%0";
-	    }
-	  operands[1] = GEN_INT (CONST_DOUBLE_LOW (const_op));
-	  output_asm_insn ("movw %1,%0", operands);
-	  operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-	  operands[1] = GEN_INT (CONST_DOUBLE_HIGH (const_op));
-	  return "movw %1,%0";
-	}
-    }
-
-  return "movl %1,%0";
-}
-
-/* Output a shift insns, after having reduced integer arguments to
-   avoid as warnings.  */
-
-char *
-output_shift (pattern, op2, mod)
-     char *pattern;
-     rtx op2;
-     int mod;
-{
-  if (GET_CODE (op2) == CONST_INT)
-    {
-      int cnt = INTVAL (op2) % mod;
-      if (cnt == 0)
-	{
-	  cc_status = cc_prev_status;
-	  return "";
-	}
-      op2 = GEN_INT (cnt);
-    }
-  return pattern;
-}
-
-/* Return non-zero if the code of this rtx pattern is a relop.  */
-
-int
-relop (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case EQ:
-    case NE:
-    case LT:
-    case LE:
-    case GE:
-    case GT:
-    case LTU:
-    case LEU:
-    case GEU:
-    case GTU:
-      return 1;
-    }
-  return 0;
-}
-
-void
-notice_update_cc (EXP, INSN)
-     rtx EXP, INSN;
-{
-  switch (GET_CODE (EXP))
-    {
-    case SET:
-      switch (GET_CODE (SET_DEST (EXP)))
-	{
-	case CC0:
-	  cc_status.mdep = 0;
-	  cc_status.flags = 0;
-	  cc_status.value1 = 0;
-	  cc_status.value2 = SET_SRC (EXP);
-	  break;
-
-	case PC:
-	  break;
-
-	case REG:
-	  switch (GET_CODE (SET_SRC (EXP)))
-	    {
-	    case CALL:
-	      goto call;
-	    case MEM:
-	      if (GET_MODE (SET_SRC (EXP)) == QImode
-		  || GET_MODE (SET_SRC (EXP)) == HImode)
-		{
-		  cc_status.mdep = 0;
-		  cc_status.flags = CC_NO_OVERFLOW;
-		  cc_status.value1 = SET_DEST (EXP);
-		  cc_status.value2 = SET_SRC (EXP);
-		  break;
-		}
-	      /* else: Fall through.  */
-	    case CONST_INT:
-	    case SYMBOL_REF:
-	    case LABEL_REF:
-	    case CONST:
-	    case CONST_DOUBLE:
-	    case REG:
-	      if (cc_status.value1
-		  && reg_overlap_mentioned_p (SET_DEST (EXP),
-					      cc_status.value1))
-		cc_status.value1 = 0;
-	      if (cc_status.value2
-		  && reg_overlap_mentioned_p (SET_DEST (EXP),
-					      cc_status.value2))
-		cc_status.value2 = 0;
-	      break;
-
-	    case UDIV:
-	    case UMOD:
-	      cc_status.mdep = CC_VALID_FOR_UNSIGNED;
-	      cc_status.flags = CC_NO_OVERFLOW;
-	      cc_status.value1 = SET_DEST (EXP);
-	      cc_status.value2 = SET_SRC (EXP);
-	      break;
-	    default:
-	      cc_status.mdep = 0;
-	      cc_status.flags = CC_NO_OVERFLOW;
-	      cc_status.value1 = SET_DEST (EXP);
-	      cc_status.value2 = SET_SRC (EXP);
-	      break;
-	    }
-	  break;
-
-	case MEM:
-	  switch (GET_CODE (SET_SRC (EXP)))
-	    {
-	    case REG:
-	      if (GET_MODE (SET_SRC (EXP)) == QImode
-		  || GET_MODE (SET_SRC (EXP)) == HImode)
-		{
-		  cc_status.flags = CC_NO_OVERFLOW;
-		  cc_status.value1 = SET_DEST (EXP);
-		  cc_status.value2 = SET_SRC (EXP);
-		  cc_status.mdep = 0;
-		  break;
-		}
-	      /* else: Fall through.  */
-	    case CONST_INT:
-	    case SYMBOL_REF:
-	    case LABEL_REF:
-	    case CONST:
-	    case CONST_DOUBLE:
-	    case MEM:
-	      /* Need to forget cc_status about memory positions each
-		 time a memory store is made, even if the memory store
-		 insns in question doesn't modify the condition codes.  */
-	      if (cc_status.value1 &&
-		  GET_CODE (cc_status.value1) == MEM)
-		cc_status.value1 = 0;
-	      if (cc_status.value2 &&
-		  GET_CODE (cc_status.value2) == MEM)
-		cc_status.value2 = 0;
-	      break;
-	    case SIGN_EXTEND:
-	    case FLOAT_EXTEND:
-	    case FLOAT_TRUNCATE:
-	    case FLOAT:
-	    case FIX:
-	      cc_status.flags = CC_NO_OVERFLOW;
-	      cc_status.value1 = SET_DEST (EXP);
-	      cc_status.value2 = SET_SRC (EXP);
-	      cc_status.mdep = 0;
-	      break;
-
-	    default:
-	      abort ();
-	    }
-	  break;
-
-	default:
-	  abort ();
-	}
-      break;
-
-    case CALL:
-    call:
-      CC_STATUS_INIT;
-      break;
-      /* Do calls preserve the condition codes?  (At least forget
-	 cc_status expressions if they refer to registers
-	 not preserved across calls.  Also forget expressions
-	 about memory contents.)  */
-      if (cc_status.value1
-	  && (refers_to_regno_p (PYR_TREG (0), PYR_TREG (15),
-				 cc_status.value1, 0)
-	      || GET_CODE (cc_status.value1) == MEM))
-	cc_status.value1 = 0;
-      if (cc_status.value2
-	  && (refers_to_regno_p (PYR_TREG (0), PYR_TREG (15),
-				 cc_status.value2, 0)
-	      || GET_CODE (cc_status.value2) == MEM))
-	cc_status.value2 = 0;
-      break;
-
-    default:
-      CC_STATUS_INIT;
-    }
-}
-
-void
-forget_cc_if_dependent (op)
-     rtx op;
-{
-  cc_status = cc_prev_status;
-  if (cc_status.value1 && reg_overlap_mentioned_p (op, cc_status.value1))
-    cc_status.value1 = 0;
-  if (cc_status.value2 && reg_overlap_mentioned_p (op, cc_status.value2))
-    cc_status.value2 = 0;
-}
diff --git a/gcc/config/pyr/pyr.h b/gcc/config/pyr/pyr.h
deleted file mode 100755
index e5ffcb8..0000000
--- a/gcc/config/pyr/pyr.h
+++ /dev/null
@@ -1,1506 +0,0 @@
-/* Definitions of target machine parameters for GNU compiler,
-   for Pyramid 90x, 9000, and MIServer Series.
-   Copyright (C) 1989, 1995, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/*
- * If you're going to change this, and you haven't already,
- * you should get and read
- * 	``OSx Operating System Porting Guide'',
- *	  publication number 4100-0066-A
- *	  Revision A
- *	  Pyramid Technology Corporation.
- *
- * or whatever the most recent version is.  In any case, page and
- * section number references given herein refer to this document.
- *
- *  The instruction table for gdb lists the available insns and
- *  the valid addressing modes.
- *
- *  Any other information on the Pyramid architecture is proprietary
- *  and hard to get. (Pyramid cc -S and adb are also useful.)
- *
- */
-
-/*** Run-time compilation parameters selecting different hardware subsets. ***/
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dpyr -Dunix -Asystem(unix) -Acpu(pyr) -Amachine(pyr)"
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fprintf (stderr, " (pyr)");
-
-extern int target_flags;
-
-/* Nonzero if compiling code that Unix assembler can assemble.  */
-#define TARGET_UNIX_ASM (target_flags & 1)
-
-/* Implement stdarg in the same fashion used on all other machines.  */
-#define TARGET_GNU_STDARG   (target_flags & 2)
-
-/* Compile using RETD to pop off the args.
-   This will not work unless you use prototypes at least
-   for all functions that can take varying numbers of args.
-   This contravenes the Pyramid calling convention, so we don't
-   do it yet.  */
-
-#define TARGET_RETD (target_flags & 4)
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.
-
-   -mgnu will be useful if we ever have GAS on a pyramid.  */
-
-#define TARGET_SWITCHES  \
-  { {"unix", 1},  		\
-    {"gnu", -1},  		\
-    {"gnu-stdarg", 2},		\
-    {"nognu-stdarg", -2},	\
-    {"retd", 4},		\
-    {"no-retd", -4},		\
-    { "", TARGET_DEFAULT}}
-
-/* Default target_flags if no switches specified.
-
-   (equivalent to "-munix -mindex -mgnu-stdarg")  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (1 + 2)
-#endif
-
-/* Make GCC agree with types.h.  */
-#ifdef	SIZE_TYPE
-#undef	SIZE_TYPE
-#endif
-#define	SIZE_TYPE	"unsigned int"
-
-/* Assembler does not permit $ in labels */
-
-#define	NO_DOLLAR_IN_LABEL
-
-/* Maybe it doesn't permit dot either.  */
-#define NO_DOT_IN_LABEL
-
-/* Never allow $ in identifiers */
-
-#define DOLLARS_IN_IDENTIFIERS 0
-
-/*** Target machine storage layout ***/
-
-/* Define this to non-zero if most significant bit is lowest
-   numbered in instructions that operate on numbered bit-fields.
-   This is not true on the pyramid.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this to non-zero if most significant byte of a word is
-   the lowest numbered.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this to non-zero if most significant word of a multiword
-   number is the lowest numbered.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 32
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 32
-
-/* Specified types of bitfields affect alignment of those fields
-   and of the structure as a whole.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Make strings word-aligned so strcpy from constants will be faster. 
-   Pyramid documentation says the best alignment is to align
-   on the size of a cache line, which is 32 bytes.
-   Newer pyrs have single insns that do strcmp() and strcpy(), so this
-   may not actually win anything.   */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  (TREE_CODE (EXP) == STRING_CST	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/*** Standard register usage.  ***/
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  */
-
-/* Nota Bene:
-   Pyramids have 64 addressable 32-bit registers, arranged as four
-   groups of sixteen registers each. Pyramid names the groups
-   global, parameter, local, and temporary.
-
-   The sixteen global registers are fairly conventional; the last
-   four are overloaded with a PSW, frame pointer, stack pointer, and pc.
-   The non-dedicated global registers used to be reserved for Pyramid
-   operating systems, and still have cryptic and undocumented uses for
-   certain library calls.  We do not use global registers gr0 through
-   gr11.
-
-   The parameter, local, and temporary registers provide register
-   windowing.  Each procedure call has its own set of these 48
-   registers, which constitute its call frame. (These frames are
-   not allocated on the conventional stack, but contiguously
-   on a separate stack called the control stack.)
-   Register windowing is a facility whereby the temporary registers
-   of frame n become the parameter registers of frame n+1, viz.:
-
-                                      0         15 0         15 0         15
-                                     +------------+------------+------------+
-frame n+1                            |            |            |            |
-                                     +------------+------------+------------+
-                                        Parameter     Local       Temporary
-
-                                          ^
-                                          | These 16 regs are the same.
-                                          v
-
-            0         15 0         15 0         15
-           +------------+------------+------------+
-frame n    |            |            |            |
-           +------------+------------+------------+
-             Parameter     Local       Temporary
-
-   New frames are automatically allocated on the control stack by the
-   call instruction and de-allocated by the return insns "ret" and
-   "retd".  The control-stack grows contiguously upward from a
-   well-known address in memory; programs are free to allocate
-   a variable sized, conventional frame on the data stack, which
-   grows downwards in memory from just below the control stack.
-
-   Temporary registers are used for parameter passing, and are not
-   preserved across calls.  TR0 through TR11 correspond to
-   gcc's ``input'' registers; PR0 through TR11 the ``output''
-   registers. The call insn stores the PC and PSW in PR14 and PR15 of
-   the frame it creates; the return insns restore these into the PC
-   and PSW. The same is true for interrupts; TR14 and TR15 of the
-   current frame are reserved and should never be used, since an
-   interrupt may occur at any time and clobber them.
-
-   An interesting quirk is the ability to take the address of a
-   variable in a windowed register.  This done by adding the memory
-   address of the base of the current window frame, to the offset
-   within the frame of the desired register.  The resulting address
-   can be treated just like any other pointer; if a quantity is stored
-   into that address, the appropriate register also changes.
-   GCC does not, and according to RMS will not, support this feature,
-   even though some programs rely on this (mis)feature.
- */
-
-#define PYR_GREG(n) (n)
-#define PYR_PREG(n) (16+(n))
-#define PYR_LREG(n) (32+(n))
-#define PYR_TREG(n) (48+(n))
-
-/* Define this macro if the target machine has "register windows".  This
-   C expression returns the register number as seen by the called function
-   corresponding to register number OUT as seen by the calling function.
-   Return OUT if register number OUT is not an outbound register.  */
-
-#define INCOMING_REGNO(OUT) \
- (((OUT) < 48 || (OUT) > 63) ? (OUT) : (OUT) - 32)
-
-/* Define this macro if the target machine has "register windows".  This
-   C expression returns the register number as seen by the calling function
-   corresponding to register number IN as seen by the called function.
-   Return IN if register number IN is not an inbound register.  */
-
-#define OUTGOING_REGNO(IN) \
- (((IN) < 15 || (IN) > 31) ? (IN) : (IN) + 32)
-
-#define FIRST_PSEUDO_REGISTER 64
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   On the pyramid, these are LOGPSW, SP, and PC.  */
-
-#define FIXED_REGISTERS \
-  {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,	\
-   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,	\
-   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	\
-   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS \
-  {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,	\
-   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,	\
-   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 	\
-   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
-
-/* #define DEFAULT_CALLER_SAVES */
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-   On the pyramid, all registers are one word long.  */
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On the pyramid, all registers can hold all modes.  */
-
-/* -->FIXME: this is not the case for 64-bit quantities in tr11/12 through
-   --> TR14/15.  This should be fixed,  but to do it correctly, we also
-   --> need to fix MODES_TIEABLE_P. Yuk.  We ignore this, since GCC should
-   --> do the "right" thing due to FIXED_REGISTERS. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) 1
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* Pyramid pc is overloaded on global register 15.  */
-#define PC_REGNUM PYR_GREG(15)
-
-/* Register to use for pushing function arguments.
-   --> on Pyramids, the data stack pointer. */
-#define STACK_POINTER_REGNUM PYR_GREG(14)
-
-/* Base register for access to local variables of the function.
-   Pyramid uses CFP (GR13) as both frame pointer and argument pointer. */
-#define FRAME_POINTER_REGNUM 13 /* pyr cpp fails on PYR_GREG(13) */
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.
-
-   Setting this to 1 can't break anything.  Since the Pyramid has
-   register windows, I don't know if defining this to be zero can
-   win anything.  It could changed later, if it wins. */
-#define FRAME_POINTER_REQUIRED 1
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 13 /* PYR_GREG(13) */
-
-/* Register in which static-chain is passed to a function.  */
-/* If needed, Pyramid says to use temporary register 12. */
-#define STATIC_CHAIN_REGNUM PYR_TREG(12)
-
-/* If register windows are used, STATIC_CHAIN_INCOMING_REGNUM
-   is the register number as seen by the called function, while
-   STATIC_CHAIN_REGNUM is the register number as seen by the calling
-   function. */
-#define STATIC_CHAIN_INCOMING_REGNUM PYR_PREG(12)
-
-/* Register in which address to store a structure value
-   is passed to a function.
-   On a Pyramid, this is temporary register 0 (TR0).   */
-
-#define STRUCT_VALUE_REGNUM PYR_TREG(0)
-#define STRUCT_VALUE_INCOMING_REGNUM PYR_PREG(0)
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-/* The pyramid has only one kind of registers, so NO_REGS and ALL_REGS
-   are the only classes.  */
-
-enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Since GENERAL_REGS is the same class as ALL_REGS,
-   don't give it a different class number; just make it an alias.  */
-
-#define GENERAL_REGS ALL_REGS
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS {{0,0}, {0xffffffff,0xffffffff}}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) ALL_REGS
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define BASE_REG_CLASS ALL_REGS
-#define INDEX_REG_CLASS ALL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) NO_REGS
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)  (CLASS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-/* On the pyramid, this is always the size of MODE in words,
-   since all registers are the same size.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   --> For the Pyramid, 'I' can be used for the 6-bit signed integers
-   --> (-32 to 31) allowed as immediate short operands in many
-   --> instructions. 'J' cane be used for any value that doesn't fit
-   --> in 6 bits.  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'I' ? (VALUE) >= -32 && (VALUE) < 32 : \
-   (C) == 'J' ? (VALUE) < -32 || (VALUE) >= 32 : \
-   (C) == 'K' ? (VALUE) == 0xff || (VALUE) == 0xffff : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
-
-
-/*** Stack layout; function entry, exit and calling.  ***/
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-/* FIXME: this used to work when defined as 0.  But that makes gnu
-   stdargs clobber the first arg.  What gives?? */
-#define STARTING_FRAME_OFFSET 0
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.
-
-   The Pyramid OSx Porting Guide says we are never to do this;
-   using RETD in this way violates the Pyramid calling convention.
-   We may nevertheless provide this as an option.   */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE)   \
-  ((TARGET_RETD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE)	\
-    && (TYPE_ARG_TYPES (FUNTYPE) == 0				\
-	|| (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE)))	\
-	    == void_type_node)))				\
-   ? (SIZE) : 0)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-/* --> Pyramid has register windows.
-   --> The caller sees the return value is in TR0(/TR1) regardless of
-   --> its type.   */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), PYR_TREG(0))
-
-/* --> but the callee has to leave it in PR0(/PR1) */
-
-#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC)	\
-  gen_rtx (REG, TYPE_MODE (VALTYPE), PYR_PREG(0))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-/* --> On Pyramid the return value is in TR0/TR1 regardless.  */
-
-#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, PYR_TREG(0))
-
-/* Define this if PCC uses the nonreentrant convention for returning
-   structure and union values.  */
-
-#define PCC_STATIC_STRUCT_RETURN
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.
-
-  On the Pyramid, TR0 is the only register thus used.   */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == PYR_TREG(0))
-
-/* 1 if N is a possible register number for function argument passing.
-   On the Pyramid, the first twelve temporary registers are available.  */
-
-/* FIXME FIXME FIXME
-   it's not clear whether this macro should be defined from the point
-   of view of the caller or the callee.  Since it's never actually used
-   in GNU CC, the point is somewhat moot :-).
-
-   This definition is consistent with register usage in the md's for
-   other register-window architectures (sparc and spur).
- */
-#define FUNCTION_ARG_REGNO_P(N) ((PYR_TREG(0) <= (N)) && ((N) <= PYR_TREG(11)))
-
-/*** Parameter passing: FUNCTION_ARG and FUNCTION_INCOMING_ARG ***/
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On Pyramids, each parameter is passed either completely on the stack
-   or completely in registers.  No parameter larger than a double may
-   be passed in a register.  Also, no struct or union may be passed in
-   a register, even if it would fit.
-
-    So parameters are not necessarily passed "consecutively".
-    Thus we need a vector data type: one element to record how many
-    parameters have been passed in registers and on the stack,
-    respectively.
-
-    ((These constraints seem like a gross waste of registers. But if we
-    ignore the constraint about structs & unions, we won`t be able to
-    freely mix gcc-compiled code and pyr cc-compiled code.  It looks
-    like better argument passing conventions, and a machine-dependent
-    flag to enable them, might be a win.))   */
-
-
-#define CUMULATIVE_ARGS int
-
-/* Define the number of registers that can hold parameters.
-   This macro is used only in other macro definitions below.   */
-#define NPARM_REGS 12
-
-/* Decide whether or not a parameter can be put in a register.
-   (We may still have problems with libcalls. GCC doesn't seem
-   to know about anything more than the machine mode.  I trust
-   structures are never passed to a libcall...
-
-   If compiling with -mgnu-stdarg, this definition should make
-   functions using the gcc-supplied stdarg, and calls to such
-   functions (declared with an arglist ending in"..."),  work.
-   But such fns won't be able to call pyr cc-compiled
-   varargs fns (eg, printf(), _doprnt.)
-
-   If compiling with -mnognu-stdarg, this definition should make
-   calls to pyr cc-compiled functions work.  Functions using
-   the gcc-supplied stdarg will be utterly broken.
-   There will be no better solution until RMS can be persuaded that
-   one is needed.
-
-   This macro is used only in other macro definitions below.
-   (well, it may be used in pyr.c, because the damn pyramid cc
-   can't handle the macro definition of PARAM_SAFE_FOR_REG_P !   */
-
-
-#define INNER_PARAM_SAFE_HELPER(TYPE) \
- ((TARGET_GNU_STDARG ? (! TREE_ADDRESSABLE ((tree)TYPE)): 1)	\
-   && (TREE_CODE ((tree)TYPE) != RECORD_TYPE)			\
-   && (TREE_CODE ((tree)TYPE) != UNION_TYPE))
-
-#ifdef __GNUC__
-#define PARAM_SAFE_HELPER(TYPE) \
-  INNER_PARAM_SAFE_HELPER((TYPE))
-#else
-extern int inner_param_safe_helper();
-#define PARAM_SAFE_HELPER(TYPE) \
-  inner_param_safe_helper((tree)(TYPE))
-#endif
-
-/* Be careful with the expression (long) (TYPE) == 0.
-   Writing it in more obvious/correct forms makes the Pyr cc
-   dump core!   */
-#define PARAM_SAFE_FOR_REG_P(MODE, TYPE, NAMED) \
-  (((MODE) != BLKmode)				\
-   && ((TARGET_GNU_STDARG) ? (NAMED) : 1)	\
-   && ((((long)(TYPE))==0) || PARAM_SAFE_HELPER((TYPE))))
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.   */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
-  ((CUM) = (FNTYPE && !flag_pcc_struct_return		\
-	    && aggregate_value_p (TREE_TYPE (FNTYPE))))
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis). */
-
-#define FUNCTION_ARG_HELPER(CUM, MODE, TYPE, NAMED) \
-(PARAM_SAFE_FOR_REG_P(MODE,TYPE,NAMED)				\
- ? (NPARM_REGS >= ((CUM)					\
-		   + ((MODE) == BLKmode				\
-		      ? (int_size_in_bytes (TYPE) + 3) / 4	\
-		      : (GET_MODE_SIZE (MODE) + 3) / 4))	\
-    ? gen_rtx (REG, (MODE), PYR_TREG(CUM))			\
-    : 0)							\
- : 0)
-#ifdef __GNUC__
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-	FUNCTION_ARG_HELPER(CUM, MODE, TYPE, NAMED)
-#else
-/*****************  Avoid bug in Pyramid OSx compiler... ******************/
-#define FUNCTION_ARG  (rtx) pyr_function_arg
-extern void* pyr_function_arg ();
-#endif
-
-/* Define where a function finds its arguments.
-   This is different from FUNCTION_ARG because of register windows.  */
-
-#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
-(PARAM_SAFE_FOR_REG_P(MODE,TYPE,NAMED)			\
- ? (NPARM_REGS >= ((CUM)				\
-	   + ((MODE) == BLKmode				\
-	      ? (int_size_in_bytes (TYPE) + 3) / 4	\
-	      : (GET_MODE_SIZE (MODE) + 3) / 4))	\
-    ? gen_rtx (REG, (MODE), PYR_PREG(CUM))		\
-    : 0)						\
- : 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM,MODE,TYPE,NAMED)  \
-((CUM)	+=  (PARAM_SAFE_FOR_REG_P(MODE,TYPE,NAMED)	\
-	     ? ((MODE) != BLKmode			\
-		? (GET_MODE_SIZE (MODE) + 3) / 4	\
-		: (int_size_in_bytes (TYPE) + 3) / 4)	\
-	     : 0))
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#if FRAME_POINTER_REQUIRED
-
-/* We always have frame pointers */
-
-/* Don't set up a frame pointer if it's not referenced.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) \
-{									\
-  int _size = (SIZE) + current_function_pretend_args_size;		\
-  if (_size + current_function_args_size != 0				\
-      || current_function_calls_alloca)					\
-    {									\
-      fprintf (FILE, "\tadsf $%d\n", _size);				\
-      if (current_function_pretend_args_size > 0)			\
-      fprintf (FILE, "\tsubw $%d,cfp\n",				\
-	  current_function_pretend_args_size);				\
-    }									\
-}
-
-#else /* !FRAME_POINTER_REQUIRED */
-
-/* Don't set up a frame pointer if `frame_pointer_needed' tells us
-   there is no need.  Also, don't set up a frame pointer if it's not
-   referenced.  */
-
-/* The definition used to be broken.  Write a new one.  */
-
-#endif /* !FRAME_POINTER_REQUIRED */
-
-/* the trampoline stuff was taken from convex.h - S.P. */
-
-/* A C statement to output, on the stream FILE, assembler code for a
-   block of data that contains the constant parts of a trampoline.  This
-   code should not include a label - the label is taken care of
-   automatically.
-	We use TR12/PR12 for the static chain.
-	movew $<STATIC>,pr12	# I2R
-	jump $<func>		# S2R
- */
-#define TRAMPOLINE_TEMPLATE(FILE) \
-{ ASM_OUTPUT_INT (FILE, GEN_INT (0x2100001C));	\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0x00000000));	\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0x40000000));	\
-  ASM_OUTPUT_INT (FILE, GEN_INT (0x00000000)); }
-
-#define TRAMPOLINE_SIZE		16
-#define TRAMPOLINE_ALIGNMENT	32
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-{ emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 4)), CXT);	\
-  emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 12)), FNADDR); \
-  emit_call_insn (gen_call (gen_rtx (MEM, QImode,			\
-				     gen_rtx (SYMBOL_REF, Pmode,	\
-					      "__enable_execute_stack")), \
-			    const0_rtx));				\
-}
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   fprintf (FILE, "\tmova LP%d,tr0\n\tcall mcount\n", (LABELNO));
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.
-   Don't know if this works on Pyrs. */
-
-#if 0 /* don't do basic_block profiling yet */
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, \
-           "\tmtstw LPBX0,tr0\n\tbne LPI%d\n\tmova LP%d,TR0\n\tcall __bb_init_func\nLPI%d:\n", \
-           LABELNO, LABELNO);
-
-/* Output assembler code to increment the count associated with
-   the basic block number BLOCKNO.  Not sure how to do this on pyrs. */
-#define BLOCK_PROFILER(FILE, BLOCKNO)  \
-    fprintf (FILE, "\taddw", 4 * BLOCKNO)
-#endif /* don't do basic_block profiling yet */
-
-/* When returning from a function, the stack pointer does not matter
-   (as long as there is a frame pointer).  */
-
-/* This should return non-zero when we really set up a frame pointer.
-   Otherwise, GCC is directed to preserve sp by returning zero.  */
-extern int current_function_pretend_args_size;
-extern int current_function_args_size;
-extern int current_function_calls_alloca;
-#define EXIT_IGNORE_STACK \
-  (get_frame_size () + current_function_pretend_args_size		\
-   + current_function_args_size != 0					\
-   || current_function_calls_alloca)					\
-
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved.
-
-   On the Pyramid, FRAME_POINTER_REQUIRED is always 1, so the definition
-   of this macro doesn't matter.  But it must be defined.  */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0;
-
-/*** Addressing modes, and classification of registers for them.  ***/
-
-/* #define HAVE_POST_INCREMENT 0 */	/* pyramid has none of these */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-/* All registers except gr0 OK as index or base registers.  */
-
-#define REGNO_OK_FOR_BASE_P(regno) \
-((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
-
-#define REGNO_OK_FOR_INDEX_P(regno)  \
-((unsigned) (regno) - 1 < FIRST_PSEUDO_REGISTER - 1 \
- || reg_renumber[regno] > 0)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2     /* check MAX_REGS_PER_ADDRESS */
-
-/* 1 if X is an rtx for a constant that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) (REGNO (X) > 0)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) 1
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
-   except for CONSTANT_ADDRESS_P which is actually machine-independent.  */
-
-
-/* Go to ADDR if X is indexable -- i.e., neither indexed nor offset.  */
-#define GO_IF_INDEXABLE_ADDRESS(X, ADDR)  \
-{ register rtx xfoob = (X);						\
-  if ((CONSTANT_ADDRESS_P (xfoob))					\
-      || (GET_CODE (xfoob) == REG && (REG_OK_FOR_BASE_P (xfoob))))	\
-	  goto ADDR;							\
- }
-
-
-/* Go to label ADDR if X is a valid address that doesn't use indexing.
-   This is so if X is either a simple address, or the contents of a register
-   plus an offset.
-   This macro also gets used in output-pyramid.h in the function that
-   recognizes non-indexed operands.  */
-
-#define GO_IF_NONINDEXED_ADDRESS(X, ADDR)  \
-{									\
-  if (GET_CODE (X) == REG)						\
-      goto ADDR;							\
-  GO_IF_INDEXABLE_ADDRESS (X, ADDR);					\
-  if (GET_CODE (X) == PLUS)						\
-    { /* Handle offset(reg) represented with offset on left */		\
-      if (CONSTANT_ADDRESS_P (XEXP (X, 0)))				\
-	{ if (GET_CODE (XEXP (X, 1)) == REG				\
-	      && REG_OK_FOR_BASE_P (XEXP (X, 1)))			\
-	    goto ADDR;							\
-	 }								\
-      /* Handle offset(reg) represented with offset on right */		\
-      if (CONSTANT_ADDRESS_P (XEXP (X, 1)))				\
-	{ if (GET_CODE (XEXP (X, 0)) == REG				\
-	      && REG_OK_FOR_BASE_P (XEXP (X, 0)))			\
-	    goto ADDR;							\
-	 }								\
-     }									\
-}
-
-/* 1 if PROD is either a reg or a reg times a valid offset multiplier
-   (ie, 2, 4, or 8).
-   This macro's expansion uses the temporary variables xfoo0 and xfoo1
-   that must be declared in the surrounding context.  */
-#define INDEX_TERM_P(PROD, MODE)   \
-((GET_CODE (PROD) == REG && REG_OK_FOR_BASE_P (PROD))			\
-  || (GET_CODE (PROD) == MULT						\
-      &&								\
-      (xfoo0 = XEXP (PROD, 0), xfoo1 = XEXP (PROD, 1),			\
-       ((GET_CODE (xfoo0) == CONST_INT					\
-         && (INTVAL (xfoo0) == 1					\
-	     || INTVAL (xfoo0) == 2					\
-	     || INTVAL (xfoo0) == 4					\
-	     || INTVAL (xfoo0) == 8)					\
-         && GET_CODE (xfoo1) == REG					\
-         && REG_OK_FOR_INDEX_P (xfoo1))					\
-        ||								\
-        (GET_CODE (xfoo1) == CONST_INT					\
-	 && (INTVAL (xfoo1) == 1					\
-	     || INTVAL (xfoo1) == 2					\
-	     || INTVAL (xfoo1) == 4					\
-	     || INTVAL (xfoo1) == 8)					\
-        && GET_CODE (xfoo0) == REG					\
-        && REG_OK_FOR_INDEX_P (xfoo0))))))
-
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
-{ register rtx xone, xtwo, xfoo0, xfoo1;				\
-  GO_IF_NONINDEXED_ADDRESS (X, ADDR);					\
-  if (GET_CODE (X) == PLUS)						\
-    {									\
-      /* Handle <address>[index] represented with index-sum outermost */\
-      xone = XEXP (X, 0);						\
-      xtwo = XEXP (X, 1);						\
-      if (INDEX_TERM_P (xone, MODE))					\
-	{ GO_IF_INDEXABLE_ADDRESS (xtwo, ADDR); }			\
-      /* Handle <address>[index] represented with index-sum innermost */\
-      if (INDEX_TERM_P (xtwo, MODE))					\
-	{ GO_IF_INDEXABLE_ADDRESS (xone, ADDR); }			\
-    }									\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   --> FIXME: We haven't yet figured out what optimizations are useful
-   --> on Pyramids.   */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)  {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   There don't seem to be any such modes on pyramids. */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-/*** Miscellaneous Parameters ***/
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/*#define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.
-   It's just a guess. I have no idea of insn cost on pyrs. */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.  */
-/* This is untrue for pyramid.  The cvtdw instruction generates a trap
-   for input operands that are out-of-range for a signed int.  */
-/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
-
-/* Define this macro if the preprocessor should silently ignore
-  '#sccs' directives. */
-/* #define SCCS_DIRECTIVE */
-
-/* Define this macro if the preprocessor should silently ignore
-  '#ident' directives. */
-/* #define IDENT_DIRECTIVE */
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 8
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-/* #define SLOW_ZERO_EXTEND */
-
-/* number of bits in an 'int' on target machine */
-#define INT_TYPE_SIZE 32
-
-/* 1 if byte access requires more than one instruction */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
-   few bits. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Define this macro if it is as good or better to call a constant
-   function address than to call an address kept in a register.  */
-/* #define NO_FUNCTION_CSE */
-
-/* When a prototype says `char' or `short', really pass an `int'.  */
-#define PROMOTE_PROTOTYPES
-
-/* There are no flag store insns on a pyr. */
-/* #define STORE_FLAG_VALUE */
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    if (CONST_OK_FOR_LETTER_P (INTVAL (RTX),'I')) return 0;	\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 4;							\
-  case CONST_DOUBLE:						\
-    return 6;
-
-/* A flag which says to swap the operands of certain insns
-   when they are output.  */
-extern int swap_operands;
-
-/*** Condition Code Information ***/
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  No extra ones are needed for the pyr.  */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-/* This is a very simple definition of NOTICE_UPDATE_CC.
-   Many cases can be optimized, to improve condition code usage.
-   Maybe we should handle this entirely in the md, since it complicated
-   to describe the way pyr sets cc.  */
-
-#define TRULY_UNSIGNED_COMPARE_P(X) \
-  (X == GEU || X == GTU || X == LEU || X == LTU)
-#define CC_VALID_FOR_UNSIGNED 2
-
-#define CC_STATUS_MDEP_INIT cc_status.mdep = 0
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-  notice_update_cc(EXP, INSN)
-
-/*** Output of Assembler Code ***/
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(FILE) \
-  fprintf (FILE, ((TARGET_UNIX_ASM)? "" : "#NO_APP\n"));
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ((TARGET_UNIX_ASM) ? "" : "#APP\n")
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ((TARGET_UNIX_ASM) ? "" : "#NO_APP\n")
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"gr0", "gr1", "gr2", "gr3", "gr4", "gr5", "gr6", "gr7", "gr8", \
- "gr9", "gr10", "gr11", "logpsw", "cfp", "sp", "pc", \
- "pr0", "pr1", "pr2", "pr3", "pr4", "pr5", "pr6", "pr7", \
- "pr8", "pr9", "pr10", "pr11", "pr12", "pr13", "pr14", "pr15", \
- "lr0", "lr1", "lr2", "lr3", "lr4", "lr5", "lr6", "lr7", \
- "lr8", "lr9", "lr10", "lr11", "lr12", "lr13", "lr14", "lr15", \
- "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
- "tr8", "tr9", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"}
-
-/* How to renumber registers for dbx and gdb.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Our preference is for dbx rather than sdb.
-   Yours may be different. */
-#define DBX_DEBUGGING_INFO
-/* #define SDB_DEBUGGING_INFO */
-
-/* Don't use the `xsfoo;' construct in DBX output; this system
-   doesn't support it.  */
-
-#define DBX_NO_XREFS 1
-
-/* Do not break .stabs pseudos into continuations.  */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* This is the char to use for continuation (in case we need to turn
-   continuation back on).  */
-
-#define DBX_CONTIN_CHAR '?'
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-  fprintf (FILE, "\t.double 0d%.20e\n", (VALUE))
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-  fprintf (FILE, "\t.float 0f%.20e\n", (VALUE))
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.half "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tsubw $4,sp\n\tmovw %s,(sp)\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tmovw (sp),%s\n\taddw $4,sp\n", reg_names[REGNO])
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.word L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.
-
-   On Pyramids, the text segment must always be word aligned.
-   On Pyramids, .align takes only args between 2 and 5.
-  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
-  fprintf (FILE, "\t.align %d\n", (LOG) < 2 ? 2 : (LOG))
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %u\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.
-   On the Pyr, we support the conventional CODE characters:
-
-   'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
-   which are never used. */
-
-/* FIXME : should be more robust with CONST_DOUBLE. */
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names [REGNO (X) + ((CODE) == 'R')]);	\
-									\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-									\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode)	\
-    { union { double d; int i[2]; } u;					\
-      union { float f; int i; } u1;					\
-      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
-      u1.f = u.d;							\
-      if (CODE == 'f')							\
-        fprintf (FILE, "$0f%.0e", u1.f);				\
-      else								\
-        fprintf (FILE, "$0x%x", u1.i); }				\
-									\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)	\
-    { union { double d; int i[2]; } u;					\
-      u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);	\
-      fprintf (FILE, "$0d%.20e", u.d); }				\
-									\
-  else if (CODE == 'N')							\
-    switch (GET_CODE (X))						\
-      {									\
-      case EQ:	fputs ("eq", FILE);	break;				\
-      case NE:	fputs ("ne", FILE);	break;				\
-      case GT:								\
-      case GTU:	fputs ("gt", FILE);	break;				\
-      case LT:								\
-      case LTU:	fputs ("lt", FILE);	break;				\
-      case GE:								\
-      case GEU:	fputs ("ge", FILE);	break;				\
-      case LE:								\
-      case LEU:	fputs ("le", FILE);	break;				\
-      }									\
-									\
-  else if (CODE == 'C')							\
-    switch (GET_CODE (X))						\
-      {									\
-      case EQ:	fputs ("ne", FILE);	break;				\
-      case NE:	fputs ("eq", FILE);	break;				\
-      case GT:								\
-      case GTU:	fputs ("le", FILE);	break;				\
-      case LT:								\
-      case LTU:	fputs ("ge", FILE);	break;				\
-      case GE:								\
-      case GEU:	fputs ("lt", FILE);	break;				\
-      case LE:								\
-      case LEU:	fputs ("gt", FILE);	break;				\
-      }									\
-									\
-  else if (CODE == 'R')							\
-    switch (GET_CODE (X))						\
-      {									\
-      case EQ:	fputs ("eq", FILE);	break;				\
-      case NE:	fputs ("ne", FILE);	break;				\
-      case GT:								\
-      case GTU:	fputs ("lt", FILE);	break;				\
-      case LT:								\
-      case LTU:	fputs ("gt", FILE);	break;				\
-      case GE:								\
-      case GEU:	fputs ("le", FILE);	break;				\
-      case LE:								\
-      case LEU:	fputs ("ge", FILE);	break;				\
-      }									\
-									\
-  else { putc ('$', FILE); output_addr_const (FILE, X); }		\
-}
-
-/* Print a memory operand whose address is ADDR, on file FILE.  */
-/* This is horrendously complicated.  */
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{									\
-  register rtx reg1, reg2, breg, ireg;					\
-  register rtx addr = ADDR;						\
-  rtx offset, scale;							\
- retry:									\
-  switch (GET_CODE (addr))						\
-    {									\
-    case MEM:								\
-      fprintf (stderr, "bad Mem "); debug_rtx (addr);			\
-      addr = XEXP (addr, 0);						\
-      abort ();								\
-    case REG:								\
-      fprintf (FILE, "(%s)", reg_names [REGNO (addr)]);			\
-      break;								\
-    case PLUS:								\
-      reg1 = 0;	reg2 = 0;						\
-      ireg = 0;	breg = 0;						\
-      offset = 0;							\
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0))				\
-	  || GET_CODE (XEXP (addr, 0)) == MEM)				\
-	{								\
-	  offset = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))			\
-	       || GET_CODE (XEXP (addr, 1)) == MEM)			\
-	{								\
-	  offset = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) != PLUS) ;					\
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 0)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 0);					\
-	  addr = XEXP (addr, 1);					\
-	}								\
-      else if (GET_CODE (XEXP (addr, 1)) == REG)			\
-	{								\
-	  reg1 = XEXP (addr, 1);					\
-	  addr = XEXP (addr, 0);					\
-	}								\
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)		\
-	{								\
-	  if (reg1 == 0)						\
-	    reg1 = addr;						\
-          else								\
-	    reg2 = addr;						\
-	  addr = 0;							\
-	}								\
-      if (offset != 0) 							\
-	{								\
-	  if (addr != 0) {						\
-	    fprintf (stderr, "\nBad addr "); debug_rtx (addr);		\
-	    abort ();}							\
-	  addr = offset;						\
-	}								\
-      if (reg1 != 0 && GET_CODE (reg1) == MULT)				\
-	{ breg = reg2; ireg = reg1; }					\
-      else if (reg2 != 0 && GET_CODE (reg2) == MULT)			\
-	{ breg = reg1; ireg = reg2; }					\
-      else if (reg2 != 0 || GET_CODE (addr) == MEM)			\
-	{ breg = reg2; ireg = reg1; }					\
-      else								\
-	{ breg = reg1; ireg = reg2; }					\
-      if (addr != 0)							\
-	output_address (offset);					\
-      if (breg != 0)							\
-	{ if (GET_CODE (breg) != REG)					\
-	    {								\
-	      fprintf (stderr, "bad Breg"); debug_rtx (addr);		\
-	      abort ();							\
-	    }								\
-	  fprintf (FILE, "(%s)", reg_names[REGNO (breg)]); }		\
-      if (ireg != 0)							\
-	{								\
-	  if (GET_CODE (ireg) == MULT)					\
-	    {								\
-	      scale = XEXP (ireg, 1);					\
-	      ireg = XEXP (ireg, 0);					\
-	      if (GET_CODE (ireg) != REG)				\
-	        { register rtx tem;					\
-		  tem = ireg; ireg = scale; scale = tem;		\
-	        }							\
- 	      if (GET_CODE (ireg) != REG) {				\
-		      fprintf (stderr, "bad idx "); debug_rtx (addr);	\
-		abort (); }						\
-	      if ((GET_CODE (scale) == CONST_INT) && (INTVAL(scale) >= 1))\
-		fprintf (FILE, "[%s*0x%x]", reg_names[REGNO (ireg)],	\
-			 INTVAL(scale));				\
-	      else							\
-		fprintf (FILE, "[%s*1]", reg_names[REGNO (ireg)]);	\
- 	    } 								\
-	  else if (GET_CODE (ireg) == REG)				\
-	      fprintf (FILE, "[%s*1]", reg_names[REGNO (ireg)]);	\
-	  else								\
-	    {								\
-	      fprintf (stderr, "Not indexed at all!"); debug_rtx (addr);\
-	      abort ();							\
-	    }								\
-	 }								\
-       break;								\
-    default:								\
-      output_addr_const (FILE, addr);					\
-   }									\
-}
diff --git a/gcc/config/pyr/pyr.md b/gcc/config/pyr/pyr.md
deleted file mode 100755
index c1d440a..0000000
--- a/gcc/config/pyr/pyr.md
+++ /dev/null
@@ -1,1360 +0,0 @@
-;; GNU C machine description for Pyramid 90x, 9000, MIServer Series
-;; Copyright (C) 1989, 1990, 1995, 1997 Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;; Instruction patterns.  When multiple patterns apply,
-;; the first one in the file is chosen.
-;;
-;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
-;;
-;; cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;; updates for most instructions.
-
-;; These comments are mostly obsolete.  Written for gcc version 1.XX.
-;; * Try using define_insn instead of some peepholes in more places.
-;; * Set REG_NOTES:REG_EQUIV for cvt[bh]w loads.  This would make the
-;;   backward scan in sign_extend needless.
-;; * Match (pc) (label_ref) case in peephole patterns.
-;; * Should optimize
-;;   "cmpX op1,op2;  b{eq,ne} LY;  ucmpX op1.op2;  b{lt,le,gt,ge} LZ"
-;;   to
-;;   "ucmpX op1,op2;  b{eq,ne} LY;  b{lt,le,gt,ge} LZ"
-;;   by pre-scanning insn and running notice_update_cc for them.
-;; * Is it necessary to do copy_rtx in the test and compare patterns?
-;; * Fix true frame pointer omission.
-;; * Make the jump tables contain branches, not addresses!  This would
-;;   save us one instruction.
-;; * Could the complicated scheme for compares be simplified, if we had
-;;   no named cmpqi or cmphi patterns, and instead anonymous patterns for
-;;   the less-than-word compare cases pyr can handle???
-;; * The jump insn seems to accept more than just IR addressing.  Would
-;;   we win by telling GCC?  Or can we use movw into the global reg which
-;;   is a synonym for pc?
-;; * More DImode patterns.
-;; * Scan backwards in "zero_extendhisi2", "zero_extendqisi2" to find out
-;;   if the extension can be omitted.
-;; * "divmodsi" with Pyramid "ediv" insn.  Is it possible in rtl??
-;; * Would "rcsp tmpreg; u?cmp[bh] op1_regdispl(tmpreg),op2" win in
-;;   comparison with the two extensions and single test generated now?
-;;   The rcsp insn could be expanded, and moved out of loops by the
-;;   optimizer, making 1 (64 bit) insn of 3 (32 bit) insns in loops.
-;;   The rcsp insn could be followed by an add insn, making non-displacement
-;;   IR addressing sufficient.
-
-;______________________________________________________________________
-;
-;	Test and Compare Patterns.
-;______________________________________________________________________
-
-; The argument for the rather complicated test and compare expansion
-; scheme, is the irregular pyramid instructions for these operations.
-; 1) Pyramid has different signed and unsigned compares.  2) HImode
-; and QImode integers are memory-memory and immediate-memory only.  3)
-; Unsigned HImode compares doesn't exist.  4) Only certain
-; combinations of addresses are allowed for memory-memory compares.
-; Whenever necessary, in order to fulfill these addressing
-; constraints, the compare operands are swapped.
-
-(define_expand "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "general_operand" ""))]
-  "" "operands[0] = force_reg (SImode, operands[0]);")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:SI 0 "memory_operand" "m")
-		 (match_operand:SI 1 "memory_operand" "m")))]
-  "weird_memory_memory (operands[0], operands[1])"
-  "*
-{
-  rtx br_insn = NEXT_INSN (insn);
-  RTX_CODE br_code;
-
-  if (GET_CODE (br_insn) != JUMP_INSN)
-    abort();
-  br_code =  GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));
-
-  weird_memory_memory (operands[0], operands[1]);
-
-  if (swap_operands)
-    {
-      cc_status.flags = CC_REVERSED;
-      if (TRULY_UNSIGNED_COMPARE_P (br_code))
-	{
-	  cc_status.mdep = CC_VALID_FOR_UNSIGNED;
-	  return \"ucmpw %0,%1\";
-	}
-      return \"cmpw %0,%1\";
-    }
-
-  if (TRULY_UNSIGNED_COMPARE_P (br_code))
-    {
-      cc_status.mdep = CC_VALID_FOR_UNSIGNED;
-      return \"ucmpw %1,%0\";
-    }
-  return \"cmpw %1,%0\";
-}")
-
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "r,g")
-		 (match_operand:SI 1 "general_operand" "g,r")))]
-  ""
-  "*
-{
-  rtx br_insn = NEXT_INSN (insn);
-  RTX_CODE br_code;
-
-  if (GET_CODE (br_insn) != JUMP_INSN)
-    abort();
-  br_code =  GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));
-
-  if (which_alternative != 0)
-    {
-      cc_status.flags = CC_REVERSED;
-      if (TRULY_UNSIGNED_COMPARE_P (br_code))
-	{
-	  cc_status.mdep = CC_VALID_FOR_UNSIGNED;
-	  return \"ucmpw %0,%1\";
-	}
-      return \"cmpw %0,%1\";
-    }
-
-  if (TRULY_UNSIGNED_COMPARE_P (br_code))
-    {
-      cc_status.mdep = CC_VALID_FOR_UNSIGNED;
-      return \"ucmpw %1,%0\";
-    }
-  return \"cmpw %1,%0\";
-}")
-
-(define_insn ""
-  [(set (cc0)
-	(match_operand:SI 0 "nonimmediate_operand" "r"))]
-  ""
-  "*
-{
-#if 0
-  cc_status.flags |= CC_NO_OVERFLOW;
-  return \"cmpw $0,%0\";
-#endif
-  rtx br_insn = NEXT_INSN (insn);
-  RTX_CODE br_code;
-
-  if (GET_CODE (br_insn) != JUMP_INSN)
-    abort();
-  br_code =  GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));
-
-  if (TRULY_UNSIGNED_COMPARE_P (br_code))
-    {
-      cc_status.mdep = CC_VALID_FOR_UNSIGNED;
-      return \"ucmpw $0,%0\";
-    }
-  return \"mtstw %0,%0\";
-}")
-
-(define_expand "cmphi"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "nonimmediate_operand" "")
-		 (match_operand:HI 1 "general_operand" "")))]
-  ""
-  "
-{
-  extern rtx test_op0, test_op1;  extern enum machine_mode test_mode;
-  test_op0 = copy_rtx (operands[0]);
-  test_op1 = copy_rtx (operands[1]);
-  test_mode = HImode;
-  DONE;
-}")
-
-(define_expand "tsthi"
-  [(set (cc0)
-	(match_operand:HI 0 "nonimmediate_operand" ""))]
-  ""
-  "
-{
-  extern rtx test_op0;  extern enum machine_mode test_mode;
-  test_op0 = copy_rtx (operands[0]);
-  test_mode = HImode;
-  DONE;
-}")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:HI 0 "memory_operand" "m")
-		 (match_operand:HI 1 "memory_operand" "m")))]
-  "(!TRULY_UNSIGNED_COMPARE_P (GET_CODE (XEXP (SET_SRC (PATTERN (NEXT_INSN (insn))), 0))))
-   && weird_memory_memory (operands[0], operands[1])"
-  "*
-{
-  rtx br_insn = NEXT_INSN (insn);
-
-  if (GET_CODE (br_insn) != JUMP_INSN)
-    abort();
-
-  weird_memory_memory (operands[0], operands[1]);
-
-  if (swap_operands)
-    {
-      cc_status.flags = CC_REVERSED;
-      return \"cmph %0,%1\";
-    }
-
-  return \"cmph %1,%0\";
-}")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:HI 0 "nonimmediate_operand" "r,m")
-		 (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
-  "(!TRULY_UNSIGNED_COMPARE_P (GET_CODE (XEXP (SET_SRC (PATTERN (NEXT_INSN (insn))), 0))))
-   && ((GET_CODE (operands[0]) == MEM) != (GET_CODE (operands[1]) == MEM))"
-  "*
-{
-  rtx br_insn = NEXT_INSN (insn);
-
-  if (GET_CODE (br_insn) != JUMP_INSN)
-    abort();
-
-  if (which_alternative != 0)
-    {
-      cc_status.flags = CC_REVERSED;
-      return \"cmph %0,%1\";
-    }
-
-  return \"cmph %1,%0\";
-}")
-
-(define_expand "cmpqi"
-  [(set (cc0)
-	(compare (match_operand:QI 0 "nonimmediate_operand" "")
-		 (match_operand:QI 1 "general_operand" "")))]
-  ""
-  "
-{
-  extern rtx test_op0, test_op1;  extern enum machine_mode test_mode;
-  test_op0 = copy_rtx (operands[0]);
-  test_op1 = copy_rtx (operands[1]);
-  test_mode = QImode;
-  DONE;
-}")
-
-(define_expand "tstqi"
-  [(set (cc0)
-	(match_operand:QI 0 "nonimmediate_operand" ""))]
-  ""
-  "
-{
-  extern rtx test_op0;  extern enum machine_mode test_mode;
-  test_op0 = copy_rtx (operands[0]);
-  test_mode = QImode;
-  DONE;
-}")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:QI 0 "memory_operand" "m")
-		 (match_operand:QI 1 "memory_operand" "m")))]
-  "weird_memory_memory (operands[0], operands[1])"
-  "*
-{
-  rtx br_insn = NEXT_INSN (insn);
-  RTX_CODE br_code;
-
-  if (GET_CODE (br_insn) != JUMP_INSN)
-    abort();
-  br_code =  GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));
-
-  weird_memory_memory (operands[0], operands[1]);
-
-  if (swap_operands)
-    {
-      cc_status.flags = CC_REVERSED;
-      if (TRULY_UNSIGNED_COMPARE_P (br_code))
-	{
-	  cc_status.mdep = CC_VALID_FOR_UNSIGNED;
-	  return \"ucmpb %0,%1\";
-	}
-      return \"cmpb %0,%1\";
-    }
-
-  if (TRULY_UNSIGNED_COMPARE_P (br_code))
-    {
-      cc_status.mdep = CC_VALID_FOR_UNSIGNED;
-      return \"ucmpb %1,%0\";
-    }
-  return \"cmpb %1,%0\";
-}")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:QI 0 "nonimmediate_operand" "r,m")
-		 (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
-  "((GET_CODE (operands[0]) == MEM) != (GET_CODE (operands[1]) == MEM))"
-  "*
-{
-  rtx br_insn = NEXT_INSN (insn);
-  RTX_CODE br_code;
-
-  if (GET_CODE (br_insn) != JUMP_INSN)
-    abort();
-  br_code =  GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));
-
-  if (which_alternative != 0)
-    {
-      cc_status.flags = CC_REVERSED;
-      if (TRULY_UNSIGNED_COMPARE_P (br_code))
-	{
-	  cc_status.mdep = CC_VALID_FOR_UNSIGNED;
-	  return \"ucmpb %0,%1\";
-	}
-      return \"cmpb %0,%1\";
-    }
-
-  if (TRULY_UNSIGNED_COMPARE_P (br_code))
-    {
-      cc_status.mdep = CC_VALID_FOR_UNSIGNED;
-      return \"ucmpb %1,%0\";
-    }
-  return \"cmpb %1,%0\";
-}")
-
-(define_expand "bgt"
-  [(set (pc) (if_then_else (gt (cc0) (const_int 0))
-			   (label_ref (match_operand 0 "" "")) (pc)))]
-  "" "extend_and_branch (SIGN_EXTEND);")
-
-(define_expand "blt"
-  [(set (pc) (if_then_else (lt (cc0) (const_int 0))
-			   (label_ref (match_operand 0 "" "")) (pc)))]
-  "" "extend_and_branch (SIGN_EXTEND);")
-
-(define_expand "bge"
-  [(set (pc) (if_then_else (ge (cc0) (const_int 0))
-			   (label_ref (match_operand 0 "" "")) (pc)))]
-  "" "extend_and_branch (SIGN_EXTEND);")
-
-(define_expand "ble"
-  [(set (pc) (if_then_else (le (cc0) (const_int 0))
-			   (label_ref (match_operand 0 "" "")) (pc)))]
-  "" "extend_and_branch (SIGN_EXTEND);")
-
-(define_expand "beq"
-  [(set (pc) (if_then_else (eq (cc0) (const_int 0))
-			   (label_ref (match_operand 0 "" "")) (pc)))]
-  "" "extend_and_branch (SIGN_EXTEND);")
-
-(define_expand "bne"
-  [(set (pc) (if_then_else (ne (cc0) (const_int 0))
-			   (label_ref (match_operand 0 "" "")) (pc)))]
-  "" "extend_and_branch (SIGN_EXTEND);")
-
-(define_expand "bgtu"
-  [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
-			   (label_ref (match_operand 0 "" "")) (pc)))]
-  "" "extend_and_branch (ZERO_EXTEND);")
-
-(define_expand "bltu"
-  [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
-			   (label_ref (match_operand 0 "" "")) (pc)))]
-  "" "extend_and_branch (ZERO_EXTEND);")
-
-(define_expand "bgeu"
-  [(set (pc) (if_then_else (geu (cc0) (const_int 0))
-			   (label_ref (match_operand 0 "" "")) (pc)))]
-  "" "extend_and_branch (ZERO_EXTEND);")
-
-(define_expand "bleu"
-  [(set (pc) (if_then_else (leu (cc0) (const_int 0))
-			   (label_ref (match_operand 0 "" "")) (pc)))]
-  "" "extend_and_branch (ZERO_EXTEND);")
-
-(define_insn "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "register_operand" "r")
-		 (match_operand:DF 1 "register_operand" "r")))]
-  ""
-  "cmpd %1,%0")
-
-(define_insn "cmpsf"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "register_operand" "r")
-		 (match_operand:SF 1 "register_operand" "r")))]
-  ""
-  "cmpf %1,%0")
-
-(define_insn "tstdf"
-  [(set (cc0)
-       	(match_operand:DF 0 "register_operand" "r"))]
-  ""
-  "mtstd %0,%0")
-
-(define_insn "tstsf"
-  [(set (cc0)
-       	(match_operand:SF 0 "register_operand" "r"))]
-  ""
-  "mtstf %0,%0")
-
-;______________________________________________________________________
-;
-;	Fixed-point Arithmetic.
-;______________________________________________________________________
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,!r")
-	(plus:SI (match_operand:SI 1 "general_operand" "%0,r")
-		 (match_operand:SI 2 "general_operand" "g,rJ")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 32
-	    ? \"subw %n2,%0\" : \"addw %2,%0\");
-  else
-    {
-      forget_cc_if_dependent (operands[0]);
-      return \"mova %a2[%1*1],%0\";
-    }
-}")
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(minus:SI (match_operand:SI 1 "general_operand" "0,g")
-		  (match_operand:SI 2 "general_operand" "g,0")))]
-  ""
-  "* return (which_alternative == 0) ? \"subw %2,%0\" : \"rsubw %1,%0\";")
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (match_operand:SI 1 "general_operand" "%0")
-		 (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "mulw %2,%0")
-
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(div:SI (match_operand:SI 1 "general_operand" "0,g")
-		(match_operand:SI 2 "general_operand" "g,0")))]
-  ""
-  "* return (which_alternative == 0) ? \"divw %2,%0\" : \"rdivw %1,%0\";")
-
-(define_insn "udivsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(udiv:SI (match_operand:SI 1 "register_operand" "0")
-		 (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "udivw %2,%0")
-
-(define_insn "modsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mod:SI (match_operand:SI 1 "register_operand" "0")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "modw %2,%0")
-
-(define_insn "umodsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(umod:SI (match_operand:SI 1 "register_operand" "0")
-		 (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "umodw %2,%0")
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "mnegw %1,%0")
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "mcomw %1,%0")
-
-(define_insn "abssi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(abs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "mabsw %1,%0")
-
-;______________________________________________________________________
-;
-;	Floating-point Arithmetic.
-;______________________________________________________________________
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(plus:DF (match_operand:DF 1 "register_operand" "%0")
-		 (match_operand:DF 2 "register_operand" "r")))]
-  ""
-  "addd %2,%0")
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(plus:SF (match_operand:SF 1 "register_operand" "%0")
-		 (match_operand:SF 2 "register_operand" "r")))]
-  ""
-  "addf %2,%0")
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(minus:DF (match_operand:DF 1 "register_operand" "0")
-		  (match_operand:DF 2 "register_operand" "r")))]
-  ""
-  "subd %2,%0")
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(minus:SF (match_operand:SF 1 "register_operand" "0")
-		  (match_operand:SF 2 "register_operand" "r")))]
-  ""
-  "subf %2,%0")
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(mult:DF (match_operand:DF 1 "register_operand" "%0")
-		 (match_operand:DF 2 "register_operand" "r")))]
-  ""
-  "muld %2,%0")
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(mult:SF (match_operand:SF 1 "register_operand" "%0")
-		 (match_operand:SF 2 "register_operand" "r")))]
-  ""
-  "mulf %2,%0")
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(div:DF (match_operand:DF 1 "register_operand" "0")
-		(match_operand:DF 2 "register_operand" "r")))]
-  ""
-  "divd %2,%0")
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(div:SF (match_operand:SF 1 "register_operand" "0")
-		(match_operand:SF 2 "register_operand" "r")))]
-  ""
-  "divf %2,%0")
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(neg:DF (match_operand:DF 1 "register_operand" "r")))]
-  ""
-  "mnegd %1,%0")
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(neg:SF (match_operand:SF 1 "register_operand" "r")))]
-  ""
-  "mnegf %1,%0")
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "=r")
-	(abs:DF (match_operand:DF 1 "register_operand" "r")))]
-  ""
-  "mabsd %1,%0")
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(abs:SF (match_operand:SF 1 "register_operand" "r")))]
-  ""
-  "mabsf %1,%0")
-
-;______________________________________________________________________
-;
-;	Logical and Shift Instructions.
-;______________________________________________________________________
-
-(define_insn ""
-  [(set (cc0)
-	(and:SI (match_operand:SI 0 "general_operand" "%r")
-		(match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "*
-{
-  cc_status.flags |= CC_NO_OVERFLOW;
-  return \"bitw %1,%0\";
-}")
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(and:SI (match_operand:SI 1 "general_operand" "%0,r")
-		(match_operand:SI 2 "general_operand" "g,K")))]
-  ""
-  "*
-{
-  if (which_alternative == 0)
-    return \"andw %2,%0\";
-
-  cc_status.flags = CC_NOT_NEGATIVE;
-  return (INTVAL (operands[2]) == 255
-	  ? \"movzbw %1,%0\" : \"movzhw %1,%0\");
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
-		(match_operand:SI 2 "register_operand" "0")))]
-  ""
-  "bicw %1,%0")
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (match_operand:SI 1 "general_operand" "%0")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "orw %2,%0")
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(xor:SI (match_operand:SI 1 "general_operand" "%0")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "xorw %2,%0")
-
-; The arithmetic left shift instructions work strangely on pyramids.
-; They fail to modify the sign bit.  Therefore, use logic shifts.
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:SI 2 "general_operand" "rnm")))]
-  ""
-  "*
-{
-  extern char *output_shift ();
-  return output_shift (\"lshlw %2,%0\", operands[2], 32);
-}")
-
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:SI 2 "general_operand" "rnm")))]
-  ""
-  "*
-{
-  extern char *output_shift ();
-  return output_shift (\"ashrw %2,%0\", operands[2], 32);
-}")
-
-(define_insn "ashrdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
-		     (match_operand:SI 2 "general_operand" "rnm")))]
-  ""
-  "*
-{
-  extern char *output_shift ();
-  return output_shift (\"ashrl %2,%0\", operands[2], 64);
-}")
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:SI 2 "general_operand" "rnm")))]
-  ""
-  "*
-{
-  extern char *output_shift ();
-  return output_shift (\"lshrw %2,%0\", operands[2], 32);
-}")
-
-(define_insn "rotlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(rotate:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:SI 2 "general_operand" "rnm")))]
-  ""
-  "*
-{
-  extern char *output_shift ();
-  return output_shift (\"rotlw %2,%0\", operands[2], 32);
-}")
-
-(define_insn "rotrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(rotatert:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:SI 2 "general_operand" "rnm")))]
-  ""
-  "*
-{
-  extern char *output_shift ();
-  return output_shift (\"rotrw %2,%0\", operands[2], 32);
-}")
-
-;______________________________________________________________________
-;
-;	Fixed and Floating Moves.
-;______________________________________________________________________
-
-;; If the destination is a memory operand, indexed source operands are
-;; disallowed.  Big DImode constants are always loaded into a reg pair,
-;; although offsettable memory addresses really could be dealt with.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "memory_operand" "=m")
-	(match_operand:DI 1 "nonindexed_operand" "gF"))]
-  "(GET_CODE (operands[1]) == CONST_DOUBLE
-     ? ((CONST_DOUBLE_HIGH (operands[1]) == 0
-	 && CONST_DOUBLE_LOW (operands[1]) >= 0)
-	|| (CONST_DOUBLE_HIGH (operands[1]) == -1
-	    && CONST_DOUBLE_LOW (operands[1]) < 0))
-     : 1)"
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-  return \"movl %1,%0\";
-}")
-
-;; Force the destination to a register, so all source operands are allowed.
-
-(define_insn "movdi"
-  [(set (match_operand:DI 0 "general_operand" "=r")
-	(match_operand:DI 1 "general_operand" "gF"))]
-  ""
-  "*
-{
-  extern char *output_move_double ();
-  return output_move_double (operands);
-}")
-
-;; If the destination is a memory address, indexed source operands are
-;; disallowed.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "memory_operand" "=m")
-	(match_operand:SI 1 "nonindexed_operand" "g"))]
-  ""
-  "movw %1,%0")
-
-;; Force the destination to a register, so all source operands are allowed.
-
-(define_insn "movsi"
-  [(set (match_operand:SI 0 "general_operand" "=r")
-	(match_operand:SI 1 "general_operand" "g"))]
-  ""
-  "movw %1,%0")
-
-;; If the destination is a memory address, indexed source operands are
-;; disallowed.
-
-(define_insn ""
-  [(set (match_operand:HI 0 "memory_operand" "=m")
-	(match_operand:HI 1 "nonindexed_operand" "g"))]
-  ""
-  "*
-{
-  if (REG_P (operands[1]))
-    return \"cvtwh %1,%0\";		/* reg -> mem */
-  else
-    return \"movh %1,%0\";		/* mem imm -> mem */
-}")
-
-;; Force the destination to a register, so all source operands are allowed.
-
-(define_insn "movhi"
-  [(set (match_operand:HI 0 "general_operand" "=r")
-	(match_operand:HI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) != MEM)
-    return \"movw %1,%0\";		/* reg imm -> reg  */
-  return \"cvthw %1,%0\";		/* mem -> reg */
-}")
-
-;; If the destination is a memory address, indexed source operands are
-;; disallowed.
-
-(define_insn ""
-  [(set (match_operand:QI 0 "memory_operand" "=m")
-	(match_operand:QI 1 "nonindexed_operand" "g"))]
-  ""
-  "*
-{
-  if (REG_P (operands[1]))
-    return \"cvtwb %1,%0\";		/* reg -> mem */
-  else
-    return \"movb %1,%0\";		/* mem imm -> mem */
-}")
-
-;; Force the destination to a register, so all source operands are allowed.
-
-(define_insn "movqi"
-  [(set (match_operand:QI 0 "general_operand" "=r")
-	(match_operand:QI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) != MEM)
-    return \"movw %1,%0\";		/* reg imm -> reg  */
-  return \"cvtbw %1,%0\";		/* mem -> reg */
-}")
-
-;; If the destination is a memory address, indexed source operands are
-;; disallowed.
-
-(define_insn ""
-  [(set (match_operand:DF 0 "memory_operand" "=m")
-	(match_operand:DF 1 "nonindexed_operand" "g"))]
-  "GET_CODE (operands[1]) != CONST_DOUBLE"
-  "movl %1,%0")
-
-;; Force the destination to a register, so all source operands are allowed.
-
-(define_insn "movdf"
-  [(set (match_operand:DF 0 "general_operand" "=r")
-	(match_operand:DF 1 "general_operand" "gF"))]
-  ""
-  "*
-{
-  extern char *output_move_double ();
-  return output_move_double (operands);
-}")
-
-;; If the destination is a memory address, indexed source operands are
-;; disallowed.
-
-(define_insn ""
-  [(set (match_operand:SF 0 "memory_operand" "=m")
-	(match_operand:SF 1 "nonindexed_operand" "g"))]
-  ""
-  "movw %1,%0")
-
-;; Force the destination to a register, so all source operands are allowed.
-
-(define_insn "movsf"
-  [(set (match_operand:SF 0 "general_operand" "=r")
-	(match_operand:SF 1 "general_operand" "g"))]
-  ""
-  "movw %1,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:QI 1 "address_operand" "p"))]
-  ""
-  "*
-{
-  forget_cc_if_dependent (operands[0]);
-  return \"mova %a1,%0\";
-}")
-
-;______________________________________________________________________
-;
-;	Conversion patterns.
-;______________________________________________________________________
-
-;; The trunc patterns are used only when non compile-time constants are used.
-
-(define_insn "truncsiqi2"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(truncate:QI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "*
-{
-  if (REG_P (operands[0]) && REG_P (operands[1])
-      && REGNO (operands[0]) == REGNO (operands[1]))
-    {
-      cc_status = cc_prev_status;
-      return \"\";
-    }
-  forget_cc_if_dependent (operands[0]);
-  return \"movw %1,%0\";
-}")
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(truncate:HI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "*
-{
-  if (REG_P (operands[0]) && REG_P (operands[1])
-      && REGNO (operands[0]) == REGNO (operands[1]))
-    {
-      cc_status = cc_prev_status;
-      return \"\";
-    }
-  forget_cc_if_dependent (operands[0]);
-  return \"movw %1,%0\";
-}")
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=r,m")
-	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm,r")))]
-  ""
-  "*
-{
-  if (optimize && REG_P (operands[0]) && REG_P (operands[1])
-      && REGNO (operands[0]) == REGNO (operands[1])
-      && already_sign_extended (insn, HImode, operands[0]))
-    {
-      cc_status = cc_prev_status;
-      return \"\";
-    }
-  return \"cvthw %1,%0\";
-}")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=r,m")
-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm,r")))]
-  ""
-  "*
-{
-  if (optimize && REG_P (operands[0]) && REG_P (operands[1])
-      && REGNO (operands[0]) == REGNO (operands[1])
-      && already_sign_extended (insn, QImode, operands[0]))
-    {
-      cc_status = cc_prev_status;
-      return \"\";
-    }
-  return \"cvtbw %1,%0\";
-}")
-
-; Pyramid doesn't have insns *called* "cvtbh" or "movzbh".
-; But we can cvtbw/movzbw into a register, where there is no distinction
-; between words and halfwords.
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "cvtbw %1,%0")
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "*
-{
-  cc_status.flags = CC_NOT_NEGATIVE;
-  return \"movzhw %1,%0\";
-}")
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "*
-{
-  cc_status.flags = CC_NOT_NEGATIVE;
-  return \"movzbw %1,%0\";
-}")
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
-  ""
-  "*
-{
-  cc_status.flags = CC_NOT_NEGATIVE;
-  return \"movzbw %1,%0\";
-}")
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "general_operand" "=&r,m")
-	(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "rm,r")))]
-  ""
-  "cvtfd %1,%0")
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "general_operand" "=&r,m")
-	(float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "rm,r")))]
-  ""
-  "cvtdf %1,%0")
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "general_operand" "=&r,m")
-	(float:SF (match_operand:SI 1 "nonimmediate_operand" "rm,r")))]
-  ""
-  "cvtwf %1,%0")
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "general_operand" "=&r,m")
-	(float:DF (match_operand:SI 1 "nonimmediate_operand" "rm,r")))]
-  ""
-  "cvtwd %1,%0")
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=&r,m")
-	(fix:SI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "rm,r"))))]
-  ""
-  "cvtfw %1,%0")
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=&r,m")
-	(fix:SI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "rm,r"))))]
-  ""
-  "cvtdw %1,%0")
-
-;______________________________________________________________________
-;
-;	Flow Control Patterns.
-;______________________________________________________________________
-
-;; Prefer "br" to "jump" for unconditional jumps, since it's faster.
-;; (The assembler can manage with out-of-range branches.)
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "br %l0")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "relop" [(cc0) (const_int 0)])
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  if (optimize)
-    switch (GET_CODE (operands[0]))
-      {
-      case EQ: case NE:
-	break;
-      case LT: case LE: case GE: case GT:
-	if (cc_prev_status.mdep == CC_VALID_FOR_UNSIGNED)
-	  return 0;
-	break;
-      case LTU: case LEU: case GEU: case GTU:
-	if (cc_prev_status.mdep != CC_VALID_FOR_UNSIGNED)
-	  return 0;
-	break;
-      }
-
-  return \"b%N0 %l1\";
-}")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "relop" [(cc0) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 1 "" ""))))]
-  ""
-  "*
-{
-  if (optimize)
-    switch (GET_CODE (operands[0]))
-      {
-      case EQ: case NE:
-	break;
-      case LT: case LE: case GE: case GT:
-	if (cc_prev_status.mdep == CC_VALID_FOR_UNSIGNED)
-	  return 0;
-	break;
-      case LTU: case LEU: case GEU: case GTU:
-	if (cc_prev_status.mdep != CC_VALID_FOR_UNSIGNED)
-	  return 0;
-	break;
-      }
-
-  return \"b%C0 %l1\";
-}")
-
-(define_insn "call"
-  [(call (match_operand:QI 0 "memory_operand" "m")
-	 (match_operand:SI 1 "immediate_operand" "n"))]
-  ""
-  "call %0")
-
-(define_insn "call_value"
-  [(set (match_operand 0 "" "=r")
-	(call (match_operand:QI 1 "memory_operand" "m")
-	      (match_operand:SI 2 "immediate_operand" "n")))]
-  ;; Operand 2 not really used on Pyramid architecture.
-  ""
-  "call %1")
-
-(define_insn "return"
-  [(return)]
-  ""
-  "*
-{
-  if (get_frame_size () + current_function_pretend_args_size
-      + current_function_args_size != 0
-      || current_function_calls_alloca)
-    {
-      int dealloc_size = current_function_pretend_args_size;
-      if (current_function_pops_args)
-        dealloc_size += current_function_args_size;
-      operands[0] = GEN_INT (dealloc_size);
-      return \"retd %0\";
-    }
-  else
-    return \"ret\";
-}")
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jump (%0)")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "movw gr0,gr0  # nop")
-
-;______________________________________________________________________
-;
-;	Peep-hole Optimization Patterns.
-;______________________________________________________________________
-
-;; Optimize fullword move followed by a test of the moved value.
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "nonimmediate_operand" "rm"))
-   (set (cc0) (match_operand:SI 2 "nonimmediate_operand" "rm"))]
-  "rtx_equal_p (operands[2], operands[0])
-   || rtx_equal_p (operands[2], operands[1])"
-  "*
-  cc_status.flags |= CC_NO_OVERFLOW;
-  return \"mtstw %1,%0\";
-")
-
-;; Optimize loops with an incremented/decremented variable.
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 0)
-		 (const_int -1)))
-   (set (cc0)
-	(compare (match_operand:SI 1 "register_operand" "r")
-		 (match_operand:SI 2 "nonmemory_operand" "ri")))
-   (set (pc)
-	(if_then_else (match_operator:SI 3 "signed_comparison"
-			 [(cc0) (const_int 0)])
-		      (label_ref (match_operand 4 "" ""))
-		      (pc)))]
-  "(GET_CODE (operands[2]) == CONST_INT
-    ? (unsigned)INTVAL (operands[2]) + 32 >= 64
-    : 1) && (rtx_equal_p (operands[0], operands[1])
-	     || rtx_equal_p (operands[0], operands[2]))"
-  "*
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      output_asm_insn (\"dcmpw %2,%0\", operands);
-      return \"b%N3 %l4\";
-    }
-  else
-    {
-      output_asm_insn (\"dcmpw %1,%0\", operands);
-      return \"b%R3 %l4\";
-    }
-")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 0)
-		 (const_int 1)))
-   (set (cc0)
-	(compare (match_operand:SI 1 "register_operand" "r")
-		 (match_operand:SI 2 "nonmemory_operand" "ri")))
-   (set (pc)
-	(if_then_else (match_operator:SI 3 "signed_comparison"
-			 [(cc0) (const_int 0)])
-		      (label_ref (match_operand 4 "" ""))
-		      (pc)))]
-  "(GET_CODE (operands[2]) == CONST_INT
-    ? (unsigned)INTVAL (operands[2]) + 32 >= 64
-    : 1) && (rtx_equal_p (operands[0], operands[1])
-	     || rtx_equal_p (operands[0], operands[2]))"
-  "*
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      output_asm_insn (\"icmpw %2,%0\", operands);
-      return \"b%N3 %l4\";
-    }
-  else
-    {
-      output_asm_insn (\"icmpw %1,%0\", operands);
-      return \"b%R3 %l4\";
-    }
-")
-
-;; Combine two word moves with consecutive operands into one long move.
-;; Also combines immediate moves, if the high-order destination operand
-;; is loaded with 0 or -1 and the low-order destination operand is loaded
-;; with a constant with the same sign.
-
-(define_peephole
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operand:SI 1 "general_operand" "g"))
-   (set (match_operand:SI 2 "general_operand" "=g")
-	(match_operand:SI 3 "general_operand" "g"))]
-  "movdi_possible (operands)"
-  "*
-{
-  output_asm_insn (\"# COMBINE movw %1,%0\", operands);
-  output_asm_insn (\"# COMBINE movw %3,%2\", operands);
-  movdi_possible (operands);
-  if (CONSTANT_P (operands[1]))
-    return (swap_operands ? \"movl %3,%0\" : \"movl %1,%2\");
-
-  return (swap_operands ? \"movl %1,%0\" : \"movl %3,%2\");
-}")
-
-;; Optimize certain tests after memory stores.
-
-(define_peephole
-  [(set (match_operand 0 "memory_operand" "=m")
-	(match_operand 1 "register_operand" "r"))
-   (set (match_operand:SI 2 "register_operand" "=r")
-	(sign_extend:SI (match_dup 1)))
-   (set (cc0)
-	(match_dup 2))]
-  "dead_or_set_p (insn, operands[2])"
-  "*
-  cc_status.flags |= CC_NO_OVERFLOW;
-  if (GET_MODE (operands[0]) == QImode)
-    return \"cvtwb %1,%0\";
-  else
-    return \"cvtwh %1,%0\";
-")
-
-;______________________________________________________________________
-;
-;	DImode Patterns.
-;______________________________________________________________________
-
-(define_expand "extendsidi2"
-  [(set (subreg:SI (match_operand:DI 0 "register_operand" "=r") 1)
-	(match_operand:SI 1 "general_operand" "g"))
-   (set (subreg:SI (match_dup 0) 0)
-	(subreg:SI (match_dup 0) 1))
-   (set (subreg:SI (match_dup 0) 0)
-	(ashiftrt:SI (subreg:SI (match_dup 0) 0)
-		     (const_int 31)))]
-  ""
-  "")
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_operand:DI 1 "nonmemory_operand" "%0")
-		 (match_operand:DI 2 "nonmemory_operand" "rF")))]
-  ""
-  "*
-{
-  rtx xoperands[2];
-  CC_STATUS_INIT;
-  xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  if (REG_P (operands[2]))
-    xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
-  else
-    {
-      xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
-      operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
-    }
-  output_asm_insn (\"addw %1,%0\", xoperands);
-  return \"addwc %2,%0\";
-}")
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "register_operand" "0")
-		  (match_operand:DI 2 "nonmemory_operand" "rF")))]
-  ""
-  "*
-{
-  rtx xoperands[2];
-  CC_STATUS_INIT;
-  xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  if (REG_P (operands[2]))
-    xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
-  else
-    {
-      xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
-      operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
-    }
-  output_asm_insn (\"subw %1,%0\", xoperands);
-  return \"subwb %2,%0\";
-}")
-
-(define_insn "iordi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ior:DI (match_operand:DI 1 "nonmemory_operand" "%0")
-		(match_operand:DI 2 "nonmemory_operand" "rF")))]
-  ""
-  "*
-{
-  rtx xoperands[2];
-  CC_STATUS_INIT;
-  xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  if (REG_P (operands[2]))
-    xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
-  else
-    {
-      xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
-      operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
-    }
-  output_asm_insn (\"orw %1,%0\", xoperands);
-  return \"orw %2,%0\";
-}")
-
-(define_insn "anddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(and:DI (match_operand:DI 1 "nonmemory_operand" "%0")
-		(match_operand:DI 2 "nonmemory_operand" "rF")))]
-  ""
-  "*
-{
-  rtx xoperands[2];
-  CC_STATUS_INIT;
-  xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  if (REG_P (operands[2]))
-    xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
-  else
-    {
-      xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
-      operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
-    }
-  output_asm_insn (\"andw %1,%0\", xoperands);
-  return \"andw %2,%0\";
-}")
-
-(define_insn "xordi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(xor:DI (match_operand:DI 1 "nonmemory_operand" "%0")
-		(match_operand:DI 2 "nonmemory_operand" "rF")))]
-  ""
-  "*
-{
-  rtx xoperands[2];
-  CC_STATUS_INIT;
-  xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  if (REG_P (operands[2]))
-    xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
-  else
-    {
-      xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
-      operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
-    }
-  output_asm_insn (\"xorw %1,%0\", xoperands);
-  return \"xorw %2,%0\";
-}")
-
-;; My version, modelled after Jonathan Stone's and "tablejump" - S.P.
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "general_operand" "r"))]
-  ""
-  "jump (%0)")
diff --git a/gcc/config/pyr/x-pyr b/gcc/config/pyr/x-pyr
deleted file mode 100755
index 5ee249a..0000000
--- a/gcc/config/pyr/x-pyr
+++ /dev/null
@@ -1,2 +0,0 @@
-CLIB=-lc /usr/.attlib/libPW.a
-
diff --git a/gcc/config/pyr/xm-pyr.h b/gcc/config/pyr/xm-pyr.h
deleted file mode 100755
index d3e1168..0000000
--- a/gcc/config/pyr/xm-pyr.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Configuration for GNU compiler, for Pyramid 90x, 9000, and MIServer Series.
-   Copyright (C) 1989, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_WORDS_BIG_ENDIAN
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
diff --git a/gcc/config/romp/romp.c b/gcc/config/romp/romp.c
deleted file mode 100755
index 0f64a9e..0000000
--- a/gcc/config/romp/romp.c
+++ /dev/null
@@ -1,2038 +0,0 @@
-/* Subroutines used for code generation on ROMP.
-   Copyright (C) 1990, 1991, 1992, 1993, 1997 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#include "expr.h"
-#include "obstack.h"
-#include "tree.h"
-
-#define min(A,B)	((A) < (B) ? (A) : (B))
-#define max(A,B)	((A) > (B) ? (A) : (B))
-
-static int unsigned_comparisons_p ();
-static void output_loadsave_fpregs ();
-static void output_fpops ();
-static void init_fpops ();
-
-/* Return 1 if the insn using CC0 set by INSN does not contain
-   any unsigned tests applied to the condition codes.
-
-   Based on `next_insn_tests_no_inequality' in recog.c.  */
-
-int
-next_insn_tests_no_unsigned (insn)
-     rtx insn;
-{
-  register rtx next = next_cc0_user (insn);
-
-  if (next == 0)
-    {
-      if (find_reg_note (insn, REG_UNUSED, cc0_rtx))
-	return 1;
-      else
-	abort ();
-    }
-
-  return ((GET_CODE (next) == JUMP_INSN
-	   || GET_CODE (next) == INSN
-	   || GET_CODE (next) == CALL_INSN)
-	  && ! unsigned_comparisons_p (PATTERN (next)));
-}
-
-static int
-unsigned_comparisons_p (x)
-     rtx x;
-{
-  register char *fmt;
-  register int len, i;
-  register enum rtx_code code = GET_CODE (x);
-
-  switch (code)
-    {
-    case REG:
-    case PC:
-    case CC0:
-    case CONST_INT:
-    case CONST_DOUBLE:
-    case CONST:
-    case LABEL_REF:
-    case SYMBOL_REF:
-      return 0;
-
-    case LTU:
-    case GTU:
-    case LEU:
-    case GEU:
-      return (XEXP (x, 0) == cc0_rtx || XEXP (x, 1) == cc0_rtx);
-    }
-
-  len = GET_RTX_LENGTH (code);
-  fmt = GET_RTX_FORMAT (code);
-
-  for (i = 0; i < len; i++)
-    {
-      if (fmt[i] == 'e')
-	{
-	  if (unsigned_comparisons_p (XEXP (x, i)))
-	    return 1;
-	}
-      else if (fmt[i] == 'E')
-	{
-	  register int j;
-	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
-	    if (unsigned_comparisons_p (XVECEXP (x, i, j)))
-	      return 1;
-	}
-    }
-	    
-  return 0;
-}
-
-/* Update the condition code from the insn.  Look mostly at the first
-   byte of the machine-specific insn description information.
-
-   cc_state.value[12] refer to two possible values that might correspond
-   to the CC.  We only store register values.  */
-
-update_cc (body, insn)
-    rtx body;
-    rtx insn;
-{
-  switch (get_attr_cc (insn))
-    {
-    case CC_NONE:
-      /* Insn does not affect the CC at all.  */
-      break;
-
-    case CC_CHANGE0:
-      /* Insn doesn't affect the CC but does modify operand[0], known to be
-	 a register.  */
-      if (cc_status.value1 != 0
-	  && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1))
-	cc_status.value1 = 0;
-
-      if (cc_status.value2 != 0
-	  && reg_overlap_mentioned_p (recog_operand[0], cc_status.value2))
-	cc_status.value2 = 0;
-
-      break;
-
-    case CC_COPY1TO0:
-      /* Insn copies operand[1] to operand[0], both registers, but doesn't
-         affect the CC.  */
-      if (cc_status.value1 != 0
-	  && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1))
-	cc_status.value1 = 0;
-
-      if (cc_status.value2 != 0
-	  && reg_overlap_mentioned_p (recog_operand[0], cc_status.value2))
-	cc_status.value2 = 0;
-
-      if (cc_status.value1 != 0
-	  && rtx_equal_p (cc_status.value1, recog_operand[1]))
-	cc_status.value2 = recog_operand[0];
-
-      if (cc_status.value2 != 0
-	  && rtx_equal_p (cc_status.value2, recog_operand[1]))
-	cc_status.value1 = recog_operand[0];
-
-      break;
-
-    case CC_CLOBBER:
-      /* Insn clobbers CC. */
-      CC_STATUS_INIT;
-      break;
-
-    case CC_SETS:
-      /* Insn sets CC to recog_operand[0], but overflow is impossible.  */
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_NO_OVERFLOW;
-      cc_status.value1 = recog_operand[0];
-      break;
-
-   case CC_COMPARE:
-      /* Insn is a compare which sets the CC fully.  Update CC_STATUS for this
-	 compare and mark whether the test will be signed or unsigned.  */
-      {
-	register rtx p = PATTERN (insn);
-
-	CC_STATUS_INIT;
-
-	if (GET_CODE (p) == PARALLEL)
-	  p = XVECEXP (p, 0, 0);
-	cc_status.value1 = SET_SRC (p);
-
-	if (GET_CODE (SET_SRC (p)) == REG)
-	  cc_status.flags |= CC_NO_OVERFLOW;
-	if (! next_insn_tests_no_unsigned (insn))
-	  cc_status.flags |= CC_UNSIGNED;
-      }
-      break;
-
-    case CC_TBIT:
-      /* Insn sets T bit if result is non-zero.  Next insn must be branch. */
-      CC_STATUS_INIT;
-      cc_status.flags = CC_IN_TB | CC_NOT_NEGATIVE;
-      break;
-
-    default:
-      abort ();
-   }
-}
-
-/* Return 1 if a previous compare needs to be re-issued.  This will happen
-   if two compares tested the same objects, but one was signed and the
-   other unsigned.  OP is the comparison operation being performed.  */
-
-int
-restore_compare_p (op)
-     rtx op;
-{
-  enum rtx_code code = GET_CODE (op);
-
-  return (((code == GEU || code == LEU || code == GTU || code == LTU)
-	   && ! (cc_status.flags & CC_UNSIGNED))
-	  || ((code == GE || code == LE || code == GT || code == LT)
-	      && (cc_status.flags & CC_UNSIGNED)));
-}
-
-/*  Generate the (long) string corresponding to an inline multiply insn.
-    Note that `r10' does not refer to the register r10, but rather to the
-    SCR used as the MQ.  */
-char *
-output_in_line_mul ()
-{
-  static char insns[200];
-  int i;
-
-  strcpy (insns, "s %0,%0\n");
-  strcat (insns, "\tmts r10,%1\n");
-  for (i = 0; i < 16; i++)
-    strcat (insns, "\tm %0,%2\n");
-  strcat (insns, "\tmfs r10,%0");
-
-  return insns;
-}
-
-/* Returns 1 if OP is a memory reference with an offset from a register within
-   the range specified.  The offset must also be a multiple of the size of the
-   mode.  */
-
-static int
-memory_offset_in_range_p (op, mode, low, high)
-     register rtx op;
-     enum machine_mode mode;
-     int low, high;
-{
-  int offset = 0;
-
-  if (! memory_operand (op, mode))
-    return 0;
-
-  while (GET_CODE (op) == SUBREG)
-    {
-      offset += SUBREG_WORD (op) * UNITS_PER_WORD;
-#if BYTES_BIG_ENDIAN
-      offset -= (min (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op)))
-		 - min (UNITS_PER_WORD,
-			GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))));
-#endif
-      op = SUBREG_REG (op);
-    }
-
-  /* We must now have either (mem (reg (x)), (mem (plus (reg (x)) (c))),
-     or a constant pool address.  */
-  if (GET_CODE (op) != MEM)
-    abort ();
-
-  /* Now use the actual mode and get the address.  */
-  mode = GET_MODE (op);
-  op = XEXP (op, 0);
-  if (GET_CODE (op) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (op))
-    offset = get_pool_offset (op) + 12;
-  else if (GET_CODE (op) == PLUS)
-    {
-      if (GET_CODE (XEXP (op, 1)) != CONST_INT
-	  || ! register_operand (XEXP (op, 0), Pmode))
-	return 0;
-
-      offset += INTVAL (XEXP (op, 1));
-    }
-
-  else if (! register_operand (op, Pmode))
-    return 0;
-
-  return (offset >= low && offset <= high
-	  && (offset % GET_MODE_SIZE (mode) == 0));
-}
-
-/* Return 1 if OP is a valid operand for a memory reference insn that can
-   only reference indirect through a register.   */
-
-int
-zero_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return memory_offset_in_range_p (op, mode, 0, 0);
-}
-
-/* Return 1 if OP is a valid operand for a `short' memory reference insn. */
-
-int
-short_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (mode == VOIDmode)
-    mode = GET_MODE (op);
-
-  return memory_offset_in_range_p (op, mode, 0,
-				   15 * min (UNITS_PER_WORD,
-					     GET_MODE_SIZE (mode)));
-}
-
-/* Returns 1 if OP is a memory reference involving a symbolic constant
-   that is not in the constant pool. */
-
-int
-symbolic_memory_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (! memory_operand (op, mode))
-    return 0;
-
-  while (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (GET_CODE (op) != MEM)
-    abort ();
-
-  op = XEXP (op, 0);
-  if (constant_pool_address_operand (op, VOIDmode))
-    return 0;
-  else
-    return romp_symbolic_operand (op, Pmode)
-      || (GET_CODE (op) == PLUS && register_operand (XEXP (op, 0), Pmode)
-	  && romp_symbolic_operand (XEXP (op, 1), Pmode));
-}
-
-
-/* Returns 1 if OP is a constant pool reference to the current function.  */
-
-int
-current_function_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != MEM || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
-      ||  ! CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
-    return 0;
-
-  op = get_pool_constant (XEXP (op, 0));
-  return (GET_CODE (op) == SYMBOL_REF
-	  && ! strcmp (current_function_name, XSTR (op, 0)));
-}
-
-/* Return non-zero if this function is known to have a null epilogue.  */
-
-int
-null_epilogue ()
-{
-  return (reload_completed
-	  && first_reg_to_save () == 16
-	  && ! romp_pushes_stack ());
-}
-
-/* Returns 1 if OP is the address of a location in the constant pool.  */
-
-int
-constant_pool_address_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return ((GET_CODE (op) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (op))
-	  || (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == PLUS
-	      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
-	      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
-	      && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (op, 0), 0))));
-}
-
-/* Returns 1 if OP is either a symbol reference or a sum of a symbol
-   reference and a constant.  */
-
-int
-romp_symbolic_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return ! op->integrated;
-
-    case CONST:
-      op = XEXP (op, 0);
-      return (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
-	      || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-	     && GET_CODE (XEXP (op, 1)) == CONST_INT;
-
-    default:
-      return 0;
-    }
-}
-
-/* Returns 1 if OP is a valid constant for the ROMP.  */
-
-int
-constant_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case LABEL_REF:
-    case SYMBOL_REF:
-    case PLUS:
-    case CONST:
-      return romp_symbolic_operand (op,mode);
-
-    case CONST_INT:
-      return (unsigned int) (INTVAL (op) + 0x8000) < 0x10000
-	     || (INTVAL (op) & 0xffff) == 0 || (INTVAL (op) & 0xffff0000) == 0;
-
-    default:
-      return 0;
-    }
-}
-
-/* Returns 1 if OP is either a constant integer valid for the ROMP or a
-   register.  If a register, it must be in the proper mode unless MODE is
-   VOIDmode.  */
-
-int
-reg_or_cint_operand (op, mode)
-      register rtx op;
-      enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return constant_operand (op, mode);
-
-  return register_operand (op, mode);
-}
-
-/* Return 1 is the operand is either a register or ANY constant integer.  */
-
-int
-reg_or_any_cint_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-     return GET_CODE (op) == CONST_INT || register_operand (op, mode);
-}
-
-/* Return 1 if the operand is either a register or a valid D-type operand. */
-
-int
-reg_or_D_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return (unsigned) (INTVAL (op) + 0x8000) < 0x10000;
-
-  return register_operand (op, mode);
-}
-
-/* Return 1 if the operand is either a register or an item that can be
-   used as the operand of an SI add insn.  */
-
-int
-reg_or_add_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  return reg_or_D_operand (op, mode) || romp_symbolic_operand (op, mode)
-	 || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0);
-}
-
-/* Return 1 if the operand is either a register or an item that can be
-   used as the operand of a ROMP logical AND insn.  */
-
-int
-reg_or_and_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  if (reg_or_cint_operand (op, mode))
-    return 1;
-
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-
-  return (INTVAL (op) & 0xffff) == 0xffff
-	 || (INTVAL (op) & 0xffff0000) == 0xffff0000;
-}
-
-/* Return 1 if the operand is a register or memory operand.  */
-
-int
-reg_or_mem_operand (op, mode)
-     register rtx op;
-     register enum machine_mode mode;
-{
-  return register_operand (op, mode) || memory_operand (op, mode);
-}
-
-/* Return 1 if the operand is either a register or a memory operand that is
-   not symbolic.  */
-
-int
-reg_or_nonsymb_mem_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  if (register_operand (op, mode))
-    return 1;
-
-  if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
-    return 1;
-
-  return 0;
-}
-
-/* Return 1 if this operand is valid for the ROMP.  This is any operand except
-   certain constant integers.  */
-
-int
-romp_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return constant_operand (op, mode);
-
-  return general_operand (op, mode);
-}
-
-/* Return 1 if the operand is (reg:mode 0).  */
-
-int
-reg_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return ((mode == VOIDmode || mode == GET_MODE (op))
-	  && GET_CODE (op) == REG && REGNO (op) == 0);
-}
-
-/* Return 1 if the operand is (reg:mode 15).  */
-
-int
-reg_15_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return ((mode == VOIDmode || mode == GET_MODE (op))
-	  && GET_CODE (op) == REG && REGNO (op) == 15);
-}
-
-/* Return 1 if this is a binary floating-point operation.  */
-
-int
-float_binary (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-
-  if (GET_MODE (op) != SFmode && GET_MODE (op) != DFmode)
-    return 0;
-
-  switch (GET_CODE (op))
-    {
-    case PLUS:
-    case MINUS:
-    case MULT:
-    case DIV:
-      return GET_MODE (XEXP (op, 0)) == GET_MODE (op)
-	     && GET_MODE (XEXP (op, 1)) == GET_MODE (op);
-
-    default:
-      return 0;
-    }
-}
-
-/* Return 1 if this is a unary floating-point operation.  */
-
-int
-float_unary (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-
-  if (GET_MODE (op) != SFmode && GET_MODE (op) != DFmode)
-    return 0;
-
-  return (GET_CODE (op) == NEG || GET_CODE (op) == ABS)
-	 && GET_MODE (XEXP (op, 0)) == GET_MODE (op);
-}
-
-/* Return 1 if this is a valid floating-point conversion that can be done
-   as part of an operation by the RT floating-point routines.  */
-
-int
-float_conversion (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-
-  switch (GET_CODE (op))
-    {
-    case FLOAT_TRUNCATE:
-      return GET_MODE (op) == SFmode && GET_MODE (XEXP (op, 0)) == DFmode;
-
-    case FLOAT_EXTEND:
-      return GET_MODE (op) == DFmode && GET_MODE (XEXP (op, 0)) == SFmode;
-
-    case FLOAT:
-      return ((GET_MODE (XEXP (op, 0)) == SImode
-	       || GET_CODE (XEXP (op, 0)) == CONST_INT)
-	      && (GET_MODE (op) == SFmode || GET_MODE (op) == DFmode));
-
-    case FIX:
-      return ((GET_MODE (op) == SImode
-	       || GET_CODE (XEXP (op, 0)) == CONST_INT)
-	      && (GET_MODE (XEXP (op, 0)) == SFmode
-		  || GET_MODE (XEXP (op, 0)) == DFmode));
-
-    default:
-      return 0;
-    }
-}
-
-/* Print an operand.  Recognize special options, documented below.  */
-
-void
-print_operand (file, x, code)
-    FILE *file;
-    rtx x;
-    char code;
-{
-  int i;
-
-  switch (code)
-    {
-    case 'B':
-      /* Byte number (const/8) */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%B value");
-
-      fprintf (file, "%d", INTVAL (x) / 8);
-      break;
-
-    case 'L':
-      /* Low order 16 bits of constant.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%L value");
-
-      fprintf (file, "%d", INTVAL (x) & 0xffff);
-      break;
-
-    case 's':
-      /* Null or "16" depending on whether the constant is greater than 16. */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%s value");
-
-      if (INTVAL (x) >= 16)
-	fprintf (file, "16");
-
-      break;
-
-    case 'S':
-      /* For shifts: 's' will have given the half.  Just give the amount
-	 within 16.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%S value");
-
-      fprintf (file, "%d", INTVAL (x) & 15);
-      break;
-
-    case 'b':
-      /* The number of a single bit set or cleared, mod 16.  Note that the ROMP
-	 numbers bits with the high-order bit 31.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%b value");
-
-      if ((i = exact_log2 (INTVAL (x))) >= 0)
-	fprintf (file, "%d", (31 - i) % 16);
-      else if ((i = exact_log2 (~ INTVAL (x))) >= 0)
-	fprintf (file, "%d", (31 - i) % 16);
-      else
-	output_operand_lossage ("invalid %%b value");
-
-      break;
-
-    case 'h':
-      /* "l" or "u" depending on which half of the constant is zero.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%h value");
-
-      if ((INTVAL (x) & 0xffff0000) == 0)
-	fprintf (file, "l");
-      else if ((INTVAL (x) & 0xffff) == 0)
-	fprintf (file, "u");
-      else
-	output_operand_lossage ("invalid %%h value");
-
-      break;
-
-    case 'H':
-      /* Upper or lower half, depending on which half is zero.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%H value");
-
-      if ((INTVAL (x) & 0xffff0000) == 0)
-	fprintf (file, "%d", INTVAL (x) & 0xffff);
-      else if ((INTVAL (x) & 0xffff) == 0)
-	fprintf (file, "%d", (INTVAL (x) >> 16) & 0xffff);
-      else
-	output_operand_lossage ("invalid %%H value");
-
-      break;
-
-    case 'z':
-      /* Write two characters:
-		'lo'	if the high order part is all ones
-		'lz'	if the high order part is all zeros
-		'uo'	if the low order part is all ones
-		'uz'	if the low order part is all zeros 
-       */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%z value");
-
-      if ((INTVAL (x) & 0xffff0000) == 0)
-	fprintf (file, "lz");
-      else if ((INTVAL (x) & 0xffff0000) == 0xffff0000)
-	fprintf (file, "lo");
-      else if ((INTVAL (x) & 0xffff) == 0)
-	fprintf (file, "uz");
-      else if ((INTVAL (x) & 0xffff) == 0xffff)
-	fprintf (file, "uo");
-      else
-	output_operand_lossage ("invalid %%z value");
-
-      break;
-
-    case 'Z':
-      /* Upper or lower half, depending on which is non-zero or not
-	 all ones.  Must be consistent with 'z' above.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%Z value");
-
-      if ((INTVAL (x) & 0xffff0000) == 0
-	  || (INTVAL (x) & 0xffff0000) == 0xffff0000)
-	fprintf (file, "%d", INTVAL (x) & 0xffff);
-      else if ((INTVAL (x) & 0xffff) == 0 || (INTVAL (x) & 0xffff) == 0xffff)
-	fprintf (file, "%d", (INTVAL (x) >> 16) & 0xffff);
-      else
-	output_operand_lossage ("invalid %%Z value");
-
-      break;
-
-    case 'k':
-      /* Same as 'z', except the trailing 'o' or 'z' is not written.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%k value");
-
-      if ((INTVAL (x) & 0xffff0000) == 0
-	  || (INTVAL (x) & 0xffff0000) == 0xffff0000)
-	fprintf (file, "l");
-      else if ((INTVAL (x) & 0xffff) == 0
-	       || (INTVAL (x) & 0xffff) == 0xffff)
-	fprintf (file, "u");
-      else
-	output_operand_lossage ("invalid %%k value");
-
-      break;
-
-    case 't':
-      /* Similar to 's', except that we write 'h' or 'u'.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%k value");
-
-      if (INTVAL (x) < 16)
-	fprintf (file, "u");
-      else
-	fprintf (file, "l");
-      break;
-
-    case 'M':
-      /* For memory operations, write 's' if the operand is a short
-	 memory operand.  */
-      if (short_memory_operand (x, VOIDmode))
-	fprintf (file, "s");
-      break;
-
-    case 'N':
-      /* Like 'M', but check for zero memory offset.  */
-      if (zero_memory_operand (x, VOIDmode))
-	fprintf (file, "s");
-      break;
-
-    case 'O':
-      /* Write low-order part of DImode or DFmode.  Supported for MEM
-	 and REG only.  */
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", reg_names[REGNO (x) + 1]);
-      else if (GET_CODE (x) == MEM)
-	print_operand (file, gen_rtx (MEM, GET_MODE (x),
-				      plus_constant (XEXP (x, 0), 4)), 0);
-      else
-	abort ();
-      break;
-
-    case 'C':
-      /* Offset in constant pool for constant pool address.  */
-      if (! constant_pool_address_operand (x, VOIDmode))
-	abort ();
-      if (GET_CODE (x) == SYMBOL_REF)
-	fprintf (file, "%d", get_pool_offset (x) + 12);
-      else 
-	/* Must be (const (plus (symbol_ref) (const_int))) */
-	fprintf (file, "%d",
-		 (get_pool_offset (XEXP (XEXP (x, 0), 0)) + 12
-		  + INTVAL (XEXP (XEXP (x, 0), 1))));
-      break;
-
-    case 'j':
-      /* Branch opcode.  Check for condition in test bit for eq/ne.  */
-      switch (GET_CODE (x))
-	{
-	case EQ:
-	  if (cc_status.flags & CC_IN_TB)
-	    fprintf (file, "ntb");
-	  else
-	    fprintf (file, "eq");
-	  break;
-
-	case NE:
-	  if (cc_status.flags & CC_IN_TB)
-	    fprintf (file, "tb");
-	  else
-	    fprintf (file, "ne");
-	  break;
-
-	case GT:
-	case GTU:
-	  fprintf (file, "h");
-	  break;
-
-	case LT:
-	case LTU:
-	  fprintf (file, "l");
-	  break;
-
-	case GE:
-	case GEU:
-	  fprintf (file, "he");
-	  break;
-
-	case LE:
-	case LEU:
-	  fprintf (file, "le");
-	  break;
-
-	default:
-	  output_operand_lossage ("invalid %%j value");
-	}
-      break;
-
-    case 'J':
-      /* Reversed branch opcode.  */
-      switch (GET_CODE (x))
-	{
-	case EQ:
-	  if (cc_status.flags & CC_IN_TB)
-	    fprintf (file, "tb");
-	  else
-	    fprintf (file, "ne");
-	  break;
-
-	case NE:
-	  if (cc_status.flags & CC_IN_TB)
-	    fprintf (file, "ntb");
-	  else
-	    fprintf (file, "eq");
-	  break;
-
-	case GT:
-	case GTU:
-	  fprintf (file, "le");
-	  break;
-
-	case LT:
-	case LTU:
-	  fprintf (file, "he");
-	  break;
-
-	case GE:
-	case GEU:
-	  fprintf (file, "l");
-	  break;
-
-	case LE:
-	case LEU:
-	  fprintf (file, "h");
-	  break;
-
-	default:
-	  output_operand_lossage ("invalid %%j value");
-	}
-      break;
-
-    case '.':
-      /* Output nothing.  Used as delimiter in, e.g., "mc%B1%.3 " */
-      break;
-
-    case '#':
-      /* Output 'x' if this insn has a delay slot, else nothing.  */
-      if (dbr_sequence_length ())
-	fprintf (file, "x");
-      break;
-
-    case 0:
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", reg_names[REGNO (x)]);
-      else if (GET_CODE (x) == MEM)
-	{
-	  if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
-	      && current_function_operand (x, Pmode))
-	    fprintf (file, "r14");
-	  else
-	    output_address (XEXP (x, 0));
-	}
-      else
-	output_addr_const (file, x);
-      break;
-
-    default:
-      output_operand_lossage ("invalid %%xn code");
-    }
-}
-
-/* This page contains routines that are used to determine what the function
-   prologue and epilogue code will do and write them out.  */
-
-/*  Return the first register that is required to be saved. 16 if none.  */
-
-int
-first_reg_to_save()
-{
-  int first_reg;
-
-  /* Find lowest numbered live register.  */
-  for (first_reg = 6; first_reg <= 15; first_reg++)
-    if (regs_ever_live[first_reg])
-      break;
-
-  /* If we think that we do not have to save r14, see if it will be used
-     to be sure.  */
-  if (first_reg > 14 && romp_using_r14 ())
-    first_reg = 14;
-
-  return first_reg;
-}
-
-/* Compute the size of the save area in the stack, including the space for
-   the first four incoming arguments.  */
-
-int
-romp_sa_size ()
-{
-  int size;
-  int i;
-
-  /* We have the 4 words corresponding to the arguments passed in registers,
-     4 reserved words, space for static chain, general register save area,
-     and floating-point save area.  */
-  size = 4 + 4 + 1 + (16 - first_reg_to_save ());
-
-  /* The documentation says we have to leave 18 words in the save area if
-     any floating-point registers at all are saved, not the three words
-     per register you might otherwise expect.  */
-  for (i = 2 + (TARGET_FP_REGS != 0); i <= 7; i++)
-    if (regs_ever_live[i + 17])
-      {
-	size += 18;
-	break;
-      }
-
-  return size * 4;
-}
-
-/* Return non-zero if this function makes calls or has fp operations
-   (which are really calls).  */
-
-int
-romp_makes_calls ()
-{
-  rtx insn;
-
-  for (insn = get_insns (); insn; insn = next_insn (insn))
-    {
-      if (GET_CODE (insn) == CALL_INSN)
-	return 1;
-      else if (GET_CODE (insn) == INSN)
-	{
-	  rtx body = PATTERN (insn);
-
-	  if (GET_CODE (body) != USE && GET_CODE (body) != CLOBBER
-	      && GET_CODE (body) != ADDR_VEC
-	      && GET_CODE (body) != ADDR_DIFF_VEC
-	      && get_attr_type (insn) == TYPE_FP)
-	    return 1;
-	}
-    }
-
-  return 0;
-}
-
-/* Return non-zero if this function will use r14 as a pointer to its
-   constant pool.  */
-
-int
-romp_using_r14 ()
-{
-  /* If we are debugging, profiling, have a non-empty constant pool, or
-     call a function, we need r14.  */
-  return (write_symbols != NO_DEBUG || profile_flag || get_pool_size () != 0
-	  || romp_makes_calls ());
-}
-
-/* Return non-zero if this function needs to push space on the stack.  */
-
-int
-romp_pushes_stack ()
-{
-  /* We need to push the stack if a frame pointer is needed (because the
-     stack might be dynamically adjusted), if we are debugging, if the
-     total required size is more than 100 bytes, or if we make calls.  */
-
-  return (frame_pointer_needed || write_symbols != NO_DEBUG
-	  || (romp_sa_size () + get_frame_size ()) > 100
-	  || romp_makes_calls ());
-}
-
-/* Write function prologue.
-
-   We compute the size of the fixed area required as follows:
-
-   We always allocate 4 words for incoming arguments, 4 word reserved, 1
-   word for static link, as many words as required for general register
-   save area, plus 2 words for each FP reg 2-7 that must be saved.  */
-
-void
-output_prolog (file, size)
-     FILE *file;
-     int size;
-{
-  int first_reg;
-  int reg_save_offset;
-  int fp_save = size + current_function_outgoing_args_size;
-
-  init_fpops ();
-
-  /* Add in fixed size plus output argument area.  */
-  size += romp_sa_size () + current_function_outgoing_args_size;
-
-  /* Compute first register to save and perform the save operation if anything
-     needs to be saved.  */
-  first_reg = first_reg_to_save();
-  reg_save_offset = - (4 + 4 + 1 + (16 - first_reg)) * 4;
-  if (first_reg == 15)
-    fprintf (file, "\tst r15,%d(r1)\n", reg_save_offset);
-  else if (first_reg < 16)
-    fprintf (file, "\tstm r%d,%d(r1)\n", first_reg, reg_save_offset);
-
-  /* Set up pointer to data area if it is needed.  */
-  if (romp_using_r14 ())
-    fprintf (file, "\tcas r14,r0,r0\n");
-
-  /* Set up frame pointer if needed.  */
-  if (frame_pointer_needed)
-    fprintf (file, "\tcal r13,-%d(r1)\n", romp_sa_size () + 64);
-
-  /* Push stack if neeeded.  There are a couple of ways of doing this.  */
-  if (romp_pushes_stack ())
-    {
-      if (size >= 32768)
-	{
-	  if (size >= 65536)
-	    {
-	      fprintf (file, "\tcau r0,%d(r0)\n", size >> 16);
-	      fprintf (file, "\toil r0,r0,%d\n", size & 0xffff);
-	    }
-	  else
-	    fprintf (file, "\tcal16 r0,%d(r0)\n", size);
-	  fprintf (file, "\ts r1,r0\n");
-	}
-      else
-	fprintf (file, "\tcal r1,-%d(r1)\n", size);
-    }
-
-  /* Save floating-point registers.  */
-  output_loadsave_fpregs (file, USE,
-			  plus_constant (stack_pointer_rtx, fp_save));
-}
-
-/* Output the offset information used by debuggers.
-   This is the exactly the total_size value of output_epilog
-   which is added to the frame pointer. However the value in the debug
-   table is encoded in a space-saving way as follows:
-
-   The first byte contains two fields: a 2-bit size field and the first
-   6 bits of an offset value. The 2-bit size field is in the high-order
-   position and specifies how many subsequent bytes follow after
-   this one. An offset value is at most 4-bytes long.
-
-   The last 6 bits of the first byte initialize the offset value. In many
-   cases where procedures have small local storage, this is enough and, in
-   this case, the high-order size field is zero so the byte can (almost) be
-   used as is (see below). Thus, the byte value of 0x0d is encodes a offset
-   size of 13 words, or 52 bytes.
-
-   For procedures with a local space larger than 60 bytes, the 6 bits
-   are the high-order 6 bits.  The remaining bytes follow as necessary,
-   in Big Endian order.  Thus, the short value of 16907 (= 16384+523)
-   encodes an offset of 2092 bytes (523 words).
-
-   The total offset value is in words (not bytes), so the final value has to
-   be multiplied by 4 before it can be used in address computations by a
-   debugger.   */
-
-void
-output_encoded_offset (file, reg_offset)
-     FILE *file;
-     unsigned reg_offset;
-{
-  /* Convert the offset value to 4-byte words rather than bytes. */
-  reg_offset = (reg_offset + 3) / 4;
-
-  /* Now output 1-4 bytes in encoded form. */
-  if (reg_offset < (1 << 6))
-    /* Fits into one byte */
-    fprintf (file, "\t.byte %d\n", reg_offset);
-  else if (reg_offset < (1 << (6 + 8)))
-    /* Fits into two bytes */
-    fprintf (file, "\t.short %d\n", (1 << (6 + 8)) + reg_offset);
-  else if (reg_offset < (1 << (6 + 8 + 8)))
-    {
-      /* Fits in three bytes */
-      fprintf (file, "\t.byte %d\n", (2 << 6) + (reg_offset >> ( 6+ 8)));
-      fprintf (file, "\t.short %d\n", reg_offset % (1 << (6 + 8)));
-    }
-  else
-    {
-      /* Use 4 bytes.  */
-      fprintf (file, "\t.short %d", (3 << (6 + 8)) + (reg_offset >> (6 + 8)));
-      fprintf (file, "\t.short %d\n", reg_offset % (1 << (6 + 8)));
-    }
-}
-
-/* Write function epilogue.  */
-
-void
-output_epilog (file, size)
-     FILE *file;
-     int size;
-{
-  int first_reg = first_reg_to_save();
-  int pushes_stack = romp_pushes_stack ();
-  int reg_save_offset = - ((16 - first_reg) + 1 + 4 + 4) * 4;
-  int total_size = (size + romp_sa_size ()
-		    + current_function_outgoing_args_size);
-  int fp_save = size + current_function_outgoing_args_size;
-  int long_frame = total_size >= 32768;
-  rtx insn = get_last_insn ();
-  int write_code = 1;
-
-  int nargs = 0;		/* words of arguments */
-  tree argptr;
-
-  /* Compute the number of words of arguments.  Since this is just for
-     the traceback table, we ignore arguments that don't have a size or
-     don't have a fixed size.  */
-
-  for (argptr = DECL_ARGUMENTS (current_function_decl);
-       argptr; argptr = TREE_CHAIN (argptr))
-    {
-      int this_size = int_size_in_bytes (TREE_TYPE (argptr));
-
-      if (this_size > 0)
-	nargs += (this_size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-    }
-  
-  /* If the last insn was a BARRIER, we don't have to write anything except
-     the trace table.  */
-  if (GET_CODE (insn) == NOTE)
-    insn = prev_nonnote_insn (insn);
-  if (insn && GET_CODE (insn) == BARRIER)
-    write_code = 0;
-
-  /* Restore floating-point registers.  */
-  if (write_code)
-    output_loadsave_fpregs (file, CLOBBER,
-			    gen_rtx (PLUS, Pmode, gen_rtx (REG, Pmode, 1),
-				     GEN_INT (fp_save)));
-
-  /* If we push the stack and do not have size > 32K, adjust the register
-     save location to the current position of sp.  Otherwise, if long frame,
-     restore sp from fp.  */
-  if (pushes_stack && ! long_frame)
-    reg_save_offset += total_size;
-  else if (long_frame && write_code)
-    fprintf (file, "\tcal r1,%d(r13)\n", romp_sa_size () + 64);
-
-  /* Restore registers.  */
-  if (first_reg == 15 && write_code)
-    fprintf (file, "\tl r15,%d(r1)\n", reg_save_offset);
-  else if (first_reg < 16 && write_code)
-    fprintf (file, "\tlm r%d,%d(r1)\n", first_reg, reg_save_offset);
-  if (first_reg == 16) first_reg = 0;
-
-  /* Handle popping stack, if needed and write debug table entry.  */
-  if (pushes_stack)
-    {
-      if (write_code)
-	{
-	  if (long_frame)
-	    fprintf (file, "\tbr r15\n");
-	  else
-	    fprintf (file, "\tbrx r15\n\tcal r1,%d(r1)\n", total_size);
-	}
-
-      /* Table header (0xdf), usual-type stack frame (0x07),
-	 table header (0xdf), and first register saved.
-
-	 The final 0x08 means that there is a byte following this one
-	 describing the number of parameter words and the register used as
-	 stack pointer.
-
-	 If GCC passed floating-point parameters in floating-point registers,
-	 it would be necessary to change the final byte from 0x08 to 0x0c.
-	 Also an additional entry byte would be need to be emitted to specify
-	 the first floating-point register.
-
-	 (See also Section 11 (Trace Tables) in ``IBM/4.3 Linkage Convention,''
-	 pages IBM/4.3-PSD:5-7 of Volume III of the IBM Academic Operating
-	 System Manual dated July 1987.)  */
-
-      fprintf (file, "\t.long 0x%x\n", 0xdf07df08 + first_reg * 0x10);
-
-      if (nargs > 15) nargs = 15;
-
-      /* The number of parameter words and the register used as the stack
-	 pointer (encoded here as r1).
-
-	 Note: The MetWare Hich C Compiler R2.1y actually gets this wrong;
-	 it erroneously lists r13 but uses r1 as the stack too. But a bug in
-	 dbx 1.5 nullifies this mistake---most of the time.
-         (Dbx retrieves the value of r13 saved on the stack which is often
-	 the value of r1 before the call.)  */
-
-      fprintf (file, "\t.byte 0x%x1\n", nargs);
-      output_encoded_offset (file, total_size);
-    }
-  else
-    {
-      if (write_code)
-	fprintf (file, "\tbr r15\n");
-
-      /* Table header (0xdf), no stack frame (0x02),
-	 table header (0xdf) and no parameters saved (0x00).
-
-	 If GCC passed floating-point parameters in floating-point registers,
-	 it might be necessary to change the final byte from 0x00 to 0x04.
-	 Also a byte would be needed to specify the first floating-point
-	 register.  */
-      fprintf (file, "\t.long 0xdf02df00\n");
-    }
-
-  /* Output any pending floating-point operations.  */
-  output_fpops (file);
-}
-
-/* For the ROMP we need to make new SYMBOL_REFs for the actual name of a
-   called routine.  To keep them unique we maintain a hash table of all
-   that have been created so far.  */
-
-struct symref_hashent {
-  rtx symref;			/* Created SYMBOL_REF rtx.  */
-  struct symref_hashent *next;	/* Next with same hash code.  */
-};
-
-#define SYMHASHSIZE 151
-#define HASHBITS 65535
-
-/* Define the hash table itself.  */
-
-static struct symref_hashent *symref_hash_table[SYMHASHSIZE];
-
-/* Given a name (allocable in temporary storage), return a SYMBOL_REF
-   for the name.  The rtx is allocated from the current rtl_obstack, while
-   the name string is allocated from the permanent obstack.  */
-rtx
-get_symref (name)
-     register char *name;
-{
-  extern struct obstack permanent_obstack;
-  register char *sp = name;
-  unsigned int hash = 0;
-  struct symref_hashent *p, **last_p;
-
-  /* Compute the hash code for the string.  */
-  while (*sp)
-    hash = (hash << 4) + *sp++;
-
-  /* Search for a matching entry in the hash table, keeping track of the
-     insertion location as we do so.  */
-  hash = (hash & HASHBITS) % SYMHASHSIZE;
-  for (last_p = &symref_hash_table[hash], p = *last_p;
-       p; last_p = &p->next, p = *last_p)
-    if (strcmp (name, XSTR (p->symref, 0)) == 0)
-      break;
-
-  /* If couldn't find matching SYMBOL_REF, make a new one.  */
-  if (p == 0)
-    {
-      /* Ensure SYMBOL_REF will stay around.  */
-      end_temporary_allocation ();
-      p = *last_p = (struct symref_hashent *)
-			permalloc (sizeof (struct symref_hashent));
-      p->symref = gen_rtx (SYMBOL_REF, Pmode,
-			   obstack_copy0 (&permanent_obstack,
-					  name, strlen (name)));
-      p->next = 0;
-      resume_temporary_allocation ();
-    }
-
-  return p->symref;
-}
-
-/* Validate the precision of a floating-point operation.
-
-   We merge conversions from integers and between floating-point modes into
-   the insn.  However, this must not effect the desired precision of the
-   insn.  The RT floating-point system uses the widest of the operand modes.
-   If this should be a double-precision insn, ensure that one operand
-   passed to the floating-point processor has double mode.
-
-   Note that since we don't check anything if the mode is single precision,
-   it, strictly speaking, isn't necessary to call this for those insns.
-   However, we do so in case something else needs to be checked in the
-   future.
-
-   This routine returns 1 if the operation is OK.  */
-
-int
-check_precision (opmode, op1, op2)
-     enum machine_mode opmode;
-     rtx op1, op2;
-{
-  if (opmode == SFmode)
-    return 1;
-
-  /* If operand is not a conversion from an integer mode or an extension from
-     single-precision, it must be a double-precision value.  */
-  if (GET_CODE (op1) != FLOAT && GET_CODE (op1) != FLOAT_EXTEND)
-    return 1;
-
-  if (op2 && GET_CODE (op2) != FLOAT && GET_CODE (op2) != FLOAT_EXTEND)
-    return 1;
-
-  return 0;
-}
-
-/* Floating-point on the RT is done by creating an operation block in the data
-   area that describes the operation.  If two floating-point operations are the
-   same in a single function, they can use the same block.
-
-   These routines are responsible for managing these blocks.  */
-
-/* Structure to describe a floating-point operation.  */
-
-struct fp_op {
-  struct fp_op *next_same_hash;		/* Next op with same hash code. */
-  struct fp_op *next_in_mem;		/* Next op in memory. */
-  int mem_offset;			/* Offset from data area.  */
-  short size;				/* Size of block in bytes.  */
-  short noperands;			/* Number of operands in block.  */
-  rtx ops[3];				/* RTL for operands. */
-  enum rtx_code opcode;			/* Operation being performed.  */
-};
-
-/* Size of hash table.  */
-#define FP_HASH_SIZE 101
-
-/* Hash table of floating-point operation blocks.  */
-static struct fp_op *fp_hash_table[FP_HASH_SIZE];
-
-/* First floating-point block in data area.  */
-static struct fp_op *first_fpop;
-
-/* Last block in data area so far.  */
-static struct fp_op *last_fpop_in_mem;
-
-/* Subroutine number in file, to get unique "LF" labels.  */
-static int subr_number = 0;
-
-/* Current word offset in data area (includes header and any constant pool). */
-int data_offset;
-
-/* Compute hash code for an RTX used in floating-point.  */
-
-static unsigned int
-hash_rtx (x)
-     register rtx x;
-{
-  register unsigned int hash = (((int) GET_CODE (x) << 10)
-				+ ((int) GET_MODE (x) << 20));
-  register int i;
-  register char *fmt = GET_RTX_FORMAT (GET_CODE (x));
-
-  for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
-    if (fmt[i] == 'e')
-      hash += hash_rtx (XEXP (x, i));
-    else if (fmt[i] == 'u')
-      hash += (unsigned HOST_WIDE_INT) XEXP (x, i);
-    else if (fmt[i] == 'i')
-      hash += XINT (x, i);
-    else if (fmt[i] == 's')
-      hash += (unsigned HOST_WIDE_INT) XSTR (x, i);
-
-  return hash;
-}
-
-/* Given an operation code and up to three operands, return a character string
-   corresponding to the code to emit to branch to a floating-point operation
-   block.  INSN is provided to see if the delay slot has been filled or not.
-
-   A new floating-point operation block is created if this operation has not
-   been seen before.  */
-
-char *
-output_fpop (code, op0, op1, op2, insn)
-     enum rtx_code code;
-     rtx op0, op1, op2;
-     rtx insn;
-{
-  static char outbuf[40];
-  unsigned int hash, hash0, hash1, hash2;
-  int size, i;
-  register struct fp_op *fpop, *last_fpop;
-  int dyadic = (op2 != 0);
-  enum machine_mode opmode;
-  int noperands;
-  rtx tem;
-  unsigned int tem_hash;
-  int fr0_avail = 0;
-
-  /* Compute hash code for each operand.  If the operation is commutative,
-     put the one with the smaller hash code first.  This will make us see
-     more operations as identical.  */
-  hash0 = op0 ? hash_rtx (op0) : 0;
-  hash1 = op1 ? hash_rtx (op1) : 0;
-  hash2 = op2 ? hash_rtx (op2) : 0;
-
-  if (hash0 > hash1 && code == EQ)
-    {
-      tem = op0; op0 = op1; op1 = tem;
-      tem_hash = hash0; hash0 = hash1; hash1 = tem_hash;
-    }
-  else if (hash1 > hash2 && (code == PLUS || code == MULT))
-    {
-      tem = op1; op1 = op2; op2 = tem;
-      tem_hash = hash1; hash1 = hash2; hash2 = tem_hash;
-    }
-
-  /* If operation is commutative and the first and third operands are equal,
-     swap the second and third operands.  Note that we must consider two
-     operands equal if they are the same register even if different modes.  */
-  if (op2 && (code == PLUS || code == MULT)
-      && (rtx_equal_p (op0, op2)
-	  || (GET_CODE (op0) == REG && GET_CODE (op2) == REG
-	      && REGNO (op0) == REGNO (op2))))
-    {
-      tem = op1; op1 = op2; op2 = tem;
-      tem_hash = hash1; hash1 = hash2; hash2 = tem_hash;
-    }
-
-  /* If the first and second operands are the same, merge them.  Don't do this
-     for SFmode or SImode in general registers because this triggers a bug in
-     the RT fp code.  */
-  if (op1 && rtx_equal_p (op0, op1)
-      && code != EQ && code != GE && code != SET
-      && ((GET_MODE (op1) != SFmode && GET_MODE (op1) != SImode)
-	  || GET_CODE (op0) != REG || FP_REGNO_P (REGNO (op0))))
-    {
-      op1 = op2;
-      op2 = 0;
-    }
-
-  noperands = 1 + (op1 != 0) + (op2 != 0);
-
-  /* Compute hash code for entire expression and see if operation block
-     already exists.  */
-  hash = ((int) code << 13) + (hash0 << 2) + (hash1 << 1) + hash2;
-
-  hash %= FP_HASH_SIZE;
-  for (fpop = fp_hash_table[hash], last_fpop = 0;
-       fpop;
-       last_fpop = fpop, fpop = fpop->next_same_hash)
-    if (fpop->opcode == code && noperands == fpop->noperands
-	&& (op0 == 0 || rtx_equal_p (op0, fpop->ops[0]))
-	&& (op1 == 0 || rtx_equal_p (op1, fpop->ops[1]))
-	&& (op2 == 0 || rtx_equal_p (op2, fpop->ops[2])))
-      goto win;
-
-  /* We have never seen this operation before.  */
-  fpop = (struct fp_op *) oballoc (sizeof (struct fp_op));
-  fpop->mem_offset = data_offset;
-  fpop->opcode = code;
-  fpop->noperands = noperands;
-  fpop->ops[0] = op0;
-  fpop->ops[1] = op1;
-  fpop->ops[2] = op2;
-
-  /* Compute the size using the rules in Appendix A of the RT Linkage
-     Convention (4.3/RT-PSD:5) manual.  These rules are a bit ambiguous,
-     but if we guess wrong, it will effect only efficiency, not correctness. */
-
-  /* Size = 24 + 32 for each non-fp (or fr7) */
-  size = 24;
-  if (op0 && (GET_CODE (op0) != REG
-	      || ! FP_REGNO_P (REGNO (op0)) || REGNO (op0) == 23))
-    size += 32;
-
-  if (op1 && (GET_CODE (op1) != REG
-	      || ! FP_REGNO_P (REGNO (op1)) || REGNO (op1) == 23))
-    size += 32;
-
-  if (op2 && (GET_CODE (op2) != REG
-	      || ! FP_REGNO_P (REGNO (op2)) || REGNO (op2) == 23))
-    size += 32;
-
-  /* Size + 12 for each conversion.  First get operation mode.  */
-  if ((op0 && GET_MODE (op0) == DFmode)
-      || (op1 && GET_MODE (op1) == DFmode)
-      || (op2 && GET_MODE (op2) == DFmode))
-    opmode = DFmode;
-  else
-    opmode = SFmode;
-
-  if (op0 && GET_MODE (op0) != opmode)
-    size += 12;
-  if (op1 && GET_MODE (op1) != opmode)
-    size += 12;
-  if (op2 && GET_MODE (op2) != opmode)
-    size += 12;
-
-  /* 12 more if first and third operand types not the same. */
-  if (op2 && GET_MODE (op0) != GET_MODE (op2))
-    size += 12;
-
-  /* CMP and CMPT need additional.  Also, compute size of save/restore here. */
-  if (code == EQ)
-    size += 32;
-  else if (code == GE)
-    size += 64;
-  else if (code == USE || code == CLOBBER)
-    {
-      /* 34 + 24 for each additional register plus 8 if fr7 saved.  (We
-         call it 36 because we need to keep the block length a multiple
-	 of four.  */
-      size = 36 - 24;
-      for (i = 0; i <= 7; i++)
-	if (INTVAL (op0) & (1 << (7-i)))
-	  size += 24 + 8 * (i == 7);
-    }
-
-  /* We provide no general-purpose scratch registers.  */
-  size +=16;
-
-  /* No floating-point scratch registers are provided.  Compute extra
-     length due to this.  This logic is that shown in the referenced
-     appendix.  */
-
-  i = 0;
-  if (op0 && GET_CODE (op0) == REG && FP_REGNO_P (REGNO (op0)))
-    i++;
-  if (op1 && GET_CODE (op1) == REG && FP_REGNO_P (REGNO (op1)))
-    i++;
-  if (op2 && GET_CODE (op2) == REG && FP_REGNO_P (REGNO (op2)))
-    i++;
-
-  if ((op0 == 0 || GET_CODE (op0) != REG || REGNO(op0) != 17)
-      && (op1 == 0 || GET_CODE (op1) != REG || REGNO(op1) != 17)
-      && (op2 == 0 || GET_CODE (op2) != REG || REGNO(op2) != 17))
-    fr0_avail = 1;
-
-  if (dyadic)
-    {
-      if (i == 0)
-	size += fr0_avail ? 64 : 112;
-      else if (fpop->noperands == 2 && i == 1)
-	size += fr0_avail ? 0 : 64;
-      else if (fpop->noperands == 3)
-	{
-	  if (GET_CODE (op0) == REG && FP_REGNO_P (REGNO (op0))
-	      && GET_CODE (op2) == REG && FP_REGNO_P (REGNO (op2)))
-	    {
-	      if (REGNO (op0) == REGNO (op2))
-#if 1
-		/* This triggers a bug on the RT. */
-		abort ();
-#else
-		size += fr0_avail ? 0 : 64;
-#endif
-	    }
-	  else
-	    {
-	      i = 0;
-	      if (GET_CODE (op0) == REG && FP_REGNO_P (REGNO (op0)))
-		i++;
-	      if (GET_CODE (op2) == REG && FP_REGNO_P (REGNO (op2)))
-		i++;
-	      if (i == 0)
-		size += fr0_avail ? 64 : 112;
-	      else if (i == 1)
-		size += fr0_avail ? 0 : 64;
-	    }
-	}
-    }
-  else if (code != USE && code != CLOBBER
-	   && (GET_CODE (op0) != REG || ! FP_REGNO_P (REGNO (op0))))
-    size += 64;
-    
-  if (! TARGET_FULL_FP_BLOCKS)
-    {
-      /* If we are not to pad the blocks, just compute its actual length.  */
-      size = 12;	/* Header + opcode */
-      if (code == USE || code == CLOBBER)
-        size += 2;
-      else
-        {
-	  if (op0) size += 2;
-	  if (op1) size += 2;
-	  if (op2) size += 2;
-	}
-
-      /* If in the middle of a word, round.  */
-      if (size % UNITS_PER_WORD)
-	size += 2;
-	
-      /* Handle any immediates.  */
-      if (code != USE && code != CLOBBER && op0 && GET_CODE (op0) != REG)
-        size += 4;
-      if (op1 && GET_CODE (op1) != REG)
-        size += 4;
-      if (op2 && GET_CODE (op2) != REG)
-        size += 4;
-
-      if (code != USE && code != CLOBBER && 
-	  op0 && GET_CODE (op0) == CONST_DOUBLE && GET_MODE (op0) == DFmode)
-        size += 4;
-      if (op1 && GET_CODE (op1) == CONST_DOUBLE && GET_MODE (op1) == DFmode)
-        size += 4;
-      if (op2 && GET_CODE (op2) == CONST_DOUBLE && GET_MODE (op2) == DFmode)
-        size += 4;
-    }
-
-  /* Done with size computation!  Chain this in. */
-  fpop->size = size;
-  data_offset += size / UNITS_PER_WORD;
-  fpop->next_in_mem = 0;
-  fpop->next_same_hash = 0;
-
-  if (last_fpop_in_mem)
-    last_fpop_in_mem->next_in_mem = fpop;
-  else
-    first_fpop = fpop;
-  last_fpop_in_mem = fpop;
-
-  if (last_fpop)
-    last_fpop->next_same_hash = fpop;
-  else
-    fp_hash_table[hash] = fpop;
-
-win:
-  /* FPOP describes the operation to be performed.  Return a string to branch
-     to it.  */
-  if (fpop->mem_offset < 32768 / UNITS_PER_WORD)
-    sprintf (outbuf, "cal r15,%d(r14)\n\tbalr%s r15,r15",
-	     fpop->mem_offset * UNITS_PER_WORD,
-	     dbr_sequence_length () ? "x" : "");
-  else
-    sprintf (outbuf, "get r15,$L%dF%d\n\tbalr%s r15,r15",
-	     subr_number, fpop->mem_offset * UNITS_PER_WORD,
-	     dbr_sequence_length () ? "x" : "");
-  return outbuf;
-}
-
-/* If necessary, output a floating-point operation to save or restore all
-   floating-point registers.
-
-   file is the file to write the operation to, CODE is USE for save, CLOBBER
-   for restore, and ADDR is the address of the same area, as RTL.  */
-
-static void
-output_loadsave_fpregs (file, code, addr)
-     FILE *file;
-     enum rtx_code code;
-     rtx addr;
-{
-  register int i;
-  register int mask = 0;
-
-  for (i = 2 + (TARGET_FP_REGS != 0); i <= 7; i++)
-    if (regs_ever_live[i + 17])
-      mask |= 1 << (7 - i);
-
-  if (mask)
-    fprintf (file, "\t%s\n",
-	     output_fpop (code, GEN_INT (mask),
-				gen_rtx (MEM, Pmode, addr),
-				0, const0_rtx));
-
-}
-
-/* Output any floating-point operations at the end of the routine.  */
-
-static void
-output_fpops (file)
-     FILE *file;
-{
-  register struct fp_op *fpop;
-  register int size_so_far;
-  register int i;
-  rtx immed[3];
-
-  if (first_fpop == 0)
-    return;
-
-  data_section ();
-
-  ASM_OUTPUT_ALIGN (file, 2);
-
-  for (fpop = first_fpop; fpop; fpop = fpop->next_in_mem)
-    {
-      if (fpop->mem_offset < 32768 / UNITS_PER_WORD)
-	fprintf (file, "# data area offset = %d\n",
-		 fpop->mem_offset * UNITS_PER_WORD);
-      else
-	fprintf (file, "L%dF%d:\n",
-		 subr_number, fpop->mem_offset * UNITS_PER_WORD);
-
-      fprintf (file, "\tcas r0,r15,r0\n");
-      fprintf (file, "\t.long FPGLUE\n");
-      switch (fpop->opcode)
-	{
-	case USE:
-	  fprintf (file, "\t.byte 0x1d\t# STOREM\n");
-	  break;
-	case CLOBBER:
-	  fprintf (file, "\t.byte 0x0f\t# LOADM\n");
-	  break;
-	case ABS:
-	  fprintf (file, "\t.byte 0x00\t# ABS\n");
-	  break;
-	case PLUS:
-	  fprintf (file, "\t.byte 0x02\t# ADD\n");
-	  break;
-	case EQ:
-	  fprintf (file, "\t.byte 0x07\t# CMP\n");
-	  break;
-	case GE:
-	  fprintf (file, "\t.byte 0x08\t# CMPT\n");
-	  break;
-	case DIV:
-	  fprintf (file, "\t.byte 0x0c\t# DIV\n");
-	  break;
-	case SET:
-	  fprintf (file, "\t.byte 0x14\t# MOVE\n");
-	  break;
-	case MULT:
-	  fprintf (file, "\t.byte 0x15\t# MUL\n");
-	  break;
-	case NEG:
-	  fprintf (file, "\t.byte 0x16\t# NEG\n");
-	  break;
-	case SQRT:
-	  fprintf (file, "\t.byte 0x1c\t# SQRT\n");
-	  break;
-	case MINUS:
-	  fprintf (file, "\t.byte 0x1e\t# SUB\n");
-	  break;
-	default:
-	  abort ();
-	}
-
-      fprintf (file, "\t.byte %d\n", fpop->noperands);
-      fprintf (file, "\t.short 0x8001\n");
-      
-      if ((fpop->ops[0] == 0
-	   || GET_CODE (fpop->ops[0]) != REG || REGNO(fpop->ops[0]) != 17)
-	  && (fpop->ops[1] == 0 || GET_CODE (fpop->ops[1]) != REG
-	      || REGNO(fpop->ops[1]) != 17)
-	  && (fpop->ops[2] == 0 || GET_CODE (fpop->ops[2]) != REG
-	      || REGNO(fpop->ops[2]) != 17))
-	fprintf (file, "\t.byte %d, 0x80\n", fpop->size);
-      else
-	fprintf (file, "\t.byte %d, 0\n", fpop->size);
-      size_so_far = 12;
-      for (i = 0; i < fpop->noperands; i++)
-	{
-	  register int type;
-	  register int opbyte;
-	  register char *desc0;
-	  char desc1[50];
-
-	  immed[i] = 0;
-	  switch (GET_MODE (fpop->ops[i]))
-	    {
-	    case SImode:
-	    case VOIDmode:
-	      desc0 = "int";
-	      type = 0;
-	      break;
-	    case SFmode:
-	      desc0 = "float";
-	      type = 2;
-	      break;
-	    case DFmode:
-	      desc0 = "double";
-	      type = 3;
-	      break;
-	    default:
-	      abort ();
-	    }
-
-	  switch (GET_CODE (fpop->ops[i]))
-	    {
-	    case REG:
-	      strcpy(desc1, reg_names[REGNO (fpop->ops[i])]);
-	      if (FP_REGNO_P (REGNO (fpop->ops[i])))
-		{
-		  type += 0x10;
-		  opbyte = REGNO (fpop->ops[i]) - 17;
-		}
-	      else
-		{
-		  type += 0x00;
-		  opbyte = REGNO (fpop->ops[i]);
-		  if (type == 3)
-		    opbyte = (opbyte << 4) + opbyte + 1;
-		}
-	      break;
-
-	    case MEM:
-	      type += 0x30;
-	      if (GET_CODE (XEXP (fpop->ops[i], 0)) == PLUS)
-		{
-		  immed[i] = XEXP (XEXP (fpop->ops[i], 0), 1);
-		  opbyte = REGNO (XEXP (XEXP (fpop->ops[i], 0), 0));
-		  if (GET_CODE (immed[i]) == CONST_INT)
-		    sprintf (desc1, "%d(%s)", INTVAL (immed[i]),
-			     reg_names[opbyte]);
-		  else
-		    sprintf (desc1, "<memory> (%s)", reg_names[opbyte]);
-		}
-	      else if (GET_CODE (XEXP (fpop->ops[i], 0)) == REG)
-		{
-		  opbyte = REGNO (XEXP (fpop->ops[i], 0));
-		  immed[i] = const0_rtx;
- 		  sprintf (desc1, "(%s)", reg_names[opbyte]);
-		}
-	      else
-		{
-		  immed[i] = XEXP (fpop->ops[i], 0);
-		  opbyte = 0;
-		  sprintf(desc1, "<memory>");
-		}
-	      break;
-
-	    case CONST_INT:
-	    case CONST_DOUBLE:
-	    case CONST:
-	    case SYMBOL_REF:
-	    case LABEL_REF:
-	      type += 0x20;
-	      opbyte = 0;
-	      immed[i] = fpop->ops[i];
-	      desc1[0] = '$';
-	      desc1[1] = '\0';
-	      break;
-
-	    default:
-	      abort ();
-	    }
-
-	  /* Save/restore is special.  */
-	  if (i == 0 && (fpop->opcode == USE || fpop->opcode == CLOBBER))
-	    type = 0xff, opbyte = INTVAL (fpop->ops[0]), immed[i] = 0;
-
-	  fprintf (file, "\t.byte 0x%x,0x%x # (%s) %s\n",
-		   type, opbyte, desc0, desc1);
-
-	  size_so_far += 2;
-	}
-
-      /* If in the middle of a word, round.  */
-      if (size_so_far % UNITS_PER_WORD)
-	{
-	  fprintf (file, "\t.space 2\n");
-	  size_so_far += 2;
-	}
-
-      for (i = 0; i < fpop->noperands; i++)
-	if (immed[i])
-	  switch (GET_MODE (immed[i]))
-	    {
-	    case SImode:
-	    case VOIDmode:
-	      size_so_far += 4;
-	      fprintf (file, "\t.long ");
-	      output_addr_const (file, immed[i]);
-	      fprintf (file, "\n");
-	      break;
-
-	    case DFmode:
-	      size_so_far += 4;
-	    case SFmode:
-	      size_so_far += 4;
-	      if (GET_CODE (immed[i]) == CONST_DOUBLE)
-		{
-		  union real_extract u;
-
-		  bcopy ((char *) &CONST_DOUBLE_LOW (immed[i]),
-			 (char *) &u, sizeof u);
-		  if (GET_MODE (immed[i]) == DFmode)
-		    ASM_OUTPUT_DOUBLE (file, u.d);
-		  else
-		    ASM_OUTPUT_FLOAT (file, u.d);
-		}
-	      else
-		abort ();
-	      break;
-
-	    default:
-	      abort ();
-	    }
-	
-      if (size_so_far != fpop->size)
-        {
-          if (TARGET_FULL_FP_BLOCKS)
-	    fprintf (file, "\t.space %d\n", fpop->size - size_so_far);
-	  else
-	    abort ();
-	}
-    }
-
-  /* Update for next subroutine.  */
-  subr_number++;
-  text_section ();
-}
-
- /* Initialize floating-point operation table.  */
-
-static void
-init_fpops()
-{
-  register int i;
-
-  first_fpop = last_fpop_in_mem = 0;
-  for (i = 0; i < FP_HASH_SIZE; i++)
-    fp_hash_table[i] = 0;
-}
-
-/* Return the offset value of an automatic variable (N_LSYM) having
-   the given offset. Basically, we correct by going from a frame pointer to
-   stack pointer value.
-*/
-
-int
-romp_debugger_auto_correction(offset)
-     int offset;
-{
-  int fp_to_sp;
-
-  /* We really want to go from STACK_POINTER_REGNUM to
-     FRAME_POINTER_REGNUM, but this isn't defined. So go the other
-     direction and negate. */
-  INITIAL_ELIMINATION_OFFSET (FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM,
-			      fp_to_sp);
-
-  /* The offset value points somewhere between the frame pointer and
-     the stack pointer. What is up from the frame pointer is down from the
-     stack pointer. Therefore the negation in the offset value too. */
-
-  return -(offset+fp_to_sp+4);
-}
-
-/* Return the offset value of an argument having
-   the given offset. Basically, we correct by going from a arg pointer to
-   stack pointer value. */
-
-int
-romp_debugger_arg_correction (offset)
-     int offset;
-{
-  int fp_to_argp;
-
-  INITIAL_ELIMINATION_OFFSET (ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM,
-			      fp_to_argp);
-
-  /* Actually, something different happens if offset is from a floating-point
-     register argument, but we don't handle it here.  */
-
-  return (offset - fp_to_argp);
-}
diff --git a/gcc/config/romp/romp.h b/gcc/config/romp/romp.h
deleted file mode 100755
index 82a0186..0000000
--- a/gcc/config/romp/romp.h
+++ /dev/null
@@ -1,1636 +0,0 @@
-/* Definitions of target machine for GNU compiler, for ROMP chip.
-   Copyright (C) 1989, 1991, 1993, 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dibm032 -Dunix -Asystem(unix) -Asystem(bsd)  -Acpu(ibm032) -Amachine(ibm032)"
-
-/* Print subsidiary information on the compiler version in use.  */
-#define TARGET_VERSION ;
-
-/* Add -lfp_p when running with -p or -pg.  */
-#define LIB_SPEC "%{pg:-lfp_p}%{p:-lfp_p} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-/* Flag to generate all multiplies as an in-line sequence of multiply-step
-   insns instead of calling a library routine.  */
-#define TARGET_IN_LINE_MUL (target_flags & 1)
-
-/* Flag to generate padded floating-point data blocks.  Otherwise, we generate
-   them the minimum size.  This trades off execution speed against size.  */
-#define TARGET_FULL_FP_BLOCKS (target_flags & 2)
-
-/* Flag to pass and return floating point values in floating point registers.
-   Since this violates the linkage convention, we feel free to destroy fr2
-   and fr3 on function calls.
-   fr1-fr3 are used to pass the arguments. */
-#define TARGET_FP_REGS (target_flags & 4)
-
-/* Flag to return structures of more than one word in memory.  This is for
-   compatibility with the MetaWare HighC (hc) compiler.  */
-#define TARGET_HC_STRUCT_RETURN (target_flags & 010)
-
-extern int target_flags;
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES		\
-  { {"in-line-mul", 1},		\
-    {"call-lib-mul", -1},	\
-    {"full-fp-blocks", 2},	\
-    {"minimum-fp-blocks", -2},	\
-    {"fp-arg-in-fpregs", 4},	\
-    {"fp-arg-in-gregs", -4},	\
-    {"hc-struct-return", 010},  \
-    {"nohc-struct-return", - 010}, \
-    { "", TARGET_DEFAULT}}
-
-#define TARGET_DEFAULT 3
-
-/* target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields. */
-/* That is true on ROMP. */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is true on ROMP.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered. 
-
-   For ROMP we can decide arbitrarily since there are no machine instructions
-   for them.  Might as well be consistent with bits and bytes. */
-#define WORDS_BIG_ENDIAN 1
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 16
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  (TREE_CODE (EXP) == STRING_CST	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   ROMP has 16 fullword registers and 8 floating point registers.
-
-   In addition, the difference between the frame and argument pointers is
-   a function of the number of registers saved, so we need to have a register
-   to use for AP that will later be eliminated in favor of sp or fp.  This is
-   a normal register, but it is fixed.  */
-
-#define FIRST_PSEUDO_REGISTER 25
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   On ROMP, r1 is used for the stack and r14 is used for a
-   data area pointer.
-
-   HACK WARNING:  On the RT, there is a bug in code generation for
-   the MC68881 when the first and third operands are the same floating-point
-   register.  See the definition of the FINAL_PRESCAN_INSN macro for details.
-   Here we need to reserve fr0 for this purpose.  */
-#define FIXED_REGISTERS  \
- {0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	\
-  1,							\
-  1, 0, 0, 0, 0, 0, 0, 0}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS				\
- {1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	\
-  1,							\
-  1, 1, 0, 0, 0, 0, 0, 0}
-
-/* List the order in which to allocate registers.  Each register must be
-   listed once, even those in FIXED_REGISTERS.
-
-   We allocate in the following order:
-	fr0, fr1	(not saved)
-	fr2 ... fr6
-	fr7		(more expensive for some FPA's)
-	r0		(not saved and won't conflict with parameter register)
-	r4, r3, r2	(not saved, highest used first to make less conflict)
-	r5		(not saved, but forces r6 to be saved if DI/DFmode)
-	r15, r14, r13, r12, r11, r10, r9, r8, r7, r6 (less to save)
-	r1, ap 			*/
-
-#define REG_ALLOC_ORDER		\
-  {17, 18,			\
-   19, 20, 21, 22, 23,		\
-   24,				\
-   0,				\
-   4, 3, 2,			\
-   5,				\
-   15, 14, 13, 12, 11, 10,	\
-   9, 8, 7, 6, 			\
-   1, 16}
-
-/* True if register is floating-point.  */
-#define FP_REGNO_P(N) ((N) >= 17)
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On ROMP, ordinary registers hold 32 bits worth;
-   a single floating point register is always enough for
-   anything that can be stored in them at all.  */
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  (FP_REGNO_P (REGNO) ? GET_MODE_NUNITS (MODE)	\
-   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On ROMP, the cpu registers can hold any mode but the float registers
-   can hold only floating point. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-  (! FP_REGNO_P (REGNO) || GET_MODE_CLASS (MODE) == MODE_FLOAT	\
-   || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  ((GET_MODE_CLASS (MODE1) == MODE_FLOAT		\
-    || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)	\
-   == (GET_MODE_CLASS (MODE2) == MODE_FLOAT		\
-       || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
-
-/* A C expression returning the cost of moving data from a register of class
-   CLASS1 to one of CLASS2.
-
-   On the ROMP, access to floating-point registers is expensive (even between
-   two FP regs.)  */
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)	\
-  (2 + 10 * ((CLASS1) == FP_REGS) + 10 * (CLASS2 == FP_REGS))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* ROMP pc isn't overloaded on a register that the compiler knows about.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 1
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 13
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 16
-
-/* Place to put static chain when calling a function that requires it.  */
-#define STATIC_CHAIN							\
-  gen_rtx (MEM, Pmode, gen_rtx (PLUS, Pmode, stack_pointer_rtx,		\
-				GEN_INT (-36)))
-
-/* Place where static chain is found upon entry to routine.  */
-#define STATIC_CHAIN_INCOMING						\
-  gen_rtx (MEM, Pmode, gen_rtx (PLUS, Pmode, arg_pointer_rtx,		\
-				GEN_INT (-20)))
-
-/* Place that structure value return address is placed.
-
-   On the ROMP, it is passed as an extra parameter.  */
-#define STRUCT_VALUE	0
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-/* The ROMP has two types of registers, general and floating-point.
-
-   However, r0 is special in that it cannot be used as a base register.
-   So make a class for registers valid as base registers.
-
-   For floating-point support, add classes that just consist of r0 and
-   r15, respectively.  */
-
-enum reg_class { NO_REGS, R0_REGS, R15_REGS, BASE_REGS, GENERAL_REGS,
-		 FP_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "R0_REGS", "R15_REGS", "BASE_REGS", "GENERAL_REGS", \
-  "FP_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS {0, 0x00001, 0x08000, 0x1fffe, 0x1ffff,  \
-			    0x1fe0000, 0x1ffffff }
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) \
- ((REGNO) == 0 ? GENERAL_REGS : FP_REGNO_P (REGNO) ? FP_REGS : BASE_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS BASE_REGS
-#define BASE_REG_CLASS BASE_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'f' ? FP_REGS		\
-   : (C) == 'b' ? BASE_REGS	\
-   : (C) == 'z' ? R0_REGS	\
-   : (C) == 't' ? R15_REGS	\
-   : NO_REGS)
-
-/* The letters I, J, K, L, M, N, and P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   `I' is constants less than 16
-   `J' is negative constants greater than -16
-   `K' is the range for a normal D insn.
-   `L' is a constant with only the low-order 16 bits set
-   `M' is a constant with only the high-order 16 bits set
-   `N' is a single-bit constant
-   `O' is a constant with either the high-order or low-order 16 bits all ones
-   `P' is the complement of a single-bit constant
-  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  		   \
-   ( (C) == 'I' ? (unsigned) (VALUE) < 0x10		   \
-   : (C) == 'J' ? (VALUE) < 0 && (VALUE) > -16		   \
-   : (C) == 'K' ? (unsigned) ((VALUE) + 0x8000) < 0x10000  \
-   : (C) == 'L' ? ((VALUE) & 0xffff0000) == 0		   \
-   : (C) == 'M' ? ((VALUE) & 0xffff) == 0		   \
-   : (C) == 'N' ? exact_log2 (VALUE) >= 0		   \
-   : (C) == 'O' ? ((VALUE) & 0xffff) == 0xffff		   \
-		  || ((VALUE) & 0xffff0000) == 0xffff0000  \
-   : (C) == 'P' ? exact_log2 (~ (VALUE)) >= 0		   \
-   : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.
-   No floating-point constants on ROMP.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  0
-
-/* Optional extra constraints for this machine.
-
-   For the ROMP, `Q' means that this is a memory operand but not a symbolic
-   memory operand.  Note that an unassigned pseudo register is such a
-   memory operand.  If register allocation has not been done, we reject
-   pseudos, since we assume (hope) that they will get hard registers.
-
-   `R' means that this is a constant pool reference to the current function.
-   This is just r14 and so can be treated as a register.  We bother with this
-   just in move insns as that is the only place it is likely to occur.
-
-   `S' means that this is the address of a constant pool location.  This is
-   equal to r14 plus a constant.  We also only check for this in move insns. */
-
-#define EXTRA_CONSTRAINT(OP, C)				\
-  ((C) == 'Q' ?						\
-   ((GET_CODE (OP) == REG				\
-     && REGNO (OP) >= FIRST_PSEUDO_REGISTER		\
-     && reg_renumber != 0				\
-     && reg_renumber[REGNO (OP)] < 0)			\
-    || (GET_CODE (OP) == MEM				\
-        && ! symbolic_memory_operand (OP, VOIDmode)))	\
-   : (C) == 'R' ? current_function_operand (OP, VOIDmode) \
-   : (C) == 'S' ? constant_pool_address_operand (OP, VOIDmode) \
-   : 0)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.
-
-   For the ROMP, if X is a memory reference that involves a symbol,
-   we must use a BASE_REGS register instead of GENERAL_REGS
-   to do the reload. The argument of MEM be either REG, PLUS, or SYMBOL_REF
-   to be valid, so we assume that this is the case.
-
-   Also, if X is an integer class, ensure that floating-point registers
-   aren't used.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)					\
-  ((CLASS) == FP_REGS && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT	\
-   ? GENERAL_REGS :							\
-   (CLASS) != GENERAL_REGS ? (CLASS) :					\
-   GET_CODE (X) != MEM ? GENERAL_REGS :					\
-   GET_CODE (XEXP (X, 0)) == SYMBOL_REF ? BASE_REGS :			\
-   GET_CODE (XEXP (X, 0)) == LABEL_REF ? BASE_REGS :			\
-   GET_CODE (XEXP (X, 0)) == CONST ? BASE_REGS :			\
-   GET_CODE (XEXP (X, 0)) == REG ? GENERAL_REGS :			\
-   GET_CODE (XEXP (X, 0)) != PLUS ? GENERAL_REGS :			\
-   GET_CODE (XEXP (XEXP (X, 0), 1)) == SYMBOL_REF ? BASE_REGS :		\
-   GET_CODE (XEXP (XEXP (X, 0), 1)) == LABEL_REF ? BASE_REGS :		\
-   GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST ? BASE_REGS : GENERAL_REGS)
-
-/* Return the register class of a scratch register needed to store into
-   OUT from a register of class CLASS in MODE.  
-
-   On the ROMP, we cannot store into a symbolic memory address from an
-   integer register; we need a BASE_REGS register as a scratch to do it.  */
-
-#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
-  (GET_MODE_CLASS (MODE) == MODE_INT && symbolic_memory_operand (OUT, MODE) \
-   ? BASE_REGS : NO_REGS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.
-
-   On ROMP, this is the size of MODE in words,
-   except in the FP regs, where a single reg is always enough.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- ((CLASS) == FP_REGS ? 1			\
-  : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.
-   On the ROMP, if we set the frame pointer to 15 words below the highest
-   address of the highest local variable, the first 16 words will be
-   addressable via D-short insns. */
-#define STARTING_FRAME_OFFSET 64
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On ROMP, don't define this because there are no push insns.  */
-/*  #define PUSH_ROUNDING(BYTES) */
-
-/* Offset of first parameter from the argument pointer register value.
-   On the ROMP, we define the argument pointer to the start of the argument
-   area.  */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Define this if stack space is still allocated for a parameter passed
-   in a register.  The value is the number of bytes.  */
-#define REG_PARM_STACK_SPACE(FNDECL) 16
-
-/* This is the difference between the logical top of stack and the actual sp.
-
-   For the ROMP, sp points past the words allocated for the first four outgoing
-   arguments (they are part of the callee's frame).  */
-#define STACK_POINTER_OFFSET -16
-
-/* Define this if the maximum size of all the outgoing args is to be
-   accumulated and pushed during the prologue.  The amount can be
-   found in the variable current_function_outgoing_args_size.  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.
-
-   On ROMP the value is found in r2, unless the machine specific option
-   fp-arg-in-fpregs is selected, in which case FP return values are in fr1 */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)	\
-  gen_rtx (REG, TYPE_MODE (VALTYPE),	\
-	   (TARGET_FP_REGS &&		\
-	    GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT) ? 18 : 2)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, 2)
-
-/* The definition of this macro implies that there are cases where
-   a scalar value cannot be returned in registers.
-
-   For the ROMP, if compatibility with HC is required, anything of
-   type DImode is returned in memory.  */
-
-#define RETURN_IN_MEMORY(type) \
-  (TYPE_MODE (type) == BLKmode \
-   || (TARGET_HC_STRUCT_RETURN && TYPE_MODE (type) == DImode))
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.
-
-   On ROMP, r2 is the only register thus used unless fp values are to be
-   returned in fp regs, in which case fr1 is also used.  */
-
-#define FUNCTION_VALUE_REGNO_P(N)  ((N) == 2 || ((N) == 18 && TARGET_FP_REGS))
-
-/* 1 if N is a possible register number for function argument passing.
-   On ROMP, these are r2-r5 (and fr1-fr4 if fp regs are used).  */
-
-#define FUNCTION_ARG_REGNO_P(N)	\
-  (((N) <= 5 && (N) >= 2) || (TARGET_FP_REGS && (N) > 17 && (N) < 21))
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the ROMP, this is a structure.  The first word is the number of
-   words of (integer only if -mfp-arg-in-fpregs is specified) arguments
-   scanned so far (including the invisible argument, if any, which holds
-   the structure-value-address).  The second word hold the corresponding
-   value for floating-point arguments, except that both single and double
-   count as one register.  */
-
-struct rt_cargs {int gregs, fregs; };
-#define CUMULATIVE_ARGS struct rt_cargs 
-
-#define USE_FP_REG(MODE,CUM)					\
-  (TARGET_FP_REGS && GET_MODE_CLASS (MODE) == MODE_FLOAT	\
-   && (CUM).fregs < 3)
-
-/* Define intermediate macro to compute the size (in registers) of an argument
-   for the ROMP.  */
-
-#define ROMP_ARG_SIZE(MODE, TYPE, NAMED)				\
-(! (NAMED) ? 0								\
- : (MODE) != BLKmode							\
- ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD 	\
- : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On ROMP, the offset normally starts at 0, but starts at 4 bytes
-   when the function gets a structure-value-address as an
-   invisible first argument.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
-  (CUM).gregs = 0,				\
-  (CUM).fregs = 0
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
-{ if (NAMED)						\
-    {							\
-      if (USE_FP_REG(MODE, CUM))			\
-	(CUM).fregs++;					\
-      else						\
-	(CUM).gregs += ROMP_ARG_SIZE (MODE, TYPE, NAMED); \
-    }							\
-}
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-
-   On ROMP the first four words of args are normally in registers
-   and the rest are pushed.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)				\
-  (! (NAMED) ? 0							\
-   : ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST) ? 0	\
-   : USE_FP_REG(MODE,CUM) ? gen_rtx(REG, (MODE),(CUM.fregs) + 17)	\
-   : (CUM).gregs < 4 ? gen_rtx(REG, (MODE), 2 + (CUM).gregs) : 0)
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)		\
-  (! (NAMED) ? 0							\
-   : USE_FP_REG(MODE,CUM) ? 0						\
-   : (((CUM).gregs < 4							\
-       && 4 < ((CUM).gregs + ROMP_ARG_SIZE (MODE, TYPE, NAMED)))	\
-      ? 4 - (CUM).gregs : 0))
-
-/* Perform any needed actions needed for a function that is receiving a
-   variable number of arguments. 
-
-   CUM is as above.
-
-   MODE and TYPE are the mode and type of the current parameter.
-
-   PRETEND_SIZE is a variable that should be set to the amount of stack
-   that must be pushed by the prolog to pretend that our caller pushed
-   it.
-
-   Normally, this macro will push all remaining incoming registers on the
-   stack and set PRETEND_SIZE to the length of the registers pushed.  */
-
-#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL)	\
-{ if (TARGET_FP_REGS)							\
-    error ("can't have varargs with -mfp-arg-in-fp-regs");		\
-  else if ((CUM).gregs < 4)						\
-    {									\
-      int first_reg_offset = (CUM).gregs;				\
-									\
-      if (MUST_PASS_IN_STACK (MODE, TYPE))				\
-	first_reg_offset += ROMP_ARG_SIZE (TYPE_MODE (TYPE), TYPE, 1);	\
-									\
-      if (first_reg_offset > 4)						\
-	first_reg_offset = 4;						\
-									\
-      if (! NO_RTL && first_reg_offset != 4)				\
-	move_block_from_reg						\
-	  (2 + first_reg_offset,					\
-	   gen_rtx (MEM, BLKmode,					\
-		    plus_constant (virtual_incoming_args_rtx,		\
-				   first_reg_offset * 4)), 		\
-	   4 - first_reg_offset, (4 - first_reg_offset) * UNITS_PER_WORD); \
-      PRETEND_SIZE = (4 - first_reg_offset) * UNITS_PER_WORD;		\
-    }									\
-}
-
-/* This macro produces the initial definition of a function name.
-   On the ROMP, we need to place an extra '.' in the function name.  */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL)	\
-{ if (TREE_PUBLIC(DECL))				\
-    fprintf (FILE, "\t.globl _.%s\n", NAME);		\
-  fprintf (FILE, "_.%s:\n", NAME);			\
-}
-
-/* This macro is used to output the start of the data area.
-
-   On the ROMP, the _name is a pointer to the data area.  At that
-   location is the address of _.name, which is really the name of
-   the function.  We need to set all this up here.
-
-   The global declaration of the data area, if needed, is done in 
-   `assemble_function', where it thinks it is globalizing the function
-   itself.  */
-
-#define ASM_OUTPUT_POOL_PROLOGUE(FILE, NAME, DECL, SIZE)	\
-{ extern int data_offset;					\
-  data_section ();						\
-  fprintf (FILE, "\t.align 2\n");				\
-  ASM_OUTPUT_LABEL (FILE, NAME);				\
-  fprintf (FILE, "\t.long _.%s, 0, ", NAME);			\
-  if (current_function_calls_alloca)				\
-    fprintf (FILE, "0x%x\n",					\
-	     0xf6900000 + current_function_outgoing_args_size); \
-  else								\
-    fprintf (FILE, "0\n");					\
-  data_offset = ((SIZE) + 12 + 3) / 4;				\
-}
-
-/* Select section for constant in constant pool.
-
-   On ROMP, all constants are in the data area.  */
-
-#define SELECT_RTX_SECTION(MODE, X)	data_section ()
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) output_prolog (FILE, SIZE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)	\
-  fprintf(FILE, "\tcas r0,r15,r0\n\tbali r15,mcount\n");
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-/* #define EXIT_IGNORE_STACK	1	*/
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) output_epilog (FILE, SIZE)
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.
-
-   The trampoline should set the static chain pointer to value placed
-   into the trampoline and should branch to the specified routine.
-
-   On the ROMP, we have a problem.  There are no free registers to use
-   to construct the static chain and function addresses.  Hence we use
-   the following kludge:  r15 (the return address) is first saved in mq.
-   Then we use r15 to form the function address.  We then branch to the
-   function and restore r15 in the delay slot.  This makes it appear that
-   the function was called directly from the caller.
-
-   (Note that the function address built is actually that of the data block.
-   This is passed in r0 and the actual routine address is loaded into r15.)
-
-   In addition, note that the address of the "called function", in this case
-   the trampoline, is actually the address of the data area.  So we need to
-   make a fake data area that will contain the address of the trampoline.
-   Note that this must be defined as two half-words, since the trampoline
-   template (as opposed to the trampoline on the stack) is only half-word
-   aligned.  */
-
-#define TRAMPOLINE_TEMPLATE(FILE)	\
-{					\
-  fprintf (FILE, "\t.short 0,0\n");	\
-  fprintf (FILE, "\tcau r0,0(r0)\n");	\
-  fprintf (FILE, "\toil r0,r0,0\n");	\
-  fprintf (FILE, "\tmts r10,r15\n");	\
-  fprintf (FILE, "\tst r0,-36(r1)\n");	\
-  fprintf (FILE, "\tcau r15,0(r0)\n");	\
-  fprintf (FILE, "\toil r15,r15,0\n");	\
-  fprintf (FILE, "\tcas r0,r15,r0\n");	\
-  fprintf (FILE, "\tls r15,0(r15)\n");	\
-  fprintf (FILE, "\tbrx r15\n");	\
-  fprintf (FILE, "\tmfs r10,r15\n");	\
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE    36
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.
-
-   On the RT, the static chain and function addresses are written in
-   two 16-bit sections.
-
-   We also need to write the address of the first instruction in
-   the trampoline into the first word of the trampoline to simulate a
-   data area.  */
-
-#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT)		\
-{								\
-  rtx _addr, _temp;						\
-  rtx _val;							\
-								\
-  _temp = expand_binop (SImode, add_optab, ADDR,		\
-			GEN_INT (4),				\
-			0, 1, OPTAB_LIB_WIDEN);			\
-  emit_move_insn (gen_rtx (MEM, SImode,				\
-			   memory_address (SImode, ADDR)), _temp); \
-								\
-  _val = force_reg (SImode, CXT);				\
-  _addr = memory_address (HImode, plus_constant (ADDR, 10));	\
-  emit_move_insn (gen_rtx (MEM, HImode, _addr),			\
-		  gen_lowpart (HImode, _val));			\
-  _temp = expand_shift (RSHIFT_EXPR, SImode, _val,		\
-			build_int_2 (16, 0), 0, 1);		\
-  _addr = memory_address (HImode, plus_constant (ADDR, 6));	\
-  emit_move_insn (gen_rtx (MEM, HImode, _addr),			\
-		  gen_lowpart (HImode, _temp));			\
-								\
-  _val = force_reg (SImode, FNADDR);				\
-  _addr = memory_address (HImode, plus_constant (ADDR, 24));	\
-  emit_move_insn (gen_rtx (MEM, HImode, _addr),			\
-		  gen_lowpart (HImode, _val));			\
-  _temp = expand_shift (RSHIFT_EXPR, SImode, _val,		\
-			build_int_2 (16, 0), 0, 1);		\
-  _addr = memory_address (HImode, plus_constant (ADDR, 20));	\
-  emit_move_insn (gen_rtx (MEM, HImode, _addr),			\
-		  gen_lowpart (HImode, _temp));			\
-								\
-}
-
-/* Definitions for register eliminations.
-
-   We have two registers that can be eliminated on the ROMP.  First, the
-   frame pointer register can often be eliminated in favor of the stack
-   pointer register.  Secondly, the argument pointer register can always be
-   eliminated; it is replaced with either the stack or frame pointer.
-
-   In addition, we use the elimination mechanism to see if r14 is needed.
-   Initially we assume that it isn't.  If it is, we spill it.  This is done
-   by making it an eliminable register.  It doesn't matter what we replace
-   it with, since it will never occur in the rtl at this point.  */
-
-/* This is an array of structures.  Each structure initializes one pair
-   of eliminable registers.  The "from" register number is given first,
-   followed by "to".  Eliminations of the same "from" register are listed
-   in order of preference.  */
-#define ELIMINABLE_REGS				\
-{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
- { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},	\
- { 14, 0}}
-
-/* Given FROM and TO register numbers, say whether this elimination is allowed.
-   Frame pointer elimination is automatically handled.
-
-   For the ROMP, if frame pointer elimination is being done, we would like to
-   convert ap into fp, not sp.
-
-   We need r14 if various conditions (tested in romp_using_r14) are true.
-
-   All other eliminations are valid.  */
-#define CAN_ELIMINATE(FROM, TO)					\
- ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM	\
-  ? ! frame_pointer_needed					\
-  : (FROM) == 14 ? ! romp_using_r14 ()				\
-  : 1)
-
-/* Define the offset between two registers, one to be eliminated, and the other
-   its replacement, at the start of a routine.  */
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
-{ if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	\
-    {									\
-      if (romp_pushes_stack ())						\
-	(OFFSET) = ((get_frame_size () - 64)				\
-		    + current_function_outgoing_args_size);		\
-      else								\
-	(OFFSET) = - (romp_sa_size () + 64);				\
-    }									\
-  else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
-    (OFFSET) = romp_sa_size () - 16 + 64;				\
-  else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
-    {									\
-      if (romp_pushes_stack ())						\
-	(OFFSET) = (get_frame_size () + (romp_sa_size () - 16)		\
-		    + current_function_outgoing_args_size);		\
-      else								\
-	(OFFSET) = -16;							\
-    }									\
-  else if ((FROM) == 14)						\
-    (OFFSET) = 0;							\
-  else									\
-    abort ();								\
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) 0
-#define REGNO_OK_FOR_BASE_P(REGNO)				\
-((REGNO) < FIRST_PSEUDO_REGISTER				\
- ? (REGNO) < 16 && (REGNO) != 0 && (REGNO) != 16		\
- : (reg_renumber[REGNO] < 16 && reg_renumber[REGNO] >= 0	\
-    && reg_renumber[REGNO] != 16))
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 1
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
-
-   On the ROMP, there is a bit of a hack here.  Basically, we wish to
-   only issue instructions that are not `as' macros.  However, in the
-   case of `get', `load', and `store', if the operand is a relocatable
-   symbol (possibly +/- an integer), there is no way to express the
-   resulting split-relocation except with the macro.  Therefore, allow
-   either a constant valid in a normal (sign-extended) D-format insn or
-   a relocatable expression.
-
-   Also, for DFmode and DImode, we must ensure that both words are
-   addressable.
-
-   We define two macros: The first is given an offset (0 or 4) and indicates
-   that the operand is a CONST_INT that is valid for that offset.  The second
-   indicates a valid non-CONST_INT constant.  */
-
-#define LEGITIMATE_ADDRESS_INTEGER_P(X,OFFSET)				\
-  (GET_CODE (X) == CONST_INT						\
-   && (unsigned) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
-
-#define LEGITIMATE_ADDRESS_CONSTANT_P(X)				\
- (GET_CODE (X) == SYMBOL_REF						\
-  || GET_CODE (X) == LABEL_REF						\
-  || (GET_CODE (X) == CONST						\
-      && (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF		\
-          || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF)		\
-      && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))
-
-/* Include all constant integers and constant double, but exclude 
-   SYMBOL_REFs that are to be obtained from the data area (see below).  */
-#define LEGITIMATE_CONSTANT_P(X)		\
-  ((LEGITIMATE_ADDRESS_CONSTANT_P (X)		\
-    || GET_CODE (X) == CONST_INT		\
-    || GET_CODE (X) == CONST_DOUBLE)		\
-   && ! (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)))
-
-/* For no good reason, we do the same as the other RT compilers and load
-   the addresses of data areas for a function from our data area.  That means
-   that we need to mark such SYMBOL_REFs.  We do so here.  */
-#define ENCODE_SECTION_INFO(DECL)			\
-  if (TREE_CODE (TREE_TYPE (DECL)) == FUNCTION_TYPE)	\
-    SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) 0
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X)		\
-  (REGNO (X) != 0 && (REGNO (X) < 17 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   On the ROMP, a legitimate address is either a legitimate constant,
-   a register plus a legitimate constant, or a register.  See the
-   discussion at the LEGITIMATE_ADDRESS_CONSTANT_P macro.  */
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-{ if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
-    goto ADDR;								\
-  if (GET_CODE (X) != CONST_INT && LEGITIMATE_ADDRESS_CONSTANT_P (X))	\
-    goto ADDR;								\
-  if (GET_CODE (X) == PLUS						\
-      && GET_CODE (XEXP (X, 0)) == REG					\
-      && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
-      && LEGITIMATE_ADDRESS_CONSTANT_P (XEXP (X, 1)))			\
-	goto ADDR;							\
-  if (GET_CODE (X) == PLUS						\
-      && GET_CODE (XEXP (X, 0)) == REG					\
-      && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
-      && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0)			\
-      && (((MODE) != DFmode && (MODE) != DImode)			\
-	  || (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4))))		\
-	goto ADDR;							\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   On ROMP, check for the sum of a register with a constant
-   integer that is out of range.  If so, generate code to add the
-   constant with the low-order 16 bits masked to the register and force
-   this result into another register (this can be done with `cau').
-   Then generate an address of REG+(CONST&0xffff), allowing for the 
-   possibility of bit 16 being a one.
-
-   If the register is not OK for a base register, abort.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)			\
-{ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG	\
-    && GET_CODE (XEXP (X, 1)) == CONST_INT			\
-    && (unsigned) (INTVAL (XEXP (X, 1)) + 0x8000) >= 0x10000)	\
-    { int high_int, low_int;					\
-      if (! REG_OK_FOR_BASE_P (XEXP (X, 0)))			\
-	abort ();						\
-      high_int = INTVAL (XEXP (X, 1)) >> 16;			\
-      low_int = INTVAL (XEXP (X, 1)) & 0xffff;			\
-      if (low_int & 0x8000)					\
-	high_int += 1, low_int |= 0xffff0000;			\
-      (X) = gen_rtx (PLUS, SImode,				\
-		     force_operand				\
-		     	(gen_rtx (PLUS, SImode, XEXP (X, 0), \
-				  GEN_INT (high_int << 16)), 0),\
-		     GEN_INT (low_int));			\
-    }								\
-}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-
-   On the ROMP this is true only if the address is valid with a zero offset
-   but not with an offset of four (this means it cannot be used as an
-   address for DImode or DFmode).  Since we know it is valid, we just check
-   for an address that is not valid with an offset of four.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)		\
-{ if (GET_CODE (ADDR) == PLUS					\
-      && ! LEGITIMATE_ADDRESS_CONSTANT_P (XEXP (ADDR, 1))	\
-      && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 4))	\
-    goto LABEL;							\
-}
-
-/* Define this if some processing needs to be done immediately before
-   emitting code for an insn.
-
-   This is used on the ROMP, to compensate for a bug in the floating-point
-   code.  When a floating-point operation is done with the first and third
-   operands both the same floating-point register, it will generate bad code
-   for the MC68881.  So we must detect this.  If it occurs, we patch the 
-   first operand to be fr0 and insert a move insn to move it to the desired
-   destination.  */
-#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS)			\
-  { rtx op0, op1, op2, operation, tem;					\
-    if (NOPERANDS >= 3	&& get_attr_type (INSN) == TYPE_FP)		\
-      {									\
-	op0 = OPERANDS[0];						\
-	operation = OPERANDS[1];					\
-	if (float_conversion (operation, VOIDmode))			\
-	  operation = XEXP (operation, 0);				\
-        if (float_binary (operation, VOIDmode))				\
-	  {								\
-	    op1 = XEXP (operation, 0), op2 = XEXP (operation, 1);	\
-	    if (float_conversion (op1, VOIDmode))			\
-	      op1 = XEXP (op1, 0);					\
-	    if (float_conversion (op2, VOIDmode))			\
-	      op2 = XEXP (op2, 0);					\
-	    if (rtx_equal_p (op0, op2)					\
-		&& (GET_CODE (operation) == PLUS			\
-		    || GET_CODE (operation) == MULT))			\
-	      tem = op1, op1 = op2, op2 = tem;				\
-	    if (GET_CODE (op0) == REG && FP_REGNO_P (REGNO (op0))	\
-		&& GET_CODE (op2) == REG && FP_REGNO_P (REGNO (op2))	\
-		&& REGNO (op0) == REGNO (op2))				\
-	      {								\
-		tem = gen_rtx (REG, GET_MODE (op0), 17);		\
-		emit_insn_after (gen_move_insn (op0, tem), INSN);	\
-		SET_DEST (XVECEXP (PATTERN (INSN), 0, 0)) = tem; 	\
-		OPERANDS[0] = tem;					\
-	      }								\
-	  }								\
-      }									\
-  }
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.
-
-   We actually lie a bit here as overflow conditions are different.  But
-   they aren't being checked anyway.  */
-
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 4
-
-/* Nonzero if access to memory by bytes is no faster than for words.
-   Also non-zero if doing byte operations (specifically shifts) in registers
-   is undesirable.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.  */
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* This is BSD, so it wants DBX format.  */
-#define DBX_DEBUGGING_INFO
-
-/* Define the letter code used in a stabs entry for parameters passed
-   with the register attribute.
-
-   GCC's default value, 'P', is used by dbx to refers to an external
-   procedure. The section 5 manual page for dbx implies that 'R' would be the
-   right letter, but dbx 1.5 has a bug in it that precludes its use.
-   Probably that is why neither hc or pcc use this. pcc puts in two
-   stabs entries: one for the parameter location and one for the register
-   location. The letter `r' (register)
-   would be okay, but it loses parameter attribute of the stabs entry.  */
-#define DBX_REGPARM_STABS_LETTER 'R'
-
-/* A C expression for the integer offset value of an automatic variable
-   (N_LSYM) having address X (an RTX). This gets used in .stabs entries
-   for the local variables. Compare with the default definition.  */
-extern int romp_debugger_auto_correction();
-#define DEBUGGER_AUTO_OFFSET(X)                        \
-  (GET_CODE (X) == PLUS                                \
-   ? romp_debugger_auto_correction (INTVAL (XEXP (X, 1)) ) \
-   : 0 )
-
-/* A C expression for the integer offset value of an argument (N_PSYM)
-   having address X (an RTX).  The nominal offset is OFFSET.  */
-extern int romp_debugger_arg_correction();
-#define DEBUGGER_ARG_OFFSET(OFFSET, X)             \
-  romp_debugger_arg_correction (OFFSET);
-
-/* We don't have GAS for the RT yet, so don't write out special
-   .stabs in cc1plus.  */
-   
-#define FASCIST_ASSEMBLER
-
-/* Do not break .stabs pseudos into continuations.  */
-#define DBX_CONTIN_LENGTH 0
-
-/* Don't try to use the `x' type-cross-reference character in DBX data.
-   Also has the consequence of putting each struct, union or enum
-   into a separate .stabs, containing only cross-refs to the others.  */
-#define DBX_NO_XREFS
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* Mode of a function address in a call instruction (for indexing purposes).
-
-   Doesn't matter on ROMP.  */
-#define FUNCTION_MODE SImode
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.  */
-#define NO_FUNCTION_CSE
-
-/* Define this if shift instructions ignore all but the low-order
-   few bits.
-
-   This is not true on the RT since it uses the low-order 6, not 5, bits.
-   At some point, this should be extended to see how to express that.  */
-
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Compute the cost of computing a constant rtl expression RTX whose
-   rtx-code is CODE, contained within an expression of code OUTER_CODE.
-   The body of this macro is a portion of a switch statement.  If the
-   code is computed here, return it with a return statement.  Otherwise,
-   break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    if ((OUTER_CODE) == IOR && exact_log2 (INTVAL (RTX)) >= 0	\
-	|| (OUTER_CODE) == AND && exact_log2 (~INTVAL (RTX)) >= 0 \
-	|| (((OUTER_CODE) == PLUS || (OUTER_CODE) == MINUS)	\
-	    && (unsigned int) (INTVAL (RTX) + 15) < 31)		\
-	|| ((OUTER_CODE) == SET && (unsigned int) INTVAL (RTX) < 16))\
-      return 0;							\
-    return ((unsigned int) (INTVAL(RTX) + 0x8000) < 0x10000		\
-	    || (INTVAL (RTX) & 0xffff0000) == 0) ? 0 : COSTS_N_INSNS (2);\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    if (current_function_operand (RTX, Pmode)) return 0;	\
-    return COSTS_N_INSNS (2);					\
-  case CONST_DOUBLE:						\
-    if ((RTX) == CONST0_RTX (GET_MODE (RTX))) return 2;		\
-    return ((GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT)	\
-	    ? COSTS_N_INSNS (5) : COSTS_N_INSNS (4));
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE. 
-
-   References to our own data area are really references to r14, so they
-   are very cheap.  Multiples and divides are very expensive.  */
-
-#define RTX_COSTS(X,CODE,OUTER_CODE)			\
-  case MEM:						\
-    return current_function_operand (X, Pmode) ? 0 : COSTS_N_INSNS (2);	\
-  case MULT:						\
-    return (TARGET_IN_LINE_MUL && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT)\
-	   ? COSTS_N_INSNS (19) : COSTS_N_INSNS (25);	\
-  case DIV:						\
-  case UDIV:						\
-  case MOD:						\
-  case UMOD:						\
-    return COSTS_N_INSNS (45);
-
-/* Compute the cost of an address.  This is meant to approximate the size
-   and/or execution delay of an insn using that address.  If the cost is
-   approximated by the RTL complexity, including CONST_COSTS above, as
-   is usually the case for CISC machines, this macro should not be defined.
-   For aggressively RISCy machines, only one insn format is allowed, so
-   this macro should be a constant.  The value of this macro only matters
-   for valid addresses.
-
-   For the ROMP, everything is cost 0 except for addresses involving
-   symbolic constants, which are cost 1.  */
-
-#define ADDRESS_COST(RTX)				\
-  ((GET_CODE (RTX) == SYMBOL_REF			\
-    && ! CONSTANT_POOL_ADDRESS_P (RTX))			\
-   || GET_CODE (RTX) == LABEL_REF			\
-   || (GET_CODE (RTX) == CONST				\
-       && ! constant_pool_address_operand (RTX, Pmode))	\
-   || (GET_CODE (RTX) == PLUS				\
-       && ((GET_CODE (XEXP (RTX, 1)) == SYMBOL_REF	\
-	    && ! CONSTANT_POOL_ADDRESS_P (XEXP (RTX, 0))) \
-	   || GET_CODE (XEXP (RTX, 1)) == LABEL_REF	\
-	   || GET_CODE (XEXP (RTX, 1)) == CONST)))
-
-/* Adjust the length of an INSN.  LENGTH is the currently-computed length and
-   should be adjusted to reflect any required changes.  This macro is used when
-   there is some systematic length adjustment required that would be difficult
-   to express in the length attribute.
-
-   On the ROMP, there are two adjustments:  First, a 2-byte insn in the delay
-   slot of a CALL (including floating-point operations) actually takes four
-   bytes.  Second, we have to make the worst-case alignment assumption for
-   address vectors.  */
-
-#define ADJUST_INSN_LENGTH(X,LENGTH)					\
-  if (GET_CODE (X) == INSN && GET_CODE (PATTERN (X)) == SEQUENCE	\
-      && GET_CODE (XVECEXP (PATTERN (X), 0, 0)) != JUMP_INSN		\
-      && get_attr_length (XVECEXP (PATTERN (X), 0, 1)) == 2)		\
-    (LENGTH) += 2;							\
-  else if (GET_CODE (X) == JUMP_INSN && GET_CODE (PATTERN (X)) == ADDR_VEC) \
-    (LENGTH) += 2;
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  */
-
-/* Set if condition code (really not-Z) is stored in `test bit'.  */
-#define CC_IN_TB	 01000
-
-/* Set if condition code is set by an unsigned compare. */
-#define	CC_UNSIGNED        02000
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define NOTICE_UPDATE_CC(BODY,INSN) \
-  update_cc (BODY, INSN)
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(FILE)				\
-{ extern char *version_string;				\
-  char *p;						\
-							\
-  fprintf (FILE, "\t.globl .oVncs\n\t.set .oVncs,0\n") ; \
-  fprintf (FILE, "\t.globl .oVgcc");			\
-  for (p = version_string; *p != ' ' && *p != 0; p++)	\
-    fprintf (FILE, "%c", *p);				\
-  fprintf (FILE, "\n\t.set .oVgcc");			\
-  for (p = version_string; *p != ' ' && *p != 0; p++)	\
-    fprintf (FILE, "%c", *p);				\
-  fprintf (FILE, ",0\n");				\
-}
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-
-/* Output before instructions and read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",	\
- "r10", "r11", "r12", "r13", "r14", "r15", "ap",		\
- "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7" }
-
-/* How to renumber registers for dbx and gdb.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to output a label for a jump table.  Arguments are the same as
-   for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
-   passed. */
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN)	\
-{ ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)		\
-  fprintf (FILE, "\t.double 0d%.20e\n", (VALUE))
-
-/* This is how to output an assembler line defining a `float' constant.
-
-   WARNING:  Believe it or not, the ROMP assembler has a bug in its
-   handling of single-precision floating-point values making it impossible
-   to output such values in the expected way.  Therefore, it must be output
-   in hex.  THIS WILL NOT WORK IF CROSS-COMPILING FROM A MACHINE THAT DOES
-   NOT USE IEEE-FORMAT FLOATING-POINT, but there is nothing that can be done
-   about it short of fixing the assembler.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)		\
-  do { union { int i; float f; } u_i_f;		\
-       u_i_f.f = (VALUE);			\
-       fprintf (FILE, "\t.long 0x%x\n", u_i_f.i);\
-     } while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.short "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* This is how to output code to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tsis r1,4\n\tsts %s,0(r1)\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tls r1,0(r1)\n\tais r1,4\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.long L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.
-   Don't define this if it is not supported. */
-
-/* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", (LOG))
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %d\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED)	\
-( fputs (".lcomm ", (FILE)),				\
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand (FILE, X, CODE)
-
-/* Define which CODE values are valid.  */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)	\
-  ((CODE) == '.' || (CODE) == '#')
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)			\
-{ register rtx addr = ADDR;					\
-  register rtx base = 0, offset = addr;				\
-  if (GET_CODE (addr) == REG)					\
-    base = addr, offset = const0_rtx;				\
-  else if (GET_CODE (addr) == PLUS				\
-	   && GET_CODE (XEXP (addr, 0)) == REG)			\
-    base = XEXP (addr, 0), offset = XEXP (addr, 1);		\
-  else if (GET_CODE (addr) == SYMBOL_REF			\
-	   && CONSTANT_POOL_ADDRESS_P (addr))			\
-    {								\
-      offset = GEN_INT (get_pool_offset (addr) + 12);  \
-      base = gen_rtx (REG, SImode, 14);				\
-    }								\
-  else if (GET_CODE (addr) == CONST				\
-	   && GET_CODE (XEXP (addr, 0)) == PLUS			\
-	   && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT	\
-	   && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF	\
-	   && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addr, 0), 0))) \
-    {								\
-      offset = plus_constant (XEXP (XEXP (addr, 0), 1),		\
-			      (get_pool_offset (XEXP (XEXP (addr, 0), 0)) \
-			       + 12));				\
-      base = gen_rtx (REG, SImode, 14);				\
-    }								\
-  output_addr_const (FILE, offset);				\
-  if (base)							\
-    fprintf (FILE, "(%s)", reg_names [REGNO (base)]);		\
-}
-
-/* Define the codes that are matched by predicates in aux-output.c.  */
-
-#define PREDICATE_CODES \
-  {"zero_memory_operand", {SUBREG, MEM}},			\
-  {"short_memory_operand", {SUBREG, MEM}},			\
-  {"symbolic_memory_operand", {SUBREG, MEM}},			\
-  {"current_function_operand", {MEM}},				\
-  {"constant_pool_address_operand", {SUBREG, CONST}},		\
-  {"romp_symbolic_operand", {LABEL_REF, SYMBOL_REF, CONST}},	\
-  {"constant_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST, CONST_INT}}, \
-  {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}},		\
-  {"reg_or_any_cint_operand", {SUBREG, REG, CONST_INT}},	\
-  {"short_cint_operand", {CONST_INT}},				\
-  {"reg_or_D_operand", {SUBREG, REG, CONST_INT}},		\
-  {"reg_or_add_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF,	\
-			  PLUS, CONST, CONST_INT}}, 		\
-  {"reg_or_and_operand", {SUBREG, REG, CONST_INT}},		\
-  {"reg_or_mem_operand", {SUBREG, REG, MEM}},			\
-  {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}},		\
-  {"romp_operand", {SUBREG, MEM, REG, CONST_INT, CONST, LABEL_REF, \
-		    SYMBOL_REF, CONST_DOUBLE}},			\
-  {"reg_0_operand", {REG}},					\
-  {"reg_15_operand", {REG}},					\
-  {"float_binary", {PLUS, MINUS, MULT, DIV}},			\
-  {"float_unary", {NEG, ABS}},					\
-  {"float_conversion", {FLOAT_TRUNCATE, FLOAT_EXTEND, FLOAT, FIX}},
-
-/* Define functions defined in aux-output.c and used in templates.  */
-
-extern char *output_in_line_mul ();
-extern char *output_fpop ();
diff --git a/gcc/config/romp/romp.md b/gcc/config/romp/romp.md
deleted file mode 100755
index 3abd56b..0000000
--- a/gcc/config/romp/romp.md
+++ /dev/null
@@ -1,2776 +0,0 @@
-;;- Machine description for ROMP chip for GNU C compiler
-;;   Copyright (C) 1988, 1991, 1993, 1994, 1995 Free Software Foundation, Inc.
-;;   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; Define the attributes for the ROMP.
-
-;; Insn type.  Used to default other attribute values.
-
-(define_attr "type"
-  "branch,ibranch,return,fp,load,loadz,store,call,address,arith,compare,multi,misc"
-  (const_string "arith"))
-
-;; Length in bytes.
-
-(define_attr "length" ""
-  (cond [(eq_attr "type" "branch")
-	 (if_then_else (and (ge (minus (pc) (match_dup 0))
-				(const_int -256))
-			    (le (minus (pc) (match_dup 0))
-				(const_int 254)))
-		       (const_int 2)
-		       (const_int 4))
-	 (eq_attr "type" "return,ibranch") (const_int 2)
-	 (eq_attr "type" "fp")		(const_int 10)
-	 (eq_attr "type" "call")	(const_int 4)
-	 (eq_attr "type" "load")
-	   (cond [(match_operand 1 "short_memory_operand" "") (const_int 2)
-		  (match_operand 1 "symbolic_memory_operand" "") (const_int 8)]
-		 (const_int 4))
-         (eq_attr "type" "loadz")
-	   (cond [(match_operand 1 "zero_memory_operand" "") (const_int 2)
-		  (match_operand 1 "symbolic_memory_operand" "") (const_int 8)]
-		 (const_string "4"))
-	 (eq_attr "type" "store")
-	   (cond [(match_operand 0 "short_memory_operand" "") (const_int 2)
-		  (match_operand 0 "symbolic_memory_operand" "") (const_int 8)]
-		 (const_int 4))]
-	(const_int 4)))
-
-;; Whether insn can be placed in a delay slot.
-
-(define_attr "in_delay_slot" "yes,no" 
-  (cond [(eq_attr "length" "8,10,38")			(const_string "no")
-	 (eq_attr "type" "branch,ibranch,return,call,multi")
-	 (const_string "no")]
-	(const_string "yes")))
-
-;; Whether insn needs a delay slot.  We have to say that two-byte
-;; branches do not need a delay slot.  Otherwise, branch shortening will
-;; try to do something with delay slot insns (we want it to on the PA).
-;; This is a kludge, which should be cleaned up at some point.
-
-(define_attr "needs_delay_slot" "yes,no"
-  (if_then_else (ior (and (eq_attr "type" "branch")
-			  (eq_attr "length" "4"))
-		     (eq_attr "type" "ibranch,return,call"))
-		(const_string "yes") (const_string "no")))
-
-;; What insn does to the condition code.
-
-(define_attr "cc"
-  "clobber,none,sets,change0,copy1to0,compare,tbit"
-  (cond [(eq_attr "type" "load,loadz")		(const_string "change0")
-	 (eq_attr "type" "store")		(const_string "none")
-	 (eq_attr "type" "fp,call")		(const_string "clobber")
-	 (eq_attr "type" "branch,ibranch,return") (const_string "none")
-	 (eq_attr "type" "address")		(const_string "change0")
-	 (eq_attr "type" "compare")		(const_string "compare")
-	 (eq_attr "type" "arith")		(const_string "sets")]
-	(const_string "clobber")))
-
-;; Define attributes for `asm' insns.
-
-(define_asm_attributes [(set_attr "type" "misc")
-			(set_attr "length" "8")
-			(set_attr "in_delay_slot" "no")
-			(set_attr "cc" "clobber")])
-
-;; Define the delay slot requirements for branches and calls.  We don't have
-;; any annulled insns.
-;;
-(define_delay (eq_attr "needs_delay_slot" "yes")
-  [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
-
-;; We cannot give a floating-point comparison a delay slot, even though it
-;; could make use of it.  This is because it would confuse next_cc0_user
-;; to do so.  Other fp insns can't get a delay slow because they set their
-;; result and use their input after the delay slot insn is executed.  This
-;; isn't what reorg.c expects.  
-
-;; Define load & store delays.  These were obtained by measurements done by
-;; jfc@athena.mit.edu.
-;;
-;; In general, the memory unit can support at most two simultaneous operations.
-;;
-;; Loads take 5 cycles to return the data and can be pipelined up to the
-;; limit of two simultaneous operations.
-(define_function_unit "memory" 1 2 (eq_attr "type" "load,loadz") 5 0)
-
-;; Stores do not return data, but tie up the memory unit for 2 cycles if the
-;; next insn is also a store.
-(define_function_unit "memory" 1 2 (eq_attr "type" "store") 1 2
-  [(eq_attr "type" "store")])
-
-;; Move word instructions.
-;;
-;; If destination is memory but source is not register, force source to
-;; register.
-;;
-;; If source is a constant that is too large to load in a single insn, build
-;; it in two pieces.
-;;
-;; If destination is memory and source is a register, a temporary register
-;; will be needed.  In that case, make a PARALLEL of the SET and a
-;; CLOBBER of a SCRATCH to allocate the required temporary.
-;;
-;; This temporary is ACTUALLY only needed when the destination is a
-;; relocatable expression.  For generating RTL, however, we always
-;; place the CLOBBER.  In insns where it is not needed, the SCRATCH will
-;; not be allocated to a register.
-;;
-;; Also, avoid creating pseudo-registers or SCRATCH rtx's during reload as
-;; they will not be correctly handled.  We never need pseudos for that
-;; case anyway.
-;;
-;; We do not use DEFINE_SPLIT for loading constants because the number
-;; of cases in the resulting unsplit insn would be too high to deal
-;; with practically.
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{ rtx op0 = operands[0];
-  rtx op1 = operands[1];
-
-  if (GET_CODE (op1) == REG && REGNO (op1) == 16)
-    DONE;
-
-  if (GET_CODE (op0) == REG && REGNO (op0) == 16)
-    DONE;
-
-  if (GET_CODE (op0) == MEM && ! reload_in_progress)
-    {
-      emit_insn (gen_storesi (operands[0], force_reg (SImode, operands[1])));
-      DONE;
-    }
-  else if (GET_CODE (op1) == CONST_INT)
-    {
-      int const_val = INTVAL (op1);
-
-      /* Try a number of cases to see how to best load the constant.  */
-      if ((const_val & 0xffff) == 0
-	  || (const_val & 0xffff0000) == 0
-	  || (unsigned) (const_val + 0x8000) < 0x10000)
-	/* Can do this in one insn, so generate it.  */
-	;
-      else if (((- const_val) & 0xffff) == 0
-	       || ((- const_val) & 0xffff0000) == 0
-	       || (unsigned) ((- const_val) + 0x8000) < 0x10000)
-	{
-	  /* Can do this by loading the negative constant and then negating. */
-	  emit_move_insn (operands[0],
-			  GEN_INT (- const_val));
-	  emit_insn (gen_negsi2 (operands[0], operands[0]));
-	  DONE;
-	}
-      else
-	/* Do this the long way.  */
-	{
-	  unsigned int high_part = const_val & 0xffff0000;
-	  unsigned int low_part = const_val & 0xffff;
-	  int i;
-
-	  if (low_part >= 0x10 && exact_log2 (low_part) >= 0)
-	    i = high_part, high_part = low_part, low_part = i;
-
-	  emit_move_insn (operands[0],
-			  GEN_INT (low_part));
-	  emit_insn (gen_iorsi3 (operands[0], operands[0],
-				 GEN_INT (high_part)));
-	  DONE;
-	}
-    }
-}")
-
-;; Move from a symbolic memory location to a register is special.  In this
-;; case, we know in advance that the register cannot be r0, so we can improve
-;; register allocation by treating it separately.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=b")
-	(match_operand:SI 1 "symbolic_memory_operand" "m"))]
-  ""
-  "load %0,%1"
-  [(set_attr "type" "load")])
-
-;; Generic single-word move insn.  We avoid the case where the destination is
-;; a symbolic address, as that needs a temporary register.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,r,r,r,b,Q")
-	(match_operand:SI 1 "romp_operand" "rR,I,K,L,M,S,s,Q,m,r"))]
-  "register_operand (operands[0], SImode)
-   || register_operand (operands[1], SImode)"
-  "@
-   cas %0,%1,r0
-   lis %0,%1
-   cal %0,%1(r0)
-   cal16 %0,%1(r0)
-   cau %0,%H1(r0)
-   ail %0,r14,%C1
-   get %0,$%1
-   l%M1 %0,%1
-   load %0,%1
-   st%M0 %1,%0"
-  [(set_attr "type" "address,address,address,address,address,arith,misc,load,load,store")
-   (set_attr "length" "2,2,4,4,4,4,8,*,*,*")])
-
-(define_insn "storesi"
-  [(set (match_operand:SI 0 "memory_operand" "=Q,m")
-	(match_operand:SI 1 "register_operand" "r,r"))
-   (clobber (match_scratch:SI 2 "=X,&b"))]
-  ""
-  "@
-   st%M0 %1,%0
-   store %1,%0,%2"
-  [(set_attr "type" "store")])
-
-;; This pattern is used by reload when we store into a symbolic address.  It
-;; provides the temporary register required.  This pattern is only used
-;; when SECONDARY_OUTPUT_RELOAD_CLASS returns something other than
-;; NO_REGS, so we need not have any predicates here.
-
-(define_expand "reload_outsi"
-  [(parallel [(set (match_operand:SI 0 "symbolic_memory_operand" "=m")
-		   (match_operand:SI 1 "" "r"))
-	      (clobber (match_operand:SI 2 "" "=&b"))])]
-  ""
-  "")
-
-;; Now do the same for the QI move instructions.
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{ rtx op0 = operands[0];
-
-  if (GET_CODE (op0) == MEM && ! reload_in_progress)
-    {
-      emit_insn (gen_storeqi (operands[0], force_reg (QImode, operands[1])));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "=b")
-	(match_operand:QI 1 "symbolic_memory_operand" "m"))]
-  "" 
-  "loadc %0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,b,Q")
-	(match_operand:QI 1 "romp_operand" "r,I,n,s,Q,m,r"))]
-  "register_operand (operands[0], QImode)
-   || register_operand (operands[1], QImode)"
-  "@
-   cas %0,%1,r0
-   lis %0,%1
-   cal %0,%L1(r0)
-   get %0,$%1
-   lc%M1 %0,%1
-   loadc %0,%1
-   stc%M0 %1,%0"
-  [(set_attr "type" "address,address,address,misc,load,load,store")
-   (set_attr "length" "2,2,4,8,*,*,*")])
-
-(define_insn "storeqi"
-  [(set (match_operand:QI 0 "memory_operand" "=Q,m")
-	(match_operand:QI 1 "register_operand" "r,r"))
-   (clobber (match_scratch:SI 2 "=X,&b"))]
-  ""
-  "@
-   stc%M0 %1,%0
-   storec %1,%0,%2"
-  [(set_attr "type" "store")])
-
-(define_expand "reload_outqi"
-  [(parallel [(set (match_operand:QI 0 "symbolic_memory_operand" "=m")
-		   (match_operand:QI 1 "" "r"))
-	      (clobber (match_operand:SI 2 "" "=&b"))])]
-  ""
-  "")
-
-;; Finally, the HI instructions.
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{ rtx op0 = operands[0];
-
-  if (GET_CODE (op0) == MEM && ! reload_in_progress)
-    {
-      emit_insn (gen_storehi (operands[0], force_reg (HImode, operands[1])));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=b")
-	(match_operand:HI 1 "symbolic_memory_operand" "m"))]
-  ""
-  "loadha %0,%1"
-  [(set_attr "type" "load")])
-
-
-;; use cal16 instead of cal for constant source because combine requires
-;; the high bits of the register to be 0 after a HImode load of a constant
-
-(define_insn ""
-  [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,b,Q")
-	(match_operand:HI 1 "romp_operand" "r,I,n,s,Q,m,r"))]
-  "register_operand (operands[0], HImode)
-   || register_operand (operands[1], HImode)"
-  "@
-   cas %0,%1,r0
-   lis %0,%1
-   cal16 %0,%L1(r0)
-   get %0,$%1
-   lh%N1 %0,%1
-   loadh %0,%1
-   sth%M0 %1,%0"
-  [(set_attr "type" "address,address,address,misc,loadz,loadz,store")
-   (set_attr "length" "2,2,4,8,*,*,*")])
-
-(define_insn "storehi"
-  [(set (match_operand:HI 0 "memory_operand" "=Q,m")
-	(match_operand:HI 1 "register_operand" "r,r"))
-   (clobber (match_scratch:SI 2 "=X,&b"))]
-  ""
-  "@
-   sth%M0 %1,%0
-   storeh %1,%0,%2"
-  [(set_attr "type" "store")])
-
-(define_expand "reload_outhi"
-  [(parallel [(set (match_operand:HI 0 "symbolic_memory_operand" "=m")
-		   (match_operand:HI 1 "" "r"))
-	      (clobber (match_operand:SI 2 "" "=&b"))])]
-  ""
-  "")
-
-;; For DI move, if we have a constant, break the operation apart into
-;; two SImode moves because the optimizer may be able to do a better job
-;; with the resulting code.
-;;
-;; For memory stores, make the required pseudo for a temporary in case we
-;; are storing into an absolute address.
-;;
-;; We need to be careful about the cases where the output is a register that is
-;; the second register of the input.
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{ rtx op0 = operands[0];
-  rtx op1 = operands[1];
- 
-  if (CONSTANT_P (op1))
-    {
-      rtx insns;
-
-      start_sequence ();
-      emit_move_insn (operand_subword (op0, 0, 1, DImode),
-		      operand_subword (op1, 0, 1, DImode));
-      emit_move_insn (operand_subword (op0, 1, 1, DImode),
-		      operand_subword (op1, 1, 1, DImode));
-      insns = get_insns ();
-      end_sequence ();
-
-      emit_no_conflict_block (insns, op0, op1, 0, op1);
-      DONE;
-    }
-
-  if (GET_CODE (op0) == MEM && ! reload_in_progress)
-    {
-      emit_insn (gen_storedi (operands[0], force_reg (DImode, operands[1])));
-      DONE;
-    }
-}")
-
-(define_insn ""
- [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,Q")
-       (match_operand:DI 1 "reg_or_mem_operand" "r,Q,m,r"))]
-  "register_operand (operands[0], DImode)
-   || register_operand (operands[1], DImode)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
-	return \"cas %O0,%O1,r0\;cas %0,%1,r0\";
-      else
-	return \"cas %0,%1,r0\;cas %O0,%O1,r0\";
-    case 1:
-      /* Here we must see which word to load first.  We default to the
-	 low-order word unless it occurs in the address.  */
-      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			     operands[1], 0))
-	return \"l%M1 %O0,%O1\;l%M1 %0,%1\";
-      else
-	return \"l%M1 %0,%1\;l%M1 %O0,%O1\";
-    case 2:
-      return \"get %O0,$%1\;ls %0,0(%O0)\;ls %O0,4(%O0)\";
-    case 3:
-      return \"st%M0 %1,%0\;st%M0 %O1,%O0\";
-    }
-}"
-  [(set_attr "type" "multi")
-   (set_attr "cc" "change0,change0,change0,none")
-   (set_attr "length" "4,12,8,8")])
-
-(define_insn "storedi"
-  [(set (match_operand:DI 0 "memory_operand" "=Q,m")
-	(match_operand:DI 1 "register_operand" "r,r"))
-   (clobber (match_scratch:SI 2 "=X,&b"))]
-  ""
-  "@
-   st%M0 %1,%0\;st%M0 %O1,%O0
-   get %2,$%0\;sts %1,0(%2)\;sts %O1,4(%2)"
-  [(set_attr "type" "multi,multi")
-   (set_attr "cc" "none,none")
-   (set_attr "length" "8,12")])
-
-(define_expand "reload_outdi"
-  [(parallel [(set (match_operand:DI 0 "symbolic_memory_operand" "=m")
-		   (match_operand:DI 1 "" "r"))
-	      (clobber (match_operand:SI 2 "" "=&b"))])]
-  ""
-  "")
-
-;; Split symbolic memory operands differently.  We first load the address
-;; into a register and then do the two loads or stores.  We can only do
-;; this if operand_subword won't produce a SUBREG, which is only when
-;; operands[0] is a hard register.  Thus, these won't be used during the
-;; first insn scheduling pass.
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_operand:DI 1 "symbolic_memory_operand" ""))]
-  "GET_CODE (operands[0]) == REG
-   && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 5))
-   (set (match_dup 6) (match_dup 7))]
-  "
-{ operands[2] = operand_subword (operands[0], 1, 0, DImode);
-  operands[3] = XEXP (operands[1], 0);
-  operands[4] = operand_subword (operands[0], 0, 0, DImode);
-  operands[5] = gen_rtx (MEM, SImode, operands[2]);
-  operands[6] = operands[2];
-  operands[7] = gen_rtx (MEM, SImode,
-			 gen_rtx (PLUS, SImode, operands[2],
-				  GEN_INT (4)));
-
-  if (operands[2] == 0 || operands[4] == 0)
-    FAIL;
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "symbolic_memory_operand" "")
-	(match_operand:DI 1 "register_operand" ""))
-   (clobber (match_operand:SI 2 "register_operand" ""))] 
-  "GET_CODE (operands[0]) == REG
-   && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 5))
-   (set (match_dup 6) (match_dup 7))]
-  "
-{ operands[3] = XEXP (operands[0], 0);
-  operands[4] = gen_rtx (MEM, SImode, operands[2]);
-  operands[5] = operand_subword (operands[1], 0, 0, DImode);
-  operands[6] = gen_rtx (MEM, SImode,
-			 gen_rtx (PLUS, SImode, operands[2],
-				  GEN_INT (4)));
-  operands[7] = operand_subword (operands[1], 1, 0, DImode);
-
-  if (operands[5] == 0 || operands[7] == 0)
-    FAIL;
-}")
-
-;; If the output is a register and the input is memory, we have to be careful
-;; and see which word needs to be loaded first.
-;;
-;; Note that this case doesn't have a CLOBBER.   Therefore, we must either
-;; be after reload or operand[0] must not be a MEM.  So we don't need a
-;; CLOBBER on the new insns either.
-;;
-;; Due to a bug in sched.c, we do not want to split this insn if both
-;; operands are registers and they overlap unless reload has completed.
-(define_split
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  "! symbolic_memory_operand (operands[0], DImode)
-   && ! symbolic_memory_operand (operands[1], DImode)
-   && ! (GET_CODE (operands[0]) == REG
-         && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
-   && ! (GET_CODE (operands[1]) == REG
-         && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
-   && ! (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
-	 && ! reload_completed
-	 && reg_overlap_mentioned_p (operands[0], operands[1]))"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 5))]
-  "
-{ if (GET_CODE (operands[0]) != REG
-      || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			      operands[1], 0))
-    {
-      operands[2] = operand_subword (operands[0], 0, 0, DImode);
-      operands[3] = operand_subword (operands[1], 0, 0, DImode);
-      operands[4] = operand_subword (operands[0], 1, 0, DImode);
-      operands[5] = operand_subword (operands[1], 1, 0, DImode);
-    }
-  else
-    {
-      operands[2] = operand_subword (operands[0], 1, 0, DImode);
-      operands[3] = operand_subword (operands[1], 1, 0, DImode);
-      operands[4] = operand_subword (operands[0], 0, 0, DImode);
-      operands[5] = operand_subword (operands[1], 0, 0, DImode);
-    }
-
-  if (operands[2] == 0 || operands[3] == 0
-      || operands[4] == 0 || operands[5] == 0)
-    FAIL;
-}")
-
-(define_split
- [(set (match_operand:DI 0 "general_operand" "")
-       (match_operand:DI 1 "general_operand" ""))
-  (clobber (match_operand:SI 6 "register_operand" ""))]
-  "! symbolic_memory_operand (operands[0], DImode)
-   && ! symbolic_memory_operand (operands[1], DImode)
-   && ! (GET_CODE (operands[0]) == REG
-         && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
-   && ! (GET_CODE (operands[1]) == REG
-         && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
-   && ! (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
-	 && ! reload_completed
-	 && reg_overlap_mentioned_p (operands[0], operands[1]))"
- [(parallel [(set (match_dup 2) (match_dup 3))
-	     (clobber (match_dup 7))])
-  (parallel [(set (match_dup 4) (match_dup 5))
-	     (clobber (match_dup 8))])]
- "
-{ if (GET_CODE (operands[0]) != REG
-      || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			      operands[1], 0))
-    {
-      operands[2] = operand_subword (operands[0], 0, 0, DImode);
-      operands[3] = operand_subword (operands[1], 0, 0, DImode);
-      operands[4] = operand_subword (operands[0], 1, 0, DImode);
-      operands[5] = operand_subword (operands[1], 1, 0, DImode);
-    }
-  else
-    {
-      operands[2] = operand_subword (operands[0], 1, 0, DImode);
-      operands[3] = operand_subword (operands[1], 1, 0, DImode);
-      operands[4] = operand_subword (operands[0], 0, 0, DImode);
-      operands[5] = operand_subword (operands[1], 0, 0, DImode);
-    }
-
-  if (operands[2] == 0 || operands[3] == 0
-      || operands[4] == 0 || operands[5] == 0)
-    FAIL;
-
-  /* We must be sure to make two different SCRATCH operands, since they
-     are not allowed to be shared.  After reload, however, we only have
-     a SCRATCH if we won't use the operand, so it is allowed to share it
-     then.  */
-  if (reload_completed || GET_CODE (operands[6]) != SCRATCH)
-    operands[7] = operands[8] = operands[6];
-  else
-    {
-      operands[7] = gen_rtx (SCRATCH, SImode);
-      operands[8] = gen_rtx (SCRATCH, SImode);
-    }
-}")
-
-;; Define move insns for SF, and DF.
-;;
-;; For register-register copies or a copy of something to itself, emit a
-;; single SET insn since it will likely be optimized away.
-;;
-;; Otherwise, emit a floating-point move operation unless both input and
-;; output are either constant, memory, or a non-floating-point hard register.
-(define_expand "movdf"
-  [(parallel [(set (match_operand:DF 0 "general_operand" "")
-		   (match_operand:DF 1 "general_operand" ""))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "
-{ rtx op0 = operands[0];
-  rtx op1 = operands[1];
-
-  if (op0 == op1)
-    {
-      emit_insn (gen_rtx (SET, VOIDmode, op0, op1));
-      DONE;
-    }
-
-  if ((GET_CODE (op0) == MEM
-       || (GET_CODE (op0) == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER
-	   && ! FP_REGNO_P (REGNO (op0))))
-      && (GET_CODE (op1) == MEM
-	  || GET_CODE (op1) == CONST_DOUBLE
-	  || (GET_CODE (op1) == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER
-	      && ! FP_REGNO_P (REGNO (op1)) && ! rtx_equal_p (op0, op1))))
-    {
-      rtx insns;
-
-      if (GET_CODE (op1) == CONST_DOUBLE)
-	op1 = force_const_mem (DFmode, op1);
-
-      start_sequence ();
-      if (GET_CODE (operands[0]) != REG
-	  || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-				  operands[1]), 0)
-	{
-	  emit_move_insn (operand_subword (op0, 0, 1, DFmode),
-			  operand_subword_force (op1, 0, DFmode));
-	  emit_move_insn (operand_subword (op0, 1, 1, DFmode),
-			  operand_subword_force (op1, 1, DFmode));
-	}
-      else
-	{
-	  emit_move_insn (operand_subword (op0, 1, 1, DFmode),
-			  operand_subword_force (op1, 1, DFmode));
-	  emit_move_insn (operand_subword (op0, 0, 1, DFmode),
-			  operand_subword_force (op1, 0, DFmode));
-	}
-
-      insns = get_insns ();
-      end_sequence ();
-
-      emit_no_conflict_block (insns, op0, op1, 0, op1);
-      DONE;
-    }
-}")
-
-(define_expand "movsf"
-  [(parallel [(set (match_operand:SF 0 "general_operand" "")
-		   (match_operand:SF 1 "general_operand" ""))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "
-{ rtx op0 = operands[0];
-  rtx op1 = operands[1];
-  
-  if (op0 == op1)
-    {
-      emit_insn (gen_rtx (SET, VOIDmode, op0, op1));
-      DONE;
-    }
-
-  if ((GET_CODE (op0) == MEM
-       || (GET_CODE (op0) == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER
-	   && ! FP_REGNO_P (REGNO (op0))))
-       && (GET_CODE (op1) == MEM
-	   || GET_CODE (op1) == CONST_DOUBLE
-	   || (GET_CODE (op1) == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER
-	       && ! FP_REGNO_P (REGNO (op1)))))
-    {
-      rtx last;
-
-      if (GET_CODE (op1) == CONST_DOUBLE)
-	op1 = force_const_mem (SFmode, op1);
-
-      last = emit_move_insn (operand_subword (op0, 0, 1, SFmode),
-			     operand_subword_force (op1, 0, SFmode));
-
-      REG_NOTES (last) = gen_rtx (EXPR_LIST, REG_EQUAL, op1, REG_NOTES (last));
-      DONE;
-    }
-}")
-
-;; Define the move insns for SF and DF.  Check for all general regs
-;; in the FP insns and make them non-FP if so.  Do the same if the input and
-;; output are the same (the insn will be deleted in this case and we don't
-;; want to think there are FP insns when there might not be).
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=*frg")
-	(match_dup 0))]
-  ""
-  "nopr r0"
-  [(set_attr "type" "address")
-   (set_attr "length" "2")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=r,*fr,r,r,Q,m,frg")
-	(match_operand:SF 1 "general_operand" "r,0,Q,m,r,r,frg"))
-   (clobber (match_operand:SI 2 "reg_0_operand" "=&z,z,z,z,z,z,z"))
-   (clobber (match_operand:SI 3 "reg_15_operand" "=&t,t,t,t,t,t,t"))]
-  ""
-  "*
-{ switch (which_alternative)
-    {
-    case 0:
-      return \"cas %0,%1,r0\";
-    case 1:
-      return \"nopr r0\";
-    case 2:
-      return \"l%M1 %0,%1\";
-    case 3:
-      return \"load %0,%1\";
-    case 4:
-      return \"st%M0 %1,%0\";
-    case 5:
-      return \"store %1,%0,%3\";
-    default:
-      return output_fpop (SET, operands[0], operands[1], 0, insn);
-    }
-}"
-  [(set_attr "type" "address,address,load,load,store,store,fp")
-   (set_attr "length" "2,2,*,*,*,*,*")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=*frg")
-	(match_dup 0))]
-  ""
-  "nopr r0"
-  [(set_attr "type" "address")
-   (set_attr "length" "2")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=r,*fr,r,r,Q,m,frg")
-	(match_operand:DF 1 "general_operand" "r,0,Q,m,r,r,*frg"))
-   (clobber (match_operand:SI 2 "reg_0_operand" "=&z,z,z,z,z,z,z"))
-   (clobber (match_operand:SI 3 "reg_15_operand" "=&t,t,t,t,t,t,t"))]
-  ""
-  "*
-{ switch (which_alternative)
-    {
-    case 0:
-      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
-	return \"cas %O0,%O1,r0\;cas %0,%1,r0\";
-      else
-	return \"cas %0,%1,r0\;cas %O0,%O1,r0\";
-    case 1:
-      return \"nopr r0\";
-    case 2:
-      /* Here we must see which word to load first.  We default to the
-	 low-order word unless it occurs in the address.  */
-      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			     operands[1], 0))
-	return \"l%M1 %O0,%O1\;l%M1 %0,%1\";
-      else
-	return \"l%M1 %0,%1\;l%M1 %O0,%O1\";
-    case 3:
-      return \"get %3,$%1\;ls %0,0(%3)\;ls %O0,4(%3)\";
-    case 4:
-      return \"st%M0 %1,%0\;st%M0 %O1,%O0\";
-    case 5:
-      return \"get %3,$%0\;sts %1,0(%3)\;sts %O1,4(%3)\";
-    default:
-      return output_fpop (SET, operands[0], operands[1], 0, insn);
-    }
-}"
-  [(set_attr "type" "address,multi,multi,multi,multi,multi,fp")
-   (set_attr "length" "2,4,*,*,*,*,*")])
-
-;; Split all the above cases that involve multiple insns and no floating-point
-;; data block.  If before reload, we can make a SCRATCH.  Otherwise, use
-;; register 15.
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-	(match_operand:DF 1 "symbolic_memory_operand" ""))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 15))]
-  "GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 16"
-  [(set (reg:SI 15) (match_dup 2))
-   (set (match_dup 3) (match_dup 4))
-   (set (match_dup 5) (match_dup 6))]
-  "
-{ operands[2] = XEXP (operands[1], 0);
-  operands[3] = operand_subword (operands[0], 0, 0, DFmode);
-  operands[4] = gen_rtx (MEM, SImode, gen_rtx (REG, SImode, 15));
-  operands[5] = operand_subword (operands[0], 1, 0, DFmode);
-  operands[6] = gen_rtx (MEM, SImode,
-			 gen_rtx (PLUS, SImode, gen_rtx (REG, SImode, 15),
-				  GEN_INT (4)));
-
-  if (operands[3] == 0 || operands[5] == 0)
-    FAIL;
-}")
-
-(define_split
-  [(set (match_operand:DF 0 "symbolic_memory_operand" "")
-	(match_operand:DF 1 "register_operand" ""))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 15))]
-  "GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 16"
-  [(set (reg:SI 15) (match_dup 2))
-   (set (match_dup 3) (match_dup 4))
-   (set (match_dup 5) (match_dup 6))]
-  "
-{ operands[2] = XEXP (operands[0], 0);
-  operands[3] = gen_rtx (MEM, SImode, gen_rtx (REG, SImode, 15));
-  operands[4] = operand_subword (operands[1], 0, 0, DFmode);
-  operands[5] = gen_rtx (MEM, SImode,
-			 gen_rtx (PLUS, SImode, gen_rtx (REG, SImode, 15),
-				  GEN_INT (4)));
-  operands[6] = operand_subword (operands[1], 1, 0, DFmode);
-
-  if (operands[4] == 0 || operands[6] == 0)
-    FAIL;
-}")
-
-;; If the output is a register and the input is memory, we have to be careful
-;; and see which word needs to be loaded first.  We also cannot to the
-;; split if the input is a constant because it would result in invalid
-;; insns.  When the output is a MEM, we must put a CLOBBER on each of the
-;; resulting insn, when it is not a MEM, we must not.
-(define_split
-  [(set (match_operand:DF 0 "memory_operand" "")
-	(match_operand:DF 1 "register_operand" ""))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 15))]
-  "GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 15"
-  [(parallel [(set (match_dup 2) (match_dup 3))
-	      (clobber (match_dup 6))])
-   (parallel [(set (match_dup 4) (match_dup 5))
-	      (clobber (match_dup 7))])]
-  "
-{ operands[2] = operand_subword (operands[0], 0, 0, DFmode);
-  operands[3] = operand_subword (operands[1], 0, 0, DFmode);
-  operands[4] = operand_subword (operands[0], 1, 0, DFmode);
-  operands[5] = operand_subword (operands[1], 1, 0, DFmode);
-
-  if (operands[2] == 0 || operands[3] == 0
-      || operands[4] == 0 || operands[5] == 0)
-    FAIL;
-
-  if (reload_completed)
-    operands[6] = operands[7] = gen_rtx (REG, SImode, 15);
-  else
-    {
-      operands[6] = gen_rtx (SCRATCH, SImode);
-      operands[7] = gen_rtx (SCRATCH, SImode);
-    }
-}")
-
-(define_split
-  [(set (match_operand:DF 0 "nonmemory_operand" "")
-	(match_operand:DF 1 "general_operand" ""))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 15))]
-  "! symbolic_memory_operand (operands[1], DFmode)
-   && GET_CODE (operands[1]) != CONST_DOUBLE
-   && (GET_CODE (operands[0]) != REG || REGNO (operands[0]) < 15)
-   && (GET_CODE (operands[1]) != REG || REGNO (operands[1]) < 15)
-   && (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)
-   && ! (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
-	 && ! reload_completed
-	 && reg_overlap_mentioned_p (operands[0], operands[1]))"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 5))]
-  "
-{ if (GET_CODE (operands[0]) != REG
-      || ! refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			      operands[1], 0))
-    {
-      operands[2] = operand_subword (operands[0], 0, 0, DFmode);
-      operands[3] = operand_subword (operands[1], 0, 0, DFmode);
-      operands[4] = operand_subword (operands[0], 1, 0, DFmode);
-      operands[5] = operand_subword (operands[1], 1, 0, DFmode);
-    }
-  else
-    {
-      operands[2] = operand_subword (operands[0], 1, 0, DFmode);
-      operands[3] = operand_subword (operands[1], 1, 0, DFmode);
-      operands[4] = operand_subword (operands[0], 0, 0, DFmode);
-      operands[5] = operand_subword (operands[1], 0, 0, DFmode);
-    }
-
-  if (operands[2] == 0 || operands[3] == 0
-      || operands[4] == 0 || operands[5] == 0)
-    FAIL;
-}")
-
-;; Conversions from one integer mode to another.
-;; It is possible sometimes to sign- or zero-extend while fetching from memory.
-;;
-;; First, sign-extensions:
-(define_expand "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=b")
-	(sign_extend:SI (match_operand:HI 1 "symbolic_memory_operand" "m")))]
-  ""
-  "loadha %0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,b")
-	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Q,m")))]
-  ""
-  "@
-   exts %0,%1
-   lha%M1 %0,%1
-   loadha %0,%1"
-  [(set_attr "type" "arith,load,load")
-   (set_attr "length" "2,*,*")])
-
-(define_expand "extendqisi2"
-  [(set (match_dup 2)
-	(ashift:SI (match_operand:QI 1 "register_operand" "")
-		   (const_int 24)))
-   (set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:SI (match_dup 2)
-		     (const_int 24)))]
-  ""
-  "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "extendqihi2"
-  [(set (match_dup 2)
-	(ashift:SI (match_operand:QI 1 "register_operand" "")
-		   (const_int 24)))
-   (set (match_operand:HI 0 "register_operand" "")
-	(ashiftrt:SI (match_dup 2)
-		     (const_int 24)))]
-  ""
-  "
-{ operands[0] = gen_lowpart (SImode, operands[0]);
-  operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
-;; Define peepholes to eliminate an instruction when we are doing a sign
-;; extension but cannot clobber the input.
-;;
-;; In this case we will shift left 24 bits, but need a copy first.  The shift
-;; can be replaced by a "mc03" instruction, but this can only be done if
-;; followed by the right shift of 24 or more bits.
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "")
-	(subreg:SI (match_operand:QI 1 "register_operand" "") 0))
-   (set (match_dup 0)
-	(ashift:SI (match_dup 0)
-		   (const_int 24)))
-   (set (match_dup 0)
-	(ashiftrt:SI (match_dup 0)
-		     (match_operand:SI 2 "const_int_operand" "")))]
-  "INTVAL (operands[2]) >= 24"
-  "mc03 %0,%1\;sari16 %0,%S2"
- [(set_attr "type" "multi")
-  (set_attr "length" "4")
-  (set_attr "cc" "sets")])
-
-;; Now zero extensions:
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=b")
-	(zero_extend:SI (match_operand:HI 1 "symbolic_memory_operand" "m")))]
-  ""
-  "loadh %0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,b")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,Q,m")))]
-  ""
-  "@
-   nilz %0,%1,65535
-   lh%N1 %0,%1
-   loadh %0,%1"
-  [(set_attr "type" "arith,loadz,load")])
-
-(define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=b")
-	(zero_extend:SI (match_operand:QI 1 "symbolic_memory_operand" "m")))]
-  ""
-  "loadc %0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,b")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Q,m")))]
-  ""
-  "@
-   nilz %0,%1,255
-   lc%M1 %0,%1
-   loadc %0,%1"
-  [(set_attr "type" "arith,load,load")])
-
-(define_expand "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=b")
-	(zero_extend:HI (match_operand:QI 1 "symbolic_memory_operand" "m")))]
-  ""
-  "loadc %0,%1"
-  [(set_attr "type" "load")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r,b")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,Q,m")))]
-  ""
-  "@
-   nilz %0,%1,255
-   lc%M1 %0,%1
-   loadc %0,%1"
-  [(set_attr "type" "arith,load,load")])
-
-;; Various extract and insertion operations.
-(define_expand "extzv"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "")
-			 (match_operand:SI 2 "const_int_operand" "")
-			 (match_operand:SI 3 "const_int_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
-    FAIL;
-
-  if (GET_CODE (operands[3]) != CONST_INT)
-    FAIL;
-
-  if (INTVAL (operands[3]) != 0 && INTVAL (operands[3]) != 8
-      && INTVAL (operands[3]) != 16 && INTVAL (operands[3]) != 24)
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (const_int 8)
-			 (match_operand:SI 2 "const_int_operand" "n")))]
-  "(INTVAL (operands[2]) & 7) == 0"
-  "lis %0,0\;mc3%B2 %0,%1"
-  [(set_attr "type" "multi")
-   (set_attr "cc" "change0")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (const_int 8)
-			 (match_operand:SI 2 "const_int_operand" "n")))]
-  "(INTVAL (operands[2]) & 7) == 0"
-  [(set (match_dup 0) (const_int 0))
-   (set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 24))
-	(zero_extract:SI (match_dup 1) (const_int 8) (match_dup 2)))]
-  "")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-			 (const_int 8)
-			 (const_int 24))
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (const_int 8)
-			 (match_operand:SI 2 "const_int_operand" "n")))]
-  "(INTVAL (operands[2]) & 7) == 0"
-  "mc3%B2 %0,%1"
-  [(set_attr "type" "address")
-   (set_attr "length" "2")])
-
-(define_expand "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
-			 (match_operand:SI 1 "const_int_operand" "")
-			 (match_operand:SI 2 "const_int_operand" ""))
-	(match_operand:SI 3 "register_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    FAIL;
-
-  if (GET_CODE (operands[1]) != CONST_INT)
-    FAIL;
-
-  if (INTVAL (operands[1]) == 1)
-    {
-      emit_insn (gen_bit_insv (operands[0], operands[1], operands[2],
-			       operands[3]));
-      DONE;
-    }
-  else if (INTVAL (operands[1]) == 8
-	   && (INTVAL (operands[2]) % 8 == 0))
-    ;				/* Accept aligned byte-wide field. */
-  else
-    FAIL;
-}")
-
-;; For a single-bit insert, it is better to explicitly generate references
-;; to the T bit.  We will call the T bit "CC0" because it can be clobbered
-;; by some CC0 sets (single-bit tests).
-
-(define_expand "bit_insv"
-  [(set (cc0)
-	(zero_extract:SI (match_operand:SI 3 "register_operand" "")
-			 (const_int 1)
-			 (const_int 31)))
-   (parallel [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
-				    (match_operand:SI 1 "const_int_operand" "")
-				    (match_operand:SI 2 "const_int_operand" ""))
-		   (ne (cc0) (const_int 0)))
-	      (clobber (match_scratch:SI 4 ""))])]
-  ""
-  "")
-	
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-			 (const_int 8)
-			 (match_operand:SI 1 "const_int_operand" "n"))
-	(match_operand:SI 2 "register_operand" "r"))]
-  "(INTVAL (operands[1]) & 7) == 0"
-  "mc%B1%.3 %0,%2"
-  [(set_attr "type" "address")
-   (set_attr "length" "2")])
-
-;; This pattern cannot have any input reloads since if references CC0.
-;; So we have to add code to support memory, which is the only other
-;; thing that a "register_operand" can become.  There is still a problem
-;; if the address isn't valid and *it* needs a reload, but there is no
-;; way to solve that problem, so let's hope it never happens.
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,m")
-			 (const_int 1)
-			 (match_operand:SI 1 "const_int_operand" "n,m"))
-	(ne (cc0) (const_int 0)))
-   (clobber (match_scratch:SI 2 "=X,b"))]
-  ""
-  "@
-   mftbi%t1 %0,%S1
-   l%M0 %2,%0\;mftb%t1 %2,%S1\;st%M0 %2,%0"
-  [(set_attr "type" "*,multi")
-   (set_attr "cc" "none,none")
-   (set_attr "length" "2,10")])
-
-;; Arithmetic instructions.  First, add and subtract.
-;;
-;; It may be that the second input is either large or small enough that
-;; the operation cannot be done in a single insn.  In that case, emit two.
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned) (INTVAL (operands[2]) + 0x8000) >= 0x10000
-      && (INTVAL (operands[2]) & 0xffff) != 0)
-    {
-      int low = INTVAL (operands[2]) & 0xffff;
-      int high = (unsigned) INTVAL (operands[2]) >> 16;
-
-      if (low & 0x8000)
-	high++, low |= 0xffff0000;
-
-      emit_insn (gen_addsi3 (operands[0], operands[1],
-			     GEN_INT (high << 16)));
-      operands[1] = operands[0];
-      operands[2] = GEN_INT (low);
-    }
-}")
-
-;; Put the insn to add a symbolic constant to a register separately to
-;; improve register allocation since it has different register requirements.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=b")
-	(plus:SI (match_operand:SI 1 "register_operand" "%b")
-		 (match_operand:SI 2 "romp_symbolic_operand" "s")))]
-   ""
-   "get %0,$%2(%1)"
-   [(set_attr "type" "address")
-    (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,b")
-	(plus:SI (match_operand:SI 1 "reg_or_add_operand" "%0,0,r,b,0,r,b")
-		 (match_operand:SI 2 "reg_or_add_operand" "I,J,K,M,r,b,s")))]
-  "register_operand (operands[1], SImode)
-   || register_operand (operands[2], SImode)"
-  "@
-   ais %0,%2
-   sis %0,%n2
-   ail %0,%1,%2
-   cau %0,%H2(%1)
-   a %0,%2
-   cas %0,%1,%2
-   get %0,$%2(%1)"
-  [(set_attr "type" "arith,arith,arith,address,arith,address,misc")
-   (set_attr "length" "2,2,4,4,2,2,8")])
-
-;; Now subtract.
-;;
-;; 1.	If third operand is constant integer, convert it to add of the negative
-;;	of that integer.
-;; 2.	If the second operand is not a valid constant integer, force it into a
-;;	register.
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 1 "reg_or_any_cint_operand" "")
-		  (match_operand:SI 2 "reg_or_any_cint_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands [2]) == CONST_INT)
-    {
-      emit_insn (gen_addsi3 (operands[0], operands[1], 
-			     GEN_INT (- INTVAL (operands[2]))));
-      DONE;
-    }
-  else
-    operands[2] = force_reg (SImode, operands[2]);
-
-  if (GET_CODE (operands[1]) != CONST_INT
-      || (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000)
-    operands[1] = force_reg (SImode, operands[1]);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(minus:SI (match_operand:SI 1 "reg_or_D_operand" "K,0,r")
-		  (match_operand:SI 2 "register_operand" "r,r,0")))]
-  ""
-  "@
-   sfi %0,%2,%1
-   s %0,%2
-   sf %0,%1"
-  [(set_attr "length" "4,2,2")])
-
-;; Multiply either calls a special RT routine or is done in-line, depending
-;; on the value of a -m flag.
-;;
-;; First define the way we call the subroutine.
-(define_expand "mulsi3_subr"
-  [(set (reg:SI 2) (match_operand:SI 1 "register_operand" ""))
-   (set (reg:SI 3) (match_operand:SI 2 "register_operand" ""))
-   (parallel [(set (reg:SI 2) (mult:SI (reg:SI 2) (reg:SI 3)))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])
-   (set (match_operand:SI 0 "register_operand" "")
-	(reg:SI 2))]
-  ""
-  "")
-
-(define_expand "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(mult:SI (match_operand:SI 1 "register_operand" "")
-		 (match_operand:SI 2 "register_operand" "")))]
-  ""
-  "
-{
-  if (! TARGET_IN_LINE_MUL)
-    {
-      emit_insn (gen_mulsi3_subr (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-;; Define the patterns to match.
-;; We would like to provide a delay slot for the insns that call internal
-;; routines, but doing so is risky since reorg will think that the use of
-;; r2 and r3 is completed in the insn needing the delay slot.  Also, it
-;; won't know that the cc will be clobbered.  So take the safe approach
-;; and don't give them delay slots.
-(define_insn ""
-  [(set (reg:SI 2)
-	(mult:SI (reg:SI 2) (reg:SI 3)))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 15))]
-  "! TARGET_IN_LINE_MUL"
-  "bali%# r15,lmul$$"
-  [(set_attr "type" "misc")
-   (set_attr "in_delay_slot" "no")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(mult:SI (match_operand:SI 1 "register_operand" "%r")
-		 (match_operand:SI 2 "register_operand" "r")))]
-  "TARGET_IN_LINE_MUL"
-  "*
-{ return output_in_line_mul (); }"
-  [(set_attr "length" "38")
-   (set_attr "type" "multi")])
-
-;; Handle divide and modulus.  The same function returns both values,
-;; so use divmodsi4.  This divides arg 1 by arg 2 with quotient to go
-;; into arg 0 and remainder in arg 3.
-;;
-;; We want to put REG_EQUAL notes for the two outputs.  So we need a
-;; function to do everything else.
-(define_expand "divmodsi4_doit"
-  [(set (reg:SI 2)
-	(match_operand:SI 0 "register_operand" ""))
-   (set (reg:SI 3)
-	(match_operand:SI 1 "register_operand" ""))
-   (parallel [(set (reg:SI 2) (div:SI (reg:SI 2) (reg:SI 3)))
-	      (set (reg:SI 3) (mod:SI (reg:SI 2) (reg:SI 3)))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "divmodsi4"
-  [(parallel [(set (match_operand:SI 0 "register_operand" "")
-		   (div:SI (match_operand:SI 1 "register_operand" "")
-			   (match_operand:SI 2 "register_operand" "")))
-	      (set (match_operand:SI 3 "register_operand" "")
-		   (mod:SI (match_dup 1) (match_dup 2)))])]
-  ""
-  "
-{
-  rtx insn;
-
-  emit_insn (gen_divmodsi4_doit (operands[1], operands[2]));
-  insn = emit_move_insn (operands[0], gen_rtx (REG, SImode, 2));
-  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL,
-			      gen_rtx (DIV, SImode, operands[1],
-				       operands[2]),
-			      REG_NOTES (insn));
-  insn = emit_move_insn (operands[3], gen_rtx (REG, SImode, 3));
-  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL,
-			      gen_rtx (MOD, SImode, operands[1],
-				       operands[2]),
-			      REG_NOTES (insn));
-  DONE;
-}")
-
-(define_insn ""
-  [(set (reg:SI 2)
-	(div:SI (reg:SI 2) (reg:SI 3)))
-   (set (reg:SI 3)
-	(mod:SI (reg:SI 2) (reg:SI 3)))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 15))]
-  ""
-  "bali%# r15,ldiv$$"
-  [(set_attr "type" "misc")
-   (set_attr "in_delay_slot" "no")])
-
-;; Similarly for unsigned divide.
-(define_expand "udivmodsi4_doit"
-  [(set (reg:SI 2)
-	(match_operand:SI 0 "register_operand" ""))
-   (set (reg:SI 3)
-	(match_operand:SI 1 "register_operand" ""))
-   (parallel [(set (reg:SI 2) (udiv:SI (reg:SI 2) (reg:SI 3)))
-	      (set (reg:SI 3) (umod:SI (reg:SI 2) (reg:SI 3)))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "udivmodsi4"
-  [(parallel [(set (match_operand:SI 0 "register_operand" "")
-		   (udiv:SI (match_operand:SI 1 "register_operand" "")
-			    (match_operand:SI 2 "register_operand" "")))
-	      (set (match_operand:SI 3 "register_operand" "")
-		   (umod:SI (match_dup 1) (match_dup 2)))])]
-  ""
-  "
-{
-  rtx insn;
-
-  emit_insn (gen_udivmodsi4_doit (operands[1], operands[2]));
-  insn = emit_move_insn (operands[0], gen_rtx (REG, SImode, 2));
-  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL,
-			      gen_rtx (UDIV, SImode, operands[1],
-				       operands[2]),
-			      REG_NOTES (insn));
-  insn = emit_move_insn (operands[3], gen_rtx (REG, SImode, 3));
-  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL,
-			      gen_rtx (UMOD, SImode, operands[1],
-				       operands[2]),
-			      REG_NOTES (insn));
-  DONE;
-}")
-
-(define_insn ""
-  [(set (reg:SI 2)
-	(udiv:SI (reg:SI 2) (reg:SI 3)))
-   (set (reg:SI 3)
-	(umod:SI (reg:SI 2) (reg:SI 3)))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 15))]
-  ""
-  "bali%# r15,uldiv$$"
-  [(set_attr "type" "misc")
-   (set_attr "in_delay_slot" "no")])
-
-;; Define DImode arithmetic operations.
-;;
-;; It is possible to do certain adds and subtracts with constants in a single
-;; insn, but it doesn't seem worth the trouble.
-;;
-;; Don't use DEFINE_SPLIT on these because the dependency on CC can't be
-;; easily tracked in that case!
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_operand:DI 1 "register_operand" "%0")
-		 (match_operand:DI 2 "register_operand" "r")))]
-  ""
-  "a %O0,%O2\;ae %0,%2"
-  [(set_attr "type" "multi")])
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "register_operand" "0")
-		  (match_operand:DI 2 "register_operand" "r")))]
-  ""
-  "s %O0,%O2\;se %0,%2"
-  [(set_attr "type" "multi")])
-
-(define_insn "negdi2"
-  [(set (match_operand:DI 0 "register_operand" "=r,&r")
-	(neg:DI (match_operand:DI 1 "register_operand" "0,r")))]
-  ""
-  "twoc %O0,%O1\;onec %0,%1\;aei %0,%0,0"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
-;; Unary arithmetic operations.
-(define_insn "abssi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(abs:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "abs %0,%1"
-  [(set_attr "length" "2")])
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "twoc %0,%1"
-  [(set_attr "length" "2")])
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "onec %0,%1"
-  [(set_attr "length" "2")])
-
-
-;; Logical insns: AND, IOR, and XOR
-;;
-;; If the operation is being performed on a 32-bit constant such that
-;; it cannot be done in one insn, do it in two.  We may lose a bit on
-;; CSE in pathological cases, but it seems better doing it this way.
-(define_expand "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(and:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "reg_or_any_cint_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int top = (unsigned) INTVAL (operands[2]) >> 16;
-      int bottom = INTVAL (operands[2]) & 0xffff;
-
-      if (top != 0 && top != 0xffff && bottom != 0 && bottom != 0xffff)
-	{
-	  emit_insn (gen_andsi3 (operands[0], operands[1],
-				 GEN_INT ((top << 16) | 0xffff)));
-	  operands[1] = operands[0];
-	  operands[2] = GEN_INT (0xffff0000 | bottom);
-	}
-    }
-}");
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(and:SI (match_operand:SI 1 "reg_or_and_operand" "%0,r,0")
-		(match_operand:SI 2 "reg_or_and_operand" "P,LMO,r")))]
-  "register_operand (operands[1], SImode)
-   || register_operand (operands[2], SImode)"
-  "@
-   clrb%k2 %0,%b2
-   ni%z2 %0,%1,%Z2
-   n %0,%2"
-  [(set_attr "length" "2,4,2")])
-
-;; logical OR (IOR)
-(define_expand "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ior:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "reg_or_any_cint_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int top = (unsigned) INTVAL (operands[2]) >> 16;
-      int bottom = INTVAL (operands[2]) & 0xffff;
-
-      if (top != 0 && bottom != 0)
-	{
-	  emit_insn (gen_iorsi3 (operands[0], operands[1],
-				 GEN_INT ((top << 16))));
-	  operands[1] = operands[0];
-	  operands[2] = GEN_INT (bottom);
-	}
-    }
-}");
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(ior:SI (match_operand:SI 1 "reg_or_cint_operand" "%0,r,0")
-		(match_operand:SI 2 "reg_or_cint_operand" "N,LM,r")))]
-  "register_operand (operands[1], SImode)
-   || register_operand (operands[2], SImode)"
-  "@
-   setb%h2 %0,%b2
-   oi%h2 %0,%1,%H2
-   o %0,%2"
-  [(set_attr "length" "2,4,2")])
-
-;; exclusive-or (XOR)
-(define_expand "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(xor:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "reg_or_any_cint_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      int top = (unsigned) INTVAL (operands[2]) >> 16;
-      int bottom = INTVAL (operands[2]) & 0xffff;
-
-      if (top == 0xffff && bottom == 0xffff)
-	{
-	  emit_insn (gen_one_cmplsi2 (operands[0], operands[1]));
-	  DONE;
-	}
-      else if (top != 0 && bottom != 0)
-	{
-	  emit_insn (gen_xorsi3 (operands[0], operands[1],
-				 GEN_INT ((top << 16))));
-	  operands[1] = operands[0];
-	  operands[2] = GEN_INT (bottom);
-	}
-    }
-}");
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(xor:SI (match_operand:SI 1 "reg_or_cint_operand" "%r,0")
-		(match_operand:SI 2 "reg_or_cint_operand" "LM,r")))]
-  "register_operand (operands[1], SImode)
-   || register_operand (operands[2], SImode)"
-  "@
-   xi%h2 %0,%1,%H2
-   x %0,%2"
-  [(set_attr "length" "4,2")])
-
-;; Various shift insns
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
-		     (match_operand:SI 2 "reg_or_cint_operand" "r,n")))]
-  ""
-  "@
-   sar %0,%2
-   sari%s2 %0,%S2"
-  [(set_attr "length" "2")])
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
-		     (match_operand:SI 2 "reg_or_cint_operand" "r,n")))]
-  ""
-  "@
-   sr %0,%2
-   sri%s2 %0,%S2"
-  [(set_attr "length" "2")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "b")
-		   (const_int 1)))]
-  ""
-  "cas %0,%1,%1"
-  [(set_attr "length" "2")
-   (set_attr "type" "address")])
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "0,0")
-		   (match_operand:SI 2 "reg_or_cint_operand" "r,n")))]
-  ""
-  "@
-   sl %0,%2
-   sli%s2 %0,%S2"
-  [(set_attr "length" "2")])
-
-;; Function call insns:
-;;
-;; On the ROMP, &fcn is actually a pointer to the data area, which is passed
-;; to the function in r0.  &.fcn is the actual starting address of the
-;; function.  Also, the word at &fcn contains &.fcn.
-;;
-;; For both functions that do and don't return values, there are two cases:
-;; where the function's address is a constant, and where it isn't.
-;;
-;; Operand 1 (2 for `call_value') is the number of arguments and is not used.
-(define_expand "call"
-  [(use (match_operand:SI 0 "address_operand" ""))
-   (use (match_operand 1 "" ""))]
-  ""
-  "
-{
-  rtx reg0 = gen_rtx (REG, SImode, 0);
-  rtx call_insn;
-
-  if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
-    abort();
-
-  operands[0] = XEXP (operands[0], 0);
-  if (GET_CODE (operands[0]) == SYMBOL_REF)
-    {
-      extern rtx get_symref ();
-      char *real_fcnname =
-		(char *) alloca (strlen (XSTR (operands[0], 0)) + 2);
-
-      /* Copy the data area address to r0.  */
-      emit_move_insn (reg0, force_reg (SImode, operands[0]));
-      strcpy (real_fcnname, \".\");
-      strcat (real_fcnname, XSTR (operands[0], 0));
-      operands[0] = get_symref (real_fcnname);
-    }
-  else
-    {
-      rtx data_access;
-
-      emit_move_insn (reg0, force_reg (SImode, operands[0]));
-      data_access = gen_rtx (MEM, SImode, operands[0]);
-      RTX_UNCHANGING_P (data_access) = 1;
-      operands[0] = copy_to_reg (data_access);
-    }
-
-  call_insn = emit_call_insn (gen_call_internal (operands[0], operands[1]));
-  use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), reg0);
-  DONE;
-}")
-
-(define_insn "call_internal"
-  [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
-	 (match_operand 1 "" "g"))
-   (clobber (reg:SI 15))]
-  ""
-  "balr%# r15,%0"
-  [(set_attr "type" "call")
-   (set_attr "length" "2")])
-
-(define_insn ""
-  [(call (mem:SI (match_operand:SI 0 "romp_symbolic_operand" "i"))
-	 (match_operand 1 "" "g"))
-   (clobber (reg:SI 15))]
-  "GET_CODE (operands[0]) == SYMBOL_REF"
-  "bali%# r15,%0"
-  [(set_attr "type" "call")])
-
-;; Call a function and return a value.
-(define_expand "call_value"
-  [(use (match_operand 0 "" ""))
-   (use (match_operand:SI 1 "address_operand" ""))
-   (use (match_operand 2 "" ""))]
-  ""
-  "
-{
-  rtx reg0 = gen_rtx (REG, SImode, 0);
-  rtx call_insn;
-
-  if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
-    abort();
-
-  operands[1] = XEXP (operands[1], 0);
-  if (GET_CODE (operands[1]) == SYMBOL_REF)
-    {
-      extern rtx get_symref ();
-      char *real_fcnname =
-		(char *) alloca (strlen (XSTR (operands[1], 0)) + 2);
-
-      /* Copy the data area address to r0.  */
-      emit_move_insn (reg0,force_reg (SImode, operands[1]));
-      strcpy (real_fcnname, \".\");
-      strcat (real_fcnname, XSTR (operands[1], 0));
-      operands[1] = get_symref (real_fcnname);
-    }
-  else
-    {
-      rtx data_access;
-
-      emit_move_insn (reg0,force_reg (SImode, operands[1]));
-      data_access = gen_rtx (MEM, SImode, operands[1]);
-      RTX_UNCHANGING_P (data_access) = 1;
-      operands[1] = copy_to_reg (data_access);
-    }
-
-  call_insn = emit_call_insn (gen_call_value_internal (operands[0],
-						       operands[1],
-						       operands[2]));
-  use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), reg0);
-  DONE;
-}")
-
-(define_insn "call_value_internal"
-  [(set (match_operand 0 "" "=fg")
-	(call (mem:SI (match_operand:SI 1 "register_operand" "b"))
-	      (match_operand 2 "" "g")))
-   (clobber (reg:SI 15))]
-  ""
-  "balr%# r15,%1"
-  [(set_attr "length" "2")
-   (set_attr "type" "call")])
-
-(define_insn ""
-  [(set (match_operand 0 "" "=fg")
-	(call (mem:SI (match_operand:SI 1 "romp_symbolic_operand" "i"))
-	      (match_operand 2 "" "g")))
-   (clobber (reg:SI 15))]
-  "GET_CODE (operands[1]) == SYMBOL_REF"
-  "bali%# r15,%1"
-  [(set_attr "type" "call")])
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-;; No operation insn.
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nopr r0"
-  [(set_attr "type" "address")
-   (set_attr "length" "2")
-   (set_attr "cc" "none")])
-
-;; Here are the floating-point operations.
-;;
-;; Start by providing DEFINE_EXPAND for each operation.
-;; The insns will be handled with MATCH_OPERATOR; the methodology will be
-;; discussed below.
-
-;; First the conversion operations.
-
-(define_expand "truncdfsf2"
-  [(parallel [(set (match_operand:SF 0 "general_operand" "")
-		   (float_truncate:SF (match_operand:DF 1 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "extendsfdf2"
-  [(parallel [(set (match_operand:DF 0 "general_operand" "")
-		   (float_extend:DF (match_operand:SF 1 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "floatsisf2"
-  [(parallel [(set (match_operand:SF 0 "general_operand" "")
-		   (float:SF (match_operand:SI 1 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "floatsidf2"
-  [(parallel [(set (match_operand:DF 0 "general_operand" "")
-		   (float:DF (match_operand:SI 1 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "fix_truncsfsi2"
-  [(parallel [(set (match_operand:SI 0 "general_operand" "")
-		   (fix:SI (match_operand:SF 1 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "fix_truncdfsi2"
-  [(parallel [(set (match_operand:SI 0 "general_operand" "")
-		   (fix:SI (match_operand:DF 1 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-;; Now the binary operations.
-
-(define_expand "addsf3"
-  [(parallel [(set (match_operand:SF 0 "general_operand" "")
-		   (plus:SF (match_operand:SF 1 "general_operand" "")
-			    (match_operand:SF 2 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "adddf3"
-  [(parallel [(set (match_operand:DF 0 "general_operand" "")
-		   (plus:DF (match_operand:DF 1 "general_operand" "")
-			    (match_operand:DF 2 "general_operand" "")))
-	       (clobber (reg:SI 0))
-	       (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "subsf3"
-  [(parallel [(set (match_operand:SF 0 "general_operand" "")
-		   (minus:SF (match_operand:SF 1 "general_operand" "")
-			     (match_operand:SF 2 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "subdf3"
-  [(parallel [(set (match_operand:DF 0 "general_operand" "")
-		   (minus:DF (match_operand:DF 1 "general_operand" "")
-			     (match_operand:DF 2 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "mulsf3"
-  [(parallel [(set (match_operand:SF 0 "general_operand" "")
-		   (mult:SF (match_operand:SF 1 "general_operand" "")
-			    (match_operand:SF 2 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "muldf3"
-  [(parallel [(set (match_operand:DF 0 "general_operand" "")
-		   (mult:DF (match_operand:DF 1 "general_operand" "")
-			    (match_operand:DF 2 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "divsf3"
-  [(parallel [(set (match_operand:SF 0 "general_operand" "")
-		   (div:SF (match_operand:SF 1 "general_operand" "")
-			   (match_operand:SF 2 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "divdf3"
-  [(parallel [(set (match_operand:DF 0 "general_operand" "")
-		   (div:DF (match_operand:DF 1 "general_operand" "")
-			   (match_operand:DF 2 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-;; Unary floating-point operations.
-;;
-;; Negations can be done without floating-point, since this is IEEE.
-;; But we cannot do this if an operand is a hard FP register, since
-;; the SUBREG we create would not be valid.
-(define_expand "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(neg:SF (match_operand:SF 1 "register_operand" "")))]
-  ""
-  "
-{
-  if (! (GET_CODE (operands[0]) == REG
-	 && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-	 && FP_REGNO_P (REGNO (operands[0])))
-      && ! (GET_CODE (operands[1]) == REG
-	    && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-	    && FP_REGNO_P (REGNO (operands[1]))))
-    {
-      rtx result;
-      rtx target = operand_subword (operands[0], 0, 1, SFmode);
-
-      result = expand_binop (SImode, xor_optab,
-			     operand_subword_force (operands[1], 0, SFmode),
-			     GEN_INT (0x80000000),
-			     target, 0, OPTAB_WIDEN);
-      if (result == 0)
-	abort ();
-
-      if (result != target)
-	emit_move_insn (result, target);
-
-      /* Make a place for REG_EQUAL.  */
-      emit_move_insn (operands[0], operands[0]);
-      DONE;
-    }
-}")
-
-(define_expand "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(neg:DF (match_operand:DF 1 "register_operand" "")))]
-  ""
-  "
-{
-  if (! (GET_CODE (operands[0]) == REG
-	 && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-	 && FP_REGNO_P (REGNO (operands[0])))
-      && ! (GET_CODE (operands[1]) == REG
-	    && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
-	    && FP_REGNO_P (REGNO (operands[1]))))
-    {
-      rtx result;
-      rtx target = operand_subword (operands[0], 0, 1, DFmode);
-      rtx insns;
-
-      start_sequence ();
-      result = expand_binop (SImode, xor_optab,
-			     operand_subword_force (operands[1], 0, DFmode),
-			     GEN_INT (0x80000000),
-			     target, 0, OPTAB_WIDEN);
-      if (result == 0)
-	abort ();
-
-      if (result != target)
-	emit_move_insn (result, target);
-  
-      emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
-		      operand_subword_force (operands[1], 1, DFmode));
-
-      insns = get_insns ();
-      end_sequence ();
-
-      emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
-      DONE;
-    }
-}")
-
-(define_expand "abssf2"
-  [(parallel [(set (match_operand:SF 0 "general_operand" "")
-		   (abs:SF (match_operand:SF 1 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "absdf2"
-  [(parallel [(set (match_operand:DF 0 "general_operand" "")
-		   (abs:DF (match_operand:DF 1 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-;; Any floating-point operation can be either SFmode or DFmode, and each
-;; operand (including the output) can be either a normal operand or a
-;; conversion from a normal operand.
-;;
-;; We use MATCH_OPERATOR to match a floating-point binary or unary operator
-;; and input and output conversions.  So we need 2^N patterns for each type
-;; of operation, where N is the number of operands, including the output.
-;; There are thus a total of 14 patterns, 8 for binary operations, 4 for
-;; unary operations and two for conversion/move operations (only one
-;; operand can have a conversion for move operations).  In addition, we have
-;; to be careful that a floating-point reload register doesn't get allocated
-;; for an integer.  We take care of this for inputs with PREFERRED_RELOAD_CLASS
-;; but need to have two different constraints for outputs.  This means that
-;; we have to duplicate each pattern where the output could be an integer.
-;; This adds another 7 patterns, for a total of 21.
-
-;; Start with conversion operations (moves are done above).
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operator 1 "float_conversion"
-		[(match_operand 2 "general_operand" "frg")]))
-   (clobber (match_operand:SI 3 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))]
-  ""
-  "*
-{ return output_fpop (SET, operands[0], operands[2], 0, insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_conversion"
-		[(match_operand 2 "general_operand" "frg")]))
-   (clobber (match_operand:SI 3 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))]
-  ""
-  "*
-{ return output_fpop (SET, operands[0], operands[2], 0, insn);
-}"
-  [(set_attr "type" "fp")])
-
-;; Next, binary floating-point operations.
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_binary"
-		[(match_operand 2 "general_operand" "frg")
-		 (match_operand 3 "general_operand" "frg")]))
-   (clobber (match_operand:SI 4 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[1]), operands[2], operands[3])"
-  "*
-{ return output_fpop (GET_CODE (operands[1]), operands[0], 
-		      operands[2], operands[3], insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_binary"
-		[(match_operand 2 "general_operand" "frg")
-		 (match_operator 3 "float_conversion"
-			[(match_operand 4 "general_operand" "frg")])]))
-   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[1]), operands[2], operands[4])"
-  "*
-{ return output_fpop (GET_CODE (operands[1]), operands[0], 
-		      operands[2], operands[4], insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_binary"
-		[(match_operator 2 "float_conversion"
-			[(match_operand 3 "general_operand" "frg")])
-		 (match_operand 4 "general_operand" "frg")]))
-   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[1]), operands[3], operands[4])"
-  "*
-{ return output_fpop (GET_CODE (operands[1]), operands[0], 
-		      operands[3], operands[4], insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_binary"
-		[(match_operator 2 "float_conversion"
-			[(match_operand 3 "general_operand" "frg")])
-		 (match_operator 4 "float_conversion"
-			[(match_operand 5 "general_operand" "frg")])]))
-   (clobber (match_operand:SI 6 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[1]), operands[3], operands[5])"
-  "*
-{ return output_fpop (GET_CODE (operands[1]), operands[0], 
-		      operands[3], operands[5], insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operator 1 "float_conversion"
-		[(match_operator 2 "float_binary"
-			[(match_operand 3 "general_operand" "frg")
-			 (match_operand 4 "general_operand" "frg")])]))
-   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[2]), operands[3], operands[4])"
-  "*
-{ return output_fpop (GET_CODE (operands[2]), operands[0], 
-		      operands[3], operands[4], insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_conversion"
-		[(match_operator 2 "float_binary"
-			[(match_operand 3 "general_operand" "frg")
-			 (match_operand 4 "general_operand" "frg")])]))
-   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[2]), operands[3], operands[4])"
-  "*
-{ return output_fpop (GET_CODE (operands[2]), operands[0], 
-		      operands[3], operands[4], insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operator 1 "float_conversion"
-		[(match_operator 2 "float_binary"
-			[(match_operand 3 "general_operand" "frg")
-			 (match_operator 4 "float_conversion"
-			 	[(match_operand 5 "general_operand" "frg")])])]))
-   (clobber (match_operand:SI 6 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[2]), operands[3], operands[4])"
-  "*
-{ return output_fpop (GET_CODE (operands[2]), operands[0], 
-		      operands[3], operands[5], insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_conversion"
-		[(match_operator 2 "float_binary"
-			[(match_operand 3 "general_operand" "frg")
-			 (match_operator 4 "float_conversion"
-			 	[(match_operand 5 "general_operand" "frg")])])]))
-   (clobber (match_operand:SI 6 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[2]), operands[3], operands[4])"
-  "*
-{ return output_fpop (GET_CODE (operands[2]), operands[0], 
-		      operands[3], operands[5], insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operator 1 "float_conversion"
-		[(match_operator 2 "float_binary"
-			[(match_operator 3 "float_conversion"
-			 	[(match_operand 4 "general_operand" "frg")])
-			 (match_operand 5 "general_operand" "frg")])]))
-   (clobber (match_operand:SI 6 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[2]), operands[4], operands[5])"
-  "*
-{ return output_fpop (GET_CODE (operands[2]), operands[0], 
-		      operands[4], operands[5], insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_conversion"
-		[(match_operator 2 "float_binary"
-			[(match_operator 3 "float_conversion"
-			 	[(match_operand 4 "general_operand" "frg")])
-			 (match_operand 5 "general_operand" "frg")])]))
-   (clobber (match_operand:SI 6 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 7 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[2]), operands[4], operands[5])"
-  "*
-{ return output_fpop (GET_CODE (operands[2]), operands[0], 
-		      operands[4], operands[5], insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operator 1 "float_conversion"
-		[(match_operator 2 "float_binary"
-			[(match_operator 3 "float_conversion"
-			 	[(match_operand 4 "general_operand" "frg")])
-			 (match_operator 5 "float_conversion"
-			 	[(match_operand 6 "general_operand" "frg")])])]))
-   (clobber (match_operand:SI 7 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 8 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[2]), operands[4], operands[6])"
-  "*
-{ return output_fpop (GET_CODE (operands[2]), operands[0], 
-		      operands[4], operands[6], insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_conversion"
-		[(match_operator 2 "float_binary"
-			[(match_operator 3 "float_conversion"
-			 	[(match_operand 4 "general_operand" "frg")])
-			 (match_operator 5 "float_conversion"
-			 	[(match_operand 6 "general_operand" "frg")])])]))
-   (clobber (match_operand:SI 7 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 8 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[2]), operands[4], operands[6])"
-  "*
-{ return output_fpop (GET_CODE (operands[2]), operands[0], 
-		      operands[4], operands[6], insn);
-}"
-  [(set_attr "type" "fp")])
-
-;; Unary floating-point operations.
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_unary"
-		[(match_operand 2 "general_operand" "frg")]))
-   (clobber (match_operand:SI 3 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[1]), operands[2], 0)"
-  "*
-{ return output_fpop (GET_CODE (operands[1]), operands[0], operands[2],
-		      0, insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_unary"
-		[(match_operator 2 "float_conversion"
-			[(match_operand 3 "general_operand" "frg")])]))
-   (clobber (match_operand:SI 4 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[1]), operands[3], 0)"
-  "*
-{ return output_fpop (GET_CODE (operands[1]), operands[0], operands[3],
-		      0, insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operator 1 "float_conversion"
-		[(match_operator 2 "float_unary"
-			[(match_operand 3 "general_operand" "frg")])]))
-   (clobber (match_operand:SI 4 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[2]), operands[3], 0)"
-  "*
-{ return output_fpop (GET_CODE (operands[2]), operands[0], operands[3],
-		      0, insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_conversion"
-		[(match_operator 2 "float_unary"
-			[(match_operand 3 "general_operand" "frg")])]))
-   (clobber (match_operand:SI 4 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[2]), operands[3], 0)"
-  "*
-{ return output_fpop (GET_CODE (operands[2]), operands[0], operands[3],
-		      0, insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operator 1 "float_conversion"
-		[(match_operator 2 "float_unary"
-			[(match_operator 3 "float_conversion"
-			 	[(match_operand 4 "general_operand" "frg")])])]))
-   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[2]), operands[4], 0)"
-  "*
-{ return output_fpop (GET_CODE (operands[2]), operands[0], operands[4],
-		      0, insn);
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand 0 "general_operand" "=frg")
-	(match_operator 1 "float_conversion"
-		[(match_operator 2 "float_unary"
-			[(match_operator 3 "float_conversion"
-			 	[(match_operand 4 "general_operand" "frg")])])]))
-   (clobber (match_operand:SI 5 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 6 "reg_15_operand" "=&t"))]
-  "check_precision (GET_MODE (operands[2]), operands[4], 0)"
-  "*
-{ return output_fpop (GET_CODE (operands[2]), operands[0], operands[4],
-		      0, insn);
-}"
-  [(set_attr "type" "fp")])
-
-;; Compare insns are next.  Note that the ROMP has two types of compares,
-;; signed & unsigned, and one type of branch.  Use the routine
-;; `next_insn_tests_no_unsigned' to see which type to use.
-(define_expand "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "register_operand" "r"))]
-  ""
-  "")
-
-(define_expand "cmpsi"
-  [(set (cc0)
-        (compare (match_operand:SI 0 "register_operand" "")
-  		 (match_operand:SI 1 "reg_or_cint_operand" "")))]
-  ""
-  "")
-
-;; Signed compare, `test' first.
-
-(define_insn ""
-  [(set (cc0)
-	(match_operand:SI 0 "register_operand" "r"))]
-  "next_insn_tests_no_unsigned (insn)"
-  "cis %0,0"
-  [(set_attr "length" "2")
-   (set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (cc0) (match_operand:SI 0 "register_operand" "r,r,r"))
-   (set (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "=0,r,Q")
-	(match_dup 0))]
-  "next_insn_tests_no_unsigned (insn)"
-  "@
-   cis %1,0
-   nilo %1,%0,65535
-   st%M1 %0,%1\;cis %0,0"
-  [(set_attr "type" "compare,compare,store")
-   (set_attr "length" "2,4,6")
-   (set_attr "cc" "compare")])
-
-(define_insn ""
-  [(set (cc0)
-        (compare (match_operand:SI 0 "register_operand" "r,r,r")
-		 (match_operand:SI 1 "reg_or_cint_operand" "I,K,r")))]
-  "next_insn_tests_no_unsigned (insn)"
-  "@
-   cis %0,%1
-   cil %0,%1
-   c %0,%1"
-  [(set_attr "length" "2,4,2")
-   (set_attr "type" "compare")])
-
-;; Unsigned comparisons, `test' first, again.
-(define_insn ""
-  [(set (cc0)
-	(match_operand:SI 0 "register_operand" "r"))]
-  "! next_insn_tests_no_unsigned (insn)"
-  "clil %0,0"
-  [(set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (cc0)
-        (compare (match_operand:SI 0 "register_operand" "r,r")
-		 (match_operand:SI 1 "reg_or_cint_operand" "K,r")))]
-  "! next_insn_tests_no_unsigned (insn)"
-  "@
-   clil %0,%1
-   cl %0,%1"
-  [(set_attr "length" "4,2")
-   (set_attr "type" "compare")])
-
-;; Bit test insn.  Many cases are converted into this by combine.  This
-;; uses the ROMP test bit.
-
-(define_insn ""
-  [(set (cc0)
-	(zero_extract (match_operand:SI 0 "register_operand" "r,r")
-		      (const_int 1)
-		      (match_operand:SI 1 "reg_or_any_cint_operand" "r,n")))]
-  "next_insn_tests_no_inequality (insn)"
-  "@
-   mttb %0,%1
-   mttbi%t1 %0,%S1"
-  [(set_attr "length" "2")
-   (set_attr "type" "compare")
-   (set_attr "cc" "tbit")])
-
-;; Floating-point comparisons.  There are two, equality and order.
-;; The difference will be that a trap for NaN will be given on the orderr
-;; comparisons only.
-
-(define_expand "cmpsf"
-  [(parallel [(set (cc0) (compare (match_operand:SF 0 "general_operand" "")
-				  (match_operand:SF 1 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "cmpdf"
-  [(parallel [(set (cc0) (compare (match_operand:DF 0 "general_operand" "")
-				  (match_operand:DF 1 "general_operand" "")))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "tstsf"
-  [(parallel [(set (cc0) (match_operand:SF 0 "general_operand" ""))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-(define_expand "tstdf"
-  [(parallel [(set (cc0) (match_operand:DF 0 "general_operand" ""))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 15))])]
-  ""
-  "")
-
-;; There are four cases for compare and two for test.  These correspond
-;; to each input having a floating-point conversion or not.
-
-(define_insn ""
-  [(set (cc0) (compare (match_operand 0 "general_operand" "frg")
-		       (match_operand 1 "general_operand" "frg")))
-   (clobber (match_operand:SI 2 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 3 "reg_15_operand" "=&t"))]
-  "GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode"
-  "*
-{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE,
-		      operands[0], operands[1], 0, insn);
-}"
-  [(set_attr "type" "fp")
-   (set_attr "cc" "compare")])
-
-(define_insn ""
-  [(set (cc0) (compare (match_operand 0 "general_operand" "frg")
-		       (match_operator 1 "float_conversion"
-			      [(match_operand 2 "general_operand" "frg")])))
-   (clobber (match_operand:SI 3 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))]
-  ""
-  "*
-{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE,
-		      operands[0], operands[2], 0, insn);
-}"
-  [(set_attr "type" "fp")
-   (set_attr "cc" "compare")])
-
-(define_insn ""
-  [(set (cc0) (compare (match_operator 0 "float_conversion"
-			      [(match_operand 1 "general_operand" "frg")])
-		       (match_operand 2 "general_operand" "frg")))
-   (clobber (match_operand:SI 3 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 4 "reg_15_operand" "=&t"))]
-  ""
-  "*
-{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE,
-		      operands[1], operands[2], 0, insn);
-}"
-  [(set_attr "type" "fp")
-   (set_attr "cc" "compare")])
-
-(define_insn ""
-  [(set (cc0) (compare (match_operator 0 "float_conversion"
-			      [(match_operand 1 "general_operand" "frg")])
-		       (match_operator 2 "float_conversion"
-			      [(match_operand 3 "general_operand" "frg")])))
-   (clobber (match_operand:SI 4 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 5 "reg_15_operand" "=&t"))]
-  ""
-  "*
-{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE,
-		      operands[1], operands[3], 0, insn);
-}"
-  [(set_attr "type" "fp")
-   (set_attr "cc" "compare")])
-
-(define_insn ""
-  [(set (cc0) (match_operand 0 "general_operand" "frg"))
-   (clobber (match_operand:SI 1 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 2 "reg_15_operand" "=&t"))]
-  "GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode"
-  "*
-{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE,
-		      operands[0], CONST0_RTX (GET_MODE (operands[0])),
-		      0, insn);
-}"
-  [(set_attr "type" "fp")
-   (set_attr "cc" "compare")])
-
-(define_insn ""
-  [(set (cc0) (match_operator 0 "float_conversion"
-			[(match_operand 1 "general_operand" "frg")]))
-   (clobber (match_operand:SI 2 "reg_0_operand" "=&z"))
-   (clobber (match_operand:SI 3 "reg_15_operand" "=&t"))]
-  ""
-  "*
-{ return output_fpop (next_insn_tests_no_inequality (insn) ? EQ : GE,
-		      operands[1], CONST0_RTX (GET_MODE (operands[1])),
-		      0, insn);
-}"
-  [(set_attr "type" "fp")
-   (set_attr "cc" "compare")])
-
-;; Branch insns.  Unsigned vs. signed have already
-;; been taken care of.  The only insns that need to be concerned about the
-;; test bit are beq and bne because the rest are either always true,
-;; always false, or converted to EQ or NE.
-
-;; For conditional branches, we use `define_expand' and just have two patterns
-;; that match them.  Operand printing does most of the work.
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-;; Define both directions of branch and return.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  if (restore_compare_p (operands[1]))
-    return 0;
-  else if (get_attr_length (insn) == 2)
-    return \"j%j1 %l0\";
-  else
-    return \"b%j1%# %l0\";
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (return)
-		      (pc)))]
-  "null_epilogue ()"
-  "*
-{
-  if (restore_compare_p (operands[0]))
-    return 0;
-  else
-    return \"b%j0r%# r15\";
-}"
-  [(set_attr "type" "return")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				[(cc0) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  if (restore_compare_p (operands[1]))
-    return 0;
-  else if (get_attr_length (insn) == 2)
-    return \"j%J1 %l0\";
-  else
-    return \"b%J1%# %l0\";
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (pc)
-		      (return)))]
-  "null_epilogue ()"
-  "*
-{
-  if (restore_compare_p (operands[0]))
-    return 0;
-  else
-    return \"b%J0r%# r15\";
-}"
-  [(set_attr "type" "return")])
-
-;; Unconditional branch and return.
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "*
-{
-  if (get_attr_length (insn) == 2)
-    return \"j %l0\";
-  else
-    return \"b%# %l0\";
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn "return"
-  [(return)]
-  "null_epilogue ()"
-  "br%# r15"
-  [(set_attr "type" "return")])
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
-  ""
-  "br%# %0"
-  [(set_attr "type" "ibranch")])
-
-;; Table jump for switch statements:
-(define_insn "tablejump"
-  [(set (pc)
-	(match_operand:SI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "br%# %0"
-  [(set_attr "type" "ibranch")])
diff --git a/gcc/config/romp/x-mach b/gcc/config/romp/x-mach
deleted file mode 100755
index a181e1b..0000000
--- a/gcc/config/romp/x-mach
+++ /dev/null
@@ -1,5 +0,0 @@
-# Ensure that CPATH is used and suppress lots of warnings.
-CC=hc2 -Hcpp -w
-
-# The default `make' on the RT doesn't define MAKE, so do it here.
-MAKE=make
diff --git a/gcc/config/romp/x-romp b/gcc/config/romp/x-romp
deleted file mode 100755
index 82f9e64..0000000
--- a/gcc/config/romp/x-romp
+++ /dev/null
@@ -1,11 +0,0 @@
-# obstack.h assumes that if __STDC__ is defined an ANSI C preprocessor is
-# being used.  -Hnocpp makes hc use its builtin preprocessor instead of
-# /lib/cpp.  gcc doesn't use <sys/ioctl.h>, so it doesn't matter whether
-# fixincludes has been run.
-#
-# hc's warnings do nothing but obscure the output, hence the -w.
-# 
-CC=hc -Hnocpp -w -U__STDC__
-
-# The default `make' on the RT doesn't define MAKE, so do it here.
-MAKE=make
diff --git a/gcc/config/romp/xm-romp.h b/gcc/config/romp/xm-romp.h
deleted file mode 100755
index 37de6de..0000000
--- a/gcc/config/romp/xm-romp.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Configuration for GNU C-compiler for IBM RT PC.
-   Copyright (C) 1989, 1991, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_WORDS_BIG_ENDIAN
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* If compiled with hc, use the built-in alloca and memcpy.
-   These definitions assume hc version 2.  */
-#ifdef __HIGHC__
-#define	alloca _Alloca
-#define bcopy(s,d,l) memcpy(d,s,l)
-#define FUNCTION_CONVERSION_BUG
-#endif
-
-/* We cannot allow cccp.o to contain a copy of BCOPY as this will
-   cause multiple definitions since BLT and BCOPY share an object file
-   in libc.a and the library references BLT.  */
-#define	BSTRING
diff --git a/gcc/config/rs6000/aix31.h b/gcc/config/rs6000/aix31.h
deleted file mode 100755
index 46bd03c..0000000
--- a/gcc/config/rs6000/aix31.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Definitions of target machine for GNU compiler,
-   for IBM RS/6000 running AIX version 3.1.
-   Copyright (C) 1993,1997 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "rs6000/rs6000.h"
-
-/* AIX 3.2 defined _AIX32, but older versions do not.  */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D_IBMR2 -D_AIX -Asystem(unix) -Asystem(aix) -Acpu(rs6000) -Amachine(rs6000)"
-
-/* AIX 3.1 uses bit 15 in CROR as the magic nop.  */
-#undef RS6000_CALL_GLUE
-#define RS6000_CALL_GLUE "cror 15,15,15"
-
-/* AIX 3.1 does not prepend underscores to itrunc, uitrunc, or mcount.  */
-#undef RS6000_ITRUNC
-#define RS6000_ITRUNC "itrunc"
-#undef RS6000_UITRUNC
-#define RS6000_UITRUNC "uitrunc"
-#undef RS6000_MCOUNT
-#define RS6000_MCOUNT ".mcount"
-
diff --git a/gcc/config/rs6000/aix3newas.h b/gcc/config/rs6000/aix3newas.h
deleted file mode 100755
index 9659794..0000000
--- a/gcc/config/rs6000/aix3newas.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Definitions of target machine for GNU compiler,
-   for IBM RS/6000 POWER running AIX version 3.x with the fixed assembler.
-   Copyright (C) 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Jason Merrill (jason@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Enable AIX XL compiler calling convention breakage compatibility.  */
-#define MASK_XL_CALL		0x40000000
-#define	TARGET_XL_CALL		(target_flags & MASK_XL_CALL)
-#undef  SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES		\
-  {"xl-call", 		MASK_XL_CALL},	\
-  {"no-xl-call",	- MASK_XL_CALL},
-
-#include "rs6000/rs6000.h"
-
-/* Tell the assembler to assume that all undefined names are external.  */
-
-#undef ASM_SPEC
-#define ASM_SPEC "-u %(asm_cpu)"
-
-#undef ASM_DEFAULT_SPEC
-#define ASM_DEFAULT_SPEC "-mpwr"
-
-/* Define the options for the binder: Start text at 512, align all segments
-   to 512 bytes, and warn if there is text relocation.
-
-   The -bhalt:4 option supposedly changes the level at which ld will abort,
-   but it also suppresses warnings about multiply defined symbols and is
-   used by the AIX cc command.  So we use it here.
-
-   -bnodelcsect undoes a poor choice of default relating to multiply-defined
-   csects.  See AIX documentation for more information about this.
-
-   -bM:SRE tells the linker that the output file is Shared REusable.  Note
-   that to actually build a shared library you will also need to specify an
-   export list with the -Wl,-bE option.
-
-   If -mcpu=common, export the architecture dependent multiply/divide routines
-   as per README.RS6000.  */
-
-#undef	LINK_SPEC
-#ifndef CROSS_COMPILE
-#define LINK_SPEC "-T512 -H512 %{!r:-btextro} -bhalt:4 -bnodelcsect\
-   %{static:-bnso -bI:/lib/syscalls.exp} \
-   %{mcpu=common: milli.exp%s} \
-   %{!shared:%{g*:-bexport:/usr/lib/libg.exp}} %{shared:-bM:SRE}"
-#else
-#define LINK_SPEC "-T512 -H512 %{!r:-btextro} -bhalt:4 -bnodelcsect\
-   %{static:-bnso} \
-   %{mcpu=common: milli.exp%s} \
-   %{shared:-bM:SRE}"
-#endif
-
-/* These are not necessary when we pass -u to the assembler, and undefining
-   them saves a great deal of space in object files.  */
-
-#undef ASM_OUTPUT_EXTERNAL
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)	\
-{ rtx _symref = XEXP (DECL_RTL (DECL), 0);	\
-  if ((TREE_CODE (DECL) == VAR_DECL		\
-       || TREE_CODE (DECL) == FUNCTION_DECL)	\
-      && (NAME)[strlen (NAME) - 1] != ']')	\
-    {						\
-      char *_name = (char *) permalloc (strlen (XSTR (_symref, 0)) + 5); \
-      strcpy (_name, XSTR (_symref, 0));	\
-      strcat (_name, TREE_CODE (DECL) == FUNCTION_DECL ? "[DS]" : "[RW]"); \
-      XSTR (_symref, 0) = _name;		\
-    }						\
-}
diff --git a/gcc/config/rs6000/aix41.h b/gcc/config/rs6000/aix41.h
deleted file mode 100755
index b35fe93..0000000
--- a/gcc/config/rs6000/aix41.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Definitions of target machine for GNU compiler,
-   for IBM RS/6000 POWER running AIX version 4.1.
-   Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by David Edelsohn (edelsohn@npac.syr.edu).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Enable AIX XL compiler calling convention breakage compatibility.  */
-#define MASK_XL_CALL		0x40000000
-#define	TARGET_XL_CALL		(target_flags & MASK_XL_CALL)
-#undef  SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES		\
-  {"xl-call", 		MASK_XL_CALL},	\
-  {"no-xl-call",	- MASK_XL_CALL}, \
-  {"threads",		0},		\
-  {"pe",		0},
-
-#include "rs6000/rs6000.h"
-
-#undef ASM_SPEC
-#define ASM_SPEC "-u %(asm_cpu)"
-
-/* Common ASM definitions used by ASM_SPEC amonst the various targets
-   for handling -mcpu=xxx switches.  */
-#undef ASM_CPU_SPEC
-#define ASM_CPU_SPEC \
-"%{!mcpu*: \
-  %{mpower: %{!mpower2: -mpwr}} \
-  %{mpower2: -mpwr2} \
-  %{mpowerpc*: -mppc} \
-  %{!mpower*: %{!mpowerpc*: %(asm_default)}}} \
-%{mcpu=common: -mcom} \
-%{mcpu=power: -mpwr} \
-%{mcpu=power2: -mpwr2} \
-%{mcpu=powerpc: -mppc} \
-%{mcpu=rios: -mpwr} \
-%{mcpu=rios1: -mpwr} \
-%{mcpu=rios2: -mpwr2} \
-%{mcpu=rsc: -mpwr} \
-%{mcpu=rsc1: -mpwr} \
-%{mcpu=403: -mppc} \
-%{mcpu=505: -mppc} \
-%{mcpu=601: -m601} \
-%{mcpu=602: -mppc} \
-%{mcpu=603: -m603} \
-%{mcpu=603e: -m603} \
-%{mcpu=604: -m604} \
-%{mcpu=620: -mppc} \
-%{mcpu=821: -mppc} \
-%{mcpu=860: -mppc}"
-
-#undef	ASM_DEFAULT_SPEC
-#define ASM_DEFAULT_SPEC "-mcom"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D_IBMR2 -D_POWER -D_AIX -D_AIX32 -D_AIX41 \
--D_LONG_LONG -Asystem(unix) -Asystem(aix)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{posix: -D_POSIX_SOURCE}\
-   %{mpe: -I/usr/lpp/ppe.poe/include}\
-   %{mthreads: -D_THREAD_SAFE}\
-   %(cpp_cpu)"
-
-/* Common CPP definitions used by CPP_SPEC among the various targets
-   for handling -mcpu=xxx switches.  */
-#undef CPP_CPU_SPEC
-#define CPP_CPU_SPEC \
-"%{!mcpu*: \
-  %{mpower: %{!mpower2: -D_ARCH_PWR}} \
-  %{mpower2: -D_ARCH_PWR2} \
-  %{mpowerpc*: -D_ARCH_PPC} \
-  %{!mpower*: %{!mpowerpc*: %(cpp_default)}}} \
-%{mcpu=common: -D_ARCH_COM} \
-%{mcpu=power: -D_ARCH_PWR} \
-%{mcpu=power2: -D_ARCH_PWR2} \
-%{mcpu=powerpc: -D_ARCH_PPC} \
-%{mcpu=rios: -D_ARCH_PWR} \
-%{mcpu=rios1: -D_ARCH_PWR} \
-%{mcpu=rios2: -D_ARCH_PWR2} \
-%{mcpu=rsc: -D_ARCH_PWR} \
-%{mcpu=rsc1: -D_ARCH_PWR} \
-%{mcpu=403: -D_ARCH_PPC} \
-%{mcpu=505: -D_ARCH_PPC} \
-%{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
-%{mcpu=602: -D_ARCH_PPC} \
-%{mcpu=603: -D_ARCH_PPC} \
-%{mcpu=603e: -D_ARCH_PPC} \
-%{mcpu=604: -D_ARCH_PPC} \
-%{mcpu=620: -D_ARCH_PPC} \
-%{mcpu=821: -D_ARCH_PPC} \
-%{mcpu=860: -D_ARCH_PPC}"
-
-#undef	CPP_DEFAULT_SPEC
-#define CPP_DEFAULT_SPEC "-D_ARCH_COM"
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT MASK_NEW_MNEMONICS
-
-#undef PROCESSOR_DEFAULT
-#define PROCESSOR_DEFAULT PROCESSOR_PPC601
-
-/* Define this macro as a C expression for the initializer of an
-   array of string to tell the driver program which options are
-   defaults for this target and thus do not need to be handled
-   specially when using `MULTILIB_OPTIONS'.
-
-   Do not define this macro if `MULTILIB_OPTIONS' is not defined in
-   the target makefile fragment or if none of the options listed in
-   `MULTILIB_OPTIONS' are set by default.  *Note Target Fragment::.  */
-
-#undef	MULTILIB_DEFAULTS
-#define	MULTILIB_DEFAULTS { "mcpu=common" }
-
-/* These are not necessary when we pass -u to the assembler, and undefining
-   them saves a great deal of space in object files.  */
-
-#undef ASM_OUTPUT_EXTERNAL
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)	\
-{ rtx _symref = XEXP (DECL_RTL (DECL), 0);	\
-  if ((TREE_CODE (DECL) == VAR_DECL		\
-       || TREE_CODE (DECL) == FUNCTION_DECL)	\
-      && (NAME)[strlen (NAME) - 1] != ']')	\
-    {						\
-      char *_name = (char *) permalloc (strlen (XSTR (_symref, 0)) + 5); \
-      strcpy (_name, XSTR (_symref, 0));	\
-      strcat (_name, TREE_CODE (DECL) == FUNCTION_DECL ? "[DS]" : "[RW]"); \
-      XSTR (_symref, 0) = _name;		\
-    }						\
-}
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{pg:-L/lib/profiled -L/usr/lib/profiled}\
-   %{p:-L/lib/profiled -L/usr/lib/profiled} %{!shared:%{g*:-lg}}\
-   %{mpe:-L/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
-   %{mthreads: -L/usr/lib/threads -lpthreads -lc_r /usr/lib/libc.a}\
-   %{!mthreads: -lc}"
-
-#undef LINK_SPEC
-#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro} -bnodelcsect\
-   %{static:-bnso %(link_syscalls) } %{!shared: %{g*: %(link_libg) }}\
-   %{shared:-bM:SRE %{!e:-bnoentry}}"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared:\
-   %{mpe:%{pg:/usr/lpp/ppe.poe/lib/gcrt0.o}\
-         %{!pg:%{p:/usr/lpp/ppe.poe/lib/mcrt0.o}\
-               %{!p:/usr/lpp/ppe.poe/lib/crt0.o}}}\
-   %{!mpe:\
-     %{mthreads:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
-     %{!mthreads:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}"
-
diff --git a/gcc/config/rs6000/aix43.h b/gcc/config/rs6000/aix43.h
deleted file mode 100755
index 124fc17..0000000
--- a/gcc/config/rs6000/aix43.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/* Definitions of target machine for GNU compiler,
-   for IBM RS/6000 POWER running AIX version 4.3.
-   Copyright (C) 1998 Free Software Foundation, Inc.
-   Contributed by David Edelsohn (edelsohn@mhpcc.edu).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Enable AIX XL compiler calling convention breakage compatibility.  */
-#define MASK_XL_CALL		0x40000000
-#define	TARGET_XL_CALL		(target_flags & MASK_XL_CALL)
-#undef  SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES					\
-  {"aix64", 		MASK_64BIT | MASK_POWERPC64 | MASK_POWERPC}, \
-  {"aix32",		- (MASK_64BIT | MASK_POWERPC64)},	\
-  {"xl-call", 		MASK_XL_CALL},				\
-  {"no-xl-call",	- MASK_XL_CALL}, 			\
-  {"threads",		0},					\
-  {"pe",		0},
-
-/* Sometimes certain combinations of command options do not make sense
-   on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
-   get control.  */
-
-#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2 | MASK_STRING)
-#define SUBTARGET_OVERRIDE_OPTIONS					\
-do {									\
-  if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS))		\
-    {									\
-      target_flags &= ~NON_POWERPC_MASKS;				\
-      error ("-maix64 and POWER architecture are incompatible.");	\
-    }									\
-} while (0);
-
-#include "rs6000/rs6000.h"
-
-#undef ASM_SPEC
-#define ASM_SPEC "-u %{maix64:-a64 -mppc64} %(asm_cpu)"
-
-/* Common ASM definitions used by ASM_SPEC amonst the various targets
-   for handling -mcpu=xxx switches.  */
-#undef ASM_CPU_SPEC
-#define ASM_CPU_SPEC \
-"%{!mcpu*: %{!maix64: \
-  %{mpower: %{!mpower2: -mpwr}} \
-  %{mpower2: -mpwr2} \
-  %{mpowerpc*: %{!mpowerpc64: -mppc}} \
-  %{mpowerpc64: -mppc64} \
-  %{!mpower*: %{!mpowerpc*: %(asm_default)}}}} \
-%{mcpu=common: -mcom} \
-%{mcpu=power: -mpwr} \
-%{mcpu=power2: -mpwr2} \
-%{mcpu=powerpc: -mppc} \
-%{mcpu=rios: -mpwr} \
-%{mcpu=rios1: -mpwr} \
-%{mcpu=rios2: -mpwr2} \
-%{mcpu=rsc: -mpwr} \
-%{mcpu=rsc1: -mpwr} \
-%{mcpu=403: -mppc} \
-%{mcpu=505: -mppc} \
-%{mcpu=601: -m601} \
-%{mcpu=602: -mppc} \
-%{mcpu=603: -m603} \
-%{mcpu=603e: -m603} \
-%{mcpu=604: -m604} \
-%{mcpu=620: -mppc} \
-%{mcpu=821: -mppc} \
-%{mcpu=860: -mppc}"
-
-#undef	ASM_DEFAULT_SPEC
-#define ASM_DEFAULT_SPEC "-mcom"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D_IBMR2 -D_POWER -D_AIX -D_AIX32 -D_AIX41 -D_AIX43 \
--D_LONG_LONG -Asystem(unix) -Asystem(aix)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{posix: -D_POSIX_SOURCE}\
-   %{maix64: -D__64BIT__ -D_ARCH_PPC}\
-   %{mpe: -I/usr/lpp/ppe.poe/include}\
-   %{mthreads: -D_THREAD_SAFE}\
-   %(cpp_cpu)"
-
-/* Common CPP definitions used by CPP_SPEC among the various targets
-   for handling -mcpu=xxx switches.  */
-#undef CPP_CPU_SPEC
-#define CPP_CPU_SPEC \
-"%{!mcpu*: %{!maix64: \
-  %{mpower: %{!mpower2: -D_ARCH_PWR}} \
-  %{mpower2: -D_ARCH_PWR2} \
-  %{mpowerpc*: -D_ARCH_PPC} \
-  %{!mpower*: %{!mpowerpc*: %(cpp_default)}}}} \
-%{mcpu=common: -D_ARCH_COM} \
-%{mcpu=power: -D_ARCH_PWR} \
-%{mcpu=power2: -D_ARCH_PWR2} \
-%{mcpu=powerpc: -D_ARCH_PPC} \
-%{mcpu=rios: -D_ARCH_PWR} \
-%{mcpu=rios1: -D_ARCH_PWR} \
-%{mcpu=rios2: -D_ARCH_PWR2} \
-%{mcpu=rsc: -D_ARCH_PWR} \
-%{mcpu=rsc1: -D_ARCH_PWR} \
-%{mcpu=403: -D_ARCH_PPC} \
-%{mcpu=505: -D_ARCH_PPC} \
-%{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
-%{mcpu=602: -D_ARCH_PPC} \
-%{mcpu=603: -D_ARCH_PPC} \
-%{mcpu=603e: -D_ARCH_PPC} \
-%{mcpu=604: -D_ARCH_PPC} \
-%{mcpu=620: -D_ARCH_PPC} \
-%{mcpu=821: -D_ARCH_PPC} \
-%{mcpu=860: -D_ARCH_PPC}"
-
-#undef	CPP_DEFAULT_SPEC
-#define CPP_DEFAULT_SPEC "-D_ARCH_COM"
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT MASK_NEW_MNEMONICS
-
-#undef PROCESSOR_DEFAULT
-#define PROCESSOR_DEFAULT PROCESSOR_PPC604
-
-/* Define this macro as a C expression for the initializer of an
-   array of string to tell the driver program which options are
-   defaults for this target and thus do not need to be handled
-   specially when using `MULTILIB_OPTIONS'.
-
-   Do not define this macro if `MULTILIB_OPTIONS' is not defined in
-   the target makefile fragment or if none of the options listed in
-   `MULTILIB_OPTIONS' are set by default.  *Note Target Fragment::.  */
-
-#undef	MULTILIB_DEFAULTS
-#define	MULTILIB_DEFAULTS { "mcpu=common" }
-
-/* These are not necessary when we pass -u to the assembler, and undefining
-   them saves a great deal of space in object files.  */
-
-#undef ASM_OUTPUT_EXTERNAL
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)	\
-{ rtx _symref = XEXP (DECL_RTL (DECL), 0);	\
-  if ((TREE_CODE (DECL) == VAR_DECL		\
-       || TREE_CODE (DECL) == FUNCTION_DECL)	\
-      && (NAME)[strlen (NAME) - 1] != ']')	\
-    {						\
-      char *_name = (char *) permalloc (strlen (XSTR (_symref, 0)) + 5); \
-      strcpy (_name, XSTR (_symref, 0));	\
-      strcat (_name, TREE_CODE (DECL) == FUNCTION_DECL ? "[DS]" : "[RW]"); \
-      XSTR (_symref, 0) = _name;		\
-    }						\
-}
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{pg:-L/lib/profiled -L/usr/lib/profiled}\
-   %{p:-L/lib/profiled -L/usr/lib/profiled} %{!shared:%{g*:-lg}}\
-   %{mpe:-L/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
-   %{mthreads: -L/usr/lib/threads -lpthreads -lc_r /usr/lib/libc.a}\
-   %{!mthreads: -lc}"
-
-#undef LINK_SPEC
-#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro} -bnodelcsect\
-   %{static:-bnso %(link_syscalls) } %{!shared: %{g*: %(link_libg) }}\
-   %{shared:-bM:SRE %{!e:-bnoentry}} %{maix64:-b64}"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared:\
-   %{mpe:%{pg:/usr/lpp/ppe.poe/lib/gcrt0.o}\
-         %{!pg:%{p:/usr/lpp/ppe.poe/lib/mcrt0.o}\
-               %{!p:/usr/lpp/ppe.poe/lib/crt0.o}}}\
-   %{!mpe:\
-     %{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
-     %{!maix64:\
-       %{mthreads:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
-       %{!mthreads:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}}"
-
-/* AIX 4.3 typedefs ptrdiff_t as "long" while earlier releases used "int".  */
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "long int"
-
diff --git a/gcc/config/rs6000/beos.h b/gcc/config/rs6000/beos.h
deleted file mode 100755
index 851601f..0000000
--- a/gcc/config/rs6000/beos.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/* Definitions of target machine for GNU compiler, for BeOS.
-   Copyright (C) 1997 Free Software Foundation, Inc.
-   Contributed by Fred Fish (fnf@cygnus.com), based on aix41.h
-   from David Edelsohn (edelsohn@npac.syr.edu).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Enable AIX XL compiler calling convention breakage compatibility.  */
-#define MASK_XL_CALL		0x40000000
-#define	TARGET_XL_CALL		(target_flags & MASK_XL_CALL)
-#undef  SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES		\
-  {"xl-call", 		MASK_XL_CALL},	\
-  {"no-xl-call",	- MASK_XL_CALL}, \
-  {"threads",		0},		\
-  {"pe",		0},
-
-#include "rs6000/rs6000.h"
-
-#undef ASM_SPEC
-#define ASM_SPEC "-u %(asm_cpu)"
-
-#undef CPP_PREDEFINES
-/* __POWERPC__ must be defined for some header files */
-#define CPP_PREDEFINES "-D__BEOS__ -D__POWERPC__ -Asystem(beos) -Acpu(powerpc) -Amachine(powerpc)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} %(cpp_cpu)"
-
-#undef	CPP_DEFAULT_SPEC
-#define CPP_DEFAULT_SPEC "-D_ARCH_PPC"
-
-/* This is the easiest way to disable use of gcc's builtin alloca,
-   which in the current BeOS release (DR9) is a problem because of the
-   relatively low default stack size of 256K with no way to expand it.
-   So anything we compile for the BeOS target should not use the
-   builtin alloca.  This also has the unwanted side effect of
-   disabling all builtin functions though. */
-
-#undef CC1_SPEC
-#define CC1_SPEC "%{!fbuiltin: -fno-builtin}"
-#undef CC1PLUS_SPEC
-#define CC1PLUS_SPEC "%{!fbuiltin: -fno-builtin}"
-
-#undef	ASM_DEFAULT_SPEC
-#define ASM_DEFAULT_SPEC "-mppc"
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS)
-
-#undef PROCESSOR_DEFAULT
-#define PROCESSOR_DEFAULT PROCESSOR_PPC603
-
-/* Define this macro as a C expression for the initializer of an
-   array of string to tell the driver program which options are
-   defaults for this target and thus do not need to be handled
-   specially when using `MULTILIB_OPTIONS'.
-
-   Do not define this macro if `MULTILIB_OPTIONS' is not defined in
-   the target makefile fragment or if none of the options listed in
-   `MULTILIB_OPTIONS' are set by default.  *Note Target Fragment::.  */
-
-#undef	MULTILIB_DEFAULTS
-#define	MULTILIB_DEFAULTS { "mcpu=powerpc" }
-
-/* These are not necessary when we pass -u to the assembler, and undefining
-   them saves a great deal of space in object files.  */
-
-#undef ASM_OUTPUT_EXTERNAL
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)	\
-{ rtx _symref = XEXP (DECL_RTL (DECL), 0);	\
-  if ((TREE_CODE (DECL) == VAR_DECL		\
-       || TREE_CODE (DECL) == FUNCTION_DECL)	\
-      && (NAME)[strlen (NAME) - 1] != ']')	\
-    {						\
-      char *_name = (char *) permalloc (strlen (XSTR (_symref, 0)) + 5); \
-      strcpy (_name, XSTR (_symref, 0));	\
-      strcat (_name, TREE_CODE (DECL) == FUNCTION_DECL ? "[DS]" : "[RW]"); \
-      XSTR (_symref, 0) = _name;		\
-    }						\
-}
-
-/* These empty definitions get rid of the attempt to link in crt0.o
-   and any libraries like libc.a.
-   On BeOS the ld executable is actually a linker front end that first runs
-   the GNU linker with the -r option to generate a relocatable XCOFF output
-   file, and then runs Metrowork's linker (mwld) to generate a fully linked
-   executable. */
-
-#undef LIB_SPEC
-#define LIB_SPEC ""
-
-#undef LINK_SPEC
-#define LINK_SPEC ""
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-
-/* Text to write out after a CALL that may be replaced by glue code by
-   the loader. */
-
-#undef RS6000_CALL_GLUE
-#define RS6000_CALL_GLUE "cror 15,15,15"
-
-/* Struct alignments are done on 4 byte boundaries for all types. */
-#undef BIGGEST_FIELD_ALIGNMENT
-#define BIGGEST_FIELD_ALIGNMENT 32
diff --git a/gcc/config/rs6000/cygwin.h b/gcc/config/rs6000/cygwin.h
deleted file mode 100755
index 0ed448b..0000000
--- a/gcc/config/rs6000/cygwin.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Operating system specific defines to be used when targeting GCC for
-   hosting on Windows NT 3.x, using the Cygnus API 
-
-   This is different to the winnt.h file, since that is used
-   to build GCC for use with a windows style library and tool
-   set, winnt.h uses the Microsoft tools to do that.
-
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-
-/* Ugly hack */
-#include "rs6000/win-nt.h"
-
-
-#ifdef CPP_PREDEFINES
-#undef CPP_PREDEFINES
-#endif
-
-#define	CPP_PREDEFINES "-D_WIN32 -DWINNT -D__CYGWIN__ -D__CYGWIN32__ -DPOSIX \
-  -D_POWER -D_ARCH_PPC -D__PPC__ -Asystem(winnt) -Acpu(powerpc) -Amachine(powerpc)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "-remap %{posix: -D_POSIX_SOURCE} %(cpp_cpu)"
-
-/* We have to dynamic link to get to the system DLLs.  All of libc, libm and
-   the Unix stuff is in cygwin.dll.  The import library is called
-   'libcygwin.a'.  For Windows applications, include more libraries, but
-   always include kernel32.  We'd like to specific subsystem windows to
-   ld, but that doesn't work just yet.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC "-lcygwin %{mwindows:-luser32 -lgdi32 -lcomdlg32} -lkernel32"
-
-#undef	LINK_SPEC
-#define	LINK_SPEC "%{v:-V}"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "crti%O%s crt0%O%s"
-
-#undef	ENDFILE_SPEC
-#define	ENDFILE_SPEC "crtn%O%s"
-
-#define PTRDIFF_TYPE "int"
-#define WCHAR_UNSIGNED 1
-#define WCHAR_TYPE_SIZE 16
-#define WCHAR_TYPE "short unsigned int"
-
-#define DBX_DEBUGGING_INFO 
-#undef SDB_DEBUGGING_INFO 
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
diff --git a/gcc/config/rs6000/eabi-ci.asm b/gcc/config/rs6000/eabi-ci.asm
deleted file mode 100755
index da3914c..0000000
--- a/gcc/config/rs6000/eabi-ci.asm
+++ /dev/null
@@ -1,131 +0,0 @@
-# crti.s for eabi
-
-#   Copyright (C) 1996 Free Software Foundation, Inc.
-#   Written By Michael Meissner
-# 
-# This file is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License as published by the
-# Free Software Foundation; either version 2, or (at your option) any
-# later version.
-# 
-# In addition to the permissions in the GNU General Public License, the
-# Free Software Foundation gives you unlimited permission to link the
-# compiled version of this file with other programs, and to distribute
-# those programs without any restriction coming from the use of this
-# file.  (The General Public License restrictions do apply in other
-# respects; for example, they cover modification of the file, and
-# distribution when not linked into another program.)
-# 
-# This file is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-# General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with this program; see the file COPYING.  If not, write to
-# the Free Software Foundation, 59 Temple Place - Suite 330,
-# Boston, MA 02111-1307, USA.
-# 
-#    As a special exception, if you link this library with files
-#    compiled with GCC to produce an executable, this does not cause
-#    the resulting executable to be covered by the GNU General Public License.
-#    This exception does not however invalidate any other reasons why
-#    the executable file might be covered by the GNU General Public License.
-# 
-
-# This file just supplies labeled starting points for the .got* and other
-# special sections.  It is linked in first before other modules.
- 
-	.file	"crti.s"
-	.ident	"GNU C crti.s"
-
-#include <ppc-asm.h>
-
-	.section ".got","aw"
-	.globl	__GOT_START__
-	.type	__GOT_START__,@object
-__GOT_START__:
-
-	.section ".got1","aw"
-	.globl	__GOT1_START__
-	.type	__GOT1_START__,@object
-__GOT1_START__:
-
-	.section ".got2","aw"
-	.globl	__GOT2_START__
-	.type	__GOT2_START__,@object
-__GOT2_START__:
-
-	.section ".fixup","aw"
-	.globl	__FIXUP_START__
-	.type	__FIXUP_START__,@object
-__FIXUP_START__:
-
-	.section ".ctors","aw"
-	.globl	__CTOR_LIST__
-	.type	__CTOR_LIST__,@object
-__CTOR_LIST__:
-
-# CYGNUS LOCAL vmakarov
-	.globl	___CTOR_LIST__	#  add support for -fleading-underscore
-	.type	___CTOR_LIST__,@object
-___CTOR_LIST__:
-# END CYGNUS LOCAL
-
-	.section ".dtors","aw"
-	.globl	__DTOR_LIST__
-	.type	__DTOR_LIST__,@object
-__DTOR_LIST__:
-
-# CYGNUS LOCAL vmakarov
-	.globl	___DTOR_LIST__
-	.type	___DTOR_LIST__,@object
-___DTOR_LIST__:
-# END CYGNUS LOCAL
-
-	.section ".sdata","aw"
-	.globl	__SDATA_START__
-	.type	__SDATA_START__,@object
-	.weak	_SDA_BASE_
-	.type	_SDA_BASE_,@object
-__SDATA_START__:
-_SDA_BASE_:
-
-	.section ".sbss","aw",@nobits
-	.globl	__SBSS_START__
-	.type	__SBSS_START__,@object
-__SBSS_START__:
-
-	.section ".sdata2","a"
-	.weak	_SDA2_BASE_
-	.type	_SDA2_BASE_,@object
-	.globl	__SDATA2_START__
-	.type	__SDATA2_START__,@object
-__SDATA2_START__:
-_SDA2_BASE_:
-
-	.section ".sbss2","a"
-	.globl	__SBSS2_START__
-	.type	__SBSS2_START__,@object
-__SBSS2_START__:
-
-	.section ".gcc_except_table","aw"
-	.globl	__EXCEPT_START__
-	.type	__EXCEPT_START__,@object
-__EXCEPT_START__:
-
-# Head of __init function used for static constructors in Solaris
-	.section ".init","ax"
-	.align 2
-FUNC_START(__init)
-	stwu 1,-8(1)
-	mflr 0
-	stw 0,12(1)
-
-# Head of __fini function used for static destructors in Solaris
-	.section ".fini","ax"
-	.align 2
-FUNC_START(__fini)
-	stwu 1,-8(1)
-	mflr 0
-	stw 0,12(1)
diff --git a/gcc/config/rs6000/eabi-cn.asm b/gcc/config/rs6000/eabi-cn.asm
deleted file mode 100755
index 9456762..0000000
--- a/gcc/config/rs6000/eabi-cn.asm
+++ /dev/null
@@ -1,121 +0,0 @@
-# crtn.s for eabi
-
-#   Copyright (C) 1996 Free Software Foundation, Inc.
-#   Written By Michael Meissner
-# 
-# This file is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License as published by the
-# Free Software Foundation; either version 2, or (at your option) any
-# later version.
-# 
-# In addition to the permissions in the GNU General Public License, the
-# Free Software Foundation gives you unlimited permission to link the
-# compiled version of this file with other programs, and to distribute
-# those programs without any restriction coming from the use of this
-# file.  (The General Public License restrictions do apply in other
-# respects; for example, they cover modification of the file, and
-# distribution when not linked into another program.)
-# 
-# This file is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-# General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with this program; see the file COPYING.  If not, write to
-# the Free Software Foundation, 59 Temple Place - Suite 330,
-# Boston, MA 02111-1307, USA.
-# 
-#    As a special exception, if you link this library with files
-#    compiled with GCC to produce an executable, this does not cause
-#    the resulting executable to be covered by the GNU General Public License.
-#    This exception does not however invalidate any other reasons why
-#    the executable file might be covered by the GNU General Public License.
-# 
-
-# This file just supplies labeled ending points for the .got* and other
-# special sections.  It is linked in last after other modules.
- 
-	.file	"crtn.s"
-	.ident	"GNU C crtn.s"
-
-	.section ".got","aw"
-	.globl	__GOT_END__
-	.type	__GOT_END__,@object
-__GOT_END__:
-
-	.section ".got1","aw"
-	.globl	__GOT1_END__
-	.type	__GOT1_END__,@object
-__GOT1_END__:
-
-	.section ".got2","aw"
-	.globl	__GOT2_END__
-	.type	__GOT2_END__,@object
-__GOT2_END__:
-
-	.section ".fixup","aw"
-	.globl	__FIXUP_END__
-	.type	__FIXUP_END__,@object
-__FIXUP_END__:
-
-	.section ".ctors","aw"
-	.globl	__CTOR_END__
-	.type	__CTOR_END__,@object
-__CTOR_END__:
-
-# CYGNUS LOCAL vmakarov
-	.globl	___CTOR_END__	# add support for -fleading-underscore
-	.type	___CTOR_END__,@object
-___CTOR_END__:
-# END CYGNUS LOCAL
-
-	.section ".dtors","aw"
-	.globl	__DTOR_END__
-	.type	__DTOR_END__,@object
-__DTOR_END__:
-
-# CYGNUS LOCAL vmakarov
-	.globl	___DTOR_END__
-	.type	___DTOR_END__,@object
-___DTOR_END__:
-# END CYGNUS LOCAL
-
-	.section ".sdata","aw"
-	.globl	__SDATA_END__
-	.type	__SDATA_END__,@object
-__SDATA_END__:
-
-	.section ".sbss","aw",@nobits
-	.globl	__SBSS_END__
-	.type	__SBSS_END__,@object
-__SBSS_END__:
-
-	.section ".sdata2","a"
-	.globl	__SDATA2_END__
-	.type	__SDATA2_END__,@object
-__SDATA2_END__:
-
-	.section ".sbss2","a"
-	.globl	__SBSS2_END__
-	.type	__SBSS2_END__,@object
-__SBSS2_END__:
-
-	.section ".gcc_except_table","aw"
-	.globl	__EXCEPT_END__
-	.type	__EXCEPT_END__,@object
-__EXCEPT_END__:
-
-# Tail of __init used for static constructors in Solaris
-	.section ".init","ax"
-	lwz 0,12(1)
-	mtlr 0
-	addi 1,1,8
-	blr
-
-# Tail of __fini used for static destructors in Solaris
-	.section ".fini","ax"
-	lwz 0,12(1)
-	mtlr 0
-	addi 1,1,8
-	blr
diff --git a/gcc/config/rs6000/eabi-ctors.c b/gcc/config/rs6000/eabi-ctors.c
deleted file mode 100755
index ebc23de..0000000
--- a/gcc/config/rs6000/eabi-ctors.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Stripped down support to run global constructors and destructors on
-   embedded PowerPC systems.
-
-   Copyright (C) 1995 Free Software Foundation, Inc.
-   Contributed by Michael Meissner  (meissner@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with other files,
-   some of which are compiled with GCC, to produce an executable,
-   this library does not by itself cause the resulting executable
-   to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-
-/*  Declare a pointer to void function type.  */
-
-typedef void (*func_ptr) (void);
-
-/* Declare the set of symbols use as begin and end markers for the lists
-   of global object constructors and global object destructors.  */
-
-extern func_ptr __CTOR_LIST__[];
-extern func_ptr __CTOR_END__ [];
-extern func_ptr __DTOR_LIST__[];
-extern func_ptr __DTOR_END__ [];
-
-extern void __do_global_ctors (void);
-extern void __do_global_dtors (void);
-
-extern void __init (), __fini ();
-
-/* The Solaris linker seems to incorrectly relocate PC relative relocations
-   to a different section (ie, calls to __init, __fini), so avoid it by
-   using a function pointer.  */
-static void (*init_ptr) (void) = __init;
-static void (*fini_ptr) (void) = __fini;
-
-void (*__atexit)(func_ptr);
-
-/* Call all global constructors */
-void
-__do_global_ctors (void)
-{
-  func_ptr *ptr = &__CTOR_LIST__[0];
-  func_ptr *end = &__CTOR_END__[0];
-
-  if (__atexit)
-    __atexit (__do_global_dtors);
-
-  /* Call the constructors collected in the .ctors section.  */
-  for ( ; ptr != end; ptr++)
-    if (*ptr)
-      (*ptr)();
-
-  /* Call the initialization function in the .init section.  */
-  (*init_ptr) ();
-}
-
-/* Call all global destructors */
-void
-__do_global_dtors (void)
-{
-  func_ptr *ptr   = &__DTOR_END__[0] - 1;
-  func_ptr *start = &__DTOR_LIST__[0];
-
-  /* Call the termination function in the .fini section.  */
-  (*fini_ptr) ();
-
-  /* Call the  destructors collected in the .dtors section.  Run
-     the destructors in reverse order.  */
-  for ( ; ptr >= start; ptr--)
-    if (*ptr)
-      (*ptr)();
-}
-
diff --git a/gcc/config/rs6000/eabi.asm b/gcc/config/rs6000/eabi.asm
deleted file mode 100755
index 803105f..0000000
--- a/gcc/config/rs6000/eabi.asm
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- * special support for eabi
- *
- *   Copyright (C) 1995, 1996, 1998 Free Software Foundation, Inc.
- *   Written By Michael Meissner
- * 
- * This file is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- * 
- * In addition to the permissions in the GNU General Public License, the
- * Free Software Foundation gives you unlimited permission to link the
- * compiled version of this file with other programs, and to distribute
- * those programs without any restriction coming from the use of this
- * file.  (The General Public License restrictions do apply in other
- * respects; for example, they cover modification of the file, and
- * distribution when not linked into another program.)
- * 
- * This file is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, 59 Temple Place - Suite 330,
- * Boston, MA 02111-1307, USA.
- * 
- *    As a special exception, if you link this library with files
- *    compiled with GCC to produce an executable, this does not cause
- *    the resulting executable to be covered by the GNU General Public License.
- *    This exception does not however invalidate any other reasons why
- *    the executable file might be covered by the GNU General Public License.
- */ 
-
-/* Do any initializations needed for the eabi environment */
-
-	.file	"eabi.asm"
-	.section ".text"
-	#include "ppc-asm.h"
-
-	 .section ".got2","aw"
-	.align	2
-.LCTOC1 = . /* +32768 */
-
-/* Table of addresses */
-.Ltable = .-.LCTOC1
-	.long	.LCTOC1				/* address we are really at */
-
-.Lsda = .-.LCTOC1
-	.long	_SDA_BASE_			/* address of the first small data area */
-
-.Lsdas = .-.LCTOC1
-	.long	__SDATA_START__			/* start of .sdata/.sbss section */
-
-.Lsdae = .-.LCTOC1
-	.long	__SBSS_END__			/* end of .sdata/.sbss section */
-
-.Lsda2 = .-.LCTOC1
-	.long	_SDA2_BASE_			/* address of the second small data area */
-
-.Lsda2s = .-.LCTOC1
-	.long	__SDATA2_START__		/* start of .sdata2/.sbss2 section */
-
-.Lsda2e = .-.LCTOC1
-	.long	__SBSS2_END__			/* end of .sdata2/.sbss2 section */
-
-#ifdef _RELOCATABLE
-.Lgots = .-.LCTOC1
-	.long	__GOT_START__			/* Global offset table start */
-
-.Lgotm1 = .-.LCTOC1
-	.long	_GLOBAL_OFFSET_TABLE_-4		/* end of GOT ptrs before BLCL + 3 reserved words */
-
-.Lgotm2 = .-.LCTOC1
-	.long	_GLOBAL_OFFSET_TABLE_+12	/* start of GOT ptrs after BLCL + 3 reserved words */
-
-.Lgote = .-.LCTOC1
-	.long	__GOT_END__			/* Global offset table end */
-
-.Lgot2s = .-.LCTOC1
-	.long	__GOT2_START__			/* -mrelocatable GOT pointers start */
-
-.Lgot2e = .-.LCTOC1
-	.long	__GOT2_END__			/* -mrelocatable GOT pointers end */
-
-.Lfixups = .-.LCTOC1
-	.long	__FIXUP_START__			/* start of .fixup section */
-
-.Lfixupe = .-.LCTOC1
-	.long	__FIXUP_END__			/* end of .fixup section */
-
-.Lctors = .-.LCTOC1
-	.long	__CTOR_LIST__			/* start of .ctor section */
-
-.Lctore = .-.LCTOC1
-	.long	__CTOR_END__			/* end of .ctor section */
-
-.Ldtors = .-.LCTOC1
-	.long	__DTOR_LIST__			/* start of .dtor section */
-
-.Ldtore = .-.LCTOC1
-	.long	__DTOR_END__			/* end of .dtor section */
-
-.Lexcepts = .-.LCTOC1
-	.long	__EXCEPT_START__		/* start of .gcc_except_table section */
-
-.Lexcepte = .-.LCTOC1
-	.long	__EXCEPT_END__			/* end of .gcc_except_table section */
-
-.Linit = .-.LCTOC1
-	.long	.Linit_p			/* address of variable to say we've been called */
-
-	.text
-	.align	2
-.Lptr:
-	.long	.LCTOC1-.Laddr			/* PC relative pointer to .got2 */
-#endif
-
-	.data
-	.align	2
-.Linit_p:
-	.long	0
-
-	.text
-
-/* CYGNUS LOCAL vmakarov */
-#if 0
-/* END CYGNUS LOCAL */
-FUNC_START(__eabi)
-/* CYGNUS LOCAL vmakarov */
-#endif
-	/* Don't use FUNC_NAME here, this name doesn't depend on
-	   -fleading-underscore.  */
-	.globl	__eabi
-	.type	__eabi@function
-__eabi:
-/* END CYGNUS LOCAL */
-
-/* Eliminate -mrelocatable code if not -mrelocatable, so that this file can
-   be assembled with other assemblers than GAS, such as the Solaris PowerPC
-   assembler.  */
-
-#ifndef _RELOCATABLE
-	addis	10,0,.Linit_p@ha		/* init flag */
-	addis	11,0,.LCTOC1@ha			/* load address of .LCTOC1 */
-	lwz	9,.Linit_p@l(10)		/* init flag */
-	addi	11,11,.LCTOC1@l
-	cmplwi	2,9,0				/* init flag != 0? */
-	bnelr	2				/* return now, if we've been called already */
-	stw	1,.Linit_p@l(10)		/* store a non-zero value in the done flag */
-
-#else /* -mrelocatable */
-	mflr	0
-	bl	.Laddr				/* get current address */
-.Laddr:
-	mflr	12				/* real address of .Laddr */
-	lwz	11,(.Lptr-.Laddr)(12)		/* linker generated address of .LCTOC1 */
-	add	11,11,12			/* correct to real pointer */
-	lwz	12,.Ltable(11)			/* get linker's idea of where .Laddr is */
-	lwz	10,.Linit(11)			/* address of init flag */
-	subf.	12,12,11			/* calculate difference */
-	lwzx	9,10,12				/* done flag */
-	cmplwi	2,9,0				/* init flag != 0? */
-	mtlr	0				/* restore in case branch was taken */
-	bnelr	2				/* return now, if we've been called already */
-	stwx	1,10,12				/* store a non-zero value in the done flag */
-	beq+	0,.Lsdata			/* skip if we don't need to relocate */
-
-/* We need to relocate the .got2 pointers. */
-
-	lwz	3,.Lgot2s(11)			/* GOT2 pointers start */
-	lwz	4,.Lgot2e(11)			/* GOT2 pointers end */
-	add	3,12,3				/* adjust pointers */
-	add	4,12,4
-	bl	FUNC_NAME(__eabi_convert)	/* convert pointers in .got2 section */
-
-/* Fixup the .ctor section for static constructors */
-
-	lwz	3,.Lctors(11)			/* constructors pointers start */
-	lwz	4,.Lctore(11)			/* constructors pointers end */
-	bl	FUNC_NAME(__eabi_convert)	/* convert constructors */
-
-/* Fixup the .dtor section for static destructors */
-
-	lwz	3,.Ldtors(11)			/* destructors pointers start */
-	lwz	4,.Ldtore(11)			/* destructors pointers end */
-	bl	FUNC_NAME(__eabi_convert)	/* convert destructors */
-
-/* Fixup the .gcc_except_table section for G++ exceptions */
-
-	lwz	3,.Lexcepts(11)			/* exception table pointers start */
-	lwz	4,.Lexcepte(11)			/* exception table pointers end */
-	bl	FUNC_NAME(__eabi_convert)	/* convert exceptions */
-
-/* Fixup the addresses in the GOT below _GLOBAL_OFFSET_TABLE_-4 */
-
-	lwz	3,.Lgots(11)			/* GOT table pointers start */
-	lwz	4,.Lgotm1(11)			/* GOT table pointers below _GLOBAL_OFFSET_TABLE-4 */
-	bl	FUNC_NAME(__eabi_convert)	/* convert lower GOT */
-
-/* Fixup the addresses in the GOT above _GLOBAL_OFFSET_TABLE_+12 */
-
-	lwz	3,.Lgotm2(11)			/* GOT table pointers above _GLOBAL_OFFSET_TABLE+12 */
-	lwz	4,.Lgote(11)			/* GOT table pointers end */
-	bl	FUNC_NAME(__eabi_convert)	/* convert lower GOT */
-
-/* Fixup any user initialized pointers now (the compiler drops pointers to */
-/* each of the relocs that it does in the .fixup section).  */
-
-.Lfix:
-	lwz	3,.Lfixups(11)			/* fixup pointers start */
-	lwz	4,.Lfixupe(11)			/* fixup pointers end */
-	bl	FUNC_NAME(__eabi_uconvert)	/* convert user initialized pointers */
-
-.Lsdata:
-	mtlr	0				/* restore link register */
-#endif /* _RELOCATABLE */
-
-/* Only load up register 13 if there is a .sdata and/or .sbss section */
-	lwz	3,.Lsdas(11)			/* start of .sdata/.sbss section */
-	lwz	4,.Lsdae(11)			/* end of .sdata/.sbss section */
-	cmpw	1,3,4				/* .sdata/.sbss section non-empty? */
-	beq-	1,.Lsda2l			/* skip loading r13 */
-
-	lwz	13,.Lsda(11)			/* load r13 with _SDA_BASE_ address */
-
-/* Only load up register 2 if there is a .sdata2 and/or .sbss2 section */
-
-.Lsda2l:	
-	lwz	3,.Lsda2s(11)			/* start of .sdata/.sbss section */
-	lwz	4,.Lsda2e(11)			/* end of .sdata/.sbss section */
-	cmpw	1,3,4				/* .sdata/.sbss section non-empty? */
-	beq+	1,.Ldone			/* skip loading r2 */
-
-	lwz	2,.Lsda2(11)			/* load r2 with _SDA2_BASE_ address */
-
-/* Done adjusting pointers, return by way of doing the C++ global constructors.  */
-
-.Ldone:
-	b	FUNC_NAME(__do_global_ctors)	/* do any C++ global constructors (which returns to caller) */
-/* CYGNUS LOCAL vmakarov */
-#if 0
-/* END CYGNUS LOCAL */
-FUNC_END(__eabi)
-/* CYGNUS LOCAL vmakarov */
-#endif
-.L.end:
-	.size	__eabi,.L.end-__eabi
-/* END CYGNUS LOCAL */
-
-/* Special subroutine to convert a bunch of pointers directly.
-   r0		has original link register
-   r3		has low pointer to convert
-   r4		has high pointer to convert
-   r5 .. r10	are scratch registers
-   r11		has the address of .LCTOC1 in it.
-   r12		has the value to add to each pointer
-   r13 .. r31	are unchanged */
-	
-FUNC_START(__eabi_convert)
-        cmplw	1,3,4				/* any pointers to convert? */
-        subf	5,3,4				/* calculate number of words to convert */
-        bclr	4,4				/* return if no pointers */
-
-        srawi	5,5,2
-	addi	3,3,-4				/* start-4 for use with lwzu */
-        mtctr	5
-
-.Lcvt:
-	lwzu	6,4(3)				/* pointer to convert */
-	cmpi	0,6,0
-	beq-	.Lcvt2				/* if pointer is null, don't convert */
-
-        add	6,6,12				/* convert pointer */
-        stw	6,0(3)
-.Lcvt2:
-        bdnz+	.Lcvt
-        blr
-
-FUNC_END(__eabi_convert)
-
-/* Special subroutine to convert the pointers the user has initialized.  The
-   compiler has placed the address of the initialized pointer into the .fixup
-   section.
-
-   r0		has original link register
-   r3		has low pointer to convert
-   r4		has high pointer to convert
-   r5 .. r10	are scratch registers
-   r11		has the address of .LCTOC1 in it.
-   r12		has the value to add to each pointer
-   r13 .. r31	are unchanged */
-	
-FUNC_START(__eabi_uconvert)
-        cmplw	1,3,4				/* any pointers to convert? */
-        subf	5,3,4				/* calculate number of words to convert */
-        bclr	4,4				/* return if no pointers */
-
-        srawi	5,5,2
-	addi	3,3,-4				/* start-4 for use with lwzu */
-        mtctr	5
-
-.Lucvt:
-	lwzu	6,4(3)				/* next pointer to pointer to convert */
-	add	6,6,12				/* adjust pointer */
-	lwz	7,0(6)				/* get the pointer it points to */
-	stw	6,0(3)				/* store adjusted pointer */
-	add	7,7,12				/* adjust */
-	stw	7,0(6)
-        bdnz+	.Lucvt
-        blr
-
-FUNC_END(__eabi_uconvert)
-
-/* Routines for saving floating point registers, called by the compiler. */
-/* Called with r11 pointing to the stack header word of the caller of the */
-/* function, just beyond the end of the floating point save area. */
-
-FUNC_START(_savefpr_14)	stfd	14,-144(11)	/* save fp registers */
-FUNC_START(_savefpr_15)	stfd	15,-136(11)
-FUNC_START(_savefpr_16)	stfd	16,-128(11)
-FUNC_START(_savefpr_17)	stfd	17,-120(11)
-FUNC_START(_savefpr_18)	stfd	18,-112(11)
-FUNC_START(_savefpr_19)	stfd	19,-104(11)
-FUNC_START(_savefpr_20)	stfd	20,-96(11)
-FUNC_START(_savefpr_21)	stfd	21,-88(11)
-FUNC_START(_savefpr_22)	stfd	22,-80(11)
-FUNC_START(_savefpr_23)	stfd	23,-72(11)
-FUNC_START(_savefpr_24)	stfd	24,-64(11)
-FUNC_START(_savefpr_25)	stfd	25,-56(11)
-FUNC_START(_savefpr_26)	stfd	26,-48(11)
-FUNC_START(_savefpr_27)	stfd	27,-40(11)
-FUNC_START(_savefpr_28)	stfd	28,-32(11)
-FUNC_START(_savefpr_29)	stfd	29,-24(11)
-FUNC_START(_savefpr_30)	stfd	30,-16(11)
-FUNC_START(_savefpr_31)	stfd	31,-8(11)
-			blr
-FUNC_END(_savefpr_31)
-FUNC_END(_savefpr_30)
-FUNC_END(_savefpr_29)
-FUNC_END(_savefpr_28)
-FUNC_END(_savefpr_27)
-FUNC_END(_savefpr_26)
-FUNC_END(_savefpr_25)
-FUNC_END(_savefpr_24)
-FUNC_END(_savefpr_23)
-FUNC_END(_savefpr_22)
-FUNC_END(_savefpr_21)
-FUNC_END(_savefpr_20)
-FUNC_END(_savefpr_19)
-FUNC_END(_savefpr_18)
-FUNC_END(_savefpr_17)
-FUNC_END(_savefpr_16)
-FUNC_END(_savefpr_15)
-FUNC_END(_savefpr_14)
-
-/* Routines for saving integer registers, called by the compiler. */
-/* Called with r11 pointing to the stack header word of the caller of the */
-/* function, just beyond the end of the integer save area. */
-
-FUNC_START(_savegpr_14)	stw	14,-72(11)	/* save gp registers */
-FUNC_START(_savegpr_15)	stw	15,-68(11)
-FUNC_START(_savegpr_16)	stw	16,-64(11)
-FUNC_START(_savegpr_17)	stw	17,-60(11)
-FUNC_START(_savegpr_18)	stw	18,-56(11)
-FUNC_START(_savegpr_19)	stw	19,-52(11)
-FUNC_START(_savegpr_20)	stw	20,-48(11)
-FUNC_START(_savegpr_21)	stw	21,-44(11)
-FUNC_START(_savegpr_22)	stw	22,-40(11)
-FUNC_START(_savegpr_23)	stw	23,-36(11)
-FUNC_START(_savegpr_24)	stw	24,-32(11)
-FUNC_START(_savegpr_25)	stw	25,-28(11)
-FUNC_START(_savegpr_26)	stw	26,-24(11)
-FUNC_START(_savegpr_27)	stw	27,-20(11)
-FUNC_START(_savegpr_28)	stw	28,-16(11)
-FUNC_START(_savegpr_29)	stw	29,-12(11)
-FUNC_START(_savegpr_30)	stw	30,-8(11)
-FUNC_START(_savegpr_31)	stw	31,-4(11)
-			blr
-FUNC_END(_savegpr_31)
-FUNC_END(_savegpr_30)
-FUNC_END(_savegpr_29)
-FUNC_END(_savegpr_28)
-FUNC_END(_savegpr_27)
-FUNC_END(_savegpr_26)
-FUNC_END(_savegpr_25)
-FUNC_END(_savegpr_24)
-FUNC_END(_savegpr_23)
-FUNC_END(_savegpr_22)
-FUNC_END(_savegpr_21)
-FUNC_END(_savegpr_20)
-FUNC_END(_savegpr_19)
-FUNC_END(_savegpr_18)
-FUNC_END(_savegpr_17)
-FUNC_END(_savegpr_16)
-FUNC_END(_savegpr_15)
-FUNC_END(_savegpr_14)
-
-/* Routines for restoring floating point registers, called by the compiler. */
-/* Called with r11 pointing to the stack header word of the caller of the */
-/* function, just beyond the end of the floating point save area. */
-
-FUNC_START(_restfpr_14)	lfd	14,-144(11)	/* restore fp registers */
-FUNC_START(_restfpr_15)	lfd	15,-136(11)
-FUNC_START(_restfpr_16)	lfd	16,-128(11)
-FUNC_START(_restfpr_17)	lfd	17,-120(11)
-FUNC_START(_restfpr_18)	lfd	18,-112(11)
-FUNC_START(_restfpr_19)	lfd	19,-104(11)
-FUNC_START(_restfpr_20)	lfd	20,-96(11)
-FUNC_START(_restfpr_21)	lfd	21,-88(11)
-FUNC_START(_restfpr_22)	lfd	22,-80(11)
-FUNC_START(_restfpr_23)	lfd	23,-72(11)
-FUNC_START(_restfpr_24)	lfd	24,-64(11)
-FUNC_START(_restfpr_25)	lfd	25,-56(11)
-FUNC_START(_restfpr_26)	lfd	26,-48(11)
-FUNC_START(_restfpr_27)	lfd	27,-40(11)
-FUNC_START(_restfpr_28)	lfd	28,-32(11)
-FUNC_START(_restfpr_29)	lfd	29,-24(11)
-FUNC_START(_restfpr_30)	lfd	30,-16(11)
-FUNC_START(_restfpr_31)	lfd	31,-8(11)
-			blr
-FUNC_END(_restfpr_31)
-FUNC_END(_restfpr_30)
-FUNC_END(_restfpr_29)
-FUNC_END(_restfpr_28)
-FUNC_END(_restfpr_27)
-FUNC_END(_restfpr_26)
-FUNC_END(_restfpr_25)
-FUNC_END(_restfpr_24)
-FUNC_END(_restfpr_23)
-FUNC_END(_restfpr_22)
-FUNC_END(_restfpr_21)
-FUNC_END(_restfpr_20)
-FUNC_END(_restfpr_19)
-FUNC_END(_restfpr_18)
-FUNC_END(_restfpr_17)
-FUNC_END(_restfpr_16)
-FUNC_END(_restfpr_15)
-FUNC_END(_restfpr_14)
-
-/* Routines for restoring integer registers, called by the compiler. */
-/* Called with r11 pointing to the stack header word of the caller of the */
-/* function, just beyond the end of the integer restore area. */
-
-FUNC_START(_restgpr_14)	lwz	14,-72(11)	/* restore gp registers */
-FUNC_START(_restgpr_15)	lwz	15,-68(11)
-FUNC_START(_restgpr_16)	lwz	16,-64(11)
-FUNC_START(_restgpr_17)	lwz	17,-60(11)
-FUNC_START(_restgpr_18)	lwz	18,-56(11)
-FUNC_START(_restgpr_19)	lwz	19,-52(11)
-FUNC_START(_restgpr_20)	lwz	20,-48(11)
-FUNC_START(_restgpr_21)	lwz	21,-44(11)
-FUNC_START(_restgpr_22)	lwz	22,-40(11)
-FUNC_START(_restgpr_23)	lwz	23,-36(11)
-FUNC_START(_restgpr_24)	lwz	24,-32(11)
-FUNC_START(_restgpr_25)	lwz	25,-28(11)
-FUNC_START(_restgpr_26)	lwz	26,-24(11)
-FUNC_START(_restgpr_27)	lwz	27,-20(11)
-FUNC_START(_restgpr_28)	lwz	28,-16(11)
-FUNC_START(_restgpr_29)	lwz	29,-12(11)
-FUNC_START(_restgpr_30)	lwz	30,-8(11)
-FUNC_START(_restgpr_31)	lwz	31,-4(11)
-			blr
-FUNC_END(_restgpr_31)
-FUNC_END(_restgpr_30)
-FUNC_END(_restgpr_29)
-FUNC_END(_restgpr_28)
-FUNC_END(_restgpr_27)
-FUNC_END(_restgpr_26)
-FUNC_END(_restgpr_25)
-FUNC_END(_restgpr_24)
-FUNC_END(_restgpr_23)
-FUNC_END(_restgpr_22)
-FUNC_END(_restgpr_21)
-FUNC_END(_restgpr_20)
-FUNC_END(_restgpr_19)
-FUNC_END(_restgpr_18)
-FUNC_END(_restgpr_17)
-FUNC_END(_restgpr_16)
-FUNC_END(_restgpr_15)
-FUNC_END(_restgpr_14)
-
-/* Routines for restoring floating point registers, called by the compiler. */
-/* Called with r11 pointing to the stack header word of the caller of the */
-/* function, just beyond the end of the floating point save area. */
-/* In addition to restoring the fp registers, it will return to the caller's */
-/* caller */
-
-FUNC_START(_restfpr_14_x)	lfd	14,-144(11)	/* restore fp registers */
-FUNC_START(_restfpr_15_x)	lfd	15,-136(11)
-FUNC_START(_restfpr_16_x)	lfd	16,-128(11)
-FUNC_START(_restfpr_17_x)	lfd	17,-120(11)
-FUNC_START(_restfpr_18_x)	lfd	18,-112(11)
-FUNC_START(_restfpr_19_x)	lfd	19,-104(11)
-FUNC_START(_restfpr_20_x)	lfd	20,-96(11)
-FUNC_START(_restfpr_21_x)	lfd	21,-88(11)
-FUNC_START(_restfpr_22_x)	lfd	22,-80(11)
-FUNC_START(_restfpr_23_x)	lfd	23,-72(11)
-FUNC_START(_restfpr_24_x)	lfd	24,-64(11)
-FUNC_START(_restfpr_25_x)	lfd	25,-56(11)
-FUNC_START(_restfpr_26_x)	lfd	26,-48(11)
-FUNC_START(_restfpr_27_x)	lfd	27,-40(11)
-FUNC_START(_restfpr_28_x)	lfd	28,-32(11)
-FUNC_START(_restfpr_29_x)	lfd	29,-24(11)
-FUNC_START(_restfpr_30_x)	lfd	30,-16(11)
-FUNC_START(_restfpr_31_x)	lwz	0,4(11)
-				lfd	31,-8(11)
-				mtlr	0
-				mr	1,11
-				blr
-FUNC_END(_restfpr_31_x)
-FUNC_END(_restfpr_30_x)
-FUNC_END(_restfpr_29_x)
-FUNC_END(_restfpr_28_x)
-FUNC_END(_restfpr_27_x)
-FUNC_END(_restfpr_26_x)
-FUNC_END(_restfpr_25_x)
-FUNC_END(_restfpr_24_x)
-FUNC_END(_restfpr_23_x)
-FUNC_END(_restfpr_22_x)
-FUNC_END(_restfpr_21_x)
-FUNC_END(_restfpr_20_x)
-FUNC_END(_restfpr_19_x)
-FUNC_END(_restfpr_18_x)
-FUNC_END(_restfpr_17_x)
-FUNC_END(_restfpr_16_x)
-FUNC_END(_restfpr_15_x)
-FUNC_END(_restfpr_14_x)
-
-/* Routines for restoring integer registers, called by the compiler. */
-/* Called with r11 pointing to the stack header word of the caller of the */
-/* function, just beyond the end of the integer restore area. */
-
-FUNC_START(_restgpr_14_x)	lwz	14,-72(11)	/* restore gp registers */
-FUNC_START(_restgpr_15_x)	lwz	15,-68(11)
-FUNC_START(_restgpr_16_x)	lwz	16,-64(11)
-FUNC_START(_restgpr_17_x)	lwz	17,-60(11)
-FUNC_START(_restgpr_18_x)	lwz	18,-56(11)
-FUNC_START(_restgpr_19_x)	lwz	19,-52(11)
-FUNC_START(_restgpr_20_x)	lwz	20,-48(11)
-FUNC_START(_restgpr_21_x)	lwz	21,-44(11)
-FUNC_START(_restgpr_22_x)	lwz	22,-40(11)
-FUNC_START(_restgpr_23_x)	lwz	23,-36(11)
-FUNC_START(_restgpr_24_x)	lwz	24,-32(11)
-FUNC_START(_restgpr_25_x)	lwz	25,-28(11)
-FUNC_START(_restgpr_26_x)	lwz	26,-24(11)
-FUNC_START(_restgpr_27_x)	lwz	27,-20(11)
-FUNC_START(_restgpr_28_x)	lwz	28,-16(11)
-FUNC_START(_restgpr_29_x)	lwz	29,-12(11)
-FUNC_START(_restgpr_30_x)	lwz	30,-8(11)
-FUNC_START(_restgpr_31_x)	lwz	0,4(11)
-				lwz	31,-4(11)
-				mtlr	0
-				mr	1,11
-				blr
-FUNC_END(_restgpr_31_x)
-FUNC_END(_restgpr_30_x)
-FUNC_END(_restgpr_29_x)
-FUNC_END(_restgpr_28_x)
-FUNC_END(_restgpr_27_x)
-FUNC_END(_restgpr_26_x)
-FUNC_END(_restgpr_25_x)
-FUNC_END(_restgpr_24_x)
-FUNC_END(_restgpr_23_x)
-FUNC_END(_restgpr_22_x)
-FUNC_END(_restgpr_21_x)
-FUNC_END(_restgpr_20_x)
-FUNC_END(_restgpr_19_x)
-FUNC_END(_restgpr_18_x)
-FUNC_END(_restgpr_17_x)
-FUNC_END(_restgpr_16_x)
-FUNC_END(_restgpr_15_x)
-FUNC_END(_restgpr_14_x)
diff --git a/gcc/config/rs6000/eabi.h b/gcc/config/rs6000/eabi.h
deleted file mode 100755
index 1c225ea..0000000
--- a/gcc/config/rs6000/eabi.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Core target definitions for GNU compiler
-   for IBM RS/6000 PowerPC targeted to embedded ELF systems.
-   Copyright (C) 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "rs6000/sysv4.h"
-
-/* Add -meabi to target flags */
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_EABI)
-
-/* Invoke an initializer function to set up the GOT */
-#define NAME__MAIN "__eabi"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (PowerPC Embedded)");
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-  "-DPPC -D__embedded__ -Asystem(embedded) -Acpu(powerpc) -Amachine(powerpc)"
-
-#undef	MULTILIB_DEFAULTS
-#define	MULTILIB_DEFAULTS { "mbig", "mcall-sysv" }
diff --git a/gcc/config/rs6000/eabiaix.h b/gcc/config/rs6000/eabiaix.h
deleted file mode 100755
index 5cfd890..0000000
--- a/gcc/config/rs6000/eabiaix.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Embedded ELF system support, using old AIX based calling sequence.
-   Copyright (C) 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "rs6000/eabi.h"
-
-/* Default ABI to use */
-#undef	RS6000_ABI_NAME
-#define RS6000_ABI_NAME "aix"
-
-#undef	CPP_SYSV_DEFAULT_SPEC
-#define	CPP_SYSV_DEFAULT_SPEC "-D_CALL_AIX"
-
-/* Define this macro as a C expression for the initializer of an
-   array of string to tell the driver program which options are
-   defaults for this target and thus do not need to be handled
-   specially when using `MULTILIB_OPTIONS'.
-
-   Do not define this macro if `MULTILIB_OPTIONS' is not defined in
-   the target makefile fragment or if none of the options listed in
-   `MULTILIB_OPTIONS' are set by default.  *Note Target Fragment::.  */
-
-#undef	MULTILIB_DEFAULTS
-#define	MULTILIB_DEFAULTS { "mbig", "mcall-aix" }
diff --git a/gcc/config/rs6000/eabile.h b/gcc/config/rs6000/eabile.h
deleted file mode 100755
index 97e2b7c..0000000
--- a/gcc/config/rs6000/eabile.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Core target definitions for GNU compiler for PowerPC targeted to
-   little endian embedded ELF systems.
-   Copyright (C) 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "rs6000/eabi.h"
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_LITTLE_ENDIAN | MASK_EABI)
-
-#undef	CPP_ENDIAN_DEFAULT_SPEC
-#define	CPP_ENDIAN_DEFAULT_SPEC "%(cpp_endian_little)"
-
-#undef	CC1_ENDIAN_DEFAULT_SPEC
-#define	CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)"
-
-#undef	LINK_TARGET_SPEC
-#define	LINK_TARGET_SPEC "\
-%{mbig: -oformat elf32-powerpc } %{mbig-endian: -oformat elf32-powerpc } \
-%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: %{mcall-linux: -oformat elf32-powerpc}}}}}"
-
-/* Define this macro as a C expression for the initializer of an
-   array of string to tell the driver program which options are
-   defaults for this target and thus do not need to be handled
-   specially when using `MULTILIB_OPTIONS'.
-
-   Do not define this macro if `MULTILIB_OPTIONS' is not defined in
-   the target makefile fragment or if none of the options listed in
-   `MULTILIB_OPTIONS' are set by default.  *Note Target Fragment::.  */
-
-#undef	MULTILIB_DEFAULTS
-#define	MULTILIB_DEFAULTS { "mlittle", "mcall-sysv" }
diff --git a/gcc/config/rs6000/eabilesim.h b/gcc/config/rs6000/eabilesim.h
deleted file mode 100755
index 7ced05c..0000000
--- a/gcc/config/rs6000/eabilesim.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Support for GCC on simulated PowerPC systems targeted to embedded ELF
-   systems.
-   Copyright (C) 1995 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "rs6000/eabile.h"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (PowerPC Simulated)");
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-  "-DPPC -D__embedded__ -D__simulator__ -Asystem(embedded) -Asystem(simulator) -Acpu(powerpc) -Amachine(powerpc)"
-
-/* Make the simulator the default */
-#undef	LIB_DEFAULT_SPEC
-#define LIB_DEFAULT_SPEC "%(lib_sim)"
-
-#undef	STARTFILE_DEFAULT_SPEC
-#define STARTFILE_DEFAULT_SPEC "%(startfile_sim)"
-
-#undef	ENDFILE_DEFAULT_SPEC
-#define ENDFILE_DEFAULT_SPEC "%(endfile_sim)"
-
-#undef	LINK_START_DEFAULT_SPEC
-#define LINK_START_DEFAULT_SPEC "%(link_start_sim)"
-
-#undef	LINK_OS_DEFAULT_SPEC
-#define LINK_OS_DEFAULT_SPEC "%(link_start_sim)"
diff --git a/gcc/config/rs6000/eabisim.h b/gcc/config/rs6000/eabisim.h
deleted file mode 100755
index 0fc590b..0000000
--- a/gcc/config/rs6000/eabisim.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Support for GCC on simulated PowerPC systems targeted to embedded ELF
-   systems.
-   Copyright (C) 1995, 1996 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "rs6000/eabi.h"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (PowerPC Simulated)");
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-  "-DPPC -D__embedded__ -D__simulator__ -Asystem(embedded) -Asystem(simulator) -Acpu(powerpc) -Amachine(powerpc)"
-
-/* Make the simulator the default */
-#undef	LIB_DEFAULT_SPEC
-#define LIB_DEFAULT_SPEC "%(lib_sim)"
-
-#undef	STARTFILE_DEFAULT_SPEC
-#define STARTFILE_DEFAULT_SPEC "%(startfile_sim)"
-
-#undef	ENDFILE_DEFAULT_SPEC
-#define ENDFILE_DEFAULT_SPEC "%(endfile_sim)"
-
-#undef	LINK_START_DEFAULT_SPEC
-#define LINK_START_DEFAULT_SPEC "%(link_start_sim)"
-
-#undef	LINK_OS_DEFAULT_SPEC
-#define LINK_OS_DEFAULT_SPEC "%(link_os_sim)"
diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h
deleted file mode 100755
index cdc4dc0..0000000
--- a/gcc/config/rs6000/linux.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Definitions of target machine for GNU compiler,
-   for IBM RS/6000 running AIX version 3.1.
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Michael Meissner (meissner@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "rs6000/sysv4.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-DPPC -D__ELF__ -Dunix -Dlinux -Dpowerpc -Asystem(unix) -Asystem(linux) -Acpu(powerpc) -Amachine(powerpc)"
-
-#undef	CPP_OS_DEFAULT_SPEC
-#define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)"
-
-#undef LINK_SPEC
-#define LINK_SPEC "-m elf32ppc %{G*} %{shared:-shared} \
-  %{!shared: \
-    %{!static: \
-      %{rdynamic:-export-dynamic} \
-      %{!dynamic-linker:-dynamic-linker /lib/ld.so.1}} \
-    %{static:-static}}"
-
-#undef	LIB_DEFAULT_SPEC
-#define LIB_DEFAULT_SPEC "%(lib_linux)"
-
-#undef	STARTFILE_DEFAULT_SPEC
-#define STARTFILE_DEFAULT_SPEC "%(startfile_linux)"
-
-#undef	ENDFILE_DEFAULT_SPEC
-#define ENDFILE_DEFAULT_SPEC "%(endfile_linux)"
-
-#undef	LINK_START_DEFAULT_SPEC
-#define LINK_START_DEFAULT_SPEC "%(link_start_linux)"
-
-#undef	LINK_OS_DEFAULT_SPEC
-#define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (PowerPC GNU/Linux)");
-
-/* Define this macro as a C expression for the initializer of an
-   array of string to tell the driver program which options are
-   defaults for this target and thus do not need to be handled
-   specially when using `MULTILIB_OPTIONS'.
-
-   Do not define this macro if `MULTILIB_OPTIONS' is not defined in
-   the target makefile fragment or if none of the options listed in
-   `MULTILIB_OPTIONS' are set by default.  *Note Target Fragment::.  */
-
-#undef	MULTILIB_DEFAULTS
-#define	MULTILIB_DEFAULTS { "mbig", "mcall-linux" }
-
-#undef DEFAULT_VTABLE_THUNKS
-#ifndef USE_GNULIBC_1
-#define DEFAULT_VTABLE_THUNKS 1
-#endif
-
-#undef JUMP_TABLES_IN_TEXT_SECTION
-#define JUMP_TABLES_IN_TEXT_SECTION 0
diff --git a/gcc/config/rs6000/lynx.h b/gcc/config/rs6000/lynx.h
deleted file mode 100755
index e2fe633..0000000
--- a/gcc/config/rs6000/lynx.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Definitions for Rs6000 running LynxOS.
-   Copyright (C) 1995, 1996 Free Software Foundation, Inc.
-   Contributed by David Henkel-Wallace, Cygnus Support (gumby@cygnus.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <lynx.h>
-
-/* Definitions we want to override with those from rs6000.h: */
-#undef LIB_SPEC
-#undef PTRDIFF_TYPE
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-#undef ASM_FILE_START
-#undef EXTRA_SECTIONS
-#undef READONLY_DATA_SECTION
-#undef EXTRA_SECTION_FUNCTIONS
-#undef SELECT_RTX_SECTION
-#undef SELECT_SECTION
-#undef USER_LABEL_PREFIX
-#undef ASM_OUTPUT_LABELREF
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#undef ASM_GENERATE_INTERNAL_LABEL
-#undef ASM_OUTPUT_COMMON
-#undef ASM_OUTPUT_LOCAL
-#undef ASM_OUTPUT_CONSTRUCTOR
-#undef ASM_OUTPUT_DESTRUCTOR
-#undef CTORS_SECTION_FUNCTION
-#undef DTORS_SECTION_FUNCTION
-
-#undef SDB_DEBUGGING_INFO
-#undef DBX_DEBUGGING_INFO
-#undef PREFERRED_DEBUGGING_TYPE
-
-#undef FUNCTION_PROFILER
-
-#include <rs6000/rs6000.h>
-
-/* LynxOS has signed chars, regardless of what most R/S 6000 systems do */
-#undef DEFAULT_SIGNED_CHAR
-#define DEFAULT_SIGNED_CHAR 1
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Acpu(rs6000) -Amachine(rs6000) -Asystem(lynx) -Asystem(unix) -DLynx -D_IBMR2 -Dunix -Drs6000 -Dlynx -DLYNX"
-
-#undef LINK_SPEC
-#define LINK_SPEC "-T0x10001000 -H0x1000 -D0x20000000 -btextro -bhalt:4 -bnodelcsect -bnso -bro -bnoglink %{v} %{b*}"
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{mthreads:-L/lib/thread/}  \
-  %{msystem-v:-lc_v -lm.v}  \
-  %{!msystem-v:%{mposix:-lc_p} -lc -lm}"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{p:%{mthreads:thread/pinit.o%s}%{!mthreads:pinit.o%s}}%{!p:%{msystem-v:vinit.o%s -e_start}%{!msystem-v:%{mthreads:thread/init.o%s}%{!mthreads:init.o%s}}}"
-
-#undef ENDFILE_SPEC
-
-/* This can become more refined as we have more powerpc options. */
-#undef ASM_SPEC
-#define ASM_SPEC "-u %(asm_cpu)"
-
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-    {"threads",		MASK_THREADS},		\
-    {"posix",		MASK_POSIX},		\
-    {"system-v",	MASK_SYSTEM_V},
-
-#undef SUBTARGET_OVERRIDE_OPTIONS
-#define SUBTARGET_OVERRIDE_OPTIONS \
-do {								\
-  if (TARGET_SYSTEM_V && profile_flag)				\
-    warning ("-msystem-v and -p are incompatible");		\
-  if (TARGET_SYSTEM_V && TARGET_THREADS)			\
-    warning ("-msystem-v and -mthreads are incompatible");	\
-} while (0)
-
-/* For collect2 */
-#define OBJECT_FORMAT_NONE
-#undef OBJECT_FORMAT_COFF
-#undef OBJECT_FORMAT_ROSE
-#undef MD_EXEC_PREFIX
-#undef REAL_LD_FILE_NAME
-#undef REAL_NM_FILE_NAME
-#undef REAL_STRIP_FILE_NAME
-
-/* LynxOS doesn't have mcount. */
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(file, profile_label_no)
diff --git a/gcc/config/rs6000/mach.h b/gcc/config/rs6000/mach.h
deleted file mode 100755
index bb4e8b4..0000000
--- a/gcc/config/rs6000/mach.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Definitions of target machine for GNU compiler,
-   for IBM RS/6000 running MACH.
-   Copyright (C) 1992 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define TARGET_AIX 0
-
-#include "rs6000/rs6000.h"
-
-/* We don't define AIX under MACH; instead we define `unix'.  */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Drios -D_IBMR2 -Dunix -Asystem(unix) -Asystem(mach) -Acpu(rs6000) -Amachine(rs6000)"
-
-/* Define different binder options for MACH.  */
-#undef LINK_SPEC
-#define LINK_SPEC \
- "-T0x10000000 -D0x20000000 -K %{!nostdlib:%{!r*:%{!e*:-e __start}}} \
-  -bnoso -berrmsg -btextro -bhalt:4 -bnodelcsect"
-
-/* MACH doesn't have atexit.  */
-#undef HAVE_ATEXIT
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
diff --git a/gcc/config/rs6000/milli.exp b/gcc/config/rs6000/milli.exp
deleted file mode 100755
index ea3a2b7..0000000
--- a/gcc/config/rs6000/milli.exp
+++ /dev/null
@@ -1,7 +0,0 @@
-#!
-__mulh          0x3100
-__mull          0x3180
-__divss         0x3200
-__divus         0x3280
-__quoss         0x3300
-__quous         0x3380
diff --git a/gcc/config/rs6000/netware.h b/gcc/config/rs6000/netware.h
deleted file mode 100755
index 61133b9..0000000
--- a/gcc/config/rs6000/netware.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/* Core target definitions for GNU compiler
-   for IBM RS/6000 PowerPC running NetWare
-   Copyright (C) 1994, 1995, 1996, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define TARGET_AIX 0
-
-#define CPP_DEFAULT_SPEC "-D_ARCH_PPC"
-
-#define ASM_DEFAULT_SPEC "-mppc"
-
-#include "rs6000/rs6000.h"
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS)
-
-#undef PROCESSOR_DEFAULT
-#define PROCESSOR_DEFAULT PROCESSOR_PPC601
-
-/* Don't generate XCOFF debugging information.  */
-
-#undef XCOFF_DEBUGGING_INFO
-
-/* Don't use the COFF object file format.  */
-
-#undef OBJECT_FORMAT_COFF
-
-/* The XCOFF support uses weird symbol suffixes, which we don't want
-   for ELF.  */
-
-#undef STRIP_NAME_ENCODING
-
-/* Don't bother to output .extern pseudo-ops.  They are not needed by
-   ELF assemblers.  */
-
-#undef ASM_OUTPUT_EXTERNAL
-
-/* Undefine some things which are defined by the generic svr4.h.  */
-
-#undef ASM_FILE_END
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-#undef READONLY_DATA_SECTION
-#undef SELECT_SECTION
-#undef ASM_DECLARE_FUNCTION_NAME
-
-/* Use the regular svr4 definitions.  */
-
-#include "svr4.h"
-#include "netware.h"
-
-/* Create a function descriptor when we declare a function name.  This
-   is a mixture of the ASM_DECLARE_FUNCTION_NAME macros in rs6000.h
-   and svr4.h.  The unmodified function name is used to name the
-   descriptor.  The function name with an initial `.' is used to name
-   the code.  */
-
-#undef ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "function");			\
-    putc ('\n', FILE);							\
-    ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));			\
-    if (TREE_PUBLIC (DECL))						\
-      {									\
-        fprintf (FILE, "\t.globl .");					\
-	assemble_name (FILE, NAME);					\
-        fprintf (FILE, "\n");						\
-      }									\
-    data_section ();							\
-    ASM_OUTPUT_ALIGN (FILE, 2);						\
-    ASM_OUTPUT_LABEL (FILE, NAME);					\
-    fprintf (FILE, "\t.long .");					\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, ", __GOT0, 0\n");					\
-    text_section ();							\
-    fprintf (FILE, ".");						\
-    ASM_OUTPUT_LABEL (FILE, NAME);					\
-  } while (0)
-
-/* We need to override the .size output in order to put a `.' before
-   the function name.  */
-
-#undef ASM_DECLARE_FUNCTION_SIZE
-#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)			\
-  do {									\
-    if (!flag_inhibit_size_directive)					\
-      {									\
-        char label[256];						\
-	static int labelno;						\
-	labelno++;							\
-	ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno);		\
-	ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno);		\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, (FNAME));					\
-        fprintf (FILE, ",");						\
-	assemble_name (FILE, label);					\
-        fprintf (FILE, "-.");						\
-	assemble_name (FILE, (FNAME));					\
-	putc ('\n', FILE);						\
-      }									\
-  } while (0)
-
-/* Use ELF style section commands.  */
-
-#undef TEXT_SECTION_ASM_OP
-#define TEXT_SECTION_ASM_OP	"\t.section\t\".text\""
-
-#undef DATA_SECTION_ASM_OP
-#define DATA_SECTION_ASM_OP	"\t.section\t\".data\""
-
-/* Besides the usual ELF sections, we need a toc section.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_ctors, in_dtors, in_toc
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CONST_SECTION_FUNCTION						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION						\
-  TOC_SECTION_FUNCTION
-
-#define TOC_SECTION_FUNCTION						\
-void									\
-toc_section ()								\
-{									\
-  if (TARGET_MINIMAL_TOC)						\
-    {									\
-      static int toc_initialized = 0;					\
-									\
-      if (! toc_initialized)						\
-	{								\
-	  fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);		\
-	  fprintf (asm_out_file, ".LCTOC0:\n");				\
-	  fprintf (asm_out_file, "\t.tc .LCTOC1\n");			\
-	  fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);	\
-	  fprintf (asm_out_file, ".LCTOC1:\n");				\
-	  toc_initialized = 1;						\
-	}								\
-    }									\
-									\
-  if (in_section != in_toc)						\
-    {									\
-      fprintf (asm_out_file, "%s\n",					\
-	       (TARGET_MINIMAL_TOC					\
-		? MINIMAL_TOC_SECTION_ASM_OP				\
-		: TOC_SECTION_ASM_OP));					\
-      in_section = in_toc;						\
-    }									\
-}
-
-#define TOC_SECTION_ASM_OP "\t.section\t.got,\"aw\""
-#define MINIMAL_TOC_SECTION_ASM_OP "\t.section\t.got1,\"aw\""
-
-/* Use the TOC section for TOC entries.  */
-
-#undef SELECT_RTX_SECTION
-#define SELECT_RTX_SECTION(MODE, X)		\
-{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X))	\
-    toc_section ();				\
-  else						\
-    const_section ();				\
-}
-
-/* How to renumber registers for dbx and gdb.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* svr4.h overrides ASM_OUTPUT_INTERNAL_LABEL.  */
-
-#undef ASM_OUTPUT_INTERNAL_LABEL_PREFIX
-#define ASM_OUTPUT_INTERNAL_LABEL_PREFIX(FILE,PREFIX)	\
-  fprintf (FILE, ".%s", PREFIX)
-
-#undef ASM_SPEC
-#define ASM_SPEC "-u %(asm_cpu) \
-{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*}"
-/* This is the end of what might become sysv4.h.  */
-
-/* Enable output of DBX (stabs) debugging information when asked for it.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Prefer DBX (stabs) debugging information over the native (DWARF) format. */
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* Line numbers are relative to the current function.  */
-
-#undef  ASM_OUTPUT_SOURCE_LINE
-#define ASM_OUTPUT_SOURCE_LINE(file, line)		\
-  { static int sym_lineno = 1;				\
-    fprintf (file, ".stabn 68,0,%d,.LM%d-.%s\n.LM%d:\n",\
-	     line, sym_lineno, 				\
-	     XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0), \
-	     sym_lineno);				\
-    sym_lineno += 1; }
-
-/* But, to make this work, we have to output the stabs for the function
-   name *first*...  */
-
-#define	DBX_FUNCTION_FIRST
-
-/* We need to output LBRAC and RBRAC lines specially to include the
-   dot in from of the text symbol for a function.  */
-
-#define DBX_OUTPUT_LBRAC(FILE, BUF)					   \
-do									   \
-  {									   \
-    fprintf (FILE, "%s %d,0,0,", ASM_STABN_OP, N_LBRAC);		   \
-    assemble_name (FILE, BUF);						   \
-    fprintf (FILE, "-.");						   \
-    assemble_name (asmfile,						   \
-		   XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));  \
-    fprintf (asmfile, "\n");						   \
-  }									   \
-while (0)
-
-#define DBX_OUTPUT_RBRAC(FILE, BUF)					   \
-do									   \
-  {									   \
-    fprintf (FILE, "%s %d,0,0,", ASM_STABN_OP, N_RBRAC);		   \
-    assemble_name (FILE, BUF);						   \
-    fprintf (FILE, "-.");						   \
-    assemble_name (asmfile,						   \
-		   XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));  \
-    fprintf (asmfile, "\n");						   \
-  }									   \
-while (0)
-
-/* We are using function descriptors, so the value of a function
-   symbol is in the .data section.  However, we want the stabs entry
-   for that function to point at the actual function code in the .text
-   section, which we get by prefixing the symbol with a dot.  */
-
-#define DBX_FINISH_SYMBOL(sym)						\
-do {									\
-  int line = 0;								\
-  if (use_gnu_debug_info_extensions && sym != 0)			\
-    line = DECL_SOURCE_LINE (sym);					\
-									\
-  fprintf (asmfile, "\",%d,0,%d,", current_sym_code, line);		\
-  if (current_sym_addr)							\
-    {									\
-      if (TREE_CODE (sym) == FUNCTION_DECL)				\
-	fprintf (asmfile, ".");						\
-      output_addr_const (asmfile, current_sym_addr);			\
-    }									\
-  else									\
-    fprintf (asmfile, "%d", current_sym_value);				\
-  putc ('\n', asmfile);							\
-} while (0)
-
-/* This is the end of what might become sysv4dbx.h.  */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (PowerPC Netware)");
-
-/* FIXME: These should actually indicate PowerPC, when there is some
-   standard way of expressing that.  */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-  "-DPPC D__netware__ -Asystem(netware) -Acpu(powerpc) -Amachine(powerpc)"
diff --git a/gcc/config/rs6000/nt-ci.asm b/gcc/config/rs6000/nt-ci.asm
deleted file mode 100755
index 67ca956..0000000
--- a/gcc/config/rs6000/nt-ci.asm
+++ /dev/null
@@ -1,48 +0,0 @@
-# crti.s for Windows NT
-
-#   Copyright (C) 1996 Free Software Foundation, Inc.
-#   Written By Michael Meissner
-# 
-# This file is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License as published by the
-# Free Software Foundation; either version 2, or (at your option) any
-# later version.
-# 
-# In addition to the permissions in the GNU General Public License, the
-# Free Software Foundation gives you unlimited permission to link the
-# compiled version of this file with other programs, and to distribute
-# those programs without any restriction coming from the use of this
-# file.  (The General Public License restrictions do apply in other
-# respects; for example, they cover modification of the file, and
-# distribution when not linked into another program.)
-# 
-# This file is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-# General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with this program; see the file COPYING.  If not, write to
-# the Free Software Foundation, 59 Temple Place - Suite 330,
-# Boston, MA 02111-1307, USA.
-# 
-#    As a special exception, if you link this library with files
-#    compiled with GCC to produce an executable, this does not cause
-#    the resulting executable to be covered by the GNU General Public License.
-#    This exception does not however invalidate any other reasons why
-#    the executable file might be covered by the GNU General Public License.
-# 
-
-# This file just supplies labeled starting points for the static constructors
-# and destructors.  It is linked in first before other modules.
- 
-	.file	"crti.s"
-	.ident	"GNU C crti.s"
-
-	.section .ctors,"w"
-	.globl	__CTOR_LIST__
-__CTOR_LIST__:
-
-	.section .dtors,"w"
-	.globl	__DTOR_LIST__
-__DTOR_LIST__:
diff --git a/gcc/config/rs6000/nt-cn.asm b/gcc/config/rs6000/nt-cn.asm
deleted file mode 100755
index dd6daf2..0000000
--- a/gcc/config/rs6000/nt-cn.asm
+++ /dev/null
@@ -1,48 +0,0 @@
-# crtn.s for Windows NT
-
-#   Copyright (C) 1996 Free Software Foundation, Inc.
-#   Written By Michael Meissner
-# 
-# This file is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License as published by the
-# Free Software Foundation; either version 2, or (at your option) any
-# later version.
-# 
-# In addition to the permissions in the GNU General Public License, the
-# Free Software Foundation gives you unlimited permission to link the
-# compiled version of this file with other programs, and to distribute
-# those programs without any restriction coming from the use of this
-# file.  (The General Public License restrictions do apply in other
-# respects; for example, they cover modification of the file, and
-# distribution when not linked into another program.)
-# 
-# This file is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-# General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with this program; see the file COPYING.  If not, write to
-# the Free Software Foundation, 59 Temple Place - Suite 330,
-# Boston, MA 02111-1307, USA.
-# 
-#    As a special exception, if you link this library with files
-#    compiled with GCC to produce an executable, this does not cause
-#    the resulting executable to be covered by the GNU General Public License.
-#    This exception does not however invalidate any other reasons why
-#    the executable file might be covered by the GNU General Public License.
-# 
-
-# This file just supplies labeled ending points for the static constructors
-# and destructors.  It is linked in last after other modules.
- 
-	.file	"crtn.s"
-	.ident	"GNU C crtn.s"
-
-	.section .ctors,"w"
-	.globl	__CTOR_END__
-__CTOR_END__:
-
-	.section .dtors,"w"
-	.globl	__DTOR_END__
-__DTOR_END__:
diff --git a/gcc/config/rs6000/ntstack.asm b/gcc/config/rs6000/ntstack.asm
deleted file mode 100755
index aa4179e..0000000
--- a/gcc/config/rs6000/ntstack.asm
+++ /dev/null
@@ -1,42 +0,0 @@
-# Allocate stack for NT, inserting stack probes every 4k pages
-
-	.file	"ntstack.asm"
-
-#	Setup MS Structured-Exception-Handling
-	.pdata
-	.align 2
-	.ualong ..__allocate_stack,__allocate_stack.e,0,0,__allocate_stack.b
-
-#	Switch to the relocation section
-	.reldata
-	.globl __allocate_stack
-	.globl ..__allocate_stack
-__allocate_stack:
-	.ualong ..__allocate_stack,.toc
-
-	.text
-	.align 2
-..__allocate_stack:
-	.function	..__allocate_stack
-__allocate_stack.b:
-	addi	3,3,15			# round up to 16 byte alignment
-	lwz	0,0(1)			# old stack link
-	rlwinm	3,3,0,0,28
-	srawi.	4,3,12			# get # of pages to check
-	neg	3,3			# negate so we can use stwux
-	bgt-	0,.Lcheck
-	stwux	0,1,3			# small request, just decrement and return
-	blr
-
-.Lcheck:
-	mtctr	4			# number of pages to check
-	mr	5,1			# tmp pointer
-.Lloop:
-	lwzu	6,-4096(5)		# touch the page
-	bdnz+	.Lloop			# and loop back
-
-	stwux	0,1,3			# update stack pointer
-	blr
-
-__allocate_stack.e:
-FE_MOT_RESVD..__allocate_stack:
diff --git a/gcc/config/rs6000/powerpc.h b/gcc/config/rs6000/powerpc.h
deleted file mode 100755
index 9f1ffd6..0000000
--- a/gcc/config/rs6000/powerpc.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Definitions of target machine for GNU compiler,
-   for IBM RS/6000 PowerPC running AIX version 3.2.
-   Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
-   Contributed by David Edelsohn (edelsohn@npac.syr.edu).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "rs6000/rs6000.h"
-
-#undef ASM_SPEC
-#define ASM_SPEC "-u %(asm_cpu)"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D_IBMR2 -D_POWER -D_AIX -D_AIX32 \
--Asystem(unix) -Asystem(aix) -Acpu(powerpc) -Amachine(powerpc)"
-
-#undef	CPP_DEFAULT_SPEC
-#define	CPP_DEFAULT_SPEC "-D_ARCH_PPC"
-
-#undef	ASM_DEFAULT_SPEC
-#define	ASM_DEFAULT_SPEC "-mppc"
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS)
-
-#undef PROCESSOR_DEFAULT
-#define PROCESSOR_DEFAULT PROCESSOR_PPC601
-
-/* These are not necessary when we pass -u to the assembler, and undefining
-   them saves a great deal of space in object files.  */
-
-#undef ASM_OUTPUT_EXTERNAL
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)	\
-{ rtx _symref = XEXP (DECL_RTL (DECL), 0);	\
-  if ((TREE_CODE (DECL) == VAR_DECL		\
-       || TREE_CODE (DECL) == FUNCTION_DECL)	\
-      && (NAME)[strlen (NAME) - 1] != ']')	\
-    {						\
-      char *_name = (char *) permalloc (strlen (XSTR (_symref, 0)) + 5); \
-      strcpy (_name, XSTR (_symref, 0));	\
-      strcat (_name, TREE_CODE (DECL) == FUNCTION_DECL ? "[DS]" : "[RW]"); \
-      XSTR (_symref, 0) = _name;		\
-    }						\
-}
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
deleted file mode 100755
index 53ef3f1..0000000
--- a/gcc/config/rs6000/rs6000.c
+++ /dev/null
@@ -1,7156 +0,0 @@
-/* Subroutines used for code generation on IBM RS/6000.
-   Copyright (C) 1991, 93-8, 1999 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include "system.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#include "expr.h"
-#include "obstack.h"
-#include "tree.h"
-#include "except.h"
-#include "function.h"
-#include "output.h"
-#include "toplev.h"
-
-#ifndef TARGET_NO_PROTOTYPE
-#define TARGET_NO_PROTOTYPE 0
-#endif
-
-extern char *language_string;
-extern int profile_block_flag;
-
-#define min(A,B)	((A) < (B) ? (A) : (B))
-#define max(A,B)	((A) > (B) ? (A) : (B))
-
-/* Target cpu type */
-
-enum processor_type rs6000_cpu;
-struct rs6000_cpu_select rs6000_select[3] =
-{
-  /* switch	name,			tune	arch */
-  { (char *)0,	"--with-cpu=",		1,	1 },
-  { (char *)0,	"-mcpu=",		1,	1 },
-  { (char *)0,	"-mtune=",		1,	0 },
-};
-
-/* Set to non-zero by "fix" operation to indicate that itrunc and
-   uitrunc must be defined.  */
-
-int rs6000_trunc_used;
-
-/* Set to non-zero once they have been defined.  */
-
-static int trunc_defined;
-
-/* Set to non-zero once AIX common-mode calls have been defined.  */
-static int common_mode_defined;
-
-/* Save information from a "cmpxx" operation until the branch or scc is
-   emitted.  */
-rtx rs6000_compare_op0, rs6000_compare_op1;
-int rs6000_compare_fp_p;
-
-/* CYGNUS LOCAL -- vmakarov */
-/* Override for BRANCH_COST */
-char *rs6000_branch_cost_string;
-int rs6000_branch_cost = BRANCH_COST_DEFAULT;
-/* END CYGNUS LOCAL */
-
-#ifdef USING_SVR4_H
-/* Label number of label created for -mrelocatable, to call to so we can
-   get the address of the GOT section */
-int rs6000_pic_labelno;
-int rs6000_pic_func_labelno;
-
-/* Which abi to adhere to */
-char *rs6000_abi_name = RS6000_ABI_NAME;
-
-/* Semantics of the small data area */
-enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
-
-/* Which small data model to use */
-char *rs6000_sdata_name = (char *)0;
-#endif
-
-/* Whether a System V.4 varargs area was created.  */
-int rs6000_sysv_varargs_p;
-
-/* ABI enumeration available for subtarget to use.  */
-enum rs6000_abi rs6000_current_abi;
-
-/* Offset & size for fpmem stack locations used for converting between
-   float and integral types.  */
-int rs6000_fpmem_offset;
-int rs6000_fpmem_size;
-
-/* Debug flags */
-char *rs6000_debug_name;
-int rs6000_debug_stack;		/* debug stack applications */
-int rs6000_debug_arg;		/* debug argument handling */
-
-/* Flag to say the TOC is initialized */
-int toc_initialized;
-
-
-/* Default register names.  */
-char rs6000_reg_names[][8] =
-{
-      "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
-      "8",  "9", "10", "11", "12", "13", "14", "15",
-     "16", "17", "18", "19", "20", "21", "22", "23",
-     "24", "25", "26", "27", "28", "29", "30", "31",
-      "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
-      "8",  "9", "10", "11", "12", "13", "14", "15",
-     "16", "17", "18", "19", "20", "21", "22", "23",
-     "24", "25", "26", "27", "28", "29", "30", "31",
-     "mq", "lr", "ctr","ap",
-      "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
-  "fpmem"
-};
-
-#ifdef TARGET_REGNAMES
-static char alt_reg_names[][8] =
-{
-   "%r0",   "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
-   "%r8",   "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
-  "%r16",  "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
-  "%r24",  "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
-   "%f0",   "%f1",  "%f2",  "%f3",  "%f4",  "%f5",  "%f6",  "%f7",
-   "%f8",   "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
-  "%f16",  "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
-  "%f24",  "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
-    "mq",    "lr",  "ctr",   "ap",
-  "%cr0",  "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
- "fpmem"
-};
-#endif
-
-#ifndef MASK_STRICT_ALIGN
-#define MASK_STRICT_ALIGN 0
-#endif
-
-/* Override command line options.  Mostly we process the processor
-   type and sometimes adjust other TARGET_ options.  */
-
-void
-rs6000_override_options (default_cpu)
-     char *default_cpu;
-{
-  size_t i, j;
-  struct rs6000_cpu_select *ptr;
-
-  /* Simplify the entries below by making a mask for any POWER
-     variant and any PowerPC variant.  */
-
-#define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
-#define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
-		       | MASK_PPC_GFXOPT | MASK_POWERPC64)
-#define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
-
-  static struct ptt
-    {
-      char *name;		/* Canonical processor name.  */
-      enum processor_type processor; /* Processor type enum value.  */
-      int target_enable;	/* Target flags to enable.  */
-      int target_disable;	/* Target flags to disable.  */
-    } processor_target_table[]
-      = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS,
-	    POWER_MASKS | POWERPC_MASKS},
-	 {"power", PROCESSOR_POWER,
-	    MASK_POWER | MASK_MULTIPLE | MASK_STRING,
-	    MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
-	 {"power2", PROCESSOR_POWER,
-	    MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
-	    POWERPC_MASKS | MASK_NEW_MNEMONICS},
-	 {"powerpc", PROCESSOR_POWERPC,
-	    MASK_POWERPC | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
-	 {"rios", PROCESSOR_RIOS1,
-	    MASK_POWER | MASK_MULTIPLE | MASK_STRING,
-	    MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
-	 {"rios1", PROCESSOR_RIOS1,
-	    MASK_POWER | MASK_MULTIPLE | MASK_STRING,
-	    MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
-	 {"rsc", PROCESSOR_PPC601,
-	    MASK_POWER | MASK_MULTIPLE | MASK_STRING,
-	    MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
-	 {"rsc1", PROCESSOR_PPC601,
-	    MASK_POWER | MASK_MULTIPLE | MASK_STRING,
-	    MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
-	 {"rios2", PROCESSOR_RIOS2,
-	    MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
-	    POWERPC_MASKS | MASK_NEW_MNEMONICS},
-	 {"401", PROCESSOR_PPC403,
-	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
-	 {"403", PROCESSOR_PPC403,
-	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN,
-	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
-	 {"505", PROCESSOR_MPCCORE,
-	    MASK_POWERPC | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
-	 {"601", PROCESSOR_PPC601,
-	    MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
-	    MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
-	 {"602", PROCESSOR_PPC603,
-	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
-	 {"603", PROCESSOR_PPC603,
-	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
-	 {"603e", PROCESSOR_PPC603,
-	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
-	 {"ec603e", PROCESSOR_PPC603,
-	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
-	 {"604", PROCESSOR_PPC604,
-	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
-	 {"604e", PROCESSOR_PPC604e,
-	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
-	 {"620", PROCESSOR_PPC620,
-	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | MASK_PPC_GPOPT},
-	 {"740", PROCESSOR_PPC750,
-	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
-	 {"750", PROCESSOR_PPC750,
-	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
-	 {"801", PROCESSOR_MPCCORE,
-	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
-	 {"821", PROCESSOR_MPCCORE,
-	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
-	 {"823", PROCESSOR_MPCCORE,
-	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
-	 {"860", PROCESSOR_MPCCORE,
-	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
-	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}};
-
-  size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
-
-  int multiple = TARGET_MULTIPLE;	/* save current -mmultiple/-mno-multiple status */
-  int string   = TARGET_STRING;		/* save current -mstring/-mno-string status */
-
-  profile_block_flag = 0;
-
-  /* Identify the processor type */
-  rs6000_select[0].string = default_cpu;
-  rs6000_cpu = PROCESSOR_DEFAULT;
-
-  for (i = 0; i < sizeof (rs6000_select) / sizeof (rs6000_select[0]); i++)
-    {
-      ptr = &rs6000_select[i];
-      if (ptr->string != (char *)0 && ptr->string[0] != '\0')
-	{
-	  for (j = 0; j < ptt_size; j++)
-	    if (! strcmp (ptr->string, processor_target_table[j].name))
-	      {
-		if (ptr->set_tune_p)
-		  rs6000_cpu = processor_target_table[j].processor;
-
-		if (ptr->set_arch_p)
-		  {
-		    target_flags |= processor_target_table[j].target_enable;
-		    target_flags &= ~processor_target_table[j].target_disable;
-		  }
-		break;
-	      }
-
-	  if (i == ptt_size)
-	    error ("bad value (%s) for %s switch", ptr->string, ptr->name);
-	}
-    }
-
-  /* If we are optimizing big endian systems for space, use the
-     store multiple instructions.  */
-  if (BYTES_BIG_ENDIAN && optimize_size)
-    target_flags |= MASK_MULTIPLE;
-
-  /* If -mmultiple or -mno-multiple was explicitly used, don't
-     override with the processor default */
-  if (TARGET_MULTIPLE_SET)
-    target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
-
-  /* If -mstring or -mno-string was explicitly used, don't
-     override with the processor default */
-  if (TARGET_STRING_SET)
-    target_flags = (target_flags & ~MASK_STRING) | string;
-
-  /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu
-     is a 750, because the hardware doesn't support the instructions used in
-     little endian mode, and causes an alignment trap.  The 750 does not cause
-     an alignment trap (except when the target is unaligned).  */
-
-  if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
-    {
-      if (TARGET_MULTIPLE)
-	{
-	  target_flags &= ~MASK_MULTIPLE;
-	  if (TARGET_MULTIPLE_SET)
-	    warning ("-mmultiple is not supported on little endian systems");
-	}
-
-      if (TARGET_STRING)
-	{
-	  target_flags &= ~MASK_STRING;
-	  if (TARGET_STRING_SET)
-	    warning ("-mstring is not supported on little endian systems");
-	}
-    }
-
-  if (flag_pic && (DEFAULT_ABI == ABI_AIX))
-    {
-      warning ("-f%s ignored for AIX (all code is position independent)",
-	       (flag_pic > 1) ? "PIC" : "pic");
-      flag_pic = 0;
-    }
-
-  /* Set debug flags */
-  if (rs6000_debug_name)
-    {
-      if (!strcmp (rs6000_debug_name, "all"))
-	rs6000_debug_stack = rs6000_debug_arg = 1;
-      else if (!strcmp (rs6000_debug_name, "stack"))
-	rs6000_debug_stack = 1;
-      else if (!strcmp (rs6000_debug_name, "arg"))
-	rs6000_debug_arg = 1;
-      else
-	error ("Unknown -mdebug-%s switch", rs6000_debug_name);
-    }
-
-#ifdef TARGET_REGNAMES
-  /* If the user desires alternate register names, copy in the alternate names
-     now.  */
-  if (TARGET_REGNAMES)
-    bcopy ((char *)alt_reg_names, (char *)rs6000_reg_names, sizeof (rs6000_reg_names));
-#endif
-
-  /* CYGNUS LOCAL -- vmakarov */
-  /* Override BRANCH_COST if -mbranch-cost= */
-  if (rs6000_branch_cost_string)
-    rs6000_branch_cost = atoi (rs6000_branch_cost_string);
-  /* END CYGNUS LOCAL */
-
-#ifdef SUBTARGET_OVERRIDE_OPTIONS
-  SUBTARGET_OVERRIDE_OPTIONS;
-#endif
-}
-
-void
-optimization_options (level, size)
-     int level;
-     int size ATTRIBUTE_UNUSED;
-{
-#ifdef HAVE_decrement_and_branch_on_count
-  /* When optimizing, enable use of BCT instruction.  */
-  if (level >= 1)
-      flag_branch_on_count_reg = 1;
-#endif
-}
-
-/* Do anything needed at the start of the asm file.  */
-
-void
-rs6000_file_start (file, default_cpu)
-     FILE *file;
-     char *default_cpu;
-{
-  size_t i;
-  char buffer[80];
-  char *start = buffer;
-  struct rs6000_cpu_select *ptr;
-
-  if (flag_verbose_asm)
-    {
-      sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
-      rs6000_select[0].string = default_cpu;
-
-      for (i = 0; i < sizeof (rs6000_select) / sizeof (rs6000_select[0]); i++)
-	{
-	  ptr = &rs6000_select[i];
-	  if (ptr->string != (char *)0 && ptr->string[0] != '\0')
-	    {
-	      fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
-	      start = "";
-	    }
-	}
-
-#ifdef USING_SVR4_H
-      switch (rs6000_sdata)
-	{
-	case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
-	case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
-	case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
-	case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
-	}
-
-      if (rs6000_sdata && g_switch_value)
-	{
-	  fprintf (file, "%s -G %d", start, g_switch_value);
-	  start = "";
-	}
-#endif
-
-      if (*start == '\0')
-	fputs ("\n", file);
-    }
-}
-
-
-/* Create a CONST_DOUBLE from a string.  */
-
-struct rtx_def *
-rs6000_float_const (string, mode)
-     char *string;
-     enum machine_mode mode;
-{
-  REAL_VALUE_TYPE value = REAL_VALUE_ATOF (string, mode);
-  return immed_real_const_1 (value, mode);
-}
-
-/* Return non-zero if this function is known to have a null epilogue.  */
-
-int
-direct_return ()
-{
-  if (reload_completed)
-    {
-      rs6000_stack_t *info = rs6000_stack_info ();
-
-      if (info->first_gp_reg_save == 32
-	  && info->first_fp_reg_save == 64
-	  && !info->lr_save_p
-	  && !info->cr_save_p
-	  && !info->push_p)
-	return 1;
-    }
-
-  return 0;
-}
-
-/* Returns 1 always.  */
-
-int
-any_operand (op, mode)
-     register rtx op ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return 1;
-}
-
-/* Returns 1 if op is the count register */
-int
-count_register_operand(op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) != REG)
-    return 0;
-
-  if (REGNO (op) == COUNT_REGISTER_REGNUM)
-    return 1;
-
-  if (REGNO (op) > FIRST_PSEUDO_REGISTER)
-    return 1;
-
-  return 0;
-}
-
-/* Returns 1 if op is memory location for float/int conversions that masquerades
-   as a register.  */
-int
-fpmem_operand(op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) != REG)
-    return 0;
-
-  if (FPMEM_REGNO_P (REGNO (op)))
-    return 1;
-
-#if 0
-  if (REGNO (op) > FIRST_PSEUDO_REGISTER)
-    return 1;
-#endif
-
-  return 0;
-}
-
-/* Return 1 if OP is a constant that can fit in a D field.  */
-
-int
-short_cint_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return ((GET_CODE (op) == CONST_INT
-	   && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) < 0x10000)
-	  || GET_CODE (op) == CONSTANT_P_RTX);
-}
-
-/* Similar for a unsigned D field.  */
-
-int
-u_short_cint_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return ((GET_CODE (op) == CONST_INT
-	   && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0)
-	  || GET_CODE (op) == CONSTANT_P_RTX);
-}
-
-/* Return 1 if OP is a CONST_INT that cannot fit in a signed D field.  */
-
-int
-non_short_cint_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT
-	  && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
-}
-
-/* Returns 1 if OP is a register that is not special (i.e., not MQ,
-   ctr, or lr).  */
-
-int
-gpc_reg_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  && (GET_CODE (op) != REG
-	      || (REGNO (op) >= 67 && !FPMEM_REGNO_P (REGNO (op)))
-	      || REGNO (op) < 64));
-}
-
-/* Returns 1 if OP is either a pseudo-register or a register denoting a
-   CR field.  */
-
-int
-cc_reg_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  && (GET_CODE (op) != REG
-	      || REGNO (op) >= FIRST_PSEUDO_REGISTER
-	      || CR_REGNO_P (REGNO (op))));
-}
-
-/* Returns 1 if OP is either a pseudo-register or a register denoting a
-   CR field that isn't CR0.  */
-
-int
-cc_reg_not_cr0_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  && (GET_CODE (op) != REG
-	      || REGNO (op) >= FIRST_PSEUDO_REGISTER
-	      || CR_REGNO_NOT_CR0_P (REGNO (op))));
-}
-
-/* Returns 1 if OP is either a constant integer valid for a D-field or a
-   non-special register.  If a register, it must be in the proper mode unless
-   MODE is VOIDmode.  */
-
-int
-reg_or_short_operand (op, mode)
-      register rtx op;
-      enum machine_mode mode;
-{
-  return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
-}
-
-/* Similar, except check if the negation of the constant would be valid for
-   a D-field.  */
-
-int
-reg_or_neg_short_operand (op, mode)
-      register rtx op;
-      enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
-
-  return gpc_reg_operand (op, mode);
-}
-
-/* Return 1 if the operand is either a register or an integer whose high-order
-   16 bits are zero.  */
-
-int
-reg_or_u_short_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
-}
-
-/* Return 1 is the operand is either a non-special register or ANY
-   constant integer.  */
-
-int
-reg_or_cint_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-     return (GET_CODE (op) == CONST_INT
-	     || GET_CODE (op) == CONSTANT_P_RTX
-	     || gpc_reg_operand (op, mode));
-}
-
-/* Return 1 if the operand is an operand that can be loaded via the GOT */
-
-int
-got_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == SYMBOL_REF
-	  || GET_CODE (op) == CONST
-	  || GET_CODE (op) == LABEL_REF);
-}
-
-/* Return 1 if the operand is a simple references that can be loaded via
-   the GOT (labels involving addition aren't allowed).  */
-
-int
-got_no_const_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
-}
-
-/* Return the number of instructions it takes to form a constant in an
-   integer register.  */
-
-static int
-num_insns_constant_wide (value)
-     HOST_WIDE_INT value;
-{
-  /* signed constant loadable with {cal|addi} */
-  if (((unsigned HOST_WIDE_INT)value + 0x8000) < 0x10000)
-    return 1;
-
-#if HOST_BITS_PER_WIDE_INT == 32
-  /* constant loadable with {cau|addis} */
-  else if ((value & 0xffff) == 0)
-    return 1;
-
-#else
-  /* constant loadable with {cau|addis} */
-  else if ((value & 0xffff) == 0 && (value & ~0xffffffff) == 0)
-    return 1;
-
-  else if (TARGET_64BIT)
-    {
-      HOST_WIDE_INT low  = value & 0xffffffff;
-      HOST_WIDE_INT high = value >> 32;
-
-      if (high == 0 && (low & 0x80000000) == 0)
-	return 2;
-
-      else if (high == 0xffffffff && (low & 0x80000000) != 0)
-	return 2;
-
-      else if (!low)
-	return num_insns_constant_wide (high) + 1;
-
-      else
-	return (num_insns_constant_wide (high)
-		+ num_insns_constant_wide (low) + 1);
-    }
-#endif
-
-  else
-    return 2;
-}
-
-int
-num_insns_constant (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return num_insns_constant_wide (INTVAL (op));
-
-  else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
-    {
-      long l;
-      REAL_VALUE_TYPE rv;
-
-      REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
-      REAL_VALUE_TO_TARGET_SINGLE (rv, l);
-      return num_insns_constant_wide ((HOST_WIDE_INT)l);
-    }
-
-  else if (GET_CODE (op) == CONST_DOUBLE)
-    {
-      HOST_WIDE_INT low;
-      HOST_WIDE_INT high;
-      long l[2];
-      REAL_VALUE_TYPE rv;
-      int endian = (WORDS_BIG_ENDIAN == 0);
-
-      if (mode == VOIDmode || mode == DImode)
-	{
-	  high = CONST_DOUBLE_HIGH (op);
-	  low  = CONST_DOUBLE_LOW (op);
-	}
-      else
-	{
-	  REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
-	  REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
-	  high = l[endian];
-	  low  = l[1 - endian];
-	}
-
-      if (TARGET_32BIT)
-	return (num_insns_constant_wide (low)
-		+ num_insns_constant_wide (high));
-
-      else
-	{
-	  if (high == 0 && (low & 0x80000000) == 0)
-	    return num_insns_constant_wide (low);
-
-	  else if (((high & 0xffffffff) == 0xffffffff)
-		   && ((low & 0x80000000) != 0))
-	    return num_insns_constant_wide (low);
-
-	  else if (mask64_operand (op, mode))
-	    return 2;
-
-	  else if (low == 0)
-	    return num_insns_constant_wide (high) + 1;
-
-	  else
-	    return (num_insns_constant_wide (high)
-		    + num_insns_constant_wide (low) + 1);
-	}
-    }
-
-  else
-    abort ();
-}
-
-/* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register
-   with one instruction per word.  We only do this if we can safely read
-   CONST_DOUBLE_{LOW,HIGH}.  */
-
-int
-easy_fp_constant (op, mode)
-     register rtx op;
-     register enum machine_mode mode;
-{
-  if (GET_CODE (op) != CONST_DOUBLE
-      || GET_MODE (op) != mode
-      || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
-    return 0;
-
-  /* Consider all constants with -msoft-float to be easy */
-  if (TARGET_SOFT_FLOAT && mode != DImode)
-    return 1;
-
-  /* If we are using V.4 style PIC, consider all constants to be hard */
-  if (flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
-    return 0;
-
-#ifdef TARGET_RELOCATABLE
-  /* Similarly if we are using -mrelocatable, consider all constants to be hard */
-  if (TARGET_RELOCATABLE)
-    return 0;
-#endif
-
-  if (mode == DFmode)
-    {
-      long k[2];
-      REAL_VALUE_TYPE rv;
-
-      REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
-      REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
-
-      return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1
-	      && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1);
-    }
-
-  else if (mode == SFmode)
-    {
-      long l;
-      REAL_VALUE_TYPE rv;
-
-      REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
-      REAL_VALUE_TO_TARGET_SINGLE (rv, l);
-
-      return num_insns_constant_wide (l) == 1;
-    }
-
-  else if (mode == DImode)
-    return ((TARGET_64BIT
-	     && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
-	    || (num_insns_constant (op, DImode) <= 2));
-
-  else
-    abort ();
-}
-
-/* Return 1 if the operand is in volatile memory.  Note that during the
-   RTL generation phase, memory_operand does not return TRUE for
-   volatile memory references.  So this function allows us to
-   recognize volatile references where its safe.  */
-
-int
-volatile_mem_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != MEM)
-    return 0;
-
-  if (!MEM_VOLATILE_P (op))
-    return 0;
-
-  if (mode != GET_MODE (op))
-    return 0;
-
-  if (reload_completed)
-    return memory_operand (op, mode);
-
-  if (reload_in_progress)
-    return strict_memory_address_p (mode, XEXP (op, 0));
-
-  return memory_address_p (mode, XEXP (op, 0));
-}
-
-/* Return 1 if the operand is an offsettable memory address.  */
-
-int
-offsettable_addr_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return offsettable_address_p (reload_completed | reload_in_progress,
-				mode, op);
-}
-
-/* Return 1 if the operand is either an easy FP constant (see above) or
-   memory.  */
-
-int
-mem_or_easy_const_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return memory_operand (op, mode) || easy_fp_constant (op, mode);
-}
-
-/* Return 1 if the operand is either a non-special register or an item
-   that can be used as the operand of an SI add insn.  */
-
-int
-add_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  return (reg_or_short_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0));
-}
-
-/* Return 1 if OP is a constant but not a valid add_operand.  */
-
-int
-non_add_cint_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT
-	  && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000
-	  && (INTVAL (op) & 0xffff) != 0);
-}
-
-/* Return 1 if the operand is a non-special register or a constant that
-   can be used as the operand of an OR or XOR insn on the RS/6000.  */
-
-int
-logical_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return (gpc_reg_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT
-	      && ((INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0
-		  || (INTVAL (op) & 0xffff) == 0))
-	  || GET_CODE (op) == CONSTANT_P_RTX);
-}
-
-/* Return 1 if C is a constant that is not a logical operand (as
-   above).  */
-
-int
-non_logical_cint_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT
-	  && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) != 0
-	  && (INTVAL (op) & 0xffff) != 0);
-}
-
-/* Return 1 if C is a constant that can be encoded in a mask on the
-   RS/6000.  It is if there are no more than two 1->0 or 0->1 transitions.
-   Reject all ones and all zeros, since these should have been optimized
-   away and confuse the making of MB and ME.  */
-
-int
-mask_constant (c)
-     register HOST_WIDE_INT c;
-{
-  int i;
-  int last_bit_value;
-  int transitions = 0;
-
-  if (c == 0 || c == ~0)
-    return 0;
-
-  last_bit_value = c & 1;
-
-  for (i = 1; i < 32; i++)
-    if (((c >>= 1) & 1) != last_bit_value)
-      last_bit_value ^= 1, transitions++;
-
-  return transitions <= 2;
-}
-
-/* Return 1 if the operand is a constant that is a mask on the RS/6000. */
-
-int
-mask_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op));
-}
-
-/* Return 1 if the operand is a constant that is a PowerPC64 mask.
-   It is if there are no more than one 1->0 or 0->1 transitions.
-   Reject all ones and all zeros, since these should have been optimized
-   away and confuse the making of MB and ME.  */
-
-int
-mask64_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    {
-      HOST_WIDE_INT c = INTVAL (op);
-      int i;
-      int last_bit_value;
-      int transitions = 0;
-
-      if (c == 0 || c == ~0)
-	return 0;
-
-      last_bit_value = c & 1;
-
-      for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
-	if (((c >>= 1) & 1) != last_bit_value)
-	  last_bit_value ^= 1, transitions++;
-
-#if HOST_BITS_PER_WIDE_INT == 32
-      /* Consider CONST_INT sign-extended.  */
-      transitions += (last_bit_value != 1);
-#endif
-
-      return transitions <= 1;
-    }
-  else if (GET_CODE (op) == CONST_DOUBLE
-	   && (mode == VOIDmode || mode == DImode))
-    {
-      HOST_WIDE_INT low = CONST_DOUBLE_LOW (op);
-#if HOST_BITS_PER_WIDE_INT == 32
-      HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op);
-#endif
-      int i;
-      int last_bit_value;
-      int transitions = 0;
-
-      if ((low == 0
-#if HOST_BITS_PER_WIDE_INT == 32
-	  && high == 0
-#endif
-	   )
-	  || (low == ~0
-#if HOST_BITS_PER_WIDE_INT == 32
-	      && high == ~0
-#endif
-	      ))
-	return 0;
-
-      last_bit_value = low & 1;
-
-      for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
-	if (((low >>= 1) & 1) != last_bit_value)
-	  last_bit_value ^= 1, transitions++;
-
-#if HOST_BITS_PER_WIDE_INT == 32
-      if ((high & 1) != last_bit_value)
-	last_bit_value ^= 1, transitions++;
-
-      for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
-	if (((high >>= 1) & 1) != last_bit_value)
-	  last_bit_value ^= 1, transitions++;
-#endif
-
-      return transitions <= 1;
-    }
-  else
-    return 0;
-}
-
-/* Return 1 if the operand is either a non-special register or a constant
-   that can be used as the operand of a PowerPC64 logical AND insn.  */
-
-int
-and64_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  return (logical_operand (op, mode)
-	  || mask64_operand (op, mode));
-}
-
-/* Return 1 if the operand is either a non-special register or a
-   constant that can be used as the operand of an RS/6000 logical AND insn.  */
-
-int
-and_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  return (logical_operand (op, mode)
-	  || mask_operand (op, mode));
-}
-
-/* Return 1 if the operand is a general register or memory operand.  */
-
-int
-reg_or_mem_operand (op, mode)
-     register rtx op;
-     register enum machine_mode mode;
-{
-  return (gpc_reg_operand (op, mode)
-	  || memory_operand (op, mode)
-	  || volatile_mem_operand (op, mode));
-}
-
-/* Return 1 if the operand is a general register or memory operand without
-   pre-inc or pre_dec which produces invalid form of PowerPC lwa
-   instruction.  */
-
-int
-lwa_operand (op, mode)
-     register rtx op;
-     register enum machine_mode mode;
-{
-  rtx inner = op;
-
-  if (reload_completed && GET_CODE (inner) == SUBREG)
-    inner = SUBREG_REG (inner);
-    
-  return gpc_reg_operand (inner, mode)
-    || (memory_operand (inner, mode)
-	&& GET_CODE (XEXP (inner, 0)) != PRE_INC
-	&& GET_CODE (XEXP (inner, 0)) != PRE_DEC);
-}
-
-/* Return 1 if the operand, used inside a MEM, is a valid first argument
-   to CALL.  This is a SYMBOL_REF or a pseudo-register, which will be
-   forced to lr.  */
-
-int
-call_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (mode != VOIDmode && GET_MODE (op) != mode)
-    return 0;
-
-  return (GET_CODE (op) == SYMBOL_REF
-	  || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER));
-}
-
-
-/* Return 1 if the operand is a SYMBOL_REF for a function known to be in
-   this file.  */
-
-int
-current_file_function_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == SYMBOL_REF
-	  && (SYMBOL_REF_FLAG (op)
-	      || op == XEXP (DECL_RTL (current_function_decl), 0)));
-}
-
-
-/* Return 1 if this operand is a valid input for a move insn.  */
-
-int
-input_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  /* Memory is always valid.  */
-  if (memory_operand (op, mode))
-    return 1;
-
-  /* For floating-point, easy constants are valid.  */
-  if (GET_MODE_CLASS (mode) == MODE_FLOAT
-      && CONSTANT_P (op)
-      && easy_fp_constant (op, mode))
-    return 1;
-
-  /* Allow any integer constant.  */
-  if (GET_MODE_CLASS (mode) == MODE_INT
-      && (GET_CODE (op) == CONST_INT
-	  || GET_CODE (op) == CONSTANT_P_RTX
-	  || GET_CODE (op) == CONST_DOUBLE))
-    return 1;
-
-  /* For floating-point or multi-word mode, the only remaining valid type
-     is a register.  */
-  if (GET_MODE_CLASS (mode) == MODE_FLOAT
-      || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
-    return register_operand (op, mode);
-
-  /* The only cases left are integral modes one word or smaller (we
-     do not get called for MODE_CC values).  These can be in any
-     register.  */
-  if (register_operand (op, mode))
-    return 1;
-
-  /* A SYMBOL_REF referring to the TOC is valid.  */
-  if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
-    return 1;
-
-  /* Windows NT allows SYMBOL_REFs and LABEL_REFs against the TOC
-     directly in the instruction stream */
-  if (DEFAULT_ABI == ABI_NT
-      && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF))
-    return 1;
-
-  /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
-     to be valid.  */
-  if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-      && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
-      && small_data_operand (op, Pmode))
-    return 1;
-
-  return 0;
-}
-
-/* Return 1 for an operand in small memory on V.4/eabi */
-
-int
-small_data_operand (op, mode)
-     rtx op ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-#if TARGET_ELF
-  rtx sym_ref, const_part;
-
-  if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
-    return 0;
-
-  if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
-    return 0;
-
-  if (GET_CODE (op) == SYMBOL_REF)
-    sym_ref = op;
-
-  else if (GET_CODE (op) != CONST
-	   || GET_CODE (XEXP (op, 0)) != PLUS
-	   || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
-	   || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
-    return 0;
-
-  else
-    {
-      rtx sum = XEXP (op, 0);
-      HOST_WIDE_INT summand;
-
-      /* We have to be careful here, because it is the referenced address
-        that must be 32k from _SDA_BASE_, not just the symbol.  */
-      summand = INTVAL (XEXP (sum, 1));
-      if (summand < 0 || summand > g_switch_value)
-       return 0;
-
-      sym_ref = XEXP (sum, 0);
-    }
-
-  if (*XSTR (sym_ref, 0) != '@')
-    return 0;
-
-  return 1;
-
-#else
-  return 0;
-#endif
-}
-
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   For incoming args we set the number of arguments in the prototype large
-   so we never return a PARALLEL.  */
-
-void
-init_cumulative_args (cum, fntype, libname, incoming)
-     CUMULATIVE_ARGS *cum;
-     tree fntype;
-     rtx libname ATTRIBUTE_UNUSED;
-     int incoming;
-{
-  static CUMULATIVE_ARGS zero_cumulative;
-  enum rs6000_abi abi = DEFAULT_ABI;
-
-  *cum = zero_cumulative;
-  cum->words = 0;
-  cum->fregno = FP_ARG_MIN_REG;
-  cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
-  cum->call_cookie = CALL_NORMAL;
-
-  if (incoming)
-    {
-      cum->nargs_prototype = 1000;		/* don't return a PARALLEL */
-      if (abi == ABI_V4 || abi == ABI_SOLARIS)
-	cum->varargs_offset = RS6000_VARARGS_OFFSET;
-    }
-
-  else if (cum->prototype)
-    cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
-			    + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
-			       || RETURN_IN_MEMORY (TREE_TYPE (fntype))));
-
-  else
-    cum->nargs_prototype = 0;
-
-  cum->orig_nargs = cum->nargs_prototype;
-
-  /* Check for DLL import functions */
-  if (abi == ABI_NT
-      && fntype
-      && lookup_attribute ("dllimport", TYPE_ATTRIBUTES (fntype)))
-    cum->call_cookie = CALL_NT_DLLIMPORT;
-
-  /* Also check for longcall's */
-  else if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)))
-    cum->call_cookie = CALL_LONG;
-
-  if (TARGET_DEBUG_ARG)
-    {
-      fprintf (stderr, "\ninit_cumulative_args:");
-      if (fntype)
-	{
-	  tree ret_type = TREE_TYPE (fntype);
-	  fprintf (stderr, " ret code = %s,",
-		   tree_code_name[ (int)TREE_CODE (ret_type) ]);
-	}
-
-      if ((abi == ABI_V4 || abi == ABI_SOLARIS) && incoming)
-	fprintf (stderr, " varargs = %d, ", cum->varargs_offset);
-
-      if (cum->call_cookie & CALL_NT_DLLIMPORT)
-	fprintf (stderr, " dllimport,");
-
-      if (cum->call_cookie & CALL_LONG)
-	fprintf (stderr, " longcall,");
-
-      fprintf (stderr, " proto = %d, nargs = %d\n",
-	       cum->prototype, cum->nargs_prototype);
-    }
-}
-
-/* If defined, a C expression which determines whether, and in which
-   direction, to pad out an argument with extra space.  The value
-   should be of type `enum direction': either `upward' to pad above
-   the argument, `downward' to pad below, or `none' to inhibit
-   padding.
-
-   For the AIX ABI structs are always stored left shifted in their
-   argument slot.  */
-
-int
-function_arg_padding (mode, type)
-     enum machine_mode mode;
-     tree type;
-{
-  if (type != 0 && AGGREGATE_TYPE_P (type))
-    return (int)upward;
-
-  /* This is the default definition.  */
-  return (! BYTES_BIG_ENDIAN
-          ? (int)upward
-          : ((mode == BLKmode
-              ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
-                 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
-              : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
-             ? (int)downward : (int)upward));
-}
-
-/* If defined, a C expression that gives the alignment boundary, in bits,
-   of an argument with the specified mode and type.  If it is not defined, 
-   PARM_BOUNDARY is used for all arguments.
-   
-   Windows NT wants anything >= 8 bytes to be double word aligned.
-
-   V.4 wants long longs to be double word aligned.  */
-
-int
-function_arg_boundary (mode, type)
-     enum machine_mode mode;
-     tree type;
-{
-  if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && mode == DImode)
-    return 64;
-
-  if (DEFAULT_ABI != ABI_NT || TARGET_64BIT)
-    return PARM_BOUNDARY;
-
-  if (mode != BLKmode)
-    return (GET_MODE_SIZE (mode)) >= 8 ? 64 : 32;
-
-  return (int_size_in_bytes (type) >= 8) ? 64 : 32;
-}
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-void
-function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int align = (TARGET_32BIT && (cum->words & 1) != 0
-	       && function_arg_boundary (mode, type) == 64) ? 1 : 0;
-  cum->words += align;
-  cum->nargs_prototype--;
-
-  if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-    {
-      /* Long longs must not be split between registers and stack */
-      if ((GET_MODE_CLASS (mode) != MODE_FLOAT || TARGET_SOFT_FLOAT)
-	  && type && !AGGREGATE_TYPE_P (type)
-	  && cum->words < GP_ARG_NUM_REG
-	  && cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG)
-	{
-	  cum->words = GP_ARG_NUM_REG;
-	}
-
-      /* Aggregates get passed as pointers */
-      if (type && AGGREGATE_TYPE_P (type))
-	cum->words++;
-
-      /* Floats go in registers, & don't occupy space in the GP registers
-	 like they do for AIX unless software floating point.  */
-      else if (GET_MODE_CLASS (mode) == MODE_FLOAT
-	       && TARGET_HARD_FLOAT
-	       && cum->fregno <= FP_ARG_V4_MAX_REG)
-	cum->fregno++;
-
-      else
-	cum->words += RS6000_ARG_SIZE (mode, type, 1);
-    }
-  else
-    if (named)
-      {
-	cum->words += RS6000_ARG_SIZE (mode, type, named);
-	if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT)
-	  cum->fregno++;
-      }
-
-  if (TARGET_DEBUG_ARG)
-    fprintf (stderr,
-	     "function_adv: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d, align = %d\n",
-	     cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named, align);
-}
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-
-   On RS/6000 the first eight words of non-FP are normally in registers
-   and the rest are pushed.  Under AIX, the first 13 FP args are in registers.
-   Under V.4, the first 8 FP args are in registers.
-
-   If this is floating-point and no prototype is specified, we use
-   both an FP and integer register (or possibly FP reg and stack).  Library
-   functions (when TYPE is zero) always have the proper types for args,
-   so we can pass the FP value just in one register.  emit_library_function
-   doesn't support PARALLEL anyway.  */
-
-struct rtx_def *
-function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int align = (TARGET_32BIT && (cum->words & 1) != 0
-	       && function_arg_boundary (mode, type) == 64) ? 1 : 0;
-  int align_words = cum->words + align;
-
-  if (TARGET_DEBUG_ARG)
-    fprintf (stderr,
-	     "function_arg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d, align = %d\n",
-	     cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named, align);
-
-  /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4
-     uses to say fp args were passed in registers.  Assume that we don't need the
-     marker for software floating point, or compiler generated library calls.  */
-  if (mode == VOIDmode)
-    {
-      enum rs6000_abi abi = DEFAULT_ABI;
-
-      if ((abi == ABI_V4 || abi == ABI_SOLARIS)
-	  && TARGET_HARD_FLOAT
-	  && cum->nargs_prototype < 0
-	  && type && (cum->prototype || TARGET_NO_PROTOTYPE))
-	{
-	  return GEN_INT (cum->call_cookie
-			  | ((cum->fregno == FP_ARG_MIN_REG)
-			     ? CALL_V4_SET_FP_ARGS
-			     : CALL_V4_CLEAR_FP_ARGS));
-	}
-
-      return GEN_INT (cum->call_cookie);
-    }
-
-  if (!named)
-    {
-      if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
-	return NULL_RTX;
-    }
-
-  if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
-    return NULL_RTX;
-
-  if (USE_FP_FOR_ARG_P (*cum, mode, type))
-    {
-      if (DEFAULT_ABI == ABI_V4 /* V.4 never passes FP values in GP registers */
-	  || DEFAULT_ABI == ABI_SOLARIS
-	  || ! type
-	  || ((cum->nargs_prototype > 0)
-	      /* IBM AIX extended its linkage convention definition always to
-		 require FP args after register save area hole on the stack.  */
-	      && (DEFAULT_ABI != ABI_AIX
-		  || ! TARGET_XL_CALL
-		  || (align_words < GP_ARG_NUM_REG))))
-	return gen_rtx_REG (mode, cum->fregno);
-
-      return gen_rtx_PARALLEL (mode,
-		      gen_rtvec
-		      (2,
-		       gen_rtx_EXPR_LIST (VOIDmode,
-				((align_words >= GP_ARG_NUM_REG)
-				 ? NULL_RTX
-				 : (align_words
-				    + RS6000_ARG_SIZE (mode, type, named)
-				    > GP_ARG_NUM_REG
-				    /* If this is partially on the stack, then
-				       we only include the portion actually
-				       in registers here.  */
-				    ? gen_rtx_REG (SImode,
-					       GP_ARG_MIN_REG + align_words)
-				    : gen_rtx_REG (mode,
-					       GP_ARG_MIN_REG + align_words))),
-				const0_rtx),
-		       gen_rtx_EXPR_LIST (VOIDmode,
-				gen_rtx_REG (mode, cum->fregno),
-				const0_rtx)));
-    }
-
-  /* Long longs won't be split between register and stack;
-     FP arguments get passed on the stack if they didn't get a register.  */
-  else if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) &&
-	   (align_words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG
-	    || (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT)))
-    {
-      return NULL_RTX;
-    }
-
-  else if (align_words < GP_ARG_NUM_REG)
-    return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
-
-  return NULL_RTX;
-}
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-int
-function_arg_partial_nregs (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  if (! named)
-    return 0;
-
-  if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-    return 0;
-
-  if (USE_FP_FOR_ARG_P (*cum, mode, type))
-    {
-      if (cum->nargs_prototype >= 0)
-	return 0;
-    }
-
-  if (cum->words < GP_ARG_NUM_REG
-      && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type, named)))
-    {
-      int ret = GP_ARG_NUM_REG - cum->words;
-      if (ret && TARGET_DEBUG_ARG)
-	fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
-
-      return ret;
-    }
-
-  return 0;
-}
-
-/* A C expression that indicates when an argument must be passed by
-   reference.  If nonzero for an argument, a copy of that argument is
-   made in memory and a pointer to the argument is passed instead of
-   the argument itself.  The pointer is passed in whatever way is
-   appropriate for passing a pointer to that type.
-
-   Under V.4, structures and unions are passed by reference.  */
-
-int
-function_arg_pass_by_reference (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
-{
-  if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-      && type && AGGREGATE_TYPE_P (type))
-    {
-      if (TARGET_DEBUG_ARG)
-	fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
-
-      return 1;
-    }
-
-  return 0;
-}
-
-
-/* Perform any needed actions needed for a function that is receiving a
-   variable number of arguments. 
-
-   CUM is as above.
-
-   MODE and TYPE are the mode and type of the current parameter.
-
-   PRETEND_SIZE is a variable that should be set to the amount of stack
-   that must be pushed by the prolog to pretend that our caller pushed
-   it.
-
-   Normally, this macro will push all remaining incoming registers on the
-   stack and set PRETEND_SIZE to the length of the registers pushed.  */
-
-void
-setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int *pretend_size;
-     int no_rtl;
-
-{
-  rtx save_area = virtual_incoming_args_rtx;
-  int reg_size	= TARGET_32BIT ? 4 : 8;
-
-  if (TARGET_DEBUG_ARG)
-    fprintf (stderr,
-	     "setup_vararg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, no_rtl= %d\n",
-	     cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), no_rtl);
-
-  if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-    {
-      rs6000_sysv_varargs_p = 1;
-      if (! no_rtl)
-	save_area = plus_constant (frame_pointer_rtx, RS6000_VARARGS_OFFSET);
-    }
-  else
-    rs6000_sysv_varargs_p = 0;
-
-  if (cum->words < 8)
-    {
-      int first_reg_offset = cum->words;
-
-      if (MUST_PASS_IN_STACK (mode, type))
-	first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type, 1);
-
-      if (first_reg_offset > GP_ARG_NUM_REG)
-	first_reg_offset = GP_ARG_NUM_REG;
-
-      if (!no_rtl && first_reg_offset != GP_ARG_NUM_REG)
-	move_block_from_reg
-	  (GP_ARG_MIN_REG + first_reg_offset,
-	   gen_rtx_MEM (BLKmode,
-		    plus_constant (save_area, first_reg_offset * reg_size)),
-	   GP_ARG_NUM_REG - first_reg_offset,
-	   (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD);
-
-      *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD;
-    }
-
-  /* Save FP registers if needed.  */
-  if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && TARGET_HARD_FLOAT && !no_rtl)
-    {
-      int fregno     = cum->fregno;
-      int num_fp_reg = FP_ARG_V4_MAX_REG + 1 - fregno;
-
-      if (num_fp_reg >= 0)
-	{
-	  rtx cr1 = gen_rtx_REG (CCmode, 69);
-	  rtx lab = gen_label_rtx ();
-	  int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
-
-	  emit_jump_insn (gen_rtx_SET (VOIDmode,
-				   pc_rtx,
-				   gen_rtx_IF_THEN_ELSE (VOIDmode,
-					    gen_rtx_NE (VOIDmode, cr1, const0_rtx),
-					    gen_rtx_LABEL_REF (VOIDmode, lab),
-					    pc_rtx)));
-
-	  while ( num_fp_reg-- >= 0)
-	    {
-	      emit_move_insn (gen_rtx_MEM (DFmode, plus_constant (save_area, off)),
-			      gen_rtx_REG (DFmode, fregno++));
-	      off += 8;
-	    }
-
-	  emit_label (lab);
-	}
-    }
-}
-
-/* If defined, is a C expression that produces the machine-specific
-   code for a call to `__builtin_saveregs'.  This code will be moved
-   to the very beginning of the function, before any parameter access
-   are made.  The return value of this function should be an RTX that
-   contains the value to use as the return of `__builtin_saveregs'.
-
-   The argument ARGS is a `tree_list' containing the arguments that
-   were passed to `__builtin_saveregs'.
-
-   If this macro is not defined, the compiler will output an ordinary
-   call to the library function `__builtin_saveregs'.
-   
-   On the Power/PowerPC return the address of the area on the stack
-   used to hold arguments.  Under AIX, this includes the 8 word register
-   save area.  Under V.4 this does not.  */
-
-struct rtx_def *
-expand_builtin_saveregs (args)
-     tree args ATTRIBUTE_UNUSED;
-{
-  return virtual_incoming_args_rtx;
-}
-
-
-/* Generate a memory reference for expand_block_move, copying volatile,
-   and other bits from an original memory reference.  */
-
-static rtx
-expand_block_move_mem (mode, addr, orig_mem)
-     enum machine_mode mode;
-     rtx addr;
-     rtx orig_mem;
-{
-  rtx mem = gen_rtx_MEM (mode, addr);
-
-  RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (orig_mem);
-  MEM_COPY_ATTRIBUTES (mem, orig_mem);
-#ifdef MEM_UNALIGNED_P
-  MEM_UNALIGNED_P (mem) = MEM_UNALIGNED_P (orig_mem);
-#endif
-  return mem;
-}
-
-/* Expand a block move operation, and return 1 if successful.  Return 0
-   if we should let the compiler generate normal code.
-
-   operands[0] is the destination
-   operands[1] is the source
-   operands[2] is the length
-   operands[3] is the alignment */
-
-#define MAX_MOVE_REG 4
-
-int
-expand_block_move (operands)
-     rtx operands[];
-{
-  rtx orig_dest = operands[0];
-  rtx orig_src	= operands[1];
-  rtx bytes_rtx	= operands[2];
-  rtx align_rtx = operands[3];
-  int constp	= (GET_CODE (bytes_rtx) == CONST_INT);
-  int align	= XINT (align_rtx, 0);
-  int bytes;
-  int offset;
-  int num_reg;
-  int i;
-  rtx src_reg;
-  rtx dest_reg;
-  rtx src_addr;
-  rtx dest_addr;
-  rtx tmp_reg;
-  rtx stores[MAX_MOVE_REG];
-  int move_bytes;
-
-  /* If this is not a fixed size move, just call memcpy */
-  if (!constp)
-    return 0;
-
-  /* Anything to move? */
-  bytes = INTVAL (bytes_rtx);
-  if (bytes <= 0)
-    return 1;
-
-  /* Don't support real large moves.  If string instructions are not used,
-     then don't generate more than 8 loads.  */
-  if (TARGET_STRING)
-    {
-      if (bytes > 4*8)
-	return 0;
-    }
-  else if (!STRICT_ALIGNMENT)
-    {
-      if (bytes > 4*8)
-	return 0;
-    }
-  else if (bytes > 8*align)
-    return 0;
-
-  /* Move the address into scratch registers.  */
-  dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
-  src_reg  = copy_addr_to_reg (XEXP (orig_src,  0));
-
-  if (TARGET_STRING)	/* string instructions are available */
-    {
-      for ( ; bytes > 0; bytes -= move_bytes)
-	{
-	  if (bytes > 24		/* move up to 32 bytes at a time */
-	      && !fixed_regs[5]
-	      && !fixed_regs[6]
-	      && !fixed_regs[7]
-	      && !fixed_regs[8]
-	      && !fixed_regs[9]
-	      && !fixed_regs[10]
-	      && !fixed_regs[11]
-	      && !fixed_regs[12])
-	    {
-	      move_bytes = (bytes > 32) ? 32 : bytes;
-	      emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
-					    expand_block_move_mem (BLKmode, src_reg, orig_src),
-					    GEN_INT ((move_bytes == 32) ? 0 : move_bytes),
-					    align_rtx));
-	    }
-	  else if (bytes > 16	/* move up to 24 bytes at a time */
-		   && !fixed_regs[7]
-		   && !fixed_regs[8]
-		   && !fixed_regs[9]
-		   && !fixed_regs[10]
-		   && !fixed_regs[11]
-		   && !fixed_regs[12])
-	    {
-	      move_bytes = (bytes > 24) ? 24 : bytes;
-	      emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
-					    expand_block_move_mem (BLKmode, src_reg, orig_src),
-					    GEN_INT (move_bytes),
-					    align_rtx));
-	    }
-	  else if (bytes > 8	/* move up to 16 bytes at a time */
-		   && !fixed_regs[9]
-		   && !fixed_regs[10]
-		   && !fixed_regs[11]
-		   && !fixed_regs[12])
-	    {
-	      move_bytes = (bytes > 16) ? 16 : bytes;
-	      emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
-					    expand_block_move_mem (BLKmode, src_reg, orig_src),
-					    GEN_INT (move_bytes),
-					    align_rtx));
-	    }
-	  else if (bytes > 4 && !TARGET_64BIT)
-	    {			/* move up to 8 bytes at a time */
-	      move_bytes = (bytes > 8) ? 8 : bytes;
-	      emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
-					    expand_block_move_mem (BLKmode, src_reg, orig_src),
-					    GEN_INT (move_bytes),
-					    align_rtx));
-	    }
-	  else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
-	    {			/* move 4 bytes */
-	      move_bytes = 4;
-	      tmp_reg = gen_reg_rtx (SImode);
-	      emit_move_insn (tmp_reg, expand_block_move_mem (SImode, src_reg, orig_src));
-	      emit_move_insn (expand_block_move_mem (SImode, dest_reg, orig_dest), tmp_reg);
-	    }
-	  else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT))
-	    {			/* move 2 bytes */
-	      move_bytes = 2;
-	      tmp_reg = gen_reg_rtx (HImode);
-	      emit_move_insn (tmp_reg, expand_block_move_mem (HImode, src_reg, orig_src));
-	      emit_move_insn (expand_block_move_mem (HImode, dest_reg, orig_dest), tmp_reg);
-	    }
-	  else if (bytes == 1)	/* move 1 byte */
-	    {
-	      move_bytes = 1;
-	      tmp_reg = gen_reg_rtx (QImode);
-	      emit_move_insn (tmp_reg, expand_block_move_mem (QImode, src_reg, orig_src));
-	      emit_move_insn (expand_block_move_mem (QImode, dest_reg, orig_dest), tmp_reg);
-	    }
-	  else
-	    {			/* move up to 4 bytes at a time */
-	      move_bytes = (bytes > 4) ? 4 : bytes;
-	      emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
-					    expand_block_move_mem (BLKmode, src_reg, orig_src),
-					    GEN_INT (move_bytes),
-					    align_rtx));
-	    }
-
-	  if (bytes > move_bytes)
-	    {
-	      emit_insn (gen_addsi3 (src_reg, src_reg, GEN_INT (move_bytes)));
-	      emit_insn (gen_addsi3 (dest_reg, dest_reg, GEN_INT (move_bytes)));
-	    }
-	}
-    }
-
-  else			/* string instructions not available */
-    {
-      num_reg = offset = 0;
-      for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
-	{
-	  /* Calculate the correct offset for src/dest */
-	  if (offset == 0)
-	    {
-	      src_addr  = src_reg;
-	      dest_addr = dest_reg;
-	    }
-	  else
-	    {
-	      src_addr  = gen_rtx_PLUS (Pmode, src_reg,  GEN_INT (offset));
-	      dest_addr = gen_rtx_PLUS (Pmode, dest_reg, GEN_INT (offset));
-	    }
-
-	  /* Generate the appropriate load and store, saving the stores for later */
-	  if (bytes >= 8 && TARGET_64BIT && (align >= 8 || !STRICT_ALIGNMENT))
-	    {
-	      move_bytes = 8;
-	      tmp_reg = gen_reg_rtx (DImode);
-	      emit_insn (gen_movdi (tmp_reg, expand_block_move_mem (DImode, src_addr, orig_src)));
-	      stores[ num_reg++ ] = gen_movdi (expand_block_move_mem (DImode, dest_addr, orig_dest), tmp_reg);
-	    }
-	  else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
-	    {
-	      move_bytes = 4;
-	      tmp_reg = gen_reg_rtx (SImode);
-	      emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (SImode, src_addr, orig_src)));
-	      stores[ num_reg++ ] = gen_movsi (expand_block_move_mem (SImode, dest_addr, orig_dest), tmp_reg);
-	    }
-	  else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT))
-	    {
-	      move_bytes = 2;
-	      tmp_reg = gen_reg_rtx (HImode);
-	      emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (HImode, src_addr, orig_src)));
-	      stores[ num_reg++ ] = gen_movhi (expand_block_move_mem (HImode, dest_addr, orig_dest), tmp_reg);
-	    }
-	  else
-	    {
-	      move_bytes = 1;
-	      tmp_reg = gen_reg_rtx (QImode);
-	      emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (QImode, src_addr, orig_src)));
-	      stores[ num_reg++ ] = gen_movqi (expand_block_move_mem (QImode, dest_addr, orig_dest), tmp_reg);
-	    }
-
-	  if (num_reg >= MAX_MOVE_REG)
-	    {
-	      for (i = 0; i < num_reg; i++)
-		emit_insn (stores[i]);
-	      num_reg = 0;
-	    }
-	}
-
-      for (i = 0; i < num_reg; i++)
-	emit_insn (stores[i]);
-    }
-
-  return 1;
-}
-
-
-/* Return 1 if OP is a load multiple operation.  It is known to be a
-   PARALLEL and the first section will be tested.  */
-
-int
-load_multiple_operation (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  int count = XVECLEN (op, 0);
-  int dest_regno;
-  rtx src_addr;
-  int i;
-
-  /* Perform a quick check so we don't blow up below.  */
-  if (count <= 1
-      || GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
-      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
-    return 0;
-
-  dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
-  src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
-
-  for (i = 1; i < count; i++)
-    {
-      rtx elt = XVECEXP (op, 0, i);
-
-      if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_DEST (elt)) != REG
-	  || GET_MODE (SET_DEST (elt)) != SImode
-	  || REGNO (SET_DEST (elt)) != dest_regno + i
-	  || GET_CODE (SET_SRC (elt)) != MEM
-	  || GET_MODE (SET_SRC (elt)) != SImode
-	  || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
-	  || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
-	  || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
-	  || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
-	return 0;
-    }
-
-  return 1;
-}
-
-/* Similar, but tests for store multiple.  Here, the second vector element
-   is a CLOBBER.  It will be tested later.  */
-
-int
-store_multiple_operation (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  int count = XVECLEN (op, 0) - 1;
-  int src_regno;
-  rtx dest_addr;
-  int i;
-
-  /* Perform a quick check so we don't blow up below.  */
-  if (count <= 1
-      || GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
-      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
-    return 0;
-
-  src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
-  dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
-
-  for (i = 1; i < count; i++)
-    {
-      rtx elt = XVECEXP (op, 0, i + 1);
-
-      if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_SRC (elt)) != REG
-	  || GET_MODE (SET_SRC (elt)) != SImode
-	  || REGNO (SET_SRC (elt)) != src_regno + i
-	  || GET_CODE (SET_DEST (elt)) != MEM
-	  || GET_MODE (SET_DEST (elt)) != SImode
-	  || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
-	  || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
-	  || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
-	  || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
-	return 0;
-    }
-
-  return 1;
-}
-
-/* Return 1 if OP is a comparison operation that is valid for a branch insn.
-   We only check the opcode against the mode of the CC value here.  */
-
-int
-branch_comparison_operator (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  enum rtx_code code = GET_CODE (op);
-  enum machine_mode cc_mode;
-
-  if (GET_RTX_CLASS (code) != '<')
-    return 0;
-
-  cc_mode = GET_MODE (XEXP (op, 0));
-  if (GET_MODE_CLASS (cc_mode) != MODE_CC)
-    return 0;
-
-  if ((code == GT || code == LT || code == GE || code == LE)
-      && cc_mode == CCUNSmode)
-    return 0;
-
-  if ((code == GTU || code == LTU || code == GEU || code == LEU)
-      && (cc_mode != CCUNSmode))
-    return 0;
-
-  return 1;
-}
-
-/* Return 1 if OP is a comparison operation that is valid for an scc insn.
-   We check the opcode against the mode of the CC value and disallow EQ or
-   NE comparisons for integers.  */
-
-int
-scc_comparison_operator (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  enum rtx_code code = GET_CODE (op);
-  enum machine_mode cc_mode;
-
-  if (GET_MODE (op) != mode && mode != VOIDmode)
-    return 0;
-
-  if (GET_RTX_CLASS (code) != '<')
-    return 0;
-
-  cc_mode = GET_MODE (XEXP (op, 0));
-  if (GET_MODE_CLASS (cc_mode) != MODE_CC)
-    return 0;
-
-  if (code == NE && cc_mode != CCFPmode)
-    return 0;
-
-  if ((code == GT || code == LT || code == GE || code == LE)
-      && cc_mode == CCUNSmode)
-    return 0;
-
-  if ((code == GTU || code == LTU || code == GEU || code == LEU)
-      && (cc_mode != CCUNSmode))
-    return 0;
-
-  if (cc_mode == CCEQmode && code != EQ && code != NE)
-    return 0;
-
-  return 1;
-}
-
-int
-trap_comparison_operator (op, mode)
-    rtx op;
-    enum machine_mode mode;
-{
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-  return (GET_RTX_CLASS (GET_CODE (op)) == '<'
-          || GET_CODE (op) == EQ || GET_CODE (op) == NE);
-}
-
-/* Return 1 if ANDOP is a mask that has no bits on that are not in the
-   mask required to convert the result of a rotate insn into a shift
-   left insn of SHIFTOP bits.  Both are known to be CONST_INT.  */
-
-int
-includes_lshift_p (shiftop, andop)
-     register rtx shiftop;
-     register rtx andop;
-{
-  int shift_mask = (~0 << INTVAL (shiftop));
-
-  return (INTVAL (andop) & ~shift_mask) == 0;
-}
-
-/* Similar, but for right shift.  */
-
-int
-includes_rshift_p (shiftop, andop)
-     register rtx shiftop;
-     register rtx andop;
-{
-  unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
-
-  shift_mask >>= INTVAL (shiftop);
-
-  return (INTVAL (andop) & ~ shift_mask) == 0;
-}
-
-/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
-   for lfq and stfq insns.
-
-   Note reg1 and reg2 *must* be hard registers.  To be sure we will
-   abort if we are passed pseudo registers.  */
-
-int
-registers_ok_for_quad_peep (reg1, reg2)
-     rtx reg1, reg2;
-{
-  /* We might have been passed a SUBREG.  */
-  if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 
-    return 0;
-
-  return (REGNO (reg1) == REGNO (reg2) - 1);
-}
-
-/* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.  addr1 and
-   addr2 must be in consecutive memory locations (addr2 == addr1 + 8).  */
-
-int
-addrs_ok_for_quad_peep (addr1, addr2)
-     register rtx addr1;
-     register rtx addr2;
-{
-  int reg1;
-  int offset1;
-
-  /* Extract an offset (if used) from the first addr.  */
-  if (GET_CODE (addr1) == PLUS)
-    {
-      /* If not a REG, return zero.  */
-      if (GET_CODE (XEXP (addr1, 0)) != REG)
-	return 0;
-      else
-	{
-          reg1 = REGNO (XEXP (addr1, 0));
-	  /* The offset must be constant!  */
-	  if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
-            return 0;
-          offset1 = INTVAL (XEXP (addr1, 1));
-	}
-    }
-  else if (GET_CODE (addr1) != REG)
-    return 0;
-  else
-    {
-      reg1 = REGNO (addr1);
-      /* This was a simple (mem (reg)) expression.  Offset is 0.  */
-      offset1 = 0;
-    }
-
-  /* Make sure the second address is a (mem (plus (reg) (const_int).  */
-  if (GET_CODE (addr2) != PLUS)
-    return 0;
-
-  if (GET_CODE (XEXP (addr2, 0)) != REG
-      || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
-    return 0;
-
-  if (reg1 != REGNO (XEXP (addr2, 0)))
-    return 0;
-
-  /* The offset for the second addr must be 8 more than the first addr.  */
-  if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
-    return 0;
-
-  /* All the tests passed.  addr1 and addr2 are valid for lfq or stfq
-     instructions.  */
-  return 1;
-}
-
-/* Return the register class of a scratch register needed to copy IN into
-   or out of a register in CLASS in MODE.  If it can be done directly,
-   NO_REGS is returned.  */
-
-enum reg_class
-secondary_reload_class (class, mode, in)
-     enum reg_class class;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     rtx in;
-{
-  int regno;
-
-  /* We can not copy a symbolic operand directly into anything other than
-     BASE_REGS for TARGET_ELF.  So indicate that a register from BASE_REGS
-     is needed as an intermediate register.  */
-  if (TARGET_ELF
-      && class != BASE_REGS
-      && (GET_CODE (in) == SYMBOL_REF
-	  || GET_CODE (in) == HIGH
-	  || GET_CODE (in) == LABEL_REF
-	  || GET_CODE (in) == CONST))
-    return BASE_REGS;
-
-  if (GET_CODE (in) == REG)
-    {
-      regno = REGNO (in);
-      if (regno >= FIRST_PSEUDO_REGISTER)
-	{
-	  regno = true_regnum (in);
-	  if (regno >= FIRST_PSEUDO_REGISTER)
-	    regno = -1;
-	}
-    }
-  else if (GET_CODE (in) == SUBREG)
-    {
-      regno = true_regnum (in);
-      if (regno >= FIRST_PSEUDO_REGISTER)
-	regno = -1;
-    }
-  else
-    regno = -1;
-
-  /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
-     into anything.  */
-  if (class == GENERAL_REGS || class == BASE_REGS
-      || (regno >= 0 && INT_REGNO_P (regno)))
-    return NO_REGS;
-
-  /* Constants, memory, and FP registers can go into FP registers.  */
-  if ((regno == -1 || FP_REGNO_P (regno))
-      && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
-    return NO_REGS;
-
-  /* We can copy among the CR registers.  */
-  if ((class == CR_REGS || class == CR0_REGS)
-      && regno >= 0 && CR_REGNO_P (regno))
-    return NO_REGS;
-
-  /* Otherwise, we need GENERAL_REGS.  */
-  return GENERAL_REGS;
-}
-
-/* Given a comparison operation, return the bit number in CCR to test.  We
-   know this is a valid comparison.  
-
-   SCC_P is 1 if this is for an scc.  That means that %D will have been
-   used instead of %C, so the bits will be in different places.
-
-   Return -1 if OP isn't a valid comparison for some reason.  */
-
-int
-ccr_bit (op, scc_p)
-     register rtx op;
-     int scc_p;
-{
-  /* CYGNUS LOCAL -- meissner/branch prediction */
-  enum rtx_code code = GET_CODE (op);
-  enum machine_mode cc_mode;
-  int cc_regnum;
-  int base_bit;
-  rtx reg;
-
-  if (GET_RTX_CLASS (code) != '<')
-    return -1;
-
-  reg = XEXP (op, 0);
-
-  if (GET_CODE (reg) == EXPECT)
-    reg = XEXP (reg, 0);
-
-  if (GET_CODE (reg) != REG
-      || REGNO (reg) < 68
-      || REGNO (reg) > 75)
-    abort ();
-
-  cc_mode = GET_MODE (reg);
-  cc_regnum = REGNO (reg);
-  base_bit = 4 * (cc_regnum - 68);
-  /* END CYGNUS LOCAL -- meissner/branch prediction */
-
-  /* In CCEQmode cases we have made sure that the result is always in the
-     third bit of the CR field.  */
-
-  if (cc_mode == CCEQmode)
-    return base_bit + 3;
-
-  switch (code)
-    {
-    case NE:
-      return scc_p ? base_bit + 3 : base_bit + 2;
-    case EQ:
-      return base_bit + 2;
-    case GT:  case GTU:
-      return base_bit + 1;
-    case LT:  case LTU:
-      return base_bit;
-
-    case GE:  case GEU:
-      /* If floating-point, we will have done a cror to put the bit in the
-	 unordered position.  So test that bit.  For integer, this is ! LT
-	 unless this is an scc insn.  */
-      return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit;
-
-    case LE:  case LEU:
-      return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1;
-
-    default:
-      abort ();
-    }
-}
-
-/* Return the GOT register, creating it if needed.  */
-
-struct rtx_def *
-rs6000_got_register (value)
-     rtx value;
-{
-  if (!current_function_uses_pic_offset_table || !pic_offset_table_rtx)
-    {
-      if (reload_in_progress || reload_completed)
-	fatal_insn ("internal error -- needed new GOT register during reload phase to load:", value);
-
-      current_function_uses_pic_offset_table = 1;
-      pic_offset_table_rtx = gen_rtx_REG (Pmode, GOT_TOC_REGNUM);
-    }
-
-  return pic_offset_table_rtx;
-}
-
-
-/* Replace all occurrences of register FROM with an new pseudo register in an insn X.
-   Store the pseudo register used in REG.
-   This is only safe during FINALIZE_PIC, since the registers haven't been setup
-   yet.  */
-
-static rtx
-rs6000_replace_regno (x, from, reg)
-     rtx x;
-     int from;
-     rtx *reg;
-{
-  register int i, j;
-  register char *fmt;
-
-  /* Allow this function to make replacements in EXPR_LISTs.  */
-  if (!x)
-    return x;
-
-  switch (GET_CODE (x))
-    {
-    case SCRATCH:
-    case PC:
-    case CC0:
-    case CONST_INT:
-    case CONST_DOUBLE:
-    case CONST:
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return x;
-
-    case REG:
-      if (REGNO (x) == from)
-	{
-	  if (! *reg)
-	    *reg = pic_offset_table_rtx = gen_reg_rtx (Pmode);
-
-	  return *reg;
-	}
-
-      return x;
-
-    default:
-      break;
-    }
-
-  fmt = GET_RTX_FORMAT (GET_CODE (x));
-  for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
-    {
-      if (fmt[i] == 'e')
-	XEXP (x, i) = rs6000_replace_regno (XEXP (x, i), from, reg);
-      else if (fmt[i] == 'E')
-	for (j = XVECLEN (x, i) - 1; j >= 0; j--)
-	  XVECEXP (x, i, j) = rs6000_replace_regno (XVECEXP (x, i, j), from, reg);
-    }
-
-  return x;
-}  
-
-
-/* By generating position-independent code, when two different
-   programs (A and B) share a common library (libC.a), the text of
-   the library can be shared whether or not the library is linked at
-   the same address for both programs.  In some of these
-   environments, position-independent code requires not only the use
-   of different addressing modes, but also special code to enable the
-   use of these addressing modes.
-
-   The `FINALIZE_PIC' macro serves as a hook to emit these special
-   codes once the function is being compiled into assembly code, but
-   not before.  (It is not done before, because in the case of
-   compiling an inline function, it would lead to multiple PIC
-   prologues being included in functions which used inline functions
-   and were compiled to assembly language.)  */
-
-void
-rs6000_finalize_pic ()
-{
-  /* Loop through all of the insns, replacing the special GOT_TOC_REGNUM
-     with an appropriate pseudo register.  If we find we need GOT/TOC,
-     add the appropriate init code.  */
-  if (flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
-    {
-      rtx insn = get_insns ();
-      rtx reg = NULL_RTX;
-      rtx first_insn;
-      rtx last_insn = NULL_RTX;
-
-      if (GET_CODE (insn) == NOTE)
-	insn = next_nonnote_insn (insn);
-
-      first_insn = insn;
-      for ( ; insn != NULL_RTX; insn = NEXT_INSN (insn))
-	{
-	  if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
-	    {
-	      PATTERN (insn) = rs6000_replace_regno (PATTERN (insn),
-						     GOT_TOC_REGNUM,
-						     &reg);
-
-	      if (REG_NOTES (insn))
-		REG_NOTES (insn) = rs6000_replace_regno (REG_NOTES (insn),
-							 GOT_TOC_REGNUM,
-							 &reg);
-	    }
-
-	  if (GET_CODE (insn) != NOTE)
-	    last_insn = insn;
-	}
-
-      if (reg)
-	{
-	  rtx init = gen_init_v4_pic (reg);
-	  emit_insn_before (init, first_insn);
-	  if (!optimize && last_insn)
-	    emit_insn_after (gen_rtx_USE (VOIDmode, reg), last_insn);
-	}
-    }
-}
-
-
-/* Search for any occurrence of the GOT_TOC register marker that should
-   have been eliminated, but may have crept back in.  */
-
-void
-rs6000_reorg (insn)
-     rtx insn;
-{
-  if (flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
-    {
-      rtx got_reg = gen_rtx_REG (Pmode, GOT_TOC_REGNUM);
-      for ( ; insn != NULL_RTX; insn = NEXT_INSN (insn))
-	if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
-	    && reg_mentioned_p (got_reg, PATTERN (insn)))
-	  fatal_insn ("GOT/TOC register marker not removed:", PATTERN (insn));
-    }
-}
-
-
-/* Define the structure for the machine field in struct function.  */
-struct machine_function
-{
-  int sysv_varargs_p;
-  int save_toc_p;
-  int fpmem_size;
-  int fpmem_offset;
-  rtx pic_offset_table_rtx;
-};
-
-/* Functions to save and restore rs6000_fpmem_size.
-   These will be called, via pointer variables,
-   from push_function_context and pop_function_context.  */
-
-void
-rs6000_save_machine_status (p)
-     struct function *p;
-{
-  struct machine_function *machine =
-    (struct machine_function *) xmalloc (sizeof (struct machine_function));
-
-  p->machine = machine;
-  machine->sysv_varargs_p = rs6000_sysv_varargs_p;
-  machine->fpmem_size     = rs6000_fpmem_size;
-  machine->fpmem_offset   = rs6000_fpmem_offset;
-  machine->pic_offset_table_rtx = pic_offset_table_rtx;
-}
-
-void
-rs6000_restore_machine_status (p)
-     struct function *p;
-{
-  struct machine_function *machine = p->machine;
-
-  rs6000_sysv_varargs_p = machine->sysv_varargs_p;
-  rs6000_fpmem_size     = machine->fpmem_size;
-  rs6000_fpmem_offset   = machine->fpmem_offset;
-  pic_offset_table_rtx  = machine->pic_offset_table_rtx;
-
-  free (machine);
-  p->machine = (struct machine_function *)0;
-}
-
-/* Do anything needed before RTL is emitted for each function.  */
-
-void
-rs6000_init_expanders ()
-{
-  /* Reset varargs and save TOC indicator */
-  rs6000_sysv_varargs_p = 0;
-  rs6000_fpmem_size = 0;
-  rs6000_fpmem_offset = 0;
-  pic_offset_table_rtx = (rtx)0;
-
-  /* Arrange to save and restore machine status around nested functions.  */
-  save_machine_status = rs6000_save_machine_status;
-  restore_machine_status = rs6000_restore_machine_status;
-}
-
-
-/* Print an operand.  Recognize special options, documented below.  */
-
-#if TARGET_ELF
-#define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
-#define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
-#else
-#define SMALL_DATA_RELOC "sda21"
-#define SMALL_DATA_REG 0
-#endif
-
-void
-print_operand (file, x, code)
-    FILE *file;
-    rtx x;
-    char code;
-{
-  int i;
-  /* CYGNUS LOCAL -- meissner/branch prediction */
-  int succeed;
-  /* END CYGNUS LOCAL -- meissner/branch prediction */
-  HOST_WIDE_INT val;
-
-  /* These macros test for integers and extract the low-order bits.  */
-#define INT_P(X)  \
-((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE)	\
- && GET_MODE (X) == VOIDmode)
-
-#define INT_LOWPART(X) \
-  (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
-
-  switch (code)
-    {
-    case '.':
-      /* Write out an instruction after the call which may be replaced
-	 with glue code by the loader.  This depends on the AIX version.  */
-      asm_fprintf (file, RS6000_CALL_GLUE);
-      return;
-
-    case '*':
-      /* Write the register number of the TOC register.  */
-      fputs (TARGET_MINIMAL_TOC ? reg_names[30] : reg_names[2], file);
-      return;
-
-    case '$':
-      /* Write out either a '.' or '$' for the current location, depending
-	 on whether this is Solaris or not.  */
-      putc ((DEFAULT_ABI == ABI_SOLARIS) ? '.' : '$', file);
-      return;
-
-    case 'A':
-      /* If X is a constant integer whose low-order 5 bits are zero,
-	 write 'l'.  Otherwise, write 'r'.  This is a kludge to fix a bug
-	 in the AIX assembler where "sri" with a zero shift count
-	 write a trash instruction.  */
-      if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
-	putc ('l', file);
-      else
-	putc ('r', file);
-      return;
-
-    case 'b':
-      /* Low-order 16 bits of constant, unsigned.  */
-      if (! INT_P (x))
-	output_operand_lossage ("invalid %%b value");
-
-      fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
-      return;
-
-    case 'B':
-      /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
-	 for 64-bit mask direction.  */
-      putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
-      return;
-
-    case 'C':
-      /* This is an optional cror needed for LE or GE floating-point
-	 comparisons.  Otherwise write nothing.  */
-      if ((GET_CODE (x) == LE || GET_CODE (x) == GE)
-	  && GET_MODE (XEXP (x, 0)) == CCFPmode)
-	{
-	  int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
-
-	  fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
-		   base_bit + 2, base_bit + (GET_CODE (x) == GE));
-	}
-      return;
-
-    case 'D':
-      /* Similar, except that this is for an scc, so we must be able to
-	 encode the test in a single bit that is one.  We do the above
-	 for any LE, GE, GEU, or LEU and invert the bit for NE.  */
-      if (GET_CODE (x) == LE || GET_CODE (x) == GE
-	  || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
-	{
-	  int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
-
-	  fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
-		   base_bit + 2,
-		   base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
-	}
-
-      else if (GET_CODE (x) == NE)
-	{
-	  int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
-
-	  fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
-		   base_bit + 2, base_bit + 2);
-	}
-      return;
-
-    case 'E':
-      /* X is a CR register.  Print the number of the third bit of the CR */
-      if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
-	output_operand_lossage ("invalid %%E value");
-
-      fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3);
-      return;
-
-    case 'f':
-      /* X is a CR register.  Print the shift count needed to move it
-	 to the high-order four bits.  */
-      if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
-	output_operand_lossage ("invalid %%f value");
-      else
-	fprintf (file, "%d", 4 * (REGNO (x) - 68));
-      return;
-
-    case 'F':
-      /* Similar, but print the count for the rotate in the opposite
-	 direction.  */
-      if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
-	output_operand_lossage ("invalid %%F value");
-      else
-	fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68));
-      return;
-
-    case 'G':
-      /* X is a constant integer.  If it is negative, print "m",
-	 otherwise print "z".  This is to make a aze or ame insn.  */
-      if (GET_CODE (x) != CONST_INT)
-	output_operand_lossage ("invalid %%G value");
-      else if (INTVAL (x) >= 0)
-	putc ('z', file);
-      else
-	putc ('m', file);
-      return;
-	
-    case 'h':
-      /* If constant, output low-order five bits.  Otherwise,
-	 write normally. */
-      if (INT_P (x))
-	fprintf (file, "%d", INT_LOWPART (x) & 31);
-      else
-	print_operand (file, x, 0);
-      return;
-
-    case 'H':
-      /* If constant, output low-order six bits.  Otherwise,
-	 write normally. */
-      if (INT_P (x))
-	fprintf (file, "%d", INT_LOWPART (x) & 63);
-      else
-	print_operand (file, x, 0);
-      return;
-
-    case 'I':
-      /* Print `i' if this is a constant, else nothing.  */
-      if (INT_P (x))
-	putc ('i', file);
-      return;
-
-    case 'j':
-      /* Write the bit number in CCR for jump.  */
-      i = ccr_bit (x, 0);
-      if (i == -1)
-	output_operand_lossage ("invalid %%j code");
-      else
-	fprintf (file, "%d", i);
-      return;
-
-    case 'J':
-      /* Similar, but add one for shift count in rlinm for scc and pass
-	 scc flag to `ccr_bit'.  */
-      i = ccr_bit (x, 1);
-      if (i == -1)
-	output_operand_lossage ("invalid %%J code");
-      else
-	/* If we want bit 31, write a shift count of zero, not 32.  */
-	fprintf (file, "%d", i == 31 ? 0 : i + 1);
-      return;
-
-    case 'k':
-      /* X must be a constant.  Write the 1's complement of the
-	 constant.  */
-      if (! INT_P (x))
-	output_operand_lossage ("invalid %%k value");
-
-      fprintf (file, "%d", ~ INT_LOWPART (x));
-      return;
-
-    case 'L':
-      /* Write second word of DImode or DFmode reference.  Works on register
-	 or non-indexed memory only.  */
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", reg_names[REGNO (x) + 1]);
-      else if (GET_CODE (x) == MEM)
-	{
-	  /* Handle possible auto-increment.  Since it is pre-increment and
-	     we have already done it, we can just use an offset of word.  */
-	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
-	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
-	    output_address (plus_constant (XEXP (XEXP (x, 0), 0),
-					   UNITS_PER_WORD));
-	  else
-	    output_address (plus_constant (XEXP (x, 0), UNITS_PER_WORD));
-	  if (small_data_operand (x, GET_MODE (x)))
-	    fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
-		     reg_names[SMALL_DATA_REG]);
-	}
-      return;
-			    
-    case 'm':
-      /* MB value for a mask operand.  */
-      if (! mask_operand (x, VOIDmode))
-	output_operand_lossage ("invalid %%m value");
-
-      val = INT_LOWPART (x);
-
-      /* If the high bit is set and the low bit is not, the value is zero.
-	 If the high bit is zero, the value is the first 1 bit we find from
-	 the left.  */
-      if ((val & 0x80000000) && ((val & 1) == 0))
-	{
-	  putc ('0', file);
-	  return;
-	}
-      else if ((val & 0x80000000) == 0)
-	{
-	  for (i = 1; i < 32; i++)
-	    if ((val <<= 1) & 0x80000000)
-	      break;
-	  fprintf (file, "%d", i);
-	  return;
-	}
-	  
-      /* Otherwise, look for the first 0 bit from the right.  The result is its
-	 number plus 1. We know the low-order bit is one.  */
-      for (i = 0; i < 32; i++)
-	if (((val >>= 1) & 1) == 0)
-	  break;
-
-      /* If we ended in ...01, i would be 0.  The correct value is 31, so
-	 we want 31 - i.  */
-      fprintf (file, "%d", 31 - i);
-      return;
-
-    case 'M':
-      /* ME value for a mask operand.  */
-      if (! mask_operand (x, VOIDmode))
-	output_operand_lossage ("invalid %%M value");
-
-      val = INT_LOWPART (x);
-
-      /* If the low bit is set and the high bit is not, the value is 31.
-	 If the low bit is zero, the value is the first 1 bit we find from
-	 the right.  */
-      if ((val & 1) && ((val & 0x80000000) == 0))
-	{
-	  fputs ("31", file);
-	  return;
-	}
-      else if ((val & 1) == 0)
-	{
-	  for (i = 0; i < 32; i++)
-	    if ((val >>= 1) & 1)
-	      break;
-
-	  /* If we had ....10, i would be 0.  The result should be
-	     30, so we need 30 - i.  */
-	  fprintf (file, "%d", 30 - i);
-	  return;
-	}
-	  
-      /* Otherwise, look for the first 0 bit from the left.  The result is its
-	 number minus 1. We know the high-order bit is one.  */
-      for (i = 0; i < 32; i++)
-	if (((val <<= 1) & 0x80000000) == 0)
-	  break;
-
-      fprintf (file, "%d", i);
-      return;
-
-    case 'N':
-      /* Write the number of elements in the vector times 4.  */
-      if (GET_CODE (x) != PARALLEL)
-	output_operand_lossage ("invalid %%N value");
-
-      fprintf (file, "%d", XVECLEN (x, 0) * 4);
-      return;
-
-    case 'O':
-      /* Similar, but subtract 1 first.  */
-      if (GET_CODE (x) != PARALLEL)
-	output_operand_lossage ("invalid %%O value");
-
-      fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
-      return;
-
-    case 'p':
-      /* X is a CONST_INT that is a power of two.  Output the logarithm.  */
-      if (! INT_P (x)
-	  || (i = exact_log2 (INT_LOWPART (x))) < 0)
-	output_operand_lossage ("invalid %%p value");
-
-      fprintf (file, "%d", i);
-      return;
-
-    case 'P':
-      /* The operand must be an indirect memory reference.  The result
-	 is the register number. */
-      if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
-	  || REGNO (XEXP (x, 0)) >= 32)
-	output_operand_lossage ("invalid %%P value");
-
-      fprintf (file, "%d", REGNO (XEXP (x, 0)));
-      return;
-
-      /* CYGNUS LOCAL -- meissner/branch prediction */
-    case 'q':
-    case 'Q':
-      /* Write -/+ depending on whether a branch is expected to succeed */
-      succeed = (code == 'Q');
-      if (x != const0_rtx)
-	succeed = !succeed;
-
-      putc ((succeed) ? '+' : '-', file);
-      return;
-      /* END CYGNUS LOCAL -- meissner/branch prediction */
-
-    case 'R':
-      /* X is a CR register.  Print the mask for `mtcrf'.  */
-      if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
-	output_operand_lossage ("invalid %%R value");
-      else
-	fprintf (file, "%d", 128 >> (REGNO (x) - 68));
-      return;
-
-    case 's':
-      /* Low 5 bits of 32 - value */
-      if (! INT_P (x))
-	output_operand_lossage ("invalid %%s value");
-
-      fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31);
-      return;
-
-    case 'S':
-      /* PowerPC64 mask position.  All 0's and all 1's are excluded.
-	 CONST_INT 32-bit mask is considered sign-extended so any
-	 transition must occur within the CONST_INT, not on the boundary.  */
-      if (! mask64_operand (x, VOIDmode))
-	output_operand_lossage ("invalid %%S value");
-
-      val = INT_LOWPART (x);
-
-      if (val & 1)      /* Clear Left */
-	{
-	  for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
-	    if (!((val >>= 1) & 1))
-	      break;
-
-#if HOST_BITS_PER_WIDE_INT == 32
-	  if (GET_CODE (x) == CONST_DOUBLE && i == 32)
-	    {
-	      val = CONST_DOUBLE_HIGH (x);
-
-	      if (val == 0)
-		--i;
-	      else
-		for (i = 32; i < 64; i++)
-		  if (!((val >>= 1) & 1))
-		    break;
-	    }
-#endif
-	/* i = index of last set bit from right
-	   mask begins at 63 - i from left */
-	  if (i > 63)
-	    output_operand_lossage ("%%S computed all 1's mask");
-	  fprintf (file, "%d", 63 - i);
-	  return;
-	}
-      else	/* Clear Right */
-	{
-	  for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
-	    if ((val >>= 1) & 1)
-	      break;
-
-#if HOST_BITS_PER_WIDE_INT == 32
-	if (GET_CODE (x) == CONST_DOUBLE && i == 32)
-	  {
-	    val = CONST_DOUBLE_HIGH (x);
-
-	    if (val == (HOST_WIDE_INT) -1)
-	      --i;
-	    else
-	      for (i = 32; i < 64; i++)
-		if ((val >>= 1) & 1)
-		  break;
-	  }
-#endif
-	/* i = index of last clear bit from right
-	   mask ends at 62 - i from left */
-	  if (i > 62)
-	    output_operand_lossage ("%%S computed all 0's mask");
-	  fprintf (file, "%d", 62 - i);
-	  return;
-	}
-
-    case 't':
-      /* Write 12 if this jump operation will branch if true, 4 otherwise. 
-	 All floating-point operations except NE branch true and integer
-	 EQ, LT, GT, LTU and GTU also branch true.  */
-      if (GET_RTX_CLASS (GET_CODE (x)) != '<')
-	output_operand_lossage ("invalid %%t value");
-
-      else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
-		&& GET_CODE (x) != NE)
-	       || GET_CODE (x) == EQ
-	       || GET_CODE (x) == LT || GET_CODE (x) == GT
-	       || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
-	fputs ("12", file);
-      else
-	putc ('4', file);
-      return;
-      
-    case 'T':
-      /* Opposite of 't': write 4 if this jump operation will branch if true,
-	 12 otherwise.   */
-      if (GET_RTX_CLASS (GET_CODE (x)) != '<')
-	output_operand_lossage ("invalid %%T value");
-
-      else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
-		&& GET_CODE (x) != NE)
-	       || GET_CODE (x) == EQ
-	       || GET_CODE (x) == LT || GET_CODE (x) == GT
-	       || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
-	putc ('4', file);
-      else
-	fputs ("12", file);
-      return;
-      
-    case 'u':
-      /* High-order 16 bits of constant for use in unsigned operand.  */
-      if (! INT_P (x))
-	output_operand_lossage ("invalid %%u value");
-
-      fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff);
-      return;
-
-    case 'v':
-      /* High-order 16 bits of constant for use in signed operand.  */
-      if (! INT_P (x))
-	output_operand_lossage ("invalid %%v value");
-
-      {
-	int value = (INT_LOWPART (x) >> 16) & 0xffff;
-
-	/* Solaris assembler doesn't like lis 0,0x80000 */
-	if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0)
-	  fprintf (file, "%d", value | (~0 << 16));
-	else
-	  fprintf (file, "0x%x", value);
-	return;
-      }
-
-    case 'U':
-      /* Print `u' if this has an auto-increment or auto-decrement.  */
-      if (GET_CODE (x) == MEM
-	  && (GET_CODE (XEXP (x, 0)) == PRE_INC
-	      || GET_CODE (XEXP (x, 0)) == PRE_DEC))
-	putc ('u', file);
-      return;
-
-    case 'V':
-      /* Print the trap code for this operand.  */
-      switch (GET_CODE (x))
-	{
-	case EQ:
-	  fputs ("eq", file);   /* 4 */
-	  break;
-	case NE:
-	  fputs ("ne", file);   /* 24 */
-	  break;
-	case LT:
-	  fputs ("lt", file);   /* 16 */
-	  break;
-	case LE:
-	  fputs ("le", file);   /* 20 */
-	  break;
-	case GT:
-	  fputs ("gt", file);   /* 8 */
-	  break;
-	case GE:
-	  fputs ("ge", file);   /* 12 */
-	  break;
-	case LTU:
-	  fputs ("llt", file);  /* 2 */
-	  break;
-	case LEU:
-	  fputs ("lle", file);  /* 6 */
-	  break;
-	case GTU:
-	  fputs ("lgt", file);  /* 1 */
-	  break;
-	case GEU:
-	  fputs ("lge", file);  /* 5 */
-	  break;
-	default:
-	  abort ();
-	}
-      break;
-
-    case 'w':
-      /* If constant, low-order 16 bits of constant, signed.  Otherwise, write
-	 normally.  */
-      if (INT_P (x))
-	fprintf (file, "%d",
-		 (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000));
-      else
-	print_operand (file, x, 0);
-      return;
-
-    case 'W':
-      /* If constant, low-order 16 bits of constant, unsigned.
-	 Otherwise, write normally.  */
-      if (INT_P (x))
-	fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
-      else
-	print_operand (file, x, 0);
-      return;
-
-    case 'X':
-      if (GET_CODE (x) == MEM
-	  && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0)))
-	putc ('x', file);
-      return;
-
-    case 'Y':
-      /* Like 'L', for third word of TImode  */
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", reg_names[REGNO (x) + 2]);
-      else if (GET_CODE (x) == MEM)
-	{
-	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
-	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
-	    output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
-	  else
-	    output_address (plus_constant (XEXP (x, 0), 8));
-	  if (small_data_operand (x, GET_MODE (x)))
-	    fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
-		     reg_names[SMALL_DATA_REG]);
-	}
-      return;
-			    
-    case 'z':
-      /* X is a SYMBOL_REF.  Write out the name preceded by a
-	 period and without any trailing data in brackets.  Used for function
-	 names.  If we are configured for System V (or the embedded ABI) on
-	 the PowerPC, do not emit the period, since those systems do not use
-	 TOCs and the like.  */
-      if (GET_CODE (x) != SYMBOL_REF)
-	abort ();
-
-      if (XSTR (x, 0)[0] != '.')
-	{
-	  switch (DEFAULT_ABI)
-	    {
-	    default:
-	      abort ();
-
-	    case ABI_AIX:
-	      putc ('.', file);
-	      break;
-
-	    case ABI_V4:
-	    case ABI_AIX_NODESC:
-	    case ABI_SOLARIS:
-	      break;
-
-	    case ABI_NT:
-	      fputs ("..", file);
-	      break;
-	    }
-	}
-      RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
-      return;
-
-    case 'Z':
-      /* Like 'L', for last word of TImode.  */
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", reg_names[REGNO (x) + 3]);
-      else if (GET_CODE (x) == MEM)
-	{
-	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
-	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
-	    output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
-	  else
-	    output_address (plus_constant (XEXP (x, 0), 12));
-	  if (small_data_operand (x, GET_MODE (x)))
-	    fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
-		     reg_names[SMALL_DATA_REG]);
-	}
-      return;
-			    
-    case 0:
-      if (GET_CODE (x) == REG)
-	fprintf (file, "%s", reg_names[REGNO (x)]);
-      else if (GET_CODE (x) == MEM)
-	{
-	  /* We need to handle PRE_INC and PRE_DEC here, since we need to
-	     know the width from the mode.  */
-	  if (GET_CODE (XEXP (x, 0)) == PRE_INC)
-	    fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)),
-		     REGNO (XEXP (XEXP (x, 0), 0)));
-	  else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
-	    fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)),
-		     REGNO (XEXP (XEXP (x, 0), 0)));
-	  else
-	    output_address (XEXP (x, 0));
-	}
-      else
-	output_addr_const (file, x);
-      return;
-
-    default:
-      output_operand_lossage ("invalid %%xn code");
-    }
-}
-
-/* Print the address of an operand.  */
-
-void
-print_operand_address (file, x)
-     FILE *file;
-     register rtx x;
-{
-  if (GET_CODE (x) == REG)
-    fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
-  else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST || GET_CODE (x) == LABEL_REF)
-    {
-      output_addr_const (file, x);
-      if (small_data_operand (x, GET_MODE (x)))
-	fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
-		 reg_names[SMALL_DATA_REG]);
-
-#ifdef TARGET_NO_TOC
-      else if (TARGET_NO_TOC)
-	;
-#endif
-      else
-	fprintf (file, "(%s)", reg_names[ TARGET_MINIMAL_TOC ? 30 : 2 ]);
-    }
-  else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
-    {
-      if (REGNO (XEXP (x, 0)) == 0)
-	fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
-		 reg_names[ REGNO (XEXP (x, 0)) ]);
-      else
-	fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
-		 reg_names[ REGNO (XEXP (x, 1)) ]);
-    }
-  else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
-    fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
-  else if (TARGET_ELF && !TARGET_64BIT && GET_CODE (x) == LO_SUM
-	   && GET_CODE (XEXP (x, 0)) == REG && CONSTANT_P (XEXP (x, 1)))
-    {
-      output_addr_const (file, XEXP (x, 1));
-      fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
-    }
-  else
-    abort ();
-}
-
-/* This page contains routines that are used to determine what the function
-   prologue and epilogue code will do and write them out.  */
-
-/*  Return the first fixed-point register that is required to be saved. 32 if
-    none.  */
-
-int
-first_reg_to_save ()
-{
-  int first_reg;
-
-  /* Find lowest numbered live register.  */
-  for (first_reg = 13; first_reg <= 31; first_reg++)
-    if (regs_ever_live[first_reg])
-      break;
-
-  /* If profiling, then we must save/restore every register that contains
-     a parameter before/after the .__mcount call.  Use registers from 30 down
-     to 23 to do this.  Don't use the frame pointer in reg 31.
-
-     For now, save enough room for all of the parameter registers.  */
-  if (DEFAULT_ABI == ABI_AIX && profile_flag)
-    if (first_reg > 23)
-      first_reg = 23;
-
-  return first_reg;
-}
-
-/* Similar, for FP regs.  */
-
-int
-first_fp_reg_to_save ()
-{
-  int first_reg;
-
-  /* Find lowest numbered live register.  */
-  for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
-    if (regs_ever_live[first_reg])
-      break;
-
-  return first_reg;
-}
-
-/* Return non-zero if this function makes calls.  */
-
-int
-rs6000_makes_calls ()
-{
-  rtx insn;
-
-  /* If we are profiling, we will be making a call to __mcount.
-     Under the System V ABI's, we store the LR directly, so
-     we don't need to do it here.  */
-  if (DEFAULT_ABI == ABI_AIX && profile_flag)
-    return 1;
-
-  for (insn = get_insns (); insn; insn = next_insn (insn))
-    if (GET_CODE (insn) == CALL_INSN)
-      return 1;
-
-  return 0;
-}
-
-
-/* Calculate the stack information for the current function.  This is
-   complicated by having two separate calling sequences, the AIX calling
-   sequence and the V.4 calling sequence.
-
-   AIX stack frames look like:
-							  32-bit  64-bit
-	SP---->	+---------------------------------------+
-		| back chain to caller			| 0	  0
-		+---------------------------------------+
-		| saved CR				| 4       8 (8-11)
-		+---------------------------------------+
-		| saved LR				| 8       16
-		+---------------------------------------+
-		| reserved for compilers		| 12      24
-		+---------------------------------------+
-		| reserved for binders			| 16      32
-		+---------------------------------------+
-		| saved TOC pointer			| 20      40
-		+---------------------------------------+
-		| Parameter save area (P)		| 24      48
-		+---------------------------------------+
-		| Alloca space (A)			| 24+P    etc.
-		+---------------------------------------+
-		| Local variable space (L)		| 24+P+A
-		+---------------------------------------+
-		| Float/int conversion temporary (X)	| 24+P+A+L
-		+---------------------------------------+
-		| Save area for GP registers (G)	| 24+P+A+X+L
-		+---------------------------------------+
-		| Save area for FP registers (F)	| 24+P+A+X+L+G
-		+---------------------------------------+
-	old SP->| back chain to caller's caller		|
-		+---------------------------------------+
-
-   The required alignment for AIX configurations is two words (i.e., 8
-   or 16 bytes).
-
-
-   V.4 stack frames look like:
-
-	SP---->	+---------------------------------------+
-		| back chain to caller			| 0
-		+---------------------------------------+
-		| caller's saved LR			| 4
-		+---------------------------------------+
-		| Parameter save area (P)		| 8
-		+---------------------------------------+
-		| Alloca space (A)			| 8+P
-		+---------------------------------------+    
-		| Varargs save area (V)			| 8+P+A
-		+---------------------------------------+    
-		| Local variable space (L)		| 8+P+A+V
-		+---------------------------------------+    
-		| Float/int conversion temporary (X)	| 8+P+A+V+L
-		+---------------------------------------+
-		| saved CR (C)				| 8+P+A+V+L+X
-		+---------------------------------------+    
-		| Save area for GP registers (G)	| 8+P+A+V+L+X+C
-		+---------------------------------------+    
-		| Save area for FP registers (F)	| 8+P+A+V+L+X+C+G
-		+---------------------------------------+
-	old SP->| back chain to caller's caller		|
-		+---------------------------------------+
-
-   The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
-   given.  (But note below and in sysv4.h that we require only 8 and
-   may round up the size of our stack frame anyways.  The historical
-   reason is early versions of powerpc-linux which didn't properly
-   align the stack at program startup.  A happy side-effect is that
-   -mno-eabi libraries can be used with -meabi programs.)
-
-
-   A PowerPC Windows/NT frame looks like:
-
-	SP---->	+---------------------------------------+
-		| back chain to caller			| 0
-		+---------------------------------------+
-		| reserved				| 4
-		+---------------------------------------+
-		| reserved				| 8
-		+---------------------------------------+
-		| reserved				| 12
-		+---------------------------------------+
-		| reserved				| 16
-		+---------------------------------------+
-		| reserved				| 20
-		+---------------------------------------+
-		| Parameter save area (P)		| 24
-		+---------------------------------------+
-		| Alloca space (A)			| 24+P
-		+---------------------------------------+     
-		| Local variable space (L)		| 24+P+A
-		+---------------------------------------+     
-		| Float/int conversion temporary (X)	| 24+P+A+L
-		+---------------------------------------+
-		| Save area for FP registers (F)	| 24+P+A+L+X
-		+---------------------------------------+     
-		| Possible alignment area (Y)		| 24+P+A+L+X+F
-		+---------------------------------------+     
-		| Save area for GP registers (G)	| 24+P+A+L+X+F+Y
-		+---------------------------------------+     
-		| Save area for CR (C)			| 24+P+A+L+X+F+Y+G
-		+---------------------------------------+     
-		| Save area for TOC (T)			| 24+P+A+L+X+F+Y+G+C
-		+---------------------------------------+     
-		| Save area for LR (R)			| 24+P+A+L+X+F+Y+G+C+T
-		+---------------------------------------+
-	old SP->| back chain to caller's caller		|
-		+---------------------------------------+
-
-   For NT, there is no specific order to save the registers, but in
-   order to support __builtin_return_address, the save area for the
-   link register needs to be in a known place, so we use -4 off of the
-   old SP.  To support calls through pointers, we also allocate a
-   fixed slot to store the TOC, -8 off the old SP.
-
-   The required alignment for NT is 16 bytes.
-
-
-   The EABI configuration defaults to the V.4 layout, unless
-   -mcall-aix is used, in which case the AIX layout is used.  However,
-   the stack alignment requirements may differ.  If -mno-eabi is not
-   given, the required stack alignment is 8 bytes; if -mno-eabi is
-   given, the required alignment is 16 bytes.  (But see V.4 comment
-   above.)  */
-
-#ifndef ABI_STACK_BOUNDARY
-#define ABI_STACK_BOUNDARY STACK_BOUNDARY
-#endif
-
-rs6000_stack_t *
-rs6000_stack_info ()
-{
-  static rs6000_stack_t info, zero_info;
-  rs6000_stack_t *info_ptr = &info;
-  int reg_size = TARGET_32BIT ? 4 : 8;
-  enum rs6000_abi abi;
-  int total_raw_size;
-
-  /* Zero all fields portably */
-  info = zero_info;
-
-  /* Select which calling sequence */
-  info_ptr->abi = abi = DEFAULT_ABI;
-
-  /* Calculate which registers need to be saved & save area size */
-  info_ptr->first_gp_reg_save = first_reg_to_save ();
-  info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
-
-  info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
-  info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
-
-  /* Does this function call anything? */
-  info_ptr->calls_p = rs6000_makes_calls ();
-
-  /* Allocate space to save the toc. */
-  if (abi == ABI_NT && info_ptr->calls_p)
-    {
-      info_ptr->toc_save_p = 1;
-      info_ptr->toc_size = reg_size;
-    }
-
-  /* Does this machine need the float/int conversion area? */
-  info_ptr->fpmem_p = regs_ever_live[FPMEM_REGNUM];
-
-  /* If this is main and we need to call a function to set things up,
-     save main's arguments around the call.  */
-#ifdef TARGET_EABI
-  if (TARGET_EABI)
-#endif
-    {
-      if (strcmp (IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), "main") == 0
-	  && DECL_CONTEXT (current_function_decl) == NULL_TREE)
-	{
-	  info_ptr->main_p = 1;
-
-#ifdef NAME__MAIN
-	  info_ptr->calls_p = 1;
-
-	  if (DECL_ARGUMENTS (current_function_decl))
-	    {
-	      int i;
-	      tree arg;
-
-	      info_ptr->main_save_p = 1;
-	      info_ptr->main_size = 0;
-
-	      for ((i = 0), (arg = DECL_ARGUMENTS (current_function_decl));
-		   arg != NULL_TREE && i < 8;
-		   (arg = TREE_CHAIN (arg)), i++)
-		{
-		  info_ptr->main_size += reg_size;
-		}
-	    }
-#endif
-	}
-    }
-
-  /* Determine if we need to save the link register */
-  if (regs_ever_live[65]
-      || (DEFAULT_ABI == ABI_AIX && profile_flag)
-#ifdef TARGET_RELOCATABLE
-      || (TARGET_RELOCATABLE && (get_pool_size () != 0))
-#endif
-      || (info_ptr->first_fp_reg_save != 64
-	  && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
-      || (abi == ABI_V4 && current_function_calls_alloca)
-      || (abi == ABI_SOLARIS && current_function_calls_alloca)
-      || info_ptr->calls_p)
-    {
-      info_ptr->lr_save_p = 1;
-      regs_ever_live[65] = 1;
-      if (abi == ABI_NT)
-	info_ptr->lr_size = reg_size;
-    }
-
-  /* Determine if we need to save the condition code registers */
-  if (regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72])
-    {
-      info_ptr->cr_save_p = 1;
-      if (abi == ABI_V4 || abi == ABI_NT || abi == ABI_SOLARIS)
-	info_ptr->cr_size = reg_size;
-    }
-
-  /* Determine various sizes */
-  info_ptr->reg_size     = reg_size;
-  info_ptr->fixed_size   = RS6000_SAVE_AREA;
-  info_ptr->varargs_size = RS6000_VARARGS_AREA;
-  info_ptr->vars_size    = RS6000_ALIGN (get_frame_size (), 8);
-  info_ptr->parm_size    = RS6000_ALIGN (current_function_outgoing_args_size, 8);
-  info_ptr->fpmem_size	 = (info_ptr->fpmem_p) ? 8 : 0;
-  info_ptr->save_size    = RS6000_ALIGN (info_ptr->fp_size
-				  + info_ptr->gp_size
-				  + info_ptr->cr_size
-				  + info_ptr->lr_size
-				  + info_ptr->toc_size
-				  + info_ptr->main_size, 8);
-
-  /* Calculate the offsets */
-  switch (abi)
-    {
-    case ABI_NONE:
-    default:
-      abort ();
-
-    case ABI_AIX:
-    case ABI_AIX_NODESC:
-      info_ptr->fp_save_offset   = - info_ptr->fp_size;
-      info_ptr->gp_save_offset   = info_ptr->fp_save_offset - info_ptr->gp_size;
-      info_ptr->main_save_offset = info_ptr->gp_save_offset - info_ptr->main_size;
-      info_ptr->cr_save_offset   = reg_size; /* first word when 64-bit.  */
-      info_ptr->lr_save_offset   = 2*reg_size;
-      break;
-
-    case ABI_V4:
-    case ABI_SOLARIS:
-      info_ptr->fp_save_offset   = - info_ptr->fp_size;
-      info_ptr->gp_save_offset   = info_ptr->fp_save_offset - info_ptr->gp_size;
-      info_ptr->cr_save_offset   = info_ptr->gp_save_offset - info_ptr->cr_size;
-      info_ptr->toc_save_offset  = info_ptr->cr_save_offset - info_ptr->toc_size;
-      info_ptr->main_save_offset = info_ptr->toc_save_offset - info_ptr->main_size;
-      info_ptr->lr_save_offset   = reg_size;
-      break;
-
-    case ABI_NT:
-      info_ptr->lr_save_offset    = -reg_size;
-      info_ptr->toc_save_offset   = info_ptr->lr_save_offset - info_ptr->lr_size;
-      info_ptr->cr_save_offset    = info_ptr->toc_save_offset - info_ptr->toc_size;
-      info_ptr->gp_save_offset    = info_ptr->cr_save_offset - info_ptr->cr_size - info_ptr->gp_size + reg_size;
-      info_ptr->fp_save_offset    = info_ptr->gp_save_offset - info_ptr->fp_size;
-      if (info_ptr->fp_size && ((- info_ptr->fp_save_offset) % 8) != 0)
-	info_ptr->fp_save_offset -= reg_size;
-
-      info_ptr->main_save_offset = info_ptr->fp_save_offset - info_ptr->main_size;
-      break;
-    }
-
-  /* Ensure that fpmem_offset will be aligned to an 8-byte boundary. */
-  if (info_ptr->fpmem_p
-      && (info_ptr->main_save_offset - info_ptr->fpmem_size) % 8)
-    info_ptr->fpmem_size += reg_size;
-
-  total_raw_size	 = (info_ptr->vars_size
-			    + info_ptr->parm_size
-			    + info_ptr->fpmem_size
-			    + info_ptr->save_size
-			    + info_ptr->varargs_size
-			    + info_ptr->fixed_size);
-
-  info_ptr->total_size   = RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT);
-
-  /* Determine if we need to allocate any stack frame:
-
-     For AIX we need to push the stack if a frame pointer is needed (because
-     the stack might be dynamically adjusted), if we are debugging, if we
-     make calls, or if the sum of fp_save, gp_save, fpmem, and local variables
-     are more than the space needed to save all non-volatile registers:
-     32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 + 19*8 = 296
-
-     For V.4 we don't have the stack cushion that AIX uses, but assume that
-     the debugger can handle stackless frames.  */
-
-  if (info_ptr->calls_p)
-    info_ptr->push_p = 1;
-
-  else if (abi == ABI_V4 || abi == ABI_NT || abi == ABI_SOLARIS)
-    info_ptr->push_p = (total_raw_size > info_ptr->fixed_size
-			|| (abi == ABI_NT ? info_ptr->lr_save_p
-			    : info_ptr->calls_p));
-
-  else
-    info_ptr->push_p = (frame_pointer_needed
-			|| write_symbols != NO_DEBUG
-			|| ((total_raw_size - info_ptr->fixed_size)
-			    > (TARGET_32BIT ? 220 : 296)));
-
-  if (info_ptr->fpmem_p)
-    {
-      info_ptr->fpmem_offset = info_ptr->main_save_offset - info_ptr->fpmem_size;
-      rs6000_fpmem_size   = info_ptr->fpmem_size;
-      rs6000_fpmem_offset = (info_ptr->push_p
-			     ? info_ptr->total_size + info_ptr->fpmem_offset
-			     : info_ptr->fpmem_offset);
-    }
-  else
-    info_ptr->fpmem_offset = 0;  
-
-  /* Zero offsets if we're not saving those registers */
-  if (info_ptr->fp_size == 0)
-    info_ptr->fp_save_offset = 0;
-
-  if (info_ptr->gp_size == 0)
-    info_ptr->gp_save_offset = 0;
-
-  if (!info_ptr->lr_save_p)
-    info_ptr->lr_save_offset = 0;
-
-  if (!info_ptr->cr_save_p)
-    info_ptr->cr_save_offset = 0;
-
-  if (!info_ptr->toc_save_p)
-    info_ptr->toc_save_offset = 0;
-
-  if (!info_ptr->main_save_p)
-    info_ptr->main_save_offset = 0;
-
-  return info_ptr;
-}
-
-void
-debug_stack_info (info)
-     rs6000_stack_t *info;
-{
-  char *abi_string;
-
-  if (!info)
-    info = rs6000_stack_info ();
-
-  fprintf (stderr, "\nStack information for function %s:\n",
-	   ((current_function_decl && DECL_NAME (current_function_decl))
-	    ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
-	    : "<unknown>"));
-
-  switch (info->abi)
-    {
-    default:		 abi_string = "Unknown";	break;
-    case ABI_NONE:	 abi_string = "NONE";		break;
-    case ABI_AIX:	 abi_string = "AIX";		break;
-    case ABI_AIX_NODESC: abi_string = "AIX";		break;
-    case ABI_V4:	 abi_string = "V.4";		break;
-    case ABI_SOLARIS:	 abi_string = "Solaris";	break;
-    case ABI_NT:	 abi_string = "NT";		break;
-    }
-
-  fprintf (stderr, "\tABI                 = %5s\n", abi_string);
-
-  if (info->first_gp_reg_save != 32)
-    fprintf (stderr, "\tfirst_gp_reg_save   = %5d\n", info->first_gp_reg_save);
-
-  if (info->first_fp_reg_save != 64)
-    fprintf (stderr, "\tfirst_fp_reg_save   = %5d\n", info->first_fp_reg_save);
-
-  if (info->lr_save_p)
-    fprintf (stderr, "\tlr_save_p           = %5d\n", info->lr_save_p);
-
-  if (info->cr_save_p)
-    fprintf (stderr, "\tcr_save_p           = %5d\n", info->cr_save_p);
-
-  if (info->toc_save_p)
-    fprintf (stderr, "\ttoc_save_p          = %5d\n", info->toc_save_p);
-
-  if (info->push_p)
-    fprintf (stderr, "\tpush_p              = %5d\n", info->push_p);
-
-  if (info->calls_p)
-    fprintf (stderr, "\tcalls_p             = %5d\n", info->calls_p);
-
-  if (info->main_p)
-    fprintf (stderr, "\tmain_p              = %5d\n", info->main_p);
-
-  if (info->main_save_p)
-    fprintf (stderr, "\tmain_save_p         = %5d\n", info->main_save_p);
-
-  if (info->fpmem_p)
-    fprintf (stderr, "\tfpmem_p             = %5d\n", info->fpmem_p);
-
-  if (info->gp_save_offset)
-    fprintf (stderr, "\tgp_save_offset      = %5d\n", info->gp_save_offset);
-
-  if (info->fp_save_offset)
-    fprintf (stderr, "\tfp_save_offset      = %5d\n", info->fp_save_offset);
-
-  if (info->lr_save_offset)
-    fprintf (stderr, "\tlr_save_offset      = %5d\n", info->lr_save_offset);
-
-  if (info->cr_save_offset)
-    fprintf (stderr, "\tcr_save_offset      = %5d\n", info->cr_save_offset);
-
-  if (info->toc_save_offset)
-    fprintf (stderr, "\ttoc_save_offset     = %5d\n", info->toc_save_offset);
-
-  if (info->varargs_save_offset)
-    fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
-
-  if (info->main_save_offset)
-    fprintf (stderr, "\tmain_save_offset    = %5d\n", info->main_save_offset);
-
-  if (info->fpmem_offset)
-    fprintf (stderr, "\tfpmem_offset        = %5d\n", info->fpmem_offset);
-
-  if (info->total_size)
-    fprintf (stderr, "\ttotal_size          = %5d\n", info->total_size);
-
-  if (info->varargs_size)
-    fprintf (stderr, "\tvarargs_size        = %5d\n", info->varargs_size);
-
-  if (info->vars_size)
-    fprintf (stderr, "\tvars_size           = %5d\n", info->vars_size);
-
-  if (info->parm_size)
-    fprintf (stderr, "\tparm_size           = %5d\n", info->parm_size);
-
-  if (info->fpmem_size)
-    fprintf (stderr, "\tfpmem_size          = %5d\n", info->fpmem_size);
-
-  if (info->fixed_size)
-    fprintf (stderr, "\tfixed_size          = %5d\n", info->fixed_size);
-
-  if (info->gp_size)
-    fprintf (stderr, "\tgp_size             = %5d\n", info->gp_size);
-
-  if (info->fp_size)
-    fprintf (stderr, "\tfp_size             = %5d\n", info->fp_size);
-
- if (info->lr_size)
-    fprintf (stderr, "\tlr_size             = %5d\n", info->cr_size);
-
-  if (info->cr_size)
-    fprintf (stderr, "\tcr_size             = %5d\n", info->cr_size);
-
- if (info->toc_size)
-    fprintf (stderr, "\ttoc_size            = %5d\n", info->toc_size);
-
- if (info->main_size)
-    fprintf (stderr, "\tmain_size           = %5d\n", info->main_size);
-
-  if (info->save_size)
-    fprintf (stderr, "\tsave_size           = %5d\n", info->save_size);
-
-  if (info->reg_size != 4)
-    fprintf (stderr, "\treg_size            = %5d\n", info->reg_size);
-
-  fprintf (stderr, "\n");
-}
-
-
-/* CYGNUS LOCAL -- vmakarov/prolog-epilog instruction scheduling */
-#if 0
-/* END CYGNUS LOCAL */
-
-/* Write out an instruction to load the TOC_TABLE address into register 30.
-   This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
-   a constant pool.  */
-
-void
-rs6000_output_load_toc_table (file, reg)
-     FILE *file;
-     int reg;
-{
-  char buf[256];
-
-#ifdef USING_SVR4_H
-  if (TARGET_RELOCATABLE)
-    {
-      ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
-      fprintf (file, "\tbl ");
-      assemble_name (file, buf);
-      fprintf (file, "\n");
-
-      /* possibly create the toc section */
-      if (!toc_initialized)
-	{
-	  toc_section ();
-	  function_section (current_function_decl);
-	}
-
-      /* If not first call in this function, we need to put the
-	 different between .LCTOC1 and the address we get to right
-	 after the bl.  It will mess up disassembling the instructions
-	 but that can't be helped.  We will later need to bias the
-	 address before loading.  */
-      if (rs6000_pic_func_labelno != rs6000_pic_labelno)
-	{
-	  char *init_ptr = TARGET_32BIT ? ".long" : ".quad";
-	  char *buf_ptr;
-
-	  ASM_OUTPUT_INTERNAL_LABEL (file, "LCL", rs6000_pic_labelno);
-
-	  ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
-	  STRIP_NAME_ENCODING (buf_ptr, buf);
-	  fprintf (file, "\t%s %s-", init_ptr, buf_ptr);
-
-	  ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
-	  fprintf (file, "%s\n", buf_ptr);
-	}
-
-      ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno);
-      fprintf (file, "\tmflr %s\n", reg_names[reg]);
-
-      if (rs6000_pic_func_labelno != rs6000_pic_labelno)
-	  asm_fprintf(file, "\t{cal|la} %s,%d(%s)\n", reg_names[reg],
-		      (TARGET_32BIT ? 4 : 8), reg_names[reg]);
-
-      asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s,(" : "\tld %s,(",
-		   reg_names[0]);
-      ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
-      assemble_name (file, buf);
-      fputs ("-", file);
-      ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
-      assemble_name (file, buf);
-      fprintf (file, ")(%s)\n", reg_names[reg]);
-      asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
-		   reg_names[reg], reg_names[0], reg_names[reg]);
-      rs6000_pic_labelno++;
-    }
-  else if (!TARGET_64BIT)
-    {
-      ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
-      asm_fprintf (file, "\t{liu|lis} %s,", reg_names[reg]);
-      assemble_name (file, buf);
-      fputs ("@ha\n", file);
-      asm_fprintf (file, "\t{cal|la} %s,", reg_names[reg]);
-      assemble_name (file, buf);
-      asm_fprintf (file, "@l(%s)\n", reg_names[reg]);
-    }
-  else
-    abort ();
-
-#else	/* !USING_SVR4_H */
-  ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0);
-  asm_fprintf (file, TARGET_32BIT ? "\t{l|lwz} %s," : "\tld %s,",
-	       reg_names[reg]);
-  assemble_name (file, buf);
-  asm_fprintf (file, "(%s)\n", reg_names[2]);
-#endif /* USING_SVR4_H */
-}
-
-
-/* Emit the correct code for allocating stack space.  If COPY_R12, make sure a copy
-   of the old frame is left in r12.  */
-
-void
-rs6000_allocate_stack_space (file, size, copy_r12)
-     FILE *file;
-     int size;
-     int copy_r12;
-{
-  int neg_size = -size;
-  if (TARGET_UPDATE)
-    {
-      if (size < 32767)
-	asm_fprintf (file,
-		     (TARGET_32BIT) ? "\t{stu|stwu} %s,%d(%s)\n" : "\tstdu %s,%d(%s)\n",
-		     reg_names[1], neg_size, reg_names[1]);
-      else
-	{
-	  if (copy_r12)
-	    fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
-
-	  asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
-		       reg_names[0], (neg_size >> 16) & 0xffff,
-		       reg_names[0], reg_names[0], neg_size & 0xffff);
-	  asm_fprintf (file,
-		       (TARGET_32BIT) ? "\t{stux|stwux} %s,%s,%s\n" : "\tstdux %s,%s,%s\n",
-		       reg_names[1], reg_names[1], reg_names[0]);
-	}
-    }
-  else
-    {
-      fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
-      if (size < 32767)
-	asm_fprintf (file, "\t{cal|la} %s,%d(%s)\n",
-		 reg_names[1], neg_size, reg_names[1]);
-      else
-	{
-	  asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
-		       reg_names[0], (neg_size >> 16) & 0xffff,
-		       reg_names[0], reg_names[0], neg_size & 0xffff);
-	  asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", reg_names[1],
-		       reg_names[0], reg_names[1]);
-	}
-
-      asm_fprintf (file,
-		   (TARGET_32BIT) ? "\t{st|stw} %s,0(%s)\n" : "\tstd %s,0(%s)\n",
-		   reg_names[12], reg_names[1]);
-    }
-}
-
-
-/* Write function prologue.  */
-void
-output_prolog (file, size)
-     FILE *file;
-     int size ATTRIBUTE_UNUSED;
-{
-  rs6000_stack_t *info = rs6000_stack_info ();
-  int reg_size = info->reg_size;
-  char *store_reg;
-  char *load_reg;
-  int sp_reg = 1;
-  int sp_offset = 0;
-
-  if (TARGET_32BIT)
-    {
-      store_reg = "\t{st|stw} %s,%d(%s)\n";
-      load_reg = "\t{l|lwz} %s,%d(%s)\n";
-    }
-  else
-    {
-      store_reg = "\tstd %s,%d(%s)\n";
-      load_reg = "\tlld %s,%d(%s)\n";
-    }
-
-  if (TARGET_DEBUG_STACK)
-    debug_stack_info (info);
-
-  /* Write .extern for any function we will call to save and restore fp
-     values.  */
-  if (info->first_fp_reg_save < 64 && !FP_SAVE_INLINE (info->first_fp_reg_save))
-    fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
-	     SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
-	     RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
-
-  /* Write .extern for truncation routines, if needed.  */
-  if (rs6000_trunc_used && ! trunc_defined)
-    {
-      fprintf (file, "\t.extern .%s\n\t.extern .%s\n",
-	       RS6000_ITRUNC, RS6000_UITRUNC);
-      trunc_defined = 1;
-    }
-
-  /* Write .extern for AIX common mode routines, if needed.  */
-  if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
-    {
-      fputs ("\t.extern __mulh\n", file);
-      fputs ("\t.extern __mull\n", file);
-      fputs ("\t.extern __divss\n", file);
-      fputs ("\t.extern __divus\n", file);
-      fputs ("\t.extern __quoss\n", file);
-      fputs ("\t.extern __quous\n", file);
-      common_mode_defined = 1;
-    }
-
-  /* For V.4, update stack before we do any saving and set back pointer.  */
-  if (info->push_p && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
-    {
-      if (info->total_size < 32767)
-	sp_offset = info->total_size;
-      else
-	sp_reg = 12;
-      rs6000_allocate_stack_space (file, info->total_size, sp_reg == 12);
-    }
-
-  /* If we use the link register, get it into r0.  */
-  if (info->lr_save_p)
-    asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
-
-  /* If we need to save CR, put it into r12.  */
-  if (info->cr_save_p && sp_reg != 12)
-    asm_fprintf (file, "\tmfcr %s\n", reg_names[12]);
-
-  /* Do any required saving of fpr's.  If only one or two to save, do it
-     ourself.  Otherwise, call function.  Note that since they are statically
-     linked, we do not need a nop following them.  */
-  if (FP_SAVE_INLINE (info->first_fp_reg_save))
-    {
-      int regno = info->first_fp_reg_save;
-      int loc   = info->fp_save_offset + sp_offset;
-
-      for ( ; regno < 64; regno++, loc += 8)
-	asm_fprintf (file, "\tstfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]);
-    }
-  else if (info->first_fp_reg_save != 64)
-    asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX,
-		 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
-
-  /* Now save gpr's.  */
-  if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
-    {
-      int regno    = info->first_gp_reg_save;
-      int loc      = info->gp_save_offset + sp_offset;
-
-      for ( ; regno < 32; regno++, loc += reg_size)
-	asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[sp_reg]);
-    }
-
-  else if (info->first_gp_reg_save != 32)
-    asm_fprintf (file, "\t{stm|stmw} %s,%d(%s)\n",
-		 reg_names[info->first_gp_reg_save],
-		 info->gp_save_offset + sp_offset,
-		 reg_names[sp_reg]);
-
-  /* Save main's arguments if we need to call a function */
-#ifdef NAME__MAIN
-  if (info->main_save_p)
-    {
-      int regno;
-      int loc = info->main_save_offset + sp_offset;
-      int size = info->main_size;
-
-      for (regno = 3; size > 0; regno++, loc += reg_size, size -= reg_size)
-	asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[sp_reg]);
-    }
-#endif
-
-  /* Save lr if we used it.  */
-  if (info->lr_save_p)
-    asm_fprintf (file, store_reg, reg_names[0], info->lr_save_offset + sp_offset,
-		 reg_names[sp_reg]);
-
-  /* Save CR if we use any that must be preserved.  */
-  if (info->cr_save_p)
-    {
-      if (sp_reg == 12)	/* If r12 is used to hold the original sp, copy cr now */
-	{
-	  asm_fprintf (file, "\tmfcr %s\n", reg_names[0]);
-	  asm_fprintf (file, store_reg, reg_names[0],
-		       info->cr_save_offset + sp_offset,
-		       reg_names[sp_reg]);
-	}
-      else
-	asm_fprintf (file, store_reg, reg_names[12], info->cr_save_offset + sp_offset,
-		     reg_names[sp_reg]);
-    }
-
-  /* NT needs us to probe the stack frame every 4k pages for large frames, so
-     do it here.  */
-  if (DEFAULT_ABI == ABI_NT && info->total_size > 4096)
-    {
-      if (info->total_size < 32768)
-	{
-	  int probe_offset = 4096;
-	  while (probe_offset < info->total_size)
-	    {
-	      asm_fprintf (file, "\t{l|lwz} %s,%d(%s)\n", reg_names[0], -probe_offset, reg_names[1]);
-	      probe_offset += 4096;
-	    }
-	}
-      else
-	{
-	  int probe_iterations = info->total_size / 4096;
-	  static int probe_labelno = 0;
-	  char buf[256];
-
-	  if (probe_iterations < 32768)
-	    asm_fprintf (file, "\tli %s,%d\n", reg_names[12], probe_iterations);
-	  else
-	    {
-	      asm_fprintf (file, "\tlis %s,%d\n", reg_names[12], probe_iterations >> 16);
-	      if (probe_iterations & 0xffff)
-		asm_fprintf (file, "\tori %s,%s,%d\n", reg_names[12], reg_names[12],
-			     probe_iterations & 0xffff);
-	    }
-	  asm_fprintf (file, "\tmtctr %s\n", reg_names[12]);
-	  asm_fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
-	  ASM_OUTPUT_INTERNAL_LABEL (file, "LCprobe", probe_labelno);
-	  asm_fprintf (file, "\t{lu|lwzu} %s,-4096(%s)\n", reg_names[0], reg_names[12]);
-	  ASM_GENERATE_INTERNAL_LABEL (buf, "LCprobe", probe_labelno++);
-	  fputs ("\tbdnz ", file);
-	  assemble_name (file, buf);
-	  fputs ("\n", file);
-	}
-    }
-
-  /* Update stack and set back pointer unless this is V.4, which was done previously */
-  if (info->push_p && DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
-    rs6000_allocate_stack_space (file, info->total_size, FALSE);
-
-  /* Set frame pointer, if needed.  */
-  if (frame_pointer_needed)
-    asm_fprintf (file, "\tmr %s,%s\n", reg_names[31], reg_names[1]);
-
-#ifdef NAME__MAIN
-  /* If we need to call a function to set things up for main, do so now
-     before dealing with the TOC.  */
-  if (info->main_p)
-    {
-      char *prefix = "";
-
-      switch (DEFAULT_ABI)
-	{
-	case ABI_AIX:	prefix = ".";	break;
-	case ABI_NT:	prefix = "..";	break;
-	}
-
-      fprintf (file, "\tbl %s%s\n", prefix, NAME__MAIN);
-#ifdef RS6000_CALL_GLUE2
-      fprintf (file, "\t%s%s%s\n", RS6000_CALL_GLUE2, prefix, NAME_MAIN);
-#else
-#ifdef RS6000_CALL_GLUE
-      if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
-	fprintf (file, "\t%s\n", RS6000_CALL_GLUE);
-#endif
-#endif
-
-      if (info->main_save_p)
-	{
-	  int regno;
-	  int loc;
-	  int size = info->main_size;
-
-	  if (info->total_size < 32767)
-	    {
-	      loc = info->total_size + info->main_save_offset;
-	      for (regno = 3; size > 0; regno++, size -= reg_size, loc += reg_size)
-		asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[1]);
-	    }
-	  else
-	    {
-	      int neg_size = info->main_save_offset - info->total_size;
-	      loc = 0;
-	      asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
-			   reg_names[0], (neg_size >> 16) & 0xffff,
-			   reg_names[0], reg_names[0], neg_size & 0xffff);
-
-	      asm_fprintf (file, "\t{sf|subf} %s,%s,%s\n", reg_names[0], reg_names[0],
-			   reg_names[1]);
-
-	      for (regno = 3; size > 0; regno++, size -= reg_size, loc += reg_size)
-		asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[0]);
-	    }
-	}
-    }
-#endif
-
-
-  /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
-     TOC_TABLE address into register 30.  */
-  if (TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
-    {
-#ifdef USING_SVR4_H
-      if (!profile_flag)
-	rs6000_pic_func_labelno = rs6000_pic_labelno;
-#endif
-      rs6000_output_load_toc_table (file, 30);
-    }
-
-  if (DEFAULT_ABI == ABI_NT)
-    {
-      assemble_name (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
-      fputs (".b:\n", file);
-    }
-}
-
-/* Write function epilogue.  */
-
-void
-output_epilog (file, size)
-     FILE *file;
-     int size ATTRIBUTE_UNUSED;
-{
-  rs6000_stack_t *info = rs6000_stack_info ();
-  char *load_reg = (TARGET_32BIT) ? "\t{l|lwz} %s,%d(%s)\n" : "\tld %s,%d(%s)\n";
-  rtx insn = get_last_insn ();
-  int sp_reg = 1;
-  int sp_offset = 0;
-
-  /* If the last insn was a BARRIER, we don't have to write anything except
-     the trace table.  */
-  if (GET_CODE (insn) == NOTE)
-    insn = prev_nonnote_insn (insn);
-  if (insn == 0 ||  GET_CODE (insn) != BARRIER)
-    {
-      /* If we have a frame pointer, a call to alloca,  or a large stack
-	 frame, restore the old stack pointer using the backchain.  Otherwise,
-	 we know what size to update it with.  */
-      if (frame_pointer_needed || current_function_calls_alloca
-	  || info->total_size > 32767)
-	{
-	  /* Under V.4, don't reset the stack pointer until after we're done
-	     loading the saved registers.  */
-	  if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-	    sp_reg = 11;
-
-	  asm_fprintf (file, load_reg, reg_names[sp_reg], 0, reg_names[1]);
-	}
-      else if (info->push_p)
-	{
-	  if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-	    sp_offset = info->total_size;
-	  else
-	    asm_fprintf (file, "\t{cal|la} %s,%d(%s)\n",
-			 reg_names[1], info->total_size, reg_names[1]);
-	}
-
-      /* Get the old lr if we saved it.  */
-      if (info->lr_save_p)
-	asm_fprintf (file, load_reg, reg_names[0], info->lr_save_offset + sp_offset, reg_names[sp_reg]);
-
-      /* Get the old cr if we saved it.  */
-      if (info->cr_save_p)
-	asm_fprintf (file, load_reg, reg_names[12], info->cr_save_offset + sp_offset, reg_names[sp_reg]);
-
-      /* Set LR here to try to overlap restores below.  */
-      if (info->lr_save_p)
-	asm_fprintf (file, "\tmtlr %s\n", reg_names[0]);
-
-      /* Restore gpr's.  */
-      if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
-	{
-	  int regno    = info->first_gp_reg_save;
-	  int loc      = info->gp_save_offset + sp_offset;
-	  int reg_size = (TARGET_32BIT) ? 4 : 8;
-
-	  for ( ; regno < 32; regno++, loc += reg_size)
-	    asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[sp_reg]);
-	}
-
-      else if (info->first_gp_reg_save != 32)
-	asm_fprintf (file, "\t{lm|lmw} %s,%d(%s)\n",
-		     reg_names[info->first_gp_reg_save],
-		     info->gp_save_offset + sp_offset,
-		     reg_names[sp_reg]);
-
-      /* Restore fpr's if we can do it without calling a function.  */
-      if (FP_SAVE_INLINE (info->first_fp_reg_save))
-	{
-	  int regno = info->first_fp_reg_save;
-	  int loc   = info->fp_save_offset + sp_offset;
-
-	  for ( ; regno < 64; regno++, loc += 8)
-	    asm_fprintf (file, "\tlfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]);
-	}
-
-      /* If we saved cr, restore it here.  Just those of cr2, cr3, and cr4
-	 that were used.  */
-      if (info->cr_save_p)
-	asm_fprintf (file, "\tmtcrf %d,%s\n",
-		     (regs_ever_live[70] != 0) * 0x20
-		     + (regs_ever_live[71] != 0) * 0x10
-		     + (regs_ever_live[72] != 0) * 0x8, reg_names[12]);
-
-      /* If this is V.4, unwind the stack pointer after all of the loads
-	 have been done */
-      if (sp_offset != 0)
-	asm_fprintf (file, "\t{cal|la} %s,%d(%s)\n",
-		     reg_names[1], sp_offset, reg_names[1]);
-      else if (sp_reg != 1)
-	asm_fprintf (file, "\tmr %s,%s\n", reg_names[1], reg_names[sp_reg]);
-
-      /* If we have to restore more than two FP registers, branch to the
-	 restore function.  It will return to our caller.  */
-      if (info->first_fp_reg_save != 64 && !FP_SAVE_INLINE (info->first_fp_reg_save))
-	asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX,
-		     info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
-      else
-	asm_fprintf (file, "\t{br|blr}\n");
-    }
-
-  /* Output a traceback table here.  See /usr/include/sys/debug.h for info
-     on its format.
-
-     We don't output a traceback table if -finhibit-size-directive was
-     used.  The documentation for -finhibit-size-directive reads
-     ``don't output a @code{.size} assembler directive, or anything
-     else that would cause trouble if the function is split in the
-     middle, and the two halves are placed at locations far apart in
-     memory.''  The traceback table has this property, since it
-     includes the offset from the start of the function to the
-     traceback table itself.
-
-     System V.4 Powerpc's (and the embedded ABI derived from it) use a
-     different traceback table.  */
-  if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive)
-    {
-      char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
-      int fixed_parms, float_parms, parm_info;
-      int i;
-
-      while (*fname == '.')	/* V.4 encodes . in the name */
-	fname++;
-
-      /* Need label immediately before tbtab, so we can compute its offset
-	 from the function start.  */
-      if (*fname == '*')
-	++fname;
-      ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
-      ASM_OUTPUT_LABEL (file, fname);
-
-      /* The .tbtab pseudo-op can only be used for the first eight
-	 expressions, since it can't handle the possibly variable
-	 length fields that follow.  However, if you omit the optional
-	 fields, the assembler outputs zeros for all optional fields
-	 anyways, giving each variable length field is minimum length
-	 (as defined in sys/debug.h).  Thus we can not use the .tbtab
-	 pseudo-op at all.  */
-
-      /* An all-zero word flags the start of the tbtab, for debuggers
-	 that have to find it by searching forward from the entry
-	 point or from the current pc.  */
-      fputs ("\t.long 0\n", file);
-
-      /* Tbtab format type.  Use format type 0.  */
-      fputs ("\t.byte 0,", file);
-
-      /* Language type.  Unfortunately, there doesn't seem to be any
-	 official way to get this info, so we use language_string.  C
-	 is 0.  C++ is 9.  No number defined for Obj-C, so use the
-	 value for C for now.  There is no official value for Java,
-         although IBM appears to be using 13.  There is no official value
-	 for Chill, so we've choosen 44 pseudo-randomly.  */
-      if (! strcmp (language_string, "GNU C")
-	  || ! strcmp (language_string, "GNU Obj-C"))
-	i = 0;
-      else if (! strcmp (language_string, "GNU F77"))
-	i = 1;
-      else if (! strcmp (language_string, "GNU Ada"))
-	i = 3;
-      else if (! strcmp (language_string, "GNU Pascal"))
-	i = 2;
-      else if (! strcmp (language_string, "GNU C++"))
-	i = 9;
-      else if (! strcmp (language_string, "GNU Java"))
-	i = 13;
-      else if (! strcmp (language_string, "GNU CHILL"))
-	i = 44;
-      else
-	abort ();
-      fprintf (file, "%d,", i);
-
-      /* 8 single bit fields: global linkage (not set for C extern linkage,
-	 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
-	 from start of procedure stored in tbtab, internal function, function
-	 has controlled storage, function has no toc, function uses fp,
-	 function logs/aborts fp operations.  */
-      /* Assume that fp operations are used if any fp reg must be saved.  */
-      fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1));
-
-      /* 6 bitfields: function is interrupt handler, name present in
-	 proc table, function calls alloca, on condition directives
-	 (controls stack walks, 3 bits), saves condition reg, saves
-	 link reg.  */
-      /* The `function calls alloca' bit seems to be set whenever reg 31 is
-	 set up as a frame pointer, even when there is no alloca call.  */
-      fprintf (file, "%d,",
-	       ((1 << 6) | (frame_pointer_needed << 5)
-		| (info->cr_save_p << 1) | (info->lr_save_p)));
-
-      /* 3 bitfields: saves backchain, spare bit, number of fpr saved
-	 (6 bits).  */
-      fprintf (file, "%d,",
-	       (info->push_p << 7) | (64 - info->first_fp_reg_save));
-
-      /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits).  */
-      fprintf (file, "%d,", (32 - first_reg_to_save ()));
-
-      {
-	/* Compute the parameter info from the function decl argument
-	   list.  */
-	tree decl;
-	int next_parm_info_bit;
-
-	next_parm_info_bit = 31;
-	parm_info = 0;
-	fixed_parms = 0;
-	float_parms = 0;
-
-	for (decl = DECL_ARGUMENTS (current_function_decl);
-	     decl; decl = TREE_CHAIN (decl))
-	  {
-	    rtx parameter = DECL_INCOMING_RTL (decl);
-	    enum machine_mode mode = GET_MODE (parameter);
-
-	    if (GET_CODE (parameter) == REG)
-	      {
-		if (GET_MODE_CLASS (mode) == MODE_FLOAT)
-		  {
-		    int bits;
-
-		    float_parms++;
-
-		    if (mode == SFmode)
-		      bits = 0x2;
-		    else if (mode == DFmode)
-		      bits = 0x3;
-		    else
-		      abort ();
-
-		    /* If only one bit will fit, don't or in this entry.  */
-		    if (next_parm_info_bit > 0)
-		      parm_info |= (bits << (next_parm_info_bit - 1));
-		    next_parm_info_bit -= 2;
-		  }
-		else
-		  {
-		    fixed_parms += ((GET_MODE_SIZE (mode)
-				     + (UNITS_PER_WORD - 1))
-				    / UNITS_PER_WORD);
-		    next_parm_info_bit -= 1;
-		  }
-	      }
-	  }
-      }
-
-      /* Number of fixed point parameters.  */
-      /* This is actually the number of words of fixed point parameters; thus
-	 an 8 byte struct counts as 2; and thus the maximum value is 8.  */
-      fprintf (file, "%d,", fixed_parms);
-
-      /* 2 bitfields: number of floating point parameters (7 bits), parameters
-	 all on stack.  */
-      /* This is actually the number of fp registers that hold parameters;
-	 and thus the maximum value is 13.  */
-      /* Set parameters on stack bit if parameters are not in their original
-	 registers, regardless of whether they are on the stack?  Xlc
-	 seems to set the bit when not optimizing.  */
-      fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
-
-      /* Optional fields follow.  Some are variable length.  */
-
-      /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
-	 11 double float.  */
-      /* There is an entry for each parameter in a register, in the order that
-	 they occur in the parameter list.  Any intervening arguments on the
-	 stack are ignored.  If the list overflows a long (max possible length
-	 34 bits) then completely leave off all elements that don't fit.  */
-      /* Only emit this long if there was at least one parameter.  */
-      if (fixed_parms || float_parms)
-	fprintf (file, "\t.long %d\n", parm_info);
-
-      /* Offset from start of code to tb table.  */
-      fputs ("\t.long ", file);
-      ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
-      RS6000_OUTPUT_BASENAME (file, fname);
-      fputs ("-.", file);
-      RS6000_OUTPUT_BASENAME (file, fname);
-      putc ('\n', file);
-
-      /* Interrupt handler mask.  */
-      /* Omit this long, since we never set the interrupt handler bit
-	 above.  */
-
-      /* Number of CTL (controlled storage) anchors.  */
-      /* Omit this long, since the has_ctl bit is never set above.  */
-
-      /* Displacement into stack of each CTL anchor.  */
-      /* Omit this list of longs, because there are no CTL anchors.  */
-
-      /* Length of function name.  */
-      fprintf (file, "\t.short %d\n", (int) strlen (fname));
-
-      /* Function name.  */
-      assemble_string (fname, strlen (fname));
-
-      /* Register for alloca automatic storage; this is always reg 31.
-	 Only emit this if the alloca bit was set above.  */
-      if (frame_pointer_needed)
-	fputs ("\t.byte 31\n", file);
-    }
-
-  if (DEFAULT_ABI == ABI_NT)
-    {
-      RS6000_OUTPUT_BASENAME (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
-      fputs (".e:\nFE_MOT_RESVD..", file);
-      RS6000_OUTPUT_BASENAME (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
-      fputs (":\n", file);
-    }
-}
-
-/* CYGNUS LOCAL -- vmakarov/prolog-epilog instruction scheduling */
-#endif
-
-/* This part (from CYGNUS LOCAL to CYGNUS local) contains code needed
-   for scheduling of prologue and epilogue.  The part is based on the
-   analogous functions above.  Now it works only for EABI.  The code
-   contains new code for RTL generation and old code for assembler
-   output (for output prologue/epilogue for other ABI besides EABI).
-   So now this implementation is different from MIPS one.  When RTL
-   generation for all other ABI is written, the assembler code output
-   (and code above between #if 0 and #endif) can be removed and the
-   implementation will become analogous to MIPS/ARM one.  The code for
-   RTL generation for the following ABI must be finished and tested
-   for this (please pay attention onto 64 bit targets too):
-
-   ABI_AIX, ABI_AIX_NODESC
-   ABI_NT, ABI_SOLARIS  (did they die???)
-
-*/
-
-/* Write out an assembler instruction (if !RTX_FLAG) otherwise RTL
-   insns to load the TOC_TABLE address into register 30.  This is only
-   necessary when TARGET_TOC, TARGET_MINIMAL_TOC, and there is a
-   constant pool.  */
-
-void
-rs6000_output_load_toc_table (file, reg, rtx_flag)
-     FILE *file;
-     int reg;
-     int rtx_flag;
-{
-  char buf[256];
-  rtx insn;
-  enum machine_mode reg_mode = (TARGET_32BIT) ? SImode : DImode;
-
-#ifdef USING_SVR4_H
-  if (TARGET_RELOCATABLE)
-    {
-      if (rtx_flag)
-	{
-	  if (reg != 30)
-	    abort;
-	  insn = emit_call_insn
-	         (TARGET_32BIT
-		  ? gen_loadsi_svr4_relocatable_toc (gen_rtx
-						     (REG, reg_mode, 0))
-		  : gen_loaddi_svr4_relocatable_toc (gen_rtx
-						     (REG, reg_mode, 0)));
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	  return;
-	}
-
-      ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
-      fprintf (file, "\tbl ");
-      assemble_name (file, buf);
-      fprintf (file, "\n");
-
-      /* possibly create the toc section */
-      if (!toc_initialized)
-	{
-	  toc_section ();
-	  function_section (current_function_decl);
-	}
-
-      /* If not first call in this function, we need to put the
-	 different between .LCTOC1 and the address we get to right
-	 after the bl.  It will mess up disassembling the instructions
-	 but that can't be helped.  We will later need to bias the
-	 address before loading.  */
-      if (rs6000_pic_func_labelno != rs6000_pic_labelno)
-	{
-	  char *init_ptr = TARGET_32BIT ? ".long" : ".quad";
-	  char *buf_ptr;
-
-	  ASM_OUTPUT_INTERNAL_LABEL (file, "LCL", rs6000_pic_labelno);
-
-	  ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
-	  STRIP_NAME_ENCODING (buf_ptr, buf);
-	  fprintf (file, "\t%s %s-", init_ptr, buf_ptr);
-
-	  ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
-	  fprintf (file, "%s\n", buf_ptr);
-	}
-
-      ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno);
-      fprintf (file, "\tmflr %s\n", reg_names[reg]);
-
-      if (rs6000_pic_func_labelno != rs6000_pic_labelno)
-	  asm_fprintf(file, "\t{cal|la} %s,%d(%s)\n", reg_names[reg],
-		      (TARGET_32BIT ? 4 : 8), reg_names[reg]);
-
-      asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s,(" : "\tld %s,(",
-		   reg_names[0]);
-      ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
-      assemble_name (file, buf);
-      fputs ("-", file);
-      ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
-      assemble_name (file, buf);
-      fprintf (file, ")(%s)\n", reg_names[reg]);
-      asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
-		   reg_names[reg], reg_names[0], reg_names[reg]);
-      rs6000_pic_labelno++;
-    }
-  else if (!TARGET_64BIT)
-    {
-      if (rtx_flag)
-	{
-	  if (reg != 30)
-	    abort;
-	  insn = emit_insn (gen_loadsi_svr4_toc ());
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	  return;
-	}
-      ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
-      asm_fprintf (file, "\t{liu|lis} %s,", reg_names[reg]);
-      assemble_name (file, buf);
-      fputs ("@ha\n", file);
-      asm_fprintf (file, "\t{cal|la} %s,", reg_names[reg]);
-      assemble_name (file, buf);
-      asm_fprintf (file, "@l(%s)\n", reg_names[reg]);
-    }
-  else
-    abort ();
-
-#else	/* !USING_SVR4_H */
-  if (rtx_flag)
-    {
-      if (reg != 30)
-	abort ();
-      insn
-	= emit_insn (TARGET_32BIT
-		     ? gen_loadsi_nonsvr4_toc (gen_rtx (REG, reg_mode, 2))
-		     : gen_loaddi_nonsvr4_toc (gen_rtx (REG, reg_mode, 2)));
-      RTX_FRAME_RELATED_P (insn) = 1;
-      return;
-    }
-  ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0);
-  asm_fprintf (file, TARGET_32BIT ? "\t{l|lwz} %s," : "\tld %s,",
-	       reg_names[reg]);
-  assemble_name (file, buf);
-  asm_fprintf (file, "(%s)\n", reg_names[2]);
-#endif /* USING_SVR4_H */
-}
-
-
-
-/* Emit the correct code for allocating stack space.  If COPY_R12,
-   make sure a copy of the old frame is left in r12.  We generate RTX
-   instead of assembler code when RTX_FLAG is true. */
-static void
-rs6000_allocate_stack_space (file, size, copy_r12, rtx_flag)
-     FILE *file;
-     int size;
-     int copy_r12;
-     int rtx_flag;
-{
-  int neg_size = -size;
-  rtx insn;
-  enum machine_mode reg_mode = (TARGET_32BIT) ? SImode : DImode;
-
-  if (TARGET_UPDATE)
-    {
-      if (size < 32767)
-	{
-	  if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	    asm_fprintf (file,
-			 (TARGET_32BIT)
-			 ? "\t{stu|stwu} %s,%d(%s)\n" : "\tstdu %s,%d(%s)\n",
-			 reg_names[1], neg_size, reg_names[1]);
-	  else if (rtx_flag)
-	    {
-	      rtx incr = GEN_INT (neg_size);
-
-	      if (TARGET_32BIT)
-		insn = emit_insn (gen_movsi_update (stack_pointer_rtx,
-						    stack_pointer_rtx, incr,
-						    stack_pointer_rtx));
-	      else
-		insn = emit_insn (gen_movdi_update (stack_pointer_rtx,
-						    stack_pointer_rtx, incr,
-						    stack_pointer_rtx));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-      else
-	{
-	  if (copy_r12)
-	    {
-	      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-		fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
-	      else if (rtx_flag)
-		{
-		  rtx r12_rtx = gen_rtx (REG, Pmode, 12);
-
-		  insn = emit_move_insn (r12_rtx, stack_pointer_rtx);
-		  RTX_FRAME_RELATED_P (insn) = 1;
-		}
-	    }
-	  if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	    {
-	      asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
-			   reg_names[0], (neg_size >> 16) & 0xffff,
-			   reg_names[0], reg_names[0], neg_size & 0xffff);
-	      asm_fprintf (file,
-			   (TARGET_32BIT)
-			   ? "\t{stux|stwux} %s,%s,%s\n"
-			   : "\tstdux %s,%s,%s\n",
-			   reg_names[1], reg_names[1], reg_names[0]);
-	    }
-	  else if (rtx_flag)
-	    {
-	      rtx r0_rtx = gen_rtx (REG, reg_mode, 0);
-	      rtx const_int_rtx;
-	      
-	      const_int_rtx = GEN_INT (((neg_size >> 16) & 0xffff) << 16);
-	      insn = emit_insn (gen_rtx (SET, VOIDmode,
-					 r0_rtx, const_int_rtx));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	      const_int_rtx = GEN_INT (neg_size & 0xffff);
-	      insn = emit_insn (TARGET_32BIT
-				? gen_iorsi3 (r0_rtx, r0_rtx, const_int_rtx)
-				: gen_iordi3 (r0_rtx, r0_rtx, const_int_rtx));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	      insn = emit_insn (TARGET_32BIT
-				? gen_movsi_update (stack_pointer_rtx,
-						    stack_pointer_rtx, r0_rtx,
-						    stack_pointer_rtx)
-				: gen_movdi_update (stack_pointer_rtx,
-						    stack_pointer_rtx, r0_rtx,
-						    stack_pointer_rtx));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-    }
-  else
-    {
-      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
-      else if (rtx_flag)
-	{
-	  rtx r12_rtx = gen_rtx (REG, Pmode, 12);
-	  
-	  insn = emit_move_insn (r12_rtx, stack_pointer_rtx);
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	}
-      if (size < 32767)
-	{
-	  if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	    asm_fprintf (file, "\t{cal|la} %s,%d(%s)\n",
-			 reg_names[1], neg_size, reg_names[1]);
-	  else if (rtx_flag)
-	    {
-	      rtx reg_rtx = gen_rtx (REG, reg_mode, 1);
-	      
-	      insn = emit_insn (gen_addsi3 (reg_rtx, reg_rtx,
-					    GEN_INT (neg_size)));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-      else
-	{
-	  if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	    {
-	      asm_fprintf (file,
-			   "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
-			   reg_names[0], (neg_size >> 16) & 0xffff,
-			   reg_names[0], reg_names[0], neg_size & 0xffff);
-	    }
-	  else if (rtx_flag)
-	    {
-	      rtx r0_rtx = gen_rtx (REG, reg_mode, 0);
-	      rtx const_int_rtx;
-	      
-	      const_int_rtx = GEN_INT (((neg_size >> 16) & 0xffff) << 16);
-	      insn = emit_insn (gen_rtx (SET, VOIDmode, r0_rtx,
-					 const_int_rtx));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	      const_int_rtx = GEN_INT (neg_size & 0xffff);
-	      insn = emit_insn (TARGET_32BIT
-				? gen_iorsi3 (r0_rtx, r0_rtx, const_int_rtx)
-				: gen_iordi3 (r0_rtx, r0_rtx, const_int_rtx));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	  if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	    asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", reg_names[1],
-			 reg_names[0], reg_names[1]);
-	  else if (rtx_flag)
-	    {
-	      rtx r0_rtx = gen_rtx (REG, reg_mode, 0);
-	      rtx r1_rtx = gen_rtx (REG, reg_mode, 1);
-	      
-	      insn = emit_insn (TARGET_32BIT
-				? gen_addsi3 (r1_rtx, r0_rtx, r1_rtx)
-				: gen_adddi3 (r1_rtx, r0_rtx, r1_rtx));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-
-      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	asm_fprintf (file,
-		     (TARGET_32BIT)
-		     ? "\t{st|stw} %s,0(%s)\n" : "\tstd %s,0(%s)\n",
-		     reg_names[12], reg_names[1]);
-      else if (rtx_flag)
-	{
-	  rtx r12_rtx = gen_rtx (REG, reg_mode, 12);
-	  rtx r1_rtx = gen_rtx (REG, Pmode, 1);
-	      
-	  insn = emit_move_insn (gen_rtx (MEM, reg_mode, r1_rtx), r12_rtx);
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	}
-    }
-}
-
-
-/* Write function prologue.  The function is called twice with two
-   different values of RTX_FLAG.  Generate or not rtl or assembler
-   code is depended from value of TARGET_SCHED_PROLOG. */
-
-static void
-rs6000_prolog (file, rtx_flag, info)
-     FILE *file;
-     int rtx_flag;
-     rs6000_stack_t *info;
-{
-  int reg_size = info->reg_size;
-  char *store_reg;
-  char *load_reg;
-  int sp_reg = 1;
-  int sp_offset = 0;
-  enum machine_mode reg_mode;
-  rtx insn;
-  rtx sp_reg_rtx = stack_pointer_rtx;
-
-  if (TARGET_32BIT)
-    {
-      store_reg = "\t{st|stw} %s,%d(%s)\n";
-      load_reg = "\t{l|lwz} %s,%d(%s)\n";
-      reg_mode = SImode;
-    }
-  else
-    {
-      store_reg = "\tstd %s,%d(%s)\n";
-      load_reg = "\tlld %s,%d(%s)\n";
-      reg_mode = DImode;
-    }
-
-  if (TARGET_DEBUG_STACK)
-    debug_stack_info (info);
-
-  /* Write .extern for any function we will call to save and restore fp
-     values.  */
-  if (!rtx_flag && info->first_fp_reg_save < 64
-      && !FP_SAVE_INLINE (info->first_fp_reg_save))
-    fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
-	     SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
-	     RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
-	     RESTORE_FP_SUFFIX);
-
-  /* Write .extern for truncation routines, if needed.  */
-  if (!rtx_flag && rs6000_trunc_used && ! trunc_defined)
-    {
-      fprintf (file, "\t.extern .%s\n\t.extern .%s\n",
-	       RS6000_ITRUNC, RS6000_UITRUNC);
-      trunc_defined = 1;
-    }
-
-  /* Write .extern for AIX common mode routines, if needed.  */
-  if (!rtx_flag && !TARGET_POWER && !TARGET_POWERPC && !common_mode_defined)
-    {
-      fputs ("\t.extern __mulh\n", file);
-      fputs ("\t.extern __mull\n", file);
-      fputs ("\t.extern __divss\n", file);
-      fputs ("\t.extern __divus\n", file);
-      fputs ("\t.extern __quoss\n", file);
-      fputs ("\t.extern __quous\n", file);
-      common_mode_defined = 1;
-    }
-
-  /* For V.4, update stack before we do any saving and set back pointer.  */
-  if (info->push_p && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
-    {
-      if (info->total_size < 32767)
-	sp_offset = info->total_size;
-      else
-	{
-	  sp_reg = 12;
-	  sp_reg_rtx = gen_rtx (REG, Pmode, 12);
-	}
-      rs6000_allocate_stack_space (file, info->total_size, sp_reg == 12,
-				   rtx_flag);
-    }
-
-  /* If we use the link register, get it into r0.  */
-  if (info->lr_save_p)
-    {
-      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
-      else if (rtx_flag)
-	{
-	  insn = emit_move_insn (gen_rtx (REG, Pmode, 0),
-				 gen_rtx (REG, Pmode, 65));
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	}
-    }
-  /* If we need to save CR, put it into r12.  */
-  if (info->cr_save_p && sp_reg != 12)
-    {
-      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	asm_fprintf (file, "\tmfcr %s\n", reg_names[12]);
-      else if (rtx_flag)
-	{
-	  insn = emit_insn (TARGET_32BIT
-			    ? gen_movesi_from_cr (gen_rtx (REG, reg_mode, 12))
-			    : gen_movedi_from_cr (gen_rtx
-						  (REG, reg_mode, 12)));
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	}
-    }
-
-  /* Do any required saving of fpr's.  If only one or two to save, do it
-     ourself.  Otherwise, call function.  Note that since they are statically
-     linked, we do not need a nop following them.  */
-  if (FP_SAVE_INLINE (info->first_fp_reg_save))
-    {
-      int regno = info->first_fp_reg_save;
-      int loc   = info->fp_save_offset + sp_offset;
-
-      for ( ; regno < 64; regno++, loc += 8)
-	if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	  asm_fprintf (file, "\tstfd %s,%d(%s)\n",
-		       reg_names[regno], loc, reg_names[sp_reg]);
-	else if (rtx_flag)
-	  {
-	    insn = emit_move_insn (gen_rtx
-				   (MEM, DFmode,
-				    gen_rtx (PLUS, Pmode,
-					     sp_reg_rtx, GEN_INT (loc))),
-				   gen_rtx (REG, DFmode, regno));
-	    RTX_FRAME_RELATED_P (insn) = 1;
-	  }
-    }
-  else if (info->first_fp_reg_save != 64)
-    {
-      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX,
-		     info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
-      else if (rtx_flag)
-	{
-	  static char label [100];
-	  
-	  sprintf (label, "%s%d%s", SAVE_FP_PREFIX,
-		   info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
-	  insn = emit_jump_insn (gen_jump (gen_rtx (SYMBOL_REF, Pmode,
-						    label)));
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	}
-    }
-
-  /* Now save gpr's.  */
-  if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
-    {
-      int regno    = info->first_gp_reg_save;
-      int loc      = info->gp_save_offset + sp_offset;
-
-      for ( ; regno < 32; regno++, loc += reg_size)
-	if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	  asm_fprintf (file, store_reg,
-		       reg_names[regno], loc, reg_names[sp_reg]);
-	else if (rtx_flag)
-	  {
-	    insn = emit_move_insn (gen_rtx (MEM, reg_mode,
-					    gen_rtx (PLUS, Pmode, sp_reg_rtx,
-						     GEN_INT (loc))),
-				   gen_rtx (REG, reg_mode, regno));
-	    RTX_FRAME_RELATED_P (insn) = 1;
-	  }
-    }
-  else if (info->first_gp_reg_save != 32)
-    {
-      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	asm_fprintf (file, "\t{stm|stmw} %s,%d(%s)\n",
-		     reg_names[info->first_gp_reg_save],
-		     info->gp_save_offset + sp_offset,
-		     reg_names[sp_reg]);
-      else if (rtx_flag)
-	{
-	  int loc;
-	  int regno;
-
-	  for (loc = info->gp_save_offset + sp_offset,
-		 regno = info->first_gp_reg_save;
-	       regno <= 31;
-	     regno++, loc += reg_size)
-	    {
-	      insn = emit_move_insn (gen_rtx (MEM, reg_mode,
-					      gen_rtx (PLUS, Pmode,
-						       sp_reg_rtx,
-						       GEN_INT (loc))),
-				     gen_rtx (REG, reg_mode, regno));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-    }
-  /* Save main's arguments if we need to call a function */
-#ifdef NAME__MAIN
-  if (info->main_save_p)
-    {
-      int regno;
-      int loc = info->main_save_offset + sp_offset;
-      int size = info->main_size;
-
-      for (regno = 3; size > 0; regno++, loc += reg_size, size -= reg_size)
-	if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	  asm_fprintf (file, store_reg,
-		       reg_names[regno], loc, reg_names[sp_reg]);
-	else if (rtx_flag)
-	  {
-	    insn = emit_move_insn (gen_rtx (MEM, reg_mode,
-					    gen_rtx (PLUS, Pmode, sp_reg_rtx,
-						     GEN_INT (loc))),
-				   gen_rtx (REG, reg_mode, regno));
-	    RTX_FRAME_RELATED_P (insn) = 1;
-	  }
-    }
-#endif
-
-  /* Save lr if we used it.  */
-  if (info->lr_save_p)
-    {
-      int loc = info->lr_save_offset + sp_offset;
-
-      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	asm_fprintf (file, store_reg, reg_names[0], loc, reg_names[sp_reg]);
-      else if (rtx_flag)
-	{
-	  insn = emit_move_insn (gen_rtx (MEM, reg_mode,
-					  gen_rtx (PLUS, Pmode, sp_reg_rtx,
-						   GEN_INT (loc))),
-				 gen_rtx (REG, reg_mode, 0));
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	}
-    }
-
-  /* Save CR if we use any that must be preserved.  */
-  if (info->cr_save_p)
-    {
-      int loc = info->cr_save_offset + sp_offset;
-
-      if (sp_reg == 12)
-	/* If r12 is used to hold the original sp, copy cr now */
-	{
-	  if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	    {
-	      asm_fprintf (file, "\tmfcr %s\n", reg_names[0]);
-	      asm_fprintf (file, store_reg, reg_names[0],
-			   loc, reg_names[sp_reg]);
-	    }
-	  else if (rtx_flag)
-	    {
-	      insn = emit_insn (TARGET_32BIT
-				? gen_movesi_from_cr (gen_rtx
-						      (REG, reg_mode, 0))
-				: gen_movedi_from_cr (gen_rtx
-						      (REG, reg_mode, 0)));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	      insn = emit_move_insn (gen_rtx (MEM, reg_mode,
-					      gen_rtx (PLUS, Pmode,
-						       sp_reg_rtx,
-						       GEN_INT (loc))),
-				     gen_rtx (REG, reg_mode, 0));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-      else
-	{
-	  if (!rtx_flag && !TARGET_SCHED_PROLOG)
-
-	    asm_fprintf (file, store_reg, reg_names[12],
-			 loc, reg_names[sp_reg]);
-
-	  else if (rtx_flag)
-	    {
-	      insn = emit_move_insn (gen_rtx (MEM, reg_mode,
-					      gen_rtx (PLUS, Pmode,
-						       sp_reg_rtx,
-						       GEN_INT (loc))),
-				     gen_rtx (REG, reg_mode, 12));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-    }
-
-  /* NT needs us to probe the stack frame every 4k pages for large frames, so
-     do it here.  */
-  if (DEFAULT_ABI == ABI_NT && info->total_size > 4096)
-    {
-      if (info->total_size < 32768)
-	{
-	  int probe_offset = 4096;
-	  while (probe_offset < info->total_size)
-	    {
-	      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-		asm_fprintf (file, "\t{l|lwz} %s,%d(%s)\n",
-			     reg_names[0], -probe_offset, reg_names[1]);
-	      else if (rtx_flag)
-		{
-		  insn = emit_move_insn (gen_rtx (REG, reg_mode, 0),
-					 gen_rtx
-					 (MEM, reg_mode,
-					  gen_rtx (PLUS, Pmode,
-						   stack_pointer_rtx,
-						   GEN_INT (-probe_offset))));
-		  RTX_FRAME_RELATED_P (insn) = 1;
-		}
-	      probe_offset += 4096;
-	    }
-	}
-      else
-	{
-	  int probe_iterations = info->total_size / 4096;
-	  static int probe_labelno = 0;
-	  char buf[256];
-	  rtx r12_rtx = gen_rtx (REG, reg_mode, 12);
-	  rtx r0_rtx = gen_rtx (REG, reg_mode, 0);
-
-	  if (probe_iterations < 32768)
-	    {
-	      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-		asm_fprintf (file, "\tli %s,%d\n",
-			     reg_names[12], probe_iterations);
-	      else if (rtx_flag)
-		{
-		  insn
-		    = emit_insn (TARGET_32BIT
-				 ? gen_addsi3 (r12_rtx, r0_rtx,
-					       GEN_INT (probe_iterations))
-				 : gen_adddi3 (r12_rtx, r0_rtx,
-					       GEN_INT (probe_iterations)));
-		  RTX_FRAME_RELATED_P (insn) = 1;
-		}
-	    }
-	  else
-	    {
-	      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-		asm_fprintf (file, "\tlis %s,%d\n",
-			     reg_names[12], probe_iterations >> 16);
-	      else if (rtx_flag)
-		{
-		  insn = emit_insn (TARGET_32BIT
-				    ? gen_addsi3 (r12_rtx, r0_rtx,
-						  GEN_INT ((probe_iterations
-							    >> 16) << 16))
-				    : gen_adddi3 (r12_rtx, r0_rtx,
-						  GEN_INT ((probe_iterations
-							    >> 16) << 16)));
-		  RTX_FRAME_RELATED_P (insn) = 1;
-		}
-	      if (probe_iterations & 0xffff)
-		{
-		  rtx const_int_rtx;
-
-		  if (!rtx_flag && !TARGET_SCHED_PROLOG)
-		    asm_fprintf (file, "\tori %s,%s,%d\n", reg_names[12],
-				 reg_names[12], probe_iterations & 0xffff);
-		  else if (rtx_flag)
-		    {
-		      const_int_rtx = GEN_INT (probe_iterations & 0xffff);
-
-		      insn = emit_insn (TARGET_32BIT
-					? gen_iorsi3 (r12_rtx, r12_rtx,
-						      const_int_rtx)
-					: gen_iordi3 (r12_rtx, r12_rtx,
-						      const_int_rtx));
-		      RTX_FRAME_RELATED_P (insn) = 1;
-		    }
-		}
-	    }
-
-	  if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	    {
-	      asm_fprintf (file, "\tmtctr %s\n", reg_names[12]);
-	      asm_fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
-	      ASM_OUTPUT_INTERNAL_LABEL (file, "LCprobe", probe_labelno);
-	      asm_fprintf (file, "\t{lu|lwzu} %s,-4096(%s)\n",
-			   reg_names[0], reg_names[12]);
-	      ASM_GENERATE_INTERNAL_LABEL (buf, "LCprobe", probe_labelno++);
-	      fputs ("\tbdnz ", file);
-	      assemble_name (file, buf);
-	      fputs ("\n", file);
-	    }
-	  else if (rtx_flag)
-	    {
-	      abort (); /* ??? vmakarov: Not implemented yet (ABI_NT). */
-	    }
-	}
-    }
-
-  /* Update stack and set back pointer unless this is V.4, which was
-     done previously */
-  if (info->push_p && DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
-    rs6000_allocate_stack_space (file, info->total_size, FALSE, rtx_flag);
-
-  /* Set frame pointer, if needed.  */
-  if (frame_pointer_needed)
-    {
-      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	asm_fprintf (file, "\tmr %s,%s\n", reg_names[31], reg_names[1]);
-      else if (rtx_flag)
-	{
-	  insn = emit_move_insn (gen_rtx (REG, reg_mode, 31),
-				 gen_rtx (REG, reg_mode, 1));
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	}
-    }
-
-#ifdef NAME__MAIN
-  /* If we need to call a function to set things up for main, do so now
-     before dealing with the TOC.  */
-  if (info->main_p)
-    {
-      char *prefix = "";
-
-      switch (DEFAULT_ABI)
-	{
-	case ABI_AIX:	prefix = ".";	break;
-	case ABI_NT:	prefix = "..";	break;
-	}
-
-      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	{
-	  fprintf (file, "\tbl %s%s\n", prefix, NAME__MAIN);
-#ifdef RS6000_CALL_GLUE2
-	  fprintf (file, "\t%s%s%s\n", RS6000_CALL_GLUE2, prefix, NAME_MAIN);
-#else
-#ifdef RS6000_CALL_GLUE
-	  if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
-	    fprintf (file, "\t%s\n", RS6000_CALL_GLUE);
-#endif
-#endif
-	}
-      else if (rtx_flag)
-	{
-	  static char name [100];
-
-	  sprintf (name, "%s%s", prefix, NAME__MAIN);
-	  insn = emit_call_insn (gen_rtx
-				 (PARALLEL, VOIDmode,
-				  gen_rtvec
-				  (3,
-				   gen_rtx (CALL, VOIDmode,
-					    gen_rtx (MEM, FUNCTION_MODE,
-						     gen_rtx (SYMBOL_REF,
-							      Pmode, name)),
-					    const0_rtx),
-				   gen_rtx (USE, VOIDmode, const0_rtx),
-				   gen_rtx (CLOBBER, VOIDmode,
-					    gen_rtx (REG, reg_mode, 65)))));
-	  RTX_FRAME_RELATED_P (insn) = 1;
-	}
-
-      if (info->main_save_p)
-	{
-	  int regno;
-	  int loc;
-	  int size = info->main_size;
-
-	  if (info->total_size < 32767)
-	    {
-	      loc = info->total_size + info->main_save_offset;
-	      for (regno = 3;
-		   size > 0;
-		   regno++, size -= reg_size, loc += reg_size)
-		if (!rtx_flag && !TARGET_SCHED_PROLOG)
-		  asm_fprintf (file, load_reg,
-			       reg_names[regno], loc, reg_names[1]);
-		else if (rtx_flag)
-		  {
-		    insn = emit_move_insn (gen_rtx (REG, reg_mode, regno),
-					   gen_rtx
-					   (MEM, reg_mode,
-					    gen_rtx (PLUS, Pmode,
-						     stack_pointer_rtx,
-						     GEN_INT (loc))));
-		    RTX_FRAME_RELATED_P (insn) = 1;
-		  }
-	    }
-	  else
-	    {
-	      int neg_size = info->main_save_offset - info->total_size;
-	      loc = 0;
-
-	      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-		{
-		  asm_fprintf (file,
-			       "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
-			       reg_names[0], (neg_size >> 16) & 0xffff,
-			       reg_names[0], reg_names[0], neg_size & 0xffff);
-		  asm_fprintf (file, "\t{sf|subf} %s,%s,%s\n",
-			       reg_names[0], reg_names[0], reg_names[1]);
-		}
-	      else if (rtx_flag)
-		{
-		  rtx r0_rtx = gen_rtx (REG, reg_mode, 0);
-		  rtx const_int_rtx;
-	  
-		  const_int_rtx = GEN_INT (((neg_size >> 16) & 0xffff) << 16);
-		  insn = emit_insn (gen_rtx (SET, VOIDmode, r0_rtx,
-					     const_int_rtx));
-		  RTX_FRAME_RELATED_P (insn) = 1;
-		  const_int_rtx = GEN_INT (neg_size & 0xffff);
-		  insn = emit_insn (TARGET_32BIT
-				    ? gen_iorsi3 (r0_rtx, r0_rtx,
-						  const_int_rtx)
-				    : gen_iordi3 (r0_rtx, r0_rtx,
-						  const_int_rtx));
-		  RTX_FRAME_RELATED_P (insn) = 1;
-		  insn = emit_insn (gen_rtx (MINUS, reg_mode,
-					     r0_rtx,
-					     gen_rtx (REG, reg_mode, 1),
-					     r0_rtx));
-		  RTX_FRAME_RELATED_P (insn) = 1;
-		}
-
-	      for (regno = 3;
-		   size > 0;
-		   regno++, size -= reg_size, loc += reg_size)
-		if (!rtx_flag && !TARGET_SCHED_PROLOG)
-		  asm_fprintf (file, load_reg,
-			       reg_names[regno], loc, reg_names[0]);
-		else if (rtx_flag)
-		  {
-		    insn = emit_move_insn (gen_rtx (REG, reg_mode, regno),
-					   gen_rtx
-					   (MEM, reg_mode,
-					    gen_rtx (PLUS, Pmode,
-						     gen_rtx (REG, reg_mode,
-							      0),
-						     GEN_INT (loc))));
-		    RTX_FRAME_RELATED_P (insn) = 1;
-		  }
-	    }
-	}
-    }
-#endif
-
-
-  /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
-     TOC_TABLE address into register 30.  */
-  if (TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
-    {
-#ifdef USING_SVR4_H
-      if (!profile_flag)
-	rs6000_pic_func_labelno = rs6000_pic_labelno;
-#endif
-      /* There is no oportuntity to optimize loading toc table --
-         linear dependecies. */
-      if (!rtx_flag && !TARGET_SCHED_PROLOG)
-	rs6000_output_load_toc_table (file, 30, FALSE);
-      else if (rtx_flag)
-	rs6000_output_load_toc_table (file, 30, TRUE);
-    }
-
-  if (DEFAULT_ABI == ABI_NT)
-    {
-      assemble_name (file,
-		     XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
-      fputs (".b:\n", file);
-    }
-}
-
-/* Write function epilogue.  The function is called twice with two
-   different values of RTX_FLAG.  Generate or not rtl or assembler
-   code is depended from value of TARGET_SCHED_PROLOG. */
-
-static void
-rs6000_epilog (file, rtx_flag, info)
-     FILE *file;
-     int rtx_flag;
-     rs6000_stack_t *info;
-{
-  char *load_reg = ((TARGET_32BIT) ?
-		    "\t{l|lwz} %s,%d(%s)\n" : "\tld %s,%d(%s)\n");
-  enum machine_mode reg_mode = (TARGET_32BIT) ? SImode : DImode;
-  rtx insn = get_last_insn ();
-  int sp_reg = 1;
-  rtx sp_reg_rtx = gen_rtx (REG, reg_mode, 1);
-  int sp_offset = 0;
-
-  /* If the last insn was a BARRIER, we don't have to write anything except
-     the trace table.  */
-  if (insn != 0 && GET_CODE (insn) == NOTE)
-    insn = prev_nonnote_insn (insn);
-  if (insn == 0 ||  GET_CODE (insn) != BARRIER)
-    {
-      /* If we have a frame pointer, a call to alloca,  or a large stack
-	 frame, restore the old stack pointer using the backchain.  Otherwise,
-	 we know what size to update it with.  */
-      if (frame_pointer_needed || current_function_calls_alloca
-	  || info->total_size > 32767)
-	{
-	  /* Under V.4, don't reset the stack pointer until after we're done
-	     loading the saved registers.  */
-	  if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-	    {
-	      sp_reg = 11;
-	      sp_reg_rtx = gen_rtx (REG, reg_mode, 11);
-	    }
-	  if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	    asm_fprintf (file, load_reg, reg_names[sp_reg], 0, reg_names[1]);
-	  else if (rtx_flag)
-	    {
-	      insn = emit_move_insn (sp_reg_rtx,
-				     gen_rtx
-				     (MEM, reg_mode,
-				      gen_rtx (PLUS, Pmode,
-					       gen_rtx (REG, reg_mode, 1),
-					       const0_rtx)));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-      else if (info->push_p)
-	{
-	  if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-	    sp_offset = info->total_size;
-	  else
-	    {
-	      if (!rtx_flag && !TARGET_SCHED_EPILOG)
-		asm_fprintf (file, "\t{cal|la} %s,%d(%s)\n",
-			     reg_names[1], info->total_size, reg_names[1]);
-	      else if (rtx_flag)
-		{
-		  rtx reg_rtx = gen_rtx (REG, reg_mode, 1);
-
-		  insn
-		    = emit_insn (TARGET_32BIT
-				 ? gen_addsi3 (reg_rtx, reg_rtx,
-					       GEN_INT (info->total_size))
-				 : gen_adddi3 (reg_rtx, reg_rtx,
-					       GEN_INT (info->total_size)));
-		  RTX_FRAME_RELATED_P (insn) = 1;
-		}
-	    }
-	}
-
-      /* Get the old lr if we saved it.  */
-      if (info->lr_save_p)
-	{
-	  if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	    asm_fprintf (file, load_reg, reg_names[0],
-			 info->lr_save_offset + sp_offset, reg_names[sp_reg]);
-	  else if (rtx_flag)
-	    {
-	      insn = emit_move_insn (gen_rtx (REG, reg_mode, 0),
-				     gen_rtx
-				     (MEM, reg_mode,
-				      gen_rtx (PLUS, Pmode,
-					       sp_reg_rtx,
-					       GEN_INT (info->lr_save_offset
-							+ sp_offset))));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-
-      /* Get the old cr if we saved it.  */
-      if (info->cr_save_p)
-	{
-	  if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	    asm_fprintf (file, load_reg, reg_names[12],
-			 info->cr_save_offset + sp_offset, reg_names[sp_reg]);
-	  else if (rtx_flag)
-	    {
-	      insn = emit_move_insn (gen_rtx (REG, reg_mode, 12),
-				     gen_rtx
-				     (MEM, reg_mode,
-				      gen_rtx (PLUS, Pmode,
-					       sp_reg_rtx,
-					       GEN_INT (info->cr_save_offset
-							+ sp_offset))));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-
-      /* Set LR here to try to overlap restores below.  */
-      if (info->lr_save_p)
-	{
-	  if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	    asm_fprintf (file, "\tmtlr %s\n", reg_names[0]);
-	  else if (rtx_flag)
-	    {
-	      insn = emit_move_insn (gen_rtx (REG, reg_mode, 65),
-				     gen_rtx (REG, reg_mode, 0));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-
-      /* Restore gpr's.  */
-      if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
-	{
-	  int regno    = info->first_gp_reg_save;
-	  int loc      = info->gp_save_offset + sp_offset;
-	  int reg_size = (TARGET_32BIT) ? 4 : 8;
-
-	  for ( ; regno < 32; regno++, loc += reg_size)
-	    if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	      asm_fprintf (file, load_reg,
-			   reg_names[regno], loc, reg_names[sp_reg]);
-	    else if (rtx_flag)
-	      {
-		insn = emit_move_insn (gen_rtx (REG, reg_mode, regno),
-				       gen_rtx
-				       (MEM, reg_mode,
-					gen_rtx (PLUS, Pmode,
-						 sp_reg_rtx, GEN_INT (loc))));
-		RTX_FRAME_RELATED_P (insn) = 1;
-	      }
-	}
-      else if (info->first_gp_reg_save != 32)
-	{
-	  if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	    asm_fprintf (file, "\t{lm|lmw} %s,%d(%s)\n",
-			 reg_names[info->first_gp_reg_save],
-			 info->gp_save_offset + sp_offset,
-			 reg_names[sp_reg]);
-	  else if (rtx_flag)
-	    {
-	      int loc;
-	      int regno;
-	      int reg_size = (TARGET_32BIT) ? 4 : 8;
-
-	      for (loc = info->gp_save_offset + sp_offset,
-		     regno = info->first_gp_reg_save;
-		   regno <= 31;
-		   regno++, loc += reg_size)
-		{
-		  insn = emit_move_insn (gen_rtx (REG, reg_mode, regno),
-					 gen_rtx (MEM, reg_mode,
-						  gen_rtx (PLUS, Pmode,
-							   sp_reg_rtx,
-							   GEN_INT (loc))));
-		  RTX_FRAME_RELATED_P (insn) = 1;
-		}
-	    }
-	}
-
-      /* Restore fpr's if we can do it without calling a function.  */
-      if (FP_SAVE_INLINE (info->first_fp_reg_save))
-	{
-	  int regno = info->first_fp_reg_save;
-	  int loc   = info->fp_save_offset + sp_offset;
-
-	  for ( ; regno < 64; regno++, loc += 8)
-	    if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	      asm_fprintf (file, "\tlfd %s,%d(%s)\n",
-			   reg_names[regno], loc, reg_names[sp_reg]);
-	    else if (rtx_flag)
-	      {
-		insn = emit_move_insn (gen_rtx (REG, DFmode, regno),
-				       gen_rtx
-				       (MEM, DFmode,
-					gen_rtx (PLUS, Pmode,
-						 sp_reg_rtx, GEN_INT (loc))));
-		RTX_FRAME_RELATED_P (insn) = 1;
-	      }
-	}
-
-      /* If we saved cr, restore it here.  Just those of cr2, cr3, and cr4
-	 that were used.  */
-      if (info->cr_save_p)
-	{
-	  if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	    asm_fprintf (file, "\tmtcrf %d,%s\n",
-			 (regs_ever_live[70] != 0) * 0x20
-			 + (regs_ever_live[71] != 0) * 0x10
-			 + (regs_ever_live[72] != 0) * 0x8, reg_names[12]);
-	  else if (rtx_flag)
-	    {
-	      rtx r12_rtx = gen_rtx (REG, reg_mode, 12);
-	      
-	      insn = emit_insn (TARGET_32BIT
-				? gen_movesi_to_cr (r12_rtx)
-				: gen_movedi_to_cr (r12_rtx));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-      
-
-      /* If this is V.4, unwind the stack pointer after all of the loads
-	 have been done */
-      if (sp_offset != 0)
-	{
-	  if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	    asm_fprintf (file, "\t{cal|la} %s,%d(%s)\n",
-			 reg_names[1], sp_offset, reg_names[1]);
-	  else if (rtx_flag)
-	    {
-	      rtx reg_rtx = gen_rtx (REG, reg_mode, 1);
-	      
-	      insn = emit_insn (TARGET_32BIT
-				? gen_addsi3 (reg_rtx, reg_rtx,
-					      GEN_INT (sp_offset))
-				: gen_adddi3 (reg_rtx, reg_rtx,
-					      GEN_INT (sp_offset)));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-      else if (sp_reg != 1)
-	{
-	  if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	    asm_fprintf (file, "\tmr %s,%s\n",
-			 reg_names[1], reg_names[sp_reg]);
-	  else if (rtx_flag)
-	    {
-	      insn = emit_move_insn (gen_rtx (REG, reg_mode, 1), sp_reg_rtx);
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-      /* If we have to restore more than two FP registers, branch to the
-	 restore function.  It will return to our caller.  */
-      if (info->first_fp_reg_save != 64
-	  && !FP_SAVE_INLINE (info->first_fp_reg_save))
-	{
-	  if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	    asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX,
-			 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
-	  else if (rtx_flag)
-	    {
-	      static char label [100];
-
-	      sprintf (label, "%s%d%s", RESTORE_FP_PREFIX,
-		       info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
-	      insn = emit_jump_insn (gen_jump (gen_rtx (SYMBOL_REF, Pmode,
-							label)));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-      else
-	{
-	  if (!rtx_flag && !TARGET_SCHED_EPILOG)
-	    asm_fprintf (file, "\t{br|blr}\n");
-	  else if (rtx_flag)
-	    {
-	      insn = emit_jump_insn (gen_indirect_jump
-				     (gen_rtx (REG, reg_mode, 65)));
-	      RTX_FRAME_RELATED_P (insn) = 1;
-	    }
-	}
-    }
-
-  /* Output a traceback table here.  See /usr/include/sys/debug.h for info
-     on its format.
-
-     We don't output a traceback table if -finhibit-size-directive was
-     used.  The documentation for -finhibit-size-directive reads
-     ``don't output a @code{.size} assembler directive, or anything
-     else that would cause trouble if the function is split in the
-     middle, and the two halves are placed at locations far apart in
-     memory.''  The traceback table has this property, since it
-     includes the offset from the start of the function to the
-     traceback table itself.
-
-     System V.4 Powerpc's (and the embedded ABI derived from it) use a
-     different traceback table.  */
-  if (!rtx_flag && DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive)
-    {
-      char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
-      int fixed_parms, float_parms, parm_info;
-      int i;
-
-      while (*fname == '.')	/* V.4 encodes . in the name */
-	fname++;
-
-      /* Need label immediately before tbtab, so we can compute its offset
-	 from the function start.  */
-      if (*fname == '*')
-	++fname;
-      ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
-      ASM_OUTPUT_LABEL (file, fname);
-
-      /* The .tbtab pseudo-op can only be used for the first eight
-	 expressions, since it can't handle the possibly variable
-	 length fields that follow.  However, if you omit the optional
-	 fields, the assembler outputs zeros for all optional fields
-	 anyways, giving each variable length field is minimum length
-	 (as defined in sys/debug.h).  Thus we can not use the .tbtab
-	 pseudo-op at all.  */
-
-      /* An all-zero word flags the start of the tbtab, for debuggers
-	 that have to find it by searching forward from the entry
-	 point or from the current pc.  */
-      fputs ("\t.long 0\n", file);
-
-      /* Tbtab format type.  Use format type 0.  */
-      fputs ("\t.byte 0,", file);
-
-      /* Language type.  Unfortunately, there doesn't seem to be any
-	 official way to get this info, so we use language_string.  C
-	 is 0.  C++ is 9.  No number defined for Obj-C, so use the
-	 value for C for now.  There is no official value for Java,
-         although IBM appears to be using 13.  There is no official value
-	 for Chill, so we've choosen 44 pseudo-randomly.  */
-      if (! strcmp (language_string, "GNU C")
-	  || ! strcmp (language_string, "GNU Obj-C"))
-	i = 0;
-      else if (! strcmp (language_string, "GNU F77"))
-	i = 1;
-      else if (! strcmp (language_string, "GNU Ada"))
-	i = 3;
-      else if (! strcmp (language_string, "GNU Pascal"))
-	i = 2;
-      else if (! strcmp (language_string, "GNU C++"))
-	i = 9;
-      else if (! strcmp (language_string, "GNU Java"))
-	i = 13;
-      else if (! strcmp (language_string, "GNU CHILL"))
-	i = 44;
-      else
-	abort ();
-      fprintf (file, "%d,", i);
-
-      /* 8 single bit fields: global linkage (not set for C extern linkage,
-	 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
-	 from start of procedure stored in tbtab, internal function, function
-	 has controlled storage, function has no toc, function uses fp,
-	 function logs/aborts fp operations.  */
-      /* Assume that fp operations are used if any fp reg must be saved.  */
-      fprintf (file, "%d,",
-	       (1 << 5) | ((info->first_fp_reg_save != 64) << 1));
-
-      /* 6 bitfields: function is interrupt handler, name present in
-	 proc table, function calls alloca, on condition directives
-	 (controls stack walks, 3 bits), saves condition reg, saves
-	 link reg.  */
-      /* The `function calls alloca' bit seems to be set whenever reg 31 is
-	 set up as a frame pointer, even when there is no alloca call.  */
-      fprintf (file, "%d,",
-	       ((1 << 6) | (frame_pointer_needed << 5)
-		| (info->cr_save_p << 1) | (info->lr_save_p)));
-
-      /* 3 bitfields: saves backchain, spare bit, number of fpr saved
-	 (6 bits).  */
-      fprintf (file, "%d,",
-	       (info->push_p << 7) | (64 - info->first_fp_reg_save));
-
-      /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits).  */
-      fprintf (file, "%d,", (32 - first_reg_to_save ()));
-
-      {
-	/* Compute the parameter info from the function decl argument
-	   list.  */
-	tree decl;
-	int next_parm_info_bit;
-
-	next_parm_info_bit = 31;
-	parm_info = 0;
-	fixed_parms = 0;
-	float_parms = 0;
-
-	for (decl = DECL_ARGUMENTS (current_function_decl);
-	     decl; decl = TREE_CHAIN (decl))
-	  {
-	    rtx parameter = DECL_INCOMING_RTL (decl);
-	    enum machine_mode mode = GET_MODE (parameter);
-
-	    if (GET_CODE (parameter) == REG)
-	      {
-		if (GET_MODE_CLASS (mode) == MODE_FLOAT)
-		  {
-		    int bits;
-
-		    float_parms++;
-
-		    if (mode == SFmode)
-		      bits = 0x2;
-		    else if (mode == DFmode)
-		      bits = 0x3;
-		    else
-		      abort ();
-
-		    /* If only one bit will fit, don't or in this entry.  */
-		    if (next_parm_info_bit > 0)
-		      parm_info |= (bits << (next_parm_info_bit - 1));
-		    next_parm_info_bit -= 2;
-		  }
-		else
-		  {
-		    fixed_parms += ((GET_MODE_SIZE (mode)
-				     + (UNITS_PER_WORD - 1))
-				    / UNITS_PER_WORD);
-		    next_parm_info_bit -= 1;
-		  }
-	      }
-	  }
-      }
-
-      /* Number of fixed point parameters.  */
-      /* This is actually the number of words of fixed point parameters; thus
-	 an 8 byte struct counts as 2; and thus the maximum value is 8.  */
-      fprintf (file, "%d,", fixed_parms);
-
-      /* 2 bitfields: number of floating point parameters (7 bits), parameters
-	 all on stack.  */
-      /* This is actually the number of fp registers that hold parameters;
-	 and thus the maximum value is 13.  */
-      /* Set parameters on stack bit if parameters are not in their original
-	 registers, regardless of whether they are on the stack?  Xlc
-	 seems to set the bit when not optimizing.  */
-      fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
-
-      /* Optional fields follow.  Some are variable length.  */
-
-      /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
-	 11 double float.  */
-      /* There is an entry for each parameter in a register, in the order that
-	 they occur in the parameter list.  Any intervening arguments on the
-	 stack are ignored.  If the list overflows a long (max possible length
-	 34 bits) then completely leave off all elements that don't fit.  */
-      /* Only emit this long if there was at least one parameter.  */
-      if (fixed_parms || float_parms)
-	fprintf (file, "\t.long %d\n", parm_info);
-
-      /* Offset from start of code to tb table.  */
-      fputs ("\t.long ", file);
-      ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
-      RS6000_OUTPUT_BASENAME (file, fname);
-      fputs ("-.", file);
-      RS6000_OUTPUT_BASENAME (file, fname);
-      putc ('\n', file);
-
-      /* Interrupt handler mask.  */
-      /* Omit this long, since we never set the interrupt handler bit
-	 above.  */
-
-      /* Number of CTL (controlled storage) anchors.  */
-      /* Omit this long, since the has_ctl bit is never set above.  */
-
-      /* Displacement into stack of each CTL anchor.  */
-      /* Omit this list of longs, because there are no CTL anchors.  */
-
-      /* Length of function name.  */
-      fprintf (file, "\t.short %d\n", (int) strlen (fname));
-
-      /* Function name.  */
-      assemble_string (fname, strlen (fname));
-
-      /* Register for alloca automatic storage; this is always reg 31.
-	 Only emit this if the alloca bit was set above.  */
-      if (frame_pointer_needed)
-	fputs ("\t.byte 31\n", file);
-    }
-
-  if (!rtx_flag && DEFAULT_ABI == ABI_NT)
-    {
-      RS6000_OUTPUT_BASENAME
-	(file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
-      fputs (".e:\nFE_MOT_RESVD..", file);
-      RS6000_OUTPUT_BASENAME
-	(file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
-      fputs (":\n", file);
-    }
-}
-
-
-
-
-/* Write function prologue.  */
-void
-output_prolog (file, size)
-     FILE *file;
-     int size;
-{
-  rs6000_prolog (file, FALSE, rs6000_stack_info ());
-}
-
-/* Write function epilogue.  */
-
-void
-output_epilog (file, size)
-     FILE *file;
-     int size;
-{
-  rs6000_epilog (file, FALSE, rs6000_stack_info ());
-}
-
-/* END CYGNUS LOCAL */
-
-
-/* A C compound statement that outputs the assembler code for a thunk function,
-   used to implement C++ virtual function calls with multiple inheritance.  The
-   thunk acts as a wrapper around a virtual function, adjusting the implicit
-   object parameter before handing control off to the real function.
-
-   First, emit code to add the integer DELTA to the location that contains the
-   incoming first argument.  Assume that this argument contains a pointer, and
-   is the one used to pass the `this' pointer in C++.  This is the incoming
-   argument *before* the function prologue, e.g. `%o0' on a sparc.  The
-   addition must preserve the values of all other incoming arguments.
-
-   After the addition, emit code to jump to FUNCTION, which is a
-   `FUNCTION_DECL'.  This is a direct pure jump, not a call, and does not touch
-   the return address.  Hence returning from FUNCTION will return to whoever
-   called the current `thunk'.
-
-   The effect must be as if FUNCTION had been called directly with the adjusted
-   first argument.  This macro is responsible for emitting all of the code for
-   a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not
-   invoked.
-
-   The THUNK_FNDECL is redundant.  (DELTA and FUNCTION have already been
-   extracted from it.)  It might possibly be useful on some targets, but
-   probably not.
-
-   If you do not define this macro, the target-independent code in the C++
-   frontend will generate a less efficient heavyweight thunk that calls
-   FUNCTION instead of jumping to it.  The generic approach does not support
-   varargs.  */
-
-void
-output_mi_thunk (file, thunk_fndecl, delta, function)
-     FILE *file;
-     tree thunk_fndecl;
-     int delta;
-     tree function;
-{
-  char *this_reg = reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ];
-  char *r0	 = reg_names[0];
-  char *sp	 = reg_names[1];
-  char *toc	 = reg_names[2];
-  char *schain	 = reg_names[11];
-  char *r12	 = reg_names[12];
-  char *prefix;
-  char *fname;
-  char buf[512];
-  static int labelno = 0;
-
-  /* Small constants that can be done by one add instruction */
-  if (delta >= -32768 && delta <= 32767)
-    {
-      if (!TARGET_NEW_MNEMONICS)
-	fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg);
-      else
-	fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta);
-    }
-
-  /* Large constants that can be done by one addis instruction */
-  else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1)
-    asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg,
-		 delta >> 16);
-
-  /* 32-bit constants that can be done by an add and addis instruction.  */
-  else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1)
-    {
-      /* Break into two pieces, propigating the sign bit from the low word to
-	 the upper word.  */
-      int delta_high = delta >> 16;
-      int delta_low  = delta & 0xffff;
-      if ((delta_low & 0x8000) != 0)
-	{
-	  delta_high++;
-	  delta_low = (delta_low ^ 0x8000) - 0x8000;	/* sign extend */
-	}
-
-      asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg,
-		   delta_high);
-
-      if (!TARGET_NEW_MNEMONICS)
-	fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg);
-      else
-	fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low);
-    }
-
-  /* 64-bit constants, fixme */
-  else
-    abort ();
-
-  /* Get the prefix in front of the names.  */
-  switch (DEFAULT_ABI)
-    {
-    default:
-      abort ();
-
-    case ABI_AIX:
-      prefix = ".";
-      break;
-
-    case ABI_V4:
-    case ABI_AIX_NODESC:
-    case ABI_SOLARIS:
-      prefix = "";
-      break;
-
-    case ABI_NT:
-      prefix = "..";
-      break;
-    }
-
-  /* If the function is compiled in this module, jump to it directly.
-     Otherwise, load up its address and jump to it.  */
-
-  fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
-#if 1
-  /* For now, just emit a branch always, until we can figure out better when we
-     need to load the address into the count register and emit the slower bctr
-     instruction.  */
-  fprintf (file, "\tb %s", prefix);
-  assemble_name (file, fname);
-  fprintf (file, "\n");
-
-#else
-  if (current_file_function_operand (XEXP (DECL_RTL (function), 0))
-      && !lookup_attribute ("longcall", TYPE_ATTRIBUTES (TREE_TYPE (function))))
-    {
-      fprintf (file, "\tb %s", prefix);
-      assemble_name (file, fname);
-      fprintf (file, "\n");
-    }
-
-  else
-    {
-      switch (DEFAULT_ABI)
-	{
-	default:
-	case ABI_NT:
-	  abort ();
-
-	case ABI_AIX:
-	  /* Set up a TOC entry for the function.  */
-	  ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno);
-	  toc_section ();
-	  ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno);
-	  labelno++;
-
-	  /* Note, MINIMAL_TOC doesn't make sense in the case of a thunk, since
-	     there will be only one TOC entry for this function.  */
-	  fputs ("\t.tc\t", file);
-	  assemble_name (file, buf);
-	  fputs ("[TC],", file);
-	  assemble_name (file, buf);
-	  putc ('\n', file);
-	  text_section ();
-	  asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s", r12);
-	  assemble_name (file, buf);
-	  asm_fprintf (file, "(%s)\n", reg_names[2]);
-	  asm_fprintf (file,
-		       (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n",
-		       r0, r12);
-
-	  asm_fprintf (file,
-		       (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n",
-		       toc, r12);
-
-	  asm_fprintf (file, "\tmtctr %s\n", r0);
-	  asm_fprintf (file,
-		       (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n",
-		       schain, r12);
-
-	  asm_fprintf (file, "\tbctr\n");
-	  break;
-
-	  /* Don't use r11, that contains the static chain, just use r0/r12.  */
-	case ABI_V4:
-	case ABI_AIX_NODESC:
-	case ABI_SOLARIS:
-	  if (flag_pic == 1)
-	    {
-	      fprintf (file, "\tmflr %s\n", r0);
-	      fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
-	      asm_fprintf (file, "\tmflr %s\n", r12);
-	      asm_fprintf (file, "\tmtlr %s\n", r0);
-	      asm_fprintf (file, "\t{l|lwz} %s,", r0);
-	      assemble_name (file, fname);
-	      asm_fprintf (file, "@got(%s)\n", r12);
-	      asm_fprintf (file, "\tmtctr %s\n", r0);
-	      asm_fprintf (file, "\tbctr\n");
-	    }
-#if TARGET_ELF
-	  else if (flag_pic > 1 || TARGET_RELOCATABLE)
-	    {
-	      ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno);
-	      labelno++;
-	      fprintf (file, "\tmflr %s\n", r0);
-	      asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", r0, sp);
-	      rs6000_pic_func_labelno = rs6000_pic_labelno;
-	      rs6000_output_load_toc_table (file, 12
-/* CYGNUS LOCAL -- vmakarov/prolog-epilog instruction scheduling */
-					, FALSE
-/* END CYGNUS LOCAL */
-					);
-	      asm_fprintf (file, "\t{l|lwz} %s,", r0);
-	      assemble_name (file, buf);
-	      asm_fprintf (file, "(%s)\n", r12);
-	      asm_fprintf (file, "\t{l|lwz} %s,4(%s)\n", r12, sp);
-	      asm_fprintf (file, "\tmtlr %s\n", r12);
-	      asm_fprintf (file, "\tmtctr %s\n", r0);
-	      asm_fprintf (file, "\tbctr\n");
-	      asm_fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
-	      assemble_name (file, buf);
-	      fputs (" = .-.LCTOC1\n", file);
-	      fputs ("\t.long ", file);
-	      assemble_name (file, fname);
-	      fputs ("\n\t.previous\n", file);
-	    }
-#endif	/* TARGET_ELF */
-
-	  else
-	    {
-	      asm_fprintf (file, "\t{liu|lis} %s,", r12);
-	      assemble_name (file, fname);
-	      asm_fprintf (file, "@ha\n");
-	      asm_fprintf (file, "\t{cal|la} %s,", r12);
-	      assemble_name (file, fname);
-	      asm_fprintf (file, "@l(%s)\n", r12);
-	      asm_fprintf (file, "\tmtctr %s\n", r12);
-	      asm_fprintf (file, "\tbctr\n");
-	    }
-
-	  break;
-	}
-    }
-#endif	/* #if 0 out code to use bctr for far away jumps */
-}
-
-
-/* Output a TOC entry.  We derive the entry name from what is
-   being written.  */
-
-void
-output_toc (file, x, labelno)
-     FILE *file;
-     rtx x;
-     int labelno;
-{
-  char buf[256];
-  char *name = buf;
-  char *real_name;
-  rtx base = x;
-  int offset = 0;
-
-  if (TARGET_NO_TOC)
-    abort ();
-
-  /* if we're going to put a double constant in the TOC, make sure it's
-     aligned properly when strict alignment is on. */
-  if (GET_CODE (x) == CONST_DOUBLE
-      && STRICT_ALIGNMENT
-      && GET_MODE (x) == DFmode
-      && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
-    ASM_OUTPUT_ALIGN (file, 3);
-  }
-
-
-  if (TARGET_ELF && TARGET_MINIMAL_TOC)
-    {
-      ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
-      fprintf (file, "%d = .-", labelno);
-      ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC");
-      fputs ("1\n", file);
-    }
-  else
-    ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
-
-  /* Handle FP constants specially.  Note that if we have a minimal
-     TOC, things we put here aren't actually in the TOC, so we can allow
-     FP constants.  */
-  if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode
-      && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
-    {
-      REAL_VALUE_TYPE rv;
-      long k[2];
-
-      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-      REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
-      if (TARGET_64BIT)
-	{
-	  if (TARGET_MINIMAL_TOC)
-	    fprintf (file, "\t.llong 0x%lx%08lx\n", k[0], k[1]);
-	  else
-	    fprintf (file, "\t.tc FD_%lx_%lx[TC],0x%lx%08lx\n",
-		     k[0], k[1], k[0] & 0xffffffff, k[1] & 0xffffffff);
-	  return;
-	}
-      else
-	{
-	  if (TARGET_MINIMAL_TOC)
-	    fprintf (file, "\t.long %ld\n\t.long %ld\n", k[0], k[1]);
-	  else
-	    fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n",
-		     k[0], k[1], k[0], k[1]);
-	  return;
-	}
-    }
-  else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode
-	   && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
-    {
-      REAL_VALUE_TYPE rv;
-      long l;
-
-      REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-      REAL_VALUE_TO_TARGET_SINGLE (rv, l);
-
-      if (TARGET_MINIMAL_TOC)
-	fprintf (file, TARGET_32BIT ? "\t.long %ld\n" : "\t.llong %ld\n", l);
-      else
-	fprintf (file, "\t.tc FS_%lx[TC],%ld\n", l, l);
-      return;
-    }
-  else if (GET_MODE (x) == DImode
-	   && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
-	   && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
-    {
-      HOST_WIDE_INT low;
-      HOST_WIDE_INT high;
-
-      if (GET_CODE (x) == CONST_DOUBLE)
-	{
-	  low = CONST_DOUBLE_LOW (x);
-	  high = CONST_DOUBLE_HIGH (x);
-	}
-      else
-#if HOST_BITS_PER_WIDE_INT == 32
-	{
-	  low = INTVAL (x);
-	  high = (low < 0) ? ~0 : 0;
-	}
-#else
-	{
-          low = INTVAL (x) & 0xffffffff;
-          high = (HOST_WIDE_INT) INTVAL (x) >> 32;
-	}
-#endif
-
-      if (TARGET_64BIT)
-	{
-	  if (TARGET_MINIMAL_TOC)
-	    fprintf (file, "\t.llong 0x%lx%08lx\n", (long)high, (long)low);
-	  else
-	    fprintf (file, "\t.tc ID_%lx_%lx[TC],0x%lx%08lx\n",
-		     (long)high, (long)low, (long)high, (long)low);
-	  return;
-	}
-      else
-	{
-	  if (TARGET_MINIMAL_TOC)
-	    fprintf (file, "\t.long %ld\n\t.long %ld\n",
-		     (long)high, (long)low);
-	  else
-	    fprintf (file, "\t.tc ID_%lx_%lx[TC],%ld,%ld\n",
-		     (long)high, (long)low, (long)high, (long)low);
-	  return;
-	}
-    }
-
-  if (GET_CODE (x) == CONST)
-    {
-      base = XEXP (XEXP (x, 0), 0);
-      offset = INTVAL (XEXP (XEXP (x, 0), 1));
-    }
-  
-  if (GET_CODE (base) == SYMBOL_REF)
-    name = XSTR (base, 0);
-  else if (GET_CODE (base) == LABEL_REF)
-    ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
-  else if (GET_CODE (base) == CODE_LABEL)
-    ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
-  else
-    abort ();
-
-  STRIP_NAME_ENCODING (real_name, name);
-  if (TARGET_MINIMAL_TOC)
-    fputs (TARGET_32BIT ? "\t.long " : "\t.llong ", file);
-  else
-    {
-      fprintf (file, "\t.tc %s", real_name);
-
-      if (offset < 0)
-	fprintf (file, ".N%d", - offset);
-      else if (offset)
-	fprintf (file, ".P%d", offset);
-
-      fputs ("[TC],", file);
-    }
-
-  /* Currently C++ toc references to vtables can be emitted before it
-     is decided whether the vtable is public or private.  If this is
-     the case, then the linker will eventually complain that there is
-     a TOC reference to an unknown section.  Thus, for vtables only,
-     we emit the TOC reference to reference the symbol and not the
-     section.  */
-  if (!strncmp ("_vt.", name, 4))
-    {
-      RS6000_OUTPUT_BASENAME (file, name);
-      if (offset < 0)
-	fprintf (file, "%d", offset);
-      else if (offset > 0)
-	fprintf (file, "+%d", offset);
-    }
-  else
-    output_addr_const (file, x);
-  putc ('\n', file);
-}
-
-/* Output an assembler pseudo-op to write an ASCII string of N characters
-   starting at P to FILE.
-
-   On the RS/6000, we have to do this using the .byte operation and
-   write out special characters outside the quoted string.
-   Also, the assembler is broken; very long strings are truncated,
-   so we must artificially break them up early. */
-
-void
-output_ascii (file, p, n)
-     FILE *file;
-     char *p;
-     int n;
-{
-  char c;
-  int i, count_string;
-  char *for_string = "\t.byte \"";
-  char *for_decimal = "\t.byte ";
-  char *to_close = NULL;
-
-  count_string = 0;
-  for (i = 0; i < n; i++)
-    {
-      c = *p++;
-      if (c >= ' ' && c < 0177)
-	{
-	  if (for_string)
-	    fputs (for_string, file);
-	  putc (c, file);
-
-	  /* Write two quotes to get one.  */
-	  if (c == '"')
-	    {
-	      putc (c, file);
-	      ++count_string;
-	    }
-
-	  for_string = NULL;
-	  for_decimal = "\"\n\t.byte ";
-	  to_close = "\"\n";
-	  ++count_string;
-
-	  if (count_string >= 512)
-	    {
-	      fputs (to_close, file);
-
-	      for_string = "\t.byte \"";
-	      for_decimal = "\t.byte ";
-	      to_close = NULL;
-	      count_string = 0;
-	    }
-	}
-      else
-	{
-	  if (for_decimal)
-	    fputs (for_decimal, file);
-	  fprintf (file, "%d", c);
-
-	  for_string = "\n\t.byte \"";
-	  for_decimal = ", ";
-	  to_close = "\n";
-	  count_string = 0;
-	}
-    }
-
-  /* Now close the string if we have written one.  Then end the line.  */
-  if (to_close)
-    fprintf (file, to_close);
-}
-
-/* Generate a unique section name for FILENAME for a section type
-   represented by SECTION_DESC.  Output goes into BUF.
-
-   SECTION_DESC can be any string, as long as it is different for each
-   possible section type.
-
-   We name the section in the same manner as xlc.  The name begins with an
-   underscore followed by the filename (after stripping any leading directory
-   names) with the last period replaced by the string SECTION_DESC.  If
-   FILENAME does not contain a period, SECTION_DESC is appended to the end of
-   the name.  */
-
-void
-rs6000_gen_section_name (buf, filename, section_desc)
-     char **buf;
-     char *filename;
-     char *section_desc;
-{
-  char *q, *after_last_slash, *last_period;
-  char *p;
-  int len;
-
-  after_last_slash = filename;
-  for (q = filename; *q; q++)
-    {
-      if (*q == '/')
-	after_last_slash = q + 1;
-      else if (*q == '.')
-	last_period = q;
-    }
-
-  len = strlen (after_last_slash) + strlen (section_desc) + 2;
-  *buf = (char *) permalloc (len);
-
-  p = *buf;
-  *p++ = '_';
-
-  for (q = after_last_slash; *q; q++)
-    {
-      if (q == last_period)
-        {
-	  strcpy (p, section_desc);
-	  p += strlen (section_desc);
-        }
-
-      else if (ISALNUM (*q))
-        *p++ = *q;
-    }
-
-  if (last_period == 0)
-    strcpy (p, section_desc);
-  else
-    *p = '\0';
-}
-
-/* Write function profiler code. */
-
-void
-output_function_profiler (file, labelno)
-  FILE *file;
-  int labelno;
-{
-  /* The last used parameter register.  */
-  int last_parm_reg;
-  int i, j;
-  char buf[100];
-
-  ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
-  switch (DEFAULT_ABI)
-    {
-    default:
-      abort ();
-
-    case ABI_V4:
-    case ABI_SOLARIS:
-    case ABI_AIX_NODESC:
-      fprintf (file, "\tmflr %s\n", reg_names[0]);
-      if (flag_pic == 1)
-	{
-	  fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
-	  asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
-		       reg_names[0], reg_names[1]);
-	  asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
-	  asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
-	  assemble_name (file, buf);
-	  asm_fprintf (file, "@got(%s)\n", reg_names[12]);
-	}
-#if TARGET_ELF
-      else if (flag_pic > 1 || TARGET_RELOCATABLE)
-	{
-	  asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
-		       reg_names[0], reg_names[1]);
-	  rs6000_pic_func_labelno = rs6000_pic_labelno;
-	  rs6000_output_load_toc_table (file, 12
-/* CYGNUS LOCAL -- vmakarov/prolog-epilog instruction scheduling */
-					, FALSE
-/* END CYGNUS LOCAL */
-					);
-	  asm_fprintf (file, "\t{l|lwz} %s,", reg_names[12]);
-	  assemble_name (file, buf);
-	  asm_fprintf (file, "X(%s)\n", reg_names[12]);
-	  asm_fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
-	  assemble_name (file, buf);
-	  fputs ("X = .-.LCTOC1\n", file);
-	  fputs ("\t.long ", file);
-	  assemble_name (file, buf);
-	  fputs ("\n\t.previous\n", file);
-	}
-#endif
-      else
-	{
-	  asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
-	  assemble_name (file, buf);
-	  fputs ("@ha\n", file);
-	  asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", reg_names[0], reg_names[1]);
-	  asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
-	  assemble_name (file, buf);
-	  asm_fprintf (file, "@l(%s)\n", reg_names[12]);
-	}
-
-      fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
-      break;
-
-    case ABI_AIX:
-      /* Set up a TOC entry for the profiler label.  */
-      toc_section ();
-      ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno);
-      if (TARGET_MINIMAL_TOC)
-	{
-	  fputs (TARGET_32BIT ? "\t.long " : "\t.llong ", file);
-	  assemble_name (file, buf);
-	  putc ('\n', file);
-	}
-      else
-	{
-	  fputs ("\t.tc\t", file);
-	  assemble_name (file, buf);
-	  fputs ("[TC],", file);
-	  assemble_name (file, buf);
-	  putc ('\n', file);
-	}
-      text_section ();
-
-  /* Figure out last used parameter register.  The proper thing to do is
-     to walk incoming args of the function.  A function might have live
-     parameter registers even if it has no incoming args.  */
-
-      for (last_parm_reg = 10;
-	   last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
-	   last_parm_reg--)
-	;
-
-  /* Save parameter registers in regs 23-30.  Don't overwrite reg 31, since
-     it might be set up as the frame pointer.  */
-
-      for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
-	asm_fprintf (file, "\tmr %d,%d\n", j, i);
-
-  /* Load location address into r3, and call mcount.  */
-
-      ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno);
-      asm_fprintf (file, TARGET_32BIT ? "\t{l|lwz} %s," : "\tld %s,",
-		   reg_names[3]);
-      assemble_name (file, buf);
-      asm_fprintf (file, "(%s)\n\tbl %s\n\t%s\n",
-		   reg_names[2], RS6000_MCOUNT, RS6000_CALL_GLUE);
-
-  /* Restore parameter registers.  */
-
-      for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
-	asm_fprintf (file, "\tmr %d,%d\n", i, j);
-      break;
-    }
-}
-
-/* Adjust the cost of a scheduling dependency.  Return the new cost of
-   a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
-
-int
-rs6000_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn ATTRIBUTE_UNUSED;
-     int cost;
-{
-  if (! recog_memoized (insn))
-    return 0;
-
-  if (REG_NOTE_KIND (link) != 0)
-    return 0;
-
-  if (REG_NOTE_KIND (link) == 0)
-    {
-      /* Data dependency; DEP_INSN writes a register that INSN reads some
-	 cycles later.  */
-
-      /* Tell the first scheduling pass about the latency between a mtctr
-	 and bctr (and mtlr and br/blr).  The first scheduling pass will not
-	 know about this latency since the mtctr instruction, which has the
-	 latency associated to it, will be generated by reload.  */
-      if (get_attr_type (insn) == TYPE_JMPREG)
-	return TARGET_POWER ? 5 : 4;
-
-      /* Fall out to return default cost.  */
-    }
-
-  return cost;
-}
-
-/* A C statement (sans semicolon) to update the integer scheduling priority
-   INSN_PRIORITY (INSN).  Reduce the priority to execute the INSN earlier,
-   increase the priority to execute INSN later.  Do not define this macro if
-   you do not need to adjust the scheduling priorities of insns.  */
-
-int
-rs6000_adjust_priority (insn, priority)
-     rtx insn;
-     int priority;
-{
-  /* On machines (like the 750) which have asymetric integer units, where one
-     integer unit can do multiply and divides and the other can't, reduce the
-     priority of multiply/divide so it is scheduled before other integer
-     operationss.  */
-
-#if 0
-  if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
-    return priority;
-
-  if (GET_CODE (PATTERN (insn)) == USE)
-    return priority;
-
-  switch (rs6000_cpu_attr) {
-  case CPU_PPC750:
-    switch (get_attr_type (insn))
-      {
-      default:
-	break;
-
-      case TYPE_IMUL:
-      case TYPE_IDIV:
-	fprintf (stderr, "priority was %#x (%d) before adjustment\n", priority, priority);
-	if (priority >= 0 && priority < 0x01000000)
-	  priority >>= 3;
-	break;
-      }
-  }
-#endif
-
-  return priority;
-}
-
-/* Return how many instructions the machine can issue per cycle */
-int get_issue_rate()
-{
-  switch (rs6000_cpu_attr) {
-  case CPU_RIOS1:
-    return 3;       /* ? */
-  case CPU_RIOS2:
-    return 4;
-  case CPU_PPC601:
-    return 3;       /* ? */
-  case CPU_PPC603:
-    return 2; 
-  case CPU_PPC750:
-    return 2; 
-  case CPU_PPC604:
-    return 4;
-  case CPU_PPC620:
-    return 4;
-  default:
-    return 1;
-  }
-}
-
-
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.
-
-   The trampoline should set the static chain pointer to value placed
-   into the trampoline and should branch to the specified routine.  */
-
-void
-rs6000_trampoline_template (file)
-     FILE *file;
-{
-  char *sc = reg_names[STATIC_CHAIN_REGNUM];
-  char *r0 = reg_names[0];
-  char *r2 = reg_names[2];
-
-  switch (DEFAULT_ABI)
-    {
-    default:
-      abort ();
-
-    /* Under AIX, this is not code at all, but merely a data area,
-       since that is the way all functions are called.  The first word is
-       the address of the function, the second word is the TOC pointer (r2),
-       and the third word is the static chain value.  */
-    case ABI_AIX:
-      break;
-
-
-    /* V.4/eabi function pointers are just a single pointer, so we need to
-       do the full gory code to load up the static chain.  */
-    case ABI_V4:
-    case ABI_SOLARIS:
-    case ABI_AIX_NODESC:
-      break;
-
-  /* NT function pointers point to a two word area (real address, TOC)
-     which unfortunately does not include a static chain field.  So we
-     use the function field to point to ..LTRAMP1 and the toc field
-     to point to the whole table.  */
-    case ABI_NT:
-      if (STATIC_CHAIN_REGNUM == 0
-	  || STATIC_CHAIN_REGNUM == 2
-	  || TARGET_64BIT
-	  || !TARGET_NEW_MNEMONICS)
-	abort ();
-
-      fprintf (file, "\t.ualong 0\n");			/* offset  0 */
-      fprintf (file, "\t.ualong 0\n");			/* offset  4 */
-      fprintf (file, "\t.ualong 0\n");			/* offset  8 */
-      fprintf (file, "\t.ualong 0\n");			/* offset 12 */
-      fprintf (file, "\t.ualong 0\n");			/* offset 16 */
-      fprintf (file, "..LTRAMP1..0:\n");		/* offset 20 */
-      fprintf (file, "\tlwz %s,8(%s)\n", r0, r2);	/* offset 24 */
-      fprintf (file, "\tlwz %s,12(%s)\n", sc, r2);	/* offset 28 */
-      fprintf (file, "\tmtctr %s\n", r0);		/* offset 32 */
-      fprintf (file, "\tlwz %s,16(%s)\n", r2, r2);	/* offset 36 */
-      fprintf (file, "\tbctr\n");			/* offset 40 */
-      break;
-    }
-
-  return;
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-int
-rs6000_trampoline_size ()
-{
-  int ret = 0;
-
-  switch (DEFAULT_ABI)
-    {
-    default:
-      abort ();
-
-    case ABI_AIX:
-      ret = (TARGET_32BIT) ? 12 : 24;
-      break;
-
-    case ABI_V4:
-    case ABI_SOLARIS:
-    case ABI_AIX_NODESC:
-      ret = (TARGET_32BIT) ? 40 : 48;
-      break;
-
-    case ABI_NT:
-      ret = 20;
-      break;
-    }
-
-  return ret;
-}
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-void
-rs6000_initialize_trampoline (addr, fnaddr, cxt)
-     rtx addr;
-     rtx fnaddr;
-     rtx cxt;
-{
-  enum machine_mode pmode = Pmode;
-  int regsize = (TARGET_32BIT) ? 4 : 8;
-  rtx ctx_reg = force_reg (pmode, cxt);
-
-  switch (DEFAULT_ABI)
-    {
-    default:
-      abort ();
-
-/* Macros to shorten the code expansions below.  */
-#define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
-#define MEM_PLUS(addr,offset) gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
-
-    /* Under AIX, just build the 3 word function descriptor */
-    case ABI_AIX:
-      {
-	rtx fn_reg = gen_reg_rtx (pmode);
-	rtx toc_reg = gen_reg_rtx (pmode);
-	emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
-	emit_move_insn (toc_reg, MEM_PLUS (fnaddr, 4));
-	emit_move_insn (MEM_DEREF (addr), fn_reg);
-	emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
-	emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
-      }
-      break;
-
-    /* Under V.4/eabi, call __trampoline_setup to do the real work.  */
-    case ABI_V4:
-    case ABI_SOLARIS:
-    case ABI_AIX_NODESC:
-      emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
-			 FALSE, VOIDmode, 4,
-			 addr, pmode,
-			 GEN_INT (rs6000_trampoline_size ()), SImode,
-			 fnaddr, pmode,
-			 ctx_reg, pmode);
-      break;
-
-    /* Under NT, update the first word to point to the ..LTRAMP1..0 header,
-       the second word will point to the whole trampoline, third-fifth words
-       will then have the real address, static chain, and toc value.  */
-    case ABI_NT:
-      {
-	rtx tramp_reg = gen_reg_rtx (pmode);
-	rtx fn_reg = gen_reg_rtx (pmode);
-	rtx toc_reg = gen_reg_rtx (pmode);
-
-	emit_move_insn (tramp_reg, gen_rtx_SYMBOL_REF (pmode, "..LTRAMP1..0"));
-	addr = force_reg (pmode, addr);
-	emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
-	emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
-	emit_move_insn (MEM_DEREF (addr), tramp_reg);
-	emit_move_insn (MEM_PLUS (addr, regsize), addr);
-	emit_move_insn (MEM_PLUS (addr, 2*regsize), fn_reg);
-	emit_move_insn (MEM_PLUS (addr, 3*regsize), ctx_reg);
-	emit_move_insn (MEM_PLUS (addr, 4*regsize), gen_rtx_REG (pmode, 2));
-      }
-      break;
-    }
-
-  return;
-}
-
-
-/* If defined, a C expression whose value is nonzero if IDENTIFIER
-   with arguments ARGS is a valid machine specific attribute for DECL.
-   The attributes in ATTRIBUTES have previously been assigned to DECL.  */
-
-int
-rs6000_valid_decl_attribute_p (decl, attributes, identifier, args)
-     tree decl ATTRIBUTE_UNUSED;
-     tree attributes ATTRIBUTE_UNUSED;
-     tree identifier ATTRIBUTE_UNUSED;
-     tree args ATTRIBUTE_UNUSED;
-{
-  return 0;
-}
-
-/* If defined, a C expression whose value is nonzero if IDENTIFIER
-   with arguments ARGS is a valid machine specific attribute for TYPE.
-   The attributes in ATTRIBUTES have previously been assigned to TYPE.  */
-
-int
-rs6000_valid_type_attribute_p (type, attributes, identifier, args)
-     tree type;
-     tree attributes ATTRIBUTE_UNUSED;
-     tree identifier;
-     tree args;
-{
-  if (TREE_CODE (type) != FUNCTION_TYPE
-      && TREE_CODE (type) != FIELD_DECL
-      && TREE_CODE (type) != TYPE_DECL)
-    return 0;
-
-  /* Longcall attribute says that the function is not within 2**26 bytes
-     of the current function, and to do an indirect call.  */
-  if (is_attribute_p ("longcall", identifier))
-    return (args == NULL_TREE);
-
-  if (DEFAULT_ABI == ABI_NT)
-    {
-      /* Stdcall attribute says callee is responsible for popping arguments
-	 if they are not variable.  */
-      if (is_attribute_p ("stdcall", identifier))
-	return (args == NULL_TREE);
-
-      /* Cdecl attribute says the callee is a normal C declaration */
-      if (is_attribute_p ("cdecl", identifier))
-	return (args == NULL_TREE);
-
-      /* Dllimport attribute says the caller is to call the function
-	 indirectly through a __imp_<name> pointer.  */
-      if (is_attribute_p ("dllimport", identifier))
-	return (args == NULL_TREE);
-
-      /* Dllexport attribute says the callee is to create a __imp_<name>
-	 pointer.  */
-      if (is_attribute_p ("dllexport", identifier))
-	return (args == NULL_TREE);
-
-      /* Exception attribute allows the user to specify 1-2 strings or identifiers
-	 that will fill in the 3rd and 4th fields of the structured exception
-	 table.  */
-      if (is_attribute_p ("exception", identifier))
-	{
-	  int i;
-
-	  if (args == NULL_TREE)
-	    return 0;
-
-	  for (i = 0; i < 2 && args != NULL_TREE; i++)
-	    {
-	      tree this_arg = TREE_VALUE (args);
-	      args = TREE_PURPOSE (args);
-
-	      if (TREE_CODE (this_arg) != STRING_CST
-		  && TREE_CODE (this_arg) != IDENTIFIER_NODE)
-		return 0;
-	    }
-
-	  return (args == NULL_TREE);
-	}
-    }
-
-  return 0;
-}
-
-/* If defined, a C expression whose value is zero if the attributes on
-   TYPE1 and TYPE2 are incompatible, one if they are compatible, and
-   two if they are nearly compatible (which causes a warning to be
-   generated).  */
-
-int
-rs6000_comp_type_attributes (type1, type2)
-     tree type1 ATTRIBUTE_UNUSED;
-     tree type2 ATTRIBUTE_UNUSED;
-{
-  return 1;
-}
-
-/* If defined, a C statement that assigns default attributes to newly
-   defined TYPE.  */
-
-void
-rs6000_set_default_type_attributes (type)
-     tree type ATTRIBUTE_UNUSED;
-{
-}
-
-/* Return a dll import reference corresponding to a call's SYMBOL_REF */
-struct rtx_def *
-rs6000_dll_import_ref (call_ref)
-     rtx call_ref;
-{
-  char *call_name;
-  int len;
-  char *p;
-  rtx reg1, reg2;
-  tree node;
-
-  if (GET_CODE (call_ref) != SYMBOL_REF)
-    abort ();
-
-  call_name = XSTR (call_ref, 0);
-  len = sizeof ("__imp_") + strlen (call_name);
-  p = alloca (len);
-  reg2 = gen_reg_rtx (Pmode);
-
-  strcpy (p, "__imp_");
-  strcat (p, call_name);
-  node = get_identifier (p);
-
-  reg1 = force_reg (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)));
-  emit_move_insn (reg2, gen_rtx_MEM (Pmode, reg1));
-
-  return reg2;
-}
-
-/* Return a reference suitable for calling a function with the longcall attribute.  */
-struct rtx_def *
-rs6000_longcall_ref (call_ref)
-     rtx call_ref;
-{
-  char *call_name;
-  tree node;
-
-  if (GET_CODE (call_ref) != SYMBOL_REF)
-    return call_ref;
-
-  /* System V adds '.' to the internal name, so skip them.  */
-  call_name = XSTR (call_ref, 0);
-  if (*call_name == '.')
-    {
-      while (*call_name == '.')
-	call_name++;
-
-      node = get_identifier (call_name);
-      call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
-    }
-
-  return force_reg (Pmode, call_ref);
-}
-
-
-/* A C statement or statements to switch to the appropriate section
-   for output of RTX in mode MODE.  You can assume that RTX is some
-   kind of constant in RTL.  The argument MODE is redundant except in
-   the case of a `const_int' rtx.  Select the section by calling
-   `text_section' or one of the alternatives for other sections.
-
-   Do not define this macro if you put all constants in the read-only
-   data section.  */
-
-#ifdef USING_SVR4_H
-
-void
-rs6000_select_rtx_section (mode, x)
-     enum machine_mode mode;
-     rtx x;
-{
-  if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x))
-    toc_section ();
-  else
-    const_section ();
-}
-
-/* A C statement or statements to switch to the appropriate
-   section for output of DECL.  DECL is either a `VAR_DECL' node
-   or a constant of some sort.  RELOC indicates whether forming
-   the initial value of DECL requires link-time relocations.  */
-
-void
-rs6000_select_section (decl, reloc)
-     tree decl;
-     int reloc;
-{
-  int size = int_size_in_bytes (TREE_TYPE (decl));
-
-  if (TREE_CODE (decl) == STRING_CST)
-    {
-      if (! flag_writable_strings)
-	const_section ();
-      else
-	data_section ();
-    }
-  else if (TREE_CODE (decl) == VAR_DECL)
-    {
-      if ((flag_pic && reloc)
-	  || !TREE_READONLY (decl)
-	  || TREE_SIDE_EFFECTS (decl)
-	  || !DECL_INITIAL (decl)
-	  || (DECL_INITIAL (decl) != error_mark_node
-	      && !TREE_CONSTANT (DECL_INITIAL (decl))))
-	{
-	  if (rs6000_sdata != SDATA_NONE && (size > 0) && (size <= g_switch_value))
-	    sdata_section ();
-	  else
-	    data_section ();
-	}
-      else
-	{
-	  if (rs6000_sdata != SDATA_NONE && (size > 0) && (size <= g_switch_value))
-	    {
-	      if (rs6000_sdata == SDATA_EABI)
-		sdata2_section ();
-	      else
-		sdata_section ();	/* System V doesn't have .sdata2/.sbss2 */
-	    }
-	  else
-	    const_section ();
-	}
-    }
-  else
-    const_section ();
-}
-
-
-
-/* If we are referencing a function that is static or is known to be
-   in this file, make the SYMBOL_REF special.  We can use this to indicate
-   that we can branch to this function without emitting a no-op after the
-   call.  For real AIX and NT calling sequences, we also replace the
-   function name with the real name (1 or 2 leading .'s), rather than
-   the function descriptor name.  This saves a lot of overriding code
-   to read the prefixes.  */
-
-void
-rs6000_encode_section_info (decl)
-     tree decl;
-{
-  if (TREE_CODE (decl) == FUNCTION_DECL)
-    {
-      rtx sym_ref = XEXP (DECL_RTL (decl), 0);
-      if (TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl))
-	SYMBOL_REF_FLAG (sym_ref) = 1;
-
-      if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
-	{
-	  char *prefix = (DEFAULT_ABI == ABI_AIX) ? "." : "..";
-	  char *str = permalloc (strlen (prefix) + 1
-				 + strlen (XSTR (sym_ref, 0)));
-	  strcpy (str, prefix);
-	  strcat (str, XSTR (sym_ref, 0));
-	  XSTR (sym_ref, 0) = str;
-	}
-    }
-  else if (rs6000_sdata != SDATA_NONE
-	   && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-	   && TREE_CODE (decl) == VAR_DECL)
-    {
-      int size = int_size_in_bytes (TREE_TYPE (decl));
-      tree section_name = DECL_SECTION_NAME (decl);
-      char *name = (char *)0;
-      int len = 0;
-
-      if (section_name)
-	{
-	  if (TREE_CODE (section_name) == STRING_CST)
-	    {
-	      name = TREE_STRING_POINTER (section_name);
-	      len = TREE_STRING_LENGTH (section_name);
-	    }
-	  else
-	    abort ();
-	}
-
-      if ((size > 0 && size <= g_switch_value)
-	  || (name
-	      && ((len == sizeof (".sdata")-1 && strcmp (name, ".sdata") == 0)
-		  || (len == sizeof (".sdata2")-1 && strcmp (name, ".sdata2") == 0)
-		  || (len == sizeof (".sbss")-1 && strcmp (name, ".sbss") == 0)
-		  || (len == sizeof (".sbss2")-1 && strcmp (name, ".sbss2") == 0)
-		  || (len == sizeof (".PPC.EMB.sdata0")-1 && strcmp (name, ".PPC.EMB.sdata0") == 0)
-		  || (len == sizeof (".PPC.EMB.sbss0")-1 && strcmp (name, ".PPC.EMB.sbss0") == 0))))
-	{
-	  rtx sym_ref = XEXP (DECL_RTL (decl), 0);
-	  char *str = permalloc (2 + strlen (XSTR (sym_ref, 0)));
-	  strcpy (str, "@");
-	  strcat (str, XSTR (sym_ref, 0));
-	  XSTR (sym_ref, 0) = str;
-	}
-    }
-}
-
-#endif /* USING_SVR4_H */
-
-void
-rs6000_fatal_bad_address (op)
-  rtx op;
-{
-  fatal_insn ("bad address", op);
-}
-
-/* CYGNUS LOCAL -- vmakarov/prolog-epilog instruction scheduling */
-
-
-void
-rs6000_expand_prologue (void)
-{
-  rs6000_stack_t *info;
-
-  /* Trick is here.  We need information about function but we have
-     started new insn sequence in `gen_prologue'. */
-  end_sequence ();
-  info = rs6000_stack_info ();
-  start_sequence ();
-  rs6000_prolog (NULL, TRUE, info);
-}
-
-void
-rs6000_expand_epilogue (void)
-{
-  rs6000_stack_t *info;
-
-  /* Trick is here.  We need information about function but we have
-     started new insn sequence in `gen_epilogue'. */
-  end_sequence ();
-  info = rs6000_stack_info ();
-  start_sequence ();
-  rs6000_epilog (NULL, TRUE, info);
-}
-
-/* END CYGNUS LOCAL */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
deleted file mode 100755
index 5890aaa..0000000
--- a/gcc/config/rs6000/rs6000.h
+++ /dev/null
@@ -1,3403 +0,0 @@
-/* Definitions of target machine for GNU compiler, for IBM RS/6000.
-   Copyright (C) 1992, 93-8, 1999 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Note that some other tm.h files include this one and then override
-   many of the definitions that relate to assembler syntax.  */
-
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-D_IBMR2 -D_POWER -D_AIX -D_AIX32 -D_LONG_LONG \
--Asystem(unix) -Asystem(aix) -Acpu(rs6000) -Amachine(rs6000)"
-
-/* Print subsidiary information on the compiler version in use.  */
-#define TARGET_VERSION ;
-
-/* Default string to use for cpu if not specified.  */
-#ifndef TARGET_CPU_DEFAULT
-#define TARGET_CPU_DEFAULT ((char *)0)
-#endif
-
-/* Tell the assembler to assume that all undefined names are external.
-
-   Don't do this until the fixed IBM assembler is more generally available.
-   When this becomes permanently defined, the ASM_OUTPUT_EXTERNAL,
-   ASM_OUTPUT_EXTERNAL_LIBCALL, and RS6000_OUTPUT_BASENAME macros will no
-   longer be needed.  Also, the extern declaration of mcount in ASM_FILE_START
-   will no longer be needed.  */
-
-/* #define ASM_SPEC "-u %(asm_cpu)" */
-
-/* Define appropriate architecture macros for preprocessor depending on
-   target switches.  */
-
-#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} %(cpp_cpu)"
-
-/* Common CPP definitions used by CPP_SPEC among the various targets
-   for handling -mcpu=xxx switches.  */
-#define CPP_CPU_SPEC \
-"%{!mcpu*: \
-  %{mpower: %{!mpower2: -D_ARCH_PWR}} \
-  %{mpower2: -D_ARCH_PWR2} \
-  %{mpowerpc*: -D_ARCH_PPC} \
-  %{mno-power: %{!mpowerpc*: -D_ARCH_COM}} \
-  %{!mno-power: %{!mpower2: %(cpp_default)}}} \
-%{mcpu=common: -D_ARCH_COM} \
-%{mcpu=power: -D_ARCH_PWR} \
-%{mcpu=power2: -D_ARCH_PWR2} \
-%{mcpu=powerpc: -D_ARCH_PPC} \
-%{mcpu=rios: -D_ARCH_PWR} \
-%{mcpu=rios1: -D_ARCH_PWR} \
-%{mcpu=rios2: -D_ARCH_PWR2} \
-%{mcpu=rsc: -D_ARCH_PWR} \
-%{mcpu=rsc1: -D_ARCH_PWR} \
-%{mcpu=401: -D_ARCH_PPC} \
-%{mcpu=403: -D_ARCH_PPC} \
-%{mcpu=505: -D_ARCH_PPC} \
-%{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
-%{mcpu=602: -D_ARCH_PPC} \
-%{mcpu=603: -D_ARCH_PPC} \
-%{mcpu=603e: -D_ARCH_PPC} \
-%{mcpu=ec603e: -D_ARCH_PPC} \
-%{mcpu=604: -D_ARCH_PPC} \
-%{mcpu=604e: -D_ARCH_PPC} \
-%{mcpu=620: -D_ARCH_PPC} \
-%{mcpu=740: -D_ARCH_PPC} \
-%{mcpu=750: -D_ARCH_PPC} \
-%{mcpu=801: -D_ARCH_PPC} \
-%{mcpu=821: -D_ARCH_PPC} \
-%{mcpu=823: -D_ARCH_PPC} \
-%{mcpu=860: -D_ARCH_PPC}"
-
-#ifndef CPP_DEFAULT_SPEC
-#define CPP_DEFAULT_SPEC "-D_ARCH_PWR"
-#endif
-
-#ifndef CPP_SYSV_SPEC
-#define CPP_SYSV_SPEC ""
-#endif
-
-#ifndef CPP_ENDIAN_SPEC
-#define CPP_ENDIAN_SPEC ""
-#endif
-
-#ifndef CPP_ENDIAN_DEFAULT_SPEC
-#define CPP_ENDIAN_DEFAULT_SPEC ""
-#endif
-
-#ifndef CPP_SYSV_DEFAULT_SPEC
-#define CPP_SYSV_DEFAULT_SPEC ""
-#endif
-
-/* Common ASM definitions used by ASM_SPEC among the various targets
-   for handling -mcpu=xxx switches.  */
-#define ASM_CPU_SPEC \
-"%{!mcpu*: \
-  %{mpower: %{!mpower2: -mpwr}} \
-  %{mpower2: -mpwrx} \
-  %{mpowerpc*: -mppc} \
-  %{mno-power: %{!mpowerpc*: -mcom}} \
-  %{!mno-power: %{!mpower2: %(asm_default)}}} \
-%{mcpu=common: -mcom} \
-%{mcpu=power: -mpwr} \
-%{mcpu=power2: -mpwrx} \
-%{mcpu=powerpc: -mppc} \
-%{mcpu=rios: -mpwr} \
-%{mcpu=rios1: -mpwr} \
-%{mcpu=rios2: -mpwrx} \
-%{mcpu=rsc: -mpwr} \
-%{mcpu=rsc1: -mpwr} \
-%{mcpu=401: -mppc} \
-%{mcpu=403: -mppc} \
-%{mcpu=505: -mppc} \
-%{mcpu=601: -m601} \
-%{mcpu=602: -mppc} \
-%{mcpu=603: -mppc} \
-%{mcpu=603e: -mppc} \
-%{mcpu=ec603e: -mppc} \
-%{mcpu=604: -mppc} \
-%{mcpu=604e: -mppc} \
-%{mcpu=620: -mppc} \
-%{mcpu=740: -mppc} \
-%{mcpu=750: -mppc} \
-%{mcpu=821: -mppc} \
-%{mcpu=823: -mppc} \
-%{mcpu=860: -mppc}"
-
-#ifndef ASM_DEFAULT_SPEC
-#define ASM_DEFAULT_SPEC ""
-#endif
-
-/* This macro defines names of additional specifications to put in the specs
-   that can be used in various specifications like CC1_SPEC.  Its definition
-   is an initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   specification name, and a string constant that used by the GNU CC driver
-   program.
-
-   Do not define this macro if it does not need to do anything.  */
-
-#ifndef SUBTARGET_EXTRA_SPECS
-#define SUBTARGET_EXTRA_SPECS
-#endif
-
-#define EXTRA_SPECS							\
-  { "cpp_cpu",			CPP_CPU_SPEC },				\
-  { "cpp_default",		CPP_DEFAULT_SPEC },			\
-  { "cpp_sysv",			CPP_SYSV_SPEC },			\
-  { "cpp_sysv_default",		CPP_SYSV_DEFAULT_SPEC },		\
-  { "cpp_endian_default",	CPP_ENDIAN_DEFAULT_SPEC },		\
-  { "cpp_endian",		CPP_ENDIAN_SPEC },			\
-  { "asm_cpu",			ASM_CPU_SPEC },				\
-  { "asm_default",		ASM_DEFAULT_SPEC },			\
-  { "link_syscalls",		LINK_SYSCALLS_SPEC },			\
-  { "link_libg",		LINK_LIBG_SPEC },			\
-  SUBTARGET_EXTRA_SPECS
-
-/* Default location of syscalls.exp under AIX */
-#ifndef CROSS_COMPILE
-#define LINK_SYSCALLS_SPEC "-bI:/lib/syscalls.exp"
-#else
-#define LINK_SYSCALLS_SPEC ""
-#endif
-
-/* Default location of libg.exp under AIX */
-#ifndef CROSS_COMPILE
-#define LINK_LIBG_SPEC "-bexport:/usr/lib/libg.exp"
-#else
-#define LINK_LIBG_SPEC ""
-#endif
-
-/* Define the options for the binder: Start text at 512, align all segments
-   to 512 bytes, and warn if there is text relocation.
-
-   The -bhalt:4 option supposedly changes the level at which ld will abort,
-   but it also suppresses warnings about multiply defined symbols and is
-   used by the AIX cc command.  So we use it here.
-
-   -bnodelcsect undoes a poor choice of default relating to multiply-defined
-   csects.  See AIX documentation for more information about this.
-
-   -bM:SRE tells the linker that the output file is Shared REusable.  Note
-   that to actually build a shared library you will also need to specify an
-   export list with the -Wl,-bE option.  */
-
-#define LINK_SPEC "-T512 -H512 %{!r:-btextro} -bhalt:4 -bnodelcsect\
-   %{static:-bnso %(link_syscalls) } \
-   %{!shared:%{g*: %(link_libg) }} %{shared:-bM:SRE}"
-
-/* Profiled library versions are used by linking with special directories.  */
-#define LIB_SPEC "%{pg:-L/lib/profiled -L/usr/lib/profiled}\
-   %{p:-L/lib/profiled -L/usr/lib/profiled} %{!shared:%{g*:-lg}} -lc"
-
-/* gcc must do the search itself to find libgcc.a, not use -l.  */
-#define LIBGCC_SPEC "libgcc.a%s"
-
-/* Don't turn -B into -L if the argument specifies a relative file name.  */
-#define RELATIVE_PREFIX_NOT_LINKDIR
-
-/* Architecture type.  */
-
-extern int target_flags;
-
-/* Use POWER architecture instructions and MQ register.  */
-#define MASK_POWER		0x00000001
-
-/* Use POWER2 extensions to POWER architecture.  */
-#define MASK_POWER2		0x00000002
-
-/* Use PowerPC architecture instructions.  */
-#define MASK_POWERPC		0x00000004
-
-/* Use PowerPC General Purpose group optional instructions, e.g. fsqrt.  */
-#define MASK_PPC_GPOPT		0x00000008
-
-/* Use PowerPC Graphics group optional instructions, e.g. fsel.  */
-#define MASK_PPC_GFXOPT		0x00000010
-
-/* Use PowerPC-64 architecture instructions.  */
-#define MASK_POWERPC64		0x00000020
-
-/* Use revised mnemonic names defined for PowerPC architecture.  */
-#define MASK_NEW_MNEMONICS	0x00000040
-
-/* Disable placing fp constants in the TOC; can be turned on when the
-   TOC overflows.  */
-#define MASK_NO_FP_IN_TOC	0x00000080
-
-/* Disable placing symbol+offset constants in the TOC; can be turned on when
-   the TOC overflows.  */
-#define MASK_NO_SUM_IN_TOC	0x00000100
-
-/* Output only one TOC entry per module.  Normally linking fails if
-   there are more than 16K unique variables/constants in an executable.  With
-   this option, linking fails only if there are more than 16K modules, or
-   if there are more than 16K unique variables/constant in a single module.
-
-   This is at the cost of having 2 extra loads and one extra store per
-   function, and one less allocable register.  */
-#define MASK_MINIMAL_TOC	0x00000200
-
-/* Nonzero for the 64bit model: ints, longs, and pointers are 64 bits.  */
-#define MASK_64BIT		0x00000400
-
-/* Disable use of FPRs.  */
-#define MASK_SOFT_FLOAT		0x00000800
-
-/* Enable load/store multiple, even on powerpc */
-#define	MASK_MULTIPLE		0x00001000
-#define	MASK_MULTIPLE_SET	0x00002000
-
-/* Use string instructions for block moves */
-#define MASK_STRING		0x00004000
-#define MASK_STRING_SET		0x00008000
-
-/* Disable update form of load/store */
-#define MASK_NO_UPDATE		0x00010000
-
-/* Disable fused multiply/add operations */
-#define MASK_NO_FUSED_MADD	0x00020000
-
-/* CYGNUS LOCAL -- vmakarov/prolog-epilog instruction scheduling */
-/* Nonzero if we need to make scheduling prolog  */
-#define MASK_SCHED_PROLOG	(0x40000)
-/* Nonzero if we need to make scheduling epilog */
-#define MASK_SCHED_EPILOG	(0x80000)
-/* END CYGNUS LOCAL */
-
-#define TARGET_POWER		(target_flags & MASK_POWER)
-#define TARGET_POWER2		(target_flags & MASK_POWER2)
-#define TARGET_POWERPC		(target_flags & MASK_POWERPC)
-#define TARGET_PPC_GPOPT	(target_flags & MASK_PPC_GPOPT)
-#define TARGET_PPC_GFXOPT	(target_flags & MASK_PPC_GFXOPT)
-#define TARGET_POWERPC64	(target_flags & MASK_POWERPC64)
-#define TARGET_NEW_MNEMONICS	(target_flags & MASK_NEW_MNEMONICS)
-#define TARGET_NO_FP_IN_TOC	(target_flags & MASK_NO_FP_IN_TOC)
-#define TARGET_NO_SUM_IN_TOC	(target_flags & MASK_NO_SUM_IN_TOC)
-#define TARGET_MINIMAL_TOC	(target_flags & MASK_MINIMAL_TOC)
-#define TARGET_64BIT		(target_flags & MASK_64BIT)
-#define TARGET_SOFT_FLOAT	(target_flags & MASK_SOFT_FLOAT)
-#define	TARGET_MULTIPLE		(target_flags & MASK_MULTIPLE)
-#define	TARGET_MULTIPLE_SET	(target_flags & MASK_MULTIPLE_SET)
-#define TARGET_STRING		(target_flags & MASK_STRING)
-#define TARGET_STRING_SET	(target_flags & MASK_STRING_SET)
-#define TARGET_NO_UPDATE	(target_flags & MASK_NO_UPDATE)
-#define TARGET_NO_FUSED_MADD	(target_flags & MASK_NO_FUSED_MADD)
-
-#define TARGET_32BIT		(! TARGET_64BIT)
-#define TARGET_HARD_FLOAT	(! TARGET_SOFT_FLOAT)
-#define TARGET_UPDATE		(! TARGET_NO_UPDATE)
-#define TARGET_FUSED_MADD	(! TARGET_NO_FUSED_MADD)
-
-/* Pseudo target to indicate whether the object format is ELF
-   (to get around not having conditional compilation in the md file)  */
-#ifndef	TARGET_ELF
-#define	TARGET_ELF		0
-#endif
-
-/* If this isn't V.4, don't support -mno-toc.  */
-#ifndef TARGET_NO_TOC
-#define TARGET_NO_TOC		0
-#define	TARGET_TOC		1
-#endif
-
-/* Pseudo target to say whether this is Windows NT */
-#ifndef	TARGET_WINDOWS_NT
-#define	TARGET_WINDOWS_NT 0
-#endif
-
-/* Pseudo target to say whether this is MAC */
-#ifndef	TARGET_MACOS
-#define	TARGET_MACOS 0
-#endif
-
-/* Pseudo target to say whether this is AIX */
-#ifndef TARGET_AIX
-#if (TARGET_ELF || TARGET_WINDOWS_NT || TARGET_MACOS)
-#define TARGET_AIX 0
-#else
-#define TARGET_AIX 1
-#endif
-#endif
-
-#ifndef TARGET_XL_CALL
-#define TARGET_XL_CALL 0
-#endif
-
-/* Run-time compilation parameters selecting different hardware subsets.
-
-   Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-/* This is meant to be redefined in the host dependent files */
-#ifndef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES
-#endif
-
-#define TARGET_SWITCHES							\
- {{"power",		MASK_POWER  | MASK_MULTIPLE | MASK_STRING},	\
-  {"power2",		(MASK_POWER | MASK_MULTIPLE | MASK_STRING	\
-			 | MASK_POWER2)},				\
-  {"no-power2",		- MASK_POWER2},					\
-  {"no-power",		- (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE	\
-			   | MASK_STRING)},				\
-  {"powerpc",		MASK_POWERPC},					\
-  {"no-powerpc",	- (MASK_POWERPC | MASK_PPC_GPOPT		\
-			   | MASK_PPC_GFXOPT | MASK_POWERPC64)},	\
-  {"powerpc-gpopt",	MASK_POWERPC | MASK_PPC_GPOPT},			\
-  {"no-powerpc-gpopt",	- MASK_PPC_GPOPT},				\
-  {"powerpc-gfxopt",	MASK_POWERPC | MASK_PPC_GFXOPT},		\
-  {"no-powerpc-gfxopt",	- MASK_PPC_GFXOPT},				\
-  {"powerpc64",		MASK_POWERPC64},				\
-  {"no-powerpc64",	- MASK_POWERPC64},				\
-  {"new-mnemonics",	MASK_NEW_MNEMONICS},				\
-  {"old-mnemonics",	-MASK_NEW_MNEMONICS},				\
-  {"full-toc",		- (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC	\
-			   | MASK_MINIMAL_TOC)},			\
-  {"fp-in-toc",		- MASK_NO_FP_IN_TOC},				\
-  {"no-fp-in-toc",	MASK_NO_FP_IN_TOC},				\
-  {"sum-in-toc",	- MASK_NO_SUM_IN_TOC},				\
-  {"no-sum-in-toc",	MASK_NO_SUM_IN_TOC},				\
-  {"minimal-toc",	MASK_MINIMAL_TOC},				\
-  {"minimal-toc",	- (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC)},	\
-  {"no-minimal-toc",	- MASK_MINIMAL_TOC},				\
-  {"hard-float",	- MASK_SOFT_FLOAT},				\
-  {"soft-float",	MASK_SOFT_FLOAT},				\
-  {"multiple",		MASK_MULTIPLE | MASK_MULTIPLE_SET},		\
-  {"no-multiple",	- MASK_MULTIPLE},				\
-  {"no-multiple",	MASK_MULTIPLE_SET},				\
-  {"string",		MASK_STRING | MASK_STRING_SET},			\
-  {"no-string",		- MASK_STRING},					\
-  {"no-string",		MASK_STRING_SET},				\
-  {"update",		- MASK_NO_UPDATE},				\
-  {"no-update",		MASK_NO_UPDATE},				\
-  {"fused-madd",	- MASK_NO_FUSED_MADD},				\
-  {"no-fused-madd",	MASK_NO_FUSED_MADD},				\
-/* CYGNUS LOCAL -- vmakarov/prolog-epilog instruction scheduling */     \
-  {"sched-prolog",      MASK_SCHED_PROLOG},                             \
-  {"no-sched-prolog",   -MASK_SCHED_PROLOG},                            \
-  {"sched-epilog",      MASK_SCHED_EPILOG},                             \
-  {"no-sched-epilog",   -MASK_SCHED_EPILOG},                            \
-/* END CYGNUS LOCAL */							\
-  SUBTARGET_SWITCHES							\
-  {"",			TARGET_DEFAULT}}
-
-#define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
-
-/* Processor type.  Order must match cpu attribute in MD file.  */
-enum processor_type
-{
-  PROCESSOR_RIOS1,
-  PROCESSOR_RIOS2,
-  PROCESSOR_MPCCORE,
-  PROCESSOR_PPC403,
-  PROCESSOR_PPC601,
-  PROCESSOR_PPC603,
-  PROCESSOR_PPC604,
-  PROCESSOR_PPC604e,
-  PROCESSOR_PPC620,
-  PROCESSOR_PPC750
-};
-
-extern enum processor_type rs6000_cpu;
-
-/* Recast the processor type to the cpu attribute.  */
-#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
-
-/* Define generic processor types based upon current deployment.  */
-#define PROCESSOR_COMMON  PROCESSOR_PPC601
-#define PROCESSOR_POWER   PROCESSOR_RIOS1
-#define PROCESSOR_POWERPC PROCESSOR_PPC604
-
-/* Define the default processor.  This is overridden by other tm.h files.  */
-#define PROCESSOR_DEFAULT PROCESSOR_RIOS1
-
-/* Specify the dialect of assembler to use.  New mnemonics is dialect one
-   and the old mnemonics are dialect zero.  */
-#define ASSEMBLER_DIALECT TARGET_NEW_MNEMONICS ? 1 : 0
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an
-   initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   fixed part of the option name, and the address of a variable.
-   The variable, type `char *', is set to the variable part of the
-   given option if the fixed part matches.  The actual option name
-   is made by appending `-m' to the specified name.
-
-   Here is an example which defines `-mshort-data-NUMBER'.  If the
-   given option is `-mshort-data-512', the variable `m88k_short_data'
-   will be set to the string `"512"'.
-
-	extern char *m88k_short_data;
-	#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } }  */
-
-/* This is meant to be overridden in target specific files.  */
-#ifndef SUBTARGET_OPTIONS
-#define	SUBTARGET_OPTIONS
-#endif
-
-#define TARGET_OPTIONS				\
-{						\
-   {"cpu=",  &rs6000_select[1].string},		\
-   {"tune=", &rs6000_select[2].string},		\
-   {"debug-", &rs6000_debug_name},		\
-   {"debug=", &rs6000_debug_name},		\
-   /* CYGNUS LOCAL -- vmakarov */		\
-   {"branch-cost=", &rs6000_branch_cost_string},\
-   /* END CYGNUS LOCAL */			\
-   SUBTARGET_OPTIONS				\
-}
-
-/* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
-struct rs6000_cpu_select
-{
-  char *string;
-  char *name;
-  int set_tune_p;
-  int set_arch_p;
-};
-
-extern struct rs6000_cpu_select rs6000_select[];
-
-/* Debug support */
-extern char *rs6000_debug_name;		/* Name for -mdebug-xxxx option */
-extern int rs6000_debug_stack;		/* debug stack applications */
-extern int rs6000_debug_arg;		/* debug argument handling */
-
-#define	TARGET_DEBUG_STACK	rs6000_debug_stack
-#define	TARGET_DEBUG_ARG	rs6000_debug_arg
-
-/* CYGNUS LOCAL -- vmakarov/prolog-epilog instruction scheduling. */
-#define TARGET_SCHED_PROLOG	((target_flags & MASK_SCHED_PROLOG)\
-				 && rs6000_current_abi == ABI_V4)
-#define TARGET_SCHED_EPILOG	((target_flags & MASK_SCHED_EPILOG)\
-				 && rs6000_current_abi == ABI_V4)
-/* END CYGNUS LOCAL */
-
-/* CYGNUS LOCAL -- vmakarov */
-/* Override for BRANCH_COST */
-extern char *rs6000_branch_cost_string;
-int rs6000_branch_cost;
-/* END CYGNUS LOCAL */
-
-/* Sometimes certain combinations of command options do not make sense
-   on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.
-
-   On the RS/6000 this is used to define the target cpu type.  */
-
-#define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
-
-/* Define this to change the optimizations performed by default.  */
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
-
-
-/* Show we can debug even without a frame pointer.  */
-#define CAN_DEBUG_WITHOUT_FP
-
-/* target machine storage layout */
-
-/* Define to support cross compilation to an RS6000 target.  */
-#define REAL_ARITHMETIC
-
-/* Define this macro if it is advisable to hold scalars in registers
-   in a wider mode than that declared by the program.  In such cases,
-   the value is constrained to be within the bounds of the declared
-   type, but kept valid in the wider mode.  The signedness of the
-   extension may differ from that of the type.  */
-
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)	\
-  if (GET_MODE_CLASS (MODE) == MODE_INT		\
-      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
-    (MODE) = (! TARGET_POWERPC64 ? SImode : DImode);
-
-/* Define this if function arguments should also be promoted using the above
-   procedure.  */
-
-#define PROMOTE_FUNCTION_ARGS
-
-/* Likewise, if the function return value is promoted.  */
-
-#define PROMOTE_FUNCTION_RETURN
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields. */
-/* That is true on RS/6000. */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is true on RS/6000.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered.
-
-   For RS/6000 we can decide arbitrarily since there are no machine
-   instructions for them.  Might as well be consistent with bits and bytes. */
-#define WORDS_BIG_ENDIAN 1
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD (! TARGET_POWERPC64 ? 32 : 64)
-#define MAX_BITS_PER_WORD 64
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
-#define MIN_UNITS_PER_WORD 4
-#define UNITS_PER_FP_WORD 8
-
-/* Type used for ptrdiff_t, as a string used in a declaration.  */
-#define PTRDIFF_TYPE "int"
-
-/* Type used for wchar_t, as a string used in a declaration.  */
-#define WCHAR_TYPE "short unsigned int"
-
-/* Width of wchar_t in bits.  */
-#define WCHAR_TYPE_SIZE 16
-
-/* A C expression for the size in bits of the type `short' on the
-   target machine.  If you don't define this, the default is half a
-   word.  (If this would be less than one storage unit, it is
-   rounded up to one unit.)  */
-#define SHORT_TYPE_SIZE 16
-
-/* A C expression for the size in bits of the type `int' on the
-   target machine.  If you don't define this, the default is one
-   word.  */
-#define INT_TYPE_SIZE 32
-
-/* A C expression for the size in bits of the type `long' on the
-   target machine.  If you don't define this, the default is one
-   word.  */
-#define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
-#define MAX_LONG_TYPE_SIZE 64
-
-/* A C expression for the size in bits of the type `long long' on the
-   target machine.  If you don't define this, the default is two
-   words.  */
-#define LONG_LONG_TYPE_SIZE 64
-
-/* A C expression for the size in bits of the type `char' on the
-   target machine.  If you don't define this, the default is one
-   quarter of a word.  (If this would be less than one storage unit,
-   it is rounded up to one unit.)  */
-#define CHAR_TYPE_SIZE BITS_PER_UNIT
-
-/* A C expression for the size in bits of the type `float' on the
-   target machine.  If you don't define this, the default is one
-   word.  */
-#define FLOAT_TYPE_SIZE 32
-
-/* A C expression for the size in bits of the type `double' on the
-   target machine.  If you don't define this, the default is two
-   words.  */
-#define DOUBLE_TYPE_SIZE 64
-
-/* A C expression for the size in bits of the type `long double' on
-   the target machine.  If you don't define this, the default is two
-   words.  */
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY (TARGET_32BIT ? 64 : 128)
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 32
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 64
-
-/* AIX word-aligns FP doubles but doubleword-aligns 64-bit ints.  */
-#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
-  (TYPE_MODE (TREE_CODE (TREE_TYPE (FIELD)) == ARRAY_TYPE \
-	      ? get_inner_array_type (FIELD) \
-	      : TREE_TYPE (FIELD)) == DFmode \
-   ? MIN ((COMPUTED), 32) : (COMPUTED))
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* AIX increases natural record alignment to doubleword if the first
-   field is an FP double while the FP fields remain word aligned.  */
-#define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED)	\
-  ((TREE_CODE (STRUCT) == RECORD_TYPE			\
-    || TREE_CODE (STRUCT) == UNION_TYPE			\
-    || TREE_CODE (STRUCT) == QUAL_UNION_TYPE)		\
-   && TYPE_FIELDS (STRUCT) != 0				\
-   && DECL_MODE (TYPE_FIELDS (STRUCT)) == DFmode	\
-   ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
-   : MAX ((COMPUTED), (SPECIFIED)))
-
-/* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  (TREE_CODE (EXP) == STRING_CST	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Non-zero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 0
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   RS/6000 has 32 fixed-point registers, 32 floating-point registers,
-   an MQ register, a count register, a link register, and 8 condition
-   register fields, which we view here as separate registers.
-
-   In addition, the difference between the frame and argument pointers is
-   a function of the number of registers saved, so we need to have a
-   register for AP that will later be eliminated in favor of SP or FP.
-   This is a normal register, but it is fixed.
-
-   We also create a pseudo register for float/int conversions, that will
-   really represent the memory location used.  It is represented here as
-   a register, in order to work around problems in allocating stack storage
-   in inline functions.  */
-
-#define FIRST_PSEUDO_REGISTER 77
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   On RS/6000, r1 is used for the stack and r2 is used as the TOC pointer.
-
-   cr5 is not supposed to be used.
-
-   On System V implementations, r13 is fixed and not available for use.  */
-
-#ifndef FIXED_R13
-#define FIXED_R13 0
-#endif
-
-#define FIXED_REGISTERS  \
-  {0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
-   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-   0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-
-#define CALL_USED_REGISTERS  \
-  {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
-   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
-   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-   1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1}
-
-/* List the order in which to allocate registers.  Each register must be
-   listed once, even those in FIXED_REGISTERS.
-
-   We allocate in the following order:
-	fp0		(not saved or used for anything)
-	fp13 - fp2	(not saved; incoming fp arg registers)
-	fp1		(not saved; return value)
- 	fp31 - fp14	(saved; order given to save least number)
-	cr7, cr6	(not saved or special)
-	cr1		(not saved, but used for FP operations)
-	cr0		(not saved, but used for arithmetic operations)
-	cr4, cr3, cr2	(saved)
-        r0		(not saved; cannot be base reg)
-	r9		(not saved; best for TImode)
-	r11, r10, r8-r4	(not saved; highest used first to make less conflict)
-	r3     		(not saved; return value register)
-	r31 - r13	(saved; order given to save least number)
-	r12		(not saved; if used for DImode or DFmode would use r13)
-	mq		(not saved; best to use it if we can)
-	ctr		(not saved; when we have the choice ctr is better)
-	lr		(saved)
-        cr5, r1, r2, ap, fpmem (fixed)  */
-
-#define REG_ALLOC_ORDER					\
-  {32, 							\
-   45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34,	\
-   33,							\
-   63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51,	\
-   50, 49, 48, 47, 46, 					\
-   75, 74, 69, 68, 72, 71, 70,				\
-   0,							\
-   9, 11, 10, 8, 7, 6, 5, 4,				\
-   3,							\
-   31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19,	\
-   18, 17, 16, 15, 14, 13, 12,				\
-   64, 66, 65, 						\
-   73, 1, 2, 67, 76}
-
-/* True if register is floating-point.  */
-#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
-
-/* True if register is a condition register.  */
-#define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
-
-/* True if register is condition register 0.  */
-#define CR0_REGNO_P(N) ((N) == 68)
-
-/* True if register is a condition register, but not cr0.  */
-#define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
-
-/* True if register is an integer register.  */
-#define INT_REGNO_P(N) ((N) <= 31 || (N) == 67)
-
-/* True if register is the temporary memory location used for int/float
-   conversion.  */
-#define FPMEM_REGNO_P(N) ((N) == FPMEM_REGNUM)
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   POWER and PowerPC GPRs hold 32 bits worth;
-   PowerPC64 GPRs and FPRs point register holds 64 bits worth.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)					\
-  (FP_REGNO_P (REGNO) || FPMEM_REGNO_P (REGNO)				\
-   ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
-   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   For POWER and PowerPC, the GPRs can hold any mode, but the float
-   registers only can hold floating modes and DImode, and CR register only
-   can hold CC modes.  We cannot put TImode anywhere except general
-   register and it must be able to fit within the register set. */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE)					\
-  (FP_REGNO_P (REGNO) ?							\
-   (GET_MODE_CLASS (MODE) == MODE_FLOAT					\
-    || (GET_MODE_CLASS (MODE) == MODE_INT				\
-	&& GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD))			\
-   : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC		\
-   : FPMEM_REGNO_P (REGNO) ? ((MODE) == DImode || (MODE) == DFmode)	\
-   : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT		\
-			      && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
-   : 1)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  (GET_MODE_CLASS (MODE1) == MODE_FLOAT		\
-   ? GET_MODE_CLASS (MODE2) == MODE_FLOAT	\
-   : GET_MODE_CLASS (MODE2) == MODE_FLOAT	\
-   ? GET_MODE_CLASS (MODE1) == MODE_FLOAT	\
-   : GET_MODE_CLASS (MODE1) == MODE_CC		\
-   ? GET_MODE_CLASS (MODE2) == MODE_CC		\
-   : GET_MODE_CLASS (MODE2) == MODE_CC		\
-   ? GET_MODE_CLASS (MODE1) == MODE_CC		\
-   : 1)
-
-/* A C expression returning the cost of moving data from a register of class
-   CLASS1 to one of CLASS2.
-
-   On the RS/6000, copying between floating-point and fixed-point
-   registers is expensive.  */
-
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)			\
-  ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2		\
-   : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10	\
-   : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10	\
-   : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS		\
-       || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS		\
-       || (CLASS1) == LINK_OR_CTR_REGS)				\
-      && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS	\
-	  || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS	\
-	  || (CLASS2) == LINK_OR_CTR_REGS)) ? 10		\
-   : 2)
-
-/* A C expressions returning the cost of moving data of MODE from a register to
-   or from memory.
-
-   On the RS/6000, bump this up a bit.  */
-
-#define MEMORY_MOVE_COST(MODE,CLASS,IN)	\
-  ((GET_MODE_CLASS (MODE) == MODE_FLOAT	\
-    && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \
-    ? 3 : 2) \
-   + 4)
-
-/* Specify the cost of a branch insn; roughly the number of extra insns that
-   should be added to avoid a branch.
-
-   Set this to 3 on the RS/6000 since that is roughly the average cost of an
-   unscheduled conditional branch.  */
-
-/* CYGNUS LOCAL -- vmakarov */
-#define BRANCH_COST_DEFAULT 3
-#define BRANCH_COST rs6000_branch_cost
-/* END CYGNUS LOCAL */
-
-/* A C statement (sans semicolon) to update the integer variable COST
-   based on the relationship between INSN that is dependent on
-   DEP_INSN through the dependence LINK.  The default is to make no
-   adjustment to COST.  On the RS/6000, ignore the cost of anti- and
-   output-dependencies.  In fact, output dependencies on the CR do have
-   a cost, but it is probably not worthwhile to track it.  */
-
-#define ADJUST_COST(INSN,LINK,DEP_INSN,COST)				\
-  (COST) = rs6000_adjust_cost (INSN,LINK,DEP_INSN,COST)
-
-/* A C statement (sans semicolon) to update the integer scheduling priority
-   INSN_PRIORITY (INSN).  Reduce the priority to execute the INSN earlier,
-   increase the priority to execute INSN later.  Do not define this macro if
-   you do not need to adjust the scheduling priorities of insns.  */
-
-#define ADJUST_PRIORITY(INSN)						\
-  INSN_PRIORITY (INSN) = rs6000_adjust_priority (INSN, INSN_PRIORITY (INSN))
-
-/* Define this macro to change register usage conditional on target flags.
-   Set MQ register fixed (already call_used) if not POWER architecture
-   (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
-   64-bit AIX reserves GPR13 for thread-private data.
-   Conditionally disable FPRs.  */
-
-#define CONDITIONAL_REGISTER_USAGE	\
-{					\
-  if (! TARGET_POWER)			\
-    fixed_regs[64] = 1;			\
-  if (TARGET_64BIT)			\
-    fixed_regs[13] = call_used_regs[13] = 1; \
-  if (TARGET_SOFT_FLOAT)		\
-    for (i = 32; i < 64; i++)		\
-      fixed_regs[i] = call_used_regs[i] = 1; \
-}
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* RS/6000 pc isn't overloaded on a register that the compiler knows about.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 1
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 31
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 67
-
-/* Place to put static chain when calling a function that requires it.  */
-#define STATIC_CHAIN_REGNUM 11
-
-/* count register number for special purposes */
-#define COUNT_REGISTER_REGNUM 66
-
-/* Special register that represents memory, used for float/int conversions.  */
-#define FPMEM_REGNUM 76
-
-/* Register to use as a placeholder for the GOT/allocated TOC register.
-   FINALIZE_PIC will change all uses of this register to a an appropriate
-   pseudo register when it adds the code to setup the GOT.  We use r2
-   because it is a reserved register in all of the ABI's.  */
-#define GOT_TOC_REGNUM 2
-
-/* Place that structure value return address is placed.
-
-   On the RS/6000, it is passed as an extra parameter.  */
-#define STRUCT_VALUE 0
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-/* The RS/6000 has three types of registers, fixed-point, floating-point,
-   and condition registers, plus three special registers, MQ, CTR, and the
-   link register.
-
-   However, r0 is special in that it cannot be used as a base register.
-   So make a class for registers valid as base registers.
-
-   Also, cr0 is the only condition code register that can be used in
-   arithmetic insns, so make a separate class for it.
-
-   There is a special 'register' (76), which is not a register, but a
-   placeholder for memory allocated to convert between floating point and
-   integral types.  This works around a problem where if we allocate memory
-   with allocate_stack_{local,temp} and the function is an inline function, the
-   memory allocated will clobber memory in the caller.  So we use a special
-   register, and if that is used, we allocate stack space for it.  */
-
-enum reg_class
-{
-  NO_REGS,
-  BASE_REGS,
-  GENERAL_REGS,
-  FLOAT_REGS,
-  NON_SPECIAL_REGS,
-  MQ_REGS,
-  LINK_REGS,
-  CTR_REGS,
-  LINK_OR_CTR_REGS,
-  SPECIAL_REGS,
-  SPEC_OR_GEN_REGS,
-  CR0_REGS,
-  CR_REGS,
-  NON_FLOAT_REGS,
-  FPMEM_REGS,
-  FLOAT_OR_FPMEM_REGS,
-  ALL_REGS,
-  LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES							\
-{									\
-  "NO_REGS",								\
-  "BASE_REGS",								\
-  "GENERAL_REGS",							\
-  "FLOAT_REGS",								\
-  "NON_SPECIAL_REGS",							\
-  "MQ_REGS",								\
-  "LINK_REGS",								\
-  "CTR_REGS",								\
-  "LINK_OR_CTR_REGS",							\
-  "SPECIAL_REGS",							\
-  "SPEC_OR_GEN_REGS",							\
-  "CR0_REGS",								\
-  "CR_REGS",								\
-  "NON_FLOAT_REGS",							\
-  "FPMEM_REGS",								\
-  "FLOAT_OR_FPMEM_REGS",						\
-  "ALL_REGS"								\
-}
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS						\
-{									\
-  { 0x00000000, 0x00000000, 0x00000000 },	/* NO_REGS */		\
-  { 0xfffffffe, 0x00000000, 0x00000008 },	/* BASE_REGS */		\
-  { 0xffffffff, 0x00000000, 0x00000008 },	/* GENERAL_REGS */	\
-  { 0x00000000, 0xffffffff, 0x00000000 },	/* FLOAT_REGS */	\
-  { 0xffffffff, 0xffffffff, 0x00000008 },	/* NON_SPECIAL_REGS */	\
-  { 0x00000000, 0x00000000, 0x00000001 },	/* MQ_REGS */		\
-  { 0x00000000, 0x00000000, 0x00000002 },	/* LINK_REGS */		\
-  { 0x00000000, 0x00000000, 0x00000004 },	/* CTR_REGS */		\
-  { 0x00000000, 0x00000000, 0x00000006 },	/* LINK_OR_CTR_REGS */	\
-  { 0x00000000, 0x00000000, 0x00000007 },	/* SPECIAL_REGS */	\
-  { 0xffffffff, 0x00000000, 0x0000000f },	/* SPEC_OR_GEN_REGS */	\
-  { 0x00000000, 0x00000000, 0x00000010 },	/* CR0_REGS */		\
-  { 0x00000000, 0x00000000, 0x00000ff0 },	/* CR_REGS */		\
-  { 0xffffffff, 0x00000000, 0x0000ffff },	/* NON_FLOAT_REGS */	\
-  { 0x00000000, 0x00000000, 0x00010000 },	/* FPMEM_REGS */	\
-  { 0x00000000, 0xffffffff, 0x00010000 },	/* FLOAT_OR_FPMEM_REGS */ \
-  { 0xffffffff, 0xffffffff, 0x0001ffff }	/* ALL_REGS */		\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO)		\
- ((REGNO) == 0 ? GENERAL_REGS		\
-  : (REGNO) < 32 ? BASE_REGS		\
-  : FP_REGNO_P (REGNO) ? FLOAT_REGS	\
-  : (REGNO) == 68 ? CR0_REGS		\
-  : CR_REGNO_P (REGNO) ? CR_REGS	\
-  : (REGNO) == 64 ? MQ_REGS		\
-  : (REGNO) == 65 ? LINK_REGS		\
-  : (REGNO) == 66 ? CTR_REGS		\
-  : (REGNO) == 67 ? BASE_REGS		\
-  : (REGNO) == 76 ? FPMEM_REGS		\
-  : NO_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS BASE_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'f' ? FLOAT_REGS	\
-   : (C) == 'b' ? BASE_REGS	\
-   : (C) == 'h' ? SPECIAL_REGS	\
-   : (C) == 'q' ? MQ_REGS	\
-   : (C) == 'c' ? CTR_REGS	\
-   : (C) == 'l' ? LINK_REGS	\
-   : (C) == 'x' ? CR0_REGS	\
-   : (C) == 'y' ? CR_REGS	\
-   : (C) == 'z' ? FPMEM_REGS	\
-   : NO_REGS)
-
-/* The letters I, J, K, L, M, N, and P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   `I' is signed 16-bit constants
-   `J' is a constant with only the high-order 16 bits non-zero
-   `K' is a constant with only the low-order 16 bits non-zero
-   `L' is a constant that can be placed into a mask operand
-   `M' is a constant that is greater than 31
-   `N' is a constant that is an exact power of two
-   `O' is the constant zero
-   `P' is a constant whose negation is a signed 16-bit constant */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)					\
-   ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000	\
-   : (C) == 'J' ? ((VALUE) & 0xffff) == 0				\
-   : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0		\
-   : (C) == 'L' ? mask_constant (VALUE)					\
-   : (C) == 'M' ? (VALUE) > 31						\
-   : (C) == 'N' ? exact_log2 (VALUE) >= 0				\
-   : (C) == 'O' ? (VALUE) == 0						\
-   : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x1000 \
-   : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.
-
-   We flag for special constants when we can copy the constant into
-   a general register in two insns for DF/DI and one insn for SF.
-
-   'H' is used for DI/DF constants that take 3 insns.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)				\
-  (  (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE))		\
-		   == ((GET_MODE (VALUE) == SFmode) ? 1 : 2))		\
-   : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3)	\
-   : 0)
-
-/* Optional extra constraints for this machine.
-
-   'Q' means that is a memory operand that is just an offset from a reg.
-   'R' is for AIX TOC entries.
-   'S' is a constant that can be placed into a 64-bit mask operand
-   'U' is for V.4 small data references.  */
-
-#define EXTRA_CONSTRAINT(OP, C)						\
-  ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG	\
-   : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP)		\
-   : (C) == 'S' ? mask64_operand (OP, VOIDmode)				\
-   : (C) == 'U' ? ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) \
-		   && small_data_operand (OP, GET_MODE (OP)))		\
-   : 0)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.
-
-   On the RS/6000, we have to return NO_REGS when we want to reload a
-   floating-point CONST_DOUBLE to force it to be copied to memory.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)			\
-  ((GET_CODE (X) == CONST_DOUBLE			\
-    && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT)	\
-   ? NO_REGS : (CLASS))
-
-/* Return the register class of a scratch register needed to copy IN into
-   or out of a register in CLASS in MODE.  If it can be done directly,
-   NO_REGS is returned.  */
-
-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
-  secondary_reload_class (CLASS, MODE, IN)
-
-/* If we are copying between FP registers and anything else, we need a memory
-   location.  */
-
-#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
- ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS || (CLASS2) == FLOAT_REGS))
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.
-
-   On RS/6000, this is the size of MODE in words,
-   except in the FP regs, where a single reg is enough for two words.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)					\
- (((CLASS) == FLOAT_REGS || (CLASS) == FPMEM_REGS			\
-   || (CLASS) == FLOAT_OR_FPMEM_REGS)					\
-  ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
-  : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* If defined, gives a class of registers that cannot be used as the
-   operand of a SUBREG that changes the size of the object.  */
-
-#define CLASS_CANNOT_CHANGE_SIZE	FLOAT_OR_FPMEM_REGS
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Enumeration to give which calling sequence to use.  */
-enum rs6000_abi {
-  ABI_NONE,
-  ABI_AIX,			/* IBM's AIX */
-  ABI_AIX_NODESC,		/* AIX calling sequence minus function descriptors */
-  ABI_V4,			/* System V.4/eabi */
-  ABI_NT,			/* Windows/NT */
-  ABI_SOLARIS			/* Solaris */
-};
-
-extern enum rs6000_abi rs6000_current_abi;	/* available for use by subtarget */
-
-/* Default ABI to compile code for */
-#ifndef DEFAULT_ABI
-#define DEFAULT_ABI ABI_AIX
-/* The prefix to add to user-visible assembler symbols. */
-#define USER_LABEL_PREFIX "."
-#endif
-
-/* Structure used to define the rs6000 stack */
-typedef struct rs6000_stack {
-  int first_gp_reg_save;	/* first callee saved GP register used */
-  int first_fp_reg_save;	/* first callee saved FP register used */
-  int lr_save_p;		/* true if the link reg needs to be saved */
-  int cr_save_p;		/* true if the CR reg needs to be saved */
-  int toc_save_p;		/* true if the TOC needs to be saved */
-  int push_p;			/* true if we need to allocate stack space */
-  int calls_p;			/* true if the function makes any calls */
-  int main_p;			/* true if this is main */
-  int main_save_p;		/* true if this is main and we need to save args */
-  int fpmem_p;			/* true if float/int conversion temp needed */
-  enum rs6000_abi abi;		/* which ABI to use */
-  int gp_save_offset;		/* offset to save GP regs from initial SP */
-  int fp_save_offset;		/* offset to save FP regs from initial SP */
-  int lr_save_offset;		/* offset to save LR from initial SP */
-  int cr_save_offset;		/* offset to save CR from initial SP */
-  int toc_save_offset;		/* offset to save the TOC pointer */
-  int varargs_save_offset;	/* offset to save the varargs registers */
-  int main_save_offset;		/* offset to save main's args */
-  int fpmem_offset;		/* offset for float/int conversion temp */
-  int reg_size;			/* register size (4 or 8) */
-  int varargs_size;		/* size to hold V.4 args passed in regs */
-  int vars_size;		/* variable save area size */
-  int parm_size;		/* outgoing parameter size */
-  int main_size;		/* size to hold saving main's args */
-  int save_size;		/* save area size */
-  int fixed_size;		/* fixed size of stack frame */
-  int gp_size;			/* size of saved GP registers */
-  int fp_size;			/* size of saved FP registers */
-  int cr_size;			/* size to hold CR if not in save_size */
-  int lr_size;			/* size to hold LR if not in save_size */
-  int fpmem_size;		/* size to hold float/int conversion */
-  int toc_size;			/* size to hold TOC if not in save_size */
-  int total_size;		/* total bytes allocated for stack */
-} rs6000_stack_t;
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.
-
-   On the RS/6000, we grow upwards, from the area after the outgoing
-   arguments.  */
-/* #define FRAME_GROWS_DOWNWARD */
-
-/* Size of the outgoing register save area */
-#define RS6000_REG_SAVE (TARGET_32BIT ? 32 : 64)
-
-/* Size of the fixed area on the stack */
-#define RS6000_SAVE_AREA (TARGET_32BIT ? 24 : 48)
-
-/* Address to save the TOC register */
-#define RS6000_SAVE_TOC plus_constant (stack_pointer_rtx, (TARGET_32BIT ? 20 : 40))
-
-/* Offset & size for fpmem stack locations used for converting between
-   float and integral types.  */
-extern int rs6000_fpmem_offset;
-extern int rs6000_fpmem_size;
-
-/* Size of the V.4 varargs area if needed */
-#define RS6000_VARARGS_AREA 0
-
-/* Whether a V.4 varargs area is needed */
-extern int rs6000_sysv_varargs_p;
-
-/* Align an address */
-#define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
-
-/* Initialize data used by insn expanders.  This is called from
-   init_emit, once for each function, before code is generated. */
-#define INIT_EXPANDERS rs6000_init_expanders ()
-
-/* Size of V.4 varargs area in bytes */
-#define RS6000_VARARGS_SIZE \
-  ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
-
-/* Offset of V.4 varargs area */
-#define RS6000_VARARGS_OFFSET						\
-  (RS6000_ALIGN (current_function_outgoing_args_size, 8)		\
-   + RS6000_SAVE_AREA)
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.
-
-   On the RS/6000, the frame pointer is the same as the stack pointer,
-   except for dynamic allocations.  So we start after the fixed area and
-   outgoing parameter area.  */
-
-#define STARTING_FRAME_OFFSET						\
-  (RS6000_ALIGN (current_function_outgoing_args_size, 8)		\
-   + RS6000_VARARGS_AREA						\
-   + RS6000_SAVE_AREA)
-
-/* Offset from the stack pointer register to an item dynamically
-   allocated on the stack, e.g., by `alloca'.
-
-   The default value for this macro is `STACK_POINTER_OFFSET' plus the
-   length of the outgoing arguments.  The default is correct for most
-   machines.  See `function.c' for details.  */
-#define STACK_DYNAMIC_OFFSET(FUNDECL)					\
-  (RS6000_ALIGN (current_function_outgoing_args_size, 8)		\
-   + (STACK_POINTER_OFFSET))
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On RS/6000, don't define this because there are no push insns.  */
-/*  #define PUSH_ROUNDING(BYTES) */
-
-/* Offset of first parameter from the argument pointer register value.
-   On the RS/6000, we define the argument pointer to the start of the fixed
-   area.  */
-#define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
-
-/* Define this if stack space is still allocated for a parameter passed
-   in a register.  The value is the number of bytes allocated to this
-   area.  */
-#define REG_PARM_STACK_SPACE(FNDECL)	RS6000_REG_SAVE
-
-/* Define this if the above stack space is to be considered part of the
-   space allocated by the caller.  */
-#define OUTGOING_REG_PARM_STACK_SPACE
-
-/* This is the difference between the logical top of stack and the actual sp.
-
-   For the RS/6000, sp points past the fixed area. */
-#define STACK_POINTER_OFFSET RS6000_SAVE_AREA
-
-/* Define this if the maximum size of all the outgoing args is to be
-   accumulated and pushed during the prologue.  The amount can be
-   found in the variable current_function_outgoing_args_size.  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.
-
-   On RS/6000 an integer value is in r3 and a floating-point value is in
-   fp1, unless -msoft-float.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)				\
-  gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE)			\
-		&& TYPE_PRECISION (VALTYPE) < BITS_PER_WORD)	\
-	       || POINTER_TYPE_P (VALTYPE)			\
-	       ? word_mode : TYPE_MODE (VALTYPE),		\
-	       TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT ? 33 : 3)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE)		\
-  gen_rtx_REG (MODE,			\
-	       GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT ? 33 : 3)
-
-/* The definition of this macro implies that there are cases where
-   a scalar value cannot be returned in registers.
-
-   For the RS/6000, any structure or union type is returned in memory, except for
-   Solaris, which returns structures <= 8 bytes in registers.  */
-
-#define RETURN_IN_MEMORY(TYPE)						\
-  (TYPE_MODE (TYPE) == BLKmode						\
-   && (DEFAULT_ABI != ABI_SOLARIS || int_size_in_bytes (TYPE) > 8))
-
-/* Mode of stack savearea.
-   FUNCTION is VOIDmode because calling convention maintains SP.
-   BLOCK needs Pmode for SP.
-   NONLOCAL needs twice Pmode to maintain both backchain and SP.  */
-#define STACK_SAVEAREA_MODE(LEVEL)	\
-  (LEVEL == SAVE_FUNCTION ? VOIDmode	\
-  : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
-
-/* Minimum and maximum general purpose registers used to hold arguments.  */
-#define GP_ARG_MIN_REG 3
-#define GP_ARG_MAX_REG 10
-#define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
-
-/* Minimum and maximum floating point registers used to hold arguments.  */
-#define FP_ARG_MIN_REG 33
-#define	FP_ARG_AIX_MAX_REG 45
-#define	FP_ARG_V4_MAX_REG  40
-#define FP_ARG_MAX_REG FP_ARG_AIX_MAX_REG
-#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
-
-/* Return registers */
-#define GP_ARG_RETURN GP_ARG_MIN_REG
-#define FP_ARG_RETURN FP_ARG_MIN_REG
-
-/* Flags for the call/call_value rtl operations set up by function_arg */
-#define CALL_NORMAL		0x00000000	/* no special processing */
-#define CALL_NT_DLLIMPORT	0x00000001	/* NT, this is a DLL import call */
-#define CALL_V4_CLEAR_FP_ARGS	0x00000002	/* V.4, no FP args passed */
-#define CALL_V4_SET_FP_ARGS	0x00000004	/* V.4, FP args were passed */
-#define CALL_LONG		0x00000008	/* always call indirect */
-
-/* Define cutoff for using external functions to save floating point */
-#define FP_SAVE_INLINE(FIRST_REG) ((FIRST_REG) == 62 || (FIRST_REG) == 63)
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.
-
-   On RS/6000, this is r3 and fp1.  */
-#define FUNCTION_VALUE_REGNO_P(N)  ((N) == GP_ARG_RETURN || ((N) == FP_ARG_RETURN))
-
-/* 1 if N is a possible register number for function argument passing.
-   On RS/6000, these are r3-r10 and fp1-fp13.  */
-#define FUNCTION_ARG_REGNO_P(N)						\
-  (((unsigned)((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG))	\
-   || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))
-
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the RS/6000, this is a structure.  The first element is the number of
-   total argument words, the second is used to store the next
-   floating-point register number, and the third says how many more args we
-   have prototype types for.
-
-   The System V.4 varargs/stdarg support requires that this structure's size
-   be a multiple of sizeof(int), and that WORDS, FREGNO, NARGS_PROTOTYPE,
-   ORIG_NARGS, and VARARGS_OFFSET be the first five ints.  */
-
-typedef struct rs6000_args
-{
-  int words;			/* # words uses for passing GP registers */
-  int fregno;			/* next available FP register */
-  int nargs_prototype;		/* # args left in the current prototype */
-  int orig_nargs;		/* Original value of nargs_prototype */
-  int varargs_offset;		/* offset of the varargs save area */
-  int prototype;		/* Whether a prototype was defined */
-  int call_cookie;		/* Do special things for this call */
-} CUMULATIVE_ARGS;
-
-/* Define intermediate macro to compute the size (in registers) of an argument
-   for the RS/6000.  */
-
-#define RS6000_ARG_SIZE(MODE, TYPE, NAMED)				\
-(! (NAMED) ? 0								\
- : (MODE) != BLKmode							\
- ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD 	\
- : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
-  init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
-
-/* Similar, but when scanning the definition of a procedure.  We always
-   set NARGS_PROTOTYPE large so we never return an EXPR_LIST.  */
-
-#define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
-  init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
-  function_arg_advance (&CUM, MODE, TYPE, NAMED)
-
-/* Non-zero if we can use a floating-point register to pass this arg.  */
-#define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
-  (GET_MODE_CLASS (MODE) == MODE_FLOAT  \
-   && (CUM).fregno <= FP_ARG_MAX_REG    \
-   && TARGET_HARD_FLOAT)
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-
-   On RS/6000 the first eight words of non-FP are normally in registers
-   and the rest are pushed.  The first 13 FP args are in registers.
-
-   If this is floating-point and no prototype is specified, we use
-   both an FP and integer register (or possibly FP reg and stack).  Library
-   functions (when TYPE is zero) always have the proper types for args,
-   so we can pass the FP value just in one register.  emit_library_function
-   doesn't support EXPR_LIST anyway.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  function_arg (&CUM, MODE, TYPE, NAMED)
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-  function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
-
-/* A C expression that indicates when an argument must be passed by
-   reference.  If nonzero for an argument, a copy of that argument is
-   made in memory and a pointer to the argument is passed instead of
-   the argument itself.  The pointer is passed in whatever way is
-   appropriate for passing a pointer to that type. */
-
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
-  function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
-
-/* If defined, a C expression which determines whether, and in which
-   direction, to pad out an argument with extra space.  The value
-   should be of type `enum direction': either `upward' to pad above
-   the argument, `downward' to pad below, or `none' to inhibit
-   padding.  */
-
-#define FUNCTION_ARG_PADDING(MODE, TYPE) \
-  (enum direction) function_arg_padding (MODE, TYPE)
-
-/* If defined, a C expression that gives the alignment boundary, in bits,
-   of an argument with the specified mode and type.  If it is not defined,
-   PARM_BOUNDARY is used for all arguments.  */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
-  function_arg_boundary (MODE, TYPE)
-
-/* Perform any needed actions needed for a function that is receiving a
-   variable number of arguments.
-
-   CUM is as above.
-
-   MODE and TYPE are the mode and type of the current parameter.
-
-   PRETEND_SIZE is a variable that should be set to the amount of stack
-   that must be pushed by the prolog to pretend that our caller pushed
-   it.
-
-   Normally, this macro will push all remaining incoming registers on the
-   stack and set PRETEND_SIZE to the length of the registers pushed.  */
-
-#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
-  setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
-
-/* If defined, is a C expression that produces the machine-specific
-   code for a call to `__builtin_saveregs'.  This code will be moved
-   to the very beginning of the function, before any parameter access
-   are made.  The return value of this function should be an RTX that
-   contains the value to use as the return of `__builtin_saveregs'.
-
-   The argument ARGS is a `tree_list' containing the arguments that
-   were passed to `__builtin_saveregs'.
-
-   If this macro is not defined, the compiler will output an ordinary
-   call to the library function `__builtin_saveregs'.  */
-
-#define EXPAND_BUILTIN_SAVEREGS(ARGS) \
-  expand_builtin_saveregs (ARGS)
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) output_prolog (FILE, SIZE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)	\
-  output_function_profiler ((FILE), (LABELNO));
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter. No definition is equivalent to
-   always zero.
-
-   On the RS/6000, this is non-zero because we can restore the stack from
-   its backpointer, which we maintain.  */
-#define EXIT_IGNORE_STACK	1
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) output_epilog (FILE, SIZE)
-
-/* A C compound statement that outputs the assembler code for a thunk function,
-   used to implement C++ virtual function calls with multiple inheritance.  The
-   thunk acts as a wrapper around a virtual function, adjusting the implicit
-   object parameter before handing control off to the real function.
-
-   First, emit code to add the integer DELTA to the location that contains the
-   incoming first argument.  Assume that this argument contains a pointer, and
-   is the one used to pass the `this' pointer in C++.  This is the incoming
-   argument *before* the function prologue, e.g. `%o0' on a sparc.  The
-   addition must preserve the values of all other incoming arguments.
-
-   After the addition, emit code to jump to FUNCTION, which is a
-   `FUNCTION_DECL'.  This is a direct pure jump, not a call, and does not touch
-   the return address.  Hence returning from FUNCTION will return to whoever
-   called the current `thunk'.
-
-   The effect must be as if FUNCTION had been called directly with the adjusted
-   first argument.  This macro is responsible for emitting all of the code for
-   a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not
-   invoked.
-
-   The THUNK_FNDECL is redundant.  (DELTA and FUNCTION have already been
-   extracted from it.)  It might possibly be useful on some targets, but
-   probably not.
-
-   If you do not define this macro, the target-independent code in the C++
-   frontend will generate a less efficient heavyweight thunk that calls
-   FUNCTION instead of jumping to it.  The generic approach does not support
-   varargs.  */
-#if TARGET_ELF
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
-  output_mi_thunk (FILE, THUNK_FNDECL, DELTA, FUNCTION)
-#endif
-
-/* TRAMPOLINE_TEMPLATE deleted */
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE rs6000_trampoline_size ()
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT)		\
-  rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
-
-/* If defined, a C expression whose value is nonzero if IDENTIFIER
-   with arguments ARGS is a valid machine specific attribute for DECL.
-   The attributes in ATTRIBUTES have previously been assigned to DECL.  */
-
-#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, NAME, ARGS) \
-  (rs6000_valid_decl_attribute_p (DECL, ATTRIBUTES, NAME, ARGS))
-
-/* If defined, a C expression whose value is nonzero if IDENTIFIER
-   with arguments ARGS is a valid machine specific attribute for TYPE.
-   The attributes in ATTRIBUTES have previously been assigned to TYPE.  */
-
-#define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
-  (rs6000_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
-
-/* If defined, a C expression whose value is zero if the attributes on
-   TYPE1 and TYPE2 are incompatible, one if they are compatible, and
-   two if they are nearly compatible (which causes a warning to be
-   generated).  */
-
-#define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
-  (rs6000_comp_type_attributes (TYPE1, TYPE2))
-
-/* If defined, a C statement that assigns default attributes to newly
-   defined TYPE.  */
-
-#define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
-  (rs6000_set_default_type_attributes (TYPE))
-
-
-/* Definitions for __builtin_return_address and __builtin_frame_address.
-   __builtin_return_address (0) should give link register (65), enable
-   this. */
-/* This should be uncommented, so that the link register is used, but
-   currently this would result in unmatched insns and spilling fixed
-   registers so we'll leave it for another day.  When these problems are
-   taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
-   (mrs) */
-/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
-
-/* Number of bytes into the frame return addresses can be found.  See
-   rs6000_stack_info in rs6000.c for more information on how the different
-   abi's store the return address.  */
-#define RETURN_ADDRESS_OFFSET						\
- ((DEFAULT_ABI == ABI_AIX						\
-   || DEFAULT_ABI == ABI_AIX_NODESC)	? 8 :				\
-  (DEFAULT_ABI == ABI_V4						\
-   || DEFAULT_ABI == ABI_SOLARIS)	? (TARGET_32BIT ? 4 : 8) :	\
-  (DEFAULT_ABI == ABI_NT)		? -4 :				\
-  (fatal ("RETURN_ADDRESS_OFFSET not supported"), 0))
-
-/* The current return address is in link register (65).  The return address
-   of anything farther back is accessed normally at an offset of 8 from the
-   frame pointer.  */
-#define RETURN_ADDR_RTX(count, frame)			\
-  ((count == -1)					\
-   ? gen_rtx_REG (Pmode, 65)				\
-   : gen_rtx_MEM (Pmode,				\
-	      memory_address (Pmode, 			\
-			      plus_constant (copy_to_reg (gen_rtx_MEM (Pmode, \
-								   memory_address (Pmode, frame))), \
-					     RETURN_ADDRESS_OFFSET))))
-
-/* Definitions for register eliminations.
-
-   We have two registers that can be eliminated on the RS/6000.  First, the
-   frame pointer register can often be eliminated in favor of the stack
-   pointer register.  Secondly, the argument pointer register can always be
-   eliminated; it is replaced with either the stack or frame pointer.
-
-   In addition, we use the elimination mechanism to see if r30 is needed
-   Initially we assume that it isn't.  If it is, we spill it.  This is done
-   by making it an eliminable register.  We replace it with itself so that
-   if it isn't needed, then existing uses won't be modified.  */
-
-/* This is an array of structures.  Each structure initializes one pair
-   of eliminable registers.  The "from" register number is given first,
-   followed by "to".  Eliminations of the same "from" register are listed
-   in order of preference.  */
-#define ELIMINABLE_REGS				\
-{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
- { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},	\
- { 30, 30} }
-
-/* Given FROM and TO register numbers, say whether this elimination is allowed.
-   Frame pointer elimination is automatically handled.
-
-   For the RS/6000, if frame pointer elimination is being done, we would like
-   to convert ap into fp, not sp.
-
-   We need r30 if -mminimal-toc was specified, and there are constant pool
-   references.  */
-
-#define CAN_ELIMINATE(FROM, TO)					\
- ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM	\
-  ? ! frame_pointer_needed					\
-  : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
-  : 1)
-
-/* Define the offset between two registers, one to be eliminated, and the other
-   its replacement, at the start of a routine.  */
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
-{									\
-  rs6000_stack_t *info = rs6000_stack_info ();				\
-									\
- if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	\
-   (OFFSET) = (info->push_p) ? 0 : - info->total_size;			\
- else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)	\
-   (OFFSET) = info->total_size;						\
- else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	\
-   (OFFSET) = (info->push_p) ? info->total_size : 0;			\
-  else if ((FROM) == 30)						\
-    (OFFSET) = 0;							\
-  else									\
-    abort ();								\
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-#define HAVE_PRE_DECREMENT 1
-#define HAVE_PRE_INCREMENT 1
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO)				\
-((REGNO) < FIRST_PSEUDO_REGISTER				\
- ? (REGNO) <= 31 || (REGNO) == 67				\
- : (reg_renumber[REGNO] >= 0					\
-    && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
-
-#define REGNO_OK_FOR_BASE_P(REGNO)				\
-((REGNO) < FIRST_PSEUDO_REGISTER				\
- ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67		\
- : (reg_renumber[REGNO] > 0					\
-    && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
-
-   On the RS/6000, all integer constants are acceptable, most won't be valid
-   for particular insns, though.  Only easy FP constants are
-   acceptable.  */
-
-#define LEGITIMATE_CONSTANT_P(X)				\
-  (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode	\
-   || (TARGET_POWERPC64 && GET_MODE (X) == DImode)		\
-   || easy_fp_constant (X, GET_MODE (X)))
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X)			\
-  (REGNO (X) <= 31 || REGNO (X) == 67 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X)					 \
-  (REGNO (X) > 0 && REG_OK_FOR_INDEX_P (X))
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   On the RS/6000, there are four valid address: a SYMBOL_REF that
-   refers to a constant pool entry of an address (or the sum of it
-   plus a constant), a short (16-bit signed) constant plus a register,
-   the sum of two registers, or a register indirect, possibly with an
-   auto-increment.  For DFmode and DImode with an constant plus register,
-   we must ensure that both words are addressable or PowerPC64 with offset
-   word aligned.
-
-   For modes spanning multiple registers (DFmode in 32-bit GPRs,
-   32-bit DImode, TImode), indexed addressing cannot be used because
-   adjacent memory cells are accessed by adding word-sized offsets
-   during assembly output.  */
-
-#define LEGITIMATE_CONSTANT_POOL_BASE_P(X)				\
-  (TARGET_TOC && GET_CODE (X) == SYMBOL_REF				\
-   && CONSTANT_POOL_ADDRESS_P (X)					\
-   && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (X)))
-
-/* AIX64 guaranteed to have 64 bit TOC alignment.  */
-#define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X)				\
-  (LEGITIMATE_CONSTANT_POOL_BASE_P (X)					\
-   || (TARGET_TOC							\
-       && GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS	\
-       && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT			\
-       && LEGITIMATE_CONSTANT_POOL_BASE_P (XEXP (XEXP (X, 0), 0))))
-
-#define LEGITIMATE_SMALL_DATA_P(MODE, X)				\
-  ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)		\
-   && !flag_pic && !TARGET_TOC						\
-   && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST)		\
-   && small_data_operand (X, MODE))
-
-#define LEGITIMATE_ADDRESS_INTEGER_P(X,OFFSET)				\
- (GET_CODE (X) == CONST_INT						\
-  && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
-
-#define LEGITIMATE_OFFSET_ADDRESS_P(MODE,X)		\
- (GET_CODE (X) == PLUS					\
-  && GET_CODE (XEXP (X, 0)) == REG			\
-  && REG_OK_FOR_BASE_P (XEXP (X, 0))			\
-  && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0)	\
-  && (((MODE) != DFmode && (MODE) != DImode)		\
-      || (TARGET_32BIT					\
-	  ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
-	  : ! (INTVAL (XEXP (X, 1)) & 3)))		\
-  && ((MODE) != TImode					\
-      || (TARGET_32BIT					\
-	  ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
-	  : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
-	     && ! (INTVAL (XEXP (X, 1)) & 3)))))
-
-#define LEGITIMATE_INDEXED_ADDRESS_P(X)		\
- (GET_CODE (X) == PLUS				\
-  && GET_CODE (XEXP (X, 0)) == REG		\
-  && GET_CODE (XEXP (X, 1)) == REG		\
-  && ((REG_OK_FOR_BASE_P (XEXP (X, 0))		\
-       && REG_OK_FOR_INDEX_P (XEXP (X, 1)))	\
-      || (REG_OK_FOR_BASE_P (XEXP (X, 1))	\
-	  && REG_OK_FOR_INDEX_P (XEXP (X, 0)))))
-
-#define LEGITIMATE_INDIRECT_ADDRESS_P(X)	\
-  (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
-
-#define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X)		\
-  (TARGET_ELF						\
-   && !flag_pic && !TARGET_TOC				\
-   && (MODE) != DImode					\
-   && (MODE) != TImode					\
-   && (TARGET_HARD_FLOAT || (MODE) != DFmode)		\
-   && GET_CODE (X) == LO_SUM				\
-   && GET_CODE (XEXP (X, 0)) == REG			\
-   && REG_OK_FOR_BASE_P (XEXP (X, 0))			\
-   && CONSTANT_P (XEXP (X, 1)))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)		\
-{ if (LEGITIMATE_INDIRECT_ADDRESS_P (X))		\
-    goto ADDR;						\
-  if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
-      && TARGET_UPDATE					\
-      && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (X, 0)))	\
-    goto ADDR;						\
-  if (LEGITIMATE_SMALL_DATA_P (MODE, X))		\
-    goto ADDR;						\
-  if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (X))		\
-    goto ADDR;						\
-  if (LEGITIMATE_OFFSET_ADDRESS_P (MODE, X))		\
-    goto ADDR;						\
-  if ((MODE) != TImode					\
-      && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || (MODE) != DFmode) \
-      && (TARGET_POWERPC64 || (MODE) != DImode)		\
-      && LEGITIMATE_INDEXED_ADDRESS_P (X))		\
-    goto ADDR;						\
-  if (LEGITIMATE_LO_SUM_ADDRESS_P (MODE, X))		\
-    goto ADDR;						\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   On RS/6000, first check for the sum of a register with a constant
-   integer that is out of range.  If so, generate code to add the
-   constant with the low-order 16 bits masked to the register and force
-   this result into another register (this can be done with `cau').
-   Then generate an address of REG+(CONST&0xffff), allowing for the
-   possibility of bit 16 being a one.
-
-   Then check for the sum of a register and something not constant, try to
-   load the other things into a register and return the sum.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)				\
-{ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG		\
-    && GET_CODE (XEXP (X, 1)) == CONST_INT				\
-    && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) + 0x8000) >= 0x10000) \
-    { HOST_WIDE_INT high_int, low_int;					\
-      rtx sum;								\
-      high_int = INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff);	\
-      low_int = INTVAL (XEXP (X, 1)) & 0xffff;				\
-      if (low_int & 0x8000)						\
-	high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16;	\
-      sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (X, 0),		\
-				    GEN_INT (high_int)), 0);		\
-      (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));		\
-      goto WIN;								\
-    }									\
-  else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG	\
-	   && GET_CODE (XEXP (X, 1)) != CONST_INT			\
-	   && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || (MODE) != DFmode) \
-	   && (TARGET_POWERPC64 || (MODE) != DImode)			\
-	   && (MODE) != TImode)						\
-    {									\
-      (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0),				\
-		     force_reg (Pmode, force_operand (XEXP (X, 1), 0))); \
-      goto WIN;								\
-    }									\
-  else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC			\
-	   && !flag_pic							\
-	   && GET_CODE (X) != CONST_INT					\
-	   && GET_CODE (X) != CONST_DOUBLE && CONSTANT_P (X)		\
-	   && (TARGET_HARD_FLOAT || (MODE) != DFmode)			\
-	   && (MODE) != DImode && (MODE) != TImode)			\
-    {									\
-      rtx reg = gen_reg_rtx (Pmode);					\
-      emit_insn (gen_elf_high (reg, (X)));				\
-      (X) = gen_rtx_LO_SUM (Pmode, reg, (X));				\
-      goto WIN;								\
-    }									\
-}
-
-/* Try a machine-dependent way of reloading an illegitimate address
-   operand.  If we find one, push the reload and jump to WIN.  This
-   macro is used in only one place: `find_reloads_address' in reload.c.
-
-   For RS/6000, we wish to handle large displacements off a base
-   register by splitting the addend across an addiu/addis and the mem insn.
-   This cuts number of extra insns needed from 3 to 1.  */
-   
-#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN)     \
-do {                                                                    \
-  /* We must recognize output that we have already generated ourselves.  */ \
-  if (GET_CODE (X) == PLUS						\
-      && GET_CODE (XEXP (X, 0)) == PLUS					\
-      && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG			\
-      && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT			\
-      && GET_CODE (XEXP (X, 1)) == CONST_INT)				\
-    {									\
-      push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR,       \
-                   BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0,        \
-                   OPNUM, TYPE);                                        \
-      goto WIN;                                                         \
-    }									\
-  if (GET_CODE (X) == PLUS                                              \
-      && GET_CODE (XEXP (X, 0)) == REG                                  \
-      && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER                    \
-      && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE)                     \
-      && GET_CODE (XEXP (X, 1)) == CONST_INT)                           \
-    {                                                                   \
-      HOST_WIDE_INT val = INTVAL (XEXP (X, 1));                         \
-      HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;           \
-      HOST_WIDE_INT high                                                \
-        = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;       \
-                                                                        \
-      /* Check for 32-bit overflow.  */                                 \
-      if (high + low != val)                                            \
-        break;                                                          \
-                                                                        \
-      /* Reload the high part into a base reg; leave the low part       \
-         in the mem directly.  */                                       \
-                                                                        \
-      X = gen_rtx_PLUS (GET_MODE (X),                                   \
-                        gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0),        \
-                                      GEN_INT (high)),                  \
-                        GEN_INT (low));                                 \
-                                                                        \
-      push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR,       \
-                   BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0,        \
-                   OPNUM, TYPE);                                        \
-      goto WIN;                                                         \
-    }                                                                   \
-} while (0)
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-
-   On the RS/6000 this is true if the address is valid with a zero offset
-   but not with an offset of four (this means it cannot be used as an
-   address for DImode or DFmode) or is a pre-increment or decrement.  Since
-   we know it is valid, we just check for an address that is not valid with
-   an offset of four.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)		\
-{ if (GET_CODE (ADDR) == PLUS					\
-      && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0)	\
-      && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1),	\
-					 (TARGET_32BIT ? 4 : 8))) \
-    goto LABEL;							\
-  if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC)		\
-    goto LABEL;							\
-  if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC)		\
-    goto LABEL;							\
-  if (GET_CODE (ADDR) == LO_SUM)				\
-    goto LABEL;							\
-}
-
-/* The register number of the register used to address a table of
-   static data addresses in memory.  In some cases this register is
-   defined by a processor's "application binary interface" (ABI).
-   When this macro is defined, RTL is generated for this register
-   once, as with the stack pointer and frame pointer registers.  If
-   this macro is not defined, it is up to the machine-dependent files
-   to allocate such a register (if necessary).  */
-
-/* #define PIC_OFFSET_TABLE_REGNUM */
-
-/* Define this macro if the register defined by
-   `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls.  Do not define
-   this macro if `PPIC_OFFSET_TABLE_REGNUM' is not defined. */
-
-/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
-
-/* By generating position-independent code, when two different
-   programs (A and B) share a common library (libC.a), the text of
-   the library can be shared whether or not the library is linked at
-   the same address for both programs.  In some of these
-   environments, position-independent code requires not only the use
-   of different addressing modes, but also special code to enable the
-   use of these addressing modes.
-
-   The `FINALIZE_PIC' macro serves as a hook to emit these special
-   codes once the function is being compiled into assembly code, but
-   not before.  (It is not done before, because in the case of
-   compiling an inline function, it would lead to multiple PIC
-   prologues being included in functions which used inline functions
-   and were compiled to assembly language.)  */
-
-#define FINALIZE_PIC rs6000_finalize_pic ()
-
-/* A C expression that is nonzero if X is a legitimate immediate
-   operand on the target machine when generating position independent
-   code.  You can assume that X satisfies `CONSTANT_P', so you need
-   not check this.  You can also assume FLAG_PIC is true, so you need
-   not check it either.  You need not define this macro if all
-   constants (including `SYMBOL_REF') can be immediate operands when
-   generating position independent code.  */
-
-/* #define LEGITIMATE_PIC_OPERAND_P (X) */
-
-/* In rare cases, correct code generation requires extra machine
-   dependent processing between the second jump optimization pass and
-   delayed branch scheduling.  On those machines, define this macro
-   as a C statement to act on the code starting at INSN.
-
-   On the RS/6000, we use it to make sure the GOT_TOC register marker
-   that FINALIZE_PIC is supposed to remove actually got removed.  */
-
-#define MACHINE_DEPENDENT_REORG(INSN) rs6000_reorg (INSN)
-
-
-/* Define this if some processing needs to be done immediately before
-   emitting code for an insn.  */
-
-/* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE (TARGET_32BIT ? SImode : DImode)
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE 1
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.  */
-
-/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
-#define MAX_MOVE_MAX 8
-
-/* Nonzero if access to memory by bytes is no faster than for words.
-   Also non-zero if doing byte operations (specifically shifts) in registers
-   is undesirable.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.  */
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* Define if loading short immediate values into registers sign extends.  */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
-
-/* The RS/6000 uses the XCOFF format.  */
-
-#define XCOFF_DEBUGGING_INFO
-
-/* Define if the object format being used is COFF or a superset.  */
-#define OBJECT_FORMAT_COFF
-
-/* Define the magic numbers that we recognize as COFF.
-   AIX 4.3 adds U803XTOCMAGIC (0757) for 64-bit objects, but collect2.c
-   does not include files in the correct order to conditionally define
-   the symbolic name in this macro.  */
-#define MY_ISCOFF(magic) \
-  ((magic) == U802WRMAGIC || (magic) == U802ROMAGIC \
-   || (magic) == U802TOCMAGIC || (magic) == 0757)
-
-/* This is the only version of nm that collect2 can work with.  */
-#define REAL_NM_FILE_NAME "/usr/ucb/nm"
-
-/* We don't have GAS for the RS/6000 yet, so don't write out special
-   .stabs in cc1plus.  */
-
-#define FASCIST_ASSEMBLER
-
-/* AIX does not have any init/fini or ctor/dtor sections, so create
-   static constructors and destructors as normal functions.  */
-/* #define ASM_OUTPUT_CONSTRUCTOR(file, name) */
-/* #define ASM_OUTPUT_DESTRUCTOR(file, name) */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode (TARGET_32BIT ? SImode : DImode)
-
-/* Mode of a function address in a call instruction (for indexing purposes).
-   Doesn't matter on RS/6000.  */
-#define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode)
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.  */
-#define NO_FUNCTION_CSE
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
-   few bits.
-
-   The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
-   have been dropped from the PowerPC architecture.  */
-
-#define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
-
-/* Use atexit for static constructors/destructors, instead of defining
-   our own exit function.  */
-#define HAVE_ATEXIT
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.
-
-   On the RS/6000, if it is valid in the insn, it is free.  So this
-   always returns 0.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE)			\
-  case CONST_INT:						\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-  case CONST_DOUBLE:						\
-  case HIGH:							\
-    return 0;
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  */
-
-#define RTX_COSTS(X,CODE,OUTER_CODE)					\
-  case PLUS:								\
-    return ((GET_CODE (XEXP (X, 1)) == CONST_INT			\
-	     && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1))		\
-					   + 0x8000) >= 0x10000)	\
-	     && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0))			\
-	    ? COSTS_N_INSNS (2)						\
-	    : COSTS_N_INSNS (1));					\
-  case AND:								\
-  case IOR:								\
-  case XOR:								\
-    return ((GET_CODE (XEXP (X, 1)) == CONST_INT			\
-	     && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \
-	     && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0))			\
-	    ? COSTS_N_INSNS (2)						\
-	    : COSTS_N_INSNS (1));					\
-  case MULT:								\
-    switch (rs6000_cpu)							\
-      {									\
-      case PROCESSOR_RIOS1:						\
-        return (GET_CODE (XEXP (X, 1)) != CONST_INT			\
-		? COSTS_N_INSNS (5)					\
-		: INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
-		? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));		\
-      case PROCESSOR_RIOS2:						\
-      case PROCESSOR_MPCCORE:						\
-      case PROCESSOR_PPC604e:						\
-        return COSTS_N_INSNS (2);					\
-      case PROCESSOR_PPC601:						\
-        return COSTS_N_INSNS (5);					\
-      case PROCESSOR_PPC603:						\
-      case PROCESSOR_PPC750:						\
-        return (GET_CODE (XEXP (X, 1)) != CONST_INT			\
-		? COSTS_N_INSNS (5)					\
-		: INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
-		? COSTS_N_INSNS (2) : COSTS_N_INSNS (3));		\
-      case PROCESSOR_PPC403:						\
-      case PROCESSOR_PPC604:						\
-      case PROCESSOR_PPC620:						\
-        return COSTS_N_INSNS (4);					\
-      }									\
-  case DIV:								\
-  case MOD:								\
-    if (GET_CODE (XEXP (X, 1)) == CONST_INT				\
-	&& exact_log2 (INTVAL (XEXP (X, 1))) >= 0)			\
-      return COSTS_N_INSNS (2);						\
-    /* otherwise fall through to normal divide.  */			\
-  case UDIV:								\
-  case UMOD:								\
-    switch (rs6000_cpu)							\
-      {									\
-      case PROCESSOR_RIOS1:						\
-	return COSTS_N_INSNS (19);					\
-      case PROCESSOR_RIOS2:						\
-	return COSTS_N_INSNS (13);					\
-      case PROCESSOR_MPCCORE:						\
-	return COSTS_N_INSNS (6);					\
-      case PROCESSOR_PPC403:						\
-	return COSTS_N_INSNS (33);					\
-      case PROCESSOR_PPC601:						\
-	return COSTS_N_INSNS (36);					\
-      case PROCESSOR_PPC603:						\
-	return COSTS_N_INSNS (37);					\
-      case PROCESSOR_PPC604:						\
-      case PROCESSOR_PPC604e:						\
-      case PROCESSOR_PPC620:						\
-	return COSTS_N_INSNS (20);					\
-      case PROCESSOR_PPC750:						\
-        return COSTS_N_INSNS (19);					\
-      }									\
-  case FFS:								\
-    return COSTS_N_INSNS (4);						\
-  case MEM:								\
-    /* MEM should be slightly more expensive than (plus (reg) (const)) */ \
-    return 5;
-
-/* Compute the cost of an address.  This is meant to approximate the size
-   and/or execution delay of an insn using that address.  If the cost is
-   approximated by the RTL complexity, including CONST_COSTS above, as
-   is usually the case for CISC machines, this macro should not be defined.
-   For aggressively RISCy machines, only one insn format is allowed, so
-   this macro should be a constant.  The value of this macro only matters
-   for valid addresses.
-
-   For the RS/6000, everything is cost 0.  */
-
-#define ADDRESS_COST(RTX) 0
-
-/* Adjust the length of an INSN.  LENGTH is the currently-computed length and
-   should be adjusted to reflect any required changes.  This macro is used when
-   there is some systematic length adjustment required that would be difficult
-   to express in the length attribute.  */
-
-/* #define ADJUST_INSN_LENGTH(X,LENGTH) */
-
-/* Add any extra modes needed to represent the condition code.
-
-   For the RS/6000, we need separate modes when unsigned (logical) comparisons
-   are being done and we need a separate mode for floating-point.  We also
-   use a mode for the case when we are comparing the results of two
-   comparisons.  */
-
-#define EXTRA_CC_MODES CCUNSmode, CCFPmode, CCEQmode
-
-/* Define the names for the modes specified above.  */
-#define EXTRA_CC_NAMES "CCUNS", "CCFP", "CCEQ"
-
-/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
-   return the mode to be used for the comparison.  For floating-point, CCFPmode
-   should be used.  CCUNSmode should be used for unsigned comparisons.
-   CCEQmode should be used when we are doing an inequality comparison on
-   the result of a comparison. CCmode should be used in all other cases.  */
-
-#define SELECT_CC_MODE(OP,X,Y) \
-  (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode	\
-   : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
-   : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<'   \
-      ? CCEQmode : CCmode))
-
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  Note that we can't use "rtx" here
-   since it hasn't been defined!  */
-
-extern struct rtx_def *rs6000_compare_op0, *rs6000_compare_op1;
-extern int rs6000_compare_fp_p;
-
-/* Set to non-zero by "fix" operation to indicate that itrunc and
-   uitrunc must be defined.  */
-
-extern int rs6000_trunc_used;
-
-/* Function names to call to do floating point truncation.  */
-
-#define RS6000_ITRUNC "__itrunc"
-#define RS6000_UITRUNC "__uitrunc"
-
-/* Prefix and suffix to use to saving floating point */
-#ifndef SAVE_FP_PREFIX
-#define	SAVE_FP_PREFIX "._savef"
-#define SAVE_FP_SUFFIX ""
-#endif
-
-/* Prefix and suffix to use to restoring floating point */
-#ifndef RESTORE_FP_PREFIX
-#define	RESTORE_FP_PREFIX "._restf"
-#define RESTORE_FP_SUFFIX ""
-#endif
-
-/* Function name to call to do profiling.  */
-#define RS6000_MCOUNT ".__mcount"
-
-
-/* Control the assembler format that we output.  */
-
-/* A C string constant describing how to begin a comment in the target
-   assembler language.  The compiler assumes that the comment will end at
-   the end of the line.  */
-#define ASM_COMMENT_START " #"
-
-/* Output at beginning of assembler file.
-
-   Initialize the section names for the RS/6000 at this point.
-
-   Specify filename to assembler.
-
-   We want to go into the TOC section so at least one .toc will be emitted.
-   Also, in order to output proper .bs/.es pairs, we need at least one static
-   [RW] section emitted.
-
-   We then switch back to text to force the gcc2_compiled. label and the space
-   allocated after it (when profiling) into the text section.
-
-   Finally, declare mcount when profiling to make the assembler happy.  */
-
-#define ASM_FILE_START(FILE)					\
-{								\
-  rs6000_gen_section_name (&xcoff_bss_section_name,		\
-			   main_input_filename, ".bss_");	\
-  rs6000_gen_section_name (&xcoff_private_data_section_name,	\
-			   main_input_filename, ".rw_");	\
-  rs6000_gen_section_name (&xcoff_read_only_section_name,	\
-			   main_input_filename, ".ro_");	\
-								\
-  output_file_directive (FILE, main_input_filename);		\
-  if (TARGET_64BIT)						\
-    fputs ("\t.machine\t\"ppc64\"\n", FILE);			\
-  toc_section ();						\
-  if (write_symbols != NO_DEBUG)				\
-    private_data_section ();					\
-  text_section ();						\
-  if (profile_flag)						\
-    fprintf (FILE, "\t.extern %s\n", RS6000_MCOUNT);		\
-  rs6000_file_start (FILE, TARGET_CPU_DEFAULT);			\
-}
-
-/* Output at end of assembler file.
-
-   On the RS/6000, referencing data should automatically pull in text.  */
-
-#define ASM_FILE_END(FILE)					\
-{								\
-  text_section ();						\
-  fputs ("_section_.text:\n", FILE);				\
-  data_section ();						\
-  fputs ("\t.long _section_.text\n", FILE);			\
-}
-
-/* We define this to prevent the name mangler from putting dollar signs into
-   function names.  */
-
-#define NO_DOLLAR_IN_LABEL
-
-/* We define this to 0 so that gcc will never accept a dollar sign in a
-   variable name.  This is needed because the AIX assembler will not accept
-   dollar signs.  */
-
-#define DOLLARS_IN_IDENTIFIERS 0
-
-/* Implicit library calls should use memcpy, not bcopy, etc.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Define the extra sections we need.  We define three: one is the read-only
-   data section which is used for constants.  This is a csect whose name is
-   derived from the name of the input file.  The second is for initialized
-   global variables.  This is a csect whose name is that of the variable.
-   The third is the TOC.  */
-
-#define EXTRA_SECTIONS \
-   read_only_data, private_data, read_only_private_data, toc, bss
-
-/* Define the name of our readonly data section.  */
-
-#define READONLY_DATA_SECTION read_only_data_section
-
-
-/* Define the name of the section to use for the exception tables.
-   TODO: test and see if we can use read_only_data_section, if so,
-   remove this.  */
-
-#define EXCEPTION_SECTION data_section
-
-/* If we are referencing a function that is static or is known to be
-   in this file, make the SYMBOL_REF special.  We can use this to indicate
-   that we can branch to this function without emitting a no-op after the
-   call.  */
-
-#define ENCODE_SECTION_INFO(DECL)  \
-  if (TREE_CODE (DECL) == FUNCTION_DECL			\
-      && (TREE_ASM_WRITTEN (DECL) || ! TREE_PUBLIC (DECL))) \
-    SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
-
-/* Indicate that jump tables go in the text section.  */
-
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* Define the routines to implement these extra sections.  */
-
-#define EXTRA_SECTION_FUNCTIONS				\
-							\
-void							\
-read_only_data_section ()				\
-{							\
-  if (in_section != read_only_data)			\
-    {							\
-      fprintf (asm_out_file, ".csect %s[RO]\n",		\
-	       xcoff_read_only_section_name);		\
-      in_section = read_only_data;			\
-    }							\
-}							\
-							\
-void							\
-private_data_section ()					\
-{							\
-  if (in_section != private_data)			\
-    {							\
-      fprintf (asm_out_file, ".csect %s[RW]\n",		\
-	       xcoff_private_data_section_name);	\
-							\
-      in_section = private_data;			\
-    }							\
-}							\
-							\
-void							\
-read_only_private_data_section ()			\
-{							\
-  if (in_section != read_only_private_data)		\
-    {							\
-      fprintf (asm_out_file, ".csect %s[RO]\n",		\
-	       xcoff_private_data_section_name);	\
-      in_section = read_only_private_data;		\
-    }							\
-}							\
-							\
-void							\
-toc_section ()						\
-{							\
-  if (TARGET_MINIMAL_TOC)				\
-    {							\
-      /* toc_section is always called at least once from ASM_FILE_START, \
-	 so this is guaranteed to always be defined once and only once   \
-	 in each file.  */						 \
-      if (! toc_initialized)				\
-	{						\
-	  fputs (".toc\nLCTOC..0:\n", asm_out_file);	\
-	  fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file); \
-	  toc_initialized = 1;				\
-	}						\
-							\
-      if (in_section != toc)				\
-	fputs (".csect toc_table[RW]\n", asm_out_file); \
-    }							\
-  else							\
-    {							\
-      if (in_section != toc)				\
-        fputs (".toc\n", asm_out_file);			\
-    }							\
-  in_section = toc;					\
-}
-
-/* Flag to say the TOC is initialized */
-extern int toc_initialized;
-
-/* This macro produces the initial definition of a function name.
-   On the RS/6000, we need to place an extra '.' in the function name and
-   output the function descriptor.
-
-   The csect for the function will have already been created by the
-   `text_section' call previously done.  We do have to go back to that
-   csect, however.  */
-
-/* ??? What do the 16 and 044 in the .function line really mean?  */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL)		\
-{ if (TREE_PUBLIC (DECL))					\
-    {								\
-      fputs ("\t.globl .", FILE);				\
-      RS6000_OUTPUT_BASENAME (FILE, NAME);			\
-      putc ('\n', FILE);					\
-    }								\
-  else								\
-    {								\
-      fputs ("\t.lglobl .", FILE);				\
-      RS6000_OUTPUT_BASENAME (FILE, NAME);			\
-      putc ('\n', FILE);					\
-    }								\
-  fputs (".csect ", FILE);					\
-  RS6000_OUTPUT_BASENAME (FILE, NAME);				\
-  fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", FILE);		\
-  RS6000_OUTPUT_BASENAME (FILE, NAME);				\
-  fputs (":\n", FILE);						\
-  fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", FILE);	\
-  RS6000_OUTPUT_BASENAME (FILE, NAME);				\
-  fputs (", TOC[tc0], 0\n", FILE);				\
-  fputs (".csect .text[PR]\n.", FILE);				\
-  RS6000_OUTPUT_BASENAME (FILE, NAME);				\
-  fputs (":\n", FILE);						\
-  if (write_symbols == XCOFF_DEBUG)				\
-    xcoffout_declare_function (FILE, DECL, NAME);		\
-}
-
-/* Return non-zero if this entry is to be written into the constant pool
-   in a special way.  We do so if this is a SYMBOL_REF, LABEL_REF or a CONST
-   containing one of them.  If -mfp-in-toc (the default), we also do
-   this for floating-point constants.  We actually can only do this
-   if the FP formats of the target and host machines are the same, but
-   we can't check that since not every file that uses
-   GO_IF_LEGITIMATE_ADDRESS_P includes real.h.  */
-
-#define ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X)				\
-  (TARGET_TOC								\
-   && (GET_CODE (X) == SYMBOL_REF					\
-       || (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS	\
-	   && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF)		\
-       || GET_CODE (X) == LABEL_REF					\
-       || (! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)		\
-	   && GET_CODE (X) == CONST_DOUBLE				\
-	   && (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT		\
-	       || (TARGET_POWERPC64 && GET_MODE (X) == DImode)))))
-#if 0
-	   && BITS_PER_WORD == HOST_BITS_PER_INT)))
-#endif
-
-/* Select section for constant in constant pool.
-
-   On RS/6000, all constants are in the private read-only data area.
-   However, if this is being placed in the TOC it must be output as a
-   toc entry.  */
-
-#define SELECT_RTX_SECTION(MODE, X)		\
-{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X))	\
-    toc_section ();				\
-  else						\
-    read_only_private_data_section ();		\
-}
-
-/* Macro to output a special constant pool entry.  Go to WIN if we output
-   it.  Otherwise, it is written the usual way.
-
-   On the RS/6000, toc entries are handled this way.  */
-
-#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN)  \
-{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X))	\
-    {						\
-      output_toc (FILE, X, LABELNO);		\
-      goto WIN;					\
-    }						\
-}
-
-/* Select the section for an initialized data object.
-
-   On the RS/6000, we have a special section for all variables except those
-   that are static.  */
-
-#define SELECT_SECTION(EXP,RELOC)			\
-{							\
-  if ((TREE_CODE (EXP) == STRING_CST			\
-       && !flag_writable_strings)			\
-      || (TREE_CODE_CLASS (TREE_CODE (EXP)) == 'd'	\
-	  && TREE_READONLY (EXP) && ! TREE_THIS_VOLATILE (EXP) \
-	  && DECL_INITIAL (EXP)				\
-	  && (DECL_INITIAL (EXP) == error_mark_node	\
-	      || TREE_CONSTANT (DECL_INITIAL (EXP)))	\
-	  && ! (RELOC)))				\
-    {							\
-      if (TREE_PUBLIC (EXP))				\
-        read_only_data_section ();			\
-      else						\
-        read_only_private_data_section ();		\
-    }							\
-  else							\
-    {							\
-      if (TREE_PUBLIC (EXP))				\
-        data_section ();				\
-      else						\
-        private_data_section ();			\
-    }							\
-}
-
-/* This outputs NAME to FILE up to the first null or '['.  */
-
-#define RS6000_OUTPUT_BASENAME(FILE, NAME)	\
-  {						\
-    char *_p;					\
-						\
-    STRIP_NAME_ENCODING (_p, (NAME));		\
-    assemble_name ((FILE), _p);			\
-  }
-
-/* Remove any trailing [DS] or the like from the symbol name.  */
-
-#define STRIP_NAME_ENCODING(VAR,NAME)					\
-  do									\
-    {									\
-      char *_name = (NAME);						\
-      int _len;								\
-      if (_name[0] == '*')						\
-	_name++;							\
-      _len = strlen (_name);						\
-      if (_name[_len - 1] != ']')					\
-	(VAR) = _name;							\
-      else								\
-	{								\
-	  (VAR) = (char *) alloca (_len + 1);				\
-	  strcpy ((VAR), _name);					\
-	  (VAR)[_len - 4] = '\0';					\
-	}								\
-    }									\
-  while (0)
-
-/* Output something to declare an external symbol to the assembler.  Most
-   assemblers don't need this.
-
-   If we haven't already, add "[RW]" (or "[DS]" for a function) to the
-   name.  Normally we write this out along with the name.  In the few cases
-   where we can't, it gets stripped off.  */
-
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)	\
-{ rtx _symref = XEXP (DECL_RTL (DECL), 0);	\
-  if ((TREE_CODE (DECL) == VAR_DECL		\
-       || TREE_CODE (DECL) == FUNCTION_DECL)	\
-      && (NAME)[strlen (NAME) - 1] != ']')	\
-    {						\
-      char *_name = (char *) permalloc (strlen (XSTR (_symref, 0)) + 5); \
-      strcpy (_name, XSTR (_symref, 0));	\
-      strcat (_name, TREE_CODE (DECL) == FUNCTION_DECL ? "[DS]" : "[RW]"); \
-      XSTR (_symref, 0) = _name;		\
-    }						\
-  fputs ("\t.extern ", FILE);			\
-  assemble_name (FILE, XSTR (_symref, 0));	\
-  if (TREE_CODE (DECL) == FUNCTION_DECL)	\
-    {						\
-      fputs ("\n\t.extern .", FILE);		\
-      RS6000_OUTPUT_BASENAME (FILE, XSTR (_symref, 0));	\
-    }						\
-  putc ('\n', FILE);				\
-}
-
-/* Similar, but for libcall.  We only have to worry about the function name,
-   not that of the descriptor. */
-
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN)	\
-{ fputs ("\t.extern .", FILE);			\
-  assemble_name (FILE, XSTR (FUN, 0));		\
-  putc ('\n', FILE);				\
-}
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-
-/* Output before instructions.  */
-
-#define TEXT_SECTION_ASM_OP ".csect .text[PR]"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".csect .data[RW]"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-extern char rs6000_reg_names[][8];	/* register names (0 vs. %r0). */
-
-#define REGISTER_NAMES							\
-{									\
-  &rs6000_reg_names[ 0][0],	/* r0   */				\
-  &rs6000_reg_names[ 1][0],	/* r1	*/				\
-  &rs6000_reg_names[ 2][0],     /* r2	*/				\
-  &rs6000_reg_names[ 3][0],	/* r3	*/				\
-  &rs6000_reg_names[ 4][0],	/* r4	*/				\
-  &rs6000_reg_names[ 5][0],	/* r5	*/				\
-  &rs6000_reg_names[ 6][0],	/* r6	*/				\
-  &rs6000_reg_names[ 7][0],	/* r7	*/				\
-  &rs6000_reg_names[ 8][0],	/* r8	*/				\
-  &rs6000_reg_names[ 9][0],	/* r9	*/				\
-  &rs6000_reg_names[10][0],	/* r10  */				\
-  &rs6000_reg_names[11][0],	/* r11  */				\
-  &rs6000_reg_names[12][0],	/* r12  */				\
-  &rs6000_reg_names[13][0],	/* r13  */				\
-  &rs6000_reg_names[14][0],	/* r14  */				\
-  &rs6000_reg_names[15][0],	/* r15  */				\
-  &rs6000_reg_names[16][0],	/* r16  */				\
-  &rs6000_reg_names[17][0],	/* r17  */				\
-  &rs6000_reg_names[18][0],	/* r18  */				\
-  &rs6000_reg_names[19][0],	/* r19  */				\
-  &rs6000_reg_names[20][0],	/* r20  */				\
-  &rs6000_reg_names[21][0],	/* r21  */				\
-  &rs6000_reg_names[22][0],	/* r22  */				\
-  &rs6000_reg_names[23][0],	/* r23  */				\
-  &rs6000_reg_names[24][0],	/* r24  */				\
-  &rs6000_reg_names[25][0],	/* r25  */				\
-  &rs6000_reg_names[26][0],	/* r26  */				\
-  &rs6000_reg_names[27][0],	/* r27  */				\
-  &rs6000_reg_names[28][0],	/* r28  */				\
-  &rs6000_reg_names[29][0],	/* r29  */				\
-  &rs6000_reg_names[30][0],	/* r30  */				\
-  &rs6000_reg_names[31][0],	/* r31  */				\
-									\
-  &rs6000_reg_names[32][0],     /* fr0  */				\
-  &rs6000_reg_names[33][0],	/* fr1  */				\
-  &rs6000_reg_names[34][0],	/* fr2  */				\
-  &rs6000_reg_names[35][0],	/* fr3  */				\
-  &rs6000_reg_names[36][0],	/* fr4  */				\
-  &rs6000_reg_names[37][0],	/* fr5  */				\
-  &rs6000_reg_names[38][0],	/* fr6  */				\
-  &rs6000_reg_names[39][0],	/* fr7  */				\
-  &rs6000_reg_names[40][0],	/* fr8  */				\
-  &rs6000_reg_names[41][0],	/* fr9  */				\
-  &rs6000_reg_names[42][0],	/* fr10 */				\
-  &rs6000_reg_names[43][0],	/* fr11 */				\
-  &rs6000_reg_names[44][0],	/* fr12 */				\
-  &rs6000_reg_names[45][0],	/* fr13 */				\
-  &rs6000_reg_names[46][0],	/* fr14 */				\
-  &rs6000_reg_names[47][0],	/* fr15 */				\
-  &rs6000_reg_names[48][0],	/* fr16 */				\
-  &rs6000_reg_names[49][0],	/* fr17 */				\
-  &rs6000_reg_names[50][0],	/* fr18 */				\
-  &rs6000_reg_names[51][0],	/* fr19 */				\
-  &rs6000_reg_names[52][0],	/* fr20 */				\
-  &rs6000_reg_names[53][0],	/* fr21 */				\
-  &rs6000_reg_names[54][0],	/* fr22 */				\
-  &rs6000_reg_names[55][0],	/* fr23 */				\
-  &rs6000_reg_names[56][0],	/* fr24 */				\
-  &rs6000_reg_names[57][0],	/* fr25 */				\
-  &rs6000_reg_names[58][0],	/* fr26 */				\
-  &rs6000_reg_names[59][0],	/* fr27 */				\
-  &rs6000_reg_names[60][0],	/* fr28 */				\
-  &rs6000_reg_names[61][0],	/* fr29 */				\
-  &rs6000_reg_names[62][0],	/* fr30 */				\
-  &rs6000_reg_names[63][0],	/* fr31 */				\
-									\
-  &rs6000_reg_names[64][0],     /* mq   */				\
-  &rs6000_reg_names[65][0],	/* lr   */				\
-  &rs6000_reg_names[66][0],	/* ctr  */				\
-  &rs6000_reg_names[67][0],	/* ap   */				\
-									\
-  &rs6000_reg_names[68][0],	/* cr0  */				\
-  &rs6000_reg_names[69][0],	/* cr1  */				\
-  &rs6000_reg_names[70][0],	/* cr2  */				\
-  &rs6000_reg_names[71][0],	/* cr3  */				\
-  &rs6000_reg_names[72][0],	/* cr4  */				\
-  &rs6000_reg_names[73][0],	/* cr5  */				\
-  &rs6000_reg_names[74][0],	/* cr6  */				\
-  &rs6000_reg_names[75][0],	/* cr7  */				\
-									\
-  &rs6000_reg_names[76][0],	/* fpmem */				\
-}
-
-/* print-rtl can't handle the above REGISTER_NAMES, so define the
-   following for it.  Switch to use the alternate names since
-   they are more mnemonic.  */
-
-#define DEBUG_REGISTER_NAMES						\
-{									\
-     "r0", "r1",   "r2",  "r3",  "r4",  "r5",  "r6",  "r7",		\
-     "r8", "r9",  "r10", "r11", "r12", "r13", "r14", "r15",		\
-    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",		\
-    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",		\
-     "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",		\
-     "f8",  "f9", "f10", "f11", "f12", "f13", "f14", "f15",		\
-    "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",		\
-    "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",		\
-     "mq",  "lr", "ctr",  "ap",						\
-    "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",		\
-  "fpmem"								\
-}
-
-/* Table of additional register names to use in user input.  */
-
-#define ADDITIONAL_REGISTER_NAMES \
- {{"r0",    0}, {"r1",    1}, {"r2",    2}, {"r3",    3},	\
-  {"r4",    4}, {"r5",    5}, {"r6",    6}, {"r7",    7},	\
-  {"r8",    8}, {"r9",    9}, {"r10",  10}, {"r11",  11},	\
-  {"r12",  12}, {"r13",  13}, {"r14",  14}, {"r15",  15},	\
-  {"r16",  16}, {"r17",  17}, {"r18",  18}, {"r19",  19},	\
-  {"r20",  20}, {"r21",  21}, {"r22",  22}, {"r23",  23},	\
-  {"r24",  24}, {"r25",  25}, {"r26",  26}, {"r27",  27},	\
-  {"r28",  28}, {"r29",  29}, {"r30",  30}, {"r31",  31},	\
-  {"fr0",  32}, {"fr1",  33}, {"fr2",  34}, {"fr3",  35},	\
-  {"fr4",  36}, {"fr5",  37}, {"fr6",  38}, {"fr7",  39},	\
-  {"fr8",  40}, {"fr9",  41}, {"fr10", 42}, {"fr11", 43},	\
-  {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47},	\
-  {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51},	\
-  {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55},	\
-  {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59},	\
-  {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63},	\
-  /* no additional names for: mq, lr, ctr, ap */		\
-  {"cr0",  68}, {"cr1",  69}, {"cr2",  70}, {"cr3",  71},	\
-  {"cr4",  72}, {"cr5",  73}, {"cr6",  74}, {"cr7",  75},	\
-  {"cc",   68}, {"sp",    1}, {"toc",   2} }
-
-/* How to renumber registers for dbx and gdb.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Text to write out after a CALL that may be replaced by glue code by
-   the loader.  This depends on the AIX version.  */
-#define RS6000_CALL_GLUE "cror 31,31,31"
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { RS6000_OUTPUT_BASENAME (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs ("\t.globl ", FILE);	\
-       RS6000_OUTPUT_BASENAME (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-
-#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
-  fputs (NAME, FILE)
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s..%d:\n", PREFIX, NUM)
-
-/* This is how to output an internal label prefix.  rs6000.c uses this
-   when generating traceback tables.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL_PREFIX(FILE,PREFIX)	\
-  fprintf (FILE, "%s..", PREFIX)
-
-/* This is how to output a label for a jump table.  Arguments are the same as
-   for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
-   passed. */
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN)	\
-{ ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s..%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t[2];							\
-	REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);			\
-	fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n",		\
-		t[0] & 0xffffffff, t[1] & 0xffffffff);			\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str);			\
-	fprintf (FILE, "\t.double 0d%s\n", str);			\
-      }									\
-  }
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t;								\
-	REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
-	fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff);		\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);			\
-	fprintf (FILE, "\t.float 0d%s\n", str);				\
-      }									\
-  }
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE)				\
-do {									\
-  if (TARGET_32BIT)							\
-    {									\
-      assemble_integer (operand_subword ((VALUE), 0, 0, DImode),	\
-                        UNITS_PER_WORD, 1);				\
-      assemble_integer (operand_subword ((VALUE), 1, 0, DImode),	\
-                        UNITS_PER_WORD, 1);				\
-    }									\
-  else									\
-    {									\
-      fputs ("\t.llong ", FILE);					\
-      output_addr_const (FILE, (VALUE));				\
-      putc ('\n', FILE);						\
-    }									\
-} while (0)
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fputs ("\t.long ", FILE),			\
-  output_addr_const (FILE, (VALUE)),		\
-  putc ('\n', FILE))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fputs ("\t.short ", FILE),			\
-  output_addr_const (FILE, (VALUE)),		\
-  putc ('\n', FILE))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fputs ("\t.byte ", FILE),			\
-  output_addr_const (FILE, (VALUE)),		\
-  putc ('\n', FILE))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* This is how to output an assembler line to define N characters starting
-   at P to FILE.  */
-
-#define ASM_OUTPUT_ASCII(FILE, P, N)  output_ascii ((FILE), (P), (N))
-
-/* This is how to output code to push a register on the stack.
-   It need not be very fast code.
-
-   On the rs6000, we must keep the backchain up to date.  In order
-   to simplify things, always allocate 16 bytes for a push (System V
-   wants to keep stack aligned to a 16 byte boundary).  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)					\
-do {									\
-  extern char *reg_names[];						\
-  asm_fprintf (FILE, "\t{stu|stwu} %s,-16(%s)\n\t{st|stw} %s,8(%s)\n",	\
-	       reg_names[1], reg_names[1], reg_names[REGNO],		\
-	       reg_names[1]);						\
-} while (0)
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)					\
-do {									\
-  extern char *reg_names[];						\
-  asm_fprintf (FILE, "\t{l|lwz} %s,8(%s)\n\t{ai|addic} %s,%s,16\n",	\
-	       reg_names[REGNO], reg_names[1], reg_names[1],		\
-	       reg_names[1]);						\
-} while (0)
-
-/* This is how to output an element of a case-vector that is absolute.
-   (RS/6000 does not use such vectors, but we must define this macro
-   anyway.)   */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)		\
-  do { char buf[100];					\
-       fputs (TARGET_32BIT ? "\t.long " : "\t.llong ", FILE);	\
-       ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE);	\
-       assemble_name (FILE, buf);			\
-       putc ('\n', FILE);				\
-     } while (0)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
-  do { char buf[100];					\
-       fputs (TARGET_32BIT ? "\t.long " : "\t.llong ", FILE);	\
-       ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE);	\
-       assemble_name (FILE, buf);			\
-       putc ('-', FILE);				\
-       ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL);	\
-       assemble_name (FILE, buf);			\
-       putc ('\n', FILE);				\
-     } while (0)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", (LOG))
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %d\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGNMENT)	\
-  do { fputs (".comm ", (FILE));			\
-       RS6000_OUTPUT_BASENAME ((FILE), (NAME));		\
-       if ( (SIZE) > 4)					\
-         fprintf ((FILE), ",%d,3\n", (SIZE));		\
-       else						\
-	 fprintf( (FILE), ",%d\n", (SIZE));		\
-  } while (0)
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED)	\
-  do { fputs (".lcomm ", (FILE));			\
-       RS6000_OUTPUT_BASENAME ((FILE), (NAME));		\
-       fprintf ((FILE), ",%d,%s\n", (SIZE), xcoff_bss_section_name); \
-     } while (0)
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand (FILE, X, CODE)
-
-/* Define which CODE values are valid.  */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)  \
-  ((CODE) == '.' || (CODE) == '*' || (CODE) == '$')
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
-
-/* Define the codes that are matched by predicates in rs6000.c.  */
-
-#define PREDICATE_CODES						\
-  {"short_cint_operand", {CONST_INT, CONSTANT_P_RTX}},		\
-  {"u_short_cint_operand", {CONST_INT, CONSTANT_P_RTX}},	\
-  {"non_short_cint_operand", {CONST_INT}},			\
-  {"gpc_reg_operand", {SUBREG, REG}},				\
-  {"cc_reg_operand", {SUBREG, REG}},				\
-  {"cc_reg_not_cr0_operand", {SUBREG, REG}},			\
-  {"reg_or_short_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
-  {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}},	\
-  {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
-  {"reg_or_cint_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
-  {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}},		\
-  {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}},		\
-  {"easy_fp_constant", {CONST_DOUBLE}},				\
-  {"reg_or_mem_operand", {SUBREG, MEM, REG}},			\
-  {"lwa_operand", {SUBREG, MEM, REG}},				\
-  {"volatile_mem_operand", {MEM}},				\
-  {"offsettable_addr_operand", {REG, SUBREG, PLUS}},		\
-  {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}},	\
-  {"add_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}},	\
-  {"non_add_cint_operand", {CONST_INT}},			\
-  {"and_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}},	\
-  {"and64_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX,	\
-		     CONST_DOUBLE}},				\
-  {"logical_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
-  {"non_logical_cint_operand", {CONST_INT}},			\
-  {"mask_operand", {CONST_INT}},				\
-  {"mask64_operand", {CONST_INT, CONST_DOUBLE}},		\
-  {"count_register_operand", {REG}},				\
-  {"fpmem_operand", {REG}},					\
-  {"call_operand", {SYMBOL_REF, REG}},				\
-  {"current_file_function_operand", {SYMBOL_REF}},		\
-  {"input_operand", {SUBREG, MEM, REG, CONST_INT, CONSTANT_P_RTX, \
-		     CONST_DOUBLE, SYMBOL_REF}}, 		\
-  {"load_multiple_operation", {PARALLEL}},			\
-  {"store_multiple_operation", {PARALLEL}},			\
-  {"branch_comparison_operator", {EQ, NE, LE, LT, GE,		\
-				  GT, LEU, LTU, GEU, GTU}},	\
-  {"scc_comparison_operator", {EQ, NE, LE, LT, GE,		\
-			       GT, LEU, LTU, GEU, GTU}},	\
-  {"trap_comparison_operator", {EQ, NE, LE, LT, GE,		\
-				GT, LEU, LTU, GEU, GTU}},
-
-/* uncomment for disabling the corresponding default options */
-/* #define  MACHINE_no_sched_interblock */
-/* #define  MACHINE_no_sched_speculative */
-/* #define  MACHINE_no_sched_speculative_load */
-
-/* indicate that issue rate is defined for this machine
-   (no need to use the default) */
-#define ISSUE_RATE get_issue_rate ()
-
-/* General flags.  */
-extern int flag_pic;
-extern int optimize;
-extern int flag_expensive_optimizations;
-extern int frame_pointer_needed;
-
-/* Declare functions in rs6000.c */
-extern void output_options ();
-extern void rs6000_override_options ();
-extern void rs6000_file_start ();
-extern struct rtx_def *rs6000_float_const ();
-extern struct rtx_def *rs6000_got_register ();
-extern int direct_return ();
-extern int get_issue_rate ();
-extern int any_operand ();
-extern int short_cint_operand ();
-extern int u_short_cint_operand ();
-extern int non_short_cint_operand ();
-extern int gpc_reg_operand ();
-extern int cc_reg_operand ();
-extern int cc_reg_not_cr0_operand ();
-extern int reg_or_short_operand ();
-extern int reg_or_neg_short_operand ();
-extern int reg_or_u_short_operand ();
-extern int reg_or_cint_operand ();
-extern int got_operand ();
-extern int got_no_const_operand ();
-extern int num_insns_constant ();
-extern int easy_fp_constant ();
-extern int volatile_mem_operand ();
-extern int offsettable_addr_operand ();
-extern int mem_or_easy_const_operand ();
-extern int add_operand ();
-extern int non_add_cint_operand ();
-extern int non_logical_cint_operand ();
-extern int logical_operand ();
-extern int mask_constant ();
-extern int mask_operand ();
-extern int mask64_operand ();
-extern int and64_operand ();
-extern int and_operand ();
-extern int count_register_operand ();
-extern int fpmem_operand ();
-extern int reg_or_mem_operand ();
-extern int lwa_operand ();
-extern int call_operand ();
-extern int current_file_function_operand ();
-extern int input_operand ();
-extern int small_data_operand ();
-extern void init_cumulative_args ();
-extern void function_arg_advance ();
-extern int function_arg_boundary ();
-extern struct rtx_def *function_arg ();
-extern int function_arg_partial_nregs ();
-extern int function_arg_pass_by_reference ();
-extern void setup_incoming_varargs ();
-extern struct rtx_def *expand_builtin_saveregs ();
-extern struct rtx_def *rs6000_stack_temp ();
-extern int expand_block_move ();
-extern int load_multiple_operation ();
-extern int store_multiple_operation ();
-extern int branch_comparison_operator ();
-extern int scc_comparison_operator ();
-extern int trap_comparison_operator ();
-extern int includes_lshift_p ();
-extern int includes_rshift_p ();
-extern int registers_ok_for_quad_peep ();
-extern int addrs_ok_for_quad_peep ();
-extern enum reg_class secondary_reload_class ();
-extern int ccr_bit ();
-extern void rs6000_finalize_pic ();
-extern void rs6000_reorg ();
-extern void rs6000_save_machine_status ();
-extern void rs6000_restore_machine_status ();
-extern void rs6000_init_expanders ();
-extern void print_operand ();
-extern void print_operand_address ();
-extern int first_reg_to_save ();
-extern int first_fp_reg_to_save ();
-extern int rs6000_makes_calls ();
-extern rs6000_stack_t *rs6000_stack_info ();
-extern void output_prolog ();
-extern void output_epilog ();
-extern void output_mi_thunk ();
-extern void output_toc ();
-extern void output_ascii ();
-extern void rs6000_gen_section_name ();
-extern void output_function_profiler ();
-extern int rs6000_adjust_cost ();
-extern int rs6000_adjust_priority ();
-extern void rs6000_trampoline_template ();
-extern int rs6000_trampoline_size ();
-extern void rs6000_initialize_trampoline ();
-extern void rs6000_output_load_toc_table ();
-extern int rs6000_comp_type_attributes ();
-extern int rs6000_valid_decl_attribute_p ();
-extern int rs6000_valid_type_attribute_p ();
-extern void rs6000_set_default_type_attributes ();
-extern struct rtx_def *rs6000_dll_import_ref ();
-extern struct rtx_def *rs6000_longcall_ref ();
-extern int function_arg_padding ();
-extern void toc_section ();
-extern void private_data_section ();
-extern void rs6000_fatal_bad_address ();
-/* CYGNUS LOCAL -- vmakarov/prolog-epilog instruction scheduling. */
-extern void rs6000_expand_prologue ();
-extern void rs6000_expand_epilogue ();
-/* END CYGNUS LOCAL */
-
-/* See nonlocal_goto_receiver for when this must be set.  */
-
-#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_TOC && TARGET_MINIMAL_TOC)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
deleted file mode 100755
index 9891796..0000000
--- a/gcc/config/rs6000/rs6000.md
+++ /dev/null
@@ -1,13242 +0,0 @@
-;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
-;; Copyright (C) 1990, 91-98, 1999 Free Software Foundation, Inc.
-;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; Define an insn type attribute.  This is used in function unit delay
-;; computations.
-(define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
-  (const_string "integer"))
-
-;; Length (in bytes).
-(define_attr "length" ""
-  (if_then_else (eq_attr "type" "branch")
-		(if_then_else (and (ge (minus (pc) (match_dup 0))
-				       (const_int -32768))
-				   (lt (minus (pc) (match_dup 0))
-				       (const_int 32767)))
-			      (const_int 8)
-			      (const_int 12))
-		(const_int 4)))
-
-;; Processor type -- this attribute must exactly match the processor_type
-;; enumeration in rs6000.h.
-
-(define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"
-  (const (symbol_ref "rs6000_cpu_attr")))
-
-; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
-;			TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
-
-; Load/Store Unit -- pure PowerPC only
-; (POWER and 601 use Integer Unit)
-(define_function_unit "lsu" 1 0
-  (and (eq_attr "type" "load")
-       (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750"))
-  2 1)
-
-(define_function_unit "lsu" 1 0
-  (and (eq_attr "type" "store,fpstore")
-       (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750"))
-  1 1)
-
-(define_function_unit "lsu" 1 0
-  (and (eq_attr "type" "fpload")
-       (eq_attr "cpu" "mpccore,ppc603,ppc750"))
-  2 1)
-
-(define_function_unit "lsu" 1 0
-  (and (eq_attr "type" "fpload")
-       (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
-  3 1)
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "load")
-       (eq_attr "cpu" "rios1,ppc403,ppc601"))
-  2 1)
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "store,fpstore")
-       (eq_attr "cpu" "rios1,ppc403,ppc601"))
-  1 1)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "fpstore")
-       (eq_attr "cpu" "rios1,ppc601"))
-  0 1)
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "fpload")
-       (eq_attr "cpu" "rios1"))
-  2 1)
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "fpload")
-       (eq_attr "cpu" "ppc601"))
-  3 1)
-
-(define_function_unit "iu2" 2 0
-  (and (eq_attr "type" "load,fpload")
-       (eq_attr "cpu" "rios2"))
-  2 1)
-
-(define_function_unit "iu2" 2 0
-  (and (eq_attr "type" "store,fpstore")
-       (eq_attr "cpu" "rios2"))
-  1 1)
-
-; Integer Unit (RIOS1, PPC601, PPC603)
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "integer")
-       (eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603"))
-  1 1)
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "ppc403"))
-  4 4)
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "rios1,ppc601,ppc603"))
-  5 5)
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "rios1"))
-  19 19)
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "ppc403"))
-  33 33)
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "ppc601"))
-  36 36)
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "ppc603"))
-  37 36)
-
-; RIOS2 has two integer units: a primary one which can perform all
-; operations and a secondary one which is fed in lock step with the first
-; and can perform "simple" integer operations.  
-; To catch this we define a 'dummy' imuldiv-unit that is also needed
-; for the complex insns. 
-(define_function_unit "iu2" 2 0
-  (and (eq_attr "type" "integer")
-       (eq_attr "cpu" "rios2"))
-  1 1)
-
-(define_function_unit "iu2" 2 0
-  (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "rios2"))
-  2 2)
-
-(define_function_unit "iu2" 2 0
-  (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "rios2"))
-  13 13)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "rios2"))
-  2 2)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "rios2"))
-  13 13)
-
-; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
-; Divide latency varies greatly from 2-11, use 6 as average
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "mpccore"))
-  2 1)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "mpccore"))
-  6 6)
-
-; PPC604{,e} has two units that perform integer operations
-; and one unit for divide/multiply operations (and move
-; from/to spr).
-(define_function_unit "iu2" 2 0
-  (and (eq_attr "type" "integer")
-       (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
-  1 1)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "ppc604,ppc620"))
-  4 2)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "ppc604e"))
-  2 1)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
-  20 19)
-
-; PPC750 has two integer units: a primary one which can perform all
-; operations and a secondary one which is fed in lock step with the first
-; and can perform "simple" integer operations.  
-; To catch this we define a 'dummy' imuldiv-unit that is also needed
-; for the complex insns. 
-(define_function_unit "iu2" 2 0
-  (and (eq_attr "type" "integer")
-       (eq_attr "cpu" "ppc750"))
-  1 1)
-
-(define_function_unit "iu2" 2 0
-  (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "ppc750"))
-  4 2)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "imul")
-       (eq_attr "cpu" "ppc750"))
-  4 2)
-
-(define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "idiv")
-       (eq_attr "cpu" "ppc750"))
-  19 19)
-
-; compare is done on integer unit, but feeds insns which
-; execute on the branch unit.
-(define_function_unit "iu" 1 0   
-  (and (eq_attr "type" "compare")
-       (eq_attr "cpu" "rios1"))
-  4 1)
-
-(define_function_unit "iu" 1 0   
-  (and (eq_attr "type" "delayed_compare")
-       (eq_attr "cpu" "rios1"))
-  5 1)
-
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "compare,delayed_compare")
-       (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
-  3 1)
-
-(define_function_unit "iu2" 2 0   
-  (and (eq_attr "type" "compare,delayed_compare")
-       (eq_attr "cpu" "rios2"))
-  3 1)
-
-(define_function_unit "iu2" 2 0
-  (and (eq_attr "type" "compare,delayed_compare")
-       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc750"))
-  1 1)
-
-; fp compare uses fp unit
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "fpcompare")
-       (eq_attr "cpu" "rios1"))
-  9 1)
-
-; rios1 and rios2 have different fpcompare delays
-(define_function_unit "fpu2" 2 0
-  (and (eq_attr "type" "fpcompare")
-       (eq_attr "cpu" "rios2"))
-  5 1)
-
-; on ppc601 and ppc603, fpcompare takes also 2 cycles from
-; the integer unit
-; here we do not define delays, just occupy the unit. The dependencies
-; will be assigned by the fpcompare definition in the fpu.
-(define_function_unit "iu" 1 0
-  (and (eq_attr "type" "fpcompare")
-       (eq_attr "cpu" "ppc601,ppc603"))
-  0 2)
-
-; fp compare uses fp unit
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "fpcompare")
-       (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
-  5 1)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "fpcompare")
-       (eq_attr "cpu" "mpccore"))
-  1 1)
-
-(define_function_unit "bpu" 1 0
-  (and (eq_attr "type" "mtjmpr")
-       (eq_attr "cpu" "rios1,rios2"))
-  5 1)
-
-(define_function_unit "bpu" 1 0
-  (and (eq_attr "type" "mtjmpr")
-       (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
-  4 1)
-
-; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
-(define_function_unit "bpu" 1 0
-  (eq_attr "type" "jmpreg")
-  1 1)
-
-(define_function_unit "bpu" 1 0
-  (eq_attr "type" "branch")
-  1 1)
-
-; Floating Point Unit
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "fp,dmul")
-       (eq_attr "cpu" "rios1"))
-  2 1)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "fp")
-       (eq_attr "cpu" "mpccore"))
-  4 4)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "fp")
-       (eq_attr "cpu" "ppc601"))
-  4 1)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "fp")
-       (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750"))
-  3 1)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "dmul")
-       (eq_attr "cpu" "mpccore"))
-  5 5)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "dmul")
-       (eq_attr "cpu" "ppc601"))
-  5 2)
-
-; is this true?
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "dmul")
-       (eq_attr "cpu" "ppc603,ppc750"))
-  4 2)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "dmul")
-       (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
-  3 1)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "sdiv,ddiv")
-       (eq_attr "cpu" "rios1"))
-  19 19)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "sdiv")
-       (eq_attr "cpu" "ppc601"))
-  17 17)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "sdiv")
-       (eq_attr "cpu" "mpccore"))
-  10 10)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "sdiv")
-       (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620"))
-  18 18)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "ddiv")
-       (eq_attr "cpu" "mpccore"))
-  17 17)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "ddiv")
-       (eq_attr "cpu" "ppc601,ppc604,ppc604e,ppc620,ppc750"))
-  31 31)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "ddiv")
-       (eq_attr "cpu" "ppc603"))
-  33 33)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "ssqrt")
-       (eq_attr "cpu" "ppc620"))
-  31 31)
-
-(define_function_unit "fpu" 1 0
-  (and (eq_attr "type" "dsqrt")
-       (eq_attr "cpu" "ppc620"))
-  31 31)
-
-; RIOS2 has two symmetric FPUs.
-(define_function_unit "fpu2" 2 0
-  (and (eq_attr "type" "fp")
-       (eq_attr "cpu" "rios2"))
-  2 1)
-
-(define_function_unit "fpu2" 2 0
-  (and (eq_attr "type" "dmul")
-       (eq_attr "cpu" "rios2"))
-  2 1)
-
-(define_function_unit "fpu2" 2 0
-  (and (eq_attr "type" "sdiv,ddiv")
-       (eq_attr "cpu" "rios2"))
-  17 17)
-
-(define_function_unit "fpu2" 2 0
-  (and (eq_attr "type" "ssqrt,dsqrt")
-       (eq_attr "cpu" "rios2"))
-  26 26)
-
-
-;; Start with fixed-point load and store insns.  Here we put only the more
-;; complex forms.  Basic data transfer is done later.
-
-(define_expand "zero_extendqidi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
-  "TARGET_POWERPC64"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
-  "TARGET_POWERPC64"
-  "@
-   lbz%U1%X1 %0,%1
-   rldicl %0,%1,0,56"
-  [(set_attr "type" "load,*")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   rldicl. %2,%1,0,56
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r"))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2)
-	(zero_extend:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64"
-  "@
-   rldicl. %0,%1,0,56
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:DI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "extendqidi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64"
-  "extsb %0,%1")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   extsb. %2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2)
-	(sign_extend:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64"
-  "@
-   extsb. %0,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(sign_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(sign_extend:DI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "zero_extendhidi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
-  "TARGET_POWERPC64"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
-  "TARGET_POWERPC64"
-  "@
-   lhz%U1%X1 %0,%1
-   rldicl %0,%1,0,48"
-  [(set_attr "type" "load,*")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   rldicl. %2,%1,0,48
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2)
-	(zero_extend:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64"
-  "@
-   rldicl. %0,%1,0,48
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:DI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "extendhidi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
-  "TARGET_POWERPC64"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
-  "TARGET_POWERPC64"
-  "@
-   lha%U1%X1 %0,%1
-   extsh %0,%1"
-  [(set_attr "type" "load,*")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   extsh. %2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2)
-	(sign_extend:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64"
-  "@
-   extsh. %0,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(sign_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(sign_extend:DI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "zero_extendsidi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
-  "TARGET_POWERPC64"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
-  "TARGET_POWERPC64"
-  "@
-   lwz%U1%X1 %0,%1
-   rldicl %0,%1,0,32"
-  [(set_attr "type" "load,*")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   rldicl. %2,%1,0,32
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2)
-	(zero_extend:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64"
-  "@
-   rldicl. %0,%1,0,32
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:DI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "extendsidi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
-  "TARGET_POWERPC64"
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
-  "TARGET_POWERPC64"
-  "@
-   lwa%U1%X1 %0,%1
-   extsw %0,%1"
-  [(set_attr "type" "load,*")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   extsw. %2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2)
-	(sign_extend:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64"
-  "@
-   extsw. %0,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(sign_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(sign_extend:DI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
-  ""
-  "@
-   lbz%U1%X1 %0,%1
-   {rlinm|rlwinm} %0,%1,0,0xff"
-  [(set_attr "type" "load,*")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 "=r,r"))]
-  ""
-  "@
-   {andil.|andi.} %2,%1,0xff
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 2)
-	(zero_extend:SI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI (match_dup 1)))]
-  ""
-  "@
-   {andil.|andi.} %0,%1,0xff
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(zero_extend:SI (match_dup 1)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:SI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "extendqisi2"
-  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
-   (use (match_operand:QI 1 "gpc_reg_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_POWERPC)
-    emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
-  else if (TARGET_POWER)
-    emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
-  else
-    emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
-  DONE;
-}")
-
-(define_insn "extendqisi2_ppc"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC"
-  "extsb %0,%1")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 "=r,r"))]
-  "TARGET_POWERPC"
-  "@
-   extsb. %2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 ""))]
-  "TARGET_POWERPC && reload_completed"
-  [(set (match_dup 2)
-	(sign_extend:SI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:SI (match_dup 1)))]
-  "TARGET_POWERPC"
-  "@
-   extsb. %0,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(sign_extend:SI (match_dup 1)))]
-  "TARGET_POWERPC && reload_completed"
-  [(set (match_dup 0)
-	(sign_extend:SI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "extendqisi2_power"
-  [(parallel [(set (match_dup 2)
-		   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
-			      (const_int 24)))
-	      (clobber (scratch:SI))])
-   (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
-		   (ashiftrt:SI (match_dup 2)
-				(const_int 24)))
-	      (clobber (scratch:SI))])]
-  "TARGET_POWER"
-  "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "extendqisi2_no_power"
-  [(set (match_dup 2)
-	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
-		   (const_int 24)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashiftrt:SI (match_dup 2)
-		     (const_int 24)))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "
-{ operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "zero_extendqihi2"
-  [(set (match_operand:HI 0 "gpc_reg_operand" "")
-	(zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
-  ""
-  "@
-   lbz%U1%X1 %0,%1
-   {rlinm|rlwinm} %0,%1,0,0xff"
-  [(set_attr "type" "load,*")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:HI 2 "=r,r"))]
-  ""
-  "@
-   {andil.|andi.} %2,%1,0xff
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:HI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 2)
-	(zero_extend:SI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "
-{
-  rtx reg;
-  int offset;
-  if (GET_CODE (operands[2]) == REG)
-    {
-      reg = operands[2];
-      offset = 0;
-    }
-  else if (GET_CODE (operands[2]) == SUBREG)
-    {
-      reg = SUBREG_REG (operands[2]);
-      offset = SUBREG_WORD (operands[2]);
-    }
-  else
-    abort ();
-
-  operands[3] = gen_rtx_SUBREG (SImode, reg, offset);
-}")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:HI (match_dup 1)))]
-  ""
-  "@
-   {andil.|andi.} %0,%1,0xff
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:HI 0 "gpc_reg_operand" "")
-	(zero_extend:HI (match_dup 1)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:HI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "
-{
-  rtx reg;
-  int offset;
-  if (GET_CODE (operands[0]) == REG)
-    {
-      reg = operands[2];
-      offset = 0;
-    }
-  else if (GET_CODE (operands[2]) == SUBREG)
-    {
-      reg = SUBREG_REG (operands[2]);
-      offset = SUBREG_WORD (operands[2]);
-    }
-  else
-    abort ();
-
-  operands[3] = gen_rtx_SUBREG (SImode, reg, offset);
-}")
-
-(define_expand "extendqihi2"
-  [(use (match_operand:HI 0 "gpc_reg_operand" ""))
-   (use (match_operand:QI 1 "gpc_reg_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_POWERPC)
-    emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
-  else if (TARGET_POWER)
-    emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
-  else
-    emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
-  DONE;
-}")
-
-(define_insn "extendqihi2_ppc"
-  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
-	(sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC"
-  "extsb %0,%1")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:HI 2 "=r,r"))]
-  "TARGET_POWERPC"
-  "@
-   extsb. %2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:HI 2 ""))]
-  "TARGET_POWERPC && reload_completed"
-  [(set (match_dup 2)
-	(zero_extend:HI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "
-{
-  rtx reg;
-  int offset;
-  if (GET_CODE (operands[2]) == REG)
-    {
-      reg = operands[2];
-      offset = 0;
-    }
-  else if (GET_CODE (operands[2]) == SUBREG)
-    {
-      reg = SUBREG_REG (operands[2]);
-      offset = SUBREG_WORD (operands[2]);
-    }
-  else
-    abort ();
-
-  operands[3] = gen_rtx_SUBREG (SImode, reg, offset);
-}")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:HI (match_dup 1)))]
-  "TARGET_POWERPC"
-  "@
-   extsb. %0,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:HI 0 "gpc_reg_operand" "")
-	(sign_extend:HI (match_dup 1)))]
-  "TARGET_POWERPC && reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:HI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "
-{
-  rtx reg;
-  int offset;
-  if (GET_CODE (operands[0]) == REG)
-    {
-      reg = operands[0];
-      offset = 0;
-    }
-  else if (GET_CODE (operands[0]) == SUBREG)
-    {
-      reg = SUBREG_REG (operands[0]);
-      offset = SUBREG_WORD (operands[0]);
-    }
-  else
-    abort ();
-
-  operands[3] = gen_rtx_SUBREG (SImode, reg, offset);
-}")
-
-(define_expand "extendqihi2_power"
-  [(parallel [(set (match_dup 2)
-		   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
-			      (const_int 24)))
-	      (clobber (scratch:SI))])
-   (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
-		   (ashiftrt:SI (match_dup 2)
-				(const_int 24)))
-	      (clobber (scratch:SI))])]
-  "TARGET_POWER"
-  "
-{ operands[0] = gen_lowpart (SImode, operands[0]);
-  operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "extendqihi2_no_power"
-  [(set (match_dup 2)
-	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
-		   (const_int 24)))
-   (set (match_operand:HI 0 "gpc_reg_operand" "")
-	(ashiftrt:SI (match_dup 2)
-		     (const_int 24)))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "
-{ operands[0] = gen_lowpart (SImode, operands[0]);
-  operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode); }")
-
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
-  ""
-  "@
-   lhz%U1%X1 %0,%1
-   {rlinm|rlwinm} %0,%1,0,0xffff"
-  [(set_attr "type" "load,*")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 "=r,r"))]
-  ""
-  "@
-   {andil.|andi.} %2,%1,0xffff
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 2)
-	(zero_extend:SI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI (match_dup 1)))]
-  ""
-  "@
-   {andil.|andi.} %0,%1,0xffff
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(zero_extend:SI (match_dup 1)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:SI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "extendhisi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
-  ""
-  "@
-   lha%U1%X1 %0,%1
-   {exts|extsh} %0,%1"
-  [(set_attr "type" "load,*")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 "=r,r"))]
-  ""
-  "@
-   {exts.|extsh.} %2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "=x,?y")
-	(compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:SI (match_dup 1)))]
-  ""
-  "@
-   {exts.|extsh.} %0,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_operand" "")
-	(compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(sign_extend:SI (match_dup 1)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(sign_extend:SI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-
-;; Fixed-point arithmetic insns.
-
-;; Discourage ai/addic because of carry but provide it in an alternative
-;; allowing register zero as source.
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		 (match_operand:SI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT && !add_operand (operands[2], SImode))
-    {
-      rtx tmp = ((reload_in_progress || reload_completed
-		  || rtx_equal_p (operands[0], operands[1]))
-		 ? operands[0] : gen_reg_rtx (SImode));
-
-      HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
-      HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
-
-      if (low & 0x8000)
-        high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
-
-      emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high)));
-      emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
-      DONE;
-    }
-}")
-
-(define_insn "*addsi3_internal1"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
-	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
-		 (match_operand:SI 2 "add_operand" "r,I,I,J")))]
-  ""
-  "@
-   {cax|add} %0,%1,%2
-   {cal %0,%2(%1)|addi %0,%1,%2}
-   {ai|addic} %0,%1,%2
-   {cau|addis} %0,%1,%v2"
-  [(set_attr "length" "4,4,4,4")])
-
-(define_insn "*addsi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
-			     (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
-  ""
-  "@
-   {cax.|add.} %3,%1,%2
-   {ai.|addic.} %3,%1,%2
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			     (match_operand:SI 2 "reg_or_short_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(plus:SI (match_dup 1)
-		 (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*addsi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
-			     (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(plus:SI (match_dup 1)
-		 (match_dup 2)))]
-  ""
-  "@
-   {cax.|add.} %0,%1,%2
-   {ai.|addic.} %0,%1,%2
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			     (match_operand:SI 2 "reg_or_short_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(plus:SI (match_dup 1)
-		 (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-;; Split an add that we can't do in one insn into two insns, each of which
-;; does one 16-bit part.  This is used by combine.  Note that the low-order
-;; add should be last in case the result gets used in an address.
-
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		 (match_operand:SI 2 "non_add_cint_operand" "")))]
-  ""
-  [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
-   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
-"
-{
-  HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
-  HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
-
-  if (low & 0x8000)
-    high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
-
-  operands[3] = GEN_INT (high);
-  operands[4] = GEN_INT (low);
-}")
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  ""
-  "nor %0,%1,%1")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 "=r,r"))]
-  ""
-  "@
-   nor. %2,%1,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 2)
-	(not:SI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(not:SI (match_dup 1)))]
-  ""
-  "@
-   nor. %0,%1,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(not:SI (match_dup 1)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(not:SI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
-		  (match_operand:SI 2 "gpc_reg_operand" "r")))]
-  "! TARGET_POWERPC"
-  "{sf%I1|subf%I1c} %0,%2,%1")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
-		  (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
-  "TARGET_POWERPC"
-  "@
-   subf %0,%2,%1
-   subfic %0,%2,%1")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "! TARGET_POWERPC"
-  "@
-   {sf.|subfc.} %3,%2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			      (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "! TARGET_POWERPC && reload_completed"
-  [(set (match_dup 3)
-	(minus:SI (match_dup 1)
-		  (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "TARGET_POWERPC"
-  "@
-   subf. %3,%2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			      (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "TARGET_POWERPC && reload_completed"
-  [(set (match_dup 3)
-	(minus:SI (match_dup 1)
-		  (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(minus:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWERPC"
-  "@
-   {sf.|subfc.} %0,%2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			      (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(minus:SI (match_dup 1)
-		  (match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(minus:SI (match_dup 1)
-		  (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(minus:SI (match_dup 1)
-		  (match_dup 2)))]
-  "TARGET_POWERPC"
-  "subf. %0,%2,%1"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			      (match_operand:SI 2 "reg_or_short_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(minus:SI (match_dup 1)
-		  (match_dup 2)))]
-  "TARGET_POWERPC && reload_completed"
-  [(set (match_dup 0)
-	(minus:SI (match_dup 1)
-		  (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
-		  (match_operand:SI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      emit_insn (gen_addsi3 (operands[0], operands[1],
-			     negate_rtx (SImode, operands[2])));
-      DONE;
-    }
-}")
-
-;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
-;; instruction and some auxiliary computations.  Then we just have a single
-;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
-;; combine.
-
-(define_expand "sminsi3"
-  [(set (match_dup 3)
-	(if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				(match_operand:SI 2 "reg_or_short_operand" ""))
-			 (const_int 0)
-			 (minus:SI (match_dup 2) (match_dup 1))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(minus:SI (match_dup 2) (match_dup 3)))]
-  "TARGET_POWER"
-  "
-{ operands[3] = gen_reg_rtx (SImode); }")
-
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		 (match_operand:SI 2 "reg_or_short_operand" "")))
-   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
-  "TARGET_POWER"
-  [(set (match_dup 3)
-	(if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
-			 (const_int 0)
-			 (minus:SI (match_dup 2) (match_dup 1))))
-   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
-  "")
-
-(define_expand "smaxsi3"
-  [(set (match_dup 3)
-	(if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				(match_operand:SI 2 "reg_or_short_operand" ""))
-			 (const_int 0)
-			 (minus:SI (match_dup 2) (match_dup 1))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (match_dup 3) (match_dup 1)))]
-  "TARGET_POWER"
-  "
-{ operands[3] = gen_reg_rtx (SImode); }")
-
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		 (match_operand:SI 2 "reg_or_short_operand" "")))
-   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
-  "TARGET_POWER"
-  [(set (match_dup 3)
-	(if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
-			 (const_int 0)
-			 (minus:SI (match_dup 2) (match_dup 1))))
-   (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
-  "")
-
-(define_expand "uminsi3"
-  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			      (match_dup 5)))
-   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
-			      (match_dup 5)))
-   (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
-				       (const_int 0)
-				       (minus:SI (match_dup 4) (match_dup 3))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(minus:SI (match_dup 2) (match_dup 3)))]
-  "TARGET_POWER"
-  "
-{
-  operands[3] = gen_reg_rtx (SImode);
-  operands[4] = gen_reg_rtx (SImode);
-  operands[5] = GEN_INT (-2147483647 - 1);
-}")
-
-(define_expand "umaxsi3"
-  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			      (match_dup 5)))
-   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
-			      (match_dup 5)))
-   (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
-				       (const_int 0)
-				       (minus:SI (match_dup 4) (match_dup 3))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (match_dup 3) (match_dup 1)))]
-  "TARGET_POWER"
-  "
-{
-  operands[3] = gen_reg_rtx (SImode);
-  operands[4] = gen_reg_rtx (SImode);
-  operands[5] = GEN_INT (-2147483647 - 1);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
-			     (match_operand:SI 2 "reg_or_short_operand" "rI"))
-			 (const_int 0)
-			 (minus:SI (match_dup 2) (match_dup 1))))]
-  "TARGET_POWER"
-  "doz%I2 %0,%1,%2")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-			  (const_int 0)
-			  (minus:SI (match_dup 2) (match_dup 1)))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "TARGET_POWER"
-  "@
-   doz%I2. %3,%1,%2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "=x,?y")
-	(compare:CC
-	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-			  (const_int 0)
-			  (minus:SI (match_dup 2) (match_dup 1)))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 3)
-	(if_then_else:SI (gt (match_dup 1)
-			     (match_dup 2))
-			 (const_int 0)
-			 (minus:SI (match_dup 2)
-				   (match_dup 1))))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-			  (const_int 0)
-			  (minus:SI (match_dup 2) (match_dup 1)))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
-			 (const_int 0)
-			 (minus:SI (match_dup 2) (match_dup 1))))]
-  "TARGET_POWER"
-  "doz%I2. %0,%1,%2"
-  [(set_attr "type" "delayed_compare")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "=x,?y")
-	(compare:CC
-	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-			  (const_int 0)
-			  (minus:SI (match_dup 2) (match_dup 1)))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(if_then_else:SI (gt (match_dup 1)
-			     (match_dup 2))
-			 (const_int 0)
-			 (minus:SI (match_dup 2)
-				   (match_dup 1))))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(if_then_else:SI (gt (match_dup 1)
-			     (match_dup 2))
-			 (const_int 0)
-			 (minus:SI (match_dup 2)
-				   (match_dup 1))))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-;; We don't need abs with condition code because such comparisons should
-;; never be done.
-(define_expand "abssi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
-  ""
-  "
-{
-  if (!TARGET_POWER)
-    {
-      emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
-      DONE;
-    }
-}")
-
-(define_insn "abssi2_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWER"
-  "abs %0,%1")
-
-(define_insn "abssi2_nopower"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
-	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
-   (clobber (match_scratch:SI 2 "=&r,&r"))]
-  "!TARGET_POWER"
-  "*
-{
-  return (TARGET_POWERPC)
-    ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
-    : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
-}"
-  [(set_attr "length" "12")])
-
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
-	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
-   (clobber (match_scratch:SI 2 "=&r,&r"))]
-  "!TARGET_POWER && reload_completed"
-  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
-   (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
-   (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
-  "")
-
-(define_insn "*nabs_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
-  "TARGET_POWER"
-  "nabs %0,%1")
-
-(define_insn "*nabs_no_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
-	(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
-   (clobber (match_scratch:SI 2 "=&r,&r"))]
-  "!TARGET_POWER"
-  "*
-{
-  return (TARGET_POWERPC)
-    ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
-    : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
-}"
-  [(set_attr "length" "12")])
-
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
-	(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
-   (clobber (match_scratch:SI 2 "=&r,&r"))]
-  "!TARGET_POWER && reload_completed"
-  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
-   (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
-   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
-  "")
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  ""
-  "neg %0,%1")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 "=r,r"))]
-  ""
-  "@
-   neg. %2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 2)
-	(neg:SI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(neg:SI (match_dup 1)))]
-  ""
-  "@
-   neg. %0,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (match_dup 1)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(neg:SI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "ffssi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
-	(ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  ""
-  "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
-  [(set_attr "length" "16")])
-
-(define_expand "mulsi3"
-  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
-   (use (match_operand:SI 1 "gpc_reg_operand" ""))
-   (use (match_operand:SI 2 "reg_or_short_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_POWER)
-    emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn "mulsi3_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
-		 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-   (clobber (match_scratch:SI 3 "=q,q"))]
-  "TARGET_POWER"
-  "@
-   {muls|mullw} %0,%1,%2
-   {muli|mulli} %0,%1,%2"
-   [(set_attr "type" "imul")])
-
-(define_insn "mulsi3_no_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
-		 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
-  "! TARGET_POWER"
-  "@
-   {muls|mullw} %0,%1,%2
-   {muli|mulli} %0,%1,%2"
-   [(set_attr "type" "imul")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			     (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))
-   (clobber (match_scratch:SI 4 "=q,q"))]
-  "TARGET_POWER"
-  "@
-   {muls.|mullw.} %3,%1,%2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			     (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 3)
-		   (mult:SI (match_dup 1)
-			    (match_dup 2)))
-	      (clobber (match_dup 4))])
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			     (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "! TARGET_POWER"
-  "@
-   {muls.|mullw.} %3,%1,%2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			     (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(mult:SI (match_dup 1)
-		 (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			     (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(mult:SI (match_dup 1)
-		 (match_dup 2)))
-   (clobber (match_scratch:SI 4 "=q,q"))]
-  "TARGET_POWER"
-  "@
-   {muls.|mullw.} %0,%1,%2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			     (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(mult:SI (match_dup 1)
-		 (match_dup 2)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
-		   (mult:SI (match_dup 1)
-			    (match_dup 2)))
-	      (clobber (match_dup 4))])
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			     (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(mult:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWER"
-  "@
-   {muls.|mullw.} %0,%1,%2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			     (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(mult:SI (match_dup 1)
-		 (match_dup 2)))]
-  "!TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(mult:SI (match_dup 1)
-		 (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-;; Operand 1 is divided by operand 2; quotient goes to operand
-;; 0 and remainder to operand 3.
-;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
-
-(define_expand "divmodsi4"
-  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
-		   (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			   (match_operand:SI 2 "gpc_reg_operand" "")))
-	      (set (match_operand:SI 3 "gpc_reg_operand" "")
-		   (mod:SI (match_dup 1) (match_dup 2)))])]
-  "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
-  "
-{
-  if (! TARGET_POWER && ! TARGET_POWERPC)
-    {
-      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
-      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
-      emit_insn (gen_divss_call ());
-      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
-      emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		(match_operand:SI 2 "gpc_reg_operand" "r")))
-   (set (match_operand:SI 3 "gpc_reg_operand" "=q")
-	(mod:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWER"
-  "divs %0,%1,%2"
-  [(set_attr "type" "idiv")])
-
-(define_expand "udivsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-        (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
-                 (match_operand:SI 2 "gpc_reg_operand" "")))]
-  "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
-  "
-{
-  if (! TARGET_POWER && ! TARGET_POWERPC)
-    {
-      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
-      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
-      emit_insn (gen_quous_call ());
-      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
-      DONE;
-    }
-  else if (TARGET_POWER)
-    {
-      emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-(define_insn "udivsi3_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-        (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-                 (match_operand:SI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 3 "=q"))]
-  "TARGET_POWERPC && TARGET_POWER"
-  "divwu %0,%1,%2"
-  [(set_attr "type" "idiv")])
-
-(define_insn "*udivsi3_no_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-        (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-                 (match_operand:SI 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC && ! TARGET_POWER"
-  "divwu %0,%1,%2"
-  [(set_attr "type" "idiv")])
-
-;; For powers of two we can do srai/aze for divide and then adjust for
-;; modulus.  If it isn't a power of two, FAIL on POWER so divmodsi4 will be
-;; used; for PowerPC, force operands into register and do a normal divide;
-;; for AIX common-mode, use quoss call on register operands.
-(define_expand "divsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(div:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(match_operand:SI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && exact_log2 (INTVAL (operands[2])) >= 0)
-    ;
-  else if (TARGET_POWERPC)
-    {
-      operands[2] = force_reg (SImode, operands[2]);
-      if (TARGET_POWER)
-	{
-	  emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
-	  DONE;
-	}
-    }
-  else if (TARGET_POWER)
-    FAIL;
-  else
-    {
-      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
-      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
-      emit_insn (gen_quoss_call ());
-      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
-      DONE;
-    }
-}")
-
-(define_insn "divsi3_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-        (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-                (match_operand:SI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 3 "=q"))]
-  "TARGET_POWERPC && TARGET_POWER"
-  "divw %0,%1,%2"
-  [(set_attr "type" "idiv")])
-
-(define_insn "*divsi3_no_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-        (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-                (match_operand:SI 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC && ! TARGET_POWER"
-  "divw %0,%1,%2"
-  [(set_attr "type" "idiv")])
-
-(define_expand "modsi3"
-  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
-   (use (match_operand:SI 1 "gpc_reg_operand" ""))
-   (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
-  ""
-  "
-{
-  int i = exact_log2 (INTVAL (operands[2]));
-  rtx temp1;
-  rtx temp2;
-
-  if (GET_CODE (operands[2]) != CONST_INT || i < 0)
-    FAIL;
-
-  temp1 = gen_reg_rtx (SImode);
-  temp2 = gen_reg_rtx (SImode);
-
-  emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
-  emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
-  emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		(match_operand:SI 2 "const_int_operand" "N")))]
-  "exact_log2 (INTVAL (operands[2])) >= 0"
-  "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
-  [(set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:SI 2 "const_int_operand" "N,N"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "exact_log2 (INTVAL (operands[2])) >= 0"
-  "@
-   {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "const_int_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed && exact_log2 (INTVAL (operands[2])) >= 0"
-  [(set (match_dup 3)
-	(div:SI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:SI 2 "const_int_operand" "N,N"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(div:SI (match_dup 1)
-		(match_dup 2)))]
-  "exact_log2 (INTVAL (operands[2])) >= 0"
-  "@
-   {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "reg_or_short_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(div:SI (match_dup 1)
-		(match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(div:SI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(udiv:SI
-	 (plus:DI (ashift:DI
-		   (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
-		   (const_int 32))
-		  (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
-	 (match_operand:SI 3 "gpc_reg_operand" "r")))
-   (set (match_operand:SI 2 "register_operand" "=*q")
-	(umod:SI
-	 (plus:DI (ashift:DI
-		   (zero_extend:DI (match_dup 1)) (const_int 32))
-		  (zero_extend:DI (match_dup 4)))
-	 (match_dup 3)))]
-  "TARGET_POWER"
-  "div %0,%1,%3"
-  [(set_attr "type" "idiv")])
-
-;; To do unsigned divide we handle the cases of the divisor looking like a
-;; negative number.  If it is a constant that is less than 2**31, we don't
-;; have to worry about the branches.  So make a few subroutines here.
-;;
-;; First comes the normal case.
-(define_expand "udivmodsi4_normal"
-  [(set (match_dup 4) (const_int 0))
-   (parallel [(set (match_operand:SI 0 "" "")
-		   (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
-						(const_int 32))
-				     (zero_extend:DI (match_operand:SI 1 "" "")))
-			    (match_operand:SI 2 "" "")))
-	      (set (match_operand:SI 3 "" "")
-		   (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
-						(const_int 32))
-				     (zero_extend:DI (match_dup 1)))
-			    (match_dup 2)))])]
-  "TARGET_POWER"
-  "
-{ operands[4] = gen_reg_rtx (SImode); }")
-
-;; This handles the branches.
-(define_expand "udivmodsi4_tests"
-  [(set (match_operand:SI 0 "" "") (const_int 0))
-   (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
-   (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
-   (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
-			   (label_ref (match_operand:SI 4 "" "")) (pc)))
-   (set (match_dup 0) (const_int 1))
-   (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
-   (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
-			   (label_ref (match_dup 4)) (pc)))]
-  "TARGET_POWER"
-  "
-{ operands[5] = gen_reg_rtx (CCUNSmode);
-  operands[6] = gen_reg_rtx (CCmode);
-}")
-
-(define_expand "udivmodsi4"
-  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
-		   (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "reg_or_cint_operand" "")))
-	      (set (match_operand:SI 3 "gpc_reg_operand" "")
-		   (umod:SI (match_dup 1) (match_dup 2)))])]
-  ""
-  "
-{
-  rtx label = 0;
-
-  if (! TARGET_POWER)
-    {
-      if (! TARGET_POWERPC)
-        {
-	  emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
-	  emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
-	  emit_insn (gen_divus_call ());
-	  emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
-	  emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
-	  DONE;
-        }
-      else
-        FAIL;
-    }
-
-  if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
-    {
-      operands[2] = force_reg (SImode, operands[2]);
-      label = gen_label_rtx ();
-      emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
-				  operands[3], label));
-    }
-  else
-    operands[2] = force_reg (SImode, operands[2]);
-
-  emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
-			       operands[3]));
-  if (label)
-    emit_label (label);
-
-  DONE;
-}")
-
-;; AIX architecture-independent common-mode multiply (DImode),
-;; divide/modulus, and quotient subroutine calls.  Input operands in R3 and
-;; R4; results in R3 and sometimes R4; link register always clobbered by bla
-;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
-;; assumed unused if generating common-mode, so ignore.
-(define_insn "mulh_call"
-  [(set (reg:SI 3)
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
-			       (sign_extend:DI (reg:SI 4)))
-		      (const_int 32))))
-   (clobber (match_scratch:SI 0 "=l"))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __mulh"
-  [(set_attr "type" "imul")])
-
-(define_insn "mull_call"
-  [(set (reg:DI 3)
-	(mult:DI (sign_extend:DI (reg:SI 3))
-		 (sign_extend:DI (reg:SI 4))))
-   (clobber (match_scratch:SI 0 "=l"))
-   (clobber (reg:SI 0))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __mull"
-  [(set_attr "type" "imul")])
-
-(define_insn "divss_call"
-  [(set (reg:SI 3)
-	(div:SI (reg:SI 3) (reg:SI 4)))
-   (set (reg:SI 4)
-	(mod:SI (reg:SI 3) (reg:SI 4)))
-   (clobber (match_scratch:SI 0 "=l"))
-   (clobber (reg:SI 0))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __divss"
-  [(set_attr "type" "idiv")])
-
-(define_insn "divus_call"
-  [(set (reg:SI 3)
-	(udiv:SI (reg:SI 3) (reg:SI 4)))
-   (set (reg:SI 4)
-	(umod:SI (reg:SI 3) (reg:SI 4)))
-   (clobber (match_scratch:SI 0 "=l"))
-   (clobber (reg:SI 0))
-   (clobber (match_scratch:CC 1 "=x"))
-   (clobber (reg:CC 69))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __divus"
-  [(set_attr "type" "idiv")])
-
-(define_insn "quoss_call"
-  [(set (reg:SI 3)
-	(div:SI (reg:SI 3) (reg:SI 4)))
-   (clobber (match_scratch:SI 0 "=l"))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __quoss"
-  [(set_attr "type" "idiv")])
-
-(define_insn "quous_call"
-  [(set (reg:SI 3)
-	(udiv:SI (reg:SI 3) (reg:SI 4)))
-   (clobber (match_scratch:SI 0 "=l"))
-   (clobber (reg:SI 0))
-   (clobber (match_scratch:CC 1 "=x"))
-   (clobber (reg:CC 69))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __quous"
-  [(set_attr "type" "idiv")])
-
-;; Logical instructions
-(define_expand "andsi3"
-  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-		   (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
-			   (match_operand:SI 2 "and_operand" "?r,L,K,J")))
-	      (clobber (match_scratch:CC 3 "=X,X,x,x"))])]
-  ""
-  "")
-
-;; If cr0 isn't available, and we want to do an andi, load the register into
-;; the destination first.
-
-(define_insn "andsi3_internal1"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,&??r,&??r")
-	(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
-		(match_operand:SI 2 "and_operand" "?r,L,K,J,K,J")))
-   (clobber (match_operand:CC 3 "scratch_operand" "=X,X,x,x,X,X"))]
-  ""
-  "@
-   and %0,%1,%2
-   {rlinm|rlwinm} %0,%1,0,%m2,%M2
-   {andil.|andi.} %0,%1,%b2
-   {andiu.|andis.} %0,%1,%u2
-   #
-   #"
-  [(set_attr "length" "4,4,4,4,8,8")])
-
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(and:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(match_operand:SI 2 "const_int_operand" "")))
-   (clobber (scratch:CC))]
-  "reload_completed && !mask_constant (INTVAL (operands[2]))"
-  [(set (match_dup 0)
-	(match_dup 2))
-   (parallel [(set (match_dup 0)
-		   (and:SI (match_dup 0)
-			   (match_dup 1)))
-	      (clobber (scratch:CC))])]
-  "")
-
-;; Note to set cr's other than cr0 we do the and immediate and then
-;; the test again -- this avoids a mcrf which on the higher end
-;; machines causes an execution serialization
-
-(define_insn "*andsi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y,???y,???y")
-	(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
-			    (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L,K,L"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r,&r,&r"))
-   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))]
-  ""
-  "@
-   and. %3,%1,%2
-   {andil.|andi.} %3,%1,%b2
-   {andiu.|andis.} %3,%1,%u2
-   {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
-   #
-   #
-   #
-   #
-   #
-   #"
-  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")
-   (set_attr "length" "4,4,4,4,8,8,8,8,12,12")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "and_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))
-   (clobber (match_scratch:CC 4 ""))]
-  "reload_completed"
-  [(parallel [(set (match_dup 3)
-		   (and:SI (match_dup 1)
-			   (match_dup 2)))
-	      (clobber (match_dup 4))])
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*andsi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y,???y,???y")
-	(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
-			    (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L,K,J"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,&r,&r")
-	(and:SI (match_dup 1)
-		(match_dup 2)))
-   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))]
-  ""
-  "@
-   and. %0,%1,%2
-   {andil.|andi.} %0,%1,%b2
-   {andiu.|andis.} %0,%1,%u2
-   {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
-   #
-   #
-   #
-   #
-   #
-   #"
-  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")
-   (set_attr "length" "4,4,4,4,8,8,8,8,12,12")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "and_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(and:SI (match_dup 1)
-		(match_dup 2)))
-   (clobber (match_scratch:CC 4 ""))]
-  "reload_completed"
-  [(parallel [(set (match_dup 0)
-		   (and:SI (match_dup 1)
-			   (match_dup 2)))
-	      (clobber (match_dup 4))])
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "iorsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(match_operand:SI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && !logical_operand (operands[2], SImode))
-    {
-      HOST_WIDE_INT value = INTVAL (operands[2]);
-      rtx tmp = ((reload_in_progress || reload_completed
-		  || rtx_equal_p (operands[0], operands[1]))
-		 ? operands[0] : gen_reg_rtx (SImode));
-
-      emit_insn (gen_iorsi3 (tmp, operands[1],
-			     GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
-      emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
-      DONE;
-    }
-}")
-
-(define_insn "*iorsi3_internal1"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
-	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
-		(match_operand:SI 2 "logical_operand" "r,K,J")))]
-  ""
-  "@
-   or %0,%1,%2
-   {oril|ori} %0,%1,%b2
-   {oriu|oris} %0,%1,%u2"
-  [(set_attr "length" "4,4,4")])
-
-(define_insn "*iorsi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  ""
-  "@
-   or. %3,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(ior:SI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*iorsi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (match_dup 1)
-		(match_dup 2)))]
-  ""
-  "@
-   or. %0,%1,%2
-   #"
-  [(set_attr "type" "compare")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (match_dup 1) (match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(ior:SI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-;; Split an IOR that we can't do in one insn into two insns, each of which
-;; does one 16-bit part.  This is used by combine.
-
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(match_operand:SI 2 "non_logical_cint_operand" "")))]
-  ""
-  [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
-   (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
-"
-{
-  operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
-  operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
-}")
-
-(define_expand "xorsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(match_operand:SI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && !logical_operand (operands[2], SImode))
-    {
-      HOST_WIDE_INT value = INTVAL (operands[2]);
-      rtx tmp = ((reload_in_progress || reload_completed
-		  || rtx_equal_p (operands[0], operands[1]))
-		 ? operands[0] : gen_reg_rtx (SImode));
-
-      emit_insn (gen_xorsi3 (tmp, operands[1],
-			     GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
-      emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
-      DONE;
-    }
-}")
-
-(define_insn "*xorsi3_internal1"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
-	(xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
-		(match_operand:SI 2 "logical_operand" "r,K,J")))]
-  ""
-  "@
-   xor %0,%1,%2
-   {xoril|xori} %0,%1,%b2
-   {xoriu|xoris} %0,%1,%u2"
-  [(set_attr "length" "4,4,4")])
-
-(define_insn "*xorsi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  ""
-  "@
-   xor. %3,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(xor:SI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*xorsi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(xor:SI (match_dup 1)
-		(match_dup 2)))]
-  ""
-  "@
-   xor. %0,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(xor:SI (match_dup 1) (match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(xor:SI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-;; Split an XOR that we can't do in one insn into two insns, each of which
-;; does one 16-bit part.  This is used by combine.
-
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-        (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
-                (match_operand:SI 2 "non_logical_cint_operand" "")))]
-  ""
-  [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
-   (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
-"
-{
-  operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
-  operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
-}")
-
-(define_insn "*eqvsi3_internal1"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
-			(match_operand:SI 2 "gpc_reg_operand" "r"))))]
-   ""
-   "eqv %0,%1,%2")
-
-(define_insn "*eqvsi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-				    (match_operand:SI 2 "gpc_reg_operand" "r,r")))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-   ""
-   "@
-    eqv. %3,%1,%2
-    #"
-   [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				    (match_operand:SI 2 "gpc_reg_operand" "")))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(not:SI (xor:SI (match_dup 1)
-			(match_dup 2))))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*eqvsi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-				    (match_operand:SI 2 "gpc_reg_operand" "r,r")))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(not:SI (xor:SI (match_dup 1) (match_dup 2))))]
-   ""
-   "@
-    eqv. %0,%1,%2
-    #"
-   [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				    (match_operand:SI 2 "reg_or_short_operand" "")))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(not:SI (xor:SI (match_dup 1)
-			(match_dup 2))))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(not:SI (xor:SI (match_dup 1)
-			(match_dup 2))))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*andcsi3_internal1"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-		(match_operand:SI 2 "gpc_reg_operand" "r")))]
-  ""
-  "andc %0,%2,%1")
-
-(define_insn "*andcsi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-			    (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  ""
-  "@
-   andc. %3,%2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-			    (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(and:SI (not:SI (match_dup 1))
-		(match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*andcsi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-			    (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(and:SI (not:SI (match_dup 1))
-		(match_dup 2)))]
-  ""
-  "@
-   andc. %0,%2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-			    (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(and:SI (not:SI (match_dup 1))
-		(match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(and:SI (not:SI (match_dup 1))
-		(match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*iorcsi3_internal1"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-		(match_operand:SI 2 "gpc_reg_operand" "r")))]
-  ""
-  "orc %0,%2,%1")
-
-(define_insn "*iorcsi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-			    (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  ""
-  "@
-   orc. %3,%2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-			    (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(ior:SI (not:SI (match_dup 1))
-		(match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*iorcsi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-			    (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
-  ""
-  "@
-   orc. %0,%2,%1
-   #"
-  [(set_attr "type" "compare")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-			    (match_operand:SI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (not:SI (match_dup 1))
-		(match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(ior:SI (not:SI (match_dup 1))
-		(match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*nandsi3_internal1"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
-  ""
-  "nand %0,%1,%2")
-
-(define_insn "*nandsi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  ""
-  "@
-   nand. %3,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(ior:SI (not:SI (match_dup 1))
-		(not:SI (match_dup 2))))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*nandsi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (not:SI (match_dup 1))
-		(not:SI (match_dup 2))))]
-  ""
-  "@
-   nand. %0,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (not:SI (match_dup 1))
-		(not:SI (match_dup 2))))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(ior:SI (not:SI (match_dup 1))
-		(not:SI (match_dup 2))))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*norsi3_internal1"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
-  ""
-  "nor %0,%1,%2")
-
-(define_insn "*norsi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  ""
-  "@
-   nor. %3,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(and:SI (not:SI (match_dup 1))
-		(not:SI (match_dup 2))))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*norsi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(and:SI (not:SI (match_dup 1))
-		(not:SI (match_dup 2))))]
-  ""
-  "@
-   nor. %0,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(and:SI (not:SI (match_dup 1))
-		(not:SI (match_dup 2))))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(and:SI (not:SI (match_dup 1))
-		(not:SI (match_dup 2))))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-;; maskir insn.  We need four forms because things might be in arbitrary
-;; orders.  Don't define forms that only set CR fields because these
-;; would modify an input register.
-
-(define_insn "*maskir_internal1"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
-			(match_operand:SI 1 "gpc_reg_operand" "0"))
-		(and:SI (match_dup 2)
-			(match_operand:SI 3 "gpc_reg_operand" "r"))))]
-  "TARGET_POWER"
-  "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
-			(match_operand:SI 1 "gpc_reg_operand" "0"))
-		(and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
-			(match_dup 2))))]
-  "TARGET_POWER"
-  "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
-			(match_operand:SI 3 "gpc_reg_operand" "r"))
-		(and:SI (not:SI (match_dup 2))
-			(match_operand:SI 1 "gpc_reg_operand" "0"))))]
-  "TARGET_POWER"
-  "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal4"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
-			(match_operand:SI 2 "gpc_reg_operand" "r"))
-		(and:SI (not:SI (match_dup 2))
-			(match_operand:SI 1 "gpc_reg_operand" "0"))))]
-  "TARGET_POWER"
-  "maskir %0,%3,%2")
-
-(define_insn "*maskir_internal5"
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-			 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
-		 (and:SI (match_dup 2)
-			 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
-		(and:SI (match_dup 2) (match_dup 3))))]
-  "TARGET_POWER"
-  "@
-   maskir. %0,%3,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
-			 (match_operand:SI 1 "gpc_reg_operand" ""))
-		 (and:SI (match_dup 2)
-			 (match_operand:SI 3 "gpc_reg_operand" "")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
-		(and:SI (match_dup 2) (match_dup 3))))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(ior:SI (and:SI (not:SI (match_dup 2))
-			(match_dup 1))
-		(and:SI (match_dup 2)
-			(match_dup 3))))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-
-(define_insn "*maskir_internal6"
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-			 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
-		 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
-			 (match_dup 2)))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
-		(and:SI (match_dup 3) (match_dup 2))))]
-  "TARGET_POWER"
-  "@
-   maskir. %0,%3,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
-			 (match_operand:SI 1 "gpc_reg_operand" ""))
-		 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
-			 (match_dup 2)))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
-		(and:SI (match_dup 3) (match_dup 2))))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(ior:SI (and:SI (not:SI (match_dup 2))
-			(match_dup 1))
-		(and:SI (match_dup 3)
-			(match_dup 2))))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*maskir_internal7"
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-		 (and:SI (not:SI (match_dup 2))
-			 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (and:SI (match_dup 2) (match_dup 3))
-		(and:SI (not:SI (match_dup 2)) (match_dup 1))))]
-  "TARGET_POWER"
-  "@
-   maskir. %0,%3,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
-			 (match_operand:SI 3 "gpc_reg_operand" ""))
-		 (and:SI (not:SI (match_dup 2))
-			 (match_operand:SI 1 "gpc_reg_operand" "")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ior:SI (and:SI (match_dup 2) (match_dup 3))
-		(and:SI (not:SI (match_dup 2)) (match_dup 1))))]
-  "TARGET_POWER"
-  [(set (match_dup 0)
-	(ior:SI (and:SI (match_dup 2)
-			(match_dup 3))
-		(and:SI (not:SI (match_dup 2))
-			(match_dup 1))))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*maskir_internal8"
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-		 (and:SI (not:SI (match_dup 2))
-			 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (and:SI (match_dup 3) (match_dup 2))
-		(and:SI (not:SI (match_dup 2)) (match_dup 1))))]
-  "TARGET_POWER"
-  "@
-   maskir. %0,%3,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "gpc_reg_operand" ""))
-		 (and:SI (not:SI (match_dup 2))
-			 (match_operand:SI 1 "gpc_reg_operand" "")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ior:SI (and:SI (match_dup 3) (match_dup 2))
-		(and:SI (not:SI (match_dup 2)) (match_dup 1))))]
-  "TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(ior:SI (and:SI (match_dup 3)
-			(match_dup 2))
-		(and:SI (not:SI (match_dup 2))
-			(match_dup 1))))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-
-;; Rotate and shift insns, in all their variants.  These support shifts,
-;; field inserts and extracts, and various combinations thereof.
-(define_expand "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (match_operand:SI 1 "const_int_operand" "i")
-			 (match_operand:SI 2 "const_int_operand" "i"))
-	(match_operand:SI 3 "gpc_reg_operand" "r"))]
-  ""
-  "
-{
-  /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
-     the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
-     compiler if the address of the structure is taken later.  */
-  if (GET_CODE (operands[0]) == SUBREG
-      && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (match_operand:SI 1 "const_int_operand" "i")
-			 (match_operand:SI 2 "const_int_operand" "i"))
-	(match_operand:SI 3 "gpc_reg_operand" "r"))]
-  ""
-  "*
-{
-  int start = INTVAL (operands[2]) & 31;
-  int size = INTVAL (operands[1]) & 31;
-
-  operands[4] = GEN_INT (32 - start - size);
-  operands[1] = GEN_INT (start + size - 1);
-  return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (match_operand:SI 1 "const_int_operand" "i")
-			 (match_operand:SI 2 "const_int_operand" "i"))
-	(ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
-		   (match_operand:SI 4 "const_int_operand" "i")))]
-  "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
-  "*
-{
-  int shift = INTVAL (operands[4]) & 31;
-  int start = INTVAL (operands[2]) & 31;
-  int size = INTVAL (operands[1]) & 31;
-
-  operands[4] = GEN_INT (shift - start - size);
-  operands[1] = GEN_INT (start + size - 1);
-  return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (match_operand:SI 1 "const_int_operand" "i")
-			 (match_operand:SI 2 "const_int_operand" "i"))
-	(ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
-		     (match_operand:SI 4 "const_int_operand" "i")))]
-  "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
-  "*
-{
-  int shift = INTVAL (operands[4]) & 31;
-  int start = INTVAL (operands[2]) & 31;
-  int size = INTVAL (operands[1]) & 31;
-
-  operands[4] = GEN_INT (32 - shift - start - size);
-  operands[1] = GEN_INT (start + size - 1);
-  return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (match_operand:SI 1 "const_int_operand" "i")
-			 (match_operand:SI 2 "const_int_operand" "i"))
-	(lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
-		     (match_operand:SI 4 "const_int_operand" "i")))]
-  "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
-  "*
-{
-  int shift = INTVAL (operands[4]) & 31;
-  int start = INTVAL (operands[2]) & 31;
-  int size = INTVAL (operands[1]) & 31;
-
-  operands[4] = GEN_INT (32 - shift - start - size);
-  operands[1] = GEN_INT (start + size - 1);
-  return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (match_operand:SI 1 "const_int_operand" "i")
-			 (match_operand:SI 2 "const_int_operand" "i"))
-	(zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
-			 (match_operand:SI 4 "const_int_operand" "i")
-			 (match_operand:SI 5 "const_int_operand" "i")))]
-  "INTVAL (operands[4]) >= INTVAL (operands[1])"
-  "*
-{
-  int extract_start = INTVAL (operands[5]) & 31;
-  int extract_size = INTVAL (operands[4]) & 31;
-  int insert_start = INTVAL (operands[2]) & 31;
-  int insert_size = INTVAL (operands[1]) & 31;
-
-/* Align extract field with insert field */
-  operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
-  operands[1] = GEN_INT (insert_start + insert_size - 1);
-  return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
-}")
-
-(define_insn ""
-  [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
-			 (match_operand:DI 1 "const_int_operand" "i")
-			 (match_operand:DI 2 "const_int_operand" "i"))
-	(match_operand:DI 3 "gpc_reg_operand" "r"))]
-  "TARGET_POWERPC64"
-  "*
-{
-  int start = INTVAL (operands[2]) & 63;
-  int size = INTVAL (operands[1]) & 63;
-
-  operands[2] = GEN_INT (64 - start - size);
-  return \"rldimi %0,%3,%H2,%H1\";
-}")
-
-(define_expand "extzv"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			 (match_operand:SI 2 "const_int_operand" "i")
-			 (match_operand:SI 3 "const_int_operand" "i")))]
-  ""
-  "
-{
-  /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
-     the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
-     compiler if the address of the structure is taken later.  */
-  if (GET_CODE (operands[0]) == SUBREG
-      && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			 (match_operand:SI 2 "const_int_operand" "i")
-			 (match_operand:SI 3 "const_int_operand" "i")))]
-  ""
-  "*
-{
-  int start = INTVAL (operands[3]) & 31;
-  int size = INTVAL (operands[2]) & 31;
-
-  if (start + size >= 32)
-    operands[3] = const0_rtx;
-  else
-    operands[3] = GEN_INT (start + size);
-  return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
-}")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "const_int_operand" "i,i")
-			 (match_operand:SI 3 "const_int_operand" "i,i"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 4 "=r,r"))]
-  ""
-  "*
-{
-  int start = INTVAL (operands[3]) & 31;
-  int size = INTVAL (operands[2]) & 31;
-
-  /* Split insn if not setting cr0.  */
-  if (cc_reg_not_cr0_operand (operands[0], CCmode))
-    return \"#\";
-
-  /* If the bitfield being tested fits in the upper or lower half of a
-     word, it is possible to use andiu. or andil. to test it.  This is
-     useful because the condition register set-use delay is smaller for
-     andi[ul]. than for rlinm.  This doesn't work when the starting bit
-     position is 0 because the LT and GT bits may be set wrong.  */
-
-  if ((start > 0 && start + size <= 16) || start >= 16)
-    {
-      operands[3] = GEN_INT (((1 << (16 - (start & 15)))
-			      - (1 << (16 - (start & 15) - size))));
-      if (start < 16)
-	return \"{andiu.|andis.} %4,%1,%3\";
-      else
-	return \"{andil.|andi.} %4,%1,%3\";
-    }
-
-  if (start + size >= 32)
-    operands[3] = const0_rtx;
-  else
-    operands[3] = GEN_INT (start + size);
-  return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
-}"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "const_int_operand" "")
-			 (match_operand:SI 3 "const_int_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 4 ""))]
-  "reload_completed"
-  [(set (match_dup 4)
-	(zero_extract:SI (match_dup 1)
-			 (match_dup 2)
-			 (match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "const_int_operand" "i,i")
-			 (match_operand:SI 3 "const_int_operand" "i,i"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
-  ""
-  "*
-{
-  int start = INTVAL (operands[3]) & 31;
-  int size = INTVAL (operands[2]) & 31;
-
-  /* Split insn if not setting cr0.  */
-  if (cc_reg_not_cr0_operand (operands[0], CCmode))
-    return \"#\";
-
-  if (start >= 16 && start + size == 32)
-    {
-      operands[3] = GEN_INT ((1 << (32 - start)) - 1);
-      return \"{andil.|andi.} %0,%1,%3\";
-    }
-
-  if (start + size >= 32)
-    operands[3] = const0_rtx;
-  else
-    operands[3] = GEN_INT (start + size);
-  return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
-}"
-  [(set_attr "type" "delayed_compare")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			 (match_operand:SI 2 "const_int_operand" "")
-			 (match_operand:SI 3 "const_int_operand" ""))
-		    (const_int 0)))
-   (set (match_dup 0)
-	(zero_extract:SI (match_dup 1)
-			 (match_dup 2)
-			 (match_dup 3)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(zero_extract:SI (match_dup 1)
-			 (match_dup 2)
-			 (match_dup 3)))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-			 (match_operand:DI 2 "const_int_operand" "i")
-			 (match_operand:DI 3 "const_int_operand" "i")))]
-  "TARGET_POWERPC64"
-  "*
-{
-  int start = INTVAL (operands[3]) & 63;
-  int size = INTVAL (operands[2]) & 63;
-
-  if (start + size >= 64)
-    operands[3] = const0_rtx;
-  else
-    operands[3] = GEN_INT (start + size);
-  operands[2] = GEN_INT (64 - size);
-  return \"rldicl %0,%1,%3,%2\";
-}")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "gpc_reg_operand" "=x,?y")
-	(compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:DI 2 "const_int_operand" "i,i")
-			 (match_operand:DI 3 "const_int_operand" "i,i"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 4 "=r,r"))]
-  "TARGET_POWERPC64"
-  "*
-{
-  int start = INTVAL (operands[3]) & 63;
-  int size = INTVAL (operands[2]) & 63;
-
-  /* Split insn if not setting cr0.  */
-  if (cc_reg_not_cr0_operand (operands[0], CCmode))
-    return \"#\";
-
-  if (start + size >= 64)
-    operands[3] = const0_rtx;
-  else
-    operands[3] = GEN_INT (start + size);
-  operands[2] = GEN_INT (64 - size);
-  return \"rldicl. %4,%1,%3,%2\";
-}")
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			 (match_operand:DI 2 "const_int_operand" "")
-			 (match_operand:DI 3 "const_int_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 4 ""))]
-  "reload_completed"
-  [(set (match_dup 4)
-	(zero_extract:DI (match_dup 1)
-			 (match_dup 2)
-			 (match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 4 "gpc_reg_operand" "=x,?y")
-	(compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:DI 2 "const_int_operand" "i,i")
-			 (match_operand:DI 3 "const_int_operand" "i,i"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
-  "TARGET_POWERPC64"
-  "*
-{
-  int start = INTVAL (operands[3]) & 63;
-  int size = INTVAL (operands[2]) & 63;
-
-  /* Split insn if not setting cr0.  */
-  if (cc_reg_not_cr0_operand (operands[0], CCmode))
-    return \"#\";
-
-  if (start + size >= 64)
-    operands[3] = const0_rtx;
-  else
-    operands[3] = GEN_INT (start + size);
-  operands[2] = GEN_INT (64 - size);
-  return \"rldicl. %0,%1,%3,%2\";
-}")
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			 (match_operand:DI 2 "const_int_operand" "")
-			 (match_operand:DI 3 "const_int_operand" ""))
-		    (const_int 0)))
-   (set (match_dup 0)
-	(zero_extract:DI (match_dup 1)
-			 (match_dup 2)
-			 (match_dup 3)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(zero_extract:DI (match_dup 1)
-			 (match_dup 2)
-			 (match_dup 3)))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "rotlsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
-  ""
-  "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
-
-(define_insn "*rotlsi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  ""
-  "@
-   {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(rotate:SI (match_dup 1)
-		   (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotlsi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(rotate:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "@
-   {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(rotate:SI (match_dup 1)
-		   (match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(rotate:SI (match_dup 1)
-		   (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotlsi3_internal4"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			   (match_operand:SI 2 "reg_or_cint_operand" "ri"))
-		(match_operand:SI 3 "mask_operand" "L")))]
-  ""
-  "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
-
-(define_insn "*rotlsi3_internal5"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (and:SI
-		     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-				(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		     (match_operand:SI 3 "mask_operand" "L,L"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 4 "=r,r"))]
-  ""
-  "@
-   {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:SI
-		     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				(match_operand:SI 2 "reg_or_cint_operand" ""))
-		     (match_operand:SI 3 "mask_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 4 ""))]
-  "reload_completed"
-  [(set (match_dup 4)
-	(and:SI (rotate:SI (match_dup 1)
-			   (match_dup 2))
-		(match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotlsi3_internal6"
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC (and:SI
-		     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-				(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		     (match_operand:SI 3 "mask_operand" "L,L"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  ""
-  "@
-   {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:SI
-		     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				(match_operand:SI 2 "reg_or_cint_operand" ""))
-		     (match_operand:SI 3 "mask_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(and:SI
-	 (rotate:SI (match_dup 1)
-		    (match_dup 2))
-	 (match_dup 3)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(and:SI (rotate:SI (match_dup 1)
-			   (match_dup 2))
-		(match_dup 3)))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotlsi3_internal7"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(zero_extend:SI
-	 (subreg:QI
-	  (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
-  ""
-  "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
-
-(define_insn "*rotlsi3_internal8"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:SI
-		     (subreg:QI
-		      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  ""
-  "@
-   {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:SI
-		     (subreg:QI
-		      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(zero_extend:SI
-	 (subreg:QI
-	  (rotate:SI (match_dup 1)
-		     (match_dup 2)) 0)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-				 
-(define_insn "*rotlsi3_internal9"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:SI
-		     (subreg:QI
-		      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
-  ""
-  "@
-   {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "=x,?y")
-	(compare:CC (zero_extend:SI
-		     (subreg:QI
-		      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:SI
-	 (subreg:QI
-	  (rotate:SI (match_dup 1)
-		     (match_dup 2)) 0)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-	 
-(define_insn "*rotlsi3_internal10"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(zero_extend:SI
-	 (subreg:HI
-	  (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
-  ""
-  "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
-
-(define_insn "*rotlsi3_internal11"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:SI
-		     (subreg:HI
-		      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  ""
-  "@
-   {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:SI
-		     (subreg:HI
-		      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(zero_extend:SI
-	 (subreg:HI
-	  (rotate:SI (match_dup 1)
-		     (match_dup 2)) 0)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotlsi3_internal12"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:SI
-		     (subreg:HI
-		      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
-  ""
-  "@
-   {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "=x,?y")
-	(compare:CC (zero_extend:SI
-		     (subreg:HI
-		      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:SI
-	 (subreg:HI
-	  (rotate:SI (match_dup 1)
-		     (match_dup 2)) 0)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-;; Note that we use "sle." instead of "sl." so that we can set
-;; SHIFT_COUNT_TRUNCATED.
-
-(define_expand "ashlsi3"
-  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
-   (use (match_operand:SI 1 "gpc_reg_operand" ""))
-   (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_POWER)
-    emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn "ashlsi3_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		   (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
-   (clobber (match_scratch:SI 3 "=q,X"))]
-  "TARGET_POWER"
-  "@
-   sle %0,%1,%2
-   {sli|slwi} %0,%1,%h2"
-  [(set_attr "length" "8")])
-
-(define_insn "ashlsi3_no_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
-  "! TARGET_POWER"
-  "{sl|slw}%I2 %0,%1,%h2"
-  [(set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r,r,r"))
-   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
-  "TARGET_POWER"
-  "@
-   sle. %3,%1,%2
-   {sli.|slwi.} %3,%1,%h2
-   #
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 3)
-		   (ashift:SI (match_dup 1)
-			      (match_dup 2)))
-	      (clobber (match_dup 4))])
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "! TARGET_POWER"
-  "@
-   {sl|slw}%I2. %3,%1,%h2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "! TARGET_POWER && reload_completed"
-  [(set (match_dup 3)
-	(ashift:SI (match_dup 1)
-		   (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(ashift:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
-  "TARGET_POWER"
-  "@
-   sle. %0,%1,%2
-   {sli.|slwi.} %0,%1,%h2
-   #
-   #"
-  [(set_attr "type" "delayed_compare")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashift:SI (match_dup 1)
-		   (match_dup 2)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
-		   (ashift:SI (match_dup 1)
-			      (match_dup 2)))
-	      (clobber (match_dup 4))])
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ashift:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWER"
-  "{sl|slw}%I2. %0,%1,%h2"
-  [(set_attr "type" "delayed_compare")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashift:SI (match_dup 1)
-		   (match_dup 2)))]
-  "! TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(ashift:SI (match_dup 1)
-		   (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			   (match_operand:SI 2 "const_int_operand" "i"))
-		(match_operand:SI 3 "mask_operand" "L")))]
-  "includes_lshift_p (operands[2], operands[3])"
-  "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:SI 2 "const_int_operand" "i,i"))
-		 (match_operand:SI 3 "mask_operand" "L,L"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=r,r"))]
-  "includes_lshift_p (operands[2], operands[3])"
-  "@
-  {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
-  #"
-  [(set_attr "type" "delayed_compare")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "const_int_operand" ""))
-		 (match_operand:SI 3 "mask_operand" ""))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 ""))]
-  "reload_completed && includes_lshift_p (operands[2], operands[3])"
-  [(set (match_dup 4)
-	(and:SI (ashift:SI (match_dup 1)
-			   (match_dup 2))
-		(match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:SI 2 "const_int_operand" "i,i"))
-		 (match_operand:SI 3 "mask_operand" "L,L"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "includes_lshift_p (operands[2], operands[3])"
-  "@
-  {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
-  #"
-  [(set_attr "type" "delayed_compare")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "const_int_operand" ""))
-		 (match_operand:SI 3 "mask_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(and:SI (ashift:SI (match_dup 1)
-			   (match_dup 2))
-		 (match_dup 3)))]
-  "reload_completed && includes_lshift_p (operands[2], operands[3])"
-  [(set (match_dup 4)
-	(and:SI (ashift:SI (match_dup 1)
-			   (match_dup 2))
-		(match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-;; The AIX assembler mis-handles "sri x,x,0", so write that case as
-;; "sli x,x,0".
-(define_expand "lshrsi3"
-  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
-   (use (match_operand:SI 1 "gpc_reg_operand" ""))
-   (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_POWER)
-    emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn "lshrsi3_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
-	(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
-   (clobber (match_scratch:SI 3 "=q,X,X"))]
-  "TARGET_POWER"
-  "@
-  sre %0,%1,%2
-  mr %0,%1
-  {s%A2i|s%A2wi} %0,%1,%h2")
-
-(define_insn "lshrsi3_no_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
-  "! TARGET_POWER"
-  "@
-  mr %0,%1
-  {sr|srw}%I2 %0,%1,%h2")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,y,?y")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
-   (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
-  "TARGET_POWER"
-  "@
-  sre. %3,%1,%2
-  mr. %1,%1
-  {s%A2i.|s%A2wi.} %3,%1,%h2
-  #
-  cmpli %0,%1,0
-  #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,4,4,8,8,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
-  [(parallel [(set (match_dup 3)
-		   (lshiftrt:SI (match_dup 1)
-				(match_dup 2)))
-	      (clobber (match_dup 4))])
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,y,?y")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=X,r,X,r"))]
-  "! TARGET_POWER"
-  "@
-   mr. %1,%1
-   {sr|srw}%I2. %3,%1,%h2
-   cmpli %0,%1,0
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,4,4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "! TARGET_POWER && reload_completed
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
-  [(set (match_dup 3)
-	(lshiftrt:SI (match_dup 1)
-		     (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,rOi"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(lshiftrt:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 4 "=q,X,X,q"))]
-  "TARGET_POWER"
-  "@
-  sre. %0,%1,%2
-  mr. %0,%1
-  {s%A2i.|s%A2wi.} %0,%1,%h2
-  #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,4,4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(lshiftrt:SI (match_dup 1)
-		     (match_dup 2)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 3)
-		   (lshiftrt:SI (match_dup 1)
-				(match_dup 2)))
-	      (clobber (match_dup 4))])
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(lshiftrt:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWER"
-  "@
-   mr. %0,%1
-   {sr|srw}%I2. %0,%1,%h2
-   #
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(lshiftrt:SI (match_dup 1)
-		     (match_dup 2)))]
-  "! TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(lshiftrt:SI (match_dup 1)
-		     (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			     (match_operand:SI 2 "const_int_operand" "i"))
-		(match_operand:SI 3 "mask_operand" "L")))]
-  "includes_rshift_p (operands[2], operands[3])"
-  "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:SI 2 "const_int_operand" "i,i"))
-		 (match_operand:SI 3 "mask_operand" "L,L"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=r,r"))]
-  "includes_rshift_p (operands[2], operands[3])"
-  "@
-   {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			      (match_operand:SI 2 "const_int_operand" ""))
-		 (match_operand:SI 3 "mask_operand" ""))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 ""))]
-  "reload_completed && includes_rshift_p (operands[2], operands[3])"
-  [(set (match_dup 4)
-	(and:SI (lshiftrt:SI (match_dup 1)
-			     (match_dup 2))
-		(match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:SI 2 "const_int_operand" "i,i"))
-		 (match_operand:SI 3 "mask_operand" "L,L"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "includes_rshift_p (operands[2], operands[3])"
-  "@
-   {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			      (match_operand:SI 2 "const_int_operand" ""))
-		 (match_operand:SI 3 "mask_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(and:SI (lshiftrt:SI (match_dup 1)
-			   (match_dup 2))
-		 (match_dup 3)))]
-  "reload_completed && includes_rshift_p (operands[2], operands[3])"
-  [(set (match_dup 4)
-	(and:SI (lshiftrt:SI (match_dup 1)
-			     (match_dup 2))
-		(match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(zero_extend:SI
-	 (subreg:QI
-	  (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		       (match_operand:SI 2 "const_int_operand" "i")) 0)))]
-  "includes_rshift_p (operands[2], GEN_INT (255))"
-  "{rlinm|rlwinm} %0,%1,%s2,0xff")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (zero_extend:SI
-	  (subreg:QI
-	   (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			(match_operand:SI 2 "const_int_operand" "i,i")) 0))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "includes_rshift_p (operands[2], GEN_INT (255))"
-  "@
-   {rlinm.|rlwinm.} %3,%1,%s2,0xff
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (zero_extend:SI
-	  (subreg:QI
-	   (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			(match_operand:SI 2 "const_int_operand" "")) 0))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed && includes_rshift_p (operands[2], GEN_INT (255))"
-  [(set (match_dup 3)
-	(zero_extend:SI
-	 (subreg:QI
-	  (lshiftrt:SI (match_dup 1)
-		       (match_dup 2)) 0)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (zero_extend:SI
-	  (subreg:QI
-	   (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			(match_operand:SI 2 "const_int_operand" "i,i")) 0))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
-  "includes_rshift_p (operands[2], GEN_INT (255))"
-  "@
-   {rlinm.|rlwinm.} %0,%1,%s2,0xff
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (zero_extend:SI
-	  (subreg:QI
-	   (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			(match_operand:SI 2 "const_int_operand" "")) 0))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(zero_extend:SI
-	 (subreg:QI
-	  (lshiftrt:SI (match_dup 1)
-		       (match_dup 2)) 0)))]
-  "reload_completed && includes_rshift_p (operands[2], GEN_INT (255))"
-  [(set (match_dup 0)
-	(zero_extend:SI
-	 (subreg:QI
-	  (lshiftrt:SI (match_dup 1)
-		       (match_dup 2)) 0)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(zero_extend:SI
-	 (subreg:HI
-	  (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		       (match_operand:SI 2 "const_int_operand" "i")) 0)))]
-  "includes_rshift_p (operands[2], GEN_INT (65535))"
-  "{rlinm|rlwinm} %0,%1,%s2,0xffff")
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (zero_extend:SI
-	  (subreg:HI
-	   (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			(match_operand:SI 2 "const_int_operand" "")) 0))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed && includes_rshift_p (operands[2], GEN_INT (255))"
-  [(set (match_dup 3)
-	(zero_extend:SI
-	 (subreg:HI
-	  (lshiftrt:SI (match_dup 1)
-		       (match_dup 2)) 0)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (zero_extend:SI
-	  (subreg:HI
-	   (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			(match_operand:SI 2 "const_int_operand" "i,i")) 0))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "includes_rshift_p (operands[2], GEN_INT (65535))"
-  "@
-   {rlinm.|rlwinm.} %3,%1,%s2,0xffff
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (zero_extend:SI
-	  (subreg:HI
-	   (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			(match_operand:SI 2 "const_int_operand" "i,i")) 0))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
-  "includes_rshift_p (operands[2], GEN_INT (65535))"
-  "{rlinm.|rlwinm.} %0,%1,%s2,0xffff"
-  [(set_attr "type" "delayed_compare")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (zero_extend:SI
-	  (subreg:HI
-	   (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			(match_operand:SI 2 "const_int_operand" "")) 0))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(zero_extend:SI
-	 (subreg:HI
-	  (lshiftrt:SI (match_dup 1)
-		       (match_dup 2)) 0)))]
-  "reload_completed && includes_rshift_p (operands[2], GEN_INT (255))"
-  [(set (match_dup 0)
-	(zero_extend:SI
-	 (subreg:HI
-	  (lshiftrt:SI (match_dup 1)
-		       (match_dup 2)) 0)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (const_int 1)
-			 (match_operand:SI 1 "gpc_reg_operand" "r"))
-	(ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
-		     (const_int 31)))]
-  "TARGET_POWER"
-  "rrib %0,%1,%2")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (const_int 1)
-			 (match_operand:SI 1 "gpc_reg_operand" "r"))
-	(lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
-		     (const_int 31)))]
-  "TARGET_POWER"
-  "rrib %0,%1,%2")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
-			 (const_int 1)
-			 (match_operand:SI 1 "gpc_reg_operand" "r"))
-	(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
-			 (const_int 1)
-			 (const_int 0)))]
-  "TARGET_POWER"
-  "rrib %0,%1,%2")
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		     (match_operand:SI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_POWER)
-    emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn "ashrsi3_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
-   (clobber (match_scratch:SI 3 "=q,X"))]
-  "TARGET_POWER"
-  "@
-   srea %0,%1,%2
-   {srai|srawi} %0,%1,%h2")
-
-(define_insn "ashrsi3_no_power"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
-  "! TARGET_POWER"
-  "{sra|sraw}%I2 %0,%1,%h2")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r,r,r"))
-   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
-  "TARGET_POWER"
-  "@
-   srea. %3,%1,%2
-   {srai.|srawi.} %3,%1,%h2
-   #
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 3)
-		   (ashiftrt:SI (match_dup 1)
-				(match_dup 2)))
-	      (clobber (match_dup 4))])
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "! TARGET_POWER"
-  "@
-   {sra|sraw}%I2. %3,%1,%h2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(ashiftrt:SI (match_dup 1)
-		     (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(ashiftrt:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
-  "TARGET_POWER"
-  "@
-   srea. %0,%1,%2
-   {srai.|srawi.} %0,%1,%h2
-   #
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashiftrt:SI (match_dup 1)
-		     (match_dup 2)))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
-		   (ashiftrt:SI (match_dup 1)
-				(match_dup 2)))
-	      (clobber (match_dup 4))])
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ashiftrt:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWER"
-  "@
-   {sra|sraw}%I2. %0,%1,%h2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashiftrt:SI (match_dup 1)
-		     (match_dup 2)))]
-  "! TARGET_POWER && reload_completed"
-  [(set (match_dup 0)
-	(ashiftrt:SI (match_dup 1)
-		     (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-;; Floating-point insns, excluding normal data motion.
-;;
-;; PowerPC has a full set of single-precision floating point instructions.
-;;
-;; For the POWER architecture, we pretend that we have both SFmode and
-;; DFmode insns, while, in fact, all fp insns are actually done in double.
-;; The only conversions we will do will be when storing to memory.  In that
-;; case, we will use the "frsp" instruction before storing.
-;;
-;; Note that when we store into a single-precision memory location, we need to
-;; use the frsp insn first.  If the register being stored isn't dead, we
-;; need a scratch register for the frsp.  But this is difficult when the store
-;; is done by reload.  It is not incorrect to do the frsp on the register in
-;; this case, we just lose precision that we would have otherwise gotten but
-;; is not guaranteed.  Perhaps this should be tightened up at some point.
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"\";
-  else
-    return \"fmr %0,%1\";
-}"
-  [(set_attr "type" "fp")])
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "frsp %0,%1"
-  [(set_attr "type" "fp")])
-
-(define_insn "aux_truncdfsf2"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
-  "! TARGET_POWERPC && TARGET_HARD_FLOAT"
-  "frsp %0,%1"
-  [(set_attr "type" "fp")])
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "fneg %0,%1"
-  [(set_attr "type" "fp")])
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "fabs %0,%1"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
-  "TARGET_HARD_FLOAT"
-  "fnabs %0,%1"
-  [(set_attr "type" "fp")])
-
-(define_expand "addsf3"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "")
-	(plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
-		 (match_operand:SF 2 "gpc_reg_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-		 (match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "TARGET_POWERPC && TARGET_HARD_FLOAT"
-  "fadds %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-		 (match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "! TARGET_POWERPC && TARGET_HARD_FLOAT"
-  "{fa|fadd} %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_expand "subsf3"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "")
-	(minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
-		  (match_operand:SF 2 "gpc_reg_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
-		  (match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "TARGET_POWERPC && TARGET_HARD_FLOAT"
-  "fsubs %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
-		  (match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "! TARGET_POWERPC && TARGET_HARD_FLOAT"
-  "{fs|fsub} %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_expand "mulsf3"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "")
-	(mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
-		 (match_operand:SF 2 "gpc_reg_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-		 (match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "TARGET_POWERPC && TARGET_HARD_FLOAT"
-  "fmuls %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-		 (match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "! TARGET_POWERPC && TARGET_HARD_FLOAT"
-  "{fm|fmul} %0,%1,%2"
-  [(set_attr "type" "dmul")])
-
-(define_expand "divsf3"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "")
-	(div:SF (match_operand:SF 1 "gpc_reg_operand" "")
-		(match_operand:SF 2 "gpc_reg_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
-		(match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "TARGET_POWERPC && TARGET_HARD_FLOAT"
-  "fdivs %0,%1,%2"
-  [(set_attr "type" "sdiv")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
-		(match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "! TARGET_POWERPC && TARGET_HARD_FLOAT"
-  "{fd|fdiv} %0,%1,%2"
-  [(set_attr "type" "ddiv")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-			  (match_operand:SF 2 "gpc_reg_operand" "f"))
-		 (match_operand:SF 3 "gpc_reg_operand" "f")))]
-  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "fmadds %0,%1,%2,%3"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-			  (match_operand:SF 2 "gpc_reg_operand" "f"))
-		 (match_operand:SF 3 "gpc_reg_operand" "f")))]
-  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "{fma|fmadd} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-			   (match_operand:SF 2 "gpc_reg_operand" "f"))
-		  (match_operand:SF 3 "gpc_reg_operand" "f")))]
-  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "fmsubs %0,%1,%2,%3"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-			   (match_operand:SF 2 "gpc_reg_operand" "f"))
-		  (match_operand:SF 3 "gpc_reg_operand" "f")))]
-  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "{fms|fmsub} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-				  (match_operand:SF 2 "gpc_reg_operand" "f"))
-			 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
-  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "fnmadds %0,%1,%2,%3"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-				  (match_operand:SF 2 "gpc_reg_operand" "f"))
-			 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
-  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "{fnma|fnmadd} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-				   (match_operand:SF 2 "gpc_reg_operand" "f"))
-			  (match_operand:SF 3 "gpc_reg_operand" "f"))))]
-  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "fnmsubs %0,%1,%2,%3"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
-				   (match_operand:SF 2 "gpc_reg_operand" "f"))
-			  (match_operand:SF 3 "gpc_reg_operand" "f"))))]
-  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "{fnms|fnmsub} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
-
-(define_expand "sqrtsf2"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "")
-	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
-  "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
-  "")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
-  "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
-  "fsqrts %0,%1"
-  [(set_attr "type" "ssqrt")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
-  "TARGET_POWER2 && TARGET_HARD_FLOAT"
-  "fsqrt %0,%1"
-  [(set_attr "type" "dsqrt")])
-
-;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
-;; fsel instruction and some auxiliary computations.  Then we just have a
-;; single DEFINE_INSN for fsel and the define_splits to make them if made by
-;; combine.
-(define_expand "maxsf3"
-  [(set (match_dup 3)
-	(minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
-		  (match_operand:SF 2 "gpc_reg_operand" "")))
-   (set (match_operand:SF 0 "gpc_reg_operand" "")
-	(if_then_else:SF (ge (match_dup 3)
-			     (const_int 0))
-			 (match_dup 1)
-			 (match_dup 2)))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  "
-{ operands[3] = gen_reg_rtx (SFmode); }")
-
-(define_split
-  [(set (match_operand:SF 0 "gpc_reg_operand" "")
-	(smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
-		 (match_operand:SF 2 "gpc_reg_operand" "")))
-   (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  [(set (match_dup 3)
-	(minus:SF (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(if_then_else:SF (ge (match_dup 3)
-			     (const_int 0))
-			 (match_dup 1)
-			 (match_dup 2)))]
-  "")
-
-(define_expand "minsf3"
-  [(set (match_dup 3)
-	(minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
-		  (match_operand:SF 1 "gpc_reg_operand" "")))
-   (set (match_operand:SF 0 "gpc_reg_operand" "")
-	(if_then_else:SF (ge (match_dup 3)
-			     (const_int 0))
-			 (match_dup 1)
-			 (match_dup 2)))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  "
-{ operands[3] = gen_reg_rtx (SFmode); }")
-
-(define_split
-  [(set (match_operand:SF 0 "gpc_reg_operand" "")
-	(smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
-		 (match_operand:SF 2 "gpc_reg_operand" "")))
-   (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  [(set (match_dup 3)
-	(minus:SF (match_dup 2) (match_dup 1)))
-   (set (match_dup 0)
-	(if_then_else:SF (ge (match_dup 3)
-			     (const_int 0))
-			 (match_dup 1)
-			 (match_dup 2)))]
-  "")
-
-(define_expand "movsfcc"
-   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	 (if_then_else:SF (match_operand 1 "comparison_operator" "")
-			  (match_operand:SF 2 "gpc_reg_operand" "f")
-			  (match_operand:SF 3 "gpc_reg_operand" "f")))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  "
-{
-  rtx temp, op0, op1;
-  enum rtx_code code = GET_CODE (operands[1]);
-  if (! rs6000_compare_fp_p)
-    FAIL;
-  switch (code)
-    {
-    case GE: case EQ: case NE:
-      op0 = rs6000_compare_op0;
-      op1 = rs6000_compare_op1;
-      break;
-    case GT:
-      op0 = rs6000_compare_op1;
-      op1 = rs6000_compare_op0;
-      temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
-      break;
-    case LE:
-      op0 = rs6000_compare_op1;
-      op1 = rs6000_compare_op0;
-      break;
-    case LT:
-      op0 = rs6000_compare_op0;
-      op1 = rs6000_compare_op1;
-      temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
-      break;
-    default:
-      FAIL;
-    }
-  if (GET_MODE (rs6000_compare_op0) == DFmode)
-    {
-      temp = gen_reg_rtx (DFmode);
-      emit_insn (gen_subdf3 (temp, op0, op1));
-      emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3]));
-      if (code == EQ)
-	{
-	  emit_insn (gen_negdf2 (temp, temp));
-	  emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3]));
-	}
-      else if (code == NE)
-	{
-	  emit_insn (gen_negdf2 (temp, temp));
-	  emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0]));
-	}
-    }
-  else
-    {
-      temp = gen_reg_rtx (SFmode);
-      emit_insn (gen_subsf3 (temp, op0, op1));
-      emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3]));
-      if (code == EQ)
-	{
-	  emit_insn (gen_negsf2 (temp, temp));
-	  emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3]));
-	}
-      else if (code == NE)
-	{
-	  emit_insn (gen_negsf2 (temp, temp));
-	  emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0]));
-	}
-    }
-  DONE;
-}")
-
-(define_insn "fselsfsf4"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
-			     (const_int 0))
-			 (match_operand:SF 2 "gpc_reg_operand" "f")
-			 (match_operand:SF 3 "gpc_reg_operand" "f")))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  "fsel %0,%1,%2,%3"
-  [(set_attr "type" "fp")])
-
-(define_insn "fseldfsf4"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
-	(if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
-			     (const_int 0))
-			 (match_operand:SF 2 "gpc_reg_operand" "f")
-			 (match_operand:SF 3 "gpc_reg_operand" "f")))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  "fsel %0,%1,%2,%3"
-  [(set_attr "type" "fp")])
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "fneg %0,%1"
-  [(set_attr "type" "fp")])
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "fabs %0,%1"
-  [(set_attr "type" "fp")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
-  "TARGET_HARD_FLOAT"
-  "fnabs %0,%1"
-  [(set_attr "type" "fp")])
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
-		 (match_operand:DF 2 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "{fa|fadd} %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
-		  (match_operand:DF 2 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "{fs|fsub} %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
-		 (match_operand:DF 2 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "{fm|fmul} %0,%1,%2"
-  [(set_attr "type" "dmul")])
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
-		(match_operand:DF 2 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "{fd|fdiv} %0,%1,%2"
-  [(set_attr "type" "ddiv")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
-			  (match_operand:DF 2 "gpc_reg_operand" "f"))
-		 (match_operand:DF 3 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "{fma|fmadd} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
-			   (match_operand:DF 2 "gpc_reg_operand" "f"))
-		  (match_operand:DF 3 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "{fms|fmsub} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
-				  (match_operand:DF 2 "gpc_reg_operand" "f"))
-			 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
-  "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "{fnma|fnmadd} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
-				   (match_operand:DF 2 "gpc_reg_operand" "f"))
-			  (match_operand:DF 3 "gpc_reg_operand" "f"))))]
-  "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "{fnms|fnmsub} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
-
-(define_insn "sqrtdf2"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
-  "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
-  "fsqrt %0,%1"
-  [(set_attr "type" "dsqrt")])
-
-;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
-;; fsel instruction and some auxiliary computations.  Then we just have a
-;; single DEFINE_INSN for fsel and the define_splits to make them if made by
-;; combine.
-
-(define_expand "maxdf3"
-  [(set (match_dup 3)
-	(minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
-		  (match_operand:DF 2 "gpc_reg_operand" "")))
-   (set (match_operand:DF 0 "gpc_reg_operand" "")
-	(if_then_else:DF (ge (match_dup 3)
-			     (const_int 0))
-			 (match_dup 1)
-			 (match_dup 2)))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  "
-{ operands[3] = gen_reg_rtx (DFmode); }")
-
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
-		 (match_operand:DF 2 "gpc_reg_operand" "")))
-   (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  [(set (match_dup 3)
-	(minus:DF (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(if_then_else:DF (ge (match_dup 3)
-			     (const_int 0))
-			 (match_dup 1)
-			 (match_dup 2)))]
-  "")
-
-(define_expand "mindf3"
-  [(set (match_dup 3)
-	(minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
-		  (match_operand:DF 1 "gpc_reg_operand" "")))
-   (set (match_operand:DF 0 "gpc_reg_operand" "")
-	(if_then_else:DF (ge (match_dup 3)
-			     (const_int 0))
-			 (match_dup 1)
-			 (match_dup 2)))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  "
-{ operands[3] = gen_reg_rtx (DFmode); }")
-
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
-		 (match_operand:DF 2 "gpc_reg_operand" "")))
-   (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  [(set (match_dup 3)
-	(minus:DF (match_dup 2) (match_dup 1)))
-   (set (match_dup 0)
-	(if_then_else:DF (ge (match_dup 3)
-			     (const_int 0))
-			 (match_dup 1)
-			 (match_dup 2)))]
-  "")
-
-(define_expand "movdfcc"
-   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	 (if_then_else:DF (match_operand 1 "comparison_operator" "")
-			  (match_operand:DF 2 "gpc_reg_operand" "f")
-			  (match_operand:DF 3 "gpc_reg_operand" "f")))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  "
-{
-  rtx temp, op0, op1;
-  enum rtx_code code = GET_CODE (operands[1]);
-  if (! rs6000_compare_fp_p)
-    FAIL;
-  switch (code)
-    {
-    case GE: case EQ: case NE:
-      op0 = rs6000_compare_op0;
-      op1 = rs6000_compare_op1;
-      break;
-    case GT:
-      op0 = rs6000_compare_op1;
-      op1 = rs6000_compare_op0;
-      temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
-      break;
-    case LE:
-      op0 = rs6000_compare_op1;
-      op1 = rs6000_compare_op0;
-      break;
-    case LT:
-      op0 = rs6000_compare_op0;
-      op1 = rs6000_compare_op1;
-      temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
-      break;
-    default:
-      FAIL;
-    }
-  if (GET_MODE (rs6000_compare_op0) == DFmode)
-    {
-      temp = gen_reg_rtx (DFmode);
-      emit_insn (gen_subdf3 (temp, op0, op1));
-      emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3]));
-      if (code == EQ)
-	{
-	  emit_insn (gen_negdf2 (temp, temp));
-	  emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3]));
-	}
-      else if (code == NE)
-	{
-	  emit_insn (gen_negdf2 (temp, temp));
-	  emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0]));
-	}
-    }
-  else
-    {
-      temp = gen_reg_rtx (SFmode);
-      emit_insn (gen_subsf3 (temp, op0, op1));
-      emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3]));
-      if (code == EQ)
-	{
-	  emit_insn (gen_negsf2 (temp, temp));
-	  emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3]));
-	}
-      else if (code == NE)
-	{
-	  emit_insn (gen_negsf2 (temp, temp));
-	  emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0]));
-	}
-    }
-  DONE;
-}")
-
-(define_insn "fseldfdf4"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
-			     (const_int 0))
-			 (match_operand:DF 2 "gpc_reg_operand" "f")
-			 (match_operand:DF 3 "gpc_reg_operand" "f")))]
-  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
-  "fsel %0,%1,%2,%3"
-  [(set_attr "type" "fp")])
-
-(define_insn "fselsfdf4"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
-			     (const_int 0))
-			 (match_operand:DF 2 "gpc_reg_operand" "f")
-			 (match_operand:DF 3 "gpc_reg_operand" "f")))]
-  "TARGET_PPC_GFXOPT"
-  "fsel %0,%1,%2,%3"
-  [(set_attr "type" "fp")])
-
-;; Conversions to and from floating-point.
-
-(define_expand "floatsidf2"
-  [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
-		   (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
-	      (use (match_dup 2))
-	      (use (match_dup 3))
-	      (clobber (match_dup 4))
-	      (clobber (match_dup 5))
-	      (clobber (reg:DF 76))])]
-  "TARGET_HARD_FLOAT"
-  "
-{
-  operands[2] = force_reg (SImode, GEN_INT (0x43300000));
-  operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
-  operands[4] = gen_reg_rtx (SImode);
-  operands[5] = gen_reg_rtx (Pmode);
-}")
-
-(define_insn "*floatsidf2_internal"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
-	(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
-   (use (match_operand:SI 2 "gpc_reg_operand" "r"))
-   (use (match_operand:DF 3 "gpc_reg_operand" "f"))
-   (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
-   (clobber (match_operand 5 "gpc_reg_operand" "=b"))
-   (clobber (reg:DF 76))]
-  "TARGET_HARD_FLOAT"
-  "#"
-  [(set_attr "length" "24")])
-
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
-   (use (match_operand:SI 2 "gpc_reg_operand" ""))
-   (use (match_operand:DF 3 "gpc_reg_operand" ""))
-   (clobber (match_operand:SI 4 "gpc_reg_operand" ""))
-   (clobber (match_operand 5 "gpc_reg_operand" ""))
-   (clobber (reg:DF 76))]
-  "TARGET_HARD_FLOAT"
-  [(set (match_dup 4)
-	(xor:SI (match_dup 1)
-		(match_dup 6)))
-   (set (match_dup 5)
-	(unspec [(const_int 0)] 11))
-   (set (match_dup 7)
-	(unspec [(match_dup 4)
-		 (match_dup 5)] 12))	;; low word
-   (set (match_dup 7)
-	(unspec [(match_dup 2)
-		 (match_dup 5)
-		 (match_dup 7)] 13))	;; high word
-   (set (match_dup 0)
-	(unspec [(match_dup 7)
-		 (match_dup 5)] 14))
-   (set (match_dup 0)
-	(minus:DF (match_dup 0)
-		  (match_dup 3)))]
-  "
-{
-  operands[6] = GEN_INT (0x80000000);
-  operands[7] = gen_rtx_REG (DFmode, FPMEM_REGNUM);
-}")
-
-(define_expand "floatunssidf2"
-  [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
-		   (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
-	      (use (match_dup 2))
-	      (use (match_dup 3))
-	      (clobber (match_dup 4))
-	      (clobber (reg:DF 76))])]
-  "TARGET_HARD_FLOAT"
-  "
-{
-  operands[2] = force_reg (SImode, GEN_INT (0x43300000));
-  operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
-  operands[4] = gen_reg_rtx (Pmode);
-}")
-
-(define_insn "*floatunssidf2_internal"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
-	(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
-   (use (match_operand:SI 2 "gpc_reg_operand" "r"))
-   (use (match_operand:DF 3 "gpc_reg_operand" "f"))
-   (clobber (match_operand 4 "gpc_reg_operand" "=b"))
-   (clobber (reg:DF 76))]
-  "TARGET_HARD_FLOAT"
-  "#"
-  [(set_attr "length" "20")])
-
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
-   (use (match_operand:SI 2 "gpc_reg_operand" ""))
-   (use (match_operand:DF 3 "gpc_reg_operand" ""))
-   (clobber (match_operand 4 "gpc_reg_operand" ""))
-   (clobber (reg:DF 76))]
-  "TARGET_HARD_FLOAT"
-  [(set (match_dup 4)
-	(unspec [(const_int 0)] 11))
-   (set (match_dup 5)
-	(unspec [(match_dup 1)
-		 (match_dup 4)] 12))	;; low word
-   (set (match_dup 5)
-	(unspec [(match_dup 2)
-		 (match_dup 4)
-		 (match_dup 5)] 13))	;; high word
-   (set (match_dup 0)
-	(unspec [(match_dup 5)
-		 (match_dup 4)] 14))
-   (set (match_dup 0)
-	(minus:DF (match_dup 0)
-		  (match_dup 3)))]
-  "operands[5] = gen_rtx_REG (DFmode, FPMEM_REGNUM);")
-
-;; Load up scratch register with base address + offset if needed
-(define_insn "*floatsidf2_loadaddr"
-  [(set (match_operand 0 "gpc_reg_operand" "=b")
-	(unspec [(const_int 0)] 11))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  if (rs6000_fpmem_offset > 32760)
-    {
-      rtx xop[3];
-
-      xop[0] = operands[0];
-      xop[1] = (frame_pointer_needed) ? frame_pointer_rtx : stack_pointer_rtx;
-      xop[2] = GEN_INT ((rs6000_fpmem_offset >> 16) + ((rs6000_fpmem_offset & 0x8000) >> 15));
-      output_asm_insn (\"{cau|addis} %0,%1,%2\", xop);
-    }
-
-  return \"\";
-}"
-  [(set_attr "length" "4")])
-
-(define_insn "*floatsidf2_store1"
-  [(set (reg:DF 76)
-	(unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
-		 (match_operand 1 "gpc_reg_operand" "b")] 12))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  rtx indx;
-
-  if (rs6000_fpmem_offset > 32760)
-    indx = operands[1];
-  else if (frame_pointer_needed)
-    indx = frame_pointer_rtx;
-  else
-    indx = stack_pointer_rtx;
-
-  operands[2] = gen_rtx_MEM (SImode,
-			 gen_rtx_PLUS (Pmode,
-				  indx,
-				  GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000)
-					   + ((WORDS_BIG_ENDIAN != 0) * 4))));
-
-  return \"{st|stw} %0,%2\";
-}"
-  [(set_attr "type" "store")])
-
-(define_insn "*floatsidf2_store2"
-  [(set (reg:DF 76)
-	(unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
-		 (match_operand 1 "gpc_reg_operand" "b")
-		 (reg:DF 76)] 13))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  rtx indx;
-
-  if (rs6000_fpmem_offset > 32760)
-    indx = operands[1];
-  else if (frame_pointer_needed)
-    indx = frame_pointer_rtx;
-  else
-    indx = stack_pointer_rtx;
-
-  operands[2] = gen_rtx_MEM (SImode,
-			 gen_rtx_PLUS (Pmode,
-				  indx,
-				  GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000)
-					   + ((WORDS_BIG_ENDIAN == 0) * 4))));
-
-  return \"{st|stw} %0,%2\";
-}"
-  [(set_attr "type" "store")])
-
-(define_insn "*floatsidf2_load"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(unspec [(reg:DF 76)
-		 (match_operand 1 "gpc_reg_operand" "b")] 14))]
-  "TARGET_HARD_FLOAT"
-  "*
-{
-  rtx indx;
-  HOST_WIDE_INT offset = rs6000_fpmem_offset;
-
-  if (rs6000_fpmem_offset > 32760)
-    {
-      indx = operands[1];
-      offset = (((offset & 0xffff) ^ 0x8000) - 0x8000);
-    }
-  else if (frame_pointer_needed)
-    indx = frame_pointer_rtx;
-  else
-    indx = stack_pointer_rtx;
-
-  operands[2] = gen_rtx_MEM (SImode,
-			 gen_rtx_PLUS (Pmode, indx, GEN_INT (offset)));
-
-  return \"lfd %0,%2\";
-}"
-  [(set_attr "type" "fpload")])
-
-(define_expand "fix_truncdfsi2"
-  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
-		   (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
-	      (clobber (match_dup 2))
-	      (clobber (match_dup 3))
-	      (clobber (match_dup 4))])]
-  "TARGET_HARD_FLOAT"
-  "
-{
-  if (!TARGET_POWER2 && !TARGET_POWERPC)
-    {
-      emit_insn (gen_trunc_call (operands[0], operands[1],
-				 gen_rtx_SYMBOL_REF (Pmode, RS6000_ITRUNC)));
-      DONE;
-    }
-
-  operands[2] = gen_reg_rtx (DImode);
-  operands[3] = gen_reg_rtx (Pmode);
-  operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);
-}")
-
-(define_insn "*fix_truncdfsi2_internal"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
-   (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
-   (clobber (match_operand 3 "gpc_reg_operand" "=b"))
-   (clobber (reg:DI 76))]
-  "TARGET_HARD_FLOAT"
-  "#"
-  [(set_attr "length" "12")])
-
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
-   (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
-   (clobber (match_operand 3 "gpc_reg_operand" ""))
-   (clobber (reg:DI 76))]
-  "TARGET_HARD_FLOAT"
-  [(set (match_dup 2)
-	(sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))))
-   (set (match_dup 3)
-	(unspec [(const_int 0)] 11))
-   (set (match_dup 4)
-	(unspec [(match_dup 2)
-		 (match_dup 3)] 15))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(unspec [(match_dup 4)
-		 (match_dup 3)] 16))]
-  "operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);")
-
-(define_insn "*fix_truncdfsi2_store"
-  [(set (reg:DI 76)
-	(unspec [(match_operand:DI 0 "gpc_reg_operand" "f")
-		 (match_operand 1 "gpc_reg_operand" "b")] 15))]
-  "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
-  "*
-{
-  rtx indx;
-
-  if (rs6000_fpmem_offset > 32760)
-    indx = operands[1];
-  else if (frame_pointer_needed)
-    indx = frame_pointer_rtx;
-  else
-    indx = stack_pointer_rtx;
-
-  operands[2] = gen_rtx_MEM (DFmode,
-			 gen_rtx_PLUS (Pmode,
-				  indx,
-				  GEN_INT ((((rs6000_fpmem_offset & 0xffff)
-					     ^ 0x8000) - 0x8000))));
-
-  return \"stfd %0,%2\";
-}"
-  [(set_attr "type" "fpstore")])
-
-(define_insn "*fix_truncdfsi2_load"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(unspec [(reg:DI 76)
-		 (match_operand 1 "gpc_reg_operand" "b")] 16))]
-  "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
-  "*
-{
-  rtx indx;
-
-  if (rs6000_fpmem_offset > 32760)
-    indx = operands[1];
-  else if (frame_pointer_needed)
-    indx = frame_pointer_rtx;
-  else
-    indx = stack_pointer_rtx;
-
-  operands[2] = gen_rtx_MEM (DFmode,
-			 gen_rtx_PLUS (Pmode,
-				  indx,
-				  GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000)
-					   + ((WORDS_BIG_ENDIAN) ? 4 : 0))));
-
-  return \"{l|lwz} %0,%2\";
-}"
-  [(set_attr "type" "load")])
-
-(define_expand "fixuns_truncdfsi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
-  "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT"
-  "
-{
-  emit_insn (gen_trunc_call (operands[0], operands[1],
-			     gen_rtx_SYMBOL_REF (Pmode, RS6000_UITRUNC)));
-  DONE;
-}")
-
-(define_expand "trunc_call"
-  [(parallel [(set (match_operand:SI 0 "" "")
-		   (fix:SI (match_operand:DF 1 "" "")))
-	      (use (match_operand:SI 2 "" ""))])]
-  "TARGET_HARD_FLOAT"
-  "
-{
-  rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
-  rtx first = XVECEXP (insns, 0, 0);
-  rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
-
-  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
-			       REG_NOTES (first));
-  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
-
-  emit_insn (insns);
-  DONE;
-}")
-
-(define_expand "trunc_call_rtl"
-  [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
-   (use (reg:DF 33))
-   (parallel [(set (reg:SI 3)
-		   (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
-	      (use (const_int 0))
-	      (clobber (scratch:SI))])
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(reg:SI 3))]
-  "TARGET_HARD_FLOAT"
-  "
-{
-  rs6000_trunc_used = 1;
-}")
-
-(define_insn "*fctiwz"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
-	(sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))]
-  "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
-  "{fcirz|fctiwz} %0,%1"
-  [(set_attr "type" "fp")])
-
-(define_insn "floatdidf2"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
-  "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
-  "fcfid %0,%1"
-  [(set_attr "type" "fp")])
-
-(define_insn "fix_truncdfdi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
-	(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
-  "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
-  "fctidz %0,%1"
-  [(set_attr "type" "fp")])
-
-;; Define the DImode operations that can be done in a small number
-;; of instructions.  The & constraints are to prevent the register
-;; allocator from allocating registers that overlap with the inputs
-;; (for example, having an input in 7,8 and an output in 6,7).  We
-;; also allow for the output being the same as one of the inputs.
-
-(define_insn "*adddi3_noppc64"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
-	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
-		 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
-  "! TARGET_POWERPC64"
-  "*
-{
-  if (WORDS_BIG_ENDIAN)
-    return (GET_CODE (operands[2])) != CONST_INT
-	    ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
-	    : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
-  else
-    return (GET_CODE (operands[2])) != CONST_INT
-	    ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
-	    : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
-}"
-  [(set_attr "length" "8")])
-
-(define_insn "*subdi3_noppc64"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
-	(minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
-		  (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
-  "! TARGET_POWERPC64"
-  "*
-{
-  if (WORDS_BIG_ENDIAN)
-    return (GET_CODE (operands[1]) != CONST_INT)
-	    ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
-	    : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
-  else
-    return (GET_CODE (operands[1]) != CONST_INT)
-	    ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
-	    : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
-}"
-  [(set_attr "length" "8")])
-
-(define_insn "*negdi2_noppc64"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
-	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
-  "! TARGET_POWERPC64"
-  "*
-{
-  return (WORDS_BIG_ENDIAN)
-    ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
-    : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
-}"
-  [(set_attr "length" "8")])
-
-(define_expand "mulsidi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
-  "! TARGET_POWERPC64"
-  "
-{
-  if (! TARGET_POWER && ! TARGET_POWERPC)
-    {
-      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
-      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
-      emit_insn (gen_mull_call ());
-      if (WORDS_BIG_ENDIAN)
-        emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
-      else
-	{
-	  emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
-			  gen_rtx_REG (SImode, 3));
-	  emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
-			  gen_rtx_REG (SImode, 4));
-	}
-      DONE;
-    }
-  else if (TARGET_POWER)
-    {
-      emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-(define_insn "mulsidi3_mq"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
-   (clobber (match_scratch:SI 3 "=q"))]
-  "TARGET_POWER"
-  "mul %0,%1,%2\;mfmq %L0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "8")])
-
-(define_insn "*mulsidi3_no_mq"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
-  "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
-  "*
-{
-  return (WORDS_BIG_ENDIAN)
-    ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
-    : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
-}"
-  [(set_attr "type" "imul")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
-  "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
-			       (sign_extend:DI (match_dup 2)))
-		      (const_int 32))))
-   (set (match_dup 4)
-	(mult:SI (match_dup 1)
-		 (match_dup 2)))]
-  "
-{
-  int endian = (WORDS_BIG_ENDIAN == 0);
-  operands[3] = operand_subword (operands[0], endian, 0, DImode);
-  operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
-}")
-
-(define_expand "umulsidi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
-  "TARGET_POWERPC && ! TARGET_POWERPC64"
-  "
-{
-  if (TARGET_POWER)
-    {
-      emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-(define_insn "umulsidi3_mq"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
-   (clobber (match_scratch:SI 3 "=q"))]
-  "TARGET_POWERPC && TARGET_POWER"
-  "*
-{
-  return (WORDS_BIG_ENDIAN)
-    ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
-    : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
-}"
-  [(set_attr "type" "imul")
-   (set_attr "length" "8")])
-
-(define_insn "*umulsidi3_no_mq"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
-  "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
-  "*
-{
-  return (WORDS_BIG_ENDIAN)
-    ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
-    : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
-}"
-  [(set_attr "type" "imul")
-   (set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
-  "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
-			       (zero_extend:DI (match_dup 2)))
-		      (const_int 32))))
-   (set (match_dup 4)
-	(mult:SI (match_dup 1)
-		 (match_dup 2)))]
-  "
-{
-  int endian = (WORDS_BIG_ENDIAN == 0);
-  operands[3] = operand_subword (operands[0], endian, 0, DImode);
-  operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
-}")
-
-(define_expand "smulsi3_highpart"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI
-				(match_operand:SI 1 "gpc_reg_operand" "%r"))
-			       (sign_extend:DI
-				(match_operand:SI 2 "gpc_reg_operand" "r")))
-		      (const_int 32))))]
-  ""
-  "
-{
-  if (! TARGET_POWER && ! TARGET_POWERPC)
-    {
-      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
-      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
-      emit_insn (gen_mulh_call ());
-      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
-      DONE;
-    }
-  else if (TARGET_POWER)
-    {
-      emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-(define_insn "smulsi3_highpart_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI
-				(match_operand:SI 1 "gpc_reg_operand" "%r"))
-			       (sign_extend:DI
-				(match_operand:SI 2 "gpc_reg_operand" "r")))
-		      (const_int 32))))
-   (clobber (match_scratch:SI 3 "=q"))]
-  "TARGET_POWER"
-  "mul %0,%1,%2"
-  [(set_attr "type" "imul")])
-
-(define_insn "*smulsi3_highpart_no_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI
-				(match_operand:SI 1 "gpc_reg_operand" "%r"))
-			       (sign_extend:DI
-				(match_operand:SI 2 "gpc_reg_operand" "r")))
-		      (const_int 32))))]
-  "TARGET_POWERPC && ! TARGET_POWER"
-  "mulhw %0,%1,%2"
-  [(set_attr "type" "imul")])
-
-(define_expand "umulsi3_highpart"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI
-				(match_operand:SI 1 "gpc_reg_operand" ""))
-			       (zero_extend:DI
-				(match_operand:SI 2 "gpc_reg_operand" "")))
-		      (const_int 32))))]
-  "TARGET_POWERPC"
-  "
-{
-  if (TARGET_POWER)
-    {
-      emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-(define_insn "umulsi3_highpart_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI
-				(match_operand:SI 1 "gpc_reg_operand" "%r"))
-			       (zero_extend:DI
-				(match_operand:SI 2 "gpc_reg_operand" "r")))
-		      (const_int 32))))
-   (clobber (match_scratch:SI 3 "=q"))]
-  "TARGET_POWERPC && TARGET_POWER"
-  "mulhwu %0,%1,%2"
-  [(set_attr "type" "imul")])
-
-(define_insn "*umulsi3_highpart_no_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI
-				(match_operand:SI 1 "gpc_reg_operand" "%r"))
-			       (zero_extend:DI
-				(match_operand:SI 2 "gpc_reg_operand" "r")))
-		      (const_int 32))))]
-  "TARGET_POWERPC && ! TARGET_POWER"
-  "mulhwu %0,%1,%2"
-  [(set_attr "type" "imul")])
-
-;; If operands 0 and 2 are in the same register, we have a problem.  But
-;; operands 0 and 1 (the usual case) can be in the same register.  That's
-;; why we have the strange constraints below.
-(define_insn "ashldi3_power"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
-	(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
-		   (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
-   (clobber (match_scratch:SI 3 "=X,q,q,q"))]
-  "TARGET_POWER"
-  "@
-   {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
-   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
-   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
-   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
-  [(set_attr "length" "8")])
-
-(define_insn "lshrdi3_power"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
-	(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
-   (clobber (match_scratch:SI 3 "=X,q,q,q"))]
-  "TARGET_POWER"
-  "@
-   {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
-   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
-   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
-   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
-  [(set_attr "length" "8")])
-
-;; Shift by a variable amount is too complex to be worth open-coding.  We
-;; just handle shifts by constants.
-(define_insn "ashrdi3_power"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
-	(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-		     (match_operand:SI 2 "const_int_operand" "M,i")))
-   (clobber (match_scratch:SI 3 "=X,q"))]
-  "TARGET_POWER"
-  "@
-   {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
-   sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
-  [(set_attr "length" "8")])
-
-;; PowerPC64 DImode operations.
-
-(define_expand "adddi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		 (match_operand:DI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
-{
-  if (! TARGET_POWERPC64)
-    {
-      if (non_short_cint_operand (operands[2], DImode))
-	FAIL;
-    }
-  else
-    if (GET_CODE (operands[2]) == CONST_INT
-	&& !add_operand (operands[2], DImode))
-      {
-	rtx tmp = ((reload_in_progress || reload_completed
-		    || rtx_equal_p (operands[0], operands[1]))
-		   ? operands[0] : gen_reg_rtx (DImode));
-
-	HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
-	HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
-
-	if (low & 0x8000)
-	  high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
-
-	emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (high)));
-	emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
-	DONE;
-      }
-}")
-
-;; Discourage ai/addic because of carry but provide it in an alternative
-;; allowing register zero as source.
-
-(define_insn "*adddi3_internal1"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
-	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
-		 (match_operand:DI 2 "add_operand" "r,I,I,J")))]
-  "TARGET_POWERPC64"
-  "@
-   add %0,%1,%2
-   addi %0,%1,%2
-   addic %0,%1,%2
-   addis %0,%1,%v2")
-
-(define_insn "*adddi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
-			     (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   add. %3,%1,%2
-   addic. %3,%1,%2
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			     (match_operand:DI 2 "reg_or_short_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(plus:DI (match_dup 1)
-		 (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*adddi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
-			     (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
-	(plus:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64"
-  "@
-   add. %0,%1,%2
-   addic. %0,%1,%2
-   #
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			     (match_operand:DI 2 "reg_or_short_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(plus:DI (match_dup 1)
-		 (match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(plus:DI (match_dup 1)
-		 (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-;; Split an add that we can't do in one insn into two insns, each of which
-;; does one 16-bit part.  This is used by combine.  Note that the low-order
-;; add should be last in case the result gets used in an address.
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		 (match_operand:DI 2 "non_add_cint_operand" "")))]
-  "TARGET_POWERPC64"
-  [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
-   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
-"
-{
-  HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
-  HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
-
-  if (low & 0x8000)
-    high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
-
-  operands[3] = GEN_INT (high);
-  operands[4] = GEN_INT (low);
-}")
-
-(define_insn "one_cmpldi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64"
-  "nor %0,%1,%1")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_POWERPC64"
-  "nor. %2,%1,%1"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 2)
-	(not:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(not:DI (match_dup 1)))]
-  "TARGET_POWERPC64"
-  "nor. %0,%1,%1"
-  [(set_attr "type" "compare")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(not:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(not:DI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
-		  (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
-  "TARGET_POWERPC64"
-  "@
-   subf %0,%2,%1
-   subfic %0,%2,%1")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "subf. %3,%2,%1"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			      (match_operand:DI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(minus:DI (match_dup 1)
-		  (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			      (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(minus:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64"
-  "subf. %0,%2,%1"
-  [(set_attr "type" "compare")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			      (match_operand:DI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(minus:DI (match_dup 1)
-		  (match_dup 2)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(minus:DI (match_dup 1)
-		  (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "subdi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
-		  (match_operand:DI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      emit_insn (gen_adddi3 (operands[0], operands[1],
-			     negate_rtx (DImode, operands[2])));
-      DONE;
-    }
-}")
-
-(define_insn "absdi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
-	(abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
-   (clobber (match_scratch:DI 2 "=&r,&r"))]
-  "TARGET_POWERPC64"
-  "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0"
-  [(set_attr "length" "12")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
-	(abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
-   (clobber (match_scratch:DI 2 "=&r,&r"))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
-   (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
-   (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
-	(neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
-   (clobber (match_scratch:DI 2 "=&r,&r"))]
-  "TARGET_POWERPC64"
-  "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2"
-  [(set_attr "length" "12")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
-	(neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
-   (clobber (match_scratch:DI 2 "=&r,&r"))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
-   (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
-   (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
-  "")
-
-(define_expand "negdi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64"
-  "neg %0,%1")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   neg. %2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2)
-	(neg:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(neg:DI (match_dup 1)))]
-  "TARGET_POWERPC64"
-  "@
-   neg. %0,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(neg:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(neg:DI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "ffsdi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
-	(ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64"
-  "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
-  [(set_attr "length" "16")])
-
-(define_insn "muldi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
-		 (match_operand:DI 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64"
-  "mulld %0,%1,%2"
-   [(set_attr "type" "imul")])
-
-(define_insn "smuldi3_highpart"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(truncate:DI
-	 (lshiftrt:TI (mult:TI (sign_extend:TI
-				(match_operand:DI 1 "gpc_reg_operand" "%r"))
-			       (sign_extend:TI
-				(match_operand:DI 2 "gpc_reg_operand" "r")))
-		      (const_int 64))))]
-  "TARGET_POWERPC64"
-  "mulhd %0,%1,%2"
-  [(set_attr "type" "imul")])
-
-(define_insn "umuldi3_highpart"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(truncate:DI
-	 (lshiftrt:TI (mult:TI (zero_extend:TI
-				(match_operand:DI 1 "gpc_reg_operand" "%r"))
-			       (zero_extend:TI
-				(match_operand:DI 2 "gpc_reg_operand" "r")))
-		      (const_int 64))))]
-  "TARGET_POWERPC64"
-  "mulhdu %0,%1,%2"
-  [(set_attr "type" "imul")])
-
-(define_expand "divdi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(div:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		(match_operand:DI 2 "reg_or_cint_operand" "")))]
-  "TARGET_POWERPC64"
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && exact_log2 (INTVAL (operands[2])) >= 0)
-    ;
-  else
-    operands[2] = force_reg (DImode, operands[2]);
-}")
-
-(define_expand "moddi3"
-  [(use (match_operand:DI 0 "gpc_reg_operand" ""))
-   (use (match_operand:DI 1 "gpc_reg_operand" ""))
-   (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
-  "TARGET_POWERPC64"
-  "
-{
-  int i = exact_log2 (INTVAL (operands[2]));
-  rtx temp1;
-  rtx temp2;
-
-  if (GET_CODE (operands[2]) != CONST_INT || i < 0)
-    FAIL;
-
-  temp1 = gen_reg_rtx (DImode);
-  temp2 = gen_reg_rtx (DImode);
-
-  emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
-  emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
-  emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-		(match_operand:DI 2 "const_int_operand" "N")))]
-  "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
-  "sradi %0,%1,%p2\;addze %0,%0"
-  [(set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:DI 2 "const_int_operand" "N,N"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
-  "@
-   sradi %3,%1,%p2\;addze. %3,%3
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			    (match_operand:DI 2 "const_int_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed && exact_log2 (INTVAL (operands[2])) >= 0"
-  [(set (match_dup 3)
-	(div:DI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:DI 2 "const_int_operand" "N,N"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(div:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
-  "@
-   sradi %0,%1,%p2\;addze. %0,%0
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			    (match_operand:DI 2 "const_int_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(div:DI (match_dup 1)
-		(match_dup 2)))]
-  "TARGET_POWERPC64 && reload_completed && exact_log2 (INTVAL (operands[2])) >= 0"
-  [(set (match_dup 0)
-	(div:DI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-        (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-                (match_operand:DI 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64"
-  "divd %0,%1,%2"
-  [(set_attr "type" "idiv")])
-
-(define_insn "udivdi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-        (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-                 (match_operand:DI 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64"
-  "divdu %0,%1,%2"
-  [(set_attr "type" "idiv")])
-
-(define_insn "rotldi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-		   (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
-  "TARGET_POWERPC64"
-  "rld%I2cl %0,%1,%H2,0")
-
-(define_insn "*rotldi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			       (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   rld%I2cl. %3,%1,%H2,0
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			       (match_operand:DI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(rotate:DI (match_dup 1)
-		   (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotldi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			       (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(rotate:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64"
-  "@
-   rld%I2cl. %0,%1,%H2,0
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			       (match_operand:DI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(rotate:DI (match_dup 1)
-		   (match_dup 2)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(rotate:DI (match_dup 1)
-		   (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotldi3_internal4"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-			   (match_operand:DI 2 "reg_or_cint_operand" "ri"))
-		(match_operand:DI 3 "mask64_operand" "S")))]
-  "TARGET_POWERPC64"
-  "rld%I2c%B3 %0,%1,%H2,%S3")
-
-(define_insn "*rotldi3_internal5"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (and:DI
-		     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
-		     (match_operand:DI 3 "mask64_operand" "S,S"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 4 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   rld%I2c%B3. %4,%1,%H2,%S3
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:DI
-		     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
-				(match_operand:DI 2 "reg_or_cint_operand" ""))
-		     (match_operand:DI 3 "mask64_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 4 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 4)
-	(and:DI
-	 (rotate:DI (match_dup 1)
-		    (match_dup 2))
-	 (match_dup 3)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 4)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotldi3_internal6"
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC (and:DI
-		     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
-		     (match_operand:DI 3 "mask64_operand" "S,S"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "TARGET_POWERPC64"
-  "@
-   rld%I2c%B3. %0,%1,%H2,%S3
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:DI
-		     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
-				(match_operand:DI 2 "reg_or_cint_operand" ""))
-		     (match_operand:DI 3 "mask64_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(and:DI
-	 (rotate:DI (match_dup 1)
-		    (match_dup 2))
-	 (match_dup 3)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(and:DI
-	 (rotate:DI (match_dup 1)
-		    (match_dup 2))
-	 (match_dup 3)))
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotldi3_internal7"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(zero_extend:DI
-	 (subreg:QI
-	  (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-		     (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
-  "TARGET_POWERPC64"
-  "rld%I2cl %0,%1,%H2,56")
-
-(define_insn "*rotldi3_internal8"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI
-		     (subreg:QI
-		      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   rld%I2cl. %3,%1,%H2,56
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI
-		     (subreg:QI
-		      (rotate:DI
-		       (match_operand:DI 1 "gpc_reg_operand" "")
-		       (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(zero_extend:DI
-	 (subreg:QI
-	  (rotate:DI
-	   (match_dup 1)
-	   (match_dup 2)) 0)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotldi3_internal9"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI
-		     (subreg:QI
-		      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-  "TARGET_POWERPC64"
-  "@
-   rld%I2cl. %0,%1,%H2,56
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI
-		     (subreg:QI
-		      (rotate:DI
-		       (match_operand:DI 1 "gpc_reg_operand" "")
-		       (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI
-	 (subreg:QI
-	  (rotate:DI
-	   (match_dup 1)
-	   (match_dup 2)) 0)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:DI
-	 (subreg:QI
-	  (rotate:DI
-	   (match_dup 1)
-	   (match_dup 2)) 0)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotldi3_internal10"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(zero_extend:DI
-	 (subreg:HI
-	  (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-		     (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
-  "TARGET_POWERPC64"
-  "rld%I2cl %0,%1,%H2,48")
-
-(define_insn "*rotldi3_internal11"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI
-		     (subreg:HI
-		      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   rld%I2cl. %3,%1,%H2,48
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI
-		     (subreg:HI
-		      (rotate:DI
-		       (match_operand:DI 1 "gpc_reg_operand" "")
-		       (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(zero_extend:DI
-	 (subreg:HI
-	  (rotate:DI
-	   (match_dup 1)
-	   (match_dup 2)) 0)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotldi3_internal12"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI
-		     (subreg:HI
-		      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-  "TARGET_POWERPC64"
-  "@
-   rld%I2cl. %0,%1,%H2,48
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI
-		     (subreg:HI
-		      (rotate:DI
-		       (match_operand:DI 1 "gpc_reg_operand" "")
-		       (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI
-	 (subreg:HI
-	  (rotate:DI
-	   (match_dup 1)
-	   (match_dup 2)) 0)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:DI
-	 (subreg:QI
-	  (rotate:DI
-	   (match_dup 1)
-	   (match_dup 2)) 0)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotldi3_internal13"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(zero_extend:DI
-	 (subreg:SI
-	  (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-		     (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
-  "TARGET_POWERPC64"
-  "rld%I2cl %0,%1,%H2,32")
-
-(define_insn "*rotldi3_internal14"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI
-		     (subreg:SI
-		      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   rld%I2cl. %3,%1,%H2,32
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI
-		     (subreg:SI
-		      (rotate:DI
-		       (match_operand:DI 1 "gpc_reg_operand" "")
-		       (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(zero_extend:DI
-	 (subreg:SI
-	  (rotate:DI
-	   (match_dup 1)
-	   (match_dup 2)) 0)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*rotldi3_internal15"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (zero_extend:DI
-		     (subreg:SI
-		      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
-  "TARGET_POWERPC64"
-  "@
-   rld%I2cl. %0,%1,%H2,32
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (zero_extend:DI
-		     (subreg:SI
-		      (rotate:DI
-		       (match_operand:DI 1 "gpc_reg_operand" "")
-		       (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(zero_extend:DI
-	 (subreg:SI
-	  (rotate:DI
-	   (match_dup 1)
-	   (match_dup 2)) 0)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(zero_extend:DI
-	 (subreg:QI
-	  (rotate:DI
-	   (match_dup 1)
-	   (match_dup 2)) 0)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "ashldi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		   (match_operand:SI 2 "reg_or_cint_operand" "")))]
-  "TARGET_POWERPC64 || TARGET_POWER"
-  "
-{
-  if (TARGET_POWERPC64)
-    ;
-  else if (TARGET_POWER)
-    {
-      emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-  else
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-		   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
-  "TARGET_POWERPC64"
-  "sld%I2 %0,%1,%H2"
-  [(set_attr "length" "8")])
-  
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   sld%I2. %3,%1,%H2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			       (match_operand:DI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(ashift:DI (match_dup 1)
-		   (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(ashift:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64"
-  "@
-   sld%I2. %0,%1,%H2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			       (match_operand:DI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ashift:DI (match_dup 1)
-		   (match_dup 2)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(ashift:DI (match_dup 1)
-		   (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "lshrdi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		     (match_operand:SI 2 "reg_or_cint_operand" "")))]
-  "TARGET_POWERPC64 || TARGET_POWER"
-  "
-{
-  if (TARGET_POWERPC64)
-    ;
-  else if (TARGET_POWER)
-    {
-      emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-  else
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
-  "TARGET_POWERPC64"
-  "srd%I2 %0,%1,%H2")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   srd%I2. %3,%1,%H2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
-				 (match_operand:DI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(lshiftrt:DI (match_dup 1)
-		     (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(lshiftrt:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64"
-  "@
-   srd%I2. %0,%1,%H2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
-				 (match_operand:DI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(lshiftrt:DI (match_dup 1)
-		     (match_dup 2)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(lshiftrt:DI (match_dup 1)
-		     (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "ashrdi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		     (match_operand:SI 2 "reg_or_cint_operand" "")))]
-  "TARGET_POWERPC64 || TARGET_POWER"
-  "
-{
-  if (TARGET_POWERPC64)
-    ;
-  else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
-    {
-      emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-  else
-    FAIL;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
-  "TARGET_POWERPC64"
-  "srad%I2 %0,%1,%H2")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   srad%I2. %3,%1,%H2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
-				 (match_operand:DI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(ashiftrt:DI (match_dup 1)
-		     (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(ashiftrt:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64"
-  "@
-   srad%I2. %0,%1,%H2
-   #"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
-				 (match_operand:DI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ashiftrt (match_dup 1)
-		  (match_dup 2)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(ashiftrt (match_dup 1)
-		  (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "anddi3"
-  [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
-		   (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
-			   (match_operand:DI 2 "and_operand" "?r,L,K,J")))
-	      (clobber (match_scratch:CC 3 "=X,X,x,x"))])]
-  "TARGET_POWERPC64"
-  "")
-
-;; If cr0 isn't available, and we want to do an andi, load the register into
-;; the destination first.
-
-(define_insn "anddi3_internal1"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,&??r,&??r")
-	(and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
-		(match_operand:DI 2 "and_operand" "?r,L,K,J,K,J")))
-   (clobber (match_operand:CC 3 "scratch_operand" "=X,X,x,x,X,X"))]
-  "TARGET_POWERPC64"
-  "@
-   and %0,%1,%2
-   {rlinm|rlwinm} %0,%1,0,%m2,%M2
-   andil %0,%1,%b2
-   andis. %0,%1,%u2
-   #
-   #"
-  [(set_attr "length" "4,4,4,4,8,8")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(and:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		(match_operand:DI 2 "const_int_operand" "")))
-   (clobber (scratch:CC))]
-  "TARGET_POWERPC64 && reload_completed && !mask_constant (INTVAL (operands[2]))"
-  [(set (match_dup 0)
-	(match_dup 2))
-   (parallel [(set (match_dup 0)
-		   (and:DI (match_dup 0)
-			   (match_dup 1)))
-	      (clobber (scratch:CC))])]
-  "")
-
-;; Note to set cr's other than cr0 we do the and immediate and then
-;; the test again -- this avoids a mcrf which on the higher end
-;; machines causes an execution serialization
-
-(define_insn "*anddi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y,???y,???y")
-	(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
-			    (match_operand:DI 2 "and_operand" "r,K,J,L,r,K,J,L,K,L"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,&r,&r"))
-   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))]
-  "TARGET_POWERPC64"
-  "@
-   and. %3,%1,%2
-   {andil.|andi.} %3,%1,%b2
-   {andiu.|andis.} %3,%1,%u2
-   {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
-   #
-   #
-   #
-   #
-   #
-   #"
-  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")
-   (set_attr "length" "4,4,4,4,8,8,8,8,12,12")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			    (match_operand:DI 2 "and_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))
-   (clobber (match_scratch:CC 4 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(parallel [(set (match_dup 3)
-		   (and:DI (match_dup 1)
-			   (match_dup 2)))
-	      (clobber (match_dup 4))])
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*anddi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y,???y,???y")
-	(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
-			    (match_operand:DI 2 "and_operand" "r,K,J,L,r,K,J,L,K,J"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,&r,&r")
-	(and:DI (match_dup 1)
-		(match_dup 2)))
-   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))]
-  "TARGET_POWERPC64"
-  "@
-   and. %0,%1,%2
-   andi. %0,%1,%b2
-   andis. %0,%1,%u2
-   rldic%B2 %0,%1,0,%m2,%M2
-   #
-   #
-   #
-   #
-   #
-   #"
-  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")
-   (set_attr "length" "4,4,4,4,8,8,8,8,12,12")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			    (match_operand:DI 2 "and_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(and:DI (match_dup 1)
-		(match_dup 2)))
-   (clobber (match_scratch:CC 4 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(parallel [(set (match_dup 0)
-		   (and:DI (match_dup 1)
-			   (match_dup 2)))
-	      (clobber (match_dup 4))])
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_expand "iordi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		(match_operand:DI 2 "reg_or_cint_operand" "")))]
-  "TARGET_POWERPC64"
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && !logical_operand (operands[2], DImode))
-    {
-      HOST_WIDE_INT value = INTVAL (operands[2]);
-      rtx tmp = ((reload_in_progress || reload_completed
-		  || rtx_equal_p (operands[0], operands[1]))
-		 ? operands[0] : gen_reg_rtx (DImode));
-
-      emit_insn (gen_iordi3 (tmp, operands[1],
-			     GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
-      emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
-      DONE;
-    }
-}")
-
-(define_insn "*iordi3_internal1"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
-	(ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
-		(match_operand:DI 2 "logical_operand" "r,K,J")))]
-  "TARGET_POWERPC64"
-  "@
-   or %0,%1,%2
-   ori %0,%1,%b2
-   oris %0,%1,%u2")
-
-(define_insn "*iordi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   or. %3,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			    (match_operand:DI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(ior:DI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*iordi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(ior:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64"
-  "@
-   or. %0,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			    (match_operand:DI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ior:DI (match_dup 1) (match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(ior:DI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-;; Split an IOR that we can't do in one insn into two insns, each of which
-;; does one 16-bit part.  This is used by combine.
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		(match_operand:DI 2 "non_logical_cint_operand" "")))]
-  "TARGET_POWERPC64"
-  [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3)))
-   (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))]
-"
-{
-  operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
-  operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
-}")
-
-(define_expand "xordi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		(match_operand:DI 2 "reg_or_cint_operand" "")))]
-  "TARGET_POWERPC64"
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && !logical_operand (operands[2], DImode))
-    {
-      HOST_WIDE_INT value = INTVAL (operands[2]);
-      rtx tmp = ((reload_in_progress || reload_completed
-		  || rtx_equal_p (operands[0], operands[1]))
-		 ? operands[0] : gen_reg_rtx (DImode));
-
-      emit_insn (gen_xordi3 (tmp, operands[1],
-			     GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
-      emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
-      DONE;
-    }
-}")
-
-(define_insn "*xordi3_internal1"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
-	(xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
-		(match_operand:DI 2 "logical_operand" "r,K,J")))]
-  "TARGET_POWERPC64"
-  "@
-   xor %0,%1,%2
-   xori %0,%1,%b2
-   xoris %0,%1,%u2")
-
-(define_insn "*xordi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   xor. %3,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			    (match_operand:DI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(xor:DI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*xordi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(xor:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64"
-  "@
-   xor. %0,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			    (match_operand:DI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(xor:DI (match_dup 1) (match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(xor:DI (match_dup 1)
-		(match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-;; Split an XOR that we can't do in one insn into two insns, each of which
-;; does one 16-bit part.  This is used by combine.
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-        (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
-                (match_operand:DI 2 "non_logical_cint_operand" "")))]
-  "TARGET_POWERPC64"
-  [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3)))
-   (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))]
-"
-{
-  operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
-  operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
-}")
-
-(define_insn "*eqvdi3_internal1"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
-			(match_operand:DI 2 "gpc_reg_operand" "r"))))]
-   "TARGET_POWERPC64"
-   "eqv %0,%1,%2")
-
-(define_insn "*eqvdi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				    (match_operand:DI 2 "gpc_reg_operand" "r,r")))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-   "TARGET_POWERPC64"
-   "@
-    eqv. %3,%1,%2
-    #"
-   [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
-				    (match_operand:DI 2 "gpc_reg_operand" "")))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(not:DI (xor:DI (match_dup 1)
-			(match_dup 2))))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*eqvdi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-				    (match_operand:DI 2 "gpc_reg_operand" "r,r")))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(not:DI (xor:DI (match_dup 1) (match_dup 2))))]
-   "TARGET_POWERPC64"
-   "@
-    eqv. %0,%1,%2
-    #"
-   [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
-				    (match_operand:DI 2 "reg_or_short_operand" "")))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(not:DI (xor:DI (match_dup 1)
-			(match_dup 2))))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(not:DI (xor:DI (match_dup 1)
-			(match_dup 2))))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*andcdi3_internal1"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
-		(match_operand:DI 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64"
-  "andc %0,%2,%1")
-
-(define_insn "*andcdi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-			    (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   andc. %3,%2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-			    (match_operand:DI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(and:DI (not:DI (match_dup 1))
-		(match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*andcdi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-			    (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(and:DI (not:DI (match_dup 1)) (match_dup 2)))]
-  "TARGET_POWERPC64"
-  "@
-   andc. %0,%2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-			    (match_operand:DI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(and:DI (not:DI (match_dup 1))
-		(match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(and:DI (not:DI (match_dup 1))
-		(match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*iorcdi3_internal1"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
-		(match_operand:DI 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64"
-  "orc %0,%2,%1")
-
-(define_insn "*iorcdi3_inernal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-			    (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   orc. %3,%2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-			    (match_operand:DI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(ior:DI (not:DI (match_dup 1))
-		(match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*iorcdi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-			    (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(ior:DI (not:DI (match_dup 1)) (match_dup 2)))]
-  "TARGET_POWERPC64"
-  "@
-   orc. %0,%2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-			    (match_operand:DI 2 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ior:DI (not:DI (match_dup 1))
-		(match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(ior:DI (not:DI (match_dup 1))
-		(match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*nanddi3_internal1"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
-		(not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
-  "TARGET_POWERPC64"
-  "nand %0,%1,%2")
-
-(define_insn "*nanddi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-			    (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r")))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   nand. %3,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-			    (not:DI (match_operand:DI 2 "gpc_reg_operand" "")))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(ior:DI (not:DI (match_dup 1))
-		(not:DI (match_dup 2))))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*nanddi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-			    (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r")))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
-  "TARGET_POWERPC64"
-  "@
-   nand. %0,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-			    (not:DI (match_operand:DI 2 "gpc_reg_operand" "")))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ior:DI (not:DI (match_dup 1))
-		(not:DI (match_dup 2))))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(ior:DI (not:DI (match_dup 1))
-		(not:DI (match_dup 2))))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*nordi3_internal1"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
-		(not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
-  "TARGET_POWERPC64"
-  "nor %0,%1,%2")
-
-(define_insn "*nordi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-			    (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r")))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   nor. %3,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-			    (not:DI (match_operand:DI 2 "gpc_reg_operand" "")))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(and:DI (not:DI (match_dup 1))
-		(not:DI (match_dup 2))))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*nordi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-			    (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r")))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
-  "TARGET_POWERPC64"
-  "@
-   nor. %0,%1,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-			    (not:DI (match_operand:DI 2 "gpc_reg_operand" "")))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(and:DI (not:DI (match_dup 1))
-		(not:DI (match_dup 2))))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(and:DI (not:DI (match_dup 1))
-		(not:DI (match_dup 2))))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-
-;; Now define ways of moving data around.
-
-;; Elf specific ways of loading addresses for non-PIC code.
-;; The output of this could be r0, but we limit it to base
-;; registers, since almost all uses of this will need it
-;; in a base register shortly.
-(define_insn "elf_high"
-  [(set (match_operand:SI 0 "register_operand" "=b")
-	(high:SI (match_operand 1 "" "")))]
-  "TARGET_ELF && !TARGET_64BIT"
-  "{liu|lis} %0,%1@ha")
-
-(define_insn "elf_low"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lo_sum:SI (match_operand:SI 1 "register_operand" "b")
-		   (match_operand 2 "" "")))]
-   "TARGET_ELF && !TARGET_64BIT"
-   "{cal|la} %0,%2@l(%1)")
-
-;; Set up a register with a value from the GOT table
-
-(define_expand "movsi_got"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(unspec [(match_operand:SI 1 "got_operand" "")
-		 (match_dup 2)] 8))]
-  "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
-  "
-{
-  if (GET_CODE (operands[1]) == CONST)
-    {
-      rtx offset = const0_rtx;
-      HOST_WIDE_INT value;
-
-      operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
-      value = INTVAL (offset);
-      if (value != 0)
-	{
-	  rtx tmp = ((reload_in_progress || reload_completed)
-		     ? operands[0]
-		     : gen_reg_rtx (Pmode));
-	  emit_insn (gen_movsi_got (tmp, operands[1]));
-	  emit_insn (gen_addsi3 (operands[0], tmp, offset));
-	  DONE;
-	}
-    }
-
-  operands[2] = rs6000_got_register (operands[1]);
-}")
-
-(define_insn "*movsi_got_internal"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(unspec [(match_operand:SI 1 "got_no_const_operand" "")
-		 (match_operand:SI 2 "register_operand" "b")] 8))]
-  "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
-  "{l|lwz} %0,%a1@got(%2)"
-  [(set_attr "type" "load")])
-
-;; Sometimes, though, the GOT `register' will be on the stack. Deal with
-;; this case specially.
-;; Force final to split this insn (if it hasn't been split already) to
-;; avoid having to create a suitable output template.
-(define_insn "*movsi_got_internal_mem"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(unspec [(match_operand:SI 1 "got_no_const_operand" "")
-		 (match_operand:SI 2 "memory_operand" "m")] 8))]
-  "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-    && flag_pic == 1
-    && (reload_in_progress || reload_completed)"
-  "#"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
-;; Used by sched, shorten_branches and final when the GOT pseudo reg
-;; didn't get allocated to a hard register.
-(define_split 
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(unspec [(match_operand:SI 1 "got_no_const_operand" "")
-		 (match_operand:SI 2 "memory_operand" "m")] 8))]
-  "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-    && flag_pic == 1
-    && (reload_in_progress || reload_completed)"
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (unspec [(match_dup 1)(match_dup 0)] 8))]
-  "")
-
-;; For SI, we special-case integers that can't be loaded in one insn.  We
-;; do the load 16-bits at a time.  We could do this by loading from memory,
-;; and this is even supposed to be faster, but it is simpler not to get
-;; integers in the TOC.
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "any_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) != REG)
-    operands[1] = force_reg (SImode, operands[1]);
-
-  /* Convert a move of a CONST_DOUBLE into a CONST_INT */
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-
-  /* Use default pattern for address of ELF small data */
-  if (TARGET_ELF
-      && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-      && (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
-      && small_data_operand (operands[1], SImode))
-    {
-      emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
-      DONE;
-    }
-
-  if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-      && flag_pic == 1 && got_operand (operands[1], SImode))
-    {
-      emit_insn (gen_movsi_got (operands[0], operands[1]));
-      DONE;
-    }
-
-  if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT
-      && !flag_pic
-      && CONSTANT_P (operands[1])
-      && GET_CODE (operands[1]) != HIGH
-      && GET_CODE (operands[1]) != CONST_INT
-      && GET_CODE (operands[1]) != CONSTANT_P_RTX)
-    {
-      rtx target = (reload_completed || reload_in_progress)
-			? operands[0] : gen_reg_rtx (SImode);
-
-      /* If this is a function address on -mcall-aixdesc or -mcall-nt,
-	 convert it to the address of the descriptor.  */
-      if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
-	  && GET_CODE (operands[1]) == SYMBOL_REF
-	  && XSTR (operands[1], 0)[0] == '.')
-	{
-	  char *name = XSTR (operands[1], 0);
-	  rtx new_ref;
-	  while (*name == '.')
-	    name++;
-	  new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
-	  CONSTANT_POOL_ADDRESS_P (new_ref) = CONSTANT_POOL_ADDRESS_P (operands[1]);
-	  SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]);
-	  SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
-	  operands[1] = new_ref;
-	}
-
-      emit_insn (gen_elf_high (target, operands[1]));
-      emit_insn (gen_elf_low (operands[0], target, operands[1]));
-      DONE;
-    }
-
-  if (GET_CODE (operands[1]) == CONST
-      && DEFAULT_ABI == ABI_NT
-      && !side_effects_p (operands[0]))
-    {
-      rtx const_term = const0_rtx;
-      rtx sym = eliminate_constant_term (XEXP (operands[1], 0), &const_term);
-      if (sym && GET_CODE (const_term) == CONST_INT
-	  && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF))
-	{
-	  unsigned HOST_WIDE_INT value = INTVAL (const_term);
-	  int new_reg_p = (flag_expensive_optimizations
-			   && !reload_completed
-			   && !reload_in_progress);
-	  rtx tmp1 = (new_reg_p && value != 0) ? gen_reg_rtx (SImode) : operands[0];
-
-	  emit_insn (gen_movsi (tmp1, sym));
-	  if (INTVAL (const_term) != 0)
-	    emit_insn (gen_addsi3 (operands[0], tmp1, GEN_INT (value)));
-	  DONE;
-	}
-      else
-	rs6000_fatal_bad_address (operands[1]);
-    }
-
-  if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT)
-      && CONSTANT_P (operands[1])
-      && GET_CODE (operands[1]) != CONST_INT
-      && GET_CODE (operands[1]) != CONSTANT_P_RTX
-      && GET_CODE (operands[1]) != HIGH
-      && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
-    {
-      /* Emit a USE operation so that the constant isn't deleted if
-	 expensive optimizations are turned on because nobody
-	 references it.  This should only be done for operands that
-	 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
-	 This should not be done for operands that contain LABEL_REFs.
-	 For now, we just handle the obvious case.  */
-      if (GET_CODE (operands[1]) != LABEL_REF)
-	emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
-
-      /* If we are to limit the number of things we put in the TOC and
-	 this is a symbol plus a constant we can add in one insn,
-	 just put the symbol in the TOC and add the constant.  Don't do
-	 this if reload is in progress.  */
-      if (GET_CODE (operands[1]) == CONST
-	  && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
-	  && GET_CODE (XEXP (operands[1], 0)) == PLUS
-	  && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode)
-	  && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
-	      || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
-	  && ! side_effects_p (operands[0]))
-	{
-	  rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0));
-	  rtx other = XEXP (XEXP (operands[1], 0), 1);
-
-	  emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other));
-	  DONE;
-	}
-
-      operands[1] = force_const_mem (SImode, operands[1]);
-      if (! memory_address_p (SImode, XEXP (operands[1], 0))
-	  && ! reload_in_progress)
-	operands[1] = change_address (operands[1], SImode,
-				      XEXP (operands[1], 0));
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
-	(match_operand:SI 1 "input_operand" "r,U,m,r,I,J,n,R,*h,r,r,0"))]
-  "gpc_reg_operand (operands[0], SImode)
-   || gpc_reg_operand (operands[1], SImode)"
-  "@
-   mr %0,%1
-   {cal|la} %0,%a1
-   {l%U1%X1|lwz%U1%X1} %0,%1
-   {st%U0%X0|stw%U0%X0} %1,%0
-   {lil|li} %0,%1
-   {liu|lis} %0,%v1
-   #
-   {cal|la} %0,%1(%*)
-   mf%1 %0
-   mt%0 %1
-   mt%0 %1
-   cror 0,0,0"
-  [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*")
-   (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")])
-
-;; Split a load of a large constant into the appropriate two-insn
-;; sequence.
-
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(match_operand:SI 1 "const_int_operand" ""))]
-  "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
-   && (INTVAL (operands[1]) & 0xffff) != 0"
-  [(set (match_dup 0)
-	(match_dup 2))
-   (set (match_dup 0)
-	(ior:SI (match_dup 0)
-		(match_dup 3)))]
-  "
-{
-  operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
-  operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
-}")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
-  ""
-  "@
-  mr. %0,%1
-  #"
-  [(set_attr "type" "compare")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(match_dup 1))]
-  "reload_completed && rtx_equal_p (operands[0], operands[1])"
-  [(set (match_dup 2)
-	(compare:CC (match_dup 1)
-		    (const_int 0)))]
-  "")
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(match_dup 1))]
-  "reload_completed && !rtx_equal_p (operands[0], operands[1])"
-  [(set (match_dup 2)
-	(compare:CC (match_dup 1)
-		    (const_int 0)))
-   (set (match_dup 0)
-	(match_dup 1))]
-  "")
-
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "any_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) != REG)
-    operands[1] = force_reg (HImode, operands[1]);
-
-  if (CONSTANT_P (operands[1])
-      && GET_CODE (operands[1]) != CONST_INT
-      && GET_CODE (operands[1]) != CONSTANT_P_RTX)
-    {
-      operands[1] = force_const_mem (HImode, operands[1]);
-      if (! memory_address_p (HImode, XEXP (operands[1], 0))
-	  && ! reload_in_progress)
-	operands[1] = change_address (operands[1], HImode,
-				      XEXP (operands[1], 0));
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
-	(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
-  "gpc_reg_operand (operands[0], HImode)
-   || gpc_reg_operand (operands[1], HImode)"
-  "@
-   mr %0,%1
-   lhz%U1%X1 %0,%1
-   sth%U0%X0 %1,%0
-   {lil|li} %0,%w1
-   mf%1 %0
-   mt%0 %1
-   mt%0 %1
-   cror 0,0,0"
-  [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "any_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) != REG)
-    operands[1] = force_reg (QImode, operands[1]);
-
-  if (CONSTANT_P (operands[1])
-      && GET_CODE (operands[1]) != CONST_INT
-      && GET_CODE (operands[1]) != CONSTANT_P_RTX)
-    {
-      operands[1] = force_const_mem (QImode, operands[1]);
-      if (! memory_address_p (QImode, XEXP (operands[1], 0))
-	  && ! reload_in_progress)
-	operands[1] = change_address (operands[1], QImode,
-				      XEXP (operands[1], 0));
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
-	(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
-  "gpc_reg_operand (operands[0], QImode)
-   || gpc_reg_operand (operands[1], QImode)"
-  "@
-   mr %0,%1
-   lbz%U1%X1 %0,%1
-   stb%U0%X0 %1,%0
-   {lil|li} %0,%1
-   mf%1 %0
-   mt%0 %1
-   mt%0 %1
-   cror 0,0,0"
-  [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
-
-;; Here is how to move condition codes around.  When we store CC data in
-;; an integer register or memory, we store just the high-order 4 bits.
-;; This lets us not shift in the most common case of CR0.
-(define_expand "movcc"
-  [(set (match_operand:CC 0 "nonimmediate_operand" "")
-	(match_operand:CC 1 "nonimmediate_operand" ""))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
-	(match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
-  "register_operand (operands[0], CCmode)
-   || register_operand (operands[1], CCmode)"
-  "@
-   mcrf %0,%1
-   mtcrf 128,%1
-   {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
-   mfcr %0
-   mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
-   mr %0,%1
-   {l%U1%X1|lwz%U1%X1} %0,%1
-   {st%U0%U1|stw%U0%U1} %1,%0"
-  [(set_attr "type" "*,*,*,compare,*,*,load,store")
-   (set_attr "length" "*,*,12,*,8,*,*,*")])
-
-;; For floating-point, we normally deal with the floating-point registers
-;; unless -msoft-float is used.  The sole exception is that parameter passing
-;; can produce floating-point values in fixed-point registers.  Unless the
-;; value is a simple constant or already in memory, we deal with this by
-;; allocating memory and copying the value explicitly via that memory location.
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "")
-	(match_operand:SF 1 "any_operand" ""))]
-  ""
-  "
-{
-  /* If we are called from reload, we might be getting a SUBREG of a hard
-     reg.  So expand it.  */
-  if (GET_CODE (operands[0]) == SUBREG
-      && GET_CODE (SUBREG_REG (operands[0])) == REG
-      && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
-    operands[0] = alter_subreg (operands[0]);
-  if (GET_CODE (operands[1]) == SUBREG
-      && GET_CODE (SUBREG_REG (operands[1])) == REG
-      && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
-    operands[1] = alter_subreg (operands[1]);
-
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      /* If operands[1] is a register, it may have double-precision data
-	 in it, so truncate it to single precision.  We need not do
-	 this for POWERPC.  */
-      if (! TARGET_POWERPC && TARGET_HARD_FLOAT
-	  && GET_CODE (operands[1]) == REG
-	  && (FP_REGNO_P (REGNO (operands[1]))
-	      || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
-	{
-	  rtx newreg
-	    = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
-	  emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
-	  operands[1] = newreg;
-	}
-
-      operands[1] = force_reg (SFmode, operands[1]);
-    }
-
-  if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT)
-    {
-      operands[1] = force_const_mem (SFmode, operands[1]);
-      if (! memory_address_p (SFmode, XEXP (operands[1], 0))
-	  && ! reload_in_progress)
-	operands[1] = change_address (operands[1], SFmode,
-				      XEXP (operands[1], 0));
-    }
-}")
-
-(define_split
-  [(set (match_operand:SF 0 "gpc_reg_operand" "")
-	(match_operand:SF 1 "const_double_operand" ""))]
-  "reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
-	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
-  [(set (match_dup 2) (match_dup 3))]
-  "
-{
-  long l;
-  REAL_VALUE_TYPE rv;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-  REAL_VALUE_TO_TARGET_SINGLE (rv, l);
-
-  if (! TARGET_POWERPC64)
-    operands[2] = operand_subword (operands[0], 0, 0, SFmode);
-  else
-    operands[2] = gen_lowpart (SImode, operands[0]);
-
-  operands[3] = GEN_INT(l);
-}")
-
-(define_insn "*movsf_hardfloat"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r")
-	(match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))]
-  "(gpc_reg_operand (operands[0], SFmode)
-   || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
-  "@
-   mr %0,%1
-   {l%U1%X1|lwz%U1%X1} %0,%1
-   {st%U0%X0|stw%U0%X0} %1,%0
-   fmr %0,%1
-   lfs%U1%X1 %0,%1
-   stfs%U0%X0 %1,%0
-   #
-   #"
-  [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*")
-   (set_attr "length" "4,4,4,4,4,4,4,8")])
-
-(define_insn "*movsf_softfloat"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
-	(match_operand:SF 1 "input_operand" "r,m,r,I,J,R,G,Fn"))]
-  "(gpc_reg_operand (operands[0], SFmode)
-   || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
-  "@
-   mr %0,%1
-   {l%U1%X1|lwz%U1%X1} %0,%1
-   {st%U0%X0|stw%U0%X0} %1,%0
-   {lil|li} %0,%1
-   {liu|lis} %0,%v1
-   {cal|la} %0,%1(%*)
-   #
-   #"
-  [(set_attr "type" "*,load,store,*,*,*,*,*")
-   (set_attr "length" "4,4,4,4,4,4,4,8")])
-
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "")
-	(match_operand:DF 1 "any_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) != REG)
-    operands[1] = force_reg (DFmode, operands[1]);
-
-  if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode))
-    {
-      operands[1] = force_const_mem (DFmode, operands[1]);
-      if (! memory_address_p (DFmode, XEXP (operands[1], 0))
-	  && ! reload_in_progress)
-	operands[1] = change_address (operands[1], DFmode,
-				      XEXP (operands[1], 0));
-    }
-}")
-
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(match_operand:DF 1 "const_int_operand" ""))]
-  "! TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
-	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
-  [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (match_dup 1))]
-  "
-{
-  int endian = (WORDS_BIG_ENDIAN == 0);
-  operands[2] = operand_subword (operands[0], endian, 0, DFmode);
-  operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
-  operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
-}")
-
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(match_operand:DF 1 "const_double_operand" ""))]
-  "! TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
-	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
-  [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (match_dup 5))]
-  "
-{
-  int endian = (WORDS_BIG_ENDIAN == 0);
-  long l[2];
-  REAL_VALUE_TYPE rv;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-  REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
-
-  operands[2] = operand_subword (operands[0], endian, 0, DFmode);
-  operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
-  operands[4] = GEN_INT (l[endian]);
-  operands[5] = GEN_INT (l[1 - endian]);
-}")
-
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(match_operand:DF 1 "easy_fp_constant" ""))]
-  "TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
-	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
-  [(set (match_dup 2) (match_dup 3))]
-  "
-{
-  int endian = (WORDS_BIG_ENDIAN == 0);
-  long l[2];
-  REAL_VALUE_TYPE rv;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-  REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
-
-  operands[2] = gen_lowpart (DImode, operands[0]);
-  /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN.  */
-  operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
-}")
-
-;; Don't have reload use general registers to load a constant.  First,
-;; it might not work if the output operand is the equivalent of
-;; a non-offsettable memref, but also it is less efficient than loading
-;; the constant into an FP register, since it will probably be used there.
-;; The "??" is a kludge until we can figure out a more reasonable way
-;; of handling these non-offsettable values.
-;; CYGNUS LOCAL -- meissner/add non-offsetable load
-(define_insn "*movdf_hardfloat32"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,&????r,o,!r,!r,!r,f,f,m")
-	(match_operand:DF 1 "input_operand" "r,o,m,r,G,H,F,f,m,f"))]
-  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    default:
-      abort ();
-    case 0:
-      /* We normally copy the low-numbered register first.  However, if
-	 the first register operand 0 is the same as the second register of
-	 operand 1, we must copy in the opposite order.  */
-      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
-	return \"mr %L0,%L1\;mr %0,%1\";
-      else
-	return \"mr %0,%1\;mr %L0,%L1\";
-    case 1:
-      /* If the low-address word is used in the address, we must load it
-	 last.  Otherwise, load it first.  Note that we cannot have
-	 auto-increment in that case since the address register is known to be
-	 dead.  */
-      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			     operands [1], 0))
-	return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
-      else
-	return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
-      /* We don't have an offsetable address for the load, use the bottom register
-         being loaded to hold the address.  */
-    case 2:
-      {
-	rtx addr = XEXP (operands[1], 0);
-
-        if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
-	    && GET_CODE (XEXP (addr, 0)) == REG)
-	  {
-	    rtx left = XEXP (addr, 0);
-	    rtx right = XEXP (addr, 1);
-
-	    operands[2] = left;
-	    operands[3] = right;
-
-	    if (GET_CODE (right) == REG)
-	      return \"{cax|add} %L0,%2,%3\;{l|lwz} %0,0(%L0)\;{l|lwz} %L0,4(%L0)\";
-
-	    else if (TARGET_ELF && CONSTANT_P (right))
-	      return \"{cal|la} %L0,%3@l(%2)\;{l|lwz} %0,0(%L0)\;{l|lwz} %L0,4(%L0)\";
-	  }
-	fatal_insn (\"nonoffsetable movdf case not handled\", insn);
-      }
-    case 3:
-      return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
-    case 4:
-    case 5:
-    case 6:
-      return \"#\";
-    case 7:
-      return \"fmr %0,%1\";
-    case 8:
-      return \"lfd%U1%X1 %0,%1\";
-    case 9:
-      return \"stfd%U0%X0 %1,%0\";
-    }
-}"
-  [(set_attr "type" "*,load,load,store,*,*,*,fp,fpload,fpstore")
-   (set_attr "length" "8,8,12,8,8,12,16,*,*,*")])
-;; END CYGNUS LOCAL -- meissner/add non-offsetable load
-
-(define_insn "*movdf_softfloat32"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
-	(match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
-  "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    default:
-      abort ();
-    case 0:
-      /* We normally copy the low-numbered register first.  However, if
-	 the first register operand 0 is the same as the second register of
-	 operand 1, we must copy in the opposite order.  */
-      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
-	return \"mr %L0,%L1\;mr %0,%1\";
-      else
-	return \"mr %0,%1\;mr %L0,%L1\";
-    case 1:
-      /* If the low-address word is used in the address, we must load it
-	 last.  Otherwise, load it first.  Note that we cannot have
-	 auto-increment in that case since the address register is known to be
-	 dead.  */
-      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			     operands [1], 0))
-	return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
-      else
-	return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
-    case 2:
-      return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
-    case 3:
-    case 4:
-    case 5:
-      return \"#\";
-    }
-}"
-  [(set_attr "type" "*,load,store,*,*,*")
-   (set_attr "length" "8,8,8,8,12,16")])
-
-(define_insn "*movdf_hardfloat64"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
-	(match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
-  "TARGET_POWERPC64 && TARGET_HARD_FLOAT
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
-  "@
-   mr %0,%1
-   ld%U1%X1 %0,%1
-   std%U0%X0 %1,%0
-   #
-   #
-   #
-   fmr %0,%1
-   lfd%U1%X1 %0,%1
-   stfd%U0%X0 %1,%0"
-  [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
-   (set_attr "length" "4,4,4,8,12,16,4,4,4")])
-
-(define_insn "*movdf_softfloat64"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
-	(match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
-  "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
-  "@
-   mr %0,%1
-   ld%U1%X1 %0,%1
-   std%U0%X0 %1,%0
-   #
-   #
-   #"
-  [(set_attr "type" "*,load,store,*,*,*")
-   (set_attr "length" "*,*,*,8,12,16")])
-
-;; Next come the multi-word integer load and store and the load and store
-;; multiple insns.
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "any_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) != REG)
-    operands[1] = force_reg (DImode, operands[1]);
-
-  /* Convert a move of a CONST_DOUBLE into a CONST_INT
-     only if sign-extended lower-half for 32-bit host.  */
-  if (GET_CODE (operands[1]) == CONST_DOUBLE
-#if HOST_BITS_PER_WIDE_INT == 32
-      && ((CONST_DOUBLE_HIGH (operands[1]) == 0
-	   && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
-	  || (CONST_DOUBLE_HIGH (operands[1]) == 0xffffffff
-	      && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))
-#endif
-	 )
-    operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-
-  if (TARGET_64BIT
-      && CONSTANT_P (operands[1])
-#if HOST_BITS_PER_WIDE_INT == 32
-      && GET_CODE (operands[1]) != CONST_INT
-      && GET_CODE (operands[1]) != CONSTANT_P_RTX
-#endif
-      && ! easy_fp_constant (operands[1], DImode)
-      && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
-    {
-      /* Emit a USE operation so that the constant isn't deleted if
-	 expensive optimizations are turned on because nobody
-	 references it.  This should only be done for operands that
-	 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
-	 This should not be done for operands that contain LABEL_REFs.
-	 For now, we just handle the obvious case.  */
-      if (GET_CODE (operands[1]) != LABEL_REF)
-	emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
-
-      /* If we are to limit the number of things we put in the TOC and
-	 this is a symbol plus a constant we can add in one insn,
-	 just put the symbol in the TOC and add the constant.  Don't do
-	 this if reload is in progress.  */
-      if (GET_CODE (operands[1]) == CONST
-	  && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
-	  && GET_CODE (XEXP (operands[1], 0)) == PLUS
-	  && add_operand (XEXP (XEXP (operands[1], 0), 1), DImode)
-	  && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
-	      || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
-	  && ! side_effects_p (operands[0]))
-	{
-	  rtx sym = force_const_mem (DImode, XEXP (XEXP (operands[1], 0), 0));
-	  rtx other = XEXP (XEXP (operands[1], 0), 1);
-
-	  emit_insn (gen_adddi3 (operands[0], force_reg (DImode, sym), other));
-	  DONE;
-	}
-
-      operands[1] = force_const_mem (DImode, operands[1]);
-      if (! memory_address_p (DImode, XEXP (operands[1], 0))
-	  && ! reload_in_progress)
-	operands[1] = change_address (operands[1], DImode,
-				      XEXP (operands[1], 0));
-    }
-}")
-
-(define_insn "*movdi_32"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
-	(match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
-  "! TARGET_POWERPC64
-   && (gpc_reg_operand (operands[0], DImode)
-       || gpc_reg_operand (operands[1], DImode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    default:
-      abort ();
-    case 0:
-      /* We normally copy the low-numbered register first.  However, if
-	 the first register operand 0 is the same as the second register of
-	 operand 1, we must copy in the opposite order.  */
-      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
-	return \"mr %L0,%L1\;mr %0,%1\";
-      else
-	return \"mr %0,%1\;mr %L0,%L1\";
-    case 1:
-      /* If the low-address word is used in the address, we must load it
-	 last.  Otherwise, load it first.  Note that we cannot have
-	 auto-increment in that case since the address register is known to be
-	 dead.  */
-      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			     operands [1], 0))
-	return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
-      else
-	return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
-    case 2:
-      return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
-    case 3:
-      return \"fmr %0,%1\";
-    case 4:
-      return \"lfd%U1%X1 %0,%1\";
-    case 5:
-      return \"stfd%U0%X0 %1,%0\";
-    case 6:
-    case 7:
-    case 8:
-    case 9:
-    case 10:
-      return \"#\";
-    }
-}"
-  [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
-   (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_operand:DI 1 "const_int_operand" ""))]
-  "! TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (match_dup 1))]
-  "
-{
-  operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
-  operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
-#if HOST_BITS_PER_WIDE_INT == 32
-  operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
-#else
-  operands[4] = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
-  operands[1] = INTVAL (operands[1]) & 0xffffffff;
-#endif
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_operand:DI 1 "const_double_operand" ""))]
-  "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2) (match_dup 4))
-   (set (match_dup 3) (match_dup 5))]
-  "
-{
-  operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
-  operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
-  operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
-  operands[5] = GEN_INT (CONST_DOUBLE_LOW  (operands[1]));
-}")
-
-(define_insn "*movdi_64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
-	(match_operand:DI 1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,0"))]
-  "TARGET_POWERPC64
-   && (gpc_reg_operand (operands[0], DImode)
-       || gpc_reg_operand (operands[1], DImode))"
-  "@
-   mr %0,%1
-   ld%U1%X1 %0,%1
-   std%U0%X0 %1,%0
-   li %0,%1
-   lis %0,%v1
-   #
-   {cal|la} %0,%1(%*)
-   fmr %0,%1
-   lfd%U1%X1 %0,%1
-   stfd%U0%X0 %1,%0
-   mf%1 %0
-   mt%0 %1
-   cror 0,0,0"
-  [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
-   (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(match_operand:DI 1 "const_double_operand" "F"))]
-  "TARGET_POWERPC64 && GET_CODE (operands[1]) == CONST_DOUBLE
-   && num_insns_constant (operands[1], DImode) == 1"
-  "*
-{
-  return ((unsigned HOST_WIDE_INT)
-	  (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
-	 ? \"li %0,%1\" : \"lis %0,%v1\";
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_operand:DI 1 "const_int_operand" ""))]
-  "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
-   && num_insns_constant (operands[1], DImode) > 1"
-  [(set (match_dup 0)
-	(match_dup 2))
-   (set (match_dup 0)
-	(ior:DI (match_dup 0)
-		(match_dup 3)))]
-  "
-{
-  operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
-  operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_operand:DI 1 "const_double_operand" ""))]
-  "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
-   && GET_CODE (operands[1]) == CONST_DOUBLE
-   && ((CONST_DOUBLE_HIGH (operands[1]) == 0
-        && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
-       || (CONST_DOUBLE_HIGH (operands[1]) == 0xffffffff
-           && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))"
-  [(set (match_dup 0)
-	(match_dup 2))
-   (set (match_dup 0)
-	(ior:DI (match_dup 0)
-		(match_dup 3)))]
-  "
-{
-  operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff0000);
-  operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff);
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_operand:DI 1 "const_double_operand" ""))]
-  "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
-   && GET_CODE (operands[1]) == CONST_DOUBLE
-   && CONST_DOUBLE_HIGH (operands[1]) == 0
-   && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0"
-  [(set (match_dup 0)
-	(match_dup 2))
-   (set (match_dup 0)
-	(zero_extend:DI (subreg:SI (match_dup 0) 0)))]
-  "
-{ operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); }")
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_operand:DI 1 "const_double_operand" ""))]
-  "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
-   && GET_CODE (operands[1]) == CONST_DOUBLE
-   && CONST_DOUBLE_LOW (operands[1]) == 0"
-  [(set (match_dup 0)
-	(match_dup 2))
-   (set (match_dup 0)
-	(ashift:DI (match_dup 0)
-		   (const_int 32)))]
-  "
-{ operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); }")
-
-;; Generate all one-bits and clear left or right.
-;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_operand:DI 1 "mask64_operand" ""))]
-  "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
-  [(set (match_dup 0) (const_int -1))
-   (set (match_dup 0)
-	(and:DI (rotate:DI (match_dup 0)
-			   (const_int 0))
-		(match_dup 1)))]
-  "")
-
-;; Split a load of a large constant into the appropriate five-instruction
-;; sequence.  Handle anything in a constant number of insns.
-;; When non-easy constants can go in the TOC, this should use
-;; easy_fp_constant predicate.
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_operand:DI 1 "const_double_operand" ""))]
-  "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
-  [(set (match_dup 0)
-	(match_dup 2))
-   (set (match_dup 0)
-	(ashift:DI (match_dup 0)
-		   (const_int 32)))
-   (set (match_dup 0)
-	(ior:DI (match_dup 0)
-		(match_dup 3)))]
-  "
-{
-  HOST_WIDE_INT low;
-  HOST_WIDE_INT high;
-
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    {
-      low = CONST_DOUBLE_LOW (operands[1]);
-      high = CONST_DOUBLE_HIGH (operands[1]);
-    }
-  else
-#if HOST_BITS_PER_WIDE_INT == 32
-    {
-      low = INTVAL (operands[1]);
-      high = (low < 0) ? ~0 : 0;
-    }
-#else
-    {
-      low = INTVAL (operands[1]) & 0xffffffff;
-      high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
-    }
-#endif
-
-  operands[2] = GEN_INT (high);
-  operands[3] = GEN_INT (low);
-}")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
-  "TARGET_POWERPC64"
-  "@
-  mr. %0,%1
-  #"
-  [(set_attr "type" "compare")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_dup 1))]
-  "reload_completed && rtx_equal_p (operands[0], operands[1])"
-  [(set (match_dup 2)
-	(compare:CC (match_dup 1)
-		    (const_int 0)))]
-  "")
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_dup 1))]
-  "reload_completed && !rtx_equal_p (operands[0], operands[1])"
-  [(set (match_dup 2)
-	(compare:CC (match_dup 1)
-		    (const_int 0)))
-   (set (match_dup 0)
-	(match_dup 1))]
-  "")
-
-;; TImode is similar, except that we usually want to compute the address into
-;; a register and use lsi/stsi (the exception is during reload).  MQ is also
-;; clobbered in stsi for POWER, so we need a SCRATCH for it.
-(define_expand "movti"
-  [(parallel [(set (match_operand:TI 0 "general_operand" "")
-		   (match_operand:TI 1 "general_operand" ""))
-	      (clobber (scratch:SI))])]
-  "TARGET_STRING || TARGET_POWERPC64"
-  "
-{
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (TImode, operands[1]);
-
-  if (GET_CODE (operands[0]) == MEM
-      && GET_CODE (XEXP (operands[0], 0)) != REG
-      && ! reload_in_progress)
-    operands[0] = change_address (operands[0], TImode,
-				  copy_addr_to_reg (XEXP (operands[0], 0)));
-
-  if (GET_CODE (operands[1]) == MEM
-      && GET_CODE (XEXP (operands[1], 0)) != REG
-      && ! reload_in_progress)
-    operands[1] = change_address (operands[1], TImode,
-				  copy_addr_to_reg (XEXP (operands[1], 0)));
-}")
-
-;; We say that MQ is clobbered in the last alternative because the first
-;; alternative would never get used otherwise since it would need a reload
-;; while the 2nd alternative would not.  We put memory cases first so they
-;; are preferred.  Otherwise, we'd try to reload the output instead of
-;; giving the SCRATCH mq.
-(define_insn "*movti_power"
-  [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
-	(match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
-   (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
-  "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
-   && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    default:
-      abort ();
-
-    case 0:
-      return \"{stsi|stswi} %1,%P0,16\";
-
-    case 1:
-      return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
-
-    case 2:
-      /* Normally copy registers with lowest numbered register copied first.
-	 But copy in the other order if the first register of the output
-	 is the second, third, or fourth register in the input.  */
-      if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
-	  && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
-	return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
-      else
-	return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
-    case 3:
-      /* If the address is not used in the output, we can use lsi.  Otherwise,
-	 fall through to generating four loads.  */
-      if (! reg_overlap_mentioned_p (operands[0], operands[1]))
-	return \"{lsi|lswi} %0,%P1,16\";
-      /* ... fall through ... */
-    case 4:
-      /* If the address register is the same as the register for the lowest-
-	 addressed word, load it last.  Similarly for the next two words.
-	 Otherwise load lowest address to highest.  */
-      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			     operands[1], 0))
-	return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
-      else if (refers_to_regno_p (REGNO (operands[0]) + 1,
-				  REGNO (operands[0]) + 2, operands[1], 0))
-	return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
-      else if (refers_to_regno_p (REGNO (operands[0]) + 2,
-				  REGNO (operands[0]) + 3, operands[1], 0))
-	return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
-      else
-	return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
-    }
-}"
-  [(set_attr "type" "store,store,*,load,load")
-   (set_attr "length" "*,16,16,*,16")])
-
-(define_insn "*movti_string"
-  [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
-	(match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
-   (clobber (match_scratch:SI 2 "=X,X,X"))]
-  "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64
-   && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    default:
-      abort ();
-
-    case 0:
-      return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
-
-    case 1:
-      /* Normally copy registers with lowest numbered register copied first.
-	 But copy in the other order if the first register of the output
-	 is the second, third, or fourth register in the input.  */
-      if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
-	  && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
-	return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
-      else
-	return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
-    case 2:
-      /* If the address register is the same as the register for the lowest-
-	 addressed word, load it last.  Similarly for the next two words.
-	 Otherwise load lowest address to highest.  */
-      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			     operands[1], 0))
-	return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
-      else if (refers_to_regno_p (REGNO (operands[0]) + 1,
-				  REGNO (operands[0]) + 2, operands[1], 0))
-	return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
-      else if (refers_to_regno_p (REGNO (operands[0]) + 2,
-				  REGNO (operands[0]) + 3, operands[1], 0))
-	return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
-      else
-	return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
-    }
-}"
-  [(set_attr "type" "store,*,load")
-   (set_attr "length" "16,16,16")])
-
-(define_insn "*movti_ppc64"
-  [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
-	(match_operand:TI 1 "input_operand" "r,m,r"))]
-  "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
-   || gpc_reg_operand (operands[1], TImode))"
-  "*
-{
-  switch (which_alternative)
-    {
-    default:
-      abort ();
-    case 0:
-      /* We normally copy the low-numbered register first.  However, if
-	 the first register operand 0 is the same as the second register of
-	 operand 1, we must copy in the opposite order.  */
-      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
-	return \"mr %L0,%L1\;mr %0,%1\";
-      else
-	return \"mr %0,%1\;mr %L0,%L1\";
-    case 1:
-      /* If the low-address word is used in the address, we must load it
-	 last.  Otherwise, load it first.  Note that we cannot have
-	 auto-increment in that case since the address register is known to be
-	 dead.  */
-      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
-			     operands [1], 0))
-	return \"ld %L0,%L1\;ld %0,%1\";
-      else
-	return \"ld%U1 %0,%1\;ld %L0,%L1\";
-    case 2:
-      return \"std%U0 %1,%0\;std %L1,%L0\";
-    }
-}"
-  [(set_attr "type" "*,load,store")
-   (set_attr "length" "8,8,8")])
-
-(define_expand "load_multiple"
-  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
-			  (match_operand:SI 1 "" ""))
-		     (use (match_operand:SI 2 "" ""))])]
-  "TARGET_STRING"
-  "
-{
-  int regno;
-  int count;
-  rtx from;
-  int i;
-
-  /* Support only loading a constant number of fixed-point registers from
-     memory and only bother with this if more than two; the machine
-     doesn't support more than eight.  */
-  if (GET_CODE (operands[2]) != CONST_INT
-      || INTVAL (operands[2]) <= 2
-      || INTVAL (operands[2]) > 8
-      || GET_CODE (operands[1]) != MEM
-      || GET_CODE (operands[0]) != REG
-      || REGNO (operands[0]) >= 32)
-    FAIL;
-
-  count = INTVAL (operands[2]);
-  regno = REGNO (operands[0]);
-
-  operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
-  from = force_reg (SImode, XEXP (operands[1], 0));
-
-  for (i = 0; i < count; i++)
-    XVECEXP (operands[3], 0, i)
-      = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
-		 change_address (operands[1], SImode,
-				 plus_constant (from, i * 4)));
-}")
-
-(define_insn ""
-  [(match_parallel 0 "load_multiple_operation"
-		   [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
-			 (mem:SI (match_operand:SI 2 "register_operand" "b")))])]
-  "TARGET_STRING"
-  "*
-{
-  /* We have to handle the case where the pseudo used to contain the address
-     is assigned to one of the output registers.  */
-  int i, j;
-  int words = XVECLEN (operands[0], 0);
-  rtx xop[10];
-
-  if (XVECLEN (operands[0], 0) == 1)
-    return \"{l|lwz} %1,0(%2)\";
-
-  for (i = 0; i < words; i++)
-    if (refers_to_regno_p (REGNO (operands[1]) + i,
-			   REGNO (operands[1]) + i + 1, operands[2], 0))
-      {
-	if (i == words-1)
-	  {
-	    xop[0] = operands[1];
-	    xop[1] = operands[2];
-	    xop[2] = GEN_INT (4 * (words-1));
-	    output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop);
-	    return \"\";
-	  }
-	else if (i == 0)
-	  {
-	    xop[0] = operands[1];
-	    xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
-	    xop[2] = GEN_INT (4 * (words-1));
-	    output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop);
-	    return \"\";
-	  }
-	else
-	  {
-	    for (j = 0; j < words; j++)
-	      if (j != i)
-		{
-		  xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j);
-		  xop[1] = operands[2];
-		  xop[2] = GEN_INT (j * 4);
-		  output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop);
-		}
-	    xop[0] = operands[2];
-	    xop[1] = GEN_INT (i * 4);
-	    output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop);
-	    return \"\";
-	  }
-      }
-
-  return \"{lsi|lswi} %1,%2,%N0\";
-}"
-  [(set_attr "type" "load")
-   (set_attr "length" "32")])
-
-
-(define_expand "store_multiple"
-  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
-			  (match_operand:SI 1 "" ""))
-		     (clobber (scratch:SI))
-		     (use (match_operand:SI 2 "" ""))])]
-  "TARGET_STRING"
-  "
-{
-  int regno;
-  int count;
-  rtx to;
-  int i;
-
-  /* Support only storing a constant number of fixed-point registers to
-     memory and only bother with this if more than two; the machine
-     doesn't support more than eight.  */
-  if (GET_CODE (operands[2]) != CONST_INT
-      || INTVAL (operands[2]) <= 2
-      || INTVAL (operands[2]) > 8
-      || GET_CODE (operands[0]) != MEM
-      || GET_CODE (operands[1]) != REG
-      || REGNO (operands[1]) >= 32)
-    FAIL;
-
-  count = INTVAL (operands[2]);
-  regno = REGNO (operands[1]);
-
-  operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
-  to = force_reg (SImode, XEXP (operands[0], 0));
-
-  XVECEXP (operands[3], 0, 0)
-    = gen_rtx_SET (VOIDmode, change_address (operands[0], SImode, to),
-	       operands[1]);
-  XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
-						  gen_rtx_SCRATCH (SImode));
-
-  for (i = 1; i < count; i++)
-    XVECEXP (operands[3], 0, i + 1)
-      = gen_rtx_SET (VOIDmode,
-		 change_address (operands[0], SImode,
-				 plus_constant (to, i * 4)),
-		 gen_rtx_REG (SImode, regno + i));
-}")
-
-(define_insn ""
-  [(match_parallel 0 "store_multiple_operation"
-		   [(set (match_operand:SI 1 "indirect_operand" "=Q")
-			 (match_operand:SI 2 "gpc_reg_operand" "r"))
-		    (clobber (match_scratch:SI 3 "=q"))])]
-  "TARGET_STRING && TARGET_POWER"
-  "{stsi|stswi} %2,%P1,%O0"
-  [(set_attr "type" "store")])
-
-(define_insn ""
-  [(match_parallel 0 "store_multiple_operation"
-		   [(set (mem:SI (match_operand:SI 1 "register_operand" "b"))
-			 (match_operand:SI 2 "gpc_reg_operand" "r"))
-		    (clobber (match_scratch:SI 3 "X"))])]
-  "TARGET_STRING && !TARGET_POWER"
-  "{stsi|stswi} %2,%1,%O0"
-  [(set_attr "type" "store")])
-
-
-;; String/block move insn.
-;; Argument 0 is the destination
-;; Argument 1 is the source
-;; Argument 2 is the length
-;; Argument 3 is the alignment
-
-(define_expand "movstrsi"
-  [(parallel [(set (match_operand:BLK 0 "" "")
-		   (match_operand:BLK 1 "" ""))
-	      (use (match_operand:SI 2 "" ""))
-	      (use (match_operand:SI 3 "" ""))])]
-  ""
-  "
-{
-  if (expand_block_move (operands))
-    DONE;
-  else
-    FAIL;
-}")
-
-;; Move up to 32 bytes at a time.  The fixed registers are needed because the
-;; register allocator doesn't have a clue about allocating 8 word registers
-(define_expand "movstrsi_8reg"
-  [(parallel [(set (match_operand 0 "" "")
-		   (match_operand 1 "" ""))
-	      (use (match_operand 2 "" ""))
-	      (use (match_operand 3 "" ""))
-	      (clobber (reg:SI  5))
-	      (clobber (reg:SI  6))
-	      (clobber (reg:SI  7))
-	      (clobber (reg:SI  8))
-	      (clobber (reg:SI  9))
-	      (clobber (reg:SI 10))
-	      (clobber (reg:SI 11))
-	      (clobber (reg:SI 12))
-	      (clobber (match_scratch:SI 4 ""))])]
-  "TARGET_STRING"
-  "")
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "register_operand" "=r"))
-   (clobber (reg:SI  6))
-   (clobber (reg:SI  7))
-   (clobber (reg:SI  8))
-   (clobber (reg:SI  9))
-   (clobber (reg:SI 10))
-   (clobber (reg:SI 11))
-   (clobber (reg:SI 12))
-   (clobber (match_scratch:SI 5 "=q"))]
-  "TARGET_STRING && TARGET_POWER
-   && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
-   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
-   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
-   && REGNO (operands[4]) == 5"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "register_operand" "=r"))
-   (clobber (reg:SI  6))
-   (clobber (reg:SI  7))
-   (clobber (reg:SI  8))
-   (clobber (reg:SI  9))
-   (clobber (reg:SI 10))
-   (clobber (reg:SI 11))
-   (clobber (reg:SI 12))
-   (clobber (match_scratch:SI 5 "X"))]
-  "TARGET_STRING && !TARGET_POWER
-   && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
-   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
-   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
-   && REGNO (operands[4]) == 5"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
-;; Move up to 24 bytes at a time.  The fixed registers are needed because the
-;; register allocator doesn't have a clue about allocating 6 word registers
-(define_expand "movstrsi_6reg"
-  [(parallel [(set (match_operand 0 "" "")
-		   (match_operand 1 "" ""))
-	      (use (match_operand 2 "" ""))
-	      (use (match_operand 3 "" ""))
-	      (clobber (reg:SI  7))
-	      (clobber (reg:SI  8))
-	      (clobber (reg:SI  9))
-	      (clobber (reg:SI 10))
-	      (clobber (reg:SI 11))
-	      (clobber (reg:SI 12))
-	      (clobber (match_scratch:SI 4 ""))])]
-  "TARGET_STRING"
-  "")
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "register_operand" "=r"))
-   (clobber (reg:SI  8))
-   (clobber (reg:SI  9))
-   (clobber (reg:SI 10))
-   (clobber (reg:SI 11))
-   (clobber (reg:SI 12))
-   (clobber (match_scratch:SI 5 "=q"))]
-  "TARGET_STRING && TARGET_POWER
-   && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
-   && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
-   && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
-   && REGNO (operands[4]) == 7"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "register_operand" "=r"))
-   (clobber (reg:SI  8))
-   (clobber (reg:SI  9))
-   (clobber (reg:SI 10))
-   (clobber (reg:SI 11))
-   (clobber (reg:SI 12))
-   (clobber (match_scratch:SI 5 "X"))]
-  "TARGET_STRING && !TARGET_POWER
-   && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
-   && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
-   && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
-   && REGNO (operands[4]) == 7"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
-;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems
-;; with TImode
-(define_expand "movstrsi_4reg"
-  [(parallel [(set (match_operand 0 "" "")
-		   (match_operand 1 "" ""))
-	      (use (match_operand 2 "" ""))
-	      (use (match_operand 3 "" ""))
-	      (clobber (reg:SI  9))
-	      (clobber (reg:SI 10))
-	      (clobber (reg:SI 11))
-	      (clobber (reg:SI 12))
-	      (clobber (match_scratch:SI 4 ""))])]
-  "TARGET_STRING"
-  "")
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "register_operand" "=r"))
-   (clobber (reg:SI 10))
-   (clobber (reg:SI 11))
-   (clobber (reg:SI 12))
-   (clobber (match_scratch:SI 5 "=q"))]
-  "TARGET_STRING && TARGET_POWER
-   && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
-   && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
-   && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
-   && REGNO (operands[4]) == 9"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "register_operand" "=r"))
-   (clobber (reg:SI 10))
-   (clobber (reg:SI 11))
-   (clobber (reg:SI 12))
-   (clobber (match_scratch:SI 5 "X"))]
-  "TARGET_STRING && !TARGET_POWER
-   && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
-   && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
-   && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
-   && REGNO (operands[4]) == 9"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
-;; Move up to 8 bytes at a time.
-(define_expand "movstrsi_2reg"
-  [(parallel [(set (match_operand 0 "" "")
-		   (match_operand 1 "" ""))
-	      (use (match_operand 2 "" ""))
-	      (use (match_operand 3 "" ""))
-	      (clobber (match_scratch:DI 4 ""))
-	      (clobber (match_scratch:SI 5 ""))])]
-  "TARGET_STRING && !TARGET_64BIT"
-  "")
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_scratch:DI 4 "=&r"))
-   (clobber (match_scratch:SI 5 "=q"))]
-  "TARGET_STRING && TARGET_POWER && !TARGET_64BIT
-   && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_scratch:DI 4 "=&r"))
-   (clobber (match_scratch:SI 5 "X"))]
-  "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
-   && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
-;; Move up to 4 bytes at a time.
-(define_expand "movstrsi_1reg"
-  [(parallel [(set (match_operand 0 "" "")
-		   (match_operand 1 "" ""))
-	      (use (match_operand 2 "" ""))
-	      (use (match_operand 3 "" ""))
-	      (clobber (match_scratch:SI 4 ""))
-	      (clobber (match_scratch:SI 5 ""))])]
-  "TARGET_STRING"
-  "")
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_scratch:SI 4 "=&r"))
-   (clobber (match_scratch:SI 5 "=q"))]
-  "TARGET_STRING && TARGET_POWER
-   && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "register_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_scratch:SI 4 "=&r"))
-   (clobber (match_scratch:SI 5 "X"))]
-  "TARGET_STRING && !TARGET_POWER
-   && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
-
-;; Define insns that do load or store with update.  Some of these we can
-;; get by using pre-decrement or pre-increment, but the hardware can also
-;; do cases where the increment is not the size of the object.
-;;
-;; In all these cases, we use operands 0 and 1 for the register being
-;; incremented because those are the operands that local-alloc will
-;; tie and these are the pair most likely to be tieable (and the ones
-;; that will benefit the most).
-
-(define_insn "*movdi_update1"
-  [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
-	(mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
-	(plus:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64 && TARGET_UPDATE"
-  "@
-   ldux %3,%0,%2
-   ldu %3,%2(%0)"
-  [(set_attr "type" "load")])
-
-(define_insn "*movdi_update2"
-  [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
-	(sign_extend:DI
-	 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
-			  (match_operand:DI 2 "gpc_reg_operand" "r")))))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=b")
-	(plus:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64"
-  "lwaux %3,%0,%2"
-  [(set_attr "type" "load")])
-
-(define_insn "movdi_update"
-  [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
-	(match_operand:DI 3 "gpc_reg_operand" "r,r"))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
-	(plus:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64 && TARGET_UPDATE"
-  "@
-   stdux %3,%0,%2
-   stdu %3,%2(%0)"
-  [(set_attr "type" "store")])
-
-(define_insn "*movsi_update1"
-  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
-	(mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "@
-   {lux|lwzux} %3,%0,%2
-   {lu|lwzu} %3,%2(%0)"
-  [(set_attr "type" "load")])
-
-(define_insn "movsi_update"
-  [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-	(match_operand:SI 3 "gpc_reg_operand" "r,r"))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_UPDATE"
-  "@
-   {stux|stwux} %3,%0,%2
-   {stu|stwu} %3,%2(%0)"
-  [(set_attr "type" "store")])
-
-(define_insn "*movhi_update"
-  [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
-	(mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_UPDATE"
-  "@
-   lhzux %3,%0,%2
-   lhzu %3,%2(%0)"
-  [(set_attr "type" "load")])
-
-(define_insn "*movhi_update2"
-  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI
-	 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			  (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_UPDATE"
-  "@
-   lhzux %3,%0,%2
-   lhzu %3,%2(%0)"
-  [(set_attr "type" "load")])
-
-(define_insn "*movhi_update3"
-  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
-	(sign_extend:SI
-	 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			  (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_UPDATE"
-  "@
-   lhaux %3,%0,%2
-   lhau %3,%2(%0)"
-  [(set_attr "type" "load")])
-
-(define_insn "*movhi_update4"
-  [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-	(match_operand:HI 3 "gpc_reg_operand" "r,r"))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_UPDATE"
-  "@
-   sthux %3,%0,%2
-   sthu %3,%2(%0)"
-  [(set_attr "type" "store")])
-
-(define_insn "*movqi_update1"
-  [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
-	(mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_UPDATE"
-  "@
-   lbzux %3,%0,%2
-   lbzu %3,%2(%0)"
-  [(set_attr "type" "load")])
-
-(define_insn "*movqi_update2"
-  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
-	(zero_extend:SI
-	 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			  (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_UPDATE"
-  "@
-   lbzux %3,%0,%2
-   lbzu %3,%2(%0)"
-  [(set_attr "type" "load")])
-
-(define_insn "*movqi_update3"
-  [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-	(match_operand:QI 3 "gpc_reg_operand" "r,r"))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_UPDATE"
-  "@
-   stbux %3,%0,%2
-   stbu %3,%2(%0)"
-  [(set_attr "type" "store")])
-
-(define_insn "*movsf_update1"
-  [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
-	(mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_HARD_FLOAT && TARGET_UPDATE"
-  "@
-   lfsux %3,%0,%2
-   lfsu %3,%2(%0)"
-  [(set_attr "type" "fpload")])
-
-(define_insn "*movsf_update2"
-  [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-	(match_operand:SF 3 "gpc_reg_operand" "f,f"))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_HARD_FLOAT && TARGET_UPDATE"
-  "@
-   stfsux %3,%0,%2
-   stfsu %3,%2(%0)"
-  [(set_attr "type" "fpstore")])
-
-(define_insn "*movsf_update3"
-  [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
-	(mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_SOFT_FLOAT && TARGET_UPDATE"
-  "@
-   {lux|lwzux} %3,%0,%2
-   {lu|lwzu} %3,%2(%0)"
-  [(set_attr "type" "load")])
-
-(define_insn "*movsf_update4"
-  [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-	(match_operand:SF 3 "gpc_reg_operand" "r,r"))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_SOFT_FLOAT && TARGET_UPDATE"
-  "@
-   {stux|stwux} %3,%0,%2
-   {stu|stwu} %3,%2(%0)"
-  [(set_attr "type" "store")])
-
-(define_insn "*movdf_update1"
-  [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
-	(mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_HARD_FLOAT && TARGET_UPDATE"
-  "@
-   lfdux %3,%0,%2
-   lfdu %3,%2(%0)"
-  [(set_attr "type" "fpload")])
-
-(define_insn "*movdf_update2"
-  [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-	(match_operand:DF 3 "gpc_reg_operand" "f,f"))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_HARD_FLOAT && TARGET_UPDATE"
-  "@
-   stfdux %3,%0,%2
-   stfdu %3,%2(%0)"
-  [(set_attr "type" "fpstore")])
-
-;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
-
-(define_peephole
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(match_operand:DF 1 "memory_operand" ""))
-   (set (match_operand:DF 2 "gpc_reg_operand" "=f")
-	(match_operand:DF 3 "memory_operand" ""))]
-  "TARGET_POWER2
-   && TARGET_HARD_FLOAT
-   && registers_ok_for_quad_peep (operands[0], operands[2])
-   && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
-   && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
-  "lfq%U1%X1 %0,%1")
-
-(define_peephole
-  [(set (match_operand:DF 0 "memory_operand" "")
-	(match_operand:DF 1 "gpc_reg_operand" "f"))
-   (set (match_operand:DF 2 "memory_operand" "")
-	(match_operand:DF 3 "gpc_reg_operand" "f"))]
-  "TARGET_POWER2
-   && TARGET_HARD_FLOAT
-   && registers_ok_for_quad_peep (operands[1], operands[3])
-   && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
-   && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
-  "stfq%U0%X0 %1,%0")
-
-;; Next come insns related to the calling sequence.
-;;
-;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
-;; We move the back-chain and decrement the stack pointer.
-
-(define_expand "allocate_stack"
-  [(set (match_operand 0 "register_operand" "=r")
-	(minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
-   (set (reg 1)
-	(minus (reg 1) (match_dup 1)))]
-  ""
-  "
-{ rtx chain = gen_reg_rtx (Pmode);
-  rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
-  rtx neg_op0;
-
-  emit_move_insn (chain, stack_bot);
-
-  /* Under Windows NT, we need to add stack probes for large/variable
-     allocations, so do it via a call to the external function alloca
-     instead of doing it inline.  */
-  if (DEFAULT_ABI == ABI_NT
-      && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 4096))
-    {
-      rtx tmp = gen_reg_rtx (Pmode);
-      emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__allocate_stack\"),
-			       tmp, 0, Pmode, 1, operands[1], Pmode);
-      emit_insn (gen_set_sp (tmp));
-      emit_move_insn (operands[0], tmp);
-      DONE;
-    }
-
-  if (GET_CODE (operands[1]) != CONST_INT
-      || INTVAL (operands[1]) < -32767
-      || INTVAL (operands[1]) > 32768)
-    {
-      neg_op0 = gen_reg_rtx (Pmode);
-      if (TARGET_32BIT)
-	emit_insn (gen_negsi2 (neg_op0, operands[1]));
-      else
-	emit_insn (gen_negdi2 (neg_op0, operands[1]));
-    }
-  else
-    neg_op0 = GEN_INT (- INTVAL (operands[1]));
-
-  if (TARGET_UPDATE)
-    emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
-		(stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
-
-  else
-    {
-      emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
-		 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
-      emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
-    }
-
-  emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
-  DONE;
-}")
-
-;; Marker to indicate that the stack pointer was changed under NT in
-;; ways not known to the compiler
-
-(define_insn "set_sp"
-  [(set (reg:SI 1)
-	(unspec [(match_operand:SI 0 "register_operand" "r")] 7))]
-  ""
-  ""
-  [(set_attr "length" "0")])
-
-;; These patterns say how to save and restore the stack pointer.  We need not
-;; save the stack pointer at function level since we are careful to
-;; preserve the backchain.  At block level, we have to restore the backchain
-;; when we restore the stack pointer.
-;;
-;; For nonlocal gotos, we must save both the stack pointer and its
-;; backchain and restore both.  Note that in the nonlocal case, the
-;; save area is a memory location.
-
-(define_expand "save_stack_function"
-  [(match_operand 0 "any_operand" "")
-   (match_operand 1 "any_operand" "")]
-  ""
-  "DONE;")
-
-(define_expand "restore_stack_function"
-  [(match_operand 0 "any_operand" "")
-   (match_operand 1 "any_operand" "")]
-  ""
-  "DONE;")
-
-(define_expand "restore_stack_block"
-  [(use (match_operand 0 "register_operand" ""))
-   (set (match_dup 2) (match_dup 3))
-   (set (match_dup 0) (match_operand 1 "register_operand" ""))
-   (set (match_dup 3) (match_dup 2))]
-  ""
-  "
-{
-  operands[2] = gen_reg_rtx (Pmode);
-  operands[3] = gen_rtx_MEM (Pmode, operands[0]);
-}")
-
-(define_expand "save_stack_nonlocal"
-  [(match_operand 0 "memory_operand" "")
-   (match_operand 1 "register_operand" "")]
-  ""
-  "
-{
-  rtx temp = gen_reg_rtx (Pmode);
-
-  /* Copy the backchain to the first word, sp to the second.  */
-  emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
-  emit_move_insn (operand_subword (operands[0], 0, 0, (TARGET_32BIT ? DImode : TImode)),
-		  temp);
-  emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
-		  operands[1]);
-  DONE;
-}")
-
-(define_expand "restore_stack_nonlocal"
-  [(match_operand 0 "register_operand" "")
-   (match_operand 1 "memory_operand" "")]
-  ""
-  "
-{
-  rtx temp = gen_reg_rtx (Pmode);
-
-  /* Restore the backchain from the first word, sp from the second.  */
-  emit_move_insn (temp,
-		  operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
-  emit_move_insn (operands[0],
-		  operand_subword (operands[1], 1, 0, (TARGET_32BIT ? DImode : TImode)));
-  emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
-  DONE;
-}")
-
-;; If we have -mminimal-toc, we need to reload r30 after a nonlocal goto.
-
-;; NB. Kenner removed the '&& get_pool_size() != 0' part of the condition
-;; on Oct 18, 1997 for an as yet undetermined reason.  Without this condition, 
-;; the powerpc-eabi targets mistakenly force a load of r30 at the beginning 
-;; of exception handlers in functions which have no constant section.
-;; Presumably the original reason for the change will re-surface at some 
-;; point, and this comment will help sort out the right thing to do.
-;; If this needs to be changed back again, it may be that the rs6000
-;; prologue code should have the equivilent change made so that there is
-;; a TOC value to restore.  (It currently uses the get_pool_size() check).
-
-(define_insn "nonlocal_goto_receiver"
-  [(unspec_volatile [(const_int 0)] 1)]
-  "TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size() != 0"
-  "*
-{
-  rs6000_output_load_toc_table (asm_out_file, 30, FALSE);
-  return \"\";
-}"
-  [(set_attr "type" "load")])
-
-;; A function pointer under AIX is a pointer to a data area whose first word
-;; contains the actual address of the function, whose second word contains a
-;; pointer to its TOC, and whose third word contains a value to place in the
-;; static chain register (r11).  Note that if we load the static chain, our
-;; "trampoline" need not have any executable code.
-;;
-;; operands[0] is a register pointing to the 3 word descriptor (aka, the function address)
-;; operands[1] is the stack size to clean up
-;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for AIX)
-;; operands[3] is location to store the TOC
-;; operands[4] is the TOC register
-;; operands[5] is the static chain register
-;;
-;; We do not break this into separate insns, so that the scheduler will not try
-;; to move the load of the new TOC before any loads from the TOC.
-
-(define_insn "call_indirect_aix32"
-  [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
-	 (match_operand 1 "const_int_operand" "n"))
-   (use (match_operand 2 "const_int_operand" "n"))
-   (use (match_operand 3 "offsettable_addr_operand" "p"))
-   (use (match_operand 4 "register_operand" "r"))
-   (clobber (match_operand 5 "register_operand" "=r"))
-   (clobber (match_scratch:SI 6 "=&r"))
-   (clobber (match_scratch:SI 7 "=l"))]
-  "DEFAULT_ABI == ABI_AIX
-   && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
-  "{st|stw} %4,%a3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0)\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%a3"
-  [(set_attr "type" "load")
-   (set_attr "length" "28")])
-
-(define_insn "call_indirect_aix64"
-  [(call (mem:SI (match_operand:DI 0 "register_operand" "b"))
-	 (match_operand 1 "const_int_operand" "n"))
-   (use (match_operand 2 "const_int_operand" "n"))
-   (use (match_operand 3 "offsettable_addr_operand" "p"))
-   (use (match_operand 4 "register_operand" "r"))
-   (clobber (match_operand 5 "register_operand" "=r"))
-   (clobber (match_scratch:SI 6 "=&r"))
-   (clobber (match_scratch:SI 7 "=l"))]
-  "TARGET_64BIT && DEFAULT_ABI == ABI_AIX
-   && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
-  "std %4,%a3\;ld %6,0(%0)\;ld %4,8(%0)\;mt%7 %6\;ld %5,16(%0)\;blrl\;ld %4,%a3"
-  [(set_attr "type" "load")
-   (set_attr "length" "28")])
-
-(define_insn "call_value_indirect_aix32"
-  [(set (match_operand 0 "register_operand" "fg")
-	(call (mem:SI (match_operand:SI 1 "register_operand" "b"))
-	      (match_operand 2 "const_int_operand" "n")))
-   (use (match_operand 3 "const_int_operand" "n"))
-   (use (match_operand 4 "offsettable_addr_operand" "p"))
-   (use (match_operand 5 "register_operand" "r"))
-   (clobber (match_operand 6 "register_operand" "=r"))
-   (clobber (match_scratch:SI 7 "=&r"))
-   (clobber (match_scratch:SI 8 "=l"))]
-  "DEFAULT_ABI == ABI_AIX
-   && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
-  "{st|stw} %5,%a4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1)\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%a4"
-  [(set_attr "type" "load")
-   (set_attr "length" "28")])
-
-(define_insn "call_value_indirect_aix64"
-  [(set (match_operand 0 "register_operand" "fg")
-	(call (mem:SI (match_operand:DI 1 "register_operand" "b"))
-	      (match_operand 2 "const_int_operand" "n")))
-   (use (match_operand 3 "const_int_operand" "n"))
-   (use (match_operand 4 "offsettable_addr_operand" "p"))
-   (use (match_operand 5 "register_operand" "r"))
-   (clobber (match_operand 6 "register_operand" "=r"))
-   (clobber (match_scratch:SI 7 "=&r"))
-   (clobber (match_scratch:SI 8 "=l"))]
-  "TARGET_64BIT && DEFAULT_ABI == ABI_AIX
-   && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
-  "std %5,%a4\;ld %7,0(%1)\;ld %5,8(%1)\;mt%8 %7\;ld %6,16(%1)\;blrl\;ld %5,%a4"
-  [(set_attr "type" "load")
-   (set_attr "length" "28")])
-
-;; A function pointer undef NT is a pointer to a data area whose first word
-;; contains the actual address of the function, whose second word contains a
-;; pointer to its TOC.  The static chain is not stored under NT, which means
-;; that we need a trampoline.
-;;
-;; operands[0] is an SImode pseudo in which we place the address of the function.
-;; operands[1] is the stack size to clean up
-;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for NT)
-;; operands[3] is location to store the TOC
-;; operands[4] is the TOC register
-;;
-;; We do not break this into separate insns, so that the scheduler will not try
-;; to move the load of the new TOC before any loads from the TOC.
-
-(define_insn "call_indirect_nt"
-  [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
-	 (match_operand 1 "const_int_operand" "n"))
-   (use (match_operand 2 "const_int_operand" "n"))
-   (use (match_operand 3 "offsettable_addr_operand" "p"))
-   (use (match_operand 4 "register_operand" "r"))
-   (clobber (match_scratch:SI 5 "=&r"))
-   (clobber (match_scratch:SI 6 "=l"))]
-  "DEFAULT_ABI == ABI_NT
-   && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
-  "{st|stw} %4,%a3\;{l|lwz} %5,0(%0)\;{l|lwz} %4,4(%0)\;mt%6 %5\;{brl|blrl}\;{l|lwz} %4,%a3"
-  [(set_attr "type" "load")
-   (set_attr "length" "24")])
-
-(define_insn "call_value_indirect_nt"
-  [(set (match_operand 0 "register_operand" "fg")
-	(call (mem:SI (match_operand:SI 1 "register_operand" "b"))
-	      (match_operand 2 "const_int_operand" "n")))
-   (use (match_operand 3 "const_int_operand" "n"))
-   (use (match_operand 4 "offsettable_addr_operand" "p"))
-   (use (match_operand 5 "register_operand" "r"))
-   (clobber (match_scratch:SI 6 "=&r"))
-   (clobber (match_scratch:SI 7 "=l"))]
-  "DEFAULT_ABI == ABI_NT
-   && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
-  "{st|stw} %5,%a4\;{l|lwz} %6,0(%1)\;{l|lwz} %5,4(%1)\;mt%7 %6\;{brl|blrl}\;{l|lwz} %5,%a4"
-  [(set_attr "type" "load")
-   (set_attr "length" "24")])
-
-;; A function pointer under System V is just a normal pointer
-;; operands[0] is the function pointer
-;; operands[1] is the stack size to clean up
-;; operands[2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1
-
-(define_insn "call_indirect_sysv"
-  [(call (mem:SI (match_operand:SI 0 "register_operand" "l,l"))
-	 (match_operand 1 "const_int_operand" "n,n"))
-   (use (match_operand 2 "const_int_operand" "O,n"))
-   (clobber (match_scratch:SI 3 "=l,l"))]
-  "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
-  "*
-{
-  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
-    output_asm_insn (\"crxor 6,6,6\", operands);
-
-  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
-    output_asm_insn (\"creqv 6,6,6\", operands);
-
-  return \"{brl|blrl}\";
-}"
-  [(set_attr "type" "jmpreg")
-   (set_attr "length" "4,8")])
-
-(define_insn "call_value_indirect_sysv"
-  [(set (match_operand 0 "register_operand" "=fg,fg")
-	(call (mem:SI (match_operand:SI 1 "register_operand" "l,l"))
-	      (match_operand 2 "const_int_operand" "n,n")))
-   (use (match_operand 3 "const_int_operand" "O,n"))
-   (clobber (match_scratch:SI 4 "=l,l"))]
-  "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
-  "*
-{
-  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
-    output_asm_insn (\"crxor 6,6,6\", operands);
-
-  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
-    output_asm_insn (\"creqv 6,6,6\", operands);
-
-  return \"{brl|blrl}\";
-}"
-  [(set_attr "type" "jmpreg")
-   (set_attr "length" "4,8")])
-
-;; Now the definitions for the call and call_value insns
-(define_expand "call"
-  [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
-		    (match_operand 1 "" ""))
-	      (use (match_operand 2 "" ""))
-	      (clobber (scratch:SI))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
-    abort ();
-
-  operands[0] = XEXP (operands[0], 0);
-
-  /* Convert NT DLL imports into an indirect call.  */
-  if (GET_CODE (operands[0]) == SYMBOL_REF
-      && (INTVAL (operands[2]) & CALL_NT_DLLIMPORT) != 0)
-    {
-      operands[0] = rs6000_dll_import_ref (operands[0]);
-      operands[2] = GEN_INT ((int)CALL_NORMAL);
-    }
-
-  if (GET_CODE (operands[0]) != SYMBOL_REF
-      || (INTVAL (operands[2]) & CALL_LONG) != 0)
-    {
-      if (INTVAL (operands[2]) & CALL_LONG)
-	operands[0] = rs6000_longcall_ref (operands[0]);
-
-      if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
-	emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[0]),
-						operands[1], operands[2]));
-      else
-	{
-	  rtx toc_reg = gen_rtx_REG (Pmode, 2);
-	  rtx toc_addr = RS6000_SAVE_TOC;
-
-	  if (DEFAULT_ABI == ABI_AIX)
-	    {
-	      /* AIX function pointers are really pointers to a three word area */
-	      rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
-	      emit_call_insn (TARGET_32BIT
-			      ? gen_call_indirect_aix32 (force_reg (Pmode, operands[0]),
-						         operands[1], operands[2],
-						         toc_addr, toc_reg, static_chain)
-			      : gen_call_indirect_aix64 (force_reg (Pmode, operands[0]),
-						         operands[1], operands[2],
-						         toc_addr, toc_reg, static_chain));
-	    }
-	  else if (DEFAULT_ABI == ABI_NT)
-	    {
-	      /* NT function pointers are really pointers to a two word area */
-	      emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[0]),
-						    operands[1], operands[2],
-						    toc_addr, toc_reg));
-	    }
-	  else
-	    abort ();
-	}
-      DONE;
-    }
-}")
-
-(define_expand "call_value"
-  [(parallel [(set (match_operand 0 "" "")
-		   (call (mem:SI (match_operand 1 "address_operand" ""))
-			 (match_operand 2 "" "")))
-	      (use (match_operand 3 "" ""))
-	      (clobber (scratch:SI))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
-    abort ();
-
-  operands[1] = XEXP (operands[1], 0);
-
-  /* Convert NT DLL imports into an indirect call.  */
-  if (GET_CODE (operands[1]) == SYMBOL_REF
-      && (INTVAL (operands[3]) & CALL_NT_DLLIMPORT) != 0)
-    {
-      operands[1] = rs6000_dll_import_ref (operands[1]);
-      operands[3] = GEN_INT ((int)CALL_NORMAL);
-    }
-
-  if (GET_CODE (operands[1]) != SYMBOL_REF
-      || (INTVAL (operands[3]) & CALL_LONG) != 0)
-    {
-      if (INTVAL (operands[2]) & CALL_LONG)
-	operands[1] = rs6000_longcall_ref (operands[1]);
-
-      if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
-	emit_call_insn (gen_call_value_indirect_sysv (operands[0], operands[1],
-						      operands[2], operands[3]));
-      else
-	{
-	  rtx toc_reg = gen_rtx_REG (Pmode, 2);
-	  rtx toc_addr = RS6000_SAVE_TOC;
-
-	  if (DEFAULT_ABI == ABI_AIX)
-	    {
-	      /* AIX function pointers are really pointers to a three word area */
-	      rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
-	      emit_call_insn (TARGET_32BIT
-			      ? gen_call_value_indirect_aix32 (operands[0],
-							       force_reg (Pmode, operands[1]),
-							       operands[2], operands[3],
-							       toc_addr, toc_reg, static_chain)
-			      : gen_call_value_indirect_aix64 (operands[0],
-							       force_reg (Pmode, operands[1]),
-							       operands[2], operands[3],
-							       toc_addr, toc_reg, static_chain));
-	    }
-	  else if (DEFAULT_ABI == ABI_NT)
-	    {
-	      /* NT function pointers are really pointers to a two word area */
-	      emit_call_insn (gen_call_value_indirect_nt (operands[0],
-							  force_reg (Pmode, operands[1]),
-							  operands[2], operands[3],
-							  toc_addr, toc_reg));
-	    }
-	  else
-	    abort ();
-	}
-      DONE;
-    }
-}")
-
-;; Call to function in current module.  No TOC pointer reload needed.
-;; Operand2 is non-zero if we are using the V.4 calling sequence and
-;; either the function was not prototyped, or it was prototyped as a
-;; variable argument function.  It is > 0 if FP registers were passed
-;; and < 0 if they were not.
-
-(define_insn "*call_local32"
-  [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
-	 (match_operand 1 "" "g,g"))
-   (use (match_operand:SI 2 "immediate_operand" "O,n"))
-   (clobber (match_scratch:SI 3 "=l,l"))]
-  "(INTVAL (operands[2]) & CALL_LONG) == 0"
-  "*
-{
-  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
-    output_asm_insn (\"crxor 6,6,6\", operands);
-
-  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
-    output_asm_insn (\"creqv 6,6,6\", operands);
-
-  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "4,8")])
-
-(define_insn "*call_local64"
-  [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
-	 (match_operand 1 "" "g,g"))
-   (use (match_operand:SI 2 "immediate_operand" "O,n"))
-   (clobber (match_scratch:SI 3 "=l,l"))]
-  "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
-  "*
-{
-  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
-    output_asm_insn (\"crxor 6,6,6\", operands);
-
-  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
-    output_asm_insn (\"creqv 6,6,6\", operands);
-
-  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "4,8")])
-
-(define_insn "*ret_call_local32"
-  [(set (match_operand 0 "" "=fg,fg")
-	(call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
-	      (match_operand 2 "" "g,g")))
-   (use (match_operand:SI 3 "immediate_operand" "O,n"))
-   (clobber (match_scratch:SI 4 "=l,l"))]
-  "(INTVAL (operands[3]) & CALL_LONG) == 0"
-  "*
-{
-  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
-    output_asm_insn (\"crxor 6,6,6\", operands);
-
-  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
-    output_asm_insn (\"creqv 6,6,6\", operands);
-
-  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "4,8")])
-
-
-(define_insn "*ret_call_local64"
-  [(set (match_operand 0 "" "=fg,fg")
-	(call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
-	      (match_operand 2 "" "g,g")))
-   (use (match_operand:SI 3 "immediate_operand" "O,n"))
-   (clobber (match_scratch:SI 4 "=l,l"))]
-  "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
-  "*
-{
-  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
-    output_asm_insn (\"crxor 6,6,6\", operands);
-
-  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
-    output_asm_insn (\"creqv 6,6,6\", operands);
-
-  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "4,8")])
-
-;; Call to function which may be in another module.  Restore the TOC
-;; pointer (r2) after the call unless this is System V.
-;; Operand2 is non-zero if we are using the V.4 calling sequence and
-;; either the function was not prototyped, or it was prototyped as a
-;; variable argument function.  It is > 0 if FP registers were passed
-;; and < 0 if they were not.
-
-(define_insn "*call_nonlocal_aix32"
-  [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
-	 (match_operand 1 "" "fg,fg"))
-   (use (match_operand:SI 2 "immediate_operand" "O,n"))
-   (clobber (match_scratch:SI 3 "=l,l"))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
-   && (INTVAL (operands[2]) & CALL_LONG) == 0"
-  "*
-{
-  /* Indirect calls should go through call_indirect */
-  if (GET_CODE (operands[0]) == REG)
-    abort ();
-
-  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
-    output_asm_insn (\"crxor 6,6,6\", operands);
-
-  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
-    output_asm_insn (\"creqv 6,6,6\", operands);
-
-  return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "8,12")])
-
-(define_insn "*call_nonlocal_aix64"
-  [(call (mem:SI (match_operand:DI 0 "call_operand" "s,s"))
-	 (match_operand 1 "" "fg,fg"))
-   (use (match_operand:SI 2 "immediate_operand" "O,n"))
-   (clobber (match_scratch:SI 3 "=l,l"))]
-  "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
-   && (INTVAL (operands[2]) & CALL_LONG) == 0"
-  "*
-{
-  /* Indirect calls should go through call_indirect */
-  if (GET_CODE (operands[0]) == REG)
-    abort ();
-
-  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
-    output_asm_insn (\"crxor 6,6,6\", operands);
-
-  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
-    output_asm_insn (\"creqv 6,6,6\", operands);
-
-  return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "8,12")])
-
-(define_insn "*call_nonlocal_sysv"
-  [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
-	 (match_operand 1 "" "fg,fg"))
-   (use (match_operand:SI 2 "immediate_operand" "O,n"))
-   (clobber (match_scratch:SI 3 "=l,l"))]
-  "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-   && (INTVAL (operands[2]) & CALL_LONG) == 0"
-  "*
-{
-  /* Indirect calls should go through call_indirect */
-  if (GET_CODE (operands[0]) == REG)
-    abort ();
-
-  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
-    output_asm_insn (\"crxor 6,6,6\", operands);
-
-  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
-    output_asm_insn (\"creqv 6,6,6\", operands);
-
-  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "4,8")])
-
-(define_insn "*ret_call_nonlocal_aix32"
-  [(set (match_operand 0 "" "=fg,fg")
-	(call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
-	      (match_operand 2 "" "fg,fg")))
-   (use (match_operand:SI 3 "immediate_operand" "O,n"))
-   (clobber (match_scratch:SI 4 "=l,l"))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
-   && (INTVAL (operands[3]) & CALL_LONG) == 0"
-  "*
-{
-  /* This should be handled by call_value_indirect */
-  if (GET_CODE (operands[1]) == REG)
-    abort ();
-
-  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
-    output_asm_insn (\"crxor 6,6,6\", operands);
-
-  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
-    output_asm_insn (\"creqv 6,6,6\", operands);
-
-  return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "8,12")])
-
-(define_insn "*ret_call_nonlocal_aix64"
-  [(set (match_operand 0 "" "=fg,fg")
-	(call (mem:SI (match_operand:DI 1 "call_operand" "s,s"))
-	      (match_operand 2 "" "fg,fg")))
-   (use (match_operand:SI 3 "immediate_operand" "O,n"))
-   (clobber (match_scratch:SI 4 "=l,l"))]
-  "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
-   && (INTVAL (operands[3]) & CALL_LONG) == 0"
-  "*
-{
-  /* This should be handled by call_value_indirect */
-  if (GET_CODE (operands[1]) == REG)
-    abort ();
-
-  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
-    output_asm_insn (\"crxor 6,6,6\", operands);
-
-  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
-    output_asm_insn (\"creqv 6,6,6\", operands);
-
-  return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "8,12")])
-
-(define_insn "*ret_call_nonlocal_sysv"
-  [(set (match_operand 0 "" "=fg,fg")
-	(call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
-	      (match_operand 2 "" "fg,fg")))
-   (use (match_operand:SI 3 "immediate_operand" "O,n"))
-   (clobber (match_scratch:SI 4 "=l,l"))]
-  "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
-   && (INTVAL (operands[3]) & CALL_LONG) == 0"
-  "*
-{
-  /* This should be handled by call_value_indirect */
-  if (GET_CODE (operands[1]) == REG)
-    abort ();
-
-  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
-    output_asm_insn (\"crxor 6,6,6\", operands);
-
-  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
-    output_asm_insn (\"creqv 6,6,6\", operands);
-
-  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "4,8")])
-
-;; Call subroutine returning any type.
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-;; V.4 specific code to initialize the PIC register
-
-(define_insn "init_v4_pic"
-  [(set (match_operand:SI 0 "register_operand" "=l")
-	(unspec [(const_int 0)] 7))]
-  "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS"
-  "bl _GLOBAL_OFFSET_TABLE_@local-4"
-  [(set_attr "type" "branch")
-   (set_attr "length" "4")])
-
-
-;; Compare insns are next.  Note that the RS/6000 has two types of compares,
-;; signed & unsigned, and one type of branch.
-;;
-;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
-;; insns, and branches.  We store the operands of compares until we see
-;; how it is used.
-(define_expand "cmpsi"
-  [(set (cc0)
-        (compare (match_operand:SI 0 "gpc_reg_operand" "")
-  		 (match_operand:SI 1 "reg_or_short_operand" "")))]
-  ""
-  "
-{
-  /* Take care of the possibility that operands[1] might be negative but
-     this might be a logical operation.  That insn doesn't exist.  */
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL (operands[1]) < 0)
-    operands[1] = force_reg (SImode, operands[1]);
-
-  rs6000_compare_op0 = operands[0];
-  rs6000_compare_op1 = operands[1];
-  rs6000_compare_fp_p = 0;
-  DONE;
-}")
-
-(define_expand "cmpdi"
-  [(set (cc0)
-        (compare (match_operand:DI 0 "gpc_reg_operand" "")
-  		 (match_operand:DI 1 "reg_or_short_operand" "")))]
-  "TARGET_POWERPC64"
-  "
-{
-  /* Take care of the possibility that operands[1] might be negative but
-     this might be a logical operation.  That insn doesn't exist.  */
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL (operands[1]) < 0)
-    operands[1] = force_reg (DImode, operands[1]);
-
-  rs6000_compare_op0 = operands[0];
-  rs6000_compare_op1 = operands[1];
-  rs6000_compare_fp_p = 0;
-  DONE;
-}")
-
-(define_expand "cmpsf"
-  [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
-		       (match_operand:SF 1 "gpc_reg_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "
-{
-  rs6000_compare_op0 = operands[0];
-  rs6000_compare_op1 = operands[1];
-  rs6000_compare_fp_p = 1;
-  DONE;
-}")
-
-(define_expand "cmpdf"
-  [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
-		       (match_operand:DF 1 "gpc_reg_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "
-{
-  rs6000_compare_op0 = operands[0];
-  rs6000_compare_op1 = operands[1];
-  rs6000_compare_fp_p = 1;
-  DONE;
-}")
-
-(define_expand "beq"
-  [(set (match_dup 2) (match_dup 1))
-   (set (pc)
-	(if_then_else (eq (match_dup 2)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
-  operands[1] = gen_rtx_COMPARE (mode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (mode);
-}")
-
-(define_expand "bne"
-  [(set (match_dup 2) (match_dup 1))
-   (set (pc)
-	(if_then_else (ne (match_dup 2)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
-  operands[1] = gen_rtx_COMPARE (mode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (mode);
-}")
-
-(define_expand "blt"
-  [(set (match_dup 2) (match_dup 1))
-   (set (pc)
-	(if_then_else (lt (match_dup 2)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
-  operands[1] = gen_rtx_COMPARE (mode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (mode);
-}")
-
-(define_expand "bgt"
-  [(set (match_dup 2) (match_dup 1))
-   (set (pc)
-	(if_then_else (gt (match_dup 2)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
-  operands[1] = gen_rtx_COMPARE (mode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (mode);
-}")
-
-(define_expand "ble"
-  [(set (match_dup 2) (match_dup 1))
-   (set (pc)
-	(if_then_else (le (match_dup 2)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
-  operands[1] = gen_rtx_COMPARE (mode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (mode);
-}")
-
-(define_expand "bge"
-  [(set (match_dup 2) (match_dup 1))
-   (set (pc)
-	(if_then_else (ge (match_dup 2)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
-  operands[1] = gen_rtx_COMPARE (mode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (mode);
-}")
-
-(define_expand "bgtu"
-  [(set (match_dup 2) (match_dup 1))
-   (set (pc)
-	(if_then_else (gtu (match_dup 2)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_rtx_COMPARE (CCUNSmode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (CCUNSmode);
-}")
-
-(define_expand "bltu"
-  [(set (match_dup 2) (match_dup 1))
-   (set (pc)
-	(if_then_else (ltu (match_dup 2)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_rtx_COMPARE (CCUNSmode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (CCUNSmode);
-}")
-
-(define_expand "bgeu"
-  [(set (match_dup 2) (match_dup 1))
-   (set (pc)
-	(if_then_else (geu (match_dup 2)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_rtx_COMPARE (CCUNSmode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (CCUNSmode);
-}")
-
-(define_expand "bleu"
-  [(set (match_dup 2) (match_dup 1))
-   (set (pc)
-	(if_then_else (leu (match_dup 2)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_rtx_COMPARE (CCUNSmode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (CCUNSmode);
-}")
-
-;; For SNE, we would prefer that the xor/abs sequence be used for integers.
-;; For SEQ, likewise, except that comparisons with zero should be done
-;; with an scc insns.  However, due to the order that combine see the
-;; resulting insns, we must, in fact, allow SEQ for integers.  Fail in
-;; the cases we don't want to handle.
-(define_expand "seq"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(eq:SI (match_dup 2) (const_int 0)))]
-  ""
-  "
-{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
-  operands[1] = gen_rtx_COMPARE (mode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (mode);
-}")
-
-(define_expand "sne"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ne:SI (match_dup 2) (const_int 0)))]
-  ""
-  "
-{ if (! rs6000_compare_fp_p)
-    FAIL;
-
-  operands[1] = gen_rtx_COMPARE (CCFPmode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (CCFPmode);
-}")
-
-;; A > 0 is best done using the portable sequence, so fail in that case.
-(define_expand "sgt"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(gt:SI (match_dup 2) (const_int 0)))]
-  ""
-  "
-{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
-
-  if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
-    FAIL;
-
-  operands[1] = gen_rtx_COMPARE (mode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (mode);
-}")
-
-;; A < 0 is best done in the portable way for A an integer.
-(define_expand "slt"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(lt:SI (match_dup 2) (const_int 0)))]
-  ""
-  "
-{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
-
-  if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
-    FAIL;
-
-  operands[1] = gen_rtx_COMPARE (mode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (mode);
-}")
-
-(define_expand "sge"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ge:SI (match_dup 2) (const_int 0)))]
-  ""
-  "
-{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
-  operands[1] = gen_rtx_COMPARE (mode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (mode);
-}")
-
-;; A <= 0 is best done the portable way for A an integer.
-(define_expand "sle"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(le:SI (match_dup 2) (const_int 0)))]
-  ""
-  "
-{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
-
-  if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
-    FAIL;
-
-  operands[1] = gen_rtx_COMPARE (mode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (mode);
-}")
-
-(define_expand "sgtu"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(gtu:SI (match_dup 2) (const_int 0)))]
-  ""
-  "
-{ operands[1] = gen_rtx_COMPARE (CCUNSmode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (CCUNSmode);
-}")
-
-(define_expand "sltu"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ltu:SI (match_dup 2) (const_int 0)))]
-  ""
-  "
-{ operands[1] = gen_rtx_COMPARE (CCUNSmode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (CCUNSmode);
-}")
-
-(define_expand "sgeu"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(geu:SI (match_dup 2) (const_int 0)))]
-  ""
-  "
-{ operands[1] = gen_rtx_COMPARE (CCUNSmode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (CCUNSmode);
-}")
-
-(define_expand "sleu"
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(leu:SI (match_dup 2) (const_int 0)))]
-  ""
-  "
-{ operands[1] = gen_rtx_COMPARE (CCUNSmode,
-			 rs6000_compare_op0, rs6000_compare_op1);
-  operands[2] = gen_reg_rtx (CCUNSmode);
-}")
-
-;; Here are the actual compare insns.
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
-	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
-		    (match_operand:SI 2 "reg_or_short_operand" "rI")))]
-  ""
-  "{cmp%I2|cmpw%I2} %0,%1,%2"
-  [(set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
-	(compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
-		    (match_operand:DI 2 "reg_or_short_operand" "rI")))]
-  "TARGET_POWERPC64"
-  "cmpd%I2 %0,%1,%2"
-  [(set_attr "type" "compare")])
-
-;; If we are comparing a register for equality with a large constant,
-;; we can do this with an XOR followed by a compare.  But we need a scratch
-;; register for the result of the XOR.
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_operand" "")
-	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
-		    (match_operand:SI 2 "non_short_cint_operand" "")))
-   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
-  "find_single_use (operands[0], insn, 0)
-   && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
-       || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
-  [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
-   (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
-  "
-{
-  /* Get the constant we are comparing against, C,  and see what it looks like
-     sign-extended to 16 bits.  Then see what constant could be XOR'ed
-     with C to get the sign-extended value.  */
-
-  int c = INTVAL (operands[2]);
-  int sextc = (c << 16) >> 16;
-  int xorv = c ^ sextc;
-
-  operands[4] = GEN_INT (xorv);
-  operands[5] = GEN_INT (sextc);
-}")
-
-(define_insn ""
-  [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
-	(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
-		       (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
-  ""
-  "{cmpl%I2|cmplw%I2} %0,%1,%W2"
-  [(set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
-	(compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
-		       (match_operand:DI 2 "reg_or_u_short_operand" "rI")))]
-  ""
-  "cmpld%I2 %0,%1,%W2"
-  [(set_attr "type" "compare")])
-
-;; The following two insns don't exist as single insns, but if we provide
-;; them, we can swap an add and compare, which will enable us to overlap more
-;; of the required delay between a compare and branch.  We generate code for
-;; them by splitting.
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=y")
-	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
-		    (match_operand:SI 2 "short_cint_operand" "i")))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
-  ""
-  "#"
-  [(set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
-	(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
-		       (match_operand:SI 2 "u_short_cint_operand" "i")))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
-  ""
-  "#"
-  [(set_attr "length" "8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_operand" "")
-	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
-		    (match_operand:SI 2 "short_cint_operand" "")))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
-  ""
-  [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
-
-(define_split
-  [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
-	(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
-		       (match_operand:SI 2 "u_short_cint_operand" "")))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
-  ""
-  [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
-
-(define_insn ""
-  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
-	(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
-		      (match_operand:SF 2 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "fcmpu %0,%1,%2"
-  [(set_attr "type" "fpcompare")])
-
-(define_insn ""
-  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
-	(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
-		      (match_operand:DF 2 "gpc_reg_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "fcmpu %0,%1,%2"
-  [(set_attr "type" "fpcompare")])
-
-;; Now we have the scc insns.  We can do some combinations because of the
-;; way the machine works.
-;;
-;; Note that this is probably faster if we can put an insn between the
-;; mfcr and rlinm, but this is tricky.  Let's leave it for now.  In most
-;; cases the insns below which don't use an intermediate CR field will
-;; be used instead.
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(match_operator:SI 1 "scc_comparison_operator"
-			   [(match_operand 2 "cc_reg_operand" "y")
-			    (const_int 0)]))]
-  ""
-  "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (match_operator:SI 1 "scc_comparison_operator"
-				       [(match_operand 2 "cc_reg_operand" "y")
-					(const_int 0)])
-		    (const_int 0)))
-   (set (match_operand:SI 3 "gpc_reg_operand" "=r")
-	(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
-  ""
-  "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ashift:SI (match_operator:SI 1 "scc_comparison_operator"
-				      [(match_operand 2 "cc_reg_operand" "y")
-				       (const_int 0)])
-		   (match_operand:SI 3 "const_int_operand" "n")))]
-  ""
-  "*
-{
-  int is_bit = ccr_bit (operands[1], 1);
-  int put_bit = 31 - (INTVAL (operands[3]) & 31);
-  int count;
-
-  if (is_bit >= put_bit)
-    count = is_bit - put_bit;
-  else
-    count = 32 - (put_bit - is_bit);
-
-  operands[4] = GEN_INT (count);
-  operands[5] = GEN_INT (put_bit);
-
-  return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
-}"
- [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC
-	 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
-				       [(match_operand 2 "cc_reg_operand" "y")
-					(const_int 0)])
-		    (match_operand:SI 3 "const_int_operand" "n"))
-	 (const_int 0)))
-   (set (match_operand:SI 4 "gpc_reg_operand" "=r")
-	(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
-		   (match_dup 3)))]
-  ""
-  "*
-{
-  int is_bit = ccr_bit (operands[1], 1);
-  int put_bit = 31 - (INTVAL (operands[3]) & 31);
-  int count;
-
-  if (is_bit >= put_bit)
-    count = is_bit - put_bit;
-  else
-    count = 32 - (put_bit - is_bit);
-
-  operands[5] = GEN_INT (count);
-  operands[6] = GEN_INT (put_bit);
-
-  return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
-}"
-  [(set_attr "type" "delayed_compare")
-   (set_attr "length" "12")])
-
-;; If we are comparing the result of two comparisons, this can be done
-;; using creqv or crxor.
-
-(define_insn ""
-  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
-	(compare:CCEQ (match_operator 1 "scc_comparison_operator"
-			      [(match_operand 2 "cc_reg_operand" "y")
-			       (const_int 0)])
-		      (match_operator 3 "scc_comparison_operator"
-			      [(match_operand 4 "cc_reg_operand" "y")
-			       (const_int 0)])))]
-  "REGNO (operands[2]) != REGNO (operands[4])"
-  "*
-{
-  enum rtx_code code1, code2;
-
-  code1 = GET_CODE (operands[1]);
-  code2 = GET_CODE (operands[3]);
-
-  if ((code1 == EQ || code1 == LT || code1 == GT
-       || code1 == LTU || code1 == GTU
-       || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
-      !=
-      (code2 == EQ || code2 == LT || code2 == GT
-       || code2 == LTU || code2 == GTU
-       || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
-    return \"%C1%C3crxor %E0,%j1,%j3\";
-  else
-    return \"%C1%C3creqv %E0,%j1,%j3\";
-}"
-  [(set_attr "length" "12")])
-
-;; There is a 3 cycle delay between consecutive mfcr instructions
-;; so it is useful to combine 2 scc instructions to use only one mfcr.
-
-(define_peephole
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(match_operator:SI 1 "scc_comparison_operator"
-			   [(match_operand 2 "cc_reg_operand" "y")
-			    (const_int 0)]))
-   (set (match_operand:SI 3 "gpc_reg_operand" "=r")
-	(match_operator:SI 4 "scc_comparison_operator"
-			   [(match_operand 5 "cc_reg_operand" "y")
-			    (const_int 0)]))]
-   "REGNO (operands[2]) != REGNO (operands[5])"
-   "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
-   [(set_attr "length" "20")])
-
-;; There are some scc insns that can be done directly, without a compare.
-;; These are faster because they don't involve the communications between
-;; the FXU and branch units.   In fact, we will be replacing all of the
-;; integer scc insns here or in the portable methods in emit_store_flag.
-;;
-;; Also support (neg (scc ..)) since that construct is used to replace
-;; branches, (plus (scc ..) ..) since that construct is common and
-;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
-;; cases where it is no more expensive than (neg (scc ..)).
-
-;; Have reload force a constant into a register for the simple insns that
-;; otherwise won't accept constants.  We do this because it is faster than
-;; the cmp/mfcr sequence we would otherwise generate.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
-	(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
-	       (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
-   (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
-  ""
-  "@
-   xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
-   {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
-   {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
-   {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
-   {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
-  [(set_attr "length" "12,8,12,12,12")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
-	(eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
-	       (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
-   (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
-   subfic %3,%1,0\;adde %0,%3,%1
-   xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
-   xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
-   subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
-  [(set_attr "length" "12,8,12,12,12")])
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
-	(compare:CC
-	 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
-		(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
-	(eq:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
-  ""
-  "@
-   xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
-   {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
-   {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
-   {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
-   {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
-   xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
-   {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1\;cmpli %4,%0,0
-   {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0\;cmpli %4,%0,0
-   {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0\;cmpli %4,%0,0
-   {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0\;cmpli %4,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
-	(compare:CC
-	 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
-		(match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
-	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
-	(eq:DI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
-  "TARGET_POWERPC64"
-  "@
-   xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
-   subfic %3,%1,0\;adde. %0,%3,%1
-   xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
-   xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
-   subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
-   xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
-   subfic %3,%1,0\;adde %0,%3,%1\;cmpli %4,%0,0
-   xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0\;cmpli %4,%0,0
-   xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0\;cmpli %4,%0,0
-   subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0\;cmpli %4,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
-
-;; We have insns of the form shown by the first define_insn below.  If
-;; there is something inside the comparison operation, we must split it.
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (match_operator 1 "comparison_operator"
-				 [(match_operand:SI 2 "" "")
-				  (match_operand:SI 3
-						    "reg_or_cint_operand" "")])
-		 (match_operand:SI 4 "gpc_reg_operand" "")))
-   (clobber (match_operand:SI 5 "register_operand" ""))]
-  "! gpc_reg_operand (operands[2], SImode)"
-  [(set (match_dup 5) (match_dup 2))
-   (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
-			       (match_dup 4)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
-	(plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
-			(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
-  ""
-  "@
-   xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
-   {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
-   {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
-   {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
-   {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
-  [(set_attr "length" "12,8,12,12,12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
-	(compare:CC
-	 (plus:SI
-	  (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
-		 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
-	  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
-  ""
-  "@
-   xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
-   {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
-   {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
-   {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
-   {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
-   xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3\;cmpli %0,%4,0
-   {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3\;cmpli %0,%4,0
-   {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0
-   {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0
-   {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
-
-(define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
-	(compare:CC
-	 (plus:SI
-	  (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
-		 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
-	  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
-	(plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
-  ""
-  "@
-   xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
-   {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
-   {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
-   {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
-   {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
-   xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3\;cmpli %5,%0,0
-   {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3\;cmpli %5,%0,0
-   {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3\;cmpli %5,%0,0
-   {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3\;cmpli %5,%0,0
-   {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3\;cmpli %5,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
-	(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
-		       (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
-  ""
-  "@
-   xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
-   {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
-   {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
-   {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
-   {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
-   [(set_attr "length" "12,8,12,12,12")])
-
-;; Simplify (ne X (const_int 0)) on the PowerPC.  No need to on the Power,
-;; since it nabs/sr is just as fast.
-(define_insn "*ne0"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
-	(lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
-		     (const_int 31)))
-   (clobber (match_scratch:SI 2 "=&r"))]
-  "!TARGET_POWER"
-  "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
-  [(set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
-		     (const_int 63)))
-   (clobber (match_scratch:DI 2 "=&r"))]
-  "TARGET_POWERPC64"
-  "addic %2,%1,-1\;subfe %0,%2,%1"
-  [(set_attr "length" "8")])
-
-;; This is what (plus (ne X (const_int 0)) Y) looks like.
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(plus:SI (lshiftrt:SI
-		  (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
-		  (const_int 31))
-		 (match_operand:SI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 3 "=&r"))]
-  ""
-  "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
-  [(set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(plus:DI (lshiftrt:DI
-		  (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
-		  (const_int 63))
-		 (match_operand:DI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:DI 3 "=&r"))]
-  "TARGET_POWERPC64"
-  "addic %3,%1,-1\;addze %0,%2"
-  [(set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (lshiftrt:SI
-		   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
-		   (const_int 31))
-		  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 "=&r,&r"))]
-  ""
-  "@
-   {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
-   {ai|addic} %3,%1,-1\;{aze|addze} %3,%2\;cmpli %0,%3,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:DI (lshiftrt:DI
-		   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
-		   (const_int 63))
-		  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:DI 3 "=&r,&r"))]
-  "TARGET_POWERPC64"
-  "@
-   addic %3,%1,-1\;addze. %3,%2
-   addic %3,%1,-1\;addze. %3,%2\;cmpdi %0,%3,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (lshiftrt:SI
-		   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
-		   (const_int 31))
-		  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
-		 (match_dup 2)))
-   (clobber (match_scratch:SI 3 "=&r,&r"))]
-  ""
-  "@
-   {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
-   {ai|addic} %3,%1,-1\;{aze|addze} %0,%2\;cmpli %4,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:DI (lshiftrt:DI
-		   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
-		   (const_int 63))
-		  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
-		 (match_dup 2)))
-   (clobber (match_scratch:DI 3 "=&r,&r"))]
-  "TARGET_POWERPC64"
-  "@
-   addic %3,%1,-1\;addze. %0,%2
-   addic %3,%1,-1\;addze. %0,%2\;cmpdi %4,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-	       (match_operand:SI 2 "reg_or_short_operand" "r,O")))
-   (clobber (match_scratch:SI 3 "=r,X"))]
-  "TARGET_POWER"
-  "@
-   doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
-   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-		(match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(le:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 3 "=r,X,r,X"))]
-  "TARGET_POWER"
-  "@
-   doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
-   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
-   doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3\;cmpli %4,%0,0
-   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31\;cmpli %4,%0,0"
-  [(set_attr "type" "compare,delayed_compare,compare,compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			(match_operand:SI 2 "reg_or_short_operand" "r,O"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
-   {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
-   {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
-   doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0
-   {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3\;cmpli %0,%4,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
-   {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3
-   doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3\;cmpli %5,%0,0
-   {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3\;cmpli %5,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		       (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
-  "TARGET_POWER"
-  "@
-   doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
-   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		(match_operand:SI 2 "reg_or_short_operand" "rI")))]
-  ""
-  "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(leu:SI (match_dup 1) (match_dup 2)))]
-   ""
-  "@
-   {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
-   {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0\;cmpli %3,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			 (match_operand:SI 2 "reg_or_short_operand" "rI"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 4 "=&r"))]
-  ""
-  "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
-  [(set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			  (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
-  "@
-   {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
-   {sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %4,%3\;cmpli %0,%4,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			  (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
-  "@
-   {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3
-   {sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3\;cmpli %5,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
-  ""
-  "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
-   [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(and:SI (neg:SI
-		 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			 (match_operand:SI 2 "reg_or_short_operand" "rI")))
-		(match_operand:SI 3 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 4 "=&r"))]
-  ""
-  "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (and:SI (neg:SI
-		  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			  (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
-		 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
-  "@
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %4,%3,%4\;cmpli %0,%4,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (and:SI (neg:SI
-		  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			  (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
-		 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
-  "@
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4\;cmpli %5,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-	       (match_operand:SI 2 "reg_or_short_operand" "rI")))]
-  "TARGET_POWER"
-  "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
-   [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(lt:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
-   doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31\;cmpli %3,%0,0"
-  [(set_attr "type" "delayed_compare,compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(match_operand:SI 2 "reg_or_short_operand" "rI"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 4 "=&r"))]
-  "TARGET_POWER"
-  "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
-   doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %4,%3\;cmpli %0,%4,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
-   doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3\;cmpli %5,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		       (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
-  "TARGET_POWER"
-  "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
-  ""
-  "@
-   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
-   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-		 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(ltu:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "@
-   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
-   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
-   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0\;cmpli %3,%0,0
-   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0\;cmpli %3,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
-		 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
-   (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
-  ""
-  "@
-  {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
-  {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
-  {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
-  {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
- [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  ""
-  "@
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %4,%4,%3\;cmpli %0,%4,0
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %4,%4,%3\;cmpli %0,%4,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  ""
-  "@
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %0,%4,%3\;cmpli %5,%0,0
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %0,%4,%3\;cmpli %5,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
-  ""
-  "@
-   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
-   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
-  [(set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-	       (match_operand:SI 2 "reg_or_short_operand" "rI")))
-   (clobber (match_scratch:SI 3 "=r"))]
-  "TARGET_POWER"
-  "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
-   [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ge:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
-   doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3\;cmpli %4,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(match_operand:SI 2 "reg_or_short_operand" "rI"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 4 "=&r"))]
-  "TARGET_POWER"
-  "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
-   doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
-   doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3\;cmpli %5,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		       (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
-  "TARGET_POWER"
-  "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
-  [(set_attr "length" "12")])
-
-;; This is (and (neg (ge X (const_int 0))) Y).
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(and:SI (neg:SI
-		 (lshiftrt:SI
-		  (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-		  (const_int 31)))
-		(match_operand:SI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 3 "=&r"))]
-  ""
-  "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
-  [(set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (and:SI (neg:SI
-		  (lshiftrt:SI
-		   (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		   (const_int 31)))
-		 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 "=&r,&r"))]
-  ""
-  "@
-   {srai|srawi} %3,%1,31\;andc. %3,%2,%3
-   {srai|srawi} %3,%1,31\;andc %3,%2,%3\;cmpli %0,%3,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (and:SI (neg:SI
-		  (lshiftrt:SI
-		   (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		   (const_int 31)))
-		 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
-				     (const_int 31)))
-		(match_dup 2)))
-   (clobber (match_scratch:SI 3 "=&r,&r"))]
-  ""
-  "@
-   {srai|srawi} %3,%1,31\;andc. %0,%2,%3
-   {srai|srawi} %3,%1,31\;andc %0,%2,%3\;cmpli %4,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
-  ""
-  "@
-   {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
-   {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-		 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(geu:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "@
-   {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
-   {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
-   {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0\;cmpli %3,%0,0
-   {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0\;cmpli %3,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
-  "@
-   {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
-   {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
-  [(set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  ""
-  "@
-   {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
-   {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
-   {sf|subfc} %4,%2,%1\;{aze|addze} %4,%3\;cmpli %0,%4,0
-   {ai|addic} %4,%1,%n2\;{aze|addze} %4,%3\;cmpli %0,%4,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,8,12,12")])
-
-(define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  ""
-  "@
-   {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
-   {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
-   {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3\;cmpli %5,%0,0
-   {ai|addic} %4,%1,%n2\;{aze|addze} %4,%3\;cmpli %5,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,8,12,12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			(match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
-  ""
-  "@
-   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
-   {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(and:SI (neg:SI
-		 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
-		(match_operand:SI 3 "gpc_reg_operand" "r,r")))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
-  "@
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (and:SI (neg:SI
-		  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
-		 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  ""
-  "@
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %4,%3,%4\;cmpli %0,%4,0
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4\;cmpli %0,%4,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (and:SI (neg:SI
-		  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
-		 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  ""
-  "@
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4\;cmpli %5,%0,0
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4\;cmpli %5,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,12,16,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-	       (const_int 0)))]
-  ""
-  "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(const_int 0))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(gt:SI (match_dup 1) (const_int 0)))]
-  ""
-  "@
-   {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
-   {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31\;cmpli %2,%0,0"
-  [(set_attr "type" "delayed_compare,compare")
-   (set_attr "length" "12,8")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-	       (match_operand:SI 2 "reg_or_short_operand" "r")))]
-  "TARGET_POWER"
-  "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		(match_operand:SI 2 "reg_or_short_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(gt:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWER"
-  "@
-   doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
-   doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31\;cmpli %3,%0,0"
-  [(set_attr "type" "delayed_compare,compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(const_int 0))
-		 (match_operand:SI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 3 "=&r"))]
-  ""
-  "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (const_int 0))
-		  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 "=&r,&r"))]
-  ""
-  "@
-   {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
-   {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %3,%2\;cmpli %0,%3"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (const_int 0))
-		  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
-   (clobber (match_scratch:SI 3 "=&r,&r"))]
-  ""
-  "@
-   {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
-   {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %3,%2\;cmpli %4,%3"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(match_operand:SI 2 "reg_or_short_operand" "r"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 4 "=&r"))]
-  "TARGET_POWER"
-  "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
-   doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %4,%3\;cmpli %0,%4,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
-  "TARGET_POWER"
-  "@
-   doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
-   doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3\;cmpli %5,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		       (const_int 0))))]
-  ""
-  "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		       (match_operand:SI 2 "reg_or_short_operand" "r"))))]
-  "TARGET_POWER"
-  "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		(match_operand:SI 2 "reg_or_short_operand" "rI")))]
-  ""
-  "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
-  [(set_attr "length" "12")])
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(gtu:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "@
-   {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
-   {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0\;cmpli %3,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "12,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
-	(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
-			 (match_operand:SI 2 "reg_or_short_operand" "I,r,rI"))
-		 (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r"))]
-  ""
-  "@
-   {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
-  [(set_attr "length" "8,12,12")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  ""
-  "@
-   {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
-   {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3\;cmpli %0,%4,0
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3\;cmpli %0,%4,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12,12,16")])
-
-(define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC
-	 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			  (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
-		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
-  ""
-  "@
-   {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
-   {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3\;cmpli %5,%0,0
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %0,%4,%3\;cmpli %5,%0,0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12,12,16")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
-  ""
-  "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
-  [(set_attr "length" "8")])
-
-;; Define both directions of branch and return.  If we need a reload
-;; register, we'd rather use CR0 since it is much easier to copy a
-;; register CC value to there.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "branch_comparison_operator"
-				      [(match_operand 2
-						      "cc_reg_operand" "x,?y")
-				       (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  if (get_attr_length (insn) == 8)
-    return \"%C1bc %t1,%j1,%l0\";
-  else
-    return \"%C1bc %T1,%j1,%$+8\;b %l0\";
-
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "branch_comparison_operator"
-				      [(match_operand 1
-						      "cc_reg_operand" "x,?y")
-				       (const_int 0)])
-		      (return)
-		      (pc)))]
-  "direct_return ()"
-  "{%C0bcr|%C0bclr} %t0,%j0"
-  [(set_attr "type" "branch")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "branch_comparison_operator"
-				      [(match_operand 2
-						      "cc_reg_operand" "x,?y")
-				       (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  if (get_attr_length (insn) == 8)
-    return \"%C1bc %T1,%j1,%l0\";
-  else
-    return \"%C1bc %t1,%j1,%$+8\;b %l0\";
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "branch_comparison_operator"
-				      [(match_operand 1
-						      "cc_reg_operand" "x,?y")
-				       (const_int 0)])
-		      (pc)
-		      (return)))]
-  "direct_return ()"
-  "{%C0bcr|%C0bclr} %T0,%j0"
-  [(set_attr "type" "branch")
-   (set_attr "length" "8")])
-
-;; Unconditional branch and return.
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "b %l0"
-  [(set_attr "type" "branch")])
-
-(define_insn "return"
-  [(return)]
-  "direct_return ()"
-  "{br|blr}"
-  [(set_attr "type" "jmpreg")])
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
-  ""
-  "@
-   bctr
-   {br|blr}"
-  [(set_attr "type" "jmpreg")])
-
-(define_insn ""
-  [(set (pc) (match_operand:DI 0 "register_operand" "c,l"))]
-  "TARGET_POWERPC64"
-  "@
-   bctr
-   {br|blr}"
-  [(set_attr "type" "jmpreg")])
-
-;; Table jump for switch statements:
-(define_expand "tablejump"
-  [(use (match_operand 0 "" ""))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "
-{
-  if (TARGET_32BIT)
-    emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
-  else
-    emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
-  DONE;
-}")
-
-(define_expand "tablejumpsi"
-  [(set (match_dup 3)
-	(plus:SI (match_operand:SI 0 "" "")
-		 (match_dup 2)))
-   (parallel [(set (pc) (match_dup 3))
-	      (use (label_ref (match_operand 1 "" "")))])]
-  ""
-  "
-{ operands[0] = force_reg (SImode, operands[0]);
-  operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (VOIDmode, operands[1]));
-  operands[3] = gen_reg_rtx (SImode);
-}")
-
-(define_expand "tablejumpdi"
-  [(set (match_dup 3)
-	(plus:DI (match_operand:DI 0 "" "")
-		 (match_dup 2)))
-   (parallel [(set (pc) (match_dup 3))
-	      (use (label_ref (match_operand 1 "" "")))])]
-  ""
-  "
-{ operands[0] = force_reg (DImode, operands[0]);
-  operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (VOIDmode, operands[1]));
-  operands[3] = gen_reg_rtx (DImode);
-}")
-
-(define_insn ""
-  [(set (pc)
-	(match_operand:SI 0 "register_operand" "c,l"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "@
-   bctr
-   {br|blr}"
-  [(set_attr "type" "jmpreg")])
-
-(define_insn ""
-  [(set (pc)
-	(match_operand:DI 0 "register_operand" "c,l"))
-   (use (label_ref (match_operand 1 "" "")))]
-  "TARGET_POWERPC64"
-  "@
-   bctr
-   {br|blr}"
-  [(set_attr "type" "jmpreg")])
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "{cror 0,0,0|nop}")
-
-;; Define the subtract-one-and-jump insns, starting with the template
-;; so loop.c knows what to generate.
-
-(define_expand "decrement_and_branch_on_count"
-  [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "")
-					  (const_int 1))
-				      (label_ref (match_operand 1 "" ""))
-				      (pc)))
-	      (set (match_dup 0)
-		   (plus:SI (match_dup 0)
-			    (const_int -1)))
-	      (clobber (match_scratch:CC 2 ""))
-	      (clobber (match_scratch:SI 3 ""))])]
-  ""
-  "")
-
-;; We need to be able to do this for any operand, including MEM, or we
-;; will cause reload to blow up since we don't allow output reloads on
-;; JUMP_INSNs.
-;; In order that the length attribute is calculated correctly, the
-;; label MUST be operand 0.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
-			  (const_int 1))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))
-   (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
-	(plus:SI (match_dup 1)
-		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x"))
-   (clobber (match_scratch:SI 4 "=X,X,r"))]
-  ""
-  "*
-{
-  if (which_alternative != 0)
-    return \"#\";
-  else if (get_attr_length (insn) == 8)
-    return \"{bdn|bdnz} %l0\";
-  else
-    return \"bdz %$+8\;b %l0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
-			  (const_int 1))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))
-   (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
-	(plus:SI (match_dup 1)
-		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x"))
-   (clobber (match_scratch:SI 4 "=X,X,r"))]
-  ""
-  "*
-{
-  if (which_alternative != 0)
-    return \"#\";
-  else if (get_attr_length (insn) == 8)
-    return \"bdz %l0\";
-  else
-    return \"{bdn|bdnz} %$+8\;b %l0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
-
-;; Similar, but we can use GE since we have a REG_NONNEG.
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))
-   (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
-	(plus:SI (match_dup 1)
-		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&X"))
-   (clobber (match_scratch:SI 4 "=X,X,r"))]
-  "find_reg_note (insn, REG_NONNEG, 0)"
-  "*
-{
-  if (which_alternative != 0)
-    return \"#\";
-  else if (get_attr_length (insn) == 8)
-    return \"{bdn|bdnz} %l0\";
-  else
-    return \"bdz %$+8\;b %l0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))
-   (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
-	(plus:SI (match_dup 1)
-		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&X"))
-   (clobber (match_scratch:SI 4 "=X,X,r"))]
-  "find_reg_note (insn, REG_NONNEG, 0)"
-  "*
-{
-  if (which_alternative != 0)
-    return \"#\";
-  else if (get_attr_length (insn) == 8)
-    return \"bdz %l0\";
-  else
-    return \"{bdn|bdnz} %$+8\;b %l0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
-			  (const_int 1))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))
-   (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
-	(plus:SI (match_dup 1)
-		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x"))
-   (clobber (match_scratch:SI 4 "=X,X,r"))]
-  ""
-  "*
-{
-  if (which_alternative != 0)
-    return \"#\";
-  else if (get_attr_length (insn) == 8)
-    return \"bdz %l0\";
-  else
-    return \"{bdn|bdnz} %$+8\;b %l0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
-			  (const_int 1))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))
-   (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
-	(plus:SI (match_dup 1)
-		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x"))
-   (clobber (match_scratch:SI 4 "=X,X,r"))]
-  ""
-  "*
-{
-  if (which_alternative != 0)
-    return \"#\";
-  else if (get_attr_length (insn) == 8)
-    return \"{bdn|bdnz} %l0\";
-  else
-    return \"bdz %$+8\;b %l0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16")])
-
-(define_split
-  [(set (pc)
-	(if_then_else (match_operator 2 "comparison_operator"
-				      [(match_operand:SI 1 "gpc_reg_operand" "")
-				       (const_int 1)])
-		      (match_operand 5 "" "")
-		      (match_operand 6 "" "")))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (match_dup 1)
-		 (const_int -1)))
-   (clobber (match_scratch:CC 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "reload_completed"
-  [(parallel [(set (match_dup 3)
-		   (compare:CC (plus:SI (match_dup 1)
-					(const_int -1))
-			       (const_int 0)))
-	      (set (match_dup 0)
-		   (plus:SI (match_dup 1)
-			    (const_int -1)))])
-   (set (pc) (if_then_else (match_dup 7)
-			   (match_dup 5)
-			   (match_dup 6)))]
-  "
-{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
-			 const0_rtx); }")
-
-(define_split
-  [(set (pc)
-	(if_then_else (match_operator 2 "comparison_operator"
-				      [(match_operand:SI 1 "gpc_reg_operand" "")
-				       (const_int 1)])
-		      (match_operand 5 "" "")
-		      (match_operand 6 "" "")))
-   (set (match_operand:SI 0 "general_operand" "")
-	(plus:SI (match_dup 1) (const_int -1)))
-   (clobber (match_scratch:CC 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
-  [(parallel [(set (match_dup 3)
-		   (compare:CC (plus:SI (match_dup 1)
-					(const_int -1))
-			       (const_int 0)))
-	      (set (match_dup 4)
-		   (plus:SI (match_dup 1)
-			    (const_int -1)))])
-   (set (match_dup 0)
-	(match_dup 4))
-   (set (pc) (if_then_else (match_dup 7)
-			   (match_dup 5)
-			   (match_dup 6)))]
-  "
-{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
-			 const0_rtx); }")
-
-(define_insn "trap"
-  [(trap_if (const_int 1) (const_int 0))]
-  ""
-  "{t 31,0,0|trap}")
-
-(define_expand "conditional_trap"
-  [(trap_if (match_operator 0 "trap_comparison_operator"
-			    [(match_dup 2) (match_dup 3)])
-	    (match_operand 1 "const_int_operand" ""))]
-  ""
-  "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
-   operands[2] = rs6000_compare_op0;
-   operands[3] = rs6000_compare_op1;")
-
-(define_insn ""
-  [(trap_if (match_operator 0 "trap_comparison_operator"
-                            [(match_operand:SI 1 "register_operand" "r")
-                             (match_operand:SI 2 "reg_or_short_operand" "rI")])
-	    (const_int 0))]
-  ""
-  "t%V0%I2 %1,%2")
-
-
-;; CYGNUS LOCAL -- meissner/branch prediction
-;; Branch prediction insns
-(define_expand "expectsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(expect:SI (match_operand:SI 1 "nonmemory_operand" "")
-		   (match_operand:SI 2 "immediate_operand" "")))]
-  ""
-  "
-{
-  if (CONSTANT_P (operands[1]))
-    {
-      emit_move_insn (operands[0], operands[1]);
-      DONE;
-    }
-}")
-
-(define_insn "*expectsi3_internal"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r,r,r,r")
-	(expect:SI (match_operand:SI 1 "nonmemory_operand" "0,r,I,J,i")
-		   (match_operand:SI 2 "immediate_operand" "n,n,n,n,n")))]
-  ""
-  "@
-   # expect register %0 to be %2
-   mr %0,%1\;# expect register %0 to be %2
-   {lil|li} %0,%1
-   {liu|lis} %0,%v1
-   #"
-  [(set_attr "type" "integer")
-   (set_attr "length" "0,4,4,4,8")])
-
-;; Split a load of a large constant into the appropriate two-insn
-;; sequence.
-
-(define_split
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(expect:SI (match_operand:SI 1 "const_int_operand" "")
-		   (match_operand:SI 2 "immediate_operand" "")))]
-  "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
-   && (INTVAL (operands[1]) & 0xffff) != 0"
-  [(set (match_dup 0)
-	(match_dup 3))
-   (set (match_dup 0)
-	(ior:SI (match_dup 0)
-		(match_dup 4)))]
-  "
-{
-  operands[3] = gen_rtx (CONST_INT, VOIDmode,
-			 INTVAL (operands[1]) & 0xffff0000);
-  operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
-}")
-
-(define_insn "*compare_expect1"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
-	(compare:CC (expect:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-			       (match_operand:SI 2 "immediate_operand" "n"))
-		    (match_operand:SI 3 "reg_or_short_operand" "rI")))]
-  ""
-  "{cmp%I3|cmpw%I3} %0,%1,%3\\t# expect register %1 to be %2"
-  [(set_attr "type" "compare")])
-
-(define_insn "*compare_expect2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
-	(compare:CC (expect:SI (match_operand:DI 1 "gpc_reg_operand" "r")
-			       (match_operand:DI 2 "immediate_operand" "n"))
-		    (match_operand:DI 3 "reg_or_short_operand" "rI")))]
-  "TARGET_POWERPC64"
-  "cmpd%I3 %0,%1,%3\\t# expect register %1 to be %2"
-  [(set_attr "type" "compare")])
-
-(define_insn "*branch_expect1"
-  [(set (pc)
-	(if_then_else (match_operator 1 "branch_comparison_operator"
-				      [(expect (match_operand 2 "cc_reg_operand" "x,?y")
-					       (match_operand:SI 3 "immediate_operand" "n,n"))
-				       (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  if (get_attr_length (insn) == 8)
-    return \"%C1bc%Q3 %t1,%j1,%l0\";
-  else
-    return \"%C1bc%q3 %T1,%j1,%$+8\;b %l0\";
-
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn "*branch_expect2"
-  [(set (pc)
-	(if_then_else (match_operator 0 "branch_comparison_operator"
-				      [(expect (match_operand 1 "cc_reg_operand" "x,?y")
-					       (match_operand:SI 2 "immediate_operand" "n,n"))
-				       (const_int 0)])
-		      (return)
-		      (pc)))]
-  "direct_return ()"
-  "{%C0bcr|%C0bclr}%Q2 %t0,%j0"
-  [(set_attr "type" "branch")
-   (set_attr "length" "8")])
-
-(define_insn "*branch_expect3"
-  [(set (pc)
-	(if_then_else (match_operator 1 "branch_comparison_operator"
-				      [(expect (match_operand 2 "cc_reg_operand" "x,?y")
-					       (match_operand:SI 3 "immediate_operand" "n,n"))
-				       (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  if (get_attr_length (insn) == 8)
-    return \"%C1bc%q3 %T1,%j1,%l0\";
-  else
-    return \"%C1bc%Q3 %t1,%j1,%$+8\;b %l0\";
-}"
-  [(set_attr "type" "branch")])
-
-(define_insn "*branch_expect4"
-  [(set (pc)
-	(if_then_else (match_operator 0 "branch_comparison_operator"
-				      [(expect (match_operand 1 "cc_reg_operand" "x,?y")
-					       (match_operand:SI 2 "immediate_operand" "n,n"))
-				       (const_int 0)])
-		      (pc)
-		      (return)))]
-  "direct_return ()"
-  "{%C0bcr|%C0bclr}%q2 %T0,%j0"
-  [(set_attr "type" "branch")
-   (set_attr "length" "8")])
-;; END CYGNUS LOCAL -- meissner/branch prediction
-
-;; CYGNUS LOCAL -- vmakarov/prolog-epilog instruction scheduling
-
-;; The following is necessary for generation of RTL representation of
-;; prologue and epilogue and subsequent instruction scheduling and
-;; branch delay slot scheduling (if any).
-
-;;
-;;  ....................
-;;
-;;	Function prologue/epilogue
-;;
-;;  ....................
-;;
-
-(define_expand "prologue"
-  [(const_int 1)]
-  "TARGET_SCHED_PROLOG"
-  "
-{
-      rs6000_expand_prologue ();
-      DONE;
-}")
-
-;; At present, don't expand the epilogue, reorg.c will clobber the
-;; return register in compiling gen_lowpart (emit-rtl.c).
- 
-(define_expand "epilogue"
-  [(const_int 2)]
-  "TARGET_SCHED_EPILOG"
-  "
-{
-      rs6000_expand_epilogue ();
-      DONE;
-}")
-
-(define_insn "movesi_from_cr"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-        (unspec [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) (reg:CC 72)
-                 (reg:CC 73) (reg:CC 74) (reg:CC 75)] 101))]
-  "!TARGET_POWERPC64"
-  "mfcr %0")
-
-(define_insn "movedi_from_cr"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-        (unspec [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) (reg:CC 72)
-                 (reg:CC 73) (reg:CC 74) (reg:CC 75)] 102))]
-  "TARGET_POWERPC64"
-  "mfcr %0")
-
-(define_insn "movesi_to_cr"
-  [(set (reg:CC 68) (unspec [(match_operand:SI 0 "gpc_reg_operand" "=r")] 113))
-   (set (reg:CC 69) (unspec [(match_dup 0)] 114))
-   (set (reg:CC 70) (unspec [(match_dup 0)] 115))
-   (set (reg:CC 71) (unspec [(match_dup 0)] 116))
-   (set (reg:CC 72) (unspec [(match_dup 0)] 117))
-   (set (reg:CC 73) (unspec [(match_dup 0)] 118))
-   (set (reg:CC 74) (unspec [(match_dup 0)] 119))
-   (set (reg:CC 75) (unspec [(match_dup 0)] 120))]
-  "!TARGET_POWERPC64"
-  "mtcr %0")
-
-(define_insn "movedi_to_cr"
-  [(set (reg:CC 68) (unspec [(match_operand:DI 0 "gpc_reg_operand" "=r")] 123))
-   (set (reg:CC 69) (unspec [(match_dup 0)] 124))
-   (set (reg:CC 70) (unspec [(match_dup 0)] 125))
-   (set (reg:CC 71) (unspec [(match_dup 0)] 126))
-   (set (reg:CC 72) (unspec [(match_dup 0)] 127))
-   (set (reg:CC 73) (unspec [(match_dup 0)] 128))
-   (set (reg:CC 74) (unspec [(match_dup 0)] 129))
-   (set (reg:CC 75) (unspec [(match_dup 0)] 130))]
-  "TARGET_POWERPC64"
-  "mtcr %0")
-
-(define_insn "loadsi_svr4_relocatable_toc"
-  [(set (reg:SI 30) (unspec [(pc)] 133))
-   (set (pc) (unspec [(pc)] 143))
-   (clobber (reg:SI 65))
-   (clobber (match_operand:SI 0 "gpc_reg_operand" "r"))]
-  ""
-  "*
-{
-  rs6000_output_load_toc_table (asm_out_file, 30, FALSE);
-  return \"# end of toc load\";
-}")
-
-(define_insn "loaddi_svr4_relocatable_toc"
-  [(set (reg:DI 30) (unspec [(pc)] 153))
-   (set (pc) (unspec [(pc)] 154))
-   (clobber (reg:DI 65))
-   (clobber (match_operand:DI 0 "gpc_reg_operand" "r"))]
-  ""
-  "*
-{
-  rs6000_output_load_toc_table (asm_out_file, 30, FALSE);
-  return \"# end of toc load\";
-}")
-
-(define_insn "loadsi_svr4_toc"
-  [(set (reg:SI 30) (unspec [(pc)] 134))]
-  ""
-  "*
-{
-  rs6000_output_load_toc_table (asm_out_file, 30, FALSE);
-  return \"# end of toc load\";
-}")
-
-(define_insn "loadsi_nonsvr4_toc"
-  [(set (reg:SI 30) (unspec [(pc)] 136))
-   (clobber (match_operand:SI 0 "gpc_reg_operand" "r"))]
-  ""
-  "*
-{
-  rs6000_output_load_toc_table (asm_out_file, 30, FALSE);
-  return \"# end of toc load\";
-}")
-
-(define_insn "loaddi_nonsvr4_toc"
-  [(set (reg:DI 30) (unspec [(pc)] 137))
-   (clobber (match_operand:DI 0 "gpc_reg_operand" "r"))]
-  ""
-  "*
-{
-  rs6000_output_load_toc_table (asm_out_file, 30, FALSE);
-  return \"# end of toc load\";
-}")
-
-;; END CYGNUS LOCAL -- vmakarov/prolog-epilog instruction scheduling
diff --git a/gcc/config/rs6000/rtems.h b/gcc/config/rs6000/rtems.h
deleted file mode 100755
index bf14072..0000000
--- a/gcc/config/rs6000/rtems.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Definitions for rtems targeting a PowerPC using elf.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "rs6000/eabi.h"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-DPPC -Drtems -D__rtems__ \
-   -Asystem(rtems) -Acpu(powerpc) -Amachine(powerpc)"
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#ifndef TARGET_MEM_FUNCTIONS
-#define TARGET_MEM_FUNCTIONS
-#endif
-
-#undef STARTFILE_DEFAULT_SPEC
-#define STARTFILE_DEFAULT_SPEC "crt0.o%s"
-
-/* end of rs6000/rtems.h */
diff --git a/gcc/config/rs6000/sol-c0.c b/gcc/config/rs6000/sol-c0.c
deleted file mode 100755
index bf935c3..0000000
--- a/gcc/config/rs6000/sol-c0.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Solaris PowerPC startfile.  */
-/* Copyright (C) 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with other files,
-   some of which are compiled with GCC, to produce an executable,
-   this library does not by itself cause the resulting executable
-   to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-extern char **_environ;
-
-extern int atexit (void (*__func) (void));
-extern void __init (void) __attribute__ ((__longcall__));
-extern void __fini (void) __attribute__ ((__longcall__));
-
-typedef void (*func_ptr) (void);
-int (*__atexit)(func_ptr) = atexit;
-
-/* Exception handling */
-struct ex_shared1 {
-  void	*prev;
-  void	*next;
-  char	*text_start;
-  char	*range_start;
-  char	*text_end;
-  char	*range_end;
-};
-
-struct ex_shared {
-  void (*ex_register) (struct ex_shared1 *);
-  void (*ex_deregister) (struct ex_shared1 *);
-  struct ex_shared1 shared_info;
-};
-
-extern char _ex_text0[], _ex_text1[];
-extern char _ex_range0[], _ex_range1[];
-extern void _ex_register (struct ex_shared1 *);
-extern void _ex_deregister (struct ex_shared1 *);
-extern char _SDA_BASE_[];
-extern char _SDA2_BASE_[];
-
-struct ex_shared shared __attribute__((section(".ex_shared"))) = {
-  _ex_register,
-  _ex_deregister,
-  {
-    (void *)0,
-    (void *)0,
-    _ex_text0,
-    _ex_range0,
-    _ex_text1,
-    _ex_range1
-  }
-};
-
-static void
-deregister (void)
-{
-  (* shared.ex_deregister) (&shared.shared_info);
-}
-
-/* Start function.  */
-void
-_start(int argc, char *argv[], char *envp[], void *auxp, void (*termfunc)())
-{
-  int ret;
-  int dummy = 0;
-
-#if 0
-  /* Disable this for now, it causes an impossible reload.  */
-  /* Load up r13/r2 before we do anything else.  */
-  __asm__ volatile ("mr %%r13,%0;mr %%r2,%1" : "=r" (dummy) : "r" (&_SDA_BASE_[0]), "r" (&_SDA2_BASE_[0]), "r" (dummy));
-#endif
-
-  _environ = envp + dummy;
-
-  /* Register loader termination function (the || dummy is to make sure the above asm
-     is not optimized away).  */
-  if (termfunc)
-    atexit (termfunc);
-
-  /* Register exception handler if needed */
-  if (shared.ex_register)
-    (* shared.ex_register) (&shared.shared_info);
-
-  if (shared.ex_deregister)
-    atexit (deregister);
-
-  /* Call any global constructors and destructors.  */
-  __init ();
-
-  atexit (__fini);
-
-  /* Call the main program now */
-  ret = main (argc, argv, envp, auxp);
-
-  /* Return to the os */
-  exit (ret);
-}
-
-/* Provide a dummy __eabi in case main got compiled without -mcall-solaris.  */
-void
-__eabi ()
-{
-}
diff --git a/gcc/config/rs6000/sol-ci.asm b/gcc/config/rs6000/sol-ci.asm
deleted file mode 100755
index d0eced3..0000000
--- a/gcc/config/rs6000/sol-ci.asm
+++ /dev/null
@@ -1,104 +0,0 @@
-# crti.s for solaris
-
-#   Copyright (C) 1996 Free Software Foundation, Inc.
-#   Written By Michael Meissner
-# 
-# This file is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License as published by the
-# Free Software Foundation; either version 2, or (at your option) any
-# later version.
-# 
-# In addition to the permissions in the GNU General Public License, the
-# Free Software Foundation gives you unlimited permission to link the
-# compiled version of this file with other programs, and to distribute
-# those programs without any restriction coming from the use of this
-# file.  (The General Public License restrictions do apply in other
-# respects; for example, they cover modification of the file, and
-# distribution when not linked into another program.)
-# 
-# This file is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-# General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with this program; see the file COPYING.  If not, write to
-# the Free Software Foundation, 59 Temple Place - Suite 330,
-# Boston, MA 02111-1307, USA.
-# 
-#    As a special exception, if you link this library with files
-#    compiled with GCC to produce an executable, this does not cause
-#    the resulting executable to be covered by the GNU General Public License.
-#    This exception does not however invalidate any other reasons why
-#    the executable file might be covered by the GNU General Public License.
-# 
-
-# This file just supplies labeled starting points for the .got* and other
-# special sections.  It is linked in first before other modules.
- 
-	.file	"scrti.s"
-	.ident	"GNU C scrti.s"
-
-# Start of .text
-	.section ".text"
-	.globl	_ex_text0
-_ex_text0:
-
-# Exception range
-	.section ".exception_ranges","aw"
-	.globl	_ex_range0
-_ex_range0:
-
-# List of C++ constructors
-	.section ".ctors","aw"
-	.globl	__CTOR_LIST__
-	.type	__CTOR_LIST__,@object
-__CTOR_LIST__:
-
-# List of C++ destructors
-	.section ".dtors","aw"
-	.globl	__DTOR_LIST__
-	.type	__DTOR_LIST__,@object
-__DTOR_LIST__:
-
-# Head of __init function used for static constructors in Solaris
-	.section ".init","ax"
-	.align 2
-	.globl __init
-	.type __init,@function
-__init:	stwu	%r1,-16(%r1)
-	mflr	%r0
-	stw	%r31,12(%r1)
-	stw	%r0,16(%r1)
-
-	bl	_GLOBAL_OFFSET_TABLE_-4	# get the GOT address
-	mflr	%r31
-
-#	lwz	%r3,_ex_shared0@got(%r31)
-#	lwz	%r4,-8(%r3)		# _ex_register or 0
-#	cmpi	%cr0,%r4,0
-#	beq	.Lno_reg
-#	mtlr	%r4
-#	blrl
-#.Lno_reg:
-
-# Head of __fini function used for static destructors in Solaris
-	.section ".fini","ax"
-	.align 2
-	.globl __fini
-	.type __fini,@function
-__fini:	stwu	%r1,-16(%r1)
-	mflr	%r0
-	stw	%r31,12(%r1)
-	stw	%r0,16(%r1)
-
-	bl	_GLOBAL_OFFSET_TABLE_-4	# get the GOT address
-	mflr	%r31
-
-# _environ and its evil twin environ, pointing to the environment
-	.section ".sdata","aw"
-	.align 2
-	.globl _environ
-	.space 4
-	.weak	environ
-	.set	environ,_environ
diff --git a/gcc/config/rs6000/sol-cn.asm b/gcc/config/rs6000/sol-cn.asm
deleted file mode 100755
index 2bc992e..0000000
--- a/gcc/config/rs6000/sol-cn.asm
+++ /dev/null
@@ -1,82 +0,0 @@
-# crtn.s for solaris
-
-#   Copyright (C) 1996 Free Software Foundation, Inc.
-#   Written By Michael Meissner
-# 
-# This file is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License as published by the
-# Free Software Foundation; either version 2, or (at your option) any
-# later version.
-# 
-# In addition to the permissions in the GNU General Public License, the
-# Free Software Foundation gives you unlimited permission to link the
-# compiled version of this file with other programs, and to distribute
-# those programs without any restriction coming from the use of this
-# file.  (The General Public License restrictions do apply in other
-# respects; for example, they cover modification of the file, and
-# distribution when not linked into another program.)
-# 
-# This file is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-# General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with this program; see the file COPYING.  If not, write to
-# the Free Software Foundation, 59 Temple Place - Suite 330,
-# Boston, MA 02111-1307, USA.
-# 
-#    As a special exception, if you link this library with files
-#    compiled with GCC to produce an executable, this does not cause
-#    the resulting executable to be covered by the GNU General Public License.
-#    This exception does not however invalidate any other reasons why
-#    the executable file might be covered by the GNU General Public License.
-# 
-
-# This file just supplies labeled ending points for the .got* and other
-# special sections.  It is linked in last after other modules.
- 
-	.file	"scrtn.s"
-	.ident	"GNU C scrtn.s"
-
-# Default versions of exception handling register/deregister
-	.weak	_ex_register
-	.weak	_ex_deregister
-	.set	_ex_register,0
-	.set	_ex_deregister,0
-
-# End list of C++ constructors
-	.section ".ctors","aw"
-	.globl	__CTOR_END__
-	.type	__CTOR_END__,@object
-__CTOR_END__:
-
-# End list of C++ destructors
-	.section ".dtors","aw"
-	.globl	__DTOR_END__
-	.type	__DTOR_END__,@object
-__DTOR_END__:
-
-	.section ".text"
-	.globl	_ex_text1
-_ex_text1:
-
-	.section ".exception_ranges","aw"
-	.globl	_ex_range1
-_ex_range1:
-
-# Tail of __init used for static constructors in Solaris
-	.section ".init","ax"
-	lwz	%r0,16(%r1)
-	lwz	%r31,12(%r1)
-	mtlr	%r0
-	addi	%r1,%r1,16
-	blr
-
-# Tail of __fini used for static destructors in Solaris
-	.section ".fini","ax"
-	lwz	%r0,16(%r1)
-	lwz	%r31,12(%r1)
-	mtlr	%r0
-	addi	%r1,%r1,16
-	blr
diff --git a/gcc/config/rs6000/sol2.h b/gcc/config/rs6000/sol2.h
deleted file mode 100755
index 0f1b13b..0000000
--- a/gcc/config/rs6000/sol2.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* Definitions of target machine for GNU compiler,
-   for IBM RS/6000 running AIX version 3.1.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by David Reese (Dave.Reese@East.Sun.COM)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "rs6000/sysv4le.h"
-
-/* Default ABI to use */
-#undef	RS6000_ABI_NAME
-#define RS6000_ABI_NAME "solaris"
-
-#undef ASM_CPU_SPEC
-#define ASM_CPU_SPEC "-le -s"
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_POWERPC | \
-			MASK_NEW_MNEMONICS | \
-			MASK_LITTLE_ENDIAN | \
-			MASK_REGNAMES)
-
-#undef	LIB_DEFAULT_SPEC
-#define LIB_DEFAULT_SPEC "%(lib_solaris)"
-
-#undef	STARTFILE_DEFAULT_SPEC
-#define STARTFILE_DEFAULT_SPEC "%(startfile_solaris)"
-
-#undef	ENDFILE_DEFAULT_SPEC
-#define ENDFILE_DEFAULT_SPEC "%(endfile_solaris)"
-
-#undef	LINK_START_DEFAULT_SPEC
-#define LINK_START_DEFAULT_SPEC "%(link_start_solaris)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{posix: -D_POSIX_SOURCE}\
-%(cpp_sysv) %(cpp_endian) %(cpp_cpu) \
-%{mmvme: %(cpp_os_mvme) } \
-%{msim: %(cpp_os_sim) } \
-%{mcall-linux: %(cpp_os_linux) } \
-%{mcall-solaris: %(cpp_os_solaris) } \
-%{!mmvme: %{!msim: %{!mcall-linux: %{!mcall-solaris: %(cpp_os_default) }}}}"
-
-#undef	CPP_OS_DEFAULT_SPEC
-#define	CPP_OS_DEFAULT_SPEC "%(cpp_os_solaris)"
-
-#undef	LINK_OS_DEFAULT_SPEC
-#define	LINK_OS_DEFAULT_SPEC "%(link_os_solaris)"
-
-#undef	CPP_ENDIAN_LITTLE_SPEC
-#define	CPP_ENDIAN_LITTLE_SPEC CPP_ENDIAN_SOLARIS_SPEC
-
-/* Don't turn -B into -L if the argument specifies a relative file name.  */
-#undef	RELATIVE_PREFIX_NOT_LINKDIR
-
-#define	DEFAULT_PCC_STRUCT_RETURN 0
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (PowerPC Solaris)");
-
-
-/* Macros to check register numbers against specific register classes.  */
-
-#undef	PREFERRED_DEBUGGING_TYPE
-#define	PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-
-#if 0
-#undef	ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fprintf ((FILE), "\t%s\t", ".lcomm");					\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
-} while (0)
-#endif
-
-/* Like block addresses, stabs line numbers are relative to the
-   current function.  */
-
-/* use .stabd instead of .stabn */
-
-#define	ASM_STABN_OP	".stabd"
-
-#undef  ASM_OUTPUT_SOURCE_LINE
-#define ASM_OUTPUT_SOURCE_LINE(file, line)				\
-do									\
-  {									\
-    static int sym_lineno = 1;						\
-    char *_p;								\
-    fprintf (file, "\t.stabd 68,0,%d,.LM%d-",				\
-	     line, sym_lineno);						\
-    STRIP_NAME_ENCODING (_p, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
-    assemble_name (file, _p);						\
-    fprintf (file, "\n.LM%d:\n", sym_lineno);				\
-    sym_lineno += 1;							\
-  }									\
-while (0)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#undef	ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t[2];							\
-	REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);			\
-	fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n",		\
-		t[0] & 0xffffffff, t[1] & 0xffffffff);			\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str);			\
-	fprintf (FILE, "\t.double %s\n", str);				\
-      }									\
-  }
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#undef	ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t;								\
-	REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
-	fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff);		\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);			\
-	fprintf (FILE, "\t.float %s\n", str);				\
-      }									\
-  }
-
-
-/* Sun-ppc assembler does not permit '.' in some symbol names.
-   Use 'name_.labelno' instead. */
-#undef ASM_FORMAT_PRIVATE_NAME
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s_.%d", (NAME), (LABELNO))) 
-
-
-/* Define this macro as a C expression for the initializer of an
-   array of string to tell the driver program which options are
-   defaults for this target and thus do not need to be handled
-   specially when using `MULTILIB_OPTIONS'.
-
-   Do not define this macro if `MULTILIB_OPTIONS' is not defined in
-   the target makefile fragment or if none of the options listed in
-   `MULTILIB_OPTIONS' are set by default.  *Note Target Fragment::.  */
-
-#undef	MULTILIB_DEFAULTS
-#define	MULTILIB_DEFAULTS { "mlittle", "mcall-solaris" }
-
-#define STDC_0_IN_SYSTEM_HEADERS
diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
deleted file mode 100755
index c0564c3..0000000
--- a/gcc/config/rs6000/sysv4.h
+++ /dev/null
@@ -1,1770 +0,0 @@
-/* Target definitions for GNU compiler for PowerPC running System V.4
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Small data support types */
-enum rs6000_sdata_type {
-  SDATA_NONE,			/* no small data support */
-  SDATA_DATA,			/* just put data in .sbss/.sdata, don't use relocs */
-  SDATA_SYSV,			/* Use r13 to point to .sdata/.sbss */
-  SDATA_EABI			/* Use r13 like above, r2 points to .sdata2/.sbss2 */
-};
-
-extern enum rs6000_sdata_type rs6000_sdata;
-
-/* V.4/eabi switches */
-#define	MASK_NO_BITFIELD_TYPE	0x40000000	/* Set PCC_BITFIELD_TYPE_MATTERS to 0 */
-#define	MASK_STRICT_ALIGN	0x20000000	/* Set STRICT_ALIGNMENT to 1.  */
-#define MASK_RELOCATABLE	0x10000000	/* GOT pointers are PC relative */
-#define	MASK_EABI		0x08000000	/* Adhere to eabi, not System V spec */
-#define MASK_LITTLE_ENDIAN	0x04000000	/* target is little endian */
-#define MASK_REGNAMES		0x02000000	/* use alternate register names.  */
-#define MASK_PROTOTYPE		0x01000000	/* Only prototyped fcns pass variable args */
-/* CYGNUS LOCAL vmakarov */
-#define MASK_NO_BITFIELD_WORD	0x00400000	/* Bitfields cannot cross word boundaries */
-/* END CYGNUS LOCAL */
-
-#define	TARGET_NO_BITFIELD_TYPE	(target_flags & MASK_NO_BITFIELD_TYPE)
-#define TARGET_STRICT_ALIGN	(target_flags & MASK_STRICT_ALIGN)
-#define TARGET_RELOCATABLE	(target_flags & MASK_RELOCATABLE)
-#define TARGET_EABI		(target_flags & MASK_EABI)
-/* CYGNUS LOCAL vmakarov */
-#define TARGET_NO_BITFIELD_WORD	(target_flags & MASK_NO_BITFIELD_WORD)
-/* END CYGNUS LOCAL */
-#define TARGET_LITTLE_ENDIAN	(target_flags & MASK_LITTLE_ENDIAN)
-#define TARGET_REGNAMES		(target_flags & MASK_REGNAMES)
-#define	TARGET_PROTOTYPE	(target_flags & MASK_PROTOTYPE)
-#define	TARGET_TOC		((target_flags & MASK_64BIT)		\
-				 || ((target_flags & (MASK_RELOCATABLE	\
-						      | MASK_MINIMAL_TOC)) \
-				     && flag_pic > 1)			\
-				 || DEFAULT_ABI == ABI_AIX		\
-				 || DEFAULT_ABI == ABI_NT)
-
-#define	TARGET_BITFIELD_TYPE	(! TARGET_NO_BITFIELD_TYPE)
-#define TARGET_BIG_ENDIAN	(! TARGET_LITTLE_ENDIAN)
-#define	TARGET_NO_PROTOTYPE	(! TARGET_PROTOTYPE)
-#define	TARGET_NO_TOC		(! TARGET_TOC)
-#define TARGET_NO_EABI		(! TARGET_EABI)
-/* CYGNUS LOCAL vmakarov */
-#define TARGET_BITFIELD_WORD	(! TARGET_NO_BITFIELD_WORD)
-/* END CYGNUS LOCAL */
-
-/* Pseudo target to indicate whether the object format is ELF
-   (to get around not having conditional compilation in the md file)  */
-#define	TARGET_ELF		1
-
-/* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be just
-   the same as -mminimal-toc.  */
-#undef	SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES						\
-  { "bit-align",	-MASK_NO_BITFIELD_TYPE },			\
-  { "no-bit-align",	 MASK_NO_BITFIELD_TYPE },			\
-  { "strict-align",	 MASK_STRICT_ALIGN },				\
-  { "no-strict-align",	-MASK_STRICT_ALIGN },				\
-  { "relocatable",	 MASK_RELOCATABLE | MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC }, \
-  { "no-relocatable",	-MASK_RELOCATABLE },				\
-  { "relocatable-lib",	 MASK_RELOCATABLE | MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC }, \
-  { "no-relocatable-lib", -MASK_RELOCATABLE },				\
-  { "little-endian",	 MASK_LITTLE_ENDIAN },				\
-  { "little",		 MASK_LITTLE_ENDIAN },				\
-  { "big-endian",	-MASK_LITTLE_ENDIAN },				\
-  { "big",		-MASK_LITTLE_ENDIAN },				\
-  { "no-toc",		 0 },						\
-  { "toc",		 MASK_MINIMAL_TOC },				\
-  { "full-toc",		 MASK_MINIMAL_TOC },				\
-  { "prototype",	 MASK_PROTOTYPE },				\
-  { "no-prototype",	-MASK_PROTOTYPE },				\
-  { "no-traceback",	 0 },						\
-  { "eabi",		 MASK_EABI },					\
-  { "no-eabi",		-MASK_EABI },					\
-/* CYGNUS LOCAL vmakarov */                                             \
-  { "bit-word",		-MASK_NO_BITFIELD_WORD },			\
-  { "no-bit-word",	 MASK_NO_BITFIELD_WORD },			\
-/* END CYGNUS LOCAL */                                                  \
-  { "regnames",		  MASK_REGNAMES },				\
-  { "no-regnames",	 -MASK_REGNAMES },				\
-  { "sdata",		 0 },						\
-  { "no-sdata",		 0 },						\
-  { "sim",		 0 },						\
-  { "ads",		 0 },						\
-  { "yellowknife",	 0 },						\
-  { "mvme",		 0 },						\
-  { "emb",		 0 },						\
-  { "solaris-cclib",	 0 },						\
-  { "shlib",		 0 },						\
-/* CYGNUS LOCAL vmakarov */                                             \
-  { "vxworks",		 0 },						\
-/* END CYGNUS LOCAL */                                                  \
-  EXTRA_SUBTARGET_SWITCHES                                              \
-  { "newlib",		 0 },
-
-/* This is meant to be redefined in the host dependent files */
-#define EXTRA_SUBTARGET_SWITCHES
-
-/* Default ABI to use */
-#define RS6000_ABI_NAME "sysv"
-
-/* Strings provided by SUBTARGET_OPTIONS */
-extern char *rs6000_abi_name;
-extern char *rs6000_sdata_name;
-
-#define SUBTARGET_OPTIONS						\
-  { "call-",  &rs6000_abi_name},					\
-  { "sdata=", &rs6000_sdata_name}
-
-/* Max # of bytes for variables to automatically be put into the .sdata
-   or .sdata2 sections.  */
-extern int g_switch_value;		/* value of the -G xx switch */
-extern int g_switch_set;		/* whether -G xx was passed.  */
-
-#ifndef SDATA_DEFAULT_SIZE
-#define SDATA_DEFAULT_SIZE 8
-#endif
-
-/* Sometimes certain combinations of command options do not make sense
-   on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to
-   get control.  */
-
-#define SUBTARGET_OVERRIDE_OPTIONS					\
-do {									\
-  if (!g_switch_set)							\
-    g_switch_value = SDATA_DEFAULT_SIZE;				\
-									\
-  if (!strcmp (rs6000_abi_name, "sysv"))				\
-    rs6000_current_abi = ABI_V4;					\
-  else if (!strcmp (rs6000_abi_name, "sysv-noeabi"))			\
-    {									\
-      rs6000_current_abi = ABI_V4;					\
-      target_flags &= ~ MASK_EABI;					\
-    }									\
-  else if (!strcmp (rs6000_abi_name, "sysv-eabi")			\
-	   || !strcmp (rs6000_abi_name, "eabi"))			\
-    {									\
-      rs6000_current_abi = ABI_V4;					\
-      target_flags |= MASK_EABI;					\
-    }									\
-  else if (!strcmp (rs6000_abi_name, "aix"))				\
-    {									\
-      rs6000_current_abi = ABI_AIX_NODESC;				\
-      target_flags |= MASK_EABI;					\
-    }									\
-  else if (!strcmp (rs6000_abi_name, "aixdesc"))			\
-    rs6000_current_abi = ABI_AIX;					\
-  else if (!strcmp (rs6000_abi_name, "nt"))				\
-    rs6000_current_abi = ABI_NT;					\
-  else if (!strcmp (rs6000_abi_name, "linux"))				\
-    rs6000_current_abi = ABI_V4;					\
-  else if (!strcmp (rs6000_abi_name, "solaris"))			\
-    rs6000_current_abi = ABI_SOLARIS;					\
-/* CYGNUS LOCAL vmakarov */                                             \
-  else if (!strcmp (rs6000_abi_name, "i960-old"))			\
-    {									\
-      rs6000_current_abi = ABI_V4;					\
-      target_flags |= (MASK_LITTLE_ENDIAN | MASK_EABI			\
-		       | MASK_NO_BITFIELD_WORD);			\
-      target_flags &= ~MASK_STRICT_ALIGN;				\
-    }									\
-/* END CYGNUS LOCAL */                                                  \
-  else									\
-    {									\
-      rs6000_current_abi = ABI_V4;					\
-      error ("Bad value for -mcall-%s", rs6000_abi_name);		\
-    }									\
-									\
-  if (rs6000_sdata_name)						\
-    {									\
-      if (!strcmp (rs6000_sdata_name, "none"))				\
-	rs6000_sdata = SDATA_NONE;					\
-      else if (!strcmp (rs6000_sdata_name, "data"))			\
-	rs6000_sdata = SDATA_DATA;					\
-      else if (!strcmp (rs6000_sdata_name, "default"))			\
-	rs6000_sdata = (TARGET_EABI) ? SDATA_EABI : SDATA_SYSV;		\
-      else if (!strcmp (rs6000_sdata_name, "sysv"))			\
-	rs6000_sdata = SDATA_SYSV;					\
-      else if (!strcmp (rs6000_sdata_name, "eabi"))			\
-	rs6000_sdata = SDATA_EABI;					\
-      else								\
-	error ("Bad value for -msdata=%s", rs6000_sdata_name);		\
-    }									\
-  else if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)		\
-    {									\
-      rs6000_sdata = SDATA_DATA;					\
-      rs6000_sdata_name = "data";					\
-    }									\
-  else									\
-    {									\
-      rs6000_sdata = SDATA_NONE;					\
-      rs6000_sdata_name = "none";					\
-    }									\
-									\
-  if (TARGET_RELOCATABLE &&						\
-      (rs6000_sdata == SDATA_EABI || rs6000_sdata == SDATA_SYSV))	\
-    {									\
-      rs6000_sdata = SDATA_DATA;					\
-      error ("-mrelocatable and -msdata=%s are incompatible.",		\
-	     rs6000_sdata_name);					\
-    }									\
-									\
-  else if (flag_pic &&							\
-	   (rs6000_sdata == SDATA_EABI || rs6000_sdata == SDATA_SYSV))	\
-    {									\
-      rs6000_sdata = SDATA_DATA;					\
-      error ("-f%s and -msdata=%s are incompatible.",			\
-	     (flag_pic > 1) ? "PIC" : "pic",				\
-	     rs6000_sdata_name);					\
-    }									\
-									\
-  if (rs6000_sdata != SDATA_NONE && DEFAULT_ABI != ABI_V4		\
-      && DEFAULT_ABI != ABI_SOLARIS)					\
-    {									\
-      rs6000_sdata = SDATA_NONE;					\
-      error ("-msdata=%s and -mcall-%s are incompatible.",		\
-	     rs6000_sdata_name, rs6000_abi_name);			\
-    }									\
-									\
-  if (TARGET_RELOCATABLE && !TARGET_MINIMAL_TOC)			\
-    {									\
-      target_flags |= MASK_MINIMAL_TOC;					\
-      error ("-mrelocatable and -mno-minimal-toc are incompatible.");	\
-    }									\
-									\
-  if (TARGET_RELOCATABLE &&						\
-      (rs6000_current_abi == ABI_AIX || rs6000_current_abi == ABI_NT))	\
-    {									\
-      target_flags &= ~MASK_RELOCATABLE;				\
-      error ("-mrelocatable and -mcall-%s are incompatible.",		\
-	     rs6000_abi_name);						\
-    }									\
-									\
-  if (flag_pic > 1 &&							\
-      (rs6000_current_abi == ABI_AIX || rs6000_current_abi == ABI_NT))	\
-    {									\
-      flag_pic = 0;							\
-      error ("-fPIC and -mcall-%s are incompatible.",			\
-	     rs6000_abi_name);						\
-    }									\
-									\
-  if (rs6000_current_abi == ABI_AIX && TARGET_LITTLE_ENDIAN)		\
-    {									\
-      target_flags &= ~MASK_LITTLE_ENDIAN;				\
-      error ("-mcall-aixdesc must be big endian");			\
-    }									\
-									\
-  if (rs6000_current_abi == ABI_NT && TARGET_BIG_ENDIAN)		\
-    {									\
-      target_flags |= MASK_LITTLE_ENDIAN;				\
-      error ("-mcall-nt must be little endian");			\
-    }									\
-									\
-  /* Treat -fPIC the same as -mrelocatable */				\
-  if (flag_pic > 1)							\
-    target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC; \
-									\
-  else if (TARGET_RELOCATABLE)						\
-    flag_pic = 2;							\
-									\
-} while (0)
-
-/* Default ABI to compile code for */
-#define DEFAULT_ABI rs6000_current_abi
-
-#define CPP_DEFAULT_SPEC "-D_ARCH_PPC"
-
-#define ASM_DEFAULT_SPEC "-mppc"
-
-#include "rs6000/rs6000.h"
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS)
-
-#undef PROCESSOR_DEFAULT
-#define PROCESSOR_DEFAULT PROCESSOR_PPC601
-
-/* System V.4 uses register 13 as a pointer to the small data area,
-   so it is not available to the normal user.  */
-
-#undef	FIXED_R13
-#define FIXED_R13 1
-
-/* System V.4 passes the first 8 floating arguments in registers,
-   instead of the first 13 like AIX does.  */
-#undef	FP_ARG_MAX_REG
-#define	FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC) \
-			? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
-
-/* Size of the V.4 varargs area if needed */
-#undef	RS6000_VARARGS_AREA
-#define RS6000_VARARGS_AREA ((rs6000_sysv_varargs_p) ? RS6000_VARARGS_SIZE : 0)
-
-/* Override default big endianism */
-#undef  BYTES_BIG_ENDIAN
-#undef  WORDS_BIG_ENDIAN
-#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
-#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
-
-/* Define this to set the endianness to use in libgcc2.c, which can
-   not depend on target_flags.  */
-#if !defined(_LITTLE_ENDIAN) && !defined(__sun__)
-#define LIBGCC2_WORDS_BIG_ENDIAN 1
-#else
-#define LIBGCC2_WORDS_BIG_ENDIAN 0
-#endif
-
-/* Size of the outgoing register save area */
-#undef	RS6000_REG_SAVE
-#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX			\
-			  || DEFAULT_ABI == ABI_AIX_NODESC)		\
-			 ? (TARGET_64BIT ? 64 : 32)			\
-			 : 0)
-
-/* Size of the fixed area on the stack.  For AIX, use the standard 6 word
-   area, otherwise use 2 words to store back chain & LR.  */
-#undef	RS6000_SAVE_AREA
-#define RS6000_SAVE_AREA \
-  (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC) ? 24 : 8) << (TARGET_64BIT ? 1 : 0))
-
-/* Define cutoff for using external functions to save floating point.
-   Currently on V.4, always use inline stores */
-#undef	FP_SAVE_INLINE
-#define FP_SAVE_INLINE(FIRST_REG) ((FIRST_REG) < 64)
-
-/* Don't generate XCOFF debugging information.  */
-
-#undef XCOFF_DEBUGGING_INFO
-
-/* Don't use the COFF object file format.  */
-
-#undef OBJECT_FORMAT_COFF
-
-/* Don't bother to output .extern pseudo-ops.  They are not needed by
-   ELF assemblers.  */
-
-#undef ASM_OUTPUT_EXTERNAL
-
-/* Put jump tables in read-only memory, rather than in .text.  */
-#undef JUMP_TABLES_IN_TEXT_SECTION
-#define JUMP_TABLES_IN_TEXT_SECTION 0
-
-/* Disable AIX-ism that disables turning -B into -L if the argument specifies a
-   relative file name.  This breaks setting GCC_EXEC_PREFIX to D:\path under
-   Windows.  */
-#undef RELATIVE_PREFIX_NOT_LINKDIR
-
-/* Undefine some things which are defined by the generic svr4.h.  */
-
-#undef ASM_FILE_END
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-#undef READONLY_DATA_SECTION
-#undef SELECT_SECTION
-#undef ASM_DECLARE_FUNCTION_NAME
-#undef ASM_OUTPUT_CONSTRUCTOR
-#undef ASM_OUTPUT_DESTRUCTOR
-
-/* Use the regular svr4 definitions.  */
-
-#include "svr4.h"
-
-/* Prefix and suffix to use to saving floating point */
-#undef	SAVE_FP_PREFIX
-#undef	SAVE_FP_SUFFIX
-#define	SAVE_FP_PREFIX "_savefpr_"
-#define SAVE_FP_SUFFIX "_l"
-
-/* Prefix and suffix to use to restoring floating point */
-#undef	RESTORE_FP_PREFIX
-#undef	RESTORE_FP_SUFFIX
-#define	RESTORE_FP_PREFIX "_restfpr_"
-#define RESTORE_FP_SUFFIX "_l"
-
-/* Type used for ptrdiff_t, as a string used in a declaration.  */
-#undef	PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-/* CYGNUS LOCAL vmakarov */
-#if 0
-/* END CYGNUS LOCAL */
-
-/* Variables to set wchar_t size/type */
-extern char *rs6000_wchar_type;
-extern int rs6000_wchar_type_size;
-
-/* Type used for wchar_t, as a string used in a declaration.  */
-#undef	WCHAR_TYPE
-#define WCHAR_TYPE rs6000_wchar_type
-
-/* Width of wchar_t in bits.  */
-#undef	WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE rs6000_wchar_type_size
-
-/* Tell the preprocessor the maximum size of wchar_t.  */
-#undef  MAX_WCHAR_TYPE_SIZE
-#define MAX_WCHAR_TYPE_SIZE INT_TYPE_SIZE
-
-/* Tell cccp we'll set up __WCHAR_TYPE__ */
-#undef	NO_BUILTIN_WCHAR_TYPE
-#define NO_BUILTIN_WCHAR_TYPE 1
-
-/* CYGNUS LOCAL vmakarov */
-#else
-/* Type used for wchar_t, as a string used in a declaration.  */
-#undef	WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-/* Width of wchar_t in bits.  */
-#undef	WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 32
-
-#endif
-/* END CYGNUS LOCAL */
-
-/* Make int foo : 8 not cause structures to be aligned to an int boundary */
-
-#undef	PCC_BITFIELD_TYPE_MATTERS
-#define	PCC_BITFIELD_TYPE_MATTERS (TARGET_BITFIELD_TYPE)
-
-/* CYGNUS LOCAL vmakarov */
-#undef	BITFIELD_NBYTES_LIMITED
-#define	BITFIELD_NBYTES_LIMITED (TARGET_NO_BITFIELD_WORD)
-/* END CYGNUS LOCAL */
-
-/* Define this macro to be the value 1 if instructions will fail to
-   work if given data not on the nominal alignment.  If instructions
-   will merely go slower in that case, define this macro as 0.  */
-#undef	STRICT_ALIGNMENT
-#define	STRICT_ALIGNMENT (TARGET_STRICT_ALIGN)
-
-/* Alignment in bits of the stack boundary.  Note, in order to allow building
-   one set of libraries with -mno-eabi instead of eabi libraries and non-eabi
-   versions, just use 64 as the stack boundary.  */
-#undef	STACK_BOUNDARY
-#define	STACK_BOUNDARY	64
-
-/* Real stack boundary as mandated by the appropriate ABI */
-#define ABI_STACK_BOUNDARY ((TARGET_EABI) ? 64 : 128)
-
-/* No data type wants to be aligned rounder than this.  */
-#undef	BIGGEST_ALIGNMENT
-#define BIGGEST_ALIGNMENT ((TARGET_EABI) ? 64 : 128)
-
-#undef  BIGGEST_FIELD_ALIGNMENT
-#undef  ADJUST_FIELD_ALIGN
-#undef  ROUND_TYPE_ALIGN
-
-/* Use ELF style section commands.  */
-
-#undef TEXT_SECTION_ASM_OP
-#define TEXT_SECTION_ASM_OP	"\t.section\t\".text\""
-
-#undef DATA_SECTION_ASM_OP
-#define DATA_SECTION_ASM_OP	"\t.section\t\".data\""
-
-#undef BSS_SECTION_ASM_OP
-#define BSS_SECTION_ASM_OP	"\t.section\t\".bss\""
-
-#undef INIT_SECTION_ASM_OP
-#define INIT_SECTION_ASM_OP "\t.section\t\".init\",\"ax\""
-
-#undef FINI_SECTION_ASM_OP
-#define FINI_SECTION_ASM_OP "\t.section\t\".fini\",\"ax\""
-
-#define TOC_SECTION_ASM_OP "\t.section\t\".got\",\"aw\""
-
-/* Put PC relative got entries in .got2 */
-#define MINIMAL_TOC_SECTION_ASM_OP \
-  ((TARGET_RELOCATABLE || flag_pic) ? "\t.section\t\".got2\",\"aw\"" : "\t.section\t\".got1\",\"aw\"")
-
-/* Put relocatable data in .data, not .rodata so initialized pointers can be updated */
-#undef	CONST_SECTION_ASM_OP
-#define CONST_SECTION_ASM_OP \
-  ((TARGET_RELOCATABLE || flag_pic) ? "\t.section\t\".data\"\t# .rodata" : "\t.section\t\".rodata\"")
-
-
-#define SDATA_SECTION_ASM_OP "\t.section\t\".sdata\",\"aw\""
-#define SDATA2_SECTION_ASM_OP "\t.section\t\".sdata2\",\"a\""
-#define SBSS_SECTION_ASM_OP \
-  ((DEFAULT_ABI == ABI_SOLARIS) ? "\t.section\t\".sbss\",\"aw\"" : "\t.section\t\".sbss\",\"aw\",@nobits")
-
-
-/* Besides the usual ELF sections, we need a toc section.  */
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_ctors, in_dtors, in_toc, in_sdata, in_sdata2, in_sbss, in_init, in_fini
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CONST_SECTION_FUNCTION						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION						\
-  TOC_SECTION_FUNCTION							\
-  SDATA_SECTION_FUNCTION						\
-  SDATA2_SECTION_FUNCTION						\
-  SBSS_SECTION_FUNCTION							\
-  INIT_SECTION_FUNCTION							\
-  FINI_SECTION_FUNCTION
-
-extern void toc_section (), sdata_section (), sdata2_section ();
-extern void sbss_section ();
-
-#define TOC_SECTION_FUNCTION						\
-void									\
-toc_section ()								\
-{									\
-  if (in_section != in_toc)						\
-    {									\
-      in_section = in_toc;						\
-      if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)		\
-	  && TARGET_MINIMAL_TOC						\
-	  && !TARGET_RELOCATABLE)					\
-	{								\
-	  if (! toc_initialized)					\
-	    {								\
-	      toc_initialized = 1;					\
-	      fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);	\
-	      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LCTOC", 0);	\
-	      fprintf (asm_out_file, "\t.tc ");				\
-	      ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],"); \
-	      ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1"); \
-	      fprintf (asm_out_file, "\n");				\
-									\
-	      fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); \
-	      ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1"); \
-	      fprintf (asm_out_file, " = .+32768\n");			\
-	    }								\
-	  else								\
-	    fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);	\
-	}								\
-      else if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)	\
-	       && !TARGET_RELOCATABLE)					\
-	fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);		\
-      else								\
-	{								\
-	  fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);	\
-	  if (! toc_initialized)					\
-	    {								\
-	      ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1"); \
-	      fprintf (asm_out_file, " = .+32768\n");			\
-	      toc_initialized = 1;					\
-	    }								\
-	}								\
-    }									\
-}
-
-#define SDATA_SECTION_FUNCTION						\
-void									\
-sdata_section ()							\
-{									\
-  if (in_section != in_sdata)						\
-    {									\
-      in_section = in_sdata;						\
-      fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP);		\
-    }									\
-}
-
-#define SDATA2_SECTION_FUNCTION						\
-void									\
-sdata2_section ()							\
-{									\
-  if (in_section != in_sdata2)						\
-    {									\
-      in_section = in_sdata2;						\
-      fprintf (asm_out_file, "%s\n", SDATA2_SECTION_ASM_OP);		\
-    }									\
-}
-
-#define SBSS_SECTION_FUNCTION						\
-void									\
-sbss_section ()								\
-{									\
-  if (in_section != in_sbss)						\
-    {									\
-      in_section = in_sbss;						\
-      fprintf (asm_out_file, "%s\n", SBSS_SECTION_ASM_OP);		\
-    }									\
-}
-
-#define INIT_SECTION_FUNCTION						\
-void									\
-init_section ()								\
-{									\
-  if (in_section != in_init)						\
-    {									\
-      in_section = in_init;						\
-      fprintf (asm_out_file, "%s\n", INIT_SECTION_ASM_OP);		\
-    }									\
-}
-
-#define FINI_SECTION_FUNCTION						\
-void									\
-fini_section ()								\
-{									\
-  if (in_section != in_fini)						\
-    {									\
-      in_section = in_fini;						\
-      fprintf (asm_out_file, "%s\n", FINI_SECTION_ASM_OP);		\
-    }									\
-}
-
-/* A C statement or statements to switch to the appropriate section
-   for output of RTX in mode MODE.  You can assume that RTX is some
-   kind of constant in RTL.  The argument MODE is redundant except in
-   the case of a `const_int' rtx.  Select the section by calling
-   `text_section' or one of the alternatives for other sections.
-
-   Do not define this macro if you put all constants in the read-only
-   data section.  */
-
-extern void rs6000_select_rtx_section (), rs6000_select_section ();
-
-#undef SELECT_RTX_SECTION
-#define SELECT_RTX_SECTION(MODE, X) rs6000_select_rtx_section (MODE, X)
-
-/* A C statement or statements to switch to the appropriate
-   section for output of DECL.  DECL is either a `VAR_DECL' node
-   or a constant of some sort.  RELOC indicates whether forming
-   the initial value of DECL requires link-time relocations.  */
-
-#undef SELECT_SECTION
-#define SELECT_SECTION(DECL,RELOC) rs6000_select_section (DECL, RELOC)
-
-/* Return non-zero if this entry is to be written into the constant pool
-   in a special way.  We do so if this is a SYMBOL_REF, LABEL_REF or a CONST
-   containing one of them.  If -mfp-in-toc (the default), we also do
-   this for floating-point constants.  We actually can only do this
-   if the FP formats of the target and host machines are the same, but
-   we can't check that since not every file that uses
-   GO_IF_LEGITIMATE_ADDRESS_P includes real.h.
-
-   Unlike AIX, we don't key off of -mminimal-toc, but instead do not
-   allow floating point constants in the TOC if -mrelocatable.  */
-
-#undef	ASM_OUTPUT_SPECIAL_POOL_ENTRY_P
-#define ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X)				\
-  (TARGET_TOC								\
-   && (GET_CODE (X) == SYMBOL_REF					\
-       || (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS	\
-	   && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF)		\
-       || GET_CODE (X) == LABEL_REF					\
-       || (!TARGET_NO_FP_IN_TOC						\
-	   && !TARGET_RELOCATABLE					\
-	   && GET_CODE (X) == CONST_DOUBLE				\
-	   && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT		\
-	   && BITS_PER_WORD == HOST_BITS_PER_INT)))
-
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare a function properly.
-   Some svr4 assemblers need to also have something extra said about the
-   function's return value.  We allow for that here.  */
-
-extern int rs6000_pic_labelno;
-
-/* CYGNUS LOCAL vmakarov */
-#undef USER_LABEL_PREFIX
-/* END CYGNUS LOCAL */
-
-#undef	ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-  do {									\
-    char *orig_name;							\
-    char *init_ptr = (TARGET_64BIT) ? ".quad" : ".long";		\
-    STRIP_NAME_ENCODING (orig_name, NAME);				\
-									\
-    if (TARGET_RELOCATABLE && (get_pool_size () != 0 || profile_flag))	\
-      {									\
-	char buf[256], *buf_ptr;					\
-									\
-	ASM_OUTPUT_INTERNAL_LABEL (FILE, "LCL", rs6000_pic_labelno);	\
-									\
-	ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);			\
-	STRIP_NAME_ENCODING (buf_ptr, buf);				\
-	fprintf (FILE, "\t%s %s-", init_ptr, buf_ptr);			\
-									\
-	ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);	\
-	fprintf (FILE, "%s\n", buf_ptr);				\
-      }									\
-									\
-    asm_fprintf (FILE, "\t%s\t %U%s,", TYPE_ASM_OP, orig_name);	 /* CYGNUS LOCAL vmakarov: asm_fprintf */ \
-    fprintf (FILE, TYPE_OPERAND_FMT, "function");			\
-    putc ('\n', FILE);							\
-    ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));			\
-									\
-    if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)		\
-      {									\
-	char *desc_name = orig_name;					\
-									\
-	while (*desc_name == '.')					\
-	  desc_name++;							\
-									\
-	if (TREE_PUBLIC (DECL))						\
-	  fprintf (FILE, "\t.globl %s\n", desc_name);			\
-									\
-	fprintf (FILE, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);		\
-	fprintf (FILE, "%s:\n", desc_name);				\
-	fprintf (FILE, "\t%s %s\n", init_ptr, orig_name);		\
-	fprintf (FILE, "\t%s _GLOBAL_OFFSET_TABLE_\n", init_ptr);	\
-	if (DEFAULT_ABI == ABI_AIX)					\
-	  fprintf (FILE, "\t%s 0\n", init_ptr);				\
-	fprintf (FILE, "\t.previous\n");				\
-      }									\
-    asm_fprintf (FILE, "%U%s:\n", orig_name); /* CYGNUS LOCAL vmakarov: asm_fprintf */	\
-  } while (0)
-
-/* How to renumber registers for dbx and gdb.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* CYGNUS LOCAL vmakarov */
-/* If defined, C string expressions to be used for the `%R', `%L',
-   `%U', and `%I' options of `asm_fprintf' (see `final.c').  These
-   are useful when a single `md' file must support multiple assembler
-   formats.  In that case, the various `tm.h' files can define these
-   macros differently.  */
-
-#ifndef	REGISTER_PREFIX
-#define REGISTER_PREFIX ""
-#endif
-
-#ifndef	LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX "."
-#endif
-
-#ifndef	USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-#endif
-
-#ifndef	IMMEDIATE_PREFIX
-#define IMMEDIATE_PREFIX ""
-#endif
-/* END CYGNUS LOCAL */
-
-/* svr4.h overrides ASM_OUTPUT_INTERNAL_LABEL.  */
-
-#undef ASM_OUTPUT_INTERNAL_LABEL_PREFIX
-#define ASM_OUTPUT_INTERNAL_LABEL_PREFIX(FILE,PREFIX)	\
-  asm_fprintf (FILE, "%L%s", PREFIX) /* CYGNUS LOCAL vmakarov: asm_fprintf */
-
-/* This is how to allocate empty space in some section.  Use .space
-   instead of .zero because the Solaris PowerPC assembler doesn't
-   like it, and gas accepts either syntax.  */
-
-#undef	SKIP_ASM_OP
-#define SKIP_ASM_OP	".space"
-
-/* This says how to output assembler code to declare an
-   uninitialized internal linkage data object.  Under SVR4,
-   the linker seems to want the alignment of data objects
-   to depend on their types.  We do exactly that here.  */
-
-#ifndef LOCAL_ASM_OP
-#define LOCAL_ASM_OP	".local"
-#endif
-
-#ifndef LCOMM_ASM_OP
-#define LCOMM_ASM_OP	".lcomm"
-#endif
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  if (rs6000_sdata != SDATA_NONE && (SIZE) > 0				\
-      && (SIZE) <= g_switch_value)					\
-    {									\
-      sbss_section ();							\
-      ASM_OUTPUT_ALIGN (FILE, exact_log2 (ALIGN / BITS_PER_UNIT));	\
-      ASM_OUTPUT_LABEL (FILE, NAME);					\
-      ASM_OUTPUT_SKIP (FILE, SIZE);					\
-      if (!flag_inhibit_size_directive && (SIZE) > 0)			\
-	{								\
-	  fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			\
-	  assemble_name (FILE, NAME);					\
-	  fprintf (FILE, ",%d\n",  SIZE);				\
-	}								\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\t%s\t", LCOMM_ASM_OP);				\
-      assemble_name ((FILE), (NAME));					\
-      fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
-    }									\
-} while (0)
-
-/* Describe how to emit uninitialized external linkage items  */
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN)		\
-do {									\
-  ASM_GLOBALIZE_LABEL (FILE, NAME);					\
-  ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN);			\
-} while (0)
-
-/* Switch  Recognition by gcc.c.  Add -G xx support */
-
-#undef SWITCH_TAKES_ARG
-#define SWITCH_TAKES_ARG(CHAR)						\
-  ((CHAR) == 'D' || (CHAR) == 'U' || (CHAR) == 'o'			\
-   || (CHAR) == 'e' || (CHAR) == 'T' || (CHAR) == 'u'			\
-   || (CHAR) == 'I' || (CHAR) == 'm' || (CHAR) == 'x'			\
-   || (CHAR) == 'L' || (CHAR) == 'A' || (CHAR) == 'V'			\
-   || (CHAR) == 'B' || (CHAR) == 'b' || (CHAR) == 'G')
-
-/* Output .file.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)						\
-do {									\
-  output_file_directive ((FILE), main_input_filename);			\
-  rs6000_file_start (FILE, TARGET_CPU_DEFAULT);				\
-} while (0)
-
-
-/* This is how to output an assembler line defining an `int' constant.
-   For -mrelocatable, we mark all addresses that need to be fixed up
-   in the .fixup section.  */
-#undef	ASM_OUTPUT_INT
-#define ASM_OUTPUT_INT(FILE,VALUE)					\
-do {									\
-  static int recurse = 0;						\
-  if ((TARGET_RELOCATABLE || flag_pic)					\
-      && in_section != in_toc						\
-      && in_section != in_text						\
-      && in_section != in_ctors						\
-      && in_section != in_dtors						\
-      && !recurse							\
-      && GET_CODE (VALUE) != CONST_INT					\
-      && GET_CODE (VALUE) != CONST_DOUBLE				\
-      && CONSTANT_P (VALUE))						\
-    {									\
-      static int labelno = 0;						\
-      char buf[256], *p;						\
-									\
-      recurse = 1;							\
-      ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", labelno++);		\
-      STRIP_NAME_ENCODING (p, buf);					\
-      fprintf (FILE, "%s:\n", p);					\
-      fprintf (FILE, "\t.long (");					\
-      output_addr_const (FILE, (VALUE));				\
-      fprintf (FILE, ")@fixup\n");					\
-      fprintf (FILE, "\t.section\t\".fixup\",\"aw\"\n");		\
-      ASM_OUTPUT_ALIGN (FILE, 2);					\
-      fprintf (FILE, "\t.long\t%s\n", p);				\
-      fprintf (FILE, "\t.previous\n");					\
-      recurse = 0;							\
-    }									\
-  /* Remove initial .'s to turn a -mcall-aixdesc or -mcall-nt function	\
-     address into the address of the descriptor, not the function	\
-     itself.  */							\
-  else if (GET_CODE (VALUE) == SYMBOL_REF				\
-	   && XSTR (VALUE, 0)[0] == '.'					\
-	   && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT))	\
-    {									\
-      char *name = XSTR (VALUE, 0);					\
-      while (*name == '.')						\
-	name++;								\
-									\
-      fprintf (FILE, "\t.long %s\n", name);				\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\t.long ");					\
-      output_addr_const (FILE, (VALUE));				\
-      fprintf (FILE, "\n");						\
-    }									\
-} while (0)
-
-/* This is the end of what might become sysv4.h.  */
-
-/* Allow stabs and dwarf, for now, make stabs the default debugging type,
-   not dwarf since G++ doesn't support dwarf. */
-#undef	PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#define	DBX_DEBUGGING_INFO
-#define	DWARF_DEBUGGING_INFO
-
-/* If we are referencing a function that is static or is known to be
-   in this file, make the SYMBOL_REF special.  We can use this to indicate
-   that we can branch to this function without emitting a no-op after the
-   call.  For real AIX and NT calling sequences, we also replace the
-   function name with the real name (1 or 2 leading .'s), rather than
-   the function descriptor name.  This saves a lot of overriding code
-   to readd the prefixes.  */
-
-#undef	ENCODE_SECTION_INFO
-#define ENCODE_SECTION_INFO(DECL) rs6000_encode_section_info (DECL)
-
-extern void rs6000_encode_section_info ();
-
-/* This macro gets just the user-specified name
-   out of the string in a SYMBOL_REF.  Discard
-   a leading * or @. */
-#undef  STRIP_NAME_ENCODING
-#define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME)				\
-do {									\
-  char *_name = SYMBOL_NAME;						\
-  while (*_name == '*' || *_name == '@')				\
-    _name++;								\
-  (VAR) = _name;							\
-} while (0)
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
-do {									\
-  char *_name = NAME;							\
-  while (*_name == '*' || *_name == '@')				\
-    _name++;								\
-  asm_fprintf (FILE, "%U%s", _name); /* CYGNUS LOCAL vmakarov: asm_fprintf */ \
-} while (0)
-
-/*
- * Switch into a generic section.
- *
- * We make the section read-only and executable for a function decl,
- * read-only for a const data decl, and writable for a non-const data decl.
- *
- * If the section has already been defined, we must not
- * emit the attributes here. The SVR4 assembler does not
- * recognize section redefinitions.
- * If DECL is NULL, no attributes are emitted.
- *
- * Note, Solaris as doesn't like @nobits, and gas can handle .sbss without
- * needing @nobits.
- */
-
-#undef	ASM_OUTPUT_SECTION_NAME
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC)		\
-do {									\
-  static struct section_info						\
-    {									\
-      struct section_info *next;				        \
-      char *name;						        \
-      enum sect_enum {SECT_RW, SECT_RO, SECT_EXEC} type;		\
-    } *sections;							\
-  struct section_info *s;						\
-  char *mode;								\
-  enum sect_enum type;							\
-									\
-  for (s = sections; s; s = s->next)					\
-    if (!strcmp (NAME, s->name))					\
-      break;								\
-									\
-  if (DECL && TREE_CODE (DECL) == FUNCTION_DECL)			\
-    type = SECT_EXEC, mode = "ax";					\
-  else if (DECL && DECL_READONLY_SECTION (DECL, RELOC) && !TARGET_RELOCATABLE && !flag_pic) \
-    type = SECT_RO, mode = "a";						\
-  else									\
-    type = SECT_RW, mode = "aw";					\
-									\
-  if (s == 0)								\
-    {									\
-      s = (struct section_info *) xmalloc (sizeof (struct section_info));  \
-      s->name = xmalloc ((strlen (NAME) + 1) * sizeof (*NAME));		\
-      strcpy (s->name, NAME);						\
-      s->type = type;							\
-      s->next = sections;						\
-      sections = s;							\
-      fprintf (FILE, "\t.section\t\"%s\",\"%s\"\n", NAME, mode);	\
-    }									\
-  else									\
-    {									\
-      if (DECL && s->type != type)					\
-	error_with_decl (DECL, "%s causes a section type conflict");	\
-									\
-      fprintf (FILE, "\t.section\t\"%s\"\n", NAME);			\
-    }									\
-} while (0)
-
-#undef ASM_OUTPUT_CONSTRUCTOR
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    if (DEFAULT_ABI != ABI_SOLARIS)					\
-      {									\
-	ctors_section ();						\
-	fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-      }									\
-    else								\
-      {									\
-	init_section ();						\
-	fputs ("\tbl ", FILE);						\
-	assemble_name (FILE, NAME);					\
-      }									\
-    fputs ("\n", FILE);							\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#undef ASM_OUTPUT_DESTRUCTOR
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    if (DEFAULT_ABI != ABI_SOLARIS)					\
-      {									\
-	dtors_section ();						\
-	fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-      }									\
-    else								\
-      {									\
-	fini_section ();						\
-	fputs ("\tbl ", FILE);						\
-	assemble_name (FILE, NAME);					\
-      }									\
-    fputs ("\n", FILE);							\
-  } while (0)
-
-/* But, to make this work, we have to output the stabs for the function
-   name *first*...  */
-
-#define	DBX_FUNCTION_FIRST
-
-/* This is the end of what might become sysv4dbx.h.  */
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (PowerPC System V.4)");
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-  "-DPPC -Dunix -D__svr4__ -Asystem(unix) -Asystem(svr4) -Acpu(powerpc) -Amachine(powerpc)"
-
-/* Pass various options to the assembler */
-#undef ASM_SPEC
-#define ASM_SPEC "%(asm_cpu) \
-%{.s: %{mregnames} %{mno-regnames}} %{.S: %{mregnames} %{mno-regnames}} \
-%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
-%{mrelocatable} %{mrelocatable-lib} %{fpic:-K PIC} %{fPIC:-K PIC} \
-%{memb} %{!memb: %{msdata: -memb} %{msdata=eabi: -memb}} \
-%{mlittle} %{mlittle-endian} %{mbig} %{mbig-endian} \
-%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \
-    %{mcall-solaris: -mlittle -msolaris} \
-    %{cygnus-local-vmakarov: } \
-    %{mcall-i960-old: -mlittle} \
-    %{end-cygnus-local: } \
-    %{mcall-linux: -mbig} }}}}"
-
-#ifndef CC1_ENDIAN_BIG_SPEC
-#define CC1_ENDIAN_BIG_SPEC ""
-#endif
-
-#ifndef CC1_ENDIAN_LITTLE_SPEC
-#define CC1_ENDIAN_LITTLE_SPEC "\
-%{!mstrict-align: %{!mno-strict-align: \
-    %{cygnus-local-vmakarov: } \
-    %{!mcall-i960-old: \
-    %{end-cygnus-local: } \
-	-mstrict-align \
-    %{cygnus-local-vmakarov: } \
-    } \
-    %{end-cygnus-local: } \
-}}"
-#endif
-
-#ifndef CC1_ENDIAN_DEFAULT_SPEC
-#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_big_spec)"
-#endif
-
-#undef CC1_SPEC
-/* Pass -G xxx to the compiler and set correct endian mode */
-#define CC1_SPEC "%{G*} \
-%{mlittle: %(cc1_endian_little)} %{!mlittle: %{mlittle-endian: %(cc1_endian_little)}} \
-%{mbig: %(cc1_endian_big)} %{!mbig: %{mbig-endian: %(cc1_endian_big)}} \
-%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \
-    %{mcall-nt: -mlittle %(cc1_endian_little) } \
-    %{mcall-aixdesc: -mbig %(cc1_endian_big) } \
-    %{mcall-solaris: -mlittle %(cc1_endian_little) } \
-    %{cygnus-local-vmakarov: } \
-    %{mcall-i960-old: -mlittle %(cc1_endian_little) } \
-    %{end-cygnus-local: } \
-    %{mcall-linux: -mbig %(cc1_endian_big) }} \
-    %{!mcall-nt: %{!mcall-aixdesc: %{!mcall-solaris: %{!mcall-linux: \
-    %{cygnus-local-vmakarov: } \
-	%{!mcall-i960-old: \
-    %{end-cygnus-local: } \
-	    %(cc1_endian_default) \
-    %{cygnus-local-vmakarov: } \
-	} \
-    %{end-cygnus-local: } \
-    }}}} \
-}}} \
-%{mcall-solaris: -mregnames } \
-%{mno-sdata: -msdata=none } \
-%{meabi: %{!mcall-*: -mcall-sysv }} \
-%{!meabi: %{!mno-eabi: \
-    %{mrelocatable: -meabi } \
-    %{mcall-solaris: -mno-eabi } \
-    %{cygnus-local-vmakarov: } \
-    %{mcall-i960-old: -meabi } \
-    %{end-cygnus-local: } \
-    %{mcall-linux: -mno-eabi }}} \
-%{msdata: -msdata=default} \
-%{mno-sdata: -msdata=none}"
-
-/* Don't put -Y P,<path> for cross compilers */
-#undef LINK_PATH_SPEC
-#ifndef CROSS_COMPILE
-#define LINK_PATH_SPEC "\
-%{!R*:%{L*:-R %*}} \
-%{!nostdlib: %{!YP,*: \
-    %{compat-bsd: \
-	%{p:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-	%{!p:-Y P,/usr/ucblib:/usr/ccs/lib:/usr/lib}} \
-	%{!R*: %{!L*: -R /usr/ucblib}} \
-    %{!compat-bsd: \
-	%{p:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-	%{!p:-Y P,/usr/ccs/lib:/usr/lib}}}}"
-
-#else
-#define LINK_PATH_SPEC ""
-#endif
-
-/* Default starting address if specified */
-#ifndef LINK_START_SPEC
-#define LINK_START_SPEC "\
-%{mads: %(link_start_ads) } \
-%{myellowknife: %(link_start_yellowknife) } \
-%{mmvme: %(link_start_mvme) } \
-%{msim: %(link_start_sim) } \
-%{mcall-linux: %(link_start_linux) } \
-%{mcall-solaris: %(link_start_solaris) } \
-%{cygnus-local-vmakarov: } \
-%{mvxworks: %(link_start_vxworks) } \
-%{end-cygnus-local: } \
-%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-linux: %{!mcall-solaris:\
-%{cygnus-local-vmakarov: } \
- %{!mvxworks: \
-%{end-cygnus-local: } \
- %(link_start_default) \
-%{cygnus-local-vmakarov: } \
- } \
-%{end-cygnus-local: } \
-}}}}}}"
-#endif
-
-#ifndef	LINK_START_DEFAULT_SPEC
-#define LINK_START_DEFAULT_SPEC ""
-#endif
-
-#undef LINK_SPEC
-/* CYGNUS LOCAL jlemke (mpc860) */
-#define LINK_SPEC "\
-%{h*} %{v:-V} %{G*} \
-%{Wl,*:%*} %{YP,*} %{R*} \
-%{Qy:} %{!Qn:-Qy} \
-%(link_shlib) \
-%{!Ttext*: %(link_start) } \
-%(link_target) \
-%{mmpc860c0*:--mpc860c0%*} \
-%(link_os)"
-/* END CYGNUS LOCAL */
-
-/* For now, turn off shared libraries by default.  */
-#ifndef SHARED_LIB_SUPPORT
-#define NO_SHARED_LIB_SUPPORT
-#endif
-
-#undef  LINK_SHLIB_SPEC
-#ifndef NO_SHARED_LIB_SUPPORT
-/* Shared libraries are default.  */
-#define LINK_SHLIB_SPEC "\
-%{!static: %(link_path) %{!R*:%{L*:-R %*}}} \
-%{mshlib: } \
-%{static:-dn -Bstatic} \
-%{shared:-G -dy -z text} \
-%{symbolic:-Bsymbolic -G -dy -z text}"
-
-#else
-/* Shared libraries are not default.  */
-#define LINK_SHLIB_SPEC "\
-%{mshlib: %(link_path) } \
-%{!mshlib: %{!shared: %{!symbolic: -dn -Bstatic}}} \
-%{static: } \
-%{shared:-G -dy -z text %(link_path) } \
-%{symbolic:-Bsymbolic -G -dy -z text %(link_path) }"
-#endif
-
-/* Override the default target of the linker.  */
-#undef	LINK_TARGET_SPEC
-#define	LINK_TARGET_SPEC "\
-%{mlittle: -oformat elf32-powerpcle } %{mlittle-endian: -oformat elf32-powerpcle } \
-%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \
-    %{cygnus-local-vmakarov: } \
-    %{mcall-i960-old: -oformat elf32-powerpcle} \
-    %{end-cygnus-local: } \
-    %{mcall-solaris: -oformat elf32-powerpcle} \
-    %{mcall-linux: -oformat elf32-powerpc}}}}}"
-
-/* Any specific OS flags */
-#ifndef LINK_OS_SPEC
-#define LINK_OS_SPEC "\
-%{mads: %(link_os_ads) } \
-%{myellowknife: %(link_os_yellowknife) } \
-%{mmvme: %(link_os_mvme) } \
-%{msim: %(link_os_sim) } \
-%{mcall-linux: %(link_os_linux) } \
-%{mcall-solaris: %(link_os_solaris) } \
-%{cygnus-local-vmakarov: } \
-%{mvxworks: %(link_os_vxworks) } \
-%{end-cygnus-local: } \
-%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-linux: %{!mcall-solaris:\
-%{cygnus-local-vmakarov: } \
- %{!mvxworks: \
-%{end-cygnus-local: } \
- %(link_os_default) \
-%{cygnus-local-vmakarov: } \
- } \
-%{end-cygnus-local: } \
-}}}}}}"
-#endif
-
-#ifndef	LINK_OS_DEFAULT_SPEC
-#define LINK_OS_DEFAULT_SPEC ""
-#endif
-
-#undef	CPP_SYSV_SPEC
-#define CPP_SYSV_SPEC \
-"%{mrelocatable*: -D_RELOCATABLE} \
-%{fpic: -D__PIC__=1 -D__pic__=1} \
-%{fPIC: -D__PIC__=2 -D__pic__=2} \
-%{mcall-sysv: -D_CALL_SYSV} %{mcall-nt: -D_CALL_NT} \
-%{mcall-aix: -D_CALL_AIX} %{mcall-aixdesc: -D_CALL_AIX -D_CALL_AIXDESC} \
-%{!mcall-sysv: %{!mcall-aix: %{!mcall-aixdesc: %{!mcall-nt: %(cpp_sysv_default) }}}} \
-%{msoft-float: -D_SOFT_FLOAT} \
-%{cygnus-local-vmakarov: } \
-%{!msoft-float: %{!mhard-float: \
-    %{mcpu=401: -D_SOFT_FLOAT} \
-    %{mcpu=403: -D_SOFT_FLOAT} \
-    %{mcpu=ec603e: -D_SOFT_FLOAT} \
-    %{mcpu=801: -D_SOFT_FLOAT} \
-    %{mcpu=821: -D_SOFT_FLOAT} \
-    %{mcpu=823: -D_SOFT_FLOAT} \
-    %{mcpu=860: -D_SOFT_FLOAT} \
-    %{!mcpu*: %(cpp_float_default) }}} \
-%{end-cygnus-local: }"
-
-/* CYGNUS LOCAL vmakarov */
-/* Whether floating point is disabled by default */
-#undef	CPP_FLOAT_DEFAULT_SPEC
-#define	CPP_FLOAT_DEFAULT_SPEC ""
-
-/* For solaris, don't define _LITTLE_ENDIAN, it conflicts with a
-   header file.  For VxWorks, don't define either _{BIG,LITTLE}_ENDIAN
-   for the same reason.  */
-/* END CYGNUS LOCAL */
-#undef	CPP_SYSV_DEFAULT_SPEC
-#define	CPP_SYSV_DEFAULT_SPEC "-D_CALL_SYSV"
-
-#ifndef CPP_ENDIAN_BIG_SPEC
-#define CPP_ENDIAN_BIG_SPEC "\
-%{cygnus-local-vmakarov: } \
-%{!mcall-solaris: %{!mvxworks: -D_BIG_ENDIAN }} \
-%{end-cygnus-local: } \
--D__BIG_ENDIAN__ -Amachine(bigendian)"
-#endif
-
-#ifndef CPP_ENDIAN_LITTLE_SPEC
-#define CPP_ENDIAN_LITTLE_SPEC "\
-%{cygnus-local-vmakarov: } \
-%{!mcall-solaris: %{!mvxworks: -D_LITTLE_ENDIAN }} \
-%{end-cygnus-local: } \
--D__LITTLE_ENDIAN__ -Amachine(littleendian)"
-#endif
-
-/* CYGNUS LOCAL vmakarov */
-#if 0
-/* END CYGNUS LOCAL */
-#ifndef CPP_ENDIAN_SOLARIS_SPEC
-#define CPP_ENDIAN_SOLARIS_SPEC "-D__LITTLE_ENDIAN__ -Amachine(littleendian)"
-#endif
-/* For solaris, don't define _LITTLE_ENDIAN, it conflicts with a header file.  */
-/* CYGNUS LOCAL vmakarov */
-#endif
-/* END CYGNUS LOCAL */
-
-#undef	CPP_ENDIAN_SPEC
-#define	CPP_ENDIAN_SPEC \
-"%{mlittle: %(cpp_endian_little) } \
-%{mlittle-endian: %(cpp_endian_little) } \
-%{mbig: %(cpp_endian_big) } \
-%{mbig-endian: %(cpp_endian_big) } \
-%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \
-    %{mcall-solaris: %(cpp_endian_little) } %{cygnus-local-cpp-endian-little: }\
-    %{mcall-nt: %(cpp_endian_little) } \
-    %{cygnus-local-vmakarov: } \
-    %{mcall-i960-old: %(cpp_endian_little) } \
-    %{end-cygnus-local: } \
-    %{mcall-linux: %(cpp_endian_big) } \
-    %{mcall-aixdesc:  %(cpp_endian_big) } \
-    %{!mcall-solaris: %{!mcall-linux: %{!mcall-nt: %{!mcall-aixdesc: %(cpp_endian_default) }}}}}}}}"
-
-#undef	CPP_ENDIAN_DEFAULT_SPEC
-#define	CPP_ENDIAN_DEFAULT_SPEC "%(cpp_endian_big)"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} %{msoft-float: -D_SOFT_FLOAT} \
-%(cpp_sysv) %(cpp_endian) %(cpp_cpu) \
-%{mads: %(cpp_os_ads) } \
-%{myellowknife: %(cpp_os_yellowknife) } \
-%{mmvme: %(cpp_os_mvme) } \
-%{msim: %(cpp_os_sim) } \
-%{mcall-linux: %(cpp_os_linux) } \
-%{mcall-solaris: %(cpp_os_solaris) } \
-%{cygnus-local-vmakarov: } \
-%{mvxworks: %(cpp_os_vxworks) } \
-%{end-cygnus-local: } \
-%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-linux: %{!mcall-solaris:\
-%{cygnus-local-vmakarov: } \
-%{!mvxworks: \
-%{end-cygnus-local: } \
-   %(cpp_os_default) \
- } \
-%{end-cygnus-local: } \
-}}}}}}"
-
-#ifndef CPP_OS_DEFAULT_SPEC
-#define CPP_OS_DEFAULT_SPEC ""
-#endif
-
-#undef  STARTFILE_SPEC
-#define	STARTFILE_SPEC "\
-%{mads: %(startfile_ads) } \
-%{myellowknife: %(startfile_yellowknife) } \
-%{mmvme: %(startfile_mvme) } \
-%{msim: %(startfile_sim) } \
-%{mcall-linux: %(startfile_linux) } \
-%{mcall-solaris: %(startfile_solaris) } \
-%{cygnus-local-vmakarov: } \
-%{mvxworks: %(startfile_vxworks) } \
-%{end-cygnus-local: } \
-%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-linux: %{!mcall-solaris:\
-%{cygnus-local-vmakarov: } \
-%{!mvxworks: \
-%{end-cygnus-local: } \
-  %(startfile_default) \
-%{cygnus-local-vmakarov: } \
-  } \
-%{end-cygnus-local: } \
-}}}}}}"
-
-#undef	STARTFILE_DEFAULT_SPEC
-#define	STARTFILE_DEFAULT_SPEC ""
-
-#undef	LIB_SPEC
-#define	LIB_SPEC "\
-%{mads: %(lib_ads) } \
-%{myellowknife: %(lib_yellowknife) } \
-%{mmvme: %(lib_mvme) } \
-%{msim: %(lib_sim) } \
-%{mcall-linux: %(lib_linux) } \
-%{mcall-solaris: %(lib_solaris) } \
-%{cygnus-local-vmakarov: } \
-%{mvxworks: %(lib_vxworks) } \
-%{end-cygnus-local: } \
-%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-linux: %{!mcall-solaris:\
-%{cygnus-local-vmakarov: } \
-%{!mvxworks: \
-%{end-cygnus-local: } \
-   %(lib_default) \
-%{cygnus-local-vmakarov: } \
-  }\
-%{end-cygnus-local: } \
-}}}}}}"
-
-#undef	LIBGCC_SPEC
-#define	LIBGCC_SPEC "libgcc.a%s"
-
-#ifndef LIB_DEFAULT_SPEC
-#define LIB_DEFAULT_SPEC ""
-#endif
-
-#undef	ENDFILE_SPEC
-
-/* CYGNUS LOCAL vmakarov */
-#if 0
-/* END CYGNUS LOCAL */
-#define	ENDFILE_SPEC "\
-%{mads: ecrtn.o%s} \
-%{myellowknife: ecrtn.o%s} \
-%{mmvme: ecrtn.o%s} \
-%{msim: ecrtn.o%s} \
-%{mcall-linux: %(endfile_linux) } \
-%{mcall-solaris: scrtn.o%s} \
-%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-linux: %{!mcall-solaris: %(endfile_default) }}}}}}"
-
-/* CYGNUS LOCAL vmakarov */
-#endif
-
-#define	ENDFILE_SPEC "\
-%{mads: %(endfile_ads) } \
-%{myellowknife: %(endfile_yellowknife) } \
-%{mmvme: %(endfile_mvme) } \
-%{msim: %(endfile_sim) } \
-%{mcall-linux: %(endfile_linux) } \
-%{mcall-solaris: %(endfile_solarils) } \
-%{mvxworks: %(endfile_vxworks) } \
-%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-linux: %{!mcall-solaris: %{!mvxworks: %(endfile_default) }}}}}}}"
-/* END CYGNUS LOCAL */
-
-#undef	ENDFILE_DEFAULT_SPEC
-#define	ENDFILE_DEFAULT_SPEC ""
-
-/* Motorola ADS support.  */
-#ifndef	LIB_ADS_SPEC
-#define LIB_ADS_SPEC "--start-group -lads -lc --end-group"
-#endif
-
-#ifndef	STARTFILE_ADS_SPEC
-#define	STARTFILE_ADS_SPEC "ecrti.o%s crt0.o%s"
-#endif
-
-#ifndef	ENDFILE_ADS_SPEC
-#define	ENDFILE_ADS_SPEC "ecrtn.o%s"
-#endif
-
-#ifndef LINK_START_ADS_SPEC
-#define LINK_START_ADS_SPEC "-T ads.ld%s"
-#endif
-
-#ifndef LINK_OS_ADS_SPEC
-#define LINK_OS_ADS_SPEC ""
-#endif
-
-#ifndef CPP_OS_ADS_SPEC
-#define CPP_OS_ADS_SPEC ""
-#endif
-
-/* Motorola Yellowknife support.  */
-#ifndef	LIB_YELLOWKNIFE_SPEC
-#define LIB_YELLOWKNIFE_SPEC "--start-group -lyk -lc --end-group"
-#endif
-
-#ifndef	STARTFILE_YELLOWKNIFE_SPEC
-#define	STARTFILE_YELLOWKNIFE_SPEC "ecrti.o%s crt0.o%s"
-#endif
-
-#ifndef	ENDFILE_YELLOWKNIFE_SPEC
-#define	ENDFILE_YELLOWKNIFE_SPEC "ecrtn.o%s"
-#endif
-
-#ifndef LINK_START_YELLOWKNIFE_SPEC
-#define LINK_START_YELLOWKNIFE_SPEC "-T yellowknife.ld%s"
-#endif
-
-#ifndef LINK_OS_YELLOWKNIFE_SPEC
-#define LINK_OS_YELLOWKNIFE_SPEC ""
-#endif
-
-#ifndef CPP_OS_YELLOWKNIFE_SPEC
-#define CPP_OS_YELLOWKNIFE_SPEC ""
-#endif
-
-/* Motorola MVME support.  */
-#ifndef	LIB_MVME_SPEC
-#define LIB_MVME_SPEC "--start-group -lmvme -lc --end-group"
-#endif
-
-#ifndef	STARTFILE_MVME_SPEC
-#define	STARTFILE_MVME_SPEC "ecrti.o%s crt0.o%s"
-#endif
-
-#ifndef	ENDFILE_MVME_SPEC
-#define	ENDFILE_MVME_SPEC "ecrtn.o%s"
-#endif
-
-#ifndef LINK_START_MVME_SPEC
-#define LINK_START_MVME_SPEC "%{!Wl,-T*: %{!T*: -Ttext 0x40000}}"
-#endif
-
-#ifndef LINK_OS_MVME_SPEC
-#define LINK_OS_MVME_SPEC ""
-#endif
-
-#ifndef CPP_OS_MVME_SPEC
-#define CPP_OS_MVME_SPEC ""
-#endif
-
-/* PowerPC simulator based on netbsd system calls support.  */
-#ifndef	LIB_SIM_SPEC
-#define LIB_SIM_SPEC "--start-group -lsim -lc --end-group"
-#endif
-
-#ifndef	STARTFILE_SIM_SPEC
-#define	STARTFILE_SIM_SPEC "ecrti.o%s sim-crt0.o%s"
-#endif
-
-#ifndef	ENDFILE_SIM_SPEC
-#define	ENDFILE_SIM_SPEC "ecrtn.o%s"
-#endif
-
-#ifndef LINK_START_SIM_SPEC
-#define LINK_START_SIM_SPEC "-Ttext 0x10000074"
-#endif
-
-#ifndef LINK_OS_SIM_SPEC
-#define LINK_OS_SIM_SPEC ""
-#endif
-
-#ifndef CPP_OS_SIM_SPEC
-#define CPP_OS_SIM_SPEC ""
-#endif
-
-/* GNU/Linux support.  */
-#ifndef	LIB_LINUX_SPEC
-#define LIB_LINUX_SPEC "%{mnewlib: --start-group -llinux -lc --end-group } %{!mnewlib: -lc }"
-#endif
-
-#ifndef	STARTFILE_LINUX_SPEC
-#define	STARTFILE_LINUX_SPEC "\
-%{!shared: %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}} \
-%{mnewlib: ecrti.o%s} \
-%{!mnewlib: crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}"
-#endif
-
-#ifndef	ENDFILE_LINUX_SPEC
-#define	ENDFILE_LINUX_SPEC "\
-%{mnewlib: ecrtn.o%s} \
-%{!mnewlib: %{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s}"
-#endif
-
-#ifndef LINK_START_LINUX_SPEC
-#define LINK_START_LINUX_SPEC "-Ttext 0x400074"
-#endif
-
-#ifndef LINK_OS_LINUX_SPEC
-#define LINK_OS_LINUX_SPEC ""
-#endif
-
-#ifndef CPP_OS_LINUX_SPEC
-#define CPP_OS_LINUX_SPEC "-D__unix__ -D__linux__ \
-%{!ansi: -Dunix -Dlinux } \
--Asystem(unix) -Asystem(linux)"
-#endif
-
-#ifndef CPP_OS_LINUX_SPEC
-#define CPP_OS_LINUX_SPEC ""
-#endif
-
-/* Solaris support.  */
-/* For Solaris, Gcc automatically adds in one of the files
-   /usr/ccs/lib/values-Xc.o, /usr/ccs/lib/values-Xa.o, or
-   /usr/ccs/lib/values-Xt.o for each final link step (depending upon the other
-   gcc options selected, such as -traditional and -ansi).  These files each
-   contain one (initialized) copy of a special variable called `_lib_version'.
-   Each one of these files has `_lib_version' initialized to a different (enum)
-   value.  The SVR4 library routines query the value of `_lib_version' at run
-   to decide how they should behave.  Specifically, they decide (based upon the
-   value of `_lib_version') if they will act in a strictly ANSI conforming
-   manner or not.  */
-
-#ifndef	LIB_SOLARIS_SPEC
-#define LIB_SOLARIS_SPEC "\
-%{mnewlib: --start-group -lsolaris -lc --end-group } \
-%{!mnewlib: \
-    %{ansi:values-Xc.o%s} \
-    %{!ansi: \
-	%{traditional:values-Xt.o%s} \
-	%{!traditional:values-Xa.o%s}} \
-	%{compat-bsd:-lucb -lsocket -lnsl -lelf -laio} \
-    %{solaris-cclib: /opt/SUNWspro/SC4.0/lib/libabi.a} \
-    %{!shared: %{!symbolic: -lc }}}"
-#endif
-
-#ifndef	STARTFILE_SOLARIS_SPEC
-#define	STARTFILE_SOLARIS_SPEC "\
-%{!msolaris-cclib: scrti.o%s scrt0.o%s} \
-%{msolaris-cclib: /opt/SUNWspro/SC4.0/lib/crti.o%s /opt/SUNWspro/SC4.0/lib/crt1.o%s}"
-#endif
-
-#ifndef	ENDFILE_SOLARIS_SPEC
-#define	ENDFILE_SOLARIS_SPEC "\
-%{!msolaris-cclib: scrtn.o%s} \
-%{msolaris-cclib: /opt/SUNWspro/SC4.0/lib/crtn.o%s}"
-#endif
-
-#ifndef LINK_START_SOLARIS_SPEC
-#ifdef CROSS_COMPILER
-#define LINK_START_SOLARIS_SPEC "-Ttext 0x2000074"
-#else
-#define LINK_START_SOLARIS_SPEC ""
-#endif
-#endif
-
-#ifndef LINK_OS_SOLARIS_SPEC
-#define LINK_OS_SOLARIS_SPEC ""
-#endif
-
-#ifndef CPP_OS_SOLARIS_SPEC
-#define CPP_OS_SOLARIS_SPEC "-D__ppc -D__sun__=1 -D__unix__ -D__svr4__  -D__SVR4__ \
-%{!ansi: -Dsun=1 -Dunix -DSVR4 -D__EXTENSIONS__ } \
--Amachine(prep)"
-#endif
-
-/* CYGNUS LOCAL vmakarov */
-/* VxWorks support.  */
-/* VxWorks does all the library stuff itself.  */
-#ifndef	LIB_VXWORKS_SPEC
-#define LIB_VXWORKS_SPEC ""
-#endif
-
-/* Because it uses ld -r, vxworks has no start/end files, nor starting address.  */
-#ifndef	STARTFILE_VXWORKS_SPEC
-#define	STARTFILE_VXWORKS_SPEC ""
-#endif
-
-#ifndef	ENDFILE_VXWORKS_SPEC
-#define	ENDFILE_VXWORKS_SPEC ""
-#endif
-
-#ifndef LINK_START_VXWORKS_SPEC
-#define LINK_START_VXWORKS_SPEC ""
-#endif
-
-#ifndef LINK_OS_VXWORKS_SPEC
-#define LINK_OS_VXWORKS_SPEC "-r"
-#endif
-
-#ifndef CPP_OS_VXWORKS_SPEC
-#define CPP_OS_VXWORKS_SPEC "\
--DCPU_FAMILY=PPC \
-%{!mcpu*: \
-  %{mpowerpc*: -DCPU=PPC603} \
-  %{!mno-powerpc: -DCPU=PPC603}} \
-%{mcpu=powerpc: -DCPU=PPC603} \
-%{mcpu=401: -DCPU=PPC403} \
-%{mcpu=403: -DCPU=PPC403} \
-%{mcpu=601: -DCPU=PPC601} \
-%{mcpu=602: -DCPU=PPC603} \
-%{mcpu=603: -DCPU=PPC603} \
-%{mcpu=603e: -DCPU=PPC603} \
-%{mcpu=ec603e: -DCPU=PPC603} \
-%{mcpu=604: -DCPU=PPC604} \
-%{mcpu=604e: -DCPU=PPC604} \
-%{mcpu=620: -DCPU=PPC604} \
-%{mcpu=801: -DCPU=PPC603} \
-%{mcpu=821: -DCPU=PPC603} \
-%{mcpu=823: -DCPU=PPC603} \
-%{mcpu=860: -DCPU=PPC603}"
-
-#endif
-/* END CYGNUS LOCAL */
-
-/* Define any extra SPECS that the compiler needs to generate.  */
-#undef	SUBTARGET_EXTRA_SPECS
-#define SUBTARGET_EXTRA_SPECS						\
-  { "lib_ads",			LIB_ADS_SPEC },				\
-  { "lib_yellowknife",		LIB_YELLOWKNIFE_SPEC },			\
-  { "lib_mvme",			LIB_MVME_SPEC },			\
-  { "lib_sim",			LIB_SIM_SPEC },				\
-  { "lib_linux",		LIB_LINUX_SPEC },			\
-  { "lib_solaris",		LIB_SOLARIS_SPEC },			\
-/* CYGNUS LOCAL vmakarov */                                             \
-  { "lib_vxworks",		LIB_VXWORKS_SPEC },			\
-/* END CYGNUS LOCAL */                                                  \
-  { "lib_default",		LIB_DEFAULT_SPEC },			\
-  { "startfile_ads",		STARTFILE_ADS_SPEC },			\
-  { "startfile_yellowknife",	STARTFILE_YELLOWKNIFE_SPEC },		\
-  { "startfile_mvme",		STARTFILE_MVME_SPEC },			\
-  { "startfile_sim",		STARTFILE_SIM_SPEC },			\
-  { "startfile_linux",		STARTFILE_LINUX_SPEC },			\
-  { "startfile_solaris",	STARTFILE_SOLARIS_SPEC },		\
-/* CYGNUS LOCAL vmakarov */                                             \
-  { "startfile_vxworks",	STARTFILE_VXWORKS_SPEC },		\
-/* END CYGNUS LOCAL */                                                  \
-  { "startfile_default",	STARTFILE_DEFAULT_SPEC },		\
-  { "endfile_ads",		ENDFILE_ADS_SPEC },			\
-  { "endfile_yellowknife",	ENDFILE_YELLOWKNIFE_SPEC },		\
-  { "endfile_mvme",		ENDFILE_MVME_SPEC },			\
-  { "endfile_sim",		ENDFILE_SIM_SPEC },			\
-  { "endfile_linux",		ENDFILE_LINUX_SPEC },			\
-  { "endfile_solaris",		ENDFILE_SOLARIS_SPEC },			\
-/* CYGNUS LOCAL vmakarov */                                             \
-  { "endfile_vxworks",		ENDFILE_VXWORKS_SPEC },			\
-/* END CYGNUS LOCAL */                                                  \
-  { "endfile_default",		ENDFILE_DEFAULT_SPEC },			\
-  { "link_path",		LINK_PATH_SPEC },			\
-  { "link_shlib",		LINK_SHLIB_SPEC },			\
-  { "link_target",		LINK_TARGET_SPEC },			\
-  { "link_start",		LINK_START_SPEC },			\
-  { "link_start_ads",		LINK_START_ADS_SPEC },			\
-  { "link_start_yellowknife",	LINK_START_YELLOWKNIFE_SPEC },		\
-  { "link_start_mvme",		LINK_START_MVME_SPEC },			\
-  { "link_start_sim",		LINK_START_SIM_SPEC },			\
-  { "link_start_linux",		LINK_START_LINUX_SPEC },		\
-  { "link_start_solaris",	LINK_START_SOLARIS_SPEC },		\
-/* CYGNUS LOCAL vmakarov */                                             \
-  { "link_start_vxworks",	LINK_START_VXWORKS_SPEC },		\
-/* END CYGNUS LOCAL */                                                  \
-  { "link_start_default",	LINK_START_DEFAULT_SPEC },		\
-  { "link_os",			LINK_OS_SPEC },				\
-  { "link_os_ads",		LINK_OS_ADS_SPEC },			\
-  { "link_os_yellowknife",	LINK_OS_YELLOWKNIFE_SPEC },		\
-  { "link_os_mvme",		LINK_OS_MVME_SPEC },			\
-  { "link_os_sim",		LINK_OS_SIM_SPEC },			\
-  { "link_os_linux",		LINK_OS_LINUX_SPEC },			\
-  { "link_os_solaris",		LINK_OS_SOLARIS_SPEC },			\
-/* CYGNUS LOCAL vmakarov */                                             \
-  { "link_os_vxworks",		LINK_OS_VXWORKS_SPEC },			\
-/* END CYGNUS LOCAL */                                                  \
-  { "link_os_default",		LINK_OS_DEFAULT_SPEC },			\
-  { "cc1_endian_big",		CC1_ENDIAN_BIG_SPEC },			\
-  { "cc1_endian_little",	CC1_ENDIAN_LITTLE_SPEC },		\
-  { "cc1_endian_default",	CC1_ENDIAN_DEFAULT_SPEC },		\
-  { "cpp_endian_big",		CPP_ENDIAN_BIG_SPEC },			\
-  { "cpp_endian_little",	CPP_ENDIAN_LITTLE_SPEC },		\
-/* CYGNUS LOCAL vmakarov */                                             \
-  { "cpp_endian_default",	CPP_ENDIAN_DEFAULT_SPEC },		\
-  { "cpp_float_default",	CPP_FLOAT_DEFAULT_SPEC },		\
-/* END CYGNUS LOCAL */                                                  \
-  { "cpp_os_ads",		CPP_OS_ADS_SPEC },			\
-  { "cpp_os_yellowknife",	CPP_OS_YELLOWKNIFE_SPEC },		\
-  { "cpp_os_mvme",		CPP_OS_MVME_SPEC },			\
-  { "cpp_os_sim",		CPP_OS_SIM_SPEC },			\
-  { "cpp_os_linux",		CPP_OS_LINUX_SPEC },			\
-  { "cpp_os_solaris",		CPP_OS_SOLARIS_SPEC },			\
-/* CYGNUS LOCAL vmakarov */                                             \
-  { "cpp_os_vxworks",		CPP_OS_VXWORKS_SPEC },			\
-/* END CYGNUS LOCAL */                                                  \
-  { "cpp_os_default",		CPP_OS_DEFAULT_SPEC },
-
-/* Define this macro as a C expression for the initializer of an
-   array of string to tell the driver program which options are
-   defaults for this target and thus do not need to be handled
-   specially when using `MULTILIB_OPTIONS'.
-
-   Do not define this macro if `MULTILIB_OPTIONS' is not defined in
-   the target makefile fragment or if none of the options listed in
-   `MULTILIB_OPTIONS' are set by default.  *Note Target Fragment::.  */
-
-#undef	MULTILIB_DEFAULTS
-#define	MULTILIB_DEFAULTS { "mbig", "mcall-sysv" }
-
-/* Define this macro if the code for function profiling should come
-   before the function prologue.  Normally, the profiling code comes
-   after.  */
-#define PROFILE_BEFORE_PROLOGUE 1
-
-/* Function name to call to do profiling.  */
-#undef	RS6000_MCOUNT
-#define RS6000_MCOUNT "_mcount"
diff --git a/gcc/config/rs6000/sysv4le.h b/gcc/config/rs6000/sysv4le.h
deleted file mode 100755
index d444a1a..0000000
--- a/gcc/config/rs6000/sysv4le.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Target definitions for GNU compiler for a little endian PowerPC
-   running System V.4
-   Copyright (C) 1995, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "rs6000/sysv4.h"
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_LITTLE_ENDIAN)
-
-#undef	CPP_ENDIAN_DEFAULT_SPEC
-#define	CPP_ENDIAN_DEFAULT_SPEC "%(cpp_endian_little)"
-
-#undef	CC1_ENDIAN_DEFAULT_SPEC
-#define	CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)"
-
-#undef	LINK_TARGET_SPEC
-#define	LINK_TARGET_SPEC "\
-%{mbig: -oformat elf32-powerpc } %{mbig-endian: -oformat elf32-powerpc } \
-%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \
-    %{cygnus-local-vmakarov: } \
-    %{mcall-i960-old: -oformat elf32-powerpcle} \
-    %{end-cygnus-local: } \
-    %{mcall-solaris: -oformat elf32-powerpcle} \
-    %{mcall-linux: -oformat elf32-powerpc}}}}}"
-
-/* Define this macro as a C expression for the initializer of an
-   array of string to tell the driver program which options are
-   defaults for this target and thus do not need to be handled
-   specially when using `MULTILIB_OPTIONS'.
-
-   Do not define this macro if `MULTILIB_OPTIONS' is not defined in
-   the target makefile fragment or if none of the options listed in
-   `MULTILIB_OPTIONS' are set by default.  *Note Target Fragment::.  */
-
-#undef	MULTILIB_DEFAULTS
-#define	MULTILIB_DEFAULTS { "mlittle", "mcall-sysv" }
diff --git a/gcc/config/rs6000/t-aix43 b/gcc/config/rs6000/t-aix43
deleted file mode 100755
index 56ddb45..0000000
--- a/gcc/config/rs6000/t-aix43
+++ /dev/null
@@ -1,48 +0,0 @@
-# Do not build libgcc1.
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# Build the libraries for both hard and soft floating point and all of the 
-# different processor models
-
-MULTILIB_OPTIONS	= msoft-float \
-			  mcpu=common/mcpu=power/mcpu=powerpc/maix64
-
-MULTILIB_DIRNAMES	= soft-float \
-			  common power powerpc aix64
-
-MULTILIB_MATCHES	= msoft-float=mcpu?403 \
-			  maix64=maix64 \
-			  mcpu?power=mpower \
-			  mcpu?power=mrios1 \
-			  mcpu?power=mcpu?rios1 \
-			  mcpu?power=mcpu?rsc \
-			  mcpu?power=mcpu?rsc1 \
-			  mcpu?power=mpower2 \
-			  mcpu?power=mrios2 \
-			  mcpu?power=mcpu=rios2 \
-			  mcpu?powerpc=mcpu?601 \
-			  mcpu?powerpc=mcpu?602 \
-			  mcpu?powerpc=mcpu?603 \
-			  mcpu?powerpc=mcpu?603e \
-			  mcpu?powerpc=mcpu?604 \
-			  mcpu?powerpc=mcpu?620 \
-			  mcpu?powerpc=mcpu?403 \
-			  mcpu?powerpc=mpowerpc \
-			  mcpu?powerpc=mpowerpc-gpopt \
-			  mcpu?powerpc=mpowerpc-gfxopt
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
diff --git a/gcc/config/rs6000/t-beos b/gcc/config/rs6000/t-beos
deleted file mode 100755
index 1436108..0000000
--- a/gcc/config/rs6000/t-beos
+++ /dev/null
@@ -1,51 +0,0 @@
-# Do not build libgcc1.
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# Build the libraries for both hard and soft floating point
-
-MULTILIB_OPTIONS = msoft-float mcpu=common
-MULTILIB_DIRNAMES = soft-float common
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# This is probably the correct define, to override the Makefile
-# default, but using it causes more problems than it solves.
-#
-# Using it will cause fixincludes to try and fix some of the
-# mwcc header files, which it seems to do a poor job of.  On
-# the other hand, not using it will only cause the gcc version
-# of limits.h to lack the header and trailer parts that are
-# tacked on to it when there is a limits.h in the system header
-# dir.
-#
-# For now it is probably better to change the rule for
-# LIMITS_H_TEST to explicitly look for the BeOS limits.h.
-# If the gcc limits.h is not set up to #include_next the
-# BeOS limits.h, then some things will go undefined, like
-# PATH_MAX.
-
-#SYSTEM_HEADER_DIR=/boot/develop/headers/posix
-# Test to see whether <limits.h> exists in the system header files.
-LIMITS_H_TEST = [ -f /boot/develop/headers/posix/limits.h ]
-
-# Aix 3.2.x needs milli.exp for -mcpu=common
-EXTRA_PARTS = milli.exp
-milli.exp: $(srcdir)/config/rs6000/milli.exp
-	rm -f milli.exp
-	cp $(srcdir)/config/rs6000/milli.exp ./milli.exp
-
-# Don't use collect.
-USE_COLLECT2 =
diff --git a/gcc/config/rs6000/t-newas b/gcc/config/rs6000/t-newas
deleted file mode 100755
index 823b03b..0000000
--- a/gcc/config/rs6000/t-newas
+++ /dev/null
@@ -1,52 +0,0 @@
-# Do not build libgcc1.
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# Build the libraries for both hard and soft floating point and all of the 
-# different processor models
-
-MULTILIB_OPTIONS	= msoft-float \
-			  mcpu=common/mcpu=power/mcpu=powerpc
-
-MULTILIB_DIRNAMES	= soft-float \
-			  common power powerpc
-
-MULTILIB_MATCHES	= msoft-float=mcpu?403 \
-			  mcpu?power=mpower \
-			  mcpu?power=mrios1 \
-			  mcpu?power=mcpu?rios1 \
-			  mcpu?power=mcpu?rsc \
-			  mcpu?power=mcpu?rsc1 \
-			  mcpu?power=mpower2 \
-			  mcpu?power=mrios2 \
-			  mcpu?power=mcpu=rios2 \
-			  mcpu?powerpc=mcpu?601 \
-			  mcpu?powerpc=mcpu?602 \
-			  mcpu?powerpc=mcpu?603 \
-			  mcpu?powerpc=mcpu?603e \
-			  mcpu?powerpc=mcpu?604 \
-			  mcpu?powerpc=mcpu?620 \
-			  mcpu?powerpc=mcpu?403 \
-			  mcpu?powerpc=mpowerpc \
-			  mcpu?powerpc=mpowerpc-gpopt \
-			  mcpu?powerpc=mpowerpc-gfxopt
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# Aix 3.2.x needs milli.exp for -mcpu=common
-EXTRA_PARTS = milli.exp
-milli.exp: $(srcdir)/config/rs6000/milli.exp
-	rm -f milli.exp
-	cp $(srcdir)/config/rs6000/milli.exp ./milli.exp
diff --git a/gcc/config/rs6000/t-ppc b/gcc/config/rs6000/t-ppc
deleted file mode 100755
index 8143488..0000000
--- a/gcc/config/rs6000/t-ppc
+++ /dev/null
@@ -1,12 +0,0 @@
-# PowerPC support without gas
-
-# Build libgcc.a with different options.  If no gas support, don't build
-# explicit little endian or big endian libraries, since it depends on the
-# -mbig/-mlittle switches passed to gas.  The -mrelocatable support also needs
-# -mrelocatable passed to gas, so don't use it either.
-
-MULTILIB_OPTIONS	= msoft-float
-MULTILIB_DIRNAMES	= nof
-MULTILIB_EXCEPTIONS	=
-MULTILIB_EXTRA_OPTS	= mstrict-align
-MULTILIB_MATCHES	= ${MULTILIB_MATCHES_FLOAT}
diff --git a/gcc/config/rs6000/t-ppccomm b/gcc/config/rs6000/t-ppccomm
deleted file mode 100755
index 9ed1690..0000000
--- a/gcc/config/rs6000/t-ppccomm
+++ /dev/null
@@ -1,79 +0,0 @@
-# Common support for PowerPC eabi, System V targets.
-
-# Do not build libgcc1.
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c eabi.S eabi-ctors.c tramp.S
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-eabi.S: $(srcdir)/config/rs6000/eabi.asm
-	cat $(srcdir)/config/rs6000/eabi.asm > eabi.S
-
-eabi-ctors.c: $(srcdir)/config/rs6000/eabi-ctors.c
-	cat $(srcdir)/config/rs6000/eabi-ctors.c > eabi-ctors.c
-
-tramp.S: $(srcdir)/config/rs6000/tramp.asm
-	cat $(srcdir)/config/rs6000/tramp.asm > tramp.S
-
-# Switch synonyms
-MULTILIB_MATCHES_FLOAT	= msoft-float=mcpu?401 \
-			  msoft-float=mcpu?403 \
-			  msoft-float=mcpu?ec603e \
-			  msoft-float=mcpu?801 \
-			  msoft-float=mcpu?821 \
-			  msoft-float=mcpu?823 \
-			  msoft-float=mcpu?860
-MULTILIB_MATCHES_ENDIAN	= mlittle=mlittle-endian mbig=mbig-endian
-MULTILIB_MATCHES_SYSV	= mcall-sysv=mcall-sysv-eabi mcall-sysv=mcall-sysv-noeabi
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-EXTRA_MULTILIB_PARTS = ecrti$(objext) ecrtn$(objext) scrt0$(objext) scrti$(objext) scrtn$(objext)
-
-# We build {e,s}crti.o, {e,s}crtn.o, and scrt0.o which serve to add begin and
-# end labels to all of the special sections used when we link using gcc.
-
-# Assemble startup files.
-ecrti.S: $(srcdir)/config/rs6000/eabi-ci.asm
-	cat $(srcdir)/config/rs6000/eabi-ci.asm >ecrti.S
-
-ecrtn.S: $(srcdir)/config/rs6000/eabi-cn.asm
-	cat $(srcdir)/config/rs6000/eabi-cn.asm >ecrtn.S
-
-scrti.S: $(srcdir)/config/rs6000/sol-ci.asm
-	cat $(srcdir)/config/rs6000/sol-ci.asm >scrti.S
-
-scrtn.S: $(srcdir)/config/rs6000/sol-cn.asm
-	cat $(srcdir)/config/rs6000/sol-cn.asm >scrtn.S
-
-scrt0.c: $(srcdir)/config/rs6000/sol-c0.c
-	cat $(srcdir)/config/rs6000/sol-c0.c >scrt0.c
-
-# Build multiple copies of ?crt{i,n}.o, one for each target switch.
-$(T)ecrti$(objext): ecrti.S
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c ecrti.S -o $(T)ecrti$(objext)
-
-$(T)ecrtn$(objext): ecrtn.S
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c ecrtn.S -o $(T)ecrtn$(objext)
-
-$(T)scrti$(objext): scrti.S
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c scrti.S -o $(T)scrti$(objext)
-
-$(T)scrtn$(objext): scrtn.S
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c scrtn.S -o $(T)scrtn$(objext)
-
-$(T)scrt0$(objext): scrt0.c
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c scrt0.c -o $(T)scrt0$(objext)
-
-# It is important that crtbegin.o, etc., aren't surprised by stuff in .sdata.
-CRTSTUFF_T_CFLAGS = -msdata=none
-CRTSTUFF_T_CFLAGS_S = -fpic -msdata=none
diff --git a/gcc/config/rs6000/t-ppcgas b/gcc/config/rs6000/t-ppcgas
deleted file mode 100755
index ce4c469..0000000
--- a/gcc/config/rs6000/t-ppcgas
+++ /dev/null
@@ -1,22 +0,0 @@
-# PowerPC embedded support with gas.
-# Build libgcc.a with different options.
-
-MULTILIB_OPTIONS	= msoft-float \
-			  mlittle/mbig \
-			  mcall-sysv/mcall-aix/mcall-linux/mcall-i960-old \
-			  fleading-underscore # CYGNUS local vmakarov: mcall-i960-old and fleading-underscore
-
-MULTILIB_DIRNAMES	= nof \
-			  le be \
-			  cs ca lin o960 \
-			  uns  # CYGNUS local vmakarov: o960 and uns
-
-MULTILIB_EXTRA_OPTS	= mrelocatable-lib mno-eabi mstrict-align
-MULTILIB_EXCEPTIONS	= *mbig/*mcall-linux* \
-			  *mlittle/*mcall-linux* \
-			  *msoft-float/*mcall-linux* \
-			  *mbig/*mcall-i960-old* # CYGNUS local vmakarov
-
-MULTILIB_MATCHES	= ${MULTILIB_MATCHES_FLOAT} \
-			  ${MULTILIB_MATCHES_ENDIAN} \
-			  ${MULTILIB_MATCHES_SYSV}
diff --git a/gcc/config/rs6000/t-ppcos b/gcc/config/rs6000/t-ppcos
deleted file mode 100755
index 480665a..0000000
--- a/gcc/config/rs6000/t-ppcos
+++ /dev/null
@@ -1,12 +0,0 @@
-# Target config file for a System V based system (Solaris, GNU/Linux, Netbsd)
-# with gas.
-
-# Build libgcc.a with different options.  With gas, build pic libraries
-# as well no floating point
-MULTILIB_OPTIONS	= msoft-float fPIC
-MULTILIB_DIRNAMES	= nof pic
-MULTILIB_EXCEPTIONS	=
-MULTILIB_MATCHES	= ${MULTILIB_MATCHES_FLOAT} \
-			  fPIC=mrelocatable-lib \
-			  fPIC=mrelocatable \
-			  fPIC=fpic
diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000
deleted file mode 100755
index 4c659a6..0000000
--- a/gcc/config/rs6000/t-rs6000
+++ /dev/null
@@ -1,22 +0,0 @@
-# Do not build libgcc1.
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# Build the libraries for both hard and soft floating point
-
-MULTILIB_OPTIONS = msoft-float
-MULTILIB_DIRNAMES = soft-float
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/rs6000/t-vxworks b/gcc/config/rs6000/t-vxworks
deleted file mode 100755
index df4f856..0000000
--- a/gcc/config/rs6000/t-vxworks
+++ /dev/null
@@ -1,3 +0,0 @@
-# Inhibit building libc routines under VxWorks for now
-
-TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc
diff --git a/gcc/config/rs6000/t-winnt b/gcc/config/rs6000/t-winnt
deleted file mode 100755
index f58aefe..0000000
--- a/gcc/config/rs6000/t-winnt
+++ /dev/null
@@ -1,35 +0,0 @@
-# Do not build libgcc1.
-LIBGCC1 = 
-CROSS_LIBGCC1 =
-
-EXTRA_PARTS = crti.o crtn.o
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c ntstack.S
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-ntstack.S: $(srcdir)/config/rs6000/ntstack.asm
-	cat $(srcdir)/config/rs6000/ntstack.asm > ntstack.S
-
-# For NT we build crti.o and crtn.o which serve to add begin and
-# end labels for the static constructors and destructors.
-
-# Assemble startup files.
-crti.s: $(srcdir)/config/rs6000/nt-ci.asm
-	cat $(srcdir)/config/rs6000/nt-ci.asm >crti.s
-
-crtn.s: $(srcdir)/config/rs6000/nt-cn.asm
-	cat $(srcdir)/config/rs6000/nt-cn.asm >crtn.s
-
-crti.o: crti.s
-	$(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -c -o crti.o crti.s
-	
-crtn.o: crtn.s
-	$(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -c -o crtn.o crtn.s
diff --git a/gcc/config/rs6000/t-xnewas b/gcc/config/rs6000/t-xnewas
deleted file mode 100755
index 285f825..0000000
--- a/gcc/config/rs6000/t-xnewas
+++ /dev/null
@@ -1,58 +0,0 @@
-# Same as t-newas, except don't build libgcc1-test.  This is because
-# the compiler emits code to call external functions to save the
-# arguments that are in libc, but since libgcc1-test is linked without
-# libc, they will show up as errors.
-LIBGCC1_TEST =
-
-# Do not build libgcc1.
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# Build the libraries for both hard and soft floating point and all of the 
-# different processor models
-
-MULTILIB_OPTIONS	= msoft-float \
-			  mcpu=common/mcpu=power/mcpu=powerpc
-
-MULTILIB_DIRNAMES	= soft-float \
-			  common power powerpc
-
-MULTILIB_MATCHES	= msoft-float=mcpu?403 \
-			  mcpu?power=mpower \
-			  mcpu?power=mrios1 \
-			  mcpu?power=mcpu?rios1 \
-			  mcpu?power=mcpu?rsc \
-			  mcpu?power=mcpu?rsc1 \
-			  mcpu?power=mpower2 \
-			  mcpu?power=mrios2 \
-			  mcpu?power=mcpu=rios2 \
-			  mcpu?powerpc=mcpu?601 \
-			  mcpu?powerpc=mcpu?602 \
-			  mcpu?powerpc=mcpu?603 \
-			  mcpu?powerpc=mcpu?603e \
-			  mcpu?powerpc=mcpu?604 \
-			  mcpu?powerpc=mcpu?620 \
-			  mcpu?powerpc=mcpu?403 \
-			  mcpu?powerpc=mpowerpc \
-			  mcpu?powerpc=mpowerpc-gpopt \
-			  mcpu?powerpc=mpowerpc-gfxopt
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# Aix 3.2.x needs milli.exp for -mcpu=common
-EXTRA_PARTS = milli.exp
-milli.exp: $(srcdir)/config/rs6000/milli.exp
-	rm -f milli.exp
-	cp $(srcdir)/config/rs6000/milli.exp ./milli.exp
diff --git a/gcc/config/rs6000/t-xrs6000 b/gcc/config/rs6000/t-xrs6000
deleted file mode 100755
index f5d34d6..0000000
--- a/gcc/config/rs6000/t-xrs6000
+++ /dev/null
@@ -1,28 +0,0 @@
-# Same as t-rs6000, except don't build libgcc1-test.  This is because
-# the compiler emits code to call external functions to save the
-# arguments that are in libc, but since libgcc1-test is linked without
-# libc, they will show up as errors.
-LIBGCC1_TEST =
-
-# Do not build libgcc1.
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so... [taken from t-sparclite]
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# Build the libraries for both hard and soft floating point
-
-MULTILIB_OPTIONS = msoft-float
-MULTILIB_DIRNAMES = soft-float
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/rs6000/tramp.asm b/gcc/config/rs6000/tramp.asm
deleted file mode 100755
index 47ab7d6..0000000
--- a/gcc/config/rs6000/tramp.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-/*  Special support for trampolines
- *
- *   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
- *   Written By Michael Meissner
- * 
- * This file is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- * 
- * In addition to the permissions in the GNU General Public License, the
- * Free Software Foundation gives you unlimited permission to link the
- * compiled version of this file with other programs, and to distribute
- * those programs without any restriction coming from the use of this
- * file.  (The General Public License restrictions do apply in other
- * respects; for example, they cover modification of the file, and
- * distribution when not linked into another program.)
- * 
- * This file is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, 59 Temple Place - Suite 330,
- * Boston, MA 02111-1307, USA.
- * 
- *    As a special exception, if you link this library with files
- *    compiled with GCC to produce an executable, this does not cause
- *    the resulting executable to be covered by the GNU General Public License.
- *    This exception does not however invalidate any other reasons why
- *    the executable file might be covered by the GNU General Public License.
- */ 
-
-/* Set up trampolines */
-
-	.file	"tramp.asm"
-	.section ".text"
-	#include "ppc-asm.h"
-
-	.globl	__trampoline_initial
-	.type	__trampoline_initial,@object
-	.align	2
-__trampoline_initial:
-	mflr	r0
-	bl	1f
-.Lfunc = .-__trampoline_initial
-	.long	0			/* will be replaced with function address */
-.Lchain = .-__trampoline_initial
-	.long	0			/* will be replaced with static chain */
-1:	mflr	r11
-	mtlr	r0
-	lwz	r0,0(r11)		/* function address */
-	lwz	r11,4(r11)		/* static chain */
-	mtctr	r0
-	bctr
-
-__trampoline_size = .-__trampoline_initial
-	.size	__trampoline_initial,__trampoline_size
-
-        .section ".got2","aw"
-.LCTOC1 = .+32768
-.Ltramp = .-.LCTOC1
-        .long __trampoline_initial-4
-
-	.section ".text"
-.LCL0:
-        .long .LCTOC1-.LCF0
-
-/* R3 = stack address to store trampoline */
-/* R4 = length of trampoline area */
-/* R5 = function address */
-/* R6 = static chain */
-
-FUNC_START(__trampoline_setup)
-	mflr	r0			/* save return address */
-        bl	.LCF0			/* load up __trampoline_initial into r7 */
-.LCF0:
-        mflr	r11
-        lwz	r12,(.LCL0-.LCF0)(r11)
-        add	r11,r12,r11
-        lwz	r7,.Ltramp(r11)		/* trampoline address -4 */
-
-	li	r8,__trampoline_size	/* verify that the trampoline is big enough */
-	cmpw	cr1,r8,r4
-	srwi	r4,r4,2			/* # words to move */
-	addi	r9,r3,-4		/* adjust pointer for lwzu */
-	mtctr	r4
-	blt	cr1,.Labort
-
-	mtlr	r0
-
-	/* Copy the instructions to the stack */
-.Lmove:
-	lwzu	r10,4(r7)
-	stwu	r10,4(r9)
-	bdnz	.Lmove
-
-	/* Store correct function and static chain */
-	stw	r5,.Lfunc(r3)
-	stw	r6,.Lchain(r3)
-
-	/* Now flush both caches */
-	mtctr	r4
-.Lcache:
-	icbi	0,r3
-	dcbf	0,r3
-	addi	r3,r3,4
-	bdnz	.Lcache
-
-	/* Finally synchronize things & return */
-	sync
-	isync
-	blr
-
-.Labort:
-	bl	abort
-FUNC_END(__trampoline_setup)
-/* END CYGNUS LOCAL -- waiting for FSF sources to be restored/meissner */
diff --git a/gcc/config/rs6000/vxppc.h b/gcc/config/rs6000/vxppc.h
deleted file mode 100755
index 83b2348..0000000
--- a/gcc/config/rs6000/vxppc.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Vxworks PowerPC version.
-   Copyright (C) 1996, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file just exists to give specs for the PowerPC running on VxWorks.  */
-
-#include "rs6000/sysv4.h"
-
-/* CYGNUS LOCAL vmakarov */
-#if 0
-/* END CYGNUS LOCAL */
-/* ??? This file redefines CPP_SPEC which is wrong.  It should instead define
-   one of the extra specs that gets included in CPP_SPEC.  For instance,
-   CPP_OS_DEFAULT_SPEC.  The mrelocatable line was copied from CPP_SYSV_SPEC.
-   There is probably other stuff missing.  */
-
-#undef CPP_SPEC
-#define CPP_SPEC "\
-%{posix: -D_POSIX_SOURCE} \
-%{mrelocatable*: -D_RELOCATABLE} \
-%{!mcpu*: \
-  %{mpowerpc*: -D_ARCH_PPC -DCPU=PPC603} \
-  %{!mno-powerpc: -D_ARCH_PPC -DCPU=PPC603}} \
-%{mcpu=powerpc: -D_ARCH_PPC -DCPU=PPC603} \
-%{mcpu=403: -D_ARCH_PPC -DCPU=PPC403} \
-%{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR -DCPU=PPC601} \
-%{mcpu=603: -D_ARCH_PPC -DCPU=PPC603} \
-%{mcpu=604: -D_ARCH_PPC -DCPU=PPC604}"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "\
--D__vxworks -D__vxworks__ -Asystem(vxworks) -Asystem(embedded) \
--Acpu(powerpc) -Amachine(powerpc)"
-
-/* VxWorks does all the library stuff itself.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC ""
-
-/* VxWorks uses object files, not loadable images.  make linker just
-   combine objects. */
-
-#undef LINK_SPEC
-#define LINK_SPEC "-r"
-
-/* VxWorks provides the functionality of crt0.o and friends itself.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC ""
-
-/* CYGNUS LOCAL vmakarov */
-#endif
-
-/* Reset defaults */
-#undef	CPP_OS_DEFAULT_SPEC
-#define CPP_OS_DEFAULT_SPEC "%(cpp_os_vxworks)"
-
-#undef	LIB_DEFAULT_SPEC
-#define LIB_DEFAULT_SPEC "%(lib_vxworks)"
-
-#undef	STARTFILE_DEFAULT_SPEC
-#define STARTFILE_DEFAULT_SPEC "%(startfile_vxworks)"
-
-#undef	ENDFILE_DEFAULT_SPEC
-#define ENDFILE_DEFAULT_SPEC "%(endfile_vxworks)"
-
-#undef	LINK_START_DEFAULT_SPEC
-#define LINK_START_DEFAULT_SPEC "%(link_start_vxworks)"
-
-#undef	LINK_OS_DEFAULT_SPEC
-#define LINK_OS_DEFAULT_SPEC "%(link_os_vxworks)"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "\
--D__vxworks -D__vxworks__ -Asystem(vxworks) -Asystem(embedded) \
--Acpu(powerpc) -Amachine(powerpc)"
-
-/* Don't define _LITTLE_ENDIAN or _BIG_ENDIAN */
-#undef	CPP_ENDIAN_BIG_SPEC
-#define CPP_ENDIAN_BIG_SPEC "-D__BIG_ENDIAN__ -Amachine(bigendian)"
-
-#undef	CPP_ENDIAN_LITTLE_SPEC
-#define CPP_ENDIAN_LITTLE_SPEC "-D__LITTLE_ENDIAN__ -Amachine(littleendian)"
-/* END CYGNUS LOCAL */
-
-/* We use stabs-in-elf for debugging */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
diff --git a/gcc/config/rs6000/vxppcle.h b/gcc/config/rs6000/vxppcle.h
deleted file mode 100755
index fadec99..0000000
--- a/gcc/config/rs6000/vxppcle.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Vxworks PowerPC version.
-   Copyright (C) 1996, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file just exists to give specs for the PowerPC running on VxWorks.  */
-
-#include "rs6000/sysv4le.h"
-
-/* Reset defaults */
-#undef	CPP_OS_DEFAULT_SPEC
-#define CPP_OS_DEFAULT_SPEC "%(cpp_os_vxworks)"
-
-#undef	LIB_DEFAULT_SPEC
-#define LIB_DEFAULT_SPEC "%(lib_vxworks)"
-
-#undef	STARTFILE_DEFAULT_SPEC
-#define STARTFILE_DEFAULT_SPEC "%(startfile_vxworks)"
-
-#undef	ENDFILE_DEFAULT_SPEC
-#define ENDFILE_DEFAULT_SPEC "%(endfile_vxworks)"
-
-#undef	LINK_START_DEFAULT_SPEC
-#define LINK_START_DEFAULT_SPEC "%(link_start_vxworks)"
-
-#undef	LINK_OS_DEFAULT_SPEC
-#define LINK_OS_DEFAULT_SPEC "%(link_os_vxworks)"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "\
--D__vxworks -D__vxworks__ -Asystem(vxworks) -Asystem(embedded) \
--Acpu(powerpc) -Amachine(powerpc)"
-
-/* Don't define _LITTLE_ENDIAN or _BIG_ENDIAN */
-#undef	CPP_ENDIAN_BIG_SPEC
-#define CPP_ENDIAN_BIG_SPEC "-D__BIG_ENDIAN__ -Amachine(bigendian)"
-
-#undef	CPP_ENDIAN_LITTLE_SPEC
-#define CPP_ENDIAN_LITTLE_SPEC "-D__LITTLE_ENDIAN__ -Amachine(littleendian)"
-
-/* We use stabs-in-elf for debugging */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
diff --git a/gcc/config/rs6000/win-nt.h b/gcc/config/rs6000/win-nt.h
deleted file mode 100755
index 742a5e8..0000000
--- a/gcc/config/rs6000/win-nt.h
+++ /dev/null
@@ -1,481 +0,0 @@
-/* Definitions of target machine for GNU compiler, for PowerPC
-   running Windows/NT.
-   Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Say this is Windows/NT for the other config files.  */
-#define WINDOWS_NT 1
-#define COFF_WITH_PE 1
-
-/* Default ABI to compile code for */
-#define DEFAULT_ABI ABI_NT
-
-#define CPP_DEFAULT_SPEC "-D_ARCH_PPC"
-
-#define ASM_DEFAULT_SPEC "-mppc"
-
-/* Pseudo target that we can test in the md file.  */
-#define	TARGET_WINDOWS_NT 1
-
-#include "rs6000/rs6000.h"
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS)
-
-#undef PROCESSOR_DEFAULT
-#define PROCESSOR_DEFAULT PROCESSOR_POWERPC
-
-#undef	CPP_PREDEFINES
-#define	CPP_PREDEFINES "-DWIN32 -D_WIN32 \
-  -DWINNT -D__STDC__=0 -DALMOST_STDC \
-  -D_POWER -D_ARCH_PPC -D__PPC__ -Asystem(winnt) -Acpu(powerpc) -Amachine(powerpc)"
-
-#if 0
-#include "winnt/win-nt.h"
-#endif
-
-#undef	LIB_SPEC
-#define	LIB_SPEC "%{mwindows:-subsystem:windows -entry:WinMainCRTStartup \
-  USER32.LIB GDI32.LIB COMDLG32.LIB WINSPOOL.LIB} \
- %{!mwindows:-subsystem console -e mainCRTStartup} \
- %{mcrtmt:LIBCMT.LIB KERNEL32.LIB} %{!mcrtmt:-lkernel32 -lcygwin} \
- %{v}"
-
-#undef	LINK_SPEC
-#define	LINK_SPEC "%{v:-V}"
-
-/* Allow switches specified in LIB_SPEC, but don't do anything with them
-   in the compiler.  */
-#undef	SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES	\
-   { "windows",	0 },		\
-   { "crtmt",	0 },
-
-#undef XCOFF_DEBUGGING_INFO
-
-/* this is pure coff, not xcoff */
-#define SDB_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-
-#undef  SDB_DELIM
-#define SDB_DELIM ";"
-
-#undef	PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* NT always runs little endian */
-#undef  BYTES_BIG_ENDIAN
-#define BYTES_BIG_ENDIAN 0 
-
-#undef  WORDS_BIG_ENDIAN
-#define WORDS_BIG_ENDIAN 0 
-
-/* Define cutoff for using external functions to save floating point.
-   Currently on NT, always use inline stores */
-#undef	FP_SAVE_INLINE
-#define FP_SAVE_INLINE(FIRST_REG) ((FIRST_REG) < 64)
-
-/* Note, little endian systems trap on unaligned addresses, so never
-   turn off strict alignment in that case. */
-
-#undef STRICT_ALIGNMENT
-#define	STRICT_ALIGNMENT 1
-
-/* Align stack to 16 byte boundaries */
-#undef	STACK_BOUNDARY
-#define	STACK_BOUNDARY	128
-
-/* No data type wants to be aligned rounder than this.  */
-#undef	BIGGEST_ALIGNMENT
-#define BIGGEST_ALIGNMENT 128
-
-/* NT aligns internal doubles in structures on dword boundaries.  */
-#undef	BIGGEST_FIELD_ALIGNMENT
-#define BIGGEST_FIELD_ALIGNMENT 64
-
-#undef  ADJUST_FIELD_ALIGN
-#undef  ROUND_TYPE_ALIGN
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (PowerPC PE)");
-
-#undef TARGET_DEFAULT 
-#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC)
-
-/* Address to save the TOC register */
-#undef	RS6000_SAVE_TOC
-#define RS6000_SAVE_TOC plus_constant (virtual_incoming_args_rtx, -RS6000_SAVE_AREA - 8)
-
-/* Windows NT specifies that r13 is reserved to the OS, so it is not available
-   to the normal user.  */
-
-#undef	FIXED_R13
-#define FIXED_R13 1
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#undef	ASM_OUTPUT_ALIGNED_COMMON
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGNMENT)	\
-  do { fputs ("\t.comm \t", (FILE));			        \
-       assemble_name ((FILE), (NAME));				\
-       if ( (SIZE) > 4)                                         \
-         fprintf ((FILE), ",%d,%d\n", (SIZE), 3);               \
-       else                                                     \
-	 fprintf( (FILE), ",%d\n", (SIZE));                     \
-  } while (0) 
-
-#undef	ASM_OUTPUT_ALIGNED_LOCAL
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#undef  ASM_OUTPUT_COMMON
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)	\
-  do { fputs ("\t.comm \t", (FILE));			\
-       assemble_name ((FILE), (NAME));			\
-       fprintf ((FILE), ",%d\n", (SIZE)); } while (0)
-
-/* This says how to output an assembler line
-   to define an aligned local common symbol.  */
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  bss_section ();							\
-  ASM_OUTPUT_ALIGN (FILE, exact_log2 (ALIGN / BITS_PER_UNIT));		\
-  ASM_OUTPUT_LABEL (FILE, NAME);					\
-  ASM_OUTPUT_SKIP (FILE, SIZE);						\
-} while (0)
-
-/* Describe how to emit uninitialized external linkage items  */
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN)		\
-do {									\
-  ASM_GLOBALIZE_LABEL (FILE, NAME);					\
-  ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN);			\
-} while (0)
-
-/* This says out to put a global symbol in the BSS section */
-#undef ASM_OUTPUT_ALIGNED_BSS
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
-
-
-/* Stuff to force fit us into the Motorola PPC assembler */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)						\
-do {									\
-  output_file_directive ((FILE), main_input_filename);			\
-  rs6000_file_start (FILE, TARGET_CPU_DEFAULT);				\
-  data_section ();							\
-} while (0)
-
-#undef ASM_FILE_END
-
-#undef	ASM_DECLARE_FUNCTION_NAME
-#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL)			\
-{									\
-  tree exception_args;							\
-  int i;								\
-									\
-  if (TREE_PUBLIC (DECL))						\
-    {									\
-      fprintf (FILE, "\t.globl ..");					\
-      assemble_name (FILE, NAME);					\
-      fprintf (FILE, "\n");						\
-    }									\
-									\
-  fprintf (FILE, "\n#\tFunction: '..");					\
-  assemble_name (FILE, NAME);						\
-  fputs ("'\n", FILE);							\
-  fputs ("#\tText in section: <default>\n\n", FILE);			\
-  fputs ("#\tSetup MS Structured-Exception-Handling\n", FILE);		\
-  fputs ("\t.pdata\n", FILE);						\
-  fputs ("\t.align 2\n", FILE);						\
-  fputs ("\t.ualong ..", FILE);						\
-  assemble_name (FILE, NAME);						\
-  fputs (",", FILE);							\
-  assemble_name (FILE, NAME);						\
-  fputs (".e,", FILE);							\
-  exception_args = lookup_attribute ("exception",			\
-				     TYPE_ATTRIBUTES (TREE_TYPE (DECL))); \
-									\
-  if (exception_args)							\
-    exception_args = TREE_VALUE (exception_args);			\
-									\
-  for (i = 0; i < 2; i++)						\
-    {									\
-      if (!exception_args)						\
-	fputs ("0,", FILE);						\
-      else								\
-	{								\
-	  tree field = TREE_VALUE (exception_args);			\
-	  exception_args = TREE_PURPOSE (exception_args);		\
-	  if (TREE_CODE (field) == STRING_CST)				\
-	    fprintf (FILE, "%.*s,", TREE_STRING_LENGTH (field),		\
-		     TREE_STRING_POINTER (field));			\
-	  else if (TREE_CODE (field) == IDENTIFIER_NODE)		\
-	    fprintf (FILE, "%.*s,", IDENTIFIER_LENGTH (field),		\
-		     IDENTIFIER_POINTER (field));			\
-	  else								\
-	    abort ();							\
-	}								\
-    }									\
-									\
-  assemble_name (FILE, NAME);						\
-  fprintf (FILE, ".b\n\n");						\
-  fprintf (FILE, "#\tSwitch to the relocation section\n");		\
-  fprintf (FILE, "\t.reldata\n");					\
-  assemble_name (FILE, NAME);						\
-  fprintf (FILE, ":\n");						\
-  fprintf (FILE, "\t.ualong ..");					\
-  assemble_name (FILE, NAME);						\
-  fprintf (FILE, ",.toc\n");						\
-									\
-  if (lookup_attribute ("dllexport",					\
-			TYPE_ATTRIBUTES (TREE_TYPE (DECL))))		\
-    {									\
-      fprintf (FILE, "\t.globl __imp_");				\
-      assemble_name (FILE, NAME);					\
-      fprintf (FILE, "\n__imp_");					\
-      assemble_name (FILE, NAME);					\
-      fprintf (FILE, ":\n\t.ulong ");					\
-      assemble_name (FILE, NAME);					\
-      fprintf (FILE, "\n");						\
-    }									\
-									\
-  fprintf (FILE, "\t.section .text\n\t.align 2\n..");			\
-  assemble_name (FILE, NAME);						\
-  fprintf (FILE, ":\n");						\
-  fprintf (FILE, "\t.function\t..");					\
-  assemble_name (FILE, NAME);						\
-  fprintf (FILE, "\n");							\
-}
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#undef	ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t[2];							\
-	REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);			\
-	fprintf (FILE, "\t.ualong 0x%lx\n\t.long 0x%lx\n",		\
-		t[0] & 0xffffffff, t[1] & 0xffffffff);			\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str);			\
-	fprintf (FILE, "\t.double %s\n", str);				\
-      }									\
-  }
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#undef	ASM_OUTPUT_FLOAT
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t;								\
-	REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
-	fprintf (FILE, "\t.ualong 0x%lx\n", t & 0xffffffff);		\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);			\
-	fprintf (FILE, "\t.float %s\n", str);				\
-      }									\
-  }
-
-/* Output before instructions.  */
-#undef TEXT_SECTION_ASM_OP
-#define TEXT_SECTION_ASM_OP "\t.text"
-
-/* Output before writable data.  */
-#undef DATA_SECTION_ASM_OP
-#define DATA_SECTION_ASM_OP "\t.data"
-
-/* Output to the bss section.  */
-#undef BSS_SECTION_ASM_OP
-#define BSS_SECTION_ASM_OP "\t.section .bss"
-
-/* Define the extra sections we need.  We define a dummy TOC section,
-   plus sections to hold the list of static constructors (.ctors) and
-   destructors (.dtors).  */
-
-#undef	READONLY_DATA_SECTION
-#undef	EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_toc, in_ctors, in_dtors
-
-/* Define the routines to implement these extra sections.  */
-
-#undef	EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION						\
-  TOC_SECTION_FUNCTION							\
-
-#define TOC_SECTION_FUNCTION						\
-void									\
-toc_section ()								\
-{									\
-}
-
-#define CTORS_SECTION_ASM_OP	".section\t.ctors"
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_ASM_OP	".section\t.dtors"
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-#undef SELECT_SECTION
-#undef SELECT_RTX_SECTION
-
-/* Make sure __main gets called */
-#define INVOKE__main 1
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#undef	ASM_OUTPUT_CONSTRUCTOR
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t.ualong ");					\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#undef	ASM_OUTPUT_DESTRUCTOR
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t.ualong ");					\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-
-/* Text to write out after a CALL that may be replaced by glue code by
-   the loader.  The motorola asm demands that, for dll support, a .znop
-   be issued after a bl instruction, and the symbol on the .znop is the
-   symbol on the bl instruction */
-
-#undef RS6000_CALL_GLUE
-#define RS6000_CALL_GLUE "nop #\tFIXME: only works for non-dll calls."
-
-#define RS6000_CALL_GLUE2 ".znop "
-
-#undef ASM_OUTPUT_SPECIAL_POOL_ENTRY
-
-/* Output something to declare an external symbol to the assembler.  Most
-   assemblers don't need this.  */
-
-#undef ASM_OUTPUT_EXTERNAL
-
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)				\
-{									\
-  char *_name;								\
-  rtx _symref = XEXP (DECL_RTL (DECL), 0);				\
-  if ((TREE_CODE (DECL) == VAR_DECL					\
-       || TREE_CODE (DECL) == FUNCTION_DECL)				\
-      && (NAME)[strlen (NAME) - 1] != ']')				\
-    {									\
-      _name = (char *) permalloc (strlen (XSTR (_symref, 0)) + 5);	\
-      strcpy (_name, XSTR (_symref, 0));				\
-      XSTR (_symref, 0) = _name;					\
-    }									\
-  else									\
-    _name = XSTR (_symref, 0);						\
-									\
-  if (DECL_FUNCTION_CODE (DECL) == 0)					\
-    {									\
-      fputs ("\t.extern ", FILE);					\
-      assemble_name (FILE, _name);					\
-      putc ('\n', FILE);						\
-      if (TREE_CODE (DECL) == FUNCTION_DECL)				\
-	{								\
-	  fputs ("\t.extern ..", FILE);					\
-	  assemble_name (FILE, _name);					\
-	  putc ('\n', FILE);						\
-	}								\
-    }									\
-}
-
-/* Similar, but for libcall.  We only have to worry about the function name,
-   not that of the descriptor. */
-
-#undef ASM_OUTPUT_EXTERNAL_LIBCALL
-
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN)	\
-{ fprintf (FILE, "\t.extern ..");		\
-  assemble_name (FILE, XSTR (FUN, 0));		\
-  fprintf (FILE, "\n");				\
-}
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX ".."
-
-/* Eliminate AIX style constant pool processing */
-#undef	LEGITIMATE_CONSTANT_POOL_BASE_P
-#define	LEGITIMATE_CONSTANT_POOL_BASE_P(X) 0
-
-#undef	LEGITIMATE_CONSTANT_POOL_ADDRESS_P
-#define	LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) 0
-
-#undef ASM_OUTPUT_SPECIAL_POOL_ENTRY
-
-#undef  ASM_IDENTIFY_GCC
-#define ASM_IDENTIFY_GCC(x)
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.
-
-   The trampoline should set the static chain pointer to value placed
-   into the trampoline and should branch to the specified routine.  */
-#define TRAMPOLINE_TEMPLATE(FILE) rs6000_trampoline_template (FILE)
diff --git a/gcc/config/rs6000/x-aix31 b/gcc/config/rs6000/x-aix31
deleted file mode 100755
index 9f171fc..0000000
--- a/gcc/config/rs6000/x-aix31
+++ /dev/null
@@ -1,9 +0,0 @@
-# configuration for IBM rs6000 running aix
-# Show we need to use the C version of ALLOCA
-ALLOCA=alloca.o
-
-# For some reason, we need -lm for cc1.
-# We need -lld for collect2 (actually this only matters
-# for a native compiler, but this is as good a place as any
-# to define the symbol).
-CLIB=-lm -lld
diff --git a/gcc/config/rs6000/x-aix41 b/gcc/config/rs6000/x-aix41
deleted file mode 100755
index 69c666b..0000000
--- a/gcc/config/rs6000/x-aix41
+++ /dev/null
@@ -1,12 +0,0 @@
-# configuration for IBM RS/6000 running AIX 4.1+
-
-# Show we need to use the C version of ALLOCA
-ALLOCA=alloca.o
-
-# We need -lld for collect2 (actually this only matters
-# for a native compiler, but this is as good a place as any
-# to define the symbol).
-CLIB=-lld
-
-# f771 and cc1plus overflow the AIX TOC
-BOOT_LDFLAGS=-Wl,-bbigtoc
diff --git a/gcc/config/rs6000/x-aix43 b/gcc/config/rs6000/x-aix43
deleted file mode 100755
index 072d925..0000000
--- a/gcc/config/rs6000/x-aix43
+++ /dev/null
@@ -1,15 +0,0 @@
-# configuration for IBM RS/6000 running AIX 4.3+
-
-# Show we need to use the C version of ALLOCA
-ALLOCA=alloca.o
-
-# We need -lld for collect2 (actually this only matters
-# for a native compiler, but this is as good a place as any
-# to define the symbol).
-CLIB=-lld
-
-# f771 and cc1plus overflow the AIX TOC
-BOOT_LDFLAGS=-Wl,-bbigtoc
-
-# Both 32-bit and 64-bit objects in archives
-AR_FOR_TARGET=ar -X32_64
diff --git a/gcc/config/rs6000/x-beos b/gcc/config/rs6000/x-beos
deleted file mode 100755
index 37b8cca..0000000
--- a/gcc/config/rs6000/x-beos
+++ /dev/null
@@ -1,9 +0,0 @@
-# configuration for BeOS
-INSTALL=install -c
-
-# Show we need to use the C version of ALLOCA
-ALLOCA=alloca.o
-# Use it regardless of whether we are compiling with gcc or not.
-USE_ALLOCA= `echo "${ALLOCA}"`
-USE_HOST_ALLOCA= `echo ${HOST_PREFIX}${HOST_ALLOCA}`
-SUBDIR_USE_ALLOCA = `if [ x$(ALLOCA) != x ]; then echo ../$(ALLOCA); else true; fi`
diff --git a/gcc/config/rs6000/x-cygwin b/gcc/config/rs6000/x-cygwin
deleted file mode 100755
index 5e796a0..0000000
--- a/gcc/config/rs6000/x-cygwin
+++ /dev/null
@@ -1,4 +0,0 @@
-# Don't run fixproto
-STMP_FIXPROTO =
-# Don't need collect2
-USE_COLLECT2 =
diff --git a/gcc/config/rs6000/x-lynx b/gcc/config/rs6000/x-lynx
deleted file mode 100755
index a1a2a73..0000000
--- a/gcc/config/rs6000/x-lynx
+++ /dev/null
@@ -1,14 +0,0 @@
-# /bin/cc is hopelessly broken, so we must use /bin/gcc instead.
-CC	= $(OLDCC)
-OLDCC	= /bin/gcc
-
-# /bin/sh is too buggy, so use /bin/bash instead.
-SHELL = /bin/bash
-
-# Show we need to use the C version of ALLOCA
-ALLOCA=alloca.o
-
-# configuration for IBM rs6000 running lynx
-
-# For some reason, we need -lm for cc1.
-CLIB=-lm
diff --git a/gcc/config/rs6000/x-mach b/gcc/config/rs6000/x-mach
deleted file mode 100755
index 64f39a5..0000000
--- a/gcc/config/rs6000/x-mach
+++ /dev/null
@@ -1,7 +0,0 @@
-# configuration for IBM rs6000 running MACH
-
-# Show we need to use the C version of ALLOCA
-ALLOCA=alloca.o
-
-# For some reason, we need -lm for cc1.
-CLIB=-lm
diff --git a/gcc/config/rs6000/x-rs6000 b/gcc/config/rs6000/x-rs6000
deleted file mode 100755
index 0d8f311..0000000
--- a/gcc/config/rs6000/x-rs6000
+++ /dev/null
@@ -1,9 +0,0 @@
-# configuration for IBM rs6000 running aix
-
-# Show we need to use the C version of ALLOCA
-ALLOCA=alloca.o
-
-# We need -lld for collect2 (actually this only matters
-# for a native compiler, but this is as good a place as any
-# to define the symbol).
-CLIB=-lld
diff --git a/gcc/config/rs6000/x-sysv4 b/gcc/config/rs6000/x-sysv4
deleted file mode 100755
index 2a661e3..0000000
--- a/gcc/config/rs6000/x-sysv4
+++ /dev/null
@@ -1,2 +0,0 @@
-X_CFLAGS=-DSVR4
-ALLOCA=alloca.o
diff --git a/gcc/config/rs6000/xm-beos.h b/gcc/config/rs6000/xm-beos.h
deleted file mode 100755
index 681aa73..0000000
--- a/gcc/config/rs6000/xm-beos.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Configuration for GNU C-compiler for BeOS host.
-   Copyright (C) 1997 Free Software Foundation, Inc.
-   Contributed by Fred Fish (fnf@cygnus.com), based on xm-rs6000.h
-   by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
-
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-
-#define	FALSE	0
-#define	TRUE	1
-
-/* This describes the machine the compiler is hosted on.  */
-
-#define	HOST_BITS_PER_CHAR	8
-#define	HOST_BITS_PER_SHORT	16
-#define	HOST_BITS_PER_INT	32
-#define	HOST_BITS_PER_LONG	32
-#define HOST_BITS_PER_LONGLONG	64
-
-#define	HOST_WORDS_BIG_ENDIAN
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-
-#define	SUCCESS_EXIT_CODE	0
-#define	FATAL_EXIT_CODE		33
-
-/* Use the C alloca and use only int bitfields.  */
-
-#define USE_C_ALLOCA
-extern void *alloca ();
-#define	ONLY_INT_FIELDS
-
-/* use ANSI/SYSV style byte manipulation routines instead of BSD ones */
-
-#undef bcopy
-#define bcopy(s,d,n)	memmove((d),(s),(n))
-#undef bzero
-#define bzero(d,n)	memset((d),0,(n))
-#undef bcmp
-#define bcmp(l,r,n)	memcmp((l),(r),(n))
-#undef index
-#define index		strchr
-#undef rindex
-#define rindex		strrchr
-
-/* BeOS is closer to USG than BSD */
-
-#define USG
-
-/* Define various things that the BeOS host has. */
-
-#define HAVE_VPRINTF
-#define HAVE_PUTENV
-#define HAVE_ATEXIT
-#define HAVE_RENAME
-
-#define STDC_HEADERS 1
-
-/* STANDARD_INCLUDE_DIR is the equivalent of "/usr/include" on UNIX. */
-
-#define STANDARD_INCLUDE_DIR	"/boot/develop/headers/posix"
-
-/* SYSTEM_INCLUDE_DIR is the location for system specific, non-POSIX headers. */
-
-#define SYSTEM_INCLUDE_DIR	"/boot/develop/headers/be"
-
diff --git a/gcc/config/rs6000/xm-cygwin.h b/gcc/config/rs6000/xm-cygwin.h
deleted file mode 100755
index ca54831..0000000
--- a/gcc/config/rs6000/xm-cygwin.h
+++ /dev/null
@@ -1 +0,0 @@
-#define EXECUTABLE_SUFFIX ".exe"
diff --git a/gcc/config/rs6000/xm-lynx.h b/gcc/config/rs6000/xm-lynx.h
deleted file mode 100755
index 1c093c2..0000000
--- a/gcc/config/rs6000/xm-lynx.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Configuration for GNU C-compiler for rs6000 platforms running LynxOS.
-   Copyright (C) 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <xm-lynx.h>
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_WORDS_BIG_ENDIAN 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-
-#include "tm.h"
diff --git a/gcc/config/rs6000/xm-mach.h b/gcc/config/rs6000/xm-mach.h
deleted file mode 100755
index 2d4ee5d..0000000
--- a/gcc/config/rs6000/xm-mach.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#undef USG
-#undef COLLECT_EXPORT_LIST
diff --git a/gcc/config/rs6000/xm-rs6000.h b/gcc/config/rs6000/xm-rs6000.h
deleted file mode 100755
index 1ad9da9..0000000
--- a/gcc/config/rs6000/xm-rs6000.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Configuration for GNU C-compiler for IBM RS/6000 running AIX in 32-bit mode.
-   Copyright (C) 1990, 1993, 1995, 1998 Free Software Foundation, Inc.
-   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define	FALSE	0
-#define	TRUE	1
-
-/* This describes the machine the compiler is hosted on.  */
-#define	HOST_BITS_PER_CHAR	8
-#define	HOST_BITS_PER_SHORT	16
-#define	HOST_BITS_PER_INT	32
-#define	HOST_BITS_PER_LONG	32
-#define	HOST_BITS_PER_LONGLONG	64
-
-#define	HOST_WORDS_BIG_ENDIAN
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define	SUCCESS_EXIT_CODE	0
-#define	FATAL_EXIT_CODE		33
-
-/* If not compiled with GNU C, use the C alloca and use only int bitfields.  */
-#ifndef __GNUC__
-#define USE_C_ALLOCA
-#if __STDC__
-extern void *alloca ();
-#else
-extern char *alloca ();
-#endif
-#define	ONLY_INT_FIELDS
-#endif
-
-/* AIX is a flavor of System V */
-#define	USG
-
-/* Big buffers improve performance.  */
-#define IO_BUFFER_SIZE (0x8000 - 4096)
-
-#ifndef CROSS_COMPILE
-/* The AIX linker will discard static constructors in object files before
-   collect has a chance to see them, so scan the object files directly.  */
-#define COLLECT_EXPORT_LIST
-#endif
diff --git a/gcc/config/rs6000/xm-sysv4.h b/gcc/config/rs6000/xm-sysv4.h
deleted file mode 100755
index cf56eb4..0000000
--- a/gcc/config/rs6000/xm-sysv4.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Configuration for GNU C-compiler for PowerPC running System V.4.
-   Copyright (C) 1995, 1998 Free Software Foundation, Inc.
-
-   Cloned from sparc/xm-sysv4.h by Michael Meissner (meissner@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#if 0
-#define HOST_BITS_PER_LONGLONG 64
-#endif
-
-/* Doubles are stored in memory with the high order word first.  This
-   matters when cross-compiling.  */
-#define HOST_WORDS_BIG_ENDIAN 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-#ifdef __linux__
-#include "xm-linux.h"
-#endif
-
-/* if not compiled with GNU C, use the C alloca and use only int bitfields. */
-#ifndef __GNUC__
-#define	USE_C_ALLOCA
-#ifdef __STDC__
-extern void *alloca ();
-#else
-extern char *alloca ();
-#endif
-#undef ONLY_INT_FIELDS
-#define ONLY_INT_FIELDS
-#endif
-
-#ifdef __PPC__
-#ifndef __STDC__
-extern char *malloc (), *realloc (), *calloc ();
-#else
-extern void *malloc (), *realloc (), *calloc ();
-#endif
-extern void free ();
-#endif
diff --git a/gcc/config/sh/elf.h b/gcc/config/sh/elf.h
deleted file mode 100755
index 68cc691..0000000
--- a/gcc/config/sh/elf.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* Definitions of target machine for gcc for Hitachi Super-H using ELF.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Ian Lance Taylor <ian@cygnus.com>.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Mostly like the regular SH configuration.  */
-#include "sh/sh.h"
-
-/* No SDB debugging info.  */
-#undef SDB_DEBUGGING_INFO
-
-/* Undefine some macros defined in both sh.h and svr4.h.  */
-#undef IDENT_ASM_OP
-#undef ASM_FILE_END
-#undef ASM_OUTPUT_SOURCE_LINE
-#undef DBX_OUTPUT_MAIN_SOURCE_FILE_END
-#undef CTORS_SECTION_ASM_OP
-#undef DTORS_SECTION_ASM_OP
-#undef ASM_OUTPUT_SECTION_NAME
-#undef ASM_OUTPUT_CONSTRUCTOR
-#undef ASM_OUTPUT_DESTRUCTOR
-#undef ASM_DECLARE_FUNCTION_NAME
-#undef PREFERRED_DEBUGGING_TYPE
-#undef MAX_OFILE_ALIGNMENT
-
-/* Be ELF-like.  */
-#include "svr4.h"
-
-/* The prefix to add to user-visible assembler symbols.
-   Note that svr4.h redefined it from the original value (that we want)
-   in sh.h */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX "_"
-
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX "."
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) do {				\
-  output_file_directive ((FILE), main_input_filename);		\
-  if (TARGET_LITTLE_ENDIAN)					\
-    fprintf ((FILE), "\t.little\n");				\
-} while (0)
-
-
-
-/* Let code know that this is ELF.  */
-#define CPP_PREDEFINES "-D__sh__ -D__ELF__ -Acpu(sh) -Amachine(sh)"
-
-/* Pass -ml and -mrelax to the assembler and linker.  */
-#undef ASM_SPEC
-#define ASM_SPEC  "%{ml:-little} %{mrelax:-relax}"
-
-#undef LINK_SPEC
-#define LINK_SPEC "%{ml:-m shlelf} %{mrelax:-relax}"
-
-/* svr4.h undefined DBX_REGISTER_NUMBER, so we need to define it
-   again.  */
-#define DBX_REGISTER_NUMBER(REGNO)	\
-  (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO))
-
-/* SH ELF, unlike most ELF implementations, uses underscores before
-   symbol names.  */
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(STREAM,NAME) \
-  asm_fprintf (STREAM, "%U%s", NAME)
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
-  sprintf ((STRING), "*%s%s%d", LOCAL_LABEL_PREFIX, (PREFIX), (NUM))
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
-  asm_fprintf ((FILE), "%L%s%d:\n", (PREFIX), (NUM))
-
-#undef  ASM_OUTPUT_SOURCE_LINE
-#define ASM_OUTPUT_SOURCE_LINE(file, line)				\
-do									\
-  {									\
-    static int sym_lineno = 1;						\
-    asm_fprintf ((file), ".stabn 68,0,%d,%LLM%d-",			\
-	     (line), sym_lineno);					\
-    assemble_name ((file),						\
-		   XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));\
-    asm_fprintf ((file), "\n%LLM%d:\n", sym_lineno);			\
-    sym_lineno += 1;							\
-  }									\
-while (0)
-
-#undef DBX_OUTPUT_MAIN_SOURCE_FILE_END
-#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME)			\
-do {									\
-  text_section ();							\
-  fprintf ((FILE), "\t.stabs \"\",%d,0,0,Letext\nLetext:\n", N_SO);	\
-} while (0)
-
-/* Arrange to call __main, rather than using crtbegin.o and crtend.o
-   and relying on .init and .fini being executed at appropriate times.  */
-#undef INIT_SECTION_ASM_OP
-#undef FINI_SECTION_ASM_OP
-#undef STARTFILE_SPEC
-#undef ENDFILE_SPEC
-
-/* HANDLE_SYSV_PRAGMA (defined by svr4.h) takes precedence over HANDLE_PRAGMA.
-   We want to use the HANDLE_PRAGMA from sh.h.  */
-#undef HANDLE_SYSV_PRAGMA
diff --git a/gcc/config/sh/lib1funcs.asm b/gcc/config/sh/lib1funcs.asm
deleted file mode 100755
index bf9ea9a..0000000
--- a/gcc/config/sh/lib1funcs.asm
+++ /dev/null
@@ -1,1206 +0,0 @@
-/* Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with other files,
-   some of which are compiled with GCC, to produce an executable,
-   this library does not by itself cause the resulting executable
-   to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-
-!! libgcc1 routines for the Hitachi SH cpu.
-!! Contributed by Steve Chamberlain.
-!! sac@cygnus.com
-
-!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
-!! recoded in assembly by Toshiyasu Morita
-!! tm@netcom.com
-
-/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
-   ELF local label prefixes by J"orn Rennecke
-   amylaar@cygnus.com  */
-
-#ifdef __ELF__
-#define LOCAL(X) .L_##X
-#else
-#define LOCAL(X) L_##X
-#endif
-
-#ifdef L_ashiftrt
-	.global	___ashiftrt_r4_0
-	.global	___ashiftrt_r4_1
-	.global	___ashiftrt_r4_2
-	.global	___ashiftrt_r4_3
-	.global	___ashiftrt_r4_4
-	.global	___ashiftrt_r4_5
-	.global	___ashiftrt_r4_6
-	.global	___ashiftrt_r4_7
-	.global	___ashiftrt_r4_8
-	.global	___ashiftrt_r4_9
-	.global	___ashiftrt_r4_10
-	.global	___ashiftrt_r4_11
-	.global	___ashiftrt_r4_12
-	.global	___ashiftrt_r4_13
-	.global	___ashiftrt_r4_14
-	.global	___ashiftrt_r4_15
-	.global	___ashiftrt_r4_16
-	.global	___ashiftrt_r4_17
-	.global	___ashiftrt_r4_18
-	.global	___ashiftrt_r4_19
-	.global	___ashiftrt_r4_20
-	.global	___ashiftrt_r4_21
-	.global	___ashiftrt_r4_22
-	.global	___ashiftrt_r4_23
-	.global	___ashiftrt_r4_24
-	.global	___ashiftrt_r4_25
-	.global	___ashiftrt_r4_26
-	.global	___ashiftrt_r4_27
-	.global	___ashiftrt_r4_28
-	.global	___ashiftrt_r4_29
-	.global	___ashiftrt_r4_30
-	.global	___ashiftrt_r4_31
-	.global	___ashiftrt_r4_32
-
-	.align	1
-___ashiftrt_r4_32:
-___ashiftrt_r4_31:
-	rotcl	r4
-	rts
-	subc	r4,r4
-
-___ashiftrt_r4_30:
-	shar	r4
-___ashiftrt_r4_29:
-	shar	r4
-___ashiftrt_r4_28:
-	shar	r4
-___ashiftrt_r4_27:
-	shar	r4
-___ashiftrt_r4_26:
-	shar	r4
-___ashiftrt_r4_25:
-	shar	r4
-___ashiftrt_r4_24:
-	shlr16	r4
-	shlr8	r4
-	rts
-	exts.b	r4,r4
-
-___ashiftrt_r4_23:
-	shar	r4
-___ashiftrt_r4_22:
-	shar	r4
-___ashiftrt_r4_21:
-	shar	r4
-___ashiftrt_r4_20:
-	shar	r4
-___ashiftrt_r4_19:
-	shar	r4
-___ashiftrt_r4_18:
-	shar	r4
-___ashiftrt_r4_17:
-	shar	r4
-___ashiftrt_r4_16:
-	shlr16	r4
-	rts
-	exts.w	r4,r4
-
-___ashiftrt_r4_15:
-	shar	r4
-___ashiftrt_r4_14:
-	shar	r4
-___ashiftrt_r4_13:
-	shar	r4
-___ashiftrt_r4_12:
-	shar	r4
-___ashiftrt_r4_11:
-	shar	r4
-___ashiftrt_r4_10:
-	shar	r4
-___ashiftrt_r4_9:
-	shar	r4
-___ashiftrt_r4_8:
-	shar	r4
-___ashiftrt_r4_7:
-	shar	r4
-___ashiftrt_r4_6:
-	shar	r4
-___ashiftrt_r4_5:
-	shar	r4
-___ashiftrt_r4_4:
-	shar	r4
-___ashiftrt_r4_3:
-	shar	r4
-___ashiftrt_r4_2:
-	shar	r4
-___ashiftrt_r4_1:
-	rts
-	shar	r4
-
-___ashiftrt_r4_0:
-	rts
-	nop
-#endif
-
-#ifdef L_ashiftrt_n
-
-!
-! ___ashrsi3
-!
-! Entry:
-!
-! r4: Value to shift
-! r5: Shifts
-!
-! Exit:
-!
-! r0: Result
-!
-! Destroys:
-!
-! (none)
-!
-
-	.global	___ashrsi3
-	.align	2
-___ashrsi3:
-	mov	#31,r0
-	and	r0,r5
-	mova	LOCAL(ashrsi3_table),r0
-	mov.b	@(r0,r5),r5
-#ifdef __sh1__
-	add	r5,r0
-	jmp	@r0
-#else
-	braf	r5
-#endif
-	mov	r4,r0
-
-	.align	2
-LOCAL(ashrsi3_table):
-	.byte		LOCAL(ashrsi3_0)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_1)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_2)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_3)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_4)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_5)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_6)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_7)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_8)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_9)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_10)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_11)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_12)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_13)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_14)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_15)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_16)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_17)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_18)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_19)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_20)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_21)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_22)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_23)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_24)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_25)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_26)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_27)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_28)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_29)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_30)-LOCAL(ashrsi3_table)
-	.byte		LOCAL(ashrsi3_31)-LOCAL(ashrsi3_table)
-
-LOCAL(ashrsi3_31):
-	rotcl	r0
-	rts
-	subc	r0,r0
-
-LOCAL(ashrsi3_30):
-	shar	r0
-LOCAL(ashrsi3_29):
-	shar	r0
-LOCAL(ashrsi3_28):
-	shar	r0
-LOCAL(ashrsi3_27):
-	shar	r0
-LOCAL(ashrsi3_26):
-	shar	r0
-LOCAL(ashrsi3_25):
-	shar	r0
-LOCAL(ashrsi3_24):
-	shlr16	r0
-	shlr8	r0
-	rts
-	exts.b	r0,r0
-
-LOCAL(ashrsi3_23):
-	shar	r0
-LOCAL(ashrsi3_22):
-	shar	r0
-LOCAL(ashrsi3_21):
-	shar	r0
-LOCAL(ashrsi3_20):
-	shar	r0
-LOCAL(ashrsi3_19):
-	shar	r0
-LOCAL(ashrsi3_18):
-	shar	r0
-LOCAL(ashrsi3_17):
-	shar	r0
-LOCAL(ashrsi3_16):
-	shlr16	r0
-	rts
-	exts.w	r0,r0
-
-LOCAL(ashrsi3_15):
-	shar	r0
-LOCAL(ashrsi3_14):
-	shar	r0
-LOCAL(ashrsi3_13):
-	shar	r0
-LOCAL(ashrsi3_12):
-	shar	r0
-LOCAL(ashrsi3_11):
-	shar	r0
-LOCAL(ashrsi3_10):
-	shar	r0
-LOCAL(ashrsi3_9):
-	shar	r0
-LOCAL(ashrsi3_8):
-	shar	r0
-LOCAL(ashrsi3_7):
-	shar	r0
-LOCAL(ashrsi3_6):
-	shar	r0
-LOCAL(ashrsi3_5):
-	shar	r0
-LOCAL(ashrsi3_4):
-	shar	r0
-LOCAL(ashrsi3_3):
-	shar	r0
-LOCAL(ashrsi3_2):
-	shar	r0
-LOCAL(ashrsi3_1):
-	rts
-	shar	r0
-
-LOCAL(ashrsi3_0):
-	rts
-	nop
-
-#endif
-
-#ifdef L_ashiftlt
-
-!
-! ___ashlsi3
-!
-! Entry:
-!
-! r4: Value to shift
-! r5: Shifts
-!
-! Exit:
-!
-! r0: Result
-!
-! Destroys:
-!
-! (none)
-!
-	.global	___ashlsi3
-	.align	2
-___ashlsi3:
-	mov	#31,r0
-	and	r0,r5
-	mova	LOCAL(ashlsi3_table),r0
-	mov.b	@(r0,r5),r5
-#ifdef __sh1__
-	add	r5,r0
-	jmp	@r0
-#else
-	braf	r5
-#endif
-	mov	r4,r0
-
-	.align	2
-LOCAL(ashlsi3_table):
-	.byte		LOCAL(ashlsi3_0)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_1)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_2)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_3)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_4)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_5)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_6)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_7)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_8)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_9)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_10)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_11)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_12)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_13)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_14)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_15)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_16)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_17)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_18)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_19)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_20)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_21)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_22)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_23)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_24)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_25)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_26)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_27)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_28)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_29)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_30)-LOCAL(ashlsi3_table)
-	.byte		LOCAL(ashlsi3_31)-LOCAL(ashlsi3_table)
-
-LOCAL(ashlsi3_6):
-	shll2	r0
-LOCAL(ashlsi3_4):
-	shll2	r0
-LOCAL(ashlsi3_2):
-	rts
-	shll2	r0
-
-LOCAL(ashlsi3_7):
-	shll2	r0
-LOCAL(ashlsi3_5):
-	shll2	r0
-LOCAL(ashlsi3_3):
-	shll2	r0
-LOCAL(ashlsi3_1):
-	rts
-	shll	r0
-
-LOCAL(ashlsi3_14):
-	shll2	r0
-LOCAL(ashlsi3_12):
-	shll2	r0
-LOCAL(ashlsi3_10):
-	shll2	r0
-LOCAL(ashlsi3_8):
-	rts
-	shll8	r0
-
-LOCAL(ashlsi3_15):
-	shll2	r0
-LOCAL(ashlsi3_13):
-	shll2	r0
-LOCAL(ashlsi3_11):
-	shll2	r0
-LOCAL(ashlsi3_9):
-	shll8	r0
-	rts
-	shll	r0
-
-LOCAL(ashlsi3_22):
-	shll2	r0
-LOCAL(ashlsi3_20):
-	shll2	r0
-LOCAL(ashlsi3_18):
-	shll2	r0
-LOCAL(ashlsi3_16):
-	rts
-	shll16	r0
-
-LOCAL(ashlsi3_23):
-	shll2	r0
-LOCAL(ashlsi3_21):
-	shll2	r0
-LOCAL(ashlsi3_19):
-	shll2	r0
-LOCAL(ashlsi3_17):
-	shll16	r0
-	rts
-	shll	r0
-
-LOCAL(ashlsi3_30):
-	shll2	r0
-LOCAL(ashlsi3_28):
-	shll2	r0
-LOCAL(ashlsi3_26):
-	shll2	r0
-LOCAL(ashlsi3_24):
-	shll16	r0
-	rts
-	shll8	r0
-
-LOCAL(ashlsi3_31):
-	shll2	r0
-LOCAL(ashlsi3_29):
-	shll2	r0
-LOCAL(ashlsi3_27):
-	shll2	r0
-LOCAL(ashlsi3_25):
-	shll16	r0
-	shll8	r0
-	rts
-	shll	r0
-
-LOCAL(ashlsi3_0):
-	rts
-	nop
-
-#endif
-
-#ifdef L_lshiftrt
-
-!
-! ___lshrsi3
-!
-! Entry:
-!
-! r4: Value to shift
-! r5: Shifts
-!
-! Exit:
-!
-! r0: Result
-!
-! Destroys:
-!
-! (none)
-!
-	.global	___lshrsi3
-	.align	2
-___lshrsi3:
-	mov	#31,r0
-	and	r0,r5
-	mova	LOCAL(lshrsi3_table),r0
-	mov.b	@(r0,r5),r5
-#ifdef __sh1__
-	add	r5,r0
-	jmp	@r0
-#else
-	braf	r5
-#endif
-	mov	r4,r0
-
-	.align	2
-LOCAL(lshrsi3_table):
-	.byte		LOCAL(lshrsi3_0)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_1)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_2)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_3)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_4)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_5)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_6)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_7)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_8)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_9)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_10)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_11)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_12)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_13)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_14)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_15)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_16)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_17)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_18)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_19)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_20)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_21)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_22)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_23)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_24)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_25)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_26)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_27)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_28)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_29)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_30)-LOCAL(lshrsi3_table)
-	.byte		LOCAL(lshrsi3_31)-LOCAL(lshrsi3_table)
-
-LOCAL(lshrsi3_6):
-	shlr2	r0
-LOCAL(lshrsi3_4):
-	shlr2	r0
-LOCAL(lshrsi3_2):
-	rts
-	shlr2	r0
-
-LOCAL(lshrsi3_7):
-	shlr2	r0
-LOCAL(lshrsi3_5):
-	shlr2	r0
-LOCAL(lshrsi3_3):
-	shlr2	r0
-LOCAL(lshrsi3_1):
-	rts
-	shlr	r0
-
-LOCAL(lshrsi3_14):
-	shlr2	r0
-LOCAL(lshrsi3_12):
-	shlr2	r0
-LOCAL(lshrsi3_10):
-	shlr2	r0
-LOCAL(lshrsi3_8):
-	rts
-	shlr8	r0
-
-LOCAL(lshrsi3_15):
-	shlr2	r0
-LOCAL(lshrsi3_13):
-	shlr2	r0
-LOCAL(lshrsi3_11):
-	shlr2	r0
-LOCAL(lshrsi3_9):
-	shlr8	r0
-	rts
-	shlr	r0
-
-LOCAL(lshrsi3_22):
-	shlr2	r0
-LOCAL(lshrsi3_20):
-	shlr2	r0
-LOCAL(lshrsi3_18):
-	shlr2	r0
-LOCAL(lshrsi3_16):
-	rts
-	shlr16	r0
-
-LOCAL(lshrsi3_23):
-	shlr2	r0
-LOCAL(lshrsi3_21):
-	shlr2	r0
-LOCAL(lshrsi3_19):
-	shlr2	r0
-LOCAL(lshrsi3_17):
-	shlr16	r0
-	rts
-	shlr	r0
-
-LOCAL(lshrsi3_30):
-	shlr2	r0
-LOCAL(lshrsi3_28):
-	shlr2	r0
-LOCAL(lshrsi3_26):
-	shlr2	r0
-LOCAL(lshrsi3_24):
-	shlr16	r0
-	rts
-	shlr8	r0
-
-LOCAL(lshrsi3_31):
-	shlr2	r0
-LOCAL(lshrsi3_29):
-	shlr2	r0
-LOCAL(lshrsi3_27):
-	shlr2	r0
-LOCAL(lshrsi3_25):
-	shlr16	r0
-	shlr8	r0
-	rts
-	shlr	r0
-
-LOCAL(lshrsi3_0):
-	rts
-	nop
-
-#endif
-
-#ifdef L_movstr
-	.text
-! done all the large groups, do the remainder
-
-! jump to movstr+
-done:
-	add	#64,r5
-	mova	___movstrSI0,r0
-	shll2	r6
-	add	r6,r0
-	jmp	@r0
-	add	#64,r4
-	.align	4
-	.global	___movstrSI64
-___movstrSI64:
-	mov.l	@(60,r5),r0
-	mov.l	r0,@(60,r4)
-	.global	___movstrSI60
-___movstrSI60:
-	mov.l	@(56,r5),r0
-	mov.l	r0,@(56,r4)
-	.global	___movstrSI56
-___movstrSI56:
-	mov.l	@(52,r5),r0
-	mov.l	r0,@(52,r4)
-	.global	___movstrSI52
-___movstrSI52:
-	mov.l	@(48,r5),r0
-	mov.l	r0,@(48,r4)
-	.global	___movstrSI48
-___movstrSI48:
-	mov.l	@(44,r5),r0
-	mov.l	r0,@(44,r4)
-	.global	___movstrSI44
-___movstrSI44:
-	mov.l	@(40,r5),r0
-	mov.l	r0,@(40,r4)
-	.global	___movstrSI40
-___movstrSI40:
-	mov.l	@(36,r5),r0
-	mov.l	r0,@(36,r4)
-	.global	___movstrSI36
-___movstrSI36:
-	mov.l	@(32,r5),r0
-	mov.l	r0,@(32,r4)
-	.global	___movstrSI32
-___movstrSI32:
-	mov.l	@(28,r5),r0
-	mov.l	r0,@(28,r4)
-	.global	___movstrSI28
-___movstrSI28:
-	mov.l	@(24,r5),r0
-	mov.l	r0,@(24,r4)
-	.global	___movstrSI24
-___movstrSI24:
-	mov.l	@(20,r5),r0
-	mov.l	r0,@(20,r4)
-	.global	___movstrSI20
-___movstrSI20:
-	mov.l	@(16,r5),r0
-	mov.l	r0,@(16,r4)
-	.global	___movstrSI16
-___movstrSI16:
-	mov.l	@(12,r5),r0
-	mov.l	r0,@(12,r4)
-	.global	___movstrSI12
-___movstrSI12:
-	mov.l	@(8,r5),r0
-	mov.l	r0,@(8,r4)
-	.global	___movstrSI8
-___movstrSI8:
-	mov.l	@(4,r5),r0
-	mov.l	r0,@(4,r4)
-	.global	___movstrSI4
-___movstrSI4:
-	mov.l	@(0,r5),r0
-	mov.l	r0,@(0,r4)
-___movstrSI0:
-	rts
-	or	r0,r0,r0
-
-	.align	4
-
-	.global	___movstr
-___movstr:
-	mov.l	@(60,r5),r0
-	mov.l	r0,@(60,r4)
-
-	mov.l	@(56,r5),r0
-	mov.l	r0,@(56,r4)
-
-	mov.l	@(52,r5),r0
-	mov.l	r0,@(52,r4)
-
-	mov.l	@(48,r5),r0
-	mov.l	r0,@(48,r4)
-
-	mov.l	@(44,r5),r0
-	mov.l	r0,@(44,r4)
-
-	mov.l	@(40,r5),r0
-	mov.l	r0,@(40,r4)
-
-	mov.l	@(36,r5),r0
-	mov.l	r0,@(36,r4)
-
-	mov.l	@(32,r5),r0
-	mov.l	r0,@(32,r4)
-
-	mov.l	@(28,r5),r0
-	mov.l	r0,@(28,r4)
-
-	mov.l	@(24,r5),r0
-	mov.l	r0,@(24,r4)
-
-	mov.l	@(20,r5),r0
-	mov.l	r0,@(20,r4)
-
-	mov.l	@(16,r5),r0
-	mov.l	r0,@(16,r4)
-
-	mov.l	@(12,r5),r0
-	mov.l	r0,@(12,r4)
-
-	mov.l	@(8,r5),r0
-	mov.l	r0,@(8,r4)
-
-	mov.l	@(4,r5),r0
-	mov.l	r0,@(4,r4)
-
-	mov.l	@(0,r5),r0
-	mov.l	r0,@(0,r4)
-
-	add	#-16,r6
-	cmp/pl	r6
-	bf	done
-
-	add	#64,r5
-	bra	___movstr
-	add	#64,r4
-#endif
-
-#ifdef L_movstr_i4
-#if defined(__SH4__) || defined(__SH4_SINGLE__) || defined(__SH4_SINGLE_ONLY__)
-	.text
-	.global	___movstr_i4_even
-	.global	___movstr_i4_odd
-	.global	___movstrSI12_i4
-
-	.p2align	5
-L_movstr_2mod4_end:
-	mov.l	r0,@(16,r4)
-	rts
-	mov.l	r1,@(20,r4)
-
-	.p2align	2
-
-___movstr_i4_odd:
-	mov.l	@r5+,r1
-	add	#-4,r4
-	mov.l	@r5+,r2
-	mov.l	@r5+,r3
-	mov.l	r1,@(4,r4)
-	mov.l	r2,@(8,r4)
-
-L_movstr_loop:
-	mov.l	r3,@(12,r4)
-	dt	r6
-	mov.l	@r5+,r0
-	bt/s	L_movstr_2mod4_end
-	mov.l	@r5+,r1
-	add	#16,r4
-L_movstr_start_even:
-	mov.l	@r5+,r2
-	mov.l	@r5+,r3
-	mov.l	r0,@r4
-	dt	r6
-	mov.l	r1,@(4,r4)
-	bf/s	L_movstr_loop
-	mov.l	r2,@(8,r4)
-	rts
-	mov.l	r3,@(12,r4)
-
-___movstr_i4_even:
-	mov.l	@r5+,r0
-	bra	L_movstr_start_even
-	mov.l	@r5+,r1
-
-	.p2align	4
-___movstrSI12_i4:
-	mov.l	@r5,r0
-	mov.l	@(4,r5),r1
-	mov.l	@(8,r5),r2
-	mov.l	r0,@r4
-	mov.l	r1,@(4,r4)
-	rts
-	mov.l	r2,@(8,r4)
-#endif /* ! __SH4__ */
-#endif
-
-#ifdef L_mulsi3
-
-
-	.global	___mulsi3
-
-! r4 =       aabb
-! r5 =       ccdd
-! r0 = aabb*ccdd  via partial products
-!
-! if aa == 0 and cc = 0
-! r0 = bb*dd
-!
-! else
-! aa = bb*dd + (aa*dd*65536) + (cc*bb*65536)
-!
-
-___mulsi3:
-	mulu    r4,r5		! multiply the lsws  macl=bb*dd
-	mov     r5,r3		! r3 = ccdd
-	swap.w  r4,r2		! r2 = bbaa
-	xtrct   r2,r3		! r3 = aacc
-	tst  	r3,r3		! msws zero ?
-	bf      hiset
-	rts			! yes - then we have the answer
-	sts     macl,r0
-
-hiset:	sts	macl,r0		! r0 = bb*dd
-	mulu	r2,r5		| brewing macl = aa*dd
-	sts	macl,r1
-	mulu	r3,r4		| brewing macl = cc*bb
-	sts	macl,r2
-	add	r1,r2
-	shll16	r2
-	rts
-	add	r2,r0
-
-
-#endif
-#ifdef L_sdivsi3_i4
-	.title "SH DIVIDE"
-!! 4 byte integer Divide code for the Hitachi SH
-#ifdef __SH4__
-!! args in r4 and r5, result in fpul, clobber dr0, dr2
-
-	.global	___sdivsi3_i4
-___sdivsi3_i4:
-	lds r4,fpul
-	float fpul,dr0
-	lds r5,fpul
-	float fpul,dr2
-	fdiv dr2,dr0
-	rts
-	ftrc dr0,fpul
-
-#elif defined(__SH4_SINGLE__) || defined(__SH4_SINGLE_ONLY__)
-!! args in r4 and r5, result in fpul, clobber r2, dr0, dr2
-
-	.global	___sdivsi3_i4
-___sdivsi3_i4:
-	sts.l fpscr,@-r15
-	mov #8,r2
-	swap.w r2,r2
-	lds r2,fpscr
-	lds r4,fpul
-	float fpul,dr0
-	lds r5,fpul
-	float fpul,dr2
-	fdiv dr2,dr0
-	ftrc dr0,fpul
-	rts
-	lds.l @r15+,fpscr
-
-#endif /* ! __SH4__ */
-#endif
-
-#ifdef L_sdivsi3
-/* __SH4_SINGLE_ONLY__ keeps this part for link compatibility with
-   sh3e code.  */
-#if ! defined(__SH4__) && ! defined (__SH4_SINGLE__)
-!!
-!! Steve Chamberlain
-!! sac@cygnus.com
-!!
-!!
-
-!! args in r4 and r5, result in r0 clobber r1,r2,r3
-
-	.global	___sdivsi3
-___sdivsi3:
-	mov	r4,r1
-	mov	r5,r0
-
-	tst	r0,r0
-	bt	div0
-	mov	#0,r2
-	div0s	r2,r1
-	subc	r3,r3
-	subc	r2,r1
-	div0s	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	div1	r0,r3
-	rotcl	r1
-	addc	r2,r1
-	rts
-	mov	r1,r0
-
-
-div0:	rts
-	mov	#0,r0
-
-#endif /* ! __SH4__ */
-#endif
-#ifdef L_udivsi3_i4
-
-	.title "SH DIVIDE"
-!! 4 byte integer Divide code for the Hitachi SH
-#ifdef __SH4__
-!! args in r4 and r5, result in fpul, clobber r0, r1, r4, r5, dr0, dr2, dr4
-
-	.global	___udivsi3_i4
-___udivsi3_i4:
-	mov #1,r1
-	cmp/hi r1,r5
-	bf trivial
-	rotr r1
-	xor r1,r4
-	lds r4,fpul
-	mova L1,r0
-#ifdef FMOVD_WORKS
-	fmov.d @r0+,dr4
-#else
-#ifdef __LITTLE_ENDIAN__
-	fmov.s @r0+,fr5
-	fmov.s @r0,fr4
-#else
-	fmov.s @r0+,fr4
-	fmov.s @r0,fr5
-#endif
-#endif
-	float fpul,dr0
-	xor r1,r5
-	lds r5,fpul
-	float fpul,dr2
-	fadd dr4,dr0
-	fadd dr4,dr2
-	fdiv dr2,dr0
-	rts
-	ftrc dr0,fpul
-
-trivial:
-	rts
-	lds r4,fpul
-
-	.align 2
-L1:
-	.double 2147483648
-
-#elif defined(__SH4_SINGLE__) || defined(__SH4_SINGLE_ONLY__)
-!! args in r4 and r5, result in fpul, clobber r0, r1, r4, r5, dr0, dr2, dr4
-
-	.global	___udivsi3_i4
-___udivsi3_i4:
-	mov #1,r1
-	cmp/hi r1,r5
-	bf trivial
-	sts.l fpscr,@-r15
-	mova L1,r0
-	lds.l @r0+,fpscr
-	rotr r1
-	xor r1,r4
-	lds r4,fpul
-#ifdef FMOVD_WORKS
-	fmov.d @r0+,dr4
-#else
-#ifdef __LITTLE_ENDIAN__
-	fmov.s @r0+,fr5
-	fmov.s @r0,fr4
-#else
-	fmov.s @r0+,fr4
-	fmov.s @r0,fr5
-#endif
-#endif
-	float fpul,dr0
-	xor r1,r5
-	lds r5,fpul
-	float fpul,dr2
-	fadd dr4,dr0
-	fadd dr4,dr2
-	fdiv dr2,dr0
-	ftrc dr0,fpul
-	rts
-	lds.l @r15+,fpscr
-
-trivial:
-	rts
-	lds r4,fpul
-
-	.align 2
-L1:
-#if defined (__LITTLE_ENDIAN__) || ! defined (FMOVD_WORKS)
-	.long 0x80000
-#else
-	.long 0x180000
-#endif
-	.double 2147483648
-
-#endif /* ! __SH4__ */
-#endif
-
-#ifdef L_udivsi3
-/* __SH4_SINGLE_ONLY__ keeps this part for link compatibility with
-   sh3e code.  */
-#if ! defined(__SH4__) && ! defined (__SH4_SINGLE__)
-!!
-!! Steve Chamberlain
-!! sac@cygnus.com
-!!
-!!
-
-!! args in r4 and r5, result in r0, clobbers r4, pr, and t bit
-	.global	___udivsi3
-
-___udivsi3:
-longway:
-	mov	#0,r0
-	div0u
-	! get one bit from the msb of the numerator into the T
-	! bit and divide it by whats in r5.  Put the answer bit
-	! into the T bit so it can come out again at the bottom
-
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-shortway:
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-
-vshortway:
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4 ; div1 r5,r0
-	rotcl	r4
-ret:	rts
-	mov	r4,r0
-
-#endif /* __SH4__ */
-#endif
-#ifdef L_set_fpscr
-#if defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
-	.global ___set_fpscr
-___set_fpscr:
-	lds r4,fpscr
-	mov.l ___set_fpscr_L1,r1
-	swap.w r4,r0
-	or #24,r0
-#ifndef FMOVD_WORKS
-	xor #16,r0
-#endif
-#if defined(__SH4__)
-	swap.w r0,r3
-	mov.l r3,@(4,r1)
-#else /* defined(__SH3E__) || defined(__SH4_SINGLE*__) */
-	swap.w r0,r2
-	mov.l r2,@r1
-#endif
-#ifndef FMOVD_WORKS
-	xor #8,r0
-#else
-	xor #24,r0
-#endif
-#if defined(__SH4__)
-	swap.w r0,r2
-	rts
-	mov.l r2,@r1
-#else /* defined(__SH3E__) || defined(__SH4_SINGLE*__) */
-	swap.w r0,r3
-	rts
-	mov.l r3,@(4,r1)
-#endif
-	.align 2
-___set_fpscr_L1:
-	.long ___fpscr_values
-#ifdef __ELF__
-        .comm   ___fpscr_values,8,4
-#else
-        .comm   ___fpscr_values,8
-#endif /* ELF */
-#endif /* SH3E / SH4 */
-#endif /* L_set_fpscr */
diff --git a/gcc/config/sh/rtems.h b/gcc/config/sh/rtems.h
deleted file mode 100755
index 3e3fc7b..0000000
--- a/gcc/config/sh/rtems.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Definitions for rtems targeting a SH using COFF.
-   Copyright (C) 1997 Free Software Foundation, Inc.
-   Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sh/sh.h"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D__sh__ -Drtems -D__rtems__ \
-  -Asystem(rtems) -Acpu(sh) -Amachine(sh)"
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#ifndef TARGET_MEM_FUNCTIONS
-#define TARGET_MEM_FUNCTIONS
-#endif
-
-/* end of sh/rtems.h */
diff --git a/gcc/config/sh/rtemself.h b/gcc/config/sh/rtemself.h
deleted file mode 100755
index 8000a3a..0000000
--- a/gcc/config/sh/rtemself.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Definitions for rtems targeting a SH using elf.
-   Copyright (C) 1997 Free Software Foundation, Inc.
-   Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sh/elf.h"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D__sh__ -D__ELF__ -Drtems -D__rtems__ \
-  -Asystem(rtems) -Acpu(sh) -Amachine(sh)"
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#ifndef TARGET_MEM_FUNCTIONS
-#define TARGET_MEM_FUNCTIONS
-#endif
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
deleted file mode 100755
index 4d4b5cd..0000000
--- a/gcc/config/sh/sh.c
+++ /dev/null
@@ -1,4786 +0,0 @@
-/* Output routines for GCC for Hitachi Super-H.
-   Copyright (C) 1993-1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Contributed by Steve Chamberlain (sac@cygnus.com).
-   Improved by Jim Wilson (wilson@cygnus.com).  */
-
-#include "config.h"
-
-#include <stdio.h>
-
-#include "rtl.h"
-#include "tree.h"
-#include "flags.h"
-#include "insn-flags.h"
-#include "expr.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "output.h"
-#include "insn-attr.h"
-
-int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
-
-#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
-#define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
-
-/* ??? The pragma interrupt support will not work for SH3.  */
-/* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
-   output code for the next function appropriate for an interrupt handler.  */
-int pragma_interrupt;
-
-/* This is set by the trap_exit attribute for functions.   It specifies
-   a trap number to be used in a trapa instruction at function exit
-   (instead of an rte instruction).  */
-int trap_exit;
-
-/* This is used by the sp_switch attribute for functions.  It specifies
-   a variable holding the address of the stack the interrupt function
-   should switch to/from at entry/exit.  */
-rtx sp_switch;
-
-/* This is set by #pragma trapa, and is similar to the above, except that
-   the compiler doesn't emit code to preserve all registers.  */
-static int pragma_trapa;
-
-/* This is set by #pragma nosave_low_regs.  This is useful on the SH3,
-   which has a separate set of low regs for User and Supervisor modes.
-   This should only be used for the lowest level of interrupts.  Higher levels
-   of interrupts must save the registers in case they themselves are
-   interrupted.  */
-int pragma_nosave_low_regs;
-
-/* This is used for communication between SETUP_INCOMING_VARARGS and
-   sh_expand_prologue.  */
-int current_function_anonymous_args;
-
-/* Global variables from toplev.c and final.c that are used within, but
-   not declared in any header file.  */
-extern char *version_string;
-extern int *insn_addresses;
-
-/* Global variables for machine-dependent things. */
-
-/* Which cpu are we scheduling for.  */
-enum processor_type sh_cpu;
-
-/* Saved operands from the last compare to use when we generate an scc
-   or bcc insn.  */
-
-rtx sh_compare_op0;
-rtx sh_compare_op1;
-
-enum machine_mode sh_addr_diff_vec_mode;
-
-/* Provides the class number of the smallest class containing
-   reg number.  */
-
-int regno_reg_class[FIRST_PSEUDO_REGISTER] =
-{
-  R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
-  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
-  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
-  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
-  GENERAL_REGS, PR_REGS, T_REGS, NO_REGS,
-  MAC_REGS, MAC_REGS, FPUL_REGS, GENERAL_REGS,
-  FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
-  FP_REGS, FP_REGS, FP_REGS, FP_REGS,
-  FP_REGS, FP_REGS, FP_REGS, FP_REGS,
-  FP_REGS, FP_REGS, FP_REGS, FP_REGS,
-  DF_REGS, DF_REGS, DF_REGS, DF_REGS,
-  DF_REGS, DF_REGS, DF_REGS, DF_REGS,
-  FPSCR_REGS,
-};
-
-char fp_reg_names[][5] =
-{
-  "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
-  "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
-  "fpul",
-  "xd0","xd2","xd4", "xd6", "xd8", "xd10", "xd12", "xd14",
-};
-
-/* Provide reg_class from a letter such as appears in the machine
-   description.  */
-
-enum reg_class reg_class_from_letter[] =
-{
-  /* a */ ALL_REGS, /* b */ NO_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
-  /* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
-  /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ PR_REGS,
-  /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
-  /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
-  /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
-  /* y */ FPUL_REGS, /* z */ R0_REGS
-};
-
-int assembler_dialect;
-
-rtx get_fpscr_rtx ();
-void emit_sf_insn ();
-void emit_df_insn ();
-
-static void split_branches PROTO ((rtx));
-
-/* Print the operand address in x to the stream.  */
-
-void
-print_operand_address (stream, x)
-     FILE *stream;
-     rtx x;
-{
-  switch (GET_CODE (x))
-    {
-    case REG:
-    case SUBREG:
-      fprintf (stream, "@%s", reg_names[true_regnum (x)]);
-      break;
-
-    case PLUS:
-      {
-	rtx base = XEXP (x, 0);
-	rtx index = XEXP (x, 1);
-
-	switch (GET_CODE (index))
-	  {
-	  case CONST_INT:
-	    fprintf (stream, "@(%d,%s)", INTVAL (index),
-		     reg_names[true_regnum (base)]);
-	    break;
-
-	  case REG:
-	  case SUBREG:
-	    {
-	      int base_num = true_regnum (base);
-	      int index_num = true_regnum (index);
-
-	      fprintf (stream, "@(r0,%s)",
-		       reg_names[MAX (base_num, index_num)]);
-	      break;
-	    }
-
-	  default:
-	    debug_rtx (x);
-	    abort ();
-	  }
-      }
-      break;
-
-    case PRE_DEC:
-      fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
-      break;
-
-    case POST_INC:
-      fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
-      break;
-
-    default:
-      output_addr_const (stream, x);
-      break;
-    }
-}
-
-/* Print operand x (an rtx) in assembler syntax to file stream
-   according to modifier code.
-
-   '.'  print a .s if insn needs delay slot
-   ','  print LOCAL_LABEL_PREFIX
-   '@'  print trap, rte or rts depending upon pragma interruptness
-   '#'  output a nop if there is nothing to put in the delay slot
-   'O'  print a constant without the #
-   'R'  print the LSW of a dp value - changes if in little endian
-   'S'  print the MSW of a dp value - changes if in little endian
-   'T'  print the next word of a dp value - same as 'R' in big endian mode.
-   'o'  output an operator.  */
-
-void
-print_operand (stream, x, code)
-     FILE *stream;
-     rtx x;
-     int code;
-{
-  switch (code)
-    {
-    case '.':
-      if (final_sequence
-	  && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
-	fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
-      break;
-    case ',':
-      fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
-      break;
-    case '@':
-      {
-	int interrupt_handler;
-
-	if ((lookup_attribute
-	     ("interrupt_handler",
-	      DECL_MACHINE_ATTRIBUTES (current_function_decl)))
-	    != NULL_TREE)
-	  interrupt_handler = 1;
-	else
-	  interrupt_handler = 0;
-	
-      if (trap_exit)
-	fprintf (stream, "trapa #%d", trap_exit);
-      else if (interrupt_handler)
-	fprintf (stream, "rte");
-      else
-	fprintf (stream, "rts");
-      break;
-      }
-    case '#':
-      /* Output a nop if there's nothing in the delay slot.  */
-      if (dbr_sequence_length () == 0)
-	fprintf (stream, "\n\tnop");
-      break;
-    case 'O':
-      output_addr_const (stream, x);
-      break;
-    case 'R':
-      fputs (reg_names[REGNO (x) + LSW], (stream));
-      break;
-    case 'S':
-      fputs (reg_names[REGNO (x) + MSW], (stream));
-      break;
-    case 'T':
-      /* Next word of a double.  */
-      switch (GET_CODE (x))
-	{
-	case REG:
-	  fputs (reg_names[REGNO (x) + 1], (stream));
-	  break;
-	case MEM:
-	  if (GET_CODE (XEXP (x, 0)) != PRE_DEC
-	      && GET_CODE (XEXP (x, 0)) != POST_INC)
-	    x = adj_offsettable_operand (x, 4);
-	  print_operand_address (stream, XEXP (x, 0));
-	  break;
-	}
-      break;
-    case 'o':
-      switch (GET_CODE (x))
-	{
-	case PLUS:  fputs ("add", stream); break;
-	case MINUS: fputs ("sub", stream); break;
-	case MULT:  fputs ("mul", stream); break;
-	case DIV:   fputs ("div", stream); break;
-	}
-      break;
-    default:
-      switch (GET_CODE (x))
-	{
-	case REG:
-	  if (REGNO (x) >= FIRST_FP_REG && REGNO (x) <= LAST_FP_REG
-	      && GET_MODE_SIZE (GET_MODE (x)) > 4)
-	    fprintf ((stream), "d%s", reg_names[REGNO (x)]+1);
-	  else
-	    fputs (reg_names[REGNO (x)], (stream));
-	  break;
-	case MEM:
-	  output_address (XEXP (x, 0));
-	  break;
-	default:
-	  fputc ('#', stream);
-	  output_addr_const (stream, x);
-	  break;
-	}
-      break;
-    }
-}
-
-/* Emit code to perform a block move.  Choose the best method.
-
-   OPERANDS[0] is the destination.
-   OPERANDS[1] is the source.
-   OPERANDS[2] is the size.
-   OPERANDS[3] is the alignment safe to use.  */
-
-int
-expand_block_move (operands)
-     rtx *operands;
-{
-  int align = INTVAL (operands[3]);
-  int constp = (GET_CODE (operands[2]) == CONST_INT);
-  int bytes = (constp ? INTVAL (operands[2]) : 0);
-
-  /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
-     alignment, or if it isn't a multiple of 4 bytes, then fail.  */
-  if (! constp || align < 4 || (bytes % 4 != 0))
-    return 0;
-
-  if (TARGET_HARD_SH4)
-    {
-      if (bytes < 12)
-	return 0;
-      else if (bytes == 12)
-	{
-	  tree entry_name;
-	  rtx func_addr_rtx;
-	  rtx r4 = gen_rtx (REG, SImode, 4);
-	  rtx r5 = gen_rtx (REG, SImode, 5);
-
-	  entry_name = get_identifier ("__movstrSI12_i4");
-
-	  func_addr_rtx
-	    = copy_to_mode_reg (Pmode,
-				gen_rtx_SYMBOL_REF (Pmode,
-						    IDENTIFIER_POINTER (entry_name)));
-	  emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
-	  emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
-	  emit_insn (gen_block_move_real_i4 (func_addr_rtx));
-	  return 1;
-	}
-      else if (! TARGET_SMALLCODE)
-	{
-	  tree entry_name;
-	  rtx func_addr_rtx;
-	  int dwords;
-	  rtx r4 = gen_rtx (REG, SImode, 4);
-	  rtx r5 = gen_rtx (REG, SImode, 5);
-	  rtx r6 = gen_rtx (REG, SImode, 6);
-
-	  entry_name = get_identifier (bytes & 4
-				       ? "__movstr_i4_odd"
-				       : "__movstr_i4_even");
-	  func_addr_rtx
-	    = copy_to_mode_reg (Pmode,
-				gen_rtx_SYMBOL_REF (Pmode,
-						    IDENTIFIER_POINTER (entry_name)));
-	  emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
-	  emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
-
-	  dwords = bytes >> 3;
-	  emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
-	  emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
-	  return 1;
-	}
-      else
-	return 0;
-    }
-  if (bytes < 64)
-    {
-      char entry[30];
-      tree entry_name;
-      rtx func_addr_rtx;
-      rtx r4 = gen_rtx (REG, SImode, 4);
-      rtx r5 = gen_rtx (REG, SImode, 5);
-
-      sprintf (entry, "__movstrSI%d", bytes);
-      entry_name = get_identifier (entry);
-
-      func_addr_rtx
-	= copy_to_mode_reg (Pmode,
-			    gen_rtx (SYMBOL_REF, Pmode,
-				     IDENTIFIER_POINTER (entry_name)));
-      emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
-      emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
-      emit_insn (gen_block_move_real (func_addr_rtx));
-      return 1;
-    }
-
-  /* This is the same number of bytes as a memcpy call, but to a different
-     less common function name, so this will occasionally use more space.  */
-  if (! TARGET_SMALLCODE)
-    {
-      tree entry_name;
-      rtx func_addr_rtx;
-      int final_switch, while_loop;
-      rtx r4 = gen_rtx (REG, SImode, 4);
-      rtx r5 = gen_rtx (REG, SImode, 5);
-      rtx r6 = gen_rtx (REG, SImode, 6);
-
-      entry_name = get_identifier ("__movstr");
-      func_addr_rtx
-	= copy_to_mode_reg (Pmode,
-			    gen_rtx (SYMBOL_REF, Pmode,
-				     IDENTIFIER_POINTER (entry_name)));
-      emit_insn (gen_move_insn (r4, XEXP (operands[0], 0)));
-      emit_insn (gen_move_insn (r5, XEXP (operands[1], 0)));
-
-      /* r6 controls the size of the move.  16 is decremented from it
-	 for each 64 bytes moved.  Then the negative bit left over is used
-	 as an index into a list of move instructions.  e.g., a 72 byte move
-	 would be set up with size(r6) = 14, for one iteration through the
-	 big while loop, and a switch of -2 for the last part.  */
-
-      final_switch = 16 - ((bytes / 4) % 16);
-      while_loop = ((bytes / 4) / 16 - 1) * 16;
-      emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
-      emit_insn (gen_block_lump_real (func_addr_rtx));
-      return 1;
-    }
-
-  return 0;
-}
-
-/* Prepare operands for a move define_expand; specifically, one of the
-   operands must be in a register.  */
-
-int
-prepare_move_operands (operands, mode)
-     rtx operands[];
-     enum machine_mode mode;
-{
-  if (! reload_in_progress && ! reload_completed)
-    {
-      /* Copy the source to a register if both operands aren't registers.  */
-      if (! register_operand (operands[0], mode)
-	  && ! register_operand (operands[1], mode))
-	operands[1] = copy_to_mode_reg (mode, operands[1]);
-
-      /* This case can happen while generating code to move the result
-	 of a library call to the target.  Reject `st r0,@(rX,rY)' because
-	 reload will fail to find a spill register for rX, since r0 is already
-	 being used for the source.  */
-      else if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 0
-	       && GET_CODE (operands[0]) == MEM
-	       && GET_CODE (XEXP (operands[0], 0)) == PLUS
-	       && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
-	operands[1] = copy_to_mode_reg (mode, operands[1]);
-    }
-
-  return 0;
-}
-
-/* Prepare the operands for an scc instruction; make sure that the
-   compare has been done.  */
-rtx
-prepare_scc_operands (code)
-     enum rtx_code code;
-{
-  rtx t_reg = gen_rtx (REG, SImode, T_REG);
-  enum rtx_code oldcode = code;
-  enum machine_mode mode;
-
-  /* First need a compare insn.  */
-  switch (code)
-    {
-    case NE:
-      /* It isn't possible to handle this case.  */
-      abort ();
-    case LT:
-      code = GT;
-      break;
-    case LE:
-      code = GE;
-      break;
-    case LTU:
-      code = GTU;
-      break;
-    case LEU:
-      code = GEU;
-      break;
-    }
-  if (code != oldcode)
-    {
-      rtx tmp = sh_compare_op0;
-      sh_compare_op0 = sh_compare_op1;
-      sh_compare_op1 = tmp;
-    }
-
-  mode = GET_MODE (sh_compare_op0);
-  if (mode == VOIDmode)
-    mode = GET_MODE (sh_compare_op1);
-
-  sh_compare_op0 = force_reg (mode, sh_compare_op0);
-  if ((code != EQ && code != NE
-       && (sh_compare_op1 != const0_rtx
-	   || code == GTU  || code == GEU || code == LTU || code == LEU))
-      || TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT)
-    sh_compare_op1 = force_reg (mode, sh_compare_op1);
-
-  if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
-    (mode == SFmode ? emit_sf_insn : emit_df_insn)
-     (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
-		gen_rtx (SET, VOIDmode, t_reg,
-			 gen_rtx (code, SImode,
-				  sh_compare_op0, sh_compare_op1)),
-		gen_rtx (USE, VOIDmode, get_fpscr_rtx ()))));
-  else
-    emit_insn (gen_rtx (SET, VOIDmode, t_reg,
-			gen_rtx (code, SImode, sh_compare_op0,
-				 sh_compare_op1)));
-
-  return t_reg;
-}
-
-/* Called from the md file, set up the operands of a compare instruction.  */
-
-void
-from_compare (operands, code)
-     rtx *operands;
-     int code;
-{
-  enum machine_mode mode = GET_MODE (sh_compare_op0);
-  rtx insn;
-  if (mode == VOIDmode)
-    mode = GET_MODE (sh_compare_op1);
-  if (code != EQ
-      || mode == DImode
-      || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
-    {
-      /* Force args into regs, since we can't use constants here.  */
-      sh_compare_op0 = force_reg (mode, sh_compare_op0);
-      if (sh_compare_op1 != const0_rtx
-	  || code == GTU  || code == GEU
-	  || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
-	sh_compare_op1 = force_reg (mode, sh_compare_op1);
-    }
-  if (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
-    {
-      from_compare (operands, GT);
-      insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
-    }
-  else
-    insn = gen_rtx (SET, VOIDmode,
-		    gen_rtx (REG, SImode, 18),
-		    gen_rtx (code, SImode, sh_compare_op0, sh_compare_op1));
-  if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
-    {
-      insn = gen_rtx (PARALLEL, VOIDmode,
-		      gen_rtvec (2, insn,
-				 gen_rtx (USE, VOIDmode, get_fpscr_rtx ())));
-      (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
-    }
-  else
-    emit_insn (insn);
-}
-
-/* Functions to output assembly code.  */
-
-/* Return a sequence of instructions to perform DI or DF move.
-
-   Since the SH cannot move a DI or DF in one instruction, we have
-   to take care when we see overlapping source and dest registers.  */
-
-char *
-output_movedouble (insn, operands, mode)
-     rtx insn;
-     rtx operands[];
-     enum machine_mode mode;
-{
-  rtx dst = operands[0];
-  rtx src = operands[1];
-
-  if (GET_CODE (dst) == MEM
-      && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
-    return "mov.l	%T1,%0\n\tmov.l	%1,%0";
-
-  if (register_operand (dst, mode)
-      && register_operand (src, mode))
-    {
-      if (REGNO (src) == MACH_REG)
-	return "sts	mach,%S0\n\tsts	macl,%R0";
-
-      /* When mov.d r1,r2 do r2->r3 then r1->r2;
-         when mov.d r1,r0 do r1->r0 then r2->r1.  */
-
-      if (REGNO (src) + 1 == REGNO (dst))
-	return "mov	%T1,%T0\n\tmov	%1,%0";
-      else
-	return "mov	%1,%0\n\tmov	%T1,%T0";
-    }
-  else if (GET_CODE (src) == CONST_INT)
-    {
-      if (INTVAL (src) < 0)
-	output_asm_insn ("mov	#-1,%S0", operands);
-      else
-	output_asm_insn ("mov	#0,%S0", operands);
-
-      return "mov	%1,%R0";
-    }
-  else if (GET_CODE (src) == MEM)
-    {
-      int ptrreg = -1;
-      int dreg = REGNO (dst);
-      rtx inside = XEXP (src, 0);
-
-      if (GET_CODE (inside) == REG)
-	ptrreg = REGNO (inside);
-      else if (GET_CODE (inside) == SUBREG)
-	ptrreg = REGNO (SUBREG_REG (inside)) + SUBREG_WORD (inside);
-      else if (GET_CODE (inside) == PLUS)
-	{
-	  ptrreg = REGNO (XEXP (inside, 0));
-	  /* ??? A r0+REG address shouldn't be possible here, because it isn't
-	     an offsettable address.  Unfortunately, offsettable addresses use
-	     QImode to check the offset, and a QImode offsettable address
-	     requires r0 for the other operand, which is not currently
-	     supported, so we can't use the 'o' constraint.
-	     Thus we must check for and handle r0+REG addresses here.
-	     We punt for now, since this is likely very rare.  */
-	  if (GET_CODE (XEXP (inside, 1)) == REG)
-	    abort ();
-	}
-      else if (GET_CODE (inside) == LABEL_REF)
-	return "mov.l	%1,%0\n\tmov.l	%1+4,%T0";
-      else if (GET_CODE (inside) == POST_INC)
-	return "mov.l	%1,%0\n\tmov.l	%1,%T0";
-      else
-	abort ();
-
-      /* Work out the safe way to copy.  Copy into the second half first.  */
-      if (dreg == ptrreg)
-	return "mov.l	%T1,%T0\n\tmov.l	%1,%0";
-    }
-
-  return "mov.l	%1,%0\n\tmov.l	%T1,%T0";
-}
-
-/* Print an instruction which would have gone into a delay slot after
-   another instruction, but couldn't because the other instruction expanded
-   into a sequence where putting the slot insn at the end wouldn't work.  */
-
-static void
-print_slot (insn)
-     rtx insn;
-{
-  final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
-
-  INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
-}
-
-char *
-output_far_jump (insn, op)
-     rtx insn;
-     rtx op;
-{
-  struct { rtx lab, reg, op; } this;
-  char *jump;
-  int far;
-  int offset = branch_dest (insn) - insn_addresses[INSN_UID (insn)];
-
-  this.lab = gen_label_rtx ();
-
-  if (TARGET_SH2
-      && offset >= -32764
-      && offset - get_attr_length (insn) <= 32766)
-    {
-      far = 0;
-      jump = "mov.w	%O0,%1;braf	%1";
-    }
-  else
-    {
-      far = 1;
-      jump = "mov.l	%O0,%1;jmp	@%1";
-    }
-  /* If we have a scratch register available, use it.  */
-  if (GET_CODE (PREV_INSN (insn)) == INSN
-      && INSN_CODE (PREV_INSN (insn)) == CODE_FOR_indirect_jump_scratch)
-    {
-      this.reg = SET_DEST (PATTERN (PREV_INSN (insn)));
-      output_asm_insn (jump, &this.lab);
-      if (dbr_sequence_length ())
-	print_slot (final_sequence);
-      else
-	output_asm_insn ("nop", 0);
-    }
-  else
-    {
-      /* Output the delay slot insn first if any.  */
-      if (dbr_sequence_length ())
-	print_slot (final_sequence);
-
-      this.reg = gen_rtx (REG, SImode, 13);
-      output_asm_insn ("mov.l	r13,@-r15", 0);
-      output_asm_insn (jump, &this.lab);
-      output_asm_insn ("mov.l	@r15+,r13", 0);
-    }
-  if (far)
-    output_asm_insn (".align	2", 0);
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
-  this.op = op;
-  output_asm_insn (far ? ".long	%O2" : ".word %O2-%O0", &this.lab);
-  return "";
-}
-
-/* Local label counter, used for constants in the pool and inside
-   pattern branches.  */
-
-static int lf = 100;
-
-/* Output code for ordinary branches.  */
-
-char *
-output_branch (logic, insn, operands)
-     int logic;
-     rtx insn;
-     rtx *operands;
-{
-  switch (get_attr_length (insn))
-    {
-    case 6:
-      /* This can happen if filling the delay slot has caused a forward
-	 branch to exceed its range (we could reverse it, but only
-	 when we know we won't overextend other branches; this should
-	 best be handled by relaxation).
-	 It can also happen when other condbranches hoist delay slot insn
-	 from their destination, thus leading to code size increase.
-	 But the branch will still be in the range -4092..+4098 bytes.  */
-
-      if (! TARGET_RELAX)
-	{
-	  int label = lf++;
-	  /* The call to print_slot will clobber the operands.  */
-	  rtx op0 = operands[0];
-    
-	  /* If the instruction in the delay slot is annulled (true), then
-	     there is no delay slot where we can put it now.  The only safe
-	     place for it is after the label.  final will do that by default.  */
-    
-	  if (final_sequence
-	      && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
-	    {
-	      asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
-	                   ASSEMBLER_DIALECT ? "/" : ".", label);
-	      print_slot (final_sequence);
-	    }
-	  else
-	    asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
-    
-	  output_asm_insn ("bra\t%l0", &op0);
-	  fprintf (asm_out_file, "\tnop\n");
-	  ASM_OUTPUT_INTERNAL_LABEL(asm_out_file, "LF", label);
-    
-	  return "";
-	}
-      /* When relaxing, handle this like a short branch.  The linker
-	 will fix it up if it still doesn't fit after relaxation.  */
-    case 2:
-      return logic ? "bt%.\t%l0" : "bf%.\t%l0";
-    default:
-      abort ();
-    }
-}
-
-char *
-output_branchy_insn (code, template, insn, operands)
-     char *template;
-     enum rtx_code code;
-     rtx insn;
-     rtx *operands;
-{
-  rtx next_insn = NEXT_INSN (insn);
-  int label_nr;
-
-  if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
-    {
-      rtx src = SET_SRC (PATTERN (next_insn));
-      if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
-	{
-	  /* Following branch not taken */
-	  operands[9] = gen_label_rtx ();
-	  emit_label_after (operands[9], next_insn);
-	  return template;
-	}
-      else
-	{
-	  int offset = (branch_dest (next_insn)
-			- insn_addresses[INSN_UID (next_insn)] + 4);
-	  if (offset >= -252 && offset <= 258)
-	    {
-	      if (GET_CODE (src) == IF_THEN_ELSE)
-		/* branch_true */
-		src = XEXP (src, 1);
-	      operands[9] = src;
-	      return template;
-	    }
-	}
-    }
-  operands[9] = gen_label_rtx ();
-  emit_label_after (operands[9], insn);
-  return template;
-}
-
-char *
-output_ieee_ccmpeq (insn, operands)
-     rtx insn, operands;
-{
-  output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
-}
-
-/* Output to FILE the start of the assembler file.  */
-
-void
-output_file_start (file)
-     FILE *file;
-{
-  register int pos;
-
-  output_file_directive (file, main_input_filename);
-
-  /* Switch to the data section so that the coffsem symbol and the
-     gcc2_compiled. symbol aren't in the text section.  */
-  data_section ();
-
-  if (TARGET_LITTLE_ENDIAN)
-    fprintf (file, "\t.little\n");
-}
-
-/* Actual number of instructions used to make a shift by N.  */
-static char ashiftrt_insns[] =
-  { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
-
-/* Left shift and logical right shift are the same.  */
-static char shift_insns[]    =
-  { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
-
-/* Individual shift amounts needed to get the above length sequences.
-   One bit right shifts clobber the T bit, so when possible, put one bit
-   shifts in the middle of the sequence, so the ends are eligible for
-   branch delay slots.  */
-static short shift_amounts[32][5] = {
-  {0}, {1}, {2}, {2, 1},
-  {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
-  {8}, {8, 1}, {8, 2}, {8, 1, 2},
-  {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
-  {16}, {16, 1}, {16, 2}, {16, 1, 2},
-  {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
-  {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
-  {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
-
-/* Likewise, but for shift amounts < 16, up to three highmost bits
-   might be clobbered.  This is typically used when combined with some
-   kind of sign or zero extension.  */
-   
-static char ext_shift_insns[]    =
-  { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
-
-static short ext_shift_amounts[32][4] = {
-  {0}, {1}, {2}, {2, 1},
-  {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
-  {8}, {8, 1}, {8, 2}, {8, 1, 2},
-  {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
-  {16}, {16, 1}, {16, 2}, {16, 1, 2},
-  {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
-  {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
-  {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
-
-/* Assuming we have a value that has been sign-extended by at least one bit,
-   can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
-   to shift it by N without data loss, and quicker than by other means?  */
-#define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
-
-/* This is used in length attributes in sh.md to help compute the length
-   of arbitrary constant shift instructions.  */
-
-int
-shift_insns_rtx (insn)
-     rtx insn;
-{
-  rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
-  int shift_count = INTVAL (XEXP (set_src, 1));
-  enum rtx_code shift_code = GET_CODE (set_src);
-
-  switch (shift_code)
-    {
-    case ASHIFTRT:
-      return ashiftrt_insns[shift_count];
-    case LSHIFTRT:
-    case ASHIFT:
-      return shift_insns[shift_count];
-    default:
-      abort();
-    }
-}
-
-/* Return the cost of a shift.  */
-
-int
-shiftcosts (x)
-     rtx x;
-{
-  int value = INTVAL (XEXP (x, 1));
-
-  /* If shift by a non constant, then this will be expensive.  */
-  if (GET_CODE (XEXP (x, 1)) != CONST_INT)
-    return SH_DYNAMIC_SHIFT_COST;
-
-  /* Otherwise, return the true cost in instructions.  */
-  if (GET_CODE (x) == ASHIFTRT)
-    {
-      int cost = ashiftrt_insns[value];
-      /* If SH3, then we put the constant in a reg and use shad.  */
-      if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
-	cost = 1 + SH_DYNAMIC_SHIFT_COST;
-      return cost;
-    }
-  else
-    return shift_insns[value];
-}
-
-/* Return the cost of an AND operation.  */
-
-int
-andcosts (x)
-     rtx x;
-{
-  int i;
-
-  /* Anding with a register is a single cycle and instruction.  */
-  if (GET_CODE (XEXP (x, 1)) != CONST_INT)
-    return 1;
-
-  i = INTVAL (XEXP (x, 1));
-  /* These constants are single cycle extu.[bw] instructions.  */
-  if (i == 0xff || i == 0xffff)
-    return 1;
-  /* Constants that can be used in an and immediate instruction is a single
-     cycle, but this requires r0, so make it a little more expensive.  */
-  if (CONST_OK_FOR_L (i))
-    return 2;
-  /* Constants that can be loaded with a mov immediate and an and.
-     This case is probably unnecessary.  */
-  if (CONST_OK_FOR_I (i))
-    return 2;
-  /* Any other constants requires a 2 cycle pc-relative load plus an and.
-     This case is probably unnecessary.  */
-  return 3;
-}
-
-/* Return the cost of a multiply.  */
-int
-multcosts (x)
-     rtx x;
-{
-  if (TARGET_SH2)
-    {
-      /* We have a mul insn, so we can never take more than the mul and the
-	 read of the mac reg, but count more because of the latency and extra
-	 reg usage.  */
-      if (TARGET_SMALLCODE)
-	return 2;
-      return 3;
-    }
-
-  /* If we're aiming at small code, then just count the number of
-     insns in a multiply call sequence.  */
-  if (TARGET_SMALLCODE)
-    return 5;
-
-  /* Otherwise count all the insns in the routine we'd be calling too.  */
-  return 20;
-}
-
-/* Code to expand a shift.  */
-
-void
-gen_ashift (type, n, reg)
-     int type;
-     int n;
-     rtx reg;
-{
-  /* Negative values here come from the shift_amounts array.  */
-  if (n < 0)
-    {
-      if (type == ASHIFT)
-	type = LSHIFTRT;
-      else
-	type = ASHIFT;
-      n = -n;
-    }
-
-  switch (type)
-    {
-    case ASHIFTRT:
-      emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
-      break;
-    case LSHIFTRT:
-      if (n == 1)
-	emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
-      else
-	emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
-      break;
-    case ASHIFT:
-      emit_insn (gen_ashlsi3_k (reg, reg, GEN_INT (n)));
-      break;
-    }
-}
-
-/* Same for HImode */
-
-void
-gen_ashift_hi (type, n, reg)
-     int type;
-     int n;
-     rtx reg;
-{
-  /* Negative values here come from the shift_amounts array.  */
-  if (n < 0)
-    {
-      if (type == ASHIFT)
-	type = LSHIFTRT;
-      else
-	type = ASHIFT;
-      n = -n;
-    }
-
-  switch (type)
-    {
-    case ASHIFTRT:
-    case LSHIFTRT:
-      /* We don't have HImode right shift operations because using the
-	 ordinary 32 bit shift instructions for that doesn't generate proper
-	 zero/sign extension.
-	 gen_ashift_hi is only called in contexts where we know that the
-	 sign extension works out correctly.  */
-      {
-	int word = 0;
-	if (GET_CODE (reg) == SUBREG)
-	  {
-	    word = SUBREG_WORD (reg);
-	    reg = SUBREG_REG (reg);
-	  }
-	gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, word));
-	break;
-      }
-    case ASHIFT:
-      emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
-      break;
-    }
-}
-
-/* Output RTL to split a constant shift into its component SH constant
-   shift instructions.  */
-   
-int
-gen_shifty_op (code, operands)
-     int code;
-     rtx *operands;
-{
-  int value = INTVAL (operands[2]);
-  int max, i;
-
-  /* Truncate the shift count in case it is out of bounds.  */
-  value = value & 0x1f;
- 
-  if (value == 31)
-    {
-      if (code == LSHIFTRT)
-	{
-	  emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
-	  emit_insn (gen_movt (operands[0]));
-	  return;
-	}
-      else if (code == ASHIFT)
-	{
-	  /* There is a two instruction sequence for 31 bit left shifts,
-	     but it requires r0.  */
-	  if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
-	    {
-	      emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
-	      emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
-	      return;
-	    }
-	}
-    }
-  else if (value == 0)
-    {
-      /* This can happen when not optimizing.  We must output something here
-	 to prevent the compiler from aborting in final.c after the try_split
-	 call.  */
-      emit_insn (gen_nop ());
-      return;
-    }
-
-  max = shift_insns[value];
-  for (i = 0; i < max; i++)
-    gen_ashift (code, shift_amounts[value][i], operands[0]);
-}
-   
-/* Same as above, but optimized for values where the topmost bits don't
-   matter.  */
-
-int
-gen_shifty_hi_op (code, operands)
-     int code;
-     rtx *operands;
-{
-  int value = INTVAL (operands[2]);
-  int max, i;
-  void (*gen_fun)();
-
-  /* This operation is used by and_shl for SImode values with a few
-     high bits known to be cleared.  */
-  value &= 31;
-  if (value == 0)
-    {
-      emit_insn (gen_nop ());
-      return;
-    }
-
-  gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
-  if (code == ASHIFT)
-    {
-      max = ext_shift_insns[value];
-      for (i = 0; i < max; i++)
-	gen_fun (code, ext_shift_amounts[value][i], operands[0]);
-    }
-  else
-    /* When shifting right, emit the shifts in reverse order, so that
-       solitary negative values come first.  */
-    for (i = ext_shift_insns[value] - 1; i >= 0; i--)
-      gen_fun (code, ext_shift_amounts[value][i], operands[0]);
-}
-
-/* Output RTL for an arithmetic right shift.  */
-
-/* ??? Rewrite to use super-optimizer sequences.  */
-
-int
-expand_ashiftrt (operands)
-     rtx *operands;
-{
-  rtx wrk;
-  char func[18];
-  tree func_name;
-  int value;
-
-  if (TARGET_SH3)
-    {
-      if (GET_CODE (operands[2]) != CONST_INT)
-	{
-	  rtx count = copy_to_mode_reg (SImode, operands[2]);
-	  emit_insn (gen_negsi2 (count, count));
-	  emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
-	  return 1;
-	}
-      else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
-	       > 1 + SH_DYNAMIC_SHIFT_COST)
-	{
-	  rtx count
-	    = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
-	  emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
-	  return 1;
-	}
-    }
-  if (GET_CODE (operands[2]) != CONST_INT)
-    return 0;
-
-  value = INTVAL (operands[2]) & 31;
-
-  if (value == 31)
-    {
-      emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
-      return 1;
-    }
-  else if (value >= 16 && value <= 19)
-    {
-      wrk = gen_reg_rtx (SImode);
-      emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
-      value -= 16;
-      while (value--)
-	gen_ashift (ASHIFTRT, 1, wrk);
-      emit_move_insn (operands[0], wrk);
-      return 1;
-    }
-  /* Expand a short sequence inline, longer call a magic routine.  */
-  else if (value <= 5)
-    {
-      wrk = gen_reg_rtx (SImode);
-      emit_move_insn (wrk, operands[1]);
-      while (value--)
-	gen_ashift (ASHIFTRT, 1, wrk);
-      emit_move_insn (operands[0], wrk);
-      return 1;
-    }
-
-  wrk = gen_reg_rtx (Pmode);
-
-  /* Load the value into an arg reg and call a helper.  */
-  emit_move_insn (gen_rtx (REG, SImode, 4), operands[1]);
-  sprintf (func, "__ashiftrt_r4_%d", value);
-  func_name = get_identifier (func);
-  emit_move_insn (wrk, gen_rtx (SYMBOL_REF, Pmode,
-				IDENTIFIER_POINTER (func_name)));
-  emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
-  emit_move_insn (operands[0], gen_rtx (REG, SImode, 4));
-  return 1;
-}
-
-int sh_dynamicalize_shift_p (count)
-     rtx count;
-{
-  return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
-}
-
-/* Try to find a good way to implement the combiner pattern
-  [(set (match_operand:SI 0 "register_operand" "r")
-        (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-                           (match_operand:SI 2 "const_int_operand" "n"))
-                (match_operand:SI 3 "const_int_operand" "n"))) .
-  LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
-  return 0 for simple right / left or left/right shift combination.
-  return 1 for a combination of shifts with zero_extend.
-  return 2 for a combination of shifts with an AND that needs r0.
-  return 3 for a combination of shifts with an AND that needs an extra
-    scratch register, when the three highmost bits of the AND mask are clear.
-  return 4 for a combination of shifts with an AND that needs an extra
-    scratch register, when any of the three highmost bits of the AND mask
-    is set.
-  If ATTRP is set, store an initial right shift width in ATTRP[0],
-  and the instruction length in ATTRP[1] .  These values are not valid
-  when returning 0.
-  When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
-  shift_amounts for the last shift value that is to be used before the
-  sign extend.  */
-int
-shl_and_kind (left_rtx, mask_rtx, attrp)
-     rtx left_rtx, mask_rtx;
-     int *attrp;
-{
-  unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
-  int left = INTVAL (left_rtx), right;
-  int best = 0;
-  int cost, best_cost = 10000;
-  int best_right = 0, best_len = 0;
-  int i;
-  int can_ext;
-
-  if (left < 0 || left > 31)
-    return 0;
-  if (GET_CODE (mask_rtx) == CONST_INT)
-    mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
-  else
-    mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
-  /* Can this be expressed as a right shift / left shift pair ? */
-  lsb = ((mask ^ (mask - 1)) >> 1) + 1;
-  right = exact_log2 (lsb);
-  mask2 = ~(mask + lsb - 1);
-  lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
-  /* mask has no zeroes but trailing zeroes <==> ! mask2 */
-  if (! mask2)
-    best_cost = shift_insns[right] + shift_insns[right + left];
-  /* mask has no trailing zeroes <==> ! right */
-  else if (! right && mask2 == ~(lsb2 - 1))
-    {
-      int late_right = exact_log2 (lsb2);
-      best_cost = shift_insns[left + late_right] + shift_insns[late_right];
-    }
-  /* Try to use zero extend */
-  if (mask2 == ~(lsb2 - 1))
-    {
-      int width, first;
-
-      for (width = 8; width <= 16; width += 8)
-	{
-	  /* Can we zero-extend right away? */
-	  if (lsb2 == (HOST_WIDE_INT)1 << width)
-	    {
-	      cost
-		= 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
-	      if (cost < best_cost)
-		{
-		  best = 1;
-		  best_cost = cost;
-		  best_right = right;
-		  best_len = cost;
-		  if (attrp)
-		    attrp[2] = -1;
-		}
-	      continue;
-	    }
-	  /* ??? Could try to put zero extend into initial right shift,
-	     or even shift a bit left before the right shift. */
-	  /* Determine value of first part of left shift, to get to the
-	     zero extend cut-off point.  */
-	  first = width - exact_log2 (lsb2) + right;
-	  if (first >= 0 && right + left - first >= 0)
-	    {
-	      cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
-		+ ext_shift_insns[right + left - first];
-	      if (cost < best_cost)
-		{
-		  best = 1;
-		  best_cost = cost;
-		  best_right = right;
-		  best_len = cost;
-		  if (attrp)
-		    attrp[2] = first;
-		  }
-	    }
-	}
-    }
-  /* Try to use r0 AND pattern */
-  for (i = 0; i <= 2; i++)
-    {
-      if (i > right)
-	break;
-      if (! CONST_OK_FOR_L (mask >> i))
-	continue;
-      cost = (i != 0) + 2 + ext_shift_insns[left + i];
-      if (cost < best_cost)
-	{
-	  best = 2;
-	  best_cost = cost;
-	  best_right = i;
-	  best_len = cost - 1;
-	}
-    }
-  /* Try to use a scratch register to hold the AND operand.  */
-  can_ext = ((mask << left) & 0xe0000000) == 0;
-  for (i = 0; i <= 2; i++)
-    {
-      if (i > right)
-	break;
-      cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3)
-	+ (can_ext ? ext_shift_insns : shift_insns)[left + i];
-      if (cost < best_cost)
-	{
-	  best = 4 - can_ext;
-	  best_cost = cost;
-	  best_right = i;
-	  best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i);
-	}
-    }
-
-  if (attrp)
-    {
-      attrp[0] = best_right;
-      attrp[1] = best_len;
-    }
-  return best;
-}
-
-/* This is used in length attributes of the unnamed instructions
-   corresponding to shl_and_kind return values of 1 and 2.  */
-int
-shl_and_length (insn)
-     rtx insn;
-{
-  rtx set_src, left_rtx, mask_rtx;
-  int attributes[3];
-
-  set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
-  left_rtx = XEXP (XEXP (set_src, 0), 1);
-  mask_rtx = XEXP (set_src, 1);
-  shl_and_kind (left_rtx, mask_rtx, attributes);
-  return attributes[1];
-}
-
-/* This is used in length attribute of the and_shl_scratch instruction.  */
-
-int
-shl_and_scr_length (insn)
-     rtx insn;
-{
-  rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
-  int len = shift_insns[INTVAL (XEXP (set_src, 1))];
-  rtx op = XEXP (set_src, 0);
-  len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
-  op = XEXP (XEXP (op, 0), 0);
-  return len + shift_insns[INTVAL (XEXP (op, 1))];
-}
-
-/* Generating rtl? */
-extern int rtx_equal_function_value_matters;
-
-/* Generate rtl for instructions for which shl_and_kind advised a particular
-   method of generating them, i.e. returned zero.  */
-
-int
-gen_shl_and (dest, left_rtx, mask_rtx, source)
-     rtx dest, left_rtx, mask_rtx, source;
-{
-  int attributes[3];
-  unsigned HOST_WIDE_INT mask;
-  int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
-  int right, total_shift;
-  int (*shift_gen_fun) PROTO((int, rtx*)) = gen_shifty_hi_op;
-
-  right = attributes[0];
-  total_shift = INTVAL (left_rtx) + right;
-  mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
-  switch (kind)
-    {
-    default:
-      return -1;
-    case 1:
-      {
-	int first = attributes[2];
-	rtx operands[3];
-
-	if (first < 0)
-	  {
-	    emit_insn ((mask << right) <= 0xff
-		       ? gen_zero_extendqisi2(dest,
-					      gen_lowpart (QImode, source))
-		       : gen_zero_extendhisi2(dest,
-					      gen_lowpart (HImode, source)));
-	    source = dest;
-	  }
-	if (source != dest)
-	  emit_insn (gen_movsi (dest, source));
-	operands[0] = dest;
-	if (right)
-	  {
-	    operands[2] = GEN_INT (right);
-	    gen_shifty_hi_op (LSHIFTRT, operands);
-	  }
-	if (first > 0)
-	  {
-	    operands[2] = GEN_INT (first);
-	    gen_shifty_hi_op (ASHIFT, operands);
-	    total_shift -= first;
-	    mask <<= first;
-	  }
-	if (first >= 0)
-	  emit_insn (mask <= 0xff
-		     ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
-		     : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
-	if (total_shift > 0)
-	  {
-	    operands[2] = GEN_INT (total_shift);
-	    gen_shifty_hi_op (ASHIFT, operands);
-	  }
-	break;
-      }
-    case 4:
-      shift_gen_fun = gen_shifty_op;
-    case 3:
-      /* If the topmost bit that matters is set, set the topmost bits
-	 that don't matter.  This way, we might be able to get a shorter
-	 signed constant.  */
-      if (mask & ((HOST_WIDE_INT)1 << 31 - total_shift))
-	mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
-    case 2:
-      /* Don't expand fine-grained when combining, because that will
-         make the pattern fail.  */
-      if (rtx_equal_function_value_matters
-	  || reload_in_progress || reload_completed)
-	{
-	  rtx operands[3];
-  
-	  /* Cases 3 and 4 should be handled by this split
-	     only while combining  */
-	  if (kind > 2)
-	    abort ();
-	  if (right)
-	    {
-	      emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
-	      source = dest;
-	    }
-	  emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
-	  if (total_shift)
-	    {
-	      operands[0] = dest;
-	      operands[1] = dest;
-	      operands[2] = GEN_INT (total_shift);
-	      shift_gen_fun (ASHIFT, operands);
-	    }
-	  break;
-	}
-      else
-	{
-	  int neg = 0;
-	  if (kind != 4 && total_shift < 16)
-	    {
-	      neg = -ext_shift_amounts[total_shift][1];
-	      if (neg > 0)
-		neg -= ext_shift_amounts[total_shift][2];
-	      else
-		neg = 0;
-	    }
-	  emit_insn (gen_and_shl_scratch (dest, source,
-					  GEN_INT (right),
-					  GEN_INT (mask),
-					  GEN_INT (total_shift + neg),
-					  GEN_INT (neg)));
-	  emit_insn (gen_movsi (dest, dest));
-	  break;
-	}
-    }
-  return 0;
-}
-
-/* Try to find a good way to implement the combiner pattern
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-                                    (match_operand:SI 2 "const_int_operand" "n")
-                         (match_operand:SI 3 "const_int_operand" "n")
-                         (const_int 0)))
-   (clobber (reg:SI 18))]
-  LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
-  return 0 for simple left / right shift combination.
-  return 1 for left shift / 8 bit sign extend / left shift.
-  return 2 for left shift / 16 bit sign extend / left shift.
-  return 3 for left shift / 8 bit sign extend / shift / sign extend.
-  return 4 for left shift / 16 bit sign extend / shift / sign extend.
-  return 5 for left shift / 16 bit sign extend / right shift
-  return 6 for < 8 bit sign extend / left shift.
-  return 7 for < 8 bit sign extend / left shift / single right shift.
-  If COSTP is nonzero, assign the calculated cost to *COSTP.  */
-
-int
-shl_sext_kind (left_rtx, size_rtx, costp)
-     rtx left_rtx, size_rtx;
-     int *costp;
-{
-  int left, size, insize, ext;
-  int cost, best_cost;
-  int kind;
-
-  left = INTVAL (left_rtx);
-  size = INTVAL (size_rtx);
-  insize = size - left;
-  if (insize <= 0)
-    abort ();
-  /* Default to left / right shift.  */
-  kind = 0;
-  best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
-  if (size <= 16)
-    {
-      /* 16 bit shift / sign extend / 16 bit shift */
-      cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
-      /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
-	 below, by alternative 3 or something even better.  */
-      if (cost < best_cost)
-	{
-	  kind = 5;
-	  best_cost = cost;
-	}
-    }
-  /* Try a plain sign extend between two shifts.  */
-  for (ext = 16; ext >= insize; ext -= 8)
-    {
-      if (ext <= size)
-	{
-	  cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
-	  if (cost < best_cost)
-	    {
-	      kind = ext / 8U;
-	      best_cost = cost;
-	    }
-	}
-      /* Check if we can do a sloppy shift with a final signed shift
-	 restoring the sign.  */
-      if (EXT_SHIFT_SIGNED (size - ext))
-	cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
-      /* If not, maybe it's still cheaper to do the second shift sloppy,
-	 and do a final sign extend?  */
-      else if (size <= 16)
-	cost = ext_shift_insns[ext - insize] + 1
-	  + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
-      else
-	continue;
-      if (cost < best_cost)
-	{
-	  kind = ext / 8U + 2;
-	  best_cost = cost;
-	}
-    }
-  /* Check if we can sign extend in r0 */
-  if (insize < 8)
-    {
-      cost = 3 + shift_insns[left];
-      if (cost < best_cost)
-	{
-	  kind = 6;
-	  best_cost = cost;
-	}
-      /* Try the same with a final signed shift.  */
-      if (left < 31)
-	{
-	  cost = 3 + ext_shift_insns[left + 1] + 1;
-	  if (cost < best_cost)
-	    {
-	      kind = 7;
-	      best_cost = cost;
-	    }
-	}
-    }
-  if (TARGET_SH3)
-    {
-      /* Try to use a dynamic shift.  */
-      cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
-      if (cost < best_cost)
-	{
-	  kind = 0;
-	  best_cost = cost;
-	}
-    }
-  if (costp)
-    *costp = cost;
-  return kind;
-}
-
-/* Function to be used in the length attribute of the instructions
-   implementing this pattern.  */
-
-int
-shl_sext_length (insn)
-     rtx insn;
-{
-  rtx set_src, left_rtx, size_rtx;
-  int cost;
-
-  set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
-  left_rtx = XEXP (XEXP (set_src, 0), 1);
-  size_rtx = XEXP (set_src, 1);
-  shl_sext_kind (left_rtx, size_rtx, &cost);
-  return cost;
-}
-
-/* Generate rtl for this pattern */
-
-int
-gen_shl_sext (dest, left_rtx, size_rtx, source)
-     rtx dest, left_rtx, size_rtx, source;
-{
-  int kind;
-  int left, size, insize, cost;
-  rtx operands[3];
-
-  kind = shl_sext_kind (left_rtx, size_rtx, &cost);
-  left = INTVAL (left_rtx);
-  size = INTVAL (size_rtx);
-  insize = size - left;
-  switch (kind)
-    {
-    case 1:
-    case 2:
-    case 3:
-    case 4:
-      {
-	int ext = kind & 1 ? 8 : 16;
-	int shift2 = size - ext;
-
-	/* Don't expand fine-grained when combining, because that will
-	   make the pattern fail.  */
-	if (! rtx_equal_function_value_matters
-	    && ! reload_in_progress && ! reload_completed)
-	  {
-	    emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
-	    emit_insn (gen_movsi (dest, source));
-	    break;
-	  }
-	if (dest != source)
-	  emit_insn (gen_movsi (dest, source));
-	operands[0] = dest;
-	if (ext - insize)
-	  {
-	    operands[2] = GEN_INT (ext - insize);
-	    gen_shifty_hi_op (ASHIFT, operands);
-	  }
-	emit_insn (kind & 1
-		   ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
-		   : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
-	if (kind <= 2)
-	  {
-	    if (shift2)
-	      {
-		operands[2] = GEN_INT (shift2);
-		gen_shifty_op (ASHIFT, operands);
-	      }
-	  }
-	else
-	  {
-	    if (shift2 > 0)
-	      {
-		if (EXT_SHIFT_SIGNED (shift2))
-		  {
-		    operands[2] = GEN_INT (shift2 + 1);
-		    gen_shifty_op (ASHIFT, operands);
-		    operands[2] = GEN_INT (1);
-		    gen_shifty_op (ASHIFTRT, operands);
-		    break;
-		  }
-		operands[2] = GEN_INT (shift2);
-		gen_shifty_hi_op (ASHIFT, operands);
-	      }
-	    else if (shift2)
-	      {
-		operands[2] = GEN_INT (-shift2);
-		gen_shifty_hi_op (LSHIFTRT, operands);
-	      }
-	    emit_insn (size <= 8
-		       ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
-		       : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
-	  }
-	break;
-      }
-    case 5:
-      {
-	int i = 16 - size;
-	if (! rtx_equal_function_value_matters
-	    && ! reload_in_progress && ! reload_completed)
-	  emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
-	else
-	  {
-	    operands[0] = dest;
-	    operands[2] = GEN_INT (16 - insize);
-	    gen_shifty_hi_op (ASHIFT, operands);
-	    emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
-	  }
-	/* Don't use gen_ashrsi3 because it generates new pseudos.  */
-	while (--i >= 0)
-	  gen_ashift (ASHIFTRT, 1, dest);
-	break;
-      }
-    case 6:
-    case 7:
-      /* Don't expand fine-grained when combining, because that will
-	 make the pattern fail.  */
-      if (! rtx_equal_function_value_matters
-	  && ! reload_in_progress && ! reload_completed)
-	{
-	  emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
-	  emit_insn (gen_movsi (dest, source));
-	  break;
-	}
-      emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
-      emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
-      emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
-      operands[0] = dest;
-      operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
-      gen_shifty_op (ASHIFT, operands);
-      if (kind == 7)
-	emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
-      break;
-    default:
-      return -1;
-    }
-  return 0;
-}
-
-/* The SH cannot load a large constant into a register, constants have to
-   come from a pc relative load.  The reference of a pc relative load
-   instruction must be less than 1k infront of the instruction.  This
-   means that we often have to dump a constant inside a function, and
-   generate code to branch around it.
-
-   It is important to minimize this, since the branches will slow things
-   down and make things bigger.
-
-   Worst case code looks like:
-
-   mov.l L1,rn
-   bra   L2
-   nop
-   align
-   L1:   .long value
-   L2:
-   ..
-
-   mov.l L3,rn
-   bra   L4
-   nop
-   align
-   L3:   .long value
-   L4:
-   ..
-
-   We fix this by performing a scan before scheduling, which notices which
-   instructions need to have their operands fetched from the constant table
-   and builds the table.
-
-   The algorithm is:
-
-   scan, find an instruction which needs a pcrel move.  Look forward, find the
-   last barrier which is within MAX_COUNT bytes of the requirement.
-   If there isn't one, make one.  Process all the instructions between
-   the find and the barrier.
-
-   In the above example, we can tell that L3 is within 1k of L1, so
-   the first move can be shrunk from the 3 insn+constant sequence into
-   just 1 insn, and the constant moved to L3 to make:
-
-   mov.l        L1,rn
-   ..
-   mov.l        L3,rn
-   bra          L4
-   nop
-   align
-   L3:.long value
-   L4:.long value
-
-   Then the second move becomes the target for the shortening process.  */
-
-typedef struct
-{
-  rtx value;			/* Value in table.  */
-  rtx label;			/* Label of value.  */
-  enum machine_mode mode;	/* Mode of value.  */
-} pool_node;
-
-/* The maximum number of constants that can fit into one pool, since
-   the pc relative range is 0...1020 bytes and constants are at least 4
-   bytes long.  */
-
-#define MAX_POOL_SIZE (1020/4)
-static pool_node pool_vector[MAX_POOL_SIZE];
-static int pool_size;
-
-/* ??? If we need a constant in HImode which is the truncated value of a
-   constant we need in SImode, we could combine the two entries thus saving
-   two bytes.  Is this common enough to be worth the effort of implementing
-   it?  */
-
-/* ??? This stuff should be done at the same time that we shorten branches.
-   As it is now, we must assume that all branches are the maximum size, and
-   this causes us to almost always output constant pools sooner than
-   necessary.  */
-
-/* Add a constant to the pool and return its label.  */
-
-static rtx
-add_constant (x, mode, last_value)
-     rtx last_value;
-     rtx x;
-     enum machine_mode mode;
-{
-  int i;
-  rtx lab;
-
-  /* First see if we've already got it.  */
-  for (i = 0; i < pool_size; i++)
-    {
-      if (x->code == pool_vector[i].value->code
-	  && mode == pool_vector[i].mode)
-	{
-	  if (x->code == CODE_LABEL)
-	    {
-	      if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
-		continue;
-	    }
-	  if (rtx_equal_p (x, pool_vector[i].value))
-	    {
-	      lab = 0;
-	      if (! last_value
-		  || ! i
-		  || ! rtx_equal_p (last_value, pool_vector[i-1].value))
-		{
-		  lab = pool_vector[i].label;
-		  if (! lab)
-		    pool_vector[i].label = lab = gen_label_rtx ();
-		}
-	      return lab;
-	    }
-	}
-    }
-
-  /* Need a new one.  */
-  pool_vector[pool_size].value = x;
-  if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
-    lab = 0;
-  else
-    lab = gen_label_rtx ();
-  pool_vector[pool_size].mode = mode;
-  pool_vector[pool_size].label = lab;
-  pool_size++;
-  return lab;
-}
-
-/* Output the literal table.  */
-
-static void
-dump_table (scan)
-     rtx scan;
-{
-  int i;
-  int need_align = 1;
-
-  /* Do two passes, first time dump out the HI sized constants.  */
-
-  for (i = 0; i < pool_size; i++)
-    {
-      pool_node *p = &pool_vector[i];
-
-      if (p->mode == HImode)
-	{
-	  if (need_align)
-	    {
-	      scan = emit_insn_after (gen_align_2 (), scan);
-	      need_align = 0;
-	    }
-	  scan = emit_label_after (p->label, scan);
-	  scan = emit_insn_after (gen_consttable_2 (p->value), scan);
-	}
-    }
-
-  need_align = 1;
-
-  for (i = 0; i < pool_size; i++)
-    {
-      pool_node *p = &pool_vector[i];
-
-      switch (p->mode)
-	{
-	case HImode:
-	  break;
-	case SImode:
-	case SFmode:
-	  if (need_align)
-	    {
-	      need_align = 0;
-	      scan = emit_label_after (gen_label_rtx (), scan);
-	      scan = emit_insn_after (gen_align_4 (), scan);
-	    }
-	  if (p->label)
-	    scan = emit_label_after (p->label, scan);
-	  scan = emit_insn_after (gen_consttable_4 (p->value), scan);
-	  break;
-	case DFmode:
-	case DImode:
-	  if (need_align)
-	    {
-	      need_align = 0;
-	      scan = emit_label_after (gen_label_rtx (), scan);
-	      scan = emit_insn_after (gen_align_4 (), scan);
-	    }
-	  if (p->label)
-	    scan = emit_label_after (p->label, scan);
-	  scan = emit_insn_after (gen_consttable_8 (p->value), scan);
-	  break;
-	default:
-	  abort ();
-	  break;
-	}
-    }
-
-  scan = emit_insn_after (gen_consttable_end (), scan);
-  scan = emit_barrier_after (scan);
-  pool_size = 0;
-}
-
-/* Return non-zero if constant would be an ok source for a
-   mov.w instead of a mov.l.  */
-
-static int
-hi_const (src)
-     rtx src;
-{
-  return (GET_CODE (src) == CONST_INT
-	  && INTVAL (src) >= -32768
-	  && INTVAL (src) <= 32767);
-}
-
-/* Non-zero if the insn is a move instruction which needs to be fixed.  */
-
-/* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
-   CONST_DOUBLE input value is CONST_OK_FOR_I.  For a SFmode move, we don't
-   need to fix it if the input value is CONST_OK_FOR_I.  */
-
-static int
-broken_move (insn)
-     rtx insn;
-{
-  if (GET_CODE (insn) == INSN)
-    {
-      rtx pat = PATTERN (insn);
-      if (GET_CODE (pat) == PARALLEL)
-	pat = XVECEXP (pat, 0, 0);
-      if (GET_CODE (pat) == SET
-	  /* We can load any 8 bit value if we don't care what the high
-	     order bits end up as.  */
-	  && GET_MODE (SET_DEST (pat)) != QImode
-	  && CONSTANT_P (SET_SRC (pat))
-	  && ! (TARGET_SH3E
-		&& GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
-		&& (fp_zero_operand (SET_SRC (pat))
-		    || fp_one_operand (SET_SRC (pat)))
-		&& GET_CODE (SET_DEST (pat)) == REG
-		&& REGNO (SET_DEST (pat)) >= FIRST_FP_REG
-		&& REGNO (SET_DEST (pat)) <= LAST_FP_REG)
-	  && (GET_CODE (SET_SRC (pat)) != CONST_INT
-	      || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat)))))
-	return 1;
-    }
-
-  return 0;
-}
-
-static int
-mova_p (insn)
-     rtx insn;
-{
-  return (GET_CODE (insn) == INSN
-	  && GET_CODE (PATTERN (insn)) == SET
-	  && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
-	  && XINT (SET_SRC (PATTERN (insn)), 1) == 1);
-}
-
-/* Find the last barrier from insn FROM which is close enough to hold the
-   constant pool.  If we can't find one, then create one near the end of
-   the range.  */
-
-static rtx
-find_barrier (num_mova, mova, from)
-     int num_mova;
-     rtx mova, from;
-{
-  int count_si = 0;
-  int count_hi = 0;
-  int found_hi = 0;
-  int found_si = 0;
-  int hi_align = 2;
-  int si_align = 2;
-  int leading_mova = num_mova;
-  rtx barrier_before_mova, found_barrier = 0, good_barrier = 0;
-  int si_limit;
-  int hi_limit;
-
-  /* For HImode: range is 510, add 4 because pc counts from address of
-     second instruction after this one, subtract 2 for the jump instruction
-     that we may need to emit before the table, subtract 2 for the instruction
-     that fills the jump delay slot (in very rare cases, reorg will take an
-     instruction from after the constant pool or will leave the delay slot
-     empty).  This gives 510.
-     For SImode: range is 1020, add 4 because pc counts from address of
-     second instruction after this one, subtract 2 in case pc is 2 byte
-     aligned, subtract 2 for the jump instruction that we may need to emit
-     before the table, subtract 2 for the instruction that fills the jump
-     delay slot.  This gives 1018.  */
-
-  /* The branch will always be shortened now that the reference address for
-     forward branches is the successor address, thus we need no longer make
-     adjustments to the [sh]i_limit for -O0.  */
-
-  si_limit = 1018;
-  hi_limit = 510;
-
-  while (from && count_si < si_limit && count_hi < hi_limit)
-    {
-      int inc = get_attr_length (from);
-      int new_align = 1;
-
-      if (GET_CODE (from) == CODE_LABEL)
-	{
-	  if (optimize)
-	    new_align = 1 << label_to_alignment (from);
-	  else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
-	    new_align = 1 << barrier_align (from);
-	  else
-	    new_align = 1;
-	  inc = 0;
-	}
-
-      if (GET_CODE (from) == BARRIER)
-	{
-
-	  found_barrier = from;
-
-	  /* If we are at the end of the function, or in front of an alignment
-	     instruction, we need not insert an extra alignment.  We prefer
-	     this kind of barrier.  */
-	  if (barrier_align (from) > 2)
-	    good_barrier = from;
-	}
-
-      if (broken_move (from))
-	{
-	  rtx pat, src, dst;
-	  enum machine_mode mode;
-
-	  pat = PATTERN (from);
-	  if (GET_CODE (pat) == PARALLEL)
-	    pat = XVECEXP (pat, 0, 0);
-	  src = SET_SRC (pat);
-	  dst = SET_DEST (pat);
-	  mode = GET_MODE (dst);
-
-	  /* We must explicitly check the mode, because sometimes the
-	     front end will generate code to load unsigned constants into
-	     HImode targets without properly sign extending them.  */
-	  if (mode == HImode
-	      || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
-	    {
-	      found_hi += 2;
-	      /* We put the short constants before the long constants, so
-		 we must count the length of short constants in the range
-		 for the long constants.  */
-	      /* ??? This isn't optimal, but is easy to do.  */
-	      si_limit -= 2;
-	    }
-	  else
-	    {
-	      while (si_align > 2 && found_si + si_align - 2 > count_si)
-		si_align >>= 1;
-	      if (found_si > count_si)
-		count_si = found_si;
-	      found_si += GET_MODE_SIZE (mode);
-	      if (num_mova)
-		si_limit -= GET_MODE_SIZE (mode);
-	    }
-	}
-
-      if (mova_p (from))
-	{
-	  if (! num_mova++)
-	    {
-	      leading_mova = 0;
-	      mova = from;
-	      barrier_before_mova = good_barrier ? good_barrier : found_barrier;
-	    }
-	  if (found_si > count_si)
-	    count_si = found_si;
-	}
-      else if (GET_CODE (from) == JUMP_INSN
-	       && (GET_CODE (PATTERN (from)) == ADDR_VEC
-		   || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
-	{
-	  if (num_mova)
-	    num_mova--;
-	  if (barrier_align (next_real_insn (from)) == CACHE_LOG)
-	    {
-	      /* We have just passed the barrier in front of the
-		 ADDR_DIFF_VEC, which is stored in found_barrier.  Since
-		 the ADDR_DIFF_VEC is accessed as data, just like our pool
-		 constants, this is a good opportunity to accommodate what
-		 we have gathered so far.
-		 If we waited any longer, we could end up at a barrier in
-		 front of code, which gives worse cache usage for separated
-		 instruction / data caches.  */
-	      good_barrier = found_barrier;
-	      break;
-	    }
-	  else
-	    {
-	      rtx body = PATTERN (from);
-	      inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
-	    }
-	}
-
-      if (found_si)
-	{
-	  if (new_align > si_align)
-	    {
-	      si_limit -= count_si - 1 & new_align - si_align;
-	      si_align = new_align;
-	    }
-	  count_si = count_si + new_align - 1 & -new_align;
-	  count_si += inc;
-	}
-      if (found_hi)
-	{
-	  if (new_align > hi_align)
-	    {
-	      hi_limit -= count_hi - 1 & new_align - hi_align;
-	      hi_align = new_align;
-	    }
-	  count_hi = count_hi + new_align - 1 & -new_align;
-	  count_hi += inc;
-	}
-      from = NEXT_INSN (from);
-    }
-
-  if (num_mova)
-    if (leading_mova)
-      {
-	/* Try as we might, the leading mova is out of range.  Change
-	   it into a load (which will become a pcload) and retry.  */
-	SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
-	INSN_CODE (mova) = -1;
-        return find_barrier (0, 0, mova);
-      }
-    else
-      {
-	/* Insert the constant pool table before the mova instruction,
-	   to prevent the mova label reference from going out of range.  */
-	from = mova;
-	good_barrier = found_barrier = barrier_before_mova;
-      }
-
-  if (found_barrier)
-    {
-      if (good_barrier && next_real_insn (found_barrier))
-	found_barrier = good_barrier;
-    }
-  else
-    {
-      /* We didn't find a barrier in time to dump our stuff,
-	 so we'll make one.  */
-      rtx label = gen_label_rtx ();
-
-      /* If we exceeded the range, then we must back up over the last
-	 instruction we looked at.  Otherwise, we just need to undo the
-	 NEXT_INSN at the end of the loop.  */
-      if (count_hi > hi_limit || count_si > si_limit)
-	from = PREV_INSN (PREV_INSN (from));
-      else
-	from = PREV_INSN (from);
-
-      /* Walk back to be just before any jump or label.
-	 Putting it before a label reduces the number of times the branch
-	 around the constant pool table will be hit.  Putting it before
-	 a jump makes it more likely that the bra delay slot will be
-	 filled.  */
-      while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
-	     || GET_CODE (from) == CODE_LABEL)
-	from = PREV_INSN (from);
-
-      from = emit_jump_insn_after (gen_jump (label), from);
-      JUMP_LABEL (from) = label;
-      LABEL_NUSES (label) = 1;
-      found_barrier = emit_barrier_after (from);
-      emit_label_after (label, found_barrier);
-    }
-
-  return found_barrier;
-}
-
-/* If the instruction INSN is implemented by a special function, and we can
-   positively find the register that is used to call the sfunc, and this
-   register is not used anywhere else in this instruction - except as the
-   destination of a set, return this register; else, return 0.  */
-rtx
-sfunc_uses_reg (insn)
-     rtx insn;
-{
-  int i;
-  rtx pattern, part, reg_part, reg;
-
-  if (GET_CODE (insn) != INSN)
-    return 0;
-  pattern = PATTERN (insn);
-  if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
-    return 0;
-
-  for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
-    {
-      part = XVECEXP (pattern, 0, i);
-      if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
-	reg_part = part;
-    }
-  if (! reg_part)
-    return 0;
-  reg = XEXP (reg_part, 0);
-  for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
-    {
-      part = XVECEXP (pattern, 0, i);
-      if (part == reg_part || GET_CODE (part) == CLOBBER)
-	continue;
-      if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
-				  && GET_CODE (SET_DEST (part)) == REG)
-				 ? SET_SRC (part) : part)))
-	return 0;
-    }
-  return reg;
-}
-
-/* See if the only way in which INSN uses REG is by calling it, or by
-   setting it while calling it.  Set *SET to a SET rtx if the register
-   is set by INSN.  */
-
-static int
-noncall_uses_reg (reg, insn, set)
-     rtx reg;
-     rtx insn;
-     rtx *set;
-{
-  rtx pattern, reg2;
-
-  *set = NULL_RTX;
-
-  reg2 = sfunc_uses_reg (insn);
-  if (reg2 && REGNO (reg2) == REGNO (reg))
-    {
-      pattern = single_set (insn);
-      if (pattern
-	  && GET_CODE (SET_DEST (pattern)) == REG
-	  && REGNO (reg) == REGNO (SET_DEST (pattern)))
-	*set = pattern;
-      return 0;
-    }
-  if (GET_CODE (insn) != CALL_INSN)
-    {
-      /* We don't use rtx_equal_p because we don't care if the mode is
-	 different.  */
-      pattern = single_set (insn);
-      if (pattern
-	  && GET_CODE (SET_DEST (pattern)) == REG
-	  && REGNO (reg) == REGNO (SET_DEST (pattern)))
-	{
-	  rtx par, part;
-	  int i;
-
-	  *set = pattern;
-	  par = PATTERN (insn);
-	  if (GET_CODE (par) == PARALLEL)
-	    for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
-	      {
-		part = XVECEXP (par, 0, i);
-		if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
-		  return 1;
-	      }
-	  return reg_mentioned_p (reg, SET_SRC (pattern));
-	}
-
-      return 1;
-    }
-
-  pattern = PATTERN (insn);
-
-  if (GET_CODE (pattern) == PARALLEL)
-    {
-      int i;
-
-      for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
-	if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
-	  return 1;
-      pattern = XVECEXP (pattern, 0, 0);
-    }
-
-  if (GET_CODE (pattern) == SET)
-    {
-      if (reg_mentioned_p (reg, SET_DEST (pattern)))
-	{
-	  /* We don't use rtx_equal_p, because we don't care if the
-             mode is different.  */
-	  if (GET_CODE (SET_DEST (pattern)) != REG
-	      || REGNO (reg) != REGNO (SET_DEST (pattern)))
-	    return 1;
-
-	  *set = pattern;
-	}
-
-      pattern = SET_SRC (pattern);
-    }
-
-  if (GET_CODE (pattern) != CALL
-      || GET_CODE (XEXP (pattern, 0)) != MEM
-      || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
-    return 1;
-
-  return 0;
-}
-
-/* Given a X, a pattern of an insn or a part of it, return a mask of used
-   general registers.  Bits 0..15 mean that the respective registers
-   are used as inputs in the instruction.  Bits 16..31 mean that the
-   registers 0..15, respectively, are used as outputs, or are clobbered.
-   IS_DEST should be set to 16 if X is the destination of a SET, else to 0.  */
-int
-regs_used (x, is_dest)
-     rtx x; int is_dest;
-{
-  enum rtx_code code;
-  char *fmt;
-  int i, used = 0;
-
-  if (! x)
-    return used;
-  code = GET_CODE (x);
-  switch (code)
-    {
-    case REG:
-      if (REGNO (x) < 16)
-	return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
-		<< (REGNO (x) + is_dest));
-      return 0;
-    case SUBREG:
-      {
-	rtx y = SUBREG_REG (x);
-     
-	if (GET_CODE (y) != REG)
-	  break;
-	if (REGNO (y) < 16)
-	  return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
-		  << (REGNO (y) + SUBREG_WORD (x) + is_dest));
-	return 0;
-      }
-    case SET:
-      return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
-    case RETURN:
-      /* If there was a return value, it must have been indicated with USE.  */
-      return 0x00ffff00;
-    case CLOBBER:
-      is_dest = 1;
-      break;
-    case MEM:
-      is_dest = 0;
-      break;
-    case CALL:
-      used |= 0x00ff00f0;
-      break;
-    }
-
-  fmt = GET_RTX_FORMAT (code);
-
-  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
-    {
-      if (fmt[i] == 'E')
-	{
-	  register int j;
-	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
-	    used |= regs_used (XVECEXP (x, i, j), is_dest);
-	}
-      else if (fmt[i] == 'e')
-	used |= regs_used (XEXP (x, i), is_dest);
-    }
-  return used;
-}
-
-/* Create an instruction that prevents redirection of a conditional branch
-   to the destination of the JUMP with address ADDR.
-   If the branch needs to be implemented as an indirect jump, try to find
-   a scratch register for it.
-   If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
-   If any preceding insn that doesn't fit into a delay slot is good enough,
-   pass 1.  Pass 2 if a definite blocking insn is needed.
-   -1 is used internally to avoid deep recursion.
-   If a blocking instruction is made or recognized, return it.  */
-   
-static rtx
-gen_block_redirect (jump, addr, need_block)
-     rtx jump;
-     int addr, need_block;
-{
-  int dead = 0;
-  rtx prev = prev_nonnote_insn (jump);
-  rtx dest;
-
-  /* First, check if we already have an instruction that satisfies our need.  */
-  if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
-    {
-      if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
-	return prev;
-      if (GET_CODE (PATTERN (prev)) == USE
-	  || GET_CODE (PATTERN (prev)) == CLOBBER
-	  || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
-	prev = jump;
-      else if ((need_block &= ~1) < 0)
-	return prev;
-      else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
-	need_block = 0;
-    }
-  /* We can't use JUMP_LABEL here because it might be undefined
-     when not optimizing.  */
-  dest = XEXP (SET_SRC (PATTERN (jump)), 0);
-  /* If the branch is out of range, try to find a scratch register for it.  */
-  if (optimize
-      && (insn_addresses[INSN_UID (dest)] - addr + 4092U > 4092 + 4098))
-    {
-      rtx scan;
-      /* Don't look for the stack pointer as a scratch register,
-	 it would cause trouble if an interrupt occurred.  */
-      unsigned try = 0x7fff, used;
-      int jump_left = flag_expensive_optimizations + 1;
-    
-      /* It is likely that the most recent eligible instruction is wanted for
-	 the delay slot.  Therefore, find out which registers it uses, and
-	 try to avoid using them.  */
-	 
-      for (scan = jump; scan = PREV_INSN (scan); )
-	{
-	  enum rtx_code code;
-
-	  if (INSN_DELETED_P (scan))
-	    continue;
-	  code = GET_CODE (scan);
-	  if (code == CODE_LABEL || code == JUMP_INSN)
-	    break;
-	  if (code == INSN
-	      && GET_CODE (PATTERN (scan)) != USE
-	      && GET_CODE (PATTERN (scan)) != CLOBBER
-	      && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
-	    {
-	      try &= ~regs_used (PATTERN (scan), 0);
-	      break;
-	    }
-	}
-      for (used = dead = 0, scan = JUMP_LABEL (jump); scan = NEXT_INSN (scan); )
-	{
-	  enum rtx_code code;
-
-	  if (INSN_DELETED_P (scan))
-	    continue;
-	  code = GET_CODE (scan);
-	  if (GET_RTX_CLASS (code) == 'i')
-	    {
-	      used |= regs_used (PATTERN (scan), 0);
-	      if (code == CALL_INSN)
-		used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
-	      dead |= (used >> 16) & ~used;
-	      if (dead & try)
-		{
-		  dead &= try;
-		  break;
-		}
-	      if (code == JUMP_INSN)
-		if (jump_left-- && simplejump_p (scan))
-		  scan = JUMP_LABEL (scan);
-		else
-		  break;
-	    }
-	}
-      /* Mask out the stack pointer again, in case it was
-	 the only 'free' register we have found.  */
-      dead &= 0x7fff;
-    }
-  /* If the immediate destination is still in range, check for possible
-     threading with a jump beyond the delay slot insn.
-     Don't check if we are called recursively; the jump has been or will be
-     checked in a different invocation then.  */
-	
-  else if (optimize && need_block >= 0)
-    {
-      rtx next = next_active_insn (next_active_insn (dest));
-      if (next && GET_CODE (next) == JUMP_INSN
-	  && GET_CODE (PATTERN (next)) == SET
-	  && recog_memoized (next) == CODE_FOR_jump)
-	{
-	  dest = JUMP_LABEL (next);
-	  if (dest
-	      && insn_addresses[INSN_UID (dest)] - addr + 4092U > 4092 + 4098)
-	    gen_block_redirect (next, insn_addresses[INSN_UID (next)], -1);
-	}
-    }
-
-  if (dead)
-    {
-      rtx reg = gen_rtx (REG, SImode, exact_log2 (dead & -dead));
-
-      /* It would be nice if we could convert the jump into an indirect
-	 jump / far branch right now, and thus exposing all constituent
-	 instructions to further optimization.  However, reorg uses
-	 simplejump_p to determine if there is an unconditional jump where
-	 it should try to schedule instructions from the target of the
-	 branch; simplejump_p fails for indirect jumps even if they have
-	 a JUMP_LABEL.  */
-      rtx insn = emit_insn_before (gen_indirect_jump_scratch
-				   (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
-				   , jump);
-      INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
-      return insn;
-    }
-  else if (need_block)
-    /* We can't use JUMP_LABEL here because it might be undefined
-       when not optimizing.  */
-    return emit_insn_before (gen_block_branch_redirect
-		      (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
-		      , jump);
-  return prev;
-}
-
-#define CONDJUMP_MIN -252
-#define CONDJUMP_MAX 262
-struct far_branch
-{
-  /* A label (to be placed) in front of the jump
-     that jumps to our ultimate destination.  */
-  rtx near_label;
-  /* Where we are going to insert it if we cannot move the jump any farther,
-     or the jump itself if we have picked up an existing jump.  */
-  rtx insert_place;
-  /* The ultimate destination.  */
-  rtx far_label;
-  struct far_branch *prev;
-  /* If the branch has already been created, its address;
-     else the address of its first prospective user.  */
-  int address;
-};
-
-enum mdep_reorg_phase_e mdep_reorg_phase;
-void
-gen_far_branch (bp)
-     struct far_branch *bp;
-{
-  rtx insn = bp->insert_place;
-  rtx jump;
-  rtx label = gen_label_rtx ();
-
-  emit_label_after (label, insn);
-  if (bp->far_label)
-    {
-      jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
-      LABEL_NUSES (bp->far_label)++;
-    }
-  else
-    jump = emit_jump_insn_after (gen_return (), insn);
-  /* Emit a barrier so that reorg knows that any following instructions
-     are not reachable via a fall-through path.
-     But don't do this when not optimizing, since we wouldn't supress the
-     alignment for the barrier then, and could end up with out-of-range
-     pc-relative loads.  */
-  if (optimize)
-    emit_barrier_after (jump);
-  emit_label_after (bp->near_label, insn);
-  JUMP_LABEL (jump) = bp->far_label;
-  if (! invert_jump (insn, label))
-    abort ();
-  /* Prevent reorg from undoing our splits.  */
-  gen_block_redirect (jump, bp->address += 2, 2);
-}
-
-/* Fix up ADDR_DIFF_VECs.  */
-void
-fixup_addr_diff_vecs (first)
-     rtx first;
-{
-  rtx insn;
-
-  for (insn = first; insn; insn = NEXT_INSN (insn))
-    {
-      rtx vec_lab, pat, prev, prevpat, x, braf_label;
-
-      if (GET_CODE (insn) != JUMP_INSN
-	  || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
-	continue;
-      pat = PATTERN (insn);
-      vec_lab = XEXP (XEXP (pat, 0), 0);
-
-      /* Search the matching casesi_jump_2.  */
-      for (prev = vec_lab; ; prev = PREV_INSN (prev))
-	{
-	  if (GET_CODE (prev) != JUMP_INSN)
-	    continue;
-	  prevpat = PATTERN (prev);
-	  if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
-	    continue;
-	  x = XVECEXP (prevpat, 0, 1);
-	  if (GET_CODE (x) != USE)
-	    continue;
-	  x = XEXP (x, 0);
-	  if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
-	    break;
-	}
-
-      /* Emit the reference label of the braf where it belongs, right after
-	 the casesi_jump_2 (i.e. braf).  */
-      braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
-      emit_label_after (braf_label, prev);
-
-      /* Fix up the ADDR_DIF_VEC to be relative
-	 to the reference address of the braf.  */
-      XEXP (XEXP (pat, 0), 0) = braf_label;
-    }
-}
-
-/* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
-   a barrier.  Return the base 2 logarithm of the desired alignment.  */
-int
-barrier_align (barrier_or_label)
-     rtx barrier_or_label;
-{
-  rtx next = next_real_insn (barrier_or_label), pat, prev;
-  int slot, credit;
- 
-  if (! next)
-    return 0;
-
-  pat = PATTERN (next);
-
-  if (GET_CODE (pat) == ADDR_DIFF_VEC)
-    return 2;
-
-  if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == 1)
-    /* This is a barrier in front of a constant table.  */
-    return 0;
-
-  prev = prev_real_insn (barrier_or_label);
-  if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
-    {
-      pat = PATTERN (prev);
-      /* If this is a very small table, we want to keep the alignment after
-	 the table to the minimum for proper code alignment.  */
-      return ((TARGET_SMALLCODE
-	       || (XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
-		   <= 1 << (CACHE_LOG - 2)))
-	      ? 1 : CACHE_LOG);
-    }
-
-  if (TARGET_SMALLCODE)
-    return 0;
-
-  if (! TARGET_SH3 || ! optimize)
-    return CACHE_LOG;
-
-  /* When fixing up pcloads, a constant table might be inserted just before
-     the basic block that ends with the barrier.  Thus, we can't trust the
-     instruction lengths before that.  */
-  if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
-    {
-      /* Check if there is an immediately preceding branch to the insn beyond
-	 the barrier.  We must weight the cost of discarding useful information
-	 from the current cache line when executing this branch and there is
-	 an alignment, against that of fetching unneeded insn in front of the
-	 branch target when there is no alignment.  */
-
-      /* PREV is presumed to be the JUMP_INSN for the barrier under
-	 investigation.  Skip to the insn before it.  */
-      prev = prev_real_insn (prev);
-
-      for (slot = 2, credit = 1 << (CACHE_LOG - 2) + 2;
-	   credit >= 0 && prev && GET_CODE (prev) == INSN;
-	   prev = prev_real_insn (prev))
-	{
-	  if (GET_CODE (PATTERN (prev)) == USE
-	      || GET_CODE (PATTERN (prev)) == CLOBBER)
-	    continue;
-	  if (GET_CODE (PATTERN (prev)) == SEQUENCE)
-	    prev = XVECEXP (PATTERN (prev), 0, 1);
-	  if (slot &&
-	      get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
-	    slot = 0;
-	  credit -= get_attr_length (prev);
-	}
-      if (prev
-	  && GET_CODE (prev) == JUMP_INSN
-	  && JUMP_LABEL (prev)
-	  && next_real_insn (JUMP_LABEL (prev)) == next_real_insn (barrier_or_label)
-	  && (credit - slot >= (GET_CODE (SET_SRC (PATTERN (prev))) == PC ? 2 : 0)))
-	return 0;
-    }
-
-  return CACHE_LOG;
-}
-
-/* If we are inside a phony loop, lmost any kind of label can turn up as the
-   first one in the loop.  Aligning a braf label causes incorrect switch
-   destination addresses; we can detect braf labels because they are
-   followed by a BARRIER.
-   Applying loop alignment to small constant or switch tables is a waste
-   of space, so we suppress this too.  */
-int
-sh_loop_align (label)
-     rtx label;
-{
-  rtx next = label;
-
-  do
-    next = next_nonnote_insn (next);
-  while (next && GET_CODE (next) == CODE_LABEL);
-
-  if (! next
-      || GET_RTX_CLASS (GET_CODE (next)) != 'i'
-      || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
-      || recog_memoized (next) == CODE_FOR_consttable_2)
-    return 0;
-  return 2;
-}
-
-/* Exported to toplev.c.
-
-   Do a final pass over the function, just before delayed branch
-   scheduling.  */
-
-void
-machine_dependent_reorg (first)
-     rtx first;
-{
-  rtx insn, mova;
-  int num_mova;
-  rtx r0_rtx = gen_rtx (REG, Pmode, 0);
-  rtx r0_inc_rtx = gen_rtx (POST_INC, Pmode, r0_rtx);
-
-  /* If relaxing, generate pseudo-ops to associate function calls with
-     the symbols they call.  It does no harm to not generate these
-     pseudo-ops.  However, when we can generate them, it enables to
-     linker to potentially relax the jsr to a bsr, and eliminate the
-     register load and, possibly, the constant pool entry.  */
-
-  mdep_reorg_phase = SH_INSERT_USES_LABELS;
-  if (TARGET_RELAX)
-    {
-      /* Remove all REG_LABEL notes.  We want to use them for our own
-	 purposes.  This works because none of the remaining passes
-	 need to look at them.
-
-	 ??? But it may break in the future.  We should use a machine
-	 dependent REG_NOTE, or some other approach entirely.  */
-      for (insn = first; insn; insn = NEXT_INSN (insn))
-	{
-	  if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
-	    {
-	      rtx note;
-
-	      while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
-		remove_note (insn, note);
-	    }
-	}
-
-      for (insn = first; insn; insn = NEXT_INSN (insn))
-	{
-	  rtx pattern, reg, link, set, scan, dies, label;
-	  int rescan = 0, foundinsn = 0;
-
-	  if (GET_CODE (insn) == CALL_INSN)
-	    {
-	      pattern = PATTERN (insn);
-
-	      if (GET_CODE (pattern) == PARALLEL)
-		pattern = XVECEXP (pattern, 0, 0);
-	      if (GET_CODE (pattern) == SET)
-		pattern = SET_SRC (pattern);
-
-	      if (GET_CODE (pattern) != CALL
-		  || GET_CODE (XEXP (pattern, 0)) != MEM)
-		continue;
-
-	      reg = XEXP (XEXP (pattern, 0), 0);
-	    }
-	  else
-	    {
-	      reg = sfunc_uses_reg (insn);
-	      if (! reg)
-		continue;
-	    }
-
-	  if (GET_CODE (reg) != REG)
-	    continue;
-
-	  /* This is a function call via REG.  If the only uses of REG
-	     between the time that it is set and the time that it dies
-	     are in function calls, then we can associate all the
-	     function calls with the setting of REG.  */
-
-	  for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
-	    {
-	      if (REG_NOTE_KIND (link) != 0)
-		continue;
-	      set = single_set (XEXP (link, 0));
-	      if (set && rtx_equal_p (reg, SET_DEST (set)))
-		{
-		  link = XEXP (link, 0);
-		  break;
-		}
-	    }
-
-	  if (! link)
-	    {
-	      /* ??? Sometimes global register allocation will have
-                 deleted the insn pointed to by LOG_LINKS.  Try
-                 scanning backward to find where the register is set.  */
-	      for (scan = PREV_INSN (insn);
-		   scan && GET_CODE (scan) != CODE_LABEL;
-		   scan = PREV_INSN (scan))
-		{
-		  if (GET_RTX_CLASS (GET_CODE (scan)) != 'i')
-		    continue;
-
-		  if (! reg_mentioned_p (reg, scan))
-		    continue;
-
-		  if (noncall_uses_reg (reg, scan, &set))
-		    break;
-
-		  if (set)
-		    {
-		      link = scan;
-		      break;
-		    }
-		}
-	    }
-
-	  if (! link)
-	    continue;
-
-	  /* The register is set at LINK.  */
-
-	  /* We can only optimize the function call if the register is
-             being set to a symbol.  In theory, we could sometimes
-             optimize calls to a constant location, but the assembler
-             and linker do not support that at present.  */
-	  if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
-	      && GET_CODE (SET_SRC (set)) != LABEL_REF)
-	    continue;
-
-	  /* Scan forward from LINK to the place where REG dies, and
-             make sure that the only insns which use REG are
-             themselves function calls.  */
-
-	  /* ??? This doesn't work for call targets that were allocated
-	     by reload, since there may not be a REG_DEAD note for the
-	     register.  */
-
-	  dies = NULL_RTX;
-	  for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
-	    {
-	      rtx scanset;
-
-	      /* Don't try to trace forward past a CODE_LABEL if we haven't
-		 seen INSN yet.  Ordinarily, we will only find the setting insn
-		 in LOG_LINKS if it is in the same basic block.  However,
-		 cross-jumping can insert code labels in between the load and
-		 the call, and can result in situations where a single call
-		 insn may have two targets depending on where we came from.  */
-
-	      if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
-		break;
-
-	      if (GET_RTX_CLASS (GET_CODE (scan)) != 'i')
-		continue;
-
-	      /* Don't try to trace forward past a JUMP.  To optimize
-                 safely, we would have to check that all the
-                 instructions at the jump destination did not use REG.  */
-
-	      if (GET_CODE (scan) == JUMP_INSN)
-		break;
-
-	      if (! reg_mentioned_p (reg, scan))
-		continue;
-
-	      if (noncall_uses_reg (reg, scan, &scanset))
-		break;
-
-	      if (scan == insn)
-		foundinsn = 1;
-
-	      if (scan != insn
-		  && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
-		{
-		  /* There is a function call to this register other
-                     than the one we are checking.  If we optimize
-                     this call, we need to rescan again below.  */
-		  rescan = 1;
-		}
-
-	      /* ??? We shouldn't have to worry about SCANSET here.
-		 We should just be able to check for a REG_DEAD note
-		 on a function call.  However, the REG_DEAD notes are
-		 apparently not dependable around libcalls; c-torture
-		 execute/920501-2 is a test case.  If SCANSET is set,
-		 then this insn sets the register, so it must have
-		 died earlier.  Unfortunately, this will only handle
-		 the cases in which the register is, in fact, set in a
-		 later insn.  */
-
-	      /* ??? We shouldn't have to use FOUNDINSN here.
-		 However, the LOG_LINKS fields are apparently not
-		 entirely reliable around libcalls;
-		 newlib/libm/math/e_pow.c is a test case.  Sometimes
-		 an insn will appear in LOG_LINKS even though it is
-		 not the most recent insn which sets the register. */
-
-	      if (foundinsn
-		  && (scanset
-		      || find_reg_note (scan, REG_DEAD, reg)))
-		{
-		  dies = scan;
-		  break;
-		}
-	    }
-
-	  if (! dies)
-	    {
-	      /* Either there was a branch, or some insn used REG
-                 other than as a function call address.  */
-	      continue;
-	    }
-
-	  /* Create a code label, and put it in a REG_LABEL note on
-             the insn which sets the register, and on each call insn
-             which uses the register.  In final_prescan_insn we look
-             for the REG_LABEL notes, and output the appropriate label
-             or pseudo-op.  */
-
-	  label = gen_label_rtx ();
-	  REG_NOTES (link) = gen_rtx (EXPR_LIST, REG_LABEL, label,
-				      REG_NOTES (link));
-	  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL, label,
-				      REG_NOTES (insn));
-	  if (rescan)
-	    {
-	      scan = link;
-	      do
-		{
-		  rtx reg2;
-
-		  scan = NEXT_INSN (scan);
-		  if (scan != insn
-		      && ((GET_CODE (scan) == CALL_INSN
-			   && reg_mentioned_p (reg, scan))
-			  || ((reg2 = sfunc_uses_reg (scan))
-			      && REGNO (reg2) == REGNO (reg))))
-		    REG_NOTES (scan) = gen_rtx (EXPR_LIST, REG_LABEL,
-						label, REG_NOTES (scan));
-		}
-	      while (scan != dies);
-	    }
-	}
-    }
-
-  if (TARGET_SH2)
-    fixup_addr_diff_vecs (first);
-
-  if (optimize)
-    {
-      mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
-      shorten_branches (first);
-    }
-  /* Scan the function looking for move instructions which have to be
-     changed to pc-relative loads and insert the literal tables.  */
-
-  mdep_reorg_phase = SH_FIXUP_PCLOAD;
-  for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
-    {
-      if (mova_p (insn))
-	{
-	  if (! num_mova++)
-	    mova = insn;
-	}
-      else if (GET_CODE (insn) == JUMP_INSN
-	       && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
-	       && num_mova)
-	{
-	  rtx scan;
-	  int total;
-
-	  num_mova--;
-
-	  /* Some code might have been inserted between the mova and
-	     its ADDR_DIFF_VEC.  Check if the mova is still in range.  */
-	  for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
-	    total += get_attr_length (scan);
-
-	  /* range of mova is 1020, add 4 because pc counts from address of
-	     second instruction after this one, subtract 2 in case pc is 2
-	     byte aligned.  Possible alignment needed for the ADDR_DIFF_VEC
-	     cancels out with alignment effects of the mova itself.  */
-	  if (total > 1022)
-	    {
-	      /* Change the mova into a load, and restart scanning
-		 there.  broken_move will then return true for mova.  */
-	      SET_SRC (PATTERN (mova))
-		= XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
-	      INSN_CODE (mova) = -1;
-	      insn = mova;
-	    }
-	}
-      if (broken_move (insn))
-	{
-	  rtx scan;
-	  /* Scan ahead looking for a barrier to stick the constant table
-	     behind.  */
-	  rtx barrier = find_barrier (num_mova, mova, insn);
-	  rtx last_float_move, last_float = 0, *last_float_addr;
-
-	  if (num_mova && ! mova_p (mova))
-	    {
-	      /* find_barrier had to change the first mova into a
-		 pcload; thus, we have to start with this new pcload.  */
-	      insn = mova;
-	      num_mova = 0;
-	    }
-	  /* Now find all the moves between the points and modify them.  */
-	  for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
-	    {
-	      if (GET_CODE (scan) == CODE_LABEL)
-		last_float = 0;
-	      if (broken_move (scan))
-		{
-		  rtx *patp = &PATTERN (scan), pat = *patp;
-		  rtx src, dst;
-		  rtx lab;
-		  rtx newinsn;
-		  rtx newsrc;
-		  enum machine_mode mode;
-
-		  if (GET_CODE (pat) == PARALLEL)
-		    patp = &XVECEXP (pat, 0, 0), pat = *patp;
-		  src = SET_SRC (pat);
-		  dst = SET_DEST (pat);
-		  mode = GET_MODE (dst);
-
-		  if (mode == SImode && hi_const (src)
-		      && REGNO (dst) != FPUL_REG)
-		    {
-		      int offset = 0;
-
-		      mode = HImode;
-		      while (GET_CODE (dst) == SUBREG)
-			{
-			  offset += SUBREG_WORD (dst);
-			  dst = SUBREG_REG (dst);
-			}
-		      dst = gen_rtx (REG, HImode, REGNO (dst) + offset);
-		    }
-
-		  if (GET_CODE (dst) == REG
-		      && ((REGNO (dst) >= FIRST_FP_REG
-			   && REGNO (dst) <= LAST_XD_REG)
-			  || REGNO (dst) == FPUL_REG))
-		    {
-		      if (last_float
-			  && reg_set_between_p (r0_rtx, last_float_move, scan))
-			last_float = 0;
-		      lab = add_constant (src, mode, last_float);
-		      if (lab)
-			emit_insn_before (gen_mova (lab), scan);
-		      else
-			*last_float_addr = r0_inc_rtx;
-		      last_float_move = scan;
-		      last_float = src;
-		      newsrc = gen_rtx (MEM, mode,
-					((TARGET_SH4 && ! TARGET_FMOVD
-					  || REGNO (dst) == FPUL_REG)
-					 ? r0_inc_rtx
-					 : r0_rtx));
-		      last_float_addr = &XEXP (newsrc, 0);
-		    }
-		  else
-		    {
-		      lab = add_constant (src, mode, 0);
-		      newsrc = gen_rtx (MEM, mode,
-					gen_rtx (LABEL_REF, VOIDmode, lab));
-		    }
-		  RTX_UNCHANGING_P (newsrc) = 1;
-		  *patp = gen_rtx (SET, VOIDmode, dst, newsrc);
-		  INSN_CODE (scan) = -1;
-		}
-	    }
-	  dump_table (barrier);
-	  insn = barrier;
-	}
-    }
-
-  mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
-  insn_addresses = 0;
-  split_branches (first);
-
-  /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
-     also has an effect on the register that holds the addres of the sfunc.
-     Insert an extra dummy insn in front of each sfunc that pretends to
-     use this register.  */
-  if (flag_delayed_branch)
-    {
-      for (insn = first; insn; insn = NEXT_INSN (insn))
-	{
-	  rtx reg = sfunc_uses_reg (insn);
-
-	  if (! reg)
-	    continue;
-	  emit_insn_before (gen_use_sfunc_addr (reg), insn);
-	}
-    }
-#if 0
-  /* fpscr is not actually a user variable, but we pretend it is for the
-     sake of the previous optimization passes, since we want it handled like
-     one.  However, we don't have eny debugging information for it, so turn
-     it into a non-user variable now.  */
-  if (TARGET_SH4)
-    REG_USERVAR_P (get_fpscr_rtx ()) = 0;
-#endif
-  if (optimize)
-    sh_flag_remove_dead_before_cse = 1;
-  mdep_reorg_phase = SH_AFTER_MDEP_REORG;
-}
-
-int
-get_dest_uid (label, max_uid)
-     rtx label;
-     int max_uid;
-{
-  rtx dest = next_real_insn (label);
-  int dest_uid;
-  if (! dest)
-    /* This can happen for an undefined label.  */
-    return 0;
-  dest_uid = INSN_UID (dest);
-  /* If this is a newly created branch redirection blocking instruction,
-     we cannot index the branch_uid or insn_addresses arrays with its
-     uid.  But then, we won't need to, because the actual destination is
-     the following branch.  */
-  while (dest_uid >= max_uid)
-    {
-      dest = NEXT_INSN (dest);
-      dest_uid = INSN_UID (dest);
-    }
-  if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
-    return 0;
-  return dest_uid;
-}
-
-/* Split condbranches that are out of range.  Also add clobbers for
-   scratch registers that are needed in far jumps.
-   We do this before delay slot scheduling, so that it can take our
-   newly created instructions into account.  It also allows us to
-   find branches with common targets more easily.  */
-
-static void
-split_branches (first)
-     rtx first;
-{
-  rtx insn;
-  struct far_branch **uid_branch, *far_branch_list = 0;
-  int max_uid = get_max_uid ();
-
-  /* Find out which branches are out of range.  */
-  shorten_branches (first);
-
-  uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
-  bzero ((char *) uid_branch, max_uid * sizeof *uid_branch);
-
-  for (insn = first; insn; insn = NEXT_INSN (insn))
-    if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
-      continue;
-    else if (INSN_DELETED_P (insn))
-      {
-	/* Shorten_branches would split this instruction again,
-	   so transform it into a note.  */
-	PUT_CODE (insn, NOTE);
-	NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
-	NOTE_SOURCE_FILE (insn) = 0;
-      }
-    else if (GET_CODE (insn) == JUMP_INSN
-	     /* Don't mess with ADDR_DIFF_VEC */
-	     && (GET_CODE (PATTERN (insn)) == SET
-		 || GET_CODE (PATTERN (insn)) == RETURN))
-      {
-	enum attr_type type = get_attr_type (insn);
-	if (type == TYPE_CBRANCH)
-	  {
-	    rtx next, beyond;
-    
-	    if (get_attr_length (insn) > 4)
-	      {
-		rtx src = SET_SRC (PATTERN (insn));
-		rtx cond = XEXP (src, 0);
-		rtx olabel = XEXP (XEXP (src, 1), 0);
-		rtx jump;
-		int addr = insn_addresses[INSN_UID (insn)];
-		rtx label = 0;
-		int dest_uid = get_dest_uid (olabel, max_uid);
-		struct far_branch *bp = uid_branch[dest_uid];
-    
-		/* redirect_jump needs a valid JUMP_LABEL, and it might delete
-		   the label if the LABEL_NUSES count drops to zero.  There is
-		   always a jump_optimize pass that sets these values, but it
-		   proceeds to delete unreferenced code, and then if not
-		   optimizing, to un-delete the deleted instructions, thus
-		   leaving labels with too low uses counts.  */
-		if (! optimize)
-		  {
-		    JUMP_LABEL (insn) = olabel;
-		    LABEL_NUSES (olabel)++;
-		  }
-		if (! bp)
-		  {
-		    bp = (struct far_branch *) alloca (sizeof *bp);
-		    uid_branch[dest_uid] = bp;
-		    bp->prev = far_branch_list;
-		    far_branch_list = bp;
-		    bp->far_label
-		      = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
-		    LABEL_NUSES (bp->far_label)++;
-		  }
-		else
-		  {
-		    label = bp->near_label;
-		    if (! label && bp->address - addr >= CONDJUMP_MIN)
-		      {
-			rtx block = bp->insert_place;
-
-			if (GET_CODE (PATTERN (block)) == RETURN)
-			  block = PREV_INSN (block);
-			else
-			  block = gen_block_redirect (block,
-						      bp->address, 2);
-			label = emit_label_after (gen_label_rtx (),
-						  PREV_INSN (block));
-			bp->near_label = label;
-		      }
-		    else if (label && ! NEXT_INSN (label))
-		      if (addr + 2 - bp->address <= CONDJUMP_MAX)
-			bp->insert_place = insn;
-		      else
-			gen_far_branch (bp);
-		  }
-		if (! label
-		    || NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN)
-		  {
-		    bp->near_label = label = gen_label_rtx ();
-		    bp->insert_place = insn;
-		    bp->address = addr;
-		  }
-		if (! redirect_jump (insn, label))
-		  abort ();
-	      }
-	    else
-	      {
-		/* get_attr_length (insn) == 2 */
-		/* Check if we have a pattern where reorg wants to redirect
-		   the branch to a label from an unconditional branch that
-		   is too far away.  */
-		/* We can't use JUMP_LABEL here because it might be undefined
-		   when not optimizing.  */
-		/* A syntax error might cause beyond to be NULL_RTX.  */
-		beyond
-		  = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
-					    0));
-	
-		if (beyond
-		    && (GET_CODE (beyond) == JUMP_INSN
-			|| (GET_CODE (beyond = next_active_insn (beyond))
-			    == JUMP_INSN))
-		    && GET_CODE (PATTERN (beyond)) == SET
-		    && recog_memoized (beyond) == CODE_FOR_jump
-		    && ((insn_addresses[INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0))]
-			 - insn_addresses[INSN_UID (insn)] + 252U)
-			> 252 + 258 + 2))
-		  gen_block_redirect (beyond,
-				      insn_addresses[INSN_UID (beyond)], 1);
-	      }
-    
-	    next = next_active_insn (insn);
-
-	    if ((GET_CODE (next) == JUMP_INSN
-		 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
-		&& GET_CODE (PATTERN (next)) == SET
-		&& recog_memoized (next) == CODE_FOR_jump
-		&& ((insn_addresses[INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0))]
-		     - insn_addresses[INSN_UID (insn)] + 252U)
-		    > 252 + 258 + 2))
-	      gen_block_redirect (next, insn_addresses[INSN_UID (next)], 1);
-	  }
-	else if (type == TYPE_JUMP || type == TYPE_RETURN)
-	  {
-	    int addr = insn_addresses[INSN_UID (insn)];
-	    rtx far_label = 0;
-	    int dest_uid = 0;
-	    struct far_branch *bp;
-
-	    if (type == TYPE_JUMP)
-	      {
-		far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
-		dest_uid = get_dest_uid (far_label, max_uid);
-		if (! dest_uid)
-		  {
-		    /* Parse errors can lead to labels outside
-		      the insn stream.  */
-		    if (! NEXT_INSN (far_label))
-		      continue;
-
-		    if (! optimize)
-		      {
-			JUMP_LABEL (insn) = far_label;
-			LABEL_NUSES (far_label)++;
-		      }
-		    redirect_jump (insn, NULL_RTX);
-		    far_label = 0;
-		  }
-	      }
-	    bp = uid_branch[dest_uid];
-	    if (! bp)
-	      {
-		bp = (struct far_branch *) alloca (sizeof *bp);
-		uid_branch[dest_uid] = bp;
-		bp->prev = far_branch_list;
-		far_branch_list = bp;
-		bp->near_label = 0;
-		bp->far_label = far_label;
-		if (far_label)
-		  LABEL_NUSES (far_label)++;
-	      }
-	    else if (bp->near_label && ! NEXT_INSN (bp->near_label))
-	      if (addr - bp->address <= CONDJUMP_MAX)
-		emit_label_after (bp->near_label, PREV_INSN (insn));
-	      else
-		{
-		  gen_far_branch (bp);
-		  bp->near_label = 0;
-		}
-	    else
-	      bp->near_label = 0;
-	    bp->address = addr;
-	    bp->insert_place = insn;
-	    if (! far_label)
-	      emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
-	    else
-	      gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
-	  }
-      }
-  /* Generate all pending far branches,
-     and free our references to the far labels.  */
-  while (far_branch_list)
-    {
-      if (far_branch_list->near_label
-	  && ! NEXT_INSN (far_branch_list->near_label))
-	gen_far_branch (far_branch_list);
-      if (optimize
-	  && far_branch_list->far_label
-	  && ! --LABEL_NUSES (far_branch_list->far_label))
-	delete_insn (far_branch_list->far_label);
-      far_branch_list = far_branch_list->prev;
-    }
-
-  /* Instruction length information is no longer valid due to the new
-     instructions that have been generated.  */
-  init_insn_lengths ();
-}
-
-/* Dump out instruction addresses, which is useful for debugging the
-   constant pool table stuff.
-
-   If relaxing, output the label and pseudo-ops used to link together
-   calls and the instruction which set the registers.  */
-
-/* ??? This is unnecessary, and probably should be deleted.  This makes
-   the insn_addresses declaration above unnecessary.  */
-
-/* ??? The addresses printed by this routine for insns are nonsense for
-   insns which are inside of a sequence where none of the inner insns have
-   variable length.  This is because the second pass of shorten_branches
-   does not bother to update them.  */
-
-void
-final_prescan_insn (insn, opvec, noperands)
-     rtx insn;
-     rtx *opvec;
-     int noperands;
-{
-  if (TARGET_DUMPISIZE)
-    fprintf (asm_out_file, "\n! at %04x\n", insn_addresses[INSN_UID (insn)]);
-
-  if (TARGET_RELAX)
-    {
-      rtx note;
-
-      note = find_reg_note (insn, REG_LABEL, NULL_RTX);
-      if (note)
-	{
-	  rtx pattern;
-
-	  pattern = PATTERN (insn);
-	  if (GET_CODE (pattern) == PARALLEL)
-	    pattern = XVECEXP (pattern, 0, 0);
-	  if (GET_CODE (pattern) == CALL
-	      || (GET_CODE (pattern) == SET
-		  && (GET_CODE (SET_SRC (pattern)) == CALL
-		      || get_attr_type (insn) == TYPE_SFUNC)))
-	    asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
-			 CODE_LABEL_NUMBER (XEXP (note, 0)));
-	  else if (GET_CODE (pattern) == SET)
-	    ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				       CODE_LABEL_NUMBER (XEXP (note, 0)));
-	  else
-	    abort ();
-	}
-    }
-}
-
-/* Dump out any constants accumulated in the final pass.  These will
-   only be labels.  */
-
-char *
-output_jump_label_table ()
-{
-  int i;
-
-  if (pool_size)
-    {
-      fprintf (asm_out_file, "\t.align 2\n");
-      for (i = 0; i < pool_size; i++)
-	{
-	  pool_node *p = &pool_vector[i];
-
-	  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
-				     CODE_LABEL_NUMBER (p->label));
-	  output_asm_insn (".long	%O0", &p->value);
-	}
-      pool_size = 0;
-    }
-
-  return "";
-}
-
-/* A full frame looks like:
-
-   arg-5
-   arg-4
-   [ if current_function_anonymous_args
-   arg-3
-   arg-2
-   arg-1
-   arg-0 ]
-   saved-fp
-   saved-r10
-   saved-r11
-   saved-r12
-   saved-pr
-   local-n
-   ..
-   local-1
-   local-0        <- fp points here.  */
-
-/* Number of bytes pushed for anonymous args, used to pass information
-   between expand_prologue and expand_epilogue.  */
-
-static int extra_push;
-
-/* Adjust the stack by SIZE bytes.  REG holds the rtl of the register
-  to be adjusted, and TEMP, if nonnegative, holds the register number
-  of a general register that we may clobber.  */
-
-static void
-output_stack_adjust (size, reg, temp)
-     int size;
-     rtx reg;
-     int temp;
-{
-  if (size)
-    {
-      if (CONST_OK_FOR_I (size))
-	emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
-      /* Try to do it with two partial adjustments; however, we must make
-	 sure that the stack is properly aligned at all times, in case
-	 an interrupt occurs between the two partial adjustments. */
-      else if (CONST_OK_FOR_I (size / 2 & -4)
-	       && CONST_OK_FOR_I (size - (size / 2 & -4)))
-	{
-	  emit_insn (gen_addsi3 (reg, reg, GEN_INT (size / 2 & -4)));
-	  emit_insn (gen_addsi3 (reg, reg, GEN_INT (size - (size / 2 & -4))));
-	}
-      else
-	{
-	  rtx const_reg;
-
-	  /* If TEMP is invalid, we could temporarily save a general
-	     register to MACL.  However, there is currently no need
-	     to handle this case, so just abort when we see it.  */
-	  if (temp < 0)
-	    abort ();
-	  const_reg = gen_rtx (REG, SImode, temp);
-
-	  /* If SIZE is negative, subtract the positive value.
-	     This sometimes allows a constant pool entry to be shared
-	     between prologue and epilogue code.  */
-	  if (size < 0)
-	    {
-	      emit_insn (gen_movsi (const_reg, GEN_INT (-size)));
-	      emit_insn (gen_subsi3 (reg, reg, const_reg));
-	    }
-	  else
-	    {
-	      emit_insn (gen_movsi (const_reg, GEN_INT (size)));
-	      emit_insn (gen_addsi3 (reg, reg, const_reg));
-	    }
-	}
-    }
-}
-
-/* Output RTL to push register RN onto the stack.  */
-
-static void
-push (rn)
-     int rn;
-{
-  rtx x;
-  if (rn == FPUL_REG)
-    x = gen_push_fpul ();
-  else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
-	   && rn >= FIRST_FP_REG && rn <= LAST_XD_REG)
-    {
-      if ((rn - FIRST_FP_REG) & 1 && rn <= LAST_FP_REG)
-	return;
-      x = gen_push_4 (gen_rtx (REG, DFmode, rn));
-    }
-  else if (TARGET_SH3E && rn >= FIRST_FP_REG && rn <= LAST_FP_REG)
-    x = gen_push_e (gen_rtx (REG, SFmode, rn));
-  else
-    x = gen_push (gen_rtx (REG, SImode, rn));
-
-  x = emit_insn (x);
-  REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
-			   gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
-}
-
-/* Output RTL to pop register RN from the stack.  */
-
-static void
-pop (rn)
-     int rn;
-{
-  rtx x;
-  if (rn == FPUL_REG)
-    x = gen_pop_fpul ();
-  else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
-	   && rn >= FIRST_FP_REG && rn <= LAST_XD_REG)
-    {
-      if ((rn - FIRST_FP_REG) & 1 && rn <= LAST_FP_REG)
-	return;
-      x = gen_pop_4 (gen_rtx (REG, DFmode, rn));
-    }
-  else if (TARGET_SH3E && rn >= FIRST_FP_REG && rn <= LAST_FP_REG)
-    x = gen_pop_e (gen_rtx (REG, SFmode, rn));
-  else
-    x = gen_pop (gen_rtx (REG, SImode, rn));
-    
-  x = emit_insn (x);
-  REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
-			   gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
-}
-
-/* Generate code to push the regs specified in the mask.  */
-
-static void
-push_regs (mask, mask2)
-     int mask, mask2;
-{
-  int i;
-
-  /* Push PR last; this gives better latencies after the prologue, and
-     candidates for the return delay slot when there are no general
-     registers pushed.  */
-  for (i = 0; i < 32; i++)
-    if (mask & (1 << i) && i != PR_REG)
-      push (i);
-  for (i = 32; i < FIRST_PSEUDO_REGISTER; i++)
-    if (mask2 & (1 << (i - 32)))
-      push (i);
-  if (mask & (1 << PR_REG))
-    push (PR_REG);
-}
-
-/* Work out the registers which need to be saved, both as a mask and a
-   count of saved words.
-
-   If doing a pragma interrupt function, then push all regs used by the
-   function, and if we call another function (we can tell by looking at PR),
-   make sure that all the regs it clobbers are safe too.  */
-
-static int
-calc_live_regs (count_ptr, live_regs_mask2)
-     int *count_ptr;
-     int *live_regs_mask2;
-{
-  int reg;
-  int live_regs_mask = 0;
-  int count;
-  int interrupt_handler;
-
-  if ((lookup_attribute
-       ("interrupt_handler",
-	DECL_MACHINE_ATTRIBUTES (current_function_decl)))
-      != NULL_TREE)
-    interrupt_handler = 1;
-  else
-    interrupt_handler = 0;
-
-  *live_regs_mask2 = 0;
-  /* If we can save a lot of saves by switching to double mode, do that.  */
-  if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
-    for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
-      if (regs_ever_live[reg] && regs_ever_live[reg+1]
-	  && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa))
-	  && ++count > 2)
-	{
-	  target_flags &= ~FPU_SINGLE_BIT;
-	  break;
-	}
-  for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
-    {
-      if ((interrupt_handler && ! pragma_trapa)
-	  ? (/* Need to save all the regs ever live.  */
-	     (regs_ever_live[reg]
-	      || (call_used_regs[reg]
-		  && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
-		  && regs_ever_live[PR_REG]))
-	     && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
-	     && reg != RETURN_ADDRESS_POINTER_REGNUM
-	     && reg != T_REG && reg != GBR_REG && reg != FPSCR_REG)
-	  : (/* Only push those regs which are used and need to be saved.  */
-	     regs_ever_live[reg] && ! call_used_regs[reg]))
-	{
-	  if (reg >= 32)
-	    *live_regs_mask2 |= 1 << (reg - 32);
-	  else
-	    live_regs_mask |= 1 << reg;
-	  count++;
-	  if (TARGET_SH4 && TARGET_FMOVD && reg >= FIRST_FP_REG)
-	    if (reg <= LAST_FP_REG)
-	      {
-		if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
-		  {
-		    if (reg >= 32)
-		      *live_regs_mask2 |= 1 << ((reg ^ 1) - 32);
-		    else
-		      live_regs_mask |= 1 << (reg ^ 1);
-		    count++;
-		  }
-	      }
-	    else if (reg <= LAST_XD_REG)
-	      {
-		/* Must switch to double mode to access these registers.  */
-		target_flags &= ~FPU_SINGLE_BIT;
-		count++;
-	      }
-	}
-    }
-
-  *count_ptr = count;
-  return live_regs_mask;
-}
-
-/* Code to generate prologue and epilogue sequences */
-
-void
-sh_expand_prologue ()
-{
-  int live_regs_mask;
-  int d, i;
-  int live_regs_mask2;
-  int save_flags = target_flags;
-  int double_align = 0;
-
-  /* We have pretend args if we had an object sent partially in registers
-     and partially on the stack, e.g. a large structure.  */
-  output_stack_adjust (-current_function_pretend_args_size,
-		       stack_pointer_rtx, 3);
-
-  extra_push = 0;
-
-  /* This is set by SETUP_VARARGS to indicate that this is a varargs
-     routine.  Clear it here so that the next function isn't affected. */
-  if (current_function_anonymous_args)
-    {
-      current_function_anonymous_args = 0;
-
-      /* This is not used by the SH3E calling convention  */
-      if (!TARGET_SH3E)
-	{
-	  /* Push arg regs as if they'd been provided by caller in stack.  */
-	  for (i = 0; i < NPARM_REGS(SImode); i++)
-	    {
-	      int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
-	      if (i >= (NPARM_REGS(SImode) 
-			- current_function_args_info.arg_count[(int) SH_ARG_INT]
-			))
-		break;
-	      push (rn);
-	      extra_push += 4;
-	    }
-	}
-    }
-
-  /* If we're supposed to switch stacks at function entry, do so now.  */
-  if (sp_switch)
-    emit_insn (gen_sp_switch_1 ());
-
-  live_regs_mask = calc_live_regs (&d, &live_regs_mask2);
-  /* ??? Maybe we could save some switching if we can move a mode switch
-     that already happens to be at the function start into the prologue.  */
-  if (target_flags != save_flags)
-    emit_insn (gen_toggle_sz ());
-  push_regs (live_regs_mask, live_regs_mask2);
-  if (target_flags != save_flags)
-    emit_insn (gen_toggle_sz ());
-
-  if (TARGET_ALIGN_DOUBLE && d & 1)
-    double_align = 4;
-
-  target_flags = save_flags;
-
-  output_stack_adjust (-get_frame_size () - double_align,
-		       stack_pointer_rtx, 3);
-
-  if (frame_pointer_needed)
-    emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
-}
-
-void
-sh_expand_epilogue ()
-{
-  int live_regs_mask;
-  int d, i;
-
-  int live_regs_mask2;
-  int save_flags = target_flags;
-  int frame_size = get_frame_size ();
-
-  live_regs_mask = calc_live_regs (&d, &live_regs_mask2);
-
-  if (TARGET_ALIGN_DOUBLE && d & 1)
-    frame_size += 4;
-
-  if (frame_pointer_needed)
-    {
-      output_stack_adjust (frame_size, frame_pointer_rtx, 7);
-
-      /* We must avoid moving the stack pointer adjustment past code
-	 which reads from the local frame, else an interrupt could
-	 occur after the SP adjustment and clobber data in the local
-	 frame.  */
-      emit_insn (gen_blockage ());
-      emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
-    }
-  else if (frame_size)
-    {
-      /* We must avoid moving the stack pointer adjustment past code
-	 which reads from the local frame, else an interrupt could
-	 occur after the SP adjustment and clobber data in the local
-	 frame.  */
-      emit_insn (gen_blockage ());
-      output_stack_adjust (frame_size, stack_pointer_rtx, 7);
-    }
-
-  /* Pop all the registers.  */
-
-  if (target_flags != save_flags)
-    emit_insn (gen_toggle_sz ());
-  if (live_regs_mask & (1 << PR_REG))
-    pop (PR_REG);
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      int j = (FIRST_PSEUDO_REGISTER - 1) - i;
-      if (j < 32 && (live_regs_mask & (1 << j)) && j != PR_REG)
-	pop (j);
-      else if (j >= 32 && (live_regs_mask2 & (1 << (j - 32))))
-	pop (j);
-    }
-  if (target_flags != save_flags)
-    emit_insn (gen_toggle_sz ());
-  target_flags = save_flags;
-
-  output_stack_adjust (extra_push + current_function_pretend_args_size,
-		       stack_pointer_rtx, 7);
-
-  /* Switch back to the normal stack if necessary.  */
-  if (sp_switch)
-    emit_insn (gen_sp_switch_2 ());
-}
-
-/* Clear variables at function end.  */
-
-void
-function_epilogue (stream, size)
-     FILE *stream;
-     int size;
-{
-  trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
-  sp_switch = NULL_RTX;
-}
-
-rtx
-sh_builtin_saveregs (arglist)
-     tree arglist;
-{
-  tree fntype = TREE_TYPE (current_function_decl);
-  /* First unnamed integer register.  */
-  int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
-  /* Number of integer registers we need to save.  */
-  int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
-  /* First unnamed SFmode float reg */
-  int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
-  /* Number of SFmode float regs to save.  */
-  int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
-  int ptrsize = GET_MODE_SIZE (Pmode);
-  rtx valist, regbuf, fpregs;
-  int bufsize, regno;
-
-  /* Allocate block of memory for the regs. */
-  /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
-     Or can assign_stack_local accept a 0 SIZE argument?  */
-  bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
-
-  regbuf = assign_stack_local (BLKmode, bufsize, 0);
-  MEM_SET_IN_STRUCT_P (regbuf, 1);
-
-  /* Save int args.
-     This is optimized to only save the regs that are necessary.  Explicitly
-     named args need not be saved.  */
-  if (n_intregs > 0)
-    move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
-			 gen_rtx (MEM, BLKmode, 
-			 	plus_constant (XEXP (regbuf, 0),
-					n_floatregs * UNITS_PER_WORD)), 
-			 n_intregs, n_intregs * UNITS_PER_WORD);
-
-  /* Save float args.
-     This is optimized to only save the regs that are necessary.  Explicitly
-     named args need not be saved.
-     We explicitly build a pointer to the buffer because it halves the insn
-     count when not optimizing (otherwise the pointer is built for each reg
-     saved).
-     We emit the moves in reverse order so that we can use predecrement.  */
-
-  fpregs = gen_reg_rtx (Pmode);
-  emit_move_insn (fpregs, XEXP (regbuf, 0));
-  emit_insn (gen_addsi3 (fpregs, fpregs,
-			 GEN_INT (n_floatregs * UNITS_PER_WORD)));
-  if (TARGET_SH4)
-    {
-      for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
-	{
-	  emit_insn (gen_addsi3 (fpregs, fpregs,
-				 GEN_INT (-2 * UNITS_PER_WORD)));
-	  emit_move_insn (gen_rtx (MEM, DFmode, fpregs),
-			  gen_rtx (REG, DFmode, BASE_ARG_REG (DFmode) + regno));
-	}
-      regno = first_floatreg;
-      if (regno & 1)
-	{
-	  emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
-	  emit_move_insn (gen_rtx (MEM, SFmode, fpregs),
-			  gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno
-						- (TARGET_LITTLE_ENDIAN != 0)));
-	}
-    }
-  else
-    for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
-      {
-	emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
-	emit_move_insn (gen_rtx (MEM, SFmode, fpregs),
-			gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno));
-      }
-
-  /* Return the address of the regbuf.  */
-  return XEXP (regbuf, 0);
-}
-
-/* Define the offset between two registers, one to be eliminated, and
-   the other its replacement, at the start of a routine.  */
-
-int
-initial_elimination_offset (from, to)
-     int from;
-     int to;
-{
-  int regs_saved;
-  int total_saved_regs_space;
-  int total_auto_space = get_frame_size ();
-  int save_flags = target_flags;
-
-  int live_regs_mask, live_regs_mask2;
-  live_regs_mask = calc_live_regs (&regs_saved, &live_regs_mask2);
-  if (TARGET_ALIGN_DOUBLE && regs_saved & 1)
-    total_auto_space += 4;
-  target_flags = save_flags;
-
-  total_saved_regs_space = (regs_saved) * 4;
-
-  if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
-    return total_saved_regs_space + total_auto_space;
-
-  if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
-    return total_saved_regs_space + total_auto_space;
-
-  /* Initial gap between fp and sp is 0.  */
-  if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
-    return 0;
-
-  if (from == RETURN_ADDRESS_POINTER_REGNUM
-      && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
-    {
-      int i, n = total_saved_regs_space;
-      for (i = PR_REG-1; i >= 0; i--)
-	if (live_regs_mask & (1 << i))
-	  n -= 4;
-      return n + total_auto_space;
-    }
-
-  abort ();
-}
-
-/* Handle machine specific pragmas to be semi-compatible with Hitachi
-   compiler.  */
-
-int
-sh_handle_pragma (p_getc, p_ungetc, pname)
-     int (*  p_getc)   PROTO((void));
-     void (* p_ungetc) PROTO((int));
-     char *  pname;
-{
-  int retval = 0;
-
-  if (strcmp (pname, "interrupt") == 0)
-    pragma_interrupt = retval = 1;
-  else if (strcmp (pname, "trapa") == 0)
-    pragma_interrupt = pragma_trapa = retval = 1;
-  else if (strcmp (pname, "nosave_low_regs") == 0)
-    pragma_nosave_low_regs = retval = 1;
-
-  return retval;
-}
-
-/* Generate 'handle_interrupt' attribute for decls */
-
-void
-sh_pragma_insert_attributes (node, attributes, prefix)
-     tree node;
-     tree * attributes;
-     tree * prefix;
-{
-  tree a;
-
-  if (! pragma_interrupt
-      || TREE_CODE (node) != FUNCTION_DECL)
-    return;
-
-  /* We are only interested in fields.  */
-  if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd')
-    return;
-
-  /* Add a 'handle_interrupt' attribute.  */
-  * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes);
-
-  return;
-}
-
-/* Return nonzero if ATTR is a valid attribute for DECL.
-   ATTRIBUTES are any existing attributes and ARGS are the arguments
-   supplied with ATTR.
-
-   Supported attributes:
-
-   interrupt_handler -- specifies this function is an interrupt handler.
-
-   sp_switch -- specifies an alternate stack for an interrupt handler
-   to run on.
-
-   trap_exit -- use a trapa to exit an interrupt function instead of
-   an rte instruction.  */
-
-int
-sh_valid_machine_decl_attribute (decl, attributes, attr, args)
-     tree decl;
-     tree attributes;
-     tree attr;
-     tree args;
-{
-  int retval = 0;
-
-  if (TREE_CODE (decl) != FUNCTION_DECL)
-    return 0;
-
-  if (is_attribute_p ("interrupt_handler", attr))
-    {
-      return 1;
-    }
-
-  if (is_attribute_p ("sp_switch", attr))
-    {
-      /* The sp_switch attribute only has meaning for interrupt functions.  */
-      if (!pragma_interrupt)
-	return 0;
-
-      /* sp_switch must have an argument.  */
-      if (!args || TREE_CODE (args) != TREE_LIST)
-	return 0;
-
-      /* The argument must be a constant string.  */
-      if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
-	return 0;
-
-      sp_switch = gen_rtx (SYMBOL_REF, VOIDmode,
-			   TREE_STRING_POINTER (TREE_VALUE (args)));
-      return 1;
-    }
-
-  if (is_attribute_p ("trap_exit", attr))
-    {
-      /* The trap_exit attribute only has meaning for interrupt functions.  */
-      if (!pragma_interrupt)
-	return 0;
-
-      /* trap_exit must have an argument.  */
-      if (!args || TREE_CODE (args) != TREE_LIST)
-	return 0;
-
-      /* The argument must be a constant integer.  */
-      if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
-	return 0;
-
-      trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
-      return 1;
-    }
-}
-
-
-/* Predicates used by the templates.  */
-
-/* Returns 1 if OP is MACL, MACH or PR.  The input must be a REG rtx.
-   Used only in general_movsrc_operand.  */
-
-int
-system_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  switch (REGNO (op))
-    {
-    case PR_REG:
-    case MACL_REG:
-    case MACH_REG:
-      return 1;
-    }
-  return 0;
-}
-
-/* Returns 1 if OP can be source of a simple move operation.
-   Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
-   invalid as are subregs of system registers.  */
-
-int
-general_movsrc_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == MEM)
-    {
-      rtx inside = XEXP (op, 0);
-      if (GET_CODE (inside) == CONST)
-	inside = XEXP (inside, 0);
-
-      if (GET_CODE (inside) == LABEL_REF)
-	return 1;
-
-      if (GET_CODE (inside) == PLUS
-	  && GET_CODE (XEXP (inside, 0)) == LABEL_REF
-	  && GET_CODE (XEXP (inside, 1)) == CONST_INT)
-	return 1;
-
-      /* Only post inc allowed.  */
-      if (GET_CODE (inside) == PRE_DEC)
-	return 0;
-    }
-
-  if ((mode == QImode || mode == HImode)
-      && (GET_CODE (op) == SUBREG
-	  && GET_CODE (XEXP (op, 0)) == REG
-	  && system_reg_operand (XEXP (op, 0), mode)))
-    return 0;
-
-  return general_operand (op, mode);
-}
-
-/* Returns 1 if OP can be a destination of a move.
-   Same as general_operand, but no preinc allowed.  */
-
-int
-general_movdst_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  /* Only pre dec allowed.  */
-  if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
-    return 0;
-
-  return general_operand (op, mode);
-}
-
-/* Returns 1 if OP is a normal arithmetic register.  */
-
-int
-arith_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (register_operand (op, mode))
-    {
-      int regno;
-
-      if (GET_CODE (op) == REG)
-	regno = REGNO (op);
-      else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
-	regno = REGNO (SUBREG_REG (op));
-      else
-	return 1;
-
-      return (regno != T_REG && regno != PR_REG
-	      && (regno != FPUL_REG || TARGET_SH4)
-	      && regno != MACH_REG && regno != MACL_REG);
-    }
-  return 0;
-}
-
-int
-fp_arith_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (register_operand (op, mode))
-    {
-      int regno;
-
-      if (GET_CODE (op) == REG)
-	regno = REGNO (op);
-      else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
-	regno = REGNO (SUBREG_REG (op));
-      else
-	return 1;
-
-      return (regno != T_REG && regno != PR_REG && regno > 15
-	      && regno != MACH_REG && regno != MACL_REG);
-    }
-  return 0;
-}
-
-int
-fp_extended_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == FLOAT_EXTEND && GET_MODE (op) == mode)
-    {
-      op = XEXP (op, 0);
-      mode = GET_MODE (op);
-    }
-  return fp_arith_reg_operand (op, mode);
-}
-
-/* Returns 1 if OP is a valid source operand for an arithmetic insn.  */
-
-int
-arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (arith_reg_operand (op, mode))
-    return 1;
-
-  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
-    return 1;
-
-  return 0;
-}
-
-/* Returns 1 if OP is a valid source operand for a compare insn.  */
-
-int
-arith_reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (arith_reg_operand (op, mode))
-    return 1;
-
-  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_N (INTVAL (op)))
-    return 1;
-
-  return 0;
-}
-
-/* Returns 1 if OP is a valid source operand for a logical operation.  */
-
-int
-logical_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (arith_reg_operand (op, mode))
-    return 1;
-
-  if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
-    return 1;
-
-  return 0;
-}
-
-/* Nonzero if OP is a floating point value with value 0.0.  */
-
-int
-fp_zero_operand (op)
-     rtx op;
-{
-  REAL_VALUE_TYPE r;
-
-  if (GET_MODE (op) != SFmode)
-    return 0;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-  return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
-}
-
-/* Nonzero if OP is a floating point value with value 1.0.  */
-
-int
-fp_one_operand (op)
-     rtx op;
-{
-  REAL_VALUE_TYPE r;
-
-  if (GET_MODE (op) != SFmode)
-    return 0;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-  return REAL_VALUES_EQUAL (r, dconst1);
-}
-
-int
-tertiary_reload_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  enum rtx_code code = GET_CODE (op);
-  return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
-}
-
-int
-fpscr_operand (op)
-     rtx op;
-{
-  return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG
-	  && GET_MODE (op) == PSImode);
-}
-
-int
-commutative_float_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_MODE (op) != mode)
-    return 0;
-  switch (GET_CODE (op))
-    {
-    case PLUS:
-    case MULT:
-      return 1;
-    }
-  return 0;
-}
-
-int
-noncommutative_float_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_MODE (op) != mode)
-    return 0;
-  switch (GET_CODE (op))
-    {
-    case MINUS:
-    case DIV:
-      return 1;
-    }
-  return 0;
-}
-
-int
-binary_float_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_MODE (op) != mode)
-    return 0;
-  switch (GET_CODE (op))
-    {
-    case PLUS:
-    case MINUS:
-    case MULT:
-    case DIV:
-      return 1;
-    }
-  return 0;
-}
-
-/* Return the destination address of a branch.  */
-   
-int
-branch_dest (branch)
-     rtx branch;
-{
-  rtx dest = SET_SRC (PATTERN (branch));
-  int dest_uid;
-
-  if (GET_CODE (dest) == IF_THEN_ELSE)
-    dest = XEXP (dest, 1);
-  dest = XEXP (dest, 0);
-  dest_uid = INSN_UID (dest);
-  return insn_addresses[dest_uid];
-}
-
-/* Return non-zero if REG is not used after INSN.
-   We assume REG is a reload reg, and therefore does
-   not live past labels.  It may live past calls or jumps though.  */
-int
-reg_unused_after (reg, insn)
-     rtx reg;
-     rtx insn;
-{
-  enum rtx_code code;
-  rtx set;
-
-  /* If the reg is set by this instruction, then it is safe for our
-     case.  Disregard the case where this is a store to memory, since
-     we are checking a register used in the store address.  */
-  set = single_set (insn);
-  if (set && GET_CODE (SET_DEST (set)) != MEM
-      && reg_overlap_mentioned_p (reg, SET_DEST (set)))
-    return 1;
-
-  while (insn = NEXT_INSN (insn))
-    {
-      code = GET_CODE (insn);
-
-#if 0
-      /* If this is a label that existed before reload, then the register
-	 if dead here.  However, if this is a label added by reorg, then
-	 the register may still be live here.  We can't tell the difference,
-	 so we just ignore labels completely.  */
-      if (code == CODE_LABEL)
-	return 1;
-      /* else */
-#endif
-
-      if (code == JUMP_INSN)
-	return 0;
-
-      /* If this is a sequence, we must handle them all at once.
-	 We could have for instance a call that sets the target register,
-	 and a insn in a delay slot that uses the register.  In this case,
-	 we must return 0.  */
-      else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
-	{
-	  int i;
-	  int retval = 0;
-
-	  for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
-	    {
-	      rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
-	      rtx set = single_set (this_insn);
-
-	      if (GET_CODE (this_insn) == CALL_INSN)
-		code = CALL_INSN;
-	      else if (GET_CODE (this_insn) == JUMP_INSN)
-		{
-		  if (INSN_ANNULLED_BRANCH_P (this_insn))
-		    return 0;
-		  code = JUMP_INSN;
-		}
-
-	      if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
-		return 0;
-	      if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
-		{
-		  if (GET_CODE (SET_DEST (set)) != MEM)
-		    retval = 1;
-		  else
-		    return 0;
-		}
-	      if (set == 0
-		  && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
-		return 0;
-	    }
-	  if (retval == 1)
-	    return 1;
-	  else if (code == JUMP_INSN)
-	    return 0;
-	}
-      else if (GET_RTX_CLASS (code) == 'i')
-	{
-	  rtx set = single_set (insn);
-
-	  if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
-	    return 0;
-	  if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
-	    return GET_CODE (SET_DEST (set)) != MEM;
-	  if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
-	    return 0;
-	}
-
-      if (code == CALL_INSN && call_used_regs[REGNO (reg)])
-	return 1;
-    }
-  return 1;
-}
-
-extern struct obstack permanent_obstack;
-
-rtx
-get_fpscr_rtx ()
-{
-  static rtx fpscr_rtx;
-
-  if (! fpscr_rtx)
-    {
-      push_obstacks (&permanent_obstack, &permanent_obstack);
-      fpscr_rtx = gen_rtx (REG, PSImode, 48);
-      REG_USERVAR_P (fpscr_rtx) = 1;
-      pop_obstacks ();
-      mark_user_reg (fpscr_rtx);
-    }
-  if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
-    mark_user_reg (fpscr_rtx);
-  return fpscr_rtx;
-}
-
-void
-emit_sf_insn (pat)
-     rtx pat;
-{
-  rtx addr;
-  /* When generating reload insns,  we must not create new registers.  FPSCR
-     should already have the correct value, so do nothing to change it.  */
-  if (! TARGET_FPU_SINGLE && ! reload_in_progress)
-    {
-      addr = gen_reg_rtx (SImode);
-      emit_insn (gen_fpu_switch0 (addr));
-    }
-  emit_insn (pat);
-  if (! TARGET_FPU_SINGLE && ! reload_in_progress)
-    {
-      addr = gen_reg_rtx (SImode);
-      emit_insn (gen_fpu_switch1 (addr));
-    }
-}
-
-void
-emit_df_insn (pat)
-     rtx pat;
-{
-  rtx addr;
-  if (TARGET_FPU_SINGLE && ! reload_in_progress)
-    {
-      addr = gen_reg_rtx (SImode);
-      emit_insn (gen_fpu_switch0 (addr));
-    }
-  emit_insn (pat);
-  if (TARGET_FPU_SINGLE && ! reload_in_progress)
-    {
-      addr = gen_reg_rtx (SImode);
-      emit_insn (gen_fpu_switch1 (addr));
-    }
-}
-
-void
-expand_sf_unop (fun, operands)
-     rtx (*fun)();
-     rtx *operands;
-{
-  emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
-}
-
-void
-expand_sf_binop (fun, operands)
-     rtx (*fun)();
-     rtx *operands;
-{
-  emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
-			 get_fpscr_rtx ()));
-}
-
-void
-expand_df_unop (fun, operands)
-     rtx (*fun)();
-     rtx *operands;
-{
-  emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
-}
-
-void
-expand_df_binop (fun, operands)
-     rtx (*fun)();
-     rtx *operands;
-{
-  emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
-			 get_fpscr_rtx ()));
-}
-
-void
-expand_fp_branch (compare, branch)
-     rtx (*compare) (), (*branch) ();
-{
-  (GET_MODE (sh_compare_op0)  == SFmode ? emit_sf_insn : emit_df_insn)
-    ((*compare) ());
-  emit_jump_insn ((*branch) ());
-}
-
-/* We don't want to make fpscr call-saved, because that would prevent
-   channging it, and it would also cost an exstra instruction to save it.
-   We don't want it to be known as a global register either, because
-   that disables all flow analysis.  But it has to be live at the function
-   return.  Thus, we need to insert a USE at the end of the function.  */
-/* This should best be called at about the time FINALIZE_PIC is called,
-   but not dependent on flag_pic.  Alas, there is no suitable hook there,
-   so this gets called from HAVE_RETURN.  */
-int
-emit_fpscr_use ()
-{
-  static int fpscr_uses = 0;
-
-  if (rtx_equal_function_value_matters)
-    {
-      emit_insn (gen_rtx (USE, VOIDmode, get_fpscr_rtx ()));
-      fpscr_uses++;
-    }
-  else
-    {
-      if (fpscr_uses > 1)
-	{
-	  /* Due to he crude way we emit the USEs, we might end up with
-	     some extra ones.  Delete all but the last one.  */
-	  rtx insn;
-
-	  for (insn = get_last_insn(); insn; insn = PREV_INSN (insn))
-	    if (GET_CODE (insn) == INSN
-		&& GET_CODE (PATTERN (insn)) == USE
-		&& GET_CODE (XEXP (PATTERN (insn), 0)) == REG
-		&& REGNO (XEXP (PATTERN (insn), 0)) == FPSCR_REG)
-	      {
-		insn = PREV_INSN (insn);
-		break;
-	      }
-	  for (; insn; insn = PREV_INSN (insn))
-	    if (GET_CODE (insn) == INSN
-		&& GET_CODE (PATTERN (insn)) == USE
-		&& GET_CODE (XEXP (PATTERN (insn), 0)) == REG
-		&& REGNO (XEXP (PATTERN (insn), 0)) == FPSCR_REG)
-	      {
-		PUT_CODE (insn, NOTE);
-		NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
-		NOTE_SOURCE_FILE (insn) = 0;
-	      }
-	}
-      fpscr_uses = 0;
-    }
-}
-
-/* ??? gcc does flow analysis strictly after common subexpression
-   elimination.  As a result, common subespression elimination fails
-   when there are some intervening statements setting the same register.
-   If we did nothing about this, this would hurt the precision switching
-   for SH4 badly.  There is some cse after reload, but it is unable to
-   undo the extra register pressure from the unused instructions, and
-   it cannot remove auto-increment loads.
-
-   A C code example that shows this flow/cse weakness for (at least) SH
-   and sparc (as of gcc ss-970706) is this:
-
-double
-f(double a)
-{
-  double d;
-  d = 0.1;
-  a += d;
-  d = 1.1;
-  d = 0.1;
-  a *= d;
-  return a;
-}
-
-   So we add another pass before common subexpression elimination, to
-   remove assignments that are dead due to a following assignment in the
-   same basic block.  */
-
-int sh_flag_remove_dead_before_cse;
-
-static void 
-mark_use (x, reg_set_block)
-     rtx x, *reg_set_block;
-{
-  enum rtx_code code;
-
-  if (! x)
-    return;
-  code = GET_CODE (x);
-  switch (code)
-    {
-    case REG:
-      {
-	int regno = REGNO (x);
-	int nregs = (regno < FIRST_PSEUDO_REGISTER
-		     ? HARD_REGNO_NREGS (regno, GET_MODE (x))
-		     : 1);
-	do
-	  {
-	    reg_set_block[regno + nregs - 1] = 0;
-	  }
-	while (--nregs);
-	break;
-      }
-    case SET:
-      {
-	rtx dest = SET_DEST (x);
-
-	if (GET_CODE (dest) == SUBREG)
-	  dest = SUBREG_REG (dest);
-	if (GET_CODE (dest) != REG)
-	  mark_use (dest, reg_set_block);
-	mark_use (SET_SRC (x), reg_set_block);
-	break;
-      }
-    case CLOBBER:
-      break;
-    default:
-      {
-	char *fmt = GET_RTX_FORMAT (code);
-	int i, j;
-	for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
-	  {
-	    if (fmt[i] == 'e')
-	      mark_use (XEXP (x, i), reg_set_block);
-	    else if (fmt[i] == 'E')
-	      for (j = XVECLEN (x, i) - 1; j >= 0; j--)
-		mark_use (XVECEXP (x, i, j), reg_set_block);
-	  }
-	break;
-      }
-    }
-}
-
-int
-remove_dead_before_cse ()
-{
-  rtx *reg_set_block, last, last_call, insn, set;
-  int in_libcall = 0;
-
-  /* This pass should run just once, after rtl generation.  */
-
-  if (! sh_flag_remove_dead_before_cse
-      || rtx_equal_function_value_matters
-      || reload_completed)
-    return;
-
-  sh_flag_remove_dead_before_cse = 0;
-
-  reg_set_block = (rtx *)alloca (max_reg_num () * sizeof (rtx));
-  bzero ((char *)reg_set_block, max_reg_num () * sizeof (rtx));
-  last_call = last = get_last_insn ();
-  for (insn = last; insn; insn = PREV_INSN (insn))
-    {
-      if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
-	continue;
-      if (GET_CODE (insn) == JUMP_INSN)
-	{
-	  last_call = last = insn;
-	  continue;
-	}
-      set = single_set (insn);
-
-      /* Don't delete parts of libcalls, since that would confuse cse, loop
-	 and flow.  */
-      if (find_reg_note (insn, REG_RETVAL, NULL_RTX))
-	in_libcall = 1;
-      else if (in_libcall)
-	{
-	  if (find_reg_note (insn, REG_LIBCALL, NULL_RTX))
-	    in_libcall = 0;
-	}
-      else if (set && GET_CODE (SET_DEST (set)) == REG)
-	{
-	  int regno = REGNO (SET_DEST (set));
-	  rtx ref_insn = (regno < FIRST_PSEUDO_REGISTER && call_used_regs[regno]
-			  ? last_call
-			  : last);
-	  if (reg_set_block[regno] == ref_insn
-	      && (regno >= FIRST_PSEUDO_REGISTER
-		  || HARD_REGNO_NREGS (regno, GET_MODE (SET_DEST (set))) == 1)
-	      && (GET_CODE (insn) != CALL_INSN || CONST_CALL_P (insn)))
-	    {
-	      PUT_CODE (insn, NOTE);
-	      NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
-	      NOTE_SOURCE_FILE (insn) = 0;
-	      continue;
-	    }
-	  else
-	    reg_set_block[REGNO (SET_DEST (set))] = ref_insn;
-	}
-      if (GET_CODE (insn) == CALL_INSN)
-	{
-	  last_call = insn;
-	  mark_use (CALL_INSN_FUNCTION_USAGE (insn), reg_set_block);
-	}
-      mark_use (PATTERN (insn), reg_set_block);
-    }
-  return 0;
-}
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
deleted file mode 100755
index eff316a..0000000
--- a/gcc/config/sh/sh.h
+++ /dev/null
@@ -1,2232 +0,0 @@
-/* Definitions of target machine for GNU compiler for Hitachi Super-H.
-   Copyright (C) 1993-1998 Free Software Foundation, Inc.
-   Contributed by Steve Chamberlain (sac@cygnus.com).
-   Improved by Jim Wilson (wilson@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#define TARGET_VERSION \
-  fputs (" (Hitachi SH)", stderr);
-
-/* Unfortunately, insn-attrtab.c doesn't include insn-codes.h.  We can't
-  include it here, because hconfig.h is also included by gencodes.c .  */
-extern int code_for_indirect_jump_scratch;
-
-/* Generate SDB debugging information.  */
-
-#define SDB_DEBUGGING_INFO
-
-/* Output DBX (stabs) debugging information if doing -gstabs.  */
-
-#include "dbxcoff.h"
-
-#define SDB_DELIM ";"
-
-#define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__} \
-%{m1:-D__sh1__} \
-%{m2:-D__sh2__} \
-%{m3:-D__sh3__} \
-%{m3e:-D__SH3E__} \
-%{m4-single-only:-D__SH4_SINGLE_ONLY__} \
-%{m4-single:-D__SH4_SINGLE__} \
-%{m4:-D__SH4__} \
-%{!m1:%{!m2:%{!m3:%{!m3e:%{!m4:%{!m4-single:%{!m4-single-only:-D__sh1__}}}}}}}"
-
-#define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
-
-#define ASM_SPEC  "%{ml:-little} %{mrelax:-relax}"
-
-#define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}"
-
-/* We can not debug without a frame pointer.  */
-/* #define CAN_DEBUG_WITHOUT_FP */
-
-#define CONDITIONAL_REGISTER_USAGE					\
-  if (! TARGET_SH4 || ! TARGET_FMOVD)					\
-    {									\
-      int regno;							\
-      for (regno = FIRST_XD_REG; regno <= LAST_XD_REG; regno++)		\
-	fixed_regs[regno] = call_used_regs[regno] = 1;			\
-      if (! TARGET_SH4)							\
-	{								\
-	  if (! TARGET_SH3E)						\
-	    {								\
-	      int regno;						\
-	      for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++)	\
-		fixed_regs[regno] = call_used_regs[regno] = 1;		\
-	      fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1;	\
-	    }								\
-	}								\
-    }									\
-  /* Hitachi saves and restores mac registers on call.  */		\
-  if (TARGET_HITACHI)							\
-    {									\
-      call_used_regs[MACH_REG] = 0;					\
-      call_used_regs[MACL_REG] = 0;					\
-    }
-
-/* ??? Need to write documentation for all SH options and add it to the
-   invoke.texi file.  */
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-#define ISIZE_BIT      	(1<<1)
-#define DALIGN_BIT     	(1<<6)
-#define SH1_BIT	       	(1<<8)
-#define SH2_BIT	       	(1<<9)
-#define SH3_BIT	       	(1<<10)
-#define SH3E_BIT	(1<<11)
-#define HARD_SH4_BIT	(1<<5)
-#define FPU_SINGLE_BIT	(1<<7)
-#define SH4_BIT	       	(1<<12)
-#define FMOVD_BIT	(1<<4)
-#define SPACE_BIT 	(1<<13)
-#define BIGTABLE_BIT  	(1<<14)
-#define RELAX_BIT	(1<<15)
-#define HITACHI_BIT     (1<<22)
-#define PADSTRUCT_BIT  (1<<28)
-#define LITTLE_ENDIAN_BIT (1<<29)
-#define IEEE_BIT (1<<30)
-
-/* Nonzero if we should dump out instruction size info.  */
-#define TARGET_DUMPISIZE  (target_flags & ISIZE_BIT)
-
-/* Nonzero to align doubles on 64 bit boundaries.  */
-#define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
-
-/* Nonzero if we should generate code using type 1 insns.  */
-#define TARGET_SH1 (target_flags & SH1_BIT)
-
-/* Nonzero if we should generate code using type 2 insns.  */
-#define TARGET_SH2 (target_flags & SH2_BIT)
-
-/* Nonzero if we should generate code using type 3 insns.  */
-#define TARGET_SH3 (target_flags & SH3_BIT)
-
-/* Nonzero if we should generate code using type 3E insns.  */
-#define TARGET_SH3E (target_flags & SH3E_BIT)
-
-/* Nonzero if the cache line size is 32. */
-#define TARGET_CACHE32 (target_flags & HARD_SH4_BIT)
-
-/* Nonzero if we schedule for a superscalar implementation. */
-#define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
-
-/* Nonzero if the target has separate instruction and data caches.  */
-#define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
-
-/* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.)  */
-#define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
-
-/* Nonzero if the default precision of th FPU is single */
-#define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
-
-/* Nonzero if we should generate code using type 4 insns.  */
-#define TARGET_SH4 (target_flags & SH4_BIT)
-
-/* Nonzero if we should generate fmovd.  */
-#define TARGET_FMOVD (target_flags & FMOVD_BIT)
-
-/* Nonzero if we respect NANs.  */
-#define TARGET_IEEE (target_flags & IEEE_BIT)
-
-/* Nonzero if we should generate smaller code rather than faster code.  */
-#define TARGET_SMALLCODE   (target_flags & SPACE_BIT)
-
-/* Nonzero to use long jump tables.  */
-#define TARGET_BIGTABLE     (target_flags & BIGTABLE_BIT)
-
-/* Nonzero to generate pseudo-ops needed by the assembler and linker
-   to do function call relaxing.  */
-#define TARGET_RELAX (target_flags & RELAX_BIT)
-
-/* Nonzero if using Hitachi's calling convention.  */
-#define TARGET_HITACHI 		(target_flags & HITACHI_BIT)
-
-/* Nonzero if padding structures to a multiple of 4 bytes.  This is
-   incompatible with Hitachi's compiler, and gives unusual structure layouts
-   which confuse programmers.
-   ??? This option is not useful, but is retained in case there are people
-   who are still relying on it.  It may be deleted in the future.  */
-#define TARGET_PADSTRUCT       (target_flags & PADSTRUCT_BIT)
-
-/* Nonzero if generating code for a little endian SH.  */
-#define TARGET_LITTLE_ENDIAN     (target_flags & LITTLE_ENDIAN_BIT)
-
-#define TARGET_SWITCHES  			\
-{ {"1",	        SH1_BIT},			\
-  {"2",	        SH2_BIT},			\
-  {"3",	        SH3_BIT|SH2_BIT},		\
-  {"3e",	SH3E_BIT|SH3_BIT|SH2_BIT|FPU_SINGLE_BIT},	\
-  {"4-single-only",	SH3E_BIT|SH3_BIT|SH2_BIT|SH3E_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT},	\
-  {"4-single",	SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT},\
-  {"4",	        SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|HARD_SH4_BIT},	\
-  {"b",		-LITTLE_ENDIAN_BIT},  		\
-  {"bigtable", 	BIGTABLE_BIT},			\
-  {"dalign",  	DALIGN_BIT},			\
-  {"fmovd",  	FMOVD_BIT},			\
-  {"hitachi",	HITACHI_BIT},			\
-  {"ieee",  	IEEE_BIT},			\
-  {"isize", 	ISIZE_BIT},			\
-  {"l",		LITTLE_ENDIAN_BIT},  		\
-  {"no-ieee",  	-IEEE_BIT},			\
-  {"padstruct", PADSTRUCT_BIT},    		\
-  {"relax",	RELAX_BIT},			\
-  {"space", 	SPACE_BIT},			\
-  SUBTARGET_SWITCHES                            \
-  {"",   	TARGET_DEFAULT} 		\
-}
-
-/* This are meant to be redefined in the host dependent files */
-#define SUBTARGET_SWITCHES
-
-#define TARGET_DEFAULT  (0)
-
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)				\
-do {									\
-  if (LEVEL)								\
-    flag_omit_frame_pointer = -1;					\
-  if (LEVEL)								\
-    sh_flag_remove_dead_before_cse = 1;					\
-  if (SIZE)								\
-    target_flags |= SPACE_BIT;						\
-} while (0)
-
-#define ASSEMBLER_DIALECT assembler_dialect
-
-extern int assembler_dialect;
-
-#define OVERRIDE_OPTIONS 						\
-do {									\
-  sh_cpu = CPU_SH1;							\
-  assembler_dialect = 0;						\
-  if (TARGET_SH2)							\
-    sh_cpu = CPU_SH2;							\
-  if (TARGET_SH3)							\
-    sh_cpu = CPU_SH3;							\
-  if (TARGET_SH3E)							\
-    sh_cpu = CPU_SH3E;							\
-  if (TARGET_SH4)							\
-    {									\
-      assembler_dialect = 1;						\
-      sh_cpu = CPU_SH4;							\
-    }									\
-  if (! TARGET_SH4 || ! TARGET_FMOVD)					\
-    {									\
-      /* Prevent usage of explicit register names for variables		\
-	 for registers not present / not addressable in the		\
-	 target architecture.  */					\
-      int regno;							\
-      for (regno = (TARGET_SH3E) ? 17 : 0; 				\
-	   regno <= 24; regno++)					\
-	fp_reg_names[regno][0] = 0;					\
-    }									\
-  if (flag_omit_frame_pointer < 0)					\
-   /* The debugging information is sufficient,				\
-      but gdb doesn't implement this yet */				\
-   if (0)								\
-    flag_omit_frame_pointer						\
-      = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG			\
-	 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);			\
-   else									\
-    flag_omit_frame_pointer = 0;					\
-									\
-  /* Never run scheduling before reload, since that can			\
-     break global alloc, and generates slower code anyway due		\
-     to the pressure on R0.  */						\
-  flag_schedule_insns = 0;						\
-  sh_addr_diff_vec_mode = TARGET_BIGTABLE ? SImode : HImode;		\
-} while (0)
-
-/* Target machine storage layout.  */
-
-/* Define to use software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion.  */
-#define REAL_ARITHMETIC
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.  */
-
-#define BITS_BIG_ENDIAN  0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.  */
-#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
-
-/* Define this to set the endianness to use in libgcc2.c, which can
-   not depend on target_flags.  */
-#if defined(__LITTLE_ENDIAN__)
-#define LIBGCC2_WORDS_BIG_ENDIAN 0
-#else
-#define LIBGCC2_WORDS_BIG_ENDIAN 1
-#endif
-
-/* Number of bits in an addressable storage unit.  */
-#define BITS_PER_UNIT  8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD  32
-#define MAX_BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD	4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE  32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY  	32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY  BIGGEST_ALIGNMENT
-
-/* The log (base 2) of the cache line size, in bytes.  Processors prior to
-   SH3 have no actual cache, but they fetch code in chunks of 4 bytes.  */
-#define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH3 ? 4 : 2)
-
-/* Allocation boundary (in *bits*) for the code of a function.
-   32 bit alignment is faster, because instructions are always fetched as a
-   pair from a longword boundary.  */
-#define FUNCTION_BOUNDARY  (TARGET_SMALLCODE ? 16 : (1 << CACHE_LOG) * 8)
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY  32
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT  (TARGET_ALIGN_DOUBLE ? 64 : 32)
-
-/* The best alignment to use in cases where we have a choice.  */
-#define FASTEST_ALIGNMENT 32
-
-/* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)	\
-  ((TREE_CODE (EXP) == STRING_CST	\
-    && (ALIGN) < FASTEST_ALIGNMENT)	\
-    ? FASTEST_ALIGNMENT : (ALIGN))
-
-#ifndef MAX_OFILE_ALIGNMENT
-#define MAX_OFILE_ALIGNMENT 128
-#endif
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Number of bits which any structure or union's size must be a
-   multiple of.  Each structure or union's size is rounded up to a
-   multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm.  */
-#define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
-  barrier_align (LABEL_AFTER_BARRIER)
-
-#define LOOP_ALIGN(A_LABEL) \
-  ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
-   ? 0 : sh_loop_align (A_LABEL))
-
-#define LABEL_ALIGN(A_LABEL) \
-(									\
-  (PREV_INSN (A_LABEL)							\
-   && GET_CODE (PREV_INSN (A_LABEL)) == INSN				\
-   && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE	\
-   && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == 1)			\
-   /* explicit alignment insn in constant tables. */			\
-  ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0))		\
-  : 0)
-
-/* Jump tables must be 32 bit aligned, no matter the size of the element.  */
-#define ADDR_VEC_ALIGN(ADDR_VEC) 2
-
-/* The base two logarithm of the known minimum alignment of an insn length.  */
-#define INSN_LENGTH_ALIGNMENT(A_INSN)					\
-  (GET_CODE (A_INSN) == INSN						\
-   ? 1									\
-   : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN	\
-   ? 1									\
-   : CACHE_LOG)
-
-/* Standard register usage.  */
-
-/* Register allocation for the Hitachi calling convention:
-
-        r0		arg return
-	r1..r3          scratch
-	r4..r7		args in
-	r8..r13		call saved
-	r14		frame pointer/call saved
-	r15		stack pointer
-	ap		arg pointer (doesn't really exist, always eliminated)
-	pr		subroutine return address
-	t               t bit
-	mach		multiply/accumulate result, high part
-	macl		multiply/accumulate result, low part.
-	fpul		fp/int communication register
-	rap		return address pointer register
-	fr0		fp arg return
-	fr1..fr3	scratch floating point registers
-	fr4..fr11	fp args in
-	fr12..fr15	call saved floating point registers  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  */
-
-#define AP_REG   16
-#define PR_REG   17
-#define T_REG    18
-#define GBR_REG  19
-#define MACH_REG 20
-#define MACL_REG 21
-#define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
-#define FPUL_REG 22
-#define RAP_REG 23
-#define FIRST_FP_REG 24
-#define LAST_FP_REG 39
-#define FIRST_XD_REG 40
-#define LAST_XD_REG 47
-#define FPSCR_REG 48
-
-#define FIRST_PSEUDO_REGISTER 49
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   Mach register is fixed 'cause it's only 10 bits wide for SH1.
-   It is 32 bits wide for SH2.  */
-
-#define FIXED_REGISTERS  	\
-  { 0,  0,  0,  0, 		\
-    0,  0,  0,  0, 		\
-    0,  0,  0,  0, 		\
-    0,  0,  0,  1, 		\
-    1,  1,  1,  1, 		\
-    1,  1,  0,  1,		\
-    0,  0,  0,  0,		\
-    0,  0,  0,  0,		\
-    0,  0,  0,  0,		\
-    0,  0,  0,  0,		\
-    0,  0,  0,  0,		\
-    0,  0,  0,  0,		\
-    1,				\
-}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-
-#define CALL_USED_REGISTERS 	\
-  { 1,  1,  1,  1,		\
-    1,  1,  1,  1, 		\
-    0,  0,  0,  0,		\
-    0,  0,  0,  1,		\
-    1,  0,  1,  1,		\
-    1,  1,  1,  1,		\
-    1,  1,  1,  1,		\
-    1,  1,  1,  1,		\
-    1,  1,  1,  1,		\
-    0,  0,  0,  0,		\
-    1,  1,  1,  1,		\
-    1,  1,  0,  0,		\
-    1,				\
-}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On the SH all but the XD regs are UNITS_PER_WORD bits wide.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE) \
-   ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \
-    ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
-    : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   We can allow any mode in any general register.  The special registers
-   only allow SImode.  Don't allow any mode in the PR.  */
-
-/* We cannot hold DCmode values in the XD registers because alter_reg
-   handles subregs of them incorrectly.  We could work around this by
-   spacing the XD registers like the DR registers, but this would require
-   additional memory in every compilation to hold larger register vectors.
-   We could hold SFmode / SCmode values in XD registers, but that
-   would require a tertiary reload when reloading from / to memory,
-   and a secondary reload to reload from / to general regs; that
-   seems to be a loosing proposition.  */
-#define HARD_REGNO_MODE_OK(REGNO, MODE)		\
-  (SPECIAL_REG (REGNO) ? (MODE) == SImode	\
-   : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode	\
-   : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG && (MODE) == SFmode \
-   ? 1 \
-   : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG \
-   ? ((MODE) == SFmode \
-      || (TARGET_SH3E && (MODE) == SCmode) \
-      || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode) \
-	  && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
-   : (REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \
-   ? (MODE) == DFmode \
-   : (REGNO) == PR_REG ? 0			\
-   : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
-   : 1)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* Define this if the program counter is overloaded on a register.  */
-/* #define PC_REGNUM		15*/
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM	15
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM	14
-
-/* Fake register that holds the address on the stack of the
-   current function's return address.  */
-#define RETURN_ADDRESS_POINTER_REGNUM 23
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms may be accessed
-   via the stack pointer) in functions that seem suitable.  */
-
-#define FRAME_POINTER_REQUIRED	0
-
-/* Definitions for register eliminations.
-
-   We have three registers that can be eliminated on the SH.  First, the
-   frame pointer register can often be eliminated in favor of the stack
-   pointer register.  Secondly, the argument pointer register can always be
-   eliminated; it is replaced with either the stack or frame pointer.
-   Third, there is the return address pointer, which can also be replaced
-   with either the stack or the frame pointer.  */
-
-/* This is an array of structures.  Each structure initializes one pair
-   of eliminable registers.  The "from" register number is given first,
-   followed by "to".  Eliminations of the same "from" register are listed
-   in order of preference.  */
-
-/* If you add any registers here that are not actually hard registers,
-   and that have any alternative of elimination that doesn't always
-   apply, you need to amend calc_live_regs to exclude it, because
-   reload spills all eliminable registers where it sees an
-   can_eliminate == 0 entry, thus making them 'live' .
-   If you add any hard registers that can be eliminated in different
-   ways, you have to patch reload to spill them only when all alternatives
-   of elimination fail.  */
-
-#define ELIMINABLE_REGS						\
-{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},			\
- { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
- { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM},	\
- { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},			\
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
-
-/* Given FROM and TO register numbers, say whether this elimination
-   is allowed.  */
-#define CAN_ELIMINATE(FROM, TO) \
-  (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
-
-/* Define the offset between two registers, one to be eliminated, and the other
-   its replacement, at the start of a routine.  */
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
-  OFFSET = initial_elimination_offset ((FROM), (TO))
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM	16
-
-/* Register in which the static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM	13
-
-/* The register in which a struct value address is passed.  */
-
-#define STRUCT_VALUE_REGNUM 2
-
-/* If the structure value address is not passed in a register, define
-   `STRUCT_VALUE' as an expression returning an RTX for the place
-   where the address is passed.  If it returns 0, the address is
-   passed as an "invisible" first argument.  */
-
-/*#define STRUCT_VALUE ((rtx)0)*/
-
-/* Don't default to pcc-struct-return, because we have already specified
-   exactly how to return structures in the RETURN_IN_MEMORY macro.  */
-
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-/* The SH has two sorts of general registers, R0 and the rest.  R0 can
-   be used as the destination of some of the arithmetic ops. There are
-   also some special purpose registers; the T bit register, the
-   Procedure Return Register and the Multiply Accumulate Registers.  */
-/* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
-   reg_class_subunion.  We don't want to have an actual union class
-   of these, because it would only be used when both classes are calculated
-   to give the same cost, but there is only one FPUL register.
-   Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
-   applying to the actual instruction alternative considered.  E.g., the
-   y/r alternative of movsi_ie is considered to have no more cost that
-   the r/r alternative, which is patently untrue.  */
-
-enum reg_class
-{
-  NO_REGS,
-  R0_REGS,
-  PR_REGS,
-  T_REGS,
-  MAC_REGS,
-  FPUL_REGS,
-  GENERAL_REGS,
-  FP0_REGS,
-  FP_REGS,
-  DF_REGS,
-  FPSCR_REGS,
-  GENERAL_FP_REGS,
-  ALL_REGS,
-  LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES  (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.  */
-#define REG_CLASS_NAMES	\
-{			\
-  "NO_REGS",		\
-  "R0_REGS",		\
-  "PR_REGS",		\
-  "T_REGS",		\
-  "MAC_REGS",		\
-  "FPUL_REGS",		\
-  "GENERAL_REGS",	\
-  "FP0_REGS",		\
-  "FP_REGS",		\
-  "DF_REGS",		\
-  "FPSCR_REGS",		\
-  "GENERAL_FP_REGS",	\
-  "ALL_REGS",		\
-}
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS				\
-{							\
-  { 0x00000000, 0x00000000 }, /* NO_REGS	*/	\
-  { 0x00000001, 0x00000000 }, /* R0_REGS	*/	\
-  { 0x00020000, 0x00000000 }, /* PR_REGS	*/	\
-  { 0x00040000, 0x00000000 }, /* T_REGS		*/	\
-  { 0x00300000, 0x00000000 }, /* MAC_REGS	*/	\
-  { 0x00400000, 0x00000000 }, /* FPUL_REGS	*/	\
-  { 0x0081FFFF, 0x00000000 }, /* GENERAL_REGS	*/	\
-  { 0x01000000, 0x00000000 }, /* FP0_REGS	*/	\
-  { 0xFF000000, 0x000000FF }, /* FP_REGS	*/	\
-  { 0xFF000000, 0x0000FFFF }, /* DF_REGS	*/	\
-  { 0x00000000, 0x00010000 }, /* FPSCR_REGS	*/	\
-  { 0xFF81FFFF, 0x0000FFFF }, /* GENERAL_FP_REGS */	\
-  { 0xFFFFFFFF, 0x0001FFFF }, /* ALL_REGS	*/	\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-extern int regno_reg_class[];
-#define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
-
-/* When defined, the compiler allows registers explicitly used in the
-   rtl to be used as spill registers but prevents the compiler from
-   extending the lifetime of these registers.  */
-
-#define SMALL_REGISTER_CLASSES 1
-
-/* The order in which register should be allocated.  */
-/* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
-   and GENERAL_FP_REGS the alternate class.  Since FP0 is likely to be
-   spilled or used otherwise, we better have the FP_REGS allocated first.  */
-#define REG_ALLOC_ORDER \
-  { 25,26,27,28,29,30,31,24,32,33,34,35,36,37,38,39,	\
-    40,41,42,43,44,45,46,47,48,				\
-    1,2,3,7,6,5,4,0,8,9,10,11,12,13,14,			\
-    22,15,16,17,18,19,20,21,23 }
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS  R0_REGS
-#define BASE_REG_CLASS	 GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine
-   description.  */
-extern enum reg_class reg_class_from_letter[];
-
-#define REG_CLASS_FROM_LETTER(C) \
-   ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-	I: arithmetic operand -127..128, as used in add, sub, etc
-	K: shift operand 1,2,8 or 16
-	L: logical operand 0..255, as used in and, or, etc.
-	M: constant 1
-	N: constant 0  */
-
-#define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
-			       && ((HOST_WIDE_INT)(VALUE)) <= 127)
-#define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
-#define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
-			       && ((HOST_WIDE_INT)(VALUE)) <= 255)
-#define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
-#define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
-#define CONST_OK_FOR_LETTER_P(VALUE, C)		\
-     ((C) == 'I' ? CONST_OK_FOR_I (VALUE)	\
-    : (C) == 'K' ? CONST_OK_FOR_K (VALUE)	\
-    : (C) == 'L' ? CONST_OK_FOR_L (VALUE)	\
-    : (C) == 'M' ? CONST_OK_FOR_M (VALUE)	\
-    : (C) == 'N' ? CONST_OK_FOR_N (VALUE)	\
-    : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)	\
-((C) == 'G' ? fp_zero_operand (VALUE)		\
- : (C) == 'H' ? fp_one_operand (VALUE)		\
- : (C) == 'F')
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
-
-#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
-  ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS			\
-	|| (CLASS) == DF_REGS)						\
-      && (GET_CODE (X) == REG && REGNO (X) <= AP_REG))			\
-     || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS)		\
-	 && GET_CODE (X) == REG						\
-	 && REGNO (X) >= FIRST_FP_REG && REGNO (X) <= LAST_FP_REG))	\
-    && MODE == SFmode)							\
-   ? FPUL_REGS								\
-   : ((CLASS) == FPUL_REGS						\
-      && (GET_CODE (X) == MEM						\
-	  || (GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER)))\
-   ? GENERAL_REGS							\
-   : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS)			\
-      && GET_CODE (X) == REG && REGNO (X) > 15				\
-      && (CLASS) != REGNO_REG_CLASS (REGNO (X)))			\
-   ? GENERAL_REGS : NO_REGS)
-
-#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X)  \
-  ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS)	\
-    && immediate_operand ((X), (MODE))					\
-    && ! ((fp_zero_operand (X) || fp_one_operand (X)) && (MODE) == SFmode))\
-   ? R0_REGS								\
-   : CLASS == FPUL_REGS && immediate_operand ((X), (MODE))		\
-   ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X))		\
-      ? GENERAL_REGS							\
-      : R0_REGS)							\
-   : (CLASS == FPSCR_REGS						\
-      && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER)	\
-	  || GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS))	\
-   ? GENERAL_REGS							\
-   : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.
-
-   On SH this is the size of MODE in words.  */
-#define CLASS_MAX_NREGS(CLASS, MODE) \
-     ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* If defined, gives a class of registers that cannot be used as the
-   operand of a SUBREG that changes the size of the object.  */
-
-#define CLASS_CANNOT_CHANGE_SIZE	DF_REGS
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define the number of registers that can hold parameters.
-   These macros are used only in other macro definitions below.  */
-
-#define NPARM_REGS(MODE) \
-  (TARGET_SH3E && (MODE) == SFmode \
-   ? 8 \
-   : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
-		    || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
-   ? 8 \
-   : 4)
-
-#define FIRST_PARM_REG 4
-#define FIRST_RET_REG  0
-
-#define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
-#define FIRST_FP_RET_REG FIRST_FP_REG
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/*  Define this macro if the addresses of local variable slots are at
-    negative offsets from the frame pointer.
-
-    The SH only has positive indexes, so grow the frame up.  */
-/* #define FRAME_GROWS_DOWNWARD */
-
-/* Offset from the frame pointer to the first local variable slot to
-   be allocated.  */
-#define STARTING_FRAME_OFFSET  0
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.  */
-/* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
-   When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
-   do correct alignment.  */
-#if 0
-#define PUSH_ROUNDING(NPUSHED)  (((NPUSHED) + 3) & ~3)
-#endif
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL)  0
-
-/* Value is the number of byte of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.
-
-   On the SH, the caller does not pop any of its arguments that were passed
-   on the stack.  */
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE)  0
-
-/* Nonzero if we do not know how to pass TYPE solely in registers.
-   Values that come in registers with inconvenient padding are stored
-   to memory at the function start.  */
-
-#define MUST_PASS_IN_STACK(MODE,TYPE)			\
-  ((TYPE) != 0						\
-   && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST	\
-       || TREE_ADDRESSABLE (TYPE)))
-/* Some subroutine macros specific to this machine. */
-
-#define BASE_RETURN_VALUE_REG(MODE) \
-  ((TARGET_SH3E && ((MODE) == SFmode))			\
-   ? FIRST_FP_RET_REG					\
-   : TARGET_SH3E && (MODE) == SCmode		\
-   ? FIRST_FP_RET_REG					\
-   : (TARGET_SH4					\
-      && ((MODE) == DFmode || (MODE) == SFmode		\
-	  || (MODE) == DCmode || (MODE) == SCmode ))	\
-   ? FIRST_FP_RET_REG					\
-   : FIRST_RET_REG)
-
-#define BASE_ARG_REG(MODE) \
-  ((TARGET_SH3E && ((MODE) == SFmode))			\
-   ? FIRST_FP_PARM_REG					\
-   : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT	\
-		    || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
-   ? FIRST_FP_PARM_REG					\
-   : FIRST_PARM_REG)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.
-   For the SH, this is like LIBCALL_VALUE, except that we must change the
-   mode like PROMOTE_MODE does.
-   ??? PROMOTE_MODE is ignored for non-scalar types.  The set of types
-   tested here has to be kept in sync with the one in explow.c:promote_mode.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)					\
-  gen_rtx (REG,								\
-	   ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT		\
-	     && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD	\
-	     && (TREE_CODE (VALTYPE) == INTEGER_TYPE			\
-		 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE		\
-		 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE			\
-		 || TREE_CODE (VALTYPE) == CHAR_TYPE			\
-		 || TREE_CODE (VALTYPE) == REAL_TYPE			\
-		 || TREE_CODE (VALTYPE) == OFFSET_TYPE))		\
-	    ? SImode : TYPE_MODE (VALTYPE)),				\
-	   BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
-     
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-#define LIBCALL_VALUE(MODE) \
-  gen_rtx (REG, (MODE), BASE_RETURN_VALUE_REG (MODE))
-
-/* 1 if N is a possible register number for a function value. */
-#define FUNCTION_VALUE_REGNO_P(REGNO) \
-  ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
-
-/* 1 if N is a possible register number for function argument passing.  */
-#define FUNCTION_ARG_REGNO_P(REGNO) \
-  (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4))        \
-   || (TARGET_SH3E                                                      \
-       && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8)))
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On SH, this is a single integer, which is a number of words
-   of arguments scanned so far (including the invisible argument,
-   if any, which holds the structure-value-address).
-   Thus NARGREGS or more means all following args should go on the stack.  */
-
-enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
-struct sh_args {
-    int arg_count[2];
-};
-
-#define CUMULATIVE_ARGS  struct sh_args
-
-#define GET_SH_ARG_CLASS(MODE) \
-  ((TARGET_SH3E && (MODE) == SFmode) \
-   ? SH_ARG_FLOAT \
-   : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
-		    || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
-   ? SH_ARG_FLOAT : SH_ARG_INT)
-
-#define ROUND_ADVANCE(SIZE) \
-  (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Round a register number up to a proper boundary for an arg of mode
-   MODE.
-
-   The SH doesn't care about double alignment, so we only
-   round doubles to even regs when asked to explicitly.  */
-
-#define ROUND_REG(CUM, MODE) \
-   (((TARGET_ALIGN_DOUBLE					\
-      || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode)	\
-	  && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
-     && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD)		\
-    ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)]		\
-       + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1))	\
-    : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On SH, the offset always starts at 0: the first parm reg is always
-   the same reg for a given argument class.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
-  do {								\
-    (CUM).arg_count[(int) SH_ARG_INT] = 0;			\
-    (CUM).arg_count[(int) SH_ARG_FLOAT] = 0;			\
-  } while (0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be
-   available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
-   ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)]	\
-    = (ROUND_REG ((CUM), (MODE))			\
-       + ((MODE) == BLKmode				\
-	  ? ROUND_ADVANCE (int_size_in_bytes (TYPE))	\
-	  : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
-
-/* Return boolean indicating arg of mode MODE will be passed in a reg.
-   This macro is only used in this file. */
-
-#define PASS_IN_REG_P(CUM, MODE, TYPE) \
-  (((TYPE) == 0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
-   && (TARGET_SH3E \
-       ? ((MODE) == BLKmode \
-	  ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
-	      + int_size_in_bytes (TYPE)) \
-	     <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
-	  : ((ROUND_REG((CUM), (MODE)) \
-	      + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
-	     <= NPARM_REGS (MODE))) \
-       : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-
-   On SH the first args are normally in registers
-   and the rest are pushed.  Any arg that starts within the first
-   NPARM_REGS words is at least partially passed in a register unless
-   its data type forbids.  */
-
-extern int current_function_varargs;
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  ((PASS_IN_REG_P ((CUM), (MODE), (TYPE))				\
-    && ((NAMED) || TARGET_SH3E || ! current_function_varargs))		\
-   ? gen_rtx (REG, (MODE),						\
-	      ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) 	\
-	       ^ ((MODE) == SFmode && TARGET_SH4			\
-		  && TARGET_LITTLE_ENDIAN != 0)))			\
-   : 0)
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.
-
-   We sometimes split args.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-  ((PASS_IN_REG_P ((CUM), (MODE), (TYPE))			\
-    && ! TARGET_SH4						\
-    && (ROUND_REG ((CUM), (MODE))				\
-	+ ((MODE) != BLKmode					\
-	   ? ROUND_ADVANCE (GET_MODE_SIZE (MODE))		\
-	   : ROUND_ADVANCE (int_size_in_bytes (TYPE)))		\
-	- NPARM_REGS (MODE) > 0))				\
-   ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE))		\
-   : 0)
-
-extern int current_function_anonymous_args;
-
-/* Perform any needed actions needed for a function that is receiving a
-   variable number of arguments.  */
-
-#define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
-  current_function_anonymous_args = 1;
-
-/* Call the function profiler with a given profile label.
-   We use two .aligns, so as to make sure that both the .long is aligned
-   on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
-   from the trapa instruction.  */
-
-#define FUNCTION_PROFILER(STREAM,LABELNO)			\
-{								\
-	fprintf((STREAM), "\t.align\t2\n");			\
-	fprintf((STREAM), "\ttrapa\t#33\n");			\
- 	fprintf((STREAM), "\t.align\t2\n");			\
-	asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO));	\
-}
-
-/* Define this macro if the code for function profiling should come
-   before the function prologue.  Normally, the profiling code comes
-   after.  */
-
-#define PROFILE_BEFORE_PROLOGUE
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Generate the assembly code for function exit
-   Just dump out any accumulated constant table.  */
-
-#define FUNCTION_EPILOGUE(STREAM, SIZE)  function_epilogue ((STREAM), (SIZE))
-
-/* 
-   On the SH, the trampoline looks like
-   2 0002 DD02     	   	mov.l	l2,r13
-   1 0000 D301     		mov.l	l1,r3
-   3 0004 4D2B     		jmp	@r13
-   4 0006 0009     		nop
-   5 0008 00000000 	l1:  	.long   function
-   6 000c 00000000 	l2:	.long   area  */
-
-/* Length in units of the trampoline for entering a nested function.  */
-#define TRAMPOLINE_SIZE  16
-
-/* Alignment required for a trampoline in bits .  */
-#define TRAMPOLINE_ALIGNMENT \
-  ((CACHE_LOG < 3 || TARGET_SMALLCODE && ! TARGET_HARVARD) ? 32 : 64)
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx (MEM, SImode, (TRAMP)),			\
-		  GEN_INT (TARGET_LITTLE_ENDIAN ? 0xd301dd02 : 0xdd02d301));\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 4)),	\
-		  GEN_INT (TARGET_LITTLE_ENDIAN ? 0x00094d2b : 0x4d2b0009));\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)),	\
-		  (CXT));						\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)),	\
-		  (FNADDR));						\
-  if (TARGET_HARVARD)							\
-    emit_insn (gen_ic_invalidate_line (TRAMP));				\
-}
-
-/* A C expression whose value is RTL representing the value of the return
-   address for the frame COUNT steps up from the current frame.
-   FRAMEADDR is already the frame pointer of the COUNT frame, so we
-   can ignore COUNT.  */
-
-#define RETURN_ADDR_RTX(COUNT, FRAME)	\
-  (((COUNT) == 0)				\
-   ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM)) \
-   : (rtx) 0)
-
-/* Generate necessary RTL for __builtin_saveregs().
-   ARGLIST is the argument list; see expr.c.  */
-extern struct rtx_def *sh_builtin_saveregs ();
-#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sh_builtin_saveregs (ARGLIST)
-
-/* Addressing modes, and classification of registers for them.  */
-#define HAVE_POST_INCREMENT  1
-/*#define HAVE_PRE_INCREMENT   1*/
-/*#define HAVE_POST_DECREMENT  1*/
-#define HAVE_PRE_DECREMENT   1
-
-#define USE_LOAD_POST_INCREMENT(mode)    ((mode == SImode || mode == DImode) \
-                                           ? 0 : 1)
-#define USE_LOAD_PRE_DECREMENT(mode)     0
-#define USE_STORE_POST_INCREMENT(mode)   0
-#define USE_STORE_PRE_DECREMENT(mode)    ((mode == SImode || mode == DImode) \
-                                           ? 0 : 1)
-
-#define MOVE_BY_PIECES_P(SIZE, ALIGN)  (move_by_pieces_ninsns (SIZE, ALIGN) \
-                                        < (TARGET_SMALLCODE ? 2 :           \
-                                           ((ALIGN >= 4) ? 16 : 2)))
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-  ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-  ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
-
-/* Maximum number of registers that can appear in a valid memory
-   address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)	(GET_CODE (X) == LABEL_REF)
-
-/* Nonzero if the constant value X is a legitimate general operand.  */
-
-#define LEGITIMATE_CONSTANT_P(X) \
-  (GET_CODE (X) != CONST_DOUBLE						\
-   || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode			\
-   || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-  (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) \
-  (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-
-/* Nonzero if X/OFFSET is a hard reg that can be used as an index
-   or if X is a pseudo reg.  */
-#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
-  ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-  REGNO_OK_FOR_BASE_P (REGNO (X))
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) \
-  REGNO_OK_FOR_INDEX_P (REGNO (X))
-
-/* Nonzero if X/OFFSET is a hard reg that can be used as an index.  */
-#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
-  (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
-
-#endif
-
-/* The 'Q' constraint is a pc relative load operand.  */
-#define EXTRA_CONSTRAINT_Q(OP)                          		\
-  (GET_CODE (OP) == MEM && 						\
-   ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF)				\
-    || (GET_CODE (XEXP ((OP), 0)) == CONST                		\
-	&& GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS 			\
-	&& GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF	\
-	&& GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
-
-#define EXTRA_CONSTRAINT(OP, C)		\
-  ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP)	\
-   : 0)
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS.  */
-
-#define MODE_DISP_OK_4(X,MODE) \
-(GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64	\
- && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
-
-#define MODE_DISP_OK_8(X,MODE) \
-((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60)	\
- && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
-
-#define BASE_REGISTER_RTX_P(X)				\
-  ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))	\
-   || (GET_CODE (X) == SUBREG				\
-       && GET_CODE (SUBREG_REG (X)) == REG		\
-       && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
-
-/* Since this must be r0, which is a single register class, we must check
-   SUBREGs more carefully, to be sure that we don't accept one that extends
-   outside the class.  */
-#define INDEX_REGISTER_RTX_P(X)				\
-  ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))	\
-   || (GET_CODE (X) == SUBREG				\
-       && GET_CODE (SUBREG_REG (X)) == REG		\
-       && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X))))
-
-/* Jump to LABEL if X is a valid address RTX.  This must also take
-   REG_OK_STRICT into account when deciding about valid registers, but it uses
-   the above macros so we are in luck.
-
-   Allow  REG
-	  REG+disp
-	  REG+r0
-	  REG++
-	  --REG  */
-
-/* ??? The SH3e does not have the REG+disp addressing mode when loading values
-   into the FRx registers.  We implement this by setting the maximum offset
-   to zero when the value is SFmode.  This also restricts loading of SFmode
-   values into the integer registers, but that can't be helped.  */
-
-/* The SH allows a displacement in a QI or HI amode, but only when the
-   other operand is R0. GCC doesn't handle this very well, so we forgo
-   all of that.
-
-   A legitimate index for a QI or HI is 0, SI can be any number 0..63,
-   DI can be any number 0..60.  */
-
-#define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL)  			\
-  do {									\
-    if (GET_CODE (OP) == CONST_INT) 					\
-      {									\
-	if (MODE_DISP_OK_4 ((OP), (MODE)))  goto LABEL;		      	\
-	if (MODE_DISP_OK_8 ((OP), (MODE)))  goto LABEL;		      	\
-      }									\
-  } while(0)
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL)			\
-{									\
-  if (BASE_REGISTER_RTX_P (X))						\
-    goto LABEL;								\
-  else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC)	\
-	   && BASE_REGISTER_RTX_P (XEXP ((X), 0)))			\
-    goto LABEL;								\
-  else if (GET_CODE (X) == PLUS						\
-	   && ((MODE) != PSImode || reload_completed))			\
-    {									\
-      rtx xop0 = XEXP ((X), 0);						\
-      rtx xop1 = XEXP ((X), 1);						\
-      if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0))	\
-	GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL);			\
-      if (GET_MODE_SIZE (MODE) <= 4					\
-	  || TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)	\
-	{								\
-	  if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
-	    goto LABEL;							\
-	  if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
-	    goto LABEL;							\
-	}								\
-    }									\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the SH, if X is almost suitable for indexing, but the offset is
-   out of range, convert it into a normal form so that cse has a chance
-   of reducing the number of address registers used.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)			\
-{								\
-  if (GET_CODE (X) == PLUS					\
-      && (GET_MODE_SIZE (MODE) == 4				\
-	  || GET_MODE_SIZE (MODE) == 8)				\
-      && GET_CODE (XEXP ((X), 1)) == CONST_INT			\
-      && BASE_REGISTER_RTX_P (XEXP ((X), 0))			\
-      && ! (TARGET_SH4 && (MODE) == DFmode)			\
-      && ! (TARGET_SH3E && (MODE) == SFmode))			\
-    {								\
-      rtx index_rtx = XEXP ((X), 1);				\
-      HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;	\
-      rtx sum;							\
-								\
-      GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN);		\
-      /* On rare occasions, we might get an unaligned pointer	\
-	 that is indexed in a way to give an aligned address.	\
-	 Therefore, keep the lower two bits in offset_base.  */ \
-      /* Instead of offset_base 128..131 use 124..127, so that	\
-	 simple add suffices.  */				\
-      if (offset > 127)						\
-	{							\
-	  offset_base = ((offset + 4) & ~60) - 4;		\
-	}							\
-      else							\
-	offset_base = offset & ~60;				\
-      /* Sometimes the normal form does not suit DImode.  We	\
-	 could avoid that by using smaller ranges, but that	\
-	 would give less optimized code when SImode is		\
-	 prevalent.  */						\
-      if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64)	\
-	{							\
-	  sum = expand_binop (Pmode, add_optab, XEXP ((X), 0),	\
-			      GEN_INT (offset_base), NULL_RTX, 0, \
-			      OPTAB_LIB_WIDEN);			\
-                                                                \
-	  (X) = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base)); \
-	  goto WIN;						\
-	}							\
-    }								\
-}
-
-/* A C compound statement that attempts to replace X, which is an address
-   that needs reloading, with a valid memory address for an operand of
-   mode MODE.  WIN is a C statement label elsewhere in the code.
-
-   Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
-   of the address.  That will allow inheritance of the address reloads.  */
-
-#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN)	\
-{									\
-  if (GET_CODE (X) == PLUS						\
-      && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8)	\
-      && GET_CODE (XEXP (X, 1)) == CONST_INT				\
-      && BASE_REGISTER_RTX_P (XEXP (X, 0))				\
-      && ! (TARGET_SH4 && (MODE) == DFmode)				\
-      && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS))	\
-    {									\
-      rtx index_rtx = XEXP (X, 1);					\
-      HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base;		\
-      rtx sum;								\
-									\
-      if (TARGET_SH3E && MODE == SFmode)				\
-	{								\
-	  X = copy_rtx (X);						\
-	  push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL_PTR,	\
-		       INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM),	\
-		       (TYPE));						\
-	  goto WIN;							\
-	}								\
-      /* Instead of offset_base 128..131 use 124..127, so that		\
-	 simple add suffices.  */					\
-      if (offset > 127)							\
-	{								\
-	  offset_base = ((offset + 4) & ~60) - 4;			\
-	}								\
-      else								\
-	offset_base = offset & ~60;					\
-      /* Sometimes the normal form does not suit DImode.  We		\
-	 could avoid that by using smaller ranges, but that		\
-	 would give less optimized code when SImode is			\
-	 prevalent.  */							\
-      if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64)		\
-	{								\
-	  sum = gen_rtx (PLUS, Pmode, XEXP (X, 0),			\
-			 GEN_INT (offset_base));			\
-	  X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
-	  push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL_PTR,	\
-		       BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM),	\
-		       (TYPE));						\
-	  goto WIN;							\
-	}								\
-    }									\
-  /* We must re-recognize what we created before.  */			\
-  else if (GET_CODE (X) == PLUS						\
-	   && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8)	\
-	   && GET_CODE (XEXP (X, 0)) == PLUS				\
-	   && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT		\
-	   && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0))		\
-	   && GET_CODE (XEXP (X, 1)) == CONST_INT			\
-	   && ! (TARGET_SH3E && MODE == SFmode))			\
-    {									\
-      /* Because this address is so complex, we know it must have	\
-	 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,	\
-	 it is already unshared, and needs no further unsharing.  */	\
-      push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL_PTR,	\
-		   BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
-      goto WIN;								\
-    }									\
-}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-
-   ??? Strictly speaking, we should also include all indexed addressing,
-   because the index scale factor is the length of the operand.
-   However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
-   high if we did that.  So we rely on reload to fix things up.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)			\
-{									\
-  if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC)		\
-    goto LABEL;								\
-}
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
-
-#define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
-((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
- ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
- : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
- ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
- : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
- : SImode)
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE 1
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR  FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR  TRUNC_DIV_EXPR
-
-/* Since the SH3e has only `float' support, it is desirable to make all
-   floating point types equivalent to `float'.  */
-#define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
-
-/* 'char' is signed by default.  */
-#define DEFAULT_SIGNED_CHAR  1
-
-/* The type of size_t unsigned int.  */
-#define SIZE_TYPE "unsigned int"
-
-#define WCHAR_TYPE "short unsigned int"
-#define WCHAR_TYPE_SIZE 16
-
-/* Don't cse the address of the function being compiled.  */
-/*#define NO_RECURSIVE_FUNCTION_CSE 1*/
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 4
-
-/* Max number of bytes we want move_by_pieces to be able to copy
-   efficiently.  */
-#define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4)
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.  */
-#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
-
-/* Define if loading short immediate values into registers sign extends.  */
-#define SHORT_IMMEDIATES_SIGN_EXTEND
-
-/* Define this if zero-extension is slow (more than one real instruction).
-   On the SH, it's only one instruction.  */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 0
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
-/* Immediate shift counts are truncated by the output routines (or was it
-   the assembler?).  Shift counts in a register are truncated by SH.  Note
-   that the native compiler puts too large (> 32) immediate shift counts
-   into a register and shifts by the register, letting the SH decide what
-   to do instead of doing that itself.  */
-/* ??? The library routines in lib1funcs.asm truncate the shift count.
-   However, the SH3 has hardware shifts that do not truncate exactly as gcc
-   expects - the sign bit is significant - so it appears that we need to
-   leave this zero for correct SH3 code.  */
-#define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
-
-/* All integers have the same format so truncation is easy.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC)  1
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.  */
-/*#define NO_FUNCTION_CSE 1*/
-
-/* Chars and shorts should be passed as ints.  */
-#define PROMOTE_PROTOTYPES 1
-
-/* The machine modes of pointers and functions.  */
-#define Pmode  SImode
-#define FUNCTION_MODE  Pmode
-
-/* The relative costs of various types of constants.  Note that cse.c defines
-   REG = 1, SUBREG = 2, any node = (2 + sum of subnodes).  */
-
-#define CONST_COSTS(RTX, CODE, OUTER_CODE)	\
-  case CONST_INT:				\
-    if (INTVAL (RTX) == 0)			\
-      return 0;					\
-    else if (CONST_OK_FOR_I (INTVAL (RTX)))	\
-      return 1;					\
-    else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \
-	     && CONST_OK_FOR_L (INTVAL (RTX)))	\
-      return 1;					\
-    else					\
-      return 8;					\
-  case CONST: 					\
-  case LABEL_REF:				\
-  case SYMBOL_REF:				\
-    return 5;					\
-  case CONST_DOUBLE:				\
-      return 10;
-
-#define RTX_COSTS(X, CODE, OUTER_CODE)			\
-  case PLUS:						\
-    return (COSTS_N_INSNS (1)				\
-	    + rtx_cost (XEXP ((X), 0), PLUS)		\
-	    + (rtx_equal_p (XEXP ((X), 0), XEXP ((X), 1))\
-	       ? 0 : rtx_cost (XEXP ((X), 1), PLUS)));\
-  case AND:						\
-    return COSTS_N_INSNS (andcosts (X));		\
-  case MULT:						\
-    return COSTS_N_INSNS (multcosts (X));		\
-  case ASHIFT:						\
-  case ASHIFTRT:					\
-  case LSHIFTRT:					\
-    /* Add one extra unit for the matching constraint.	\
-       Otherwise loop strength reduction would think that\
-       a shift with different sourc and destination is	\
-       as cheap as adding a constant to a register.  */	\
-    return (COSTS_N_INSNS (shiftcosts (X))		\
-	    + rtx_cost (XEXP ((X), 0), (CODE))		\
-	    + 1);					\
-  case DIV:						\
-  case UDIV:						\
-  case MOD:						\
-  case UMOD:						\
-    return COSTS_N_INSNS (20);				\
-  case FLOAT:						\
-  case FIX:						\
-    return 100;
-
-/* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
-   are actually function calls with some special constraints on arguments
-   and register usage.
-
-   These macros tell reorg that the references to arguments and
-   register clobbers for insns of type sfunc do not appear to happen
-   until after the millicode call.  This allows reorg to put insns
-   which set the argument registers into the delay slot of the millicode
-   call -- thus they act more like traditional CALL_INSNs.
-
-   get_attr_is_sfunc will try to recognize the given insn, so make sure to
-   filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
-   in particular.  */
-
-#define INSN_SETS_ARE_DELAYED(X) 		\
-  ((GET_CODE (X) == INSN			\
-    && GET_CODE (PATTERN (X)) != SEQUENCE	\
-    && GET_CODE (PATTERN (X)) != USE		\
-    && GET_CODE (PATTERN (X)) != CLOBBER	\
-    && get_attr_is_sfunc (X)))
-
-#define INSN_REFERENCES_ARE_DELAYED(X) 		\
-  ((GET_CODE (X) == INSN			\
-    && GET_CODE (PATTERN (X)) != SEQUENCE	\
-    && GET_CODE (PATTERN (X)) != USE		\
-    && GET_CODE (PATTERN (X)) != CLOBBER	\
-    && get_attr_is_sfunc (X)))
-
-/* Compute the cost of an address.  For the SH, all valid addresses are
-   the same cost.  */
-/* ??? Perhaps we should make reg+reg addresses have higher cost because
-   they add to register pressure on r0.  */
-
-#define ADDRESS_COST(RTX) 1
-
-/* Compute extra cost of moving data between one register class
-   and another.  */
-
-/* Regclass always uses 2 for moves in the same register class;
-   If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
-   it uses this information.  Hence, the general register <-> floating point
-   register information here is not used for SFmode.  */
-#define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
-  ((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REG)) ? 10		\
-   : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS || (DSTCLASS) == DF_REGS) \
-       && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS))	\
-      || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS)		\
-	  && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS		\
-	      || (SRCCLASS) == DF_REGS)))				\
-   ? TARGET_FMOVD ? 8 : 12						\
-   : (((DSTCLASS) == FPUL_REGS						\
-       && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS))	\
-      || (SRCCLASS == FPUL_REGS						\
-	  && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS)))	\
-   ? 5									\
-   : (((DSTCLASS) == FPUL_REGS						\
-       && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS))		\
-      || ((SRCCLASS) == FPUL_REGS					\
-	  && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS)))	\
-   ? 7									\
-   : 2)
-
-/* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option?  This
-   would be so that people would slow memory systems could generate
-   different code that does fewer memory accesses.  */
-
-/* Assembler output control.  */
-
-/* A C string constant describing how to begin a comment in the target
-   assembler language.  The compiler assumes that the comment will end at
-   the end of the line.  */
-#define ASM_COMMENT_START "!"
-
-/* The text to go at the start of the assembler file.  */
-#define ASM_FILE_START(STREAM) \
-  output_file_start (STREAM)
-
-#define ASM_FILE_END(STREAM)
-
-#define ASM_APP_ON  		""
-#define ASM_APP_OFF  		""
-#define FILE_ASM_OP 		"\t.file\n"
-#define IDENT_ASM_OP 		"\t.ident\n"
-#define SET_ASM_OP		".set"
-
-/* How to change between sections.  */
-
-#define TEXT_SECTION_ASM_OP  		"\t.text"
-#define DATA_SECTION_ASM_OP  		"\t.data"
-#define CTORS_SECTION_ASM_OP 		"\t.section\t.ctors\n"
-#define DTORS_SECTION_ASM_OP 		"\t.section\t.dtors\n"
-#define EXTRA_SECTIONS 			in_ctors, in_dtors
-#define EXTRA_SECTION_FUNCTIONS					\
-void								\
-ctors_section()							\
-{								\
-  if (in_section != in_ctors)					\
-    {								\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);	\
-      in_section = in_ctors;					\
-    }								\
-}								\
-void								\
-dtors_section()							\
-{								\
-  if (in_section != in_dtors)					\
-    {								\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);	\
-      in_section = in_dtors;					\
-    }								\
-}
-
-/* If defined, a C expression whose value is a string containing the
-   assembler operation to identify the following data as
-   uninitialized global data.  If not defined, and neither
-   `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
-   uninitialized global data will be output in the data section if
-   `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
-   used.  */
-#ifndef BSS_SECTION_ASM_OP
-#define BSS_SECTION_ASM_OP	".section\t.bss"
-#endif
-
-/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
-   separate, explicit argument.  If you define this macro, it is used
-   in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
-   handling the required alignment of the variable.  The alignment is
-   specified as the number of bits.
-
-   Try to use function `asm_output_aligned_bss' defined in file
-   `varasm.c' when defining this macro. */
-#ifndef ASM_OUTPUT_ALIGNED_BSS
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
-#endif
-
-/* Define this so that jump tables go in same section as the current function,
-   which could be text or it could be a user defined section.  */
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* A C statement to output something to the assembler file to switch to section
-   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
-   NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
-   define this macro in such cases.  */
-
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
-   do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
-   do { ctors_section();  asm_fprintf((FILE),"\t.long\t%U%s\n", (NAME)); } while (0)
-
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
-   do {  dtors_section();  asm_fprintf((FILE),"\t.long\t%U%s\n", (NAME)); } while (0)
-
-#undef DO_GLOBAL_CTORS_BODY
-
-#define DO_GLOBAL_CTORS_BODY			\
-{						\
-  typedef (*pfunc)();				\
-  extern pfunc __ctors[];			\
-  extern pfunc __ctors_end[];			\
-  pfunc *p;					\
-  for (p = __ctors_end; p > __ctors; )		\
-    {						\
-      (*--p)();					\
-    }						\
-}
-
-#undef DO_GLOBAL_DTORS_BODY
-#define DO_GLOBAL_DTORS_BODY			\
-{						\
-  typedef (*pfunc)();				\
-  extern pfunc __dtors[];			\
-  extern pfunc __dtors_end[];			\
-  pfunc *p;					\
-  for (p = __dtors; p < __dtors_end; p++)	\
-    {						\
-      (*p)();					\
-    }						\
-}
-
-#define ASM_OUTPUT_REG_PUSH(file, v) \
-  fprintf ((file), "\tmov.l\tr%s,-@r15\n", (v));
-
-#define ASM_OUTPUT_REG_POP(file, v) \
-  fprintf ((file), "\tmov.l\t@r15+,r%s\n", (v));
-
-/* The assembler's names for the registers.  RFP need not always be used as
-   the Real framepointer; it can also be used as a normal general register.
-   Note that the name `fp' is horribly misleading since `fp' is in fact only
-   the argument-and-return-context pointer.  */
-
-extern char fp_reg_names[][5];
-
-#define REGISTER_NAMES  				\
-{				                   	\
-  "r0", "r1", "r2",  "r3",  "r4",  "r5",  "r6",  "r7", 	\
-  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",	\
-  "ap", "pr", "t",   "gbr", "mach","macl", fp_reg_names[16], "rap", \
-  fp_reg_names[0],  fp_reg_names[1] , fp_reg_names[2],  fp_reg_names[3], \
-  fp_reg_names[4],  fp_reg_names[5],  fp_reg_names[6],  fp_reg_names[7], \
-  fp_reg_names[8],  fp_reg_names[9],  fp_reg_names[10], fp_reg_names[11], \
-  fp_reg_names[12], fp_reg_names[13], fp_reg_names[14], fp_reg_names[15], \
-  fp_reg_names[17], fp_reg_names[18], fp_reg_names[19], fp_reg_names[20], \
-  fp_reg_names[21], fp_reg_names[22], fp_reg_names[23], fp_reg_names[24], \
-  "fpscr", \
-}
-
-#define DEBUG_REGISTER_NAMES  				\
-{				                   	\
-  "r0", "r1", "r2",  "r3",  "r4",  "r5",  "r6",  "r7", 	\
-  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",	\
-  "ap", "pr", "t",  "gbr", "mach","macl", "fpul","rap", \
-  "fr0","fr1","fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
-  "fr8","fr9","fr10","fr11","fr12","fr13","fr14","fr15",\
-  "xd0","xd2","xd4", "xd6", "xd8", "xd10","xd12","xd14", \
-  "fpscr", \
-}
-
-/* DBX register number for a given compiler register number.  */
-/* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
-   to match gdb.  */
-#define DBX_REGISTER_NUMBER(REGNO)	\
-  (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO))
-
-/* Output a label definition.  */
-#define ASM_OUTPUT_LABEL(FILE,NAME) \
-  do { assemble_name ((FILE), (NAME)); fputs (":\n", (FILE)); } while (0)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf ((FILE), "\t.align %d\n", (LOG))
-
-/* Output a function label definition.  */
-#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
-    ASM_OUTPUT_LABEL((STREAM), (NAME))
-
-/* Output a globalising directive for a label.  */
-#define ASM_GLOBALIZE_LABEL(STREAM,NAME)	\
-  (fprintf ((STREAM), "\t.global\t"),		\
-   assemble_name ((STREAM), (NAME)),		\
-   fputc ('\n', (STREAM)))
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* The prefix to add to an internally generated label. */
-
-#define LOCAL_LABEL_PREFIX ""
-
-/* Make an internal label into a string.  */
-#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
-  sprintf ((STRING), "*%s%s%d", LOCAL_LABEL_PREFIX, (PREFIX), (NUM))
-
-/* Output an internal label definition.  */
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
-  asm_fprintf ((FILE), "%L%s%d:\n", (PREFIX), (NUM))
-
-/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE)	    */
-
-/* Construct a private name.  */
-#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER)	\
-  ((OUTVAR) = (char *) alloca (strlen (NAME) + 10),	\
-   sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
-
-/* Output a relative address table.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL)  		\
-  switch (GET_MODE (BODY))						\
-    {									\
-    case SImode:							\
-      asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL));	\
-      break;								\
-    case HImode:							\
-      asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL));	\
-      break;								\
-    case QImode:							\
-      asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL));	\
-      break;								\
-    }
-
-/* Output an absolute table element.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE)  				\
-  if (TARGET_BIGTABLE) 							\
-    asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); 			\
-  else									\
-    asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); 			\
-
-/* Output various types of constants.  */
-
-/* This is how to output an assembler line defining a `double'.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf ((FILE), "\t.double %s\n", dstr);		\
-   } while (0)
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf ((FILE), "\t.float %s\n", dstr);		\
-   } while (0)
-
-#define ASM_OUTPUT_INT(STREAM, EXP)		\
-  (fprintf ((STREAM), "\t.long\t"),      	\
-   output_addr_const ((STREAM), (EXP)),  	\
-   fputc ('\n', (STREAM)))
-
-#define ASM_OUTPUT_SHORT(STREAM, EXP)	\
-  (fprintf ((STREAM), "\t.short\t"),	\
-   output_addr_const ((STREAM), (EXP)),	\
-   fputc ('\n', (STREAM)))
-
-#define ASM_OUTPUT_CHAR(STREAM, EXP)		\
-  (fprintf ((STREAM), "\t.byte\t"),      	\
-   output_addr_const ((STREAM), (EXP)),  	\
-   fputc ('\n', (STREAM)))
-
-#define ASM_OUTPUT_BYTE(STREAM, VALUE)  	\
-  fprintf ((STREAM), "\t.byte\t%d\n", (VALUE)) 	\
-
-/* The next two are used for debug info when compiling with -gdwarf.  */
-#define UNALIGNED_SHORT_ASM_OP	".uaword"
-#define UNALIGNED_INT_ASM_OP	".ualong"
-
-/* Loop alignment is now done in machine_dependent_reorg, so that
-   branch shortening can know about it.  */
-
-/* This is how to output an assembler line
-   that says to advance the location counter by SIZE bytes.  */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
-  fprintf ((FILE), "\t.space %d\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)	\
-( fputs ("\t.comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
-( fputs ("\t.lcomm ", (FILE)),				\
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* The assembler's parentheses characters.  */
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Target characters.  */
-#define TARGET_BELL	007
-#define TARGET_BS	010
-#define TARGET_TAB	011
-#define TARGET_NEWLINE	012
-#define TARGET_VT	013
-#define TARGET_FF	014
-#define TARGET_CR	015
-
-/* A C statement to be executed just prior to the output of
-   assembler code for INSN, to modify the extracted operands so
-   they will be output differently.
-
-   Here the argument OPVEC is the vector containing the operands
-   extracted from INSN, and NOPERANDS is the number of elements of
-   the vector which contain meaningful data for this insn.
-   The contents of this vector are what will be used to convert the insn
-   template into assembler code, so you can change the assembler output
-   by changing the contents of the vector.  */
-
-#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
-  final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-#define PRINT_OPERAND(STREAM, X, CODE)  print_operand ((STREAM), (X), (CODE))
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-#define PRINT_OPERAND_ADDRESS(STREAM,X)  print_operand_address ((STREAM), (X))
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
-  ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ','	\
-   || (CHAR) == '$')
-
-extern struct rtx_def *sh_compare_op0;
-extern struct rtx_def *sh_compare_op1;
-extern struct rtx_def *prepare_scc_operands();
-
-/* Which processor to schedule for.  The elements of the enumeration must
-   match exactly the cpu attribute in the sh.md file.  */
-
-enum processor_type {
-  PROCESSOR_SH1,
-  PROCESSOR_SH2,
-  PROCESSOR_SH3,
-  PROCESSOR_SH3E,
-  PROCESSOR_SH4
-};
-
-#define sh_cpu_attr ((enum attr_cpu)sh_cpu)
-extern enum processor_type sh_cpu;
-
-extern enum machine_mode sh_addr_diff_vec_mode;
-
-extern int optimize; /* needed for gen_casesi.  */
-
-/* Declare functions defined in sh.c and used in templates.  */
-
-extern char *output_branch();
-extern char *output_ieee_ccmpeq();
-extern char *output_branchy_insn();
-extern char *output_shift();
-extern char *output_movedouble();
-extern char *output_movepcrel();
-extern char *output_jump_label_table();
-extern char *output_far_jump();
-
-enum mdep_reorg_phase_e
-{
-  SH_BEFORE_MDEP_REORG,
-  SH_INSERT_USES_LABELS,
-  SH_SHORTEN_BRANCHES0,
-  SH_FIXUP_PCLOAD,
-  SH_SHORTEN_BRANCHES1,
-  SH_AFTER_MDEP_REORG
-};
-
-extern enum mdep_reorg_phase_e mdep_reorg_phase;
-
-void machine_dependent_reorg ();
-struct rtx_def *sfunc_uses_reg ();
-int barrier_align ();
-int sh_loop_align ();
-
-#define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
-
-/* Generate calls to memcpy, memcmp and memset.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Define this macro if you want to implement any pragmas.  If defined, it
-   is a C expression whose value is 1 if the pragma was handled by the
-   macro, zero otherwise.  */
-#define HANDLE_PRAGMA(GETC, UNGETC, NODE) sh_handle_pragma (GETC, UNGETC, NODE)
-extern int sh_handle_pragma ();
-
-/* Set when processing a function with pragma interrupt turned on.  */
-
-extern int pragma_interrupt;
-
-/* Set to an RTX containing the address of the stack to switch to
-   for interrupt functions.  */
-extern struct rtx_def *sp_switch;
-
-/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
-   is a valid machine specific attribute for DECL.
-   The attributes in ATTRIBUTES have previously been assigned to DECL.  */
-extern int sh_valid_machine_decl_attribute ();
-#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
-sh_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
-
-extern void sh_pragma_insert_attributes ();
-#define PRAGMA_INSERT_ATTRIBUTES(node, pattr, prefix_attr) \
-  sh_pragma_insert_attributes (node, pattr, prefix_attr)
-
-extern int sh_flag_remove_dead_before_cse;
-extern int rtx_equal_function_value_matters;
-extern struct rtx_def *fpscr_rtx;
-extern struct rtx_def *get_fpscr_rtx ();
-
-
-/* Instructions with unfilled delay slots take up an extra two bytes for
-   the nop in the delay slot.  */
-
-#define ADJUST_INSN_LENGTH(X, LENGTH)				\
-  if (((GET_CODE (X) == INSN					\
-	&& GET_CODE (PATTERN (X)) != USE			\
-	&& GET_CODE (PATTERN (X)) != CLOBBER)			\
-       || GET_CODE (X) == CALL_INSN				\
-       || (GET_CODE (X) == JUMP_INSN				\
-	   && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC		\
-	   && GET_CODE (PATTERN (X)) != ADDR_VEC))		\
-      && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (X)))) != SEQUENCE \
-      && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES)	\
-    (LENGTH) += 2;
-
-/* Define the codes that are matched by predicates in sh.c.  */
-#define PREDICATE_CODES \
-  {"arith_operand", {SUBREG, REG, CONST_INT}},				\
-  {"arith_reg_operand", {SUBREG, REG}},					\
-  {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}},			\
-  {"binary_float_operator", {PLUS, MULT}},				\
-  {"commutative_float_operator", {PLUS, MULT}},				\
-  {"fp_arith_reg_operand", {SUBREG, REG}},				\
-  {"fp_extended_operand", {SUBREG, REG, FLOAT_EXTEND}},			\
-  {"fpscr_operand", {REG}},						\
-  {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}},		\
-  {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}},		\
-  {"logical_operand", {SUBREG, REG, CONST_INT}},			\
-  {"noncommutative_float_operator", {MINUS, DIV}},			\
-  {"register_operand", {SUBREG, REG}},
-
-/* Define this macro if it is advisable to hold scalars in registers
-   in a wider mode than that declared by the program.  In such cases, 
-   the value is constrained to be within the bounds of the declared
-   type, but kept valid in the wider mode.  The signedness of the
-   extension may differ from that of the type.
-
-   Leaving the unsignedp unchanged gives better code than always setting it
-   to 0.  This is despite the fact that we have only signed char and short
-   load instructions.  */
-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
-  if (GET_MODE_CLASS (MODE) == MODE_INT			\
-      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)		\
-    (MODE) = SImode;
-
-/* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
-   extensions applied to char/short functions arguments.  Defining
-   PROMOTE_FUNCTION_RETURN does the same for function returns.  */
-
-#define PROMOTE_FUNCTION_ARGS
-#define PROMOTE_FUNCTION_RETURN
-
-/* ??? Define ACCUMULATE_OUTGOING_ARGS?  This is more efficient than pushing
-   and poping arguments.  However, we do have push/pop instructions, and
-   rather limited offsets (4 bits) in load/store instructions, so it isn't
-   clear if this would give better code.  If implemented, should check for
-   compatibility problems.  */
-
-/* A C statement (sans semicolon) to update the integer variable COST
-   based on the relationship between INSN that is dependent on
-   DEP_INSN through the dependence LINK.  The default is to make no
-   adjustment to COST.  This can be used for example to specify to
-   the scheduler that an output- or anti-dependence does not incur
-   the same cost as a data-dependence.  */
-
-#define ADJUST_COST(insn,link,dep_insn,cost)				\
-do {									\
-  rtx reg;								\
-									\
-  if (GET_CODE(insn) == CALL_INSN)					\
-    {									\
-      /* The only input for a call that is timing-critical is the	\
-	 function's address.  */					\
-      rtx call = PATTERN (insn);					\
-									\
-      if (GET_CODE (call) == PARALLEL)					\
-	call = XVECEXP (call, 0 ,0);					\
-      if (GET_CODE (call) == SET)					\
-	call = SET_SRC (call);						\
-      if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM	\
-	  && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))		\
-	(cost) = 0;							\
-    }									\
-  /* All sfunc calls are parallels with at least four components.	\
-     Exploit this to avoid unnecessary calls to sfunc_uses_reg.  */	\
-  else if (GET_CODE (PATTERN (insn)) == PARALLEL			\
-	   && XVECLEN (PATTERN (insn), 0) >= 4				\
-	   && (reg = sfunc_uses_reg (insn)))				\
-    {									\
-      /* Likewise, the most timing critical input for an sfuncs call	\
-	 is the function address.  However, sfuncs typically start	\
-	 using their arguments pretty quickly.				\
-	 Assume a four cycle delay before they are needed.  */		\
-      if (! reg_set_p (reg, dep_insn))					\
-	cost -= TARGET_SUPERSCALAR ? 40 : 4;				\
-    }									\
-  /* Adjust load_si / pcload_si type insns latency.  Use the known	\
-     nominal latency and form of the insn to speed up the check.  */	\
-  else if (cost == 3							\
-	   && GET_CODE (PATTERN (dep_insn)) == SET			\
-	   /* Latency for dmpy type insns is also 3, so check the that	\
-	      it's actually a move insn.  */				\
-	   && general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode))\
-    cost = 2;								\
-  else if (cost == 30							\
-	   && GET_CODE (PATTERN (dep_insn)) == SET			\
-	   && GET_MODE (SET_SRC (PATTERN (dep_insn))) == SImode)	\
-    cost = 20;								\
-} while (0)								\
-
-/* For the sake of libgcc2.c, indicate target supports atexit.  */
-#define HAVE_ATEXIT
-
-#define SH_DYNAMIC_SHIFT_COST \
-  (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
deleted file mode 100755
index 7e417ab..0000000
--- a/gcc/config/sh/sh.md
+++ /dev/null
@@ -1,4654 +0,0 @@
-;; CYGNUS LOCAL SH4 Phase III: REG_LIBCALL / REG_RETVAL wrapping of
-;; MACH_REG / MACL_REG usage.
-;;- Machine description for the Hitachi SH.
-;;  Copyright (C) 1993 - 1999 Free Software Foundation, Inc.
-;;  Contributed by Steve Chamberlain (sac@cygnus.com).
-;;  Improved by Jim Wilson (wilson@cygnus.com).
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;; ??? Should prepend a * to all pattern names which are not used.
-;; This will make the compiler smaller, and rebuilds after changes faster.
-
-;; ??? Should be enhanced to include support for many more GNU superoptimizer
-;; sequences.  Especially the sequences for arithmetic right shifts.
-
-;; ??? Should check all DImode patterns for consistency and usefulness.
-
-;; ??? The MAC.W and MAC.L instructions are not supported.  There is no
-;; way to generate them.
-
-;; ??? The cmp/str instruction is not supported.  Perhaps it can be used
-;; for a str* inline function.
-
-;; BSR is not generated by the compiler proper, but when relaxing, it
-;; generates .uses pseudo-ops that allow linker relaxation to create
-;; BSR.  This is actually implemented in bfd/{coff,elf32}-sh.c
-
-;; Special constraints for SH machine description:
-;;
-;;    t -- T
-;;    x -- mac
-;;    l -- pr
-;;    z -- r0
-;;
-;; Special formats used for outputting SH instructions:
-;;
-;;   %.  --  print a .s if insn needs delay slot
-;;   %@  --  print rte/rts if is/isn't an interrupt function
-;;   %#  --  output a nop if there is nothing to put in the delay slot
-;;   %O  --  print a constant without the #
-;;   %R  --  print the lsw reg of a double
-;;   %S  --  print the msw reg of a double
-;;   %T  --  print next word of a double REG or MEM
-;;
-;; Special predicates:
-;;
-;;  arith_operand          -- operand is valid source for arithmetic op
-;;  arith_reg_operand      -- operand is valid register for arithmetic op
-;;  general_movdst_operand -- operand is valid move destination
-;;  general_movsrc_operand -- operand is valid move source
-;;  logical_operand        -- operand is valid source for logical op
-;; -------------------------------------------------------------------------
-;; Attributes
-;; -------------------------------------------------------------------------
-
-;; Target CPU.
-
-(define_attr "cpu"
- "sh1,sh2,sh3,sh3e,sh4"
-  (const (symbol_ref "sh_cpu_attr")))
-
-(define_attr "endian" "big,little"
- (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
-		      (const_string "little") (const_string "big"))))
-
-(define_attr "fmovd" "yes,no"
-  (const (if_then_else (symbol_ref "TARGET_FMOVD")
-		       (const_string "yes") (const_string "no"))))
-;; issues/clock
-(define_attr "issues" "1,2"
-  (const (if_then_else (symbol_ref "TARGET_SUPERSCALAR") (const_string "2") (const_string "1"))))
-
-;; cbranch	conditional branch instructions
-;; jump		unconditional jumps
-;; arith	ordinary arithmetic
-;; arith3	a compound insn that behaves similarly to a sequence of
-;;		three insns of type arith
-;; arith3b	like above, but might end with a redirected branch
-;; load		from memory
-;; load_si	Likewise, SImode variant for general register.
-;; store	to memory
-;; move		register to register
-;; fmove	register to register, floating point
-;; smpy		word precision integer multiply
-;; dmpy		longword or doublelongword precision integer multiply
-;; return	rts
-;; pload	load of pr reg, which can't be put into delay slot of rts
-;; pstore	store of pr reg, which can't be put into delay slot of jsr
-;; pcload	pc relative load of constant value
-;; pcload_si	Likewise, SImode variant for general register.
-;; rte		return from exception
-;; sfunc	special function call with known used registers
-;; call		function call
-;; fp		floating point
-;; fdiv		floating point divide (or square root)
-;; gp_fpul	move between general purpose register and fpul
-;; dfp_arith, dfp_cmp,dfp_conv
-;; dfdiv	double precision floating point divide (or square root)
-;; nil		no-op move, will be deleted.
-
-(define_attr "type"
- "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,pstore,pcload,pcload_si,rte,sfunc,call,fp,fdiv,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,nil"
-  (const_string "other"))
-
-; If a conditional branch destination is within -252..258 bytes away
-; from the instruction it can be 2 bytes long.  Something in the
-; range -4090..4100 bytes can be 6 bytes long.  All other conditional
-; branches are initially assumed to be 16 bytes long.
-; In machine_dependent_reorg, we split all branches that are longer than
-; 2 bytes.
-
-;; The maximum range used for SImode constant pool entrys is 1018.  A final
-;; instruction can add 8 bytes while only being 4 bytes in size, thus we
-;; can have a total of 1022 bytes in the pool.  Add 4 bytes for a branch
-;; instruction around the pool table, 2 bytes of alignment before the table,
-;; and 30 bytes of alignment after the table.  That gives a maximum total
-;; pool size of 1058 bytes.
-;; Worst case code/pool content size ratio is 1:2 (using asms).
-;; Thus, in the worst case, there is one instruction in front of a maximum
-;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
-;; code.  For the last n bytes of code, there are 2n + 36 bytes of pool.
-;; If we have a forward branch, the initial table will be put after the
-;; unconditional branch.
-;;
-;; ??? We could do much better by keeping track of the actual pcloads within
-;; the branch range and in the pcload range in front of the branch range.
-
-;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
-;; inside an le.
-(define_attr "short_cbranch_p" "no,yes"
-  (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
-	 (const_string "no")
-	 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
-	 (const_string "yes")
-	 (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
-	 (const_string "no")
-	 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
-	 (const_string "yes")
-         ] (const_string "no")))
-
-(define_attr "med_branch_p" "no,yes"
-  (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
-	      (const_int 1988))
-	 (const_string "yes")
-	 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
-	 (const_string "no")
-	 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
-	      (const_int 8186))
-	 (const_string "yes")
-	 ] (const_string "no")))
-
-(define_attr "med_cbranch_p" "no,yes"
-  (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
-	      (const_int 1986))
-	 (const_string "yes")
-	 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
-	 (const_string "no")
-	 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
-	       (const_int 8184))
-	 (const_string "yes")
-	 ] (const_string "no")))
-
-(define_attr "braf_branch_p" "no,yes"
-  (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
-	 (const_string "no")
-	 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
-	      (const_int 20660))
-	 (const_string "yes")
-	 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
-	 (const_string "no")
-	 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
-	      (const_int 65530))
-	 (const_string "yes")
-	 ] (const_string "no")))
-
-(define_attr "braf_cbranch_p" "no,yes"
-  (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
-	 (const_string "no")
-	 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
-	      (const_int 20658))
-	 (const_string "yes")
-	 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
-	 (const_string "no")
-	 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
-	      (const_int 65528))
-	 (const_string "yes")
-	 ] (const_string "no")))
-
-; An unconditional jump in the range -4092..4098 can be 2 bytes long.
-; For wider ranges, we need a combination of a code and a data part.
-; If we can get a scratch register for a long range jump, the code
-; part can be 4 bytes long; otherwise, it must be 8 bytes long.
-; If the jump is in the range -32764..32770, the data part can be 2 bytes
-; long; otherwise, it must be 6 bytes long.
-
-; All other instructions are two bytes long by default.
-
-;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
-;; but getattrtab doesn't understand this.
-(define_attr "length" ""
-  (cond [(eq_attr "type" "cbranch")
-	 (cond [(eq_attr "short_cbranch_p" "yes")
-		(const_int 2)
-		(eq_attr "med_cbranch_p" "yes")
-		(const_int 6)
-		(eq_attr "braf_cbranch_p" "yes")
-		(const_int 12)
-;; ??? using pc is not computed transitively.
-		(ne (match_dup 0) (match_dup 0))
-		(const_int 14)
-		] (const_int 16))
-	 (eq_attr "type" "jump")
-	 (cond [(eq_attr "med_branch_p" "yes")
-		(const_int 2)
-		(and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
-			 (symbol_ref "INSN"))
-		     (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
-			 (symbol_ref "code_for_indirect_jump_scratch")))
-		(if_then_else (eq_attr "braf_branch_p" "yes")
-			      (const_int 6)
-			      (const_int 10))
-		(eq_attr "braf_branch_p" "yes")
-		(const_int 10)
-;; ??? using pc is not computed transitively.
-		(ne (match_dup 0) (match_dup 0))
-		(const_int 12)
-		] (const_int 14))
-	 ] (const_int 2)))
-
-;; (define_function_unit {name} {num-units} {n-users} {test}
-;;                       {ready-delay} {issue-delay} [{conflict-list}])
-
-;; Load and store instructions save a cycle if they are aligned on a
-;; four byte boundary.  Using a function unit for stores encourages
-;; gcc to separate load and store instructions by one instruction,
-;; which makes it more likely that the linker will be able to word
-;; align them when relaxing.
-
-;; Loads have a latency of two.
-;; However, call insns can have a delay slot, so that we want one more
-;; insn to be scheduled between the load of the function address and the call.
-;; This is equivalent to a latency of three.
-;; We cannot use a conflict list for this, because we need to distinguish
-;; between the actual call address and the function arguments.
-;; ADJUST_COST can only properly handle reductions of the cost, so we
-;; use a latency of three here.
-;; We only do this for SImode loads of general registers, to make the work
-;; for ADJUST_COST easier.
-(define_function_unit "memory" 1 0
-  (and (eq_attr "issues" "1")
-       (eq_attr "type" "load_si,pcload_si"))
-  3 2)
-(define_function_unit "memory" 1 0
-  (and (eq_attr "issues" "1")
-       (eq_attr "type" "load,pcload,pload,store,pstore"))
-  2 2)
-
-(define_function_unit "int"    1 0
-  (and (eq_attr "issues" "1") (eq_attr "type" "arith3,arith3b")) 3 3)
-
-(define_function_unit "int"    1 0
-  (and (eq_attr "issues" "1") (eq_attr "type" "dyn_shift")) 2 2)
-
-(define_function_unit "int"    1 0
-  (and (eq_attr "issues" "1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
-
-;; ??? These are approximations.
-(define_function_unit "mpy"    1 0
-  (and (eq_attr "issues" "1") (eq_attr "type" "smpy")) 2 2)
-(define_function_unit "mpy"    1 0
-  (and (eq_attr "issues" "1") (eq_attr "type" "dmpy")) 3 3)
-
-(define_function_unit "fp"     1 0
-  (and (eq_attr "issues" "1") (eq_attr "type" "fp,fmove")) 2 1)
-(define_function_unit "fp"     1 0
-  (and (eq_attr "issues" "1") (eq_attr "type" "fdiv")) 13 12)
-
-
-;; SH4 scheduling
-;; The SH4 is a dual-issue implementation, thus we have to multiply all
-;; costs by at least two.
-;; There will be single increments of the modeled that don't correspond
-;; to the actual target ;; whenever two insns to be issued depend one a
-;; single resource, and the scheduler picks to be the first one.
-;; If we multiplied the costs just by two, just two of these single
-;; increments would amount to an actual cycle.  By picking a larger
-;; factor, we can ameliorate the effect; However, we then have to make sure
-;; that only two insns are modeled as issued per actual cycle.
-;; Moreover, we need a way to specify the latency of insns that don't
-;; use an actual function unit.
-;; We use an 'issue' function unit to do that, and a cost factor of 10.
-
-(define_function_unit "issue" 2 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "!nil,arith3"))
-  10 10)
-
-(define_function_unit "issue" 2 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "arith3"))
-  30 30)
-
-;; There is no point in providing exact scheduling information about branches,
-;; because they are at the starts / ends of basic blocks anyways.
-
-;; Some insns cannot be issued before/after another insn in the same cycle,
-;; irrespective of the type of the other insn.
-
-;; default is dual-issue, but can't be paired with an insn that
-;; uses multiple function units.
-(define_function_unit "single_issue"     1 0
-  (and (eq_attr "issues" "2")
-       (eq_attr "type" "!smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul,call,sfunc,arith3,arith3b"))
-  1 10
-  [(eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul")])
-
-(define_function_unit "single_issue"     1 0
-  (and (eq_attr "issues" "2")
-       (eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul"))
-  10 10
-  [(const_int 1)])
-
-;; arith3 insns are always pairable at the start, but not inecessarily at
-;; the end; however, there doesn;t seem to be a way to express that.
-(define_function_unit "single_issue"     1 0
-  (and (eq_attr "issues" "2")
-       (eq_attr "type" "arith3"))
-  30 20
-  [(const_int 1)])
-
-;; arith3b insn are pairable at the end and have latency that prevents pairing
-;; with the following branch, but we don't want this latency be respected;
-;; When the following branch is immediately adjacent, we can redirect the
-;; internal branch, which is likly to be a larger win.
-(define_function_unit "single_issue"     1 0
-  (and (eq_attr "issues" "2")
-       (eq_attr "type" "arith3b"))
-  20 20
-  [(const_int 1)])
-
-;; calls introduce a longisch delay that is likely to flush the pipelines.
-(define_function_unit "single_issue"     1 0
-  (and (eq_attr "issues" "2")
-       (eq_attr "type" "call,sfunc"))
-  160 160
-  [(eq_attr "type" "!call") (eq_attr "type" "call")])
-
-;; Load and store instructions have no alignment peculiarities for the SH4,
-;; but they use the load-store unit, which they share with the fmove type
-;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
-;; Loads have a latency of two.
-;; However, call insns can only paired with a preceding insn, and have
-;; a delay slot, so that we want two more insns to be scheduled between the
-;; load of the function address and the call.  This is equivalent to a
-;; latency of three.
-;; We cannot use a conflict list for this, because we need to distinguish
-;; between the actual call address and the function arguments.
-;; ADJUST_COST can only properly handle reductions of the cost, so we
-;; use a latency of three here, which gets multiplied by 10 to yield 30.
-;; We only do this for SImode loads of general registers, to make the work
-;; for ADJUST_COST easier.
-
-;; When specifying different latencies for different insns using the
-;; the same function unit, genattrtab.c assumes a 'FIFO constraint'
-;; so that the blockage is at least READY-COST (E) + 1 - READY-COST (C)
-;; for an executing insn E and a candidate insn C.
-;; Therefore, we define three different function units for load_store:
-;; load_store, load and load_si.
-
-(define_function_unit "load_si" 1 0
-  (and (eq_attr "issues" "2")
-       (eq_attr "type" "load_si,pcload_si")) 30 10)
-(define_function_unit "load" 1 0
-  (and (eq_attr "issues" "2")
-       (eq_attr "type" "load,pcload,pload")) 20 10)
-(define_function_unit "load_store" 1 0
-  (and (eq_attr "issues" "2")
-       (eq_attr "type" "load_si,pcload_si,load,pcload,pload,store,pstore,fmove"))
-  10 10)
-
-(define_function_unit "int"    1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "arith,dyn_shift")) 10 10)
-
-;; Again, we have to pretend a lower latency for the "int" unit to avoid a
-;; spurious FIFO constraint; the multiply instructions use the "int"
-;; unit actually only for two cycles.
-(define_function_unit "int"    1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 20 20)
-
-;; We use a fictous "mpy" unit to express the actual latency.
-(define_function_unit "mpy"    1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 20)
-
-;; Again, we have to pretend a lower latency for the "int" unit to avoid a
-;; spurious FIFO constraint.
-(define_function_unit "int"     1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 10 10)
-
-;; We use a fictous "gp_fpul" unit to express the actual latency.
-(define_function_unit "gp_fpul"     1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 20 10)
-
-;; ??? multiply uses the floating point unit, but with a two cycle delay.
-;; Thus, a simple single-precision fp operation could finish if issued in
-;; the very next cycle, but stalls when issued two or three cycles later.
-;; Similarily, a divide / sqrt can work without stalls if issued in
-;; the very next cycle, while it would have to block if issued two or
-;; three cycles later.
-;; There is no way to model this with gcc's function units.  This problem is
-;; actually mentioned in md.texi.  Tackling this problem requires first that
-;; it is possible to speak about the target in an open discussion.
-;; 
-;; However, simple double-precision operations always conflict.
-
-(define_function_unit "fp"    1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 40
-  [(eq_attr "type" "dfp_cmp,dfp_conv,dfp_arith")])
-
-;; The "fp" unit is for pipeline stages F1 and F2.
-
-(define_function_unit "fp"     1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "fp")) 30 10)
-
-;; Again, we have to pretend a lower latency for the "fp" unit to avoid a
-;; spurious FIFO constraint; the bulk of the fdiv type insns executes in
-;; the F3 stage.
-(define_function_unit "fp"     1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 30 10)
-
-;; The "fdiv" function unit models the aggregate effect of the F1, F2 and F3
-;; pipeline stages on the pipelining of fdiv/fsqrt insns.
-;; We also use it to give the actual latency here.
-;; fsqrt is actually one cycle faster than fdiv (and the value used here),
-;; but that will hardly matter in practice for scheduling.
-(define_function_unit "fdiv"     1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 120 100)
-
-;; There is again a late use of the "fp" unit by [d]fdiv type insns
-;; that we can't express.
-
-(define_function_unit "fp"     1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "dfp_cmp,dfp_conv")) 40 20)
-
-(define_function_unit "fp"     1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "dfp_arith")) 80 60)
-
-(define_function_unit "fp"     1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 10)
-
-(define_function_unit "fdiv"     1 0
-  (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 210)
-
-; Definitions for filling branch delay slots.
-
-(define_attr "needs_delay_slot" "yes,no" (const_string "no"))
-
-;; ??? This should be (nil) instead of (const_int 0)
-(define_attr "hit_stack" "yes,no"
-	(cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, 15)") (const_int 0))
-	       (const_string "no")]
-	      (const_string "yes")))
-
-(define_attr "interrupt_function" "no,yes"
-  (const (symbol_ref "pragma_interrupt")))
-
-(define_attr "in_delay_slot" "yes,no"
-  (cond [(eq_attr "type" "cbranch") (const_string "no")
-	 (eq_attr "type" "pcload,pcload_si") (const_string "no")
-	 (eq_attr "needs_delay_slot" "yes") (const_string "no")
-	 (eq_attr "length" "2") (const_string "yes")
-	 ] (const_string "no")))
-
-(define_attr "is_sfunc" ""
-  (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
-
-(define_delay
-  (eq_attr "needs_delay_slot" "yes")
-  [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
-
-;; On the SH and SH2, the rte instruction reads the return pc from the stack,
-;; and thus we can't put a pop instruction in its delay slot.
-;; ??? On the SH3, the rte instruction does not use the stack, so a pop
-;; instruction can go in the delay slot.
-
-;; Since a normal return (rts) implicitly uses the PR register,
-;; we can't allow PR register loads in an rts delay slot.
-
-(define_delay
-  (eq_attr "type" "return")
-  [(and (eq_attr "in_delay_slot" "yes")
-	(ior (and (eq_attr "interrupt_function" "no")
-		  (eq_attr "type" "!pload"))
-	     (and (eq_attr "interrupt_function" "yes")
-		  (eq_attr "hit_stack" "no")))) (nil) (nil)])
-
-;; Since a call implicitly uses the PR register, we can't allow
-;; a PR register store in a jsr delay slot.
-
-(define_delay
-  (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
-  [(and (eq_attr "in_delay_slot" "yes")
-	(eq_attr "type" "!pstore")) (nil) (nil)])
-
-;; Say that we have annulled true branches, since this gives smaller and
-;; faster code when branches are predicted as not taken.
-
-(define_delay
-  (and (eq_attr "type" "cbranch")
-       (ne (symbol_ref "TARGET_SH2") (const_int 0)))
-  [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)])
-
-;; -------------------------------------------------------------------------
-;; SImode signed integer comparisons
-;; -------------------------------------------------------------------------
-
-(define_insn ""
-  [(set (reg:SI 18)
-	(eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
-		       (match_operand:SI 1 "arith_operand" "L,r"))
-	       (const_int 0)))]
-  ""
-  "tst	%1,%0")
-
-;; ??? Perhaps should only accept reg/constant if the register is reg 0.
-;; That would still allow reload to create cmpi instructions, but would
-;; perhaps allow forcing the constant into a register when that is better.
-;; Probably should use r0 for mem/imm compares, but force constant into a
-;; register for pseudo/imm compares.
-
-(define_insn "cmpeqsi_t"
-  [(set (reg:SI 18) (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
-			   (match_operand:SI 1 "arith_operand" "N,rI,r")))]
-  ""
-  "@
-	tst	%0,%0
-	cmp/eq	%1,%0
-	cmp/eq	%1,%0")
-
-(define_insn "cmpgtsi_t"
-  [(set (reg:SI 18) (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
-			   (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
-  ""
-  "@
-	cmp/gt	%1,%0
-	cmp/pl	%0")
-
-(define_insn "cmpgesi_t"
-  [(set (reg:SI 18) (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
-			   (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
-  ""
-  "@
-	cmp/ge	%1,%0
-	cmp/pz	%0")
-
-;; -------------------------------------------------------------------------
-;; SImode unsigned integer comparisons
-;; -------------------------------------------------------------------------
-
-(define_insn "cmpgeusi_t"
-  [(set (reg:SI 18) (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
-			    (match_operand:SI 1 "arith_reg_operand" "r")))]
-  ""
-  "cmp/hs	%1,%0")
-
-(define_insn "cmpgtusi_t"
-  [(set (reg:SI 18) (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
-			    (match_operand:SI 1 "arith_reg_operand" "r")))]
-  ""
-  "cmp/hi	%1,%0")
-
-;; We save the compare operands in the cmpxx patterns and use them when
-;; we generate the branch.
-
-(define_expand "cmpsi"
-  [(set (reg:SI 18) (compare (match_operand:SI 0 "arith_operand" "")
-			     (match_operand:SI 1 "arith_operand" "")))]
-  ""
-  "
-{
-  sh_compare_op0 = operands[0];
-  sh_compare_op1 = operands[1];
-  DONE;
-}")
-
-;; -------------------------------------------------------------------------
-;; DImode signed integer comparisons
-;; -------------------------------------------------------------------------
-
-;; ??? Could get better scheduling by splitting the initial test from the
-;; rest of the insn after reload.  However, the gain would hardly justify
-;; the sh.md size increase necessary to do that.
-
-(define_insn ""
-  [(set (reg:SI 18)
-	(eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
-		       (match_operand:DI 1 "arith_operand" "r"))
-	       (const_int 0)))]
-  ""
-  "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
-				 insn, operands);"
-  [(set_attr "length" "6")
-   (set_attr "type" "arith3b")])
-
-(define_insn "cmpeqdi_t"
-  [(set (reg:SI 18) (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
-			   (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
-  ""
-  "*
-  return output_branchy_insn
-   (EQ,
-    (which_alternative
-     ? \"cmp/eq\\t%S1,%S0\;bf\\t%l9\;cmp/eq\\t%R1,%R0\"
-     : \"tst\\t%S0,%S0\;bf\\t%l9\;tst\\t%R0,%R0\"),
-    insn, operands);"
-  [(set_attr "length" "6")
-   (set_attr "type" "arith3b")])
-
-(define_insn "cmpgtdi_t"
-  [(set (reg:SI 18) (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
-			   (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
-  "TARGET_SH2"
-  "@
-	cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
-	tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
-  [(set_attr "length" "8")
-   (set_attr "type" "arith3")])
-
-(define_insn "cmpgedi_t"
-  [(set (reg:SI 18) (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
-			   (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
-  "TARGET_SH2"
-  "@
-	cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
-	cmp/pz\\t%S0"
-  [(set_attr "length" "8,2")
-   (set_attr "type" "arith3,arith")])
-
-;; -------------------------------------------------------------------------
-;; DImode unsigned integer comparisons
-;; -------------------------------------------------------------------------
-
-(define_insn "cmpgeudi_t"
-  [(set (reg:SI 18) (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
-			    (match_operand:DI 1 "arith_reg_operand" "r")))]
-  "TARGET_SH2"
-  "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
-  [(set_attr "length" "8")
-   (set_attr "type" "arith3")])
-
-(define_insn "cmpgtudi_t"
-  [(set (reg:SI 18) (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
-			    (match_operand:DI 1 "arith_reg_operand" "r")))]
-  "TARGET_SH2"
-  "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
-  [(set_attr "length" "8")
-   (set_attr "type" "arith3")])
-
-;; We save the compare operands in the cmpxx patterns and use them when
-;; we generate the branch.
-
-(define_expand "cmpdi"
-  [(set (reg:SI 18) (compare (match_operand:DI 0 "arith_operand" "")
-			     (match_operand:DI 1 "arith_operand" "")))]
-  "TARGET_SH2"
-  "
-{
-  sh_compare_op0 = operands[0];
-  sh_compare_op1 = operands[1];
-  DONE;
-}")
-
-;; -------------------------------------------------------------------------
-;; Addition instructions
-;; -------------------------------------------------------------------------
-
-;; ??? This should be a define expand.
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
-	(plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
-		 (match_operand:DI 2 "arith_reg_operand" "r")))
-   (clobber (reg:SI 18))]
-  ""
-  "#"
-  [(set_attr "length" "6")])
-
-(define_split
-  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
-	(plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
-		 (match_operand:DI 2 "arith_reg_operand" "r")))
-   (clobber (reg:SI 18))]
-  "reload_completed"
-  [(const_int 0)]
-  "
-{
-  rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
-  high0 = gen_rtx (REG, SImode,
-		   true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
-  high2 = gen_rtx (REG, SImode,
-		   true_regnum (operands[2]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
-  emit_insn (gen_clrt ());
-  emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
-  emit_insn (gen_addc1 (high0, high0, high2));
-  DONE;
-}")
-
-(define_insn "addc"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
-			  (match_operand:SI 2 "arith_reg_operand" "r"))
-		 (reg:SI 18)))
-   (set (reg:SI 18)
-	(ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
-  ""
-  "addc	%2,%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "addc1"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
-			  (match_operand:SI 2 "arith_reg_operand" "r"))
-		 (reg:SI 18)))
-   (clobber (reg:SI 18))]
-  ""
-  "addc	%2,%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(plus:SI (match_operand:SI 1 "arith_operand" "%0")
-		 (match_operand:SI 2 "arith_operand" "rI")))]
-  ""
-  "add	%2,%0"
-  [(set_attr "type" "arith")])
-
-;; -------------------------------------------------------------------------
-;; Subtraction instructions
-;; -------------------------------------------------------------------------
-
-;; ??? This should be a define expand.
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
-	(minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
-		 (match_operand:DI 2 "arith_reg_operand" "r")))
-   (clobber (reg:SI 18))]
-  ""
-  "#"
-  [(set_attr "length" "6")])
-
-(define_split
-  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
-	(minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
-		  (match_operand:DI 2 "arith_reg_operand" "r")))
-   (clobber (reg:SI 18))]
-  "reload_completed"
-  [(const_int 0)]
-  "
-{
-  rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
-  high0 = gen_rtx (REG, SImode,
-		   true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
-  high2 = gen_rtx (REG, SImode,
-		   true_regnum (operands[2]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
-  emit_insn (gen_clrt ());
-  emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
-  emit_insn (gen_subc1 (high0, high0, high2));
-  DONE;
-}")
-
-(define_insn "subc"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
-			    (match_operand:SI 2 "arith_reg_operand" "r"))
-		  (reg:SI 18)))
-   (set (reg:SI 18)
-	(gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
-  ""
-  "subc	%2,%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "subc1"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
-			    (match_operand:SI 2 "arith_reg_operand" "r"))
-		  (reg:SI 18)))
-   (clobber (reg:SI 18))]
-  ""
-  "subc	%2,%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "*subsi3_internal"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		  (match_operand:SI 2 "arith_reg_operand" "r")))]
-  ""
-  "sub	%2,%0"
-  [(set_attr "type" "arith")])
-
-;; Convert `constant - reg' to `neg rX; add rX, #const' since this
-;; will sometimes save one instruction.  Otherwise we might get
-;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
-;; are the same.
-
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(minus:SI (match_operand:SI 1 "arith_operand" "")
-		  (match_operand:SI 2 "arith_reg_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      emit_insn (gen_negsi2 (operands[0], operands[2]));
-      emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
-      DONE;
-    }
-}")
-
-;; -------------------------------------------------------------------------
-;; Division instructions
-;; -------------------------------------------------------------------------
-
-;; We take advantage of the library routines which don't clobber as many
-;; registers as a normal function call would.
-
-;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
-;; also has an effect on the register that holds the address of the sfunc.
-;; To make this work, we have an extra dummy insns that shows the use
-;; of this register for reorg.
-
-(define_insn "use_sfunc_addr"
-  [(set (reg:SI 17) (unspec [(match_operand:SI 0 "register_operand" "r")] 5))]
-  ""
-  ""
-  [(set_attr "length" "0")])
-
-;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
-;; hard register 0.  If we used hard register 0, then the next instruction
-;; would be a move from hard register 0 to a pseudo-reg.  If the pseudo-reg
-;; gets allocated to a stack slot that needs its address reloaded, then
-;; there is nothing to prevent reload from using r0 to reload the address.
-;; This reload would clobber the value in r0 we are trying to store.
-;; If we let reload allocate r0, then this problem can never happen.
-
-(define_insn "udivsi3_i1"
-  [(set (match_operand:SI 0 "register_operand" "=z")
-	(udiv:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 18))
-   (clobber (reg:SI 17))
-   (clobber (reg:SI 4))
-   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
-  "! TARGET_SH4"
-  "jsr	@%1%#"
-  [(set_attr "type" "sfunc")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_insn "udivsi3_i4"
-  [(set (match_operand:SI 0 "register_operand" "=y")
-	(udiv:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 17))
-   (clobber (reg:DF 24))
-   (clobber (reg:DF 26))
-   (clobber (reg:DF 28))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 1))
-   (clobber (reg:SI 4))
-   (clobber (reg:SI 5))
-   (use (reg:PSI 48))
-   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
-  "TARGET_SH4 && ! TARGET_FPU_SINGLE"
-  "jsr	@%1%#"
-  [(set_attr "type" "sfunc")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_insn "udivsi3_i4_single"
-  [(set (match_operand:SI 0 "register_operand" "=y")
-	(udiv:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 17))
-   (clobber (reg:DF 24))
-   (clobber (reg:DF 26))
-   (clobber (reg:DF 28))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 1))
-   (clobber (reg:SI 4))
-   (clobber (reg:SI 5))
-   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
-  "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
-  "jsr	@%1%#"
-  [(set_attr "type" "sfunc")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_expand "udivsi3"
-  [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
-   (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
-   (set (match_dup 3) (symbol_ref:SI "__udivsi3"))
-   (parallel [(set (match_operand:SI 0 "register_operand" "")
-		   (udiv:SI (reg:SI 4)
-			    (reg:SI 5)))
-	      (clobber (reg:SI 18))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 4))
-	      (use (match_dup 3))])]
-  ""
-  "
-{
-  rtx first, last;
-
-  first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
-  emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
-  operands[3] = gen_reg_rtx(SImode);
-  if (TARGET_HARD_SH4)
-    {
-      emit_move_insn (operands[3],
-		      gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
-      if (TARGET_FPU_SINGLE)
-	last = emit_insn (gen_udivsi3_i4_single (operands[0], operands[3]));
-      else
-	last = emit_insn (gen_udivsi3_i4 (operands[0], operands[3]));
-    }
-  else
-    {
-      emit_move_insn (operands[3],
-		      gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
-      last = emit_insn (gen_udivsi3_i1 (operands[0], operands[3]));
-    }
-  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
-     invariant code motion can move it.  */
-  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
-  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
-  DONE;
-}")
-
-(define_insn "divsi3_i1"
-  [(set (match_operand:SI 0 "register_operand" "=z")
-	(div:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 18))
-   (clobber (reg:SI 17))
-   (clobber (reg:SI 1))
-   (clobber (reg:SI 2))
-   (clobber (reg:SI 3))
-   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
-  "! TARGET_SH4"
-  "jsr	@%1%#"
-  [(set_attr "type" "sfunc")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_insn "divsi3_i4"
-  [(set (match_operand:SI 0 "register_operand" "=y")
-	(div:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 17))
-   (clobber (reg:DF 24))
-   (clobber (reg:DF 26))
-   (use (reg:PSI 48))
-   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
-  "TARGET_SH4 && ! TARGET_FPU_SINGLE"
-  "jsr	@%1%#"
-  [(set_attr "type" "sfunc")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_insn "divsi3_i4_single"
-  [(set (match_operand:SI 0 "register_operand" "=y")
-	(div:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 17))
-   (clobber (reg:DF 24))
-   (clobber (reg:DF 26))
-   (clobber (reg:SI 2))
-   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
-  "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
-  "jsr	@%1%#"
-  [(set_attr "type" "sfunc")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_expand "divsi3"
-  [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
-   (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
-   (set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
-   (parallel [(set (match_operand:SI 0 "register_operand" "")
-		   (div:SI (reg:SI 4)
-			   (reg:SI 5)))
-	      (clobber (reg:SI 18))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 1))
-	      (clobber (reg:SI 2))
-	      (clobber (reg:SI 3))
-	      (use (match_dup 3))])]
-  ""
-  "
-{
-  rtx first, last;
-
-  first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
-  emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
-  operands[3] = gen_reg_rtx(SImode);
-  if (TARGET_HARD_SH4)
-    {
-      emit_move_insn (operands[3],
-		      gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
-      if (TARGET_FPU_SINGLE)
-	last = emit_insn (gen_divsi3_i4_single (operands[0], operands[3]));
-      else
-	last = emit_insn (gen_divsi3_i4 (operands[0], operands[3]));
-    }
-  else
-    {
-      emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
-      last = emit_insn (gen_divsi3_i1 (operands[0], operands[3]));
-    }
-  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
-     invariant code motion can move it.  */
-  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
-  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
-  DONE;
-}")
-
-;; -------------------------------------------------------------------------
-;; Multiplication instructions
-;; -------------------------------------------------------------------------
-
-(define_insn "umulhisi3_i"
-  [(set (reg:SI 21)
-	(mult:SI (zero_extend:SI (match_operand:HI 0 "arith_reg_operand" "r"))
-		 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r"))))]
-  ""
-  "mulu	%1,%0"
-  [(set_attr "type" "smpy")])
-
-(define_insn "mulhisi3_i"
-  [(set (reg:SI 21)
-	(mult:SI (sign_extend:SI
-		  (match_operand:HI 0 "arith_reg_operand" "r"))
-		 (sign_extend:SI
-		  (match_operand:HI 1 "arith_reg_operand" "r"))))]
-  ""
-  "muls	%1,%0"
-  [(set_attr "type" "smpy")])
-
-(define_expand "mulhisi3"
-  [(set (reg:SI 21)
-	(mult:SI (sign_extend:SI
-		  (match_operand:HI 1 "arith_reg_operand" ""))
-		 (sign_extend:SI
-		  (match_operand:HI 2 "arith_reg_operand" ""))))
-   (set (match_operand:SI 0 "arith_reg_operand" "")
-	(reg:SI 21))]
-  ""
-  "
-{
-  rtx first, last;
-
-  first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
-  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 21));
-  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
-     invariant code motion can move it.  */
-  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
-  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
-  DONE;
-}")
-
-(define_expand "umulhisi3"
-  [(set (reg:SI 21)
-	(mult:SI (zero_extend:SI
-		  (match_operand:HI 1 "arith_reg_operand" ""))
-		 (zero_extend:SI
-		  (match_operand:HI 2 "arith_reg_operand" ""))))
-   (set (match_operand:SI 0 "arith_reg_operand" "")
-	(reg:SI 21))]
-  ""
-  "
-{
-  rtx first, last;
-
-  first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
-  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 21));
-  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
-     invariant code motion can move it.  */
-  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
-  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
-  DONE;
-}")
-
-;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
-;; a call to a routine which clobbers known registers.
-
-(define_insn ""
-  [(set (match_operand:SI 1 "register_operand" "=z")
-	(mult:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 21))
-   (clobber (reg:SI 18))
-   (clobber (reg:SI 17))
-   (clobber (reg:SI 3))
-   (clobber (reg:SI 2))
-   (clobber (reg:SI 1))
-   (use (match_operand:SI 0 "arith_reg_operand" "r"))]
-  ""
-  "jsr	@%0%#"
-  [(set_attr "type" "sfunc")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_expand "mulsi3_call"
-  [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
-   (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
-   (parallel[(set (match_operand:SI 0 "register_operand" "")
-		  (mult:SI (reg:SI 4)
-			   (reg:SI 5)))
-	     (clobber (reg:SI 21))
-	     (clobber (reg:SI 18))
-	     (clobber (reg:SI 17))
-	     (clobber (reg:SI 3))
-	     (clobber (reg:SI 2))
-	     (clobber (reg:SI 1))
-	     (use (match_operand:SI 3 "register_operand" ""))])]
-  ""
-  "")
-
-(define_insn "mul_l"
-  [(set (reg:SI 21)
-	(mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
-		 (match_operand:SI 1 "arith_reg_operand" "r")))]
-  "TARGET_SH2"
-  "mul.l	%1,%0"
-  [(set_attr "type" "dmpy")])
-
-(define_expand "mulsi3"
-  [(set (reg:SI 21)
-	(mult:SI  (match_operand:SI 1 "arith_reg_operand" "")
-		  (match_operand:SI 2 "arith_reg_operand" "")))
-   (set (match_operand:SI 0 "arith_reg_operand" "")
-	(reg:SI 21))]
-  ""
-  "
-{
-  rtx first, last;
-
-  if (!TARGET_SH2)
-    {
-      /* The address must be set outside the libcall,
-	 since it goes into a pseudo.  */
-      rtx addr = force_reg (SImode, gen_rtx_SYMBOL_REF (SImode, \"__mulsi3\"));
-      rtx insns = gen_mulsi3_call (operands[0], operands[1], operands[2], addr);
-      first = XVECEXP (insns, 0, 0);
-      last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
-      emit_insn (insns);
-    }
-  else
-    {
-      rtx macl = gen_rtx_REG (SImode, MACL_REG);
-      first = emit_insn (gen_mul_l (operands[1], operands[2]));
-      last = emit_insn (gen_movsi_i ((operands[0]), macl));
-    }
-  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
-     invariant code motion can move it.  */
-  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
-  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
-  DONE;
-}")
-
-(define_insn "mulsidi3_i"
-  [(set (reg:SI 20)
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
-			       (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
-		      (const_int 32))))
-   (set (reg:SI 21)
-	(mult:SI (match_dup 0)
-		 (match_dup 1)))]
-  "TARGET_SH2"
-  "dmuls.l	%1,%0"
-  [(set_attr "type" "dmpy")])
-
-(define_insn "mulsidi3"
-  [(set (match_operand:DI 0 "arith_reg_operand" "r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
-		 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
-   (clobber (reg:DI 20))]
-  "TARGET_SH2"
-  "#")
-
-(define_split
-  [(set (match_operand:DI 0 "arith_reg_operand" "")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
-		 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
-   (clobber (reg:DI 20))]
-  "TARGET_SH2"
-  [(const_int 0)]
-  "
-{
-  rtx low_dst = gen_lowpart (SImode, operands[0]);
-  rtx high_dst = gen_highpart (SImode, operands[0]);
-
-  emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
-
-  emit_move_insn (low_dst, gen_rtx_REG (SImode, 21));
-  emit_move_insn (high_dst, gen_rtx_REG (SImode, 20));
-  /* We need something to tag the possible REG_EQUAL notes on to.  */
-  emit_move_insn (operands[0], operands[0]);
-  DONE;
-}")
-
-(define_insn "umulsidi3_i"
-  [(set (reg:SI 20)
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
-			       (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
-		      (const_int 32))))
-   (set (reg:SI 21)
-	(mult:SI (match_dup 0)
-		 (match_dup 1)))]
-  "TARGET_SH2"
-  "dmulu.l	%1,%0"
-  [(set_attr "type" "dmpy")])
-
-(define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "arith_reg_operand" "r")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
-		 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
-   (clobber (reg:DI 20))]
-  "TARGET_SH2"
-  "#")
-
-(define_split
-  [(set (match_operand:DI 0 "arith_reg_operand" "")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
-		 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
-   (clobber (reg:DI 20))]
-  "TARGET_SH2"
-  [(const_int 0)]
-  "
-{
-  rtx low_dst = gen_lowpart (SImode, operands[0]);
-  rtx high_dst = gen_highpart (SImode, operands[0]);
-
-  emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
-
-  emit_move_insn (low_dst, gen_rtx_REG (SImode, 21));
-  emit_move_insn (high_dst, gen_rtx_REG (SImode, 20));
-  /* We need something to tag the possible REG_EQUAL notes on to.  */
-  emit_move_insn (operands[0], operands[0]);
-  DONE;
-}")
-
-(define_insn "smulsi3_highpart_i"
-  [(set (reg:SI 20)
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
-			       (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
-		      (const_int 32))))
-   (clobber (reg:SI 21))]
-  "TARGET_SH2"
-  "dmuls.l	%1,%0"
-  [(set_attr "type" "dmpy")])
-
-(define_expand "smulsi3_highpart"
-  [(parallel [(set (reg:SI 20)
-		   (truncate:SI
-		    (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
-					  (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
-				 (const_int 32))))
-	      (clobber (reg:SI 21))])
-   (set (match_operand:SI 0 "arith_reg_operand" "")
-	(reg:SI 20))]
-  "TARGET_SH2"
-  "
-{
-  rtx first, last;
-
-  first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
-  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 20));
-  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
-     invariant code motion can move it.  */
-  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
-  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
-  DONE;
-}")
-
-(define_insn "umulsi3_highpart_i"
-  [(set (reg:SI 20)
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
-			       (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
-		      (const_int 32))))
-   (clobber (reg:SI 21))]
-  "TARGET_SH2"
-  "dmulu.l	%1,%0"
-  [(set_attr "type" "dmpy")])
-
-(define_expand "umulsi3_highpart"
-  [(parallel [(set (reg:SI 20)
-		   (truncate:SI
-		    (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
-					  (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
-				 (const_int 32))))
-	      (clobber (reg:SI 21))])
-   (set (match_operand:SI 0 "arith_reg_operand" "")
-	(reg:SI 20))]
-  "TARGET_SH2"
-  "
-{
-  rtx first, last;
-
-  first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
-  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 20));
-  /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
-     invariant code motion can move it.  */
-  REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
-  REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
-  DONE;
-}")
-
-;; -------------------------------------------------------------------------
-;; Logical operations
-;; -------------------------------------------------------------------------
-
-(define_insn ""
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
-	(and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
-		(match_operand:SI 2 "logical_operand" "r,L")))]
-  ""
-  "and	%2,%0"
-  [(set_attr "type" "arith")])
-
-;; If the constant is 255, then emit a extu.b instruction instead of an
-;; and, since that will give better code.
-
-(define_expand "andsi3"
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(and:SI (match_operand:SI 1 "arith_reg_operand" "")
-		(match_operand:SI 2 "logical_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
-    {
-      emit_insn (gen_zero_extendqisi2 (operands[0],
-				       gen_lowpart (QImode, operands[1])));
-      DONE;
-    }
-}")
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
-	(ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
-		(match_operand:SI 2 "logical_operand" "r,L")))]
-  ""
-  "or	%2,%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
-	(xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
-		(match_operand:SI 2 "logical_operand" "L,r")))]
-  ""
-  "xor	%2,%0"
-  [(set_attr "type" "arith")])
-
-;; -------------------------------------------------------------------------
-;; Shifts and rotates
-;; -------------------------------------------------------------------------
-
-(define_insn "rotlsi3_1"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		   (const_int 1)))
-   (set (reg:SI 18)
-	(lshiftrt:SI (match_dup 1) (const_int 31)))]
-  ""
-  "rotl	%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "rotlsi3_31"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		   (const_int 31)))
-   (clobber (reg:SI 18))]
-  ""
-  "rotr	%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "rotlsi3_16"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
-		   (const_int 16)))]
-  ""
-  "swap.w	%1,%0"
-  [(set_attr "type" "arith")])
-
-(define_expand "rotlsi3"
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
-		   (match_operand:SI 2 "immediate_operand" "")))]
-  ""
-  "
-{
-  static char rot_tab[] = {
-    000, 000, 000, 000, 000, 000, 010, 001,
-    001, 001, 011, 013, 003, 003, 003, 003,
-    003, 003, 003, 003, 003, 013, 012, 002,
-    002, 002, 010, 000, 000, 000, 000, 000,
-  };
-
-  int count, choice;
-
-  if (GET_CODE (operands[2]) != CONST_INT)
-    FAIL;
-  count = INTVAL (operands[2]);
-  choice = rot_tab[count];
-  if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
-    FAIL;
-  choice &= 7;
-  switch (choice)
-    {
-    case 0:
-      emit_move_insn (operands[0], operands[1]);
-      count -= (count & 16) * 2;
-      break;
-    case 3:
-     emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
-     count -= 16;
-     break;
-    case 1:
-    case 2:
-      {
-	rtx parts[2];
-	parts[0] = gen_reg_rtx (SImode);
-	parts[1] = gen_reg_rtx (SImode);
-	emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
-	parts[choice-1] = operands[1];
-	emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
-	emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
-	emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
-	count = (count & ~16) - 8;
-      }
-    }
-
-  for (; count > 0; count--)
-    emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
-  for (; count < 0; count++)
-    emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
-
-  DONE;
-}")
-
-(define_insn "*rotlhi3_8"
-  [(set (match_operand:HI 0 "arith_reg_operand" "=r")
-	(rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
-		   (const_int 8)))]
-  ""
-  "swap.b	%1,%0"
-  [(set_attr "type" "arith")])
-
-(define_expand "rotlhi3"
-  [(set (match_operand:HI 0 "arith_reg_operand" "")
-	(rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
-		   (match_operand:HI 2 "immediate_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
-    FAIL;
-}")
-
-;;
-;; shift left
-
-(define_insn "ashlsi3_d"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		   (match_operand:SI 2 "arith_reg_operand" "r")))]
-  "TARGET_SH3"
-  "shld	%2,%0"
-  [(set_attr "type" "dyn_shift")])
-
-(define_insn "ashlsi3_k"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
-	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
-		   (match_operand:SI 2 "const_int_operand" "M,K")))]
-  "CONST_OK_FOR_K (INTVAL (operands[2]))"
-  "@
-	add	%0,%0
-	shll%O2	%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "ashlhi3_k"
-  [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
-	(ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
-		   (match_operand:HI 2 "const_int_operand" "M,K")))]
-  "CONST_OK_FOR_K (INTVAL (operands[2]))"
-  "@
-	add	%0,%0
-	shll%O2	%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "ashlsi3_n"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		   (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
-  "! sh_dynamicalize_shift_p (operands[2])"
-  "#"
-  [(set (attr "length")
-	(cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
-	       (const_string "2")
-	       (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
-	       (const_string "4")
-	       (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
-	       (const_string "6")]
-	      (const_string "8")))
-   (set_attr "type" "arith")])
-
-(define_split
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
-		   (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
-  ""
-  [(use (reg:SI 0))]
-  "
-{
-  gen_shifty_op (ASHIFT, operands);
-  DONE;
-}")
-
-(define_expand "ashlsi3"
-  [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
-		   (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
-			      (match_operand:SI 2 "nonmemory_operand" "")))
-	      (clobber (reg:SI 18))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && sh_dynamicalize_shift_p (operands[2]))
-    operands[2] = force_reg (SImode, operands[2]);
-  if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
-    {
-      emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-  if (! immediate_operand (operands[2], GET_MODE (operands[2])))
-    FAIL;
-}")
-
-(define_insn "ashlhi3"
-  [(set (match_operand:HI 0 "arith_reg_operand" "=r")
-	(ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
-		   (match_operand:HI 2 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
-  ""
-  "#"
-  [(set (attr "length")
-	(cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
-	       (const_string "2")
-	       (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
-	       (const_string "4")]
-	      (const_string "6")))
-   (set_attr "type" "arith")])
-
-(define_split
-  [(set (match_operand:HI 0 "arith_reg_operand" "")
-	(ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
-		   (match_operand:HI 2 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
-  ""
-  [(use (reg:SI 0))]
-  "
-{
-  gen_shifty_hi_op (ASHIFT, operands);
-  DONE;
-}")
-
-;
-; arithmetic shift right
-;
-
-(define_insn "ashrsi3_k"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "M")))
-   (clobber (reg:SI 18))]
-  "INTVAL (operands[2]) == 1"
-  "shar	%0"
-  [(set_attr "type" "arith")])
-
-;; We can't do HImode right shifts correctly unless we start out with an
-;; explicit zero / sign extension; doing that would result in worse overall
-;; code, so just let the machine independent code widen the mode.
-;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
-
-
-;; ??? This should be a define expand.
-
-(define_insn "ashrsi2_16"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-        (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
-                     (const_int 16)))]
-  ""
-  "#"
-  [(set_attr "length" "4")])
-
-(define_split
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-        (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
-		     (const_int 16)))]
-  ""
-  [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
-   (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
-  "operands[2] = gen_lowpart (HImode, operands[0]);")
-
-;; ??? This should be a define expand.
-
-(define_insn "ashrsi2_31"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		     (const_int 31)))
-   (clobber (reg:SI 18))]
-  ""
-  "#"
-  [(set_attr "length" "4")])
-
-(define_split
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		     (const_int 31)))
-   (clobber (reg:SI 18))]
-  ""
-  [(const_int 0)]
-  "
-{
-  emit_insn (gen_ashlsi_c (operands[0], operands[1]));
-  emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
-  DONE;
-}")
-
-(define_insn "ashlsi_c"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
-   (set (reg:SI 18) (lt:SI (match_dup 1)
-			   (const_int 0)))]
-  ""
-  "shll	%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "ashrsi3_d"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		     (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
-  "TARGET_SH3"
-  "shad	%2,%0"
-  [(set_attr "type" "dyn_shift")])
-
-(define_insn "ashrsi3_n"
-  [(set (reg:SI 4)
-	(ashiftrt:SI (reg:SI 4)
-		     (match_operand:SI 0 "const_int_operand" "i")))
-   (clobber (reg:SI 18))
-   (clobber (reg:SI 17))
-   (use (match_operand:SI 1 "arith_reg_operand" "r"))]
-  ""
-  "jsr	@%1%#"
-  [(set_attr "type" "sfunc")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_expand "ashrsi3"
-  [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
-		   (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
-				(match_operand:SI 2 "nonmemory_operand" "")))
-	      (clobber (reg:SI 18))])]
-  ""
-  "if (expand_ashiftrt (operands)) DONE; else FAIL;")
-
-;; logical shift right
-
-(define_insn "lshrsi3_d"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		     (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
-  "TARGET_SH3"
-  "shld	%2,%0"
-  [(set_attr "type" "dyn_shift")])
-
-;;  Only the single bit shift clobbers the T bit.
-
-(define_insn "lshrsi3_m"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "M")))
-   (clobber (reg:SI 18))]
-  "CONST_OK_FOR_M (INTVAL (operands[2]))"
-  "shlr	%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "lshrsi3_k"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "K")))]
-  "CONST_OK_FOR_K (INTVAL (operands[2]))
-   && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
-  "shlr%O2	%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "lshrsi3_n"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
-		     (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
-  "! sh_dynamicalize_shift_p (operands[2])"
-  "#"
-  [(set (attr "length")
-	(cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
-	       (const_string "2")
-	       (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
-	       (const_string "4")
-	       (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
-	       (const_string "6")]
-	      (const_string "8")))
-   (set_attr "type" "arith")])
-
-(define_split
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
-		     (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
-  ""
-  [(use (reg:SI 0))]
-  "
-{
-  gen_shifty_op (LSHIFTRT, operands);
-  DONE;
-}")
-
-(define_expand "lshrsi3"
-  [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
-		   (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
-				(match_operand:SI 2 "nonmemory_operand" "")))
-	      (clobber (reg:SI 18))])]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && sh_dynamicalize_shift_p (operands[2]))
-    operands[2] = force_reg (SImode, operands[2]);
-  if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
-    {
-      rtx count = copy_to_mode_reg (SImode, operands[2]);
-      emit_insn (gen_negsi2 (count, count));
-      emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
-      DONE;
-    }
-  if (! immediate_operand (operands[2], GET_MODE (operands[2])))
-    FAIL;
-}")
-
-;; ??? This should be a define expand.
-
-(define_insn "ashldi3_k"
-  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
-	(ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
-		   (const_int 1)))
-   (clobber (reg:SI 18))]
-  ""
-  "shll	%R0\;rotcl	%S0"
-  [(set_attr "length" "4")
-   (set_attr "type" "arith")])
-
-(define_expand "ashldi3"
-  [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
-		   (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
-			      (match_operand:DI 2 "immediate_operand" "")))
-	      (clobber (reg:SI 18))])]
-  ""
-  "{ if (GET_CODE (operands[2]) != CONST_INT
-	 || INTVAL (operands[2]) != 1) FAIL;} ")
-
-;; ??? This should be a define expand.
-
-(define_insn "lshrdi3_k"
-  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
-	(lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
-		     (const_int 1)))
-   (clobber (reg:SI 18))]
-  ""
-  "shlr	%S0\;rotcr	%R0"
-  [(set_attr "length" "4")
-   (set_attr "type" "arith")])
-
-(define_expand "lshrdi3"
-  [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
-		   (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
-			       (match_operand:DI 2 "immediate_operand" "")))
-	     (clobber (reg:SI 18))])]
-  ""
-  "{ if (GET_CODE (operands[2]) != CONST_INT
-	 || INTVAL (operands[2]) != 1) FAIL;} ")
-
-;; ??? This should be a define expand.
-
-(define_insn "ashrdi3_k"
-  [(set (match_operand:DI 0 "arith_reg_operand" "=r")
-	(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
-		     (const_int 1)))
-   (clobber (reg:SI 18))]
-  ""
-  "shar	%S0\;rotcr	%R0"
-  [(set_attr "length" "4")
-   (set_attr "type" "arith")])
-
-(define_expand "ashrdi3"
-  [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
-		   (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
-				(match_operand:DI 2 "immediate_operand" "")))
-	      (clobber (reg:SI 18))])]
-  ""
-  "{ if (GET_CODE (operands[2]) != CONST_INT
-	 || INTVAL (operands[2]) != 1) FAIL; } ")
-
-;; combined left/right shift
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
-			   (match_operand:SI 2 "const_int_operand" "n"))
-		(match_operand:SI 3 "const_int_operand" "n")))]
-  "(unsigned)INTVAL (operands[2]) < 32"
-  [(use (reg:SI 0))]
-  "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
-   DONE;")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
-			   (match_operand:SI 2 "const_int_operand" "n"))
-		(match_operand:SI 3 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
-  "(unsigned)INTVAL (operands[2]) < 32"
-  [(use (reg:SI 0))]
-  "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
-   DONE;")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
-			   (match_operand:SI 2 "const_int_operand" "n"))
-		(match_operand:SI 3 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
-  "shl_and_kind (operands[2], operands[3], 0) == 1"
- "#"
-  [(set (attr "length")
-	(cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
-	       (const_string "4")
-	       (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
-	       (const_string "6")
-	       (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
-	       (const_string "8")
-	       (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
-	       (const_string "10")
-	       (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
-	       (const_string "12")
-	       (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
-	       (const_string "14")
-	       (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
-	       (const_string "16")]
-	      (const_string "18")))
-   (set_attr "type" "arith")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=z")
-	(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
-			   (match_operand:SI 2 "const_int_operand" "n"))
-		(match_operand:SI 3 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
-  "shl_and_kind (operands[2], operands[3], 0) == 2"
- "#"
-  [(set (attr "length")
-	(cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
-	       (const_string "4")
-	       (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
-	       (const_string "6")
-	       (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
-	       (const_string "8")]
-	      (const_string "10")))
-   (set_attr "type" "arith")])
-
-;; shift left / and combination with a scratch register: The combine pass
-;; does not accept the individual instructions, even though they are
-;; cheap.  But it needs a precise description so that it is usable after
-;; reload.
-(define_insn "and_shl_scratch"
-  [(set (match_operand:SI 0 "register_operand" "=r,&r")
-	(lshiftrt:SI (ashift:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
-						     (match_operand:SI 2 "const_int_operand" "N,n"))
-					(match_operand:SI 3 "" "0,r"))
-				(match_operand:SI 4 "const_int_operand" "n,n"))
-		     (match_operand:SI 5 "const_int_operand" "n,n")))
-   (clobber (reg:SI 18))]
-  ""
-  "#"
-  [(set (attr "length")
-	(cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
-	       (const_string "4")
-	       (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
-	       (const_string "6")
-	       (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
-	       (const_string "8")
-	       (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
-	       (const_string "10")]
-	      (const_string "12")))
-   (set_attr "type" "arith")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r,&r")
-	(lshiftrt:SI (ashift:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
-						     (match_operand:SI 2 "const_int_operand" "N,n"))
-					(match_operand:SI 3 "register_operand" "0,r"))
-				(match_operand:SI 4 "const_int_operand" "n,n"))
-		     (match_operand:SI 5 "const_int_operand" "n,n")))
-   (clobber (reg:SI 18))]
-  ""
-  [(use (reg:SI 0))]
-  "
-{
-  rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
-
-  if (INTVAL (operands[2]))
-    {
-      gen_shifty_op (LSHIFTRT, operands);
-    }
-  emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
-  operands[2] = operands[4];
-  gen_shifty_op (ASHIFT, operands);
-  if (INTVAL (operands[5]))
-    {
-      operands[2] = operands[5];
-      gen_shifty_op (LSHIFTRT, operands);
-    }
-  DONE;
-}")
-
-;; signed left/right shift combination.
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-				    (match_operand:SI 2 "const_int_operand" "n"))
-			 (match_operand:SI 3 "const_int_operand" "n")
-			 (const_int 0)))
-   (clobber (reg:SI 18))]
-  ""
-  [(use (reg:SI 0))]
-  "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
-   DONE;")
-
-(define_insn "shl_sext_ext"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
-				    (match_operand:SI 2 "const_int_operand" "n"))
-			 (match_operand:SI 3 "const_int_operand" "n")
-			 (const_int 0)))
-   (clobber (reg:SI 18))]
-  "(unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
-  "#"
-  [(set (attr "length")
-	(cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
-	       (const_string "2")
-	       (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
-	       (const_string "4")
-	       (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
-	       (const_string "6")
-	       (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
-	       (const_string "8")
-	       (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
-	       (const_string "10")
-	       (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
-	       (const_string "12")
-	       (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
-	       (const_string "14")
-	       (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
-	       (const_string "16")]
-	      (const_string "18")))
-    (set_attr "type" "arith")])
-
-(define_insn "shl_sext_sub"
-  [(set (match_operand:SI 0 "register_operand" "=z")
-        (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
-				    (match_operand:SI 2 "const_int_operand" "n"))
-			 (match_operand:SI 3 "const_int_operand" "n")
-			 (const_int 0)))
-   (clobber (reg:SI 18))]
-  "(shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
-  "#"
-  [(set (attr "length")
-	(cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
-	       (const_string "6")
-	       (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
-	       (const_string "8")
-	       (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
-	       (const_string "10")
-	       (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
-	       (const_string "12")]
-	      (const_string "14")))
-    (set_attr "type" "arith")])
-
-;; These patterns are found in expansions of DImode shifts by 16, and
-;; allow the xtrct instruction to be generated from C source.
-
-(define_insn "xtrct_left"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-        (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
-			   (const_int 16))
- 	        (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
-			     (const_int 16))))]
-  ""
-  "xtrct	%1,%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "xtrct_right"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-        (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
-			     (const_int 16))
- 	        (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
-			   (const_int 16))))]
-  ""
-  "xtrct	%2,%0"
-  [(set_attr "type" "arith")])
-
-;; -------------------------------------------------------------------------
-;; Unary arithmetic
-;; -------------------------------------------------------------------------
-
-(define_insn "negc"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(neg:SI (plus:SI (reg:SI 18)
-			 (match_operand:SI 1 "arith_reg_operand" "r"))))
-   (set (reg:SI 18)
-	(ne:SI (ior:SI (reg:SI 18) (match_dup 1))
-	       (const_int 0)))]
-  ""
-  "negc	%1,%0"
-  [(set_attr "type" "arith")])
-
-(define_expand "negdi2"
-  [(set (match_operand:DI 0 "arith_reg_operand" "")
-	(neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
-   (clobber (reg:SI 18))]
-  ""
-  "
-{
-  int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
-  int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
-
-  rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
-  rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
-
-  rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
-  rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
-
-  emit_insn (gen_clrt ());
-  emit_insn (gen_negc (low_dst, low_src));
-  emit_insn (gen_negc (high_dst, high_src));
-  DONE;
-}")
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
-  ""
-  "neg	%1,%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
-  ""
-  "not	%1,%0"
-  [(set_attr "type" "arith")])
-
-;; -------------------------------------------------------------------------
-;; Zero extension instructions
-;; -------------------------------------------------------------------------
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
-  ""
-  "extu.w	%1,%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
-  ""
-  "extu.b	%1,%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "arith_reg_operand" "=r")
-	(zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
-  ""
-  "extu.b	%1,%0"
-  [(set_attr "type" "arith")])
-
-;; -------------------------------------------------------------------------
-;; Sign extension instructions
-;; -------------------------------------------------------------------------
-
-;; ??? This should be a define expand.
-;; ??? Or perhaps it should be dropped?
-
-/* There is no point in defining extendsidi2; convert_move generates good
-   code for that.  */
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
-	(sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
-  ""
-  "@
-	exts.w	%1,%0
-   	mov.w	%1,%0"
-  [(set_attr "type" "arith,load")])
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
-	(sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
-  ""
-  "@
-	exts.b	%1,%0
-	mov.b	%1,%0"
-  [(set_attr "type" "arith,load")])
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
-	(sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
-  ""
-  "@
-	exts.b	%1,%0
-	mov.b	%1,%0"
-  [(set_attr "type" "arith,load")])
-
-;; -------------------------------------------------------------------------
-;; Move instructions
-;; -------------------------------------------------------------------------
-
-;; define push and pop so it is easy for sh.c
-
-(define_expand "push"
-  [(set (mem:SI (pre_dec:SI (reg:SI 15)))
-	(match_operand:SI 0 "register_operand" "r,l,x"))]
-  ""
-  "")
-
-(define_expand "pop"
-  [(set (match_operand:SI 0 "register_operand" "=r,l,x")
-	(mem:SI (post_inc:SI (reg:SI 15))))]
-  ""
-  "")
-
-(define_expand "push_e"
-  [(parallel [(set (mem:SF (pre_dec:SI (reg:SI 15)))
-		   (match_operand:SF 0 "" ""))
-	      (use (reg:PSI 48))
-	      (clobber (scratch:SI))])]
-  ""
-  "")
-
-(define_insn "push_fpul"
-  [(set (mem:SF (pre_dec:SI (reg:SI 15))) (reg:SF 22))]
-  "TARGET_SH3E"
-  "sts.l	fpul,@-r15"
-  [(set_attr "type" "store")
-   (set_attr "hit_stack" "yes")])
-
-;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
-;; so use that.
-(define_expand "push_4"
-  [(parallel [(set (mem:DF (pre_dec:SI (reg:SI 15))) (match_operand:DF 0 "" ""))
-	      (use (reg:PSI 48))
-	      (clobber (scratch:SI))])]
-  ""
-  "")
-
-(define_expand "pop_e"
-  [(parallel [(set (match_operand:SF 0 "" "")
-	      (mem:SF (post_inc:SI (reg:SI 15))))
-	      (use (reg:PSI 48))
-	      (clobber (scratch:SI))])]
-  ""
-  "")
-
-(define_insn "pop_fpul"
-  [(set (reg:SF 22) (mem:SF (post_inc:SI (reg:SI 15))))]
-  "TARGET_SH3E"
-  "lds.l	@r15+,fpul"
-  [(set_attr "type" "load")
-   (set_attr "hit_stack" "yes")])
-
-(define_expand "pop_4"
-  [(parallel [(set (match_operand:DF 0 "" "")
-		   (mem:DF (post_inc:SI (reg:SI 15))))
-	      (use (reg:PSI 48))
-	      (clobber (scratch:SI))])]
-  ""
-  "")
-
-;; These two patterns can happen as the result of optimization, when
-;; comparisons get simplified to a move of zero or 1 into the T reg.
-;; They don't disappear completely, because the T reg is a fixed hard reg.
-
-(define_insn "clrt"
-  [(set (reg:SI 18) (const_int 0))]
-  ""
-  "clrt")
-
-(define_insn "sett"
-  [(set (reg:SI 18) (const_int 1))]
-  ""
-  "sett")
-
-;; t/r is first, so that it will be preferred over r/r when reloading a move
-;; of a pseudo-reg into the T reg
-(define_insn "movsi_i"
-  [(set (match_operand:SI 0 "general_movdst_operand" "=t,r,r,r,r,r,m,<,<,xl,x,l,r")
-	(match_operand:SI 1 "general_movsrc_operand" "r,Q,rI,mr,xl,t,r,x,l,r,>,>,i"))]
-  "
-   ! TARGET_SH3E
-   && (register_operand (operands[0], SImode)
-       || register_operand (operands[1], SImode))"
-  "@
-	cmp/pl	%1
-	mov.l	%1,%0
-	mov	%1,%0
-	mov.l	%1,%0
-	sts	%1,%0
-	movt	%0
-	mov.l	%1,%0
-	sts.l	%1,%0
-	sts.l	%1,%0
-	lds	%1,%0
-	lds.l	%1,%0
-	lds.l	%1,%0
-	fake	%1,%0"
-  [(set_attr "type" "*,pcload_si,move,load_si,move,move,store,store,pstore,move,load,pload,pcload_si")
-   (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*")])
-
-;; t/r must come after r/r, lest reload will try to reload stuff like
-;; (subreg:SI (reg:SF 38 fr14) 0) into T (compiling stdlib/strtod.c -m3e -O2)
-;; ??? This allows moves from macl to fpul to be recognized, but these moves
-;; will require a reload.
-(define_insn "movsi_ie"
-  [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,m,<,<,xl,x,l,y,r,y,r,y")
-	(match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,xl,t,r,x,l,r,>,>,>,i,r,y,y"))]
-  "TARGET_SH3E
-   && (register_operand (operands[0], SImode)
-       || register_operand (operands[1], SImode))"
-  "@
-	mov.l	%1,%0
-	mov	%1,%0
-	cmp/pl	%1
-	mov.l	%1,%0
-	sts	%1,%0
-	movt	%0
-	mov.l	%1,%0
-	sts.l	%1,%0
-	sts.l	%1,%0
-	lds	%1,%0
-	lds.l	%1,%0
-	lds.l	%1,%0
-	lds.l	%1,%0
-	fake	%1,%0
-	lds	%1,%0
-	sts	%1,%0
-	! move optimized away"
-  [(set_attr "type" "pcload_si,move,*,load_si,move,move,store,store,pstore,move,load,pload,load,pcload_si,gp_fpul,gp_fpul,nil")
-   (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
-
-(define_insn "movsi_i_lowpart"
-  [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,r,m,r"))
-	(match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,xl,t,r,i"))]
-   "register_operand (operands[0], SImode)
-    || register_operand (operands[1], SImode)"
-  "@
-	mov.l	%1,%0
-	mov	%1,%0
-	mov.l	%1,%0
-	sts	%1,%0
-	movt	%0
-	mov.l	%1,%0
-	fake	%1,%0"
-  [(set_attr "type" "pcload,move,load,move,move,store,pcload")])
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_movdst_operand" "")
-	(match_operand:SI 1 "general_movsrc_operand" ""))]
-  ""
-  "{ if (prepare_move_operands (operands, SImode)) DONE; }")
-
-(define_expand "ic_invalidate_line"
-  [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
-				(match_dup 1)] 12)
-	      (clobber (scratch:SI))])]
-  "TARGET_HARD_SH4"
-  "
-{
-  operands[0] = force_reg (Pmode, operands[0]);
-  operands[1] = force_reg (Pmode, GEN_INT (0xf0000008));
-}")
-
-;; The address %0 is assumed to be 4-aligned at least.  Thus, by ORing
-;; 0xf0000008, we get the low-oder bits *1*00 (binary), ;; which fits
-;; the requirement *0*00 for associative address writes.  The alignment of
-;; %0 implies that its least significant bit is cleared,
-;; thus we clear the V bit of a matching entry if there is one.
-(define_insn "ic_invalidate_line_i"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r,r")
-		     (match_operand:SI 1 "register_operand" "r,r")] 12)
-   (clobber (match_scratch:SI 2 "=&r,1"))]
-  "TARGET_HARD_SH4"
-  "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%r1,%r2\;mov.l\\t%0,@%2"
-  [(set_attr "length" "8")])
-
-(define_insn "movqi_i"
-  [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
-	(match_operand:QI 1 "general_movsrc_operand"  "ri,m,r,t,l,r"))]
-  "arith_reg_operand (operands[0], QImode)
-   || arith_reg_operand (operands[1], QImode)"
-  "@
-	mov	%1,%0
-	mov.b	%1,%0
-	mov.b	%1,%0
-	movt	%0
-	sts	%1,%0
-	lds	%1,%0"
- [(set_attr "type" "move,load,store,move,move,move")])
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand"  ""))]
-  ""
-  "{ if (prepare_move_operands (operands, QImode)) DONE; }")
-
-(define_insn "movhi_i"
-  [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
-	(match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
-  "arith_reg_operand (operands[0], HImode)
-   || arith_reg_operand (operands[1], HImode)"
-  "@
-	mov.w	%1,%0
-	mov	%1,%0
-	mov.w	%1,%0
-	movt	%0
-	mov.w	%1,%0
-	sts	%1,%0
-	lds	%1,%0
-	fake	%1,%0"
-  [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_movdst_operand" "")
-	(match_operand:HI 1 "general_movsrc_operand"  ""))]
-  ""
-  "{ if (prepare_move_operands (operands, HImode)) DONE; }")
-
-;; ??? This should be a define expand.
-
-;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
-;; compiled with -m2 -ml -O3 -funroll-loops
-(define_insn ""
-  [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
-	(match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
-  "arith_reg_operand (operands[0], DImode)
-   || arith_reg_operand (operands[1], DImode)"
-  "* return output_movedouble (insn, operands, DImode);"
-  [(set_attr "length" "4")
-   (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
-
-;; If the output is a register and the input is memory or a register, we have
-;; to be careful and see which word needs to be loaded first.  
-
-(define_split
-  [(set (match_operand:DI 0 "general_movdst_operand" "")
-	(match_operand:DI 1 "general_movsrc_operand" ""))]
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 5))]
-  "
-{
-  int regno;
-
-  if ((GET_CODE (operands[0]) == MEM
-       && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-      || (GET_CODE (operands[1]) == MEM
-	  && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
-    FAIL;
-
-  if (GET_CODE (operands[0]) == REG)
-    regno = REGNO (operands[0]);
-  else if (GET_CODE (operands[0]) == SUBREG)
-    regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
-  else if (GET_CODE (operands[0]) == MEM)
-    regno = -1;
-
-  if (regno == -1
-      || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
-    {
-      operands[2] = operand_subword (operands[0], 0, 0, DImode);
-      operands[3] = operand_subword (operands[1], 0, 0, DImode);
-      operands[4] = operand_subword (operands[0], 1, 0, DImode);
-      operands[5] = operand_subword (operands[1], 1, 0, DImode);
-    }
-  else
-    {
-      operands[2] = operand_subword (operands[0], 1, 0, DImode);
-      operands[3] = operand_subword (operands[1], 1, 0, DImode);
-      operands[4] = operand_subword (operands[0], 0, 0, DImode);
-      operands[5] = operand_subword (operands[1], 0, 0, DImode);
-    }
-
-  if (operands[2] == 0 || operands[3] == 0
-      || operands[4] == 0 || operands[5] == 0)
-    FAIL;
-}")
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_movdst_operand" "")
-	(match_operand:DI 1 "general_movsrc_operand" ""))]
-  ""
-  "{ if ( prepare_move_operands (operands, DImode)) DONE; }")
-
-;; ??? This should be a define expand.
-
-(define_insn "movdf_k"
-  [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
-	(match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
-  "(! TARGET_SH4 || reload_completed
-    /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
-    || GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3
-    || GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3)
-   && (arith_reg_operand (operands[0], DFmode)
-       || arith_reg_operand (operands[1], DFmode))"
-  "* return output_movedouble (insn, operands, DFmode);"
-  [(set_attr "length" "4")
-   (set_attr "type" "move,pcload,load,store")])
-
-;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
-;; However, the d/F/c/z alternative cannot be split directly; it is converted
-;; with special code in machine_dependent_reorg into a load of the R0_REG and
-;; the d/m/c/X alternative, which is split later into single-precision
-;; instructions.  And when not optimizing, no splits are done before fixing
-;; up pcloads, so we need usable length information for that.
-(define_insn "movdf_i4"
-  [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
-	(match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
-   (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
-   (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
-  "TARGET_SH4
-   && (arith_reg_operand (operands[0], DFmode)
-       || arith_reg_operand (operands[1], DFmode))"
-  "@
-	fmov	%1,%0
-	#
-	#
-	fmov.d	%1,%0
-	fmov.d	%1,%0
-	#
-	#
-	#
-	#
-	#"
-  [(set_attr_alternative "length"
-     [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
-      (const_int 4)
-      (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
-      (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
-      (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
-      (const_int 4)
-      (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
-      (const_int 8) (const_int 8)])
-   (set_attr "type" "fmove,move,pcload,load,store,pcload,load,store,load,load")])
-
-;; Moving DFmode between fp/general registers through memory
-;; (the top of the stack) is faster than moving through fpul even for
-;; little endian.  Because the type of an instruction is important for its
-;; scheduling,  it is beneficial to split these operations, rather than
-;; emitting them in one single chunk, even if this will expose a stack
-;; use that will prevent scheduling of other stack accesses beyond this
-;; instruction.
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-	(match_operand:DF 1 "register_operand" ""))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (match_scratch:SI 3 "=X"))]
-  "TARGET_SH4 && reload_completed
-   && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
-  [(const_int 0)]
-  "
-{
-  rtx insn, tos;
-
-  tos = gen_rtx (MEM, DFmode, gen_rtx (PRE_DEC, Pmode, stack_pointer_rtx));
-  insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
-  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
-  tos = gen_rtx (MEM, DFmode, gen_rtx (POST_INC, Pmode, stack_pointer_rtx));
-  insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
-  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
-  DONE;
-}")
-
-;; local-alloc sometimes allocates scratch registers even when not required,
-;; so we must be prepared to handle these.
-
-;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
-(define_split
-  [(set (match_operand:DF 0 "general_movdst_operand" "")
-	(match_operand:DF 1 "general_movsrc_operand"  ""))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (match_scratch:SI 3 "X"))]
-  "TARGET_SH4
-   && reload_completed
-   && true_regnum (operands[0]) < 16
-   && true_regnum (operands[1]) < 16"
-  [(set (match_dup 0) (match_dup 1))]
-  "
-{
-  /* If this was a reg <-> mem operation with base + index reg addressing,
-     we have to handle this in a special way.  */
-  rtx mem = operands[0];
-  int store_p = 1;
-  if (! memory_operand (mem, DFmode))
-    {
-      mem = operands[1];
-      store_p = 0;
-    }
-  if (GET_CODE (mem) == SUBREG && SUBREG_WORD (mem) == 0)
-    mem = SUBREG_REG (mem);
-  if (GET_CODE (mem) == MEM)
-    {
-      rtx addr = XEXP (mem, 0);
-      if (GET_CODE (addr) == PLUS
-	  && GET_CODE (XEXP (addr, 0)) == REG
-	  && GET_CODE (XEXP (addr, 1)) == REG)
-	{
-	  int offset;
-	  rtx reg0 = gen_rtx (REG, Pmode, 0);
-	  rtx regop = operands[store_p], word0 ,word1;
-
-	  if (GET_CODE (regop) == SUBREG)
-	    regop = alter_subreg (regop);
-	  if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
-	    offset = 2;
-	  else
-	    offset = 4;
-	  mem = copy_rtx (mem);
-	  PUT_MODE (mem, SImode);
-	  word0 = gen_rtx(SUBREG, SImode, regop, 0);
-	  emit_insn (store_p
-		     ? gen_movsi_ie (mem, word0) : gen_movsi_ie (word0, mem));
-	  emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
-	  mem = copy_rtx (mem);
-	  word1 = gen_rtx(SUBREG, SImode, regop, 1);
-	  emit_insn (store_p
-		     ? gen_movsi_ie (mem, word1) : gen_movsi_ie (word1, mem));
-	  emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
-	  DONE;
-	}
-    }
-}")
-
-;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-	(match_operand:DF 1 "memory_operand"  ""))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (reg:SI 0))]
-  "TARGET_SH4 && reload_completed"
-  [(parallel [(set (match_dup 0) (match_dup 1))
-	      (use (match_dup 2))
-	      (clobber (scratch:SI))])]
-  "")
-
-(define_expand "reload_indf"
-  [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
-		   (match_operand:DF 1 "immediate_operand" "FQ"))
-	      (use (reg:PSI 48))
-	      (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
-  ""
-  "")
-
-(define_expand "reload_outdf"
-  [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
-		   (match_operand:DF 1 "register_operand" "af,r"))
-	      (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
-  ""
-  "")
-
-;; Simplify no-op moves.
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "")
-	(match_operand:SF 1 "register_operand" ""))
-   (use (match_operand:PSI 2 "fpscr_operand" ""))
-   (clobber (match_scratch:SI 3 "X"))]
-  "TARGET_SH3E && reload_completed
-   && true_regnum (operands[0]) == true_regnum (operands[1])"
-  [(set (match_dup 0) (match_dup 0))]
-  "")
-
-;; fmovd substitute post-reload splits
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-	(match_operand:DF 1 "register_operand" ""))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (match_scratch:SI 3 "X"))]
-  "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
-   && true_regnum (operands[0]) >= FIRST_FP_REG
-   && true_regnum (operands[1]) >= FIRST_FP_REG"
-  [(const_int 0)]
-  "
-{
-  int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
-  emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst),
-			   gen_rtx (REG, SFmode, src), operands[2]));
-  emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst + 1),
-			   gen_rtx (REG, SFmode, src + 1), operands[2]));
-  DONE;
-}")
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-	(mem:DF (match_operand:SI 1 "register_operand" "")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (match_scratch:SI 3 "X"))]
-  "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
-   && true_regnum (operands[0]) >= FIRST_FP_REG
-   && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
-  [(const_int 0)]
-  "
-{
-  int regno = true_regnum (operands[0]);
-  rtx insn;
-  rtx mem2 = gen_rtx (MEM, SFmode, gen_rtx (POST_INC, Pmode, operands[1]));
-
-  insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
-					   regno + !! TARGET_LITTLE_ENDIAN),
-				  mem2, operands[2]));
-  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[1], NULL_RTX);
-  insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
-					   regno + ! TARGET_LITTLE_ENDIAN),
-				  gen_rtx (MEM, SFmode, operands[1]),
-				  operands[2]));
-  DONE;
-}")
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-	(match_operand:DF 1 "memory_operand" ""))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (match_scratch:SI 3 "X"))]
-  "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
-   && true_regnum (operands[0]) >= FIRST_FP_REG"
-  [(const_int 0)]
-  "
-{
-  int regno = true_regnum (operands[0]);
-  rtx addr, insn, adjust = NULL_RTX;
-  rtx mem2 = copy_rtx (operands[1]);
-  rtx reg0 = gen_rtx_REG (SFmode, regno + !! TARGET_LITTLE_ENDIAN);
-  rtx reg1 = gen_rtx_REG (SFmode, regno + ! TARGET_LITTLE_ENDIAN);
-
-  PUT_MODE (mem2, SFmode);
-  operands[1] = copy_rtx (mem2);
-  addr = XEXP (mem2, 0);
-  if (GET_CODE (addr) != POST_INC)
-    {
-      /* If we have to modify the stack pointer, the value that we have
-	 read with post-increment might be modified by an interrupt,
-	 so write it back.  */
-      if (REGNO (addr) == STACK_POINTER_REGNUM)
-	adjust = gen_push_e (reg0);
-      else
-	adjust = gen_addsi3 (addr, addr, GEN_INT (-4));
-      XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
-    }
-  addr = XEXP (addr, 0);
-  insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
-  REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
-  insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
-  if (adjust)
-    emit_insn (adjust);
-  else
-    REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
-  DONE;
-}")
-
-(define_split
-  [(set (match_operand:DF 0 "memory_operand" "")
-	(match_operand:DF 1 "register_operand" ""))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (match_scratch:SI 3 "X"))]
-  "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
-   && true_regnum (operands[1]) >= FIRST_FP_REG"
-  [(const_int 0)]
-  "
-{
-  int regno = true_regnum (operands[1]);
-  rtx insn, addr, adjust = NULL_RTX;
-
-  operands[0] = copy_rtx (operands[0]);
-  PUT_MODE (operands[0], SFmode);
-  insn = emit_insn (gen_movsf_ie (operands[0],
-				  gen_rtx (REG, SFmode,
-					   regno + ! TARGET_LITTLE_ENDIAN),
-				  operands[2]));
-  operands[0] = copy_rtx (operands[0]);
-  addr = XEXP (operands[0], 0);
-  if (GET_CODE (addr) != PRE_DEC)
-    {
-      adjust = gen_addsi3 (addr, addr, GEN_INT (4));
-      emit_insn_before (adjust, insn);
-      XEXP (operands[0], 0) = addr = gen_rtx (PRE_DEC, SImode, addr);
-    }
-  addr = XEXP (addr, 0);
-  if (! adjust)
-    REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
-  insn = emit_insn (gen_movsf_ie (operands[0],
-				  gen_rtx (REG, SFmode,
-					   regno + !! TARGET_LITTLE_ENDIAN),
-				  operands[2]));
-  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
-  DONE;
-}")
-
-;; The '&' for operand 2 is not really true, but push_secondary_reload
-;; insists on it.
-;; Operand 1 must accept FPUL_REGS in case fpul is reloaded to memory,
-;; to avoid a bogus tertiary reload.
-;; We need a tertiary reload when a floating point register is reloaded
-;; to memory, so the predicate for operand 0 must accept this, while the 
-;; constraint of operand 1 must reject the secondary reload register.
-;; Thus, the secondary reload register for this case has to be GENERAL_REGS,
-;; too.
-;; By having the predicate for operand 0 reject any register, we make
-;; sure that the ordinary moves that just need an intermediate register
-;; won't get a bogus tertiary reload.
-;; We use tertiary_reload_operand instead of memory_operand here because
-;; memory_operand rejects operands that are not directly addressible, e.g.:
-;; (mem:SF (plus:SI (reg:SI 14 r14)
-;;         (const_int 132)))
-
-(define_expand "reload_outsf"
-  [(parallel [(set (match_operand:SF 2 "register_operand" "=&r")
-		   (match_operand:SF 1 "register_operand" "y"))
-	      (clobber (scratch:SI))])
-   (parallel [(set (match_operand:SF 0 "tertiary_reload_operand" "=m")
-		   (match_dup 2))
-	      (clobber (scratch:SI))])]
-  ""
-  "")
-
-;; If the output is a register and the input is memory or a register, we have
-;; to be careful and see which word needs to be loaded first.  
-
-(define_split
-  [(set (match_operand:DF 0 "general_movdst_operand" "")
-	(match_operand:DF 1 "general_movsrc_operand" ""))]
-  "reload_completed"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 5))]
-  "
-{
-  int regno;
-
-  if ((GET_CODE (operands[0]) == MEM
-       && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
-      || (GET_CODE (operands[1]) == MEM
-	  && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
-    FAIL;
-
-  if (GET_CODE (operands[0]) == REG)
-    regno = REGNO (operands[0]);
-  else if (GET_CODE (operands[0]) == SUBREG)
-    regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
-  else if (GET_CODE (operands[0]) == MEM)
-    regno = -1;
-
-  if (regno == -1
-      || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
-    {
-      operands[2] = operand_subword (operands[0], 0, 0, DFmode);
-      operands[3] = operand_subword (operands[1], 0, 0, DFmode);
-      operands[4] = operand_subword (operands[0], 1, 0, DFmode);
-      operands[5] = operand_subword (operands[1], 1, 0, DFmode);
-    }
-  else
-    {
-      operands[2] = operand_subword (operands[0], 1, 0, DFmode);
-      operands[3] = operand_subword (operands[1], 1, 0, DFmode);
-      operands[4] = operand_subword (operands[0], 0, 0, DFmode);
-      operands[5] = operand_subword (operands[1], 0, 0, DFmode);
-    }
-
-  if (operands[2] == 0 || operands[3] == 0
-      || operands[4] == 0 || operands[5] == 0)
-    FAIL;
-}")
-
-;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
-;; used only once, let combine add in the index again.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(match_operand:SI 1 "" ""))
-   (clobber (match_operand 2 "register_operand" ""))]
-  "! reload_in_progress && ! reload_completed"
-  [(use (reg:SI 0))]
-  "
-{
-  rtx addr, reg, const_int;
-
-  if (GET_CODE (operands[1]) != MEM)
-    FAIL;
-  addr = XEXP (operands[1], 0);
-  if (GET_CODE (addr) != PLUS)
-    FAIL;
-  reg = XEXP (addr, 0);
-  const_int = XEXP (addr, 1);
-  if (GET_CODE (reg) != REG || GET_CODE (const_int) != CONST_INT)
-    FAIL;
-  emit_move_insn (operands[2], const_int);
-  emit_move_insn (operands[0],
-		  change_address (operands[1], VOIDmode,
-				  gen_rtx (PLUS, SImode, reg, operands[2])));
-  DONE;
-}")
-
-(define_split
-  [(set (match_operand:SI 1 "" "")
-	(match_operand:SI 0 "register_operand" ""))
-   (clobber (match_operand 2 "register_operand" ""))]
-  "! reload_in_progress && ! reload_completed"
-  [(use (reg:SI 0))]
-  "
-{
-  rtx addr, reg, const_int;
-
-  if (GET_CODE (operands[1]) != MEM)
-    FAIL;
-  addr = XEXP (operands[1], 0);
-  if (GET_CODE (addr) != PLUS)
-    FAIL;
-  reg = XEXP (addr, 0);
-  const_int = XEXP (addr, 1);
-  if (GET_CODE (reg) != REG || GET_CODE (const_int) != CONST_INT)
-    FAIL;
-  emit_move_insn (operands[2], const_int);
-  emit_move_insn (change_address (operands[1], VOIDmode,
-				  gen_rtx (PLUS, SImode, reg, operands[2])),
-		  operands[0]);
-  DONE;
-}")
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_movdst_operand" "")
-	(match_operand:DF 1 "general_movsrc_operand" ""))]
-  ""
-  "
-{
-  if (prepare_move_operands (operands, DFmode)) DONE;
-  if (TARGET_SH4)
-    {
-      if (no_new_pseudos)
-	{
-	  /* ??? FIXME: This is only a stopgap fix.  There is no guarantee
-	     that fpscr is in the right state. */
-	  emit_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
-	  DONE;
-	}
-      emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
-      /* We need something to tag possible REG_LIBCALL notes on to.  */
-      if (TARGET_FPU_SINGLE && rtx_equal_function_value_matters
-	  && GET_CODE (operands[0]) == REG)
-	emit_insn (gen_mov_nop (operands[0]));
-      DONE;
-    }
-}")
-
-
-(define_insn "movsf_i"
-  [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
-	(match_operand:SF 1 "general_movsrc_operand"  "r,I,FQ,mr,r,r,l"))]
-  "
-   (! TARGET_SH3E
-    /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
-    || GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3
-    || GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3)
-   && (arith_reg_operand (operands[0], SFmode)
-       || arith_reg_operand (operands[1], SFmode))"
-  "@
-	mov	%1,%0
-	mov	%1,%0
-	mov.l	%1,%0
-	mov.l	%1,%0
-	mov.l	%1,%0
-	lds	%1,%0
-	sts	%1,%0"
-  [(set_attr "type" "move,move,pcload,load,store,move,move")])
-
-;; We may not split the ry/yr/XX alternatives to movsi_ie, since
-;; update_flow_info would not know where to put REG_EQUAL notes
-;; when the destination changes mode.
-(define_insn "movsf_ie"
-  [(set (match_operand:SF 0 "general_movdst_operand"
-	 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,y")
-	(match_operand:SF 1 "general_movsrc_operand"
-	  "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y"))
-   (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
-   (clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X"))]
-
-  "TARGET_SH3E
-   && (arith_reg_operand (operands[0], SFmode)
-       || arith_reg_operand (operands[1], SFmode))"
-  "@
-	fmov	%1,%0
-	mov	%1,%0
-	fldi0	%0
-	fldi1	%0
-	#
-	fmov.s	%1,%0
-	fmov.s	%1,%0
-	mov.l	%1,%0
-	mov.l	%1,%0
-	mov.l	%1,%0
-	fsts	fpul,%0
-	flds	%1,fpul
-	lds.l	%1,%0
-	#
-	sts	%1,%0
-	lds	%1,%0
-	! move optimized away"
-  [(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,nil")
-   (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,4,2,2,0")])
-
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "")
-	(match_operand:SF 1 "register_operand" ""))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (reg:SI 22))]
-  ""
-  [(parallel [(set (reg:SF 22) (match_dup 1))
-	      (use (match_dup 2))
-	      (clobber (scratch:SI))])
-   (parallel [(set (match_dup 0) (reg:SF 22))
-	      (use (match_dup 2))
-	      (clobber (scratch:SI))])]
-  "")
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_movdst_operand" "")
-        (match_operand:SF 1 "general_movsrc_operand" ""))]
-  ""
-  "
-{
-  if (prepare_move_operands (operands, SFmode))
-    DONE;
-  if (TARGET_SH3E)
-    {
-      if (no_new_pseudos)
-	{
-	  /* ??? FIXME: This is only a stopgap fix.  There is no guarantee
-	     that fpscr is in the right state. */
-	  emit_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
-	  DONE;
-	}
-      emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
-      /* We need something to tag possible REG_LIBCALL notes on to.  */
-      if (! TARGET_FPU_SINGLE && rtx_equal_function_value_matters
-	  && GET_CODE (operands[0]) == REG)
-	emit_insn (gen_mov_nop (operands[0]));
-      DONE;
-    }
-}")
-
-(define_insn "mov_nop"
-  [(set (match_operand 0 "register_operand" "") (match_dup 0))]
-  "TARGET_SH3E"
-  ""
-  [(set_attr "length" "0")
-   (set_attr "type" "nil")])
-
-(define_expand "reload_insf"
-  [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
-		   (match_operand:SF 1 "immediate_operand" "FQ"))
-	      (use (reg:PSI 48))
-	      (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
-  ""
-  "")
-
-(define_expand "reload_insi"
-  [(parallel [(set (match_operand:SF 0 "register_operand" "=y")
-		   (match_operand:SF 1 "immediate_operand" "FQ"))
-	      (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
-  ""
-  "")
-
-(define_insn "*movsi_y"
-  [(set (match_operand:SI 0 "register_operand" "=y,y")
-	(match_operand:SI 1 "immediate_operand" "Qi,I"))
-   (clobber (match_scratch:SI 3 "=&z,r"))]
-  "TARGET_SH3E
-   && (reload_in_progress || reload_completed)"
-  "#"
-  [(set_attr "length" "4")
-   (set_attr "type" "pcload,move")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "y")
-	(match_operand:SI 1 "immediate_operand" "I"))
-   (clobber (match_operand:SI 2 "register_operand" "r"))]
-  ""
-  [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (match_dup 2))]
-  "")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "y")
-	(match_operand:SI 1 "memory_operand" ">"))
-   (clobber (reg:SI 0))]
-  ""
-  [(set (match_dup 0) (match_dup 1))]
-  "")
-
-;; ------------------------------------------------------------------------
-;; Define the real conditional branch instructions.
-;; ------------------------------------------------------------------------
-
-(define_insn "branch_true"
-  [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 0))
-			   (label_ref (match_operand 0 "" ""))
-			   (pc)))]
-  ""
-  "* return output_branch (1, insn, operands);"
-  [(set_attr "type" "cbranch")])
-
-(define_insn "branch_false"
-  [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 0))
-			   (label_ref (match_operand 0 "" ""))
-			   (pc)))]
-  ""
-  "* return output_branch (0, insn, operands);"
-  [(set_attr "type" "cbranch")])
-
-;; Patterns to prevent reorg from re-combining a condbranch with a branch
-;; which destination is too far away.
-;; The const_int_operand is distinct for each branch target; it avoids
-;; unwanted matches with redundant_insn.
-(define_insn "block_branch_redirect"
-  [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] 4))]
-  ""
-  ""
-  [(set_attr "length" "0")])
-
-;; This one has the additional purpose to record a possible scratch register
-;; for the following branch.
-(define_insn "indirect_jump_scratch"
-  [(set (match_operand 0 "register_operand" "r")
-	(unspec [(match_operand 1 "const_int_operand" "")] 4))]
-  ""
-  ""
-  [(set_attr "length" "0")])
-
-;; Conditional branch insns
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (ne (reg:SI 18) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "from_compare (operands, EQ);")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (eq (reg:SI 18) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "from_compare (operands, EQ);")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (ne (reg:SI 18) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "from_compare (operands, GT);")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (eq (reg:SI 18) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
-    {
-      rtx tmp = sh_compare_op0;
-      sh_compare_op0 = sh_compare_op1;
-      sh_compare_op1 = tmp;
-      emit_insn (gen_bgt (operands[0]));
-      DONE;
-    }
-  from_compare (operands, GE);
-}")
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (eq (reg:SI 18) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (TARGET_SH3E
-      && TARGET_IEEE
-      && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
-    {
-      rtx tmp = sh_compare_op0;
-      sh_compare_op0 = sh_compare_op1;
-      sh_compare_op1 = tmp;
-      emit_insn (gen_bge (operands[0]));
-      DONE;
-    }
-  from_compare (operands, GT);
-}")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ne (reg:SI 18) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (TARGET_SH3E
-      && ! TARGET_IEEE
-      && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
-    {
-      rtx tmp = sh_compare_op0;
-      sh_compare_op0 = sh_compare_op1;
-      sh_compare_op1 = tmp;
-      emit_insn (gen_ble (operands[0]));
-      DONE;
-    }
-  from_compare (operands, GE);
-}")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (ne (reg:SI 18) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "from_compare (operands, GTU); ")
-
-(define_expand "bltu"
-  [(set (pc)
-		  (if_then_else (eq (reg:SI 18) (const_int 0))
-				(label_ref (match_operand 0 "" ""))
-				(pc)))]
-  ""
-  "from_compare (operands, GEU);")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (ne (reg:SI 18) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "from_compare (operands, GEU);")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (eq (reg:SI 18) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "from_compare (operands, GTU);")
-
-;; ------------------------------------------------------------------------
-;; Jump and linkage insns
-;; ------------------------------------------------------------------------
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "*
-{
-  /* The length is 16 if the delay slot is unfilled.  */
-  if (get_attr_length(insn) > 4)
-    return output_far_jump(insn, operands[0]);
-  else
-    return   \"bra	%l0%#\";
-}"
-  [(set_attr "type" "jump")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_insn "calli"
-  [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
-	 (match_operand 1 "" ""))
-   (use (reg:SI 48))
-   (clobber (reg:SI 17))]
-  ""
-  "jsr	@%0%#"
-  [(set_attr "type" "call")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_insn "call_valuei"
-  [(set (match_operand 0 "" "=rf")
-	(call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
-	      (match_operand 2 "" "")))
-   (use (reg:SI 48))
-   (clobber (reg:SI 17))]
-  ""
-  "jsr	@%1%#"
-  [(set_attr "type" "call")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_expand "call"
-  [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
-			    (match_operand 1 "" ""))
-	      (use (reg:SI 48))
-	      (clobber (reg:SI 17))])]
-  ""
-  "operands[0] = force_reg (SImode, XEXP (operands[0], 0));")
-
-(define_expand "call_value"
-  [(parallel [(set (match_operand 0 "arith_reg_operand" "")
-		   (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
-				 (match_operand 2 "" "")))
-	      (use (reg:SI 48))
-	      (clobber (reg:SI 17))])]
-  ""
-  "operands[1] = force_reg (SImode, XEXP (operands[1], 0));")
-
-(define_insn "indirect_jump"
-  [(set (pc)
-	(match_operand:SI 0 "arith_reg_operand" "r"))]
-  ""
-  "jmp	@%0%#"
-  [(set_attr "needs_delay_slot" "yes")
-   (set_attr "type" "jump_ind")])
-
-;; The use of operand 1 / 2 helps us distinguish case table jumps
-;; which can be present in structured code from indirect jumps which can not
-;; be present in structured code.  This allows -fprofile-arcs to work.
-
-;; For SH1 processors.
-(define_insn "casesi_jump_1"
-  [(set (pc)
-	(match_operand:SI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmp  @%0%#"
-  [(set_attr "needs_delay_slot" "yes")
-   (set_attr "type" "jump_ind")])
-
-;; For all later processors.
-(define_insn "casesi_jump_2"
-  [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
-		      (label_ref (match_operand 1 "" ""))))
-   (use (label_ref (match_operand 2 "" "")))]
-  "! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn"
-  "braf	%0%#"
-  [(set_attr "needs_delay_slot" "yes")
-   (set_attr "type" "jump_ind")])
-
-;; Call subroutine returning any type.
-;; ??? This probably doesn't work.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  "TARGET_SH3E"
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; ------------------------------------------------------------------------
-;; Misc insns
-;; ------------------------------------------------------------------------
-
-(define_insn "dect"
-  [(set (reg:SI 18)
-	(eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
-   (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
-  "TARGET_SH2"
-  "dt	%0"
-  [(set_attr "type" "arith")])
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
-
-;; Load address of a label. This is only generated by the casesi expand,
-;; and by machine_dependent_reorg (fixing up fp moves).
-;; This must use unspec, because this only works for labels that are
-;; within range,
-
-(define_insn "mova"
-  [(set (reg:SI 0)
-	(unspec [(label_ref (match_operand 0 "" ""))] 1))]
-  ""
-  "mova	%O0,r0"
-  [(set_attr "in_delay_slot" "no")
-   (set_attr "type" "arith")])
-
-;; case instruction for switch statements.
-
-;; Operand 0 is index
-;; operand 1 is the minimum bound
-;; operand 2 is the maximum bound - minimum bound + 1
-;; operand 3 is CODE_LABEL for the table;
-;; operand 4 is the CODE_LABEL to go to if index out of range.
-
-(define_expand "casesi"
-  [(match_operand:SI 0 "arith_reg_operand" "")
-   (match_operand:SI 1 "arith_reg_operand" "")
-   (match_operand:SI 2 "arith_reg_operand" "")
-   (match_operand 3 "" "") (match_operand 4 "" "")]
-  ""
-  "
-{
-  rtx reg = gen_reg_rtx (SImode);
-  rtx reg2 = gen_reg_rtx (SImode);
-  operands[1] = copy_to_mode_reg (SImode, operands[1]);
-  operands[2] = copy_to_mode_reg (SImode, operands[2]);
-  /* If optimizing, casesi_worker depends on the mode of the instruction
-     before label it 'uses' - operands[3].  */
-  emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
-			   reg));
-  emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
-  if (TARGET_SH2)
-    emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
-  else
-    emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
-  /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
-     operands[3], but to lab.  We will fix this up in
-     machine_dependent_reorg.  */
-  emit_barrier ();
-  DONE;
-}")
-
-(define_expand "casesi_0"
-  [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
-   (set (match_dup 4) (minus:SI (match_dup 4)
-				(match_operand:SI 1 "arith_operand" "")))
-   (set (reg:SI 18)
-	(gtu:SI (match_dup 4)
-		(match_operand:SI 2 "arith_reg_operand" "")))
-   (set (pc)
-	(if_then_else (ne (reg:SI 18)
-			  (const_int 0))
-		      (label_ref (match_operand 3 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-;; ??? reload might clobber r0 if we use it explicitly in the RTL before
-;; reload; using a R0_REGS pseudo reg is likely to give poor code.
-;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
-
-(define_insn "casesi_worker_0"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(unspec [(match_operand 1 "register_operand" "0,r")
-		 (label_ref (match_operand 2 "" ""))] 2))
-   (clobber (match_scratch:SI 3 "=X,1"))
-   (clobber (match_scratch:SI 4 "=&z,z"))]
-  ""
-  "#")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(unspec [(match_operand 1 "register_operand" "")
-		 (label_ref (match_operand 2 "" ""))] 2))
-   (clobber (match_scratch:SI 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "! TARGET_SH2 && reload_completed"
-  [(set (reg:SI 0) (unspec [(label_ref (match_dup 2))] 1))
-   (parallel [(set (match_dup 0)
-	      (unspec [(reg:SI 0) (match_dup 1) (label_ref (match_dup 2))] 2))
-	      (clobber (match_dup 3))])
-   (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI 0)))]
-  "LABEL_NUSES (operands[2])++;")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(unspec [(match_operand 1 "register_operand" "")
-		 (label_ref (match_operand 2 "" ""))] 2))
-   (clobber (match_scratch:SI 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_SH2 && reload_completed"
-  [(set (reg:SI 0) (unspec [(label_ref (match_dup 2))] 1))
-   (parallel [(set (match_dup 0)
-	      (unspec [(reg:SI 0) (match_dup 1) (label_ref (match_dup 2))] 2))
-	      (clobber (match_dup 3))])]
-  "LABEL_NUSES (operands[2])++;")
-
-(define_insn "*casesi_worker"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(unspec [(reg:SI 0) (match_operand 1 "register_operand" "0,r")
-		 (label_ref (match_operand 2 "" ""))] 2))
-   (clobber (match_scratch:SI 3 "=X,1"))]
-  ""
-  "*
-{
-  rtx diff_vec = PATTERN (next_real_insn (operands[2]));
-
-  if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
-    abort ();
-
-  switch (GET_MODE (diff_vec))
-    {
-    case SImode:
-      return \"shll2	%1\;mov.l	@(r0,%1),%0\";
-    case HImode:
-      return \"add	%1,%1\;mov.w	@(r0,%1),%0\";
-    case QImode:
-      if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
-	return \"mov.b	@(r0,%1),%0\;extu.b	%0,%0\";
-      return \"mov.b	@(r0,%1),%0\";
-    default:
-      abort ();
-    }
-}"
-  [(set_attr "length" "4")])
-
-;; ??? This is not the proper place to invoke another compiler pass;
-;; Alas, there is no proper place to put it.
-;; ??? This is also an odd place for the call to emit_fpscr_use.  It
-;; would be all right if it were for an define_expand for return, but
-;; that doesn't mix with emitting a prologue.
-(define_insn "return"
-  [(return)]
-  "emit_fpscr_use (),
-   remove_dead_before_cse (),
-   reload_completed"
-  "%@	%#"
-  [(set_attr "type" "return")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_expand "prologue"
-  [(const_int 0)]
-  ""
-  "sh_expand_prologue (); DONE;")
-
-(define_expand "epilogue"
-  [(return)]
-  ""
-  "sh_expand_epilogue ();")
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  ""
-  [(set_attr "length" "0")])
-
-;; ------------------------------------------------------------------------
-;; Scc instructions
-;; ------------------------------------------------------------------------
-
-(define_insn "movt"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(eq:SI (reg:SI 18) (const_int 1)))]
-  ""
-  "movt	%0"
-  [(set_attr "type" "arith")])
-
-(define_expand "seq"
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = prepare_scc_operands (EQ);")
-
-(define_expand "slt"
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = prepare_scc_operands (LT);")
-
-(define_expand "sle"
-  [(match_operand:SI 0 "arith_reg_operand" "")]
-  ""
-  "
-{
-  rtx tmp = sh_compare_op0;
-  sh_compare_op0 = sh_compare_op1;
-  sh_compare_op1 = tmp;
-  emit_insn (gen_sge (operands[0]));
-  DONE;
-}")
-
-(define_expand "sgt"
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = prepare_scc_operands (GT);")
-
-(define_expand "sge"
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(match_dup 1))]
-  ""
-  "
-{
-  if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
-    {
-      if (TARGET_IEEE)
-	{
-	  rtx t_reg = gen_rtx (REG, SImode, T_REG);
-	  rtx lab = gen_label_rtx ();
-	  prepare_scc_operands (EQ);
-	  emit_jump_insn (gen_branch_true (lab));
-	  prepare_scc_operands (GT);
-	  emit_label (lab);
-	  emit_insn (gen_movt (operands[0]));
-	}
-      else
-	emit_insn (gen_movnegt (operands[0], prepare_scc_operands (LT)));
-      DONE;
-    }
-  operands[1] = prepare_scc_operands (GE);
-}")
-
-(define_expand "sgtu"
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = prepare_scc_operands (GTU);")
-
-(define_expand "sltu"
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = prepare_scc_operands (LTU);")
-
-(define_expand "sleu"
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = prepare_scc_operands (LEU);")
-
-(define_expand "sgeu"
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(match_dup 1))]
-  ""
-  "operands[1] = prepare_scc_operands (GEU);")
-
-;; sne moves the complement of the T reg to DEST like this:
-;;      cmp/eq ...
-;;      mov    #-1,temp
-;;      negc   temp,dest
-;;   This is better than xoring compare result with 1 because it does
-;;   not require r0 and further, the -1 may be CSE-ed or lifted out of a
-;;   loop.
-
-(define_expand "sne"
-  [(set (match_dup 2) (const_int -1))
-   (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
-		   (neg:SI (plus:SI (match_dup 1)
-				    (match_dup 2))))
-	      (set (reg:SI 18)
-		   (ne:SI (ior:SI (match_dup 1) (match_dup 2))
-			  (const_int 0)))])]  
-  ""
-  "
-{
-   operands[1] = prepare_scc_operands (EQ);
-   operands[2] = gen_reg_rtx (SImode);
-}")
-
-;; Use the same trick for FP sle / sge
-(define_expand "movnegt"
-  [(set (match_dup 2) (const_int -1))
-   (parallel [(set (match_operand 0 "" "")
-		   (neg:SI (plus:SI (match_dup 1)
-				    (match_dup 2))))
-	      (set (reg:SI 18)
-		   (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
-			  (const_int 0)))])]  
-  ""
-  "operands[2] = gen_reg_rtx (SImode);")
-
-;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1.
-;; This prevents a regression that occurred when we switched from xor to
-;; mov/neg for sne.
-
-(define_split
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(plus:SI (reg:SI 18)
-		 (const_int -1)))]
-  ""
-  [(set (match_dup 0) (eq:SI (reg:SI 18) (const_int 1)))
-   (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
-  "")
-
-;; -------------------------------------------------------------------------
-;; Instructions to cope with inline literal tables
-;; -------------------------------------------------------------------------
-
-; 2 byte integer in line
-
-(define_insn "consttable_2"
- [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 2)]
- ""
- "*
-{
-  assemble_integer (operands[0], 2, 1);
-  return \"\";
-}"
- [(set_attr "length" "2")
- (set_attr "in_delay_slot" "no")])
-
-; 4 byte integer in line
-
-(define_insn "consttable_4"
- [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 4)]
- ""
- "*
-{
-  assemble_integer (operands[0], 4, 1);
-  return \"\";
-}"
- [(set_attr "length" "4")
-  (set_attr "in_delay_slot" "no")])
-
-; 8 byte integer in line
-
-(define_insn "consttable_8"
- [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 6)]
- ""
- "*
-{
-  assemble_integer (operands[0], 8, 1);
-  return \"\";
-}"
- [(set_attr "length" "8")
-  (set_attr "in_delay_slot" "no")])
-
-; 4 byte floating point
-
-(define_insn "consttable_sf"
- [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")] 4)]
- ""
- "*
-{
-  union real_extract u;
-  bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
-  assemble_real (u.d, SFmode);
-  return \"\";
-}"
- [(set_attr "length" "4")
-  (set_attr "in_delay_slot" "no")])
-
-; 8 byte floating point
-
-(define_insn "consttable_df"
- [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")] 6)]
- ""
- "*
-{
-  union real_extract u;
-  bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
-  assemble_real (u.d, DFmode);
-  return \"\";
-}"
- [(set_attr "length" "8")
-  (set_attr "in_delay_slot" "no")])
-
-;; Alignment is needed for some constant tables; it may also be added for
-;; Instructions at the start of loops, or after unconditional branches.
-;; ??? We would get more accurate lengths if we did instruction
-;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
-;; here is too conservative.
-
-; align to a two byte boundary
-
-(define_expand "align_2"
- [(unspec_volatile [(const_int 1)] 1)]
- ""
- "")
-
-; align to a four byte boundary
-;; align_4 and align_log are instructions for the starts of loops, or
-;; after unconditional branches, which may take up extra room.
-
-(define_expand "align_4"
- [(unspec_volatile [(const_int 2)] 1)]
- ""
- "")
-
-; align to a cache line boundary
-
-(define_insn "align_log"
- [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 1)]
- ""
- ""
- [(set_attr "length" "0")
-  (set_attr "in_delay_slot" "no")])
-
-; emitted at the end of the literal table, used to emit the
-; 32bit branch labels if needed.
-
-(define_insn "consttable_end"
-  [(unspec_volatile [(const_int 0)] 11)]
-  ""
-  "* return output_jump_label_table ();"
-  [(set_attr "in_delay_slot" "no")])
-
-;; -------------------------------------------------------------------------
-;; Misc
-;; -------------------------------------------------------------------------
-
-;; String/block move insn.
-
-(define_expand "movstrsi"
-  [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
-		   (mem:BLK (match_operand:BLK 1 "" "")))
-	      (use (match_operand:SI 2 "nonmemory_operand" ""))
-	      (use (match_operand:SI 3 "immediate_operand" ""))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 4))
-	      (clobber (reg:SI 5))
-	      (clobber (reg:SI 0))])]
-  ""
-  "
-{
-  if(expand_block_move (operands))
-     DONE;
-  else FAIL;
-}")
-
-(define_insn "block_move_real"
-  [(parallel [(set (mem:BLK (reg:SI 4))
-		   (mem:BLK (reg:SI 5)))
-	      (use (match_operand:SI 0 "arith_reg_operand" "r"))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 0))])]
-  "! TARGET_HARD_SH4"
-  "jsr	@%0%#"
-  [(set_attr "type" "sfunc")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_insn "block_lump_real"
-  [(parallel [(set (mem:BLK (reg:SI 4))
-		   (mem:BLK (reg:SI 5)))
-	      (use (match_operand:SI 0 "arith_reg_operand" "r"))
-	      (use (reg:SI 6))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 4))
-	      (clobber (reg:SI 5))
-	      (clobber (reg:SI 6))
-	      (clobber (reg:SI 0))])]
-  "! TARGET_HARD_SH4"
-  "jsr	@%0%#"
-  [(set_attr "type" "sfunc")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_insn "block_move_real_i4"
-  [(parallel [(set (mem:BLK (reg:SI 4))
-		   (mem:BLK (reg:SI 5)))
-	      (use (match_operand:SI 0 "arith_reg_operand" "r"))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 1))
-	      (clobber (reg:SI 2))])]
-  "TARGET_HARD_SH4"
-  "jsr	@%0%#"
-  [(set_attr "type" "sfunc")
-   (set_attr "needs_delay_slot" "yes")])
-
-(define_insn "block_lump_real_i4"
-  [(parallel [(set (mem:BLK (reg:SI 4))
-		   (mem:BLK (reg:SI 5)))
-	      (use (match_operand:SI 0 "arith_reg_operand" "r"))
-	      (use (reg:SI 6))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 4))
-	      (clobber (reg:SI 5))
-	      (clobber (reg:SI 6))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 1))
-	      (clobber (reg:SI 2))
-	      (clobber (reg:SI 3))])]
-  "TARGET_HARD_SH4"
-  "jsr	@%0%#"
-  [(set_attr "type" "sfunc")
-   (set_attr "needs_delay_slot" "yes")])
-
-;; -------------------------------------------------------------------------
-;; Floating point instructions.
-;; -------------------------------------------------------------------------
-
-;; ??? All patterns should have a type attribute.
-
-(define_expand "fpu_switch0"
-  [(set (match_operand:SI 0 "" "") (symbol_ref "__fpscr_values"))
-   (set (match_dup 2) (match_dup 1))]
-  ""
-  "
-{
-  operands[1] = gen_rtx (MEM, PSImode, operands[0]);
-  RTX_UNCHANGING_P (operands[1]) = 1;
-  operands[2] = get_fpscr_rtx ();
-}")
-
-(define_expand "fpu_switch1"
-  [(set (match_operand:SI 0 "" "") (symbol_ref "__fpscr_values"))
-   (set (match_dup 1) (plus:SI (match_dup 0) (const_int 4)))
-   (set (match_dup 3) (match_dup 2))]
-  ""
-  "
-{
-  operands[1] = gen_reg_rtx (SImode);
-  operands[2] = gen_rtx (MEM, PSImode, operands[1]);
-  RTX_UNCHANGING_P (operands[2]) = 1;
-  operands[3] = get_fpscr_rtx ();
-}")
-
-(define_expand "movpsi"
-  [(set (match_operand:PSI 0 "register_operand" "")
-	(match_operand:PSI 1 "general_movsrc_operand" ""))]
-  ""
-  "")
-
-;; The c / m alternative is a fake to guide reload to load directly into
-;; fpscr, since reload doesn't know how to use post-increment.
-;; GO_IF_LEGITIMATE_ADDRESS guards about bogus addresses before reload,
-;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
-;; predicate after reload.
-;; The gp_fpul type for r/!c might look a bit odd, but it actually schedules
-;; like a gpr <-> fpul move.
-(define_insn "fpu_switch"
-  [(set (match_operand:PSI 0 "register_operand" "c,c,r,c,c,r,m,r")
-	(match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))]
-  "! reload_completed
-   || true_regnum (operands[0]) != FPSCR_REG || GET_CODE (operands[1]) != MEM
-   || GET_CODE (XEXP (operands[1], 0)) != PLUS"
-  "@
-	! precision stays the same
-	lds.l	%1,fpscr
-	mov.l	%1,%0
-	#
-	lds	%1,fpscr
-	mov	%1,%0
-	mov.l	%1,%0
-	sts	fpscr,%0"
-  [(set_attr "length" "0,2,2,4,2,2,2,2")
-   (set_attr "type" "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")])
-
-(define_split
-  [(set (reg:PSI 48) (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
-  "find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
-  [(set (match_dup 0) (match_dup 0))]
-  "
-{
-  rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
-					gen_rtx (MEM, PSImode,
-						 gen_rtx (POST_INC, Pmode,
-							  operands[0]))));
-  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
-}")
-
-(define_split
-  [(set (reg:PSI 48) (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
-  ""
-  [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
-  "
-{
-  rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
-					gen_rtx (MEM, PSImode,
-						 gen_rtx (POST_INC, Pmode,
-							  operands[0]))));
-  REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
-}")
-
-;; ??? This uses the fp unit, but has no type indicating that.
-;; If we did that, this would either give a bogus latency or introduce
-;; a bogus FIFO constraint.
-;; Since this insn is currently only used for prologues/epilogues,
-;; it is probably best to claim no function unit, which matches the
-;; current setting.
-(define_insn "toggle_sz"
-  [(set (reg:PSI 48) (xor:PSI (reg:PSI 48) (const_int 1048576)))]
-  "TARGET_SH4"
-  "fschg")
-
-(define_expand "addsf3"
-  [(match_operand:SF 0 "arith_reg_operand" "")
-   (match_operand:SF 1 "arith_reg_operand" "")
-   (match_operand:SF 2 "arith_reg_operand" "")]
-  "TARGET_SH3E"
-  "{ expand_sf_binop (&gen_addsf3_i, operands); DONE; }")
-
-(define_insn "addsf3_i"
-  [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
-		 (match_operand:SF 2 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 3 "fpscr_operand" "c"))]
-  "TARGET_SH3E"
-  "fadd	%2,%0"
-  [(set_attr "type" "fp")])
-
-(define_expand "subsf3"
-  [(match_operand:SF 0 "arith_reg_operand" "")
-   (match_operand:SF 1 "arith_reg_operand" "")
-   (match_operand:SF 2 "arith_reg_operand" "")]
-  "TARGET_SH3E"
-  "{ expand_sf_binop (&gen_subsf3_i, operands); DONE; }")
-
-(define_insn "subsf3_i"
-  [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(minus:SF (match_operand:SF 1 "arith_reg_operand" "0")
-		 (match_operand:SF 2 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 3 "fpscr_operand" "c"))]
-  "TARGET_SH3E"
-  "fsub	%2,%0"
-  [(set_attr "type" "fp")])
-
-;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
-;; register in feeding fp instructions.  Thus, we cannot generate fmac for
-;; mixed-precision SH4 targets.  To allow it to be still generated for the
-;; SH3E, we use a separate insn for SH3E mulsf3.
-
-(define_expand "mulsf3"
-  [(match_operand:SF 0 "arith_reg_operand" "")
-   (match_operand:SF 1 "arith_reg_operand" "")
-   (match_operand:SF 2 "arith_reg_operand" "")]
-  "TARGET_SH3E"
-  "
-{
-  if (TARGET_SH4)
-    expand_sf_binop (&gen_mulsf3_i4, operands);
-  else
-    emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn "mulsf3_i4"
-  [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(mult:SF (match_operand:SF 1 "arith_reg_operand" "%0")
-		 (match_operand:SF 2 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 3 "fpscr_operand" "c"))]
-  "TARGET_SH3E"
-  "fmul	%2,%0"
-  [(set_attr "type" "fp")])
-
-(define_insn "mulsf3_ie"
-  [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(mult:SF (match_operand:SF 1 "arith_reg_operand" "%0")
-		 (match_operand:SF 2 "arith_reg_operand" "f")))]
-  "TARGET_SH3E && ! TARGET_SH4"
-  "fmul	%2,%0"
-  [(set_attr "type" "fp")])
-
-(define_insn "*macsf3"
-  [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(plus:SF (mult:SF (match_operand:SF 1 "arith_reg_operand" "%w")
-			  (match_operand:SF 2 "arith_reg_operand" "f"))
-		 (match_operand:SF 3 "arith_reg_operand" "0")))
-   (use (match_operand:PSI 4 "fpscr_operand" "c"))]
-  "TARGET_SH3E && ! TARGET_SH4"
-  "fmac	fr0,%2,%0"
-  [(set_attr "type" "fp")])
-
-(define_expand "divsf3"
-  [(match_operand:SF 0 "arith_reg_operand" "")
-   (match_operand:SF 1 "arith_reg_operand" "")
-   (match_operand:SF 2 "arith_reg_operand" "")]
-  "TARGET_SH3E"
-  "{ expand_sf_binop (&gen_divsf3_i, operands); DONE; }")
-
-(define_insn "divsf3_i"
-  [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(div:SF (match_operand:SF 1 "arith_reg_operand" "0")
-		 (match_operand:SF 2 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 3 "fpscr_operand" "c"))]
-  "TARGET_SH3E"
-  "fdiv	%2,%0"
-  [(set_attr "type" "fdiv")])
-
-(define_expand "floatsisf2"
-  [(set (reg:SI 22)
-	(match_operand:SI 1 "arith_reg_operand" ""))
-   (parallel [(set (match_operand:SF 0 "arith_reg_operand" "")
-		   (float:SF (reg:SI 22)))
-	      (use (match_dup 2))])]
-  "TARGET_SH3E"
-  "
-{
-  if (TARGET_SH4)
-    {
-      emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 22),
-			  operands[1]));
-      emit_sf_insn (gen_floatsisf2_i4 (operands[0], get_fpscr_rtx ()));
-      DONE;
-    }
-  operands[2] = get_fpscr_rtx ();
-}")
-
-(define_insn "floatsisf2_i4"
-  [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(float:SF (reg:SI 22)))
-   (use (match_operand:PSI 1 "fpscr_operand" "c"))]
-  "TARGET_SH3E"
-  "float	fpul,%0"
-  [(set_attr "type" "fp")])
-
-(define_insn "*floatsisf2_ie"
-  [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(float:SF (reg:SI 22)))]
-  "TARGET_SH3E && ! TARGET_SH4"
-  "float	fpul,%0"
-  [(set_attr "type" "fp")])
-
-(define_expand "fix_truncsfsi2"
-  [(set (reg:SI 22)
-	(fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
-   (set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(reg:SI 22))]
-  "TARGET_SH3E"
-  "
-{
-  if (TARGET_SH4)
-    {
-      emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[1], get_fpscr_rtx ()));
-      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
-			  gen_rtx (REG, SImode, 22)));
-      DONE;
-    }
-}")
-
-(define_insn "fix_truncsfsi2_i4"
-  [(set (reg:SI 22)
-	(fix:SI (match_operand:SF 0 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 1 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "ftrc	%0,fpul"
-  [(set_attr "type" "fp")])
-
-(define_insn "fix_truncsfsi2_i4_2"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
-   (use (reg:SI 48))
-   (clobber (reg:SI 22))]
-  "TARGET_SH4"
-  "#"
-  [(set_attr "length" "4")])
-
-(define_split
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (reg:SI 22))]
-  "TARGET_SH4"
-  [(parallel [(set (reg:SI 22) (fix:SI (match_dup 1)))
-	      (use (match_dup 2))])
-   (set (match_dup 0) (reg:SI 22))])
-
-(define_insn "*fixsfsi"
-  [(set (reg:SI 22)
-	(fix:SI (match_operand:SF 0 "arith_reg_operand" "f")))]
-  "TARGET_SH3E && ! TARGET_SH4"
-  "ftrc	%0,fpul"
-  [(set_attr "type" "fp")])
-
-(define_insn "cmpgtsf_t"
-  [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "arith_reg_operand" "f")
-			   (match_operand:SF 1 "arith_reg_operand" "f")))]
-  "TARGET_SH3E && ! TARGET_SH4"
-  "fcmp/gt	%1,%0"
-  [(set_attr "type" "fp")])
-
-(define_insn "cmpeqsf_t"
-  [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
-			   (match_operand:SF 1 "arith_reg_operand" "f")))]
-  "TARGET_SH3E && ! TARGET_SH4"
-  "fcmp/eq	%1,%0"
-  [(set_attr "type" "fp")])
-
-(define_insn "ieee_ccmpeqsf_t"
-  [(set (reg:SI 18) (ior:SI (reg:SI 18)
-			    (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
-				   (match_operand:SF 1 "arith_reg_operand" "f"))))]
-  "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
-  "* return output_ieee_ccmpeq (insn, operands);"
-  [(set_attr "length" "4")])
-
-
-(define_insn "cmpgtsf_t_i4"
-  [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "arith_reg_operand" "f")
-			   (match_operand:SF 1 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fcmp/gt	%1,%0"
-  [(set_attr "type" "fp")])
-
-(define_insn "cmpeqsf_t_i4"
-  [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
-			   (match_operand:SF 1 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fcmp/eq	%1,%0"
-  [(set_attr "type" "fp")])
-
-(define_insn "*ieee_ccmpeqsf_t_4"
-  [(set (reg:SI 18) (ior:SI (reg:SI 18)
-			    (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
-				   (match_operand:SF 1 "arith_reg_operand" "f"))))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))]
-  "TARGET_IEEE && TARGET_SH4"
-  "* return output_ieee_ccmpeq (insn, operands);"
-  [(set_attr "length" "4")])
-
-(define_expand "cmpsf"
-  [(set (reg:SI 18) (compare (match_operand:SF 0 "arith_operand" "")
-			     (match_operand:SF 1 "arith_operand" "")))]
-  "TARGET_SH3E"
-  "
-{
-  sh_compare_op0 = operands[0];
-  sh_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "negsf2"
-  [(match_operand:SF 0 "arith_reg_operand" "")
-   (match_operand:SF 1 "arith_reg_operand" "")]
-  "TARGET_SH3E"
-  "{ expand_sf_unop (&gen_negsf2_i, operands); DONE; }")
-
-(define_insn "negsf2_i"
-  [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(neg:SF (match_operand:SF 1 "arith_reg_operand" "0")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))]
-  "TARGET_SH3E"
-  "fneg	%0"
-  [(set_attr "type" "fmove")])
-
-(define_expand "sqrtsf2"
-  [(match_operand:SF 0 "arith_reg_operand" "")
-   (match_operand:SF 1 "arith_reg_operand" "")]
-  "TARGET_SH3E"
-  "{ expand_sf_unop (&gen_sqrtsf2_i, operands); DONE; }")
-
-(define_insn "sqrtsf2_i"
-  [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "arith_reg_operand" "0")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))]
-  "TARGET_SH3E"
-  "fsqrt	%0"
-  [(set_attr "type" "fdiv")])
-
-(define_expand "abssf2"
-  [(match_operand:SF 0 "arith_reg_operand" "")
-   (match_operand:SF 1 "arith_reg_operand" "")]
-  "TARGET_SH3E"
-  "{ expand_sf_unop (&gen_abssf2_i, operands); DONE; }")
-
-(define_insn "abssf2_i"
-  [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(abs:SF (match_operand:SF 1 "arith_reg_operand" "0")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))]
-  "TARGET_SH3E"
-  "fabs	%0"
-  [(set_attr "type" "fmove")])
-
-(define_expand "adddf3"
-  [(match_operand:DF 0 "arith_reg_operand" "")
-   (match_operand:DF 1 "arith_reg_operand" "")
-   (match_operand:DF 2 "arith_reg_operand" "")]
-  "TARGET_SH4"
-  "{ expand_df_binop (&gen_adddf3_i, operands); DONE; }")
-
-(define_insn "adddf3_i"
-  [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(plus:DF (match_operand:DF 1 "arith_reg_operand" "%0")
-		 (match_operand:DF 2 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 3 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fadd	%2,%0"
-  [(set_attr "type" "dfp_arith")])
-
-(define_expand "subdf3"
-  [(match_operand:DF 0 "arith_reg_operand" "")
-   (match_operand:DF 1 "arith_reg_operand" "")
-   (match_operand:DF 2 "arith_reg_operand" "")]
-  "TARGET_SH4"
-  "{ expand_df_binop (&gen_subdf3_i, operands); DONE; }")
-
-(define_insn "subdf3_i"
-  [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(minus:DF (match_operand:DF 1 "arith_reg_operand" "0")
-		  (match_operand:DF 2 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 3 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fsub	%2,%0"
-  [(set_attr "type" "dfp_arith")])
-
-(define_expand "muldf3"
-  [(match_operand:DF 0 "arith_reg_operand" "")
-   (match_operand:DF 1 "arith_reg_operand" "")
-   (match_operand:DF 2 "arith_reg_operand" "")]
-  "TARGET_SH4"
-  "{ expand_df_binop (&gen_muldf3_i, operands); DONE; }")
-
-(define_insn "muldf3_i"
-  [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(mult:DF (match_operand:DF 1 "arith_reg_operand" "%0")
-		 (match_operand:DF 2 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 3 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fmul	%2,%0"
-  [(set_attr "type" "dfp_arith")])
-
-(define_expand "divdf3"
-  [(match_operand:DF 0 "arith_reg_operand" "")
-   (match_operand:DF 1 "arith_reg_operand" "")
-   (match_operand:DF 2 "arith_reg_operand" "")]
-  "TARGET_SH4"
-  "{ expand_df_binop (&gen_divdf3_i, operands); DONE; }")
-
-(define_insn "divdf3_i"
-  [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(div:DF (match_operand:DF 1 "arith_reg_operand" "0")
-		(match_operand:DF 2 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 3 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fdiv	%2,%0"
-  [(set_attr "type" "dfdiv")])
-
-(define_expand "floatsidf2"
-  [(match_operand:DF 0 "arith_reg_operand" "")
-   (match_operand:SI 1 "arith_reg_operand" "")]
-  "TARGET_SH4"
-  "
-{
-  emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 22), operands[1]));
-  emit_df_insn (gen_floatsidf2_i (operands[0], get_fpscr_rtx ()));
-  DONE;
-}")
-
-(define_insn "floatsidf2_i"
-  [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(float:DF (reg:SI 22)))
-   (use (match_operand:PSI 1 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "float	fpul,%0"
-  [(set_attr "type" "dfp_conv")])
-
-(define_expand "fix_truncdfsi2"
-  [(match_operand:SI 0 "arith_reg_operand" "=r")
-   (match_operand:DF 1 "arith_reg_operand" "f")]
-  "TARGET_SH4"
-  "
-{
-  emit_df_insn (gen_fix_truncdfsi2_i (operands[1], get_fpscr_rtx ()));
-  emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (REG, SImode, 22)));
-  DONE;
-}")
-
-(define_insn "fix_truncdfsi2_i"
-  [(set (reg:SI 22)
-	(fix:SI (match_operand:DF 0 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 1 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "ftrc	%0,fpul"
-  [(set_attr "type" "dfp_conv")])
-
-(define_insn "fix_truncdfsi2_i4"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (reg:SI 22))]
-  "TARGET_SH4"
-  "#"
-  [(set_attr "length" "4")])
-
-(define_split
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (reg:SI 22))]
-  "TARGET_SH4"
-  [(parallel [(set (reg:SI 22) (fix:SI (match_dup 1)))
-	      (use (match_dup 2))])
-   (set (match_dup 0) (reg:SI 22))])
-
-(define_insn "cmpgtdf_t"
-  [(set (reg:SI 18) (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
-			   (match_operand:DF 1 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fcmp/gt	%1,%0"
-  [(set_attr "type" "dfp_cmp")])
-
-(define_insn "cmpeqdf_t"
-  [(set (reg:SI 18) (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
-			   (match_operand:DF 1 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fcmp/eq	%1,%0"
-  [(set_attr "type" "dfp_cmp")])
-
-(define_insn "*ieee_ccmpeqdf_t"
-  [(set (reg:SI 18) (ior:SI (reg:SI 18)
-			    (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
-				   (match_operand:DF 1 "arith_reg_operand" "f"))))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))]
-  "TARGET_IEEE && TARGET_SH4"
-  "* return output_ieee_ccmpeq (insn, operands);"
-  [(set_attr "length" "4")])
-
-(define_expand "cmpdf"
-  [(set (reg:SI 18) (compare (match_operand:DF 0 "arith_operand" "")
-			     (match_operand:DF 1 "arith_operand" "")))]
-  "TARGET_SH4"
-  "
-{
-  sh_compare_op0 = operands[0];
-  sh_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "negdf2"
-  [(match_operand:DF 0 "arith_reg_operand" "")
-   (match_operand:DF 1 "arith_reg_operand" "")]
-  "TARGET_SH4"
-  "{ expand_df_unop (&gen_negdf2_i, operands); DONE; }")
-
-(define_insn "negdf2_i"
-  [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(neg:DF (match_operand:DF 1 "arith_reg_operand" "0")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fneg	%0"
-  [(set_attr "type" "fmove")])
-
-(define_expand "sqrtdf2"
-  [(match_operand:DF 0 "arith_reg_operand" "")
-   (match_operand:DF 1 "arith_reg_operand" "")]
-  "TARGET_SH4"
-  "{ expand_df_unop (&gen_sqrtdf2_i, operands); DONE; }")
-
-(define_insn "sqrtdf2_i"
-  [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(sqrt:DF (match_operand:DF 1 "arith_reg_operand" "0")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fsqrt	%0"
-  [(set_attr "type" "dfdiv")])
-
-(define_expand "absdf2"
-  [(match_operand:DF 0 "arith_reg_operand" "")
-   (match_operand:DF 1 "arith_reg_operand" "")]
-  "TARGET_SH4"
-  "{ expand_df_unop (&gen_absdf2_i, operands); DONE; }")
-
-(define_insn "absdf2_i"
-  [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(abs:DF (match_operand:DF 1 "arith_reg_operand" "0")))
-   (use (match_operand:PSI 2 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fabs	%0"
-  [(set_attr "type" "fmove")])
-
-(define_expand "extendsfdf2"
-  [(match_operand:DF 0 "arith_reg_operand" "")
-   (match_operand:SF 1 "arith_reg_operand" "")]
-  "TARGET_SH4"
-  "
-{
-  emit_sf_insn (gen_movsf_ie (gen_rtx (REG, SFmode, 22), operands[1],
-			      get_fpscr_rtx ()));
-  emit_df_insn (gen_extendsfdf2_i4 (operands[0], get_fpscr_rtx ()));
-  DONE;
-}")
-
-(define_insn "extendsfdf2_i4"
-  [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(float_extend:DF (reg:SF 22)))
-   (use (match_operand:PSI 1 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fcnvsd  fpul,%0"
-  [(set_attr "type" "fp")])
-
-(define_expand "truncdfsf2"
-  [(match_operand:SF 0 "arith_reg_operand" "")
-   (match_operand:DF 1 "arith_reg_operand" "")]
-  "TARGET_SH4"
-  "
-{
-  emit_df_insn (gen_truncdfsf2_i4 (operands[1], get_fpscr_rtx ()));
-  emit_sf_insn (gen_movsf_ie (operands[0], gen_rtx (REG, SFmode, 22),
-			   get_fpscr_rtx ()));
-  DONE;
-}")
-
-(define_insn "truncdfsf2_i4"
-  [(set (reg:SF 22)
-	(float_truncate:SF (match_operand:DF 0 "arith_reg_operand" "f")))
-   (use (match_operand:PSI 1 "fpscr_operand" "c"))]
-  "TARGET_SH4"
-  "fcnvds  %0,fpul"
-  [(set_attr "type" "fp")])
-
-;; Bit field extract patterns.  These give better code for packed bitfields,
-;; because they allow auto-increment addresses to be generated.
-
-(define_expand "insv"
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
-			 (match_operand:SI 1 "immediate_operand" "")
-			 (match_operand:SI 2 "immediate_operand" ""))
-	(match_operand:SI 3 "general_operand" ""))]
-  "! TARGET_LITTLE_ENDIAN"
-  "
-{
-  rtx addr_target, orig_address, shift_reg;
-  HOST_WIDE_INT size;
-
-  /* ??? expmed doesn't care for non-register predicates.  */
-  if (! memory_operand (operands[0], VOIDmode)
-      || ! immediate_operand (operands[1], VOIDmode)
-      || ! immediate_operand (operands[2], VOIDmode)
-      || ! general_operand (operands[3], VOIDmode))
-    FAIL;
-  /* If this isn't a 16 / 24 / 32 bit field, or if
-     it doesn't start on a byte boundary, then fail.  */
-  size = INTVAL (operands[1]);
-  if (size < 16 || size > 32 || size % 8 != 0
-      || (INTVAL (operands[2]) % 8) != 0)
-    FAIL;
-
-  size /= 8;
-  orig_address = XEXP (operands[0], 0);
-  addr_target = gen_reg_rtx (SImode);
-  shift_reg = gen_reg_rtx (SImode);
-  emit_insn (gen_movsi (shift_reg, operands[3]));
-  emit_insn (gen_addsi3 (addr_target, orig_address, GEN_INT (size - 1)));
-
-  operands[0] = change_address (operands[0], QImode, addr_target);
-  emit_insn (gen_movqi (operands[0], gen_rtx (SUBREG, QImode, shift_reg, 0)));
-
-  while (size -= 1)
-    {
-      emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
-      emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
-      emit_insn (gen_movqi (operands[0],
-			    gen_rtx (SUBREG, QImode, shift_reg, 0)));
-    }
-
-  DONE;
-}")
-
-;; -------------------------------------------------------------------------
-;; Peepholes
-;; -------------------------------------------------------------------------
-
-;; This matches cases where a stack pointer increment at the start of the
-;; epilogue combines with a stack slot read loading the return value.
-
-(define_peephole
-  [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
-   (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
-  "REGNO (operands[1]) != REGNO (operands[0])"
-  "mov.l	@%1+,%0")
-
-;; See the comment on the dt combiner pattern above.
-
-(define_peephole
-  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(plus:SI (match_dup 0)
-		 (const_int -1)))
-   (set (reg:SI 18)
-	(eq:SI (match_dup 0)
-	       (const_int 0)))]
-  "TARGET_SH2"
-  "dt	%0")
-
-;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
-;; to `mov #k,r0; mov.l @(r0,r15),rn'.  These sequences are generated by
-;; reload when the constant is too large for a reg+offset address.
-
-;; ??? We would get much better code if this was done in reload.  This would
-;; require modifying find_reloads_address to recognize that if the constant
-;; is out-of-range for an immediate add, then we get better code by reloading
-;; the constant into a register than by reloading the sum into a register,
-;; since the former is one instruction shorter if the address does not need
-;; to be offsettable.  Unfortunately this does not work, because there is
-;; only one register, r0, that can be used as an index register.  This register
-;; is also the function return value register.  So, if we try to force reload
-;; to use double-reg addresses, then we end up with some instructions that
-;; need to use r0 twice.  The only way to fix this is to change the calling
-;; convention so that r0 is not used to return values.
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
-   (set (mem:SI (match_dup 0))
-	(match_operand:SI 2 "general_movsrc_operand" ""))]
-  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
-  "mov.l	%2,@(%0,%1)")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
-   (set (match_operand:SI 2 "general_movdst_operand" "")
-	(mem:SI (match_dup 0)))]
-  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
-  "mov.l	@(%0,%1),%2")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
-   (set (mem:HI (match_dup 0))
-	(match_operand:HI 2 "general_movsrc_operand" ""))]
-  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
-  "mov.w	%2,@(%0,%1)")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
-   (set (match_operand:HI 2 "general_movdst_operand" "")
-	(mem:HI (match_dup 0)))]
-  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
-  "mov.w	@(%0,%1),%2")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
-   (set (mem:QI (match_dup 0))
-	(match_operand:QI 2 "general_movsrc_operand" ""))]
-  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
-  "mov.b	%2,@(%0,%1)")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
-   (set (match_operand:QI 2 "general_movdst_operand" "")
-	(mem:QI (match_dup 0)))]
-  "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
-  "mov.b	@(%0,%1),%2")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
-   (set (mem:SF (match_dup 0))
-	(match_operand:SF 2 "general_movsrc_operand" ""))]
-  "REGNO (operands[0]) == 0
-   && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
-       || (GET_CODE (operands[2]) == SUBREG
-	   && REGNO (SUBREG_REG (operands[2])) < 16))
-   && reg_unused_after (operands[0], insn)"
-  "mov.l	%2,@(%0,%1)")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
-   (set (match_operand:SF 2 "general_movdst_operand" "")
-
-	(mem:SF (match_dup 0)))]
-  "REGNO (operands[0]) == 0
-   && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
-       || (GET_CODE (operands[2]) == SUBREG
-	   && REGNO (SUBREG_REG (operands[2])) < 16))
-   && reg_unused_after (operands[0], insn)"
-  "mov.l	@(%0,%1),%2")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
-   (set (mem:SF (match_dup 0))
-	(match_operand:SF 2 "general_movsrc_operand" ""))]
-  "REGNO (operands[0]) == 0
-   && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) >= FIRST_FP_REG)
-       || (GET_CODE (operands[2]) == SUBREG
-	   && REGNO (SUBREG_REG (operands[2])) >= FIRST_FP_REG))
-   && reg_unused_after (operands[0], insn)"
-  "fmov{.s|}	%2,@(%0,%1)")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
-   (set (match_operand:SF 2 "general_movdst_operand" "")
-
-	(mem:SF (match_dup 0)))]
-  "REGNO (operands[0]) == 0
-   && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) >= FIRST_FP_REG)
-       || (GET_CODE (operands[2]) == SUBREG
-	   && REGNO (SUBREG_REG (operands[2])) >= FIRST_FP_REG))
-   && reg_unused_after (operands[0], insn)"
-  "fmov{.s|}	@(%0,%1),%2")
-
-;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).  */
-(define_insn "sp_switch_1"
-  [(const_int 1)]
-  ""
-  "*
-{
-  rtx xoperands[1];
-
-  xoperands[0] = sp_switch;
-  output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", xoperands);
-  output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", xoperands);
-  return \"mov r0,r15\";
-}"
-  [(set_attr "length" "10")])
-
-;; Switch back to the original stack for interrupt functions with the
-;; sp_switch attribute.  */
-(define_insn "sp_switch_2"
-  [(const_int 2)]
-  ""
-  "mov.l @r15+,r15\;mov.l @r15+,r0"
-  [(set_attr "length" "4")])
diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
deleted file mode 100755
index bfbf45e..0000000
--- a/gcc/config/sh/t-sh
+++ /dev/null
@@ -1,29 +0,0 @@
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = sh/lib1funcs.asm
-LIB1ASMFUNCS = _ashiftrt _ashiftrt_n _ashiftlt _lshiftrt _movstr \
-  _movstr_i4 _mulsi3 _sdivsi3 _sdivsi3_i4 _udivsi3 _udivsi3_i4 _set_fpscr
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#ifdef __LITTLE_ENDIAN__' > dp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>dp-bit.c
-	echo '#endif' 		>> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#ifdef __LITTLE_ENDIAN__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>fp-bit.c
-	echo '#endif' 		>> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-MULTILIB_OPTIONS= ml m2/m3e/m4-single-only/m4-single/m4
-MULTILIB_DIRNAMES= 
-MULTILIB_MATCHES = m2=m3
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/sh/xm-sh.h b/gcc/config/sh/xm-sh.h
deleted file mode 100755
index f51b787..0000000
--- a/gcc/config/sh/xm-sh.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Configuration for GNU C-compiler for Hitachi SH.
-   Copyright (C) 1993, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-
-/* If compiled with GNU C, use the built-in alloca.  */
-#ifdef __GNUC__
-#define alloca __builtin_alloca
-#endif
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.  */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
diff --git a/gcc/config/sparc/aout.h b/gcc/config/sparc/aout.h
deleted file mode 100755
index 478d710..0000000
--- a/gcc/config/sparc/aout.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SPARC using a.out.
-   Copyright (C) 1994, 1996 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sparc/sparc.h"	/* SPARC definitions */
-#include "aoutos.h"		/* A.out definitions */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -Acpu(sparc) -Amachine(sparc)"
diff --git a/gcc/config/sparc/bsd.h b/gcc/config/sparc/bsd.h
deleted file mode 100755
index 761abe2..0000000
--- a/gcc/config/sparc/bsd.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#include "sparc/sparc.h"
-
-#undef LIB_SPEC
-#define LIB_SPEC	"%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
- 
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC	"%{pg:gcrt0.o%s}%{!pg:%{p:gcrt0.o%s}%{!p:crt0.o%s}}"
diff --git a/gcc/config/sparc/elf.h b/gcc/config/sparc/elf.h
deleted file mode 100755
index 635238f..0000000
--- a/gcc/config/sparc/elf.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Definitions of target machine for GNU compiler,
-   for SPARC running in an embedded environment using the ELF file format.
-   Copyright (C) 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sol2.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -D__elf__ -Acpu(sparc) -Amachine(sparc)"
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
-
-/* Use the default.  */
-#undef LINK_SPEC
-
-/* Don't set the target flags, this is done by the linker script */
-#undef LIB_SPEC
-#define LIB_SPEC ""
-
-/* FIXME: until fixed */
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 64
-
-/* This solaris2 define does not apply.  */
-#undef STDC_0_IN_SYSTEM_HEADERS
-
-/* We don't want to use the Solaris2 specific long long int conversion
-   routines.  */
-#undef INIT_SUBTARGET_OPTABS
-#define INIT_SUBTARGET_OPTABS
-
-/* ??? We haven't added Solaris2 equivalent 64 bit library routines to
-   lb1sp*.asm, so we need to avoid using them.  */
-#undef MULDI3_LIBCALL
-#undef DIVDI3_LIBCALL
-#undef UDIVDI3_LIBCALL
-#undef MODDI3_LIBCALL
-#undef UMODDI3_LIBCALL
diff --git a/gcc/config/sparc/gmon-sol2.c b/gcc/config/sparc/gmon-sol2.c
deleted file mode 100755
index 2a5b898..0000000
--- a/gcc/config/sparc/gmon-sol2.c
+++ /dev/null
@@ -1,429 +0,0 @@
-/*-
- * Copyright (c) 1991 The Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/* Mangled into a form that works on Sparc Solaris 2 by Mark Eichin
- * for Cygnus Support, July 1992.
- */
-
-#ifndef lint
-static char sccsid[] = "@(#)gmon.c	5.3 (Berkeley) 5/22/91";
-#endif /* not lint */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <limits.h>
-#include <unistd.h>
-#include <fcntl.h>
-
-#if 0
-#include "sparc/gmon.h"
-#else
-struct phdr {
-  char *lpc;
-  char *hpc;
-  int ncnt;
-};
-#define HISTFRACTION 2
-#define HISTCOUNTER unsigned short
-#define HASHFRACTION 1
-#define ARCDENSITY 2
-#define MINARCS 50
-struct tostruct {
-  char *selfpc;
-  long count;
-  unsigned short link;
-};
-struct rawarc {
-    unsigned long       raw_frompc;
-    unsigned long       raw_selfpc;
-    long                raw_count;
-};
-#define ROUNDDOWN(x,y)  (((x)/(y))*(y))
-#define ROUNDUP(x,y)    ((((x)+(y)-1)/(y))*(y))
-
-#endif
-
-/* extern mcount() asm ("mcount"); */
-/*extern*/ char *minbrk /* asm ("minbrk") */;
-
-    /*
-     *	froms is actually a bunch of unsigned shorts indexing tos
-     */
-static int		profiling = 3;
-static unsigned short	*froms;
-static struct tostruct	*tos = 0;
-static long		tolimit = 0;
-static char		*s_lowpc = 0;
-static char		*s_highpc = 0;
-static unsigned long	s_textsize = 0;
-
-static int	ssiz;
-static char	*sbuf;
-static int	s_scale;
-    /* see profil(2) where this is describe (incorrectly) */
-#define		SCALE_1_TO_1	0x10000L
-
-#define	MSG "No space for profiling buffer(s)\n"
-
-static void moncontrol();
-
-void monstartup(lowpc, highpc)
-    char	*lowpc;
-    char	*highpc;
-{
-    int			monsize;
-    char		*buffer;
-    register int	o;
-
-	/*
-	 *	round lowpc and highpc to multiples of the density we're using
-	 *	so the rest of the scaling (here and in gprof) stays in ints.
-	 */
-    lowpc = (char *)
-	    ROUNDDOWN((unsigned)lowpc, HISTFRACTION*sizeof(HISTCOUNTER));
-    s_lowpc = lowpc;
-    highpc = (char *)
-	    ROUNDUP((unsigned)highpc, HISTFRACTION*sizeof(HISTCOUNTER));
-    s_highpc = highpc;
-    s_textsize = highpc - lowpc;
-    monsize = (s_textsize / HISTFRACTION) + sizeof(struct phdr);
-    buffer = sbrk( monsize );
-    if ( buffer == (char *) -1 ) {
-	write( 2 , MSG , sizeof(MSG) );
-	return;
-    }
-    froms = (unsigned short *) sbrk( s_textsize / HASHFRACTION );
-    if ( froms == (unsigned short *) -1 ) {
-	write( 2 , MSG , sizeof(MSG) );
-	froms = 0;
-	return;
-    }
-    tolimit = s_textsize * ARCDENSITY / 100;
-    if ( tolimit < MINARCS ) {
-	tolimit = MINARCS;
-    } else if ( tolimit > 65534 ) {
-	tolimit = 65534;
-    }
-    tos = (struct tostruct *) sbrk( tolimit * sizeof( struct tostruct ) );
-    if ( tos == (struct tostruct *) -1 ) {
-	write( 2 , MSG , sizeof(MSG) );
-	froms = 0;
-	tos = 0;
-	return;
-    }
-    minbrk = sbrk(0);
-    tos[0].link = 0;
-    sbuf = buffer;
-    ssiz = monsize;
-    ( (struct phdr *) buffer ) -> lpc = lowpc;
-    ( (struct phdr *) buffer ) -> hpc = highpc;
-    ( (struct phdr *) buffer ) -> ncnt = ssiz;
-    monsize -= sizeof(struct phdr);
-    if ( monsize <= 0 )
-	return;
-    o = highpc - lowpc;
-    if( monsize < o )
-#ifndef hp300
-	s_scale = ( (float) monsize / o ) * SCALE_1_TO_1;
-#else /* avoid floating point */
-    {
-	int quot = o / monsize;
-
-	if (quot >= 0x10000)
-		s_scale = 1;
-	else if (quot >= 0x100)
-		s_scale = 0x10000 / quot;
-	else if (o >= 0x800000)
-		s_scale = 0x1000000 / (o / (monsize >> 8));
-	else
-		s_scale = 0x1000000 / ((o << 8) / monsize);
-    }
-#endif
-    else
-	s_scale = SCALE_1_TO_1;
-    moncontrol(1);
-}
-
-void
-_mcleanup()
-{
-    int			fd;
-    int			fromindex;
-    int			endfrom;
-    char		*frompc;
-    int			toindex;
-    struct rawarc	rawarc;
-    char		*profdir;
-    char		*proffile;
-    char		*progname;
-    char		 buf[PATH_MAX];
-    extern char	       **___Argv;
-
-    moncontrol(0);
-
-    if ((profdir = getenv("PROFDIR")) != NULL) {
-	/* If PROFDIR contains a null value, no profiling output is produced */
-	if (*profdir == '\0') {
-	    return;
-	}
-
-	progname=strrchr(___Argv[0], '/');
-	if (progname == NULL)
-	    progname=___Argv[0];
-	else
-	    progname++;
-
-	sprintf(buf, "%s/%ld.%s", profdir, getpid(), progname);
-	proffile = buf;
-    } else {
-	proffile = "gmon.out";
-    }
-
-    fd = creat( proffile, 0666 );
-    if ( fd < 0 ) {
-	perror( proffile );
-	return;
-    }
-#   ifdef DEBUG
-	fprintf( stderr , "[mcleanup] sbuf 0x%x ssiz %d\n" , sbuf , ssiz );
-#   endif DEBUG
-    write( fd , sbuf , ssiz );
-    endfrom = s_textsize / (HASHFRACTION * sizeof(*froms));
-    for ( fromindex = 0 ; fromindex < endfrom ; fromindex++ ) {
-	if ( froms[fromindex] == 0 ) {
-	    continue;
-	}
-	frompc = s_lowpc + (fromindex * HASHFRACTION * sizeof(*froms));
-	for (toindex=froms[fromindex]; toindex!=0; toindex=tos[toindex].link) {
-#	    ifdef DEBUG
-		fprintf( stderr ,
-			"[mcleanup] frompc 0x%x selfpc 0x%x count %d\n" ,
-			frompc , tos[toindex].selfpc , tos[toindex].count );
-#	    endif DEBUG
-	    rawarc.raw_frompc = (unsigned long) frompc;
-	    rawarc.raw_selfpc = (unsigned long) tos[toindex].selfpc;
-	    rawarc.raw_count = tos[toindex].count;
-	    write( fd , &rawarc , sizeof rawarc );
-	}
-    }
-    close( fd );
-}
-
-/*
- * The Sparc stack frame is only held together by the frame pointers
- * in the register windows. According to the SVR4 SPARC ABI
- * Supplement, Low Level System Information/Operating System
- * Interface/Software Trap Types, a type 3 trap will flush all of the
- * register windows to the stack, which will make it possible to walk
- * the frames and find the return addresses.
- * 	However, it seems awfully expensive to incur a trap (system
- * call) for every function call. It turns out that "call" simply puts
- * the return address in %o7 expecting the "save" in the procedure to
- * shift it into %i7; this means that before the "save" occurs, %o7
- * contains the address of the call to mcount, and %i7 still contains
- * the caller above that. The asm mcount here simply saves those
- * registers in argument registers and branches to internal_mcount,
- * simulating a call with arguments.
- * 	Kludges:
- * 	1) the branch to internal_mcount is hard coded; it should be
- * possible to tell asm to use the assembler-name of a symbol.
- * 	2) in theory, the function calling mcount could have saved %i7
- * somewhere and reused the register; in practice, I *think* this will
- * break longjmp (and maybe the debugger) but I'm not certain. (I take
- * some comfort in the knowledge that it will break the native mcount
- * as well.)
- * 	3) if builtin_return_address worked, this could be portable.
- * However, it would really have to be optimized for arguments of 0
- * and 1 and do something like what we have here in order to avoid the
- * trap per function call performance hit. 
- * 	4) the atexit and monsetup calls prevent this from simply
- * being a leaf routine that doesn't do a "save" (and would thus have
- * access to %o7 and %i7 directly) but the call to write() at the end
- * would have also prevented this.
- *
- * -- [eichin:19920702.1107EST]
- */
-
-/* i7 == last ret, -> frompcindex */
-/* o7 == current ret, -> selfpc */
-/* Solaris 2 libraries use _mcount.  */
-asm(".global _mcount; _mcount: mov %i7,%o1; mov %o7,%o0;b,a internal_mcount");
-/* This is for compatibility with old versions of gcc which used mcount.  */
-asm(".global mcount; mcount: mov %i7,%o1; mov %o7,%o0;b,a internal_mcount");
-
-static void internal_mcount(selfpc, frompcindex)
-	register char			*selfpc;
-	register unsigned short		*frompcindex;
-{
-	register struct tostruct	*top;
-	register struct tostruct	*prevtop;
-	register long			toindex;
-	static char already_setup;
-
-	/*
-	 *	find the return address for mcount,
-	 *	and the return address for mcount's caller.
-	 */
-
-	if(!already_setup) {
-          extern etext();
-	  already_setup = 1;
-	  monstartup(0, etext);
-#ifdef USE_ONEXIT
-	  on_exit(_mcleanup, 0);
-#else
-	  atexit(_mcleanup);
-#endif
-	}
-	/*
-	 *	check that we are profiling
-	 *	and that we aren't recursively invoked.
-	 */
-	if (profiling) {
-		goto out;
-	}
-	profiling++;
-	/*
-	 *	check that frompcindex is a reasonable pc value.
-	 *	for example:	signal catchers get called from the stack,
-	 *			not from text space.  too bad.
-	 */
-	frompcindex = (unsigned short *)((long)frompcindex - (long)s_lowpc);
-	if ((unsigned long)frompcindex > s_textsize) {
-		goto done;
-	}
-	frompcindex =
-	    &froms[((long)frompcindex) / (HASHFRACTION * sizeof(*froms))];
-	toindex = *frompcindex;
-	if (toindex == 0) {
-		/*
-		 *	first time traversing this arc
-		 */
-		toindex = ++tos[0].link;
-		if (toindex >= tolimit) {
-			goto overflow;
-		}
-		*frompcindex = toindex;
-		top = &tos[toindex];
-		top->selfpc = selfpc;
-		top->count = 1;
-		top->link = 0;
-		goto done;
-	}
-	top = &tos[toindex];
-	if (top->selfpc == selfpc) {
-		/*
-		 *	arc at front of chain; usual case.
-		 */
-		top->count++;
-		goto done;
-	}
-	/*
-	 *	have to go looking down chain for it.
-	 *	top points to what we are looking at,
-	 *	prevtop points to previous top.
-	 *	we know it is not at the head of the chain.
-	 */
-	for (; /* goto done */; ) {
-		if (top->link == 0) {
-			/*
-			 *	top is end of the chain and none of the chain
-			 *	had top->selfpc == selfpc.
-			 *	so we allocate a new tostruct
-			 *	and link it to the head of the chain.
-			 */
-			toindex = ++tos[0].link;
-			if (toindex >= tolimit) {
-				goto overflow;
-			}
-			top = &tos[toindex];
-			top->selfpc = selfpc;
-			top->count = 1;
-			top->link = *frompcindex;
-			*frompcindex = toindex;
-			goto done;
-		}
-		/*
-		 *	otherwise, check the next arc on the chain.
-		 */
-		prevtop = top;
-		top = &tos[top->link];
-		if (top->selfpc == selfpc) {
-			/*
-			 *	there it is.
-			 *	increment its count
-			 *	move it to the head of the chain.
-			 */
-			top->count++;
-			toindex = prevtop->link;
-			prevtop->link = top->link;
-			top->link = *frompcindex;
-			*frompcindex = toindex;
-			goto done;
-		}
-
-	}
-done:
-	profiling--;
-	/* and fall through */
-out:
-	return;		/* normal return restores saved registers */
-
-overflow:
-	profiling++; /* halt further profiling */
-#   define	TOLIMIT	"mcount: tos overflow\n"
-	write(2, TOLIMIT, sizeof(TOLIMIT));
-	goto out;
-}
-
-/*
- * Control profiling
- *	profiling is what mcount checks to see if
- *	all the data structures are ready.
- */
-static void moncontrol(mode)
-    int mode;
-{
-    if (mode) {
-	/* start */
-	profil((unsigned short *)(sbuf + sizeof(struct phdr)),
-	       ssiz - sizeof(struct phdr),
-	       (int)s_lowpc, s_scale);
-	profiling = 0;
-    } else {
-	/* stop */
-	profil((unsigned short *)0, 0, 0, 0);
-	profiling = 3;
-    }
-}
diff --git a/gcc/config/sparc/hal.h b/gcc/config/sparc/hal.h
deleted file mode 100755
index 0222b81..0000000
--- a/gcc/config/sparc/hal.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Definitions of target machine for GNU compiler, for HAL 
-   SPARC running Solaris 2 HALOS
-   Copyright 1998 Free Software Foundation, Inc.
-   Contributed by Carol LePage (carolo@hal.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Need different command line for assembler */
-
-#undef ASM_SPEC
-#define ASM_SPEC \
-  "%{V} %{v:%{!V:-V}} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -e1 \
-   %{fpic:-K PIC} %{fPIC:-K PIC}"
-
-/* Need DWARF for debuggers.  */
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF_DEBUG
diff --git a/gcc/config/sparc/lb1spc.asm b/gcc/config/sparc/lb1spc.asm
deleted file mode 100755
index 831f33a..0000000
--- a/gcc/config/sparc/lb1spc.asm
+++ /dev/null
@@ -1,784 +0,0 @@
-/* This is an assembly language implementation of libgcc1.c for the sparc
-   processor.
-
-   These routines are derived from the Sparc Architecture Manual, version 8,
-   slightly edited to match the desired calling convention, and also to
-   optimize them for our purposes.  */
-
-#ifdef L_mulsi3
-.text
-	.align 4
-	.global .umul
-	.proc 4
-.umul:
-	or	%o0, %o1, %o4	! logical or of multiplier and multiplicand
-	mov	%o0, %y		! multiplier to Y register
-	andncc	%o4, 0xfff, %o5	! mask out lower 12 bits
-	be	mul_shortway	! can do it the short way
-	andcc	%g0, %g0, %o4	! zero the partial product and clear NV cc
-	!
-	! long multiply
-	!
-	mulscc	%o4, %o1, %o4	! first iteration of 33
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4	! 32nd iteration
-	mulscc	%o4, %g0, %o4	! last iteration only shifts
-	! the upper 32 bits of product are wrong, but we do not care
-	retl
-	rd	%y, %o0
-	!
-	! short multiply
-	!
-mul_shortway:
-	mulscc	%o4, %o1, %o4	! first iteration of 13
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4
-	mulscc	%o4, %o1, %o4	! 12th iteration
-	mulscc	%o4, %g0, %o4	! last iteration only shifts
-	rd	%y, %o5
-	sll	%o4, 12, %o4	! left shift partial product by 12 bits
-	srl	%o5, 20, %o5	! right shift partial product by 20 bits
-	retl
-	or	%o5, %o4, %o0	! merge for true product
-#endif
-
-#ifdef L_divsi3
-/*
- * Division and remainder, from Appendix E of the Sparc Version 8
- * Architecture Manual, with fixes from Gordon Irlam.
- */
-
-/*
- * Input: dividend and divisor in %o0 and %o1 respectively.
- *
- * m4 parameters:
- *  .div	name of function to generate
- *  div		div=div => %o0 / %o1; div=rem => %o0 % %o1
- *  true		true=true => signed; true=false => unsigned
- *
- * Algorithm parameters:
- *  N		how many bits per iteration we try to get (4)
- *  WORDSIZE	total number of bits (32)
- *
- * Derived constants:
- *  TOPBITS	number of bits in the top decade of a number
- *
- * Important variables:
- *  Q		the partial quotient under development (initially 0)
- *  R		the remainder so far, initially the dividend
- *  ITER	number of main division loop iterations required;
- *		equal to ceil(log2(quotient) / N).  Note that this
- *		is the log base (2^N) of the quotient.
- *  V		the current comparand, initially divisor*2^(ITER*N-1)
- *
- * Cost:
- *  Current estimate for non-large dividend is
- *	ceil(log2(quotient) / N) * (10 + 7N/2) + C
- *  A large dividend is one greater than 2^(31-TOPBITS) and takes a
- *  different path, as the upper bits of the quotient must be developed
- *  one bit at a time.
- */
-        .global .udiv
-        .align 4
-        .proc 4
-        .text
-.udiv:
-         b ready_to_divide
-         mov 0, %g3             ! result is always positive
-
-        .global .div
-        .align 4
-        .proc 4
-        .text
-.div:
-	! compute sign of result; if neither is negative, no problem
-	orcc	%o1, %o0, %g0	! either negative?
-	bge	ready_to_divide	! no, go do the divide
-	xor	%o1, %o0, %g3	! compute sign in any case
-	tst	%o1
-	bge	1f
-	tst	%o0
-	! %o1 is definitely negative; %o0 might also be negative
-	bge	ready_to_divide	! if %o0 not negative...
-	sub	%g0, %o1, %o1	! in any case, make %o1 nonneg
-1:	! %o0 is negative, %o1 is nonnegative
-	sub	%g0, %o0, %o0	! make %o0 nonnegative
-
-
-ready_to_divide:
-
-	! Ready to divide.  Compute size of quotient; scale comparand.
-	orcc	%o1, %g0, %o5
-	bne	1f
-	mov	%o0, %o3
-
-	! Divide by zero trap.  If it returns, return 0 (about as
-	! wrong as possible, but that is what SunOS does...).
-	ta	0x2    		! ST_DIV0
-	retl
-	clr	%o0
-
-1:
-	cmp	%o3, %o5		! if %o1 exceeds %o0, done
-	blu	got_result		! (and algorithm fails otherwise)
-	clr	%o2
-	sethi	%hi(1 << (32 - 4 - 1)), %g1
-	cmp	%o3, %g1
-	blu	not_really_big
-	clr	%o4
-
-	! Here the dividend is >= 2**(31-N) or so.  We must be careful here,
-	! as our usual N-at-a-shot divide step will cause overflow and havoc.
-	! The number of bits in the result here is N*ITER+SC, where SC <= N.
-	! Compute ITER in an unorthodox manner: know we need to shift V into
-	! the top decade: so do not even bother to compare to R.
-	1:
-		cmp	%o5, %g1
-		bgeu	3f
-		mov	1, %g2
-		sll	%o5, 4, %o5
-		b	1b
-		add	%o4, 1, %o4
-
-	! Now compute %g2.
-	2:	addcc	%o5, %o5, %o5
-		bcc	not_too_big
-		add	%g2, 1, %g2
-
-		! We get here if the %o1 overflowed while shifting.
-		! This means that %o3 has the high-order bit set.
-		! Restore %o5 and subtract from %o3.
-		sll	%g1, 4, %g1	! high order bit
-		srl	%o5, 1, %o5	! rest of %o5
-		add	%o5, %g1, %o5
-		b	do_single_div
-		sub	%g2, 1, %g2
-
-	not_too_big:
-	3:	cmp	%o5, %o3
-		blu	2b
-		nop
-		be	do_single_div
-		nop
-	/* NB: these are commented out in the V8-Sparc manual as well */
-	/* (I do not understand this) */
-	! %o5 > %o3: went too far: back up 1 step
-	!	srl	%o5, 1, %o5
-	!	dec	%g2
-	! do single-bit divide steps
-	!
-	! We have to be careful here.  We know that %o3 >= %o5, so we can do the
-	! first divide step without thinking.  BUT, the others are conditional,
-	! and are only done if %o3 >= 0.  Because both %o3 and %o5 may have the high-
-	! order bit set in the first step, just falling into the regular
-	! division loop will mess up the first time around.
-	! So we unroll slightly...
-	do_single_div:
-		subcc	%g2, 1, %g2
-		bl	end_regular_divide
-		nop
-		sub	%o3, %o5, %o3
-		mov	1, %o2
-		b	end_single_divloop
-		nop
-	single_divloop:
-		sll	%o2, 1, %o2
-		bl	1f
-		srl	%o5, 1, %o5
-		! %o3 >= 0
-		sub	%o3, %o5, %o3
-		b	2f
-		add	%o2, 1, %o2
-	1:	! %o3 < 0
-		add	%o3, %o5, %o3
-		sub	%o2, 1, %o2
-	2:
-	end_single_divloop:
-		subcc	%g2, 1, %g2
-		bge	single_divloop
-		tst	%o3
-		b,a	end_regular_divide
-
-not_really_big:
-1:
-	sll	%o5, 4, %o5
-	cmp	%o5, %o3
-	bleu	1b
-	addcc	%o4, 1, %o4
-	be	got_result
-	sub	%o4, 1, %o4
-
-	tst	%o3	! set up for initial iteration
-divloop:
-	sll	%o2, 4, %o2
-	! depth 1, accumulated bits 0
-	bl	L1.16
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 2, accumulated bits 1
-	bl	L2.17
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 3, accumulated bits 3
-	bl	L3.19
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 4, accumulated bits 7
-	bl	L4.23
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (7*2+1), %o2
-	
-L4.23:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (7*2-1), %o2
-	
-	
-L3.19:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 4, accumulated bits 5
-	bl	L4.21
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (5*2+1), %o2
-	
-L4.21:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (5*2-1), %o2
-	
-L2.17:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 3, accumulated bits 1
-	bl	L3.17
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 4, accumulated bits 3
-	bl	L4.19
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (3*2+1), %o2
-	
-L4.19:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (3*2-1), %o2
-
-L3.17:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 4, accumulated bits 1
-	bl	L4.17
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (1*2+1), %o2
-
-L4.17:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (1*2-1), %o2
-	
-L1.16:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 2, accumulated bits -1
-	bl	L2.15
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 3, accumulated bits -1
-	bl	L3.15
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 4, accumulated bits -1
-	bl	L4.15
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-1*2+1), %o2
-	
-L4.15:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-1*2-1), %o2
-	
-L3.15:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 4, accumulated bits -3
-	bl	L4.13
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-3*2+1), %o2
-	
-L4.13:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-3*2-1), %o2
-	
-L2.15:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 3, accumulated bits -3
-	bl	L3.13
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 4, accumulated bits -5
-	bl	L4.11
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-5*2+1), %o2
-	
-L4.11:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-5*2-1), %o2
-	
-L3.13:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 4, accumulated bits -7
-	bl	L4.9
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-7*2+1), %o2
-
-L4.9:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-7*2-1), %o2
-	
-	9:
-end_regular_divide:
-	subcc	%o4, 1, %o4
-	bge	divloop
-	tst	%o3
-	bl,a	got_result
-	! non-restoring fixup here (one instruction only!)
-	sub	%o2, 1, %o2
-
-
-got_result:
-	! check to see if answer should be < 0
-	tst	%g3
-	bl,a	1f
-	sub %g0, %o2, %o2
-1:
-	retl
-	mov %o2, %o0
-#endif
-
-#ifdef L_modsi3
-/* This implementation was taken from glibc:
- *
- * Input: dividend and divisor in %o0 and %o1 respectively.
- *
- * Algorithm parameters:
- *  N		how many bits per iteration we try to get (4)
- *  WORDSIZE	total number of bits (32)
- *
- * Derived constants:
- *  TOPBITS	number of bits in the top decade of a number
- *
- * Important variables:
- *  Q		the partial quotient under development (initially 0)
- *  R		the remainder so far, initially the dividend
- *  ITER	number of main division loop iterations required;
- *		equal to ceil(log2(quotient) / N).  Note that this
- *		is the log base (2^N) of the quotient.
- *  V		the current comparand, initially divisor*2^(ITER*N-1)
- *
- * Cost:
- *  Current estimate for non-large dividend is
- *	ceil(log2(quotient) / N) * (10 + 7N/2) + C
- *  A large dividend is one greater than 2^(31-TOPBITS) and takes a
- *  different path, as the upper bits of the quotient must be developed
- *  one bit at a time.
- */
-.text
-	.align 4
-	.global	.urem
-	.proc 4
-.urem:
-	b	divide
-	mov	0, %g3		! result always positive
-
-        .align 4
-	.global .rem
-	.proc 4
-.rem:
-	! compute sign of result; if neither is negative, no problem
-	orcc	%o1, %o0, %g0	! either negative?
-	bge	2f			! no, go do the divide
-	mov	%o0, %g3		! sign of remainder matches %o0
-	tst	%o1
-	bge	1f
-	tst	%o0
-	! %o1 is definitely negative; %o0 might also be negative
-	bge	2f			! if %o0 not negative...
-	sub	%g0, %o1, %o1	! in any case, make %o1 nonneg
-1:	! %o0 is negative, %o1 is nonnegative
-	sub	%g0, %o0, %o0	! make %o0 nonnegative
-2:
-
-	! Ready to divide.  Compute size of quotient; scale comparand.
-divide:
-	orcc	%o1, %g0, %o5
-	bne	1f
-	mov	%o0, %o3
-
-		! Divide by zero trap.  If it returns, return 0 (about as
-		! wrong as possible, but that is what SunOS does...).
-		ta	0x2   !ST_DIV0
-		retl
-		clr	%o0
-
-1:
-	cmp	%o3, %o5		! if %o1 exceeds %o0, done
-	blu	got_result		! (and algorithm fails otherwise)
-	clr	%o2
-	sethi	%hi(1 << (32 - 4 - 1)), %g1
-	cmp	%o3, %g1
-	blu	not_really_big
-	clr	%o4
-
-	! Here the dividend is >= 2**(31-N) or so.  We must be careful here,
-	! as our usual N-at-a-shot divide step will cause overflow and havoc.
-	! The number of bits in the result here is N*ITER+SC, where SC <= N.
-	! Compute ITER in an unorthodox manner: know we need to shift V into
-	! the top decade: so do not even bother to compare to R.
-	1:
-		cmp	%o5, %g1
-		bgeu	3f
-		mov	1, %g2
-		sll	%o5, 4, %o5
-		b	1b
-		add	%o4, 1, %o4
-
-	! Now compute %g2.
-	2:	addcc	%o5, %o5, %o5
-		bcc	not_too_big
-		add	%g2, 1, %g2
-
-		! We get here if the %o1 overflowed while shifting.
-		! This means that %o3 has the high-order bit set.
-		! Restore %o5 and subtract from %o3.
-		sll	%g1, 4, %g1	! high order bit
-		srl	%o5, 1, %o5		! rest of %o5
-		add	%o5, %g1, %o5
-		b	do_single_div
-		sub	%g2, 1, %g2
-
-	not_too_big:
-	3:	cmp	%o5, %o3
-		blu	2b
-		nop
-		be	do_single_div
-		nop
-	/* NB: these are commented out in the V8-Sparc manual as well */
-	/* (I do not understand this) */
-	! %o5 > %o3: went too far: back up 1 step
-	!	srl	%o5, 1, %o5
-	!	dec	%g2
-	! do single-bit divide steps
-	!
-	! We have to be careful here.  We know that %o3 >= %o5, so we can do the
-	! first divide step without thinking.  BUT, the others are conditional,
-	! and are only done if %o3 >= 0.  Because both %o3 and %o5 may have the high-
-	! order bit set in the first step, just falling into the regular
-	! division loop will mess up the first time around.
-	! So we unroll slightly...
-	do_single_div:
-		subcc	%g2, 1, %g2
-		bl	end_regular_divide
-		nop
-		sub	%o3, %o5, %o3
-		mov	1, %o2
-		b	end_single_divloop
-		nop
-	single_divloop:
-		sll	%o2, 1, %o2
-		bl	1f
-		srl	%o5, 1, %o5
-		! %o3 >= 0
-		sub	%o3, %o5, %o3
-		b	2f
-		add	%o2, 1, %o2
-	1:	! %o3 < 0
-		add	%o3, %o5, %o3
-		sub	%o2, 1, %o2
-	2:
-	end_single_divloop:
-		subcc	%g2, 1, %g2
-		bge	single_divloop
-		tst	%o3
-		b,a	end_regular_divide
-
-not_really_big:
-1:
-	sll	%o5, 4, %o5
-	cmp	%o5, %o3
-	bleu	1b
-	addcc	%o4, 1, %o4
-	be	got_result
-	sub	%o4, 1, %o4
-
-	tst	%o3	! set up for initial iteration
-divloop:
-	sll	%o2, 4, %o2
-		! depth 1, accumulated bits 0
-	bl	L1.16
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 2, accumulated bits 1
-	bl	L2.17
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 3, accumulated bits 3
-	bl	L3.19
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 4, accumulated bits 7
-	bl	L4.23
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (7*2+1), %o2
-L4.23:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (7*2-1), %o2
-	
-L3.19:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 4, accumulated bits 5
-	bl	L4.21
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (5*2+1), %o2
-	
-L4.21:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (5*2-1), %o2
-	
-L2.17:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 3, accumulated bits 1
-	bl	L3.17
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 4, accumulated bits 3
-	bl	L4.19
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (3*2+1), %o2
-	
-L4.19:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (3*2-1), %o2
-	
-L3.17:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 4, accumulated bits 1
-	bl	L4.17
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (1*2+1), %o2
-	
-L4.17:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (1*2-1), %o2
-	
-L1.16:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 2, accumulated bits -1
-	bl	L2.15
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 3, accumulated bits -1
-	bl	L3.15
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 4, accumulated bits -1
-	bl	L4.15
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-1*2+1), %o2
-	
-L4.15:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-1*2-1), %o2
-	
-L3.15:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 4, accumulated bits -3
-	bl	L4.13
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-3*2+1), %o2
-	
-L4.13:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-3*2-1), %o2
-	
-L2.15:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 3, accumulated bits -3
-	bl	L3.13
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	! depth 4, accumulated bits -5
-	bl	L4.11
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-5*2+1), %o2
-	
-L4.11:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-5*2-1), %o2
-	
-L3.13:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	! depth 4, accumulated bits -7
-	bl	L4.9
-	srl	%o5,1,%o5
-	! remainder is positive
-	subcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-7*2+1), %o2
-	
-L4.9:
-	! remainder is negative
-	addcc	%o3,%o5,%o3
-	b	9f
-	add	%o2, (-7*2-1), %o2
-	
-	9:
-end_regular_divide:
-	subcc	%o4, 1, %o4
-	bge	divloop
-	tst	%o3
-	bl,a	got_result
-	! non-restoring fixup here (one instruction only!)
-	add	%o3, %o1, %o3
-
-got_result:
-	! check to see if answer should be < 0
-	tst	%g3
-	bl,a	1f
-	sub %g0, %o3, %o3
-1:
-	retl
-	mov %o3, %o0
-
-#endif
-
diff --git a/gcc/config/sparc/lb1spl.asm b/gcc/config/sparc/lb1spl.asm
deleted file mode 100755
index 4c8bc30..0000000
--- a/gcc/config/sparc/lb1spl.asm
+++ /dev/null
@@ -1,246 +0,0 @@
-/* This is an assembly language implementation of libgcc1.c for the sparclite
-   processor.
-
-   These routines are all from the Sparclite User's Guide, slightly edited
-   to match the desired calling convention, and also to optimize them.  */
-
-#ifdef L_udivsi3
-.text
-	.align 4
-	.global .udiv
-	.proc	04
-.udiv:
-	wr	%g0,%g0,%y	! Not a delayed write for sparclite
-	tst	%g0
-	divscc	%o0,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	retl
-	divscc	%g1,%o1,%o0
-#endif
-
-#ifdef L_umodsi3
-.text
-	.align 4
-	.global .urem
-	.proc	04
-.urem:
-	wr	%g0,%g0,%y	! Not a delayed write for sparclite
-	tst	%g0
-	divscc	%o0,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	divscc	%g1,%o1,%g1
-	bl 1f
-	rd	%y,%o0
-	retl
-	nop
-1:	retl
-	add	%o0,%o1,%o0
-#endif
-
-#ifdef L_divsi3
-.text
-	.align 4
-	.global .div
-	.proc	04
-! ??? This routine could be made faster if was optimized, and if it was
-! rewritten to only calculate the quotient.
-.div:
-	wr	%g0,%g0,%y	! Not a delayed write for sparclite
-	mov	%o1,%o4
-	tst	%o1
-	bl,a	1f
-	sub	%g0,%o4,%o4
-1:	tst	%o0
-	bl,a	2f
-	mov	-1,%y
-2:	divscc	%o0,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	be	6f
-	mov	%y,%o3
-	bg	4f
-	addcc	%o3,%o4,%g0
-	be,a	6f
-	mov	%g0,%o3
-	tst	%o0
-	bl	5f
-	tst	%g1
-	ba	5f
-	add	%o3,%o4,%o3
-4:	subcc	%o3,%o4,%g0
-	be,a	6f
-	mov	%g0,%o3
-	tst	%o0
-	bge	5f
-	tst	%g1
-	sub	%o3,%o4,%o3
-5:	bl,a	6f
-	add	%g1,1,%g1
-6:	tst	%o1
-	bl,a	7f
-	sub	%g0,%g1,%g1
-7:	retl
-	mov	%g1,%o0		! Quotient is in %g1.
-#endif
-
-#ifdef L_modsi3
-.text
-	.align 4
-	.global .rem
-	.proc	04
-! ??? This routine could be made faster if was optimized, and if it was
-! rewritten to only calculate the remainder.
-.rem:
-	wr	%g0,%g0,%y	! Not a delayed write for sparclite
-	mov	%o1,%o4
-	tst	%o1
-	bl,a	1f
-	sub	%g0,%o4,%o4
-1:	tst	%o0
-	bl,a	2f
-	mov	-1,%y
-2:	divscc	%o0,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	divscc	%g1,%o4,%g1
-	be	6f
-	mov	%y,%o3
-	bg	4f
-	addcc	%o3,%o4,%g0
-	be,a	6f
-	mov	%g0,%o3
-	tst	%o0
-	bl	5f
-	tst	%g1
-	ba	5f
-	add	%o3,%o4,%o3
-4:	subcc	%o3,%o4,%g0
-	be,a	6f
-	mov	%g0,%o3
-	tst	%o0
-	bge	5f
-	tst	%g1
-	sub	%o3,%o4,%o3
-5:	bl,a	6f
-	add	%g1,1,%g1
-6:	tst	%o1
-	bl,a	7f
-	sub	%g0,%g1,%g1
-7:	retl
-	mov	%o3,%o0		! Remainder is in %o3.
-#endif
diff --git a/gcc/config/sparc/linux-aout.h b/gcc/config/sparc/linux-aout.h
deleted file mode 100755
index 76d7653..0000000
--- a/gcc/config/sparc/linux-aout.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Definitions for SPARC running Linux-based GNU systems with a.out.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Eddie C. Dost (ecd@skynet.be)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <aoutos.h>
-#include <sparc/sparc.h>
-
-/* Don't assume anything about the header files. */
-#define NO_IMPLICIT_EXTERN_C
-
-#undef HAVE_ATEXIT
-#define HAVE_ATEXIT
-
-/* GNU/Linux uses ctype from glibc.a. I am not sure how complete it is.
-   For now, we play safe. It may change later. */
-
-#if 0
-#undef MULTIBYTE_CHARS
-#define MULTIBYTE_CHARS 1
-#endif
-
-/* We need that too. */
-#define HANDLE_SYSV_PRAGMA
-
-#undef MD_EXEC_PREFIX
-#undef MD_STARTFILE_PREFIX
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)                                            \
-  do {                                                                  \
-        output_file_directive (FILE, main_input_filename);              \
-        fprintf (FILE, "\t.version\t\"01.01\"\n");                      \
-  } while (0)
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC  "%{pg:gcrt0.o%s} %{!pg:%{p:gcrt0.o%s} %{!p:crt0.o%s}} %{static:-static}"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (sparc GNU/Linux with a.out)");
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix)"
-
-#undef CPP_SUBTARGET_SPEC
-#define CPP_SUBTARGET_SPEC \
-"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}"
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler,
-   and we want to retain compatibility with older gcc versions.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-#undef LIB_SPEC
-
-#if 1
-/* We no longer link with libc_p.a or libg.a by default. If you
-   want to profile or debug the GNU/Linux C library, please add
-   -lc_p or -ggdb to LDFLAGS at the link time, respectively.  */
-#define LIB_SPEC \
-"%{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}"
-#else    
-#define LIB_SPEC \
-"%{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \
- %{!p:%{!pg:%{!g*:-lc} %{g*:-lg -static}}}" 
-#endif
-
-#undef LINK_SPEC
-#define LINK_SPEC	"-m sparclinux"
-
-/* The sun bundled assembler doesn't accept -Yd, (and neither does gas).
-   It's safe to pass -s always, even if -g is not used. */
-#undef ASM_SPEC
-#define ASM_SPEC \
-  "%{V} %{v:%{!V:-V}} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s %{fpic:-K PIC} %{fPIC:-K PIC}"
-
-#if 0
-/* Define for support of TFmode long double and REAL_ARITHMETIC.
-   Sparc ABI says that long double is 4 words. GNU/Linux does not support
-   long double yet.  */
-#define LONG_DOUBLE_TYPE_SIZE 128
-#endif
-
-/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
-   traps available which can get and set the condition codes
-   reliably.  */
-#undef MACHINE_STATE_SAVE
-#define MACHINE_STATE_SAVE(ID)				\
-  unsigned long int ms_flags, ms_saveret;		\
-  asm volatile("ta	0x20\n\t"			\
-	       "mov	%%g1, %0\n\t"			\
-	       "mov	%%g2, %1\n\t"			\
-	       : "=r" (ms_flags), "=r" (ms_saveret));
-
-#undef MACHINE_STATE_RESTORE
-#define MACHINE_STATE_RESTORE(ID)			\
-  asm volatile("mov	%0, %%g1\n\t"			\
-	       "mov	%1, %%g2\n\t"			\
-	       "ta	0x21\n\t"			\
-	       : /* no outputs */			\
-	       : "r" (ms_flags), "r" (ms_saveret));
diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h
deleted file mode 100755
index d967b01..0000000
--- a/gcc/config/sparc/linux.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/* Definitions for SPARC running Linux-based GNU systems with ELF.
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Eddie C. Dost (ecd@skynet.be)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define LINUX_DEFAULT_ELF
-
-/* Don't assume anything about the header files. */
-#define NO_IMPLICIT_EXTERN_C
-
-#undef HAVE_ATEXIT
-#define HAVE_ATEXIT
-
-/* GNU/Linux uses ctype from glibc.a. I am not sure how complete it is.
-   For now, we play safe. It may change later. */
-
-#if 0
-#undef MULTIBYTE_CHARS
-#define MULTIBYTE_CHARS 1
-#endif
-
-#ifndef USE_GNULIBC_1
-#undef DEFAULT_VTABLE_THUNKS
-#define DEFAULT_VTABLE_THUNKS 1
-#endif
-
-/* Use stabs instead of DWARF debug format.  */
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#include <sparc/sysv4.h>
-
-#undef MD_EXEC_PREFIX
-#undef MD_STARTFILE_PREFIX
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)                                            \
-  do {                                                                  \
-        output_file_directive (FILE, main_input_filename);              \
-        fprintf (FILE, "\t.version\t\"01.01\"\n");                      \
-  } while (0)
-
-/* Provide a STARTFILE_SPEC appropriate for GNU/Linux.  Here we add
-   the GNU/Linux magical crtbegin.o file (see crtstuff.c) which
-   provides part of the support for getting C++ file-scope static
-   object constructed before entering `main'. */
-   
-#undef  STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{!shared: \
-     %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\
-   crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}"
-
-/* Provide a ENDFILE_SPEC appropriate for GNU/Linux.  Here we tack on
-   the GNU/Linux magical crtend.o file (see crtstuff.c) which
-   provides part of the support for getting C++ file-scope static
-   object constructed before entering `main', followed by a normal
-   GNU/Linux "finalizer" file, `crtn.o'.  */
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC \
-  "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s"
-
-/* This is for -profile to use -lc_p instead of -lc. */
-#undef	CC1_SPEC
-#define	CC1_SPEC "%{profile:-p} \
-%{sun4:} %{target:} \
-%{mcypress:-mcpu=cypress} \
-%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
-%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
-"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (sparc GNU/Linux with ELF)");
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
- 
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-  
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-   
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-    
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D__ELF__ -Dunix -D__sparc__ -Dlinux -Asystem(unix) -Asystem(posix)"
-
-#undef CPP_SUBTARGET_SPEC
-#ifdef USE_GNULIBC_1
-#define CPP_SUBTARGET_SPEC \
-"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}"
-#else
-#define CPP_SUBTARGET_SPEC \
-"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
-#endif
-
-#undef LIB_SPEC
-/* We no longer link with libc_p.a or libg.a by default. If you
-   want to profile or debug the GNU/Linux C library, please add
-   -lc_p or -ggdb to LDFLAGS at the link time, respectively.  */
-#if 1
-#ifdef USE_GNULIBC_1
-#define LIB_SPEC \
-  "%{!shared: %{p:-lgmon} %{pg:-lgmon} %{profile:-lgmon -lc_p} \
-     %{!profile:%{!ggdb:-lc} %{ggdb:-lg}}}"
-#else
-#define LIB_SPEC \
-  "%{shared: -lc} \
-   %{!shared: %{mieee-fp:-lieee} %{pthread:-lpthread} \
-     %{profile:-lc_p} %{!profile: -lc}}"
-#endif
-#else
-#define LIB_SPEC \
-  "%{!shared: \
-     %{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \
-       %{!p:%{!pg:%{!g*:-lc} %{g*:-lg}}}}"
-#endif
-
-/* Provide a LINK_SPEC appropriate for GNU/Linux.  Here we provide support
-   for the special GCC options -static and -shared, which allow us to
-   link things in one of these three modes by applying the appropriate
-   combinations of options at link-time. We like to support here for
-   as many of the other GNU linker options as possible. But I don't
-   have the time to search for those flags. I am sure how to add
-   support for -soname shared_object_name. H.J.
-
-   I took out %{v:%{!V:-V}}. It is too much :-(. They can use
-   -Wl,-V.
-
-   When the -shared link option is used a final link is not being
-   done.  */
-
-/* If ELF is the default format, we should not use /lib/elf. */
-
-#undef  LINK_SPEC
-#ifdef USE_GNULIBC_1
-#ifndef LINUX_DEFAULT_ELF
-#define LINK_SPEC "-m elf32_sparc -Y P,/usr/lib %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-        %{rdynamic:-export-dynamic} \
-        %{!dynamic-linker:-dynamic-linker /lib/elf/ld-linux.so.1} \
-        %{!rpath:-rpath /lib/elf/}} %{static:-static}}}"
-#else
-#define LINK_SPEC "-m elf32_sparc -Y P,/usr/lib %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-        %{rdynamic:-export-dynamic} \
-        %{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.1}} \
-        %{static:-static}}}"
-#endif
-#else
-#define LINK_SPEC "-m elf32_sparc -Y P,/usr/lib %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-        %{rdynamic:-export-dynamic} \
-        %{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.2}} \
-        %{static:-static}}}"
-#endif
-
-/* The sun bundled assembler doesn't accept -Yd, (and neither does gas).
-   It's safe to pass -s always, even if -g is not used. */
-#undef ASM_SPEC
-#define ASM_SPEC \
-  "%{V} %{v:%{!V:-V}} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s %{fpic:-K PIC} %{fPIC:-K PIC}"
-
-/* Same as sparc.h */
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* We use stabs-in-elf for debugging, because that is what the native
-   toolchain uses.  XXX */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fputs ("\t.local\t", (FILE));		\
-  assemble_name ((FILE), (NAME));					\
-  putc ('\n', (FILE));							\
-  ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);			\
-} while (0)
-
-#undef COMMON_ASM_OP
-#define COMMON_ASM_OP "\t.common"
-
-/* This is how to output a definition of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef  ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".L%s%d:\n", PREFIX, NUM)
-
-/* This is how to output a reference to an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef  ASM_OUTPUT_INTERNAL_LABELREF
-#define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".L%s%d", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#undef  ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*.L%s%d", PREFIX, NUM)
-
-
-#if 0
-/* Define for support of TFmode long double and REAL_ARITHMETIC.
-   Sparc ABI says that long double is 4 words. GNU/Linux does not support
-   long double yet.  */
-#define LONG_DOUBLE_TYPE_SIZE 128
-#endif
-
-/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
-   traps available which can get and set the condition codes
-   reliably.  */
-#undef MACHINE_STATE_SAVE
-#define MACHINE_STATE_SAVE(ID)				\
-  unsigned long int ms_flags, ms_saveret;		\
-  asm volatile("ta	0x20\n\t"			\
-	       "mov	%%g1, %0\n\t"			\
-	       "mov	%%g2, %1\n\t"			\
-	       : "=r" (ms_flags), "=r" (ms_saveret));
-
-#undef MACHINE_STATE_RESTORE
-#define MACHINE_STATE_RESTORE(ID)			\
-  asm volatile("mov	%0, %%g1\n\t"			\
-	       "mov	%1, %%g2\n\t"			\
-	       "ta	0x21\n\t"			\
-	       : /* no outputs */			\
-	       : "r" (ms_flags), "r" (ms_saveret));
diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h
deleted file mode 100755
index 705b5ca..0000000
--- a/gcc/config/sparc/linux64.h
+++ /dev/null
@@ -1,366 +0,0 @@
-/* Definitions for 64-bit SPARC running Linux-based GNU systems with ELF.
-   Copyright 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by David S. Miller (davem@caip.rutgers.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define SPARC_BI_ARCH
-
-#define LINUX_DEFAULT_ELF
-
-/* Don't assume anything about the header files. */
-#define NO_IMPLICIT_EXTERN_C
-
-#undef HAVE_ATEXIT
-#define HAVE_ATEXIT
-
-#include <sparc/sysv4.h>
-
-#undef MD_EXEC_PREFIX
-#undef MD_STARTFILE_PREFIX
-
-#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
-/* A 64 bit v9 compiler with stack-bias,
-   in a Medium/Low code model environment.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT \
-  (MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
-   + MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
-#endif
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)                                            \
-  do {                                                                  \
-        output_file_directive (FILE, main_input_filename);              \
-        fprintf (FILE, "\t.version\t\"01.01\"\n");                      \
-  } while (0)
-  
-#undef ASM_CPU_DEFAULT_SPEC
-#define ASM_CPU_DEFAULT_SPEC "-Av9a"
-
-/* Provide a STARTFILE_SPEC appropriate for GNU/Linux.  Here we add
-   the GNU/Linux magical crtbegin.o file (see crtstuff.c) which
-   provides part of the support for getting C++ file-scope static
-   object constructed before entering `main'. */
-   
-#undef  STARTFILE_SPEC
-
-#define STARTFILE_SPEC32 \
-  "%{!shared: \
-     %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\
-   crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}"
-
-#define STARTFILE_SPEC64 \
-  "%{!shared: \
-     %{pg:/usr/lib64/gcrt1.o%s} %{!pg:%{p:/usr/lib64/gcrt1.o%s} %{!p:/usr/lib64/crt1.o%s}}}\
-   /usr/lib64/crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}"
-   
-#ifdef SPARC_BI_ARCH
-
-#if DEFAULT_ARCH32_P
-#define STARTFILE_SPEC "\
-%{m32:" STARTFILE_SPEC32 "} \
-%{m64:" STARTFILE_SPEC64 "} \
-%{!m32:%{!m64:" STARTFILE_SPEC32 "}}"
-#else
-#define STARTFILE_SPEC "\
-%{m32:" STARTFILE_SPEC32 "} \
-%{m64:" STARTFILE_SPEC64 "} \
-%{!m32:%{!m64:" STARTFILE_SPEC64 "}}"
-#endif
-
-#else
-
-#define STARTFILE_SPEC STARTFILE_SPEC64
-
-#endif
-
-/* Provide a ENDFILE_SPEC appropriate for GNU/Linux.  Here we tack on
-   the GNU/Linux magical crtend.o file (see crtstuff.c) which
-   provides part of the support for getting C++ file-scope static
-   object constructed before entering `main', followed by a normal
-   GNU/Linux "finalizer" file, `crtn.o'.  */
-
-#undef  ENDFILE_SPEC
-
-#define ENDFILE_SPEC32 \
-  "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s"
-
-#define ENDFILE_SPEC64 \
-  "%{!shared:crtend.o%s} %{shared:crtendS.o%s} /usr/lib64/crtn.o%s"
-  
-#ifdef SPARC_BI_ARCH
-
-#if DEFAULT_ARCH32_P
-#define ENDFILE_SPEC "\
-%{m32:" ENDFILE_SPEC32 "} \
-%{m64:" ENDFILE_SPEC64 "} \
-%{!m32:%{!m64:" ENDFILE_SPEC32 "}}"
-#else
-#define ENDFILE_SPEC "\
-%{m32:" ENDFILE_SPEC32 "} \
-%{m64:" ENDFILE_SPEC64 "} \
-%{!m32:%{!m64:" ENDFILE_SPEC64 "}}"
-#endif
-
-#else
-
-#define ENDFILE_SPEC ENDFILE_SPEC64
-
-#endif
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (sparc64 GNU/Linux with ELF)");
-
-/* The default code model.  */
-#undef SPARC_DEFAULT_CMODEL
-#define SPARC_DEFAULT_CMODEL CM_MEDLOW
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-   
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 128
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-D__ELF__ -Dunix -D_LONGLONG -D__sparc__ -Dlinux -Asystem(unix) -Asystem(posix)"
-
-#undef CPP_SUBTARGET_SPEC
-#define CPP_SUBTARGET_SPEC "\
-%{fPIC:-D__PIC__ -D__pic__} \
-%{fpic:-D__PIC__ -D__pic__} \
-%{posix:-D_POSIX_SOURCE} \
-%{pthread:-D_REENTRANT} \
-"
-
-#undef LIB_SPEC
-#define LIB_SPEC \
-  "%{shared: -lc} \
-   %{!shared: %{mieee-fp:-lieee} %{pthread:-lpthread} \
-     %{profile:-lc_p} %{!profile: -lc}}"
-
-/* Provide a LINK_SPEC appropriate for GNU/Linux.  Here we provide support
-   for the special GCC options -static and -shared, which allow us to
-   link things in one of these three modes by applying the appropriate
-   combinations of options at link-time. We like to support here for
-   as many of the other GNU linker options as possible. But I don't
-   have the time to search for those flags. I am sure how to add
-   support for -soname shared_object_name. H.J.
-
-   I took out %{v:%{!V:-V}}. It is too much :-(. They can use
-   -Wl,-V.
-
-   When the -shared link option is used a final link is not being
-   done.  */
-
-/* If ELF is the default format, we should not use /lib/elf. */
-
-#ifdef SPARC_BI_ARCH
-
-#undef SUBTARGET_EXTRA_SPECS
-#define SUBTARGET_EXTRA_SPECS \
-  { "link_arch32",       LINK_ARCH32_SPEC },              \
-  { "link_arch64",       LINK_ARCH64_SPEC },              \
-  { "link_arch_default", LINK_ARCH_DEFAULT_SPEC },	  \
-  { "link_arch",	 LINK_ARCH_SPEC },
-    
-#define LINK_ARCH32_SPEC "-m elf32_sparc -Y P,/usr/lib %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-        %{rdynamic:-export-dynamic} \
-        %{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.2}} \
-        %{static:-static}}} \
-"
-
-#define LINK_ARCH64_SPEC "-m elf64_sparc -Y P,/usr/lib64 %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-        %{rdynamic:-export-dynamic} \
-        %{!dynamic-linker:-dynamic-linker /lib64/ld-linux.so.2}} \
-        %{static:-static}}} \
-"
-
-#define LINK_ARCH_SPEC "\
-%{m32:%(link_arch32)} \
-%{m64:%(link_arch64)} \
-%{!m32:%{!m64:%(link_arch_default)}} \
-"
-
-#define LINK_ARCH_DEFAULT_SPEC \
-(DEFAULT_ARCH32_P ? LINK_ARCH32_SPEC : LINK_ARCH64_SPEC)
-
-#undef  LINK_SPEC
-#define LINK_SPEC "\
-%(link_arch) \
-%{mlittle-endian:-EL} \
-"
-
-#undef	CC1_SPEC
-#if DEFAULT_ARCH32_P
-#define CC1_SPEC "\
-%{sun4:} %{target:} \
-%{mcypress:-mcpu=cypress} \
-%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
-%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
-%{m64:-mptr64 -mcpu=ultrasparc -mstack-bias} \
-"
-#else
-#define CC1_SPEC "\
-%{sun4:} %{target:} \
-%{mcypress:-mcpu=cypress} \
-%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
-%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
-%{m32:-mptr32 -mcpu=cypress -mno-stack-bias} \
-"
-#endif
-
-#if DEFAULT_ARCH32_P
-#define MULTILIB_DEFAULTS { "m32" }
-#else
-#define MULTILIB_DEFAULTS { "m64" }
-#endif
-
-#else /* !SPARC_BI_ARCH */
-
-#undef LINK_SPEC
-#define LINK_ARCH_SPEC "-m elf64_sparc -Y P,/usr/lib64 %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-        %{rdynamic:-export-dynamic} \
-        %{!dynamic-linker:-dynamic-linker /lib64/ld-linux.so.2}} \
-        %{static:-static}}} \
-%{mlittle-endian:-EL} \
-"
-
-#endif /* !SPARC_BI_ARCH */
-
-/* The sun bundled assembler doesn't accept -Yd, (and neither does gas).
-   It's safe to pass -s always, even if -g is not used. */
-#undef ASM_SPEC
-#define ASM_SPEC "\
-%{V} \
-%{v:%{!V:-V}} \
-%{!Qn:-Qy} \
-%{n} \
-%{T} \
-%{Ym,*} \
-%{Wa,*:%*} \
--s %{fpic:-K PIC} %{fPIC:-K PIC} \
-%{mlittle-endian:-EL} \
-%(asm_cpu) %(asm_arch) \
-"
-
-/* Same as sparc.h */
-#undef DBX_REGISTER_NUMBER
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* System V Release 4 uses DWARF debugging info.  Buf DWARF1 doesn't do
-   64-bit anything, so we use DWARF2.  */
-
-#undef DWARF2_DEBUGGING_INFO
-#undef DWARF_DEBUGGING_INFO
-#undef DBX_DEBUGGING_INFO
-#define DWARF2_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fputs ("\t.local\t", (FILE));		\
-  assemble_name ((FILE), (NAME));					\
-  putc ('\n', (FILE));							\
-  ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);			\
-} while (0)
-
-#undef COMMON_ASM_OP
-#define COMMON_ASM_OP "\t.common"
-
-/* This is how to output a definition of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef  ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".L%s%d:\n", PREFIX, NUM)
-
-/* This is how to output a reference to an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef  ASM_OUTPUT_INTERNAL_LABELREF
-#define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".L%s%d", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#undef  ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*.L%s%d", PREFIX, NUM)
-
-/* Stabs doesn't use this, and it confuses a simulator.  */
-/* ??? Need to see what DWARF needs, if anything.  */
-#undef ASM_IDENTIFY_GCC
-#define ASM_IDENTIFY_GCC(FILE)
-
-/* Define the names of various pseudo-ops used by the Sparc/svr4 assembler.
-   ??? If ints are 64 bits then UNALIGNED_INT_ASM_OP (defined elsewhere) is
-   misnamed.  These should all refer to explicit sizes (half/word/xword?),
-   anything other than short/int/long/etc.  */
-
-#define UNALIGNED_DOUBLE_INT_ASM_OP	".uaxword"
-
-/* DWARF bits.  */
-
-/* Follow Irix 6 and not the Dwarf2 draft in using 64-bit offsets. 
-   Obviously the Dwarf2 folks havn't tried to actually build systems
-   with their spec.  On a 64-bit system, only 64-bit relocs become
-   RELATIVE relocations.  */
-
-/* #define DWARF_OFFSET_SIZE PTR_SIZE */
-
-/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
-   traps available which can get and set the condition codes
-   reliably.  */
-#undef MACHINE_STATE_SAVE
-#define MACHINE_STATE_SAVE(ID)				\
-  unsigned long int ms_flags, ms_saveret;		\
-  asm volatile("ta	0x20\n\t"			\
-	       "mov	%%g1, %0\n\t"			\
-	       "mov	%%g2, %1\n\t"			\
-	       : "=r" (ms_flags), "=r" (ms_saveret));
-
-#undef MACHINE_STATE_RESTORE
-#define MACHINE_STATE_RESTORE(ID)			\
-  asm volatile("mov	%0, %%g1\n\t"			\
-	       "mov	%1, %%g2\n\t"			\
-	       "ta	0x21\n\t"			\
-	       : /* no outputs */			\
-	       : "r" (ms_flags), "r" (ms_saveret));
diff --git a/gcc/config/sparc/lite.h b/gcc/config/sparc/lite.h
deleted file mode 100755
index 8d75647..0000000
--- a/gcc/config/sparc/lite.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SPARClite w/o FPU.
-   Copyright (C) 1993, 1996, 1999 Free Software Foundation, Inc.
-   Contributed by Jim Wilson (wilson@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sparc/sparc.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -Dsparclite -Acpu(sparc) -Amachine(sparc)"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (sparclite)");
-
-/* Enable sparclite, app-regs and epilogue options.  Do not enable the fpu.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_SPARCLITE + MASK_APP_REGS + MASK_EPILOGUE)
-
-/* US Software GOFAST library support.  */
-#include "gofast.h"
-#undef INIT_SUBTARGET_OPTABS
-#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-
-/* Don't set the target flags, this is done by the linker script */
-#undef LIB_SPEC
-#define LIB_SPEC ""
diff --git a/gcc/config/sparc/litecoff.h b/gcc/config/sparc/litecoff.h
deleted file mode 100755
index bd89e1b..0000000
--- a/gcc/config/sparc/litecoff.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SPARClite w/o FPU, COFF.
-   Copyright (C) 1994, 1996 Free Software Foundation, Inc.
-   Written by Ken Raeburn (raeburn@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sparc/lite.h"
-
-#undef ASM_OUTPUT_IDENT
-
-#undef SELECT_SECTION
-#undef SELECT_RTX_SECTION
-#define BSS_SECTION_ASM_OP	".section\t\".bss\""
-
-#include "svr3.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -Dsparclite -Acpu(sparc) -Amachine(sparc)"
-
-/* Default to stabs in COFF.  */
-
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#include "dbxcoff.h"
-
-/* Support the ctors and dtors sections for g++.  */
-
-#undef INIT_SECTION_ASM_OP
-
-/* Support the ctors and dtors sections for g++.  */
-
-#undef CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"x\""
-#undef DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"x\""
-
-/* A list of other sections which the compiler might be "in" at any
-   given time.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_ctors, in_dtors
-
-/* A list of extra section function definitions.  */
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CONST_SECTION_FUNCTION						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-#define INT_ASM_OP ".long"
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#undef ASM_OUTPUT_CONSTRUCTOR
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#undef ASM_OUTPUT_DESTRUCTOR
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-#undef DO_GLOBAL_CTORS_BODY
-#undef DO_GLOBAL_DTORS_BODY
diff --git a/gcc/config/sparc/liteelf.h b/gcc/config/sparc/liteelf.h
deleted file mode 100755
index 7861256..0000000
--- a/gcc/config/sparc/liteelf.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SPARClite w/o FPU.
-   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
-   Contributed by Stan Cox (scox@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sparc/elf.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -Dsparclite -Acpu(sparc) -Amachine(sparc)"
-
-/* Default to dwarf2 in ELF.  */
-
-#define DWARF_DEBUGGING_INFO
-#define DWARF2_DEBUGGING_INFO
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (sparclite)");
-
-/* Enable sparclite, app-regs and epilogue options.  Do not enable the fpu.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_SPARCLITE + MASK_APP_REGS + MASK_EPILOGUE)
-
-/* US Software GOFAST library support.  */
-#include "gofast.h"
-#undef INIT_SUBTARGET_OPTABS
-#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS      
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "crti.o%s crtbegin.o%s"
-
-/* Use __main method of constructor invocation */
-#undef INIT_SECTION_ASM_OP
-#undef FINI_SECTION_ASM_OP
diff --git a/gcc/config/sparc/lynx-ng.h b/gcc/config/sparc/lynx-ng.h
deleted file mode 100755
index 9e9f82c..0000000
--- a/gcc/config/sparc/lynx-ng.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Definitions for SPARC running LynxOS, using Lynx's old as and ld.
-   Copyright (C) 1993, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <sparc/sparc.h>
-#include <lynx-ng.h>
-
-/* ??? Must redefine to get sparclite and v8 defines.  Can this be done
-   differently?  */
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{mthreads:-D_MULTITHREADED}  \
-  %{mposix:-D_POSIX_SOURCE}  \
-  %{msystem-v:-I/usr/include_v}  \
-  %(cpp_cpu)"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dsparc -DLynx -DIBITS32 -Asystem(unix) -Asystem(lynx) -Acpu(sparc) -Amachine(sparc)"
-
-/* Provide required defaults for linker switches.  */
-
-#undef LINK_SPEC
-#define LINK_SPEC "-e __main -T 0 %{msystem-v:-V} %{mcoff:-k}"
diff --git a/gcc/config/sparc/lynx.h b/gcc/config/sparc/lynx.h
deleted file mode 100755
index 99b319a..0000000
--- a/gcc/config/sparc/lynx.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Definitions for SPARC running LynxOS.
-   Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <sparc/sparc.h>
-
-#undef ASM_OUTPUT_IDENT
-#undef SELECT_SECTION
-#undef SELECT_RTX_SECTION
-
-#define BSS_SECTION_ASM_OP	".section\t\".bss\""
-
-#include <lynx.h>
-
-/* ??? Must redefine to get sparclite and v8 defines.  Can this be done
-   differently?  */
-
-#undef CPP_SPEC
-#define CPP_SPEC "%{mthreads:-D_MULTITHREADED}  \
-  %{mposix:-D_POSIX_SOURCE}  \
-  %{msystem-v:-I/usr/include_v}  \
-  %(cpp_cpu)"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dsparc -DSPARC -DLynx -DLYNX -DIBITS32 -Asystem(unix) -Asystem(lynx) -Acpu(sparc) -Amachine(sparc)"
-
-#undef LINK_SPEC
-
-/* Sparc version of libc.a has references to libm.a (printf calls pow for
-   instance), so we must always link both. */
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{mthreads:-L/lib/thread/}  \
-  %{msystem-v:-lc_v -lm_v -lc_v}  \
-  %{!msystem-v:%{mposix:-lc_p} -lc -lm -lc}"
diff --git a/gcc/config/sparc/netbsd.h b/gcc/config/sparc/netbsd.h
deleted file mode 100755
index a512f41..0000000
--- a/gcc/config/sparc/netbsd.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#include <sparc/sparc.h>
-
-/* Get generic NetBSD definitions.  */
-
-#include <netbsd.h>
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dsparc -D__NetBSD__ -Asystem(unix) -Asystem(NetBSD) -Acpu(sparc) -Amachine(sparc)"
-
-/* Make gcc agree with <machine/ansi.h> */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "int"
-
-#undef WCHAR_UNSIGNED
-#define WCHAR_UNSIGNED 0
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 32
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* This is the char to use for continuation (in case we need to turn
-   continuation back on).  */
-
-#define DBX_CONTIN_CHAR '?'
-
-/* Don't default to pcc-struct-return, because gcc is the only compiler, and
-   we want to retain compatibility with older gcc versions.  */
-#undef DEFAULT_PCC_STRUCT_RETURN
-#define DEFAULT_PCC_STRUCT_RETURN 0
-
-/* Until they use ELF or something that handles dwarf2 unwinds
-   and initialization stuff better.  */
-#define DWARF2_UNWIND_INFO 0
-
diff --git a/gcc/config/sparc/pbd.h b/gcc/config/sparc/pbd.h
deleted file mode 100755
index 459bffd..0000000
--- a/gcc/config/sparc/pbd.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/* Definitions of target machine for GNU compiler, Citicorp/TTI Unicom PBD
-   version (using GAS and COFF (encapsulated is unacceptable) )
-   Copyright (C) 1990, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sparc/sparc.h"
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -DUnicomPBD -Dunix -D__GCC_NEW_VARARGS__ -Asystem(unix) -Acpu(sparc) -Amachine(sparc)"
-
-/* We want DBX format for use with gdb under COFF.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Generate calls to memcpy, memcmp and memset.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* we use /lib/libp/lib*  when profiling */
-
-#undef LIB_SPEC
-#define LIB_SPEC "%{p:-L/usr/lib/libp} %{pg:-L/usr/lib/libp} -lc"
-
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-/*
- * The loader directive file gcc.ifile defines how to merge the constructor 
- * sections into the data section.  Also, since gas only puts out those 
- * sections in response to N_SETT stabs, and does not (yet) have a 
- * ".sections" directive, gcc.ifile also defines the list symbols 
- * __DTOR_LIST__ and __CTOR_LIST__.
- * 
- * Finally, we must explicitly specify the file from libgcc.a that defines
- * exit(), otherwise if the user specifies (for example) "-lc_s" on the 
- * command line, the wrong exit() will be used and global destructors will 
- * not get called .
- */
-
-#define STARTFILE_SPEC \
-"%{!r: gcc.ifile%s} %{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} \
-%{!r:_exit.o%s}"
-
-#define ENDFILE_SPEC "crtn.o%s"
-
-/* cpp has to support a #sccs directive for the /usr/include files */
-
-#define SCCS_DIRECTIVE
-
-/* LINK_SPEC is needed only for SunOS 4.  */
-
-#undef LINK_SPEC
-
-/* Although the gas we use can create .ctor and .dtor sections from N_SETT
-   stabs, it does not support section directives, so we need to have the loader
-   define the lists.
-   */
-#define CTOR_LISTS_DEFINED_EXTERNALLY
-
-/* similar to default, but allows for the table defined by ld with gcc.ifile. 
-   nptrs is always 0.  So we need to instead check that __DTOR_LIST__[1] != 0.
-   The old check is left in so that the same macro can be used if and when  
-   a future version of gas does support section directives. */
-
-#define DO_GLOBAL_DTORS_BODY {int nptrs = *(int *)__DTOR_LIST__; int i; \
-  if (nptrs == -1 || (__DTOR_LIST__[0] == 0 && __DTOR_LIST__[1] != 0))  \
-    for (nptrs = 0; __DTOR_LIST__[nptrs + 1] != 0; nptrs++); 		\
-  for (i = nptrs; i >= 1; i--)						\
-    __DTOR_LIST__[i] (); }
-
-/* 
- * Here is an example gcc.ifile.  I've tested it on PBD sparc
- * systems. The NEXT(0x200000) works on just about all 386 and m68k systems, 
- * but can be reduced to any power of 2 that is >= NBPS (0x40000 on a pbd).
-
-   SECTIONS {
-       .text BIND(0x41000200) BLOCK (0x200) : 
-		{ *(.init) *(.text) vfork = fork; *(.fini) }
-
-      	GROUP BIND( NEXT(0x200000) + ADDR(.text) + SIZEOF(.text)):
-	{      .data : { __CTOR_LIST__ = . ; . += 4; *(.ctor) . += 4 ;
-		       	 __DTOR_LIST__ = . ; . += 4; *(.dtor) . += 4 ; }
-	       .bss : { }
-       }
-  }
- */
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-
-/* fixes: */
-/*
- *  Internal labels are prefixed with a period.
- */
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
-        sprintf (LABEL, "*.%s%d", PREFIX, NUM)
-
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef  ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)                      \
-        fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#undef  ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
-
-/* This is how to output an element of a case-vector that is absolute.
-   (The 68000 does not use such vectors,
-   but we must define this macro anyway.)  */
-
-#undef ASM_OUTPUT_ADDR_VEC_ELT
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.word .L%d\n", VALUE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\tsethi %%hi(.LP%d),%%o0\n\tcall mcount\n\tor %%lo(.LP%d),%%o0,%%o0\n", \
-	   (LABELNO), (LABELNO))
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.  */
-
-#undef FUNCTION_BLOCK_PROFILER
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\tsethi %%hi(.LPBX0),%%o0\n\tld [%%lo(.LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne .LPY%d\n\tnop\n\tcall ___bb_init_func\n\tnop\n.LPY%d:\n",  \
-	   (LABELNO), (LABELNO))
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  */
-
-#undef BLOCK_PROFILER
-#define BLOCK_PROFILER(FILE, BLOCKNO) \
-{								\
-  int blockn = (BLOCKNO);					\
-  fprintf (FILE, "\tsethi %%hi(.LPBX2+%d),%%g1\n\tld [%%lo(.LPBX2+%d)+%%g1],%%g2\n\
-\tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(.LPBX2+%d)+%%g1]\n",		\
-	   4 * blockn, 4 * blockn, 4 * blockn);			\
-  CC_STATUS_INIT;  /* We have clobbered %g1.  Also %g2.  */	\
-}
-/*   This is needed for SunOS 4.0, and should not hurt for 3.2
-   versions either.  */
-#undef ASM_OUTPUT_SOURCE_LINE(file, line) 
-#define ASM_OUTPUT_SOURCE_LINE(file, line)		\
-  { static int sym_lineno = 1;				\
-    fprintf (file, ".stabn 68,0,%d,.LM%d\n.LM%d:\n",	\
-	     line, sym_lineno, sym_lineno);		\
-    sym_lineno += 1; }
-
-#define ASM_INT_OP ".long "
diff --git a/gcc/config/sparc/rtems.h b/gcc/config/sparc/rtems.h
deleted file mode 100755
index 1ab0a42..0000000
--- a/gcc/config/sparc/rtems.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Definitions for rtems targeting a SPARC using a.out.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Joel Sherrill (joel@OARcorp.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sparc/aout.h"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -D__GCC_NEW_VARARGS__ -Drtems -D__rtems__ \
-  -Asystem(rtems) -Acpu(sparc) -Amachine(sparc)"
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#ifndef TARGET_MEM_FUNCTIONS
-#define TARGET_MEM_FUNCTIONS
-#endif
-
-/* end of sparc/rtems.h */
diff --git a/gcc/config/sparc/sol2-c1.asm b/gcc/config/sparc/sol2-c1.asm
deleted file mode 100755
index 894a8c3..0000000
--- a/gcc/config/sparc/sol2-c1.asm
+++ /dev/null
@@ -1,110 +0,0 @@
-! crt1.s for sparc & sparcv9 (SunOS 5)
-
-!   Copyright (C) 1992 Free Software Foundation, Inc.
-!   Written By David Vinayak Henkel-Wallace, June 1992
-! 
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-! 
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file with other programs, and to distribute
-! those programs without any restriction coming from the use of this
-! file.  (The General Public License restrictions do apply in other
-! respects; for example, they cover modification of the file, and
-! distribution when not linked into another program.)
-! 
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-! General Public License for more details.
-! 
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING.  If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-! 
-!    As a special exception, if you link this library with files
-!    compiled with GCC to produce an executable, this does not cause
-!    the resulting executable to be covered by the GNU General Public License.
-!    This exception does not however invalidate any other reasons why
-!    the executable file might be covered by the GNU General Public License.
-! 
-
-! This file takes control of the process from the kernel, as specified
-! in section 3 of the SVr4 ABI.
-! This file is the first thing linked into any executable.
-
-#ifdef __sparcv9
-#define	CPTRSIZE	8
-#define	CPTRSHIFT	3
-#define	STACK_BIAS	2047
-#define	ldn		ldx
-#define	stn		stx
-#define setn(s, scratch, dst)	setx s, scratch, dst
-#else
-#define	CPTRSIZE	4
-#define	CPTRSHIFT	2
-#define	STACK_BIAS	0
-#define	ldn		ld
-#define	stn		st
-#define setn(s, scratch, dst)	set s, dst
-#endif
-
-	.section	".text"
-	.proc	022
-	.global	_start
-
-_start:
-	mov	0, %fp		! Mark bottom frame pointer
-	ldn	[%sp + (16 * CPTRSIZE) + STACK_BIAS], %l0	! argc
-	add	%sp, (17 * CPTRSIZE) + STACK_BIAS, %l1		! argv
-
-	! Leave some room for a call.  Sun leaves 32 octets (to sit on
-	! a cache line?) so we do too.
-#ifdef __sparcv9
-	sub	%sp, 48, %sp
-#else
-	sub	%sp, 32, %sp
-#endif
-
-	! %g1 may contain a function to be registered w/atexit
-	orcc	%g0, %g1, %g0
-#ifdef __sparcv9
-	be	%xcc, .nope
-#else
-	be	.nope
-#endif
-	mov	%g1, %o0
-	call	atexit
-	nop   
-.nope:
-	! Now make sure constructors and destructors are handled.
-	setn(_fini, %o1, %o0)
-	call	atexit, 1
-	nop
-	call	_init, 0
-	nop
-
-	! We ignore the auxiliary vector; there is no defined way to
-	! access those data anyway.  Instead, go straight to main:
-	mov	%l0, %o0	! argc
-	mov	%l1, %o1	! argv
-	! Skip argc words past argv, to env:
-	sll	%l0, CPTRSHIFT, %o2
-	add	%o2, CPTRSIZE, %o2
-	add	%l1, %o2, %o2	! env
-	setn(_environ, %o4, %o3)
-	stn	%o2, [%o3]	! *_environ
-	call	main, 4
-	nop   
-	call	exit, 0
-	nop   
-	call	_exit, 0
-	nop   
-	! We should never get here.
-
-	.type	_start,#function
-	.size	_start,.-_start
diff --git a/gcc/config/sparc/sol2-ci.asm b/gcc/config/sparc/sol2-ci.asm
deleted file mode 100755
index 3dc793c..0000000
--- a/gcc/config/sparc/sol2-ci.asm
+++ /dev/null
@@ -1,68 +0,0 @@
-! crti.s for solaris 2.0.
-
-!   Copyright (C) 1992 Free Software Foundation, Inc.
-!   Written By David Vinayak Henkel-Wallace, June 1992
-! 
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-! 
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file with other programs, and to distribute
-! those programs without any restriction coming from the use of this
-! file.  (The General Public License restrictions do apply in other
-! respects; for example, they cover modification of the file, and
-! distribution when not linked into another program.)
-! 
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-! General Public License for more details.
-! 
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING.  If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-! 
-!    As a special exception, if you link this library with files
-!    compiled with GCC to produce an executable, this does not cause
-!    the resulting executable to be covered by the GNU General Public License.
-!    This exception does not however invalidate any other reasons why
-!    the executable file might be covered by the GNU General Public License.
-! 
-
-! This file just make a stack frame for the contents of the .fini and
-! .init sections.  Users may put any desired instructions in those
-! sections.
-
-! This file is linked in before the Values-Xx.o files and also before
-! crtbegin, with which perhaps it should be merged.
- 
-	.file		"crti.s"
-
-	.section	".init"
-	.proc	022
-	.global	_init
-	.type	_init,#function
-	.align	4
-_init:
-#ifdef __sparcv9
-	save	%sp, -176, %sp
-#else
-	save	%sp, -96, %sp
-#endif
-
-
-	.section	".fini"
-	.proc	022
-	.global	_fini
-	.type	_fini,#function
-	.align	4
-_fini:
-#ifdef __sparcv9
-	save	%sp, -176, %sp
-#else
-	save	%sp, -96, %sp
-#endif
diff --git a/gcc/config/sparc/sol2-cn.asm b/gcc/config/sparc/sol2-cn.asm
deleted file mode 100755
index 49e070f..0000000
--- a/gcc/config/sparc/sol2-cn.asm
+++ /dev/null
@@ -1,54 +0,0 @@
-! crtn.s for solaris 2.0.
-
-!   Copyright (C) 1992 Free Software Foundation, Inc.
-!   Written By David Vinayak Henkel-Wallace, June 1992
-! 
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-! 
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file with other programs, and to distribute
-! those programs without any restriction coming from the use of this
-! file.  (The General Public License restrictions do apply in other
-! respects; for example, they cover modification of the file, and
-! distribution when not linked into another program.)
-! 
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-! General Public License for more details.
-! 
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING.  If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-! 
-!    As a special exception, if you link this library with files
-!    compiled with GCC to produce an executable, this does not cause
-!    the resulting executable to be covered by the GNU General Public License.
-!    This exception does not however invalidate any other reasons why
-!    the executable file might be covered by the GNU General Public License.
-! 
-
-! This file just makes sure that the .fini and .init sections do in
-! fact return.  Users may put any desired instructions in those sections.
-! This file is the last thing linked into any executable.
-
-	.file		"crtn.s"
-
-	.section	".init"
-	.align		4
-
-	ret
-	restore
-
-	.section	".fini"
-	.align		4
-
-	ret
-	restore
-
-! Th-th-th-that is all folks!
diff --git a/gcc/config/sparc/sol2-g1.asm b/gcc/config/sparc/sol2-g1.asm
deleted file mode 100755
index b9d8788..0000000
--- a/gcc/config/sparc/sol2-g1.asm
+++ /dev/null
@@ -1,88 +0,0 @@
-! gcrt1.s for solaris 2.0.
-
-!   Copyright (C) 1992 Free Software Foundation, Inc.
-!   Written By David Vinayak Henkel-Wallace, June 1992
-! 
-! This file is free software; you can redistribute it and/or modify it
-! under the terms of the GNU General Public License as published by the
-! Free Software Foundation; either version 2, or (at your option) any
-! later version.
-! 
-! In addition to the permissions in the GNU General Public License, the
-! Free Software Foundation gives you unlimited permission to link the
-! compiled version of this file with other programs, and to distribute
-! those programs without any restriction coming from the use of this
-! file.  (The General Public License restrictions do apply in other
-! respects; for example, they cover modification of the file, and
-! distribution when not linked into another program.)
-! 
-! This file is distributed in the hope that it will be useful, but
-! WITHOUT ANY WARRANTY; without even the implied warranty of
-! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-! General Public License for more details.
-! 
-! You should have received a copy of the GNU General Public License
-! along with this program; see the file COPYING.  If not, write to
-! the Free Software Foundation, 59 Temple Place - Suite 330,
-! Boston, MA 02111-1307, USA.
-! 
-!    As a special exception, if you link this library with files
-!    compiled with GCC to produce an executable, this does not cause
-!    the resulting executable to be covered by the GNU General Public License.
-!    This exception does not however invalidate any other reasons why
-!    the executable file might be covered by the GNU General Public License.
-! 
-
-! This file takes control of the process from the kernel, as specified
-! in section 3 of the SVr4 ABI.
-! This file is the first thing linked into any executable.
-
-	.section	".text"
-	.proc	022
-	.global	_start
-
-_start:
-	mov	0, %fp		! Mark bottom frame pointer
-	ld	[%sp + 64], %l0	! argc
-	add	%sp, 68, %l1	! argv
-
-	! Leave some room for a call.  Sun leaves 32 octets (to sit on
-	! a cache line?) so we do too.
-	sub	%sp, 32, %sp
-
-	! %g1 may contain a function to be registered w/atexit
-	orcc	%g0, %g1, %g0
-	be	.nope
-	mov	%g1, %o0
-	call	atexit
-	nop   
-.nope:
-	! Now make sure constructors and destructors are handled.
-	set	_fini, %o0
-	call	atexit, 1
-	nop
-	call	_init, 0
-	nop
-
-	! We ignore the auxiliary vector; there's no defined way to
-	! access those data anyway.  Instead, go straight to main:
-	mov	%l0, %o0	! argc
-	mov	%l1, %o1	! argv
-	set	___Argv, %o3
-	st	%o1, [%o3]	! *___Argv
-	! Skip argc words past argv, to env:
-	sll	%l0, 2, %o2
-	add	%o2, 4, %o2
-	add	%l1, %o2, %o2	! env
-	set	_environ, %o3
-	st	%o2, [%o3]	! *_environ
-	call	main, 4
-	nop   
-	call	exit, 0
-	nop   
-	call	_exit, 0
-	nop   
-	! We should never get here.
-
-	.type	_start,#function
-	.size	_start,.-_start
diff --git a/gcc/config/sparc/sol2-sld-64.h b/gcc/config/sparc/sol2-sld-64.h
deleted file mode 100755
index c2518d8..0000000
--- a/gcc/config/sparc/sol2-sld-64.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/* Definitions of target machine for GNU compiler, for 64-bit SPARC
-   running Solaris 2 using the system linker.  */
-
-#define SPARC_BI_ARCH
-
-#include "sparc/sol2.h"
-
-/* At least up through Solaris 2.6,
-   the system linker does not work with DWARF or DWARF2,
-   since it does not have working support for relocations
-   to unaligned data.  */
-
-#define LINKER_DOES_NOT_WORK_WITH_DWARF2
-
-/* A 64 bit v9 compiler with stack-bias */
-
-#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT \
-  (MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ + \
-   MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
-#endif
-
-/* The default code model.  */
-#undef SPARC_DEFAULT_CMODEL
-#define SPARC_DEFAULT_CMODEL CM_MEDANY
-
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 128
-
-#undef ASM_CPU32_DEFAULT_SPEC
-#define ASM_CPU32_DEFAULT_SPEC	""
-#undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC	"-xarch=v9"
-
-#if TARGET_CPU_DEFAULT == TARGET_CPU_v9
-#undef CPP_CPU64_DEFAULT_SPEC
-#define CPP_CPU64_DEFAULT_SPEC ""
-#undef ASM_CPU32_DEFAULT_SPEC
-#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plus"
-#endif
-#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
-#undef CPP_CPU64_DEFAULT_SPEC
-#define CPP_CPU64_DEFAULT_SPEC ""
-#undef ASM_CPU32_DEFAULT_SPEC
-#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusa"
-#undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9a"
-#endif
-
-/* The sun bundled assembler doesn't accept -Yd, (and neither does gas).
-   It's safe to pass -s always, even if -g is not used. */
-#undef ASM_SPEC
-#define ASM_SPEC "\
-%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s \
-%{fpic:-K PIC} %{fPIC:-K PIC} \
-%(asm_cpu)\
-"
-
-#if DEFAULT_ARCH32_P
-#define DEF_ARCH32_SPEC(__str) "%{!m64:" __str "}"
-#define DEF_ARCH64_SPEC(__str) "%{m64:" __str "}"
-#else
-#define DEF_ARCH32_SPEC(__str) "%{m32:" __str "}"
-#define DEF_ARCH64_SPEC(__str) "%{!m32:" __str "}"
-#endif
-
-#undef CPP_CPU_SPEC
-#define CPP_CPU_SPEC "\
-%{mcypress:} \
-%{msparclite:-D__sparclite__} \
-%{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
-%{mv8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
-%{msupersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \
-%{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
-%{mcpu=sparclite:-D__sparclite__} \
-%{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
-%{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
-%{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \
-%{mcpu=v9:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
-%{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
-%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
-"
-
-#undef ASM_CPU_SPEC
-#define ASM_CPU_SPEC "\
-%{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-xarch=v8plusa") DEF_ARCH64_SPEC("-xarch=v9a") "} \
-%{mcpu=v9:" DEF_ARCH32_SPEC("-xarch=v8plus") DEF_ARCH64_SPEC("-xarch=v9") "} \
-%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC("-xarch=v9") "}}} \
-%{!mcpu*:%(asm_cpu_default)} \
-"
-
-#define STARTFILE_SPEC32 "\
-%{ansi:values-Xc.o%s} \
-%{!ansi: \
- %{traditional:values-Xt.o%s} \
- %{!traditional:values-Xa.o%s}}"
-
-#define STARTFILE_SPEC64 "\
-%{ansi:/usr/lib/sparcv9/values-Xc.o%s} \
-%{!ansi: \
- %{traditional:/usr/lib/sparcv9/values-Xt.o%s} \
- %{!traditional:/usr/lib/sparcv9/values-Xa.o%s}}"
- 
-#ifdef SPARC_BI_ARCH
-
-#if DEFAULT_ARCH32_P
-#define STARTFILE_ARCH_SPEC "\
-%{m32:" STARTFILE_SPEC32 "} \
-%{m64:" STARTFILE_SPEC64 "} \
-%{!m32:%{!m64:" STARTFILE_SPEC32 "}}"
-#else
-#define STARTFILE_ARCH_SPEC "\
-%{m32:" STARTFILE_SPEC32 "} \
-%{m64:" STARTFILE_SPEC64 "} \
-%{!m32:%{!m64:" STARTFILE_SPEC64 "}}"
-#endif
-
-#else /* !SPARC_BI_ARCH */
-
-/* In this case we define MD_STARTFILE_PREFIX to /usr/lib/sparcv9/ */
-#define STARTFILE_ARCH_SPEC STARTFILE_SPEC32
-
-#endif /* !SPARC_BI_ARCH */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared: \
-			 %{!symbolic: \
-			  %{p:mcrt1.o%s} \
-                          %{!p: \
-	                    %{pg:gcrt1.o%s gmon.o%s} \
-                            %{!pg:crt1.o%s}}}} \
-			crti.o%s" STARTFILE_ARCH_SPEC " \
-			crtbegin.o%s"
-
-#ifdef SPARC_BI_ARCH
-
-#undef CPP_CPU_DEFAULT_SPEC
-#define CPP_CPU_DEFAULT_SPEC \
-(DEFAULT_ARCH32_P ? "\
-%{m64:" CPP_CPU64_DEFAULT_SPEC "} \
-%{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
-" : "\
-%{m32:" CPP_CPU32_DEFAULT_SPEC "} \
-%{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
-")
-
-#undef ASM_CPU_DEFAULT_SPEC
-#define ASM_CPU_DEFAULT_SPEC \
-(DEFAULT_ARCH32_P ? "\
-%{m64:" ASM_CPU64_DEFAULT_SPEC "} \
-%{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
-" : "\
-%{m32:" ASM_CPU32_DEFAULT_SPEC "} \
-%{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
-")
-
-#undef CPP_ARCH32_SPEC
-#define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \
--D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)"
-#undef CPP_ARCH64_SPEC
-#define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
--D__arch64__ -Acpu(sparc64) -Amachine(sparcv9) -D__sparcv9"
-
-#undef CPP_ARCH_SPEC
-#define CPP_ARCH_SPEC "\
-%{m32:%(cpp_arch32)} \
-%{m64:%(cpp_arch64)} \
-%{!m32:%{!m64:%(cpp_arch_default)}} \
-"
-
-#undef ASM_ARCH_SPEC
-#define ASM_ARCH_SPEC ""
-
-#undef ASM_ARCH32_SPEC
-#define ASM_ARCH32_SPEC ""
-
-#undef ASM_ARCH64_SPEC
-#define ASM_ARCH64_SPEC ""
-
-#undef ASM_ARCH_DEFAULT_SPEC
-#define ASM_ARCH_DEFAULT_SPEC ""
-
-#undef SUBTARGET_EXTRA_SPECS
-#define SUBTARGET_EXTRA_SPECS \
-  { "link_arch32",       LINK_ARCH32_SPEC },              \
-  { "link_arch64",       LINK_ARCH64_SPEC },              \
-  { "link_arch_default", LINK_ARCH_DEFAULT_SPEC },	  \
-  { "link_arch",	 LINK_ARCH_SPEC },
-    
-/* This should be the same as in svr4.h, except with -R added.  */
-#define LINK_ARCH32_SPEC \
-  "%{G:-G} \
-   %{YP,*} \
-   %{R*} \
-   %{compat-bsd: \
-     %{!YP,*:%{p:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-       %{pg:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-       %{!p:%{!pg:-Y P,/usr/ucblib:/usr/ccs/lib:/usr/lib}}} \
-     -R /usr/ucblib} \
-   %{!compat-bsd: \
-     %{!YP,*:%{p:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-       %{pg:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-       %{!p:%{!pg:-Y P,/usr/ccs/lib:/usr/lib}}}}"
-
-#define LINK_ARCH64_SPEC \
-  "%{mcmodel=medlow:-M /usr/lib/ld/sparcv9/map.below4G} \
-   %{G:-G} \
-   %{YP,*} \
-   %{R*} \
-   %{compat-bsd: \
-     %{!YP,*:%{p:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \
-       %{pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \
-       %{!p:%{!pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/sparcv9}}} \
-     -R /usr/ucblib} \
-   %{!compat-bsd: \
-     %{!YP,*:%{p:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \
-       %{pg:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \
-       %{!p:%{!pg:-Y P,/usr/lib/sparcv9}}}}"
-
-#define LINK_ARCH_SPEC "\
-%{m32:%(link_arch32)} \
-%{m64:%(link_arch64)} \
-%{!m32:%{!m64:%(link_arch_default)}} \
-"
-
-#define LINK_ARCH_DEFAULT_SPEC \
-(DEFAULT_ARCH32_P ? LINK_ARCH32_SPEC : LINK_ARCH64_SPEC)
-
-#undef  LINK_SPEC
-#define LINK_SPEC \
-  "%{h*} %{v:-V} \
-   %{b} %{Wl,*:%*} \
-   %{static:-dn -Bstatic} \
-   %{shared:-G -dy %{!mimpure-text:-z text}} \
-   %{symbolic:-Bsymbolic -G -dy -z text} \
-   %(link_arch) \
-   %{Qy:} %{!Qn:-Qy}"
-
-#undef	CC1_SPEC
-#if DEFAULT_ARCH32_P
-#define CC1_SPEC "\
-%{sun4:} %{target:} \
-%{mcypress:-mcpu=cypress} \
-%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
-%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
-%{m64:-mptr64 -mcpu=v9 -mstack-bias -mno-v8plus} \
-"
-#else
-#define CC1_SPEC "\
-%{sun4:} %{target:} \
-%{mcypress:-mcpu=cypress} \
-%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
-%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
-%{m32:-mptr32 -mcpu=cypress -mno-stack-bias} \
-%{mv8plus:-m32 -mptr32 -mcpu=cypress -mno-stack-bias} \
-"
-#endif
-
-#if DEFAULT_ARCH32_P
-#define MULTILIB_DEFAULTS { "m32" }
-#else
-#define MULTILIB_DEFAULTS { "m64" }
-#endif
-
-#else /* !SPARC_BI_ARCH */
-
-/*
- * This should be the same as in sol2-sld.h, except with "/sparcv9"
- * appended to the paths and /usr/ccs/lib is no longer necessary
- */
-#undef LINK_SPEC
-#define LINK_SPEC \
-  "%{h*} %{v:-V} \
-   %{b} %{Wl,*:%*} \
-   %{static:-dn -Bstatic} \
-   %{shared:-G -dy %{!mimpure-text:-z text}} \
-   %{symbolic:-Bsymbolic -G -dy -z text} \
-   %{mcmodel=medlow:-M /usr/lib/ld/sparcv9/map.below4G} \
-   %{G:-G} \
-   %{YP,*} \
-   %{R*} \
-   %{compat-bsd: \
-     %{!YP,*:%{p:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \
-       %{pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \
-       %{!p:%{!pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/sparcv9}}} \
-     -R /usr/ucblib} \
-   %{!compat-bsd: \
-     %{!YP,*:%{p:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \
-       %{pg:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \
-       %{!p:%{!pg:-Y P,/usr/lib/sparcv9}}}} \
-   %{Qy:} %{!Qn:-Qy}"
-   
-#undef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/lib/sparcv9/"
- 
-#endif /* ! SPARC_BI_ARCH */
-
-/*
- * Attempt to turn on access permissions for the stack.
- *
- * This code must be defined when compiling gcc but not when compiling
- * libgcc2.a, unless we're generating code for 64 bits SPARC
- *
- * _SC_STACK_PROT is only defined for post 2.6, but we want this code
- * to run always.  2.6 can change the stack protection but has no way to
- * query it.
- *
- */
-
-#define TRANSFER_FROM_TRAMPOLINE					\
-static int need_enable_exec_stack;					\
-									\
-static void check_enabling(void) __attribute__ ((constructor));		\
-static void check_enabling(void)					\
-{									\
-  extern long sysconf(int);						\
-									\
-  int prot = (int) sysconf(515 /*_SC_STACK_PROT */);			\
-  if (prot != 7)							\
-    need_enable_exec_stack = 1;						\
-}									\
-									\
-void									\
-__enable_execute_stack (addr)						\
-     void *addr;							\
-{									\
-  if (!need_enable_exec_stack)						\
-    return;								\
-  else {								\
-    long size = getpagesize ();						\
-    long mask = ~(size-1);						\
-    char *page = (char *) (((long) addr) & mask); 			\
-    char *end  = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \
-									\
-    /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */ 			\
-    if (mprotect (page, end - page, 7) < 0)				\
-      perror ("mprotect of trampoline code");				\
-  }									\
-}
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#undef ASM_OUTPUT_CONSTRUCTOR
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", TARGET_ARCH64 ? ASM_LONGLONG : INT_ASM_OP); \
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#undef ASM_OUTPUT_DESTRUCTOR
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", TARGET_ARCH64 ? ASM_LONGLONG : INT_ASM_OP); \
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
diff --git a/gcc/config/sparc/sol2-sld.h b/gcc/config/sparc/sol2-sld.h
deleted file mode 100755
index a824987..0000000
--- a/gcc/config/sparc/sol2-sld.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SPARC running Solaris 2
-   using the system linker.  */
-
-#include "sparc/sol2.h"
-
-/* At least up through Solaris 2.6,
-   the system linker does not work with DWARF or DWARF2,
-   since it does not have working support for relocations
-   to unaligned data.  */
-
-#define LINKER_DOES_NOT_WORK_WITH_DWARF2
diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h
deleted file mode 100755
index 9274f9d..0000000
--- a/gcc/config/sparc/sol2.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SPARC running Solaris 2
-   Copyright 1992, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Ron Guilmette (rfg@netcom.com).
-   Additional changes by David V. Henkel-Wallace (gumby@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Supposedly the same as vanilla sparc svr4, except for the stuff below: */
-#include "sparc/sysv4.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
-"-Dsparc -Dsun -Dunix -D__svr4__ -D__SVR4 \
--Asystem(unix) -Asystem(svr4)"
-
-#undef CPP_SUBTARGET_SPEC
-#define CPP_SUBTARGET_SPEC "\
-%{pthreads:-D_REENTRANT -D_PTHREADS} \
-%{!pthreads:%{threads:-D_REENTRANT -D_SOLARIS_THREADS}} \
-%{compat-bsd:-iwithprefixbefore ucbinclude -I/usr/ucbinclude} \
-"
-
-/* The sun bundled assembler doesn't accept -Yd, (and neither does gas).
-   It's safe to pass -s always, even if -g is not used. */
-#undef ASM_SPEC
-#define ASM_SPEC "\
-%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s \
-%{fpic:-K PIC} %{fPIC:-K PIC} \
-%(asm_cpu) \
-"
-
-/* This is here rather than in sparc.h because it's not known what
-   other assemblers will accept.  */
-#if TARGET_CPU_DEFAULT == TARGET_CPU_v9
-#undef ASM_CPU_DEFAULT_SPEC
-#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plus"
-#endif
-#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
-#undef ASM_CPU_DEFAULT_SPEC
-#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusa"
-#endif
-#undef ASM_CPU_SPEC
-#define ASM_CPU_SPEC "\
-%{mcpu=v8plus:-xarch=v8plus} \
-%{mcpu=ultrasparc:-xarch=v8plusa} \
-%{!mcpu*:%(asm_cpu_default)} \
-"
-
-/* However it appears that Solaris 2.0 uses the same reg numbering as
-   the old BSD-style system did. */
-
-#undef DBX_REGISTER_NUMBER
-/* Same as sparc.h */
-#define DBX_REGISTER_NUMBER(REGNO) \
-  (TARGET_FLAT && REGNO == FRAME_POINTER_REGNUM ? 31 : REGNO)
-
-/* We use stabs-in-elf for debugging, because that is what the native
-   toolchain uses.  */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* The Solaris 2 assembler uses .skip, not .zero, so put this back. */
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.skip %u\n", (SIZE))
-
-/* Use .uahalf/.uaword so packed structure members don't generate
-   assembler errors when using the native assembler.  */
-#undef ASM_SHORT
-#define ASM_SHORT ".uahalf"
-#undef ASM_LONG
-#define ASM_LONG ".uaword"
-
-/* This is how to output a definition of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef  ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".L%s%d:\n", PREFIX, NUM)
-
-/* This is how to output a reference to an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef  ASM_OUTPUT_INTERNAL_LABELREF
-#define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".L%s%d", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#undef  ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf ((LABEL), "*.L%s%ld", (PREFIX), (long)(NUM))
-
-
-/* We don't use the standard svr4 STARTFILE_SPEC because it's wrong for us.
-   We don't use the standard LIB_SPEC only because we don't yet support c++ */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared: \
-			 %{!symbolic: \
-			  %{p:mcrt1.o%s} \
-                          %{!p: \
-	                    %{pg:gcrt1.o%s gmon.o%s} \
-                            %{!pg:crt1.o%s}}}} \
-			crti.o%s \
-			%{ansi:values-Xc.o%s} \
-			%{!ansi: \
-			 %{traditional:values-Xt.o%s} \
-			 %{!traditional:values-Xa.o%s}} \
-			crtbegin.o%s"
-
-/* ??? Note: in order for -compat-bsd to work fully,
-   we must somehow arrange to fixincludes /usr/ucbinclude
-   and put the result in $(libsubdir)/ucbinclude.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC \
-  "%{compat-bsd:-lucb -lsocket -lnsl -lelf -laio} \
-   %{!shared:\
-     %{!symbolic:\
-       %{pthreads:-lpthread} \
-       %{!pthreads:%{threads:-lthread}} \
-       -lc}}"
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
-
-/* This should be the same as in svr4.h, except with -R added.  */
-#undef LINK_SPEC
-#define LINK_SPEC \
-  "%{h*} %{v:-V} \
-   %{b} %{Wl,*:%*} \
-   %{static:-dn -Bstatic} \
-   %{shared:-G -dy %{!mimpure-text:-z text}} \
-   %{symbolic:-Bsymbolic -G -dy -z text} \
-   %{G:-G} \
-   %{YP,*} \
-   %{R*} \
-   %{compat-bsd: \
-     %{!YP,*:%{p:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-       %{pg:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-       %{!p:%{!pg:-Y P,/usr/ucblib:/usr/ccs/lib:/usr/lib}}} \
-     -R /usr/ucblib} \
-   %{!compat-bsd: \
-     %{!YP,*:%{p:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-       %{pg:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-       %{!p:%{!pg:-Y P,/usr/ccs/lib:/usr/lib}}}} \
-   %{Qy:} %{!Qn:-Qy}"
-
-/* This defines which switch letters take arguments.
-   It is as in svr4.h but with -R added.  */
-
-#undef SWITCH_TAKES_ARG
-#define SWITCH_TAKES_ARG(CHAR) \
-  (DEFAULT_SWITCH_TAKES_ARG(CHAR) \
-   || (CHAR) == 'R' \
-   || (CHAR) == 'h' \
-   || (CHAR) == 'x' \
-   || (CHAR) == 'z')
-
-/* ??? This does not work in SunOS 4.x, so it is not enabled in sparc.h.
-   Instead, it is enabled here, because it does work under Solaris.  */
-/* Define for support of TFmode long double and REAL_ARITHMETIC.
-   Sparc ABI says that long double is 4 words.  */
-#define LONG_DOUBLE_TYPE_SIZE 128
-
-/* But indicate that it isn't supported by the hardware.  */
-#define WIDEST_HARDWARE_FP_SIZE 64
-
-#define STDC_0_IN_SYSTEM_HEADERS
-
-#define MULDI3_LIBCALL "__mul64"
-#define DIVDI3_LIBCALL "__div64"
-#define UDIVDI3_LIBCALL "__udiv64"
-#define MODDI3_LIBCALL "__rem64"
-#define UMODDI3_LIBCALL "__urem64"
-
-#undef INIT_SUBTARGET_OPTABS
-#define INIT_SUBTARGET_OPTABS	\
-  fixsfdi_libfunc = gen_rtx_SYMBOL_REF (Pmode, \
-	TARGET_ARCH64 ? "__ftol" : "__ftoll");	\
-  fixunssfdi_libfunc = gen_rtx_SYMBOL_REF (Pmode, \
-	TARGET_ARCH64 ? "__ftoul" : "__ftoull");	\
-  fixdfdi_libfunc = gen_rtx_SYMBOL_REF (Pmode, \
-	TARGET_ARCH64 ? "__dtol" : "__dtoll");	\
-  fixunsdfdi_libfunc = gen_rtx_SYMBOL_REF (Pmode, \
-	TARGET_ARCH64 ? "__dtoul" : "__dtoull")
-
-/* No weird SPARC variants on Solaris */
-#undef TARGET_LIVE_G0
-#define TARGET_LIVE_G0	0
-#undef TARGET_BROKEN_SAVERESTORE
-#define TARGET_BROKEN_SAVERESTORE 0
-
-/* Solaris allows 64 bit out and global registers in 32 bit mode.
-   sparc_override_options will disable V8+ if not generating V9 code.  */
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_V8PLUS)
-
-/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
-   traps available which can get and set the condition codes
-   reliably.  */
-#undef MACHINE_STATE_SAVE
-#define MACHINE_STATE_SAVE(ID)				\
-  unsigned long int ms_flags, ms_saveret;		\
-  asm volatile("ta	0x20\n\t"			\
-	       "mov	%%g1, %0\n\t"			\
-	       "mov	%%g2, %1\n\t"			\
-	       : "=r" (ms_flags), "=r" (ms_saveret));
-
-#undef MACHINE_STATE_RESTORE
-#define MACHINE_STATE_RESTORE(ID)			\
-  asm volatile("mov	%0, %%g1\n\t"			\
-	       "mov	%1, %%g2\n\t"			\
-	       "ta	0x21\n\t"			\
-	       : /* no outputs */			\
-	       : "r" (ms_flags), "r" (ms_saveret));
-
diff --git a/gcc/config/sparc/sp64-aout.h b/gcc/config/sparc/sp64-aout.h
deleted file mode 100755
index e3056df..0000000
--- a/gcc/config/sparc/sp64-aout.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SPARC64, a.out.
-   Copyright (C) 1994, 1996, 1997, 1998  Free Software Foundation, Inc.
-   Contributed by Doug Evans, dje@cygnus.com.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sparc/sparc.h"
-#include "aoutos.h"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (sparc64-aout)")
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT \
-  (MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
-   + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS)
-
-/* The only code model supported is Medium/Low.  */
-#undef SPARC_DEFAULT_CMODEL
-#define SPARC_DEFAULT_CMODEL CM_MEDLOW
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -Acpu(sparc) -Amachine(sparc)"
diff --git a/gcc/config/sparc/sp64-elf.h b/gcc/config/sparc/sp64-elf.h
deleted file mode 100755
index a1e4ef0..0000000
--- a/gcc/config/sparc/sp64-elf.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SPARC64, ELF.
-   Copyright (C) 1994, 1995, 1996, 1997, 1998  Free Software Foundation, Inc.
-   Contributed by Doug Evans, dje@cygnus.com.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* ??? We're taking the scheme of including another file and then overriding
-   the values we don't like a bit too far here.  The alternative is to more or
-   less duplicate all of svr4.h, sparc/sysv4.h, and sparc/sol2.h here
-   (suitably cleaned up).  */
-
-#include "sparc/sol2.h"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (sparc64-elf)")
-
-/* A 64 bit v9 compiler in a Medium/Anywhere code model environment.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT \
-(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
- + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS)
-
-#undef SPARC_DEFAULT_CMODEL
-#define SPARC_DEFAULT_CMODEL CM_EMBMEDANY
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -D__ELF__ -Acpu(sparc) -Amachine(sparc)"
-
-/* __svr4__ is used by the C library (FIXME) */
-#undef CPP_SUBTARGET_SPEC
-#define CPP_SUBTARGET_SPEC "-D__svr4__"
-
-#undef MD_EXEC_PREFIX
-#undef MD_STARTFILE_PREFIX
-
-#undef ASM_SPEC
-#define ASM_SPEC "\
-%{v:-V} -s %{fpic:-K PIC} %{fPIC:-K PIC} \
-%{mlittle-endian:-EL} \
-%(asm_cpu) %(asm_arch) \
-"
-
-/* This is taken from sol2.h.  */
-#undef LINK_SPEC
-#define LINK_SPEC "\
-%{v:-V} \
-%{mlittle-endian:-EL} \
-"
-
-/* We need something a little simpler for the embedded environment.
-   Profiling doesn't really work yet so we just copy the default.  */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "\
-%{!shared:%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}} \
-crtbegin.o%s \
-"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s"
-
-/* Use the default (for now).  */
-#undef LIB_SPEC
-
-/* V9 chips can handle either endianness.  */
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{"big-endian", -MASK_LITTLE_ENDIAN}, \
-{"little-endian", MASK_LITTLE_ENDIAN},
-
-#undef BYTES_BIG_ENDIAN
-#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
-
-#undef WORDS_BIG_ENDIAN
-#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
-
-/* ??? This should be 32 bits for v9 but what can we do?  */
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
-
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 128
-
-/* The medium/anywhere code model practically requires us to put jump tables
-   in the text section as gcc is unable to distinguish LABEL_REF's of jump
-   tables from other label refs (when we need to).  */
-/* But we now defer the tables to the end of the function, so we make
-   this 0 to not confuse the branch shortening code.  */
-#undef JUMP_TABLES_IN_TEXT_SECTION
-#define JUMP_TABLES_IN_TEXT_SECTION 0
-
-/* System V Release 4 uses DWARF debugging info.
-   GDB doesn't support 64 bit stabs yet and the desired debug format is DWARF
-   anyway so it is the default.  */
-
-#define DWARF_DEBUGGING_INFO
-#define DWARF2_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-/* Stabs doesn't use this, and it confuses a simulator.  */
-/* ??? Need to see what DWARF needs, if anything.  */
-#undef ASM_IDENTIFY_GCC
-#define ASM_IDENTIFY_GCC(FILE)
-
-/* Define the names of various pseudo-ops used by the Sparc/svr4 assembler.
-   ??? If ints are 64 bits then UNALIGNED_INT_ASM_OP (defined elsewhere) is
-   misnamed.  These should all refer to explicit sizes (half/word/xword?),
-   anything other than short/int/long/etc.  */
-
-#define UNALIGNED_LONGLONG_ASM_OP	".uaxword"
-
-/* DWARF stuff.  */
-
-#define ASM_OUTPUT_DWARF_ADDR(FILE, LABEL) \
-do {								\
-  fprintf ((FILE), "\t%s\t", UNALIGNED_LONGLONG_ASM_OP);	\
-  assemble_name ((FILE), (LABEL));				\
-  fprintf ((FILE), "\n");					\
-} while (0)
-
-#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, RTX) \
-do {								\
-  fprintf ((FILE), "\t%s\t", UNALIGNED_LONGLONG_ASM_OP);	\
-  output_addr_const ((FILE), (RTX));				\
-  fputc ('\n', (FILE));						\
-} while (0)
-
-#define ASM_OUTPUT_DWARF2_ADDR_CONST(FILE, ADDR) \
-  fprintf ((FILE), "\t%s\t%s", UNALIGNED_LONGLONG_ASM_OP, (ADDR))
-
-/* ??? Not sure if this should be 4 or 8 bytes.  4 works for now.  */
-#define ASM_OUTPUT_DWARF_REF(FILE, LABEL) \
-do {								\
-  fprintf ((FILE), "\t%s\t", UNALIGNED_INT_ASM_OP);		\
-  assemble_name ((FILE), (LABEL));				\
-  fprintf ((FILE), "\n");					\
-} while (0)
diff --git a/gcc/config/sparc/sp64-elf_020422.h b/gcc/config/sparc/sp64-elf_020422.h
deleted file mode 100755
index 4e993dd..0000000
--- a/gcc/config/sparc/sp64-elf_020422.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SPARC64, ELF.
-   Copyright (C) 1994, 1995, 1996, 1997, 1998, 2001  Free Software Foundation, Inc.
-   Contributed by Doug Evans, dje@cygnus.com.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* ??? We're taking the scheme of including another file and then overriding
-   the values we don't like a bit too far here.  The alternative is to more or
-   less duplicate all of svr4.h, sparc/sysv4.h, and sparc/sol2.h here
-   (suitably cleaned up).  */
-
-#include "sparc/sol2.h"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (sparc64-elf)")
-
-/* A 64 bit v9 compiler in a Medium/Anywhere code model environment.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT \
-(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
- + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS)
-
-#undef SPARC_DEFAULT_CMODEL
-#define SPARC_DEFAULT_CMODEL CM_EMBMEDANY
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -D__ELF__ -Acpu(sparc) -Amachine(sparc)"
-
-/* __svr4__ is used by the C library (FIXME) */
-#undef CPP_SUBTARGET_SPEC
-#define CPP_SUBTARGET_SPEC "-D__svr4__"
-
-#undef MD_EXEC_PREFIX
-#undef MD_STARTFILE_PREFIX
-
-#undef ASM_SPEC
-#define ASM_SPEC "\
-%{v:-V} -s %{fpic:-K PIC} %{fPIC:-K PIC} \
-%{mlittle-endian:-EL} \
-%(asm_cpu) %(asm_arch) \
-"
-
-/* This is taken from sol2.h.  */
-#undef LINK_SPEC
-#define LINK_SPEC "\
-%{v:-V} \
-%{mlittle-endian:-EL} \
-"
-
-/* We need something a little simpler for the embedded environment.
-   Profiling doesn't really work yet so we just copy the default.  */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "\
-%{!shared:%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}} \
-crtbegin.o%s \
-"
-
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s"
-
-/* Use the default (for now).  */
-#undef LIB_SPEC
-
-/* V9 chips can handle either endianness.  */
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{"big-endian", -MASK_LITTLE_ENDIAN}, \
-{"little-endian", MASK_LITTLE_ENDIAN},
-
-#undef BYTES_BIG_ENDIAN
-#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
-
-#undef WORDS_BIG_ENDIAN
-#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
-
-/* ??? This should be 32 bits for v9 but what can we do?  */
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "short unsigned int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 16
-
-#undef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE 128
-
-/* The medium/anywhere code model practically requires us to put jump tables
-   in the text section as gcc is unable to distinguish LABEL_REF's of jump
-   tables from other label refs (when we need to).  */
-/* But we now defer the tables to the end of the function, so we make
-   this 0 to not confuse the branch shortening code.  */
-#undef JUMP_TABLES_IN_TEXT_SECTION
-#define JUMP_TABLES_IN_TEXT_SECTION 0
-
-/* System V Release 4 uses DWARF debugging info.
-   GDB doesn't support 64 bit stabs yet and the desired debug format is DWARF
-   anyway so it is the default.  */
-
-#define DWARF_DEBUGGING_INFO
-#define DWARF2_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-/* Stabs doesn't use this, and it confuses a simulator.  */
-/* ??? Need to see what DWARF needs, if anything.  */
-#undef ASM_IDENTIFY_GCC
-#define ASM_IDENTIFY_GCC(FILE)
-
-/* Define the names of various pseudo-ops used by the Sparc/svr4 assembler.
-   ??? If ints are 64 bits then UNALIGNED_INT_ASM_OP (defined elsewhere) is
-   misnamed.  These should all refer to explicit sizes (half/word/xword?),
-   anything other than short/int/long/etc.  */
-
-#define UNALIGNED_LONGLONG_ASM_OP	".uaxword"
-
-/* DWARF stuff.  */
-
-#define ASM_OUTPUT_DWARF_ADDR(FILE, LABEL) \
-do {								\
-  fprintf ((FILE), "\t%s\t", UNALIGNED_LONGLONG_ASM_OP);	\
-  assemble_name ((FILE), (LABEL));				\
-  fprintf ((FILE), "\n");					\
-} while (0)
-
-#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, RTX) \
-do {								\
-  fprintf ((FILE), "\t%s\t", UNALIGNED_LONGLONG_ASM_OP);	\
-  output_addr_const ((FILE), (RTX));				\
-  fputc ('\n', (FILE));						\
-} while (0)
-
-/* ??? Not sure if this should be 4 or 8 bytes.  4 works for now.  */
-#define ASM_OUTPUT_DWARF_REF(FILE, LABEL) \
-do {								\
-  fprintf ((FILE), "\t%s\t", UNALIGNED_INT_ASM_OP);		\
-  assemble_name ((FILE), (LABEL));				\
-  fprintf ((FILE), "\n");					\
-} while (0)
diff --git a/gcc/config/sparc/sp86x-aout.h b/gcc/config/sparc/sp86x-aout.h
deleted file mode 100755
index 0860f8c..0000000
--- a/gcc/config/sparc/sp86x-aout.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Definitions of target machine for GNU compiler, for sparclite 86x w/o FPU.
-   Copyright (C) 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sparc/sparc.h"
-
-#define HAVE_ATEXIT
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -Dsparclite86x -Acpu(sparc) -Amachine(sparc)"
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (sparclite 86x)");
-
-/* Enable sparclite, app-regs and epilogue options.  Do not enable the fpu.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_SPARCLITE + MASK_APP_REGS + MASK_EPILOGUE)
-
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{"big-endian", -MASK_LITTLE_ENDIAN},		\
-{"little-endian", MASK_LITTLE_ENDIAN},		
-
-#undef ASM_SPEC
-#define ASM_SPEC "%{v:-v} %{mlittle-endian-data:--little-endian-data} %(asm_cpu)"
-
-/* US Software GOFAST library support.  */
-#include "gofast.h"
-#undef INIT_SUBTARGET_OPTABS
-#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS
-
-#undef LINK_SPEC
-#define LINK_SPEC "%{v:-V}"
-
-#undef BYTES_BIG_ENDIAN
-#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN_DATA)
-#undef WORDS_BIG_ENDIAN
-#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN_DATA)
-
-#define TARGET_LITTLE_ENDIAN_DATA (target_flags & MASK_LITTLE_ENDIAN)
-#undef  SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-    { "little-endian-data",              MASK_LITTLE_ENDIAN },     
diff --git a/gcc/config/sparc/sp86x-elf.h b/gcc/config/sparc/sp86x-elf.h
deleted file mode 100755
index d734b85..0000000
--- a/gcc/config/sparc/sp86x-elf.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Definitions of target machine for GNU compiler, for sparclite 86x w/o FPU.
-   Copyright (C) 1998 Free Software Foundation, Inc.
-   Contributed by Stan Cox (scox@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sparc/elf.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -Dsparclite86x -Acpu(sparc) -Amachine(sparc)"
-
-/* Default to dwarf2 in ELF.  */
-
-#define DWARF_DEBUGGING_INFO
-#define DWARF2_DEBUGGING_INFO
-
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (sparclite 86x)");
-
-/* Enable sparclite, app-regs and epilogue options.  Do not enable the fpu.  */
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_SPARCLITE + MASK_APP_REGS + MASK_EPILOGUE)
-
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{"big-endian", -MASK_LITTLE_ENDIAN},		\
-{"little-endian", MASK_LITTLE_ENDIAN},		
-
-#undef ASM_SPEC
-#define ASM_SPEC "%{v:-V} %{mlittle-endian-data:--little-endian-data} %(asm_cpu)"
-
-/* US Software GOFAST library support.  */
-#include "gofast.h"
-#undef INIT_SUBTARGET_OPTABS
-#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS      
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "crti.o%s crtbegin.o%s"
-
-#undef LINK_SPEC
-#define LINK_SPEC "%{v:-V} %{mlittle-endian-data:-EL}"
-
-#undef BYTES_BIG_ENDIAN
-#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN_DATA)
-#undef WORDS_BIG_ENDIAN
-#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN_DATA)
-
-/* Use __main method of constructor invocation */
-#undef INIT_SECTION_ASM_OP
-
-#define TARGET_LITTLE_ENDIAN_DATA (target_flags & MASK_LITTLE_ENDIAN)
-#undef  SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-    { "little-endian-data",              MASK_LITTLE_ENDIAN },     
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
deleted file mode 100755
index 5ad6620..0000000
--- a/gcc/config/sparc/sparc.c
+++ /dev/null
@@ -1,7532 +0,0 @@
-/* Subroutines for insn-output.c for Sun SPARC.
-   Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@cygnus.com)
-   64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
-   at Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include "system.h"
-#include "tree.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "expr.h"
-#include "recog.h"
-#include "toplev.h"
-
-/* 1 if the caller has placed an "unimp" insn immediately after the call.
-   This is used in v8 code when calling a function that returns a structure.
-   v9 doesn't have this.  Be careful to have this test be the same as that
-   used on the call.  */
-
-#define SKIP_CALLERS_UNIMP_P  \
-(!TARGET_ARCH64 && current_function_returns_struct			\
- && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl)))	\
- && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))	\
-     == INTEGER_CST))
-
-/* Global variables for machine-dependent things.  */
-
-/* Size of frame.  Need to know this to emit return insns from leaf procedures.
-   ACTUAL_FSIZE is set by compute_frame_size() which is called during the
-   reload pass.  This is important as the value is later used in insn
-   scheduling (to see what can go in a delay slot).
-   APPARENT_FSIZE is the size of the stack less the register save area and less
-   the outgoing argument area.  It is used when saving call preserved regs.  */
-static int apparent_fsize;
-static int actual_fsize;
-
-/* Save the operands last given to a compare for use when we
-   generate a scc or bcc insn.  */
-
-rtx sparc_compare_op0, sparc_compare_op1;
-
-/* We may need an epilogue if we spill too many registers.
-   If this is non-zero, then we branch here for the epilogue.  */
-static rtx leaf_label;
-
-#ifdef LEAF_REGISTERS
-
-/* Vector to say how input registers are mapped to output
-   registers.  FRAME_POINTER_REGNUM cannot be remapped by
-   this function to eliminate it.  You must use -fomit-frame-pointer
-   to get that.  */
-char leaf_reg_remap[] =
-{ 0, 1, 2, 3, 4, 5, 6, 7,
-  -1, -1, -1, -1, -1, -1, 14, -1,
-  -1, -1, -1, -1, -1, -1, -1, -1,
-  8, 9, 10, 11, 12, 13, -1, 15,
-
-  32, 33, 34, 35, 36, 37, 38, 39,
-  40, 41, 42, 43, 44, 45, 46, 47,
-  48, 49, 50, 51, 52, 53, 54, 55,
-  56, 57, 58, 59, 60, 61, 62, 63,
-  64, 65, 66, 67, 68, 69, 70, 71,
-  72, 73, 74, 75, 76, 77, 78, 79,
-  80, 81, 82, 83, 84, 85, 86, 87,
-  88, 89, 90, 91, 92, 93, 94, 95,
-  96, 97, 98, 99, 100};
-
-#endif
-
-/* Name of where we pretend to think the frame pointer points.
-   Normally, this is "%fp", but if we are in a leaf procedure,
-   this is "%sp+something".  We record "something" separately as it may be
-   too big for reg+constant addressing.  */
-
-static char *frame_base_name;
-static int frame_base_offset;
-
-static rtx pic_setup_code	PROTO((void));
-static void sparc_init_modes	PROTO((void));
-static int save_regs		PROTO((FILE *, int, int, char *,
-				       int, int, int));
-static int restore_regs		PROTO((FILE *, int, int, char *, int, int));
-static void build_big_number	PROTO((FILE *, int, char *));
-static int function_arg_slotno	PROTO((const CUMULATIVE_ARGS *,
-				       enum machine_mode, tree, int, int,
-				       int *, int *));
-
-static int supersparc_adjust_cost PROTO((rtx, rtx, rtx, int));
-static int hypersparc_adjust_cost PROTO((rtx, rtx, rtx, int));
-static int ultrasparc_adjust_cost PROTO((rtx, rtx, rtx, int));
-
-static void sparc_output_addr_vec PROTO((rtx));
-static void sparc_output_addr_diff_vec PROTO((rtx));
-static void sparc_output_deferred_case_vectors PROTO((void));
-
-
-#ifdef DWARF2_DEBUGGING_INFO
-extern char *dwarf2out_cfi_label ();
-#endif
-
-/* Option handling.  */
-
-/* Code model option as passed by user.  */
-char *sparc_cmodel_string;
-/* Parsed value.  */
-enum cmodel sparc_cmodel;
-
-/* Record alignment options as passed by user.  */
-char *sparc_align_loops_string;
-char *sparc_align_jumps_string;
-char *sparc_align_funcs_string;
-
-/* Parsed values, as a power of two.  */
-int sparc_align_loops;
-int sparc_align_jumps;
-int sparc_align_funcs;
-
-struct sparc_cpu_select sparc_select[] =
-{
-  /* switch	name,		tune	arch */
-  { (char *)0,	"default",	1,	1 },
-  { (char *)0,	"-mcpu=",	1,	1 },
-  { (char *)0,	"-mtune=",	1,	0 },
-  { 0, 0, 0, 0 }
-};
-
-/* CPU type.  This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx.  */
-enum processor_type sparc_cpu;
-
-/* Validate and override various options, and do some machine dependent
-   initialization.  */
-
-void
-sparc_override_options ()
-{
-  static struct code_model {
-    char *name;
-    int value;
-  } cmodels[] = {
-    { "32", CM_32 },
-    { "medlow", CM_MEDLOW },
-    { "medmid", CM_MEDMID },
-    { "medany", CM_MEDANY },
-    { "embmedany", CM_EMBMEDANY },
-    { 0, 0 }
-  };
-  struct code_model *cmodel;
-  /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=.  */
-  static struct cpu_default {
-    int cpu;
-    char *name;
-  } cpu_default[] = {
-    /* There must be one entry here for each TARGET_CPU value.  */
-    { TARGET_CPU_sparc, "cypress" },
-    { TARGET_CPU_sparclet, "tsc701" },
-    { TARGET_CPU_sparclite, "f930" },
-    { TARGET_CPU_v8, "v8" },
-    { TARGET_CPU_hypersparc, "hypersparc" },
-    { TARGET_CPU_sparclite86x, "sparclite86x" },
-    { TARGET_CPU_supersparc, "supersparc" },
-    { TARGET_CPU_v9, "v9" },
-    { TARGET_CPU_ultrasparc, "ultrasparc" },
-    { 0, 0 }
-  };
-  struct cpu_default *def;
-  /* Table of values for -m{cpu,tune}=.  */
-  static struct cpu_table {
-    char *name;
-    enum processor_type processor;
-    int disable;
-    int enable;
-  } cpu_table[] = {
-    { "v7",         PROCESSOR_V7, MASK_ISA, 0 },
-    { "cypress",    PROCESSOR_CYPRESS, MASK_ISA, 0 },
-    { "v8",         PROCESSOR_V8, MASK_ISA, MASK_V8 },
-    /* TI TMS390Z55 supersparc */
-    { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
-    { "sparclite",  PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
-    /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
-       The Fujitsu MB86934 is the recent sparclite chip, with an fpu.  */
-    { "f930",       PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
-    { "f934",       PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
-    { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
-    { "sparclite86x",  PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
-      MASK_SPARCLITE },
-    { "sparclet",   PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
-    /* TEMIC sparclet */
-    { "tsc701",     PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
-    { "v9",         PROCESSOR_V9, MASK_ISA, MASK_V9 },
-    /* TI ultrasparc */
-    { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 },
-    { 0, 0, 0, 0 }
-  };
-  struct cpu_table *cpu;
-  struct sparc_cpu_select *sel;
-  int fpu;
-  
-#ifndef SPARC_BI_ARCH
-  /* Check for unsupported architecture size.  */
-  if (! TARGET_64BIT != DEFAULT_ARCH32_P)
-    {
-      error ("%s is not supported by this configuration",
-	     DEFAULT_ARCH32_P ? "-m64" : "-m32");
-    }
-#endif
-
-  /* At the moment we don't allow different pointer size and architecture */
-  if (! TARGET_64BIT != ! TARGET_PTR64)
-    {
-      error ("-mptr%d not allowed on -m%d",
-      	     TARGET_PTR64 ? 64 : 32, TARGET_64BIT ? 64 : 32);
-      if (TARGET_64BIT)
-    	target_flags |= MASK_PTR64;
-      else
-        target_flags &= ~MASK_PTR64;
-    }
-
-  /* Code model selection.  */
-  sparc_cmodel = SPARC_DEFAULT_CMODEL;
-  
-#ifdef SPARC_BI_ARCH
-  if (TARGET_ARCH32)
-    sparc_cmodel = CM_32;
-#endif
-
-  if (sparc_cmodel_string != NULL)
-    {
-      if (TARGET_ARCH64)
-	{
-	  for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
-	    if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
-	      break;
-	  if (cmodel->name == NULL)
-	    error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
-	  else
-	    sparc_cmodel = cmodel->value;
-	}
-      else
-	error ("-mcmodel= is not supported on 32 bit systems");
-    }
-
-  fpu = TARGET_FPU; /* save current -mfpu status */
-
-  /* Set the default CPU.  */
-  for (def = &cpu_default[0]; def->name; ++def)
-    if (def->cpu == TARGET_CPU_DEFAULT)
-      break;
-  if (! def->name)
-    abort ();
-  sparc_select[0].string = def->name;
-
-  for (sel = &sparc_select[0]; sel->name; ++sel)
-    {
-      if (sel->string)
-	{
-	  for (cpu = &cpu_table[0]; cpu->name; ++cpu)
-	    if (! strcmp (sel->string, cpu->name))
-	      {
-		if (sel->set_tune_p)
-		  sparc_cpu = cpu->processor;
-
-		if (sel->set_arch_p)
-		  {
-		    target_flags &= ~cpu->disable;
-		    target_flags |= cpu->enable;
-		  }
-		break;
-	      }
-
-	  if (! cpu->name)
-	    error ("bad value (%s) for %s switch", sel->string, sel->name);
-	}
-    }
-
-  /* If -mfpu or -mno-fpu was explicitly used, don't override with
-     the processor default.  */
-  if (TARGET_FPU_SET)
-    target_flags = (target_flags & ~MASK_FPU) | fpu;
-
-  /* Use the deprecated v8 insns for sparc64 in 32 bit mode.  */
-  if (TARGET_V9 && TARGET_ARCH32)
-    target_flags |= MASK_DEPRECATED_V8_INSNS;
-
-  /* V8PLUS requires V9, makes no sense in 64 bit mode.  */
-  if (! TARGET_V9 || TARGET_ARCH64)
-    target_flags &= ~MASK_V8PLUS;
-
-  /* Don't use stack biasing in 32 bit mode.  */
-  if (TARGET_ARCH32)
-    target_flags &= ~MASK_STACK_BIAS;
-    
-  /* Don't allow -mvis if FPU is disabled.  */
-  if (! TARGET_FPU)
-    target_flags &= ~MASK_VIS;
-
-  /* Validate -malign-loops= value, or provide default.  */
-  if (sparc_align_loops_string)
-    {
-      sparc_align_loops = exact_log2 (atoi (sparc_align_loops_string));
-      if (sparc_align_loops < 2 || sparc_align_loops > 7)
-	fatal ("-malign-loops=%s is not between 4 and 128 or is not a power of two",
-	       sparc_align_loops_string);
-    }
-  else
-    {
-      /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
-	 its 0.  This sounds a bit kludgey.  */
-      sparc_align_loops = 0;
-    }
-
-  /* Validate -malign-jumps= value, or provide default.  */
-  if (sparc_align_jumps_string)
-    {
-      sparc_align_jumps = exact_log2 (atoi (sparc_align_jumps_string));
-      if (sparc_align_jumps < 2 || sparc_align_loops > 7)
-	fatal ("-malign-jumps=%s is not between 4 and 128 or is not a power of two",
-	       sparc_align_jumps_string);
-    }
-  else
-    {
-      /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
-	 its 0.  This sounds a bit kludgey.  */
-      sparc_align_jumps = 0;
-    }
-
-  /* Validate -malign-functions= value, or provide default. */
-  if (sparc_align_funcs_string)
-    {
-      sparc_align_funcs = exact_log2 (atoi (sparc_align_funcs_string));
-      if (sparc_align_funcs < 2 || sparc_align_loops > 7)
-	fatal ("-malign-functions=%s is not between 4 and 128 or is not a power of two",
-	       sparc_align_funcs_string);
-    }
-  else
-    sparc_align_funcs = DEFAULT_SPARC_ALIGN_FUNCS;
-
-  /* Validate PCC_STRUCT_RETURN.  */
-  if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
-    flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
-
-  /* Do various machine dependent initializations.  */
-  sparc_init_modes ();
-}
-
-/* Miscellaneous utilities.  */
-
-/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
-   or branch on register contents instructions.  */
-
-int
-v9_regcmp_p (code)
-     enum rtx_code code;
-{
-  return (code == EQ || code == NE || code == GE || code == LT
-	  || code == LE || code == GT);
-}
-
-
-/* Operand constraints.  */
-
-/* Return non-zero only if OP is a register of mode MODE,
-   or const0_rtx.  Don't allow const0_rtx if TARGET_LIVE_G0 because
-   %g0 may contain anything.  */
-
-int
-reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (register_operand (op, mode))
-    return 1;
-  if (TARGET_LIVE_G0)
-    return 0;
-  if (op == const0_rtx)
-    return 1;
-  if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
-      && CONST_DOUBLE_HIGH (op) == 0
-      && CONST_DOUBLE_LOW (op) == 0)
-    return 1;
-  if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
-      && GET_CODE (op) == CONST_DOUBLE
-      && fp_zero_operand (op))
-    return 1;
-  return 0;
-}
-
-/* Nonzero if OP is a floating point value with value 0.0.  */
-
-int
-fp_zero_operand (op)
-     rtx op;
-{
-  REAL_VALUE_TYPE r;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, op);
-  return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r));
-}
-
-/* Nonzero if OP is an integer register.  */
-
-int
-intreg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (register_operand (op, SImode)
-	  || (TARGET_ARCH64 && register_operand (op, DImode)));
-}
-
-/* Nonzero if OP is a floating point condition code register.  */
-
-int
-fcc_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  /* This can happen when recog is called from combine.  Op may be a MEM.
-     Fail instead of calling abort in this case.  */
-  if (GET_CODE (op) != REG)
-    return 0;
-
-  if (mode != VOIDmode && mode != GET_MODE (op))
-    return 0;
-  if (mode == VOIDmode
-      && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
-    return 0;
-
-#if 0	/* ??? ==> 1 when %fcc0-3 are pseudos first.  See gen_compare_reg().  */
-  if (reg_renumber == 0)
-    return REGNO (op) >= FIRST_PSEUDO_REGISTER;
-  return REGNO_OK_FOR_CCFP_P (REGNO (op));
-#else
-  return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
-#endif
-}
-
-/* Nonzero if OP is an integer or floating point condition code register.  */
-
-int
-icc_or_fcc_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
-    {
-      if (mode != VOIDmode && mode != GET_MODE (op))
-	return 0;
-      if (mode == VOIDmode
-	  && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
-	return 0;
-      return 1;
-    }
-
-  return fcc_reg_operand (op, mode);
-}
-
-/* Nonzero if OP can appear as the dest of a RESTORE insn.  */
-int
-restore_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == REG && GET_MODE (op) == mode
-	  && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
-}
-
-/* Call insn on SPARC can take a PC-relative constant address, or any regular
-   memory address.  */
-
-int
-call_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != MEM)
-    abort ();
-  op = XEXP (op, 0);
-  return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
-}
-
-int
-call_operand_address (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
-}
-
-/* Returns 1 if OP is either a symbol reference or a sum of a symbol
-   reference and a constant.  */
-
-int
-symbolic_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return 1;
-
-    case CONST:
-      op = XEXP (op, 0);
-      return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
-	       || GET_CODE (XEXP (op, 0)) == LABEL_REF)
-	      && GET_CODE (XEXP (op, 1)) == CONST_INT);
-
-      /* ??? This clause seems to be irrelevant.  */
-    case CONST_DOUBLE:
-      return GET_MODE (op) == mode;
-
-    default:
-      return 0;
-    }
-}
-
-/* Return truth value of statement that OP is a symbolic memory
-   operand of mode MODE.  */
-
-int
-symbolic_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-  if (GET_CODE (op) != MEM)
-    return 0;
-  op = XEXP (op, 0);
-  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
-	  || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
-}
-
-/* Return truth value of statement that OP is a LABEL_REF of mode MODE.  */
-
-int
-label_ref_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != LABEL_REF)
-    return 0;
-  if (GET_MODE (op) != mode)
-    return 0;
-  return 1;
-}
-
-/* Return 1 if the operand is an argument used in generating pic references
-   in either the medium/low or medium/anywhere code models of sparc64.  */
-
-int
-sp64_medium_pic_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  /* Check for (const (minus (symbol_ref:GOT)
-                             (const (minus (label) (pc))))).  */
-  if (GET_CODE (op) != CONST)
-    return 0;
-  op = XEXP (op, 0);
-  if (GET_CODE (op) != MINUS)
-    return 0;
-  if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
-    return 0;
-  /* ??? Ensure symbol is GOT.  */
-  if (GET_CODE (XEXP (op, 1)) != CONST)
-    return 0;
-  if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
-    return 0;
-  return 1;
-}
-
-/* Return 1 if the operand is a data segment reference.  This includes
-   the readonly data segment, or in other words anything but the text segment.
-   This is needed in the medium/anywhere code model on v9.  These values
-   are accessed with EMBMEDANY_BASE_REG.  */
-
-int
-data_segment_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  switch (GET_CODE (op))
-    {
-    case SYMBOL_REF :
-      return ! SYMBOL_REF_FLAG (op);
-    case PLUS :
-      /* Assume canonical format of symbol + constant.
-	 Fall through.  */
-    case CONST :
-      return data_segment_operand (XEXP (op, 0));
-    default :
-      return 0;
-    }
-}
-
-/* Return 1 if the operand is a text segment reference.
-   This is needed in the medium/anywhere code model on v9.  */
-
-int
-text_segment_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  switch (GET_CODE (op))
-    {
-    case LABEL_REF :
-      return 1;
-    case SYMBOL_REF :
-      return SYMBOL_REF_FLAG (op);
-    case PLUS :
-      /* Assume canonical format of symbol + constant.
-	 Fall through.  */
-    case CONST :
-      return text_segment_operand (XEXP (op, 0));
-    default :
-      return 0;
-    }
-}
-
-/* Return 1 if the operand is either a register or a memory operand that is
-   not symbolic.  */
-
-int
-reg_or_nonsymb_mem_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
-{
-  if (register_operand (op, mode))
-    return 1;
-
-  if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
-    return 1;
-
-  return 0;
-}
-
-int
-splittable_symbolic_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) != MEM)
-    return 0;
-  if (! symbolic_operand (XEXP (op, 0), Pmode))
-    return 0;
-  return 1;
-}
-
-int
-splittable_immediate_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) != MEM)
-    return 0;
-  if (! immediate_operand (XEXP (op, 0), Pmode))
-    return 0;
-  return 1;
-}
-
-/* Return truth value of whether OP is EQ or NE.  */
-
-int
-eq_or_neq (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
-}
-
-/* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
-   or LTU for non-floating-point.  We handle those specially.  */
-
-int
-normal_comp_operator (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  enum rtx_code code = GET_CODE (op);
-
-  if (GET_RTX_CLASS (code) != '<')
-    return 0;
-
-  if (GET_MODE (XEXP (op, 0)) == CCFPmode
-      || GET_MODE (XEXP (op, 0)) == CCFPEmode)
-    return 1;
-
-  return (code != NE && code != EQ && code != GEU && code != LTU);
-}
-
-/* Return 1 if this is a comparison operator.  This allows the use of
-   MATCH_OPERATOR to recognize all the branch insns.  */
-
-int
-noov_compare_op (op, mode)
-    register rtx op;
-    enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  enum rtx_code code = GET_CODE (op);
-
-  if (GET_RTX_CLASS (code) != '<')
-    return 0;
-
-  if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
-    /* These are the only branches which work with CC_NOOVmode.  */
-    return (code == EQ || code == NE || code == GE || code == LT);
-  return 1;
-}
-
-/* Nonzero if OP is a comparison operator suitable for use in v9
-   conditional move or branch on register contents instructions.  */
-
-int
-v9_regcmp_op (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  enum rtx_code code = GET_CODE (op);
-
-  if (GET_RTX_CLASS (code) != '<')
-    return 0;
-
-  return v9_regcmp_p (code);
-}
-
-/* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation.  */
-
-int
-extend_op (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
-}
-
-/* Return nonzero if OP is an operator of mode MODE which can set
-   the condition codes explicitly.  We do not include PLUS and MINUS
-   because these require CC_NOOVmode, which we handle explicitly.  */
-
-int
-cc_arithop (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  if (GET_CODE (op) == AND
-      || GET_CODE (op) == IOR
-      || GET_CODE (op) == XOR)
-    return 1;
-
-  return 0;
-}
-
-/* Return nonzero if OP is an operator of mode MODE which can bitwise
-   complement its second operand and set the condition codes explicitly.  */
-
-int
-cc_arithopn (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  /* XOR is not here because combine canonicalizes (xor (not ...) ...)
-     and (xor ... (not ...)) to (not (xor ...)).   */
-  return (GET_CODE (op) == AND
-	  || GET_CODE (op) == IOR);
-}
-
-/* Return true if OP is a register, or is a CONST_INT that can fit in a
-   signed 13 bit immediate field.  This is an acceptable SImode operand for
-   most 3 address instructions.  */
-
-int
-arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int val;
-  if (register_operand (op, mode))
-    return 1;
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  val = INTVAL (op) & 0xffffffff;
-  return SPARC_SIMM13_P (val);
-}
-
-/* Return true if OP is a constant 4096  */
-
-int
-arith_4096_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  int val;
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-  val = INTVAL (op) & 0xffffffff;
-  return val == 4096;
-}
-
-/* Return true if OP is suitable as second operand for add/sub */
-
-int
-arith_add_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return arith_operand (op, mode) || arith_4096_operand (op, mode);
-}
-
-/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
-   immediate field of OR and XOR instructions.  Used for 64-bit
-   constant formation patterns.  */
-int
-const64_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return ((GET_CODE (op) == CONST_INT
-	   && SPARC_SIMM13_P (INTVAL (op)))
-#if HOST_BITS_PER_WIDE_INT != 64
-	  || (GET_CODE (op) == CONST_DOUBLE
-	      && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
-	      && (CONST_DOUBLE_HIGH (op) ==
-		  ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
-		   (HOST_WIDE_INT)0xffffffff : 0)))
-#endif
-	  );
-}
-
-/* The same, but only for sethi instructions.  */
-int
-const64_high_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return ((GET_CODE (op) == CONST_INT
-	   && (INTVAL (op) & 0xfffffc00) != 0
-	   && SPARC_SETHI_P (INTVAL (op))
-#if HOST_BITS_PER_WIDE_INT != 64
-	   /* Must be positive on non-64bit host else the
-	      optimizer is fooled into thinking that sethi
-	      sign extends, even though it does not.  */
-	   && INTVAL (op) >= 0
-#endif
-	   )
-	  || (GET_CODE (op) == CONST_DOUBLE
-	      && CONST_DOUBLE_HIGH (op) == 0
-	      && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
-	      && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
-}
-
-/* Return true if OP is a register, or is a CONST_INT that can fit in a
-   signed 11 bit immediate field.  This is an acceptable SImode operand for
-   the movcc instructions.  */
-
-int
-arith11_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
-}
-
-/* Return true if OP is a register, or is a CONST_INT that can fit in a
-   signed 10 bit immediate field.  This is an acceptable SImode operand for
-   the movrcc instructions.  */
-
-int
-arith10_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
-}
-
-/* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
-   immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
-   immediate field.
-   v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
-   can fit in a 13 bit immediate field.  This is an acceptable DImode operand
-   for most 3 address instructions.  */
-
-int
-arith_double_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
-	  || (! TARGET_ARCH64
-	      && GET_CODE (op) == CONST_DOUBLE
-	      && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
-	      && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
-	  || (TARGET_ARCH64
-	      && GET_CODE (op) == CONST_DOUBLE
-	      && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
-	      && ((CONST_DOUBLE_HIGH (op) == -1
-		   && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
-		  || (CONST_DOUBLE_HIGH (op) == 0
-		      && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
-}
-
-/* Return true if OP is a constant 4096 for DImode on ARCH64 */
-
-int
-arith_double_4096_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (TARGET_ARCH64 &&
-  	  ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
-  	   (GET_CODE (op) == CONST_DOUBLE &&
-  	    CONST_DOUBLE_LOW (op) == 4096 &&
-  	    CONST_DOUBLE_HIGH (op) == 0)));
-}
-
-/* Return true if OP is suitable as second operand for add/sub in DImode */
-
-int
-arith_double_add_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
-}
-
-/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
-   can fit in an 11 bit immediate field.  This is an acceptable DImode
-   operand for the movcc instructions.  */
-/* ??? Replace with arith11_operand?  */
-
-int
-arith11_double_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_DOUBLE
-	      && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
-	      && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
-	      && ((CONST_DOUBLE_HIGH (op) == -1
-		   && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
-		  || (CONST_DOUBLE_HIGH (op) == 0
-		      && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
-	  || (GET_CODE (op) == CONST_INT
-	      && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
-	      && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
-}
-
-/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
-   can fit in an 10 bit immediate field.  This is an acceptable DImode
-   operand for the movrcc instructions.  */
-/* ??? Replace with arith10_operand?  */
-
-int
-arith10_double_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  || (GET_CODE (op) == CONST_DOUBLE
-	      && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
-	      && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
-	      && ((CONST_DOUBLE_HIGH (op) == -1
-		   && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
-		  || (CONST_DOUBLE_HIGH (op) == 0
-		      && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
-	  || (GET_CODE (op) == CONST_INT
-	      && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
-	      && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
-}
-
-/* Return truth value of whether OP is a integer which fits the
-   range constraining immediate operands in most three-address insns,
-   which have a 13 bit immediate field.  */
-
-int
-small_int (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
-}
-
-int
-small_int_or_double (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
-	  || (GET_CODE (op) == CONST_DOUBLE
-	      && CONST_DOUBLE_HIGH (op) == 0
-	      && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
-}
-
-/* Recognize operand values for the umul instruction.  That instruction sign
-   extends immediate values just like all other sparc instructions, but
-   interprets the extended result as an unsigned number.  */
-
-int
-uns_small_int (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-#if HOST_BITS_PER_WIDE_INT > 32
-  /* All allowed constants will fit a CONST_INT.  */
-  return (GET_CODE (op) == CONST_INT
-	  && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
-	      || (INTVAL (op) >= 0xFFFFF000
-                  && INTVAL (op) < 0x100000000)));
-#else
-  return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
-	  || (GET_CODE (op) == CONST_DOUBLE
-	      && CONST_DOUBLE_HIGH (op) == 0
-	      && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
-#endif
-}
-
-int
-uns_arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return register_operand (op, mode) || uns_small_int (op, mode);
-}
-
-/* Return truth value of statement that OP is a call-clobbered register.  */
-int
-clobbered_register (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
-}
-
-/* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns.  */
-
-int
-zero_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return op == const0_rtx;
-}
-
-/* Return 1 if OP is a valid operand for the source of a move insn.  */
-
-int
-input_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  /* If both modes are non-void they must be the same.  */
-  if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
-    return 0;
-
-  /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary.  */
-  if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX)
-    return 1;
-
-  /* Allow any one instruction integer constant, and all CONST_INT
-     variants when we are working in DImode and !arch64.  */
-  if (GET_MODE_CLASS (mode) == MODE_INT
-      && ((GET_CODE (op) == CONST_INT
-	   && ((SPARC_SETHI_P (INTVAL (op))
-		&& (! TARGET_ARCH64
-		    || (INTVAL (op) >= 0)
-		    || mode == SImode))
-	       || SPARC_SIMM13_P (INTVAL (op))
-	       || (mode == DImode
-		   && ! TARGET_ARCH64)))
-	  || (TARGET_ARCH64
-	      && GET_CODE (op) == CONST_DOUBLE
-	      && ((CONST_DOUBLE_HIGH (op) == 0
-		   && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
-		  ||
-#if HOST_BITS_PER_WIDE_INT == 64
-		  (CONST_DOUBLE_HIGH (op) == 0
-		   && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
-#else
-		  (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
-		   && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
-			&& CONST_DOUBLE_HIGH (op) == 0)
-		       || (CONST_DOUBLE_HIGH (op) == -1)))
-#endif
-		  ))))
-    return 1;
-
-  /* If !arch64 and this is a DImode const, allow it so that
-     the splits can be generated.  */
-  if (! TARGET_ARCH64
-      && mode == DImode
-      && GET_CODE (op) == CONST_DOUBLE)
-    return 1;
-
-  if (register_operand (op, mode))
-    return 1;
-
-  /* If this is a SUBREG, look inside so that we handle
-     paradoxical ones.  */
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  /* Check for valid MEM forms.  */
-  if (GET_CODE (op) == MEM)
-    {
-      rtx inside = XEXP (op, 0);
-
-      if (GET_CODE (inside) == LO_SUM)
-	{
-	  /* We can't allow these because all of the splits
-	     (eventually as they trickle down into DFmode
-	     splits) require offsettable memory references.  */
-	  if (! TARGET_V9
-	      && GET_MODE (op) == TFmode)
-	    return 0;
-
-	  return (register_operand (XEXP (inside, 0), Pmode)
-		  && CONSTANT_P (XEXP (inside, 1)));
-	}
-      return memory_address_p (mode, inside);
-    }
-
-  return 0;
-}
-
-
-/* We know it can't be done in one insn when we get here,
-   the movsi expander guarentees this.  */
-void
-sparc_emit_set_const32 (op0, op1)
-     rtx op0;
-     rtx op1;
-{
-  enum machine_mode mode = GET_MODE (op0);
-  rtx temp;
-
-  if (GET_CODE (op1) == CONST_INT)
-    {
-      HOST_WIDE_INT value = INTVAL (op1);
-
-      if (SPARC_SETHI_P (value)
-	  || SPARC_SIMM13_P (value))
-	abort ();
-    }
-
-  /* Full 2-insn decomposition is needed.  */
-  if (reload_in_progress || reload_completed)
-    temp = op0;
-  else
-    temp = gen_reg_rtx (mode);
-
-  if (GET_CODE (op1) == CONST_INT)
-    {
-      /* Emit them as real moves instead of a HIGH/LO_SUM,
-	 this way CSE can see everything and reuse intermediate
-	 values if it wants.  */
-      if (TARGET_ARCH64
-	  && HOST_BITS_PER_WIDE_INT != 64
-	  && (INTVAL (op1) & 0x80000000) != 0)
-	{
-	  emit_insn (gen_rtx_SET (VOIDmode,
-				  temp,
-				  gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx,
-							INTVAL (op1) & 0xfffffc00, 0)));
-	}
-      else
-	{
-	  emit_insn (gen_rtx_SET (VOIDmode,
-				  temp,
-				  GEN_INT (INTVAL (op1) & 0xfffffc00)));
-	}
-      emit_insn (gen_rtx_SET (VOIDmode,
-			      op0,
-			      gen_rtx_IOR (mode,
-					   temp,
-					   GEN_INT (INTVAL (op1) & 0x3ff))));
-    }
-  else
-    {
-      /* A symbol, emit in the traditional way.  */
-      emit_insn (gen_rtx_SET (VOIDmode,
-			      temp,
-			      gen_rtx_HIGH (mode,
-					    op1)));
-      emit_insn (gen_rtx_SET (VOIDmode,
-			      op0,
-			      gen_rtx_LO_SUM (mode,
-					      temp,
-					      op1)));
-
-    }
-}
-
-
-/* Sparc-v9 code-model support. */
-void
-sparc_emit_set_symbolic_const64 (op0, op1, temp1)
-     rtx op0;
-     rtx op1;
-     rtx temp1;
-{
-  switch (sparc_cmodel)
-    {
-    case CM_MEDLOW:
-      /* The range spanned by all instructions in the object is less
-	 than 2^31 bytes (2GB) and the distance from any instruction
-	 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
-	 than 2^31 bytes (2GB).
-
-	 The executable must be in the low 4TB of the virtual address
-	 space.
-
-	 sethi	%hi(symbol), %temp
-	 or	%temp, %lo(symbol), %reg  */
-      emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
-      emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
-      break;
-
-    case CM_MEDMID:
-      /* The range spanned by all instructions in the object is less
-	 than 2^31 bytes (2GB) and the distance from any instruction
-	 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
-	 than 2^31 bytes (2GB).
-
-	 The executable must be in the low 16TB of the virtual address
-	 space.
-
-	 sethi	%h44(symbol), %temp1
-	 or	%temp1, %m44(symbol), %temp2
-	 sllx	%temp2, 12, %temp3
-	 or	%temp3, %l44(symbol), %reg  */
-      emit_insn (gen_seth44 (op0, op1));
-      emit_insn (gen_setm44 (op0, op0, op1));
-      emit_insn (gen_rtx_SET (VOIDmode, temp1,
-			      gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
-      emit_insn (gen_setl44 (op0, temp1, op1));
-      break;
-
-    case CM_MEDANY:
-      /* The range spanned by all instructions in the object is less
-	 than 2^31 bytes (2GB) and the distance from any instruction
-	 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
-	 than 2^31 bytes (2GB).
-
-	 The executable can be placed anywhere in the virtual address
-	 space.
-
-	 sethi	%hh(symbol), %temp1
-	 sethi	%lm(symbol), %temp2
-	 or	%temp1, %hm(symbol), %temp3
-	 or	%temp2, %lo(symbol), %temp4
-	 sllx	%temp3, 32, %temp5
-	 or	%temp4, %temp5, %reg  */
-
-      /* Getting this right wrt. reloading is really tricky.
-	 We _MUST_ have a seperate temporary at this point,
-	 if we don't barf immediately instead of generating
-	 incorrect code.  */
-      if (temp1 == op0)
-	abort ();
-
-      emit_insn (gen_sethh (op0, op1));
-      emit_insn (gen_setlm (temp1, op1));
-      emit_insn (gen_sethm (op0, op0, op1));
-      emit_insn (gen_rtx_SET (VOIDmode, op0,
-			      gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
-      emit_insn (gen_rtx_SET (VOIDmode, op0,
-			      gen_rtx_PLUS (DImode, op0, temp1)));
-      emit_insn (gen_setlo (op0, op0, op1));
-      break;
-
-    case CM_EMBMEDANY:
-      /* Old old old backwards compatibility kruft here.
-	 Essentially it is MEDLOW with a fixed 64-bit
-	 virtual base added to all data segment addresses.
-	 Text-segment stuff is computed like MEDANY, we can't
-	 reuse the code above because the relocation knobs
-	 look different.
-
-	 Data segment:	sethi	%hi(symbol), %temp1
-			or	%temp1, %lo(symbol), %temp2
-			add	%temp2, EMBMEDANY_BASE_REG, %reg
-
-	 Text segment:	sethi	%uhi(symbol), %temp1
-			sethi	%hi(symbol), %temp2
-			or	%temp1, %ulo(symbol), %temp3
-			or	%temp2, %lo(symbol), %temp4
-			sllx	%temp3, 32, %temp5
-			or	%temp4, %temp5, %reg  */
-      if (data_segment_operand (op1, GET_MODE (op1)))
-	{
-	  emit_insn (gen_embmedany_sethi (temp1, op1));
-	  emit_insn (gen_embmedany_brsum (op0, temp1));
-	  emit_insn (gen_embmedany_losum (op0, op0, op1));
-	}
-      else
-	{
-	  /* Getting this right wrt. reloading is really tricky.
-	     We _MUST_ have a seperate temporary at this point,
-	     so we barf immediately instead of generating
-	     incorrect code.  */
-	  if (temp1 == op0)
-	    abort ();
-
-	  emit_insn (gen_embmedany_textuhi (op0, op1));
-	  emit_insn (gen_embmedany_texthi  (temp1, op1));
-	  emit_insn (gen_embmedany_textulo (op0, op0, op1));
-	  emit_insn (gen_rtx_SET (VOIDmode, op0,
-				  gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
-	  emit_insn (gen_rtx_SET (VOIDmode, op0,
-				  gen_rtx_PLUS (DImode, op0, temp1)));
-	  emit_insn (gen_embmedany_textlo  (op0, op0, op1));
-	}
-      break;
-
-    default:
-      abort();
-    }
-}
-
-/* These avoid problems when cross compiling.  If we do not
-   go through all this hair then the optimizer will see
-   invalid REG_EQUAL notes or in some cases none at all.  */
-static void sparc_emit_set_safe_HIGH64 PROTO ((rtx, HOST_WIDE_INT));
-static rtx gen_safe_SET64 PROTO ((rtx, HOST_WIDE_INT));
-static rtx gen_safe_OR64 PROTO ((rtx, HOST_WIDE_INT));
-static rtx gen_safe_XOR64 PROTO ((rtx, HOST_WIDE_INT));
-
-#if HOST_BITS_PER_WIDE_INT == 64
-#define GEN_HIGHINT64(__x)		GEN_INT ((__x) & 0xfffffc00)
-#define GEN_INT64(__x)			GEN_INT (__x)
-#else
-#define GEN_HIGHINT64(__x) \
-	gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
-			      (__x) & 0xfffffc00, 0)
-#define GEN_INT64(__x) \
-	gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
-			      (__x) & 0xffffffff, \
-			      ((__x) & 0x80000000 \
-			       ? 0xffffffff : 0))
-#endif
-
-/* The optimizer is not to assume anything about exactly
-   which bits are set for a HIGH, they are unspecified.
-   Unfortunately this leads to many missed optimizations
-   during CSE.  We mask out the non-HIGH bits, and matches
-   a plain movdi, to alleviate this problem.  */
-static void
-sparc_emit_set_safe_HIGH64 (dest, val)
-     rtx dest;
-     HOST_WIDE_INT val;
-{
-  emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
-}
-
-static rtx
-gen_safe_SET64 (dest, val)
-     rtx dest;
-     HOST_WIDE_INT val;
-{
-  return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
-}
-
-static rtx
-gen_safe_OR64 (src, val)
-     rtx src;
-     HOST_WIDE_INT val;
-{
-  return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
-}
-
-static rtx
-gen_safe_XOR64 (src, val)
-     rtx src;
-     HOST_WIDE_INT val;
-{
-  return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
-}
-
-/* Worker routines for 64-bit constant formation on arch64.
-   One of the key things to be doing in these emissions is
-   to create as many temp REGs as possible.  This makes it
-   possible for half-built constants to be used later when
-   such values are similar to something required later on.
-   Without doing this, the optimizer cannot see such
-   opportunities.  */
-
-static void sparc_emit_set_const64_quick1
-	PROTO((rtx, rtx, unsigned HOST_WIDE_INT, int));
-
-static void
-sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
-  rtx op0;
-  rtx temp;
-  unsigned HOST_WIDE_INT low_bits;
-  int is_neg;
-{
-  unsigned HOST_WIDE_INT high_bits;
-
-  if (is_neg)
-    high_bits = (~low_bits) & 0xffffffff;
-  else
-    high_bits = low_bits;
-
-  sparc_emit_set_safe_HIGH64 (temp, high_bits);
-  if (!is_neg)
-    {
-      emit_insn (gen_rtx_SET (VOIDmode, op0,
-			      gen_safe_OR64 (temp, (high_bits & 0x3ff))));
-    }
-  else
-    {
-      /* If we are XOR'ing with -1, then we should emit a one's complement
-	 instead.  This way the combiner will notice logical operations
-	 such as ANDN later on and substitute.  */
-      if ((low_bits & 0x3ff) == 0x3ff)
-	{
-	  emit_insn (gen_rtx_SET (VOIDmode, op0,
-				  gen_rtx_NOT (DImode, temp)));
-	}
-      else
-	{
-	  emit_insn (gen_rtx_SET (VOIDmode, op0,
-				  gen_safe_XOR64 (temp,
-						  (-0x400 | (low_bits & 0x3ff)))));
-	}
-    }
-}
-
-static void sparc_emit_set_const64_quick2
-	PROTO((rtx, rtx, unsigned HOST_WIDE_INT,
-	       unsigned HOST_WIDE_INT, int));
-
-static void
-sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
-  rtx op0;
-  rtx temp;
-  unsigned HOST_WIDE_INT high_bits;
-  unsigned HOST_WIDE_INT low_immediate;
-  int shift_count;
-{
-  rtx temp2 = op0;
-
-  if ((high_bits & 0xfffffc00) != 0)
-    {
-      sparc_emit_set_safe_HIGH64 (temp, high_bits);
-      if ((high_bits & ~0xfffffc00) != 0)
-	emit_insn (gen_rtx_SET (VOIDmode, op0,
-				gen_safe_OR64 (temp, (high_bits & 0x3ff))));
-      else
-	temp2 = temp;
-    }
-  else
-    {
-      emit_insn (gen_safe_SET64 (temp, high_bits));
-      temp2 = temp;
-    }
-
-  /* Now shift it up into place. */
-  emit_insn (gen_rtx_SET (VOIDmode, op0,
-			  gen_rtx_ASHIFT (DImode, temp2,
-					  GEN_INT (shift_count))));
-
-  /* If there is a low immediate part piece, finish up by
-     putting that in as well.  */
-  if (low_immediate != 0)
-    emit_insn (gen_rtx_SET (VOIDmode, op0,
-			    gen_safe_OR64 (op0, low_immediate)));
-}
-
-static void sparc_emit_set_const64_longway
-	PROTO((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
-
-/* Full 64-bit constant decomposition.  Even though this is the
-   'worst' case, we still optimize a few things away.  */
-static void
-sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
-     rtx op0;
-     rtx temp;
-     unsigned HOST_WIDE_INT high_bits;
-     unsigned HOST_WIDE_INT low_bits;
-{
-  rtx sub_temp;
-
-  if (reload_in_progress || reload_completed)
-    sub_temp = op0;
-  else
-    sub_temp = gen_reg_rtx (DImode);
-
-  if ((high_bits & 0xfffffc00) != 0)
-    {
-      sparc_emit_set_safe_HIGH64 (temp, high_bits);
-      if ((high_bits & ~0xfffffc00) != 0)
-	emit_insn (gen_rtx_SET (VOIDmode,
-				sub_temp,
-				gen_safe_OR64 (temp, (high_bits & 0x3ff))));
-      else
-	sub_temp = temp;
-    }
-  else
-    {
-      emit_insn (gen_safe_SET64 (temp, high_bits));
-      sub_temp = temp;
-    }
-
-  if (!reload_in_progress && !reload_completed)
-    {
-      rtx temp2 = gen_reg_rtx (DImode);
-      rtx temp3 = gen_reg_rtx (DImode);
-      rtx temp4 = gen_reg_rtx (DImode);
-
-      emit_insn (gen_rtx_SET (VOIDmode, temp4,
-			      gen_rtx_ASHIFT (DImode, sub_temp,
-					      GEN_INT (32))));
-
-      sparc_emit_set_safe_HIGH64 (temp2, low_bits);
-      if ((low_bits & ~0xfffffc00) != 0)
-	{
-	  emit_insn (gen_rtx_SET (VOIDmode, temp3,
-				  gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
-	  emit_insn (gen_rtx_SET (VOIDmode, op0,
-				  gen_rtx_PLUS (DImode, temp4, temp3)));
-	}
-      else
-	{
-	  emit_insn (gen_rtx_SET (VOIDmode, op0,
-				  gen_rtx_PLUS (DImode, temp4, temp2)));
-	}
-    }
-  else
-    {
-      rtx low1 = GEN_INT ((low_bits >> (32 - 12))          & 0xfff);
-      rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12))     & 0xfff);
-      rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
-      int to_shift = 12;
-
-      /* We are in the middle of reload, so this is really
-	 painful.  However we do still make an attempt to
-	 avoid emitting truly stupid code.  */
-      if (low1 != const0_rtx)
-	{
-	  emit_insn (gen_rtx_SET (VOIDmode, op0,
-				  gen_rtx_ASHIFT (DImode, sub_temp,
-						  GEN_INT (to_shift))));
-	  emit_insn (gen_rtx_SET (VOIDmode, op0,
-				  gen_rtx_IOR (DImode, op0, low1)));
-	  sub_temp = op0;
-	  to_shift = 12;
-	}
-      else
-	{
-	  to_shift += 12;
-	}
-      if (low2 != const0_rtx)
-	{
-	  emit_insn (gen_rtx_SET (VOIDmode, op0,
-				  gen_rtx_ASHIFT (DImode, sub_temp,
-						  GEN_INT (to_shift))));
-	  emit_insn (gen_rtx_SET (VOIDmode, op0,
-				  gen_rtx_IOR (DImode, op0, low2)));
-	  sub_temp = op0;
-	  to_shift = 8;
-	}
-      else
-	{
-	  to_shift += 8;
-	}
-      emit_insn (gen_rtx_SET (VOIDmode, op0,
-			      gen_rtx_ASHIFT (DImode, sub_temp,
-					      GEN_INT (to_shift))));
-      if (low3 != const0_rtx)
-	emit_insn (gen_rtx_SET (VOIDmode, op0,
-				gen_rtx_IOR (DImode, op0, low3)));
-      /* phew... */
-    }
-}
-
-/* Analyze a 64-bit constant for certain properties. */
-static void analyze_64bit_constant
-	PROTO((unsigned HOST_WIDE_INT,
-	       unsigned HOST_WIDE_INT,
-	       int *, int *, int *));
-
-static void
-analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
-     unsigned HOST_WIDE_INT high_bits, low_bits;
-     int *hbsp, *lbsp, *abbasp;
-{
-  int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
-  int i;
-
-  lowest_bit_set = highest_bit_set = -1;
-  i = 0;
-  do
-    {
-      if ((lowest_bit_set == -1)
-	  && ((low_bits >> i) & 1))
-	lowest_bit_set = i;
-      if ((highest_bit_set == -1)
-	  && ((high_bits >> (32 - i - 1)) & 1))
-	highest_bit_set = (64 - i - 1);
-    }
-  while (++i < 32
-	 && ((highest_bit_set == -1)
-	     || (lowest_bit_set == -1)));
-  if (i == 32)
-    {
-      i = 0;
-      do
-	{
-	  if ((lowest_bit_set == -1)
-	      && ((high_bits >> i) & 1))
-	    lowest_bit_set = i + 32;
-	  if ((highest_bit_set == -1)
-	      && ((low_bits >> (32 - i - 1)) & 1))
-	    highest_bit_set = 32 - i - 1;
-	}
-      while (++i < 32
-	     && ((highest_bit_set == -1)
-		 || (lowest_bit_set == -1)));
-    }
-  /* If there are no bits set this should have gone out
-     as one instruction!  */
-  if (lowest_bit_set == -1
-      || highest_bit_set == -1)
-    abort ();
-  all_bits_between_are_set = 1;
-  for (i = lowest_bit_set; i <= highest_bit_set; i++)
-    {
-      if (i < 32)
-	{
-	  if ((low_bits & (1 << i)) != 0)
-	    continue;
-	}
-      else
-	{
-	  if ((high_bits & (1 << (i - 32))) != 0)
-	    continue;
-	}
-      all_bits_between_are_set = 0;
-      break;
-    }
-  *hbsp = highest_bit_set;
-  *lbsp = lowest_bit_set;
-  *abbasp = all_bits_between_are_set;
-}
-
-static int const64_is_2insns
-	PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
-
-static int
-const64_is_2insns (high_bits, low_bits)
-     unsigned HOST_WIDE_INT high_bits, low_bits;
-{
-  int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
-
-  if (high_bits == 0
-      || high_bits == 0xffffffff)
-    return 1;
-
-  analyze_64bit_constant (high_bits, low_bits,
-			  &highest_bit_set, &lowest_bit_set,
-			  &all_bits_between_are_set);
-
-  if ((highest_bit_set == 63
-       || lowest_bit_set == 0)
-      && all_bits_between_are_set != 0)
-    return 1;
-
-  if ((highest_bit_set - lowest_bit_set) < 21)
-    return 1;
-
-  return 0;
-}
-
-static unsigned HOST_WIDE_INT create_simple_focus_bits
-	PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
-	       int, int));
-
-static unsigned HOST_WIDE_INT
-create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
-     unsigned HOST_WIDE_INT high_bits, low_bits;
-     int lowest_bit_set, shift;
-{
-  HOST_WIDE_INT hi, lo;
-
-  if (lowest_bit_set < 32)
-    {
-      lo = (low_bits >> lowest_bit_set) << shift;
-      hi = ((high_bits << (32 - lowest_bit_set)) << shift);
-    }
-  else
-    {
-      lo = 0;
-      hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
-    }
-  if (hi & lo)
-    abort ();
-  return (hi | lo);
-}
-
-/* Here we are sure to be arch64 and this is an integer constant
-   being loaded into a register.  Emit the most efficient
-   insn sequence possible.  Detection of all the 1-insn cases
-   has been done already.  */
-void
-sparc_emit_set_const64 (op0, op1)
-     rtx op0;
-     rtx op1;
-{
-  unsigned HOST_WIDE_INT high_bits, low_bits;
-  int lowest_bit_set, highest_bit_set;
-  int all_bits_between_are_set;
-  rtx temp;
-
-  /* Sanity check that we know what we are working with.  */
-  if (! TARGET_ARCH64
-      || GET_CODE (op0) != REG
-      || (REGNO (op0) >= SPARC_FIRST_FP_REG
-	  && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
-    abort ();
-
-  if (reload_in_progress || reload_completed)
-    temp = op0;
-  else
-    temp = gen_reg_rtx (DImode);
-
-  if (GET_CODE (op1) != CONST_DOUBLE
-      && GET_CODE (op1) != CONST_INT)
-    {
-      sparc_emit_set_symbolic_const64 (op0, op1, temp);
-      return;
-    }
-
-  if (GET_CODE (op1) == CONST_DOUBLE)
-    {
-#if HOST_BITS_PER_WIDE_INT == 64
-      high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
-      low_bits  = CONST_DOUBLE_LOW (op1) & 0xffffffff;
-#else
-      high_bits = CONST_DOUBLE_HIGH (op1);
-      low_bits = CONST_DOUBLE_LOW (op1);
-#endif
-    }
-  else
-    {
-#if HOST_BITS_PER_WIDE_INT == 64
-      high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
-      low_bits = (INTVAL (op1) & 0xffffffff);
-#else
-      high_bits = ((INTVAL (op1) < 0) ?
-		   0xffffffff :
-		   0x00000000);
-      low_bits = INTVAL (op1);
-#endif
-    }
-
-  /* low_bits	bits 0  --> 31
-     high_bits	bits 32 --> 63  */
-
-  analyze_64bit_constant (high_bits, low_bits,
-			  &highest_bit_set, &lowest_bit_set,
-			  &all_bits_between_are_set);
-
-  /* First try for a 2-insn sequence.  */
-
-  /* These situations are preferred because the optimizer can
-   * do more things with them:
-   * 1) mov	-1, %reg
-   *    sllx	%reg, shift, %reg
-   * 2) mov	-1, %reg
-   *    srlx	%reg, shift, %reg
-   * 3) mov	some_small_const, %reg
-   *    sllx	%reg, shift, %reg
-   */
-  if (((highest_bit_set == 63
-	|| lowest_bit_set == 0)
-       && all_bits_between_are_set != 0)
-      || ((highest_bit_set - lowest_bit_set) < 12))
-    {
-      HOST_WIDE_INT the_const = -1;
-      int shift = lowest_bit_set;
-
-      if ((highest_bit_set != 63
-	   && lowest_bit_set != 0)
-	  || all_bits_between_are_set == 0)
-	{
-	  the_const =
-	    create_simple_focus_bits (high_bits, low_bits,
-				      lowest_bit_set, 0);
-	}
-      else if (lowest_bit_set == 0)
-	shift = -(63 - highest_bit_set);
-
-      if (! SPARC_SIMM13_P (the_const))
-	abort ();
-
-      emit_insn (gen_safe_SET64 (temp, the_const));
-      if (shift > 0)
-	emit_insn (gen_rtx_SET (VOIDmode,
-				op0,
-				gen_rtx_ASHIFT (DImode,
-						temp,
-						GEN_INT (shift))));
-      else if (shift < 0)
-	emit_insn (gen_rtx_SET (VOIDmode,
-				op0,
-				gen_rtx_LSHIFTRT (DImode,
-						  temp,
-						  GEN_INT (-shift))));
-      else
-	abort ();
-      return;
-    }
-
-  /* Now a range of 22 or less bits set somewhere.
-   * 1) sethi	%hi(focus_bits), %reg
-   *    sllx	%reg, shift, %reg
-   * 2) sethi	%hi(focus_bits), %reg
-   *    srlx	%reg, shift, %reg
-   */
-  if ((highest_bit_set - lowest_bit_set) < 21)
-    {
-      unsigned HOST_WIDE_INT focus_bits =
-	create_simple_focus_bits (high_bits, low_bits,
-				  lowest_bit_set, 10);
-
-      if (! SPARC_SETHI_P (focus_bits))
-	 abort ();
-
-      sparc_emit_set_safe_HIGH64 (temp, focus_bits);
-
-      /* If lowest_bit_set == 10 then a sethi alone could have done it.  */
-      if (lowest_bit_set < 10)
-	emit_insn (gen_rtx_SET (VOIDmode,
-				op0,
-				gen_rtx_LSHIFTRT (DImode, temp,
-						  GEN_INT (10 - lowest_bit_set))));
-      else if (lowest_bit_set > 10)
-	emit_insn (gen_rtx_SET (VOIDmode,
-				op0,
-				gen_rtx_ASHIFT (DImode, temp,
-						GEN_INT (lowest_bit_set - 10))));
-      else
-	abort ();
-      return;
-    }
-
-  /* 1) sethi	%hi(low_bits), %reg
-   *    or	%reg, %lo(low_bits), %reg
-   * 2) sethi	%hi(~low_bits), %reg
-   *	xor	%reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
-   */
-  if (high_bits == 0
-      || high_bits == 0xffffffff)
-    {
-      sparc_emit_set_const64_quick1 (op0, temp, low_bits,
-				     (high_bits == 0xffffffff));
-      return;
-    }
-
-  /* Now, try 3-insn sequences.  */
-
-  /* 1) sethi	%hi(high_bits), %reg
-   *    or	%reg, %lo(high_bits), %reg
-   *    sllx	%reg, 32, %reg
-   */
-  if (low_bits == 0)
-    {
-      sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
-      return;
-    }
-
-  /* We may be able to do something quick
-     when the constant is negated, so try that.  */
-  if (const64_is_2insns ((~high_bits) & 0xffffffff,
-			 (~low_bits) & 0xfffffc00))
-    {
-      /* NOTE: The trailing bits get XOR'd so we need the
-	 non-negated bits, not the negated ones.  */
-      unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
-
-      if ((((~high_bits) & 0xffffffff) == 0
-	   && ((~low_bits) & 0x80000000) == 0)
-	  || (((~high_bits) & 0xffffffff) == 0xffffffff
-	      && ((~low_bits) & 0x80000000) != 0))
-	{
-	  int fast_int = (~low_bits & 0xffffffff);
-
-	  if ((SPARC_SETHI_P (fast_int)
-	       && (~high_bits & 0xffffffff) == 0)
-	      || SPARC_SIMM13_P (fast_int))
-	    emit_insn (gen_safe_SET64 (temp, fast_int));
-	  else
-	    sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
-	}
-      else
-	{
-	  rtx negated_const;
-#if HOST_BITS_PER_WIDE_INT == 64
-	  negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
-				   (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
-#else
-	  negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx,
-						(~low_bits) & 0xfffffc00,
-						(~high_bits) & 0xffffffff);
-#endif
-	  sparc_emit_set_const64 (temp, negated_const);
-	}
-
-      /* If we are XOR'ing with -1, then we should emit a one's complement
-	 instead.  This way the combiner will notice logical operations
-	 such as ANDN later on and substitute.  */
-      if (trailing_bits == 0x3ff)
-	{
-	  emit_insn (gen_rtx_SET (VOIDmode, op0,
-				  gen_rtx_NOT (DImode, temp)));
-	}
-      else
-	{
-	  emit_insn (gen_rtx_SET (VOIDmode,
-				  op0,
-				  gen_safe_XOR64 (temp,
-						  (-0x400 | trailing_bits))));
-	}
-      return;
-    }
-
-  /* 1) sethi	%hi(xxx), %reg
-   *    or	%reg, %lo(xxx), %reg
-   *	sllx	%reg, yyy, %reg
-   *
-   * ??? This is just a generalized version of the low_bits==0
-   * thing above, FIXME...
-   */
-  if ((highest_bit_set - lowest_bit_set) < 32)
-    {
-      unsigned HOST_WIDE_INT focus_bits =
-	create_simple_focus_bits (high_bits, low_bits,
-				  lowest_bit_set, 0);
-
-      /* We can't get here in this state.  */
-      if (highest_bit_set < 32
-	  || lowest_bit_set >= 32)
-	abort ();
-
-      /* So what we know is that the set bits straddle the
-	 middle of the 64-bit word.  */
-      sparc_emit_set_const64_quick2 (op0, temp,
-				     focus_bits, 0,
-				     lowest_bit_set);
-      return;
-    }
-
-  /* 1) sethi	%hi(high_bits), %reg
-   *    or	%reg, %lo(high_bits), %reg
-   *    sllx	%reg, 32, %reg
-   *	or	%reg, low_bits, %reg
-   */
-  if (SPARC_SIMM13_P(low_bits)
-      && ((int)low_bits > 0))
-    {
-      sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
-      return;
-    }
-
-  /* The easiest way when all else fails, is full decomposition. */
-#if 0
-  printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
-	  high_bits, low_bits, ~high_bits, ~low_bits);
-#endif
-  sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
-}
-
-/* X and Y are two things to compare using CODE.  Emit the compare insn and
-   return the rtx for the cc reg in the proper mode.  */
-
-rtx
-gen_compare_reg (code, x, y)
-     enum rtx_code code;
-     rtx x, y;
-{
-  enum machine_mode mode = SELECT_CC_MODE (code, x, y);
-  rtx cc_reg;
-
-  /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
-     fcc regs (cse can't tell they're really call clobbered regs and will
-     remove a duplicate comparison even if there is an intervening function
-     call - it will then try to reload the cc reg via an int reg which is why
-     we need the movcc patterns).  It is possible to provide the movcc
-     patterns by using the ldxfsr/stxfsr v9 insns.  I tried it: you need two
-     registers (say %g1,%g5) and it takes about 6 insns.  A better fix would be
-     to tell cse that CCFPE mode registers (even pseudos) are call
-     clobbered.  */
-
-  /* ??? This is an experiment.  Rather than making changes to cse which may
-     or may not be easy/clean, we do our own cse.  This is possible because
-     we will generate hard registers.  Cse knows they're call clobbered (it
-     doesn't know the same thing about pseudos). If we guess wrong, no big
-     deal, but if we win, great!  */
-
-  if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
-#if 1 /* experiment */
-    {
-      int reg;
-      /* We cycle through the registers to ensure they're all exercised.  */
-      static int next_fcc_reg = 0;
-      /* Previous x,y for each fcc reg.  */
-      static rtx prev_args[4][2];
-
-      /* Scan prev_args for x,y.  */
-      for (reg = 0; reg < 4; reg++)
-	if (prev_args[reg][0] == x && prev_args[reg][1] == y)
-	  break;
-      if (reg == 4)
-	{
-	  reg = next_fcc_reg;
-	  prev_args[reg][0] = x;
-	  prev_args[reg][1] = y;
-	  next_fcc_reg = (next_fcc_reg + 1) & 3;
-	}
-      cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
-    }
-#else
-    cc_reg = gen_reg_rtx (mode);
-#endif /* ! experiment */
-  else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
-    cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
-  else
-    cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
-
-  emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
-			  gen_rtx_COMPARE (mode, x, y)));
-
-  return cc_reg;
-}
-
-/* This function is used for v9 only.
-   CODE is the code for an Scc's comparison.
-   OPERANDS[0] is the target of the Scc insn.
-   OPERANDS[1] is the value we compare against const0_rtx (which hasn't
-   been generated yet).
-
-   This function is needed to turn
-
-	   (set (reg:SI 110)
-	       (gt (reg:CCX 100 %icc)
-	           (const_int 0)))
-   into
-	   (set (reg:SI 110)
-	       (gt:DI (reg:CCX 100 %icc)
-	           (const_int 0)))
-
-   IE: The instruction recognizer needs to see the mode of the comparison to
-   find the right instruction. We could use "gt:DI" right in the
-   define_expand, but leaving it out allows us to handle DI, SI, etc.
-
-   We refer to the global sparc compare operands sparc_compare_op0 and
-   sparc_compare_op1.  */
-
-int
-gen_v9_scc (compare_code, operands)
-     enum rtx_code compare_code;
-     register rtx *operands;
-{
-  rtx temp, op0, op1;
-
-  if (! TARGET_ARCH64
-      && (GET_MODE (sparc_compare_op0) == DImode
-	  || GET_MODE (operands[0]) == DImode))
-    return 0;
-
-  /* Handle the case where operands[0] == sparc_compare_op0.
-     We "early clobber" the result.  */
-  if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
-    {
-      op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
-      emit_move_insn (op0, sparc_compare_op0);
-    }
-  else
-    op0 = sparc_compare_op0;
-  /* For consistency in the following.  */
-  op1 = sparc_compare_op1;
-
-  /* Try to use the movrCC insns.  */
-  if (TARGET_ARCH64
-      && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
-      && op1 == const0_rtx
-      && v9_regcmp_p (compare_code))
-    {
-      /* Special case for op0 != 0.  This can be done with one instruction if
-	 operands[0] == sparc_compare_op0.  We don't assume they are equal
-	 now though.  */
-
-      if (compare_code == NE
-	  && GET_MODE (operands[0]) == DImode
-	  && GET_MODE (op0) == DImode)
-	{
-	  emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0));
-	  emit_insn (gen_rtx_SET (VOIDmode, operands[0],
-			      gen_rtx_IF_THEN_ELSE (DImode,
-				       gen_rtx_fmt_ee (compare_code, DImode,
-						       op0, const0_rtx),
-				       const1_rtx,
-				       operands[0])));
-	  return 1;
-	}
-
-      emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
-      if (GET_MODE (op0) != DImode)
-	{
-	  temp = gen_reg_rtx (DImode);
-	  convert_move (temp, op0, 0);
-	}
-      else
-	temp = op0;
-      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
-			  gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
-				   gen_rtx_fmt_ee (compare_code, DImode,
-						   temp, const0_rtx),
-				   const1_rtx,
-				   operands[0])));
-      return 1;
-    }
-  else
-    {
-      operands[1] = gen_compare_reg (compare_code, op0, op1);
-
-      switch (GET_MODE (operands[1]))
-	{
-	  case CCmode :
-	  case CCXmode :
-	  case CCFPEmode :
-	  case CCFPmode :
-	    break;
-	  default :
-	    abort ();
-	}
-      emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
-      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
-			  gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
-				   gen_rtx_fmt_ee (compare_code,
-						   GET_MODE (operands[1]),
-						   operands[1], const0_rtx),
-				    const1_rtx, operands[0])));
-      return 1;
-    }
-}
-
-/* Emit a conditional jump insn for the v9 architecture using comparison code
-   CODE and jump target LABEL.
-   This function exists to take advantage of the v9 brxx insns.  */
-
-void
-emit_v9_brxx_insn (code, op0, label)
-     enum rtx_code code;
-     rtx op0, label;
-{
-  emit_jump_insn (gen_rtx_SET (VOIDmode,
-			   pc_rtx,
-			   gen_rtx_IF_THEN_ELSE (VOIDmode,
-				    gen_rtx_fmt_ee (code, GET_MODE (op0),
-						    op0, const0_rtx),
-				    gen_rtx_LABEL_REF (VOIDmode, label),
-				    pc_rtx)));
-}
-
-/* Return nonzero if a return peephole merging return with
-   setting of output register is ok.  */
-int
-leaf_return_peephole_ok ()
-{
-  return (actual_fsize == 0);
-}
-
-/* Return nonzero if TRIAL can go into the function epilogue's
-   delay slot.  SLOT is the slot we are trying to fill.  */
-
-int
-eligible_for_epilogue_delay (trial, slot)
-     rtx trial;
-     int slot;
-{
-  rtx pat, src;
-
-  if (slot >= 1)
-    return 0;
-
-  if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
-    return 0;
-
-  if (get_attr_length (trial) != 1)
-    return 0;
-
-  /* If %g0 is live, there are lots of things we can't handle.
-     Rather than trying to find them all now, let's punt and only
-     optimize things as necessary.  */
-  if (TARGET_LIVE_G0)
-    return 0;
-
-  /* In the case of a true leaf function, anything can go into the delay slot.
-     A delay slot only exists however if the frame size is zero, otherwise
-     we will put an insn to adjust the stack after the return.  */
-  if (leaf_function)
-    {
-      if (leaf_return_peephole_ok ())
-	return ((get_attr_in_uncond_branch_delay (trial)
-		 == IN_BRANCH_DELAY_TRUE));
-      return 0;
-    }
-
-  /* If only trivial `restore' insns work, nothing can go in the
-     delay slot.  */
-  else if (TARGET_BROKEN_SAVERESTORE)
-    return 0;
-
-  pat = PATTERN (trial);
-
-  /* Otherwise, only operations which can be done in tandem with
-     a `restore' insn can go into the delay slot.  */
-  if (GET_CODE (SET_DEST (pat)) != REG
-      || REGNO (SET_DEST (pat)) >= 32
-      || REGNO (SET_DEST (pat)) < 24)
-    return 0;
-
-  /* The set of insns matched here must agree precisely with the set of
-     patterns paired with a RETURN in sparc.md.  */
-
-  src = SET_SRC (pat);
-
-  /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64.  */
-  if (arith_operand (src, GET_MODE (src)))
-    {
-      if (TARGET_ARCH64)
-        return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
-      else
-        return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
-    }
-    
-  /* This matches "*return_di".  */
-  else if (arith_double_operand (src, GET_MODE (src)))
-    return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
-
-  /* This matches "*return_sf_no_fpu".  */
-  else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
-	   && register_operand (src, SFmode))
-    return 1;
-
-  /* This matches "*return_addsi".  */
-  else if (GET_CODE (src) == PLUS
-	   && arith_operand (XEXP (src, 0), SImode)
-	   && arith_operand (XEXP (src, 1), SImode)
-	   && (register_operand (XEXP (src, 0), SImode)
-	       || register_operand (XEXP (src, 1), SImode)))
-    return 1;
-
-  /* This matches "*return_adddi".  */
-  else if (GET_CODE (src) == PLUS
-	   && arith_double_operand (XEXP (src, 0), DImode)
-	   && arith_double_operand (XEXP (src, 1), DImode)
-	   && (register_operand (XEXP (src, 0), DImode)
-	       || register_operand (XEXP (src, 1), DImode)))
-    return 1;
-
-  return 0;
-}
-
-static int
-check_return_regs (x)
-     rtx x;
-{
-  switch (GET_CODE (x))
-    {
-    case REG:
-      return IN_OR_GLOBAL_P (x);
-
-    case CONST_INT:
-    case CONST_DOUBLE:
-    case CONST:
-    case SYMBOL_REF:
-    case LABEL_REF:
-    return 1;
-
-    case SET:
-    case IOR:
-    case AND:
-    case XOR:
-    case PLUS:
-    case MINUS:
-      if (check_return_regs (XEXP (x, 1)) == 0)
-  return 0;
-    case NOT:
-    case NEG:
-    case MEM:
-      return check_return_regs (XEXP (x, 0));
-      
-    default:
-      return 0;
-    }
-
-}
-
-/* Return 1 if TRIAL references only in and global registers.  */
-int
-eligible_for_return_delay (trial)
-     rtx trial;
-{
-  if (GET_CODE (PATTERN (trial)) != SET)
-    return 0;
-
-  return check_return_regs (PATTERN (trial));
-}
-
-int
-short_branch (uid1, uid2)
-     int uid1, uid2;
-{
-  unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
-  if (delta + 1024 < 2048)
-    return 1;
-  /* warning ("long branch, distance %d", delta); */
-  return 0;
-}
-
-/* Return non-zero if REG is not used after INSN.
-   We assume REG is a reload reg, and therefore does
-   not live past labels or calls or jumps.  */
-int
-reg_unused_after (reg, insn)
-     rtx reg;
-     rtx insn;
-{
-  enum rtx_code code, prev_code = UNKNOWN;
-
-  while ((insn = NEXT_INSN (insn)))
-    {
-      if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
-	return 1;
-
-      code = GET_CODE (insn);
-      if (GET_CODE (insn) == CODE_LABEL)
-	return 1;
-
-      if (GET_RTX_CLASS (code) == 'i')
-	{
-	  rtx set = single_set (insn);
-	  int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
-	  if (set && in_src)
-	    return 0;
-	  if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
-	    return 1;
-	  if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
-	    return 0;
-	}
-      prev_code = code;
-    }
-  return 1;
-}
-
-/* The table we use to reference PIC data.  */
-static rtx global_offset_table;
-
-/* The function we use to get at it.  */
-static rtx get_pc_symbol;
-static char get_pc_symbol_name[256];
-
-/* Ensure that we are not using patterns that are not OK with PIC.  */
-
-int
-check_pic (i)
-     int i;
-{
-  switch (flag_pic)
-    {
-    case 1:
-      if (GET_CODE (recog_operand[i]) == SYMBOL_REF
-	  || (GET_CODE (recog_operand[i]) == CONST
-	      && ! (GET_CODE (XEXP (recog_operand[i], 0)) == MINUS
-		    && (XEXP (XEXP (recog_operand[i], 0), 0)
-			== global_offset_table)
-		    && (GET_CODE (XEXP (XEXP (recog_operand[i], 0), 1))
-			== CONST))))
-	abort ();
-    case 2:
-    default:
-      return 1;
-    }
-}
-
-/* Return true if X is an address which needs a temporary register when 
-   reloaded while generating PIC code.  */
-
-int
-pic_address_needs_scratch (x)
-     rtx x;
-{
-  /* An address which is a symbolic plus a non SMALL_INT needs a temp reg.  */
-  if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
-      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
-      && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
-    return 1;
-
-  return 0;
-}
-
-/* Legitimize PIC addresses.  If the address is already position-independent,
-   we return ORIG.  Newly generated position-independent addresses go into a
-   reg.  This is REG if non zero, otherwise we allocate register(s) as
-   necessary.  */
-
-rtx
-legitimize_pic_address (orig, mode, reg)
-     rtx orig;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     rtx reg;
-{
-  if (GET_CODE (orig) == SYMBOL_REF)
-    {
-      rtx pic_ref, address;
-      rtx insn;
-
-      if (reg == 0)
-	{
-	  if (reload_in_progress || reload_completed)
-	    abort ();
-	  else
-	    reg = gen_reg_rtx (Pmode);
-	}
-
-      if (flag_pic == 2)
-	{
-	  /* If not during reload, allocate another temp reg here for loading
-	     in the address, so that these instructions can be optimized
-	     properly.  */
-	  rtx temp_reg = ((reload_in_progress || reload_completed)
-			  ? reg : gen_reg_rtx (Pmode));
-
-	  /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
-	     won't get confused into thinking that these two instructions
-	     are loading in the true address of the symbol.  If in the
-	     future a PIC rtx exists, that should be used instead.  */
-	  if (Pmode == SImode)
-	    {
-	      emit_insn (gen_movsi_high_pic (temp_reg, orig));
-	      emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
-	    }
-	  else
-	    {
-	      emit_insn (gen_movdi_high_pic (temp_reg, orig));
-	      emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
-	    }
-	  address = temp_reg;
-	}
-      else
-	address = orig;
-
-      pic_ref = gen_rtx_MEM (Pmode,
-			 gen_rtx_PLUS (Pmode,
-				  pic_offset_table_rtx, address));
-      current_function_uses_pic_offset_table = 1;
-      RTX_UNCHANGING_P (pic_ref) = 1;
-      insn = emit_move_insn (reg, pic_ref);
-      /* Put a REG_EQUAL note on this insn, so that it can be optimized
-	 by loop.  */
-      REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
-				  REG_NOTES (insn));
-      return reg;
-    }
-  else if (GET_CODE (orig) == CONST)
-    {
-      rtx base, offset;
-
-      if (GET_CODE (XEXP (orig, 0)) == PLUS
-	  && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
-	return orig;
-
-      if (reg == 0)
-	{
-	  if (reload_in_progress || reload_completed)
-	    abort ();
-	  else
-	    reg = gen_reg_rtx (Pmode);
-	}
-
-      if (GET_CODE (XEXP (orig, 0)) == PLUS)
-	{
-	  base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
-	  offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
-					 base == reg ? 0 : reg);
-	}
-      else
-	abort ();
-
-      if (GET_CODE (offset) == CONST_INT)
-	{
-	  if (SMALL_INT (offset))
-	    return plus_constant_for_output (base, INTVAL (offset));
-	  else if (! reload_in_progress && ! reload_completed)
-	    offset = force_reg (Pmode, offset);
-	  else
-	    /* If we reach here, then something is seriously wrong.  */
-	    abort ();
-	}
-      return gen_rtx_PLUS (Pmode, base, offset);
-    }
-  else if (GET_CODE (orig) == LABEL_REF)
-    /* ??? Why do we do this?  */
-    /* Now movsi_pic_label_ref uses it, but we ought to be checking that
-       the register is live instead, in case it is eliminated.  */
-    current_function_uses_pic_offset_table = 1;
-
-  return orig;
-}
-
-/* Return the RTX for insns to set the PIC register.  */
-
-static rtx
-pic_setup_code ()
-{
-  rtx seq;
-
-  start_sequence ();
-  emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
-			 get_pc_symbol));
-  seq = gen_sequence ();
-  end_sequence ();
-
-  return seq;
-}
-
-/* Emit special PIC prologues and epilogues.  */
-
-void
-finalize_pic ()
-{
-  /* Labels to get the PC in the prologue of this function.  */
-  int orig_flag_pic = flag_pic;
-  rtx insn;
-
-  if (current_function_uses_pic_offset_table == 0)
-    return;
-
-  if (! flag_pic)
-    abort ();
-
-  /* If we havn't emitted the special get_pc helper function, do so now.  */
-  if (get_pc_symbol_name[0] == 0)
-    {
-      int align;
-
-      ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
-      text_section ();
-
-      align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
-      if (align > 0)
-	ASM_OUTPUT_ALIGN (asm_out_file, align);
-      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
-      fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file);
-    }
-
-  /* Initialize every time through, since we can't easily
-     know this to be permanent.  */
-  global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
-  get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
-  flag_pic = 0;
-
-  emit_insn_after (pic_setup_code (), get_insns ());
-
-  /* Insert the code in each nonlocal goto receiver.
-     If you make changes here or to the nonlocal_goto_receiver
-     pattern, make sure the unspec_volatile numbers still
-     match.  */
-  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-    if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
-	&& XINT (PATTERN (insn), 1) == 5)
-      emit_insn_after (pic_setup_code (), insn);
-
-  flag_pic = orig_flag_pic;
-
-  /* Need to emit this whether or not we obey regdecls,
-     since setjmp/longjmp can cause life info to screw up.
-     ??? In the case where we don't obey regdecls, this is not sufficient
-     since we may not fall out the bottom.  */
-  emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
-}
-
-/* Return 1 if RTX is a MEM which is known to be aligned to at
-   least an 8 byte boundary.  */
-
-int
-mem_min_alignment (mem, desired)
-     rtx mem;
-     int desired;
-{
-  rtx addr, base, offset;
-
-  /* If it's not a MEM we can't accept it.  */
-  if (GET_CODE (mem) != MEM)
-    return 0;
-
-  addr = XEXP (mem, 0);
-  base = offset = NULL_RTX;
-  if (GET_CODE (addr) == PLUS)
-    {
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-	{
-	  base = XEXP (addr, 0);
-
-	  /* What we are saying here is that if the base
-	     REG is aligned properly, the compiler will make
-	     sure any REG based index upon it will be so
-	     as well.  */
-	  if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
-	    offset = XEXP (addr, 1);
-	  else
-	    offset = const0_rtx;
-	}
-    }
-  else if (GET_CODE (addr) == REG)
-    {
-      base = addr;
-      offset = const0_rtx;
-    }
-
-  if (base != NULL_RTX)
-    {
-      int regno = REGNO (base);
-
-      if (regno != FRAME_POINTER_REGNUM
-	  && regno != STACK_POINTER_REGNUM)
-	{
-	  /* Check if the compiler has recorded some information
-	     about the alignment of the base REG.  If reload has
-	     completed, we already matched with proper alignments.  */
-	  if (((regno_pointer_align != NULL
-		&& REGNO_POINTER_ALIGN (regno) >= desired)
-	       || reload_completed)
-	      && ((INTVAL (offset) & (desired - 1)) == 0))
-	    return 1;
-	}
-      else
-	{
-	  if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
-	    return 1;
-	}
-    }
-  else if (! TARGET_UNALIGNED_DOUBLES
-	   || CONSTANT_P (addr)
-	   || GET_CODE (addr) == LO_SUM)
-    {
-      /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
-	 is true, in which case we can only assume that an access is aligned if
-	 it is to a constant address, or the address involves a LO_SUM.  */
-      return 1;
-    }
-  
-  /* An obviously unaligned address.  */
-  return 0;
-}
-
-
-/* Vectors to keep interesting information about registers where it can easily
-   be got.  We use to use the actual mode value as the bit number, but there
-   are more than 32 modes now.  Instead we use two tables: one indexed by
-   hard register number, and one indexed by mode.  */
-
-/* The purpose of sparc_mode_class is to shrink the range of modes so that
-   they all fit (as bit numbers) in a 32 bit word (again).  Each real mode is
-   mapped into one sparc_mode_class mode.  */
-
-enum sparc_mode_class {
-  S_MODE, D_MODE, T_MODE, O_MODE,
-  SF_MODE, DF_MODE, TF_MODE, OF_MODE,
-  CC_MODE, CCFP_MODE
-};
-
-/* Modes for single-word and smaller quantities.  */
-#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
-
-/* Modes for double-word and smaller quantities.  */
-#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
-
-/* Modes for quad-word and smaller quantities.  */
-#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
-
-/* Modes for single-float quantities.  We must allow any single word or
-   smaller quantity.  This is because the fix/float conversion instructions
-   take integer inputs/outputs from the float registers.  */
-#define SF_MODES (S_MODES)
-
-/* Modes for double-float and smaller quantities.  */
-#define DF_MODES (S_MODES | D_MODES)
-
-#define DF_MODES64 DF_MODES
-
-/* Modes for double-float only quantities.  */
-#define DF_ONLY_MODES ((1 << (int) DF_MODE) | (1 << (int) D_MODE))
-
-/* Modes for double-float and larger quantities.  */
-#define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
-
-/* Modes for quad-float only quantities.  */
-#define TF_ONLY_MODES (1 << (int) TF_MODE)
-
-/* Modes for quad-float and smaller quantities.  */
-#define TF_MODES (DF_MODES | TF_ONLY_MODES)
-
-#define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
-
-/* Modes for condition codes.  */
-#define CC_MODES (1 << (int) CC_MODE)
-#define CCFP_MODES (1 << (int) CCFP_MODE)
-
-/* Value is 1 if register/mode pair is acceptable on sparc.
-   The funny mixture of D and T modes is because integer operations
-   do not specially operate on tetra quantities, so non-quad-aligned
-   registers can hold quadword quantities (except %o4 and %i4 because
-   they cross fixed registers).  */
-
-/* This points to either the 32 bit or the 64 bit version.  */
-int *hard_regno_mode_classes;
-
-static int hard_32bit_mode_classes[] = {
-  S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
-  T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
-  T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
-  T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
-
-  TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
-  TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
-  TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
-  TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
-
-  /* FP regs f32 to f63.  Only the even numbered registers actually exist,
-     and none can hold SFmode/SImode values.  */
-  DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
-  DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
-  DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
-  DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
-
-  /* %fcc[0123] */
-  CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
-
-  /* %icc */
-  CC_MODES
-};
-
-static int hard_64bit_mode_classes[] = {
-  D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
-  T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
-  T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
-  T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
-
-  TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
-  TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
-  TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
-  TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
-
-  /* FP regs f32 to f63.  Only the even numbered registers actually exist,
-     and none can hold SFmode/SImode values.  */
-  DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
-  DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
-  DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
-  DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
-
-  /* %fcc[0123] */
-  CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
-
-  /* %icc */
-  CC_MODES
-};
-
-int sparc_mode_class [NUM_MACHINE_MODES];
-
-enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
-
-static void
-sparc_init_modes ()
-{
-  int i;
-
-  for (i = 0; i < NUM_MACHINE_MODES; i++)
-    {
-      switch (GET_MODE_CLASS (i))
-	{
-	case MODE_INT:
-	case MODE_PARTIAL_INT:
-	case MODE_COMPLEX_INT:
-	  if (GET_MODE_SIZE (i) <= 4)
-	    sparc_mode_class[i] = 1 << (int) S_MODE;
-	  else if (GET_MODE_SIZE (i) == 8)
-	    sparc_mode_class[i] = 1 << (int) D_MODE;
-	  else if (GET_MODE_SIZE (i) == 16)
-	    sparc_mode_class[i] = 1 << (int) T_MODE;
-	  else if (GET_MODE_SIZE (i) == 32)
-	    sparc_mode_class[i] = 1 << (int) O_MODE;
-	  else 
-	    sparc_mode_class[i] = 0;
-	  break;
-	case MODE_FLOAT:
-	case MODE_COMPLEX_FLOAT:
-	  if (GET_MODE_SIZE (i) <= 4)
-	    sparc_mode_class[i] = 1 << (int) SF_MODE;
-	  else if (GET_MODE_SIZE (i) == 8)
-	    sparc_mode_class[i] = 1 << (int) DF_MODE;
-	  else if (GET_MODE_SIZE (i) == 16)
-	    sparc_mode_class[i] = 1 << (int) TF_MODE;
-	  else if (GET_MODE_SIZE (i) == 32)
-	    sparc_mode_class[i] = 1 << (int) OF_MODE;
-	  else 
-	    sparc_mode_class[i] = 0;
-	  break;
-	case MODE_CC:
-	default:
-	  /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
-	     we must explicitly check for them here.  */
-	  if (i == (int) CCFPmode || i == (int) CCFPEmode)
-	    sparc_mode_class[i] = 1 << (int) CCFP_MODE;
-	  else if (i == (int) CCmode || i == (int) CC_NOOVmode
-		   || i == (int) CCXmode || i == (int) CCX_NOOVmode)
-	    sparc_mode_class[i] = 1 << (int) CC_MODE;
-	  else
-	    sparc_mode_class[i] = 0;
-	  break;
-	}
-    }
-
-  if (TARGET_ARCH64)
-    hard_regno_mode_classes = hard_64bit_mode_classes;
-  else
-    hard_regno_mode_classes = hard_32bit_mode_classes;
-
-  /* Initialize the array used by REGNO_REG_CLASS.  */
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      if (i < 16 && TARGET_V8PLUS)
-	sparc_regno_reg_class[i] = I64_REGS;
-      else if (i < 32)
-	sparc_regno_reg_class[i] = GENERAL_REGS;
-      else if (i < 64)
-	sparc_regno_reg_class[i] = FP_REGS;
-      else if (i < 96)
-	sparc_regno_reg_class[i] = EXTRA_FP_REGS;
-      else if (i < 100)
-	sparc_regno_reg_class[i] = FPCC_REGS;
-      else
-	sparc_regno_reg_class[i] = NO_REGS;
-    }
-}
-
-/* Save non call used registers from LOW to HIGH at BASE+OFFSET.
-   N_REGS is the number of 4-byte regs saved thus far.  This applies even to
-   v9 int regs as it simplifies the code.  */
-
-static int
-save_regs (file, low, high, base, offset, n_regs, real_offset)
-     FILE *file;
-     int low, high;
-     char *base;
-     int offset;
-     int n_regs;
-     int real_offset;
-{
-  int i;
-
-  if (TARGET_ARCH64 && high <= 32)
-    {
-      for (i = low; i < high; i++)
-	{
-	  if (regs_ever_live[i] && ! call_used_regs[i])
-	    {
-	      fprintf (file, "\tstx\t%s, [%s+%d]\n",
-		       reg_names[i], base, offset + 4 * n_regs);
-	      if (dwarf2out_do_frame ())
-		dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
-	      n_regs += 2;
-	    }
-	}
-    }
-  else
-    {
-      for (i = low; i < high; i += 2)
-	{
-	  if (regs_ever_live[i] && ! call_used_regs[i])
-	    {
-	      if (regs_ever_live[i+1] && ! call_used_regs[i+1])
-		{
-		  fprintf (file, "\tstd\t%s, [%s+%d]\n",
-			   reg_names[i], base, offset + 4 * n_regs);
-		  if (dwarf2out_do_frame ())
-		    {
-		      char *l = dwarf2out_cfi_label ();
-		      dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
-		      dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
-		    }
-		  n_regs += 2;
-		}
-	      else
-		{
-		  fprintf (file, "\tst\t%s, [%s+%d]\n",
-			   reg_names[i], base, offset + 4 * n_regs);
-		  if (dwarf2out_do_frame ())
-		    dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
-		  n_regs += 2;
-		}
-	    }
-	  else
-	    {
-	      if (regs_ever_live[i+1] && ! call_used_regs[i+1])
-		{
-		  fprintf (file, "\tst\t%s, [%s+%d]\n",
-			   reg_names[i+1], base, offset + 4 * n_regs + 4);
-		  if (dwarf2out_do_frame ())
-		    dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
-		  n_regs += 2;
-		}
-	    }
-	}
-    }
-  return n_regs;
-}
-
-/* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
-
-   N_REGS is the number of 4-byte regs saved thus far.  This applies even to
-   v9 int regs as it simplifies the code.  */
-
-static int
-restore_regs (file, low, high, base, offset, n_regs)
-     FILE *file;
-     int low, high;
-     char *base;
-     int offset;
-     int n_regs;
-{
-  int i;
-
-  if (TARGET_ARCH64 && high <= 32)
-    {
-      for (i = low; i < high; i++)
-	{
-	  if (regs_ever_live[i] && ! call_used_regs[i])
-	    fprintf (file, "\tldx\t[%s+%d], %s\n",
-	      base, offset + 4 * n_regs, reg_names[i]),
-	    n_regs += 2;
-	}
-    }
-  else
-    {
-      for (i = low; i < high; i += 2)
-	{
-	  if (regs_ever_live[i] && ! call_used_regs[i])
-	    if (regs_ever_live[i+1] && ! call_used_regs[i+1])
-	      fprintf (file, "\tldd\t[%s+%d], %s\n",
-		       base, offset + 4 * n_regs, reg_names[i]),
-	      n_regs += 2;
-	    else
-	      fprintf (file, "\tld\t[%s+%d],%s\n",
-		       base, offset + 4 * n_regs, reg_names[i]),
-	      n_regs += 2;
-	  else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
-	    fprintf (file, "\tld\t[%s+%d],%s\n",
-		     base, offset + 4 * n_regs + 4, reg_names[i+1]),
-	    n_regs += 2;
-	}
-    }
-  return n_regs;
-}
-
-/* Static variables we want to share between prologue and epilogue.  */
-
-/* Number of live general or floating point registers needed to be saved
-   (as 4-byte quantities).  This is only done if TARGET_EPILOGUE.  */
-static int num_gfregs;
-
-/* Compute the frame size required by the function.  This function is called
-   during the reload pass and also by output_function_prologue().  */
-
-int
-compute_frame_size (size, leaf_function)
-     int size;
-     int leaf_function;
-{
-  int n_regs = 0, i;
-  int outgoing_args_size = (current_function_outgoing_args_size
-			    + REG_PARM_STACK_SPACE (current_function_decl));
-
-  if (TARGET_EPILOGUE)
-    {
-      /* N_REGS is the number of 4-byte regs saved thus far.  This applies
-	 even to v9 int regs to be consistent with save_regs/restore_regs.  */
-
-      if (TARGET_ARCH64)
-	{
-	  for (i = 0; i < 8; i++)
-	    if (regs_ever_live[i] && ! call_used_regs[i])
-	      n_regs += 2;
-	}
-      else
-	{
-	  for (i = 0; i < 8; i += 2)
-	    if ((regs_ever_live[i] && ! call_used_regs[i])
-		|| (regs_ever_live[i+1] && ! call_used_regs[i+1]))
-	      n_regs += 2;
-	}
-
-      for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
-	if ((regs_ever_live[i] && ! call_used_regs[i])
-	    || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
-	  n_regs += 2;
-    }
-
-  /* Set up values for use in `function_epilogue'.  */
-  num_gfregs = n_regs;
-
-  if (leaf_function && n_regs == 0
-      && size == 0 && current_function_outgoing_args_size == 0)
-    {
-      actual_fsize = apparent_fsize = 0;
-    }
-  else
-    {
-      /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
-         The stack bias (if any) is taken out to undo its effects.  */
-      apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
-      apparent_fsize += n_regs * 4;
-      actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
-    }
-
-  /* Make sure nothing can clobber our register windows.
-     If a SAVE must be done, or there is a stack-local variable,
-     the register window area must be allocated.
-     ??? For v8 we apparently need an additional 8 bytes of reserved space.  */
-  if (leaf_function == 0 || size > 0)
-    actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
-
-  return SPARC_STACK_ALIGN (actual_fsize);
-}
-
-/* Build a (32 bit) big number in a register.  */
-/* ??? We may be able to use the set macro here too.  */
-
-static void
-build_big_number (file, num, reg)
-     FILE *file;
-     int num;
-     char *reg;
-{
-  if (num >= 0 || ! TARGET_ARCH64)
-    {
-      fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
-      if ((num & 0x3ff) != 0)
-	fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
-    }
-  else /* num < 0 && TARGET_ARCH64 */
-    {
-      /* Sethi does not sign extend, so we must use a little trickery
-	 to use it for negative numbers.  Invert the constant before
-	 loading it in, then use xor immediate to invert the loaded bits
-	 (along with the upper 32 bits) to the desired constant.  This
-	 works because the sethi and immediate fields overlap.  */
-      int asize = num;
-      int inv = ~asize;
-      int low = -0x400 + (asize & 0x3FF);
-	  
-      fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
-	       inv, reg, reg, low, reg);
-    }
-}
-
-/* Output code for the function prologue.  */
-
-void
-output_function_prologue (file, size, leaf_function)
-     FILE *file;
-     int size;
-     int leaf_function;
-{
-  /* Need to use actual_fsize, since we are also allocating
-     space for our callee (and our own register save area).  */
-  actual_fsize = compute_frame_size (size, leaf_function);
-
-  if (leaf_function)
-    {
-      frame_base_name = "%sp";
-      frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
-    }
-  else
-    {
-      frame_base_name = "%fp";
-      frame_base_offset = SPARC_STACK_BIAS;
-    }
-
-  /* This is only for the human reader.  */
-  fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
-
-  if (actual_fsize == 0)
-    /* do nothing.  */ ;
-  else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
-    {
-      if (actual_fsize <= 4096)
-	fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
-      else if (actual_fsize <= 8192)
-	{
-	  fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
-	  fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
-	}
-      else
-	{
-	  build_big_number (file, -actual_fsize, "%g1");
-	  fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
-	}
-    }
-  else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
-    {
-      /* We assume the environment will properly handle or otherwise avoid
-	 trouble associated with an interrupt occurring after the `save' or
-	 trap occurring during it.  */
-      fprintf (file, "\tsave\n");
-
-      if (actual_fsize <= 4096)
-	fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize);
-      else if (actual_fsize <= 8192)
-	{
-	  fprintf (file, "\tadd\t%%fp, -4096, %%sp\n");
-	  fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096);
-	}
-      else
-	{
-	  build_big_number (file, -actual_fsize, "%g1");
-	  fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n");
-	}
-    }
-  else /* leaf function */
-    {
-      if (actual_fsize <= 4096)
-	fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
-      else if (actual_fsize <= 8192)
-	{
-	  fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
-	  fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
-	}
-      else
-	{
-	  build_big_number (file, -actual_fsize, "%g1");
-	  fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
-	}
-    }
-
-  if (dwarf2out_do_frame () && actual_fsize)
-    {
-      char *label = dwarf2out_cfi_label ();
-
-      /* The canonical frame address refers to the top of the frame.  */
-      dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
-				 : FRAME_POINTER_REGNUM),
-			 frame_base_offset);
-
-      if (! leaf_function)
-	{
-	  /* Note the register window save.  This tells the unwinder that
-	     it needs to restore the window registers from the previous
-	     frame's window save area at 0(cfa).  */
-	  dwarf2out_window_save (label);
-
-	  /* The return address (-8) is now in %i7.  */
-	  dwarf2out_return_reg (label, 31);
-	}
-    }
-
-  /* If doing anything with PIC, do it now.  */
-  if (! flag_pic)
-    fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
-
-  /* Call saved registers are saved just above the outgoing argument area.  */
-  if (num_gfregs)
-    {
-      int offset, real_offset, n_regs;
-      char *base;
-
-      real_offset = -apparent_fsize;
-      offset = -apparent_fsize + frame_base_offset;
-      if (offset < -4096 || offset + num_gfregs * 4 > 4096)
-	{
-	  /* ??? This might be optimized a little as %g1 might already have a
-	     value close enough that a single add insn will do.  */
-	  /* ??? Although, all of this is probably only a temporary fix
-	     because if %g1 can hold a function result, then
-	     output_function_epilogue will lose (the result will get
-	     clobbered).  */
-	  build_big_number (file, offset, "%g1");
-	  fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
-	  base = "%g1";
-	  offset = 0;
-	}
-      else
-	{
-	  base = frame_base_name;
-	}
-
-      n_regs = 0;
-      if (TARGET_EPILOGUE && ! leaf_function)
-	/* ??? Originally saved regs 0-15 here.  */
-	n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
-      else if (leaf_function)
-	/* ??? Originally saved regs 0-31 here.  */
-	n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
-      if (TARGET_EPILOGUE)
-	save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
-		   real_offset);
-    }
-
-  leaf_label = 0;
-  if (leaf_function && actual_fsize != 0)
-    {
-      /* warning ("leaf procedure with frame size %d", actual_fsize); */
-      if (! TARGET_EPILOGUE)
-	leaf_label = gen_label_rtx ();
-    }
-}
-
-/* Output code for the function epilogue.  */
-
-void
-output_function_epilogue (file, size, leaf_function)
-     FILE *file;
-     int size ATTRIBUTE_UNUSED;
-     int leaf_function;
-{
-  char *ret;
-
-  if (leaf_label)
-    {
-      emit_label_after (leaf_label, get_last_insn ());
-      final_scan_insn (get_last_insn (), file, 0, 0, 1);
-    }
-
-#ifdef FUNCTION_BLOCK_PROFILER_EXIT
-  else if (profile_block_flag == 2)
-    {
-      FUNCTION_BLOCK_PROFILER_EXIT(file);
-    }
-#endif
-
-  else if (current_function_epilogue_delay_list == 0)
-    {                                                
-      /* If code does not drop into the epilogue, we need
-	 do nothing except output pending case vectors.  */
-      rtx insn = get_last_insn ();                               
-      if (GET_CODE (insn) == NOTE)                               
-      insn = prev_nonnote_insn (insn);                           
-      if (insn && GET_CODE (insn) == BARRIER)                    
-      goto output_vectors;                                                    
-    }
-
-  /* Restore any call saved registers.  */
-  if (num_gfregs)
-    {
-      int offset, n_regs;
-      char *base;
-
-      offset = -apparent_fsize + frame_base_offset;
-      if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
-	{
-	  build_big_number (file, offset, "%g1");
-	  fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
-	  base = "%g1";
-	  offset = 0;
-	}
-      else
-	{
-	  base = frame_base_name;
-	}
-
-      n_regs = 0;
-      if (TARGET_EPILOGUE && ! leaf_function)
-	/* ??? Originally saved regs 0-15 here.  */
-	n_regs = restore_regs (file, 0, 8, base, offset, 0);
-      else if (leaf_function)
-	/* ??? Originally saved regs 0-31 here.  */
-	n_regs = restore_regs (file, 0, 8, base, offset, 0);
-      if (TARGET_EPILOGUE)
-	restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
-    }
-
-  /* Work out how to skip the caller's unimp instruction if required.  */
-  if (leaf_function)
-    ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
-  else
-    ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
-
-  if (TARGET_EPILOGUE || leaf_label)
-    {
-      int old_target_epilogue = TARGET_EPILOGUE;
-      target_flags &= ~old_target_epilogue;
-
-      if (! leaf_function)
-	{
-	  /* If we wound up with things in our delay slot, flush them here.  */
-	  if (current_function_epilogue_delay_list)
-	    {
-	      rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
-					       get_last_insn ());
-	      PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
-					gen_rtvec (2,
-						   PATTERN (XEXP (current_function_epilogue_delay_list, 0)),
-						   PATTERN (insn)));
-	      final_scan_insn (insn, file, 1, 0, 1);
-	    }
-	  else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
-	    fputs ("\treturn\t%i7+8\n\tnop\n", file);
-	  else
-	    fprintf (file, "\t%s\n\trestore\n", ret);
-	}
-      /* All of the following cases are for leaf functions.  */
-      else if (current_function_epilogue_delay_list)
-	{
-	  /* eligible_for_epilogue_delay_slot ensures that if this is a
-	     leaf function, then we will only have insn in the delay slot
-	     if the frame size is zero, thus no adjust for the stack is
-	     needed here.  */
-	  if (actual_fsize != 0)
-	    abort ();
-	  fprintf (file, "\t%s\n", ret);
-	  final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
-			   file, 1, 0, 1);
-	}
-      /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
-	 avoid generating confusing assembly language output.  */
-      else if (actual_fsize == 0)
-	fprintf (file, "\t%s\n\tnop\n", ret);
-      else if (actual_fsize <= 4096)
-	fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
-      else if (actual_fsize <= 8192)
-	fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
-		 ret, actual_fsize - 4096);
-      else if ((actual_fsize & 0x3ff) == 0)
-	fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
-		 actual_fsize, ret);
-      else		 
-	fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
-		 actual_fsize, actual_fsize, ret);
-      target_flags |= old_target_epilogue;
-    }
-
- output_vectors:
-  sparc_output_deferred_case_vectors ();
-}
-
-/* Functions for handling argument passing.
-
-   For v8 the first six args are normally in registers and the rest are
-   pushed.  Any arg that starts within the first 6 words is at least
-   partially passed in a register unless its data type forbids.
-
-   For v9, the argument registers are laid out as an array of 16 elements
-   and arguments are added sequentially.  The first 6 int args and up to the
-   first 16 fp args (depending on size) are passed in regs.
-
-   Slot    Stack   Integral   Float   Float in structure   Double   Long Double
-   ----    -----   --------   -----   ------------------   ------   -----------
-    15   [SP+248]              %f31       %f30,%f31         %d30
-    14   [SP+240]              %f29       %f28,%f29         %d28       %q28
-    13   [SP+232]              %f27       %f26,%f27         %d26
-    12   [SP+224]              %f25       %f24,%f25         %d24       %q24
-    11   [SP+216]              %f23       %f22,%f23         %d22
-    10   [SP+208]              %f21       %f20,%f21         %d20       %q20
-     9   [SP+200]              %f19       %f18,%f19         %d18
-     8   [SP+192]              %f17       %f16,%f17         %d16       %q16
-     7   [SP+184]              %f15       %f14,%f15         %d14
-     6   [SP+176]              %f13       %f12,%f13         %d12       %q12
-     5   [SP+168]     %o5      %f11       %f10,%f11         %d10
-     4   [SP+160]     %o4       %f9        %f8,%f9           %d8        %q8
-     3   [SP+152]     %o3       %f7        %f6,%f7           %d6
-     2   [SP+144]     %o2       %f5        %f4,%f5           %d4        %q4
-     1   [SP+136]     %o1       %f3        %f2,%f3           %d2
-     0   [SP+128]     %o0       %f1        %f0,%f1           %d0        %q0
-
-   Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
-
-   Integral arguments are always passed as 64 bit quantities appropriately
-   extended.
-
-   Passing of floating point values is handled as follows.
-   If a prototype is in scope:
-     If the value is in a named argument (i.e. not a stdarg function or a
-     value not part of the `...') then the value is passed in the appropriate
-     fp reg.
-     If the value is part of the `...' and is passed in one of the first 6
-     slots then the value is passed in the appropriate int reg.
-     If the value is part of the `...' and is not passed in one of the first 6
-     slots then the value is passed in memory.
-   If a prototype is not in scope:
-     If the value is one of the first 6 arguments the value is passed in the
-     appropriate integer reg and the appropriate fp reg.
-     If the value is not one of the first 6 arguments the value is passed in
-     the appropriate fp reg and in memory.
-   */
-
-/* Maximum number of int regs for args.  */
-#define SPARC_INT_ARG_MAX 6
-/* Maximum number of fp regs for args.  */
-#define SPARC_FP_ARG_MAX 16
-
-#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Handle the INIT_CUMULATIVE_ARGS macro.
-   Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-
-void
-init_cumulative_args (cum, fntype, libname, indirect)
-     CUMULATIVE_ARGS *cum;
-     tree fntype;
-     tree libname ATTRIBUTE_UNUSED;
-     int indirect ATTRIBUTE_UNUSED;
-{
-  cum->words = 0;
-  cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
-  cum->libcall_p = fntype == 0;
-}
-
-/* Compute the slot number to pass an argument in.
-   Returns the slot number or -1 if passing on the stack.
-
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-   INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
-   *PREGNO records the register number to use if scalar type.
-   *PPADDING records the amount of padding needed in words.  */
-
-static int
-function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
-     const CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-     int incoming_p;
-     int *pregno;
-     int *ppadding;
-{
-  int regbase = (incoming_p
-		 ? SPARC_INCOMING_INT_ARG_FIRST
-		 : SPARC_OUTGOING_INT_ARG_FIRST);
-  int slotno = cum->words;
-  int regno;
-
-  *ppadding = 0;
-
-  if (type != 0 && TREE_ADDRESSABLE (type))
-    return -1;
-  if (TARGET_ARCH32
-      && type != 0 && mode == BLKmode
-      && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
-    return -1;
-
-  switch (mode)
-    {
-    case VOIDmode :
-      /* MODE is VOIDmode when generating the actual call.
-	 See emit_call_1.  */
-      return -1;
-
-    case QImode : case CQImode :
-    case HImode : case CHImode :
-    case SImode : case CSImode :
-    case DImode : case CDImode :
-      if (slotno >= SPARC_INT_ARG_MAX)
-	return -1;
-      regno = regbase + slotno;
-      break;
-
-    case SFmode : case SCmode :
-    case DFmode : case DCmode :
-    case TFmode : case TCmode :
-      if (TARGET_ARCH32)
-	{
-	  if (slotno >= SPARC_INT_ARG_MAX)
-	    return -1;
-	  regno = regbase + slotno;
-	}
-      else
-	{
-	  if ((mode == TFmode || mode == TCmode)
-	      && (slotno & 1) != 0)
-	    slotno++, *ppadding = 1;
-	  if (TARGET_FPU && named)
-	    {
-	      if (slotno >= SPARC_FP_ARG_MAX)
-		return -1;
-	      regno = SPARC_FP_ARG_FIRST + slotno * 2;
-	      if (mode == SFmode)
-		regno++;
-	    }
-	  else
-	    {
-	      if (slotno >= SPARC_INT_ARG_MAX)
-		return -1;
-	      regno = regbase + slotno;
-	    }
-	}
-      break;
-
-    case BLKmode :
-      /* For sparc64, objects requiring 16 byte alignment get it.  */
-      if (TARGET_ARCH64)
-	{
-	  if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
-	    slotno++, *ppadding = 1;
-	}
-
-      if (TARGET_ARCH32
-	  || (type && TREE_CODE (type) == UNION_TYPE))
-	{
-	  if (slotno >= SPARC_INT_ARG_MAX)
-	    return -1;
-	  regno = regbase + slotno;
-	}
-      else
-	{
-	  tree field;
-	  int intregs_p = 0, fpregs_p = 0;
-	  /* The ABI obviously doesn't specify how packed
-	     structures are passed.  These are defined to be passed
-	     in int regs if possible, otherwise memory.  */
-	  int packed_p = 0;
-
-	  /* First see what kinds of registers we need.  */
-	  for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
-	    {
-	      if (TREE_CODE (field) == FIELD_DECL)
-		{
-		  if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
-		      && TARGET_FPU)
-		    fpregs_p = 1;
-		  else
-		    intregs_p = 1;
-		  if (DECL_PACKED (field))
-		    packed_p = 1;
-		}
-	    }
-	  if (packed_p || !named)
-	    fpregs_p = 0, intregs_p = 1;
-
-	  /* If all arg slots are filled, then must pass on stack.  */
-	  if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
-	    return -1;
-	  /* If there are only int args and all int arg slots are filled,
-	     then must pass on stack.  */
-	  if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
-	    return -1;
-	  /* Note that even if all int arg slots are filled, fp members may
-	     still be passed in regs if such regs are available.
-	     *PREGNO isn't set because there may be more than one, it's up
-	     to the caller to compute them.  */
-	  return slotno;
-	}
-      break;
-
-    default :
-      abort ();
-    }
-
-  *pregno = regno;
-  return slotno;
-}
-
-/* Handle recursive register counting for structure field layout.  */
-
-struct function_arg_record_value_parms
-{
-  rtx ret;
-  int slotno, named, regbase;
-  int nregs, intoffset;
-};
-
-static void function_arg_record_value_3
-	PROTO((int, struct function_arg_record_value_parms *));
-static void function_arg_record_value_2
-	PROTO((tree, int, struct function_arg_record_value_parms *));
-static rtx function_arg_record_value
-	PROTO((tree, enum machine_mode, int, int, int));
-
-static void
-function_arg_record_value_1 (type, startbitpos, parms)
-     tree type;
-     int startbitpos;
-     struct function_arg_record_value_parms *parms;
-{
-  tree field;
-
-  /* The ABI obviously doesn't specify how packed structures are
-     passed.  These are defined to be passed in int regs if possible,
-     otherwise memory.  */
-  int packed_p = 0;
-
-  /* We need to compute how many registers are needed so we can
-     allocate the PARALLEL but before we can do that we need to know
-     whether there are any packed fields.  If there are, int regs are
-     used regardless of whether there are fp values present.  */
-  for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
-    {
-      if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
-	{
-	  packed_p = 1;
-	  break;
-	}
-    }
-
-  /* Compute how many registers we need.  */
-  for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
-    {
-      if (TREE_CODE (field) == FIELD_DECL)
-	{
-	  int bitpos = startbitpos;
-	  if (DECL_FIELD_BITPOS (field))
-	    bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
-	  /* ??? FIXME: else assume zero offset.  */
-
-	  if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
-	    {
-	      function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
-	    }
-	  else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
-	           && TARGET_FPU
-	           && ! packed_p
-	           && parms->named)
-	    {
-	      if (parms->intoffset != -1)
-		{
-		  int intslots, this_slotno;
-
-		  intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
-		    / BITS_PER_WORD;
-		  this_slotno = parms->slotno + parms->intoffset
-		    / BITS_PER_WORD;
-
-		  intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
-		  intslots = MAX (intslots, 0);
-		  parms->nregs += intslots;
-		  parms->intoffset = -1;
-		}
-
-	      /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
-		 If it wasn't true we wouldn't be here.  */
-	      parms->nregs += 1;
-	    }
-	  else
-	    {
-	      if (parms->intoffset == -1)
-		parms->intoffset = bitpos;
-	    }
-	}
-    }
-}
-
-/* Handle recursive structure field register assignment.  */
-
-static void 
-function_arg_record_value_3 (bitpos, parms)
-     int bitpos;
-     struct function_arg_record_value_parms *parms;
-{
-  enum machine_mode mode;
-  int regno, this_slotno, intslots, intoffset;
-  rtx reg;
-
-  if (parms->intoffset == -1)
-    return;
-  intoffset = parms->intoffset;
-  parms->intoffset = -1;
-
-  intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD;
-  this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
-
-  intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
-  if (intslots <= 0)
-    return;
-
-  /* If this is the trailing part of a word, only load that much into
-     the register.  Otherwise load the whole register.  Note that in
-     the latter case we may pick up unwanted bits.  It's not a problem
-     at the moment but may wish to revisit.  */
-
-  if (intoffset % BITS_PER_WORD != 0)
-    {
-      mode = mode_for_size (BITS_PER_WORD - intoffset%BITS_PER_WORD,
-			    MODE_INT, 0);
-    }
-  else
-    mode = word_mode;
-
-  intoffset /= BITS_PER_UNIT;
-  do
-    {
-      regno = parms->regbase + this_slotno;
-      reg = gen_rtx_REG (mode, regno);
-      XVECEXP (parms->ret, 0, parms->nregs)
-	= gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
-
-      this_slotno += 1;
-      intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
-      parms->nregs += 1;
-      intslots -= 1;
-    }
-  while (intslots > 0);
-}
-
-static void
-function_arg_record_value_2 (type, startbitpos, parms)
-     tree type;
-     int startbitpos;
-     struct function_arg_record_value_parms *parms;
-{
-  tree field;
-  int packed_p = 0;
-
-  for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
-    {
-      if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
-	{
-	  packed_p = 1;
-	  break;
-	}
-    }
-
-  for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
-    {
-      if (TREE_CODE (field) == FIELD_DECL)
-	{
-	  int bitpos = startbitpos;
-	  if (DECL_FIELD_BITPOS (field))
-	    bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
-	  /* ??? FIXME: else assume zero offset.  */
-
-	  if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
-	    {
-	      function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
-	    }
-	  else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
-	           && TARGET_FPU
-	           && ! packed_p
-	           && parms->named)
-	    {
-	      int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
-	      rtx reg;
-
-	      function_arg_record_value_3 (bitpos, parms);
-
-	      reg = gen_rtx_REG (DECL_MODE (field),
-			         (SPARC_FP_ARG_FIRST + this_slotno * 2
-			          + (DECL_MODE (field) == SFmode
-				     && (bitpos & 32) != 0)));
-	      XVECEXP (parms->ret, 0, parms->nregs)
-		= gen_rtx_EXPR_LIST (VOIDmode, reg,
-			   GEN_INT (bitpos / BITS_PER_UNIT));
-	      parms->nregs += 1;
-	    }
-	  else
-	    {
-	      if (parms->intoffset == -1)
-		parms->intoffset = bitpos;
-	    }
-	}
-    }
-}
-
-static rtx
-function_arg_record_value (type, mode, slotno, named, regbase)
-     tree type;
-     enum machine_mode mode;
-     int slotno, named, regbase;
-{
-  HOST_WIDE_INT typesize = int_size_in_bytes (type);
-  struct function_arg_record_value_parms parms;
-  int nregs;
-
-  parms.ret = NULL_RTX;
-  parms.slotno = slotno;
-  parms.named = named;
-  parms.regbase = regbase;
-
-  /* Compute how many registers we need.  */
-  parms.nregs = 0;
-  parms.intoffset = 0;
-  function_arg_record_value_1 (type, 0, &parms);
-
-  if (parms.intoffset != -1)
-    {
-      int intslots, this_slotno;
-
-      intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1)
-	/ BITS_PER_WORD;
-      this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
-
-      intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
-      intslots = MAX (intslots, 0);
-
-      parms.nregs += intslots;
-    }
-  nregs = parms.nregs;
-
-  /* Allocate the vector and handle some annoying special cases.  */
-  if (nregs == 0)
-    {
-      /* ??? Empty structure has no value?  Duh?  */
-      if (typesize <= 0)
-	{
-	  /* Though there's nothing really to store, return a word register
-	     anyway so the rest of gcc doesn't go nuts.  Returning a PARALLEL
-	     leads to breakage due to the fact that there are zero bytes to
-	     load.  */
-	  return gen_rtx_REG (mode, regbase);
-	}
-      else
-	{
-	  /* ??? C++ has structures with no fields, and yet a size.  Give up
-	     for now and pass everything back in integer registers.  */
-	  nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
-	}
-      if (nregs + slotno > SPARC_INT_ARG_MAX)
-	nregs = SPARC_INT_ARG_MAX - slotno;
-    }
-  if (nregs == 0)
-    abort ();
-
-  parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
-
-  /* Fill in the entries.  */
-  parms.nregs = 0;
-  parms.intoffset = 0;
-  function_arg_record_value_2 (type, 0, &parms);
-  function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
-
-  if (parms.nregs != nregs)
-    abort ();
-
-  return parms.ret;
-}
-
-/* Handle the FUNCTION_ARG macro.
-   Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-   INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.  */
-
-rtx
-function_arg (cum, mode, type, named, incoming_p)
-     const CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-     int incoming_p;
-{
-  int regbase = (incoming_p
-		 ? SPARC_INCOMING_INT_ARG_FIRST
-		 : SPARC_OUTGOING_INT_ARG_FIRST);
-  int slotno, regno, padding;
-  rtx reg;
-
-  slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
-				&regno, &padding);
-
-  if (slotno == -1)
-    return 0;
-
-  if (TARGET_ARCH32)
-    {
-      reg = gen_rtx_REG (mode, regno);
-      return reg;
-    }
-
-  /* v9 fp args in reg slots beyond the int reg slots get passed in regs
-     but also have the slot allocated for them.
-     If no prototype is in scope fp values in register slots get passed
-     in two places, either fp regs and int regs or fp regs and memory.  */
-  if ((GET_MODE_CLASS (mode) == MODE_FLOAT
-       || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
-      && SPARC_FP_REG_P (regno))
-    {
-      reg = gen_rtx_REG (mode, regno);
-      if (cum->prototype_p || cum->libcall_p)
-	{
-	  /* "* 2" because fp reg numbers are recorded in 4 byte
-	     quantities.  */
-#if 0
-	  /* ??? This will cause the value to be passed in the fp reg and
-	     in the stack.  When a prototype exists we want to pass the
-	     value in the reg but reserve space on the stack.  That's an
-	     optimization, and is deferred [for a bit].  */
-	  if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
-	    return gen_rtx_PARALLEL (mode,
-			    gen_rtvec (2,
-				       gen_rtx_EXPR_LIST (VOIDmode,
-						NULL_RTX, const0_rtx),
-				       gen_rtx_EXPR_LIST (VOIDmode,
-						reg, const0_rtx)));
-	  else
-#else
-	  /* ??? It seems that passing back a register even when past
-	     the area declared by REG_PARM_STACK_SPACE will allocate
-	     space appropriately, and will not copy the data onto the
-	     stack, exactly as we desire.
-
-	     This is due to locate_and_pad_parm being called in
-	     expand_call whenever reg_parm_stack_space > 0, which
-	     while benefical to our example here, would seem to be
-	     in error from what had been intended.  Ho hum...  -- r~ */
-#endif
-	    return reg;
-	}
-      else
-	{
-	  rtx v0, v1;
-
-	  if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
-	    {
-	      int intreg;
-
-	      /* On incoming, we don't need to know that the value
-		 is passed in %f0 and %i0, and it confuses other parts
-		 causing needless spillage even on the simplest cases.  */
-	      if (incoming_p)
-		return reg;
-
-	      intreg = (SPARC_OUTGOING_INT_ARG_FIRST
-			+ (regno - SPARC_FP_ARG_FIRST) / 2);
-
-	      v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
-	      v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
-				      const0_rtx);
-	      return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
-	    }
-	  else
-	    {
-	      v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
-	      v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
-	      return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
-	    }
-	}
-    }
-  else if (type && TREE_CODE (type) == RECORD_TYPE)
-    {
-      /* Structures up to 16 bytes in size are passed in arg slots on the
-	 stack and are promoted to registers where possible.  */
-
-      if (int_size_in_bytes (type) > 16)
-	abort (); /* shouldn't get here */
-
-      return function_arg_record_value (type, mode, slotno, named, regbase);
-    }
-  else if (type && TREE_CODE (type) == UNION_TYPE)
-    {
-      enum machine_mode mode;
-      int bytes = int_size_in_bytes (type);
-
-      if (bytes > 16)
-	abort ();
-
-      mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
-      reg = gen_rtx_REG (mode, regno);
-    }
-  else
-    {
-      /* Scalar or complex int.  */
-      reg = gen_rtx_REG (mode, regno);
-    }
-
-  return reg;
-}
-
-/* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
-   For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.
-
-   Any arg that starts in the first 6 regs but won't entirely fit in them
-   needs partial registers on v8.  On v9, structures with integer
-   values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
-   values that begin in the last fp reg [where "last fp reg" varies with the
-   mode] will be split between that reg and memory.  */
-
-int
-function_arg_partial_nregs (cum, mode, type, named)
-     const CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int slotno, regno, padding;
-
-  /* We pass 0 for incoming_p here, it doesn't matter.  */
-  slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
-
-  if (slotno == -1)
-    return 0;
-
-  if (TARGET_ARCH32)
-    {
-      if ((slotno + (mode == BLKmode
-		     ? ROUND_ADVANCE (int_size_in_bytes (type))
-		     : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
-	  > NPARM_REGS (SImode))
-	return NPARM_REGS (SImode) - slotno;
-      return 0;
-    }
-  else
-    {
-      if (type && AGGREGATE_TYPE_P (type))
-	{
-	  int size = int_size_in_bytes (type);
-	  int align = TYPE_ALIGN (type);
-
-	  if (align == 16)
-	    slotno += slotno & 1;
-	  if (size > 8 && size <= 16
-	      && slotno == SPARC_INT_ARG_MAX - 1)
-	    return 1;
-	}
-      else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
-	       || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
-		   && ! TARGET_FPU))
-	{
-	  if (GET_MODE_ALIGNMENT (mode) == 128)
-	    {
-	      slotno += slotno & 1;
-	      if (slotno == SPARC_INT_ARG_MAX - 2)
-		return 1;
-	    }
-	  else
-	    {
-	      if (slotno == SPARC_INT_ARG_MAX - 1)
-		return 1;
-	    }
-	}
-      else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
-	{
-	  if (GET_MODE_ALIGNMENT (mode) == 128)
-	    slotno += slotno & 1;
-	  if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
-	      > SPARC_FP_ARG_MAX)
-	    return 1;
-	}
-      return 0;
-    }
-}
-
-/* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
-   !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
-   quad-precision floats by invisible reference.
-   v9: Aggregates greater than 16 bytes are passed by reference.
-   For Pascal, also pass arrays by reference.  */
-
-int
-function_arg_pass_by_reference (cum, mode, type, named)
-     const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
-     enum machine_mode mode;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
-{
-  if (TARGET_ARCH32)
-    {
-      return ((type && AGGREGATE_TYPE_P (type))
-	      || mode == TFmode || mode == TCmode);
-    }
-  else
-    {
-      return ((type && TREE_CODE (type) == ARRAY_TYPE)
-	      /* Consider complex values as aggregates, so care for TCmode. */
-	      || GET_MODE_SIZE (mode) > 16
-	      || (type && AGGREGATE_TYPE_P (type)
-		  && int_size_in_bytes (type) > 16));
-    }
-}
-
-/* Handle the FUNCTION_ARG_ADVANCE macro.
-   Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   TYPE is null for libcalls where that information may not be available.  */
-
-void
-function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int slotno, regno, padding;
-
-  /* We pass 0 for incoming_p here, it doesn't matter.  */
-  slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
-
-  /* If register required leading padding, add it.  */
-  if (slotno != -1)
-    cum->words += padding;
-
-  if (TARGET_ARCH32)
-    {
-      cum->words += (mode != BLKmode
-		     ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
-		     : ROUND_ADVANCE (int_size_in_bytes (type)));
-    }
-  else
-    {
-      if (type && AGGREGATE_TYPE_P (type))
-	{
-	  int size = int_size_in_bytes (type);
-
-	  if (size <= 8)
-	    ++cum->words;
-	  else if (size <= 16)
-	    cum->words += 2;
-	  else /* passed by reference */
-	    ++cum->words;
-	}
-      else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
-	{
-	  cum->words += 2;
-	}
-      else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
-	{
-	  cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
-	}
-      else
-	{
-	  cum->words += (mode != BLKmode
-			 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
-			 : ROUND_ADVANCE (int_size_in_bytes (type)));
-	}
-    }
-}
-
-/* Handle the FUNCTION_ARG_PADDING macro.
-   For the 64 bit ABI structs are always stored left shifted in their
-   argument slot.  */
-
-enum direction
-function_arg_padding (mode, type)
-     enum machine_mode mode;
-     tree type;
-{
-  if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
-    return upward;
-
-  /* This is the default definition.  */
-  return (! BYTES_BIG_ENDIAN
-	  ? upward
-	  : ((mode == BLKmode
-	      ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
-		 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
-	      : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
-	     ? downward : upward));
-}
-
-/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
-   For v9, function return values are subject to the same rules as arguments,
-   except that up to 32-bytes may be returned in registers.  */
-
-rtx
-function_value (type, mode, incoming_p)
-     tree type;
-     enum machine_mode mode;
-     int incoming_p;
-{
-  int regno;
-  int regbase = (incoming_p
-		 ? SPARC_OUTGOING_INT_ARG_FIRST
-		 : SPARC_INCOMING_INT_ARG_FIRST);
-
-  if (TARGET_ARCH64 && type)
-    {
-      if (TREE_CODE (type) == RECORD_TYPE)
-	{
-	  /* Structures up to 32 bytes in size are passed in registers,
-	     promoted to fp registers where possible.  */
-
-	  if (int_size_in_bytes (type) > 32)
-	    abort (); /* shouldn't get here */
-
-	  return function_arg_record_value (type, mode, 0, 1, regbase);
-	}
-      else if (TREE_CODE (type) == UNION_TYPE)
-	{
-	  int bytes = int_size_in_bytes (type);
-
-	  if (bytes > 32)
-	    abort ();
-
-	  mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
-	}
-    }
-    
-  if (TARGET_ARCH64
-      && GET_MODE_CLASS (mode) == MODE_INT 
-      && GET_MODE_SIZE (mode) < UNITS_PER_WORD
-      && type && TREE_CODE (type) != UNION_TYPE)
-    mode = DImode;
-
-  if (incoming_p)
-    regno = BASE_RETURN_VALUE_REG (mode);
-  else
-    regno = BASE_OUTGOING_VALUE_REG (mode);
-
-  return gen_rtx_REG (mode, regno);
-}
-
-/* Do what is necessary for `va_start'.  The argument is ignored.
-
-   We look at the current function to determine if stdarg or varargs
-   is used and return the address of the first unnamed parameter.  */
-
-rtx
-sparc_builtin_saveregs (arglist)
-     tree arglist ATTRIBUTE_UNUSED;
-{
-  int first_reg = current_function_args_info.words;
-  rtx address;
-  int regno;
-
-  for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
-    emit_move_insn (gen_rtx_MEM (word_mode,
-			     gen_rtx_PLUS (Pmode,
-				      frame_pointer_rtx,
-				      GEN_INT (STACK_POINTER_OFFSET
-					       + UNITS_PER_WORD * regno))),
-		    gen_rtx_REG (word_mode,
-			     BASE_INCOMING_ARG_REG (word_mode) + regno));
-
-  address = gen_rtx_PLUS (Pmode,
-		     frame_pointer_rtx,
-		     GEN_INT (STACK_POINTER_OFFSET
-			      + UNITS_PER_WORD * first_reg));
-
-  if (current_function_check_memory_usage
-      && first_reg < NPARM_REGS (word_mode))
-    emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
-		       address, ptr_mode,
-		       GEN_INT (UNITS_PER_WORD 
-			 	* (NPARM_REGS (word_mode) - first_reg)),
-		       TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW),
-		       TYPE_MODE (integer_type_node));
-
-  return address;
-}
-
-/* Return the string to output a conditional branch to LABEL, which is
-   the operand number of the label.  OP is the conditional expression.
-   XEXP (OP, 0) is assumed to be a condition code register (integer or
-   floating point) and its mode specifies what kind of comparison we made.
-
-   REVERSED is non-zero if we should reverse the sense of the comparison.
-
-   ANNUL is non-zero if we should generate an annulling branch.
-
-   NOOP is non-zero if we have to follow this branch by a noop.
-
-   INSN, if set, is the insn.  */
-
-char *
-output_cbranch (op, label, reversed, annul, noop, insn)
-     rtx op;
-     int label;
-     int reversed, annul, noop;
-     rtx insn;
-{
-  static char string[32];
-  enum rtx_code code = GET_CODE (op);
-  rtx cc_reg = XEXP (op, 0);
-  enum machine_mode mode = GET_MODE (cc_reg);
-  static char v8_labelno[] = "%lX";
-  static char v9_icc_labelno[] = "%%icc, %lX";
-  static char v9_xcc_labelno[] = "%%xcc, %lX";
-  static char v9_fcc_labelno[] = "%%fccX, %lY";
-  char *labelno;
-  int labeloff, spaces = 8;
-
-  /* ??? !v9: FP branches cannot be preceded by another floating point insn.
-     Because there is currently no concept of pre-delay slots, we can fix
-     this only by always emitting a nop before a floating point branch.  */
-
-  if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9)
-    strcpy (string, "nop\n\t");
-  else
-    string[0] = '\0';
-
-  /* If not floating-point or if EQ or NE, we can just reverse the code.  */
-  if (reversed
-      && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE))
-    code = reverse_condition (code), reversed = 0;
-
-  /* Start by writing the branch condition.  */
-  switch (code)
-    {
-    case NE:
-      if (mode == CCFPmode || mode == CCFPEmode)
-	{
-	  strcat (string, "fbne");
-	  spaces -= 4;
-	}
-      else
-	{
-	  strcpy (string, "bne");
-	  spaces -= 3;
-	}
-      break;
-
-    case EQ:
-      if (mode == CCFPmode || mode == CCFPEmode)
-	{
-	  strcat (string, "fbe");
-	  spaces -= 3;
-	}
-      else
-	{
-	  strcpy (string, "be");
-	  spaces -= 2;
-	}
-      break;
-
-    case GE:
-      if (mode == CCFPmode || mode == CCFPEmode)
-	{
-	  if (reversed)
-	    strcat (string, "fbul");
-	  else
-	    strcat (string, "fbge");
-	  spaces -= 4;
-	}
-      else if (mode == CC_NOOVmode)
-	{
-	  strcpy (string, "bpos");
-	  spaces -= 4;
-	}
-      else
-	{
-	  strcpy (string, "bge");
-	  spaces -= 3;
-	}
-      break;
-
-    case GT:
-      if (mode == CCFPmode || mode == CCFPEmode)
-	{
-	  if (reversed)
-	    {
-	      strcat (string, "fbule");
-	      spaces -= 5;
-	    }
-	  else
-	    {
-	      strcat (string, "fbg");
-	      spaces -= 3;
-	    }
-	}
-      else
-	{
-	  strcpy (string, "bg");
-	  spaces -= 2;
-	}
-      break;
-
-    case LE:
-      if (mode == CCFPmode || mode == CCFPEmode)
-	{
-	  if (reversed)
-	    strcat (string, "fbug");
-	  else
-	    strcat (string, "fble");
-	  spaces -= 4;
-	}
-      else
-	{
-	  strcpy (string, "ble");
-	  spaces -= 3;
-	}
-      break;
-
-    case LT:
-      if (mode == CCFPmode || mode == CCFPEmode)
-	{
-	  if (reversed)
-	    {
-	      strcat (string, "fbuge");
-	      spaces -= 5;
-	    }
-	  else
-	    {
-	      strcat (string, "fbl");
-	      spaces -= 3;
-	    }
-	}
-      else if (mode == CC_NOOVmode)
-	{
-	  strcpy (string, "bneg");
-	  spaces -= 4;
-	}
-      else
-	{
-	  strcpy (string, "bl");
-	  spaces -= 2;
-	}
-      break;
-
-    case GEU:
-      strcpy (string, "bgeu");
-      spaces -= 4;
-      break;
-
-    case GTU:
-      strcpy (string, "bgu");
-      spaces -= 3;
-      break;
-
-    case LEU:
-      strcpy (string, "bleu");
-      spaces -= 4;
-      break;
-
-    case LTU:
-      strcpy (string, "blu");
-      spaces -= 3;
-      break;
-
-    default:
-      abort ();
-    }
-
-  /* Now add the annulling, the label, and a possible noop.  */
-  if (annul)
-    {
-      strcat (string, ",a");
-      spaces -= 2;
-    }
-
-  if (! TARGET_V9)
-    {
-      labeloff = 2;
-      labelno = v8_labelno;
-    }
-  else
-    {
-      rtx note;
-
-      if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
-	{
-	  strcat (string,
-		  INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
-	  spaces -= 3;
-	}
-
-      labeloff = 9;
-      if (mode == CCFPmode || mode == CCFPEmode)
-	{
-	  labeloff = 10;
-	  labelno = v9_fcc_labelno;
-	  /* Set the char indicating the number of the fcc reg to use.  */
-	  labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
-	}
-      else if (mode == CCXmode || mode == CCX_NOOVmode)
-	labelno = v9_xcc_labelno;
-      else
-	labelno = v9_icc_labelno;
-    }
-  /* Set the char indicating the number of the operand containing the
-     label_ref.  */
-  labelno[labeloff] = label + '0';
-  if (spaces > 0)
-    strcat (string, "\t");
-  else
-    strcat (string, " ");
-  strcat (string, labelno);
-
-  if (noop)
-    strcat (string, "\n\tnop");
-
-  return string;
-}
-
-/* Return the string to output a conditional branch to LABEL, testing
-   register REG.  LABEL is the operand number of the label; REG is the
-   operand number of the reg.  OP is the conditional expression.  The mode
-   of REG says what kind of comparison we made.
-
-   REVERSED is non-zero if we should reverse the sense of the comparison.
-
-   ANNUL is non-zero if we should generate an annulling branch.
-
-   NOOP is non-zero if we have to follow this branch by a noop.  */
-
-char *
-output_v9branch (op, reg, label, reversed, annul, noop, insn)
-     rtx op;
-     int reg, label;
-     int reversed, annul, noop;
-     rtx insn;
-{
-  static char string[20];
-  enum rtx_code code = GET_CODE (op);
-  enum machine_mode mode = GET_MODE (XEXP (op, 0));
-  static char labelno[] = "%X, %lX";
-  rtx note;
-  int spaces = 8;
-
-  /* If not floating-point or if EQ or NE, we can just reverse the code.  */
-  if (reversed)
-    code = reverse_condition (code), reversed = 0;
-
-  /* Only 64 bit versions of these instructions exist.  */
-  if (mode != DImode)
-    abort ();
-
-  /* Start by writing the branch condition.  */
-
-  switch (code)
-    {
-    case NE:
-      strcpy (string, "brnz");
-      spaces -= 4;
-      break;
-
-    case EQ:
-      strcpy (string, "brz");
-      spaces -= 3;
-      break;
-
-    case GE:
-      strcpy (string, "brgez");
-      spaces -= 5;
-      break;
-
-    case LT:
-      strcpy (string, "brlz");
-      spaces -= 4;
-      break;
-
-    case LE:
-      strcpy (string, "brlez");
-      spaces -= 5;
-      break;
-
-    case GT:
-      strcpy (string, "brgz");
-      spaces -= 4;
-      break;
-
-    default:
-      abort ();
-    }
-
-  /* Now add the annulling, reg, label, and nop.  */
-  if (annul)
-    {
-      strcat (string, ",a");
-      spaces -= 2;
-    }
-
-  if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
-    {
-      strcat (string,
-	      INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
-      spaces -= 3;
-    }
-
-  labelno[1] = reg + '0';
-  labelno[6] = label + '0';
-  if (spaces > 0)
-    strcat (string, "\t");
-  else
-    strcat (string, " ");
-  strcat (string, labelno);
-
-  if (noop)
-    strcat (string, "\n\tnop");
-
-  return string;
-}
-
-/* Renumber registers in delay slot.  Replace registers instead of
-   renumbering because they may be shared.
-
-   This does not handle instructions other than move.  */
-
-static void
-epilogue_renumber (where)
-     rtx *where;
-{
-  rtx x = *where;
-  enum rtx_code code = GET_CODE (x);
-
-  switch (code)
-    {
-    case MEM:
-      *where = x = copy_rtx (x);
-      epilogue_renumber (&XEXP (x, 0));
-      return;
-
-    case REG:
-      {
-	int regno = REGNO (x);
-	if (regno > 8 && regno < 24)
-	  abort ();
-	if (regno >= 24 && regno < 32)
-	  *where = gen_rtx_REG (GET_MODE (x), regno - 16);
-	return;
-      }
-    case CONST_INT:
-    case CONST_DOUBLE:
-    case CONST:
-    case SYMBOL_REF:
-    case LABEL_REF:
-      return;
-
-    case IOR:
-    case AND:
-    case XOR:
-    case PLUS:
-    case MINUS:
-      epilogue_renumber (&XEXP (x, 1));
-    case NEG:
-    case NOT:
-      epilogue_renumber (&XEXP (x, 0));
-      return;
-
-    default:
-      debug_rtx (*where);
-      abort ();
-    }
-}
-
-/* Output assembler code to return from a function.  */
-
-char *
-output_return (operands)
-     rtx *operands;
-{
-  rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
-
-  if (leaf_label)
-    {
-      operands[0] = leaf_label;
-      return "b%* %l0%(";
-    }
-  else if (leaf_function)
-    {
-      /* No delay slot in a leaf function.  */
-      if (delay)
-	abort ();
-
-      /* If we didn't allocate a frame pointer for the current function,
-	 the stack pointer might have been adjusted.  Output code to
-	 restore it now.  */
-
-      operands[0] = GEN_INT (actual_fsize);
-
-      /* Use sub of negated value in first two cases instead of add to
-	 allow actual_fsize == 4096.  */
-
-      if (actual_fsize <= 4096)
-	{
-	  if (SKIP_CALLERS_UNIMP_P)
-	    return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
-	  else
-	    return "retl\n\tsub\t%%sp, -%0, %%sp";
-	}
-      else if (actual_fsize <= 8192)
-	{
-	  operands[0] = GEN_INT (actual_fsize - 4096);
-	  if (SKIP_CALLERS_UNIMP_P)
-	    return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
-	  else
-	    return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
-	}
-      else if (SKIP_CALLERS_UNIMP_P)
-	{
-	  if ((actual_fsize & 0x3ff) != 0)
-	    return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
-	  else
-	    return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
-	}
-      else
-	{
-	  if ((actual_fsize & 0x3ff) != 0)
-	    return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
-	  else
-	    return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
-	}
-    }
-  else if (TARGET_V9)
-    {
-      if (delay)
-	{
-	  epilogue_renumber (&SET_DEST (PATTERN (delay)));
-	  epilogue_renumber (&SET_SRC (PATTERN (delay)));
-	}
-      if (SKIP_CALLERS_UNIMP_P)
-	return "return\t%%i7+12%#";
-      else
-	return "return\t%%i7+8%#";
-    }
-  else
-    {
-      if (delay)
-	abort ();
-      if (SKIP_CALLERS_UNIMP_P)
-	return "jmp\t%%i7+12\n\trestore";
-      else
-	return "ret\n\trestore";
-    }
-}
-
-/* Leaf functions and non-leaf functions have different needs.  */
-
-static int
-reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
-
-static int
-reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
-
-static int *reg_alloc_orders[] = {
-  reg_leaf_alloc_order,
-  reg_nonleaf_alloc_order};
-
-void
-order_regs_for_local_alloc ()
-{
-  static int last_order_nonleaf = 1;
-
-  if (regs_ever_live[15] != last_order_nonleaf)
-    {
-      last_order_nonleaf = !last_order_nonleaf;
-      bcopy ((char *) reg_alloc_orders[last_order_nonleaf],
-	     (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int));
-    }
-}
-
-/* Return 1 if REG and MEM are legitimate enough to allow the various
-   mem<-->reg splits to be run.  */
-
-int
-sparc_splitdi_legitimate (reg, mem)
-     rtx reg;
-     rtx mem;
-{
-  /* Punt if we are here by mistake.  */
-  if (! reload_completed)
-    abort ();
-
-  /* We must have an offsettable memory reference.  */
-  if (! offsettable_memref_p (mem))
-    return 0;
-
-  /* If we have legitimate args for ldd/std, we do not want
-     the split to happen.  */
-  if ((REGNO (reg) % 2) == 0
-      && mem_min_alignment (mem, 8))
-    return 0;
-
-  /* Success.  */
-  return 1;
-}
-
-/* Return 1 if x and y are some kind of REG and they refer to
-   different hard registers.  This test is guarenteed to be
-   run after reload.  */
-
-int
-sparc_absnegfloat_split_legitimate (x, y)
-     rtx x, y;
-{
-  if (GET_CODE (x) == SUBREG)
-    x = alter_subreg (x);
-  if (GET_CODE (x) != REG)
-    return 0;
-  if (GET_CODE (y) == SUBREG)
-    y = alter_subreg (y);
-  if (GET_CODE (y) != REG)
-    return 0;
-  if (REGNO (x) == REGNO (y))
-    return 0;
-  return 1;
-}
-
-/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
-   This makes them candidates for using ldd and std insns. 
-
-   Note reg1 and reg2 *must* be hard registers.  */
-
-int
-registers_ok_for_ldd_peep (reg1, reg2)
-     rtx reg1, reg2;
-{
-  /* We might have been passed a SUBREG.  */
-  if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 
-    return 0;
-
-  if (REGNO (reg1) % 2 != 0)
-    return 0;
-
-  /* Integer ldd is deprecated in SPARC V9 */ 
-  if (TARGET_V9 && REGNO (reg1) < 32)                  
-    return 0;                             
-
-  return (REGNO (reg1) == REGNO (reg2) - 1);
-}
-
-/* Return 1 if addr1 and addr2 are suitable for use in an ldd or 
-   std insn.
-
-   This can only happen when addr1 and addr2 are consecutive memory
-   locations (addr1 + 4 == addr2).  addr1 must also be aligned on a 
-   64 bit boundary (addr1 % 8 == 0).  
-
-   We know %sp and %fp are kept aligned on a 64 bit boundary.  Other
-   registers are assumed to *never* be properly aligned and are 
-   rejected.
-
-   Knowing %sp and %fp are kept aligned on a 64 bit boundary, we 
-   need only check that the offset for addr1 % 8 == 0.  */
-
-int
-addrs_ok_for_ldd_peep (addr1, addr2)
-      rtx addr1, addr2;
-{
-  int reg1, offset1;
-
-  /* Extract a register number and offset (if used) from the first addr.  */
-  if (GET_CODE (addr1) == PLUS)
-    {
-      /* If not a REG, return zero.  */
-      if (GET_CODE (XEXP (addr1, 0)) != REG)
-	return 0;
-      else
-	{
-          reg1 = REGNO (XEXP (addr1, 0));
-	  /* The offset must be constant!  */
-	  if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
-            return 0;
-          offset1 = INTVAL (XEXP (addr1, 1));
-	}
-    }
-  else if (GET_CODE (addr1) != REG)
-    return 0;
-  else
-    {
-      reg1 = REGNO (addr1);
-      /* This was a simple (mem (reg)) expression.  Offset is 0.  */
-      offset1 = 0;
-    }
-
-  /* Make sure the second address is a (mem (plus (reg) (const_int).  */
-  if (GET_CODE (addr2) != PLUS)
-    return 0;
-
-  if (GET_CODE (XEXP (addr2, 0)) != REG
-      || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
-    return 0;
-
-  /* Only %fp and %sp are allowed.  Additionally both addresses must
-     use the same register.  */
-  if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
-    return 0;
-
-  if (reg1 != REGNO (XEXP (addr2, 0)))
-    return 0;
-
-  /* The first offset must be evenly divisible by 8 to ensure the 
-     address is 64 bit aligned.  */
-  if (offset1 % 8 != 0)
-    return 0;
-
-  /* The offset for the second addr must be 4 more than the first addr.  */
-  if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
-    return 0;
-
-  /* All the tests passed.  addr1 and addr2 are valid for ldd and std
-     instructions.  */
-  return 1;
-}
-
-/* Return 1 if reg is a pseudo, or is the first register in 
-   a hard register pair.  This makes it a candidate for use in
-   ldd and std insns.  */
-
-int
-register_ok_for_ldd (reg)
-     rtx reg;
-{
-  /* We might have been passed a SUBREG.  */
-  if (GET_CODE (reg) != REG) 
-    return 0;
-
-  if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
-    return (REGNO (reg) % 2 == 0);
-  else 
-    return 1;
-}
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
-{
-  switch (code)
-    {
-    case '#':
-      /* Output a 'nop' if there's nothing for the delay slot.  */
-      if (dbr_sequence_length () == 0)
-	fputs ("\n\t nop", file);
-      return;
-    case '*':
-      /* Output an annul flag if there's nothing for the delay slot and we
-	 are optimizing.  This is always used with '(' below.  */
-      /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
-	 this is a dbx bug.  So, we only do this when optimizing.  */
-      /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
-	 Always emit a nop in case the next instruction is a branch.  */
-      if (dbr_sequence_length () == 0
-	  && (optimize && (int)sparc_cpu < PROCESSOR_V9))
-	fputs (",a", file);
-      return;
-    case '(':
-      /* Output a 'nop' if there's nothing for the delay slot and we are
-	 not optimizing.  This is always used with '*' above.  */
-      if (dbr_sequence_length () == 0
-	  && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
-	fputs ("\n\t nop", file);
-      return;
-    case '_':
-      /* Output the Embedded Medium/Anywhere code model base register.  */
-      fputs (EMBMEDANY_BASE_REG, file);
-      return;
-    case '@':
-      /* Print out what we are using as the frame pointer.  This might
-	 be %fp, or might be %sp+offset.  */
-      /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
-      fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
-      return;
-    case 'Y':
-      /* Adjust the operand to take into account a RESTORE operation.  */
-      if (GET_CODE (x) == CONST_INT)
-	break;
-      else if (GET_CODE (x) != REG)
-	output_operand_lossage ("Invalid %%Y operand");
-      else if (REGNO (x) < 8)
-	fputs (reg_names[REGNO (x)], file);
-      else if (REGNO (x) >= 24 && REGNO (x) < 32)
-	fputs (reg_names[REGNO (x)-16], file);
-      else
-	output_operand_lossage ("Invalid %%Y operand");
-      return;
-    case 'L':
-      /* Print out the low order register name of a register pair.  */
-      if (WORDS_BIG_ENDIAN)
-	fputs (reg_names[REGNO (x)+1], file);
-      else
-	fputs (reg_names[REGNO (x)], file);
-      return;
-    case 'H':
-      /* Print out the high order register name of a register pair.  */
-      if (WORDS_BIG_ENDIAN)
-	fputs (reg_names[REGNO (x)], file);
-      else
-	fputs (reg_names[REGNO (x)+1], file);
-      return;
-    case 'R':
-      /* Print out the second register name of a register pair or quad.
-	 I.e., R (%o0) => %o1.  */
-      fputs (reg_names[REGNO (x)+1], file);
-      return;
-    case 'S':
-      /* Print out the third register name of a register quad.
-	 I.e., S (%o0) => %o2.  */
-      fputs (reg_names[REGNO (x)+2], file);
-      return;
-    case 'T':
-      /* Print out the fourth register name of a register quad.
-	 I.e., T (%o0) => %o3.  */
-      fputs (reg_names[REGNO (x)+3], file);
-      return;
-    case 'x':
-      /* Print a condition code register.  */
-      if (REGNO (x) == SPARC_ICC_REG)
-	{
-	  /* We don't handle CC[X]_NOOVmode because they're not supposed
-	     to occur here.  */
-	  if (GET_MODE (x) == CCmode)
-	    fputs ("%icc", file);
-	  else if (GET_MODE (x) == CCXmode)
-	    fputs ("%xcc", file);
-	  else
-	    abort ();
-	}
-      else
-	/* %fccN register */
-	fputs (reg_names[REGNO (x)], file);
-      return;
-    case 'm':
-      /* Print the operand's address only.  */
-      output_address (XEXP (x, 0));
-      return;
-    case 'r':
-      /* In this case we need a register.  Use %g0 if the
-	 operand is const0_rtx.  */
-      if (x == const0_rtx
-	  || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
-	{
-	  fputs ("%g0", file);
-	  return;
-	}
-      else
-	break;
-
-    case 'A':
-      switch (GET_CODE (x))
-	{
-	case IOR: fputs ("or", file); break;
-	case AND: fputs ("and", file); break;
-	case XOR: fputs ("xor", file); break;
-	default: output_operand_lossage ("Invalid %%A operand");
-	}
-      return;
-
-    case 'B':
-      switch (GET_CODE (x))
-	{
-	case IOR: fputs ("orn", file); break;
-	case AND: fputs ("andn", file); break;
-	case XOR: fputs ("xnor", file); break;
-	default: output_operand_lossage ("Invalid %%B operand");
-	}
-      return;
-
-      /* These are used by the conditional move instructions.  */
-    case 'c' :
-    case 'C':
-      {
-	enum rtx_code rc = (code == 'c'
-			    ? reverse_condition (GET_CODE (x))
-			    : GET_CODE (x));
-	switch (rc)
-	  {
-	  case NE: fputs ("ne", file); break;
-	  case EQ: fputs ("e", file); break;
-	  case GE: fputs ("ge", file); break;
-	  case GT: fputs ("g", file); break;
-	  case LE: fputs ("le", file); break;
-	  case LT: fputs ("l", file); break;
-	  case GEU: fputs ("geu", file); break;
-	  case GTU: fputs ("gu", file); break;
-	  case LEU: fputs ("leu", file); break;
-	  case LTU: fputs ("lu", file); break;
-	  default: output_operand_lossage (code == 'c'
-					   ? "Invalid %%c operand"
-					   : "Invalid %%C operand");
-	  }
-	return;
-      }
-
-      /* These are used by the movr instruction pattern.  */
-    case 'd':
-    case 'D':
-      {
-	enum rtx_code rc = (code == 'd'
-			    ? reverse_condition (GET_CODE (x))
-			    : GET_CODE (x));
-	switch (rc)
-	  {
-	  case NE: fputs ("ne", file); break;
-	  case EQ: fputs ("e", file); break;
-	  case GE: fputs ("gez", file); break;
-	  case LT: fputs ("lz", file); break;
-	  case LE: fputs ("lez", file); break;
-	  case GT: fputs ("gz", file); break;
-	  default: output_operand_lossage (code == 'd'
-					   ? "Invalid %%d operand"
-					   : "Invalid %%D operand");
-	  }
-	return;
-      }
-
-    case 'b':
-      {
-	/* Print a sign-extended character.  */
-	int i = INTVAL (x) & 0xff;
-	if (i & 0x80)
-	  i |= 0xffffff00;
-	fprintf (file, "%d", i);
-	return;
-      }
-
-    case 'f':
-      /* Operand must be a MEM; write its address.  */
-      if (GET_CODE (x) != MEM)
-	output_operand_lossage ("Invalid %%f operand");
-      output_address (XEXP (x, 0));
-      return;
-
-    case 0:
-      /* Do nothing special.  */
-      break;
-
-    default:
-      /* Undocumented flag.  */
-      output_operand_lossage ("invalid operand output code");
-    }
-
-  if (GET_CODE (x) == REG)
-    fputs (reg_names[REGNO (x)], file);
-  else if (GET_CODE (x) == MEM)
-    {
-      fputc ('[', file);
-	/* Poor Sun assembler doesn't understand absolute addressing.  */
-      if (CONSTANT_P (XEXP (x, 0))
-	  && ! TARGET_LIVE_G0)
-	fputs ("%g0+", file);
-      output_address (XEXP (x, 0));
-      fputc (']', file);
-    }
-  else if (GET_CODE (x) == HIGH)
-    {
-      fputs ("%hi(", file);
-      output_addr_const (file, XEXP (x, 0));
-      fputc (')', file);
-    }
-  else if (GET_CODE (x) == LO_SUM)
-    {
-      print_operand (file, XEXP (x, 0), 0);
-      if (TARGET_CM_MEDMID)
-	fputs ("+%l44(", file);
-      else
-	fputs ("+%lo(", file);
-      output_addr_const (file, XEXP (x, 1));
-      fputc (')', file);
-    }
-  else if (GET_CODE (x) == CONST_DOUBLE
-	   && (GET_MODE (x) == VOIDmode
-	       || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
-    {
-      if (CONST_DOUBLE_HIGH (x) == 0)
-	fprintf (file, "%u", CONST_DOUBLE_LOW (x));
-      else if (CONST_DOUBLE_HIGH (x) == -1
-	       && CONST_DOUBLE_LOW (x) < 0)
-	fprintf (file, "%d", CONST_DOUBLE_LOW (x));
-      else
-	output_operand_lossage ("long long constant not a valid immediate operand");
-    }
-  else if (GET_CODE (x) == CONST_DOUBLE)
-    output_operand_lossage ("floating point constant not a valid immediate operand");
-  else { output_addr_const (file, x); }
-}
-
-/* This function outputs assembler code for VALUE to FILE, where VALUE is
-   a 64 bit (DImode) value.  */
-
-/* ??? If there is a 64 bit counterpart to .word that the assembler
-   understands, then using that would simply this code greatly.  */
-/* ??? We only output .xword's for symbols and only then in environments
-   where the assembler can handle them.  */
-
-void
-output_double_int (file, value)
-     FILE *file;
-     rtx value;
-{
-  if (GET_CODE (value) == CONST_INT)
-    {
-      /* ??? This has endianness issues.  */
-#if HOST_BITS_PER_WIDE_INT == 64
-      HOST_WIDE_INT xword = INTVAL (value);
-      HOST_WIDE_INT high, low;
-
-      high = (xword >> 32) & 0xffffffff;
-      low  = xword & 0xffffffff;
-      ASM_OUTPUT_INT (file, GEN_INT (high));
-      ASM_OUTPUT_INT (file, GEN_INT (low));
-#else
-      if (INTVAL (value) < 0)
-	ASM_OUTPUT_INT (file, constm1_rtx);
-      else
-	ASM_OUTPUT_INT (file, const0_rtx);
-      ASM_OUTPUT_INT (file, value);
-#endif
-    }
-  else if (GET_CODE (value) == CONST_DOUBLE)
-    {
-      ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value)));
-      ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value)));
-    }
-  else if (GET_CODE (value) == SYMBOL_REF
-	   || GET_CODE (value) == CONST
-	   || GET_CODE (value) == PLUS
-	   || (TARGET_ARCH64 &&
-	       (GET_CODE (value) == LABEL_REF
-		|| GET_CODE (value) == CODE_LABEL
-		|| GET_CODE (value) == MINUS)))
-    {
-      if (! TARGET_V9)
-	{
-	  ASM_OUTPUT_INT (file, const0_rtx);
-	  ASM_OUTPUT_INT (file, value);
-	}
-      else
-	{
-	  fprintf (file, "\t%s\t", ASM_LONGLONG);
-	  output_addr_const (file, value);
-	  fprintf (file, "\n");
-	}
-    }
-  else
-    abort ();
-}
-
-/* Return the value of a code used in the .proc pseudo-op that says
-   what kind of result this function returns.  For non-C types, we pick
-   the closest C type.  */
-
-#ifndef CHAR_TYPE_SIZE
-#define CHAR_TYPE_SIZE BITS_PER_UNIT
-#endif
-
-#ifndef SHORT_TYPE_SIZE
-#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
-#endif
-
-#ifndef INT_TYPE_SIZE
-#define INT_TYPE_SIZE BITS_PER_WORD
-#endif
-
-#ifndef LONG_TYPE_SIZE
-#define LONG_TYPE_SIZE BITS_PER_WORD
-#endif
-
-#ifndef LONG_LONG_TYPE_SIZE
-#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
-#endif
-
-#ifndef FLOAT_TYPE_SIZE
-#define FLOAT_TYPE_SIZE BITS_PER_WORD
-#endif
-
-#ifndef DOUBLE_TYPE_SIZE
-#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
-#endif
-
-#ifndef LONG_DOUBLE_TYPE_SIZE
-#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
-#endif
-
-unsigned long
-sparc_type_code (type)
-     register tree type;
-{
-  register unsigned long qualifiers = 0;
-  register unsigned shift;
-
-  /* Only the first 30 bits of the qualifier are valid.  We must refrain from
-     setting more, since some assemblers will give an error for this.  Also,
-     we must be careful to avoid shifts of 32 bits or more to avoid getting
-     unpredictable results.  */
-
-  for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
-    {
-      switch (TREE_CODE (type))
-	{
-	case ERROR_MARK:
-	  return qualifiers;
-  
-	case ARRAY_TYPE:
-	  qualifiers |= (3 << shift);
-	  break;
-
-	case FUNCTION_TYPE:
-	case METHOD_TYPE:
-	  qualifiers |= (2 << shift);
-	  break;
-
-	case POINTER_TYPE:
-	case REFERENCE_TYPE:
-	case OFFSET_TYPE:
-	  qualifiers |= (1 << shift);
-	  break;
-
-	case RECORD_TYPE:
-	  return (qualifiers | 8);
-
-	case UNION_TYPE:
-	case QUAL_UNION_TYPE:
-	  return (qualifiers | 9);
-
-	case ENUMERAL_TYPE:
-	  return (qualifiers | 10);
-
-	case VOID_TYPE:
-	  return (qualifiers | 16);
-
-	case INTEGER_TYPE:
-	  /* If this is a range type, consider it to be the underlying
-	     type.  */
-	  if (TREE_TYPE (type) != 0)
-	    break;
-
-	  /* Carefully distinguish all the standard types of C,
-	     without messing up if the language is not C.  We do this by
-	     testing TYPE_PRECISION and TREE_UNSIGNED.  The old code used to
-	     look at both the names and the above fields, but that's redundant.
-	     Any type whose size is between two C types will be considered
-	     to be the wider of the two types.  Also, we do not have a
-	     special code to use for "long long", so anything wider than
-	     long is treated the same.  Note that we can't distinguish
-	     between "int" and "long" in this code if they are the same
-	     size, but that's fine, since neither can the assembler.  */
-
-	  if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
-	    return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
-  
-	  else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
-	    return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
-  
-	  else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
-	    return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
-  
-	  else
-	    return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
-  
-	case REAL_TYPE:
-	  /* If this is a range type, consider it to be the underlying
-	     type.  */
-	  if (TREE_TYPE (type) != 0)
-	    break;
-
-	  /* Carefully distinguish all the standard types of C,
-	     without messing up if the language is not C.  */
-
-	  if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
-	    return (qualifiers | 6);
-
-	  else 
-	    return (qualifiers | 7);
-  
-	case COMPLEX_TYPE:	/* GNU Fortran COMPLEX type.  */
-	  /* ??? We need to distinguish between double and float complex types,
-	     but I don't know how yet because I can't reach this code from
-	     existing front-ends.  */
-	  return (qualifiers | 7);	/* Who knows? */
-
-	case CHAR_TYPE:		/* GNU Pascal CHAR type.  Not used in C.  */
-	case BOOLEAN_TYPE:	/* GNU Fortran BOOLEAN type.  */
-	case FILE_TYPE:		/* GNU Pascal FILE type.  */
-	case SET_TYPE:		/* GNU Pascal SET type.  */
-	case LANG_TYPE:		/* ? */
-	  return qualifiers;
-  
-	default:
-	  abort ();		/* Not a type! */
-        }
-    }
-
-  return qualifiers;
-}
-
-/* Nested function support.  */
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.
-
-   This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
-   (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
-   (to store insns).  This is a bit excessive.  Perhaps a different
-   mechanism would be better here.
-
-   Emit enough FLUSH insns to synchronize the data and instruction caches.  */
-
-void
-sparc_initialize_trampoline (tramp, fnaddr, cxt)
-     rtx tramp, fnaddr, cxt;
-{
-  /* SPARC 32 bit trampoline:
-
- 	sethi	%hi(fn), %g1
- 	sethi	%hi(static), %g2
- 	jmp	%g1+%lo(fn)
- 	or	%g2, %lo(static), %g2
-
-    SETHI i,r  = 00rr rrr1 00ii iiii iiii iiii iiii iiii
-    JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
-   */
-#ifdef TRANSFER_FROM_TRAMPOLINE
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
-                     0, VOIDmode, 1, tramp, Pmode);
-#endif
-
-  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
-		  expand_binop (SImode, ior_optab,
-				expand_shift (RSHIFT_EXPR, SImode, fnaddr,
-					      size_int (10), 0, 1),
-				GEN_INT (0x03000000),
-				NULL_RTX, 1, OPTAB_DIRECT));
-
-  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
-		  expand_binop (SImode, ior_optab,
-				expand_shift (RSHIFT_EXPR, SImode, cxt,
-					      size_int (10), 0, 1),
-				GEN_INT (0x05000000),
-				NULL_RTX, 1, OPTAB_DIRECT));
-
-  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
-		  expand_binop (SImode, ior_optab,
-				expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX),
-				GEN_INT (0x81c06000),
-				NULL_RTX, 1, OPTAB_DIRECT));
-
-  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
-		  expand_binop (SImode, ior_optab,
-				expand_and (cxt, GEN_INT (0x3ff), NULL_RTX),
-				GEN_INT (0x8410a000),
-				NULL_RTX, 1, OPTAB_DIRECT));
-
-  emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
-  /* On UltraSPARC a flush flushes an entire cache line.  The trampoline is
-     aligned on a 16 byte boundary so one flush clears it all.  */
-  if (sparc_cpu != PROCESSOR_ULTRASPARC)
-    emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
-						     plus_constant (tramp, 8)))));
-}
-
-/* The 64 bit version is simpler because it makes more sense to load the
-   values as "immediate" data out of the trampoline.  It's also easier since
-   we can read the PC without clobbering a register.  */
-
-void
-sparc64_initialize_trampoline (tramp, fnaddr, cxt)
-     rtx tramp, fnaddr, cxt;
-{
-#ifdef TRANSFER_FROM_TRAMPOLINE
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
-                     0, VOIDmode, 1, tramp, Pmode);
-#endif
-
-  /*
-	rd	%pc, %g1
-	ldx	[%g1+24], %g5
-	jmp	%g5
-	ldx	[%g1+16], %g5
-	+16 bytes data
-   */
-
-  emit_move_insn (gen_rtx_MEM (SImode, tramp),
-		  GEN_INT (0x83414000));
-  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
-		  GEN_INT (0xca586018));
-  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
-		  GEN_INT (0x81c14000));
-  emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
-		  GEN_INT (0xca586010));
-  emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
-  emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
-  emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, tramp))));
-
-  if (sparc_cpu != PROCESSOR_ULTRASPARC)
-    emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
-}
-
-/* Subroutines to support a flat (single) register window calling
-   convention.  */
-
-/* Single-register window sparc stack frames look like:
-
-             Before call		        After call
-        +-----------------------+	+-----------------------+
-   high |		        |	|			|
-   mem  |  caller's temps.    	|       |  caller's temps.    	|
-	|       		|       |       	        |
-        +-----------------------+	+-----------------------+
- 	|       		|	|		        |
-        |  arguments on stack.  |	|  arguments on stack.  |
-	|       		|      	|			|
-        +-----------------------+FP+92->+-----------------------+
- 	|  6 words to save     	|	|  6 words to save	|
-	|  arguments passed	|	|  arguments passed	|
-	|  in registers, even	|	|  in registers, even	|
-       	|  if not passed.       |      	|  if not passed.	|
- SP+68->+-----------------------+FP+68->+-----------------------+
-        | 1 word struct addr	|      	| 1 word struct addr	|
-        +-----------------------+FP+64->+-----------------------+
-        |			|	|			|
-        | 16 word reg save area	|	| 16 word reg save area |
-       	|                       |      	|			|
-    SP->+-----------------------+   FP->+-----------------------+
-				        | 4 word area for	|
-				       	| fp/alu reg moves	|
-				 FP-16->+-----------------------+
-				        |			|
-				        |  local variables	|
-				        |			|
-				        +-----------------------+
-				        |		        |
-                                        |  fp register save     |
-				        |			|
-				        +-----------------------+
-				        |		        |
-                                        |  gp register save     |
-                                        |       		|
-				        +-----------------------+
-				        |			|
-                                        |  alloca allocations   |
-        			        |			|
-				        +-----------------------+
-				        |			|
-                                        |  arguments on stack   |
-        			       	|		        |
-				 SP+92->+-----------------------+
-                                        |  6 words to save      |
-				        |  arguments passed     |
-                                        |  in registers, even   |
-   low                                 	|  if not passed.       |
-   memory        		 SP+68->+-----------------------+
-				       	| 1 word struct addr	|
-				 SP+64->+-----------------------+
-				        |			|
-				        I 16 word reg save area |
-				       	|			|
-				    SP->+-----------------------+  */
-
-/* Structure to be filled in by sparc_flat_compute_frame_size with register
-   save masks, and offsets for the current function.  */
-
-struct sparc_frame_info
-{
-  unsigned long total_size;	/* # bytes that the entire frame takes up.  */
-  unsigned long var_size;	/* # bytes that variables take up.  */
-  unsigned long args_size;	/* # bytes that outgoing arguments take up.  */
-  unsigned long extra_size;	/* # bytes of extra gunk.  */
-  unsigned int  gp_reg_size;	/* # bytes needed to store gp regs.  */
-  unsigned int  fp_reg_size;	/* # bytes needed to store fp regs.  */
-  unsigned long gmask;		/* Mask of saved gp registers.  */
-  unsigned long fmask;		/* Mask of saved fp registers.  */
-  unsigned long reg_offset;	/* Offset from new sp to store regs.  */
-  int		initialized;	/* Nonzero if frame size already calculated.  */
-};
-
-/* Current frame information calculated by sparc_flat_compute_frame_size.  */
-struct sparc_frame_info current_frame_info;
-
-/* Zero structure to initialize current_frame_info.  */
-struct sparc_frame_info zero_frame_info;
-
-/* Tell prologue and epilogue if register REGNO should be saved / restored.  */
-
-#define RETURN_ADDR_REGNUM 15
-#define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
-#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
-
-#define MUST_SAVE_REGISTER(regno) \
- ((regs_ever_live[regno] && !call_used_regs[regno])		\
-  || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)	\
-  || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
-
-/* Return the bytes needed to compute the frame pointer from the current
-   stack pointer.  */
-
-unsigned long
-sparc_flat_compute_frame_size (size)
-     int size;			/* # of var. bytes allocated.  */
-{
-  int regno;
-  unsigned long total_size;	/* # bytes that the entire frame takes up.  */
-  unsigned long var_size;	/* # bytes that variables take up.  */
-  unsigned long args_size;	/* # bytes that outgoing arguments take up.  */
-  unsigned long extra_size;	/* # extra bytes.  */
-  unsigned int  gp_reg_size;	/* # bytes needed to store gp regs.  */
-  unsigned int  fp_reg_size;	/* # bytes needed to store fp regs.  */
-  unsigned long gmask;		/* Mask of saved gp registers.  */
-  unsigned long fmask;		/* Mask of saved fp registers.  */
-  unsigned long reg_offset;	/* Offset to register save area.  */
-  int           need_aligned_p;	/* 1 if need the save area 8 byte aligned.  */
-
-  /* This is the size of the 16 word reg save area, 1 word struct addr
-     area, and 4 word fp/alu register copy area.  */
-  extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
-  var_size = size;
-  gp_reg_size = 0;
-  fp_reg_size = 0;
-  gmask = 0;
-  fmask = 0;
-  reg_offset = 0;
-  need_aligned_p = 0;
-
-  args_size = 0;
-  if (!leaf_function_p ())
-    {
-      /* Also include the size needed for the 6 parameter registers.  */
-      args_size = current_function_outgoing_args_size + 24;
-    }
-  total_size = var_size + args_size;
-
-  /* Calculate space needed for gp registers.  */
-  for (regno = 1; regno <= 31; regno++)
-    {
-      if (MUST_SAVE_REGISTER (regno))
-	{
-	  /* If we need to save two regs in a row, ensure there's room to bump
-	     up the address to align it to a doubleword boundary.  */
-	  if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
-	    {
-	      if (gp_reg_size % 8 != 0)
-		gp_reg_size += 4;
-	      gp_reg_size += 2 * UNITS_PER_WORD;
-	      gmask |= 3 << regno;
-	      regno++;
-	      need_aligned_p = 1;
-	    }
-	  else
-	    {
-	      gp_reg_size += UNITS_PER_WORD;
-	      gmask |= 1 << regno;
-	    }
-	}
-    }
-
-  /* Calculate space needed for fp registers.  */
-  for (regno = 32; regno <= 63; regno++)
-    {
-      if (regs_ever_live[regno] && !call_used_regs[regno])
-	{
-	  fp_reg_size += UNITS_PER_WORD;
-	  fmask |= 1 << (regno - 32);
-	}
-    }
-
-  if (gmask || fmask)
-    {
-      int n;
-      reg_offset = FIRST_PARM_OFFSET(0) + args_size;
-      /* Ensure save area is 8 byte aligned if we need it.  */
-      n = reg_offset % 8;
-      if (need_aligned_p && n != 0)
-	{
-	  total_size += 8 - n;
-	  reg_offset += 8 - n;
-	}
-      total_size += gp_reg_size + fp_reg_size;
-    }
-
-  /* If we must allocate a stack frame at all, we must also allocate 
-     room for register window spillage, so as to be binary compatible
-     with libraries and operating systems that do not use -mflat.  */
-  if (total_size > 0)
-    total_size += extra_size;
-  else
-    extra_size = 0;
-
-  total_size = SPARC_STACK_ALIGN (total_size);
-
-  /* Save other computed information.  */
-  current_frame_info.total_size  = total_size;
-  current_frame_info.var_size    = var_size;
-  current_frame_info.args_size   = args_size;
-  current_frame_info.extra_size  = extra_size;
-  current_frame_info.gp_reg_size = gp_reg_size;
-  current_frame_info.fp_reg_size = fp_reg_size;
-  current_frame_info.gmask	 = gmask;
-  current_frame_info.fmask	 = fmask;
-  current_frame_info.reg_offset	 = reg_offset;
-  current_frame_info.initialized = reload_completed;
-
-  /* Ok, we're done.  */
-  return total_size;
-}
-
-/* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
-   OFFSET.
-
-   BASE_REG must be 8 byte aligned.  This allows us to test OFFSET for
-   appropriate alignment and use DOUBLEWORD_OP when we can.  We assume
-   [BASE_REG+OFFSET] will always be a valid address.
-
-   WORD_OP is either "st" for save, "ld" for restore.
-   DOUBLEWORD_OP is either "std" for save, "ldd" for restore.  */
-
-void
-sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
-			 doubleword_op, base_offset)
-     FILE *file;
-     char *base_reg;
-     unsigned int offset;
-     unsigned long gmask;
-     unsigned long fmask;
-     char *word_op;
-     char *doubleword_op;
-     unsigned long base_offset;
-{
-  int regno;
-
-  if (gmask == 0 && fmask == 0)
-    return;
-
-  /* Save registers starting from high to low.  We've already saved the
-     previous frame pointer and previous return address for the debugger's
-     sake.  The debugger allows us to not need a nop in the epilog if at least
-     one register is reloaded in addition to return address.  */
-
-  if (gmask)
-    {
-      for (regno = 1; regno <= 31; regno++)
-	{
-	  if ((gmask & (1L << regno)) != 0)
-	    {
-	      if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
-		{
-		  /* We can save two registers in a row.  If we're not at a
-		     double word boundary, move to one.
-		     sparc_flat_compute_frame_size ensures there's room to do
-		     this.  */
-		  if (offset % 8 != 0)
-		    offset += UNITS_PER_WORD;
-
-		  if (word_op[0] == 's')
-		    {
-		      fprintf (file, "\t%s\t%s, [%s+%d]\n",
-			       doubleword_op, reg_names[regno],
-			       base_reg, offset);
-		      if (dwarf2out_do_frame ())
-			{
-			  char *l = dwarf2out_cfi_label ();
-			  dwarf2out_reg_save (l, regno, offset + base_offset);
-			  dwarf2out_reg_save
-			    (l, regno+1, offset+base_offset + UNITS_PER_WORD);
-			}
-		    }
-		  else
-		    fprintf (file, "\t%s\t[%s+%d], %s\n",
-			     doubleword_op, base_reg, offset,
-			     reg_names[regno]);
-
-		  offset += 2 * UNITS_PER_WORD;
-		  regno++;
-		}
-	      else
-		{
-		  if (word_op[0] == 's')
-		    {
-		      fprintf (file, "\t%s\t%s, [%s+%d]\n",
-			       word_op, reg_names[regno],
-			       base_reg, offset);
-		      if (dwarf2out_do_frame ())
-			dwarf2out_reg_save ("", regno, offset + base_offset);
-		    }
-		  else
-		    fprintf (file, "\t%s\t[%s+%d], %s\n",
-			     word_op, base_reg, offset, reg_names[regno]);
-
-		  offset += UNITS_PER_WORD;
-		}
-	    }
-	}
-    }
-
-  if (fmask)
-    {
-      for (regno = 32; regno <= 63; regno++)
-	{
-	  if ((fmask & (1L << (regno - 32))) != 0)
-	    {
-	      if (word_op[0] == 's')
-		{
-		  fprintf (file, "\t%s\t%s, [%s+%d]\n",
-			   word_op, reg_names[regno],
-			   base_reg, offset);
-		  if (dwarf2out_do_frame ())
-		    dwarf2out_reg_save ("", regno, offset + base_offset);
-		}
-	      else
-		fprintf (file, "\t%s\t[%s+%d], %s\n",
-			 word_op, base_reg, offset, reg_names[regno]);
-
-	      offset += UNITS_PER_WORD;
-	    }
-	}
-    }
-}
-
-/* Set up the stack and frame (if desired) for the function.  */
-
-void
-sparc_flat_output_function_prologue (file, size)
-     FILE *file;
-     int size;
-{
-  char *sp_str = reg_names[STACK_POINTER_REGNUM];
-  unsigned long gmask = current_frame_info.gmask;
-
-  /* This is only for the human reader.  */
-  fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
-  fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
-	   ASM_COMMENT_START,
-	   current_frame_info.var_size,
-	   current_frame_info.gp_reg_size / 4,
-	   current_frame_info.fp_reg_size / 4,
-	   current_function_outgoing_args_size,
-	   current_frame_info.extra_size);
-
-  size = SPARC_STACK_ALIGN (size);
-  size = (! current_frame_info.initialized
-	  ? sparc_flat_compute_frame_size (size)
-	  : current_frame_info.total_size);
-
-  /* These cases shouldn't happen.  Catch them now.  */
-  if (size == 0 && (gmask || current_frame_info.fmask))
-    abort ();
-
-  /* Allocate our stack frame by decrementing %sp.
-     At present, the only algorithm gdb can use to determine if this is a
-     flat frame is if we always set %i7 if we set %sp.  This can be optimized
-     in the future by putting in some sort of debugging information that says
-     this is a `flat' function.  However, there is still the case of debugging
-     code without such debugging information (including cases where most fns
-     have such info, but there is one that doesn't).  So, always do this now
-     so we don't get a lot of code out there that gdb can't handle.
-     If the frame pointer isn't needn't then that's ok - gdb won't be able to
-     distinguish us from a non-flat function but there won't (and shouldn't)
-     be any differences anyway.  The return pc is saved (if necessary) right
-     after %i7 so gdb won't have to look too far to find it.  */
-  if (size > 0)
-    {
-      unsigned int reg_offset = current_frame_info.reg_offset;
-      char *fp_str = reg_names[FRAME_POINTER_REGNUM];
-      char *t1_str = "%g1";
-
-      /* Things get a little tricky if local variables take up more than ~4096
-	 bytes and outgoing arguments take up more than ~4096 bytes.  When that
-	 happens, the register save area can't be accessed from either end of
-	 the frame.  Handle this by decrementing %sp to the start of the gp
-	 register save area, save the regs, update %i7, and then set %sp to its
-	 final value.  Given that we only have one scratch register to play
-	 with it is the cheapest solution, and it helps gdb out as it won't
-	 slow down recognition of flat functions.
-	 Don't change the order of insns emitted here without checking with
-	 the gdb folk first.  */
-
-      /* Is the entire register save area offsettable from %sp?  */
-      if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
-	{
-	  if (size <= 4096)
-	    {
-	      fprintf (file, "\tadd\t%s, %d, %s\n",
-		       sp_str, -size, sp_str);
-	      if (gmask & FRAME_POINTER_MASK)
-		{
-		  fprintf (file, "\tst\t%s, [%s+%d]\n",
-			   fp_str, sp_str, reg_offset);
-		  fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
-			   sp_str, -size, fp_str, ASM_COMMENT_START);
-		  reg_offset += 4;
-		}
-	    }
-	  else
-	    {
-	      fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
-		       size, t1_str, sp_str, t1_str, sp_str);
-	      if (gmask & FRAME_POINTER_MASK)
-		{
-		  fprintf (file, "\tst\t%s, [%s+%d]\n",
-			   fp_str, sp_str, reg_offset);
-		  fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
-			   sp_str, t1_str, fp_str, ASM_COMMENT_START);
-		  reg_offset += 4;
-		}
-	    }
-	  if (dwarf2out_do_frame ())
-	    {
-	      char *l = dwarf2out_cfi_label ();
-	      if (gmask & FRAME_POINTER_MASK)
-		{
-		  dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
-				      reg_offset - 4 - size);
-		  dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
-		}
-	      else
-		dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
-	    }
-	  if (gmask & RETURN_ADDR_MASK)
-	    {
-	      fprintf (file, "\tst\t%s, [%s+%d]\n",
-		       reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
-	      if (dwarf2out_do_frame ())
-		dwarf2out_return_save ("", reg_offset - size);
-	      reg_offset += 4;
-	    }
-	  sparc_flat_save_restore (file, sp_str, reg_offset,
-				   gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
-				   current_frame_info.fmask,
-				   "st", "std", -size);
-	}
-      else
-	{
-	  /* Subtract %sp in two steps, but make sure there is always a
-	     64 byte register save area, and %sp is properly aligned.  */
-	  /* Amount to decrement %sp by, the first time.  */
-	  unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
-	  /* Offset to register save area from %sp.  */
-	  unsigned int offset = size1 - (size - reg_offset);
-	  
-	  if (size1 <= 4096)
-	    {
-	      fprintf (file, "\tadd\t%s, %d, %s\n",
-		       sp_str, -size1, sp_str);
-	      if (gmask & FRAME_POINTER_MASK)
-		{
-		  fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
-			   fp_str, sp_str, offset, sp_str, -size1, fp_str,
-			   ASM_COMMENT_START);
-		  offset += 4;
-		}
-	    }
-	  else
-	    {
-	      fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
-		       size1, t1_str, sp_str, t1_str, sp_str);
-	      if (gmask & FRAME_POINTER_MASK)
-		{
-		  fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
-			   fp_str, sp_str, offset, sp_str, t1_str, fp_str,
-			   ASM_COMMENT_START);
-		  offset += 4;
-		}
-	    }
-	  if (dwarf2out_do_frame ())
-	    {
-	      char *l = dwarf2out_cfi_label ();
-	      if (gmask & FRAME_POINTER_MASK)
-		{
-		  dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
-				      offset - 4 - size1);
-		  dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
-		}
-	      else
-		dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
-	    }
-	  if (gmask & RETURN_ADDR_MASK)
-	    {
-	      fprintf (file, "\tst\t%s, [%s+%d]\n",
-		       reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
-	      if (dwarf2out_do_frame ())
-		/* offset - size1 == reg_offset - size
-		   if reg_offset were updated above like offset.  */
-		dwarf2out_return_save ("", offset - size1);
-	      offset += 4;
-	    }
-	  sparc_flat_save_restore (file, sp_str, offset,
-				   gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
-				   current_frame_info.fmask,
-				   "st", "std", -size1);
-	  fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
-		   size - size1, t1_str, sp_str, t1_str, sp_str);
-	  if (dwarf2out_do_frame ())
-	    if (! (gmask & FRAME_POINTER_MASK))
-	      dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
-	}
-    }
-
-  fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
-}
-
-/* Do any necessary cleanup after a function to restore stack, frame,
-   and regs. */
-
-void
-sparc_flat_output_function_epilogue (file, size)
-     FILE *file;
-     int size;
-{
-  rtx epilogue_delay = current_function_epilogue_delay_list;
-  int noepilogue = FALSE;
-
-  /* This is only for the human reader.  */
-  fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
-
-  /* The epilogue does not depend on any registers, but the stack
-     registers, so we assume that if we have 1 pending nop, it can be
-     ignored, and 2 it must be filled (2 nops occur for integer
-     multiply and divide).  */
-
-  size = SPARC_STACK_ALIGN (size);
-  size = (!current_frame_info.initialized
-	   ? sparc_flat_compute_frame_size (size)
-	   : current_frame_info.total_size);
-
-  if (size == 0 && epilogue_delay == 0)
-    {
-      rtx insn = get_last_insn ();
-
-      /* If the last insn was a BARRIER, we don't have to write any code
-	 because a jump (aka return) was put there.  */
-      if (GET_CODE (insn) == NOTE)
-	insn = prev_nonnote_insn (insn);
-      if (insn && GET_CODE (insn) == BARRIER)
-	noepilogue = TRUE;
-    }
-
-  if (!noepilogue)
-    {
-      unsigned int reg_offset = current_frame_info.reg_offset;
-      unsigned int size1;
-      char *sp_str = reg_names[STACK_POINTER_REGNUM];
-      char *fp_str = reg_names[FRAME_POINTER_REGNUM];
-      char *t1_str = "%g1";
-
-      /* In the reload sequence, we don't need to fill the load delay
-	 slots for most of the loads, also see if we can fill the final
-	 delay slot if not otherwise filled by the reload sequence.  */
-
-      if (size > 4095)
-	fprintf (file, "\tset\t%d, %s\n", size, t1_str);
-
-      if (frame_pointer_needed)
-	{
-	  if (size > 4095)
-	    fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
-		     fp_str, t1_str, sp_str, ASM_COMMENT_START);
-	  else
-	    fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
-		     fp_str, size, sp_str, ASM_COMMENT_START);
-	}
-
-      /* Is the entire register save area offsettable from %sp?  */
-      if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
-	{
-	  size1 = 0;
-	}
-      else
-	{
-	  /* Restore %sp in two steps, but make sure there is always a
-	     64 byte register save area, and %sp is properly aligned.  */
-	  /* Amount to increment %sp by, the first time.  */
-	  size1 = ((reg_offset - 64 - 16) + 15) & -16;
-	  /* Offset to register save area from %sp.  */
-	  reg_offset = size1 - reg_offset;
-
-	  fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
-		   size1, t1_str, sp_str, t1_str, sp_str);
-	}
-
-      /* We must restore the frame pointer and return address reg first
-	 because they are treated specially by the prologue output code.  */
-      if (current_frame_info.gmask & FRAME_POINTER_MASK)
-	{
-	  fprintf (file, "\tld\t[%s+%d], %s\n",
-		   sp_str, reg_offset, fp_str);
-	  reg_offset += 4;
-	}
-      if (current_frame_info.gmask & RETURN_ADDR_MASK)
-	{
-	  fprintf (file, "\tld\t[%s+%d], %s\n",
-		   sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
-	  reg_offset += 4;
-	}
-
-      /* Restore any remaining saved registers.  */
-      sparc_flat_save_restore (file, sp_str, reg_offset,
-			       current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
-			       current_frame_info.fmask,
-			       "ld", "ldd", 0);
-
-      /* If we had to increment %sp in two steps, record it so the second
-	 restoration in the epilogue finishes up.  */
-      if (size1 > 0)
-	{
-	  size -= size1;
-	  if (size > 4095)
-	    fprintf (file, "\tset\t%d, %s\n",
-		     size, t1_str);
-	}
-
-      if (current_function_returns_struct)
-	fprintf (file, "\tjmp\t%%o7+12\n");
-      else
-	fprintf (file, "\tretl\n");
-
-      /* If the only register saved is the return address, we need a
-	 nop, unless we have an instruction to put into it.  Otherwise
-	 we don't since reloading multiple registers doesn't reference
-	 the register being loaded.  */
-
-      if (epilogue_delay)
-	{
-	  if (size)
-	    abort ();
-	  final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
-	}
-
-      else if (size > 4095)
-	fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
-
-      else if (size > 0)
-	fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str);
-
-      else
-	fprintf (file, "\tnop\n");
-    }
-
-  /* Reset state info for each function.  */
-  current_frame_info = zero_frame_info;
-
-  sparc_output_deferred_case_vectors ();
-}
-
-/* Define the number of delay slots needed for the function epilogue.
-
-   On the sparc, we need a slot if either no stack has been allocated,
-   or the only register saved is the return register.  */
-
-int
-sparc_flat_epilogue_delay_slots ()
-{
-  if (!current_frame_info.initialized)
-    (void) sparc_flat_compute_frame_size (get_frame_size ());
-
-  if (current_frame_info.total_size == 0)
-    return 1;
-
-  return 0;
-}
-
-/* Return true is TRIAL is a valid insn for the epilogue delay slot.
-   Any single length instruction which doesn't reference the stack or frame
-   pointer is OK.  */
-
-int
-sparc_flat_eligible_for_epilogue_delay (trial, slot)
-     rtx trial;
-     int slot ATTRIBUTE_UNUSED;
-{
-  rtx pat = PATTERN (trial);
-
-  if (get_attr_length (trial) != 1)
-    return 0;
-
-  /* If %g0 is live, there are lots of things we can't handle.
-     Rather than trying to find them all now, let's punt and only
-     optimize things as necessary.  */
-  if (TARGET_LIVE_G0)
-    return 0;
-
-  if (! reg_mentioned_p (stack_pointer_rtx, pat)
-      && ! reg_mentioned_p (frame_pointer_rtx, pat))
-    return 1;
-
-  return 0;
-}
-
-/* Adjust the cost of a scheduling dependency.  Return the new cost of
-   a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
-
-static int
-supersparc_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
-{
-  enum attr_type insn_type;
-
-  if (! recog_memoized (insn))
-    return 0;
-
-  insn_type = get_attr_type (insn);
-
-  if (REG_NOTE_KIND (link) == 0)
-    {
-      /* Data dependency; DEP_INSN writes a register that INSN reads some
-	 cycles later.  */
-
-      /* if a load, then the dependence must be on the memory address;
-	 add an extra "cycle".  Note that the cost could be two cycles
-	 if the reg was written late in an instruction group; we ca not tell
-	 here.  */
-      if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
-	return cost + 3;
-
-      /* Get the delay only if the address of the store is the dependence.  */
-      if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
-	{
-	  rtx pat = PATTERN(insn);
-	  rtx dep_pat = PATTERN (dep_insn);
-
-	  if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
-	    return cost;  /* This should not happen!  */
-
-	  /* The dependency between the two instructions was on the data that
-	     is being stored.  Assume that this implies that the address of the
-	     store is not dependent.  */
-	  if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
-	    return cost;
-
-	  return cost + 3;  /* An approximation.  */
-	}
-
-      /* A shift instruction cannot receive its data from an instruction
-	 in the same cycle; add a one cycle penalty.  */
-      if (insn_type == TYPE_SHIFT)
-	return cost + 3;   /* Split before cascade into shift.  */
-    }
-  else
-    {
-      /* Anti- or output- dependency; DEP_INSN reads/writes a register that
-	 INSN writes some cycles later.  */
-
-      /* These are only significant for the fpu unit; writing a fp reg before
-         the fpu has finished with it stalls the processor.  */
-
-      /* Reusing an integer register causes no problems.  */
-      if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
-	return 0;
-    }
-	
-  return cost;
-}
-
-static int
-hypersparc_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
-{
-  enum attr_type insn_type, dep_type;
-  rtx pat = PATTERN(insn);
-  rtx dep_pat = PATTERN (dep_insn);
-
-  if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
-    return cost;
-
-  insn_type = get_attr_type (insn);
-  dep_type = get_attr_type (dep_insn);
-
-  switch (REG_NOTE_KIND (link))
-    {
-    case 0:
-      /* Data dependency; DEP_INSN writes a register that INSN reads some
-	 cycles later.  */
-
-      switch (insn_type)
-	{
-	case TYPE_STORE:
-	case TYPE_FPSTORE:
-	  /* Get the delay iff the address of the store is the dependence. */
-	  if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
-	    return cost;
-
-	  if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
-	    return cost;
-	  return cost + 3;
-
-	case TYPE_LOAD:
-	case TYPE_SLOAD:
-	case TYPE_FPLOAD:
-	  /* If a load, then the dependence must be on the memory address.  If
-	     the addresses aren't equal, then it might be a false dependency */
-	  if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
-	    {
-	      if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
-		  || GET_CODE (SET_DEST (dep_pat)) != MEM        
-		  || GET_CODE (SET_SRC (pat)) != MEM
-		  || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
-				    XEXP (SET_SRC (pat), 0)))
-		return cost + 2;
-
-	      return cost + 8;        
-	    }
-	  break;
-
-	case TYPE_BRANCH:
-	  /* Compare to branch latency is 0.  There is no benefit from
-	     separating compare and branch.  */
-	  if (dep_type == TYPE_COMPARE)
-	    return 0;
-	  /* Floating point compare to branch latency is less than
-	     compare to conditional move.  */
-	  if (dep_type == TYPE_FPCMP)
-	    return cost - 1;
-	  break;
-	}
-	break;
-
-    case REG_DEP_ANTI:
-      /* Anti-dependencies only penalize the fpu unit. */
-      if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
-        return 0;
-      break;
-
-    default:
-      break;
-    }    
-
-  return cost;
-}
-
-static int
-ultrasparc_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
-{
-  enum attr_type insn_type, dep_type;
-  rtx pat = PATTERN(insn);
-  rtx dep_pat = PATTERN (dep_insn);
-
-  if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
-    return cost;
-
-  insn_type = get_attr_type (insn);
-  dep_type = get_attr_type (dep_insn);
-
-  /* Nothing issues in parallel with integer multiplies, so
-     mark as zero cost since the scheduler can not do anything
-     about it.  */
-  if (insn_type == TYPE_IMUL)
-    return 0;
-
-#define SLOW_FP(dep_type) \
-(dep_type == TYPE_FPSQRT || dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
-
-  switch (REG_NOTE_KIND (link))
-    {
-    case 0:
-      /* Data dependency; DEP_INSN writes a register that INSN reads some
-	 cycles later.  */
-
-      if (dep_type == TYPE_CMOVE)
-	{
-	  /* Instructions that read the result of conditional moves cannot
-	     be in the same group or the following group.  */
-	  return cost + 1;
-	}
-
-      switch (insn_type)
-	{
-	  /* UltraSPARC can dual issue a store and an instruction setting
-	     the value stored, except for divide and square root.  */
-	case TYPE_FPSTORE:
-	  if (! SLOW_FP (dep_type))
-	    return 0;
-	  return cost;
-
-	case TYPE_STORE:
-	  if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
-	    return cost;
-
-	  if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
-	    /* The dependency between the two instructions is on the data
-	       that is being stored.  Assume that the address of the store
-	       is not also dependent.  */
-	    return 0;
-	  return cost;
-
-	case TYPE_LOAD:
-	case TYPE_SLOAD:
-	case TYPE_FPLOAD:
-	  /* A load does not return data until at least 11 cycles after
-	     a store to the same location.  3 cycles are accounted for
-	     in the load latency; add the other 8 here.  */
-	  if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
-	    {
-	      /* If the addresses are not equal this may be a false
-		 dependency because pointer aliasing could not be
-		 determined.  Add only 2 cycles in that case.  2 is
-		 an arbitrary compromise between 8, which would cause
-		 the scheduler to generate worse code elsewhere to
-		 compensate for a dependency which might not really
-		 exist, and 0.  */
-	      if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
-		  || GET_CODE (SET_SRC (pat)) != MEM
-		  || GET_CODE (SET_DEST (dep_pat)) != MEM
-		  || ! rtx_equal_p (XEXP (SET_SRC (pat), 0),
-				    XEXP (SET_DEST (dep_pat), 0)))
-		return cost + 2;
-
-	      return cost + 8;
-	    }
-	  return cost;
-
-	case TYPE_BRANCH:
-	  /* Compare to branch latency is 0.  There is no benefit from
-	     separating compare and branch.  */
-	  if (dep_type == TYPE_COMPARE)
-	    return 0;
-	  /* Floating point compare to branch latency is less than
-	     compare to conditional move.  */
-	  if (dep_type == TYPE_FPCMP)
-	    return cost - 1;
-	  return cost;
-
-	case TYPE_FPCMOVE:
-	  /* FMOVR class instructions can not issue in the same cycle
-	     or the cycle after an instruction which writes any
-	     integer register.  Model this as cost 2 for dependent
-	     instructions.  */
-	  if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY
-	       || dep_type == TYPE_BINARY)
-	      && cost < 2)
-	    return 2;
-	  /* Otherwise check as for integer conditional moves. */
-
-	case TYPE_CMOVE:
-	  /* Conditional moves involving integer registers wait until
-	     3 cycles after loads return data.  The interlock applies
-	     to all loads, not just dependent loads, but that is hard
-	     to model.  */
-	  if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD)
-	    return cost + 3;
-	  return cost;
-
-	default:
-	  break;
-	}
-      break;
-
-    case REG_DEP_ANTI:
-      /* Divide and square root lock destination registers for full latency. */
-      if (! SLOW_FP (dep_type))
-	return 0;
-      break;
-
-    case REG_DEP_OUTPUT:
-      /* IEU and FPU instruction that have the same destination
-	 register cannot be grouped together.  */
-      return cost + 1;
-
-    default:
-      break;
-    }
-
-  /* Other costs not accounted for:
-     - Single precision floating point loads lock the other half of
-       the even/odd register pair.
-     - Several hazards associated with ldd/std are ignored because these
-       instructions are rarely generated for V9.
-     - The floating point pipeline can not have both a single and double
-       precision operation active at the same time.  Format conversions
-       and graphics instructions are given honorary double precision status.
-     - call and jmpl are always the first instruction in a group.  */
-
-  return cost;
-
-#undef SLOW_FP
-}
-
-int
-sparc_adjust_cost(insn, link, dep, cost)
-     rtx insn;
-     rtx link;
-     rtx dep;
-     int cost;
-{
-  switch (sparc_cpu)
-    {
-    case PROCESSOR_SUPERSPARC:
-      cost = supersparc_adjust_cost (insn, link, dep, cost);
-      break;
-    case PROCESSOR_HYPERSPARC:
-    case PROCESSOR_SPARCLITE86X:
-      cost = hypersparc_adjust_cost (insn, link, dep, cost);
-      break;
-    case PROCESSOR_ULTRASPARC:
-      cost = ultrasparc_adjust_cost (insn, link, dep, cost);
-      break;
-    default:
-      break;
-    }
-  return cost;
-}
-
-/* This describes the state of the UltraSPARC pipeline during
-   instruction scheduling.  */
-
-#define TMASK(__x)	((unsigned)1 << ((int)(__x)))
-#define UMASK(__x)	((unsigned)1 << ((int)(__x)))
-
-enum ultra_code { NONE=0, /* no insn at all				*/
-		  IEU0,   /* shifts and conditional moves		*/
-		  IEU1,   /* condition code setting insns, calls+jumps	*/
-		  IEUN,   /* all other single cycle ieu insns		*/
-		  LSU,    /* loads and stores				*/
-		  CTI,    /* branches					*/
-		  FPM,    /* FPU pipeline 1, multiplies and divides	*/
-		  FPA,    /* FPU pipeline 2, all other operations	*/
-		  SINGLE, /* single issue instructions			*/
-		  NUM_ULTRA_CODES };
-
-static char *ultra_code_names[NUM_ULTRA_CODES] = {
-  "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI",
-  "FPM", "FPA", "SINGLE" };
-
-struct ultrasparc_pipeline_state {
-  /* The insns in this group.  */
-  rtx group[4];
-
-  /* The code for each insn.  */
-  enum ultra_code codes[4];
-
-  /* Which insns in this group have been committed by the
-     scheduler.  This is how we determine how many more
-     can issue this cycle.  */
-  char commit[4];
-
-  /* How many insns in this group.  */
-  char group_size;
-
-  /* Mask of free slots still in this group.  */
-  char free_slot_mask;
-
-  /* The slotter uses the following to determine what other
-     insn types can still make their way into this group.  */
-  char contents [NUM_ULTRA_CODES];
-  char num_ieu_insns;
-};
-
-#define ULTRA_NUM_HIST	8
-static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST];
-static int ultra_cur_hist;
-static int ultra_cycles_elapsed;
-
-#define ultra_pipe	(ultra_pipe_hist[ultra_cur_hist])
-
-/* Given TYPE_MASK compute the ultra_code it has.  */
-static enum ultra_code
-ultra_code_from_mask (type_mask)
-     int type_mask;
-{
-  if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE)))
-    return IEU0;
-  else if (type_mask & (TMASK (TYPE_COMPARE) |
-			TMASK (TYPE_CALL) |
-			TMASK (TYPE_UNCOND_BRANCH)))
-    return IEU1;
-  else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
-			TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)))
-    return IEUN;
-  else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
-			TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
-			TMASK (TYPE_FPSTORE)))
-    return LSU;
-  else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) |
-			TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRT)))
-    return FPM;
-  else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
-			TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)))
-    return FPA;
-  else if (type_mask & TMASK (TYPE_BRANCH))
-    return CTI;
-
-  return SINGLE;
-}
-
-/* Check INSN (a conditional move) and make sure that it's
-   results are available at this cycle.  Return 1 if the
-   results are in fact ready.  */
-static int
-ultra_cmove_results_ready_p (insn)
-     rtx insn;
-{
-  struct ultrasparc_pipeline_state *up;
-  int entry, slot;
-
-  /* If this got dispatched in the previous
-     group, the results are not ready.  */
-  entry = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1);
-  up = &ultra_pipe_hist[entry];
-  slot = 4;
-  while (--slot >= 0)
-    if (up->group[slot] == insn)
-      return 0;
-
-  return 1;
-}
-
-/* Walk backwards in pipeline history looking for FPU
-   operations which use a mode different than FPMODE and
-   will create a stall if an insn using FPMODE were to be
-   dispatched this cycle.  */
-static int
-ultra_fpmode_conflict_exists (fpmode)
-     enum machine_mode fpmode;
-{
-  int hist_ent;
-  int hist_lim;
-
-  hist_ent = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1);
-  if (ultra_cycles_elapsed < 4)
-    hist_lim = ultra_cycles_elapsed;
-  else
-    hist_lim = 4;
-  while (hist_lim > 0)
-    {
-      struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent];
-      int slot = 4;
-
-      while (--slot >= 0)
-	{
-	  rtx insn = up->group[slot];
-	  enum machine_mode this_mode;
-	  rtx pat;
-
-	  if (! insn
-	      || GET_CODE (insn) != INSN
-	      || (pat = PATTERN (insn)) == 0
-	      || GET_CODE (pat) != SET)
-	    continue;
-
-	  this_mode = GET_MODE (SET_DEST (pat));
-	  if ((this_mode != SFmode
-	       && this_mode != DFmode)
-	      || this_mode == fpmode)
-	    continue;
-
-	  /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
-	     we will get a stall.  Loads and stores are independant
-	     of these rules.  */
-	  if (GET_CODE (SET_SRC (pat)) != ABS
-	      && GET_CODE (SET_SRC (pat)) != NEG
-	      && ((TMASK (get_attr_type (insn)) &
-		   (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) |
-		    TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRT) |
-                    TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0))
-	    return 1;
-	}
-      hist_lim--;
-      hist_ent = (hist_ent - 1) % (ULTRA_NUM_HIST - 1);
-    }
-
-  /* No conflicts, safe to dispatch.  */
-  return 0;
-}
-
-/* Find an instruction in LIST which has one of the
-   type attributes enumerated in TYPE_MASK.  START
-   says where to begin the search.
-
-   NOTE: This scheme depends upon the fact that we
-         have less than 32 distinct type attributes.  */
-
-static int ultra_types_avail;
-
-static rtx *
-ultra_find_type (type_mask, list, start)
-     int type_mask;
-     rtx *list;
-     int start;
-{
-  int i;
-
-  /* Short circuit if no such insn exists in the ready
-     at the moment.  */
-  if ((type_mask & ultra_types_avail) == 0)
-    return 0;
-
-  for (i = start; i >= 0; i--)
-    {
-      rtx insn = list[i];
-
-      if (recog_memoized (insn) >= 0
-	  && (TMASK(get_attr_type (insn)) & type_mask))
-	{
-	  enum machine_mode fpmode = SFmode;
-	  rtx pat = 0;
-	  int slot;
-	  int check_depend = 0;
-	  int check_fpmode_conflict = 0;
-
-	  if (GET_CODE (insn) == INSN
-	      && (pat = PATTERN(insn)) != 0
-	      && GET_CODE (pat) == SET
-	      && !(type_mask & (TMASK (TYPE_STORE) |
-				TMASK (TYPE_FPSTORE))))
-	    {
-	      check_depend = 1;
-	      if (GET_MODE (SET_DEST (pat)) == SFmode
-		  || GET_MODE (SET_DEST (pat)) == DFmode)
-		{
-		  fpmode = GET_MODE (SET_DEST (pat));
-		  check_fpmode_conflict = 1;
-		}
-	    }
-
-	  slot = 4;
-	  while(--slot >= 0)
-	    {
-	      rtx slot_insn = ultra_pipe.group[slot];
-	      rtx slot_pat;
-
-	      /* Already issued, bad dependency, or FPU
-		 mode conflict.  */
-	      if (slot_insn != 0
-		  && (slot_pat = PATTERN (slot_insn)) != 0
-		  && ((insn == slot_insn)
-		      || (check_depend == 1
-			  && GET_CODE (slot_insn) == INSN
-			  && GET_CODE (slot_pat) == SET
-			  && ((GET_CODE (SET_DEST (slot_pat)) == REG
-			       && GET_CODE (SET_SRC (pat)) == REG
-			       && REGNO (SET_DEST (slot_pat)) ==
-			            REGNO (SET_SRC (pat)))
-			      || (GET_CODE (SET_DEST (slot_pat)) == SUBREG
-				  && GET_CODE (SET_SRC (pat)) == SUBREG
-				  && REGNO (SUBREG_REG (SET_DEST (slot_pat))) ==
-				       REGNO (SUBREG_REG (SET_SRC (pat)))
-				  && SUBREG_WORD (SET_DEST (slot_pat)) ==
-				       SUBREG_WORD (SET_SRC (pat)))))
-		      || (check_fpmode_conflict == 1
-			  && GET_CODE (slot_insn) == INSN
-			  && GET_CODE (slot_pat) == SET
-			  && (GET_MODE (SET_DEST (slot_pat)) == SFmode
-			      || GET_MODE (SET_DEST (slot_pat)) == DFmode)
-			  && GET_MODE (SET_DEST (slot_pat)) != fpmode)))
-		goto next;
-	    }
-
-	  /* Check for peculiar result availability and dispatch
-	     interference situations.  */
-	  if (pat != 0
-	      && ultra_cycles_elapsed > 0)
-	    {
-	      rtx link;
-
-	      for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
-		{
-		  rtx link_insn = XEXP (link, 0);
-		  if (GET_CODE (link_insn) == INSN
-		      && recog_memoized (link_insn) >= 0
-		      && (TMASK (get_attr_type (link_insn)) &
-			  (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE)))
-		      && ! ultra_cmove_results_ready_p (link_insn))
-		    goto next;
-		}
-
-	      if (check_fpmode_conflict
-		  && ultra_fpmode_conflict_exists (fpmode))
-		goto next;
-	    }
-
-	  return &list[i];
-	}
-    next:
-      ;
-    }
-  return 0;
-}
-
-static void
-ultra_build_types_avail (ready, n_ready)
-  rtx *ready;
-  int n_ready;
-{
-  int i = n_ready - 1;
-
-  ultra_types_avail = 0;
-  while(i >= 0)
-    {
-      rtx insn = ready[i];
-
-      if (recog_memoized (insn) >= 0)
-	ultra_types_avail |= TMASK (get_attr_type (insn));
-
-      i -= 1;
-    }
-}
-
-/* Place insn pointed to my IP into the pipeline.
-   Make element THIS of READY be that insn if it
-   is not already.  TYPE indicates the pipeline class
-   this insn falls into.  */
-static void
-ultra_schedule_insn (ip, ready, this, type)
-     rtx *ip;
-     rtx *ready;
-     int this;
-     enum ultra_code type;
-{
-  int pipe_slot;
-  char mask = ultra_pipe.free_slot_mask;
-
-  /* Obtain free slot.  */
-  for (pipe_slot = 0; pipe_slot < 4; pipe_slot++)
-    if ((mask & (1 << pipe_slot)) != 0)
-      break;
-  if (pipe_slot == 4)
-    abort ();
-
-  /* In it goes, and it hasn't been committed yet.  */
-  ultra_pipe.group[pipe_slot] = *ip;
-  ultra_pipe.codes[pipe_slot] = type;
-  ultra_pipe.contents[type] = 1;
-  if (UMASK (type) &
-      (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
-    ultra_pipe.num_ieu_insns += 1;
-
-  ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot));
-  ultra_pipe.group_size += 1;
-  ultra_pipe.commit[pipe_slot] = 0;
-
-  /* Update ready list.  */
-  if (ip != &ready[this])
-    {
-      rtx temp = *ip;
-
-      *ip = ready[this];
-      ready[this] = temp;
-    }
-}
-
-/* Advance to the next pipeline group.  */
-static void
-ultra_flush_pipeline ()
-{
-  ultra_cur_hist = (ultra_cur_hist + 1) % (ULTRA_NUM_HIST - 1);
-  ultra_cycles_elapsed += 1;
-  bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
-  ultra_pipe.free_slot_mask = 0xf;
-}
-
-static int ultra_reorder_called_this_block;
-
-/* Init our data structures for this current block.  */
-void
-ultrasparc_sched_init (dump, sched_verbose)
-     FILE *dump ATTRIBUTE_UNUSED;
-     int sched_verbose ATTRIBUTE_UNUSED;
-{
-  bzero ((char *) ultra_pipe_hist, sizeof ultra_pipe_hist);
-  ultra_cur_hist = 0;
-  ultra_cycles_elapsed = 0;
-  ultra_reorder_called_this_block = 0;
-  ultra_pipe.free_slot_mask = 0xf;
-}
-
-/* INSN has been scheduled, update pipeline commit state
-   and return how many instructions are still to be
-   scheduled in this group.  */
-int
-ultrasparc_variable_issue (insn)
-     rtx insn;
-{
-  struct ultrasparc_pipeline_state *up = &ultra_pipe;
-  int i, left_to_fire;
-
-  left_to_fire = 0;
-  for (i = 0; i < 4; i++)
-    {
-      if (up->group[i] == 0)
-	continue;
-
-      if (up->group[i] == insn)
-	{
-	  up->commit[i] = 1;
-	}
-      else if (! up->commit[i])
-	left_to_fire++;
-    }
-
-  return left_to_fire;
-}
-
-/* In actual_hazard_this_instance, we may have yanked some
-   instructions from the ready list due to conflict cost
-   adjustments.  If so, and such an insn was in our pipeline
-   group, remove it and update state.  */
-static void
-ultra_rescan_pipeline_state (ready, n_ready)
-     rtx *ready;
-     int n_ready;
-{
-  struct ultrasparc_pipeline_state *up = &ultra_pipe;
-  int i;
-
-  for (i = 0; i < 4; i++)
-    {
-      rtx insn = up->group[i];
-      int j;
-
-      if (! insn)
-	continue;
-
-      /* If it has been committed, then it was removed from
-	 the ready list because it was actually scheduled,
-	 and that is not the case we are searching for here.  */
-      if (up->commit[i] != 0)
-	continue;
-
-      for (j = n_ready - 1; j >= 0; j--)
-	if (ready[j] == insn)
-	  break;
-
-      /* If we didn't find it, toss it.  */
-      if (j < 0)
-	{
-	  enum ultra_code ucode = up->codes[i];
-
-	  up->group[i] = 0;
-	  up->codes[i] = NONE;
-	  up->contents[ucode] = 0;
-	  if (UMASK (ucode) &
-	      (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
-	    up->num_ieu_insns -= 1;
-
-	  up->free_slot_mask |= (1 << i);
-	  up->group_size -= 1;
-	  up->commit[i] = 0;
-	}
-    }
-}
-
-void
-ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
-     FILE *dump;
-     int sched_verbose;
-     rtx *ready;
-     int n_ready;
-{
-  struct ultrasparc_pipeline_state *up = &ultra_pipe;
-  int i, this_insn;
-
-  /* We get called once unnecessarily per block of insns
-     scheduled.  */
-  if (ultra_reorder_called_this_block == 0)
-    {
-      ultra_reorder_called_this_block = 1;
-      return;
-    }
-
-  if (sched_verbose)
-    {
-      int n;
-
-      fprintf (dump, "\n;;\tUltraSPARC Looking at [");
-      for (n = n_ready - 1; n >= 0; n--)
-	{
-	  rtx insn = ready[n];
-	  enum ultra_code ucode;
-
-	  if (recog_memoized (insn) < 0)
-	    continue;
-	  ucode = ultra_code_from_mask (TMASK (get_attr_type (insn)));
-	  if (n != 0)
-	    fprintf (dump, "%s(%d) ",
-		     ultra_code_names[ucode],
-		     INSN_UID (insn));
-	  else
-	    fprintf (dump, "%s(%d)",
-		     ultra_code_names[ucode],
-		     INSN_UID (insn));
-	}
-      fprintf (dump, "]\n");
-    }
-
-  this_insn = n_ready - 1;
-
-  /* Skip over junk we don't understand.  */
-  while ((this_insn >= 0)
-	 && recog_memoized (ready[this_insn]) < 0)
-    this_insn--;
-
-  ultra_build_types_avail (ready, this_insn + 1);
-
-  while (this_insn >= 0) {
-    int old_group_size = up->group_size;
-
-    if (up->group_size != 0)
-      {
-	int num_committed;
-
-	num_committed = (up->commit[0] + up->commit[1] +
-			 up->commit[2] + up->commit[3]);
-	/* If nothing has been commited from our group, or all of
-	   them have.  Clear out the (current cycle's) pipeline
-	   state and start afresh.  */
-	if (num_committed == 0
-	    || num_committed == up->group_size)
-	  {
-	    ultra_flush_pipeline ();
-	    up = &ultra_pipe;
-	    old_group_size = 0;
-	  }
-	else
-	  {
-	    /* OK, some ready list insns got requeued and thus removed
-	       from the ready list.  Account for this fact.  */
-	    ultra_rescan_pipeline_state (ready, n_ready);
-
-	    /* Something "changed", make this look like a newly
-	       formed group so the code at the end of the loop
-	       knows that progress was in fact made.  */
-	    if (up->group_size != old_group_size)
-	      old_group_size = 0;
-	  }
-      }
-
-    if (up->group_size == 0)
-      {
-	/* If the pipeline is (still) empty and we have any single
-	   group insns, get them out now as this is a good time.  */
-	rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) |
-				    TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) |
-				    TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)),
-				   ready, this_insn);
-	if (ip)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, SINGLE);
-	    break;
-	  }
-
-	/* If we are not in the process of emptying out the pipe, try to
-	   obtain an instruction which must be the first in it's group.  */
-	ip = ultra_find_type ((TMASK (TYPE_CALL) |
-			       TMASK (TYPE_CALL_NO_DELAY_SLOT) |
-			       TMASK (TYPE_UNCOND_BRANCH)),
-			      ready, this_insn);
-	if (ip)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, IEU1);
-	    this_insn--;
-	  }
-	else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) |
-					 TMASK (TYPE_FPDIVD) |
-					 TMASK (TYPE_FPSQRT)),
-					ready, this_insn)) != 0)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, FPM);
-	    this_insn--;
-	  }
-      }
-
-    /* Try to fill the integer pipeline.  First, look for an IEU0 specific
-       operation.  We can't do more IEU operations if the first 3 slots are
-       all full or we have dispatched two IEU insns already.  */
-    if ((up->free_slot_mask & 0x7) != 0
-	&& up->num_ieu_insns < 2
-	&& up->contents[IEU0] == 0
-	&& up->contents[IEUN] == 0)
-      {
-	rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn);
-	if (ip)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, IEU0);
-	    this_insn--;
-	  }
-      }
-
-    /* If we can, try to find an IEU1 specific or an unnamed
-       IEU instruction.  */
-    if ((up->free_slot_mask & 0x7) != 0
-	&& up->num_ieu_insns < 2)
-      {
-	rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
-				    TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) |
-				    (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)),
-				   ready, this_insn);
-	if (ip)
-	  {
-	    rtx insn = *ip;
-
-	    ultra_schedule_insn (ip, ready, this_insn,
-				 (!up->contents[IEU1]
-				  && get_attr_type (insn) == TYPE_COMPARE)
-				 ? IEU1 : IEUN);
-	    this_insn--;
-	  }
-      }
-
-    /* If only one IEU insn has been found, try to find another unnamed
-       IEU operation or an IEU1 specific one.  */
-    if ((up->free_slot_mask & 0x7) != 0
-	&& up->num_ieu_insns < 2)
-      {
-	rtx *ip;
-	int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
-		     TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY));
-
-	if (!up->contents[IEU1])
-	  tmask |= TMASK (TYPE_COMPARE);
-	ip = ultra_find_type (tmask, ready, this_insn);
-	if (ip)
-	  {
-	    rtx insn = *ip;
-
-	    ultra_schedule_insn (ip, ready, this_insn,
-				 (!up->contents[IEU1]
-				  && get_attr_type (insn) == TYPE_COMPARE)
-				 ? IEU1 : IEUN);
-	    this_insn--;
-	  }
-      }
-
-    /* Try for a load or store, but such an insn can only be issued
-       if it is within' one of the first 3 slots.  */
-    if ((up->free_slot_mask & 0x7) != 0
-        && up->contents[LSU] == 0)
-      {
-	rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
-				   TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
-				   TMASK (TYPE_FPSTORE)), ready, this_insn);
-	if (ip)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, LSU);
-	    this_insn--;
-	  }
-      }
-
-    /* Now find FPU operations, first FPM class.  But not divisions or
-       square-roots because those will break the group up.  Unlike all
-       the previous types, these can go in any slot.  */
-    if (up->free_slot_mask != 0
-	&& up->contents[FPM] == 0)
-      {
-	rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn);
-	if (ip)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, FPM);
-	    this_insn--;
-	  }
-      }
-    
-    /* Continue on with FPA class if we have not filled the group already.  */
-    if (up->free_slot_mask != 0
-	&& up->contents[FPA] == 0)
-      {
-	rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
-				    TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)),
-				   ready, this_insn);
-	if (ip)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, FPA);
-	    this_insn--;
-	  }
-      }
-
-    /* Finally, maybe stick a branch in here.  */
-    if (up->free_slot_mask != 0
-	&& up->contents[CTI] == 0)
-      {
-	rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn);
-
-	/* Try to slip in a branch only if it is one of the
-	   next 2 in the ready list.  */
-	if (ip && ((&ready[this_insn] - ip) < 2))
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, CTI);
-	    this_insn--;
-	  }
-      }
-
-    up->group_size = 0;
-    for (i = 0; i < 4; i++)
-      if ((up->free_slot_mask & (1 << i)) == 0)
-	up->group_size++;
-
-    /* See if we made any progress...  */
-    if (old_group_size != up->group_size)
-      break;
-
-    /* Clean out the (current cycle's) pipeline state
-       and try once more.  If we placed no instructions
-       into the pipeline at all, it means a real hard
-       conflict exists with some earlier issued instruction
-       so we must advance to the next cycle to clear it up.  */
-    if (up->group_size == 0)
-      {
-	ultra_flush_pipeline ();
-	up = &ultra_pipe;
-      }
-    else
-      {
-	bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
-	ultra_pipe.free_slot_mask = 0xf;
-      }
-  }
-
-  if (sched_verbose)
-    {
-      int n, gsize;
-
-      fprintf (dump, ";;\tUltraSPARC Launched   [");
-      gsize = up->group_size;
-      for (n = 0; n < 4; n++)
-	{
-	  rtx insn = up->group[n];
-
-	  if (! insn)
-	    continue;
-
-	  gsize -= 1;
-	  if (gsize != 0)
-	    fprintf (dump, "%s(%d) ",
-		     ultra_code_names[up->codes[n]],
-		     INSN_UID (insn));
-	  else
-	    fprintf (dump, "%s(%d)",
-		     ultra_code_names[up->codes[n]],
-		     INSN_UID (insn));
-	}
-      fprintf (dump, "]\n");
-    }
-}
-
-int                                                           
-sparc_issue_rate ()
-{
-  switch (sparc_cpu)
-    {
-    default:                                 
-      return 1;                                                    
-    case PROCESSOR_V9:                                                
-      /* Assume V9 processors are capable of at least dual-issue.  */
-      return 2;
-    case PROCESSOR_SUPERSPARC:                                        
-      return 3;                                                      
-    case PROCESSOR_HYPERSPARC:
-    case PROCESSOR_SPARCLITE86X:
-      return 2;
-    case PROCESSOR_ULTRASPARC:                                            
-      return 4;                                                    
-    }
-}
-
-static int
-set_extends(x, insn)
-     rtx x, insn;
-{
-  register rtx pat = PATTERN (insn);
-
-  switch (GET_CODE (SET_SRC (pat)))
-    {
-      /* Load and some shift instructions zero extend. */
-    case MEM:
-    case ZERO_EXTEND:
-      /* sethi clears the high bits */
-    case HIGH:
-      /* LO_SUM is used with sethi.  sethi cleared the high
-	 bits and the values used with lo_sum are positive */
-    case LO_SUM:
-      /* Store flag stores 0 or 1 */
-    case LT: case LTU:
-    case GT: case GTU:
-    case LE: case LEU:
-    case GE: case GEU:
-    case EQ:
-    case NE:
-      return 1;
-    case AND:
-      {
-	rtx op1 = XEXP (SET_SRC (pat), 1);
-	if (GET_CODE (op1) == CONST_INT)
-	  return INTVAL (op1) >= 0;
-	if (GET_CODE (XEXP (SET_SRC (pat), 0)) == REG
-	    && sparc_check_64 (XEXP (SET_SRC (pat), 0), insn) == 1)
-	  return 1;
-	if (GET_CODE (op1) == REG
-	    && sparc_check_64 ((op1), insn) == 1)
-	  return 1;
-      }
-    case ASHIFT:
-    case LSHIFTRT:
-      return GET_MODE (SET_SRC (pat)) == SImode;
-      /* Positive integers leave the high bits zero. */
-    case CONST_DOUBLE:
-      return ! (CONST_DOUBLE_LOW (x) & 0x80000000);
-    case CONST_INT:
-      return ! (INTVAL (x) & 0x80000000);
-    case ASHIFTRT:
-    case SIGN_EXTEND:
-      return - (GET_MODE (SET_SRC (pat)) == SImode);
-    default:
-      return 0;
-    }
-}
-
-/* We _ought_ to have only one kind per function, but... */
-static rtx sparc_addr_diff_list;
-static rtx sparc_addr_list;
-
-void
-sparc_defer_case_vector (lab, vec, diff)
-     rtx lab, vec;
-     int diff;
-{
-  vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
-  if (diff)
-    sparc_addr_diff_list
-      = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
-  else
-    sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
-}
-
-static void 
-sparc_output_addr_vec (vec)
-     rtx vec;
-{
-  rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
-  int idx, vlen = XVECLEN (body, 0);
-
-#ifdef ASM_OUTPUT_ADDR_VEC_START  
-  ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
-#endif
-
-#ifdef ASM_OUTPUT_CASE_LABEL
-  ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
-			 NEXT_INSN (lab));
-#else
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
-#endif
-
-  for (idx = 0; idx < vlen; idx++)
-    {
-      ASM_OUTPUT_ADDR_VEC_ELT
-	(asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
-    }
-    
-#ifdef ASM_OUTPUT_ADDR_VEC_END
-  ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
-#endif
-}
-
-static void 
-sparc_output_addr_diff_vec (vec)
-     rtx vec;
-{
-  rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
-  rtx base = XEXP (XEXP (body, 0), 0);
-  int idx, vlen = XVECLEN (body, 1);
-
-#ifdef ASM_OUTPUT_ADDR_VEC_START  
-  ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
-#endif
-
-#ifdef ASM_OUTPUT_CASE_LABEL
-  ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
-			 NEXT_INSN (lab));
-#else
-  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
-#endif
-
-  for (idx = 0; idx < vlen; idx++)
-    {
-      ASM_OUTPUT_ADDR_DIFF_ELT
-        (asm_out_file,
-         body,
-         CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
-         CODE_LABEL_NUMBER (base));
-    }
-    
-#ifdef ASM_OUTPUT_ADDR_VEC_END
-  ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
-#endif
-}
-
-static void
-sparc_output_deferred_case_vectors ()
-{
-  rtx t;
-  int align;
-
-  if (sparc_addr_list == NULL_RTX
-      && sparc_addr_diff_list == NULL_RTX)
-    return;
-
-  /* Align to cache line in the function's code section.  */
-  function_section (current_function_decl);
-
-  align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
-  if (align > 0)
-    ASM_OUTPUT_ALIGN (asm_out_file, align);
-  
-  for (t = sparc_addr_list; t ; t = XEXP (t, 1))
-    sparc_output_addr_vec (XEXP (t, 0));
-  for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
-    sparc_output_addr_diff_vec (XEXP (t, 0));
-
-  sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
-}
-
-/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
-   unknown.  Return 1 if the high bits are zero, -1 if the register is
-   sign extended.  */
-int
-sparc_check_64 (x, insn)
-     rtx x, insn;
-{
-  /* If a register is set only once it is safe to ignore insns this
-     code does not know how to handle.  The loop will either recognize
-     the single set and return the correct value or fail to recognize
-     it and return 0.  */
-  int set_once = 0;
-
-  if (GET_CODE (x) == REG
-      && flag_expensive_optimizations
-      && REG_N_SETS (REGNO (x)) == 1)
-    set_once = 1;
-
-  if (insn == 0)
-    {
-      if (set_once)
-	insn = get_last_insn_anywhere ();
-      else
-	return 0;
-    }
-
-  while ((insn = PREV_INSN (insn)))
-    {
-      switch (GET_CODE (insn))
-	{
-	case JUMP_INSN:
-	case NOTE:
-	  break;
-	case CODE_LABEL:
-	case CALL_INSN:
-	default:
-	  if (! set_once)
-	    return 0;
-	  break;
-	case INSN:
-	  {
-	    rtx pat = PATTERN (insn);
-	    if (GET_CODE (pat) != SET)
-	      return 0;
-	    if (rtx_equal_p (x, SET_DEST (pat)))
-	      return set_extends (x, insn);
-	    if (reg_overlap_mentioned_p (SET_DEST (pat), x))
-	      return 0;
-	  }
-	}
-    }
-  return 0;
-}
-
-char *
-sparc_v8plus_shift (operands, insn, opcode)
-     rtx *operands;
-     rtx insn;
-     char *opcode;
-{
-  static char asm_code[60];
-
-  if (GET_CODE (operands[3]) == SCRATCH)
-    operands[3] = operands[0];
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      output_asm_insn ("mov %1,%3", operands);
-    }
-  else
-    {
-      output_asm_insn ("sllx %H1,32,%3", operands);
-      if (sparc_check_64 (operands[1], insn) <= 0)
-	output_asm_insn ("srl %L1,0,%L1", operands);
-      output_asm_insn ("or %L1,%3,%3", operands);
-    }
-
-  strcpy(asm_code, opcode);
-  if (which_alternative != 2)
-    return strcat (asm_code, " %0,%2,%L0\n\tsrlx %L0,32,%H0");
-  else
-    return strcat (asm_code, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0");
-}
-
-
-/* Return 1 if DEST and SRC reference only global and in registers. */
-
-int
-sparc_return_peephole_ok (dest, src)
-     rtx dest, src;
-{
-  if (! TARGET_V9)
-    return 0;
-  if (leaf_function)
-    return 0;
-  if (GET_CODE (src) != CONST_INT
-      && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
-    return 0;
-  return IN_OR_GLOBAL_P (dest);
-}
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
deleted file mode 100755
index 5080b3e..0000000
--- a/gcc/config/sparc/sparc.h
+++ /dev/null
@@ -1,3504 +0,0 @@
-/* Definitions of target machine for GNU compiler, for Sun SPARC.
-   Copyright (C) 1987, 88, 89, 92, 94-98, 1999 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@cygnus.com).
-   64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
-   at Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Note that some other tm.h files include this one and then override
-   whatever definitions are necessary.  */
-
-/* Specify this in a cover file to provide bi-architecture (32/64) support.  */
-/* #define SPARC_BI_ARCH */
-
-/* Macro used later in this file to determine default architecture.  */
-#define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
-
-/* TARGET_ARCH{32,64} are the main macros to decide which of the two
-   architectures to compile for.  We allow targets to choose compile time or
-   runtime selection.  */
-#ifdef SPARC_BI_ARCH
-#ifdef IN_LIBGCC2
-#if defined(__sparcv9) || defined(__sparcv_v9) || defined(__arch64__)
-#define TARGET_ARCH32 0
-#else
-#define TARGET_ARCH32 1
-#endif /* V9 sparc */
-#else
-#define TARGET_ARCH32 (! TARGET_64BIT)
-#endif /* IN_LIBGCC2 */
-#else
-#define TARGET_ARCH32 (DEFAULT_ARCH32_P)
-#endif /* SPARC_BI_ARCH */
-#define TARGET_ARCH64 (! TARGET_ARCH32)
-
-/* Code model selection.
-   -mcmodel is used to select the v9 code model.
-   Different code models aren't supported for v8 code.
-
-   TARGET_CM_32:     32 bit address space, top 32 bits = 0,
-		     pointers are 32 bits.  Note that this isn't intended
-                     to imply a v8 abi.
-
-   TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
-                     avoid generating %uhi and %ulo terms,
-		     pointers are 64 bits.
-
-   TARGET_CM_MEDMID: 64 bit address space.
-                     The executable must be in the low 16 TB of memory.
-                     This corresponds to the low 44 bits, and the %[hml]44
-                     relocs are used.  The text segment has a maximum size
-                     of 31 bits.
-
-   TARGET_CM_MEDANY: 64 bit address space.
-                     The text and data segments have a maximum size of 31
-                     bits and may be located anywhere.  The maximum offset
-                     from any instruction to the label _GLOBAL_OFFSET_TABLE_
-                     is 31 bits.
-
-   TARGET_CM_EMBMEDANY: 64 bit address space.
-                     The text and data segments have a maximum size of 31 bits
-                     and may be located anywhere.  Register %g4 contains
-                     the start address of the data segment.
-*/
-
-enum cmodel {
-  CM_32,
-  CM_MEDLOW,
-  CM_MEDMID,
-  CM_MEDANY,
-  CM_EMBMEDANY
-};
-
-/* Value of -mcmodel specified by user.  */
-extern char *sparc_cmodel_string;
-/* One of CM_FOO.  */
-extern enum cmodel sparc_cmodel;
-
-/* V9 code model selection.  */
-#define TARGET_CM_MEDLOW    (sparc_cmodel == CM_MEDLOW)
-#define TARGET_CM_MEDMID    (sparc_cmodel == CM_MEDMID)
-#define TARGET_CM_MEDANY    (sparc_cmodel == CM_MEDANY)
-#define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
-
-#define SPARC_DEFAULT_CMODEL CM_MEDLOW
-
-/* This is call-clobbered in the normal ABI, but is reserved in the
-   home grown (aka upward compatible) embedded ABI.  */
-#define EMBMEDANY_BASE_REG "%g4"
-
-/* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
-   and specified by the user via --with-cpu=foo.
-   This specifies the cpu implementation, not the architecture size.  */
-/* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit 
-   capable cpu's.  */
-#define TARGET_CPU_sparc	0
-#define TARGET_CPU_v7		0	/* alias for previous */
-#define TARGET_CPU_sparclet	1
-#define TARGET_CPU_sparclite	2
-#define TARGET_CPU_v8		3	/* generic v8 implementation */
-#define TARGET_CPU_supersparc	4
-#define TARGET_CPU_hypersparc   5
-#define TARGET_CPU_sparc86x	6
-#define TARGET_CPU_sparclite86x	6
-#define TARGET_CPU_v9		7	/* generic v9 implementation */
-#define TARGET_CPU_sparcv9	7	/* alias */
-#define TARGET_CPU_sparc64	7	/* alias */
-#define TARGET_CPU_ultrasparc	8
-
-#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
- || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
-
-#define CPP_CPU32_DEFAULT_SPEC ""
-#define ASM_CPU32_DEFAULT_SPEC ""
-
-#if TARGET_CPU_DEFAULT == TARGET_CPU_v9
-/* ??? What does Sun's CC pass?  */
-#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
-/* ??? It's not clear how other assemblers will handle this, so by default
-   use GAS.  Sun's Solaris assembler recognizes -xarch=v8plus, but this case
-   is handled in sol2.h.  */
-#define ASM_CPU64_DEFAULT_SPEC "-Av9"
-#endif
-#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
-#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
-#define ASM_CPU64_DEFAULT_SPEC "-Av9a"
-#endif
-
-#else
-
-#define CPP_CPU64_DEFAULT_SPEC ""
-#define ASM_CPU64_DEFAULT_SPEC ""
-
-#if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
- || TARGET_CPU_DEFAULT == TARGET_CPU_v8
-#define CPP_CPU32_DEFAULT_SPEC ""
-#define ASM_CPU32_DEFAULT_SPEC ""
-#endif
-
-#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
-#define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
-#define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
-#endif
-
-#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
-#define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
-#define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
-#endif
-
-#if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
-#define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
-#define ASM_CPU32_DEFAULT_SPEC ""
-#endif
-
-#if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
-#define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
-#define ASM_CPU32_DEFAULT_SPEC ""
-#endif
-
-#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
-#define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
-#define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
-#endif
-
-#endif
-
-#if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
-Unrecognized value in TARGET_CPU_DEFAULT.
-#endif
-
-#ifdef SPARC_BI_ARCH
-
-#define CPP_CPU_DEFAULT_SPEC \
-(DEFAULT_ARCH32_P ? "\
-%{m64:" CPP_CPU64_DEFAULT_SPEC "} \
-%{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
-" : "\
-%{m32:" CPP_CPU32_DEFAULT_SPEC "} \
-%{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
-")
-#define ASM_CPU_DEFAULT_SPEC \
-(DEFAULT_ARCH32_P ? "\
-%{m64:" ASM_CPU64_DEFAULT_SPEC "} \
-%{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
-" : "\
-%{m32:" ASM_CPU32_DEFAULT_SPEC "} \
-%{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
-")
-
-#else /* !SPARC_BI_ARCH */
-
-#define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
-#define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
-
-#endif /* !SPARC_BI_ARCH */
-
-/* Names to predefine in the preprocessor for this target machine.
-   ??? It would be nice to not include any subtarget specific values here,
-   however there's no way to portably provide subtarget values to
-   CPP_PREFINES.  Also, -D values in CPP_SUBTARGET_SPEC don't get turned into
-   foo, __foo and __foo__.  */
-
-#define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -Asystem(unix) -Asystem(bsd)"
-
-/* Define macros to distinguish architectures.  */
-
-/* Common CPP definitions used by CPP_SPEC amongst the various targets
-   for handling -mcpu=xxx switches.  */
-#define CPP_CPU_SPEC "\
-%{mcypress:} \
-%{msparclite:-D__sparclite__} \
-%{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
-%{mv8:-D__sparc_v8__} \
-%{msupersparc:-D__supersparc__ -D__sparc_v8__} \
-%{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
-%{mcpu=sparclite:-D__sparclite__} \
-%{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
-%{mcpu=v8:-D__sparc_v8__} \
-%{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
-%{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
-%{mcpu=sparclite86x:-D__sparclite86x__} \
-%{mcpu=v9:-D__sparc_v9__} \
-%{mcpu=ultrasparc:-D__sparc_v9__} \
-%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
-"
-
-/* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
-   the right varags.h file when bootstrapping.  */
-/* ??? It's not clear what value we want to use for -Acpu/machine for
-   sparc64 in 32 bit environments, so for now we only use `sparc64' in
-   64 bit environments.  */
-
-#ifdef SPARC_BI_ARCH
-
-#define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \
--D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)"
-#define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
--D__arch64__ -Acpu(sparc64) -Amachine(sparc64)"
-
-#else
-
-#define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)"
-#define CPP_ARCH64_SPEC "-D__arch64__ -Acpu(sparc64) -Amachine(sparc64)"
-
-#endif
-
-#define CPP_ARCH_DEFAULT_SPEC \
-(DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
-
-#define CPP_ARCH_SPEC "\
-%{m32:%(cpp_arch32)} \
-%{m64:%(cpp_arch64)} \
-%{!m32:%{!m64:%(cpp_arch_default)}} \
-"
-
-/* Macros to distinguish endianness.  */
-#define CPP_ENDIAN_SPEC "\
-%{mlittle-endian:-D__LITTLE_ENDIAN__} \
-%{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
-
-/* Macros to distinguish the particular subtarget.  */
-#define CPP_SUBTARGET_SPEC ""
-
-#define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
-
-/* Prevent error on `-sun4' and `-target sun4' options.  */
-/* This used to translate -dalign to -malign, but that is no good
-   because it can't turn off the usual meaning of making debugging dumps.  */
-/* Translate old style -m<cpu> into new style -mcpu=<cpu>.
-   ??? Delete support for -m<cpu> for 2.9.  */
-
-#define CC1_SPEC "\
-%{sun4:} %{target:} \
-%{mcypress:-mcpu=cypress} \
-%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
-%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
-"
-
-/* Override in target specific files.  */
-#define ASM_CPU_SPEC "\
-%{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
-%{msparclite:-Asparclite} \
-%{mf930:-Asparclite} %{mf934:-Asparclite} \
-%{mcpu=sparclite:-Asparclite} \
-%{mcpu=sparclite86x:-Asparclite} \
-%{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
-%{mv8plus:-Av8plus} \
-%{mcpu=v9:-Av9} \
-%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
-%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
-"
-
-/* Word size selection, among other things.
-   This is what GAS uses.  Add %(asm_arch) to ASM_SPEC to enable.  */
-
-#define ASM_ARCH32_SPEC "-32"
-#define ASM_ARCH64_SPEC "-64"
-#define ASM_ARCH_DEFAULT_SPEC \
-(DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
-
-#define ASM_ARCH_SPEC "\
-%{m32:%(asm_arch32)} \
-%{m64:%(asm_arch64)} \
-%{!m32:%{!m64:%(asm_arch_default)}} \
-"
-
-/* Special flags to the Sun-4 assembler when using pipe for input.  */
-
-#define ASM_SPEC "\
-%| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
-%(asm_cpu) \
-"
-
-#define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}"
-
-/* Provide required defaults for linker -e and -d switches.  */
-
-#define LINK_SPEC \
- "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \
-  %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}"
-
-/* This macro defines names of additional specifications to put in the specs
-   that can be used in various specifications like CC1_SPEC.  Its definition
-   is an initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   specification name, and a string constant that used by the GNU CC driver
-   program.
-
-   Do not define this macro if it does not need to do anything.  */
-
-#define EXTRA_SPECS \
-  { "cpp_cpu",		CPP_CPU_SPEC },		\
-  { "cpp_cpu_default",	CPP_CPU_DEFAULT_SPEC },	\
-  { "cpp_arch32",	CPP_ARCH32_SPEC },	\
-  { "cpp_arch64",	CPP_ARCH64_SPEC },	\
-  { "cpp_arch_default",	CPP_ARCH_DEFAULT_SPEC },\
-  { "cpp_arch",		CPP_ARCH_SPEC },	\
-  { "cpp_endian",	CPP_ENDIAN_SPEC },	\
-  { "cpp_subtarget",	CPP_SUBTARGET_SPEC },	\
-  { "asm_cpu",		ASM_CPU_SPEC },		\
-  { "asm_cpu_default",	ASM_CPU_DEFAULT_SPEC },	\
-  { "asm_arch32",	ASM_ARCH32_SPEC },	\
-  { "asm_arch64",	ASM_ARCH64_SPEC },	\
-  { "asm_arch_default",	ASM_ARCH_DEFAULT_SPEC },\
-  { "asm_arch",		ASM_ARCH_SPEC },	\
-  SUBTARGET_EXTRA_SPECS
-
-#define SUBTARGET_EXTRA_SPECS
-
-#ifdef SPARC_BI_ARCH
-#define NO_BUILTIN_PTRDIFF_TYPE
-#define NO_BUILTIN_SIZE_TYPE
-#endif
-#define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
-#define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
-
-/* ??? This should be 32 bits for v9 but what can we do?  */
-#define WCHAR_TYPE "short unsigned int"
-#define WCHAR_TYPE_SIZE 16
-#define MAX_WCHAR_TYPE_SIZE 16
-
-/* Show we can debug even without a frame pointer.  */
-#define CAN_DEBUG_WITHOUT_FP
-
-/* To make profiling work with -f{pic,PIC}, we need to emit the profiling
-   code into the rtl.  Also, if we are profiling, we cannot eliminate
-   the frame pointer (because the return address will get smashed).  */
-
-void sparc_override_options ();
-
-#define OVERRIDE_OPTIONS \
-  do {									\
-    if (profile_flag || profile_block_flag || profile_arc_flag)		\
-      {									\
-	if (flag_pic)							\
-	  {								\
-	    char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC";	\
-	    warning ("%s and profiling conflict: disabling %s",		\
-		     pic_string, pic_string);				\
-	    flag_pic = 0;						\
-	  }								\
-	flag_omit_frame_pointer = 0;					\
-      }									\
-    sparc_override_options ();						\
-    SUBTARGET_OVERRIDE_OPTIONS;						\
-  } while (0)
-
-/* This is meant to be redefined in the host dependent files.  */
-#define SUBTARGET_OVERRIDE_OPTIONS
-
-/* These compiler options take an argument.  We ignore -target for now.  */
-
-#define WORD_SWITCH_TAKES_ARG(STR)				\
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR)				\
-  || !strcmp (STR, "target") || !strcmp (STR, "assert"))
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fprintf (stderr, " (sparc)");
-
-/* Generate DBX debugging information.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Nonzero if we should generate code to use the fpu.  */
-#define MASK_FPU 1
-#define TARGET_FPU (target_flags & MASK_FPU)
-
-/* Nonzero if we should use FUNCTION_EPILOGUE.  Otherwise, we
-   use fast return insns, but lose some generality.  */
-#define MASK_EPILOGUE 2
-#define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
-
-/* Nonzero if we should assume that double pointers might be unaligned.
-   This can happen when linking gcc compiled code with other compilers,
-   because the ABI only guarantees 4 byte alignment.  */
-#define MASK_UNALIGNED_DOUBLES 4
-#define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
-
-/* Nonzero means that we should generate code for a v8 sparc.  */
-#define MASK_V8 0x8
-#define TARGET_V8 (target_flags & MASK_V8)
-
-/* Nonzero means that we should generate code for a sparclite.
-   This enables the sparclite specific instructions, but does not affect
-   whether FPU instructions are emitted.  */
-#define MASK_SPARCLITE 0x10
-#define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
-
-/* Nonzero if we're compiling for the sparclet.  */
-#define MASK_SPARCLET 0x20
-#define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
-
-/* Nonzero if we're compiling for v9 sparc.
-   Note that v9's can run in 32 bit mode so this doesn't necessarily mean
-   the word size is 64.  */
-#define MASK_V9 0x40
-#define TARGET_V9 (target_flags & MASK_V9)
-
-/* Non-zero to generate code that uses the instructions deprecated in
-   the v9 architecture.  This option only applies to v9 systems.  */
-/* ??? This isn't user selectable yet.  It's used to enable such insns
-   on 32 bit v9 systems and for the moment they're permanently disabled
-   on 64 bit v9 systems.  */
-#define MASK_DEPRECATED_V8_INSNS 0x80
-#define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
-
-/* Mask of all CPU selection flags.  */
-#define MASK_ISA \
-(MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
-
-/* Non-zero means don't pass `-assert pure-text' to the linker.  */
-#define MASK_IMPURE_TEXT 0x100
-#define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
-
-/* Nonzero means that we should generate code using a flat register window
-   model, i.e. no save/restore instructions are generated, which is
-   compatible with normal sparc code.
-   The frame pointer is %i7 instead of %fp.  */
-#define MASK_FLAT 0x200
-#define TARGET_FLAT (target_flags & MASK_FLAT)
-
-/* Nonzero means use the registers that the Sparc ABI reserves for
-   application software.  This must be the default to coincide with the
-   setting in FIXED_REGISTERS.  */
-#define MASK_APP_REGS 0x400
-#define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
-
-/* Option to select how quad word floating point is implemented.
-   When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
-   Otherwise, we use the SPARC ABI quad library functions.  */
-#define MASK_HARD_QUAD 0x800
-#define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
-
-/* Non-zero on little-endian machines.  */
-/* ??? Little endian support currently only exists for sparclet-aout and
-   sparc64-elf configurations.  May eventually want to expand the support
-   to all targets, but for now it's kept local to only those two.  */
-#define MASK_LITTLE_ENDIAN 0x1000
-#define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
-
-/* 0x2000, 0x4000 are unused */
-
-/* Nonzero if pointers are 64 bits.
-   At the moment it must follow architecture size flag.  */
-#define MASK_PTR64 0x8000
-#define TARGET_PTR64 (target_flags & MASK_PTR64)
-
-/* Nonzero if generating code to run in a 64 bit environment.
-   This is intended to only be used by TARGET_ARCH{32,64} as they are the
-   mechanism used to control compile time or run time selection.  */
-#define MASK_64BIT 0x10000
-#define TARGET_64BIT (target_flags & MASK_64BIT)
-
-/* 0x20000,0x40000 unused */
-
-/* Non-zero means use a stack bias of 2047.  Stack offsets are obtained by
-   adding 2047 to %sp.  This option is for v9 only and is the default.  */
-#define MASK_STACK_BIAS 0x80000
-#define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
-
-/* Non-zero means %g0 is a normal register.
-   We still clobber it as necessary, but we can't rely on it always having
-   a zero value.
-   We don't bother to support this in true 64 bit mode.  */
-#define MASK_LIVE_G0 0x100000
-#define TARGET_LIVE_G0 (target_flags & MASK_LIVE_G0)
-
-/* Non-zero means the cpu has broken `save' and `restore' insns, only
-   the trivial versions work (save %g0,%g0,%g0; restore %g0,%g0,%g0).
-   We assume the environment will properly handle or otherwise avoid
-   trouble associated with an interrupt occurring after the `save' or trap
-   occurring during it.  */
-#define MASK_BROKEN_SAVERESTORE 0x200000
-#define TARGET_BROKEN_SAVERESTORE (target_flags & MASK_BROKEN_SAVERESTORE)
-
-/* Non-zero means -m{,no-}fpu was passed on the command line.  */
-#define MASK_FPU_SET 0x400000
-#define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
-
-/* Use the UltraSPARC Visual Instruction Set extensions.  */
-#define MASK_VIS 0x1000000          
-#define TARGET_VIS (target_flags & MASK_VIS)
-
-/* Compile for Solaris V8+.  32 bit Solaris preserves the high bits of
-   the current out and global registers.  Linux saves the high bits on
-   context switches but not signals.  */
-#define MASK_V8PLUS 0x2000000                 
-#define TARGET_V8PLUS (target_flags & MASK_V8PLUS)                            
-
-/* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
-   TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
-   to get high 32 bits.  False in V8+ or V9 because multiply stores
-   a 64 bit result in a register.  */
-
-#define TARGET_HARD_MUL32				\
-  ((TARGET_V8 || TARGET_SPARCLITE			\
-    || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS)	\
-   && ! TARGET_V8PLUS)
-
-#define TARGET_HARD_MUL					\
-  (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET	\
-   || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)                        
-
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  { {"fpu", MASK_FPU | MASK_FPU_SET},	\
-    {"no-fpu", -MASK_FPU},		\
-    {"no-fpu", MASK_FPU_SET},		\
-    {"hard-float", MASK_FPU | MASK_FPU_SET}, \
-    {"soft-float", -MASK_FPU},		\
-    {"soft-float", MASK_FPU_SET},	\
-    {"epilogue", MASK_EPILOGUE},	\
-    {"no-epilogue", -MASK_EPILOGUE},	\
-    {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \
-    {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \
-    {"impure-text", MASK_IMPURE_TEXT},	\
-    {"no-impure-text", -MASK_IMPURE_TEXT}, \
-    {"flat", MASK_FLAT},		\
-    {"no-flat", -MASK_FLAT},		\
-    {"app-regs", MASK_APP_REGS},	\
-    {"no-app-regs", -MASK_APP_REGS},	\
-    {"hard-quad-float", MASK_HARD_QUAD}, \
-    {"soft-quad-float", -MASK_HARD_QUAD}, \
-    {"v8plus", MASK_V8PLUS},		\
-    {"no-v8plus", -MASK_V8PLUS},	\
-    {"vis", MASK_VIS},			\
-    {"no-vis", -MASK_VIS},		\
-    /* ??? These are deprecated, coerced to -mcpu=.  Delete in 2.9.  */ \
-    {"cypress", 0},			\
-    {"sparclite", 0},			\
-    {"f930", 0},			\
-    {"f934", 0},			\
-    {"v8", 0},				\
-    {"supersparc", 0},			\
-    /* End of deprecated options.  */	\
-    {"ptr64", MASK_PTR64},		\
-    {"ptr32", -MASK_PTR64},		\
-    {"32", -MASK_64BIT},		\
-    {"64", MASK_64BIT},			\
-    {"stack-bias", MASK_STACK_BIAS},	\
-    {"no-stack-bias", -MASK_STACK_BIAS}, \
-    SUBTARGET_SWITCHES			\
-    { "", TARGET_DEFAULT}}
-
-/* MASK_APP_REGS must always be the default because that's what
-   FIXED_REGISTERS is set to and -ffixed- is processed before
-   CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs).  */
-#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
-
-/* This is meant to be redefined in target specific files.  */
-#define SUBTARGET_SWITCHES
-
-/* Processor type.
-   These must match the values for the cpu attribute in sparc.md.  */
-enum processor_type {
-  PROCESSOR_V7,
-  PROCESSOR_CYPRESS,
-  PROCESSOR_V8,
-  PROCESSOR_SUPERSPARC,
-  PROCESSOR_SPARCLITE,
-  PROCESSOR_F930,
-  PROCESSOR_F934,
-  PROCESSOR_HYPERSPARC,
-  PROCESSOR_SPARCLITE86X,
-  PROCESSOR_SPARCLET,
-  PROCESSOR_TSC701,
-  PROCESSOR_V9,
-  PROCESSOR_ULTRASPARC
-};
-
-/* This is set from -m{cpu,tune}=xxx.  */
-extern enum processor_type sparc_cpu;
-
-/* Recast the cpu class to be the cpu attribute.
-   Every file includes us, but not every file includes insn-attr.h.  */
-#define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an
-   initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   fixed part of the option name, and the address of a variable. 
-   The variable, type `char *', is set to the variable part of the
-   given option if the fixed part matches.  The actual option name
-   is made by appending `-m' to the specified name.
-
-   Here is an example which defines `-mshort-data-NUMBER'.  If the
-   given option is `-mshort-data-512', the variable `m88k_short_data'
-   will be set to the string `"512"'.
-
-	extern char *m88k_short_data;
-	#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } }  */
-
-#define TARGET_OPTIONS \
-{							\
-  { "cpu=",  &sparc_select[1].string },			\
-  { "tune=", &sparc_select[2].string },			\
-  { "cmodel=", &sparc_cmodel_string },			\
-  { "align-loops=",	&sparc_align_loops_string },	\
-  { "align-jumps=",	&sparc_align_jumps_string },	\
-  { "align-functions=",	&sparc_align_funcs_string },	\
-  SUBTARGET_OPTIONS 					\
-}
-
-/* This is meant to be redefined in target specific files.  */
-#define SUBTARGET_OPTIONS
-
-/* sparc_select[0] is reserved for the default cpu.  */
-struct sparc_cpu_select
-{
-  char *string;
-  char *name;
-  int set_tune_p;
-  int set_arch_p;
-};
-
-extern struct sparc_cpu_select sparc_select[];
-
-/* Variables to record values the user passes.  */
-extern char *sparc_align_loops_string;
-extern char *sparc_align_jumps_string;
-extern char *sparc_align_funcs_string;
-/* Parsed values as a power of two.  */
-extern int sparc_align_loops;
-extern int sparc_align_jumps;
-extern int sparc_align_funcs;
-
-#define DEFAULT_SPARC_ALIGN_FUNCS \
-(sparc_cpu == PROCESSOR_ULTRASPARC ? 5 : 2)
-
-/* target machine storage layout */
-
-/* Define for cross-compilation to a sparc target with no TFmode from a host
-   with a different float format (e.g. VAX).  */
-#define REAL_ARITHMETIC
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.  */
-#define BITS_BIG_ENDIAN 1
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* Define this to set the endianness to use in libgcc2.c, which can
-   not depend on target_flags.  */
-#if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
-#define LIBGCC2_WORDS_BIG_ENDIAN 0
-#else
-#define LIBGCC2_WORDS_BIG_ENDIAN 1
-#endif
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD		(TARGET_ARCH64 ? 64 : 32)
-#define MAX_BITS_PER_WORD	64
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD		(TARGET_ARCH64 ? 8 : 4)
-#define MIN_UNITS_PER_WORD	4
-
-/* Now define the sizes of the C data types.  */
-
-#define SHORT_TYPE_SIZE		16
-#define INT_TYPE_SIZE		32
-#define LONG_TYPE_SIZE		(TARGET_ARCH64 ? 64 : 32)
-#define LONG_LONG_TYPE_SIZE	64
-#define FLOAT_TYPE_SIZE		32
-#define DOUBLE_TYPE_SIZE	64
-
-#if defined (SPARC_BI_ARCH)
-#define MAX_LONG_TYPE_SIZE	64
-#endif
-
-#if 0
-/* ??? This does not work in SunOS 4.x, so it is not enabled here.
-   Instead, it is enabled in sol2.h, because it does work under Solaris.  */
-/* Define for support of TFmode long double and REAL_ARITHMETIC.
-   Sparc ABI says that long double is 4 words.  */
-#define LONG_DOUBLE_TYPE_SIZE 128
-#endif
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
-
-/* A macro to update MODE and UNSIGNEDP when an object whose type
-   is TYPE and which has the specified mode and signedness is to be
-   stored in a register.  This macro is only called when TYPE is a
-   scalar type.  */
-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
-if (TARGET_ARCH64				\
-    && GET_MODE_CLASS (MODE) == MODE_INT	\
-    && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)	\
-{						\
-  (MODE) = DImode;				\
-}
-
-/* Define this macro if the promotion described by PROMOTE_MODE
-   should also be done for outgoing function arguments.  */
-/* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
-   for TARGET_ARCH32 this is ok.  Otherwise we'd need to add a runtime test
-   for this value.  */
-#define PROMOTE_FUNCTION_ARGS
-
-/* Define this macro if the promotion described by PROMOTE_MODE
-   should also be done for the return value of functions.
-   If this macro is defined, FUNCTION_VALUE must perform the same
-   promotions done by PROMOTE_MODE.  */
-/* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
-   for TARGET_ARCH32 this is ok.  Otherwise we'd need to add a runtime test
-   for this value.  */
-#define PROMOTE_FUNCTION_RETURN
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
-
-/* ALIGN FRAMES on double word boundaries */
-
-#define SPARC_STACK_ALIGN(LOC) \
-  (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY (1 << (sparc_align_funcs + 3))
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
-
-/* The best alignment to use in cases where we have a choice.  */
-#define FASTEST_ALIGNMENT 64
-
-/* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  ((TREE_CODE (EXP) == STRING_CST	\
-    && (ALIGN) < FASTEST_ALIGNMENT)	\
-   ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Things that must be doubleword aligned cannot go in the text section,
-   because the linker fails to align the text section enough!
-   Put them in the data section.  This macro is only used in this file.  */
-#define MAX_TEXT_ALIGN 32
-
-/* This forces all variables and constants to the data section when PIC.
-   This is because the SunOS 4 shared library scheme thinks everything in
-   text is a function, and patches the address to point to a loader stub.  */
-/* This is defined to zero for every system which doesn't use the a.out object
-   file format.  */
-#ifndef SUNOS4_SHARED_LIBRARIES
-#define SUNOS4_SHARED_LIBRARIES 0
-#endif
-
-/* This is defined differently for v9 in a cover file.  */
-#define SELECT_SECTION(T,RELOC)						\
-{									\
-  if (TREE_CODE (T) == VAR_DECL)					\
-    {									\
-      if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T)			\
-	  && DECL_INITIAL (T)						\
-	  && (DECL_INITIAL (T) == error_mark_node			\
-	      || TREE_CONSTANT (DECL_INITIAL (T)))			\
-	  && DECL_ALIGN (T) <= MAX_TEXT_ALIGN				\
-	  && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)))	\
-	text_section ();						\
-      else								\
-	data_section ();						\
-    }									\
-  else if (TREE_CODE (T) == CONSTRUCTOR)				\
-    {									\
-      if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))		\
-	data_section ();						\
-    }									\
-  else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c')			\
-    {									\
-      if ((TREE_CODE (T) == STRING_CST && flag_writable_strings)	\
-	  || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN		\
-	  || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)))	\
-	data_section ();						\
-      else								\
-	text_section ();						\
-    }									\
-}
-
-/* Use text section for a constant
-   unless we need more alignment than that offers.  */
-/* This is defined differently for v9 in a cover file.  */
-#define SELECT_RTX_SECTION(MODE, X)		\
-{						\
-  if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
-      && ! (flag_pic && (symbolic_operand (X) || SUNOS4_SHARED_LIBRARIES)))  \
-    text_section ();				\
-  else						\
-    data_section ();				\
-}
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   SPARC has 32 integer registers and 32 floating point registers.
-   64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
-   accessible.  We still account for them to simplify register computations
-   (eg: in CLASS_MAX_NREGS).  There are also 4 fp condition code registers, so
-   32+32+32+4 == 100.
-   Register 100 is used as the integer condition code register.  */
-
-#define FIRST_PSEUDO_REGISTER 101
-
-#define SPARC_FIRST_FP_REG     32
-/* Additional V9 fp regs.  */
-#define SPARC_FIRST_V9_FP_REG  64
-#define SPARC_LAST_V9_FP_REG   95
-/* V9 %fcc[0123].  V8 uses (figuratively) %fcc0.  */
-#define SPARC_FIRST_V9_FCC_REG 96
-#define SPARC_LAST_V9_FCC_REG  99
-/* V8 fcc reg.  */
-#define SPARC_FCC_REG 96
-/* Integer CC reg.  We don't distinguish %icc from %xcc.  */
-#define SPARC_ICC_REG 100
-
-/* Nonzero if REGNO is an fp reg.  */
-#define SPARC_FP_REG_P(REGNO) \
-((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
-
-/* Argument passing regs.  */
-#define SPARC_OUTGOING_INT_ARG_FIRST 8
-#define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
-#define SPARC_FP_ARG_FIRST           32
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   On non-v9 systems:
-   g1 is free to use as temporary.
-   g2-g4 are reserved for applications.  Gcc normally uses them as
-   temporaries, but this can be disabled via the -mno-app-regs option.
-   g5 through g7 are reserved for the operating system.
-
-   On v9 systems:
-   g1,g5 are free to use as temporaries, and are free to use between calls
-   if the call is to an external function via the PLT.
-   g4 is free to use as a temporary in the non-embedded case.
-   g4 is reserved in the embedded case.
-   g2-g3 are reserved for applications.  Gcc normally uses them as
-   temporaries, but this can be disabled via the -mno-app-regs option.
-   g6-g7 are reserved for the operating system (or application in
-   embedded case).
-   ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
-   currently be a fixed register until this pattern is rewritten.
-   Register 1 is also used when restoring call-preserved registers in large
-   stack frames.
-
-   Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
-   CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
-*/
-
-#define FIXED_REGISTERS  \
- {1, 0, 0, 0, 0, 0, 1, 1,	\
-  0, 0, 0, 0, 0, 0, 1, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 1, 1,	\
-				\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-				\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-				\
-  0, 0, 0, 0, 0}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-
-#define CALL_USED_REGISTERS  \
- {1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 1, 1,	\
-				\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-				\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-				\
-  1, 1, 1, 1, 1}
-
-/* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
-   they won't be allocated.  */
-
-#define CONDITIONAL_REGISTER_USAGE				\
-do								\
-  {								\
-    if (flag_pic)						\
-      {								\
-	fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;		\
-	call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;		\
-      }								\
-    if (TARGET_ARCH32)						\
-      {								\
-	fixed_regs[5] = 1;					\
-      }								\
-    if (TARGET_LIVE_G0)						\
-      fixed_regs[0] = 0;					\
-    if (! TARGET_V9)						\
-      {								\
-	int regno;						\
-	for (regno = SPARC_FIRST_V9_FP_REG;			\
-	     regno <= SPARC_LAST_V9_FP_REG;			\
-	     regno++)						\
-	  fixed_regs[regno] = 1;				\
-	/* %fcc0 is used by v8 and v9.  */			\
-	for (regno = SPARC_FIRST_V9_FCC_REG + 1;		\
-	     regno <= SPARC_LAST_V9_FCC_REG;			\
-	     regno++)						\
-	  fixed_regs[regno] = 1;				\
-      }								\
-    if (! TARGET_FPU)						\
-      {								\
-	int regno;						\
-	for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
-	  fixed_regs[regno] = 1;				\
-      }								\
-    /* Don't unfix g2-g4 if they were fixed with -ffixed-.  */	\
-    fixed_regs[2] |= ! TARGET_APP_REGS;				\
-    fixed_regs[3] |= ! TARGET_APP_REGS;				\
-    fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_CM_EMBMEDANY;	\
-    if (TARGET_FLAT)						\
-      {								\
-	/* Let the compiler believe the frame pointer is still	\
-	   %fp, but output it as %i7.  */			\
-	fixed_regs[31] = 1;					\
-	reg_names[FRAME_POINTER_REGNUM] = "%i7";		\
-	/* ??? This is a hack to disable leaf functions.  */	\
-	global_regs[7] = 1;					\
-      }								\
-    if (profile_block_flag)					\
-      {								\
-	/* %g1 and %g2 must be fixed, because BLOCK_PROFILER	\
-	    uses them.  */					\
-	fixed_regs[1] = 1;					\
-	fixed_regs[2] = 1;					\
-      }								\
-  }								\
-while (0)
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On SPARC, ordinary registers hold 32 bits worth;
-   this means both integer and floating point registers.
-   On v9, integer regs hold 64 bits worth; floating point regs hold
-   32 bits worth (this includes the new fp regs as even the odd ones are
-   included in the hard register count).  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE) \
-  (TARGET_ARCH64							\
-   ?  ((REGNO) < 32							\
-       ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD	\
-       : (GET_MODE_SIZE (MODE) + 3) / 4)				\
-   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* A subreg in 64 bit mode will have the wrong offset for a floating point
-   register.  The least significant part is at offset 1, compared to 0 for
-   integer registers.  This only applies when FMODE is a larger mode.
-   We also need to handle a special case of TF-->DF conversions.  */
-#define ALTER_HARD_SUBREG(TMODE, WORD, FMODE, REGNO)			\
-     (TARGET_ARCH64							\
-      && (REGNO) >= SPARC_FIRST_FP_REG					\
-      && (REGNO) <= SPARC_LAST_V9_FP_REG				\
-      && (TMODE) == SImode						\
-      && !((FMODE) == QImode || (FMODE) == HImode)			\
-      ? ((REGNO) + 1)							\
-      : ((TMODE) == DFmode && (FMODE) == TFmode)			\
-        ? ((REGNO) + ((WORD) * 2))					\
-        : ((REGNO) + (WORD)))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   See sparc.c for how we initialize this.  */
-extern int *hard_regno_mode_classes;
-extern int sparc_mode_class[];
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-  ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.
-
-   For V9: SFmode can't be combined with other float modes, because they can't
-   be allocated to the %d registers.  Also, DFmode won't fit in odd %f
-   registers, but SFmode will.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  ((MODE1) == (MODE2)						\
-   || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)		\
-       && (! TARGET_V9						\
-	   || (GET_MODE_CLASS (MODE1) != MODE_FLOAT		\
-	       || (MODE1 != SFmode && MODE2 != SFmode)))))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* SPARC pc isn't overloaded on a register that the compiler knows about.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 14
-
-/* Actual top-of-stack address is 92/176 greater than the contents of the
-   stack pointer register for !v9/v9.  That is:
-   - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
-     address, and 6*4 bytes for the 6 register parameters.
-   - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
-     parameter regs.  */
-#define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
-
-/* The stack bias (amount by which the hardware register is offset by).  */
-#define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
-
-/* Is stack biased? */
-#define STACK_BIAS SPARC_STACK_BIAS
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 30
-
-#if 0
-/* Register that is used for the return address for the flat model.  */
-#define RETURN_ADDR_REGNUM 15
-#endif
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.
-   Used in flow.c, global.c, and reload1.c.
-
-   Being a non-leaf function does not mean a frame pointer is needed in the
-   flat window model.  However, the debugger won't be able to backtrace through
-   us with out it.  */
-#define FRAME_POINTER_REQUIRED \
-  (TARGET_FLAT ? (current_function_calls_alloca || current_function_varargs \
-		  || !leaf_function_p ()) \
-   : ! (leaf_function_p () && only_leaf_regs_used ()))
-
-/* C statement to store the difference between the frame pointer
-   and the stack pointer values immediately after the function prologue.
-
-   Note, we always pretend that this is a leaf function because if
-   it's not, there's no point in trying to eliminate the
-   frame pointer.  If it is a leaf function, we guessed right!  */
-#define INITIAL_FRAME_POINTER_OFFSET(VAR) \
-  ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \
-	    : compute_frame_size (get_frame_size (), 1)))
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
-
-/* Register in which static-chain is passed to a function.  This must
-   not be a register used by the prologue.  */
-#define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
-
-/* Register which holds offset table for position-independent
-   data references.  */
-
-#define PIC_OFFSET_TABLE_REGNUM 23
-
-#define FINALIZE_PIC finalize_pic ()
-
-/* Pick a default value we can notice from override_options:
-   !v9: Default is on.
-   v9: Default is off.  */
-
-#define DEFAULT_PCC_STRUCT_RETURN -1
-
-/* Sparc ABI says that quad-precision floats and all structures are returned
-   in memory.
-   For v9: unions <= 32 bytes in size are returned in int regs,
-   structures up to 32 bytes are returned in int and fp regs.  */
-
-#define RETURN_IN_MEMORY(TYPE)				\
-(TARGET_ARCH32						\
- ? (TYPE_MODE (TYPE) == BLKmode				\
-    || TYPE_MODE (TYPE) == TFmode			\
-    || TYPE_MODE (TYPE) == TCmode)			\
- : (TYPE_MODE (TYPE) == BLKmode				\
-    && int_size_in_bytes (TYPE) > 32))
-
-/* Functions which return large structures get the address
-   to place the wanted value at offset 64 from the frame.
-   Must reserve 64 bytes for the in and local registers.
-   v9: Functions which return large structures get the address to place the
-   wanted value from an invisible first argument.  */
-/* Used only in other #defines in this file.  */
-#define STRUCT_VALUE_OFFSET 64
-
-#define STRUCT_VALUE \
-  (TARGET_ARCH64					\
-   ? 0							\
-   : gen_rtx_MEM (Pmode,				\
-		  gen_rtx_PLUS (Pmode, stack_pointer_rtx, \
-		       GEN_INT (STRUCT_VALUE_OFFSET))))
-#define STRUCT_VALUE_INCOMING \
-  (TARGET_ARCH64					\
-   ? 0							\
-   : gen_rtx_MEM (Pmode,				\
-		  gen_rtx_PLUS (Pmode, frame_pointer_rtx, \
-		       GEN_INT (STRUCT_VALUE_OFFSET))))
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-/* The SPARC has various kinds of registers: general, floating point,
-   and condition codes [well, it has others as well, but none that we
-   care directly about].
-
-   For v9 we must distinguish between the upper and lower floating point
-   registers because the upper ones can't hold SFmode values.
-   HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
-   satisfying a group need for a class will also satisfy a single need for
-   that class.  EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
-   regs.
-
-   It is important that one class contains all the general and all the standard
-   fp regs.  Otherwise find_reg() won't properly allocate int regs for moves,
-   because reg_class_record() will bias the selection in favor of fp regs,
-   because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
-   because FP_REGS > GENERAL_REGS.
-
-   It is also important that one class contain all the general and all the
-   fp regs.  Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
-   but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
-   allocate_reload_reg() to bypass it causing an abort because the compiler
-   thinks it doesn't have a spill reg when in fact it does.
-
-   v9 also has 4 floating point condition code registers.  Since we don't
-   have a class that is the union of FPCC_REGS with either of the others,
-   it is important that it appear first.  Otherwise the compiler will die
-   trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
-   constraints.
-
-   It is important that SPARC_ICC_REG have class NO_REGS.  Otherwise combine
-   may try to use it to hold an SImode value.  See register_operand.
-   ??? Should %fcc[0123] be handled similarly?
-*/
-
-enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
-		 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
-		 ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
-  { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS",	\
-     "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS",	\
-     "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS \
-  {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {0xffff, 0, 0, 0}, \
-   {-1, 0, 0, 0}, {0, -1, 0, 0}, {0, -1, -1, 0}, \
-   {-1, -1, 0, 0}, {-1, -1, -1, 0}, {-1, -1, -1, 0x1f}}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-extern enum reg_class sparc_regno_reg_class[];
-
-#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
-
-/* This is the order in which to allocate registers normally.  
-   
-   We put %f0/%f1 last among the float registers, so as to make it more
-   likely that a pseudo-register which dies in the float return register
-   will get allocated to the float return register, thus saving a move
-   instruction at the end of the function.  */
-
-#define REG_ALLOC_ORDER \
-{ 8, 9, 10, 11, 12, 13, 2, 3,		\
-  15, 16, 17, 18, 19, 20, 21, 22,	\
-  23, 24, 25, 26, 27, 28, 29, 31,	\
-  34, 35, 36, 37, 38, 39,		/* %f2-%f7 */   \
-  40, 41, 42, 43, 44, 45, 46, 47,	/* %f8-%f15 */  \
-  48, 49, 50, 51, 52, 53, 54, 55,	/* %f16-%f23 */ \
-  56, 57, 58, 59, 60, 61, 62, 63,	/* %f24-%f31 */ \
-  64, 65, 66, 67, 68, 69, 70, 71,	/* %f32-%f39 */ \
-  72, 73, 74, 75, 76, 77, 78, 79,	/* %f40-%f47 */ \
-  80, 81, 82, 83, 84, 85, 86, 87,	/* %f48-%f55 */ \
-  88, 89, 90, 91, 92, 93, 94, 95,	/* %f56-%f63 */ \
-  32, 33,				/* %f0,%f1 */   \
-  96, 97, 98, 99, 100,			/* %fcc0-3, %icc */ \
-  1, 4, 5, 6, 7, 0, 14, 30}
-
-/* This is the order in which to allocate registers for
-   leaf functions.  If all registers can fit in the "i" registers,
-   then we have the possibility of having a leaf function.  */
-
-#define REG_LEAF_ALLOC_ORDER \
-{ 2, 3, 24, 25, 26, 27, 28, 29,		\
-  15, 8, 9, 10, 11, 12, 13,		\
-  16, 17, 18, 19, 20, 21, 22, 23,	\
-  34, 35, 36, 37, 38, 39,		\
-  40, 41, 42, 43, 44, 45, 46, 47,	\
-  48, 49, 50, 51, 52, 53, 54, 55,	\
-  56, 57, 58, 59, 60, 61, 62, 63,	\
-  64, 65, 66, 67, 68, 69, 70, 71,	\
-  72, 73, 74, 75, 76, 77, 78, 79,	\
-  80, 81, 82, 83, 84, 85, 86, 87,	\
-  88, 89, 90, 91, 92, 93, 94, 95,	\
-  32, 33,				\
-  96, 97, 98, 99, 100,			\
-  1, 4, 5, 6, 7, 0, 14, 30, 31}
-
-#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
-
-/* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when
-   -mflat is used.  Function only_leaf_regs_used will return 0 if a global
-   register is used and is not permitted in a leaf function.  We make %g7
-   a global reg if -mflat and voila.  Since %g7 is a system register and is
-   fixed it won't be used by gcc anyway.  */
-
-#define LEAF_REGISTERS \
-{ 1, 1, 1, 1, 1, 1, 1, 0,	\
-  0, 0, 0, 0, 0, 0, 1, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 0,	\
-  1, 1, 1, 1, 1, 1, 0, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1, 1, 1, 1,	\
-  1, 1, 1, 1, 1}
-
-extern char leaf_reg_remap[];
-#define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Local macro to handle the two v9 classes of FP regs.  */
-#define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
-
-/* Get reg_class from a letter such as appears in the machine description.
-   In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
-   .md file for v8 and v9.
-   'd' and 'b' are used for single and double precision VIS operations,
-   if TARGET_VIS.
-   'h' is used for V8+ 64 bit global and out registers. */
-
-#define REG_CLASS_FROM_LETTER(C)		\
-(TARGET_V9					\
- ? ((C) == 'f' ? FP_REGS			\
-    : (C) == 'e' ? EXTRA_FP_REGS 		\
-    : (C) == 'c' ? FPCC_REGS			\
-    : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
-    : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
-    : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
-    : NO_REGS)					\
- : ((C) == 'f' ? FP_REGS			\
-    : (C) == 'e' ? FP_REGS			\
-    : (C) == 'c' ? FPCC_REGS			\
-    : NO_REGS))
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   `I' is used for the range of constants an insn can actually contain.
-   `J' is used for the range which is just zero (since that is R0).
-   `K' is used for constants which can be loaded with a single sethi insn.
-   `L' is used for the range of constants supported by the movcc insns.
-   `M' is used for the range of constants supported by the movrcc insns.  */
-
-#define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
-#define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
-#define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
-/* 10 and 11 bit immediates are only used for a few specific insns.
-   SMALL_INT is used throughout the port so we continue to use it.  */
-#define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
-/* 13 bit immediate, considering only the low 32 bits */
-#define SMALL_INT32(X) (SPARC_SIMM13_P ((int)INTVAL (X) & 0xffffffff))
-#define SPARC_SETHI_P(X) \
-(((unsigned HOST_WIDE_INT) (X) & ~(unsigned HOST_WIDE_INT) 0xfffffc00) == 0)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'I' ? SPARC_SIMM13_P (VALUE)			\
-   : (C) == 'J' ? (VALUE) == 0				\
-   : (C) == 'K' ? SPARC_SETHI_P (VALUE)			\
-   : (C) == 'L' ? SPARC_SIMM11_P (VALUE)		\
-   : (C) == 'M' ? SPARC_SIMM10_P (VALUE)		\
-   : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)	\
-  ((C) == 'G' ? fp_zero_operand (VALUE)			\
-   : (C) == 'H' ? arith_double_operand (VALUE, DImode)	\
-   : 0)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-/* - We can't load constants into FP registers.  We can't load any FP
-     constant if an 'E' constraint fails to match it.
-   - Try and reload integer constants (symbolic or otherwise) back into
-     registers directly, rather than having them dumped to memory.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)			\
-  (CONSTANT_P (X)					\
-   ? ((FP_REG_CLASS_P (CLASS)				\
-       || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT	\
-	   && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT	\
-	       || HOST_BITS_PER_INT != BITS_PER_WORD)))	\
-      ? NO_REGS						\
-      : (!FP_REG_CLASS_P (CLASS)			\
-         && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT)	\
-      ? GENERAL_REGS					\
-      : (CLASS))					\
-   : (CLASS))
-
-/* Return the register class of a scratch register needed to load IN into
-   a register of class CLASS in MODE.
-
-   We need a temporary when loading/storing a HImode/QImode value
-   between memory and the FPU registers.  This can happen when combine puts
-   a paradoxical subreg in a float/fix conversion insn.  */
-
-#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN)		\
-  ((FP_REG_CLASS_P (CLASS)					\
-    && ((MODE) == HImode || (MODE) == QImode)			\
-    && (GET_CODE (IN) == MEM					\
-        || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG)	\
-            && true_regnum (IN) == -1)))			\
-   ? GENERAL_REGS						\
-   : (((TARGET_CM_MEDANY					\
-        && symbolic_operand ((IN), (MODE)))			\
-       || (TARGET_CM_EMBMEDANY					\
-           && text_segment_operand ((IN), (MODE))))		\
-      && !flag_pic)						\
-     ? GENERAL_REGS						\
-     : NO_REGS)
-
-#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN)		\
-   ((FP_REG_CLASS_P (CLASS)					\
-     && ((MODE) == HImode || (MODE) == QImode)			\
-     && (GET_CODE (IN) == MEM					\
-         || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG)	\
-             && true_regnum (IN) == -1)))			\
-    ? GENERAL_REGS						\
-   : (((TARGET_CM_MEDANY					\
-        && symbolic_operand ((IN), (MODE)))			\
-       || (TARGET_CM_EMBMEDANY					\
-           && text_segment_operand ((IN), (MODE))))		\
-      && !flag_pic)						\
-     ? GENERAL_REGS						\
-     : NO_REGS)
-
-/* On SPARC it is not possible to directly move data between 
-   GENERAL_REGS and FP_REGS.  */
-#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
-  (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
-
-/* Return the stack location to use for secondary memory needed reloads.
-   We want to use the reserved location just below the frame pointer.
-   However, we must ensure that there is a frame, so use assign_stack_local
-   if the frame size is zero.  */
-#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
-  (get_frame_size () == 0						\
-   ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0)			\
-   : gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, frame_pointer_rtx,	\
-				  GEN_INT (STARTING_FRAME_OFFSET))))
-
-/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
-   because the movsi and movsf patterns don't handle r/f moves.
-   For v8 we copy the default definition.  */
-#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
-  (TARGET_ARCH64						\
-   ? (GET_MODE_BITSIZE (MODE) < 32				\
-      ? mode_for_size (32, GET_MODE_CLASS (MODE), 0)		\
-      : MODE)							\
-   : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD			\
-      ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0)	\
-      : MODE))
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-/* On SPARC, this is the size of MODE in words.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
-  (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
-   : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define the number of register that can hold parameters.
-   This macro is only used in other macro definitions below and in sparc.c.
-   MODE is the mode of the argument.
-   !v9: All args are passed in %o0-%o5.
-   v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
-   See the description in sparc.c.  */
-#define NPARM_REGS(MODE) \
-(TARGET_ARCH64 \
- ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
- : 6)
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-/* This allows space for one TFmode floating point value.  */
-#define STARTING_FRAME_OFFSET \
-  (TARGET_ARCH64 ? (SPARC_STACK_BIAS - 16) \
-   : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On SPARC, don't define this because there are no push insns.  */
-/*  #define PUSH_ROUNDING(BYTES) */
-
-/* Offset of first parameter from the argument pointer register value.
-   !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
-   even if this function isn't going to use it.
-   v9: This is 128 for the ins and locals.  */
-#define FIRST_PARM_OFFSET(FNDECL) \
-  (TARGET_ARCH64 ? (SPARC_STACK_BIAS + 16 * UNITS_PER_WORD) \
-   : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD))
-
-/* Offset from the argument pointer register value to the CFA.  */
-
-#define ARG_POINTER_CFA_OFFSET  SPARC_STACK_BIAS
-
-/* When a parameter is passed in a register, stack space is still
-   allocated for it.
-   !v9: All 6 possible integer registers have backing store allocated.
-   v9: Only space for the arguments passed is allocated. */
-/* ??? Ideally, we'd use zero here (as the minimum), but zero has special
-   meaning to the backend.  Further, we need to be able to detect if a
-   varargs/unprototyped function is called, as they may want to spill more
-   registers than we've provided space.  Ugly, ugly.  So for now we retain
-   all 6 slots even for v9.  */
-#define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
-
-/* Keep the stack pointer constant throughout the function.
-   This is both an optimization and a necessity: longjmp
-   doesn't behave itself when the stack pointer moves within
-   the function!  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Some subroutine macros specific to this machine.
-   When !TARGET_FPU, put float return values in the general registers,
-   since we don't have any fp registers.  */
-#define BASE_RETURN_VALUE_REG(MODE)					\
-  (TARGET_ARCH64							\
-   ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8)			\
-   : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
-
-#define BASE_OUTGOING_VALUE_REG(MODE)				\
-  (TARGET_ARCH64						\
-   ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32			\
-      : TARGET_FLAT ? 8 : 24)					\
-   : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32	\
-      : (TARGET_FLAT ? 8 : 24)))
-
-#define BASE_PASSING_ARG_REG(MODE)				\
-  (TARGET_ARCH64						\
-   ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8)		\
-   : 8)
-
-/* ??? FIXME -- seems wrong for v9 structure passing... */
-#define BASE_INCOMING_ARG_REG(MODE)				\
-  (TARGET_ARCH64						\
-   ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32			\
-      : TARGET_FLAT ? 8 : 24)					\
-   : (TARGET_FLAT ? 8 : 24))
-
-/* Define this macro if the target machine has "register windows".  This
-   C expression returns the register number as seen by the called function
-   corresponding to register number OUT as seen by the calling function.
-   Return OUT if register number OUT is not an outbound register.  */
-
-#define INCOMING_REGNO(OUT) \
- ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
-
-/* Define this macro if the target machine has "register windows".  This
-   C expression returns the register number as seen by the calling function
-   corresponding to register number IN as seen by the called function.
-   Return IN if register number IN is not an inbound register.  */
-
-#define OUTGOING_REGNO(IN) \
- ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-/* On SPARC the value is found in the first "output" register.  */
-
-extern struct rtx_def *function_value ();
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-  function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
-
-/* But the called function leaves it in the first "input" register.  */
-
-#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
-  function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE) \
-  function_value (NULL_TREE, (MODE), 1)
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.
-   On SPARC, the first "output" reg is used for integer values,
-   and the first floating point register is used for floating point values.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
-
-/* Define the size of space to allocate for the return value of an
-   untyped_call.  */
-
-#define APPLY_RESULT_SIZE 16
-
-/* 1 if N is a possible register number for function argument passing.
-   On SPARC, these are the "output" registers.  v9 also uses %f0-%f31.  */
-
-#define FUNCTION_ARG_REGNO_P(N) \
-(TARGET_ARCH64 \
- ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
- : ((N) >= 8 && (N) <= 13))
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On SPARC (!v9), this is a single integer, which is a number of words
-   of arguments scanned so far (including the invisible argument,
-   if any, which holds the structure-value-address).
-   Thus 7 or more means all following args should go on the stack.
-
-   For v9, we also need to know whether a prototype is present.  */
-
-struct sparc_args {
-  int words;       /* number of words passed so far */
-  int prototype_p; /* non-zero if a prototype is present */
-  int libcall_p;   /* non-zero if a library call */
-};
-#define CUMULATIVE_ARGS struct sparc_args
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-
-extern void init_cumulative_args ();
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
-init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT));
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   TYPE is null for libcalls where that information may not be available.  */
-
-extern void function_arg_advance ();
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
-function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-extern struct rtx_def *function_arg ();
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
-
-/* Define where a function finds its arguments.
-   This is different from FUNCTION_ARG because of register windows.  */
-
-#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
-function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-extern int function_arg_partial_nregs ();
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
-
-/* A C expression that indicates when an argument must be passed by reference.
-   If nonzero for an argument, a copy of that argument is made in memory and a
-   pointer to the argument is passed instead of the argument itself.
-   The pointer is passed in whatever way is appropriate for passing a pointer
-   to that type.  */
-
-extern int function_arg_pass_by_reference ();
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
-function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
-
-/* If defined, a C expression which determines whether, and in which direction,
-   to pad out an argument with extra space.  The value should be of type
-   `enum direction': either `upward' to pad above the argument,
-   `downward' to pad below, or `none' to inhibit padding.  */
-
-#define FUNCTION_ARG_PADDING(MODE, TYPE) \
-function_arg_padding ((MODE), (TYPE))
-
-/* If defined, a C expression that gives the alignment boundary, in bits,
-   of an argument with the specified mode and type.  If it is not defined,
-   PARM_BOUNDARY is used for all arguments.
-   For sparc64, objects requiring 16 byte alignment are passed that way.  */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
-((TARGET_ARCH64					\
-  && (GET_MODE_ALIGNMENT (MODE) == 128		\
-      || ((TYPE) && TYPE_ALIGN (TYPE) == 128)))	\
- ? 128 : PARM_BOUNDARY)
-
-/* Define the information needed to generate branch and scc insns.  This is
-   stored from the compare operation.  Note that we can't use "rtx" here
-   since it hasn't been defined!  */
-
-extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
-
-/* Define the function that build the compare insn for scc and bcc.  */
-
-extern struct rtx_def *gen_compare_reg ();
-
-/* This function handles all v9 scc insns */
-
-extern int gen_v9_scc ();
-
-/* Generate the special assembly code needed to tell the assembler whatever
-   it might need to know about the return value of a function.
-
-   For Sparc assemblers, we need to output a .proc pseudo-op which conveys
-   information to the assembler relating to peephole optimization (done in
-   the assembler).  */
-
-#define ASM_DECLARE_RESULT(FILE, RESULT) \
-  fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
-
-/* Output the label for a function definition.  */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-do {									\
-  ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));			\
-  ASM_OUTPUT_LABEL (FILE, NAME);					\
-} while (0)
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-/* On SPARC, move-double insns between fpu and cpu need an 8-byte block
-   of memory.  If any fpu reg is used in the function, we allocate
-   such a block here, at the bottom of the frame, just in case it's needed.
-
-   If this function is a leaf procedure, then we may choose not
-   to do a "save" insn.  The decision about whether or not
-   to do this is made in regclass.c.  */
-
-extern int leaf_function;
-#define FUNCTION_PROLOGUE(FILE, SIZE) \
-  (TARGET_FLAT ? sparc_flat_output_function_prologue (FILE, (int)SIZE) \
-   : output_function_prologue (FILE, (int)SIZE, leaf_function))
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.
-
-   32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered
-   during profiling so we need to save/restore it around the call to mcount.
-   We're guaranteed that a save has just been done, and we use the space
-   allocated for intreg/fpreg value passing.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  			\
-  do {								\
-    char buf[20];						\
-    ASM_GENERATE_INTERNAL_LABEL (buf, "LP", (LABELNO));		\
-    if (! TARGET_ARCH64)					\
-      fputs ("\tst %g2,[%fp-4]\n", FILE);			\
-    fputs ("\tsethi %hi(", FILE);				\
-    assemble_name (FILE, buf);					\
-    fputs ("),%o0\n", FILE);					\
-    fputs ("\tcall mcount\n\tadd %o0,%lo(", FILE);		\
-    assemble_name (FILE, buf);					\
-    fputs ("),%o0\n", FILE);					\
-    if (! TARGET_ARCH64)					\
-      fputs ("\tld [%fp-4],%g2\n", FILE);			\
-  } while (0)
-
-/* There are three profiling modes for basic blocks available.
-   The modes are selected at compile time by using the options
-   -a or -ax of the gnu compiler.
-   The variable `profile_block_flag' will be set according to the
-   selected option.
-
-   profile_block_flag == 0, no option used:
-
-      No profiling done.
-
-   profile_block_flag == 1, -a option used.
-
-      Count frequency of execution of every basic block.
-
-   profile_block_flag == 2, -ax option used.
-
-      Generate code to allow several different profiling modes at run time. 
-      Available modes are:
-             Produce a trace of all basic blocks.
-             Count frequency of jump instructions executed.
-      In every mode it is possible to start profiling upon entering
-      certain functions and to disable profiling of some other functions.
-
-    The result of basic-block profiling will be written to a file `bb.out'.
-    If the -ax option is used parameters for the profiling will be read
-    from file `bb.in'.
-
-*/
-
-/* The following macro shall output assembler code to FILE
-   to initialize basic-block profiling.
-
-   If profile_block_flag == 2
-
-	Output code to call the subroutine `__bb_init_trace_func'
-	and pass two parameters to it. The first parameter is
-	the address of a block allocated in the object module.
-	The second parameter is the number of the first basic block
-	of the function.
-
-	The name of the block is a local symbol made with this statement:
-	
-	    ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
-
-	Of course, since you are writing the definition of
-	`ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
-	can take a short cut in the definition of this macro and use the
-	name that you know will result.
-
-	The number of the first basic block of the function is
-	passed to the macro in BLOCK_OR_LABEL.
-
-	If described in a virtual assembler language the code to be
-	output looks like:
-
-		parameter1 <- LPBX0
-		parameter2 <- BLOCK_OR_LABEL
-		call __bb_init_trace_func
-
-    else if profile_block_flag != 0
-
-	Output code to call the subroutine `__bb_init_func'
-	and pass one single parameter to it, which is the same
-	as the first parameter to `__bb_init_trace_func'.
-
-	The first word of this parameter is a flag which will be nonzero if
-	the object module has already been initialized.  So test this word
-	first, and do not call `__bb_init_func' if the flag is nonzero.
-	Note: When profile_block_flag == 2 the test need not be done
-	but `__bb_init_trace_func' *must* be called.
-
-	BLOCK_OR_LABEL may be used to generate a label number as a
-	branch destination in case `__bb_init_func' will not be called.
-
-	If described in a virtual assembler language the code to be
-	output looks like:
-
-		cmp (LPBX0),0
-		jne local_label
-		parameter1 <- LPBX0
-		call __bb_init_func
-local_label:
-
-*/
-
-#define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL)	\
-do							\
-  {							\
-    int bol = (BLOCK_OR_LABEL);				\
-    switch (profile_block_flag)				\
-      {							\
-      case 2:						\
-        fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%o0,%%lo(LPBX0),%%o0\n\tsethi %%hi(%d),%%o1\n\tcall ___bb_init_trace_func\n\tor %%o1,%%lo(%d),%%o1\n",\
-                 bol, bol);				\
-        break;						\
-      default:						\
-        fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n",\
-                 bol, bol);				\
-        break;						\
-      }							\
-  }							\
-while (0)
-
-/* The following macro shall output assembler code to FILE
-   to increment a counter associated with basic block number BLOCKNO.
-
-   If profile_block_flag == 2
-
-	Output code to initialize the global structure `__bb' and
-	call the function `__bb_trace_func' which will increment the
-	counter.
-
-	`__bb' consists of two words. In the first word the number
-	of the basic block has to be stored. In the second word
-	the address of a block allocated in the object module 
-	has to be stored.
-
-	The basic block number is given by BLOCKNO.
-
-	The address of the block is given by the label created with 
-
-	    ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
-
-	by FUNCTION_BLOCK_PROFILER.
-
-	Of course, since you are writing the definition of
-	`ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
-	can take a short cut in the definition of this macro and use the
-	name that you know will result.
-
-	If described in a virtual assembler language the code to be
-	output looks like:
-
-		move BLOCKNO -> (__bb)
-		move LPBX0 -> (__bb+4)
-		call __bb_trace_func
-
-	Note that function `__bb_trace_func' must not change the
-	machine state, especially the flag register. To grant
-	this, you must output code to save and restore registers
-	either in this macro or in the macros MACHINE_STATE_SAVE
-	and MACHINE_STATE_RESTORE. The last two macros will be
-	used in the function `__bb_trace_func', so you must make
-	sure that the function prologue does not change any 
-	register prior to saving it with MACHINE_STATE_SAVE.
-
-   else if profile_block_flag != 0
-
-	Output code to increment the counter directly.
-	Basic blocks are numbered separately from zero within each
-	compiled object module. The count associated with block number
-	BLOCKNO is at index BLOCKNO in an array of words; the name of 
-	this array is a local symbol made with this statement:
-
-	    ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
-
-	Of course, since you are writing the definition of
-	`ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
-	can take a short cut in the definition of this macro and use the
-	name that you know will result. 
-
-	If described in a virtual assembler language, the code to be
-	output looks like:
-
-		inc (LPBX2+4*BLOCKNO)
-
-*/
-
-#define BLOCK_PROFILER(FILE, BLOCKNO)	\
-do					\
-  {					\
-    int blockn = (BLOCKNO);		\
-    switch (profile_block_flag)		\
-      {					\
-      case 2:				\
-        fprintf (FILE, "\tsethi %%hi(___bb),%%g1\n\tsethi %%hi(%d),%%g2\n\tor %%g2,%%lo(%d),%%g2\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tsethi %%hi(LPBX0),%%g2\n\tor %%g2,%%lo(LPBX0),%%g2\n\tadd 4,%%g1,%%g1\n\tst %%g2,[%%lo(___bb)+%%g1]\n\tmov %%o7,%%g2\n\tcall ___bb_trace_func\n\tnop\n\tmov %%g2,%%o7\n",\
-                 blockn, blockn); \
-        break;				\
-      default:				\
-        fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
-\tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
-                 4 * blockn, 4 * blockn, 4 * blockn); \
-        break;				\
-      }					\
-  }					\
-while(0)
-
-/* The following macro shall output assembler code to FILE
-   to indicate a return from function during basic-block profiling.
-
-   If profiling_block_flag == 2:
-
-	Output assembler code to call function `__bb_trace_ret'.
-
-	Note that function `__bb_trace_ret' must not change the
-	machine state, especially the flag register. To grant
-	this, you must output code to save and restore registers
-	either in this macro or in the macros MACHINE_STATE_SAVE_RET
-	and MACHINE_STATE_RESTORE_RET. The last two macros will be
-	used in the function `__bb_trace_ret', so you must make
-	sure that the function prologue does not change any 
-	register prior to saving it with MACHINE_STATE_SAVE_RET.
-
-   else if profiling_block_flag != 0:
-
-	The macro will not be used, so it need not distinguish
-	these cases.
-*/
-
-#define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
-  fprintf (FILE, "\tcall ___bb_trace_ret\n\tnop\n" );
-
-/* The function `__bb_trace_func' is called in every basic block
-   and is not allowed to change the machine state. Saving (restoring)
-   the state can either be done in the BLOCK_PROFILER macro,
-   before calling function (rsp. after returning from function)
-   `__bb_trace_func', or it can be done inside the function by
-   defining the macros:
-
-	MACHINE_STATE_SAVE(ID)
-	MACHINE_STATE_RESTORE(ID)
-
-   In the latter case care must be taken, that the prologue code
-   of function `__bb_trace_func' does not already change the
-   state prior to saving it with MACHINE_STATE_SAVE.
-
-   The parameter `ID' is a string identifying a unique macro use.
-
-   On sparc it is sufficient to save the psw register to memory.
-   Unfortunately the psw register can be read in supervisor mode only,
-   so we read only the condition codes by using branch instructions
-   and hope that this is enough. */
-
-#define MACHINE_STATE_SAVE(ID)			\
-  int ms_flags, ms_saveret;			\
-  asm volatile(					\
-	"mov %%g0,%0\n\
-	be,a LFLGNZ"ID"\n\
-	or %0,4,%0\n\
-LFLGNZ"ID":\n\
-	bcs,a LFLGNC"ID"\n\
-	or %0,1,%0\n\
-LFLGNC"ID":\n\
-	bvs,a LFLGNV"ID"\n\
-	or %0,2,%0\n\
-LFLGNV"ID":\n\
-	bneg,a LFLGNN"ID"\n\
-	or %0,8,%0\n\
-LFLGNN"ID":\n\
-	mov %%g2,%1"				\
-	: "=r"(ms_flags), "=r"(ms_saveret));
-
-/* On sparc MACHINE_STATE_RESTORE restores the psw register from memory.
-   The psw register can be written in supervisor mode only,
-   which is true even for simple condition codes.
-   We use some combination of instructions to produce the
-   proper condition codes, but some flag combinations can not
-   be generated in this way. If this happens an unimplemented
-   instruction will be executed to abort the program. */
-
-#define MACHINE_STATE_RESTORE(ID)				\
-{ extern char flgtab[] __asm__("LFLGTAB"ID);			\
-  int scratch;							\
-  asm volatile (						\
-	"jmpl %2+%1,%%g0\n\
-    ! Do part of VC in the delay slot here, as it needs 3 insns.\n\
-	 addcc 2,%3,%%g0\n\
-LFLGTAB" ID ":\n\
-    ! 0\n\
-	ba LFLGRET"ID"\n\
-	 orcc 1,%%g0,%%g0\n\
-    ! C\n\
-	ba LFLGRET"ID"\n\
-	 addcc 2,%3,%%g0\n\
-    ! V\n\
-	unimp\n\
-	nop\n\
-    ! VC\n\
-	ba LFLGRET"ID"\n\
-	 addxcc %4,%4,%0\n\
-    ! Z\n\
-	ba LFLGRET"ID"\n\
-	 subcc %%g0,%%g0,%%g0\n\
-    ! ZC\n\
-	ba LFLGRET"ID"\n\
-	 addcc 1,%3,%0\n\
-    ! ZVC\n\
-	ba LFLGRET"ID"\n\
-	 addcc %4,%4,%0\n\
-    ! N\n\
-	ba LFLGRET"ID"\n\
-	 orcc %%g0,-1,%%g0\n\
-    ! NC\n\
-	ba LFLGRET"ID"\n\
-	 addcc %%g0,%3,%%g0\n\
-    ! NV\n\
-	unimp\n\
-	nop\n\
-    ! NVC\n\
-	unimp\n\
-	nop\n\
-    ! NZ\n\
-	unimp\n\
-	nop\n\
-    ! NZC\n\
-	unimp\n\
-	nop\n\
-    ! NZV\n\
-	unimp\n\
-	nop\n\
-    ! NZVC\n\
-	unimp\n\
-	nop\n\
-LFLGRET"ID":\n\
-	mov %5,%%g2"						\
-	: "=r"(scratch)						\
-	: "r"(ms_flags*8), "r"(flgtab), "r"(-1),		\
-	  "r"(0x80000000), "r"(ms_saveret)			\
-	: "cc", "%g2"); }
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-extern int current_function_calls_alloca;
-extern int current_function_outgoing_args_size;
-
-#define EXIT_IGNORE_STACK	\
- (get_frame_size () != 0	\
-  || current_function_calls_alloca || current_function_outgoing_args_size)
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-/* This declaration is needed due to traditional/ANSI
-   incompatibilities which cannot be #ifdefed away
-   because they occur inside of macros.  Sigh.  */
-extern union tree_node *current_function_decl;
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-  (TARGET_FLAT ? sparc_flat_output_function_epilogue (FILE, (int)SIZE) \
-   : output_function_epilogue (FILE, (int)SIZE, leaf_function))
-
-#define DELAY_SLOTS_FOR_EPILOGUE \
-  (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
-#define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
-  (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
-   : eligible_for_epilogue_delay (trial, slots_filled))
-
-/* Define registers used by the epilogue and return instruction.  */
-#define EPILOGUE_USES(REGNO) \
-  (!TARGET_FLAT && REGNO == 31)
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
-
-#define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-void sparc_initialize_trampoline ();
-void sparc64_initialize_trampoline ();
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-    if (TARGET_ARCH64)						\
-      sparc64_initialize_trampoline (TRAMP, FNADDR, CXT);	\
-    else							\
-      sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
-
-/* Generate necessary RTL for __builtin_saveregs().
-   ARGLIST is the argument list; see expr.c.  */
-
-extern struct rtx_def *sparc_builtin_saveregs ();
-#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
-
-/* Define this macro if the location where a function argument is passed
-   depends on whether or not it is a named argument.
-
-   This macro controls how the NAMED argument to FUNCTION_ARG
-   is set for varargs and stdarg functions.  With this macro defined,
-   the NAMED argument is always true for named arguments, and false for
-   unnamed arguments.  If this is not defined, but SETUP_INCOMING_VARARGS
-   is defined, then all arguments are treated as named.  Otherwise, all named
-   arguments except the last are treated as named.
-   For the v9 we want NAMED to mean what it says it means.  */
-
-#define STRICT_ARGUMENT_NAMING TARGET_V9
-
-/* Generate RTL to flush the register windows so as to make arbitrary frames
-   available.  */
-#define SETUP_FRAME_ADDRESSES()		\
-  emit_insn (gen_flush_register_windows ())
-
-/* Given an rtx for the address of a frame,
-   return an rtx for the address of the word in the frame
-   that holds the dynamic chain--the previous frame's address.
-   ??? -mflat support? */
-#define DYNAMIC_CHAIN_ADDRESS(frame) \
-  gen_rtx_PLUS (Pmode, frame, GEN_INT (14 * UNITS_PER_WORD))
-
-/* The return address isn't on the stack, it is in a register, so we can't
-   access it from the current frame pointer.  We can access it from the
-   previous frame pointer though by reading a value from the register window
-   save area.  */
-#define RETURN_ADDR_IN_PREVIOUS_FRAME
-
-/* This is the offset of the return address to the true next instruction to be
-   executed for the current function. */
-#define RETURN_ADDR_OFFSET \
-  (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
-
-/* The current return address is in %i7.  The return address of anything
-   farther back is in the register window save area at [%fp+60].  */
-/* ??? This ignores the fact that the actual return address is +8 for normal
-   returns, and +12 for structure returns.  */
-#define RETURN_ADDR_RTX(count, frame)		\
-  ((count == -1)				\
-   ? gen_rtx_REG (Pmode, 31)			\
-   : gen_rtx_MEM (Pmode,			\
-	      memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD))))
-
-/* Before the prologue, the return address is %o7 + 8.  OK, sometimes it's
-   +12, but always using +8 is close enough for frame unwind purposes.
-   Actually, just using %o7 is close enough for unwinding, but %o7+8
-   is something you can return to.  */
-#define INCOMING_RETURN_ADDR_RTX \
-  gen_rtx_PLUS (word_mode, gen_rtx_REG (word_mode, 15), GEN_INT (8))
-
-/* The offset from the incoming value of %sp to the top of the stack frame
-   for the current function.  On sparc64, we have to account for the stack
-   bias if present.  */
-#define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
-
-#define DOESNT_NEED_UNWINDER (! TARGET_FLAT)
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32)
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32)
-#define REGNO_OK_FOR_FP_P(REGNO) \
-  (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
-   || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
-#define REGNO_OK_FOR_CCFP_P(REGNO) \
- (TARGET_V9 \
-  && (((unsigned) (REGNO) - 96 < (unsigned)4) \
-      || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
-
-/* Now macros that check whether X is a register and also,
-   strictly, whether it is in a specified class.
-
-   These macros are specific to the SPARC, and may be used only
-   in code for printing assembler insns and in conditions for
-   define_optimization.  */
-
-/* 1 if X is an fp register.  */
-
-#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
-
-/* Is X, a REG, an in or global register?  i.e. is regno 0..7 or 24..31 */
-#define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address.
-   When PIC, we do not accept an address that would require a scratch reg
-   to load into a register.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH			\
-   || (GET_CODE (X) == CONST						\
-       && ! (flag_pic && pic_address_needs_scratch (X))))
-
-/* Define this, so that when PIC, reload won't try to reload invalid
-   addresses which require two reload registers.  */
-
-#define LEGITIMATE_PIC_OPERAND_P(X)  (! pic_address_needs_scratch (X))
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   Anything can be made to work except floating point constants.
-   If TARGET_VIS, 0.0 can be made to work as well.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 					\
-  (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || 		\
-   (TARGET_VIS && (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode) &&	\
-    fp_zero_operand (X)))
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-/* Optional extra constraints for this machine.
-
-   'T' handles memory addresses where the alignment is known to
-       be at least 8 bytes.
-
-   `U' handles all pseudo registers or a hard even numbered
-       integer register, needed for ldd/std instructions.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) \
-  (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-  (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
-
-/* 'T', 'U' are for aligned memory loads which aren't needed for v9.  */
-
-#define EXTRA_CONSTRAINT(OP, C)				\
-   ((! TARGET_ARCH64 && (C) == 'T')			\
-    ? (mem_min_alignment (OP, 8))			\
-    : ((! TARGET_ARCH64 && (C) == 'U')			\
-       ? (register_ok_for_ldd (OP))			\
-       : 0))
- 
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#define EXTRA_CONSTRAINT(OP, C)				\
-   ((! TARGET_ARCH64 && (C) == 'T')			\
-    ? mem_min_alignment (OP, 8) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
-    : ((! TARGET_ARCH64 && (C) == 'U')			\
-       ? (GET_CODE (OP) == REG				\
-          && (REGNO (OP) < FIRST_PSEUDO_REGISTER	\
-	      || reg_renumber[REGNO (OP)] >= 0)		\
-          && register_ok_for_ldd (OP))			\
-       : 0))
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
-   ordinarily.  This changes a bit when generating PIC.
-
-   If you change this, execute "rm explow.o recog.o reload.o".  */
-
-#define RTX_OK_FOR_BASE_P(X)						\
-  ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
-  || (GET_CODE (X) == SUBREG						\
-      && GET_CODE (SUBREG_REG (X)) == REG				\
-      && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
-
-#define RTX_OK_FOR_INDEX_P(X)						\
-  ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))			\
-  || (GET_CODE (X) == SUBREG						\
-      && GET_CODE (SUBREG_REG (X)) == REG				\
-      && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
-
-#define RTX_OK_FOR_OFFSET_P(X)						\
-  (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)		\
-{ if (RTX_OK_FOR_BASE_P (X))				\
-    goto ADDR;						\
-  else if (GET_CODE (X) == PLUS)			\
-    {							\
-      register rtx op0 = XEXP (X, 0);			\
-      register rtx op1 = XEXP (X, 1);			\
-      if (flag_pic && op0 == pic_offset_table_rtx)	\
-	{						\
-	  if (RTX_OK_FOR_BASE_P (op1))			\
-	    goto ADDR;					\
-	  else if (flag_pic == 1			\
-		   && GET_CODE (op1) != REG		\
-		   && GET_CODE (op1) != LO_SUM		\
-		   && GET_CODE (op1) != MEM		\
-		   && (GET_CODE (op1) != CONST_INT	\
-		       || SMALL_INT (op1)))		\
-	    goto ADDR;					\
-	}						\
-      else if (RTX_OK_FOR_BASE_P (op0))			\
-	{						\
-	  if (RTX_OK_FOR_INDEX_P (op1)			\
- 	      /* We prohibit REG + REG for TFmode when	\
-		 there are no instructions which accept	\
-		 REG+REG instructions.  We make this	\
-		 because REG+REG is not offsetable	\
-		 address and we could get the situation	\
-		 in reload when source and destination	\
-		 of a movtf pattern are MEMs with	\
-		 REG+REG address and only one of them	\
-		 gets converted to an offsetable	\
-		 address. */				\
- 	      && (MODE != TFmode			\
-		  || (TARGET_FPU && TARGET_ARCH64	\
-		      && TARGET_V9 && TARGET_HARD_QUAD))\
-	      || RTX_OK_FOR_OFFSET_P (op1))		\
-	    goto ADDR;					\
-	}						\
-      else if (RTX_OK_FOR_BASE_P (op1))			\
-	{						\
-	  if (RTX_OK_FOR_INDEX_P (op0)			\
- 	      /* See the previous comment. */		\
- 	      && (MODE != TFmode			\
-		  || (TARGET_FPU && TARGET_ARCH64	\
-		      && TARGET_V9 && TARGET_HARD_QUAD))\
-	      || RTX_OK_FOR_OFFSET_P (op0))		\
-	    goto ADDR;					\
-	}						\
-    }							\
-  else if (GET_CODE (X) == LO_SUM)			\
-    {							\
-      register rtx op0 = XEXP (X, 0);			\
-      register rtx op1 = XEXP (X, 1);			\
-      if (RTX_OK_FOR_BASE_P (op0)			\
-	  && CONSTANT_P (op1)				\
-	  /* We can't allow TFmode, because an offset	\
-	     greater than or equal to the alignment (8)	\
-	     may cause the LO_SUM to overflow if !v9. */\
-	  && (MODE != TFmode || TARGET_V9))		\
-	goto ADDR;					\
-    }							\
-  else if (GET_CODE (X) == CONST_INT && SMALL_INT (X))	\
-    goto ADDR;						\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.  */
-
-/* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG.  */
-extern struct rtx_def *legitimize_pic_address ();
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)	\
-{ rtx sparc_x = (X);						\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT)	\
-    (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1),			\
-		   force_operand (XEXP (X, 0), NULL_RTX));	\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT)	\
-    (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0),			\
-		   force_operand (XEXP (X, 1), NULL_RTX));	\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS)	\
-    (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
-		   XEXP (X, 1));				\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS)	\
-    (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0),			\
-		   force_operand (XEXP (X, 1), NULL_RTX));	\
-  if (sparc_x != (X) && memory_address_p (MODE, X))		\
-    goto WIN;							\
-  if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0);	\
-  else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1)))	\
-    (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0),			\
-		   copy_to_mode_reg (Pmode, XEXP (X, 1)));	\
-  else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0)))	\
-    (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1),			\
-		   copy_to_mode_reg (Pmode, XEXP (X, 0)));	\
-  else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST	\
-	   || GET_CODE (X) == LABEL_REF)			\
-    (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); 		\
-  if (memory_address_p (MODE, X))				\
-    goto WIN; }
-
-/* Try a machine-dependent way of reloading an illegitimate address
-   operand.  If we find one, push the reload and jump to WIN.  This
-   macro is used in only one place: `find_reloads_address' in reload.c.
-
-   For Sparc 32, we wish to handle addresses by splitting them into
-   HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. 
-   This cuts the number of extra insns by one.  */
-   
-#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN)     \
-do {                                                                    \
-  /* Decompose SImode constants into hi+lo_sum.  We do have to 		\
-     rerecognize what we produce, so be careful.  */			\
-  if (CONSTANT_P (X)							\
-      && (MODE != TFmode || TARGET_V9)					\
-      && GET_MODE (X) == SImode						\
-      && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH)		\
-    {									\
-      X = gen_rtx_LO_SUM (GET_MODE (X),					\
-			  gen_rtx_HIGH (GET_MODE (X), X), X);		\
-      push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR,	\
-                   BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0,	\
-                   OPNUM, TYPE);					\
-      goto WIN;								\
-    }									\
-  /* ??? 64-bit reloads.  */						\
-} while (0)
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the SPARC this is never true.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-/* If we are referencing a function make the SYMBOL_REF special.
-   In the Embedded Medium/Anywhere code model, %g4 points to the data segment
-   so we must not add it to function addresses.  */
-
-#define ENCODE_SECTION_INFO(DECL) \
-  do {							\
-    if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
-      SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;	\
-  } while (0)
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-/* If we ever implement any of the full models (such as CM_FULLANY),
-   this has to be DImode in that case */
-#ifdef HAVE_GAS_SUBSECTION_ORDERING
-#define CASE_VECTOR_MODE \
-(! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
-#else
-/* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
-   we have to sign extend which slows things down. */
-#define CASE_VECTOR_MODE \
-(! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
-#endif
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 8
-
-#if 0 /* Sun 4 has matherr, so this is no good.  */
-/* This is the value of the error code EDOM for this machine,
-   used by the sqrt instruction.  */
-#define TARGET_EDOM 33
-
-/* This is how to refer to the variable errno.  */
-#define GEN_ERRNO_RTX \
-  gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno"))
-#endif /* 0 */
-
-/* Define if operations between registers always perform the operation
-   on the full register even if a narrower mode is specified.  */
-#define WORD_REGISTER_OPERATIONS
-
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.  */
-#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-
-/* Nonzero if access to memory by bytes is slow and undesirable.
-   For RISC chips, it means that access to memory by bytes is no
-   better than access by words when possible, so grab a whole word
-   and maybe make use of that.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
-/* When a prototype says `char' or `short', really pass an `int'.  */
-#define PROMOTE_PROTOTYPES
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
-   few bits. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode (TARGET_PTR64 ? DImode : SImode)
-
-/* Generate calls to memcpy, memcmp and memset.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Add any extra modes needed to represent the condition code.
-
-   On the Sparc, we have a "no-overflow" mode which is used when an add or
-   subtract insn is used to set the condition code.  Different branches are
-   used in this case for some operations.
-
-   We also have two modes to indicate that the relevant condition code is
-   in the floating-point condition code register.  One for comparisons which
-   will generate an exception if the result is unordered (CCFPEmode) and
-   one for comparisons which will never trap (CCFPmode).
-
-   CCXmode and CCX_NOOVmode are only used by v9.  */
-
-#define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode
-
-/* Define the names for the modes specified above.  */
-
-#define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE"
-
-/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
-   return the mode to be used for the comparison.  For floating-point,
-   CCFP[E]mode is used.  CC_NOOVmode should be used when the first operand is a
-   PLUS, MINUS, NEG, or ASHIFT.  CCmode should be used when no special
-   processing is needed.  */
-#define SELECT_CC_MODE(OP,X,Y) \
-  (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT				\
-   ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode)			\
-   : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS			\
-       || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT)		\
-      ? (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \
-      : ((TARGET_ARCH64 || TARGET_V8PLUS) && GET_MODE (X) == DImode ? CCXmode : CCmode)))
-
-/* Return non-zero if SELECT_CC_MODE will never return MODE for a
-   floating point inequality comparison.  */
-
-#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE SImode
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.  */
-#define NO_FUNCTION_CSE
-
-/* alloca should avoid clobbering the old register save area.  */
-#define SETJMP_VIA_SAVE_AREA
-
-/* Define subroutines to call to handle multiply and divide.
-   Use the subroutines that Sun's library provides.
-   The `*' prevents an underscore from being prepended by the compiler.  */
-
-#define DIVSI3_LIBCALL "*.div"
-#define UDIVSI3_LIBCALL "*.udiv"
-#define MODSI3_LIBCALL "*.rem"
-#define UMODSI3_LIBCALL "*.urem"
-/* .umul is a little faster than .mul.  */
-#define MULSI3_LIBCALL "*.umul"
-
-/* Define library calls for quad FP operations.  These are all part of the
-   SPARC ABI.
-   ??? ARCH64 still does not work as the _Qp_* routines take pointers.  */
-#define ADDTF3_LIBCALL (TARGET_ARCH64 ? "_Qp_add" : "_Q_add")
-#define SUBTF3_LIBCALL (TARGET_ARCH64 ? "_Qp_sub" : "_Q_sub")
-#define NEGTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_neg" : "_Q_neg")
-#define MULTF3_LIBCALL (TARGET_ARCH64 ? "_Qp_mul" : "_Q_mul")
-#define DIVTF3_LIBCALL (TARGET_ARCH64 ? "_Qp_div" : "_Q_div")
-#define FLOATSITF2_LIBCALL (TARGET_ARCH64 ? "_Qp_itoq" : "_Q_itoq")
-#define FIX_TRUNCTFSI2_LIBCALL (TARGET_ARCH64 ? "_Qp_qtoi" : "_Q_qtoi")
-#define FIXUNS_TRUNCTFSI2_LIBCALL (TARGET_ARCH64 ? "_Qp_qtoui" : "_Q_qtou")
-#define EXTENDSFTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_stoq" : "_Q_stoq")
-#define TRUNCTFSF2_LIBCALL (TARGET_ARCH64 ? "_Qp_qtos" :  "_Q_qtos")
-#define EXTENDDFTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_dtoq" : "_Q_dtoq")
-#define TRUNCTFDF2_LIBCALL (TARGET_ARCH64 ? "_Qp_qtod" : "_Q_qtod")
-#define EQTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq")
-#define NETF2_LIBCALL (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne")
-#define GTTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt")
-#define GETF2_LIBCALL (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge")
-#define LTTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt")
-#define LETF2_LIBCALL (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle")
-
-/* We can define the TFmode sqrt optab only if TARGET_FPU.  This is because
-   with soft-float, the SFmode and DFmode sqrt instructions will be absent,
-   and the compiler will notice and try to use the TFmode sqrt instruction
-   for calls to the builtin function sqrt, but this fails.  */
-#define INIT_TARGET_OPTABS						\
-  do {									\
-    add_optab->handlers[(int) TFmode].libfunc				\
-      = gen_rtx_SYMBOL_REF (Pmode, ADDTF3_LIBCALL);			\
-    sub_optab->handlers[(int) TFmode].libfunc				\
-      = gen_rtx_SYMBOL_REF (Pmode, SUBTF3_LIBCALL);			\
-    neg_optab->handlers[(int) TFmode].libfunc				\
-      = gen_rtx_SYMBOL_REF (Pmode, NEGTF2_LIBCALL);			\
-    smul_optab->handlers[(int) TFmode].libfunc				\
-      = gen_rtx_SYMBOL_REF (Pmode, MULTF3_LIBCALL);			\
-    flodiv_optab->handlers[(int) TFmode].libfunc			\
-      = gen_rtx_SYMBOL_REF (Pmode, DIVTF3_LIBCALL);			\
-    eqtf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EQTF2_LIBCALL);		\
-    netf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, NETF2_LIBCALL);		\
-    gttf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, GTTF2_LIBCALL);		\
-    getf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, GETF2_LIBCALL);		\
-    lttf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, LTTF2_LIBCALL);		\
-    letf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, LETF2_LIBCALL);		\
-    trunctfsf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, TRUNCTFSF2_LIBCALL);   \
-    trunctfdf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, TRUNCTFDF2_LIBCALL);   \
-    extendsftf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EXTENDSFTF2_LIBCALL); \
-    extenddftf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EXTENDDFTF2_LIBCALL); \
-    floatsitf_libfunc = gen_rtx_SYMBOL_REF (Pmode, FLOATSITF2_LIBCALL);    \
-    fixtfsi_libfunc = gen_rtx_SYMBOL_REF (Pmode, FIX_TRUNCTFSI2_LIBCALL);  \
-    fixunstfsi_libfunc							\
-      = gen_rtx_SYMBOL_REF (Pmode, FIXUNS_TRUNCTFSI2_LIBCALL);		\
-    if (TARGET_FPU)							\
-      sqrt_optab->handlers[(int) TFmode].libfunc			\
-	= gen_rtx_SYMBOL_REF (Pmode, "_Q_sqrt");			\
-    INIT_SUBTARGET_OPTABS;						\
-  } while (0)
-
-/* This is meant to be redefined in the host dependent files */
-#define INIT_SUBTARGET_OPTABS
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000)	\
-      return 0;							\
-  case HIGH:							\
-    return 2;							\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 4;							\
-  case CONST_DOUBLE:						\
-    if (GET_MODE (RTX) == DImode)				\
-      if ((XINT (RTX, 3) == 0					\
-	   && (unsigned) XINT (RTX, 2) < 0x1000)		\
-	  || (XINT (RTX, 3) == -1				\
-	      && XINT (RTX, 2) < 0				\
-	      && XINT (RTX, 2) >= -0x1000))			\
-	return 0;						\
-    return 8;
-
-#define ADDRESS_COST(RTX)  1
-
-/* Compute extra cost of moving data between one register class
-   and another.  */
-#define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)			\
-  (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
-    || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
-    || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS)		\
-   ? (sparc_cpu == PROCESSOR_ULTRASPARC ? 12 : 6) : 2)
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  The purpose for the cost of MULT is to encourage
-   `synth_mult' to find a synthetic multiply when reasonable.
-
-   If we need more than 12 insns to do a multiply, then go out-of-line,
-   since the call overhead will be < 10% of the cost of the multiply.  */
-
-#define RTX_COSTS(X,CODE,OUTER_CODE)			\
-  case MULT:						\
-    if (sparc_cpu == PROCESSOR_ULTRASPARC)		\
-      return (GET_MODE (X) == DImode ?			\
-              COSTS_N_INSNS (34) : COSTS_N_INSNS (19));	\
-    return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
-  case DIV:						\
-  case UDIV:						\
-  case MOD:						\
-  case UMOD:						\
-    if (sparc_cpu == PROCESSOR_ULTRASPARC)		\
-      return (GET_MODE (X) == DImode ?			\
-              COSTS_N_INSNS (68) : COSTS_N_INSNS (37));	\
-    return COSTS_N_INSNS (25);				\
-  /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
-     so that cse will favor the latter.  */		\
-  case FLOAT:						\
-  case FIX:						\
-    return 19;
-
-#define ISSUE_RATE  sparc_issue_rate()
-
-/* Adjust the cost of dependencies.  */
-#define ADJUST_COST(INSN,LINK,DEP,COST) \
-  sparc_adjust_cost(INSN, LINK, DEP, COST)
-
-extern void ultrasparc_sched_reorder ();
-extern void ultrasparc_sched_init ();
-extern int ultrasparc_variable_issue ();
-
-#define MD_SCHED_INIT(DUMP, SCHED_VERBOSE)				\
-  if (sparc_cpu == PROCESSOR_ULTRASPARC)				\
-    ultrasparc_sched_init (DUMP, SCHED_VERBOSE)
-
-#define MD_SCHED_REORDER(DUMP, SCHED_VERBOSE, READY, N_READY)		\
-  if (sparc_cpu == PROCESSOR_ULTRASPARC)				\
-    ultrasparc_sched_reorder (DUMP, SCHED_VERBOSE, READY, N_READY)
-
-#define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
-  if (sparc_cpu == PROCESSOR_ULTRASPARC)			\
-    (CAN_ISSUE_MORE) = ultrasparc_variable_issue (INSN);	\
-  else								\
-    (CAN_ISSUE_MORE)--
-
-/* Conditional branches with empty delay slots have a length of two.  */
-#define ADJUST_INSN_LENGTH(INSN, LENGTH)				\
-  if (GET_CODE (INSN) == CALL_INSN					\
-      || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn)))	\
-    LENGTH += 1; else
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(file)
-
-/* A C string constant describing how to begin a comment in the target
-   assembler language.  The compiler assumes that the comment will end at
-   the end of the line.  */
-
-#define ASM_COMMENT_START "!"
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-
-/* ??? Try to make the style consistent here (_OP?).  */
-
-#define ASM_LONGLONG	".xword"
-#define ASM_LONG	".word"
-#define ASM_SHORT	".half"
-#define ASM_BYTE_OP	".byte"
-#define ASM_FLOAT	".single"
-#define ASM_DOUBLE	".double"
-#define ASM_LONGDOUBLE	".xxx"		/* ??? Not known (or used yet). */
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7",		\
- "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7",		\
- "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7",		\
- "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7",		\
- "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",		\
- "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",		\
- "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",	\
- "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",	\
- "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39",	\
- "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47",	\
- "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55",	\
- "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63",	\
- "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc"}
-
-/* Define additional names for use in asm clobbers and asm declarations.  */
-
-#define ADDITIONAL_REGISTER_NAMES \
-{{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
-
-/* How to renumber registers for dbx and gdb.  In the flat model, the frame
-   pointer is really %i7.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) \
-  (TARGET_FLAT && REGNO == FRAME_POINTER_REGNUM ? 31 : REGNO)
-
-/* On Sun 4, this limit is 2048.  We use 1000 to be safe, since the length
-   can run past this up to a continuation point.  Once we used 1500, but
-   a single entry in C++ can run more than 500 bytes, due to the length of
-   mangled symbol names.  dbxout.c should really be fixed to do
-   continuations when they are actually needed instead of trying to
-   guess...  */
-#define DBX_CONTIN_LENGTH 1000
-
-/* This is how to output a note to DBX telling it the line number
-   to which the following sequence of instructions corresponds.
-
-   This is needed for SunOS 4.0, and should not hurt for 3.2
-   versions either.  */
-#define ASM_OUTPUT_SOURCE_LINE(file, line)		\
-  { static int sym_lineno = 1;				\
-    fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n",	\
-	     line, sym_lineno, sym_lineno);		\
-    sym_lineno += 1; }
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output a definition of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
-
-/* This is how to output an assembler line defining a `float' constant.
-   We always have to use a .long pseudo-op to do this because the native
-   SVR4 ELF assembler is buggy and it generates incorrect values when we
-   try to use the .float pseudo-op instead.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
-  {								\
-    long t;							\
-    char str[30];						\
-    REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
-    REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);		\
-    fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t,		\
-	     ASM_COMMENT_START, str);				\
-  }								\
-
-/* This is how to output an assembler line defining a `double' constant.
-   We always have to use a .long pseudo-op to do this because the native
-   SVR4 ELF assembler is buggy and it generates incorrect values when we
-   try to use the .float pseudo-op instead.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
-  {								\
-    long t[2];							\
-    char str[30];						\
-    REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);			\
-    REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);		\
-    fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0],	\
-	     ASM_COMMENT_START, str);				\
-    fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]);		\
-  }
-
-/* This is how to output an assembler line defining a `long double'
-   constant.  */
-
-#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
-  {								\
-    long t[4];							\
-    char str[30];						\
-    REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t);		\
-    REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);		\
-    fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0],	\
-	     ASM_COMMENT_START, str);				\
-    fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]);		\
-    fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[2]);		\
-    fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[3]);		\
-  }
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t%s\t", ASM_LONG),		\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line defining a DImode constant.  */
-#define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE)  \
-  output_double_int (FILE, VALUE)
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t%s\t", ASM_SHORT),		\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t%s\t", ASM_BYTE_OP),	\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
-
-/* This is how we hook in and defer the case-vector until the end of
-   the function.  */
-extern void sparc_defer_case_vector ();
-
-#define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
-  sparc_defer_case_vector ((LAB),(VEC), 0)
-
-#define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
-  sparc_defer_case_vector ((LAB),(VEC), 1)
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-do {									\
-  char label[30];							\
-  ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);			\
-  if (CASE_VECTOR_MODE == SImode)					\
-    fprintf (FILE, "\t.word\t");					\
-  else									\
-    fprintf (FILE, "\t.xword\t");					\
-  assemble_name (FILE, label);						\
-  fputc ('\n', FILE);							\
-} while (0)
-
-/* This is how to output an element of a case-vector that is relative.
-   (SPARC uses such vectors only when generating PIC.)  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)		\
-do {									\
-  char label[30];							\
-  ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE));			\
-  if (CASE_VECTOR_MODE == SImode)					\
-    fprintf (FILE, "\t.word\t");					\
-  else									\
-    fprintf (FILE, "\t.xword\t");					\
-  assemble_name (FILE, label);						\
-  ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL));			\
-  fputc ('-', FILE);							\
-  assemble_name (FILE, label);						\
-  fputc ('\n', FILE);							\
-} while (0)
-
-/* This is what to output before and after case-vector (both
-   relative and absolute).  If .subsection -1 works, we put case-vectors
-   at the beginning of the current section.  */
-
-#ifdef HAVE_GAS_SUBSECTION_ORDERING
-
-#define ASM_OUTPUT_ADDR_VEC_START(FILE)					\
-  fprintf(FILE, "\t.subsection\t-1\n")
-
-#define ASM_OUTPUT_ADDR_VEC_END(FILE)					\
-  fprintf(FILE, "\t.previous\n")
-
-#endif
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
-
-#define LABEL_ALIGN_AFTER_BARRIER(LABEL) (sparc_align_jumps)
-
-#define LOOP_ALIGN(LABEL) (sparc_align_loops)
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.skip %u\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\t.common ", (FILE)),		\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
-
-/* This says how to output an assembler line to define a local common
-   symbol.  */
-
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED)		\
-( fputs ("\t.reserve ", (FILE)),					\
-  assemble_name ((FILE), (NAME)),					\
-  fprintf ((FILE), ",%u,\"bss\",%u\n",					\
-	   (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of uninitialized global DECL named
-   NAME whose size is SIZE bytes and alignment is ALIGN bytes.
-   Try to use asm_output_aligned_bss to implement this macro.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN)	\
-  do {								\
-    fputs (".globl ", (FILE));					\
-    assemble_name ((FILE), (NAME));				\
-    fputs ("\n", (FILE));					\
-    ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN);		\
-  } while (0)
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-#define IDENT_ASM_OP ".ident"
-
-/* Output #ident as a .ident.  */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
-
-/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
-   Used for C++ multiple inheritance.  */
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION)	\
-do {									\
-  int big_delta = (DELTA) >= 4096 || (DELTA) < -4096;			\
-  if (big_delta)							\
-    fprintf (FILE, "\tset %d,%%g1\n\tadd %%o0,%%g1,%%o0\n", (DELTA));	\
-  /* Don't use the jmp solution unless we know the target is local to	\
-     the application or shared object.  				\
-     XXX: Wimp out and don't actually check anything except if this is	\
-     an embedded target where we assume there are no shared libs.  */	\
-  if (!TARGET_CM_EMBMEDANY || flag_pic)					\
-    {									\
-      if (! big_delta)							\
-	fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA);			\
-      fprintf (FILE, "\tmov %%o7,%%g1\n");				\
-      fprintf (FILE, "\tcall ");					\
-      assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0));	\
-      fprintf (FILE, ",0\n");						\
-    }									\
-  else if (TARGET_CM_EMBMEDANY)						\
-    {									\
-      fprintf (FILE, "\tsetx ");					\
-      assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0));	\
-      fprintf (FILE, ",%%g5,%%g1\n\tjmp %%g1\n");			\
-    }									\
-  else									\
-    {									\
-      fprintf (FILE, "\tsethi %%hi(");					\
-      assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0));	\
-      fprintf (FILE, "),%%g1\n\tjmp %%g1+%%lo(");			\
-      assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0));	\
-      fprintf (FILE, ")\n");						\
-    }									\
-  if (!TARGET_CM_EMBMEDANY || flag_pic)					\
-    fprintf (FILE, "\tmov %%g1,%%o7\n");				\
-  else if (big_delta)							\
-    fprintf (FILE, "\tnop\n");						\
-  else									\
-    fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA);			\
-} while (0)
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
-  ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx base, index = 0;					\
-  int offset = 0;						\
-  register rtx addr = ADDR;					\
-  if (GET_CODE (addr) == REG)					\
-    fputs (reg_names[REGNO (addr)], FILE);			\
-  else if (GET_CODE (addr) == PLUS)				\
-    {								\
-      if (GET_CODE (XEXP (addr, 0)) == CONST_INT)		\
-	offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
-      else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)		\
-	offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
-      else							\
-	base = XEXP (addr, 0), index = XEXP (addr, 1);		\
-      fputs (reg_names[REGNO (base)], FILE);			\
-      if (index == 0)						\
-	fprintf (FILE, "%+d", offset);				\
-      else if (GET_CODE (index) == REG)				\
-	fprintf (FILE, "+%s", reg_names[REGNO (index)]);	\
-      else if (GET_CODE (index) == SYMBOL_REF			\
-	       || GET_CODE (index) == CONST)			\
-	fputc ('+', FILE), output_addr_const (FILE, index);	\
-      else abort ();						\
-    }								\
-  else if (GET_CODE (addr) == MINUS				\
-	   && GET_CODE (XEXP (addr, 1)) == LABEL_REF)		\
-    {								\
-      output_addr_const (FILE, XEXP (addr, 0));			\
-      fputs ("-(", FILE);					\
-      output_addr_const (FILE, XEXP (addr, 1));			\
-      fputs ("-.)", FILE);					\
-    }								\
-  else if (GET_CODE (addr) == LO_SUM)				\
-    {								\
-      output_operand (XEXP (addr, 0), 0);			\
-      if (TARGET_CM_MEDMID)					\
-        fputs ("+%l44(", FILE);					\
-      else							\
-        fputs ("+%lo(", FILE);					\
-      output_address (XEXP (addr, 1));				\
-      fputc (')', FILE);					\
-    }								\
-  else if (flag_pic && GET_CODE (addr) == CONST			\
-	   && GET_CODE (XEXP (addr, 0)) == MINUS		\
-	   && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST	\
-	   && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS	\
-	   && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx)	\
-    {								\
-      addr = XEXP (addr, 0);					\
-      output_addr_const (FILE, XEXP (addr, 0));			\
-      /* Group the args of the second CONST in parenthesis.  */	\
-      fputs ("-(", FILE);					\
-      /* Skip past the second CONST--it does nothing for us.  */\
-      output_addr_const (FILE, XEXP (XEXP (addr, 1), 0));	\
-      /* Close the parenthesis.  */				\
-      fputc (')', FILE);					\
-    }								\
-  else								\
-    {								\
-      output_addr_const (FILE, addr);				\
-    }								\
-}
-
-/* Define the codes that are matched by predicates in sparc.c.  */
-
-#define PREDICATE_CODES							\
-{"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},		\
-{"fp_zero_operand", {CONST_DOUBLE}},					\
-{"intreg_operand", {SUBREG, REG}},					\
-{"fcc_reg_operand", {REG}},						\
-{"icc_or_fcc_reg_operand", {REG}},					\
-{"restore_operand", {REG}},						\
-{"call_operand", {MEM}},						\
-{"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE,	\
-	ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}},		\
-{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE}},	\
-{"symbolic_memory_operand", {SUBREG, MEM}},				\
-{"label_ref_operand", {LABEL_REF}},					\
-{"sp64_medium_pic_operand", {CONST}},					\
-{"data_segment_operand", {SYMBOL_REF, PLUS, CONST}},			\
-{"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}},		\
-{"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}},			\
-{"splittable_symbolic_memory_operand", {MEM}},				\
-{"splittable_immediate_memory_operand", {MEM}},				\
-{"eq_or_neq", {EQ, NE}},						\
-{"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}},			\
-{"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}},	\
-{"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}},				\
-{"extend_op", {SIGN_EXTEND, ZERO_EXTEND}},				\
-{"cc_arithop", {AND, IOR, XOR}},					\
-{"cc_arithopn", {AND, IOR}},						\
-{"arith_operand", {SUBREG, REG, CONST_INT}},				\
-{"arith_add_operand", {SUBREG, REG, CONST_INT}},			\
-{"arith11_operand", {SUBREG, REG, CONST_INT}},				\
-{"arith10_operand", {SUBREG, REG, CONST_INT}},				\
-{"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
-{"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
-{"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
-{"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
-{"small_int", {CONST_INT}},						\
-{"small_int_or_double", {CONST_INT, CONST_DOUBLE}},			\
-{"uns_small_int", {CONST_INT}},						\
-{"uns_arith_operand", {SUBREG, REG, CONST_INT}},			\
-{"clobbered_register", {REG}},						\
-{"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}},		\
-{"zero_operand", {CONST_INT}},						\
-{"const64_operand", {CONST_INT, CONST_DOUBLE}},				\
-{"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
-
-/* The number of Pmode words for the setjmp buffer.  */
-#define JMP_BUF_SIZE 12
-
-#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)
-
-/* Declare functions defined in sparc.c and used in templates.  */
-
-extern void sparc_emit_set_const32 ();
-extern void sparc_emit_set_const64 ();
-extern void sparc_emit_set_symbolic_const64 ();
-extern int sparc_splitdi_legitimate ();
-extern int sparc_absnegfloat_split_legitimate ();
-
-extern char *output_cbranch ();
-extern char *output_return ();
-extern char *output_v9branch ();
-
-extern void emit_v9_brxx_insn ();
-extern void finalize_pic ();
-extern void order_regs_for_local_alloc ();
-extern void output_double_int ();
-extern void output_function_epilogue ();
-extern void output_function_prologue ();
-extern void print_operand ();
-extern void sparc_flat_output_function_epilogue ();
-extern void sparc_flat_output_function_prologue ();
-
-extern int addrs_ok_for_ldd_peep ();
-extern int arith10_double_operand ();
-extern int arith10_operand ();
-extern int arith11_double_operand ();
-extern int arith11_operand ();
-extern int arith_double_operand ();
-extern int arith_double_4096_operand ();
-extern int arith_double_add_operand ();
-extern int arith_operand ();
-extern int arith_4096_operand ();
-extern int arith_add_operand ();
-extern int call_operand_address ();
-extern int input_operand ();
-extern int zero_operand ();
-extern int const64_operand ();
-extern int const64_high_operand ();
-extern int cc_arithop ();
-extern int cc_arithopn ();
-extern int check_pic ();
-extern int compute_frame_size ();
-extern int data_segment_operand ();
-extern int eligible_for_epilogue_delay ();
-extern int eligible_for_return_delay ();
-extern int emit_move_sequence ();
-extern int extend_op ();
-extern int fcc_reg_operand ();
-extern int fp_zero_operand ();
-extern int icc_or_fcc_reg_operand ();
-extern int label_ref_operand ();
-extern int mem_min_alignment ();
-extern int noov_compare_op ();
-extern int pic_address_needs_scratch ();
-extern int reg_or_0_operand ();
-extern int reg_or_nonsymb_mem_operand ();
-extern int reg_unused_after ();
-extern int register_ok_for_ldd ();
-extern int registers_ok_for_ldd_peep ();
-extern int restore_operand ();
-extern int short_branch ();
-extern int small_int ();
-extern int small_int_or_double ();
-extern int sp64_medium_pic_operand ();
-extern int sparc_flat_eligible_for_epilogue_delay ();
-extern int sparc_flat_epilogue_delay_slots ();
-extern int sparc_issue_rate ();
-extern int splittable_immediate_memory_operand ();
-extern int splittable_symbolic_memory_operand ();
-extern int sparc_adjust_cost ();
-extern int symbolic_memory_operand ();
-extern int symbolic_operand ();
-extern int text_segment_operand ();
-extern int uns_small_int ();
-extern int v9_regcmp_op ();
-extern int v9_regcmp_p ();
-
-extern unsigned long sparc_flat_compute_frame_size ();
-extern unsigned long sparc_type_code ();
-
-extern char *sparc_v8plus_shift ();
-
-#ifdef __STDC__
-/* Function used for V8+ code generation.  Returns 1 if the high
-   32 bits of REG are 0 before INSN.  */   
-extern int sparc_check_64 (struct rtx_def *, struct rtx_def *);
-extern int sparc_return_peephole_ok (struct rtx_def *, struct rtx_def *);
-extern int compute_frame_size (int, int);
-#endif
-
-/* Defined in flags.h, but insn-emit.c does not include flags.h.  */
-
-extern int flag_pic;
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
deleted file mode 100755
index 1277e2b..0000000
--- a/gcc/config/sparc/sparc.md
+++ /dev/null
@@ -1,8242 +0,0 @@
-;;- Machine description for SPARC chip for GNU C compiler
-;;  Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
-;;  Contributed by Michael Tiemann (tiemann@cygnus.com)
-;;  64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
-;;  at Cygnus Support.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; Uses of UNSPEC and UNSPEC_VOLATILE in this file:
-;;
-;; UNSPEC:		0	movsi_{lo_sum,high}_pic
-;;				pic_lo_sum_di
-;;				pic_sethi_di
-;;			1	update_return
-;;			2	get_pc
-;;			5	movsi_{,lo_sum_,high_}pic_label_ref
-;;			6	seth44
-;;			7	setm44
-;;			8	setl44
-;;			9	sethh
-;;			10	setlm
-;;			11	embmedany_sethi, embmedany_brsum
-;;                      12	movsf_const_high
-;;			13	embmedany_textuhi
-;;			14	embmedany_texthi
-;;			15	embmedany_textulo
-;;			16	embmedany_textlo
-;;                      17	movsf_const_lo
-;;			18	sethm
-;;			19	setlo
-;;
-;; UNSPEC_VOLATILE:	0	blockage
-;;			1	flush_register_windows
-;;			2	goto_handler_and_restore
-;;			3	goto_handler_and_restore_v9*
-;;			4	flush
-;;			5	nonlocal_goto_receiver
-;;
-
-;; The upper 32 fp regs on the v9 can't hold SFmode values.  To deal with this
-;; a second register class, EXTRA_FP_REGS, exists for the v9 chip.  The name
-;; is a bit of a misnomer as it covers all 64 fp regs.  The corresponding
-;; constraint letter is 'e'.  To avoid any confusion, 'e' is used instead of
-;; 'f' for all DF/TFmode values, including those that are specific to the v8.
-;;
-;; -mlive-g0 is *not* supported for TARGET_ARCH64, so we don't bother to
-;; test TARGET_LIVE_G0 if we have TARGET_ARCH64.
-
-;; Attribute for cpu type.
-;; These must match the values for enum processor_type in sparc.h.
-(define_attr "cpu" "v7,cypress,v8,supersparc,sparclite,f930,f934,hypersparc,sparclite86x,sparclet,tsc701,v9,ultrasparc"
-  (const (symbol_ref "sparc_cpu_attr")))
-
-;; Attribute for the instruction set.
-;; At present we only need to distinguish v9/!v9, but for clarity we
-;; test TARGET_V8 too.
-(define_attr "isa" "v6,v8,v9,sparclet"
- (const
-  (cond [(symbol_ref "TARGET_V9") (const_string "v9")
-	 (symbol_ref "TARGET_V8") (const_string "v8")
-	 (symbol_ref "TARGET_SPARCLET") (const_string "sparclet")]
-	(const_string "v6"))))
-
-;; Architecture size.
-(define_attr "arch" "arch32bit,arch64bit"
- (const
-  (cond [(symbol_ref "TARGET_ARCH64") (const_string "arch64bit")]
-	(const_string "arch32bit"))))
-
-;; Whether -mlive-g0 is in effect.
-(define_attr "live_g0" "no,yes"
- (const
-  (cond [(symbol_ref "TARGET_LIVE_G0") (const_string "yes")]
-	(const_string "no"))))
-
-;; Insn type.  Used to default other attribute values.
-
-;; type "unary" insns have one input operand (1) and one output operand (0)
-;; type "binary" insns have two input operands (1,2) and one output (0)
-;; type "compare" insns have one or two input operands (0,1) and no output
-;; type "call_no_delay_slot" is a call followed by an unimp instruction.
-
-(define_attr "type"
-  "move,unary,binary,compare,load,sload,store,ialu,shift,uncond_branch,branch,call,call_no_delay_slot,return,address,imul,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrt,cmove,multi,misc"
-  (const_string "binary"))
-
-;; Set true if insn uses call-clobbered intermediate register.
-(define_attr "use_clobbered" "false,true"
-  (if_then_else (and (eq_attr "type" "address")
-		     (match_operand 0 "clobbered_register" ""))
-	 	(const_string "true")
-		(const_string "false")))
-
-;; Length (in # of insns).
-(define_attr "length" ""
-  (cond [(eq_attr "type" "load,sload,fpload")
-	 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
-		       (const_int 2) (const_int 1))
-
-	 (eq_attr "type" "store,fpstore")
-	 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
-		       (const_int 2) (const_int 1))
-
-	 (eq_attr "type" "address") (const_int 2)
-
-	 (eq_attr "type" "binary")
-	 (if_then_else (ior (match_operand 2 "arith_operand" "")
-			    (match_operand 2 "arith_double_operand" ""))
-		       (const_int 1) (const_int 3))
-
-	 (eq_attr "type" "multi") (const_int 2)
-
-	 (eq_attr "type" "move,unary")
-	 (if_then_else (ior (match_operand 1 "arith_operand" "")
-			    (match_operand 1 "arith_double_operand" ""))
-		       (const_int 1) (const_int 2))]
-
-	(const_int 1)))
-
-(define_asm_attributes
-  [(set_attr "length" "1")
-   (set_attr "type" "multi")])
-
-;; Attributes for instruction and branch scheduling
-
-(define_attr "in_call_delay" "false,true"
-  (cond [(eq_attr "type" "uncond_branch,branch,call,call_no_delay_slot,return,multi")
-	 	(const_string "false")
-	 (eq_attr "type" "load,fpload,store,fpstore")
-	 	(if_then_else (eq_attr "length" "1")
-			      (const_string "true")
-			      (const_string "false"))
-	 (eq_attr "type" "address")
-	 	(if_then_else (eq_attr "use_clobbered" "false")
-			      (const_string "true")
-			      (const_string "false"))]
-	(if_then_else (eq_attr "length" "1")
-		      (const_string "true")
-		      (const_string "false"))))
-
-(define_delay (eq_attr "type" "call")
-  [(eq_attr "in_call_delay" "true") (nil) (nil)])
-
-(define_attr "leaf_function" "false,true"
-  (const (symbol_ref "leaf_function")))
-
-(define_attr "in_return_delay" "false,true"
-  (if_then_else (and (and (and (eq_attr "type" "move,load,sload,store,binary,ialu")
-			       (eq_attr "length" "1"))
-			  (eq_attr "leaf_function" "false"))
-		     (match_insn "eligible_for_return_delay"))
-		(const_string "true")
-		(const_string "false")))
-
-(define_delay (and (eq_attr "type" "return")
-		   (eq_attr "isa" "v9"))
-  [(eq_attr "in_return_delay" "true") (nil) (nil)])
-
-;; ??? Should implement the notion of predelay slots for floating point
-;; branches.  This would allow us to remove the nop always inserted before
-;; a floating point branch.
-
-;; ??? It is OK for fill_simple_delay_slots to put load/store instructions
-;; in a delay slot, but it is not OK for fill_eager_delay_slots to do so.
-;; This is because doing so will add several pipeline stalls to the path
-;; that the load/store did not come from.  Unfortunately, there is no way
-;; to prevent fill_eager_delay_slots from using load/store without completely
-;; disabling them.  For the SPEC benchmark set, this is a serious lose,
-;; because it prevents us from moving back the final store of inner loops.
-
-(define_attr "in_branch_delay" "false,true"
-  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,call_no_delay_slot,multi")
-		     (eq_attr "length" "1"))
-		(const_string "true")
-		(const_string "false")))
-
-(define_attr "in_uncond_branch_delay" "false,true"
-  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,call_no_delay_slot,multi")
-		     (eq_attr "length" "1"))
-		(const_string "true")
-		(const_string "false")))
-
-(define_attr "in_annul_branch_delay" "false,true"
-  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,call_no_delay_slot,multi")
-		     (eq_attr "length" "1"))
-		(const_string "true")
-		(const_string "false")))
-
-(define_delay (eq_attr "type" "branch")
-  [(eq_attr "in_branch_delay" "true")
-   (nil) (eq_attr "in_annul_branch_delay" "true")])
-
-(define_delay (eq_attr "type" "uncond_branch")
-  [(eq_attr "in_uncond_branch_delay" "true")
-   (nil) (nil)])
-   
-;; Function units of the SPARC
-
-;; (define_function_unit {name} {num-units} {n-users} {test}
-;;                       {ready-delay} {issue-delay} [{conflict-list}])
-
-;; The integer ALU.
-;; (Noted only for documentation; units that take one cycle do not need to
-;; be specified.)
-
-;; On the sparclite, integer multiply takes 1, 3, or 5 cycles depending on
-;; the inputs.
-
-;; (define_function_unit "alu" 1 0
-;;  (eq_attr "type" "unary,binary,move,address") 1 0)
-
-;; ---- cypress CY7C602 scheduling:
-;; Memory with load-delay of 1 (i.e., 2 cycle load).
-
-(define_function_unit "memory" 1 0 
-  (and (eq_attr "cpu" "cypress")
-    (eq_attr "type" "load,sload,fpload"))
-  2 2)
-
-;; SPARC has two floating-point units: the FP ALU,
-;; and the FP MUL/DIV/SQRT unit.
-;; Instruction timings on the CY7C602 are as follows
-;; FABSs	4
-;; FADDs/d	5/5
-;; FCMPs/d	4/4
-;; FDIVs/d	23/37
-;; FMOVs	4
-;; FMULs/d	5/7
-;; FNEGs	4
-;; FSQRTs/d	34/63
-;; FSUBs/d	5/5
-;; FdTOi/s	5/5
-;; FsTOi/d	5/5
-;; FiTOs/d	9/5
-
-;; The CY7C602 can only support 2 fp isnsn simultaneously.
-;; More insns cause the chip to stall.
-
-(define_function_unit "fp_alu" 1 0
-  (and (eq_attr "cpu" "cypress")
-    (eq_attr "type" "fp,fpmove"))
-  5 5)
-
-(define_function_unit "fp_mds" 1 0
-  (and (eq_attr "cpu" "cypress")
-    (eq_attr "type" "fpmul"))
-  7 7)
-
-(define_function_unit "fp_mds" 1 0
-  (and (eq_attr "cpu" "cypress")
-    (eq_attr "type" "fpdivs,fpdivd"))
-  37 37)
-
-(define_function_unit "fp_mds" 1 0
-  (and (eq_attr "cpu" "cypress")
-    (eq_attr "type" "fpsqrt"))
-  63 63)
-
-;; ----- The TMS390Z55 scheduling
-;; The Supersparc can issue 1 - 3 insns per cycle: up to two integer,
-;; one ld/st, one fp.
-;; Memory delivers its result in one cycle to IU, zero cycles to FP
-
-(define_function_unit "memory" 1 0
-  (and (eq_attr "cpu" "supersparc")
-    (eq_attr "type" "load,sload"))
-  1 1)
-
-(define_function_unit "memory" 1 0
-  (and (eq_attr "cpu" "supersparc")
-    (eq_attr "type" "fpload"))
-  0 1)
-
-(define_function_unit "memory" 1 0
-  (and (eq_attr "cpu" "supersparc")
-    (eq_attr "type" "store,fpstore"))
-  1 1)
-
-(define_function_unit "shift" 1 0
-  (and (eq_attr "cpu" "supersparc")
-    (eq_attr "type" "shift"))
-  1 1)
-
-;; There are only two write ports to the integer register file
-;; A store also uses a write port
-
-(define_function_unit "iwport" 2 0
-  (and (eq_attr "cpu" "supersparc")
-    (eq_attr "type" "load,sload,store,shift,ialu"))
-  1 1)
-
-;; Timings; throughput/latency
-;; FADD     1/3    add/sub, format conv, compar, abs, neg
-;; FMUL     1/3
-;; FDIVs    4/6
-;; FDIVd    7/9
-;; FSQRTs   6/8
-;; FSQRTd  10/12
-;; IMUL     4/4
-
-(define_function_unit "fp_alu" 1 0
-  (and (eq_attr "cpu" "supersparc")
-    (eq_attr "type" "fp,fpmove,fpcmp"))
-  3 1)
-
-(define_function_unit "fp_mds" 1 0
-  (and (eq_attr "cpu" "supersparc")
-    (eq_attr "type" "fpmul"))
-  3 1)
-
-(define_function_unit "fp_mds" 1 0
-  (and (eq_attr "cpu" "supersparc")
-    (eq_attr "type" "fpdivs"))
-  6 4)
-
-(define_function_unit "fp_mds" 1 0
-  (and (eq_attr "cpu" "supersparc")
-    (eq_attr "type" "fpdivd"))
-  9 7)
-
-(define_function_unit "fp_mds" 1 0
-  (and (eq_attr "cpu" "supersparc")
-    (eq_attr "type" "fpsqrt"))
-  12 10)
-
-(define_function_unit "fp_mds" 1 0
-  (and (eq_attr "cpu" "supersparc")
-    (eq_attr "type" "imul"))
-  4 4)
-
-;; ----- hypersparc/sparclite86x scheduling
-;; The Hypersparc can issue 1 - 2 insns per cycle.  The dual issue cases are:
-;; L-Ld/St I-Int F-Float B-Branch LI/LF/LB/II/IF/IB/FF/FB
-;; II/FF case is only when loading a 32 bit hi/lo constant
-;; Single issue insns include call, jmpl, u/smul, u/sdiv, lda, sta, fcmp
-;; Memory delivers its result in one cycle to IU
-
-(define_function_unit "memory" 1 0
-  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
-    (eq_attr "type" "load,sload,fpload"))
-  1 1)
-
-(define_function_unit "memory" 1 0
-  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
-    (eq_attr "type" "store,fpstore"))
-  2 1)
-
-(define_function_unit "fp_alu" 1 0
-  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
-    (eq_attr "type" "fp,fpmove,fpcmp"))
-  1 1)
-
-(define_function_unit "fp_mds" 1 0
-  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
-    (eq_attr "type" "fpmul"))
-  1 1)
-
-(define_function_unit "fp_mds" 1 0
-  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
-    (eq_attr "type" "fpdivs"))
-  8 6)
-
-(define_function_unit "fp_mds" 1 0
-  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
-    (eq_attr "type" "fpdivd"))
-  12 10)
-
-(define_function_unit "fp_mds" 1 0
-  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
-    (eq_attr "type" "fpsqrt"))
-  17 15)
-
-(define_function_unit "fp_mds" 1 0
-  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
-    (eq_attr "type" "imul"))
-  17 15)
-
-;; ----- sparclet tsc701 scheduling
-;; The tsc701 issues 1 insn per cycle.
-;; Results may be written back out of order.
-
-;; Loads take 2 extra cycles to complete and 4 can be buffered at a time.
-
-(define_function_unit "tsc701_load" 4 1
-  (and (eq_attr "cpu" "tsc701")
-    (eq_attr "type" "load,sload"))
-  3 1)
-
-;; Stores take 2(?) extra cycles to complete.
-;; It is desirable to not have any memory operation in the following 2 cycles.
-;; (??? or 2 memory ops in the case of std).
-
-(define_function_unit "tsc701_store" 1 0
-  (and (eq_attr "cpu" "tsc701")
-    (eq_attr "type" "store"))
-  3 3
-  [(eq_attr "type" "load,sload,store")])
-
-;; The multiply unit has a latency of 5.
-(define_function_unit "tsc701_mul" 1 0
-  (and (eq_attr "cpu" "tsc701")
-    (eq_attr "type" "imul"))
-  5 5)
-
-;; ----- The UltraSPARC-1 scheduling
-;; UltraSPARC has two integer units.  Shift instructions can only execute
-;; on IE0.  Condition code setting instructions, call, and jmpl (including
-;; the ret and retl pseudo-instructions) can only execute on IE1.
-;; Branch on register uses IE1, but branch on condition code does not.
-;; Conditional moves take 2 cycles.  No other instruction can issue in the
-;; same cycle as a conditional move.
-;; Multiply and divide take many cycles during which no other instructions
-;; can issue.
-;; Memory delivers its result in two cycles (except for signed loads,
-;; which take one cycle more).  One memory instruction can be issued per
-;; cycle.
-
-(define_function_unit "memory" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "load,fpload"))
-  2 1)
-
-(define_function_unit "memory" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "sload"))
-  3 1)
-
-(define_function_unit "memory" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "store,fpstore"))
-  1 1)
-
-(define_function_unit "ieuN" 2 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "ialu,binary,move,unary,shift,compare,call,call_no_delay_slot,uncond_branch"))
-  1 1)
-
-(define_function_unit "ieu0" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "shift"))
-  1 1)
-
-(define_function_unit "ieu0" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "cmove"))
-  2 1)
-
-(define_function_unit "ieu1" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "compare,call,call_no_delay_slot,uncond_branch"))
-  1 1)
-
-(define_function_unit "cti" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "branch"))
-  1 1)
-
-;; Timings; throughput/latency
-;; FMOV     1/1    fmov, fabs, fneg
-;; FMOVcc   1/2
-;; FADD     1/4    add/sub, format conv, compar
-;; FMUL     1/4
-;; FDIVs    12/12
-;; FDIVd    22/22
-;; FSQRTs   12/12
-;; FSQRTd   22/22
-;; FCMP takes 1 cycle to branch, 2 cycles to conditional move.
-;;
-;; ??? This is really bogus because the timings really depend upon
-;; who uses the result.  We should record who the user is with
-;; more descriptive 'type' attribute names and account for these
-;; issues in ultrasparc_adjust_cost. 
-
-(define_function_unit "fadd" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpmove"))
-  1 1)
-
-(define_function_unit "fadd" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpcmove"))
-  2 1)
-
-(define_function_unit "fadd" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fp"))
-  4 1)
-
-(define_function_unit "fadd" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpcmp"))
-  2 1)
-
-(define_function_unit "fmul" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpmul"))
-  4 1)
-
-(define_function_unit "fadd" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpcmove"))
-  2 1)
-
-(define_function_unit "fmul" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpdivs"))
-  12 12)
-
-(define_function_unit "fmul" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpdivd"))
-  22 22)
-
-(define_function_unit "fmul" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpsqrt"))
-  12 12)
-
-;; Compare instructions.
-;; This controls RTL generation and register allocation.
-
-;; We generate RTL for comparisons and branches by having the cmpxx 
-;; patterns store away the operands.  Then, the scc and bcc patterns
-;; emit RTL for both the compare and the branch.
-;;
-;; We do this because we want to generate different code for an sne and
-;; seq insn.  In those cases, if the second operand of the compare is not
-;; const0_rtx, we want to compute the xor of the two operands and test
-;; it against zero.
-;;
-;; We start with the DEFINE_EXPANDs, then the DEFINE_INSNs to match
-;; the patterns.  Finally, we have the DEFINE_SPLITs for some of the scc
-;; insns that actually require more than one machine instruction.
-
-;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
-
-(define_expand "cmpsi"
-  [(set (reg:CC 100)
-	(compare:CC (match_operand:SI 0 "register_operand" "")
-		    (match_operand:SI 1 "arith_operand" "")))]
-  ""
-  "
-{
-  sparc_compare_op0 = operands[0];
-  sparc_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "cmpdi"
-  [(set (reg:CCX 100)
-	(compare:CCX (match_operand:DI 0 "register_operand" "")
-		     (match_operand:DI 1 "arith_double_operand" "")))]
-  "TARGET_ARCH64"
-  "
-{
-  sparc_compare_op0 = operands[0];
-  sparc_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "cmpsf"
-  ;; The 96 here isn't ever used by anyone.
-  [(set (reg:CCFP 96)
-	(compare:CCFP (match_operand:SF 0 "register_operand" "")
-		      (match_operand:SF 1 "register_operand" "")))]
-  "TARGET_FPU"
-  "
-{
-  sparc_compare_op0 = operands[0];
-  sparc_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "cmpdf"
-  ;; The 96 here isn't ever used by anyone.
-  [(set (reg:CCFP 96)
-	(compare:CCFP (match_operand:DF 0 "register_operand" "")
-		      (match_operand:DF 1 "register_operand" "")))]
-  "TARGET_FPU"
-  "
-{
-  sparc_compare_op0 = operands[0];
-  sparc_compare_op1 = operands[1];
-  DONE;
-}")
-
-(define_expand "cmptf"
-  ;; The 96 here isn't ever used by anyone.
-  [(set (reg:CCFP 96)
-	(compare:CCFP (match_operand:TF 0 "register_operand" "")
-		      (match_operand:TF 1 "register_operand" "")))]
-  "TARGET_FPU"
-  "
-{
-  sparc_compare_op0 = operands[0];
-  sparc_compare_op1 = operands[1];
-  DONE;
-}")
-
-;; Now the compare DEFINE_INSNs.
-
-(define_insn "*cmpsi_insn"
-  [(set (reg:CC 100)
-	(compare:CC (match_operand:SI 0 "register_operand" "r")
-		    (match_operand:SI 1 "arith_operand" "rI")))]
-  ""
-  "cmp\\t%0, %1"
-  [(set_attr "type" "compare")])
-
-(define_insn "*cmpdi_sp64"
-  [(set (reg:CCX 100)
-	(compare:CCX (match_operand:DI 0 "register_operand" "r")
-		     (match_operand:DI 1 "arith_double_operand" "rHI")))]
-  "TARGET_ARCH64"
-  "cmp\\t%0, %1"
-  [(set_attr "type" "compare")])
-
-(define_insn "*cmpsf_fpe"
-  [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
-	(compare:CCFPE (match_operand:SF 1 "register_operand" "f")
-		       (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "*
-{
-  if (TARGET_V9)
-    return \"fcmpes\\t%0, %1, %2\";
-  return \"fcmpes\\t%1, %2\";
-}"
-  [(set_attr "type" "fpcmp")])
-
-(define_insn "*cmpdf_fpe"
-  [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
-	(compare:CCFPE (match_operand:DF 1 "register_operand" "e")
-		       (match_operand:DF 2 "register_operand" "e")))]
-  "TARGET_FPU"
-  "*
-{
-  if (TARGET_V9)
-    return \"fcmped\\t%0, %1, %2\";
-  return \"fcmped\\t%1, %2\";
-}"
-  [(set_attr "type" "fpcmp")])
-
-(define_insn "*cmptf_fpe"
-  [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
-	(compare:CCFPE (match_operand:TF 1 "register_operand" "e")
-		       (match_operand:TF 2 "register_operand" "e")))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "*
-{
-  if (TARGET_V9)
-    return \"fcmpeq\\t%0, %1, %2\";
-  return \"fcmpeq\\t%1, %2\";
-}"
-  [(set_attr "type" "fpcmp")])
-
-(define_insn "*cmpsf_fp"
-  [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
-	(compare:CCFP (match_operand:SF 1 "register_operand" "f")
-		      (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "*
-{
-  if (TARGET_V9)
-    return \"fcmps\\t%0, %1, %2\";
-  return \"fcmps\\t%1, %2\";
-}"
-  [(set_attr "type" "fpcmp")])
-
-(define_insn "*cmpdf_fp"
-  [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
-	(compare:CCFP (match_operand:DF 1 "register_operand" "e")
-		      (match_operand:DF 2 "register_operand" "e")))]
-  "TARGET_FPU"
-  "*
-{
-  if (TARGET_V9)
-    return \"fcmpd\\t%0, %1, %2\";
-  return \"fcmpd\\t%1, %2\";
-}"
-  [(set_attr "type" "fpcmp")])
-
-(define_insn "*cmptf_fp"
-  [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
-	(compare:CCFP (match_operand:TF 1 "register_operand" "e")
-		      (match_operand:TF 2 "register_operand" "e")))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "*
-{
-  if (TARGET_V9)
-    return \"fcmpq\\t%0, %1, %2\";
-  return \"fcmpq\\t%1, %2\";
-}"
-  [(set_attr "type" "fpcmp")])
-
-;; Next come the scc insns.  For seq, sne, sgeu, and sltu, we can do this
-;; without jumps using the addx/subx instructions.  For seq/sne on v9 we use
-;; the same code as v8 (the addx/subx method has more applications).  The
-;; exception to this is "reg != 0" which can be done in one instruction on v9
-;; (so we do it).  For the rest, on v9 we use conditional moves; on v8, we do
-;; branches.
-
-;; Seq_special[_xxx] and sne_special[_xxx] clobber the CC reg, because they
-;; generate addcc/subcc instructions.
-
-(define_expand "seqsi_special"
-  [(set (match_dup 3)
-	(xor:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "register_operand" "")))
-   (parallel [(set (match_operand:SI 0 "register_operand" "")
-		   (eq:SI (match_dup 3) (const_int 0)))
-	      (clobber (reg:CC 100))])]
-  "! TARGET_LIVE_G0"
-  "{ operands[3] = gen_reg_rtx (SImode); }")
-
-(define_expand "seqdi_special"
-  [(set (match_dup 3)
-	(xor:DI (match_operand:DI 1 "register_operand" "")
-		(match_operand:DI 2 "register_operand" "")))
-   (set (match_operand:DI 0 "register_operand" "")
-	(eq:DI (match_dup 3) (const_int 0)))]
-  "TARGET_ARCH64"
-  "{ operands[3] = gen_reg_rtx (DImode); }")
-
-(define_expand "snesi_special"
-  [(set (match_dup 3)
-	(xor:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "register_operand" "")))
-   (parallel [(set (match_operand:SI 0 "register_operand" "")
-		   (ne:SI (match_dup 3) (const_int 0)))
-	      (clobber (reg:CC 100))])]
-  "! TARGET_LIVE_G0"
-  "{ operands[3] = gen_reg_rtx (SImode); }")
-
-(define_expand "snedi_special"
-  [(set (match_dup 3)
-	(xor:DI (match_operand:DI 1 "register_operand" "")
-		(match_operand:DI 2 "register_operand" "")))
-   (set (match_operand:DI 0 "register_operand" "")
-	(ne:DI (match_dup 3) (const_int 0)))]
-  "TARGET_ARCH64"
-  "{ operands[3] = gen_reg_rtx (DImode); }")
-
-(define_expand "seqdi_special_trunc"
-  [(set (match_dup 3)
-	(xor:DI (match_operand:DI 1 "register_operand" "")
-		(match_operand:DI 2 "register_operand" "")))
-   (set (match_operand:SI 0 "register_operand" "")
-	(eq:SI (match_dup 3) (const_int 0)))]
-  "TARGET_ARCH64"
-  "{ operands[3] = gen_reg_rtx (DImode); }")
-
-(define_expand "snedi_special_trunc"
-  [(set (match_dup 3)
-	(xor:DI (match_operand:DI 1 "register_operand" "")
-		(match_operand:DI 2 "register_operand" "")))
-   (set (match_operand:SI 0 "register_operand" "")
-	(ne:SI (match_dup 3) (const_int 0)))]
-  "TARGET_ARCH64"
-  "{ operands[3] = gen_reg_rtx (DImode); }")
-
-(define_expand "seqsi_special_extend"
-  [(set (match_dup 3)
-	(xor:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "register_operand" "")))
-   (parallel [(set (match_operand:DI 0 "register_operand" "")
-		   (eq:DI (match_dup 3) (const_int 0)))
-	      (clobber (reg:CC 100))])]
-  "TARGET_ARCH64"
-  "{ operands[3] = gen_reg_rtx (SImode); }")
-
-(define_expand "snesi_special_extend"
-  [(set (match_dup 3)
-	(xor:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "register_operand" "")))
-   (parallel [(set (match_operand:DI 0 "register_operand" "")
-		   (ne:DI (match_dup 3) (const_int 0)))
-	      (clobber (reg:CC 100))])]
-  "TARGET_ARCH64"
-  "{ operands[3] = gen_reg_rtx (SImode); }")
-
-;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
-;; However, the code handles both SImode and DImode.
-(define_expand "seq"
-  [(set (match_operand:SI 0 "intreg_operand" "")
-	(eq:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "
-{
-  if (GET_MODE (sparc_compare_op0) == SImode)
-    {
-      rtx pat;
-
-      if (GET_MODE (operands[0]) == SImode)
-	pat = gen_seqsi_special (operands[0], sparc_compare_op0,
-				 sparc_compare_op1);
-      else if (! TARGET_ARCH64)
-	FAIL;
-      else
-	pat = gen_seqsi_special_extend (operands[0], sparc_compare_op0,
-					sparc_compare_op1);
-      emit_insn (pat);
-      DONE;
-    }
-  else if (GET_MODE (sparc_compare_op0) == DImode)
-    {
-      rtx pat;
-
-      if (! TARGET_ARCH64)
-	FAIL;
-      else if (GET_MODE (operands[0]) == SImode)
-	pat = gen_seqdi_special_trunc (operands[0], sparc_compare_op0,
-				       sparc_compare_op1);
-      else
-	pat = gen_seqdi_special (operands[0], sparc_compare_op0,
-				 sparc_compare_op1);
-      emit_insn (pat);
-      DONE;
-    }
-  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
-    {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
-      emit_insn (gen_sne (operands[0]));
-      DONE;
-    }      
-  else if (TARGET_V9)
-    {
-      if (gen_v9_scc (EQ, operands))
-	DONE;
-      /* fall through */
-    }
-  FAIL;
-}")
-
-;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
-;; However, the code handles both SImode and DImode.
-(define_expand "sne"
-  [(set (match_operand:SI 0 "intreg_operand" "")
-	(ne:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "
-{
-  if (GET_MODE (sparc_compare_op0) == SImode)
-    {
-      rtx pat;
-
-      if (GET_MODE (operands[0]) == SImode)
-	pat = gen_snesi_special (operands[0], sparc_compare_op0,
-				 sparc_compare_op1);
-      else if (! TARGET_ARCH64)
-	FAIL;
-      else
-	pat = gen_snesi_special_extend (operands[0], sparc_compare_op0,
-					sparc_compare_op1);
-      emit_insn (pat);
-      DONE;
-    }
-  else if (GET_MODE (sparc_compare_op0) == DImode)
-    {
-      rtx pat;
-
-      if (! TARGET_ARCH64)
-	FAIL;
-      else if (GET_MODE (operands[0]) == SImode)
-	pat = gen_snedi_special_trunc (operands[0], sparc_compare_op0,
-				       sparc_compare_op1);
-      else
-	pat = gen_snedi_special (operands[0], sparc_compare_op0,
-				 sparc_compare_op1);
-      emit_insn (pat);
-      DONE;
-    }
-  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
-    {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
-      emit_insn (gen_sne (operands[0]));
-      DONE;
-    }      
-  else if (TARGET_V9)
-    {
-      if (gen_v9_scc (NE, operands))
-	DONE;
-      /* fall through */
-    }
-  FAIL;
-}")
-
-(define_expand "sgt"
-  [(set (match_operand:SI 0 "intreg_operand" "")
-	(gt:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "
-{
-  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
-    {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
-      emit_insn (gen_sne (operands[0]));
-      DONE;
-    }
-  else if (TARGET_V9)
-    {
-      if (gen_v9_scc (GT, operands))
-	DONE;
-      /* fall through */
-    }
-  FAIL;
-}")
-
-(define_expand "slt"
-  [(set (match_operand:SI 0 "intreg_operand" "")
-	(lt:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "
-{
-  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
-    {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
-      emit_insn (gen_sne (operands[0]));
-      DONE;
-    }
-  else if (TARGET_V9)
-    {
-      if (gen_v9_scc (LT, operands))
-	DONE;
-      /* fall through */
-    }
-  FAIL;
-}")
-
-(define_expand "sge"
-  [(set (match_operand:SI 0 "intreg_operand" "")
-	(ge:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "
-{
-  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
-    {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
-      emit_insn (gen_sne (operands[0]));
-      DONE;
-    }
-  else if (TARGET_V9)
-    {
-      if (gen_v9_scc (GE, operands))
-	DONE;
-      /* fall through */
-    }
-  FAIL;
-}")
-
-(define_expand "sle"
-  [(set (match_operand:SI 0 "intreg_operand" "")
-	(le:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "
-{
-  if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
-    {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
-      emit_insn (gen_sne (operands[0]));
-      DONE;
-    }
-  else if (TARGET_V9)
-    {
-      if (gen_v9_scc (LE, operands))
-	DONE;
-      /* fall through */
-    }
-  FAIL;
-}")
-
-(define_expand "sgtu"
-  [(set (match_operand:SI 0 "intreg_operand" "")
-	(gtu:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "
-{
-  if (! TARGET_V9)
-    {
-      rtx tem, pat;
-
-      /* We can do ltu easily, so if both operands are registers, swap them and
-	 do a LTU.  */
-      if ((GET_CODE (sparc_compare_op0) == REG
-	   || GET_CODE (sparc_compare_op0) == SUBREG)
-	  && (GET_CODE (sparc_compare_op1) == REG
-	      || GET_CODE (sparc_compare_op1) == SUBREG))
-	{
-	  tem = sparc_compare_op0;
-	  sparc_compare_op0 = sparc_compare_op1;
-	  sparc_compare_op1 = tem;
-	  pat = gen_sltu (operands[0]);
-          if (pat == NULL_RTX)
-            FAIL;
-          emit_insn (pat);
-	  DONE;
-	}
-    }
-  else
-    {
-      if (gen_v9_scc (GTU, operands))
-	DONE;
-    }
-  FAIL;
-}")
-
-(define_expand "sltu"
-  [(set (match_operand:SI 0 "intreg_operand" "")
-	(ltu:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "
-{
-  if (TARGET_V9)
-    {
-      if (gen_v9_scc (LTU, operands))
-	DONE;
-    }
-  operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
-}")
-
-(define_expand "sgeu"
-  [(set (match_operand:SI 0 "intreg_operand" "")
-	(geu:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "
-{
-  if (TARGET_V9)
-    {
-      if (gen_v9_scc (GEU, operands))
-	DONE;
-    }
-  operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
-}")
-
-(define_expand "sleu"
-  [(set (match_operand:SI 0 "intreg_operand" "")
-	(leu:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "
-{
-  if (! TARGET_V9)
-    {
-      rtx tem, pat;
-
-      /* We can do geu easily, so if both operands are registers, swap them and
-	 do a GEU.  */
-      if ((GET_CODE (sparc_compare_op0) == REG
-	   || GET_CODE (sparc_compare_op0) == SUBREG)
-	  && (GET_CODE (sparc_compare_op1) == REG
-	      || GET_CODE (sparc_compare_op1) == SUBREG))
-	{
-	  tem = sparc_compare_op0;
-	  sparc_compare_op0 = sparc_compare_op1;
-	  sparc_compare_op1 = tem;
-	  pat = gen_sgeu (operands[0]);
-          if (pat == NULL_RTX)
-            FAIL;
-          emit_insn (pat);
-	  DONE;
-	}
-    }
-  else
-    {
-      if (gen_v9_scc (LEU, operands))
-	DONE;
-    }
-  FAIL;
-}")
-
-;; Now the DEFINE_INSNs for the scc cases.
-
-;; The SEQ and SNE patterns are special because they can be done
-;; without any branching and do not involve a COMPARE.  We want
-;; them to always use the splitz below so the results can be
-;; scheduled.
-
-(define_insn "*snesi_zero"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ne:SI (match_operand:SI 1 "register_operand" "r")
-	       (const_int 0)))
-   (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
-  "#"
-  [(set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ne:SI (match_operand:SI 1 "register_operand" "")
-	       (const_int 0)))
-   (clobber (reg:CC 100))]
-  ""
-  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
-					   (const_int 0)))
-   (set (match_dup 0) (ltu:SI (reg:CC 100) (const_int 0)))]
-  "")
-
-(define_insn "*neg_snesi_zero"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
-		       (const_int 0))))
-   (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
-  "#"
-  [(set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(neg:SI (ne:SI (match_operand:SI 1 "register_operand" "")
-		       (const_int 0))))
-   (clobber (reg:CC 100))]
-  ""
-  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
-					   (const_int 0)))
-   (set (match_dup 0) (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
-  "")
-
-(define_insn "*snesi_zero_extend"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ne:DI (match_operand:SI 1 "register_operand" "r")
-	       (const_int 0)))
-   (clobber (reg:CC 100))]
-  "TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (ne:DI (match_operand:SI 1 "register_operand" "")
-               (const_int 0)))
-   (clobber (reg:CC 100))]
-  "TARGET_ARCH64"
-  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1))
-                                           (const_int 0)))
-   (set (match_dup 0) (zero_extend:DI (plus:SI (plus:SI (const_int 0)
-                                                        (const_int 0))
-                                               (ltu:SI (reg:CC_NOOV 100)
-                                                       (const_int 0)))))]
-  "")
-
-(define_insn "*snedi_zero"
-  [(set (match_operand:DI 0 "register_operand" "=&r")
-	(ne:DI (match_operand:DI 1 "register_operand" "r")
-	       (const_int 0)))]
-  "TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (ne:DI (match_operand:DI 1 "register_operand" "")
-               (const_int 0)))]
-  "TARGET_ARCH64"
-  [(set (match_dup 0) (const_int 0))
-   (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
-                                              (const_int 0))
-                                       (const_int 1)
-                                       (match_dup 0)))]
-  "")
-
-(define_insn "*neg_snedi_zero"
-  [(set (match_operand:DI 0 "register_operand" "=&r")
-	(neg:DI (ne:DI (match_operand:DI 1 "register_operand" "r")
-		       (const_int 0))))]
-  "TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "")
-                       (const_int 0))))]
-  "TARGET_ARCH64"
-  [(set (match_dup 0) (const_int 0))
-   (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
-                                              (const_int 0))
-                                       (const_int -1)
-                                       (match_dup 0)))]
-  "")
-
-(define_insn "*snedi_zero_trunc"
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(ne:SI (match_operand:DI 1 "register_operand" "r")
-	       (const_int 0)))]
-  "TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-        (ne:SI (match_operand:DI 1 "register_operand" "")
-               (const_int 0)))]
-  "TARGET_ARCH64"
-  [(set (match_dup 0) (const_int 0))
-   (set (match_dup 0) (if_then_else:SI (ne:DI (match_dup 1)
-                                              (const_int 0))
-                                       (const_int 1)
-                                       (match_dup 0)))]
-  "")
-
-(define_insn "*seqsi_zero"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (match_operand:SI 1 "register_operand" "r")
-	       (const_int 0)))
-   (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
-  "#"
-  [(set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(eq:SI (match_operand:SI 1 "register_operand" "")
-	       (const_int 0)))
-   (clobber (reg:CC 100))]
-  ""
-  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
-					   (const_int 0)))
-   (set (match_dup 0) (geu:SI (reg:CC 100) (const_int 0)))]
-  "")
-
-(define_insn "*neg_seqsi_zero"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
-		       (const_int 0))))
-   (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
-  "#"
-  [(set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(neg:SI (eq:SI (match_operand:SI 1 "register_operand" "")
-		       (const_int 0))))
-   (clobber (reg:CC 100))]
-  ""
-  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
-					   (const_int 0)))
-   (set (match_dup 0) (neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
-  "")
-
-(define_insn "*seqsi_zero_extend"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(eq:DI (match_operand:SI 1 "register_operand" "r")
-	       (const_int 0)))
-   (clobber (reg:CC 100))]
-  "TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (eq:DI (match_operand:SI 1 "register_operand" "")
-               (const_int 0)))
-   (clobber (reg:CC 100))]
-  "TARGET_ARCH64"
-  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1))
-                                           (const_int 0)))
-   (set (match_dup 0) (zero_extend:DI (minus:SI (minus:SI (const_int 0)
-                                                          (const_int -1))
-                                                (ltu:SI (reg:CC_NOOV 100)
-                                                        (const_int 0)))))]
-  "")
-
-(define_insn "*seqdi_zero"
-  [(set (match_operand:DI 0 "register_operand" "=&r")
-	(eq:DI (match_operand:DI 1 "register_operand" "r")
-	       (const_int 0)))]
-  "TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (eq:DI (match_operand:DI 1 "register_operand" "")
-               (const_int 0)))]
-  "TARGET_ARCH64"
-  [(set (match_dup 0) (const_int 0))
-   (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
-                                              (const_int 0))
-                                       (const_int 1)
-                                       (match_dup 0)))]
-  "")
-
-(define_insn "*neg_seqdi_zero"
-  [(set (match_operand:DI 0 "register_operand" "=&r")
-	(neg:DI (eq:DI (match_operand:DI 1 "register_operand" "r")
-		       (const_int 0))))]
-  "TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "2")]) 
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "")
-                       (const_int 0))))]
-  "TARGET_ARCH64"
-  [(set (match_dup 0) (const_int 0))
-   (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
-                                              (const_int 0))
-                                       (const_int -1)
-                                       (match_dup 0)))]
-  "")
-
-(define_insn "*seqdi_zero_trunc"
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(eq:SI (match_operand:DI 1 "register_operand" "r")
-	       (const_int 0)))]
-  "TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-        (eq:SI (match_operand:DI 1 "register_operand" "")
-               (const_int 0)))]
-  "TARGET_ARCH64"
-  [(set (match_dup 0) (const_int 0))
-   (set (match_dup 0) (if_then_else:SI (eq:DI (match_dup 1)
-                                              (const_int 0))
-                                       (const_int 1)
-                                       (match_dup 0)))]
-  "")
-
-;; We can also do (x + (i == 0)) and related, so put them in.
-;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
-;; versions for v9.
-
-(define_insn "*x_plus_i_ne_0"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
-			(const_int 0))
-		 (match_operand:SI 2 "register_operand" "r")))
-   (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
-  "#"
-  [(set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (ne:SI (match_operand:SI 1 "register_operand" "")
-			(const_int 0))
-		 (match_operand:SI 2 "register_operand" "")))
-   (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
-  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
-					   (const_int 0)))
-   (set (match_dup 0) (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
-			       (match_dup 2)))]
-  "")
-
-(define_insn "*x_minus_i_ne_0"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 2 "register_operand" "r")
-		  (ne:SI (match_operand:SI 1 "register_operand" "r")
-			 (const_int 0))))
-   (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
-  "#"
-  [(set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 2 "register_operand" "")
-		  (ne:SI (match_operand:SI 1 "register_operand" "")
-			 (const_int 0))))
-   (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
-  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
-					   (const_int 0)))
-   (set (match_dup 0) (minus:SI (match_dup 2)
-				(ltu:SI (reg:CC 100) (const_int 0))))]
-  "")
-
-(define_insn "*x_plus_i_eq_0"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
-			(const_int 0))
-		 (match_operand:SI 2 "register_operand" "r")))
-   (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
-  "#"
-  [(set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (eq:SI (match_operand:SI 1 "register_operand" "")
-			(const_int 0))
-		 (match_operand:SI 2 "register_operand" "")))
-   (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
-  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
-					   (const_int 0)))
-   (set (match_dup 0) (plus:SI (geu:SI (reg:CC 100) (const_int 0))
-			       (match_dup 2)))]
-  "")
-
-(define_insn "*x_minus_i_eq_0"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 2 "register_operand" "r")
-		  (eq:SI (match_operand:SI 1 "register_operand" "r")
-			 (const_int 0))))
-   (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
-  "#"
-  [(set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 2 "register_operand" "")
-		  (eq:SI (match_operand:SI 1 "register_operand" "")
-			 (const_int 0))))
-   (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
-  [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
-					   (const_int 0)))
-   (set (match_dup 0) (minus:SI (match_dup 2)
-				(geu:SI (reg:CC 100) (const_int 0))))]
-  "")
-
-;; We can also do GEU and LTU directly, but these operate after a compare.
-;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
-;; versions for v9.
-
-(define_insn "*sltu_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ltu:SI (reg:CC 100) (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "addx\\t%%g0, 0, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "*neg_sltu_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
-  "! TARGET_LIVE_G0"
-  "subx\\t%%g0, 0, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-;; ??? Combine should canonicalize these next two to the same pattern.
-(define_insn "*neg_sltu_minus_x"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (neg:SI (ltu:SI (reg:CC 100) (const_int 0)))
-		  (match_operand:SI 1 "arith_operand" "rI")))]
-  "! TARGET_LIVE_G0"
-  "subx\\t%%g0, %1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "*neg_sltu_plus_x"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
-			 (match_operand:SI 1 "arith_operand" "rI"))))]
-  "! TARGET_LIVE_G0"
-  "subx\\t%%g0, %1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "*sgeu_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(geu:SI (reg:CC 100) (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "subx\\t%%g0, -1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "*neg_sgeu_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
-  "! TARGET_LIVE_G0"
-  "addx\\t%%g0, -1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in.
-;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
-;; versions for v9.
-
-(define_insn "*sltu_plus_x"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (ltu:SI (reg:CC 100) (const_int 0))
-		 (match_operand:SI 1 "arith_operand" "rI")))]
-  "! TARGET_LIVE_G0"
-  "addx\\t%%g0, %1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "*sltu_plus_x_plus_y"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (ltu:SI (reg:CC 100) (const_int 0))
-		 (plus:SI (match_operand:SI 1 "arith_operand" "%r")
-			  (match_operand:SI 2 "arith_operand" "rI"))))]
-  ""
-  "addx\\t%1, %2, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "*x_minus_sltu"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (ltu:SI (reg:CC 100) (const_int 0))))]
-  ""
-  "subx\\t%1, 0, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-;; ??? Combine should canonicalize these next two to the same pattern.
-(define_insn "*x_minus_y_minus_sltu"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-			    (match_operand:SI 2 "arith_operand" "rI"))
-		  (ltu:SI (reg:CC 100) (const_int 0))))]
-  ""
-  "subx\\t%r1, %2, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "*x_minus_sltu_plus_y"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-		  (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
-			   (match_operand:SI 2 "arith_operand" "rI"))))]
-  ""
-  "subx\\t%r1, %2, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "*sgeu_plus_x"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (geu:SI (reg:CC 100) (const_int 0))
-		 (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "subx\\t%1, -1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "*x_minus_sgeu"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (geu:SI (reg:CC 100) (const_int 0))))]
-  ""
-  "addx\\t%1, -1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operator:SI 2 "noov_compare_op"
-			   [(match_operand 1 "icc_or_fcc_reg_operand" "")
-			    (const_int 0)]))]
-  ;; 32 bit LTU/GEU are better implemented using addx/subx
-  "TARGET_V9 && REGNO (operands[1]) == SPARC_ICC_REG
-   && (GET_MODE (operands[1]) == CCXmode
-       || (GET_CODE (operands[2]) != LTU && GET_CODE (operands[2]) != GEU))"
-  [(set (match_dup 0) (const_int 0))
-   (set (match_dup 0)
-	(if_then_else:SI (match_op_dup:SI 2 [(match_dup 1) (const_int 0)])
-			 (const_int 1)
-			 (match_dup 0)))]
-  "")
-
-
-;; These control RTL generation for conditional jump insns
-
-;; The quad-word fp compare library routines all return nonzero to indicate
-;; true, which is different from the equivalent libgcc routines, so we must
-;; handle them specially here.
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && GET_MODE (sparc_compare_op0) == DImode)
-    {
-      emit_v9_brxx_insn (EQ, sparc_compare_op0, operands[0]);
-      DONE;
-    }
-  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
-    {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
-      emit_jump_insn (gen_bne (operands[0]));
-      DONE;
-    }      
-  operands[1] = gen_compare_reg (EQ, sparc_compare_op0, sparc_compare_op1);
-}")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && GET_MODE (sparc_compare_op0) == DImode)
-    {
-      emit_v9_brxx_insn (NE, sparc_compare_op0, operands[0]);
-      DONE;
-    }
-  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
-    {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
-      emit_jump_insn (gen_bne (operands[0]));
-      DONE;
-    }      
-  operands[1] = gen_compare_reg (NE, sparc_compare_op0, sparc_compare_op1);
-}")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && GET_MODE (sparc_compare_op0) == DImode)
-    {
-      emit_v9_brxx_insn (GT, sparc_compare_op0, operands[0]);
-      DONE;
-    }
-  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
-    {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
-      emit_jump_insn (gen_bne (operands[0]));
-      DONE;
-    }      
-  operands[1] = gen_compare_reg (GT, sparc_compare_op0, sparc_compare_op1);
-}")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (GTU, sparc_compare_op0, sparc_compare_op1);
-}")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && GET_MODE (sparc_compare_op0) == DImode)
-    {
-      emit_v9_brxx_insn (LT, sparc_compare_op0, operands[0]);
-      DONE;
-    }
-  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
-    {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
-      emit_jump_insn (gen_bne (operands[0]));
-      DONE;
-    }      
-  operands[1] = gen_compare_reg (LT, sparc_compare_op0, sparc_compare_op1);
-}")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
-}")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && GET_MODE (sparc_compare_op0) == DImode)
-    {
-      emit_v9_brxx_insn (GE, sparc_compare_op0, operands[0]);
-      DONE;
-    }
-  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
-    {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
-      emit_jump_insn (gen_bne (operands[0]));
-      DONE;
-    }      
-  operands[1] = gen_compare_reg (GE, sparc_compare_op0, sparc_compare_op1);
-}")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
-}")
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{
-  if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && GET_MODE (sparc_compare_op0) == DImode)
-    {
-      emit_v9_brxx_insn (LE, sparc_compare_op0, operands[0]);
-      DONE;
-    }
-  else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
-    {
-      emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
-      emit_jump_insn (gen_bne (operands[0]));
-      DONE;
-    }      
-  operands[1] = gen_compare_reg (LE, sparc_compare_op0, sparc_compare_op1);
-}")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (match_dup 1) (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "
-{ operands[1] = gen_compare_reg (LEU, sparc_compare_op0, sparc_compare_op1);
-}")
-
-;; Now match both normal and inverted jump.
-
-;; XXX fpcmp nop braindamage
-(define_insn "*normal_branch"
-  [(set (pc)
-	(if_then_else (match_operator 0 "noov_compare_op"
-				      [(reg 100) (const_int 0)])
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  return output_cbranch (operands[0], 1, 0,
-			 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
-			 ! final_sequence, insn);
-}"
-  [(set_attr "type" "branch")])
-
-;; XXX fpcmp nop braindamage
-(define_insn "*inverted_branch"
-  [(set (pc)
-	(if_then_else (match_operator 0 "noov_compare_op"
-				      [(reg 100) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 1 "" ""))))]
-  ""
-  "*
-{
-  return output_cbranch (operands[0], 1, 1,
-			 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
-			 ! final_sequence, insn);
-}"
-  [(set_attr "type" "branch")])
-
-;; XXX fpcmp nop braindamage
-(define_insn "*normal_fp_branch"
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(match_operand:CCFP 0 "fcc_reg_operand" "c")
-				       (const_int 0)])
-		      (label_ref (match_operand 2 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  return output_cbranch (operands[1], 2, 0,
-			 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
-			 ! final_sequence, insn);
-}"
-  [(set_attr "type" "branch")])
-
-;; XXX fpcmp nop braindamage
-(define_insn "*inverted_fp_branch"
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(match_operand:CCFP 0 "fcc_reg_operand" "c")
-				       (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 2 "" ""))))]
-  ""
-  "*
-{
-  return output_cbranch (operands[1], 2, 1,
-			 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
-			 ! final_sequence, insn);
-}"
-  [(set_attr "type" "branch")])
-
-;; XXX fpcmp nop braindamage
-(define_insn "*normal_fpe_branch"
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(match_operand:CCFPE 0 "fcc_reg_operand" "c")
-				       (const_int 0)])
-		      (label_ref (match_operand 2 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  return output_cbranch (operands[1], 2, 0,
-			 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
-			 ! final_sequence, insn);
-}"
-  [(set_attr "type" "branch")])
-
-;; XXX fpcmp nop braindamage
-(define_insn "*inverted_fpe_branch"
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(match_operand:CCFPE 0 "fcc_reg_operand" "c")
-				       (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 2 "" ""))))]
-  ""
-  "*
-{
-  return output_cbranch (operands[1], 2, 1,
-			 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
-			 ! final_sequence, insn);
-}"
-  [(set_attr "type" "branch")])
-
-;; Sparc V9-specific jump insns.  None of these are guaranteed to be
-;; in the architecture.
-
-;; There are no 32 bit brreg insns.
-
-;; XXX
-(define_insn "*normal_int_branch_sp64"
-  [(set (pc)
-	(if_then_else (match_operator 0 "v9_regcmp_op"
-				      [(match_operand:DI 1 "register_operand" "r")
-				       (const_int 0)])
-		      (label_ref (match_operand 2 "" ""))
-		      (pc)))]
-  "TARGET_ARCH64"
-  "*
-{
-  return output_v9branch (operands[0], 1, 2, 0,
-			  final_sequence && INSN_ANNULLED_BRANCH_P (insn),
-			  ! final_sequence, insn);
-}"
-  [(set_attr "type" "branch")])
-
-;; XXX
-(define_insn "*inverted_int_branch_sp64"
-  [(set (pc)
-	(if_then_else (match_operator 0 "v9_regcmp_op"
-				      [(match_operand:DI 1 "register_operand" "r")
-				       (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 2 "" ""))))]
-  "TARGET_ARCH64"
-  "*
-{
-  return output_v9branch (operands[0], 1, 2, 1,
-			  final_sequence && INSN_ANNULLED_BRANCH_P (insn),
-			  ! final_sequence, insn);
-}"
-  [(set_attr "type" "branch")])
-
-;; Load program counter insns.
-
-(define_insn "get_pc"
-  [(clobber (reg:SI 15))
-   (set (match_operand 0 "register_operand" "=r")
-	(unspec [(match_operand 1 "" "") (match_operand 2 "" "")] 2))]
-  "flag_pic && REGNO (operands[0]) == 23"
-  "sethi\\t%%hi(%a1-4), %0\\n\\tcall\\t%a2\\n\\tadd\\t%0, %%lo(%a1+4), %0"
-  [(set_attr "length" "3")])
-
-;; Currently unused...
-;; (define_insn "get_pc_via_rdpc"
-;;   [(set (match_operand 0 "register_operand" "=r") (pc))]
-;;   "TARGET_V9"
-;;   "rd\\t%%pc, %0"
-;;   [(set_attr "type" "move")])
-
-
-;; Move instructions
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Working with CONST_INTs is easier, so convert
-     a double if needed.  */
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    {
-      operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xff);
-    }
-  else if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      /* And further, we know for all QI cases that only the
-	 low byte is significant, which we can always process
-	 in a single insn.  So mask it now.  */
-      operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
-    }
-
-  /* Handle sets of MEM first.  */
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      /* This checks TARGET_LIVE_G0 for us.  */
-      if (reg_or_0_operand (operands[1], QImode))
-	goto movqi_is_ok;
-
-      if (! reload_in_progress)
-	{
-	  operands[0] = validize_mem (operands[0]);
-	  operands[1] = force_reg (QImode, operands[1]);
-	}
-    }
-
-  /* Fixup PIC cases.  */
-  if (flag_pic)
-    {
-      if (CONSTANT_P (operands[1])
-	  && pic_address_needs_scratch (operands[1]))
-	operands[1] = legitimize_pic_address (operands[1], QImode, 0);
-
-      if (symbolic_operand (operands[1], QImode))
-	{
-	  operands[1] = legitimize_pic_address (operands[1],
-						QImode,
-						(reload_in_progress ?
-						 operands[0] :
-						 NULL_RTX));
-	  goto movqi_is_ok;
-	}
-    }
-
-  /* All QI constants require only one insn, so proceed.  */
-
- movqi_is_ok:
-  ;
-}")
-
-(define_insn "*movqi_insn"
-  [(set (match_operand:QI 0 "general_operand" "=r,r,m")
-	(match_operand:QI 1 "input_operand"   "rI,m,rJ"))]
-  "(register_operand (operands[0], QImode)
-    || reg_or_0_operand (operands[1], QImode))"
-  "@
-   mov\\t%1, %0
-   ldub\\t%1, %0
-   stb\\t%r1, %0"
-  [(set_attr "type" "move,load,store")
-   (set_attr "length" "1")])
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Working with CONST_INTs is easier, so convert
-     a double if needed.  */
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-
-  /* Handle sets of MEM first.  */
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      /* This checks TARGET_LIVE_G0 for us.  */
-      if (reg_or_0_operand (operands[1], HImode))
-	goto movhi_is_ok;
-
-      if (! reload_in_progress)
-	{
-	  operands[0] = validize_mem (operands[0]);
-	  operands[1] = force_reg (HImode, operands[1]);
-	}
-    }
-
-  /* Fixup PIC cases.  */
-  if (flag_pic)
-    {
-      if (CONSTANT_P (operands[1])
-	  && pic_address_needs_scratch (operands[1]))
-	operands[1] = legitimize_pic_address (operands[1], HImode, 0);
-
-      if (symbolic_operand (operands[1], HImode))
-	{
-	  operands[1] = legitimize_pic_address (operands[1],
-						HImode,
-						(reload_in_progress ?
-						 operands[0] :
-						 NULL_RTX));
-	  goto movhi_is_ok;
-	}
-    }
-
-  /* This makes sure we will not get rematched due to splittage. */
-  if (! CONSTANT_P (operands[1]) || input_operand (operands[1], HImode))
-    ;
-  else if (CONSTANT_P (operands[1])
-	   && GET_CODE (operands[1]) != HIGH
-	   && GET_CODE (operands[1]) != LO_SUM)
-    {
-      sparc_emit_set_const32 (operands[0], operands[1]);
-      DONE;
-    }
- movhi_is_ok:
-  ;
-}")
-
-(define_insn "*movhi_const64_special"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(match_operand:HI 1 "const64_high_operand" ""))]
-  "TARGET_ARCH64"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "*movhi_insn"
-  [(set (match_operand:HI 0 "general_operand" "=r,r,r,m")
-	(match_operand:HI 1 "input_operand"   "rI,K,m,rJ"))]
-  "(register_operand (operands[0], HImode)
-    || reg_or_0_operand (operands[1], HImode))"
-  "@
-   mov\\t%1, %0
-   sethi\\t%%hi(%a1), %0
-   lduh\\t%1, %0
-   sth\\t%r1, %0"
-  [(set_attr "type" "move,move,load,store")
-   (set_attr "length" "1")])
-
-;; We always work with constants here.
-(define_insn "*movhi_lo_sum"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(ior:HI (match_operand:HI 1 "arith_operand" "%r")
-                (match_operand:HI 2 "arith_operand" "I")))]
-  ""
-  "or\\t%1, %2, %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Working with CONST_INTs is easier, so convert
-     a double if needed.  */
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-
-  /* Handle sets of MEM first.  */
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      /* This checks TARGET_LIVE_G0 for us.  */
-      if (reg_or_0_operand (operands[1], SImode))
-	goto movsi_is_ok;
-
-      if (! reload_in_progress)
-	{
-	  operands[0] = validize_mem (operands[0]);
-	  operands[1] = force_reg (SImode, operands[1]);
-	}
-    }
-
-  /* Fixup PIC cases.  */
-  if (flag_pic)
-    {
-      if (CONSTANT_P (operands[1])
-	  && pic_address_needs_scratch (operands[1]))
-	operands[1] = legitimize_pic_address (operands[1], SImode, 0);
-
-      if (GET_CODE (operands[1]) == LABEL_REF)
-	{
-	  /* shit */
-	  emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
-	  DONE;
-	}
-
-      if (symbolic_operand (operands[1], SImode))
-	{
-	  operands[1] = legitimize_pic_address (operands[1],
-						SImode,
-						(reload_in_progress ?
-						 operands[0] :
-						 NULL_RTX));
-	  goto movsi_is_ok;
-	}
-    }
-
-  /* If we are trying to toss an integer constant into the
-     FPU registers, force it into memory.  */
-  if (GET_CODE (operands[0]) == REG
-      && REGNO (operands[0]) >= SPARC_FIRST_FP_REG
-      && REGNO (operands[0]) <= SPARC_LAST_V9_FP_REG
-      && CONSTANT_P (operands[1]))
-    operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
-						 operands[1]));
-
-  /* This makes sure we will not get rematched due to splittage. */
-  if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
-    ;
-  else if (CONSTANT_P (operands[1])
-	   && GET_CODE (operands[1]) != HIGH
-	   && GET_CODE (operands[1]) != LO_SUM)
-    {
-      sparc_emit_set_const32 (operands[0], operands[1]);
-      DONE;
-    }
- movsi_is_ok:
-  ;
-}")
-
-;; Special LIVE_G0 pattern to obtain zero in a register.
-(define_insn "*movsi_zero_liveg0"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (match_operand:SI 1 "zero_operand" "J"))]
-  "TARGET_LIVE_G0"
-  "and\\t%0, 0, %0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "1")])
-
-;; This is needed to show CSE exactly which bits are set
-;; in a 64-bit register by sethi instructions.
-(define_insn "*movsi_const64_special"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "const64_high_operand" ""))]
-  "TARGET_ARCH64"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "*movsi_insn"
-  [(set (match_operand:SI 0 "general_operand" "=r,f,r,r,r,f,m,m,d")
-	(match_operand:SI 1 "input_operand"   "rI,!f,K,J,m,!m,rJ,!f,J"))]
-  "(register_operand (operands[0], SImode)
-    || reg_or_0_operand (operands[1], SImode))"
-  "@
-   mov\\t%1, %0
-   fmovs\\t%1, %0
-   sethi\\t%%hi(%a1), %0
-   clr\\t%0
-   ld\\t%1, %0
-   ld\\t%1, %0
-   st\\t%r1, %0
-   st\\t%1, %0
-   fzeros\\t%0"
-  [(set_attr "type" "move,fpmove,move,move,load,fpload,store,fpstore,fpmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movsi_lo_sum"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-                   (match_operand:SI 2 "immediate_operand" "in")))]
-  ""
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_insn "*movsi_high"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(high:SI (match_operand:SI 1 "immediate_operand" "in")))]
-  ""
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC
-;; so that CSE won't optimize the address computation away.
-(define_insn "movsi_lo_sum_pic"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-                   (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))]
-  "flag_pic"
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_insn "movsi_high_pic"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (high:SI (unspec:SI [(match_operand 1 "" "")] 0)))]
-  "flag_pic && check_pic (1)"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_expand "movsi_pic_label_ref"
-  [(set (match_dup 3) (high:SI
-     (unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
-		 (match_dup 2)] 5)))
-   (set (match_dup 4) (lo_sum:SI (match_dup 3)
-     (unspec:SI [(match_dup 1) (match_dup 2)] 5)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_dup 5) (match_dup 4)))]
-  "flag_pic"
-  "
-{
-  current_function_uses_pic_offset_table = 1;
-  operands[2] = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
-  operands[3] = gen_reg_rtx (SImode);
-  operands[4] = gen_reg_rtx (SImode);
-  operands[5] = pic_offset_table_rtx;
-}")
-
-(define_insn "*movsi_high_pic_label_ref"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-      (high:SI
-        (unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
-		    (match_operand:SI 2 "" "")] 5)))]
-  "flag_pic"
-  "sethi\\t%%hi(%a2-(%a1-.)), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "*movsi_lo_sum_pic_label_ref"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-      (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-        (unspec:SI [(match_operand:SI 2 "label_ref_operand" "")
-		    (match_operand:SI 3 "" "")] 5)))]
-  "flag_pic"
-  "or\\t%1, %%lo(%a3-(%a2-.)), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Where possible, convert CONST_DOUBLE into a CONST_INT.  */
-  if (GET_CODE (operands[1]) == CONST_DOUBLE
-#if HOST_BITS_PER_WIDE_INT != 64
-      && ((CONST_DOUBLE_HIGH (operands[1]) == 0
-	   && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
-	  || (CONST_DOUBLE_HIGH (operands[1]) == 0xffffffff
-	      && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))
-#endif
-      )
-    operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-
-  /* Handle MEM cases first.  */
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      /* If it's a REG, we can always do it.
-	 The const zero case is more complex, on v9
-	 we can always perform it.  */
-      if (register_operand (operands[1], DImode)
-	  || (TARGET_ARCH64
-              && (operands[1] == const0_rtx)))
-        goto movdi_is_ok;
-
-      if (! reload_in_progress)
-	{
-	  operands[0] = validize_mem (operands[0]);
-	  operands[1] = force_reg (DImode, operands[1]);
-	}
-    }
-
-  if (flag_pic)
-    {
-      if (CONSTANT_P (operands[1])
-	  && pic_address_needs_scratch (operands[1]))
-	operands[1] = legitimize_pic_address (operands[1], DImode, 0);
-
-      if (GET_CODE (operands[1]) == LABEL_REF)
-        {
-          if (! TARGET_ARCH64)
-            abort ();
-          emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
-          DONE;
-        }
-
-      if (symbolic_operand (operands[1], DImode))
-	{
-	  operands[1] = legitimize_pic_address (operands[1],
-						DImode,
-						(reload_in_progress ?
-						 operands[0] :
-						 NULL_RTX));
-	  goto movdi_is_ok;
-	}
-    }
-
-  /* If we are trying to toss an integer constant into the
-     FPU registers, force it into memory.  */
-  if (GET_CODE (operands[0]) == REG
-      && REGNO (operands[0]) >= SPARC_FIRST_FP_REG
-      && REGNO (operands[0]) <= SPARC_LAST_V9_FP_REG
-      && CONSTANT_P (operands[1]))
-    operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
-						 operands[1]));
-
-  /* This makes sure we will not get rematched due to splittage. */
-  if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
-    ;
-  else if (TARGET_ARCH64
-	   && CONSTANT_P (operands[1])
-           && GET_CODE (operands[1]) != HIGH
-           && GET_CODE (operands[1]) != LO_SUM)
-    {
-      sparc_emit_set_const64 (operands[0], operands[1]);
-      DONE;
-    }
-
- movdi_is_ok:
-  ;
-}")
-
-;; Be careful, fmovd does not exist when !arch64.
-;; We match MEM moves directly when we have correct even
-;; numbered registers, but fall into splits otherwise.
-;; The constraint ordering here is really important to
-;; avoid insane problems in reload, especially for patterns
-;; of the form:
-;;
-;; (set (mem:DI (plus:SI (reg:SI 30 %fp)
-;;                       (const_int -5016)))
-;;      (reg:DI 2 %g2))
-;;
-(define_insn "*movdi_insn_sp32"
-  [(set (match_operand:DI 0 "general_operand" "=T,U,o,r,r,r,?T,?f,?f,?o,?f")
-        (match_operand:DI 1 "input_operand"    "U,T,r,o,i,r,f,T,o,f,f"))]
-  "! TARGET_ARCH64 &&
-   (register_operand (operands[0], DImode)
-    || register_operand (operands[1], DImode))"
-  "@
-   std\\t%1, %0
-   ldd\\t%1, %0
-   #
-   #
-   #
-   #
-   std\\t%1, %0
-   ldd\\t%1, %0
-   #
-   #
-   #"
-  [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*")
-   (set_attr "length" "1,1,2,2,2,2,1,1,2,2,2")])
-
-;; The following are generated by sparc_emit_set_const64
-(define_insn "*movdi_sp64_dbl"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (match_operand:DI 1 "const64_operand" ""))]
-  "(TARGET_ARCH64
-    && HOST_BITS_PER_WIDE_INT != 64)"
-  "mov\\t%1, %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-;; This is needed to show CSE exactly which bits are set
-;; in a 64-bit register by sethi instructions.
-(define_insn "*movdi_const64_special"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(match_operand:DI 1 "const64_high_operand" ""))]
-  "TARGET_ARCH64"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "*movdi_insn_sp64"
-  [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,m,?e,?e,?m,b")
-        (match_operand:DI 1 "input_operand"   "rI,K,J,m,rJ,e,m,e,J"))]
-  "TARGET_ARCH64 &&
-   (register_operand (operands[0], DImode)
-    || reg_or_0_operand (operands[1], DImode))"
-  "@
-   mov\\t%1, %0
-   sethi\\t%%hi(%a1), %0
-   clr\\t%0
-   ldx\\t%1, %0
-   stx\\t%r1, %0
-   fmovd\\t%1, %0
-   ldd\\t%1, %0
-   std\\t%1, %0
-   fzero\\t%0"
-  [(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore,fpmove")
-   (set_attr "length" "1")])
-
-(define_expand "movdi_pic_label_ref"
-  [(set (match_dup 3) (high:DI
-     (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
-                 (match_dup 2)] 5)))
-   (set (match_dup 4) (lo_sum:DI (match_dup 3)
-     (unspec:DI [(match_dup 1) (match_dup 2)] 5)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-        (minus:DI (match_dup 5) (match_dup 4)))]
-  "TARGET_ARCH64 && flag_pic"
-  "
-{
-  current_function_uses_pic_offset_table = 1;
-  operands[2] = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
-  operands[3] = gen_reg_rtx (DImode);
-  operands[4] = gen_reg_rtx (DImode);
-  operands[5] = pic_offset_table_rtx;
-}")
-
-(define_insn "*movdi_high_pic_label_ref"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI
-          (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
-                      (match_operand:DI 2 "" "")] 5)))]
-  "TARGET_ARCH64 && flag_pic"
-  "sethi\\t%%hi(%a2-(%a1-.)), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "*movdi_lo_sum_pic_label_ref"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-      (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-        (unspec:DI [(match_operand:DI 2 "label_ref_operand" "")
-                    (match_operand:DI 3 "" "")] 5)))]
-  "TARGET_ARCH64 && flag_pic"
-  "or\\t%1, %%lo(%a3-(%a2-.)), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-;; Sparc-v9 code model support insns.  See sparc_emit_set_symbolic_const64
-;; in sparc.c to see what is going on here... PIC stuff comes first.
-
-(define_insn "movdi_lo_sum_pic"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))]
-  "TARGET_ARCH64 && flag_pic"
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_insn "movdi_high_pic"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (unspec:DI [(match_operand 1 "" "")] 0)))]
-  "TARGET_ARCH64 && flag_pic && check_pic (1)"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "*sethi_di_medlow_embmedany_pic"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))]
-  "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
-  "sethi\\t%%lo(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "*sethi_di_medlow"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (match_operand:DI 1 "symbolic_operand" "")))]
-  "TARGET_CM_MEDLOW && check_pic (1)"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "*losum_di_medlow"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (match_operand:DI 2 "symbolic_operand" "")))]
-  "TARGET_CM_MEDLOW"
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_insn "seth44"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))]
-  "TARGET_CM_MEDMID"
-  "sethi\\t%%h44(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "setm44"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))]
-  "TARGET_CM_MEDMID"
-  "or\\t%1, %%m44(%a2), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "setl44"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (match_operand:DI 2 "symbolic_operand" "")))]
-  "TARGET_CM_MEDMID"
-  "or\\t%1, %%l44(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_insn "sethh"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))]
-  "TARGET_CM_MEDANY"
-  "sethi\\t%%hh(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "setlm"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))]
-  "TARGET_CM_MEDANY"
-  "sethi\\t%%lm(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "sethm"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))]
-  "TARGET_CM_MEDANY"
-  "or\\t%1, %%hm(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_insn "setlo"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (match_operand:DI 2 "symbolic_operand" "")))]
-  "TARGET_CM_MEDANY"
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_insn "embmedany_sethi"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] 11)))]
-  "TARGET_CM_EMBMEDANY && check_pic (1)"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "embmedany_losum"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (match_operand:DI 2 "data_segment_operand" "")))]
-  "TARGET_CM_EMBMEDANY"
-  "add\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_insn "embmedany_brsum"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 11))]
-  "TARGET_CM_EMBMEDANY"
-  "add\\t%1, %_, %0"
-  [(set_attr "length" "1")])
-
-(define_insn "embmedany_textuhi"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 13)))]
-  "TARGET_CM_EMBMEDANY && check_pic (1)"
-  "sethi\\t%%uhi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "embmedany_texthi"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 14)))]
-  "TARGET_CM_EMBMEDANY && check_pic (1)"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "embmedany_textulo"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))]
-  "TARGET_CM_EMBMEDANY"
-  "or\\t%1, %%ulo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_insn "embmedany_textlo"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-                   (match_operand:DI 2 "text_segment_operand" "")))]
-  "TARGET_CM_EMBMEDANY"
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-;; Now some patterns to help reload out a bit.
-(define_expand "reload_indi"
-  [(parallel [(match_operand:DI 0 "register_operand" "=r")
-              (match_operand:DI 1 "immediate_operand" "")
-              (match_operand:TI 2 "register_operand" "=&r")])]
-  "(TARGET_CM_MEDANY
-    || TARGET_CM_EMBMEDANY)
-   && ! flag_pic"
-  "
-{
-  sparc_emit_set_symbolic_const64 (operands[0], operands[1],
-                                   gen_rtx_REG (DImode, REGNO (operands[2])));
-  DONE;
-}")
-
-(define_expand "reload_outdi"
-  [(parallel [(match_operand:DI 0 "register_operand" "=r")
-              (match_operand:DI 1 "immediate_operand" "")
-              (match_operand:TI 2 "register_operand" "=&r")])]
-  "(TARGET_CM_MEDANY
-    || TARGET_CM_EMBMEDANY)
-   && ! flag_pic"
-  "
-{
-  sparc_emit_set_symbolic_const64 (operands[0], operands[1],
-                                   gen_rtx_REG (DImode, REGNO (operands[2])));
-  DONE;
-}")
-
-;; Split up putting CONSTs and REGs into DI regs when !arch64
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (match_operand:DI 1 "const_int_operand" ""))]
-  "! TARGET_ARCH64 && reload_completed"
-  [(clobber (const_int 0))]
-  "
-{
-  emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
-			(INTVAL (operands[1]) < 0) ?
-			constm1_rtx :
-			const0_rtx));
-  emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
-			operands[1]));
-  DONE;
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (match_operand:DI 1 "const_double_operand" ""))]
-  "! TARGET_ARCH64 && reload_completed"
-  [(clobber (const_int 0))]
-  "
-{
-  emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
-			GEN_INT (CONST_DOUBLE_HIGH (operands[1]))));
-
-  /* Slick... but this trick loses if this subreg constant part
-     can be done in one insn.  */
-  if (CONST_DOUBLE_LOW (operands[1]) == CONST_DOUBLE_HIGH (operands[1])
-      && !(SPARC_SETHI_P (CONST_DOUBLE_HIGH (operands[1]))
-	   || SPARC_SIMM13_P (CONST_DOUBLE_HIGH (operands[1]))))
-    {
-      emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
-			    gen_highpart (SImode, operands[0])));
-    }
-  else
-    {
-      emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
-			    GEN_INT (CONST_DOUBLE_LOW (operands[1]))));
-    }
-  DONE;
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (match_operand:DI 1 "register_operand" ""))]
-  "! TARGET_ARCH64 && reload_completed"
-  [(clobber (const_int 0))]
-  "
-{
-  rtx set_dest = operands[0];
-  rtx set_src = operands[1];
-  rtx dest1, dest2;
-  rtx src1, src2;
-
-  if (GET_CODE (set_dest) == SUBREG)
-    set_dest = alter_subreg (set_dest);
-  if (GET_CODE (set_src) == SUBREG)
-    set_src = alter_subreg (set_src);
-
-  dest1 = gen_highpart (SImode, set_dest);
-  dest2 = gen_lowpart (SImode, set_dest);
-  src1 = gen_highpart (SImode, set_src);
-  src2 = gen_lowpart (SImode, set_src);
-
-  /* Now emit using the real source and destination we found, swapping
-     the order if we detect overlap.  */
-  if (reg_overlap_mentioned_p (dest1, src2))
-    {
-      emit_insn (gen_movsi (dest2, src2));
-      emit_insn (gen_movsi (dest1, src1));
-    }
-  else
-    {
-      emit_insn (gen_movsi (dest1, src1));
-      emit_insn (gen_movsi (dest2, src2));
-    }
-  DONE;
-}")
-
-;; Now handle the cases of memory moves from/to non-even
-;; DI mode register pairs.
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (match_operand:DI 1 "memory_operand" ""))]
-  "(! TARGET_ARCH64
-    && reload_completed
-    && sparc_splitdi_legitimate (operands[0], operands[1]))"
-  [(clobber (const_int 0))]
-  "
-{
-  rtx word0 = change_address (operands[1], SImode, NULL_RTX);
-  rtx word1 = change_address (operands[1], SImode,
-			      plus_constant_for_output (XEXP (word0, 0), 4));
-  rtx high_part = gen_highpart (SImode, operands[0]);
-  rtx low_part = gen_lowpart (SImode, operands[0]);
-
-  if (reg_overlap_mentioned_p (high_part, word1))
-    {
-      emit_insn (gen_movsi (low_part, word1));
-      emit_insn (gen_movsi (high_part, word0));
-    }
-  else
-    {
-      emit_insn (gen_movsi (high_part, word0));
-      emit_insn (gen_movsi (low_part, word1));
-    }
-  DONE;
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "memory_operand" "")
-        (match_operand:DI 1 "register_operand" ""))]
-  "(! TARGET_ARCH64
-    && reload_completed
-    && sparc_splitdi_legitimate (operands[1], operands[0]))"
-  [(clobber (const_int 0))]
-  "
-{
-  rtx word0 = change_address (operands[0], SImode, NULL_RTX);
-  rtx word1 = change_address (operands[0], SImode,
-			      plus_constant_for_output (XEXP (word0, 0), 4));
-  rtx high_part = gen_highpart (SImode, operands[1]);
-  rtx low_part = gen_lowpart (SImode, operands[1]);
-
-  emit_insn (gen_movsi (word0, high_part));
-  emit_insn (gen_movsi (word1, low_part));
-  DONE;
-}")
-
-
-;; Floating point move insns
-
-(define_insn "*clear_sf"
-  [(set (match_operand:SF 0 "general_operand" "=f")
-        (match_operand:SF 1 "" ""))]
-  "TARGET_VIS
-   && GET_CODE (operands[1]) == CONST_DOUBLE
-   && GET_CODE (operands[0]) == REG
-   && fp_zero_operand (operands[1])"
-  "fzeros\\t%0"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movsf_const_intreg"
-  [(set (match_operand:SF 0 "general_operand" "=f,r")
-        (match_operand:SF 1 ""                 "m,F"))]
-  "TARGET_FPU
-   && GET_CODE (operands[1]) == CONST_DOUBLE
-   && GET_CODE (operands[0]) == REG"
-  "*
-{
-  REAL_VALUE_TYPE r;
-  long i;
-
-  if (which_alternative == 0)
-    return \"ld\\t%1, %0\";
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
-  REAL_VALUE_TO_TARGET_SINGLE (r, i);
-  if (SPARC_SIMM13_P (i) || SPARC_SETHI_P (i))
-    {
-      operands[1] = GEN_INT (i);
-      if (SPARC_SIMM13_P (INTVAL (operands[1])))
-        return \"mov\\t%1, %0\";
-      else if (SPARC_SETHI_P (INTVAL (operands[1])))
-        return \"sethi\\t%%hi(%a1), %0\";
-      else
-        abort ();
-    }
-  else
-    return \"#\";
-}"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-;; There isn't much I can do about this, if I change the
-;; mode then flow info gets really confused because the
-;; destination no longer looks the same.  Ho hum...
-(define_insn "*movsf_const_high"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-        (unspec:SF [(match_operand 1 "const_int_operand" "")] 12))]
-  ""
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_insn "*movsf_const_lo"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-        (unspec:SF [(match_operand 1 "register_operand" "r")
-                    (match_operand 2 "const_int_operand" "")] 17))]
-  ""
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "")
-        (match_operand:SF 1 "const_double_operand" ""))]
-  "TARGET_FPU
-   && (GET_CODE (operands[0]) == REG
-       && REGNO (operands[0]) < 32)"
-  [(set (match_dup 0) (unspec:SF [(match_dup 1)] 12))
-   (set (match_dup 0) (unspec:SF [(match_dup 0) (match_dup 1)] 17))]
-  "
-{
-  REAL_VALUE_TYPE r;
-  long i;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
-  REAL_VALUE_TO_TARGET_SINGLE (r, i);
-  operands[1] = GEN_INT (i);
-}")
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Force SFmode constants into memory.  */
-  if (GET_CODE (operands[0]) == REG
-      && CONSTANT_P (operands[1]))
-    {
-      if (TARGET_VIS
-          && GET_CODE (operands[1]) == CONST_DOUBLE
-	  && fp_zero_operand (operands[1]))
-	goto movsf_is_ok;
-
-      /* emit_group_store will send such bogosity to us when it is
-         not storing directly into memory.  So fix this up to avoid
-         crashes in output_constant_pool.  */
-      if (operands [1] == const0_rtx)
-        operands[1] = CONST0_RTX (SFmode);
-      operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
-                                                   operands[1]));
-    }
-
-  /* Handle sets of MEM first.  */
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (register_operand (operands[1], SFmode))
-	goto movsf_is_ok;
-
-      if (! reload_in_progress)
-	{
-	  operands[0] = validize_mem (operands[0]);
-	  operands[1] = force_reg (SFmode, operands[1]);
-	}
-    }
-
-  /* Fixup PIC cases.  */
-  if (flag_pic)
-    {
-      if (CONSTANT_P (operands[1])
-	  && pic_address_needs_scratch (operands[1]))
-	operands[1] = legitimize_pic_address (operands[1], SFmode, 0);
-
-      if (symbolic_operand (operands[1], SFmode))
-	{
-	  operands[1] = legitimize_pic_address (operands[1],
-						SFmode,
-						(reload_in_progress ?
-						 operands[0] :
-						 NULL_RTX));
-	}
-    }
-
- movsf_is_ok:
-  ;
-}")
-
-(define_insn "*movsf_insn"
-  [(set (match_operand:SF 0 "general_operand" "=f,f,m,r,r,m")
-	(match_operand:SF 1 "input_operand"    "f,m,f,r,m,r"))]
-  "TARGET_FPU
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode))"
-  "@
-   fmovs\\t%1, %0
-   ld\\t%1, %0
-   st\\t%1, %0
-   mov\\t%1, %0
-   ld\\t%1, %0
-   st\\t%1, %0"
-  [(set_attr "type" "fpmove,fpload,fpstore,move,load,store")
-   (set_attr "length" "1")])
-
-;; Exactly the same as above, except that all `f' cases are deleted.
-;; This is necessary to prevent reload from ever trying to use a `f' reg
-;; when -mno-fpu.
-
-(define_insn "*movsf_no_f_insn"
-  [(set (match_operand:SF 0 "general_operand" "=r,r,m")
-	(match_operand:SF 1 "input_operand"    "r,m,r"))]
-  "! TARGET_FPU
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode))"
-  "@
-   mov\\t%1, %0
-   ld\\t%1, %0
-   st\\t%1, %0"
-  [(set_attr "type" "move,load,store")
-   (set_attr "length" "1")])
-
-(define_insn "*clear_df"
-  [(set (match_operand:DF 0 "general_operand" "=e")
-        (match_operand:DF 1 "" ""))]
-  "TARGET_VIS
-   && GET_CODE (operands[1]) == CONST_DOUBLE
-   && GET_CODE (operands[0]) == REG
-   && fp_zero_operand (operands[1])"
-  "fzero\\t%0"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movdf_const_intreg_sp32"
-  [(set (match_operand:DF 0 "general_operand" "=e,e,r")
-        (match_operand:DF 1 ""                 "T,o,F"))]
-  "TARGET_FPU && ! TARGET_ARCH64
-   && GET_CODE (operands[1]) == CONST_DOUBLE
-   && GET_CODE (operands[0]) == REG"
-  "*
-{
-  if (which_alternative == 0)
-    return \"ldd\\t%1, %0\";
-  else
-    return \"#\";
-}"
-  [(set_attr "type" "move")
-   (set_attr "length" "1,2,2")])
-
-;; Now that we redo life analysis with a clean slate after
-;; instruction splitting for sched2 this can work.
-(define_insn "*movdf_const_intreg_sp64"
-  [(set (match_operand:DF 0 "general_operand" "=e,e,r")
-        (match_operand:DF 1 ""                 "m,o,F"))]
-  "TARGET_FPU
-   && TARGET_ARCH64
-   && GET_CODE (operands[1]) == CONST_DOUBLE
-   && GET_CODE (operands[0]) == REG"
-  "*
-{
-  if (which_alternative == 0)
-    return \"ldd\\t%1, %0\";
-  else
-    return \"#\";
-}"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-        (match_operand:DF 1 "const_double_operand" ""))]
-  "TARGET_FPU
-   && GET_CODE (operands[1]) == CONST_DOUBLE
-   && (GET_CODE (operands[0]) == REG
-       && REGNO (operands[0]) < 32)
-   && reload_completed"
-  [(clobber (const_int 0))]
-  "
-{
-  REAL_VALUE_TYPE r;
-  long l[2];
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
-  REAL_VALUE_TO_TARGET_DOUBLE (r, l);
-  if (GET_CODE (operands[0]) == SUBREG)
-    operands[0] = alter_subreg (operands[0]);
-  operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0]));
-
-  if (TARGET_ARCH64)
-    {
-#if HOST_BITS_PER_WIDE_INT == 64
-      HOST_WIDE_INT val;
-
-      val = ((HOST_WIDE_INT)l[1] |
-             ((HOST_WIDE_INT)l[0] << 32));
-      emit_insn (gen_movdi (operands[0], GEN_INT (val)));
-#else
-      emit_insn (gen_movdi (operands[0],
-                            gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx,
-                                                  l[1], l[0])));
-#endif
-    }
-  else
-    {
-      emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
-			    GEN_INT (l[0])));
-
-      /* Slick... but this trick loses if this subreg constant part
-         can be done in one insn.  */
-      if (l[1] == l[0]
-          && !(SPARC_SETHI_P (l[0])
-	       || SPARC_SIMM13_P (l[0])))
-        {
-          emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
-			        gen_highpart (SImode, operands[0])));
-        }
-      else
-        {
-          emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
-			        GEN_INT (l[1])));
-        }
-    }
-  DONE;
-}")
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Force DFmode constants into memory.  */
-  if (GET_CODE (operands[0]) == REG
-      && CONSTANT_P (operands[1]))
-    {
-      if (TARGET_VIS
-          && GET_CODE (operands[1]) == CONST_DOUBLE
-	  && fp_zero_operand (operands[1]))
-	goto movdf_is_ok;
-
-      /* emit_group_store will send such bogosity to us when it is
-         not storing directly into memory.  So fix this up to avoid
-         crashes in output_constant_pool.  */
-      if (operands [1] == const0_rtx)
-        operands[1] = CONST0_RTX (DFmode);
-      operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
-                                                   operands[1]));
-    }
-
-  /* Handle MEM cases first.  */
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (register_operand (operands[1], DFmode))
-	goto movdf_is_ok;
-
-      if (! reload_in_progress)
-	{
-	  operands[0] = validize_mem (operands[0]);
-	  operands[1] = force_reg (DFmode, operands[1]);
-	}
-    }
-
-  /* Fixup PIC cases.  */
-  if (flag_pic)
-    {
-      if (CONSTANT_P (operands[1])
-	  && pic_address_needs_scratch (operands[1]))
-	operands[1] = legitimize_pic_address (operands[1], DFmode, 0);
-
-      if (symbolic_operand (operands[1], DFmode))
-	{
-	  operands[1] = legitimize_pic_address (operands[1],
-						DFmode,
-						(reload_in_progress ?
-						 operands[0] :
-						 NULL_RTX));
-	}
-    }
-
- movdf_is_ok:
-  ;
-}")
-
-;; Be careful, fmovd does not exist when !v9.
-(define_insn "*movdf_insn_sp32"
-  [(set (match_operand:DF 0 "general_operand" "=e,T,U,T,e,r,r,o,e,o")
-	(match_operand:DF 1 "input_operand"    "T,e,T,U,e,r,o,r,o,e"))]
-  "TARGET_FPU
-   && ! TARGET_V9
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
-  "@
-  ldd\\t%1, %0
-  std\\t%1, %0
-  ldd\\t%1, %0
-  std\\t%1, %0
-  #
-  #
-  #
-  #
-  #
-  #"
- [(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*")
-  (set_attr "length" "1,1,1,1,2,2,2,2,2,2")])
-
-(define_insn "*movdf_no_e_insn_sp32"
-  [(set (match_operand:DF 0 "general_operand" "=U,T,r,r,o")
-	(match_operand:DF 1 "input_operand"    "T,U,r,o,r"))]
-  "! TARGET_FPU
-   && ! TARGET_ARCH64
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
-  "@
-  ldd\\t%1, %0
-  std\\t%1, %0
-  #
-  #
-  #"
-  [(set_attr "type" "load,store,*,*,*")
-   (set_attr "length" "1,1,2,2,2")])
-
-;; We have available v9 double floats but not 64-bit
-;; integer registers.
-(define_insn "*movdf_insn_v9only"
-  [(set (match_operand:DF 0 "general_operand" "=e,e,m,U,T,r,r,o")
-        (match_operand:DF 1 "input_operand"    "e,m,e,T,U,r,o,r"))]
-  "TARGET_FPU
-   && TARGET_V9
-   && ! TARGET_ARCH64
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
-  "@
-  fmovd\\t%1, %0
-  ldd\\t%1, %0
-  std\\t%1, %0
-  ldd\\t%1, %0
-  std\\t%1, %0
-  #
-  #
-  #"
-  [(set_attr "type" "fpmove,load,store,load,store,*,*,*")
-   (set_attr "length" "1,1,1,1,1,2,2,2")])
-
-;; We have available both v9 double floats and 64-bit
-;; integer registers.
-(define_insn "*movdf_insn_sp64"
-  [(set (match_operand:DF 0 "general_operand" "=e,e,m,r,r,m")
-        (match_operand:DF 1 "input_operand"    "e,m,e,r,m,r"))]
-  "TARGET_FPU
-   && TARGET_V9
-   && TARGET_ARCH64
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
-  "@
-  fmovd\\t%1, %0
-  ldd\\t%1, %0
-  std\\t%1, %0
-  mov\\t%1, %0
-  ldx\\t%1, %0
-  stx\\t%1, %0"
-  [(set_attr "type" "fpmove,load,store,move,load,store")
-   (set_attr "length" "1")])
-
-(define_insn "*movdf_no_e_insn_sp64"
-  [(set (match_operand:DF 0 "general_operand" "=r,r,m")
-        (match_operand:DF 1 "input_operand"    "r,m,r"))]
-  "! TARGET_FPU
-   && TARGET_ARCH64
-   && (register_operand (operands[0], DFmode)
-       || register_operand (operands[1], DFmode))"
-  "@
-  mov\\t%1, %0
-  ldx\\t%1, %0
-  stx\\t%1, %0"
-  [(set_attr "type" "move,load,store")
-   (set_attr "length" "1")])
-
-;; Ok, now the splits to handle all the multi insn and
-;; mis-aligned memory address cases.
-;; In these splits please take note that we must be
-;; careful when V9 but not ARCH64 because the integer
-;; register DFmode cases must be handled.
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-        (match_operand:DF 1 "register_operand" ""))]
-  "(! TARGET_V9
-    || (! TARGET_ARCH64
-        && ((GET_CODE (operands[0]) == REG
-             && REGNO (operands[0]) < 32)
-            || (GET_CODE (operands[0]) == SUBREG
-                && GET_CODE (SUBREG_REG (operands[0])) == REG
-                && REGNO (SUBREG_REG (operands[0])) < 32))))
-   && reload_completed"
-  [(clobber (const_int 0))]
-  "
-{
-  rtx set_dest = operands[0];
-  rtx set_src = operands[1];
-  rtx dest1, dest2;
-  rtx src1, src2;
-
-  if (GET_CODE (set_dest) == SUBREG)
-    set_dest = alter_subreg (set_dest);
-  if (GET_CODE (set_src) == SUBREG)
-    set_src = alter_subreg (set_src);
-
-  dest1 = gen_highpart (SFmode, set_dest);
-  dest2 = gen_lowpart (SFmode, set_dest);
-  src1 = gen_highpart (SFmode, set_src);
-  src2 = gen_lowpart (SFmode, set_src);
-
-  /* Now emit using the real source and destination we found, swapping
-     the order if we detect overlap.  */
-  if (reg_overlap_mentioned_p (dest1, src2))
-    {
-      emit_insn (gen_movsf (dest2, src2));
-      emit_insn (gen_movsf (dest1, src1));
-    }
-  else
-    {
-      emit_insn (gen_movsf (dest1, src1));
-      emit_insn (gen_movsf (dest2, src2));
-    }
-  DONE;
-}")
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-	(match_operand:DF 1 "memory_operand" ""))]
-  "((! TARGET_V9
-     || (! TARGET_ARCH64
-         && ((GET_CODE (operands[0]) == REG
-              && REGNO (operands[0]) < 32)
-             || (GET_CODE (operands[0]) == SUBREG
-                 && GET_CODE (SUBREG_REG (operands[0])) == REG
-                 && REGNO (SUBREG_REG (operands[0])) < 32))))
-    && (reload_completed
-        && (((REGNO (operands[0])) % 2) != 0
-             || ! mem_min_alignment (operands[1], 8))
-        && offsettable_memref_p (operands[1])))"
-  [(clobber (const_int 0))]
-  "
-{
-  rtx word0 = change_address (operands[1], SFmode, NULL_RTX);
-  rtx word1 = change_address (operands[1], SFmode,
-			      plus_constant_for_output (XEXP (word0, 0), 4));
-  rtx src1, src2;
-
-  if (GET_CODE (operands[0]) == SUBREG)
-    operands[0] = alter_subreg (operands[0]);
-
-  if (GET_CODE (operands[0]) == REG)
-    {
-      src1 = gen_rtx_REG (SFmode, REGNO (operands[0]));
-      src2 = gen_rtx_REG (SFmode, REGNO (operands[0]) + 1);
-    }
-  else
-    {
-      src1 = gen_highpart (SFmode, operands[0]);
-      src2 = gen_lowpart (SFmode, operands[0]);
-    }
-
-  if (reg_overlap_mentioned_p (src1, word1))
-    {
-      emit_insn (gen_movsf (src2, word1));
-      emit_insn (gen_movsf (src1, word0));
-    }
-  else
-    {
-      emit_insn (gen_movsf (src1, word0));
-      emit_insn (gen_movsf (src2, word1));
-    }
-  DONE;
-}")
-
-(define_split
-  [(set (match_operand:DF 0 "memory_operand" "")
-	(match_operand:DF 1 "register_operand" ""))]
-  "((! TARGET_V9
-     || (! TARGET_ARCH64
-         && ((GET_CODE (operands[1]) == REG
-              && REGNO (operands[1]) < 32)
-             || (GET_CODE (operands[1]) == SUBREG
-                 && GET_CODE (SUBREG_REG (operands[1])) == REG
-                 && REGNO (SUBREG_REG (operands[1])) < 32))))
-    && (reload_completed
-        && (((REGNO (operands[1])) % 2) != 0
-             || ! mem_min_alignment (operands[0], 8))
-        && offsettable_memref_p (operands[0])))"
-  [(clobber (const_int 0))]
-  "
-{
-  rtx word0 = change_address (operands[0], SFmode, NULL_RTX);
-  rtx word1 = change_address (operands[0], SFmode,
-			      plus_constant_for_output (XEXP (word0, 0), 4));
-  rtx dest1, dest2;
-
-  if (GET_CODE (operands[1]) == SUBREG)
-    operands[1] = alter_subreg (operands[1]);
-
-  if (GET_CODE (operands[1]) == REG)
-    {
-      dest1 = gen_rtx_REG (SFmode, REGNO (operands[1]));
-      dest2 = gen_rtx_REG (SFmode, REGNO (operands[1]) + 1);
-    }
-  else
-    {
-      dest1 = gen_highpart (SFmode, operands[1]);
-      dest2 = gen_lowpart (SFmode, operands[1]);
-    }
-
-  emit_insn (gen_movsf (word0, dest1));
-  emit_insn (gen_movsf (word1, dest2));
-  DONE;
-}")
-
-(define_expand "movtf"
-  [(set (match_operand:TF 0 "general_operand" "")
-	(match_operand:TF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* Force TFmode constants into memory. */
-  if (GET_CODE (operands[0]) == REG
-      && CONSTANT_P (operands[1]))
-    {
-      /* emit_group_store will send such bogosity to us when it is
-         not storing directly into memory.  So fix this up to avoid
-         crashes in output_constant_pool.  */
-      if (operands [1] == const0_rtx)
-        operands[1] = CONST0_RTX (TFmode);
-      operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
-                                                   operands[1]));
-    }
-
-  /* Handle MEM cases first, note that only v9 guarentees
-     full 16-byte alignment for quads. */
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      if (register_operand (operands[1], TFmode))
-        goto movtf_is_ok;
-
-      if (! reload_in_progress)
-	{
-	  operands[0] = validize_mem (operands[0]);
-	  operands[1] = force_reg (TFmode, operands[1]);
-	}
-    }
-
-  /* Fixup PIC cases.  */
-  if (flag_pic)
-    {
-      if (CONSTANT_P (operands[1])
-	  && pic_address_needs_scratch (operands[1]))
-	operands[1] = legitimize_pic_address (operands[1], TFmode, 0);
-
-      if (symbolic_operand (operands[1], TFmode))
-	{
-	  operands[1] = legitimize_pic_address (operands[1],
-						TFmode,
-						(reload_in_progress ?
-						 operands[0] :
-						 NULL_RTX));
-	}
-    }
-
- movtf_is_ok:
-  ;
-}")
-
-;; Be careful, fmovq and {st,ld}{x,q} do not exist when !arch64 so
-;; we must split them all.  :-(
-(define_insn "*movtf_insn_sp32"
-  [(set (match_operand:TF 0 "general_operand" "=e,o,U,o,e,r,r,o")
-	(match_operand:TF 1 "input_operand"    "o,e,o,U,e,r,o,r"))]
-  "TARGET_FPU
-   && ! TARGET_ARCH64
-   && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode))"
-  "#"
-  [(set_attr "length" "4")])
-
-;; Exactly the same as above, except that all `e' cases are deleted.
-;; This is necessary to prevent reload from ever trying to use a `e' reg
-;; when -mno-fpu.
-
-(define_insn "*movtf_no_e_insn_sp32"
-  [(set (match_operand:TF 0 "general_operand" "=U,o,r,r,o")
-	(match_operand:TF 1 "input_operand"    "o,U,r,o,r"))]
-  "! TARGET_FPU
-   && ! TARGET_ARCH64
-   && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode))"
-  "#"
-  [(set_attr "length" "4")])
-
-;; Now handle the float reg cases directly when arch64,
-;; hard_quad, and proper reg number alignment are all true.
-(define_insn "*movtf_insn_hq_sp64"
-  [(set (match_operand:TF 0 "general_operand" "=e,e,m,r,r,o")
-        (match_operand:TF 1 "input_operand"    "e,m,e,r,o,r"))]
-  "TARGET_FPU
-   && TARGET_ARCH64
-   && TARGET_V9
-   && TARGET_HARD_QUAD
-   && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode))"
-  "@
-  fmovq\\t%1, %0
-  ldq\\t%1, %0
-  stq\\t%1, %0
-  #
-  #
-  #"
-  [(set_attr "type" "fpmove,fpload,fpstore,*,*,*")
-   (set_attr "length" "1,1,1,2,2,2")])
-
-;; Now we allow the integer register cases even when
-;; only arch64 is true.
-(define_insn "*movtf_insn_sp64"
-  [(set (match_operand:TF 0 "general_operand" "=e,o,r,o,e,r")
-        (match_operand:TF 1 "input_operand"    "o,e,o,r,e,r"))]
-  "TARGET_FPU
-   && TARGET_ARCH64
-   && ! TARGET_HARD_QUAD
-   && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode))"
-  "#"
-  [(set_attr "length" "2")])
-
-(define_insn "*movtf_no_e_insn_sp64"
-  [(set (match_operand:TF 0 "general_operand" "=r,o,r")
-        (match_operand:TF 1 "input_operand"    "o,r,r"))]
-  "! TARGET_FPU
-   && TARGET_ARCH64
-   && (register_operand (operands[0], TFmode)
-       || register_operand (operands[1], TFmode))"
-  "#"
-  [(set_attr "length" "2")])
-
-;; Now all the splits to handle multi-insn TF mode moves.
-(define_split
-  [(set (match_operand:TF 0 "register_operand" "")
-        (match_operand:TF 1 "register_operand" ""))]
-  "reload_completed
-   && (! TARGET_ARCH64
-       || (TARGET_FPU
-           && ! TARGET_HARD_QUAD))"
-  [(clobber (const_int 0))]
-  "
-{
-  rtx set_dest = operands[0];
-  rtx set_src = operands[1];
-  rtx dest1, dest2;
-  rtx src1, src2;
-
-  if (GET_CODE (set_dest) == SUBREG)
-    set_dest = alter_subreg (set_dest);
-  if (GET_CODE (set_src) == SUBREG)
-    set_src = alter_subreg (set_src);
-
-  /* Ugly, but gen_highpart will crap out here for 32-bit targets.  */
-  dest1 = gen_rtx_SUBREG (DFmode, set_dest, WORDS_BIG_ENDIAN == 0);
-  dest2 = gen_rtx_SUBREG (DFmode, set_dest, WORDS_BIG_ENDIAN != 0);
-  src1 = gen_rtx_SUBREG (DFmode, set_src, WORDS_BIG_ENDIAN == 0);
-  src2 = gen_rtx_SUBREG (DFmode, set_src, WORDS_BIG_ENDIAN != 0);
-
-  /* Now emit using the real source and destination we found, swapping
-     the order if we detect overlap.  */
-  if (reg_overlap_mentioned_p (dest1, src2))
-    {
-      emit_insn (gen_movdf (dest2, src2));
-      emit_insn (gen_movdf (dest1, src1));
-    }
-  else
-    {
-      emit_insn (gen_movdf (dest1, src1));
-      emit_insn (gen_movdf (dest2, src2));
-    }
-  DONE;
-}")
-
-(define_split
-  [(set (match_operand:TF 0 "register_operand" "")
-        (match_operand:TF 1 "memory_operand" ""))]
-  "(reload_completed
-    && offsettable_memref_p (operands[1]))"
-  [(clobber (const_int 0))]
-  "
-{
-  rtx word0 = change_address (operands[1], DFmode, NULL_RTX);
-  rtx word1 = change_address (operands[1], DFmode,
-			      plus_constant_for_output (XEXP (word0, 0), 8));
-  rtx dest1, dest2;
-
-  /* Ugly, but gen_highpart will crap out here for 32-bit targets.  */
-  dest1 = gen_rtx_SUBREG (DFmode, operands[0], WORDS_BIG_ENDIAN == 0);
-  dest2 = gen_rtx_SUBREG (DFmode, operands[0], WORDS_BIG_ENDIAN != 0);
-
-  /* Now output, ordering such that we don't clobber any registers
-     mentioned in the address.  */
-  if (reg_overlap_mentioned_p (dest1, word1))
-
-    {
-      emit_insn (gen_movdf (dest2, word1));
-      emit_insn (gen_movdf (dest1, word0));
-    }
-  else
-   {
-      emit_insn (gen_movdf (dest1, word0));
-      emit_insn (gen_movdf (dest2, word1));
-   }
-  DONE;
-}")
-
-(define_split
-  [(set (match_operand:TF 0 "memory_operand" "")
-	(match_operand:TF 1 "register_operand" ""))]
-  "(reload_completed
-    && offsettable_memref_p (operands[0]))"
-  [(clobber (const_int 0))]
-  "
-{
-  rtx word0 = change_address (operands[0], DFmode, NULL_RTX);
-  rtx word1 = change_address (operands[0], DFmode,
-			      plus_constant_for_output (XEXP (word0, 0), 8));
-  rtx src1, src2;
-
-  /* Ugly, but gen_highpart will crap out here for 32-bit targets.  */
-  src1 = gen_rtx_SUBREG (DFmode, operands[1], WORDS_BIG_ENDIAN == 0);
-  src2 = gen_rtx_SUBREG (DFmode, operands[1], WORDS_BIG_ENDIAN != 0);
-  emit_insn (gen_movdf (word0, src1));
-  emit_insn (gen_movdf (word1, src2));
-  DONE;
-}")
-
-;; Sparc V9 conditional move instructions.
-
-;; We can handle larger constants here for some flavors, but for now we keep
-;; it simple and only allow those constants supported by all flavours.
-;; Note that emit_conditional_move canonicalizes operands 2,3 so that operand
-;; 3 contains the constant if one is present, but we handle either for
-;; generality (sparc.c puts a constant in operand 2).
-
-(define_expand "movqicc"
-  [(set (match_operand:QI 0 "register_operand" "")
-	(if_then_else:QI (match_operand 1 "comparison_operator" "")
-			 (match_operand:QI 2 "arith10_operand" "")
-			 (match_operand:QI 3 "arith10_operand" "")))]
-  "TARGET_V9"
-  "
-{
-  enum rtx_code code = GET_CODE (operands[1]);
-
-  if (GET_MODE (sparc_compare_op0) == DImode
-      && ! TARGET_ARCH64)
-    FAIL;
-
-  if (sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && GET_MODE (sparc_compare_op0) == DImode
-      && v9_regcmp_p (code))
-    {
-      operands[1] = gen_rtx_fmt_ee (code, DImode,
-			     sparc_compare_op0, sparc_compare_op1);
-    }
-  else
-    {
-      rtx cc_reg = gen_compare_reg (code,
-				    sparc_compare_op0, sparc_compare_op1);
-      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
-    }
-}")
-
-(define_expand "movhicc"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(if_then_else:HI (match_operand 1 "comparison_operator" "")
-			 (match_operand:HI 2 "arith10_operand" "")
-			 (match_operand:HI 3 "arith10_operand" "")))]
-  "TARGET_V9"
-  "
-{
-  enum rtx_code code = GET_CODE (operands[1]);
-
-  if (GET_MODE (sparc_compare_op0) == DImode
-      && ! TARGET_ARCH64)
-    FAIL;
-
-  if (sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && GET_MODE (sparc_compare_op0) == DImode
-      && v9_regcmp_p (code))
-    {
-      operands[1] = gen_rtx_fmt_ee (code, DImode,
-			     sparc_compare_op0, sparc_compare_op1);
-    }
-  else
-    {
-      rtx cc_reg = gen_compare_reg (code,
-				    sparc_compare_op0, sparc_compare_op1);
-      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
-    }
-}")
-
-(define_expand "movsicc"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(if_then_else:SI (match_operand 1 "comparison_operator" "")
-			 (match_operand:SI 2 "arith10_operand" "")
-			 (match_operand:SI 3 "arith10_operand" "")))]
-  "TARGET_V9"
-  "
-{
-  enum rtx_code code = GET_CODE (operands[1]);
-  enum machine_mode op0_mode = GET_MODE (sparc_compare_op0);
-
-  if (sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && (TARGET_ARCH64 && op0_mode == DImode && v9_regcmp_p (code)))
-    {
-      operands[1] = gen_rtx_fmt_ee (code, op0_mode,
-			     sparc_compare_op0, sparc_compare_op1);
-    }
-  else
-    {
-      rtx cc_reg = gen_compare_reg (code,
-				    sparc_compare_op0, sparc_compare_op1);
-      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg),
-				    cc_reg, const0_rtx);
-    }
-}")
-
-(define_expand "movdicc"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI (match_operand 1 "comparison_operator" "")
-			 (match_operand:DI 2 "arith10_double_operand" "")
-			 (match_operand:DI 3 "arith10_double_operand" "")))]
-  "TARGET_ARCH64"
-  "
-{
-  enum rtx_code code = GET_CODE (operands[1]);
-
-  if (sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && GET_MODE (sparc_compare_op0) == DImode
-      && v9_regcmp_p (code))
-    {
-      operands[1] = gen_rtx_fmt_ee (code, DImode,
-			     sparc_compare_op0, sparc_compare_op1);
-    }
-  else
-    {
-      rtx cc_reg = gen_compare_reg (code,
-				    sparc_compare_op0, sparc_compare_op1);
-      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg),
-				    cc_reg, const0_rtx);
-    }
-}")
-
-(define_expand "movsfcc"
-  [(set (match_operand:SF 0 "register_operand" "")
-	(if_then_else:SF (match_operand 1 "comparison_operator" "")
-			 (match_operand:SF 2 "register_operand" "")
-			 (match_operand:SF 3 "register_operand" "")))]
-  "TARGET_V9 && TARGET_FPU"
-  "
-{
-  enum rtx_code code = GET_CODE (operands[1]);
-
-  if (GET_MODE (sparc_compare_op0) == DImode
-      && ! TARGET_ARCH64)
-    FAIL;
-
-  if (sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && GET_MODE (sparc_compare_op0) == DImode
-      && v9_regcmp_p (code))
-    {
-      operands[1] = gen_rtx_fmt_ee (code, DImode,
-			     sparc_compare_op0, sparc_compare_op1);
-    }
-  else
-    {
-      rtx cc_reg = gen_compare_reg (code,
-				    sparc_compare_op0, sparc_compare_op1);
-      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
-    }
-}")
-
-(define_expand "movdfcc"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(if_then_else:DF (match_operand 1 "comparison_operator" "")
-			 (match_operand:DF 2 "register_operand" "")
-			 (match_operand:DF 3 "register_operand" "")))]
-  "TARGET_V9 && TARGET_FPU"
-  "
-{
-  enum rtx_code code = GET_CODE (operands[1]);
-
-  if (GET_MODE (sparc_compare_op0) == DImode
-      && ! TARGET_ARCH64)
-    FAIL;
-
-  if (sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && GET_MODE (sparc_compare_op0) == DImode
-      && v9_regcmp_p (code))
-    {
-      operands[1] = gen_rtx_fmt_ee (code, DImode,
-			     sparc_compare_op0, sparc_compare_op1);
-    }
-  else
-    {
-      rtx cc_reg = gen_compare_reg (code,
-				    sparc_compare_op0, sparc_compare_op1);
-      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
-    }
-}")
-
-(define_expand "movtfcc"
-  [(set (match_operand:TF 0 "register_operand" "")
-	(if_then_else:TF (match_operand 1 "comparison_operator" "")
-			 (match_operand:TF 2 "register_operand" "")
-			 (match_operand:TF 3 "register_operand" "")))]
-  "TARGET_V9 && TARGET_FPU"
-  "
-{
-  enum rtx_code code = GET_CODE (operands[1]);
-
-  if (GET_MODE (sparc_compare_op0) == DImode
-      && ! TARGET_ARCH64)
-    FAIL;
-
-  if (sparc_compare_op1 == const0_rtx
-      && GET_CODE (sparc_compare_op0) == REG
-      && GET_MODE (sparc_compare_op0) == DImode
-      && v9_regcmp_p (code))
-    {
-      operands[1] = gen_rtx_fmt_ee (code, DImode,
-			     sparc_compare_op0, sparc_compare_op1);
-    }
-  else
-    {
-      rtx cc_reg = gen_compare_reg (code,
-				    sparc_compare_op0, sparc_compare_op1);
-      operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
-    }
-}")
-
-;; Conditional move define_insns.
-
-(define_insn "*movqi_cc_sp64"
-  [(set (match_operand:QI 0 "register_operand" "=r,r")
-	(if_then_else:QI (match_operator 1 "comparison_operator"
-				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
-				 (const_int 0)])
-                         (match_operand:QI 3 "arith11_operand" "rL,0")
-                         (match_operand:QI 4 "arith11_operand" "0,rL")))]
-  "TARGET_V9"
-  "@
-   mov%C1\\t%x2, %3, %0
-   mov%c1\\t%x2, %4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movhi_cc_sp64"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(if_then_else:HI (match_operator 1 "comparison_operator"
-				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
-				 (const_int 0)])
-                         (match_operand:HI 3 "arith11_operand" "rL,0")
-                         (match_operand:HI 4 "arith11_operand" "0,rL")))]
-  "TARGET_V9"
-  "@
-   mov%C1\\t%x2, %3, %0
-   mov%c1\\t%x2, %4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movsi_cc_sp64"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(if_then_else:SI (match_operator 1 "comparison_operator"
-				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
-				 (const_int 0)])
-                         (match_operand:SI 3 "arith11_operand" "rL,0")
-                         (match_operand:SI 4 "arith11_operand" "0,rL")))]
-  "TARGET_V9"
-  "@
-   mov%C1\\t%x2, %3, %0
-   mov%c1\\t%x2, %4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
-
-;; ??? The constraints of operands 3,4 need work.
-(define_insn "*movdi_cc_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(if_then_else:DI (match_operator 1 "comparison_operator"
-				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
-				 (const_int 0)])
-                         (match_operand:DI 3 "arith11_double_operand" "rLH,0")
-                         (match_operand:DI 4 "arith11_double_operand" "0,rLH")))]
-  "TARGET_ARCH64"
-  "@
-   mov%C1\\t%x2, %3, %0
-   mov%c1\\t%x2, %4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movdi_cc_sp64_trunc"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(if_then_else:SI (match_operator 1 "comparison_operator"
-				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
-				 (const_int 0)])
-                         (match_operand:SI 3 "arith11_double_operand" "rLH,0")
-                         (match_operand:SI 4 "arith11_double_operand" "0,rLH")))]
-  "TARGET_ARCH64"
-  "@
-   mov%C1\\t%x2, %3, %0
-   mov%c1\\t%x2, %4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movsf_cc_sp64"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-	(if_then_else:SF (match_operator 1 "comparison_operator"
-				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
-				 (const_int 0)])
-                         (match_operand:SF 3 "register_operand" "f,0")
-                         (match_operand:SF 4 "register_operand" "0,f")))]
-  "TARGET_V9 && TARGET_FPU"
-  "@
-   fmovs%C1\\t%x2, %3, %0
-   fmovs%c1\\t%x2, %4, %0"
-  [(set_attr "type" "fpcmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movdf_cc_sp64"
-  [(set (match_operand:DF 0 "register_operand" "=e,e")
-	(if_then_else:DF (match_operator 1 "comparison_operator"
-				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
-				 (const_int 0)])
-                         (match_operand:DF 3 "register_operand" "e,0")
-                         (match_operand:DF 4 "register_operand" "0,e")))]
-  "TARGET_V9 && TARGET_FPU"
-  "@
-   fmovd%C1\\t%x2, %3, %0
-   fmovd%c1\\t%x2, %4, %0"
-  [(set_attr "type" "fpcmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movtf_cc_sp64"
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
-	(if_then_else:TF (match_operator 1 "comparison_operator"
-				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
-				 (const_int 0)])
-                         (match_operand:TF 3 "register_operand" "e,0")
-                         (match_operand:TF 4 "register_operand" "0,e")))]
-  "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
-  "@
-   fmovq%C1\\t%x2, %3, %0
-   fmovq%c1\\t%x2, %4, %0"
-  [(set_attr "type" "fpcmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movqi_cc_reg_sp64"
-  [(set (match_operand:QI 0 "register_operand" "=r,r")
-	(if_then_else:QI (match_operator 1 "v9_regcmp_op"
-				[(match_operand:DI 2 "register_operand" "r,r")
-				 (const_int 0)])
-                         (match_operand:QI 3 "arith10_operand" "rM,0")
-                         (match_operand:QI 4 "arith10_operand" "0,rM")))]
-  "TARGET_ARCH64"
-  "@
-   movr%D1\\t%2, %r3, %0
-   movr%d1\\t%2, %r4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movhi_cc_reg_sp64"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(if_then_else:HI (match_operator 1 "v9_regcmp_op"
-				[(match_operand:DI 2 "register_operand" "r,r")
-				 (const_int 0)])
-                         (match_operand:HI 3 "arith10_operand" "rM,0")
-                         (match_operand:HI 4 "arith10_operand" "0,rM")))]
-  "TARGET_ARCH64"
-  "@
-   movr%D1\\t%2, %r3, %0
-   movr%d1\\t%2, %r4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movsi_cc_reg_sp64"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(if_then_else:SI (match_operator 1 "v9_regcmp_op"
-				[(match_operand:DI 2 "register_operand" "r,r")
-				 (const_int 0)])
-                         (match_operand:SI 3 "arith10_operand" "rM,0")
-                         (match_operand:SI 4 "arith10_operand" "0,rM")))]
-  "TARGET_ARCH64"
-  "@
-   movr%D1\\t%2, %r3, %0
-   movr%d1\\t%2, %r4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
-
-;; ??? The constraints of operands 3,4 need work.
-(define_insn "*movdi_cc_reg_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(if_then_else:DI (match_operator 1 "v9_regcmp_op"
-				[(match_operand:DI 2 "register_operand" "r,r")
-				 (const_int 0)])
-                         (match_operand:DI 3 "arith10_double_operand" "rMH,0")
-                         (match_operand:DI 4 "arith10_double_operand" "0,rMH")))]
-  "TARGET_ARCH64"
-  "@
-   movr%D1\\t%2, %r3, %0
-   movr%d1\\t%2, %r4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movdi_cc_reg_sp64_trunc"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(if_then_else:SI (match_operator 1 "v9_regcmp_op"
-				[(match_operand:DI 2 "register_operand" "r,r")
-				 (const_int 0)])
-                         (match_operand:SI 3 "arith10_double_operand" "rMH,0")
-                         (match_operand:SI 4 "arith10_double_operand" "0,rMH")))]
-  "TARGET_ARCH64"
-  "@
-   movr%D1\\t%2, %r3, %0
-   movr%d1\\t%2, %r4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movsf_cc_reg_sp64"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-	(if_then_else:SF (match_operator 1 "v9_regcmp_op"
-				[(match_operand:DI 2 "register_operand" "r,r")
-				 (const_int 0)])
-                         (match_operand:SF 3 "register_operand" "f,0")
-                         (match_operand:SF 4 "register_operand" "0,f")))]
-  "TARGET_ARCH64 && TARGET_FPU"
-  "@
-   fmovrs%D1\\t%2, %3, %0
-   fmovrs%d1\\t%2, %4, %0"
-  [(set_attr "type" "fpcmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movdf_cc_reg_sp64"
-  [(set (match_operand:DF 0 "register_operand" "=e,e")
-	(if_then_else:DF (match_operator 1 "v9_regcmp_op"
-				[(match_operand:DI 2 "register_operand" "r,r")
-				 (const_int 0)])
-                         (match_operand:DF 3 "register_operand" "e,0")
-                         (match_operand:DF 4 "register_operand" "0,e")))]
-  "TARGET_ARCH64 && TARGET_FPU"
-  "@
-   fmovrd%D1\\t%2, %3, %0
-   fmovrd%d1\\t%2, %4, %0"
-  [(set_attr "type" "fpcmove")
-   (set_attr "length" "1")])
-
-(define_insn "*movtf_cc_reg_sp64"
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
-	(if_then_else:TF (match_operator 1 "v9_regcmp_op"
-				[(match_operand:DI 2 "register_operand" "r,r")
-				 (const_int 0)])
-                         (match_operand:TF 3 "register_operand" "e,0")
-                         (match_operand:TF 4 "register_operand" "0,e")))]
-  "TARGET_ARCH64 && TARGET_FPU"
-  "@
-   fmovrq%D1\\t%2, %3, %0
-   fmovrq%d1\\t%2, %4, %0"
-  [(set_attr "type" "fpcmove")
-   (set_attr "length" "1")])
-
-;;- zero extension instructions
-
-;; These patterns originally accepted general_operands, however, slightly
-;; better code is generated by only accepting register_operands, and then
-;; letting combine generate the ldu[hb] insns.
-
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
-  ""
-  "
-{
-  rtx temp = gen_reg_rtx (SImode);
-  rtx shift_16 = GEN_INT (16);
-  int op1_subword = 0;
-
-  if (GET_CODE (operand1) == SUBREG)
-    {
-      op1_subword = SUBREG_WORD (operand1);
-      operand1 = XEXP (operand1, 0);
-    }
-
-  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1,
-					 op1_subword),
-			  shift_16));
-  emit_insn (gen_lshrsi3 (operand0, temp, shift_16));
-  DONE;
-}")
-
-(define_insn "*zero_extendhisi2_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
-  ""
-  "lduh\\t%1, %0"
-  [(set_attr "type" "load")
-   (set_attr "length" "1")])
-
-(define_expand "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn "*zero_extendqihi2_insn"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(zero_extend:HI (match_operand:QI 1 "input_operand" "r,m")))]
-  "GET_CODE (operands[1]) != CONST_INT"
-  "@
-   and\\t%1, 0xff, %0
-   ldub\\t%1, %0"
-  [(set_attr "type" "unary,load")
-   (set_attr "length" "1")])
-
-(define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn "*zero_extendqisi2_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(zero_extend:SI (match_operand:QI 1 "input_operand" "r,m")))]
-  "GET_CODE (operands[1]) != CONST_INT"
-  "@
-   and\\t%1, 0xff, %0
-   ldub\\t%1, %0"
-  [(set_attr "type" "unary,load")
-   (set_attr "length" "1")])
-
-(define_expand "zero_extendqidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
-  "TARGET_ARCH64"
-  "")
-
-(define_insn "*zero_extendqidi2_insn"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(zero_extend:DI (match_operand:QI 1 "input_operand" "r,m")))]
-  "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT"
-  "@
-   and\\t%1, 0xff, %0
-   ldub\\t%1, %0"
-  [(set_attr "type" "unary,load")
-   (set_attr "length" "1")])
-
-(define_expand "zero_extendhidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
-  "TARGET_ARCH64"
-  "
-{
-  rtx temp = gen_reg_rtx (DImode);
-  rtx shift_48 = GEN_INT (48);
-  int op1_subword = 0;
-
-  if (GET_CODE (operand1) == SUBREG)
-    {
-      op1_subword = SUBREG_WORD (operand1);
-      operand1 = XEXP (operand1, 0);
-    }
-
-  emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1,
-						op1_subword),
-			  shift_48));
-  emit_insn (gen_lshrdi3 (operand0, temp, shift_48));
-  DONE;
-}")
-
-(define_insn "*zero_extendhidi2_insn"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
-  "TARGET_ARCH64"
-  "lduh\\t%1, %0"
-  [(set_attr "type" "load")
-   (set_attr "length" "1")])
-
-
-;; ??? Write truncdisi pattern using sra?
-
-(define_expand "zero_extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn "*zero_extendsidi2_insn_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(zero_extend:DI (match_operand:SI 1 "input_operand" "r,m")))]
-  "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT"
-  "@
-   srl\\t%1, 0, %0
-   lduw\\t%1, %0"
-  [(set_attr "type" "shift,load")
-   (set_attr "length" "1")])
-
-(define_insn "*zero_extendsidi2_insn_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
-  "! TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
-  "! TARGET_ARCH64 && reload_completed"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (match_dup 5))]
-  "
-{
-  rtx dest1, dest2;
-
-  if (GET_CODE (operands[0]) == SUBREG)
-    operands[0] = alter_subreg (operands[0]);
-
-  dest1 = gen_highpart (SImode, operands[0]);
-  dest2 = gen_lowpart (SImode, operands[0]);
-
-  /* Swap the order in case of overlap.  */
-  if (REGNO (dest1) == REGNO (operands[1]))
-    {
-      operands[2] = dest2;
-      operands[3] = operands[1];
-      operands[4] = dest1;
-      operands[5] = const0_rtx;
-    }
-  else
-    {
-      operands[2] = dest1;
-      operands[3] = const0_rtx;
-      operands[4] = dest2;
-      operands[5] = operands[1];
-    }
-}")
-
-;; Simplify comparisons of extended values.
-
-(define_insn "*cmp_zero_extendqisi2"
-  [(set (reg:CC 100)
-	(compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r"))
-		    (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "andcc\\t%0, 0xff, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_zero_extendqisi2_set"
-  [(set (reg:CC 100)
-	(compare:CC (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI (match_dup 1)))]
-  ""
-  "andcc\\t%1, 0xff, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_zero_extendqidi2"
-  [(set (reg:CCX 100)
-	(compare:CCX (zero_extend:DI (match_operand:QI 0 "register_operand" "r"))
-		     (const_int 0)))]
-  "TARGET_ARCH64"
-  "andcc\\t%0, 0xff, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_zero_extendqidi2_set"
-  [(set (reg:CCX 100)
-	(compare:CCX (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
-		     (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (match_dup 1)))]
-  "TARGET_ARCH64"
-  "andcc\\t%1, 0xff, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare.
-
-(define_insn "*cmp_siqi_trunc"
-  [(set (reg:CC 100)
-	(compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 0)
-		    (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "andcc\\t%0, 0xff, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_siqi_trunc_set"
-  [(set (reg:CC 100)
-	(compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 0)
-		    (const_int 0)))
-   (set (match_operand:QI 0 "register_operand" "=r")
-	(subreg:QI (match_dup 1) 0))]
-  ""
-  "andcc\\t%1, 0xff, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_diqi_trunc"
-  [(set (reg:CC 100)
-	(compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 0)
-		    (const_int 0)))]
-  "TARGET_ARCH64"
-  "andcc\\t%0, 0xff, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_diqi_trunc_set"
-  [(set (reg:CC 100)
-	(compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 0)
-		    (const_int 0)))
-   (set (match_operand:QI 0 "register_operand" "=r")
-	(subreg:QI (match_dup 1) 0))]
-  "TARGET_ARCH64"
-  "andcc\\t%1, 0xff, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-;;- sign extension instructions
-
-;; These patterns originally accepted general_operands, however, slightly
-;; better code is generated by only accepting register_operands, and then
-;; letting combine generate the lds[hb] insns.
-
-(define_expand "extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
-  ""
-  "
-{
-  rtx temp = gen_reg_rtx (SImode);
-  rtx shift_16 = GEN_INT (16);
-  int op1_subword = 0;
-
-  if (GET_CODE (operand1) == SUBREG)
-    {
-      op1_subword = SUBREG_WORD (operand1);
-      operand1 = XEXP (operand1, 0);
-    }
-
-  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1,
-						op1_subword),
-			  shift_16));
-  emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
-  DONE;
-}")
-
-(define_insn "*sign_extendhisi2_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
-  ""
-  "ldsh\\t%1, %0"
-  [(set_attr "type" "sload")
-   (set_attr "length" "1")])
-
-(define_expand "extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
-  ""
-  "
-{
-  rtx temp = gen_reg_rtx (SImode);
-  rtx shift_24 = GEN_INT (24);
-  int op1_subword = 0;
-  int op0_subword = 0;
-
-  if (GET_CODE (operand1) == SUBREG)
-    {
-      op1_subword = SUBREG_WORD (operand1);
-      operand1 = XEXP (operand1, 0);
-    }
-  if (GET_CODE (operand0) == SUBREG)
-    {
-      op0_subword = SUBREG_WORD (operand0);
-      operand0 = XEXP (operand0, 0);
-    }
-  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1,
-						op1_subword),
-			  shift_24));
-  if (GET_MODE (operand0) != SImode)
-    operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subword);
-  emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
-  DONE;
-}")
-
-(define_insn "*sign_extendqihi2_insn"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
-  ""
-  "ldsb\\t%1, %0"
-  [(set_attr "type" "sload")
-   (set_attr "length" "1")])
-
-(define_expand "extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
-  ""
-  "
-{
-  rtx temp = gen_reg_rtx (SImode);
-  rtx shift_24 = GEN_INT (24);
-  int op1_subword = 0;
-
-  if (GET_CODE (operand1) == SUBREG)
-    {
-      op1_subword = SUBREG_WORD (operand1);
-      operand1 = XEXP (operand1, 0);
-    }
-
-  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1,
-						op1_subword),
-			  shift_24));
-  emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
-  DONE;
-}")
-
-(define_insn "*sign_extendqisi2_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
-  ""
-  "ldsb\\t%1, %0"
-  [(set_attr "type" "sload")
-   (set_attr "length" "1")])
-
-(define_expand "extendqidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
-  "TARGET_ARCH64"
-  "
-{
-  rtx temp = gen_reg_rtx (DImode);
-  rtx shift_56 = GEN_INT (56);
-  int op1_subword = 0;
-
-  if (GET_CODE (operand1) == SUBREG)
-    {
-      op1_subword = SUBREG_WORD (operand1);
-      operand1 = XEXP (operand1, 0);
-    }
-
-  emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1,
-						op1_subword),
-			  shift_56));
-  emit_insn (gen_ashrdi3 (operand0, temp, shift_56));
-  DONE;
-}")
-
-(define_insn "*sign_extendqidi2_insn"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
-  "TARGET_ARCH64"
-  "ldsb\\t%1, %0"
-  [(set_attr "type" "sload")
-   (set_attr "length" "1")])
-
-(define_expand "extendhidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
-  "TARGET_ARCH64"
-  "
-{
-  rtx temp = gen_reg_rtx (DImode);
-  rtx shift_48 = GEN_INT (48);
-  int op1_subword = 0;
-
-  if (GET_CODE (operand1) == SUBREG)
-    {
-      op1_subword = SUBREG_WORD (operand1);
-      operand1 = XEXP (operand1, 0);
-    }
-
-  emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1,
-						op1_subword),
-			  shift_48));
-  emit_insn (gen_ashrdi3 (operand0, temp, shift_48));
-  DONE;
-}")
-
-(define_insn "*sign_extendhidi2_insn"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
-  "TARGET_ARCH64"
-  "ldsh\\t%1, %0"
-  [(set_attr "type" "sload")
-   (set_attr "length" "1")])
-
-(define_expand "extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI (match_operand:SI 1 "register_operand" "")))]
-  "TARGET_ARCH64"
-  "")
-
-(define_insn "*sign_extendsidi2_insn"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(sign_extend:DI (match_operand:SI 1 "input_operand" "r,m")))]
-  "TARGET_ARCH64"
-  "@
-  sra\\t%1, 0, %0
-  ldsw\\t%1, %0"
-  [(set_attr "type" "shift,sload")
-   (set_attr "length" "1")])
-
-;; Special pattern for optimizing bit-field compares.  This is needed
-;; because combine uses this as a canonical form.
-
-(define_insn "*cmp_zero_extract"
-  [(set (reg:CC 100)
-	(compare:CC
-	 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
-			  (match_operand:SI 1 "small_int_or_double" "n")
-			  (match_operand:SI 2 "small_int_or_double" "n"))
-	 (const_int 0)))]
-  "! TARGET_LIVE_G0
-   && ((GET_CODE (operands[2]) == CONST_INT
-        && INTVAL (operands[2]) > 19)
-       || (GET_CODE (operands[2]) == CONST_DOUBLE
-           && CONST_DOUBLE_LOW (operands[2]) > 19))"
-  "*
-{
-  int len = (GET_CODE (operands[1]) == CONST_INT
-             ? INTVAL (operands[1])
-             : CONST_DOUBLE_LOW (operands[1]));
-  int pos = 32 -
-            (GET_CODE (operands[2]) == CONST_INT
-             ? INTVAL (operands[2])
-             : CONST_DOUBLE_LOW (operands[2])) - len;
-  HOST_WIDE_INT mask = ((1 << len) - 1) << pos;
-
-  operands[1] = GEN_INT (mask);
-  return \"andcc\\t%0, %1, %%g0\";
-}"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_zero_extract_sp64"
-  [(set (reg:CCX 100)
-	(compare:CCX
-	 (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
-			  (match_operand:SI 1 "small_int_or_double" "n")
-			  (match_operand:SI 2 "small_int_or_double" "n"))
-	 (const_int 0)))]
-  "TARGET_ARCH64
-   && ((GET_CODE (operands[2]) == CONST_INT
-        && INTVAL (operands[2]) > 51)
-       || (GET_CODE (operands[2]) == CONST_DOUBLE
-           && CONST_DOUBLE_LOW (operands[2]) > 51))"
-  "*
-{
-  int len = (GET_CODE (operands[1]) == CONST_INT
-             ? INTVAL (operands[1])
-             : CONST_DOUBLE_LOW (operands[1]));
-  int pos = 64 -
-            (GET_CODE (operands[2]) == CONST_INT
-             ? INTVAL (operands[2])
-             : CONST_DOUBLE_LOW (operands[2])) - len;
-  HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos;
-
-  operands[1] = GEN_INT (mask);
-  return \"andcc\\t%0, %1, %%g0\";
-}"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-;; Conversions between float, double and long double.
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=e")
-	(float_extend:DF
-	 (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fstod\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "extendsftf2"
-  [(set (match_operand:TF 0 "register_operand" "=e")
-	(float_extend:TF
-	 (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "fstoq\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "extenddftf2"
-  [(set (match_operand:TF 0 "register_operand" "=e")
-	(float_extend:TF
-	 (match_operand:DF 1 "register_operand" "e")))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "fdtoq\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float_truncate:SF
-	 (match_operand:DF 1 "register_operand" "e")))]
-  "TARGET_FPU"
-  "fdtos\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "trunctfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float_truncate:SF
-	 (match_operand:TF 1 "register_operand" "e")))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "fqtos\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "trunctfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=e")
-	(float_truncate:DF
-	 (match_operand:TF 1 "register_operand" "e")))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "fqtod\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-;; Conversion between fixed point and floating point.
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float:SF (match_operand:SI 1 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fitos\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "register_operand" "=e")
-	(float:DF (match_operand:SI 1 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fitod\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "floatsitf2"
-  [(set (match_operand:TF 0 "register_operand" "=e")
-	(float:TF (match_operand:SI 1 "register_operand" "f")))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "fitoq\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-;; Now the same for 64 bit sources.
-
-(define_insn "floatdisf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(float:SF (match_operand:DI 1 "register_operand" "e")))]
-  "TARGET_V9 && TARGET_FPU"
-  "fxtos\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "floatdidf2"
-  [(set (match_operand:DF 0 "register_operand" "=e")
-	(float:DF (match_operand:DI 1 "register_operand" "e")))]
-  "TARGET_V9 && TARGET_FPU"
-  "fxtod\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "floatditf2"
-  [(set (match_operand:TF 0 "register_operand" "=e")
-	(float:TF (match_operand:DI 1 "register_operand" "e")))]
-  "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
-  "fxtoq\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-;; Convert a float to an actual integer.
-;; Truncation is performed as part of the conversion.
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=f")
-	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
-  "TARGET_FPU"
-  "fstoi\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=f")
-	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "e"))))]
-  "TARGET_FPU"
-  "fdtoi\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "fix_trunctfsi2"
-  [(set (match_operand:SI 0 "register_operand" "=f")
-	(fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "fqtoi\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-;; Now the same, for V9 targets
-
-(define_insn "fix_truncsfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=e")
-	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
-  "TARGET_V9 && TARGET_FPU"
-  "fstox\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "fix_truncdfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=e")
-	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "e"))))]
-  "TARGET_V9 && TARGET_FPU"
-  "fdtox\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "fix_trunctfdi2"
-  [(set (match_operand:DI 0 "register_operand" "=e")
-	(fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
-  "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
-  "fqtox\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-;;- arithmetic instructions
-
-(define_expand "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
-		 (match_operand:DI 2 "arith_double_add_operand" "rHI")))]
-  ""
-  "
-{
-  if (! TARGET_ARCH64)
-    {
-      emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
-			  gen_rtx_SET (VOIDmode, operands[0],
-				   gen_rtx_PLUS (DImode, operands[1],
-						 operands[2])),
-			  gen_rtx_CLOBBER (VOIDmode,
-				   gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
-      DONE;
-    }
-  if (arith_double_4096_operand(operands[2], DImode))
-    {
-      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
-			      gen_rtx_MINUS (DImode, operands[1],
-					     GEN_INT(-4096))));
-      DONE;
-    }
-}")
-
-(define_insn "adddi3_insn_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
-		 (match_operand:DI 2 "arith_double_operand" "rHI")))
-   (clobber (reg:CC 100))]
-  "! TARGET_ARCH64"
-  "#"
-  [(set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
-		 (match_operand:DI 2 "arith_double_operand" "rHI")))
-   (clobber (reg:CC 100))]
-  "! TARGET_ARCH64 && reload_completed"
-  [(parallel [(set (reg:CC_NOOV 100)
-		   (compare:CC_NOOV (plus:SI (match_dup 4)
-					     (match_dup 5))
-				    (const_int 0)))
-	      (set (match_dup 3)
-		   (plus:SI (match_dup 4) (match_dup 5)))])
-   (set (match_dup 6)
-	(plus:SI (plus:SI (match_dup 7)
-			  (match_dup 8))
-		 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
-  "
-{
-  operands[3] = gen_lowpart (SImode, operands[0]);
-  operands[4] = gen_lowpart (SImode, operands[1]);
-  operands[5] = gen_lowpart (SImode, operands[2]);
-  operands[6] = gen_highpart (SImode, operands[0]);
-  operands[7] = gen_highpart (SImode, operands[1]);
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) < 0)
-	operands[8] = constm1_rtx;
-      else
-	operands[8] = const0_rtx;
-    }
-  else
-    operands[8] = gen_highpart (SImode, operands[2]);
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "arith_double_operand" "r")
-		  (match_operand:DI 2 "arith_double_operand" "rHI")))
-   (clobber (reg:CC 100))]
-  "! TARGET_ARCH64 && reload_completed"
-  [(parallel [(set (reg:CC_NOOV 100)
-		   (compare:CC_NOOV (minus:SI (match_dup 4)
-					      (match_dup 5))
-				    (const_int 0)))
-	      (set (match_dup 3)
-		   (minus:SI (match_dup 4) (match_dup 5)))])
-   (set (match_dup 6)
-	(minus:SI (minus:SI (match_dup 7)
-			    (match_dup 8))
-		  (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
-  "
-{
-  operands[3] = gen_lowpart (SImode, operands[0]);
-  operands[4] = gen_lowpart (SImode, operands[1]);
-  operands[5] = gen_lowpart (SImode, operands[2]);
-  operands[6] = gen_highpart (SImode, operands[0]);
-  operands[7] = gen_highpart (SImode, operands[1]);
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      if (INTVAL (operands[2]) < 0)
-	operands[8] = constm1_rtx;
-      else
-	operands[8] = const0_rtx;
-    }
-  else
-    operands[8] = gen_highpart (SImode, operands[2]);
-}")
-
-;; LTU here means "carry set"
-(define_insn "addx"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (plus:SI (match_operand:SI 1 "arith_operand" "%r")
-			  (match_operand:SI 2 "arith_operand" "rI"))
-		 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
-  ""
-  "addx\\t%1, %2, %0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "1")])
-
-(define_insn "*addx_extend_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
-                                          (match_operand:SI 2 "arith_operand" "rI"))
-                                 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
-  "! TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
-                                          (match_operand:SI 2 "arith_operand" ""))
-                                 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
-  "! TARGET_ARCH64 && reload_completed"
-  [(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
-                               (ltu:SI (reg:CC_NOOV 100) (const_int 0))))
-   (set (match_dup 4) (const_int 0))]
-  "operands[3] = gen_lowpart (SImode, operands[0]);
-   operands[4] = gen_highpart (SImode, operands[1]);")
-
-(define_insn "*addx_extend_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
-                                          (match_operand:SI 2 "arith_operand" "rI"))
-                                 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
-  "TARGET_ARCH64"
-  "addx\\t%r1, %2, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "subx"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-			    (match_operand:SI 2 "arith_operand" "rI"))
-		  (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
-  ""
-  "subx\\t%r1, %2, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "*subx_extend_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-                                            (match_operand:SI 2 "arith_operand" "rI"))
-                                  (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
-  "TARGET_ARCH64"
-  "subx\\t%r1, %2, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "*subx_extend"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-                                            (match_operand:SI 2 "arith_operand" "rI"))
-                                  (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
-  "! TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-                                            (match_operand:SI 2 "arith_operand" "rI"))
-                                  (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
-  "! TARGET_ARCH64 && reload_completed"
-  [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2))
-                                (ltu:SI (reg:CC_NOOV 100) (const_int 0))))
-   (set (match_dup 4) (const_int 0))]
-  "operands[3] = gen_lowpart (SImode, operands[0]);
-   operands[4] = gen_highpart (SImode, operands[0]);")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
-                 (match_operand:DI 2 "register_operand" "r")))
-   (clobber (reg:CC 100))]
-  "! TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
-                 (match_operand:DI 2 "register_operand" "")))
-   (clobber (reg:CC 100))]
-  "! TARGET_ARCH64 && reload_completed"
-  [(parallel [(set (reg:CC_NOOV 100)
-                   (compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1))
-                                    (const_int 0)))
-              (set (match_dup 5) (plus:SI (match_dup 3) (match_dup 1)))])
-   (set (match_dup 6)
-        (plus:SI (plus:SI (match_dup 4) (const_int 0))
-                 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
-  "operands[3] = gen_lowpart (SImode, operands[2]);
-   operands[4] = gen_highpart (SImode, operands[2]);
-   operands[5] = gen_lowpart (SImode, operands[0]);
-   operands[6] = gen_highpart (SImode, operands[0]);")
-
-(define_insn "*adddi3_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
-		 (match_operand:DI 2 "arith_double_operand" "rHI")))]
-  "TARGET_ARCH64"
-  "add\\t%1, %2, %0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "1")])
-
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(plus:SI (match_operand:SI 1 "arith_operand" "%r,d")
-		 (match_operand:SI 2 "arith_add_operand" "rI,d")))]
-  ""
-  "
-{
-  if (arith_4096_operand(operands[2], DImode))
-    {
-      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
-			      gen_rtx_MINUS (SImode, operands[1],
-					     GEN_INT(-4096))));
-      DONE;
-    }
-}")
-
-(define_insn "*addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(plus:SI (match_operand:SI 1 "arith_operand" "%r,d")
-		 (match_operand:SI 2 "arith_operand" "rI,d")))]
-  ""
-  "@
-   add\\t%1, %2, %0
-   fpadd32s\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_cc_plus"
-  [(set (reg:CC_NOOV 100)
-	(compare:CC_NOOV (plus:SI (match_operand:SI 0 "arith_operand" "%r")
-				  (match_operand:SI 1 "arith_operand" "rI"))
-			 (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "addcc\\t%0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_ccx_plus"
-  [(set (reg:CCX_NOOV 100)
-	(compare:CCX_NOOV (plus:DI (match_operand:DI 0 "arith_double_operand" "%r")
-				   (match_operand:DI 1 "arith_double_operand" "rHI"))
-			  (const_int 0)))]
-  "TARGET_ARCH64"
-  "addcc\\t%0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_cc_plus_set"
-  [(set (reg:CC_NOOV 100)
-	(compare:CC_NOOV (plus:SI (match_operand:SI 1 "arith_operand" "%r")
-				  (match_operand:SI 2 "arith_operand" "rI"))
-			 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "addcc\\t%1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_ccx_plus_set"
-  [(set (reg:CCX_NOOV 100)
-	(compare:CCX_NOOV (plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
-				   (match_operand:DI 2 "arith_double_operand" "rHI"))
-			  (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_ARCH64"
-  "addcc\\t%1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_expand "subdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "register_operand" "r")
-		  (match_operand:DI 2 "arith_double_add_operand" "rHI")))]
-  ""
-  "
-{
-  if (! TARGET_ARCH64)
-    {
-      emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
-			  gen_rtx_SET (VOIDmode, operands[0],
-				   gen_rtx_MINUS (DImode, operands[1],
-						  operands[2])),
-			  gen_rtx_CLOBBER (VOIDmode,
-				   gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
-      DONE;
-    }
-  if (arith_double_4096_operand(operands[2], DImode))
-    {
-      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
-			      gen_rtx_PLUS (DImode, operands[1],
-					    GEN_INT(-4096))));
-      DONE;
-    }
-}")
-
-(define_insn "*subdi3_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "register_operand" "r")
-		  (match_operand:DI 2 "arith_double_operand" "rHI")))
-   (clobber (reg:CC 100))]
-  "! TARGET_ARCH64"
-  "#"
-  [(set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (minus:DI (match_operand:DI 1 "register_operand" "")
-                  (match_operand:DI 2 "arith_double_operand" "")))
-   (clobber (reg:CC 100))]
-  "! TARGET_ARCH64
-   && reload_completed
-   && (GET_CODE (operands[2]) == CONST_INT
-       || GET_CODE (operands[2]) == CONST_DOUBLE)"
-  [(clobber (const_int 0))]
-  "
-{
-  rtx highp, lowp;
-
-  highp = gen_highpart (SImode, operands[2]);
-  lowp = gen_lowpart (SImode, operands[2]);
-  if ((lowp == const0_rtx)
-      && (operands[0] == operands[1]))
-    {
-      emit_insn (gen_rtx_SET (VOIDmode,
-                              gen_highpart (SImode, operands[0]),
-                              gen_rtx_MINUS (SImode,
-                                             gen_highpart (SImode, operands[1]),
-                                             highp)));
-    }
-  else
-    {
-      emit_insn (gen_cmp_minus_cc_set (gen_lowpart (SImode, operands[0]),
-                                       gen_lowpart (SImode, operands[1]),
-                                       lowp));
-      emit_insn (gen_subx (gen_highpart (SImode, operands[0]),
-                           gen_highpart (SImode, operands[1]),
-                           highp));
-    }
-  DONE;
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (minus:DI (match_operand:DI 1 "register_operand" "")
-                  (match_operand:DI 2 "register_operand" "")))
-   (clobber (reg:CC 100))]
-  "! TARGET_ARCH64
-   && reload_completed"
-  [(clobber (const_int 0))]
-  "
-{
-  emit_insn (gen_cmp_minus_cc_set (gen_lowpart (SImode, operands[0]),
-                                   gen_lowpart (SImode, operands[1]),
-                                   gen_lowpart (SImode, operands[2])));
-  emit_insn (gen_subx (gen_highpart (SImode, operands[0]),
-                       gen_highpart (SImode, operands[1]),
-                       gen_highpart (SImode, operands[2])));
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-      (minus:DI (match_operand:DI 1 "register_operand" "r")
-                (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))
-   (clobber (reg:CC 100))]
-  "! TARGET_ARCH64"
-  "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (minus:DI (match_operand:DI 1 "register_operand" "")
-                  (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))
-   (clobber (reg:CC 100))]
-  "! TARGET_ARCH64 && reload_completed"
-  [(parallel [(set (reg:CC_NOOV 100)
-                   (compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2))
-                                    (const_int 0)))
-              (set (match_dup 5) (minus:SI (match_dup 3) (match_dup 2)))])
-   (set (match_dup 6)
-        (minus:SI (minus:SI (match_dup 4) (const_int 0))
-                  (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
-  "operands[3] = gen_lowpart (SImode, operands[1]);
-   operands[4] = gen_highpart (SImode, operands[1]);
-   operands[5] = gen_lowpart (SImode, operands[0]);
-   operands[6] = gen_highpart (SImode, operands[0]);")
-
-(define_insn "*subdi3_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "register_operand" "r")
-		  (match_operand:DI 2 "arith_double_operand" "rHI")))]
-  "TARGET_ARCH64"
-  "sub\\t%1, %2, %0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "1")])
-
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(minus:SI (match_operand:SI 1 "register_operand" "r,d")
-		  (match_operand:SI 2 "arith_add_operand" "rI,d")))]
-  ""
-  "
-{
-  if (arith_4096_operand(operands[2], DImode))
-    {
-      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
-			      gen_rtx_PLUS (SImode, operands[1],
-					    GEN_INT(-4096))));
-      DONE;
-    }
-}")
-
-(define_insn "*subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(minus:SI (match_operand:SI 1 "register_operand" "r,d")
-		  (match_operand:SI 2 "arith_operand" "rI,d")))]
-  ""
-  "@
-   sub\\t%1, %2, %0
-   fpsub32s\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_minus_cc"
-  [(set (reg:CC_NOOV 100)
-	(compare:CC_NOOV (minus:SI (match_operand:SI 0 "reg_or_0_operand" "rJ")
-				   (match_operand:SI 1 "arith_operand" "rI"))
-			 (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "subcc\\t%r0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_minus_ccx"
-  [(set (reg:CCX_NOOV 100)
-	(compare:CCX_NOOV (minus:DI (match_operand:DI 0 "register_operand" "r")
-				    (match_operand:DI 1 "arith_double_operand" "rHI"))
-			  (const_int 0)))]
-  "TARGET_ARCH64"
-  "subcc\\t%0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "cmp_minus_cc_set"
-  [(set (reg:CC_NOOV 100)
-	(compare:CC_NOOV (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-				   (match_operand:SI 2 "arith_operand" "rI"))
-			 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_dup 1) (match_dup 2)))]
-  ""
-  "subcc\\t%r1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_minus_ccx_set"
-  [(set (reg:CCX_NOOV 100)
-	(compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "r")
-				    (match_operand:DI 2 "arith_double_operand" "rHI"))
-			  (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_ARCH64"
-  "subcc\\t%1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-;; Integer Multiply/Divide.
-
-;; The 32 bit multiply/divide instructions are deprecated on v9 and shouldn't
-;; we used.  We still use them in 32 bit v9 compilers.
-;; The 64 bit v9 compiler will (/should) widen the args and use muldi3.
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (match_operand:SI 1 "arith_operand" "%r")
-		 (match_operand:SI 2 "arith_operand" "rI")))]
-  "TARGET_HARD_MUL"
-  "smul\\t%1, %2, %0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "1")])
-
-(define_expand "muldi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(mult:DI (match_operand:DI 1 "arith_double_operand" "%r")
-		 (match_operand:DI 2 "arith_double_operand" "rHI")))]
-  "TARGET_ARCH64 || TARGET_V8PLUS"
-  "
-{
-  if (TARGET_V8PLUS)
-    {
-      emit_insn (gen_muldi3_v8plus (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-(define_insn "*muldi3_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(mult:DI (match_operand:DI 1 "arith_double_operand" "%r")
-		 (match_operand:DI 2 "arith_double_operand" "rHI")))]
-  "TARGET_ARCH64"
-  "mulx\\t%1, %2, %0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "1")])
-
-;; V8plus wide multiply.
-;; XXX
-(define_insn "muldi3_v8plus"
-  [(set (match_operand:DI 0 "register_operand" "=r,h")
-	(mult:DI (match_operand:DI 1 "arith_double_operand" "%r,0")
-		 (match_operand:DI 2 "arith_double_operand" "rHI,rHI")))
-   (clobber (match_scratch:SI 3 "=&h,X"))
-   (clobber (match_scratch:SI 4 "=&h,X"))]
-  "TARGET_V8PLUS"
-  "*
-{
-  if (sparc_check_64 (operands[1], insn) <= 0)
-    output_asm_insn (\"srl\\t%L1, 0, %L1\", operands);
-  if (which_alternative == 1)
-    output_asm_insn (\"sllx\\t%H1, 32, %H1\", operands);
-  if (sparc_check_64 (operands[2], insn) <= 0)
-    output_asm_insn (\"srl\\t%L2, 0, %L2\", operands);
-  if (which_alternative == 1)
-    return \"or\\t%L1, %H1, %H1\\n\\tsllx\\t%H2, 32, %L1\\n\\tor\\t%L2, %L1, %L1\\n\\tmulx\\t%H1, %L1, %L0\;srlx\\t%L0, 32, %H0\";
-  else
-    return \"sllx\\t%H1, 32, %3\\n\\tsllx\\t%H2, 32, %4\\n\\tor\\t%L1, %3, %3\\n\\tor\\t%L2, %4, %4\\n\\tmulx\\t%3, %4, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\";
-}"
-  [(set_attr "length" "9,8")])
-
-;; It is not known whether this will match.
-
-(define_insn "*cmp_mul_set"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (match_operand:SI 1 "arith_operand" "%r")
-		 (match_operand:SI 2 "arith_operand" "rI")))
-   (set (reg:CC_NOOV 100)
-	(compare:CC_NOOV (mult:SI (match_dup 1) (match_dup 2))
-			 (const_int 0)))]
-  "TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS"
-  "smulcc\\t%1, %2, %0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "1")])
-
-(define_expand "mulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
-		 (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))))]
-  "TARGET_HARD_MUL"
-  "
-{
-  if (CONSTANT_P (operands[2]))
-    {
-      if (TARGET_V8PLUS)
-	{
-	  emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1],
-						operands[2]));
-	  DONE;
-	}
-      emit_insn (gen_const_mulsidi3 (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-  if (TARGET_V8PLUS)
-    {
-      emit_insn (gen_mulsidi3_v8plus (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-;; V9 puts the 64 bit product in a 64 bit register.  Only out or global
-;; registers can hold 64 bit values in the V8plus environment.
-;; XXX
-(define_insn "mulsidi3_v8plus"
-  [(set (match_operand:DI 0 "register_operand" "=h,r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
-		 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
-   (clobber (match_scratch:SI 3 "=X,&h"))]
-  "TARGET_V8PLUS"
-  "@
-   smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
-   smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
-  [(set_attr "length" "2,3")])
-
-;; XXX
-(define_insn "const_mulsidi3_v8plus"
-  [(set (match_operand:DI 0 "register_operand" "=h,r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
-		 (match_operand:SI 2 "small_int" "I,I")))
-   (clobber (match_scratch:SI 3 "=X,&h"))]
-  "TARGET_V8PLUS"
-  "@
-   smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
-   smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
-  [(set_attr "length" "2,3")])
-
-;; XXX
-(define_insn "*mulsidi3_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
-		 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
-  "TARGET_HARD_MUL32"
-  "*
-{
-  return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
-}"
-  [(set (attr "length")
-	(if_then_else (eq_attr "isa" "sparclet")
-		      (const_int 1) (const_int 2)))])
-
-;; Extra pattern, because sign_extend of a constant isn't valid.
-
-;; XXX
-(define_insn "const_mulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
-		 (match_operand:SI 2 "small_int" "I")))]
-  "TARGET_HARD_MUL"
-  "*
-{
-  return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
-}"
-  [(set (attr "length")
-	(if_then_else (eq_attr "isa" "sparclet")
-		      (const_int 1) (const_int 2)))])
-
-(define_expand "smulsi3_highpart"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
-			       (sign_extend:DI (match_operand:SI 2 "arith_operand" "")))
-		      (const_int 32))))]
-  "TARGET_HARD_MUL"
-  "
-{
-  if (CONSTANT_P (operands[2]))
-    {
-      if (TARGET_V8PLUS)
-	{
-	  emit_insn (gen_const_smulsi3_highpart_v8plus (operands[0],
-							operands[1],
-							operands[2],
-							GEN_INT (32)));
-	  DONE;
-	}
-      emit_insn (gen_const_smulsi3_highpart (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-  if (TARGET_V8PLUS)
-    {
-      emit_insn (gen_smulsi3_highpart_v8plus (operands[0], operands[1],
-					      operands[2], GEN_INT (32)));
-      DONE;
-    }
-}")
-
-;; XXX
-(define_insn "smulsi3_highpart_v8plus"
-  [(set (match_operand:SI 0 "register_operand" "=h,r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
-			       (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
-		      (match_operand:SI 3 "const_int_operand" "i,i"))))
-   (clobber (match_scratch:SI 4 "=X,&h"))]
-  "TARGET_V8PLUS"
-  "@
-   smul %1,%2,%0\;srlx %0,%3,%0
-   smul %1,%2,%4\;srlx %4,%3,%0"
-  [(set_attr "length" "2")])
-
-;; The combiner changes TRUNCATE in the previous pattern to SUBREG.
-;; XXX
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=h,r")
-	(subreg:SI
-	 (lshiftrt:DI
-	  (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
-		   (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
-	  (match_operand:SI 3 "const_int_operand" "i,i"))
-	 1))
-   (clobber (match_scratch:SI 4 "=X,&h"))]
-  "TARGET_V8PLUS"
-  "@
-   smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
-   smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
-  [(set_attr "length" "2")])
-
-;; XXX
-(define_insn "const_smulsi3_highpart_v8plus"
-  [(set (match_operand:SI 0 "register_operand" "=h,r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
-			       (match_operand 2 "small_int" "i,i"))
-		      (match_operand:SI 3 "const_int_operand" "i,i"))))
-   (clobber (match_scratch:SI 4 "=X,&h"))]
-  "TARGET_V8PLUS"
-  "@
-   smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
-   smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
-  [(set_attr "length" "2")])
-
-;; XXX
-(define_insn "*smulsi3_highpart_sp32"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
-			       (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
-		      (const_int 32))))]
-  "TARGET_HARD_MUL32
-   && ! TARGET_LIVE_G0"
-  "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
-  [(set_attr "length" "2")])
-
-;; XXX
-(define_insn "const_smulsi3_highpart"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
-			       (match_operand:SI 2 "register_operand" "r"))
-		      (const_int 32))))]
-  "TARGET_HARD_MUL32
-   && ! TARGET_LIVE_G0"
-  "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
-  [(set_attr "length" "2")])
-
-(define_expand "umulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
-		 (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))))]
-  "TARGET_HARD_MUL"
-  "
-{
-  if (CONSTANT_P (operands[2]))
-    {
-      if (TARGET_V8PLUS)
-	{
-	  emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1],
-						 operands[2]));
-	  DONE;
-	}
-      emit_insn (gen_const_umulsidi3 (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-  if (TARGET_V8PLUS)
-    {
-      emit_insn (gen_umulsidi3_v8plus (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-;; XXX
-(define_insn "umulsidi3_v8plus"
-  [(set (match_operand:DI 0 "register_operand" "=h,r")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
-		 (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
-   (clobber (match_scratch:SI 3 "=X,&h"))]
-  "TARGET_V8PLUS"
-  "@
-   umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
-   umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
-  [(set_attr "length" "2,3")])
-
-;; XXX
-(define_insn "*umulsidi3_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
-		 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
-  "TARGET_HARD_MUL32"
-  "*
-{
-  return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
-}"
-  [(set (attr "length")
-	(if_then_else (eq_attr "isa" "sparclet")
-		      (const_int 1) (const_int 2)))])
-
-;; Extra pattern, because sign_extend of a constant isn't valid.
-
-;; XXX
-(define_insn "const_umulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
-		 (match_operand:SI 2 "uns_small_int" "")))]
-  "TARGET_HARD_MUL32"
-  "*
-{
-  return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
-}"
-  [(set (attr "length")
-	(if_then_else (eq_attr "isa" "sparclet")
-		      (const_int 1) (const_int 2)))])
-
-;; XXX
-(define_insn "const_umulsidi3_v8plus"
-  [(set (match_operand:DI 0 "register_operand" "=h,r")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
-		 (match_operand:SI 2 "uns_small_int" "")))
-   (clobber (match_scratch:SI 3 "=X,h"))]
-  "TARGET_V8PLUS"
-  "@
-   umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
-   umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
-  [(set_attr "length" "2,3")])
-
-(define_expand "umulsi3_highpart"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
-			       (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" "")))
-		      (const_int 32))))]
-  "TARGET_HARD_MUL"
-  "
-{
-  if (CONSTANT_P (operands[2]))
-    {
-      if (TARGET_V8PLUS)
-	{
-	  emit_insn (gen_const_umulsi3_highpart_v8plus (operands[0],
-							operands[1],
-							operands[2],
-							GEN_INT (32)));
-	  DONE;
-	}
-      emit_insn (gen_const_umulsi3_highpart (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-  if (TARGET_V8PLUS)
-    {
-      emit_insn (gen_umulsi3_highpart_v8plus (operands[0], operands[1],
-					      operands[2], GEN_INT (32)));
-      DONE;
-    }
-}")
-
-;; XXX
-(define_insn "umulsi3_highpart_v8plus"
-  [(set (match_operand:SI 0 "register_operand" "=h,r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
-			       (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
-		      (match_operand:SI 3 "const_int_operand" "i,i"))))
-   (clobber (match_scratch:SI 4 "=X,h"))]
-  "TARGET_V8PLUS"
-  "@
-   umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
-   umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
-  [(set_attr "length" "2")])
-
-;; XXX
-(define_insn "const_umulsi3_highpart_v8plus"
-  [(set (match_operand:SI 0 "register_operand" "=h,r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
-			       (match_operand:SI 2 "uns_small_int" ""))
-		      (match_operand:SI 3 "const_int_operand" "i,i"))))
-   (clobber (match_scratch:SI 4 "=X,h"))]
-  "TARGET_V8PLUS"
-  "@
-   umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
-   umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
-  [(set_attr "length" "2")])
-
-;; XXX
-(define_insn "*umulsi3_highpart_sp32"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
-			       (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
-		      (const_int 32))))]
-  "TARGET_HARD_MUL32
-   && ! TARGET_LIVE_G0"
-  "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
-  [(set_attr "length" "2")])
-
-;; XXX
-(define_insn "const_umulsi3_highpart"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
-			       (match_operand:SI 2 "uns_small_int" ""))
-		      (const_int 32))))]
-  "TARGET_HARD_MUL32
-   && ! TARGET_LIVE_G0"
-  "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
-  [(set_attr "length" "2")])
-
-;; The v8 architecture specifies that there must be 3 instructions between
-;; a y register write and a use of it for correct results.
-
-;; XXX SHEESH
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(div:SI (match_operand:SI 1 "register_operand" "r,r")
-		(match_operand:SI 2 "input_operand" "rI,m")))
-   (clobber (match_scratch:SI 3 "=&r,&r"))]
-  "(TARGET_V8
-    || TARGET_DEPRECATED_V8_INSNS)
-   && ! TARGET_LIVE_G0"
-  "*
-{
-  if (which_alternative == 0)
-  if (TARGET_V9)
-    return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tsdiv\\t%1, %2, %0\";
-  else
-    return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %2, %0\";
-  else
-    if (TARGET_V9)
-      return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tld\\t%2, %3\\n\\tsdiv\\t%1, %3, %0\";
-    else
-      return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0\";
-}"
-  [(set (attr "length")
-	(if_then_else (eq_attr "isa" "v9")
-		      (const_int 4) (const_int 7)))])
-
-(define_insn "divdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(div:DI (match_operand:DI 1 "register_operand" "r")
-		(match_operand:DI 2 "arith_double_operand" "rHI")))]
-  "TARGET_ARCH64"
-  "sdivx\\t%1, %2, %0")
-
-;; It is not known whether this will match.
-
-;; XXX I hope it doesn't fucking match...
-(define_insn "*cmp_sdiv_cc_set"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(div:SI (match_operand:SI 1 "register_operand" "r")
-		(match_operand:SI 2 "arith_operand" "rI")))
-   (set (reg:CC 100)
-	(compare:CC (div:SI (match_dup 1) (match_dup 2))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=&r"))]
-  "(TARGET_V8
-    || TARGET_DEPRECATED_V8_INSNS)
-   && ! TARGET_LIVE_G0"
-  "*
-{
-  if (TARGET_V9)
-    return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tsdivcc\\t%1, %2, %0\";
-  else
-    return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0\";
-}"
-  [(set (attr "length")
-	(if_then_else (eq_attr "isa" "v9")
-		      (const_int 3) (const_int 6)))])
-
-;; XXX
-(define_insn "udivsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,&r,&r")
-	(udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "r,r,m")
-		 (match_operand:SI 2 "input_operand" "rI,m,r")))]
-  "(TARGET_V8
-    || TARGET_DEPRECATED_V8_INSNS)
-   && ! TARGET_LIVE_G0"
-  "*
-{
-  output_asm_insn (\"wr\\t%%g0, %%g0, %%y\", operands);
-  switch (which_alternative)
-    {
-    default:
-  if (TARGET_V9)
-	return \"udiv\\t%1, %2, %0\";
-      return \"nop\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %2, %0\";
-    case 1:
-      return \"ld\\t%2, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %0, %0\";
-    case 2:
-      return \"ld\\t%1, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%0, %2, %0\";
-    }
-}"
-  [(set (attr "length")
-	(if_then_else (and (eq_attr "isa" "v9")
-			   (eq_attr "alternative" "0"))
-		      (const_int 2) (const_int 5)))])
-
-(define_insn "udivdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(udiv:DI (match_operand:DI 1 "register_operand" "r")
-		 (match_operand:DI 2 "arith_double_operand" "rHI")))]
-  "TARGET_ARCH64"
-  "udivx\\t%1, %2, %0")
-
-;; It is not known whether this will match.
-
-;; XXX I hope it doesn't fucking match...
-(define_insn "*cmp_udiv_cc_set"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(udiv:SI (match_operand:SI 1 "register_operand" "r")
-		(match_operand:SI 2 "arith_operand" "rI")))
-   (set (reg:CC 100)
-	(compare:CC (udiv:SI (match_dup 1) (match_dup 2))
-		    (const_int 0)))]
-  "(TARGET_V8
-    || TARGET_DEPRECATED_V8_INSNS)
-   && ! TARGET_LIVE_G0"
-  "*
-{
-  if (TARGET_V9)
-    return \"wr\\t%%g0, %%g0, %%y\\n\\tudivcc\\t%1, %2, %0\";
-  else
-    return \"wr\\t%%g0, %%g0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tudivcc\\t%1, %2, %0\";
-}"
-  [(set (attr "length")
-	(if_then_else (eq_attr "isa" "v9")
-		      (const_int 2) (const_int 5)))])
-
-; sparclet multiply/accumulate insns
-
-(define_insn "*smacsi"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "%r")
-			  (match_operand:SI 2 "arith_operand" "rI"))
-		 (match_operand:SI 3 "register_operand" "0")))]
-  "TARGET_SPARCLET"
-  "smac\\t%1, %2, %0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "1")])
-
-(define_insn "*smacdi"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (mult:DI (sign_extend:DI
-			   (match_operand:SI 1 "register_operand" "%r"))
-			  (sign_extend:DI
-			   (match_operand:SI 2 "register_operand" "r")))
-		 (match_operand:DI 3 "register_operand" "0")))]
-  "TARGET_SPARCLET"
-  "smacd\\t%1, %2, %L0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "1")])
-
-(define_insn "*umacdi"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (mult:DI (zero_extend:DI
-			   (match_operand:SI 1 "register_operand" "%r"))
-			  (zero_extend:DI
-			   (match_operand:SI 2 "register_operand" "r")))
-		 (match_operand:DI 3 "register_operand" "0")))]
-  "TARGET_SPARCLET"
-  "umacd\\t%1, %2, %L0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "1")])
-
-;;- Boolean instructions
-;; We define DImode `and' so with DImode `not' we can get
-;; DImode `andn'.  Other combinations are possible.
-
-(define_expand "anddi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(and:DI (match_operand:DI 1 "arith_double_operand" "")
-		(match_operand:DI 2 "arith_double_operand" "")))]
-  ""
-  "")
-
-(define_insn "*anddi3_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(and:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
-		(match_operand:DI 2 "arith_double_operand" "rHI,b")))]
-  "! TARGET_ARCH64"
-  "@
-  #
-  fand\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "2,1")])
-
-(define_insn "*anddi3_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(and:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
-		(match_operand:DI 2 "arith_double_operand" "rHI,b")))]
-  "TARGET_ARCH64"
-  "@
-   and\\t%1, %2, %0
-   fand\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(and:SI (match_operand:SI 1 "arith_operand" "%r,d")
-		(match_operand:SI 2 "arith_operand" "rI,d")))]
-  ""
-  "@
-   and\\t%1, %2, %0
-   fands\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(and:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "GET_CODE (operands[2]) == CONST_INT
-   && !SMALL_INT32 (operands[2])
-   && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))]
-  "
-{
-  operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff);
-}")
-
-;; Split DImode logical operations requiring two instructions.
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(match_operator:DI 1 "cc_arithop"	; AND, IOR, XOR
-			   [(match_operand:DI 2 "register_operand" "")
-			    (match_operand:DI 3 "arith_double_operand" "")]))]
-  "! TARGET_ARCH64
-   && reload_completed
-   && ((GET_CODE (operands[0]) == REG
-        && REGNO (operands[0]) < 32)
-       || (GET_CODE (operands[0]) == SUBREG
-           && GET_CODE (SUBREG_REG (operands[0])) == REG
-           && REGNO (SUBREG_REG (operands[0])) < 32))"
-  [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)]))
-   (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))]
-  "
-{
-  if (GET_CODE (operands[0]) == SUBREG)
-    operands[0] = alter_subreg (operands[0]);
-  operands[4] = gen_highpart (SImode, operands[0]);
-  operands[5] = gen_lowpart (SImode, operands[0]);
-  operands[6] = gen_highpart (SImode, operands[2]);
-  operands[7] = gen_lowpart (SImode, operands[2]);
-  if (GET_CODE (operands[3]) == CONST_INT)
-    {
-      if (INTVAL (operands[3]) < 0)
-	operands[8] = constm1_rtx;
-      else
-	operands[8] = const0_rtx;
-    }
-  else
-    operands[8] = gen_highpart (SImode, operands[3]);
-  operands[9] = gen_lowpart (SImode, operands[3]);
-}")
-
-(define_insn "*and_not_di_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(and:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
-		(match_operand:DI 2 "register_operand" "r,b")))]
-  "! TARGET_ARCH64"
-  "@
-   #
-   fandnot1\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "2,1")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (and:DI (not:DI (match_operand:DI 1 "register_operand" ""))
-                (match_operand:DI 2 "register_operand" "")))]
-  "! TARGET_ARCH64
-   && reload_completed
-   && ((GET_CODE (operands[0]) == REG
-        && REGNO (operands[0]) < 32)
-       || (GET_CODE (operands[0]) == SUBREG
-           && GET_CODE (SUBREG_REG (operands[0])) == REG
-           && REGNO (SUBREG_REG (operands[0])) < 32))"
-  [(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))
-   (set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))]
-  "if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
-   operands[3] = gen_highpart (SImode, operands[0]);
-   operands[4] = gen_highpart (SImode, operands[1]);
-   operands[5] = gen_highpart (SImode, operands[2]);
-   operands[6] = gen_lowpart (SImode, operands[0]);
-   operands[7] = gen_lowpart (SImode, operands[1]);
-   operands[8] = gen_lowpart (SImode, operands[2]);")
-
-(define_insn "*and_not_di_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(and:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
-		(match_operand:DI 2 "register_operand" "r,b")))]
-  "TARGET_ARCH64"
-  "@
-   andn\\t%2, %1, %0
-   fandnot1\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
-
-(define_insn "*and_not_si"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(and:SI (not:SI (match_operand:SI 1 "register_operand" "r,d"))
-		(match_operand:SI 2 "register_operand" "r,d")))]
-  ""
-  "@
-   andn\\t%2, %1, %0
-   fandnot1s\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
-
-(define_expand "iordi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ior:DI (match_operand:DI 1 "arith_double_operand" "")
-		(match_operand:DI 2 "arith_double_operand" "")))]
-  ""
-  "")
-
-(define_insn "*iordi3_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(ior:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
-		(match_operand:DI 2 "arith_double_operand" "rHI,b")))]
-  "! TARGET_ARCH64"
-  "@
-  #
-  for\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "2,1")])
-
-(define_insn "*iordi3_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(ior:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
-		(match_operand:DI 2 "arith_double_operand" "rHI,b")))]
-  "TARGET_ARCH64"
-  "@
-  or\\t%1, %2, %0
-  for\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(ior:SI (match_operand:SI 1 "arith_operand" "%r,d")
-		(match_operand:SI 2 "arith_operand" "rI,d")))]
-  ""
-  "@
-   or\\t%1, %2, %0
-   fors\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ior:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "GET_CODE (operands[2]) == CONST_INT
-   && !SMALL_INT32 (operands[2])
-   && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))]
-  "
-{
-  operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff);
-}")
-
-(define_insn "*or_not_di_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(ior:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
-		(match_operand:DI 2 "register_operand" "r,b")))]
-  "! TARGET_ARCH64"
-  "@
-   #
-   fornot1\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "2,1")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (ior:DI (not:DI (match_operand:DI 1 "register_operand" ""))
-                (match_operand:DI 2 "register_operand" "")))]
-  "! TARGET_ARCH64
-   && reload_completed
-   && ((GET_CODE (operands[0]) == REG
-        && REGNO (operands[0]) < 32)
-       || (GET_CODE (operands[0]) == SUBREG
-           && GET_CODE (SUBREG_REG (operands[0])) == REG
-           && REGNO (SUBREG_REG (operands[0])) < 32))"
-  [(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))
-   (set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))]
-  "if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
-   operands[3] = gen_highpart (SImode, operands[0]);
-   operands[4] = gen_highpart (SImode, operands[1]);
-   operands[5] = gen_highpart (SImode, operands[2]);
-   operands[6] = gen_lowpart (SImode, operands[0]);
-   operands[7] = gen_lowpart (SImode, operands[1]);
-   operands[8] = gen_lowpart (SImode, operands[2]);")
-
-(define_insn "*or_not_di_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(ior:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
-		(match_operand:DI 2 "register_operand" "r,b")))]
-  "TARGET_ARCH64"
-  "@
-  orn\\t%2, %1, %0
-  fornot1\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
-
-(define_insn "*or_not_si"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(ior:SI (not:SI (match_operand:SI 1 "register_operand" "r,d"))
-		(match_operand:SI 2 "register_operand" "r,d")))]
-  ""
-  "@
-   orn\\t%2, %1, %0
-   fornot1s\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
-
-(define_expand "xordi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(xor:DI (match_operand:DI 1 "arith_double_operand" "")
-		(match_operand:DI 2 "arith_double_operand" "")))]
-  ""
-  "")
-
-(define_insn "*xordi3_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(xor:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
-		(match_operand:DI 2 "arith_double_operand" "rHI,b")))]
-  "! TARGET_ARCH64"
-  "@
-  #
-  fxor\\t%1, %2, %0"
-  [(set_attr "length" "2,1")
-   (set_attr "type" "ialu,fp")])
-
-(define_insn "*xordi3_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(xor:DI (match_operand:DI 1 "arith_double_operand" "%rJ,b")
-		(match_operand:DI 2 "arith_double_operand" "rHI,b")))]
-  "TARGET_ARCH64"
-  "@
-  xor\\t%r1, %2, %0
-  fxor\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
-
-(define_insn "*xordi3_sp64_dbl"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(xor:DI (match_operand:DI 1 "register_operand" "r")
-		(match_operand:DI 2 "const64_operand" "")))]
-  "(TARGET_ARCH64
-    && HOST_BITS_PER_WIDE_INT != 64)"
-  "xor\\t%1, %2, %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(xor:SI (match_operand:SI 1 "arith_operand" "%rJ,d")
-		(match_operand:SI 2 "arith_operand" "rI,d")))]
-  ""
-  "@
-   xor\\t%r1, %2, %0
-   fxors\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(xor:SI (match_operand:SI 1 "register_operand" "")
-		(match_operand:SI 2 "" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "GET_CODE (operands[2]) == CONST_INT
-   && !SMALL_INT32 (operands[2])
-   && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))]
-  "
-{
-  operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff);
-}")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(not:SI (xor:SI (match_operand:SI 1 "register_operand" "")
-			(match_operand:SI 2 "" ""))))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "GET_CODE (operands[2]) == CONST_INT
-   && !SMALL_INT32 (operands[2])
-   && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))]
-  "
-{
-  operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff);
-}")
-
-;; xnor patterns.  Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b).
-;; Combine now canonicalizes to the rightmost expression.
-(define_insn "*xor_not_di_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(not:DI (xor:DI (match_operand:DI 1 "register_operand" "r,b")
-			(match_operand:DI 2 "register_operand" "r,b"))))]
-  "! TARGET_ARCH64"
-  "@
-   #
-   fxnor\\t%1, %2, %0"
-  [(set_attr "length" "2,1")
-   (set_attr "type" "ialu,fp")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (not:DI (xor:DI (match_operand:DI 1 "register_operand" "")
-                        (match_operand:DI 2 "register_operand" ""))))]
-  "! TARGET_ARCH64
-   && reload_completed
-   && ((GET_CODE (operands[0]) == REG
-        && REGNO (operands[0]) < 32)
-       || (GET_CODE (operands[0]) == SUBREG
-           && GET_CODE (SUBREG_REG (operands[0])) == REG
-           && REGNO (SUBREG_REG (operands[0])) < 32))"
-  [(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5))))
-   (set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))]
-  "if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
-   operands[3] = gen_highpart (SImode, operands[0]);
-   operands[4] = gen_highpart (SImode, operands[1]);
-   operands[5] = gen_highpart (SImode, operands[2]);
-   operands[6] = gen_lowpart (SImode, operands[0]);
-   operands[7] = gen_lowpart (SImode, operands[1]);
-   operands[8] = gen_lowpart (SImode, operands[2]);")
-
-(define_insn "*xor_not_di_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,b")
-			(match_operand:DI 2 "arith_double_operand" "rHI,b"))))]
-  "TARGET_ARCH64"
-  "@
-  xnor\\t%r1, %2, %0
-  fxnor\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
-
-(define_insn "*xor_not_si"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(not:SI (xor:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,d")
-			(match_operand:SI 2 "arith_operand" "rI,d"))))]
-  ""
-  "@
-   xnor\\t%r1, %2, %0
-   fxnors\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
-
-;; These correspond to the above in the case where we also (or only)
-;; want to set the condition code.  
-
-(define_insn "*cmp_cc_arith_op"
-  [(set (reg:CC 100)
-	(compare:CC
-	 (match_operator:SI 2 "cc_arithop"
-			    [(match_operand:SI 0 "arith_operand" "%r")
-			     (match_operand:SI 1 "arith_operand" "rI")])
-	 (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "%A2cc\\t%0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_ccx_arith_op"
-  [(set (reg:CCX 100)
-	(compare:CCX
-	 (match_operator:DI 2 "cc_arithop"
-			    [(match_operand:DI 0 "arith_double_operand" "%r")
-			     (match_operand:DI 1 "arith_double_operand" "rHI")])
-	 (const_int 0)))]
-  "TARGET_ARCH64"
-  "%A2cc\\t%0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_cc_arith_op_set"
-  [(set (reg:CC 100)
-	(compare:CC
-	 (match_operator:SI 3 "cc_arithop"
-			    [(match_operand:SI 1 "arith_operand" "%r")
-			     (match_operand:SI 2 "arith_operand" "rI")])
-	 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(match_dup 3))]
-  ""
-  "%A3cc\\t%1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_ccx_arith_op_set"
-  [(set (reg:CCX 100)
-	(compare:CCX
-	 (match_operator:DI 3 "cc_arithop"
-			    [(match_operand:DI 1 "arith_double_operand" "%r")
-			     (match_operand:DI 2 "arith_double_operand" "rHI")])
-	 (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-	(match_dup 3))]
-  "TARGET_ARCH64"
-  "%A3cc\\t%1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_cc_xor_not"
-  [(set (reg:CC 100)
-	(compare:CC
-	 (not:SI (xor:SI (match_operand:SI 0 "reg_or_0_operand" "%rJ")
-			 (match_operand:SI 1 "arith_operand" "rI")))
-	 (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "xnorcc\\t%r0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_ccx_xor_not"
-  [(set (reg:CCX 100)
-	(compare:CCX
-	 (not:DI (xor:DI (match_operand:DI 0 "reg_or_0_operand" "%rJ")
-			 (match_operand:DI 1 "arith_double_operand" "rHI")))
-	 (const_int 0)))]
-  "TARGET_ARCH64"
-  "xnorcc\\t%r0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_cc_xor_not_set"
-  [(set (reg:CC 100)
-	(compare:CC
-	 (not:SI (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
-			 (match_operand:SI 2 "arith_operand" "rI")))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (xor:SI (match_dup 1) (match_dup 2))))]
-  ""
-  "xnorcc\\t%r1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_ccx_xor_not_set"
-  [(set (reg:CCX 100)
-	(compare:CCX
-	 (not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
-			 (match_operand:DI 2 "arith_double_operand" "rHI")))
-	 (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-	(not:DI (xor:DI (match_dup 1) (match_dup 2))))]
-  "TARGET_ARCH64"
-  "xnorcc\\t%r1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_cc_arith_op_not"
-  [(set (reg:CC 100)
-	(compare:CC
-	 (match_operator:SI 2 "cc_arithopn"
-			    [(not:SI (match_operand:SI 0 "arith_operand" "rI"))
-			     (match_operand:SI 1 "reg_or_0_operand" "rJ")])
-	 (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "%B2cc\\t%r1, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_ccx_arith_op_not"
-  [(set (reg:CCX 100)
-	(compare:CCX
-	 (match_operator:DI 2 "cc_arithopn"
-			    [(not:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
-			     (match_operand:DI 1 "reg_or_0_operand" "rJ")])
-	 (const_int 0)))]
-  "TARGET_ARCH64"
-  "%B2cc\\t%r1, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_cc_arith_op_not_set"
-  [(set (reg:CC 100)
-	(compare:CC
-	 (match_operator:SI 3 "cc_arithopn"
-			    [(not:SI (match_operand:SI 1 "arith_operand" "rI"))
-			     (match_operand:SI 2 "reg_or_0_operand" "rJ")])
-	 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(match_dup 3))]
-  ""
-  "%B3cc\\t%r2, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_ccx_arith_op_not_set"
-  [(set (reg:CCX 100)
-	(compare:CCX
-	 (match_operator:DI 3 "cc_arithopn"
-			    [(not:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
-			     (match_operand:DI 2 "reg_or_0_operand" "rJ")])
-	 (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-	(match_dup 3))]
-  "TARGET_ARCH64"
-  "%B3cc\\t%r2, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-;; We cannot use the "neg" pseudo insn because the Sun assembler
-;; does not know how to make it work for constants.
-
-(define_expand "negdi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(neg:DI (match_operand:DI 1 "register_operand" "r")))]
-  ""
-  "
-{
-  if (! TARGET_ARCH64)
-    {
-      emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
-			  gen_rtx_SET (VOIDmode, operand0,
-				   gen_rtx_NEG (DImode, operand1)),
-			  gen_rtx_CLOBBER (VOIDmode,
-				   gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
-      DONE;
-    }
-}")
-
-(define_insn "*negdi2_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(neg:DI (match_operand:DI 1 "register_operand" "r")))
-   (clobber (reg:CC 100))]
-  "! TARGET_ARCH64
-   && ! TARGET_LIVE_G0"
-  "#"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (neg:DI (match_operand:DI 1 "register_operand" "")))
-   (clobber (reg:CC 100))]
-  "! TARGET_ARCH64
-   && ! TARGET_LIVE_G0
-   && reload_completed"
-  [(parallel [(set (reg:CC_NOOV 100)
-                   (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5))
-                                    (const_int 0)))
-              (set (match_dup 4) (minus:SI (const_int 0) (match_dup 5)))])
-   (set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3))
-                                (ltu:SI (reg:CC 100) (const_int 0))))]
-  "operands[2] = gen_highpart (SImode, operands[0]);
-   operands[3] = gen_highpart (SImode, operands[1]);
-   operands[4] = gen_lowpart (SImode, operands[0]);
-   operands[5] = gen_lowpart (SImode, operands[1]);")
-
-(define_insn "*negdi2_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(neg:DI (match_operand:DI 1 "register_operand" "r")))]
-  "TARGET_ARCH64"
-  "sub\\t%%g0, %1, %0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "1")])
-
-(define_expand "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-        (neg:SI (match_operand:SI 1 "arith_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_LIVE_G0)
-    {
-      rtx zero_reg = gen_reg_rtx (SImode);
-
-      emit_insn (gen_rtx_SET (VOIDmode, zero_reg, const0_rtx));
-      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
-                                      gen_rtx_MINUS (SImode, zero_reg,
-                                                             operands[1])));
-      DONE;
-    }
-}")
-
-(define_insn "*negsi2_not_liveg0"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
-  "! TARGET_LIVE_G0"
-  "sub\\t%%g0, %1, %0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_cc_neg"
-  [(set (reg:CC_NOOV 100)
-	(compare:CC_NOOV (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
-			 (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "subcc\\t%%g0, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_ccx_neg"
-  [(set (reg:CCX_NOOV 100)
-	(compare:CCX_NOOV (neg:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
-			  (const_int 0)))]
-  "TARGET_ARCH64"
-  "subcc\\t%%g0, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_cc_set_neg"
-  [(set (reg:CC_NOOV 100)
-	(compare:CC_NOOV (neg:SI (match_operand:SI 1 "arith_operand" "rI"))
-			 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_dup 1)))]
-  "! TARGET_LIVE_G0"
-  "subcc\\t%%g0, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_ccx_set_neg"
-  [(set (reg:CCX_NOOV 100)
-	(compare:CCX_NOOV (neg:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
-			  (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-	(neg:DI (match_dup 1)))]
-  "TARGET_ARCH64"
-  "subcc\\t%%g0, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-;; We cannot use the "not" pseudo insn because the Sun assembler
-;; does not know how to make it work for constants.
-(define_expand "one_cmpldi2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(not:DI (match_operand:DI 1 "register_operand" "")))]
-  ""
-  "")
-
-(define_insn "*one_cmpldi2_sp32"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(not:DI (match_operand:DI 1 "register_operand" "r,b")))]
-  "! TARGET_ARCH64"
-  "@
-   #
-   fnot1\\t%1, %0"
-  [(set_attr "type" "unary,fp")
-   (set_attr "length" "2,1")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-        (not:DI (match_operand:DI 1 "register_operand" "")))]
-  "! TARGET_ARCH64
-   && reload_completed
-   && ((GET_CODE (operands[0]) == REG
-        && REGNO (operands[0]) < 32)
-       || (GET_CODE (operands[0]) == SUBREG
-           && GET_CODE (SUBREG_REG (operands[0])) == REG
-           && REGNO (SUBREG_REG (operands[0])) < 32))"
-  [(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0))))
-   (set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))]
-  "if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
-   operands[2] = gen_highpart (SImode, operands[0]);
-   operands[3] = gen_highpart (SImode, operands[1]);
-   operands[4] = gen_lowpart (SImode, operands[0]);
-   operands[5] = gen_lowpart (SImode, operands[1]);")
-
-(define_insn "*one_cmpldi2_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r,b")
-	(not:DI (match_operand:DI 1 "arith_double_operand" "rHI,b")))]
-  "TARGET_ARCH64"
-  "@
-   xnor\\t%%g0, %1, %0
-   fnot1\\t%1, %0"
-  [(set_attr "type" "unary,fp")
-   (set_attr "length" "1")])
-
-(define_expand "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-        (not:SI (match_operand:SI 1 "arith_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_LIVE_G0
-      && GET_CODE (operands[1]) == CONST_INT)
-    {
-      rtx zero_reg = gen_reg_rtx (SImode);
-
-      emit_insn (gen_rtx_SET (VOIDmode, zero_reg, const0_rtx));
-      emit_insn (gen_rtx_SET (VOIDmode,
-                              operands[0],
-                              gen_rtx_NOT (SImode,
-                                           gen_rtx_XOR (SImode,
-                                                        zero_reg,
-                                                        operands[1]))));
-      DONE;
-    }
-}")
-
-(define_insn "*one_cmplsi2_not_liveg0"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(not:SI (match_operand:SI 1 "arith_operand" "rI,d")))]
-  "! TARGET_LIVE_G0"
-  "@
-  xnor\\t%%g0, %1, %0
-  fnot1s\\t%1, %0"
-  [(set_attr "type" "unary,fp")
-   (set_attr "length" "1,1")])
-
-(define_insn "*one_cmplsi2_liveg0"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(not:SI (match_operand:SI 1 "arith_operand" "r,d")))]
-  "TARGET_LIVE_G0"
-  "@
-  xnor\\t%1, 0, %0
-  fnot1s\\t%1, %0"
-  [(set_attr "type" "unary,fp")
-   (set_attr "length" "1,1")])
-
-(define_insn "*cmp_cc_not"
-  [(set (reg:CC 100)
-	(compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI"))
-		    (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "xnorcc\\t%%g0, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_ccx_not"
-  [(set (reg:CCX 100)
-	(compare:CCX (not:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
-		     (const_int 0)))]
-  "TARGET_ARCH64"
-  "xnorcc\\t%%g0, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_cc_set_not"
-  [(set (reg:CC 100)
-	(compare:CC (not:SI (match_operand:SI 1 "arith_operand" "rI"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_dup 1)))]
-  "! TARGET_LIVE_G0"
-  "xnorcc\\t%%g0, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_ccx_set_not"
-  [(set (reg:CCX 100)
-	(compare:CCX (not:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-	(not:DI (match_dup 1)))]
-  "TARGET_ARCH64"
-  "xnorcc\\t%%g0, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-;; Floating point arithmetic instructions.
-
-(define_insn "addtf3"
-  [(set (match_operand:TF 0 "register_operand" "=e")
-	(plus:TF (match_operand:TF 1 "register_operand" "e")
-		 (match_operand:TF 2 "register_operand" "e")))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "faddq\\t%1, %2, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=e")
-	(plus:DF (match_operand:DF 1 "register_operand" "e")
-		 (match_operand:DF 2 "register_operand" "e")))]
-  "TARGET_FPU"
-  "faddd\\t%1, %2, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fadds\\t%1, %2, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "subtf3"
-  [(set (match_operand:TF 0 "register_operand" "=e")
-	(minus:TF (match_operand:TF 1 "register_operand" "e")
-		  (match_operand:TF 2 "register_operand" "e")))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "fsubq\\t%1, %2, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=e")
-	(minus:DF (match_operand:DF 1 "register_operand" "e")
-		  (match_operand:DF 2 "register_operand" "e")))]
-  "TARGET_FPU"
-  "fsubd\\t%1, %2, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (match_operand:SF 1 "register_operand" "f")
-		  (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fsubs\\t%1, %2, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
-
-(define_insn "multf3"
-  [(set (match_operand:TF 0 "register_operand" "=e")
-	(mult:TF (match_operand:TF 1 "register_operand" "e")
-		 (match_operand:TF 2 "register_operand" "e")))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "fmulq\\t%1, %2, %0"
-  [(set_attr "type" "fpmul")
-   (set_attr "length" "1")])
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=e")
-	(mult:DF (match_operand:DF 1 "register_operand" "e")
-		 (match_operand:DF 2 "register_operand" "e")))]
-  "TARGET_FPU"
-  "fmuld\\t%1, %2, %0"
-  [(set_attr "type" "fpmul")
-   (set_attr "length" "1")])
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(mult:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fmuls\\t%1, %2, %0"
-  [(set_attr "type" "fpmul")
-   (set_attr "length" "1")])
-
-(define_insn "*muldf3_extend"
-  [(set (match_operand:DF 0 "register_operand" "=e")
-	(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
-		 (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
-  "(TARGET_V8 || TARGET_V9) && TARGET_FPU"
-  "fsmuld\\t%1, %2, %0"
-  [(set_attr "type" "fpmul")
-   (set_attr "length" "1")])
-
-(define_insn "*multf3_extend"
-  [(set (match_operand:TF 0 "register_operand" "=e")
-	(mult:TF (float_extend:TF (match_operand:DF 1 "register_operand" "e"))
-		 (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))]
-  "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD"
-  "fdmulq\\t%1, %2, %0"
-  [(set_attr "type" "fpmul")
-   (set_attr "length" "1")])
-
-;; don't have timing for quad-prec. divide.
-(define_insn "divtf3"
-  [(set (match_operand:TF 0 "register_operand" "=e")
-	(div:TF (match_operand:TF 1 "register_operand" "e")
-		(match_operand:TF 2 "register_operand" "e")))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "fdivq\\t%1, %2, %0"
-  [(set_attr "type" "fpdivd")
-   (set_attr "length" "1")])
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=e")
-	(div:DF (match_operand:DF 1 "register_operand" "e")
-		(match_operand:DF 2 "register_operand" "e")))]
-  "TARGET_FPU"
-  "fdivd\\t%1, %2, %0"
-  [(set_attr "type" "fpdivd")
-   (set_attr "length" "1")])
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(div:SF (match_operand:SF 1 "register_operand" "f")
-		(match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fdivs\\t%1, %2, %0"
-  [(set_attr "type" "fpdivs")
-   (set_attr "length" "1")])
-
-(define_expand "negtf2"
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
-	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
-  "TARGET_FPU"
-  "")
-
-(define_insn "*negtf2_notv9"
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
-	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
-  ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
-  "TARGET_FPU
-   && ! TARGET_V9"
-  "@
-  fnegs\\t%0, %0
-  #"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1,2")])
-
-(define_split
-  [(set (match_operand:TF 0 "register_operand" "")
-	(neg:TF (match_operand:TF 1 "register_operand" "")))]
-  "TARGET_FPU
-   && ! TARGET_V9
-   && reload_completed
-   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
-  [(set (match_dup 2) (neg:SF (match_dup 3)))
-   (set (match_dup 4) (match_dup 5))
-   (set (match_dup 6) (match_dup 7))]
-  "if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
-   if (GET_CODE (operands[1]) == SUBREG)
-     operands[1] = alter_subreg (operands[1]);
-   operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
-   operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
-   operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
-   operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
-   operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
-   operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
-
-(define_insn "*negtf2_v9"
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
-	(neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
-  ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
-  "TARGET_FPU && TARGET_V9"
-  "@
-  fnegd\\t%0, %0
-  #"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1,2")])
-
-(define_split
-  [(set (match_operand:TF 0 "register_operand" "")
-	(neg:TF (match_operand:TF 1 "register_operand" "")))]
-  "TARGET_FPU
-   && TARGET_V9
-   && reload_completed
-   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
-  [(set (match_dup 2) (neg:DF (match_dup 3)))
-   (set (match_dup 4) (match_dup 5))]
-  "if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
-   if (GET_CODE (operands[1]) == SUBREG)
-     operands[1] = alter_subreg (operands[1]);
-   operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
-   operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
-   operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
-   operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
-
-(define_expand "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(neg:DF (match_operand:DF 1 "register_operand" "")))]
-  "TARGET_FPU"
-  "")
-
-(define_insn "*negdf2_notv9"
-  [(set (match_operand:DF 0 "register_operand" "=e,e")
-	(neg:DF (match_operand:DF 1 "register_operand" "0,e")))]
-  "TARGET_FPU && ! TARGET_V9"
-  "@
-  fnegs\\t%0, %0
-  #"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1,2")])
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-        (neg:DF (match_operand:DF 1 "register_operand" "")))]
-  "TARGET_FPU
-   && ! TARGET_V9
-   && reload_completed
-   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
-  [(set (match_dup 2) (neg:SF (match_dup 3)))
-   (set (match_dup 4) (match_dup 5))]
-  "if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
-   if (GET_CODE (operands[1]) == SUBREG)
-     operands[1] = alter_subreg (operands[1]);
-   operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
-   operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
-   operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
-   operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
-
-(define_insn "*negdf2_v9"
-  [(set (match_operand:DF 0 "register_operand" "=e")
-	(neg:DF (match_operand:DF 1 "register_operand" "e")))]
-  "TARGET_FPU && TARGET_V9"
-  "fnegd\\t%1, %0"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1")])
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fnegs\\t%1, %0"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1")])
-
-(define_insn "abstf2"
-  [(set (match_operand:TF 0 "register_operand" "")
-	(abs:TF (match_operand:TF 1 "register_operand" "")))]
-  "TARGET_FPU"
-  "")
-
-(define_insn "*abstf2_notv9"
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
-	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
-  ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
-  "TARGET_FPU && ! TARGET_V9"
-  "@
-  fabss\\t%0, %0
-  #"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1,2")])
-
-(define_split
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
-	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
-  "TARGET_FPU
-   && ! TARGET_V9
-   && reload_completed
-   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
-  [(set (match_dup 2) (abs:SF (match_dup 3)))
-   (set (match_dup 4) (match_dup 5))
-   (set (match_dup 6) (match_dup 7))]
-  "if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
-   if (GET_CODE (operands[1]) == SUBREG)
-     operands[1] = alter_subreg (operands[1]);
-   operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
-   operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
-   operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
-   operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
-   operands[6] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 2);
-   operands[7] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 2);")
-
-(define_insn "*abstf2_v9"
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
-	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
-  ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
-  "TARGET_FPU && TARGET_V9"
-  "@
-  fabsd\\t%0, %0
-  #"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1,2")])
-
-(define_split
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
-	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
-  "TARGET_FPU
-   && TARGET_V9
-   && reload_completed
-   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
-  [(set (match_dup 2) (abs:DF (match_dup 3)))
-   (set (match_dup 4) (match_dup 5))]
-  "if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
-   if (GET_CODE (operands[1]) == SUBREG)
-     operands[1] = alter_subreg (operands[1]);
-   operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
-   operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
-   operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
-   operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
-
-(define_expand "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "")
-	(abs:DF (match_operand:DF 1 "register_operand" "")))]
-  "TARGET_FPU"
-  "")
-
-(define_insn "*absdf2_notv9"
-  [(set (match_operand:DF 0 "register_operand" "=e,e")
-	(abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
-  "TARGET_FPU && ! TARGET_V9"
-  "@
-  fabss\\t%0, %0
-  #"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1,2")])
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "=e,e")
-	(abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
-  "TARGET_FPU
-   && ! TARGET_V9
-   && reload_completed
-   && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
-  [(set (match_dup 2) (abs:SF (match_dup 3)))
-   (set (match_dup 4) (match_dup 5))]
-  "if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
-   if (GET_CODE (operands[1]) == SUBREG)
-     operands[1] = alter_subreg (operands[1]);
-   operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
-   operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
-   operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
-   operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
-
-(define_insn "*absdf2_v9"
-  [(set (match_operand:DF 0 "register_operand" "=e")
-	(abs:DF (match_operand:DF 1 "register_operand" "e")))]
-  "TARGET_FPU && TARGET_V9"
-  "fabsd\\t%0, %0"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1")])
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(abs:SF (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fabss\\t%1, %0"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1")])
-
-(define_insn "sqrttf2"
-  [(set (match_operand:TF 0 "register_operand" "=e")
-	(sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
-  "TARGET_FPU && TARGET_HARD_QUAD"
-  "fsqrtq\\t%1, %0"
-  [(set_attr "type" "fpsqrt")
-   (set_attr "length" "1")])
-
-(define_insn "sqrtdf2"
-  [(set (match_operand:DF 0 "register_operand" "=e")
-	(sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
-  "TARGET_FPU"
-  "fsqrtd\\t%1, %0"
-  [(set_attr "type" "fpsqrt")
-   (set_attr "length" "1")])
-
-(define_insn "sqrtsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fsqrts\\t%1, %0"
-  [(set_attr "type" "fpsqrt")
-   (set_attr "length" "1")])
-
-;;- arithmetic shift instructions
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "r")
-		   (match_operand:SI 2 "arith_operand" "rI")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
-  return \"sll\\t%1, %2, %0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
-
-;; We special case multiplication by two, as add can be done
-;; in both ALUs, while shift only in IEU0 on UltraSPARC.
-(define_insn "*ashlsi3_const1"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (ashift:SI (match_operand:SI 1 "register_operand" "r")
-                   (const_int 1)))]
-  ""
-  "add\\t%1, %1, %0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "1")])
-
-(define_expand "ashldi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (match_operand:DI 1 "register_operand" "r")
-		   (match_operand:SI 2 "arith_operand" "rI")))]
-  "TARGET_ARCH64 || TARGET_V8PLUS"
-  "
-{
-  if (! TARGET_ARCH64)
-    {
-      if (GET_CODE (operands[2]) == CONST_INT)
-	FAIL;
-      emit_insn (gen_ashldi3_v8plus (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-;; We special case multiplication by two, as add can be done
-;; in both ALUs, while shift only in IEU0 on UltraSPARC.
-(define_insn "*ashldi3_const1"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (match_operand:DI 1 "register_operand" "r")
-		   (const_int 1)))]
-  "TARGET_ARCH64"
-  "add\\t%1, %1, %0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "1")])
-
-(define_insn "*ashldi3_sp64"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashift:DI (match_operand:DI 1 "register_operand" "r")
-		   (match_operand:SI 2 "arith_operand" "rI")))]
-  "TARGET_ARCH64"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
-  return \"sllx\\t%1, %2, %0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
-
-;; XXX UGH!
-(define_insn "ashldi3_v8plus"
-  [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
-	(ashift:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
-		   (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
-   (clobber (match_scratch:SI 3 "=X,X,&h"))]
-  "TARGET_V8PLUS"
-  "*return sparc_v8plus_shift (operands, insn, \"sllx\");"
-  [(set_attr "length" "5,5,6")])
-
-;; Optimize (1LL<<x)-1
-;; XXX this also needs to be fixed to handle equal subregs
-;; XXX first before we could re-enable it.
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=h")
-	(plus:DI (ashift:DI (const_int 1)
-			    (match_operand:SI 2 "arith_operand" "rI"))
-		 (const_int -1)))]
-  "0 && TARGET_V8PLUS"
-  "*
-{
-  if (GET_CODE (operands[2]) == REG && REGNO (operands[2]) == REGNO (operands[0]))
-    return \"mov 1,%L0\;sllx %L0,%2,%L0\;sub %L0,1,%L0\;srlx %L0,32,%H0\";
-  return \"mov 1,%H0\;sllx %H0,%2,%L0\;sub %L0,1,%L0\;srlx %L0,32,%H0\";
-}"
-  [(set_attr "length" "4")])
-
-(define_insn "*cmp_cc_ashift_1"
-  [(set (reg:CC_NOOV 100)
-	(compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r")
-				    (const_int 1))
-			 (const_int 0)))]
-  "! TARGET_LIVE_G0"
-  "addcc\\t%0, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "*cmp_cc_set_ashift_1"
-  [(set (reg:CC_NOOV 100)
-	(compare:CC_NOOV (ashift:SI (match_operand:SI 1 "register_operand" "r")
-				    (const_int 1))
-			 (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (match_dup 1) (const_int 1)))]
-  ""
-  "addcc\\t%1, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
-
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
-		     (match_operand:SI 2 "arith_operand" "rI")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
-  return \"sra\\t%1, %2, %0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
-
-(define_insn "*ashrsi3_extend"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
-				     (match_operand:SI 2 "arith_operand" "r"))))]
-  "TARGET_ARCH64"
-  "sra\\t%1, %2, %0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
-
-;; This handles the case as above, but with constant shift instead of
-;; register. Combiner "simplifies" it for us a little bit though.
-(define_insn "*ashrsi3_extend2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
-				(const_int 32))
-		     (match_operand:SI 2 "small_int_or_double" "n")))]
-  "TARGET_ARCH64
-   && ((GET_CODE (operands[2]) == CONST_INT
-        && INTVAL (operands[2]) >= 32 && INTVAL (operands[2]) < 64)
-       || (GET_CODE (operands[2]) == CONST_DOUBLE
-	   && !CONST_DOUBLE_HIGH (operands[2])
-           && CONST_DOUBLE_LOW (operands[2]) >= 32
-           && CONST_DOUBLE_LOW (operands[2]) < 64))"
-  "*
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
-
-  return \"sra\\t%1, %2, %0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
-
-(define_expand "ashrdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
-		     (match_operand:SI 2 "arith_operand" "rI")))]
-  "TARGET_ARCH64 || TARGET_V8PLUS"
-  "
-{
-  if (! TARGET_ARCH64)
-    {
-      if (GET_CODE (operands[2]) == CONST_INT)
-        FAIL;	/* prefer generic code in this case */
-      emit_insn (gen_ashrdi3_v8plus (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
-		     (match_operand:SI 2 "arith_operand" "rI")))]
-  "TARGET_ARCH64"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
-  return \"srax\\t%1, %2, %0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
-
-;; XXX
-(define_insn "ashrdi3_v8plus"
-  [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
-	(ashiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
-		     (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
-   (clobber (match_scratch:SI 3 "=X,X,&h"))]
-  "TARGET_V8PLUS"
-  "*return sparc_v8plus_shift (operands, insn, \"srax\");"
-  [(set_attr "length" "5,5,6")])
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
-		     (match_operand:SI 2 "arith_operand" "rI")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
-  return \"srl\\t%1, %2, %0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
-
-;; This handles the case where
-;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))),
-;; but combiner "simplifies" it for us.
-(define_insn "*lshrsi3_extend"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(and:DI (subreg:DI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
-			   (match_operand:SI 2 "arith_operand" "r")) 0)
-		(match_operand 3 "" "")))]
-  "TARGET_ARCH64
-   && ((GET_CODE (operands[3]) == CONST_DOUBLE
-           && CONST_DOUBLE_HIGH (operands[3]) == 0
-           && CONST_DOUBLE_LOW (operands[3]) == 0xffffffff)
-#if HOST_BITS_PER_WIDE_INT >= 64
-          || (GET_CODE (operands[3]) == CONST_INT
-              && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff)
-#endif
-         )"
-  "srl\\t%1, %2, %0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
-
-;; This handles the case where
-;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32))
-;; but combiner "simplifies" it for us.
-(define_insn "*lshrsi3_extend2"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extract:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
-			 (match_operand 2 "small_int_or_double" "n")
-			 (const_int 32)))]
-  "TARGET_ARCH64
-   && ((GET_CODE (operands[2]) == CONST_INT
-        && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32)
-       || (GET_CODE (operands[2]) == CONST_DOUBLE
-	   && CONST_DOUBLE_HIGH (operands[2]) == 0
-           && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
-  "*
-{
-  operands[2] = GEN_INT (32 - INTVAL (operands[2]));
-
-  return \"srl\\t%1, %2, %0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
-
-(define_expand "lshrdi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
-		     (match_operand:SI 2 "arith_operand" "rI")))]
-  "TARGET_ARCH64 || TARGET_V8PLUS"
-  "
-{
-  if (! TARGET_ARCH64)
-    {
-      if (GET_CODE (operands[2]) == CONST_INT)
-        FAIL;
-      emit_insn (gen_lshrdi3_v8plus (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
-		     (match_operand:SI 2 "arith_operand" "rI")))]
-  "TARGET_ARCH64"
-  "*
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
-    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
-  return \"srlx\\t%1, %2, %0\";
-}"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
-
-;; XXX
-(define_insn "lshrdi3_v8plus"
-  [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
-	(lshiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
-		     (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
-   (clobber (match_scratch:SI 3 "=X,X,&h"))]
-  "TARGET_V8PLUS"
-  "*return sparc_v8plus_shift (operands, insn, \"srlx\");"
-  [(set_attr "length" "5,5,6")])
-
-;; Unconditional and other jump instructions
-;; On the Sparc, by setting the annul bit on an unconditional branch, the
-;; following insn is never executed.  This saves us a nop.  Dbx does not
-;; handle such branches though, so we only use them when optimizing.
-(define_insn "jump"
-  [(set (pc) (label_ref (match_operand 0 "" "")))]
-  ""
-  "*
-{
-  /* TurboSparc is reported to have problems with
-     with
-	foo: b,a foo
-     i.e. an empty loop with the annul bit set.  The workaround is to use 
-        foo: b foo; nop
-     instead.  */
-
-  if (! TARGET_V9 && flag_delayed_branch
-      && (insn_addresses[INSN_UID (operands[0])]
-	  == insn_addresses[INSN_UID (insn)]))
-    return \"b\\t%l0%#\";
-  else
-    return TARGET_V9 ? \"ba,pt%*\\t%%xcc, %l0%(\" : \"b%*\\t%l0%(\";
-}"
-  [(set_attr "type" "uncond_branch")])
-
-(define_expand "tablejump"
-  [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
-	      (use (label_ref (match_operand 1 "" "")))])]
-  ""
-  "
-{
-  if (GET_MODE (operands[0]) != CASE_VECTOR_MODE)
-    abort ();
-
-  /* In pic mode, our address differences are against the base of the
-     table.  Add that base value back in; CSE ought to be able to combine
-     the two address loads.  */
-  if (flag_pic)
-    {
-      rtx tmp, tmp2;
-      tmp = gen_rtx_LABEL_REF (Pmode, operands[1]);
-      tmp2 = operands[0];
-      if (CASE_VECTOR_MODE != Pmode)
-        tmp2 = gen_rtx_SIGN_EXTEND (Pmode, tmp2);
-      tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
-      operands[0] = memory_address (Pmode, tmp);
-    }
-}")
-
-(define_insn "*tablejump_sp32"
-  [(set (pc) (match_operand:SI 0 "address_operand" "p"))
-   (use (label_ref (match_operand 1 "" "")))]
-  "! TARGET_PTR64"
-  "jmp\\t%a0%#"
-  [(set_attr "type" "uncond_branch")])
-
-(define_insn "*tablejump_sp64"
-  [(set (pc) (match_operand:DI 0 "address_operand" "p"))
-   (use (label_ref (match_operand 1 "" "")))]
-  "TARGET_PTR64"
-  "jmp\\t%a0%#"
-  [(set_attr "type" "uncond_branch")])
-
-;; This pattern recognizes the "instruction" that appears in 
-;; a function call that wants a structure value, 
-;; to inform the called function if compiled with Sun CC.
-;(define_insn "*unimp_insn"
-;  [(match_operand:SI 0 "immediate_operand" "")]
-;  "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) > 0"
-;  "unimp\\t%0"
-;  [(set_attr "type" "marker")])
-
-;;- jump to subroutine
-(define_expand "call"
-  ;; Note that this expression is not used for generating RTL.
-  ;; All the RTL is generated explicitly below.
-  [(call (match_operand 0 "call_operand" "")
-	 (match_operand 3 "" "i"))]
-  ;; operands[2] is next_arg_register
-  ;; operands[3] is struct_value_size_rtx.
-  ""
-  "
-{
-  rtx fn_rtx, nregs_rtx;
-
-   if (GET_MODE (operands[0]) != FUNCTION_MODE)
-    abort ();
-
-  if (GET_CODE (XEXP (operands[0], 0)) == LABEL_REF)
-    {
-      /* This is really a PIC sequence.  We want to represent
-	 it as a funny jump so its delay slots can be filled. 
-
-	 ??? But if this really *is* a CALL, will not it clobber the
-	 call-clobbered registers?  We lose this if it is a JUMP_INSN.
-	 Why cannot we have delay slots filled if it were a CALL?  */
-
-      if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0)
-	emit_jump_insn
-	  (gen_rtx_PARALLEL (VOIDmode,
-		    gen_rtvec (3,
-			       gen_rtx_SET (VOIDmode, pc_rtx,
-					XEXP (operands[0], 0)),
-			       GEN_INT (INTVAL (operands[3]) & 0xfff),
-			       gen_rtx_CLOBBER (VOIDmode,
-					gen_rtx_REG (Pmode, 15)))));
-      else
-	emit_jump_insn
-	  (gen_rtx_PARALLEL (VOIDmode,
-		    gen_rtvec (2,
-			       gen_rtx_SET (VOIDmode, pc_rtx,
-					XEXP (operands[0], 0)),
-			       gen_rtx_CLOBBER (VOIDmode,
-					gen_rtx_REG (Pmode, 15)))));
-      goto finish_call;
-    }
-
-  fn_rtx = operands[0];
-
-  /* Count the number of parameter registers being used by this call.
-     if that argument is NULL, it means we are using them all, which
-     means 6 on the sparc.  */
-#if 0
-  if (operands[2])
-    nregs_rtx = GEN_INT (REGNO (operands[2]) - 8);
-  else
-    nregs_rtx = GEN_INT (6);
-#else
-  nregs_rtx = const0_rtx;
-#endif
-
-  if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0)
-    emit_call_insn
-      (gen_rtx_PARALLEL (VOIDmode,
-		gen_rtvec (3, gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx),
-			   GEN_INT (INTVAL (operands[3]) & 0xfff),
-			   gen_rtx_CLOBBER (VOIDmode,
-				    gen_rtx_REG (Pmode, 15)))));
-  else
-    emit_call_insn
-      (gen_rtx_PARALLEL (VOIDmode,
-		gen_rtvec (2, gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx),
-			   gen_rtx_CLOBBER (VOIDmode,
-				    gen_rtx_REG (Pmode, 15)))));
-
- finish_call:
-#if 0
-  /* If this call wants a structure value,
-     emit an unimp insn to let the called function know about this.  */
-  if (! TARGET_ARCH64 && INTVAL (operands[3]) > 0)
-    {
-      rtx insn = emit_insn (operands[3]);
-      SCHED_GROUP_P (insn) = 1;
-    }
-#endif
-
-  DONE;
-}")
-
-;; We can't use the same pattern for these two insns, because then registers
-;; in the address may not be properly reloaded.
-
-(define_insn "*call_address_sp32"
-  [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
-	 (match_operand 1 "" ""))
-   (clobber (reg:SI 15))]
-  ;;- Do not use operand 1 for most machines.
-  "! TARGET_PTR64"
-  "call\\t%a0, %1%#"
-  [(set_attr "type" "call")])
-
-(define_insn "*call_symbolic_sp32"
-  [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
-	 (match_operand 1 "" ""))
-   (clobber (reg:SI 15))]
-  ;;- Do not use operand 1 for most machines.
-  "! TARGET_PTR64"
-  "call\\t%a0, %1%#"
-  [(set_attr "type" "call")])
-
-(define_insn "*call_address_sp64"
-  [(call (mem:SI (match_operand:DI 0 "address_operand" "p"))
-	 (match_operand 1 "" ""))
-   (clobber (reg:DI 15))]
-  ;;- Do not use operand 1 for most machines.
-  "TARGET_PTR64"
-  "call\\t%a0, %1%#"
-  [(set_attr "type" "call")])
-
-(define_insn "*call_symbolic_sp64"
-  [(call (mem:SI (match_operand:DI 0 "symbolic_operand" "s"))
-	 (match_operand 1 "" ""))
-   (clobber (reg:DI 15))]
-  ;;- Do not use operand 1 for most machines.
-  "TARGET_PTR64"
-  "call\\t%a0, %1%#"
-  [(set_attr "type" "call")])
-
-;; This is a call that wants a structure value.
-;; There is no such critter for v9 (??? we may need one anyway).
-(define_insn "*call_address_struct_value_sp32"
-  [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
-	 (match_operand 1 "" ""))
-   (match_operand 2 "immediate_operand" "")
-   (clobber (reg:SI 15))]
-  ;;- Do not use operand 1 for most machines.
-  "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0"
-  "call\\t%a0, %1\\n\\tnop\\n\\tunimp\\t%2"
-  [(set_attr "type" "call_no_delay_slot")])
-
-;; This is a call that wants a structure value.
-;; There is no such critter for v9 (??? we may need one anyway).
-(define_insn "*call_symbolic_struct_value_sp32"
-  [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
-	 (match_operand 1 "" ""))
-   (match_operand 2 "immediate_operand" "")
-   (clobber (reg:SI 15))]
-  ;;- Do not use operand 1 for most machines.
-  "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0"
-  "call\\t%a0, %1\\n\\tnop\\n\\tunimp\\t%2"
-  [(set_attr "type" "call_no_delay_slot")])
-
-;; This is a call that may want a structure value.  This is used for
-;; untyped_calls.
-(define_insn "*call_address_untyped_struct_value_sp32"
-  [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
-	 (match_operand 1 "" ""))
-   (match_operand 2 "immediate_operand" "")
-   (clobber (reg:SI 15))]
-  ;;- Do not use operand 1 for most machines.
-  "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
-  "call\\t%a0, %1\\n\\tnop\\n\\tnop"
-  [(set_attr "type" "call_no_delay_slot")])
-
-;; This is a call that wants a structure value.
-(define_insn "*call_symbolic_untyped_struct_value_sp32"
-  [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
-	 (match_operand 1 "" ""))
-   (match_operand 2 "immediate_operand" "")
-   (clobber (reg:SI 15))]
-  ;;- Do not use operand 1 for most machines.
-  "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
-  "call\\t%a0, %1\\n\\tnop\\n\\tnop"
-  [(set_attr "type" "call_no_delay_slot")])
-
-(define_expand "call_value"
-  ;; Note that this expression is not used for generating RTL.
-  ;; All the RTL is generated explicitly below.
-  [(set (match_operand 0 "register_operand" "=rf")
-	(call (match_operand:SI 1 "" "")
-	      (match_operand 4 "" "")))]
-  ;; operand 2 is stack_size_rtx
-  ;; operand 3 is next_arg_register
-  ""
-  "
-{
-  rtx fn_rtx, nregs_rtx;
-  rtvec vec;
-
-  if (GET_MODE (operands[1]) != FUNCTION_MODE)
-    abort ();
-
-  fn_rtx = operands[1];
-
-#if 0
-  if (operands[3])
-    nregs_rtx = GEN_INT (REGNO (operands[3]) - 8);
-  else
-    nregs_rtx = GEN_INT (6);
-#else
-  nregs_rtx = const0_rtx;
-#endif
-
-  vec = gen_rtvec (2,
-		   gen_rtx_SET (VOIDmode, operands[0],
-			    gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx)),
-		   gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)));
-
-  emit_call_insn (gen_rtx_PARALLEL (VOIDmode, vec));
-
-  DONE;
-}")
-
-(define_insn "*call_value_address_sp32"
-  [(set (match_operand 0 "" "=rf")
-	(call (mem:SI (match_operand:SI 1 "address_operand" "p"))
-	      (match_operand 2 "" "")))
-   (clobber (reg:SI 15))]
-  ;;- Do not use operand 2 for most machines.
-  "! TARGET_PTR64"
-  "call\\t%a1, %2%#"
-  [(set_attr "type" "call")])
-
-(define_insn "*call_value_symbolic_sp32"
-  [(set (match_operand 0 "" "=rf")
-	(call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
-	      (match_operand 2 "" "")))
-   (clobber (reg:SI 15))]
-  ;;- Do not use operand 2 for most machines.
-  "! TARGET_PTR64"
-  "call\\t%a1, %2%#"
-  [(set_attr "type" "call")])
-
-(define_insn "*call_value_address_sp64"
-  [(set (match_operand 0 "" "")
-	(call (mem:SI (match_operand:DI 1 "address_operand" "p"))
-	      (match_operand 2 "" "")))
-   (clobber (reg:DI 15))]
-  ;;- Do not use operand 2 for most machines.
-  "TARGET_PTR64"
-  "call\\t%a1, %2%#"
-  [(set_attr "type" "call")])
-
-(define_insn "*call_value_symbolic_sp64"
-  [(set (match_operand 0 "" "")
-	(call (mem:SI (match_operand:DI 1 "symbolic_operand" "s"))
-	      (match_operand 2 "" "")))
-   (clobber (reg:DI 15))]
-  ;;- Do not use operand 2 for most machines.
-  "TARGET_PTR64"
-  "call\\t%a1, %2%#"
-  [(set_attr "type" "call")])
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  /* Pass constm1 to indicate that it may expect a structure value, but
-     we don't know what size it is.  */
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, constm1_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-;; Prepare to return any type including a structure value.
-
-(define_expand "untyped_return"
-  [(match_operand:BLK 0 "memory_operand" "")
-   (match_operand 1 "" "")]
-  ""
-  "
-{
-  rtx valreg1 = gen_rtx_REG (DImode, 24);
-  rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
-  rtx result = operands[0];
-
-  if (! TARGET_ARCH64)
-    {
-      rtx rtnreg = gen_rtx_REG (SImode, (leaf_function ? 15 : 31));
-      rtx value = gen_reg_rtx (SImode);
-
-      /* Fetch the instruction where we will return to and see if it's an unimp
-	 instruction (the most significant 10 bits will be zero).  If so,
-	 update the return address to skip the unimp instruction.  */
-      emit_move_insn (value,
-		      gen_rtx_MEM (SImode, plus_constant (rtnreg, 8)));
-      emit_insn (gen_lshrsi3 (value, value, GEN_INT (22)));
-      emit_insn (gen_update_return (rtnreg, value));
-    }
-
-  /* Reload the function value registers.  */
-  emit_move_insn (valreg1, change_address (result, DImode, XEXP (result, 0)));
-  emit_move_insn (valreg2,
-		  change_address (result, TARGET_ARCH64 ? TFmode : DFmode,
-				  plus_constant (XEXP (result, 0), 8)));
-
-  /* Put USE insns before the return.  */
-  emit_insn (gen_rtx_USE (VOIDmode, valreg1));
-  emit_insn (gen_rtx_USE (VOIDmode, valreg2));
-
-  /* Construct the return.  */
-  expand_null_return ();
-
-  DONE;
-}")
-
-;; This is a bit of a hack.  We're incrementing a fixed register (%i7),
-;; and parts of the compiler don't want to believe that the add is needed.
-
-(define_insn "update_return"
-  [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
-	       (match_operand:SI 1 "register_operand" "r")] 1)]
-  "! TARGET_ARCH64"
-  "cmp %1,0\;be,a .+8\;add %0,4,%0"
-  [(set_attr "type" "multi")])
-
-(define_insn "return"
-  [(return)
-   (use (reg:SI 31))]
-  "! TARGET_EPILOGUE"
-  "* return output_return (operands);"
-  [(set_attr "type" "return")])
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "arith_operand" "rI"))
-   (parallel [(return)
-	      (use (reg:SI 31))])]
-  "sparc_return_peephole_ok (operands[0], operands[1])"
-  "return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
-
-(define_expand "indirect_jump"
-  [(set (pc) (match_operand 0 "address_operand" "p"))]
-  ""
-  "")
-
-(define_insn "*branch_sp32"
-  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
-  "! TARGET_PTR64"
- "jmp\\t%a0%#"
- [(set_attr "type" "uncond_branch")])
- 
-(define_insn "*branch_sp64"
-  [(set (pc) (match_operand:DI 0 "address_operand" "p"))]
-  "TARGET_PTR64"
-  "jmp\\t%a0%#"
-  [(set_attr "type" "uncond_branch")])
-
-;; ??? Doesn't work with -mflat.
-(define_expand "nonlocal_goto"
-  [(match_operand:SI 0 "general_operand" "")
-   (match_operand:SI 1 "general_operand" "")
-   (match_operand:SI 2 "general_operand" "")
-   (match_operand:SI 3 "" "")]
-  ""
-  "
-{
-  rtx chain = operands[0];
-  rtx fp = operands[1];
-  rtx stack = operands[2];
-  rtx lab = operands[3];
-  rtx labreg;
-
-  /* Trap instruction to flush all the register windows.  */
-  emit_insn (gen_flush_register_windows ());
-
-  /* Load the fp value for the containing fn into %fp.  This is needed
-     because STACK refers to %fp.  Note that virtual register instantiation
-     fails if the virtual %fp isn't set from a register.  */
-  if (GET_CODE (fp) != REG)
-    fp = force_reg (Pmode, fp);
-  emit_move_insn (virtual_stack_vars_rtx, fp);
-
-  /* Find the containing function's current nonlocal goto handler,
-     which will do any cleanups and then jump to the label.  */
-  labreg = gen_rtx_REG (Pmode, 8);
-  emit_move_insn (labreg, lab);
-
-  /* Restore %fp from stack pointer value for containing function.
-     The restore insn that follows will move this to %sp,
-     and reload the appropriate value into %fp.  */
-  emit_move_insn (frame_pointer_rtx, stack);
-
-  /* USE of frame_pointer_rtx added for consistency; not clear if
-     really needed.  */
-  /*emit_insn (gen_rtx_USE (VOIDmode, frame_pointer_rtx));*/
-  emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
-
-#if 0
-  /* Return, restoring reg window and jumping to goto handler.  */
-  if (TARGET_V9 && GET_CODE (chain) == CONST_INT
-      && ! (INTVAL (chain) & ~(HOST_WIDE_INT)0xffffffff))
-    {
-      emit_insn (gen_goto_handler_and_restore_v9 (labreg, static_chain_rtx,
-						  chain));
-      emit_barrier ();
-      DONE;
-    }
-  /* Put in the static chain register the nonlocal label address.  */
-  emit_move_insn (static_chain_rtx, chain);
-#endif
-
-  emit_insn (gen_rtx_USE (VOIDmode, static_chain_rtx));
-  emit_insn (gen_goto_handler_and_restore (labreg));
-  emit_barrier ();
-  DONE;
-}")
-
-;; Special trap insn to flush register windows.
-(define_insn "flush_register_windows"
-  [(unspec_volatile [(const_int 0)] 1)]
-  ""
-  "* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn "goto_handler_and_restore"
-  [(unspec_volatile [(match_operand 0 "register_operand" "=r")] 2)]
-  ""
-  "jmp\\t%0+0\\n\\trestore"
-  [(set_attr "type" "misc")
-   (set_attr "length" "2")])
-
-;;(define_insn "goto_handler_and_restore_v9"
-;;  [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r,r")
-;;		     (match_operand:SI 1 "register_operand" "=r,r")
-;;		     (match_operand:SI 2 "const_int_operand" "I,n")] 3)]
-;;  "TARGET_V9 && ! TARGET_ARCH64"
-;;  "@
-;;   return\\t%0+0\\n\\tmov\\t%2, %Y1
-;;   sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1"
-;;  [(set_attr "type" "misc")
-;;   (set_attr "length" "2,3")])
-;;
-;;(define_insn "*goto_handler_and_restore_v9_sp64"
-;;  [(unspec_volatile [(match_operand:DI 0 "register_operand" "=r,r")
-;;		     (match_operand:DI 1 "register_operand" "=r,r")
-;;		     (match_operand:SI 2 "const_int_operand" "I,n")] 3)]
-;;  "TARGET_V9 && TARGET_ARCH64"
-;;  "@
-;;   return\\t%0+0\\n\\tmov\\t%2, %Y1
-;;   sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1"
-;;  [(set_attr "type" "misc")
-;;   (set_attr "length" "2,3")])
-
-;; Pattern for use after a setjmp to store FP and the return register
-;; into the stack area.
-
-(define_expand "setjmp"
-  [(const_int 0)]
-  ""
-  "
-{
-  if (TARGET_ARCH64)
-    emit_insn (gen_setjmp_64 ());
-  else
-    emit_insn (gen_setjmp_32 ());
-  DONE;
-}")
-
-(define_expand "setjmp_32"
-  [(set (mem:SI (plus:SI (reg:SI 14) (const_int 56))) (match_dup 0))
-   (set (mem:SI (plus:SI (reg:SI 14) (const_int 60))) (reg:SI 31))]
-  ""
-  "
-{ operands[0] = frame_pointer_rtx; }")
-
-(define_expand "setjmp_64"
-  [(set (mem:DI (plus:DI (reg:DI 14) (const_int 112))) (match_dup 0))
-   (set (mem:DI (plus:DI (reg:DI 14) (const_int 120))) (reg:DI 31))]
-  ""
-  "
-{ operands[0] = frame_pointer_rtx; }")
-
-;; Special pattern for the FLUSH instruction.
-
-(define_insn "flush"
-  [(unspec_volatile [(match_operand 0 "memory_operand" "m")] 4)]
-  ""
-  "* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-;; find first set.
-
-;; The scan instruction searches from the most significant bit while ffs
-;; searches from the least significant bit.  The bit index and treatment of
-;; zero also differ.  It takes at least 7 instructions to get the proper
-;; result.  Here is an obvious 8 instruction sequence.
-
-;; XXX
-(define_insn "ffssi2"
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(ffs:SI (match_operand:SI 1 "register_operand" "r")))
-   (clobber (match_scratch:SI 2 "=&r"))]
-  "TARGET_SPARCLITE || TARGET_SPARCLET"
-  "*
-{
-  if (TARGET_LIVE_G0)
-    output_asm_insn (\"and %%g0,0,%%g0\", operands);
-  return \"sub %%g0,%1,%0\;and %0,%1,%0\;scan %0,0,%0\;mov 32,%2\;sub %2,%0,%0\;sra %0,31,%2\;and %2,31,%2\;add %2,%0,%0\";
-}"
-  [(set_attr "type" "multi")
-   (set_attr "length" "8")])
-
-;; ??? This should be a define expand, so that the extra instruction have
-;; a chance of being optimized away.
-
-;; Disabled because none of the UltraSparcs implement popc.  The HAL R1
-;; does, but no one uses that and we don't have a switch for it.
-;
-;(define_insn "ffsdi2"
-;  [(set (match_operand:DI 0 "register_operand" "=&r")
-;	(ffs:DI (match_operand:DI 1 "register_operand" "r")))
-;   (clobber (match_scratch:DI 2 "=&r"))]
-;  "TARGET_ARCH64"
-;  "neg %1,%2\;xnor %1,%2,%2\;popc %2,%0\;movzr %1,0,%0"
-;  [(set_attr "type" "multi")
-;   (set_attr "length" "4")])
-
-
-;; Peepholes go at the end.
-
-;; Optimize consecutive loads or stores into ldd and std when possible.
-;; The conditions in which we do this are very restricted and are 
-;; explained in the code for {registers,memory}_ok_for_ldd functions.
-
-(define_peephole
-  [(set (match_operand:SI 0 "memory_operand" "")
-      (const_int 0))
-   (set (match_operand:SI 1 "memory_operand" "")
-      (const_int 0))]
-  "TARGET_V9
-   && ! MEM_VOLATILE_P (operands[0])
-   && ! MEM_VOLATILE_P (operands[1])
-   && addrs_ok_for_ldd_peep (XEXP (operands[0], 0), XEXP (operands[1], 0))"
-  "stx\\t%%g0, %0")
-
-(define_peephole
-  [(set (match_operand:SI 0 "memory_operand" "")
-      (const_int 0))
-   (set (match_operand:SI 1 "memory_operand" "")
-      (const_int 0))]
-  "TARGET_V9
-   && ! MEM_VOLATILE_P (operands[0])
-   && ! MEM_VOLATILE_P (operands[1])
-   && addrs_ok_for_ldd_peep (XEXP (operands[1], 0), XEXP (operands[0], 0))"
-  "stx\\t%%g0, %1")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=rf")
-        (match_operand:SI 1 "memory_operand" ""))
-   (set (match_operand:SI 2 "register_operand" "=rf")
-        (match_operand:SI 3 "memory_operand" ""))]
-  "registers_ok_for_ldd_peep (operands[0], operands[2]) 
-   && ! MEM_VOLATILE_P (operands[1])
-   && ! MEM_VOLATILE_P (operands[3])
-   && addrs_ok_for_ldd_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" 
-  "ldd\\t%1, %0")
-
-(define_peephole
-  [(set (match_operand:SI 0 "memory_operand" "")
-        (match_operand:SI 1 "register_operand" "rf"))
-   (set (match_operand:SI 2 "memory_operand" "")
-        (match_operand:SI 3 "register_operand" "rf"))]
-  "registers_ok_for_ldd_peep (operands[1], operands[3]) 
-   && ! MEM_VOLATILE_P (operands[0])
-   && ! MEM_VOLATILE_P (operands[2])
-   && addrs_ok_for_ldd_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
-  "std\\t%1, %0")
- 
-(define_peephole
-  [(set (match_operand:SF 0 "register_operand" "=fr")
-        (match_operand:SF 1 "memory_operand" ""))
-   (set (match_operand:SF 2 "register_operand" "=fr")
-        (match_operand:SF 3 "memory_operand" ""))]
-  "registers_ok_for_ldd_peep (operands[0], operands[2]) 
-   && ! MEM_VOLATILE_P (operands[1])
-   && ! MEM_VOLATILE_P (operands[3])
-   && addrs_ok_for_ldd_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
-  "ldd\\t%1, %0")
-
-(define_peephole
-  [(set (match_operand:SF 0 "memory_operand" "")
-        (match_operand:SF 1 "register_operand" "fr"))
-   (set (match_operand:SF 2 "memory_operand" "")
-        (match_operand:SF 3 "register_operand" "fr"))]
-  "registers_ok_for_ldd_peep (operands[1], operands[3]) 
-  && ! MEM_VOLATILE_P (operands[0])
-  && ! MEM_VOLATILE_P (operands[2])
-  && addrs_ok_for_ldd_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
-  "std\\t%1, %0")
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=rf")
-        (match_operand:SI 1 "memory_operand" ""))
-   (set (match_operand:SI 2 "register_operand" "=rf")
-        (match_operand:SI 3 "memory_operand" ""))]
-  "registers_ok_for_ldd_peep (operands[2], operands[0]) 
-  && ! MEM_VOLATILE_P (operands[3])
-  && ! MEM_VOLATILE_P (operands[1])
-  && addrs_ok_for_ldd_peep (XEXP (operands[3], 0), XEXP (operands[1], 0))"
-  "ldd\\t%3, %2")
-
-(define_peephole
-  [(set (match_operand:SI 0 "memory_operand" "")
-        (match_operand:SI 1 "register_operand" "rf"))
-   (set (match_operand:SI 2 "memory_operand" "")
-        (match_operand:SI 3 "register_operand" "rf"))]
-  "registers_ok_for_ldd_peep (operands[3], operands[1]) 
-  && ! MEM_VOLATILE_P (operands[2])
-  && ! MEM_VOLATILE_P (operands[0])
-  && addrs_ok_for_ldd_peep (XEXP (operands[2], 0), XEXP (operands[0], 0))" 
-  "std\\t%3, %2")
- 
-(define_peephole
-  [(set (match_operand:SF 0 "register_operand" "=fr")
-        (match_operand:SF 1 "memory_operand" ""))
-   (set (match_operand:SF 2 "register_operand" "=fr")
-        (match_operand:SF 3 "memory_operand" ""))]
-  "registers_ok_for_ldd_peep (operands[2], operands[0]) 
-  && ! MEM_VOLATILE_P (operands[3])
-  && ! MEM_VOLATILE_P (operands[1])
-  && addrs_ok_for_ldd_peep (XEXP (operands[3], 0), XEXP (operands[1], 0))"
-  "ldd\\t%3, %2")
-
-(define_peephole
-  [(set (match_operand:SF 0 "memory_operand" "")
-        (match_operand:SF 1 "register_operand" "fr"))
-   (set (match_operand:SF 2 "memory_operand" "")
-        (match_operand:SF 3 "register_operand" "fr"))]
-  "registers_ok_for_ldd_peep (operands[3], operands[1]) 
-  && ! MEM_VOLATILE_P (operands[2])
-  && ! MEM_VOLATILE_P (operands[0])
-  && addrs_ok_for_ldd_peep (XEXP (operands[2], 0), XEXP (operands[0], 0))"
-  "std\\t%3, %2")
- 
-;; Optimize the case of following a reg-reg move with a test
-;; of reg just moved.  Don't allow floating point regs for operand 0 or 1.
-;; This can result from a float to fix conversion.
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "register_operand" "r"))
-   (set (reg:CC 100)
-	(compare:CC (match_operand:SI 2 "register_operand" "r")
-		    (const_int 0)))]
-  "(rtx_equal_p (operands[2], operands[0])
-    || rtx_equal_p (operands[2], operands[1]))
-   && ! FP_REG_P (operands[0])
-   && ! FP_REG_P (operands[1])"
-  "orcc\\t%1, 0, %0")
-
-(define_peephole
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(match_operand:DI 1 "register_operand" "r"))
-   (set (reg:CCX 100)
-	(compare:CCX (match_operand:DI 2 "register_operand" "r")
-		    (const_int 0)))]
-  "TARGET_ARCH64
-   && (rtx_equal_p (operands[2], operands[0])
-       || rtx_equal_p (operands[2], operands[1]))
-   && ! FP_REG_P (operands[0])
-   && ! FP_REG_P (operands[1])"
-  "orcc\\t%1, 0, %0")
-
-;; Return peepholes.  First the "normal" ones.
-;; These are necessary to catch insns ending up in the epilogue delay list.
-
-(define_insn "*return_qi"
-  [(set (match_operand:QI 0 "restore_operand" "")
-	(match_operand:QI 1 "arith_operand" "rI"))
-   (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
-  "*
-{
-  if (! TARGET_ARCH64 && current_function_returns_struct)
-    return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\";
-  else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT
-			 || IN_OR_GLOBAL_P (operands[1])))
-    return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\";
-  else
-    return \"ret\\n\\trestore %%g0, %1, %Y0\";
-}"
-  [(set_attr "type" "multi")])
-
-(define_insn "*return_hi"
-  [(set (match_operand:HI 0 "restore_operand" "")
-	(match_operand:HI 1 "arith_operand" "rI"))
-   (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
-  "*
-{
-  if (! TARGET_ARCH64 && current_function_returns_struct)
-    return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\";
-  else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT
-			 || IN_OR_GLOBAL_P (operands[1])))
-    return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\";
-  else
-    return \"ret\;restore %%g0, %1, %Y0\";
-}"
-  [(set_attr "type" "multi")])
-
-(define_insn "*return_si"
-  [(set (match_operand:SI 0 "restore_operand" "")
-	(match_operand:SI 1 "arith_operand" "rI"))
-   (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
-  "*
-{
-  if (! TARGET_ARCH64 && current_function_returns_struct)
-    return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\";
-  else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT
-			 || IN_OR_GLOBAL_P (operands[1])))
-    return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\";
-  else
-    return \"ret\;restore %%g0, %1, %Y0\";
-}"
-  [(set_attr "type" "multi")])
-
-;; The following pattern is only generated by delayed-branch scheduling,
-;; when the insn winds up in the epilogue.  This can happen not only when
-;; ! TARGET_FPU because we move complex types around by parts using
-;; SF mode SUBREGs.
-(define_insn "*return_sf_no_fpu"
-  [(set (match_operand:SF 0 "restore_operand" "r")
-	(match_operand:SF 1 "register_operand" "r"))
-   (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
-  "*
-{
-  if (! TARGET_ARCH64 && current_function_returns_struct)
-    return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\";
-  else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1]))
-    return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\";
-  else
-    return \"ret\;restore %%g0, %1, %Y0\";
-}"
-  [(set_attr "type" "multi")])
-
-(define_insn "*return_addsi"
-  [(set (match_operand:SI 0 "restore_operand" "")
-	(plus:SI (match_operand:SI 1 "register_operand" "r")
-		 (match_operand:SI 2 "arith_operand" "rI")))
-   (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
-  "*
-{
-  if (! TARGET_ARCH64 && current_function_returns_struct)
-    return \"jmp\\t%%i7+12\\n\\trestore %r1, %2, %Y0\";
-  /* If operands are global or in registers, can use return */
-  else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1])
-	   && (GET_CODE (operands[2]) == CONST_INT
-	       || IN_OR_GLOBAL_P (operands[2])))
-    return \"return\\t%%i7+8\\n\\tadd\\t%Y1, %Y2, %Y0\";
-  else
-    return \"ret\;restore %r1, %2, %Y0\";
-}"
-  [(set_attr "type" "multi")])
-
-(define_insn "*return_di"
-  [(set (match_operand:DI 0 "restore_operand" "")
-	(match_operand:DI 1 "arith_double_operand" "rHI"))
-   (return)]
-  "TARGET_ARCH64 && ! TARGET_EPILOGUE"
-  "ret\;restore %%g0, %1, %Y0"
-  [(set_attr "type" "multi")])
-
-(define_insn "*return_adddi"
-  [(set (match_operand:DI 0 "restore_operand" "")
-	(plus:DI (match_operand:DI 1 "arith_operand" "%r")
-		 (match_operand:DI 2 "arith_double_operand" "rHI")))
-   (return)]
-  "TARGET_ARCH64 && ! TARGET_EPILOGUE"
-  "ret\;restore %r1, %2, %Y0"
-  [(set_attr "type" "multi")])
-
-;; The following pattern is only generated by delayed-branch scheduling,
-;; when the insn winds up in the epilogue.
-(define_insn "*return_sf"
-  [(set (reg:SF 32)
-	(match_operand:SF 0 "register_operand" "f"))
-   (return)]
-  "! TARGET_EPILOGUE"
-  "ret\;fmovs\\t%0, %%f0"
-  [(set_attr "type" "multi")])
-
-;; Now peepholes to do a call followed by a jump.
-
-(define_peephole
-  [(parallel [(set (match_operand 0 "" "")
-		   (call (mem:SI (match_operand:SI 1 "call_operand_address" "ps"))
-			 (match_operand 2 "" "")))
-	      (clobber (reg:SI 15))])
-   (set (pc) (label_ref (match_operand 3 "" "")))]
-  "short_branch (INSN_UID (insn), INSN_UID (operands[3]))
-   && in_same_eh_region (insn, operands[3])
-   && in_same_eh_region (insn, ins1)"
-  "call\\t%a1, %2\\n\\tadd\\t%%o7, (%l3-.-4), %%o7")
-
-(define_peephole
-  [(parallel [(call (mem:SI (match_operand:SI 0 "call_operand_address" "ps"))
-		    (match_operand 1 "" ""))
-	      (clobber (reg:SI 15))])
-   (set (pc) (label_ref (match_operand 2 "" "")))]
-  "short_branch (INSN_UID (insn), INSN_UID (operands[2]))
-   && in_same_eh_region (insn, operands[2])
-   && in_same_eh_region (insn, ins1)"
-  "call\\t%a0, %1\\n\\tadd\\t%%o7, (%l2-.-4), %%o7")
-
-(define_peephole
-  [(parallel [(set (match_operand 0 "" "")
-		   (call (mem:SI (match_operand:DI 1 "call_operand_address" "ps"))
-			 (match_operand 2 "" "")))
-	      (clobber (reg:DI 15))])
-   (set (pc) (label_ref (match_operand 3 "" "")))]
-  "TARGET_ARCH64
-   && short_branch (INSN_UID (insn), INSN_UID (operands[3]))
-   && in_same_eh_region (insn, operands[3])
-   && in_same_eh_region (insn, ins1)"
-  "call\\t%a1, %2\\n\\tadd\\t%%o7, (%l3-.-4), %%o7")
-
-(define_peephole
-  [(parallel [(call (mem:SI (match_operand:DI 0 "call_operand_address" "ps"))
-		    (match_operand 1 "" ""))
-	      (clobber (reg:DI 15))])
-   (set (pc) (label_ref (match_operand 2 "" "")))]
-  "TARGET_ARCH64
-   && short_branch (INSN_UID (insn), INSN_UID (operands[2]))
-   && in_same_eh_region (insn, operands[2])
-   && in_same_eh_region (insn, ins1)"
-  "call\\t%a0, %1\\n\\tadd\\t%%o7, (%l2-.-4), %%o7")
-
-;; After a nonlocal goto, we need to restore the PIC register, but only
-;; if we need it.  So do nothing much here, but we'll check for this in
-;; finalize_pic.
-
-;; Make sure this unspec_volatile number agrees with finalize_pic.
-(define_insn "nonlocal_goto_receiver"
-  [(unspec_volatile [(const_int 0)] 5)]
-  "flag_pic"
-  "")
-
-(define_insn "trap"
-  [(trap_if (const_int 1) (const_int 5))]
-  ""
-  "ta\\t5"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_expand "conditional_trap"
-  [(trap_if (match_operator 0 "noov_compare_op"
-			    [(match_dup 2) (match_dup 3)])
-	    (match_operand:SI 1 "arith_operand" ""))]
-  ""
-  "operands[2] = gen_compare_reg (GET_CODE (operands[0]),
-				  sparc_compare_op0, sparc_compare_op1);
-   operands[3] = const0_rtx;")
-
-(define_insn ""
-  [(trap_if (match_operator 0 "noov_compare_op" [(reg:CC 100) (const_int 0)])
-	    (match_operand:SI 1 "arith_operand" "rM"))]
-  ""
-  "t%C0\\t%1"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
-(define_insn ""
-  [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)])
-	    (match_operand:SI 1 "arith_operand" "rM"))]
-  "TARGET_V9"
-  "t%C0\\t%%xcc, %1"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
-
diff --git a/gcc/config/sparc/splet.h b/gcc/config/sparc/splet.h
deleted file mode 100755
index 50dbb58..0000000
--- a/gcc/config/sparc/splet.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SPARClet.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Doug Evans (dje@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sparc/aout.h"
-
-/* -mbroken-saverestore is not included here because the long term
-   default is -mno-broken-saverestore.  */
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
-
-/* -mlive-g0 is only supported on the sparclet.  */
-#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{"big-endian", -MASK_LITTLE_ENDIAN},		\
-{"little-endian", MASK_LITTLE_ENDIAN},		\
-{"live-g0", MASK_LIVE_G0},			\
-{"no-live-g0", -MASK_LIVE_G0},			\
-{"broken-saverestore", MASK_BROKEN_SAVERESTORE},	\
-{"no-broken-saverestore", -MASK_BROKEN_SAVERESTORE},
-
-#undef ASM_SPEC
-#define ASM_SPEC "%{mlittle-endian:-EL} %(asm_cpu)"
-
-/* Require the user to supply crt0.o.  */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-
-#undef LINK_SPEC
-#define LINK_SPEC "%{mlittle-endian:-EL}"
-
-/* sparclet chips are bi-endian.  */
-#undef BYTES_BIG_ENDIAN
-#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
-#undef WORDS_BIG_ENDIAN
-#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
-
-#undef SUBTARGET_OVERRIDE_OPTIONS
-#define SUBTARGET_OVERRIDE_OPTIONS 					\
-  do {									\
-    if (TARGET_LIVE_G0)							\
-      {									\
-	warning ("Option '-mlive-g0' deprecated.");			\
-        target_flags &= ~MASK_LIVE_G0;					\
-      }									\
-    else if (TARGET_BROKEN_SAVERESTORE)					\
-      {									\
-	warning ("Option '-mbroken-saverestore' deprecated.");		\
-        target_flags &= ~MASK_BROKEN_SAVERESTORE;			\
-      }									\
-  } while (0)
-
diff --git a/gcc/config/sparc/sun4gas.h b/gcc/config/sparc/sun4gas.h
deleted file mode 100755
index 3cea956..0000000
--- a/gcc/config/sparc/sun4gas.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SunOS 4.x with gas
-   Copyright (C) 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* gas supports unaligned data.  */
-#define UNALIGNED_DOUBLE_INT_ASM_OP ".uaxword"
-#define UNALIGNED_INT_ASM_OP	".uaword"
-#define UNALIGNED_SHORT_ASM_OP	".uahalf"
-
-/* defaults.h will define DWARF2_UNWIND_INFO for us.  */
-#undef DWARF2_UNWIND_INFO
diff --git a/gcc/config/sparc/sun4o3.h b/gcc/config/sparc/sun4o3.h
deleted file mode 100755
index 10c7391..0000000
--- a/gcc/config/sparc/sun4o3.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#include "sparc/sparc.h"
-
-#undef FUNCTION_PROFILER
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\tsethi %%hi(LP%d),%%o0\n\tcall .mcount\n\tor %%lo(LP%d),%%o0,%%o0\n", \
-	   (LABELNO), (LABELNO))
-
-/* LINK_SPEC is needed only for SunOS 4.  */
-
-#undef LINK_SPEC
-
-/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
-   traps available which can get and set the condition codes
-   reliably.  */
-#undef MACHINE_STATE_SAVE
-#define MACHINE_STATE_SAVE(ID)				\
-  unsigned long int ms_flags, ms_saveret;		\
-  asm volatile("ta	0x20\n\t"			\
-	       "mov	%%g1, %0\n\t"			\
-	       "mov	%%g2, %1\n\t"			\
-	       : "=r" (ms_flags), "=r" (ms_saveret));
-
-#undef MACHINE_STATE_RESTORE
-#define MACHINE_STATE_RESTORE(ID)			\
-  asm volatile("mov	%0, %%g1\n\t"			\
-	       "mov	%1, %%g2\n\t"			\
-	       "ta	0x21\n\t"			\
-	       : /* no outputs */			\
-	       : "r" (ms_flags), "r" (ms_saveret));
diff --git a/gcc/config/sparc/sunos4.h b/gcc/config/sparc/sunos4.h
deleted file mode 100755
index 14c7a43..0000000
--- a/gcc/config/sparc/sunos4.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SunOS 4.x
-   Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define SUNOS4_SHARED_LIBRARIES 1
-
-/* Use N_BINCL stabs.  */
-
-#define DBX_USE_BINCL
-
-#include "sparc/sparc.h"
-
-/* The Sun as doesn't like unaligned data.  */
-#define DWARF2_UNWIND_INFO 0
-
-/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
-   traps available which can get and set the condition codes
-   reliably.  */
-#undef MACHINE_STATE_SAVE
-#define MACHINE_STATE_SAVE(ID)				\
-  unsigned long int ms_flags, ms_saveret;		\
-  asm volatile("ta	0x20\n\t"			\
-	       "mov	%%g1, %0\n\t"			\
-	       "mov	%%g2, %1\n\t"			\
-	       : "=r" (ms_flags), "=r" (ms_saveret));
-
-#undef MACHINE_STATE_RESTORE
-#define MACHINE_STATE_RESTORE(ID)			\
-  asm volatile("mov	%0, %%g1\n\t"			\
-	       "mov	%1, %%g2\n\t"			\
-	       "ta	0x21\n\t"			\
-	       : /* no outputs */			\
-	       : "r" (ms_flags), "r" (ms_saveret));
diff --git a/gcc/config/sparc/sysv4.h b/gcc/config/sparc/sysv4.h
deleted file mode 100755
index 572b9dc..0000000
--- a/gcc/config/sparc/sysv4.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/* Target definitions for GNU compiler for Sparc running System V.4
-   Copyright (C) 1991, 92, 95, 96, 97, 1998 Free Software Foundation, Inc.
-   Contributed by Ron Guilmette (rfg@monkeys.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sparc/sparc.h"
-
-/* Undefine some symbols which are defined in "sparc.h" but which are
-   appropriate only for SunOS 4.x, and not for svr4.  */
-
-#undef WORD_SWITCH_TAKES_ARG
-#undef ASM_OUTPUT_SOURCE_LINE
-#undef SELECT_SECTION
-#undef ASM_DECLARE_FUNCTION_NAME
-#undef TEXT_SECTION_ASM_OP
-#undef DATA_SECTION_ASM_OP
-
-#include "svr4.h"
-
-/* ??? Put back the SIZE_TYPE/PTRDIFF_TYPE definitions set by sparc.h.
-   Why, exactly, is svr4.h messing with this?  Seems like the chip 
-   would know best.  */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
-
-/* Undefined some symbols which are defined in "svr4.h" but which are
-   appropriate only for typical svr4 systems, but not for the specific
-   case of svr4 running on a Sparc.  */
-
-#undef INIT_SECTION_ASM_OP
-#undef FINI_SECTION_ASM_OP
-#undef CONST_SECTION_ASM_OP
-#undef TYPE_OPERAND_FMT
-#undef PUSHSECTION_FORMAT
-#undef STRING_ASM_OP
-#undef COMMON_ASM_OP
-#undef SKIP_ASM_OP
-#undef SET_ASM_OP	/* Has no equivalent.  See ASM_OUTPUT_DEF below.  */
-
-/* Provide a set of pre-definitions and pre-assertions appropriate for
-   the Sparc running svr4.  __svr4__ is our extension.  */
-
-#define CPP_PREDEFINES \
-"-Dsparc -Dunix -D__svr4__ -Asystem(unix) -Asystem(svr4)"
-
-/* The native assembler can't compute differences between symbols in different
-   sections when generating pic code, so we must put jump tables in the
-   text section.  */
-/* But we now defer the tables to the end of the function, so we make
-   this 0 to not confuse the branch shortening code.  */
-#define JUMP_TABLES_IN_TEXT_SECTION 0
-
-/* Pass -K to the assembler when PIC.  */
-#undef ASM_SPEC
-#define ASM_SPEC \
-  "%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
-   %{fpic:-K PIC} %{fPIC:-K PIC} %(asm_cpu)"
-
-/* Must use data section for relocatable constants when pic.  */
-#undef SELECT_RTX_SECTION
-#define SELECT_RTX_SECTION(MODE,RTX)		\
-{						\
-  if (flag_pic && symbolic_operand (RTX))	\
-    data_section ();				\
-  else						\
-    const_section ();				\
-}
-
-/* Define the names of various pseudo-op used by the Sparc/svr4 assembler.
-   Note that many of these are different from the typical pseudo-ops used
-   by most svr4 assemblers.  That is probably due to a (misguided?) attempt
-   to keep the Sparc/svr4 assembler somewhat compatible with the Sparc/SunOS
-   assembler.  */
-
-#define STRING_ASM_OP		".asciz"
-#define COMMON_ASM_OP		".common"
-#define SKIP_ASM_OP		".skip"
-#define UNALIGNED_DOUBLE_INT_ASM_OP ".uaxword"
-#define UNALIGNED_INT_ASM_OP	".uaword"
-#define UNALIGNED_SHORT_ASM_OP	".uahalf"
-#define PUSHSECTION_ASM_OP	".pushsection"
-#define POPSECTION_ASM_OP	".popsection"
-
-/* This is defined in sparc.h but is not used by svr4.h.  */
-#undef ASM_LONG
-#define ASM_LONG ".long"
-
-/* This is the format used to print the second operand of a .type pseudo-op
-   for the Sparc/svr4 assembler.  */
-
-#define TYPE_OPERAND_FMT      "#%s"
-
-/* This is the format used to print a .pushsection pseudo-op (and its operand)
-   for the Sparc/svr4 assembler.  */
-
-#define PUSHSECTION_FORMAT	"\t%s\t\"%s\"\n"
-
-#undef ASM_OUTPUT_CASE_LABEL
-#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE)		\
-do { ASM_OUTPUT_ALIGN ((FILE), Pmode == SImode ? 2 : 3);		\
-     ASM_OUTPUT_INTERNAL_LABEL ((FILE), PREFIX, NUM);			\
-   } while (0)
-
-/* This is how to equate one symbol to another symbol.  The syntax used is
-   `SYM1=SYM2'.  Note that this is different from the way equates are done
-   with most svr4 assemblers, where the syntax is `.set SYM1,SYM2'.  */
-
-#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)				\
- do {	fprintf ((FILE), "\t");						\
-	assemble_name (FILE, LABEL1);					\
-	fprintf (FILE, " = ");						\
-	assemble_name (FILE, LABEL2);					\
-	fprintf (FILE, "\n");						\
-  } while (0)
-
-/* Define how the Sparc registers should be numbered for Dwarf output.
-   The numbering provided here should be compatible with the native
-   svr4 SDB debugger in the Sparc/svr4 reference port.  The numbering
-   is as follows:
-
-   Assembly name	gcc internal regno	Dwarf regno
-   ----------------------------------------------------------
-   g0-g7		0-7			0-7
-   o0-o7		8-15			8-15
-   l0-l7		16-23			16-23
-   i0-i7		24-31			24-31
-   f0-f31		32-63			40-71
-*/
-
-#define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 32 ? (REGNO) : (REGNO) + 8)
-
-/* A set of symbol definitions for assembly pseudo-ops which will
-   get us switched to various sections of interest.  These are used
-   in all places where we simply want to switch to a section, and
-   *not* to push the previous section name onto the assembler's
-   section names stack (as we do often in dwarfout.c).  */
-
-#define TEXT_SECTION_ASM_OP	".section\t\".text\""
-#define DATA_SECTION_ASM_OP	".section\t\".data\""
-#define BSS_SECTION_ASM_OP	".section\t\".bss\""
-#define CONST_SECTION_ASM_OP	".section\t\".rodata\""
-#define INIT_SECTION_ASM_OP	".section\t\".init\""
-#define FINI_SECTION_ASM_OP	".section\t\".fini\""
-
-/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
- 
-   Note that we want to give these sections the SHF_WRITE attribute
-   because these sections will actually contain data (i.e. tables of
-   addresses of functions in the current root executable or shared library
-   file) and, in the case of a shared library, the relocatable addresses
-   will have to be properly resolved/relocated (and then written into) by
-   the dynamic linker when it actually attaches the given shared library
-   to the executing process.  (Note that on SVR4, you may wish to use the
-   `-z text' option to the ELF linker, when building a shared library, as
-   an additional check that you are doing everything right.  But if you do
-   use the `-z text' option when building a shared library, you will get
-   errors unless the .ctors and .dtors sections are marked as writable
-   via the SHF_WRITE attribute.)  */
- 
-#undef CTORS_SECTION_ASM_OP
-#define CTORS_SECTION_ASM_OP    ".section\t\".ctors\",#alloc,#write"
-#undef DTORS_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP    ".section\t\".dtors\",#alloc,#write"
-#undef EH_FRAME_SECTION_ASM_OP
-#define EH_FRAME_SECTION_ASM_OP ".section\t\".eh_frame\",#alloc,#write"
-
-/* A C statement to output something to the assembler file to switch to section
-   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
-   NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
-   define this macro in such cases.  */
-
-#undef	ASM_OUTPUT_SECTION_NAME	/* Override svr4.h's definition.  */
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
-do {									\
-  if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL)			\
-    fprintf (FILE, ".section\t\"%s\",#alloc,#execinstr\n",		\
-	                                      (NAME));		\
-  else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC))		\
-    fprintf (FILE, ".section\t\"%s\",#alloc\n", (NAME));		\
-  else									\
-    fprintf (FILE, ".section\t\"%s\",#alloc,#write\n", (NAME));		\
-} while (0)
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.  */
-
-#undef FUNCTION_BLOCK_PROFILER
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  \
-  do { \
-    fprintf (FILE, "\tsethi %%hi(.LLPBX0),%%o0\n\tld [%%lo(.LLPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(.LLPBX0),%%o0\n\tcall __bb_init_func\n\tnop\nLPY%d:\n", \
-	     (LABELNO), (LABELNO)); \
-  } while (0)
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  */
-
-#undef BLOCK_PROFILER
-#define BLOCK_PROFILER(FILE, BLOCKNO) \
-{ \
-  int blockn = (BLOCKNO); \
-  fprintf (FILE, "\tsethi %%hi(.LLPBX2+%d),%%g1\n\tld [%%lo(.LLPBX2+%d)+%%g1],%%g2\n\
-\tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(.LLPBX2+%d)+%%g1]\n", \
-	   4 * blockn, 4 * blockn, 4 * blockn); \
-}
-
-/* A C statement (sans semicolon) to output to the stdio stream
-   FILE the assembler definition of uninitialized global DECL named
-   NAME whose size is SIZE bytes and alignment is ALIGN bytes.
-   Try to use asm_output_aligned_bss to implement this macro.  */
-
-#undef ASM_OUTPUT_ALIGNED_BSS
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
diff --git a/gcc/config/sparc/t-elf b/gcc/config/sparc/t-elf
deleted file mode 100755
index da9df38..0000000
--- a/gcc/config/sparc/t-elf
+++ /dev/null
@@ -1,39 +0,0 @@
-# we need to supply our own assembly versions of libgcc1.c files,
-# since the user may not have native 'cc' available
-
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = sparc/lb1spc.asm
-LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3
-
-# crt0 is built elsewhere
-LIBGCC1_TEST =
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# MULTILIB_OPTIONS should have msparclite too, but we'd have to make
-# gas build...
-#MULTILIB_OPTIONS = msoft-float mcpu=v8
-MULTILIB_OPTIONS = msoft-float
-#MULTILIB_DIRNAMES = soft v8
-MULTILIB_DIRNAMES = soft
-#MULTILIB_MATCHES = msoft-float=mno-fpu mcpu?v8=mv8
-MULTILIB_MATCHES = msoft-float=mno-fpu
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# Assemble startup files.
-crti.o: $(srcdir)/config/sparc/sol2-ci.asm $(GCC_PASSES)
-	$(GCC_FOR_TARGET) -c -o crti.o -x assembler $(srcdir)/config/sparc/sol2-ci.asm
-crtn.o: $(srcdir)/config/sparc/sol2-cn.asm $(GCC_PASSES)
-	$(GCC_FOR_TARGET) -c -o crtn.o -x assembler $(srcdir)/config/sparc/sol2-cn.asm
diff --git a/gcc/config/sparc/t-halos b/gcc/config/sparc/t-halos
deleted file mode 100755
index 0bd5496..0000000
--- a/gcc/config/sparc/t-halos
+++ /dev/null
@@ -1,2 +0,0 @@
-# For a native HALOS compile, we need to set -e1 for the assembler
-AS=as -e1
diff --git a/gcc/config/sparc/t-linux b/gcc/config/sparc/t-linux
deleted file mode 100755
index 6e37a02..0000000
--- a/gcc/config/sparc/t-linux
+++ /dev/null
@@ -1,6 +0,0 @@
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# We don't want to build .umul, etc., because gnu/Linux provides them,
-# which means that libgcc1-test will fail for cross-compiler.
-LIBGCC1_TEST =
diff --git a/gcc/config/sparc/t-linux64 b/gcc/config/sparc/t-linux64
deleted file mode 100755
index 077cf69..0000000
--- a/gcc/config/sparc/t-linux64
+++ /dev/null
@@ -1,21 +0,0 @@
-MULTILIB_OPTIONS = m64/m32
-MULTILIB_DIRNAMES = 64 32
-MULTILIB_MATCHES =
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o
-
-tcrtbeginS.o: crtstuff.c $(GCC_PASSES) $(CONFIG_H) \
-  defaults.h frame.h gbl-ctors.h
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \
-	  -finhibit-size-directive -fno-inline-functions -fno-exceptions $(CRTSTUFF_T_CFLAGS_S) \
-	  -c $(srcdir)/crtstuff.c -DCRT_BEGIN -o tcrtbeginS$(objext)
-
-tcrtendS.o: crtstuff.c $(GCC_PASSES) $(CONFIG_H) \
-  defaults.h frame.h gbl-ctors.h
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \
-	  -finhibit-size-directive -fno-inline-functions -fno-exceptions $(CRTSTUFF_T_CFLAGS_S) \
-	  -c $(srcdir)/crtstuff.c -DCRT_END -o tcrtendS$(objext)
-
diff --git a/gcc/config/sparc/t-sol2 b/gcc/config/sparc/t-sol2
deleted file mode 100755
index a9b6ee1..0000000
--- a/gcc/config/sparc/t-sol2
+++ /dev/null
@@ -1,30 +0,0 @@
-# we need to supply our own assembly versions of libgcc1.c files,
-# since the user may not have native 'cc' available
-
-LIBGCC1 =
-CROSS_LIBGCC1 =
-LIBGCC1_TEST =
-
-# gmon build rule:
-$(T)gmon.o:	$(srcdir)/config/sparc/gmon-sol2.c $(GCC_PASSES) $(CONFIG_H) stmp-int-hdrs
-	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) \
-		-c $(srcdir)/config/sparc/gmon-sol2.c -o $(T)gmon.o
-
-# Assemble startup files.
-$(T)crt1.o: $(srcdir)/config/sparc/sol2-c1.asm $(GCC_PASSES)
-	$(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) -c -o $(T)crt1.o -x assembler-with-cpp $(srcdir)/config/sparc/sol2-c1.asm
-$(T)crti.o: $(srcdir)/config/sparc/sol2-ci.asm $(GCC_PASSES)
-	$(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/sparc/sol2-ci.asm
-$(T)crtn.o: $(srcdir)/config/sparc/sol2-cn.asm $(GCC_PASSES)
-	$(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/sparc/sol2-cn.asm
-$(T)gcrt1.o: $(srcdir)/config/sparc/sol2-c1.asm $(GCC_PASSES)
-	$(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) -c -DGCRT1 -o $(T)gcrt1.o -x assembler-with-cpp $(srcdir)/config/sparc/sol2-c1.asm
-
-# We need to use -fPIC when we are using gcc to compile the routines in
-# crtstuff.c.  This is only really needed when we are going to use gcc/g++
-# to produce a shared library, but since we don't know ahead of time when
-# we will be doing that, we just always use -fPIC when compiling the
-# routines in crtstuff.c.
-
-CRTSTUFF_T_CFLAGS = -fPIC
-TARGET_LIBGCC2_CFLAGS = -fPIC
diff --git a/gcc/config/sparc/t-sol2-64 b/gcc/config/sparc/t-sol2-64
deleted file mode 100755
index 8d42c44..0000000
--- a/gcc/config/sparc/t-sol2-64
+++ /dev/null
@@ -1,8 +0,0 @@
-MULTILIB_OPTIONS = m32/m64
-MULTILIB_DIRNAMES = sparcv7 sparcv9
-MULTILIB_MATCHES =
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o gmon.o crt1.o crti.o crtn.o gcrt1.o
diff --git a/gcc/config/sparc/t-sp64 b/gcc/config/sparc/t-sp64
deleted file mode 100755
index 99acd5d..0000000
--- a/gcc/config/sparc/t-sp64
+++ /dev/null
@@ -1,2 +0,0 @@
-LIBGCC1 =
-CROSS_LIBGCC1 =
diff --git a/gcc/config/sparc/t-sp86x b/gcc/config/sparc/t-sp86x
deleted file mode 100755
index 933fe09..0000000
--- a/gcc/config/sparc/t-sp86x
+++ /dev/null
@@ -1,21 +0,0 @@
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = sparc/lb1spc.asm
-LIB1ASMFUNCS = _divsi3 _modsi3
-
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' > dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-MULTILIB_OPTIONS = mlittle-endian-data
-MULTILIB_DIRNAMES = little
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
diff --git a/gcc/config/sparc/t-sparcbare b/gcc/config/sparc/t-sparcbare
deleted file mode 100755
index 8bd978b..0000000
--- a/gcc/config/sparc/t-sparcbare
+++ /dev/null
@@ -1,26 +0,0 @@
-# configuration file for a bare sparc cpu
-
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = sparc/lb1spc.asm
-LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-# MULTILIB_OPTIONS should have msparclite too, but we'd have to make
-# gas build...
-MULTILIB_OPTIONS = msoft-float mcpu=v8
-MULTILIB_DIRNAMES = soft v8
-MULTILIB_MATCHES = msoft-float=mno-fpu mcpu?v8=mv8
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/sparc/t-sparclite b/gcc/config/sparc/t-sparclite
deleted file mode 100755
index 7cdfbb0..0000000
--- a/gcc/config/sparc/t-sparclite
+++ /dev/null
@@ -1,24 +0,0 @@
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = sparc/lb1spl.asm
-LIB1ASMFUNCS = _divsi3 _udivsi3 _modsi3 _umodsi3
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' > dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-MULTILIB_OPTIONS = mfpu mflat
-MULTILIB_DIRNAMES =
-MULTILIB_MATCHES = mfpu=mhard-float mfpu=mcpu?f934
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/sparc/t-splet b/gcc/config/sparc/t-splet
deleted file mode 100755
index 3329e0b..0000000
--- a/gcc/config/sparc/t-splet
+++ /dev/null
@@ -1,22 +0,0 @@
-# configuration file for a bare sparclet cpu, aout format files
-
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = sparc/lb1spc.asm
-LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	cat $(srcdir)/config/fp-bit.c > dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-MULTILIB_OPTIONS = mlittle-endian mflat
-MULTILIB_DIRNAMES = little flat
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/sparc/t-sunos40 b/gcc/config/sparc/t-sunos40
deleted file mode 100755
index 3e10575..0000000
--- a/gcc/config/sparc/t-sunos40
+++ /dev/null
@@ -1,7 +0,0 @@
-# SunOS 4.0.* 
-# /bin/as doesn't recognize the v8 instructions, so we can't do a v8
-# multilib build.
-
-LIBGCC1 =
-CROSS_LIBGCC1 =
-LIBGCC1_TEST =
diff --git a/gcc/config/sparc/t-sunos41 b/gcc/config/sparc/t-sunos41
deleted file mode 100755
index 5783d6a..0000000
--- a/gcc/config/sparc/t-sunos41
+++ /dev/null
@@ -1,16 +0,0 @@
-# SunOS 4.1.*
-
-LIBGCC1 =
-CROSS_LIBGCC1 =
-LIBGCC1_TEST =
-
-MULTILIB_OPTIONS = fpic/fPIC mcpu=v8
-MULTILIB_DIRNAMES = pic ucpic v8
-MULTILIB_MATCHES = mcpu?v8=mv8
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
-# The native linker doesn't handle linking -fpic code with -fPIC code.  Ugh.
-# We cope by building both variants of libgcc.
-#TARGET_LIBGCC2_CFLAGS = -fPIC
diff --git a/gcc/config/sparc/t-vxsparc b/gcc/config/sparc/t-vxsparc
deleted file mode 100755
index 0c7a14a..0000000
--- a/gcc/config/sparc/t-vxsparc
+++ /dev/null
@@ -1,17 +0,0 @@
-LIBGCC1 =
-CROSS_LIBGCC1 =
-
-# We don't want to build .umul, etc., because VxWorks provides them,
-# which means that libgcc1-test will fail.
-LIBGCC1_TEST =
-
-# We don't want to put exit in libgcc.a for VxWorks, because VxWorks
-# does not have _exit.
-TARGET_LIBGCC2_CFLAGS = -Dexit=unused_exit
-
-MULTILIB_OPTIONS=msoft-float mv8
-MULTILIB_DIRNAMES=soft v8
-MULTILIB_MATCHES=msoft-float=mno-fpu
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/sparc/vxsim.h b/gcc/config/sparc/vxsim.h
deleted file mode 100755
index 6c80375..0000000
--- a/gcc/config/sparc/vxsim.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SPARC VxSim
-   Copyright 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Supposedly the same as vanilla sparc svr4, except for the stuff below: */
-#include "sparc/sysv4.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-DCPU=SIMSPARCSOLARIS -D__vxworks -D__vxworks__ -Dsparc -D__svr4__ -D__SVR4 \
-  -Asystem(embedded) -Asystem(svr4) -Acpu(sparc) -Amachine(sparc)\
-  -D__GCC_NEW_VARARGS__"
-
-#undef CPP_SPEC
-#define CPP_SPEC ""
-
-#undef CC1_SPEC
-#define CC1_SPEC "-fno-builtin %{sun4:} %{target:}"
-
-/* The sun bundled assembler doesn't accept -Yd, (and neither does gas).
-   It's safe to pass -s always, even if -g is not used. */
-#undef ASM_SPEC
-#define ASM_SPEC \
-  "%{V} %{v:%{!V:-V}} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s \
-   %{fpic:-K PIC} %{fPIC:-K PIC}"
-
-/* However it appears that Solaris 2.0 uses the same reg numbering as
-   the old BSD-style system did. */
-
-#undef DBX_REGISTER_NUMBER
-/* Same as sparc.h */
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* We use stabs-in-elf for debugging, because that is what the native
-   toolchain uses.  */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* The Solaris 2 assembler uses .skip, not .zero, so put this back. */
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.skip %u\n", (SIZE))
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fputs ("\t.local\t", (FILE));		\
-  assemble_name ((FILE), (NAME));					\
-  putc ('\n', (FILE));							\
-  ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);			\
-} while (0)
-
-#undef COMMON_ASM_OP
-#define COMMON_ASM_OP "\t.common"
-
-/* This is how to output a definition of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef  ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".L%s%d:\n", PREFIX, NUM)
-
-/* This is how to output a reference to an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#undef  ASM_OUTPUT_INTERNAL_LABELREF
-#define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".L%s%d", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#undef  ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*.L%s%d", PREFIX, NUM)
-
-
-
-#undef LIB_SPEC
-#define LIB_SPEC ""
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC ""
-
-#undef LINK_SPEC
-#define LINK_SPEC "-r"
-
-/* This defines which switch letters take arguments.
-   It is as in svr4.h but with -R added.  */
-
-#undef SWITCH_TAKES_ARG
-#define SWITCH_TAKES_ARG(CHAR) \
-  (   (CHAR) == 'D' \
-   || (CHAR) == 'U' \
-   || (CHAR) == 'o' \
-   || (CHAR) == 'e' \
-   || (CHAR) == 'u' \
-   || (CHAR) == 'I' \
-   || (CHAR) == 'm' \
-   || (CHAR) == 'L' \
-   || (CHAR) == 'R' \
-   || (CHAR) == 'A' \
-   || (CHAR) == 'h' \
-   || (CHAR) == 'z')
-
-/* ??? This does not work in SunOS 4.x, so it is not enabled in sparc.h.
-   Instead, it is enabled here, because it does work under Solaris.  */
-/* Define for support of TFmode long double and REAL_ARITHMETIC.
-   Sparc ABI says that long double is 4 words.  */
-#define LONG_DOUBLE_TYPE_SIZE 64
diff --git a/gcc/config/sparc/vxsparc.h b/gcc/config/sparc/vxsparc.h
deleted file mode 100755
index 18ce6ed..0000000
--- a/gcc/config/sparc/vxsparc.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Vxworks SPARC version.
-   Copyright (C) 1994, 1996 Free Software Foundation, Inc.
-   Contributed by David Henkel-Wallace (gumby@cygnus.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "sparc/aout.h"
-
-/* Specify what to link with.  */
-/* VxWorks does all the library stuff itself.  */
-
-#undef LIB_SPEC
-#define LIB_SPEC ""
-
-/* Provide required defaults for linker -e. */
-#undef LINK_SPEC
-#define LINK_SPEC "%{!nostdlib:%{!r*:%{!e*:-e start}}}"
-
-/* VxWorks provides the functionality of crt0.o and friends itself.  */
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dsparc -Acpu(sparc) -Amachine(sparc)"
-
-/* Note that we define CPU here even if the user has specified -ansi.
-   This violates user namespace, but the VxWorks headers, and potentially
-   user code, all explicitly rely upon the definition of CPU in order to get
-   the proper processor information.  */
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) -DCPU=SPARC"
-
-#undef PTRDIFF_TYPE
-#undef SIZE_TYPE
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-
-#define PTRDIFF_TYPE "long int"
-#define SIZE_TYPE "unsigned int"
-#define WCHAR_TYPE "char"
-#define WCHAR_TYPE_SIZE 8
-
-/* US Software GOFAST library support.  */
-#include "gofast.h"
-#undef INIT_SUBTARGET_OPTABS
-#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS
diff --git a/gcc/config/sparc/x-sysv4 b/gcc/config/sparc/x-sysv4
deleted file mode 100755
index 2a661e3..0000000
--- a/gcc/config/sparc/x-sysv4
+++ /dev/null
@@ -1,2 +0,0 @@
-X_CFLAGS=-DSVR4
-ALLOCA=alloca.o
diff --git a/gcc/config/sparc/xm-linux.h b/gcc/config/sparc/xm-linux.h
deleted file mode 100755
index 691c7d1..0000000
--- a/gcc/config/sparc/xm-linux.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Configuration for GCC for SPARC running Linux-based GNU systems.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Eddie C. Dost (ecd@skynet.be)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#ifndef inhibit_libc
-#include <alloca.h>
-#include <stdlib.h>
-#include <string.h>
-#endif
diff --git a/gcc/config/sparc/xm-lynx.h b/gcc/config/sparc/xm-lynx.h
deleted file mode 100755
index 90fef85..0000000
--- a/gcc/config/sparc/xm-lynx.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Configuration for GNU C-compiler for sparc platforms running LynxOS.
-   Copyright (C) 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <xm-lynx.h>
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_WORDS_BIG_ENDIAN 1
-
-/* Include <sys/wait.h> to define the exit status access macros.  */
-#include <sys/types.h>
-#include <sys/wait.h>
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-
-#include "tm.h"
diff --git a/gcc/config/sparc/xm-netbsd.h b/gcc/config/sparc/xm-netbsd.h
deleted file mode 100755
index 5f11b8d..0000000
--- a/gcc/config/sparc/xm-netbsd.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/* Configuration for GCC for Sun SPARC running NetBSD as host.  */
-
-#include <sparc/xm-sparc.h>
-#include <xm-netbsd.h>
diff --git a/gcc/config/sparc/xm-pbd.h b/gcc/config/sparc/xm-pbd.h
deleted file mode 100755
index 1c3f475..0000000
--- a/gcc/config/sparc/xm-pbd.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Host environment for the tti "Unicom" PBB 68020 boards */
-
-#include "sparc/xm-sparc.h"
-
-#define USG
-
-#ifndef __GNUC__
-#define USE_C_ALLOCA
-#endif
-
diff --git a/gcc/config/sparc/xm-sol2.h b/gcc/config/sparc/xm-sol2.h
deleted file mode 100755
index 5613b08..0000000
--- a/gcc/config/sparc/xm-sol2.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/* If not compiled with GNU C, include the system's <alloca.h> header.  */
-#ifndef __GNUC__
-#include <alloca.h>
-#endif
diff --git a/gcc/config/sparc/xm-sp64.h b/gcc/config/sparc/xm-sp64.h
deleted file mode 100755
index b673161..0000000
--- a/gcc/config/sparc/xm-sp64.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Configuration for GCC for Sparc v9 running 64-bit native.
-   Copyright (C) 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <sparc/xm-sparc.h>
-
-/* This describes the machine the compiler is hosted on.  */
-#if defined(__arch64__) || defined(__sparc_v9__) || defined(__sparcv9)
-#undef HOST_BITS_PER_LONG
-#define HOST_BITS_PER_LONG 64
-#endif
diff --git a/gcc/config/sparc/xm-sparc.h b/gcc/config/sparc/xm-sparc.h
deleted file mode 100755
index e553a0d..0000000
--- a/gcc/config/sparc/xm-sparc.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Configuration for GNU C-compiler for Sun Sparc.
-   Copyright (C) 1988, 1993, 1995, 1997 Free Software Foundation, Inc.
-   Contributed by Michael Tiemann (tiemann@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Doubles are stored in memory with the high order word first.  This
-   matters when cross-compiling.  */
-#define HOST_WORDS_BIG_ENDIAN 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* If compiled with Sun CC, the use of alloca requires this #include.  */
-#ifndef __GNUC__
-#include "alloca.h"
-#endif
diff --git a/gcc/config/sparc/xm-sysv4-64.h b/gcc/config/sparc/xm-sysv4-64.h
deleted file mode 100755
index c506d22..0000000
--- a/gcc/config/sparc/xm-sysv4-64.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Configuration for GCC for Sparc v9 running 64-bit native.
-   Copyright (C) 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <sparc/xm-sysv4.h>
-
-/* This describes the machine the compiler is hosted on.  */
-#if defined(__arch64__) || defined(__sparc_v9__) || defined(__sparcv9)
-#undef HOST_BITS_PER_LONG
-#define HOST_BITS_PER_LONG 64
-#endif
diff --git a/gcc/config/sparc/xm-sysv4.h b/gcc/config/sparc/xm-sysv4.h
deleted file mode 100755
index 6e663d1..0000000
--- a/gcc/config/sparc/xm-sysv4.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Configuration for GNU C-compiler for Sun Sparc running System V.4.
-   Copyright (C) 1992, 1993, 1998 Free Software Foundation, Inc.
-   Contributed by Ron Guilmette (rfg@netcom.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Doubles are stored in memory with the high order word first.  This
-   matters when cross-compiling.  */
-#define HOST_WORDS_BIG_ENDIAN 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-#ifndef __GNUC__
-#define ONLY_INT_FIELDS
-#endif
diff --git a/gcc/config/spur/spur.c b/gcc/config/spur/spur.c
deleted file mode 100755
index 83e37b8..0000000
--- a/gcc/config/spur/spur.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/* Subroutines for insn-output.c for SPUR.  Adapted from routines for
-   the Motorola 68000 family.
-   Copyright (C) 1988, 1991, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-
-static rtx find_addr_reg ();
-
-char *
-output_compare (operands, opcode, exchange_opcode, 
-		neg_opcode, neg_exchange_opcode)
-     rtx *operands;
-     char *opcode;
-     char *exchange_opcode;
-     char *neg_opcode;
-     char *neg_exchange_opcode;
-{
-  static char buf[100];
-  operands[2] = operands[0];
-  if (GET_CODE (cc_prev_status.value1) == CONST_INT)
-    {
-      operands[1] = cc_prev_status.value1;
-      operands[0] = cc_prev_status.value2;
-      opcode = exchange_opcode, neg_opcode = neg_exchange_opcode;
-    }
-  else
-    {
-      operands[0] = cc_prev_status.value1;
-      operands[1] = cc_prev_status.value2;
-    }
-  if (TARGET_LONG_JUMPS)
-    sprintf (buf,
-	     "cmp_br_delayed %s,%%0,%%1,1f\n\tnop\n\tjump %%l2\n\tnop\n1:",
-	     neg_opcode);
-  else 
-    sprintf (buf, "cmp_br_delayed %s,%%0,%%1,%%l2\n\tnop", opcode);
-  return buf;
-}
-
-/* Return the best assembler insn template
-   for moving operands[1] into operands[0] as a fullword.  */
-
-static char *
-singlemove_string (operands)
-     rtx *operands;
-{
-  if (GET_CODE (operands[0]) == MEM)
-    return "st_32 %r1,%0";
-  if (GET_CODE (operands[1]) == MEM)
-    return "ld_32 %0,%1\n\tnop";
-  if (GET_CODE (operands[1]) == REG)
-    return "add_nt %0,%1,$0";
-  return "add_nt %0,r0,%1";
-}
-
-/* Output assembler code to perform a doubleword move insn
-   with operands OPERANDS.  */
-
-char *
-output_move_double (operands)
-     rtx *operands;
-{
-  enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
-  rtx latehalf[2];
-  rtx addreg0 = 0, addreg1 = 0;
-
-  /* First classify both operands.  */
-
-  if (REG_P (operands[0]))
-    optype0 = REGOP;
-  else if (offsettable_memref_p (operands[0]))
-    optype0 = OFFSOP;
-  else if (GET_CODE (operands[0]) == MEM)
-    optype0 = MEMOP;
-  else
-    optype0 = RNDOP;
-
-  if (REG_P (operands[1]))
-    optype1 = REGOP;
-  else if (CONSTANT_P (operands[1]))
-    optype1 = CNSTOP;
-  else if (offsettable_memref_p (operands[1]))
-    optype1 = OFFSOP;
-  else if (GET_CODE (operands[1]) == MEM)
-    optype1 = MEMOP;
-  else
-    optype1 = RNDOP;
-
-  /* Check for the cases that the operand constraints are not
-     supposed to allow to happen.  Abort if we get one,
-     because generating code for these cases is painful.  */
-
-  if (optype0 == RNDOP || optype1 == RNDOP)
-    abort ();
-
-  /* If an operand is an unoffsettable memory ref, find a register
-     we can increment temporarily to make it refer to the second word.  */
-
-  if (optype0 == MEMOP)
-    addreg0 = find_addr_reg (XEXP (operands[0], 0));
-
-  if (optype1 == MEMOP)
-    addreg1 = find_addr_reg (XEXP (operands[1], 0));
-
-  /* Ok, we can do one word at a time.
-     Normally we do the low-numbered word first,
-     but if either operand is autodecrementing then we
-     do the high-numbered word first.
-
-     In either case, set up in LATEHALF the operands to use
-     for the high-numbered word and in some cases alter the
-     operands in OPERANDS to be suitable for the low-numbered word.  */
-
-  if (optype0 == REGOP)
-    latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  else if (optype0 == OFFSOP)
-    latehalf[0] = adj_offsettable_operand (operands[0], 4);
-  else
-    latehalf[0] = operands[0];
-
-  if (optype1 == REGOP)
-    latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-  else if (optype1 == OFFSOP)
-    latehalf[1] = adj_offsettable_operand (operands[1], 4);
-  else if (optype1 == CNSTOP)
-    {
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	{
-	  latehalf[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
-	  operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-	}
-      else if (CONSTANT_P (operands[1]))
-	latehalf[1] = const0_rtx;
-    }
-  else
-    latehalf[1] = operands[1];
-
-  /* If the first move would clobber the source of the second one,
-     do them in the other order.  This happens only for registers;
-     such overlap can't happen in memory unless the user explicitly
-     sets it up, and that is an undefined circumstance.  */
-
-  if (optype0 == REGOP && optype1 == REGOP
-      && REGNO (operands[0]) == REGNO (latehalf[1]))
-    {
-      /* Make any unoffsettable addresses point at high-numbered word.  */
-      if (addreg0)
-	output_asm_insn ("add_nt %0,%0,$4", &addreg0);
-      if (addreg1)
-	output_asm_insn ("add_nt %0,%0,$4", &addreg1);
-
-      /* Do that word.  */
-      output_asm_insn (singlemove_string (latehalf), latehalf);
-
-      /* Undo the adds we just did.  */
-      if (addreg0)
-	output_asm_insn ("add_nt %0,%0,$-4", &addreg0);
-      if (addreg1)
-	output_asm_insn ("add_nt %0,%0,$-4", &addreg0);
-
-      /* Do low-numbered word.  */
-      return singlemove_string (operands);
-    }
-
-  /* Normal case: do the two words, low-numbered first.  */
-
-  output_asm_insn (singlemove_string (operands), operands);
-
-  /* Make any unoffsettable addresses point at high-numbered word.  */
-  if (addreg0)
-    output_asm_insn ("add_nt %0,%0,$4", &addreg0);
-  if (addreg1)
-    output_asm_insn ("add_nt %0,%0,$4", &addreg1);
-
-  /* Do that word.  */
-  output_asm_insn (singlemove_string (latehalf), latehalf);
-
-  /* Undo the adds we just did.  */
-  if (addreg0)
-    output_asm_insn ("add_nt %0,%0,$-4", &addreg0);
-  if (addreg1)
-    output_asm_insn ("add_nt %0,%0,$-4", &addreg1);
-
-  return "";
-}
-
-static char *
-output_fp_move_double (operands)
-     rtx *operands;
-{
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return "fmov %0,%1";
-      if (GET_CODE (operands[1]) == REG)
-	{
-	  rtx xoperands[2];
-	  int offset = - get_frame_size () - 8;
-	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-	  xoperands[0] = GEN_INT (offset + 4);
-	  output_asm_insn ("st_32 %1,r25,%0", xoperands);
-	  xoperands[1] = operands[1];
-	  xoperands[0] = GEN_INT (offset);
-	  output_asm_insn ("st_32 %1,r25,%0", xoperands);
-	  xoperands[1] = operands[0];
-	  output_asm_insn ("ld_dbl %1,r25,%0\n\tnop", xoperands);
-	  return "";
-	}
-      return "ld_dbl %0,%1\n\tnop";
-    }
-  else if (FP_REG_P (operands[1]))
-    {
-      if (GET_CODE (operands[0]) == REG)
-	{
-	  rtx xoperands[2];
-	  int offset = - get_frame_size () - 8;
-	  xoperands[0] = GEN_INT (offset);
-	  xoperands[1] = operands[1];
-	  output_asm_insn ("st_dbl %1,r25,%0", xoperands);
-	  xoperands[1] = operands[0];
-	  output_asm_insn ("ld_32 %1,r25,%0\n\tnop", xoperands);
-	  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-	  xoperands[0] = GEN_INT (offset + 4);
-	  output_asm_insn ("ld_32 %1,r25,%0\n\tnop", xoperands);
-	  return "";
-	}
-      return "st_dbl %1,%0";
-    }
-}
-
-/* Return a REG that occurs in ADDR with coefficient 1.
-   ADDR can be effectively incremented by incrementing REG.  */
-
-static rtx
-find_addr_reg (addr)
-     rtx addr;
-{
-  while (GET_CODE (addr) == PLUS)
-    {
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-	addr = XEXP (addr, 0);
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	addr = XEXP (addr, 1);
-      else if (CONSTANT_P (XEXP (addr, 0)))
-	addr = XEXP (addr, 1);
-      else if (CONSTANT_P (XEXP (addr, 1)))
-	addr = XEXP (addr, 0);
-      else
-	abort ();
-    }
-  if (GET_CODE (addr) == REG)
-    return addr;
-  abort ();
-}
-
-/* Generate code to add a large integer constant to register, reg, storing
- * the result in a register, target.  Offset must be 27-bit signed quantity */
-
-static char *
-output_add_large_offset (target, reg, offset)
-     rtx target, reg;
-     int offset;
-{
-  rtx operands[3];
-  int high, n, i;
-  operands[0] = target, operands[1] = reg;
-    
-  for (high = offset, n = 0; 
-       (unsigned) (high + 0x2000) >= 0x4000; 
-       high >>= 1, n += 1)
-    ;
-  operands[2] = GEN_INT (high);
-  output_asm_insn ("add_nt r2,r0,%2", operands);
-  i = n;
-  while (i >= 3)
-    output_asm_insn ("sll r2,r2,$3", operands), i -= 3;
-  if (i == 2) 
-    output_asm_insn ("sll r2,r2,$2", operands);
-  else if (i == 1)
-    output_asm_insn ("sll r2,r2,$1", operands);
-  output_asm_insn ("add_nt %0,r2,%1", operands);
-  if (offset - (high << n) != 0)
-    {
-      operands[2] = GEN_INT (offset - (high << n));
-      output_asm_insn ("add_nt %0,%0,%2", operands);
-    }
-  return "";
-}
-
-/* Additional TESTFN for matching. Like immediate_operand, but matches big
- * constants */
-
-int
-big_immediate_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == CONST_INT);
-}
diff --git a/gcc/config/spur/spur.h b/gcc/config/spur/spur.h
deleted file mode 100755
index e6d058a..0000000
--- a/gcc/config/spur/spur.h
+++ /dev/null
@@ -1,1051 +0,0 @@
-/* Definitions of target machine for GNU compiler, for SPUR chip.
-   Copyright (C) 1988, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Note that some other tm.h files include this one and then override
-   many of the definitions that relate to assembler syntax.  */
-
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dspur -Acpu(spur) -Amachine(spur)"
-
-/* Link with libg.a when debugging, for dbx's sake.  */
-
-#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
-
-/* Print subsidiary information on the compiler version in use.  */
-#define TARGET_VERSION fprintf (stderr, " (spur)");
-
-/* Run-time compilation parameters selecting different hardware subsets.
-
-   On the SPUR, we don't yet need any.  */
-
-extern int target_flags;
-
-/* Nonzero if we should generate code to use the fpu.  */
-#define TARGET_FPU (target_flags & 1)
-
-/* Nonzero if we should expand constant shifts into series of shift
-   instructions.  */
-#define TARGET_EXPAND_SHIFTS (target_flags & 2)
-
-/* Nonzero if we should generate long jumps for compares. */
-#define TARGET_LONG_JUMPS (target_flags & 4)
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  { {"fpu", 1},			\
-    {"soft-float", -1},		\
-    {"expand-shifts", 2},       \
-    {"lib-shifts", -2},		\
-    {"long-jumps", 4},		\
-    {"short-jumps", -4},	\
-    { "", TARGET_DEFAULT}}
-
-#define TARGET_DEFAULT 0
-
-/* target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is a moot question on the SPUR due to the lack of bit-field insns.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is not true on SPUR.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.  */
-/* For SPUR we can decide arbitrarily
-   since there are no machine instructions for them.  */
-#define WORDS_BIG_ENDIAN 0
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 64
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 64
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 32
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 64
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   SPUR has 32 fullword registers and 15 floating point registers.  */
-
-#define FIRST_PSEUDO_REGISTER 47
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   On SPUR, this includes all the global registers
-   and the callee return address register.  */
-#define FIXED_REGISTERS  \
- {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 0, 0, 0, 0, 0,		\
-  0, 0, 0, 0, 0, 0, 0, 0, 1, 1,	\
-  1, 0, 0, 0, 0, 0,		\
-  1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS  \
- {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-  1, 0, 0, 0, 0, 0,		\
-  0, 0, 0, 0, 0, 0, 0, 0, 1, 1,	\
-  1, 1, 1, 1, 1, 1,		\
-  1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On SPUR, ordinary registers hold 32 bits worth;
-   a single floating point register is always enough for
-   anything that can be stored in them at all.  */
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((REGNO) >= 32 ? GET_MODE_NUNITS ((MODE))	\
-   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On SPUR, the cpu registers can hold any mode but the float registers
-   can hold only floating point.  And they can't hold anything if use
-   of hardware floating point is disabled.  */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-  (((REGNO) < 32							\
-    && (REGNO) + ((GET_MODE_UNIT_SIZE ((MODE)) + 3) / 4) <= 32)		\
-   || (TARGET_FPU && ((MODE) == SFmode || (MODE) == DFmode		\
-		      || (MODE) == SCmode || (MODE) == DCmode)))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  (((MODE1) == SFmode || (MODE1) == DFmode		\
-    || (MODE1) == SCmode || (MODE1) == DCmode)		\
-   == ((MODE2) == SFmode || (MODE2) == DFmode		\
-       || (MODE2) == SCmode || (MODE2) == DCmode))
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* SPUR pc isn't overloaded on a register that the compiler knows about.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 4
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 25
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 1
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 25
-
-/* Register in which static-chain is passed to a function.  */
-/* ??? */
-#define STATIC_CHAIN_REGNUM 8
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 27
-#define STRUCT_VALUE_INCOMING_REGNUM 11
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-/* The 68000 has two kinds of registers, hence four classes.  */
-
-enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS {{0, 0}, {-1, 0}, {0, 0x7fff}, {-1, 0x7fff}}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) \
- ((REGNO) >= 32 ? FP_REGS : GENERAL_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS GENERAL_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'f' ? FP_REGS : NO_REGS)
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   For SPUR, `I' is used for the range of constants an insn
-   can actually contain.
-   `J' is used for the range which is just zero (since that is R0).
-   `K' is used for the 5-bit operand of a compare insns.  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'I' ? (unsigned) ((VALUE) + 0x2000) < 0x4000	\
-   : (C) == 'J' ? (VALUE) == 0				\
-   : (C) == 'K' ? (unsigned) (VALUE) < 0x20		\
-   : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  	\
-  ((C) == 'G' && CONST_DOUBLE_HIGH (VALUE) == 0		\
-   && CONST_DOUBLE_LOW (VALUE) == 0)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-/* On SPUR, this is the size of MODE in words,
-   except in the FP regs, where a single reg is always enough.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- ((CLASS) == FP_REGS ? 1			\
-  : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On SPUR, don't define this because there are no push insns.  */
-/*  #define PUSH_ROUNDING(BYTES) */
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-/* On SPUR the value is found in the second "output" register.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), 27)
-
-/* But the called function leaves it in the second "input" register.  */
-
-#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), 11)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, 27)
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.
-   On SPUR, the first "output" reg is the only register thus used.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 27)
-
-/* 1 if N is a possible register number for function argument passing.
-   On SPUR, these are the "output" registers.  */
-
-#define FUNCTION_ARG_REGNO_P(N) ((N) < 32 && (N) > 26)
-
-/* Define this macro if the target machine has "register windows".  This
-   C expression returns the register number as seen by the called function
-   corresponding to register number OUT as seen by the calling function.
-   Return OUT if register number OUT is not an outbound register.  */
-
-#define INCOMING_REGNO(OUT) \
- (((OUT) < 27 || (OUT) > 31) ? (OUT) : (OUT) - 16)
-
-/* Define this macro if the target machine has "register windows".  This
-   C expression returns the register number as seen by the calling function
-   corresponding to register number IN as seen by the called function.
-   Return IN if register number IN is not an inbound register.  */
-
-#define OUTGOING_REGNO(IN) \
- (((IN) < 11 || (IN) > 15) ? (IN) : (IN) + 16)
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On SPUR, this is a single integer, which is a number of words
-   of arguments scanned so far (including the invisible argument,
-   if any, which holds the structure-value-address).
-   Thus 5 or more means all following args should go on the stack.  */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On SPUR, the offset normally starts at 0, but starts at 4 bytes
-   when the function gets a structure-value-address as an
-   invisible first argument.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM) = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE ((FNTYPE)))))
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM) += ((MODE) != BLKmode			\
-	    ? (GET_MODE_SIZE (MODE) + 3) / 4	\
-	    : (int_size_in_bytes (TYPE) + 3) / 4))
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On SPUR the first five words of args are normally in registers
-   and the rest are pushed.  But any arg that won't entirely fit in regs
-   is pushed.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)		\
-(5 >= ((CUM)						\
-       + ((MODE) == BLKmode				\
-	  ? (int_size_in_bytes (TYPE) + 3) / 4		\
-	  : (GET_MODE_SIZE (MODE) + 3) / 4))		\
- ? gen_rtx (REG, (MODE), 27 + (CUM))			\
- : 0)
-
-/* Define where a function finds its arguments.
-   This is different from FUNCTION_ARG because of register windows.  */
-
-#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED)	\
-(5 >= ((CUM)						\
-       + ((MODE) == BLKmode				\
-	  ? (int_size_in_bytes (TYPE) + 3) / 4		\
-	  : (GET_MODE_SIZE (MODE) + 3) / 4))		\
- ? gen_rtx (REG, (MODE), 11 + (CUM))			\
- : 0)
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-/* On spur, move-double insns between fpu and cpu need an 8-byte block
-   of memory.  If any fpu reg is used in the function, we allocate
-   such a block here, at the bottom of the frame, just in case it's needed.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)				\
-{								\
-  extern char call_used_regs[];					\
-  extern int current_function_pretend_args_size;		\
-  int fsize = ((SIZE) + 7) & ~7;				\
-  int nregs, i, fp_used = 0;					\
-  for (i = 32, nregs = 0; i < FIRST_PSEUDO_REGISTER; i++)	\
-    {								\
-      if (regs_ever_live[i] && ! call_used_regs[i])		\
-        nregs++;						\
-      if (regs_ever_live[i]) fp_used = 1;			\
-    }								\
-  if (fp_used) fsize += 8;					\
-  fprintf (FILE, "0:\trd_special r24,pc\n");			\
-  fprintf (FILE, "\tand r24,r24,$~0x3\n");			\
-  fprintf (FILE, "\tadd_nt r25,r4,$%d\n",			\
-	   - current_function_pretend_args_size);		\
-  if (fsize + nregs != 0 || current_function_pretend_args_size > 0)\
-    {								\
-      int n = - fsize - nregs * 16;				\
-      if (n >= -8192)						\
-        fprintf (FILE, "\tadd_nt r4,r25,$%d\n", n);		\
-      else							\
-        {							\
-	  fprintf (FILE, "\tadd_nt r4,r25,$-8192\n");		\
-	  n += 8192;						\
-          while (n < -8192)					\
-            fprintf (FILE, "\tadd_nt r4,r4,$-8192\n"), n += 8192; \
-	  if (n != 0)						\
-            fprintf (FILE, "\tadd_nt r4,r4,$%d\n", n);		\
-        }							\
-      }								\
-  for (i = 32, nregs = 0; i < FIRST_PSEUDO_REGISTER; i++)	\
-    if (regs_ever_live[i] && ! call_used_regs[i])		\
-      {								\
-        fprintf (FILE, "\tst_ext1 %s,r4,$%d\n",			\
-	         reg_names[i], 8 * nregs++);			\
-        fprintf (FILE, "\tst_ext2 %s,r4,$%d\n",			\
-	         reg_names[i], 8 * nregs++);			\
-      }								\
-}
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   abort ();
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-extern int current_function_calls_alloca;
-extern int current_function_pretend_args_size;
-
-#define EXIT_IGNORE_STACK	\
- (get_frame_size () != 0	\
-  || current_function_calls_alloca || current_function_pretend_args_size)
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE)				\
-{								\
-  extern char call_used_regs[];					\
-  extern int current_function_calls_alloca;			\
-  extern int current_function_pretend_args_size;		\
-  int fsize = ((SIZE) + 7) & ~7;				\
-  int nregs, i, fp_used = 0;					\
-  for (i = 32, nregs = 0; i < FIRST_PSEUDO_REGISTER; i++)	\
-    {								\
-      if (regs_ever_live[i] && ! call_used_regs[i])		\
-	nregs++;						\
-      if (regs_ever_live[i]) fp_used = 1;			\
-    }								\
-  if (fp_used) fsize += 8;					\
-  if (nregs != 0)						\
-    {								\
-      fprintf (FILE, "\tadd_nt r4,r25,$%d\n", - fsize - nregs * 16); \
-      for (i = 32, nregs = 0; i < FIRST_PSEUDO_REGISTER; i++)	\
-        if (regs_ever_live[i] && ! call_used_regs[i])		\
-	  {							\
-            fprintf (FILE, "\tld_ext1 %s,r4,$%d\n\tnop\n",	\
-		     reg_names[i], 8 * nregs++);		\
-            fprintf (FILE, "\tld_ext2 %s,r4,$%d\n\tnop\n",	\
-		     reg_names[i], 8 * nregs++);		\
-	  }							\
-    }								\
-  if (fsize != 0 || nregs != 0 || current_function_calls_alloca	\
-      || current_function_pretend_args_size > 0)		\
-    fprintf (FILE, "\tadd_nt r4,r25,$%d\n",			\
-	     current_function_pretend_args_size);		\
-  fprintf (FILE, "\treturn r10,$8\n\tnop\n");			\
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
-#define REGNO_OK_FOR_FP_P(REGNO) \
-(((REGNO) ^ 0x20) < 14 || (unsigned) (reg_renumber[REGNO] ^ 0x20) < 14)
-
-/* Now macros that check whether X is a register and also,
-   strictly, whether it is in a specified class.
-
-   These macros are specific to the SPUR, and may be used only
-   in code for printing assembler insns and in conditions for
-   define_optimization.  */
-
-/* 1 if X is an fp register.  */
-
-#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X)		\
- ((GET_CODE (X) == CONST_INT			\
-   && (unsigned) (INTVAL (X) + 0x2000) < 0x4000)\
-  || (GET_CODE (X) == SYMBOL_REF && (X)->unchanging))
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   On SPUR, the actual legitimate addresses must be REG+SMALLINT or REG+REG.
-   Actually, REG+REG is not legitimate for stores, so 
-   it is obtained only by combination on loads.
-   We can treat a SYMBOL_REF as legitimate if it is part of this
-   function's constant-pool, because such addresses can actually
-   be output as REG+SMALLINT.  */
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
-{ if (GET_CODE (X) == REG			\
-      && REG_OK_FOR_BASE_P (X))			\
-    goto ADDR;					\
-  if (GET_CODE (X) == SYMBOL_REF && (X)->unchanging)	\
-    goto ADDR;					\
-  if (GET_CODE (X) == PLUS			\
-      && GET_CODE (XEXP (X, 0)) == REG		\
-      && REG_OK_FOR_BASE_P (XEXP (X, 0)))	\
-    {						\
-      if (GET_CODE (XEXP (X, 1)) == CONST_INT	\
-	  && INTVAL (XEXP (X, 1)) >= -0x2000	\
-	  && INTVAL (XEXP (X, 1)) < 0x2000)	\
-	goto ADDR;				\
-    }						\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.  */
-
-/* On SPUR, change REG+N into REG+REG, and REG+(X*Y) into REG+REG.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)	\
-{ if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1)))	\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 0),			\
-		   copy_to_mode_reg (SImode, XEXP (X, 1)));	\
-  if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0)))	\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 1),			\
-		   copy_to_mode_reg (SImode, XEXP (X, 0)));	\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT)	\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 1),			\
-		   force_operand (XEXP (X, 0), 0));		\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT)	\
-    (X) = gen_rtx (PLUS, SImode, XEXP (X, 0),			\
-		   force_operand (XEXP (X, 1), 0));		\
-  if (memory_address_p (MODE, X))				\
-    goto WIN; }
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the SPUR this is never true.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 4
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* This is BSD, so it wants DBX format.  */
-#define DBX_DEBUGGING_INFO
-
-/* Do not break .stabs pseudos into continuations.  */
-#define DBX_CONTIN_LENGTH 0
-
-/* Don't try to use the `x' type-cross-reference character in DBX data.
-   Also has the consequence of putting each struct, union or enum
-   into a separate .stabs, containing only cross-refs to the others.  */
-#define DBX_NO_XREFS
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE SImode
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap.  */
-#define NO_FUNCTION_CSE
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    if (INTVAL (RTX) < 0x2000 && INTVAL (RTX) >= -0x2000) return 1; \
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 2;							\
-  case CONST_DOUBLE:						\
-    return 4;
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  */
-
-/* (None are needed on SPUR.)  */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-/* The SPUR does not really have a condition code.  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-{ CC_STATUS_INIT; }
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(FILE)
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",		\
- "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",	\
- "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",	\
- "r30", "r31",								\
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",	\
- "f10", "f11", "f12", "f13", "f14" }
-
-/* How to renumber registers for dbx and gdb.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-  fprintf (FILE, "\t.double %.20e\n", (VALUE))
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-  fprintf (FILE, "\t.single %.12e\n", (VALUE))
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* This is how to output code to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tadd_nt r4,r4,$-4\n\tst_32 %s,r4,$0\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tld_32 %s,r4,$0\n\tadd_nt r4,r4,$4\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.long L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.
-   (SPUR does not use such vectors,
-   but we must define this macro anyway.)  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", (LOG))
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %u\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.
-
-   On SPUR, the CODE can be `r', meaning this is a register-only operand
-   and an immediate zero should be represented as `r0'.  */
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else if (GET_CODE (X) == CONST_DOUBLE)				\
-    abort ();								\
-  else if ((CODE) == 'r' && (X) == const0_rtx)				\
-    fprintf (FILE, "r0");						\
-  else { putc ('$', FILE); output_addr_const (FILE, X); }}
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx base, index = 0;					\
-  int offset = 0;						\
-  register rtx addr = ADDR;					\
-  if (GET_CODE (addr) == REG)					\
-    {								\
-      fprintf (FILE, "%s,$0", reg_names[REGNO (addr)]);		\
-    }								\
-  else if (GET_CODE (addr) == PLUS)				\
-    {								\
-      if (GET_CODE (XEXP (addr, 0)) == CONST_INT)		\
-	offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
-      else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)		\
-	offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
-      else							\
-	base = XEXP (addr, 0), index = XEXP (addr, 1);		\
-      fprintf (FILE, "%s,", reg_names[REGNO (base)]);		\
-      if (index == 0)						\
-	fprintf (FILE, "$%d", offset);				\
-      else							\
-	fprintf (FILE, "%s,", reg_names[REGNO (index)]);	\
-    }								\
-  else								\
-    {								\
-      fprintf (FILE, "r24,$(");					\
-      output_addr_const (FILE, addr);				\
-      fprintf (FILE, "-0b)");					\
-    }								\
-}
diff --git a/gcc/config/spur/spur.md b/gcc/config/spur/spur.md
deleted file mode 100755
index 7ad4af5..0000000
--- a/gcc/config/spur/spur.md
+++ /dev/null
@@ -1,1092 +0,0 @@
-;;- Machine description for SPUR chip for GNU C compiler
-;;   Copyright (C) 1988 Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-;;- Operand classes for the register allocator:
-
-;; Compare instructions.
-;; This pattern is used for generating an "insn"
-;; which does just a compare and sets a (fictitious) condition code.
-
-;; The actual SPUR insns are compare-and-conditional-jump.
-;; The define_peephole's below recognize the combinations of
-;; compares and jumps, and output each pair as a single assembler insn.
-
-;; This controls RTL generation and register allocation.
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "register_operand" "rK")
-		 (match_operand:SI 1 "nonmemory_operand" "rK")))]
-  ""
-  "*
-{
-  cc_status.value1 = operands[0], cc_status.value2 = operands[1];
-  return \"\";
-}")
-
-;; We have to have this because cse can optimize the previous pattern
-;; into this one.
-
-(define_insn "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "register_operand" "r"))]
-  ""
-  "*
-{
-  cc_status.value1 = operands[0], cc_status.value2 = const0_rtx;
-  return \"\";
-}")
-
-
-;; These control RTL generation for conditional jump insns
-;; and match them for register allocation.
-
-(define_insn "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_compare (operands, \"eq\", \"eq\", \"ne\", \"ne\"); ")
-
-(define_insn "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_compare (operands, \"ne\", \"ne\", \"eq\", \"eq\"); ")
-
-(define_insn "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_compare (operands, \"gt\", \"lt\", \"le\", \"ge\"); ")
-
-(define_insn "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_compare (operands, \"ugt\", \"ult\", \"ule\", \"uge\"); ")
-
-(define_insn "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_compare (operands, \"lt\", \"gt\", \"ge\", \"le\"); ")
-
-(define_insn "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_compare (operands, \"ult\", \"ugt\", \"uge\", \"ule\"); ")
-
-(define_insn "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_compare (operands, \"ge\", \"le\", \"lt\", \"gt\"); ")
-
-(define_insn "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_compare (operands, \"uge\", \"ule\", \"ult\", \"ugt\"); ")
-
-(define_insn "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_compare (operands, \"le\", \"ge\", \"gt\", \"lt\"); ")
-
-(define_insn "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "* return output_compare (operands, \"ule\", \"uge\", \"ugt\", \"ult\"); ")
-
-;; These match inverted jump insns for register allocation.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_compare (operands, \"ne\", \"ne\", \"eq\", \"eq\"); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_compare (operands, \"eq\", \"eq\", \"ne\", \"ne\"); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_compare (operands, \"le\", \"ge\", \"gt\", \"lt\"); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_compare (operands, \"ule\", \"uge\", \"ugt\", \"ult\"); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_compare (operands, \"ge\", \"le\", \"lt\", \"gt\"); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_compare (operands, \"uge\", \"ule\", \"ult\", \"ugt\"); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_compare (operands, \"lt\", \"gt\", \"ge\", \"le\"); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_compare (operands, \"ult\", \"ugt\", \"uge\", \"ule\"); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_compare (operands, \"gt\", \"lt\", \"le\", \"ge\"); ")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "* return output_compare (operands, \"ugt\", \"ult\", \"ule\", \"uge\"); ")
-
-;; Move instructions
-
-(define_insn "movsi"
-  [(set (match_operand:SI 0 "general_operand" "=r,m")
-	(match_operand:SI 1 "general_operand" "rmi,rJ"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM)
-    return \"st_32 %r1,%0\";
-  if (GET_CODE (operands[1]) == MEM)
-    return \"ld_32 %0,%1\;nop\";
-  if (GET_CODE (operands[1]) == REG)
-    return \"add_nt %0,%1,$0\";
-  if (GET_CODE (operands[1]) == SYMBOL_REF && operands[1]->unchanging)
-    return \"add_nt %0,r24,$(%1-0b)\";
-  return \"add_nt %0,r0,%1\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "register_operand" "r"))))]
-  ""
-  "ld_32 %0,%1,%2\;nop")
-
-;; Generate insns for moving single bytes.
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-    operands[1] = copy_to_reg (operands[1]);
-
-  if (GET_CODE (operands[1]) == MEM)
-    {
-      rtx tem = gen_reg_rtx (SImode);
-      rtx addr = force_reg (SImode, XEXP (operands[1], 0));
-      rtx subreg;
-
-      emit_move_insn (tem, gen_rtx (MEM, SImode, addr));
-      if (GET_CODE (operands[0]) == SUBREG)
-	subreg = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[0]),
-			  SUBREG_WORD (operands[0]));
-      else
-	subreg = gen_rtx (SUBREG, SImode, operands[0], 0);
-
-      emit_insn (gen_rtx (SET, VOIDmode, subreg,
-			  gen_rtx (ZERO_EXTRACT, SImode, tem,
-				   GEN_INT (8),
-				   addr)));
-    }
-  else if (GET_CODE (operands[0]) == MEM)
-    {
-      rtx tem = gen_reg_rtx (SImode);
-      rtx addr = force_reg (SImode, XEXP (operands[0], 0));
-      rtx subreg;
-
-      emit_move_insn (tem, gen_rtx (MEM, SImode, addr));
-      if (! CONSTANT_ADDRESS_P (operands[1]))
-	{
-	  if (GET_CODE (operands[1]) == SUBREG)
-	    subreg = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[1]),
-			      SUBREG_WORD (operands[1]));
-	  else
-	    subreg = gen_rtx (SUBREG, SImode, operands[1], 0);
-	}
-
-      emit_insn (gen_rtx (SET, VOIDmode,
-			  gen_rtx (ZERO_EXTRACT, SImode, tem,
-				   GEN_INT (8),
-				   addr),
-			  subreg));
-      emit_move_insn (gen_rtx (MEM, SImode, addr), tem);
-    }
-  else
-    {
-      emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
-    }
-  DONE;
-}")
-
-;; Recognize insns generated for moving single bytes.
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=r,m")
-	(match_operand:QI 1 "general_operand" "rmi,r"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM)
-    return \"st_32 %1,%0\";
-  if (GET_CODE (operands[1]) == MEM)
-    return \"ld_32 %0,%1\;nop\";
-  if (GET_CODE (operands[1]) == REG)
-    return \"add_nt %0,%1,$0\";
-  return \"add_nt %0,r0,%1\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (const_int 8)
-			 (match_operand:SI 2 "nonmemory_operand" "rI")))]
-  ""
-  "extract %0,%1,%2")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-			 (const_int 8)
-			 (match_operand:SI 1 "nonmemory_operand" "rI"))
-	(match_operand:SI 2 "nonmemory_operand" "ri"))]
-  ""
-  "wr_insert %1\;insert %0,%0,%2")
-
-;; Constant propagation can optimize the previous pattern into this pattern.
-;[Not any more.  It could when the position-operand contains a MULT.]
-
-;(define_insn ""
-;  [(set (zero_extract:QI (match_operand:SI 0 "register_operand" "+r")
-;			 (const_int 8)
-;			 (match_operand:SI 1 "immediate_operand" "I"))
-;	(match_operand:QI 2 "register_operand" "r"))]
-;  "GET_CODE (operands[1]) == CONST_INT
-;   && INTVAL (operands[1]) % 8 == 0
-;   && (unsigned) INTVAL (operands[1]) < 32"
-;  "*
-;{
-;  operands[1] = GEN_INT (INTVAL (operands[1]) / 8);
-;  return \"wr_insert 0,0,%1\;insert %0,%0,%2\";
-;}")
-
-;; The three define_expand patterns on this page
-;; serve as subroutines of "movhi".
-
-;; Generate code to fetch an aligned halfword from memory.
-;; Operand 0 is the destination register (HImode).
-;; Operand 1 is the memory address (SImode).
-;; Operand 2 is a temporary (SImode).
-;; Operand 3 is a temporary (SImode).
-;; Operand 4 is a temporary (QImode).
-
-;; Operand 5 is an internal temporary (HImode).
-
-(define_expand "loadhi"
-  [(set (match_operand:SI 2 "register_operand" "")
-	(mem:SI (match_operand:SI 1 "register_operand" "")))
-   ;; Extract the low byte.
-   (set (subreg:SI (match_dup 5) 0)
-	(zero_extract:SI (match_dup 2) (const_int 8) (match_dup 1)))
-   ;; Form address of high byte.
-   (set (match_operand:SI 3 "register_operand" "")
-	(plus:SI (match_dup 1) (const_int 1)))
-   ;; Extract the high byte.
-   (set (subreg:SI (match_operand:QI 4 "register_operand" "") 0)
-	(zero_extract:SI (match_dup 2) (const_int 8) (match_dup 3)))
-   ;; Put the high byte in with the low one.
-   (set (zero_extract:SI (match_dup 5) (const_int 8) (const_int 1))
-	(subreg:SI (match_dup 4) 0))
-   (set (match_operand:HI 0 "register_operand" "") (match_dup 5))]
-  ""
-  "operands[5] = gen_reg_rtx (HImode);")
-
-;; Generate code to store an aligned halfword into memory.
-;; Operand 0 is the destination address (SImode).
-;; Operand 1 is the source register (HImode, not constant).
-;; Operand 2 is a temporary (SImode).
-;; Operand 3 is a temporary (SImode).
-;; Operand 4 is a temporary (QImode).
-
-;; Operand 5 is an internal variable made from operand 1.
-
-(define_expand "storehi"
-  [(set (match_operand:SI 2 "register_operand" "")
-	(mem:SI (match_operand:SI 0 "register_operand" "")))
-   ;; Insert the low byte.
-   (set (zero_extract:SI (match_dup 2) (const_int 8) (match_dup 0))
-	(match_dup 5))
-   ;; Form address of high byte.
-   (set (match_operand:SI 3 "register_operand" "")
-	(plus:SI (match_dup 0) (const_int 1)))
-   ;; Extract the high byte from the source.
-   (set (subreg:SI (match_operand:QI 4 "register_operand" "") 0)
-	(zero_extract:SI (match_operand:HI 1 "register_operand" "")
-			 (const_int 8) (const_int 1)))
-   ;; Store high byte into the memory word
-   (set (zero_extract:SI (match_dup 2) (const_int 8) (match_dup 3))
-	(subreg:SI (match_dup 4) 0))
-   ;; Put memory word back into memory.
-   (set (mem:SI (match_dup 0))
-	(match_dup 2))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == SUBREG)
-    operands[5] = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[1]),
-			   SUBREG_WORD (operands[1]));
-  else
-    operands[5] = gen_rtx (SUBREG, SImode, operands[1], 0);
-}")
-
-;; Like storehi but operands[1] is a CONST_INT.
-
-(define_expand "storeinthi"
-  [(set (match_operand:SI 2 "register_operand" "")
-	(mem:SI (match_operand:SI 0 "register_operand" "")))
-   ;; Insert the low byte.
-   (set (zero_extract:SI (match_dup 2) (const_int 8) (match_dup 0))
-	(match_dup 5))
-   ;; Form address of high byte.
-   (set (match_operand:SI 3 "register_operand" "")
-	(plus:SI (match_dup 0) (const_int 1)))
-   ;; Store high byte into the memory word
-   (set (zero_extract:SI (match_dup 2) (const_int 8) (match_dup 3))
-	(match_dup 6))
-   ;; Put memory word back into memory.
-   (set (mem:SI (match_dup 0))
-	(match_dup 2))]
-  ""
-  " operands[5] = GEN_INT (INTVAL (operands[1]) & 255);
-    operands[6] = GEN_INT ((INTVAL (operands[1]) >> 8) & 255);
-")
-
-;; Main entry for generating insns to move halfwords.
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-    operands[1] = copy_to_reg (operands[1]);
-  
-  if (GET_CODE (operands[1]) == MEM)
-    {
-      rtx insn =
-	emit_insn (gen_loadhi (operands[0],
-			       force_reg (SImode, XEXP (operands[1], 0)),
-			       gen_reg_rtx (SImode), gen_reg_rtx (SImode),
-			       gen_reg_rtx (QImode)));
-      /* Tell cse what value the loadhi produces, so it detect duplicates.  */
-      REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, operands[1],
-					     REG_NOTES (insn));
-    }
-  else if (GET_CODE (operands[0]) == MEM)
-    {
-      if (GET_CODE (operands[1]) == CONST_INT)
-	emit_insn (gen_storeinthi (force_reg (SImode, XEXP (operands[0], 0)),
-			           operands[1],
-				   gen_reg_rtx (SImode), gen_reg_rtx (SImode),
-				   gen_reg_rtx (QImode)));
-      else
-	{
-	  if (CONSTANT_P (operands[1]))
-            operands[1] = force_reg (HImode, operands[1]);
-	  emit_insn (gen_storehi (force_reg (SImode, XEXP (operands[0], 0)),
-				  operands[1],
-				  gen_reg_rtx (SImode), gen_reg_rtx (SImode),
-				  gen_reg_rtx (QImode)));
-	}
-    }
-  else
-    emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
-  DONE;
-}")
-
-;; Recognize insns generated for moving halfwords.
-;; (Note that the extract and insert patterns for single-byte moves
-;;  are also involved in recognizing some of the insns used for this purpose.)
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=r,m")
-	(match_operand:HI 1 "general_operand" "rmi,r"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) == MEM)
-    return \"st_32 %1,%0\";
-  if (GET_CODE (operands[1]) == MEM)
-    return \"ld_32 %0,%1\;nop\";
-  if (GET_CODE (operands[1]) == REG)
-    return \"add_nt %0,%1,$0\";
-  return \"add_nt %0,r0,%1\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extract:SI (match_operand:HI 1 "register_operand" "r")
-			 (const_int 8)
-			 (match_operand:SI 2 "nonmemory_operand" "rI")))]
-  ""
-  "extract %0,%1,%2")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:HI 0 "register_operand" "+r")
-			 (const_int 8)
-			 (match_operand:SI 1 "nonmemory_operand" "rI"))
-	(match_operand:SI 2 "nonmemory_operand" "ri"))]
-  ""
-  "wr_insert %1\;insert %0,%0,%2")
-
-;; Constant propagation can optimize the previous pattern into this pattern.
-
-;(define_insn ""
-;  [(set (zero_extract:QI (match_operand:HI 0 "register_operand" "+r")
-;			 (const_int 8)
-;			 (match_operand:SI 1 "immediate_operand" "I"))
-;	(match_operand:QI 2 "register_operand" "r"))]
-;  "GET_CODE (operands[1]) == CONST_INT
-;   && INTVAL (operands[1]) % 8 == 0
-;   && (unsigned) INTVAL (operands[1]) < 32"
-;  "*
-;{
-;  operands[1] = GEN_INT (INTVAL (operands[1]) / 8);
-;  return \"wr_insert 0,0,%1\;insert %0,%0,%2\";
-;}")
-
-;; This pattern forces (set (reg:DF ...) (const_double ...))
-;; to be reloaded by putting the constant into memory.
-;; It must come before the more general movdf pattern.
-(define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=&r,f,&o")
-	(match_operand:DF 1 "" "mG,m,G"))]
-  "GET_CODE (operands[1]) == CONST_DOUBLE"
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    return output_fp_move_double (operands);
-  if (operands[1] == CONST0_RTX (DFmode) && GET_CODE (operands[0]) == REG)
-    {
-      operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-      return \"add_nt %0,r0,$0\;add_nt %1,r0,$0\";
-    }
-  if (operands[1] == CONST0_RTX (DFmode) && GET_CODE (operands[0]) == MEM)
-    {
-      operands[1] = adj_offsettable_operand (operands[0], 4);
-      return \"st_32 r0,%0\;st_32 r0,%1\";
-    }
-  return output_move_double (operands);
-}
-")
-  
-(define_insn "movdf"
-  [(set (match_operand:DF 0 "general_operand" "=r,&r,m,?f,?rm")
-	(match_operand:DF 1 "general_operand" "r,m,r,rfm,f"))]
-  ""
-  "*
-{
-  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
-    return output_fp_move_double (operands);
-  return output_move_double (operands);
-}
-")
-
-(define_insn "movdi"
-  [(set (match_operand:DI 0 "general_operand" "=r,&r,m,?f,?rm")
-	(match_operand:DI 1 "general_operand" "r,m,r,rfm,f"))]
-  ""
-  "*
-{
-  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
-    return output_fp_move_double (operands);
-  return output_move_double (operands);
-}
-")
-
-(define_insn "movsf"
-  [(set (match_operand:SF 0 "general_operand" "=rf,m")
-	(match_operand:SF 1 "general_operand" "rfm,rf"))]
-  ""
-  "*
-{
-  if (FP_REG_P (operands[0]))
-    {
-      if (FP_REG_P (operands[1]))
-	return \"fmov %0,%1\";
-      if (GET_CODE (operands[1]) == REG)
-	{
-	  rtx xoperands[2];
-	  int offset = - get_frame_size () - 8;
-	  xoperands[1] = operands[1];
-	  xoperands[0] = GEN_INT (offset);
-	  output_asm_insn (\"st_32 %1,r25,%0\", xoperands);
-	  xoperands[1] = operands[0];
-	  output_asm_insn (\"ld_sgl %1,r25,%0\;nop\", xoperands);
-	  return \"\";
-	}
-      return \"ld_sgl %0,%1\;nop\";
-    }
-  if (FP_REG_P (operands[1]))
-    {
-      if (GET_CODE (operands[0]) == REG)
-	{
-	  rtx xoperands[2];
-	  int offset = - get_frame_size () - 8;
-	  xoperands[0] = GEN_INT (offset);
-	  xoperands[1] = operands[1];
-	  output_asm_insn (\"st_sgl %1,r25,%0\", xoperands);
-	  xoperands[1] = operands[0];
-	  output_asm_insn (\"ld_32 %1,r25,%0\;nop\", xoperands);
-	  return \"\";
-	}
-      return \"st_sgl %1,%0\";
-    }
-  if (GET_CODE (operands[0]) == MEM)
-    return \"st_32 %r1,%0\";
-  if (GET_CODE (operands[1]) == MEM)
-    return \"ld_32 %0,%1\;nop\";
-  if (GET_CODE (operands[1]) == REG)
-    return \"add_nt %0,%1,$0\";
-  return \"add_nt %0,r0,%1\";
-}")
-
-;;- truncation instructions
-(define_insn "truncsiqi2"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(truncate:QI
-	 (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "add_nt %0,%1,$0")
-
-(define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "register_operand" "=r")
-	(truncate:QI
-	 (match_operand:HI 1 "register_operand" "r")))]
-  ""
-  "add_nt %0,%1,$0")
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(truncate:HI
-	 (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "add_nt %0,%1,$0")
-
-;;- zero extension instructions
-
-;; Note that the one starting from HImode comes before those for QImode
-;; so that a constant operand will match HImode, not QImode.
-(define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(and:SI (match_operand:HI 1 "register_operand" "") ;Changed to SI below
-		;; This constant is invalid, but reloading will handle it.
-		;; It's useless to generate here the insns to construct it
-		;; because constant propagation would simplify them anyway.
-		(match_dup 2)))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == SUBREG)
-    operands[1] = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[1]),
-			   SUBREG_WORD (operands[1]));
-  else
-    operands[1] = gen_rtx (SUBREG, SImode, operands[1], 0);
-
-  operands[2] = force_reg (SImode, GEN_INT (65535));
-}")
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(zero_extend:HI
-	 (match_operand:QI 1 "register_operand" "r")))]
-  ""
-  "extract %0,%1,$0")
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI
-	 (match_operand:QI 1 "register_operand" "r")))]
-  ""
-  "extract %0,%1,$0")
-
-;;- sign extension instructions
-;; Note that the one starting from HImode comes before those for QImode
-;; so that a constant operand will match HImode, not QImode.
-
-(define_expand "extendhisi2"
-  [(set (match_dup 2)
-	(and:SI (match_operand:HI 1 "register_operand" "") ;Changed to SI below
-		(match_dup 4)))
-   (set (match_dup 3) (plus:SI (match_dup 2) (match_dup 5)))
-   (set (match_operand:SI 0 "register_operand" "")
-	(xor:SI (match_dup 3) (match_dup 5)))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == SUBREG)
-    operands[1] = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[1]),
-			   SUBREG_WORD (operands[1]));
-  else
-    operands[1] = gen_rtx (SUBREG, SImode, operands[1], 0);
-
-  operands[2] = gen_reg_rtx (SImode);
-  operands[3] = gen_reg_rtx (SImode);
-  operands[4] = force_reg (SImode, GEN_INT (65535));
-  operands[5] = force_reg (SImode, GEN_INT (-32768));
-}")
-
-(define_expand "extendqihi2"
-  [(set (match_dup 2)
-	(and:HI (match_operand:QI 1 "register_operand" "") ;Changed to SI below
-		(const_int 255)))
-   (set (match_dup 3)
-	(plus:SI (match_dup 2) (const_int -128)))
-   (set (match_operand:HI 0 "register_operand" "")
-	(xor:SI (match_dup 3) (const_int -128)))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == SUBREG)
-    operands[1] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[1]),
-			   SUBREG_WORD (operands[1]));
-  else
-    operands[1] = gen_rtx (SUBREG, HImode, operands[1], 0);
-
-  operands[2] = gen_reg_rtx (HImode);
-  operands[3] = gen_reg_rtx (HImode);
-}")
-
-(define_expand "extendqisi2"
-  [(set (match_dup 2)
-	(and:SI (match_operand:QI 1 "register_operand" "") ;Changed to SI below
-		(const_int 255)))
-   (set (match_dup 3) (plus:SI (match_dup 2) (const_int -128)))
-   (set (match_operand:SI 0 "register_operand" "")
-	(xor:SI (match_dup 3) (const_int -128)))]
-  ""
-  "
-{
-  if (GET_CODE (operands[1]) == SUBREG)
-    operands[1] = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[1]),
-			   SUBREG_WORD (operands[1]));
-  else
-    operands[1] = gen_rtx (SUBREG, SImode, operands[1], 0);
-
-  operands[2] = gen_reg_rtx (SImode);
-  operands[3] = gen_reg_rtx (SImode);
-}")
-
-;;- arithmetic instructions
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_operand:SI 1 "nonmemory_operand" "%r")
-		 (match_operand:SI 2 "nonmemory_operand" "rI")))]
-  ""
-  "add %0,%1,%2")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_operand:SI 1 "nonmemory_operand" "%r")
-		 (match_operand:SI 2 "big_immediate_operand" "g")))]
-  "GET_CODE (operands[2]) == CONST_INT 
-   && (unsigned) (INTVAL (operands[2]) + 0x8000000) < 0x10000000"
-  "*
-{
-  return 
-    output_add_large_offset (operands[0], operands[1], INTVAL (operands[2]));
-}")
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "r")
-		  (match_operand:SI 2 "nonmemory_operand" "rI")))]
-  ""
-  "sub %0,%1,%2")
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (match_operand:SI 1 "nonmemory_operand" "%r")
-		(match_operand:SI 2 "nonmemory_operand" "rI")))]
-  ""
-  "and %0,%1,%2")
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (match_operand:SI 1 "nonmemory_operand" "%r")
-		(match_operand:SI 2 "nonmemory_operand" "rI")))]
-  ""
-  "or %0,%1,%2")
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(xor:SI (match_operand:SI 1 "nonmemory_operand" "%r")
-		(match_operand:SI 2 "nonmemory_operand" "rI")))]
-  ""
-  "xor %0,%1,%2")
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "nonmemory_operand" "rI")))]
-  ""
-  "sub %0,r0,%1")
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "xor %0,%1,$-1")
-
-;; Floating point arithmetic instructions.
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(plus:DF (match_operand:DF 1 "register_operand" "f")
-		 (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fadd %0,%1,%2")
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(plus:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fadd %0,%1,%2")
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 1 "register_operand" "f")
-		  (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fsub %0,%1,%2")
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (match_operand:SF 1 "register_operand" "f")
-		  (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fsub %0,%1,%2")
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mult:DF (match_operand:DF 1 "register_operand" "f")
-		 (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fmul %0,%1,%2")
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(mult:SF (match_operand:SF 1 "register_operand" "f")
-		 (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fmul %0,%1,%2")
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(div:DF (match_operand:DF 1 "register_operand" "f")
-		(match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fdiv %0,%1,%2")
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(div:SF (match_operand:SF 1 "register_operand" "f")
-		(match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_FPU"
-  "fdiv %0,%1,%2")
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(neg:DF (match_operand:DF 1 "nonmemory_operand" "f")))]
-  "TARGET_FPU"
-  "fneg %0,%1")
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(neg:SF (match_operand:SF 1 "nonmemory_operand" "f")))]
-  "TARGET_FPU"
-  "fneg %0,%1")
-
-(define_insn "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(abs:DF (match_operand:DF 1 "nonmemory_operand" "f")))]
-  "TARGET_FPU"
-  "fabs %0,%1")
-
-(define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(abs:SF (match_operand:SF 1 "nonmemory_operand" "f")))]
-  "TARGET_FPU"
-  "fabs %0,%1")
-
-;; Shift instructions
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "register_operand" "r")
-		   (match_operand:SI 2 "immediate_operand" "I")))]
-  "GET_CODE (operands[2]) == CONST_INT"
-  "*
-{
-  unsigned int amount = INTVAL (operands[2]);
-
-  switch (amount)
-    {
-    case 0:
-      return \"add_nt %0,%1,$0\";
-    case 1:
-      return \"sll %0,%1,$1\";
-    case 2:
-      return \"sll %0,%1,$2\";
-    default:
-      output_asm_insn (\"sll %0,%1,$3\", operands);
-
-      for (amount -= 3; amount >= 3; amount -= 3)
-	output_asm_insn (\"sll %0,%0,$3\", operands);
-
-      if (amount > 0)
-	output_asm_insn (amount == 1 ? \"sll %0,%0,$1\" : \"sll %0,%0,$2\",
-			 operands);
-      return \"\";
-    }
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
-	             (match_operand:SI 2 "immediate_operand" "I")))]
-  "GET_CODE (operands[2]) == CONST_INT"
-  "*
-{
-  unsigned int amount = INTVAL (operands[2]);
-
-  if (amount == 0) 
-    return \"add_nt %0,%1,$0\";
-  else
-    output_asm_insn (\"sra %0,%1,$1\", operands);
-  
-  for (amount -= 1; amount > 0; amount -= 1)
-    output_asm_insn (\"sra %0,%0,$1\", operands);
-
-  return \"\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
-	             (match_operand:SI 2 "immediate_operand" "I")))]
-  "GET_CODE (operands[2]) == CONST_INT"
-  "*
-{
-  unsigned int amount = INTVAL (operands[2]);
-
-  if (amount == 0) 
-    return \"add_nt %0,%1,$0\";
-  else
-    output_asm_insn (\"srl %0,%1,$1\", operands);
-  
-  for (amount -= 1; amount > 0; amount -= 1)
-    output_asm_insn (\"srl %0,%0,$1\", operands);
-
-  return \"\";
-}")
-
-(define_expand "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashift:SI (match_operand:SI 1 "register_operand" "")
-		   (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT
-      || (! TARGET_EXPAND_SHIFTS && (unsigned) INTVAL (operands[2]) > 3))
-    FAIL;
-}")
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT
-      || (! TARGET_EXPAND_SHIFTS && (unsigned) INTVAL (operands[2]) > 1))
-    FAIL;
-}")
-
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
-		     (match_operand:SI 2 "nonmemory_operand" "")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT
-      || (! TARGET_EXPAND_SHIFTS && (unsigned) INTVAL (operands[2]) > 1))
-    FAIL;
-}")
-
-;; Unconditional and other jump instructions
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "jump %l0\;nop")
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jump_reg r0,%0\;nop")
-
-;;- jump to subroutine
-(define_insn "call"
-  [(call (match_operand:SI 0 "memory_operand" "m")
-	 (match_operand:SI 1 "general_operand" "g"))]
-  ;;- Don't use operand 1 for most machines.
-  ""
-  "add_nt r2,%0\;call .+8\;jump_reg r0,r2\;nop")
-
-(define_insn "call_value"
-  [(set (match_operand 0 "" "=g")
-	(call (match_operand:SI 1 "memory_operand" "m")
-	      (match_operand:SI 2 "general_operand" "g")))]
-  ;;- Don't use operand 1 for most machines.
-  ""
-  "add_nt r2,%1\;call .+8\;jump_reg r0,r2\;nop")
-
-;; A memory ref with constant address is not normally valid.
-;; But it is valid in a call insns.  This pattern allows the
-;; loading of the address to combine with the call.
-(define_insn ""
-  [(call (mem:SI (match_operand:SI 0 "" "i"))
-	 (match_operand:SI 1 "general_operand" "g"))]
-  ;;- Don't use operand 1 for most machines.
-  "GET_CODE (operands[0]) == SYMBOL_REF"
-  "call %0\;nop")
-
-(define_insn ""
-  [(set (match_operand 0 "" "=g")
-	(call (mem:SI (match_operand:SI 1 "" "i"))
-	      (match_operand:SI 2 "general_operand" "g")))]
-  ;;- Don't use operand 1 for most machines.
-  "GET_CODE (operands[1]) == SYMBOL_REF"
-  "call %1\;nop")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
diff --git a/gcc/config/spur/xm-spur.h b/gcc/config/spur/xm-spur.h
deleted file mode 100755
index 1d30053..0000000
--- a/gcc/config/spur/xm-spur.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Configuration for GNU C-compiler for Berkeley SPUR processor.
-   Copyright (C) 1988, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
diff --git a/gcc/config/svr3.h b/gcc/config/svr3.h
deleted file mode 100755
index 3475561..0000000
--- a/gcc/config/svr3.h
+++ /dev/null
@@ -1,375 +0,0 @@
-/* Operating system specific defines to be used when targeting GCC for
-   generic System V Release 3 system.
-   Copyright (C) 1991, 1996 Free Software Foundation, Inc.
-   Contributed by Ron Guilmette (rfg@monkeys.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.
-
-   To use this file, make up a file with a name like:
-
-	?????svr3.h
-
-   where ????? is replaced by the name of the basic hardware that you
-   are targeting for.  Then, in the file ?????svr3.h, put something
-   like:
-
-	#include "?????.h"
-	#include "svr3.h"
-
-   followed by any really system-specific defines (or overrides of
-   defines) which you find that you need.  For example, CPP_PREDEFINES
-   is defined here with only the defined -Dunix and -DSVR3.  You should
-   probably override that in your target-specific ?????svr3.h file
-   with a set of defines that includes these, but also contains an
-   appropriate define for the type of hardware that you are targeting.
-*/
-
-/* Define a symbol indicating that we are using svr3.h.  */
-#define USING_SVR3_H
-
-/* Define a symbol so that libgcc* can know what sort of operating
-   environment and assembler syntax we are targeting for.  */
-#define SVR3_target
-
-/* Cpp, assembler, linker, library, and startfile spec's.  */
-
-/* You should redefine CPP_PREDEFINES in any file which includes this one.
-   The definition should be appropriate for the type of target system
-   involved, and it should include any -A (assertion) options which are
-   appropriate for the given target system.  */
-
-#undef CPP_PREDEFINES
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)					\
-  do { output_file_directive ((FILE), main_input_filename);	\
-       if (optimize) ASM_FILE_START_1 (FILE);			\
-     } while (0)
-
-/* By default, do nothing: a few machines support .optim, but not most.  */
-#undef ASM_FILE_START_1
-#define ASM_FILE_START_1(FILE)
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-/* We don't use ROUNDED because the standard compiler doesn't,
-   and the linker gives error messages if a common symbol
-   has more than one length value.  */
-
-#undef ASM_OUTPUT_COMMON
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (SIZE)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-/* Note that using bss_section here caused errors
-   in building shared libraries on system V.3.  */
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
-  do {							\
-    int align = exact_log2 (ROUNDED);			\
-    if (align > 2) align = 2;				\
-    data_section ();					\
-    ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align);	\
-    ASM_OUTPUT_LABEL ((FILE), (NAME));			\
-    fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED));	\
-  } while (0)
-
-#if 0 /* For now, let's leave these machine-specific.  */
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-
-#define STARTFILE_SPEC  \
-  "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
-
-#ifdef CROSS_COMPILE
-#define LIB_SPEC "-lc crtn.o%s"
-#else
-#define LIB_SPEC "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} -lc crtn.o%s"
-#endif
-
-/* Special flags for the linker.  I don't know what they do.  */
-
-#define LINK_SPEC "%{T*} %{z:-lm}"
-#endif
-
-/* Allow #sccs in preprocessor.  */
-
-#define SCCS_DIRECTIVE
-
-/* Output #ident as a .ident.  */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-
-/* Use periods rather than dollar signs in special g++ assembler names.  */
-
-#define NO_DOLLAR_IN_LABEL
-
-/* Implicit library calls should use memcpy, not bcopy, etc.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* System V Release 3 uses COFF debugging info.  */
-
-#define SDB_DEBUGGING_INFO
-
-/* We don't want to output DBX debugging information.  */
-
-#undef DBX_DEBUGGING_INFO
-
-/* Define the actual types of some ANSI-mandated types.  These
-   definitions should work for most SVR3 systems.  */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-/* Assembler pseudos to introduce constants of various size.  These
-   definitions should work for most svr3 systems.  */
-
-#undef ASM_BYTE_OP
-#define ASM_BYTE_OP "\t.byte"
-
-/* The prefix to add to user-visible assembler symbols.
-
-   For System V Release 3 the convention is to prepend a leading
-   underscore onto user-level symbol names.  */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-
-   For most svr3 systems, the convention is that any symbol which begins
-   with a period is not put into the linker symbol table by the assembler.  */
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.
-
-   For most svr3 systems, the convention is that any symbol which begins
-   with a period is not put into the linker symbol table by the assembler.  */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
-
-/* We want local labels to start with period if made with asm_fprintf.  */
-#undef LOCAL_LABEL_PREFIX
-#define LOCAL_LABEL_PREFIX "."
-
-/* Support const sections and the ctors and dtors sections for g++.
-   Note that there appears to be two different ways to support const
-   sections at the moment.  You can either #define the symbol
-   READONLY_DATA_SECTION (giving it some code which switches to the
-   readonly data section) or else you can #define the symbols
-   EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
-   SELECT_RTX_SECTION.  We do both here just to be on the safe side.
-   However, use of the const section is turned off by default
-   unless the specific tm.h file turns it on by defining
-   USE_CONST_SECTION as 1.  */
-
-/* Define a few machine-specific details of the implementation of
-   constructors.
-
-   The __CTORS_LIST__ goes in the .init section.  Define CTOR_LIST_BEGIN
-   and CTOR_LIST_END to contribute to the .init section an instruction to
-   push a word containing 0 (or some equivalent of that).
-
-   Define ASM_OUTPUT_CONSTRUCTOR to push the address of the constructor.  */
-
-#define USE_CONST_SECTION	0
-
-#define INIT_SECTION_ASM_OP     ".section\t.init"
-#define FINI_SECTION_ASM_OP     ".section .fini,\"x\""
-#define CONST_SECTION_ASM_OP	".section\t.rodata, \"x\""
-#define CTORS_SECTION_ASM_OP	INIT_SECTION_ASM_OP
-#define DTORS_SECTION_ASM_OP    FINI_SECTION_ASM_OP
-
-/* CTOR_LIST_BEGIN and CTOR_LIST_END are machine-dependent
-   because they push on the stack.  */
-
-#ifndef STACK_GROWS_DOWNWARD
-
-/* Constructor list on stack is in reverse order.  Go to the end of the
-   list and go backwards to call constructors in the right order.  */
-#define DO_GLOBAL_CTORS_BODY					\
-do {								\
-  func_ptr *p, *beg = alloca (0);				\
-  for (p = beg; *p; p++)					\
-    ;								\
-  while (p != beg)						\
-    (*--p) ();							\
-} while (0)
-
-#else
-
-/* Constructor list on stack is in correct order.  Just call them.  */
-#define DO_GLOBAL_CTORS_BODY					\
-do {								\
-  func_ptr *p, *beg = alloca (0);				\
-  for (p = beg; *p; )						\
-    (*p++) ();							\
-} while (0)
-
-#endif /* STACK_GROWS_DOWNWARD */
-
-/* Add extra sections .rodata, .init and .fini.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_init, in_fini
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS					\
-  CONST_SECTION_FUNCTION					\
-  INIT_SECTION_FUNCTION						\
-  FINI_SECTION_FUNCTION
-
-#define INIT_SECTION_FUNCTION					\
-void								\
-init_section ()							\
-{								\
-  if (in_section != in_init)					\
-    {								\
-      fprintf (asm_out_file, "\t%s\n", INIT_SECTION_ASM_OP);	\
-      in_section = in_init;					\
-    }								\
-}
-
-#define FINI_SECTION_FUNCTION					\
-void								\
-fini_section ()							\
-{								\
-  if (in_section != in_fini)					\
-    {								\
-      fprintf (asm_out_file, "\t%s\n", FINI_SECTION_ASM_OP);	\
-      in_section = in_fini;					\
-    }								\
-}
-
-#define READONLY_DATA_SECTION() const_section ()
-
-#define CONST_SECTION_FUNCTION						\
-void									\
-const_section ()							\
-{									\
-  extern void text_section();						\
-  if (!USE_CONST_SECTION)						\
-    text_section();							\
-  else if (in_section != in_const)					\
-    {									\
-      fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP);		\
-      in_section = in_const;						\
-    }									\
-}
-
-/* The ctors and dtors sections are not normally put into use 
-   by EXTRA_SECTIONS and EXTRA_SECTION_FUNCTIONS as defined in svr3.h,
-   but it can't hurt to define these macros for whatever systems use them.  */
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-/* This is machine-dependent
-   because it needs to push something on the stack.  */
-#undef ASM_OUTPUT_CONSTRUCTOR
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    fini_section ();                   				\
-    fprintf (FILE, "%s\t ", ASM_LONG);					\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement or statements to switch to the appropriate
-   section for output of DECL.  DECL is either a `VAR_DECL' node
-   or a constant of some sort.  RELOC indicates whether forming
-   the initial value of DECL requires link-time relocations.  */
-
-#define SELECT_SECTION(DECL,RELOC)					\
-{									\
-  if (TREE_CODE (DECL) == STRING_CST)					\
-    {									\
-      if (! flag_writable_strings)					\
-	const_section ();						\
-      else								\
-	data_section ();						\
-    }									\
-  else if (TREE_CODE (DECL) == VAR_DECL)				\
-    {									\
-      if ((0 && RELOC)	/* should be (flag_pic && RELOC) */		\
-	  || !TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)		\
-	  || !DECL_INITIAL (DECL)					\
-	  || (DECL_INITIAL (DECL) != error_mark_node			\
-	      && !TREE_CONSTANT (DECL_INITIAL (DECL))))			\
-	data_section ();						\
-      else								\
-	const_section ();						\
-    }									\
-  else									\
-    const_section ();							\
-}
-
-/* A C statement or statements to switch to the appropriate
-   section for output of RTX in mode MODE.  RTX is some kind
-   of constant in RTL.  The argument MODE is redundant except
-   in the case of a `const_int' rtx.  Currently, these always
-   go into the const section.  */
-
-#define SELECT_RTX_SECTION(MODE,RTX) const_section()
diff --git a/gcc/config/svr4.h b/gcc/config/svr4.h
deleted file mode 100755
index 1211f68..0000000
--- a/gcc/config/svr4.h
+++ /dev/null
@@ -1,993 +0,0 @@
-/* Operating system specific defines to be used when targeting GCC for some
-   generic System V Release 4 system.
-   Copyright (C) 1991, 94-97, 1998 Free Software Foundation, Inc.
-   Contributed by Ron Guilmette (rfg@monkeys.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.
-
-   To use this file, make up a file with a name like:
-
-	?????svr4.h
-
-   where ????? is replaced by the name of the basic hardware that you
-   are targeting for.  Then, in the file ?????svr4.h, put something
-   like:
-
-	#include "?????.h"
-	#include "svr4.h"
-
-   followed by any really system-specific defines (or overrides of
-   defines) which you find that you need.  For example, CPP_PREDEFINES
-   is defined here with only the defined -Dunix and -DSVR4.  You should
-   probably override that in your target-specific ?????svr4.h file
-   with a set of defines that includes these, but also contains an
-   appropriate define for the type of hardware that you are targeting.
-*/
-
-/* Define a symbol indicating that we are using svr4.h.  */
-#define USING_SVR4_H
-
-/* For the sake of libgcc2.c, indicate target supports atexit.  */
-#define HAVE_ATEXIT
-
-/* Cpp, assembler, linker, library, and startfile spec's.  */
-
-/* This defines which switch letters take arguments.  On svr4, most of
-   the normal cases (defined in gcc.c) apply, and we also have -h* and
-   -z* options (for the linker).  Note however that there is no such
-   thing as a -T option for svr4.  */
-
-#define SWITCH_TAKES_ARG(CHAR) \
-  (DEFAULT_SWITCH_TAKES_ARG (CHAR) \
-   || (CHAR) == 'h' \
-   || (CHAR) == 'x' \
-   || (CHAR) == 'z')
-
-/* This defines which multi-letter switches take arguments.  On svr4,
-   there are no such switches except those implemented by GCC itself.  */
-
-#define WORD_SWITCH_TAKES_ARG(STR)			\
- (DEFAULT_WORD_SWITCH_TAKES_ARG (STR)			\
-  && strcmp (STR, "Tdata") && strcmp (STR, "Ttext")	\
-  && strcmp (STR, "Tbss"))
-
-/* You should redefine CPP_PREDEFINES in any file which includes this one.
-   The definition should be appropriate for the type of target system
-   involved, and it should include any -A (assertion) options which are
-   appropriate for the given target system.  */
-#undef CPP_PREDEFINES
-
-/* Provide an ASM_SPEC appropriate for svr4.  Here we try to support as
-   many of the specialized svr4 assembler options as seems reasonable,
-   given that there are certain options which we can't (or shouldn't)
-   support directly due to the fact that they conflict with other options
-   for other svr4 tools (e.g. ld) or with other options for GCC itself.
-   For example, we don't support the -o (output file) or -R (remove
-   input file) options because GCC already handles these things.  We
-   also don't support the -m (run m4) option for the assembler because
-   that conflicts with the -m (produce load map) option of the svr4
-   linker.  We do however allow passing arbitrary options to the svr4
-   assembler via the -Wa, option.
-
-   Note that gcc doesn't allow a space to follow -Y in a -Ym,* or -Yd,*
-   option.
-*/
-
-#undef ASM_SPEC
-#define ASM_SPEC \
-  "%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*}"
-
-/* svr4 assemblers need the `-' (indicating input from stdin) to come after
-   the -o option (and its argument) for some reason.  If we try to put it
-   before the -o option, the assembler will try to read the file named as
-   the output file in the -o option as an input file (after it has already
-   written some stuff to it) and the binary stuff contained therein will
-   cause totally confuse the assembler, resulting in many spurious error
-   messages.  */
-
-#undef ASM_FINAL_SPEC
-#define ASM_FINAL_SPEC "%|"
-
-/* Under svr4, the normal location of the `ld' and `as' programs is the
-   /usr/ccs/bin directory.  */
-
-#ifndef CROSS_COMPILE
-#undef MD_EXEC_PREFIX
-#define MD_EXEC_PREFIX "/usr/ccs/bin/"
-#endif
-
-/* Under svr4, the normal location of the various *crt*.o files is the
-   /usr/ccs/lib directory.  */
-
-#ifndef CROSS_COMPILE
-#undef MD_STARTFILE_PREFIX
-#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
-#endif
-
-/* Provide a LIB_SPEC appropriate for svr4.  Here we tack on the default
-   standard C library (unless we are building a shared library).  */
-
-#undef	LIB_SPEC
-#define LIB_SPEC "%{!shared:%{!symbolic:-lc}}"
-
-/* Provide an ENDFILE_SPEC appropriate for svr4.  Here we tack on our own
-   magical crtend.o file (see crtstuff.c) which provides part of the
-   support for getting C++ file-scope static object constructed before
-   entering `main', followed by the normal svr3/svr4 "finalizer" file,
-   which is either `gcrtn.o' or `crtn.o'.  */
-
-#undef  ENDFILE_SPEC
-#define ENDFILE_SPEC "crtend.o%s %{pg:gcrtn.o%s}%{!pg:crtn.o%s}"
-
-/* Provide a LINK_SPEC appropriate for svr4.  Here we provide support
-   for the special GCC options -static, -shared, and -symbolic which
-   allow us to link things in one of these three modes by applying the
-   appropriate combinations of options at link-time.  We also provide
-   support here for as many of the other svr4 linker options as seems
-   reasonable, given that some of them conflict with options for other
-   svr4 tools (e.g. the assembler).  In particular, we do support the
-   -z*, -V, -b, -t, -Qy, -Qn, and -YP* options here, and the -e*,
-   -l*, -o*, -r, -s, -u*, and -L* options are directly supported
-   by gcc.c itself.  We don't directly support the -m (generate load
-   map) option because that conflicts with the -m (run m4) option of
-   the svr4 assembler.  We also don't directly support the svr4 linker's
-   -I* or -M* options because these conflict with existing GCC options.
-   We do however allow passing arbitrary options to the svr4 linker
-   via the -Wl, option.  We don't support the svr4 linker's -a option
-   at all because it is totally useless and because it conflicts with
-   GCC's own -a option.
-
-   Note that gcc doesn't allow a space to follow -Y in a -YP,* option.
-
-   When the -G link option is used (-shared and -symbolic) a final link is
-   not being done.  */
-
-#undef	LINK_SPEC
-#ifdef CROSS_COMPILE
-#define LINK_SPEC "%{h*} %{v:-V} \
-		   %{b} %{Wl,*:%*} \
-		   %{static:-dn -Bstatic} \
-		   %{shared:-G -dy -z text} \
-		   %{symbolic:-Bsymbolic -G -dy -z text} \
-		   %{G:-G} \
-		   %{YP,*} \
-		   %{Qy:} %{!Qn:-Qy}"
-#else
-#define LINK_SPEC "%{h*} %{v:-V} \
-		   %{b} %{Wl,*:%*} \
-		   %{static:-dn -Bstatic} \
-		   %{shared:-G -dy -z text} \
-		   %{symbolic:-Bsymbolic -G -dy -z text} \
-		   %{G:-G} \
-		   %{YP,*} \
-		   %{!YP,*:%{p:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
-		    %{!p:-Y P,/usr/ccs/lib:/usr/lib}} \
-		   %{Qy:} %{!Qn:-Qy}"
-#endif
-
-/* Gcc automatically adds in one of the files /usr/ccs/lib/values-Xc.o,
-   /usr/ccs/lib/values-Xa.o, or /usr/ccs/lib/values-Xt.o for each final
-   link step (depending upon the other gcc options selected, such as
-   -traditional and -ansi).  These files each contain one (initialized)
-   copy of a special variable called `_lib_version'.  Each one of these
-   files has `_lib_version' initialized to a different (enum) value.
-   The SVR4 library routines query the value of `_lib_version' at run
-   to decide how they should behave.  Specifically, they decide (based
-   upon the value of `_lib_version') if they will act in a strictly ANSI
-   conforming manner or not.
-*/
-
-#undef	STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared: \
-			 %{!symbolic: \
-			  %{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}\
-			%{pg:gcrti.o%s}%{!pg:crti.o%s} \
-			%{ansi:values-Xc.o%s} \
-			%{!ansi: \
-			 %{traditional:values-Xt.o%s} \
-			 %{!traditional:values-Xa.o%s}} \
- 			crtbegin.o%s"
-
-/* Attach a special .ident directive to the end of the file to identify
-   the version of GCC which compiled this code.  The format of the
-   .ident string is patterned after the ones produced by native svr4
-   C compilers.  */
-
-#define IDENT_ASM_OP ".ident"
-
-#define ASM_FILE_END(FILE)					\
-do {				 				\
-     fprintf ((FILE), "\t%s\t\"GCC: (GNU) %s\"\n",		\
-	      IDENT_ASM_OP, version_string);			\
-   } while (0)
-
-/* Allow #sccs in preprocessor.  */
-
-#define SCCS_DIRECTIVE
-
-/* Output #ident as a .ident.  */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
-  fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
-
-/* Use periods rather than dollar signs in special g++ assembler names.  */
-
-#define NO_DOLLAR_IN_LABEL
-
-/* Writing `int' for a bitfield forces int alignment for the structure.  */
-
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Implicit library calls should use memcpy, not bcopy, etc.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Handle #pragma weak and #pragma pack.  */
-
-#define HANDLE_SYSV_PRAGMA
-
-/* System V Release 4 uses DWARF debugging info.  */
-
-#define DWARF_DEBUGGING_INFO
-
-/* All ELF targets can support DWARF-2.  */
-
-#define DWARF2_DEBUGGING_INFO
-
-/* The numbers used to denote specific machine registers in the System V
-   Release 4 DWARF debugging information are quite likely to be totally
-   different from the numbers used in BSD stabs debugging information
-   for the same kind of target machine.  Thus, we undefine the macro
-   DBX_REGISTER_NUMBER here as an extra inducement to get people to
-   provide proper machine-specific definitions of DBX_REGISTER_NUMBER
-   (which is also used to provide DWARF registers numbers in dwarfout.c)
-   in their tm.h files which include this file.  */
-
-#undef DBX_REGISTER_NUMBER
-
-/* gas on SVR4 supports the use of .stabs.  Permit -gstabs to be used
-   in general, although it will only work when using gas.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* When generating stabs debugging, use N_BINCL entries.  */
-
-#define DBX_USE_BINCL
-
-/* Use DWARF debugging info by default.  */
-
-#ifndef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DWARF_DEBUG
-#endif
-
-/* Make LBRAC and RBRAC addresses relative to the start of the
-   function.  The native Solaris stabs debugging format works this
-   way, gdb expects it, and it reduces the number of relocation
-   entries.  */
-
-#define DBX_BLOCKS_FUNCTION_RELATIVE 1
-
-/* When using stabs, gcc2_compiled must be a stabs entry, not an
-   ordinary symbol, or gdb won't see it.  Furthermore, since gdb reads
-   the input piecemeal, starting with each N_SO, it's a lot easier if
-   the gcc2 flag symbol is *after* the N_SO rather than before it.  So
-   we emit an N_OPT stab there.  */
-
-#define ASM_IDENTIFY_GCC(FILE)						\
-do									\
-  {									\
-    if (write_symbols != DBX_DEBUG)					\
-      fputs ("gcc2_compiled.:\n", FILE);				\
-  }									\
-while (0)
-
-#define ASM_IDENTIFY_GCC_AFTER_SOURCE(FILE)				\
-do									\
-  {									\
-    if (write_symbols == DBX_DEBUG)					\
-      fputs ("\t.stabs\t\"gcc2_compiled.\", 0x3c, 0, 0, 0\n", FILE);	\
-  }									\
-while (0)
-
-/* Like block addresses, stabs line numbers are relative to the
-   current function.  */
-
-#define ASM_OUTPUT_SOURCE_LINE(file, line)				\
-do									\
-  {									\
-    static int sym_lineno = 1;						\
-    fprintf (file, ".stabn 68,0,%d,.LM%d-",				\
-	     line, sym_lineno);						\
-    assemble_name (file,						\
-		   XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));\
-    fprintf (file, "\n.LM%d:\n", sym_lineno);				\
-    sym_lineno += 1;							\
-  }									\
-while (0)
-
-/* In order for relative line numbers to work, we must output the
-   stabs entry for the function name first.  */
-
-#define DBX_FUNCTION_FIRST
-
-/* Generate a blank trailing N_SO to mark the end of the .o file, since
-   we can't depend upon the linker to mark .o file boundaries with
-   embedded stabs.  */
-
-#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME)			\
-do									\
-  {									\
-    text_section ();							\
-    fprintf (FILE,							\
-	   "\t.stabs \"\",%d,0,0,.Letext\n.Letext:\n", N_SO);		\
-  }									\
-while (0)
-
-/* Define the actual types of some ANSI-mandated types.  (These
-   definitions should work for most SVR4 systems).  */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "long int"
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
-
-/* This causes trouble, because it requires the host machine
-   to support ANSI C.  */
-/* #define MULTIBYTE_CHARS */
-
-#undef ASM_BYTE_OP
-#define ASM_BYTE_OP	".byte"
-
-#undef SET_ASM_OP
-#define SET_ASM_OP	".set"
-
-/* This is how to begin an assembly language file.  Most svr4 assemblers want
-   at least a .file directive to come first, and some want to see a .version
-   directive come right after that.  Here we just establish a default
-   which generates only the .file directive.  If you need a .version
-   directive for any specific target, you should override this definition
-   in the target-specific file which includes this one.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)                                    \
-  output_file_directive ((FILE), main_input_filename)
-
-/* This is how to allocate empty space in some section.  The .zero
-   pseudo-op is used for this on most svr4 assemblers.  */
-
-#define SKIP_ASM_OP	".zero"
-
-#undef ASM_OUTPUT_SKIP
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
-  fprintf (FILE, "\t%s\t%u\n", SKIP_ASM_OP, (SIZE))
-
-/* The prefix to add to user-visible assembler symbols.
-
-   For System V Release 4 the convention is *not* to prepend a leading
-   underscore onto user-level symbol names.  */
-
-#undef USER_LABEL_PREFIX
-#define USER_LABEL_PREFIX ""
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-
-   For most svr4 systems, the convention is that any symbol which begins
-   with a period is not put into the linker symbol table by the assembler.  */
-
-#undef ASM_OUTPUT_INTERNAL_LABEL
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM)			\
-do {									\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM);				\
-} while (0)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.
-
-   For most svr4 systems, the convention is that any symbol which begins
-   with a period is not put into the linker symbol table by the assembler.  */
-
-#undef ASM_GENERATE_INTERNAL_LABEL
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)			\
-do {									\
-  sprintf (LABEL, "*.%s%d", PREFIX, (unsigned) (NUM));			\
-} while (0)
-
-/* Output the label which precedes a jumptable.  Note that for all svr4
-   systems where we actually generate jumptables (which is to say every
-   svr4 target except i386, where we use casesi instead) we put the jump-
-   tables into the .rodata section and since other stuff could have been
-   put into the .rodata section prior to any given jumptable, we have to
-   make sure that the location counter for the .rodata section gets pro-
-   perly re-aligned prior to the actual beginning of the jump table.  */
-
-#define ALIGN_ASM_OP ".align"
-
-#ifndef ASM_OUTPUT_BEFORE_CASE_LABEL
-#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
-  ASM_OUTPUT_ALIGN ((FILE), 2);
-#endif
-
-#undef ASM_OUTPUT_CASE_LABEL
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,JUMPTABLE)		\
-  do {									\
-    ASM_OUTPUT_BEFORE_CASE_LABEL (FILE, PREFIX, NUM, JUMPTABLE)		\
-    ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM);			\
-  } while (0)
-
-/* The standard SVR4 assembler seems to require that certain builtin
-   library routines (e.g. .udiv) be explicitly declared as .globl
-   in each assembly file where they are referenced.  */
-
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN)				\
-  ASM_GLOBALIZE_LABEL (FILE, XSTR (FUN, 0))
-
-/* This says how to output assembler code to declare an
-   uninitialized external linkage data object.  Under SVR4,
-   the linker seems to want the alignment of data objects
-   to depend on their types.  We do exactly that here.  */
-
-#define COMMON_ASM_OP	".comm"
-
-#undef ASM_OUTPUT_ALIGNED_COMMON
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fprintf ((FILE), "\t%s\t", COMMON_ASM_OP);				\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
-} while (0)
-
-/* This says how to output assembler code to declare an
-   uninitialized internal linkage data object.  Under SVR4,
-   the linker seems to want the alignment of data objects
-   to depend on their types.  We do exactly that here.  */
-
-#define LOCAL_ASM_OP	".local"
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
-do {									\
-  fprintf ((FILE), "\t%s\t", LOCAL_ASM_OP);				\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), "\n");						\
-  ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);			\
-} while (0)
-
-/* Biggest alignment supported by the object file format of this
-   machine.  Use this macro to limit the alignment which can be
-   specified using the `__attribute__ ((aligned (N)))' construct.  If
-   not defined, the default value is `BIGGEST_ALIGNMENT'.  */
-
-#define MAX_OFILE_ALIGNMENT (32768*8)
-
-/* This is the pseudo-op used to generate a 32-bit word of data with a
-   specific value in some section.  This is the same for all known svr4
-   assemblers.  */
-
-#define INT_ASM_OP		".long"
-
-/* This is the pseudo-op used to generate a contiguous sequence of byte
-   values from a double-quoted string WITHOUT HAVING A TERMINATING NUL
-   AUTOMATICALLY APPENDED.  This is the same for most svr4 assemblers.  */
-
-#undef ASCII_DATA_ASM_OP
-#define ASCII_DATA_ASM_OP	".ascii"
-
-/* Support const sections and the ctors and dtors sections for g++.
-   Note that there appears to be two different ways to support const
-   sections at the moment.  You can either #define the symbol
-   READONLY_DATA_SECTION (giving it some code which switches to the
-   readonly data section) or else you can #define the symbols
-   EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and
-   SELECT_RTX_SECTION.  We do both here just to be on the safe side.  */
-
-#define USE_CONST_SECTION	1
-
-#define CONST_SECTION_ASM_OP	".section\t.rodata"
-
-/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
-
-   Note that we want to give these sections the SHF_WRITE attribute
-   because these sections will actually contain data (i.e. tables of
-   addresses of functions in the current root executable or shared library
-   file) and, in the case of a shared library, the relocatable addresses
-   will have to be properly resolved/relocated (and then written into) by
-   the dynamic linker when it actually attaches the given shared library
-   to the executing process.  (Note that on SVR4, you may wish to use the
-   `-z text' option to the ELF linker, when building a shared library, as
-   an additional check that you are doing everything right.  But if you do
-   use the `-z text' option when building a shared library, you will get
-   errors unless the .ctors and .dtors sections are marked as writable
-   via the SHF_WRITE attribute.)  */
-
-#define CTORS_SECTION_ASM_OP	".section\t.ctors,\"aw\""
-#define DTORS_SECTION_ASM_OP	".section\t.dtors,\"aw\""
-
-/* On svr4, we *do* have support for the .init and .fini sections, and we
-   can put stuff in there to be executed before and after `main'.  We let
-   crtstuff.c and other files know this by defining the following symbols.
-   The definitions say how to change sections to the .init and .fini
-   sections.  This is the same for all known svr4 assemblers.  */
-
-#define INIT_SECTION_ASM_OP	".section\t.init"
-#define FINI_SECTION_ASM_OP	".section\t.fini"
-
-/* A default list of other sections which we might be "in" at any given
-   time.  For targets that use additional sections (e.g. .tdesc) you
-   should override this definition in the target-specific file which
-   includes this file.  */
-
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_ctors, in_dtors
-
-/* A default list of extra section function definitions.  For targets
-   that use additional sections (e.g. .tdesc) you should override this
-   definition in the target-specific file which includes this file.  */
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS						\
-  CONST_SECTION_FUNCTION						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION
-
-#define READONLY_DATA_SECTION() const_section ()
-
-extern void text_section ();
-
-#define CONST_SECTION_FUNCTION						\
-void									\
-const_section ()							\
-{									\
-  if (!USE_CONST_SECTION)						\
-    text_section();							\
-  else if (in_section != in_const)					\
-    {									\
-      fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP);		\
-      in_section = in_const;						\
-    }									\
-}
-
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
-{									\
-  if (in_section != in_ctors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-/* Switch into a generic section.
- 
-   We make the section read-only and executable for a function decl,
-   read-only for a const data decl, and writable for a non-const data decl.
- 
-   If the section has already been defined, we must not
-   emit the attributes here. The SVR4 assembler does not
-   recognize section redefinitions.
-   If DECL is NULL, no attributes are emitted.  */
-
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC)		\
-do {									\
-  static struct section_info						\
-    {									\
-      struct section_info *next;				        \
-      char *name;						        \
-      enum sect_enum {SECT_RW, SECT_RO, SECT_EXEC} type;		\
-    } *sections;							\
-  struct section_info *s;						\
-  char *mode;								\
-  enum sect_enum type;							\
-									\
-  for (s = sections; s; s = s->next)					\
-    if (!strcmp (NAME, s->name))					\
-      break;								\
-									\
-  if (DECL && TREE_CODE (DECL) == FUNCTION_DECL)			\
-    type = SECT_EXEC, mode = "ax";					\
-  else if (DECL && DECL_READONLY_SECTION (DECL, RELOC))			\
-    type = SECT_RO, mode = "a";						\
-  else									\
-    type = SECT_RW, mode = "aw";					\
-									\
-  if (s == 0)								\
-    {									\
-      s = (struct section_info *) xmalloc (sizeof (struct section_info));  \
-      s->name = xmalloc ((strlen (NAME) + 1) * sizeof (*NAME));		\
-      strcpy (s->name, NAME);						\
-      s->type = type;							\
-      s->next = sections;						\
-      sections = s;							\
-      fprintf (FILE, ".section\t%s,\"%s\",@progbits\n", NAME, mode);	\
-    }									\
-  else									\
-    {									\
-      if (DECL && s->type != type)					\
-	error_with_decl (DECL, "%s causes a section type conflict");	\
-									\
-      fprintf (FILE, ".section\t%s\n", NAME);				\
-    }									\
-} while (0)
-
-#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
-#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
-#define UNIQUE_SECTION(DECL,RELOC)				\
-do {								\
-  int len;							\
-  char *name, *string, *prefix;					\
-								\
-  name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL));	\
-								\
-  if (! DECL_ONE_ONLY (DECL))					\
-    {								\
-      prefix = ".";                                             \
-      if (TREE_CODE (DECL) == FUNCTION_DECL)			\
-	prefix = ".text.";					\
-      else if (DECL_READONLY_SECTION (DECL, RELOC))		\
-	prefix = ".rodata.";					\
-      else							\
-	prefix = ".data.";					\
-    }								\
-  else if (TREE_CODE (DECL) == FUNCTION_DECL)			\
-    prefix = ".gnu.linkonce.t.";				\
-  else if (DECL_READONLY_SECTION (DECL, RELOC))			\
-    prefix = ".gnu.linkonce.r.";				\
-  else								\
-    prefix = ".gnu.linkonce.d.";				\
-								\
-  len = strlen (name) + strlen (prefix);			\
-  string = alloca (len + 1);					\
-  sprintf (string, "%s%s", prefix, name);			\
-								\
-  DECL_SECTION_NAME (DECL) = build_string (len, string);	\
-} while (0)
-/* A C statement (sans semicolon) to output an element in the table of
-   global constructors.  */
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-  do {									\
-    ctors_section ();							\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement (sans semicolon) to output an element in the table of
-   global destructors.  */
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
-  do {									\
-    dtors_section ();                   				\
-    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
-    assemble_name (FILE, NAME);              				\
-    fprintf (FILE, "\n");						\
-  } while (0)
-
-/* A C statement or statements to switch to the appropriate
-   section for output of DECL.  DECL is either a `VAR_DECL' node
-   or a constant of some sort.  RELOC indicates whether forming
-   the initial value of DECL requires link-time relocations.  */
-
-#define SELECT_SECTION(DECL,RELOC)					\
-{									\
-  if (flag_pic && RELOC)						\
-    data_section ();							\
-  else if (TREE_CODE (DECL) == STRING_CST)				\
-    {									\
-      if (! flag_writable_strings)					\
-	const_section ();						\
-      else								\
-	data_section ();						\
-    }									\
-  else if (TREE_CODE (DECL) == VAR_DECL)				\
-    {									\
-      if (! DECL_READONLY_SECTION (DECL, RELOC))			\
-	data_section ();						\
-      else								\
-	const_section ();						\
-    }									\
-  else									\
-    const_section ();							\
-}
-
-/* A C statement or statements to switch to the appropriate
-   section for output of RTX in mode MODE.  RTX is some kind
-   of constant in RTL.  The argument MODE is redundant except
-   in the case of a `const_int' rtx.  Currently, these always
-   go into the const section.  */
-
-#undef SELECT_RTX_SECTION
-#define SELECT_RTX_SECTION(MODE,RTX) const_section()
-
-/* Define the strings used for the special svr4 .type and .size directives.
-   These strings generally do not vary from one system running svr4 to
-   another, but if a given system (e.g. m88k running svr) needs to use
-   different pseudo-op names for these, they may be overridden in the
-   file which includes this one.  */
-
-#define TYPE_ASM_OP	".type"
-#define SIZE_ASM_OP	".size"
-
-/* This is how we tell the assembler that a symbol is weak.  */
-
-#define ASM_WEAKEN_LABEL(FILE,NAME) \
-  do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \
-       fputc ('\n', FILE); } while (0)
-
-/* The following macro defines the format used to output the second
-   operand of the .type assembler directive.  Different svr4 assemblers
-   expect various different forms for this operand.  The one given here
-   is just a default.  You may need to override it in your machine-
-   specific tm.h file (depending upon the particulars of your assembler).  */
-
-#define TYPE_OPERAND_FMT	"@%s"
-
-/* Write the extra assembler code needed to declare a function's result.
-   Most svr4 assemblers don't require any special declaration of the
-   result value, but there are exceptions.  */
-
-#ifndef ASM_DECLARE_RESULT
-#define ASM_DECLARE_RESULT(FILE, RESULT)
-#endif
-
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare a function properly.
-   Some svr4 assemblers need to also have something extra said about the
-   function's return value.  We allow for that here.  */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "function");			\
-    putc ('\n', FILE);							\
-    ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));			\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Write the extra assembler code needed to declare an object properly.  */
-
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
-    assemble_name (FILE, NAME);						\
-    putc (',', FILE);							\
-    fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
-    putc ('\n', FILE);							\
-    size_directive_output = 0;						\
-    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-      {									\
-	size_directive_output = 1;					\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, NAME);					\
-	putc (',', FILE);						\
-	fprintf (FILE, HOST_WIDE_INT_PRINT_DEC,				\
-		 int_size_in_bytes (TREE_TYPE (DECL)));			\
-	fputc ('\n', FILE);						\
-      }									\
-    ASM_OUTPUT_LABEL(FILE, NAME);					\
-  } while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
-	 assemble_name (FILE, name);					 \
-	 putc (',', FILE);						 \
-	 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC,			 \
-		  int_size_in_bytes (TREE_TYPE (DECL))); 		 \
-	fputc ('\n', FILE);						 \
-       }								 \
-   } while (0)
-
-/* This is how to declare the size of a function.  */
-
-#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)			\
-  do {									\
-    if (!flag_inhibit_size_directive)					\
-      {									\
-        char label[256];						\
-	static int labelno;						\
-	labelno++;							\
-	ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno);		\
-	ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno);		\
-	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
-	assemble_name (FILE, (FNAME));					\
-        fprintf (FILE, ",");						\
-	assemble_name (FILE, label);					\
-        fprintf (FILE, "-");						\
-	assemble_name (FILE, (FNAME));					\
-	putc ('\n', FILE);						\
-      }									\
-  } while (0)
-
-/* A table of bytes codes used by the ASM_OUTPUT_ASCII and
-   ASM_OUTPUT_LIMITED_STRING macros.  Each byte in the table
-   corresponds to a particular byte value [0..255].  For any
-   given byte value, if the value in the corresponding table
-   position is zero, the given character can be output directly.
-   If the table value is 1, the byte must be output as a \ooo
-   octal escape.  If the tables value is anything else, then the
-   byte value should be output as a \ followed by the value
-   in the table.  Note that we can use standard UN*X escape
-   sequences for many control characters, but we don't use
-   \a to represent BEL because some svr4 assemblers (e.g. on
-   the i386) don't know about that.  Also, we don't use \v
-   since some versions of gas, such as 2.2 did not accept it.  */
-
-#define ESCAPES \
-"\1\1\1\1\1\1\1\1btn\1fr\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\0\0\"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
-\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\\\0\0\0\
-\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
-\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1"
-
-/* Some svr4 assemblers have a limit on the number of characters which
-   can appear in the operand of a .string directive.  If your assembler
-   has such a limitation, you should define STRING_LIMIT to reflect that
-   limit.  Note that at least some svr4 assemblers have a limit on the
-   actual number of bytes in the double-quoted string, and that they
-   count each character in an escape sequence as one byte.  Thus, an
-   escape sequence like \377 would count as four bytes.
-
-   If your target assembler doesn't support the .string directive, you
-   should define this to zero.
-*/
-
-#define STRING_LIMIT	((unsigned) 256)
-
-#define STRING_ASM_OP	".string"
-
-/* The routine used to output NUL terminated strings.  We use a special
-   version of this for most svr4 targets because doing so makes the
-   generated assembly code more compact (and thus faster to assemble)
-   as well as more readable, especially for targets like the i386
-   (where the only alternative is to output character sequences as
-   comma separated lists of numbers).   */
-
-#define ASM_OUTPUT_LIMITED_STRING(FILE, STR)				\
-  do									\
-    {									\
-      register unsigned char *_limited_str = (unsigned char *) (STR);	\
-      register unsigned ch;						\
-      fprintf ((FILE), "\t%s\t\"", STRING_ASM_OP);			\
-      for (; (ch = *_limited_str); _limited_str++)			\
-        {								\
-	  register int escape;						\
-	  switch (escape = ESCAPES[ch])					\
-	    {								\
-	    case 0:							\
-	      putc (ch, (FILE));					\
-	      break;							\
-	    case 1:							\
-	      fprintf ((FILE), "\\%03o", ch);				\
-	      break;							\
-	    default:							\
-	      putc ('\\', (FILE));					\
-	      putc (escape, (FILE));					\
-	      break;							\
-	    }								\
-        }								\
-      fprintf ((FILE), "\"\n");						\
-    }									\
-  while (0)
-
-/* The routine used to output sequences of byte values.  We use a special
-   version of this for most svr4 targets because doing so makes the
-   generated assembly code more compact (and thus faster to assemble)
-   as well as more readable.  Note that if we find subparts of the
-   character sequence which end with NUL (and which are shorter than
-   STRING_LIMIT) we output those using ASM_OUTPUT_LIMITED_STRING.  */
-
-#undef ASM_OUTPUT_ASCII
-#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH)				\
-  do									\
-    {									\
-      register unsigned char *_ascii_bytes = (unsigned char *) (STR);	\
-      register unsigned char *limit = _ascii_bytes + (LENGTH);		\
-      register unsigned bytes_in_chunk = 0;				\
-      for (; _ascii_bytes < limit; _ascii_bytes++)			\
-        {								\
-	  register unsigned char *p;					\
-	  if (bytes_in_chunk >= 60)					\
-	    {								\
-	      fprintf ((FILE), "\"\n");					\
-	      bytes_in_chunk = 0;					\
-	    }								\
-	  for (p = _ascii_bytes; p < limit && *p != '\0'; p++)		\
-	    continue;							\
-	  if (p < limit && (p - _ascii_bytes) <= (long)STRING_LIMIT)	\
-	    {								\
-	      if (bytes_in_chunk > 0)					\
-		{							\
-		  fprintf ((FILE), "\"\n");				\
-		  bytes_in_chunk = 0;					\
-		}							\
-	      ASM_OUTPUT_LIMITED_STRING ((FILE), _ascii_bytes);		\
-	      _ascii_bytes = p;						\
-	    }								\
-	  else								\
-	    {								\
-	      register int escape;					\
-	      register unsigned ch;					\
-	      if (bytes_in_chunk == 0)					\
-		fprintf ((FILE), "\t%s\t\"", ASCII_DATA_ASM_OP);	\
-	      switch (escape = ESCAPES[ch = *_ascii_bytes])		\
-		{							\
-		case 0:							\
-		  putc (ch, (FILE));					\
-		  bytes_in_chunk++;					\
-		  break;						\
-		case 1:							\
-		  fprintf ((FILE), "\\%03o", ch);			\
-		  bytes_in_chunk += 4;					\
-		  break;						\
-		default:						\
-		  putc ('\\', (FILE));					\
-		  putc (escape, (FILE));				\
-		  bytes_in_chunk += 2;					\
-		  break;						\
-		}							\
-	    }								\
-	}								\
-      if (bytes_in_chunk > 0)						\
-        fprintf ((FILE), "\"\n");					\
-    }									\
-  while (0)
-
-/* All SVR4 targets use the ELF object file format.  */
-#define OBJECT_FORMAT_ELF
diff --git a/gcc/config/t-gnu b/gcc/config/t-gnu
deleted file mode 100755
index 58969f2..0000000
--- a/gcc/config/t-gnu
+++ /dev/null
@@ -1,13 +0,0 @@
-LIBGCC1=libgcc1.null
-CROSS_LIBGCC1=libgcc1.null
-
-# The pushl in CTOR initialization interferes with frame pointer elimination.
-
-# We need to use -fPIC when we are using gcc to compile the routines in
-# crtstuff.c.  This is only really needed when we are going to use gcc/g++
-# to produce a shared library, but since we don't know ahead of time when
-# we will be doing that, we just always use -fPIC when compiling the
-# routines in crtstuff.c.
-
-CRTSTUFF_T_CFLAGS = -fPIC -fno-omit-frame-pointer
-TARGET_LIBGCC2_CFLAGS = -fPIC
diff --git a/gcc/config/t-libc-ok b/gcc/config/t-libc-ok
deleted file mode 100755
index 43e4f5e..0000000
--- a/gcc/config/t-libc-ok
+++ /dev/null
@@ -1,3 +0,0 @@
-LIBGCC1=libgcc1.null
-CROSS_LIBGCC1=libgcc1.null
-CRTSTUFF_T_FLAGS_S=-fPIC
diff --git a/gcc/config/t-linux b/gcc/config/t-linux
deleted file mode 100755
index d67feed..0000000
--- a/gcc/config/t-linux
+++ /dev/null
@@ -1,16 +0,0 @@
-# Don't run fixproto
-STMP_FIXPROTO =
-
-# Don't install "assert.h" in gcc. We use the one in glibc.
-INSTALL_ASSERT_H =
-
-# Compile crtbeginS.o and crtendS.o with pic.
-CRTSTUFF_T_CFLAGS_S = -fPIC
-# Compile libgcc2.a with pic.
-TARGET_LIBGCC2_CFLAGS = -fPIC
-
-# Do not build libgcc1. Let gcc generate those functions. The GNU/Linux
-# C library can handle them.
-LIBGCC1 = 
-CROSS_LIBGCC1 =
-LIBGCC1_TEST =
diff --git a/gcc/config/t-linux-aout b/gcc/config/t-linux-aout
deleted file mode 100755
index 8826cdd..0000000
--- a/gcc/config/t-linux-aout
+++ /dev/null
@@ -1,11 +0,0 @@
-# Don't run fixproto
-STMP_FIXPROTO =
-
-# Don't install "assert.h" in gcc. We use the one in glibc.
-INSTALL_ASSERT_H =
-
-# Do not build libgcc1. Let gcc generate those functions. The GNU/Linux
-# C library can handle them.
-LIBGCC1 = 
-CROSS_LIBGCC1 =
-LIBGCC1_TEST =
diff --git a/gcc/config/t-linux-gnulibc1 b/gcc/config/t-linux-gnulibc1
deleted file mode 100755
index 7bb7bce..0000000
--- a/gcc/config/t-linux-gnulibc1
+++ /dev/null
@@ -1,2 +0,0 @@
-# We are building for the Linux C library 5.
-T_CFLAGS = -DUSE_GNULIBC_1
diff --git a/gcc/config/t-netbsd b/gcc/config/t-netbsd
deleted file mode 100755
index 85d6057..0000000
--- a/gcc/config/t-netbsd
+++ /dev/null
@@ -1,9 +0,0 @@
-LIBGCC1=libgcc1.null
-CROSS_LIBGCC1=libgcc1.null
-LIBGCC1_TEST=
-
-# Don't run fixproto
-STMP_FIXPROTO =
-
-# Don't install "assert.h" in gcc. We use the one in glibc.
-INSTALL_ASSERT_H =
diff --git a/gcc/config/t-rtems b/gcc/config/t-rtems
deleted file mode 100755
index aa0ca66..0000000
--- a/gcc/config/t-rtems
+++ /dev/null
@@ -1,6 +0,0 @@
-# RTEMS uses newlib which does not require prototype fixing
-STMP_FIXPROTO =
-
-# Don't install "assert.h" in gcc.  RTEMS uses the one in newlib.
-INSTALL_ASSERT_H =
-
diff --git a/gcc/config/t-svr4 b/gcc/config/t-svr4
deleted file mode 100755
index e6be0c3..0000000
--- a/gcc/config/t-svr4
+++ /dev/null
@@ -1,8 +0,0 @@
-# We need to use -fPIC when we are using gcc to compile the routines in
-# crtstuff.c.  This is only really needed when we are going to use gcc/g++
-# to produce a shared library, but since we don't know ahead of time when
-# we will be doing that, we just always use -fPIC when compiling the
-# routines in crtstuff.c.  Likewise for libgcc2.c.
-
-CRTSTUFF_T_CFLAGS = -fPIC
-TARGET_LIBGCC2_CFLAGS = -fPIC
diff --git a/gcc/config/tahoe/harris.h b/gcc/config/tahoe/harris.h
deleted file mode 100755
index 9226445..0000000
--- a/gcc/config/tahoe/harris.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Harris tahoe version.
-   Copyright (C) 1989, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "tahoe/tahoe.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dtahoe -Dunix -Dhcx -Asystem(unix) -Acpu(tahoe) -Amachine(tahoe)"
-
-#undef DBX_DEBUGGING_INFO
-#define SDB_DEBUGGING_INFO
-
-#undef LIB_SPEC
-
-#undef TARGET_DEFAULT
-#define TARGET_DEFAULT 1
-
-/* urem and udiv don't exist on this system.  */
-#undef UDIVSI3_LIBCALL
-#undef UMODSI3_LIBCALL
-
-/* Operand of .align is not logarithmic.  */
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
-  LOG ? fprintf (FILE, "\t.align %d\n", 1 << (LOG)) : 0
-
-/* For the same reason, we need .align 2 after casesi.  */
-#undef PRINT_OPERAND
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ if (CODE == '@')							\
-    putc ('2', FILE);							\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else { putc ('$', FILE); output_addr_const (FILE, X); }}
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".bss ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u,4\n", (ROUNDED)))
-
-/* Output at beginning of assembler file.  */
-/* The .file command should always begin the output.  */
-
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE)			\
-  output_file_directive ((FILE), main_input_filename);
-
-#define ASM_OUTPUT_ASCII(FILE, PTR, SIZE)		\
-do {							\
-  unsigned char *_p = (PTR);				\
-  int _thissize = (SIZE);				\
-  fprintf ((FILE), "\t.ascii \"");			\
-  for (i = 0; i < _thissize; i++)			\
-    {							\
-      register int c = _p[i];				\
-      if (c >= ' ' && c < 0177 && c != '\"' && c != '\\') \
-	putc (c, (FILE));				\
-      else						\
-	{						\
-	  fprintf ((FILE), "\\%o", c);			\
-	  if (i < _thissize - 1				\
-	      && _p[i + 1] >= '0' && _p[i + 1] <= '9')	\
-	    fprintf ((FILE), "\"\n\t.ascii \"");	\
-	}						\
-    }							\
-  fprintf ((FILE), "\"\n");				\
-} while (0)
diff --git a/gcc/config/tahoe/tahoe.c b/gcc/config/tahoe/tahoe.c
deleted file mode 100755
index 9dd189b..0000000
--- a/gcc/config/tahoe/tahoe.c
+++ /dev/null
@@ -1,564 +0,0 @@
-/* Subroutines for insn-output.c for Tahoe.
-   Copyright (C) 1989, 1991, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-
-/*
- * File: output-tahoe.c
- *
- * Original port made at the University of Buffalo by Devon Bowen,
- * Dale Wiles and Kevin Zachmann.
- *
- * Changes for HCX by Piet van Oostrum,
- * University of Utrecht, The Netherlands (piet@cs.ruu.nl)
- *
- * Speed tweaks by Michael Tiemann (tiemann@lurch.stanford.edu).
- *
- * Mail bugs reports or fixes to:	gcc@cs.buffalo.edu
- */
-
-
-/* On tahoe, you have to go to memory to convert a register
-   from sub-word to word.  */
-
-rtx tahoe_reg_conversion_loc;
-
-int
-extensible_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if ((GET_CODE (op) == REG
-       || (GET_CODE (op) == SUBREG
-	   && GET_CODE (SUBREG_REG (op)) == REG))
-      && tahoe_reg_conversion_loc == 0)
-    tahoe_reg_conversion_loc = assign_stack_local (SImode, GET_MODE_SIZE (SImode));
-  return general_operand (op, mode);
-}
-
-/* most of the print_operand_address function was taken from the vax	*/
-/* since the modes are basically the same. I had to add a special case,	*/
-/* though, for symbol references with offsets.				*/
-
-print_operand_address (file, addr)
-     FILE *file;
-     register rtx addr;
-{
-  register rtx reg1, reg2, breg, ireg;
-  rtx offset;
-  static char *reg_name[] = REGISTER_NAMES;
-
- retry:
-  switch (GET_CODE (addr))
-    {
-    case MEM:
-      fprintf (file, "*");
-      addr = XEXP (addr, 0);
-      goto retry;
-
-    case REG:
-      fprintf (file, "(%s)", reg_name [REGNO (addr)]);
-      break;
-
-    case PRE_DEC:
-      fprintf (file, "-(%s)", reg_name [REGNO (XEXP (addr, 0))]);
-      break;
-
-    case POST_INC:
-      fprintf (file, "(%s)+", reg_name [REGNO (XEXP (addr, 0))]);
-      break;
-
-    case PLUS:
-      reg1 = 0;	reg2 = 0;
-      ireg = 0;	breg = 0;
-      offset = 0;
-
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
-	  && GET_CODE (XEXP (addr, 1)) == CONST_INT)
-	output_addr_const (file, addr);
-
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
-	  && GET_CODE (XEXP (addr, 0)) == CONST_INT)
-	output_addr_const (file, addr);
-
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
-	  || GET_CODE (XEXP (addr, 0)) == MEM)
-	{
-	  offset = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
-	}
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
-	       || GET_CODE (XEXP (addr, 1)) == MEM)
-	{
-	  offset = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-      if (GET_CODE (addr) != PLUS)
-	;
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)
-	{
-	  reg1 = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
-	}
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)
-	{
-	  reg1 = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-      else if (GET_CODE (XEXP (addr, 0)) == REG)
-	{
-	  reg1 = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
-	}
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	{
-	  reg1 = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-      if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
-	{
-	  if (reg1 == 0)
-	    reg1 = addr;
-	  else
-	    reg2 = addr;
-	  addr = 0;
-	}
-      if (offset != 0)
-	{
-	  if (addr != 0) abort ();
-	  addr = offset;
-	}
-      if (reg1 != 0 && GET_CODE (reg1) == MULT)
-	{
-	  breg = reg2;
-	  ireg = reg1;
-	}
-      else if (reg2 != 0 && GET_CODE (reg2) == MULT)
-	{
-	  breg = reg1;
-	  ireg = reg2;
-	}
-      else if (reg2 != 0 || GET_CODE (addr) == MEM)
-	{
-	  breg = reg2;
-	  ireg = reg1;
-	}
-      else
-	{
-	  breg = reg1;
-	  ireg = reg2;
-	}
-      if (addr != 0)
-	output_address (offset);
-      if (breg != 0)
-	{
-	  if (GET_CODE (breg) != REG)
-	    abort ();
-	  fprintf (file, "(%s)", reg_name[REGNO (breg)]);
-	}
-      if (ireg != 0)
-	{
-	  if (GET_CODE (ireg) == MULT)
-	    ireg = XEXP (ireg, 0);
-	  if (GET_CODE (ireg) != REG)
-	    abort ();
-	  fprintf (file, "[%s]", reg_name[REGNO (ireg)]);
-	}
-      break;
-
-    default:
-      output_addr_const (file, addr);
-    }
-}
-
-/* Do a quick check and find out what the best way to do the */
-/* mini-move is. Could be a push or a move.....		     */
-
-static char *
-singlemove_string (operands)
-     rtx *operands;
-{
-  if (operands[1] == const0_rtx)
-      return "clrl %0";
-  if (push_operand (operands[0], SImode))
-    return "pushl %1";
-  return "movl %1,%0";
-}
-
-/* given the rtx for an address, return true if the given */
-/* register number is used in the address somewhere.	  */
-
-regisused(addr,regnum)
-rtx addr;
-int regnum;
-{
-	if (GET_CODE(addr) == REG)
-		if (REGNO(addr) == regnum)
-			return (1);
-		else
-			return (0);
-
-	if (GET_CODE(addr) == MEM)
-		return regisused(XEXP(addr,0),regnum);
-
-	if ((GET_CODE(addr) == MULT) || (GET_CODE(addr) == PLUS))
-		return ((regisused(XEXP(addr,0),regnum)) ||
-					(regisused(XEXP(addr,1),regnum)));
-
-	return 0;
-}
-
-
-/* Given some rtx, traverse it and return the register used in a */
-/* index. If no index is found, return 0.			 */
-
-rtx
-index_reg(addr)
-rtx addr;
-{
-	rtx temp;
-
-	if (GET_CODE(addr) == MEM)
-		return index_reg(XEXP(addr,0));
-
-	if (GET_CODE(addr) == MULT)
-		if (GET_CODE(XEXP(addr,0)) == REG)
-			return XEXP(addr,0);
-		else
-			return XEXP(addr,1);
-
-	if (GET_CODE(addr) == PLUS)
-		if (temp = index_reg(XEXP(addr,0)))
-			return temp;
-		else
-			return index_reg(XEXP(addr,1));
-
-	return 0;
-}
-
-
-/* simulate the move double by generating two movl's. You have */
-/* to be careful about mixing modes here.		       */
-
-char *
-output_move_double (operands)
-     rtx *operands;
-{
-  enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, INDOP, CNSTOP, RNDOP }
-    optype0, optype1;
-  rtx latehalf[2];
-  rtx shftreg0 = 0, shftreg1 = 0;
-  rtx temp0 = 0, temp1 = 0;
-  rtx addreg0 = 0, addreg1 = 0;
-  int dohighfirst = 0;
-
-  /* First classify both operands. */
-
-  if (REG_P (operands[0]))
-    optype0 = REGOP;
-  else if ((GET_CODE(operands[0])==MEM) && (shftreg0=index_reg(operands[0])))
-    optype0 = INDOP;
-  else if (offsettable_memref_p (operands[0]))
-    optype0 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) {
-    optype0 = PUSHOP;
-    dohighfirst++;
-  } else if (GET_CODE (operands[0]) == MEM)
-    optype0 = MEMOP;
-  else
-    optype0 = RNDOP;
-
-  if (REG_P (operands[1]))
-    optype1 = REGOP;
-  else if ((GET_CODE(operands[1])==MEM) && (shftreg1=index_reg(operands[1])))
-    optype1 = INDOP;
-  else if (offsettable_memref_p (operands[1]))
-    optype1 = OFFSOP;
-  else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
-    optype1 = POPOP; 
-  else if (GET_CODE (operands[1]) == MEM)
-    optype1 = MEMOP;
-  else if (CONSTANT_P (operands[1]))
-    optype1 = CNSTOP;
-  else
-    optype1 = RNDOP;
-
-  /* set up for the high byte move for operand zero */
-
-  switch (optype0) {
-
-	/* if it's a register, just use the next highest in the */
-	/* high address move.					*/
-
-	case REGOP  : latehalf[0] = gen_rtx (REG,SImode,REGNO(operands[0])+1);
-		      break;
-
-	/* for an offsettable address, use the gcc function to  */
-	/* modify the operand to get an offset of 4 higher for  */
-	/* the second move.					*/
-
-	case OFFSOP : latehalf[0] = adj_offsettable_operand (operands[0], 4);
-		      break;
-
-	/* if the operand is MEMOP type, it must be a pointer	*/
-	/* to a pointer. So just remember to increase the mem	*/
-	/* location and use the same operand.			*/
-
-	case MEMOP  : latehalf[0] = operands[0];
-		      addreg0 = XEXP(operands[0],0);
-		      break;
-
-	/* if we're dealing with a push instruction, just leave */
-	/* the operand alone since it auto-increments.		*/
-
-	case PUSHOP : latehalf[0] = operands[0];
-		      break;
-
-	/* YUCK! Indexed addressing!! If the address is considered   */
-	/* offsettable, go use the offset in the high part. Otherwise */
-	/* find what exactly is being added to the multiplication. If */
-	/* it's a mem reference, increment that with the high part   */
-	/* being unchanged to cause the shift. If it's a reg, do the */
-	/* same. If you can't identify it, abort. Remember that the  */
-	/* shift register was already set during identification.     */
-
-	case INDOP  : if (offsettable_memref_p(operands[0])) {
-			   latehalf[0] = adj_offsettable_operand(operands[0],4);
-			   break;
-		      }
-
-		      latehalf[0] = operands[0];
-
-		      temp0 = XEXP(XEXP(operands[0],0),0);
-                      if (GET_CODE(temp0) == MULT) {
-			   temp1 = temp0;
-			   temp0 = XEXP(XEXP(operands[0],0),1);
-		      } else {
-			   temp1 = XEXP(XEXP(operands[0],0),1);
-			   if (GET_CODE(temp1) != MULT)
-				abort();
-		      }
-
-		      if (GET_CODE(temp0) == MEM)
-			   addreg0 = temp0;
-		      else if (GET_CODE(temp0) == REG)
-			   addreg0 = temp0;
-		      else
-			   abort();
-
-		      break;
-
-	/* if we don't know the operand type, print a friendly  */
-	/* little error message...   8-)			*/
-
-	case RNDOP  :
-	default     : abort();
-  }
-
-  /* do the same setup for operand one */
-
-  switch (optype1) {
-
-	case REGOP  : latehalf[1] = gen_rtx(REG,SImode,REGNO(operands[1])+1);
-		      break;
-
-	case OFFSOP : latehalf[1] = adj_offsettable_operand (operands[1], 4);
-		      break;
-
-	case MEMOP  : latehalf[1] = operands[1];
-		      addreg1 = XEXP(operands[1],0);
-		      break;
-
-	case POPOP  : latehalf[1] = operands[1];
-		      break;
-
-	case INDOP  : if (offsettable_memref_p(operands[1])) {
-			   latehalf[1] = adj_offsettable_operand(operands[1],4);
-			   break;
-		      }
-
-		      latehalf[1] = operands[1];
-
-		      temp0 = XEXP(XEXP(operands[1],0),0);
-                      if (GET_CODE(temp0) == MULT) {
-			   temp1 = temp0;
-			   temp0 = XEXP(XEXP(operands[1],0),1);
-		      } else {
-			   temp1 = XEXP(XEXP(operands[1],0),1);
-			   if (GET_CODE(temp1) != MULT)
-				abort();
-		      }
-
-		      if (GET_CODE(temp0) == MEM)
-			   addreg1 = temp0;
-		      else if (GET_CODE(temp0) == REG)
-			   addreg1 = temp0;
-		      else
-			   abort();
-
-		      break;
-
-	case CNSTOP :
-	  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-	    split_double (operands[1], &operands[1], &latehalf[1]);
-	  else if (CONSTANT_P (operands[1]))
-	    latehalf[1] = const0_rtx;
-	  else abort ();
-	  break;
-
-	case RNDOP  :
-	default     : abort();
-  }
-
-
-  /* double the register used for shifting in both of the operands */
-  /* but make sure the same register isn't doubled twice!	   */
-
-  if (shftreg0 && shftreg1 && (rtx_equal_p(shftreg0,shftreg1)))
-	output_asm_insn("addl2 %0,%0", &shftreg0);
-  else {
-	if (shftreg0)
-		output_asm_insn("addl2 %0,%0", &shftreg0);
-	if (shftreg1)
-		output_asm_insn("addl2 %0,%0", &shftreg1);
-  }
-
-  /* if the destination is a register and that register is needed in  */
-  /* the source addressing mode, swap the order of the moves since we */
-  /* don't want this destroyed til last. If both regs are used, not   */
-  /* much we can do, so abort. If these becomes a problem, maybe we   */
-  /* can do it on the stack?					      */
-
-  if (GET_CODE(operands[0])==REG && regisused(operands[1],REGNO(operands[0])))
-	if (regisused(latehalf[1],REGNO(latehalf[0])))
-		8;
-	else
-		dohighfirst++;
-
-  /* if we're pushing, do the high address part first. */
-
-  if (dohighfirst) {
-
-	if (addreg0 && addreg1 && (rtx_equal_p(addreg0,addreg1)))
-		output_asm_insn("addl2 $4,%0", &addreg0);
-	else {
-		if (addreg0)
-			output_asm_insn("addl2 $4,%0", &addreg0);
-		if (addreg1)
-			output_asm_insn("addl2 $4,%0", &addreg1);
-	}
-
-	output_asm_insn(singlemove_string(latehalf), latehalf);
-
-	if (addreg0 && addreg1 && (rtx_equal_p(addreg0,addreg1)))
-		output_asm_insn("subl2 $4,%0", &addreg0);
-	else {
-		if (addreg0)
-			output_asm_insn("subl2 $4,%0", &addreg0);
-		if (addreg1)
-			output_asm_insn("subl2 $4,%0", &addreg1);
-	}
-
-	return singlemove_string(operands);
-  }
-
-  output_asm_insn(singlemove_string(operands), operands);
-
-  if (addreg0 && addreg1 && (rtx_equal_p(addreg0,addreg1)))
-	output_asm_insn("addl2 $4,%0", &addreg0);
-  else {
-	if (addreg0)
-		output_asm_insn("addl2 $4,%0", &addreg0);
-	if (addreg1)
-		output_asm_insn("addl2 $4,%0", &addreg1);
-  }
-
-  output_asm_insn(singlemove_string(latehalf), latehalf);
-
-  if (addreg0 && addreg1 && (rtx_equal_p(addreg0,addreg1)))
-	output_asm_insn("subl2 $4,%0", &addreg0);
-  else {
-	if (addreg0)
-		output_asm_insn("subl2 $4,%0", &addreg0);
-	if (addreg1)
-		output_asm_insn("subl2 $4,%0", &addreg1);
-  }
-
-  if (shftreg0 && shftreg1 && (rtx_equal_p(shftreg0,shftreg1)))
-	output_asm_insn("shar $1,%0,%0", &shftreg0);
-  else {
-	if (shftreg0)
-		output_asm_insn("shar $1,%0,%0", &shftreg0);
-	if (shftreg1)
-		output_asm_insn("shar $1,%0,%0", &shftreg1);
-  }
-
-  return "";
-}
-
-
-/* This checks if a zero_extended cmp[bw] can be replaced by a sign_extended
-   cmp[bw]. This can be done if the operand is a constant that fits in a
-   byte/word or a memory operand. Besides that the next instruction must be an
-   unsigned compare. Some of these tests are done by the machine description */
-
-int
-tahoe_cmp_check (insn, op, max)
-rtx insn, op; int max;
-{
-    if (GET_CODE (op) == CONST_INT
-	&& ( INTVAL (op) < 0 || INTVAL (op) > max ))
-	return 0;
-    {
-	register rtx next = NEXT_INSN (insn);
-
-	if ((GET_CODE (next) == JUMP_INSN
-	   || GET_CODE (next) == INSN
-	   || GET_CODE (next) == CALL_INSN))
-	    {
-		next = PATTERN (next);
-		if (GET_CODE (next) == SET
-		    && SET_DEST (next) == pc_rtx
-		    && GET_CODE (SET_SRC (next)) == IF_THEN_ELSE)
-		    switch (GET_CODE (XEXP (SET_SRC (next), 0)))
-			{
-			case EQ:
-			case NE:
-			case LTU:
-			case GTU:
-			case LEU:
-			case GEU:
-			    return 1;
-			}
-	    }
-    }
-    return 0;
-}
diff --git a/gcc/config/tahoe/tahoe.h b/gcc/config/tahoe/tahoe.h
deleted file mode 100755
index 29ac013..0000000
--- a/gcc/config/tahoe/tahoe.h
+++ /dev/null
@@ -1,1017 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Tahoe version.
-   Copyright (C) 1989, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/*
- * Original port made at the University of Buffalo by Devon Bowen,
- * Dale Wiles and Kevin Zachmann.
- *
- * HCX/UX version by Piet van Oostrum (piet@cs.ruu.nl)
- *
- * Performance hacking by Michael Tiemann (tiemann@cygnus.com)
- */
-
-/* define this for the HCX/UX version */
-
-/* #define HCX_UX */
-
-/*
- * Run-time Target Specification
- */
-
-#ifdef HCX_UX
-/* no predefines, see Makefile and hcx-universe.c */
-/* have cc1 print that this is the hcx version */
-#define TARGET_VERSION printf (" (hcx)");
-#else
-/* we want "tahoe" and "unix" defined for all future compilations */
-#define CPP_PREDEFINES "-Dtahoe -Dunix -Asystem(unix) -Acpu(tahoe) -Amachine(tahoe)"
-/* have cc1 print that this is the tahoe version */
-#define TARGET_VERSION printf (" (tahoe)");
-#endif
-
-/* this is required in all tm files to hold flags */
-
-extern int target_flags;
-
-/* Zero if it is safe to output .dfloat and .float pseudos.  */
-#define TARGET_HEX_FLOAT (target_flags & 1)
-
-#define TARGET_DEFAULT 1
-
-#define TARGET_SWITCHES		\
-  { {"hex-float", 1},		\
-    {"no-hex-float", -1},	\
-    { "", TARGET_DEFAULT} }
-
-
-/*
- * Storage Layout
- */
-
-/* This symbol was previously not mentioned, so apparently the tahoe
-   is little-endian for bits, or else doesn't care.  */
-#define BITS_BIG_ENDIAN 0
-
-/* tahoe uses a big endian byte order */
-
-#define BYTES_BIG_ENDIAN 1
-
-/* tahoe uses a big endian word order */
-
-#define WORDS_BIG_ENDIAN 1
-
-/* standard byte size is usable on tahoe */
-
-#define BITS_PER_UNIT 8
-
-/* longs on the tahoe are 4 byte groups */
-
-#define BITS_PER_WORD 32
-
-/* from the last two params we get 4 bytes per word */
-
-#define UNITS_PER_WORD 4
-
-/* addresses are 32 bits (one word) */
-
-#define POINTER_SIZE 32
-
-/* all parameters line up on 32 boundaries */
-
-#define PARM_BOUNDARY 32
-
-/* stack should line up on 32 boundaries */
-
-#define STACK_BOUNDARY 32
-
-/* line functions up on 32 bits */
-
-#define FUNCTION_BOUNDARY 32
-
-/* the biggest alignment the tahoe needs in 32 bits */
-
-#define BIGGEST_ALIGNMENT 32
-
-/* we have to align after an 'int : 0' in a structure */
-
-#define EMPTY_FIELD_BOUNDARY 32
-
-#ifdef HCX_UX
-/* structures must be made of full words */
-
-#define STRUCTURE_SIZE_BOUNDARY 32
-#else
-/* structures must be made of full bytes */
-
-#define STRUCTURE_SIZE_BOUNDARY 8
-#endif
-
-/* tahoe is picky about data alignment */
-
-#define STRICT_ALIGNMENT 1
-
-/* keep things standard with pcc */
-
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* this section is borrowed from the vax version since the */
-/* formats are the same in both of the architectures	   */
-
-#define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
-  if (OVERFLOW)								\
-    (D) = 1.7014117331926443e+38;					\
-  else if ((MODE) == SFmode)						\
-    {									\
-      if ((D) > 1.7014117331926443e+38)					\
-	(OVERFLOW) = 1, (D) = 1.7014117331926443e+38;			\
-      else if ((D) < -1.7014117331926443e+38)				\
-	(OVERFLOW) = 1, (D) = -1.7014117331926443e+38;			\
-      else if (((D) > 0) && ((D) < 2.9387358770557188e-39))		\
-	(OVERFLOW) = 1, (D) = 0.0;					\
-      else if (((D) < 0) && ((D) > -2.9387358770557188e-39))		\
-	(OVERFLOW) = 1, (D) = 0.0;					\
-    }
-
-
-/*
- * Register Usage
- */
-
-/* define 15 general regs plus one for the floating point reg (FPP) */
-
-#define FIRST_PSEUDO_REGISTER 17
-
-/* let the compiler know what the fp, sp and pc are */
-
-#define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0}
-
-/* lots of regs aren't guaranteed to return from a call. The FPP reg */
-/* must be included in these since it can't be saved by the reg mask */
-
-#define CALL_USED_REGISTERS {1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
-
-/* A single fp reg can handle any type of float.
-   CPU regs hold just 32 bits.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE) \
- (REGNO != 16 ? ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD)  \
-  : GET_MODE_NUNITS ((MODE)))
-
-/* any mode greater than 4 bytes (doubles) can only go in an even regs */
-/* and the FPP can only hold SFmode and DFmode 			       */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (REGNO != 16							\
-  ? (GET_MODE_UNIT_SIZE (MODE) <= 4 ? 1 : (REGNO % 2 - 1))	\
-  : ((MODE) == SFmode || (MODE) == DFmode			\
-     || (MODE) == SCmode || (MODE) == DCmode))
-
-/* if mode1 or mode2, but not both, are doubles then modes cannot be tied */
-
-#define MODES_TIEABLE_P(MODE1, MODE2) \
- (((MODE1) == DFmode || (MODE1) == DCmode)	\
-  == ((MODE2) == DFmode || (MODE2) == DCmode))
-
-/* return nonzero if register variable of mode MODE is not
-   a priori a bad idea.  Used only if defined.  */
-#define MODE_OK_FOR_USERVAR(MODE)	\
-  ((MODE) == SImode)
-
-/* the program counter is reg 15 */
-
-#define PC_REGNUM 15
-
-/* the stack pointer is reg 14 */
-
-#define STACK_POINTER_REGNUM 14
-
-/* the frame pointer is reg 13 */
-
-#define FRAME_POINTER_REGNUM 13
-
-/* tahoe does require an fp */
-
-#define FRAME_POINTER_REQUIRED 1
-
-/* since tahoe doesn't have a argument pointer, make it the fp */
-
-#define ARG_POINTER_REGNUM 13
-
-/* this isn't currently used since C doesn't support this feature */
-
-#define STATIC_CHAIN_REGNUM 0
-
-/* we'll use reg 1 for structure passing cause the destination */
-/* of the eventual movblk requires it to be there anyway.      */
-
-#define STRUCT_VALUE_REGNUM 1
-
-
-/*
- * Register Classes
- */
-
-/* tahoe has two types of regs. GENERAL_REGS are all the regs up */
-/* to number 15. FPP_REG is the special floating point processor  */
-/* register class (only one reg).				  */
-
-enum reg_class {NO_REGS,GENERAL_REGS,FPP_REG,ALL_REGS,LIM_REG_CLASSES};
-
-/* defines the number of reg classes.				    */
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* this defines what the classes are officially named for debugging */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS","GENERAL_REGS","FPP_REG","ALL_REGS"}
-
-/* set general regs to be the first 16 regs and the fpp reg to be 17th */
-
-#define REG_CLASS_CONTENTS {0,0xffff,0x10000,0x1ffff}
-
-/* register class for the fpp reg is FPP_REG, all others are GENERAL_REGS */
-
-#define REGNO_REG_CLASS(REGNO) (REGNO == 16 ? FPP_REG : GENERAL_REGS)
-
-/* only general registers can be used as a base reg */
-
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* only general registers can be used to index */
-
-#define INDEX_REG_CLASS GENERAL_REGS
-
-/* 'a' as a constraint in the md file means the FFP_REG class */
-
-#define REG_CLASS_FROM_LETTER(C) (C == 'a' ? FPP_REG : NO_REGS)
-
-/* any general reg but the fpp can be a base reg */
-
-#define REGNO_OK_FOR_BASE_P(regno) \
-((regno) < FIRST_PSEUDO_REGISTER - 1 || reg_renumber[regno] >= 0)
-
-/* any general reg except the pc and fpp can be an index reg */
-
-#define REGNO_OK_FOR_INDEX_P(regno)  \
-((regno) < FIRST_PSEUDO_REGISTER - 2 || reg_renumber[regno] >= 0)
-
-/* if your loading a floating point constant, it can't be done */
-/* through a register. Force it to be a memory constant.       */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
-	((GET_CODE (X) == CONST_DOUBLE) ? NO_REGS : CLASS)
-
-/* for the fpp reg, all modes fit; for any others, you need two for doubles */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- (CLASS != FPP_REG ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) : 1)
-
-/* we don't define any special constant sizes so all should fail */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  0
-
-/* we don't define any special double sizes so all should fail */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
-
-
-/*
- * Describing Stack Layout
- */
-
-/* tahoe stack grows from high to low memory */
-
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if longjmp restores from saved registers
-   rather than from what setjmp saved.  */
-#define LONGJMP_RESTORE_FROM_STACK
-
-/* tahoe call frames grow from high to low memory on the stack */
-
-#define FRAME_GROWS_DOWNWARD
-
-/* the tahoe fp points to the *top* of the frame instead of the   */
-/* bottom, so we have to make this offset a constant large enough */
-/* to jump over the biggest frame possible.			  */
-
-#define STARTING_FRAME_OFFSET -52
-
-/* tahoe always pushes 4 bytes unless it's a double in which case */
-/* it pushes a full 8 bytes.					  */
-
-#define PUSH_ROUNDING(BYTES) (BYTES <= 4 ? 4 : 8)
-
-/* the first parameter in a function is at the fp + 4 */
-
-#define FIRST_PARM_OFFSET(FNDECL) 4
-
-/* the tahoe return function takes care of everything on the stack */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)
-
-/* function values for all types are returned in register 0 */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
-
-/* library routines also return things in reg 0 */
-
-#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, 0)
-
-/* Tahoe doesn't return structures in a reentrant way */
-
-#define PCC_STATIC_STRUCT_RETURN
-
-/* we only return values from a function in reg 0 */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-/* we never pass args through a register */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
-
-/* int is fine to hold the argument summary in FUNCTION_ARG */
-
-#define CUMULATIVE_ARGS int
-
-/* we just set CUM to 0 before the FUNCTION_ARG call. No matter what */
-/* we make it, FUNCTION_ARG will return 0 anyway		     */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM) = 0)
-
-/* all modes push their size rounded to the nearest word boundary */
-/* except block which is the size of the block rounded up	  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM) += ((MODE) != BLKmode			\
-	    ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
-	    : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-/* this is always false since we never pass params in regs */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-
-/* this code calculates the register entry mask and sets up    */
-/* the stack pointer for the function. The stack is set down   */
-/* far enough from the fp to jump over any push regs and local */
-/* vars. This is a problem since the tahoe has the fp pointing */
-/* to the top of the frame and the compiler must know the off- */
-/* set off the fp to the local vars.			       */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)     \
-{ register int regno;						\
-  register int mask = 0;					\
-  extern char call_used_regs[];					\
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER-1; regno++)	\
-    if (regs_ever_live[regno] && !call_used_regs[regno])	\
-       mask |= 1 << regno;					\
-  fprintf (FILE, "\t.word 0x%x\n", mask);			\
-  if (SIZE != 0) fprintf (FILE, "\tsubl3 $%d,fp,sp\n", (SIZE) - STARTING_FRAME_OFFSET); }
-
-/* Zero out global variable in case it was used in this function.  */
-#define FUNCTION_EPILOGUE(FILE, SIZE)	\
-{ extern rtx tahoe_reg_conversion_loc;				\
-  tahoe_reg_conversion_loc = 0;					\
-}
-
-#ifdef HCX_UX
-
-/* to call the profiler, the address of the counter var is placed */
-/* on the stack and then passed into mcount this way			  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   fprintf (FILE, "\tpushal LP%d\n\tcallf $8,mcount\n", (LABELNO));
-
-#else
-
-/* to call the profiler, push the variable value onto the stack */
-/* and call mcount like a regular function.			*/
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   fprintf (FILE, "\tpushl $LP%d\n\tcallf $8,mcount\n", (LABELNO));
-
-#endif
-
-/* all stack handling at the end of a function is handled by the */
-/* return command.						 */
-
-#define EXIT_IGNORE_STACK 1
-
-/*
- * Library Subroutine Names
- */
-
-/* udiv is a valid C library routine in libc.a, so we call that */
-
-#define UDIVSI3_LIBCALL "*udiv"
-
-/* urem is a valid C library routine in libc.a, so we call that */
-/* but not so on hcx/ux */
-
-#ifdef HCX_UX
-#undef UMODSI3_LIBCALL
-#else
-#define UMODSI3_LIBCALL "*urem"
-#endif
-
-
-/*
- * Addressing Modes
- */
-
-/* constant addresses can be treated exactly the same as normal constants */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* we can have as many as two regs in any given address */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* The following is all the code for GO_IF_LEGITIMATE_ADDRESS */
-/* most of this taken directly from the vax tm file since the */
-/* tahoe and vax addressing modes are nearly identical.	      */
-
-/* Is x an indirectable address? */
-
-#define INDIRECTABLE_ADDRESS_P(X)  \
-  (CONSTANT_ADDRESS_P (X)						\
-   || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
-   || (GET_CODE (X) == PLUS						\
-       && GET_CODE (XEXP (X, 0)) == REG					\
-       && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
-       && CONSTANT_ADDRESS_P (XEXP (X, 1))))
-
-/* If x is a non-indexed-address, go to ADDR. */
-
-#define GO_IF_NONINDEXED_ADDRESS(X, ADDR)  \
-{ register rtx xfoob = (X);						\
-  if (GET_CODE (xfoob) == REG) goto ADDR;				\
-  if (INDIRECTABLE_ADDRESS_P (xfoob)) goto ADDR;			\
-  xfoob = XEXP (X, 0);							\
-  if (GET_CODE (X) == MEM && INDIRECTABLE_ADDRESS_P (xfoob))		\
-    goto ADDR;								\
-  if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC)		\
-      && GET_CODE (xfoob) == REG && REGNO (xfoob) == 14)		\
-    goto ADDR; }
-
-/* Is PROD an index term in mode MODE. */
-
-#define INDEX_TERM_P(PROD, MODE)   \
-(GET_MODE_SIZE (MODE) == 1						\
- ? (GET_CODE (PROD) == REG && REG_OK_FOR_BASE_P (PROD))			\
- : (GET_CODE (PROD) == MULT						\
-    &&									\
-    (xfoo0 = XEXP (PROD, 0), xfoo1 = XEXP (PROD, 1),			\
-     ((GET_CODE (xfoo0) == CONST_INT					\
-       && INTVAL (xfoo0) == GET_MODE_SIZE (MODE)			\
-       && GET_CODE (xfoo1) == REG					\
-       && REG_OK_FOR_INDEX_P (xfoo1))					\
-      ||								\
-      (GET_CODE (xfoo1) == CONST_INT					\
-       && INTVAL (xfoo1) == GET_MODE_SIZE (MODE)			\
-       && GET_CODE (xfoo0) == REG					\
-       && REG_OK_FOR_INDEX_P (xfoo0))))))
-
-/* Is the addition to the index a reg? */
-
-#define GO_IF_REG_PLUS_INDEX(X, MODE, ADDR)	\
-{ register rtx xfooa;							\
-  if (GET_CODE (X) == PLUS)						\
-    { if (GET_CODE (XEXP (X, 0)) == REG					\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
-	  && (xfooa = XEXP (X, 1),					\
-	      INDEX_TERM_P (xfooa, MODE)))				\
-	goto ADDR;							\
-      if (GET_CODE (XEXP (X, 1)) == REG					\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 1))				\
-	  && (xfooa = XEXP (X, 0),					\
-	      INDEX_TERM_P (xfooa, MODE)))				\
-	goto ADDR; } }
-
-/* Is the rtx X a valid memory address for operand of mode MODE? */
-/* If it is, go to ADDR */
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
-{ register rtx xfoo, xfoo0, xfoo1;					\
-  GO_IF_NONINDEXED_ADDRESS (X, ADDR);					\
-  if (GET_CODE (X) == PLUS)						\
-    { xfoo = XEXP (X, 0);						\
-      if (INDEX_TERM_P (xfoo, MODE))					\
-	{ GO_IF_NONINDEXED_ADDRESS (XEXP (X, 1), ADDR); }		\
-      xfoo = XEXP (X, 1);						\
-      if (INDEX_TERM_P (xfoo, MODE))					\
-	{ GO_IF_NONINDEXED_ADDRESS (XEXP (X, 0), ADDR); }		\
-      if (CONSTANT_ADDRESS_P (XEXP (X, 0)))				\
-	{ if (GET_CODE (XEXP (X, 1)) == REG				\
-	      && REG_OK_FOR_BASE_P (XEXP (X, 1)))			\
-	    goto ADDR;							\
-	  GO_IF_REG_PLUS_INDEX (XEXP (X, 1), MODE, ADDR); }		\
-      if (CONSTANT_ADDRESS_P (XEXP (X, 1)))				\
-	{ if (GET_CODE (XEXP (X, 0)) == REG				\
-	      && REG_OK_FOR_BASE_P (XEXP (X, 0)))			\
-	    goto ADDR;							\
-	  GO_IF_REG_PLUS_INDEX (XEXP (X, 0), MODE, ADDR); } } }
-
-/* Register 16 can never be used for index or base */
-
-#ifndef REG_OK_STRICT
-#define REG_OK_FOR_INDEX_P(X) (REGNO(X) != 16)
-#define REG_OK_FOR_BASE_P(X) (REGNO(X) != 16)
-#else
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-#endif
-
-/* Addressing is too simple to allow optimizing here */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)  {}
-
-/* Post_inc and pre_dec always adds 4 */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
- { if (GET_CODE(ADDR) == POST_INC || GET_CODE(ADDR) == PRE_DEC)		\
-       goto LABEL;							\
-   if (GET_CODE (ADDR) == PLUS)						\
-     { if (CONSTANT_ADDRESS_P (XEXP (ADDR, 0))				\
-	   && GET_CODE (XEXP (ADDR, 1)) == REG);			\
-       else if (CONSTANT_ADDRESS_P (XEXP (ADDR, 1))			\
-		&& GET_CODE (XEXP (ADDR, 0)) == REG);			\
-       else goto LABEL; }}
-
-/* Double's are not legitimate as immediate operands */
-
-#define LEGITIMATE_CONSTANT_P(X) \
-  (GET_CODE (X) != CONST_DOUBLE)
-
-
-/*
- * Miscellaneous Parameters
- */
-
-/* the elements in the case jump table are all words */
-
-#define CASE_VECTOR_MODE HImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE 1
-
-/* tahoe case instructions just fall through to the next instruction */
-/* if not satisfied. It doesn't support a default action	     */
-
-#define CASE_DROPS_THROUGH
-
-/* the standard answer is given here and work ok */
-
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* in a general div case, it's easiest to use TRUNC_DIV_EXPR */
-
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* the standard seems to be leaving char's as signed so we left it */
-/* this way even though we think they should be unsigned!	   */
-
-#define DEFAULT_SIGNED_CHAR 1
-
-/* the most we can move without cutting down speed is 4 bytes */
-
-#define MOVE_MAX 4
-
-/* our int is 32 bits */
-
-#define INT_TYPE_SIZE 32
-
-/* byte access isn't really slower than anything else */
-
-#define SLOW_BYTE_ACCESS 0
-
-/* zero extension is more than one instruction so try to avoid it */
-
-#define SLOW_ZERO_EXTEND
-
-/* any bits higher than the low 4 are ignored in the shift count */
-/* so don't bother zero extending or sign extending them         */
-
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* we don't need to officially convert from one fixed type to another */
-/* in order to use it as that type. We can just assume it's the same  */
-
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* pass chars as ints */
-
-#define PROMOTE_PROTOTYPES
-
-/* pointers can be represented by an si mode expression */
-
-#define Pmode SImode
-
-/* function addresses are made by specifying a byte address */
-
-#define FUNCTION_MODE QImode
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   On the tahoe a call with a constant address is much faster than one with a
-   register. */
-
-#define NO_FUNCTION_CSE
-
-/* specify the costs of various sorts of constants,
-   and also indicate that multiplication is cheap on this machine.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    /* Constant zero is super cheap due to clr instruction.  */	\
-    if (RTX == const0_rtx) return 0;				\
-    if ((unsigned) INTVAL (RTX) < 077) return 1;		\
-    if (INTVAL (RTX) <= 127 && INTVAL (RTX) >= -128) return 2;	\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 3;							\
-  case CONST_DOUBLE:						\
-    return 5;							\
-  case MULT:							\
-    total = 2;
-
-
-/*
- * Condition Code Information
- */
-
-/* Nonzero if the results of the previous comparison are
-   in the floating point condition code register.  */
-
-#define CC_UNCHANGED 04000
-
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-{ if (cc_status.flags & CC_UNCHANGED)				\
-    /* Happens for cvtld and a few other insns.  */		\
-    cc_status.flags &= ~CC_UNCHANGED;				\
-  else if (GET_CODE (EXP) == SET)				\
-    { if (GET_CODE (SET_SRC (EXP)) == CALL)			\
-	CC_STATUS_INIT;						\
-      else if (GET_CODE (SET_DEST (EXP)) != PC)			\
-	{ cc_status.flags = 0;					\
-	  cc_status.value1 = SET_DEST (EXP);			\
-	  cc_status.value2 = SET_SRC (EXP); } }			\
-  else if (GET_CODE (EXP) == PARALLEL				\
-	   && GET_CODE (XVECEXP (EXP, 0, 0)) == SET		\
-	   && GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) != PC)	\
-    { cc_status.flags = 0;					\
-      cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0));	\
-      cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0)); }	\
-  /* PARALLELs whose first element sets the PC are aob, sob insns.	\
-     They do change the cc's.  So drop through and forget the cc's.  */ \
-  else CC_STATUS_INIT;						\
-  if (cc_status.value1 && GET_CODE (cc_status.value1) == REG	\
-      && cc_status.value2					\
-      && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))	\
-    cc_status.value2 = 0;					\
-  if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM	\
-      && cc_status.value2					\
-      && GET_CODE (cc_status.value2) == MEM)			\
-    cc_status.value2 = 0; }
-/* Actual condition, one line up, should be that value2's address
-   depends on value1, but that is too much of a pain.  */
-
-
-/*
- * Output of Assembler Code
- */
-
-/* print which tahoe version compiled this code and print a directive */
-/* to the gnu assembler to say that the following is normal assembly  */
-
-#ifdef HCX_UX
-#define ASM_FILE_START(FILE)		\
-{ fprintf (FILE, "#gcc hcx 1.0\n\n");	\
-  output_file_directive ((FILE), main_input_filename);} while (0)
-#else
-#define ASM_FILE_START(FILE) fprintf (FILE, "#gcc tahoe 1.0\n#NO_APP\n");
-#endif
-
-/* the instruction that turns on the APP for the gnu assembler */
-
-#define ASM_APP_ON "#APP\n"
-
-/* the instruction that turns off the APP for the gnu assembler */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* what to output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* what to output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* this is what we call each of the regs. notice that the FPP reg is   */
-/* called "ac". This should never get used due to the way we've set    */
-/* up FPP instructions in the md file. But we call it "ac" here to     */
-/* fill the list.						       */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", \
- "r9", "r10", "r11", "r12", "fp", "sp", "pc", "ac"}
-
-#ifdef HCX_UX
-/* allow generation of sdb info in the assembly */
-#define SDB_DEBUGGING_INFO
-#else
-/* allow generation of dbx info in the assembly */
-
-#define DBX_DEBUGGING_INFO
-
-/* our dbx doesn't support this */
-
-#define DBX_NO_XREFS
-
-/* we don't want symbols broken up */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* this'll really never be used, but we'll leave it at this */
-
-#define DBX_CONTIN_CHAR '?'
-
-#endif /* HCX_UX */
-
-/* registers are called the same thing in dbx anything else */
-/* This is necessary even if we generate SDB output */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* labels are the label followed by a colon and a newline */
-/* must be a statement, so surround it in a null loop     */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* use the .globl directive to make labels global for the linker */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* use the standard format for printing internal labels */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* a * is used for label indirection in unix assembly */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* outputting a double is easy cause we only have one kind */
-
-#ifdef HCX_UX
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-  fprintf (FILE, "\t.double 0d%.20e\n", (VALUE))
-#else
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-{							\
-  union { int i[2]; double d;} temp;			\
-  temp.d = (VALUE);					\
-  if (TARGET_HEX_FLOAT)					\
-    fprintf ((FILE), "\t.long 0x%x,0x%x  # %.20e\n",	\
-	     temp.i[0], temp.i[1], temp.d);		\
-  else							\
-    fprintf (FILE, "\t.dfloat 0d%.20e\n", temp.d);	\
-}
-#endif
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#ifdef HCX_UX
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-  fprintf (FILE, "\t.float 0f%.20e\n", (VALUE))
-#else
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-{							\
-  union { int i; float f;} temp;			\
-  temp.f = (float) (VALUE);				\
-  if (TARGET_HEX_FLOAT)					\
-    fprintf ((FILE), "\t.long 0x%x  # %.20e\n",		\
-	     temp.i, temp.f);				\
-  else							\
-    fprintf (FILE, "\t.float 0f%.20e\n", temp.f);	\
-}
-#endif
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#ifdef HCX_UX
-/* This is how to output an assembler line for an ASCII string.  */
-
-#define ASM_OUTPUT_ASCII(FILE, p, size)  		\
-do {	register int i;					\
-	  fprintf ((FILE), "\t.ascii \""); 		\
-	  for (i = 0; i < (size); i++) 			\
-	    {						\
-	      register int c = (p)[i];			\
-	      if (c == '\'' || c == '\\')		\
-		putc ('\\', (FILE));			\
-	      if (c >= ' ' && c < 0177 && c != '\"')	\
-		putc (c, (FILE));			\
-	      else					\
-		{					\
-		  fprintf ((FILE), "\\%03o", c);	\
-		}					\
-	    }						\
-	  fprintf ((FILE), "\"\n"); } while (0)
-#endif
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* this is the insn to push a register onto the stack */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)	\
-  fprintf (FILE, "\tpushl %s\n", reg_names[REGNO])
-
-/* this is the insn to pop a register from the stack */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)	\
-  fprintf (FILE, "\tmovl (sp)+,%s\n", reg_names[REGNO])
-
-/* this is required even thought tahoe doesn't support it */
-/* cause the C code expects it to be defined		  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.long L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#ifdef HCX_UX
-#define CASE_ALIGNMENT 2
-#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
-    if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG))
-#else
-#define CASE_ALIGNMENT 1
-#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
-  LOG ? fprintf (FILE, "\t.align %d\n", (LOG)) : 0
-#endif
-
-/* This is how to skip over some space */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %u\n", (SIZE))
-
-/* This defines common variables across files */
-
-#ifdef HCX_UX
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (SIZE)))
-#else
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-#endif
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#ifdef HCX_UX
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs ("\t.bss ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u,4\n", (SIZE),(ROUNDED)))
-#else
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-#endif
-
-/* code to generate a label */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print an instruction operand X on file FILE.
-   CODE is the code from the %-spec that requested printing this operand;
-   if `%z3' was used to print operand 3, then CODE is 'z'.
-   On the Vax, the only code used is `#', indicating that either
-   `d' or `g' should be printed, depending on whether we're using dfloat
-   or gfloat.  */
-/* Print an operand.  Some difference from the vax code,
-   since the tahoe can't support immediate floats and doubles.
-
-   %@ means print the proper alignment operand for aligning after a casesi.
-   This depends on the assembler syntax.
-   This is 1 for our assembler, since .align is logarithmic.
-
-   %s means the number given is supposed to be a shift value, but on
-   the tahoe it should be converted to a number that can be used as a
-   multiplicative constant (cause multiplication is a whole lot faster
-   than shifting). So make the number 2^n instead. */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)				\
-  ((CODE) == '@')
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ if (CODE == '@')							\
-    putc ('0' + CASE_ALIGNMENT, FILE);					\
-  else if (CODE == 's')							\
-    fprintf (FILE, "$%d", 1 << INTVAL(X));				\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else { putc ('$', FILE); output_addr_const (FILE, X); }}
-
-/* When the operand is an address, call print_operand_address to */
-/* do the work from output-tahoe.c.				 */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
- print_operand_address (FILE, ADDR)
-
-/* This is for G++ */
-
-#define CRT0_DUMMIES
-#define DOT_GLOBAL_START
-#ifdef HCX_UX
-#define NO_GNU_LD /* because of COFF format */
-#define LINK_SPEC "-L/usr/staff/lib"
-#endif
diff --git a/gcc/config/tahoe/tahoe.md b/gcc/config/tahoe/tahoe.md
deleted file mode 100755
index 021c1b0..0000000
--- a/gcc/config/tahoe/tahoe.md
+++ /dev/null
@@ -1,2113 +0,0 @@
-;; Machine description for GNU compiler, Tahoe version
-;; Copyright (C) 1989, 1994, 1996, 1997 Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-; File: tahoe.md
-;
-; Original port made at the University of Buffalo by Devon Bowen,
-; Dale Wiles and Kevin Zachmann.
-;
-; Piet van Oostrum (piet@cs.ruu.nl) made changes for HCX/UX, fixed
-; some bugs and made some improvements (hopefully).
-;
-; Mail bugs reports or fixes to:	gcc@cs.buffalo.edu
-
-
-; movdi must call the output_move_double routine to move it around since
-; the tahoe doesn't efficiently support 8 bit moves.
-
-(define_insn "movdi"
-  [(set (match_operand:DI 0 "general_operand" "=g")
-	(match_operand:DI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return output_move_double (operands);
-}")
-
-
-; the trick in the movsi is accessing the contents of the sp register.  The
-; tahoe doesn't allow you to access it directly so you have to access the
-; address of the top of the stack instead.
-
-(define_insn "movsi"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operand:SI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-   rtx link;
-   if (operands[1] == const1_rtx
-      && (link = find_reg_note (insn, REG_WAS_0, 0))
-      && ! INSN_DELETED_P (XEXP (link, 0))
-      && GET_CODE (XEXP (link, 0)) != NOTE
-      && no_labels_between_p (XEXP (link, 0), insn)
-      /* Make sure the reg hasn't been clobbered.  */
-      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
-    return \"incl %0\";
-   if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
-    {
-      if (push_operand (operands[0], SImode))
-	return \"pushab %a1\";
-      return \"movab %a1,%0\";
-    }
-  if (operands[1] == const0_rtx)
-    return \"clrl %0\";
-  if (push_operand (operands[0], SImode))
-    return \"pushl %1\";
-  if (GET_CODE(operands[1]) == REG && REGNO(operands[1]) == 14)
-    return \"moval (sp),%0\";
-  return \"movl %1,%0\";
-}")
-
-
-(define_insn "movhi"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(match_operand:HI 1 "general_operand" "g"))]
-  ""
-  "*
-{
- rtx link;
- if (operands[1] == const1_rtx
-     && (link = find_reg_note (insn, REG_WAS_0, 0))
-     && ! INSN_DELETED_P (XEXP (link, 0))
-     && GET_CODE (XEXP (link, 0)) != NOTE
-     && no_labels_between_p (XEXP (link, 0), insn)
-     /* Make sure the reg hasn't been clobbered.  */
-     && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
-    return \"incw %0\";
-  if (operands[1] == const0_rtx)
-    return \"clrw %0\";
-  return \"movw %1,%0\";
-}")
-
-
-(define_insn "movqi"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(match_operand:QI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  if (operands[1] == const0_rtx)
-    return \"clrb %0\";
-  return \"movb %1,%0\";
-}")
-
-
-; movsf has three cases since they can move from one place to another
-; or to/from the fpp and since different instructions are needed for
-; each case.  The fpp related instructions don't set the flags properly.
-
-(define_insn "movsf"
-  [(set (match_operand:SF 0 "general_operand" "=g,=a,=g")
-	(match_operand:SF 1 "general_operand" "g,g,a"))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  switch (which_alternative)
-    {
-    case 0: return \"movl %1,%0\";
-    case 1: return \"ldf %1\";
-    case 2: return \"stf %0\";
-   }
-}")
-
-
-; movdf has a number of different cases.  If it's going to or from
-; the fpp, use the special instructions to do it.  If not, use the
-; output_move_double function.
-
-(define_insn "movdf"
-  [(set (match_operand:DF 0 "general_operand" "=a,=g,?=g")
-	(match_operand:DF 1 "general_operand" "g,a,g"))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  switch (which_alternative)
-    {
-    case 0:
-      return \"ldd %1\";
-    case 1:
-      if (push_operand (operands[0], DFmode))
-        return \"pushd\";
-      else
-        return \"std %0\";
-    case 2:
-      return output_move_double (operands);
-   }
-}")
-
-
-;========================================================================
-; The tahoe has the following semantics for byte (and similar for word)
-; operands: if the operand is a register or immediate, it takes the full 32
-; bit operand, if the operand is memory, it sign-extends the byte.  The
-; operation is performed on the 32 bit values.  If the destination is a
-; register, the full 32 bit result is stored, if the destination is memory,
-; of course only the low part is stored.  The condition code is based on the
-; 32 bit operation.  Only on the movz instructions the byte from memory is
-; zero-extended rather than sign-extended.
-
-; This means that for arithmetic instructions we can use addb etc.  to
-; perform a long add from a signed byte from memory to a register.  Of
-; course this would also work for logical operations, but that doesn't seem
-; very useful.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))
-		 (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))]
-  ""
-  "addb3 %1,%2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_operand:SI 1 "nonmemory_operand" "%ri")
-		 (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"addb2 %2,%0\";
-  return \"addb3 %1,%2,%0\";
-}")
-
-; We can also consider the result to be a half integer
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(plus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))
-		 (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))]
-  ""
-  "addb3 %1,%2,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(plus:HI (match_operand:HI 1 "nonmemory_operand" "%ri")
-		 (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"addb2 %2,%0\";
-  return \"addb3 %1,%2,%0\";
-}")
-
-; The same applies to words (HI)
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
-		 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))]
-  ""
-  "addw3 %1,%2,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(plus:SI (match_operand:SI 1 "nonmemory_operand" "%ri")
-		 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"addw2 %2,%0\";
-  return \"addw3 %1,%2,%0\";
-}")
-
-; ======================= Now for subtract ==============================
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))
-		  (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))]
-  ""
-  "subb3 %2,%1,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "nonmemory_operand" "ri")
-		  (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"subb2 %2,%0\";
-  return \"subb3 %2,%1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))
-		  (match_operand:SI 2 "nonmemory_operand" "ri")))]
-  ""
-  "subb3 %2,%1,%0")
-
-; We can also consider the result to be a half integer
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(minus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))
-		 (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))]
-  ""
-  "subb3 %2,%1,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(minus:HI (match_operand:HI 1 "nonmemory_operand" "%ri")
-		 (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"subb2 %2,%0\";
-  return \"subb3 %2,%1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(minus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))
-		 (match_operand:HI 2 "nonmemory_operand" "ri")))]
-  ""
-  "subb3 %2,%1,%0")
-
-; The same applies to words (HI)
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
-		  (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))]
-  ""
-  "subw3 %2,%1,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "nonmemory_operand" "ri")
-		 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"subw2 %2,%0\";
-  return \"subw3 %2,%1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
-		  (match_operand:SI 2 "nonmemory_operand" "ri")))]
-  ""
-  "subw3 %2,%1,%0")
-
-; ======================= Now for neg ==============================
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
-  ""
-  "mnegb %1,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(neg:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))))]
-  ""
-  "mnegb %1,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
-  ""
-  "mnegw %1,%0")
-
-;========================================================================
-
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(plus:SI (match_operand:SI 1 "general_operand" "g")
-		 (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      if (operands[2] == const1_rtx)
-	return \"incl %0\";
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && INTVAL (operands[2]) == -1)
-	return \"decl %0\";
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && (unsigned) (- INTVAL (operands[2])) < 64)
-	return \"subl2 $%n2,%0\";
-      return \"addl2 %2,%0\";
-    }
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"addl2 %1,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT
-      && GET_CODE (operands[1]) == REG)
-    {
-      if (push_operand (operands[0], SImode))
-        return \"pushab %c2(%1)\";
-      return \"movab %c2(%1),%0\";
-    }
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned) (- INTVAL (operands[2])) < 64)
-    return \"subl3 $%n2,%1,%0\";
-  return \"addl3 %1,%2,%0\";
-}")
-
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(plus:HI (match_operand:HI 1 "general_operand" "g")
-		 (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      if (operands[2] == const1_rtx)
-	return \"incw %0\";
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && INTVAL (operands[2]) == -1)
-	return \"decw %0\";
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && (unsigned) (- INTVAL (operands[2])) < 64)
-	return \"subw2 $%n2,%0\";
-      return \"addw2 %2,%0\";
-    }
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"addw2 %1,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned) (- INTVAL (operands[2])) < 64)
-    return \"subw3 $%n2,%1,%0\";
-  return \"addw3 %1,%2,%0\";
-}")
-
-
-(define_insn "addqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(plus:QI (match_operand:QI 1 "general_operand" "g")
-		 (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      if (operands[2] == const1_rtx)
-	return \"incb %0\";
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && INTVAL (operands[2]) == -1)
-	return \"decb %0\";
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && (unsigned) (- INTVAL (operands[2])) < 64)
-	return \"subb2 $%n2,%0\";
-      return \"addb2 %2,%0\";
-    }
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"addb2 %1,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned) (- INTVAL (operands[2])) < 64)
-    return \"subb3 $%n2,%1,%0\";
-  return \"addb3 %1,%2,%0\";
-}")
-
-; addsf3 can only add into the fpp register since the fpp is treated
-; as a separate unit in the machine.  It also doesn't set the flags at
-; all.
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(plus:SF (match_operand:SF 1 "register_operand" "%0")
-		 (match_operand:SF 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"addf %2\";
-}")
-
-
-; adddf3 can only add into the fpp reg since the fpp is treated as a
-; separate entity.  Doubles can only be read from a register or memory
-; since a double is not an immediate mode.  Flags are not set by this
-; instruction.
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=a")
-	(plus:DF (match_operand:DF 1 "register_operand" "%0")
-		 (match_operand:DF 2 "general_operand" "rm")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"addd %2\";
-}")
-
-
-; Subtraction from the sp (needed by the built in alloc function) needs
-; to be different since the sp cannot be directly read on the tahoe.
-; If it's a simple constant, you just use displacement.  Otherwise, you
-; push the sp, and then do the subtraction off the stack.
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(minus:SI (match_operand:SI 1 "general_operand" "g")
-		  (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      if (operands[2] == const1_rtx)
-	return \"decl %0\";
-      if (GET_CODE(operands[0]) == REG && REGNO(operands[0]) == 14)
-        {
-	  if (GET_CODE(operands[2]) == CONST_INT)
-	    return \"movab %n2(sp),sp\";
-	  else
-	    return \"pushab (sp)\;subl3 %2,(sp),sp\";
-	}
-      return \"subl2 %2,%0\";
-    }
-  if (rtx_equal_p (operands[1], operands[2]))
-    return \"clrl %0\";
-  return \"subl3 %2,%1,%0\";
-}")
-
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(minus:HI (match_operand:HI 1 "general_operand" "g")
-		  (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      if (operands[2] == const1_rtx)
-	return \"decw %0\";
-      return \"subw2 %2,%0\";
-    }
-  if (rtx_equal_p (operands[1], operands[2]))
-    return \"clrw %0\";
-  return \"subw3 %2,%1,%0\";
-}")
-
-
-(define_insn "subqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(minus:QI (match_operand:QI 1 "general_operand" "g")
-		  (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      if (operands[2] == const1_rtx)
-	return \"decb %0\";
-      return \"subb2 %2,%0\";
-    }
-  if (rtx_equal_p (operands[1], operands[2]))
-    return \"clrb %0\";
-  return \"subb3 %2,%1,%0\";
-}")
-
-
-; subsf3 can only subtract into the fpp accumulator due to the way
-; the fpp reg is limited by the instruction set.  This also doesn't
-; bother setting up flags.
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(minus:SF (match_operand:SF 1 "register_operand" "0")
-		  (match_operand:SF 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"subf %2\";
-}")
-
-
-; subdf3 is set up to subtract into the fpp reg due to limitations
-; of the fpp instruction set.  Doubles can not be immediate.  This
-; instruction does not set the flags.
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=a")
-	(minus:DF (match_operand:DF 1 "register_operand" "0")
-		  (match_operand:DF 2 "general_operand" "rm")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"subd %2\";
-}")
-
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(mult:SI (match_operand:SI 1 "general_operand" "g")
-		 (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"mull2 %2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"mull2 %1,%0\";
-  return \"mull3 %1,%2,%0\";
-}")
-
-
-; mulsf3 can only multiply into the fpp accumulator due to limitations
-; of the fpp.  It also does not set the condition codes properly.
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(mult:SF (match_operand:SF 1 "register_operand" "%0")
-		 (match_operand:SF 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"mulf %2\";
-}")
-
-
-; muldf3 can only multiply into the fpp reg since the fpp is limited
-; from the rest.  Doubles may not be immediate mode.  This does not set
-; the flags like gcc would expect.
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=a")
-	(mult:DF (match_operand:DF 1 "register_operand" "%0")
-		 (match_operand:DF 2 "general_operand" "rm")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"muld %2\";
-}")
-
-
-
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(div:SI (match_operand:SI 1 "general_operand" "g")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[1], operands[2]))
-    return \"movl $1,%0\";
-  if (operands[1] == const0_rtx)
-    return \"clrl %0\";
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) == -1)
-    return \"mnegl %1,%0\";
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"divl2 %2,%0\";
-  return \"divl3 %2,%1,%0\";
-}")
-
-
-; divsf3 must divide into the fpp accumulator.  Flags are not set by
-; this instruction, so they are cleared.
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(div:SF (match_operand:SF 1 "register_operand" "0")
-		(match_operand:SF 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"divf %2\";
-}")
-
-
-; divdf3 also must divide into the fpp reg so optimization isn't
-; possible.  Note that doubles cannot be immediate.  The flags here
-; are not set correctly so they must be ignored.
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=a")
-	(div:DF (match_operand:DF 1 "register_operand" "0")
-		(match_operand:DF 2 "general_operand" "rm")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"divd %2\";
-}")
-
-
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(and:SI (match_operand:SI 1 "general_operand" "g")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"andl2 %2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"andl2 %1,%0\";
-  return \"andl3 %2,%1,%0\";
-}")
-
-
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(and:HI (match_operand:HI 1 "general_operand" "g")
-		(match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"andw2 %2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"andw2 %1,%0\";
-  return \"andw3 %2,%1,%0\";
-}")
-
-
-(define_insn "andqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(and:QI (match_operand:QI 1 "general_operand" "g")
-		(match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"andb2 %2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"andb2 %1,%0\";
-  return \"andb3 %2,%1,%0\";
-}")
-
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(ior:SI (match_operand:SI 1 "general_operand" "g")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"orl2 %2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"orl2 %1,%0\";
-  return \"orl3 %2,%1,%0\";
-}")
-
-
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(ior:HI (match_operand:HI 1 "general_operand" "g")
-		(match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"orw2 %2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"orw2 %1,%0\";
-  return \"orw3 %2,%1,%0\";
-}")
-
-
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(ior:QI (match_operand:QI 1 "general_operand" "g")
-		(match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"orb2 %2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"orb2 %1,%0\";
-  return \"orb3 %2,%1,%0\";
-}")
-
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(xor:SI (match_operand:SI 1 "general_operand" "g")
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"xorl2 %2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"xorl2 %1,%0\";
-  return \"xorl3 %2,%1,%0\";
-}")
-
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(xor:HI (match_operand:HI 1 "general_operand" "g")
-		(match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"xorw2 %2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"xorw2 %1,%0\";
-  return \"xorw3 %2,%1,%0\";
-}")
-
-
-(define_insn "xorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(xor:QI (match_operand:QI 1 "general_operand" "g")
-		(match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"xorb2 %2,%0\";
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"xorb2 %1,%0\";
-  return \"xorb3 %2,%1,%0\";
-}")
-
-
-; shifts on the tahoe are expensive, try some magic first...
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(ashift:SI (match_operand:SI 1 "general_operand" "g")
-		   (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE(operands[2]) == REG)
-      return \"mull3 ___shtab[%2],%1,%0\";
-  /* if (GET_CODE(operands[2]) == REG)
-    if (rtx_equal_p (operands[0], operands[1]))
-      return \"mull2 ___shtab[%2],%1\";
-    else
-      return \"mull3 ___shtab[%2],%1,%0\"; */
-  if (GET_CODE(operands[1]) == REG)
-    {
-      if (operands[2] == const1_rtx)
-	{
-	  CC_STATUS_INIT;
-	  return \"movaw 0[%1],%0\";
-	}
-      if (GET_CODE(operands[2]) == CONST_INT && INTVAL(operands[2]) == 2)
-	{
-	  CC_STATUS_INIT;
-	  return \"moval 0[%1],%0\";
-	}
-    }
-  if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) == 1)
-    return \"shal %2,%1,%0\";
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"mull2 %s2,%1\";
-  else
-    return \"mull3 %s2,%1,%0\";
-}")
-
-
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
-		   (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "shar %2,%1,%0")
-
-
-; shifts are very expensive, try some magic first...
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
-		   (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "shrl %2,%1,%0")
-
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(neg:SI (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "mnegl %1,%0")
-
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(neg:HI (match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "mnegw %1,%0")
-
-
-(define_insn "negqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(neg:QI (match_operand:QI 1 "general_operand" "g")))]
-  ""
-  "mnegb %1,%0")
-
-
-; negsf2 can only negate the value already in the fpp accumulator.
-; The value remains in the fpp accumulator.  No flags are set.
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=a,=a")
-	(neg:SF (match_operand:SF 1 "register_operand" "a,g")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  switch (which_alternative)
-    {
-    case 0: return \"negf\";
-    case 1: return \"lnf %1\";
-    }
-}")
-
-
-; negdf2 can only negate the value already in the fpp accumulator.
-; The value remains in the fpp accumulator.  No flags are set.
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=a,=a")
-	(neg:DF (match_operand:DF 1 "register_operand" "a,g")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  switch (which_alternative)
-    {
-    case 0: return \"negd\";
-    case 1: return \"lnd %1\";
-    }
-}")
-
-
-; sqrtsf2 tahoe can calculate the square root of a float in the
-; fpp accumulator.  The answer remains in the fpp accumulator.  No
-; flags are set by this function.
-
-(define_insn "sqrtsf2"
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"sqrtf\";
-}")
-
-
-; ffssi2 tahoe instruction gives one less than gcc desired result for
-; any given input.  So the increment is necessary here.
-
-(define_insn "ffssi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(ffs:SI (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (push_operand(operands[0], SImode))
-    return \"ffs %1,%0\;incl (sp)\";
-  return \"ffs %1,%0\;incl %0\";
-}")
-
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(not:SI (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "mcoml %1,%0")
-
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(not:HI (match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "mcomw %1,%0")
-
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(not:QI (match_operand:QI 1 "general_operand" "g")))]
-  ""
-  "mcomb %1,%0")
-
-
-; cmpsi works fine, but due to microcode problems, the tahoe doesn't
-; properly compare hi's and qi's.  Leaving them out seems to be acceptable
-; to the compiler, so they were left out.  Compares of the stack are
-; possible, though.
-
-; There are optimized cases possible, however.  These follow first.
-
-(define_insn ""
-  [(set (cc0)
-	(compare (sign_extend:SI (match_operand:HI 0 "memory_operand" "m"))
-		 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
-  ""
-  "cmpw %0,%1")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonmemory_operand" "ri")
-		 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
-  ""
-  "cmpw %0,%1")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (sign_extend:SI (match_operand:HI 0 "memory_operand" "m"))
-		 (match_operand:SI 1 "nonmemory_operand" "ri")))]
-  ""
-  "cmpw %0,%1")
-
-; zero-extended compares give the same result as sign-extended compares, if
-; the compare is unsigned.  Just see: if both operands are <65536 they are the
-; same in both cases.  If both are >=65536 the you effectively compare x+D
-; with y+D, where D=2**32-2**16, so the result is the same.  if x<65536 and
-; y>=65536 then you compare x with y+D, and in both cases the result is x<y.
-
-(define_insn ""
-  [(set (cc0)
-	(compare (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
-		 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
-  "tahoe_cmp_check (insn, operands[0], 0)"
-  "cmpw %0,%1")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
-		 (match_operand:SI 1 "immediate_operand" "i")))]
-  "tahoe_cmp_check(insn, operands[1], 65535)"
-  "*
-{
-  if (INTVAL (operands[1]) > 32767)
-    operands[1] = GEN_INT (INTVAL (operands[1]) + 0xffff0000);
-  return \"cmpw %0,%1\";
-}")
-
-
-(define_insn ""
-  [(set (cc0)
-	(compare (sign_extend:SI (match_operand:QI 0 "memory_operand" "m"))
-		 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
-  ""
-  "cmpb %0,%1")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonmemory_operand" "ri")
-		 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
-  ""
-  "cmpb %0,%1")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (sign_extend:SI (match_operand:QI 0 "memory_operand" "m"))
-		 (match_operand:SI 1 "nonmemory_operand" "ri")))]
-  ""
-  "cmpb %0,%1")
-
-; zero-extended compares give the same result as sign-extended compares, if
-; the compare is unsigned.  Just see: if both operands are <128 they are the
-; same in both cases.  If both are >=128 the you effectively compare x+D
-; with y+D, where D=2**32-2**8, so the result is the same.  if x<128 and
-; y>=128 then you compare x with y+D, and in both cases the result is x<y.
-
-(define_insn ""
-  [(set (cc0)
-	(compare (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
-		 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
-  "tahoe_cmp_check (insn, operands[0], 0)"
-  "cmpb %0,%1")
-
-(define_insn ""
-  [(set (cc0)
-	(compare (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
-		 (match_operand:SI 1 "immediate_operand" "i")))]
-  "tahoe_cmp_check(insn, operands[1], 255)"
-  "*
-{
-  if (INTVAL (operands[1]) > 127)
-    operands[1] = GEN_INT (INTVAL (operands[1]) + 0xffffff00);
-  return \"cmpb %0,%1\";
-}")
-
-
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "g")
-	         (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "cmpl %0,%1")
-
-
-; cmpsf similar to vax, but first operand is expected to be in the
-; fpp accumulator.
-
-(define_insn "cmpsf"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "general_operand" "a,g")
-	       (match_operand:SF 1 "general_operand" "g,g")))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0: return \"cmpf %1\";
-    case 1: return \"cmpf2 %0,%1\";
-    }
-}")
-
-
-; cmpdf similar to vax, but first operand is expected to be in the
-; fpp accumulator.  Immediate doubles not allowed.
-
-(define_insn "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "general_operand" "a,rm")
-		 (match_operand:DF 1 "general_operand" "rm,rm")))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0: return \"cmpd %1\";
-    case 1: return \"cmpd2 %0,%1\";
-    }
-}")
-
-;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
-;; be folded while optimizing anyway.
-
-(define_insn "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "nonimmediate_operand" "g"))]
-  ""
-  "tstl %0")
-
-
-; small tests from memory are normal, but testing from registers doesn't
-; expand the data properly.  So test in this case does a convert and tests
-; the new register data from the stack.
-
-; First some special cases that do work
-
-
-(define_insn ""
-  [(set (cc0)
-	(sign_extend:SI (match_operand:HI 0 "memory_operand" "m")))]
-  ""
-  "tstw %0")
-
-(define_insn ""
-  [(set (cc0)
-	(zero_extend:SI (match_operand:HI 0 "memory_operand" "m")))]
-  "tahoe_cmp_check (insn, operands[0], 0)"
-  "tstw %0")
-
-
-(define_insn "tsthi"
-  [(set (cc0)
-	(match_operand:HI 0 "extensible_operand" "m,!r"))]
-  "GET_MODE (operands[0]) != VOIDmode"
-  "*
-{
-  rtx xoperands[2];
-  extern rtx tahoe_reg_conversion_loc;
-  switch (which_alternative)
-    {
-    case 0:
-      return \"tstw %0\";
-    case 1:
-      xoperands[0] = operands[0];
-      xoperands[1] = tahoe_reg_conversion_loc;
-      output_asm_insn (\"movl %0,%1\", xoperands);
-      xoperands[1] = plus_constant (XEXP (tahoe_reg_conversion_loc, 0), 2);
-      output_asm_insn (\"tstw %a1\", xoperands);
-      return \"\";
-    }
-}")
-
-
-(define_insn ""
-  [(set (cc0)
-	(sign_extend:SI (match_operand:QI 0 "memory_operand" "m")))]
-  ""
-  "tstb %0")
-
-(define_insn ""
-  [(set (cc0)
-	(zero_extend:SI (match_operand:QI 0 "memory_operand" "m")))]
-  "tahoe_cmp_check (insn, operands[0], 0)"
-  "tstb %0")
-
-
-(define_insn "tstqi"
-  [(set (cc0)
-	(match_operand:QI 0 "extensible_operand" "m,!r"))]
-  "GET_MODE (operands[0]) != VOIDmode"
-  "*
-{
-  rtx xoperands[2];
-  extern rtx tahoe_reg_conversion_loc;
-  switch (which_alternative)
-    {
-    case 0:
-      return \"tstb %0\";
-    case 1:
-      xoperands[0] = operands[0];
-      xoperands[1] = tahoe_reg_conversion_loc;
-      output_asm_insn (\"movl %0,%1\", xoperands);
-      xoperands[1] = plus_constant (XEXP (tahoe_reg_conversion_loc, 0), 3);
-      output_asm_insn (\"tstb %a1\", xoperands);
-      return \"\";
-    }
-}")
-
-; tstsf compares a given value to a value already in the fpp accumulator.
-; No flags are set by this so ignore them.
-
-(define_insn "tstsf"
-  [(set (cc0)
-	(match_operand:SF 0 "register_operand" "a"))]
-  ""
-  "tstf")
-
-
-; tstdf compares a given value to a value already in the fpp accumulator.
-; immediate doubles not allowed.  Flags are ignored after this.
-
-(define_insn "tstdf"
-  [(set (cc0)
-	(match_operand:DF 0 "register_operand" "a"))]
-  ""
-  "tstd")
-
-
-
-; movstrhi tahoe instruction does not load registers by itself like
-; the vax counterpart does.  registers 0-2 must be primed by hand.
-; we have loaded the registers in the order: dst, src, count.
-
-(define_insn "movstrhi"
-  [(set (match_operand:BLK 0 "general_operand" "p")
-	 (match_operand:BLK 1 "general_operand" "p"))
-   (use (match_operand:HI 2 "general_operand" "g"))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 1))
-   (clobber (reg:SI 2))]
-  ""
-  "movab %0,r1\;movab %1,r0\;movl %2,r2\;movblk")
-
-
-; floatsisf2 on tahoe converts the long from reg/mem into the fpp
-; accumulator.  There are no hi and qi counterparts.  Flags are not
-; set correctly here.
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(float:SF (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"cvlf %1\";
-}")
-
-
-; floatsidf2 on tahoe converts the long from reg/mem into the fpp
-; accumulator.  There are no hi and qi counterparts.  Flags are not
-; set correctly here.
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "register_operand" "=a")
-	(float:DF (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"cvld %1\";
-}")
-
-
-; fix_truncsfsi2 to convert a float to long, tahoe must have the float
-; in the fpp accumulator.  Flags are not set here.
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "a"))))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"cvfl %0\";
-}")
-
-
-; fix_truncsfsi2 to convert a double to long, tahoe must have the double
-; in the fpp accumulator.  Flags are not set here.
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a"))))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"cvdl %0\";
-}")
-
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(truncate:HI (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "cvtlw %1,%0")
-
-
-(define_insn "truncsiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(truncate:QI (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "cvtlb %1,%0")
-
-
-(define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(truncate:QI (match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "cvtwb %1,%0")
-
-
-; The fpp related instructions don't set flags, so ignore them
-; after this instruction.
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "register_operand" "=a")
-	(float_truncate:SF (match_operand:DF 1 "register_operand" "0")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"cvdf\";
-}")
-
-
-; This monster is to cover for the Tahoe's nasty habit of not extending
-; a number if the source is in a register.  (It just moves it!) Case 0 is
-; a normal extend from memory.  Case 1 does the extension from the top of
-; the stack.  Extension from the stack doesn't set the flags right since
-; the moval changes them.
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g,?=g")
-	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      return \"cvtwl %1,%0\";
-    case 1:
-      if (push_operand (operands[0], SImode))
-	return \"pushl %1\;cvtwl 2(sp),(sp)\";
-      else
-	{
-          CC_STATUS_INIT;
-	  return \"pushl %1\;cvtwl 2(sp),%0\;moval 4(sp),sp\";
-	}
-    }
-}")
-
-; This monster is to cover for the Tahoe's nasty habit of not extending
-; a number if the source is in a register.  (It just moves it!) Case 0 is
-; a normal extend from memory.  Case 1 does the extension from the top of
-; the stack.  Extension from the stack doesn't set the flags right since
-; the moval changes them.
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g,?=g")
-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      return \"cvtbl %1,%0\";
-    case 1:
-      if (push_operand (operands[0], SImode))
-	return \"pushl %1\;cvtbl 3(sp),(sp)\";
-      else
-	{
-	  CC_STATUS_INIT;
-	  return \"pushl %1\;cvtbl 3(sp),%0\;moval 4(sp),sp\";
-	}
-    }
-}")
-
-
-; This monster is to cover for the Tahoe's nasty habit of not extending
-; a number if the source is in a register.  (It just moves it!) Case 0 is
-; a normal extend from memory.  Case 1 does the extension from the top of
-; the stack.  Extension from the stack doesn't set the flags right since
-; the moval changes them.
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=g,?=g")
-	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0:
-      return \"cvtbw %1,%0\";
-    case 1:
-      if (push_operand (operands[0], SImode))
-	return \"pushl %1\;cvtbw 3(sp),(sp)\";
-      else
-	{
-	  CC_STATUS_INIT;
-	  return \"pushl %1\;cvtbw 3(sp),%0\;moval 4(sp),sp\";
-	}
-     }
-}")
-
-
-; extendsfdf2 tahoe uses the fpp accumulator to do the extension.
-; It takes a float and loads it up directly as a double.
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=a")
-	(float_extend:DF (match_operand:SF 1 "general_operand" "g")))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  return \"ldfd %1\";
-}")
-
-
-; movz works fine from memory but not from register for the same reasons
-; the cvt instructions don't work right.  So we use the normal instruction
-; from memory and we use an and to simulate it from register.  This is faster
-; than pulling it off the stack.
-
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g,?=g")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0: return \"movzwl %1,%0\";
-    case 1: return \"andl3 $0xffff,%1,%0\";
-    }
-}")
-
-; movz works fine from memory but not from register for the same reasons
-; the cvt instructions don't work right.  So we use the normal instruction
-; from memory and we use an and to simulate it from register.  This is faster
-; than pulling it off the stack.
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=g,?=g")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0: return \"movzbw %1,%0\";
-    case 1: return \"andw3 $0xff,%1,%0\";
-    }
-}")
-
-
-; movz works fine from memory but not from register for the same reasons
-; the cvt instructions don't work right.  So we use the normal instruction
-; from memory and we use an and to simulate it from register.  This is faster
-; than pulling it off the stack.
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g,?=g")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0: return \"movzbl %1,%0\";
-    case 1: return \"andl3 $0xff,%1,%0\";
-    }
-}")
-
-
-(define_insn "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jeql %l0")
-
-
-(define_insn "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jneq %l0")
-
-
-(define_insn "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jgtr %l0")
-
-
-(define_insn "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jgtru %l0")
-
-
-(define_insn "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jlss %l0")
-
-
-(define_insn "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jlssu %l0")
-
-
-(define_insn "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jgeq %l0")
-
-
-(define_insn "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jgequ %l0")
-
-
-(define_insn "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jleq %l0")
-
-
-(define_insn "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jlequ %l0")
-
-
-; gcc does not account for register mask/argc longword.  Thus the number
-; for the call = number bytes for args + 4
-
-(define_insn "call"
-  [(call (match_operand:QI 0 "memory_operand" "m")
-	 (match_operand:QI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  operands[1] = GEN_INT ((INTVAL (operands[1]) + 4));
-  if (GET_CODE(operands[0]) == MEM
-      && CONSTANT_ADDRESS_P (XEXP(operands[0], 0))
-      && INTVAL (operands[1]) < 64)
-    return \"callf %1,%0\"; /* this is much faster */   
-  return \"calls %1,%0\";
-}")
-
-; gcc does not account for register mask/argc longword.  Thus the number
-; for the call = number bytes for args + 4
-
-(define_insn "call_value"
-  [(set (match_operand 0 "" "=g")
-	(call (match_operand:QI 1 "memory_operand" "m")
-	      (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  operands[2] = GEN_INT ((INTVAL (operands[2]) + 4));
-  if (GET_CODE(operands[1]) == MEM
-      && CONSTANT_ADDRESS_P (XEXP(operands[1], 0))
-      && INTVAL (operands[2]) < 64)
-    return \"callf %2,%1\"; /* this is much faster */   
-  return \"calls %2,%1\";
-}")
-
-
-(define_insn "return"
-  [(return)]
-  ""
-  "ret")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
-
-; casesi this code extracted from the vax code.  The instructions are
-; very similar.  Tahoe requires that the table be word aligned.  GCC
-; places the table immediately after, thus the alignment directive.
-
-(define_insn "casesi"
-  [(set (pc)
-	(if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
-				    (match_operand:SI 1 "general_operand" "g"))
-			  (match_operand:SI 2 "general_operand" "g"))
-		      (plus:SI (sign_extend:SI
-				(mem:HI (plus:SI (pc)
-						 (minus:SI (match_dup 0)
-							   (match_dup 1)))))
-			       (label_ref:SI (match_operand 3 "" "")))
-		      (pc)))]
-  ""
-  "casel %0,%1,%2\;.align %@")
-
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "jbr %l0")
-
-
-;; This is the list of all the non-standard insn patterns
-
-
-; This is used to access the address of a byte.  This is similar to
-; movqi, but the second operand had to be "address_operand" type, so
-; it had to be an unnamed one.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operand:QI 1 "address_operand" "p"))]
-  ""
-  "*
-{
-  if (push_operand (operands[0], SImode))
-    return \"pushab %a1\";
-  return \"movab %a1,%0\";
-}")
-
-; This is used to access the address of a word.  This is similar to
-; movhi, but the second operand had to be "address_operand" type, so
-; it had to be an unnamed one.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operand:HI 1 "address_operand" "p"))]
-  ""
-  "*
-{
-  if (push_operand (operands[0], SImode))
-    return \"pushaw %a1\";
-  return \"movaw %a1,%0\";
-}")
-
-; This is used to access the address of a long.  This is similar to
-; movsi, but the second operand had to be "address_operand" type, so
-; it had to be an unnamed one.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operand:SI 1 "address_operand" "p"))]
-  ""
-  "*
-{
-  if (push_operand (operands[0], SImode))
-    return \"pushal %a1\";
-  return \"moval %a1,%0\";
-}")
-
-
-; bit test longword instruction, same as vax
-
-(define_insn ""
-  [(set (cc0)
-	(and:SI (match_operand:SI 0 "general_operand" "g")
-		(match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "bitl %0,%1")
-
-
-; bit test word instructions, same as vax
-
-(define_insn ""
-  [(set (cc0)
-	(and:HI (match_operand:HI 0 "general_operand" "g")
-		(match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "bitw %0,%1")
-
-
-; bit test instructions, same as vax
-
-(define_insn ""
-  [(set (cc0)
-	(and:QI (match_operand:QI 0 "general_operand" "g")
-		(match_operand:QI 1 "general_operand" "g")))]
-  ""
-  "bitb %0,%1")
-
-
-; bne counterpart.  in case gcc reverses the conditional.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jneq %l0")
-
-
-; beq counterpart.  in case gcc reverses the conditional.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jeql %l0")
-
-
-; ble counterpart.  in case gcc reverses the conditional.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jleq %l0")
-
-
-; bleu counterpart.  in case gcc reverses the conditional.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jlequ %l0")
-
-
-; bge counterpart.  in case gcc reverses the conditional.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jgeq %l0")
-
-
-; bgeu counterpart.  in case gcc reverses the conditional.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jgequ %l0")
-
-
-; blt counterpart.  in case gcc reverses the conditional.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jlss %l0")
-
-
-; bltu counterpart.  in case gcc reverses the conditional.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jlssu %l0")
-
-
-; bgt counterpart.  in case gcc reverses the conditional.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jgtr %l0")
-
-
-; bgtu counterpart.  in case gcc reverses the conditional.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jgtru %l0")
-
-
-; casesi alternate form as found in vax code.  this form is to
-; compensate for the table's offset being no distance (0 displacement)
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (le (match_operand:SI 0 "general_operand" "g")
-			  (match_operand:SI 1 "general_operand" "g"))
-		      (plus:SI (sign_extend:SI
-				(mem:HI (plus:SI (pc)
-						 (minus:SI (match_dup 0)
-							   (const_int 0)))))
-			       (label_ref:SI (match_operand 3 "" "")))
-		      (pc)))]
-  ""
-  "casel %0,$0,%1\;.align %@")
-
-
-; casesi alternate form as found in vax code.  another form to
-; compensate for the table's offset being no distance (0 displacement)
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (le (match_operand:SI 0 "general_operand" "g")
-			  (match_operand:SI 1 "general_operand" "g"))
-		      (plus:SI (sign_extend:SI
-				(mem:HI (plus:SI (pc)
-						 (match_dup 0))))
-			       (label_ref:SI (match_operand 3 "" "")))
-		      (pc)))]
-  ""
-  "casel %0,$0,%1 \;.align %@")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (lt (plus:SI (match_operand:SI 0 "general_operand" "+g")
-		      (const_int 1))
-	     (match_operand:SI 1 "general_operand" "g"))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int 1)))]
-  ""
-  "aoblss %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (le (plus:SI (match_operand:SI 0 "general_operand" "+g")
-		      (const_int 1))
-	     (match_operand:SI 1 "general_operand" "g"))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int 1)))]
-  ""
-  "aobleq %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")
-		      (const_int 1))
-	     (match_operand:SI 1 "general_operand" "g"))
-	 (pc)
-	 (label_ref (match_operand 2 "" ""))))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int 1)))]
-  ""
-  "aoblss %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (gt (plus:SI (match_operand:SI 0 "general_operand" "+g")
-		      (const_int 1))
-	     (match_operand:SI 1 "general_operand" "g"))
-	 (pc)
-	 (label_ref (match_operand 2 "" ""))))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int 1)))]
-  ""
-  "aobleq %1,%0,%l2")
-
-; bbs/bbc
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
-			      (const_int 1)
-		      (subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
-	     (const_int 0))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))]
-  ""
-  "bbs %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
-			      (const_int 1)
-		      (subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
-	     (const_int 0))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))]
-  ""
-  "bbc %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
-			      (const_int 1)
-		      (subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
-	     (const_int 0))
-	 (pc)
-	 (label_ref (match_operand 2 "" ""))))]
-  ""
-  "bbc %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
-			      (const_int 1)
-		      (subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
-	     (const_int 0))
-	 (pc)
-	 (label_ref (match_operand 2 "" ""))))]
-  ""
-  "bbs %1,%0,%l2")
-
-; if the shift count is a byte in a register we can use it as a long
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
-			      (const_int 1)
-			      (match_operand:QI 1 "register_operand" "r"))
-	     (const_int 0))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))]
-  ""
-  "bbs %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
-			      (const_int 1)
-			      (match_operand:QI 1 "register_operand" "r"))
-	     (const_int 0))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))]
-  ""
-  "bbc %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
-			      (const_int 1)
-			      (match_operand:QI 1 "register_operand" "r"))
-	     (const_int 0))
-	 (pc)
-	 (label_ref (match_operand 2 "" ""))))]
-  ""
-  "bbc %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
-			      (const_int 1)
-			      (match_operand:QI 1 "register_operand" "r"))
-	     (const_int 0))
-	 (pc)
-	 (label_ref (match_operand 2 "" ""))))]
-  ""
-  "bbs %1,%0,%l2")
-
-; special case for 1 << constant.  We don't do these because they are slower
-; than the bitl instruction
-
-;(define_insn ""
-;  [(set (pc)
-;	(if_then_else
-;	 (ne (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm")
-;		     (match_operand:SI 1 "immediate_operand" "i"))
-;	     (const_int 0))
-;	 (label_ref (match_operand 2 "" ""))
-;	 (pc)))]
-;  "GET_CODE (operands[1]) == CONST_INT
-;   && exact_log2 (INTVAL (operands[1])) >= 0"
-;  "*
-;{
-;  operands[1]
-;    = GEN_INT (exact_log2 (INTVAL (operands[1])));
-;  return \"bbs %1,%0,%l2\";
-;}")
-;
-;(define_insn ""
-;  [(set (pc)
-;	(if_then_else
-;	 (eq (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm")
-;		     (match_operand:SI 1 "immediate_operand" "i"))
-;	     (const_int 0))
-;	 (label_ref (match_operand 2 "" ""))
-;	 (pc)))]
-;  "GET_CODE (operands[1]) == CONST_INT
-;   && exact_log2 (INTVAL (operands[1])) >= 0"
-;  "*
-;{
-;  operands[1]
-;    = GEN_INT (exact_log2 (INTVAL (operands[1])));
-;  return \"bbc %1,%0,%l2\";
-;}")
-;
-;(define_insn ""
-;  [(set (pc)
-;	(if_then_else
-;	 (ne (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm")
-;		     (match_operand:SI 1 "immediate_operand" "i"))
-;	     (const_int 0))
-;	 (pc)
-;	 (label_ref (match_operand 2 "" ""))))]
-;  "GET_CODE (operands[1]) == CONST_INT
-;   && exact_log2 (INTVAL (operands[1])) >= 0"
-;  "*
-;{
-;  operands[1]
-;    = GEN_INT (exact_log2 (INTVAL (operands[1])));
-;  return \"bbc %1,%0,%l2\";
-;}")
-;
-;(define_insn ""
-;  [(set (pc)
-;	(if_then_else
-;	 (eq (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm")
-;		     (match_operand:SI 1 "immediate_operand" "i"))
-;	     (const_int 0))
-;	 (pc)
-;	 (label_ref (match_operand 2 "" ""))))]
-;  "GET_CODE (operands[1]) == CONST_INT
-;   && exact_log2 (INTVAL (operands[1])) >= 0"
-;  "*
-;{
-;  operands[1]
-;    = GEN_INT (exact_log2 (INTVAL (operands[1])));
-;  return \"bbs %1,%0,%l2\";
-;}")
diff --git a/gcc/config/tahoe/xm-tahoe.h b/gcc/config/tahoe/xm-tahoe.h
deleted file mode 100755
index 1af7bdd..0000000
--- a/gcc/config/tahoe/xm-tahoe.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Configuration for GNU C-compiler for Tahoe.
-   Copyright (C) 1987, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/*
- * File: xm-tahoe.h
- *
- * Original port made at the University of Buffalo by Devon Bowen,
- * Dale Wiles and Kevin Zachmann.
- *
- * Changes for HCX by Piet van Oostrum,
- * University of Utrecht, The Netherlands (piet@cs.ruu.nl)
- *
- * Mail bugs reports or fixes to:	gcc@cs.buffalo.edu
- */
-
-
-/* This file has the same stuff the vax version does */
-
-/* defines that need visibility everywhere */
-
-#define FALSE 0
-#define TRUE 1
-
-/* target machine dependencies
-   tm.h is a symbolic link to the actual target specific file.   */
-
-#include "tm.h"
-
-/* This describes the machine the compiler is hosted on.  */
-
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_WORDS_BIG_ENDIAN
-
-/* Arguments to use with `exit'.  */
-
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
diff --git a/gcc/config/tm-dwarf2.h b/gcc/config/tm-dwarf2.h
deleted file mode 100755
index a580964..0000000
--- a/gcc/config/tm-dwarf2.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/* Enable Dwarf2 debugging and make it the default */
-#define  DWARF2_DEBUGGING_INFO 1
-#define  PREFERRED_DEBUGGING_TYPE  DWARF2_DEBUG
-
diff --git a/gcc/config/v850/lib1funcs.asm b/gcc/config/v850/lib1funcs.asm
deleted file mode 100755
index b07830d..0000000
--- a/gcc/config/v850/lib1funcs.asm
+++ /dev/null
@@ -1,1670 +0,0 @@
-/* libgcc1 routines for NEC V850.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with files
-   compiled with GCC to produce an executable, this does not cause
-   the resulting executable to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-#ifdef L_mulsi3
-	.text
-	.globl ___mulsi3
-	.type  ___mulsi3,@function
-
-/*
- * In order to not deal with negative numbers (mulh is a signed multiply
- * and we want an unsigned multiply, code the multiplication as a series
- * of 7 bit multiplies).
- *
- * int __mulsi3 (unsigned a, unsigned b)
- * {
- *   int i, j;
- *   int ret = 0;
- *
- *   for (i = 0; i < 32; i += 7)
- *     {
- *       short a_part = a & 0x7f;
- *       unsigned b_tmp = b;
- *       a >>= 7;
- * 
- *       for (j = 0; (i+j) < 32; j += 7)
- * 	{
- * 	  short b_part = b_tmp & 0x7f;
- * 	  ret += (((int)a_part) * ((int)b_part)) << (i+j);
- * 	  b_tmp >>= 7;
- * 	}
- *    }
- *
- *   return ret;
- * }
- */
-
-___mulsi3:
-	mov 0,r10			/* total */
-	mov 0,r14			/* i = 0, index for multiply a's part */
-	movea lo(31),r0,r16		/* upper bounds for loop */
-.L5:
-	mov r7,r13			/* b_tmp = b */
-	andi 0x7f,r6,r15		/* a_part = (a & 127) */
-	shr 7,r6			/* a >>= 7 */
-	mov r14,r12			/* i+j = i */
-.L9:
-	andi 0x7f,r13,r11		/* b_part = (b_tmp & 127) */
-	mulh r15,r11			/* ((int)a_part) * ((int)b_part) */
-	shr 7,r13			/* b_tmp >>= 7 */
-	shl r12,r11			/* (((int)a_part) * ((int)b_part)) << (i+j) */
-	add r11,r10			/* ret += (((int)a_part) * ((int)b_part)) << (i+j) */
-	add 7,r12			/* i+j += 7 */
-	cmp r16,r12			/* i+j < 32 */
-	ble .L9
-
-	add 7,r14			/* i += 7 */
-	cmp r16,r14			/* i < 32 */
-	ble .L5
-
-	jmp [r31]			/* return */
-	.size ___mulsi3,.-___mulsi3
-#endif
-
-#ifdef L_udivsi3
-	.text
-	.global ___udivsi3
-	.type	___udivsi3,@function
-___udivsi3:
-	mov 1,r12
-	mov 0,r10
-	cmp r6,r7
-	bnl .L12
-	movhi hi(-2147483648),r0,r13
-	cmp r0,r7
-	blt .L12
-.L4:
-	shl 1,r7
-	shl 1,r12
-	cmp r6,r7
-	bnl .L12
-	cmp r0,r12
-	be .L8
-	mov r7,r19
-	and r13,r19
-	be .L4
-	br .L12
-.L9:
-	cmp r7,r6
-	bl .L10
-	sub r7,r6
-	or r12,r10
-.L10:
-	shr 1,r12
-	shr 1,r7
-.L12:
-	cmp r0,r12
-	bne .L9
-.L8:
-	jmp [r31]
-	.size ___udivsi3,.-___udivsi3
-#endif
-
-#ifdef L_divsi3
-	.text
-	.globl ___divsi3
-	.type  ___divsi3,@function
-___divsi3:
-	add -8,sp
-	st.w r31,4[sp]
-	st.w r22,0[sp]
-	mov 1,r22
-	tst r7,r7
-	bp .L3
-	subr r0,r7
-	subr r0,r22
-.L3:
-	tst r6,r6
-	bp .L4
-	subr r0,r6
-	subr r0,r22
-.L4:
-	jarl ___udivsi3,r31
-	cmp r0,r22
-	bp .L7
-	subr r0,r10
-.L7:
-	ld.w 0[sp],r22
-	ld.w 4[sp],r31
-	add 8,sp
-	jmp [r31]
-	.size ___divsi3,.-___divsi3
-#endif
-
-#ifdef  L_umodsi3
-	.text
-	.globl ___umodsi3
-	.type  ___umodsi3,@function
-___umodsi3:
-	add -12,sp
-	st.w r31,8[sp]
-	st.w r7,4[sp]
-	st.w r6,0[sp]
-	jarl ___udivsi3,r31
-	ld.w 4[sp],r7
-	mov r10,r6
-	jarl ___mulsi3,r31
-	ld.w 0[sp],r6
-	subr r6,r10
-	ld.w 8[sp],r31
-	add 12,sp
-	jmp [r31]
-	.size ___umodsi3,.-___umodsi3
-#endif /* L_umodsi3 */
-
-#ifdef  L_modsi3
-	.text
-	.globl ___modsi3
-	.type  ___modsi3,@function
-___modsi3:
-	add -12,sp
-	st.w r31,8[sp]
-	st.w r7,4[sp]
-	st.w r6,0[sp]
-	jarl ___divsi3,r31
-	ld.w 4[sp],r7
-	mov r10,r6
-	jarl ___mulsi3,r31
-	ld.w 0[sp],r6
-	subr r6,r10
-	ld.w 8[sp],r31
-	add 12,sp
-	jmp [r31]
-	.size ___modsi3,.-___modsi3
-#endif /* L_modsi3 */
-
-/* CYGNUS LOCAL v850e */
-#ifdef  __v850__
-/* END CYGNUS LOCAL */
-#ifdef	L_save_2
-	.text
-	.align	2
-	.globl	__save_r2_r29
-	.type	__save_r2_r29,@function
-	/* Allocate space and save registers 2, 20 .. 29 on the stack */
-	/* Called via:	jalr __save_r2_r29,r10 */
-__save_r2_r29:
-	mov	ep,r1
-	addi	-44,sp,sp
-	mov	sp,ep
-	sst.w	r29,0[ep]
-	sst.w	r28,4[ep]
-	sst.w	r27,8[ep]
-	sst.w	r26,12[ep]
-	sst.w	r25,16[ep]
-	sst.w	r24,20[ep]
-	sst.w	r23,24[ep]
-	sst.w	r22,28[ep]
-	sst.w	r21,32[ep]
-	sst.w	r20,36[ep]
-	sst.w	r2,40[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r2_r29,.-__save_r2_r29
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r2_r29 */
-	.align	2
-	.globl	__return_r2_r29
-	.type	__return_r2_r29,@function
-__return_r2_r29:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	0[ep],r29
-	sld.w	4[ep],r28
-	sld.w	8[ep],r27
-	sld.w	12[ep],r26
-	sld.w	16[ep],r25
-	sld.w	20[ep],r24
-	sld.w	24[ep],r23
-	sld.w	28[ep],r22
-	sld.w	32[ep],r21
-	sld.w	36[ep],r20
-	sld.w	40[ep],r2
-	addi	44,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r2_r29,.-__return_r2_r29
-#endif /* L_save_2 */
-
-#ifdef	L_save_20
-	.text
-	.align	2
-	.globl	__save_r20_r29
-	.type	__save_r20_r29,@function
-	/* Allocate space and save registers 20 .. 29 on the stack */
-	/* Called via:	jalr __save_r20_r29,r10 */
-__save_r20_r29:
-	mov	ep,r1
-	addi	-40,sp,sp
-	mov	sp,ep
-	sst.w	r29,0[ep]
-	sst.w	r28,4[ep]
-	sst.w	r27,8[ep]
-	sst.w	r26,12[ep]
-	sst.w	r25,16[ep]
-	sst.w	r24,20[ep]
-	sst.w	r23,24[ep]
-	sst.w	r22,28[ep]
-	sst.w	r21,32[ep]
-	sst.w	r20,36[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r20_r29,.-__save_r20_r29
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r20_r29 */
-	.align	2
-	.globl	__return_r20_r29
-	.type	__return_r20_r29,@function
-__return_r20_r29:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	0[ep],r29
-	sld.w	4[ep],r28
-	sld.w	8[ep],r27
-	sld.w	12[ep],r26
-	sld.w	16[ep],r25
-	sld.w	20[ep],r24
-	sld.w	24[ep],r23
-	sld.w	28[ep],r22
-	sld.w	32[ep],r21
-	sld.w	36[ep],r20
-	addi	40,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r20_r29,.-__return_r20_r29
-#endif /* L_save_20 */
-
-#ifdef	L_save_21
-	.text
-	.align	2
-	.globl	__save_r21_r29
-	.type	__save_r21_r29,@function
-	/* Allocate space and save registers 21 .. 29 on the stack */
-	/* Called via:	jalr __save_r21_r29,r10 */
-__save_r21_r29:
-	mov	ep,r1
-	addi	-36,sp,sp
-	mov	sp,ep
-	sst.w	r29,0[ep]
-	sst.w	r28,4[ep]
-	sst.w	r27,8[ep]
-	sst.w	r26,12[ep]
-	sst.w	r25,16[ep]
-	sst.w	r24,20[ep]
-	sst.w	r23,24[ep]
-	sst.w	r22,28[ep]
-	sst.w	r21,32[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r21_r29,.-__save_r21_r29
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r21_r29 */
-	.align	2
-	.globl	__return_r21_r29
-	.type	__return_r21_r29,@function
-__return_r21_r29:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	0[ep],r29
-	sld.w	4[ep],r28
-	sld.w	8[ep],r27
-	sld.w	12[ep],r26
-	sld.w	16[ep],r25
-	sld.w	20[ep],r24
-	sld.w	24[ep],r23
-	sld.w	28[ep],r22
-	sld.w	32[ep],r21
-	addi	36,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r21_r29,.-__return_r21_r29
-#endif /* L_save_21 */
-
-#ifdef	L_save_22
-	.text
-	.align	2
-	.globl	__save_r22_r29
-	.type	__save_r22_r29,@function
-	/* Allocate space and save registers 22 .. 29 on the stack */
-	/* Called via:	jalr __save_r22_r29,r10 */
-__save_r22_r29:
-	mov	ep,r1
-	addi	-32,sp,sp
-	mov	sp,ep
-	sst.w	r29,0[ep]
-	sst.w	r28,4[ep]
-	sst.w	r27,8[ep]
-	sst.w	r26,12[ep]
-	sst.w	r25,16[ep]
-	sst.w	r24,20[ep]
-	sst.w	r23,24[ep]
-	sst.w	r22,28[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r22_r29,.-__save_r22_r29
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r22_r29 */
-	.align	2
-	.globl	__return_r22_r29
-	.type	__return_r22_r29,@function
-__return_r22_r29:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	0[ep],r29
-	sld.w	4[ep],r28
-	sld.w	8[ep],r27
-	sld.w	12[ep],r26
-	sld.w	16[ep],r25
-	sld.w	20[ep],r24
-	sld.w	24[ep],r23
-	sld.w	28[ep],r22
-	addi	32,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r22_r29,.-__return_r22_r29
-#endif /* L_save_22 */
-
-#ifdef	L_save_23
-	.text
-	.align	2
-	.globl	__save_r23_r29
-	.type	__save_r23_r29,@function
-	/* Allocate space and save registers 23 .. 29 on the stack */
-	/* Called via:	jalr __save_r23_r29,r10 */
-__save_r23_r29:
-	mov	ep,r1
-	addi	-28,sp,sp
-	mov	sp,ep
-	sst.w	r29,0[ep]
-	sst.w	r28,4[ep]
-	sst.w	r27,8[ep]
-	sst.w	r26,12[ep]
-	sst.w	r25,16[ep]
-	sst.w	r24,20[ep]
-	sst.w	r23,24[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r23_r29,.-__save_r23_r29
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r23_r29 */
-	.align	2
-	.globl	__return_r23_r29
-	.type	__return_r23_r29,@function
-__return_r23_r29:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	0[ep],r29
-	sld.w	4[ep],r28
-	sld.w	8[ep],r27
-	sld.w	12[ep],r26
-	sld.w	16[ep],r25
-	sld.w	20[ep],r24
-	sld.w	24[ep],r23
-	addi	28,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r23_r29,.-__return_r23_r29
-#endif /* L_save_23 */
-
-#ifdef	L_save_24
-	.text
-	.align	2
-	.globl	__save_r24_r29
-	.type	__save_r24_r29,@function
-	/* Allocate space and save registers 24 .. 29 on the stack */
-	/* Called via:	jalr __save_r24_r29,r10 */
-__save_r24_r29:
-	mov	ep,r1
-	addi	-24,sp,sp
-	mov	sp,ep
-	sst.w	r29,0[ep]
-	sst.w	r28,4[ep]
-	sst.w	r27,8[ep]
-	sst.w	r26,12[ep]
-	sst.w	r25,16[ep]
-	sst.w	r24,20[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r24_r29,.-__save_r24_r29
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r24_r29 */
-	.align	2
-	.globl	__return_r24_r29
-	.type	__return_r24_r29,@function
-__return_r24_r29:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	0[ep],r29
-	sld.w	4[ep],r28
-	sld.w	8[ep],r27
-	sld.w	12[ep],r26
-	sld.w	16[ep],r25
-	sld.w	20[ep],r24
-	addi	24,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r24_r29,.-__return_r24_r29
-#endif /* L_save_24 */
-
-#ifdef	L_save_25
-	.text
-	.align	2
-	.globl	__save_r25_r29
-	.type	__save_r25_r29,@function
-	/* Allocate space and save registers 25 .. 29 on the stack */
-	/* Called via:	jalr __save_r25_r29,r10 */
-__save_r25_r29:
-	mov	ep,r1
-	addi	-20,sp,sp
-	mov	sp,ep
-	sst.w	r29,0[ep]
-	sst.w	r28,4[ep]
-	sst.w	r27,8[ep]
-	sst.w	r26,12[ep]
-	sst.w	r25,16[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r25_r29,.-__save_r25_r29
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r25_r29 */
-	.align	2
-	.globl	__return_r25_r29
-	.type	__return_r25_r29,@function
-__return_r25_r29:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	0[ep],r29
-	sld.w	4[ep],r28
-	sld.w	8[ep],r27
-	sld.w	12[ep],r26
-	sld.w	16[ep],r25
-	addi	20,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r25_r29,.-__return_r25_r29
-#endif /* L_save_25 */
-
-#ifdef	L_save_26
-	.text
-	.align	2
-	.globl	__save_r26_r29
-	.type	__save_r26_r29,@function
-	/* Allocate space and save registers 26 .. 29 on the stack */
-	/* Called via:	jalr __save_r26_r29,r10 */
-__save_r26_r29:
-	mov	ep,r1
-	add	-16,sp
-	mov	sp,ep
-	sst.w	r29,0[ep]
-	sst.w	r28,4[ep]
-	sst.w	r27,8[ep]
-	sst.w	r26,12[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r26_r29,.-__save_r26_r29
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r26_r29 */
-	.align	2
-	.globl	__return_r26_r29
-	.type	__return_r26_r29,@function
-__return_r26_r29:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	0[ep],r29
-	sld.w	4[ep],r28
-	sld.w	8[ep],r27
-	sld.w	12[ep],r26
-	addi	16,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r26_r29,.-__return_r26_r29
-#endif /* L_save_26 */
-
-#ifdef	L_save_27
-	.text
-	.align	2
-	.globl	__save_r27_r29
-	.type	__save_r27_r29,@function
-	/* Allocate space and save registers 27 .. 29 on the stack */
-	/* Called via:	jalr __save_r27_r29,r10 */
-__save_r27_r29:
-	add	-12,sp
-	st.w	r29,0[sp]
-	st.w	r28,4[sp]
-	st.w	r27,8[sp]
-	jmp	[r10]
-	.size	__save_r27_r29,.-__save_r27_r29
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r27_r29 */
-	.align	2
-	.globl	__return_r27_r29
-	.type	__return_r27_r29,@function
-__return_r27_r29:
-	ld.w	0[sp],r29
-	ld.w	4[sp],r28
-	ld.w	8[sp],r27
-	add	12,sp
-	jmp	[r31]
-	.size	__return_r27_r29,.-__return_r27_r29
-#endif /* L_save_27 */
-
-#ifdef	L_save_28
-	.text
-	.align	2
-	.globl	__save_r28_r29
-	.type	__save_r28_r29,@function
-	/* Allocate space and save registers 28,29 on the stack */
-	/* Called via:	jalr __save_r28_r29,r10 */
-__save_r28_r29:
-	add	-8,sp
-	st.w	r29,0[sp]
-	st.w	r28,4[sp]
-	jmp	[r10]
-	.size	__save_r28_r29,.-__save_r28_r29
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r28_r29 */
-	.align	2
-	.globl	__return_r28_r29
-	.type	__return_r28_r29,@function
-__return_r28_r29:
-	ld.w	0[sp],r29
-	ld.w	4[sp],r28
-	add	8,sp
-	jmp	[r31]
-	.size	__return_r28_r29,.-__return_r28_r29
-#endif /* L_save_28 */
-
-#ifdef	L_save_29
-	.text
-	.align	2
-	.globl	__save_r29
-	.type	__save_r29,@function
-	/* Allocate space and save register 29 on the stack */
-	/* Called via:	jalr __save_r29,r10 */
-__save_r29:
-	add	-4,sp
-	st.w	r29,0[sp]
-	jmp	[r10]
-	.size	__save_r29,.-__save_r29
-
-	/* Restore saved register 29, deallocate stack and return to the user */
-	/* Called via:	jr __return_r29 */
-	.align	2
-	.globl	__return_r29
-	.type	__return_r29,@function
-__return_r29:
-	ld.w	0[sp],r29
-	add	4,sp
-	jmp	[r31]
-	.size	__return_r29,.-__return_r29
-#endif /* L_save_28 */
-
-#ifdef	L_save_2c
-	.text
-	.align	2
-	.globl	__save_r2_r31
-	.type	__save_r2_r31,@function
-	/* Allocate space and save registers 20 .. 29, 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	jalr __save_r2_r31,r10 */
-__save_r2_r31:
-	mov	ep,r1
-	addi	-64,sp,sp
-	mov	sp,ep
-	sst.w	r29,16[ep]
-	sst.w	r28,20[ep]
-	sst.w	r27,24[ep]
-	sst.w	r26,28[ep]
-	sst.w	r25,32[ep]
-	sst.w	r24,36[ep]
-	sst.w	r23,40[ep]
-	sst.w	r22,44[ep]
-	sst.w	r21,48[ep]
-	sst.w	r20,52[ep]
-	sst.w	r2,56[ep]
-	sst.w	r31,60[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r2_r31,.-__save_r2_r31
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r20_r31 */
-	.align	2
-	.globl	__return_r2_r31
-	.type	__return_r2_r31,@function
-__return_r2_r31:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	16[ep],r29
-	sld.w	20[ep],r28
-	sld.w	24[ep],r27
-	sld.w	28[ep],r26
-	sld.w	32[ep],r25
-	sld.w	36[ep],r24
-	sld.w	40[ep],r23
-	sld.w	44[ep],r22
-	sld.w	48[ep],r21
-	sld.w	52[ep],r20
-	sld.w	56[ep],r2
-	sld.w	60[ep],r31
-	addi	64,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r2_r31,.-__return_r2_r31
-#endif /* L_save_2c */
-
-#ifdef	L_save_20c
-	.text
-	.align	2
-	.globl	__save_r20_r31
-	.type	__save_r20_r31,@function
-	/* Allocate space and save registers 20 .. 29, 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	jalr __save_r20_r31,r10 */
-__save_r20_r31:
-	mov	ep,r1
-	addi	-60,sp,sp
-	mov	sp,ep
-	sst.w	r29,16[ep]
-	sst.w	r28,20[ep]
-	sst.w	r27,24[ep]
-	sst.w	r26,28[ep]
-	sst.w	r25,32[ep]
-	sst.w	r24,36[ep]
-	sst.w	r23,40[ep]
-	sst.w	r22,44[ep]
-	sst.w	r21,48[ep]
-	sst.w	r20,52[ep]
-	sst.w	r31,56[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r20_r31,.-__save_r20_r31
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r20_r31 */
-	.align	2
-	.globl	__return_r20_r31
-	.type	__return_r20_r31,@function
-__return_r20_r31:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	16[ep],r29
-	sld.w	20[ep],r28
-	sld.w	24[ep],r27
-	sld.w	28[ep],r26
-	sld.w	32[ep],r25
-	sld.w	36[ep],r24
-	sld.w	40[ep],r23
-	sld.w	44[ep],r22
-	sld.w	48[ep],r21
-	sld.w	52[ep],r20
-	sld.w	56[ep],r31
-	addi	60,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r20_r31,.-__return_r20_r31
-#endif /* L_save_20c */
-
-#ifdef	L_save_21c
-	.text
-	.align	2
-	.globl	__save_r21_r31
-	.type	__save_r21_r31,@function
-	/* Allocate space and save registers 21 .. 29, 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	jalr __save_r21_r31,r10 */
-__save_r21_r31:
-	mov	ep,r1
-	addi	-56,sp,sp
-	mov	sp,ep
-	sst.w	r29,16[ep]
-	sst.w	r28,20[ep]
-	sst.w	r27,24[ep]
-	sst.w	r26,28[ep]
-	sst.w	r25,32[ep]
-	sst.w	r24,36[ep]
-	sst.w	r23,40[ep]
-	sst.w	r22,44[ep]
-	sst.w	r21,48[ep]
-	sst.w	r31,52[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r21_r31,.-__save_r21_r31
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r21_r31 */
-	.align	2
-	.globl	__return_r21_r31
-	.type	__return_r21_r31,@function
-__return_r21_r31:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	16[ep],r29
-	sld.w	20[ep],r28
-	sld.w	24[ep],r27
-	sld.w	28[ep],r26
-	sld.w	32[ep],r25
-	sld.w	36[ep],r24
-	sld.w	40[ep],r23
-	sld.w	44[ep],r22
-	sld.w	48[ep],r21
-	sld.w	52[ep],r31
-	addi	56,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r21_r31,.-__return_r21_r31
-#endif /* L_save_21c */
-
-#ifdef	L_save_22c
-	.text
-	.align	2
-	.globl	__save_r22_r31
-	.type	__save_r22_r31,@function
-	/* Allocate space and save registers 22 .. 29, 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	jalr __save_r22_r31,r10 */
-__save_r22_r31:
-	mov	ep,r1
-	addi	-52,sp,sp
-	mov	sp,ep
-	sst.w	r29,16[ep]
-	sst.w	r28,20[ep]
-	sst.w	r27,24[ep]
-	sst.w	r26,28[ep]
-	sst.w	r25,32[ep]
-	sst.w	r24,36[ep]
-	sst.w	r23,40[ep]
-	sst.w	r22,44[ep]
-	sst.w	r31,48[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r22_r31,.-__save_r22_r31
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r22_r31 */
-	.align	2
-	.globl	__return_r22_r31
-	.type	__return_r22_r31,@function
-__return_r22_r31:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	16[ep],r29
-	sld.w	20[ep],r28
-	sld.w	24[ep],r27
-	sld.w	28[ep],r26
-	sld.w	32[ep],r25
-	sld.w	36[ep],r24
-	sld.w	40[ep],r23
-	sld.w	44[ep],r22
-	sld.w	48[ep],r31
-	addi	52,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r22_r31,.-__return_r22_r31
-#endif /* L_save_22c */
-
-#ifdef	L_save_23c
-	.text
-	.align	2
-	.globl	__save_r23_r31
-	.type	__save_r23_r31,@function
-	/* Allocate space and save registers 23 .. 29, 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	jalr __save_r23_r31,r10 */
-__save_r23_r31:
-	mov	ep,r1
-	addi	-48,sp,sp
-	mov	sp,ep
-	sst.w	r29,16[ep]
-	sst.w	r28,20[ep]
-	sst.w	r27,24[ep]
-	sst.w	r26,28[ep]
-	sst.w	r25,32[ep]
-	sst.w	r24,36[ep]
-	sst.w	r23,40[ep]
-	sst.w	r31,44[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r23_r31,.-__save_r23_r31
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r23_r31 */
-	.align	2
-	.globl	__return_r23_r31
-	.type	__return_r23_r31,@function
-__return_r23_r31:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	16[ep],r29
-	sld.w	20[ep],r28
-	sld.w	24[ep],r27
-	sld.w	28[ep],r26
-	sld.w	32[ep],r25
-	sld.w	36[ep],r24
-	sld.w	40[ep],r23
-	sld.w	44[ep],r31
-	addi	48,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r23_r31,.-__return_r23_r31
-#endif /* L_save_23c */
-
-#ifdef	L_save_24c
-	.text
-	.align	2
-	.globl	__save_r24_r31
-	.type	__save_r24_r31,@function
-	/* Allocate space and save registers 24 .. 29, 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	jalr __save_r24_r31,r10 */
-__save_r24_r31:
-	mov	ep,r1
-	addi	-44,sp,sp
-	mov	sp,ep
-	sst.w	r29,16[ep]
-	sst.w	r28,20[ep]
-	sst.w	r27,24[ep]
-	sst.w	r26,28[ep]
-	sst.w	r25,32[ep]
-	sst.w	r24,36[ep]
-	sst.w	r31,40[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r24_r31,.-__save_r24_r31
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r24_r31 */
-	.align	2
-	.globl	__return_r24_r31
-	.type	__return_r24_r31,@function
-__return_r24_r31:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	16[ep],r29
-	sld.w	20[ep],r28
-	sld.w	24[ep],r27
-	sld.w	28[ep],r26
-	sld.w	32[ep],r25
-	sld.w	36[ep],r24
-	sld.w	40[ep],r31
-	addi	44,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r24_r31,.-__return_r24_r31
-#endif /* L_save_24c */
-
-#ifdef	L_save_25c
-	.text
-	.align	2
-	.globl	__save_r25_r31
-	.type	__save_r25_r31,@function
-	/* Allocate space and save registers 25 .. 29, 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	jalr __save_r25_r31,r10 */
-__save_r25_r31:
-	mov	ep,r1
-	addi	-40,sp,sp
-	mov	sp,ep
-	sst.w	r29,16[ep]
-	sst.w	r28,20[ep]
-	sst.w	r27,24[ep]
-	sst.w	r26,28[ep]
-	sst.w	r25,32[ep]
-	sst.w	r31,36[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r25_r31,.-__save_r25_r31
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r25_r31 */
-	.align	2
-	.globl	__return_r25_r31
-	.type	__return_r25_r31,@function
-__return_r25_r31:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	16[ep],r29
-	sld.w	20[ep],r28
-	sld.w	24[ep],r27
-	sld.w	28[ep],r26
-	sld.w	32[ep],r25
-	sld.w	36[ep],r31
-	addi	40,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r25_r31,.-__return_r25_r31
-#endif /* L_save_25c */
-
-#ifdef	L_save_26c
-	.text
-	.align	2
-	.globl	__save_r26_r31
-	.type	__save_r26_r31,@function
-	/* Allocate space and save registers 26 .. 29, 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	jalr __save_r26_r31,r10 */
-__save_r26_r31:
-	mov	ep,r1
-	addi	-36,sp,sp
-	mov	sp,ep
-	sst.w	r29,16[ep]
-	sst.w	r28,20[ep]
-	sst.w	r27,24[ep]
-	sst.w	r26,28[ep]
-	sst.w	r31,32[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r26_r31,.-__save_r26_r31
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r26_r31 */
-	.align	2
-	.globl	__return_r26_r31
-	.type	__return_r26_r31,@function
-__return_r26_r31:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	16[ep],r29
-	sld.w	20[ep],r28
-	sld.w	24[ep],r27
-	sld.w	28[ep],r26
-	sld.w	32[ep],r31
-	addi	36,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r26_r31,.-__return_r26_r31
-#endif /* L_save_26c */
-
-#ifdef	L_save_27c
-	.text
-	.align	2
-	.globl	__save_r27_r31
-	.type	__save_r27_r31,@function
-	/* Allocate space and save registers 27 .. 29, 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	jalr __save_r27_r31,r10 */
-__save_r27_r31:
-	mov	ep,r1
-	addi	-32,sp,sp
-	mov	sp,ep
-	sst.w	r29,16[ep]
-	sst.w	r28,20[ep]
-	sst.w	r27,24[ep]
-	sst.w	r31,28[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r27_r31,.-__save_r27_r31
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r27_r31 */
-	.align	2
-	.globl	__return_r27_r31
-	.type	__return_r27_r31,@function
-__return_r27_r31:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	16[ep],r29
-	sld.w	20[ep],r28
-	sld.w	24[ep],r27
-	sld.w	28[ep],r31
-	addi	32,sp,sp
-	mov	r1,ep
-	jmp	[r31]
-	.size	__return_r27_r31,.-__return_r27_r31
-#endif /* L_save_27c */
-
-#ifdef	L_save_28c
-	.text
-	.align	2
-	.globl	__save_r28_r31
-	.type	__save_r28_r31,@function
-	/* Allocate space and save registers 28 .. 29, 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	jalr __save_r28_r31,r10 */
-__save_r28_r31:
-	addi	-28,sp,sp
-	st.w	r29,16[sp]
-	st.w	r28,20[sp]
-	st.w	r31,24[sp]
-	jmp	[r10]
-	.size	__save_r28_r31,.-__save_r28_r31
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r28_r31 */
-	.align	2
-	.globl	__return_r28_r31
-	.type	__return_r28_r31,@function
-__return_r28_r31:
-	ld.w	16[sp],r29
-	ld.w	20[sp],r28
-	ld.w	24[sp],r31
-	addi	28,sp,sp
-	jmp	[r31]
-	.size	__return_r28_r31,.-__return_r28_r31
-#endif /* L_save_28c */
-
-#ifdef	L_save_29c
-	.text
-	.align	2
-	.globl	__save_r29_r31
-	.type	__save_r29_r31,@function
-	/* Allocate space and save registers 29 & 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	jalr __save_r29_r31,r10 */
-__save_r29_r31:
-	addi	-24,sp,sp
-	st.w	r29,16[sp]
-	st.w	r31,20[sp]
-	jmp	[r10]
-	.size	__save_r29_r31,.-__save_r29_r31
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r29_r31 */
-	.align	2
-	.globl	__return_r29_r31
-	.type	__return_r29_r31,@function
-__return_r29_r31:
-	ld.w	16[sp],r29
-	ld.w	20[sp],r31
-	addi	24,sp,sp
-	jmp	[r31]
-	.size	__return_r29_r31,.-__return_r29_r31
-#endif /* L_save_29c */
-
-#ifdef	L_save_31c
-	.text
-	.align	2
-	.globl	__save_r31
-	.type	__save_r31,@function
-	/* Allocate space and save register 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	jalr __save_r29_r31,r10 */
-__save_r31:
-	addi	-20,sp,sp
-	st.w	r31,16[sp]
-	jmp	[r10]
-	.size	__save_r31,.-__save_r31
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	jr __return_r31 */
-	.align	2
-	.globl	__return_r31
-	.type	__return_r31,@function
-__return_r31:
-	ld.w	16[sp],r31
-	addi	20,sp,sp
-	jmp	[r31]
-	.size	__return_r29_r31,.-__return_r29_r31
-#endif /* L_save_31c */
-
-#ifdef L_save_varargs
-	.text
-	.align	2
-	.globl	__save_r6_r9
-	.type	__save_r6_r9,@function
-	/* Save registers 6 .. 9 on the stack for variable argument functions */
-	/* Called via:	jalr __save_r6_r9,r10 */
-__save_r6_r9:
-	mov	ep,r1
-	mov	sp,ep
-	sst.w	r6,0[ep]
-	sst.w	r7,4[ep]
-	sst.w	r8,8[ep]
-	sst.w	r9,12[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_r6_r9,.-__save_r6_r9
-#endif /* L_save_varargs */
-
-#ifdef	L_save_interrupt
-	.text
-	.align	2
-	.globl	__save_interrupt
-	.type	__save_interrupt,@function
-	/* Save registers r1, r4 on stack and load up with expected values */
-	/* Note, 12 bytes of stack have already been allocated. */
-	/* Called via:	jalr __save_interrupt,r10 */
-__save_interrupt:
-	st.w	ep,0[sp]
-	st.w	gp,4[sp]
-	st.w	r1,8[sp]
-	movhi	hi(__ep),r0,ep
-	movea	lo(__ep),ep,ep
-	movhi	hi(__gp),r0,gp
-	movea	lo(__gp),gp,gp
-	jmp	[r10]
-	.size	__save_interrupt,.-__save_interrupt
-
-	/* Restore saved registers, deallocate stack and return from the interrupt */
-	/* Called via:	jr __return_interrupt */
-	.align	2
-	.globl	__return_interrupt
-	.type	__return_interrupt,@function
-__return_interrupt:
-	ld.w	0[sp],ep
-	ld.w	4[sp],gp
-	ld.w	8[sp],r1
-	ld.w	12[sp],r10
-	addi	16,sp,sp
-	reti
-	.size	__return_interrupt,.-__return_interrupt
-#endif /* L_save_interrupt */
-
-#ifdef L_save_all_interrupt
-	.text
-	.align	2
-	.globl	__save_all_interrupt
-	.type	__save_all_interrupt,@function
-	/* Save all registers except for those saved in __save_interrupt */
-	/* allocate enough stack for all of the registers & 16 bytes of space */
-	/* Called via:	jalr __save_all_interrupt,r10 */
-__save_all_interrupt:
-	addi	-120,sp,sp
-	mov	ep,r1
-	mov	sp,ep
-	sst.w	r31,116[ep]
-	sst.w	r2,112[ep]
-	sst.w	gp,108[ep]
-	sst.w	r6,104[ep]
-	sst.w	r7,100[ep]
-	sst.w	r8,96[ep]
-	sst.w	r9,92[ep]
-	sst.w	r11,88[ep]
-	sst.w	r12,84[ep]
-	sst.w	r13,80[ep]
-	sst.w	r14,76[ep]
-	sst.w	r15,72[ep]
-	sst.w	r16,68[ep]
-	sst.w	r17,64[ep]
-	sst.w	r18,60[ep]
-	sst.w	r19,56[ep]
-	sst.w	r20,52[ep]
-	sst.w	r21,48[ep]
-	sst.w	r22,44[ep]
-	sst.w	r23,40[ep]
-	sst.w	r24,36[ep]
-	sst.w	r25,32[ep]
-	sst.w	r26,28[ep]
-	sst.w	r27,24[ep]
-	sst.w	r28,20[ep]
-	sst.w	r29,16[ep]
-	mov	r1,ep
-	jmp	[r10]
-	.size	__save_all_interrupt,.-__save_all_interrupt
-
-	.globl	__restore_all_interrupt
-	.type	__restore_all_interrupt,@function
-	/* Restore all registers saved in __save_all_interrupt */
-	/* & deallocate the stack space */
-	/* Called via:	jalr __restore_all_interrupt,r10 */
-__restore_all_interrupt:
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	116[ep],r31
-	sld.w	112[ep],r2
-	sld.w	108[ep],gp
-	sld.w	104[ep],r6
-	sld.w	100[ep],r7
-	sld.w	96[ep],r8
-	sld.w	92[ep],r9
-	sld.w	88[ep],r11
-	sld.w	84[ep],r12
-	sld.w	80[ep],r13
-	sld.w	76[ep],r14
-	sld.w	72[ep],r15
-	sld.w	68[ep],r16
-	sld.w	64[ep],r17
-	sld.w	60[ep],r18
-	sld.w	56[ep],r19
-	sld.w	52[ep],r20
-	sld.w	48[ep],r21
-	sld.w	44[ep],r22
-	sld.w	40[ep],r23
-	sld.w	36[ep],r24
-	sld.w	32[ep],r25
-	sld.w	28[ep],r26
-	sld.w	24[ep],r27
-	sld.w	20[ep],r28
-	sld.w	16[ep],r29
-	mov	r1,ep
-	addi	120,sp,sp
-	jmp	[r10]
-	.size	__restore_all_interrupt,.-__restore_all_interrupt
-#endif /* L_save_all_interrupt */
-
-/* CYGNUS LOCAL v850e */
-#endif /* __v850__ */
-	
-#if defined  __v850e__ || defined __v850ea__
-#ifdef	L_callt_save_r2_r29
-	/* Put these functions into the call table area */
-	.call_table_text
-	
-	/* Allocate space and save registers 2, 20 .. 29 on the stack */
-	/* Called via:	callt ctoff(__callt_save_r2_r29) */
-	.align	2
-.L_save_r2_r29:
-#ifdef __v850ea__
-	pushml {r2}
-#else
-	addi	-4, sp, sp
-	st.w	r2, 0[sp]
-#endif
-	prepare {r20 - r29}, 0
-	ctret
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	callt ctoff(__callt_return_r2_r29) */
-	.align	2
-.L_return_r2_r29:
-	dispose 0, {r20-r29}
-#ifdef __v850ea__
-	popml   {r2}
-#else
-	ld.w    0[sp], r2
-	addi	4, sp, sp
-#endif
-	jmp     [r31]
-
-	/* Place the offsets of the start of these routines into the call table.  */
-	.call_table_data
-
-	.global	__callt_save_r2_r29
-	.type	__callt_save_r2_r29,@function
-__callt_save_r2_r29:	.short ctoff(.L_save_r2_r29)
-	
-	.global	__callt_return_r2_r29
-	.type	__callt_return_r2_r29,@function
-__callt_return_r2_r29:	.short ctoff(.L_return_r2_r29)
-	
-#endif /* L_callt_save_r2_r29 */
-
-
-#ifdef	L_callt_save_r2_r31
-	/* Put these functions into the call table area */
-	.call_table_text
-	
-	/* Allocate space and save registers 2 and 20 .. 29, 31 on the stack */
-	/* Also allocate space for the argument save area */
-	/* Called via:	callt ctoff(__callt_save_r2_r31) */
-	.align	2
-.L_save_r2_r31:
-#ifdef __v850ea__
-	pushml {r2}
-#else
-	addi	-4, sp, sp
-	st.w	r2, 0[sp]
-#endif
-	prepare {r20 - r29, r31}, 4
-	ctret
-
-	/* Restore saved registers, deallocate stack and return to the user */
-	/* Called via:	callt ctoff(__callt_return_r2_r31) */
-	.align	2
-.L_return_r2_r31:
-	dispose 4, {r20 - r29, r31}
-#ifdef __v850ea__
-	popml   {r2}
-#else
-	ld.w    0[sp], r2
-	addi	4, sp, sp
-#endif
-	jmp     [r31]
-
-	/* Place the offsets of the start of these routines into the call table.  */
-	.call_table_data
-
-	.global	__callt_save_r2_r31
-	.type	__callt_save_r2_r31,@function
-__callt_save_r2_r31:	.short ctoff(.L_save_r2_r31)
-	
-	.global	__callt_return_r2_r31
-	.type	__callt_return_r2_r31,@function
-__callt_return_r2_r31:	.short ctoff(.L_return_r2_r31)
-	
-#endif /* L_callt_save_r2_r31 */
-
-
-#ifdef L_callt_save_r6_r9
-	/* Put these functions into the call table area. */
-	.call_table_text
-	
-	/* Save registers r6 - r9 onto the stack in the space reserved for them.
-	   Use by variable argument functions. 
-	   Called via:	callt ctoff(__callt_save_r6_r9) */
-	.align	2
-.L_save_r6_r9:
-	mov	ep,r1
-	mov	sp,ep
-	sst.w	r6,0[ep]
-	sst.w	r7,4[ep]
-	sst.w	r8,8[ep]
-	sst.w	r9,12[ep]
-	mov	r1,ep
-	ctret
-
-	/* Place the offsets of the start of this routines into the call table.  */
-	.call_table_data
-
-	.global	__callt_save_r6_r9
-	.type	__callt_save_r6_r9,@function
-__callt_save_r6_r9:	.short ctoff(.L_save_r6_r9)
-#endif /* L_callt_save_r6_r9 */
-
-	
-#ifdef	L_callt_save_interrupt
-	/* Put this functions into the call table area */
-	.call_table_text
-	
-	/* Save registers r1, ep, gp, r10 on stack and load up with expected values */
-	/* Called via:	callt ctoff(__callt_save_interrupt) */
-	.align	2
-.L_save_interrupt:
-	add     -16, sp
-	st.w	ep,  0[sp]
-	st.w	r10, 4[sp]
-	st.w	gp,  8[sp]
-	st.w	r1,  12[sp]
-	mov	hilo(__ep),ep
-	mov	hilo(__gp),gp
-	ctret
-
-
-	/* Restore saved registers, deallocate stack and return from the interrupt */
-	/* Called via:	jr __return_interupt */
-	.text
-	.align	2
-	.globl	__return_interrupt
-	.type	__return_interrupt,@function
-__return_interrupt:
-	ld.w	 0[sp], ep
-	ld.w	 4[sp], r10
-	ld.w	 8[sp], gp
-	ld.w	12[sp], r1
-	addi	16, sp, sp
-	reti
-
-	/* Place the offsets of the start of the routine into the call table.  */
-	.call_table_data
-
-	.global	__callt_save_interrupt
-	.type   __callt_save_interrupt,@function
-__callt_save_interrupt:	.short ctoff(.L_save_interrupt)
-	
-#endif /* L_callt_save_interrupt */
-
-#ifdef L_callt_save_all_interrupt
-	/* Put this functions into the call table area */
-	.call_table_text
-	
-	/* Save all registers except for those saved in __save_interrupt.  */
-	/* Allocate enough stack for all of the registers & 16 bytes of space.  */
-	/* Called via:	callt ctoff(__callt_save_all_interrupt).  */
-	.align	2
-.L_save_all_interrupt:
-#ifdef __v850ea__
-	pushml {r2, r5 - r9, r11 - r15}
-	pushmh {r16 - r29, r31}
-	addi	-16,sp,sp
-#else
-	addi	-60,sp,sp
-	mov	ep,r1
-	mov	sp,ep
-	sst.w	r2, 56[ep]
-	sst.w	r5, 52[ep]
-	sst.w	r6, 48[ep]
-	sst.w	r7, 44[ep]
-	sst.w	r8, 40[ep]
-	sst.w	r9, 36[ep]
-	sst.w	r11,32[ep]
-	sst.w	r12,28[ep]
-	sst.w	r13,24[ep]
-	sst.w	r14,20[ep]
-	sst.w	r15,16[ep]
-	sst.w	r16,12[ep]
-	sst.w	r17, 8[ep]
-	sst.w	r18, 4[ep]
-	sst.w	r19, 0[ep]
-	mov	r1,ep
-
-	prepare {r20 - r29, r31}, 4
-#endif
-	ctret	
-
-	/* Restore all registers saved in __save_all_interrupt */
-	/* & deallocate the stack space */
-	/* Called via:	callt ctoff(__callt_restore_all_interrupt) */
-	.align 2
-.L_restore_all_interrupt:
-#ifdef __v850ea__
-	addi	16,sp,sp
-	popmh   {r16 - r29, r31}
-	popml   {r2, r5 - r9, r11 - r15}
-#else
-	dispose 4, {r20 - r29, r31}
-	
-	mov	ep,r1
-	mov	sp,ep
-	sld.w	0 [ep],r19
-	sld.w	4 [ep],r18
-	sld.w	8 [ep],r17
-	sld.w	12[ep],r16
-	sld.w	16[ep],r15
-	sld.w	20[ep],r14
-	sld.w	24[ep],r13
-	sld.w	28[ep],r12
-	sld.w	32[ep],r11
-	sld.w	36[ep],r9
-	sld.w	40[ep],r8
-	sld.w	44[ep],r7
-	sld.w	48[ep],r6
-	sld.w	52[ep],r5
-	sld.w	56[ep],r2
-	mov	r1,ep
-	addi	60,sp,sp
-#endif
-	ctret
-
-	/* Place the offsets of the start of these routines into the call table.  */
-	.call_table_data
-
-	.global	__callt_save_all_interrupt
-	.type	__callt_save_all_interrupt,@function
-__callt_save_all_interrupt:	.short ctoff(.L_save_all_interrupt)
-	
-	.global	__callt_restore_all_interrupt
-	.type	__callt_restore_all_interrupt,@function
-__callt_restore_all_interrupt:	.short ctoff(.L_restore_all_interrupt)
-	
-#endif /* L_callt_save_all_interrupt */
-
-
-#define MAKE_CALLT_FUNCS( START )						\
-	.call_table_text							;\
-	.align	2								;\
-	/* Allocate space and save registers START .. r29 on the stack */	;\
-	/* Called via:	callt ctoff(__callt_save_START_r29). */			;\
-.L_save_##START##_r29:								;\
-	prepare { START - r29 }, 0						;\
-	ctret									;\
-										;\
-	/* Restore saved registers, deallocate stack and return */		;\
-	/* Called via:	callt ctoff(__return_START_r29) */			;\
-	.align	2								;\
-.L_return_##START##_r29:							;\
-	dispose 0, { START - r29 }, r31						;\
-										;\
-	/* Place the offsets of the start of these funcs into the call table. */;\
-	.call_table_data							;\
-										;\
-	.global	__callt_save_##START##_r29					;\
-	.type	__callt_save_##START##_r29,@function				;\
-__callt_save_##START##_r29:	.short ctoff(.L_save_##START##_r29 )		;\
-										;\
-	.global	__callt_return_##START##_r29					;\
-	.type	__callt_return_##START##_r29,@function				;\
-__callt_return_##START##_r29:	.short ctoff(.L_return_##START##_r29 )	
-
-
-#define MAKE_CALLT_CFUNCS( START )						\
-	.call_table_text							;\
-	.align	2								;\
-	/* Allocate space and save registers START .. r31 on the stack */	;\
-	/* Called via:	callt ctoff(__callt_save_START_r31c). */		;\
-.L_save_##START##_r31c:								;\
-	prepare { START - r29, r31}, 4						;\
-	ctret									;\
-										;\
-	/* Restore saved registers, deallocate stack and return */		;\
-	/* Called via:	callt ctoff(__return_START_r31c) */			;\
-	.align	2								;\
-.L_return_##START##_r31c:							;\
-	dispose 4, { START - r29, r31}, r31					;\
-										;\
-	/* Place the offsets of the start of these funcs into the call table. */;\
-	.call_table_data							;\
-										;\
-	.global	__callt_save_##START##_r31c					;\
-	.type	__callt_save_##START##_r31c,@function				;\
-__callt_save_##START##_r31c:    .short ctoff(.L_save_##START##_r31c )		;\
-										;\
-	.global	__callt_return_##START##_r31c					;\
-	.type	__callt_return_##START##_r31c,@function				;\
-__callt_return_##START##_r31c:  .short ctoff(.L_return_##START##_r31c )	
-
-
-
-	
-#ifdef	L_callt_save_20
-	MAKE_CALLT_FUNCS (r20)
-#endif
-#ifdef	L_callt_save_21
-	MAKE_CALLT_FUNCS (r21)
-#endif
-#ifdef	L_callt_save_22
-	MAKE_CALLT_FUNCS (r22)
-#endif
-#ifdef	L_callt_save_23
-	MAKE_CALLT_FUNCS (r23)
-#endif
-#ifdef	L_callt_save_24
-	MAKE_CALLT_FUNCS (r24)
-#endif
-#ifdef	L_callt_save_25
-	MAKE_CALLT_FUNCS (r25)
-#endif
-#ifdef	L_callt_save_26
-	MAKE_CALLT_FUNCS (r26)
-#endif
-#ifdef	L_callt_save_27
-	MAKE_CALLT_FUNCS (r27)
-#endif
-#ifdef	L_callt_save_28
-	MAKE_CALLT_FUNCS (r28)
-#endif
-#ifdef	L_callt_save_29
-	MAKE_CALLT_FUNCS (r29)
-#endif
-
-#ifdef	L_callt_save_20c
-	MAKE_CALLT_CFUNCS (r20)
-#endif
-#ifdef	L_callt_save_21c
-	MAKE_CALLT_CFUNCS (r21)
-#endif
-#ifdef	L_callt_save_22c
-	MAKE_CALLT_CFUNCS (r22)
-#endif
-#ifdef	L_callt_save_23c
-	MAKE_CALLT_CFUNCS (r23)
-#endif
-#ifdef	L_callt_save_24c
-	MAKE_CALLT_CFUNCS (r24)
-#endif
-#ifdef	L_callt_save_25c
-	MAKE_CALLT_CFUNCS (r25)
-#endif
-#ifdef	L_callt_save_26c
-	MAKE_CALLT_CFUNCS (r26)
-#endif
-#ifdef	L_callt_save_27c
-	MAKE_CALLT_CFUNCS (r27)
-#endif
-#ifdef	L_callt_save_28c
-	MAKE_CALLT_CFUNCS (r28)
-#endif
-#ifdef	L_callt_save_29c
-	MAKE_CALLT_CFUNCS (r29)
-#endif
-
-	
-#ifdef	L_callt_save_31c
-	.call_table_text
-	.align	2
-	/* Allocate space and save register r31 on the stack */
-	/* Called via:	callt ctoff(__callt_save_r31c). */
-.L_callt_save_r31c:
-	prepare {r31}, 4
-	ctret
-
-	/* Restore saved registers, deallocate stack and return */
-	/* Called via:	callt ctoff(__return_r31c) */
-	.align	2
-.L_callt_return_r31c:
-	dispose 4, {r31}, r31
-	
-	/* Place the offsets of the start of these funcs into the call table. */
-	.call_table_data
-
-	.global	__callt_save_r31c
-	.type	__callt_save_r31c,@function
-__callt_save_r31c:	.short ctoff(.L_callt_save_r31c)
-
-	.global	__callt_return_r31c
-	.type	__callt_return_r31c,@function
-__callt_return_r31c:	.short ctoff(.L_callt_return_r31c)		
-#endif
-
-#endif /* __v850e__ or __v850ea__ */
-/* END CYGNUS LOCAL */
diff --git a/gcc/config/v850/t-v850 b/gcc/config/v850/t-v850
deleted file mode 100755
index eb0bb3b..0000000
--- a/gcc/config/v850/t-v850
+++ /dev/null
@@ -1,120 +0,0 @@
-CROSS_LIBGCC1 = libgcc1-asm.a
-LIB1ASMSRC = v850/lib1funcs.asm
-LIB1ASMFUNCS	= _mulsi3 \
-		  _divsi3 \
-		  _udivsi3 \
-		  _modsi3 \
-		  _umodsi3 \
-		  _save_2 \
-		  _save_20 \
-		  _save_21 \
-		  _save_22 \
-		  _save_23 \
-		  _save_24 \
-		  _save_25 \
-		  _save_26 \
-		  _save_27 \
-		  _save_28 \
-		  _save_29 \
-		  _save_2c \
-		  _save_20c \
-		  _save_21c \
-		  _save_22c \
-		  _save_23c \
-		  _save_24c \
-		  _save_25c \
-		  _save_26c \
-		  _save_27c \
-		  _save_28c \
-		  _save_29c \
-		  _save_31c \
-		  _save_varargs \
-		  _save_interrupt \
-		  _save_all_interrupt
-
-# CYGNUS LOCAL v850e
-
-LIB1ASMFUNCS	= _mulsi3 \
-		  _divsi3 \
-		  _udivsi3 \
-		  _modsi3 \
-		  _umodsi3 \
-		  _save_2 \
-		  _save_20 \
-		  _save_21 \
-		  _save_22 \
-		  _save_23 \
-		  _save_24 \
-		  _save_25 \
-		  _save_26 \
-		  _save_27 \
-		  _save_28 \
-		  _save_29 \
-		  _save_2c \
-		  _save_20c \
-		  _save_21c \
-		  _save_22c \
-		  _save_23c \
-		  _save_24c \
-		  _save_25c \
-		  _save_26c \
-		  _save_27c \
-		  _save_28c \
-		  _save_29c \
-		  _save_31c \
-		  _save_varargs \
-		  _save_interrupt \
-		  _callt_save_20 \
-		  _callt_save_21 \
-		  _callt_save_22 \
-		  _callt_save_23 \
-		  _callt_save_24 \
-		  _callt_save_25 \
-		  _callt_save_26 \
-		  _callt_save_27 \
-		  _callt_save_28 \
-		  _callt_save_29 \
-		  _callt_save_20c \
-		  _callt_save_21c \
-		  _callt_save_22c \
-		  _callt_save_23c \
-		  _callt_save_24c \
-		  _callt_save_25c \
-		  _callt_save_26c \
-		  _callt_save_27c \
-		  _callt_save_28c \
-		  _callt_save_29c \
-		  _callt_save_31c \
-		  _callt_save_varargs \
-		  _callt_save_interrupt \
-		  _callt_save_all_interrupt \
-		  _callt_save_r2_r29 \
-		  _callt_save_r2_r31 \
-		  _callt_save_r6_r9  \
-		  _save_all_interrupt
-# END CYGNUS LOCAL
-	
-
-# These are really part of libgcc1, but this will cause them to be
-# built correctly, so...
-
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#ifdef __LITTLE_ENDIAN__' > dp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>dp-bit.c
-	echo '#endif' 		>> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#ifdef __LITTLE_ENDIAN__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>fp-bit.c
-	echo '#endif' 		>> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-TCFLAGS = -Wa,-mwarn-signed-overflow -Wa,-mwarn-unsigned-overflow
-# CYGNUS LOCAL v850e
-# Create non-target specific versions of the libraries
-TCFLAGS = -mno-app-regs -msmall-sld -mv850 -D__v850e__ -Wa,-mv850any -Wa,-mwarn-signed-overflow -Wa,-mwarn-unsigned-overflow
-# END CYGNUS LOCAL
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
deleted file mode 100755
index 60cb9e1..0000000
--- a/gcc/config/v850/v850.c
+++ /dev/null
@@ -1,3673 +0,0 @@
-/* Subroutines for insn-output.c for NEC V850 series
-   Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-   Contributed by Jeff Law (law@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <stdio.h>
-#include <ctype.h>
-#include "config.h"
-#include "tree.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "flags.h"
-#include "recog.h"
-#include "expr.h"
-#include "obstack.h"
-#include "toplev.h"
-
-#ifndef streq
-#define streq(a,b) (strcmp (a, b) == 0)
-#endif
-
-/* Function prototypes that cannot exist in v850.h due to dependency
-   compilcations.  */
-extern rtx    function_arg
-  PROTO ((CUMULATIVE_ARGS *, enum machine_mode, tree, int));
-extern int    function_arg_partial_nregs
-  PROTO ((CUMULATIVE_ARGS *, enum machine_mode, tree, int));
-extern void   asm_file_start                PROTO ((FILE *));
-extern void   print_operand                 PROTO ((FILE *, rtx, int ));
-extern void   print_operand_address         PROTO ((FILE *, rtx));
-extern void   v850_output_aligned_bss
-  PROTO ((FILE *, tree, char *, int, int));
-extern void   v850_output_common
-  PROTO ((FILE *, tree, char *, int, int));
-extern void   v850_output_local
-  PROTO ((FILE *, tree, char *, int, int));
-extern int    const_costs                   PROTO ((rtx, enum rtx_code));
-extern char * output_move_double            PROTO ((rtx *));
-extern char * output_move_single            PROTO ((rtx *));
-extern int    ep_memory_operand
-  PROTO ((rtx, enum machine_mode, int));
-extern int    reg_or_0_operand              PROTO ((rtx, enum machine_mode));
-extern int    reg_or_int5_operand           PROTO ((rtx, enum machine_mode));
-extern int    call_address_operand          PROTO ((rtx, enum machine_mode));
-extern int    movsi_source_operand          PROTO ((rtx, enum machine_mode));
-extern int    power_of_two_operand          PROTO ((rtx, enum machine_mode));
-extern int    not_power_of_two_operand      PROTO ((rtx, enum machine_mode));
-extern int    special_symbolref_operand     PROTO ((rtx, enum machine_mode));
-extern void   v850_reorg                    PROTO ((rtx));
-extern void   notice_update_cc              PROTO ((rtx, rtx));
-extern int    v850_valid_machine_decl_attribute
-  PROTO ((tree, tree, tree));
-extern int    v850_interrupt_function_p     PROTO ((tree));
-extern int    pattern_is_ok_for_prologue    PROTO ((rtx, enum machine_mode));
-extern int    pattern_is_ok_for_epilogue    PROTO ((rtx, enum machine_mode));
-extern int    register_is_ok_for_epilogue   PROTO ((rtx, enum machine_mode));
-extern char * construct_save_jarl           PROTO ((rtx));
-extern char * construct_restore_jr          PROTO ((rtx));
-extern void   v850_encode_data_area         PROTO ((tree));
-extern void   v850_set_default_decl_attr    PROTO ((tree));
-
-/* Function prototypes for stupid compilers:  */
-static void const_double_split
-  PROTO ((rtx, HOST_WIDE_INT *, HOST_WIDE_INT *));
-static int  const_costs_int        PROTO ((HOST_WIDE_INT, int));
-static void substitute_ep_register PROTO ((rtx, rtx, int, int, rtx *, rtx *));
-static int  push_data_area         PROTO ((v850_data_area));
-static int  pop_data_area          PROTO ((v850_data_area));
-static int  parse_ghs_pragma_token PROTO ((char *));
-static int  ep_memory_offset       PROTO ((enum machine_mode, int));
-static int  mark_current_function_as_interrupt PROTO ((void));
-static void v850_set_data_area     PROTO ((tree, v850_data_area));
-/* CYGNUS LOCAL v850e */
-extern int    pattern_is_ok_for_prepare     PROTO ((rtx, enum machine_mode));
-extern int    pattern_is_ok_for_dispose     PROTO ((rtx, enum machine_mode));
-extern char * construct_dispose_instruction PROTO ((rtx));
-extern char * construct_prepare_instruction PROTO ((rtx));
-/* END CYGNUS LOCAL */
-
-/* True if the current function has anonymous arguments.  */
-int current_function_anonymous_args;
-
-/* Information about the various small memory areas.  */
-struct small_memory_info small_memory[ (int)SMALL_MEMORY_max ] =
-{
-  /* name	value		max		physical max */
-  { "tda",	(char *)0,	0,		256 },
-  { "sda",	(char *)0,	0,		65536 },
-  { "zda",	(char *)0,	0,		32768 },
-};
-
-/* True if we don't need to check any more if the current
-   function is an interrupt handler */
-static int v850_interrupt_cache_p = FALSE;
-
-/* Whether current function is an interrupt handler.  */
-static int v850_interrupt_p = FALSE;
-
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-
-void
-override_options ()
-{
-  int i;
-  extern int atoi PROTO ((const char *));
-
-  /* Parse -m{s,t,z}da=nnn switches */
-  for (i = 0; i < (int)SMALL_MEMORY_max; i++)
-    {
-      if (small_memory[i].value)
-	{
-	  if (!isdigit (*small_memory[i].value))
-	    error ("%s=%s is not numeric.",
-		   small_memory[i].name,
-		   small_memory[i].value);
-	  else
-	    {
-	      small_memory[i].max = atoi (small_memory[i].value);
-	      if (small_memory[i].max > small_memory[i].physical_max)
-		error ("%s=%s is too large.",
-		   small_memory[i].name,
-		   small_memory[i].value);
-	    }
-	}
-    }
-/* CYGNUS LOCAL v850e */
-#ifdef MASK_US_BIT_SET
-  /* Make sure that the US_BIT_SET mask has been correctly initialised.  */
-  if ((target_flags & MASK_US_MASK_SET) == 0)
-    {
-      if (TARGET_V850EA)
-	target_flags |= (MASK_US_MASK_SET | MASK_US_BIT_SET);
-      else
-	{
-	  target_flags |= MASK_US_MASK_SET;
-	  target_flags &= ~MASK_US_BIT_SET;
-	}
-    }
-#endif
-/* END CYGNUS LOCAL */
-}
-
-
-/* Output assembly code for the start of the file.  */
-
-void
-asm_file_start (file)
-     FILE *file;
-{
-  output_file_directive (file, main_input_filename);
-}
-
-
-/* Return an RTX to represent where a value with mode MODE will be returned
-   from a function.  If the result is 0, the argument is pushed.  */
-
-rtx
-function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  rtx result = 0;
-  int size, align;
-
-  if (TARGET_GHS && !named)
-    return NULL_RTX;
-
-  if (mode == BLKmode)
-    size = int_size_in_bytes (type);
-  else
-    size = GET_MODE_SIZE (mode);
-
-  if (type)
-    align = TYPE_ALIGN (type) / BITS_PER_UNIT;
-  else
-    align = size;
-
-  cum->nbytes = (cum->nbytes + align - 1) &~(align - 1);
-
-  if (cum->nbytes > 4 * UNITS_PER_WORD)
-    return 0;
-
-  if (type == NULL_TREE
-      && cum->nbytes + size > 4 * UNITS_PER_WORD)
-    return 0;
-
-  switch (cum->nbytes / UNITS_PER_WORD)
-    {
-    case 0:
-      result = gen_rtx (REG, mode, 6);
-      break;
-    case 1:
-      result = gen_rtx (REG, mode, 7);
-      break;
-    case 2:
-      result = gen_rtx (REG, mode, 8);
-      break;
-    case 3:
-      result = gen_rtx (REG, mode, 9);
-      break;
-    default:
-      result = 0;
-    }
-
-  return result;
-}
-
-
-/* Return the number of words which must be put into registers
-   for values which are part in registers and part in memory.  */
-
-int
-function_arg_partial_nregs (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int size, align;
-
-  if (TARGET_GHS && !named)
-    return 0;
-
-  if (mode == BLKmode)
-    size = int_size_in_bytes (type);
-  else
-    size = GET_MODE_SIZE (mode);
-
-  if (type)
-    align = TYPE_ALIGN (type) / BITS_PER_UNIT;
-  else
-    align = size;
-
-  cum->nbytes = (cum->nbytes + align - 1) &~(align - 1);
-
-  if (cum->nbytes > 4 * UNITS_PER_WORD)
-    return 0;
-
-  if (cum->nbytes + size <= 4 * UNITS_PER_WORD)
-    return 0;
-
-  if (type == NULL_TREE
-      && cum->nbytes + size > 4 * UNITS_PER_WORD)
-    return 0;
-
-  return (4 * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
-}
-
-
-/* Return the high and low words of a CONST_DOUBLE */
-
-static void
-const_double_split (x, p_high, p_low)
-     rtx x;
-     HOST_WIDE_INT *p_high;
-     HOST_WIDE_INT *p_low;
-{
-  if (GET_CODE (x) == CONST_DOUBLE)
-    {
-      long t[2];
-      REAL_VALUE_TYPE rv;
-
-      switch (GET_MODE (x))
-	{
-	case DFmode:
-	  REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-	  REAL_VALUE_TO_TARGET_DOUBLE (rv, t);
-	  *p_high = t[1];	/* since v850 is little endian */
-	  *p_low = t[0];	/* high is second word */
-	  return;
-
-	case SFmode:
-	  REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
-	  REAL_VALUE_TO_TARGET_SINGLE (rv, *p_high);
-	  *p_low = 0;
-	  return;
-
-	case VOIDmode:
-	case DImode:
-	  *p_high = CONST_DOUBLE_HIGH (x);
-	  *p_low  = CONST_DOUBLE_LOW (x);
-	  return;
-
-	default:
-	  break;
-	}
-    }
-
-  fatal_insn ("const_double_split got a bad insn:", x);
-}
-
-
-/* Return the cost of the rtx R with code CODE.  */
-
-static int
-const_costs_int (value, zero_cost)
-     HOST_WIDE_INT value;
-     int zero_cost;
-{
-  if (CONST_OK_FOR_I (value))
-      return zero_cost;
-  else if (CONST_OK_FOR_J (value))
-    return 1;
-  else if (CONST_OK_FOR_K (value))
-    return 2;
-  else
-    return 4;
-}
-
-int
-const_costs (r, c)
-     rtx r;
-     enum rtx_code c;
-{
-  HOST_WIDE_INT high, low;
-
-  switch (c)
-    {
-    case CONST_INT:
-      return const_costs_int (INTVAL (r), 0);
-
-    case CONST_DOUBLE:
-      const_double_split (r, &high, &low);
-      if (GET_MODE (r) == SFmode)
-	return const_costs_int (high, 1);
-      else
-	return const_costs_int (high, 1) + const_costs_int (low, 1);
-
-    case SYMBOL_REF:
-    case LABEL_REF:
-    case CONST:
-      return 2;
-
-    case HIGH:
-      return 1;
-
-    default:
-      return 4;
-    }
-}
-
-
-/* Print operand X using operand code CODE to assembly language output file
-   FILE.  */
-
-void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
-{
-  HOST_WIDE_INT high, low;
-
-  switch (code)
-    {
-    case 'c':
-      /* We use 'c' operands with symbols for .vtinherit */
-      if (GET_CODE (x) == SYMBOL_REF)
-        {
-          output_addr_const(file, x);
-          break;
-        }
-      /* fall through */
-    case 'b':
-    case 'B':
-    case 'C':
-      switch ((code == 'B' || code == 'C')
-	      ? reverse_condition (GET_CODE (x)) : GET_CODE (x))
-	{
-	  case NE:
-	    if (code == 'c' || code == 'C')
-	      fprintf (file, "nz");
-	    else
-	      fprintf (file, "ne");
-	    break;
-	  case EQ:
-	    if (code == 'c' || code == 'C')
-	      fprintf (file, "z");
-	    else
-	      fprintf (file, "e");
-	    break;
-	  case GE:
-	    fprintf (file, "ge");
-	    break;
-	  case GT:
-	    fprintf (file, "gt");
-	    break;
-	  case LE:
-	    fprintf (file, "le");
-	    break;
-	  case LT:
-	    fprintf (file, "lt");
-	    break;
-	  case GEU:
-	    fprintf (file, "nl");
-	    break;
-	  case GTU:
-	    fprintf (file, "h");
-	    break;
-	  case LEU:
-	    fprintf (file, "nh");
-	    break;
-	  case LTU:
-	    fprintf (file, "l");
-	    break;
-	  default:
-	    abort ();
-	}
-      break;
-    case 'F':			/* high word of CONST_DOUBLE */
-      if (GET_CODE (x) == CONST_INT)
-	fprintf (file, "%d", (INTVAL (x) >= 0) ? 0 : -1);
-      else if (GET_CODE (x) == CONST_DOUBLE)
-	{
-	  const_double_split (x, &high, &low);
-	  fprintf (file, "%ld", (long) high);
-	}
-      else
-	abort ();
-      break;
-    case 'G':			/* low word of CONST_DOUBLE */
-      if (GET_CODE (x) == CONST_INT)
-	fprintf (file, "%ld", (long) INTVAL (x));
-      else if (GET_CODE (x) == CONST_DOUBLE)
-	{
-	  const_double_split (x, &high, &low);
-	  fprintf (file, "%ld", (long) low);
-	}
-      else
-	abort ();
-      break;
-    case 'L':
-      fprintf (file, "%d\n", INTVAL (x) & 0xffff);
-      break;
-    case 'M':
-      fprintf (file, "%d", exact_log2 (INTVAL (x)));
-      break;
-    case 'O':
-      if (special_symbolref_operand (x, VOIDmode))
-        {
-          char* name;
-
-	  if (GET_CODE (x) == SYMBOL_REF)
-	    name = XSTR (x, 0);
-	  else if (GET_CODE (x) == CONST)
-	    name = XSTR (XEXP (XEXP (x, 0), 0), 0);
-	  else
-	    abort ();
-
-          if (ZDA_NAME_P (name))
-            fprintf (file, "zdaoff");
-          else if (SDA_NAME_P (name))
-            fprintf (file, "sdaoff");
-          else if (TDA_NAME_P (name))
-            fprintf (file, "tdaoff");
-          else
-            abort ();
-        }
-      else
-        abort ();
-      break;
-    case 'P':
-      if (special_symbolref_operand (x, VOIDmode))
-        output_addr_const (file, x);
-      else
-        abort ();
-      break;
-    case 'Q':
-      if (special_symbolref_operand (x, VOIDmode))
-        {
-          char* name;
-
-	  if (GET_CODE (x) == SYMBOL_REF)
-	    name = XSTR (x, 0);
-	  else if (GET_CODE (x) == CONST)
-	    name = XSTR (XEXP (XEXP (x, 0), 0), 0);
-	  else
-	    abort ();
-
-          if (ZDA_NAME_P (name))
-            fprintf (file, "r0");
-          else if (SDA_NAME_P (name))
-            fprintf (file, "gp");
-          else if (TDA_NAME_P (name))
-            fprintf (file, "ep");
-          else
-            abort ();
-        }
-      else
-        abort ();
-      break;
-    case 'R':		/* 2nd word of a double.  */
-      switch (GET_CODE (x))
-	{
-	case REG:
-	  fprintf (file, reg_names[REGNO (x) + 1]);
-	  break;
-	case MEM:
-	  print_operand_address (file,
-				 XEXP (adj_offsettable_operand (x, 4), 0));
-	  break;
-	  
-	default:
-	  break;
-	}
-      break;
-    case 'S':
-      {
-        /* if it's a reference to a TDA variable, use sst/sld vs. st/ld */
-        if (GET_CODE (x) == MEM && ep_memory_operand (x, GET_MODE (x), FALSE))
-          fputs ("s", file);
-
-        break;
-      }
-    case 'T':
-      {
-	/* Like an 'S' operand above, but for unsigned loads only.  */
-        if (GET_CODE (x) == MEM && ep_memory_operand (x, GET_MODE (x), TRUE))
-          fputs ("s", file);
-
-        break;
-      }
-    case 'W':			/* print the instruction suffix */
-      switch (GET_MODE (x))
-	{
-	default:
-	  abort ();
-
-	case QImode: fputs (".b", file); break;
-	case HImode: fputs (".h", file); break;
-	case SImode: fputs (".w", file); break;
-	case SFmode: fputs (".w", file); break;
-	}
-      break;
-    case '.':			/* register r0 */
-      fputs (reg_names[0], file);
-      break;
-    case 'z':			/* reg or zero */
-      if (x == const0_rtx)
-	fputs (reg_names[0], file);
-      else if (GET_CODE (x) == REG)
-	fputs (reg_names[REGNO (x)], file);
-      else
-	abort ();
-      break;
-    default:
-      switch (GET_CODE (x))
-	{
-	case MEM:
-	  if (GET_CODE (XEXP (x, 0)) == CONST_INT)
-	    output_address (gen_rtx (PLUS, SImode,
-				     gen_rtx (REG, SImode, 0),
-				     XEXP (x, 0)));
-	  else
-	    output_address (XEXP (x, 0));
-	  break;
-
-	case REG:
-	  fputs (reg_names[REGNO (x)], file);
-	  break;
-	case SUBREG:
-	  fputs (reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)], file);
-	  break;
-	case CONST_INT:
-	case SYMBOL_REF:
-	case CONST:
-	case LABEL_REF:
-	case CODE_LABEL:
-	  print_operand_address (file, x);
-	  break;
-	default:
-	  abort ();
-	}
-      break;
-
-    }
-}
-
-
-/* Output assembly language output for the address ADDR to FILE.  */
-
-void
-print_operand_address (file, addr)
-     FILE *file;
-     rtx addr;
-{
-  switch (GET_CODE (addr))
-    {
-    case REG:
-      fprintf (file, "0[");
-      print_operand (file, addr, 0);
-      fprintf (file, "]");
-      break;
-    case LO_SUM:
-      if (GET_CODE (XEXP (addr, 0)) == REG)
-	{
-	  /* reg,foo */
-	  fprintf (file, "lo(");
-	  print_operand (file, XEXP (addr, 1), 0);
-	  fprintf (file, ")[");
-	  print_operand (file, XEXP (addr, 0), 0);
-	  fprintf (file, "]");
-	}
-      break;
-    case PLUS:
-      if (GET_CODE (XEXP (addr, 0)) == REG
-	  || GET_CODE (XEXP (addr, 0)) == SUBREG)
-	{
-	  /* reg,foo */
-	  print_operand (file, XEXP (addr, 1), 0);
-	  fprintf (file, "[");
-	  print_operand (file, XEXP (addr, 0), 0);
-	  fprintf (file, "]");
-	}
-      else
-	{
-	  print_operand (file, XEXP (addr, 0), 0);
-	  fprintf (file, "+");
-	  print_operand (file, XEXP (addr, 1), 0);
-	}
-      break;
-    case SYMBOL_REF:
-      if (ENCODED_NAME_P (XSTR (addr, 0)))
-        {
-          char* name = XSTR (addr, 0);
-          char* off_name;
-          char* reg_name;
-
-          if (ZDA_NAME_P (name))
-            {
-              off_name = "zdaoff";
-              reg_name = "r0";
-            }
-          else if (SDA_NAME_P (name))
-            {
-              off_name = "sdaoff";
-              reg_name = "gp";
-            }
-          else if (TDA_NAME_P (name))
-            {
-              off_name = "tdaoff";
-              reg_name = "ep";
-            }
-          else
-            abort ();
-
-          fprintf (file, "%s(", off_name);
-          output_addr_const (file, addr);
-          fprintf (file, ")[%s]", reg_name);
-        }
-      else
-        output_addr_const (file, addr);
-      break;
-    case CONST:
-      if (special_symbolref_operand (addr, VOIDmode))
-        {
-          char* name = XSTR (XEXP (XEXP (addr, 0), 0), 0);
-          char* off_name;
-          char* reg_name;
-
-          if (ZDA_NAME_P (name))
-            {
-              off_name = "zdaoff";
-              reg_name = "r0";
-            }
-          else if (SDA_NAME_P (name))
-            {
-              off_name = "sdaoff";
-              reg_name = "gp";
-            }
-          else if (TDA_NAME_P (name))
-            {
-              off_name = "tdaoff";
-              reg_name = "ep";
-            }
-          else
-            abort ();
-
-          fprintf (file, "%s(", off_name);
-          output_addr_const (file, addr);
-          fprintf (file, ")[%s]", reg_name);
-        }
-      else
-        output_addr_const (file, addr);
-      break;
-    default:
-      output_addr_const (file, addr);
-      break;
-    }
-}
-
-
-/* Return appropriate code to load up a 1, 2, or 4 integer/floating
-   point value.  */
-
-char *
-output_move_single (operands)
-     rtx *operands;
-{
-  rtx dst = operands[0];
-  rtx src = operands[1];
-
-  if (REG_P (dst))
-    {
-      if (REG_P (src))
-	return "mov %1,%0";
-
-      else if (GET_CODE (src) == CONST_INT)
-	{
-	  HOST_WIDE_INT value = INTVAL (src);
-
-	  if (CONST_OK_FOR_J (value))		/* signed 5 bit immediate */
-	    return "mov %1,%0";
-
-	  else if (CONST_OK_FOR_K (value))	/* signed 16 bit immediate */
-	    return "movea lo(%1),%.,%0";
-
-	  else if (CONST_OK_FOR_L (value))	/* upper 16 bits were set */
-	    return "movhi hi(%1),%.,%0";
-
-	  else					/* random constant */
-/* CYGNUS LOCAL v850e */
-	    if (TARGET_V850E)
-	      return  "mov %1,%0";
-	  else
-/* END CYGNUS LOCAL */
-	    return "movhi hi(%1),%.,%0\n\tmovea lo(%1),%0,%0";
-	}
-
-      else if (GET_CODE (src) == CONST_DOUBLE && GET_MODE (src) == SFmode)
-	{
-	  HOST_WIDE_INT high, low;
-
-	  const_double_split (src, &high, &low);
-	  if (CONST_OK_FOR_J (high))		/* signed 5 bit immediate */
-	    return "mov %F1,%0";
-
-	  else if (CONST_OK_FOR_K (high))	/* signed 16 bit immediate */
-	    return "movea lo(%F1),%.,%0";
-
-	  else if (CONST_OK_FOR_L (high))	/* upper 16 bits were set */
-	    return "movhi hi(%F1),%.,%0";
-
-	  else					/* random constant */
-/* CYGNUS LOCAL v850e */
-	    if (TARGET_V850E)
-	      return  "mov %F1,%0";
-	  else
-/* END CYGNUS LOCAL */
-	    return "movhi hi(%F1),%.,%0\n\tmovea lo(%F1),%0,%0";
-	}
-
-      else if (GET_CODE (src) == MEM)
-	return "%S1ld%W1 %1,%0";
-
-      else if (special_symbolref_operand (src, VOIDmode))
-	return "movea %O1(%P1),%Q1,%0";
-
-      else if (GET_CODE (src) == LABEL_REF
-	       || GET_CODE (src) == SYMBOL_REF
-	       || GET_CODE (src) == CONST)
-	{
-/* CYGNUS LOCAL v850e */
-	  if (TARGET_V850E)
-	    return "mov hilo(%1),%0";
-	  else
-/* END CYGNUS LOCAL */
-	  return "movhi hi(%1),%.,%0\n\tmovea lo(%1),%0,%0";
-	}
-
-      else if (GET_CODE (src) == HIGH)
-	return "movhi hi(%1),%.,%0";
-
-      else if (GET_CODE (src) == LO_SUM)
-	{
-	  operands[2] = XEXP (src, 0);
-	  operands[3] = XEXP (src, 1);
-	  return "movea lo(%3),%2,%0";
-	}
-    }
-
-  else if (GET_CODE (dst) == MEM)
-    {
-      if (REG_P (src))
-	return "%S0st%W0 %1,%0";
-
-      else if (GET_CODE (src) == CONST_INT && INTVAL (src) == 0)
-	return "%S0st%W0 %.,%0";
-
-      else if (GET_CODE (src) == CONST_DOUBLE
-	       && CONST0_RTX (GET_MODE (dst)) == src)
-	return "%S0st%W0 %.,%0";
-    }
-
-  fatal_insn ("output_move_single:", gen_rtx (SET, VOIDmode, dst, src));
-  return "";
-}
-
-
-/* Return appropriate code to load up an 8 byte integer or
-   floating point value */
-
-char *
-output_move_double (operands)
-    rtx *operands;
-{
-  enum machine_mode mode = GET_MODE (operands[0]);
-  rtx dst = operands[0];
-  rtx src = operands[1];
-
-  if (register_operand (dst, mode)
-      && register_operand (src, mode))
-    {
-      if (REGNO (src) + 1 == REGNO (dst))
-	return "mov %R1,%R0\n\tmov %1,%0";
-      else
-	return "mov %1,%0\n\tmov %R1,%R0";
-    }
-
-  /* Storing 0 */
-  if (GET_CODE (dst) == MEM
-      && ((GET_CODE (src) == CONST_INT && INTVAL (src) == 0)
-	  || (GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src))))
-    return "st.w %.,%0\n\tst.w %.,%R0";
-
-  if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
-    {
-      HOST_WIDE_INT high_low[2];
-      int i;
-      rtx xop[10];
-
-      if (GET_CODE (src) == CONST_DOUBLE)
-	const_double_split (src, &high_low[1], &high_low[0]);
-      else
-	{
-	  high_low[0] = INTVAL (src);
-	  high_low[1] = (INTVAL (src) >= 0) ? 0 : -1;
-	}
-
-      for (i = 0; i < 2; i++)
-	{
-	  xop[0] = gen_rtx (REG, SImode, REGNO (dst)+i);
-	  xop[1] = GEN_INT (high_low[i]);
-	  output_asm_insn (output_move_single (xop), xop);
-	}
-
-      return "";
-    }
-
-  if (GET_CODE (src) == MEM)
-    {
-      int ptrreg = -1;
-      int dreg = REGNO (dst);
-      rtx inside = XEXP (src, 0);
-
-      if (GET_CODE (inside) == REG)
- 	ptrreg = REGNO (inside);
-      else if (GET_CODE (inside) == SUBREG)
-	ptrreg = REGNO (SUBREG_REG (inside)) + SUBREG_WORD (inside);
-      else if (GET_CODE (inside) == PLUS)
-	ptrreg = REGNO (XEXP (inside, 0));
-      else if (GET_CODE (inside) == LO_SUM)
-	ptrreg = REGNO (XEXP (inside, 0));
-
-      if (dreg == ptrreg)
-	return "ld.w %R1,%R0\n\tld.w %1,%0";
-    }
-
-  if (GET_CODE (src) == MEM)
-    return "ld.w %1,%0\n\tld.w %R1,%R0";
-  
-  if (GET_CODE (dst) == MEM)
-    return "st.w %1,%0\n\tst.w %R1,%R0";
-
-  return "mov %1,%0\n\tmov %R1,%R0";
-}
-
-
-/* Return maximum offset supported for a short EP memory reference of mode
-   MODE and signedness UNSIGNEDP.  */
-
-static int
-ep_memory_offset (mode, unsignedp)
-     enum machine_mode mode;
-     int ATTRIBUTE_UNUSED unsignedp;
-{
-  int max_offset = 0;
-
-  switch (mode)
-    {
-    case QImode:
-/* CYGNUS LOCAL v850e */
-      if (TARGET_SMALL_SLD)
-	{
-	  max_offset = (1 << 4);
-	  break;
-	}
-/* END CYGNUS LOCAL */
-      max_offset = (1 << 7);
-      
-/* CYGNUS LOCAL v850e */
-#ifdef TARGET_US_BIT_SET
-      if (TARGET_V850E 
-	  && (   (  unsignedp && ! TARGET_US_BIT_SET)
-	      || (! unsignedp &&   TARGET_US_BIT_SET)))
-	max_offset = (1 << 4);
-#else
-      if (TARGET_V850E && unsignedp)
-	max_offset = (1 << 4);
-#endif
-/* END CYGNUS LOCAL */
-      break;
-
-    case HImode:
-/* CYGNUS LOCAL v850e */
-      if (TARGET_SMALL_SLD)
-	{
-	  max_offset = (1 << 5);
-	  break;
-	}
-/* END CYGNUS LOCAL v850e */
-      max_offset = (1 << 8);
-      
-/* CYGNUS LOCAL v850e */
-#ifdef TARGET_US_BIT_SET
-      if (TARGET_V850E
-	  && ((  unsignedp && ! TARGET_US_BIT_SET)
-	      || (! unsignedp &&   TARGET_US_BIT_SET)))
-	max_offset = (1 << 5);
-#else
-      if (TARGET_V850E && unsignedp)
-	max_offset = (1 << 5);
-#endif
-/* END CYGNUS LOCAL */
-      break;
-
-    case SImode:
-    case SFmode:
-      max_offset = (1 << 8);
-      break;
-      
-    default:
-      break;
-    }
-
-  return max_offset;
-}
-
-/* Return true if OP is a valid short EP memory reference */
-
-int
-ep_memory_operand (op, mode, unsigned_load)
-     rtx op;
-     enum machine_mode mode;
-     int unsigned_load;
-{
-  rtx addr, op0, op1;
-  int max_offset;
-  int mask;
-
-  if (GET_CODE (op) != MEM)
-    return FALSE;
-
-  max_offset = ep_memory_offset (mode, unsigned_load);
-
-  mask = GET_MODE_SIZE (mode) - 1;
-
-  addr = XEXP (op, 0);
-  if (GET_CODE (addr) == CONST)
-    addr = XEXP (addr, 0);
-
-  switch (GET_CODE (addr))
-    {
-    default:
-      break;
-
-    case SYMBOL_REF:
-      return TDA_NAME_P (XSTR (addr, 0));
-
-    case REG:
-      return REGNO (addr) == EP_REGNUM;
-
-    case PLUS:
-      op0 = XEXP (addr, 0);
-      op1 = XEXP (addr, 1);
-      if (GET_CODE (op1) == CONST_INT
-	  && INTVAL (op1) < max_offset
-	  && INTVAL (op1) >= 0
-	  && (INTVAL (op1) & mask) == 0)
-	{
-	  if (GET_CODE (op0) == REG && REGNO (op0) == EP_REGNUM)
-	    return TRUE;
-
-	  if (GET_CODE (op0) == SYMBOL_REF && TDA_NAME_P (XSTR (op0, 0)))
-	    return TRUE;
-	}
-      break;
-    }
-
-  return FALSE;
-}
-
-/* Return true if OP is either a register or 0 */
-
-int
-reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return INTVAL (op) == 0;
-
-  else if (GET_CODE (op) == CONST_DOUBLE)
-    return CONST_DOUBLE_OK_FOR_G (op);
-
-  else
-    return register_operand (op, mode);
-}
-
-/* Return true if OP is either a register or a signed five bit integer */
-
-int
-reg_or_int5_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return CONST_OK_FOR_J (INTVAL (op));
-
-  else
-    return register_operand (op, mode);
-}
-
-/* Return true if OP is a valid call operand.  */
-
-int
-call_address_operand (op, mode)
-     rtx op;
-     enum machine_mode ATTRIBUTE_UNUSED mode;
-{
-  /* Only registers are valid call operands if TARGET_LONG_CALLS.  */
-  if (TARGET_LONG_CALLS)
-    return GET_CODE (op) == REG;
-  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
-}
-
-int
-special_symbolref_operand (op, mode)
-     rtx op;
-     enum machine_mode ATTRIBUTE_UNUSED mode;
-{
-  if (GET_CODE (op) == SYMBOL_REF)
-    return ENCODED_NAME_P (XSTR (op, 0));
-
-  else if (GET_CODE (op) == CONST)
-    return (GET_CODE (XEXP (op, 0)) == PLUS
-	    && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
-	    && ENCODED_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0))
-	    && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
-	    && CONST_OK_FOR_K (INTVAL (XEXP (XEXP (op, 0), 1))));
-
-  return FALSE;
-}
-
-int
-movsi_source_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  /* Some constants, as well as symbolic operands
-     must be done with HIGH & LO_SUM patterns.  */
-  if (CONSTANT_P (op)
-      && GET_CODE (op) != HIGH
-      && GET_CODE (op) != CONSTANT_P_RTX
-      && !(GET_CODE (op) == CONST_INT
-           && (CONST_OK_FOR_J (INTVAL (op))
-               || CONST_OK_FOR_K (INTVAL (op))
-               || CONST_OK_FOR_L (INTVAL (op)))))
-    return special_symbolref_operand (op, mode);
-  else
-    return general_operand (op, mode);
-}
-
-int
-power_of_two_operand (op, mode)
-     rtx op;
-     enum machine_mode ATTRIBUTE_UNUSED mode;
-{
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-
-  if (exact_log2 (INTVAL (op)) == -1)
-    return 0;
-  return 1;
-}
-
-int
-not_power_of_two_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  unsigned int mask;
-
-  if (mode == QImode)
-    mask = 0xff;
-  else if (mode == HImode)
-    mask = 0xffff;
-  else if (mode == SImode)
-    mask = 0xffffffff; 
-  else
-    return 0;
-
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-
-  if (exact_log2 (~INTVAL (op) & mask) == -1)
-    return 0;
-  return 1;
-}
-
-
-/* Substitute memory references involving a pointer, to use the ep pointer,
-   taking care to save and preserve the ep.  */
-
-static void
-substitute_ep_register (first_insn, last_insn, uses, regno, p_r1, p_ep)
-     rtx first_insn;
-     rtx last_insn;
-     int uses;
-     int regno;
-     rtx *p_r1;
-     rtx *p_ep;
-{
-  rtx reg = gen_rtx (REG, Pmode, regno);
-  rtx insn;
-
-  if (!*p_r1)
-    {
-      regs_ever_live[1] = 1;
-      *p_r1 = gen_rtx (REG, Pmode, 1);
-      *p_ep = gen_rtx (REG, Pmode, 30);
-    }
-
-  if (TARGET_DEBUG)
-    fprintf (stderr, "\
-Saved %d bytes (%d uses of register %s) in function %s, starting as insn %d, ending at %d\n",
-	     2 * (uses - 3), uses, reg_names[regno],
-	     IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
-	     INSN_UID (first_insn), INSN_UID (last_insn));
-
-  if (GET_CODE (first_insn) == NOTE)
-    first_insn = next_nonnote_insn (first_insn);
-
-  last_insn = next_nonnote_insn (last_insn);
-  for (insn = first_insn; insn && insn != last_insn; insn = NEXT_INSN (insn))
-    {
-      if (GET_CODE (insn) == INSN)
-	{
-	  rtx pattern = single_set (insn);
-
-	  /* Replace the memory references.  */
-	  if (pattern)
-	    {
-	      rtx *p_mem;
-	      /* Memory operands are signed by default.  */
-	      int unsignedp = FALSE;
-
-	      if (GET_CODE (SET_DEST (pattern)) == MEM
-		  && GET_CODE (SET_SRC (pattern)) == MEM)
-		p_mem = (rtx *)0;
-
-	      else if (GET_CODE (SET_DEST (pattern)) == MEM)
-		p_mem = &SET_DEST (pattern);
-
-	      else if (GET_CODE (SET_SRC (pattern)) == MEM)
-		p_mem = &SET_SRC (pattern);
-
-	      /* CYGNUS LOCAL v850e */
-	      else if (GET_CODE (SET_SRC (pattern)) == SIGN_EXTEND
-		       && GET_CODE (XEXP (SET_SRC (pattern), 0)) == MEM)
-		p_mem = &XEXP (SET_SRC (pattern), 0);
-
-	      else if (GET_CODE (SET_SRC (pattern)) == ZERO_EXTEND
-		       && GET_CODE (XEXP (SET_SRC (pattern), 0)) == MEM)
-		{
-		  p_mem = &XEXP (SET_SRC (pattern), 0);
-		  unsignedp = TRUE;
-		}
-	      /* END CYGNUS LOCAL */
-
-	      else
-		p_mem = (rtx *)0;
-
-	      if (p_mem)
-		{
-		  rtx addr = XEXP (*p_mem, 0);
-
-		  if (GET_CODE (addr) == REG && REGNO (addr) == regno)
-		    *p_mem = change_address (*p_mem, VOIDmode, *p_ep);
-
-		  else if (GET_CODE (addr) == PLUS
-			   && GET_CODE (XEXP (addr, 0)) == REG
-			   && REGNO (XEXP (addr, 0)) == regno
-			   && GET_CODE (XEXP (addr, 1)) == CONST_INT
-			   && ((INTVAL (XEXP (addr, 1)))
-			       < ep_memory_offset (GET_MODE (*p_mem),
-						   unsignedp))
-			   && ((INTVAL (XEXP (addr, 1))) >= 0))
-		    *p_mem = change_address (*p_mem, VOIDmode,
-					     gen_rtx (PLUS, Pmode,
-						      *p_ep, XEXP (addr, 1)));
-		}
-	    }
-	}
-    }
-
-  /* Optimize back to back cases of ep <- r1 & r1 <- ep.  */
-  insn = prev_nonnote_insn (first_insn);
-  if (insn && GET_CODE (insn) == INSN
-      && GET_CODE (PATTERN (insn)) == SET
-      && SET_DEST (PATTERN (insn)) == *p_ep
-      && SET_SRC (PATTERN (insn)) == *p_r1)
-    delete_insn (insn);
-  else
-    emit_insn_before (gen_rtx (SET, Pmode, *p_r1, *p_ep), first_insn);
-
-  emit_insn_before (gen_rtx (SET, Pmode, *p_ep, reg), first_insn);
-  emit_insn_before (gen_rtx (SET, Pmode, *p_ep, *p_r1), last_insn);
-}
-
-
-/* In rare cases, correct code generation requires extra machine
-   dependent processing between the second jump optimization pass and
-   delayed branch scheduling.  On those machines, define this macro
-   as a C statement to act on the code starting at INSN.
-
-   On the 850, we use it to implement the -mep mode to copy heavily used
-   pointers to ep to use the implicit addressing */
-
-void v850_reorg (start_insn)
-     rtx start_insn;
-{
-  struct
-  {
-    int uses;
-    rtx first_insn;
-    rtx last_insn;
-  }
-  regs[FIRST_PSEUDO_REGISTER];
-
-  int i;
-  int use_ep = FALSE;
-  rtx r1 = NULL_RTX;
-  rtx ep = NULL_RTX;
-  rtx insn;
-  rtx pattern;
-
-  /* If not ep mode, just return now */
-  if (!TARGET_EP)
-    return;
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      regs[i].uses = 0;
-      regs[i].first_insn = NULL_RTX;
-      regs[i].last_insn = NULL_RTX;
-    }
-
-  for (insn = start_insn; insn != NULL_RTX; insn = NEXT_INSN (insn))
-    {
-      switch (GET_CODE (insn))
-	{
-	  /* End of basic block */
-	default:
-	  if (!use_ep)
-	    {
-	      int max_uses = -1;
-	      int max_regno = -1;
-
-	      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-		{
-		  if (max_uses < regs[i].uses)
-		    {
-		      max_uses = regs[i].uses;
-		      max_regno = i;
-		    }
-		}
-
-	      if (max_uses > 3)
-		substitute_ep_register (regs[max_regno].first_insn,
-					regs[max_regno].last_insn,
-					max_uses, max_regno, &r1, &ep);
-	    }
-
-	  use_ep = FALSE;
-	  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	    {
-	      regs[i].uses = 0;
-	      regs[i].first_insn = NULL_RTX;
-	      regs[i].last_insn = NULL_RTX;
-	    }
-	  break;
-
-	case NOTE:
-	  break;
-
-	case INSN:
-	  pattern = single_set (insn);
-
-	  /* See if there are any memory references we can shorten */
-	  if (pattern)
-	    {
-	      rtx src = SET_SRC (pattern);
-	      rtx dest = SET_DEST (pattern);
-	      rtx mem;
-	      /* Memory operands are signed by default.  */
-	      int unsignedp = FALSE;
-
-	      /* We might have (SUBREG (MEM)) here, so just get rid of the
-		 subregs to make this code simpler.  It is safe to call
-		 alter_subreg any time after reload.  */
-	      if (GET_CODE (dest) == SUBREG)
-		dest = alter_subreg (dest);
-	      if (GET_CODE (src) == SUBREG)
-		src = alter_subreg (src);
-
-	      if (GET_CODE (dest) == MEM && GET_CODE (src) == MEM)
-		mem = NULL_RTX;
-
-	      else if (GET_CODE (dest) == MEM)
-		mem = dest;
-
-	      else if (GET_CODE (src) == MEM)
-		mem = src;
-
-	      /* CYGNUS LOCAL v850e */
-	      else if (GET_CODE (src) == SIGN_EXTEND
-		       && GET_CODE (XEXP (src, 0)) == MEM)
-		mem = XEXP (src, 0);
-
-	      else if (GET_CODE (src) == ZERO_EXTEND
-		       && GET_CODE (XEXP (src, 0)) == MEM)
-		{
-		  mem = XEXP (src, 0);
-		  unsignedp = TRUE;
-		}
-	      /* END CYGNUS LOCAL */
-
-	      else
-		mem = NULL_RTX;
-
-	      if (mem && ep_memory_operand (mem, GET_MODE (mem), unsignedp))
-		use_ep = TRUE;
-
-	      else if (!use_ep && mem
-		       && GET_MODE_SIZE (GET_MODE (mem)) <= UNITS_PER_WORD)
-		{
-		  rtx addr = XEXP (mem, 0);
-		  int regno = -1;
-		  int short_p;
-
-		  if (GET_CODE (addr) == REG)
-		    {
-		      short_p = TRUE;
-		      regno = REGNO (addr);
-		    }
-
-		  else if (GET_CODE (addr) == PLUS
-			   && GET_CODE (XEXP (addr, 0)) == REG
-			   && GET_CODE (XEXP (addr, 1)) == CONST_INT
-			   && ((INTVAL (XEXP (addr, 1)))
-			       < ep_memory_offset (GET_MODE (mem), unsignedp))
-			   && ((INTVAL (XEXP (addr, 1))) >= 0))
-		    {
-		      short_p = TRUE;
-		      regno = REGNO (XEXP (addr, 0));
-		    }
-
-		  else
-		    short_p = FALSE;
-
-		  if (short_p)
-		    {
-		      regs[regno].uses++;
-		      regs[regno].last_insn = insn;
-		      if (!regs[regno].first_insn)
-			regs[regno].first_insn = insn;
-		    }
-		}
-
-	      /* Loading up a register in the basic block zaps any savings
-		 for the register */
-	      if (GET_CODE (dest) == REG)
-		{
-		  enum machine_mode mode = GET_MODE (dest);
-		  int regno;
-		  int endregno;
-
-		  regno = REGNO (dest);
-		  endregno = regno + HARD_REGNO_NREGS (regno, mode);
-
-		  if (!use_ep)
-		    {
-		      /* See if we can use the pointer before this
-			 modification.  */
-		      int max_uses = -1;
-		      int max_regno = -1;
-
-		      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-			{
-			  if (max_uses < regs[i].uses)
-			    {
-			      max_uses = regs[i].uses;
-			      max_regno = i;
-			    }
-			}
-
-		      if (max_uses > 3
-			  && max_regno >= regno
-			  && max_regno < endregno)
-			{
-			  substitute_ep_register (regs[max_regno].first_insn,
-						  regs[max_regno].last_insn,
-						  max_uses, max_regno, &r1,
-						  &ep);
-
-			  /* Since we made a substitution, zap all remembered
-			     registers.  */
-			  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-			    {
-			      regs[i].uses = 0;
-			      regs[i].first_insn = NULL_RTX;
-			      regs[i].last_insn = NULL_RTX;
-			    }
-			}
-		    }
-
-		  for (i = regno; i < endregno; i++)
-		    {
-		      regs[i].uses = 0;
-		      regs[i].first_insn = NULL_RTX;
-		      regs[i].last_insn = NULL_RTX;
-		    }
-		}
-	    }
-	}
-    }
-}
-
-
-/* # of registers saved by the interrupt handler.  */
-#define INTERRUPT_FIXED_NUM 4
-
-/* # of bytes for registers saved by the interrupt handler.  */
-#define INTERRUPT_FIXED_SAVE_SIZE (4 * INTERRUPT_FIXED_NUM)
-
-/* # of registers saved in register parameter area.  */
-#define INTERRUPT_REGPARM_NUM 4
-/* # of words saved for other registers.  */
-#define INTERRUPT_ALL_SAVE_NUM \
-  (30 - INTERRUPT_FIXED_NUM + INTERRUPT_REGPARM_NUM)
-
-#define INTERRUPT_ALL_SAVE_SIZE (4 * INTERRUPT_ALL_SAVE_NUM)
-
-int
-compute_register_save_size (p_reg_saved)
-     long *p_reg_saved;
-{
-  int size = 0;
-  int i;
-  int interrupt_handler = v850_interrupt_function_p (current_function_decl);
-  int call_p = regs_ever_live [LINK_POINTER_REGNUM];
-  long reg_saved = 0;
-
-  /* Count the return pointer if we need to save it.  */
-  if (profile_flag && !call_p)
-    regs_ever_live [LINK_POINTER_REGNUM] = call_p = 1;
- 
-  /* Count space for the register saves.  */
-  if (interrupt_handler)
-    {
-      for (i = 0; i <= 31; i++)
-	switch (i)
-	  {
-	  default:
-	    if (regs_ever_live[i] || call_p)
-	      {
-		size += 4;
-		reg_saved |= 1L << i;
-	      }
-	    break;
-
-	    /* We don't save/restore r0 or the stack pointer */
-	  case 0:
-	  case STACK_POINTER_REGNUM:
-	    break;
-
-	    /* For registers with fixed use, we save them, set them to the
-	       appropriate value, and then restore them.
-	       These registers are handled specially, so don't list them
-	       on the list of registers to save in the prologue.  */
-	  case 1:		/* temp used to hold ep */
-	  case 4:		/* gp */
-	  case 10:		/* temp used to call interrupt save/restore */
-	  case EP_REGNUM:	/* ep */
-	    size += 4;
-	    break;
-	  }
-    }
-  else
-    {
-      /* Find the first register that needs to be saved.  */
-      for (i = 0; i <= 31; i++)
-	if (regs_ever_live[i] && ((! call_used_regs[i])
-				  || i == LINK_POINTER_REGNUM))
-	  break;
-
-      /* If it is possible that an out-of-line helper function might be
-	 used to generate the prologue for the current function, then we
-	 need to cover the possibility that such a helper function will
-	 be used, despite the fact that there might be gaps in the list of
-	 registers that need to be saved.  To detect this we note that the
-	 helper functions always push at least register r29 if the link
-	 register is not used, and at least registers r27 - r31 if the
-	 link register is used (and provided that the function is not an
-	 interrupt handler).  */
-	 
-      if (TARGET_PROLOG_FUNCTION
-	  && (i == 2 || i >= 20)
-	  && regs_ever_live[LINK_POINTER_REGNUM] ? (i < 28) : (i < 30))
-	{
-	  if (i == 2)
-	    {
-	      size += 4;
-	      reg_saved |= 1L << i;
-
-	      i = 20;
-	    }
-
-	  /* Helper functions save all registers between the starting
-	     register and the last register, regardless of whether they
-	     are actually used by the function or not.  */
-	  for (; i <= 29; i++)
-	    {
-	      size += 4;
-	      reg_saved |= 1L << i;
-	    }
-
-	  if (regs_ever_live [LINK_POINTER_REGNUM])
-	    {
-	      size += 4;
-	      reg_saved |= 1L << LINK_POINTER_REGNUM;
-	    }
-	}
-      else
-	{
-	  for (; i <= 31; i++)
-	    if (regs_ever_live[i] && ((! call_used_regs[i])
-				      || i == LINK_POINTER_REGNUM))
-	      {
-		size += 4;
-		reg_saved |= 1L << i;
-	      }
-	}
-    }
-  
-  if (p_reg_saved)
-    *p_reg_saved = reg_saved;
-
-  return size;
-}
-
-int
-compute_frame_size (size, p_reg_saved)
-     int size;
-     long *p_reg_saved;
-{
-  extern int current_function_outgoing_args_size;
-
-  return (size
-	  + compute_register_save_size (p_reg_saved)
-	  + current_function_outgoing_args_size);
-}
-
-
-void
-expand_prologue ()
-{
-  unsigned int i;
-  int offset;
-  unsigned int size = get_frame_size ();
-  unsigned int actual_fsize;
-  unsigned int init_stack_alloc = 0;
-  rtx save_regs[32];
-  rtx save_all;
-  unsigned int num_save;
-  unsigned int default_stack;
-  int code;
-  int interrupt_handler = v850_interrupt_function_p (current_function_decl);
-  long reg_saved = 0;
-
-  actual_fsize = compute_frame_size (size, &reg_saved);
-
-  /* Save/setup global registers for interrupt functions right now */
-  if (interrupt_handler)
-    {
-/* CYGNUS LOCAL v850e */
-      if (TARGET_V850E && ! TARGET_DISABLE_CALLT)
-	emit_insn (gen_save_interrupt_v850e ());
-      else
-/* END CYGNUS LOCAL */
-	emit_insn (gen_save_interrupt ());
-      
-      actual_fsize -= INTERRUPT_FIXED_SAVE_SIZE;
-      
-      if (((1L << LINK_POINTER_REGNUM) & reg_saved) != 0)
-	actual_fsize -= INTERRUPT_ALL_SAVE_SIZE;
-    }
-
-  /* Save arg registers to the stack if necessary.  */
-  else if (current_function_anonymous_args)
-    {
-      if (TARGET_PROLOG_FUNCTION)
-	{
-/* CYGNUS LOCAL v850e */
-	  if (TARGET_V850E && ! TARGET_DISABLE_CALLT)
-	    emit_insn (gen_save_r6_r9_v850e ());
-	  else
-/* END CYGNUS LOCAL */
-	    emit_insn (gen_save_r6_r9 ());
-	}
-      else
-	{
-	  offset = 0;
-	  for (i = 6; i < 10; i++)
-	    {
-	      emit_move_insn (gen_rtx (MEM, SImode,
-				       plus_constant (stack_pointer_rtx,
-						      offset)),
-			      gen_rtx (REG, SImode, i));
-	      offset += 4;
-	    }
-	}
-    }
-
-  /* Identify all of the saved registers */
-  num_save = 0;
-  default_stack = 0;
-  for (i = 1; i < 31; i++)
-    {
-      if (((1L << i) & reg_saved) != 0)
-	save_regs[num_save++] = gen_rtx (REG, Pmode, i);
-    }
-
-  /* If the return pointer is saved, the helper functions also allocate
-     16 bytes of stack for arguments to be saved in.  */
-  if (((1L << LINK_POINTER_REGNUM) & reg_saved) != 0)
-    {
-      save_regs[num_save++] = gen_rtx (REG, Pmode, LINK_POINTER_REGNUM);
-      default_stack = 16;
-    }
-
-  /* See if we have an insn that allocates stack space and saves the particular
-     registers we want to.  */
-  save_all = NULL_RTX;
-  if (TARGET_PROLOG_FUNCTION && num_save > 0 && actual_fsize >= default_stack)
-    {
-      int alloc_stack = (4 * num_save) + default_stack;
-      int unalloc_stack = actual_fsize - alloc_stack;
-      int save_func_len = 4;
-      int save_normal_len;
-
-      if (unalloc_stack)
-	save_func_len += CONST_OK_FOR_J (unalloc_stack) ? 2 : 4;
-
-      /* see if we would have used ep to save the stack */
-      if (TARGET_EP && num_save > 3 && (unsigned)actual_fsize < 255)
-	save_normal_len = (3 * 2) + (2 * num_save);
-      else
-	save_normal_len = 4 * num_save;
-
-      save_normal_len += CONST_OK_FOR_J (actual_fsize) ? 2 : 4;
-
-      /* Don't bother checking if we don't actually save any space.
-	 This happens for instance if one register is saved and additional
-	 stack space is allocated.  */
-      if (save_func_len < save_normal_len)
-	{
-	  save_all = gen_rtx (PARALLEL, VOIDmode,
-			      rtvec_alloc (num_save + (TARGET_V850 ? 2 : 1)));
-	  XVECEXP (save_all, 0, 0) = gen_rtx (SET, VOIDmode,
-					      stack_pointer_rtx,
-					      gen_rtx (PLUS, Pmode,
-						       stack_pointer_rtx,
-						       GEN_INT (-alloc_stack)));
-
-	  if (TARGET_V850)
-	    {
-	      XVECEXP (save_all, 0, num_save + 1)
-		= gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, Pmode, 10));
-	    }
-
-	  offset = - default_stack;
-	  for (i = 0; i < num_save; i++)
-	    {
-	      XVECEXP (save_all, 0, i + 1)
-		= gen_rtx (SET, VOIDmode,
-			   gen_rtx (MEM, Pmode,
-				    plus_constant (stack_pointer_rtx, offset)),
-				    save_regs[i]);
-	      offset -= 4;
-	    }
-
-	  code = recog (save_all, NULL_RTX, NULL_PTR);
-	  if (code >= 0)
-	    {
-	      rtx insn = emit_insn (save_all);
-	      INSN_CODE (insn) = code;
-	      actual_fsize -= alloc_stack;
-	      
-	      if (TARGET_DEBUG)
-		fprintf (stderr, "\
-Saved %d bytes via prologue function (%d vs. %d) for function %s\n",
-			 save_normal_len - save_func_len,
-			 save_normal_len, save_func_len,
-			 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)));
-	    }
-	  else
-	    save_all = NULL_RTX;
-	}
-    }
-
-  /* If no prolog save function is available, store the registers the old
-     fashioned way (one by one). */
-  if (!save_all)
-    {
-      /* Special case interrupt functions that save all registers for a call.  */
-      if (interrupt_handler && ((1L << LINK_POINTER_REGNUM) & reg_saved) != 0)
-	{
-/* CYGNUS LOCAL v850e */
-	  if (TARGET_V850E && ! TARGET_DISABLE_CALLT)
-	    emit_insn (gen_save_all_interrupt_v850e ());
-	  else
-/* END CYGNUS LOCAL */
-	    emit_insn (gen_save_all_interrupt ());
-	}
-      else
-	{
-	  /* If the stack is too big, allocate it in chunks so we can do the
-	     register saves.  We use the register save size so we use the ep
-	     register.  */
-	  if (actual_fsize && !CONST_OK_FOR_K (-actual_fsize))
-	    init_stack_alloc = compute_register_save_size (NULL);
-	  else
-	    init_stack_alloc = actual_fsize;
-	      
-	  /* Save registers at the beginning of the stack frame */
-	  offset = init_stack_alloc - 4;
-	  
-	  if (init_stack_alloc)
-	    emit_insn (gen_addsi3 (stack_pointer_rtx,
-				   stack_pointer_rtx,
-				   GEN_INT (-init_stack_alloc)));
-	  
-	  /* Save the return pointer first.  */
-	  if (num_save > 0 && REGNO (save_regs[num_save-1]) == LINK_POINTER_REGNUM)
-	    {
-	      emit_move_insn (gen_rtx (MEM, SImode,
-				       plus_constant (stack_pointer_rtx,
-						      offset)),
-			      save_regs[--num_save]);
-	      offset -= 4;
-	    }
-	  
-	  for (i = 0; i < num_save; i++)
-	    {
-	      emit_move_insn (gen_rtx (MEM, SImode,
-				       plus_constant (stack_pointer_rtx,
-						      offset)),
-			      save_regs[i]);
-	      offset -= 4;
-	    }
-	}
-    }
-
-  /* Allocate the rest of the stack that was not allocated above (either it is
-     > 32K or we just called a function to save the registers and needed more
-     stack.  */
-  if (actual_fsize > init_stack_alloc)
-    {
-      int diff = actual_fsize - init_stack_alloc;
-      if (CONST_OK_FOR_K (diff))
-	emit_insn (gen_addsi3 (stack_pointer_rtx,
-			       stack_pointer_rtx,
-			       GEN_INT (-diff)));
-      else
-	{
-	  rtx reg = gen_rtx (REG, Pmode, 12);
-	  emit_move_insn (reg, GEN_INT (-diff));
-	  emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
-	}
-    }
-
-  /* If we need a frame pointer, set it up now.  */
-  if (frame_pointer_needed)
-    emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
-}
-
-
-void
-expand_epilogue ()
-{
-  unsigned int i;
-  int offset;
-  unsigned int size = get_frame_size ();
-  long reg_saved = 0;
-  unsigned int actual_fsize = compute_frame_size (size, &reg_saved);
-  unsigned int init_stack_free = 0;
-  rtx restore_regs[32];
-  rtx restore_all;
-  unsigned int num_restore;
-  unsigned int default_stack;
-  int code;
-  int interrupt_handler = v850_interrupt_function_p (current_function_decl);
-
-  /* Eliminate the initial stack stored by interrupt functions.  */
-  if (interrupt_handler)
-    {
-      actual_fsize -= INTERRUPT_FIXED_SAVE_SIZE;
-      if (((1L << LINK_POINTER_REGNUM) & reg_saved) != 0)
-	actual_fsize -= INTERRUPT_ALL_SAVE_SIZE;
-    }
-
-  /* Cut off any dynamic stack created.  */
-  if (frame_pointer_needed)
-    emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
-
-  /* Identify all of the saved registers */
-  num_restore = 0;
-  default_stack = 0;
-  for (i = 1; i < 31; i++)
-    {
-      if (((1L << i) & reg_saved) != 0)
-	restore_regs[num_restore++] = gen_rtx (REG, Pmode, i);
-    }
-
-  /* If the return pointer is saved, the helper functions also allocate
-     16 bytes of stack for arguments to be saved in.  */
-  if (((1L << LINK_POINTER_REGNUM) & reg_saved) != 0)
-    {
-      restore_regs[num_restore++] = gen_rtx (REG, Pmode, LINK_POINTER_REGNUM);
-      default_stack = 16;
-    }
-
-  /* See if we have an insn that restores the particular registers we
-     want to.  */
-  restore_all = NULL_RTX;
-  if (TARGET_PROLOG_FUNCTION && num_restore > 0
-      && actual_fsize >= default_stack
-      && !interrupt_handler)
-    {
-      int alloc_stack = (4 * num_restore) + default_stack;
-      int unalloc_stack = actual_fsize - alloc_stack;
-      int restore_func_len = 4;
-      int restore_normal_len;
-
-      if (unalloc_stack)
-	restore_func_len += CONST_OK_FOR_J (unalloc_stack) ? 2 : 4;
-
-      /* see if we would have used ep to restore the registers */
-      if (TARGET_EP && num_restore > 3 && (unsigned)actual_fsize < 255)
-	restore_normal_len = (3 * 2) + (2 * num_restore);
-      else
-	restore_normal_len = 4 * num_restore;
-
-      restore_normal_len += (CONST_OK_FOR_J (actual_fsize) ? 2 : 4) + 2;
-
-      /* Don't bother checking if we don't actually save any space.  */
-      if (restore_func_len < restore_normal_len)
-	{
-	  restore_all = gen_rtx (PARALLEL, VOIDmode,
-				 rtvec_alloc (num_restore + 2));
-	  XVECEXP (restore_all, 0, 0) = gen_rtx (RETURN, VOIDmode);
-	  XVECEXP (restore_all, 0, 1)
-	    = gen_rtx (SET, VOIDmode, stack_pointer_rtx,
-		       gen_rtx (PLUS, Pmode,
-				stack_pointer_rtx,
-				GEN_INT (alloc_stack)));
-
-	  offset = alloc_stack - 4;
-	  for (i = 0; i < num_restore; i++)
-	    {
-	      XVECEXP (restore_all, 0, i+2)
-		= gen_rtx (SET, VOIDmode,
-			   restore_regs[i],
-			   gen_rtx (MEM, Pmode,
-				    plus_constant
-				    (stack_pointer_rtx, offset)));
-	      offset -= 4;
-	    }
-
-	  code = recog (restore_all, NULL_RTX, NULL_PTR);
-	  if (code >= 0)
-	    {
-	      rtx insn;
-
-	      actual_fsize -= alloc_stack;
-	      if (actual_fsize)
-		{
-		  if (CONST_OK_FOR_K (actual_fsize))
-		    emit_insn (gen_addsi3 (stack_pointer_rtx,
-					   stack_pointer_rtx,
-					   GEN_INT (actual_fsize)));
-		  else
-		    {
-		      rtx reg = gen_rtx (REG, Pmode, 12);
-		      emit_move_insn (reg, GEN_INT (actual_fsize));
-		      emit_insn (gen_addsi3 (stack_pointer_rtx,
-					     stack_pointer_rtx,
-					     reg));
-		    }
-		}
-
-	      insn = emit_jump_insn (restore_all);
-	      INSN_CODE (insn) = code;
-
-	      if (TARGET_DEBUG)
-		fprintf (stderr, "\
-Saved %d bytes via epilogue function (%d vs. %d) in function %s\n",
-			 restore_normal_len - restore_func_len,
-			 restore_normal_len, restore_func_len,
-			 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)));
-	    }
-	  else
-	    restore_all = NULL_RTX;
-	}
-    }
-
-  /* If no epilog save function is available, restore the registers the
-     old fashioned way (one by one). */
-  if (!restore_all)
-    {
-      /* If the stack is large, we need to cut it down in 2 pieces.  */
-      if (actual_fsize && !CONST_OK_FOR_K (-actual_fsize))
-	init_stack_free = 4 * num_restore;
-      else
-	init_stack_free = actual_fsize;
-
-      /* Deallocate the rest of the stack if it is > 32K or if extra stack
-	 was allocated for an interrupt handler that makes a call.  */
-      if (actual_fsize > init_stack_free
-	  || (interrupt_handler && actual_fsize))
-	{
-	  int diff;
-
-	  diff = actual_fsize - ((interrupt_handler) ? 0 : init_stack_free);
-	  
-	  if (CONST_OK_FOR_K (diff))
-	    emit_insn (gen_addsi3 (stack_pointer_rtx,
-				   stack_pointer_rtx,
-				   GEN_INT (diff)));
-	  else
-	    {
-	      rtx reg = gen_rtx (REG, Pmode, 12);
-	      emit_move_insn (reg, GEN_INT (diff));
-	      emit_insn (gen_addsi3 (stack_pointer_rtx,
-				     stack_pointer_rtx,
-				     reg));
-	    }
-	}
-
-      /* Special case interrupt functions that save all registers
-	 for a call.  */
-      if (interrupt_handler && ((1L << LINK_POINTER_REGNUM) & reg_saved) != 0)
-	{
-/* CYGNUS LOCAL v850e */
-	  if (TARGET_V850E && ! TARGET_DISABLE_CALLT)
-	    emit_insn (gen_restore_all_interrupt_v850e ());
-	  else
-/* END CYGNUS LOCAL */
-	    emit_insn (gen_restore_all_interrupt ());
-	}
-      else
-	{
-	  /* Restore registers from the beginning of the stack frame */
-	  offset = init_stack_free - 4;
-
-	  /* Restore the return pointer first.  */
-	  if (num_restore > 0
-	      && REGNO (restore_regs [num_restore - 1]) == LINK_POINTER_REGNUM)
-	    {
-	      emit_move_insn (restore_regs[--num_restore],
-			      gen_rtx (MEM, SImode,
-				       plus_constant (stack_pointer_rtx,
-						      offset)));
-	      offset -= 4;
-	    }
-
-	  for (i = 0; i < num_restore; i++)
-	    {
-	      emit_move_insn (restore_regs[i],
-			      gen_rtx (MEM, SImode,
-				       plus_constant (stack_pointer_rtx,
-						      offset)));
-
-	      offset -= 4;
-	    }
-
-	  /* Cut back the remainder of the stack.  */
-	  if (init_stack_free)
-	    emit_insn (gen_addsi3 (stack_pointer_rtx,
-				   stack_pointer_rtx,
-				   GEN_INT (init_stack_free)));
-	}
-
-      /* And return or use reti for interrupt handlers.  */
-      if (interrupt_handler)
-	emit_jump_insn (gen_restore_interrupt ());
-      else if (actual_fsize)
-	emit_jump_insn (gen_return_internal ());
-      else
-	emit_jump_insn (gen_return ());
-    }
-
-  current_function_anonymous_args = 0;
-  v850_interrupt_cache_p = FALSE;
-  v850_interrupt_p = FALSE;
-}
-
-
-/* Update the condition code from the insn.  */
-
-void
-notice_update_cc (body, insn)
-     rtx body;
-     rtx insn;
-{
-  switch (get_attr_cc (insn))
-    {
-    case CC_NONE:
-      /* Insn does not affect CC at all.  */
-      break;
-
-    case CC_NONE_0HIT:
-      /* Insn does not change CC, but the 0'th operand has been changed.  */
-      if (cc_status.value1 != 0
-	  && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1))
-	cc_status.value1 = 0;
-      break;
-
-    case CC_SET_ZN:
-      /* Insn sets the Z,N flags of CC to recog_operand[0].
-	 V,C is in an unusable state.  */
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
-      cc_status.value1 = recog_operand[0];
-      break;
-
-    case CC_SET_ZNV:
-      /* Insn sets the Z,N,V flags of CC to recog_operand[0].
-	 C is in an unusable state.  */
-      CC_STATUS_INIT;
-      cc_status.flags |= CC_NO_CARRY;
-      cc_status.value1 = recog_operand[0];
-      break;
-
-    case CC_COMPARE:
-      /* The insn is a compare instruction.  */
-      CC_STATUS_INIT;
-      cc_status.value1 = SET_SRC (body);
-      break;
-
-    case CC_CLOBBER:
-      /* Insn doesn't leave CC in a usable state.  */
-      CC_STATUS_INIT;
-      break;
-    }
-}
-
-/* Retrieve the data area that has been chosen for the given decl.  */
-
-v850_data_area
-v850_get_data_area (decl)
-     tree decl;
-{
-  if (lookup_attribute ("sda", DECL_MACHINE_ATTRIBUTES (decl)) != NULL_TREE)
-    return DATA_AREA_SDA;
-  
-  if (lookup_attribute ("tda", DECL_MACHINE_ATTRIBUTES (decl)) != NULL_TREE)
-    return DATA_AREA_TDA;
-  
-  if (lookup_attribute ("zda", DECL_MACHINE_ATTRIBUTES (decl)) != NULL_TREE)
-    return DATA_AREA_ZDA;
-
-  return DATA_AREA_NORMAL;
-}
-
-/* Store the indicated data area in the decl's attributes.  */
-
-static void
-v850_set_data_area (decl, data_area)
-     tree decl;
-     v850_data_area data_area;
-{
-  tree name;
-  
-  switch (data_area)
-    {
-    case DATA_AREA_SDA: name = get_identifier ("sda"); break;
-    case DATA_AREA_TDA: name = get_identifier ("tda"); break;
-    case DATA_AREA_ZDA: name = get_identifier ("zda"); break;
-    default:
-      return;
-    }
-
-  DECL_MACHINE_ATTRIBUTES (decl) = tree_cons
-    (name, NULL, DECL_MACHINE_ATTRIBUTES (decl));
-}
-
-/* Return nonzero if ATTR is a valid attribute for DECL.
-   ARGS are the arguments supplied with ATTR.  */
-
-int
-v850_valid_machine_decl_attribute (decl, attr, args)
-     tree decl;
-     tree attr;
-     tree args;
-{
-  v850_data_area data_area;
-  v850_data_area area;
-  
-  if (args != NULL_TREE)
-    return 0;
-
-  if (is_attribute_p ("interrupt_handler", attr)
-      || is_attribute_p ("interrupt", attr))
-    return TREE_CODE (decl) == FUNCTION_DECL;
-
-  /* Implement data area attribute.  */
-  if (is_attribute_p ("sda", attr))
-    data_area = DATA_AREA_SDA;
-  else if (is_attribute_p ("tda", attr))
-    data_area = DATA_AREA_TDA;
-  else if (is_attribute_p ("zda", attr))
-    data_area = DATA_AREA_ZDA;
-  else
-    return 0;
-  
-  switch (TREE_CODE (decl))
-    {
-    case VAR_DECL:
-      if (current_function_decl != NULL_TREE)
-	error_with_decl (decl, "\
-a data area attribute cannot be specified for local variables");
-      
-      /* Drop through.  */
-
-    case FUNCTION_DECL:
-      area = v850_get_data_area (decl);
-      if (area != DATA_AREA_NORMAL && data_area != area)
-	error_with_decl (decl, "\
-data area of '%s' conflicts with previous declaration");
-      
-      return 1;
-      
-    default:
-      break;
-    }
-  
-  return 0;
-}
-
-
-/* Return nonzero if FUNC is an interrupt function as specified
-   by the "interrupt" attribute.  */
-
-int
-v850_interrupt_function_p (func)
-     tree func;
-{
-  tree a;
-  int ret = 0;
-
-  if (v850_interrupt_cache_p)
-    return v850_interrupt_p;
-
-  if (TREE_CODE (func) != FUNCTION_DECL)
-    return 0;
-
-  a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func));
-  if (a != NULL_TREE)
-    ret = 1;
-
-  else
-    {
-      a = lookup_attribute ("interrupt", DECL_MACHINE_ATTRIBUTES (func));
-      ret = a != NULL_TREE;
-    }
-
-  /* Its not safe to trust global variables until after function inlining has
-     been done.  */
-  if (reload_completed | reload_in_progress)
-    v850_interrupt_p = ret;
-
-  return ret;
-}
-
-
-extern struct obstack * saveable_obstack;
-
-void
-v850_encode_data_area (decl)
-     tree decl;
-{
-  char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
-  int    len = strlen (str);
-  char * newstr;
-
-  /* Map explict sections into the appropriate attribute */
-  if (v850_get_data_area (decl) == DATA_AREA_NORMAL)
-    {
-      if (DECL_SECTION_NAME (decl))
-	{
-	  char * name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
-	  
-	  if (streq (name, ".zdata") || streq (name, ".zbss"))
-	    v850_set_data_area (decl, DATA_AREA_ZDA);
-
-	  else if (streq (name, ".sdata") || streq (name, ".sbss"))
-	    v850_set_data_area (decl, DATA_AREA_SDA);
-
-	  else if (streq (name, ".tdata"))
-	    v850_set_data_area (decl, DATA_AREA_TDA);
-	}
-
-      /* If no attribute, support -m{zda,sda,tda}=n */
-      else
-	{
-	  int size = int_size_in_bytes (TREE_TYPE (decl));
-	  if (size <= 0)
-	    ;
-
-	  else if (size <= small_memory [(int) SMALL_MEMORY_TDA].max)
-	    v850_set_data_area (decl, DATA_AREA_TDA);
-
-	  else if (size <= small_memory [(int) SMALL_MEMORY_SDA].max)
-	    v850_set_data_area (decl, DATA_AREA_SDA);
-
-	  else if (size <= small_memory [(int) SMALL_MEMORY_ZDA].max)
-	    v850_set_data_area (decl, DATA_AREA_ZDA);
-	}
-      
-      if (v850_get_data_area (decl) == DATA_AREA_NORMAL)
-	return;
-    }
-
-  newstr = obstack_alloc (saveable_obstack, len + 2);
-
-  strcpy (newstr + 1, str);
-
-  switch (v850_get_data_area (decl))
-    {
-    case DATA_AREA_ZDA: *newstr = ZDA_NAME_FLAG_CHAR; break;
-    case DATA_AREA_TDA: *newstr = TDA_NAME_FLAG_CHAR; break;
-    case DATA_AREA_SDA: *newstr = SDA_NAME_FLAG_CHAR; break;
-    default: abort ();
-    }
-
-  XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
-}
-
-/* Return true if the given RTX is a register which can be restored
-   by a function epilogue.  */
-int
-register_is_ok_for_epilogue (op, mode)
-     rtx op;
-     enum machine_mode ATTRIBUTE_UNUSED mode;
-{
-  /* The save/restore routines can only cope with registers 2, and 20 - 31 */
-  return (GET_CODE (op) == REG)
-	  && (((REGNO (op) >= 20) && REGNO (op) <= 31)
-	      || REGNO (op) == 2);
-}
-
-/* Return non-zero if the given RTX is suitable for collapsing into
-   jump to a function epilogue.  */
-int
-pattern_is_ok_for_epilogue (op, mode)
-     rtx op;
-     enum machine_mode ATTRIBUTE_UNUSED mode;
-{
-  int count = XVECLEN (op, 0);
-  int i;
-  
-  /* If there are no registers to restore then the function epilogue
-     is not suitable.  */
-  if (count <= 2)
-    return 0;
-
-  /* The pattern matching has already established that we are performing a
-     function epilogue and that we are popping at least one register.  We must
-     now check the remaining entries in the vector to make sure that they are
-     also register pops.  There is no good reason why there should ever be
-     anything else in this vector, but being paranoid always helps...
-
-     The test below performs the C equivalent of this machine description
-     pattern match:
-
-        (set (match_operand:SI n "register_is_ok_for_epilogue" "r")
-	  (mem:SI (plus:SI (reg:SI 3) (match_operand:SI n "immediate_operand" "i"))))
-     */
-
-  for (i = 3; i < count; i++)
-    {
-      rtx vector_element = XVECEXP (op, 0, i);
-      rtx dest;
-      rtx src;
-      rtx plus;
-      
-      if (GET_CODE (vector_element) != SET)
-	return 0;
-      
-      dest = SET_DEST (vector_element);
-      src = SET_SRC (vector_element);
-
-      if (GET_CODE (dest) != REG
-	  || GET_MODE (dest) != SImode
-	  || ! register_is_ok_for_epilogue (dest, SImode)
-	  || GET_CODE (src) != MEM
-	  || GET_MODE (src) != SImode)
-	return 0;
-
-      plus = XEXP (src, 0);
-
-      if (GET_CODE (plus) != PLUS
-	  || GET_CODE (XEXP (plus, 0)) != REG
-	  || GET_MODE (XEXP (plus, 0)) != SImode
-	  || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
-	  || GET_CODE (XEXP (plus, 1)) != CONST_INT)
-	return 0;
-    }
-
-  return 1;
-}
-
-/* Construct a JR instruction to a routine that will perform the equivalent of
-   the RTL passed in as an argument.  This RTL is a function epilogue that
-   pops registers off the stack and possibly releases some extra stack space
-   as well.  The code has already verified that the RTL matches these
-   requirements.  */
-char *
-construct_restore_jr (op)
-     rtx op;
-{
-  int count = XVECLEN (op, 0);
-  int stack_bytes;
-  unsigned long int mask;
-  unsigned long int first;
-  unsigned long int last;
-  int i;
-  static char buff [100]; /* XXX */
-  
-  if (count <= 2)
-    {
-      error ("Bogus JR construction: %d\n", count);
-      return NULL;
-    }
-
-  /* Work out how many bytes to pop off the stack before retrieving
-     registers.  */
-  if (GET_CODE (XVECEXP (op, 0, 1)) != SET)
-    abort ();
-  if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) != PLUS)
-    abort ();
-  if (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)) != CONST_INT)
-    abort ();
-    
-  stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1));
-
-  /* Each pop will remove 4 bytes from the stack... */
-  stack_bytes -= (count - 2) * 4;
-
-  /* Make sure that the amount we are popping either 0 or 16 bytes.  */
-  if (stack_bytes != 0 && stack_bytes != 16)
-    {
-      error ("Bad amount of stack space removal: %d", stack_bytes);
-      return NULL;
-    }
-
-  /* Now compute the bit mask of registers to push.  */
-  mask = 0;
-  for (i = 2; i < count; i++)
-    {
-      rtx vector_element = XVECEXP (op, 0, i);
-      
-      if (GET_CODE (vector_element) != SET)
-	abort ();
-      if (GET_CODE (SET_DEST (vector_element)) != REG)
-	abort ();
-      if (! register_is_ok_for_epilogue (SET_DEST (vector_element), SImode))
-	abort ();
-      
-      mask |= 1 << REGNO (SET_DEST (vector_element));
-    }
-
-  /* Scan for the first register to pop.  */
-  for (first = 0; first < 32; first++)
-    {
-      if (mask & (1 << first))
-	break;
-    }
-
-  if (first >= 32)
-    abort ();
-
-  /* Discover the last register to pop.  */
-  if (mask & (1 << LINK_POINTER_REGNUM))
-    {
-      if (stack_bytes != 16)
-	abort ();
-      
-      last = LINK_POINTER_REGNUM;
-    }
-  else
-    {
-      if (stack_bytes != 0)
-	abort ();
-      
-      if ((mask & (1 << 29)) == 0)
-	abort ();
-      
-      last = 29;
-    }
-
-  /* Note, it is possible to have gaps in the register mask.
-     We ignore this here, and generate a JR anyway.  We will
-     be popping more registers than is strictly necessary, but
-     it does save code space.  */
-  
-  if (TARGET_LONG_CALLS)
-    {
-      char name[40];
-      
-      if (first == last)
-	sprintf (name, "__return_%s", reg_names [first]);
-      else
-	sprintf (name, "__return_%s_%s", reg_names [first], reg_names [last]);
-      
-      sprintf (buff, "movhi hi(%s), r0, r6\n\tmovea lo(%s), r6, r6\n\tjmp r6",
-	       name, name);
-    }
-  else
-    {
-      if (first == last)
-	sprintf (buff, "jr __return_%s", reg_names [first]);
-      else
-	sprintf (buff, "jr __return_%s_%s", reg_names [first], reg_names [last]);
-    }
-  
-  return buff;
-}
-
-
-/* Return non-zero if the given RTX is suitable for collapsing into
-   a jump to a function prologue.  */
-int
-pattern_is_ok_for_prologue (op, mode)
-     rtx op;
-     enum machine_mode ATTRIBUTE_UNUSED mode;
-{
-  int count = XVECLEN (op, 0);
-  int i; 
-  rtx vector_element;
- 
-  /* If there are no registers to save then the function prologue
-     is not suitable.  */
-  if (count <= 2)
-    return 0;
-
-  /* The pattern matching has already established that we are adjusting the
-     stack and pushing at least one register.  We must now check that the
-     remaining entries in the vector to make sure that they are also register
-     pushes, except for the last entry which should be a CLOBBER of r10.
-
-     The test below performs the C equivalent of this machine description
-     pattern match:
-
-     (set (mem:SI (plus:SI (reg:SI 3)
-      (match_operand:SI 2 "immediate_operand" "i")))
-      (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
-
-     */
-
-  for (i = 2; i < count - 1; i++)
-    {
-      rtx dest;
-      rtx src;
-      rtx plus;
-      
-      vector_element = XVECEXP (op, 0, i);
-      
-      if (GET_CODE (vector_element) != SET)
-	return 0;
-      
-      dest = SET_DEST (vector_element);
-      src = SET_SRC (vector_element);
-
-      if (GET_CODE (dest) != MEM
-	  || GET_MODE (dest) != SImode
-	  || GET_CODE (src) != REG
-	  || GET_MODE (src) != SImode
-	  || ! register_is_ok_for_epilogue (src, SImode))
-	return 0;
-
-      plus = XEXP (dest, 0);
-
-      if ( GET_CODE (plus) != PLUS
-	  || GET_CODE (XEXP (plus, 0)) != REG
-	  || GET_MODE (XEXP (plus, 0)) != SImode
-	  || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
-	  || GET_CODE (XEXP (plus, 1)) != CONST_INT)
-	return 0;
-
-      /* If the register is being pushed somewhere other than the stack
-	 space just acquired by the first operand then abandon this quest.
-	 Note: the test is <= because both values are negative.	 */
-      if (INTVAL (XEXP (plus, 1))
-	  <= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
-	{
-	  return 0;
-	}
-    }
-
-  /* Make sure that the last entry in the vector is a clobber.  */
-  vector_element = XVECEXP (op, 0, i);
-  
-  if (GET_CODE (vector_element) != CLOBBER
-      || GET_CODE (XEXP (vector_element, 0)) != REG
-      || REGNO (XEXP (vector_element, 0)) != 10)
-    return 0;
-  
-  return 1;
-}
-
-/* Construct a JARL instruction to a routine that will perform the equivalent
-   of the RTL passed as a parameter.  This RTL is a function prologue that
-   saves some of the registers r20 - r31 onto the stack, and possibly acquires
-   some stack space as well.  The code has already verified that the RTL
-   matches these requirements.  */
-char *
-construct_save_jarl (op)
-     rtx op;
-{
-  int count = XVECLEN (op, 0);
-  int stack_bytes;
-  unsigned long int mask;
-  unsigned long int first;
-  unsigned long int last;
-  int i;
-  static char buff [100]; /* XXX */
-  
-  if (count <= 2)
-    {
-      error ("Bogus JARL construction: %d\n", count);
-      return NULL;
-    }
-
-  /* Paranoia.  */
-  if (GET_CODE (XVECEXP (op, 0, 0)) != SET)
-    abort ();
-  if (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != PLUS)
-    abort ();
-  if (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0)) != REG)
-    abort ();
-  if (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)) != CONST_INT)
-    abort ();
-    
-  /* Work out how many bytes to push onto the stack after storing the
-     registers.  */
-  stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1));
-
-  /* Each push will put 4 bytes from the stack... */
-  stack_bytes += (count - 2) * 4;
-
-  /* Make sure that the amount we are popping either 0 or 16 bytes.  */
-  if (stack_bytes != 0 && stack_bytes != -16)
-    {
-      error ("Bad amount of stack space removal: %d", stack_bytes);
-      return NULL;
-    }
-
-  /* Now compute the bit mask of registers to push.  */
-  mask = 0;
-  for (i = 1; i < count - 1; i++)
-    {
-      rtx vector_element = XVECEXP (op, 0, i);
-      
-      if (GET_CODE (vector_element) != SET)
-	abort ();
-      if (GET_CODE (SET_SRC (vector_element)) != REG)
-	abort ();
-      if (! register_is_ok_for_epilogue (SET_SRC (vector_element), SImode))
-	abort ();
-      
-      mask |= 1 << REGNO (SET_SRC (vector_element));
-    }
-
-  /* Scan for the first register to push.  */  
-  for (first = 0; first < 32; first++)
-    {
-      if (mask & (1 << first))
-	break;
-    }
-
-  if (first >= 32)
-    abort ();
-
-  /* Discover the last register to push.  */
-  if (mask & (1 << LINK_POINTER_REGNUM))
-    {
-      if (stack_bytes != -16)
-	abort ();
-      
-      last = LINK_POINTER_REGNUM;
-    }
-  else
-    {
-      if (stack_bytes != 0)
-	abort ();
-      if ((mask & (1 << 29)) == 0)
-	abort ();
-      
-      last = 29;
-    }
-
-  /* Note, it is possible to have gaps in the register mask.
-     We ignore this here, and generate a JARL anyway.  We will
-     be pushing more registers than is strictly necessary, but
-     it does save code space.  */
-  
-  if (TARGET_LONG_CALLS)
-    {
-      char name[40];
-      
-      if (first == last)
-	sprintf (name, "__save_%s", reg_names [first]);
-      else
-	sprintf (name, "__save_%s_%s", reg_names [first], reg_names [last]);
-      
-      sprintf (buff, "movhi hi(%s), r0, r11\n\tmovea lo(%s), r11, r11\n\tjarl .+4, r10\n\tadd 4, r10\n\tjmp r11",
-	       name, name);
-    }
-  else
-    {
-      if (first == last)
-	sprintf (buff, "jarl __save_%s, r10", reg_names [first]);
-      else
-	sprintf (buff, "jarl __save_%s_%s, r10", reg_names [first],
-		 reg_names [last]);
-    }
-
-  return buff;
-}
-
-extern tree last_assemble_variable_decl;
-extern int size_directive_output;
-
-/* A version of asm_output_aligned_bss() that copes with the special
-   data areas of the v850. */
-void
-v850_output_aligned_bss (file, decl, name, size, align)
-     FILE * file;
-     tree decl;
-     char * name;
-     int size;
-     int align;
-{
-  ASM_GLOBALIZE_LABEL (file, name);
-  
-  switch (v850_get_data_area (decl))
-    {
-    case DATA_AREA_ZDA:
-      zbss_section ();
-      break;
-
-    case DATA_AREA_SDA:
-      sbss_section ();
-      break;
-
-    case DATA_AREA_TDA:
-      tdata_section ();
-      
-    default:
-      bss_section ();
-      break;
-    }
-  
-  ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
-#ifdef ASM_DECLARE_OBJECT_NAME
-  last_assemble_variable_decl = decl;
-  ASM_DECLARE_OBJECT_NAME (file, name, decl);
-#else
-  /* Standard thing is just output label for the object.  */
-  ASM_OUTPUT_LABEL (file, name);
-#endif /* ASM_DECLARE_OBJECT_NAME */
-  ASM_OUTPUT_SKIP (file, size ? size : 1);
-}
-
-/* Called via the macro ASM_OUTPUT_DECL_COMMON */
-void
-v850_output_common (file, decl, name, size, align)
-     FILE * file;
-     tree decl;
-     char * name;
-     int size;
-     int align;
-{
-  if (decl == NULL_TREE)
-    {
-      fprintf (file, "\t%s\t", COMMON_ASM_OP);
-    }
-  else
-    {
-      switch (v850_get_data_area (decl))
-	{
-	case DATA_AREA_ZDA:
-	  fprintf (file, "\t%s\t", ZCOMMON_ASM_OP);
-	  break;
-
-	case DATA_AREA_SDA:
-	  fprintf (file, "\t%s\t", SCOMMON_ASM_OP);
-	  break;
-
-	case DATA_AREA_TDA:
-	  fprintf (file, "\t%s\t", TCOMMON_ASM_OP);
-	  break;
-      
-	default:
-	  fprintf (file, "\t%s\t", COMMON_ASM_OP);
-	  break;
-	}
-    }
-  
-  assemble_name (file, name);
-  fprintf (file, ",%u,%u\n", size, align / BITS_PER_UNIT);
-}
-
-/* Called via the macro ASM_OUTPUT_DECL_LOCAL */
-void
-v850_output_local (file, decl, name, size, align)
-     FILE * file;
-     tree decl;
-     char * name;
-     int size;
-     int align;
-{
-  fprintf (file, "\t%s\t", LOCAL_ASM_OP);
-  assemble_name (file, name);
-  fprintf (file, "\n");
-  
-  ASM_OUTPUT_ALIGNED_DECL_COMMON (file, decl, name, size, align);
-}
-
-/* The following code is for handling pragmas supported by the
-   v850 compiler produced by Green Hills Software.  This is at
-   the specific request of a customer.  */
-
-/* Track the current data area set by the data area pragma (which 
-   can be nested).  Tested by check_default_data_area. */
-
-typedef struct data_area_stack_element
-{
-  struct data_area_stack_element * prev;
-  v850_data_area                   data_area; /* current default data area. */
-} data_area_stack_element;
-
-static data_area_stack_element * data_area_stack = NULL;
-
-/* Names of the various data areas used on the v850.  */
-static tree GHS_default_section_names [(int) COUNT_OF_GHS_SECTION_KINDS];
-static tree GHS_current_section_names [(int) COUNT_OF_GHS_SECTION_KINDS];
-
-/* Push a data area onto the stack.  */
-static int
-push_data_area (data_area)
-     v850_data_area data_area;
-{
-  data_area_stack_element * elem;
-
-  elem = (data_area_stack_element *) xmalloc (sizeof (* elem));
-
-  if (elem == NULL)
-    return 0;
-
-  elem->prev      = data_area_stack;
-  elem->data_area = data_area;
-
-  data_area_stack = elem;
-
-  return 1;
-}
-
-/* Remove a data area from the stack.  */
-static int
-pop_data_area (data_area)
-     v850_data_area data_area;
-{
-  if (data_area_stack == NULL)
-    warning ("#pragma GHS endXXXX found without previous startXXX");
-  else if (data_area != data_area_stack->data_area)
-    warning ("#pragma GHS endXXX does not match previous startXXX");
-  else
-    {
-      data_area_stack_element * elem;
-
-      elem = data_area_stack;
-      data_area_stack = data_area_stack->prev;
-
-      free (elem);
-
-      return 1;
-    }
-
-  return 0;
-}
-
-/* Set the machine specific 'interrupt' attribute on the current function.  */
-static int
-mark_current_function_as_interrupt ()
-{
-  tree name;
-  
-  if (current_function_decl ==  NULL_TREE)
-    {
-      warning ("Cannot set interrupt attribute: no current function");
-      return 0;
-    }
-
-  name = get_identifier ("interrupt");
-
-  if (name == NULL_TREE || TREE_CODE (name) != IDENTIFIER_NODE)
-    {
-      warning ("Cannot set interrupt attribute: no such identifier");
-      return 0;
-    }
-  
-  return valid_machine_attribute
-    (name, NULL_TREE, current_function_decl, NULL_TREE);
-}
-
-/* Parse STRING as part of a GHS pragma.
-   Returns 0 if the pragma has been parsed and there was a problem,
-   non-zero in all other cases.  */
-static int
-parse_ghs_pragma_token (string)
-     char * string;
-{
-  static enum v850_pragma_state state = V850_PS_START;
-  static enum v850_pragma_type  type  = V850_PT_UNKNOWN;
-  static v850_data_area         data_area = DATA_AREA_NORMAL;
-  static char *                 data_area_name;
-  static enum GHS_section_kind  GHS_section_kind = GHS_SECTION_KIND_DEFAULT;
-
-  /* If the string is NULL then we have reached the end of the
-     #pragma construct.  Make sure that we are in an end state, and
-     then implement the pragma's directive.  */
-  if (string == NULL)
-    {
-      int ret_val = 1;
-      
-      if (state != V850_PS_SHOULD_BE_DONE
-	  && state != V850_PS_MAYBE_COMMA
-	  && state != V850_PS_MAYBE_SECTION_NAME)
-	{
-	  if (state != V850_PS_BAD)
-	    warning ("Incomplete #pragma ghs");
-
-	  ret_val = 0;
-	}
-      else switch (type)
-	{
-	case V850_PT_UNKNOWN:
-	  warning ("Nothing follows #pragma ghs");
-	  ret_val = 0;
-	  break;
-	  
-	case V850_PT_INTERRUPT:
-	  ret_val = mark_current_function_as_interrupt ();
-	  break;
-	  
-	case V850_PT_SECTION:
-	  /* If a section kind has not been specified, then reset
-	     all section names back to their defaults.  */
-	  if (GHS_section_kind == GHS_SECTION_KIND_DEFAULT)
-	    {
-	      int i;
-	      
-	      for (i = COUNT_OF_GHS_SECTION_KINDS; i--;)
-		GHS_current_section_names [i] = NULL;
-	    }
-	  /* If a section has been specified, then this will be handled
-	     by check_default_section_name ().  */
-	  break;
-	  
-	case V850_PT_START_SECTION:
-	  ret_val = push_data_area (data_area);
-	  break;
-	  
-	case V850_PT_END_SECTION:
-	  ret_val = pop_data_area (data_area);
-	  break;
-	}
-
-      state = V850_PS_START;
-      type  = V850_PT_UNKNOWN;
-      
-      return ret_val;
-    }
-  
-  switch (state)
-    {
-    case V850_PS_START:
-      data_area = DATA_AREA_NORMAL;
-      data_area_name = NULL;
-      
-      if (streq (string, "interrupt"))
-	{
-	  type = V850_PT_INTERRUPT;
-	  state = V850_PS_SHOULD_BE_DONE;
-	}
-      else if (streq (string, "section"))
-	{
-	  type = V850_PT_SECTION;
-	  state = V850_PS_MAYBE_SECTION_NAME;
-	  GHS_section_kind = GHS_SECTION_KIND_DEFAULT;
-	}
-      else if (streq (string, "starttda"))
-	{
-	  type = V850_PT_START_SECTION;
-	  state = V850_PS_SHOULD_BE_DONE;
-	  data_area = DATA_AREA_TDA;
-	}
-      else if (streq (string, "endtda"))
-	{
-	  type = V850_PT_END_SECTION;
-	  state = V850_PS_SHOULD_BE_DONE;
-	  data_area = DATA_AREA_TDA;
-	}
-      else if (streq (string, "startsda"))
-	{
-	  type = V850_PT_START_SECTION;
-	  state = V850_PS_SHOULD_BE_DONE;
-	  data_area = DATA_AREA_SDA;
-	}
-      else if (streq (string, "endsda"))
-	{
-	  type = V850_PT_END_SECTION;
-	  state = V850_PS_SHOULD_BE_DONE;
-	  data_area = DATA_AREA_SDA;
-	}
-      else if (streq (string, "startzda"))
-	{
-	  type = V850_PT_START_SECTION;
-	  state = V850_PS_SHOULD_BE_DONE;
-	  data_area = DATA_AREA_ZDA;
-	}
-      else if (streq (string, "endzda"))
-	{
-	  type = V850_PT_END_SECTION;
-	  state = V850_PS_SHOULD_BE_DONE;
-	  data_area = DATA_AREA_ZDA;
-	}
-      else
-	{
-	  warning ("Unrecognised GHS pragma: '%s'\n", string);
-	  state = V850_PS_BAD;
-	}
-      break;
-      
-    case V850_PS_SHOULD_BE_DONE:
-      warning ("Extra text after valid #pragma: '%s'", string);
-      state = V850_PS_BAD;
-      break;
-      
-    case V850_PS_BAD:
-      /* Ignore tokens in a pragma that has been diagnosed as being corrupt. */
-      break;
-
-    case V850_PS_MAYBE_SECTION_NAME:
-      state = V850_PS_EXPECTING_EQUALS;
-      
-           if (streq (string, "data"))	  GHS_section_kind = GHS_SECTION_KIND_DATA;
-      else if (streq (string, "text"))	  GHS_section_kind = GHS_SECTION_KIND_TEXT;
-      else if (streq (string, "rodata"))  GHS_section_kind = GHS_SECTION_KIND_RODATA;
-      else if (streq (string, "const"))	  GHS_section_kind = GHS_SECTION_KIND_RODATA;
-      else if (streq (string, "rosdata")) GHS_section_kind = GHS_SECTION_KIND_ROSDATA;
-      else if (streq (string, "rozdata")) GHS_section_kind = GHS_SECTION_KIND_ROZDATA;
-      else if (streq (string, "sdata"))	  GHS_section_kind = GHS_SECTION_KIND_SDATA;
-      else if (streq (string, "tdata"))	  GHS_section_kind = GHS_SECTION_KIND_TDATA;
-      else if (streq (string, "zdata"))	  GHS_section_kind = GHS_SECTION_KIND_ZDATA;
-      /* According to GHS beta documentation, the following should not be allowed!  */
-      else if (streq (string, "bss"))	  GHS_section_kind = GHS_SECTION_KIND_BSS;
-      else if (streq (string, "zbss"))	  GHS_section_kind = GHS_SECTION_KIND_ZDATA;
-      else
-	{
-	  warning ("Unrecognised section name '%s' in GHS section pragma",
-		   string);
-	  state = V850_PS_BAD;
-	}
-      break;
-
-    case V850_PS_EXPECTING_EQUALS:
-      if (streq (string, "="))
-	state = V850_PS_EXPECTING_SECTION_ALIAS;
-      else
-	{
-	  warning ("Missing '=' in GHS section pragma");
-	  state = V850_PS_BAD;
-	}
-      break;
-      
-    case V850_PS_EXPECTING_SECTION_ALIAS:
-      if (streq (string, "default"))
-	GHS_current_section_names [GHS_section_kind] = NULL;
-      else
-	GHS_current_section_names [GHS_section_kind] =
-	  build_string (strlen (string) + 1, string);
-      
-      state = V850_PS_MAYBE_COMMA;
-      break;
-      
-    case V850_PS_MAYBE_COMMA:
-      if (streq (string, ","))
-	state = V850_PS_MAYBE_SECTION_NAME;
-      else
-	{
-	  warning
-	    ("Malformed GHS section pragma: found '%s' instead of a comma",
-	     string);
-	  state = V850_PS_BAD;
-	}
-      break;
-    }
-  
-  return 1;
-}
-
-/* Handle the parsing of an entire GHS pragma.  */
-int
-v850_handle_pragma (p_getc, p_ungetc, name)
-     int (*  p_getc) PROTO ((void));
-     void (* p_ungetc) PROTO ((int));
-     char *  name;
-{
-  /* Parse characters in the input stream until:
-
-   * end of line
-   * end of file
-   * a complete GHS pragma has been parsed
-   * a corrupted GHS pragma has been parsed
-   * an unknown pragma is encountered.
-
-   If an unknown pragma is encountered, we must return with
-   the input stream in the same state as upon entry to this function.
-   
-   The first token in the input stream has already been parsed
-   for us, and is passed as 'name'.  */
-  
-  if (! streq (name, "ghs"))
-    return 0;
-
-  /* We now know that we are parsing a GHS pragma, so we do
-     not need to preserve the original input stream state.  */
-  for (;;)
-    {
-      static char buffer [128];
-      int         c;
-      char *      buff;
-      
-      /* Skip white space.  */
-      do
-	c = p_getc ();
-      while (c == ' ' || c == '\t');
-      
-      p_ungetc (c);
-      
-      if (c == '\n' || c == EOF || c == '\r')
-	return parse_ghs_pragma_token (NULL);
-
-      /* Read next word.  We have to do the parsing ourselves, rather
-	 than calling yylex() because we can be built with front ends
-	 that do not provide such functions.  */
-      buff = buffer;
-      * buff ++ = (c = p_getc ());
-
-      switch (c)
-	{
-	case ',':
-	case '=':
-	  * buff ++ = (c = p_getc ());
-	  break;
-	  
-	case '"':
-	  /* Skip opening double parenthesis.  */
-	  -- buff;
-
-	  /* Read string.  */
-	  do
-	    * buff ++ = (c = p_getc ());
-	  while (c != EOF && isascii (c)
-		 && (isalnum (c) || c == '_' || c == '.' || c == ' ')
-		 && (buff < buffer + 126));
-	  
-	  if (c != '"')
-	    warning ("Missing trailing \" in #pragma ghs");
-	  else
-	    c = p_getc ();
-	  break;
-
-	default:
-	  while (c != EOF && isascii (c)
-		 && (isalnum (c) || c == '_' || c == '.')
-		 && (buff < buffer + 126))
-	    * buff ++ = (c = p_getc ());
-	  break;
-	}
-
-      p_ungetc (c);
-
-      /* If nothing was read then terminate the parsing.  */
-      if (buff == buffer + 1)
-	return parse_ghs_pragma_token (NULL);
-
-      /* Parse and continue.  */
-      * -- buff = 0;
-      
-      parse_ghs_pragma_token (buffer);
-    }
-}
-
-/* Add data area to the given declaration if a ghs data area pragma is
-   currently in effect (#pragma ghs startXXX/endXXX).  */
-void
-v850_set_default_decl_attr (decl)
-     tree decl;
-{
-  if (data_area_stack
-      && data_area_stack->data_area
-      && current_function_decl == NULL_TREE
-      && (TREE_CODE (decl) == VAR_DECL || TREE_CODE (decl) == CONST_DECL)
-      && v850_get_data_area (decl) == DATA_AREA_NORMAL)
-    v850_set_data_area (decl, data_area_stack->data_area);
-
-  /* Initialise the default names of the v850 specific sections,
-     if this has not been done before.  */
-  
-  if (GHS_default_section_names [(int) GHS_SECTION_KIND_SDATA] == NULL)
-    {
-      GHS_default_section_names [(int) GHS_SECTION_KIND_SDATA]
-	= build_string (sizeof (".sdata")-1, ".sdata");
-
-      GHS_default_section_names [(int) GHS_SECTION_KIND_ROSDATA]
-	= build_string (sizeof (".rosdata")-1, ".rosdata");
-
-      GHS_default_section_names [(int) GHS_SECTION_KIND_TDATA]
-	= build_string (sizeof (".tdata")-1, ".tdata");
-      
-      GHS_default_section_names [(int) GHS_SECTION_KIND_ZDATA]
-	= build_string (sizeof (".zdata")-1, ".zdata");
-
-      GHS_default_section_names [(int) GHS_SECTION_KIND_ROZDATA]
-	= build_string (sizeof (".rozdata")-1, ".rozdata");
-    }
-  
-  if (current_function_decl == NULL_TREE
-      && (TREE_CODE (decl) == VAR_DECL
-	  || TREE_CODE (decl) == CONST_DECL
-	  || TREE_CODE (decl) == FUNCTION_DECL)
-      && (!DECL_EXTERNAL (decl) || DECL_INITIAL (decl))
-      && !DECL_SECTION_NAME (decl))
-    {
-      enum GHS_section_kind kind = GHS_SECTION_KIND_DEFAULT;
-      tree chosen_section;
-
-      if (TREE_CODE (decl) == FUNCTION_DECL)
-	kind = GHS_SECTION_KIND_TEXT;
-      else
-	{
-	  /* First choose a section kind based on the data area of the decl. */
-	  switch (v850_get_data_area (decl))
-	    {
-	    default:
-	      abort ();
-	      
-	    case DATA_AREA_SDA:
-	      kind = ((TREE_READONLY (decl))
-		      ? GHS_SECTION_KIND_ROSDATA
-		      : GHS_SECTION_KIND_SDATA);
-	      break;
-	      
-	    case DATA_AREA_TDA:
-	      kind = GHS_SECTION_KIND_TDATA;
-	      break;
-	      
-	    case DATA_AREA_ZDA:
-	      kind = ((TREE_READONLY (decl))
-		      ? GHS_SECTION_KIND_ROZDATA
-		      : GHS_SECTION_KIND_ZDATA);
-	      break;
-	      
-	    case DATA_AREA_NORMAL:		 /* default data area */
-	      if (TREE_READONLY (decl))
-		kind = GHS_SECTION_KIND_RODATA;
-	      else if (DECL_INITIAL (decl))
-		kind = GHS_SECTION_KIND_DATA;
-	      else
-		kind = GHS_SECTION_KIND_BSS;
-	    }
-	}
-
-      /* Now, if the section kind has been explicitly renamed,
-         then attach a section attribute. */
-      chosen_section = GHS_current_section_names [(int) kind];
-
-      /* Otherwise, if this kind of section needs an explicit section
-         attribute, then also attach one. */
-      if (chosen_section == NULL)
-        chosen_section = GHS_default_section_names [(int) kind];
-
-      if (chosen_section)
-	{
-	  /* Only set the section name if specified by a pragma, because
-	     otherwise it will force those variables to get allocated storage
-	     in this module, rather than by the linker.  */
-	  DECL_SECTION_NAME (decl) = chosen_section;
-	}
-    }
-}
-
-/* CYGNUS LOCAL v850e */
-/* Return non-zero if the given RTX is suitable for collapsing into a
-   DISPOSE instruction.  */
-int
-pattern_is_ok_for_dispose (op, mode)
-  rtx 			op;
-  enum machine_mode	mode;
-{
-  int count = XVECLEN (op, 0);
-  int i;
-  
-  /* If there are no registers to restore then the dispose instruction is not
-     suitable.  */
-  if (count <= 2)
-    return 0;
-
-  /* The pattern matching has already established that we are performing a
-     function epilogue and that we are popping at least one register.  We must
-     now check the remaining entries in the vector to make sure that they are
-     also register pops.  There is no good reason why there should ever be
-     anything else in this vector, but being paranoid always helps...
-
-     The test below performs the C equivalent of this machine description
-     pattern match:
-
-        (set (match_operand:SI n "register_is_ok_for_epilogue" "r")
-	  (mem:SI (plus:SI (reg:SI 3)
-	    (match_operand:SI n "immediate_operand" "i"))))
-     */
-
-  for (i = 3; i < count; i++)
-    {
-      rtx vector_element = XVECEXP (op, 0, i);
-      rtx dest;
-      rtx src;
-      rtx plus;
-      
-      if (GET_CODE (vector_element) != SET)
-	return 0;
-      
-      dest = SET_DEST (vector_element);
-      src  = SET_SRC (vector_element);
-
-      if (   GET_CODE (dest) != REG
-	  || GET_MODE (dest) != SImode
-	  || ! register_is_ok_for_epilogue (dest, SImode)
-	  || GET_CODE (src) != MEM
-	  || GET_MODE (src) != SImode)
-	return 0;
-
-      plus = XEXP (src, 0);
-
-      if (   GET_CODE (plus) != PLUS
-	  || GET_CODE (XEXP (plus, 0)) != REG
-	  || GET_MODE (XEXP (plus, 0)) != SImode
-	  || REGNO    (XEXP (plus, 0)) != STACK_POINTER_REGNUM
-	  || GET_CODE (XEXP (plus, 1)) != CONST_INT)
-	return 0;
-    }
-
-  return 1;
-}
-
-/* Construct a DISPOSE instruction that is the equivalent of
-   the given RTX.  We have already verified that this should
-   be possible.  */
-char *
-construct_dispose_instruction (op)
-     rtx op;
-{
-  int                count = XVECLEN (op, 0);
-  int                stack_bytes;
-  unsigned long int  mask;
-  int		     i;
-  static char        buff[ 100 ]; /* XXX */
-  int                use_callt = 0;
-  
-  if (count <= 2)
-    {
-      error ("Bogus DISPOSE construction: %d\n", count);
-      return NULL;
-    }
-
-  /* Work out how many bytes to pop off the stack before retrieving
-     registers.  */
-  if (GET_CODE (XVECEXP (op, 0, 1)) != SET)
-    abort ();
-  if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) != PLUS)
-    abort ();
-  if (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)) != CONST_INT)
-    abort ();
-    
-  stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1));
-
-  /* Each pop will remove 4 bytes from the stack... */
-
-  stack_bytes -= (count - 2) * 4;
-
-  /* Make sure that the amount we are popping will fit into the DISPOSE
-     instruction.  */
-  if (stack_bytes > 128)
-    {
-      error ("Too much stack space to dispose of: %d", stack_bytes);
-      return NULL;
-    }
-
-  /* Now compute the bit mask of registers to push.  */
-  mask = 0;
-
-  for (i = 2; i < count; i++)
-    {
-      rtx vector_element = XVECEXP (op, 0, i);
-      
-      if (GET_CODE (vector_element) != SET)
-	abort ();
-      if (GET_CODE (SET_DEST (vector_element)) != REG)
-	abort ();
-      if (! register_is_ok_for_epilogue (SET_DEST (vector_element), SImode))
-	abort ();
-
-      if (REGNO (SET_DEST (vector_element)) == 2)
-	use_callt = 1;
-      else
-        mask |= 1 << REGNO (SET_DEST (vector_element));
-    }
-
-  if (! TARGET_DISABLE_CALLT
-      && (use_callt || stack_bytes == 0 || stack_bytes == 16))
-    {
-      if (use_callt)
-	{
-	  sprintf (buff, "callt ctoff(__callt_return_r2_r%d)", (mask & (1 << 31)) ? 31 : 29);
-	  return buff;
-	}
-      else
-	{
-	  for (i = 20; i < 32; i++)
-	    {
-	      if (mask & (1 << i))
-		break;
-	    }
-	  
-	  if (i == 31)
-	    {
-	      sprintf (buff, "callt ctoff(__callt_return_r31c)");
-	    }
-	  else
-	    {
-	      sprintf (buff, "callt ctoff(__callt_return_r%d_r%d%s)",
-		       i, (mask & (1 << 31)) ? 31 : 29, stack_bytes ? "c" : "");
-	    }
-	}
-    }
-  else
-    {
-      static char        regs [100]; /* XXX */
-      int                done_one;
-      
-      /* Generate the DISPOSE instruction.  Note we could just issue the
-	 bit mask as a number as the assembler can cope with this, but for
-	 the sake of our readers we turn it into a textual description.  */
-      
-      regs[0] = 0;
-      done_one = 0;
-      
-      for (i = 20; i < 32; i++)
-	{
-	  if (mask & (1 << i))
-	    {
-	      int first;
-	      
-	      if (done_one)
-		strcat (regs, ", ");
-	      else
-		done_one = 1;
-	      
-	      first = i;
-	      strcat (regs, reg_names[ first ]);
-	      
-	      for (i++; i < 32; i++)
-		if ((mask & (1 << i)) == 0)
-		  break;
-	      
-	      if (i > first + 1)
-		{
-		  strcat (regs, " - ");
-		  strcat (regs, reg_names[ i - 1 ] );
-		}
-	    }
-	}
-      
-      sprintf (buff, "dispose %d {%s}, r31", stack_bytes / 4, regs);
-    }
-  
-  return buff;
-}
-
-/* Return non-zero if the given RTX is suitable for collapsing into a PREPARE
-   instruction.  */
-int
-pattern_is_ok_for_prepare (op, mode)
-     rtx		op;
-     enum machine_mode	mode;
-{
-  int count = XVECLEN (op, 0);
-  int i;
-  
-  /* If there are no registers to restore then the prepare instruction
-     is not suitable.  */
-  if (count <= 1)
-    return 0;
-
-  /* The pattern matching has already established that we are adjusting the
-     stack and pushing at least one register.  We must now check that the
-     remaining entries in the vector to make sure that they are also register
-     pushes.
-
-     The test below performs the C equivalent of this machine description
-     pattern match:
-
-     (set (mem:SI (plus:SI (reg:SI 3)
-       (match_operand:SI 2 "immediate_operand" "i")))
-         (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
-
-     */
-
-  for (i = 2; i < count; i++)
-    {
-      rtx vector_element = XVECEXP (op, 0, i);
-      rtx dest;
-      rtx src;
-      rtx plus;
-      
-      if (GET_CODE (vector_element) != SET)
-	return 0;
-      
-      dest = SET_DEST (vector_element);
-      src  = SET_SRC (vector_element);
-
-      if (   GET_CODE (dest) != MEM
-	  || GET_MODE (dest) != SImode
-	  || GET_CODE (src) != REG
-	  || GET_MODE (src) != SImode
-	  || ! register_is_ok_for_epilogue (src, SImode)
-	     )
-	return 0;
-
-      plus = XEXP (dest, 0);
-
-      if (   GET_CODE (plus) != PLUS
-	  || GET_CODE (XEXP (plus, 0)) != REG
-	  || GET_MODE (XEXP (plus, 0)) != SImode
-	  || REGNO    (XEXP (plus, 0)) != STACK_POINTER_REGNUM
-	  || GET_CODE (XEXP (plus, 1)) != CONST_INT)
-	return 0;
-
-      /* If the register is being pushed somewhere other than the stack
-	 space just aquired by the first operand then abandon this quest.
-	 Note: the test is <= becuase both values are negative.	 */
-      if (INTVAL (XEXP (plus, 1))
-	  <= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
-	{
-	  return 0;
-	}
-    }
-
-  return 1;
-}
-
-/* Construct a PREPARE instruction that is the equivalent of
-   the given RTL.  We have already verified that this should
-   be possible.  */
-char *
-construct_prepare_instruction (op)
-     rtx op;
-{
-  int                count = XVECLEN (op, 0);
-  int                stack_bytes;
-  unsigned long int  mask;
-  int		     i;
-  static char        buff[ 100 ]; /* XXX */
-  int		     use_callt = 0;
-  
-  if (count <= 1)
-    {
-      error ("Bogus PREPEARE construction: %d\n", count);
-      return NULL;
-    }
-
-  /* Work out how many bytes to push onto the stack after storing the
-     registers.  */
-  if (GET_CODE (XVECEXP (op, 0, 0)) != SET)
-    abort ();
-  if (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != PLUS)
-    abort ();
-  if (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)) != CONST_INT)
-    abort ();
-    
-  stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1));
-
-  /* Each push will put 4 bytes from the stack... */
-  stack_bytes += (count - 1) * 4;
-
-  /* Make sure that the amount we are popping will fit into the DISPOSE
-     instruction.  */
-  if (stack_bytes < -128)
-    {
-      error ("Too much stack space to prepare: %d", stack_bytes);
-      return NULL;
-    }
-
-  /* Now compute the bit mask of registers to push.  */
-  mask = 0;
-  for (i = 1; i < count; i++)
-    {
-      rtx vector_element = XVECEXP (op, 0, i);
-      
-      if (GET_CODE (vector_element) != SET)
-	abort ();
-      if (GET_CODE (SET_SRC (vector_element)) != REG)
-	abort ();
-      if (! register_is_ok_for_epilogue (SET_SRC (vector_element), SImode))
-	abort ();
-
-      if (REGNO (SET_SRC (vector_element)) == 2)
-	use_callt = 1;
-      else
-	mask |= 1 << REGNO (SET_SRC (vector_element));
-    }
-
-  if ((! TARGET_DISABLE_CALLT)
-      && (use_callt || stack_bytes == 0 || stack_bytes == -16))
-    {
-      if (use_callt)
-	{
-	  sprintf (buff, "callt ctoff(__callt_save_r2_r%d)", (mask & (1 << 31)) ? 31 : 29 );
-	  return buff;
-	}
-      
-      for (i = 20; i < 32; i++)
-	{
-	  if (mask & (1 << i))
-	    break;
-	}
-
-      if (i == 31)
-	{
-	  sprintf (buff, "callt ctoff(__callt_save_r31c)");
-	}
-      else
-	{
-	  sprintf (buff, "callt ctoff(__callt_save_r%d_r%d%s)",
-		   i, (mask & (1 << 31)) ? 31 : 29, stack_bytes ? "c" : "");
-	}
-    }
-  else
-    {
-      static char        regs [100]; /* XXX */
-      int                done_one;
-
-      
-      /* Generate the PREPARE instruction.  Note we could just issue the
-	 bit mask as a number as the assembler can cope with this, but for
-	 the sake of our readers we turn it into a textual description.  */
-      
-      regs[0] = 0;
-      done_one = 0;
-      
-      for (i = 20; i < 32; i++)
-	{
-	  if (mask & (1 << i))
-	    {
-	      int first;
-	      
-	      if (done_one)
-		strcat (regs, ", ");
-	      else
-		done_one = 1;
-	      
-	      first = i;
-	      strcat (regs, reg_names[ first ]);
-	      
-	      for (i++; i < 32; i++)
-		if ((mask & (1 << i)) == 0)
-		  break;
-	      
-	      if (i > first + 1)
-		{
-		  strcat (regs, " - ");
-		  strcat (regs, reg_names[ i - 1 ] );
-		}
-	    }
-	}
-      	 
-      sprintf (buff, "prepare {%s}, %d", regs, (- stack_bytes) / 4);
-    }
-  
-  return buff;
-}
-
-/* END CYGNUS LOCAL */
diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h
deleted file mode 100755
index 44c8b2a..0000000
--- a/gcc/config/v850/v850.h
+++ /dev/null
@@ -1,1792 +0,0 @@
-/* Definitions of target machine for GNU compiler. NEC V850 series
-   Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-   Contributed by Jeff Law (law@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "svr4.h"	/* Automatically does #undef CPP_PREDEFINES */
-
-#undef ASM_SPEC
-#define ASM_SPEC "%{mv*:-mv%*}"
-
-/* CYGNUS LOCAL v850e */
-/* We must pass a -mv850 option to the assembler if no explicit -mv* option
-   is given, because the assembler's processor default may not be correct.  */
-
-#ifndef SUBTARGET_ASM_SPEC
-#define SUBTARGET_ASM_SPEC "%{!mv*:-mv850}"
-#endif
-
-#undef ASM_SPEC
-#define ASM_SPEC "%{mv*:-mv%*} %(subtarget_asm_spec)"
-
-#ifndef CPP_SPEC
-#define CPP_SPEC "%{mv850ea:-D__v850ea__} %{mv850e:-D__v850e__} %{mv850:-D__v850__} %{!mv*:-D__v850__}"
-#endif
-
-#define EXTRA_SPECS { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }
-/* END CYGNUS LOCAL */
-
-#ifndef CPP_SPEC
-#define CPP_SPEC "-D__v850__"
-#endif
-
-#undef ASM_FINAL_SPEC
-#undef LIB_SPEC
-#undef ENDFILE_SPEC
-#undef LINK_SPEC
-#undef STARTFILE_SPEC
-
-/* Names to predefine in the preprocessor for this target machine.  */
-#define CPP_PREDEFINES "-D__v851__ -D__v850"
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#ifndef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (NEC V850)");
-#endif
-
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Target flags bits, see below for an explanation of the bits.  */
-#define MASK_GHS		0x00000001
-#define MASK_LONG_CALLS		0x00000002
-#define MASK_EP			0x00000004
-#define MASK_PROLOG_FUNCTION	0x00000008
-#define MASK_DEBUG		0x40000000
-
-#define MASK_CPU                0x00000030
-#define MASK_V850               0x00000010
-
-/* CYGNUS LOCAL v850e */
-#define MASK_SMALL_SLD          0x00000040
-/* END CYGNUS LOCAL */
-#define MASK_BIG_SWITCH		0x00000100
-/* CYGNUS LOCAL nickc/ghs */
-#define MASK_NO_APP_REGS        0x00000200
-/* END CYGNUS LOCAL */
-/* CYGNUS LOCAL v850e */
-#define MASK_DISABLE_CALLT      0x00000400
-/* END CYGNUS LOCAL */
-
-#ifndef MASK_DEFAULT
-#define MASK_DEFAULT            MASK_V850
-#endif
-
-#define TARGET_V850    		((target_flags & MASK_CPU) == MASK_V850)
-
-/* CYGNUS LOCAL nickc/v850e */
-/* This is a development hack.  In order to test building
-   GCC for a V850 toolchain as well as a V850EA toolchain
-   I want to be able to use the same sources.
-   This would normally fail because TARGET_V850E is undefined,
-   so v850.md will not compile.  To get around this I define
-   TARGET_V850E here.  In released code this hack, plus the
-   sections of v850.md where TARGET_V850E are used will
-   disappear, so noone need ever know what I have done :-) */
-
-#ifndef TARGET_V850E
-#define MASK_V850E              0x00000020
-#define TARGET_V850E   		((target_flags & MASK_CPU) == MASK_V850E)
-#endif
-
-#ifndef TARGET_V850EA
-#define MASK_V850EA              0x00000030
-#define TARGET_V850EA  		((target_flags & MASK_CPU) == MASK_V850EA)
-#endif
-
-#ifndef EXTRA_SWITCHES
-#define EXTRA_SWITCHES 		{ "v850e",   MASK_V850E, "Compile for v850e processor" },            \
-                                { "v850e", -(MASK_V850E ^ MASK_CPU), "" }, /* Make sure that the other bits are cleared.  */ \
-                       		{ "v850ea", MASK_V850EA, "Compile for v850ea processor" },
-#endif
-
-/* END CYGNUS LOCAL */
-
-
-/* Macros used in the machine description to test the flags.  */
-
-/* The GHS calling convention support doesn't really work,
-   mostly due to a lack of documentation.  Outstanding issues:
-
-     * How do varargs & stdarg really work.  How to they handle
-     passing structures (if at all).
-
-     * Doubles are normally 4 byte aligned, except in argument
-     lists where they are 8 byte aligned.  Is the alignment
-     in the argument list based on the first parameter,
-     first stack parameter, etc etc.
-
-     * Passing/returning of large structures probably isn't the same
-     as GHS.  We don't have enough documentation on their conventions
-     to be compatible.
-
-     * Tests of SETUP_INCOMING_VARARGS need to be made runtime checks
-     since it depends on TARGET_GHS.  */
-#define TARGET_GHS (target_flags & MASK_GHS)
- 
-/* Don't do PC-relative calls, instead load the address of the target
-   function into a register and perform a register indirect call.  */
-#define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
-
-/* Whether to optimize space by using ep (r30) for pointers with small offsets
-   in basic blocks.  */
-#define TARGET_EP (target_flags & MASK_EP)
-
-/* Whether to call out-of-line functions to save registers or not.  */
-#define TARGET_PROLOG_FUNCTION (target_flags & MASK_PROLOG_FUNCTION)
-
-/* CYGNUS LOCAL v850e */
-/* Whether to assume that the SLD.B and SLD.H instructions only have small
-   displacement fields, thus allowing the generated code to run on any of
-   the V850 range of processors.  */
-#define TARGET_SMALL_SLD (target_flags & MASK_SMALL_SLD)
-
-/* True if callt will not be used for function prolog & epilog */
-#define TARGET_DISABLE_CALLT (target_flags & MASK_DISABLE_CALLT)
-/* END CYGNUS LOCAL */
-				  
-/* Whether to emit 2 byte per entry or 4 byte per entry switch tables.  */
-#define TARGET_BIG_SWITCH (target_flags & MASK_BIG_SWITCH)
-
-/* CYGNUS LOCAL nickc/ghs */
-/* True if r2 and r5 can be used by the compiler.  False if r2 and r5
-   are to be fixed registers (for compatibility with GHS).  */
-#define TARGET_NO_APP_REGS  (target_flags & MASK_NO_APP_REGS)
-/* END CYGNUS LOCAL */
-				  
-/* General debug flag */
-#define TARGET_DEBUG (target_flags & MASK_DEBUG)
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES							\
-  {{ "ghs",			 MASK_GHS, "Support Green Hills ABI" },	\
-   { "no-ghs",			-MASK_GHS, "" },			\
-   { "long-calls",		 MASK_LONG_CALLS, 			\
-       				"Prohibit PC relative function calls" },\
-   { "no-long-calls",		-MASK_LONG_CALLS, "" },			\
-   { "ep",			 MASK_EP,				\
-                                "Reuse r30 on a per function basis" },  \
-   { "no-ep",			-MASK_EP, "" },				\
-   { "prolog-function",		 MASK_PROLOG_FUNCTION, 			\
-       				"Use stubs for function prologues" },	\
-   { "no-prolog-function",	-MASK_PROLOG_FUNCTION, "" },		\
-   { "space",			 MASK_EP | MASK_PROLOG_FUNCTION, 	\
-       				"Same as: -mep -mprolog-function" },	\
-   { "debug",			 MASK_DEBUG, "Enable backend debugging" }, \
-   { "v850",		 	 MASK_V850,				\
-                                "Compile for the v850 processor" },	\
-   { "v850",		 	 -(MASK_V850 ^ MASK_CPU), "" },		\
-   { "big-switch",		 MASK_BIG_SWITCH, 			\
-       				"Use 4 byte entries in switch tables" },\
-/* CYGNUS LOCAL nickc/ghs */ 						\
-   { "app-regs",                -MASK_NO_APP_REGS, ""  },               \
-   { "no-app-regs",              MASK_NO_APP_REGS, 			\
-       				"Do not use registers r2 and r5" },     \
-/* END CYGNUS LOCAL */ 							\
-/* CYGNUS LOCAL v850e */						\
-   { "small-sld",		 MASK_SMALL_SLD, "" },			\
-   { "no-small-sld",		-MASK_SMALL_SLD, "" },			\
-   { "disable-callt",            MASK_DISABLE_CALLT, 			\
-       				"Do not use the callt instruction" },   \
-   { "no-disable-callt",         -MASK_DISABLE_CALLT, "" },             \
-/* END CYGNUS LOCAL */							\
-   EXTRA_SWITCHES							\
-   { "",			 TARGET_DEFAULT, ""}}
-
-#ifndef EXTRA_SWITCHES
-#define EXTRA_SWITCHES
-#endif
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 		MASK_DEFAULT
-#endif
-
-/* Information about the various small memory areas.  */
-struct small_memory_info {
-  char *name;
-  char *value;
-  long max;
-  long physical_max;
-};
-
-enum small_memory_type {
-  /* tiny data area, using EP as base register */
-  SMALL_MEMORY_TDA = 0,
-  /* small data area using dp as base register */
-  SMALL_MEMORY_SDA,
-  /* zero data area using r0 as base register */
-  SMALL_MEMORY_ZDA,
-  SMALL_MEMORY_max
-};
-
-extern struct small_memory_info small_memory[(int)SMALL_MEMORY_max];
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an
-   initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   fixed part of the option name, and the address of a variable.  The
-   variable, type `char *', is set to the variable part of the given
-   option if the fixed part matches.  The actual option name is made
-   by appending `-m' to the specified name.
-
-   Here is an example which defines `-mshort-data-NUMBER'.  If the
-   given option is `-mshort-data-512', the variable `m88k_short_data'
-   will be set to the string `"512"'.
-
-          extern char *m88k_short_data;
-          #define TARGET_OPTIONS \
-           { { "short-data-", &m88k_short_data } } */
-
-#define TARGET_OPTIONS							\
-{									\
-  { "tda=",	&small_memory[ (int)SMALL_MEMORY_TDA ].value,		\
-      "Set the max size of data eligible for the TDA area"  },		\
-  { "tda-",	&small_memory[ (int)SMALL_MEMORY_TDA ].value, "" },	\
-  { "sda=",	&small_memory[ (int)SMALL_MEMORY_SDA ].value, 		\
-      "Set the max size of data eligible for the SDA area"  },		\
-  { "sda-",	&small_memory[ (int)SMALL_MEMORY_SDA ].value, "" },	\
-  { "zda=",	&small_memory[ (int)SMALL_MEMORY_ZDA ].value, 		\
-      "Set the max size of data eligible for the ZDA area"  },		\
-  { "zda-",	&small_memory[ (int)SMALL_MEMORY_ZDA ].value, "" },	\
-}
-
-/* Sometimes certain combinations of command options do not make
-   sense on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   Don't use this macro to turn on various extra optimizations for
-   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
-#define OVERRIDE_OPTIONS override_options ()
-
-
-/* Show we can debug even without a frame pointer.  */
-#define CAN_DEBUG_WITHOUT_FP
-
-/* Some machines may desire to change what optimizations are
-   performed for various optimization levels.   This macro, if
-   defined, is executed once just after the optimization level is
-   determined and before the remainder of the command options have
-   been parsed.  Values set in this macro are used as the default
-   values for the other command line options.
-
-   LEVEL is the optimization level specified; 2 if `-O2' is
-   specified, 1 if `-O' is specified, and 0 if neither is specified.
-
-   SIZE is non-zero if `-Os' is specified, 0 otherwise.  
-
-   You should not use this macro to change options that are not
-   machine-specific.  These should uniformly selected by the same
-   optimization level on all supported machines.  Use this macro to
-   enable machine-specific optimizations.
-
-   *Do not examine `write_symbols' in this macro!* The debugging
-   options are not supposed to alter the generated code. */
-
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)				\
-{									\
-  if (LEVEL)								\
-    target_flags |= (MASK_EP | MASK_PROLOG_FUNCTION);			\
-}
-
-
-/* Target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is not true on the NEC V850.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* This is not true on the NEC V850.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered.
-   This is not true on the NEC V850.  */
-#define WORDS_BIG_ENDIAN 0
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD		32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD		4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 		32
-
-/* Define this macro if it is advisable to hold scalars in registers
-   in a wider mode than that declared by the program.  In such cases,
-   the value is constrained to be within the bounds of the declared
-   type, but kept valid in the wider mode.  The signedness of the
-   extension may differ from that of the type.
-
-   Some simple experiments have shown that leaving UNSIGNEDP alone
-   generates the best overall code.  */
-
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)  \
-  if (GET_MODE_CLASS (MODE) == MODE_INT \
-      && GET_MODE_SIZE (MODE) < 4)      \
-    { (MODE) = SImode; }
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY		32
-
-/* The stack goes in 32 bit lumps.  */
-#define STACK_BOUNDARY 		32
-
-/* Allocation boundary (in *bits*) for the code of a function.
-   16 is the minimum boundary; 32 would give better performance.  */
-#define FUNCTION_BOUNDARY 16
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT	32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* No structure field wants to be aligned rounder than this.  */
-#define BIGGEST_FIELD_ALIGNMENT 32
-
-/* Define this if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Define this as 1 if `char' should by default be signed; else as 0.
-
-   On the NEC V850, loads do sign extension, so make this default. */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  */
-
-#define FIRST_PSEUDO_REGISTER 34
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.  */
-
-#define FIXED_REGISTERS \
-  { 1, 1, 0, 1, 1, 0, 0, 0, \
-    0, 0, 0, 0, 0, 0, 0, 0, \
-    0, 0, 0, 0, 0, 0, 0, 0, \
-    0, 0, 0, 0, 0, 0, 1, 0, \
-    1, 1}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you
-   like.  */
-
-#define CALL_USED_REGISTERS \
-  { 1, 1, 0, 1, 1, 1, 1, 1, \
-    1, 1, 1, 1, 1, 1, 1, 1, \
-    1, 1, 1, 1, 0, 0, 0, 0, \
-    0, 0, 0, 0, 0, 0, 1, 1, \
-    1, 1}
-
-/* List the order in which to allocate registers.  Each register must be
-   listed once, even those in FIXED_REGISTERS.
-
-   On the 850, we make the return registers first, then all of the volatile
-   registers, then the saved registers in reverse order to better save the
-   registers with an out of line function, and finally the fixed
-   registers.  */
-
-#define REG_ALLOC_ORDER							\
-{									\
-  10, 11,				/* return registers */		\
-  12, 13, 14, 15, 16, 17, 18, 19,	/* scratch registers */		\
-   6,  7,  8,  9, 31,			/* argument registers */	\
-  29, 28, 27, 26, 25, 24, 23, 22,	/* saved registers */		\
-  21, 20,  2,								\
-   0,  1,  3,  4,  5, 30, 32, 33	/* fixed registers */		\
-}
-
-/* CYGNUS LOCAL nickc/ghs */
-/* If TARGET_NO_APP_REGS is not defined then add r2 and r5 to
-   the pool of fixed registers. See PR 14505. */
-#define CONDITIONAL_REGISTER_USAGE  \
-{                                                       \
-  if (TARGET_NO_APP_REGS)                               \
-    {                                                   \
-     fixed_regs[2] = 1;  call_used_regs[2] = 1;         \
-     fixed_regs[5] = 1;  call_used_regs[5] = 1;         \
-    }                                                   \
-}
-/* END CYGNUS LOCAL */
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
-   MODE.  */
-
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((((REGNO) & 1) == 0) || (GET_MODE_SIZE (MODE) <= 4))
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
-  (MODE1 == MODE2 || GET_MODE_SIZE (MODE1) <= 4 && GET_MODE_SIZE (MODE2) <= 4)
-
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-enum reg_class
-{
-  NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
-};
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
-{ "NO_REGS", "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS  			\
-{  0x00000000,		/* No regs      */	\
-   0xffffffff,		/* GENERAL_REGS */    	\
-   0xffffffff,		/* ALL_REGS 	*/	\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO)  GENERAL_REGS
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS NO_REGS
-#define BASE_REG_CLASS  GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) (NO_REGS)
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
- 
-#define REGNO_OK_FOR_BASE_P(regno) \
-  ((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
-
-#define REGNO_OK_FOR_INDEX_P(regno) 0
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)  (CLASS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* The letters I, J, K, L, M, N, O, P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.  */
-
-#define INT_7_BITS(VALUE) ((unsigned) (VALUE) + 0x40 < 0x80)
-#define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100)
-/* zero */
-#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
-/* 5 bit signed immediate */
-#define CONST_OK_FOR_J(VALUE) ((unsigned) (VALUE) + 0x10 < 0x20)
-/* 16 bit signed immediate */
-#define CONST_OK_FOR_K(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000)
-/* valid constant for movhi instruction.  */
-#define CONST_OK_FOR_L(VALUE) \
-  (((unsigned) ((int) (VALUE) >> 16) + 0x8000 < 0x10000) \
-   && CONST_OK_FOR_I ((VALUE & 0xffff)))
-/* 16 bit unsigned immediate */
-#define CONST_OK_FOR_M(VALUE) ((unsigned)(VALUE) < 0x10000)
-/* 5 bit unsigned immediate in shift instructions */
-#define CONST_OK_FOR_N(VALUE) ((unsigned) (VALUE) <= 31)
-
-#define CONST_OK_FOR_O(VALUE) 0
-#define CONST_OK_FOR_P(VALUE) 0
-
-/* CYGNUS LOCAL v850e */
-#undef CONST_OK_FOR_O
-/* 9 bit signed immediate for word multiply instruction.  */
-#define CONST_OK_FOR_O(VALUE) ((unsigned) (VALUE) + 0x10000 < 0x20000)
-/* END CYGNUS LOCAL */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  \
-  ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
-   (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
-   (C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
-   (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
-   (C) == 'M' ? CONST_OK_FOR_M (VALUE) : \
-   (C) == 'N' ? CONST_OK_FOR_N (VALUE) : \
-   (C) == 'O' ? CONST_OK_FOR_O (VALUE) : \
-   (C) == 'P' ? CONST_OK_FOR_P (VALUE) : \
-   0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself. 
-     
-  `G' is a zero of some form.  */
-
-#define CONST_DOUBLE_OK_FOR_G(VALUE)					\
-  ((GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT			\
-    && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))			\
-   || (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_INT			\
-       && CONST_DOUBLE_LOW (VALUE) == 0					\
-       && CONST_DOUBLE_HIGH (VALUE) == 0))
-
-#define CONST_DOUBLE_OK_FOR_H(VALUE) 0
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)				\
-  ((C) == 'G'   ? CONST_DOUBLE_OK_FOR_G (VALUE)				\
-   : (C) == 'H' ? CONST_DOUBLE_OK_FOR_H (VALUE)				\
-   : 0)
-
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-
-#define STARTING_FRAME_OFFSET 0
-
-/* Offset of first parameter from the argument pointer register value.  */
-/* Is equal to the size of the saved fp + pc, even if an fp isn't
-   saved since the value is used before we know.  */
-
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 3
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 32
-
-/* Register containing return address from latest function call.  */
-#define LINK_POINTER_REGNUM 31
-     
-/* On some machines the offset between the frame pointer and starting
-   offset of the automatic variables is not known until after register
-   allocation has been done (for example, because the saved registers
-   are between these two locations).  On those machines, define
-   `FRAME_POINTER_REGNUM' the number of a special, fixed register to
-   be used internally until the offset is known, and define
-   `HARD_FRAME_POINTER_REGNUM' to be actual the hard register number
-   used for the frame pointer.
-
-   You should define this macro only in the very rare circumstances
-   when it is not possible to calculate the offset between the frame
-   pointer and the automatic variables until after register
-   allocation has been completed.  When this macro is defined, you
-   must also indicate in your definition of `ELIMINABLE_REGS' how to
-   eliminate `FRAME_POINTER_REGNUM' into either
-   `HARD_FRAME_POINTER_REGNUM' or `STACK_POINTER_REGNUM'.
-
-   Do not define this macro if it would be the same as
-   `FRAME_POINTER_REGNUM'. */
-#undef  HARD_FRAME_POINTER_REGNUM 
-#define HARD_FRAME_POINTER_REGNUM 29
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 33
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 20
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 0
-
-/* If defined, this macro specifies a table of register pairs used to
-   eliminate unneeded registers that point into the stack frame.  If
-   it is not defined, the only elimination attempted by the compiler
-   is to replace references to the frame pointer with references to
-   the stack pointer.
-
-   The definition of this macro is a list of structure
-   initializations, each of which specifies an original and
-   replacement register.
-
-   On some machines, the position of the argument pointer is not
-   known until the compilation is completed.  In such a case, a
-   separate hard register must be used for the argument pointer.
-   This register can be eliminated by replacing it with either the
-   frame pointer or the argument pointer, depending on whether or not
-   the frame pointer has been eliminated.
-
-   In this case, you might specify:
-        #define ELIMINABLE_REGS  \
-        {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
-         {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
-         {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
-
-   Note that the elimination of the argument pointer with the stack
-   pointer is specified first since that is the preferred elimination. */
-
-#define ELIMINABLE_REGS							\
-{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },			\
- { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },			\
- { ARG_POINTER_REGNUM,	 STACK_POINTER_REGNUM },			\
- { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }}			\
-
-/* A C expression that returns non-zero if the compiler is allowed to
-   try to replace register number FROM-REG with register number
-   TO-REG.  This macro need only be defined if `ELIMINABLE_REGS' is
-   defined, and will usually be the constant 1, since most of the
-   cases preventing register elimination are things that the compiler
-   already knows about. */
-
-#define CAN_ELIMINATE(FROM, TO) \
- ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
-
-/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'.  It
-   specifies the initial difference between the specified pair of
-   registers.  This macro must be defined if `ELIMINABLE_REGS' is
-   defined. */
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
-{									\
-  if ((FROM) == FRAME_POINTER_REGNUM)					\
-    (OFFSET) = get_frame_size () + current_function_outgoing_args_size;	\
-  else if ((FROM) == ARG_POINTER_REGNUM)				\
-   (OFFSET) = compute_frame_size (get_frame_size (), (long *)0);	\
-  else									\
-    abort ();								\
-}
-
-/* A guess for the V850.  */
-#define PROMOTE_PROTOTYPES 1
-
-/* Keep the stack pointer constant throughout the function.  */
-#define ACCUMULATE_OUTGOING_ARGS
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
-
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.  */
-
-#define CUMULATIVE_ARGS struct cum_arg
-struct cum_arg { int nbytes; };
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  function_arg (&CUM, MODE, TYPE, NAMED)
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-  function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM).nbytes = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM).nbytes += ((MODE) != BLKmode			\
-  ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD	\
-  : (int_size_in_bytes (TYPE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD))
-
-/* When a parameter is passed in a register, stack space is still
-   allocated for it.  */
-#define REG_PARM_STACK_SPACE(DECL) (!TARGET_GHS ? 16 : 0)
-
-/* Define this if the above stack space is to be considered part of the
-   space allocated by the caller.  */
-#define OUTGOING_REG_PARM_STACK_SPACE
-
-extern int current_function_anonymous_args;
-/* Do any setup necessary for varargs/stdargs functions.  */
-#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PAS, SECOND) \
-  current_function_anonymous_args = (!TARGET_GHS ? 1 : 0);
-
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)		\
-  ((TYPE) && int_size_in_bytes (TYPE) > 8)
- 
-#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
-  ((TYPE) && int_size_in_bytes (TYPE) > 8)
-
-/* 1 if N is a possible register number for function argument passing.  */
-
-#define FUNCTION_ARG_REGNO_P(N) (N >= 6 && N <= 9)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.   */
-   
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), 10)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-#define LIBCALL_VALUE(MODE) \
-  gen_rtx (REG, MODE, 10)
-
-/* 1 if N is a possible register number for a function value.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 10)
-
-/* Return values > 8 bytes in length in memory.  */
-#define DEFAULT_PCC_STRUCT_RETURN 0
-#define RETURN_IN_MEMORY(TYPE)  \
-  (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode)
-
-/* Register in which address to store a structure value
-   is passed to a function.  On the V850 it's passed as
-   the first parameter.  */
-
-#define STRUCT_VALUE 0
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) ;
-
-#define TRAMPOLINE_TEMPLATE(FILE)			\
-  do {							\
-    fprintf (FILE, "\tjarl .+4,r12\n");			\
-    fprintf (FILE, "\tld.w 12[r12],r5\n");		\
-    fprintf (FILE, "\tld.w 16[r12],r12\n");		\
-    fprintf (FILE, "\tjmp [r12]\n");			\
-    fprintf (FILE, "\tnop\n");				\
-    fprintf (FILE, "\t.long 0\n");			\
-    fprintf (FILE, "\t.long 0\n");			\
-  } while (0)
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 24
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 16)),	\
- 		 (CXT));						\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 20)),	\
-		 (FNADDR));						\
-}
-
-/* Addressing modes, and classification of registers for them.  */
-
-
-/* 1 if X is an rtx for a constant that is a valid address.  */
-
-/* ??? This seems too exclusive.  May get better code by accepting more
-   possibilities here, in particular, should accept ZDA_NAME SYMBOL_REFs.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == CONST_INT				\
-   && CONST_OK_FOR_K (INTVAL (X)))
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) 0
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) 1
-#define REG_OK_FOR_INDEX_P_STRICT(X) 0
-#define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-#define STRICT 0
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) 0
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-#define STRICT 1
-
-#endif
-
-/* A C expression that defines the optional machine-dependent
-   constraint letters that can be used to segregate specific types of
-   operands, usually memory references, for the target machine.
-   Normally this macro will not be defined.  If it is required for a
-   particular target machine, it should return 1 if VALUE corresponds
-   to the operand type represented by the constraint letter C.  If C
-   is not defined as an extra constraint, the value returned should
-   be 0 regardless of VALUE.
-
-   For example, on the ROMP, load instructions cannot have their
-   output in r0 if the memory reference contains a symbolic address.
-   Constraint letter `Q' is defined as representing a memory address
-   that does *not* contain a symbolic address.  An alternative is
-   specified with a `Q' constraint on the input and `r' on the
-   output.  The next alternative specifies `m' on the input and a
-   register class that does not include r0 on the output.  */
-
-/* CYGNUS LOCAL nickc */
-#define EXTRA_CONSTRAINT(OP, C)						\
- ((C) == 'Q'   ? ep_memory_operand (OP, GET_MODE (OP), FALSE)		\
-  : (C) == 'R' ? special_symbolref_operand (OP, VOIDmode)		\
-  : (C) == 'S' ? (GET_CODE (OP) == SYMBOL_REF && ! ZDA_NAME_P (XSTR (OP, 0))) \
-  : (C) == 'T' ? ep_memory_operand (OP, GET_MODE (OP), TRUE)		\
-  : (C) == 'U' ? ((GET_CODE (OP) == SYMBOL_REF && ZDA_NAME_P (XSTR (OP, 0))) \
-		  || (GET_CODE (OP) == CONST				\
-		      && GET_CODE (XEXP (OP, 0)) == PLUS		\
-		      && GET_CODE (XEXP (XEXP (OP, 0), 0)) == SYMBOL_REF \
-		      && ZDA_NAME_P (XSTR (XEXP (XEXP (OP, 0), 0), 0)))) \
-  : 0)
-/* END CYGNUS LOCAL */
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
-   except for CONSTANT_ADDRESS_P which is actually
-   machine-independent.  */
-
-/* Accept either REG or SUBREG where a register is valid.  */
-  
-#define RTX_OK_FOR_BASE_P(X)						\
-  ((REG_P (X) && REG_OK_FOR_BASE_P (X))					\
-   || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))			\
-       && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
-do {									\
-  if (RTX_OK_FOR_BASE_P (X)) goto ADDR;					\
-  if (CONSTANT_ADDRESS_P (X)						\
-      && (MODE == QImode || INTVAL (X) % 2 == 0))			\
-    goto ADDR;								\
-  if (GET_CODE (X) == LO_SUM						\
-      && GET_CODE (XEXP (X, 0)) == REG					\
-      && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
-      && CONSTANT_P (XEXP (X, 1))					\
-      && (GET_CODE (XEXP (X, 1)) != CONST_INT				\
-	  || ((MODE == QImode || INTVAL (XEXP (X, 1)) % 2 == 0)		\
-	      && CONST_OK_FOR_K (INTVAL (XEXP (X, 1)))))		\
-      && GET_MODE_SIZE (MODE) <= GET_MODE_SIZE (word_mode))		\
-    goto ADDR;								\
-  if (special_symbolref_operand (X, MODE)				\
-      && (GET_MODE_SIZE (MODE) <= GET_MODE_SIZE (word_mode)))		\
-     goto ADDR;								\
-  if (GET_CODE (X) == PLUS						\
-      && CONSTANT_ADDRESS_P (XEXP (X, 1))				\
-      && (MODE == QImode || INTVAL (XEXP (X, 1)) % 2 == 0)		\
-      && RTX_OK_FOR_BASE_P (XEXP (X, 0))) goto ADDR;			\
-} while (0)
-
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.   */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)  {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.  */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  {}
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X)					\
-  (GET_CODE (X) == CONST_DOUBLE						\
-   || !(GET_CODE (X) == CONST						\
-	&& GET_CODE (XEXP (X, 0)) == PLUS				\
-	&& GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF		\
-	&& GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT		\
-	&& ! CONST_OK_FOR_K (INTVAL (XEXP (XEXP (X, 0), 1)))))
-
-/* In rare cases, correct code generation requires extra machine
-   dependent processing between the second jump optimization pass and
-   delayed branch scheduling.  On those machines, define this macro
-   as a C statement to act on the code starting at INSN.  */
-
-#define MACHINE_DEPENDENT_REORG(INSN) v850_reorg (INSN)
-
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  No extra ones are needed for the vax.  */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define CC_OVERFLOW_UNUSABLE 0x200
-#define CC_NO_CARRY CC_NO_OVERFLOW
-#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
-
-/* A part of a C `switch' statement that describes the relative costs
-   of constant RTL expressions.  It must contain `case' labels for
-   expression codes `const_int', `const', `symbol_ref', `label_ref'
-   and `const_double'.  Each case must ultimately reach a `return'
-   statement to return the relative cost of the use of that kind of
-   constant value in an expression.  The cost may depend on the
-   precise value of the constant, which is available for examination
-   in X, and the rtx code of the expression in which it is contained,
-   found in OUTER_CODE.
-
-   CODE is the expression code--redundant, since it can be obtained
-   with `GET_CODE (X)'. */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE)				\
-  case CONST_INT:							\
-  case CONST_DOUBLE:							\
-  case CONST:								\
-  case SYMBOL_REF:							\
-  case LABEL_REF:							\
-    {									\
-      int _zxy = const_costs(RTX, CODE);				\
-      return (_zxy) ? COSTS_N_INSNS (_zxy) : 0;				\
-    }
-
-/* A crude cut at RTX_COSTS for the V850.  */
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE. 
-
-   There aren't DImode MOD, DIV or MULT operations, so call them
-   very expensive.  Everything else is pretty much a constant cost.  */
-
-#define RTX_COSTS(RTX,CODE,OUTER_CODE)					\
-  case MOD:								\
-  case DIV:								\
-    return 60;								\
-  case MULT:								\
-    return 20;
-
-/* All addressing modes have the same cost on the V850 series.  */
-#define ADDRESS_COST(ADDR) 1
-
-/* Nonzero if access to memory by bytes or half words is no faster
-   than accessing full words.  */
-#define SLOW_BYTE_ACCESS 1
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-#define SLOW_ZERO_EXTEND 
-
-/* According expr.c, a value of around 6 should minimize code size, and
-   for the V850 series, that's our primary concern.  */
-#define MOVE_RATIO 6
-
-/* Indirect calls are expensive, never turn a direct call
-   into an indirect call.  */
-#define NO_FUNCTION_CSE
-
-/* The four different data regions on the v850.  */
-typedef enum 
-{
-  DATA_AREA_NORMAL,
-  DATA_AREA_SDA,
-  DATA_AREA_TDA,
-  DATA_AREA_ZDA
-} v850_data_area;
-
-/* A list of names for sections other than the standard two, which are
-   `in_text' and `in_data'.  You need not define this macro on a
-   system with no other sections (that GCC needs to use).  */
-#undef	EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_tdata, in_sdata, in_zdata, in_const, in_ctors, \
-in_dtors, in_rozdata, in_rosdata, in_sbss, in_zbss, in_zcommon, in_scommon
-
-/* One or more functions to be defined in `varasm.c'.  These
-   functions should do jobs analogous to those of `text_section' and
-   `data_section', for your additional sections.  Do not define this
-   macro if you do not define `EXTRA_SECTIONS'. */
-#undef	EXTRA_SECTION_FUNCTIONS
-
-/* This could be done a lot more cleanly using ANSI C ... */
-#define EXTRA_SECTION_FUNCTIONS						\
-CONST_SECTION_FUNCTION							\
-CTORS_SECTION_FUNCTION							\
-DTORS_SECTION_FUNCTION							\
-									\
-void									\
-sdata_section ()							\
-{									\
-  if (in_section != in_sdata)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP);		\
-      in_section = in_sdata;						\
-    }									\
-}									\
-									\
-void									\
-rosdata_section ()							\
-{									\
-  if (in_section != in_rosdata)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", ROSDATA_SECTION_ASM_OP);		\
-      in_section = in_sdata;						\
-    }									\
-}									\
-									\
-void									\
-sbss_section ()								\
-{									\
-  if (in_section != in_sbss)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", SBSS_SECTION_ASM_OP);		\
-      in_section = in_sbss;						\
-    }									\
-}									\
-									\
-void									\
-tdata_section ()							\
-{									\
-  if (in_section != in_tdata)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", TDATA_SECTION_ASM_OP);		\
-      in_section = in_tdata;						\
-    }									\
-}									\
-									\
-void									\
-zdata_section ()							\
-{									\
-  if (in_section != in_zdata)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", ZDATA_SECTION_ASM_OP);		\
-      in_section = in_zdata;						\
-    }									\
-}									\
-									\
-void									\
-rozdata_section ()							\
-{									\
-  if (in_section != in_rozdata)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", ROZDATA_SECTION_ASM_OP);		\
-      in_section = in_rozdata;						\
-    }									\
-}									\
-									\
-void									\
-zbss_section ()								\
-{									\
-  if (in_section != in_zbss)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", ZBSS_SECTION_ASM_OP);		\
-      in_section = in_zbss;						\
-    }									\
-}
-
-#define TEXT_SECTION_ASM_OP  "\t.section .text"
-#define DATA_SECTION_ASM_OP  "\t.section .data"
-#define BSS_SECTION_ASM_OP   "\t.section .bss"
-#define SDATA_SECTION_ASM_OP "\t.section .sdata,\"aw\""
-#define SBSS_SECTION_ASM_OP  "\t.section .sbss,\"aw\""
-#define ZDATA_SECTION_ASM_OP "\t.section .zdata,\"aw\""
-#define ZBSS_SECTION_ASM_OP  "\t.section .zbss,\"aw\""
-#define TDATA_SECTION_ASM_OP "\t.section .tdata,\"aw\""
-#define ROSDATA_SECTION_ASM_OP "\t.section .rosdata,\"a\""
-#define ROZDATA_SECTION_ASM_OP "\t.section .rozdata,\"a\""
-
-#define SCOMMON_ASM_OP 	       ".scomm"
-#define ZCOMMON_ASM_OP 	       ".zcomm"
-#define TCOMMON_ASM_OP 	       ".tcomm"
-
-/* A C statement or statements to switch to the appropriate section
-   for output of EXP.  You can assume that EXP is either a `VAR_DECL'
-   node or a constant of some sort.  RELOC indicates whether the
-   initial value of EXP requires link-time relocations.  Select the
-   section by calling `text_section' or one of the alternatives for
-   other sections.
-
-   Do not define this macro if you put all read-only variables and
-   constants in the read-only data section (usually the text section).  */
-#undef  SELECT_SECTION
-#define SELECT_SECTION(EXP, RELOC)					\
-do {									\
-  if (TREE_CODE (EXP) == VAR_DECL)					\
-    {									\
-      int is_const;							\
-      if (!TREE_READONLY (EXP)						\
-	  || TREE_SIDE_EFFECTS (EXP)					\
-	  || !DECL_INITIAL (EXP)					\
-	  || (DECL_INITIAL (EXP) != error_mark_node			\
-	      && !TREE_CONSTANT (DECL_INITIAL (EXP))))			\
-        is_const = FALSE;						\
-      else								\
-        is_const = TRUE;						\
-									\
-      switch (v850_get_data_area (EXP))					\
-        {								\
-        case DATA_AREA_ZDA:						\
-	  if (is_const)	        					\
-	    rozdata_section ();						\
-	  else								\
-	    zdata_section ();						\
-	  break;							\
-									\
-        case DATA_AREA_TDA:						\
-	  tdata_section ();						\
-	  break;							\
-									\
-        case DATA_AREA_SDA:						\
-	  if (is_const)		                        		\
-	    rosdata_section ();						\
-	  else								\
-	    sdata_section ();						\
-	  break;							\
-									\
-        default:							\
-          if (is_const)							\
-	    const_section ();						\
-	  else								\
-	    data_section ();						\
-	  break;							\
-        }								\
-    }									\
-  else if (TREE_CODE (EXP) == STRING_CST)				\
-    {									\
-      if (! flag_writable_strings)					\
-	const_section ();						\
-      else								\
-	data_section ();						\
-    }									\
-									\
-  else									\
-    const_section ();							\
-									\
-} while (0)
-
-/* A C statement or statements to switch to the appropriate section
-   for output of RTX in mode MODE.  You can assume that RTX is some
-   kind of constant in RTL.  The argument MODE is redundant except in
-   the case of a `const_int' rtx.  Select the section by calling
-   `text_section' or one of the alternatives for other sections.
-
-   Do not define this macro if you put all constants in the read-only
-   data section.  */
-/* #define SELECT_RTX_SECTION(MODE, RTX) */
-
-/* Output at beginning/end of assembler file.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) asm_file_start(FILE)
-
-#define ASM_COMMENT_START "#"
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* This is how to output an assembler line defining a `double' constant.
-   It is .double or .float, depending.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.double %s\n", dstr);		\
-   } while (0)
-
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE, VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.float %s\n", dstr);		\
-   } while (0)
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE, VALUE)		\
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE, VALUE)		\
-( fprintf (FILE, "\t.hword "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE, VALUE)		\
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-#define ASM_OUTPUT_BYTE(FILE, VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* This says how to output the assembler to define a global
-   uninitialized but not common symbol.  */
-
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
-
-#undef  ASM_OUTPUT_ALIGNED_BSS 
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-  v850_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
-
-/* This says how to output the assembler to define a global
-   uninitialized, common symbol. */
-#undef  ASM_OUTPUT_ALIGNED_COMMON
-#undef  ASM_OUTPUT_COMMON
-#define ASM_OUTPUT_ALIGNED_DECL_COMMON(FILE, DECL, NAME, SIZE, ALIGN) \
-     v850_output_common (FILE, DECL, NAME, SIZE, ALIGN)
-
-/* This says how to output the assembler to define a local
-   uninitialized symbol. */
-#undef  ASM_OUTPUT_ALIGNED_LOCAL
-#undef  ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(FILE, DECL, NAME, SIZE, ALIGN) \
-     v850_output_local (FILE, DECL, NAME, SIZE, ALIGN)
-     
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE, NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE, NAME)	\
-  do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE, NAME)	          \
-  do {                                            \
-  char* real_name;                                \
-  STRIP_NAME_ENCODING (real_name, (NAME));        \
-  fprintf (FILE, "_%s", real_name);               \
-  } while (0)           
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
-
-/* This is how we tell the assembler that two symbols have the same value.  */
-
-#define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
-  do { assemble_name(FILE, NAME1); 	 \
-       fputs(" = ", FILE);		 \
-       assemble_name(FILE, NAME2);	 \
-       fputc('\n', FILE); } while (0)
-
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES							\
-{  "r0",  "r1",  "r2",  "sp",  "gp",  "r5",  "r6" , "r7",		\
-   "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",		\
-  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",		\
-  "r24", "r25", "r26", "r27", "r28", "r29",  "ep", "r31",		\
-  ".fp", ".ap"}
-
-#define ADDITIONAL_REGISTER_NAMES					\
-{ { "zero",	0 },							\
-  { "hp",	2 },							\
-  { "r3",	3 },							\
-  { "r4",	4 },							\
-  { "tp",	5 },							\
-  { "fp",	29 },							\
-  { "r30",	30 },							\
-  { "lp",	31} }
-
-/* Print an instruction operand X on file FILE.
-   look in v850.c for details */
-
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand (FILE, X, CODE)
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
-  ((CODE) == '.')
-
-/* Print a memory operand whose address is X, on file FILE.
-   This uses a function in output-vax.c.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
-  asm_fprintf (FILE, "\t%s .L%d\n",					\
-	       (TARGET_BIG_SWITCH ? ".long" : ".short"), VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t%s .L%d-.L%d\n",					\
-	   (TARGET_BIG_SWITCH ? ".long" : ".short"),			\
-	   VALUE, REL)
-
-/* CYGNUS LOCAL v850e */
-#undef ASM_OUTPUT_ADDR_DIFF_ELT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-  fprintf (FILE, "\t%s %s.L%d-.L%d%s\n",				\
-	   (TARGET_BIG_SWITCH ? ".long" : ".short"),			\
-	   (! TARGET_BIG_SWITCH && TARGET_V850E ? "(" : ""),		\
-	   VALUE, REL,							\
-	   (! TARGET_BIG_SWITCH && TARGET_V850E ? ")>>1" : ""))
-/* END CYGNUS LOCAL */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", (LOG))
-
-/* We don't have to worry about dbx compatibility for the v850.  */
-#define DEFAULT_GDB_EXTENSIONS 1
-
-/* Use stabs debugging info by default.  */
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-#define DBX_REGISTER_NUMBER(REGNO) REGNO
-
-/* Define to use software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion. */
-#define REAL_ARITHMETIC
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : HImode)
-
-/* Define this if the case instruction drops through after the table
-   when the index is out of range.  Don't define it if the case insn
-   jumps to the default label instead.  */
-/* #define CASE_DROPS_THROUGH */
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE 1
-
-/* The switch instruction requires that the jump table immediately follow
-   it. */
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-/* svr4.h defines this assuming that 4 byte alignment is required.  */
-#undef ASM_OUTPUT_BEFORE_CASE_LABEL
-#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
-  ASM_OUTPUT_ALIGN ((FILE), (TARGET_BIG_SWITCH ? 2 : 1));
-
-#define WORD_REGISTER_OPERATIONS
-
-/* Byte and short loads sign extend the value to a word.  */
-#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.  */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX	4
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-#define STORE_FLAG_VALUE 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
-   is a valid machine specific attribute for DECL.
-   The attributes in ATTRIBUTES have previously been assigned to DECL.  */
-#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
-  v850_valid_machine_decl_attribute (DECL, IDENTIFIER, ARGS)
-
-/* A C statement that assigns default attributes to a newly created DECL.  */
-#define SET_DEFAULT_DECL_ATTRIBUTES(decl, attr) \
-     v850_set_default_decl_attr (decl)
-
-/* Tell compiler we want to support GHS pragmas */
-#define HANDLE_PRAGMA(get, unget, name) v850_handle_pragma (get, unget, name)
-
-enum v850_pragma_state
-{
-  V850_PS_START,
-  V850_PS_SHOULD_BE_DONE,
-  V850_PS_BAD,
-  V850_PS_MAYBE_SECTION_NAME,
-  V850_PS_EXPECTING_EQUALS,
-  V850_PS_EXPECTING_SECTION_ALIAS,
-  V850_PS_MAYBE_COMMA
-};
-
-enum v850_pragma_type
-{
-  V850_PT_UNKNOWN,
-  V850_PT_INTERRUPT,
-  V850_PT_SECTION,
-  V850_PT_START_SECTION,
-  V850_PT_END_SECTION
-};
-
-/* enum GHS_SECTION_KIND is an enumeration of the kinds of sections that
-   can appear in the "ghs section" pragma.  These names are used to index
-   into the GHS_default_section_names[] and GHS_current_section_names[]
-   that are defined in v850.c, and so the ordering of each must remain
-   consistant. 
-
-   These arrays give the default and current names for each kind of 
-   section defined by the GHS pragmas.  The current names can be changed
-   by the "ghs section" pragma.  If the current names are null, use 
-   the default names.  Note that the two arrays have different types.
-
-   For the *normal* section kinds (like .data, .text, etc.) we do not
-   want to explicitly force the name of these sections, but would rather
-   let the linker (or at least the back end) choose the name of the 
-   section, UNLESS the user has force a specific name for these section
-   kinds.  To accomplish this set the name in ghs_default_section_names
-   to null.  */
-
-enum GHS_section_kind
-{ 
-  GHS_SECTION_KIND_DEFAULT,
-
-  GHS_SECTION_KIND_TEXT,
-  GHS_SECTION_KIND_DATA, 
-  GHS_SECTION_KIND_RODATA,
-  GHS_SECTION_KIND_BSS,
-  GHS_SECTION_KIND_SDATA,
-  GHS_SECTION_KIND_ROSDATA,
-  GHS_SECTION_KIND_TDATA,
-  GHS_SECTION_KIND_ZDATA,
-  GHS_SECTION_KIND_ROZDATA,
-
-  COUNT_OF_GHS_SECTION_KINDS  /* must be last */
-};
-
-/* The assembler op to start the file.  */
-
-#define FILE_ASM_OP "\t.file\n"
-
-/* Enable the register move pass to improve code.  */
-#define ENABLE_REGMOVE_PASS
-
-
-/* Implement ZDA, TDA, and SDA */
-
-#define EP_REGNUM 30	/* ep register number */
-
-#define ENCODE_SECTION_INFO(DECL)					\
-do {									\
-  if ((TREE_STATIC (DECL) || DECL_EXTERNAL (DECL))			\
-      && TREE_CODE (DECL) == VAR_DECL)					\
-    v850_encode_data_area (DECL);					\
-} while (0)
-
-#define ZDA_NAME_FLAG_CHAR '@'
-#define TDA_NAME_FLAG_CHAR '%'
-#define SDA_NAME_FLAG_CHAR '&'
-
-#define ZDA_NAME_P(NAME) (*(NAME) == ZDA_NAME_FLAG_CHAR)
-#define TDA_NAME_P(NAME) (*(NAME) == TDA_NAME_FLAG_CHAR)
-#define SDA_NAME_P(NAME) (*(NAME) == SDA_NAME_FLAG_CHAR)
-
-#define ENCODED_NAME_P(SYMBOL_NAME)    \
-  (ZDA_NAME_P (SYMBOL_NAME)            \
-   || TDA_NAME_P (SYMBOL_NAME)         \
-   || SDA_NAME_P (SYMBOL_NAME))
-
-#define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME) \
-     (VAR) = (SYMBOL_NAME) + (ENCODED_NAME_P (SYMBOL_NAME) || *(SYMBOL_NAME) == '*')
-
-/* Define this if you have defined special-purpose predicates in the
-   file `MACHINE.c'.  This macro is called within an initializer of an
-   array of structures.  The first field in the structure is the name
-   of a predicate and the second field is an array of rtl codes.  For
-   each predicate, list all rtl codes that can be in expressions
-   matched by the predicate.  The list should have a trailing comma.  */
-
-#define PREDICATE_CODES							\
-{ "ep_memory_operand",		{ MEM }},				\
-{ "reg_or_0_operand",		{ REG, SUBREG, CONST_INT, CONST_DOUBLE }}, \
-{ "reg_or_int5_operand",	{ REG, SUBREG, CONST_INT }},		\
-{ "call_address_operand",	{ REG, SYMBOL_REF }},			\
-{ "movsi_source_operand",	{ LABEL_REF, SYMBOL_REF, CONST_INT,	\
-				  CONST_DOUBLE, CONST, HIGH, MEM,	\
-				  REG, SUBREG }},			\
-{ "special_symbolref_operand",	{ SYMBOL_REF }},			\
-{ "power_of_two_operand",	{ CONST_INT }},				\
-{ "pattern_is_ok_for_prologue",	{ PARALLEL }},				\
-{ "pattern_is_ok_for_epilogue",	{ PARALLEL }},				\
-{ "register_is_ok_for_epilogue",{ REG }},				\
-/* CYGNUS LOCAL v850e */ 						\
-{ "pattern_is_ok_for_dispose",	{ PARALLEL }},				\
-{ "pattern_is_ok_for_prepare",	{ PARALLEL }},				\
-{ "register_is_ok_for_dispose",	{ REG }},				\
-/* END CYGNUS LOCAL */ 							\
-{ "not_power_of_two_operand",	{ CONST_INT }},
-
-  /* Note, due to dependency and search path conflicts, prototypes
-     involving the FILE, rtx or tree types cannot be included here.
-     They are included at the start of v850.c  */
-  
-extern void   asm_file_start                ();
-extern void   print_operand                 ();
-extern void   print_operand_address         ();
-extern int    function_arg_partial_nregs    ();
-extern int    const_costs                   ();
-extern char * output_move_double            ();
-extern char * output_move_single            ();
-extern int    ep_memory_operand             ();
-extern int    reg_or_0_operand              ();
-extern int    reg_or_int5_operand           ();
-extern int    call_address_operand          ();
-extern int    movsi_source_operand          ();
-extern int    power_of_two_operand          ();
-extern int    not_power_of_two_operand      ();
-extern int    special_symbolref_operand     ();
-extern void   v850_reorg                    ();
-extern void   notice_update_cc              ();
-extern int    v850_valid_machine_decl_attribute ();
-extern int    v850_interrupt_function_p     ();
-extern int    pattern_is_ok_for_prologue    ();
-extern int    pattern_is_ok_for_epilogue    ();
-extern int    register_is_ok_for_epilogue   ();
-extern char * construct_save_jarl           ();
-extern char * construct_restore_jr          ();
-
-extern void   override_options              PROTO ((void));
-extern int    compute_register_save_size    PROTO ((long *));
-extern int    compute_frame_size            PROTO ((int, long *));
-extern void   expand_prologue               PROTO ((void));
-extern void   expand_epilogue               PROTO ((void));
-
-extern void   v850_output_aligned_bss       ();
-extern void   v850_output_common            ();
-extern void   v850_output_local             ();
-extern void   sdata_section                 PROTO ((void));
-extern void   rosdata_section               PROTO ((void));
-extern void   sbss_section                  PROTO ((void));
-extern void   tdata_section                 PROTO ((void));
-extern void   zdata_section                 PROTO ((void));
-extern void   rozdata_section               PROTO ((void));
-extern void   zbss_section                  PROTO ((void));
-extern int    v850_handle_pragma            PROTO ((int (*)(void), void (*)(int), char *));
-extern void   v850_encode_data_area         ();
-extern void   v850_set_default_decl_attr    ();
-extern v850_data_area v850_get_data_area    ();
-/* CYGNUS LOCAL v850e */
-extern int    pattern_is_ok_for_prepare     ();
-extern int    pattern_is_ok_for_dispose     ();
-extern char * construct_dispose_instruction ();
-extern char * construct_prepare_instruction ();
-/* END CYGNUS LOCAL */
diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md
deleted file mode 100755
index 01c56cd..0000000
--- a/gcc/config/v850/v850.md
+++ /dev/null
@@ -1,1813 +0,0 @@
-;; GCC machine description for NEC V850
-;; Copyright (C) 1996, 1997, 1999 Free Software Foundation, Inc.
-
-;;   Contributed by Jeff Law (law@cygnus.com).
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-;; The original PO technology requires these to be ordered by speed,
-;; so that assigner will pick the fastest.
-
-;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;; The V851 manual states that the instruction address space is 16M;
-;; the various branch/call instructions only have a 22bit offset (4M range).
-;;
-;; One day we'll probably need to handle calls to targets more than 4M
-;; away.
-
-;; The size of instructions in bytes.
-
-(define_attr "length" ""
-  (const_int 200))
-
-(define_attr "long_calls" "yes,no"
-  (const (if_then_else (symbol_ref "TARGET_LONG_CALLS")
-		       (const_string "yes")
-		       (const_string "no"))))
-	    
-;; Types of instructions (for scheduling purposes).
-
-(define_attr "type" "load,mult,other"
-  (const_string "other"))
-
-;; Condition code settings.
-;; none - insn does not affect cc
-;; none_0hit - insn does not affect cc but it does modify operand 0
-;;	This attribute is used to keep track of when operand 0 changes.
-;; 	See the description of NOTICE_UPDATE_CC for more info.
-;; set_znv - sets z,n,v to usable values; c is unknown.
-;; set_zn  - sets z,n to usable values; v,c is unknown.
-;; compare - compare instruction
-;; clobber - value of cc is unknown
-(define_attr "cc" "none,none_0hit,set_zn,set_znv,compare,clobber"
-  (const_string "clobber"))
-
-;; Function units for the V850.  As best as I can tell, there's
-;; a traditional memory load/use stall as well as a stall if
-;; the result of a multiply is used too early.
-;;
-(define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0)
-(define_function_unit "mult"   1 0 (eq_attr "type" "mult") 2 0)
-
-
-;; ----------------------------------------------------------------------
-;; MOVE INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; movqi
-
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register or 0 */
-  if (!register_operand (operand0, QImode)
-      && !reg_or_0_operand (operand1, QImode))
-    operands[1] = copy_to_mode_reg (QImode, operand1);
-}")
-
-(define_insn "*movqi_internal"
-  [(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m")
-	(match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
-  "register_operand (operands[0], QImode)
-   || reg_or_0_operand (operands[1], QImode)"
-  "* return output_move_single (operands);"
-  [(set_attr "length" "2,4,2,2,4,4,4")
-   (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
-   (set_attr "type" "other,other,load,other,load,other,other")])
-
-;; movhi
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register or 0 */
-  if (!register_operand (operand0, HImode)
-      && !reg_or_0_operand (operand1, HImode))
-    operands[1] = copy_to_mode_reg (HImode, operand1);
-}")
-
-(define_insn "*movhi_internal"
-  [(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m")
-	(match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
-  "register_operand (operands[0], HImode)
-   || reg_or_0_operand (operands[1], HImode)"
-  "* return output_move_single (operands);"
-  [(set_attr "length" "2,4,2,2,4,4,4")
-   (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
-   (set_attr "type" "other,other,load,other,load,other,other")])
-
-;; movsi and helpers
-
-(define_insn "*movsi_high"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(high:SI (match_operand 1 "" "")))]
-  ""
-  "movhi hi(%1),%.,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")
-   (set_attr "type" "other")])
-
-(define_insn "*movsi_lo"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
-		   (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "movea lo(%2),%1,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")
-   (set_attr "type" "other")])
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register or 0 */
-  if (!register_operand (operand0, SImode)
-      && !reg_or_0_operand (operand1, SImode))
-    operands[1] = copy_to_mode_reg (SImode, operand1);
-
-  /* Some constants, as well as symbolic operands
-     must be done with HIGH & LO_SUM patterns.  */
-  if (CONSTANT_P (operands[1])
-      && GET_CODE (operands[1]) != HIGH
-/* CYGNUS LOCAL v850e */
-      && ! TARGET_V850E
-/* END CYGNUS LOCAL */
-      && !special_symbolref_operand (operands[1], VOIDmode)
-      && !(GET_CODE (operands[1]) == CONST_INT
-	   && (CONST_OK_FOR_J (INTVAL (operands[1]))
-	       || CONST_OK_FOR_K (INTVAL (operands[1]))
-	       || CONST_OK_FOR_L (INTVAL (operands[1])))))
-    {
-      rtx high;
-      rtx temp;
-
-      if (reload_in_progress || reload_completed)
-        temp = operands[0];
-      else
-	temp = gen_reg_rtx (SImode);
-
-      emit_insn (gen_rtx (SET, SImode, temp,
-                          gen_rtx (HIGH, SImode, operand1)));
-      emit_insn (gen_rtx (SET, SImode, operand0,
-                          gen_rtx (LO_SUM, SImode, temp, operand1)));
-      DONE;
-    }
-}")
-
-;; CYGNUS LOCAL v850e
-;; This is the same as the following pattern, except that it includes
-;; support for arbitrary 32 bit immediates.
-
-;; ??? This always loads addresses using hilo.  If the only use of this address
-;; was in a load/store, then we would get smaller code if we only loaded the
-;; upper part with hi, and then put the lower part in the load/store insn.
-
-(define_insn "*movsi_internal_v850e"
-  [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m,r")
-	(match_operand:SI 1 "general_operand" "Jr,K,L,Q,Ir,m,R,r,I,i"))]
-  "TARGET_V850E
-   && (register_operand (operands[0], SImode)
-       || reg_or_0_operand (operands[1], SImode))"
-  "* return output_move_single (operands);"
-  [(set_attr "length" "2,4,4,2,2,4,4,4,4,6")
-   (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
-   (set_attr "type" "other,other,other,load,other,load,other,other,other,other")])
-;; END CYGNUS LOCAL 
-
-(define_insn "*movsi_internal"
-  [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m")
-	(match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))]
-  "register_operand (operands[0], SImode)
-   || reg_or_0_operand (operands[1], SImode)"
-  "* return output_move_single (operands);"
-  [(set_attr "length" "2,4,4,2,2,4,4,4,4")
-   (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
-   (set_attr "type" "other,other,other,load,other,load,other,other,other")])
-
-
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register or 0 */
-  if (!register_operand (operand0, DImode)
-      && !reg_or_0_operand (operand1, DImode))
-    operands[1] = copy_to_mode_reg (DImode, operand1);
-}")
-
-(define_insn "*movdi_internal"
-  [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,m,r")
-	(match_operand:DI 1 "general_operand" "Jr,K,L,i,m,r,IG,iF"))]
-  "register_operand (operands[0], DImode)
-   || reg_or_0_operand (operands[1], DImode)"
-  "* return output_move_double (operands);"
-  [(set_attr "length" "4,8,8,16,8,8,8,16")
-   (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
-   (set_attr "type" "other,other,other,other,load,other,other,other")])
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "general_operand" "")
-	(match_operand:SF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register or 0 */
-  if (!register_operand (operand0, SFmode)
-      && !reg_or_0_operand (operand1, SFmode))
-    operands[1] = copy_to_mode_reg (SFmode, operand1);
-}")
-
-(define_insn "*movsf_internal"
-  [(set (match_operand:SF 0 "general_operand" "=r,r,r,r,r,Q,r,m,m,r")
-	(match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))]
-  "register_operand (operands[0], SFmode)
-   || reg_or_0_operand (operands[1], SFmode)"
-  "* return output_move_single (operands);"
-  [(set_attr "length" "2,4,4,8,2,2,4,4,4,8")
-   (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
-   (set_attr "type" "other,other,other,other,load,other,load,other,other,other")])
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "general_operand" "")
-	(match_operand:DF 1 "general_operand" ""))]
-  ""
-  "
-{
-  /* One of the ops has to be in a register or 0 */
-  if (!register_operand (operand0, DFmode)
-      && !reg_or_0_operand (operand1, DFmode))
-    operands[1] = copy_to_mode_reg (DFmode, operand1);
-}")
-
-(define_insn "*movdf_internal"
-  [(set (match_operand:DF 0 "general_operand" "=r,r,r,r,r,m,m,r")
-	(match_operand:DF 1 "general_operand" "Jr,K,L,i,m,r,IG,iF"))]
-  "register_operand (operands[0], DFmode)
-   || reg_or_0_operand (operands[1], DFmode)"
-  "* return output_move_double (operands);"
-  [(set_attr "length" "4,8,8,16,8,8,8,16")
-   (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
-   (set_attr "type" "other,other,other,other,load,other,other,other")])
-
-
-;; ----------------------------------------------------------------------
-;; TEST INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "*v850_tst1"
-  [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
-                               (const_int 1)
-                               (match_operand:QI 1 "const_int_operand" "n")))]
-  ""
-  "tst1 %1,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-;; This replaces ld.b;sar;andi with tst1;setf nz.
-
-;; ??? The zero_extract sets the Z bit to the opposite of what one would
-;; expect.  This perhaps should be wrapped in a (eq: X (const_int 0)).
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(zero_extract:SI (match_operand:QI 1 "memory_operand" "")
-			 (const_int 1)
-			 (match_operand 2 "const_int_operand" "")))]
-  ""
-  [(set (cc0) (zero_extract:SI (match_dup 1)
-			       (const_int 1)
-			       (match_dup 2)))
-   (set (match_dup 0) (ne:SI (cc0) (const_int 0)))])
-
-(define_insn "tstsi"
-  [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
-  ""
-  "cmp %.,%0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_znv")])
-
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "register_operand" "r,r")
-		 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
-  ""
-  "@
-  cmp %1,%0
-  cmp %1,%0"
-  [(set_attr "length" "2,2")
-   (set_attr "cc" "compare")])
-
-;; ----------------------------------------------------------------------
-;; ADD INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,r,r")
-		 (match_operand:SI 2 "nonmemory_operand" "rJ,K,U")))]
-  ""
-  "@
-   add %2,%0
-   addi %2,%1,%0
-   addi %O2(%P2),%1,%0"
-  [(set_attr "length" "2,4,4")
-   (set_attr "cc" "set_zn,set_zn,set_zn")])
-
-;; ----------------------------------------------------------------------
-;; SUBTRACT INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(minus:SI (match_operand:SI 1 "register_operand" "0,r")
-		  (match_operand:SI 2 "register_operand" "r,0")))]
-  ""
-  "@
-  sub %2,%0
-  subr %1,%0"
-  [(set_attr "length" "2,2")
-   (set_attr "cc" "set_zn")])
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (neg:SI (match_operand:SI 1 "register_operand" "0")))]
-  ""
-  "subr %.,%0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-;; ----------------------------------------------------------------------
-;; MULTIPLY INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_expand "mulhisi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(mult:SI
-	  (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
-	  (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))]
-  ""
-  "")
-
-(define_insn "*mulhisi3_internal1"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI
-	  (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
-	  (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
-  ""
-  "mulh %2,%0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none_0hit")
-   (set_attr "type" "mult")])
-
-;; ??? Sign extending constants isn't valid.  Fix?
-
-(define_insn "*mulhisi3_internal2"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(mult:SI
-	  (sign_extend:SI (match_operand:HI 1 "register_operand" "%0,r"))
-	  (sign_extend:SI (match_operand 2 "const_int_operand" "J,K"))))]
-  ""
-  "@
-   mulh %2,%0
-   mulhi %2,%1,%0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "none_0hit,none_0hit")
-   (set_attr "type" "mult")])
-
-;; CYGNUS LOCAL v850e
-
-;; ??? The scheduling info is probably wrong.
-
-;; ??? This instruction can also generate the 32 bit highpart, but using it
-;; may increase code size counter to the desired result.
-
-;; ??? This instructions can also give a DImode result.
-
-;; ??? There is unsigned version, but it matters only for the DImode/highpart
-;; results.
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(mult:SI (match_operand:SI 1 "register_operand" "%0")
-		 (match_operand:SI 2 "register_operand" "rO")))]
-  "TARGET_V850E"
-  "mul %2,%1,%."
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")
-   (set_attr "type" "mult")])
-
-;; ----------------------------------------------------------------------
-;; DIVIDE INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; ??? These insns do set the Z/N condition codes, except that they are based
-;; on only one of the two results, so it doesn't seem to make sense to use
-;; them.
-
-;; ??? The scheduling info is probably wrong.
-
-(define_insn "divmodsi4"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(div:SI (match_operand:SI 1 "register_operand" "0")
-		(match_operand:SI 2 "register_operand" "r")))
-   (set (match_operand:SI 3 "register_operand" "=r")
-	(mod:SI (match_dup 1)
-		(match_dup 2)))]
-  "TARGET_V850E"
-  "div %2,%0,%3"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")
-   (set_attr "type" "other")])
-	
-(define_insn "udivmodsi4"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(udiv:SI (match_operand:SI 1 "register_operand" "0")
-		 (match_operand:SI 2 "register_operand" "r")))
-   (set (match_operand:SI 3 "register_operand" "=r")
-	(umod:SI (match_dup 1)
-		 (match_dup 2)))]
-  "TARGET_V850E"
-  "divu %2,%0,%3"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")
-   (set_attr "type" "other")])
-	
-;; ??? There is a 2 byte instruction for generating only the quotient.
-;; However, it isn't clear how to compute the length field correctly.
-
-(define_insn "divmodhi4"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(div:HI (match_operand:HI 1 "register_operand" "0")
-		(match_operand:HI 2 "register_operand" "r")))
-   (set (match_operand:HI 3 "register_operand" "=r")
-	(mod:HI (match_dup 1)
-		(match_dup 2)))]
-  "TARGET_V850E"
-  "divh %2,%0,%3"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")
-   (set_attr "type" "other")])
-
-;; Half-words are sign-extended by default, so we must zero extend to a word
-;; here before doing the divide.
-
-(define_insn "udivmodhi4"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(udiv:HI (match_operand:HI 1 "register_operand" "0")
-		 (match_operand:HI 2 "register_operand" "r")))
-   (set (match_operand:HI 3 "register_operand" "=r")
-	(umod:HI (match_dup 1)
-		 (match_dup 2)))]
-  "TARGET_V850E"
-  "zxh %0\;divhu %2,%0,%3"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")
-   (set_attr "type" "other")])
-;; END CYGNUS LOCAL 
-
-;; ----------------------------------------------------------------------
-;; AND INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "*v850_clr1_1"
-  [(set (match_operand:QI 0 "memory_operand" "=m")
-	(subreg:QI
-	  (and:SI (subreg:SI (match_dup 0) 0)
-		  (match_operand:QI 1 "not_power_of_two_operand" "")) 0))]
-  ""
-  "*
-{
-  rtx xoperands[2];
-  xoperands[0] = operands[0];
-  xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff);
-  output_asm_insn (\"clr1 %M1,%0\", xoperands);
-  return \"\";
-}"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "*v850_clr1_2"
-  [(set (match_operand:HI 0 "indirect_operand" "=m")
-	(subreg:HI
-	  (and:SI (subreg:SI (match_dup 0) 0)
-		  (match_operand:HI 1 "not_power_of_two_operand" "")) 0))]
-  ""
-  "*
-{
-  int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff);
-
-  rtx xoperands[2];
-  xoperands[0] = gen_rtx (MEM, QImode,
-			  plus_constant (XEXP (operands[0], 0), log2 / 8));
-  xoperands[1] = GEN_INT (log2 % 8);
-  output_asm_insn (\"clr1 %1,%0\", xoperands);
-  return \"\";
-}"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "*v850_clr1_3"
-  [(set (match_operand:SI 0 "indirect_operand" "=m")
-	(and:SI (match_dup 0)
-		(match_operand:SI 1 "not_power_of_two_operand" "")))]
-  ""
-  "*
-{
-  int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff);
-
-  rtx xoperands[2];
-  xoperands[0] = gen_rtx (MEM, QImode,
-			  plus_constant (XEXP (operands[0], 0), log2 / 8));
-  xoperands[1] = GEN_INT (log2 % 8);
-  output_asm_insn (\"clr1 %1,%0\", xoperands);
-  return \"\";
-}"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
-		(match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
-  ""
-  "@
-  and %2,%0
-  and %.,%0
-  andi %2,%1,%0"
-  [(set_attr "length" "2,2,4")
-   (set_attr "cc" "set_znv")])
-
-;; ----------------------------------------------------------------------
-;; OR INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "*v850_set1_1"
-  [(set (match_operand:QI 0 "memory_operand" "=m")
-	(subreg:QI (ior:SI (subreg:SI (match_dup 0) 0)
-			   (match_operand 1 "power_of_two_operand" "")) 0))]
-  ""
-  "set1 %M1,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "*v850_set1_2"
-  [(set (match_operand:HI 0 "indirect_operand" "=m")
-	(subreg:HI (ior:SI (subreg:SI (match_dup 0) 0)
-			   (match_operand 1 "power_of_two_operand" "")) 0))]
-  ""
-  "*
-{
-  int log2 = exact_log2 (INTVAL (operands[1]));
-
-  if (log2 < 8)
-    return \"set1 %M1,%0\";
-  else
-    {
-      rtx xoperands[2];
-      xoperands[0] = gen_rtx (MEM, QImode,
-			      plus_constant (XEXP (operands[0], 0), log2 / 8));
-      xoperands[1] = GEN_INT (log2 % 8);
-      output_asm_insn (\"set1 %1,%0\", xoperands);
-    }
-  return \"\";
-}"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "*v850_set1_3"
-  [(set (match_operand:SI 0 "indirect_operand" "=m")
-	(ior:SI (match_dup 0)
-		(match_operand 1 "power_of_two_operand" "")))]
-  ""
-  "*
-{
-  int log2 = exact_log2 (INTVAL (operands[1]));
-
-  if (log2 < 8)
-    return \"set1 %M1,%0\";
-  else
-    {
-      rtx xoperands[2];
-      xoperands[0] = gen_rtx (MEM, QImode,
-			      plus_constant (XEXP (operands[0], 0), log2 / 8));
-      xoperands[1] = GEN_INT (log2 % 8);
-      output_asm_insn (\"set1 %1,%0\", xoperands);
-    }
-  return \"\";
-}"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
-		(match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
-  ""
-  "@
-  or %2,%0
-  or %.,%0
-  ori %2,%1,%0"
-  [(set_attr "length" "2,2,4")
-   (set_attr "cc" "set_znv")])
-
-;; ----------------------------------------------------------------------
-;; XOR INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "*v850_not1_1"
-  [(set (match_operand:QI 0 "memory_operand" "=m")
-	(subreg:QI (xor:SI (subreg:SI (match_dup 0) 0)
-			   (match_operand 1 "power_of_two_operand" "")) 0))]
-  ""
-  "not1 %M1,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "*v850_not1_2"
-  [(set (match_operand:HI 0 "indirect_operand" "=m")
-	(subreg:HI (xor:SI (subreg:SI (match_dup 0) 0)
-			   (match_operand 1 "power_of_two_operand" "")) 0))]
-  ""
-  "*
-{
-  int log2 = exact_log2 (INTVAL (operands[1]));
-
-  if (log2 < 8)
-    return \"not1 %M1,%0\";
-  else
-    {
-      rtx xoperands[2];
-      xoperands[0] = gen_rtx (MEM, QImode,
-			      plus_constant (XEXP (operands[0], 0), log2 / 8));
-      xoperands[1] = GEN_INT (log2 % 8);
-      output_asm_insn (\"not1 %1,%0\", xoperands);
-    }
-  return \"\";
-}"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "*v850_not1_3"
-  [(set (match_operand:SI 0 "indirect_operand" "=m")
-	(xor:SI (match_dup 0)
-		(match_operand 1 "power_of_two_operand" "")))]
-  ""
-  "*
-{
-  int log2 = exact_log2 (INTVAL (operands[1]));
-
-  if (log2 < 8)
-    return \"not1 %M1,%0\";
-  else
-    {
-      rtx xoperands[2];
-      xoperands[0] = gen_rtx (MEM, QImode,
-			      plus_constant (XEXP (operands[0], 0), log2 / 8));
-      xoperands[1] = GEN_INT (log2 % 8);
-      output_asm_insn (\"not1 %1,%0\", xoperands);
-    }
-  return \"\";
-}"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
-		(match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
-  ""
-  "@
-  xor %2,%0
-  xor %.,%0
-  xori %2,%1,%0"
-  [(set_attr "length" "2,2,4")
-   (set_attr "cc" "set_znv")])
-
-;; ----------------------------------------------------------------------
-;; NOT INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "not %1,%0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_znv")])
-
-;; -----------------------------------------------------------------
-;; BIT FIELDS
-;; -----------------------------------------------------------------
-
-;; ??? Is it worth defining insv and extv for the V850 series?!?
-
-;; An insv pattern would be useful, but does not get used because
-;; store_bit_field never calls insv when storing a constant value into a
-;; single-bit bitfield.
-
-;; extv/extzv patterns would be useful, but do not get used because
-;; optimize_bitfield_compare in fold-const usually converts single
-;; bit extracts into an AND with a mask.
-
-;; -----------------------------------------------------------------
-;; Scc INSTRUCTIONS
-;; -----------------------------------------------------------------
-
-(define_insn "sle"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (le:SI (cc0) (const_int 0)))]
-  ""
-  "*
-{
-  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
-    return 0;
-
-  return \"setf le,%0\";
-}"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")])
-
-(define_insn "sleu"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (leu:SI (cc0) (const_int 0)))]
-  ""
-  "setf nh,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")])
-
-(define_insn "sge"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (ge:SI (cc0) (const_int 0)))]
-  ""
-  "*
-{
-  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
-    return 0;
-
-  return \"setf ge,%0\";
-}"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")])
-
-(define_insn "sgeu"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (geu:SI (cc0) (const_int 0)))]
-  ""
-  "setf nl,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")])
-
-(define_insn "slt"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (lt:SI (cc0) (const_int 0)))]
-  ""
-  "*
-{
-  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
-    return 0;
-
-  return \"setf lt,%0\";
-}"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")])
-
-(define_insn "sltu"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (ltu:SI (cc0) (const_int 0)))]
-  ""
-  "setf l,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")])
-
-(define_insn "sgt"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (gt:SI (cc0) (const_int 0)))]
-  ""
-  "*
-{
-  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
-    return 0;
-
-  return \"setf gt,%0\";
-}"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")])
-
-(define_insn "sgtu"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (gtu:SI (cc0) (const_int 0)))]
-  ""
-  "setf h,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")])
-
-(define_insn "seq"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (eq:SI (cc0) (const_int 0)))]
-  ""
-  "setf z,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")])
-
-(define_insn "sne"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (ne:SI (cc0) (const_int 0)))]
-  ""
-  "setf nz,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "none_0hit")])
-
-;; CYGNUS LOCAL v850e
-;; ----------------------------------------------------------------------
-;; CONDITIONAL MOVE INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; Instructions using cc0 aren't allowed to have input reloads, so we must
-;; hide the fact that this instruction uses cc0.  We do so by including the
-;; compare instruction inside it.
-
-;; ??? This is very ugly.  The right way to do this is to modify cmpsi so
-;; that it doesn't emit RTL, and then modify the bcc/scc patterns so that
-;; they emit RTL for the compare instruction.  Unfortunately, this requires
-;; lots of changes that will be hard to sanitise.  So for now, cmpsi still
-;; emits RTL, and I get the compare operands here from the previous insn.
-
-(define_expand "movsicc"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(if_then_else:SI
-	 (match_operator 1 "comparison_operator"
-			 [(match_dup 4) (match_dup 5)])
-	 (match_operand:SI 2 "reg_or_int5_operand" "rJ")
-	 (match_operand:SI 3 "reg_or_0_operand" "rI")))]
-  "TARGET_V850E"
-  "
-{
-  rtx insn = get_last_insn_anywhere ();
-  if (GET_CODE (insn) == INSN
-      && GET_CODE (PATTERN (insn)) == SET
-      && SET_DEST (PATTERN (insn)) == cc0_rtx)
-    {
-      rtx src = SET_SRC (PATTERN (insn));
-
-      if (GET_CODE (src) == COMPARE)
-	{
-	  operands[4] = XEXP (src, 0);
-	  operands[5] = XEXP (src, 1);
-	}
-      else if (GET_CODE (src) == REG)
-	{
-	  operands[4] = src;
-	  operands[5] = const0_rtx;
-	}
-      else
-	abort ();
-    }
-  else
-    abort ();
-}")
-
-;; ??? Clobbering the condition codes is overkill.
-
-;; ??? We sometimes emit an unnecessary compare instruction because the
-;; condition codes may have already been set by an earlier instruction,
-;; but we have no code here to avoid the compare if it is unnecessary.
-
-(define_insn "*movsicc_normal"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(if_then_else:SI
-	 (match_operator 1 "comparison_operator"
-			 [(match_operand:SI 4 "register_operand" "r")
-			  (match_operand:SI 5 "reg_or_int5_operand" "rJ")])
-	 (match_operand:SI 2 "reg_or_int5_operand" "rJ")
-	 (match_operand:SI 3 "reg_or_0_operand" "rI")))]
-  "TARGET_V850E"
-  "cmp %5,%4\;cmov %c1,%2,%z3,%0"
-  [(set_attr "length" "6")
-   (set_attr "cc" "clobber")])
-
-(define_insn "*movsicc_reversed"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(if_then_else:SI
-	 (match_operator 1 "comparison_operator"
-			 [(match_operand:SI 4 "register_operand" "r")
-			  (match_operand:SI 5 "reg_or_int5_operand" "rJ")])
-	 (match_operand:SI 2 "reg_or_0_operand" "rI")
-	 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))]
-  "TARGET_V850E"
-  "cmp %5,%4\;cmov %C1,%3,%z2,%0"
-  [(set_attr "length" "6")
-   (set_attr "cc" "clobber")])
-
-(define_insn "*movsicc_tst1"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(if_then_else:SI
-	 (match_operator 1 "comparison_operator"
-			 [(zero_extract:SI
-			   (match_operand:QI 2 "memory_operand" "m")
-			   (const_int 1)
-			   (match_operand 3 "const_int_operand" "n"))
-			  (const_int 0)])
-	 (match_operand:SI 4 "reg_or_int5_operand" "rJ")
-	 (match_operand:SI 5 "reg_or_0_operand" "rI")))]
-  "TARGET_V850E"
-  "tst1 %3,%2\;cmov %c1,%4,%z5,%0"
-  [(set_attr "length" "8")
-   (set_attr "cc" "clobber")])
-
-(define_insn "*movsicc_tst1_reversed"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(if_then_else:SI
-	 (match_operator 1 "comparison_operator"
-			 [(zero_extract:SI
-			   (match_operand:QI 2 "memory_operand" "m")
-			   (const_int 1)
-			   (match_operand 3 "const_int_operand" "n"))
-			  (const_int 0)])
-	 (match_operand:SI 4 "reg_or_0_operand" "rI")
-	 (match_operand:SI 5 "reg_or_int5_operand" "rJ")))]
-  "TARGET_V850E"
-  "tst1 %3,%2\;cmov %C1,%5,%z4,%0"
-  [(set_attr "length" "8")
-   (set_attr "cc" "clobber")])
-
-;; Matching for sasf requires combining 4 instructions, so we provide a
-;; dummy pattern to match the first 3, which will always be turned into the
-;; second pattern by subsequent combining.  As above, we must include the
-;; comparison to avoid input reloads in an insn using cc0.
-
-(define_insn "*sasf_1"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(ior:SI (match_operator 1 "comparison_operator" [(cc0) (const_int 0)])
-		(ashift:SI (match_operand:SI 2 "register_operand" "")
-			   (const_int 1))))]
-  "TARGET_V850E"
-  "* abort ();")
-
-(define_insn "*sasf_2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI
-	 (match_operator 1 "comparison_operator"
-			 [(match_operand:SI 3 "register_operand" "r")
-			  (match_operand:SI 4 "reg_or_int5_operand" "rJ")])
-	 (ashift:SI (match_operand:SI 2 "register_operand" "0")
-		    (const_int 1))))]
-  "TARGET_V850E"
-  "cmp %4,%3\;sasf %c1,%0"
-  [(set_attr "length" "6")
-   (set_attr "cc" "clobber")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(if_then_else:SI
-	 (match_operator 1 "comparison_operator"
-			 [(match_operand:SI 4 "register_operand" "")
-			  (match_operand:SI 5 "reg_or_int5_operand" "")])
-	 (match_operand:SI 2 "const_int_operand" "")
-	 (match_operand:SI 3 "const_int_operand" "")))]
-  "TARGET_V850E
-   && ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1)
-   && REGNO (operands[0]) != REGNO (operands[4])"
-  [(set (match_dup 0) (match_dup 6))
-   (set (match_dup 0)
-	(ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)])
-		(ashift:SI (match_dup 0) (const_int 1))))]
-  "
-{
-  operands[6] = GEN_INT (INTVAL (operands[2]) >> 1);
-  if (INTVAL (operands[2]) & 0x1)
-    operands[7] = operands[1];
-  else
-    operands[7] = gen_rtx (reverse_condition (GET_CODE (operands[1])),
-			   GET_MODE (operands[1]), XEXP (operands[1], 0),
-			   XEXP (operands[1], 1));
-}")
-;; ---------------------------------------------------------------------
-;; BYTE SWAP INSTRUCTIONS
-;; ---------------------------------------------------------------------
-
-(define_expand "rotlhi3"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(rotate:HI (match_operand:HI 1 "register_operand" "")
-		   (match_operand:HI 2 "const_int_operand" "")))]
-  "TARGET_V850E"
-  "
-{
-  if (INTVAL (operands[2]) != 8)
-    FAIL;
-}")
-
-(define_insn "*rotlhi3_8"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(rotate:HI (match_operand:HI 1 "register_operand" "r")
-		   (const_int 8)))]
-  "TARGET_V850E"
-  "bsh %1,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-(define_expand "rotlsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(rotate:SI (match_operand:SI 1 "register_operand" "")
-		   (match_operand:SI 2 "const_int_operand" "")))]
-  "TARGET_V850E"
-  "
-{
-  if (INTVAL (operands[2]) != 16)
-    FAIL;
-}")
-
-(define_insn "*rotlsi3_16"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(rotate:SI (match_operand:SI 1 "register_operand" "r")
-		   (const_int 16)))]
-  "TARGET_V850E"
-  "hsw %1,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-;; END CYGNUS LOCAL
-
-;; ----------------------------------------------------------------------
-;; JUMP INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; Conditional jump instructions
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_insn "*branch_normal"
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "*
-{
-  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
-      && (GET_CODE (operands[1]) == GT
-	  || GET_CODE (operands[1]) == GE
-	  || GET_CODE (operands[1]) == LE
-	  || GET_CODE (operands[1]) == LT))
-    return 0;
-
-  if (get_attr_length (insn) == 2)
-    return \"b%b1 %l0\";
-  else
-    return \"b%B1 .+6\;jr %l0\";
-}"
- [(set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 0) (pc)))
-		      (const_int 256))
-		  (const_int 2)
-		  (const_int 6)))
-  (set_attr "cc" "none")])
-
-(define_insn "*branch_invert"
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
-      && (GET_CODE (operands[1]) == GT
-	  || GET_CODE (operands[1]) == GE
-	  || GET_CODE (operands[1]) == LE
-	  || GET_CODE (operands[1]) == LT))
-    return 0;
-  if (get_attr_length (insn) == 2)
-    return \"b%B1 %l0\";
-  else
-    return \"b%b1 .+6\;jr %l0\";
-}"
- [(set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 0) (pc)))
-		      (const_int 256))
-		  (const_int 2)
-		  (const_int 6)))
-  (set_attr "cc" "none")])
-
-;; Unconditional and other jump instructions.
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "*
-{
-  if (get_attr_length (insn) == 2)
-    return \"br %0\";
-  else
-    return \"jr %0\";
-}"
- [(set (attr "length")
-    (if_then_else (lt (abs (minus (match_dup 0) (pc)))
-		      (const_int 256))
-		  (const_int 2)
-		  (const_int 4)))
-  (set_attr "cc" "none")])
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
-  ""
-  "jmp %0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none")])
-
-(define_insn "tablejump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jmp  %0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none")])
-
-;; CYGNUS LOCAL v850e
-(define_insn "switch"
-  [(set (pc)
-	(plus:SI
-	 (sign_extend:SI
-	  (mem:HI
-	   (plus:SI (ashift:SI (match_operand:SI 0 "register_operand" "r")
-			       (const_int 1))
-		    (label_ref (match_operand:SI 1 "" "")))))
-	 (label_ref (match_dup 1))))]
-  "TARGET_V850E"
-  "switch %0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none")])
-
-;; END CYGNUS LOCAL
-(define_expand "casesi"
-  [(match_operand:SI 0 "register_operand" "")
-   (match_operand:SI 1 "register_operand" "")
-   (match_operand:SI 2 "register_operand" "")
-   (match_operand 3 "" "") (match_operand 4 "" "")]
-  ""
-  "
-{
-  rtx reg = gen_reg_rtx (SImode);
-  rtx tableaddress = gen_reg_rtx (SImode);
-  rtx mem;
-
-  /* Subtract the lower bound from the index.  */
-  emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
-  /* Compare the result against the number of table entries.  */
-  emit_insn (gen_cmpsi (reg, operands[2]));
-  /* Branch to the default label if out of range of the table.  */
-  emit_jump_insn (gen_bgtu (operands[4]));
-
-/* CYGNUS LOCAL v850e */
-  if (! TARGET_BIG_SWITCH && TARGET_V850E)
-    {
-      emit_jump_insn (gen_switch (reg, operands[3]));
-      DONE;
-    }
-
-/* END CYGNUS LOCAL */
-  /* Shift index for the table array access.  */
-  emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1)));
-  /* Load the table address into a pseudo.  */
-  emit_insn (gen_movsi (tableaddress,
-			gen_rtx (LABEL_REF, VOIDmode, operands[3])));
-  /* Add the table address to the index.  */
-  emit_insn (gen_addsi3 (reg, reg, tableaddress));
-  /* Load the table entry.  */
-  mem = gen_rtx (MEM, CASE_VECTOR_MODE, reg);
-  RTX_UNCHANGING_P (mem);
-  if (! TARGET_BIG_SWITCH)
-    {
-      rtx reg2 = gen_reg_rtx (HImode);
-      emit_insn (gen_movhi (reg2, mem));
-      emit_insn (gen_extendhisi2 (reg, reg2));
-    }
-  else
-    emit_insn (gen_movsi (reg, mem));
-  /* Add the table address.  */
-  emit_insn (gen_addsi3 (reg, reg, tableaddress));
-  /* Branch to the switch label.  */
-  emit_jump_insn (gen_tablejump (reg, operands[3]));
-  DONE;
-}")
-
-;; Call subroutine with no return value.
-
-(define_expand "call"
-  [(call (match_operand:QI 0 "general_operand" "")
-	 (match_operand:SI 1 "general_operand" ""))]
-  ""
-  "
-{
-  if (! call_address_operand (XEXP (operands[0], 0))
-      || TARGET_LONG_CALLS)
-    XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
-  if (TARGET_LONG_CALLS)
-    emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1]));
-  else
-    emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1]));
-  
-  DONE;
-}")
-
-(define_insn "call_internal_short"
-  [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
-	 (match_operand:SI 1 "general_operand" "g,g"))
-   (clobber (reg:SI 31))]
-  "! TARGET_LONG_CALLS"
-  "@
-  jarl %0,r31
-  jarl .+4,r31\\n\\tadd 4,r31\\n\\tjmp %0"
-  [(set_attr "length" "4,8")]
-)
-
-(define_insn "call_internal_long"
-  [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
-	 (match_operand:SI 1 "general_operand" "g,g"))
-   (clobber (reg:SI 31))]
-  "TARGET_LONG_CALLS"
-  "*
-  {
-  if (which_alternative == 0)
-    {
-      if (GET_CODE (operands[0]) == REG)
-        return \"jarl %0,r31\";
-      else
-        return \"movhi hi(%0), r0, r11\\n\\tmovea lo(%0), r11, r11\\n\\tjarl .+4,r31\\n\\tadd 4, r31\\n\\tjmp r11\";
-    }
-  else
-    return \"jarl .+4,r31\\n\\tadd 4,r31\\n\\tjmp %0\";
-  }"
-  [(set_attr "length" "16,8")]
-)
-
-;; Call subroutine, returning value in operand 0
-;; (which must be a hard register).
-
-(define_expand "call_value"
-  [(set (match_operand 0 "" "")
-	(call (match_operand:QI 1 "general_operand" "")
-	      (match_operand:SI 2 "general_operand" "")))]
-  ""
-  "
-{
-  if (! call_address_operand (XEXP (operands[1], 0))
-      || TARGET_LONG_CALLS)
-    XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
-  if (TARGET_LONG_CALLS)
-    emit_call_insn (gen_call_value_internal_long (operands[0],
-	 				          XEXP (operands[1], 0),
-					          operands[2]));
-  else
-    emit_call_insn (gen_call_value_internal_short (operands[0],
-	 				           XEXP (operands[1], 0),
-					           operands[2]));
-  DONE;
-}")
-
-(define_insn "call_value_internal_short"
-  [(set (match_operand 0 "" "=r,r")
-	(call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
-	      (match_operand:SI 2 "general_operand" "g,g")))
-   (clobber (reg:SI 31))]
-  "! TARGET_LONG_CALLS"
-  "@
-  jarl %1,r31
-  jarl .+4,r31\\n\\tadd 4,r31\\n\\tjmp %1"
-  [(set_attr "length" "4,8")]
-)
-
-(define_insn "call_value_internal_long"
-  [(set (match_operand 0 "" "=r,r")
-	(call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
-	      (match_operand:SI 2 "general_operand" "g,g")))
-   (clobber (reg:SI 31))]
-  "TARGET_LONG_CALLS"
-  "*
-  {
-  if (which_alternative == 0)
-    {
-      if (GET_CODE (operands[1]) == REG)
-        return \"jarl %1, r31\";
-      else
-      /* Reload can generate this pattern... */
-        return \"movhi hi(%1), r0, r11\\n\\tmovea lo(%1), r11, r11\\n\\tjarl .+4, r31\\n\\tadd 4, r31\\n\\tjmp r11\";
-    }
-  else
-    return \"jarl .+4, r31\\n\\tadd 4, r31\\n\\tjmp %1\";
-  }"
-  [(set_attr "length" "16,8")]
-)
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none")])
-
-;; ----------------------------------------------------------------------
-;; EXTEND INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-;; CYGNUS LOCAL v850e
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(zero_extend:SI
-	 (match_operand:HI 1 "nonimmediate_operand" "0,r,T,m")))]
-  "TARGET_V850E"
-  "@
-   zxh %0
-   andi 65535,%1,%0
-   sld.hu %1,%0
-   ld.hu %1,%0"
-  [(set_attr "length" "2,4,2,4")
-   (set_attr "cc" "none_0hit,set_znv,none_0hit,none_0hit")])
-;; END CYGNUS LOCAL
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI
-	 (match_operand:HI 1 "register_operand" "r")))]
-  ""
-  "andi 65535,%1,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "set_znv")])
-
-;; CYGNUS LOCAL v850e
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(zero_extend:SI
-	 (match_operand:QI 1 "nonimmediate_operand" "0,r,T,m")))]
-  "TARGET_V850E"
-  "@
-   zxb %0
-   andi 255,%1,%0
-   sld.bu %1,%0
-   ld.bu %1,%0"
-  [(set_attr "length" "2,4,2,4")
-   (set_attr "cc" "none_0hit,set_znv,none_0hit,none_0hit")])
-;; END CYGNUS LOCAL
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(zero_extend:SI
-	 (match_operand:QI 1 "register_operand" "r")))]
-  ""
-  "andi 255,%1,%0"
-  [(set_attr "length" "4")
-   (set_attr "cc" "set_znv")])
-
-;;- sign extension instructions
-
-;; CYGNUS LOCAL v850e
-
-;; ??? The extendhisi2 pattern should not emit shifts for v850e?
-
-(define_insn "*extendhisi_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,Q,m")))]
-  "TARGET_V850E"
-  "@
-   sxh %0
-   sld.h %1,%0
-   ld.h %1,%0"
-  [(set_attr "length" "2,2,4")
-   (set_attr "cc" "none_0hit,none_0hit,none_0hit")])
-;; END CYGNUS LOCAL
-
-;; ??? This is missing a sign extend from memory pattern to match the ld.h
-;; instruction.
-
-(define_expand "extendhisi2"
-  [(set (match_dup 2)
-        (ashift:SI (match_operand:HI 1 "register_operand" "")
-                   (const_int 16)))
-   (set (match_operand:SI 0 "register_operand" "")
-       (ashiftrt:SI (match_dup 2)
-                     (const_int 16)))]
-  ""
-  "
-{
-  operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode);
-}")
-
-;; CYGNUS LOCAL v850e
-
-;; ??? The extendqisi2 pattern should not emit shifts for v850e?
-
-(define_insn "*extendqisi_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,Q,m")))]
-  "TARGET_V850E"
-  "@
-   sxb %0
-   sld.b %1,%0
-   ld.b %1,%0"
-  [(set_attr "length" "2,2,4")
-   (set_attr "cc" "none_0hit,none_0hit,none_0hit")])
-;; END CYGNUS LOCAL
-
-;; ??? This is missing a sign extend from memory pattern to match the ld.b
-;; instruction.
-
-(define_expand "extendqisi2"
-  [(set (match_dup 2)
-        (ashift:SI (match_operand:QI 1 "register_operand" "")
-                   (const_int 24)))
-   (set (match_operand:SI 0 "register_operand" "")
-        (ashiftrt:SI (match_dup 2)
-                     (const_int 24)))]
-  ""
-  "
-{
-  operands[1] = gen_lowpart (SImode, operands[1]);
-  operands[2] = gen_reg_rtx (SImode);
-}")
-
-;; ----------------------------------------------------------------------
-;; SHIFTS
-;; ----------------------------------------------------------------------
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ashift:SI
-	 (match_operand:SI 1 "register_operand" "0,0")
-	 (match_operand:SI 2 "nonmemory_operand" "r,N")))]
-  ""
-  "@
-  shl %2,%0
-  shl %2,%0"
-  [(set_attr "length" "4,2")
-   (set_attr "cc" "set_znv")])
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(lshiftrt:SI
-	 (match_operand:SI 1 "register_operand" "0,0")
-	 (match_operand:SI 2 "nonmemory_operand" "r,N")))]
-  ""
-  "@
-  shr %2,%0
-  shr %2,%0"
-  [(set_attr "length" "4,2")
-   (set_attr "cc" "set_znv")])
-
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(ashiftrt:SI
-	 (match_operand:SI 1 "register_operand" "0,0")
-	 (match_operand:SI 2 "nonmemory_operand" "r,N")))]
-  ""
-  "@
-  sar %2,%0
-  sar %2,%0"
-  [(set_attr "length" "4,2")
-   (set_attr "cc" "set_znv")])
-
-;; ----------------------------------------------------------------------
-;; PROLOGUE/EPILOGUE
-;; ----------------------------------------------------------------------
-(define_expand "prologue"
-  [(const_int 0)]
-  ""
-  "expand_prologue (); DONE;")
-
-(define_expand "epilogue"
-  [(return)]
-  ""
-  "
-{
-  /* Try to use the trivial return first.  Else use the
-     full epilogue.  */
-  if (0)
-    emit_jump_insn (gen_return ());
-  else
-    expand_epilogue ();
-  DONE;
-}")
-
-(define_insn "return"
-  [(return)]
-  "reload_completed && compute_frame_size (get_frame_size (), (long *)0) == 0"
-  "jmp [r31]"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none")])
-
-(define_insn "return_internal"
-  [(return)
-   (use (reg:SI 31))]
-  ""
-  "jmp [r31]"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none")])
-
-
-
-;; ----------------------------------------------------------------------
-;; HELPER INSTRUCTIONS for saving the prologue and epilog registers
-;; ----------------------------------------------------------------------
-
-;; This pattern will match a stack adjust RTX followed by any number of push
-;; RTXs.  These RTXs will then be turned into a suitable call to a worker
-;; function.
-
-;; CYGNUS LOCAL v850e
-;;
-;; Actually, convert the RTXs into a PREPARE instruction.
-;;
-(define_insn ""
- [(match_parallel 0 "pattern_is_ok_for_prepare"
-   [(set (reg:SI 3)
-	 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
-    (set (mem:SI (plus:SI (reg:SI 3)
-			  (match_operand:SI 2 "immediate_operand" "i")))
-	 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
- "TARGET_PROLOG_FUNCTION && TARGET_V850E"
- "* return construct_prepare_instruction (operands[0]);
- "
- [(set_attr "length" "4")
-  (set_attr "cc"     "none")])
-;; END CYGNUS LOCAL
-
-(define_insn ""
- [(match_parallel 0 "pattern_is_ok_for_prologue"
-   [(set (reg:SI 3)
-	 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
-    (set (mem:SI (plus:SI (reg:SI 3)
-			   (match_operand:SI 2 "immediate_operand" "i")))
-	 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
- "TARGET_PROLOG_FUNCTION"
- "* return construct_save_jarl (operands[0]);
- "
- [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
-				     (const_string "16")
-				     (const_string "4")))
-  (set_attr "cc"     "clobber")])
-
-;; CYGNUS LOCAL v850e
-;; NOTE: The SAVE_INTERRUPT and SAVE_ALL_INTERRUPT patterns have been moved
-;; to further down this file.
-
-;;
-;; Actually, turn the RTXs into a DISPOSE instruction.
-;;
-(define_insn ""
- [(match_parallel 0 "pattern_is_ok_for_dispose"
-   [(return)
-    (set (reg:SI 3)
-	 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
-    (set (match_operand:SI 2 "register_is_ok_for_epilogue" "r")
-	 (mem:SI (plus:SI (reg:SI 3)
-			  (match_operand:SI 3 "immediate_operand" "i"))))])]
- "TARGET_PROLOG_FUNCTION && TARGET_V850E"
- "* return construct_dispose_instruction (operands[0]);
- "
- [(set_attr "length" "4")
-  (set_attr "cc"     "none")])
-;; END CYGNUS LOCAL 
-
-(define_insn ""
-[(match_parallel 0 "pattern_is_ok_for_epilogue"
-   [(return)
-    (set (reg:SI 3)
-	 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
-    (set (match_operand:SI 2 "register_is_ok_for_epilogue" "r")
-	 (mem:SI (plus:SI (reg:SI 3)
-			  (match_operand:SI 3 "immediate_operand" "i"))))])]
- "TARGET_PROLOG_FUNCTION && TARGET_V850"
- "* return construct_restore_jr (operands[0]);
- "
- [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
-				     (const_string "12")
-				     (const_string "4")))
-  (set_attr "cc"     "clobber")])
-
-;; Initialize an interrupt function.  Do not depend on TARGET_PROLOG_FUNCTION.
-;; CYGNUS LOCAL v850e
-(define_insn "save_interrupt_v850e"
-  [(set (reg:SI 3) (plus:SI (reg:SI 3) (const_int -16)))
-   (set (mem:SI (reg:SI 3)) (reg:SI 30))
-   (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 10))
-   (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 4))
-   (set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 1))]
-  "TARGET_V850E && !TARGET_DISABLE_CALLT"
-  "callt ctoff(__callt_save_interrupt)"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none")])
-;; END CYGNUS LOCAL 
-
-(define_insn "save_interrupt"
-  [(set (reg:SI 3) (plus:SI (reg:SI 3) (const_int -16)))
-   (set (mem:SI (reg:SI 3)) (reg:SI 30))
-   (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 10))
-   (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 4))
-   (set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 1))]
-  "TARGET_V850 && ! TARGET_LONG_CALLS"
-  "add -16,sp\;st.w r10,12[sp]\;jarl __save_interrupt,r10"
-  [(set_attr "length" "12")
-   (set_attr "cc" "clobber")])
-
-;; Restore r1, r4, r10, and return from the interrupt
-(define_insn "restore_interrupt"
-  [(return)
-   (set (reg:SI 3) (plus:SI (reg:SI 3) (const_int 16)))
-   (set (reg:SI 30) (mem:SI (plus:SI (reg:SI 3) (const_int 12))))
-   (set (reg:SI 10) (mem:SI (plus:SI (reg:SI 3) (const_int 8))))
-   (set (reg:SI 4)  (mem:SI (plus:SI (reg:SI 3) (const_int 4))))
-   (set (reg:SI 1)  (mem:SI (reg:SI 3)))]
-  ""
-  "jr __return_interrupt"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-
-;; Save all registers except for the registers saved in save_interrupt when
-;; an interrupt function makes a call.
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-;; This is needed because the rest of the compiler is not ready to handle
-;; insns this complicated.
-
-;; CYGNUS LOCAL v850e
-(define_insn "save_all_interrupt_v850e"
-  [(unspec_volatile [(const_int 0)] 0)]
-  "TARGET_V850E && !TARGET_DISABLE_CALLT"
-  "callt ctoff(__callt_save_all_interrupt)"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none")])
-;; END CYGNUS LOCAL
-
-(define_insn "save_all_interrupt"
-  [(unspec_volatile [(const_int 0)] 0)]
-  "TARGET_V850 && ! TARGET_LONG_CALLS"
-  "jarl __save_all_interrupt,r10"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-
-;; Restore all registers saved when an interrupt function makes a call.
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-;; This is needed because the rest of the compiler is not ready to handle
-;; insns this complicated.
-
-;; CYGNUS LOCAL v850e
-(define_insn "restore_all_interrupt_v850e"
-  [(unspec_volatile [(const_int 0)] 1)]
-  "TARGET_V850E && !TARGET_DISABLE_CALLT"
-  "callt ctoff(__callt_restore_all_interrupt)"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none")])
-;; END CYGNUS LOCAL
-
-(define_insn "restore_all_interrupt"
-  [(unspec_volatile [(const_int 0)] 1)]
-  "TARGET_V850 && ! TARGET_LONG_CALLS"
-  "jarl __restore_all_interrupt,r10"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
-;; Save r6-r9 for a variable argument function
-;; CYGNUS LOCAL v850e
-(define_insn "save_r6_r9_v850e"
-  [(set (mem:SI (reg:SI 3)) (reg:SI 6))
-   (set (mem:SI (plus:SI (reg:SI 3) (const_int 4))) (reg:SI 7))
-   (set (mem:SI (plus:SI (reg:SI 3) (const_int 8))) (reg:SI 8))
-   (set (mem:SI (plus:SI (reg:SI 3) (const_int 12))) (reg:SI 9))
-  ]
-  "TARGET_PROLOG_FUNCTION && TARGET_V850E && !TARGET_DISABLE_CALLT"
-  "callt ctoff(__callt_save_r6_r9)"
-  [(set_attr "length" "2")
-   (set_attr "cc" "none")])
-;; END CYGNUS LOCAL
-
-(define_insn "save_r6_r9"
-  [(set (mem:SI (reg:SI 3)) (reg:SI 6))
-   (set (mem:SI (plus:SI (reg:SI 3) (const_int 4))) (reg:SI 7))
-   (set (mem:SI (plus:SI (reg:SI 3) (const_int 8))) (reg:SI 8))
-   (set (mem:SI (plus:SI (reg:SI 3) (const_int 12))) (reg:SI 9))
-   (clobber (reg:SI 10))]
-  "TARGET_PROLOG_FUNCTION && ! TARGET_LONG_CALLS"
-  "jarl __save_r6_r9,r10"
-  [(set_attr "length" "4")
-   (set_attr "cc" "clobber")])
-
diff --git a/gcc/config/v850/v850e.h b/gcc/config/v850/v850e.h
deleted file mode 100755
index 7a33ae0..0000000
--- a/gcc/config/v850/v850e.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* CYGNUS LOCAL entire file
-   
-   Definitions of target machine for GNU compiler. 
-   NEC V850E series
-   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Nick Clifton (nickc@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#ifndef CPP_SPEC
-#define CPP_SPEC		"%{mv850ea:-D__v850ea__} %{mv850e:-D__v850e__} %{mv850:-D__v850__} %{!mv*:-D__v850e__}"
-#endif
-
-#ifndef TARGET_VERSION
-#define TARGET_VERSION 		fprintf (stderr, " (NEC V850E)");
-#endif
-
-#define MASK_V850E              0x00000020
-
-#ifndef MASK_V850EA
-#define MASK_V850EA             0x00000030
-#endif
-
-#ifndef MASK_DEFAULT
-#define MASK_DEFAULT            MASK_V850E
-#endif
-
-#ifndef TARGET_V850E
-#define TARGET_V850E   		((target_flags & MASK_CPU) == MASK_V850E)
-#endif
-
-#ifndef EXTRA_SWITCHES
-#define EXTRA_SWITCHES 		{ "v850e",   MASK_V850E, "Compile for v850e processor" },            \
-                                { "v850e", -(MASK_V850E ^ MASK_CPU), "" }, /* Make sure that the other bits are cleared.  */ \
-                       		{ "v850ea", MASK_V850EA, "Compile for v850ea processor" },
-#endif
-  
-/* We must pass a -mv850e option to the assembler if no explicit -mv* option
-   is given, because the assembler's processor default may not be correct.  */
-
-#ifndef SUBTARGET_ASM_SPEC
-#define SUBTARGET_ASM_SPEC "%{!mv*:-mv850e}"
-#endif
-
-/* Now include the rest of the definitions.  */
-#include "v850.h"
diff --git a/gcc/config/v850/v850ea.h b/gcc/config/v850/v850ea.h
deleted file mode 100755
index 6b971ef..0000000
--- a/gcc/config/v850/v850ea.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* CYGNUS LOCAL entire file
-   
-   Definitions of target machine for GNU compiler. 
-   NEC V850EA series
-   Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
-   Contributed by Nick Clifton (nickc@cygnus.com).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define CPP_SPEC		"%{mv850ea:-D__v850ea__} %{mv850e:-D__v850e__} %{mv850:-D__v850__} %{!mv*:-D__v850ea__}"
-
-#define TARGET_VERSION 		fprintf (stderr, " (NEC V850EA)");
-
-#define MASK_V850EA             0x00000030
-#define MASK_US_BIT_SET         0x00001000
-#define MASK_US_MASK_SET        0x00002000
-
-#define MASK_DEFAULT            MASK_V850EA
-
-/* Special version of TARGET_V850E which will be true if MASK_V850EA flag is set.  */
-#define TARGET_V850E   		((target_flags & MASK_V850E) == MASK_V850E)
-#define TARGET_V850EA   	((target_flags & MASK_CPU) == MASK_V850EA)
-
-#define TARGET_US_BIT_SET	(target_flags & MASK_US_BIT_SET)
-
-#define EXTRA_SWITCHES 		{ "v850e",   MASK_V850E, "Compile for v850e processor" },            \
-                                { "v850e", -(MASK_V850E ^ MASK_CPU), "" }, /* Make sure that the other bits are cleared.  */ \
-                       		{ "v850ea", MASK_V850EA, "" }, \
-                       		{ "US-bit-set", (MASK_US_BIT_SET | MASK_US_MASK_SET), "" },	\
-                       		{ "no-US-bit-set", - MASK_US_BIT_SET, "" },	\
-                       		{ "no-US-bit-set", MASK_US_MASK_SET, "" },
-
-/* We must pass a -mv850ea option to the assembler if no explicit -mv* option
-   is given, because the assembler's processor default may not be correct.  */
-
-#define SUBTARGET_ASM_SPEC "%{!mv*:-mv850ea}"
-
-/* Now include the rest of the definitions.  */
-#include "v850e.h"
diff --git a/gcc/config/v850/xm-v850.h b/gcc/config/v850/xm-v850.h
deleted file mode 100755
index 1e43d03..0000000
--- a/gcc/config/v850/xm-v850.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Configuration for NEC V850. 
-   Copyright (C) 1996 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-#ifdef __v850
-#ifndef __STDC__
-extern char *malloc (), *realloc (), *calloc ();
-#else
-extern void *malloc (), *realloc (), *calloc ();
-#endif
-extern void free ();
-#endif
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-
-#include "tm.h"
diff --git a/gcc/config/vax/netbsd.h b/gcc/config/vax/netbsd.h
deleted file mode 100755
index 23f3ff5..0000000
--- a/gcc/config/vax/netbsd.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -Dvax -D__NetBSD__ -Asystem(unix) -Asystem(NetBSD) -Acpu(vax) -Amachine(vax)"
-
-/* Make gcc agree with <machine/ansi.h> */
-
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
-
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
-
-#undef WCHAR_TYPE
-#define WCHAR_TYPE "int"
-
-#undef WCHAR_UNSIGNED
-#define WCHAR_UNSIGNED 0
-
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE 32
-
-/* Until they use ELF or something that handles dwarf2 unwinds
-   and initialization stuff better.  */
-#undef DWARF2_UNWIND_INFO
-
diff --git a/gcc/config/vax/ultrix.h b/gcc/config/vax/ultrix.h
deleted file mode 100755
index 3a14419..0000000
--- a/gcc/config/vax/ultrix.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES " -Dvax -Dunix -Dultrix -Dbsd4_2 -D__vax -D__unix -D__ultrix -D__bsd4_2 -Asystem(unix) -Asystem(bsd) -Acpu(vax) -Amachine(vax)"
-
-/* These are as defined in /usr/include/sys/stdtypes.h.
-   These values are for ultrix 4.2 on the vax.  */
-#define SIZE_TYPE "unsigned int"
-#define PTRDIFF_TYPE "int"
-#define WCHAR_TYPE "unsigned int"
-#define WCHAR_TYPE_SIZE 32
-
-/* True for Ultrix 4.3 and later and possibly earlier.  */
-#define HAVE_ATEXIT
diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c
deleted file mode 100755
index bac442a..0000000
--- a/gcc/config/vax/vax.c
+++ /dev/null
@@ -1,837 +0,0 @@
-/* Subroutines for insn-output.c for Vax.
-   Copyright (C) 1987, 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#ifdef VMS_TARGET
-#include "tree.h"
-#endif
-
-/* This is like nonimmediate_operand with a restriction on the type of MEM.  */
-
-void
-split_quadword_operands (operands, low, n)
-     rtx *operands, *low;
-     int n;
-{
-  int i;
-  /* Split operands.  */
-
-  low[0] = low[1] = low[2] = 0;
-  for (i = 0; i < 3; i++)
-    {
-      if (low[i])
-	/* it's already been figured out */;
-      else if (GET_CODE (operands[i]) == MEM
-	       && (GET_CODE (XEXP (operands[i], 0)) == POST_INC))
-	{
-	  rtx addr = XEXP (operands[i], 0);
-	  operands[i] = low[i] = gen_rtx (MEM, SImode, addr);
-	  if (which_alternative == 0 && i == 0)
-	    {
-	      addr = XEXP (operands[i], 0);
-	      operands[i+1] = low[i+1] = gen_rtx (MEM, SImode, addr);
-	    }
-	}
-      else
-	{
-	  low[i] = operand_subword (operands[i], 0, 0, DImode);
-	  operands[i] = operand_subword (operands[i], 1, 0, DImode);
-	}
-    }
-}
-
-print_operand_address (file, addr)
-     FILE *file;
-     register rtx addr;
-{
-  register rtx reg1, reg2, breg, ireg;
-  rtx offset;
-
- retry:
-  switch (GET_CODE (addr))
-    {
-    case MEM:
-      fprintf (file, "*");
-      addr = XEXP (addr, 0);
-      goto retry;
-
-    case REG:
-      fprintf (file, "(%s)", reg_names[REGNO (addr)]);
-      break;
-
-    case PRE_DEC:
-      fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case POST_INC:
-      fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
-      break;
-
-    case PLUS:
-      /* There can be either two or three things added here.  One must be a
-	 REG.  One can be either a REG or a MULT of a REG and an appropriate
-	 constant, and the third can only be a constant or a MEM.
-
-	 We get these two or three things and put the constant or MEM in
-	 OFFSET, the MULT or REG in IREG, and the REG in BREG.  If we have
-	 a register and can't tell yet if it is a base or index register,
-	 put it into REG1.  */
-
-      reg1 = 0; ireg = 0; breg = 0; offset = 0;
-
-      if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
-	  || GET_CODE (XEXP (addr, 0)) == MEM)
-	{
-	  offset = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
-	}
-      else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
-	       || GET_CODE (XEXP (addr, 1)) == MEM)
-	{
-	  offset = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-      else if (GET_CODE (XEXP (addr, 1)) == MULT)
-	{
-	  ireg = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-      else if (GET_CODE (XEXP (addr, 0)) == MULT)
-	{
-	  ireg = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
-	}
-      else if (GET_CODE (XEXP (addr, 1)) == REG)
-	{
-	  reg1 = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
-	}
-      else if (GET_CODE (XEXP (addr, 0)) == REG)
-	{
-	  reg1 = XEXP (addr, 0);
-	  addr = XEXP (addr, 1);
-	}
-      else
-	abort ();
-
-      if (GET_CODE (addr) == REG)
-	{
-	  if (reg1)
-	    ireg = addr;
-	  else
-	    reg1 = addr;
-	}
-      else if (GET_CODE (addr) == MULT)
-	ireg = addr;
-      else if (GET_CODE (addr) == PLUS)
-	{
-	  if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
-	      || GET_CODE (XEXP (addr, 0)) == MEM)
-	    {
-	      if (offset)
-		{
-		  if (GET_CODE (offset) == CONST_INT)
-		    offset = plus_constant (XEXP (addr, 0), INTVAL (offset));
-		  else if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
-		    offset = plus_constant (offset, INTVAL (XEXP (addr, 0)));
-		  else
-		    abort ();
-		}
-	      offset = XEXP (addr, 0);
-	    }
-	  else if (GET_CODE (XEXP (addr, 0)) == REG)
-	    {
-	      if (reg1)
-		ireg = reg1, breg = XEXP (addr, 0), reg1 = 0;
-	      else
-		reg1 = XEXP (addr, 0);
-	    }
-	  else if (GET_CODE (XEXP (addr, 0)) == MULT)
-	    {
-	      if (ireg)
-		abort ();
-	      ireg = XEXP (addr, 0);
-	    }
-	  else
-	    abort ();
-
-	  if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
-	      || GET_CODE (XEXP (addr, 1)) == MEM)
-	    {
-	      if (offset)
-		{
-		  if (GET_CODE (offset) == CONST_INT)
-		    offset = plus_constant (XEXP (addr, 1), INTVAL (offset));
-		  else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
-		    offset = plus_constant (offset, INTVAL (XEXP (addr, 1)));
-		  else
-		    abort ();
-		}
-	      offset = XEXP (addr, 1);
-	    }
-	  else if (GET_CODE (XEXP (addr, 1)) == REG)
-	    {
-	      if (reg1)
-		ireg = reg1, breg = XEXP (addr, 1), reg1 = 0;
-	      else
-		reg1 = XEXP (addr, 1);
-	    }
-	  else if (GET_CODE (XEXP (addr, 1)) == MULT)
-	    {
-	      if (ireg)
-		abort ();
-	      ireg = XEXP (addr, 1);
-	    }
-	  else
-	    abort ();
-	}
-      else
-	abort ();
-
-      /* If REG1 is non-zero, figure out if it is a base or index register.  */
-      if (reg1)
-	{
-	  if (breg != 0 || (offset && GET_CODE (offset) == MEM))
-	    {
-	      if (ireg)
-		abort ();
-	      ireg = reg1;
-	    }
-	  else
-	    breg = reg1;
-	}
-
-      if (offset != 0)
-	output_address (offset);
-
-      if (breg != 0)
-	fprintf (file, "(%s)", reg_names[REGNO (breg)]);
-
-      if (ireg != 0)
-	{
-	  if (GET_CODE (ireg) == MULT)
-	    ireg = XEXP (ireg, 0);
-	  if (GET_CODE (ireg) != REG)
-	    abort ();
-	  fprintf (file, "[%s]", reg_names[REGNO (ireg)]);
-	}
-      break;
-
-    default:
-      output_addr_const (file, addr);
-    }
-}
-
-char *
-rev_cond_name (op)
-     rtx op;
-{
-  switch (GET_CODE (op))
-    {
-    case EQ:
-      return "neq";
-    case NE:
-      return "eql";
-    case LT:
-      return "geq";
-    case LE:
-      return "gtr";
-    case GT:
-      return "leq";
-    case GE:
-      return "lss";
-    case LTU:
-      return "gequ";
-    case LEU:
-      return "gtru";
-    case GTU:
-      return "lequ";
-    case GEU:
-      return "lssu";
-
-    default:
-      abort ();
-    }
-}
-
-int
-vax_float_literal(c)
-    register rtx c;
-{
-  register enum machine_mode mode;
-  int i;
-  union {double d; int i[2];} val;
-
-  if (GET_CODE (c) != CONST_DOUBLE)
-    return 0;
-
-  mode = GET_MODE (c);
-
-  if (c == const_tiny_rtx[(int) mode][0]
-      || c == const_tiny_rtx[(int) mode][1]
-      || c == const_tiny_rtx[(int) mode][2])
-    return 1;
-
-#if HOST_FLOAT_FORMAT == VAX_FLOAT_FORMAT
-
-  val.i[0] = CONST_DOUBLE_LOW (c);
-  val.i[1] = CONST_DOUBLE_HIGH (c);
-
-  for (i = 0; i < 7; i ++)
-    if (val.d == 1 << i || val.d == 1 / (1 << i))
-      return 1;
-#endif
-  return 0;
-}
-
-
-/* Return the cost in cycles of a memory address, relative to register
-   indirect.
-
-   Each of the following adds the indicated number of cycles:
-
-   1 - symbolic address
-   1 - pre-decrement
-   1 - indexing and/or offset(register)
-   2 - indirect */
-
-
-int vax_address_cost(addr)
-    register rtx addr;
-{
-  int reg = 0, indexed = 0, indir = 0, offset = 0, predec = 0;
-  rtx plus_op0 = 0, plus_op1 = 0;
- restart:
-  switch (GET_CODE (addr))
-    {
-    case PRE_DEC:
-      predec = 1;
-    case REG:
-    case SUBREG:
-    case POST_INC:
-      reg = 1;
-      break;
-    case MULT:
-      indexed = 1;	/* 2 on VAX 2 */
-      break;
-    case CONST_INT:
-      /* byte offsets cost nothing (on a VAX 2, they cost 1 cycle) */
-      if (offset == 0)
-	offset = (unsigned)(INTVAL(addr)+128) > 256;
-      break;
-    case CONST:
-    case SYMBOL_REF:
-      offset = 1;	/* 2 on VAX 2 */
-      break;
-    case LABEL_REF:	/* this is probably a byte offset from the pc */
-      if (offset == 0)
-	offset = 1;
-      break;
-    case PLUS:
-      if (plus_op0)
-	plus_op1 = XEXP (addr, 0);
-      else
-	plus_op0 = XEXP (addr, 0);
-      addr = XEXP (addr, 1);
-      goto restart;
-    case MEM:
-      indir = 2;	/* 3 on VAX 2 */
-      addr = XEXP (addr, 0);
-      goto restart;
-    }
-
-  /* Up to 3 things can be added in an address.  They are stored in
-     plus_op0, plus_op1, and addr.  */
-
-  if (plus_op0)
-    {
-      addr = plus_op0;
-      plus_op0 = 0;
-      goto restart;
-    }
-  if (plus_op1)
-    {
-      addr = plus_op1;
-      plus_op1 = 0;
-      goto restart;
-    }
-  /* Indexing and register+offset can both be used (except on a VAX 2)
-     without increasing execution time over either one alone. */
-  if (reg && indexed && offset)
-    return reg + indir + offset + predec;
-  return reg + indexed + indir + offset + predec;
-}
-
-
-/* Cost of an expression on a VAX.  This version has costs tuned for the
-   CVAX chip (found in the VAX 3 series) with comments for variations on
-   other models.  */
-
-int
-vax_rtx_cost (x)
-    register rtx x;
-{
-  register enum rtx_code code = GET_CODE (x);
-  enum machine_mode mode = GET_MODE (x);
-  register int c;
-  int i = 0;				/* may be modified in switch */
-  char *fmt = GET_RTX_FORMAT (code);	/* may be modified in switch */
-
-  switch (code)
-    {
-    case POST_INC:
-      return 2;
-    case PRE_DEC:
-      return 3;
-    case MULT:
-      switch (mode)
-	{
-	case DFmode:
-	  c = 16;		/* 4 on VAX 9000 */
-	  break;
-	case SFmode:
-	  c = 9;		/* 4 on VAX 9000, 12 on VAX 2 */
-	  break;
-	case DImode:
-	  c = 16;		/* 6 on VAX 9000, 28 on VAX 2 */
-	  break;
-	case SImode:
-	case HImode:
-	case QImode:
-	  c = 10;		/* 3-4 on VAX 9000, 20-28 on VAX 2 */
-	  break;
-	}
-      break;
-    case UDIV:
-      c = 17;
-      break;
-    case DIV:
-      if (mode == DImode)
-	c = 30;	/* highly variable */
-      else if (mode == DFmode)
-	/* divide takes 28 cycles if the result is not zero, 13 otherwise */
-	c = 24;
-      else
-	c = 11;			/* 25 on VAX 2 */
-      break;
-    case MOD:
-      c = 23;
-      break;
-    case UMOD:
-      c = 29;
-      break;
-    case FLOAT:
-      c = 6 + (mode == DFmode) + (GET_MODE (XEXP (x, 0)) != SImode);
-      /* 4 on VAX 9000 */
-      break;
-    case FIX:
-      c = 7;			/* 17 on VAX 2 */
-      break;
-    case ASHIFT:
-    case LSHIFTRT:
-    case ASHIFTRT:
-      if (mode == DImode)
-	c = 12;
-      else
-	c = 10;			/* 6 on VAX 9000 */
-      break;
-    case ROTATE:
-    case ROTATERT:
-      c = 6;			/* 5 on VAX 2, 4 on VAX 9000 */
-      if (GET_CODE (XEXP (x, 1)) == CONST_INT)
-	fmt = "e";	/* all constant rotate counts are short */
-      break;
-    case PLUS:
-      /* Check for small negative integer operand: subl2 can be used with
-	 a short positive constant instead.  */
-      if (GET_CODE (XEXP (x, 1)) == CONST_INT)
-	if ((unsigned)(INTVAL (XEXP (x, 1)) + 63) < 127)
-	  fmt = "e";
-    case MINUS:
-      c = (mode == DFmode) ? 13 : 8;	/* 6/8 on VAX 9000, 16/15 on VAX 2 */
-    case IOR:
-    case XOR:
-      c = 3;
-      break;
-    case AND:
-      /* AND is special because the first operand is complemented. */
-      c = 3;
-      if (GET_CODE (XEXP (x, 0)) == CONST_INT)
-	{
-	  if ((unsigned)~INTVAL (XEXP (x, 0)) > 63)
-	    c = 4;
-	  fmt = "e";
-	  i = 1;
-	}
-      break;
-    case NEG:
-      if (mode == DFmode)
-	return 9;
-      else if (mode == SFmode)
-	return 6;
-      else if (mode == DImode)
-	return 4;
-    case NOT:
-      return 2;
-    case ZERO_EXTRACT:
-    case SIGN_EXTRACT:
-      c = 15;
-      break;
-    case MEM:
-      if (mode == DImode || mode == DFmode)
-	c = 5;				/* 7 on VAX 2 */
-      else
-	c = 3;				/* 4 on VAX 2 */
-      x = XEXP (x, 0);
-      if (GET_CODE (x) == REG || GET_CODE (x) == POST_INC)
-	return c;
-      return c + vax_address_cost (x);
-    default:
-      c = 3;
-      break;
-    }
-
-
-  /* Now look inside the expression.  Operands which are not registers or
-     short constants add to the cost.
-
-     FMT and I may have been adjusted in the switch above for instructions
-     which require special handling */
-
-  while (*fmt++ == 'e')
-    {
-      register rtx op = XEXP (x, i++);
-      code = GET_CODE (op);
-
-      /* A NOT is likely to be found as the first operand of an AND
-	 (in which case the relevant cost is of the operand inside
-	 the not) and not likely to be found anywhere else.  */
-      if (code == NOT)
-	op = XEXP (op, 0), code = GET_CODE (op);
-
-      switch (code)
-	{
-	case CONST_INT:
-	  if ((unsigned)INTVAL (op) > 63 && GET_MODE (x) != QImode)
-	    c += 1;		/* 2 on VAX 2 */
-	  break;
-	case CONST:
-	case LABEL_REF:
-	case SYMBOL_REF:
-	  c += 1;		/* 2 on VAX 2 */
-	  break;
-	case CONST_DOUBLE:
-	  if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
-	    {
-	      /* Registers are faster than floating point constants -- even
-		 those constants which can be encoded in a single byte.  */
-	      if (vax_float_literal (op))
-		c++;
-	      else
-		c += (GET_MODE (x) == DFmode) ? 3 : 2;
-	    }
-	  else
-	    {
-	      if (CONST_DOUBLE_HIGH (op) != 0
-		  || (unsigned)CONST_DOUBLE_LOW (op) > 63)
-		c += 2;
-	    }
-	  break;
-	case MEM:
-	  c += 1;		/* 2 on VAX 2 */
-	  if (GET_CODE (XEXP (op, 0)) != REG)
-	    c += vax_address_cost (XEXP (op, 0));
-	  break;
-	case REG:
-	case SUBREG:
-	  break;
-	default:
-	  c += 1;
-	  break;
-	}
-    }
-  return c;
-}
-
-/* Check a `double' value for validity for a particular machine mode.  */
-
-static char *float_strings[] =
-{
-   "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
-  "-1.70141173319264430e+38",
-   "2.93873587705571877e-39", /* 2^-128 */
-  "-2.93873587705571877e-39"
-};
-
-static REAL_VALUE_TYPE float_values[4];
-
-static int inited_float_values = 0;
-
-
-int
-check_float_value (mode, d, overflow)
-     enum machine_mode mode;
-     REAL_VALUE_TYPE *d;
-     int overflow;
-{
-  if (inited_float_values == 0)
-    {
-      int i;
-      for (i = 0; i < 4; i++)
-	{
-	  float_values[i] = REAL_VALUE_ATOF (float_strings[i], DFmode);
-	}
-
-      inited_float_values = 1;
-    }
-
-  if (overflow)
-    {
-      bcopy ((char *) &float_values[0], (char *) d, sizeof (REAL_VALUE_TYPE));
-      return 1;
-    }
-
-  if ((mode) == SFmode)
-    {
-      REAL_VALUE_TYPE r;
-      bcopy ((char *) d, (char *) &r, sizeof (REAL_VALUE_TYPE));
-      if (REAL_VALUES_LESS (float_values[0], r))
-	{
-	  bcopy ((char *) &float_values[0], (char *) d,
-		 sizeof (REAL_VALUE_TYPE));
-	  return 1;
-	}
-      else if (REAL_VALUES_LESS (r, float_values[1]))
-	{
-	  bcopy ((char *) &float_values[1], (char*) d,
-		 sizeof (REAL_VALUE_TYPE));
-	  return 1;
-	}
-      else if (REAL_VALUES_LESS (dconst0, r)
-		&& REAL_VALUES_LESS (r, float_values[2]))
-	{
-	  bcopy ((char *) &dconst0, (char *) d, sizeof (REAL_VALUE_TYPE));
-	  return 1;
-	}
-      else if (REAL_VALUES_LESS (r, dconst0)
-		&& REAL_VALUES_LESS (float_values[3], r))
-	{
-	  bcopy ((char *) &dconst0, (char *) d, sizeof (REAL_VALUE_TYPE));
-	  return 1;
-	}
-    }
-
-  return 0;
-}
-
-#ifdef VMS_TARGET
-/* Additional support code for VMS target. */
-
-/* Linked list of all externals that are to be emitted when optimizing
-   for the global pointer if they haven't been declared by the end of
-   the program with an appropriate .comm or initialization.  */
-
-static
-struct extern_list {
-  struct extern_list *next;	/* next external */
-  char *name;			/* name of the external */
-  int size;			/* external's actual size */
-  int in_const;			/* section type flag */
-} *extern_head = 0, *pending_head = 0;
-
-/* Check whether NAME is already on the external definition list.  If not,
-   add it to either that list or the pending definition list.  */
-
-void
-vms_check_external (decl, name, pending)
-     tree decl;
-     char *name;
-     int pending;
-{
-  register struct extern_list *p, *p0;
-
-  for (p = extern_head; p; p = p->next)
-    if (!strcmp (p->name, name))
-      return;
-
-  for (p = pending_head, p0 = 0; p; p0 = p, p = p->next)
-    if (!strcmp (p->name, name))
-      {
-	if (pending)
-	  return;
-
-	/* Was pending, but has now been defined; move it to other list.  */
-	if (p == pending_head)
-	  pending_head = p->next;
-	else
-	  p0->next = p->next;
-	p->next = extern_head;
-	extern_head = p;
-	return;
-      }
-
-  /* Not previously seen; create a new list entry.  */
-  p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
-  p->name = name;
-
-  if (pending)
-    {
-      /* Save the size and section type and link to `pending' list.  */
-      p->size = (DECL_SIZE (decl) == 0) ? 0 :
-	TREE_INT_CST_LOW (size_binop (CEIL_DIV_EXPR, DECL_SIZE (decl),
-				      size_int (BITS_PER_UNIT)));
-      p->in_const = (TREE_READONLY (decl) && ! TREE_THIS_VOLATILE (decl));
-
-      p->next = pending_head;
-      pending_head = p;
-    }
-  else
-    {
-      /* Size and section type don't matter; link to `declared' list.  */
-      p->size = p->in_const = 0;        /* arbitrary init */
-
-      p->next = extern_head;
-      extern_head = p;
-    }
-  return;
-}
-
-void
-vms_flush_pending_externals (file)
-     FILE *file;
-{
-  register struct extern_list *p;
-
-  while (pending_head)
-    {
-      /* Move next pending declaration to the "done" list.  */
-      p = pending_head;
-      pending_head = p->next;
-      p->next = extern_head;
-      extern_head = p;
-
-      /* Now output the actual declaration.  */
-      if (p->in_const)
-	const_section ();
-      else
-	data_section ();
-      fputs (".comm ", file);
-      assemble_name (file, p->name);
-      fprintf (file, ",%d\n", p->size);
-    }
-}
-#endif /* VMS_TARGET */
-
-#ifdef VMS
-/* Additional support code for VMS host. */
-
-#ifdef QSORT_WORKAROUND
-  /*
-	Do not use VAXCRTL's qsort() due to a severe bug:  once you've
-	sorted something which has a size that's an exact multiple of 4
-	and is longword aligned, you cannot safely sort anything which
-	is either not a multiple of 4 in size or not longword aligned.
-	A static "move-by-longword" optimization flag inside qsort() is
-	never reset.  This is known of affect VMS V4.6 through VMS V5.5-1,
-	and was finally fixed in VMS V5.5-2.
-
-	In this work-around an insertion sort is used for simplicity.
-	The qsort code from glibc should probably be used instead.
-   */
-void
-not_qsort (array, count, size, compare)
-     void *array;
-     unsigned count, size;
-     int (*compare)();
-{
-
-  if (size == sizeof (short))
-    {
-      register int i;
-      register short *next, *prev;
-      short tmp, *base = array;
-
-      for (next = base, i = count - 1; i > 0; i--)
-	{
-	  prev = next++;
-	  if ((*compare)(next, prev) < 0)
-	    {
-	      tmp = *next;
-	      do  *(prev + 1) = *prev;
-		while (--prev >= base ? (*compare)(&tmp, prev) < 0 : 0);
-	      *(prev + 1) = tmp;
-	    }
-	}
-    }
-  else if (size == sizeof (long))
-    {
-      register int i;
-      register long *next, *prev;
-      long tmp, *base = array;
-
-      for (next = base, i = count - 1; i > 0; i--)
-	{
-	  prev = next++;
-	  if ((*compare)(next, prev) < 0)
-	    {
-	      tmp = *next;
-	      do  *(prev + 1) = *prev;
-		while (--prev >= base ? (*compare)(&tmp, prev) < 0 : 0);
-	      *(prev + 1) = tmp;
-	    }
-	}
-    }
-  else  /* arbitrary size */
-    {
-      register int i;
-      register char *next, *prev, *tmp = alloca (size), *base = array;
-
-      for (next = base, i = count - 1; i > 0; i--)
-	{   /* count-1 forward iterations */
-	  prev = next,  next += size;		/* increment front pointer */
-	  if ((*compare)(next, prev) < 0)
-	    {	/* found element out of order; move others up then re-insert */
-	      memcpy (tmp, next, size);		/* save smaller element */
-	      do { memcpy (prev + size, prev, size); /* move larger elem. up */
-		   prev -= size;		/* decrement back pointer */
-		 } while (prev >= base ? (*compare)(tmp, prev) < 0 : 0);
-	      memcpy (prev + size, tmp, size);	/* restore small element */
-	    }
-	}
-#ifdef USE_C_ALLOCA
-      alloca (0);
-#endif
-    }
-
-  return;
-}
-#endif /* QSORT_WORKAROUND */
-
-#endif /* VMS */
diff --git a/gcc/config/vax/vax.h b/gcc/config/vax/vax.h
deleted file mode 100755
index ad8fb7c..0000000
--- a/gcc/config/vax/vax.h
+++ /dev/null
@@ -1,1317 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Vax version.
-   Copyright (C) 1987, 88, 91, 93-96, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dvax -D__vax__ -Dunix -Asystem(unix) -Asystem(bsd) -Acpu(vax) -Amachine(vax)"
-
-/* If using g-format floating point, alter math.h.  */
-
-#define	CPP_SPEC "%{mg:-DGFLOAT}"
-
-/* Choose proper libraries depending on float format.
-   Note that there are no profiling libraries for g-format.
-   Also use -lg for the sake of dbx.  */
-
-#define LIB_SPEC "%{g:-lg}\
- %{mg:%{lm:-lmg} -lcg \
-  %{p:%eprofiling not supported with -mg\n}\
-  %{pg:%eprofiling not supported with -mg\n}}\
- %{!mg:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}"
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#ifndef TARGET_NAME	/* A more specific value might be supplied via -D.  */
-#define TARGET_NAME "vax"
-#endif
-#define TARGET_VERSION fprintf (stderr, " (%s)", TARGET_NAME)
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Nonzero if compiling code that Unix assembler can assemble.  */
-#define TARGET_UNIX_ASM (target_flags & 1)
-
-/* Nonzero if compiling with VAX-11 "C" style structure alignment */
-#define	TARGET_VAXC_ALIGNMENT (target_flags & 2)
-
-/* Nonzero if compiling with `G'-format floating point */
-#define TARGET_G_FLOAT (target_flags & 4)
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  { {"unix", 1},  \
-    {"gnu", -1},  \
-    {"vaxc-alignment", 2}, \
-    {"g", 4}, \
-    {"g-float", 4}, \
-    {"d", -4},	\
-    {"d-float", -4}, \
-    { "", TARGET_DEFAULT}}
-
-/* Default target_flags if no switches specified.  */
-
-#ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT 1
-#endif
-
-/* Target machine storage layout */
-
-/* Define for software floating point emulation of VAX format
-   when cross compiling from a non-VAX host. */
-/* #define REAL_ARITHMETIC */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-   This is not true on the vax.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is not true on the vax.  */
-#define BYTES_BIG_ENDIAN 0
-
-/* Define this if most significant word of a multiword number is the lowest
-   numbered.  */
-/* This is not true on the vax.  */
-#define WORDS_BIG_ENDIAN 0
-
-/* Number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 16
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY (TARGET_VAXC_ALIGNMENT ? 8 : 32)
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 8
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS (! TARGET_VAXC_ALIGNMENT)
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 32
-
-/* No structure field wants to be aligned rounder than this.  */
-#define BIGGEST_FIELD_ALIGNMENT (TARGET_VAXC_ALIGNMENT ? 8 : 32)
-
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 0
-
-/* Let's keep the stack somewhat aligned.  */
-#define STACK_BOUNDARY 32
-
-/* The table of an ADDR_DIFF_VEC must be contiguous with the case
-   opcode, it is part of the case instruction.  */
-#define ADDR_VEC_ALIGN(ADDR_VEC) 0
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.  */
-#define FIRST_PSEUDO_REGISTER 16
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-   On the vax, these are the AP, FP, SP and PC.  */
-#define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS {1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-   On the vax, all registers are one word long.  */
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
-   On the vax, all registers can hold all modes.  */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2)  1
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* Vax pc is overloaded on a register.  */
-#define PC_REGNUM 15
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 14
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 13
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 1
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 12
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 0
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 1
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-   
-/* The vax has only one kind of registers, so NO_REGS and ALL_REGS
-   are the only classes.  */
-
-enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Since GENERAL_REGS is the same class as ALL_REGS,
-   don't give it a different class number; just make it an alias.  */
-
-#define GENERAL_REGS ALL_REGS
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- {"NO_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS {0, 0xffff}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) ALL_REGS
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS ALL_REGS
-#define BASE_REG_CLASS ALL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C) NO_REGS
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   `I' is the constant zero.  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'I' ? (VALUE) == 0		\
-   : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself. 
-
-   `G' is a floating-point zero.  */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'G' ? ((VALUE) == CONST0_RTX (DFmode)		\
-		 || (VALUE) == CONST0_RTX (SFmode))	\
-   : 0)
-
-/* Optional extra constraints for this machine.
-
-   For the VAX, `Q' means that OP is a MEM that does not have a mode-dependent
-   address.  */
-
-#define EXTRA_CONSTRAINT(OP, C) \
-  ((C) == 'Q'								\
-   ? GET_CODE (OP) == MEM && ! mode_dependent_address_p (XEXP (OP, 0))	\
-   : 0)
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.  */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)  (CLASS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-/* On the vax, this is always the size of MODE in words,
-   since all registers are the same size.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if longjmp restores from saved registers
-   rather than from what setjmp saved.  */
-#define LONGJMP_RESTORE_FROM_STACK
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET 0
-
-/* Given an rtx for the address of a frame,
-   return an rtx for the address of the word in the frame
-   that holds the dynamic chain--the previous frame's address.  */
-#define DYNAMIC_CHAIN_ADDRESS(frame) \
-gen_rtx (PLUS, Pmode, frame, GEN_INT (12))
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On the vax, -(sp) pushes only the bytes of the operands.  */
-#define PUSH_ROUNDING(BYTES) (BYTES)
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 4
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.
-
-   On the Vax, the RET insn always pops all the args for any function.  */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-/* On the Vax the return value is in R0 regardless.  */   
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-/* On the Vax the return value is in R0 regardless.  */   
-
-#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, 0)
-
-/* Define this if PCC uses the nonreentrant convention for returning
-   structure and union values.  */
-
-#define PCC_STATIC_STRUCT_RETURN
-
-/* 1 if N is a possible register number for a function value.
-   On the Vax, R0 is the only register thus used.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-/* 1 if N is a possible register number for function argument passing.
-   On the Vax, no registers are used in this way.  */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the vax, this is a single integer, which is a number of bytes
-   of arguments scanned so far.  */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the vax, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM) += ((MODE) != BLKmode			\
-	    ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
-	    : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On the vax all args are pushed.  */   
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate,
-   adjusted by STARTING_FRAME_OFFSET to accommodate vms.h.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)     \
-{ register int regno;						\
-  register int mask = 0;					\
-  register int size = SIZE - STARTING_FRAME_OFFSET;		\
-  extern char call_used_regs[];					\
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)	\
-    if (regs_ever_live[regno] && !call_used_regs[regno])	\
-       mask |= 1 << regno;					\
-  fprintf (FILE, "\t.word 0x%x\n", mask);			\
-  MAYBE_VMS_FUNCTION_PROLOGUE(FILE)				\
-  if ((size) >= 64) fprintf (FILE, "\tmovab %d(sp),sp\n", -size);\
-  else if (size) fprintf (FILE, "\tsubl2 $%d,sp\n", (size)); }
-
-/* vms.h redefines this.  */
-#define MAYBE_VMS_FUNCTION_PROLOGUE(FILE)
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-   fprintf (FILE, "\tmovab LP%d,r0\n\tjsb mcount\n", (LABELNO));
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.  */
-
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\ttstl LPBX0\n\tjneq LPI%d\n\tpushal LPBX0\n\tcalls $1,__bb_init_func\nLPI%d:\n",  \
-	   LABELNO, LABELNO);
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  This is a real pain in the
-   sphincter on a VAX, since we do not want to change any of the bits in the
-   processor status word.  The way it is done here, it is pushed onto the stack
-   before any flags have changed, and then the stack is fixed up to account for
-   the fact that the instruction to restore the flags only reads a word.
-   It may seem a bit clumsy, but at least it works.
-*/
-
-#define BLOCK_PROFILER(FILE, BLOCKNO)	\
-  fprintf (FILE, "\tmovpsl -(sp)\n\tmovw (sp),2(sp)\n\taddl2 $2,sp\n\taddl2 $1,LPBX2+%d\n\tbicpsw $255\n\tbispsw (sp)+\n", \
-		4 * BLOCKNO)
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 1
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.  */
-
-/* #define FUNCTION_EPILOGUE(FILE, SIZE)  */
-
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved.
-
-   On the Vax, FRAME_POINTER_REQUIRED is always 1, so the definition of this
-   macro doesn't matter.  But it must be defined.  */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0;
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  */
-
-/* On the vax, the trampoline contains an entry mask and two instructions:
-     .word NN
-     movl $STATIC,r0   (store the functions static chain)
-     jmp  *$FUNCTION   (jump to function code at address FUNCTION)  */
-
-#define TRAMPOLINE_TEMPLATE(FILE)					\
-{									\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x8fd0));	\
-  ASM_OUTPUT_INT (FILE, const0_rtx);					\
-  ASM_OUTPUT_BYTE  (FILE, 0x50+STATIC_CHAIN_REGNUM);			\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x9f17));	\
-  ASM_OUTPUT_INT (FILE, const0_rtx);					\
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 15
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-/* We copy the register-mask from the function's pure code
-   to the start of the trampoline.  */
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_insn (gen_rtx (ASM_INPUT, VOIDmode,				\
-		      "movpsl -(sp)\n\tpushal 1(pc)\n\trei"));		\
-  emit_move_insn (gen_rtx (MEM, HImode, TRAMP),				\
-		  gen_rtx (MEM, HImode, FNADDR));			\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), CXT);\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 11)),	\
-		  plus_constant (FNADDR, 2));				\
-}
-
-/* Byte offset of return address in a stack frame.  The "saved PC" field
-   is in element [4] when treating the frame as an array of longwords.  */
-
-#define RETURN_ADDRESS_OFFSET	(4 * UNITS_PER_WORD)	/* 16 */
-
-/* A C expression whose value is RTL representing the value of the return
-   address for the frame COUNT steps up from the current frame.
-   FRAMEADDR is already the frame pointer of the COUNT frame, so we
-   can ignore COUNT.  */
-
-#define RETURN_ADDR_RTX(COUNT, FRAME)	\
-  ((COUNT == 0)				\
-   ? gen_rtx (MEM, Pmode, plus_constant (FRAME, RETURN_ADDRESS_OFFSET)) \
-   : (rtx) 0)
-
-
-/* Addressing modes, and classification of registers for them.  */
-
-#define HAVE_POST_INCREMENT 1
-/* #define HAVE_POST_DECREMENT 0 */
-
-#define HAVE_PRE_DECREMENT 1
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(regno)  \
-((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
-#define REGNO_OK_FOR_BASE_P(regno) \
-((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 2
-
-/* 1 if X is an rtx for a constant that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) 1
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) 1
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
-
-   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
-   except for CONSTANT_ADDRESS_P which is actually machine-independent.  */
-
-#ifdef NO_EXTERNAL_INDIRECT_ADDRESS
-
-/* Zero if this contains a (CONST (PLUS (SYMBOL_REF) (...))) and the
-   symbol in the SYMBOL_REF is an external symbol.  */
-
-#define INDIRECTABLE_CONSTANT_P(X) \
- (! (GET_CODE ((X)) == CONST					\
-     && GET_CODE (XEXP ((X), 0)) == PLUS			\
-     && GET_CODE (XEXP (XEXP ((X), 0), 0)) == SYMBOL_REF	\
-     && SYMBOL_REF_FLAG (XEXP (XEXP ((X), 0), 0))))
-
-/* Re-definition of CONSTANT_ADDRESS_P, which is true only when there
-   are no SYMBOL_REFs for external symbols present.  */
-
-#define INDIRECTABLE_CONSTANT_ADDRESS_P(X)   				\
-  (GET_CODE (X) == LABEL_REF 						\
-   || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_FLAG (X))		\
-   || (GET_CODE (X) == CONST && INDIRECTABLE_CONSTANT_P(X))		\
-   || GET_CODE (X) == CONST_INT)
-
-
-/* Non-zero if X is an address which can be indirected.  External symbols
-   could be in a sharable image library, so we disallow those.  */
-
-#define INDIRECTABLE_ADDRESS_P(X)  \
-  (INDIRECTABLE_CONSTANT_ADDRESS_P (X) 					\
-   || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
-   || (GET_CODE (X) == PLUS						\
-       && GET_CODE (XEXP (X, 0)) == REG					\
-       && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
-       && INDIRECTABLE_CONSTANT_ADDRESS_P (XEXP (X, 1))))
-
-#else /* not NO_EXTERNAL_INDIRECT_ADDRESS */
-
-#define INDIRECTABLE_CONSTANT_ADDRESS_P(X) CONSTANT_ADDRESS_P(X)
-
-/* Non-zero if X is an address which can be indirected.  */
-#define INDIRECTABLE_ADDRESS_P(X)  \
-  (CONSTANT_ADDRESS_P (X)						\
-   || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))			\
-   || (GET_CODE (X) == PLUS						\
-       && GET_CODE (XEXP (X, 0)) == REG					\
-       && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
-       && CONSTANT_ADDRESS_P (XEXP (X, 1))))
-
-#endif /* not NO_EXTERNAL_INDIRECT_ADDRESS */
-
-/* Go to ADDR if X is a valid address not using indexing.
-   (This much is the easy part.)  */
-#define GO_IF_NONINDEXED_ADDRESS(X, ADDR)  \
-{ register rtx xfoob = (X);						\
-  if (GET_CODE (xfoob) == REG)						\
-    {									\
-      extern rtx *reg_equiv_mem;					\
-      if (! reload_in_progress						\
-	  || reg_equiv_mem[REGNO (xfoob)] == 0				\
-	  || INDIRECTABLE_ADDRESS_P (reg_equiv_mem[REGNO (xfoob)]))	\
-	goto ADDR;							\
-    }									\
-  if (CONSTANT_ADDRESS_P (xfoob)) goto ADDR;				\
-  if (INDIRECTABLE_ADDRESS_P (xfoob)) goto ADDR;			\
-  xfoob = XEXP (X, 0);							\
-  if (GET_CODE (X) == MEM && INDIRECTABLE_ADDRESS_P (xfoob))		\
-    goto ADDR;								\
-  if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC)		\
-      && GET_CODE (xfoob) == REG && REG_OK_FOR_BASE_P (xfoob))		\
-    goto ADDR; }
-
-/* 1 if PROD is either a reg times size of mode MODE
-   or just a reg, if MODE is just one byte.
-   This macro's expansion uses the temporary variables xfoo0 and xfoo1
-   that must be declared in the surrounding context.  */
-#define INDEX_TERM_P(PROD, MODE)   \
-(GET_MODE_SIZE (MODE) == 1						\
- ? (GET_CODE (PROD) == REG && REG_OK_FOR_BASE_P (PROD))			\
- : (GET_CODE (PROD) == MULT						\
-    &&									\
-    (xfoo0 = XEXP (PROD, 0), xfoo1 = XEXP (PROD, 1),			\
-     ((GET_CODE (xfoo0) == CONST_INT					\
-       && INTVAL (xfoo0) == GET_MODE_SIZE (MODE)			\
-       && GET_CODE (xfoo1) == REG					\
-       && REG_OK_FOR_INDEX_P (xfoo1))					\
-      ||								\
-      (GET_CODE (xfoo1) == CONST_INT					\
-       && INTVAL (xfoo1) == GET_MODE_SIZE (MODE)			\
-       && GET_CODE (xfoo0) == REG					\
-       && REG_OK_FOR_INDEX_P (xfoo0))))))
-
-/* Go to ADDR if X is the sum of a register
-   and a valid index term for mode MODE.  */
-#define GO_IF_REG_PLUS_INDEX(X, MODE, ADDR)	\
-{ register rtx xfooa;							\
-  if (GET_CODE (X) == PLUS)						\
-    { if (GET_CODE (XEXP (X, 0)) == REG					\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 0))				\
-	  && (xfooa = XEXP (X, 1),					\
-	      INDEX_TERM_P (xfooa, MODE)))				\
-	goto ADDR;							\
-      if (GET_CODE (XEXP (X, 1)) == REG					\
-	  && REG_OK_FOR_BASE_P (XEXP (X, 1))				\
-	  && (xfooa = XEXP (X, 0),					\
-	      INDEX_TERM_P (xfooa, MODE)))				\
-	goto ADDR; } }
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
-{ register rtx xfoo, xfoo0, xfoo1;					\
-  GO_IF_NONINDEXED_ADDRESS (X, ADDR);					\
-  if (GET_CODE (X) == PLUS)						\
-    { /* Handle <address>[index] represented with index-sum outermost */\
-      xfoo = XEXP (X, 0);						\
-      if (INDEX_TERM_P (xfoo, MODE))					\
-	{ GO_IF_NONINDEXED_ADDRESS (XEXP (X, 1), ADDR); }		\
-      xfoo = XEXP (X, 1);						\
-      if (INDEX_TERM_P (xfoo, MODE))					\
-	{ GO_IF_NONINDEXED_ADDRESS (XEXP (X, 0), ADDR); }		\
-      /* Handle offset(reg)[index] with offset added outermost */	\
-      if (INDIRECTABLE_CONSTANT_ADDRESS_P (XEXP (X, 0)))		\
-	{ if (GET_CODE (XEXP (X, 1)) == REG				\
-	      && REG_OK_FOR_BASE_P (XEXP (X, 1)))			\
-	    goto ADDR;							\
-	  GO_IF_REG_PLUS_INDEX (XEXP (X, 1), MODE, ADDR); }		\
-      if (INDIRECTABLE_CONSTANT_ADDRESS_P (XEXP (X, 1)))		\
-	{ if (GET_CODE (XEXP (X, 0)) == REG				\
-	      && REG_OK_FOR_BASE_P (XEXP (X, 0)))			\
-	    goto ADDR;							\
-	  GO_IF_REG_PLUS_INDEX (XEXP (X, 0), MODE, ADDR); } } }
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-   For the vax, nothing needs to be done.  */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)  {}
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-   On the VAX, the predecrement and postincrement address depend thus
-   (the amount of decrement or increment being the length of the operand)
-   and all indexed address depend thus (because the index scale factor
-   is the length of the operand).  */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	\
- { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC)	\
-     goto LABEL; 							\
-   if (GET_CODE (ADDR) == PLUS)						\
-     { if (CONSTANT_ADDRESS_P (XEXP (ADDR, 0))				\
-	   && GET_CODE (XEXP (ADDR, 1)) == REG);			\
-       else if (CONSTANT_ADDRESS_P (XEXP (ADDR, 1))			\
-		&& GET_CODE (XEXP (ADDR, 0)) == REG);			\
-       else goto LABEL; }}
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE HImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE 1
-
-/* Define this if the case instruction drops through after the table
-   when the index is out of range.  Don't define it if the case insn
-   jumps to the default label instead.  */
-#define CASE_DROPS_THROUGH
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 1
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.  */
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 8
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define if shifts truncate the shift count
-   which implies one can omit a sign-extension or zero-extension
-   of a shift count.  */
-/* #define SHIFT_COUNT_TRUNCATED */
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* This machine doesn't use IEEE floats.  */
-
-#define TARGET_FLOAT_FORMAT VAX_FLOAT_FORMAT
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-/* On a VAX, constants from 0..63 are cheap because they can use the
-   1 byte literal constant format.  compare to -1 should be made cheap
-   so that decrement-and-branch insns can be formed more easily (if
-   the value -1 is copied to a register some decrement-and-branch patterns
-   will not match).  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-    if (INTVAL (RTX) == 0) return 0;				\
-    if ((OUTER_CODE) == AND)					\
-      return ((unsigned) ~INTVAL (RTX) <= 077) ? 1 : 2;		\
-    if ((unsigned) INTVAL (RTX) <= 077) return 1;		\
-    if ((OUTER_CODE) == COMPARE && INTVAL (RTX) == -1)		\
-      return 1;							\
-    if ((OUTER_CODE) == PLUS && (unsigned) -INTVAL (RTX) <= 077)\
-      return 1;							\
-  case CONST:							\
-  case LABEL_REF:						\
-  case SYMBOL_REF:						\
-    return 3;							\
-  case CONST_DOUBLE:						\
-    if (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT)		\
-      return vax_float_literal (RTX) ? 5 : 8;			\
-    else							\
-      return (((CONST_DOUBLE_HIGH (RTX) == 0			\
-		&& (unsigned) CONST_DOUBLE_LOW (RTX) < 64)	\
-	       || ((OUTER_CODE) == PLUS				\
-		   && CONST_DOUBLE_HIGH (RTX) == -1		\
-		   && (unsigned)-CONST_DOUBLE_LOW (RTX) < 64))	\
-	      ? 2 : 5);
-
-#define RTX_COSTS(RTX,CODE,OUTER_CODE) case FIX: case FLOAT:	\
- case MULT: case DIV: case UDIV: case MOD: case UMOD:		\
- case ASHIFT: case LSHIFTRT: case ASHIFTRT:			\
- case ROTATE: case ROTATERT: case PLUS: case MINUS: case IOR:	\
- case XOR: case AND: case NEG: case NOT: case ZERO_EXTRACT:	\
- case SIGN_EXTRACT: case MEM: return vax_rtx_cost(RTX)
-
-#define	ADDRESS_COST(RTX) (1 + (GET_CODE (RTX) == REG ? 0 : vax_address_cost(RTX)))
-
-/* Specify the cost of a branch insn; roughly the number of extra insns that
-   should be added to avoid a branch.
-
-   Branches are extremely cheap on the VAX while the shift insns often
-   used to replace branches can be expensive.  */
-
-#define BRANCH_COST 0
-
-/*
- * We can use the BSD C library routines for the libgcc calls that are
- * still generated, since that's what they boil down to anyways.
- */
-
-#define UDIVSI3_LIBCALL "*udiv"
-#define UMODSI3_LIBCALL "*urem"
-
-/* Check a `double' value for validity for a particular machine mode.  */
-
-/* note that it is very hard to accidentally create a number that fits in a
-   double but not in a float, since their ranges are almost the same */
-
-#define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
-  ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
-
-/* For future reference:
-   D Float: 9 bit, sign magnitude, excess 128 binary exponent
-            normalized 56 bit fraction, redundant bit not represented
-            approximately 16 decimal digits of precision
-
-   The values to use if we trust decimal to binary conversions:
-#define MAX_D_FLOAT 1.7014118346046923e+38
-#define MIN_D_FLOAT .29387358770557188e-38
-
-   G float: 12 bit, sign magnitude, excess 1024 binary exponent
-            normalized 53 bit fraction, redundant bit not represented
-            approximately 15 decimal digits precision
-
-   The values to use if we trust decimal to binary conversions:
-#define MAX_G_FLOAT .898846567431157e+308
-#define MIN_G_FLOAT .556268464626800e-308
-*/
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  No extra ones are needed for the vax.  */
-
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-{ if (GET_CODE (EXP) == SET)					\
-    { if (GET_CODE (SET_SRC (EXP)) == CALL)			\
-	CC_STATUS_INIT;						\
-      else if (GET_CODE (SET_DEST (EXP)) != ZERO_EXTRACT	\
-	       && GET_CODE (SET_DEST (EXP)) != PC)		\
-	{ cc_status.flags = 0;					\
-	  cc_status.value1 = SET_DEST (EXP);			\
-	  cc_status.value2 = SET_SRC (EXP); } }			\
-  else if (GET_CODE (EXP) == PARALLEL				\
-	   && GET_CODE (XVECEXP (EXP, 0, 0)) == SET)		\
-    {								\
-      if (GET_CODE (SET_SRC (XVECEXP (EXP, 0, 0))) == CALL)	\
-	CC_STATUS_INIT;					        \
-      else if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) != PC) \
-	{ cc_status.flags = 0;					\
-	  cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0));	\
-	  cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0)); }   \
-      else							\
-	/* PARALLELs whose first element sets the PC are aob,   \
-	   sob insns.  They do change the cc's.  */		\
-	CC_STATUS_INIT; }					\
-  else CC_STATUS_INIT;						\
-  if (cc_status.value1 && GET_CODE (cc_status.value1) == REG	\
-      && cc_status.value2					\
-      && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))	\
-    cc_status.value2 = 0;					\
-  if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM	\
-      && cc_status.value2					\
-      && GET_CODE (cc_status.value2) == MEM)			\
-    cc_status.value2 = 0; }
-/* Actual condition, one line up, should be that value2's address
-   depends on value1, but that is too much of a pain.  */
-
-#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV)  \
-{ if (cc_status.flags & CC_NO_OVERFLOW)				\
-    return NO_OV;						\
-  return NORMAL; }
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(FILE) fprintf (FILE, "#NO_APP\n");
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* Output before read-only data.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", \
- "r9", "r10", "r11", "ap", "fp", "sp", "pc"}
-
-/* This is BSD, so it wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO
-
-/* How to renumber registers for dbx and gdb.
-   Vax needs no change in the numeration.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Do not break .stabs pseudos into continuations.  */
-
-#define DBX_CONTIN_LENGTH 0
-
-/* This is the char to use for continuation (in case we need to turn
-   continuation back on).  */
-
-#define DBX_CONTIN_CHAR '?'
-
-/* Don't use the `xsfoo;' construct in DBX output; this system
-   doesn't support it.  */
-
-#define DBX_NO_XREFS
-
-/* Output the .stabs for a C `static' variable in the data section.  */
-#define DBX_STATIC_STAB_DATA_SECTION
-
-/* Vax specific: which type character is used for type double?  */
-
-#define ASM_DOUBLE_CHAR (TARGET_G_FLOAT ? 'g' : 'd')
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.
-   It is .dfloat or .gfloat, depending.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)  \
-do { char dstr[30];							\
-     REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", dstr);			\
-     fprintf (FILE, "\t.%cfloat 0%c%s\n", ASM_DOUBLE_CHAR, 		\
-					  ASM_DOUBLE_CHAR, dstr);	\
-   } while (0);
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)  \
-  do { char dstr[30];						\
-       REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", dstr);		\
-       fprintf (FILE, "\t.float 0f%s\n", dstr); } while (0);
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.long "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)  \
-  fprintf (FILE, "\tpushl %s\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)  \
-  fprintf (FILE, "\tmovl (sp)+,%s\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute.
-   (The Vax does not use such vectors,
-   but we must define this macro anyway.)  */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.long L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
-  fprintf (FILE, "\t.align %d\n", (LOG))
-
-/* This is how to output an assembler line
-   that says to advance the location counter by SIZE bytes.  */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\t.space %u\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".comm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
-( fputs (".lcomm ", (FILE)),			\
-  assemble_name ((FILE), (NAME)),		\
-  fprintf ((FILE), ",%u\n", (ROUNDED)))
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* When debugging, we want to output an extra dummy label so that gas
-   can distinguish between D_float and G_float prior to processing the
-   .stabs directive identifying type double.  */
-
-#define ASM_IDENTIFY_LANGUAGE(FILE)	\
-  do {								\
-    output_lang_identify (FILE);				\
-    if (write_symbols == DBX_DEBUG)				\
-      fprintf (FILE, "___vax_%c_doubles:\n", ASM_DOUBLE_CHAR);	\
-  } while (0)
-
-/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
-   Used for C++ multiple inheritance.
-	.mask	^m<r2,r3,r4,r5,r6,r7,r8,r9,r10,r11>	#conservative entry mask
-	addl2	$DELTA, 4(ap)	#adjust first argument
-	jmp	FUNCTION+2	#jump beyond FUNCTION's entry mask
- */
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
-do {						\
-  fprintf (FILE, "\t.word 0x0ffc\n");		\
-  fprintf (FILE, "\taddl2 $%d,4(ap)\n", DELTA);	\
-  fprintf (FILE, "\tjmp ");			\
-  assemble_name (FILE,  XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
-  fprintf (FILE, "+2\n");			\
-} while (0)
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print an instruction operand X on file FILE.
-   CODE is the code from the %-spec that requested printing this operand;
-   if `%z3' was used to print operand 3, then CODE is 'z'.
-
-VAX operand formatting codes:
-
- letter	   print
-   C	reverse branch condition
-   D	64-bit immediate operand
-   B	the low 8 bits of the complement of a constant operand
-   H	the low 16 bits of the complement of a constant operand
-   M	a mask for the N highest bits of a word
-   N	the complement of a constant integer operand
-   P	constant operand plus 1
-   R	32 - constant operand
-   b	the low 8 bits of a negated constant operand
-   h	the low 16 bits of a negated constant operand
-   #	'd' or 'g' depending on whether dfloat or gfloat is used  */
-
-/* The purpose of D is to get around a quirk or bug in vax assembler
-   whereby -1 in a 64-bit immediate operand means 0x00000000ffffffff,
-   which is not a 64-bit minus one.  */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)				\
-  ((CODE) == '#')
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ extern char *rev_cond_name ();					\
-  if (CODE == '#') fputc (ASM_DOUBLE_CHAR, FILE);			\
-  else if (CODE == 'C')							\
-    fputs (rev_cond_name (X), FILE);					\
-  else if (CODE == 'D' && GET_CODE (X) == CONST_INT && INTVAL (X) < 0)	\
-    fprintf (FILE, "$0xffffffff%08x", INTVAL (X));			\
-  else if (CODE == 'P' && GET_CODE (X) == CONST_INT)			\
-    fprintf (FILE, "$%d", INTVAL (X) + 1);				\
-  else if (CODE == 'N' && GET_CODE (X) == CONST_INT)			\
-    fprintf (FILE, "$%d", ~ INTVAL (X));				\
-  /* rotl instruction cannot deal with negative arguments.  */		\
-  else if (CODE == 'R' && GET_CODE (X) == CONST_INT)			\
-    fprintf (FILE, "$%d", 32 - INTVAL (X));				\
-  else if (CODE == 'H' && GET_CODE (X) == CONST_INT)			\
-    fprintf (FILE, "$%d", 0xffff & ~ INTVAL (X));			\
-  else if (CODE == 'h' && GET_CODE (X) == CONST_INT)			\
-    fprintf (FILE, "$%d", (short) - INTVAL (x));			\
-  else if (CODE == 'B' && GET_CODE (X) == CONST_INT)			\
-    fprintf (FILE, "$%d", 0xff & ~ INTVAL (X));				\
-  else if (CODE == 'b' && GET_CODE (X) == CONST_INT)			\
-    fprintf (FILE, "$%d", 0xff & - INTVAL (X));				\
-  else if (CODE == 'M' && GET_CODE (X) == CONST_INT)			\
-    fprintf (FILE, "$%d", ~((1 << INTVAL (x)) - 1));			\
-  else if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%s", reg_names[REGNO (X)]);				\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode)	\
-    { REAL_VALUE_TYPE r; char dstr[30];					\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      REAL_VALUE_TO_DECIMAL (r, "%.20e", dstr);				\
-      fprintf (FILE, "$0f%s", dstr); }					\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode)	\
-    { REAL_VALUE_TYPE r; char dstr[30];					\
-      REAL_VALUE_FROM_CONST_DOUBLE (r, X);				\
-      REAL_VALUE_TO_DECIMAL (r, "%.20e", dstr);				\
-      fprintf (FILE, "$0%c%s", ASM_DOUBLE_CHAR, dstr); }		\
-  else { putc ('$', FILE); output_addr_const (FILE, X); }}
-
-/* Print a memory operand whose address is X, on file FILE.
-   This uses a function in output-vax.c.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
- print_operand_address (FILE, ADDR)
diff --git a/gcc/config/vax/vax.md b/gcc/config/vax/vax.md
deleted file mode 100755
index 4ca4668..0000000
--- a/gcc/config/vax/vax.md
+++ /dev/null
@@ -1,2136 +0,0 @@
-;;- Machine description for GNU compiler, Vax Version
-;;   Copyright (C) 1987, 88, 91, 94-96, 1998 Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- Instruction patterns.  When multiple patterns apply,
-;;- the first one in the file is chosen.
-;;-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-;;-
-;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
-;;- updates for most instructions.
-
-;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
-;; be folded while optimizing anyway.
-
-(define_insn "tstsi"
-  [(set (cc0)
-	(match_operand:SI 0 "nonimmediate_operand" "g"))]
-  ""
-  "tstl %0")
-
-(define_insn "tsthi"
-  [(set (cc0)
-	(match_operand:HI 0 "nonimmediate_operand" "g"))]
-  ""
-  "tstw %0")
-
-(define_insn "tstqi"
-  [(set (cc0)
-	(match_operand:QI 0 "nonimmediate_operand" "g"))]
-  ""
-  "tstb %0")
-
-(define_insn "tstdf"
-  [(set (cc0)
-	(match_operand:DF 0 "general_operand" "gF"))]
-  ""
-  "tst%# %0")
-
-(define_insn "tstsf"
-  [(set (cc0)
-	(match_operand:SF 0 "general_operand" "gF"))]
-  ""
-  "tstf %0")
-
-(define_insn "cmpsi"
-  [(set (cc0)
-	(compare (match_operand:SI 0 "nonimmediate_operand" "g")
-		 (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "cmpl %0,%1")
-
-(define_insn "cmphi"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "nonimmediate_operand" "g")
-		 (match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "cmpw %0,%1")
-
-(define_insn "cmpqi"
-  [(set (cc0)
-	(compare (match_operand:QI 0 "nonimmediate_operand" "g")
-		 (match_operand:QI 1 "general_operand" "g")))]
-  ""
-  "cmpb %0,%1")
-
-(define_insn "cmpdf"
-  [(set (cc0)
-	(compare (match_operand:DF 0 "general_operand" "gF,gF")
-		 (match_operand:DF 1 "general_operand" "G,gF")))]
-  ""
-  "@
-   tst%# %0
-   cmp%# %0,%1")
-
-(define_insn "cmpsf"
-  [(set (cc0)
-	(compare (match_operand:SF 0 "general_operand" "gF,gF")
-		 (match_operand:SF 1 "general_operand" "G,gF")))]
-  ""
-  "@
-   tstf %0
-   cmpf %0,%1")
-
-(define_insn ""
-  [(set (cc0)
-	(and:SI (match_operand:SI 0 "general_operand" "g")
-		(match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "bitl %0,%1")
-
-(define_insn ""
-  [(set (cc0)
-	(and:HI (match_operand:HI 0 "general_operand" "g")
-		(match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "bitw %0,%1")
-
-(define_insn ""
-  [(set (cc0)
-	(and:QI (match_operand:QI 0 "general_operand" "g")
-		(match_operand:QI 1 "general_operand" "g")))]
-  ""
-  "bitb %0,%1")
-
-;; The vax has no sltu or sgeu patterns, but does have two-operand
-;; add/subtract with carry.  This is still better than the alternative.
-;; Since the cc0-using insn cannot be separated from the cc0-setting insn,
-;; and the two are created independently, we can't just use a define_expand
-;; to try to optimize this.  (The "movl" and "clrl" insns alter the cc0
-;; flags, but leave the carry flag alone, but that can't easily be expressed.)
-;;
-;; Several two-operator combinations could be added to make slightly more
-;; optimal code, but they'd have to cover all combinations of plus and minus
-;; using match_dup.  If you want to do this, I'd suggest changing the "sgeu"
-;; pattern to something like (minus (const_int 1) (ltu ...)), so fewer
-;; patterns need to be recognized.
-;; -- Ken Raeburn (Raeburn@Watch.COM) 24 August 1991.
-
-(define_insn "sltu"
-  [(set (match_operand:SI 0 "general_operand" "=ro")
-	(ltu (cc0) (const_int 0)))]
-  ""
-  "clrl %0\;adwc $0,%0")
-
-(define_insn "sgeu"
-  [(set (match_operand:SI 0 "general_operand" "=ro")
-	(geu (cc0) (const_int 0)))]
-  ""
-  "movl $1,%0\;sbwc $0,%0")
-
-(define_insn "movdf"
-  [(set (match_operand:DF 0 "general_operand" "=g,g")
-	(match_operand:DF 1 "general_operand" "G,gF"))]
-  ""
-  "@
-   clr%# %0
-   mov%# %1,%0")
-
-(define_insn "movsf"
-  [(set (match_operand:SF 0 "general_operand" "=g,g")
-	(match_operand:SF 1 "general_operand" "G,gF"))]
-  ""
-  "@
-   clrf %0
-   movf %1,%0")
-
-;; Some vaxes don't support this instruction.
-;;(define_insn "movti"
-;;  [(set (match_operand:TI 0 "general_operand" "=g")
-;;	(match_operand:TI 1 "general_operand" "g"))]
-;;  ""
-;;  "movh %1,%0")
-
-(define_insn "movdi"
-  [(set (match_operand:DI 0 "general_operand" "=g,g")
-	(match_operand:DI 1 "general_operand" "I,g"))]
-  ""
-  "@
-   clrq %0
-   movq %D1,%0")
-
-;; The VAX move instructions have space-time tradeoffs.  On a microVAX
-;; register-register mov instructions take 3 bytes and 2 CPU cycles.  clrl
-;; takes 2 bytes and 3 cycles.  mov from constant to register takes 2 cycles
-;; if the constant is smaller than 4 bytes, 3 cycles for a longword
-;; constant.  movz, mneg, and mcom are as fast as mov, so movzwl is faster
-;; than movl for positive constants that fit in 16 bits but not 6 bits.  cvt
-;; instructions take 4 cycles.  inc takes 3 cycles.  The machine description
-;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
-;; instead of movl).
-
-;; Cycle counts for other models may vary (on a VAX 750 they are similar,
-;; but on a VAX 9000 most move and add instructions with one constant
-;; operand take 1 cycle).
-
-;;  Loads of constants between 64 and 128 used to be done with
-;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
-
-(define_insn "movsi"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operand:SI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  rtx link;
-  if (operands[1] == const1_rtx
-      && (link = find_reg_note (insn, REG_WAS_0, 0))
-      /* Make sure the insn that stored the 0 is still present.  */
-      && ! INSN_DELETED_P (XEXP (link, 0))
-      && GET_CODE (XEXP (link, 0)) != NOTE
-      /* Make sure cross jumping didn't happen here.  */
-      && no_labels_between_p (XEXP (link, 0), insn)
-      /* Make sure the reg hasn't been clobbered.  */
-      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
-    return \"incl %0\";
-  if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
-    {
-      if (push_operand (operands[0], SImode))
-	return \"pushab %a1\";
-      return \"movab %a1,%0\";
-    }
-  if (operands[1] == const0_rtx)
-    return \"clrl %0\";
-  if (GET_CODE (operands[1]) == CONST_INT
-      && (unsigned) INTVAL (operands[1]) >= 64)
-    {
-      int i = INTVAL (operands[1]);
-      if ((unsigned)(~i) < 64)
-	return \"mcoml %N1,%0\";
-      if ((unsigned)i < 0x100)
-	return \"movzbl %1,%0\";
-      if (i >= -0x80 && i < 0)
-	return \"cvtbl %1,%0\";
-      if ((unsigned)i < 0x10000)
-	return \"movzwl %1,%0\";
-      if (i >= -0x8000 && i < 0)
-	return \"cvtwl %1,%0\";
-    }
-  if (push_operand (operands[0], SImode))
-    return \"pushl %1\";
-  return \"movl %1,%0\";
-}")
-
-(define_insn "movhi"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(match_operand:HI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  rtx link;
-  if (operands[1] == const1_rtx
-      && (link = find_reg_note (insn, REG_WAS_0, 0))
-      /* Make sure the insn that stored the 0 is still present.  */
-      && ! INSN_DELETED_P (XEXP (link, 0))
-      && GET_CODE (XEXP (link, 0)) != NOTE
-      /* Make sure cross jumping didn't happen here.  */
-      && no_labels_between_p (XEXP (link, 0), insn)
-      /* Make sure the reg hasn't been clobbered.  */
-      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
-    return \"incw %0\";
-
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      int i = INTVAL (operands[1]);
-      if (i == 0)
-	return \"clrw %0\";
-      else if ((unsigned int)i < 64)
-	return \"movw %1,%0\";
-      else if ((unsigned int)~i < 64)
-	return \"mcomw %H1,%0\";
-      else if ((unsigned int)i < 256)
-	return \"movzbw %1,%0\";
-    }
-  return \"movw %1,%0\";
-}")
-
-(define_insn "movstricthi"
-  [(set (strict_low_part (match_operand:HI 0 "register_operand" "=g"))
-	(match_operand:HI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      int i = INTVAL (operands[1]);
-      if (i == 0)
-	return \"clrw %0\";
-      else if ((unsigned int)i < 64)
-	return \"movw %1,%0\";
-      else if ((unsigned int)~i < 64)
-	return \"mcomw %H1,%0\";
-      else if ((unsigned int)i < 256)
-	return \"movzbw %1,%0\";
-    }
-  return \"movw %1,%0\";
-}")
-
-(define_insn "movqi"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(match_operand:QI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  rtx link;
-  if (operands[1] == const1_rtx
-      && (link = find_reg_note (insn, REG_WAS_0, 0))
-      /* Make sure the insn that stored the 0 is still present.  */
-      && ! INSN_DELETED_P (XEXP (link, 0))
-      && GET_CODE (XEXP (link, 0)) != NOTE
-      /* Make sure cross jumping didn't happen here.  */
-      && no_labels_between_p (XEXP (link, 0), insn)
-      /* Make sure the reg hasn't been clobbered.  */
-      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
-    return \"incb %0\";
-
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      int i = INTVAL (operands[1]);
-      if (i == 0)
-	return \"clrb %0\";
-      else if ((unsigned int)~i < 64)
-	return \"mcomb %B1,%0\";
-    }
-  return \"movb %1,%0\";
-}")
-
-(define_insn "movstrictqi"
-  [(set (strict_low_part (match_operand:QI 0 "register_operand" "=g"))
-	(match_operand:QI 1 "general_operand" "g"))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      int i = INTVAL (operands[1]);
-      if (i == 0)
-	return \"clrb %0\";
-      else if ((unsigned int)~i < 64)
-	return \"mcomb %B1,%0\";
-    }
-  return \"movb %1,%0\";
-}")
-
-;; This is here to accept 4 arguments and pass the first 3 along
-;; to the movstrhi1 pattern that really does the work.
-(define_expand "movstrhi"
-  [(set (match_operand:BLK 0 "general_operand" "=g")
-	(match_operand:BLK 1 "general_operand" "g"))
-   (use (match_operand:HI 2 "general_operand" "g"))
-   (match_operand 3 "" "")]
-  ""
-  "
-  emit_insn (gen_movstrhi1 (operands[0], operands[1], operands[2]));
-  DONE;
-")
-
-;; The definition of this insn does not really explain what it does,
-;; but it should suffice
-;; that anything generated as this insn will be recognized as one
-;; and that it won't successfully combine with anything.
-(define_insn "movstrhi1"
-  [(set (match_operand:BLK 0 "general_operand" "=g")
-	(match_operand:BLK 1 "general_operand" "g"))
-   (use (match_operand:HI 2 "general_operand" "g"))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 1))
-   (clobber (reg:SI 2))
-   (clobber (reg:SI 3))
-   (clobber (reg:SI 4))
-   (clobber (reg:SI 5))]
-  ""
-  "movc3 %2,%1,%0")
-
-;; Extension and truncation insns.
-
-(define_insn "truncsiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
-  ""
-  "cvtlb %1,%0")
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
-  ""
-  "cvtlw %1,%0")
-
-(define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
-  ""
-  "cvtwb %1,%0")
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
-  ""
-  "cvtwl %1,%0")
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
-  ""
-  "cvtbw %1,%0")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
-  ""
-  "cvtbl %1,%0")
-
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "general_operand" "=g")
-	(float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
-  ""
-  "cvtf%# %1,%0")
-
-(define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "general_operand" "=g")
-	(float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
-  ""
-  "cvt%#f %1,%0")
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
-  ""
-  "movzwl %1,%0")
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
-  ""
-  "movzbw %1,%0")
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
-  ""
-  "movzbl %1,%0")
-
-;; Fix-to-float conversion insns.
-
-(define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "general_operand" "=g")
-	(float:SF (match_operand:SI 1 "nonimmediate_operand" "g")))]
-  ""
-  "cvtlf %1,%0")
-
-(define_insn "floatsidf2"
-  [(set (match_operand:DF 0 "general_operand" "=g")
-	(float:DF (match_operand:SI 1 "nonimmediate_operand" "g")))]
-  ""
-  "cvtl%# %1,%0")
-
-(define_insn "floathisf2"
-  [(set (match_operand:SF 0 "general_operand" "=g")
-	(float:SF (match_operand:HI 1 "nonimmediate_operand" "g")))]
-  ""
-  "cvtwf %1,%0")
-
-(define_insn "floathidf2"
-  [(set (match_operand:DF 0 "general_operand" "=g")
-	(float:DF (match_operand:HI 1 "nonimmediate_operand" "g")))]
-  ""
-  "cvtw%# %1,%0")
-
-(define_insn "floatqisf2"
-  [(set (match_operand:SF 0 "general_operand" "=g")
-	(float:SF (match_operand:QI 1 "nonimmediate_operand" "g")))]
-  ""
-  "cvtbf %1,%0")
-
-(define_insn "floatqidf2"
-  [(set (match_operand:DF 0 "general_operand" "=g")
-	(float:DF (match_operand:QI 1 "nonimmediate_operand" "g")))]
-  ""
-  "cvtb%# %1,%0")
-
-;; Float-to-fix conversion insns.
-
-(define_insn "fix_truncsfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
-  ""
-  "cvtfb %1,%0")
-
-(define_insn "fix_truncsfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
-  ""
-  "cvtfw %1,%0")
-
-(define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
-  ""
-  "cvtfl %1,%0")
-
-(define_insn "fix_truncdfqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
-  ""
-  "cvt%#b %1,%0")
-
-(define_insn "fix_truncdfhi2"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
-  ""
-  "cvt%#w %1,%0")
-
-(define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
-  ""
-  "cvt%#l %1,%0")
-
-;;- All kinds of add instructions.
-
-(define_insn "adddf3"
-  [(set (match_operand:DF 0 "general_operand" "=g,g,g")
-	(plus:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
-		 (match_operand:DF 2 "general_operand" "gF,0,gF")))]
-  ""
-  "@
-   add%#2 %2,%0
-   add%#2 %1,%0
-   add%#3 %1,%2,%0")
-
-(define_insn "addsf3"
-  [(set (match_operand:SF 0 "general_operand" "=g,g,g")
-	(plus:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
-		 (match_operand:SF 2 "general_operand" "gF,0,gF")))]
-  ""
-  "@
-   addf2 %2,%0
-   addf2 %1,%0
-   addf3 %1,%2,%0")
-
-/* The space-time-opcode tradeoffs for addition vary by model of VAX.
-
-   On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3",
-   but it not faster on other models.
-
-   "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is
-   faster on a VAX 3, but some VAXes (e.g. VAX 9000) will stall if
-   a register is used in an address too soon after it is set.
-   Compromise by using movab only when it is shorter than the add
-   or the base register in the address is one of sp, ap, and fp,
-   which are not modified very often.  */
-
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(plus:SI (match_operand:SI 1 "general_operand" "g")
-		 (match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      if (operands[2] == const1_rtx)
-	return \"incl %0\";
-      if (operands[2] == constm1_rtx)
-	return \"decl %0\";
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && (unsigned) (- INTVAL (operands[2])) < 64)
-	return \"subl2 $%n2,%0\";
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && (unsigned) INTVAL (operands[2]) >= 64
-	  && GET_CODE (operands[1]) == REG
-	  && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
-	      || REGNO (operands[1]) > 11))
-	return \"movab %c2(%1),%0\";
-      return \"addl2 %2,%0\";
-    }
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"addl2 %1,%0\";
-
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) < 32767
-      && INTVAL (operands[2]) > -32768
-      && GET_CODE (operands[1]) == REG
-      && push_operand (operands[0], SImode))
-    return \"pushab %c2(%1)\";
-
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned) (- INTVAL (operands[2])) < 64)
-    return \"subl3 $%n2,%1,%0\";
-
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned) INTVAL (operands[2]) >= 64
-      && GET_CODE (operands[1]) == REG
-      && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
-	  || REGNO (operands[1]) > 11))
-    return \"movab %c2(%1),%0\";
-
-  /* Add this if using gcc on a VAX 3xxx:
-  if (REG_P (operands[1]) && REG_P (operands[2]))
-    return \"movab (%1)[%2],%0\";
-  */
-  return \"addl3 %1,%2,%0\";
-}")
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(plus:HI (match_operand:HI 1 "general_operand" "g")
-		 (match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      if (operands[2] == const1_rtx)
-	return \"incw %0\";
-      if (operands[2] == constm1_rtx)
-	return \"decw %0\";
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && (unsigned) (- INTVAL (operands[2])) < 64)
-	return \"subw2 $%n2,%0\";
-      return \"addw2 %2,%0\";
-    }
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"addw2 %1,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned) (- INTVAL (operands[2])) < 64)
-    return \"subw3 $%n2,%1,%0\";
-  return \"addw3 %1,%2,%0\";
-}")
-
-(define_insn "addqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(plus:QI (match_operand:QI 1 "general_operand" "g")
-		 (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      if (operands[2] == const1_rtx)
-	return \"incb %0\";
-      if (operands[2] == constm1_rtx)
-	return \"decb %0\";
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && (unsigned) (- INTVAL (operands[2])) < 64)
-	return \"subb2 $%n2,%0\";
-      return \"addb2 %2,%0\";
-    }
-  if (rtx_equal_p (operands[0], operands[2]))
-    return \"addb2 %1,%0\";
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned) (- INTVAL (operands[2])) < 64)
-    return \"subb3 $%n2,%1,%0\";
-  return \"addb3 %1,%2,%0\";
-}")
-
-;; The add-with-carry (adwc) instruction only accepts two operands.
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "general_operand" "=ro>,ro>")
-	(plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
-		 (match_operand:DI 2 "general_operand" "Fro,F")))]
-  ""
-  "*
-{
-  rtx low[3];
-  char *pattern;
-  int carry = 1;
-
-  split_quadword_operands (operands, low, 3);
-  /* Add low parts.  */
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      if (low[2] == const0_rtx)
-	/* Should examine operand, punt if not POST_INC.  */
-	pattern = \"tstl %0\", carry = 0;
-      else if (low[2] == const1_rtx)
-        pattern = \"incl %0\";
-      else
-        pattern = \"addl2 %2,%0\";
-    }
-  else
-    {
-      if (low[2] == const0_rtx)
-	pattern = \"movl %1,%0\", carry = 0;
-      else
-	pattern = \"addl3 %2,%1,%0\";
-    }
-  if (pattern)
-    output_asm_insn (pattern, low);
-  if (!carry)
-    /* If CARRY is 0, we don't have any carry value to worry about.  */
-    return OUT_FCN (CODE_FOR_addsi3) (operands, insn);
-  /* %0 = C + %1 + %2 */
-  if (!rtx_equal_p (operands[0], operands[1]))
-    output_asm_insn ((operands[1] == const0_rtx
-		      ? \"clrl %0\"
-		      : \"movl %1,%0\"), operands);
-  return \"adwc %2,%0\";
-}")
-
-;;- All kinds of subtract instructions.
-
-(define_insn "subdf3"
-  [(set (match_operand:DF 0 "general_operand" "=g,g")
-	(minus:DF (match_operand:DF 1 "general_operand" "0,gF")
-		  (match_operand:DF 2 "general_operand" "gF,gF")))]
-  ""
-  "@
-   sub%#2 %2,%0
-   sub%#3 %2,%1,%0")
-
-(define_insn "subsf3"
-  [(set (match_operand:SF 0 "general_operand" "=g,g")
-	(minus:SF (match_operand:SF 1 "general_operand" "0,gF")
-		  (match_operand:SF 2 "general_operand" "gF,gF")))]
-  ""
-  "@
-   subf2 %2,%0
-   subf3 %2,%1,%0")
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g,g")
-	(minus:SI (match_operand:SI 1 "general_operand" "0,g")
-		  (match_operand:SI 2 "general_operand" "g,g")))]
-  ""
-  "@
-   subl2 %2,%0
-   subl3 %2,%1,%0")
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g,g")
-	(minus:HI (match_operand:HI 1 "general_operand" "0,g")
-		  (match_operand:HI 2 "general_operand" "g,g")))]
-  ""
-  "@
-   subw2 %2,%0
-   subw3 %2,%1,%0")
-
-(define_insn "subqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g,g")
-	(minus:QI (match_operand:QI 1 "general_operand" "0,g")
-		  (match_operand:QI 2 "general_operand" "g,g")))]
-  ""
-  "@
-   subb2 %2,%0
-   subb3 %2,%1,%0")
-
-;; The subtract-with-carry (sbwc) instruction only takes two operands.
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "general_operand" "=or>,or>")
-	(minus:DI (match_operand:DI 1 "general_operand" "0,or>")
-		  (match_operand:DI 2 "general_operand" "For,F")))]
-  ""
-  "*
-{
-  rtx low[3];
-  char *pattern;
-  int carry = 1;
-
-  split_quadword_operands (operands, low, 3);
-  /* Subtract low parts.  */
-  if (rtx_equal_p (operands[0], operands[1]))
-    {
-      if (low[2] == const0_rtx)
-	pattern = 0, carry = 0;
-      else if (low[2] == constm1_rtx)
-	pattern = \"decl %0\";
-      else
-	pattern = \"subl2 %2,%0\";
-    }
-  else
-    {
-      if (low[2] == constm1_rtx)
-	pattern = \"decl %0\";
-      else if (low[2] == const0_rtx)
-	pattern = OUT_FCN (CODE_FOR_movsi) (low, insn), carry = 0;
-      else
-	pattern = \"subl3 %2,%1,%0\";
-    }
-  if (pattern)
-    output_asm_insn (pattern, low);
-  if (carry)
-    {
-      if (!rtx_equal_p (operands[0], operands[1]))
-	return \"movl %1,%0\;sbwc %2,%0\";
-      return \"sbwc %2,%0\";
-      /* %0 = %2 - %1 - C */
-    }
-  return OUT_FCN (CODE_FOR_subsi3) (operands, insn);
-}")
-
-;;- Multiply instructions.
-
-(define_insn "muldf3"
-  [(set (match_operand:DF 0 "general_operand" "=g,g,g")
-	(mult:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
-		 (match_operand:DF 2 "general_operand" "gF,0,gF")))]
-  ""
-  "@
-   mul%#2 %2,%0
-   mul%#2 %1,%0
-   mul%#3 %1,%2,%0")
-
-(define_insn "mulsf3"
-  [(set (match_operand:SF 0 "general_operand" "=g,g,g")
-	(mult:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
-		 (match_operand:SF 2 "general_operand" "gF,0,gF")))]
-  ""
-  "@
-   mulf2 %2,%0
-   mulf2 %1,%0
-   mulf3 %1,%2,%0")
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g,g,g")
-	(mult:SI (match_operand:SI 1 "general_operand" "0,g,g")
-		 (match_operand:SI 2 "general_operand" "g,0,g")))]
-  ""
-  "@
-   mull2 %2,%0
-   mull2 %1,%0
-   mull3 %1,%2,%0")
-
-(define_insn "mulhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g,g,")
-	(mult:HI (match_operand:HI 1 "general_operand" "0,g,g")
-		 (match_operand:HI 2 "general_operand" "g,0,g")))]
-  ""
-  "@
-   mulw2 %2,%0
-   mulw2 %1,%0
-   mulw3 %1,%2,%0")
-
-(define_insn "mulqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g,g,g")
-	(mult:QI (match_operand:QI 1 "general_operand" "0,g,g")
-		 (match_operand:QI 2 "general_operand" "g,0,g")))]
-  ""
-  "@
-   mulb2 %2,%0
-   mulb2 %1,%0
-   mulb3 %1,%2,%0")
-
-(define_insn "mulsidi3"
-  [(set (match_operand:DI 0 "general_operand" "=g")
-	(mult:DI (sign_extend:DI
-		  (match_operand:SI 1 "nonimmediate_operand" "g"))
-		 (sign_extend:DI
-		  (match_operand:SI 2 "nonimmediate_operand" "g"))))]
-  ""
-  "emul %1,%2,$0,%0")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=g")
-	(plus:DI
-	 (mult:DI (sign_extend:DI
-		   (match_operand:SI 1 "nonimmediate_operand" "g"))
-		  (sign_extend:DI
-		   (match_operand:SI 2 "nonimmediate_operand" "g")))
-	 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
-  ""
-  "emul %1,%2,%3,%0")
-
-;; 'F' constraint means type CONST_DOUBLE
-(define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=g")
-	(plus:DI
-	 (mult:DI (sign_extend:DI
-		   (match_operand:SI 1 "nonimmediate_operand" "g"))
-		  (sign_extend:DI
-		   (match_operand:SI 2 "nonimmediate_operand" "g")))
-	 (match_operand:DI 3 "immediate_operand" "F")))]
-  "GET_CODE (operands[3]) == CONST_DOUBLE 
-    && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
-  "*
-{
-  if (CONST_DOUBLE_HIGH (operands[3]))
-    operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
-  return \"emul %1,%2,%3,%0\";
-}")
-
-;;- Divide instructions.
-
-(define_insn "divdf3"
-  [(set (match_operand:DF 0 "general_operand" "=g,g")
-	(div:DF (match_operand:DF 1 "general_operand" "0,gF")
-		(match_operand:DF 2 "general_operand" "gF,gF")))]
-  ""
-  "@
-   div%#2 %2,%0
-   div%#3 %2,%1,%0")
-
-(define_insn "divsf3"
-  [(set (match_operand:SF 0 "general_operand" "=g,g")
-	(div:SF (match_operand:SF 1 "general_operand" "0,gF")
-		(match_operand:SF 2 "general_operand" "gF,gF")))]
-  ""
-  "@
-   divf2 %2,%0
-   divf3 %2,%1,%0")
-
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g,g")
-	(div:SI (match_operand:SI 1 "general_operand" "0,g")
-		(match_operand:SI 2 "general_operand" "g,g")))]
-  ""
-  "@
-   divl2 %2,%0
-   divl3 %2,%1,%0")
-
-(define_insn "divhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g,g")
-	(div:HI (match_operand:HI 1 "general_operand" "0,g")
-		(match_operand:HI 2 "general_operand" "g,g")))]
-  ""
-  "@
-   divw2 %2,%0
-   divw3 %2,%1,%0")
-
-(define_insn "divqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g,g")
-	(div:QI (match_operand:QI 1 "general_operand" "0,g")
-		(match_operand:QI 2 "general_operand" "g,g")))]
-  ""
-  "@
-   divb2 %2,%0
-   divb3 %2,%1,%0")
-
-;This is left out because it is very slow;
-;we are better off programming around the "lack" of this insn.
-;(define_insn "divmoddisi4"
-;  [(set (match_operand:SI 0 "general_operand" "=g")
-;	(div:SI (match_operand:DI 1 "general_operand" "g")
-;		(match_operand:SI 2 "general_operand" "g")))
-;   (set (match_operand:SI 3 "general_operand" "=g")
-;	(mod:SI (match_operand:DI 1 "general_operand" "g")
-;		(match_operand:SI 2 "general_operand" "g")))]
-;  ""
-;  "ediv %2,%1,%0,%3")
-
-;; Bit-and on the vax is done with a clear-bits insn.
-(define_expand "andsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
-		(match_operand:SI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  rtx op1 = operands[1];
-
-  /* If there is a constant argument, complement that one.  */
-  if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
-    {
-      operands[1] = operands[2];
-      operands[2] = op1;
-      op1 = operands[1];
-    }
-
-  if (GET_CODE (op1) == CONST_INT)
-    operands[1] = GEN_INT (~INTVAL (op1));
-  else
-    operands[1] = expand_unop (SImode, one_cmpl_optab, op1, 0, 1);
-}")
-
-(define_expand "andhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
-		(match_operand:HI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  rtx op1 = operands[1];
-
-  if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
-    {
-      operands[1] = operands[2];
-      operands[2] = op1;
-      op1 = operands[1];
-    }
-
-  if (GET_CODE (op1) == CONST_INT)
-    operands[1] = GEN_INT (65535 & ~INTVAL (op1));
-  else
-    operands[1] = expand_unop (HImode, one_cmpl_optab, op1, 0, 1);
-}")
-
-(define_expand "andqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
-		(match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  rtx op1 = operands[1];
-
-  if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
-    {
-     operands[1] = operands[2];
-     operands[2] = op1;
-     op1 = operands[1];
-   }
-
-  if (GET_CODE (op1) == CONST_INT)
-    operands[1] = GEN_INT (255 & ~INTVAL (op1));
-  else
-    operands[1] = expand_unop (QImode, one_cmpl_optab, op1, 0, 1);
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g,g")
-	(and:SI (not:SI (match_operand:SI 1 "general_operand" "g,g"))
-		(match_operand:SI 2 "general_operand" "0,g")))]
-  ""
-  "@
-   bicl2 %1,%0
-   bicl3 %1,%2,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g,g")
-	(and:HI (not:HI (match_operand:HI 1 "general_operand" "g,g"))
-		(match_operand:HI 2 "general_operand" "0,g")))]
-  ""
-  "@
-   bicw2 %1,%0
-   bicw3 %1,%2,%0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g,g")
-	(and:QI (not:QI (match_operand:QI 1 "general_operand" "g,g"))
-		(match_operand:QI 2 "general_operand" "0,g")))]
-  ""
-  "@
-   bicb2 %1,%0
-   bicb3 %1,%2,%0")
-
-;; The following used to be needed because constant propagation can
-;; create them starting from the bic insn patterns above.  This is no
-;; longer a problem.  However, having these patterns allows optimization
-;; opportunities in combine.c.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g,g")
-	(and:SI (match_operand:SI 1 "general_operand" "0,g")
-		(match_operand:SI 2 "const_int_operand" "n,n")))]
-  ""
-  "@
-   bicl2 %N2,%0
-   bicl3 %N2,%1,%0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=g,g")
-	(and:HI (match_operand:HI 1 "general_operand" "0,g")
-		(match_operand:HI 2 "const_int_operand" "n,n")))]
-  ""
-  "@
-   bicw2 %H2,%0
-   bicw3 %H2,%1,%0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "general_operand" "=g,g")
-	(and:QI (match_operand:QI 1 "general_operand" "0,g")
-		(match_operand:QI 2 "const_int_operand" "n,n")))]
-  ""
-  "@
-   bicb2 %B2,%0
-   bicb3 %B2,%1,%0")
-
-;;- Bit set instructions.
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g,g,g")
-	(ior:SI (match_operand:SI 1 "general_operand" "0,g,g")
-		(match_operand:SI 2 "general_operand" "g,0,g")))]
-  ""
-  "@
-   bisl2 %2,%0
-   bisl2 %1,%0
-   bisl3 %2,%1,%0")
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g,g,g")
-	(ior:HI (match_operand:HI 1 "general_operand" "0,g,g")
-		(match_operand:HI 2 "general_operand" "g,0,g")))]
-  ""
-  "@
-   bisw2 %2,%0
-   bisw2 %1,%0
-   bisw3 %2,%1,%0")
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g,g,g")
-	(ior:QI (match_operand:QI 1 "general_operand" "0,g,g")
-		(match_operand:QI 2 "general_operand" "g,0,g")))]
-  ""
-  "@
-   bisb2 %2,%0
-   bisb2 %1,%0
-   bisb3 %2,%1,%0")
-
-;;- xor instructions.
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g,g,g")
-	(xor:SI (match_operand:SI 1 "general_operand" "0,g,g")
-		(match_operand:SI 2 "general_operand" "g,0,g")))]
-  ""
-  "@
-   xorl2 %2,%0
-   xorl2 %1,%0
-   xorl3 %2,%1,%0")
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "general_operand" "=g,g,g")
-	(xor:HI (match_operand:HI 1 "general_operand" "0,g,g")
-		(match_operand:HI 2 "general_operand" "g,0,g")))]
-  ""
-  "@
-   xorw2 %2,%0
-   xorw2 %1,%0
-   xorw3 %2,%1,%0")
-
-(define_insn "xorqi3"
-  [(set (match_operand:QI 0 "general_operand" "=g,g,g")
-	(xor:QI (match_operand:QI 1 "general_operand" "0,g,g")
-		(match_operand:QI 2 "general_operand" "g,0,g")))]
-  ""
-  "@
-   xorb2 %2,%0
-   xorb2 %1,%0
-   xorb3 %2,%1,%0")
-
-(define_insn "negdf2"
-  [(set (match_operand:DF 0 "general_operand" "=g")
-	(neg:DF (match_operand:DF 1 "general_operand" "gF")))]
-  ""
-  "mneg%# %1,%0")
-
-(define_insn "negsf2"
-  [(set (match_operand:SF 0 "general_operand" "=g")
-	(neg:SF (match_operand:SF 1 "general_operand" "gF")))]
-  ""
-  "mnegf %1,%0")
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(neg:SI (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "mnegl %1,%0")
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(neg:HI (match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "mnegw %1,%0")
-
-(define_insn "negqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(neg:QI (match_operand:QI 1 "general_operand" "g")))]
-  ""
-  "mnegb %1,%0")
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(not:SI (match_operand:SI 1 "general_operand" "g")))]
-  ""
-  "mcoml %1,%0")
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "general_operand" "=g")
-	(not:HI (match_operand:HI 1 "general_operand" "g")))]
-  ""
-  "mcomw %1,%0")
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "general_operand" "=g")
-	(not:QI (match_operand:QI 1 "general_operand" "g")))]
-  ""
-  "mcomb %1,%0")
-
-;; Arithmetic right shift on the vax works by negating the shift count,
-;; then emitting a right shift with the shift count negated.  This means
-;; that all actual shift counts in the RTL will be positive.  This 
-;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
-;; which isn't valid.
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
-		   (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
-		     (match_operand:QI 2 "const_int_operand" "n")))]
-  ""
-  "ashl $%n2,%1,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
-		     (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
-  ""
-  "ashl %2,%1,%0")
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(ashift:SI (match_operand:SI 1 "general_operand" "g")
-		   (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
-    return \"addl2 %0,%0\";
-  if (GET_CODE (operands[1]) == REG
-      && GET_CODE (operands[2]) == CONST_INT)
-    {
-      int i = INTVAL (operands[2]);
-      if (i == 1)
-	return \"addl3 %1,%1,%0\";
-      if (i == 2)
-	return \"moval 0[%1],%0\";
-      if (i == 3)
-	return \"movad 0[%1],%0\";
-    }
-  return \"ashl %2,%1,%0\";
-}")
-
-;; Arithmetic right shift on the vax works by negating the shift count.
-(define_expand "ashrdi3"
-  [(set (match_operand:DI 0 "general_operand" "=g")
-	(ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
-		     (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
-}")
-
-(define_insn "ashldi3"
-  [(set (match_operand:DI 0 "general_operand" "=g")
-	(ashift:DI (match_operand:DI 1 "general_operand" "g")
-		   (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "ashq %2,%1,%0")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=g")
-	(ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
-		     (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
-  ""
-  "ashq %2,%1,%0")
-
-;; We used to have expand_shift handle logical right shifts by using extzv,
-;; but this make it very difficult to do lshrdi3.  Since the VAX is the
-;; only machine with this kludge, it's better to just do this with a
-;; define_expand and remove that case from expand_shift.
-
-(define_expand "lshrsi3"
-  [(set (match_dup 3)
-	(minus:QI (const_int 32)
-		  (match_dup 4)))
-   (set (match_operand:SI 0 "general_operand" "=g")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_dup 3)
-			 (match_operand:SI 2 "register_operand" "g")))]
-  ""
-  "
-{
-  operands[3] = gen_reg_rtx (QImode);
-  operands[4] = gen_lowpart (QImode, operands[2]);
-}")
-
-;; Rotate right on the vax works by negating the shift count.
-(define_expand "rotrsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(rotatert:SI (match_operand:SI 1 "general_operand" "g")
-		     (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
-}")
-
-(define_insn "rotlsi3"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(rotate:SI (match_operand:SI 1 "general_operand" "g")
-		   (match_operand:QI 2 "general_operand" "g")))]
-  ""
-  "rotl %2,%1,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(rotatert:SI (match_operand:SI 1 "general_operand" "g")
-		     (match_operand:QI 2 "const_int_operand" "n")))]
-  ""
-  "rotl %R2,%1,%0")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(rotatert:SI (match_operand:SI 1 "general_operand" "g")
-		     (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
-  ""
-  "rotl %2,%1,%0")
-
-;This insn is probably slower than a multiply and an add.
-;(define_insn ""
-;  [(set (match_operand:SI 0 "general_operand" "=g")
-;	(mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
-;			  (match_operand:SI 2 "general_operand" "g"))
-;		 (match_operand:SI 3 "general_operand" "g")))]
-;  ""
-;  "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
-
-;; Special cases of bit-field insns which we should
-;; recognize in preference to the general case.
-;; These handle aligned 8-bit and 16-bit fields,
-;; which can usually be done with move instructions.
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
-			 (match_operand:QI 1 "const_int_operand" "n")
-			 (match_operand:SI 2 "const_int_operand" "n"))
-	(match_operand:SI 3 "general_operand" "g"))]
-   "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
-   && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
-   && (GET_CODE (operands[0]) == REG
-       || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
-  "*
-{
-  if (REG_P (operands[0]))
-    {
-      if (INTVAL (operands[2]) != 0)
-	return \"insv %3,%2,%1,%0\";
-    }
-  else
-    operands[0]
-      = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
-
-  CC_STATUS_INIT;
-  if (INTVAL (operands[1]) == 8)
-    return \"movb %3,%0\";
-  return \"movw %3,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=&g")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
-			 (match_operand:QI 2 "const_int_operand" "n")
-			 (match_operand:SI 3 "const_int_operand" "n")))]
-  "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
-   && (GET_CODE (operands[1]) == REG
-       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
-  "*
-{
-  if (REG_P (operands[1]))
-    {
-      if (INTVAL (operands[3]) != 0)
-	return \"extzv %3,%2,%1,%0\";
-    }
-  else
-    operands[1]
-      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
-
-  if (INTVAL (operands[2]) == 8)
-    return \"movzbl %1,%0\";
-  return \"movzwl %1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
-			 (match_operand:QI 2 "const_int_operand" "n")
-			 (match_operand:SI 3 "const_int_operand" "n")))]
-  "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
-   && (GET_CODE (operands[1]) == REG
-       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
-  "*
-{
-  if (REG_P (operands[1]))
-    {
-      if (INTVAL (operands[3]) != 0)
-	return \"extv %3,%2,%1,%0\";
-    }
-  else
-    operands[1]
-      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
-
-  if (INTVAL (operands[2]) == 8)
-    return \"cvtbl %1,%0\";
-  return \"cvtwl %1,%0\";
-}")
-
-;; Register-only SImode cases of bit-field insns.
-
-(define_insn ""
-  [(set (cc0)
-	(compare
-	 (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
-			  (match_operand:QI 1 "general_operand" "g")
-			  (match_operand:SI 2 "general_operand" "g"))
-	 (match_operand:SI 3 "general_operand" "g")))]
-  ""
-  "cmpv %2,%1,%0,%3")
-
-(define_insn ""
-  [(set (cc0)
-	(compare
-	 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
-			  (match_operand:QI 1 "general_operand" "g")
-			  (match_operand:SI 2 "general_operand" "g"))
-	 (match_operand:SI 3 "general_operand" "g")))]
-  ""
-  "cmpzv %2,%1,%0,%3")
-
-;; When the field position and size are constant and the destination
-;; is a register, extv and extzv are much slower than a rotate followed
-;; by a bicl or sign extension.  Because we might end up choosing ext[z]v
-;; anyway, we can't allow immediate values for the primary source operand.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
-			 (match_operand:QI 2 "general_operand" "g")
-			 (match_operand:SI 3 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
-      || GET_CODE (operands[0]) != REG
-      || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
-    return \"extv %3,%2,%1,%0\";
-  if (INTVAL (operands[2]) == 8)
-    return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
-  return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
-			 (match_operand:QI 2 "general_operand" "g")
-			 (match_operand:SI 3 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
-      || GET_CODE (operands[0]) != REG)
-    return \"extzv %3,%2,%1,%0\";
-  if (INTVAL (operands[2]) == 8)
-    return \"rotl %R3,%1,%0\;movzbl %0,%0\";
-  if (INTVAL (operands[2]) == 16)
-    return \"rotl %R3,%1,%0\;movzwl %0,%0\";
-  if (INTVAL (operands[3]) & 31)
-    return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
-  if (rtx_equal_p (operands[0], operands[1]))
-    return \"bicl2 %M2,%0\";
-  return \"bicl3 %M2,%1,%0\";
-}")
-
-;; Non-register cases.
-;; nonimmediate_operand is used to make sure that mode-ambiguous cases
-;; don't match these (and therefore match the cases above instead).
-
-(define_insn ""
-  [(set (cc0)
-	(compare
-	 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
-			  (match_operand:QI 1 "general_operand" "g")
-			  (match_operand:SI 2 "general_operand" "g"))
-	 (match_operand:SI 3 "general_operand" "g")))]
-  ""
-  "cmpv %2,%1,%0,%3")
-
-(define_insn ""
-  [(set (cc0)
-	(compare
-	 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
-			  (match_operand:QI 1 "general_operand" "g")
-			  (match_operand:SI 2 "general_operand" "g"))
-	 (match_operand:SI 3 "general_operand" "g")))]
-  ""
-  "cmpzv %2,%1,%0,%3")
-
-(define_insn "extv"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
-			 (match_operand:QI 2 "general_operand" "g")
-			 (match_operand:SI 3 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
-      || GET_CODE (operands[3]) != CONST_INT
-      || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
-      || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
-      || side_effects_p (operands[1])
-      || (GET_CODE (operands[1]) == MEM
-	  && mode_dependent_address_p (XEXP (operands[1], 0))))
-    return \"extv %3,%2,%1,%0\";
-  if (INTVAL (operands[2]) == 8)
-    return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
-  return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
-}")
-
-(define_expand "extzv"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(zero_extract:SI (match_operand:SI 1 "general_operand" "")
-			 (match_operand:QI 2 "general_operand" "")
-			 (match_operand:SI 3 "general_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
-			 (match_operand:QI 2 "general_operand" "g")
-			 (match_operand:SI 3 "general_operand" "g")))]
-  ""
-  "*
-{
-  if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
-      || GET_CODE (operands[3]) != CONST_INT
-      || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
-      || side_effects_p (operands[1])
-      || (GET_CODE (operands[1]) == MEM
-	  && mode_dependent_address_p (XEXP (operands[1], 0))))
-    return \"extzv %3,%2,%1,%0\";
-  if (INTVAL (operands[2]) == 8)
-    return \"rotl %R3,%1,%0\;movzbl %0,%0\";
-  if (INTVAL (operands[2]) == 16)
-    return \"rotl %R3,%1,%0\;movzwl %0,%0\";
-  return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
-}")
-
-(define_expand "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
-			 (match_operand:QI 1 "general_operand" "")
-			 (match_operand:SI 2 "general_operand" ""))
-	(match_operand:SI 3 "general_operand" ""))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
-			 (match_operand:QI 1 "general_operand" "g")
-			 (match_operand:SI 2 "general_operand" "g"))
-	(match_operand:SI 3 "general_operand" "g"))]
-  ""
-  "insv %3,%2,%1,%0")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-			 (match_operand:QI 1 "general_operand" "g")
-			 (match_operand:SI 2 "general_operand" "g"))
-	(match_operand:SI 3 "general_operand" "g"))]
-  ""
-  "insv %3,%2,%1,%0")
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "jbr %l0")
-
-(define_insn "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jeql %l0")
-
-(define_insn "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jneq %l0")
-
-(define_insn "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jgtr %l0")
-
-(define_insn "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jgtru %l0")
-
-(define_insn "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jlss %l0")
-
-(define_insn "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jlssu %l0")
-
-(define_insn "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jgeq %l0")
-
-(define_insn "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jgequ %l0")
-
-(define_insn "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jleq %l0")
-
-(define_insn "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			   (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "jlequ %l0")
-
-;; Recognize reversed jumps.
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
-				      [(cc0)
-				       (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 1 "" ""))))]
-  ""
-  "j%C0 %l1") ; %C0 negates condition
-
-;; Recognize jbs, jlbs, jbc and jlbc instructions.  Note that the operand
-;; of jlbs and jlbc insns are SImode in the hardware.  However, if it is
-;; memory, we use QImode in the insn.  So we can't use those instructions
-;; for mode-dependent addresses.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
-			      (const_int 1)
-			      (match_operand:SI 1 "general_operand" "I,g"))
-	     (const_int 0))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))]
-  ""
-  "@
-   jlbs %0,%l2
-   jbs %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
-			      (const_int 1)
-			      (match_operand:SI 1 "general_operand" "I,g"))
-	     (const_int 0))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))]
-  ""
-  "@
-   jlbc %0,%l2
-   jbc %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
-			      (const_int 1)
-			      (match_operand:SI 1 "general_operand" "I,g"))
-	     (const_int 0))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))]
-  ""
-  "@
-   jlbs %0,%l2
-   jbs %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
-			      (const_int 1)
-			      (match_operand:SI 1 "general_operand" "I,g"))
-	     (const_int 0))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))]
-  ""
-  "@
-   jlbc %0,%l2
-   jbc %1,%0,%l2")
-
-;; Subtract-and-jump and Add-and-jump insns.
-;; These are not used when output is for the Unix assembler
-;; because it does not know how to modify them to reach far.
-
-;; Normal sob insns.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (gt (plus:SI (match_operand:SI 0 "general_operand" "+g")
-		      (const_int -1))
-	     (const_int 0))
-	 (label_ref (match_operand 1 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  "!TARGET_UNIX_ASM"
-  "jsobgtr %0,%l1")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")
-		      (const_int -1))
-	     (const_int 0))
-	 (label_ref (match_operand 1 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  "!TARGET_UNIX_ASM"
-  "jsobgeq %0,%l1")
-
-;; Normal aob insns.  Define a version for when operands[1] is a constant.
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (lt (plus:SI (match_operand:SI 0 "general_operand" "+g")
-		      (const_int 1))
-	     (match_operand:SI 1 "general_operand" "g"))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int 1)))]
-  "!TARGET_UNIX_ASM"
-  "jaoblss %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (lt (match_operand:SI 0 "general_operand" "+g")
-	     (match_operand:SI 1 "general_operand" "g"))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int 1)))]
-  "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
-  "jaoblss %P1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (le (plus:SI (match_operand:SI 0 "general_operand" "+g")
-		      (const_int 1))
-	     (match_operand:SI 1 "general_operand" "g"))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int 1)))]
-  "!TARGET_UNIX_ASM"
-  "jaobleq %1,%0,%l2")
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (le (match_operand:SI 0 "general_operand" "+g")
-	     (match_operand:SI 1 "general_operand" "g"))
-	 (label_ref (match_operand 2 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int 1)))]
-  "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
-  "jaobleq %P1,%0,%l2")
-
-;; Something like a sob insn, but compares against -1.
-;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (match_operand:SI 0 "general_operand" "g")
-	     (const_int 0))
-	 (label_ref (match_operand 1 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0)
-		 (const_int -1)))]
-  ""
-  "decl %0\;jgequ %l1")
-
-;; Note that operand 1 is total size of args, in bytes,
-;; and what the call insn wants is the number of words.
-;; It is used in the call instruction as a byte, but in the addl2 as
-;; a word.  Since the only time we actually use it in the call instruction
-;; is when it is a constant, SImode (for addl2) is the proper mode.
-(define_insn "call_pop"
-  [(call (match_operand:QI 0 "memory_operand" "m")
-	 (match_operand:SI 1 "const_int_operand" "n"))
-   (set (reg:SI 14) (plus:SI (reg:SI 14)
-			     (match_operand:SI 3 "immediate_operand" "i")))]
-  ""
-  "*
-  if (INTVAL (operands[1]) > 255 * 4)
-    /* Vax `calls' really uses only one byte of #args, so pop explicitly.  */
-    return \"calls $0,%0\;addl2 %1,sp\";
-  operands[1] = GEN_INT ((INTVAL (operands[1]) + 3)/ 4);
-  return \"calls %1,%0\";
-")
-
-(define_insn "call_value_pop"
-  [(set (match_operand 0 "" "=g")
-	(call (match_operand:QI 1 "memory_operand" "m")
-	      (match_operand:SI 2 "const_int_operand" "n")))
-   (set (reg:SI 14) (plus:SI (reg:SI 14)
-			     (match_operand:SI 4 "immediate_operand" "i")))]
-  ""
-  "*
-  if (INTVAL (operands[2]) > 255 * 4)
-    /* Vax `calls' really uses only one byte of #args, so pop explicitly.  */
-    return \"calls $0,%1\;addl2 %2,sp\";
-  operands[2] = GEN_INT ((INTVAL (operands[2]) + 3)/ 4);
-  return \"calls %2,%1\";
-")
-
-;; Define another set of these for the case of functions with no
-;; operands.  In that case, combine may simplify the adjustment of sp.
-(define_insn ""
-  [(call (match_operand:QI 0 "memory_operand" "m")
-	 (match_operand:SI 1 "const_int_operand" "n"))
-   (set (reg:SI 14) (reg:SI 14))]
-  ""
-  "*
-  if (INTVAL (operands[1]) > 255 * 4)
-    /* Vax `calls' really uses only one byte of #args, so pop explicitly.  */
-    return \"calls $0,%0\;addl2 %1,sp\";
-  operands[1] = GEN_INT ((INTVAL (operands[1]) + 3)/ 4);
-  return \"calls %1,%0\";
-")
-
-(define_insn ""
-  [(set (match_operand 0 "" "=g")
-	(call (match_operand:QI 1 "memory_operand" "m")
-	      (match_operand:SI 2 "const_int_operand" "n")))
-   (set (reg:SI 14) (reg:SI 14))]
-  ""
-  "*
-  if (INTVAL (operands[2]) > 255 * 4)
-    /* Vax `calls' really uses only one byte of #args, so pop explicitly.  */
-    return \"calls $0,%1\;addl2 %2,sp\";
-  operands[2] = GEN_INT ((INTVAL (operands[2]) + 3)/ 4);
-  return \"calls %2,%1\";
-")
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-                  (const_int 0))
-            (match_operand 1 "" "")
-            (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
-;; all of memory.  This blocks insns from being moved across this point.
-
-(define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  "")
-
-(define_insn "return"
-  [(return)]
-  ""
-  "ret")
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "nop")
-
-;; This had a wider constraint once, and it had trouble.
-;; If you are tempted to try `g', please don't--it's not worth
-;; the risk we will reopen the same bug.
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "general_operand" "r"))]
-  ""
-  "jmp (%0)")
-
-;; This is here to accept 5 arguments (as passed by expand_end_case)
-;; and pass the first 4 along to the casesi1 pattern that really does the work.
-(define_expand "casesi"
-  [(set (pc)
-	(if_then_else (leu (minus:SI (match_operand:SI 0 "general_operand" "g")
-				     (match_operand:SI 1 "general_operand" "g"))
-			   (match_operand:SI 2 "general_operand" "g"))
-		      (plus:SI (sign_extend:SI
-				(mem:HI
-				 (plus:SI (pc)
-					  (mult:SI (minus:SI (match_dup 0)
-							     (match_dup 1))
-						   (const_int 2)))))
-			       (label_ref:SI (match_operand 3 "" "")))
-		      (pc)))
-   (match_operand 4 "" "")]
-  ""
-  "
-  emit_insn (gen_casesi1 (operands[0], operands[1], operands[2], operands[3]));
-  DONE;
-")
-
-(define_insn "casesi1"
-  [(set (pc)
-	(if_then_else (leu (minus:SI (match_operand:SI 0 "general_operand" "g")
-				     (match_operand:SI 1 "general_operand" "g"))
-			   (match_operand:SI 2 "general_operand" "g"))
-		      (plus:SI (sign_extend:SI
-				(mem:HI
-				 (plus:SI (pc)
-					  (mult:SI (minus:SI (match_dup 0)
-							     (match_dup 1))
-						   (const_int 2)))))
-			       (label_ref:SI (match_operand 3 "" "")))
-		      (pc)))]
-  ""
-  "casel %0,%1,%2")
-
-;; This used to arise from the preceding by simplification
-;; if operand 1 is zero.  Perhaps it is no longer necessary.
-(define_insn ""
-  [(set (pc)
-	(if_then_else (leu (match_operand:SI 0 "general_operand" "g")
-			   (match_operand:SI 1 "general_operand" "g"))
-		      (plus:SI (sign_extend:SI
-				(mem:HI
-				 (plus:SI (pc)
-					  (mult:SI (minus:SI (match_dup 0)
-							     (const_int 0))
-						   (const_int 2)))))
-			       (label_ref:SI (match_operand 3 "" "")))
-		      (pc)))]
-  ""
-  "casel %0,$0,%1")
-
-;;- load or push effective address 
-;; These come after the move and add/sub patterns
-;; because we don't want pushl $1 turned into pushad 1.
-;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
-
-;; It does not work to use constraints to distinguish pushes from moves,
-;; because < matches any autodecrement, not just a push.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operand:QI 1 "address_operand" "p"))]
-  ""
-  "*
-{
-  if (push_operand (operands[0], SImode))
-    return \"pushab %a1\";
-  else
-    return \"movab %a1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operand:HI 1 "address_operand" "p"))]
-  ""
-  "*
-{
-  if (push_operand (operands[0], SImode))
-    return \"pushaw %a1\";
-  else
-    return \"movaw %a1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operand:SI 1 "address_operand" "p"))]
-  ""
-  "*
-{
-  if (push_operand (operands[0], SImode))
-    return \"pushal %a1\";
-  else
-    return \"moval %a1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operand:DI 1 "address_operand" "p"))]
-  ""
-  "*
-{
-  if (push_operand (operands[0], SImode))
-    return \"pushaq %a1\";
-  else
-    return \"movaq %a1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operand:SF 1 "address_operand" "p"))]
-  ""
-  "*
-{
-  if (push_operand (operands[0], SImode))
-    return \"pushaf %a1\";
-  else
-    return \"movaf %a1,%0\";
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(match_operand:DF 1 "address_operand" "p"))]
-  ""
-  "*
-{
-  if (push_operand (operands[0], SImode))
-    return \"pushad %a1\";
-  else
-    return \"movad %a1,%0\";
-}")
-
-;; These used to be peepholes, but it is more straightforward to do them
-;; as single insns.  However, we must force the output to be a register
-;; if it is not an offsettable address so that we know that we can assign
-;; to it twice. 
-
-;; If we had a good way of evaluating the relative costs, these could be
-;; machine-independent.
-
-;; Optimize   extzv ...,z;    andl2 ...,z
-;; or	      ashl ...,z;     andl2 ...,z
-;; with other operands constant.  This is what the combiner converts the
-;; above sequences to before attempting to recognize the new insn.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=ro")
-	(and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
-			     (match_operand:QI 2 "const_int_operand" "n"))
-		(match_operand:SI 3 "const_int_operand" "n")))]
-  "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
-  "*
-{
-  unsigned long mask1 = INTVAL (operands[3]);
-  unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
-
-  if ((mask1 & mask2) != mask1)
-    operands[3] = GEN_INT (mask1 & mask2);
-
-  return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
-}")
-
-;; left-shift and mask
-;; The only case where `ashl' is better is if the mask only turns off
-;; bits that the ashl would anyways, in which case it should have been
-;; optimized away.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "general_operand" "=ro")
-	(and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g")
-			   (match_operand:QI 2 "const_int_operand" "n"))
-		(match_operand:SI 3 "const_int_operand" "n")))]
-  ""
-  "*
-{
-  operands[3] = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
-  return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
-}")
diff --git a/gcc/config/vax/vaxv.h b/gcc/config/vax/vaxv.h
deleted file mode 100755
index 57dff40..0000000
--- a/gcc/config/vax/vaxv.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Definitions of target machine for GNU compiler.  Vax sysV version.
-   Copyright (C) 1988, 1993, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* Cope with these under SysV */
-
-#define SCCS_DIRECTIVE
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dvax -Dunix -Asystem(unix) -Asystem(svr3) -Acpu(vax) -Amachine(vax)"
-
-/* Output #ident as a .ident.  */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-
-#undef DBX_DEBUGGING_INFO
-#define SDB_DEBUGGING_INFO
-
-#undef LIB_SPEC
-
-/* The .file command should always begin the output.  */
-#undef ASM_FILE_START
-#define ASM_FILE_START(FILE) \
-output_file_directive ((FILE), main_input_filename)
-
-#undef ASM_OUTPUT_ALIGN
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
-  fprintf(FILE, "\t.align %d\n", 1 << (LOG))
-
-#undef ASM_OUTPUT_LOCAL
-#define ASM_OUTPUT_LOCAL(FILE,NAME,SIZE,ROUNDED)	\
-( data_section (),					\
-  assemble_name ((FILE), (NAME)),			\
-  fprintf ((FILE), ":\n\t.space %u\n", (ROUNDED)))
-
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)			\
-do {							\
-  unsigned char *s;					\
-  int i;						\
-  for (i = 0, s = (PTR); i < (LEN); s++, i++)		\
-    {							\
-      if ((i % 8) == 0)					\
-	fputs ("\n\t.byte\t", (FILE));			\
-      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
-    }							\
-  fputs ("\n", (FILE));					\
-} while (0)
-
-#undef ASM_OUTPUT_DOUBLE
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", dstr);	\
-     fprintf (FILE, "\t.double 0d%s\n", dstr);		\
-   } while (0)
diff --git a/gcc/config/vax/vms.h b/gcc/config/vax/vms.h
deleted file mode 100755
index 35c1665..0000000
--- a/gcc/config/vax/vms.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/* Output variables, constants and external declarations, for GNU compiler.
-   Copyright (C) 1988, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define VMS_TARGET
-
-/* This enables certain macros in vax.h, which will make an indirect
-   reference to an external symbol an invalid address.  This needs to be
-   defined before we include vax.h, since it determines which macros
-   are used for GO_IF_*.  */
-
-#define NO_EXTERNAL_INDIRECT_ADDRESS
-
-#include "vax/vax.h"
-
-#undef LIB_SPEC
-#undef CPP_PREDEFINES
-#undef TARGET_NAME
-#undef TARGET_DEFAULT
-#undef CALL_USED_REGISTERS
-#undef MAYBE_VMS_FUNCTION_PROLOGUE
-#undef STARTING_FRAME_OFFSET
-
-/* Predefine this in CPP because VMS limits the size of command options
-   and GNU CPP is not used on VMS except with GNU C.  */
-#define CPP_PREDEFINES \
-"-Dvax -Dvms -DVMS -D__vax__ -D__vms__ -D__VMS__\
- -D__GNUC__=2 -D__GNUC_MINOR__=7 -Asystem(vms) -Acpu(vax) -Amachine(vax)"
-
-/* These match the definitions used in VAXCRTL, the VMS C run-time library */
-
-#define SIZE_TYPE	"unsigned int"
-#define PTRDIFF_TYPE	"int"
-#define WCHAR_TYPE	"unsigned int"
-#define WCHAR_TYPE_SIZE	32	/* in bits */
-
-/* Use memcpy for structure copying, and so forth.  */
-#define TARGET_MEM_FUNCTIONS
-
-/* Strictly speaking, VMS does not use DBX at all, but the interpreter built
-   into gas only speaks straight DBX.  */
-
-#define DEFAULT_GDB_EXTENSIONS 0
-
-#define TARGET_DEFAULT 1
-#define TARGET_NAME "vax/vms"
-
-/* The structure return address arrives as an "argument" on VMS.  */
-#undef STRUCT_VALUE_REGNUM
-#define STRUCT_VALUE 0
-#undef PCC_STATIC_STRUCT_RETURN
-
-#define CALL_USED_REGISTERS {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
-
-/* The run-time library routine VAXC$ESTABLISH (necessary when mixing
-   VMS exception handling and setjmp/longjmp in the same program) requires
-   that a hidden automatic variable at the top of the stack be reserved
-   for its use.  We accomplish this by simply adding 4 bytes to the local
-   stack for all functions, and making sure that normal local variables
-   are 4 bytes lower on the stack then they would otherwise have been.  */
-
-#define STARTING_FRAME_OFFSET -4
-
-#define __MAIN_NAME " main("
-/*
- * The MAYBE_VMS_FUNCTION_PROLOGUE macro works for both gcc and g++.  It
- * first checks to see if the current routine is "main", which will only
- * happen for GCC, and add the jsb if it is.  If is not the case then try and 
- * see if __MAIN_NAME is part of current_function_name, which will only happen
- * if we are running g++, and add the jsb if it is.  In gcc there should never
- * be a paren in the function name, and in g++ there is always a "(" in the
- * function name, thus there should never be any confusion.
- *
- * Adjusting the stack pointer by 4 before calling C$MAIN_ARGS is required
- * when linking with the VMS POSIX version of the C run-time library; using
- * `subl2 $4,r0' is adequate but we use `clrl -(sp)' instead.  The extra 4
- * bytes could be removed after the call because STARTING_FRAME_OFFSET's
- * setting of -4 will end up adding them right back again, but don't bother.
- */
-#define MAYBE_VMS_FUNCTION_PROLOGUE(FILE)	\
-{ extern char *current_function_name;		\
-  char *p = current_function_name;		\
-  int is_main = strcmp ("main", p) == 0;	\
-  while (!is_main && *p != '\0')		\
-    {						\
-      if (*p == *__MAIN_NAME			\
-	  && strncmp (p, __MAIN_NAME, sizeof __MAIN_NAME - sizeof "") == 0) \
-	is_main = 1;				\
-      else					\
-	p++;					\
-    }						\
-  if (is_main)					\
-    fprintf (FILE, "\t%s\n\t%s\n", "clrl -(sp)", "jsb _C$MAIN_ARGS");	\
-}
-
-/* This macro definition sets up a default value for `main' to return.  */
-#define DEFAULT_MAIN_RETURN  c_expand_return (integer_one_node)
-
-/* This makes use of a hook in varasm.c to mark all external variables
-   for us.  We use this to make sure that external variables are correctly
-   addressed.  Under VMS there is some brain damage in the linker that requires
-   us to do this.  */
-
-#define ENCODE_SECTION_INFO(decl)  				\
-  if (DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)) 		\
-    SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1; 
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#undef ASM_GLOBALIZE_LABEL
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)		\
-  do { fputs (".globl ", FILE);			\
-       assemble_name (FILE, NAME);		\
-       fputs ("\n", FILE);			\
-       vms_check_external (NULL_TREE, NAME, 0); \
-     } while (0)
-
-/* Under VMS we write the actual size of the storage to be allocated even
-   though the symbol is external.  Although it is possible to give external
-   symbols a size of 0 (as unix does), the VMS linker does not make the
-   distinction between a variable definition and an external reference of a
-   variable, and thus the linker will not complain about a missing definition.
-   If we followed the unix example of giving external symbols a size of
-   zero, you tried to link a program where a given variable was externally
-   defined but none of the object modules contained a non-extern definition,
-   the linker would allocate 0 bytes for the variable, and any attempt to
-   use that variable would use the storage allocated to some other variable.
-
-   We must also select either const_section or data_section: this will indicate
-   whether or not the variable will get the readonly bit set.  Since the
-   VMS linker does not distinguish between a variable's definition and an
-   external reference, all usages of a given variable must have the readonly
-   bit set the same way, or the linker will get confused and give warning
-   messages.  */
-
-/* We used to round the size up to a multiple of 4,
-   but that causes linker errors sometimes when the variable was initialized
-   since the size of its definition was not likewise rounded up.  */
-
-/* Note:  the original ASM_OUTPUT_EXTERNAL code has been moved into
-   vms_check_external and vms_flush_pending_externals.  */
-
-#define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME)				\
-{ if (DECL_INITIAL (DECL) == 0 && TREE_CODE (DECL) != FUNCTION_DECL)	\
-    vms_check_external ((DECL), (NAME), 1);				\
-}
-
-/* ASM_OUTPUT_EXTERNAL will have wait until after an initializer is
-   completed in order to switch sections for an external object, so
-   use the DECLARE_OBJECT hooks to manage deferred declarations.  */
-
-/* This is the default action for ASM_DECLARE_OBJECT_NAME, but if it
-   is explicitly defined, then ASM_FINISH_DECLARE_OBJECT will be used.  */
-
-#define ASM_DECLARE_OBJECT_NAME(ASM_OUT_FILE,NAME,DECL)		\
-  ASM_OUTPUT_LABEL ((ASM_OUT_FILE), (NAME))
-
-/* We don't need to do anything special to finish the current object, but it
-   should now be safe to output any deferred external global declarations.  */
-
-#define ASM_FINISH_DECLARE_OBJECT(FILE,DECL,TOPLVL,ATEND)		\
-  vms_flush_pending_externals(FILE)
-
-/* Anything still pending must be flushed at the very end.  */
-
-#define ASM_FILE_END(STREAM)						\
-  vms_flush_pending_externals(STREAM)
-
-/* Here we redefine ASM_OUTPUT_COMMON to select the data_section or the
-   const_section before writing the ".const" assembler directive.
-   If we were specifying a size of zero for external variables, we would
-   not have to select a section, since the assembler can assume that
-   when the size > 0, the storage is for a non-external, uninitialized
-   variable (for which a "const" declaration would be senseless),
-   and the assembler can make the storage read/write.
-
-   Since the ".const" directive specifies the actual size of the storage used
-   for both external and non-external variables, the assembler cannot
-   make this assumption, and thus it has no way of deciding if storage should
-   be read/write or read-only.  To resolve this, we give the assembler some
-   assistance, in the form of a ".const" or a ".data" directive.
-
-   Under GCC 1.40, external variables were declared with a size of zero.
-   The GNU assembler, GAS, will recognize the "-2" switch when built for VMS;
-   when compiling programs with GCC 2.n this switch should be used or the
-   assembler will not give the read-only attribute to external constants.
-   Failure to use this switch will result in linker warning messages about
-   mismatched psect attributes.  */
-
-#undef ASM_OUTPUT_COMMON
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)		\
-( ((TREE_READONLY (decl) && ! TREE_THIS_VOLATILE (decl))	\
-   ? (const_section (), 0) : (data_section (), 0)),		\
-  fputs (".comm ", (FILE)),					\
-  assemble_name ((FILE), (NAME)),				\
-  fprintf ((FILE), ",%u\n", (SIZE)))
-
-/* We define this to prevent the name mangler from putting dollar signs into
-   function names.  This isn't really needed, but it has been here for
-   some time and  removing it would cause the object files generated by the
-   compiler to be incompatible with the object files from a compiler that
-   had this defined.  Since it does no harm, we leave it in.  */
-
-#define NO_DOLLAR_IN_LABEL
-
-/* Add a "const" section.  This is viewed by the assembler as being nearly
-   the same as the "data" section, with the only difference being that a
-   flag is set for variables declared while in the const section.  This
-   flag is used to determine whether or not the read/write bit should be
-   set in the Psect definition.  */
-
-#define EXTRA_SECTIONS in_const
-
-#define EXTRA_SECTION_FUNCTIONS				\
-void							\
-const_section ()					\
-{							\
-  if (in_section != in_const) {				\
-    fprintf(asm_out_file,".const\n");			\
-    in_section = in_const;				\
-  }							\
-}
-
-/* This macro contains the logic to decide which section a variable
-   should be stored in.  Static constant variables go in the text_section,
-   non-const variables go in the data_section, and non-static const
-   variables go in the const_section.
-
-   Since this macro is used in a number of places, we must also be able
-   to decide where to place string constants.  */
-
-#define SELECT_SECTION(T,RELOC)						\
-{									\
-  if (TREE_CODE (T) == VAR_DECL)					\
-    {									\
-      if (TREE_READONLY (T) && ! TREE_THIS_VOLATILE (T)			\
-	  && DECL_INITIAL (T)						\
-	  && (DECL_INITIAL (T) == error_mark_node			\
-	      || TREE_CONSTANT (DECL_INITIAL (T))))			\
-	{								\
-	  if (TREE_PUBLIC (T))						\
-	    const_section ();						\
-	  else								\
-	    text_section ();						\
-	}								\
-      else								\
-	data_section ();						\
-    }									\
-  if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c')				\
-    {									\
-      if ((TREE_CODE (T) == STRING_CST && flag_writable_strings))	\
-	data_section ();						\
-      else								\
-	text_section ();						\
-    }									\
-}
-
-/* This is used by a hook in varasm.c to write the assembler directives
-   that are needed to tell the startup code which constructors need to
-   be run.  */
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
-{									\
-  fprintf ((FILE),".globl $$PsectAttributes_NOOVR$$__gxx_init_1\n"); 	\
-  data_section();							\
-  fprintf ((FILE),"$$PsectAttributes_NOOVR$$__gxx_init_1:\n\t.long\t"); \
-  assemble_name ((FILE), (NAME));					\
-  fputc ('\n', (FILE));							\
-}
-
-/* This is used by a hook in varasm.c to write the assembler directives
-   that are needed to tell the startup code which destructors need to
-   be run.  */
-
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)				\
-{									\
-  fprintf ((FILE),".globl $$PsectAttributes_NOOVR$$__gxx_clean_1\n"); 	\
-  data_section();							\
-  fprintf ((FILE),"$$PsectAttributes_NOOVR$$__gxx_clean_1:\n\t.long\t");\
-  assemble_name ((FILE), (NAME));					\
-  fputc ('\n', (FILE));							\
-}
-
-/* True for VMS V4.6 and later.  */
-#define HAVE_ATEXIT
-
-/* The following definitions are used in libgcc2.c with the __main
-   function.  The _SHR symbol is used when the sharable image library
-   for the C++ library is used - this is picked up automatically by the linker
-   and this symbol points to the start of __CTOR_LIST__ from the C++ library.
-   If the C++ library is not used, then __CTOR_LIST_SHR__ occurs just after
-   __CTOR_LIST__, and essentially points to the same list as __CTOR_LIST.  */
-
-#ifdef L__main
-
-#define __CTOR_LIST__ __gxx_init_0
-#define __CTOR_LIST_END__ __gxx_init_2
-
-#define __CTOR_LIST_SHR__ $$PsectAttributes_NOSHR$$__gxx_init_0_shr
-#define __CTOR_LIST_SHR_END__ $$PsectAttributes_NOSHR$$__gxx_init_2_shr
-
-#define DO_GLOBAL_CTORS_BODY						\
-do {									\
-  func_ptr *p;								\
-  extern func_ptr __CTOR_LIST__[1], __CTOR_LIST_END__[1];		\
-  extern func_ptr __CTOR_LIST_SHR__[1], __CTOR_LIST_SHR_END__[1];	\
-  if (&__CTOR_LIST_SHR__[0] != &__CTOR_LIST__[1])			\
-    for (p = __CTOR_LIST_SHR__ + 1; p < __CTOR_LIST_SHR_END__ ; p++ )	\
-      if (*p) (*p) ();							\
-  for (p = __CTOR_LIST__ + 1; p < __CTOR_LIST_END__ ; p++ )		\
-    if (*p) (*p) ();							\
-  do {	/* arrange for `return' from main() to pass through exit() */	\
-      __label__ foo;							\
-      int *callers_caller_fp = (int *) __builtin_frame_address (3);	\
-      register int retval asm ("r0");					\
-      callers_caller_fp[4] = (int) && foo;				\
-      break;		/* out of do-while block */			\
-    foo:								\
-      exit (retval);							\
-  } while (0);								\
-} while (0)
-
-#define __DTOR_LIST__ __gxx_clean_0
-#define __DTOR_LIST_END__ __gxx_clean_2
-
-#define __DTOR_LIST_SHR__ $$PsectAttributes_NOSHR$$__gxx_clean_0_shr
-#define __DTOR_LIST_SHR_END__ $$PsectAttributes_NOSHR$$__gxx_clean_2_shr
-
-#define DO_GLOBAL_DTORS_BODY						\
-do {									\
-  func_ptr *p;								\
-  extern func_ptr __DTOR_LIST__[1], __DTOR_LIST_END__[1];		\
-  extern func_ptr __DTOR_LIST_SHR__[1], __DTOR_LIST_SHR_END__[1];	\
-  for (p = __DTOR_LIST__ + 1; p < __DTOR_LIST_END__ ; p++ )		\
-    if (*p) (*p) ();							\
-  if (&__DTOR_LIST_SHR__[0] != &__DTOR_LIST__[1])			\
-    for (p = __DTOR_LIST_SHR__ + 1; p < __DTOR_LIST_SHR_END__ ; p++ )	\
-      if (*p) (*p) ();							\
-} while (0)
-
-#endif /* L__main */
-
-/* Specify the list of include file directories.  */
-#define INCLUDE_DEFAULTS \
-{									\
-  { "GNU_GXX_INCLUDE:", "G++", 1, 1 },					\
-  { "GNU_CC_INCLUDE:", "GCC", 0, 0 },	/* GNU includes */		\
-  { "SYS$SYSROOT:[SYSLIB.]", 0, 0, 0 }, /* VAX-11 "C" includes */	\
-  { ".", 0, 0, 1 },		/* Make normal VMS filespecs work.  */	\
-  { 0, 0, 0, 0 }							\
-}
diff --git a/gcc/config/vax/x-vax b/gcc/config/vax/x-vax
deleted file mode 100755
index bb58a6a..0000000
--- a/gcc/config/vax/x-vax
+++ /dev/null
@@ -1,3 +0,0 @@
-# If compiling GCC with the Unix assembler, -J will handle a large function.
-# With GAS, it should have no effect.
-X_CPPFLAGS = -J
diff --git a/gcc/config/vax/xm-vax.h b/gcc/config/vax/xm-vax.h
deleted file mode 100755
index d7ef168..0000000
--- a/gcc/config/vax/xm-vax.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Configuration for GNU C-compiler for Vax.
-   Copyright (C) 1987, 1993 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* This machine doesn't use IEEE floats.  */
-#define HOST_FLOAT_FORMAT VAX_FLOAT_FORMAT
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* isinf isn't there, but finite is. */
-#define isinf(x) (!finite(x))
-
diff --git a/gcc/config/vax/xm-vaxv.h b/gcc/config/vax/xm-vaxv.h
deleted file mode 100755
index aef16f0..0000000
--- a/gcc/config/vax/xm-vaxv.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/* Config file for Vax running system V.  */
-
-#define USG
diff --git a/gcc/config/vax/xm-vms.h b/gcc/config/vax/xm-vms.h
deleted file mode 100755
index 5d01aeb..0000000
--- a/gcc/config/vax/xm-vms.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/* Configuration for GNU C-compiler for Vax.
-   Copyright (C) 1987, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* Other configurations get these via autoconfig.  */
-#define STDC_HEADERS 1
-#define HAVE_STDLIB_H 1
-#define HAVE_STRING_H 1
-#ifdef __DECC
-#define HAVE_UNISTD_H 1
-#endif
-
-#if defined(VAXC) || defined(__DECC)
-/* if compiling with VAXC, need to fix problem with <stdio.h>
-   which defines a macro called FILE_TYPE that breaks "tree.h".
-   Fortunately it uses #ifndef to suppress multiple inclusions.
-   Three possible cases:
-	1) <stdio.h> has already been included -- ours will be no-op;
-	2) <stdio.h> will be included after us -- "theirs" will be no-op;
-	3) <stdio.h> isn't needed -- including it here shouldn't hurt.
-   In all three cases, the problem macro will be removed here.  */
-#include <stdio.h>
-#undef FILE_TYPE
-#endif
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_FLOAT_FORMAT VAX_FLOAT_FORMAT
-
-#define SUCCESS_EXIT_CODE 1
-#define FATAL_EXIT_CODE (44 | 0x10000000)  /* Abort, and no DCL message.  */
-
-/* A couple of conditionals for execution machine are controlled here.  */
-#ifndef VMS
-#define VMS
-#endif
-
-#ifndef __GNUC__
-/* not present, at least in VAX-11 C (VMS) v2.2 */
-#define R_OK 4
-#define W_OK 2
-#define X_OK 1
-#define F_OK 0
-#endif
-
-#define GCC_INCLUDE_DIR "///not used with VMS///"	/* nonsense string for now */
-
-/* and define a local equivalent (sort of) for unlink */
-#define unlink remove
-
-/* Used by the preprocessor to limit size of disk I/O chunks.
-   64K - 1 is the maximum supported by VAXCRTL.  Amounts in excess
-   of 35 blocks will bypass the VMS V6.x VIOC [Virtual I/O Cache],
-   so we'll pick a limit of 16K (32 blocks).  */
-#define MAX_READ_LEN	(32 * 512)
-#define MAX_WRITE_LEN	(32 * 512)
-
-/* Under VMS a directory specification can be enclosed either in square
-   brackets or in angle brackets.  Thus we need to check both.  This
-   macro is used to help compare filenames in cp-lex.c.
-
-   We also need to make sure that the names are all lower case, because
-   we must be able to compare filenames to determine if a file implements
-   a class.  */
-
-#define FILE_NAME_NONDIRECTORY(C)				\
-({								\
-   char * pnt_ = (C), * pnt1_;					\
-   pnt1_ = pnt_ - 1;						\
-   while (*++pnt1_)						\
-     if ((*pnt1_ >= 'A' && *pnt1_ <= 'Z')) *pnt1_ |= 0x20;	\
-   pnt1_ = rindex (pnt_, ']'); 					\
-   pnt1_ = (pnt1_ == 0 ? rindex (pnt_, '>') : pnt1_);		\
-   pnt1_ = (pnt1_ == 0 ? rindex (pnt_, ':') : pnt1_);		\
-   (pnt1_ == 0 ? pnt_ : pnt1_ + 1);				\
- })
-
-/* Macro to generate the name of the cross reference file.  The standard
-   one does not work, since it was written assuming that the conventions
-   of a unix style filesystem will work on the host system.  */
-
-#define XREF_FILE_NAME(BUFF, NAME)	\
-  s = FILE_NAME_NONDIRECTORY (NAME);			\
-  if (s == NAME) sprintf(BUFF, "%s_gxref", NAME);	\
-  else {						\
-    strcpy(BUFF, NAME);					\
-    strcat(BUFF, "_gxref");				\
-  }
-
-/* Macro that is used in cp-xref.c to determine whether a file name is
-   absolute or not.  */
-
-#define FILE_NAME_ABSOLUTE_P(NAME)	\
-	(FILE_NAME_NONDIRECTORY (NAME) != (&NAME[1]))
-
-/* FILE_NAME_JOINER is defined to be the characters that are inserted between 
-   a directory name and a filename in order to make an absolute file
-   specification.  Under VMS the directory specification contains all of the
-   required characters, so we define this to be a null string.  */
-
-#define FILE_NAME_JOINER ""
-
-/* vprintf() has been available since VMS V4.6.  */
-
-#define HAVE_VPRINTF
-
-#if defined(VAXC) || defined(__DECC)
-
-/* Customizations/kludges for building with DEC's VAX C compiler
-   rather than GCC.  */
-
-#define NO_SYS_PARAMS_H		/* don't have <sys/params.h> */
-#define USE_C_ALLOCA		/* using alloca.c */
-#define QSORT_WORKAROUND	/* do not use VAXCRTL's qsort */
-
-/* use ANSI/SYSV style byte manipulation routines instead of BSD ones */
-/* rename all too-long external symbol names to avoid warnings */
-#define check_for_full_enumeration_handling	check_for_full_enum_handling
-#define current_function_contains_functions	curfunc_contains_functions
-#define current_function_epilogue_delay_list	curfunc_epilogue_delay_list
-#define current_function_has_nonlocal_goto	curfunc_has_nonlocal_goto
-#define current_function_has_nonlocal_label	curfunc_has_nonlocal_label
-#define current_function_internal_arg_pointer	curfunc_internal_arg_pointer
-#define current_function_outgoing_args_size	curfunc_outgoing_args_size
-#define current_function_pretend_args_size	curfunc_pretend_args_size
-#define current_function_returns_pcc_struct	curfunc_returns_pcc_struct
-#define current_function_returns_pointer	curfunc_returns_pointer
-#define current_function_uses_const_pool	curfunc_uses_const_pool
-#define current_function_uses_pic_offset_table	curfunc_uses_pic_offset_table
-#define dbxout_resume_previous_source_file	dbxout_resume_previous_src_file
-#define expand_builtin_extract_return_addr	expand_builtin_extract_ret_addr
-#define expand_builtin_set_return_addr_reg	expand_builtin_set_ret_addr_reg
-#define expand_start_loop_continue_elsewhere	expnd_start_loop_cont_elsewhere
-#define flag_schedule_insns_after_reload	flag_sched_insns_after_reload
-#define get_dynamic_handler_chain_libfunc	get_dynamic_hndlr_chain_libfunc
-#define lookup_name_current_level_global	lookup_name_current_level_gbl
-#define maybe_building_objc_message_expr	maybe_building_objc_msg_expr
-#define mesg_implicit_function_declaration	mesg_implicit_func_declaration
-#define output_deferred_addressed_constants	output_deferred_addr_constants
-#define protect_cleanup_actions_with_terminate  protect_cleanup_act_w_terminate
-#define reg_overlap_mentioned_for_reload_p	reg_overlap_mtnd_for_reload_p
-#define reposition_prologue_and_epilogue_notes	repos_prolog_and_epilog_notes
-#define rtx_equal_function_value_matters	rtx_equal_func_value_matters
-#define set_new_first_and_last_label_num	set_new_first_and_last_lbl_num
-#define thread_prologue_and_epilogue_insns	thread_prolog_and_epilog_insns
-#endif
-
-/* We need to avoid the library qsort routine, due to a serious bug
-   in VAXCRTL.  (Sorting anything with size that's not a multiple of 4
-   after having previously sorted something that was a multiple of 4
-   can produce wrong results and result in data corruption.)  We'll
-   use our own substitute (in vax.c) instead.  */
-/* #define QSORT_WORKAROUND */
-#ifdef QSORT_WORKAROUND
-#define qsort not_qsort
-#endif
-
-#ifdef __DECC
-/* DECC$SHR doesn't have VAXCRTL's bugs.  */
-#undef QSORT_WORKAROUND
-#undef qsort
-/* Avoid a lot of informational level diagnostics about implicitly
-   declared functions.  */
-#include <stdlib.h>
-#include <string.h>
-/* this is for genopinit.c */
- #pragma message disable (undefescap)
-#endif
-
-#if defined(USE_C_ALLOCA) && !defined(alloca)
-/* Declare alloca() using similar logic to that in alloca.c.  */
-#ifdef __STDC__
-extern void *alloca(unsigned);
-#else
-extern char *alloca();
-#endif
-#endif
diff --git a/gcc/config/we32k/we32k.c b/gcc/config/we32k/we32k.c
deleted file mode 100755
index 0c02686..0000000
--- a/gcc/config/we32k/we32k.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* Subroutines for insn-output.c for AT&T we32000 Family.
-   Contributed by John Wehle (john@feith1.uucp)
-   Copyright (C) 1991, 1992, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-#include "config.h"
-#include <stdio.h>
-#include "rtl.h"
-#include "real.h"
-
-
-void
-output_move_double (operands)
-     rtx *operands;
-{
-  rtx lsw_operands[2];
-  rtx lsw_sreg = NULL;
-  rtx msw_dreg = NULL;
-
-  if (GET_CODE (operands[0]) == REG) 
-    {
-      lsw_operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-      msw_dreg = operands[0];
-    }
-  else if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
-    lsw_operands[0] = adj_offsettable_operand (operands[0], 4);
-  else
-    abort ();
-
-  if (GET_CODE (operands[1]) == REG) 
-    {
-      lsw_operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-      lsw_sreg = lsw_operands[1];
-    }
-  else if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1])) 
-    {
-      lsw_operands[1] = adj_offsettable_operand (operands[1], 4);
-      lsw_sreg = operands[1];
-      for ( ; ; ) 
-	{
-	  if (REG_P (lsw_sreg))
-	    break;
-	  if (CONSTANT_ADDRESS_P (lsw_sreg)) 
-	    {
-	      lsw_sreg = NULL;
-	      break;
-	    }
-	  if (GET_CODE (lsw_sreg) == MEM) 
-	    {
-	      lsw_sreg = XEXP (lsw_sreg, 0);
-	      continue;
-	    }
-	  if (GET_CODE (lsw_sreg) == PLUS)
-	    {
-	      if (CONSTANT_ADDRESS_P (XEXP (lsw_sreg, 1))) 
-		{
-		  lsw_sreg = XEXP (lsw_sreg, 0);
-		  continue;
-		}
-	      else if (CONSTANT_ADDRESS_P (XEXP (lsw_sreg, 0))) 
-		{
-		  lsw_sreg = XEXP (lsw_sreg, 1);
-		  continue;
-		}
-	    }
-	  abort ();
-	}
-    }
-  else if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    {
-      lsw_operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
-      operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
-    }
-  else if (GET_CODE (operands[1]) == CONST_INT)
-    {
-      lsw_operands[1] = operands[1];
-      operands[1] = const0_rtx;
-    }
-  else
-    abort ();
-
-  if (!msw_dreg || !lsw_sreg || REGNO (msw_dreg) != REGNO (lsw_sreg)) 
-    {
-      output_asm_insn ("movw %1, %0", operands);
-      output_asm_insn ("movw %1, %0", lsw_operands);
-    }
-  else 
-    {
-      output_asm_insn ("movw %1, %0", lsw_operands);
-      output_asm_insn ("movw %1, %0", operands);
-    }
-}
-
-void
-output_push_double (operands)
-     rtx *operands;
-{
-  rtx lsw_operands[1];
-
-  if (GET_CODE (operands[0]) == REG)
-    lsw_operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  else if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
-    lsw_operands[0] = adj_offsettable_operand (operands[0], 4);
-  else if (GET_CODE (operands[0]) == CONST_DOUBLE)
-    {
-      lsw_operands[0] = GEN_INT (CONST_DOUBLE_HIGH (operands[0]));
-      operands[0] = GEN_INT (CONST_DOUBLE_LOW (operands[0]));
-    }
-  else if (GET_CODE (operands[0]) == CONST_INT)
-    { 
-      lsw_operands[0] = operands[0];
-      operands[0] = const0_rtx;
-    }
-  else
-    abort ();
-
-  output_asm_insn ("pushw %0", operands);
-  output_asm_insn ("pushw %0", lsw_operands);
-}
diff --git a/gcc/config/we32k/we32k.h b/gcc/config/we32k/we32k.h
deleted file mode 100755
index 0859ec1..0000000
--- a/gcc/config/we32k/we32k.h
+++ /dev/null
@@ -1,1048 +0,0 @@
-/* Definitions of target machine for GNU compiler.  AT&T we32000 version.
-   Copyright (C) 1991, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
-   Contributed by John Wehle (john@feith1.uucp)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-Dwe32000 -Du3b2 -Dunix -Asystem(unix) -Acpu(we32000) -Amachine(we32000)"
-
-/* Print subsidiary information on the compiler version in use.  */
-
-#define TARGET_VERSION fprintf (stderr, " (we32000)");
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-
-/* Macros used in the machine description to test the flags.  */
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-
-#define TARGET_SWITCHES  \
-  { { "", TARGET_DEFAULT}}
-
-#define TARGET_DEFAULT 0
-
-
-/* target machine storage layout */
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields. */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
-/* That is true on the we32000.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword is lowest numbered.  */
-/* For we32000 we can decide arbitrarily
-   since there are no machine instructions for them.  */
-#define WORDS_BIG_ENDIAN 1
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a we32000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 32
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 4
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE 32
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 32
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 32
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 32
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 32
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 32
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY 32
-
-/* Define this if move instructions will actually fail to work
-   when given unaligned data.  */
-#define STRICT_ALIGNMENT 1
-
-/* Define number of bits in most basic integer type.
-   (If undefined, default is BITS_PER_WORD).  */
-#define INT_TYPE_SIZE 32
-
-/* Integer bit fields should have the same size and alignment
-   as actual integers */
-#define PCC_BITFIELD_TYPE_MATTERS 1
-
-/* Specify the size_t type.  */
-#define SIZE_TYPE "unsigned int"
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers. */
-#define FIRST_PSEUDO_REGISTER 16
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator. */
-#define FIXED_REGISTERS  \
- {0, 0, 0, 0, 0, 0, 0, 0, \
-  0, 1, 1, 1, 1, 1, 1, 1, }
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-#define CALL_USED_REGISTERS \
- {1, 1, 1, 0, 0, 0, 0, 0, \
-  0, 1, 1, 1, 1, 1, 1, 1, }
-
-/* Make sure everything's fine if we *don't* have a given processor.
-   This assumes that putting a register in fixed_regs will keep the
-   compilers mitt's completely off it.  We don't bother to zero it out
-   of register classes.  */
-/* #define CONDITIONAL_REGISTER_USAGE */
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers. */
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) 0
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* Register used for the program counter */
-#define PC_REGNUM  15
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 12
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 9
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 1
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 10
-
-/* Register in which static-chain is passed to a function.  */
-#define STATIC_CHAIN_REGNUM 8
-
-/* Register in which address to store a structure value
-   is passed to a function.  */
-#define STRUCT_VALUE_REGNUM 2
-
-/* Order in which to allocate registers. */
-#define REG_ALLOC_ORDER  \
- {0, 1, 8, 7, 6, 5, 4, 3}
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-enum reg_class { NO_REGS, GENERAL_REGS,
-  ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES \
- { "NO_REGS", "GENERAL_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS \
-{							\
- 0,			/* NO_REGS */		\
- 0x000017ff,		/* GENERAL_REGS */	\
- 0x0000ffff,		/* ALL_REGS */		\
-}
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO)	\
-  (((REGNO) < 11 || (REGNO) == 12) ? GENERAL_REGS : ALL_REGS)
-
-/* The class value for index registers, and the one for base regs.  */
-
-#define INDEX_REG_CLASS NO_REGS
-#define BASE_REG_CLASS GENERAL_REGS
-
-/* Get reg_class from a letter such as appears in the machine description.
-   We do a trick here to modify the effective constraints on the
-   machine description; we zorch the constraint letters that aren't
-   appropriate for a specific target.  This allows us to guarantee
-   that a specific kind of register will not be used for a given target
-   without fiddling with the register classes above. */
-
-#define REG_CLASS_FROM_LETTER(C) \
-  ((C) == 'r' ? GENERAL_REGS : NO_REGS)
-
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C. */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)  0
-
-/*
- */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  0
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class. */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS)  (CLASS)
-
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-#define CLASS_MAX_NREGS(CLASS, MODE)	\
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-/* #define STACK_GROWS_DOWNWARD */
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-/* #define FRAME_GROWS_DOWNWARD */
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by. */
-#define PUSH_ROUNDING(BYTES) (((BYTES) + 3) & ~3)
-
-/* Offset of first parameter from the argument pointer register value.  */
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Value is 1 if returning from a function call automatically
-   pops the arguments described by the number-of-args field in the call.
-   FUNDECL is the declaration node of the function (as a tree),
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name. */
-
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
-/* On the we32000 the return value is in r0 regardless.  */
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)  \
-  gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-/* On the we32000 the return value is in r0 regardless.  */
-
-#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, 0)
-
-/* 1 if N is a possible register number for a function value.
-   On the we32000, r0 is the only register thus used.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
-
-/* Define this if PCC uses the nonreentrant convention for returning
-   structure and union values.  */
-
-/* #define PCC_STATIC_STRUCT_RETURN */
-
-/* 1 if N is a possible register number for function argument passing.
-   On the we32000, no registers are used in this way.  */
-
-#define FUNCTION_ARG_REGNO_P(N) 0
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On the we32k, this is a single integer, which is a number of bytes
-   of arguments scanned so far.  */
-
-#define CUMULATIVE_ARGS int
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-   For a library call, FNTYPE is 0.
-
-   On the we32k, the offset starts at 0.  */
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM) = 0)
-
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be available.)  */
-
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- ((CUM) += ((MODE) != BLKmode			\
-	    ? (GET_MODE_SIZE (MODE) + 3) & ~3	\
-	    : (int_size_in_bytes (TYPE) + 3) & ~3))
-
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
-
-/* On the we32000 all args are pushed */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
-
-/* For an arg passed partly in registers and partly in memory,
-   this is the number of registers used.
-   For args passed entirely in registers or entirely in memory, zero.  */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE)     \
-{ register int nregs_to_save;					\
-  register int regno;						\
-  extern char call_used_regs[];					\
-  nregs_to_save = 0;						\
-  for (regno = 8; regno > 2; regno--)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      nregs_to_save = (9 - regno);				\
-  fprintf (FILE, "\tsave &%d\n", nregs_to_save);  		\
-  if (SIZE)							\
-    fprintf (FILE, "\taddw2 &%d,%%sp\n", ((SIZE) + 3) & ~3);	}
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\tmovw &.LP%d,%%r0\n\tjsb _mcount\n", (LABELNO))
-
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.  */
-
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)  \
-  fprintf (FILE, "\tcmpw .LPBX0,&0\n\tjne .LPI%d\n\tpushw &.LPBX0\n\tcall &1,__bb_init_func\n.LPI%d:\n",  \
-	   LABELNO, LABELNO);
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  */
-
-#define BLOCK_PROFILER(FILE, BLOCKNO)	\
-  fprintf (FILE, "\taddw2 &1,.LPBX2+%d\n", 4 * BLOCKNO)
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 0
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE) \
-{ register int nregs_to_restore;				\
-  register int regno;						\
-  extern char call_used_regs[];					\
-  nregs_to_restore = 0;						\
-  for (regno = 8; regno > 2; regno--)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-       nregs_to_restore = (9 - regno);				\
-  fprintf (FILE, "\tret &%d\n", nregs_to_restore);  		}
-
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved.
-
-   On the we32k, FRAME_POINTER_REQUIRED is always 1, so the definition of this
-   macro doesn't matter.  But it must be defined.  */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0;
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.  */
-
-/* On the we32k, the trampoline contains two instructions:
-     mov #STATIC,%r8
-     jmp #FUNCTION */
-
-#define TRAMPOLINE_TEMPLATE(FILE)					\
-{									\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x844f));				\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
-  ASM_OUTPUT_CHAR (FILE, GEN_INT (0x48));				\
-  ASM_OUTPUT_SHORT (FILE, GEN_INT (0x247f));				\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
-  ASM_OUTPUT_SHORT (FILE, const0_rtx);					\
-}
-
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE 13
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), CXT); \
-  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 9)), FNADDR); \
-}
-
-/* Generate calls to memcpy() and memset() rather
-   than bcopy() and bzero() */
-#define TARGET_MEM_FUNCTIONS
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO)	0
-
-#define REGNO_OK_FOR_BASE_P(REGNO)	\
-  ((REGNO) < 11 || (REGNO) == 12 ||	\
-  (unsigned)reg_renumber[REGNO] < 11 || (unsigned)reg_renumber[REGNO] == 12)
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-
-#define MAX_REGS_PER_ADDRESS 1
-
-/* Recognize any constant value that is a valid address.  */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Nonzero if the constant value X is a legitimate general operand.
-   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
-
-#define LEGITIMATE_CONSTANT_P(X) 1
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X) 0
-
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-  (REGNO(X) < 11 || REGNO(X) == 12 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address. */
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL)			\
-{ register rtx Addr = X;						\
-  if ((MODE) == QImode || (MODE) == HImode ||				\
-    (MODE) == PSImode || (MODE) == SImode || (MODE) == SFmode)		\
-    if (GET_CODE(Addr) == MEM)						\
-      Addr = XEXP(Addr, 0);						\
-  if (CONSTANT_ADDRESS_P(Addr))						\
-    goto LABEL;								\
-  if (REG_P(Addr) && REG_OK_FOR_BASE_P(Addr))				\
-    goto LABEL;								\
-  if (GET_CODE(Addr) == PLUS &&						\
-    ((REG_P(XEXP(Addr, 0)) && REG_OK_FOR_BASE_P(XEXP(Addr, 0)) &&	\
-     CONSTANT_ADDRESS_P(XEXP(Addr, 1))) ||				\
-     (REG_P(XEXP(Addr, 1)) && REG_OK_FOR_BASE_P(XEXP(Addr, 1)) &&	\
-     CONSTANT_ADDRESS_P(XEXP(Addr, 0)))))				\
-    goto LABEL;								\
-}
-
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output. */
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)   { }
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for. */
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)	{ }
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE SImode
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* Max number of bytes we can move from memory to memory
-   in one reasonably fast instruction.  */
-#define MOVE_MAX 4
-
-/* Define this if zero-extension is slow (more than one real instruction).  */
-/* #define SLOW_ZERO_EXTEND */
-
-/* Nonzero if access to memory by bytes is slow and undesirable.  */
-#define SLOW_BYTE_ACCESS 0
-
-/* Define this to be nonzero if shift instructions ignore all but the low-order
-   few bits. */
-#define SHIFT_COUNT_TRUNCATED 1
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE -1
-
-/* When a prototype says `char' or `short', really pass an `int'.  */
-#define PROMOTE_PROTOTYPES
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-#define Pmode SImode
-
-/* A function address in a call instruction
-   is a byte address (for indexing purposes)
-   so give the MEM rtx a byte's mode.  */
-#define FUNCTION_MODE QImode
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.  */
-
-#define CONST_COSTS(RTX,CODE, OUTER_CODE)				\
-  case CONST_INT:							\
-    if (INTVAL (RTX) >= -16 && INTVAL (RTX) <= 63) return 0;		\
-    if (INTVAL (RTX) >= -128 && INTVAL (RTX) <= 127) return 1;		\
-    if (INTVAL (RTX) >= -32768 && INTVAL (RTX) <= 32767) return 2;	\
-  case CONST:								\
-  case LABEL_REF:							\
-  case SYMBOL_REF:							\
-    return 3;								\
-  case CONST_DOUBLE:							\
-    return 5;
-
-/* Tell final.c how to eliminate redundant test instructions.  */
-
-/* Here we define machine-dependent flags and fields in cc_status
-   (see `conditions.h').  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) \
-{								\
-  { CC_STATUS_INIT; }						\
-}
-
-/* Control the assembler format that we output.  */
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-
-#define STARTFILE_SPEC  "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
-
-#define ENDFILE_SPEC "crtn.o%s"
-
-/* The .file command should always begin the output.  */
-
-#define ASM_FILE_START(FILE) output_file_directive ((FILE), main_input_filename)
-
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON "#APP\n"
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF "#NO_APP\n"
-
-/* Output before code.  */
-
-#define TEXT_SECTION_ASM_OP ".text"
-
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP ".data"
-
-/* Read-only data goes in the data section because
-   AT&T's assembler doesn't guarantee the proper alignment
-   of data in the text section even if an align statement
-   is used. */
-
-#define READONLY_DATA_SECTION() data_section()
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES \
-{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",	\
- "r8", "fp", "ap", "psw", "sp", "pcbp", "isp", "pc"	}
-
-/* How to renumber registers for dbx and gdb. */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* Output SDB debugging info in response to the -g option.  */
-
-#define SDB_DEBUGGING_INFO
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do {					\
-    fputs (".globl ", FILE);		\
-    assemble_name (FILE, NAME);		\
-    fputs ("\n", FILE);			\
-  } while (0)
-
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX ""
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, ".%s%d", PREFIX, NUM)
-
-/* This is how to output an internal numbered label which
-   labels a jump table.  */
-
-#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE)	\
-  do {							\
-    ASM_OUTPUT_ALIGN (FILE, 2);				\
-    ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM);	\
-  } while (0)
-
-/* Assembler pseudo to introduce byte constants.  */
-
-#define ASM_BYTE_OP "\t.byte"
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-/* This is how to output an assembler line defining a `float' constant.  */
-
-/* AT&T's assembler can't handle floating constants written as floating.
-   However, when cross-compiling, always use that in case format differs.  */
-
-#ifdef CROSS_COMPILER
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)	\
-  fprintf (FILE, "\t.double 0r%.20g\n", (VALUE))
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)	\
-  fprintf (FILE, "\t.float 0r%.10g\n", (VALUE))
-
-#else
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)	\
-do { union { double d; long l[2];} tem;				\
-     tem.d = (VALUE);						\
-     fprintf (FILE, "\t.word 0x%x, 0x%x\n", tem.l[0], tem.l[1]);\
-   } while (0)
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)	\
-do { union { float f; long l;} tem;				\
-     tem.f = (VALUE);						\
-     fprintf (FILE, "\t.word 0x%x\n", tem.l);			\
-   } while (0)
-
-#endif /* not CROSS_COMPILER */
-
-/* This is how to output an assembler line defining an `int' constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\t.word "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\t.half "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
-( fprintf (FILE, "\t.byte "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
-
-#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)  \
-do {							\
-  unsigned char *s;					\
-  int i;						\
-  for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++)	\
-    {							\
-      if ((i % 8) == 0)					\
-	fprintf ((FILE),"%s\t.byte\t",(i?"\n":""));	\
-      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
-    }							\
-  fputs ("\n", (FILE));					\
-} while (0)
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
-  fprintf (FILE, "\tpushw %s\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO)	\
-  fprintf (FILE, "\tPOPW %s\n", reg_names[REGNO])
-
-/* This is how to output an element of a case-vector that is absolute. */
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t.word .L%d\n", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
-  if ((LOG) != 0)			\
-    fprintf (FILE, "\t.align %d\n", 1 << (LOG))
-
-/* This is how to output an assembler line
-   that says to advance the location counter by SIZE bytes.  */
-
-/* The `space' pseudo in the text segment outputs nop insns rather than 0s,
-   so we must output 0s explicitly in the text segment.  */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  if (in_text_section ())                                           	    \
-    {									    \
-      int i;								    \
-      for (i = 0; i < (SIZE) - 20; i += 20)				    \
-	fprintf (FILE, "\t.byte 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n"); \
-      if (i < (SIZE))							    \
-        {								    \
-	  fprintf (FILE, "\t.byte 0");					    \
-	  i++;								    \
-	  for (; i < (SIZE); i++)					    \
-	    fprintf (FILE, ",0");					    \
-	  fprintf (FILE, "\n");						    \
-	}								    \
-    }									    \
-  else									    \
-    fprintf ((FILE), "\t.set .,.+%u\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)	\
-  do {							\
-    data_section();					\
-    fputs ("\t.comm ", (FILE));				\
-    assemble_name ((FILE), (NAME));			\
-    fprintf ((FILE), ",%u\n", (SIZE));			\
-  } while (0)
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
-  do {							\
-    data_section();					\
-    ASM_OUTPUT_ALIGN ((FILE), 2);			\
-    ASM_OUTPUT_LABEL ((FILE), (NAME));			\
-    fprintf ((FILE), "\t.zero %u\n", (SIZE));		\
-  } while (0)
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-
-/* Output #ident as a .ident.  */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME)
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null. */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) 0
-
-#define PRINT_OPERAND(FILE, X, CODE)  \
-{ int i;								\
-  if (GET_CODE (X) == REG)						\
-    fprintf (FILE, "%%%s", reg_names[REGNO (X)]);			\
-  else if (GET_CODE (X) == MEM)						\
-    output_address (XEXP (X, 0));					\
-  else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode)	\
-         {								\
-         union { double d; long l[2]; } dtem;				\
-         union { float f; long l; } ftem;				\
-									\
-         dtem.l[0] = CONST_DOUBLE_LOW (X);				\
-         dtem.l[1] = CONST_DOUBLE_HIGH (X);				\
-         ftem.f = dtem.d;						\
-         fprintf(FILE, "&0x%lx", ftem.l);				\
-         }								\
-  else { putc ('&', FILE); output_addr_const (FILE, X); }}
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
-{ register rtx Addr = ADDR;						\
-  rtx offset;								\
-  rtx reg;								\
-  if (GET_CODE (Addr) == MEM) {						\
-    putc ('*', FILE);							\
-    Addr = XEXP (Addr, 0);						\
-    if (GET_CODE (Addr) == REG)						\
-      putc ('0', FILE);							\
-    }									\
-  switch (GET_CODE (Addr))						\
-    {									\
-    case REG:								\
-      fprintf (FILE, "(%%%s)", reg_names[REGNO (Addr)]);		\
-      break;								\
-									\
-    case PLUS:								\
-      offset = NULL;							\
-      if (CONSTANT_ADDRESS_P (XEXP (Addr, 0)))				\
-	{								\
-	  offset = XEXP (Addr, 0);					\
-	  Addr = XEXP (Addr, 1);					\
-	}								\
-      else if (CONSTANT_ADDRESS_P (XEXP (Addr, 1)))			\
-	{								\
-	  offset = XEXP (Addr, 1);					\
-	  Addr = XEXP (Addr, 0);					\
-	}								\
-      else								\
-        abort();							\
-      if (REG_P (Addr))							\
-        reg = Addr;							\
-      else								\
-        abort();							\
-      output_addr_const(FILE, offset);					\
-      fprintf(FILE, "(%%%s)", reg_names[REGNO(reg)]);			\
-      break;								\
-									\
-    default:								\
-      if ( !CONSTANT_ADDRESS_P(Addr))					\
-	abort();							\
-      output_addr_const (FILE, Addr);					\
-    }}
-
-/*
-Local variables:
-version-control: t
-End:
-*/
diff --git a/gcc/config/we32k/we32k.md b/gcc/config/we32k/we32k.md
deleted file mode 100755
index 9d85a10..0000000
--- a/gcc/config/we32k/we32k.md
+++ /dev/null
@@ -1,1185 +0,0 @@
-;; Machine description for GNU compiler, AT&T we32000 Version
-;; Copyright (C) 1991, 1992, 1994 Free Software Foundation, Inc.
-;; Contributed by John Wehle (john@feith1.uucp)
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 1, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
-
-
-;;- instruction definitions
-
-;;- @@The original PO technology requires these to be ordered by speed,
-;;- @@    so that assigner will pick the fastest.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
-;;- When naming insn's (operand 0 of define_insn) be careful about using
-;;- names from other targets machine descriptions.
-
-;; move instructions
-
-(define_insn ""
-  [(set (match_operand:DF 0 "push_operand" "=m")
-        (match_operand:DF 1 "general_operand" "mrF"))]
-  ""
-  "*
-  {
-  output_push_double(&operands[1]);
-
-  return \"\";
-  }")
-
-(define_insn "movdf"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=mr")
-        (match_operand:DF 1 "general_operand" "mrF"))]
-  ""
-  "*
-  {
-  output_move_double(operands);
-
-  return \"\";
-  }")
-
-(define_insn ""
-  [(set (match_operand:SF 0 "push_operand" "=m")
-        (match_operand:SF 1 "general_operand" "mrF"))]
-  ""
-  "pushw %1")
-
-(define_insn "movsf"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=mr")
-        (match_operand:SF 1 "general_operand" "mrF"))]
-  ""
-  "movw %1, %0")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "push_operand" "=m")
-        (match_operand:DI 1 "general_operand" "mriF"))]
-  ""
-  "*
-  {
-  output_push_double(&operands[1]);
-
-  return \"\";
-  }")
-
-(define_insn "movdi"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=mr")
-        (match_operand:DI 1 "general_operand" "mriF"))]
-  ""
-  "*
-  {
-  output_move_double(operands);
-
-  return \"\";
-  }")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "push_operand" "=m")
-        (match_operand:SI 1 "general_operand" "mri"))]
-  ""
-  "pushw %1")
-
-(define_insn "movsi"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (match_operand:SI 1 "general_operand" "mri"))]
-  ""
-  "movw %1, %0")
-
-(define_insn "movhi"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (match_operand:HI 1 "general_operand" "mri"))]
-  ""
-  "movh %1, %0")
-
-(define_insn "movqi"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (match_operand:QI 1 "general_operand" "mri"))]
-  ""
-  "movb %1, %0")
-
-;; add instructions
-
-(define_insn ""
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
-        (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
-                 (match_operand:DI 2 "general_operand" "oriF")))]
-  ""
-  "*
-  {
-  rtx label[1];
-  rtx lsw_operands[3];
-
-  if (GET_CODE (operands[0]) == REG)
-    lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
-  else
-    if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
-      lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
-    else
-      abort();
-
-  if (GET_CODE (operands[2]) == REG)
-    lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
-  else
-    if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
-      lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
-    else
-      if (GET_CODE (operands[2]) == CONST_DOUBLE)
-        {
-        lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
-        operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
-        }
-      else
-        if (GET_CODE (operands[2]) == CONST_INT)
-          {
-          lsw_operands[2] = operands[2];
-          operands[2] = const0_rtx;
-          }
-        else
-          abort();
-
-  label[0] = gen_label_rtx();
-  LABEL_NUSES(label[0]) = 1;
-
-  output_asm_insn(\"addw2 %2, %0\", operands);
-  output_asm_insn(\"addw2 %2, %0\", lsw_operands);
-  output_asm_insn(\"BCCB %l0\", label);
-  output_asm_insn(\"INCW %0\", operands);
-  output_asm_insn(\"%l0:\", label);
-
-  return \"\";
-  }")
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
-        (plus:DI (match_operand:DI 1 "general_operand" "oriF")
-                 (match_operand:DI 2 "general_operand" "oriF")))]
-  ""
-  "*
-  {
-  rtx label[1];
-  rtx lsw_operands[3];
-
-  if (GET_CODE (operands[0]) == REG)
-    lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
-  else
-    if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
-      lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
-    else
-      abort();
-
-  if (GET_CODE (operands[1]) == REG)
-    lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1);
-  else
-    if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
-      lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
-    else
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-        {
-        lsw_operands[1] = GEN_INT (CONST_DOUBLE_HIGH(operands[1]));
-        operands[1] = GEN_INT (CONST_DOUBLE_LOW(operands[1]));
-        }
-      else
-        if (GET_CODE (operands[1]) == CONST_INT)
-          {
-          lsw_operands[1] = operands[1];
-          operands[1] = const0_rtx;
-          }
-        else
-          abort();
-
-  if (GET_CODE (operands[2]) == REG)
-    lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
-  else
-    if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
-      lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
-    else
-      if (GET_CODE (operands[2]) == CONST_DOUBLE)
-        {
-        lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
-        operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
-        }
-      else
-        if (GET_CODE (operands[2]) == CONST_INT)
-          {
-          lsw_operands[2] = operands[2];
-          operands[2] = const0_rtx;
-          }
-        else
-          abort();
-
-  label[0] = gen_label_rtx();
-  LABEL_NUSES(label[0]) = 1;
-
-  output_asm_insn(\"addw3 %2, %1, %0\", operands);
-  output_asm_insn(\"addw3 %2, %1, %0\", lsw_operands);
-  output_asm_insn(\"BCCB %l0\", label);
-  output_asm_insn(\"INCW %0\", operands);
-  output_asm_insn(\"%l0:\", label);
-
-  return \"\";
-  }")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                 (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "addw2 %2, %0")
-
-(define_insn "addsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (plus:SI (match_operand:SI 1 "general_operand" "mri")
-                 (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "addw3 %2, %1, %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (plus:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-                 (match_operand:HI 2 "general_operand" "mri")))]
-  ""
-  "addh2 %2, %0")
-
-(define_insn "addhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (plus:HI (match_operand:HI 1 "general_operand" "mri")
-                 (match_operand:HI 2 "general_operand" "mri")))]
-  ""
-  "addh3 %2, %1, %0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (plus:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-                 (match_operand:QI 2 "general_operand" "mri")))]
-  ""
-  "addb2 %2, %0")
-
-(define_insn "addqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (plus:QI (match_operand:QI 1 "general_operand" "mri")
-                 (match_operand:QI 2 "general_operand" "mri")))]
-  ""
-  "addb3 %2, %1, %0")
-
-;; subtract instructions
-
-(define_insn ""
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
-        (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
-                 (match_operand:DI 2 "general_operand" "oriF")))]
-  ""
-  "*
-  {
-  rtx label[1];
-  rtx lsw_operands[3];
-
-  if (GET_CODE (operands[0]) == REG)
-    lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
-  else
-    if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
-      lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
-    else
-      abort();
-
-  if (GET_CODE (operands[2]) == REG)
-    lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
-  else
-    if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
-      lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
-    else
-      if (GET_CODE (operands[2]) == CONST_DOUBLE)
-        {
-        lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
-        operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
-        }
-      else
-        if (GET_CODE (operands[2]) == CONST_INT)
-          {
-          lsw_operands[2] = operands[2];
-          operands[2] = const0_rtx;
-          }
-        else
-          abort();
-
-  label[0] = gen_label_rtx();
-  LABEL_NUSES(label[0]) = 1;
-
-  output_asm_insn(\"subw2 %2, %0\", operands);
-  output_asm_insn(\"subw2 %2, %0\", lsw_operands);
-  output_asm_insn(\"BCCB %l0\", label);
-  output_asm_insn(\"DECW %0\", operands);
-  output_asm_insn(\"%l0:\", label);
-
-  return \"\";
-  }")
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
-        (minus:DI (match_operand:DI 1 "general_operand" "oriF")
-                 (match_operand:DI 2 "general_operand" "oriF")))]
-  ""
-  "*
-  {
-  rtx label[1];
-  rtx lsw_operands[3];
-
-  if (GET_CODE (operands[0]) == REG)
-    lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
-  else
-    if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
-      lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
-    else
-      abort();
-
-  if (GET_CODE (operands[1]) == REG)
-    lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1);
-  else
-    if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
-      lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
-    else
-      if (GET_CODE (operands[1]) == CONST_DOUBLE)
-        {
-        lsw_operands[1] = GEN_INT (CONST_DOUBLE_HIGH(operands[1]));
-        operands[1] = GEN_INT (CONST_DOUBLE_LOW(operands[1]));
-        }
-      else
-        if (GET_CODE (operands[1]) == CONST_INT)
-          {
-          lsw_operands[1] = operands[1];
-          operands[1] = const0_rtx;
-          }
-        else
-          abort();
-
-  if (GET_CODE (operands[2]) == REG)
-    lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
-  else
-    if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
-      lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
-    else
-      if (GET_CODE (operands[2]) == CONST_DOUBLE)
-        {
-        lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
-        operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
-        }
-      else
-        if (GET_CODE (operands[2]) == CONST_INT)
-          {
-          lsw_operands[2] = operands[2];
-          operands[2] = const0_rtx;
-          }
-        else
-          abort();
-
-  label[0] = gen_label_rtx();
-  LABEL_NUSES(label[0]) = 1;
-
-  output_asm_insn(\"subw3 %2, %1, %0\", operands);
-  output_asm_insn(\"subw3 %2, %1, %0\", lsw_operands);
-  output_asm_insn(\"BCCB %l0\", label);
-  output_asm_insn(\"DECW %0\", operands);
-  output_asm_insn(\"%l0:\", label);
-
-  return \"\";
-  }")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                  (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "subw2 %2, %0")
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (minus:SI (match_operand:SI 1 "general_operand" "mri")
-                  (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "subw3 %2, %1, %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-                  (match_operand:HI 2 "general_operand" "mri")))]
-  ""
-  "subh2 %2, %0")
-
-(define_insn "subhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (minus:HI (match_operand:HI 1 "general_operand" "mri")
-                  (match_operand:HI 2 "general_operand" "mri")))]
-  ""
-  "subh3 %2, %1, %0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-                  (match_operand:QI 2 "general_operand" "mri")))]
-  ""
-  "subb2 %2, %0")
-
-(define_insn "subqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (minus:QI (match_operand:QI 1 "general_operand" "mri")
-                  (match_operand:QI 2 "general_operand" "mri")))]
-  ""
-  "subb3 %2, %1, %0")
-
-;; signed multiply instructions
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (mult:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                 (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "mulw2 %2, %0")
-
-(define_insn "mulsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (mult:SI (match_operand:SI 1 "general_operand" "mri")
-                 (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "mulw3 %2, %1, %0")
-
-;; signed divide instructions
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (div:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "divw2 %2, %0")
-
-(define_insn "divsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (div:SI (match_operand:SI 1 "general_operand" "mri")
-                (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "divw3 %2, %1, %0")
-
-;; signed modulus instruction
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (mod:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "modw2 %2, %0")
-
-(define_insn "modsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (mod:SI (match_operand:SI 1 "general_operand" "mri")
-                (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "modw3 %2, %1, %0")
-
-;; unsigned divide instruction
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                 (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "udivw2 %2, %0")
-
-(define_insn "udivsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (udiv:SI (match_operand:SI 1 "general_operand" "mri")
-                 (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "udivw3 %2, %1, %0")
-
-;; unsigned modulus instruction
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (umod:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                 (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "umodw2 %2, %0")
-
-(define_insn "umodsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (umod:SI (match_operand:SI 1 "general_operand" "mri")
-                 (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "umodw3 %2, %1, %0")
-
-;; logical-and instructions
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "andw2 %2, %0")
-
-(define_insn "andsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (and:SI (match_operand:SI 1 "general_operand" "mri")
-                (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "andw3 %2, %1, %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (and:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-                (match_operand:HI 2 "general_operand" "mri")))]
-  ""
-  "andh2 %2, %0")
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (and:HI (match_operand:HI 1 "general_operand" "mri")
-                (match_operand:HI 2 "general_operand" "mri")))]
-  ""
-  "andh3 %2, %1, %0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (and:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-                (match_operand:QI 2 "general_operand" "mri")))]
-  ""
-  "andb2 %2, %0")
-
-(define_insn "andqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (and:QI (match_operand:QI 1 "general_operand" "mri")
-                (match_operand:QI 2 "general_operand" "mri")))]
-  ""
-  "andb3 %2, %1, %0")
-
-;; inclusive-or instructions
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "orw2 %2, %0")
-
-(define_insn "iorsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (ior:SI (match_operand:SI 1 "general_operand" "mri")
-                (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "orw3 %2, %1, %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (ior:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-                (match_operand:HI 2 "general_operand" "mri")))]
-  ""
-  "orh2 %2, %0")
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (ior:HI (match_operand:HI 1 "general_operand" "mri")
-                (match_operand:HI 2 "general_operand" "mri")))]
-  ""
-  "orh3 %2, %1, %0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (ior:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-                (match_operand:QI 2 "general_operand" "mri")))]
-  ""
-  "orb2 %2, %0")
-
-(define_insn "iorqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (ior:QI (match_operand:QI 1 "general_operand" "mri")
-                (match_operand:QI 2 "general_operand" "mri")))]
-  ""
-  "orb3 %2, %1, %0")
-
-;; exclusive-or instructions
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "xorw2 %2, %0")
-
-(define_insn "xorsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (xor:SI (match_operand:SI 1 "general_operand" "mri")
-                (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "xorw3 %2, %1, %0")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (xor:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-                (match_operand:HI 2 "general_operand" "mri")))]
-  ""
-  "xorh2 %2, %0")
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (xor:HI (match_operand:HI 1 "general_operand" "mri")
-                (match_operand:HI 2 "general_operand" "mri")))]
-  ""
-  "xorh3 %2, %1, %0")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (xor:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-                (match_operand:QI 2 "general_operand" "mri")))]
-  ""
-  "xorb2 %2, %0")
-
-(define_insn "xorqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (xor:QI (match_operand:QI 1 "general_operand" "mri")
-                (match_operand:QI 2 "general_operand" "mri")))]
-  ""
-  "xorb3 %2, %1, %0")
-
-;; arithmetic shift instructions
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (ashift:SI (match_operand:SI 1 "general_operand" "mri")
-                   (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "LLSW3 %2, %1, %0")
-
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (ashiftrt:SI (match_operand:SI 1 "general_operand" "mri")
-                     (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "ARSW3 %2, %1, %0")
-
-;; logical shift instructions
-
-(define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (lshiftrt:SI (match_operand:SI 1 "general_operand" "mri")
-                     (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "LRSW3 %2, %1, %0")
-
-;; rotate instruction
-
-(define_insn "rotrsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (rotatert: SI (match_operand:SI 1 "general_operand" "mri")
-                      (match_operand:SI 2 "general_operand" "mri")))]
-  ""
-  "ROTW %2, %1, %0")
-
-;; negate instructions
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (neg:SI (match_operand:SI 1 "general_operand" "mri")))]
-  ""
-  "mnegw %1, %0")
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (neg:HI (match_operand:HI 1 "general_operand" "mri")))]
-  ""
-  "mnegh %1, %0")
-
-;; complement instructions
-
-(define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (not:SI (match_operand:SI 1 "general_operand" "mri")))]
-  ""
-  "mcomw %1, %0")
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (not:HI (match_operand:HI 1 "general_operand" "mri")))]
-  ""
-  "mcomh %1, %0")
-
-(define_insn "one_cmplqi2"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (not:QI (match_operand:QI 1 "general_operand" "mri")))]
-  ""
-  "mcomb %1, %0")
-
-;; test instruction
-
-;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
-;; be folded while optimizing anyway.
-
-(define_insn "tstsi"
-  [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "mr"))]
-  ""
-  "TSTW %0")
-
-(define_insn "tsthi"
-  [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "mr"))]
-  ""
-  "TSTH %0")
-
-(define_insn "tstqi"
-  [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "mr"))]
-  ""
-  "TSTB {sbyte}%0")
-
-;; compare instruction
-
-(define_insn "cmpsi"
-  [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "mr")
-                       (match_operand:SI 1 "general_operand" "mri")))]
-  ""
-  "CMPW %1, %0")
-
-(define_insn "cmphi"
-  [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_operand" "mr")
-                       (match_operand:HI 1 "general_operand" "mri")))]
-  ""
-  "*
-  {
-
-  if (GET_CODE (operands[1]) == CONST_INT &&
-    ((unsigned long)INTVAL (operands[1]) & 0x8000L))
-    operands[1] = GEN_INT (INTVAL(operands[1]) | 0xffff0000L);
-
-  output_asm_insn(\"CMPH %1, %0\",operands);
-
-  return \"\";
-  }")
-
-(define_insn "cmpqi"
-  [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_operand" "mr")
-                       (match_operand:QI 1 "general_operand" "mri")))]
-  ""
-  "*
-  {
-
-  if (GET_CODE (operands[1]) == CONST_INT &&
-    ((unsigned long)INTVAL (operands[1]) & 0x80L))
-    operands[1] = GEN_INT (INTVAL(operands[1]) | 0xffffff00L);
-
-  output_asm_insn(\"CMPB {sbyte}%1, {sbyte}%0\",operands);
-
-  return \"\";
-  }")
-
-;; truncate instructions
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=r")
-        (float_truncate:SF (match_operand:DF 1 "general_operand" "orF")))
-   (clobber (reg:SI 1))
-   (clobber (reg:SI 2))]
-  "REGNO (operands[0]) == 0"
-  "*
-  {
-  output_push_double(&operands[1]);
-  output_asm_insn(\"call &2, _fdtos\", operands);
-
-  return \"\";
-  }")
-
-(define_expand "truncdfsf2"
-  [(parallel [(set (reg:SF 0)
-               (float_truncate:SF (match_operand:DF 1 "general_operand" "orF")))
-              (clobber (reg:SI 1))
-              (clobber (reg:SI 2))])
-   (set (match_operand:SF 0 "nonimmediate_operand" "=mr")
-        (reg:SF 0))]
-  ""
-  "")
-
-(define_insn "truncsihi2"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (truncate:HI (match_operand:SI 1 "general_operand" "mri")))]
-  ""
-  "movtwh %1, %0")
-
-(define_insn "truncsiqi2"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (truncate:QI (match_operand:SI 1 "general_operand" "mri")))]
-  ""
-  "movtwb %1, %0")
-
-(define_insn "trunchiqi2"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
-        (truncate:QI (match_operand:HI 1 "general_operand" "mri")))]
-  ""
-  "movthb %1, %0")
-
-;; sign-extend move instructions
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=r")
-        (float_extend:DF (match_operand:SF 1 "general_operand" "mrF")))
-   (clobber (reg:SI 2))]
-  "REGNO (operands[0]) == 0"
-  "*
-  {
-  output_asm_insn(\"pushw %1\", operands);
-  output_asm_insn(\"call &1, _fstod\", operands);
-
-  return \"\";
-  }")
-
-(define_expand "extendsfdf2"
-  [(parallel [(set (reg:DF 0)
-               (float_extend:DF (match_operand:SF 1 "general_operand" "mrF")))
-              (clobber (reg:SI 2))])
-   (set (match_operand:DF 0 "nonimmediate_operand" "=or")
-        (reg:DF 0))]
-  ""
-  "")
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (sign_extend:SI (match_operand:HI 1 "general_operand" "mri")))]
-  ""
-  "movbhw %1, %0")
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (sign_extend:SI (match_operand:QI 1 "general_operand" "mri")))]
-  ""
-  "movbbw %1, %0")
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (sign_extend:HI (match_operand:QI 1 "general_operand" "mri")))]
-  ""
-  "movbbh %1, %0")
-
-;; zero-extend move instructions
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (zero_extend:SI (match_operand:HI 1 "general_operand" "mri")))]
-  ""
-  "movzhw %1, %0")
-
-(define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (zero_extend:SI (match_operand:QI 1 "general_operand" "mri")))]
-  ""
-  "movzbw %1, %0")
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
-        (zero_extend:HI (match_operand:QI 1 "general_operand" "mri")))]
-  ""
-  "movzbh %1, %0")
-
-;; bit field instructions
-
-(define_insn "extzv"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (zero_extract:SI (match_operand:SI 1 "general_operand" "mri")
-                         (match_operand:SI 2 "immediate_operand" "i")
-                         (match_operand:SI 3 "general_operand" "mri")))]
-  ""
-  "*
-  {
-
-  operands[2] = GEN_INT (INTVAL(operands[2]) - 1);
-  output_asm_insn(\"EXTFW %2, %3, %1, %0\",operands);
-
-  return \"\";
-  }")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (zero_extract:SI (match_operand:HI 1 "general_operand" "mri")
-                         (match_operand:SI 2 "immediate_operand" "i")
-                         (match_operand:SI 3 "general_operand" "mri")))]
-  ""
-  "*
-  {
-
-  operands[2] = GEN_INT (INTVAL(operands[2]) - 1);
-  output_asm_insn(\"EXTFH %2, %3, {uhalf}%1, {uword}%0\",operands);
-
-  return \"\";
-  }")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
-        (zero_extract:SI (match_operand:QI 1 "general_operand" "mri")
-                         (match_operand:SI 2 "immediate_operand" "i")
-                         (match_operand:SI 3 "general_operand" "mri")))]
-  ""
-  "*
-  {
-
-  operands[2] = GEN_INT (INTVAL(operands[2]) - 1);
-  output_asm_insn(\"EXTFB %2, %3, {ubyte}%1, {uword}%0\",operands);
-
-  return \"\";
-  }")
-
-(define_insn "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+mr")
-                         (match_operand:SI 1 "immediate_operand" "i")
-                         (match_operand:SI 2 "general_operand" "mri"))
-        (match_operand:SI 3 "general_operand" "mri"))]
-  ""
-  "*
-  {
-
-  operands[1] = GEN_INT (INTVAL(operands[1]) - 1);
-  output_asm_insn(\"INSFW %1, %2, %3, %0\",operands);
-
-  return \"\";
-  }")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:HI 0 "nonimmediate_operand" "+mr")
-                         (match_operand:SI 1 "immediate_operand" "i")
-                         (match_operand:SI 2 "general_operand" "mri"))
-        (match_operand:SI 3 "general_operand" "mri"))]
-  ""
-  "*
-  {
-
-  operands[1] = GEN_INT (INTVAL(operands[1]) - 1);
-  output_asm_insn(\"INSFH %1, %2, {uword}%3, {uhalf}%0\",operands);
-
-  return \"\";
-  }")
-
-(define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+mr")
-                         (match_operand:SI 1 "immediate_operand" "i")
-                         (match_operand:SI 2 "general_operand" "mri"))
-        (match_operand:SI 3 "general_operand" "mri"))]
-  ""
-  "*
-  {
-
-  operands[1] = GEN_INT (INTVAL(operands[1]) - 1);
-  output_asm_insn(\"INSFB %1, %2, {uword}%3, {ubyte}%0\",operands);
-
-  return \"\";
-  }")
-
-;; conditional branch instructions
-
-(define_insn "beq"
-  [(set (pc) (if_then_else (eq (cc0) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "je %l0")
-
-(define_insn "bne"
-  [(set (pc) (if_then_else (ne (cc0) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "jne %l0")
-
-(define_insn "bgt"
-  [(set (pc) (if_then_else (gt (cc0) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "jg %l0")
-
-(define_insn "bgtu"
-  [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "jgu %l0")
-
-(define_insn "blt"
-  [(set (pc) (if_then_else (lt (cc0) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "jl %l0")
-
-(define_insn "bltu"
-  [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "jlu %l0")
-
-(define_insn "bge"
-  [(set (pc) (if_then_else (ge (cc0) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "jge %l0")
-
-(define_insn "bgeu"
-  [(set (pc) (if_then_else (geu (cc0) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "jgeu %l0")
-
-(define_insn "ble"
-  [(set (pc) (if_then_else (le (cc0) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "jle %l0")
-
-(define_insn "bleu"
-  [(set (pc) (if_then_else (leu (cc0) (const_int 0))
-                           (label_ref (match_operand 0 "" ""))
-                           (pc)))]
-  ""
-  "jleu %l0")
-
-;; reverse-conditional branch instructions
-
-(define_insn ""
-  [(set (pc) (if_then_else (eq (cc0) (const_int 0))
-                           (pc)
-                           (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jne %l0")
-
-(define_insn ""
-  [(set (pc) (if_then_else (ne (cc0) (const_int 0))
-                           (pc)
-                           (label_ref (match_operand 0 "" ""))))]
-  ""
-  "je %l0")
-
-(define_insn ""
-  [(set (pc) (if_then_else (gt (cc0) (const_int 0))
-                           (pc)
-                           (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jle %l0")
-
-(define_insn ""
-  [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
-                           (pc)
-                           (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jleu %l0")
-
-(define_insn ""
-  [(set (pc) (if_then_else (lt (cc0) (const_int 0))
-                           (pc)
-                           (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jge %l0")
-
-(define_insn ""
-  [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
-                           (pc)
-                           (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jgeu %l0")
-
-(define_insn ""
-  [(set (pc) (if_then_else (ge (cc0) (const_int 0))
-                           (pc)
-                           (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jl %l0")
-
-(define_insn ""
-  [(set (pc) (if_then_else (geu (cc0) (const_int 0))
-                           (pc)
-                           (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jlu %l0")
-
-(define_insn ""
-  [(set (pc) (if_then_else (le (cc0) (const_int 0))
-                           (pc)
-                           (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jg %l0")
-
-(define_insn ""
-  [(set (pc) (if_then_else (leu (cc0) (const_int 0))
-                           (pc)
-                           (label_ref (match_operand 0 "" ""))))]
-  ""
-  "jgu %l0")
-
-;; call instructions
-
-(define_insn "call"
-  [(call (match_operand:QI 0 "memory_operand" "m")
-         (match_operand:SI 1 "immediate_operand" "i"))]
-  ""
-  "call %1/4, %0")
-
-(define_insn "call_value"
-  [(set (match_operand 0 "register_operand" "=r")
-        (call (match_operand:QI 1 "memory_operand" "m")
-              (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
-  "call %2/4, %1")
-
-;; No-op instruction
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "NOP")
-
-;; jump through a dispatch table instruction
-
-(define_expand "casesi"
-  [(use (match_operand:SI 0 "general_operand" "mri"))
-   (set (cc0) (compare (match_dup 5)
-                       (match_operand:SI 1 "general_operand" "mri")))
-   (set (pc) (if_then_else (lt (cc0) (const_int 0))
-                           (label_ref (match_operand 4 "" ""))
-                           (pc)))
-   (set (match_dup 5) (minus:SI (match_dup 5)
-                                (match_dup 1)))
-   (set (cc0) (compare (match_dup 5)
-                       (match_operand:SI 2 "general_operand" "mri")))
-   (set (pc) (if_then_else (gtu (cc0) (const_int 0))
-                           (label_ref (match_dup 4))
-                           (pc)))
-   (set (match_dup 5) (ashift:SI (match_dup 5)
-                                 (const_int 2)))
-   (set (pc) (mem:SI (plus:SI (label_ref (match_operand 3 "" ""))
-                              (match_dup 5))))]
-  ""
-  "
-  {
-  operands[5] = gen_reg_rtx(GET_MODE (operands[0]));
-  emit_move_insn(operands[5], operands[0]);
-  }")
-
-;; jump instructions
-
-(define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
-  ""
-  "jmp %a0")
-
-(define_insn "jump"
-  [(set (pc) (label_ref (match_operand 0 "" "")))]
-  ""
-  "jmp %l0")
diff --git a/gcc/config/we32k/x-we32k b/gcc/config/we32k/x-we32k
deleted file mode 100755
index 3375d42..0000000
--- a/gcc/config/we32k/x-we32k
+++ /dev/null
@@ -1 +0,0 @@
-ALLOCA=alloca.o
diff --git a/gcc/config/we32k/xm-we32k.h b/gcc/config/we32k/xm-we32k.h
deleted file mode 100755
index 70aa35b..0000000
--- a/gcc/config/we32k/xm-we32k.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Configuration for GNU C-compiler for AT&T we32000 Family.
-   Copyright (C) 1991, 1992, 1993, 1996 Free Software Foundation, Inc.
-   Contributed by John Wehle (john@feith1.uucp)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-#define HOST_WORDS_BIG_ENDIAN
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-/* Don't try to use sys_siglist.  */
-#define NO_SYS_SIGLIST
-
-#ifndef MAXPATHLEN
-#define MAXPATHLEN 512
-#endif
diff --git a/gcc/config/winnt/config-nt.bat b/gcc/config/winnt/config-nt.bat
deleted file mode 100755
index 688d126..0000000
--- a/gcc/config/winnt/config-nt.bat
+++ /dev/null
@@ -1,58 +0,0 @@
-echo Configuring GCC for Windows NT on %2
-rem This batch file assumes a unix-type "sed" program
-
-if %2.==alpha. echo #include "alpha/xm-alpha.h" >config.h
-if %2.==alpha. echo #include "winnt/xm-winnt.h" >>config.h
-if %2.==alpha. echo #include "alpha/xm-winnt.h" >>config.h
-if not %2.==alpha.  echo #include "%2/xm-winnt.h" >config.h
-copy config.h hconfig.h
-copy config.h tconfig.h
-
-if %2.==alpha. echo #define TARGET_CPU_DEFAULT 64 >tm.h
-if %2.==alpha. echo #include "alpha/alpha.h" >>tm.h
-if %2.==alpha. echo #include "alpha/win-nt.h" >>tm.h
-if not %2.==alpha. echo #include "%2/win-nt.h" >tm.h
-
-rem This batch file assumes a unix-type "sed" program
-
-echo # Makefile generated by "config-nt.bat"> Makefile
-echo all.nt: cpp.exe cc1.exe cc1obj.exe xgcc.exe ld.exe stmp-headers libgcc.lib stmp-float_h specs stamp-objlist>> Makefile
-sed -f config/%2/config-nt.sed -f config/winnt/config-nt.sed Makefile.in >> Makefile
-
-set LANG=
-
-echo # >specs.h
-echo # >options.h
-
-if not exist cp\make-lang.in goto no_cp
-if exist cp\lang-specs.h echo #include "cp/lang-specs.h">>specs.h
-if exist cp\lang-options.h echo #include "cp/lang-options.h">>options.h
-sed -f config/%2/config-nt.sed -f config/winnt/config-nt.sed cp\make-lang.in >> Makefile
-sed -f config/%2/config-nt.sed -f config/winnt/config-nt.sed cp\makefile.in > cp\Makefile
-set LANG=%LANG% c++.#	
-:no_cp
-
-if not exist ada\make-lang.in goto no_ada
-if exist ada\lang-specs.h echo #include "ada/lang-specs.h">>specs.h
-if exist ada\lang-options.h echo #include "ada/lang-options.h">>options.h
-sed -f config/%2/config-nt.sed -f config/winnt/config-nt.sed ada\make-lang.in >> Makefile
-sed -f config/%2/config-nt.sed -f config/winnt/config-nt.sed ada\makefile.in > ada\Makefile
-set LANG=%LANG% ada.#	
-:no_ada
-
-if not exist f\make-lang.in goto no_f
-if exist f\lang-specs.h echo #include "f/lang-specs.h">>specs.h
-if exist f\lang-options.h echo #include "f/lang-options.h">>options.h
-sed -f config/%2/config-nt.sed -f config/winnt/config-nt.sed f\make-lang.in >> Makefile
-sed -f config/%2/config-nt.sed -f config/winnt/config-nt.sed f\makefile.in > f\Makefile
-set LANG=%LANG% f.#	
-:no_f
-
-echo lang.mostlyclean: %LANG% | sed "s/#/mostlyclean/g" >> Makefile
-echo lang.clean: %LANG% | sed "s/#/clean/g" >> Makefile
-echo lang.distclean: %LANG% | sed "s/#/distclean/g" >> Makefile
-echo lang.realclean: %LANG% | sed "s/#/realclean/g" >> Makefile
-
-echo #define MULTILIB_SELECT ". ;" > multilib.h1
-copy multilib.h1 multilib.h
-del multilib.h1
diff --git a/gcc/config/winnt/config-nt.sed b/gcc/config/winnt/config-nt.sed
deleted file mode 100755
index 9beceab..0000000
--- a/gcc/config/winnt/config-nt.sed
+++ /dev/null
@@ -1,127 +0,0 @@
-/^Makefile/,/^	rm -f config.run/d
-s/rm -f/del/
-s/|| cp/|| copy/
-/^config.status/,/	fi/d
-s/config.status//g
-s/\/dev\/null/NUL/g
-s/$(srcdir)\/c-parse/c-parse/g
-s/$(srcdir)\/objc-parse.y/objc-parse.y/g
-s/$(srcdir)\/c-gperf/c-gperf/g
-/^multilib.h/ s/multilib/not-multilib/
-/^xmake_file=/ d
-/^tmake_file=/ d
-/^lang_specs_files=/ d
-/^lang_options_files=/ d
-/^version=/ c\
-version=2.8.1
-s/CC = cc/CC = cl/
-s/^SHELL =.*/SHELL =/
-s/CFLAGS = -g/CFLAGS =/
-s/:\$/: \$/g
-s/<\ *\$(srcdir)\//< $(srcdir)\\/g
-s/^	\$(srcdir)\/move-if-change/	copy/
-s/^USE_/# USE_/
-s/`echo \$(srcdir)\///g
-s/ | sed 's,\^\\\.\/,,'`//g
-s/^	cd \$(srcdir)[ 	]*;/	/
-/^stamp-attrtab/,/copy/ {
-  /\\$/d
-  /	fi/d
-  /copy/ i\
-\	  genattrtab $(md_file) > tmp-attrtab.c
-}
-/^enquire[ 	]*:/ s/\$(GCC_PARTS)//g
-/^enquire.o[ 	]*:/ s/\$(GCC_PASSES)//g
-/^GCC_FOR_TARGET =/ c\
-GCC_FOR_TARGET = xgcc
-/^ENQUIRE_LDFLAGS =/ c\
-ENQUIRE_LDFLAGS =
-s/; *@true//
-/> *stamp-objlist/ c\
-	echo.exe  $(OBJS) | sed -e "s, \([a-z]\), ../\1,g" >stamp-objlist
-/^OBJS.*stamp-objlist/ s?`cat ../stamp-objlist`?@../stamp-objlist?
-s/^\(SUBDIR_OBSTACK *=\).*$/\1 ..\/obstack.o/
-s/^\(SUBDIR_USE_ALLOCA *=\).*$/\1/
-s/^\(SUBDIR_MALLOC *=\).*$/\1/
-/####target/ i\
-STMP_FIXPROTO = \
-OTHER_FIXINCLUDES_DIRS=. \
-RANLIB = : \
-RANLIB_TEST = false \
-OLDCC = cl \
-MAKE = nmake \
-SYMLINK = copy \
-INSTALL = $(srcdir)/install.sh -c \
-exeext = .exe \
-objext = .obj \
-oldobjext = .obj \
-\
-EXTRA_PROGRAMS=ld.exe \
-\
-ld.obj: $(srcdir)/config/winnt/ld.c \
-\	$(CC) $(CFLAGS) \\\
-\ 	-I. -I$(srcdir) -I$(srcdir)/config -c $(srcdir)/config/winnt/ld.c \
-\
-ld.exe: ld.obj \
-	link -out:ld.exe ld.obj $(LDFLAGS) $(CLIB) \
-\
-EXTRA_GCC_OBJS=spawnv.obj oldnames.obj \
-spawnv.obj: $(srcdir)/config/winnt/spawnv.c \
-\	$(CC) $(CFLAGS) \\\
-\ 	-I. -I$(srcdir) -I$(srcdir)/config -c $(srcdir)/config/winnt/spawnv.c \
-\
-oldnames.obj: $(srcdir)/config/winnt/oldnames.c \
-\	$(CC) $(CFLAGS) \\\
-\ 	-I. -I$(srcdir) -I$(srcdir)/config -c $(srcdir)/config/winnt/oldnames.c
-s/^C c:/Cc:/
-s/\${OBJS}/\$(OBJS)/g
-s/\${SYSTEM_HEADER_DIR}/\$(SYSTEM_HEADER_DIR)/g
-s/\${HOST_CC}/\$(HOST_CC)/g
-s/ \${srcdir}\// /g
-s/\${mainversion}/\$(mainversion)/g
-s/\ $(srcdir)\/move-if-change$//
-s/\$(srcdir)\/move-if-change/copy/g
-/^# USE_HOST_OBSTACK/ i\
-USE_HOST_OBSTACK=obstack.obj
-/^# USE_ALLOCA/ i\
-USE_ALLOCA=alloca.obj
-/^# USE_HOST_ALLOCA/ i\
-USE_HOST_ALLOCA=alloca.obj
-s/^ALLOCA =/ALLOCA = alloca.obj/
-s/^ALLOCA_FINISH = true/ALLOCA_FINISH =/
-s/	\.\//	/
-s/^gen\([a-z]*\) *:/gen\1.exe :/
-s/ gen\([a-z]*\)$/ gen\1.exe/
-s/ gen\([a-z]*\) / gen\1.exe /g
-s/genmultilib.exe/genmultilib/g
-s/^cccp *:/cccp.exe :/
-s/cccp$/cccp.exe/
-s/cccp /cccp.exe /
-s/CCCP=cccp.exe/CCCP=cccp/
-s/(CCCP)$/(CCCP)$(exeext)/
-s/^cpp *:/cpp.exe :/
-s/cpp$/cpp.exe/
-s/cpp /cpp.exe /
-s/^cc1 *:/cc1.exe :/
-s/cc1$/cc1.exe/
-s/cc1 /cc1.exe /
-s/^cc1obj *:/cc1obj.exe :/
-s/cc1obj$/cc1obj.exe/
-s/cc1obj /cc1obj.exe /
-s/^xgcc *:/xgcc.exe :/
-s/xgcc$/xgcc.exe/
-s/xgcc /xgcc.exe /
-s/^enquire *:/enquire.exe :/
-s/enquire$/enquire.exe/
-s/enquire /enquire.exe /
-s/\.o *:/.obj :/
-s/\.o$/.obj/
-s/\.o /.obj /g
-s/-rm -f cpp.exe/del cpp.exe/
-s/\$(CC) \$(ALL_CFLAGS) \$(LDFLAGS) -o /link $(LDFLAGS) -out:/
-s/\$(HOST_CC) \$(HOST_CFLAGS) \$(HOST_LDFLAGS) -o /link $(HOST_LDFLAGS) -out:/
-/^# Build libgcc.a/ r config/winnt/libgcc.mak
-/^# Build libgcc.a/,// d
-/^# Build the include directory\./ r config/winnt/headers.mak
-/^# Build the include directory\./,/touch objc-headers/ d
-s/^\//
diff --git a/gcc/config/winnt/dirent.c b/gcc/config/winnt/dirent.c
deleted file mode 100755
index 59f7dc1..0000000
--- a/gcc/config/winnt/dirent.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * @(#)msd_dir.c 1.4 87/11/06	Public Domain.
- *
- *  A public domain implementation of BSD directory routines for
- *  MS-DOS.  Written by Michael Rendell ({uunet,utai}michael@garfield),
- *  August 1897
- *
- *  Modified by Ian Stewartson, Data Logic (istewart@datlog.co.uk).
- *
- *  Updates:  1.  To support OS/2 1.x
- *	      2.  To support HPFS long filenames
- *	      3.  To support OS/2 2.x
- *	      4.  To support TurboC
- *	      5.  To support Windows NT
- */
-
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <malloc.h>
-
-#include <string.h>
-#include <limits.h>
-#include <ctype.h>
-#include <errno.h>
-#include <dirent.h>
-
-
-#define WIN32_LEAN_AND_MEAN
-#include <windows.h>
-
-#define FILE_NAME_E		cFileName
-#define OS_CloseFH(a)		FindClose (a)
-#define FIND_BUFFER		WIN32_FIND_DATA
-#define DISABLE_HARD_ERRORS	SetErrorMode (0)
-#define ENABLE_HARD_ERRORS	SetErrorMode (SEM_FAILCRITICALERRORS | \
-					      SEM_NOOPENFILEERRORBOX);
-
-#  define ERROR_EMPTY_DIR	ERROR_FILE_NOT_FOUND
-
-#  define ATTRIBUTES		(_A_SUBDIR | _A_HIDDEN | _A_SYSTEM | \
-				 _A_NORMAL | _A_RDONLY | _A_ARCH)
-
-/*
- * missing ??
- */
-
-#ifndef ENOTDIR
-#  define ENOTDIR	120	/* Not a directory			*/
-#endif
-
-#ifndef S_IFMT
-#  define	S_IFMT	0xf000	/* type of file				*/
-#endif
-
-#ifndef S_ISDIR
-#  define S_ISDIR(m)	((((m) & S_IFMT) == S_IFDIR))
-#endif
-
-/*
- * Internals
- */
-
-typedef struct _dircontents	DIRCONT;
-static void			free_dircontents (DIRCONT *);
-
-/*
- * Open the directory stream
- */
-
-DIR *
-opendir (name)
-    const char	*name;
-{
-    struct stat		statb;
-    DIR			*dirp;
-    char		*last;
-    DIRCONT		*dp;
-    char		*nbuf;
-    int			len = strlen (name);
-    unsigned long	rc;
-    FIND_BUFFER		dtabuf;
-    HANDLE		d_handle;
-    bool		HPFS = FALSE;
-
-    if (!len)
-    {
-	errno = ENOTDIR;
-	return (DIR *)NULL;
-    }
-
-    if ((nbuf = malloc (len + 5)) == (char *)NULL)
-	return (DIR *) NULL;
-
-    strcpy (nbuf, name);
-    last = &nbuf[len - 1];
-
-/* Ok, DOS is very picky about its directory names.  The following are
- * valid.
- *
- *  c:/
- *  c:.
- *  c:name/name1
- *
- *  c:name/ is not valid
- */
-
-    if (((*last == '\\') || (*last == '/')) && (len > 1) &&
-	(!((len == 3) && (name[1] == ':'))))
-	*(last--) = 0;
-
-/* Check its a directory */
-
-    DISABLE_HARD_ERRORS;
-    rc = stat (nbuf, &statb);
-    ENABLE_HARD_ERRORS;
-
-    if (rc)
-    {
-	free (nbuf);
-	return (DIR *) NULL;
-    }
-
-    if (!S_ISDIR (statb.st_mode))
-    {
-	free (nbuf);
-	errno = ENOTDIR;
-	return (DIR *)NULL;
-    }
-
-    if ((dirp = (DIR *) malloc (sizeof (DIR))) == (DIR *) NULL)
-    {
-	free (nbuf);
-	return (DIR *) NULL;
-    }
-
-/* Set up to find everything */
-
-    if ((*last != '\\') && (*last != '/'))
-	strcat (last, "/");
-
-    strcat (last, "*.*");
-
-/* Find the file system type */
-
-    HPFS = IsHPFSFileSystem (nbuf);
-
-    dirp->dd_loc      = 0;
-    dirp->dd_cp       = (DIRCONT *) NULL;
-    dirp->dd_contents = (DIRCONT *) NULL;
-
-    DISABLE_HARD_ERRORS;
-
-    d_handle = FindFirstFile (nbuf, &dtabuf);
-    rc = (d_handle == INVALID_HANDLE_VALUE) ? GetLastError () : 0;
-
-    ENABLE_HARD_ERRORS;
-
-/* Check for errors */
-
-    if (rc)
-    {
-	free (nbuf);
-
-/* Empty directory */
-
-#if defined (ERROR_EMPTY_DIR)
-	if (rc == ERROR_EMPTY_DIR)
-	    return dirp;
-#endif
-
-	free (dirp);
-	return (DIR *) NULL;
-    }
-
-/* Process the directory */
-
-    do
-    {
-	if (((dp = (DIRCONT *) malloc (sizeof (DIRCONT))) == (DIRCONT *)NULL) ||
-	    ((dp->_d_entry = strdup (dtabuf.FILE_NAME_E)) == (char *) NULL))
-	{
-	    if (dp->_d_entry != (char *)NULL)
-		free ((char *)dp);
-
-	    free (nbuf);
-	    free_dircontents (dirp->dd_contents);
-
-	    OS_CloseFH (d_handle);
-	    return (DIR *) NULL;
-	}
-
-	if (!HPFS)
-	    strlwr (dp->_d_entry);
-
-	if (dirp->dd_contents != (DIRCONT *) NULL)
-	    dirp->dd_cp = dirp->dd_cp->_d_next = dp;
-
-	else
-	    dirp->dd_contents = dirp->dd_cp = dp;
-
-	dp->_d_next = (DIRCONT *) NULL;
-
-    } while (FindNextFile (d_handle, &dtabuf));
-
-    dirp->dd_cp = dirp->dd_contents;
-    free (nbuf);
-
-    OS_CloseFH (d_handle);
-    return dirp;
-}
-
-
-/*
- * Close the directory stream
- */
-
-int
-closedir (dirp)
-    DIR *dirp;
-{
-    if (dirp != (DIR *)NULL)
-    {
-	free_dircontents (dirp->dd_contents);
-	free ((char *)dirp);
-    }
-
-    return 0;
-}
-
-/*
- * Read the next record from the stream
- */
-
-struct dirent *
-readdir (dirp)
-    DIR	*dirp;
-{
-    static struct dirent	dp;
-
-    if ((dirp == (DIR *)NULL) || (dirp->dd_cp == (DIRCONT *) NULL))
-	return (struct dirent *) NULL;
-
-    dp.d_reclen = strlen (strcpy (dp.d_name, dirp->dd_cp->_d_entry));
-    dp.d_off    = dirp->dd_loc * 32;
-    dp.d_ino    = (ino_t)++dirp->dd_loc;
-    dirp->dd_cp = dirp->dd_cp->_d_next;
-
-    return &dp;
-}
-
-/*
- * Restart the directory stream
- */
-
-void
-rewinddir (dirp)
-    DIR *dirp;
-{
-    seekdir (dirp, (off_t)0);
-}
-
-/*
- * Move to a know position in the stream
- */
-
-void
-seekdir (dirp, off)
-    DIR *dirp;
-    off_t off;
-{
-    long	i = off;
-    DIRCONT	*dp;
-
-    if ((dirp == (DIR *)NULL) || (off < 0L))
-	return;
-
-    for (dp = dirp->dd_contents; (--i >= 0) && (dp != (DIRCONT *)NULL);
-	 dp = dp->_d_next)
-	;
-
-    dirp->dd_loc = off - (i + 1);
-    dirp->dd_cp = dp;
-}
-
-/*
- * Get the current position
- */
-
-off_t
-telldir(dirp)
-    DIR *dirp;
-{
-    return (dirp == (DIR *)NULL) ? (off_t) -1 : dirp->dd_loc;
-}
-
-/*
- * Release the internal structure
- */
-
-static void
-free_dircontents (dp)
-    DIRCONT *dp;
-{
-    DIRCONT	*odp;
-
-    while ((odp = dp) != (DIRCONT *)NULL)
-    {
-	if (dp->_d_entry != (char *)NULL)
-	    free (dp->_d_entry);
-
-	dp = dp->_d_next;
-	free ((char *)odp);
-    }
-}
-
-
-/*
- * Windows NT version
- */
-
-bool
-IsHPFSFileSystem (directory)
-    char *directory;
-{
-    char		bName[4];
-    DWORD		flags;
-    DWORD		maxname;
-    BOOL		rc;
-    unsigned int	nDrive;
-    char		szCurDir [MAX_PATH];
-
-    if (isalpha (directory[0]) && (directory[1] == ':'))
-	nDrive = toupper (directory[0]) - '@';
-
-    else
-    {
-	GetCurrentDirectory (MAX_PATH, szCurDir);
-	nDrive = szCurDir[0] - 'A' + 1;
-    }
-
-/* Set up the drive name */
-
-    strcpy (bName, "x:\\");
-    bName[0] = (char) (nDrive + '@');
-
-/* Read the volume info, if we fail - assume non-HPFS */
-
-    DISABLE_HARD_ERRORS;
-
-    rc = GetVolumeInformation (bName, (LPTSTR)NULL, 0, (LPDWORD)NULL,
-			       &maxname, &flags, (LPTSTR)NULL, 0);
-    ENABLE_HARD_ERRORS;
-
-    return ((rc) && (flags & (FS_CASE_SENSITIVE | FS_CASE_IS_PRESERVED)))
-    		? TRUE : FALSE;
-}
-
diff --git a/gcc/config/winnt/dirent.h b/gcc/config/winnt/dirent.h
deleted file mode 100755
index 822bd2c..0000000
--- a/gcc/config/winnt/dirent.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * dirent.h
- */
-
-#ifndef _DIRENT_H
-#  define _DIRENT_H
-
-#  include <sys/types.h>
-#  include <limits.h>
-
-#define MAXNAMLEN	255	/* maximum filename length		*/
-
-#ifndef NAME_MAX
-#define	NAME_MAX	(MAXNAMLEN - 1)
-#endif
-
-struct dirent			/* data from getdents()/readdir()	*/
-{
-    ino_t	d_ino;		/* inode number of entry		*/
-    off_t	d_off;		/* offset of disk directory entry	*/
-    wchar_t	d_reclen;	/* length of this record		*/
-    char	d_name[MAXNAMLEN + 1];
-};
-
-
-/* The following nonportable ugliness could have been avoided by defining
- * DIRENTSIZ and DIRENTBASESIZ to also have (struct dirent *) arguments.
- * There shouldn't be any problem if you avoid using the DIRENTSIZ() macro.
- */
-
-#define	DIRENTBASESIZ		(((struct dirent *)0)->d_name \
-				- (char *)&((struct dirent *)0)->d_ino)
-
-#define	DIRENTSIZ(namlen)	((DIRENTBASESIZ + sizeof(long) + (namlen)) \
-				/ sizeof(long) * sizeof(long))
-
-
-
-#  ifndef _BOOL_T_DEFINED
-typedef unsigned char	bool;
-#  define _BOOL_T_DEFINED
-#  endif
-
-#  define DIRBUF	8192	/* buffer size for fs-indep. dirs	*/
-				/* must in general be larger than the	*/
-				/* filesystem buffer size		*/
-
-struct _dircontents {
-    char		*_d_entry;
-    struct _dircontents	*_d_next;
-};
-
-typedef struct _dirdesc {
-    int			dd_id;	/* uniquely identify each open directory */
-    long		dd_loc;	/* where we are in directory entry is this */
-    struct _dircontents	*dd_contents;	/* pointer to contents of dir	*/
-    struct _dircontents	*dd_cp;		/* pointer to current position	*/
-} DIR;
-
-
-#if defined (__STDC__)
-#  define _PROTO(p)	p
-#else
-#  define _PROTO(p)	()
-#  undef  const
-#  undef  volatile
-#endif
-
-/* Functions */
-
-extern DIR *		opendir	_PROTO ((const char *));
-extern struct dirent * 	readdir _PROTO ((DIR *));
-extern void		rewinddir _PROTO ((DIR *));
-
-extern int		closedir _PROTO ((DIR *));
-extern void		seekdir	_PROTO ((DIR *, off_t));
-extern off_t		telldir	_PROTO ((DIR *));
-
-extern int		chdir _PROTO ((const char *));
-extern char * 		getcwd _PROTO ((char *, size_t));
-
-extern int		mkdir _PROTO ((const char *));
-
-extern int		rmdir _PROTO ((const char *));
-extern int		scandir _PROTO ((char *,
-			 struct dirent ***,
-			 int (*)(const void *, const void *),
-			 int (*)(const void *, const void *)));
-
-extern int		_chdrive _PROTO ((int));
-extern int		_getdrive _PROTO ((void));
-extern char * 		_getdcwd _PROTO ((int, char *, int));
-
-extern bool		IsHPFSFileSystem _PROTO ((char *));
-
-#endif
diff --git a/gcc/config/winnt/fixinc-nt.c b/gcc/config/winnt/fixinc-nt.c
deleted file mode 100755
index f49d6dd..0000000
--- a/gcc/config/winnt/fixinc-nt.c
+++ /dev/null
@@ -1,260 +0,0 @@
-#include <stdlib.h>
-#include <string.h>
-#include <sys/stat.h>
-#include <dirent.h>
-#include <stdio.h>
-#include <io.h>
-#include <fcntl.h>
-#include <process.h>
-
-static char *concat();
-static char *concat3();
-static char *concat4();
-static int onlyonedir;
-static int atleastone;
-static char *fixeddirs, *origdirs;
-
-/* Convert all /'s to \'s */
-
-char *
-slash2slash (dirname)
-  char *dirname;
-{
-  int i;
-  for (i=0; dirname[i]; i++)
-    if (dirname [i] == '/')
-      dirname [i] = '\\';
-
-  return dirname;
-}
-
-/* Examine each directory component of a path and create the directory */
-
-int
-mkdirpath (dirpath)
-  char *dirpath;
-{
-  char *ndirpath = strdup (dirpath);
-  char *bp, *fp;
-
-  fp = bp = ndirpath;
-
-  while (bp) 
-    {
-      bp = strchr (fp, '\\');
-      if (bp)
-        {
-          *bp = 0;
-          _mkdir (ndirpath);
-          *bp = '\\';
-          fp = ++bp;
-        }
-      else
-        _mkdir (ndirpath);
-    }
-}
-
-/* Construct a relative directory path from a given path by removing the
-   leading slash, if it exists and changing a drive letter from X: to X-. */
-
-char *
-newname (olddirname)
-  char *olddirname;
-{
-  char *newname = strdup (olddirname);
-
-  if ((strlen (newname) >= 2)
-      && (isalpha (newname[0]) && newname[1] == ':'))
-    newname [1] = '-';
-  else if ((strlen (newname) >= 1) 
-           && (newname [0] == '/' || newname [0] == '\\'))
-    newname = &newname[1];
-
-  return newname;
- 
-}
-
-/* Run the sed script on one header file.  If no modifications were made, then
-   delete the newly created file. */
-
-int
-doheader (oneheader, outheader, oldsize)
-  char *oneheader, *outheader;
-  int oldsize;
-{
-  char *newbuff, *oldbuff;
-  char *newheader = concat3 ("include", "\\", newname (outheader));
-  struct _stat newstatbuf;
-  int newdesc, olddesc;
-  int i;
-
-  system (concat4 ("sed -f fixinc-nt.sed ", oneheader, " > ", newheader));
-  _stat (newheader, &newstatbuf);
-  if (oldsize != newstatbuf.st_size) 
-    {
-      atleastone = 1;
-      printf ("Fixing: %s\n", oneheader);
-      return 0;
-    }
-  oldbuff = malloc (oldsize);
-  newbuff = malloc (newstatbuf.st_size);
-  olddesc = open (oneheader, _O_RDONLY | _O_BINARY);
-  newdesc = open (newheader, _O_RDONLY | _O_BINARY);
-  read (olddesc, oldbuff, oldsize);
-  read (newdesc, newbuff, newstatbuf.st_size);
-  close (olddesc);
-  close (newdesc);
-  for (i=0; i<oldsize; i++)
-    {
-      if (oldbuff [i] != newbuff [i])
-        {
-          free (oldbuff);
-          free (newbuff);
-          atleastone = 1;
-          printf ("Fixing: %s\n", oneheader);
-          return 0;
-        }
-    }
-  free (oldbuff);
-  free (newbuff);
-  unlink (newheader);
-  return 0;
-  
-}
-
-/* Examine the contents of a directory and call doheader () for a regular file
-   and recursively call dodir () for an enclosed directory. */
-
-int
-dodir (indir, outdir)
-  char *indir, *outdir;
-{
-  DIR *dir;
-  struct dirent *dire;
-  struct _stat statbuf;
-  char *intempbuf, *outtempbuf;
-
-  dir = opendir (indir);
-  if (!dir) return 0;
-
-  mkdirpath (concat3 ("include", "\\", newname (outdir)));
-  while ((dire = readdir (dir)))
-    {
-      if (dire->d_name[0] == '.')
-        continue;
-  
-      intempbuf = slash2slash (concat3 (indir, "\\", dire->d_name));
-      outtempbuf = slash2slash (concat3 (outdir, "\\", dire->d_name));
-      _stat (intempbuf, &statbuf);
-  
-      /* If directory ... */
-      if (statbuf.st_mode & _S_IFDIR)
-        dodir (intempbuf, outtempbuf);
-  
-      /* If regular file ... */
-      if (statbuf.st_mode & _S_IFREG)
-        doheader (intempbuf, outtempbuf, statbuf.st_size);
-    }
-  closedir (dir);
-  return 0;
-}
-
-/* Retrieve the value of the Include environment variable, copy it into a
-   temporary and append a semi-colon for book-keeping purposes. Then call
-   dodir () for each complete directory that is named therein.  If there is
-   only one directory, then direct the output to use include\. as the
-   root instead of include/<directory path>, where <directory path> is a path
-   constructed from the path named in the Include environment variable.  
-   I.e. if Include=C:\MSTOOLS\Include;D:\MSVC20\Include then the modified
-   header files will be in include\C-\MSTOOLS\Include and 
-   include\D-\MSVC20\Include.  However if Include=C:\MSTOOLS\Include then the
-   modified files will be in include\. */
-
-int
-main ()
-{
-  char *fp, *bp, *foobar;
-  char *incvar = getenv ("Include");
-  int varlen = 0;
-  struct _stat statbuf;
-
-  if (incvar == NULL) return 0;
-
-  varlen = strlen (incvar);
-  foobar = (char *) malloc (varlen + 2);
-
-  strcpy (foobar, incvar);
-  foobar = slash2slash (foobar);
-  if (foobar [varlen-1] != ';') strcat (foobar, ";");
-  fp = bp = foobar;
-
-  if (strchr (fp, ';') == strrchr (fp, ';'))
-    onlyonedir = 1;
-  else
-    onlyonedir = 0;
-
-  fixeddirs = strdup(".\\include");
-  origdirs = strdup("");
-
-  while (bp)
-    {
-      bp = strchr (fp, ';');
-      if (bp)
-        {
-          *bp = 0;
-          _stat (fp, &statbuf);
-          if (statbuf.st_mode & _S_IFDIR)
-            {
-              atleastone = 0;
-              if (onlyonedir) 
-                dodir (fp, ".");
-              else
-                dodir (fp, fp);
-              if (atleastone && !onlyonedir)
-                {
-                  origdirs = concat3 (origdirs, ";", fp);
-                  fixeddirs = concat3 (fixeddirs, ";", 
-                    concat3 (".\\include", "\\", newname(fp)));
-                }
-            }
-          fp = ++bp;
-        }
-    }
-  printf ("set C_Include_Path=%s%s\n", fixeddirs, origdirs);
-  return 0;
-}
-
-/* Utility function that mallocs space and concatenates two strings. */
-
-static char *
-concat (s1, s2)
-     char *s1, *s2;
-{
-  int len1 = strlen (s1);
-  int len2 = strlen (s2);
-  char *result = malloc (len1 + len2 + 1);
-
-  strcpy (result, s1);
-  strcpy (result + len1, s2);
-  *(result + len1 + len2) = 0;
-
-  return result;
-}
-
-/* Utility function that concatenates three strings. */
-
-static char *
-concat3 (s1, s2, s3)
-     char *s1, *s2, *s3;
-{
-  return concat (concat (s1, s2), s3);
-}
-
-/* Utility function that concatenates four strings. */
-
-static char *
-concat4 (s1, s2, s3, s4)
-     char *s1, *s2, *s3, *s4;
-{
-  return concat (concat (s1, s2), concat (s3, s4));
-}
diff --git a/gcc/config/winnt/headers.mak b/gcc/config/winnt/headers.mak
deleted file mode 100755
index 8dec341..0000000
--- a/gcc/config/winnt/headers.mak
+++ /dev/null
@@ -1,51 +0,0 @@
-# Build the include directory.  The stamp files are stmp-* rather than
-# stamp-* so that mostlyclean does not force the include directory to
-# be rebuilt.
-
-
-# Copy in the headers provided with gcc.
-USER_H = $(srcdir)\ginclude\stdarg.h $(srcdir)\ginclude\stddef.h \
-    $(srcdir)\ginclude\varargs.h $(srcdir)\ginclude\va-alpha.h \
-    $(srcdir)\ginclude\va-h8300.h $(srcdir)\ginclude\va-i860.h \
-    $(srcdir)\ginclude\va-i960.h $(srcdir)\ginclude\va-mips.h \
-    $(srcdir)\ginclude\va-m88k.h $(srcdir)\ginclude\va-pa.h \
-    $(srcdir)\ginclude\va-pyr.h $(srcdir)\ginclude\va-sparc.h \
-    $(srcdir)\ginclude\va-clipper.h $(srcdir)\ginclude\va-spur.h \
-    $(srcdir)\ginclude\iso646.h \
-    $(srcdir)\ginclude\proto.h
-
-# Build the include directory except for float.h (which depends upon
-# enquire).
-
-stmp-int-hdrs: $(USER_H)
-	type $(srcdir)\limitx.h >xlimits.h
-	type $(srcdir)\glimits.h >>xlimits.h
-	type $(srcdir)\limity.h >>xlimits.h
-
-	-mkdir include	
-	for %%f in ($(USER_H)) do copy %%f include
-	del include\limits.h
-	copy xlimits.h include\limits.h
-	del include\syslimits.h
-	copy $(srcdir)\gsyslimits.h include\syslimits.h
-	copy include\limits.h include\syslimits.h
-	del include\README
-	copy $(srcdir)\README-fixinc include\README
-	touch stmp-int-hdrs
-
-stmp-headers: stmp-int-hdrs fixinc-nt.exe
-	fixinc-nt
-	touch stmp-headers
-
-# Build float.h.
-stmp-float_h: libgcc.lib enquire.exe
-	-.\enquire -f > tmp-float.h
-	del include\float.h
-	copy tmp-float.h include\float.h
-	touch stmp-float_h
-
-fixinc-nt.obj: $(srcdir)/config/winnt/fixinc-nt.c
-	cl -c -I. -I$(srcdir) -I$(srcdir)/include -I$(srcdir)/config/winnt $(srcdir)/config/winnt/fixinc-nt.c
-
-fixinc-nt.exe: fixinc-nt.obj dirent.obj
-	cl fixinc-nt.obj dirent.obj libc.lib kernel32.lib
diff --git a/gcc/config/winnt/ld.c b/gcc/config/winnt/ld.c
deleted file mode 100755
index 67d53e7..0000000
--- a/gcc/config/winnt/ld.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/* Call Windows NT 3.x linker.
-   Copyright (C) 1994, 1995 Free Software Foundation, Inc.
-   Contributed by Douglas B. Rupp (drupp@cs.washington.edu).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "config.h"
-#include <stdio.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <stdlib.h>
-#include <string.h>
-#include <process.h>
-
-static char *concat ();
-static char *concat3 ();
-
-/* These can be set by command line arguments */
-char *linker_path = 0;
-int verbose = 0;
-int subsystem = 0;
-int entry = 0;
-
-int link_arg_max = -1;
-char **link_args = (char **) 0;
-int link_arg_index = -1;
-
-char *search_dirs = ".";
-
-static int is_regular_file (char *name);
-
-/* Add the argument contained in STR to the list of arguments to pass to the
-   linker */
-
-static void
-addarg (str)
-     char *str;
-{
-  int i;
-
-  if (++link_arg_index >= link_arg_max)
-    {
-      char **new_link_args
-	= (char **) calloc (link_arg_max + 1000, sizeof (char *));
-
-      for (i = 0; i <= link_arg_max; i++)
-	new_link_args [i] = link_args [i];
-
-      if (link_args)
-	free (link_args);
-
-      link_arg_max += 1000;
-      link_args = new_link_args;
-    }
-
-  link_args [link_arg_index] = str;
-}
-
-/* Locate the file named in FILE_NAME in the set of paths contained in
-   PATH_VAL */
-
-static char *
-locate_file (file_name, path_val)
-     char *file_name;
-     char *path_val;
-{
-  char buf [1000];
-  int file_len = strlen (file_name);
-  char *end_path = path_val + strlen (path_val);
-  char *ptr;
-
-  /* Handle absolute pathnames */
-  if (file_name [0] == '/' || file_name [0] == DIR_SEPARATOR
-      || isalpha (file_name [0]) && file_name [1] == ':')
-    {
-      strncpy (buf, file_name, sizeof buf);
-      buf[sizeof buf - 1] = '\0';
-      if (is_regular_file (buf))
-	return strdup (buf);
-      else
-	return 0;
-  }
-
-  if (! path_val)
-    return 0;
-
-  for (;;)
-    {
-      for (; *path_val == PATH_SEPARATOR ; path_val++)
-	;
-      if (! *path_val)
-	return 0;
-
-      for (ptr = buf; *path_val && *path_val != PATH_SEPARATOR; )
-	*ptr++ = *path_val++;
-
-      ptr--;
-      if (*ptr != '/' && *ptr != DIR_SEPARATOR)
-	*++ptr = DIR_SEPARATOR;
-
-      strcpy (++ptr, file_name);
-
-      if (is_regular_file (buf))
-	return strdup (buf);
-    }
-
-  return 0;
-}
-
-/* Given a library name in NAME, i.e. foo.  Look first for libfoo.lib and then
-   libfoo.a in the set of directories we are allowed to search in */
-
-static char *
-expand_lib (name)
-     char *name;
-{
-  char *lib, *lib_path;
-
-  lib = malloc (strlen (name) + 8);
-  strcpy (lib, "lib");
-  strcat (lib, name);
-  strcat (lib, ".lib");
-  lib_path = locate_file (lib, search_dirs);
-  if (!lib_path)
-    {
-      strcpy (lib, "lib");
-      strcat (lib, name);
-      strcat (lib, ".a");
-      lib_path = locate_file (lib, search_dirs);
-      if (!lib_path)
-        {
-          fprintf
-            (stderr, 
-             "Couldn't locate library: lib%s.a or lib%s.lib\n", name, name);
-          exit (1);
-        }
-    }
-
-  return lib_path;
-}
-
-/* Check to see if the file named in NAME is a regular file, i.e. not a
-   directory */
-
-static int
-is_regular_file (name)
-     char *name;
-{
-  int ret;
-  struct stat statbuf;
-
-  ret = stat(name, &statbuf);
-  return !ret && S_ISREG (statbuf.st_mode);
-}
-
-/* Process the number of args in P_ARGC and contained in ARGV.  Look for
-   special flags, etc. that must be handled for the Microsoft linker */
-
-static void
-process_args (p_argc, argv)
-     int *p_argc;
-     char *argv[];
-{
-  int i, j;
-
-  for (i = 1; i < *p_argc; i++)
-    {
-      /* -v turns on verbose option here and is passed on to gcc */
-      if (! strcmp (argv [i], "-v"))
-	verbose = 1;
-      else if (! strncmp (argv [i], "-g", 2))
-      {
-        addarg ("-debugtype:coff -debug:full");
-      }
-      else if (! strncmp (argv [i], "-stack", 6))
-      {
-        i++;
-        addarg (concat ("-stack:",argv[i]));
-      }
-      else if (! strncmp (argv [i], "-subsystem", 10))
-      {
-	subsystem = 1;
-        i++;
-        addarg (concat ("-subsystem:",argv[i]));
-      }
-      else if (! strncmp (argv [i], "-e", 2))
-      {
-	entry = 1;
-        i++;
-        addarg (concat ("-entry:",&argv[i][1]));
-      }
-    }
-}
-
-/* The main program.  Spawn the Microsoft linker after fixing up the
-   Unix-like flags and args to be what the Microsoft linker wants */
-
-main (argc, argv)
-     int argc;
-     char *argv[];
-{
-  int i;
-  int done_an_ali = 0;
-  int file_name_index;
-  char *pathval = getenv ("PATH");
-  char *spawn_args [5];
-  char *tmppathval = malloc (strlen (pathval) + 3);
-
-  strcpy (tmppathval, ".;");
-  pathval = strcat (tmppathval, pathval);
-
-  linker_path = locate_file ("link32.exe", pathval);
-  if (!linker_path)
-    {
-      linker_path = locate_file ("link.exe", pathval);
-      if (!linker_path)
-	{
-	  fprintf (stderr, "Couldn't locate link32 or link\n");
-	  exit (1);
-	}
-    }
-
-  addarg (linker_path);
-
-  process_args (&argc , argv);
-  if (! subsystem) addarg ("-subsystem:console");
-  if (! entry) addarg ("-entry:mainCRTStartup");
-
-  for (i = 1; i < argc; i++)
-    {
-      int arg_len = strlen (argv [i]);
-
-      if (!strcmp (argv [i], "-o"))
-	{
-	  char *buff, *ptr;
-	  int out_len;
-
-	  i++;
-	  out_len = strlen (argv[i]) + 10;
-	  buff = malloc (out_len);
-	  strcpy (buff, "-out:");
-	  strcat (buff, argv[i]);
-	  ptr = strstr (buff, ".exe");
-	  if (ptr == NULL || strlen (ptr) != 4)
-	    strcat (buff, ".exe");
-	  addarg (buff);
-	}
-      else if (arg_len > 2 && !strncmp (argv [i], "-L", 2))
-	{
-	  char *nbuff, *sdbuff;
-	  int j, new_len, search_dirs_len;
-
-	  new_len = strlen (&argv[i][2]);
-	  search_dirs_len = strlen (search_dirs);
-
-	  nbuff = malloc (new_len + 1);
-	  strcpy (nbuff, &argv[i][2]);
-
-	  for (j = 0; j < new_len; j++)
-	    if (nbuff[j] == '/') nbuff[j] = DIR_SEPARATOR;
-
-	  sdbuff = malloc (search_dirs_len + new_len + 2);
-	  strcpy (sdbuff, search_dirs);
-	  sdbuff[search_dirs_len] = PATH_SEPARATOR;
-	  sdbuff[search_dirs_len+1] = 0;
-	  strcat (sdbuff, nbuff);
-
-	  search_dirs = sdbuff;
-	}
-
-      else if (arg_len > 2 && !strncmp (argv [i], "-l", 2))
-        {
-	  addarg (expand_lib (&argv[i][2]));
-        }
-      else if (!strcmp (argv [i], "-v") 
-            || !strcmp (argv [i], "-g")
-            || !strcmp (argv [i], "-noinhibit-exec"))
-        {
-          ;
-        }
-      else if (!strcmp (argv [i], "-stack")
-            || !strcmp (argv [i], "-subsystem")
-            || !strcmp (argv [i], "-e"))
-        {
-          i++;
-        }
-      else
-        {
-          addarg (argv [i]);
-        }
-    }
-
-  addarg (NULL);
-
-  if (verbose)
-    {
-      int i;
-
-      for (i = 0; i < link_arg_index; i++)
-	printf ("%s ", link_args [i]);
-      putchar ('\n');
-    }
-
-  if (spawnvp (P_WAIT, linker_path, (const char * const *)link_args) != 0)
-    {
-      fprintf (stderr, "Error executing %s\n", link_args[0]);
-      exit (1);
-    }
-
-  exit (0);
-}
-
-static char *
-concat (s1, s2)
-     char *s1, *s2;
-{
-  int len1 = strlen (s1);
-  int len2 = strlen (s2);
-  char *result = malloc (len1 + len2 + 1);
-
-  strcpy (result, s1);
-  strcpy (result + len1, s2);
-  *(result + len1 + len2) = 0;
-
-  return result;
-}
-
-static char *
-concat3 (s1, s2, s3)
-     char *s1, *s2, *s3;
-{
-  return concat (concat (s1, s2), s3);
-}
diff --git a/gcc/config/winnt/libgcc.mak b/gcc/config/winnt/libgcc.mak
deleted file mode 100755
index adfb57e..0000000
--- a/gcc/config/winnt/libgcc.mak
+++ /dev/null
@@ -1,19 +0,0 @@
-# Build libgcc.a
-
-libgcc.lib : libgcc1.c libgcc2.c mklibgcc.exe
-	mklibgcc -c
-	mklibgcc "cl -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES)" libgcc1.c $(LIB1FUNCS)
-	mklibgcc "xgcc -B./ -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES)" libgcc2.c $(LIB2FUNCS)
-	mklibnow.bat
-	-del libgcc.lib
-	lib -verbose -out:libgcc.lib lgcctmp/*.obj
-
-mklibgcc.obj : $(srcdir)/config/winnt/mklibgcc.c
-	cl -I. -I$(srcdir) -I$(srcdir)/config/winnt -c $(srcdir)/config/winnt/mklibgcc.c
-
-dirent.obj : $(srcdir)/config/winnt/dirent.c stmp-int-hdrs
-	cl -I. -I$(srcdir) -I$(srcdir)/include -I$(srcdir)/config/winnt -c $(srcdir)/config/winnt/dirent.c
-
-mklibgcc.exe : mklibgcc.obj dirent.obj
-	cl mklibgcc.obj dirent.obj libc.lib kernel32.lib
-
diff --git a/gcc/config/winnt/mklibgcc.c b/gcc/config/winnt/mklibgcc.c
deleted file mode 100755
index 081e4ec..0000000
--- a/gcc/config/winnt/mklibgcc.c
+++ /dev/null
@@ -1,97 +0,0 @@
-#include <stdio.h>
-#include <string.h>
-#include <dirent.h>
-
-char *skips[] = {
-  0
-};
-
-int
-do_clean()
-{
-  DIR *dir;
-  struct dirent *de;
-  remove("mklibnow.bat");
-
-  dir = opendir("lgcctmp");
-  if (!dir)
-    return 0;
-  while ((de=readdir(dir)))
-    {
-      char buf[30];
-      if (de->d_name[0] == '.')
-        continue;
-      sprintf(buf, "lgcctmp/%s", de->d_name);
-      unlink(buf);
-    }
-  closedir(dir);
-  return 0;
-}
-
-int
-main(int argc, char **argv)
-{
-  char *cc = argv[1];
-  char *csrc=argv[2];
-  int i;
-  FILE *batfile;
-  FILE *cfile;
-
-  if (argc > 1 && strcmp(argv[1], "-c")==0)
-    return do_clean();
-
-  _mkdir("lgcctmp", 0755);
-
-  batfile = fopen("mklibnow.bat", "a");
-  if (!batfile)
-    {
-      perror("mklibnow.bat");
-      return 1;
-    }
-/*  fprintf(batfile, "@echo off\n"); */
-
-  for (i=3; i<argc; i++)
-    {
-      char dirname[30], basename[30], fullname[30], *bp;
-      int s;
-      for (s=0; skips[s]; s++)
-        if (strcmp(skips[s], argv[i]) == 0)
-  	break;
-      if (skips[s])
-        continue;
-      strcpy(dirname, "lgcctmp/");
-      strcpy(basename, "\0");
-      if (strncmp(argv[i], "_fix", 4)==0)
-        {
-          strcat(basename, "fx");
-          strcat(basename, argv[i]+4);
-        }
-      else if (strncmp(argv[i], "_float", 4)==0)
-        {
-          strcat(basename, "flt");
-          strcat(basename, argv[i]+6);
-        }
-      else
-        {
-          strcat(basename, argv[i]);
-        }
-      strcpy (fullname, dirname);
-      strcat (fullname, basename);
-      fprintf(batfile, "%s -c lgcctmp/%s.c\n", cc, basename);
-      fprintf(batfile, "copy %s.obj lgcctmp\n", basename);
-      bp = fullname + strlen(fullname);
-      strcpy(bp, ".c");
-      cfile = fopen(fullname, "w");
-      if (cfile)
-        {
-          *bp = 0;
-          fprintf(cfile, "#define L%s\n#include \"%s\"\n", argv[i], csrc);
-          fclose(cfile);
-        }
-      else
-        perror(fullname);
-    }
-
-  fclose(batfile);
-  return 0;
-}
diff --git a/gcc/config/winnt/oldnames.c b/gcc/config/winnt/oldnames.c
deleted file mode 100755
index b7a1779..0000000
--- a/gcc/config/winnt/oldnames.c
+++ /dev/null
@@ -1,47 +0,0 @@
-int
-access (const char *path, int mode)
-{
-  return _access (path, mode);
-}
-
-int
-chmod (const char *filename, int pmode)
-{
-  return _chmod (filename, pmode);
-}
-
-int
-close (int handle)
-{
-  return _close (handle);
-}
-
-char *
-mktemp (char *template)
-{
-   return (char *) _mktemp (template);
-}
-
-int
-open (const char *filename, int oflag, int pmode)
-{
-  return _open (filename, oflag, pmode);
-} 
-
-int
-read (int handle, void *buffer, unsigned int count)
-{
-  return _read (handle, buffer, count);
-}
-
-int
-unlink (const char *path)
-{
-  return _unlink (path);
-}
-
-int
-write (int handle, void *buffer, unsigned int count)
-{
-  return _write (handle, buffer, count);
-}
diff --git a/gcc/config/winnt/spawnv.c b/gcc/config/winnt/spawnv.c
deleted file mode 100755
index 49096af..0000000
--- a/gcc/config/winnt/spawnv.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* This is a kludge to get around the Microsoft C spawn functions' propensity
-   to remove the outermost set of double quotes from all arguments.  */
-
-#define index(s,c) strchr((s),(c))
-
-extern char *malloc ();
-
-const char * const *
-fix_argv (argv)
-  char **argv;
-{
-  static char sh_chars[] = "\"";
-
-  int i, len;
-  char *new_argv;
-  char *p, *ap;
-
-  for (i=1; argv[i]; i++)
-    {
-
-      len = strlen (argv[i]);
-      new_argv = malloc (2*len+3);
-      ap = new_argv;
-
-      for (p = argv[i]; *p != '\0'; ++p)
-        {
-          if (index (sh_chars, *p) != 0)
-            *ap++ = '\\';
-          *ap++ = *p;
-        }
-      *ap = '\0';
-      argv[i] = new_argv;
-    }
-
-  return (const char * const *) argv;
-}
-
-int __spawnv (mode, cmdname, argv)
-  int mode;
-  const char *cmdname;
-  char **argv;
-{
-  _spawnv (mode, cmdname, fix_argv (argv));
-}
-
-int __spawnvp (mode, cmdname, argv)
-  int mode;
-  const char *cmdname;
-  char **argv;
-{
-  _spawnvp (mode, cmdname, fix_argv (argv));
-}
-
-int spawnve (mode, cmdname, argv, envp)
-  int mode;
-  const char *cmdname;
-  char **argv;
-  const char *const *envp;
-{
-  _spawnve (mode, cmdname, fix_argv (argv), envp);
-}
-
-int __spawnvpe (mode, cmdname, argv, envp)
-  int mode;
-  const char *cmdname;
-  char **argv;
-  const char *const *envp;
-{
-  _spawnvpe (mode, cmdname, fix_argv (argv), envp);
-}
-
diff --git a/gcc/config/winnt/win-nt.h b/gcc/config/winnt/win-nt.h
deleted file mode 100755
index f123b04..0000000
--- a/gcc/config/winnt/win-nt.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Operating system specific defines to be used when targeting GCC for
-   Windows NT 3.x.
-   Copyright (C) 1994, 1995, 1997 Free Software Foundation, Inc.
-   Contributed by Douglas B. Rupp (drupp@cs.washington.edu).
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define TARGET_MEM_FUNCTIONS
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC ""
-
-#undef LINK_SPEC
-#define LINK_SPEC "-stack 5000000,5000000 -noinhibit-exec %{g}"
-
-#undef CPP_SPEC
-#define CPP_SPEC ""
-
-#undef STANDARD_EXEC_PREFIX
-#define STANDARD_EXEC_PREFIX ""
-
-#undef STANDARD_STARTFILE_PREFIX
-#define STANDARD_STARTFILE_PREFIX ""
-
-#undef TOOLDIR_BASE_PREFIX
-#define TOOLDIR_BASE_PREFIX ""
-
-#ifdef STANDARD_INCLUDE_DIR
-#undef STANDARD_INCLUDE_DIR
-#endif
-#define STANDARD_INCLUDE_DIR ""
-
-#undef LOCAL_INCLUDE_DIR
-#define LOCAL_INCLUDE_DIR ""
-
-#undef INCLUDE_DEFAULTS
-#define INCLUDE_DEFAULTS				\
-  {							\
-    { 0, 0, 0, 0 }						\
-  }
-
-#undef STDC_VALUE
-#define STDC_VALUE 0
-
-/* Enable parsing of #pragma pack(push,<n>) and #pragma pack(pop).  */
-#define HANDLE_PRAGMA_PACK_PUSH_POP 1
diff --git a/gcc/config/winnt/x-winnt b/gcc/config/winnt/x-winnt
deleted file mode 100755
index 36e36b9..0000000
--- a/gcc/config/winnt/x-winnt
+++ /dev/null
@@ -1,34 +0,0 @@
-STMP_FIXPROTO =
-OTHER_FIXINCLUDES_DIRS=${srcdir}
-RANLIB = :
-RANLIB_TEST = false
-OLDCC = cl
-MAKE = make
-SHELL = sh
-SYMLINK = cp
-INSTALL = $(srcdir)/install.sh -c
-.SUFFIXES: .obj
-.c.obj:
-	$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
-.adb.obj:
-	$(CC) -c $(ALL_ADAFLAGS) $<
-.ads.obj:
-	$(CC) -c $(ALL_ADAFLAGS) $<
-exeext = .exe
-objext = .obj
-
-CC = gcc
-CLIB = 
-LDFLAGS = 
-
-ld.o: $(srcdir)/config/winnt/ld.c
-	$(CC) -I. -I$(srcdir) -I$(srcdir)/config -c $(srcdir)/config/winnt/ld.c
- 
-ld.exe: ld.o
-	$(CC) -o ld.exe ld.o
-
-oldnames.o: $(srcdir)/config/winnt/oldnames.c
-	$(CC) -I. -I$(srcdir) -I$(srcdir)/config -c $(srcdir)/config/winnt/oldnames.c
-
-spawnv.o: $(srcdir)/config/winnt/spawnv.c
-	$(CC) -I. -I$(srcdir) -I$(srcdir)/config -c $(srcdir)/config/winnt/spawnv.c
diff --git a/gcc/config/winnt/xm-winnt.h b/gcc/config/winnt/xm-winnt.h
deleted file mode 100755
index f56073c..0000000
--- a/gcc/config/winnt/xm-winnt.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Configuration for GNU compiler for processor running Windows NT 3.x.
-   Copyright (C) 1993, 1995, 1997 Free Software Foundation, Inc.
-   Contributed by Douglas B. Rupp (drupp@cs.washington.edu)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include <stdlib.h>
-
-#ifndef USG
-#define USG 1
-#endif
-
-#ifndef ONLY_INT_FIELD
-#define ONLY_INT_FIELDS 1
-#endif
-
-#ifndef USE_PROTOTYPES
-#define USE_PROTOTYPES 1
-#endif
-
-#ifndef HAVE_PUTENV
-#define HAVE_PUTENV 1
-#endif
-
-#ifndef HAVE_VPRINTF
-#define HAVE_VPRINTF 1
-#endif
-
-#define NO_SYS_SIGLIST 1
-#define kill(a,b) raise(b)
-
-#define OBJECT_SUFFIX ".obj"
-#define EXECUTABLE_SUFFIX ".exe"
-#define PATH_SEPARATOR ';'
-#define DIR_SEPARATOR '\\'
-
-#define S_IRUSR 0000400
-#define S_IWUSR 0000200
-#define S_IXUSR 0000100
-#define S_IRGRP 0000040
-#define S_IWGRP 0000020
-#define S_IXGRP 0000010
-#define S_IROTH 0000004
-#define S_IWOTH 0000002
-#define S_IXOTH 0000001
-#define S_IRWXU S_IRUSR | S_IWUSR | S_IXUSR
-#define S_ISREG(m) (((m)&S_IFMT) == S_IFREG)
-#define S_ISDIR(m) (((m)&S_IFMT) == S_IFDIR)
diff --git a/gcc/config/x-linux b/gcc/config/x-linux
deleted file mode 100755
index a7c0917..0000000
--- a/gcc/config/x-linux
+++ /dev/null
@@ -1,5 +0,0 @@
-# Don't run fixproto
-STMP_FIXPROTO =
-
-# Don't install "assert.h" in gcc. We use the one in glibc.
-INSTALL_ASSERT_H =
diff --git a/gcc/config/x-linux-aout b/gcc/config/x-linux-aout
deleted file mode 100755
index 36ae68a..0000000
--- a/gcc/config/x-linux-aout
+++ /dev/null
@@ -1,14 +0,0 @@
-# It is defined in config/xm-linux.h.
-# X_CFLAGS = -DPOSIX
-
-# The following is needed when compiling stages 2 and 3 because gcc's
-# limits.h must be picked up before /usr/include/limits.h.  This is because
-# each does an #include_next of the other if the other hasn't been included.
-# /usr/include/limits.h loses if it gets found first because /usr/include is
-# at the end of the search order.  When a new version of gcc is released,
-# gcc's limits.h hasn't been installed yet and hence isn't found.
-
-# BOOT_CFLAGS = -O $(CFLAGS) -Iinclude
-
-# Don't run fixproto
-# STMP_FIXPROTO =
diff --git a/gcc/config/x-lynx b/gcc/config/x-lynx
deleted file mode 100755
index 0be03e4..0000000
--- a/gcc/config/x-lynx
+++ /dev/null
@@ -1,6 +0,0 @@
-# /bin/cc is hopelessly broken, so we must use /bin/gcc instead.
-CC	= $(OLDCC)
-OLDCC	= /bin/gcc
-
-# /bin/sh is too buggy, so use /bin/bash instead.
-SHELL = /bin/bash
diff --git a/gcc/config/x-svr4 b/gcc/config/x-svr4
deleted file mode 100755
index 9c70543..0000000
--- a/gcc/config/x-svr4
+++ /dev/null
@@ -1,9 +0,0 @@
-# Some versions of SVR4 have an alloca in /usr/ucblib/libucb.a, and if we are
-# careful to link that in after libc we can use it, but since newer versions of
-# SVR4 are dropping libucb, it is better to just use the portable C version for
-# bootstrapping.  Do this by defining ALLOCA.
-
-ALLOCA = alloca.o
-
-# See all the declarations.
-FIXPROTO_DEFINES = -D_XOPEN_SOURCE
diff --git a/gcc/config/xm-alloca.h b/gcc/config/xm-alloca.h
deleted file mode 100755
index 3dbdc37..0000000
--- a/gcc/config/xm-alloca.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/* If not compiled with GNU C, use the portable alloca.  */
-#ifndef __GNUC__
-#define USE_C_ALLOCA
-#endif
diff --git a/gcc/config/xm-freebsd.h b/gcc/config/xm-freebsd.h
deleted file mode 100755
index b71ff56..0000000
--- a/gcc/config/xm-freebsd.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Configuration for GNU C-compiler for hosts running FreeBSD.
-   Copyright (C) 1994, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file defines machine-independent things specific to a host
-   running FreeBSD.  This file should not be specified as $xm_file itself;
-   instead $xm_file should be CPU/xm-freebsd.h, which should include both
-   CPU/xm-CPU.h and this file xm-freebsd.h.  */
diff --git a/gcc/config/xm-gnu.h b/gcc/config/xm-gnu.h
deleted file mode 100755
index 64e8e2f..0000000
--- a/gcc/config/xm-gnu.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Configuration for GNU C-compiler for hosts running GNU.
-   Copyright (C) 1994, 1995, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file defines machine-independent things specific to a host
-   running GNU.  This file should not be specified as $xm_file itself;
-   instead $xm_file should be CPU/xm-gnu.h, which should include both
-   CPU/xm-CPU.h and this file xm-gnu.h.  */
-
-#define POSIX			/* GNU complies to POSIX.1.  */
-
-#ifndef inhibit_libc
-/* Get a definition of O_RDONLY; some of the GCC files don't include this
-   properly and will define it themselves to be zero. */
-#include <fcntl.h>
-#endif
diff --git a/gcc/config/xm-linux.h b/gcc/config/xm-linux.h
deleted file mode 100755
index 2cffdb7..0000000
--- a/gcc/config/xm-linux.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Configuration for GCC for Intel i386 running Linux-based GNU systems.
-   Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc.
-   Contributed by H.J. Lu (hjl@nynexst.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#undef  HAVE_ATEXIT
-#define HAVE_ATEXIT
-
-#undef  POSIX
-#define POSIX
-
-/* We do have one, but I'd like to use the one come with gcc since
-   we have been doing that for a long time with USG defined.  H.J. */
-#undef HAVE_STAB_H
-
-#undef BSTRING
-#define BSTRING
diff --git a/gcc/config/xm-netbsd.h b/gcc/config/xm-netbsd.h
deleted file mode 100755
index 099a923..0000000
--- a/gcc/config/xm-netbsd.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Configuration for GNU C-compiler for hosts running NetBSD.
-   Copyright (C) 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* This file defines machine-independent things specific to a host
-   running NetBSD.  This file should not be specified as $xm_file itself;
-   instead $xm_file should be CPU/xm-netbsd.h, which should include both
-   CPU/xm-CPU.h and this file xm-netbsd.h.  */
-   
-#define HAVE_VPRINTF
diff --git a/gcc/config/xm-siglist.h b/gcc/config/xm-siglist.h
deleted file mode 100755
index d6133d6..0000000
--- a/gcc/config/xm-siglist.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Some systems provide no sys_siglist, but do offer the same data under
-   another name.  */
-
-#define sys_siglist _sys_siglist
-#undef SYS_SIGLIST_DECLARED
-#define SYS_SIGLIST_DECLARED
diff --git a/gcc/config/xm-std32.h b/gcc/config/xm-std32.h
deleted file mode 100755
index c52782e..0000000
--- a/gcc/config/xm-std32.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Configuration for GNU C-compiler for standard 32-bit host machine.
-   Copyright (C) 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 32
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
diff --git a/gcc/config/xm-svr3.h b/gcc/config/xm-svr3.h
deleted file mode 100755
index 6f25250..0000000
--- a/gcc/config/xm-svr3.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Configuration for GNU C-compiler for hosts running System V Release 3
-   Copyright (C) 1991, 1993, 1996 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define USG
-
-#ifndef SVR3
-#define SVR3
-#endif
diff --git a/gcc/config/xm-svr4.h b/gcc/config/xm-svr4.h
deleted file mode 100755
index 8534aaa..0000000
--- a/gcc/config/xm-svr4.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Configuration for GNU C-compiler for hosts running System V Release 4
-   Copyright (C) 1988, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define USG
-
-#define POSIX
-
-/* SVR4 provides no sys_siglist,
-   but does offer the same data under another name.  */
-#define sys_siglist _sys_siglist
-#undef SYS_SIGLIST_DECLARED
-#define SYS_SIGLIST_DECLARED
diff --git a/gcc/config/z8k/lib2funcs.c b/gcc/config/z8k/lib2funcs.c
deleted file mode 100755
index 8b436c7..0000000
--- a/gcc/config/z8k/lib2funcs.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License as published by the
-Free Software Foundation; either version 2, or (at your option) any
-later version.
-
-In addition to the permissions in the GNU General Public License, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file with other programs, and to distribute
-those programs without any restriction coming from the use of this
-file.  (The General Public License restrictions do apply in other
-respects; for example, they cover modification of the file, and
-distribution when not linked into another program.)
-
-This file is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, if you link this library with other files,
-   some of which are compiled with GCC, to produce an executable,
-   this library does not by itself cause the resulting executable
-   to be covered by the GNU General Public License.
-   This exception does not however invalidate any other reasons why
-   the executable file might be covered by the GNU General Public License.  */
-
-
-/* This file overrides some functions defined in libgcc2.c, and implements
-   simpler forms of the routines.  The z8k is so limited that I can get
-   faster code using less smart algorithms.. */
-
-
-#define divnorm(num, den, sign) 		\
-{						\
-  if (num < 0) 					\
-    {						\
-      num = -num;				\
-      sign = 1;					\
-    }						\
-  else 						\
-    {						\
-      sign = 0;					\
-    }						\
-						\
-  if (den < 0) 					\
-    {						\
-      den = - den;				\
-      sign = 1 - sign;				\
-    } 						\
-}
-
-
-
-
-
-static unsigned long 
-divmodsi4(int modwanted, unsigned long num, unsigned long den)	
-{						
-  unsigned long int bit = 1;				
-  long int res = 0;				
-  long prevden;
-  while (den < num && bit && !(den & (1L<<31)))			       
-    {
-      den <<=1;					
-      bit <<=1;					
-    }						
-  while (bit)
-    {					
-      if (num >= den)
-	{				
-	  num -= den;				
-	  res |= bit;				
-	}						
-      bit >>=1;					
-      den >>=1;					
-    }						
-  if (modwanted) return num;
-  return res;
-}
-
-
-
-
-
-long 
-__umodsi3 (unsigned long numerator, unsigned long denominator)
-{
-  long dividend;
-  long modul;
-
-  modul= divmodsi4 (1,  numerator, denominator);
-  return modul;
-}
-
-long 
-__udivsi3 (unsigned long numerator, unsigned long denominator)
-{
-  int sign;
-  long dividend;
-  long modul;
-  dividend =   divmodsi4 (0, numerator, denominator);
-  return dividend;
-}
-
diff --git a/gcc/config/z8k/t-z8k b/gcc/config/z8k/t-z8k
deleted file mode 100755
index 8b7b6aa..0000000
--- a/gcc/config/z8k/t-z8k
+++ /dev/null
@@ -1,26 +0,0 @@
-CROSS_LIBGCC1 = libgcc1.null
-TARGET_LIBGCC2_CFLAGS = -DCMPtype=HItype
-LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c $(srcdir)/config/z8k/lib2funcs.c
-
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#define NO_NANS' >> fp-bit.c
-	echo '#define SMALL_MACHINE' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define SMALL_MACHINE' > dp-bit.c
-	echo '#define NO_DI_MODE' >> dp-bit.c
-	echo '#define NO_NANS' >>dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-
-RUNTEST_CFLAGS = -B$$rootme/../newlib/ -L$$rootme/../newlib
-
-MULTILIB_OPTIONS = mz8001 mstd
-MULTILIB_DIRNAMES = z8001 std
-
-LIBGCC = stmp-multilib
-INSTALL_LIBGCC = install-multilib
-
diff --git a/gcc/config/z8k/xm-z8k.h b/gcc/config/z8k/xm-z8k.h
deleted file mode 100755
index 74ed36b..0000000
--- a/gcc/config/z8k/xm-z8k.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Configuration for GNU C-compiler for Z8000
-   Copyright (C) 1987 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-/* #defines that need visibility everywhere.  */
-#define FALSE 0
-#define TRUE 1
-
-/* This describes the machine the compiler is hosted on.  */
-#define HOST_BITS_PER_CHAR 8
-#define HOST_BITS_PER_SHORT 16
-#define HOST_BITS_PER_INT 16
-#define HOST_BITS_PER_LONG 32
-#define HOST_BITS_PER_LONGLONG 64
-
-/* Arguments to use with `exit'.  */
-#define SUCCESS_EXIT_CODE 0
-#define FATAL_EXIT_CODE 33
-
-/* If compiled with GNU C, use the built-in alloca */
-#ifdef __GNUC__
-#define alloca __builtin_alloca
-#else
-#define USE_C_ALLOCA
-#endif
-
-/* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
-#include "tm.h"
-
-
diff --git a/gcc/config/z8k/z8k.c b/gcc/config/z8k/z8k.c
deleted file mode 100755
index 477c97e..0000000
--- a/gcc/config/z8k/z8k.c
+++ /dev/null
@@ -1,2910 +0,0 @@
-/* Subroutines for insn-output.c for the Zilog Z8000
-   Copyright (C) 1993, 1994 Free Software Foundation, Inc.
-
-   Written by Steve Chamberlain (sac@cygnus.com)
-
-   This file is part of GNU CC.
-
-   GNU CC is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GNU CC is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GNU CC; see the file COPYING.  If not, write to
-   the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#include <stdio.h>
-#include <string.h>
-#include "config.h"
-#include "rtl.h"
-#include "regs.h"
-#include "hard-reg-set.h"
-#include "real.h"
-#include "insn-config.h"
-#include "conditions.h"
-#include "insn-flags.h"
-#include "output.h"
-#include "insn-attr.h"
-#include "tree.h"
-#include "flags.h"
-
-/* Modes ok for regs, used in tm.h for HARD_REGNO_MODE_OK */
-int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
-
-
-/* We can change which reg has the sp or fp, using this
-   to indirect */
-static int renumber[FIRST_PSEUDO_REGISTER];      
-static int rev_renumber[FIRST_PSEUDO_REGISTER];      
-
-
-/* If these are ever reversed, then things will have to change, call.c
-   assumes that args go in regs in increasing regno order */
-
-#define ARG_REGS "r2,r3,r4,r5,r6,r7"	/* Default -margs-in */
-
-/* Number of HI regs used for arg passing, can be changed on the
-   command line (-margs-in) */
-
-int arg_nregs;
-
-/* Regs  for arg passing */
-int arg_regs[FIRST_PSEUDO_REGISTER];
-
-/* And their order */
-int arg_regs_order[FIRST_PSEUDO_REGISTER];
-
-extern int frame_pointer_needed;
-#define pic_reg    (gen_rtx(REG, HImode, 13))
-
-struct reg_info_struct
-  {
-    char *mode_name[MAX_MACHINE_MODE];
-  };
-
-struct reg_info_struct rinfo[FIRST_PSEUDO_REGISTER];
-
-#define regname(x,mode)  (rinfo[renumber[x]].mode_name[mode])
-
-char *pointer_reg[FIRST_PSEUDO_REGISTER];
-
-#define STACK_REGISTER(x) \
-  ((x)==STACK_POINTER_REGNUM || (frame_pointer_needed && (x) == FRAME_POINTER_REGNUM))
-
-/* kludge - used if insn does ba bx set in ASM_OUTPUT_OPCODE if the
-   insn allows ba, bx addressing modes */
-
-static int can_ba_bx;
-
-int current_function_anonymous_args;
-
-/* Number of bytes pushed for anonymous args */
-
-static int extra_push;
-
-/* Linked list of all externals that are to be emitted if they haven't been
-   declared by the end of the program.  */
-
-struct extern_list
-  {
-    struct extern_list *next;
-    char *name;
-  }
- *extern_head = 0;
-
-rtx 
-getreg (x)
-     rtx x;
-{
-  if (GET_CODE (x) == TRUNCATE)
-    x = XEXP (x, 0);
-  if (GET_CODE (x) == SIGN_EXTEND)
-    x = XEXP (x, 0);
-  return x;
-}
-
-/* Print the operand address represented by the rtx addr */
-
-void
-print_operand_address (file, addr)
-     FILE *file;
-     register rtx addr;
-{
-  rtx lhs, rhs;
-
-retry:;
-
-  switch (GET_CODE (addr))
-    {
-    case MEM:
-      fprintf (file, "#");
-      addr = XEXP (addr, 0);
-      goto retry;
-
-    case REG:
-      fprintf (file, "@%s", pointer_reg[REGNO (addr)]);
-      break;
-
-    case PRE_DEC:
-      fprintf (file, "%s", pointer_reg[REGNO (XEXP (addr, 0))]);
-      break;
-    case POST_INC:
-      fprintf (file, "%s", pointer_reg[REGNO (XEXP (addr, 0))]);
-      break;
-    case PLUS:
-      lhs = XEXP (addr, 0);
-      rhs = XEXP (addr, 1);
-
-      if (GET_CODE (rhs) == REG
-	  && GET_CODE (lhs) != REG)
-	{
-	  rtx swap = lhs;
-	  lhs = rhs;
-	  rhs = swap;
-	}
-
-
-      if (GET_CODE (rhs) == SIGN_EXTEND
-	  || GET_CODE (rhs) == TRUNCATE)
-	{
-	  rtx swap = lhs;
-	  lhs = rhs;
-	  rhs = swap;
-	}
-
-      if (TARGET_BIG && (inside_ba_p (addr, 1)
-			 && (STACK_REGISTER (REGNO (lhs)) || can_ba_bx)
-			 && GET_CODE (rhs) == CONST_INT))
-	{
-	  int offset = INTVAL (rhs);
-	  if (REGNO (lhs) == STACK_POINTER_REGNUM && saved_reg_on_stack_hack)
-	    offset += 4;
-	  saved_reg_on_stack_hack = 0;
-	  fprintf (file, "%s(#", pointer_reg[REGNO (lhs)]);
-	  fprintf (file, "%d", offset);
-	  fprintf (file, ")");
-	}
-      else if (inside_bx_p (addr, 1)
-	       && (can_ba_bx || (STACK_REGISTER (REGNO (lhs)))))
-	{
-	  rtx base;
-	  rtx disp;
-
-	  if (GET_CODE (lhs) == REG)
-	    {
-	      base = lhs;
-	      disp = rhs;
-	    }
-	  else
-	    {
-	      base = rhs;
-	      disp = lhs;
-	    }
-	  fprintf (file, "%s(%s)", pointer_reg[REGNO (base)],
-		   regname(REGNO (getreg (disp)), HImode));
-	}
-      else if (inside_x_p (addr, 1))
-	{
-	  int r = REGNO (lhs);
-
-	  if (TARGET_BIG)
-	    {
-	      /* With a disp(reg) we only use the lsw, so
-		 inc the reg number */
-	      if (GET_MODE (lhs) == SImode || GET_MODE (lhs) == PSImode)
-		r++;
-	    }
-	  output_address (rhs);
-	  fprintf (file, "(%s)", regname(r,HImode));
-	}
-      else
-	{
-	  /* This must be an x_operand or a stack reg */
-	  output_address (rhs);
-	  fprintf (file, "(%s)",  regname(REGNO (lhs),HImode));
-
-	}
-      break;
-
-    default:
-      output_addr_const (file, addr);
-
-    }
-}
-
-
-
-void 
-maybe_need_resflg (cond)
-     rtx cond;
-{
-  int code = GET_CODE (cond);
-  if (cc_prev_status.flags & CC_NO_OVERFLOW
-      && (code == GT
-	  || code == LE))
-    {
-      fprintf (asm_out_file, "\tresflg	v\n");
-    }
-}
-
-/* Turn a condition code into a string */
-static char *
-cond_name_x (code)
-     int code;
-{
-  if (cc_prev_status.flags & CC_NO_OVERFLOW)
-    {
-      switch (code)
-	{
-	case LT:
-	  return "mi";
-	case GE:
-	  return "pl";
-	  /* The others V testers are handled by clearing V before the jump */
-	}
-    }
-  switch (code)
-    {
-    case EQ:
-      return "eq";
-    case NE:
-      return "ne";
-    case LT:
-      return "lt";
-    case LE:
-      return "le";
-    case GT:
-      return "gt";
-    case GE:
-      return "ge";
-    case LTU:
-      return "ult";
-    case LEU:
-      return "ule";
-    case GTU:
-      return "ugt";
-    case GEU:
-      return "uge";
-    default:
-      abort ();
-    }
-}
-
-
-/* print either an inc or an add depending upon the size of the value */
-
-static void
-incordec (file, n1, n2, size)
-     FILE *file;
-     char *n1;
-     char *n2;
-     int size;
-{
-  if (size)
-    {
-      fprintf (file, "\t%s\tr15,#%d\n",
-	       size > 16 ? n1 : n2, size);
-    }
-}
-
-
-#define frameish(x) ((x ==  FRAME_POINTER_REGNUM) || (x == FRAME_POINTER_REGNUM+1))
-
-/* return 1 if the register needs to be saved on function entry */
-
-static int
-need (regno)
-     int regno;
-{
-  if (TARGET_BIG && regno == STACK_POINTER_REGNUM)
-    return 0;
-
-  return (regs_ever_live[regno]
-	  && !call_used_regs[regno]
-	  && regno < STACK_POINTER_REGNUM
-	  && !((regno == FRAME_POINTER_REGNUM)
-	   || (regno == FRAME_POINTER_REGNUM + 1) && frame_pointer_needed));
-
-}
-
-
-
-
-/* return non zero if the rtx supplied can be used as an effective
-   address calculation */
-
-static int 
-address (op)
-     rtx op;
-{
-  if (GET_CODE (op) == CONST)
-    op = XEXP (op, 0);
-
-  if (TARGET_SMALL && GET_CODE (op) == CONST_INT)
-    return 1;
-
-  if (GET_MODE (op) != Pmode)
-    return 0;
-
-  /* + (symbol_ref, foo) is address */
-  if (GET_CODE (op) == PLUS && address (XEXP (op, 0)))
-    return 1;
-
-  if (GET_CODE (op) == SYMBOL_REF)
-    return 1;
-
-  if (GET_CODE (op) == LABEL_REF)
-    return 1;
-
-  return 0;
-}
-
-/*
-Use S for SI regs
-Use B & T for parts of DI regs
-  X  - stack pointer name
-  Registers
-  Q - byte sized register name
-  U - high byte of word register
-  V - low byte of word register
-  H - word register name
-  I - next word register name
-  S&B - long register name
-  T - next long register name
-  D - quad register name
-  P - register name in size of pointer
-  Integers
-  O - log two of value
-  P - inverted log two
-  H - bottom 16 bits
-  I - top 16 bits
-  N - negative
-  B - high 32 bits of 32bit number.
-  default:  value
-  Memory
-  I - adjusted upwards by two
-  T - adjusted upwards by four
-  default:  value
-  Address
-  H - low 16 bits
-  I - high 16 bits
-  A - as long constant
-  S - as A but with #
-  default: error
-  Misc
-  C - conditional name
-  D - reverse conditional name
-  F - clear v flag if necessary
-  */
-
-
-void 
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
-{
-  if (code == '^')
-    {
-      static int lab;
-      fprintf (file, "%d", lab >> 1);
-      lab++;
-    }
-  else if (code == 'F')
-    {
-      if (cc_prev_status.flags & CC_NO_OVERFLOW)
-	{
-	  fprintf (file, "resflg	v\n\t");
-	}
-    }
-  else if (code == 'X')
-    {
-      fprintf (file, "%s", pointer_reg[STACK_POINTER_REGNUM]);
-    }
-  else
-    {
-      /* If reg, output byte reg */
-      if (GET_CODE (x) == REG)
-	{
-	  switch (code)
-	    {
-	    case 'Q':
-	      fprintf (file, "%s", regname (REGNO (x), QImode));
-	      break;
-	    case 'U':
-	      fprintf (file, "rh%d", REGNO (x));
-	      break;
-	    case 'V':
-	      fprintf (file, "rl%d", REGNO (x) + 1);
-	      break;
-
-	    default:
-	      fprintf (file, "r??%d", REGNO (x));
-	      break;
-	    case 'H':
-	      fprintf (file, "%s", regname (REGNO (x), HImode));
-	      break;
-	    case 'I':
-	      fprintf (file, "%s", regname (REGNO (x) + 1, HImode));
-	      break;
-	    case 'J':
-	      fprintf (file, "%s", regname (REGNO (x) + 2, HImode));
-	      break;
-	    case 'K':
-	      fprintf (file, "%s", regname (REGNO (x) + 3, HImode));
-	      break;
-	    case 'S':
-	    case 'B':
-	      fprintf (file, "%s", regname (REGNO (x), SImode));
-	      break;
-	    case 'T':
-	      fprintf (file, "%s", regname (REGNO (x) + 2, SImode));
-	      break;
-	    case 'D':
-	      fprintf (file, "%s", regname (REGNO (x), DImode));
-	      break;
-	    case 'P':
-	      fprintf (file, "%s", regname (REGNO (x), Pmode));
-	      break;
-	    }
-
-	}
-
-      else if (GET_CODE (x) == CONST_INT)
-	{
-	  switch (code)
-	    {
-	    case 'O':
-	      fprintf (file, "#%d", exact_log2 (INTVAL (x)));
-	      break;
-	    case 'P':
-	      fprintf (file, "#%d", exact_log2 (~(INTVAL (x) | ~0xffff)));
-	      break;
-	    case 'H':
-	      fprintf (file, "#%d", INTVAL (x) & 0xffff);
-	      break;
-	    case 'I':
-	      fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xffff);
-	      break;
-	    case 'N':
-	      fprintf (file, "#%d", -INTVAL (x));
-	      break;
-	    case 'B':
-	      {
-		HOST_WIDE_INT val = INTVAL (x);
-		if (sizeof (val) == 4)
-		  val = val < 0 ? -1 : 0;
-		else {
-		  /* only happens with 32 bit values, so even when 
-		     HOST_WIDE_INT is 32 bits long this is no error */
-		  val >>= 32; 
-		}
-		fprintf (file, "#%d", val);
-	      }
-	      break;
-	    default:
-	      fprintf (file, "#%d", INTVAL (x) & 0xffffffff);
-	      break;
-	    }
-	}
-      else if (GET_CODE (x) == MEM)
-	{
-	  if (code == 'I')
-	    {
-	      x = adj_offsettable_operand (x, 2);
-	    }
-	  else if (code == 'T')
-	    {
-	      x = adj_offsettable_operand (x, 4);
-	    }
-
-	  output_address (XEXP (x, 0));
-
-	}
-      else if (address (x))
-	{
-	  switch (code)
-	    {
-	    case 'H':
-	      if (TARGET_BIG)
-		{
-		  fprintf (file, "#low(");
-		  output_addr_const (file, x);
-		  fprintf (file, ")");
-		}
-	      else
-		{
-		  fprintf (file, "#");
-		  output_addr_const (file, x);
-		}
-	      break;
-
-	    case 'I':
-	      fprintf (file, "#high(");
-	      output_addr_const (file, x);
-	      fprintf (file, ")");
-	      break;
-	    case 'A':
-	      output_addr_const (file, x);
-	      break;
-	    case 'S':
-	      fprintf (file, "#");
-	      output_addr_const (file, x);
-	      break;
-	    default:
-	      fprintf (file, "#what%c", code);
-	      output_addr_const (file, x);
-	      break;
-	    }
-	}
-      else if (code == 'C')
-	{
-	  fprintf (file, cond_name_x (reverse_condition (GET_CODE (x))));
-	}
-      else if (code == 'D')
-	{
-	  fprintf (file, cond_name_x (GET_CODE (x)));
-	}
-      else if (GET_CODE (x) == CONST_DOUBLE)
-	{
-	  double d;
-	  REAL_VALUE_FROM_CONST_DOUBLE (d, x);
-	  fprintf (file, "#");
-	  ASM_OUTPUT_FLOAT (file, d);
-	}
-      else
-	{
-	  fprintf (file, "#");
-	  if (GET_CODE (x) == CONST)
-	    x = XEXP (x, 0);
-	  if (GET_CODE (x) == TRUNCATE)
-	    x = XEXP (x, 0);
-	  output_addr_const (file, x);
-	}
-    }
-}
-
-
-static
-int
-fill_from_options (value, def, string, into, order)
-     int value;
-     char *def;
-     char *string;
-     char *into;
-     int *order;
-{
-  int regno;
-  int n = 0;
-  char *p;
-  char *list;
-
-  list = p = string ? string : def;
-
-  while (*p)
-    {
-      if (*p == 'r')
-	{
-	  p++;
-	  if (p[0] == '1' && p[1] >= '0' && p[1] <= '5')
-	    {
-	      regno = 10 + p[1] - '0';
-	      p += 2;
-	    }
-	  else if (p[0] >= '0' && p[0] <= '9')
-	    {
-	      regno = p[0] - '0';
-	      p++;
-	    }
-	  else
-	    {
-	      error ("error in register list `%s'", list);
-	      return 0;
-	    }
-	  into[regno] = value;
-	  if (order)
-	    {
-	      order[n] = regno;
-	    }
-	  n++;
-
-	}
-      else if (*p == ',' || *p == '-')
-	{
-	  p++;
-	}
-      else
-	{
-	  error ("error in register list `%s'", list);
-	  return 0;
-	}
-    }
-  return n;
-}
-extern enum debug_info_type write_symbols;
-extern enum debug_info_level debug_info_level;
-extern int flag_caller_saves;
-
-void
-override_options ()
-{
-  int i;
-  int j;
-  
-  int nfakes;
-
-
-  if (TARGET_STD)
-    {
-      target_flags |= TARGET_STD_RET_BIT | TARGET_STD_FRAME_BIT;
-      target_flags &= ~TARGET_REGPARMS_BIT;
-    }
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    renumber[i] = i;
-
-  if (TARGET_BIG)
-    pmode = PSImode;
-  else
-    pmode = HImode;
-  if (TARGET_STD_FRAME)
-    flag_omit_frame_pointer = 0;
-
-
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      int mode_index;
-
-      for (mode_index = 0;
-	   mode_index <= (int) MAX_MACHINE_MODE;
-	   mode_index++)
-	{
-	  int bsize = GET_MODE_UNIT_SIZE ((enum machine_mode) mode_index);
-	  int or;
-
-	  if (bsize > 8)
-	    or = 0;
-	  else if (bsize == 8 && (i & 1))
-	    or = 0; 
-	  else if (bsize == 4 && (i & 1))
-	    or = 0;
-	  else
-	    or = 1;
-
-	  hard_regno_mode_ok[i] |= or << mode_index;
-	}
-    }
-
-  /* Call used - current scheme is all registers are trashed */
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    call_used_regs[i] = 1;
-
-  /* except for ones which are explicitly mention */
-  if (TARGET_BIG)
-    {
-      fill_from_options (0, "r8,r9,r10,r11,r12,r13", call_used_option, call_used_regs, 0);
-    }
-  else
-    {
-      fill_from_options (0, "r8,r9,r10,r11,r12,r13,r14", call_used_option, call_used_regs, 0);
-    }
-
-
-  arg_nregs = fill_from_options (1, ARG_REGS, args_in_option,
-				 arg_regs,
-				 arg_regs_order);
-
-  if (fakes_option)
-    {
-      nfakes = atoi (fakes_option);
-    }
-  else
-    nfakes = 0;
-
-  /* Make fixed those which aren't going to be fake */
-  for (j = 0, i = STACK_POINTER_REGNUM + 1;
-       i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      fixed_regs[i] = !(j < nfakes);
-    }
-
-  /* The stack and frame pointer shouldn't be call_used */
-
-  call_used_regs[STACK_POINTER_REGNUM] = 1;
-  call_used_regs[FRAME_POINTER_REGNUM] = 0;
-
-  if (TARGET_BIG)
-    {
-      call_used_regs[STACK_POINTER_REGNUM + 1] = 1;
-      call_used_regs[FRAME_POINTER_REGNUM + 1] = 0;
-    }
-
-  /* Fill in the ok modes */
-
-  /* Work out the names of the registers */
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-
-      regname (i, QImode) = strdup ("     ");
-      sprintf (regname (i, QImode), "*QI%d", i);
-      regname (i, HImode) = strdup ("     ");
-      sprintf (regname (i, HImode), "*HI%d", i);
-      regname (i, SImode) = strdup ("     ");
-      sprintf (regname (i, SImode), "*SI%d", i);
-      regname (i, DImode) = strdup ("     ");
-      sprintf (regname (i, DImode), "*DI%d", i);
-    }
-
-  regname (0, QImode) = "rl0";
-  regname (1, QImode) = "rl1";
-  regname (2, QImode) = "rl2";
-  regname (3, QImode) = "rl3";
-  regname (4, QImode) = "rl4";
-  regname (5, QImode) = "rl5";
-  regname (6, QImode) = "rl6";
-  regname (7, QImode) = "rl7";
-
-  regname (0, HImode) = "r0";
-  regname (1, HImode) = "r1";
-  regname (2, HImode) = "r2";
-  regname (3, HImode) = "r3";
-  regname (4, HImode) = "r4";
-  regname (5, HImode) = "r5";
-  regname (6, HImode) = "r6";
-  regname (7, HImode) = "r7";
-  regname (8, HImode) = "r8";
-  regname (9, HImode) = "r9";
-  regname (10, HImode) = "r10";
-  regname (11, HImode) = "r11";
-  regname (12, HImode) = "r12";
-  regname (13, HImode) = "r13";
-  regname (14, HImode) = "r14";
-  regname (15, HImode) = "r15";
-
-  regname (0, SImode) = "rr0";
-  regname (2, SImode) = "rr2";
-  regname (4, SImode) = "rr4";
-  regname (6, SImode) = "rr6";
-  regname (8, SImode) = "rr8";
-  regname (10, SImode) = "rr10";
-  regname (12, SImode) = "rr12";
-  regname (14, SImode) = "rr14";
-
-  regname (0, PSImode) = "rr0";
-  regname (2, PSImode) = "rr2";
-  regname (4, PSImode) = "rr4";
-  regname (6, PSImode) = "rr6";
-  regname (8, PSImode) = "rr8";
-  regname (10, PSImode) = "rr10";
-  regname (12, PSImode) = "rr12";
-  regname (14, PSImode) = "rr14";
-
-  if (TARGET_BIG)
-    {
-      /* We need r11 and r15 for big mode */
-      fixed_regs[15] = 1;
-      fixed_regs[11] = 1;
-      call_used_regs[11] = 1;
-    }
-  else
-    {
-      /* for little mode we use 15 as the sp */
-      renumber[15]  = 14;
-      renumber[14]  = 15;
-    }
-
-
-  /* The frame pointer is odd too.  When in STD_FRAME mode we keep the
-     frame pointer inside GCC in r10, but we print it out as rr12 or r14.. */
-
-  if (TARGET_STD_FRAME)
-    {
-      if (TARGET_BIG) {
-	renumber[10] = 12;
-	renumber[11] = 13;
-	renumber[12] = 10;
-	renumber[13] = 11;
-      }
-      else {
-	/* So the internal fp at 10 comes out in r14,
-	   the interal sp comes out at 15
-	   and r15 is printed as r10 */
-	renumber[FRAME_POINTER_REGNUM] = 14;
-	renumber[STACK_POINTER_REGNUM] = 15;
-	renumber[15] = 10;
-      }
-    }
-
-  regname (0, DImode) = "rq0";
-  regname (4, DImode) = "rq4";
-  regname (8, DImode) = "rq8";
-  regname (12, DImode) = "rq12";
-
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    pointer_reg[i] = regname (i, Pmode);
-
-  if (TARGET_DEFS || TARGET_SOURCE || TARGET_LINE)
-    {
-      write_symbols = SDB_DEBUG;
-      debug_info_level = DINFO_LEVEL_NORMAL;
-    }
-
-  if (TARGET_PIC)
-    {
-      fixed_regs[13] = 1;
-    }
-  flag_force_mem = 0;
-  flag_caller_saves = 0;
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    rev_renumber[renumber[i]] = i;
-
-}
-
-
-/*
-  Offset from the stack pointer register to the first location at
-  which outgoing arguments are placed.  If not specified, the
-  default value of zero is used.  This is the proper value for most
-  machines.
-  */
-
-
-
-rtx
-z8k_function_arg (cum, mode, type, named)
-     int cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-{
-  int t;
-  int nregs;
-  int rn;
-  enum machine_mode rmode = ((mode == BLKmode) ? TYPE_MODE (type) : mode);
-
-  if (mode == BLKmode || mode == VOIDmode)
-    return 0;
-  else
-    nregs = (GET_MODE_SIZE (mode) + 1) / 2;
-
-  if (!TARGET_REGPARMS)
-    {
-      /* Might not be allowed to do this */
-      return 0;
-    }
-
-  /* Varargs always go on stack, unless in YASM mode*/
-  if (!TARGET_YASM)
-    {
-      if (!named)
-	return 0;
-    }
-
-  /* Never put a struct in regs - one reason is that calls.c doesn't
-     know if you load your regs backwards or forwards.  We could fix
-     this by printing r0 as r15, r1 as r14 etc
-     */
-
-  /* Move down till we have used enough regs and
-     we're aligned */
-
-  rn = cum - (nregs - 1);
-  while (rn >= 2
-	 && !HARD_REGNO_MODE_OK (rn, rmode))
-    {
-      rn--;
-    }
-
-
-  if (rn < 2 || rn > 7)
-    return 0;
-  return gen_rtx (REG, rmode, rn);
-}
-
-/* return 1 if there isn't anything tricky to do */
-
-int
-null_epilogue ()
-{
-  int i;
-
-  if (!reload_completed)
-    return 0;
-  if (frame_pointer_needed)
-    return 0;
-  if (get_frame_size ())
-    return 0;
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      if (regs_ever_live[i] && !call_used_regs[i])
-	return 0;
-    }
-
-  return 1;
-}
-
-struct rtx_def *
-z8k_builtin_saveregs (arglist)
-     tree arglist;
-{
-  int i;
-
-  for (i = 0; i < arg_nregs; i++)
-    {
-      emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, HImode, arg_regs_order[i])));
-    }
-  return 0;
-}
-
-void
-asm_output_local (file, name, size, rounded)
-     FILE *file;
-     char *name;
-     int size;
-     int rounded;
-{
-  if (TARGET_YASM)
-    {
-      tree name_tree = get_identifier (name);
-      TREE_ASM_WRITTEN (name_tree) = 1;
-    }
-
-  data_section ();
-  assemble_name (file, name);
-  fprintf (file, ":\n\tblock\t%u\n", rounded);
-}
-
-void
-asm_output_common (file, name, size, rounded)
-     FILE *file;
-     char *name;
-     int size;
-     int rounded;
-{
-  if (TARGET_YASM)
-    {
-      data_section();
-      if (size > 1)
-      {
-          ASM_OUTPUT_ALIGN (file, 1);
-      }
-      ASM_GLOBALIZE_LABEL (file, name);
-      ASM_OUTPUT_LOCAL (file, name, size, rounded);
-    }
-  else
-    {
-      fputs (".comm ", file);
-      assemble_name (file, name);
-      fprintf (file, ",%u\n", rounded);
-    }
-}
-
-void
-asm_output_name (file, name)
-     FILE *file;
-     char *name;
-{
-  if (TARGET_YASM)
-    {
-      tree name_tree = get_identifier (name);
-      TREE_ASM_WRITTEN (name_tree) = 1;
-    }
-
-  ASM_OUTPUT_LABEL (asm_out_file, name);
-}
-
-/*
-  emit instructions to move operands[1] to operands[0].
-
-  Return 1 if we've done everything that needs to be done, otherwise
-  return 0 and let the compiler emit a move instruction using possibly
-  altered operands.
-*/
-extern rtx copy_to_mode_reg ();
-rtx
-simple (mode, operand)
-     enum machine_mode mode;
-     rtx operand;
-{
-
-  if (mode == DFmode
-      && GET_CODE (operand) == MEM &&
-      GET_CODE (XEXP (operand, 0)) == PLUS)
-    {
-      /* Operand 0 of the PLUS must be a register, so we can force operand 1
-	 into a new pseudo reg, and then safely add operand 0 to it.  */
-      rtx x = XEXP (operand, 0);
-      rtx t1 = XEXP (x, 0);
-      rtx t2 = copy_to_mode_reg (Pmode, XEXP (x, 1));
-      emit_insn (gen_rtx (SET, VOIDmode, t2,
-			  gen_rtx (PLUS, Pmode, t2, t1)));
-      return gen_rtx (MEM, mode, t2);
-    }
-
-  return operand;
-}
-
-int
-emit_move (operands, mode, extra)
-     rtx operands[];
-     enum machine_mode mode;
-     int extra;
-
-{
-  extern int reload_in_progress;
-  rtx operand0 = operands[0];
-  rtx operand1 = operands[1];
-  int need_copy = 0;
-
-  if (rtx_equal_p (operand0, operand1))
-    return 1;
-  if (!reload_in_progress)
-    {
-      /* Can't push a long immediate */
-      if (mode == SImode
-	  && push_operand (operand0, mode)
-	  && immediate_operand (operand1, mode))
-	{
-	  need_copy = 1;
-	}
-
-      if (mode == SFmode
-	  && immediate_operand (operand1, mode))
-	{
-	  need_copy = 1;
-	}
-
-      if (push_operand (operand0, mode))
-	{
-	  need_copy =
-	    !ir_operand (operand1, mode)
-	    && !da_operand (operand1, mode)
-	    && !x_operand (operand1, mode);
-	  {
-	    need_copy = 1;
-	  }
-	}
-      if (!register_operand (operand0, mode)
-	  && !register_operand (operand1, mode))
-	{
-	  need_copy = 1;
-	}
-
-    }
-  if (TARGET_BIG && !reload_in_progress)
-    {
-      operand1 = simple (mode, operand1);
-      operand0 = simple (mode, operand0);
-    }
-  if (need_copy)
-    {
-      rtx temp = gen_reg_rtx (mode);
-      emit_insn (gen_rtx (SET, VOIDmode, temp, operand1));
-      emit_insn (gen_rtx (SET, VOIDmode, operand0, temp));
-      return 1;
-    }
-  operands[0] = operand0;
-  operands[1] = operand1;
-  return 0;
-}
-
-int
-r_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (BADSUBREG (op))
-    return 0;
-  return register_operand (op, mode);
-}
-
-int
-ir_operand_s (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (mode != GET_MODE (op))
-    return 0;
-  if (BADSUBREG (op))
-    return 0;
-  return IR_P (op);
-}
-
-int
-ir_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return ir_operand_s (op, mode);
-}
-
-int
-da_operand_s (op, mode, strict)
-     rtx op;
-     enum machine_mode mode;
-     int strict;
-{
-  if (mode != GET_MODE (op))
-    return 0;
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  return DA_P (op);
-}
-
-int
-da_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return da_operand_s (op, mode, reload_in_progress);
-}
-
-/*  16 bit Reg  + pointer sized bit index*/
-
-x_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (BADSUBREG (op))
-    return 0;
-  if (mode != GET_MODE (op))
-    return 0;
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  return X_P (op);
-}
-
-
-int
-find_reg (op, strict)
-     rtx op;
-     int strict;
-{
-  int rn = REGNO (op);
-  if (strict && reg_renumber == 0)
-    abort ();
-  if (strict && rn >= FIRST_PSEUDO_REGISTER)
-    return reg_renumber[rn];
-  return rn;
-}
-
-ok_for_base (op, strict)
-     rtx op;
-     int strict;
-{
-  int rn;
-  if (GET_CODE (op) != REG)
-    return 0;
-  if (GET_MODE (op) != Pmode)
-    return 0;
-  rn = find_reg (op, strict);
-
-  if (reload_in_progress && rn > FIRST_PSEUDO_REGISTER)
-    return 1;
-
-  if (strict)
-    {
-      if (rn <= 0)
-	return 0;
-      return 1;
-    }
-  else
-    {
-      return rn != 0;
-    }
-}
-
-ok_for_index (op, strict)
-     rtx op;
-     int strict;
-{
-  int rn;
-  if (GET_CODE (op) != REG)
-    return 0;
-  if (GET_MODE (op) != HImode
-      && GET_MODE (op) != Pmode)
-    return 0;
-  rn = find_reg (op, strict);
-  if (strict)
-    {
-      if (rn <= 0)
-	return 0;
-      return 1;
-    }
-  else
-    {
-      return rn != 0;
-    }
-}
-
-
-inside_bx_p (op, strict)
-     rtx op;
-{
-  if (GET_CODE (op) == PLUS)
-    {
-      rtx lhs = XEXP (op, 0);
-      rtx rhs = XEXP (op, 1);
-      if (ok_for_base (rhs, strict))
-	{
-	  if (GET_CODE (lhs) == TRUNCATE)
-	    lhs = XEXP (lhs, 0);
-	  if (GET_CODE (lhs) == SIGN_EXTEND)
-	    {
-	      lhs = XEXP (lhs, 0);
-	      if (ok_for_index (lhs, strict))
-		return 1;
-	    }
-	}
-
-      if (ok_for_base (lhs, strict))
-	{
-	  if (GET_CODE (rhs) == TRUNCATE)
-	    rhs = XEXP (rhs, 0);
-	  if (GET_CODE (rhs) == SIGN_EXTEND)
-	    {
-	      rhs = XEXP (rhs, 0);
-	      if (ok_for_index (rhs, strict))
-		return 1;
-	    }
-	}
-    }
-  return 0;
-}
-
-
-/* 16 bit register + pointer sized address */
-inside_x_p (op, strict)
-     rtx op;
-
-{
-  if (strict != 0 && strict != 1)
-    abort ();
-  if (GET_CODE (op) == PLUS)
-    {
-      rtx lhs = XEXP (op, 0);
-      rtx rhs = XEXP (op, 1);
-      if (TARGET_SMALL)
-	{
-	  if (GET_CODE (lhs) == CONST_INT && ok_for_index (rhs, strict))
-	    return 1;
-
-	  if (GET_CODE (rhs) == CONST_INT && ok_for_index (lhs, strict))
-	    return 1;
-	}
-
-      if (data_ref_p (lhs))
-	{
-
-	  if (ok_for_index (rhs, strict))
-	    {
-	      return 1;
-	    }
-	}
-
-      if (data_ref_p (rhs))
-	{
-	  if (ok_for_index (lhs, strict))
-	    {
-	      return 1;
-	    }
-	}
-
-    }
-  return 0;
-}
-
-
-inside_da_p (op, strict)
-     rtx op;
-     int strict;
-{
-  if (DATA_REF_P (op))
-    return 1;
-  return 0;
-}
-
-inside_ba_p (op, strict)
-     rtx op;
-{
-  if (strict != 0 && strict != 1)
-    abort ();
-  if (GET_CODE (op) == PLUS)
-    {
-      rtx lhs = XEXP (op, 0);
-      rtx rhs = XEXP (op, 1);
-      if (ok_for_base (lhs, strict))
-	{
-	  if (GET_CODE (rhs) == CONST_INT)
-	    {
-	      if (INTVAL (rhs) & 1)
-		return 0;
-	      return 1;
-	    }
-	}
-    }
-  return 0;
-}
-
-bx_p (op, strict)
-     rtx op;
-{
-  if (strict != 0 && strict != 1)
-    abort ();
-  if (GET_CODE (op) != MEM)
-    return 0;
-  return inside_bx_p (XEXP (op, 0), strict);
-}
-
-ba_p (op, strict)
-     rtx op;
-{
-  if (strict != 0 && strict != 1)
-    abort ();
-  if (GET_CODE (op) != MEM)
-    return 0;
-  return inside_ba_p (XEXP (op, 0), strict);
-}
-
-x_p (op, strict)
-     rtx op;
-{
-  if (GET_CODE (op) != MEM)
-    return 0;
-  return inside_x_p (XEXP (op, 0), 0);
-}
-
-
-int
-ba_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (BADSUBREG (op))
-    return 0;
-  if (mode != GET_MODE (op))
-    return 0;
-
-  if (GET_CODE (op) == SUBREG)
-    op = SUBREG_REG (op);
-
-  if (ba_p (op, 0))
-    return 1;
-  return 0;
-}
-
-int
-bx_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (BADSUBREG (op))
-    return 0;
-
-  if (bx_p (op, 0))
-    return 1;
-  return 0;
-}
-
-int
-im_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return immediate_operand (op, mode);
-}
-
-int
-r_ir_da_x_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || ir_operand (op, mode)
-    || da_operand (op, mode)
-    || x_operand (op, mode);
-  return r;
-
-}
-
-
-/* When operating on a DI or DF we'll always
-   need to get to another double word.  This makes
-   the ir mode not work (since 4(rn) is invalid unless
-   bx can also be done).  This works on the Z8002 since
-   x mode will suffice */
-int
-r_ir_da_x_operand_for_di (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || (TARGET_SMALL && ir_operand (op, mode))
-    || da_operand (op, mode)
-    || (TARGET_SMALL && x_operand (op, mode));
-  return r;
-
-}
-
-int
-r_im_ir_da_x_operand_for_di (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || im_operand (op, mode)
-    || (TARGET_SMALL && ir_operand (op, mode))
-    || da_operand (op, mode)
-    || (TARGET_SMALL && x_operand (op, mode));
-  return r;
-
-}
-
-
-
-int
-r_ir_da_x_ba_operand_for_di (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || ba_operand (op, mode)
-    || ir_operand (op, mode)	/* Note we can use this because ba is here */
-    || da_operand (op, mode)
-    || x_operand (op, mode);
-  return r;
-
-}
-
-
-
-int
-r_ir_da_x_ba_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || ir_operand (op, mode)
-    || da_operand (op, mode)
-    || x_operand (op, mode)
-    || ba_operand (op, mode);
-  return r;
-
-}
-
-int
-r_im_ir_da_x_ba_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || ir_operand (op, mode)
-    || da_operand (op, mode)
-    || im_operand (op, mode)
-    || x_operand (op, mode)
-    || ba_operand (op, mode);
-  return r;
-
-}
-
-int
-r_im_ir_da_x_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || im_operand (op, mode)
-    || ir_operand (op, mode)
-    || da_operand (op, mode)
-    || x_operand (op, mode);
-  return r;
-}
-
-
-int
-r_im_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return r_operand (op, mode) || im_operand (op, mode);
-}
-
-int
-r_im_ir_da_x_ba_bx_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || im_operand (op, mode)
-    || ir_operand (op, mode)
-    || da_operand (op, mode)
-    || x_operand (op, mode)
-    || ba_operand (op, mode)
-    || bx_operand (op, mode);
-  return r;
-}
-
-int
-r_ir_da_x_ba_bx_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || ir_operand (op, mode)
-    || da_operand (op, mode)
-    || x_operand (op, mode)
-    || ba_operand (op, mode)
-    || bx_operand (op, mode);
-  return r;
-}
-
-int
-r_ir_da_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || ir_operand (op, mode)
-    || da_operand (op, mode);
-  return r;
-}
-
-int
-move_check (operands, mode)
-     rtx operands[];
-     enum machine_mode mode;
-{
-  return 1;
-}
-
-int
-register_move_cost (x, y)
-     int x;
-     int y;
-{
-  if ((x == QI_REGS) != (y == QI_REGS))
-    return 5;
-
-  return 2;
-}
-
-int
-r_im_ir_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || im_operand (op, mode)
-    || ir_operand (op, mode);
-  return r;
-}
-
-int
-r_im_ir_da_x_operand_or_r (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (TARGET_BIG) ? r_operand (op, mode) : r_im_ir_da_x_operand (op, mode);
-}
-
-int
-r_da_x_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return r_operand (op, mode)
-    || da_operand (op, mode)
-    || x_operand (op, mode);
-}
-
-int
-r_im_ir_da_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return r_operand (op, mode)
-    || im_operand (op, mode)
-    || ir_operand (op, mode)
-    || da_operand (op, mode);
-
-
-}
-
-ir_da_x_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return ir_operand (op, mode)
-    || da_operand (op, mode)
-    || x_operand (op, mode);
-}
-
-char *
-z8k_asm_output_opcode (file, string)
-     FILE *file;
-     char *string;
-{
-  if (string[0] == '$')
-    {
-      can_ba_bx = 1;
-      string++;
-    }
-  else
-    {
-      can_ba_bx = 0;
-    }
-  return string;
-}
-
-
-int
-data_ref_p_1 (X)
-     rtx X;
-{
-  if (TARGET_PIC)
-    return 0;
-
-  return (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF
-	  || (GET_CODE (X) == PLUS
-	      && GET_CODE (XEXP (X, 0)) == SYMBOL_REF
-	      && GET_CODE (XEXP (X, 1)) == CONST_INT));
-}
-
-int
-data_ref_p (X)
-     rtx X;
-{
-  if (TARGET_PIC)
-    return 0;
-  if (TARGET_BIG)
-    return (DATA_REF_P_1 (X) || (GET_CODE (X) == CONST && DATA_REF_P_1 (XEXP (X, 0))));
-  return CONSTANT_P (X);
-}
-
-
-
-int
-disp_p (X)
-     rtx X;
-{
-  return
-    ((GET_CODE (X) == CONST_INT && (((unsigned) INTVAL (X) + 0xffff) < 0x1ffff)) || (!TARGET_HUGE && DATA_REF_P (X)));
-}
-
-
-int
-ptr_reg (x)
-     rtx x;
-{
-  if (reload_completed || !TARGET_HUGE)
-    return 1;
-  if (STACK_REGISTER (REGNO (x)))
-    return 1;
-  return 0;
-}
-
-
-/* Work out the registers which need to be saved, both as a mask and a
-   count */
-
-int
-calc_live_regs (count)
-     int *count;
-{
-  int reg;
-  int live_regs_mask = 0;
-  *count = 0;
-
-  for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
-    {
-      if (regs_ever_live[reg] && !call_used_regs[reg])
-	{
-	  (*count)++;
-	  live_regs_mask |= (1 << reg);
-
-	  if (reg == FRAME_POINTER_REGNUM && frame_pointer_needed && TARGET_BIG)
-	    {
-	      /* Count r11 too */
-	      (*count)++;
-	      reg++;
-	      live_regs_mask |= (1 << reg);
-	    }
-	}
-    }
-  return live_regs_mask;
-}
-
-io (from, to)
-{
-  int regs_saved;
-  int d = calc_live_regs (&regs_saved);
-  int total_saved_regs_space = (regs_saved) * 2;
-  int total_auto_space = get_frame_size ();
-  int pcsize = TARGET_BIG ? 4 : 2;
-
-  if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
-    {
-      return total_saved_regs_space + pcsize;
-    }
-
-  if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
-    {
-      return total_saved_regs_space + total_auto_space + pcsize;
-    }
-
-  if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
-    {
-      return total_auto_space;
-    }
-
-  if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
-    {
-      return total_saved_regs_space;
-    }
-
-  if (from == RETURN_ADDRESS_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
-    {
-      return total_saved_regs_space + total_auto_space;
-    }
-}
-
-fualign (direction, x, y)
-{
-
-  return (direction > 0 ? ((x + (y - 1)) & -y) : (x & (y - 1)));
-
-}
-
-faa (CUM, MODE, TYPE, NAMED)
-     int CUM;
-     enum machine_mode MODE;
-     tree TYPE;
-     int NAMED;
-{
-  int nrs;
-  int align;
-
-  switch (MODE)
-    {
-    case QImode:
-    case HImode:
-      nrs = 1;
-      break;
-
-    case SFmode:
-    case PSImode:
-    case SImode:
-      nrs = 2;
-      break;
-    case DFmode:
-    case DImode:
-      nrs = 4;
-      break;
-    case VOIDmode:
-    case BLKmode:
-    default:
-      nrs = (int_size_in_bytes (TYPE) + 1) / 2;
-      break;
-    }
-
-  CUM = CUM - (nrs - 1);
-  while (CUM >= 2
-	 && !HARD_REGNO_MODE_OK (CUM, MODE))
-    {
-      CUM--;
-    }
-
-  return CUM - 1;
-
-}
-
-/* Stuff taken from m88k.c */
-
-/* Output to FILE the start of the assembler file.  */
-
-struct options
-{
-  char *string;
-  int *variable;
-  int on_value;
-  char *description;
-};
-
-static int
-output_option (file, sep, type, name, indent, pos, max)
-     FILE *file;
-     char *sep;
-     char *type;
-     char *name;
-     char *indent;
-     int pos;
-     int max;
-{
-  if (strlen (sep) + strlen (type) + strlen (name) + pos > max)
-    {
-      fprintf (file, indent);
-      return fprintf (file, "%s%s", type, name);
-    }
-  return pos + fprintf (file, "%s%s%s", sep, type, name);
-}
-
-static struct
-{
-  char *name;
-  int value;
-}
-
-m_options[] = TARGET_SWITCHES;
-
-static void
-output_options (file, f_options, f_len, W_options, W_len,
-		pos, max, sep, indent, term)
-     FILE *file;
-     struct options *f_options;
-     struct options *W_options;
-     int f_len, W_len;
-     int pos;
-     int max;
-     char *sep;
-     char *indent;
-     char *term;
-{
-  register int j;
-  extern int flag_traditional;
-
-  if (optimize)
-    pos = output_option (file, sep, "-O", "", indent, pos, max);
-  if (write_symbols != NO_DEBUG)
-    pos = output_option (file, sep, "-g", "", indent, pos, max);
-  if (flag_traditional)
-    pos = output_option (file, sep, "-traditional", "", indent, pos, max);
-  if (profile_flag)
-    pos = output_option (file, sep, "-p", "", indent, pos, max);
-  if (profile_block_flag)
-    pos = output_option (file, sep, "-a", "", indent, pos, max);
-
-  for (j = 0; j < f_len; j++)
-    if (*f_options[j].variable == f_options[j].on_value)
-      pos = output_option (file, sep, "-f", f_options[j].string,
-			   indent, pos, max);
-
-  for (j = 0; j < W_len; j++)
-    if (*W_options[j].variable == W_options[j].on_value)
-      pos = output_option (file, sep, "-W", W_options[j].string,
-			   indent, pos, max);
-
-  for (j = 0; j < sizeof m_options / sizeof m_options[0]; j++)
-    if (m_options[j].name[0] != '\0'
-	&& m_options[j].value > 0
-	&& ((m_options[j].value & target_flags)
-	    == m_options[j].value))
-      pos = output_option (file, sep, "-m", m_options[j].name,
-			   indent, pos, max);
-
-
-
-}
-
-
-asm_file_start (file, f_options, f_len, W_options, W_len)
-     FILE *file;
-     struct options *f_options;
-     struct options *W_options;
-     int f_len, W_len;
-{
-  int i;
-
-  extern int arg_regs_order[];
-  extern char *main_input_filename;
-  extern int arg_nregs;
-  extern char call_used_regs[];
-  extern char *input_filename;
-
-  char *quote = TARGET_YASM ? "" : "\"";
-
-  fprintf (file, "!\tGCC  Z8000\n");
-  fprintf (file, "!\tCygnus Support\n");
-  fprintf (file, "!\tsizeof(size_t)=%d\n", TARGET_BIG ? 4 : 2);
-
-  output_file_directive (file, main_input_filename);
-  fprintf (file, "!");
-  output_options (file, f_options, f_len, W_options, W_len,
-		  0, 75, " ", "\n! ", "\n\n");
-
-  fprintf (file, "\n\n");
-
-  if (TARGET_BIG)
-    fprintf (file, "\tsegm\n");
-  else
-    fprintf (file, "\tunseg\n");
-
-  if (TARGET_YASM)
-    {
-      fprintf (file, "\trsect   USRROM\n");
-      fprintf (file, "\teven\n");
-      fprintf (file, "\trsect   USRRAM\n");
-      fprintf (file, "\teven\n");
-      fprintf (file, "\trsect   USRTXT\n");
-      fprintf (file, "\teven\n");
-    }
-
-  load_source_file (input_filename);
-}
-
-void
-asm_file_end (file)
-     FILE *file;
-{
-  if (TARGET_YASM)
-    {
-      struct extern_list *p;
-
-      for (p = extern_head; p != 0; p = p->next)
-	{
-	  tree name_tree = get_identifier (p->name);
-
-	  if (!TREE_ASM_WRITTEN (name_tree))
-	    {
-	      TREE_ASM_WRITTEN (name_tree) = 1;
-	      fputs ("\textern\t", file);
-	      assemble_name (file, p->name);
-	      fputs ("\n", file);
-	    }
-	}
-
-      fprintf (file, "\tend\n");
-    }
-}
-
-
-/*********************************************************************************************
- * Source Program Listing Generation Management Routines                                     *
- *********************************************************************************************/
-
-#ifndef  LINE_LEN
-#define  LINE_LEN        	1000
-#endif
-
-
-/* 'line_no' - contains actual source line number starting from 1.
-   'line' - points to the actual source line. */
-struct source_line_node
-{
-  struct source_line_node *prev, *next;
-  int line_no;
-  char *line;
-};
-typedef struct source_line_node line_node;
-
-/* 'name' - points to the file name.
-   'head' - points to the first source line.
-   'current_line' - points to the last referenced source line. */
-struct source_file_node
-  {
-    struct source_file_node *next;
-    char *name;
-    line_node *head, *current_line;
-  };
-typedef struct source_file_node file_node;
-
-static file_node *file_head = 0, *current_file = 0;
-
-void
-add_line (line_no, source_line)
-     int line_no;
-     char source_line[];
-{
-  if (file_head)
-    {
-      line_node *temp_node;
-
-      temp_node = (line_node *) (malloc (sizeof (line_node)));
-      temp_node->line_no = line_no;
-      temp_node->line = (char *) (malloc (strlen (source_line) + 1));
-      strcpy (temp_node->line, source_line);
-
-      if (current_file->head)
-	{
-	  temp_node->prev = current_file->current_line;
-	  temp_node->next = 0;
-	  current_file->current_line->next = temp_node;
-	  current_file->current_line = temp_node;
-	}
-      else
-	{
-	  temp_node->prev = temp_node->next = 0;
-	  current_file->head = current_file->current_line = temp_node;
-	}
-    }
-}
-
-void
-load_single_file (file_name)
-     char *file_name;
-{
-  FILE *source_fp;
-  char source_line[LINE_LEN];
-  int ch;
-  int line_no = 1;
-  int col_no = 0;
-
-  if ((source_fp = fopen (file_name, "r")) == 0)
-    {
-      char global_file_name[LINE_LEN];
-      sprintf (global_file_name, "%s%s", "/usr/include", file_name);
-      source_fp = fopen (global_file_name, "r");
-      /* If file is pre-processed with cpp not all files can be opened. */
-    }
-
-  /* If not found leave current_file->head alone. This is an indication
-     that the source file is not found. */
-  if (source_fp != 0)
-    {
-      while ((ch = fgetc (source_fp)) != EOF)
-	switch (ch)
-	  {
-	  case '\n':
-	    /* End-of-line character (\n) is added in print_source_line. */
-	    source_line[col_no] = '\0';
-	    add_line (line_no, source_line);
-	    col_no = 0;
-	    line_no++;
-	    break;
-	  default:
-	    if (col_no < LINE_LEN - 1)
-	      source_line[col_no++] = ch;
-	    break;
-	  }
-      fclose (source_fp);
-    }
-}
-
-
-load_source_file (file_name)
-     char *file_name;
-{
-  file_node *temp_node, *tail_node = file_head;
-
-  for (temp_node = file_head; temp_node != 0; tail_node = temp_node, temp_node = temp_node->next)
-    if (strcmp (temp_node->name, file_name) == 0)
-      {
-	current_file = temp_node;
-	break;
-      }
-
-  if (temp_node == 0)
-    {
-      temp_node = (file_node *) (malloc (sizeof (file_node)));
-      temp_node->next = 0;
-      temp_node->name = (char *) (malloc (strlen (file_name) + 1));
-      strcpy (temp_node->name, file_name);
-      temp_node->head = temp_node->current_line = 0;
-
-      if (file_head)
-	tail_node->next = temp_node;
-      else
-	file_head = temp_node;
-
-      current_file = temp_node;
-      load_single_file (file_name);
-    }
-}
-
-void
-print_source_line (file, line_no)
-     FILE *file;
-     int line_no;
-{
-  if (TARGET_SOURCE && current_file)
-    {
-
-      /* If current_file->head is null it definitely implies that no source file
-	 has been found in the working directory. However, if current_line is null
-	 while head is not null, it means that no source line has been printed. */
-      if (!current_file->head)
-	fprintf (file, "! Line number:%d\n", line_no);
-      else if (!current_file->current_line)
-	{
-	  for (current_file->current_line = current_file->head;
-	       current_file->current_line
-	       && current_file->current_line->line_no != line_no;
-	       current_file->current_line = current_file->current_line->next)
-	    ;
-
-	  if (current_file->current_line && current_file->current_line->line)
-	    fprintf (file, "! %s\n", current_file->current_line->line);
-	}
-      else if (current_file->current_line->line_no < line_no)
-	{
-	  for (current_file->current_line = current_file->current_line->next;
-	       current_file->current_line
-	       && current_file->current_line->line_no <= line_no;
-	       current_file->current_line = current_file->current_line->next)
-	    {
-	      fprintf (file, "! %s\n", current_file->current_line->line);
-	      if (current_file->current_line->line_no == line_no)
-		break;
-	    }
-	}
-      else
-	{
-	  for (; current_file->current_line->line_no != line_no;
-	       current_file->current_line = current_file->current_line->prev)
-	    ;
-	  if (current_file->current_line)
-	    fprintf (file, "! %s\n", current_file->current_line->line);
-	}
-    }
-
-  if (TARGET_LINE)
-    {
-      fprintf (file, ".line %d\n", line_no);
-    }
-}
-
-
-
-/**********************************************************************/
-
-/* Code to generate prologue and epilogue sequences */
-
-
-
-rtx
-gen_push (operand0, mode)
-     rtx operand0;
-     enum machine_mode mode;
-{
-  return gen_rtx (SET, VOIDmode,
-		  gen_rtx (MEM, mode, gen_rtx (PRE_DEC, mode,
-		    gen_rtx (REG, pmode, STACK_POINTER_REGNUM))), operand0);
-}
-
-rtx
-gen_pop (operand0, mode)
-     rtx operand0;
-     enum machine_mode mode;
-{
-  return gen_rtx (SET, VOIDmode,
-		  operand0,
-		  gen_rtx (MEM, mode, gen_rtx (POST_INC, mode,
-			      gen_rtx (REG, pmode, STACK_POINTER_REGNUM))));
-}
-
-void
-push (rn, mode)
-     int rn;
-     enum machine_mode mode;
-{
-  emit_insn (gen_push (gen_rtx (REG, mode, rn), mode));
-}
-
-void
-pop (rn, mode)
-     enum machine_mode mode;
-{
-  emit_insn (gen_pop (gen_rtx (REG, mode, rn), mode));
-}
-
-
-/* Generate code to push the regs specified in the mask.  remember
-   that the mask is of the internal shape of the regs, not the
-   external shape - so go through the renumber vector */
-
-static void
-push_regs (mask)
-     int mask;
-{
-  int i;
-
-  int size = 0;
-  /* The mask is a bit-for-bit for the internal register numbering system,
-     so r10 has the fp in it.  We work out the external register numbering
-     so that we can push the registers efficiently */
-  int exregs[FIRST_PSEUDO_REGISTER];
-
-  memset (exregs, 0, sizeof (exregs));
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    {
-      if (mask & (1<<i))
-	{
-	  exregs[renumber[i]] = 1;
-	}
-    }
-
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i+=2)
-    {
-      if (exregs[i] && exregs[i+1])
-	{
-	  push (rev_renumber[i], SImode);
-	}
-      else if (exregs[i])
-	{
-	  push (rev_renumber[i], HImode);
-	}
-      else if (exregs[i+1])
-	{
-	  push (rev_renumber[i+1], HImode);
-	}
-    }
-
-}
-
-
-static void
-pop_regs (mask)
-     int mask;
-{
-  int i;
-  int j;
-
-  int size = 0;
-  /* The mask is a bit-for-bit for the internal register numbering system,
-     so r10 has the fp in it.  We work out the external register numbering
-     so that we can push the registers efficiently */
-  int exregs[16];
-
-  memset (exregs, 0, sizeof (exregs));
-
-  for (i = 0; i < 16; i++)
-    {
-      if (mask & (1<<i))
-	{
-	  exregs[renumber[i]] = 1;
-	}
-    }
-
-  for (j = 0; j < 16; j+=2)
-    {
-      i = 14 - j;
-      if (exregs[i] && exregs[i+1])
-	{
-	  pop (rev_renumber[i], SImode);
-	}
-      else if (exregs[i])
-	{
-	  pop (rev_renumber[i], HImode);
-	}
-      else if (exregs[i+1])
-	{
-	  pop (rev_renumber[i+1], HImode);
-	}
-    }
-
-}
-
-/* Adjust the stack and return the number of bytes taken to do it */
-
-static void
-output_stack_adjust (direction, size)
-     int direction;
-     int size;
-{
-  if (size)
-    {
-      rtx val = GEN_INT (size * direction);
-      rtx insn;
-
-      insn = (TARGET_BIG ? gen_addpsi3 : gen_addhi3) (stack_pointer_rtx, stack_pointer_rtx, val);
-
-      emit_insn (insn);
-    }
-}
-
-void
-z8k_expand_prologue ()
-{
-  int live_regs_mask;
-  int d;
-
-  live_regs_mask = calc_live_regs (&d);
-
-  output_stack_adjust (-1, current_function_pretend_args_size);
-
-  if (frame_pointer_needed)
-    {
-      push_regs (live_regs_mask);
-      if (TARGET_BIG)
-	emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
-      else
-	emit_insn (gen_movhi (frame_pointer_rtx, stack_pointer_rtx));
-    }
-  else
-    {
-      push_regs (live_regs_mask);
-    }
-
-  output_stack_adjust (-1, get_frame_size ());
-}
-
-void
-z8k_declare_function_name (file, name, decl)
-     FILE *file;
-     char *name;
-     tree decl;
-{
-  int reg_count;
-  int parm_size = 0;
-  tree parms;
-
-  /* Figure out how many registers are saved.  */
-  calc_live_regs (&reg_count);
-
-  /* Find parameters which are passed in registers, but live on
-     this function's stack.  */
-  parms = DECL_ARGUMENTS (decl);
-  for (; parms; parms = TREE_CHAIN (parms))
-    {
-      if (GET_CODE (DECL_RTL (parms)) == MEM
-	  && XEXP (DECL_RTL (parms), 0) != const0_rtx
-	  && ! CONSTANT_P (XEXP (DECL_RTL (parms), 0)))
-	parm_size += GET_MODE_SIZE (GET_MODE (DECL_RTL (parms)));
-    }
-  
-  /* Output the information.  */
-  fprintf (file, "! stack frame requirements for %s: %d bytes\n", name,
-	   (reg_count * 2 + get_frame_size ()
-	    + current_function_pretend_args_size));
-  fprintf (file, "! register saves: %d bytes\n", reg_count * 2);
-  fprintf (file, "! automatics, spills, etc: %d bytes\n",
-	   get_frame_size () - parm_size);
-  fprintf (file, "! parameters: %d bytes\n", parm_size);
-  fprintf (file, "! varargs flushback area: %d bytes\n",
-	   current_function_pretend_args_size);
-
-  /* Now output the label for this function.  */
-  asm_output_name (file, name); 
-
-}
-
-void
-z8k_expand_epilogue ()
-{
-  int live_regs_mask;
-  int d;
-  int i;
-  int need;
-  live_regs_mask = calc_live_regs (&d);
-
-  if (frame_pointer_needed)
-    {
-      if (TARGET_BIG)
-	emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
-      else
-	emit_insn (gen_movhi (stack_pointer_rtx, frame_pointer_rtx));
-      need = 0;
-    }
-  else
-    {
-      need = get_frame_size ();
-    }
-
-  if (live_regs_mask)
-    {
-      if (need)
-	{
-	  output_stack_adjust (1, need);
-	  need = 0;
-	}
-
-      pop_regs (live_regs_mask);
-    }
-  output_stack_adjust (1, extra_push + need +
-		       current_function_pretend_args_size);
-
-  current_function_anonymous_args = 0;
-}
-
-int
-pop_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != MEM)
-    return 0;
-
-  if (GET_MODE (op) != mode)
-    return 0;
-
-  op = XEXP (op, 0);
-
-  if (GET_CODE (op) != POST_INC)
-    return 0;
-
-  return XEXP (op, 0) == stack_pointer_rtx;
-}
-
-int
-smallint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return GET_CODE (op) == CONST_INT
-    && (CONST_OK_FOR_LETTER_P (INTVAL (op), 'J')
-	|| CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'));
-}
-
-
-int
-address_cost (mode)
-     rtx mode;
-{
-  if (GET_CODE (mode) == PLUS)
-    {
-      rtx lhs = XEXP (mode, 0);
-      rtx rhs = XEXP (mode, 1);
-      if (GET_CODE (lhs) == REG
-	  && GET_CODE (rhs) == CONST_INT)
-	return 10;
-
-      if (GET_CODE (lhs) == MEM)
-	return 40;
-    }
-  return 1;
-}
-
-int
-power_two_operand (operand, mode)
-     rtx operand;
-     enum machine_mode mode;
-{
-  if (GET_CODE (operand) == CONST_INT)
-    {
-      int i;
-      return POWER_OF_2 (INTVAL (operand));
-    }
-  return 0;
-}
-
-COM_POWER_OF_2 (value)
-     int value;
-{
-  return POWER_OF_2 (~(value | (~0xffff)));
-}
-
-com_power_two_operand (operand, mode)
-     rtx operand;
-     enum machine_mode mode;
-{
-
-  if (GET_CODE (operand) == CONST_INT)
-    return COM_POWER_OF_2 (INTVAL (operand));
-  return 0;
-}
-
-
-int
-prd_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != MEM)
-    return 0;
-  if (GET_MODE (op) != mode)
-    return 0;
-  op = XEXP (op, 0);
-  if (GET_CODE (op) != PRE_DEC)
-    return 0;
-  return register_operand (XEXP (op, 0), Pmode);
-}
-
-int
-poi_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != MEM)
-    return 0;
-  if (GET_MODE (op) != mode)
-    return 0;
-  op = XEXP (op, 0);
-  if (GET_CODE (op) != POST_INC)
-    return 0;
-  return register_operand (XEXP (op, 0), Pmode);
-}
-
-
-r_im_ir_da_x_ba_bx_poi_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || im_operand (op, mode)
-    || ir_operand (op, mode)
-    || da_operand (op, mode)
-    || x_operand (op, mode)
-    || ba_operand (op, mode)
-    || bx_operand (op, mode)
-    || poi_operand (op, mode);
-  return r;
-}
-
-int
-r_ir_da_x_ba_bx_poi_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || ir_operand (op, mode)
-    || da_operand (op, mode)
-    || x_operand (op, mode)
-    || ba_operand (op, mode)
-    || bx_operand (op, mode)
-    || poi_operand (op, mode);
-  return r;
-}
-
-int
-r_ir_da_x_ba_bx_prd_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  int r;
-
-  r = r_operand (op, mode)
-    || ir_operand (op, mode)
-    || da_operand (op, mode)
-    || x_operand (op, mode)
-    || ba_operand (op, mode)
-    || bx_operand (op, mode)
-    || prd_operand (op, mode);
-  return r;
-}
-
-
-rtx
-legitimize_address (oldx, mode)
-     rtx oldx;
-     enum machine_mode mode;
-{
-#if 0
-  if (TARGET_PIC)
-    {
-      if (GET_CODE (oldx) == SYMBOL_REF
-	  || GET_CODE (oldx) == LABEL_REF)
-	{
-	  rtx ptr = gen_reg_rtx (Pmode);
-	  emit_insn (gen_rtx (SET, VOIDmode, ptr,
-			      gen_rtx (LO_SUM, pic_reg, oldx)));
-	  return gen_rtx (MEM, mode, ptr);
-	}
-    }
-#endif
-  return oldx;
-}
-
-symbol_ref (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == SYMBOL_REF)
-    return 1;
-  return 0;
-}
-
-not_subreg_register_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return (GET_CODE (op) == REG);
-}
-
-BADSUBREG (op)
-     rtx op;
-{
-  /* Can't subreg someting like subreg:HI (mem:SI (plus: reg reg) )
-     cause there's no room to put the extra +1 to get to the low part */
-
-
-  if (GET_CODE (op) == SUBREG)
-    {
-      /* Always ok if want the high word */
-      rtx inside;
-
-      /* Subreg of a reg is ok too */
-      if (GET_CODE (SUBREG_REG (op)) == REG)
-	return 0;
-
-      inside = XEXP (op, 0);
-      if (GET_CODE (inside) == MEM)
-	{
-
-	  /* Can't do paradoxical subregs in memory */
-	  if (GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (inside)))
-	    return 1;
-	  /* Ok if want the low part of a mem(symbol_ref), mem(reg), or mem(reg+k)
-
-	   since they can have indexing added to them */
-	  inside = XEXP (inside, 0);
-
-	  if (inside_da_p (inside, 0)
-	      || inside_x_p (inside, 0)
-	      || inside_ba_p (inside, 0))
-	    return 0;
-	  return 1;
-	  /* If you want the high part (the low addressed bit) then the other modes
-	   work too */
-	  if (SUBREG_WORD (op) == 0 && 0)
-	    {
-
-	      if (inside_bx_p (inside, 0))
-		return 0;
-
-	    }
-
-
-
-	  return 1;
-	}
-    }
-  return 0;
-}
-
-/* Return the register class of a scratch register needed to copy IN into
-   or out of a register in CLASS in MODE.  If it can be done directly,
-   NO_REGS is returned.  */
-
-enum reg_class
-secondary_reload_class (class, mode, in)
-     enum reg_class class;
-     enum machine_mode mode;
-     rtx in;
-{
-  int regno = -1;
-  enum rtx_code code = GET_CODE (in);
-
-  /* Can move all but qis any time */
-  if (mode != QImode)
-    return NO_REGS;
-
-  /* Can easily move in and out of qi regs */
-  if (class == QI_REGS)
-    return NO_REGS;
-  if (!CONSTANT_P (in))
-    {
-      regno = true_regnum (in);
-
-      /* A pseudo is the same as memory.  */
-      if (regno == -1 || regno >= FIRST_PSEUDO_REGISTER)
-	code = MEM;
-    }
-
-  /* If between memory we may need QI */
-
-  if (code == MEM)
-    return SQI_REGS;
-
-  return NO_REGS;
-
-}
-
-int
-ir_da_x_ba_bx_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-
-  return ir_operand (op, mode)
-    || da_operand (op, mode)
-    || x_operand (op, mode)
-    || ba_operand (op, mode)
-    || bx_operand (op, mode);
-}
-
-int
-r_da_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return r_operand (op, mode) || da_operand (op, mode);
-}
-
-
-int
-immediate15_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  return GET_CODE (op) == CONST_INT &&  (!(INTVAL (op) & 0x8000));
-}
-
-int
-moveok (operands, mode)
-     rtx *operands;
-     enum machine_mode mode;
-{
-  if (r_operand (operands[0], mode) && r_ir_da_x_ba_bx_operand (operands[1], mode))
-    return 1;
-  if (ir_da_x_ba_bx_operand (operands[0], mode) && r_operand (operands[1], mode))
-    return 1;
-  if (push_operand (operands[0], mode) && r_im_ir_da_x_operand (operands[1], mode))
-    return 1;
-  if (r_ir_da_x_operand (operands[0], mode) && pop_operand (operands[1], mode))
-    return 1;
-  if (mode == HImode || mode == QImode)
-    if (r_ir_da_x_operand (operands[0], mode) && immediate_operand (operands[1], mode))
-      return 1;
-  if (mode == SImode || mode == SFmode || mode == PSImode)
-    if (r_da_operand (operands[0], mode) && immediate_operand (operands[1], mode))
-      return 1;
-  return 0;
-}
-
-
-void
-asm_output_ascii (file, p, size)
-     FILE *file;
-     char *p;
-     int size;
-{
-  int i, col;
-  if (TARGET_YASM)
-    {
-      int max_buffer_size = 70;
-      fprintf (file, "\tsval\t'");
-      for (i = col = 0; i < size; i++, col++)
-	{
-	  register unsigned int c = (p[i] & 0xff);
-	  if (c != ';' && c != '\\' && c != '\'' && c != '\"' && c != '%' && c >= ' ' && c < 0177)
-	    putc (c, file);
-	  else
-	    fprintf (file, "%%%02x", c);
-	  /* If line is too long split the line */
-	  if (col > max_buffer_size && i < size - 1)
-	    {
-	      fprintf (file, "'\n\tsval\t'");
-	      col = 0;
-	    }
-	}
-      fprintf (file, "\047\n");
-    }
-  else
-    {
-      FILE *_hide_asm_out_file = file;
-      unsigned char *_hide_p = (unsigned char *) p;
-      int _hide_thissize = size;
-      {
-	FILE *asm_out_file = _hide_asm_out_file;
-	unsigned char *p = _hide_p;
-	int thissize = _hide_thissize;
-	int i;
-	fprintf (asm_out_file, "\t.ascii \"");
-
-	for (i = 0; i < thissize; i++)
-	  {
-	    register int c = p[i];
-	    if (c == '\"' || c == '\\')
-	      putc ('\\', asm_out_file);
-	    if (c >= ' ' && c < 0177)
-	      putc (c, asm_out_file);
-	    else
-	      {
-		fprintf (asm_out_file, "\\%o", c);
-		/* After an octal-escape, if a digit follows,
-		   terminate one string constant and start another.
-		   The Vax assembler fails to stop reading the escape
-		   after three digits, so this is the only way we
-		   can get it to parse the data properly.  */
-		if (i < thissize - 1
-		    && p[i + 1] >= '0' && p[i + 1] <= '9')
-		  fprintf (asm_out_file, "\"\n\t.ascii \"");
-	      }
-	  }
-	fprintf (asm_out_file, "\"\n");
-      }
-    }
-}
-
-/* Keep track of all externs, so that we can output an .extern declaration
-   for them at the end of the file, but only if they are not defined in
-   this file.  We assume that all names passed to us are in the permanent
-   obstack, so that they will be valid at the end of the compilation.  */
-
-void
-z8k_output_external (name)
-     char *name;
-{
-  struct extern_list *p;
-
-  p = (struct extern_list *) permalloc ((long) sizeof (struct extern_list));
-  p->next = extern_head;
-  p->name = name;
-  extern_head = p;
-}
-
-/* Work out which way a 64bit move should happen -
-   least or most significant word first */
-static
-int 
-whichway (dst, src)
-     rtx dst;
-     rtx src;
-{
-  if (GET_CODE (dst) == REG)
-    {
-      int rdst = REGNO (dst);
-      rtx dst_msw = gen_rtx (REG, SImode, rdst + 2);
-      if (GET_CODE (src) == REG)
-	{
-	  int rsrc = REGNO (src);
-	  if (rdst == rsrc + 2)
-	    return -1;
-	  else
-	    return 1;
-	}
-
-      /* if msw of dst is in the src, move the lsw first */
-      if (reg_overlap_mentioned_p (dst_msw, src))
-	{
-	  return 1;
-	}
-      if (reg_overlap_mentioned_p (dst, src))
-	{
-	  return -1;
-	}
-
-
-    }
-
-  return 1;
-}
-
-/* Return string to move 64 bit operand without trampling arguments. */
-
-char *
-output_move64 (dst, src)
-     rtx dst;
-     rtx src;
-{
-  if (push_operand (dst, GET_MODE (dst)))
-    {
-      /* Easy, unless source uses stack pointer */
-      if (reg_overlap_mentioned_p (stack_pointer_rtx, src))
-	{
-	  return "pushl	@%H0,%T1\n\tpushl	@%H0,%T1";
-	}
-      return "pushl	@%H0,%T1\n\tpushl	@%H0,%S1";
-    }
-  if (whichway (dst, src) < 0)
-    return "$ldl	%T0,%T1\n\t$ldl	%S0,%S1 ! di a";
-  else
-    return "$ldl	%S0,%S1\n\t$ldl	%T0,%T1 ! di b";
-}
diff --git a/gcc/config/z8k/z8k.h b/gcc/config/z8k/z8k.h
deleted file mode 100755
index 3fd0156..0000000
--- a/gcc/config/z8k/z8k.h
+++ /dev/null
@@ -1,1736 +0,0 @@
-/* Definitions of target machine for GNU compiler, for Zilog Z8000
-   Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc.
-   Contributed by Steve Chamberlain (sac@cygnus.com)
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
-
-#define TARGET_Z8000
-#define TARGET_SEGMENTED 1
-
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "-D__Z8000__ -Dz8000"
-
-/* Write out defines which depend on the compilation options */
-
-#define NO_BUILTIN_PTRDIFF_TYPE
-#define NO_BUILTIN_SIZE_TYPE
-
-#define SIZE_TYPE    (TARGET_BIG ? "long unsigned int" : "unsigned int")
-#define PTRDIFF_TYPE (TARGET_BIG ? "long int" : "int")
-
-#define CPP_SPEC \
-  "%{mz8001:-D__Z8001__  -D__PTRDIFF_TYPE__=long\\ int} 	\
-   %{!mz8001:-D__Z8002__ -D__PTRDIFF_TYPE__=int}		\
-   %{mz8001:-D__SIZE_TYPE__=long\\ unsigned\\ int} 		\
-   %{!mz8001:-D__SIZE_TYPE__=unsigned\\ int} 			\
-   %{!mint32:-D__INT_MAX__=32767} %{mstd:-D__STD_CALL__} %{mint32:-D__INT_MAX__=2147483647}"
-
-#define LINK_SPEC "%{mz8001:-m z8001}"
-
-/* Fetch the libraries from the right place */
-#define LIB_SPEC "-lc"
-
-/* Turn on listing when asked */
-
-#define ASM_SPEC "%{mlist:-ahld}"
-
-/* Print subsidiary information on the compiler version in use.  */
-#define TARGET_VERSION fprintf (stderr, " (z8000)");
-
-
-/* Run-time compilation parameters selecting different hardware subsets.  */
-int target_flags;
-
-/* This means that the target is a Z8001, so we use `big' mode
-   addressing */
-#define TARGET_BIG_BIT 1
-#define TARGET_BIG	(target_flags & TARGET_BIG_BIT)
-
-/* This means that the target is a z8002, so we use `small' mode
-   addressing */
-#define TARGET_SMALL	(!TARGET_BIG)
-
-/* This means that the target is a z8001, and we insert extra to allow
-   objects larger than 64k */
-#define TARGET_HUGE_BIT	2
-#define TARGET_HUGE 	(target_flags & TARGET_HUGE_BIT)
-
-/* This makes ints 32 bits long by default rather than 16 bits */
-#define TARGET_INT32_BIT 4
-#define TARGET_INT32 	(target_flags & TARGET_INT32_BIT)
-
-
-
-/* For debugging: print out how big the compiler thinks each
-   instruction is */
-#define TARGET_ISIZE_BIT 8
-#define TARGET_ISIZE	(target_flags & TARGET_ISIZE_BIT)
-
-/* output YASM syntax assembler rather than gas syntax */
-#define TARGET_YASM_BIT  16
-#define TARGET_YASM 	(target_flags & TARGET_YASM_BIT)
-
-/* pass args in registers rather than on the stack */
-#define TARGET_REGPARMS_BIT 32
-#define TARGET_REGPARMS (target_flags & TARGET_REGPARMS_BIT)
-
-
-/* print .line for each line */
-#define TARGET_LINE_BIT 64
-#define TARGET_LINE (target_flags & TARGET_LINE_BIT)
-
-/* print source for each line */
-#define TARGET_SOURCE_BIT 128
-#define TARGET_SOURCE (target_flags & TARGET_SOURCE_BIT)
-
-/* print defs for each line */
-#define TARGET_DEFS_BIT 256
-#define TARGET_DEFS (target_flags & TARGET_DEFS_BIT)
-
-
-/* print defs for each line */
-#define TARGET_LDIR_BIT 512
-#define TARGET_LDIR (target_flags & TARGET_LDIR_BIT)
-
-/* Nonzero to align doubles on 64 bit boundaries */
-#define TARGET_ALIGN_DOUBLE_BIT 1024
-#define TARGET_ALIGN_DOUBLE (target_flags & TARGET_ALIGN_DOUBLE_BIT)
-
-
-/* Nonzero to generate section pic code */
-#define TARGET_PIC_BIT 2048
-#define TARGET_PIC (target_flags & TARGET_PIC_BIT)
-
-/* print defs for each line */
-#define TARGET_COMBINE_BIT 4096
-#define TARGET_COMBINE (target_flags & TARGET_COMBINE_BIT)
-
-/* chose fast code over small code */
-#define TARGET_FAST_BIT 8192
-#define TARGET_FAST (target_flags & TARGET_FAST_BIT)
-
-/* enable djnz insns */
-#define TARGET_DJNZ_BIT (1<<14)
-#define TARGET_DJNZ (target_flags & TARGET_DJNZ_BIT)
-
-
-
-/* enable byte aligned structures */
-#define TARGET_STRUCT_BYTE_ALIGN_BIT (1<<15)
-#define TARGET_STRUCT_BYTE_ALIGN (target_flags & TARGET_STRUCT_BYTE_ALIGN_BIT)
-
-/* enable 64bit long longs */
-#define TARGET_TYPE64_BIT  	(1<<17)
-#define TARGET_TYPE64		(target_flags & TARGET_TYPE64_BIT)
-
-/* enable 64bit doubles */
-#define TARGET_TYPED64_BIT  	(1<<18)
-#define TARGET_TYPED64		(target_flags & TARGET_TYPED64_BIT)
-
-
-#define TARGET_PCCBITF_BIT  	(1<<19)
-#define TARGET_PCCBITF		(target_flags & TARGET_PCCBITF_BIT)
-
-#define TARGET_STD_FRAME_BIT  	(1<<20)
-#define TARGET_STD_FRAME	(target_flags & TARGET_STD_FRAME_BIT)
-
-#define TARGET_STD_RET_BIT  	(1<<21)
-#define TARGET_STD_RET		(target_flags & TARGET_STD_RET_BIT)
-
-#define TARGET_STD_BIT  	(1<<22)
-#define TARGET_STD		(target_flags & TARGET_STD_BIT)
-
-
-/* Macro to define tables used to set the flags.
-   This is a list in braces of pairs in braces,
-   each pair being { "NAME", VALUE }
-   where VALUE is the bits to set or minus the bits to clear.
-   An empty string NAME is used to identify the default VALUE.  */
-#define TARGET_SWITCHES  			\
-{ { "sb",        TARGET_STRUCT_BYTE_ALIGN_BIT}, \
-  { "nosb",     -TARGET_STRUCT_BYTE_ALIGN_BIT}, \
-  { "pb",        TARGET_PCCBITF_BIT},           \
-  { "nopb",     -TARGET_PCCBITF_BIT},           \
-  { "int32", 	 TARGET_INT32_BIT},		\
-  { "t64", 	 TARGET_TYPE64_BIT},		\
-  { "d64", 	 TARGET_TYPED64_BIT},		\
-  { "int16",    -TARGET_INT32_BIT},		\
-  { "z8001", 	 TARGET_BIG_BIT},		\
-  { "z8002",    -TARGET_BIG_BIT},		\
-  { "huge",	 TARGET_HUGE_BIT},		\
-  { "size",	 TARGET_ISIZE_BIT},		\
-  { "yasm",	 TARGET_YASM_BIT},		\
-  { "line",	 TARGET_LINE_BIT},		\
-  { "source",	 TARGET_SOURCE_BIT},		\
-  { "defs",	 TARGET_DEFS_BIT},		\
-  { "noyasm",	-TARGET_YASM_BIT},		\
-  { "regparms",  TARGET_REGPARMS_BIT},     	\
-  { "ldir",      TARGET_LDIR_BIT},     		\
-  { "combine",   TARGET_COMBINE_BIT},     	\
-  { "fast",      TARGET_FAST_BIT},     		\
-  { "pic",       TARGET_PIC_BIT},     		\
-  { "noldir",   -TARGET_LDIR_BIT},     		\
-  { "djnz",      TARGET_DJNZ_BIT},     		\
-  { "pushargs", -TARGET_REGPARMS_BIT},     	\
-  { "stdfp",     TARGET_STD_FRAME_BIT},     	\
-  { "stdret",    TARGET_STD_RET_BIT},     	\
-  { "std",  	 TARGET_STD_BIT},     		\
-  { "", 	 TARGET_DEFAULT}}
-
-
-#define TARGET_DEFAULT \
- (TARGET_REGPARMS_BIT|TARGET_STRUCT_BYTE_ALIGN_BIT|\
-  TARGET_TYPE64_BIT|TARGET_TYPED64_BIT)
-
-
-/* -m options which take arguments */
-char *call_used_option;
-char *args_in_option;
-char *args_mlist;
-char *fakes_option;
-
-#define TARGET_OPTIONS { { "call-used-",&call_used_option},\
-			 { "args-in", &args_in_option}, \
-			 { "fakes-", &fakes_option}, \
-			 { "list", &args_mlist}}
-
-
-/* Do any checking or such that is needed after processing the -m
-   switches.  */
-#define OVERRIDE_OPTIONS override_options()
-
-/* Define this to change the optimizations performed by default.  */
-
-#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)	\
-{					\
-  if ((LEVEL) >= 1)			\
-    {					\
-      flag_force_mem = 1;		\
-      flag_omit_frame_pointer = 1;	\
-    }					\
-}
-
-
-/* Target machine storage layout */
-
-/* Define to use software floating point emulator for REAL_ARITHMETIC and
-   decimal <-> binary conversion. */
-#define REAL_ARITHMETIC
-
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-
-   There are no such instructions on the z8000, but the documentation
-   is little endian for bits.  */
-#define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.
-   This is true on the z8000.  */
-#define BYTES_BIG_ENDIAN 1
-
-/* Define this if most significant word of a multiword number is lowest
-   numbered.
-
-   For the z8000 this is true */
-#define WORDS_BIG_ENDIAN 1
-
-/* number of bits in an addressable storage unit */
-#define BITS_PER_UNIT 8
-
-/* Width in bits of a "word", which is the contents of a machine register.
-   Note that this is not necessarily the width of data type `int';
-   if using 16-bit ints on a 68000, this would still be 32.
-   But on a machine with 16-bit registers, this would be 16.  */
-#define BITS_PER_WORD 16
-
-/* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD 2
-
-/* Define the size of `short' */
-#define SHORT_TYPE_SIZE 16
-
-/* Define the size of `int'. */
-#define INT_TYPE_SIZE (TARGET_INT32 ? 32 : 16)
-
-/* Define the size of `long'. */
-#define LONG_TYPE_SIZE 32
-
-/* Define the size of `long long' */ 
-#define LONG_LONG_TYPE_SIZE 	 (TARGET_TYPE64 ? 64 : 32)
-
-/* We only support one size of floating-point number, both `float' and
-   `double' are 32 bits long */
-
-#define FLOAT_TYPE_SIZE 	 32
-#define DOUBLE_TYPE_SIZE 	 (TARGET_TYPED64 ? 64 : 32)
-#define LONG_DOUBLE_TYPE_SIZE    64 
-
-#define WCHAR_TYPE "short int"
-#define WCHAR_TYPE_SIZE 16
-
-/* Width in bits of a pointer.
-   See also the macro `Pmode' defined below.  */
-#define POINTER_SIZE (TARGET_BIG ? 32: 16)
-
-/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY 16
-
-/* Boundary (in *bits*) on which stack pointer should be aligned.  */
-#define STACK_BOUNDARY 16
-
-/* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 16
-
-/* Alignment of field after `int : 0' in a structure.  */
-#define EMPTY_FIELD_BOUNDARY 16
-
-/* Every structure's size must be a multiple of this.  */
-#define STRUCTURE_SIZE_BOUNDARY (TARGET_STRUCT_BYTE_ALIGN ? 8 : 16)
-
-/* A bitfield declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS (TARGET_PCCBITF)
-
-/* No data type wants to be aligned rounder than this.  */
-#define BIGGEST_ALIGNMENT 16
-
-/* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  (TREE_CODE (EXP) == STRING_CST	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Set this non-zero if move instructions will actually fail to work
-   when given unaligned data.
- */
-
-#define STRICT_ALIGNMENT 1
-
-
-/* Standard register usage.  */
-
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
-
-   We define 16 integer registers, ignoring the addressable high bytes
-   of r0..r7. 
-
-   The 17th register is the fake arg pointer which has gone by code
-   emission time, and the 18th register is the fake return address
-   pointer which has to be gone by code emission time.
-*/
-
-#define FIRST_PSEUDO_REGISTER 19
-
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   In small mode we pretend that the stack pointer is really in r14,
-   and renumber the r14 and r15 on output.  This allows us to leave it
-   alone when we switch between z8001 and z8002 modes, but still gets
-   the alignment right when in small mode */
-
-#define FIXED_REGISTERS  \
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1}
-
-/* 1 for registers not available across function calls.
-   These must include the FIXED_REGISTERS and also any
-   registers that can be used without being saved.
-   The latter must include the registers where values are returned
-   and the register where structure-value addresses are passed.
-   Aside from that, you can include as many other registers as you like.  */
-
-/* This is filled in in z8k.c since it changes depending upon various
-   -t flags */
-#define CALL_USED_REGISTERS  \
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1}
-
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.  */
-
-#define HARD_REGNO_NREGS(REGNO, MODE)   \
-  (((REGNO)==ARG_POINTER_REGNUM) ? 1 :((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
-
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
-   MODE. */
-
-extern int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
-   ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
-
-
-/* Value is 1 if it is a good idea to tie two pseudo registers
-   when one has mode MODE1 and one has mode MODE2.
-   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
-   for any hard reg, then this must be 0 for correct output.  */
-
-#define MODES_TIEABLE_P(MODE1, MODE2)  1
-
-/* Specify the registers used for certain standard purposes.
-   The values of these macros are register numbers.  */
-
-/* z8000 pc isn't overloaded on a register that the compiler knows about.  */
-/* #define PC_REGNUM  */
-
-/* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM 14
-
-/* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 10
-
-/* Value should be nonzero if functions must have frame pointers.
-   Zero means the frame pointer need not be set up (and parms
-   may be accessed via the stack pointer) in functions that seem suitable.
-   This is computed in `reload', in reload1.c.  */
-#define FRAME_POINTER_REQUIRED 0
-
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM  16
-
-/* Fake register that holds the address on the stack of the
-   current function's return address.  */
-#define RETURN_ADDRESS_POINTER_REGNUM 18
-
-/* Register in which static-chain is passed to a function.
-
-   For the z8000 this hasn't been tested */
-#define STATIC_CHAIN_REGNUM 0
-
-/* Register in which address to store a structure value
-   arrives in the function.  On the z8000, the address is passed
-   as a hidden argument.  */
-#define STRUCT_VALUE 0
-
-/* Define the classes of registers for register constraints in the
-   machine description.  Also define ranges of constants.
-
-   One of the classes must always be named ALL_REGS and include all hard regs.
-   If there is more than one class, another class must be named NO_REGS
-   and contain no registers.
-
-   The name GENERAL_REGS must be the name of a class (or an alias for
-   another name such as ALL_REGS).  This is the class of registers
-   that is allowed by "g" or "r" in a register constraint.
-   Also, registers outside this class are allocated only when
-   instructions express preferences for them.
-
-   The classes must be numbered in nondecreasing order; that is,
-   a larger-numbered class must never be contained completely
-   in a smaller-numbered class.
-
-   For any two classes, it is very desirable that there be another
-   class that represents their union.  */
-
-/* ??? If we need two DFmode/DImode reloads, then they must go into
-   2/3/4/5 and 6/7/8/9.  If the first goes into 4/5/6/7 we lose.
-   We put 4 early, so that it will be more likely to be used for
-   register allocation, and thus less likely to be used for reloads.  */
-#define REG_ALLOC_ORDER { 4,5,2,3,0,1,6,7,8,9,10,11,12,13,14,15,16,17}
-/* ??? In order to make sure that we can allocate 2 group 4 reloads, put
-   regs 2-9 last.  */
-/* ??? Hack, see reload1.c.  */
-#define RELOAD_ALLOC_ORDER { 0,1,12,13,2,3,4,5,6,7,8,9,10,11,14,15,16,17}
-
-#define GENERAL_REGS ALL_REGS
-enum reg_class { NO_REGS, SQI_REGS, QI_REGS,NOTQI_REGS, SP_REGS, PTR_REGS, SP_QI_REGS, ALL_REGS, LIM_REG_CLASSES };
-
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
-
-/* Give names of register classes as strings for dump file.   */
-
-#define REG_CLASS_NAMES				\
- {"NO_REGS", "SQI_REGS", "QI_REGS", "NOTQI_REGS", "SP_REGS", "PTR_REGS", "SP_QI_REGS", "ALL_REGS" }
-
-/* Define which registers fit in which classes.
-   This is an initializer for a vector of HARD_REG_SET
-   of length N_REG_CLASSES.  */
-
-#define REG_CLASS_CONTENTS		\
-{	0x00000, /* NO_REGS  */ 	\
-	0x000fe, /* SQI_REGS  */ 	\
-	0x000ff, /* QI_REGS  */ 	\
-      	0x0c000, /* SP_REGS  */ 	\
-	0x0ff00, /* NOTQI_REGS  */ 	\
-      	0x1fffe, /* PTR_REGS */	 	\
-	0x0c0ff, /* SP_QI_REGS */	\
-        0x1ffff }
-
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-#define REGNO_REG_CLASS(REGNO) \
-    (((REGNO) == 14 || (REGNO) == 15) ? SP_REGS :  \
-     (REGNO >= 8 && REGNO <= 13) ? NOTQI_REGS :  \
-     (REGNO > 15) ? PTR_REGS :  \
-     (REGNO == 0) ? QI_REGS :  \
-     SQI_REGS) 
-
-/* The class value for index registers, and the one for base regs.  */
-#define INDEX_REG_CLASS  PTR_REGS
-#define BASE_REG_CLASS   PTR_REGS
-
-/* When defined, the compiler allows registers explicitly used in the
-   rtl to be used as spill registers but prevents the compiler from
-   extending the lifetime of these registers. */
-#define SMALL_REGISTER_CLASSES 1
-
-
-/* Get reg_class from a letter such as appears in the machine description.  */
-
-#define REG_CLASS_FROM_LETTER(C)		\
-  ((C) == 'u' ? QI_REGS  : 			\
-  ((C) == 'v' ? PTR_REGS :			\
-  ((C) == 'q' ? SP_REGS  :			\
-  ((C) == 'r' ? GENERAL_REGS  :			\
-  (NO_REGS)))))
-
-
-/* Define this macro to change register usage conditional on target flags.  */
-#define CONDITIONAL_REGISTER_USAGE
-
-/* The letters I, J, K, L, M, N, O, and P in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
-   This macro defines what the ranges are.
-   C is the letter, and VALUE is a constant value.
-   Return 1 if VALUE is in the range specified by C.
-
-   For z8k
-   `I' is the constant 0.
-   `J' is a constant for an inc (1..16)
-   `K' is a constant for a dec  (-1..-16)
-   `L' is 0..15, used in shifts and ldk
-   `M' is the constant 1, used in shifts
-   `N' is the constant 2, used in shifts
-   `O' is a power of two
-   `P' is a comp power of two
-*/
-#define POWER_OF_2(I) ((I) && POWER_OF_2_or_0(I))
-#define POWER_OF_2_or_0(I) (((I) & ((unsigned)(I) - 1)) == 0)
-
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)				\
-    ((C) == 'I' ? (VALUE) == 0   				\
-   : (C) == 'J' ? (VALUE) >=  1  && (VALUE) <=  16 		\
-   : (C) == 'K' ? (VALUE) <= -1  && (VALUE) >= -16 		\
-   : (C) == 'L' ? (VALUE) >=  0  && (VALUE) <=  15 		\
-   : (C) == 'M' ? (VALUE) ==  1					\
-   : (C) == 'N' ? (VALUE) ==  2					\
-   : (C) == 'O' ? POWER_OF_2(VALUE)                           	\
-   : (C) == 'P' ? COM_POWER_OF_2(VALUE)                         \
-   : 0)
-
-
-/* Similar, but for floating or large integer constants, and defining letters
-   G and H.   Here VALUE is the CONST_DOUBLE rtx itself.
-
-   For z8k, we don't have anything special here */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
-
-/* Given an rtx X being reloaded into a reg required to be
-   in class CLASS, return the class of reg to actually use.
-   In general this is just CLASS; but on some machines
-   in some cases it is preferable to use a more restrictive class.
-
-   On the z8k, it's better to have characters in the QI_REGS. */
-
-#define PREFERRED_RELOAD_CLASS(X, CLASS) \
-   ((GET_MODE(X) == QImode) ? QI_REGS : CLASS)
-
-/* Return the register class of a scratch register needed to copy IN into
-   or out of a register in CLASS in MODE.  If it can be done directly,
-   NO_REGS is returned.  */
-
-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
-  (secondary_reload_class (CLASS, MODE, IN))
-
-
-/* Place additional restrictions on the register class to use when it
-   is necessary to be able to hold a value of mode MODE in a reload
-   register for which class CLASS would ordinarily be used. */
-
-/*#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
-  ((MODE) == QImode && ((CLASS) == GENERAL_REGS) \
-   ? QI_REGS : (CLASS))
-*/
-/* Return the maximum number of consecutive registers
-   needed to represent mode MODE in a register of class CLASS.  */
-
-#define CLASS_MAX_NREGS(CLASS, MODE)				\
-	 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-/* Define the cost of moving between registers of various classes. 
-   
-   moving between QI_REGS and anything else may be expensive since the
-   other regs don't do QI mode too well */
-
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)  ((CLASS1) == (CLASS2) ? 2: 5) 
-
-/* A C expressions returning the cost of moving data of MODE from a register to
-   or from memory. */
-
-/*#define MEMORY_MOVE_COST(MODE,CLASS,IN)  6*/
-
-/* Provide the cost of a branch.  Exact meaning under development.  */
-/*#define BRANCH_COST 5*/
-
-
-/* Stack layout; function entry, exit and calling.  */
-
-/* Define this if pushing a word on the stack
-   makes the stack pointer a smaller address.  */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
-   is at the high-address end of the local variables;
-   that is, each additional local variable allocated
-   goes at a more negative offset in the frame.  */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
-   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
-   first local allocated.  Otherwise, it is the offset to the BEGINNING
-   of the first local allocated.  */
-
-#define STARTING_FRAME_OFFSET 0
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-
-   On the z8k, we always push words */
-
-#define PUSH_ROUNDING(X) (((X) + 1) & ~1)
-
-/* Define this if the maximum size of all the outgoing args is to be
-   accumulated and pushed during the prologue.  The amount can be
-   found in the variable current_function_outgoing_args_size.  */
-
-/*#define ACCUMULATE_OUTGOING_ARGS*/
-
-
-/* Offset of first parameter from the argument pointer register value.
-   */
-
-
-
-#define ELIMINABLE_REGS \
-{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},			\
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},			\
- { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},	\
- { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM},	\
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
-
-
-#define CAN_ELIMINATE(FROM, TO)						\
- (!frame_pointer_needed							\
-  || ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)	\
-  || ((FROM) == RETURN_ADDRESS_POINTER_REGNUM				\
-      && (TO) == FRAME_POINTER_REGNUM))
-
-
-/* On the z8k, the first parm is offset by the saved return address
-   and the frame pointer - but we use eliminable regs so it should be 0*/
-
-#define FIRST_PARM_OFFSET(FNDECL) 0
-
-/* Define the offset between two registers, one to be eliminated, and the other
-   its replacement, at the start of a routine.  */
-
-
-#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) OFFSET=io(FROM,TO);
-
-
-		
-/* Define this if stack space is still allocated for a parameter passed
-   in a register.  */
-/** #define REG_PARM_STACK_SPACE */
-
-/* Value is the number of bytes of arguments automatically
-   popped when returning from a subroutine call.
-   FUNTYPE is the data type of the function (as a tree),
-   or for a library call it is an identifier node for the subroutine name.
-   SIZE is the number of bytes of arguments passed on the stack.  */
-
-#define RETURN_POPS_ARGS(FNDECL,FUNTYPE,SIZE) 0
-
-
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.
-
-   Two ways to return on the Z8k. in r2/rr2/rq2 for HI, SI, DI stuff
-   or r7/rr6/rq4 stuff.
-
-*/
-
-#define FUNCTION_VALUE(VALTYPE, FUNC)	\
-  LIBCALL_VALUE (TYPE_MODE (VALTYPE))
-
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  */
-
-
-#define LIBCALL_VALUE(MODE) \
-  gen_rtx (REG, MODE, \
-	    (TARGET_STD_RET ? (GET_MODE_SIZE (MODE) <= GET_MODE_SIZE(HImode) ? 7 : \
-			       GET_MODE_SIZE (MODE) <= GET_MODE_SIZE(SImode) ? 6 : 4) : 2))
-
-/* 1 if N is a possible register number for a function value
-   as seen by the caller.  */
-
-#define FUNCTION_VALUE_REGNO_P(N) (TARGET_STD_RET ? ((N) >= 4 && ((N) <= 7)) : (N) == 2)
-
-
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   On z8k, this is a single integer, which is a number of words
-   of arguments scanned so far. */
-
-
-#define CUMULATIVE_ARGS  int 
-
-
-/* Initialize a variable CUM of type CUMULATIVE_ARGS
-   for a call to a function whose data type is FNTYPE.
-
-*/
-
-#define NPARM_REGS 6
-
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
-  (CUM) = 7 ;
-
-
-/* Determine where to put an argument to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-
-*/
-
-extern struct rtx_def* z8k_function_arg();
-
-#define FUNCTION_ARG(CUM,MODE,TYPE,NAMED) \
-	z8k_function_arg(CUM,MODE,TYPE,NAMED)
-
-
-
-
-extern int arg_regs[FIRST_PSEUDO_REGISTER];
-#define FUNCTION_ARG_REGNO_P(N) arg_regs[N]
-
-#define FUNCTION_ARG_ADVANCE(CUM,MODE,TYPE,NAMED)\
-  CUM=faa(CUM,MODE,TYPE,NAMED)
-
-/* Round a register number down to a proper boundary for an arg of mode 
-   MODE. 
-   
-   We round down to an even reg for things larger than a word */
-
-#define ROUND_REG(X, MODE) 					\
-  ((TARGET_ALIGN_DOUBLE 					\
-   && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) 		\
-   ? ((X) - ((X) & 1)) : (X))
-
-#define ROUND_ADVANCE(SIZE)	\
-  ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
-
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) ; 
-
-
-/* Output assembler code to FILE to increment profiler label # LABELNO
-   for profiling a function entry.  */
-
-#define FUNCTION_PROFILER(FILE, LABELNO)
-
-
-/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
-   the stack pointer does not matter.  The value is tested only in
-   functions that have frame pointers.
-   No definition is equivalent to always zero.  */
-
-#define EXIT_IGNORE_STACK 0
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE)	;
-
-
-/* Output assembler code for a block containing the constant parts
-   of a trampoline, leaving space for the variable parts.
-
-   big model
-
-   1              		.z8001
-   2 0000 14001234 		ldl	rr0,#0x12345678
-   2      5678
-   3 0006 5E008000 		jp	t,foo
-   3      0000
-   4 000c 0000     		
-
-  small model
-
-   1              		.z8002
-   2 0000 21001234 		ld	r0,#0x1234
-   3 0004 5E000000 		jp	t,foo
-   4 0008 0000     		
-
-
- */
-
-#define TRAMPOLINE_TEMPLATE(FILE)		                        \
-{									\
-  if (TARGET_BIG)  							\
-    {									\
-      fprintf (FILE,"	ldl	rr0,#0x12345678\n");			\
-      fprintf (FILE,"	jp	t,0x12345678\n");			\
-    }									\
-  else 									\
-    {									\
-      fprintf (FILE,"	ld	r0,#0x1234\n");				\
-      fprintf (FILE,"	jp	t,0x1234\n");				\
-    }									\
-}									  
-									 
-/* Length in units of the trampoline for entering a nested function.  */
-
-#define TRAMPOLINE_SIZE    (TARGET_BIG ? 12 : 8)
-
-
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  We assume
-   here that a function will be called many more times than its address
-   is taken (e.g., it might be passed to qsort), so we take the trouble
-   to initialize the "hint" field in the JMP insn.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)                             	\
-{		        							\
-   if (TARGET_BIG) 								\
-     {										\
-       emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 2)), CXT); 	\
-       emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 8)), FNADDR);\
-     }										\
-   else 									\
-     {										\
-       emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 2)), CXT); 	\
-       emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 6)), FNADDR);\
-     }										\
- }										\
-
-										 
-#define RETURN_ADDR_RTX(count, frame)						\
-  ((count == 0)									\
-   ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))	\
-   : (rtx) 0)
-
-/* Addressing modes, and classification of registers for them.  */
-
-/* #define HAVE_POST_INCREMENT 0 */
-/* #define HAVE_POST_DECREMENT 0 */
-
-/* #define HAVE_PRE_DECREMENT 0 */
-/* #define HAVE_PRE_INCREMENT 0 */
-
-/* Macros to check register numbers against specific register classes.  */
-
-/* These assume that REGNO is a hard or pseudo reg number.
-   They give nonzero only if REGNO is a hard reg of the suitable class
-   or a pseudo reg currently allocated to a suitable hard reg.
-   Since they use reg_renumber, they are safe only once reg_renumber
-   has been allocated, which happens in local-alloc.c.  */
-
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-	  (((REGNO) < FIRST_PSEUDO_REGISTER) \
-	    || (reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER && reg_renumber[REGNO] >= 0))
-
-
-/* It's ok for a base reg if it's in a hard reg which is not 0 or it
-   will be renumbered on the way out and its not -1 or 0 */
-
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-	  (((REGNO) < FIRST_PSEUDO_REGISTER && (REGNO) != 0 )  \
-	    || (reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER && reg_renumber[REGNO] > 0))
- 
-
-/* Maximum number of registers that can appear in a valid memory address.  */
-#define MAX_REGS_PER_ADDRESS 1
-
-
-/* Recognize any constant value that is a valid address.
-
-   For the z8k, any constant is a valid address */
-
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
-   || GET_CODE (X) == HIGH)
-
-/* Include all constant integers and constant doubles, but not
-   floating-point, except for floating-point zero.  */
-
-#define LEGITIMATE_CONSTANT_P(X)  (GET_CODE(X) != CONST_DOUBLE)
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
-   and check its validity for a certain class.
-   We have two alternate definitions for each of them.
-   The usual definition accepts all pseudo regs; the other rejects
-   them unless they have been allocated suitable hard regs.
-   The symbol REG_OK_STRICT causes the latter definition to be used.
-
-   Most source files want to accept pseudo regs in the hope that
-   they will get allocated to the class that the insn wants them to be in.
-   Source files for reload pass need to be strict.
-   After reload, it makes no difference, since pseudo regs have
-   been eliminated by then.  */
-
-#ifndef REG_OK_STRICT
-
-#define IS_STRICT 0
-/* Nonzero if X is a hard reg that can be used as an index
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_INDEX_P(X)  (REGNO (X) > FIRST_PSEUDO_REGISTER)
-
-/* Nonzero if X is a hard reg that can be used as a base reg
-   or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) \
-  ( GET_MODE(X) == Pmode && ( REGNO(X) > FIRST_PSEUDO_REGISTER || (REGNO(X) != 0)))
-
-#else
-#define IS_STRICT 1
-/* Nonzero if X is a hard reg that can be used as an index.  */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg.  */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-
-#endif
-
-/* 'Q' ir or da     PTR reg or direct address
-   'R' x            address + HI reg - never valid in huge mode
-   'S' ba or bx     disp + PTR reg   (or PTR reg + reg never in huge)
-   'T' ba
- */
-
-#define INSIDE(op,side) XEXP(op,side)
-
-/* Also accept (MEM (pseudo)) here during reload, because the psuedo is
-   guaranteed to be reloaded into a PTR reg.  */
-#define IR_P(op) 							\
-  (GET_CODE (op) == MEM							\
-   && ((REG_P (XEXP (op, 0)) && REG_OK_FOR_BASE_P (XEXP (op, 0)))	\
-       || (reload_in_progress && GET_CODE (XEXP (op, 0)) == REG		\
-	   && REGNO (op) >= FIRST_PSEUDO_REGISTER)))
-	  
-
-#define INSIDE_DA_P(op) DATA_REF_P(op)
-
-#define DA_P(op)				\
-	((GET_CODE(op) == MEM) && DATA_REF_P(INSIDE(op,0)))
-
-
-#define X_P(op) x_p(op, IS_STRICT)
-
-/* ptr sized reg + 16 bit index 
- only ok in huge mode if reg is sp */
-
-/* Also accept unallocated pseudo-regs here, since these will become
-   references to sp plus an offset.  */
-/* Also accept (MEM (PLUS (pseudo) CONST_INT)), since the pseudo will
-   always be allocated to a PTR reg.  We can not do this in inside_ba_p,
-   because then it would affect GO_IF_LEGITIMATE_ADDRESS which is wrong.  */
-#define BA_P(op)					\
-  (ba_p (op, IS_STRICT)					\
-   || (reload_in_progress && GET_CODE (op) == REG	\
-       && REGNO (op) >= FIRST_PSEUDO_REGISTER)		\
-   || (reload_in_progress && GET_CODE (op) == MEM	\
-       && GET_CODE (XEXP (op, 0)) == PLUS		\
-       && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG	\
-       && REGNO (op) >= FIRST_PSEUDO_REGISTER		\
-       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT \
-       && (INTVAL (XEXP (XEXP (op, 0), 1)) & 0x1) == 0))
-
-/* ptr sized reg + sign extended int reg */
-
-
-#define BX_P(op) bx_p(op, IS_STRICT)
-
-
-
-#define EXTRA_CONSTRAINT(op, c)                                 \
-	(((c) == 'Q')  ? (IR_P(op) || DA_P(op)) :               \
-        (((c) == 'R')  ? (X_P(op))  :                           \
-        (((c) == 'T')  ? (BA_P(op))  :                          \
-        (((c) == 'S')  ? (BA_P(op) || BX_P(op)) : 0))))
-
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
-   that is a valid memory address for an instruction.
-   The MODE argument is the machine mode for the MEM expression
-   that wants to use this address.
- 
-*/
-
-/* in any mode the z8k allows
-	(reg)			eg ld	r0,(r0)
-	(da)			eg ld  	r0,foo
-	(reg+disp)		eg ld	r0,rr2(#8)
-	(pre-dec of the sp)	eg push	sp,#9
-
-   in non huge mode we can also 
-        (pre-dec of any reg)	eg push r0,#9
-        (address+reg)		eg ld	r0,address(r0)
-   in small mode    
-	(reg+reg)		eg ld	r0,r1(r0)
-
-
-*/
-
-/* true if the value may be used as a displacement (-32768<=x<=32767)
-
-   (can also be a displacement if it's a symbol and we're in small
-   mode */
-
-#define DISP_P(X) disp_p(X)
-
-#define DATA_REF_P_1(X) data_ref_p_1(X)
-#define DATA_REF_P(X) data_ref_p(X)
-
-
-
-
-#define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
-{ if (REG_P (X) && REG_OK_FOR_BASE_P (X))	\
-    goto ADDR;					\
-  if (INSIDE_DA_P(X)) goto ADDR;		\
-  if (inside_ba_p(X,IS_STRICT)) goto ADDR;		\
-  if (GET_CODE(X) == PRE_DEC 			\
-      && MODE==HImode 				\
-      && REGNO(XEXP(X,0))==STACK_POINTER_REGNUM) goto ADDR;\
-}
-
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)              \
-{                                                            \
-  GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); 	     \
-   if(GET_CODE(X)==PRE_DEC				     \
-       && MODE==HImode					     \
-       && REG_OK_FOR_BASE_P(XEXP(X,0))) goto ADDR; 	     \
-   if (inside_x_p(X,IS_STRICT)) goto ADDR;			     \
-   if (GET_MODE_SIZE(MODE) <= 4 && inside_bx_p(X,IS_STRICT)) goto ADDR;	    \
-}							     \
-							     \
-   							      
-      
-/* Try machine-dependent ways of modifying an illegitimate address
-   to be legitimate.  If we find one, return the new, valid address.
-   This macro is used in only one place: `memory_address' in explow.c.
-
-   OLDX is the address as it was before break_out_memory_refs was called.
-   In some cases it is useful to look at this to decide what needs to be done.
-
-   MODE and WIN are passed so that this macro can use
-   GO_IF_LEGITIMATE_ADDRESS.
-
-   It is always safe for this macro to do nothing.  It exists to recognize
-   opportunities to optimize the output.
-
-*/
-extern struct rtx_def *legitimize_address();
-
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)	 x = legitimize_address(oldx,mode)
-
-
-/* Go to LABEL if ADDR (a legitimate address expression)
-   has an effect that depends on the machine mode it is used for.
-
-
-   For the z8k, pushing and poping needs to know the mode */
-
-
-#define GO_IF_MODE_DEPENDENT_ADDRESS(A,L)	\
- { if (GET_CODE (A) == POST_INC || GET_CODE (A) == PRE_DEC) goto L;  }
-
-
-/* Compute the cost of an address. */
-
-/* For z8k, it is better to use a complex address than let gcc copy
-   the address into a reg and make a new pseudo.  But not if the address
-   requires to two regs - that would mean more pseudos with longer
-   lifetimes.  */
-
-#define ADDRESS_COST(RTX) address_cost(RTX)
-
-
-/* Define this if some processing needs to be done immediately before
-   emitting code for an insn.  */
-
-/* We use when asked to print out how big the compiler thought the
-   instructions were */
-
-#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS)            \
-{							       \
-  static int old = 0;					       \
-  extern int *insn_addresses;				       \
-  int uid = INSN_UID (INSN);				       \
-  if (TARGET_ISIZE && insn_addresses)			       \
-  {							       \
-    fprintf (asm_out_file, "! %d %d\n", insn_addresses[uid],   \
-	     insn_addresses[uid] - old);		       \
-    old = insn_addresses[uid];				       \
-  }							       \
-}							       \
-							        
-
-
-/* Specify the machine mode that this machine uses
-   for the index in the tablejump instruction.  */
-#define CASE_VECTOR_MODE HImode 
-
-/* Define as C expression which evaluates to nonzero if the tablejump
-   instruction expects the table to contain offsets from the address of the
-   table.
-   Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE  1
-
-/* Specify the tree operation to be used to convert reals to integers.  */
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* This is the kind of divide that is easiest to do in the general case.  */
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
-/* Define this as 1 if `char' should by default be signed; else as 0.  */
-#define DEFAULT_SIGNED_CHAR 0
-
-/* This flag, if defined, says the same insns that convert to a signed fixnum
-   also convert validly to an unsigned one.
-
-   We actually lie a bit here as overflow conditions are different.  But
-   they aren't being checked anyway.  */
-
-#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
-
-/* Max number of bytes we can move to or from memory
-   in one reasonably fast instruction.  */
-
-#define MOVE_MAX 4
-
-/* Largest number of bytes of an object that can be placed in a register.
- */
-#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (SImode)
-
-/* Nonzero if access to memory by bytes is no faster than for words.
-   Also non-zero if doing byte operations (specifically shifts) in registers
-   is undesirable.
-
-*/
-
-#define SLOW_BYTE_ACCESS	1
-
-/* Define if normal loads of shorter-than-word items from memory clears
-   the rest of the bits in the register.  */
-/*#define BYTE_LOADS_ZERO_EXTEND  */
-
-/* Define if normal loads of shorter-than-word items from memory sign-extends
-   the rest of the bits in the register.  */
-/*#define BYTE_LOADS_SIGN_EXTEND*/
-
-#define SDB_DEBUGGING_INFO 
-
-/* Output DBX (stabs) debugging information if using -gstabs.  */
-
-#include "dbxcoff.h"
-
-/* Do not break .stabs pseudos into continuations.  */
-#define DBX_CONTIN_LENGTH 0
-
-/* Don't try to use the `x' type-cross-reference character in DBX data.
-   Also has the consequence of putting each struct, union or enum
-   into a separate .stabs, containing only cross-refs to the others.  */
-#define DBX_NO_XREFS
-
-/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
-   is done just by pretending it is already truncated.  */
-#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-
-/* We assume that the store-condition-codes instructions store 0 for false
-   and some other value for true.  This is the value stored for true.  */
-
-#define STORE_FLAG_VALUE 1
-
-/* Define the value returned by a floating-point comparison instruction.  */
-
-/*#define FLOAT_STORE_FLAG_VALUE 0.5*/
-
-/* Specify the machine mode that pointers have.
-   After generation of rtl, the compiler makes no further distinction
-   between pointers and any other objects of this machine mode.  */
-
-
-int pmode;
-#define Pmode pmode  /* set in z8k.c */
-#define Imode HImode
-/* Mode of a function address in a call instruction (for indexing purposes). */
-
-#define FUNCTION_MODE QImode
-
-/* Define this if addresses of constant functions
-   shouldn't be put through pseudo regs where they can be cse'd.
-   Desirable on machines where ordinary constants are expensive
-   but a CALL with constant address is cheap. */
-#define NO_FUNCTION_CSE
-
-/* Define this if shift instructions ignore all but the low-order
-   few bits. */
-/*#define SHIFT_COUNT_TRUNCATED*/
-
-/* Compute the cost of computing a constant rtl expression RTX
-   whose rtx-code is CODE.  The body of this macro is a portion
-   of a switch statement.  If the code is computed here,
-   return it with a return statement.  Otherwise, break from the switch.
-
-   We only care about the cost if it is valid in an insn, so all constants
-   are cheap.  */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
-  case CONST_INT:						\
-       if (CONST_OK_FOR_LETTER_P(INTVAL(RTX), 'I')) return 0;   \
-       if (CONST_OK_FOR_LETTER_P(INTVAL(RTX), 'L')) return 1;   \
-   return 2;                                                    \
-  case CONST_DOUBLE:						\
-  return 8;							\
-  case SYMBOL_REF:						\
-  case LABEL_REF:						\
-    return 30;							\
-  case CONST:  							\
-    return 2;
-
-/* Provide the costs of a rtl expression.  This is in the body of a
-   switch on CODE.  */
-
-#define RTX_COSTS(X,CODE,OUTER_CODE)			\
-  case PLUS:						\
-  case MINUS:						\
-    break;						\
-  case MULT:						\
-  return COSTS_N_INSNS (10);				\
-  case DIV:						\
-  case UDIV:						\
-  case MOD:						\
-  case UMOD:						\
-      return COSTS_N_INSNS (TARGET_FAST ? 17 : 2);	
-
-/* Control the assembler format that we output.  */
-
-/* Output at beginning of assembler file.  */
-
-/* Z8000 CPU Section Name */
-#define SECTION_NAME (z8k_sect.sect_name != 0 && strlen(z8k_sect.sect_name) > 0	\
-                      ? z8k_sect.sect_name : "not")
-
-#define ASM_FILE_START(STREAM) 							\
-  asm_file_start (STREAM, f_options, sizeof f_options / sizeof f_options[0], \
-		     W_options, sizeof W_options / sizeof W_options[0]); 	
-
-
-
-#define ASM_FILE_END(file) asm_file_end(file)
-  
-/* Output to assembler file text saying following lines
-   may contain character constants, extra white space, comments, etc.  */
-
-#define ASM_APP_ON ""
-
-/* Output to assembler file text saying following lines
-   no longer contain unusual constructs.  */
-
-#define ASM_APP_OFF ""
-
-#define TEXT_SECTION_ASM_OP 		(TARGET_YASM ? "\trsect\tUSRROM" : "\t.text")
-#define CTORS_SECTION_ASM_OP 		(TARGET_YASM ?"\trsect\t.CTORS" : "\t.section\t.ctors")
-#define DTORS_SECTION_ASM_OP 		(TARGET_YASM ?"\trsect\t.DTORS" : "\t.section\t.dtors")
-#define READONLY_DATA_SECTION_ASM_OP  	(TARGET_YASM ? "\trsect\tUSRROM" : "\tsect .rdata")
-#define INIT_SECTION_ASM_OP 		(TARGET_YASM ? "\trsect\tINIT" : "\t.init")
-/* Output before writable data.  */
-
-#define DATA_SECTION_ASM_OP (TARGET_YASM ? "\tsect\tUSRRAM" : "\t.data")
-
-/* Define an extra section for read-only data, a routine to enter it, and
-   indicate that it is for read-only data.  */
-
-#define EXTRA_SECTIONS	readonly_data, in_ctors, in_dtors
-
-#define EXTRA_SECTION_FUNCTIONS					\
-void							     \
-ctors_section() 					     \
-{							     \
-  if (in_section != in_ctors)				     \
-    {							     \
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);  \
-      in_section = in_ctors;				     \
-    }							     \
-}							     \
-void							     \
-dtors_section() 					     \
-{							     \
-  if (in_section != in_dtors)				     \
-    {							     \
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);  \
-      in_section = in_dtors;				     \
-    }							     \
-}								\
-void								\
-literal_section ()						\
-{								\
-  if (in_section != readonly_data)				\
-    {								\
-      fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
-      in_section = readonly_data;				\
-    }								\
-}								\
-
-#define READONLY_DATA_SECTION	literal_section
-
-#define ASM_OUTPUT_PTR(FILE,NAME) \
- do { fprintf (FILE, "\t%s\t_%s\n", TARGET_BIG ? "lval" : "wval", NAME);} while(0)
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)	\
-   do { ctors_section();  ASM_OUTPUT_PTR(FILE, NAME); } while (0)
-
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)	\
-   do {  dtors_section(); ASM_OUTPUT_PTR(FILE, NAME); } while (0)
-
-
-#undef DO_GLOBAL_CTORS_BODY                     
-#define DO_GLOBAL_CTORS_BODY			\
-{						\
-  typedef (*pfunc)();				\
-  extern pfunc __ctors[];			\
-  extern pfunc __ctors_end[];			\
-  pfunc *p;					\
-  for (p = __ctors_end; p > __ctors; )		\
-    {						\
-      (*--p)();					\
-    }						\
-}						
-
-#undef DO_GLOBAL_DTORS_BODY			 
-#define DO_GLOBAL_DTORS_BODY                    \
-{						\
-  typedef (*pfunc)();				\
-  extern pfunc __dtors[];			\
-  extern pfunc __dtors_end[];			\
-  pfunc *p;					\
-  for (p = __dtors; p < __dtors_end; p++)	\
-    {						\
-      (*p)();					\
-    }						\
-}						 
-
-
-
-/* How to refer to registers in assembler output.
-   This sequence is indexed by compiler's hard-register-number (see above).  */
-
-#define REGISTER_NAMES						\
-{ "r0","r1","r2","r3","r4","r5","r6","r7", 			\
-   "r8","r9","r10","r11","r12","r13","r14","r15","apl","aph","rap"}
-
-/* How to renumber registers for dbx and gdb.  */
-
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
-
-/* This is how to output the definition of a user-level label named NAME,
-   such as the label on a static function or variable NAME.  */
-
-#define ASM_OUTPUT_LABEL(FILE,NAME)	\
-  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
-/* This is how to output a command to make the user-level label named NAME
-   defined for reference from other files.  */
-
-#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
-  do { fputs ("\tglobal\t", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
-
-/* A C statement to output to the stdio stream STREAM any text necessary
-   for declaring the name of an external symbol named NAME which is referenced
-   in this compilation but not defined. */
-#define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME)\
-   do { if (TARGET_YASM) z8k_output_external (NAME); } while (0)
-
-/* Similar, but for libcalls.  */
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
-   do { if (TARGET_YASM) z8k_output_external (XSTR (FUN, 0)); } while (0)
-
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
-
-#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
-  fprintf (FILE, TARGET_YASM ? "%s" : "_%s", NAME)
-
-/* This is how to output an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.  */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-    fprintf (FILE, "E%s%d:\n", PREFIX, NUM)
-
-/* This is how to output a label for a jump table.  Arguments are the same as
-   for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
-   passed. */
-
-/*#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN)	\
-{ ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }*/
-
-/* This is how to store into the string LABEL
-   the symbol_ref name of an internal numbered label where
-   PREFIX is the class of label and NUM is the number within the class.
-   This is suitable for output with `assemble_name'.  */
-
-
-#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  sprintf (LABEL, "*E%s%d", PREFIX, NUM)
-
-/* This is how to output an assembler line defining a `double' constant.  */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.double %s\n", dstr);		\
-   } while (0)
-
-
-/* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)			\
-do { char dstr[30];					\
-     REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr);	\
-     fprintf (FILE, "\t.float %s\n", dstr);		\
-   } while (0)
-
-
-/* This is how to output an assembler line defining an 4 byte constant.  */
-
-#define ASM_OUTPUT_INT(FILE,VALUE)  \
-( fprintf (FILE, "\tlval "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* Likewise for `char' and `short' constants.  */
-
-#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
-( fprintf (FILE, "\twval "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-#define ASM_OUTPUT_CHAR(FILE,VALUE)		\
-( fprintf (FILE, "\tbval "),			\
-  output_addr_const (FILE, (VALUE)),		\
-  fprintf (FILE, "\n"))
-
-/* We use the default ASCII-output routine, except that we don't write more
-   than 50 characters since the assembler doesn't support very long lines.  */
-
-/* A C statement to output to the stdio stream STREAM an assembler instruction
-   to assemble a string constant containing the LEN bytes at PTR. */
-#define ASM_OUTPUT_ASCII(FILE, P, SIZE)				\
-  asm_output_ascii (FILE, P, SIZE)
-
-/* This is how to output an insn to push a register on the stack.
-   It need not be very fast code.  */
-
-
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
- fprintf (FILE, "\tpushl %s\n", reg_names[REGNO])
-
-/* This is how to output an insn to pop a register from the stack.
-   It need not be very fast code.  */
-
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
- fprintf (FILE, "\tmovl (sp)+,%s\n", reg_names[REGNO])
-
-
-/* This is how to output an assembler line for a numeric constant byte.  */
-
-#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\tbval %d\n", (VALUE))
-
-/* This is how to output an element of a case-vector that is absolute.  */
-
-#define JUMP_TABLES_IN_TEXT_SECTION 1
-
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-  fprintf (FILE, "\t%s EL%d\n", TARGET_BIG ? "lval":"wval", VALUE)
-
-/* This is how to output an element of a case-vector that is relative.
-   (Alpha does not use such vectors, but we must define this macro anyway.)  */
-
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
-  fprintf (FILE, "\twval EL%d-EL%d\n", VALUE, REL)
-
-extern char *z8k_asm_output_opcode();
-#define ASM_OUTPUT_OPCODE(f,s) s = z8k_asm_output_opcode(f,s)
-
-/* This is how to output an assembler line
-   that says to advance the location counter
-   to a multiple of 2**LOG bytes.  */
-
-
-#define ASM_OUTPUT_ALIGN(FILE,LOG)  \
-  if (LOG==1) fprintf(FILE,"\teven\n"); \
-    else fprintf (FILE, "\t.align %d\n", (LOG))
-
-/* This is how to advance the location counter by SIZE bytes.  */
-#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
-  fprintf (FILE, "\tblock %u\n", (SIZE))
-
-/* This says how to output an assembler line
-   to define a global common symbol.  */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)	\
-   asm_output_common (FILE, NAME, SIZE, ROUNDED)
-
-/* This says how to output an assembler line
-   to define a local common symbol.  */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)	\
-   asm_output_local (FILE, NAME, SIZE, ROUNDED)
-
-/* This says how to output an assembler line to start an
-   object definition.  */
-
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)	\
-   asm_output_name (FILE, NAME)
-
-/* This says how to output an assembler line to start a
-   function definition.  */
-
-#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)	\
-   z8k_declare_function_name (FILE, NAME, DECL);
-
-/* Store in OUTPUT a string (made with alloca) containing
-   an assembler-name for a local static variable named NAME.
-   LABELNO is an integer which is different for each call.  */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
-  sprintf ((OUTPUT), "%s__%d", (NAME), (LABELNO)))
-
-/* Define the parentheses used to group arithmetic operations
-   in assembler code.  */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences.  */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
-   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
-   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
-
-#define PRINT_OPERAND(FILE, X, CODE)  print_operand (FILE, X, CODE)
-
-/* Determine which codes are valid without a following integer.  These must
-   not be alphabetic.  */
-
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '^')
-
-/* Print a memory address as an operand to reference that memory location.  */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE,	ADDR)
-
-#define NOTICE_UPDATE_CC(exp, insn)				\
-{								\
-  enum attr_cond type = get_attr_cond (insn);			\
-  switch (type)							\
-    {								\
-    case COND_NOTRASHCC:					\
-      if (GET_CODE (exp) == SET)				\
-	{							\
-	  if (cc_status.value1					\
-	      && reg_overlap_mentioned_p (SET_DEST (exp),	\
-					  cc_status.value1))	\
-	    cc_status.value1 = 0;				\
-	  if (cc_status.value2					\
-	      && reg_overlap_mentioned_p (SET_DEST (exp),	\
-					  cc_status.value2))	\
-	    cc_status.value2 = 0;				\
-	}							\
-      break;							\
-    case COND_TRASHCC:						\
-      CC_STATUS_INIT;						\
-      break;							\
-    case COND_SETCC:						\
-      if (GET_CODE (exp) == SET)				\
-	{							\
-	  cc_status.flags = 0;					\
-	  cc_status.value1 = XEXP (exp, 0);			\
-	  cc_status.value2 = XEXP (exp, 1);			\
-	}							\
-      else							\
-	CC_STATUS_INIT;						\
-      break;							\
-    case COND_LOGCC:						\
-      if (GET_CODE (exp) == SET)				\
-	{							\
-	  cc_status.flags = CC_NO_OVERFLOW;			\
-	  cc_status.value1 = XEXP (exp, 0);			\
-	  cc_status.value2 = XEXP (exp, 1);			\
-	}							\
-      else							\
-	CC_STATUS_INIT;						\
-      break;							\
-    case COND_SETREVCC:						\
-      cc_status.flags = CC_REVERSED;				\
-      cc_status.value1 = XEXP (exp, 0);				\
-      cc_status.value2 = XEXP (exp, 1);				\
-      break;							\
-    }								\
-}
-
-
-/* A C statement to output DBX or SDB debugging information before code for line
-   number LINE of the current source file to the stdio stream STREAM. */
-
-/* ??? stabs-in-coff will not work until this conflict is resolved.  */
-#undef DBX_DEBUGGING_INFO
-#undef ASM_OUTPUT_SOURCE_LINE
-
-#define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE)  				\
-  (TARGET_YASM ? print_source_line(STREAM,LINE) : 			\
-   fprintf (file, "\t.ln\t%d\n", ((sdb_begin_function_line > -1) 	\
-				  ? (LINE) - sdb_begin_function_line : 1)));
- 
-  
-/* A C statement to output DBX or SDB debugging information which indicates
-   that filename NAME is the current source file to the stdio stream STREAM. */
-
-#define ASM_OUTPUT_SOURCE_FILENAME(STREAM,NAME)			\
-  { char *quote = TARGET_YASM ? "" : "\"";			\
-    fprintf (STREAM, "	name	%s%s%s\n", quote, NAME, quote);	\
-  }
-
-
-
-/* STUFF NEEDED TO DISABLE DEBUG OUTPUT */
-
-#define DP if (!TARGET_YASM || TARGET_DEFS) 
-
-#define PUT_SDB_SCL(a)     DP fprintf(asm_out_file, "\t.scl\t%d%s", (a), SDB_DELIM)
-#define PUT_SDB_INT_VAL(a) DP fprintf (asm_out_file, "\t.val\t%d%s", (a), SDB_DELIM)
-
-#define PUT_SDB_VAL(a)	DP			\
-( fputs ("\t.val\t", asm_out_file),		\
-  output_addr_const (asm_out_file, (a)),	\
-  fprintf (asm_out_file, SDB_DELIM))
-
-#define PUT_SDB_DEF(a)	\
-do { DP	 { fprintf (asm_out_file, "\t.def\t");	\
-     ASM_OUTPUT_LABELREF (asm_out_file, a); 	\
-     fprintf (asm_out_file, SDB_DELIM); } } while (0)
-
-#define PUT_SDB_PLAIN_DEF(a) DP fprintf(asm_out_file,"\t.def\t.%s%s",a, SDB_DELIM)
-#define PUT_SDB_ENDEF        DP fputs("\t.endef\n", asm_out_file)
-#define PUT_SDB_TYPE(a)      DP fprintf(asm_out_file, "\t.type\t0%o%s", a, SDB_DELIM)
-#define PUT_SDB_SIZE(a)      DP fprintf(asm_out_file, "\t.size\t%d%s", a, SDB_DELIM)
-#define PUT_SDB_START_DIM    DP fprintf(asm_out_file, "\t.dim\t")
-#define PUT_SDB_NEXT_DIM(a)  DP fprintf(asm_out_file, "%d,", a)
-#define PUT_SDB_LAST_DIM(a)  DP fprintf(asm_out_file, "%d%s", a, SDB_DELIM)
-#define PUT_SDB_TAG(a)	     DP			\
-  do { fprintf (asm_out_file, "\t.tag\t");	\
-     ASM_OUTPUT_LABELREF (asm_out_file, a);	\
-     fprintf (asm_out_file, SDB_DELIM); } while (0)
-
-#define PUT_SDB_BLOCK_START(LINE) DP		\
-  fprintf (asm_out_file,			\
-	   "\t.def\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_BLOCK_END(LINE)	 DP		\
-  fprintf (asm_out_file,			\
-	   "\t.def\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n",  \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_FUNCTION_START(LINE) DP		\
-  fprintf (asm_out_file,			\
-	   "\t.def\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_FUNCTION_END(LINE)	DP	\
-  fprintf (asm_out_file,			\
-	   "\t.def\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
-	   SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
-
-#define PUT_SDB_EPILOGUE_END(NAME) 			\
-do { DP { fprintf (asm_out_file, "\t.def\t");		\
-     ASM_OUTPUT_LABELREF (asm_out_file, NAME);		\
-     fprintf (asm_out_file,				\
-	      "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n",	\
-	      SDB_DELIM, SDB_DELIM, SDB_DELIM); } } while (0)
-
-int saved_reg_on_stack_hack;
-
-#define TARGET_MEM_FUNCTIONS
-
-char *output_move64();
-extern void z8k_declare_function_name ();
diff --git a/gcc/config/z8k/z8k.md b/gcc/config/z8k/z8k.md
deleted file mode 100755
index c339789..0000000
--- a/gcc/config/z8k/z8k.md
+++ /dev/null
@@ -1,2350 +0,0 @@
-;;-  Machine description for GNU compiler, Z8000 Version
-;;   Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc.
-
-;; This file is part of GNU CC.
-
-;; GNU CC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
-;; any later version.
-
-;; GNU CC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
-
-
-;; First incarnation by Steve Chamberlain, sac@cygnus.com
-
-;;- Instruction patterns.  When multiple patterns apply,
-;;- the first one in the file is chosen.
-;;-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-;;-
-;; We don't want to allow a constant operand for test insns because
-;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
-;; be folded while optimizing anyway.
-
-;; Q = ir da
-;; R = x
-;; S = ba bx
-
-(define_attr "type" "branch,foo,def,djnz,invisible,return" 
-  (const_string "def"))
-
-(define_attr "cond" 
-  "notrashcc,trashcc,setcc,setrevcc,logcc"
-  (const_string "trashcc"))
-
-; the longest possible instruction is the default when we are not
-; sure
-
-(define_attr "length" ""
-  (cond [(eq_attr "type" "branch")
-	 (if_then_else (and (ge (minus (pc) (match_dup 0))
-				(const_int -256))
-			    (le (minus (pc) (match_dup 0))
-				(const_int 254)))
-		       (const_int 2)
-		       (const_int 4))
-
-	 (eq_attr "type" "djnz")
-	 (if_then_else (and (ge (minus (pc) (match_dup 1))
-				(const_int -2))
-			    (le (minus (pc) (match_dup 1))
-				(const_int 252)))
-		       (const_int 2)
-		       (const_int 4))
-
-	 (eq_attr "type" "foo") (const_int 10)]
-	(const_int 6)))
-
-
-;; ----------------------------------------------------------------------
-;; Tests
-;; ----------------------------------------------------------------------
-
-(define_insn "testhi_"
-  [(set (cc0)
-	(match_operand:HI 0 "r_ir_da_x_operand" "r,QR"))]
-  ""
-  "@
-	and	%H0,%H0	
-	test	%H0"
-  [(set_attr "cond" "logcc,logcc")])
-
-(define_expand "tsthi"
-  [(set (cc0)  (match_operand:HI 0 "r_ir_da_operand" ""))]
-  ""
-  "operands[0] = force_reg (HImode, operands[0]);")
-	
-(define_insn "tstqi_"
-  [(set (cc0)
-	(match_operand:QI 0 "r_ir_da_x_operand" "u,QR"))]
-  ""
-  "@
-	andb	%Q0,%Q0	
-	testb 	%Q0"
-  [(set_attr "cond" "logcc,logcc")])
-
-;(define_expand "tstqi"
-;  [(set (cc0) (match_operand:QI 0 "r_ir_da_operand" "rQ"))]
-;  ""
-; "operands[0] = force_reg (QImode, operands[0]);")
-
-(define_insn "tstsi_"
-  [(set (cc0)
-	(match_operand:SI 0 "r_ir_da_x_operand" "rQR"))]
-  ""
-  "testl 	%S0"
-  [(set_attr "cond" "logcc")])
-
-(define_expand "tstsi"
-  [(set (cc0) (match_operand:SI 0 "r_ir_da_operand" "rQR"))]
-  ""
-  "operands[0] = force_reg (SImode, operands[0]);")
-
-
-(define_insn "tstpsi_"
-  [(set (cc0)
-	(match_operand:PSI 0 "r_ir_da_x_operand" "rQR"))]
-  ""
-  "testl 	%S0"
-  [(set_attr "cond" "logcc")])
-
-(define_expand "tstpsi"
-  [(set (cc0) (match_operand:PSI 0 "r_ir_da_operand" "rQR"))]
-  ""
-  "operands[0] = force_reg (PSImode, operands[0]);")
-
-
-;; ----------------------------------------------------------------------
-;; Compares
-;; ----------------------------------------------------------------------
-
-(define_insn "cmphi_imm"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "r_ir_da_x_operand" "rQR")
-		 (match_operand:HI 1 "immediate_operand" "i")))]
-  ""
-  "cp	%H0,%H1"
-  [(set_attr "cond" "setcc")])
-
-
-(define_insn "cmphi_other"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "r_ir_da_x_operand" "r,rQR,QR")
-		 (match_operand:HI 1 "r_im_ir_da_x_operand" "riQR,i,r")))]
-  "r_operand(operands[0], HImode)
-  || (r_im_operand(operands[1], HImode))"
-  "@
-	cp	%H0,%H1
-	cp	%H0,%H1
-	cp	%H1,%H0"
-  [(set_attr "cond" "setcc,setcc,setrevcc")])
-
-(define_expand "cmphi"
-  [
-   (set (cc0)
-	(compare (match_operand:HI 0 "r_ir_da_x_operand" "")
-		 (match_operand:HI 1 "r_im_ir_da_x_operand" "")))]
-  ""
-  "{
-    /* Can only cope with r,[r|im|ir|da|x] or [ir|da|x],im */
-	
-    if (immediate_operand (operands[1], HImode))
-      {
-	if (!r_ir_da_x_operand (operands[0], HImode))
-	  {
-	    operands[0] = force_reg (HImode, operands[0]);
-	  }
-      }
-    else if (!r_operand (operands[0]))
-      {
-	operands[0] = force_reg (HImode, operands[0]);
-      }
-  }")
-
-
-(define_insn "_cmpqi"
-  [(set (cc0)
-	(compare (match_operand:QI 0 "r_ir_da_x_operand" "u,QR")
-		 (match_operand:QI 1 "r_im_ir_da_x_operand" "uiQR,i")))]
-  "r_operand (operands[0], QImode)
-   || im_operand(operands[1], QImode)"
-  "cpb	%Q0,%Q1"
-  [(set_attr "cond" "setcc")])
-
-(define_expand "cmpqi"
-  [(set (cc0)
-	(compare (match_operand:QI 0 "r_ir_da_x_operand" "u,QR")
-		 (match_operand:QI 1 "r_im_ir_da_x_operand" "uiQR,i")))]
-  ""
-  "
-    /* Can only cope with r,[r|im|ir|da|x] or [ir|da|x],im */
-	
-    if (immediate_operand (operands[1], QImode))
-      {
-	if (!r_ir_da_x_operand (operands[0], QImode))
-	  {
-	    operands[0] = force_reg (QImode, operands[0]);
-	  }
-      }
-    else if (!r_operand (operands[0]))
-      {
-	operands[0] = force_reg (QImode, operands[0]);
-   }")
-
-
-
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:SI 0 "r_im_ir_da_x_operand" "r,iQR")
-		 (match_operand:SI 1 "r_im_ir_da_x_operand" "rQRi,r")))]
-  "r_operand(operands[0], SImode) || r_operand(operands[1], SImode)"
-  "@
-	cpl	%S0,%S1
-	cpl	%S1,%S0"
-  [(set_attr "cond" "setcc,setrevcc")])
-
-; this instruction doesnt exist for SImode
-;(define_insn ""
-;  [(set (cc0)
-;	(compare (match_operand:SI 0 "r_da_x_operand" "rQR")
-;		 (match_operand:SI 1 "immediate_operand" "i")))]
-;  ""
-;  "cpl	%S0,%S1"
-;  [(set_attr "cond" "setcc")])
-
-(define_expand "cmpsi"
-  [ (set (cc0)
-	(compare (match_operand:SI 0 "r_im_ir_da_x_operand" "")
-		 (match_operand:SI 1 "r_im_ir_da_x_operand" "")))]
-  ""
- "{
-   if (!r_operand(operands[0], SImode) 
-       && !r_operand(operands[1], SImode))
-     {
-       operands[0]  = force_reg (SImode, operands[0]);
-     }
- }")
-
-
-(define_insn ""
-  [(set (cc0)
-	(compare (match_operand:PSI 0 "r_im_ir_da_x_operand" "r,iQR")
-		 (match_operand:PSI 1 "r_im_ir_da_x_operand" "rQRi,r")))]
-  "r_operand(operands[0], PSImode) || r_operand(operands[1], PSImode)"
-  "@
-	cpl	%S0,%S1
-	cpl	%S1,%S0"
-  [(set_attr "cond" "setcc,setrevcc")])
-
-
-(define_expand "cmppsi"
-  [ (set (cc0)
-	(compare (match_operand:PSI 0 "r_im_ir_da_x_operand" "")
-		 (match_operand:PSI 1 "r_im_ir_da_x_operand" "")))]
-  ""
- "{
-   if (!r_operand(operands[0], PSImode) || r_operand(operands[1], PSImode)) 
-     {
-       operands[0] = force_reg (PSImode, operands[0]);
-     }
- }")
-
-(define_insn ""
-  [(set (cc0)
-	(zero_extract:HI (match_operand:HI 0 "r_ir_da_x_operand" "r,rQR")
-		         (const_int 1)
-			 ;; ??? insert right pred later
-			 (match_operand:HI 1 "nonmemory_operand" "r,L")))]
-  "GET_CODE (operands[1]) == CONST_INT || r_operand (operands[0], HImode)"
-  "bit	%H0,%H1"
-  [(set_attr "cond" "logcc")])
-
-
-
-;; ----------------------------------------------------------------------
-;; MOVE INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-
-;; HI MODE
-
-
-(define_insn "movhi_matcher"
-  [(set (match_operand:HI 0 "r_ir_da_x_ba_bx_prd_operand" "=r,r,r,r,rQR,QR,QR,QRS,<")
-	(match_operand:HI 1 "r_im_ir_da_x_ba_bx_poi_operand" "I,L,ri,QRS,>,I,i,r,riQR"))]
-  "moveok(operands, HImode)"
-  "@
-	xor	%H0,%H0
-	ldk	%H0,%H1
-	ld	%H0,%H1
-	$ld	%H0,%H1
-	pop	%H0,@%1
-	clr	%H0
-	ld	%H0,%H1
-	$ld	%H0,%H1
-	push	@%0,%H1"
-  [(set_attr "cond" "trashcc,notrashcc,notrashcc,notrashcc,notrashcc,notrashcc,notrashcc,notrashcc,notrashcc")])
-
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "r_ir_da_x_ba_bx_prd_operand" "")
-	(match_operand:HI 1 "r_im_ir_da_x_ba_bx_poi_operand" ""))]
-  ""
-  "
-  if (!reload_in_progress && !reload_completed
-	 && !moveok(operands, HImode))
-    operands[1] = copy_to_mode_reg (HImode, operands[1]);
-")
-
-
-;; SI mode
-
-
-(define_insn "movsi_matcher"
-  [(set (match_operand:SI 0 "r_ir_da_x_ba_bx_prd_operand" "=r,r,r,r,rQR,QRS,<")
-	(match_operand:SI 1 "r_im_ir_da_x_ba_bx_poi_operand" "I,L,ri,QRS,>,r,rQR"))]
-  "moveok(operands, SImode)"
-  "@
-	xor	%I0,%I0\;ld	%H0,%I0
-	xor	%H0,%H0\;ldk	%I0,%H1
-	ldl	%S0,%S1
-	$ldl	%S0,%S1
-	popl	%S0,@%1
-	$ldl	%S0,%S1
-	pushl	@%0,%S1"
-  [(set_attr "cond" "trashcc,trashcc,notrashcc,notrashcc,notrashcc,notrashcc,notrashcc")])
-
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "r_ir_da_x_ba_bx_operand" "")
-	(match_operand:SI 1 "r_im_ir_da_x_ba_bx_operand" ""))]
-  ""
-  "
-  if (!reload_in_progress && !reload_completed && !moveok(operands, SImode))
-    operands[1] = copy_to_mode_reg (SImode, operands[1]);
-")
-
-
-;; PSI mode
-
-(define_insn "movpsi_matcher"
-  [(set (match_operand:PSI 0 "r_ir_da_x_ba_bx_prd_operand" "=r,r,r,r,rQR,QRS,<")
-	(match_operand:PSI 1 "r_im_ir_da_x_ba_bx_poi_operand" "I,L,ri,QRS,>,r,rQR"))]
-  "moveok(operands, PSImode)"
-  "@
-	xor	%I0,%I0\;ld	%H0,%I0
-	xor	%H0,%H0\;ldk	%I0,%H1
-	ldl	%S0,%S1
-	$ldl	%S0,%S1
-	popl	%S0,@%1
-	$ldl	%S0,%S1
-	pushl	@%0,%S1"
-  [(set_attr "cond" "trashcc,trashcc,notrashcc,notrashcc,notrashcc,notrashcc,notrashcc")])
-
-(define_expand "movpsi"
-  [(set (match_operand:PSI 0 "r_ir_da_x_ba_bx_operand" "")
-	(match_operand:PSI 1 "r_im_ir_da_x_ba_bx_operand" ""))]
-  ""
-  "
-  if (!reload_in_progress && !reload_completed && !moveok(operands, PSImode))
-    operands[1] = copy_to_mode_reg (PSImode, operands[1]);
-")
- 
-(define_insn ""
-  [(set (match_operand:PSI 0 "r_operand" "=r")
-	(plus:PSI (match_operand:PSI 1 "r_operand" "0")
-		  (truncate:PSI (match_operand:SI 2 "r_im_operand" "r"))))]
-  ""
-  "add	%I0,%I2"
-  [(set_attr "cond" "logcc")])
-			   
-(define_insn "addpsi3_"
-  [(set (match_operand:PSI 0 "r_operand"           "=r,r,r,r,r,r,r,r")
-	(plus:PSI (match_operand:PSI 1 "r_ir_da_x_operand" "%0,0,0,0,0,0,0,0")
-		  (match_operand:PSI 2 "r_im_ir_da_x_operand" "J,K,n,rQRi,r,r,r,r")))]
-  "r_operand (operands[0], PSImode)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0: return \"inc	%I0,%H2 ! psi2\";
-    case 1: return \"dec	%I0,%N2 ! psi2\";
-    case 2: 
-      /* This can happen when the fp has been eliminated */
-      if (INTVAL(operands[2]) == 0) return \"\";
-      return \"add	%I0,%H2 !psi2\";
-    case 3: return \"addl	%S0,%S2 !psi2\";
-    case 4: return \"ldl	%S0,%S1\;inc	%I0,%H2 !psi2\";
-    case 5: return \"ldl	%S0,%S1\;dec	%I0,%N2 !psi2\";
-    case 6:
-      if (REGNO(operands[0]) == REGNO(operands[1]))
-	{
-	  return \"addl	%S0,%S2 ! psi2 - a\";
-	}
-      if (REGNO(operands[0]) == REGNO(operands[2]))
-	{
-	  return \"addl	%S0,%S1 ! psi2 - b\";
-	}
-      return \"ldl	%S0,%S2\;addl	%S0,%S1 ! psi2 - c\";
-    case 7:
-      /* r = r + thing */
-      if (REGNO(operands[1]) == REGNO(operands[0])) 
-	{
-	  /* Rn += thing */
-	  saved_reg_on_stack_hack =1;
-	  return \"pushl @%X0,rr0\;ldl	rr0,%S2\;addl	%S0,rr0\;popl	rr0,@%X0 ! reg alert %S0=%S1+%S2\";
-	}
-      return \"ldl	%S0,%S2\;addl	%S0,%S1\";
-    }
-}"
-  [(set_attr "cond" "trashcc")])
-
-(define_expand "addpsi3"
-  [(set (match_operand:PSI 0 "r_operand" "")
-	(plus:PSI (match_operand:PSI 1 "r_im_ir_da_x_operand" "")	
-		  (match_operand:PSI 2 "r_im_ir_da_x_operand" "")))]
-  ""
-  "")
-
-
-(define_insn "subpsi3_"
-  [(set (match_operand:PSI 0 "r_operand" "=r,r,r,r,r,r,r,r")
-	(minus:PSI (match_operand:PSI 1 "r_im_ir_da_x_operand" "0,0,0,0,0,0,0,0")
-		   (match_operand:PSI 2 "r_im_ir_da_x_operand" "J,K,n,rQRi,r,r,r,r")))]
-  ""
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0: return \"dec	%I0,%H2 ! psi2\";
-    case 1: return \"inc	%I0,%N2 ! psi2\";
-    case 2: 
-      /* This can happen when the fp has been eliminated */
-      if (INTVAL(operands[2]) == 0) return \"\";
-      return \"sub	%I0,%H2 !psi2\";
-    case 3: return \"subl	%S0,%S2 !psi2\";
-    case 4: return \"ldl	%S0,%S1\;dec	%I0,%H2 !psi2\";
-    case 5: return \"ldl	%S0,%S1\;inc	%I0,%N2 !psi2\";
-    case 6:
-      if (REGNO(operands[0]) == REGNO(operands[1]))
-	{
-	  return \"subl	%S0,%S2 ! psi2 - a\";
-	}
-      if (REGNO(operands[0]) == REGNO(operands[2]))
-	{
-	  return \"subl	%S0,%S1 ! psi2 - b\";
-	}
-      return \"ldl	%S0,%S2\;subl	%S0,%S1 ! psi2 - c\";
-    case 7:
-      /* r = r - thing */
-      if (REGNO(operands[1]) == REGNO(operands[0])) 
-	{
-	  /* Rn -= thing */
-	  saved_reg_on_stack_hack =1;
-	  return \"pushl @%X0,rr0\;ldl	rr0,%S2\;subl	%S0,rr0\;popl	rr0,@%X0 ! reg alert %S0=%S1+%S2\";
-	}
-      return \"ldl	%S0,%S2\;subl	%S0,%S1\";
-    }
-}"
-  [(set_attr "cond" "trashcc")])
-
-
-(define_expand "subpsi3"
-  [(set (match_operand:PSI 0 "register_operand" "")
-	(minus:PSI (match_operand:PSI 1 "r_im_ir_da_x_operand" "")	
-  		   (match_operand:PSI 2 "r_im_ir_da_x_operand" "")))]
-  ""
-  "")
-
-;; SF  mode
-
-(define_insn "movsf_matcher"
-  [(set (match_operand:SF 0 "r_ir_da_x_ba_bx_prd_operand" "=r,r,r,r,rQR,QRS,<")
-	(match_operand:SF 1 "r_im_ir_da_x_ba_bx_poi_operand" "I,L,ri,QRS,>,r,rQR"))]
-  "moveok(operands, SFmode)"
-  "@
-	xor	%I0,%I0\;ld	%H0,%I0
-	xor	%H0,%H0\;ldk	%I0,%H1
-	ldl	%S0,%S1
-	$ldl	%S0,%S1
-	popl	%S0,@%1
-	$ldl	%S0,%S1
-	pushl	@%0,%S1"
-  [(set_attr "cond" "trashcc,trashcc,notrashcc,notrashcc,notrashcc,notrashcc,notrashcc")])
-
-(define_expand "movsf"
-  [(set (match_operand:SF 0 "r_ir_da_x_ba_bx_operand" "")
-	(match_operand:SF 1 "r_ir_da_x_ba_bx_operand" ""))]
-  ""
-  "{
-  if (!reload_in_progress && !reload_completed && !moveok(operands, SFmode))
-    operands[1] = copy_to_mode_reg (SFmode, operands[1]);
-if (!reload_in_progress && !reload_completed && GET_CODE(operands[0]) != REG 
-)
-    operands[1] = copy_to_mode_reg (SFmode, operands[1]);
-
-  }")
-
-
-
-;; QI mode
-
-; special care has to be taken with the movqi since reload
-; likes to put bytes into regs which can't be read byte by byte
-
-(define_expand "reload_inqi"
-  [(parallel [(match_operand:QI 0 "register_operand" "=r")
-	      (match_operand:QI 1 "memory_operand" "m")
-	      (match_operand:QI 2 "register_operand" "=&u")])]
-  ""
-  "
-{ 
- operands[2] = gen_rtx (REG, QImode, REGNO(operands[2]));
-  emit_insn (gen_movqiin_using_tmp(operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_expand "reload_outqi"
-  [(parallel [(match_operand:QI 0 "memory_operand" "=m")
-	      (match_operand:QI 1 "register_operand" "r")
-	      (match_operand:QI 2 "register_operand" "=&u")])]
-  ""
-  "
-{ 
-/* Want to treat temp as a qi */
- operands[2] = gen_rtx(REG, QImode, REGNO(operands[2]));
-  emit_insn (gen_movqiout_using_tmp(operands[0], operands[1], operands[2]));
-  DONE;
-}")
-  
-
-(define_expand "movqiin_using_tmp"
-  [(set (match_operand:QI 2 "register_operand" "=u")
-	(match_operand:QI 1 "memory_operand" "m"))
-   (set (match_operand:QI 0 "register_operand" "=r")
-	(match_dup 2 ))]
-  ""
-  "")
-
-(define_expand "movqiout_using_tmp"
-  [(set (match_operand:QI 2 "register_operand" "=u")
-	(match_operand:QI 1 "register_operand" "r"))
-   (set (match_operand:QI 0 "memory_operand" "=m")
-	(match_dup 2 ))]
-  ""
-  "")
-
-; QRS/u must be before ur/rn so that MEM/PSEUDO will match it.  If it matches
-; the other way, then we need secondary reloads.
-(define_insn "movqi_matcher"
-;;  [(set (match_operand:QI 0 "r_ir_da_x_ba_bx_operand" "=r,u,r,r,u,QR,QR,QRS,!*QRS")
-;;	(match_operand:QI 1 "r_im_ir_da_x_ba_bx_operand" "I,un,L,rn,QRS,I,n,u,r"))]
-  [(set (match_operand:QI 0 "r_ir_da_x_ba_bx_operand" "=ur,u,ur,u,QR,QR,QRS,ur")
-	(match_operand:QI 1 "r_im_ir_da_x_ba_bx_operand" "I,un,L,QRS,I,n,u,rn"))]
-  "moveok(operands, QImode)"
-  "@
-	xor	%H0,%H0
-	ldb	%Q0,%Q1
-	ldk	%H0,%H1
-	$ldb	%Q0,%Q1
-	clrb	%Q0
-	$ldb	%Q0,%Q1
-	$ldb	%Q0,%Q1
-	ld	%H0,%H1"
-  [(set_attr "cond" "trashcc,notrashcc,notrashcc,notrashcc,notrashcc,notrashcc,notrashcc,notrashcc")])
- 
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "r_ir_da_x_ba_bx_operand" "")
-	(match_operand:QI 1 "r_im_ir_da_x_ba_bx_operand" ""))]
-  ""
-  "
-  if (!reload_in_progress && !moveok(operands, QImode))
-    operands[1] = copy_to_mode_reg (QImode, operands[1]);
-    emit_insn (gen_movqi_matcher(operands[0], operands[1]));
-   DONE;
-")
-
-(define_insn ""
-  [(set (match_operand:QI 0 "push_operand" "=<")
-	(match_operand:QI 1 "general_operand" "ui"))]
-  ""
-  "push	@%0,%H1")
-
-
-;; DI mode
-
-(define_insn "_pushdi"
-  [(set (match_operand:DI 0 "push_operand" "=<")
-	(match_operand:DI 1 "r_ir_da_x_operand_for_di" "rQR"))]
-  ""
-  "* return output_move64(operands[0], operands[1]);"
-  [(set_attr "cond" "notrashcc")])
-
-(define_insn "_movdi1"
-  [(set (match_operand:DI 0 "r_operand" "=r")
-	(match_operand:DI 1 "im_operand" "i"))]
-  ""
-  "*
-{
-    if ((REGNO (operands[0]) & 3) == 0)
-      return \"ldl	%T0,%T1\;extsl	%D0\";
-
-    if (INTVAL (operands[1]) < 0)
-      return \"ldl	%T0,%T1\;ldl	%S0,#-1\";
-    return \"ldl	%T0,%T1\;subl	%S0,%S0\";
-}")
-   
-(define_insn "_movdi2"
-  [(set (match_operand:DI 0 "r_ir_da_x_ba_operand_for_di" "=rQRT,r")
-	(match_operand:DI 1 "r_ir_da_x_ba_operand_for_di" "r,rQRT"))]
-  ""
-  "* return output_move64(operands[0], operands[1]);"
-  [(set_attr "cond" "notrashcc")])
-
-
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "r_ir_da_x_ba_operand_for_di" "")
-	(match_operand:DI 1 "r_ir_da_x_ba_operand_for_di" ""))]
-  ""
-  "{
-	if (emit_move(operands, DImode, 0)) 
-		DONE;
-  }")
-
-(define_insn ""
-  [(set (match_operand:DF 0 "push_operand" "=<")
-	(match_operand:DF 1 "r_ir_da_x_operand_for_di" "rQR"))]
-  ""
-  "* return output_move64(operands[0], operands[1]);"
-  [(set_attr "cond" "notrashcc")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "r_ir_da_x_ba_operand_for_di" "=rQRT,r")
-	(match_operand:DF 1 "r_ir_da_x_ba_operand_for_di" "r,rQRT"))]
-  ""
-  "* return output_move64 (operands[0], operands[1]);"
-  [(set_attr "cond" "notrashcc")])
-
-
-(define_expand "movdf"
-  [(set (match_operand:DF 0 "r_ir_da_x_ba_operand_for_di" "")
-	(match_operand:DF 1 "r_ir_da_x_ba_operand_for_di" ""))]
-  ""
-  "{
-	if (emit_move(operands, DFmode, 0)) 
-		DONE;
-}")
-
-
-
-;; BLK moves
-
-(define_insn "ldirb_z8001"
-  [(parallel [(set (mem:BLK (match_operand 0 "r_operand" "+v"))
-		   (mem:BLK (match_operand 1 "r_operand" "+v")))
-	      (set (match_dup 0) (plus:PSI (match_dup 0) 
-					   (zero_extend:PSI (match_operand 2 "r_operand" "+r"))))
-	      (set (match_dup 1) (plus:PSI (match_dup 1) 
-					   (zero_extend:PSI (match_dup 2))))
-	      (set (match_dup 2) (const_int 0))])]
-  "TARGET_LDIR"
-  "ldirb	@%P0,@%P1,%H2"
-  [(set_attr "cond" "trashcc")])
-
-(define_insn "ldirb_z8002"
-  [(parallel [(set (mem:BLK (match_operand 0 "r_operand" "+v"))
-		   (mem:BLK (match_operand 1 "r_operand" "+v")))
-	      (set (match_dup 0) (plus:HI (match_dup 0) 
-					   (match_operand 2 "r_operand" "+r")))
-	      (set (match_dup 1) (plus:HI (match_dup 1)  (match_dup 2)))
-	      (set (match_dup 2) (const_int 0))])]
-  "TARGET_LDIR"
-  "ldirb	@%P0,@%P1,%H2"
-  [(set_attr "cond" "trashcc")])
-
-
-(define_insn "ldir_z8001"
-  [(parallel [(set (mem:BLK (match_operand 0 "r_operand" "+v"))
-		   (mem:BLK (match_operand 1 "r_operand" "+v")))
-	      (set (match_dup 0) 
-		   (plus:PSI (match_dup 0) 
-			     (zero_extend:PSI (mult:HI (match_operand 2 "r_operand" "+r")
-						       (const_int 2)))))
-	      (set (match_dup 1) (plus:PSI (match_dup 1) 
-					   (mult:HI   (zero_extend:PSI (match_dup 2))
-						      (const_int 2))))
-	      (set (match_dup 2) (const_int 0))])]
-  "TARGET_LDIR"
-  "ldir	@%P0,@%P1,%H2"
-  [(set_attr "cond" "trashcc")])
-
-(define_insn "ldir_z8002"
-  [(parallel [(set (mem:BLK (match_operand 0 "r_operand" "+v"))
-		   (mem:BLK (match_operand 1 "r_operand" "+v")))
-	      (set (match_dup 0) (plus:HI (match_dup 0) 
-					  (mult:HI   (match_operand 2 "r_operand" "+r")
-						     (const_int 2))))
-	      (set (match_dup 1) (plus:HI (match_dup 1) 
-					  (mult:HI (match_dup 2)
-						   (const_int 2))))
-	      (set (match_dup 2) (const_int 0))])]
-  "TARGET_LDIR"
-  "ldir	@%P0,@%P1,%H2"
-  [(set_attr "cond" "trashcc")])
-
-  
-(define_expand "movstrhi"
-  [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
-		   (mem:BLK (match_operand:BLK 1 "general_operand" "")))
-	      (use (match_operand:HI 2 "general_operand" ""))
-	      (use (match_operand:HI 3 "immediate_operand" ""))])]
-  "TARGET_LDIR"
-  "
-{
-  rtx dst = copy_to_mode_reg (Pmode, convert_to_mode (Pmode, XEXP (operands[0], 0), 0));
-  rtx src = copy_to_mode_reg (Pmode, convert_to_mode (Pmode, XEXP (operands[1], 0), 0));
-
-  /* if the alignment is two or more, and we're moving an even sized
-     lump of data, then we can use the ldir instruction, if not
-     then we have to use the ldrib. */
-
-  if (GET_CODE (operands[2]) == CONST_INT 
-      && (INTVAL (operands[2]) %2 == 0)
-      && (INTVAL (operands[2]) > 0)
-      && (INTVAL (operands[3]) >= 2))
-    {
-      rtx count = copy_to_mode_reg (HImode,  GEN_INT (INTVAL (operands[2]) / 2));
-
-      if (TARGET_BIG)
-	emit_insn (gen_ldir_z8001 (dst, src, count));
-      else
-	emit_insn (gen_ldir_z8002 (dst, src, count));
-    }
-  else 
-    {
-      rtx count = copy_to_mode_reg (HImode, operands[2]);
-      rtx zero_count = gen_label_rtx ();
-      emit_insn (gen_tsthi (operands[2]));
-      emit_jump_insn (gen_beq (zero_count));
-
-      if (TARGET_BIG)
-	emit_insn (gen_ldirb_z8001 (dst, src, count));
-      else
-	emit_insn (gen_ldirb_z8002 (dst, src, count));
-      emit_label (zero_count);
-    }
-  emit_move_insn (src, src);
-  DONE;
-}
-")
-
-
-;; ----------------------------------------------------------------------
-;; Extension and truncation insns.
-;; ----------------------------------------------------------------------
-
-
-(define_insn "truncsipsi2"
-  [(set (match_operand:PSI 0 "general_operand" "=g")
-	(truncate:PSI (match_operand:SI 1 "general_operand" "0")))]
-  ""
-  "!truncsipsi2 %0=%1")
-
-
-(define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "r_operand" "=r")
-	(zero_extend:SI (match_operand:HI 1 "r_im_ir_da_x_operand" "rQRSo")))]
-  ""
-  "$ld	%I0,%H1\;sub	%H0,%H0")
-
-(define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "r_operand" "=u,r")
-	(zero_extend:HI (match_operand:QI 1 "r_operand" "0,0")))]
-  ""
-  "@
-	subb	%U0,%U0
-	and	%H0,#255")
-
-(define_insn "zero_extendpsisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(zero_extend:SI (match_operand:PSI 1 "general_operand" "0")))]
-  ""
-  "! zero ext %S0"
-  [(set_attr "cond" "notrashcc")])
-
-
-(define_insn "extendpsisi2"
-  [(set (match_operand:SI 0 "general_operand" "=g")
-	(sign_extend:SI (match_operand:PSI 1 "general_operand" "0")))]
-  ""
-  "! extend psi %S0"       
-  [(set_attr "cond" "notrashcc")])
-
-(define_insn "extendsidi2"
-  [(set (match_operand:DI 0 "r_operand" "=r")
-	(sign_extend:DI (match_operand:SI 1 "r_operand" "r")))]
-  "0"
-  ""
-  [(set_attr "cond" "notrashcc")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "r_operand" "=r")
-	;; (tege) why subreg here?
-	(sign_extend:SI (subreg:HI (match_operand:QI 1 "r_operand" "0") 0)))]
-
-  ""
-  "extsb	%H0\;exts	%S0")
-
-;(define_insn ""
-;  [(set (match_operand:PSI 0 "r_operand" "=r")
-;	;; (tege) why subreg here?
-;;n	(sign_extend:PSI (subreg:HI (match_operand:QI 1 "r_operand" "0") 0)))]
-;
-;  ""
-;  "extsb	%H0\;exts	%S0")
-
-
-(define_insn "extendhisi2"
-  [(set (match_operand:SI 0 "r_operand" "=r,r")
-	(sign_extend:SI (match_operand:HI 1 "r_ir_da_x_ba_bx_operand" "0,rQRSo")))]
-  ""
-  "@
-	exts	%S0
-	$ld	%I0,%H1\;exts	%S0")
-
-
-(define_insn "extendhipsi2"
-  [(set (match_operand:PSI 0 "r_operand" "=r,r")
-	(sign_extend:PSI (match_operand:HI 1 "r_ir_da_x_ba_bx_operand" "0,rQRSo")))]
-  ""
-  "@
-	exts	%S0
-	$ld	%I0,%H1\;exts	%S0")
-
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(sign_extend:HI (match_operand:QI 1 "r_operand" "0")))]
-
-  ""
-  "extsb	%H0"
-  [(set_attr "cond" "notrashcc")])
-
-; adds to the sp are only done to the bottom 16bits, since the stack cannot 
-; go over a 64k boundary.
-
-
-
-; sadly this will not work since the bits 16..23 are undefined in a pointer.
-
-(define_insn "combine1"
-  [(set (match_operand:SI 0 "r_operand" "=r")
-	(plus:SI (match_operand:SI 1 "r_operand" "v")
-		 (match_operand:SI 2 "immediate_operand" "O")))]
-  "TARGET_BIG && 0"
-  "lda	%S0,%S1(%S2)")
-
-(define_insn "addsi3_"
-  [(set (match_operand:SI 0 "r_operand" "=r,r,r")
-	(plus:SI (match_operand:SI 1 "r_operand" "%0,0,0")
-		  (match_operand:SI 2 "r_im_ir_da_x_operand" "rQRi,r,r")))]
-  "r_operand (operands[0], SImode)
-  || smallint_operand (operands[2], SImode)"
-  "*
-{
-  switch (which_alternative)
-    {
-    case 0: return \"addl	%S0,%S2 !si2\";
-    case 1:
-      if (REGNO(operands[0]) == REGNO(operands[1]))
-	{
-	  return \"addl	%S0,%S2 ! si2 - a\";
-	}
-      if (REGNO(operands[0]) == REGNO(operands[2]))
-	{
-	  return \"addl	%S0,%S1 ! si2 - b\";
-	}
-      return \"ldl	%S0,%S2\;addl	%S0,%S1 ! si2-c\";
-    case 2:
-      /* r = r + thing */
-      if (REGNO(operands[1]) == REGNO(operands[0])) 
-	{
-	  /* Rn += thing */
-	  saved_reg_on_stack_hack =1;
-	  return \"pushl @%X0,rr0\;ldl	rr0,%S2\;addl	%S0,rr0\;popl	rr0,@%X0 ! reg alert SI %S0=%S1+%S2\";
-	}
-      return \"ldl	%S0,%S2\;addl	%S0,%S1 ! si2 - d\";
-    }
-}"
-  [(set_attr "cond" "trashcc")])
-
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "r_operand" "")
-	(plus:SI (match_operand:SI 1 "r_operand" "")
-		 (match_operand:SI 2 "r_im_ir_da_x_operand" "")))]
-  ""
-  "operands[2] = force_reg(SImode, operands[2]);")
-;; tege: I think this is a pessimation.  The insn is 2 words and
-;; takes from 12 cycles and up.  It *does not* decrease reg preasure.
-;; If this was here to actually make reload happy (the name "combine2"
-;; suggests that this is not the case) we can fix it with SECONDARY_RELOAD.
-
-(define_insn "combine2"
-  [(set (match_operand:HI 0 "r_operand" "=r,r")
-	(plus:HI (match_operand:HI 1 "r_operand" "v,v")
-		 (match_operand:HI 2 "nonmemory_operand" "i,r")))]
-  "!TARGET_BIG & 0"
-  "lda	%H0,%H1(%H2)")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_ir_da_x_operand" "=rQR,rQR,r")
-	(plus:HI (match_operand:HI 1 "r_ir_da_x_operand" "%0,0,0")
-		 (match_operand:HI 2 "r_im_operand" "J,K,ri")))]
-  "r_operand (operands[0], HImode) || r_operand (operands[1], HImode)
-   || (GET_CODE (operands[2]) == CONST_INT
-       && (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
-	   || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))"
-  "@
-	inc	%H0,%H2
-	dec	%H0,%N2
-	add	%H0,%H2"
-  [(set_attr "cond" "setcc")])
-
-; strange rules for adding to the sp 
-(define_insn ""
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	;; this is invalid use of subreg, but this should never happen.
-	;; use truncate in situations like this. (tege)
-	(subreg:HI (plus:SI (match_operand:SI 1 "r_operand" "r")
-			    (match_operand:SI 2 "immediate_operand" "i"))
-		  1))]
-  ""
-  "ld	%H0,%I1\;add	%H0,%H2	! i3")
-					     
-  
-; strange rules for adding to the sp 
-(define_insn ""
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	;; this is invalid use of subreg, but this should never happen.
-	;; use truncate in situations like this. (tege)
-	(subreg:HI (plus:PSI (match_operand:PSI 1 "r_operand" "r")
-			    (match_operand:PSI 2 "immediate_operand" "i"))
-		  1))]
-  ""
-  "ld	%H0,%I1\;add	%H0,%H2	! i3")
-					     
-
-
-(define_expand "addhi3"
-  [ (set (match_operand:HI 0 "r_operand" "") 
-	 (plus:HI (match_operand:HI 1 "r_operand" "")
-		  (match_operand:HI 2 "nonmemory_operand" "")))
-
-    ]
-  ""
-  "")
-
-
-; subsi from the stack pointer is done as a 16bit sub, since the stack can't go
-; over a 64k boundary.
-
-(define_insn "subsi3"
-  [(set (match_operand:SI 0 "r_operand" "=r,q")
-	(minus:SI (match_operand:SI 1 "general_operand" "0,0")
-		  (match_operand:SI 2 "r_im_ir_da_x_operand" "riQR,riQR")))]
-  ""
-  "@
-	subl	%S0,%S2
-	sub	r15,%H2"
-  [(set_attr "cond" "setcc")])
-
-(define_insn "_subhi3"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(minus:HI (match_operand:HI 1 "r_operand" "0")
-		  (match_operand:HI 2 "r_im_ir_da_x_operand" "riQR")))]
-  ""
-  "sub	%H0,%H2"
-  [(set_attr "cond" "setcc")])
-
-(define_expand "subhi3"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(minus:HI (match_operand:HI 1 "r_operand" "r")
-		  (match_operand:HI 2 "r_im_ir_da_x_operand" "riQR")))]
-  ""
-  "")
-
-;;----------------------------------------------------------------------
-;; Multiply instructions.
-;;----------------------------------------------------------------------
-
-(define_insn ""
-  [(clobber (reg:HI 4))
-   (clobber (reg:HI 5))
-   (set (reg:DI 4)
-	(mult:DI
-	 (sign_extend:DI (reg:SI 6))
-	 (sign_extend:DI (match_operand 0 "immediate_operand" "i"))))]
-  ""
-  "multl	rq4,%S0")
-
-(define_insn ""
-  [(clobber (reg:HI 4))
-   (clobber (reg:HI 5))
-   (set (reg:DI 4)
-	(mult:DI
-	 (sign_extend:DI (reg:SI 6))
-	 (sign_extend:DI (match_operand:SI 0 "r_im_ir_da_operand" "irQR"))))]
-  ""
-  "multl	rq4,%S0")
-
-(define_expand "mulsi3"
-  [(set (reg:SI 6) 
-	(match_operand:SI 1 "r_im_ir_da_operand" "irQR"))
-   (parallel[(clobber (reg:HI 4))
-	     (clobber (reg:HI 5))
-	     (set (reg:DI 4)
-		  (mult:DI
-		   (sign_extend:DI (reg:SI 6))
-		   (sign_extend:DI (match_operand:SI 2 "r_im_ir_da_operand" "irQR"))))])
-   (set (match_operand:SI 0 "general_operand" "") (reg:SI 6))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(mult:SI 
-	 (sign_extend:SI (match_operand:HI 1 "r_im_ir_da_operand" "irQR"))
-	 (sign_extend:SI (match_operand 2 "immediate_operand" "i"))))]
-  ""
-  "ld	%I0,%H1\;mult	%S0,%H2")
-
-(define_insn "mulhisi3"
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(mult:SI 
-	 (sign_extend:SI (match_operand:HI 1 "r_im_ir_da_operand" "irQR"))
-	 (sign_extend:SI (match_operand:HI 2 "r_im_ir_da_operand" "irQR"))))]
-  ""
-  "ld	%I0,%H1\;mult	%S0,%H2")
-
-	
-
-;; ----------------------------------------------------------------------
-;; Divide instructions.
-;; ----------------------------------------------------------------------
-
-
-(define_insn ""
-  [(set (reg:HI 5)
-	(div:HI (reg:HI 5)
-		(reg:HI 7)))
-   (set (reg:HI 4)
-	(mod:HI (reg:HI 5) (reg:HI 7)))]
-  ""
-  "exts	rr4\;div	rr4,r7")
-
-(define_expand "divmodhi4"
-  [(set (reg:HI 5) (match_operand:HI 1 "r_im_ir_da_x_operand" ""))
-   (set (reg:HI 7) (match_operand:HI 2 "r_im_ir_da_x_operand" ""))
-   (parallel
-    [ 
-     (set (reg:HI 5)
-	  (div:HI (reg:HI 5)
-		  (reg:HI 7)))
-     (set (reg:HI 4)
-	  (mod:HI (reg:HI 5)
-		  (reg:HI 7)))])
-   (set (match_operand:HI 0 "r_ir_da_x_ba_bx_operand" "")
-	(reg:HI 5))
-   (set (match_operand:HI 3 "r_ir_da_x_ba_bx_operand" "") 
-	(reg:HI 4))]
-  ""
-  "")
-
-
-(define_insn ""
-  [(set (reg:HI 5)
-	(div:HI (reg:HI 5)
-		(match_operand:HI 0 "r_im_ir_da_x_operand" "riQR")))
-   (clobber (reg:HI 4))]
-  ""
-  "exts	rr4\;div	rr4,%H0")
-
-(define_expand "divhi3"
-  [(set (reg:HI 5) (match_operand:HI 1 "r_im_ir_da_x_operand" ""))
-   (parallel [(set (reg:HI 5)
-		   (div:HI (reg:HI 5)
-			   (match_operand:HI 2 "r_im_ir_da_x_operand" "")))
-	      (clobber (reg:HI 4))])
-   (set (match_operand:HI 0 "r_ir_da_x_ba_bx_operand" "") (reg:HI 5))]
-  ""
-  "")
-
-;; SI
-
-
-(define_insn ""
-  [(set (reg:SI 6)
-	(div:SI (reg:SI 6)
-		(match_operand:SI 0 "r_im_ir_da_x_operand" "riQR")))
-   (clobber (reg:SI 4))]
-  ""
-  "extsl	rq4\;divl	rq4,%S0")
-
-(define_expand "divsi3"
-  [(set (reg:SI 6) (match_operand:SI 1 "r_im_ir_da_x_operand" ""))
-   (parallel [(set (reg:SI 6)
-		   (div:SI (reg:SI 6)
-			   (match_operand:SI 2 "r_im_ir_da_x_operand" "")))
-	      (clobber (reg:SI 4))])
-   (set (match_operand:SI 0 "r_ir_da_x_ba_bx_operand" "") (reg:SI 6))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (reg:SI 6)
-	(div:SI (reg:SI 6)
-		(reg:SI 8)))
-   (set (reg:SI 4)
-	(mod:SI (reg:SI 6) (reg:SI 8)))]
-  ""
-  "extsl	rq4\;divl	rq4,rr8")
-
-(define_expand "divmodsi4"
-  [(set (reg:SI 6) (match_operand:SI 1 "r_im_ir_da_x_operand" ""))
-   (set (reg:SI 8) (match_operand:SI 2 "r_im_ir_da_x_operand" ""))
-   (parallel [(set (reg:SI 6)
-		   (div:SI (reg:SI 6)
-			   (reg:SI 8)))
-	      (set (reg:SI 4)
-		   (mod:SI (reg:SI 6)
-			   (reg:SI 8)))])
-   (set (match_operand:SI 0 "r_ir_da_x_ba_bx_operand" "")
-	(reg:SI 6))
-   (set (match_operand:SI 3 "r_ir_da_x_ba_bx_operand" "") 
-	(reg:SI 4))
-   ]
-  ""
-  "")
-
-(define_insn "_udivmodsi4"
-  [(set (reg:SI 2)
-	(udiv:SI (reg:SI 2)
-		 (match_operand:SI 0 "immediate15_operand" "n")))
-   (set (reg:SI 0)
-	(umod:SI (reg:SI 2) (match_dup 0)))]
-  ""
-  "subl	rr0,rr0\;divl rq0,%S0")
-
-
-(define_expand "udivmodsi4"
-  [(set (match_dup 5) (match_operand:SI 1 "general_operand" ""))
-   (parallel[(set (match_dup 5)
-		  (udiv:SI (match_dup 5)
-			   (match_operand:SI 2 "general_operand" "")))
-	     (set (match_dup 4)
-		  (umod:SI (match_dup 5) (match_dup 2)))])
-   (set (match_operand:SI 0 "general_operand" "") (match_dup 5))
-   (set (match_operand:SI 3 "general_operand" "") (match_dup 4))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT
-      || ((INTVAL (operands[2]) & 0x8000) != 0x0000))
-    FAIL;
-  operands[4] = gen_rtx (REG, SImode, 0);
-  operands[5] = gen_rtx (REG, SImode, 2);
-}")
-
-
-
-;; ----------------------------------------------------------------------
-;; And
-;; ----------------------------------------------------------------------
-
-
-(define_insn "andhi_power"
-  [(set (match_operand:HI 0 "r_ir_da_x_operand" "=rQR")
-	(and:HI (match_operand:HI 1 "r_ir_da_x_operand" "%0")
-		(match_operand:HI 2 "com_power_two_operand" "P")))]
-  ""
-  "res	%H0,%P2"
-  [(set_attr "cond" "notrashcc")])
-
-(define_insn "andhi3"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(and:HI (match_operand:HI 1 "not_subreg_register_operand" "%0")
-		(match_operand:HI 2 "r_im_ir_da_x_operand" "riQR")))]
-  ""
-  "and	%H0,%H2"
-  [(set_attr "cond" "setcc")])
-
-
-;; ----------------------------------------------------------------------
-;; IOR
-;; ----------------------------------------------------------------------
-
-
-;; To get optimal code here, we should define two special
-;; (set (cc0) (ior ...)) patterns.  Without them, we might "optimize"
-;; "ior; insn-using-flags" into "set; test; insn-using-flags".
-;; Same for and pattenrs above!
-
-(define_insn "orhi_power"
-  [(set (match_operand:HI 0 "r_ir_da_x_operand" "=rQR")
-	(ior:HI (match_operand:HI 1 "r_ir_da_x_operand" "%0")
-		(match_operand:HI 2 "power_two_operand" "O")))]
-  ""
-  "set	%H0,%O2"
-  [(set_attr "cond" "notrashcc")])
-
-(define_insn "iorhi3"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(ior:HI (match_operand:HI 1 "r_operand" "%0")
-		(match_operand:HI 2 "r_im_ir_da_x_operand" "riQR")))]
-  ""
-  "or	%H0,%H2"
-  [(set_attr "cond" "logcc")])
-
-
-
-;; ----------------------------------------------------------------------
-;; Xor
-;; ----------------------------------------------------------------------
-
-
-(define_insn "xorhi3"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(xor:HI (match_operand:HI 1 "r_operand" "%0")
-		(match_operand:HI 2 "r_im_ir_da_x_operand" "riQR")))]
-  ""
-  "xor	%H0,%H2"
-  [(set_attr "cond" "logcc")])
-
-
-;; ----------------------------------------------------------------------
-;; Negate
-;; ----------------------------------------------------------------------
-
-
-(define_insn "neghi2"
-  [(set (match_operand:HI 0 "r_ir_da_x_operand" "=rQR")
-	(neg:HI (match_operand:HI 1 "r_ir_da_x_operand" "0")))]
-  ""
-  "neg	%H0"
-  [(set_attr "cond" "logcc")])
-
-(define_insn "negsi2"
-  [(set (match_operand:SI 0 "r_operand" "=r")
-	(neg:SI (match_operand:SI 1 "r_operand" "0")))]
-  ""
-  "com	%H0\;com	%I0\;addl	%S0,#1"
-  [(set_attr "cond" "logcc")])
-
-;; ----------------------------------------------------------------------
-;; Not
-;; ----------------------------------------------------------------------
-
-(define_insn "one_cmplhi2"
-  [(set (match_operand:HI 0 "r_ir_da_x_operand" "=rQR")
-	(not:HI (match_operand:HI 1 "r_ir_da_x_operand" "0")))]
-  ""
-  "com	%H0"
-  [(set_attr "cond" "logcc")])
-
-
-;; ----------------------------------------------------------------------
-;; Shifts
-;; ----------------------------------------------------------------------
-
-
-;; arithmetic right
-
-;; SI mode
-
-(define_insn ""
-  [(set (match_operand:SI 0 "r_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "r_operand" "0")
-		     (neg:HI (match_operand:HI 2 "r_operand" "r"))))]
-  ""
-  "sdal	%S0,%H2"
-  [(set_attr "cond" "logcc")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "r_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "r_operand" "0")
-		     (match_operand:HI 2 "const_int_operand" "n")))]
-  ""
-  "sral	%S0,%2"
-  [(set_attr "cond" "logcc")])
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "r_operand" "=r,r")
-	(ashiftrt:SI (match_operand:SI 1 "r_operand" "0,0")
-		     (match_operand:HI 2 "r_im_operand" "r,i")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, HImode, negate_rtx (HImode, operands[2]));
-}")
-
-
-;; logical right 
-;; SI mode
-
-
-(define_insn ""
-  [(set (match_operand:SI 0 "r_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "r_operand" "0")
-		     (neg:HI (match_operand:HI 2 "r_operand" "r"))))]
-  ""
-  "sdll	%S0,%H2"
-  [(set_attr "cond" "logcc")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "r_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "r_operand" "0")
-		     (match_operand:HI 2 "immediate_operand" "i")))]
-  ""
-  "srll	%S0,%H2"
-  [(set_attr "cond" "logcc")])
-
-(define_expand "lshrsi3"
-  [(set (match_operand:SI 0 "r_operand" "=r,r")
-	(lshiftrt:SI (match_operand:SI 1 "r_operand" "0,0")
-		   (match_operand:HI 2 "r_im_operand" "r,i")))]
-  ""
-  "{
-    if (GET_CODE (operands[2]) != CONST_INT)
-      operands[2] = gen_rtx (NEG, HImode, negate_rtx (HImode, operands[2]));
-   }")
-
-;; left
-;; SI mode
-
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "r_operand" "=r,r,r,r")
-	(ashift:SI (match_operand:SI 1 "r_operand" "0,0,0,0")
-		   (match_operand:HI 2 "r_im_operand" "M,N,r,i")))]
-  ""
-  "@
-	addl	%S0,%S0 ! ashlsi3
-	addl	%S0,%S0\;addl	%S0,%S0 ! ashlsi3
-	sdal	%S0,%H2 ! ashlsi3
-	slal	%S0,%H2"
-  [(set_attr "cond" "logcc")])
-
-
-
-
-(define_insn "_lshrdi3"
-  [(set (match_operand:DI 0 "r_operand" "=r")
-	(lshiftrt:DI (match_operand:DI 1 "r_operand" "0")
-		     (const_int 1)))]
-  ""
-  "srll	%S0,#1\;rrc	%J0,#1\;rrc	%K0,#1")
-
-(define_expand "lshrdi3"
-  [(set (match_operand:DI 0 "r_operand" "=r")
-	(lshiftrt:DI (match_operand:DI 1 "r_operand" "0")
-		     (match_operand:HI 2 "immediate_operand" "")))]
-
-  ""
-  "
-{
-if (GET_CODE (operands[2]) != CONST_INT
-	|| INTVAL (operands[2]) != 1) FAIL;
-}
-")
-
-
-(define_insn "_ashrdi3"
-  [(set (match_operand:DI 0 "r_operand" "=r")
-	(ashiftrt:DI (match_operand:DI 1 "r_operand" "0")
-		     (const_int 1)))]
-  ""
-  "sral	%S0,#1\;rrc	%J0,#1\;rrc	%K0,#1")
-
-(define_expand "ashrdi3"
-  [(set (match_operand:DI 0 "r_operand" "=r")
-	(ashiftrt:DI (match_operand:DI 1 "r_operand" "0")
-		     (match_operand:HI 2 "immediate_operand" "")))]
-
-  ""
-  "
-{
-if (GET_CODE (operands[2]) != CONST_INT
-	|| INTVAL (operands[2]) != 1) FAIL;
-}
-")
-(define_insn "_ashldi3"
-  [(set (match_operand:DI 0 "r_operand" "=r")
-	(ashift:DI (match_operand:DI 1 "r_operand" "0")
-		   (const_int 1)))]
-  ""
-  "addl	%T0,%T0\;adc	%I0,%I1\;adc	%H0,%H1")
-
-(define_expand "ashldi3"
-  [(set (match_operand:DI 0 "r_operand" "=r")
-	(ashift:DI (match_operand:DI 1 "r_operand" "0")
-		   (match_operand:HI 2 "immediate_operand" "")))]
-
-  ""
-  "
-{
-if (GET_CODE (operands[2]) != CONST_INT
-	|| INTVAL (operands[2]) != 1) FAIL;
-}
-")
-
-
-
-;;
-;;
-;; PSI shifts
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "r_operand" "=r")
-	(ashiftrt:PSI (match_operand:PSI 1 "r_operand" "0")
-		     (neg:HI (match_operand:HI 2 "r_operand" "r"))))]
-  ""
-  "sdal	%S0,%H2"
-  [(set_attr "cond" "logcc")])
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "r_operand" "=r")
-	(lshiftrt:PSI (match_operand:PSI 1 "r_operand" "0")
-		      (match_operand:HI 2 "immediate_operand" "i")))]
-  ""
-  "srll	%S0,%H2"
-  [(set_attr "cond" "logcc")])
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "r_operand" "=r")
-	(ashiftrt:PSI (match_operand:PSI 1 "r_operand" "0")
-		     (match_operand:HI 2 "const_int_operand" "n")))]
-  ""
-  "sral	%S0,%2"
-  [(set_attr "cond" "logcc")])
-
-(define_expand "ashrpsi3"
-  [(set (match_operand:PSI 0 "r_operand" "=r,r")
-	(ashiftrt:PSI (match_operand:PSI 1 "r_operand" "0,0")
-		     (match_operand:HI 2 "r_im_operand" "r,i")))]
-  ""
-  "
-{
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, HImode, negate_rtx (HImode, operands[2]));
-}")
-
-
-;; logical right 
-;; PSI mode
-
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "r_operand" "=r")
-	(lshiftrt:PSI (match_operand:PSI 1 "r_operand" "0")
-		     (neg:HI (match_operand:HI 2 "r_operand" "r"))))]
-  ""
-  "sdll	%S0,%H2"
-  [(set_attr "cond" "logcc")])
-
-(define_expand "lshrpsi3"
-  [(set (match_operand:PSI 0 "r_operand" "=r,r")
-	(lshiftrt:PSI (match_operand:PSI 1 "r_operand" "0,0")
-		   (match_operand:HI 2 "r_im_operand" "r,i")))]
-  ""
-  "{
-    if (GET_CODE (operands[2]) != CONST_INT)
-      operands[2] = gen_rtx (NEG, HImode, negate_rtx (HImode, operands[2]));
-   }")
-
-;; left
-;; PSI mode
-
-(define_insn "ashlpsi3"
-  [(set (match_operand:PSI 0 "r_operand" "=r,r,r,r")
-	(ashift:PSI (match_operand:PSI 1 "r_operand" "0,0,0,0")
-		   (match_operand:HI 2 "r_im_operand" "M,N,r,i")))]
-  ""
-  "@
-	addl	%S0,%S0 ! ashlpsi3
-	addl	%S0,%S0\;addl	%S0,%S0 ! ashlpsi3
-	sdal	%S0,%H2
-	slal	%S0,%H2"
-  [(set_attr "cond" "logcc")])
-
-
-;; HI shifts
-
-;; arithmetic right
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(ashiftrt:HI (match_operand:HI 1 "r_operand" "0")
-		     (match_operand:HI 2 "const_int_operand" "n")))]
-  ""
-  "sra	%H0,%H2"
-  [(set_attr "cond" "logcc")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(ashiftrt:HI (match_operand:HI 1 "r_operand" "0")
-		     (neg:HI (match_operand:HI 2 "r_operand" "r"))))]
-  ""
-  "sda	%H0,%H2"
-  [(set_attr "cond" "logcc")])
-
-(define_expand "ashrhi3"
-  [(set (match_operand:HI 0 "r_operand" "=r,r")
-	(ashiftrt:HI (match_operand:HI 1 "r_operand" "0,0")
-		     (match_operand:HI 2 "r_im_operand" "r,i")))]
-  ""
-  "
-  {
-  if (GET_CODE (operands[2]) != CONST_INT)
-    operands[2] = gen_rtx (NEG, HImode, negate_rtx (HImode, operands[2]));
-  }")
-
-
-;;; logical  right
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(lshiftrt:HI (match_operand:HI 1 "r_operand" "0")
-		     (neg:HI (match_operand:HI 2 "r_operand" "r"))))]
-  ""
-  "sdl	%H0,%H2"
-  [(set_attr "cond" "logcc")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(lshiftrt:HI (match_operand:HI 1 "r_operand" "0")
-		     (match_operand:HI 2 "const_int_operand" "n")))]
-  ""
-  "srl	%H0,%H2"
-  [(set_attr "cond" "logcc")])
-
-(define_expand "lshrhi3"
-  [(set (match_operand:HI 0 "r_operand" "=r,r")
-	(lshiftrt:HI (match_operand:HI 1 "r_operand" "0,0")
-		   (match_operand:HI 2 "r_im_operand" "r,i")))]
-  ""
-  "{
-    if (GET_CODE (operands[2]) != CONST_INT)
-      operands[2] = gen_rtx (NEG, HImode, negate_rtx (HImode, operands[2]));
-   }")
-
-;; left
-
-(define_insn "ashlhi3"
-  [(set (match_operand:HI 0 "r_operand" "=r,r,r,r")
-	(ashift:HI (match_operand:HI 1 "r_operand" "0,0,0,0")
-		   (match_operand:HI 2 "r_im_operand" "M,N,L,r")))]
-  ""
-  "@
-	add	%H0,%H0
-	add	%H0,%H0\;add	%H0,%H0
-	sla	%H0,%H2
-	sda	%H0,%H2"
-  [(set_attr "cond" "logcc")])
-
-;; ----------------------------------------------------------------------
-;; Special cases of shifting
-;; ----------------------------------------------------------------------
-
-; Some of these patterns might look like they would never ever match
-; for any real code.  But they do match.
-
-; I suppose I should use DEFINE_SPLIT here to get optimal code
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_operand" "=&r")
-	(ashift:HI (const_int 1)
-		   (match_operand:HI 1 "r_operand" "r")))]
-  ""
-  "ldk	%H0,#0\;set	%H0,%H1"
-  [(set_attr "cond" "notrashcc")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_operand" "=&r")
-	(rotate:HI (const_int -2)
-		   (match_operand:HI 1 "r_operand" "r")))]
-  ""
-  "ld	%H0,#-1\;res	%H0,%H1"
-  [(set_attr "cond" "notrashcc")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_operand" "=r,&r,&r")
-	(ior:HI (ashift:HI (const_int 1)
-			   (match_operand:HI 2 "r_operand" "r,r,r"))
-		(match_operand:HI 1 "r_im_operand" "0,L,i")))]
-  ""
-  "@
-	set	%H0,%H2 !c
-	ldk	%H0,%1\;set	%H0,%H2 !c
-	ld	%H0,%1\;set	%H0,%H2 !c"
-  [(set_attr "cond" "notrashcc,notrashcc,notrashcc")])
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_operand" "=r,&r,&r")
-	(and:HI (rotate:HI (const_int -2)
-			   (match_operand:HI 2 "r_operand" "r,r,r"))
-		(match_operand:HI 1 "r_im_operand" "0,L,i")))]
-  ""
-  "@
-	res	%H0,%H2
-	ldk	%H0,%1\;res	%H0,%H2
-	ld	%H0,%1\;res	%H0,%H2"
-  [(set_attr "cond" "notrashcc,notrashcc,notrashcc")])
-
-
-;; ----------------------------------------------------------------------
-;; SCOND
-;; ----------------------------------------------------------------------
-
-(define_insn "slt"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(lt:HI (cc0) (const_int 0)))]
-  ""
-  "ldk	%H0,#0\;tcc	lt,%H0"
-  [(set_attr "cond" "notrashcc")
-   (set_attr "type" "invisible")
-   (set_attr "length" "4")])
-
-(define_insn "sne"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(ne:HI (cc0) (const_int 0)))]
-  ""
-  "ldk	%H0,#0\;tcc	ne,%H0"
-  [(set_attr "cond" "notrashcc")
-   (set_attr "type" "invisible")
-   (set_attr "length" "4")])
-
-
-(define_insn "seq"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(eq:HI (cc0) (const_int 0)))]
-  ""
-  "ldk	%H0,#0\;tcc	eq,%H0"
-  [(set_attr "cond" "notrashcc")
-   (set_attr "type" "invisible")
-   (set_attr "length" "4")])
-
-
-(define_insn "sge"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(ge:HI (cc0) (const_int 0)))]
-  ""
-  "ldk	%H0,#0\;tcc	ge,%H0"
-  [(set_attr "cond" "notrashcc")
-   (set_attr "type" "invisible")
-   (set_attr "length" "4")])
-
-(define_insn "sgt"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(gt:HI (cc0) (const_int 0)))]
-  ""
-  "ldk	%H0,#0\;%F0tcc	gt,%H0"
-  [(set_attr "cond" "notrashcc")
-   (set_attr "type" "invisible")
-   (set_attr "length" "4")])
-
-
-(define_insn "sle"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(le:HI (cc0) (const_int 0)))]
-  ""
-  "ldk	%H0,#0\;%F0tcc	le,%H0"
-  [(set_attr "cond" "notrashcc")
-   (set_attr "type" "invisible")
-   (set_attr "length" "4")])
-
-(define_insn "sleu"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(leu:HI (cc0) (const_int 0)))]
-  ""
-  "ldk	%H0,#0\;tcc	ule,%H0"
-  [(set_attr "cond" "notrashcc")
-   (set_attr "type" "invisible")
-   (set_attr "length" "4")])
-
-(define_insn "sltu"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(ltu:HI (cc0) (const_int 0)))]
-  ""
-  "ldk	%H0,#0;\tcc	ult,%H0"
-  [(set_attr "cond" "notrashcc")
-   (set_attr "type" "invisible")
-   (set_attr "length" "4")])
-
-(define_insn "sgeu"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(geu:HI (cc0) (const_int 0)))]
-  ""
-  "ldk	%H0,#0\;tcc	uge,%H0"
-  [(set_attr "cond" "notrashcc")
-   (set_attr "type" "invisible")
-   (set_attr "length" "4")])
-
-(define_insn "sgtu"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(gtu:HI (cc0) (const_int 0)))]
-  ""
-  "ldk	%H0,#0\;tcc	ugt,%H0"
-  [(set_attr "cond" "notrashcc")
-   (set_attr "type" "invisible")
-   (set_attr "length" "4")])
-
-
-;; ----------------------------------------------------------------------
-;; Branches
-;; ----------------------------------------------------------------------
-
-
-(define_expand "ble"
-  [(set (pc)
-	(if_then_else (le (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bleu"
-  [(set (pc)
-	(if_then_else (leu (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bge"
-  [(set (pc)
-	(if_then_else (ge (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgeu"
-  [(set (pc)
-	(if_then_else (geu (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "blt"
-  [(set (pc)
-	(if_then_else (lt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bltu"
-  [(set (pc)
-	(if_then_else (ltu (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgt"
-  [(set (pc)
-	(if_then_else (gt (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bgtu"
-  [(set (pc)
-	(if_then_else (gtu (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "beq"
-  [(set (pc)
-	(if_then_else (eq (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_expand "bne"
-  [(set (pc)
-	(if_then_else (ne (cc0)
-			  (const_int 0))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))]
-  ""
-  "")
-
-(define_insn ""
- [(set (pc)
-   (if_then_else (match_operator 1 "comparison_operator"
-		  [(cc0) (const_int 0)])
-    (label_ref (match_operand 0 "" ""))
-    (pc)))]
- ""
- "*
-{
-  maybe_need_resflg (operands[1]);
-  if (get_attr_length(insn) == 2) 
-    {
-      return \"jr	%D1,%l0\";
-    }
-  else 
-    {
-      return \"jp	%D1,%l0\";
-    }
-}" 
- [(set_attr "type" "branch")
-  (set_attr "cond" "notrashcc")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 1 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))]
-  ""
-  "*
-{
-  maybe_need_resflg (operands[1]);
-
-  if (get_attr_length(insn) == 2) 
-    {
-      return \"jr	%C1,%l0\";
-    }
-  else {
-    return \"jp	%D1,%l0\";
-  }
-}"
-  [(set_attr "type" "branch")
-   (set_attr "cond" "notrashcc")] )
-
-;; Unconditional and other jump instructions
-
-(define_insn "jump"
-  [(set (pc)
-	(label_ref (match_operand 0 "" "")))]
-  ""
-  "*{
-    if (get_attr_length(insn) == 2) 
-      {
-	return \"jr	%l0\";
-      }
-    else {
-      return \"jp	%l0\";
-    }
-  }"
-  [(set_attr "type" "branch")
-   (set_attr "cond" "notrashcc")] )
-
-
-
-;; ----------------------------------------------------------------------
-;; Calls
-;; ----------------------------------------------------------------------
-
-(define_insn "call"
-  [(call (match_operand:QI 0 "ir_da_x_operand" "m")
-	 (match_operand:SI 1 "immediate_operand" "n"))]
-  ""
-  "call	%S0"
-  [(set_attr "cond" "trashcc")])
-
-(define_insn "call_value"
-  [(set (match_operand 0 "" "=r")
-	(call (match_operand:QI 1 "ir_da_x_operand" "m")
-	      (match_operand:QI 2 "immediate_operand" "n")))]
-  ""
-  "call	%H1"
-  [(set_attr "cond" "trashcc")])
-
-
-;; Call subroutine returning any type.
-
-(define_expand "untyped_call"
-  [(parallel [(call (match_operand 0 "" "")
-		    (const_int 0))
-	      (match_operand 1 "" "")
-	      (match_operand 2 "" "")])]
-  ""
-  "
-{
-  int i;
-
-  emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
-
-  for (i = 0; i < XVECLEN (operands[2], 0); i++)
-    {
-      rtx set = XVECEXP (operands[2], 0, i);
-      emit_move_insn (SET_DEST (set), SET_SRC (set));
-    }
-
-  /* The optimizer does not know that the call sets the function value
-     registers we stored in the result block.  We avoid problems by
-     claiming that all hard registers are used and clobbered at this
-     point.  */
-  emit_insn (gen_blockage ());
-
-  DONE;
-}")
-
-
-;; ----------------------------------------------------------------------
-;; Return
-;; ----------------------------------------------------------------------
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (return)
-		      (pc)))]
-  "null_epilogue ()"
-  "*
-{
-  maybe_need_resflg (operands[0]);
-  return \"ret	%D0\";
-}"
-  [(set_attr "type" "return")
-   (set_attr "length" "2")
-   (set_attr "cond" "trashcc")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
-				      [(cc0) (const_int 0)])
-		      (pc)
-		      (return)))]
-  "null_epilogue ()"
-  "*
-{
-  maybe_need_resflg (operands[0]);
-  return \"ret	%C0\";
-}"
-  [(set_attr "type" "return")
-   (set_attr "length" "2")
-   (set_attr "cond" "trashcc")])
-
-(define_insn "return"
-  [(return)]
-  "reload_completed"
-  "* return TARGET_YASM ? \"ret\" : \"ret	t\";"
-  [(set_attr "type" "return")
-   (set_attr "length" "2")
-   (set_attr "cond" "trashcc")])
-
-
-;; ----------------------------------------------------------------------
-;; Misc
-;; ----------------------------------------------------------------------
-
-(define_insn "nop"
-  [(const_int 0)]
-  ""
-  "ld	r0,r0	! nop"
-  [(set_attr "cond" "notrashcc")])
-
-(define_insn "indirect_jump_si"
-  [(set (pc) (match_operand:SI 0 "r_operand" "v"))]
-  ""
-  "jp	@%S0"
-  [(set_attr "cond" "notrashcc")])
-
-(define_insn "indirect_jump_psi"
-  [(set (pc) (match_operand:PSI 0 "r_operand" "v"))]
-  ""
-  "jp	@%S0"
-  [(set_attr "cond" "notrashcc")])
-
-
-(define_insn "indirect_jump_hi"
-  [(set (pc) (match_operand:HI 0 "r_operand" "v"))]
-  ""
-  "jp	@%H0"
-  [(set_attr "cond" "notrashcc")])
-
-
-(define_expand "indirect_jump"
-  [(set (pc) (match_operand 0 "r_operand" ""))]
-	""
-	"")
-	
-	
-(define_insn "tablejump"
-  [(set (pc) (match_operand 0 "r_operand" "v"))
-   (use (label_ref (match_operand 1 "" "")))]
-  ""
-  "jp	%l1(%H0)"
-  [(set_attr "cond" "trashcc")])
-
-(define_insn "tablejump_ext"
-  [(set (pc) 
-	(mem:HI (plus:PSI (sign_extend:PSI (match_operand:HI  0 "r_operand" "v"))
-			  (label_ref (match_operand 1 "" "")))))
-   (use (label_ref (match_dup 1)))]
-  ""
-  "ld	%H0,%l1(%H0)\;jp	%l1(%H0)"
-  [(set_attr "cond" "trashcc")])
-
-
-
-;; ----------------------------------------------------------------------
-;; Machine specifics
-;; ----------------------------------------------------------------------
-
-(define_insn ""
-  [(set (match_operand:HI 0 "r_operand" "=&r")
-	(unspec:HI [(mem:BLK (match_operand:HI 1 "address_operand" "=r"))
-		   (match_operand:QI 2 "r_operand" "u")
-		   (match_operand:HI 3 "immediate_operand" "i")
-		   (match_operand:HI 4 "r_operand" "0")] 0))
-  (set (match_dup 1) (plus:HI (match_dup 1) (not:HI (match_dup 4))))]
-  ""
-  "cpirb	%Q2,@%H1,%H0,ne")
-
-(define_expand "strlenhi"
-  [(set (match_dup 4) (const_int 0))
-   (set (match_dup 6) (match_operand:QI 2 "r_operand" ""))
-   (parallel [(set (match_dup 4)
-		   (unspec:HI [(mem:BLK (match_operand:BLK 1 "r_operand" ""))
-			       (match_dup 6)
-			       (match_operand:HI 3 "immediate_operand" "")
-			       (match_dup 4)] 0))
-	      (set (match_dup 1) (plus:HI (match_dup 1) (not:HI (match_dup 4))))])
-   (set (match_operand:HI 0 "r_operand" "")
-	(not:HI (match_dup 4)))]
-  "0"
-  "{
-   operands[1] = force_reg (HImode, XEXP (operands[1], 0));
-   operands[4] = gen_reg_rtx (HImode);
-   operands[5] = gen_reg_rtx (HImode);
-   operands[6] = gen_rtx(REG, QImode, 0);
-   }")
-
-
-;; ----------------------------------------------------------------------
-;; Peepholes
-;; ----------------------------------------------------------------------
-
-; trn
-; dec Rx,-2
-; mov @Rx,Ry
-; 
-; into 
-;
-; push @Rx,Ry
-
-
-(define_peephole
-  [(set (match_operand:HI 0 "r_operand" "+r")
-	(plus:HI
-	 (match_dup 0)
-	 (const_int -2)))
-  (set (mem:HI  (match_dup 0))
-       (match_operand:HI 1 "r_operand" "r"))]
-  ""
-  "push	@%H0,%H1 !3")
-
-;; ----------------------------------------------------------------------
-;; addpsi 
-;; ----------------------------------------------------------------------
-
-
-(define_expand "prologue"
-  [(const_int 0)]
-  ""
-  "z8k_expand_prologue (); DONE;")
-
-(define_expand "epilogue"
-  [(return)]
-  ""
-  "z8k_expand_epilogue ();")
-
-(define_insn "blockage"
- [(unspec_volatile [(const_int 0)] 0)]
-  ""
-  ""
-  [(set_attr "length" "0")])
-
-(define_insn "pophi"
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(match_operand:HI 1 "pop_operand" ">"))]
-  ""
-  "pop	%H0,@%H1")
-
-(define_insn "popsi"
-  [(set (match_operand:SI 0 "r_operand" "=r")
-	(match_operand:SI 1 "pop_operand" ">"))]
-  ""
-  "popl	%S0,@%S1")
-
-
-;	ld	r9,@rr8
-;	cp	r9,#48875
-; ->
-;       cp      @rr8,#48875
-
-(define_peephole
-  [(set (match_operand:HI 0 "r_operand" "")
-	(match_operand:HI 1 "r_ir_da_x_operand" ""))
-   (set (cc0) (compare (match_dup 0) (match_operand:HI 2 "r_im_ir_da_x_operand" "")))]
-  "0 && dead_or_set_p (insn, operands[0])
-&& ((r_operand(operands[1], HImode) && r_im_ir_da_x_operand(operands[2], HImode))
-   || (r_ir_da_x_operand(operands[1], HImode) &&immediate_operand(operands[2], HImode)))"
-  "cp	%H1,%H2 ! p2 %H0/%H1/%H2"
-  [(set_attr "cond" "setcc")])
-
-
-
-
-
-  
-(define_insn ""
-  [(set (match_operand:PSI 0 "r_operand" "=r")
-       (plus:PSI (match_operand:PSI 1 "symbol_ref" "i")
-		 (match_operand:SI 2 "r_operand" "v")))]
-  ""
-  "lda	%S0,%A1(%I2) !i8")
-
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "r_operand" "=r")
-       (plus:PSI (match_operand:SI 2 "r_operand" "v")
-		  (match_operand:PSI 1 "symbol_ref" "i")))]
-  ""
-  "lda	%S0,%A1(%I2) !i9")
-
-
-
-(define_insn ""
-  [(set (match_operand:PSI 0 "r_operand" "=r")
-       (plus:PSI (match_operand:PSI 2 "r_operand" "v")
-		  (match_operand:PSI 1 "symbol_ref" "i")))]
-  ""
-  "lda	%S0,%A1(%I2) !i10")
-
-
-
-(define_insn "combine4"
-  [(set (match_operand:PSI 0 "r_operand" "=r,r")
-	(ashift:PSI (truncate:PSI (sign_extend:SI (match_operand:HI  1 "r_operand" "0,rQSso")))
-		    (const_int 1)))]
-  ""
-  "@
-	add	%I0,%I0\;xor	%H0,%H0 ! combine 4
-	$ld	%I0,%H1\;add	%I0,%I0\;xor	%H0,%H0 ! combine 4")
-
-
-(define_peephole
-  [(set (match_operand:HI 0 "r_operand" "=r")
-	(plus:HI (match_dup 0) (match_operand:HI 1 "const_int_operand" "n")))
-   (set (match_dup 0) (plus:HI (match_dup 0) (match_operand:HI 2 "const_int_operand" "n")))]
-  ""
-  "*
-{
-  int val = INTVAL(operands[1]) + INTVAL(operands[2]);
-  if (val) 
-    {
-      operands[1] = GEN_INT(val);
-      if (CONST_OK_FOR_LETTER_P(val,'J'))
-	{
-	  return \"inc	%H0,%H1 !p5\";
-	}
-      else if (CONST_OK_FOR_LETTER_P(val,'K'))
-	{
-	  return \"dec	%H0,%N1 !p5\";
-	}
-      else
-	{
-	  return \"add	%H0,%H1 !p5\";
-	}
-    }
-  else return \"! p5\";
-
-}")
-
-
-(define_peephole
-  [(set (match_operand:PSI 0 "r_operand" "=r")
-	(plus:PSI (match_dup 0) (match_operand:PSI 1 "const_int_operand" "i")))
-   (set (match_dup 0) (plus:PSI (match_dup 0) (match_operand:PSI 2 "const_int_operand" "i")))]
-  ""
-  "*
-{
-  int val = INTVAL(operands[1]) + INTVAL(operands[2]);
-  if (val) 
-    {
-      operands[1] = GEN_INT(val);
-      if (CONST_OK_FOR_LETTER_P(val,'J'))
-	{
-	  return \"inc	%I0,%H1 !p5\";
-	}
-      else if (CONST_OK_FOR_LETTER_P(val,'K'))
-	{
-	  return \"dec	%I0,%N1 !p5\";
-	}
-    else
-      {
-	return \"add	%I0,%H1 !p5\";
-     }
-    }
-else return \"! p5\";
-
-}
-")
-
-(define_insn "decrement_and_branch_until_zero"
-  [(set (pc)
-	(if_then_else (ne (plus:HI (match_operand:HI 0 "r_operand" "+!r,!*m")
-				   (const_int -1))
-			  (const_int 0))
-		      (label_ref (match_operand 1 "" ""))
-		      (pc)))
-   (set (match_dup 0)
-	(plus:SI (match_dup 0) (const_int -1)))]
-  "TARGET_DJNZ"
-  "*
-  if (get_attr_length (insn) == 2 && GET_CODE (operands[0]) == REG)
-    return \"djnz	%H0,%l1\";
-  else if (get_attr_length (insn) == 4)
-    return \"dec	%H0,#1\;jr	nz,%l1\";
-  else
-    return \"dec	%H0,#1\;jp	nz,%l1\";"
-  [(set_attr "type" "djnz")
-   (set_attr "cond" "notrashcc")])
-
-(define_insn ""
-  [(set (pc)
-	(if_then_else
-	 (ne (match_operand:HI 0 "r_operand" "+!r,!*m")
-	     (const_int 1))
-	 (label_ref (match_operand 1 "" ""))
-	 (pc)))
-   (set (match_dup 0)
-	(plus:HI (match_dup 0) (const_int -1)))]
-  "TARGET_DJNZ"
-  "*
-  if (get_attr_length (insn) == 2 && GET_CODE(operands[0]) == REG)
-    return \"djnz	%H0,%l1\";
-  else if (get_attr_length (insn) == 4)
-    return \"dec	%H0,#1\;jr	nz,%l1\";
-  else
-    return \"dec	%H0,#1\;jp	nz,%l1\";"
-  [(set_attr "type" "djnz")
-   (set_attr "cond" "notrashcc")
-   (set_attr "length" "2")])
-
-
-;(define_insn "combine7"
-;  [(set (match_operand:HI 0 "register_operand" "=r")
-;	(mem:HI (plus:PSI (sign
-
-(define_insn "combine7"
-  [(set (match_operand:PSI 0 "register_operand" "=r,r")
-	(truncate:PSI (sign_extend:SI (match_operand:HI 1 "register_operand" "0,r"))))]
-  ""
-  "@
-	exts	%S0 ! combine7 %H0, %S1
-	$ld	%I0,%H1\;exts	%S0 ! extendhisi2")
-
-(define_insn "combine8"
- [(set (match_operand:PSI 0 "register_operand" "=r,r")
-       (truncate:PSI (lshiftrt:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "0,r"))
-				  (match_operand:HI 2 "immediate_operand" "i,i"))))]
- ""
- "@
-	srl	%I0,%H2\;xor	%H0,%H0
-	ld	%I0,%H1\;srl	%I0,%H2\;xor	%H0,%H0"
- [(set_attr "cond" "trashcc")])
-
-
-(define_insn "combine9"
-  [(set (match_operand:PSI 0 "register_operand" "=&r")
-	(plus:PSI (truncate:PSI (lshiftrt:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "r"))
-					     (match_operand:HI 2 "immediate_operand" "i")))
-		  (match_operand:PSI 3 "register_operand" "r")))]
-  ""
-  "ld	%I0,%H1\;srl	%I0,%H2\;ld	%H0,%H3\;add	%I0,%I3"
- [(set_attr "cond" "trashcc")])
-
-
-(define_peephole
-  [(set (match_operand:PSI 0 "register_operand" "=r")
-	(truncate:PSI (match_operand:SI 1 "register_operand" "r")))
-   (set (match_operand:QI 2 "register_operand" "=u")
-	(mem:QI (plus:PSI (match_dup 0)
-			  (match_operand:PSI 3 "symbol_ref" ""))))]
- "0 && (REGNO (operands[0]) == REGNO (operands[1]) 
-  && (dead_or_set_p (insn, operands[0])))"
- "ldb	%Q2,%A3(%I1) ! p9")
-
-
-(define_peephole
-  [(set (subreg:HI (match_operand:PSI 0 "register_operand" "=r") 1)
-	(match_operand:HI 1 "register_operand" "r"))
-   (set (subreg:HI (match_dup 0) 0) (const_int 0))
-   (set (match_dup 0) (plus:PSI (match_dup 0) 
-				(match_operand:PSI 2 "general_operand" "g")))]
-  "!reg_mentioned_p (operands[0], operands[1])"
-  "ldl	%S0,%S2\;add	%I0,%H1")
-
-
-(define_insn "adddi3"
-  [(set (match_operand:DI 0 "register_operand" "=&r,&r")
-	(plus:DI (match_operand:DI 1 "register_operand" "%0,0")
-		 (match_operand:DI 2 "r_im_ir_da_x_operand_for_di" "r,iQR")))]
-  ""
-  "@
-	addl	%T0,%T2\;adc	%I0,%I2\;adc	%H0,%H2
-	addl	%T0,%T2\;jr	nc,DIL%^\;addl	%B0,#1\\nDIL%^:	addl	%B0,%B2"
-  [(set_attr "cond" "trashcc")
-   (set_attr "length" "6,8")])
-
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "r_operand" "=&r,&r")
-	(minus:DI (match_operand:DI 1 "r_operand" "0,0")
-		  (match_operand:DI 2 "r_im_ir_da_x_operand_for_di" "r,iQR")))]
-  ""
-  "@
-	subl	%T0,%T2\;sbc	%I0,%I2\;sbc	%H0,%H2
-	subl	%T0,%T2\;jr	nc,DIL%^\;subl	%B0,#1\\nDIL%^:	subl	%B0,%B2"
-  [(set_attr "cond" "trashcc")
-   (set_attr "length" "4,8")])
-
-
-(define_insn "combine10"
-  [(set (match_operand:HI 0 "register_operand" "=u")
-	(ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
-		(ashift:HI (subreg:HI (match_operand:QI 2 "r_ir_da_x_ba_bx_operand" "uQRS") 0)
-			   (const_int 8))))]
-  ""
-  "$ldb	%U0,%Q2 ! c10")
-
-